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* config/tc-cr16.h (GLOBAL_OFFSET_TABLE_NAME): Defined
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
5dd15031 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 LOCKREP_PREFIX. */
63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
67#define LOCKREP_PREFIX 4
68#define REX_PREFIX 5 /* must come last. */
69#define MAX_PREFIXES 6 /* max prefixes per opcode */
70
71/* we define the syntax here (modulo base,index,scale syntax) */
72#define REGISTER_PREFIX '%'
73#define IMMEDIATE_PREFIX '$'
74#define ABSOLUTE_PREFIX '*'
75
76/* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78#define WORD_MNEM_SUFFIX 'w'
79#define BYTE_MNEM_SUFFIX 'b'
80#define SHORT_MNEM_SUFFIX 's'
81#define LONG_MNEM_SUFFIX 'l'
82#define QWORD_MNEM_SUFFIX 'q'
83#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 84#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 85/* Intel Syntax. Use a non-ascii letter since since it never appears
86 in instructions. */
87#define LONG_DOUBLE_MNEM_SUFFIX '\1'
88
89#define END_OF_INSN '\0'
90
91/*
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
96 END.
97 */
98typedef struct
99{
100 const template *start;
101 const template *end;
102}
103templates;
104
105/* 386 operand encoding bytes: see 386 book for details of this. */
106typedef struct
107{
108 unsigned int regmem; /* codes register or memory operand */
109 unsigned int reg; /* codes register operand (or extended opcode) */
110 unsigned int mode; /* how to interpret regmem & reg */
111}
112modrm_byte;
113
114/* x86-64 extension prefix. */
115typedef int rex_byte;
116
117/* The SSE5 instructions have a two bit instruction modifier (OC) that
118 is stored in two separate bytes in the instruction. Pick apart OC
119 into the 2 separate bits for instruction. */
120#define DREX_OC0(x) (((x) & 1) != 0)
121#define DREX_OC1(x) (((x) & 2) != 0)
122
123#define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
124#define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
125
126/* OC mappings */
127#define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
128#define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
129#define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
130#define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
131
132#define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
133#define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
134
135/* Information needed to create the DREX byte in SSE5 instructions. */
136typedef struct
137{
138 unsigned int reg; /* register */
139 unsigned int rex; /* REX flags */
140 unsigned int modrm_reg; /* which arg goes in the modrm.reg field */
141 unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */
142} drex_byte;
143
144/* 386 opcode byte to code indirect addressing. */
145typedef struct
146{
147 unsigned base;
148 unsigned index;
149 unsigned scale;
150}
151sib_byte;
152
6305a203
L		 153/* x86 arch names, types and features */
154typedef struct
155{
156 const char *name; /* arch name */
157 enum processor_type type; /* arch type */
158 i386_cpu_flags flags; /* cpu feature flags */
159}
160arch_entry;
161
e3bb37b5
L		 162static void set_code_flag (int);
163static void set_16bit_gcc_code_flag (int);
164static void set_intel_syntax (int);
1efbbeb4 165static void set_intel_mnemonic (int);
db51cc60 166static void set_allow_index_reg (int);
cb19c032 167static void set_sse_check (int);
e3bb37b5 168static void set_cpu_arch (int);
6482c264 169#ifdef TE_PE
e3bb37b5 170static void pe_directive_secrel (int);
6482c264 171#endif
e3bb37b5
L		 172static void signed_cons (int);
173static char *output_invalid (int c);
a7619375 174static int i386_att_operand (char *);
e3bb37b5
L		 175static int i386_intel_operand (char *, int);
176static const reg_entry *parse_register (char *, char **);
177static char *parse_insn (char *, char *);
178static char *parse_operands (char *, const char *);
179static void swap_operands (void);
4d456e3d 180static void swap_2_operands (int, int);
e3bb37b5
L		 181static void optimize_imm (void);
182static void optimize_disp (void);
183static int match_template (void);
184static int check_string (void);
185static int process_suffix (void);
186static int check_byte_reg (void);
187static int check_long_reg (void);
188static int check_qword_reg (void);
189static int check_word_reg (void);
190static int finalize_imm (void);
85f10a01 191static void process_drex (void);
e3bb37b5
L		 192static int process_operands (void);
193static const seg_entry *build_modrm_byte (void);
194static void output_insn (void);
195static void output_imm (fragS *, offsetT);
196static void output_disp (fragS *, offsetT);
29b0f896 197#ifndef I386COFF
e3bb37b5 198static void s_bss (int);
252b5132 199#endif
17d4e2a2
L		 200#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201static void handle_large_common (int small ATTRIBUTE_UNUSED);
202#endif
252b5132 203
a847613f 204static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 205
c0f3af97
L		 206/* VEX prefix. */
207typedef struct
208{
209 /* VEX prefix is either 2 byte or 3 byte. */
210 unsigned char bytes[3];
211 unsigned int length;
212 /* Destination or source register specifier. */
213 const reg_entry *register_specifier;
214} vex_prefix;
215
252b5132 216/* 'md_assemble ()' gathers together information and puts it into a
47926f60 217 i386_insn. */
252b5132 218
520dc8e8
AM		 219union i386_op
220 {
221 expressionS *disps;
222 expressionS *imms;
223 const reg_entry *regs;
224 };
225
252b5132
RH		 226struct _i386_insn
227 {
47926f60 228 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 229 template tm;
230
7d5e4556
L		 231 /* SUFFIX holds the instruction size suffix for byte, word, dword
232 or qword, if given. */
252b5132
RH		 233 char suffix;
234
47926f60 235 /* OPERANDS gives the number of given operands. */
252b5132
RH		 236 unsigned int operands;
237
238 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
239 of given register, displacement, memory operands and immediate
47926f60 240 operands. */
252b5132
RH		 241 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
242
243 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 244 use OP[i] for the corresponding operand. */
40fb9820 245 i386_operand_type types[MAX_OPERANDS];
252b5132 246
520dc8e8
AM		 247 /* Displacement expression, immediate expression, or register for each
248 operand. */
249 union i386_op op[MAX_OPERANDS];
252b5132 250
3e73aa7c
JH		 251 /* Flags for operands. */
252 unsigned int flags[MAX_OPERANDS];
253#define Operand_PCrel 1
254
252b5132 255 /* Relocation type for operand */
f86103b7 256 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 257
252b5132
RH		 258 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
259 the base index byte below. */
260 const reg_entry *base_reg;
261 const reg_entry *index_reg;
262 unsigned int log2_scale_factor;
263
264 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 265 explicit segment overrides are given. */
ce8a8b2f 266 const seg_entry *seg[2];
252b5132
RH		 267
268 /* PREFIX holds all the given prefix opcodes (usually null).
269 PREFIXES is the number of prefix opcodes. */
270 unsigned int prefixes;
271 unsigned char prefix[MAX_PREFIXES];
272
273 /* RM and SIB are the modrm byte and the sib byte where the
85f10a01
MM		 274 addressing modes of this insn are encoded. DREX is the byte
275 added by the SSE5 instructions. */
252b5132
RH		 276
277 modrm_byte rm;
3e73aa7c 278 rex_byte rex;
252b5132 279 sib_byte sib;
85f10a01 280 drex_byte drex;
c0f3af97 281 vex_prefix vex;
252b5132
RH		 282 };
283
284typedef struct _i386_insn i386_insn;
285
286/* List of chars besides those in app.c:symbol_chars that can start an
287 operand. Used to prevent the scrubber eating vital white-space. */
32137342 288const char extra_symbol_chars[] = "*%-(["
252b5132 289#ifdef LEX_AT
32137342
NC		 290 "@"
291#endif
292#ifdef LEX_QM
293 "?"
252b5132 294#endif
32137342 295 ;
252b5132 296
29b0f896
AM		 297#if (defined (TE_I386AIX) \
298 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 299 && !defined (TE_GNU) \
29b0f896 300 && !defined (TE_LINUX) \
32137342 301 && !defined (TE_NETWARE) \
29b0f896
AM		 302 && !defined (TE_FreeBSD) \
303 && !defined (TE_NetBSD)))
252b5132 304/* This array holds the chars that always start a comment. If the
b3b91714
AM		 305 pre-processor is disabled, these aren't very useful. The option
306 --divide will remove '/' from this list. */
307const char *i386_comment_chars = "#/";
308#define SVR4_COMMENT_CHARS 1
252b5132 309#define PREFIX_SEPARATOR '\\'
252b5132 310
b3b91714
AM		 311#else
312const char *i386_comment_chars = "#";
313#define PREFIX_SEPARATOR '/'
314#endif
315
252b5132
RH		 316/* This array holds the chars that only start a comment at the beginning of
317 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 318 .line and .file directives will appear in the pre-processed output.
319 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 320 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 321 #NO_APP at the beginning of its output.
322 Also note that comments started like this one will always work if
252b5132 323 '/' isn't otherwise defined. */
b3b91714 324const char line_comment_chars[] = "#/";
252b5132 325
63a0b638 326const char line_separator_chars[] = ";";
252b5132 327
ce8a8b2f
AM		 328/* Chars that can be used to separate mant from exp in floating point
329 nums. */
252b5132
RH		 330const char EXP_CHARS[] = "eE";
331
ce8a8b2f
AM		 332/* Chars that mean this number is a floating point constant
333 As in 0f12.456
334 or 0d1.2345e12. */
252b5132
RH		 335const char FLT_CHARS[] = "fFdDxX";
336
ce8a8b2f 337/* Tables for lexical analysis. */
252b5132
RH		 338static char mnemonic_chars[256];
339static char register_chars[256];
340static char operand_chars[256];
341static char identifier_chars[256];
342static char digit_chars[256];
343
ce8a8b2f 344/* Lexical macros. */
252b5132
RH		 345#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
346#define is_operand_char(x) (operand_chars[(unsigned char) x])
347#define is_register_char(x) (register_chars[(unsigned char) x])
348#define is_space_char(x) ((x) == ' ')
349#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
350#define is_digit_char(x) (digit_chars[(unsigned char) x])
351
0234cb7c 352/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 353static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
354
355/* md_assemble() always leaves the strings it's passed unaltered. To
356 effect this we maintain a stack of saved characters that we've smashed
357 with '\0's (indicating end of strings for various sub-fields of the
47926f60 358 assembler instruction). */
252b5132 359static char save_stack[32];
ce8a8b2f 360static char *save_stack_p;
252b5132
RH		 361#define END_STRING_AND_SAVE(s) \
362 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
363#define RESTORE_END_STRING(s) \
364 do { *(s) = *--save_stack_p; } while (0)
365
47926f60 366/* The instruction we're assembling. */
252b5132
RH		 367static i386_insn i;
368
369/* Possible templates for current insn. */
370static const templates *current_templates;
371
31b2323c
L		 372/* Per instruction expressionS buffers: max displacements & immediates. */
373static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
374static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 375
47926f60
KH		 376/* Current operand we are working on. */
377static int this_operand;
252b5132 378
3e73aa7c
JH		 379/* We support four different modes. FLAG_CODE variable is used to distinguish
380 these. */
381
382enum flag_code {
383 CODE_32BIT,
384 CODE_16BIT,
385 CODE_64BIT };
386
387static enum flag_code flag_code;
4fa24527 388static unsigned int object_64bit;
3e73aa7c
JH		 389static int use_rela_relocations = 0;
390
391/* The names used to print error messages. */
b77a7acd 392static const char *flag_code_names[] =
3e73aa7c
JH		 393 {
394 "32",
395 "16",
396 "64"
397 };
252b5132 398
47926f60
KH		 399/* 1 for intel syntax,
400 0 if att syntax. */
401static int intel_syntax = 0;
252b5132 402
1efbbeb4
L		 403/* 1 for intel mnemonic,
404 0 if att mnemonic. */
405static int intel_mnemonic = !SYSV386_COMPAT;
406
5209009a 407/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 408static int old_gcc = OLDGCC_COMPAT;
409
a60de03c
JB		 410/* 1 if pseudo registers are permitted. */
411static int allow_pseudo_reg = 0;
412
47926f60
KH		 413/* 1 if register prefix % not required. */
414static int allow_naked_reg = 0;
252b5132 415
ba104c83 416/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 417static int allow_index_reg = 0;
418
daf50ae7
L		 419static enum
420 {
421 sse_check_none = 0,
422 sse_check_warning,
423 sse_check_error
424 }
425sse_check;
426
2ca3ace5
L		 427/* Register prefix used for error message. */
428static const char *register_prefix = "%";
429
47926f60
KH		 430/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
431 leave, push, and pop instructions so that gcc has the same stack
432 frame as in 32 bit mode. */
433static char stackop_size = '\0';
eecb386c 434
12b55ccc
L		 435/* Non-zero to optimize code alignment. */
436int optimize_align_code = 1;
437
47926f60
KH		 438/* Non-zero to quieten some warnings. */
439static int quiet_warnings = 0;
a38cf1db 440
47926f60
KH		 441/* CPU name. */
442static const char *cpu_arch_name = NULL;
6305a203 443static char *cpu_sub_arch_name = NULL;
a38cf1db 444
47926f60 445/* CPU feature flags. */
40fb9820
L		 446static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
447
ccc9c027
L		 448/* If we have selected a cpu we are generating instructions for. */
449static int cpu_arch_tune_set = 0;
450
9103f4f4 451/* Cpu we are generating instructions for. */
fbf3f584 452enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 453
454/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 455static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 456
ccc9c027 457/* CPU instruction set architecture used. */
fbf3f584 458enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 459
9103f4f4 460/* CPU feature flags of instruction set architecture used. */
fbf3f584 461i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 462
fddf5b5b
AM		 463/* If set, conditional jumps are not automatically promoted to handle
464 larger than a byte offset. */
465static unsigned int no_cond_jump_promotion = 0;
466
c0f3af97
L		 467/* Encode SSE instructions with VEX prefix. */
468static unsigned int sse2avx;
469
29b0f896 470/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 471static symbolS *GOT_symbol;
29b0f896 472
a4447b93
RH		 473/* The dwarf2 return column, adjusted for 32 or 64 bit. */
474unsigned int x86_dwarf2_return_column;
475
476/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
477int x86_cie_data_alignment;
478
252b5132 479/* Interface to relax_segment.
fddf5b5b
AM		 480 There are 3 major relax states for 386 jump insns because the
481 different types of jumps add different sizes to frags when we're
482 figuring out what sort of jump to choose to reach a given label. */
252b5132 483
47926f60 484/* Types. */
93c2a809
AM		 485#define UNCOND_JUMP 0
486#define COND_JUMP 1
487#define COND_JUMP86 2
fddf5b5b 488
47926f60 489/* Sizes. */
252b5132
RH		 490#define CODE16 1
491#define SMALL 0
29b0f896 492#define SMALL16 (SMALL | CODE16)
252b5132 493#define BIG 2
29b0f896 494#define BIG16 (BIG | CODE16)
252b5132
RH		 495
496#ifndef INLINE
497#ifdef __GNUC__
498#define INLINE __inline__
499#else
500#define INLINE
501#endif
502#endif
503
fddf5b5b
AM		 504#define ENCODE_RELAX_STATE(type, size) \
505 ((relax_substateT) (((type) << 2) | (size)))
506#define TYPE_FROM_RELAX_STATE(s) \
507 ((s) >> 2)
508#define DISP_SIZE_FROM_RELAX_STATE(s) \
509 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 510
511/* This table is used by relax_frag to promote short jumps to long
512 ones where necessary. SMALL (short) jumps may be promoted to BIG
513 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
514 don't allow a short jump in a 32 bit code segment to be promoted to
515 a 16 bit offset jump because it's slower (requires data size
516 prefix), and doesn't work, unless the destination is in the bottom
517 64k of the code segment (The top 16 bits of eip are zeroed). */
518
519const relax_typeS md_relax_table[] =
520{
24eab124
AM		 521 /* The fields are:
522 1) most positive reach of this state,
523 2) most negative reach of this state,
93c2a809 524 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 525 4) which index into the table to try if we can't fit into this one. */
252b5132 526
fddf5b5b 527 /* UNCOND_JUMP states. */
93c2a809
AM		 528 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
529 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
530 /* dword jmp adds 4 bytes to frag:
531 0 extra opcode bytes, 4 displacement bytes. */
252b5132 532 {0, 0, 4, 0},
93c2a809
AM		 533 /* word jmp adds 2 byte2 to frag:
534 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 535 {0, 0, 2, 0},
536
93c2a809
AM		 537 /* COND_JUMP states. */
538 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
539 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
540 /* dword conditionals adds 5 bytes to frag:
541 1 extra opcode byte, 4 displacement bytes. */
542 {0, 0, 5, 0},
fddf5b5b 543 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 544 1 extra opcode byte, 2 displacement bytes. */
545 {0, 0, 3, 0},
546
547 /* COND_JUMP86 states. */
548 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
549 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
550 /* dword conditionals adds 5 bytes to frag:
551 1 extra opcode byte, 4 displacement bytes. */
552 {0, 0, 5, 0},
553 /* word conditionals add 4 bytes to frag:
554 1 displacement byte and a 3 byte long branch insn. */
555 {0, 0, 4, 0}
252b5132
RH		 556};
557
9103f4f4
L		 558static const arch_entry cpu_arch[] =
559{
6305a203
L		 560 { "generic32", PROCESSOR_GENERIC32,
561 CPU_GENERIC32_FLAGS },
562 { "generic64", PROCESSOR_GENERIC64,
563 CPU_GENERIC64_FLAGS },
564 { "i8086", PROCESSOR_UNKNOWN,
565 CPU_NONE_FLAGS },
566 { "i186", PROCESSOR_UNKNOWN,
567 CPU_I186_FLAGS },
568 { "i286", PROCESSOR_UNKNOWN,
569 CPU_I286_FLAGS },
570 { "i386", PROCESSOR_I386,
571 CPU_I386_FLAGS },
572 { "i486", PROCESSOR_I486,
573 CPU_I486_FLAGS },
574 { "i586", PROCESSOR_PENTIUM,
575 CPU_I586_FLAGS },
576 { "i686", PROCESSOR_PENTIUMPRO,
577 CPU_I686_FLAGS },
578 { "pentium", PROCESSOR_PENTIUM,
579 CPU_I586_FLAGS },
580 { "pentiumpro", PROCESSOR_PENTIUMPRO,
581 CPU_I686_FLAGS },
582 { "pentiumii", PROCESSOR_PENTIUMPRO,
583 CPU_P2_FLAGS },
584 { "pentiumiii",PROCESSOR_PENTIUMPRO,
585 CPU_P3_FLAGS },
586 { "pentium4", PROCESSOR_PENTIUM4,
587 CPU_P4_FLAGS },
588 { "prescott", PROCESSOR_NOCONA,
589 CPU_CORE_FLAGS },
590 { "nocona", PROCESSOR_NOCONA,
591 CPU_NOCONA_FLAGS },
592 { "yonah", PROCESSOR_CORE,
593 CPU_CORE_FLAGS },
594 { "core", PROCESSOR_CORE,
595 CPU_CORE_FLAGS },
596 { "merom", PROCESSOR_CORE2,
597 CPU_CORE2_FLAGS },
598 { "core2", PROCESSOR_CORE2,
599 CPU_CORE2_FLAGS },
600 { "k6", PROCESSOR_K6,
601 CPU_K6_FLAGS },
602 { "k6_2", PROCESSOR_K6,
603 CPU_K6_2_FLAGS },
604 { "athlon", PROCESSOR_ATHLON,
605 CPU_ATHLON_FLAGS },
606 { "sledgehammer", PROCESSOR_K8,
607 CPU_K8_FLAGS },
608 { "opteron", PROCESSOR_K8,
609 CPU_K8_FLAGS },
610 { "k8", PROCESSOR_K8,
611 CPU_K8_FLAGS },
612 { "amdfam10", PROCESSOR_AMDFAM10,
613 CPU_AMDFAM10_FLAGS },
614 { ".mmx", PROCESSOR_UNKNOWN,
615 CPU_MMX_FLAGS },
616 { ".sse", PROCESSOR_UNKNOWN,
617 CPU_SSE_FLAGS },
618 { ".sse2", PROCESSOR_UNKNOWN,
619 CPU_SSE2_FLAGS },
620 { ".sse3", PROCESSOR_UNKNOWN,
621 CPU_SSE3_FLAGS },
622 { ".ssse3", PROCESSOR_UNKNOWN,
623 CPU_SSSE3_FLAGS },
624 { ".sse4.1", PROCESSOR_UNKNOWN,
625 CPU_SSE4_1_FLAGS },
626 { ".sse4.2", PROCESSOR_UNKNOWN,
627 CPU_SSE4_2_FLAGS },
628 { ".sse4", PROCESSOR_UNKNOWN,
629 CPU_SSE4_2_FLAGS },
c0f3af97
L		 630 { ".avx", PROCESSOR_UNKNOWN,
631 CPU_AVX_FLAGS },
6305a203
L		 632 { ".vmx", PROCESSOR_UNKNOWN,
633 CPU_VMX_FLAGS },
634 { ".smx", PROCESSOR_UNKNOWN,
635 CPU_SMX_FLAGS },
f03fe4c1
L		 636 { ".xsave", PROCESSOR_UNKNOWN,
637 CPU_XSAVE_FLAGS },
c0f3af97
L		 638 { ".aes", PROCESSOR_UNKNOWN,
639 CPU_AES_FLAGS },
594ab6a3
L		 640 { ".pclmul", PROCESSOR_UNKNOWN,
641 CPU_PCLMUL_FLAGS },
c0f3af97 642 { ".clmul", PROCESSOR_UNKNOWN,
594ab6a3 643 CPU_PCLMUL_FLAGS },
c0f3af97
L		 644 { ".fma", PROCESSOR_UNKNOWN,
645 CPU_FMA_FLAGS },
f1f8f695
L		 646 { ".movbe", PROCESSOR_UNKNOWN,
647 CPU_MOVBE_FLAGS },
648 { ".ept", PROCESSOR_UNKNOWN,
649 CPU_EPT_FLAGS },
6305a203
L		 650 { ".3dnow", PROCESSOR_UNKNOWN,
651 CPU_3DNOW_FLAGS },
652 { ".3dnowa", PROCESSOR_UNKNOWN,
653 CPU_3DNOWA_FLAGS },
654 { ".padlock", PROCESSOR_UNKNOWN,
655 CPU_PADLOCK_FLAGS },
656 { ".pacifica", PROCESSOR_UNKNOWN,
657 CPU_SVME_FLAGS },
658 { ".svme", PROCESSOR_UNKNOWN,
659 CPU_SVME_FLAGS },
660 { ".sse4a", PROCESSOR_UNKNOWN,
661 CPU_SSE4A_FLAGS },
662 { ".abm", PROCESSOR_UNKNOWN,
663 CPU_ABM_FLAGS },
664 { ".sse5", PROCESSOR_UNKNOWN,
665 CPU_SSE5_FLAGS },
e413e4e9
AM		 666};
667
704209c0 668#ifdef I386COFF
a6c24e68
NC		 669/* Like s_lcomm_internal in gas/read.c but the alignment string
670 is allowed to be optional. */
671
672static symbolS *
673pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
674{
675 addressT align = 0;
676
677 SKIP_WHITESPACE ();
678
679 if (needs_align
680 && *input_line_pointer == ',')
681 {
682 align = parse_align (needs_align - 1);
683
684 if (align == (addressT) -1)
685 return NULL;
686 }
687 else
688 {
689 if (size >= 8)
690 align = 3;
691 else if (size >= 4)
692 align = 2;
693 else if (size >= 2)
694 align = 1;
695 else
696 align = 0;
697 }
698
699 bss_alloc (symbolP, size, align);
700 return symbolP;
701}
702
704209c0 703static void
a6c24e68
NC		 704pe_lcomm (int needs_align)
705{
706 s_comm_internal (needs_align * 2, pe_lcomm_internal);
707}
704209c0 708#endif
a6c24e68 709
29b0f896
AM		 710const pseudo_typeS md_pseudo_table[] =
711{
712#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
713 {"align", s_align_bytes, 0},
714#else
715 {"align", s_align_ptwo, 0},
716#endif
717 {"arch", set_cpu_arch, 0},
718#ifndef I386COFF
719 {"bss", s_bss, 0},
a6c24e68
NC		 720#else
721 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 722#endif
723 {"ffloat", float_cons, 'f'},
724 {"dfloat", float_cons, 'd'},
725 {"tfloat", float_cons, 'x'},
726 {"value", cons, 2},
d182319b 727 {"slong", signed_cons, 4},
29b0f896
AM		 728 {"noopt", s_ignore, 0},
729 {"optim", s_ignore, 0},
730 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
731 {"code16", set_code_flag, CODE_16BIT},
732 {"code32", set_code_flag, CODE_32BIT},
733 {"code64", set_code_flag, CODE_64BIT},
734 {"intel_syntax", set_intel_syntax, 1},
735 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 736 {"intel_mnemonic", set_intel_mnemonic, 1},
737 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 738 {"allow_index_reg", set_allow_index_reg, 1},
739 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 740 {"sse_check", set_sse_check, 0},
3b22753a
L		 741#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
742 {"largecomm", handle_large_common, 0},
07a53e5c 743#else
e3bb37b5 744 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 745 {"loc", dwarf2_directive_loc, 0},
746 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 747#endif
6482c264
NC		 748#ifdef TE_PE
749 {"secrel32", pe_directive_secrel, 0},
750#endif
29b0f896
AM		 751 {0, 0, 0}
752};
753
754/* For interface with expression (). */
755extern char *input_line_pointer;
756
757/* Hash table for instruction mnemonic lookup. */
758static struct hash_control *op_hash;
759
760/* Hash table for register lookup. */
761static struct hash_control *reg_hash;
762\f
252b5132 763void
e3bb37b5 764i386_align_code (fragS *fragP, int count)
252b5132 765{
ce8a8b2f
AM		 766 /* Various efficient no-op patterns for aligning code labels.
767 Note: Don't try to assemble the instructions in the comments.
768 0L and 0w are not legal. */
252b5132
RH		 769 static const char f32_1[] =
770 {0x90}; /* nop */
771 static const char f32_2[] =
ccc9c027 772 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 773 static const char f32_3[] =
774 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
775 static const char f32_4[] =
776 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
777 static const char f32_5[] =
778 {0x90, /* nop */
779 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
780 static const char f32_6[] =
781 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
782 static const char f32_7[] =
783 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
784 static const char f32_8[] =
785 {0x90, /* nop */
786 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
787 static const char f32_9[] =
788 {0x89,0xf6, /* movl %esi,%esi */
789 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
790 static const char f32_10[] =
791 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
792 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
793 static const char f32_11[] =
794 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
795 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
796 static const char f32_12[] =
797 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
798 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
799 static const char f32_13[] =
800 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
801 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
802 static const char f32_14[] =
803 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
804 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 805 static const char f16_3[] =
806 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 807 static const char f16_4[] =
808 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
809 static const char f16_5[] =
810 {0x90, /* nop */
811 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
812 static const char f16_6[] =
813 {0x89,0xf6, /* mov %si,%si */
814 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
815 static const char f16_7[] =
816 {0x8d,0x74,0x00, /* lea 0(%si),%si */
817 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
818 static const char f16_8[] =
819 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
820 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 821 static const char jump_31[] =
822 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
823 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
824 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
825 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 826 static const char *const f32_patt[] = {
827 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 828 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 829 };
830 static const char *const f16_patt[] = {
76bc74dc 831 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 832 };
ccc9c027
L		 833 /* nopl (%[re]ax) */
834 static const char alt_3[] =
835 {0x0f,0x1f,0x00};
836 /* nopl 0(%[re]ax) */
837 static const char alt_4[] =
838 {0x0f,0x1f,0x40,0x00};
839 /* nopl 0(%[re]ax,%[re]ax,1) */
840 static const char alt_5[] =
841 {0x0f,0x1f,0x44,0x00,0x00};
842 /* nopw 0(%[re]ax,%[re]ax,1) */
843 static const char alt_6[] =
844 {0x66,0x0f,0x1f,0x44,0x00,0x00};
845 /* nopl 0L(%[re]ax) */
846 static const char alt_7[] =
847 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
848 /* nopl 0L(%[re]ax,%[re]ax,1) */
849 static const char alt_8[] =
850 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
851 /* nopw 0L(%[re]ax,%[re]ax,1) */
852 static const char alt_9[] =
853 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
854 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
855 static const char alt_10[] =
856 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
857 /* data16
858 nopw %cs:0L(%[re]ax,%[re]ax,1) */
859 static const char alt_long_11[] =
860 {0x66,
861 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
862 /* data16
863 data16
864 nopw %cs:0L(%[re]ax,%[re]ax,1) */
865 static const char alt_long_12[] =
866 {0x66,
867 0x66,
868 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
869 /* data16
870 data16
871 data16
872 nopw %cs:0L(%[re]ax,%[re]ax,1) */
873 static const char alt_long_13[] =
874 {0x66,
875 0x66,
876 0x66,
877 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
878 /* data16
879 data16
880 data16
881 data16
882 nopw %cs:0L(%[re]ax,%[re]ax,1) */
883 static const char alt_long_14[] =
884 {0x66,
885 0x66,
886 0x66,
887 0x66,
888 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
889 /* data16
890 data16
891 data16
892 data16
893 data16
894 nopw %cs:0L(%[re]ax,%[re]ax,1) */
895 static const char alt_long_15[] =
896 {0x66,
897 0x66,
898 0x66,
899 0x66,
900 0x66,
901 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
902 /* nopl 0(%[re]ax,%[re]ax,1)
903 nopw 0(%[re]ax,%[re]ax,1) */
904 static const char alt_short_11[] =
905 {0x0f,0x1f,0x44,0x00,0x00,
906 0x66,0x0f,0x1f,0x44,0x00,0x00};
907 /* nopw 0(%[re]ax,%[re]ax,1)
908 nopw 0(%[re]ax,%[re]ax,1) */
909 static const char alt_short_12[] =
910 {0x66,0x0f,0x1f,0x44,0x00,0x00,
911 0x66,0x0f,0x1f,0x44,0x00,0x00};
912 /* nopw 0(%[re]ax,%[re]ax,1)
913 nopl 0L(%[re]ax) */
914 static const char alt_short_13[] =
915 {0x66,0x0f,0x1f,0x44,0x00,0x00,
916 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
917 /* nopl 0L(%[re]ax)
918 nopl 0L(%[re]ax) */
919 static const char alt_short_14[] =
920 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
921 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
922 /* nopl 0L(%[re]ax)
923 nopl 0L(%[re]ax,%[re]ax,1) */
924 static const char alt_short_15[] =
925 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
926 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
927 static const char *const alt_short_patt[] = {
928 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
929 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
930 alt_short_14, alt_short_15
931 };
932 static const char *const alt_long_patt[] = {
933 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
934 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
935 alt_long_14, alt_long_15
936 };
252b5132 937
76bc74dc
L		 938 /* Only align for at least a positive non-zero boundary. */
939 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 940 return;
3e73aa7c 941
ccc9c027
L		 942 /* We need to decide which NOP sequence to use for 32bit and
943 64bit. When -mtune= is used:
4eed87de 944
76bc74dc
L		 945 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
946 PROCESSOR_GENERIC32, f32_patt will be used.
947 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
948 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
949 alt_long_patt will be used.
950 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
951 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 952
76bc74dc
L		 953 When -mtune= isn't used, alt_long_patt will be used if
954 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
955 be used.
ccc9c027
L		 956
957 When -march= or .arch is used, we can't use anything beyond
958 cpu_arch_isa_flags. */
959
960 if (flag_code == CODE_16BIT)
961 {
ccc9c027 962 if (count > 8)
33fef721 963 {
76bc74dc
L		 964 memcpy (fragP->fr_literal + fragP->fr_fix,
965 jump_31, count);
966 /* Adjust jump offset. */
967 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 968 }
76bc74dc
L		 969 else
970 memcpy (fragP->fr_literal + fragP->fr_fix,
971 f16_patt[count - 1], count);
252b5132 972 }
33fef721 973 else
ccc9c027
L		 974 {
975 const char *const *patt = NULL;
976
fbf3f584 977 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 978 {
979 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
980 switch (cpu_arch_tune)
981 {
982 case PROCESSOR_UNKNOWN:
983 /* We use cpu_arch_isa_flags to check if we SHOULD
984 optimize for Cpu686. */
fbf3f584 985 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
76bc74dc 986 patt = alt_long_patt;
ccc9c027
L		 987 else
988 patt = f32_patt;
989 break;
ccc9c027
L		 990 case PROCESSOR_PENTIUMPRO:
991 case PROCESSOR_PENTIUM4:
992 case PROCESSOR_NOCONA:
ef05d495 993 case PROCESSOR_CORE:
76bc74dc
L		 994 case PROCESSOR_CORE2:
995 case PROCESSOR_GENERIC64:
996 patt = alt_long_patt;
997 break;
ccc9c027
L		 998 case PROCESSOR_K6:
999 case PROCESSOR_ATHLON:
1000 case PROCESSOR_K8:
4eed87de 1001 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1002 patt = alt_short_patt;
1003 break;
76bc74dc 1004 case PROCESSOR_I386:
ccc9c027
L		 1005 case PROCESSOR_I486:
1006 case PROCESSOR_PENTIUM:
1007 case PROCESSOR_GENERIC32:
1008 patt = f32_patt;
1009 break;
4eed87de 1010 }
ccc9c027
L		 1011 }
1012 else
1013 {
fbf3f584 1014 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1015 {
1016 case PROCESSOR_UNKNOWN:
e6a14101 1017 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1018 PROCESSOR_UNKNOWN. */
1019 abort ();
1020 break;
1021
76bc74dc 1022 case PROCESSOR_I386:
ccc9c027
L		 1023 case PROCESSOR_I486:
1024 case PROCESSOR_PENTIUM:
ccc9c027
L		 1025 case PROCESSOR_K6:
1026 case PROCESSOR_ATHLON:
1027 case PROCESSOR_K8:
4eed87de 1028 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1029 case PROCESSOR_GENERIC32:
1030 /* We use cpu_arch_isa_flags to check if we CAN optimize
1031 for Cpu686. */
fbf3f584 1032 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1033 patt = alt_short_patt;
1034 else
1035 patt = f32_patt;
1036 break;
76bc74dc
L		 1037 case PROCESSOR_PENTIUMPRO:
1038 case PROCESSOR_PENTIUM4:
1039 case PROCESSOR_NOCONA:
1040 case PROCESSOR_CORE:
ef05d495 1041 case PROCESSOR_CORE2:
fbf3f584 1042 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1043 patt = alt_long_patt;
1044 else
1045 patt = f32_patt;
1046 break;
1047 case PROCESSOR_GENERIC64:
76bc74dc 1048 patt = alt_long_patt;
ccc9c027 1049 break;
4eed87de 1050 }
ccc9c027
L		 1051 }
1052
76bc74dc
L		 1053 if (patt == f32_patt)
1054 {
1055 /* If the padding is less than 15 bytes, we use the normal
1056 ones. Otherwise, we use a jump instruction and adjust
1057 its offset. */
1058 if (count < 15)
1059 memcpy (fragP->fr_literal + fragP->fr_fix,
1060 patt[count - 1], count);
1061 else
1062 {
1063 memcpy (fragP->fr_literal + fragP->fr_fix,
1064 jump_31, count);
1065 /* Adjust jump offset. */
1066 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1067 }
1068 }
1069 else
1070 {
1071 /* Maximum length of an instruction is 15 byte. If the
1072 padding is greater than 15 bytes and we don't use jump,
1073 we have to break it into smaller pieces. */
1074 int padding = count;
1075 while (padding > 15)
1076 {
1077 padding -= 15;
1078 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1079 patt [14], 15);
1080 }
1081
1082 if (padding)
1083 memcpy (fragP->fr_literal + fragP->fr_fix,
1084 patt [padding - 1], padding);
1085 }
ccc9c027 1086 }
33fef721 1087 fragP->fr_var = count;
252b5132
RH		 1088}
1089
c6fb90c8 1090static INLINE int
0dfbf9d7 1091operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1092{
0dfbf9d7 1093 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1094 {
1095 case 3:
0dfbf9d7 1096 if (x->array[2])
c6fb90c8
L		 1097 return 0;
1098 case 2:
0dfbf9d7 1099 if (x->array[1])
c6fb90c8
L		 1100 return 0;
1101 case 1:
0dfbf9d7 1102 return !x->array[0];
c6fb90c8
L		 1103 default:
1104 abort ();
1105 }
40fb9820
L		 1106}
1107
c6fb90c8 1108static INLINE void
0dfbf9d7 1109operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1110{
0dfbf9d7 1111 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1112 {
1113 case 3:
0dfbf9d7 1114 x->array[2] = v;
c6fb90c8 1115 case 2:
0dfbf9d7 1116 x->array[1] = v;
c6fb90c8 1117 case 1:
0dfbf9d7 1118 x->array[0] = v;
c6fb90c8
L		 1119 break;
1120 default:
1121 abort ();
1122 }
1123}
40fb9820 1124
c6fb90c8 1125static INLINE int
0dfbf9d7
L		 1126operand_type_equal (const union i386_operand_type *x,
1127 const union i386_operand_type *y)
c6fb90c8 1128{
0dfbf9d7 1129 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1130 {
1131 case 3:
0dfbf9d7 1132 if (x->array[2] != y->array[2])
c6fb90c8
L		 1133 return 0;
1134 case 2:
0dfbf9d7 1135 if (x->array[1] != y->array[1])
c6fb90c8
L		 1136 return 0;
1137 case 1:
0dfbf9d7 1138 return x->array[0] == y->array[0];
c6fb90c8
L		 1139 break;
1140 default:
1141 abort ();
1142 }
1143}
40fb9820 1144
0dfbf9d7
L		 1145static INLINE int
1146cpu_flags_all_zero (const union i386_cpu_flags *x)
1147{
1148 switch (ARRAY_SIZE(x->array))
1149 {
1150 case 3:
1151 if (x->array[2])
1152 return 0;
1153 case 2:
1154 if (x->array[1])
1155 return 0;
1156 case 1:
1157 return !x->array[0];
1158 default:
1159 abort ();
1160 }
1161}
1162
1163static INLINE void
1164cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1165{
1166 switch (ARRAY_SIZE(x->array))
1167 {
1168 case 3:
1169 x->array[2] = v;
1170 case 2:
1171 x->array[1] = v;
1172 case 1:
1173 x->array[0] = v;
1174 break;
1175 default:
1176 abort ();
1177 }
1178}
1179
1180static INLINE int
1181cpu_flags_equal (const union i386_cpu_flags *x,
1182 const union i386_cpu_flags *y)
1183{
1184 switch (ARRAY_SIZE(x->array))
1185 {
1186 case 3:
1187 if (x->array[2] != y->array[2])
1188 return 0;
1189 case 2:
1190 if (x->array[1] != y->array[1])
1191 return 0;
1192 case 1:
1193 return x->array[0] == y->array[0];
1194 break;
1195 default:
1196 abort ();
1197 }
1198}
c6fb90c8
L		 1199
1200static INLINE int
1201cpu_flags_check_cpu64 (i386_cpu_flags f)
1202{
1203 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1204 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1205}
1206
c6fb90c8
L		 1207static INLINE i386_cpu_flags
1208cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1209{
c6fb90c8
L		 1210 switch (ARRAY_SIZE (x.array))
1211 {
1212 case 3:
1213 x.array [2] &= y.array [2];
1214 case 2:
1215 x.array [1] &= y.array [1];
1216 case 1:
1217 x.array [0] &= y.array [0];
1218 break;
1219 default:
1220 abort ();
1221 }
1222 return x;
1223}
40fb9820 1224
c6fb90c8
L		 1225static INLINE i386_cpu_flags
1226cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1227{
c6fb90c8 1228 switch (ARRAY_SIZE (x.array))
40fb9820 1229 {
c6fb90c8
L		 1230 case 3:
1231 x.array [2] |= y.array [2];
1232 case 2:
1233 x.array [1] |= y.array [1];
1234 case 1:
1235 x.array [0] |= y.array [0];
40fb9820
L		 1236 break;
1237 default:
1238 abort ();
1239 }
40fb9820
L		 1240 return x;
1241}
1242
c0f3af97
L		 1243#define CPU_FLAGS_ARCH_MATCH 0x1
1244#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2
L		 1245#define CPU_FLAGS_AES_MATCH 0x4
1246#define CPU_FLAGS_AVX_MATCH 0x8
c0f3af97 1247
a5ff0eb2
L		 1248#define CPU_FLAGS_32BIT_MATCH \
1249 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1250#define CPU_FLAGS_PERFECT_MATCH \
1251 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1252
1253/* Return CPU flags match bits. */
3629bb00 1254
40fb9820 1255static int
c0f3af97 1256cpu_flags_match (const template *t)
40fb9820 1257{
c0f3af97
L		 1258 i386_cpu_flags x = t->cpu_flags;
1259 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1260
1261 x.bitfield.cpu64 = 0;
1262 x.bitfield.cpuno64 = 0;
1263
0dfbf9d7 1264 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1265 {
1266 /* This instruction is available on all archs. */
1267 match |= CPU_FLAGS_32BIT_MATCH;
1268 }
3629bb00
L		 1269 else
1270 {
c0f3af97 1271 /* This instruction is available only on some archs. */
3629bb00
L		 1272 i386_cpu_flags cpu = cpu_arch_flags;
1273
1274 cpu.bitfield.cpu64 = 0;
1275 cpu.bitfield.cpuno64 = 0;
1276 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1277 if (!cpu_flags_all_zero (&cpu))
1278 {
a5ff0eb2
L		 1279 if (x.bitfield.cpuavx)
1280 {
1281 /* We only need to check AES/SSE2AVX with AVX. */
1282 if (cpu.bitfield.cpuavx)
1283 {
1284 /* Check SSE2AVX. */
1285 if (!t->opcode_modifier.sse2avx|| sse2avx)
1286 {
1287 match |= (CPU_FLAGS_ARCH_MATCH
1288 | CPU_FLAGS_AVX_MATCH);
1289 /* Check AES. */
1290 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1291 match |= CPU_FLAGS_AES_MATCH;
1292 }
1293 }
1294 else
1295 match |= CPU_FLAGS_ARCH_MATCH;
1296 }
1297 else
c0f3af97
L		 1298 match |= CPU_FLAGS_32BIT_MATCH;
1299 }
3629bb00 1300 }
c0f3af97 1301 return match;
40fb9820
L		 1302}
1303
c6fb90c8
L		 1304static INLINE i386_operand_type
1305operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1306{
c6fb90c8
L		 1307 switch (ARRAY_SIZE (x.array))
1308 {
1309 case 3:
1310 x.array [2] &= y.array [2];
1311 case 2:
1312 x.array [1] &= y.array [1];
1313 case 1:
1314 x.array [0] &= y.array [0];
1315 break;
1316 default:
1317 abort ();
1318 }
1319 return x;
40fb9820
L		 1320}
1321
c6fb90c8
L		 1322static INLINE i386_operand_type
1323operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1324{
c6fb90c8 1325 switch (ARRAY_SIZE (x.array))
40fb9820 1326 {
c6fb90c8
L		 1327 case 3:
1328 x.array [2] |= y.array [2];
1329 case 2:
1330 x.array [1] |= y.array [1];
1331 case 1:
1332 x.array [0] |= y.array [0];
40fb9820
L		 1333 break;
1334 default:
1335 abort ();
1336 }
c6fb90c8
L		 1337 return x;
1338}
40fb9820 1339
c6fb90c8
L		 1340static INLINE i386_operand_type
1341operand_type_xor (i386_operand_type x, i386_operand_type y)
1342{
1343 switch (ARRAY_SIZE (x.array))
1344 {
1345 case 3:
1346 x.array [2] ^= y.array [2];
1347 case 2:
1348 x.array [1] ^= y.array [1];
1349 case 1:
1350 x.array [0] ^= y.array [0];
1351 break;
1352 default:
1353 abort ();
1354 }
40fb9820
L		 1355 return x;
1356}
1357
1358static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1359static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1360static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1361static const i386_operand_type inoutportreg
1362 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1363static const i386_operand_type reg16_inoutportreg
1364 = OPERAND_TYPE_REG16_INOUTPORTREG;
1365static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1366static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1367static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1368static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1369static const i386_operand_type anydisp
1370 = OPERAND_TYPE_ANYDISP;
40fb9820 1371static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1372static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1373static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1374static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1375static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1376static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1377static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1378static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1379static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1380static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1381static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
c0f3af97 1382static const i386_operand_type vex_imm4 = OPERAND_TYPE_VEX_IMM4;
40fb9820
L		 1383
1384enum operand_type
1385{
1386 reg,
40fb9820
L		 1387 imm,
1388 disp,
1389 anymem
1390};
1391
c6fb90c8 1392static INLINE int
40fb9820
L		 1393operand_type_check (i386_operand_type t, enum operand_type c)
1394{
1395 switch (c)
1396 {
1397 case reg:
1398 return (t.bitfield.reg8
1399 || t.bitfield.reg16
1400 || t.bitfield.reg32
1401 || t.bitfield.reg64);
1402
40fb9820
L		 1403 case imm:
1404 return (t.bitfield.imm8
1405 || t.bitfield.imm8s
1406 || t.bitfield.imm16
1407 || t.bitfield.imm32
1408 || t.bitfield.imm32s
1409 || t.bitfield.imm64);
1410
1411 case disp:
1412 return (t.bitfield.disp8
1413 || t.bitfield.disp16
1414 || t.bitfield.disp32
1415 || t.bitfield.disp32s
1416 || t.bitfield.disp64);
1417
1418 case anymem:
1419 return (t.bitfield.disp8
1420 || t.bitfield.disp16
1421 || t.bitfield.disp32
1422 || t.bitfield.disp32s
1423 || t.bitfield.disp64
1424 || t.bitfield.baseindex);
1425
1426 default:
1427 abort ();
1428 }
2cfe26b6
AM		 1429
1430 return 0;
40fb9820
L		 1431}
1432
5c07affc
L		 1433/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1434 operand J for instruction template T. */
1435
1436static INLINE int
1437match_reg_size (const template *t, unsigned int j)
1438{
1439 return !((i.types[j].bitfield.byte
1440 && !t->operand_types[j].bitfield.byte)
1441 || (i.types[j].bitfield.word
1442 && !t->operand_types[j].bitfield.word)
1443 || (i.types[j].bitfield.dword
1444 && !t->operand_types[j].bitfield.dword)
1445 || (i.types[j].bitfield.qword
1446 && !t->operand_types[j].bitfield.qword));
1447}
1448
1449/* Return 1 if there is no conflict in any size on operand J for
1450 instruction template T. */
1451
1452static INLINE int
1453match_mem_size (const template *t, unsigned int j)
1454{
1455 return (match_reg_size (t, j)
1456 && !((i.types[j].bitfield.unspecified
1457 && !t->operand_types[j].bitfield.unspecified)
1458 || (i.types[j].bitfield.fword
1459 && !t->operand_types[j].bitfield.fword)
1460 || (i.types[j].bitfield.tbyte
1461 && !t->operand_types[j].bitfield.tbyte)
1462 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1463 && !t->operand_types[j].bitfield.xmmword)
1464 || (i.types[j].bitfield.ymmword
1465 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1466}
1467
1468/* Return 1 if there is no size conflict on any operands for
1469 instruction template T. */
1470
1471static INLINE int
1472operand_size_match (const template *t)
1473{
1474 unsigned int j;
1475 int match = 1;
1476
1477 /* Don't check jump instructions. */
1478 if (t->opcode_modifier.jump
1479 || t->opcode_modifier.jumpbyte
1480 || t->opcode_modifier.jumpdword
1481 || t->opcode_modifier.jumpintersegment)
1482 return match;
1483
1484 /* Check memory and accumulator operand size. */
1485 for (j = 0; j < i.operands; j++)
1486 {
1487 if (t->operand_types[j].bitfield.anysize)
1488 continue;
1489
1490 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1491 {
1492 match = 0;
1493 break;
1494 }
1495
1496 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1497 {
1498 match = 0;
1499 break;
1500 }
1501 }
1502
1503 if (match
1504 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1505 return match;
1506
1507 /* Check reverse. */
1508 assert (i.operands == 2);
1509
1510 match = 1;
1511 for (j = 0; j < 2; j++)
1512 {
1513 if (t->operand_types[j].bitfield.acc
1514 && !match_reg_size (t, j ? 0 : 1))
1515 {
1516 match = 0;
1517 break;
1518 }
1519
1520 if (i.types[j].bitfield.mem
1521 && !match_mem_size (t, j ? 0 : 1))
1522 {
1523 match = 0;
1524 break;
1525 }
1526 }
1527
1528 return match;
1529}
1530
c6fb90c8 1531static INLINE int
40fb9820
L		 1532operand_type_match (i386_operand_type overlap,
1533 i386_operand_type given)
1534{
1535 i386_operand_type temp = overlap;
1536
1537 temp.bitfield.jumpabsolute = 0;
7d5e4556 1538 temp.bitfield.unspecified = 0;
5c07affc
L		 1539 temp.bitfield.byte = 0;
1540 temp.bitfield.word = 0;
1541 temp.bitfield.dword = 0;
1542 temp.bitfield.fword = 0;
1543 temp.bitfield.qword = 0;
1544 temp.bitfield.tbyte = 0;
1545 temp.bitfield.xmmword = 0;
c0f3af97 1546 temp.bitfield.ymmword = 0;
0dfbf9d7 1547 if (operand_type_all_zero (&temp))
40fb9820
L		 1548 return 0;
1549
1550 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1551 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1552}
1553
7d5e4556 1554/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1555 unless the expected operand type register overlap is null.
1556 Note that Acc in a template matches every size of reg. */
1557
c6fb90c8 1558static INLINE int
40fb9820
L		 1559operand_type_register_match (i386_operand_type m0,
1560 i386_operand_type g0,
1561 i386_operand_type t0,
1562 i386_operand_type m1,
1563 i386_operand_type g1,
1564 i386_operand_type t1)
1565{
1566 if (!operand_type_check (g0, reg))
1567 return 1;
1568
1569 if (!operand_type_check (g1, reg))
1570 return 1;
1571
1572 if (g0.bitfield.reg8 == g1.bitfield.reg8
1573 && g0.bitfield.reg16 == g1.bitfield.reg16
1574 && g0.bitfield.reg32 == g1.bitfield.reg32
1575 && g0.bitfield.reg64 == g1.bitfield.reg64)
1576 return 1;
1577
1578 if (m0.bitfield.acc)
1579 {
1580 t0.bitfield.reg8 = 1;
1581 t0.bitfield.reg16 = 1;
1582 t0.bitfield.reg32 = 1;
1583 t0.bitfield.reg64 = 1;
1584 }
1585
1586 if (m1.bitfield.acc)
1587 {
1588 t1.bitfield.reg8 = 1;
1589 t1.bitfield.reg16 = 1;
1590 t1.bitfield.reg32 = 1;
1591 t1.bitfield.reg64 = 1;
1592 }
1593
1594 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1595 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1596 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1597 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1598}
1599
252b5132 1600static INLINE unsigned int
40fb9820 1601mode_from_disp_size (i386_operand_type t)
252b5132 1602{
40fb9820
L		 1603 if (t.bitfield.disp8)
1604 return 1;
1605 else if (t.bitfield.disp16
1606 || t.bitfield.disp32
1607 || t.bitfield.disp32s)
1608 return 2;
1609 else
1610 return 0;
252b5132
RH		 1611}
1612
1613static INLINE int
e3bb37b5 1614fits_in_signed_byte (offsetT num)
252b5132
RH		 1615{
1616 return (num >= -128) && (num <= 127);
47926f60 1617}
252b5132
RH		 1618
1619static INLINE int
e3bb37b5 1620fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1621{
1622 return (num & 0xff) == num;
47926f60 1623}
252b5132
RH		 1624
1625static INLINE int
e3bb37b5 1626fits_in_unsigned_word (offsetT num)
252b5132
RH		 1627{
1628 return (num & 0xffff) == num;
47926f60 1629}
252b5132
RH		 1630
1631static INLINE int
e3bb37b5 1632fits_in_signed_word (offsetT num)
252b5132
RH		 1633{
1634 return (-32768 <= num) && (num <= 32767);
47926f60 1635}
2a962e6d 1636
3e73aa7c 1637static INLINE int
e3bb37b5 1638fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1639{
1640#ifndef BFD64
1641 return 1;
1642#else
1643 return (!(((offsetT) -1 << 31) & num)
1644 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1645#endif
1646} /* fits_in_signed_long() */
2a962e6d 1647
3e73aa7c 1648static INLINE int
e3bb37b5 1649fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1650{
1651#ifndef BFD64
1652 return 1;
1653#else
1654 return (num & (((offsetT) 2 << 31) - 1)) == num;
1655#endif
1656} /* fits_in_unsigned_long() */
252b5132 1657
c0f3af97
L		 1658static INLINE int
1659fits_in_imm4 (offsetT num)
1660{
1661 return (num & 0xf) == num;
1662}
1663
40fb9820 1664static i386_operand_type
e3bb37b5 1665smallest_imm_type (offsetT num)
252b5132 1666{
40fb9820
L		 1667 i386_operand_type t;
1668
0dfbf9d7 1669 operand_type_set (&t, 0);
40fb9820
L		 1670 t.bitfield.imm64 = 1;
1671
1672 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1673 {
1674 /* This code is disabled on the 486 because all the Imm1 forms
1675 in the opcode table are slower on the i486. They're the
1676 versions with the implicitly specified single-position
1677 displacement, which has another syntax if you really want to
1678 use that form. */
40fb9820
L		 1679 t.bitfield.imm1 = 1;
1680 t.bitfield.imm8 = 1;
1681 t.bitfield.imm8s = 1;
1682 t.bitfield.imm16 = 1;
1683 t.bitfield.imm32 = 1;
1684 t.bitfield.imm32s = 1;
1685 }
1686 else if (fits_in_signed_byte (num))
1687 {
1688 t.bitfield.imm8 = 1;
1689 t.bitfield.imm8s = 1;
1690 t.bitfield.imm16 = 1;
1691 t.bitfield.imm32 = 1;
1692 t.bitfield.imm32s = 1;
1693 }
1694 else if (fits_in_unsigned_byte (num))
1695 {
1696 t.bitfield.imm8 = 1;
1697 t.bitfield.imm16 = 1;
1698 t.bitfield.imm32 = 1;
1699 t.bitfield.imm32s = 1;
1700 }
1701 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1702 {
1703 t.bitfield.imm16 = 1;
1704 t.bitfield.imm32 = 1;
1705 t.bitfield.imm32s = 1;
1706 }
1707 else if (fits_in_signed_long (num))
1708 {
1709 t.bitfield.imm32 = 1;
1710 t.bitfield.imm32s = 1;
1711 }
1712 else if (fits_in_unsigned_long (num))
1713 t.bitfield.imm32 = 1;
1714
1715 return t;
47926f60 1716}
252b5132 1717
847f7ad4 1718static offsetT
e3bb37b5 1719offset_in_range (offsetT val, int size)
847f7ad4 1720{
508866be 1721 addressT mask;
ba2adb93 1722
847f7ad4
AM		 1723 switch (size)
1724 {
508866be
L		 1725 case 1: mask = ((addressT) 1 << 8) - 1; break;
1726 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1727 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1728#ifdef BFD64
1729 case 8: mask = ((addressT) 2 << 63) - 1; break;
1730#endif
47926f60 1731 default: abort ();
847f7ad4
AM		 1732 }
1733
ba2adb93 1734 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1735 if (!use_rela_relocations)
1736 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1737 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1738
47926f60 1739 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1740 {
1741 char buf1[40], buf2[40];
1742
1743 sprint_value (buf1, val);
1744 sprint_value (buf2, val & mask);
1745 as_warn (_("%s shortened to %s"), buf1, buf2);
1746 }
1747 return val & mask;
1748}
1749
252b5132
RH		 1750/* Returns 0 if attempting to add a prefix where one from the same
1751 class already exists, 1 if non rep/repne added, 2 if rep/repne
1752 added. */
1753static int
e3bb37b5 1754add_prefix (unsigned int prefix)
252b5132
RH		 1755{
1756 int ret = 1;
b1905489 1757 unsigned int q;
252b5132 1758
29b0f896
AM		 1759 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1760 && flag_code == CODE_64BIT)
b1905489 1761 {
161a04f6
L		 1762 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1763 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1764 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1765 ret = 0;
1766 q = REX_PREFIX;
1767 }
3e73aa7c 1768 else
b1905489
JB		 1769 {
1770 switch (prefix)
1771 {
1772 default:
1773 abort ();
1774
1775 case CS_PREFIX_OPCODE:
1776 case DS_PREFIX_OPCODE:
1777 case ES_PREFIX_OPCODE:
1778 case FS_PREFIX_OPCODE:
1779 case GS_PREFIX_OPCODE:
1780 case SS_PREFIX_OPCODE:
1781 q = SEG_PREFIX;
1782 break;
1783
1784 case REPNE_PREFIX_OPCODE:
1785 case REPE_PREFIX_OPCODE:
1786 ret = 2;
1787 /* fall thru */
1788 case LOCK_PREFIX_OPCODE:
1789 q = LOCKREP_PREFIX;
1790 break;
1791
1792 case FWAIT_OPCODE:
1793 q = WAIT_PREFIX;
1794 break;
1795
1796 case ADDR_PREFIX_OPCODE:
1797 q = ADDR_PREFIX;
1798 break;
1799
1800 case DATA_PREFIX_OPCODE:
1801 q = DATA_PREFIX;
1802 break;
1803 }
1804 if (i.prefix[q] != 0)
1805 ret = 0;
1806 }
252b5132 1807
b1905489 1808 if (ret)
252b5132 1809 {
b1905489
JB		 1810 if (!i.prefix[q])
1811 ++i.prefixes;
1812 i.prefix[q] |= prefix;
252b5132 1813 }
b1905489
JB		 1814 else
1815 as_bad (_("same type of prefix used twice"));
252b5132 1816
252b5132
RH		 1817 return ret;
1818}
1819
1820static void
e3bb37b5 1821set_code_flag (int value)
eecb386c 1822{
3e73aa7c 1823 flag_code = value;
40fb9820
L		 1824 if (flag_code == CODE_64BIT)
1825 {
1826 cpu_arch_flags.bitfield.cpu64 = 1;
1827 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1828 }
1829 else
1830 {
1831 cpu_arch_flags.bitfield.cpu64 = 0;
1832 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1833 }
1834 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1835 {
1836 as_bad (_("64bit mode not supported on this CPU."));
1837 }
40fb9820 1838 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1839 {
1840 as_bad (_("32bit mode not supported on this CPU."));
1841 }
eecb386c
AM		 1842 stackop_size = '\0';
1843}
1844
1845static void
e3bb37b5 1846set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1847{
3e73aa7c 1848 flag_code = new_code_flag;
40fb9820
L		 1849 if (flag_code != CODE_16BIT)
1850 abort ();
1851 cpu_arch_flags.bitfield.cpu64 = 0;
1852 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1853 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1854}
1855
1856static void
e3bb37b5 1857set_intel_syntax (int syntax_flag)
252b5132
RH		 1858{
1859 /* Find out if register prefixing is specified. */
1860 int ask_naked_reg = 0;
1861
1862 SKIP_WHITESPACE ();
29b0f896 1863 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1864 {
1865 char *string = input_line_pointer;
1866 int e = get_symbol_end ();
1867
47926f60 1868 if (strcmp (string, "prefix") == 0)
252b5132 1869 ask_naked_reg = 1;
47926f60 1870 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1871 ask_naked_reg = -1;
1872 else
d0b47220 1873 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1874 *input_line_pointer = e;
1875 }
1876 demand_empty_rest_of_line ();
c3332e24 1877
252b5132
RH		 1878 intel_syntax = syntax_flag;
1879
1880 if (ask_naked_reg == 0)
f86103b7
AM		 1881 allow_naked_reg = (intel_syntax
1882 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1883 else
1884 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1885
e4a3b5a4 1886 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1887 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1888 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1889}
1890
1efbbeb4
L		 1891static void
1892set_intel_mnemonic (int mnemonic_flag)
1893{
e1d4d893 1894 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1895}
1896
db51cc60
L		 1897static void
1898set_allow_index_reg (int flag)
1899{
1900 allow_index_reg = flag;
1901}
1902
cb19c032
L		 1903static void
1904set_sse_check (int dummy ATTRIBUTE_UNUSED)
1905{
1906 SKIP_WHITESPACE ();
1907
1908 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1909 {
1910 char *string = input_line_pointer;
1911 int e = get_symbol_end ();
1912
1913 if (strcmp (string, "none") == 0)
1914 sse_check = sse_check_none;
1915 else if (strcmp (string, "warning") == 0)
1916 sse_check = sse_check_warning;
1917 else if (strcmp (string, "error") == 0)
1918 sse_check = sse_check_error;
1919 else
1920 as_bad (_("bad argument to sse_check directive."));
1921 *input_line_pointer = e;
1922 }
1923 else
1924 as_bad (_("missing argument for sse_check directive"));
1925
1926 demand_empty_rest_of_line ();
1927}
1928
e413e4e9 1929static void
e3bb37b5 1930set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1931{
47926f60 1932 SKIP_WHITESPACE ();
e413e4e9 1933
29b0f896 1934 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1935 {
1936 char *string = input_line_pointer;
1937 int e = get_symbol_end ();
9103f4f4 1938 unsigned int i;
40fb9820 1939 i386_cpu_flags flags;
e413e4e9 1940
9103f4f4 1941 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1942 {
1943 if (strcmp (string, cpu_arch[i].name) == 0)
1944 {
5c6af06e
JB		 1945 if (*string != '.')
1946 {
1947 cpu_arch_name = cpu_arch[i].name;
1948 cpu_sub_arch_name = NULL;
40fb9820
L		 1949 cpu_arch_flags = cpu_arch[i].flags;
1950 if (flag_code == CODE_64BIT)
1951 {
1952 cpu_arch_flags.bitfield.cpu64 = 1;
1953 cpu_arch_flags.bitfield.cpuno64 = 0;
1954 }
1955 else
1956 {
1957 cpu_arch_flags.bitfield.cpu64 = 0;
1958 cpu_arch_flags.bitfield.cpuno64 = 1;
1959 }
ccc9c027 1960 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1961 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1962 if (!cpu_arch_tune_set)
1963 {
1964 cpu_arch_tune = cpu_arch_isa;
1965 cpu_arch_tune_flags = cpu_arch_isa_flags;
1966 }
5c6af06e
JB		 1967 break;
1968 }
40fb9820 1969
c6fb90c8
L		 1970 flags = cpu_flags_or (cpu_arch_flags,
1971 cpu_arch[i].flags);
0dfbf9d7 1972 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 1973 {
6305a203
L		 1974 if (cpu_sub_arch_name)
1975 {
1976 char *name = cpu_sub_arch_name;
1977 cpu_sub_arch_name = concat (name,
1978 cpu_arch[i].name,
1bf57e9f 1979 (const char *) NULL);
6305a203
L		 1980 free (name);
1981 }
1982 else
1983 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
40fb9820 1984 cpu_arch_flags = flags;
5c6af06e
JB		 1985 }
1986 *input_line_pointer = e;
1987 demand_empty_rest_of_line ();
1988 return;
e413e4e9
AM		 1989 }
1990 }
9103f4f4 1991 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1992 as_bad (_("no such architecture: `%s'"), string);
1993
1994 *input_line_pointer = e;
1995 }
1996 else
1997 as_bad (_("missing cpu architecture"));
1998
fddf5b5b
AM		 1999 no_cond_jump_promotion = 0;
2000 if (*input_line_pointer == ','
29b0f896 2001 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2002 {
2003 char *string = ++input_line_pointer;
2004 int e = get_symbol_end ();
2005
2006 if (strcmp (string, "nojumps") == 0)
2007 no_cond_jump_promotion = 1;
2008 else if (strcmp (string, "jumps") == 0)
2009 ;
2010 else
2011 as_bad (_("no such architecture modifier: `%s'"), string);
2012
2013 *input_line_pointer = e;
2014 }
2015
e413e4e9
AM		 2016 demand_empty_rest_of_line ();
2017}
2018
b9d79e03
JH		 2019unsigned long
2020i386_mach ()
2021{
2022 if (!strcmp (default_arch, "x86_64"))
2023 return bfd_mach_x86_64;
2024 else if (!strcmp (default_arch, "i386"))
2025 return bfd_mach_i386_i386;
2026 else
2027 as_fatal (_("Unknown architecture"));
2028}
b9d79e03 2029\f
252b5132
RH		 2030void
2031md_begin ()
2032{
2033 const char *hash_err;
2034
47926f60 2035 /* Initialize op_hash hash table. */
252b5132
RH		 2036 op_hash = hash_new ();
2037
2038 {
29b0f896
AM		 2039 const template *optab;
2040 templates *core_optab;
252b5132 2041
47926f60
KH		 2042 /* Setup for loop. */
2043 optab = i386_optab;
252b5132
RH		 2044 core_optab = (templates *) xmalloc (sizeof (templates));
2045 core_optab->start = optab;
2046
2047 while (1)
2048 {
2049 ++optab;
2050 if (optab->name == NULL
2051 || strcmp (optab->name, (optab - 1)->name) != 0)
2052 {
2053 /* different name --> ship out current template list;
47926f60 2054 add to hash table; & begin anew. */
252b5132
RH		 2055 core_optab->end = optab;
2056 hash_err = hash_insert (op_hash,
2057 (optab - 1)->name,
5a49b8ac 2058 (void *) core_optab);
252b5132
RH		 2059 if (hash_err)
2060 {
252b5132
RH		 2061 as_fatal (_("Internal Error: Can't hash %s: %s"),
2062 (optab - 1)->name,
2063 hash_err);
2064 }
2065 if (optab->name == NULL)
2066 break;
2067 core_optab = (templates *) xmalloc (sizeof (templates));
2068 core_optab->start = optab;
2069 }
2070 }
2071 }
2072
47926f60 2073 /* Initialize reg_hash hash table. */
252b5132
RH		 2074 reg_hash = hash_new ();
2075 {
29b0f896 2076 const reg_entry *regtab;
c3fe08fa 2077 unsigned int regtab_size = i386_regtab_size;
252b5132 2078
c3fe08fa 2079 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2080 {
5a49b8ac 2081 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2082 if (hash_err)
3e73aa7c
JH		 2083 as_fatal (_("Internal Error: Can't hash %s: %s"),
2084 regtab->reg_name,
2085 hash_err);
252b5132
RH		 2086 }
2087 }
2088
47926f60 2089 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2090 {
29b0f896
AM		 2091 int c;
2092 char *p;
252b5132
RH		 2093
2094 for (c = 0; c < 256; c++)
2095 {
3882b010 2096 if (ISDIGIT (c))
252b5132
RH		 2097 {
2098 digit_chars[c] = c;
2099 mnemonic_chars[c] = c;
2100 register_chars[c] = c;
2101 operand_chars[c] = c;
2102 }
3882b010 2103 else if (ISLOWER (c))
252b5132
RH		 2104 {
2105 mnemonic_chars[c] = c;
2106 register_chars[c] = c;
2107 operand_chars[c] = c;
2108 }
3882b010 2109 else if (ISUPPER (c))
252b5132 2110 {
3882b010 2111 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2112 register_chars[c] = mnemonic_chars[c];
2113 operand_chars[c] = c;
2114 }
2115
3882b010 2116 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2117 identifier_chars[c] = c;
2118 else if (c >= 128)
2119 {
2120 identifier_chars[c] = c;
2121 operand_chars[c] = c;
2122 }
2123 }
2124
2125#ifdef LEX_AT
2126 identifier_chars['@'] = '@';
32137342
NC		 2127#endif
2128#ifdef LEX_QM
2129 identifier_chars['?'] = '?';
2130 operand_chars['?'] = '?';
252b5132 2131#endif
252b5132 2132 digit_chars['-'] = '-';
c0f3af97 2133 mnemonic_chars['_'] = '_';
791fe849 2134 mnemonic_chars['-'] = '-';
0003779b 2135 mnemonic_chars['.'] = '.';
252b5132
RH		 2136 identifier_chars['_'] = '_';
2137 identifier_chars['.'] = '.';
2138
2139 for (p = operand_special_chars; *p != '\0'; p++)
2140 operand_chars[(unsigned char) *p] = *p;
2141 }
2142
2143#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2144 if (IS_ELF)
252b5132
RH		 2145 {
2146 record_alignment (text_section, 2);
2147 record_alignment (data_section, 2);
2148 record_alignment (bss_section, 2);
2149 }
2150#endif
a4447b93
RH		 2151
2152 if (flag_code == CODE_64BIT)
2153 {
2154 x86_dwarf2_return_column = 16;
2155 x86_cie_data_alignment = -8;
2156 }
2157 else
2158 {
2159 x86_dwarf2_return_column = 8;
2160 x86_cie_data_alignment = -4;
2161 }
252b5132
RH		 2162}
2163
2164void
e3bb37b5 2165i386_print_statistics (FILE *file)
252b5132
RH		 2166{
2167 hash_print_statistics (file, "i386 opcode", op_hash);
2168 hash_print_statistics (file, "i386 register", reg_hash);
2169}
2170\f
252b5132
RH		 2171#ifdef DEBUG386
2172
ce8a8b2f 2173/* Debugging routines for md_assemble. */
e3bb37b5 2174static void pte (template *);
40fb9820 2175static void pt (i386_operand_type);
e3bb37b5
L		 2176static void pe (expressionS *);
2177static void ps (symbolS *);
252b5132
RH		 2178
2179static void
e3bb37b5 2180pi (char *line, i386_insn *x)
252b5132 2181{
09f131f2 2182 unsigned int i;
252b5132
RH		 2183
2184 fprintf (stdout, "%s: template ", line);
2185 pte (&x->tm);
09f131f2
JH		 2186 fprintf (stdout, " address: base %s index %s scale %x\n",
2187 x->base_reg ? x->base_reg->reg_name : "none",
2188 x->index_reg ? x->index_reg->reg_name : "none",
2189 x->log2_scale_factor);
2190 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2191 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2192 fprintf (stdout, " sib: base %x index %x scale %x\n",
2193 x->sib.base, x->sib.index, x->sib.scale);
2194 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2195 (x->rex & REX_W) != 0,
2196 (x->rex & REX_R) != 0,
2197 (x->rex & REX_X) != 0,
2198 (x->rex & REX_B) != 0);
85f10a01
MM		 2199 fprintf (stdout, " drex: reg %d rex 0x%x\n",
2200 x->drex.reg, x->drex.rex);
252b5132
RH		 2201 for (i = 0; i < x->operands; i++)
2202 {
2203 fprintf (stdout, " #%d: ", i + 1);
2204 pt (x->types[i]);
2205 fprintf (stdout, "\n");
40fb9820
L		 2206 if (x->types[i].bitfield.reg8
2207 || x->types[i].bitfield.reg16
2208 || x->types[i].bitfield.reg32
2209 || x->types[i].bitfield.reg64
2210 || x->types[i].bitfield.regmmx
2211 || x->types[i].bitfield.regxmm
c0f3af97 2212 || x->types[i].bitfield.regymm
40fb9820
L		 2213 || x->types[i].bitfield.sreg2
2214 || x->types[i].bitfield.sreg3
2215 || x->types[i].bitfield.control
2216 || x->types[i].bitfield.debug
2217 || x->types[i].bitfield.test)
520dc8e8 2218 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 2219 if (operand_type_check (x->types[i], imm))
520dc8e8 2220 pe (x->op[i].imms);
40fb9820 2221 if (operand_type_check (x->types[i], disp))
520dc8e8 2222 pe (x->op[i].disps);
252b5132
RH		 2223 }
2224}
2225
2226static void
e3bb37b5 2227pte (template *t)
252b5132 2228{
09f131f2 2229 unsigned int i;
252b5132 2230 fprintf (stdout, " %d operands ", t->operands);
47926f60 2231 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2232 if (t->extension_opcode != None)
2233 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2234 if (t->opcode_modifier.d)
252b5132 2235 fprintf (stdout, "D");
40fb9820 2236 if (t->opcode_modifier.w)
252b5132
RH		 2237 fprintf (stdout, "W");
2238 fprintf (stdout, "\n");
2239 for (i = 0; i < t->operands; i++)
2240 {
2241 fprintf (stdout, " #%d type ", i + 1);
2242 pt (t->operand_types[i]);
2243 fprintf (stdout, "\n");
2244 }
2245}
2246
2247static void
e3bb37b5 2248pe (expressionS *e)
252b5132 2249{
24eab124 2250 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2251 fprintf (stdout, " add_number %ld (%lx)\n",
2252 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2253 if (e->X_add_symbol)
2254 {
2255 fprintf (stdout, " add_symbol ");
2256 ps (e->X_add_symbol);
2257 fprintf (stdout, "\n");
2258 }
2259 if (e->X_op_symbol)
2260 {
2261 fprintf (stdout, " op_symbol ");
2262 ps (e->X_op_symbol);
2263 fprintf (stdout, "\n");
2264 }
2265}
2266
2267static void
e3bb37b5 2268ps (symbolS *s)
252b5132
RH		 2269{
2270 fprintf (stdout, "%s type %s%s",
2271 S_GET_NAME (s),
2272 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2273 segment_name (S_GET_SEGMENT (s)));
2274}
2275
7b81dfbb 2276static struct type_name
252b5132 2277 {
40fb9820
L		 2278 i386_operand_type mask;
2279 const char *name;
252b5132 2280 }
7b81dfbb 2281const type_names[] =
252b5132 2282{
40fb9820
L		 2283 { OPERAND_TYPE_REG8, "r8" },
2284 { OPERAND_TYPE_REG16, "r16" },
2285 { OPERAND_TYPE_REG32, "r32" },
2286 { OPERAND_TYPE_REG64, "r64" },
2287 { OPERAND_TYPE_IMM8, "i8" },
2288 { OPERAND_TYPE_IMM8, "i8s" },
2289 { OPERAND_TYPE_IMM16, "i16" },
2290 { OPERAND_TYPE_IMM32, "i32" },
2291 { OPERAND_TYPE_IMM32S, "i32s" },
2292 { OPERAND_TYPE_IMM64, "i64" },
2293 { OPERAND_TYPE_IMM1, "i1" },
2294 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2295 { OPERAND_TYPE_DISP8, "d8" },
2296 { OPERAND_TYPE_DISP16, "d16" },
2297 { OPERAND_TYPE_DISP32, "d32" },
2298 { OPERAND_TYPE_DISP32S, "d32s" },
2299 { OPERAND_TYPE_DISP64, "d64" },
2300 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2301 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2302 { OPERAND_TYPE_CONTROL, "control reg" },
2303 { OPERAND_TYPE_TEST, "test reg" },
2304 { OPERAND_TYPE_DEBUG, "debug reg" },
2305 { OPERAND_TYPE_FLOATREG, "FReg" },
2306 { OPERAND_TYPE_FLOATACC, "FAcc" },
2307 { OPERAND_TYPE_SREG2, "SReg2" },
2308 { OPERAND_TYPE_SREG3, "SReg3" },
2309 { OPERAND_TYPE_ACC, "Acc" },
2310 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2311 { OPERAND_TYPE_REGMMX, "rMMX" },
2312 { OPERAND_TYPE_REGXMM, "rXMM" },
2313 { OPERAND_TYPE_ESSEG, "es" },
c0f3af97 2314 { OPERAND_TYPE_VEX_IMM4, "VEX i4" },
252b5132
RH		 2315};
2316
2317static void
40fb9820 2318pt (i386_operand_type t)
252b5132 2319{
40fb9820 2320 unsigned int j;
c6fb90c8 2321 i386_operand_type a;
252b5132 2322
40fb9820 2323 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2324 {
2325 a = operand_type_and (t, type_names[j].mask);
2326 if (!UINTS_ALL_ZERO (a))
2327 fprintf (stdout, "%s, ", type_names[j].name);
2328 }
252b5132
RH		 2329 fflush (stdout);
2330}
2331
2332#endif /* DEBUG386 */
2333\f
252b5132 2334static bfd_reloc_code_real_type
3956db08 2335reloc (unsigned int size,
64e74474
AM		 2336 int pcrel,
2337 int sign,
2338 bfd_reloc_code_real_type other)
252b5132 2339{
47926f60 2340 if (other != NO_RELOC)
3956db08
JB		 2341 {
2342 reloc_howto_type *reloc;
2343
2344 if (size == 8)
2345 switch (other)
2346 {
64e74474
AM		 2347 case BFD_RELOC_X86_64_GOT32:
2348 return BFD_RELOC_X86_64_GOT64;
2349 break;
2350 case BFD_RELOC_X86_64_PLTOFF64:
2351 return BFD_RELOC_X86_64_PLTOFF64;
2352 break;
2353 case BFD_RELOC_X86_64_GOTPC32:
2354 other = BFD_RELOC_X86_64_GOTPC64;
2355 break;
2356 case BFD_RELOC_X86_64_GOTPCREL:
2357 other = BFD_RELOC_X86_64_GOTPCREL64;
2358 break;
2359 case BFD_RELOC_X86_64_TPOFF32:
2360 other = BFD_RELOC_X86_64_TPOFF64;
2361 break;
2362 case BFD_RELOC_X86_64_DTPOFF32:
2363 other = BFD_RELOC_X86_64_DTPOFF64;
2364 break;
2365 default:
2366 break;
3956db08 2367 }
e05278af
JB		 2368
2369 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2370 if (size == 4 && flag_code != CODE_64BIT)
2371 sign = -1;
2372
3956db08
JB		 2373 reloc = bfd_reloc_type_lookup (stdoutput, other);
2374 if (!reloc)
2375 as_bad (_("unknown relocation (%u)"), other);
2376 else if (size != bfd_get_reloc_size (reloc))
2377 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2378 bfd_get_reloc_size (reloc),
2379 size);
2380 else if (pcrel && !reloc->pc_relative)
2381 as_bad (_("non-pc-relative relocation for pc-relative field"));
2382 else if ((reloc->complain_on_overflow == complain_overflow_signed
2383 && !sign)
2384 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 2385 && sign > 0))
3956db08
JB		 2386 as_bad (_("relocated field and relocation type differ in signedness"));
2387 else
2388 return other;
2389 return NO_RELOC;
2390 }
252b5132
RH		 2391
2392 if (pcrel)
2393 {
3e73aa7c 2394 if (!sign)
3956db08 2395 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2396 switch (size)
2397 {
2398 case 1: return BFD_RELOC_8_PCREL;
2399 case 2: return BFD_RELOC_16_PCREL;
2400 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2401 case 8: return BFD_RELOC_64_PCREL;
252b5132 2402 }
3956db08 2403 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2404 }
2405 else
2406 {
3956db08 2407 if (sign > 0)
e5cb08ac 2408 switch (size)
3e73aa7c
JH		 2409 {
2410 case 4: return BFD_RELOC_X86_64_32S;
2411 }
2412 else
2413 switch (size)
2414 {
2415 case 1: return BFD_RELOC_8;
2416 case 2: return BFD_RELOC_16;
2417 case 4: return BFD_RELOC_32;
2418 case 8: return BFD_RELOC_64;
2419 }
3956db08
JB		 2420 as_bad (_("cannot do %s %u byte relocation"),
2421 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2422 }
2423
bfb32b52 2424 abort ();
252b5132
RH		 2425 return BFD_RELOC_NONE;
2426}
2427
47926f60
KH		 2428/* Here we decide which fixups can be adjusted to make them relative to
2429 the beginning of the section instead of the symbol. Basically we need
2430 to make sure that the dynamic relocations are done correctly, so in
2431 some cases we force the original symbol to be used. */
2432
252b5132 2433int
e3bb37b5 2434tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2435{
6d249963 2436#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2437 if (!IS_ELF)
31312f95
AM		 2438 return 1;
2439
a161fe53
AM		 2440 /* Don't adjust pc-relative references to merge sections in 64-bit
2441 mode. */
2442 if (use_rela_relocations
2443 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2444 && fixP->fx_pcrel)
252b5132 2445 return 0;
31312f95 2446
8d01d9a9
AJ		 2447 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2448 and changed later by validate_fix. */
2449 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2450 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2451 return 0;
2452
ce8a8b2f 2453 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2454 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2455 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2456 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2457 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2458 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2459 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2460 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2461 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2462 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2463 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2464 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2465 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2466 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2467 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2468 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2469 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2470 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2471 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2472 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2473 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2474 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2475 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2476 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2477 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2478 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2479 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2480 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2481 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2482 return 0;
31312f95 2483#endif
252b5132
RH		 2484 return 1;
2485}
252b5132 2486
b4cac588 2487static int
e3bb37b5 2488intel_float_operand (const char *mnemonic)
252b5132 2489{
9306ca4a
JB		 2490 /* Note that the value returned is meaningful only for opcodes with (memory)
2491 operands, hence the code here is free to improperly handle opcodes that
2492 have no operands (for better performance and smaller code). */
2493
2494 if (mnemonic[0] != 'f')
2495 return 0; /* non-math */
2496
2497 switch (mnemonic[1])
2498 {
2499 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2500 the fs segment override prefix not currently handled because no
2501 call path can make opcodes without operands get here */
2502 case 'i':
2503 return 2 /* integer op */;
2504 case 'l':
2505 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2506 return 3; /* fldcw/fldenv */
2507 break;
2508 case 'n':
2509 if (mnemonic[2] != 'o' /* fnop */)
2510 return 3; /* non-waiting control op */
2511 break;
2512 case 'r':
2513 if (mnemonic[2] == 's')
2514 return 3; /* frstor/frstpm */
2515 break;
2516 case 's':
2517 if (mnemonic[2] == 'a')
2518 return 3; /* fsave */
2519 if (mnemonic[2] == 't')
2520 {
2521 switch (mnemonic[3])
2522 {
2523 case 'c': /* fstcw */
2524 case 'd': /* fstdw */
2525 case 'e': /* fstenv */
2526 case 's': /* fsts[gw] */
2527 return 3;
2528 }
2529 }
2530 break;
2531 case 'x':
2532 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2533 return 0; /* fxsave/fxrstor are not really math ops */
2534 break;
2535 }
252b5132 2536
9306ca4a 2537 return 1;
252b5132
RH		 2538}
2539
c0f3af97
L		 2540/* Build the VEX prefix. */
2541
2542static void
2543build_vex_prefix (void)
2544{
2545 unsigned int register_specifier;
2546 unsigned int implied_prefix;
2547 unsigned int vector_length;
2548
2549 /* Check register specifier. */
2550 if (i.vex.register_specifier)
2551 {
2552 register_specifier = i.vex.register_specifier->reg_num;
2553 if ((i.vex.register_specifier->reg_flags & RegRex))
2554 register_specifier += 8;
2555 register_specifier = ~register_specifier & 0xf;
2556 }
2557 else
2558 register_specifier = 0xf;
2559
2560 vector_length = i.tm.opcode_modifier.vex256 ? 1 : 0;
2561
2562 switch ((i.tm.base_opcode >> 8) & 0xff)
2563 {
2564 case 0:
2565 implied_prefix = 0;
2566 break;
2567 case DATA_PREFIX_OPCODE:
2568 implied_prefix = 1;
2569 break;
2570 case REPE_PREFIX_OPCODE:
2571 implied_prefix = 2;
2572 break;
2573 case REPNE_PREFIX_OPCODE:
2574 implied_prefix = 3;
2575 break;
2576 default:
2577 abort ();
2578 }
2579
2580 /* Use 2-byte VEX prefix if possible. */
2581 if (i.tm.opcode_modifier.vex0f
2582 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2583 {
2584 /* 2-byte VEX prefix. */
2585 unsigned int r;
2586
2587 i.vex.length = 2;
2588 i.vex.bytes[0] = 0xc5;
2589
2590 /* Check the REX.R bit. */
2591 r = (i.rex & REX_R) ? 0 : 1;
2592 i.vex.bytes[1] = (r << 7
2593 | register_specifier << 3
2594 | vector_length << 2
2595 | implied_prefix);
2596 }
2597 else
2598 {
2599 /* 3-byte VEX prefix. */
2600 unsigned int m, w;
2601
2602 if (i.tm.opcode_modifier.vex0f)
2603 m = 0x1;
2604 else if (i.tm.opcode_modifier.vex0f38)
2605 m = 0x2;
2606 else if (i.tm.opcode_modifier.vex0f3a)
2607 m = 0x3;
2608 else
2609 abort ();
2610
2611 i.vex.length = 3;
2612 i.vex.bytes[0] = 0xc4;
2613
2614 /* The high 3 bits of the second VEX byte are 1's compliment
2615 of RXB bits from REX. */
2616 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2617
2618 /* Check the REX.W bit. */
2619 w = (i.rex & REX_W) ? 1 : 0;
2620 if (i.tm.opcode_modifier.vexw0 || i.tm.opcode_modifier.vexw1)
2621 {
2622 if (w)
2623 abort ();
2624
2625 if (i.tm.opcode_modifier.vexw1)
2626 w = 1;
2627 }
2628
2629 i.vex.bytes[2] = (w << 7
2630 | register_specifier << 3
2631 | vector_length << 2
2632 | implied_prefix);
2633 }
2634}
2635
65da13b5
L		 2636static void
2637process_immext (void)
2638{
2639 expressionS *exp;
2640
2641 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2642 {
1fed0ba1
L		 2643 /* SSE3 Instructions have the fixed operands with an opcode
2644 suffix which is coded in the same place as an 8-bit immediate
2645 field would be. Here we check those operands and remove them
2646 afterwards. */
65da13b5
L		 2647 unsigned int x;
2648
2649 for (x = 0; x < i.operands; x++)
2650 if (i.op[x].regs->reg_num != x)
2651 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2652 register_prefix, i.op[x].regs->reg_name, x + 1,
2653 i.tm.name);
2654
2655 i.operands = 0;
65da13b5
L		 2656 }
2657
c0f3af97 2658 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2659 which is coded in the same place as an 8-bit immediate field
2660 would be. Here we fake an 8-bit immediate operand from the
2661 opcode suffix stored in tm.extension_opcode.
2662
c0f3af97
L		 2663 SSE5 and AVX instructions also use this encoding, for some of
2664 3 argument instructions. */
65da13b5
L		 2665
2666 assert (i.imm_operands == 0
2667 && (i.operands <= 2
2668 || (i.tm.cpu_flags.bitfield.cpusse5
c0f3af97
L		 2669 && i.operands <= 3)
2670 || (i.tm.opcode_modifier.vex
2671 && i.operands <= 4)));
65da13b5
L		 2672
2673 exp = &im_expressions[i.imm_operands++];
2674 i.op[i.operands].imms = exp;
2675 i.types[i.operands] = imm8;
2676 i.operands++;
2677 exp->X_op = O_constant;
2678 exp->X_add_number = i.tm.extension_opcode;
2679 i.tm.extension_opcode = None;
2680}
2681
252b5132
RH		 2682/* This is the guts of the machine-dependent assembler. LINE points to a
2683 machine dependent instruction. This function is supposed to emit
2684 the frags/bytes it assembles to. */
2685
2686void
65da13b5 2687md_assemble (char *line)
252b5132 2688{
40fb9820 2689 unsigned int j;
252b5132
RH		 2690 char mnemonic[MAX_MNEM_SIZE];
2691
47926f60 2692 /* Initialize globals. */
252b5132
RH		 2693 memset (&i, '\0', sizeof (i));
2694 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2695 i.reloc[j] = NO_RELOC;
252b5132
RH		 2696 memset (disp_expressions, '\0', sizeof (disp_expressions));
2697 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2698 save_stack_p = save_stack;
252b5132
RH		 2699
2700 /* First parse an instruction mnemonic & call i386_operand for the operands.
2701 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2702 start of a (possibly prefixed) mnemonic. */
252b5132 2703
29b0f896
AM		 2704 line = parse_insn (line, mnemonic);
2705 if (line == NULL)
2706 return;
252b5132 2707
29b0f896
AM		 2708 line = parse_operands (line, mnemonic);
2709 if (line == NULL)
2710 return;
252b5132 2711
29b0f896
AM		 2712 /* Now we've parsed the mnemonic into a set of templates, and have the
2713 operands at hand. */
2714
2715 /* All intel opcodes have reversed operands except for "bound" and
2716 "enter". We also don't reverse intersegment "jmp" and "call"
2717 instructions with 2 immediate operands so that the immediate segment
050dfa73 2718 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2719 if (intel_syntax
2720 && i.operands > 1
29b0f896 2721 && (strcmp (mnemonic, "bound") != 0)
30123838 2722 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2723 && !(operand_type_check (i.types[0], imm)
2724 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2725 swap_operands ();
2726
ec56d5c0
JB		 2727 /* The order of the immediates should be reversed
2728 for 2 immediates extrq and insertq instructions */
2729 if (i.imm_operands == 2
2730 && (strcmp (mnemonic, "extrq") == 0
2731 || strcmp (mnemonic, "insertq") == 0))
2732 swap_2_operands (0, 1);
2733
29b0f896
AM		 2734 if (i.imm_operands)
2735 optimize_imm ();
2736
b300c311
L		 2737 /* Don't optimize displacement for movabs since it only takes 64bit
2738 displacement. */
2739 if (i.disp_operands
2740 && (flag_code != CODE_64BIT
2741 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2742 optimize_disp ();
2743
2744 /* Next, we find a template that matches the given insn,
2745 making sure the overlap of the given operands types is consistent
2746 with the template operand types. */
252b5132 2747
29b0f896
AM		 2748 if (!match_template ())
2749 return;
252b5132 2750
daf50ae7 2751 if (sse_check != sse_check_none
81f8a913 2752 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 2753 && (i.tm.cpu_flags.bitfield.cpusse
2754 || i.tm.cpu_flags.bitfield.cpusse2
2755 || i.tm.cpu_flags.bitfield.cpusse3
2756 || i.tm.cpu_flags.bitfield.cpussse3
2757 || i.tm.cpu_flags.bitfield.cpusse4_1
2758 || i.tm.cpu_flags.bitfield.cpusse4_2))
2759 {
2760 (sse_check == sse_check_warning
2761 ? as_warn
2762 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
2763 }
2764
321fd21e
L		 2765 /* Zap movzx and movsx suffix. The suffix has been set from
2766 "word ptr" or "byte ptr" on the source operand in Intel syntax
2767 or extracted from mnemonic in AT&T syntax. But we'll use
2768 the destination register to choose the suffix for encoding. */
2769 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 2770 {
321fd21e
L		 2771 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2772 there is no suffix, the default will be byte extension. */
2773 if (i.reg_operands != 2
2774 && !i.suffix
2775 && intel_syntax)
2776 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2777
2778 i.suffix = 0;
cd61ebfe 2779 }
24eab124 2780
40fb9820 2781 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2782 if (!add_prefix (FWAIT_OPCODE))
2783 return;
252b5132 2784
29b0f896 2785 /* Check string instruction segment overrides. */
40fb9820 2786 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2787 {
2788 if (!check_string ())
5dd0794d 2789 return;
fc0763e6 2790 i.disp_operands = 0;
29b0f896 2791 }
5dd0794d 2792
29b0f896
AM		 2793 if (!process_suffix ())
2794 return;
e413e4e9 2795
29b0f896
AM		 2796 /* Make still unresolved immediate matches conform to size of immediate
2797 given in i.suffix. */
2798 if (!finalize_imm ())
2799 return;
252b5132 2800
40fb9820 2801 if (i.types[0].bitfield.imm1)
29b0f896 2802 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2803
40fb9820 2804 for (j = 0; j < 3; j++)
c6fb90c8
L		 2805 if (i.types[j].bitfield.inoutportreg
2806 || i.types[j].bitfield.shiftcount
2807 || i.types[j].bitfield.acc
2808 || i.types[j].bitfield.floatacc)
40fb9820
L		 2809 i.reg_operands--;
2810
c0f3af97
L		 2811 /* ImmExt should be processed after SSE2AVX. */
2812 if (!i.tm.opcode_modifier.sse2avx
2813 && i.tm.opcode_modifier.immext)
65da13b5 2814 process_immext ();
252b5132 2815
29b0f896
AM		 2816 /* For insns with operands there are more diddles to do to the opcode. */
2817 if (i.operands)
2818 {
2819 if (!process_operands ())
2820 return;
2821 }
40fb9820 2822 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2823 {
2824 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2825 as_warn (_("translating to `%sp'"), i.tm.name);
2826 }
252b5132 2827
c0f3af97
L		 2828 if (i.tm.opcode_modifier.vex)
2829 build_vex_prefix ();
2830
29b0f896
AM		 2831 /* Handle conversion of 'int $3' --> special int3 insn. */
2832 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2833 {
2834 i.tm.base_opcode = INT3_OPCODE;
2835 i.imm_operands = 0;
2836 }
252b5132 2837
40fb9820
L		 2838 if ((i.tm.opcode_modifier.jump
2839 || i.tm.opcode_modifier.jumpbyte
2840 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2841 && i.op[0].disps->X_op == O_constant)
2842 {
2843 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2844 the absolute address given by the constant. Since ix86 jumps and
2845 calls are pc relative, we need to generate a reloc. */
2846 i.op[0].disps->X_add_symbol = &abs_symbol;
2847 i.op[0].disps->X_op = O_symbol;
2848 }
252b5132 2849
40fb9820 2850 if (i.tm.opcode_modifier.rex64)
161a04f6 2851 i.rex |= REX_W;
252b5132 2852
29b0f896
AM		 2853 /* For 8 bit registers we need an empty rex prefix. Also if the
2854 instruction already has a prefix, we need to convert old
2855 registers to new ones. */
773f551c 2856
40fb9820 2857 if ((i.types[0].bitfield.reg8
29b0f896 2858 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2859 || (i.types[1].bitfield.reg8
29b0f896 2860 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2861 || ((i.types[0].bitfield.reg8
2862 || i.types[1].bitfield.reg8)
29b0f896
AM		 2863 && i.rex != 0))
2864 {
2865 int x;
726c5dcd 2866
29b0f896
AM		 2867 i.rex |= REX_OPCODE;
2868 for (x = 0; x < 2; x++)
2869 {
2870 /* Look for 8 bit operand that uses old registers. */
40fb9820 2871 if (i.types[x].bitfield.reg8
29b0f896 2872 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2873 {
29b0f896
AM		 2874 /* In case it is "hi" register, give up. */
2875 if (i.op[x].regs->reg_num > 3)
a540244d 2876 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2877 "instruction requiring REX prefix."),
a540244d 2878 register_prefix, i.op[x].regs->reg_name);
773f551c 2879
29b0f896
AM		 2880 /* Otherwise it is equivalent to the extended register.
2881 Since the encoding doesn't change this is merely
2882 cosmetic cleanup for debug output. */
2883
2884 i.op[x].regs = i.op[x].regs + 8;
773f551c 2885 }
29b0f896
AM		 2886 }
2887 }
773f551c 2888
85f10a01
MM		 2889 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2890 REX prefix. */
2891 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2892 {
2893 i.drex.rex = i.rex;
2894 i.rex = 0;
2895 }
2896 else if (i.rex != 0)
29b0f896
AM		 2897 add_prefix (REX_OPCODE | i.rex);
2898
2899 /* We are ready to output the insn. */
2900 output_insn ();
2901}
2902
2903static char *
e3bb37b5 2904parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2905{
2906 char *l = line;
2907 char *token_start = l;
2908 char *mnem_p;
5c6af06e
JB		 2909 int supported;
2910 const template *t;
29b0f896
AM		 2911
2912 /* Non-zero if we found a prefix only acceptable with string insns. */
2913 const char *expecting_string_instruction = NULL;
45288df1 2914
29b0f896
AM		 2915 while (1)
2916 {
2917 mnem_p = mnemonic;
2918 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2919 {
2920 mnem_p++;
2921 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2922 {
29b0f896
AM		 2923 as_bad (_("no such instruction: `%s'"), token_start);
2924 return NULL;
2925 }
2926 l++;
2927 }
2928 if (!is_space_char (*l)
2929 && *l != END_OF_INSN
e44823cf
JB		 2930 && (intel_syntax
2931 || (*l != PREFIX_SEPARATOR
2932 && *l != ',')))
29b0f896
AM		 2933 {
2934 as_bad (_("invalid character %s in mnemonic"),
2935 output_invalid (*l));
2936 return NULL;
2937 }
2938 if (token_start == l)
2939 {
e44823cf 2940 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2941 as_bad (_("expecting prefix; got nothing"));
2942 else
2943 as_bad (_("expecting mnemonic; got nothing"));
2944 return NULL;
2945 }
45288df1 2946
29b0f896
AM		 2947 /* Look up instruction (or prefix) via hash table. */
2948 current_templates = hash_find (op_hash, mnemonic);
47926f60 2949
29b0f896
AM		 2950 if (*l != END_OF_INSN
2951 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2952 && current_templates
40fb9820 2953 && current_templates->start->opcode_modifier.isprefix)
29b0f896 2954 {
c6fb90c8 2955 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 2956 {
2957 as_bad ((flag_code != CODE_64BIT
2958 ? _("`%s' is only supported in 64-bit mode")
2959 : _("`%s' is not supported in 64-bit mode")),
2960 current_templates->start->name);
2961 return NULL;
2962 }
29b0f896
AM		 2963 /* If we are in 16-bit mode, do not allow addr16 or data16.
2964 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 2965 if ((current_templates->start->opcode_modifier.size16
2966 || current_templates->start->opcode_modifier.size32)
29b0f896 2967 && flag_code != CODE_64BIT
40fb9820 2968 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 2969 ^ (flag_code == CODE_16BIT)))
2970 {
2971 as_bad (_("redundant %s prefix"),
2972 current_templates->start->name);
2973 return NULL;
45288df1 2974 }
29b0f896
AM		 2975 /* Add prefix, checking for repeated prefixes. */
2976 switch (add_prefix (current_templates->start->base_opcode))
2977 {
2978 case 0:
2979 return NULL;
2980 case 2:
2981 expecting_string_instruction = current_templates->start->name;
2982 break;
2983 }
2984 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2985 token_start = ++l;
2986 }
2987 else
2988 break;
2989 }
45288df1 2990
29b0f896
AM		 2991 if (!current_templates)
2992 {
2993 /* See if we can get a match by trimming off a suffix. */
2994 switch (mnem_p[-1])
2995 {
2996 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2997 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2998 i.suffix = SHORT_MNEM_SUFFIX;
2999 else
29b0f896
AM		 3000 case BYTE_MNEM_SUFFIX:
3001 case QWORD_MNEM_SUFFIX:
3002 i.suffix = mnem_p[-1];
3003 mnem_p[-1] = '\0';
3004 current_templates = hash_find (op_hash, mnemonic);
3005 break;
3006 case SHORT_MNEM_SUFFIX:
3007 case LONG_MNEM_SUFFIX:
3008 if (!intel_syntax)
3009 {
3010 i.suffix = mnem_p[-1];
3011 mnem_p[-1] = '\0';
3012 current_templates = hash_find (op_hash, mnemonic);
3013 }
3014 break;
252b5132 3015
29b0f896
AM		 3016 /* Intel Syntax. */
3017 case 'd':
3018 if (intel_syntax)
3019 {
9306ca4a 3020 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3021 i.suffix = SHORT_MNEM_SUFFIX;
3022 else
3023 i.suffix = LONG_MNEM_SUFFIX;
3024 mnem_p[-1] = '\0';
3025 current_templates = hash_find (op_hash, mnemonic);
3026 }
3027 break;
3028 }
3029 if (!current_templates)
3030 {
3031 as_bad (_("no such instruction: `%s'"), token_start);
3032 return NULL;
3033 }
3034 }
252b5132 3035
40fb9820
L		 3036 if (current_templates->start->opcode_modifier.jump
3037 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3038 {
3039 /* Check for a branch hint. We allow ",pt" and ",pn" for
3040 predict taken and predict not taken respectively.
3041 I'm not sure that branch hints actually do anything on loop
3042 and jcxz insns (JumpByte) for current Pentium4 chips. They
3043 may work in the future and it doesn't hurt to accept them
3044 now. */
3045 if (l[0] == ',' && l[1] == 'p')
3046 {
3047 if (l[2] == 't')
3048 {
3049 if (!add_prefix (DS_PREFIX_OPCODE))
3050 return NULL;
3051 l += 3;
3052 }
3053 else if (l[2] == 'n')
3054 {
3055 if (!add_prefix (CS_PREFIX_OPCODE))
3056 return NULL;
3057 l += 3;
3058 }
3059 }
3060 }
3061 /* Any other comma loses. */
3062 if (*l == ',')
3063 {
3064 as_bad (_("invalid character %s in mnemonic"),
3065 output_invalid (*l));
3066 return NULL;
3067 }
252b5132 3068
29b0f896 3069 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3070 supported = 0;
3071 for (t = current_templates->start; t < current_templates->end; ++t)
3072 {
c0f3af97
L		 3073 supported |= cpu_flags_match (t);
3074 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3075 goto skip;
5c6af06e 3076 }
3629bb00 3077
c0f3af97 3078 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3079 {
3080 as_bad (flag_code == CODE_64BIT
3081 ? _("`%s' is not supported in 64-bit mode")
3082 : _("`%s' is only supported in 64-bit mode"),
3083 current_templates->start->name);
3084 return NULL;
3085 }
c0f3af97 3086 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3087 {
3629bb00
L		 3088 as_bad (_("`%s' is not supported on `%s%s'"),
3089 current_templates->start->name, cpu_arch_name,
3090 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3091 return NULL;
29b0f896 3092 }
3629bb00
L		 3093
3094skip:
3095 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3096 && (flag_code != CODE_16BIT))
29b0f896
AM		 3097 {
3098 as_warn (_("use .code16 to ensure correct addressing mode"));
3099 }
252b5132 3100
29b0f896 3101 /* Check for rep/repne without a string instruction. */
f41bbced 3102 if (expecting_string_instruction)
29b0f896 3103 {
f41bbced
JB		 3104 static templates override;
3105
3106 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3107 if (t->opcode_modifier.isstring)
f41bbced
JB		 3108 break;
3109 if (t >= current_templates->end)
3110 {
3111 as_bad (_("expecting string instruction after `%s'"),
64e74474 3112 expecting_string_instruction);
f41bbced
JB		 3113 return NULL;
3114 }
3115 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3116 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3117 break;
3118 override.end = t;
3119 current_templates = &override;
29b0f896 3120 }
252b5132 3121
29b0f896
AM		 3122 return l;
3123}
252b5132 3124
29b0f896 3125static char *
e3bb37b5 3126parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3127{
3128 char *token_start;
3138f287 3129
29b0f896
AM		 3130 /* 1 if operand is pending after ','. */
3131 unsigned int expecting_operand = 0;
252b5132 3132
29b0f896
AM		 3133 /* Non-zero if operand parens not balanced. */
3134 unsigned int paren_not_balanced;
3135
3136 while (*l != END_OF_INSN)
3137 {
3138 /* Skip optional white space before operand. */
3139 if (is_space_char (*l))
3140 ++l;
3141 if (!is_operand_char (*l) && *l != END_OF_INSN)
3142 {
3143 as_bad (_("invalid character %s before operand %d"),
3144 output_invalid (*l),
3145 i.operands + 1);
3146 return NULL;
3147 }
3148 token_start = l; /* after white space */
3149 paren_not_balanced = 0;
3150 while (paren_not_balanced || *l != ',')
3151 {
3152 if (*l == END_OF_INSN)
3153 {
3154 if (paren_not_balanced)
3155 {
3156 if (!intel_syntax)
3157 as_bad (_("unbalanced parenthesis in operand %d."),
3158 i.operands + 1);
3159 else
3160 as_bad (_("unbalanced brackets in operand %d."),
3161 i.operands + 1);
3162 return NULL;
3163 }
3164 else
3165 break; /* we are done */
3166 }
3167 else if (!is_operand_char (*l) && !is_space_char (*l))
3168 {
3169 as_bad (_("invalid character %s in operand %d"),
3170 output_invalid (*l),
3171 i.operands + 1);
3172 return NULL;
3173 }
3174 if (!intel_syntax)
3175 {
3176 if (*l == '(')
3177 ++paren_not_balanced;
3178 if (*l == ')')
3179 --paren_not_balanced;
3180 }
3181 else
3182 {
3183 if (*l == '[')
3184 ++paren_not_balanced;
3185 if (*l == ']')
3186 --paren_not_balanced;
3187 }
3188 l++;
3189 }
3190 if (l != token_start)
3191 { /* Yes, we've read in another operand. */
3192 unsigned int operand_ok;
3193 this_operand = i.operands++;
7d5e4556 3194 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3195 if (i.operands > MAX_OPERANDS)
3196 {
3197 as_bad (_("spurious operands; (%d operands/instruction max)"),
3198 MAX_OPERANDS);
3199 return NULL;
3200 }
3201 /* Now parse operand adding info to 'i' as we go along. */
3202 END_STRING_AND_SAVE (l);
3203
3204 if (intel_syntax)
3205 operand_ok =
3206 i386_intel_operand (token_start,
3207 intel_float_operand (mnemonic));
3208 else
a7619375 3209 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3210
3211 RESTORE_END_STRING (l);
3212 if (!operand_ok)
3213 return NULL;
3214 }
3215 else
3216 {
3217 if (expecting_operand)
3218 {
3219 expecting_operand_after_comma:
3220 as_bad (_("expecting operand after ','; got nothing"));
3221 return NULL;
3222 }
3223 if (*l == ',')
3224 {
3225 as_bad (_("expecting operand before ','; got nothing"));
3226 return NULL;
3227 }
3228 }
7f3f1ea2 3229
29b0f896
AM		 3230 /* Now *l must be either ',' or END_OF_INSN. */
3231 if (*l == ',')
3232 {
3233 if (*++l == END_OF_INSN)
3234 {
3235 /* Just skip it, if it's \n complain. */
3236 goto expecting_operand_after_comma;
3237 }
3238 expecting_operand = 1;
3239 }
3240 }
3241 return l;
3242}
7f3f1ea2 3243
050dfa73 3244static void
4d456e3d 3245swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3246{
3247 union i386_op temp_op;
40fb9820 3248 i386_operand_type temp_type;
050dfa73 3249 enum bfd_reloc_code_real temp_reloc;
4eed87de 3250
050dfa73
MM		 3251 temp_type = i.types[xchg2];
3252 i.types[xchg2] = i.types[xchg1];
3253 i.types[xchg1] = temp_type;
3254 temp_op = i.op[xchg2];
3255 i.op[xchg2] = i.op[xchg1];
3256 i.op[xchg1] = temp_op;
3257 temp_reloc = i.reloc[xchg2];
3258 i.reloc[xchg2] = i.reloc[xchg1];
3259 i.reloc[xchg1] = temp_reloc;
3260}
3261
29b0f896 3262static void
e3bb37b5 3263swap_operands (void)
29b0f896 3264{
b7c61d9a 3265 switch (i.operands)
050dfa73 3266 {
c0f3af97 3267 case 5:
b7c61d9a 3268 case 4:
4d456e3d 3269 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3270 case 3:
3271 case 2:
4d456e3d 3272 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3273 break;
3274 default:
3275 abort ();
29b0f896 3276 }
29b0f896
AM		 3277
3278 if (i.mem_operands == 2)
3279 {
3280 const seg_entry *temp_seg;
3281 temp_seg = i.seg[0];
3282 i.seg[0] = i.seg[1];
3283 i.seg[1] = temp_seg;
3284 }
3285}
252b5132 3286
29b0f896
AM		 3287/* Try to ensure constant immediates are represented in the smallest
3288 opcode possible. */
3289static void
e3bb37b5 3290optimize_imm (void)
29b0f896
AM		 3291{
3292 char guess_suffix = 0;
3293 int op;
252b5132 3294
29b0f896
AM		 3295 if (i.suffix)
3296 guess_suffix = i.suffix;
3297 else if (i.reg_operands)
3298 {
3299 /* Figure out a suffix from the last register operand specified.
3300 We can't do this properly yet, ie. excluding InOutPortReg,
3301 but the following works for instructions with immediates.
3302 In any case, we can't set i.suffix yet. */
3303 for (op = i.operands; --op >= 0;)
40fb9820
L		 3304 if (i.types[op].bitfield.reg8)
3305 {
3306 guess_suffix = BYTE_MNEM_SUFFIX;
3307 break;
3308 }
3309 else if (i.types[op].bitfield.reg16)
252b5132 3310 {
40fb9820
L		 3311 guess_suffix = WORD_MNEM_SUFFIX;
3312 break;
3313 }
3314 else if (i.types[op].bitfield.reg32)
3315 {
3316 guess_suffix = LONG_MNEM_SUFFIX;
3317 break;
3318 }
3319 else if (i.types[op].bitfield.reg64)
3320 {
3321 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3322 break;
252b5132 3323 }
29b0f896
AM		 3324 }
3325 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3326 guess_suffix = WORD_MNEM_SUFFIX;
3327
3328 for (op = i.operands; --op >= 0;)
40fb9820 3329 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3330 {
3331 switch (i.op[op].imms->X_op)
252b5132 3332 {
29b0f896
AM		 3333 case O_constant:
3334 /* If a suffix is given, this operand may be shortened. */
3335 switch (guess_suffix)
252b5132 3336 {
29b0f896 3337 case LONG_MNEM_SUFFIX:
40fb9820
L		 3338 i.types[op].bitfield.imm32 = 1;
3339 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3340 break;
3341 case WORD_MNEM_SUFFIX:
40fb9820
L		 3342 i.types[op].bitfield.imm16 = 1;
3343 i.types[op].bitfield.imm32 = 1;
3344 i.types[op].bitfield.imm32s = 1;
3345 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3346 break;
3347 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3348 i.types[op].bitfield.imm8 = 1;
3349 i.types[op].bitfield.imm8s = 1;
3350 i.types[op].bitfield.imm16 = 1;
3351 i.types[op].bitfield.imm32 = 1;
3352 i.types[op].bitfield.imm32s = 1;
3353 i.types[op].bitfield.imm64 = 1;
29b0f896 3354 break;
252b5132 3355 }
252b5132 3356
29b0f896
AM		 3357 /* If this operand is at most 16 bits, convert it
3358 to a signed 16 bit number before trying to see
3359 whether it will fit in an even smaller size.
3360 This allows a 16-bit operand such as $0xffe0 to
3361 be recognised as within Imm8S range. */
40fb9820 3362 if ((i.types[op].bitfield.imm16)
29b0f896 3363 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3364 {
29b0f896
AM		 3365 i.op[op].imms->X_add_number =
3366 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3367 }
40fb9820 3368 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3369 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3370 == 0))
3371 {
3372 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3373 ^ ((offsetT) 1 << 31))
3374 - ((offsetT) 1 << 31));
3375 }
40fb9820 3376 i.types[op]
c6fb90c8
L		 3377 = operand_type_or (i.types[op],
3378 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3379
29b0f896
AM		 3380 /* We must avoid matching of Imm32 templates when 64bit
3381 only immediate is available. */
3382 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3383 i.types[op].bitfield.imm32 = 0;
29b0f896 3384 break;
252b5132 3385
29b0f896
AM		 3386 case O_absent:
3387 case O_register:
3388 abort ();
3389
3390 /* Symbols and expressions. */
3391 default:
9cd96992
JB		 3392 /* Convert symbolic operand to proper sizes for matching, but don't
3393 prevent matching a set of insns that only supports sizes other
3394 than those matching the insn suffix. */
3395 {
40fb9820 3396 i386_operand_type mask, allowed;
9cd96992
JB		 3397 const template *t;
3398
0dfbf9d7
L		 3399 operand_type_set (&mask, 0);
3400 operand_type_set (&allowed, 0);
40fb9820 3401
4eed87de
AM		 3402 for (t = current_templates->start;
3403 t < current_templates->end;
3404 ++t)
c6fb90c8
L		 3405 allowed = operand_type_or (allowed,
3406 t->operand_types[op]);
9cd96992
JB		 3407 switch (guess_suffix)
3408 {
3409 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3410 mask.bitfield.imm64 = 1;
3411 mask.bitfield.imm32s = 1;
9cd96992
JB		 3412 break;
3413 case LONG_MNEM_SUFFIX:
40fb9820 3414 mask.bitfield.imm32 = 1;
9cd96992
JB		 3415 break;
3416 case WORD_MNEM_SUFFIX:
40fb9820 3417 mask.bitfield.imm16 = 1;
9cd96992
JB		 3418 break;
3419 case BYTE_MNEM_SUFFIX:
40fb9820 3420 mask.bitfield.imm8 = 1;
9cd96992
JB		 3421 break;
3422 default:
9cd96992
JB		 3423 break;
3424 }
c6fb90c8 3425 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3426 if (!operand_type_all_zero (&allowed))
c6fb90c8 3427 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3428 }
29b0f896 3429 break;
252b5132 3430 }
29b0f896
AM		 3431 }
3432}
47926f60 3433
29b0f896
AM		 3434/* Try to use the smallest displacement type too. */
3435static void
e3bb37b5 3436optimize_disp (void)
29b0f896
AM		 3437{
3438 int op;
3e73aa7c 3439
29b0f896 3440 for (op = i.operands; --op >= 0;)
40fb9820 3441 if (operand_type_check (i.types[op], disp))
252b5132 3442 {
b300c311 3443 if (i.op[op].disps->X_op == O_constant)
252b5132 3444 {
b300c311 3445 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 3446
40fb9820 3447 if (i.types[op].bitfield.disp16
b300c311
L		 3448 && (disp & ~(offsetT) 0xffff) == 0)
3449 {
3450 /* If this operand is at most 16 bits, convert
3451 to a signed 16 bit number and don't use 64bit
3452 displacement. */
3453 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3454 i.types[op].bitfield.disp64 = 0;
b300c311 3455 }
40fb9820 3456 if (i.types[op].bitfield.disp32
b300c311
L		 3457 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3458 {
3459 /* If this operand is at most 32 bits, convert
3460 to a signed 32 bit number and don't use 64bit
3461 displacement. */
3462 disp &= (((offsetT) 2 << 31) - 1);
3463 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3464 i.types[op].bitfield.disp64 = 0;
b300c311 3465 }
40fb9820 3466 if (!disp && i.types[op].bitfield.baseindex)
b300c311 3467 {
40fb9820
L		 3468 i.types[op].bitfield.disp8 = 0;
3469 i.types[op].bitfield.disp16 = 0;
3470 i.types[op].bitfield.disp32 = 0;
3471 i.types[op].bitfield.disp32s = 0;
3472 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3473 i.op[op].disps = 0;
3474 i.disp_operands--;
3475 }
3476 else if (flag_code == CODE_64BIT)
3477 {
3478 if (fits_in_signed_long (disp))
28a9d8f5 3479 {
40fb9820
L		 3480 i.types[op].bitfield.disp64 = 0;
3481 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3482 }
b300c311 3483 if (fits_in_unsigned_long (disp))
40fb9820 3484 i.types[op].bitfield.disp32 = 1;
b300c311 3485 }
40fb9820
L		 3486 if ((i.types[op].bitfield.disp32
3487 || i.types[op].bitfield.disp32s
3488 || i.types[op].bitfield.disp16)
b300c311 3489 && fits_in_signed_byte (disp))
40fb9820 3490 i.types[op].bitfield.disp8 = 1;
252b5132 3491 }
67a4f2b7
AO		 3492 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3493 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3494 {
3495 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3496 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3497 i.types[op].bitfield.disp8 = 0;
3498 i.types[op].bitfield.disp16 = 0;
3499 i.types[op].bitfield.disp32 = 0;
3500 i.types[op].bitfield.disp32s = 0;
3501 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3502 }
3503 else
b300c311 3504 /* We only support 64bit displacement on constants. */
40fb9820 3505 i.types[op].bitfield.disp64 = 0;
252b5132 3506 }
29b0f896
AM		 3507}
3508
c0f3af97
L		 3509/* Check if operands are valid for the instrucrtion. Update VEX
3510 operand types. */
3511
3512static int
3513VEX_check_operands (const template *t)
3514{
3515 if (!t->opcode_modifier.vex)
3516 return 0;
3517
3518 /* Only check VEX_Imm4, which must be the first operand. */
3519 if (t->operand_types[0].bitfield.vex_imm4)
3520 {
3521 if (i.op[0].imms->X_op != O_constant
3522 || !fits_in_imm4 (i.op[0].imms->X_add_number))
3523 return 1;
3524
3525 /* Turn off Imm8 so that update_imm won't complain. */
3526 i.types[0] = vex_imm4;
3527 }
3528
3529 return 0;
3530}
3531
29b0f896 3532static int
e3bb37b5 3533match_template (void)
29b0f896
AM		 3534{
3535 /* Points to template once we've found it. */
3536 const template *t;
40fb9820 3537 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3538 i386_operand_type overlap4;
29b0f896 3539 unsigned int found_reverse_match;
40fb9820
L		 3540 i386_opcode_modifier suffix_check;
3541 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3542 int addr_prefix_disp;
a5c311ca 3543 unsigned int j;
3629bb00 3544 unsigned int found_cpu_match;
45664ddb 3545 unsigned int check_register;
29b0f896 3546
c0f3af97
L		 3547#if MAX_OPERANDS != 5
3548# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3549#endif
3550
29b0f896 3551 found_reverse_match = 0;
539e75ad 3552 addr_prefix_disp = -1;
40fb9820
L		 3553
3554 memset (&suffix_check, 0, sizeof (suffix_check));
3555 if (i.suffix == BYTE_MNEM_SUFFIX)
3556 suffix_check.no_bsuf = 1;
3557 else if (i.suffix == WORD_MNEM_SUFFIX)
3558 suffix_check.no_wsuf = 1;
3559 else if (i.suffix == SHORT_MNEM_SUFFIX)
3560 suffix_check.no_ssuf = 1;
3561 else if (i.suffix == LONG_MNEM_SUFFIX)
3562 suffix_check.no_lsuf = 1;
3563 else if (i.suffix == QWORD_MNEM_SUFFIX)
3564 suffix_check.no_qsuf = 1;
3565 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3566 suffix_check.no_ldsuf = 1;
29b0f896 3567
45aa61fe 3568 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3569 {
539e75ad
L		 3570 addr_prefix_disp = -1;
3571
29b0f896
AM		 3572 /* Must have right number of operands. */
3573 if (i.operands != t->operands)
3574 continue;
3575
50aecf8c 3576 /* Check processor support. */
c0f3af97
L		 3577 found_cpu_match = (cpu_flags_match (t)
3578 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3579 if (!found_cpu_match)
3580 continue;
3581
e1d4d893
L		 3582 /* Check old gcc support. */
3583 if (!old_gcc && t->opcode_modifier.oldgcc)
3584 continue;
3585
3586 /* Check AT&T mnemonic. */
3587 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3588 continue;
3589
5c07affc
L		 3590 /* Check AT&T syntax Intel syntax. */
3591 if ((intel_syntax && t->opcode_modifier.attsyntax)
3592 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3593 continue;
3594
20592a94 3595 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3596 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3597 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3598 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3599 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3600 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3601 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3602 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3603 continue;
3604
5c07affc 3605 if (!operand_size_match (t))
7d5e4556 3606 continue;
539e75ad 3607
5c07affc
L		 3608 for (j = 0; j < MAX_OPERANDS; j++)
3609 operand_types[j] = t->operand_types[j];
3610
45aa61fe
AM		 3611 /* In general, don't allow 64-bit operands in 32-bit mode. */
3612 if (i.suffix == QWORD_MNEM_SUFFIX
3613 && flag_code != CODE_64BIT
3614 && (intel_syntax
40fb9820 3615 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3616 && !intel_float_operand (t->name))
3617 : intel_float_operand (t->name) != 2)
40fb9820 3618 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3619 && !operand_types[0].bitfield.regxmm
3620 && !operand_types[0].bitfield.regymm)
40fb9820 3621 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3622 && !!operand_types[t->operands > 1].bitfield.regxmm
3623 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3624 && (t->base_opcode != 0x0fc7
3625 || t->extension_opcode != 1 /* cmpxchg8b */))
3626 continue;
3627
192dc9c6
JB		 3628 /* In general, don't allow 32-bit operands on pre-386. */
3629 else if (i.suffix == LONG_MNEM_SUFFIX
3630 && !cpu_arch_flags.bitfield.cpui386
3631 && (intel_syntax
3632 ? (!t->opcode_modifier.ignoresize
3633 && !intel_float_operand (t->name))
3634 : intel_float_operand (t->name) != 2)
3635 && ((!operand_types[0].bitfield.regmmx
3636 && !operand_types[0].bitfield.regxmm)
3637 || (!operand_types[t->operands > 1].bitfield.regmmx
3638 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3639 continue;
3640
29b0f896 3641 /* Do not verify operands when there are none. */
50aecf8c 3642 else
29b0f896 3643 {
c6fb90c8 3644 if (!t->operands)
2dbab7d5
L		 3645 /* We've found a match; break out of loop. */
3646 break;
29b0f896 3647 }
252b5132 3648
539e75ad
L		 3649 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3650 into Disp32/Disp16/Disp32 operand. */
3651 if (i.prefix[ADDR_PREFIX] != 0)
3652 {
40fb9820 3653 /* There should be only one Disp operand. */
539e75ad
L		 3654 switch (flag_code)
3655 {
3656 case CODE_16BIT:
40fb9820
L		 3657 for (j = 0; j < MAX_OPERANDS; j++)
3658 {
3659 if (operand_types[j].bitfield.disp16)
3660 {
3661 addr_prefix_disp = j;
3662 operand_types[j].bitfield.disp32 = 1;
3663 operand_types[j].bitfield.disp16 = 0;
3664 break;
3665 }
3666 }
539e75ad
L		 3667 break;
3668 case CODE_32BIT:
40fb9820
L		 3669 for (j = 0; j < MAX_OPERANDS; j++)
3670 {
3671 if (operand_types[j].bitfield.disp32)
3672 {
3673 addr_prefix_disp = j;
3674 operand_types[j].bitfield.disp32 = 0;
3675 operand_types[j].bitfield.disp16 = 1;
3676 break;
3677 }
3678 }
539e75ad
L		 3679 break;
3680 case CODE_64BIT:
40fb9820
L		 3681 for (j = 0; j < MAX_OPERANDS; j++)
3682 {
3683 if (operand_types[j].bitfield.disp64)
3684 {
3685 addr_prefix_disp = j;
3686 operand_types[j].bitfield.disp64 = 0;
3687 operand_types[j].bitfield.disp32 = 1;
3688 break;
3689 }
3690 }
539e75ad
L		 3691 break;
3692 }
539e75ad
L		 3693 }
3694
45664ddb
L		 3695 /* We check register size only if size of operands can be
3696 encoded the canonical way. */
3697 check_register = t->opcode_modifier.w;
c6fb90c8 3698 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3699 switch (t->operands)
3700 {
3701 case 1:
40fb9820 3702 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3703 continue;
3704 break;
3705 case 2:
8b38ad71
L		 3706 /* xchg %eax, %eax is a special case. It is an aliase for nop
3707 only in 32bit mode and we can use opcode 0x90. In 64bit
3708 mode, we can't use 0x90 for xchg %eax, %eax since it should
3709 zero-extend %eax to %rax. */
3710 if (flag_code == CODE_64BIT
3711 && t->base_opcode == 0x90
0dfbf9d7
L		 3712 && operand_type_equal (&i.types [0], &acc32)
3713 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 3714 continue;
29b0f896 3715 case 3:
f48ff2ae 3716 case 4:
c0f3af97 3717 case 5:
c6fb90c8 3718 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3719 if (!operand_type_match (overlap0, i.types[0])
3720 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3721 || (check_register
3722 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3723 operand_types[0],
3724 overlap1, i.types[1],
3725 operand_types[1])))
29b0f896
AM		 3726 {
3727 /* Check if other direction is valid ... */
40fb9820 3728 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3729 continue;
3730
3731 /* Try reversing direction of operands. */
c6fb90c8
L		 3732 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3733 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3734 if (!operand_type_match (overlap0, i.types[0])
3735 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3736 || (check_register
3737 && !operand_type_register_match (overlap0,
3738 i.types[0],
3739 operand_types[1],
3740 overlap1,
3741 i.types[1],
3742 operand_types[0])))
29b0f896
AM		 3743 {
3744 /* Does not match either direction. */
3745 continue;
3746 }
3747 /* found_reverse_match holds which of D or FloatDR
3748 we've found. */
40fb9820 3749 if (t->opcode_modifier.d)
8a2ed489 3750 found_reverse_match = Opcode_D;
40fb9820 3751 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3752 found_reverse_match = Opcode_FloatD;
3753 else
3754 found_reverse_match = 0;
40fb9820 3755 if (t->opcode_modifier.floatr)
8a2ed489 3756 found_reverse_match |= Opcode_FloatR;
29b0f896 3757 }
f48ff2ae 3758 else
29b0f896 3759 {
f48ff2ae 3760 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3761 switch (t->operands)
3762 {
c0f3af97
L		 3763 case 5:
3764 overlap4 = operand_type_and (i.types[4],
3765 operand_types[4]);
d1cbb4db 3766 case 4:
c6fb90c8
L		 3767 overlap3 = operand_type_and (i.types[3],
3768 operand_types[3]);
d1cbb4db 3769 case 3:
c6fb90c8
L		 3770 overlap2 = operand_type_and (i.types[2],
3771 operand_types[2]);
d1cbb4db
L		 3772 break;
3773 }
29b0f896 3774
f48ff2ae
L		 3775 switch (t->operands)
3776 {
c0f3af97
L		 3777 case 5:
3778 if (!operand_type_match (overlap4, i.types[4])
3779 || !operand_type_register_match (overlap3,
3780 i.types[3],
3781 operand_types[3],
3782 overlap4,
3783 i.types[4],
3784 operand_types[4]))
3785 continue;
f48ff2ae 3786 case 4:
40fb9820 3787 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 3788 || (check_register
3789 && !operand_type_register_match (overlap2,
3790 i.types[2],
3791 operand_types[2],
3792 overlap3,
3793 i.types[3],
3794 operand_types[3])))
f48ff2ae
L		 3795 continue;
3796 case 3:
3797 /* Here we make use of the fact that there are no
3798 reverse match 3 operand instructions, and all 3
3799 operand instructions only need to be checked for
3800 register consistency between operands 2 and 3. */
40fb9820 3801 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 3802 || (check_register
3803 && !operand_type_register_match (overlap1,
3804 i.types[1],
3805 operand_types[1],
3806 overlap2,
3807 i.types[2],
3808 operand_types[2])))
f48ff2ae
L		 3809 continue;
3810 break;
3811 }
29b0f896 3812 }
f48ff2ae 3813 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3814 slip through to break. */
3815 }
3629bb00 3816 if (!found_cpu_match)
29b0f896
AM		 3817 {
3818 found_reverse_match = 0;
3819 continue;
3820 }
c0f3af97
L		 3821
3822 /* Check if VEX operands are valid. */
3823 if (VEX_check_operands (t))
3824 continue;
3825
29b0f896
AM		 3826 /* We've found a match; break out of loop. */
3827 break;
3828 }
3829
3830 if (t == current_templates->end)
3831 {
3832 /* We found no match. */
95f283e8
L		 3833 if (intel_syntax)
3834 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3835 current_templates->start->name);
3836 else
3837 as_bad (_("suffix or operands invalid for `%s'"),
3838 current_templates->start->name);
29b0f896
AM		 3839 return 0;
3840 }
252b5132 3841
29b0f896
AM		 3842 if (!quiet_warnings)
3843 {
3844 if (!intel_syntax
40fb9820
L		 3845 && (i.types[0].bitfield.jumpabsolute
3846 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3847 {
3848 as_warn (_("indirect %s without `*'"), t->name);
3849 }
3850
40fb9820
L		 3851 if (t->opcode_modifier.isprefix
3852 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3853 {
3854 /* Warn them that a data or address size prefix doesn't
3855 affect assembly of the next line of code. */
3856 as_warn (_("stand-alone `%s' prefix"), t->name);
3857 }
3858 }
3859
3860 /* Copy the template we found. */
3861 i.tm = *t;
539e75ad
L		 3862
3863 if (addr_prefix_disp != -1)
3864 i.tm.operand_types[addr_prefix_disp]
3865 = operand_types[addr_prefix_disp];
3866
29b0f896
AM		 3867 if (found_reverse_match)
3868 {
3869 /* If we found a reverse match we must alter the opcode
3870 direction bit. found_reverse_match holds bits to change
3871 (different for int & float insns). */
3872
3873 i.tm.base_opcode ^= found_reverse_match;
3874
539e75ad
L		 3875 i.tm.operand_types[0] = operand_types[1];
3876 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3877 }
3878
3879 return 1;
3880}
3881
3882static int
e3bb37b5 3883check_string (void)
29b0f896 3884{
40fb9820
L		 3885 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3886 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3887 {
3888 if (i.seg[0] != NULL && i.seg[0] != &es)
3889 {
a87af027 3890 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 3891 i.tm.name,
a87af027
JB		 3892 mem_op + 1,
3893 register_prefix);
29b0f896
AM		 3894 return 0;
3895 }
3896 /* There's only ever one segment override allowed per instruction.
3897 This instruction possibly has a legal segment override on the
3898 second operand, so copy the segment to where non-string
3899 instructions store it, allowing common code. */
3900 i.seg[0] = i.seg[1];
3901 }
40fb9820 3902 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3903 {
3904 if (i.seg[1] != NULL && i.seg[1] != &es)
3905 {
a87af027 3906 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 3907 i.tm.name,
a87af027
JB		 3908 mem_op + 2,
3909 register_prefix);
29b0f896
AM		 3910 return 0;
3911 }
3912 }
3913 return 1;
3914}
3915
3916static int
543613e9 3917process_suffix (void)
29b0f896
AM		 3918{
3919 /* If matched instruction specifies an explicit instruction mnemonic
3920 suffix, use it. */
40fb9820
L		 3921 if (i.tm.opcode_modifier.size16)
3922 i.suffix = WORD_MNEM_SUFFIX;
3923 else if (i.tm.opcode_modifier.size32)
3924 i.suffix = LONG_MNEM_SUFFIX;
3925 else if (i.tm.opcode_modifier.size64)
3926 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 3927 else if (i.reg_operands)
3928 {
3929 /* If there's no instruction mnemonic suffix we try to invent one
3930 based on register operands. */
3931 if (!i.suffix)
3932 {
3933 /* We take i.suffix from the last register operand specified,
3934 Destination register type is more significant than source
381d071f
L		 3935 register type. crc32 in SSE4.2 prefers source register
3936 type. */
3937 if (i.tm.base_opcode == 0xf20f38f1)
3938 {
40fb9820
L		 3939 if (i.types[0].bitfield.reg16)
3940 i.suffix = WORD_MNEM_SUFFIX;
3941 else if (i.types[0].bitfield.reg32)
3942 i.suffix = LONG_MNEM_SUFFIX;
3943 else if (i.types[0].bitfield.reg64)
3944 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 3945 }
9344ff29 3946 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 3947 {
40fb9820 3948 if (i.types[0].bitfield.reg8)
20592a94
L		 3949 i.suffix = BYTE_MNEM_SUFFIX;
3950 }
381d071f
L		 3951
3952 if (!i.suffix)
3953 {
3954 int op;
3955
20592a94
L		 3956 if (i.tm.base_opcode == 0xf20f38f1
3957 || i.tm.base_opcode == 0xf20f38f0)
3958 {
3959 /* We have to know the operand size for crc32. */
3960 as_bad (_("ambiguous memory operand size for `%s`"),
3961 i.tm.name);
3962 return 0;
3963 }
3964
381d071f 3965 for (op = i.operands; --op >= 0;)
40fb9820 3966 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 3967 {
40fb9820
L		 3968 if (i.types[op].bitfield.reg8)
3969 {
3970 i.suffix = BYTE_MNEM_SUFFIX;
3971 break;
3972 }
3973 else if (i.types[op].bitfield.reg16)
3974 {
3975 i.suffix = WORD_MNEM_SUFFIX;
3976 break;
3977 }
3978 else if (i.types[op].bitfield.reg32)
3979 {
3980 i.suffix = LONG_MNEM_SUFFIX;
3981 break;
3982 }
3983 else if (i.types[op].bitfield.reg64)
3984 {
3985 i.suffix = QWORD_MNEM_SUFFIX;
3986 break;
3987 }
381d071f
L		 3988 }
3989 }
29b0f896
AM		 3990 }
3991 else if (i.suffix == BYTE_MNEM_SUFFIX)
3992 {
3993 if (!check_byte_reg ())
3994 return 0;
3995 }
3996 else if (i.suffix == LONG_MNEM_SUFFIX)
3997 {
3998 if (!check_long_reg ())
3999 return 0;
4000 }
4001 else if (i.suffix == QWORD_MNEM_SUFFIX)
4002 {
955e1e6a
L		 4003 if (intel_syntax
4004 && i.tm.opcode_modifier.ignoresize
4005 && i.tm.opcode_modifier.no_qsuf)
4006 i.suffix = 0;
4007 else if (!check_qword_reg ())
29b0f896
AM		 4008 return 0;
4009 }
4010 else if (i.suffix == WORD_MNEM_SUFFIX)
4011 {
4012 if (!check_word_reg ())
4013 return 0;
4014 }
c0f3af97
L		 4015 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4016 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4017 {
c0f3af97 4018 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4019 should check if it is a valid suffix. */
4020 }
40fb9820 4021 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4022 /* Do nothing if the instruction is going to ignore the prefix. */
4023 ;
4024 else
4025 abort ();
4026 }
40fb9820 4027 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4028 && !i.suffix
4029 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4030 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4031 {
4032 i.suffix = stackop_size;
4033 }
9306ca4a
JB		 4034 else if (intel_syntax
4035 && !i.suffix
40fb9820
L		 4036 && (i.tm.operand_types[0].bitfield.jumpabsolute
4037 || i.tm.opcode_modifier.jumpbyte
4038 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4039 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4040 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4041 {
4042 switch (flag_code)
4043 {
4044 case CODE_64BIT:
40fb9820 4045 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4046 {
4047 i.suffix = QWORD_MNEM_SUFFIX;
4048 break;
4049 }
4050 case CODE_32BIT:
40fb9820 4051 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4052 i.suffix = LONG_MNEM_SUFFIX;
4053 break;
4054 case CODE_16BIT:
40fb9820 4055 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4056 i.suffix = WORD_MNEM_SUFFIX;
4057 break;
4058 }
4059 }
252b5132 4060
9306ca4a 4061 if (!i.suffix)
29b0f896 4062 {
9306ca4a
JB		 4063 if (!intel_syntax)
4064 {
40fb9820 4065 if (i.tm.opcode_modifier.w)
9306ca4a 4066 {
4eed87de
AM		 4067 as_bad (_("no instruction mnemonic suffix given and "
4068 "no register operands; can't size instruction"));
9306ca4a
JB		 4069 return 0;
4070 }
4071 }
4072 else
4073 {
40fb9820
L		 4074 unsigned int suffixes;
4075
4076 suffixes = !i.tm.opcode_modifier.no_bsuf;
4077 if (!i.tm.opcode_modifier.no_wsuf)
4078 suffixes |= 1 << 1;
4079 if (!i.tm.opcode_modifier.no_lsuf)
4080 suffixes |= 1 << 2;
fc4adea1 4081 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4082 suffixes |= 1 << 3;
4083 if (!i.tm.opcode_modifier.no_ssuf)
4084 suffixes |= 1 << 4;
4085 if (!i.tm.opcode_modifier.no_qsuf)
4086 suffixes |= 1 << 5;
4087
4088 /* There are more than suffix matches. */
4089 if (i.tm.opcode_modifier.w
9306ca4a 4090 || ((suffixes & (suffixes - 1))
40fb9820
L		 4091 && !i.tm.opcode_modifier.defaultsize
4092 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4093 {
4094 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4095 return 0;
4096 }
4097 }
29b0f896 4098 }
252b5132 4099
9306ca4a
JB		 4100 /* Change the opcode based on the operand size given by i.suffix;
4101 We don't need to change things for byte insns. */
4102
582d5edd
L		 4103 if (i.suffix
4104 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4105 && i.suffix != XMMWORD_MNEM_SUFFIX
4106 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4107 {
4108 /* It's not a byte, select word/dword operation. */
40fb9820 4109 if (i.tm.opcode_modifier.w)
29b0f896 4110 {
40fb9820 4111 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4112 i.tm.base_opcode |= 8;
4113 else
4114 i.tm.base_opcode |= 1;
4115 }
0f3f3d8b 4116
29b0f896
AM		 4117 /* Now select between word & dword operations via the operand
4118 size prefix, except for instructions that will ignore this
4119 prefix anyway. */
ca61edf2 4120 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4121 {
ca61edf2
L		 4122 /* The address size override prefix changes the size of the
4123 first operand. */
40fb9820
L		 4124 if ((flag_code == CODE_32BIT
4125 && i.op->regs[0].reg_type.bitfield.reg16)
4126 || (flag_code != CODE_32BIT
4127 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4128 if (!add_prefix (ADDR_PREFIX_OPCODE))
4129 return 0;
4130 }
4131 else if (i.suffix != QWORD_MNEM_SUFFIX
4132 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4133 && !i.tm.opcode_modifier.ignoresize
4134 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4135 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4136 || (flag_code == CODE_64BIT
40fb9820 4137 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4138 {
4139 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4140
40fb9820 4141 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4142 prefix = ADDR_PREFIX_OPCODE;
252b5132 4143
29b0f896
AM		 4144 if (!add_prefix (prefix))
4145 return 0;
24eab124 4146 }
252b5132 4147
29b0f896
AM		 4148 /* Set mode64 for an operand. */
4149 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4150 && flag_code == CODE_64BIT
40fb9820 4151 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4152 {
4153 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4154 need rex64. cmpxchg8b is also a special case. */
4155 if (! (i.operands == 2
4156 && i.tm.base_opcode == 0x90
4157 && i.tm.extension_opcode == None
0dfbf9d7
L		 4158 && operand_type_equal (&i.types [0], &acc64)
4159 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4160 && ! (i.operands == 1
4161 && i.tm.base_opcode == 0xfc7
4162 && i.tm.extension_opcode == 1
40fb9820
L		 4163 && !operand_type_check (i.types [0], reg)
4164 && operand_type_check (i.types [0], anymem)))
f6bee062 4165 i.rex |= REX_W;
46e883c5 4166 }
3e73aa7c 4167
29b0f896
AM		 4168 /* Size floating point instruction. */
4169 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4170 if (i.tm.opcode_modifier.floatmf)
543613e9 4171 i.tm.base_opcode ^= 4;
29b0f896 4172 }
7ecd2f8b 4173
29b0f896
AM		 4174 return 1;
4175}
3e73aa7c 4176
29b0f896 4177static int
543613e9 4178check_byte_reg (void)
29b0f896
AM		 4179{
4180 int op;
543613e9 4181
29b0f896
AM		 4182 for (op = i.operands; --op >= 0;)
4183 {
4184 /* If this is an eight bit register, it's OK. If it's the 16 or
4185 32 bit version of an eight bit register, we will just use the
4186 low portion, and that's OK too. */
40fb9820 4187 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4188 continue;
4189
ca61edf2
L		 4190 /* Don't generate this warning if not needed. */
4191 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
29b0f896
AM		 4192 continue;
4193
9344ff29
L		 4194 /* crc32 doesn't generate this warning. */
4195 if (i.tm.base_opcode == 0xf20f38f0)
4196 continue;
4197
40fb9820
L		 4198 if ((i.types[op].bitfield.reg16
4199 || i.types[op].bitfield.reg32
4200 || i.types[op].bitfield.reg64)
4201 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4202 {
4203 /* Prohibit these changes in the 64bit mode, since the
4204 lowering is more complicated. */
4205 if (flag_code == CODE_64BIT
40fb9820 4206 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4207 {
2ca3ace5
L		 4208 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4209 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4210 i.suffix);
4211 return 0;
4212 }
4213#if REGISTER_WARNINGS
4214 if (!quiet_warnings
40fb9820 4215 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4216 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4217 register_prefix,
40fb9820 4218 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4219 ? REGNAM_AL - REGNAM_AX
4220 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4221 register_prefix,
29b0f896
AM		 4222 i.op[op].regs->reg_name,
4223 i.suffix);
4224#endif
4225 continue;
4226 }
4227 /* Any other register is bad. */
40fb9820
L		 4228 if (i.types[op].bitfield.reg16
4229 || i.types[op].bitfield.reg32
4230 || i.types[op].bitfield.reg64
4231 || i.types[op].bitfield.regmmx
4232 || i.types[op].bitfield.regxmm
c0f3af97 4233 || i.types[op].bitfield.regymm
40fb9820
L		 4234 || i.types[op].bitfield.sreg2
4235 || i.types[op].bitfield.sreg3
4236 || i.types[op].bitfield.control
4237 || i.types[op].bitfield.debug
4238 || i.types[op].bitfield.test
4239 || i.types[op].bitfield.floatreg
4240 || i.types[op].bitfield.floatacc)
29b0f896 4241 {
a540244d
L		 4242 as_bad (_("`%s%s' not allowed with `%s%c'"),
4243 register_prefix,
29b0f896
AM		 4244 i.op[op].regs->reg_name,
4245 i.tm.name,
4246 i.suffix);
4247 return 0;
4248 }
4249 }
4250 return 1;
4251}
4252
4253static int
e3bb37b5 4254check_long_reg (void)
29b0f896
AM		 4255{
4256 int op;
4257
4258 for (op = i.operands; --op >= 0;)
4259 /* Reject eight bit registers, except where the template requires
4260 them. (eg. movzb) */
40fb9820
L		 4261 if (i.types[op].bitfield.reg8
4262 && (i.tm.operand_types[op].bitfield.reg16
4263 || i.tm.operand_types[op].bitfield.reg32
4264 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4265 {
a540244d
L		 4266 as_bad (_("`%s%s' not allowed with `%s%c'"),
4267 register_prefix,
29b0f896
AM		 4268 i.op[op].regs->reg_name,
4269 i.tm.name,
4270 i.suffix);
4271 return 0;
4272 }
4273 /* Warn if the e prefix on a general reg is missing. */
4274 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4275 && i.types[op].bitfield.reg16
4276 && (i.tm.operand_types[op].bitfield.reg32
4277 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4278 {
4279 /* Prohibit these changes in the 64bit mode, since the
4280 lowering is more complicated. */
4281 if (flag_code == CODE_64BIT)
252b5132 4282 {
2ca3ace5
L		 4283 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4284 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4285 i.suffix);
4286 return 0;
252b5132 4287 }
29b0f896
AM		 4288#if REGISTER_WARNINGS
4289 else
a540244d
L		 4290 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4291 register_prefix,
29b0f896 4292 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4293 register_prefix,
29b0f896
AM		 4294 i.op[op].regs->reg_name,
4295 i.suffix);
4296#endif
252b5132 4297 }
29b0f896 4298 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4299 else if (i.types[op].bitfield.reg64
4300 && (i.tm.operand_types[op].bitfield.reg32
4301 || i.tm.operand_types[op].bitfield.acc))
252b5132 4302 {
34828aad 4303 if (intel_syntax
ca61edf2 4304 && i.tm.opcode_modifier.toqword
40fb9820 4305 && !i.types[0].bitfield.regxmm)
34828aad 4306 {
ca61edf2 4307 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4308 i.suffix = QWORD_MNEM_SUFFIX;
4309 }
4310 else
4311 {
4312 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4313 register_prefix, i.op[op].regs->reg_name,
4314 i.suffix);
4315 return 0;
4316 }
29b0f896
AM		 4317 }
4318 return 1;
4319}
252b5132 4320
29b0f896 4321static int
e3bb37b5 4322check_qword_reg (void)
29b0f896
AM		 4323{
4324 int op;
252b5132 4325
29b0f896
AM		 4326 for (op = i.operands; --op >= 0; )
4327 /* Reject eight bit registers, except where the template requires
4328 them. (eg. movzb) */
40fb9820
L		 4329 if (i.types[op].bitfield.reg8
4330 && (i.tm.operand_types[op].bitfield.reg16
4331 || i.tm.operand_types[op].bitfield.reg32
4332 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4333 {
a540244d
L		 4334 as_bad (_("`%s%s' not allowed with `%s%c'"),
4335 register_prefix,
29b0f896
AM		 4336 i.op[op].regs->reg_name,
4337 i.tm.name,
4338 i.suffix);
4339 return 0;
4340 }
4341 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4342 else if ((i.types[op].bitfield.reg16
4343 || i.types[op].bitfield.reg32)
4344 && (i.tm.operand_types[op].bitfield.reg32
4345 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4346 {
4347 /* Prohibit these changes in the 64bit mode, since the
4348 lowering is more complicated. */
34828aad 4349 if (intel_syntax
ca61edf2 4350 && i.tm.opcode_modifier.todword
40fb9820 4351 && !i.types[0].bitfield.regxmm)
34828aad 4352 {
ca61edf2 4353 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4354 i.suffix = LONG_MNEM_SUFFIX;
4355 }
4356 else
4357 {
4358 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4359 register_prefix, i.op[op].regs->reg_name,
4360 i.suffix);
4361 return 0;
4362 }
252b5132 4363 }
29b0f896
AM		 4364 return 1;
4365}
252b5132 4366
29b0f896 4367static int
e3bb37b5 4368check_word_reg (void)
29b0f896
AM		 4369{
4370 int op;
4371 for (op = i.operands; --op >= 0;)
4372 /* Reject eight bit registers, except where the template requires
4373 them. (eg. movzb) */
40fb9820
L		 4374 if (i.types[op].bitfield.reg8
4375 && (i.tm.operand_types[op].bitfield.reg16
4376 || i.tm.operand_types[op].bitfield.reg32
4377 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4378 {
a540244d
L		 4379 as_bad (_("`%s%s' not allowed with `%s%c'"),
4380 register_prefix,
29b0f896
AM		 4381 i.op[op].regs->reg_name,
4382 i.tm.name,
4383 i.suffix);
4384 return 0;
4385 }
4386 /* Warn if the e prefix on a general reg is present. */
4387 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4388 && i.types[op].bitfield.reg32
4389 && (i.tm.operand_types[op].bitfield.reg16
4390 || i.tm.operand_types[op].bitfield.acc))
252b5132 4391 {
29b0f896
AM		 4392 /* Prohibit these changes in the 64bit mode, since the
4393 lowering is more complicated. */
4394 if (flag_code == CODE_64BIT)
252b5132 4395 {
2ca3ace5
L		 4396 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4397 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4398 i.suffix);
4399 return 0;
252b5132 4400 }
29b0f896
AM		 4401 else
4402#if REGISTER_WARNINGS
a540244d
L		 4403 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4404 register_prefix,
29b0f896 4405 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4406 register_prefix,
29b0f896
AM		 4407 i.op[op].regs->reg_name,
4408 i.suffix);
4409#endif
4410 }
4411 return 1;
4412}
252b5132 4413
29b0f896 4414static int
40fb9820 4415update_imm (unsigned int j)
29b0f896 4416{
40fb9820
L		 4417 i386_operand_type overlap;
4418
c6fb90c8 4419 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
40fb9820
L		 4420 if ((overlap.bitfield.imm8
4421 || overlap.bitfield.imm8s
4422 || overlap.bitfield.imm16
4423 || overlap.bitfield.imm32
4424 || overlap.bitfield.imm32s
4425 || overlap.bitfield.imm64)
0dfbf9d7
L		 4426 && !operand_type_equal (&overlap, &imm8)
4427 && !operand_type_equal (&overlap, &imm8s)
4428 && !operand_type_equal (&overlap, &imm16)
4429 && !operand_type_equal (&overlap, &imm32)
4430 && !operand_type_equal (&overlap, &imm32s)
4431 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4432 {
4433 if (i.suffix)
4434 {
40fb9820
L		 4435 i386_operand_type temp;
4436
0dfbf9d7 4437 operand_type_set (&temp, 0);
40fb9820
L		 4438 if (i.suffix == BYTE_MNEM_SUFFIX)
4439 {
4440 temp.bitfield.imm8 = overlap.bitfield.imm8;
4441 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4442 }
4443 else if (i.suffix == WORD_MNEM_SUFFIX)
4444 temp.bitfield.imm16 = overlap.bitfield.imm16;
4445 else if (i.suffix == QWORD_MNEM_SUFFIX)
4446 {
4447 temp.bitfield.imm64 = overlap.bitfield.imm64;
4448 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4449 }
4450 else
4451 temp.bitfield.imm32 = overlap.bitfield.imm32;
4452 overlap = temp;
29b0f896 4453 }
0dfbf9d7
L		 4454 else if (operand_type_equal (&overlap, &imm16_32_32s)
4455 || operand_type_equal (&overlap, &imm16_32)
4456 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4457 {
40fb9820 4458 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4459 overlap = imm16;
40fb9820 4460 else
65da13b5 4461 overlap = imm32s;
29b0f896 4462 }
0dfbf9d7
L		 4463 if (!operand_type_equal (&overlap, &imm8)
4464 && !operand_type_equal (&overlap, &imm8s)
4465 && !operand_type_equal (&overlap, &imm16)
4466 && !operand_type_equal (&overlap, &imm32)
4467 && !operand_type_equal (&overlap, &imm32s)
4468 && !operand_type_equal (&overlap, &imm64))
29b0f896 4469 {
4eed87de
AM		 4470 as_bad (_("no instruction mnemonic suffix given; "
4471 "can't determine immediate size"));
29b0f896
AM		 4472 return 0;
4473 }
4474 }
40fb9820 4475 i.types[j] = overlap;
29b0f896 4476
40fb9820
L		 4477 return 1;
4478}
4479
4480static int
4481finalize_imm (void)
4482{
4483 unsigned int j;
29b0f896 4484
40fb9820
L		 4485 for (j = 0; j < 2; j++)
4486 if (update_imm (j) == 0)
4487 return 0;
4488
c6fb90c8 4489 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
40fb9820 4490 assert (operand_type_check (i.types[2], imm) == 0);
29b0f896
AM		 4491
4492 return 1;
4493}
4494
85f10a01
MM		 4495static void
4496process_drex (void)
4497{
5dd15031
JJ		 4498 i.drex.modrm_reg = 0;
4499 i.drex.modrm_regmem = 0;
85f10a01
MM		 4500
4501 /* SSE5 4 operand instructions must have the destination the same as
4502 one of the inputs. Figure out the destination register and cache
4503 it away in the drex field, and remember which fields to use for
4504 the modrm byte. */
4505 if (i.tm.opcode_modifier.drex
4506 && i.tm.opcode_modifier.drexv
4507 && i.operands == 4)
4508 {
4509 i.tm.extension_opcode = None;
4510
4511 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4512 if (i.types[0].bitfield.regxmm != 0
4513 && i.types[1].bitfield.regxmm != 0
4514 && i.types[2].bitfield.regxmm != 0
4515 && i.types[3].bitfield.regxmm != 0
4516 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4517 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4518 {
4519 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4520 operand_type_set (&i.types[0], 0);
4521 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4522 i.reg_operands -= 2;
4523
4524 /* There are two different ways to encode a 4 operand
4525 instruction with all registers that uses OC1 set to
4526 0 or 1. Favor setting OC1 to 0 since this mimics the
4527 actions of other SSE5 assemblers. Use modrm encoding 2
4528 for register/register. Include the high order bit that
4529 is normally stored in the REX byte in the register
4530 field. */
4531 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4532 i.drex.modrm_reg = 2;
4533 i.drex.modrm_regmem = 1;
4534 i.drex.reg = (i.op[3].regs->reg_num
4535 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4536 }
4537
4538 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4539 else if (i.types[0].bitfield.regxmm != 0
4540 && i.types[1].bitfield.regxmm != 0
4541 && (i.types[2].bitfield.regxmm
4542 || operand_type_check (i.types[2], anymem))
4543 && i.types[3].bitfield.regxmm != 0
4544 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4545 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4546 {
4547 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4548 operand_type_set (&i.types[0], 0);
4549 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4550 i.reg_operands -= 2;
4551
4552 /* Specify the modrm encoding for memory addressing. Include
4553 the high order bit that is normally stored in the REX byte
4554 in the register field. */
4555 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
4556 i.drex.modrm_reg = 1;
4557 i.drex.modrm_regmem = 2;
4558 i.drex.reg = (i.op[3].regs->reg_num
4559 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4560 }
4561
4562 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4563 else if (i.types[0].bitfield.regxmm != 0
4564 && operand_type_check (i.types[1], anymem) != 0
4565 && i.types[2].bitfield.regxmm != 0
4566 && i.types[3].bitfield.regxmm != 0
4567 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4568 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4569 {
4570 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4571 operand_type_set (&i.types[0], 0);
4572 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4573 i.reg_operands -= 2;
4574
4575 /* Specify the modrm encoding for memory addressing. Include
4576 the high order bit that is normally stored in the REX byte
4577 in the register field. */
4578 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4579 i.drex.modrm_reg = 2;
4580 i.drex.modrm_regmem = 1;
4581 i.drex.reg = (i.op[3].regs->reg_num
4582 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4583 }
4584
4585 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4586 else if (i.types[0].bitfield.regxmm != 0
4587 && i.types[1].bitfield.regxmm != 0
4588 && i.types[2].bitfield.regxmm != 0
4589 && i.types[3].bitfield.regxmm != 0
4590 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4591 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4592 {
4593 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4594 operand_type_set (&i.types[2], 0);
4595 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4596 i.reg_operands -= 2;
4597
4598 /* There are two different ways to encode a 4 operand
4599 instruction with all registers that uses OC1 set to
4600 0 or 1. Favor setting OC1 to 0 since this mimics the
4601 actions of other SSE5 assemblers. Use modrm encoding
4602 2 for register/register. Include the high order bit that
4603 is normally stored in the REX byte in the register
4604 field. */
4605 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4606 i.drex.modrm_reg = 1;
4607 i.drex.modrm_regmem = 0;
4608
4609 /* Remember the register, including the upper bits */
4610 i.drex.reg = (i.op[3].regs->reg_num
4611 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4612 }
4613
4614 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4615 else if (i.types[0].bitfield.regxmm != 0
4616 && (i.types[1].bitfield.regxmm
4617 || operand_type_check (i.types[1], anymem))
4618 && i.types[2].bitfield.regxmm != 0
4619 && i.types[3].bitfield.regxmm != 0
4620 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4621 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4622 {
4623 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4624 operand_type_set (&i.types[2], 0);
4625 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4626 i.reg_operands -= 2;
4627
4628 /* Specify the modrm encoding and remember the register
4629 including the bits normally stored in the REX byte. */
4630 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4631 i.drex.modrm_reg = 0;
4632 i.drex.modrm_regmem = 1;
4633 i.drex.reg = (i.op[3].regs->reg_num
4634 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4635 }
4636
4637 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4638 else if (operand_type_check (i.types[0], anymem) != 0
4639 && i.types[1].bitfield.regxmm != 0
4640 && i.types[2].bitfield.regxmm != 0
4641 && i.types[3].bitfield.regxmm != 0
4642 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4643 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4644 {
4645 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4646 operand_type_set (&i.types[2], 0);
4647 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4648 i.reg_operands -= 2;
4649
4650 /* Specify the modrm encoding and remember the register
4651 including the bits normally stored in the REX byte. */
4652 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4653 i.drex.modrm_reg = 1;
4654 i.drex.modrm_regmem = 0;
4655 i.drex.reg = (i.op[3].regs->reg_num
4656 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4657 }
4658
4659 else
4660 as_bad (_("Incorrect operands for the '%s' instruction"),
4661 i.tm.name);
4662 }
4663
4664 /* SSE5 instructions with the DREX byte where the only memory operand
4665 is in the 2nd argument, and the first and last xmm register must
4666 match, and is encoded in the DREX byte. */
4667 else if (i.tm.opcode_modifier.drex
4668 && !i.tm.opcode_modifier.drexv
4669 && i.operands == 4)
4670 {
4671 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4672 if (i.types[0].bitfield.regxmm != 0
4673 && (i.types[1].bitfield.regxmm
4674 || operand_type_check(i.types[1], anymem))
4675 && i.types[2].bitfield.regxmm != 0
4676 && i.types[3].bitfield.regxmm != 0
4677 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4678 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4679 {
4680 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4681 operand_type_set (&i.types[0], 0);
4682 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4683 i.reg_operands -= 2;
4684
4685 /* Specify the modrm encoding and remember the register
4686 including the high bit normally stored in the REX
4687 byte. */
4688 i.drex.modrm_reg = 2;
4689 i.drex.modrm_regmem = 1;
4690 i.drex.reg = (i.op[3].regs->reg_num
4691 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4692 }
4693
4694 else
4695 as_bad (_("Incorrect operands for the '%s' instruction"),
4696 i.tm.name);
4697 }
4698
4699 /* SSE5 3 operand instructions that the result is a register, being
4700 either operand can be a memory operand, using OC0 to note which
4701 one is the memory. */
4702 else if (i.tm.opcode_modifier.drex
4703 && i.tm.opcode_modifier.drexv
4704 && i.operands == 3)
4705 {
4706 i.tm.extension_opcode = None;
4707
4708 /* Case 1: 3 operand insn, src1 = register. */
4709 if (i.types[0].bitfield.regxmm != 0
4710 && i.types[1].bitfield.regxmm != 0
4711 && i.types[2].bitfield.regxmm != 0)
4712 {
4713 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4714 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4715 i.reg_operands--;
4716
4717 /* Specify the modrm encoding and remember the register
4718 including the high bit normally stored in the REX byte. */
4719 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4720 i.drex.modrm_reg = 1;
4721 i.drex.modrm_regmem = 0;
4722 i.drex.reg = (i.op[2].regs->reg_num
4723 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4724 }
4725
4726 /* Case 2: 3 operand insn, src1 = memory. */
4727 else if (operand_type_check (i.types[0], anymem) != 0
4728 && i.types[1].bitfield.regxmm != 0
4729 && i.types[2].bitfield.regxmm != 0)
4730 {
4731 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4732 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4733 i.reg_operands--;
4734
4735 /* Specify the modrm encoding and remember the register
4736 including the high bit normally stored in the REX
4737 byte. */
4738 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4739 i.drex.modrm_reg = 1;
4740 i.drex.modrm_regmem = 0;
4741 i.drex.reg = (i.op[2].regs->reg_num
4742 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4743 }
4744
4745 /* Case 3: 3 operand insn, src2 = memory. */
4746 else if (i.types[0].bitfield.regxmm != 0
4747 && operand_type_check (i.types[1], anymem) != 0
4748 && i.types[2].bitfield.regxmm != 0)
4749 {
4750 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4751 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4752 i.reg_operands--;
4753
4754 /* Specify the modrm encoding and remember the register
4755 including the high bit normally stored in the REX byte. */
4756 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4757 i.drex.modrm_reg = 0;
4758 i.drex.modrm_regmem = 1;
4759 i.drex.reg = (i.op[2].regs->reg_num
4760 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4761 }
4762
4763 else
4764 as_bad (_("Incorrect operands for the '%s' instruction"),
4765 i.tm.name);
4766 }
4767
4768 /* SSE5 4 operand instructions that are the comparison instructions
4769 where the first operand is the immediate value of the comparison
4770 to be done. */
4771 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4772 {
4773 /* Case 1: 4 operand insn, src1 = reg/memory. */
4774 if (operand_type_check (i.types[0], imm) != 0
4775 && (i.types[1].bitfield.regxmm
4776 || operand_type_check (i.types[1], anymem))
4777 && i.types[2].bitfield.regxmm != 0
4778 && i.types[3].bitfield.regxmm != 0)
4779 {
4780 /* clear the arguments that are stored in drex */
0dfbf9d7 4781 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4782 i.reg_operands--;
4783
4784 /* Specify the modrm encoding and remember the register
4785 including the high bit normally stored in the REX byte. */
4786 i.drex.modrm_reg = 2;
4787 i.drex.modrm_regmem = 1;
4788 i.drex.reg = (i.op[3].regs->reg_num
4789 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4790 }
4791
4792 /* Case 2: 3 operand insn with ImmExt that places the
4793 opcode_extension as an immediate argument. This is used for
4794 all of the varients of comparison that supplies the appropriate
4795 value as part of the instruction. */
4796 else if ((i.types[0].bitfield.regxmm
4797 || operand_type_check (i.types[0], anymem))
4798 && i.types[1].bitfield.regxmm != 0
4799 && i.types[2].bitfield.regxmm != 0
4800 && operand_type_check (i.types[3], imm) != 0)
4801 {
4802 /* clear the arguments that are stored in drex */
0dfbf9d7 4803 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4804 i.reg_operands--;
4805
4806 /* Specify the modrm encoding and remember the register
4807 including the high bit normally stored in the REX byte. */
4808 i.drex.modrm_reg = 1;
4809 i.drex.modrm_regmem = 0;
4810 i.drex.reg = (i.op[2].regs->reg_num
4811 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4812 }
4813
4814 else
4815 as_bad (_("Incorrect operands for the '%s' instruction"),
4816 i.tm.name);
4817 }
4818
4819 else if (i.tm.opcode_modifier.drex
4820 || i.tm.opcode_modifier.drexv
4821 || i.tm.opcode_modifier.drexc)
4822 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4823}
4824
c0f3af97
L		 4825static int
4826bad_implicit_operand (int xmm)
4827{
4828 const char *reg = xmm ? "xmm0" : "ymm0";
4829 if (intel_syntax)
4830 as_bad (_("the last operand of `%s' must be `%s%s'"),
4831 i.tm.name, register_prefix, reg);
4832 else
4833 as_bad (_("the first operand of `%s' must be `%s%s'"),
4834 i.tm.name, register_prefix, reg);
4835 return 0;
4836}
4837
29b0f896 4838static int
e3bb37b5 4839process_operands (void)
29b0f896
AM		 4840{
4841 /* Default segment register this instruction will use for memory
4842 accesses. 0 means unknown. This is only for optimizing out
4843 unnecessary segment overrides. */
4844 const seg_entry *default_seg = 0;
4845
85f10a01
MM		 4846 /* Handle all of the DREX munging that SSE5 needs. */
4847 if (i.tm.opcode_modifier.drex
4848 || i.tm.opcode_modifier.drexv
4849 || i.tm.opcode_modifier.drexc)
4850 process_drex ();
4851
c0f3af97
L		 4852 if (i.tm.opcode_modifier.sse2avx
4853 && (i.tm.opcode_modifier.vexnds
4854 || i.tm.opcode_modifier.vexndd))
29b0f896 4855 {
c0f3af97
L		 4856 unsigned int dup = i.operands;
4857 unsigned int dest = dup - 1;
9fcfb3d7
L		 4858 unsigned int j;
4859
c0f3af97 4860 /* The destination must be an xmm register. */
0dfbf9d7 4861 assert (i.reg_operands
c0f3af97
L		 4862 && MAX_OPERANDS > dup
4863 && operand_type_equal (&i.types[dest], &regxmm));
4864
4865 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4866 {
c0f3af97
L		 4867 /* The first operand is implicit and must be xmm0. */
4868 assert (operand_type_equal (&i.types[0], &regxmm));
4869 if (i.op[0].regs->reg_num != 0)
4870 return bad_implicit_operand (1);
4871
4872 if (i.tm.opcode_modifier.vex3sources)
4873 {
4874 /* Keep xmm0 for instructions with VEX prefix and 3
4875 sources. */
4876 goto duplicate;
4877 }
e2ec9d29 4878 else
c0f3af97
L		 4879 {
4880 /* We remove the first xmm0 and keep the number of
4881 operands unchanged, which in fact duplicates the
4882 destination. */
4883 for (j = 1; j < i.operands; j++)
4884 {
4885 i.op[j - 1] = i.op[j];
4886 i.types[j - 1] = i.types[j];
4887 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4888 }
4889 }
4890 }
4891 else if (i.tm.opcode_modifier.implicit1stxmm0)
4892 {
4893 assert ((MAX_OPERANDS - 1) > dup
4894 && i.tm.opcode_modifier.vex3sources);
4895
4896 /* Add the implicit xmm0 for instructions with VEX prefix
4897 and 3 sources. */
4898 for (j = i.operands; j > 0; j--)
4899 {
4900 i.op[j] = i.op[j - 1];
4901 i.types[j] = i.types[j - 1];
4902 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4903 }
4904 i.op[0].regs
4905 = (const reg_entry *) hash_find (reg_hash, "xmm0");
4906 i.types[0] = regxmm;
4907 i.tm.operand_types[0] = regxmm;
4908
4909 i.operands += 2;
4910 i.reg_operands += 2;
4911 i.tm.operands += 2;
4912
4913 dup++;
4914 dest++;
4915 i.op[dup] = i.op[dest];
4916 i.types[dup] = i.types[dest];
4917 i.tm.operand_types[dup] = i.tm.operand_types[dest];
e2ec9d29 4918 }
c0f3af97
L		 4919 else
4920 {
4921duplicate:
4922 i.operands++;
4923 i.reg_operands++;
4924 i.tm.operands++;
4925
4926 i.op[dup] = i.op[dest];
4927 i.types[dup] = i.types[dest];
4928 i.tm.operand_types[dup] = i.tm.operand_types[dest];
4929 }
4930
4931 if (i.tm.opcode_modifier.immext)
4932 process_immext ();
4933 }
4934 else if (i.tm.opcode_modifier.firstxmm0)
4935 {
4936 unsigned int j;
4937
4938 /* The first operand is implicit and must be xmm0/ymm0. */
4939 assert (i.reg_operands
4940 && (operand_type_equal (&i.types[0], &regxmm)
4941 || operand_type_equal (&i.types[0], &regymm)));
4942 if (i.op[0].regs->reg_num != 0)
4943 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 4944
4945 for (j = 1; j < i.operands; j++)
4946 {
4947 i.op[j - 1] = i.op[j];
4948 i.types[j - 1] = i.types[j];
4949
4950 /* We need to adjust fields in i.tm since they are used by
4951 build_modrm_byte. */
4952 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4953 }
4954
e2ec9d29
L		 4955 i.operands--;
4956 i.reg_operands--;
e2ec9d29
L		 4957 i.tm.operands--;
4958 }
4959 else if (i.tm.opcode_modifier.regkludge)
4960 {
4961 /* The imul $imm, %reg instruction is converted into
4962 imul $imm, %reg, %reg, and the clr %reg instruction
4963 is converted into xor %reg, %reg. */
4964
4965 unsigned int first_reg_op;
4966
4967 if (operand_type_check (i.types[0], reg))
4968 first_reg_op = 0;
4969 else
4970 first_reg_op = 1;
4971 /* Pretend we saw the extra register operand. */
4972 assert (i.reg_operands == 1
4973 && i.op[first_reg_op + 1].regs == 0);
4974 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4975 i.types[first_reg_op + 1] = i.types[first_reg_op];
4976 i.operands++;
4977 i.reg_operands++;
29b0f896
AM		 4978 }
4979
40fb9820 4980 if (i.tm.opcode_modifier.shortform)
29b0f896 4981 {
40fb9820
L		 4982 if (i.types[0].bitfield.sreg2
4983 || i.types[0].bitfield.sreg3)
29b0f896 4984 {
4eed87de
AM		 4985 if (i.tm.base_opcode == POP_SEG_SHORT
4986 && i.op[0].regs->reg_num == 1)
29b0f896 4987 {
a87af027 4988 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 4989 return 0;
29b0f896 4990 }
4eed87de
AM		 4991 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4992 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4993 i.rex |= REX_B;
4eed87de
AM		 4994 }
4995 else
4996 {
85f10a01
MM		 4997 /* The register or float register operand is in operand
4998 0 or 1. */
40fb9820
L		 4999 unsigned int op;
5000
5001 if (i.types[0].bitfield.floatreg
5002 || operand_type_check (i.types[0], reg))
5003 op = 0;
5004 else
5005 op = 1;
4eed87de
AM		 5006 /* Register goes in low 3 bits of opcode. */
5007 i.tm.base_opcode |= i.op[op].regs->reg_num;
5008 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5009 i.rex |= REX_B;
40fb9820 5010 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5011 {
4eed87de
AM		 5012 /* Warn about some common errors, but press on regardless.
5013 The first case can be generated by gcc (<= 2.8.1). */
5014 if (i.operands == 2)
5015 {
5016 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 5017 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
5018 register_prefix, i.op[1].regs->reg_name,
5019 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 5020 }
5021 else
5022 {
5023 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5024 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5025 register_prefix, i.op[0].regs->reg_name);
4eed87de 5026 }
29b0f896
AM		 5027 }
5028 }
5029 }
40fb9820 5030 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5031 {
5032 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5033 must be put into the modrm byte). Now, we make the modrm and
5034 index base bytes based on all the info we've collected. */
29b0f896
AM		 5035
5036 default_seg = build_modrm_byte ();
5037 }
8a2ed489 5038 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5039 {
5040 default_seg = &ds;
5041 }
40fb9820 5042 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5043 {
5044 /* For the string instructions that allow a segment override
5045 on one of their operands, the default segment is ds. */
5046 default_seg = &ds;
5047 }
5048
75178d9d
L		 5049 if (i.tm.base_opcode == 0x8d /* lea */
5050 && i.seg[0]
5051 && !quiet_warnings)
30123838 5052 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5053
5054 /* If a segment was explicitly specified, and the specified segment
5055 is not the default, use an opcode prefix to select it. If we
5056 never figured out what the default segment is, then default_seg
5057 will be zero at this point, and the specified segment prefix will
5058 always be used. */
29b0f896
AM		 5059 if ((i.seg[0]) && (i.seg[0] != default_seg))
5060 {
5061 if (!add_prefix (i.seg[0]->seg_prefix))
5062 return 0;
5063 }
5064 return 1;
5065}
5066
5067static const seg_entry *
e3bb37b5 5068build_modrm_byte (void)
29b0f896
AM		 5069{
5070 const seg_entry *default_seg = 0;
c0f3af97
L		 5071 unsigned int source, dest;
5072 int vex_3_sources;
5073
5074 /* The first operand of instructions with VEX prefix and 3 sources
5075 must be VEX_Imm4. */
5076 vex_3_sources = i.tm.opcode_modifier.vex3sources;
5077 if (vex_3_sources)
5078 {
5079 unsigned int nds, reg;
5080
5081 if (i.tm.opcode_modifier.veximmext
5082 && i.tm.opcode_modifier.immext)
5083 {
5084 dest = i.operands - 2;
5085 assert (dest == 3);
5086 }
5087 else
5088 dest = i.operands - 1;
5089 nds = dest - 1;
5090
5091 /* There are 2 kinds of instructions:
dae39acc 5092 1. 5 operands: one immediate operand and 4 register
c0f3af97
L		 5093 operands or 3 register operands plus 1 memory operand.
5094 It must have VexNDS and VexW0 or VexW1. The destination
5095 must be either XMM or YMM register.
5096 2. 4 operands: 4 register operands or 3 register operands
5097 plus 1 memory operand. It must have VexNDS and VexImmExt. */
5098 if (!((i.reg_operands == 4
5099 || (i.reg_operands == 3 && i.mem_operands == 1))
5100 && i.tm.opcode_modifier.vexnds
5101 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
5102 || operand_type_equal (&i.tm.operand_types[dest], &regymm))
c0f3af97
L		 5103 && ((dest == 4
5104 && i.imm_operands == 1
5105 && i.types[0].bitfield.vex_imm4
5106 && (i.tm.opcode_modifier.vexw0
5107 || i.tm.opcode_modifier.vexw1))
5108 || (dest == 3
5109 && (i.imm_operands == 0
5110 || (i.imm_operands == 1
5111 && i.tm.opcode_modifier.immext))
5112 && i.tm.opcode_modifier.veximmext))))
5113 abort ();
5114
c0f3af97
L		 5115 if (i.imm_operands == 0)
5116 {
5117 /* When there is no immediate operand, generate an 8bit
5118 immediate operand to encode the first operand. */
5119 expressionS *exp = &im_expressions[i.imm_operands++];
5120 i.op[i.operands].imms = exp;
5121 i.types[i.operands] = imm8;
5122 i.operands++;
5123 /* If VexW1 is set, the first operand is the source and
5124 the second operand is encoded in the immediate operand. */
5125 if (i.tm.opcode_modifier.vexw1)
5126 {
5127 source = 0;
5128 reg = 1;
5129 }
5130 else
5131 {
5132 source = 1;
5133 reg = 0;
5134 }
dae39acc
L		 5135
5136 /* FMA swaps REG and NDS. */
5137 if (i.tm.cpu_flags.bitfield.cpufma)
5138 {
5139 unsigned int tmp;
5140 tmp = reg;
5141 reg = nds;
5142 nds = tmp;
5143 }
5144
c0f3af97
L		 5145 assert (operand_type_equal (&i.tm.operand_types[reg], &regxmm)
5146 || operand_type_equal (&i.tm.operand_types[reg],
5147 &regymm));
5148 exp->X_op = O_constant;
5149 exp->X_add_number
5150 = ((i.op[reg].regs->reg_num
5151 + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
5152 }
5153 else
5154 {
5155 unsigned int imm;
5156
5157 if (i.tm.opcode_modifier.vexw0)
5158 {
5159 /* If VexW0 is set, the third operand is the source and
5160 the second operand is encoded in the immediate
5161 operand. */
5162 source = 2;
5163 reg = 1;
5164 }
5165 else
5166 {
5167 /* VexW1 is set, the second operand is the source and
5168 the third operand is encoded in the immediate
5169 operand. */
5170 source = 1;
5171 reg = 2;
5172 }
5173
5174 if (i.tm.opcode_modifier.immext)
5175 {
5176 /* When ImmExt is set, the immdiate byte is the last
5177 operand. */
5178 imm = i.operands - 1;
5179 source--;
5180 reg--;
5181 }
5182 else
5183 {
5184 imm = 0;
5185
5186 /* Turn on Imm8 so that output_imm will generate it. */
5187 i.types[imm].bitfield.imm8 = 1;
5188 }
5189
5190 assert (operand_type_equal (&i.tm.operand_types[reg], &regxmm)
5191 || operand_type_equal (&i.tm.operand_types[reg],
5192 &regymm));
5193 i.op[imm].imms->X_add_number
5194 |= ((i.op[reg].regs->reg_num
5195 + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
5196 }
dae39acc
L		 5197
5198 assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
5199 || operand_type_equal (&i.tm.operand_types[nds], &regymm));
5200 i.vex.register_specifier = i.op[nds].regs;
5201
c0f3af97
L		 5202 }
5203 else
5204 source = dest = 0;
29b0f896 5205
85f10a01
MM		 5206 /* SSE5 4 operand instructions are encoded in such a way that one of
5207 the inputs must match the destination register. Process_drex hides
5208 the 3rd argument in the drex field, so that by the time we get
5209 here, it looks to GAS as if this is a 2 operand instruction. */
5210 if ((i.tm.opcode_modifier.drex
5211 || i.tm.opcode_modifier.drexv
b5016f89 5212 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 5213 && i.reg_operands == 2)
5214 {
5215 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
5216 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
5217
5218 i.rm.reg = reg->reg_num;
5219 i.rm.regmem = regmem->reg_num;
5220 i.rm.mode = 3;
5221 if ((reg->reg_flags & RegRex) != 0)
5222 i.rex |= REX_R;
5223 if ((regmem->reg_flags & RegRex) != 0)
5224 i.rex |= REX_B;
5225 }
5226
29b0f896 5227 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5228 implicit registers do not count. If there are 3 register
5229 operands, it must be a instruction with VexNDS. For a
5230 instruction with VexNDD, the destination register is encoded
5231 in VEX prefix. If there are 4 register operands, it must be
5232 a instruction with VEX prefix and 3 sources. */
5233 else if (i.mem_operands == 0
5234 && ((i.reg_operands == 2
5235 && !i.tm.opcode_modifier.vexndd)
5236 || (i.reg_operands == 3
5237 && i.tm.opcode_modifier.vexnds)
5238 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5239 {
cab737b9
L		 5240 switch (i.operands)
5241 {
5242 case 2:
5243 source = 0;
5244 break;
5245 case 3:
c81128dc
L		 5246 /* When there are 3 operands, one of them may be immediate,
5247 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5248 the first operand must be shift count register (cl) or it
5249 is an instruction with VexNDS. */
c81128dc
L		 5250 assert (i.imm_operands == 1
5251 || (i.imm_operands == 0
c0f3af97
L		 5252 && (i.tm.opcode_modifier.vexnds
5253 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5254 if (operand_type_check (i.types[0], imm)
5255 || i.types[0].bitfield.shiftcount)
5256 source = 1;
5257 else
5258 source = 0;
cab737b9
L		 5259 break;
5260 case 4:
368d64cc
L		 5261 /* When there are 4 operands, the first two must be 8bit
5262 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5263 one.
5264
5265 For instructions with VexNDS, if the first operand
5266 an imm8, the source operand is the 2nd one. If the last
5267 operand is imm8, the source operand is the first one. */
5268 assert ((i.imm_operands == 2
5269 && i.types[0].bitfield.imm8
5270 && i.types[1].bitfield.imm8)
5271 || (i.tm.opcode_modifier.vexnds
5272 && i.imm_operands == 1
5273 && (i.types[0].bitfield.imm8
5274 || i.types[i.operands - 1].bitfield.imm8)));
5275 if (i.tm.opcode_modifier.vexnds)
5276 {
5277 if (i.types[0].bitfield.imm8)
5278 source = 1;
5279 else
5280 source = 0;
5281 }
5282 else
5283 source = 2;
5284 break;
5285 case 5:
cab737b9
L		 5286 break;
5287 default:
5288 abort ();
5289 }
5290
c0f3af97
L		 5291 if (!vex_3_sources)
5292 {
5293 dest = source + 1;
5294
5295 if (i.tm.opcode_modifier.vexnds)
5296 {
5297 /* For instructions with VexNDS, the register-only
5298 source operand must be XMM or YMM register. It is
5299 encoded in VEX prefix. */
5300 if ((dest + 1) >= i.operands
5301 || (!operand_type_equal (&i.tm.operand_types[dest],
5302 &regxmm)
5303 && !operand_type_equal (&i.tm.operand_types[dest],
5304 &regymm)))
5305 abort ();
5306 i.vex.register_specifier = i.op[dest].regs;
5307 dest++;
5308 }
5309 }
29b0f896
AM		 5310
5311 i.rm.mode = 3;
5312 /* One of the register operands will be encoded in the i.tm.reg
5313 field, the other in the combined i.tm.mode and i.tm.regmem
5314 fields. If no form of this instruction supports a memory
5315 destination operand, then we assume the source operand may
5316 sometimes be a memory operand and so we need to store the
5317 destination in the i.rm.reg field. */
40fb9820
L		 5318 if (!i.tm.operand_types[dest].bitfield.regmem
5319 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5320 {
5321 i.rm.reg = i.op[dest].regs->reg_num;
5322 i.rm.regmem = i.op[source].regs->reg_num;
5323 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5324 i.rex |= REX_R;
29b0f896 5325 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5326 i.rex |= REX_B;
29b0f896
AM		 5327 }
5328 else
5329 {
5330 i.rm.reg = i.op[source].regs->reg_num;
5331 i.rm.regmem = i.op[dest].regs->reg_num;
5332 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5333 i.rex |= REX_B;
29b0f896 5334 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5335 i.rex |= REX_R;
29b0f896 5336 }
161a04f6 5337 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5338 {
40fb9820
L		 5339 if (!i.types[0].bitfield.control
5340 && !i.types[1].bitfield.control)
c4a530c5 5341 abort ();
161a04f6 5342 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5343 add_prefix (LOCK_PREFIX_OPCODE);
5344 }
29b0f896
AM		 5345 }
5346 else
5347 { /* If it's not 2 reg operands... */
c0f3af97
L		 5348 unsigned int mem;
5349
29b0f896
AM		 5350 if (i.mem_operands)
5351 {
5352 unsigned int fake_zero_displacement = 0;
99018f42 5353 unsigned int op;
4eed87de 5354
85f10a01
MM		 5355 /* This has been precalculated for SSE5 instructions
5356 that have a DREX field earlier in process_drex. */
b5016f89
L		 5357 if (i.tm.opcode_modifier.drex
5358 || i.tm.opcode_modifier.drexv
5359 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 5360 op = i.drex.modrm_regmem;
5361 else
5362 {
c0209578
L		 5363 for (op = 0; op < i.operands; op++)
5364 if (operand_type_check (i.types[op], anymem))
5365 break;
5366 assert (op < i.operands);
85f10a01 5367 }
29b0f896
AM		 5368
5369 default_seg = &ds;
5370
5371 if (i.base_reg == 0)
5372 {
5373 i.rm.mode = 0;
5374 if (!i.disp_operands)
5375 fake_zero_displacement = 1;
5376 if (i.index_reg == 0)
5377 {
5378 /* Operand is just <disp> */
20f0a1fc 5379 if (flag_code == CODE_64BIT)
29b0f896
AM		 5380 {
5381 /* 64bit mode overwrites the 32bit absolute
5382 addressing by RIP relative addressing and
5383 absolute addressing is encoded by one of the
5384 redundant SIB forms. */
5385 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5386 i.sib.base = NO_BASE_REGISTER;
5387 i.sib.index = NO_INDEX_REGISTER;
fc225355 5388 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5389 ? disp32s : disp32);
20f0a1fc 5390 }
fc225355
L		 5391 else if ((flag_code == CODE_16BIT)
5392 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5393 {
5394 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5395 i.types[op] = disp16;
20f0a1fc
NC		 5396 }
5397 else
5398 {
5399 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5400 i.types[op] = disp32;
29b0f896
AM		 5401 }
5402 }
5403 else /* !i.base_reg && i.index_reg */
5404 {
db51cc60
L		 5405 if (i.index_reg->reg_num == RegEiz
5406 || i.index_reg->reg_num == RegRiz)
5407 i.sib.index = NO_INDEX_REGISTER;
5408 else
5409 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5410 i.sib.base = NO_BASE_REGISTER;
5411 i.sib.scale = i.log2_scale_factor;
5412 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5413 i.types[op].bitfield.disp8 = 0;
5414 i.types[op].bitfield.disp16 = 0;
5415 i.types[op].bitfield.disp64 = 0;
29b0f896 5416 if (flag_code != CODE_64BIT)
40fb9820
L		 5417 {
5418 /* Must be 32 bit */
5419 i.types[op].bitfield.disp32 = 1;
5420 i.types[op].bitfield.disp32s = 0;
5421 }
29b0f896 5422 else
40fb9820
L		 5423 {
5424 i.types[op].bitfield.disp32 = 0;
5425 i.types[op].bitfield.disp32s = 1;
5426 }
29b0f896 5427 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5428 i.rex |= REX_X;
29b0f896
AM		 5429 }
5430 }
5431 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5432 else if (i.base_reg->reg_num == RegRip ||
5433 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5434 {
5435 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5436 i.types[op].bitfield.disp8 = 0;
5437 i.types[op].bitfield.disp16 = 0;
5438 i.types[op].bitfield.disp32 = 0;
5439 i.types[op].bitfield.disp32s = 1;
5440 i.types[op].bitfield.disp64 = 0;
71903a11 5441 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5442 if (! i.disp_operands)
5443 fake_zero_displacement = 1;
29b0f896 5444 }
40fb9820 5445 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5446 {
5447 switch (i.base_reg->reg_num)
5448 {
5449 case 3: /* (%bx) */
5450 if (i.index_reg == 0)
5451 i.rm.regmem = 7;
5452 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5453 i.rm.regmem = i.index_reg->reg_num - 6;
5454 break;
5455 case 5: /* (%bp) */
5456 default_seg = &ss;
5457 if (i.index_reg == 0)
5458 {
5459 i.rm.regmem = 6;
40fb9820 5460 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5461 {
5462 /* fake (%bp) into 0(%bp) */
40fb9820 5463 i.types[op].bitfield.disp8 = 1;
252b5132 5464 fake_zero_displacement = 1;
29b0f896
AM		 5465 }
5466 }
5467 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5468 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5469 break;
5470 default: /* (%si) -> 4 or (%di) -> 5 */
5471 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5472 }
5473 i.rm.mode = mode_from_disp_size (i.types[op]);
5474 }
5475 else /* i.base_reg and 32/64 bit mode */
5476 {
5477 if (flag_code == CODE_64BIT
40fb9820
L		 5478 && operand_type_check (i.types[op], disp))
5479 {
5480 i386_operand_type temp;
0dfbf9d7 5481 operand_type_set (&temp, 0);
40fb9820
L		 5482 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5483 i.types[op] = temp;
5484 if (i.prefix[ADDR_PREFIX] == 0)
5485 i.types[op].bitfield.disp32s = 1;
5486 else
5487 i.types[op].bitfield.disp32 = 1;
5488 }
20f0a1fc 5489
29b0f896
AM		 5490 i.rm.regmem = i.base_reg->reg_num;
5491 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5492 i.rex |= REX_B;
29b0f896
AM		 5493 i.sib.base = i.base_reg->reg_num;
5494 /* x86-64 ignores REX prefix bit here to avoid decoder
5495 complications. */
5496 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5497 {
5498 default_seg = &ss;
5499 if (i.disp_operands == 0)
5500 {
5501 fake_zero_displacement = 1;
40fb9820 5502 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5503 }
5504 }
5505 else if (i.base_reg->reg_num == ESP_REG_NUM)
5506 {
5507 default_seg = &ss;
5508 }
5509 i.sib.scale = i.log2_scale_factor;
5510 if (i.index_reg == 0)
5511 {
5512 /* <disp>(%esp) becomes two byte modrm with no index
5513 register. We've already stored the code for esp
5514 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5515 Any base register besides %esp will not use the
5516 extra modrm byte. */
5517 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5518 }
5519 else
5520 {
db51cc60
L		 5521 if (i.index_reg->reg_num == RegEiz
5522 || i.index_reg->reg_num == RegRiz)
5523 i.sib.index = NO_INDEX_REGISTER;
5524 else
5525 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5526 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5527 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5528 i.rex |= REX_X;
29b0f896 5529 }
67a4f2b7
AO		 5530
5531 if (i.disp_operands
5532 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5533 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5534 i.rm.mode = 0;
5535 else
5536 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5537 }
252b5132 5538
29b0f896
AM		 5539 if (fake_zero_displacement)
5540 {
5541 /* Fakes a zero displacement assuming that i.types[op]
5542 holds the correct displacement size. */
5543 expressionS *exp;
5544
5545 assert (i.op[op].disps == 0);
5546 exp = &disp_expressions[i.disp_operands++];
5547 i.op[op].disps = exp;
5548 exp->X_op = O_constant;
5549 exp->X_add_number = 0;
5550 exp->X_add_symbol = (symbolS *) 0;
5551 exp->X_op_symbol = (symbolS *) 0;
5552 }
c0f3af97
L		 5553
5554 mem = op;
29b0f896 5555 }
c0f3af97
L		 5556 else
5557 mem = ~0;
252b5132 5558
29b0f896
AM		 5559 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5560 (if any) based on i.tm.extension_opcode. Again, we must be
5561 careful to make sure that segment/control/debug/test/MMX
5562 registers are coded into the i.rm.reg field. */
5563 if (i.reg_operands)
5564 {
99018f42
L		 5565 unsigned int op;
5566
85f10a01
MM		 5567 /* This has been precalculated for SSE5 instructions
5568 that have a DREX field earlier in process_drex. */
b5016f89
L		 5569 if (i.tm.opcode_modifier.drex
5570 || i.tm.opcode_modifier.drexv
5571 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 5572 {
5573 op = i.drex.modrm_reg;
5574 i.rm.reg = i.op[op].regs->reg_num;
5575 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5576 i.rex |= REX_R;
5577 }
5578 else
5579 {
c0f3af97
L		 5580 unsigned int vex_reg = ~0;
5581
c0209578
L		 5582 for (op = 0; op < i.operands; op++)
5583 if (i.types[op].bitfield.reg8
5584 || i.types[op].bitfield.reg16
5585 || i.types[op].bitfield.reg32
5586 || i.types[op].bitfield.reg64
5587 || i.types[op].bitfield.regmmx
5588 || i.types[op].bitfield.regxmm
c0f3af97 5589 || i.types[op].bitfield.regymm
c0209578
L		 5590 || i.types[op].bitfield.sreg2
5591 || i.types[op].bitfield.sreg3
5592 || i.types[op].bitfield.control
5593 || i.types[op].bitfield.debug
5594 || i.types[op].bitfield.test)
5595 break;
5596
c0f3af97
L		 5597 if (vex_3_sources)
5598 op = dest;
5599 else if (i.tm.opcode_modifier.vexnds)
5600 {
5601 /* For instructions with VexNDS, the register-only
5602 source operand is encoded in VEX prefix. */
5603 assert (mem != (unsigned int) ~0);
5604
5605 if (op > mem)
5606 {
5607 vex_reg = op++;
5608 assert (op < i.operands);
5609 }
5610 else
5611 {
5612 vex_reg = op + 1;
5613 assert (vex_reg < i.operands);
5614 }
5615 }
5616 else if (i.tm.opcode_modifier.vexndd)
5617 {
5618 /* For instructions with VexNDD, there should be
5619 no memory operand and the register destination
5620 is encoded in VEX prefix. */
5621 assert (i.mem_operands == 0
5622 && (op + 2) == i.operands);
5623 vex_reg = op + 1;
5624 }
5625 else
5626 assert (op < i.operands);
5627
5628 if (vex_reg != (unsigned int) ~0)
5629 {
5630 assert (i.reg_operands == 2);
5631
5632 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
5633 & regxmm)
5634 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5635 &regymm))
5636 abort ();
5637 i.vex.register_specifier = i.op[vex_reg].regs;
5638 }
99018f42 5639
85f10a01
MM		 5640 /* If there is an extension opcode to put here, the
5641 register number must be put into the regmem field. */
c0209578
L		 5642 if (i.tm.extension_opcode != None)
5643 {
5644 i.rm.regmem = i.op[op].regs->reg_num;
5645 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5646 i.rex |= REX_B;
5647 }
5648 else
5649 {
5650 i.rm.reg = i.op[op].regs->reg_num;
5651 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5652 i.rex |= REX_R;
5653 }
85f10a01 5654 }
252b5132 5655
29b0f896
AM		 5656 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5657 must set it to 3 to indicate this is a register operand
5658 in the regmem field. */
5659 if (!i.mem_operands)
5660 i.rm.mode = 3;
5661 }
252b5132 5662
29b0f896 5663 /* Fill in i.rm.reg field with extension opcode (if any). */
85f10a01
MM		 5664 if (i.tm.extension_opcode != None
5665 && !(i.tm.opcode_modifier.drex
5666 || i.tm.opcode_modifier.drexv
5667 || i.tm.opcode_modifier.drexc))
29b0f896
AM		 5668 i.rm.reg = i.tm.extension_opcode;
5669 }
5670 return default_seg;
5671}
252b5132 5672
29b0f896 5673static void
e3bb37b5 5674output_branch (void)
29b0f896
AM		 5675{
5676 char *p;
5677 int code16;
5678 int prefix;
5679 relax_substateT subtype;
5680 symbolS *sym;
5681 offsetT off;
5682
5683 code16 = 0;
5684 if (flag_code == CODE_16BIT)
5685 code16 = CODE16;
5686
5687 prefix = 0;
5688 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5689 {
29b0f896
AM		 5690 prefix = 1;
5691 i.prefixes -= 1;
5692 code16 ^= CODE16;
252b5132 5693 }
29b0f896
AM		 5694 /* Pentium4 branch hints. */
5695 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5696 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5697 {
29b0f896
AM		 5698 prefix++;
5699 i.prefixes--;
5700 }
5701 if (i.prefix[REX_PREFIX] != 0)
5702 {
5703 prefix++;
5704 i.prefixes--;
2f66722d
AM		 5705 }
5706
29b0f896
AM		 5707 if (i.prefixes != 0 && !intel_syntax)
5708 as_warn (_("skipping prefixes on this instruction"));
5709
5710 /* It's always a symbol; End frag & setup for relax.
5711 Make sure there is enough room in this frag for the largest
5712 instruction we may generate in md_convert_frag. This is 2
5713 bytes for the opcode and room for the prefix and largest
5714 displacement. */
5715 frag_grow (prefix + 2 + 4);
5716 /* Prefix and 1 opcode byte go in fr_fix. */
5717 p = frag_more (prefix + 1);
5718 if (i.prefix[DATA_PREFIX] != 0)
5719 *p++ = DATA_PREFIX_OPCODE;
5720 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5721 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5722 *p++ = i.prefix[SEG_PREFIX];
5723 if (i.prefix[REX_PREFIX] != 0)
5724 *p++ = i.prefix[REX_PREFIX];
5725 *p = i.tm.base_opcode;
5726
5727 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5728 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5729 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5730 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5731 else
5732 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5733 subtype |= code16;
3e73aa7c 5734
29b0f896
AM		 5735 sym = i.op[0].disps->X_add_symbol;
5736 off = i.op[0].disps->X_add_number;
3e73aa7c 5737
29b0f896
AM		 5738 if (i.op[0].disps->X_op != O_constant
5739 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5740 {
29b0f896
AM		 5741 /* Handle complex expressions. */
5742 sym = make_expr_symbol (i.op[0].disps);
5743 off = 0;
5744 }
3e73aa7c 5745
29b0f896
AM		 5746 /* 1 possible extra opcode + 4 byte displacement go in var part.
5747 Pass reloc in fr_var. */
5748 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5749}
3e73aa7c 5750
29b0f896 5751static void
e3bb37b5 5752output_jump (void)
29b0f896
AM		 5753{
5754 char *p;
5755 int size;
3e02c1cc 5756 fixS *fixP;
29b0f896 5757
40fb9820 5758 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5759 {
5760 /* This is a loop or jecxz type instruction. */
5761 size = 1;
5762 if (i.prefix[ADDR_PREFIX] != 0)
5763 {
5764 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5765 i.prefixes -= 1;
5766 }
5767 /* Pentium4 branch hints. */
5768 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5769 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5770 {
5771 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5772 i.prefixes--;
3e73aa7c
JH		 5773 }
5774 }
29b0f896
AM		 5775 else
5776 {
5777 int code16;
3e73aa7c 5778
29b0f896
AM		 5779 code16 = 0;
5780 if (flag_code == CODE_16BIT)
5781 code16 = CODE16;
3e73aa7c 5782
29b0f896
AM		 5783 if (i.prefix[DATA_PREFIX] != 0)
5784 {
5785 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5786 i.prefixes -= 1;
5787 code16 ^= CODE16;
5788 }
252b5132 5789
29b0f896
AM		 5790 size = 4;
5791 if (code16)
5792 size = 2;
5793 }
9fcc94b6 5794
29b0f896
AM		 5795 if (i.prefix[REX_PREFIX] != 0)
5796 {
5797 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5798 i.prefixes -= 1;
5799 }
252b5132 5800
29b0f896
AM		 5801 if (i.prefixes != 0 && !intel_syntax)
5802 as_warn (_("skipping prefixes on this instruction"));
e0890092 5803
29b0f896
AM		 5804 p = frag_more (1 + size);
5805 *p++ = i.tm.base_opcode;
e0890092 5806
3e02c1cc
AM		 5807 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5808 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5809
5810 /* All jumps handled here are signed, but don't use a signed limit
5811 check for 32 and 16 bit jumps as we want to allow wrap around at
5812 4G and 64k respectively. */
5813 if (size == 1)
5814 fixP->fx_signed = 1;
29b0f896 5815}
e0890092 5816
29b0f896 5817static void
e3bb37b5 5818output_interseg_jump (void)
29b0f896
AM		 5819{
5820 char *p;
5821 int size;
5822 int prefix;
5823 int code16;
252b5132 5824
29b0f896
AM		 5825 code16 = 0;
5826 if (flag_code == CODE_16BIT)
5827 code16 = CODE16;
a217f122 5828
29b0f896
AM		 5829 prefix = 0;
5830 if (i.prefix[DATA_PREFIX] != 0)
5831 {
5832 prefix = 1;
5833 i.prefixes -= 1;
5834 code16 ^= CODE16;
5835 }
5836 if (i.prefix[REX_PREFIX] != 0)
5837 {
5838 prefix++;
5839 i.prefixes -= 1;
5840 }
252b5132 5841
29b0f896
AM		 5842 size = 4;
5843 if (code16)
5844 size = 2;
252b5132 5845
29b0f896
AM		 5846 if (i.prefixes != 0 && !intel_syntax)
5847 as_warn (_("skipping prefixes on this instruction"));
252b5132 5848
29b0f896
AM		 5849 /* 1 opcode; 2 segment; offset */
5850 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5851
29b0f896
AM		 5852 if (i.prefix[DATA_PREFIX] != 0)
5853 *p++ = DATA_PREFIX_OPCODE;
252b5132 5854
29b0f896
AM		 5855 if (i.prefix[REX_PREFIX] != 0)
5856 *p++ = i.prefix[REX_PREFIX];
252b5132 5857
29b0f896
AM		 5858 *p++ = i.tm.base_opcode;
5859 if (i.op[1].imms->X_op == O_constant)
5860 {
5861 offsetT n = i.op[1].imms->X_add_number;
252b5132 5862
29b0f896
AM		 5863 if (size == 2
5864 && !fits_in_unsigned_word (n)
5865 && !fits_in_signed_word (n))
5866 {
5867 as_bad (_("16-bit jump out of range"));
5868 return;
5869 }
5870 md_number_to_chars (p, n, size);
5871 }
5872 else
5873 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5874 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5875 if (i.op[0].imms->X_op != O_constant)
5876 as_bad (_("can't handle non absolute segment in `%s'"),
5877 i.tm.name);
5878 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5879}
a217f122 5880
29b0f896 5881static void
e3bb37b5 5882output_insn (void)
29b0f896 5883{
2bbd9c25
JJ		 5884 fragS *insn_start_frag;
5885 offsetT insn_start_off;
5886
29b0f896
AM		 5887 /* Tie dwarf2 debug info to the address at the start of the insn.
5888 We can't do this after the insn has been output as the current
5889 frag may have been closed off. eg. by frag_var. */
5890 dwarf2_emit_insn (0);
5891
2bbd9c25
JJ		 5892 insn_start_frag = frag_now;
5893 insn_start_off = frag_now_fix ();
5894
29b0f896 5895 /* Output jumps. */
40fb9820 5896 if (i.tm.opcode_modifier.jump)
29b0f896 5897 output_branch ();
40fb9820
L		 5898 else if (i.tm.opcode_modifier.jumpbyte
5899 || i.tm.opcode_modifier.jumpdword)
29b0f896 5900 output_jump ();
40fb9820 5901 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5902 output_interseg_jump ();
5903 else
5904 {
5905 /* Output normal instructions here. */
5906 char *p;
5907 unsigned char *q;
47465058 5908 unsigned int j;
331d2d0d 5909 unsigned int prefix;
4dffcebc 5910
c0f3af97
L		 5911 /* Since the VEX prefix contains the implicit prefix, we don't
5912 need the explicit prefix. */
5913 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5914 {
c0f3af97 5915 switch (i.tm.opcode_length)
bc4bd9ab 5916 {
c0f3af97
L		 5917 case 3:
5918 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5919 {
c0f3af97
L		 5920 prefix = (i.tm.base_opcode >> 24) & 0xff;
5921 goto check_prefix;
5922 }
5923 break;
5924 case 2:
5925 if ((i.tm.base_opcode & 0xff0000) != 0)
5926 {
5927 prefix = (i.tm.base_opcode >> 16) & 0xff;
5928 if (i.tm.cpu_flags.bitfield.cpupadlock)
5929 {
4dffcebc 5930check_prefix:
c0f3af97
L		 5931 if (prefix != REPE_PREFIX_OPCODE
5932 || (i.prefix[LOCKREP_PREFIX]
5933 != REPE_PREFIX_OPCODE))
5934 add_prefix (prefix);
5935 }
5936 else
4dffcebc
L		 5937 add_prefix (prefix);
5938 }
c0f3af97
L		 5939 break;
5940 case 1:
5941 break;
5942 default:
5943 abort ();
bc4bd9ab 5944 }
c0f3af97
L		 5945
5946 /* The prefix bytes. */
5947 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5948 if (*q)
5949 FRAG_APPEND_1_CHAR (*q);
0f10071e 5950 }
252b5132 5951
c0f3af97
L		 5952 if (i.tm.opcode_modifier.vex)
5953 {
5954 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5955 if (*q)
5956 switch (j)
5957 {
5958 case REX_PREFIX:
5959 /* REX byte is encoded in VEX prefix. */
5960 break;
5961 case SEG_PREFIX:
5962 case ADDR_PREFIX:
5963 FRAG_APPEND_1_CHAR (*q);
5964 break;
5965 default:
5966 /* There should be no other prefixes for instructions
5967 with VEX prefix. */
5968 abort ();
5969 }
5970
5971 /* Now the VEX prefix. */
5972 p = frag_more (i.vex.length);
5973 for (j = 0; j < i.vex.length; j++)
5974 p[j] = i.vex.bytes[j];
5975 }
252b5132 5976
29b0f896 5977 /* Now the opcode; be careful about word order here! */
4dffcebc 5978 if (i.tm.opcode_length == 1)
29b0f896
AM		 5979 {
5980 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5981 }
5982 else
5983 {
4dffcebc 5984 switch (i.tm.opcode_length)
331d2d0d 5985 {
4dffcebc 5986 case 3:
331d2d0d
L		 5987 p = frag_more (3);
5988 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5989 break;
5990 case 2:
5991 p = frag_more (2);
5992 break;
5993 default:
5994 abort ();
5995 break;
331d2d0d 5996 }
0f10071e 5997
29b0f896
AM		 5998 /* Put out high byte first: can't use md_number_to_chars! */
5999 *p++ = (i.tm.base_opcode >> 8) & 0xff;
6000 *p = i.tm.base_opcode & 0xff;
85f10a01
MM		 6001
6002 /* On SSE5, encode the OC1 bit in the DREX field if this
6003 encoding has multiple formats. */
6004 if (i.tm.opcode_modifier.drex
6005 && i.tm.opcode_modifier.drexv
6006 && DREX_OC1 (i.tm.extension_opcode))
6007 *p |= DREX_OC1_MASK;
29b0f896 6008 }
3e73aa7c 6009
29b0f896 6010 /* Now the modrm byte and sib byte (if present). */
40fb9820 6011 if (i.tm.opcode_modifier.modrm)
29b0f896 6012 {
4a3523fa
L		 6013 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
6014 | i.rm.reg << 3
6015 | i.rm.mode << 6));
29b0f896
AM		 6016 /* If i.rm.regmem == ESP (4)
6017 && i.rm.mode != (Register mode)
6018 && not 16 bit
6019 ==> need second modrm byte. */
6020 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
6021 && i.rm.mode != 3
40fb9820 6022 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 6023 FRAG_APPEND_1_CHAR ((i.sib.base << 0
6024 | i.sib.index << 3
6025 | i.sib.scale << 6));
29b0f896 6026 }
3e73aa7c 6027
85f10a01
MM		 6028 /* Write the DREX byte if needed. */
6029 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
6030 {
6031 p = frag_more (1);
6032 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
6033
6034 /* Encode the OC0 bit if this encoding has multiple
6035 formats. */
6036 if ((i.tm.opcode_modifier.drex
6037 || i.tm.opcode_modifier.drexv)
6038 && DREX_OC0 (i.tm.extension_opcode))
6039 *p |= DREX_OC0_MASK;
6040 }
6041
29b0f896 6042 if (i.disp_operands)
2bbd9c25 6043 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 6044
29b0f896 6045 if (i.imm_operands)
2bbd9c25 6046 output_imm (insn_start_frag, insn_start_off);
29b0f896 6047 }
252b5132 6048
29b0f896
AM		 6049#ifdef DEBUG386
6050 if (flag_debug)
6051 {
7b81dfbb 6052 pi ("" /*line*/, &i);
29b0f896
AM		 6053 }
6054#endif /* DEBUG386 */
6055}
252b5132 6056
e205caa7
L		 6057/* Return the size of the displacement operand N. */
6058
6059static int
6060disp_size (unsigned int n)
6061{
6062 int size = 4;
40fb9820
L		 6063 if (i.types[n].bitfield.disp64)
6064 size = 8;
6065 else if (i.types[n].bitfield.disp8)
6066 size = 1;
6067 else if (i.types[n].bitfield.disp16)
6068 size = 2;
e205caa7
L		 6069 return size;
6070}
6071
6072/* Return the size of the immediate operand N. */
6073
6074static int
6075imm_size (unsigned int n)
6076{
6077 int size = 4;
40fb9820
L		 6078 if (i.types[n].bitfield.imm64)
6079 size = 8;
6080 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
6081 size = 1;
6082 else if (i.types[n].bitfield.imm16)
6083 size = 2;
e205caa7
L		 6084 return size;
6085}
6086
29b0f896 6087static void
64e74474 6088output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6089{
6090 char *p;
6091 unsigned int n;
252b5132 6092
29b0f896
AM		 6093 for (n = 0; n < i.operands; n++)
6094 {
40fb9820 6095 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 6096 {
6097 if (i.op[n].disps->X_op == O_constant)
6098 {
e205caa7 6099 int size = disp_size (n);
29b0f896 6100 offsetT val;
252b5132 6101
29b0f896
AM		 6102 val = offset_in_range (i.op[n].disps->X_add_number,
6103 size);
6104 p = frag_more (size);
6105 md_number_to_chars (p, val, size);
6106 }
6107 else
6108 {
f86103b7 6109 enum bfd_reloc_code_real reloc_type;
e205caa7 6110 int size = disp_size (n);
40fb9820 6111 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 6112 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6113
e205caa7 6114 /* We can't have 8 bit displacement here. */
40fb9820 6115 assert (!i.types[n].bitfield.disp8);
e205caa7 6116
29b0f896
AM		 6117 /* The PC relative address is computed relative
6118 to the instruction boundary, so in case immediate
6119 fields follows, we need to adjust the value. */
6120 if (pcrel && i.imm_operands)
6121 {
29b0f896 6122 unsigned int n1;
e205caa7 6123 int sz = 0;
252b5132 6124
29b0f896 6125 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 6126 if (operand_type_check (i.types[n1], imm))
252b5132 6127 {
e205caa7
L		 6128 /* Only one immediate is allowed for PC
6129 relative address. */
6130 assert (sz == 0);
6131 sz = imm_size (n1);
6132 i.op[n].disps->X_add_number -= sz;
252b5132 6133 }
29b0f896 6134 /* We should find the immediate. */
e205caa7 6135 assert (sz != 0);
29b0f896 6136 }
520dc8e8 6137
29b0f896 6138 p = frag_more (size);
2bbd9c25 6139 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 6140 if (GOT_symbol
2bbd9c25 6141 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 6142 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6143 || reloc_type == BFD_RELOC_X86_64_32S
6144 || (reloc_type == BFD_RELOC_64
6145 && object_64bit))
d6ab8113
JB		 6146 && (i.op[n].disps->X_op == O_symbol
6147 || (i.op[n].disps->X_op == O_add
6148 && ((symbol_get_value_expression
6149 (i.op[n].disps->X_op_symbol)->X_op)
6150 == O_subtract))))
6151 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 6152 {
6153 offsetT add;
6154
6155 if (insn_start_frag == frag_now)
6156 add = (p - frag_now->fr_literal) - insn_start_off;
6157 else
6158 {
6159 fragS *fr;
6160
6161 add = insn_start_frag->fr_fix - insn_start_off;
6162 for (fr = insn_start_frag->fr_next;
6163 fr && fr != frag_now; fr = fr->fr_next)
6164 add += fr->fr_fix;
6165 add += p - frag_now->fr_literal;
6166 }
6167
4fa24527 6168 if (!object_64bit)
7b81dfbb
AJ		 6169 {
6170 reloc_type = BFD_RELOC_386_GOTPC;
6171 i.op[n].imms->X_add_number += add;
6172 }
6173 else if (reloc_type == BFD_RELOC_64)
6174 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 6175 else
7b81dfbb
AJ		 6176 /* Don't do the adjustment for x86-64, as there
6177 the pcrel addressing is relative to the _next_
6178 insn, and that is taken care of in other code. */
d6ab8113 6179 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 6180 }
062cd5e7 6181 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 6182 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 6183 }
6184 }
6185 }
6186}
252b5132 6187
29b0f896 6188static void
64e74474 6189output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6190{
6191 char *p;
6192 unsigned int n;
252b5132 6193
29b0f896
AM		 6194 for (n = 0; n < i.operands; n++)
6195 {
40fb9820 6196 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 6197 {
6198 if (i.op[n].imms->X_op == O_constant)
6199 {
e205caa7 6200 int size = imm_size (n);
29b0f896 6201 offsetT val;
b4cac588 6202
29b0f896
AM		 6203 val = offset_in_range (i.op[n].imms->X_add_number,
6204 size);
6205 p = frag_more (size);
6206 md_number_to_chars (p, val, size);
6207 }
6208 else
6209 {
6210 /* Not absolute_section.
6211 Need a 32-bit fixup (don't support 8bit
6212 non-absolute imms). Try to support other
6213 sizes ... */
f86103b7 6214 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 6215 int size = imm_size (n);
6216 int sign;
29b0f896 6217
40fb9820 6218 if (i.types[n].bitfield.imm32s
a7d61044 6219 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6220 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6221 sign = 1;
e205caa7
L		 6222 else
6223 sign = 0;
520dc8e8 6224
29b0f896
AM		 6225 p = frag_more (size);
6226 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6227
2bbd9c25
JJ		 6228 /* This is tough to explain. We end up with this one if we
6229 * have operands that look like
6230 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6231 * obtain the absolute address of the GOT, and it is strongly
6232 * preferable from a performance point of view to avoid using
6233 * a runtime relocation for this. The actual sequence of
6234 * instructions often look something like:
6235 *
6236 * call .L66
6237 * .L66:
6238 * popl %ebx
6239 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6240 *
6241 * The call and pop essentially return the absolute address
6242 * of the label .L66 and store it in %ebx. The linker itself
6243 * will ultimately change the first operand of the addl so
6244 * that %ebx points to the GOT, but to keep things simple, the
6245 * .o file must have this operand set so that it generates not
6246 * the absolute address of .L66, but the absolute address of
6247 * itself. This allows the linker itself simply treat a GOTPC
6248 * relocation as asking for a pcrel offset to the GOT to be
6249 * added in, and the addend of the relocation is stored in the
6250 * operand field for the instruction itself.
6251 *
6252 * Our job here is to fix the operand so that it would add
6253 * the correct offset so that %ebx would point to itself. The
6254 * thing that is tricky is that .-.L66 will point to the
6255 * beginning of the instruction, so we need to further modify
6256 * the operand so that it will point to itself. There are
6257 * other cases where you have something like:
6258 *
6259 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6260 *
6261 * and here no correction would be required. Internally in
6262 * the assembler we treat operands of this form as not being
6263 * pcrel since the '.' is explicitly mentioned, and I wonder
6264 * whether it would simplify matters to do it this way. Who
6265 * knows. In earlier versions of the PIC patches, the
6266 * pcrel_adjust field was used to store the correction, but
6267 * since the expression is not pcrel, I felt it would be
6268 * confusing to do it this way. */
6269
d6ab8113 6270 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6271 || reloc_type == BFD_RELOC_X86_64_32S
6272 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6273 && GOT_symbol
6274 && GOT_symbol == i.op[n].imms->X_add_symbol
6275 && (i.op[n].imms->X_op == O_symbol
6276 || (i.op[n].imms->X_op == O_add
6277 && ((symbol_get_value_expression
6278 (i.op[n].imms->X_op_symbol)->X_op)
6279 == O_subtract))))
6280 {
2bbd9c25
JJ		 6281 offsetT add;
6282
6283 if (insn_start_frag == frag_now)
6284 add = (p - frag_now->fr_literal) - insn_start_off;
6285 else
6286 {
6287 fragS *fr;
6288
6289 add = insn_start_frag->fr_fix - insn_start_off;
6290 for (fr = insn_start_frag->fr_next;
6291 fr && fr != frag_now; fr = fr->fr_next)
6292 add += fr->fr_fix;
6293 add += p - frag_now->fr_literal;
6294 }
6295
4fa24527 6296 if (!object_64bit)
d6ab8113 6297 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6298 else if (size == 4)
d6ab8113 6299 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6300 else if (size == 8)
6301 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6302 i.op[n].imms->X_add_number += add;
29b0f896 6303 }
29b0f896
AM		 6304 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6305 i.op[n].imms, 0, reloc_type);
6306 }
6307 }
6308 }
252b5132
RH		 6309}
6310\f
d182319b
JB		 6311/* x86_cons_fix_new is called via the expression parsing code when a
6312 reloc is needed. We use this hook to get the correct .got reloc. */
6313static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6314static int cons_sign = -1;
6315
6316void
e3bb37b5 6317x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6318 expressionS *exp)
d182319b
JB		 6319{
6320 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6321
6322 got_reloc = NO_RELOC;
6323
6324#ifdef TE_PE
6325 if (exp->X_op == O_secrel)
6326 {
6327 exp->X_op = O_symbol;
6328 r = BFD_RELOC_32_SECREL;
6329 }
6330#endif
6331
6332 fix_new_exp (frag, off, len, exp, 0, r);
6333}
6334
718ddfc0
JB		 6335#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6336# define lex_got(reloc, adjust, types) NULL
6337#else
f3c180ae
AM		 6338/* Parse operands of the form
6339 <symbol>@GOTOFF+<nnn>
6340 and similar .plt or .got references.
6341
6342 If we find one, set up the correct relocation in RELOC and copy the
6343 input string, minus the `@GOTOFF' into a malloc'd buffer for
6344 parsing by the calling routine. Return this buffer, and if ADJUST
6345 is non-null set it to the length of the string we removed from the
6346 input line. Otherwise return NULL. */
6347static char *
3956db08 6348lex_got (enum bfd_reloc_code_real *reloc,
64e74474 6349 int *adjust,
40fb9820 6350 i386_operand_type *types)
f3c180ae 6351{
7b81dfbb
AJ		 6352 /* Some of the relocations depend on the size of what field is to
6353 be relocated. But in our callers i386_immediate and i386_displacement
6354 we don't yet know the operand size (this will be set by insn
6355 matching). Hence we record the word32 relocation here,
6356 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6357 static const struct {
6358 const char *str;
4fa24527 6359 const enum bfd_reloc_code_real rel[2];
40fb9820 6360 const i386_operand_type types64;
f3c180ae 6361 } gotrel[] = {
4eed87de
AM		 6362 { "PLTOFF", { 0,
6363 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6364 OPERAND_TYPE_IMM64 },
4eed87de
AM		 6365 { "PLT", { BFD_RELOC_386_PLT32,
6366 BFD_RELOC_X86_64_PLT32 },
40fb9820 6367 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6368 { "GOTPLT", { 0,
6369 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6370 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 6371 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
6372 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6373 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 6374 { "GOTPCREL", { 0,
6375 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6376 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6377 { "TLSGD", { BFD_RELOC_386_TLS_GD,
6378 BFD_RELOC_X86_64_TLSGD },
40fb9820 6379 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6380 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
6381 0 },
40fb9820 6382 OPERAND_TYPE_NONE },
4eed87de
AM		 6383 { "TLSLD", { 0,
6384 BFD_RELOC_X86_64_TLSLD },
40fb9820 6385 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6386 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
6387 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6388 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6389 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
6390 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6391 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 6392 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
6393 0 },
40fb9820 6394 OPERAND_TYPE_NONE },
4eed87de
AM		 6395 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
6396 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820
L		 6397
6398 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 6399 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
6400 0 },
40fb9820 6401 OPERAND_TYPE_NONE },
4eed87de
AM		 6402 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
6403 0 },
40fb9820 6404 OPERAND_TYPE_NONE },
4eed87de
AM		 6405 { "GOT", { BFD_RELOC_386_GOT32,
6406 BFD_RELOC_X86_64_GOT32 },
40fb9820 6407 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 6408 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
6409 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6410 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6411 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
6412 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6413 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6414 };
6415 char *cp;
6416 unsigned int j;
6417
718ddfc0
JB		 6418 if (!IS_ELF)
6419 return NULL;
6420
f3c180ae 6421 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6422 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6423 return NULL;
6424
47465058 6425 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 6426 {
6427 int len;
6428
6429 len = strlen (gotrel[j].str);
28f81592 6430 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6431 {
4fa24527 6432 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6433 {
28f81592
AM		 6434 int first, second;
6435 char *tmpbuf, *past_reloc;
f3c180ae 6436
4fa24527 6437 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 6438 if (adjust)
6439 *adjust = len;
f3c180ae 6440
3956db08
JB		 6441 if (types)
6442 {
6443 if (flag_code != CODE_64BIT)
40fb9820
L		 6444 {
6445 types->bitfield.imm32 = 1;
6446 types->bitfield.disp32 = 1;
6447 }
3956db08
JB		 6448 else
6449 *types = gotrel[j].types64;
6450 }
6451
f3c180ae
AM		 6452 if (GOT_symbol == NULL)
6453 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6454
28f81592 6455 /* The length of the first part of our input line. */
f3c180ae 6456 first = cp - input_line_pointer;
28f81592
AM		 6457
6458 /* The second part goes from after the reloc token until
67c11a9b 6459 (and including) an end_of_line char or comma. */
28f81592 6460 past_reloc = cp + 1 + len;
67c11a9b
AM		 6461 cp = past_reloc;
6462 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6463 ++cp;
6464 second = cp + 1 - past_reloc;
28f81592
AM		 6465
6466 /* Allocate and copy string. The trailing NUL shouldn't
6467 be necessary, but be safe. */
6468 tmpbuf = xmalloc (first + second + 2);
f3c180ae 6469 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6470 if (second != 0 && *past_reloc != ' ')
6471 /* Replace the relocation token with ' ', so that
6472 errors like foo@GOTOFF1 will be detected. */
6473 tmpbuf[first++] = ' ';
6474 memcpy (tmpbuf + first, past_reloc, second);
6475 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6476 return tmpbuf;
6477 }
6478
4fa24527
JB		 6479 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6480 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6481 return NULL;
6482 }
6483 }
6484
6485 /* Might be a symbol version string. Don't as_bad here. */
6486 return NULL;
6487}
6488
f3c180ae 6489void
e3bb37b5 6490x86_cons (expressionS *exp, int size)
f3c180ae 6491{
4fa24527 6492 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6493 {
6494 /* Handle @GOTOFF and the like in an expression. */
6495 char *save;
6496 char *gotfree_input_line;
6497 int adjust;
6498
6499 save = input_line_pointer;
3956db08 6500 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6501 if (gotfree_input_line)
6502 input_line_pointer = gotfree_input_line;
6503
6504 expression (exp);
6505
6506 if (gotfree_input_line)
6507 {
6508 /* expression () has merrily parsed up to the end of line,
6509 or a comma - in the wrong buffer. Transfer how far
6510 input_line_pointer has moved to the right buffer. */
6511 input_line_pointer = (save
6512 + (input_line_pointer - gotfree_input_line)
6513 + adjust);
6514 free (gotfree_input_line);
3992d3b7
AM		 6515 if (exp->X_op == O_constant
6516 || exp->X_op == O_absent
6517 || exp->X_op == O_illegal
6518 || exp->X_op == O_register
6519 || exp->X_op == O_big)
6520 {
6521 char c = *input_line_pointer;
6522 *input_line_pointer = 0;
6523 as_bad (_("missing or invalid expression `%s'"), save);
6524 *input_line_pointer = c;
6525 }
f3c180ae
AM		 6526 }
6527 }
6528 else
6529 expression (exp);
6530}
6531#endif
6532
d182319b 6533static void signed_cons (int size)
6482c264 6534{
d182319b
JB		 6535 if (flag_code == CODE_64BIT)
6536 cons_sign = 1;
6537 cons (size);
6538 cons_sign = -1;
6482c264
NC		 6539}
6540
d182319b 6541#ifdef TE_PE
6482c264
NC		 6542static void
6543pe_directive_secrel (dummy)
6544 int dummy ATTRIBUTE_UNUSED;
6545{
6546 expressionS exp;
6547
6548 do
6549 {
6550 expression (&exp);
6551 if (exp.X_op == O_symbol)
6552 exp.X_op = O_secrel;
6553
6554 emit_expr (&exp, 4);
6555 }
6556 while (*input_line_pointer++ == ',');
6557
6558 input_line_pointer--;
6559 demand_empty_rest_of_line ();
6560}
6482c264
NC		 6561#endif
6562
252b5132 6563static int
70e41ade 6564i386_immediate (char *imm_start)
252b5132
RH		 6565{
6566 char *save_input_line_pointer;
f3c180ae 6567 char *gotfree_input_line;
252b5132 6568 segT exp_seg = 0;
47926f60 6569 expressionS *exp;
40fb9820
L		 6570 i386_operand_type types;
6571
0dfbf9d7 6572 operand_type_set (&types, ~0);
252b5132
RH		 6573
6574 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6575 {
31b2323c
L		 6576 as_bad (_("at most %d immediate operands are allowed"),
6577 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6578 return 0;
6579 }
6580
6581 exp = &im_expressions[i.imm_operands++];
520dc8e8 6582 i.op[this_operand].imms = exp;
252b5132
RH		 6583
6584 if (is_space_char (*imm_start))
6585 ++imm_start;
6586
6587 save_input_line_pointer = input_line_pointer;
6588 input_line_pointer = imm_start;
6589
3956db08 6590 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6591 if (gotfree_input_line)
6592 input_line_pointer = gotfree_input_line;
252b5132
RH		 6593
6594 exp_seg = expression (exp);
6595
83183c0c 6596 SKIP_WHITESPACE ();
252b5132 6597 if (*input_line_pointer)
f3c180ae 6598 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6599
6600 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 6601 if (gotfree_input_line)
6602 free (gotfree_input_line);
252b5132 6603
3992d3b7
AM		 6604 if (exp->X_op == O_absent
6605 || exp->X_op == O_illegal
6606 || exp->X_op == O_big
6607 || (gotfree_input_line
6608 && (exp->X_op == O_constant
6609 || exp->X_op == O_register)))
252b5132 6610 {
3992d3b7 6611 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 6612 imm_start);
3992d3b7 6613 return 0;
252b5132 6614 }
3e73aa7c 6615 else if (exp->X_op == O_constant)
252b5132 6616 {
47926f60 6617 /* Size it properly later. */
40fb9820 6618 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 6619 /* If BFD64, sign extend val. */
4eed87de
AM		 6620 if (!use_rela_relocations
6621 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6622 exp->X_add_number
6623 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6624 }
4c63da97 6625#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6626 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6627 && exp_seg != absolute_section
47926f60 6628 && exp_seg != text_section
24eab124
AM		 6629 && exp_seg != data_section
6630 && exp_seg != bss_section
6631 && exp_seg != undefined_section
f86103b7 6632 && !bfd_is_com_section (exp_seg))
252b5132 6633 {
d0b47220 6634 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6635 return 0;
6636 }
6637#endif
bb8f5920
L		 6638 else if (!intel_syntax && exp->X_op == O_register)
6639 {
6640 as_bad (_("illegal immediate register operand %s"), imm_start);
6641 return 0;
6642 }
252b5132
RH		 6643 else
6644 {
6645 /* This is an address. The size of the address will be
24eab124 6646 determined later, depending on destination register,
3e73aa7c 6647 suffix, or the default for the section. */
40fb9820
L		 6648 i.types[this_operand].bitfield.imm8 = 1;
6649 i.types[this_operand].bitfield.imm16 = 1;
6650 i.types[this_operand].bitfield.imm32 = 1;
6651 i.types[this_operand].bitfield.imm32s = 1;
6652 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6653 i.types[this_operand] = operand_type_and (i.types[this_operand],
6654 types);
252b5132
RH		 6655 }
6656
6657 return 1;
6658}
6659
551c1ca1 6660static char *
e3bb37b5 6661i386_scale (char *scale)
252b5132 6662{
551c1ca1
AM		 6663 offsetT val;
6664 char *save = input_line_pointer;
252b5132 6665
551c1ca1
AM		 6666 input_line_pointer = scale;
6667 val = get_absolute_expression ();
6668
6669 switch (val)
252b5132 6670 {
551c1ca1 6671 case 1:
252b5132
RH		 6672 i.log2_scale_factor = 0;
6673 break;
551c1ca1 6674 case 2:
252b5132
RH		 6675 i.log2_scale_factor = 1;
6676 break;
551c1ca1 6677 case 4:
252b5132
RH		 6678 i.log2_scale_factor = 2;
6679 break;
551c1ca1 6680 case 8:
252b5132
RH		 6681 i.log2_scale_factor = 3;
6682 break;
6683 default:
a724f0f4
JB		 6684 {
6685 char sep = *input_line_pointer;
6686
6687 *input_line_pointer = '\0';
6688 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6689 scale);
6690 *input_line_pointer = sep;
6691 input_line_pointer = save;
6692 return NULL;
6693 }
252b5132 6694 }
29b0f896 6695 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6696 {
6697 as_warn (_("scale factor of %d without an index register"),
24eab124 6698 1 << i.log2_scale_factor);
252b5132 6699 i.log2_scale_factor = 0;
252b5132 6700 }
551c1ca1
AM		 6701 scale = input_line_pointer;
6702 input_line_pointer = save;
6703 return scale;
252b5132
RH		 6704}
6705
252b5132 6706static int
e3bb37b5 6707i386_displacement (char *disp_start, char *disp_end)
252b5132 6708{
29b0f896 6709 expressionS *exp;
252b5132
RH		 6710 segT exp_seg = 0;
6711 char *save_input_line_pointer;
f3c180ae 6712 char *gotfree_input_line;
40fb9820
L		 6713 int override;
6714 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6715 int ret;
252b5132 6716
31b2323c
L		 6717 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6718 {
6719 as_bad (_("at most %d displacement operands are allowed"),
6720 MAX_MEMORY_OPERANDS);
6721 return 0;
6722 }
6723
0dfbf9d7 6724 operand_type_set (&bigdisp, 0);
40fb9820
L		 6725 if ((i.types[this_operand].bitfield.jumpabsolute)
6726 || (!current_templates->start->opcode_modifier.jump
6727 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6728 {
40fb9820 6729 bigdisp.bitfield.disp32 = 1;
e05278af 6730 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6731 if (flag_code == CODE_64BIT)
6732 {
6733 if (!override)
6734 {
6735 bigdisp.bitfield.disp32s = 1;
6736 bigdisp.bitfield.disp64 = 1;
6737 }
6738 }
6739 else if ((flag_code == CODE_16BIT) ^ override)
6740 {
6741 bigdisp.bitfield.disp32 = 0;
6742 bigdisp.bitfield.disp16 = 1;
6743 }
e05278af
JB		 6744 }
6745 else
6746 {
6747 /* For PC-relative branches, the width of the displacement
6748 is dependent upon data size, not address size. */
e05278af 6749 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6750 if (flag_code == CODE_64BIT)
6751 {
6752 if (override || i.suffix == WORD_MNEM_SUFFIX)
6753 bigdisp.bitfield.disp16 = 1;
6754 else
6755 {
6756 bigdisp.bitfield.disp32 = 1;
6757 bigdisp.bitfield.disp32s = 1;
6758 }
6759 }
6760 else
e05278af
JB		 6761 {
6762 if (!override)
6763 override = (i.suffix == (flag_code != CODE_16BIT
6764 ? WORD_MNEM_SUFFIX
6765 : LONG_MNEM_SUFFIX));
40fb9820
L		 6766 bigdisp.bitfield.disp32 = 1;
6767 if ((flag_code == CODE_16BIT) ^ override)
6768 {
6769 bigdisp.bitfield.disp32 = 0;
6770 bigdisp.bitfield.disp16 = 1;
6771 }
e05278af 6772 }
e05278af 6773 }
c6fb90c8
L		 6774 i.types[this_operand] = operand_type_or (i.types[this_operand],
6775 bigdisp);
252b5132
RH		 6776
6777 exp = &disp_expressions[i.disp_operands];
520dc8e8 6778 i.op[this_operand].disps = exp;
252b5132
RH		 6779 i.disp_operands++;
6780 save_input_line_pointer = input_line_pointer;
6781 input_line_pointer = disp_start;
6782 END_STRING_AND_SAVE (disp_end);
6783
6784#ifndef GCC_ASM_O_HACK
6785#define GCC_ASM_O_HACK 0
6786#endif
6787#if GCC_ASM_O_HACK
6788 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6789 if (i.types[this_operand].bitfield.baseIndex
24eab124 6790 && displacement_string_end[-1] == '+')
252b5132
RH		 6791 {
6792 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6793 constraint within gcc asm statements.
6794 For instance:
6795
6796 #define _set_tssldt_desc(n,addr,limit,type) \
6797 __asm__ __volatile__ ( \
6798 "movw %w2,%0\n\t" \
6799 "movw %w1,2+%0\n\t" \
6800 "rorl $16,%1\n\t" \
6801 "movb %b1,4+%0\n\t" \
6802 "movb %4,5+%0\n\t" \
6803 "movb $0,6+%0\n\t" \
6804 "movb %h1,7+%0\n\t" \
6805 "rorl $16,%1" \
6806 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6807
6808 This works great except that the output assembler ends
6809 up looking a bit weird if it turns out that there is
6810 no offset. You end up producing code that looks like:
6811
6812 #APP
6813 movw $235,(%eax)
6814 movw %dx,2+(%eax)
6815 rorl $16,%edx
6816 movb %dl,4+(%eax)
6817 movb $137,5+(%eax)
6818 movb $0,6+(%eax)
6819 movb %dh,7+(%eax)
6820 rorl $16,%edx
6821 #NO_APP
6822
47926f60 6823 So here we provide the missing zero. */
24eab124
AM		 6824
6825 *displacement_string_end = '0';
252b5132
RH		 6826 }
6827#endif
3956db08 6828 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6829 if (gotfree_input_line)
6830 input_line_pointer = gotfree_input_line;
252b5132 6831
24eab124 6832 exp_seg = expression (exp);
252b5132 6833
636c26b0
AM		 6834 SKIP_WHITESPACE ();
6835 if (*input_line_pointer)
6836 as_bad (_("junk `%s' after expression"), input_line_pointer);
6837#if GCC_ASM_O_HACK
6838 RESTORE_END_STRING (disp_end + 1);
6839#endif
636c26b0 6840 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 6841 if (gotfree_input_line)
6842 free (gotfree_input_line);
3992d3b7 6843 ret = 1;
636c26b0 6844
24eab124
AM		 6845 /* We do this to make sure that the section symbol is in
6846 the symbol table. We will ultimately change the relocation
47926f60 6847 to be relative to the beginning of the section. */
1ae12ab7 6848 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6849 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6850 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6851 {
636c26b0 6852 if (exp->X_op != O_symbol)
3992d3b7 6853 goto inv_disp;
636c26b0 6854
e5cb08ac 6855 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 6856 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6857 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6858 exp->X_op = O_subtract;
6859 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6860 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6861 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6862 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6863 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6864 else
29b0f896 6865 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6866 }
252b5132 6867
3992d3b7
AM		 6868 else if (exp->X_op == O_absent
6869 || exp->X_op == O_illegal
6870 || exp->X_op == O_big
6871 || (gotfree_input_line
6872 && (exp->X_op == O_constant
6873 || exp->X_op == O_register)))
2daf4fd8 6874 {
3992d3b7
AM		 6875 inv_disp:
6876 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6877 disp_start);
3992d3b7 6878 ret = 0;
2daf4fd8
AM		 6879 }
6880
4c63da97 6881#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6882 else if (exp->X_op != O_constant
6883 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6884 && exp_seg != absolute_section
6885 && exp_seg != text_section
6886 && exp_seg != data_section
6887 && exp_seg != bss_section
6888 && exp_seg != undefined_section
6889 && !bfd_is_com_section (exp_seg))
24eab124 6890 {
d0b47220 6891 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6892 ret = 0;
24eab124 6893 }
252b5132 6894#endif
3956db08 6895
3992d3b7
AM		 6896 RESTORE_END_STRING (disp_end);
6897
40fb9820
L		 6898 /* Check if this is a displacement only operand. */
6899 bigdisp = i.types[this_operand];
6900 bigdisp.bitfield.disp8 = 0;
6901 bigdisp.bitfield.disp16 = 0;
6902 bigdisp.bitfield.disp32 = 0;
6903 bigdisp.bitfield.disp32s = 0;
6904 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6905 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6906 i.types[this_operand] = operand_type_and (i.types[this_operand],
6907 types);
3956db08 6908
3992d3b7 6909 return ret;
252b5132
RH		 6910}
6911
eecb386c 6912/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6913 Return 1 on success, 0 on a failure. */
6914
252b5132 6915static int
e3bb37b5 6916i386_index_check (const char *operand_string)
252b5132 6917{
3e73aa7c 6918 int ok;
fc0763e6 6919 const char *kind = "base/index";
24eab124 6920#if INFER_ADDR_PREFIX
eecb386c
AM		 6921 int fudged = 0;
6922
24eab124
AM		 6923 tryprefix:
6924#endif
3e73aa7c 6925 ok = 1;
fc0763e6
JB		 6926 if (current_templates->start->opcode_modifier.isstring
6927 && !current_templates->start->opcode_modifier.immext
6928 && (current_templates->end[-1].opcode_modifier.isstring
6929 || i.mem_operands))
6930 {
6931 /* Memory operands of string insns are special in that they only allow
6932 a single register (rDI, rSI, or rBX) as their memory address. */
6933 unsigned int expected;
6934
6935 kind = "string address";
6936
6937 if (current_templates->start->opcode_modifier.w)
6938 {
6939 i386_operand_type type = current_templates->end[-1].operand_types[0];
6940
6941 if (!type.bitfield.baseindex
6942 || ((!i.mem_operands != !intel_syntax)
6943 && current_templates->end[-1].operand_types[1]
6944 .bitfield.baseindex))
6945 type = current_templates->end[-1].operand_types[1];
6946 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
6947 }
6948 else
6949 expected = 3 /* rBX */;
6950
6951 if (!i.base_reg || i.index_reg
6952 || operand_type_check (i.types[this_operand], disp))
6953 ok = -1;
6954 else if (!(flag_code == CODE_64BIT
6955 ? i.prefix[ADDR_PREFIX]
6956 ? i.base_reg->reg_type.bitfield.reg32
6957 : i.base_reg->reg_type.bitfield.reg64
6958 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6959 ? i.base_reg->reg_type.bitfield.reg32
6960 : i.base_reg->reg_type.bitfield.reg16))
6961 ok = 0;
6962 else if (i.base_reg->reg_num != expected)
6963 ok = -1;
6964
6965 if (ok < 0)
6966 {
6967 unsigned int j;
6968
6969 for (j = 0; j < i386_regtab_size; ++j)
6970 if ((flag_code == CODE_64BIT
6971 ? i.prefix[ADDR_PREFIX]
6972 ? i386_regtab[j].reg_type.bitfield.reg32
6973 : i386_regtab[j].reg_type.bitfield.reg64
6974 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6975 ? i386_regtab[j].reg_type.bitfield.reg32
6976 : i386_regtab[j].reg_type.bitfield.reg16)
6977 && i386_regtab[j].reg_num == expected)
6978 break;
6979 assert (j < i386_regtab_size);
6980 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6981 operand_string,
6982 intel_syntax ? '[' : '(',
6983 register_prefix,
6984 i386_regtab[j].reg_name,
6985 intel_syntax ? ']' : ')');
6986 ok = 1;
6987 }
6988 }
6989 else if (flag_code == CODE_64BIT)
64e74474 6990 {
64e74474 6991 if ((i.base_reg
40fb9820
L		 6992 && ((i.prefix[ADDR_PREFIX] == 0
6993 && !i.base_reg->reg_type.bitfield.reg64)
6994 || (i.prefix[ADDR_PREFIX]
6995 && !i.base_reg->reg_type.bitfield.reg32))
6996 && (i.index_reg
9a04903e
JB		 6997 || i.base_reg->reg_num !=
6998 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6999 || (i.index_reg
40fb9820
L		 7000 && (!i.index_reg->reg_type.bitfield.baseindex
7001 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 7002 && i.index_reg->reg_num != RegRiz
7003 && !i.index_reg->reg_type.bitfield.reg64
7004 )
40fb9820 7005 || (i.prefix[ADDR_PREFIX]
db51cc60 7006 && i.index_reg->reg_num != RegEiz
40fb9820 7007 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 7008 ok = 0;
3e73aa7c
JH		 7009 }
7010 else
7011 {
7012 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
7013 {
7014 /* 16bit checks. */
7015 if ((i.base_reg
40fb9820
L		 7016 && (!i.base_reg->reg_type.bitfield.reg16
7017 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 7018 || (i.index_reg
40fb9820
L		 7019 && (!i.index_reg->reg_type.bitfield.reg16
7020 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 7021 || !(i.base_reg
7022 && i.base_reg->reg_num < 6
7023 && i.index_reg->reg_num >= 6
7024 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 7025 ok = 0;
7026 }
7027 else
e5cb08ac 7028 {
3e73aa7c
JH		 7029 /* 32bit checks. */
7030 if ((i.base_reg
40fb9820 7031 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 7032 || (i.index_reg
db51cc60
L		 7033 && ((!i.index_reg->reg_type.bitfield.reg32
7034 && i.index_reg->reg_num != RegEiz)
40fb9820 7035 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 7036 ok = 0;
3e73aa7c
JH		 7037 }
7038 }
7039 if (!ok)
24eab124
AM		 7040 {
7041#if INFER_ADDR_PREFIX
fc0763e6 7042 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 7043 {
7044 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
7045 i.prefixes += 1;
b23bac36
AM		 7046 /* Change the size of any displacement too. At most one of
7047 Disp16 or Disp32 is set.
7048 FIXME. There doesn't seem to be any real need for separate
7049 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 7050 Removing them would probably clean up the code quite a lot. */
4eed87de 7051 if (flag_code != CODE_64BIT
40fb9820
L		 7052 && (i.types[this_operand].bitfield.disp16
7053 || i.types[this_operand].bitfield.disp32))
7054 i.types[this_operand]
c6fb90c8 7055 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 7056 fudged = 1;
24eab124
AM		 7057 goto tryprefix;
7058 }
eecb386c 7059 if (fudged)
fc0763e6
JB		 7060 as_bad (_("`%s' is not a valid %s expression"),
7061 operand_string,
7062 kind);
eecb386c 7063 else
c388dee8 7064#endif
fc0763e6 7065 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 7066 operand_string,
fc0763e6
JB		 7067 flag_code_names[i.prefix[ADDR_PREFIX]
7068 ? flag_code == CODE_32BIT
7069 ? CODE_16BIT
7070 : CODE_32BIT
7071 : flag_code],
7072 kind);
24eab124 7073 }
20f0a1fc 7074 return ok;
24eab124 7075}
252b5132 7076
fc0763e6 7077/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 7078 on error. */
252b5132 7079
252b5132 7080static int
a7619375 7081i386_att_operand (char *operand_string)
252b5132 7082{
af6bdddf
AM		 7083 const reg_entry *r;
7084 char *end_op;
24eab124 7085 char *op_string = operand_string;
252b5132 7086
24eab124 7087 if (is_space_char (*op_string))
252b5132
RH		 7088 ++op_string;
7089
24eab124 7090 /* We check for an absolute prefix (differentiating,
47926f60 7091 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 7092 if (*op_string == ABSOLUTE_PREFIX)
7093 {
7094 ++op_string;
7095 if (is_space_char (*op_string))
7096 ++op_string;
40fb9820 7097 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 7098 }
252b5132 7099
47926f60 7100 /* Check if operand is a register. */
4d1bb795 7101 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 7102 {
40fb9820
L		 7103 i386_operand_type temp;
7104
24eab124
AM		 7105 /* Check for a segment override by searching for ':' after a
7106 segment register. */
7107 op_string = end_op;
7108 if (is_space_char (*op_string))
7109 ++op_string;
40fb9820
L		 7110 if (*op_string == ':'
7111 && (r->reg_type.bitfield.sreg2
7112 || r->reg_type.bitfield.sreg3))
24eab124
AM		 7113 {
7114 switch (r->reg_num)
7115 {
7116 case 0:
7117 i.seg[i.mem_operands] = &es;
7118 break;
7119 case 1:
7120 i.seg[i.mem_operands] = &cs;
7121 break;
7122 case 2:
7123 i.seg[i.mem_operands] = &ss;
7124 break;
7125 case 3:
7126 i.seg[i.mem_operands] = &ds;
7127 break;
7128 case 4:
7129 i.seg[i.mem_operands] = &fs;
7130 break;
7131 case 5:
7132 i.seg[i.mem_operands] = &gs;
7133 break;
7134 }
252b5132 7135
24eab124 7136 /* Skip the ':' and whitespace. */
252b5132
RH		 7137 ++op_string;
7138 if (is_space_char (*op_string))
24eab124 7139 ++op_string;
252b5132 7140
24eab124
AM		 7141 if (!is_digit_char (*op_string)
7142 && !is_identifier_char (*op_string)
7143 && *op_string != '('
7144 && *op_string != ABSOLUTE_PREFIX)
7145 {
7146 as_bad (_("bad memory operand `%s'"), op_string);
7147 return 0;
7148 }
47926f60 7149 /* Handle case of %es:*foo. */
24eab124
AM		 7150 if (*op_string == ABSOLUTE_PREFIX)
7151 {
7152 ++op_string;
7153 if (is_space_char (*op_string))
7154 ++op_string;
40fb9820 7155 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 7156 }
7157 goto do_memory_reference;
7158 }
7159 if (*op_string)
7160 {
d0b47220 7161 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 7162 return 0;
7163 }
40fb9820
L		 7164 temp = r->reg_type;
7165 temp.bitfield.baseindex = 0;
c6fb90c8
L		 7166 i.types[this_operand] = operand_type_or (i.types[this_operand],
7167 temp);
7d5e4556 7168 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 7169 i.op[this_operand].regs = r;
24eab124
AM		 7170 i.reg_operands++;
7171 }
af6bdddf
AM		 7172 else if (*op_string == REGISTER_PREFIX)
7173 {
7174 as_bad (_("bad register name `%s'"), op_string);
7175 return 0;
7176 }
24eab124 7177 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7178 {
24eab124 7179 ++op_string;
40fb9820 7180 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7181 {
d0b47220 7182 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7183 return 0;
7184 }
7185 if (!i386_immediate (op_string))
7186 return 0;
7187 }
7188 else if (is_digit_char (*op_string)
7189 || is_identifier_char (*op_string)
e5cb08ac 7190 || *op_string == '(')
24eab124 7191 {
47926f60 7192 /* This is a memory reference of some sort. */
af6bdddf 7193 char *base_string;
252b5132 7194
47926f60 7195 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7196 char *displacement_string_start;
7197 char *displacement_string_end;
252b5132 7198
24eab124 7199 do_memory_reference:
24eab124 7200 if ((i.mem_operands == 1
40fb9820 7201 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7202 || i.mem_operands == 2)
7203 {
7204 as_bad (_("too many memory references for `%s'"),
7205 current_templates->start->name);
7206 return 0;
7207 }
252b5132 7208
24eab124
AM		 7209 /* Check for base index form. We detect the base index form by
7210 looking for an ')' at the end of the operand, searching
7211 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7212 after the '('. */
af6bdddf 7213 base_string = op_string + strlen (op_string);
c3332e24 7214
af6bdddf
AM		 7215 --base_string;
7216 if (is_space_char (*base_string))
7217 --base_string;
252b5132 7218
47926f60 7219 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7220 displacement_string_start = op_string;
7221 displacement_string_end = base_string + 1;
252b5132 7222
24eab124
AM		 7223 if (*base_string == ')')
7224 {
af6bdddf 7225 char *temp_string;
24eab124
AM		 7226 unsigned int parens_balanced = 1;
7227 /* We've already checked that the number of left & right ()'s are
47926f60 7228 equal, so this loop will not be infinite. */
24eab124
AM		 7229 do
7230 {
7231 base_string--;
7232 if (*base_string == ')')
7233 parens_balanced++;
7234 if (*base_string == '(')
7235 parens_balanced--;
7236 }
7237 while (parens_balanced);
c3332e24 7238
af6bdddf 7239 temp_string = base_string;
c3332e24 7240
24eab124 7241 /* Skip past '(' and whitespace. */
252b5132
RH		 7242 ++base_string;
7243 if (is_space_char (*base_string))
24eab124 7244 ++base_string;
252b5132 7245
af6bdddf 7246 if (*base_string == ','
4eed87de
AM		 7247 || ((i.base_reg = parse_register (base_string, &end_op))
7248 != NULL))
252b5132 7249 {
af6bdddf 7250 displacement_string_end = temp_string;
252b5132 7251
40fb9820 7252 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7253
af6bdddf 7254 if (i.base_reg)
24eab124 7255 {
24eab124
AM		 7256 base_string = end_op;
7257 if (is_space_char (*base_string))
7258 ++base_string;
af6bdddf
AM		 7259 }
7260
7261 /* There may be an index reg or scale factor here. */
7262 if (*base_string == ',')
7263 {
7264 ++base_string;
7265 if (is_space_char (*base_string))
7266 ++base_string;
7267
4eed87de
AM		 7268 if ((i.index_reg = parse_register (base_string, &end_op))
7269 != NULL)
24eab124 7270 {
af6bdddf 7271 base_string = end_op;
24eab124
AM		 7272 if (is_space_char (*base_string))
7273 ++base_string;
af6bdddf
AM		 7274 if (*base_string == ',')
7275 {
7276 ++base_string;
7277 if (is_space_char (*base_string))
7278 ++base_string;
7279 }
e5cb08ac 7280 else if (*base_string != ')')
af6bdddf 7281 {
4eed87de
AM		 7282 as_bad (_("expecting `,' or `)' "
7283 "after index register in `%s'"),
af6bdddf
AM		 7284 operand_string);
7285 return 0;
7286 }
24eab124 7287 }
af6bdddf 7288 else if (*base_string == REGISTER_PREFIX)
24eab124 7289 {
af6bdddf 7290 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7291 return 0;
7292 }
252b5132 7293
47926f60 7294 /* Check for scale factor. */
551c1ca1 7295 if (*base_string != ')')
af6bdddf 7296 {
551c1ca1
AM		 7297 char *end_scale = i386_scale (base_string);
7298
7299 if (!end_scale)
af6bdddf 7300 return 0;
24eab124 7301
551c1ca1 7302 base_string = end_scale;
af6bdddf
AM		 7303 if (is_space_char (*base_string))
7304 ++base_string;
7305 if (*base_string != ')')
7306 {
4eed87de
AM		 7307 as_bad (_("expecting `)' "
7308 "after scale factor in `%s'"),
af6bdddf
AM		 7309 operand_string);
7310 return 0;
7311 }
7312 }
7313 else if (!i.index_reg)
24eab124 7314 {
4eed87de
AM		 7315 as_bad (_("expecting index register or scale factor "
7316 "after `,'; got '%c'"),
af6bdddf 7317 *base_string);
24eab124
AM		 7318 return 0;
7319 }
7320 }
af6bdddf 7321 else if (*base_string != ')')
24eab124 7322 {
4eed87de
AM		 7323 as_bad (_("expecting `,' or `)' "
7324 "after base register in `%s'"),
af6bdddf 7325 operand_string);
24eab124
AM		 7326 return 0;
7327 }
c3332e24 7328 }
af6bdddf 7329 else if (*base_string == REGISTER_PREFIX)
c3332e24 7330 {
af6bdddf 7331 as_bad (_("bad register name `%s'"), base_string);
24eab124 7332 return 0;
c3332e24 7333 }
24eab124
AM		 7334 }
7335
7336 /* If there's an expression beginning the operand, parse it,
7337 assuming displacement_string_start and
7338 displacement_string_end are meaningful. */
7339 if (displacement_string_start != displacement_string_end)
7340 {
7341 if (!i386_displacement (displacement_string_start,
7342 displacement_string_end))
7343 return 0;
7344 }
7345
7346 /* Special case for (%dx) while doing input/output op. */
7347 if (i.base_reg
0dfbf9d7
L		 7348 && operand_type_equal (&i.base_reg->reg_type,
7349 &reg16_inoutportreg)
24eab124
AM		 7350 && i.index_reg == 0
7351 && i.log2_scale_factor == 0
7352 && i.seg[i.mem_operands] == 0
40fb9820 7353 && !operand_type_check (i.types[this_operand], disp))
24eab124 7354 {
65da13b5 7355 i.types[this_operand] = inoutportreg;
24eab124
AM		 7356 return 1;
7357 }
7358
eecb386c
AM		 7359 if (i386_index_check (operand_string) == 0)
7360 return 0;
5c07affc 7361 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7362 i.mem_operands++;
7363 }
7364 else
ce8a8b2f
AM		 7365 {
7366 /* It's not a memory operand; argh! */
24eab124
AM		 7367 as_bad (_("invalid char %s beginning operand %d `%s'"),
7368 output_invalid (*op_string),
7369 this_operand + 1,
7370 op_string);
7371 return 0;
7372 }
47926f60 7373 return 1; /* Normal return. */
252b5132
RH		 7374}
7375\f
ee7fcc42
AM		 7376/* md_estimate_size_before_relax()
7377
7378 Called just before relax() for rs_machine_dependent frags. The x86
7379 assembler uses these frags to handle variable size jump
7380 instructions.
7381
7382 Any symbol that is now undefined will not become defined.
7383 Return the correct fr_subtype in the frag.
7384 Return the initial "guess for variable size of frag" to caller.
7385 The guess is actually the growth beyond the fixed part. Whatever
7386 we do to grow the fixed or variable part contributes to our
7387 returned value. */
7388
252b5132
RH		 7389int
7390md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 7391 fragS *fragP;
7392 segT segment;
252b5132 7393{
252b5132 7394 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7395 check for un-relaxable symbols. On an ELF system, we can't relax
7396 an externally visible symbol, because it may be overridden by a
7397 shared library. */
7398 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7399#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7400 || (IS_ELF
31312f95
AM		 7401 && (S_IS_EXTERNAL (fragP->fr_symbol)
7402 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 7403#endif
7404 )
252b5132 7405 {
b98ef147
AM		 7406 /* Symbol is undefined in this segment, or we need to keep a
7407 reloc so that weak symbols can be overridden. */
7408 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7409 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7410 unsigned char *opcode;
7411 int old_fr_fix;
f6af82bd 7412
ee7fcc42
AM		 7413 if (fragP->fr_var != NO_RELOC)
7414 reloc_type = fragP->fr_var;
b98ef147 7415 else if (size == 2)
f6af82bd
AM		 7416 reloc_type = BFD_RELOC_16_PCREL;
7417 else
7418 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7419
ee7fcc42
AM		 7420 old_fr_fix = fragP->fr_fix;
7421 opcode = (unsigned char *) fragP->fr_opcode;
7422
fddf5b5b 7423 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7424 {
fddf5b5b
AM		 7425 case UNCOND_JUMP:
7426 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7427 opcode[0] = 0xe9;
252b5132 7428 fragP->fr_fix += size;
062cd5e7
AS		 7429 fix_new (fragP, old_fr_fix, size,
7430 fragP->fr_symbol,
7431 fragP->fr_offset, 1,
7432 reloc_type);
252b5132
RH		 7433 break;
7434
fddf5b5b 7435 case COND_JUMP86:
412167cb
AM		 7436 if (size == 2
7437 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7438 {
7439 /* Negate the condition, and branch past an
7440 unconditional jump. */
7441 opcode[0] ^= 1;
7442 opcode[1] = 3;
7443 /* Insert an unconditional jump. */
7444 opcode[2] = 0xe9;
7445 /* We added two extra opcode bytes, and have a two byte
7446 offset. */
7447 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7448 fix_new (fragP, old_fr_fix + 2, 2,
7449 fragP->fr_symbol,
7450 fragP->fr_offset, 1,
7451 reloc_type);
fddf5b5b
AM		 7452 break;
7453 }
7454 /* Fall through. */
7455
7456 case COND_JUMP:
412167cb
AM		 7457 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7458 {
3e02c1cc
AM		 7459 fixS *fixP;
7460
412167cb 7461 fragP->fr_fix += 1;
3e02c1cc
AM		 7462 fixP = fix_new (fragP, old_fr_fix, 1,
7463 fragP->fr_symbol,
7464 fragP->fr_offset, 1,
7465 BFD_RELOC_8_PCREL);
7466 fixP->fx_signed = 1;
412167cb
AM		 7467 break;
7468 }
93c2a809 7469
24eab124 7470 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7471 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7472 opcode[1] = opcode[0] + 0x10;
f6af82bd 7473 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7474 /* We've added an opcode byte. */
7475 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7476 fix_new (fragP, old_fr_fix + 1, size,
7477 fragP->fr_symbol,
7478 fragP->fr_offset, 1,
7479 reloc_type);
252b5132 7480 break;
fddf5b5b
AM		 7481
7482 default:
7483 BAD_CASE (fragP->fr_subtype);
7484 break;
252b5132
RH		 7485 }
7486 frag_wane (fragP);
ee7fcc42 7487 return fragP->fr_fix - old_fr_fix;
252b5132 7488 }
93c2a809 7489
93c2a809
AM		 7490 /* Guess size depending on current relax state. Initially the relax
7491 state will correspond to a short jump and we return 1, because
7492 the variable part of the frag (the branch offset) is one byte
7493 long. However, we can relax a section more than once and in that
7494 case we must either set fr_subtype back to the unrelaxed state,
7495 or return the value for the appropriate branch. */
7496 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7497}
7498
47926f60
KH		 7499/* Called after relax() is finished.
7500
7501 In: Address of frag.
7502 fr_type == rs_machine_dependent.
7503 fr_subtype is what the address relaxed to.
7504
7505 Out: Any fixSs and constants are set up.
7506 Caller will turn frag into a ".space 0". */
7507
252b5132
RH		 7508void
7509md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7510 bfd *abfd ATTRIBUTE_UNUSED;
7511 segT sec ATTRIBUTE_UNUSED;
29b0f896 7512 fragS *fragP;
252b5132 7513{
29b0f896 7514 unsigned char *opcode;
252b5132 7515 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7516 offsetT target_address;
7517 offsetT opcode_address;
252b5132 7518 unsigned int extension = 0;
847f7ad4 7519 offsetT displacement_from_opcode_start;
252b5132
RH		 7520
7521 opcode = (unsigned char *) fragP->fr_opcode;
7522
47926f60 7523 /* Address we want to reach in file space. */
252b5132 7524 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7525
47926f60 7526 /* Address opcode resides at in file space. */
252b5132
RH		 7527 opcode_address = fragP->fr_address + fragP->fr_fix;
7528
47926f60 7529 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7530 displacement_from_opcode_start = target_address - opcode_address;
7531
fddf5b5b 7532 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7533 {
47926f60
KH		 7534 /* Don't have to change opcode. */
7535 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7536 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7537 }
7538 else
7539 {
7540 if (no_cond_jump_promotion
7541 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7542 as_warn_where (fragP->fr_file, fragP->fr_line,
7543 _("long jump required"));
252b5132 7544
fddf5b5b
AM		 7545 switch (fragP->fr_subtype)
7546 {
7547 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7548 extension = 4; /* 1 opcode + 4 displacement */
7549 opcode[0] = 0xe9;
7550 where_to_put_displacement = &opcode[1];
7551 break;
252b5132 7552
fddf5b5b
AM		 7553 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7554 extension = 2; /* 1 opcode + 2 displacement */
7555 opcode[0] = 0xe9;
7556 where_to_put_displacement = &opcode[1];
7557 break;
252b5132 7558
fddf5b5b
AM		 7559 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7560 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7561 extension = 5; /* 2 opcode + 4 displacement */
7562 opcode[1] = opcode[0] + 0x10;
7563 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7564 where_to_put_displacement = &opcode[2];
7565 break;
252b5132 7566
fddf5b5b
AM		 7567 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7568 extension = 3; /* 2 opcode + 2 displacement */
7569 opcode[1] = opcode[0] + 0x10;
7570 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7571 where_to_put_displacement = &opcode[2];
7572 break;
252b5132 7573
fddf5b5b
AM		 7574 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7575 extension = 4;
7576 opcode[0] ^= 1;
7577 opcode[1] = 3;
7578 opcode[2] = 0xe9;
7579 where_to_put_displacement = &opcode[3];
7580 break;
7581
7582 default:
7583 BAD_CASE (fragP->fr_subtype);
7584 break;
7585 }
252b5132 7586 }
fddf5b5b 7587
7b81dfbb
AJ		 7588 /* If size if less then four we are sure that the operand fits,
7589 but if it's 4, then it could be that the displacement is larger
7590 then -/+ 2GB. */
7591 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7592 && object_64bit
7593 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7594 + ((addressT) 1 << 31))
7595 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7596 {
7597 as_bad_where (fragP->fr_file, fragP->fr_line,
7598 _("jump target out of range"));
7599 /* Make us emit 0. */
7600 displacement_from_opcode_start = extension;
7601 }
47926f60 7602 /* Now put displacement after opcode. */
252b5132
RH		 7603 md_number_to_chars ((char *) where_to_put_displacement,
7604 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7605 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7606 fragP->fr_fix += extension;
7607}
7608\f
252b5132
RH		 7609/* Apply a fixup (fixS) to segment data, once it has been determined
7610 by our caller that we have all the info we need to fix it up.
7611
7612 On the 386, immediates, displacements, and data pointers are all in
7613 the same (little-endian) format, so we don't need to care about which
7614 we are handling. */
7615
94f592af 7616void
55cf6793 7617md_apply_fix (fixP, valP, seg)
47926f60
KH		 7618 /* The fix we're to put in. */
7619 fixS *fixP;
47926f60 7620 /* Pointer to the value of the bits. */
c6682705 7621 valueT *valP;
47926f60
KH		 7622 /* Segment fix is from. */
7623 segT seg ATTRIBUTE_UNUSED;
252b5132 7624{
94f592af 7625 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7626 valueT value = *valP;
252b5132 7627
f86103b7 7628#if !defined (TE_Mach)
93382f6d
AM		 7629 if (fixP->fx_pcrel)
7630 {
7631 switch (fixP->fx_r_type)
7632 {
5865bb77
ILT		 7633 default:
7634 break;
7635
d6ab8113
JB		 7636 case BFD_RELOC_64:
7637 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7638 break;
93382f6d 7639 case BFD_RELOC_32:
ae8887b5 7640 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7641 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7642 break;
7643 case BFD_RELOC_16:
7644 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7645 break;
7646 case BFD_RELOC_8:
7647 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7648 break;
7649 }
7650 }
252b5132 7651
a161fe53 7652 if (fixP->fx_addsy != NULL
31312f95 7653 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7654 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7655 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7656 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7657 && !use_rela_relocations)
252b5132 7658 {
31312f95
AM		 7659 /* This is a hack. There should be a better way to handle this.
7660 This covers for the fact that bfd_install_relocation will
7661 subtract the current location (for partial_inplace, PC relative
7662 relocations); see more below. */
252b5132 7663#ifndef OBJ_AOUT
718ddfc0 7664 if (IS_ELF
252b5132
RH		 7665#ifdef TE_PE
7666 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7667#endif
7668 )
7669 value += fixP->fx_where + fixP->fx_frag->fr_address;
7670#endif
7671#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7672 if (IS_ELF)
252b5132 7673 {
6539b54b 7674 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7675
6539b54b 7676 if ((sym_seg == seg
2f66722d 7677 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7678 && sym_seg != absolute_section))
ae6063d4 7679 && !generic_force_reloc (fixP))
2f66722d
AM		 7680 {
7681 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7682 bfd_install_relocation subtracts them out again. I think
7683 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7684 it. FIXME. */
7685 value += fixP->fx_where + fixP->fx_frag->fr_address;
7686 }
252b5132
RH		 7687 }
7688#endif
7689#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7690 /* For some reason, the PE format does not store a
7691 section address offset for a PC relative symbol. */
7692 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7693 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7694 value += md_pcrel_from (fixP);
7695#endif
7696 }
7697
7698 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7699 and we must not disappoint it. */
252b5132 7700#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7701 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7702 switch (fixP->fx_r_type)
7703 {
7704 case BFD_RELOC_386_PLT32:
3e73aa7c 7705 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7706 /* Make the jump instruction point to the address of the operand. At
7707 runtime we merely add the offset to the actual PLT entry. */
7708 value = -4;
7709 break;
31312f95 7710
13ae64f3
JJ		 7711 case BFD_RELOC_386_TLS_GD:
7712 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7713 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7714 case BFD_RELOC_386_TLS_IE:
7715 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7716 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7717 case BFD_RELOC_X86_64_TLSGD:
7718 case BFD_RELOC_X86_64_TLSLD:
7719 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7720 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7721 value = 0; /* Fully resolved at runtime. No addend. */
7722 /* Fallthrough */
7723 case BFD_RELOC_386_TLS_LE:
7724 case BFD_RELOC_386_TLS_LDO_32:
7725 case BFD_RELOC_386_TLS_LE_32:
7726 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7727 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7728 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7729 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7730 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7731 break;
7732
67a4f2b7
AO		 7733 case BFD_RELOC_386_TLS_DESC_CALL:
7734 case BFD_RELOC_X86_64_TLSDESC_CALL:
7735 value = 0; /* Fully resolved at runtime. No addend. */
7736 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7737 fixP->fx_done = 0;
7738 return;
7739
00f7efb6
JJ		 7740 case BFD_RELOC_386_GOT32:
7741 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7742 value = 0; /* Fully resolved at runtime. No addend. */
7743 break;
47926f60
KH		 7744
7745 case BFD_RELOC_VTABLE_INHERIT:
7746 case BFD_RELOC_VTABLE_ENTRY:
7747 fixP->fx_done = 0;
94f592af 7748 return;
47926f60
KH		 7749
7750 default:
7751 break;
7752 }
7753#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7754 *valP = value;
f86103b7 7755#endif /* !defined (TE_Mach) */
3e73aa7c 7756
3e73aa7c 7757 /* Are we finished with this relocation now? */
c6682705 7758 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 7759 fixP->fx_done = 1;
7760 else if (use_rela_relocations)
7761 {
7762 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7763 /* Remember value for tc_gen_reloc. */
7764 fixP->fx_addnumber = value;
3e73aa7c
JH		 7765 value = 0;
7766 }
f86103b7 7767
94f592af 7768 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7769}
252b5132 7770\f
252b5132 7771char *
499ac353 7772md_atof (int type, char *litP, int *sizeP)
252b5132 7773{
499ac353
NC		 7774 /* This outputs the LITTLENUMs in REVERSE order;
7775 in accord with the bigendian 386. */
7776 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7777}
7778\f
2d545b82 7779static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7780
252b5132 7781static char *
e3bb37b5 7782output_invalid (int c)
252b5132 7783{
3882b010 7784 if (ISPRINT (c))
f9f21a03
L		 7785 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7786 "'%c'", c);
252b5132 7787 else
f9f21a03 7788 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7789 "(0x%x)", (unsigned char) c);
252b5132
RH		 7790 return output_invalid_buf;
7791}
7792
af6bdddf 7793/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7794
7795static const reg_entry *
4d1bb795 7796parse_real_register (char *reg_string, char **end_op)
252b5132 7797{
af6bdddf
AM		 7798 char *s = reg_string;
7799 char *p;
252b5132
RH		 7800 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7801 const reg_entry *r;
7802
7803 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7804 if (*s == REGISTER_PREFIX)
7805 ++s;
7806
7807 if (is_space_char (*s))
7808 ++s;
7809
7810 p = reg_name_given;
af6bdddf 7811 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7812 {
7813 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7814 return (const reg_entry *) NULL;
7815 s++;
252b5132
RH		 7816 }
7817
6588847e
DN		 7818 /* For naked regs, make sure that we are not dealing with an identifier.
7819 This prevents confusing an identifier like `eax_var' with register
7820 `eax'. */
7821 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7822 return (const reg_entry *) NULL;
7823
af6bdddf 7824 *end_op = s;
252b5132
RH		 7825
7826 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7827
5f47d35b 7828 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7829 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7830 {
5f47d35b
AM		 7831 if (is_space_char (*s))
7832 ++s;
7833 if (*s == '(')
7834 {
af6bdddf 7835 ++s;
5f47d35b
AM		 7836 if (is_space_char (*s))
7837 ++s;
7838 if (*s >= '0' && *s <= '7')
7839 {
db557034 7840 int fpr = *s - '0';
af6bdddf 7841 ++s;
5f47d35b
AM		 7842 if (is_space_char (*s))
7843 ++s;
7844 if (*s == ')')
7845 {
7846 *end_op = s + 1;
db557034
AM		 7847 r = hash_find (reg_hash, "st(0)");
7848 know (r);
7849 return r + fpr;
5f47d35b 7850 }
5f47d35b 7851 }
47926f60 7852 /* We have "%st(" then garbage. */
5f47d35b
AM		 7853 return (const reg_entry *) NULL;
7854 }
7855 }
7856
a60de03c
JB		 7857 if (r == NULL || allow_pseudo_reg)
7858 return r;
7859
0dfbf9d7 7860 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7861 return (const reg_entry *) NULL;
7862
192dc9c6
JB		 7863 if ((r->reg_type.bitfield.reg32
7864 || r->reg_type.bitfield.sreg3
7865 || r->reg_type.bitfield.control
7866 || r->reg_type.bitfield.debug
7867 || r->reg_type.bitfield.test)
7868 && !cpu_arch_flags.bitfield.cpui386)
7869 return (const reg_entry *) NULL;
7870
7871 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7872 return (const reg_entry *) NULL;
7873
7874 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7875 return (const reg_entry *) NULL;
7876
40f12533
L		 7877 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7878 return (const reg_entry *) NULL;
7879
db51cc60 7880 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7881 if (!allow_index_reg
db51cc60
L		 7882 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7883 return (const reg_entry *) NULL;
7884
a60de03c
JB		 7885 if (((r->reg_flags & (RegRex64 | RegRex))
7886 || r->reg_type.bitfield.reg64)
40fb9820 7887 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7888 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7889 && flag_code != CODE_64BIT)
20f0a1fc 7890 return (const reg_entry *) NULL;
1ae00879 7891
b7240065
JB		 7892 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7893 return (const reg_entry *) NULL;
7894
252b5132
RH		 7895 return r;
7896}
4d1bb795
JB		 7897
7898/* REG_STRING starts *before* REGISTER_PREFIX. */
7899
7900static const reg_entry *
7901parse_register (char *reg_string, char **end_op)
7902{
7903 const reg_entry *r;
7904
7905 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7906 r = parse_real_register (reg_string, end_op);
7907 else
7908 r = NULL;
7909 if (!r)
7910 {
7911 char *save = input_line_pointer;
7912 char c;
7913 symbolS *symbolP;
7914
7915 input_line_pointer = reg_string;
7916 c = get_symbol_end ();
7917 symbolP = symbol_find (reg_string);
7918 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7919 {
7920 const expressionS *e = symbol_get_value_expression (symbolP);
7921
7922 know (e->X_op == O_register);
4eed87de 7923 know (e->X_add_number >= 0
c3fe08fa 7924 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7925 r = i386_regtab + e->X_add_number;
7926 *end_op = input_line_pointer;
7927 }
7928 *input_line_pointer = c;
7929 input_line_pointer = save;
7930 }
7931 return r;
7932}
7933
7934int
7935i386_parse_name (char *name, expressionS *e, char *nextcharP)
7936{
7937 const reg_entry *r;
7938 char *end = input_line_pointer;
7939
7940 *end = *nextcharP;
7941 r = parse_register (name, &input_line_pointer);
7942 if (r && end <= input_line_pointer)
7943 {
7944 *nextcharP = *input_line_pointer;
7945 *input_line_pointer = 0;
7946 e->X_op = O_register;
7947 e->X_add_number = r - i386_regtab;
7948 return 1;
7949 }
7950 input_line_pointer = end;
7951 *end = 0;
7952 return 0;
7953}
7954
7955void
7956md_operand (expressionS *e)
7957{
7958 if (*input_line_pointer == REGISTER_PREFIX)
7959 {
7960 char *end;
7961 const reg_entry *r = parse_real_register (input_line_pointer, &end);
7962
7963 if (r)
7964 {
7965 e->X_op = O_register;
7966 e->X_add_number = r - i386_regtab;
7967 input_line_pointer = end;
7968 }
7969 }
7970}
7971
252b5132 7972\f
4cc782b5 7973#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7974const char *md_shortopts = "kVQ:sqn";
252b5132 7975#else
12b55ccc 7976const char *md_shortopts = "qn";
252b5132 7977#endif
6e0b89ee 7978
3e73aa7c 7979#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7980#define OPTION_64 (OPTION_MD_BASE + 1)
7981#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7982#define OPTION_MARCH (OPTION_MD_BASE + 3)
7983#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 7984#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7985#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7986#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7987#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7988#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 7989#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 7990#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
b3b91714 7991
99ad8390
NC		 7992struct option md_longopts[] =
7993{
3e73aa7c 7994 {"32", no_argument, NULL, OPTION_32},
99ad8390 7995#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 7996 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7997#endif
b3b91714 7998 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7999 {"march", required_argument, NULL, OPTION_MARCH},
8000 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 8001 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
8002 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
8003 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
8004 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
8005 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 8006 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 8007 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
252b5132
RH		 8008 {NULL, no_argument, NULL, 0}
8009};
8010size_t md_longopts_size = sizeof (md_longopts);
8011
8012int
9103f4f4 8013md_parse_option (int c, char *arg)
252b5132 8014{
9103f4f4 8015 unsigned int i;
6305a203 8016 char *arch, *next;
9103f4f4 8017
252b5132
RH		 8018 switch (c)
8019 {
12b55ccc
L		 8020 case 'n':
8021 optimize_align_code = 0;
8022 break;
8023
a38cf1db
AM		 8024 case 'q':
8025 quiet_warnings = 1;
252b5132
RH		 8026 break;
8027
8028#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 8029 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8030 should be emitted or not. FIXME: Not implemented. */
8031 case 'Q':
252b5132
RH		 8032 break;
8033
8034 /* -V: SVR4 argument to print version ID. */
8035 case 'V':
8036 print_version_id ();
8037 break;
8038
a38cf1db
AM		 8039 /* -k: Ignore for FreeBSD compatibility. */
8040 case 'k':
252b5132 8041 break;
4cc782b5
ILT		 8042
8043 case 's':
8044 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 8045 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 8046 break;
99ad8390
NC		 8047#endif
8048#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 8049 case OPTION_64:
8050 {
8051 const char **list, **l;
8052
3e73aa7c
JH		 8053 list = bfd_target_list ();
8054 for (l = list; *l != NULL; l++)
8620418b 8055 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 8056 || strcmp (*l, "coff-x86-64") == 0
8057 || strcmp (*l, "pe-x86-64") == 0
8058 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 8059 {
8060 default_arch = "x86_64";
8061 break;
8062 }
3e73aa7c 8063 if (*l == NULL)
6e0b89ee 8064 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 8065 free (list);
8066 }
8067 break;
8068#endif
252b5132 8069
6e0b89ee
AM		 8070 case OPTION_32:
8071 default_arch = "i386";
8072 break;
8073
b3b91714
AM		 8074 case OPTION_DIVIDE:
8075#ifdef SVR4_COMMENT_CHARS
8076 {
8077 char *n, *t;
8078 const char *s;
8079
8080 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
8081 t = n;
8082 for (s = i386_comment_chars; *s != '\0'; s++)
8083 if (*s != '/')
8084 *t++ = *s;
8085 *t = '\0';
8086 i386_comment_chars = n;
8087 }
8088#endif
8089 break;
8090
9103f4f4 8091 case OPTION_MARCH:
6305a203
L		 8092 arch = xstrdup (arg);
8093 do
9103f4f4 8094 {
6305a203
L		 8095 if (*arch == '.')
8096 as_fatal (_("Invalid -march= option: `%s'"), arg);
8097 next = strchr (arch, '+');
8098 if (next)
8099 *next++ = '\0';
8100 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
9103f4f4 8101 {
6305a203 8102 if (strcmp (arch, cpu_arch [i].name) == 0)
ccc9c027 8103 {
6305a203
L		 8104 /* Processor. */
8105 cpu_arch_name = cpu_arch[i].name;
8106 cpu_sub_arch_name = NULL;
8107 cpu_arch_flags = cpu_arch[i].flags;
8108 cpu_arch_isa = cpu_arch[i].type;
8109 cpu_arch_isa_flags = cpu_arch[i].flags;
8110 if (!cpu_arch_tune_set)
8111 {
8112 cpu_arch_tune = cpu_arch_isa;
8113 cpu_arch_tune_flags = cpu_arch_isa_flags;
8114 }
8115 break;
8116 }
8117 else if (*cpu_arch [i].name == '.'
8118 && strcmp (arch, cpu_arch [i].name + 1) == 0)
8119 {
8120 /* ISA entension. */
8121 i386_cpu_flags flags;
8122 flags = cpu_flags_or (cpu_arch_flags,
8123 cpu_arch[i].flags);
0dfbf9d7 8124 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8125 {
8126 if (cpu_sub_arch_name)
8127 {
8128 char *name = cpu_sub_arch_name;
8129 cpu_sub_arch_name = concat (name,
8130 cpu_arch[i].name,
1bf57e9f 8131 (const char *) NULL);
6305a203
L		 8132 free (name);
8133 }
8134 else
8135 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
8136 cpu_arch_flags = flags;
8137 }
8138 break;
ccc9c027 8139 }
9103f4f4 8140 }
6305a203
L		 8141
8142 if (i >= ARRAY_SIZE (cpu_arch))
8143 as_fatal (_("Invalid -march= option: `%s'"), arg);
8144
8145 arch = next;
9103f4f4 8146 }
6305a203 8147 while (next != NULL );
9103f4f4
L		 8148 break;
8149
8150 case OPTION_MTUNE:
8151 if (*arg == '.')
8152 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8153 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
8154 {
8155 if (strcmp (arg, cpu_arch [i].name) == 0)
8156 {
ccc9c027 8157 cpu_arch_tune_set = 1;
9103f4f4
L		 8158 cpu_arch_tune = cpu_arch [i].type;
8159 cpu_arch_tune_flags = cpu_arch[i].flags;
8160 break;
8161 }
8162 }
8163 if (i >= ARRAY_SIZE (cpu_arch))
8164 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8165 break;
8166
1efbbeb4
L		 8167 case OPTION_MMNEMONIC:
8168 if (strcasecmp (arg, "att") == 0)
8169 intel_mnemonic = 0;
8170 else if (strcasecmp (arg, "intel") == 0)
8171 intel_mnemonic = 1;
8172 else
8173 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
8174 break;
8175
8176 case OPTION_MSYNTAX:
8177 if (strcasecmp (arg, "att") == 0)
8178 intel_syntax = 0;
8179 else if (strcasecmp (arg, "intel") == 0)
8180 intel_syntax = 1;
8181 else
8182 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
8183 break;
8184
8185 case OPTION_MINDEX_REG:
8186 allow_index_reg = 1;
8187 break;
8188
8189 case OPTION_MNAKED_REG:
8190 allow_naked_reg = 1;
8191 break;
8192
8193 case OPTION_MOLD_GCC:
8194 old_gcc = 1;
1efbbeb4
L		 8195 break;
8196
c0f3af97
L		 8197 case OPTION_MSSE2AVX:
8198 sse2avx = 1;
8199 break;
8200
daf50ae7
L		 8201 case OPTION_MSSE_CHECK:
8202 if (strcasecmp (arg, "error") == 0)
8203 sse_check = sse_check_error;
8204 else if (strcasecmp (arg, "warning") == 0)
8205 sse_check = sse_check_warning;
8206 else if (strcasecmp (arg, "none") == 0)
8207 sse_check = sse_check_none;
8208 else
8209 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
8210 break;
8211
252b5132
RH		 8212 default:
8213 return 0;
8214 }
8215 return 1;
8216}
8217
8218void
8219md_show_usage (stream)
8220 FILE *stream;
8221{
4cc782b5
ILT		 8222#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8223 fprintf (stream, _("\
a38cf1db
AM		 8224 -Q ignored\n\
8225 -V print assembler version number\n\
b3b91714
AM		 8226 -k ignored\n"));
8227#endif
8228 fprintf (stream, _("\
12b55ccc 8229 -n Do not optimize code alignment\n\
b3b91714
AM		 8230 -q quieten some warnings\n"));
8231#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8232 fprintf (stream, _("\
a38cf1db 8233 -s ignored\n"));
b3b91714 8234#endif
751d281c
L		 8235#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8236 fprintf (stream, _("\
8237 --32/--64 generate 32bit/64bit code\n"));
8238#endif
b3b91714
AM		 8239#ifdef SVR4_COMMENT_CHARS
8240 fprintf (stream, _("\
8241 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8242#else
8243 fprintf (stream, _("\
b3b91714 8244 --divide ignored\n"));
4cc782b5 8245#endif
9103f4f4 8246 fprintf (stream, _("\
6305a203
L		 8247 -march=CPU[,+EXTENSION...]\n\
8248 generate code for CPU and EXTENSION, CPU is one of:\n\
2cb4f3d5
L		 8249 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8250 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8251 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8252 generic32, generic64\n\
599121aa
L		 8253 EXTENSION is combination of:\n\
8254 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
f1f8f695
L		 8255 avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
8256 3dnow, 3dnowa, sse4a, sse5, svme, abm, padlock\n"));
6305a203 8257 fprintf (stream, _("\
2cb4f3d5
L		 8258 -mtune=CPU optimize for CPU, CPU is one of:\n\
8259 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8260 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8261 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8262 generic32, generic64\n"));
ba104c83 8263 fprintf (stream, _("\
c0f3af97
L		 8264 -msse2avx encode SSE instructions with VEX prefix\n"));
8265 fprintf (stream, _("\
daf50ae7
L		 8266 -msse-check=[none|error|warning]\n\
8267 check SSE instructions\n"));
8268 fprintf (stream, _("\
ba104c83
L		 8269 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8270 fprintf (stream, _("\
8271 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8272 fprintf (stream, _("\
8273 -mindex-reg support pseudo index registers\n"));
8274 fprintf (stream, _("\
8275 -mnaked-reg don't require `%%' prefix for registers\n"));
8276 fprintf (stream, _("\
8277 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8278}
8279
3e73aa7c 8280#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 8281 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH		 8282
8283/* Pick the target format to use. */
8284
47926f60 8285const char *
e3bb37b5 8286i386_target_format (void)
252b5132 8287{
3e73aa7c 8288 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 8289 {
8290 set_code_flag (CODE_64BIT);
0dfbf9d7 8291 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8292 {
8293 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8294 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8295 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8296 cpu_arch_isa_flags.bitfield.cpui486 = 1;
8297 cpu_arch_isa_flags.bitfield.cpui586 = 1;
8298 cpu_arch_isa_flags.bitfield.cpui686 = 1;
8299 cpu_arch_isa_flags.bitfield.cpup4 = 1;
8300 cpu_arch_isa_flags.bitfield.cpummx= 1;
40fb9820
L		 8301 cpu_arch_isa_flags.bitfield.cpusse = 1;
8302 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
8303 }
0dfbf9d7 8304 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8305 {
8306 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8307 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8308 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8309 cpu_arch_tune_flags.bitfield.cpui486 = 1;
8310 cpu_arch_tune_flags.bitfield.cpui586 = 1;
8311 cpu_arch_tune_flags.bitfield.cpui686 = 1;
8312 cpu_arch_tune_flags.bitfield.cpup4 = 1;
8313 cpu_arch_tune_flags.bitfield.cpummx= 1;
40fb9820
L		 8314 cpu_arch_tune_flags.bitfield.cpusse = 1;
8315 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
8316 }
9103f4f4 8317 }
3e73aa7c 8318 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 8319 {
8320 set_code_flag (CODE_32BIT);
0dfbf9d7 8321 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8322 {
8323 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8324 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8325 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8326 }
0dfbf9d7 8327 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8328 {
8329 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8330 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8331 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8332 }
9103f4f4 8333 }
3e73aa7c
JH		 8334 else
8335 as_fatal (_("Unknown architecture"));
252b5132
RH		 8336 switch (OUTPUT_FLAVOR)
8337 {
872ce6ff
L		 8338#ifdef TE_PEP
8339 case bfd_target_coff_flavour:
8340 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
8341 break;
8342#endif
4c63da97
AM		 8343#ifdef OBJ_MAYBE_AOUT
8344 case bfd_target_aout_flavour:
47926f60 8345 return AOUT_TARGET_FORMAT;
4c63da97
AM		 8346#endif
8347#ifdef OBJ_MAYBE_COFF
252b5132
RH		 8348 case bfd_target_coff_flavour:
8349 return "coff-i386";
4c63da97 8350#endif
3e73aa7c 8351#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8352 case bfd_target_elf_flavour:
3e73aa7c 8353 {
e5cb08ac 8354 if (flag_code == CODE_64BIT)
4fa24527
JB		 8355 {
8356 object_64bit = 1;
8357 use_rela_relocations = 1;
8358 }
9d7cbccd 8359 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 8360 }
4c63da97 8361#endif
252b5132
RH		 8362 default:
8363 abort ();
8364 return NULL;
8365 }
8366}
8367
47926f60 8368#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8369
8370#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8371void
8372i386_elf_emit_arch_note (void)
a847613f 8373{
718ddfc0 8374 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8375 {
8376 char *p;
8377 asection *seg = now_seg;
8378 subsegT subseg = now_subseg;
8379 Elf_Internal_Note i_note;
8380 Elf_External_Note e_note;
8381 asection *note_secp;
8382 int len;
8383
8384 /* Create the .note section. */
8385 note_secp = subseg_new (".note", 0);
8386 bfd_set_section_flags (stdoutput,
8387 note_secp,
8388 SEC_HAS_CONTENTS | SEC_READONLY);
8389
8390 /* Process the arch string. */
8391 len = strlen (cpu_arch_name);
8392
8393 i_note.namesz = len + 1;
8394 i_note.descsz = 0;
8395 i_note.type = NT_ARCH;
8396 p = frag_more (sizeof (e_note.namesz));
8397 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8398 p = frag_more (sizeof (e_note.descsz));
8399 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8400 p = frag_more (sizeof (e_note.type));
8401 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8402 p = frag_more (len + 1);
8403 strcpy (p, cpu_arch_name);
8404
8405 frag_align (2, 0, 0);
8406
8407 subseg_set (seg, subseg);
8408 }
8409}
8410#endif
252b5132 8411\f
252b5132
RH		 8412symbolS *
8413md_undefined_symbol (name)
8414 char *name;
8415{
18dc2407
ILT		 8416 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8417 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8418 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8419 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8420 {
8421 if (!GOT_symbol)
8422 {
8423 if (symbol_find (name))
8424 as_bad (_("GOT already in symbol table"));
8425 GOT_symbol = symbol_new (name, undefined_section,
8426 (valueT) 0, &zero_address_frag);
8427 };
8428 return GOT_symbol;
8429 }
252b5132
RH		 8430 return 0;
8431}
8432
8433/* Round up a section size to the appropriate boundary. */
47926f60 8434
252b5132
RH		 8435valueT
8436md_section_align (segment, size)
ab9da554 8437 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8438 valueT size;
8439{
4c63da97
AM		 8440#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8441 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8442 {
8443 /* For a.out, force the section size to be aligned. If we don't do
8444 this, BFD will align it for us, but it will not write out the
8445 final bytes of the section. This may be a bug in BFD, but it is
8446 easier to fix it here since that is how the other a.out targets
8447 work. */
8448 int align;
8449
8450 align = bfd_get_section_alignment (stdoutput, segment);
8451 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8452 }
252b5132
RH		 8453#endif
8454
8455 return size;
8456}
8457
8458/* On the i386, PC-relative offsets are relative to the start of the
8459 next instruction. That is, the address of the offset, plus its
8460 size, since the offset is always the last part of the insn. */
8461
8462long
e3bb37b5 8463md_pcrel_from (fixS *fixP)
252b5132
RH		 8464{
8465 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8466}
8467
8468#ifndef I386COFF
8469
8470static void
e3bb37b5 8471s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8472{
29b0f896 8473 int temp;
252b5132 8474
8a75718c
JB		 8475#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8476 if (IS_ELF)
8477 obj_elf_section_change_hook ();
8478#endif
252b5132
RH		 8479 temp = get_absolute_expression ();
8480 subseg_set (bss_section, (subsegT) temp);
8481 demand_empty_rest_of_line ();
8482}
8483
8484#endif
8485
252b5132 8486void
e3bb37b5 8487i386_validate_fix (fixS *fixp)
252b5132
RH		 8488{
8489 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8490 {
23df1078
JH		 8491 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8492 {
4fa24527 8493 if (!object_64bit)
23df1078
JH		 8494 abort ();
8495 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8496 }
8497 else
8498 {
4fa24527 8499 if (!object_64bit)
d6ab8113
JB		 8500 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8501 else
8502 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8503 }
252b5132
RH		 8504 fixp->fx_subsy = 0;
8505 }
8506}
8507
252b5132
RH		 8508arelent *
8509tc_gen_reloc (section, fixp)
ab9da554 8510 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8511 fixS *fixp;
8512{
8513 arelent *rel;
8514 bfd_reloc_code_real_type code;
8515
8516 switch (fixp->fx_r_type)
8517 {
3e73aa7c
JH		 8518 case BFD_RELOC_X86_64_PLT32:
8519 case BFD_RELOC_X86_64_GOT32:
8520 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8521 case BFD_RELOC_386_PLT32:
8522 case BFD_RELOC_386_GOT32:
8523 case BFD_RELOC_386_GOTOFF:
8524 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8525 case BFD_RELOC_386_TLS_GD:
8526 case BFD_RELOC_386_TLS_LDM:
8527 case BFD_RELOC_386_TLS_LDO_32:
8528 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8529 case BFD_RELOC_386_TLS_IE:
8530 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8531 case BFD_RELOC_386_TLS_LE_32:
8532 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8533 case BFD_RELOC_386_TLS_GOTDESC:
8534 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8535 case BFD_RELOC_X86_64_TLSGD:
8536 case BFD_RELOC_X86_64_TLSLD:
8537 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8538 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8539 case BFD_RELOC_X86_64_GOTTPOFF:
8540 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8541 case BFD_RELOC_X86_64_TPOFF64:
8542 case BFD_RELOC_X86_64_GOTOFF64:
8543 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8544 case BFD_RELOC_X86_64_GOT64:
8545 case BFD_RELOC_X86_64_GOTPCREL64:
8546 case BFD_RELOC_X86_64_GOTPC64:
8547 case BFD_RELOC_X86_64_GOTPLT64:
8548 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8549 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8550 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8551 case BFD_RELOC_RVA:
8552 case BFD_RELOC_VTABLE_ENTRY:
8553 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8554#ifdef TE_PE
8555 case BFD_RELOC_32_SECREL:
8556#endif
252b5132
RH		 8557 code = fixp->fx_r_type;
8558 break;
dbbaec26
L		 8559 case BFD_RELOC_X86_64_32S:
8560 if (!fixp->fx_pcrel)
8561 {
8562 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8563 code = fixp->fx_r_type;
8564 break;
8565 }
252b5132 8566 default:
93382f6d 8567 if (fixp->fx_pcrel)
252b5132 8568 {
93382f6d
AM		 8569 switch (fixp->fx_size)
8570 {
8571 default:
b091f402
AM		 8572 as_bad_where (fixp->fx_file, fixp->fx_line,
8573 _("can not do %d byte pc-relative relocation"),
8574 fixp->fx_size);
93382f6d
AM		 8575 code = BFD_RELOC_32_PCREL;
8576 break;
8577 case 1: code = BFD_RELOC_8_PCREL; break;
8578 case 2: code = BFD_RELOC_16_PCREL; break;
8579 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8580#ifdef BFD64
8581 case 8: code = BFD_RELOC_64_PCREL; break;
8582#endif
93382f6d
AM		 8583 }
8584 }
8585 else
8586 {
8587 switch (fixp->fx_size)
8588 {
8589 default:
b091f402
AM		 8590 as_bad_where (fixp->fx_file, fixp->fx_line,
8591 _("can not do %d byte relocation"),
8592 fixp->fx_size);
93382f6d
AM		 8593 code = BFD_RELOC_32;
8594 break;
8595 case 1: code = BFD_RELOC_8; break;
8596 case 2: code = BFD_RELOC_16; break;
8597 case 4: code = BFD_RELOC_32; break;
937149dd 8598#ifdef BFD64
3e73aa7c 8599 case 8: code = BFD_RELOC_64; break;
937149dd 8600#endif
93382f6d 8601 }
252b5132
RH		 8602 }
8603 break;
8604 }
252b5132 8605
d182319b
JB		 8606 if ((code == BFD_RELOC_32
8607 || code == BFD_RELOC_32_PCREL
8608 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8609 && GOT_symbol
8610 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8611 {
4fa24527 8612 if (!object_64bit)
d6ab8113
JB		 8613 code = BFD_RELOC_386_GOTPC;
8614 else
8615 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8616 }
7b81dfbb
AJ		 8617 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8618 && GOT_symbol
8619 && fixp->fx_addsy == GOT_symbol)
8620 {
8621 code = BFD_RELOC_X86_64_GOTPC64;
8622 }
252b5132
RH		 8623
8624 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8625 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8626 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8627
8628 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8629
3e73aa7c
JH		 8630 if (!use_rela_relocations)
8631 {
8632 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8633 vtable entry to be used in the relocation's section offset. */
8634 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8635 rel->address = fixp->fx_offset;
252b5132 8636
c6682705 8637 rel->addend = 0;
3e73aa7c
JH		 8638 }
8639 /* Use the rela in 64bit mode. */
252b5132 8640 else
3e73aa7c 8641 {
062cd5e7
AS		 8642 if (!fixp->fx_pcrel)
8643 rel->addend = fixp->fx_offset;
8644 else
8645 switch (code)
8646 {
8647 case BFD_RELOC_X86_64_PLT32:
8648 case BFD_RELOC_X86_64_GOT32:
8649 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8650 case BFD_RELOC_X86_64_TLSGD:
8651 case BFD_RELOC_X86_64_TLSLD:
8652 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8653 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8654 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8655 rel->addend = fixp->fx_offset - fixp->fx_size;
8656 break;
8657 default:
8658 rel->addend = (section->vma
8659 - fixp->fx_size
8660 + fixp->fx_addnumber
8661 + md_pcrel_from (fixp));
8662 break;
8663 }
3e73aa7c
JH		 8664 }
8665
252b5132
RH		 8666 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8667 if (rel->howto == NULL)
8668 {
8669 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8670 _("cannot represent relocation type %s"),
252b5132
RH		 8671 bfd_get_reloc_code_name (code));
8672 /* Set howto to a garbage value so that we can keep going. */
8673 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
8674 assert (rel->howto != NULL);
8675 }
8676
8677 return rel;
8678}
8679
64a0c779
DN		 8680\f
8681/* Parse operands using Intel syntax. This implements a recursive descent
8682 parser based on the BNF grammar published in Appendix B of the MASM 6.1
8683 Programmer's Guide.
8684
8685 FIXME: We do not recognize the full operand grammar defined in the MASM
8686 documentation. In particular, all the structure/union and
8687 high-level macro operands are missing.
8688
8689 Uppercase words are terminals, lower case words are non-terminals.
8690 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
8691 bars '|' denote choices. Most grammar productions are implemented in
8692 functions called 'intel_<production>'.
8693
8694 Initial production is 'expr'.
8695
9306ca4a 8696 addOp + | -
64a0c779
DN		 8697
8698 alpha [a-zA-Z]
8699
9306ca4a
JB		 8700 binOp & | AND | \| | OR | ^ | XOR
8701
64a0c779
DN		 8702 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
8703
8704 constant digits [[ radixOverride ]]
8705
c0f3af97 8706 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD | YMMWORD
64a0c779
DN		 8707
8708 digits decdigit
b77a7acd
AJ		 8709 | digits decdigit
8710 | digits hexdigit
64a0c779
DN		 8711
8712 decdigit [0-9]
8713
9306ca4a
JB		 8714 e04 e04 addOp e05
8715 | e05
8716
8717 e05 e05 binOp e06
b77a7acd 8718 | e06
64a0c779
DN		 8719
8720 e06 e06 mulOp e09
b77a7acd 8721 | e09
64a0c779
DN		 8722
8723 e09 OFFSET e10
a724f0f4
JB		 8724 | SHORT e10
8725 | + e10
8726 | - e10
9306ca4a
JB		 8727 | ~ e10
8728 | NOT e10
64a0c779
DN		 8729 | e09 PTR e10
8730 | e09 : e10
8731 | e10
8732
8733 e10 e10 [ expr ]
b77a7acd 8734 | e11
64a0c779
DN		 8735
8736 e11 ( expr )
b77a7acd 8737 | [ expr ]
64a0c779
DN		 8738 | constant
8739 | dataType
8740 | id
8741 | $
8742 | register
8743
a724f0f4 8744 => expr expr cmpOp e04
9306ca4a 8745 | e04
64a0c779
DN		 8746
8747 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 8748 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 8749
8750 hexdigit a | b | c | d | e | f
b77a7acd 8751 | A | B | C | D | E | F
64a0c779
DN		 8752
8753 id alpha
b77a7acd 8754 | id alpha
64a0c779
DN		 8755 | id decdigit
8756
9306ca4a 8757 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 8758
8759 quote " | '
8760
8761 register specialRegister
b77a7acd 8762 | gpRegister
64a0c779
DN		 8763 | byteRegister
8764
8765 segmentRegister CS | DS | ES | FS | GS | SS
8766
9306ca4a 8767 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 8768 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 8769 | TR3 | TR4 | TR5 | TR6 | TR7
8770
64a0c779
DN		 8771 We simplify the grammar in obvious places (e.g., register parsing is
8772 done by calling parse_register) and eliminate immediate left recursion
8773 to implement a recursive-descent parser.
8774
a724f0f4
JB		 8775 expr e04 expr'
8776
8777 expr' cmpOp e04 expr'
8778 | Empty
9306ca4a
JB		 8779
8780 e04 e05 e04'
8781
8782 e04' addOp e05 e04'
8783 | Empty
64a0c779
DN		 8784
8785 e05 e06 e05'
8786
9306ca4a 8787 e05' binOp e06 e05'
b77a7acd 8788 | Empty
64a0c779
DN		 8789
8790 e06 e09 e06'
8791
8792 e06' mulOp e09 e06'
b77a7acd 8793 | Empty
64a0c779
DN		 8794
8795 e09 OFFSET e10 e09'
a724f0f4
JB		 8796 | SHORT e10'
8797 | + e10'
8798 | - e10'
8799 | ~ e10'
8800 | NOT e10'
b77a7acd 8801 | e10 e09'
64a0c779
DN		 8802
8803 e09' PTR e10 e09'
b77a7acd 8804 | : e10 e09'
64a0c779
DN		 8805 | Empty
8806
8807 e10 e11 e10'
8808
8809 e10' [ expr ] e10'
b77a7acd 8810 | Empty
64a0c779
DN		 8811
8812 e11 ( expr )
b77a7acd 8813 | [ expr ]
64a0c779
DN		 8814 | BYTE
8815 | WORD
8816 | DWORD
9306ca4a 8817 | FWORD
64a0c779 8818 | QWORD
9306ca4a
JB		 8819 | TBYTE
8820 | OWORD
8821 | XMMWORD
c0f3af97 8822 | YMMWORD
64a0c779
DN		 8823 | .
8824 | $
8825 | register
8826 | id
8827 | constant */
8828
8829/* Parsing structure for the intel syntax parser. Used to implement the
8830 semantic actions for the operand grammar. */
8831struct intel_parser_s
8832 {
8833 char *op_string; /* The string being parsed. */
8834 int got_a_float; /* Whether the operand is a float. */
4a1805b1 8835 int op_modifier; /* Operand modifier. */
64a0c779 8836 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 8837 int in_offset; /* >=1 if parsing operand of offset. */
8838 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 8839 const reg_entry *reg; /* Last register reference found. */
8840 char *disp; /* Displacement string being built. */
a724f0f4 8841 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 8842 };
8843
8844static struct intel_parser_s intel_parser;
8845
8846/* Token structure for parsing intel syntax. */
8847struct intel_token
8848 {
8849 int code; /* Token code. */
8850 const reg_entry *reg; /* Register entry for register tokens. */
8851 char *str; /* String representation. */
8852 };
8853
8854static struct intel_token cur_token, prev_token;
8855
50705ef4
AM		 8856/* Token codes for the intel parser. Since T_SHORT is already used
8857 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 8858#define T_NIL -1
8859#define T_CONST 1
8860#define T_REG 2
8861#define T_BYTE 3
8862#define T_WORD 4
9306ca4a
JB		 8863#define T_DWORD 5
8864#define T_FWORD 6
8865#define T_QWORD 7
8866#define T_TBYTE 8
8867#define T_XMMWORD 9
50705ef4 8868#undef T_SHORT
9306ca4a
JB		 8869#define T_SHORT 10
8870#define T_OFFSET 11
8871#define T_PTR 12
8872#define T_ID 13
8873#define T_SHL 14
8874#define T_SHR 15
c0f3af97 8875#define T_YMMWORD 16
64a0c779
DN		 8876
8877/* Prototypes for intel parser functions. */
e3bb37b5
L		 8878static int intel_match_token (int);
8879static void intel_putback_token (void);
8880static void intel_get_token (void);
8881static int intel_expr (void);
8882static int intel_e04 (void);
8883static int intel_e05 (void);
8884static int intel_e06 (void);
8885static int intel_e09 (void);
8886static int intel_e10 (void);
8887static int intel_e11 (void);
64a0c779 8888
64a0c779 8889static int
e3bb37b5 8890i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 8891{
8892 int ret;
8893 char *p;
fc0763e6
JB		 8894 const reg_entry *final_base = i.base_reg;
8895 const reg_entry *final_index = i.index_reg;
64a0c779 8896
a724f0f4
JB		 8897 p = intel_parser.op_string = xstrdup (operand_string);
8898 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
8899
8900 for (;;)
64a0c779 8901 {
a724f0f4
JB		 8902 /* Initialize token holders. */
8903 cur_token.code = prev_token.code = T_NIL;
8904 cur_token.reg = prev_token.reg = NULL;
8905 cur_token.str = prev_token.str = NULL;
8906
8907 /* Initialize parser structure. */
8908 intel_parser.got_a_float = got_a_float;
8909 intel_parser.op_modifier = 0;
8910 intel_parser.is_mem = 0;
8911 intel_parser.in_offset = 0;
8912 intel_parser.in_bracket = 0;
8913 intel_parser.reg = NULL;
8914 intel_parser.disp[0] = '\0';
8915 intel_parser.next_operand = NULL;
8916
fc0763e6
JB		 8917 i.base_reg = NULL;
8918 i.index_reg = NULL;
8919
a724f0f4
JB		 8920 /* Read the first token and start the parser. */
8921 intel_get_token ();
8922 ret = intel_expr ();
8923
8924 if (!ret)
8925 break;
8926
9306ca4a
JB		 8927 if (cur_token.code != T_NIL)
8928 {
8929 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8930 current_templates->start->name, cur_token.str);
8931 ret = 0;
8932 }
64a0c779
DN		 8933 /* If we found a memory reference, hand it over to i386_displacement
8934 to fill in the rest of the operand fields. */
9306ca4a 8935 else if (intel_parser.is_mem)
64a0c779
DN		 8936 {
8937 if ((i.mem_operands == 1
40fb9820 8938 && !current_templates->start->opcode_modifier.isstring)
64a0c779
DN		 8939 || i.mem_operands == 2)
8940 {
8941 as_bad (_("too many memory references for '%s'"),
8942 current_templates->start->name);
8943 ret = 0;
8944 }
8945 else
8946 {
8947 char *s = intel_parser.disp;
64a0c779 8948
a724f0f4
JB		 8949 if (!quiet_warnings && intel_parser.is_mem < 0)
8950 /* See the comments in intel_bracket_expr. */
8951 as_warn (_("Treating `%s' as memory reference"), operand_string);
8952
64a0c779
DN		 8953 /* Add the displacement expression. */
8954 if (*s != '\0')
a4622f40
AM		 8955 ret = i386_displacement (s, s + strlen (s));
8956 if (ret)
a724f0f4
JB		 8957 {
8958 /* Swap base and index in 16-bit memory operands like
8959 [si+bx]. Since i386_index_check is also used in AT&T
8960 mode we have to do that here. */
8961 if (i.base_reg
8962 && i.index_reg
40fb9820
L		 8963 && i.base_reg->reg_type.bitfield.reg16
8964 && i.index_reg->reg_type.bitfield.reg16
a724f0f4
JB		 8965 && i.base_reg->reg_num >= 6
8966 && i.index_reg->reg_num < 6)
8967 {
8968 const reg_entry *base = i.index_reg;
8969
8970 i.index_reg = i.base_reg;
8971 i.base_reg = base;
8972 }
8973 ret = i386_index_check (operand_string);
8974 }
fc0763e6
JB		 8975 if (ret)
8976 {
8977 i.types[this_operand].bitfield.mem = 1;
8978 i.mem_operands++;
8979 }
64a0c779
DN		 8980 }
8981 }
8982
8983 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 8984 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779 8985 || intel_parser.reg == NULL)
b7240065
JB		 8986 {
8987 if (i.mem_operands < 2 && i.seg[i.mem_operands])
8988 {
8989 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8990 as_warn (_("Segment override ignored"));
8991 i.seg[i.mem_operands] = NULL;
8992 }
8993 ret = i386_immediate (intel_parser.disp);
8994 }
a724f0f4 8995
fc0763e6
JB		 8996 if (!final_base && !final_index)
8997 {
8998 final_base = i.base_reg;
8999 final_index = i.index_reg;
9000 }
9001
a724f0f4 9002 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 9003 ret = 0;
a724f0f4
JB		 9004 if (!ret || !intel_parser.next_operand)
9005 break;
9006 intel_parser.op_string = intel_parser.next_operand;
9007 this_operand = i.operands++;
7d5e4556 9008 i.types[this_operand].bitfield.unspecified = 1;
64a0c779
DN		 9009 }
9010
9011 free (p);
9012 free (intel_parser.disp);
9013
fc0763e6
JB		 9014 if (final_base || final_index)
9015 {
9016 i.base_reg = final_base;
9017 i.index_reg = final_index;
9018 }
9019
64a0c779
DN		 9020 return ret;
9021}
9022
a724f0f4
JB		 9023#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
9024
9025/* expr e04 expr'
9026
9027 expr' cmpOp e04 expr'
9028 | Empty */
64a0c779 9029static int
e3bb37b5 9030intel_expr (void)
64a0c779 9031{
a724f0f4
JB		 9032 /* XXX Implement the comparison operators. */
9033 return intel_e04 ();
9306ca4a
JB		 9034}
9035
a724f0f4 9036/* e04 e05 e04'
9306ca4a 9037
a724f0f4 9038 e04' addOp e05 e04'
9306ca4a
JB		 9039 | Empty */
9040static int
e3bb37b5 9041intel_e04 (void)
9306ca4a 9042{
a724f0f4 9043 int nregs = -1;
9306ca4a 9044
a724f0f4 9045 for (;;)
9306ca4a 9046 {
a724f0f4
JB		 9047 if (!intel_e05())
9048 return 0;
9306ca4a 9049
a724f0f4
JB		 9050 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9051 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 9052
a724f0f4
JB		 9053 if (cur_token.code == '+')
9054 nregs = -1;
9055 else if (cur_token.code == '-')
9056 nregs = NUM_ADDRESS_REGS;
9057 else
9058 return 1;
64a0c779 9059
a724f0f4
JB		 9060 strcat (intel_parser.disp, cur_token.str);
9061 intel_match_token (cur_token.code);
9062 }
64a0c779
DN		 9063}
9064
64a0c779
DN		 9065/* e05 e06 e05'
9066
9306ca4a 9067 e05' binOp e06 e05'
64a0c779
DN		 9068 | Empty */
9069static int
e3bb37b5 9070intel_e05 (void)
64a0c779 9071{
a724f0f4 9072 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 9073
a724f0f4 9074 for (;;)
64a0c779 9075 {
a724f0f4
JB		 9076 if (!intel_e06())
9077 return 0;
9078
4eed87de
AM		 9079 if (cur_token.code == '&'
9080 || cur_token.code == '|'
9081 || cur_token.code == '^')
a724f0f4
JB		 9082 {
9083 char str[2];
9084
9085 str[0] = cur_token.code;
9086 str[1] = 0;
9087 strcat (intel_parser.disp, str);
9088 }
9089 else
9090 break;
9306ca4a 9091
64a0c779
DN		 9092 intel_match_token (cur_token.code);
9093
a724f0f4
JB		 9094 if (nregs < 0)
9095 nregs = ~nregs;
64a0c779 9096 }
a724f0f4
JB		 9097 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9098 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
9099 return 1;
4a1805b1 9100}
64a0c779
DN		 9101
9102/* e06 e09 e06'
9103
9104 e06' mulOp e09 e06'
b77a7acd 9105 | Empty */
64a0c779 9106static int
e3bb37b5 9107intel_e06 (void)
64a0c779 9108{
a724f0f4 9109 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 9110
a724f0f4 9111 for (;;)
64a0c779 9112 {
a724f0f4
JB		 9113 if (!intel_e09())
9114 return 0;
9306ca4a 9115
4eed87de
AM		 9116 if (cur_token.code == '*'
9117 || cur_token.code == '/'
9118 || cur_token.code == '%')
a724f0f4
JB		 9119 {
9120 char str[2];
9306ca4a 9121
a724f0f4
JB		 9122 str[0] = cur_token.code;
9123 str[1] = 0;
9124 strcat (intel_parser.disp, str);
9125 }
9126 else if (cur_token.code == T_SHL)
9127 strcat (intel_parser.disp, "<<");
9128 else if (cur_token.code == T_SHR)
9129 strcat (intel_parser.disp, ">>");
9130 else
9131 break;
9306ca4a 9132
64e74474 9133 intel_match_token (cur_token.code);
64a0c779 9134
a724f0f4
JB		 9135 if (nregs < 0)
9136 nregs = ~nregs;
64a0c779 9137 }
a724f0f4
JB		 9138 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9139 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
9140 return 1;
64a0c779
DN		 9141}
9142
a724f0f4
JB		 9143/* e09 OFFSET e09
9144 | SHORT e09
9145 | + e09
9146 | - e09
9147 | ~ e09
9148 | NOT e09
9306ca4a
JB		 9149 | e10 e09'
9150
64a0c779 9151 e09' PTR e10 e09'
b77a7acd 9152 | : e10 e09'
64a0c779
DN		 9153 | Empty */
9154static int
e3bb37b5 9155intel_e09 (void)
64a0c779 9156{
a724f0f4
JB		 9157 int nregs = ~NUM_ADDRESS_REGS;
9158 int in_offset = 0;
9159
9160 for (;;)
64a0c779 9161 {
a724f0f4
JB		 9162 /* Don't consume constants here. */
9163 if (cur_token.code == '+' || cur_token.code == '-')
9164 {
9165 /* Need to look one token ahead - if the next token
9166 is a constant, the current token is its sign. */
9167 int next_code;
9168
9169 intel_match_token (cur_token.code);
9170 next_code = cur_token.code;
9171 intel_putback_token ();
9172 if (next_code == T_CONST)
9173 break;
9174 }
9175
9176 /* e09 OFFSET e09 */
9177 if (cur_token.code == T_OFFSET)
9178 {
9179 if (!in_offset++)
9180 ++intel_parser.in_offset;
9181 }
9182
9183 /* e09 SHORT e09 */
9184 else if (cur_token.code == T_SHORT)
9185 intel_parser.op_modifier |= 1 << T_SHORT;
9186
9187 /* e09 + e09 */
9188 else if (cur_token.code == '+')
9189 strcat (intel_parser.disp, "+");
9190
9191 /* e09 - e09
9192 | ~ e09
9193 | NOT e09 */
9194 else if (cur_token.code == '-' || cur_token.code == '~')
9195 {
9196 char str[2];
64a0c779 9197
a724f0f4
JB		 9198 if (nregs < 0)
9199 nregs = ~nregs;
9200 str[0] = cur_token.code;
9201 str[1] = 0;
9202 strcat (intel_parser.disp, str);
9203 }
9204
9205 /* e09 e10 e09' */
9206 else
9207 break;
9208
9209 intel_match_token (cur_token.code);
64a0c779
DN		 9210 }
9211
a724f0f4 9212 for (;;)
9306ca4a 9213 {
a724f0f4
JB		 9214 if (!intel_e10 ())
9215 return 0;
9306ca4a 9216
a724f0f4
JB		 9217 /* e09' PTR e10 e09' */
9218 if (cur_token.code == T_PTR)
9219 {
9220 char suffix;
9306ca4a 9221
a724f0f4 9222 if (prev_token.code == T_BYTE)
7d5e4556
L		 9223 {
9224 suffix = BYTE_MNEM_SUFFIX;
9225 i.types[this_operand].bitfield.byte = 1;
9226 }
9306ca4a 9227
a724f0f4
JB		 9228 else if (prev_token.code == T_WORD)
9229 {
34b772a6
JB		 9230 if ((current_templates->start->name[0] == 'l'
9231 && current_templates->start->name[2] == 's'
9232 && current_templates->start->name[3] == 0)
9233 || current_templates->start->base_opcode == 0x62 /* bound */)
a724f0f4
JB		 9234 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
9235 else if (intel_parser.got_a_float == 2) /* "fi..." */
9236 suffix = SHORT_MNEM_SUFFIX;
9237 else
9238 suffix = WORD_MNEM_SUFFIX;
7d5e4556 9239 i.types[this_operand].bitfield.word = 1;
a724f0f4 9240 }
64a0c779 9241
a724f0f4
JB		 9242 else if (prev_token.code == T_DWORD)
9243 {
34b772a6
JB		 9244 if ((current_templates->start->name[0] == 'l'
9245 && current_templates->start->name[2] == 's'
9246 && current_templates->start->name[3] == 0)
9247 || current_templates->start->base_opcode == 0x62 /* bound */)
a724f0f4
JB		 9248 suffix = WORD_MNEM_SUFFIX;
9249 else if (flag_code == CODE_16BIT
40fb9820
L		 9250 && (current_templates->start->opcode_modifier.jump
9251 || current_templates->start->opcode_modifier.jumpdword))
a724f0f4
JB		 9252 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9253 else if (intel_parser.got_a_float == 1) /* "f..." */
9254 suffix = SHORT_MNEM_SUFFIX;
9255 else
9256 suffix = LONG_MNEM_SUFFIX;
7d5e4556 9257 i.types[this_operand].bitfield.dword = 1;
a724f0f4 9258 }
9306ca4a 9259
a724f0f4
JB		 9260 else if (prev_token.code == T_FWORD)
9261 {
9262 if (current_templates->start->name[0] == 'l'
9263 && current_templates->start->name[2] == 's'
9264 && current_templates->start->name[3] == 0)
9265 suffix = LONG_MNEM_SUFFIX;
9266 else if (!intel_parser.got_a_float)
9267 {
9268 if (flag_code == CODE_16BIT)
9269 add_prefix (DATA_PREFIX_OPCODE);
9270 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9271 }
9272 else
9273 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7d5e4556 9274 i.types[this_operand].bitfield.fword = 1;
a724f0f4 9275 }
64a0c779 9276
a724f0f4
JB		 9277 else if (prev_token.code == T_QWORD)
9278 {
34b772a6
JB		 9279 if (current_templates->start->base_opcode == 0x62 /* bound */
9280 || intel_parser.got_a_float == 1) /* "f..." */
a724f0f4
JB		 9281 suffix = LONG_MNEM_SUFFIX;
9282 else
34b772a6 9283 suffix = QWORD_MNEM_SUFFIX;
7d5e4556 9284 i.types[this_operand].bitfield.qword = 1;
a724f0f4 9285 }
64a0c779 9286
a724f0f4
JB		 9287 else if (prev_token.code == T_TBYTE)
9288 {
9289 if (intel_parser.got_a_float == 1)
9290 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9291 else
9292 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
9293 }
9306ca4a 9294
a724f0f4 9295 else if (prev_token.code == T_XMMWORD)
9306ca4a 9296 {
582d5edd 9297 suffix = XMMWORD_MNEM_SUFFIX;
7d5e4556 9298 i.types[this_operand].bitfield.xmmword = 1;
9306ca4a 9299 }
64a0c779 9300
c0f3af97
L		 9301 else if (prev_token.code == T_YMMWORD)
9302 {
9303 suffix = YMMWORD_MNEM_SUFFIX;
9304 i.types[this_operand].bitfield.ymmword = 1;
9305 }
9306
f16b83df 9307 else
a724f0f4
JB		 9308 {
9309 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
9310 return 0;
9311 }
9312
7d5e4556
L		 9313 i.types[this_operand].bitfield.unspecified = 0;
9314
435acd52
JB		 9315 /* Operands for jump/call using 'ptr' notation denote absolute
9316 addresses. */
40fb9820
L		 9317 if (current_templates->start->opcode_modifier.jump
9318 || current_templates->start->opcode_modifier.jumpdword)
9319 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 9320
a724f0f4
JB		 9321 if (current_templates->start->base_opcode == 0x8d /* lea */)
9322 ;
9323 else if (!i.suffix)
9324 i.suffix = suffix;
9325 else if (i.suffix != suffix)
9326 {
9327 as_bad (_("Conflicting operand modifiers"));
9328 return 0;
9329 }
64a0c779 9330
9306ca4a
JB		 9331 }
9332
a724f0f4
JB		 9333 /* e09' : e10 e09' */
9334 else if (cur_token.code == ':')
9306ca4a 9335 {
a724f0f4
JB		 9336 if (prev_token.code != T_REG)
9337 {
9338 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
9339 segment/group identifier (which we don't have), using comma
9340 as the operand separator there is even less consistent, since
9341 there all branches only have a single operand. */
9342 if (this_operand != 0
9343 || intel_parser.in_offset
9344 || intel_parser.in_bracket
40fb9820
L		 9345 || (!current_templates->start->opcode_modifier.jump
9346 && !current_templates->start->opcode_modifier.jumpdword
9347 && !current_templates->start->opcode_modifier.jumpintersegment
9348 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
a724f0f4
JB		 9349 return intel_match_token (T_NIL);
9350 /* Remember the start of the 2nd operand and terminate 1st
9351 operand here.
9352 XXX This isn't right, yet (when SSSS:OOOO is right operand of
9353 another expression), but it gets at least the simplest case
9354 (a plain number or symbol on the left side) right. */
9355 intel_parser.next_operand = intel_parser.op_string;
9356 *--intel_parser.op_string = '\0';
9357 return intel_match_token (':');
9358 }
9306ca4a 9359 }
64a0c779 9360
a724f0f4 9361 /* e09' Empty */
64a0c779 9362 else
a724f0f4 9363 break;
64a0c779 9364
a724f0f4
JB		 9365 intel_match_token (cur_token.code);
9366
9367 }
9368
9369 if (in_offset)
9370 {
9371 --intel_parser.in_offset;
9372 if (nregs < 0)
9373 nregs = ~nregs;
9374 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 9375 {
a724f0f4 9376 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 9377 return 0;
9378 }
a724f0f4
JB		 9379 intel_parser.op_modifier |= 1 << T_OFFSET;
9380 }
9306ca4a 9381
a724f0f4
JB		 9382 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9383 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
9384 return 1;
9385}
64a0c779 9386
a724f0f4 9387static int
e3bb37b5 9388intel_bracket_expr (void)
a724f0f4
JB		 9389{
9390 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
9391 const char *start = intel_parser.op_string;
9392 int len;
9393
9394 if (i.op[this_operand].regs)
9395 return intel_match_token (T_NIL);
9396
9397 intel_match_token ('[');
9398
9399 /* Mark as a memory operand only if it's not already known to be an
9400 offset expression. If it's an offset expression, we need to keep
9401 the brace in. */
9402 if (!intel_parser.in_offset)
9403 {
9404 ++intel_parser.in_bracket;
435acd52
JB		 9405
9406 /* Operands for jump/call inside brackets denote absolute addresses. */
40fb9820
L		 9407 if (current_templates->start->opcode_modifier.jump
9408 || current_templates->start->opcode_modifier.jumpdword)
9409 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 9410
a724f0f4
JB		 9411 /* Unfortunately gas always diverged from MASM in a respect that can't
9412 be easily fixed without risking to break code sequences likely to be
9413 encountered (the testsuite even check for this): MASM doesn't consider
9414 an expression inside brackets unconditionally as a memory reference.
9415 When that is e.g. a constant, an offset expression, or the sum of the
9416 two, this is still taken as a constant load. gas, however, always
9417 treated these as memory references. As a compromise, we'll try to make
9418 offset expressions inside brackets work the MASM way (since that's
9419 less likely to be found in real world code), but make constants alone
9420 continue to work the traditional gas way. In either case, issue a
9421 warning. */
9422 intel_parser.op_modifier &= ~was_offset;
64a0c779 9423 }
a724f0f4 9424 else
64e74474 9425 strcat (intel_parser.disp, "[");
a724f0f4
JB		 9426
9427 /* Add a '+' to the displacement string if necessary. */
9428 if (*intel_parser.disp != '\0'
9429 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
9430 strcat (intel_parser.disp, "+");
64a0c779 9431
a724f0f4
JB		 9432 if (intel_expr ()
9433 && (len = intel_parser.op_string - start - 1,
9434 intel_match_token (']')))
64a0c779 9435 {
a724f0f4
JB		 9436 /* Preserve brackets when the operand is an offset expression. */
9437 if (intel_parser.in_offset)
9438 strcat (intel_parser.disp, "]");
9439 else
9440 {
9441 --intel_parser.in_bracket;
9442 if (i.base_reg || i.index_reg)
9443 intel_parser.is_mem = 1;
9444 if (!intel_parser.is_mem)
9445 {
9446 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
9447 /* Defer the warning until all of the operand was parsed. */
9448 intel_parser.is_mem = -1;
9449 else if (!quiet_warnings)
4eed87de
AM		 9450 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
9451 len, start, len, start);
a724f0f4
JB		 9452 }
9453 }
9454 intel_parser.op_modifier |= was_offset;
64a0c779 9455
a724f0f4 9456 return 1;
64a0c779 9457 }
a724f0f4 9458 return 0;
64a0c779
DN		 9459}
9460
9461/* e10 e11 e10'
9462
9463 e10' [ expr ] e10'
b77a7acd 9464 | Empty */
64a0c779 9465static int
e3bb37b5 9466intel_e10 (void)
64a0c779 9467{
a724f0f4
JB		 9468 if (!intel_e11 ())
9469 return 0;
64a0c779 9470
a724f0f4 9471 while (cur_token.code == '[')
64a0c779 9472 {
a724f0f4 9473 if (!intel_bracket_expr ())
21d6c4af 9474 return 0;
64a0c779
DN		 9475 }
9476
a724f0f4 9477 return 1;
64a0c779
DN		 9478}
9479
64a0c779 9480/* e11 ( expr )
b77a7acd 9481 | [ expr ]
64a0c779
DN		 9482 | BYTE
9483 | WORD
9484 | DWORD
9306ca4a 9485 | FWORD
64a0c779 9486 | QWORD
9306ca4a
JB		 9487 | TBYTE
9488 | OWORD
9489 | XMMWORD
c0f3af97 9490 | YMMWORD
4a1805b1 9491 | $
64a0c779
DN		 9492 | .
9493 | register
9494 | id
9495 | constant */
9496static int
e3bb37b5 9497intel_e11 (void)
64a0c779 9498{
a724f0f4 9499 switch (cur_token.code)
64a0c779 9500 {
a724f0f4
JB		 9501 /* e11 ( expr ) */
9502 case '(':
64a0c779
DN		 9503 intel_match_token ('(');
9504 strcat (intel_parser.disp, "(");
9505
9506 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 9507 {
9508 strcat (intel_parser.disp, ")");
9509 return 1;
9510 }
a724f0f4 9511 return 0;
4a1805b1 9512
a724f0f4
JB		 9513 /* e11 [ expr ] */
9514 case '[':
a724f0f4 9515 return intel_bracket_expr ();
64a0c779 9516
a724f0f4
JB		 9517 /* e11 $
9518 | . */
9519 case '.':
64a0c779
DN		 9520 strcat (intel_parser.disp, cur_token.str);
9521 intel_match_token (cur_token.code);
21d6c4af
DN		 9522
9523 /* Mark as a memory operand only if it's not already known to be an
9524 offset expression. */
a724f0f4 9525 if (!intel_parser.in_offset)
21d6c4af 9526 intel_parser.is_mem = 1;
64a0c779
DN		 9527
9528 return 1;
64a0c779 9529
a724f0f4
JB		 9530 /* e11 register */
9531 case T_REG:
9532 {
9533 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 9534
a724f0f4 9535 intel_match_token (T_REG);
64a0c779 9536
a724f0f4
JB		 9537 /* Check for segment change. */
9538 if (cur_token.code == ':')
9539 {
40fb9820
L		 9540 if (!reg->reg_type.bitfield.sreg2
9541 && !reg->reg_type.bitfield.sreg3)
a724f0f4 9542 {
4eed87de
AM		 9543 as_bad (_("`%s' is not a valid segment register"),
9544 reg->reg_name);
a724f0f4
JB		 9545 return 0;
9546 }
b7240065
JB		 9547 else if (i.mem_operands >= 2)
9548 as_warn (_("Segment override ignored"));
a724f0f4
JB		 9549 else if (i.seg[i.mem_operands])
9550 as_warn (_("Extra segment override ignored"));
9551 else
9552 {
9553 if (!intel_parser.in_offset)
9554 intel_parser.is_mem = 1;
9555 switch (reg->reg_num)
9556 {
9557 case 0:
9558 i.seg[i.mem_operands] = &es;
9559 break;
9560 case 1:
9561 i.seg[i.mem_operands] = &cs;
9562 break;
9563 case 2:
9564 i.seg[i.mem_operands] = &ss;
9565 break;
9566 case 3:
9567 i.seg[i.mem_operands] = &ds;
9568 break;
9569 case 4:
9570 i.seg[i.mem_operands] = &fs;
9571 break;
9572 case 5:
9573 i.seg[i.mem_operands] = &gs;
9574 break;
9575 }
9576 }
9577 }
64a0c779 9578
b7240065
JB		 9579 else if (reg->reg_type.bitfield.sreg3 && reg->reg_num == RegFlat)
9580 {
9581 as_bad (_("cannot use `FLAT' here"));
9582 return 0;
9583 }
9584
a724f0f4
JB		 9585 /* Not a segment register. Check for register scaling. */
9586 else if (cur_token.code == '*')
9587 {
9588 if (!intel_parser.in_bracket)
9589 {
9590 as_bad (_("Register scaling only allowed in memory operands"));
9591 return 0;
9592 }
64a0c779 9593
40fb9820 9594 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
a724f0f4
JB		 9595 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
9596 else if (i.index_reg)
9597 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 9598
a724f0f4
JB		 9599 /* What follows must be a valid scale. */
9600 intel_match_token ('*');
9601 i.index_reg = reg;
40fb9820 9602 i.types[this_operand].bitfield.baseindex = 1;
64a0c779 9603
a724f0f4
JB		 9604 /* Set the scale after setting the register (otherwise,
9605 i386_scale will complain) */
9606 if (cur_token.code == '+' || cur_token.code == '-')
9607 {
9608 char *str, sign = cur_token.code;
9609 intel_match_token (cur_token.code);
9610 if (cur_token.code != T_CONST)
9611 {
9612 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9613 cur_token.str);
9614 return 0;
9615 }
9616 str = (char *) xmalloc (strlen (cur_token.str) + 2);
9617 strcpy (str + 1, cur_token.str);
9618 *str = sign;
9619 if (!i386_scale (str))
9620 return 0;
9621 free (str);
9622 }
9623 else if (!i386_scale (cur_token.str))
64a0c779 9624 return 0;
a724f0f4
JB		 9625 intel_match_token (cur_token.code);
9626 }
64a0c779 9627
a724f0f4
JB		 9628 /* No scaling. If this is a memory operand, the register is either a
9629 base register (first occurrence) or an index register (second
9630 occurrence). */
7b0441f6 9631 else if (intel_parser.in_bracket)
a724f0f4 9632 {
64a0c779 9633
a724f0f4
JB		 9634 if (!i.base_reg)
9635 i.base_reg = reg;
9636 else if (!i.index_reg)
9637 i.index_reg = reg;
9638 else
9639 {
9640 as_bad (_("Too many register references in memory operand"));
9641 return 0;
9642 }
64a0c779 9643
40fb9820 9644 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4 9645 }
4a1805b1 9646
4d1bb795
JB		 9647 /* It's neither base nor index. */
9648 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4 9649 {
40fb9820
L		 9650 i386_operand_type temp = reg->reg_type;
9651 temp.bitfield.baseindex = 0;
c6fb90c8
L		 9652 i.types[this_operand] = operand_type_or (i.types[this_operand],
9653 temp);
7d5e4556 9654 i.types[this_operand].bitfield.unspecified = 0;
a724f0f4
JB		 9655 i.op[this_operand].regs = reg;
9656 i.reg_operands++;
9657 }
9658 else
9659 {
9660 as_bad (_("Invalid use of register"));
9661 return 0;
9662 }
64a0c779 9663
a724f0f4
JB		 9664 /* Since registers are not part of the displacement string (except
9665 when we're parsing offset operands), we may need to remove any
9666 preceding '+' from the displacement string. */
9667 if (*intel_parser.disp != '\0'
9668 && !intel_parser.in_offset)
9669 {
9670 char *s = intel_parser.disp;
9671 s += strlen (s) - 1;
9672 if (*s == '+')
9673 *s = '\0';
9674 }
4a1805b1 9675
a724f0f4
JB		 9676 return 1;
9677 }
9678
9679 /* e11 BYTE
9680 | WORD
9681 | DWORD
9682 | FWORD
9683 | QWORD
9684 | TBYTE
9685 | OWORD
c0f3af97
L		 9686 | XMMWORD
9687 | YMMWORD */
a724f0f4
JB		 9688 case T_BYTE:
9689 case T_WORD:
9690 case T_DWORD:
9691 case T_FWORD:
9692 case T_QWORD:
9693 case T_TBYTE:
9694 case T_XMMWORD:
c0f3af97 9695 case T_YMMWORD:
a724f0f4 9696 intel_match_token (cur_token.code);
64a0c779 9697
a724f0f4
JB		 9698 if (cur_token.code == T_PTR)
9699 return 1;
9700
9701 /* It must have been an identifier. */
9702 intel_putback_token ();
9703 cur_token.code = T_ID;
9704 /* FALLTHRU */
9705
9706 /* e11 id
9707 | constant */
9708 case T_ID:
9709 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 9710 {
9711 symbolS *symbolP;
9712
a724f0f4
JB		 9713 /* The identifier represents a memory reference only if it's not
9714 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 9715 symbolP = symbol_find(cur_token.str);
9716 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
9717 intel_parser.is_mem = 1;
9718 }
a724f0f4 9719 /* FALLTHRU */
64a0c779 9720
a724f0f4
JB		 9721 case T_CONST:
9722 case '-':
9723 case '+':
9724 {
9725 char *save_str, sign = 0;
64a0c779 9726
a724f0f4
JB		 9727 /* Allow constants that start with `+' or `-'. */
9728 if (cur_token.code == '-' || cur_token.code == '+')
9729 {
9730 sign = cur_token.code;
9731 intel_match_token (cur_token.code);
9732 if (cur_token.code != T_CONST)
9733 {
9734 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9735 cur_token.str);
9736 return 0;
9737 }
9738 }
64a0c779 9739
a724f0f4
JB		 9740 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
9741 strcpy (save_str + !!sign, cur_token.str);
9742 if (sign)
9743 *save_str = sign;
64a0c779 9744
a724f0f4
JB		 9745 /* Get the next token to check for register scaling. */
9746 intel_match_token (cur_token.code);
64a0c779 9747
4eed87de
AM		 9748 /* Check if this constant is a scaling factor for an
9749 index register. */
a724f0f4
JB		 9750 if (cur_token.code == '*')
9751 {
9752 if (intel_match_token ('*') && cur_token.code == T_REG)
9753 {
9754 const reg_entry *reg = cur_token.reg;
9755
9756 if (!intel_parser.in_bracket)
9757 {
4eed87de
AM		 9758 as_bad (_("Register scaling only allowed "
9759 "in memory operands"));
a724f0f4
JB		 9760 return 0;
9761 }
9762
4eed87de
AM		 9763 /* Disallow things like [1*si].
9764 sp and esp are invalid as index. */
40fb9820 9765 if (reg->reg_type.bitfield.reg16)
4eed87de 9766 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 9767 else if (i.index_reg)
4eed87de 9768 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 9769
9770 /* The constant is followed by `* reg', so it must be
9771 a valid scale. */
9772 i.index_reg = reg;
40fb9820 9773 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4
JB		 9774
9775 /* Set the scale after setting the register (otherwise,
9776 i386_scale will complain) */
9777 if (!i386_scale (save_str))
64a0c779 9778 return 0;
a724f0f4
JB		 9779 intel_match_token (T_REG);
9780
9781 /* Since registers are not part of the displacement
9782 string, we may need to remove any preceding '+' from
9783 the displacement string. */
9784 if (*intel_parser.disp != '\0')
9785 {
9786 char *s = intel_parser.disp;
9787 s += strlen (s) - 1;
9788 if (*s == '+')
9789 *s = '\0';
9790 }
9791
9792 free (save_str);
9793
9794 return 1;
9795 }
64a0c779 9796
a724f0f4
JB		 9797 /* The constant was not used for register scaling. Since we have
9798 already consumed the token following `*' we now need to put it
9799 back in the stream. */
64a0c779 9800 intel_putback_token ();
a724f0f4 9801 }
64a0c779 9802
a724f0f4
JB		 9803 /* Add the constant to the displacement string. */
9804 strcat (intel_parser.disp, save_str);
9805 free (save_str);
64a0c779 9806
a724f0f4
JB		 9807 return 1;
9808 }
64a0c779
DN		 9809 }
9810
64a0c779
DN		 9811 as_bad (_("Unrecognized token '%s'"), cur_token.str);
9812 return 0;
9813}
9814
64a0c779
DN		 9815/* Match the given token against cur_token. If they match, read the next
9816 token from the operand string. */
9817static int
e3bb37b5 9818intel_match_token (int code)
64a0c779
DN		 9819{
9820 if (cur_token.code == code)
9821 {
9822 intel_get_token ();
9823 return 1;
9824 }
9825 else
9826 {
0477af35 9827 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 9828 return 0;
9829 }
9830}
9831
64a0c779
DN		 9832/* Read a new token from intel_parser.op_string and store it in cur_token. */
9833static void
e3bb37b5 9834intel_get_token (void)
64a0c779
DN		 9835{
9836 char *end_op;
9837 const reg_entry *reg;
9838 struct intel_token new_token;
9839
9840 new_token.code = T_NIL;
9841 new_token.reg = NULL;
9842 new_token.str = NULL;
9843
4a1805b1 9844 /* Free the memory allocated to the previous token and move
64a0c779
DN		 9845 cur_token to prev_token. */
9846 if (prev_token.str)
9847 free (prev_token.str);
9848
9849 prev_token = cur_token;
9850
9851 /* Skip whitespace. */
9852 while (is_space_char (*intel_parser.op_string))
9853 intel_parser.op_string++;
9854
9855 /* Return an empty token if we find nothing else on the line. */
9856 if (*intel_parser.op_string == '\0')
9857 {
9858 cur_token = new_token;
9859 return;
9860 }
9861
9862 /* The new token cannot be larger than the remainder of the operand
9863 string. */
a724f0f4 9864 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 9865 new_token.str[0] = '\0';
9866
9867 if (strchr ("0123456789", *intel_parser.op_string))
9868 {
9869 char *p = new_token.str;
9870 char *q = intel_parser.op_string;
9871 new_token.code = T_CONST;
9872
9873 /* Allow any kind of identifier char to encompass floating point and
9874 hexadecimal numbers. */
9875 while (is_identifier_char (*q))
9876 *p++ = *q++;
9877 *p = '\0';
9878
9879 /* Recognize special symbol names [0-9][bf]. */
9880 if (strlen (intel_parser.op_string) == 2
4a1805b1 9881 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 9882 || intel_parser.op_string[1] == 'f'))
9883 new_token.code = T_ID;
9884 }
9885
4d1bb795 9886 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 9887 {
4d1bb795
JB		 9888 size_t len = end_op - intel_parser.op_string;
9889
64a0c779
DN		 9890 new_token.code = T_REG;
9891 new_token.reg = reg;
9892
4d1bb795
JB		 9893 memcpy (new_token.str, intel_parser.op_string, len);
9894 new_token.str[len] = '\0';
64a0c779
DN		 9895 }
9896
9897 else if (is_identifier_char (*intel_parser.op_string))
9898 {
9899 char *p = new_token.str;
9900 char *q = intel_parser.op_string;
9901
9902 /* A '.' or '$' followed by an identifier char is an identifier.
9903 Otherwise, it's operator '.' followed by an expression. */
9904 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
9905 {
9306ca4a
JB		 9906 new_token.code = '.';
9907 new_token.str[0] = '.';
64a0c779
DN		 9908 new_token.str[1] = '\0';
9909 }
9910 else
9911 {
9912 while (is_identifier_char (*q) || *q == '@')
9913 *p++ = *q++;
9914 *p = '\0';
9915
9306ca4a
JB		 9916 if (strcasecmp (new_token.str, "NOT") == 0)
9917 new_token.code = '~';
9918
9919 else if (strcasecmp (new_token.str, "MOD") == 0)
9920 new_token.code = '%';
9921
9922 else if (strcasecmp (new_token.str, "AND") == 0)
9923 new_token.code = '&';
9924
9925 else if (strcasecmp (new_token.str, "OR") == 0)
9926 new_token.code = '|';
9927
9928 else if (strcasecmp (new_token.str, "XOR") == 0)
9929 new_token.code = '^';
9930
9931 else if (strcasecmp (new_token.str, "SHL") == 0)
9932 new_token.code = T_SHL;
9933
9934 else if (strcasecmp (new_token.str, "SHR") == 0)
9935 new_token.code = T_SHR;
9936
9937 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 9938 new_token.code = T_BYTE;
9939
9940 else if (strcasecmp (new_token.str, "WORD") == 0)
9941 new_token.code = T_WORD;
9942
9943 else if (strcasecmp (new_token.str, "DWORD") == 0)
9944 new_token.code = T_DWORD;
9945
9306ca4a
JB		 9946 else if (strcasecmp (new_token.str, "FWORD") == 0)
9947 new_token.code = T_FWORD;
9948
64a0c779
DN		 9949 else if (strcasecmp (new_token.str, "QWORD") == 0)
9950 new_token.code = T_QWORD;
9951
9306ca4a
JB		 9952 else if (strcasecmp (new_token.str, "TBYTE") == 0
9953 /* XXX remove (gcc still uses it) */
9954 || strcasecmp (new_token.str, "XWORD") == 0)
9955 new_token.code = T_TBYTE;
9956
9957 else if (strcasecmp (new_token.str, "XMMWORD") == 0
9958 || strcasecmp (new_token.str, "OWORD") == 0)
9959 new_token.code = T_XMMWORD;
64a0c779 9960
c0f3af97
L		 9961 else if (strcasecmp (new_token.str, "YMMWORD") == 0)
9962 new_token.code = T_YMMWORD;
9963
64a0c779
DN		 9964 else if (strcasecmp (new_token.str, "PTR") == 0)
9965 new_token.code = T_PTR;
9966
9967 else if (strcasecmp (new_token.str, "SHORT") == 0)
9968 new_token.code = T_SHORT;
9969
9970 else if (strcasecmp (new_token.str, "OFFSET") == 0)
9971 {
9972 new_token.code = T_OFFSET;
9973
9974 /* ??? This is not mentioned in the MASM grammar but gcc
9975 makes use of it with -mintel-syntax. OFFSET may be
9976 followed by FLAT: */
9977 if (strncasecmp (q, " FLAT:", 6) == 0)
9978 strcat (new_token.str, " FLAT:");
9979 }
9980
64a0c779
DN		 9981 else
9982 new_token.code = T_ID;
9983 }
9984 }
9985
9306ca4a
JB		 9986 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
9987 {
9988 new_token.code = *intel_parser.op_string;
9989 new_token.str[0] = *intel_parser.op_string;
9990 new_token.str[1] = '\0';
9991 }
9992
9993 else if (strchr ("<>", *intel_parser.op_string)
9994 && *intel_parser.op_string == *(intel_parser.op_string + 1))
9995 {
9996 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
9997 new_token.str[0] = *intel_parser.op_string;
9998 new_token.str[1] = *intel_parser.op_string;
9999 new_token.str[2] = '\0';
10000 }
10001
64a0c779 10002 else
0477af35 10003 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 10004
10005 intel_parser.op_string += strlen (new_token.str);
10006 cur_token = new_token;
10007}
10008
64a0c779
DN		 10009/* Put cur_token back into the token stream and make cur_token point to
10010 prev_token. */
10011static void
e3bb37b5 10012intel_putback_token (void)
64a0c779 10013{
a724f0f4
JB		 10014 if (cur_token.code != T_NIL)
10015 {
10016 intel_parser.op_string -= strlen (cur_token.str);
10017 free (cur_token.str);
10018 }
64a0c779 10019 cur_token = prev_token;
4a1805b1 10020
64a0c779
DN		 10021 /* Forget prev_token. */
10022 prev_token.code = T_NIL;
10023 prev_token.reg = NULL;
10024 prev_token.str = NULL;
10025}
54cfded0 10026
a60de03c
JB		 10027void
10028tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10029{
a60de03c
JB		 10030 int saved_naked_reg;
10031 char saved_register_dot;
54cfded0 10032
a60de03c
JB		 10033 saved_naked_reg = allow_naked_reg;
10034 allow_naked_reg = 1;
10035 saved_register_dot = register_chars['.'];
10036 register_chars['.'] = '.';
10037 allow_pseudo_reg = 1;
10038 expression_and_evaluate (exp);
10039 allow_pseudo_reg = 0;
10040 register_chars['.'] = saved_register_dot;
10041 allow_naked_reg = saved_naked_reg;
10042
10043 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10044 {
a60de03c
JB		 10045 if ((addressT) exp->X_add_number < i386_regtab_size)
10046 {
10047 exp->X_op = O_constant;
10048 exp->X_add_number = i386_regtab[exp->X_add_number]
10049 .dw2_regnum[flag_code >> 1];
10050 }
10051 else
10052 exp->X_op = O_illegal;
54cfded0 10053 }
54cfded0
AM		 10054}
10055
10056void
10057tc_x86_frame_initial_instructions (void)
10058{
a60de03c
JB		 10059 static unsigned int sp_regno[2];
10060
10061 if (!sp_regno[flag_code >> 1])
10062 {
10063 char *saved_input = input_line_pointer;
10064 char sp[][4] = {"esp", "rsp"};
10065 expressionS exp;
a4447b93 10066
a60de03c
JB		 10067 input_line_pointer = sp[flag_code >> 1];
10068 tc_x86_parse_to_dw2regnum (&exp);
10069 assert (exp.X_op == O_constant);
10070 sp_regno[flag_code >> 1] = exp.X_add_number;
10071 input_line_pointer = saved_input;
10072 }
a4447b93 10073
a60de03c 10074 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 10075 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10076}
d2b2c203
DJ		 10077
10078int
10079i386_elf_section_type (const char *str, size_t len)
10080{
10081 if (flag_code == CODE_64BIT
10082 && len == sizeof ("unwind") - 1
10083 && strncmp (str, "unwind", 6) == 0)
10084 return SHT_X86_64_UNWIND;
10085
10086 return -1;
10087}
bb41ade5 10088
ad5fec3b
EB		 10089#ifdef TE_SOLARIS
10090void
10091i386_solaris_fix_up_eh_frame (segT sec)
10092{
10093 if (flag_code == CODE_64BIT)
10094 elf_section_type (sec) = SHT_X86_64_UNWIND;
10095}
10096#endif
10097
bb41ade5
AM		 10098#ifdef TE_PE
10099void
10100tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10101{
10102 expressionS expr;
10103
10104 expr.X_op = O_secrel;
10105 expr.X_add_symbol = symbol;
10106 expr.X_add_number = 0;
10107 emit_expr (&expr, size);
10108}
10109#endif
3b22753a
L		 10110
10111#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10112/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10113
10114int
10115x86_64_section_letter (int letter, char **ptr_msg)
10116{
10117 if (flag_code == CODE_64BIT)
10118 {
10119 if (letter == 'l')
10120 return SHF_X86_64_LARGE;
10121
10122 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10123 }
3b22753a 10124 else
64e74474 10125 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10126 return -1;
10127}
10128
10129int
10130x86_64_section_word (char *str, size_t len)
10131{
8620418b 10132 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10133 return SHF_X86_64_LARGE;
10134
10135 return -1;
10136}
10137
10138static void
10139handle_large_common (int small ATTRIBUTE_UNUSED)
10140{
10141 if (flag_code != CODE_64BIT)
10142 {
10143 s_comm_internal (0, elf_common_parse);
10144 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10145 }
10146 else
10147 {
10148 static segT lbss_section;
10149 asection *saved_com_section_ptr = elf_com_section_ptr;
10150 asection *saved_bss_section = bss_section;
10151
10152 if (lbss_section == NULL)
10153 {
10154 flagword applicable;
10155 segT seg = now_seg;
10156 subsegT subseg = now_subseg;
10157
10158 /* The .lbss section is for local .largecomm symbols. */
10159 lbss_section = subseg_new (".lbss", 0);
10160 applicable = bfd_applicable_section_flags (stdoutput);
10161 bfd_set_section_flags (stdoutput, lbss_section,
10162 applicable & SEC_ALLOC);
10163 seg_info (lbss_section)->bss = 1;
10164
10165 subseg_set (seg, subseg);
10166 }
10167
10168 elf_com_section_ptr = &_bfd_elf_large_com_section;
10169 bss_section = lbss_section;
10170
10171 s_comm_internal (0, elf_common_parse);
10172
10173 elf_com_section_ptr = saved_com_section_ptr;
10174 bss_section = saved_bss_section;
10175 }
10176}
10177#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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