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* config/tc-avr.c: Add specified_mcu variable for selected mcu.
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
4b95cf5c 2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d
L		 68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
22109423 136 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 137}
138arch_entry;
139
78f12dd3 140static void update_code_flag (int, int);
e3bb37b5
L		 141static void set_code_flag (int);
142static void set_16bit_gcc_code_flag (int);
143static void set_intel_syntax (int);
1efbbeb4 144static void set_intel_mnemonic (int);
db51cc60 145static void set_allow_index_reg (int);
7bab8ab5 146static void set_check (int);
e3bb37b5 147static void set_cpu_arch (int);
6482c264 148#ifdef TE_PE
e3bb37b5 149static void pe_directive_secrel (int);
6482c264 150#endif
e3bb37b5
L		 151static void signed_cons (int);
152static char *output_invalid (int c);
ee86248c
JB		 153static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
154 const char *);
155static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
156 const char *);
a7619375 157static int i386_att_operand (char *);
e3bb37b5 158static int i386_intel_operand (char *, int);
ee86248c
JB		 159static int i386_intel_simplify (expressionS *);
160static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 161static const reg_entry *parse_register (char *, char **);
162static char *parse_insn (char *, char *);
163static char *parse_operands (char *, const char *);
164static void swap_operands (void);
4d456e3d 165static void swap_2_operands (int, int);
e3bb37b5
L		 166static void optimize_imm (void);
167static void optimize_disp (void);
d3ce72d0 168static const insn_template *match_template (void);
e3bb37b5
L		 169static int check_string (void);
170static int process_suffix (void);
171static int check_byte_reg (void);
172static int check_long_reg (void);
173static int check_qword_reg (void);
174static int check_word_reg (void);
175static int finalize_imm (void);
176static int process_operands (void);
177static const seg_entry *build_modrm_byte (void);
178static void output_insn (void);
179static void output_imm (fragS *, offsetT);
180static void output_disp (fragS *, offsetT);
29b0f896 181#ifndef I386COFF
e3bb37b5 182static void s_bss (int);
252b5132 183#endif
17d4e2a2
L		 184#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185static void handle_large_common (int small ATTRIBUTE_UNUSED);
186#endif
252b5132 187
a847613f 188static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 189
43234a1e
L		 190/* This struct describes rounding control and SAE in the instruction. */
191struct RC_Operation
192{
193 enum rc_type
194 {
195 rne = 0,
196 rd,
197 ru,
198 rz,
199 saeonly
200 } type;
201 int operand;
202};
203
204static struct RC_Operation rc_op;
205
206/* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209struct Mask_Operation
210{
211 const reg_entry *mask;
212 unsigned int zeroing;
213 /* The operand where this operation is associated. */
214 int operand;
215};
216
217static struct Mask_Operation mask_op;
218
219/* The struct describes broadcasting, applied to OPERAND. FACTOR is
220 broadcast factor. */
221struct Broadcast_Operation
222{
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
224 int type;
225
226 /* Index of broadcasted operand. */
227 int operand;
228};
229
230static struct Broadcast_Operation broadcast_op;
231
c0f3af97
L		 232/* VEX prefix. */
233typedef struct
234{
43234a1e
L		 235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes[4];
c0f3af97
L		 237 unsigned int length;
238 /* Destination or source register specifier. */
239 const reg_entry *register_specifier;
240} vex_prefix;
241
252b5132 242/* 'md_assemble ()' gathers together information and puts it into a
47926f60 243 i386_insn. */
252b5132 244
520dc8e8
AM		 245union i386_op
246 {
247 expressionS *disps;
248 expressionS *imms;
249 const reg_entry *regs;
250 };
251
a65babc9
L		 252enum i386_error
253 {
86e026a4 254 operand_size_mismatch,
a65babc9
L		 255 operand_type_mismatch,
256 register_type_mismatch,
257 number_of_operands_mismatch,
258 invalid_instruction_suffix,
259 bad_imm4,
260 old_gcc_only,
261 unsupported_with_intel_mnemonic,
262 unsupported_syntax,
6c30d220
L		 263 unsupported,
264 invalid_vsib_address,
7bab8ab5 265 invalid_vector_register_set,
43234a1e
L		 266 unsupported_vector_index_register,
267 unsupported_broadcast,
268 broadcast_not_on_src_operand,
269 broadcast_needed,
270 unsupported_masking,
271 mask_not_on_destination,
272 no_default_mask,
273 unsupported_rc_sae,
274 rc_sae_operand_not_last_imm,
275 invalid_register_operand,
276 try_vector_disp8
a65babc9
L		 277 };
278
252b5132
RH		 279struct _i386_insn
280 {
47926f60 281 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 282 insn_template tm;
252b5132 283
7d5e4556
L		 284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
252b5132
RH		 286 char suffix;
287
47926f60 288 /* OPERANDS gives the number of given operands. */
252b5132
RH		 289 unsigned int operands;
290
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
47926f60 293 operands. */
252b5132
RH		 294 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
295
296 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 297 use OP[i] for the corresponding operand. */
40fb9820 298 i386_operand_type types[MAX_OPERANDS];
252b5132 299
520dc8e8
AM		 300 /* Displacement expression, immediate expression, or register for each
301 operand. */
302 union i386_op op[MAX_OPERANDS];
252b5132 303
3e73aa7c
JH		 304 /* Flags for operands. */
305 unsigned int flags[MAX_OPERANDS];
306#define Operand_PCrel 1
307
252b5132 308 /* Relocation type for operand */
f86103b7 309 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 310
252b5132
RH		 311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry *base_reg;
314 const reg_entry *index_reg;
315 unsigned int log2_scale_factor;
316
317 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 318 explicit segment overrides are given. */
ce8a8b2f 319 const seg_entry *seg[2];
252b5132
RH		 320
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes;
324 unsigned char prefix[MAX_PREFIXES];
325
326 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 327 addressing modes of this insn are encoded. */
252b5132 328 modrm_byte rm;
3e73aa7c 329 rex_byte rex;
43234a1e 330 rex_byte vrex;
252b5132 331 sib_byte sib;
c0f3af97 332 vex_prefix vex;
b6169b20 333
43234a1e
L		 334 /* Masking attributes. */
335 struct Mask_Operation *mask;
336
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation *rounding;
339
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation *broadcast;
342
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift;
345
b6169b20 346 /* Swap operand in encoding. */
4473e004 347 unsigned int swap_operand;
891edac4 348
a501d77e
L		 349 /* Prefer 8bit or 32bit displacement in encoding. */
350 enum
351 {
352 disp_encoding_default = 0,
353 disp_encoding_8bit,
354 disp_encoding_32bit
355 } disp_encoding;
f8a5c266 356
d5de92cf
L		 357 /* REP prefix. */
358 const char *rep_prefix;
359
165de32a
L		 360 /* HLE prefix. */
361 const char *hle_prefix;
42164a71 362
7e8b059b
L		 363 /* Have BND prefix. */
364 const char *bnd_prefix;
365
43234a1e
L		 366 /* Need VREX to support upper 16 registers. */
367 int need_vrex;
368
891edac4 369 /* Error message. */
a65babc9 370 enum i386_error error;
252b5132
RH		 371 };
372
373typedef struct _i386_insn i386_insn;
374
43234a1e
L		 375/* Link RC type with corresponding string, that'll be looked for in
376 asm. */
377struct RC_name
378{
379 enum rc_type type;
380 const char *name;
381 unsigned int len;
382};
383
384static const struct RC_name RC_NamesTable[] =
385{
386 { rne, STRING_COMMA_LEN ("rn-sae") },
387 { rd, STRING_COMMA_LEN ("rd-sae") },
388 { ru, STRING_COMMA_LEN ("ru-sae") },
389 { rz, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly, STRING_COMMA_LEN ("sae") },
391};
392
252b5132
RH		 393/* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 395const char extra_symbol_chars[] = "*%-([{"
252b5132 396#ifdef LEX_AT
32137342
NC		 397 "@"
398#endif
399#ifdef LEX_QM
400 "?"
252b5132 401#endif
32137342 402 ;
252b5132 403
29b0f896
AM		 404#if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 406 && !defined (TE_GNU) \
29b0f896 407 && !defined (TE_LINUX) \
8d63c93e
RM		 408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
29b0f896 410 && !defined (TE_FreeBSD) \
5b806d27 411 && !defined (TE_DragonFly) \
29b0f896 412 && !defined (TE_NetBSD)))
252b5132 413/* This array holds the chars that always start a comment. If the
b3b91714
AM		 414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416const char *i386_comment_chars = "#/";
417#define SVR4_COMMENT_CHARS 1
252b5132 418#define PREFIX_SEPARATOR '\\'
252b5132 419
b3b91714
AM		 420#else
421const char *i386_comment_chars = "#";
422#define PREFIX_SEPARATOR '/'
423#endif
424
252b5132
RH		 425/* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 429 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
252b5132 432 '/' isn't otherwise defined. */
b3b91714 433const char line_comment_chars[] = "#/";
252b5132 434
63a0b638 435const char line_separator_chars[] = ";";
252b5132 436
ce8a8b2f
AM		 437/* Chars that can be used to separate mant from exp in floating point
438 nums. */
252b5132
RH		 439const char EXP_CHARS[] = "eE";
440
ce8a8b2f
AM		 441/* Chars that mean this number is a floating point constant
442 As in 0f12.456
443 or 0d1.2345e12. */
252b5132
RH		 444const char FLT_CHARS[] = "fFdDxX";
445
ce8a8b2f 446/* Tables for lexical analysis. */
252b5132
RH		 447static char mnemonic_chars[256];
448static char register_chars[256];
449static char operand_chars[256];
450static char identifier_chars[256];
451static char digit_chars[256];
452
ce8a8b2f 453/* Lexical macros. */
252b5132
RH		 454#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455#define is_operand_char(x) (operand_chars[(unsigned char) x])
456#define is_register_char(x) (register_chars[(unsigned char) x])
457#define is_space_char(x) ((x) == ' ')
458#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459#define is_digit_char(x) (digit_chars[(unsigned char) x])
460
0234cb7c 461/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 462static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
463
464/* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
47926f60 467 assembler instruction). */
252b5132 468static char save_stack[32];
ce8a8b2f 469static char *save_stack_p;
252b5132
RH		 470#define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472#define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
474
47926f60 475/* The instruction we're assembling. */
252b5132
RH		 476static i386_insn i;
477
478/* Possible templates for current insn. */
479static const templates *current_templates;
480
31b2323c
L		 481/* Per instruction expressionS buffers: max displacements & immediates. */
482static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
483static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 484
47926f60 485/* Current operand we are working on. */
ee86248c 486static int this_operand = -1;
252b5132 487
3e73aa7c
JH		 488/* We support four different modes. FLAG_CODE variable is used to distinguish
489 these. */
490
491enum flag_code {
492 CODE_32BIT,
493 CODE_16BIT,
494 CODE_64BIT };
495
496static enum flag_code flag_code;
4fa24527 497static unsigned int object_64bit;
862be3fb 498static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 499static int use_rela_relocations = 0;
500
7af8ed2d
NC		 501#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
504
351f65ca
L		 505/* The ELF ABI to use. */
506enum x86_elf_abi
507{
508 I386_ABI,
7f56bc95
L		 509 X86_64_ABI,
510 X86_64_X32_ABI
351f65ca
L		 511};
512
513static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 514#endif
351f65ca 515
167ad85b
TG		 516#if defined (TE_PE) || defined (TE_PEP)
517/* Use big object file format. */
518static int use_big_obj = 0;
519#endif
520
47926f60
KH		 521/* 1 for intel syntax,
522 0 if att syntax. */
523static int intel_syntax = 0;
252b5132 524
1efbbeb4
L		 525/* 1 for intel mnemonic,
526 0 if att mnemonic. */
527static int intel_mnemonic = !SYSV386_COMPAT;
528
5209009a 529/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 530static int old_gcc = OLDGCC_COMPAT;
531
a60de03c
JB		 532/* 1 if pseudo registers are permitted. */
533static int allow_pseudo_reg = 0;
534
47926f60
KH		 535/* 1 if register prefix % not required. */
536static int allow_naked_reg = 0;
252b5132 537
7e8b059b
L		 538/* 1 if the assembler should add BND prefix for all control-tranferring
539 instructions supporting it, even if this prefix wasn't specified
540 explicitly. */
541static int add_bnd_prefix = 0;
542
ba104c83 543/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 544static int allow_index_reg = 0;
545
7bab8ab5 546static enum check_kind
daf50ae7 547 {
7bab8ab5
JB		 548 check_none = 0,
549 check_warning,
550 check_error
daf50ae7 551 }
7bab8ab5 552sse_check, operand_check = check_warning;
daf50ae7 553
2ca3ace5
L		 554/* Register prefix used for error message. */
555static const char *register_prefix = "%";
556
47926f60
KH		 557/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
558 leave, push, and pop instructions so that gcc has the same stack
559 frame as in 32 bit mode. */
560static char stackop_size = '\0';
eecb386c 561
12b55ccc
L		 562/* Non-zero to optimize code alignment. */
563int optimize_align_code = 1;
564
47926f60
KH		 565/* Non-zero to quieten some warnings. */
566static int quiet_warnings = 0;
a38cf1db 567
47926f60
KH		 568/* CPU name. */
569static const char *cpu_arch_name = NULL;
6305a203 570static char *cpu_sub_arch_name = NULL;
a38cf1db 571
47926f60 572/* CPU feature flags. */
40fb9820
L		 573static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
574
ccc9c027
L		 575/* If we have selected a cpu we are generating instructions for. */
576static int cpu_arch_tune_set = 0;
577
9103f4f4 578/* Cpu we are generating instructions for. */
fbf3f584 579enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 580
581/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 582static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 583
ccc9c027 584/* CPU instruction set architecture used. */
fbf3f584 585enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 586
9103f4f4 587/* CPU feature flags of instruction set architecture used. */
fbf3f584 588i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 589
fddf5b5b
AM		 590/* If set, conditional jumps are not automatically promoted to handle
591 larger than a byte offset. */
592static unsigned int no_cond_jump_promotion = 0;
593
c0f3af97
L		 594/* Encode SSE instructions with VEX prefix. */
595static unsigned int sse2avx;
596
539f890d
L		 597/* Encode scalar AVX instructions with specific vector length. */
598static enum
599 {
600 vex128 = 0,
601 vex256
602 } avxscalar;
603
43234a1e
L		 604/* Encode scalar EVEX LIG instructions with specific vector length. */
605static enum
606 {
607 evexl128 = 0,
608 evexl256,
609 evexl512
610 } evexlig;
611
612/* Encode EVEX WIG instructions with specific evex.w. */
613static enum
614 {
615 evexw0 = 0,
616 evexw1
617 } evexwig;
618
29b0f896 619/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 620static symbolS *GOT_symbol;
29b0f896 621
a4447b93
RH		 622/* The dwarf2 return column, adjusted for 32 or 64 bit. */
623unsigned int x86_dwarf2_return_column;
624
625/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
626int x86_cie_data_alignment;
627
252b5132 628/* Interface to relax_segment.
fddf5b5b
AM		 629 There are 3 major relax states for 386 jump insns because the
630 different types of jumps add different sizes to frags when we're
631 figuring out what sort of jump to choose to reach a given label. */
252b5132 632
47926f60 633/* Types. */
93c2a809
AM		 634#define UNCOND_JUMP 0
635#define COND_JUMP 1
636#define COND_JUMP86 2
fddf5b5b 637
47926f60 638/* Sizes. */
252b5132
RH		 639#define CODE16 1
640#define SMALL 0
29b0f896 641#define SMALL16 (SMALL | CODE16)
252b5132 642#define BIG 2
29b0f896 643#define BIG16 (BIG | CODE16)
252b5132
RH		 644
645#ifndef INLINE
646#ifdef __GNUC__
647#define INLINE __inline__
648#else
649#define INLINE
650#endif
651#endif
652
fddf5b5b
AM		 653#define ENCODE_RELAX_STATE(type, size) \
654 ((relax_substateT) (((type) << 2) | (size)))
655#define TYPE_FROM_RELAX_STATE(s) \
656 ((s) >> 2)
657#define DISP_SIZE_FROM_RELAX_STATE(s) \
658 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 659
660/* This table is used by relax_frag to promote short jumps to long
661 ones where necessary. SMALL (short) jumps may be promoted to BIG
662 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
663 don't allow a short jump in a 32 bit code segment to be promoted to
664 a 16 bit offset jump because it's slower (requires data size
665 prefix), and doesn't work, unless the destination is in the bottom
666 64k of the code segment (The top 16 bits of eip are zeroed). */
667
668const relax_typeS md_relax_table[] =
669{
24eab124
AM		 670 /* The fields are:
671 1) most positive reach of this state,
672 2) most negative reach of this state,
93c2a809 673 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 674 4) which index into the table to try if we can't fit into this one. */
252b5132 675
fddf5b5b 676 /* UNCOND_JUMP states. */
93c2a809
AM		 677 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
678 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
679 /* dword jmp adds 4 bytes to frag:
680 0 extra opcode bytes, 4 displacement bytes. */
252b5132 681 {0, 0, 4, 0},
93c2a809
AM		 682 /* word jmp adds 2 byte2 to frag:
683 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 684 {0, 0, 2, 0},
685
93c2a809
AM		 686 /* COND_JUMP states. */
687 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
688 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
689 /* dword conditionals adds 5 bytes to frag:
690 1 extra opcode byte, 4 displacement bytes. */
691 {0, 0, 5, 0},
fddf5b5b 692 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 693 1 extra opcode byte, 2 displacement bytes. */
694 {0, 0, 3, 0},
695
696 /* COND_JUMP86 states. */
697 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
698 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
699 /* dword conditionals adds 5 bytes to frag:
700 1 extra opcode byte, 4 displacement bytes. */
701 {0, 0, 5, 0},
702 /* word conditionals add 4 bytes to frag:
703 1 displacement byte and a 3 byte long branch insn. */
704 {0, 0, 4, 0}
252b5132
RH		 705};
706
9103f4f4
L		 707static const arch_entry cpu_arch[] =
708{
89507696
JB		 709 /* Do not replace the first two entries - i386_target_format()
710 relies on them being there in this order. */
8a2c8fef 711 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 712 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 713 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 714 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 715 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 716 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 717 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 718 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 719 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 720 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 721 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 722 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 723 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 724 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 725 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 726 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 727 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 728 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 729 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 730 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 731 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 732 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 733 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 734 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 735 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 736 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 737 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 738 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 739 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 740 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 741 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 742 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 743 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 744 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 745 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 746 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 747 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 748 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 749 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 750 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 751 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 752 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 753 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 754 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 755 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
756 CPU_K1OM_FLAGS, 0, 0 },
8a2c8fef 757 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 758 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 759 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 760 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 761 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 762 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 763 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 764 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 765 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 766 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 767 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 768 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 769 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 770 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 771 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 772 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 773 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 774 CPU_BDVER2_FLAGS, 0, 0 },
5e5c50d3
NE		 775 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
776 CPU_BDVER3_FLAGS, 0, 0 },
c7b0bd56
SE		 777 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
778 CPU_BDVER4_FLAGS, 0, 0 },
7b458c12
L		 779 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
780 CPU_BTVER1_FLAGS, 0, 0 },
781 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
782 CPU_BTVER2_FLAGS, 0, 0 },
8a2c8fef 783 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 784 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 785 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 786 CPU_287_FLAGS, 0, 0 },
8a2c8fef 787 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 788 CPU_387_FLAGS, 0, 0 },
8a2c8fef 789 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 790 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 791 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 792 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 793 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 794 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 795 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 796 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 797 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 798 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 799 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 800 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 801 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 802 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 803 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 804 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 805 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 806 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 807 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 808 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 809 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 810 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 811 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 812 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 813 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
814 CPU_AVX2_FLAGS, 0, 0 },
43234a1e
L		 815 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
816 CPU_AVX512F_FLAGS, 0, 0 },
817 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
818 CPU_AVX512CD_FLAGS, 0, 0 },
819 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
820 CPU_AVX512ER_FLAGS, 0, 0 },
821 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
822 CPU_AVX512PF_FLAGS, 0, 0 },
8a2c8fef 823 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 824 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 825 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 826 CPU_VMX_FLAGS, 0, 0 },
8729a6f6
L		 827 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
828 CPU_VMFUNC_FLAGS, 0, 0 },
8a2c8fef 829 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 830 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 831 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 832 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 833 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 834 CPU_XSAVEOPT_FLAGS, 0, 0 },
8a2c8fef 835 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 836 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 837 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 838 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 839 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 840 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 841 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 842 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 843 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 844 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 845 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 846 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 847 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
848 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 849 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 850 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 851 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 852 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 853 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 854 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 855 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 856 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 857 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 858 CPU_MOVBE_FLAGS, 0, 0 },
60aa667e
L		 859 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
860 CPU_CX16_FLAGS, 0, 0 },
8a2c8fef 861 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 862 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 863 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
864 CPU_LZCNT_FLAGS, 0, 0 },
42164a71
L		 865 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
866 CPU_HLE_FLAGS, 0, 0 },
867 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
868 CPU_RTM_FLAGS, 0, 0 },
6c30d220
L		 869 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
870 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 871 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 872 CPU_CLFLUSH_FLAGS, 0, 0 },
873 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
874 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 875 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 876 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 877 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 878 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 879 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 880 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 881 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 882 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 883 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 884 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 885 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 886 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 887 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 888 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 889 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 890 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 891 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 892 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 893 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
894 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 895 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
896 CPU_TBM_FLAGS, 0, 0 },
e2e1fcde
L		 897 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
898 CPU_ADX_FLAGS, 0, 0 },
899 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
900 CPU_RDSEED_FLAGS, 0, 0 },
901 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
902 CPU_PRFCHW_FLAGS, 0, 0 },
5c111e37
L		 903 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
904 CPU_SMAP_FLAGS, 0, 0 },
7e8b059b
L		 905 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
906 CPU_MPX_FLAGS, 0, 0 },
a0046408
L		 907 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
908 CPU_SHA_FLAGS, 0, 0 },
963f3586
IT		 909 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
910 CPU_CLFLUSHOPT_FLAGS, 0, 0 },
911 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
912 CPU_XSAVEC_FLAGS, 0, 0 },
913 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
914 CPU_XSAVES_FLAGS, 0, 0 },
dcf893b5
IT		 915 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
916 CPU_PREFETCHWT1_FLAGS, 0, 0 },
e413e4e9
AM		 917};
918
704209c0 919#ifdef I386COFF
a6c24e68
NC		 920/* Like s_lcomm_internal in gas/read.c but the alignment string
921 is allowed to be optional. */
922
923static symbolS *
924pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
925{
926 addressT align = 0;
927
928 SKIP_WHITESPACE ();
929
7ab9ffdd 930 if (needs_align
a6c24e68
NC		 931 && *input_line_pointer == ',')
932 {
933 align = parse_align (needs_align - 1);
7ab9ffdd 934
a6c24e68
NC		 935 if (align == (addressT) -1)
936 return NULL;
937 }
938 else
939 {
940 if (size >= 8)
941 align = 3;
942 else if (size >= 4)
943 align = 2;
944 else if (size >= 2)
945 align = 1;
946 else
947 align = 0;
948 }
949
950 bss_alloc (symbolP, size, align);
951 return symbolP;
952}
953
704209c0 954static void
a6c24e68
NC		 955pe_lcomm (int needs_align)
956{
957 s_comm_internal (needs_align * 2, pe_lcomm_internal);
958}
704209c0 959#endif
a6c24e68 960
29b0f896
AM		 961const pseudo_typeS md_pseudo_table[] =
962{
963#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
964 {"align", s_align_bytes, 0},
965#else
966 {"align", s_align_ptwo, 0},
967#endif
968 {"arch", set_cpu_arch, 0},
969#ifndef I386COFF
970 {"bss", s_bss, 0},
a6c24e68
NC		 971#else
972 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 973#endif
974 {"ffloat", float_cons, 'f'},
975 {"dfloat", float_cons, 'd'},
976 {"tfloat", float_cons, 'x'},
977 {"value", cons, 2},
d182319b 978 {"slong", signed_cons, 4},
29b0f896
AM		 979 {"noopt", s_ignore, 0},
980 {"optim", s_ignore, 0},
981 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
982 {"code16", set_code_flag, CODE_16BIT},
983 {"code32", set_code_flag, CODE_32BIT},
984 {"code64", set_code_flag, CODE_64BIT},
985 {"intel_syntax", set_intel_syntax, 1},
986 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 987 {"intel_mnemonic", set_intel_mnemonic, 1},
988 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 989 {"allow_index_reg", set_allow_index_reg, 1},
990 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 991 {"sse_check", set_check, 0},
992 {"operand_check", set_check, 1},
3b22753a
L		 993#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
994 {"largecomm", handle_large_common, 0},
07a53e5c 995#else
e3bb37b5 996 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 997 {"loc", dwarf2_directive_loc, 0},
998 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 999#endif
6482c264
NC		 1000#ifdef TE_PE
1001 {"secrel32", pe_directive_secrel, 0},
1002#endif
29b0f896
AM		 1003 {0, 0, 0}
1004};
1005
1006/* For interface with expression (). */
1007extern char *input_line_pointer;
1008
1009/* Hash table for instruction mnemonic lookup. */
1010static struct hash_control *op_hash;
1011
1012/* Hash table for register lookup. */
1013static struct hash_control *reg_hash;
1014\f
252b5132 1015void
e3bb37b5 1016i386_align_code (fragS *fragP, int count)
252b5132 1017{
ce8a8b2f
AM		 1018 /* Various efficient no-op patterns for aligning code labels.
1019 Note: Don't try to assemble the instructions in the comments.
1020 0L and 0w are not legal. */
252b5132
RH		 1021 static const char f32_1[] =
1022 {0x90}; /* nop */
1023 static const char f32_2[] =
ccc9c027 1024 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 1025 static const char f32_3[] =
1026 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1027 static const char f32_4[] =
1028 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1029 static const char f32_5[] =
1030 {0x90, /* nop */
1031 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1032 static const char f32_6[] =
1033 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1034 static const char f32_7[] =
1035 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1036 static const char f32_8[] =
1037 {0x90, /* nop */
1038 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1039 static const char f32_9[] =
1040 {0x89,0xf6, /* movl %esi,%esi */
1041 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1042 static const char f32_10[] =
1043 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1044 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1045 static const char f32_11[] =
1046 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1047 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1048 static const char f32_12[] =
1049 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1050 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1051 static const char f32_13[] =
1052 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1053 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1054 static const char f32_14[] =
1055 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1056 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 1057 static const char f16_3[] =
1058 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 1059 static const char f16_4[] =
1060 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1061 static const char f16_5[] =
1062 {0x90, /* nop */
1063 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1064 static const char f16_6[] =
1065 {0x89,0xf6, /* mov %si,%si */
1066 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1067 static const char f16_7[] =
1068 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1069 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1070 static const char f16_8[] =
1071 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1072 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 1073 static const char jump_31[] =
1074 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1075 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1076 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1077 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 1078 static const char *const f32_patt[] = {
1079 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1080 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 1081 };
1082 static const char *const f16_patt[] = {
76bc74dc 1083 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1084 };
ccc9c027
L		 1085 /* nopl (%[re]ax) */
1086 static const char alt_3[] =
1087 {0x0f,0x1f,0x00};
1088 /* nopl 0(%[re]ax) */
1089 static const char alt_4[] =
1090 {0x0f,0x1f,0x40,0x00};
1091 /* nopl 0(%[re]ax,%[re]ax,1) */
1092 static const char alt_5[] =
1093 {0x0f,0x1f,0x44,0x00,0x00};
1094 /* nopw 0(%[re]ax,%[re]ax,1) */
1095 static const char alt_6[] =
1096 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1097 /* nopl 0L(%[re]ax) */
1098 static const char alt_7[] =
1099 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1100 /* nopl 0L(%[re]ax,%[re]ax,1) */
1101 static const char alt_8[] =
1102 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1103 /* nopw 0L(%[re]ax,%[re]ax,1) */
1104 static const char alt_9[] =
1105 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1106 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1107 static const char alt_10[] =
1108 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1109 /* data16
1110 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1111 static const char alt_long_11[] =
1112 {0x66,
1113 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1114 /* data16
1115 data16
1116 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1117 static const char alt_long_12[] =
1118 {0x66,
1119 0x66,
1120 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1121 /* data16
1122 data16
1123 data16
1124 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1125 static const char alt_long_13[] =
1126 {0x66,
1127 0x66,
1128 0x66,
1129 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1130 /* data16
1131 data16
1132 data16
1133 data16
1134 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1135 static const char alt_long_14[] =
1136 {0x66,
1137 0x66,
1138 0x66,
1139 0x66,
1140 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1141 /* data16
1142 data16
1143 data16
1144 data16
1145 data16
1146 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1147 static const char alt_long_15[] =
1148 {0x66,
1149 0x66,
1150 0x66,
1151 0x66,
1152 0x66,
1153 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1154 /* nopl 0(%[re]ax,%[re]ax,1)
1155 nopw 0(%[re]ax,%[re]ax,1) */
1156 static const char alt_short_11[] =
1157 {0x0f,0x1f,0x44,0x00,0x00,
1158 0x66,0x0f,0x1f,0x44,0x00,0x00};
1159 /* nopw 0(%[re]ax,%[re]ax,1)
1160 nopw 0(%[re]ax,%[re]ax,1) */
1161 static const char alt_short_12[] =
1162 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1163 0x66,0x0f,0x1f,0x44,0x00,0x00};
1164 /* nopw 0(%[re]ax,%[re]ax,1)
1165 nopl 0L(%[re]ax) */
1166 static const char alt_short_13[] =
1167 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1168 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1169 /* nopl 0L(%[re]ax)
1170 nopl 0L(%[re]ax) */
1171 static const char alt_short_14[] =
1172 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1173 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1174 /* nopl 0L(%[re]ax)
1175 nopl 0L(%[re]ax,%[re]ax,1) */
1176 static const char alt_short_15[] =
1177 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1178 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1179 static const char *const alt_short_patt[] = {
1180 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1181 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
1182 alt_short_14, alt_short_15
1183 };
1184 static const char *const alt_long_patt[] = {
1185 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1186 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1187 alt_long_14, alt_long_15
1188 };
252b5132 1189
76bc74dc
L		 1190 /* Only align for at least a positive non-zero boundary. */
1191 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1192 return;
3e73aa7c 1193
ccc9c027
L		 1194 /* We need to decide which NOP sequence to use for 32bit and
1195 64bit. When -mtune= is used:
4eed87de 1196
76bc74dc
L		 1197 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1198 PROCESSOR_GENERIC32, f32_patt will be used.
1199 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 1200 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1201 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 1202 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
7b458c12 1203 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
69dd9865 1204 will be used.
ccc9c027 1205
76bc74dc 1206 When -mtune= isn't used, alt_long_patt will be used if
22109423 1207 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1208 be used.
ccc9c027
L		 1209
1210 When -march= or .arch is used, we can't use anything beyond
1211 cpu_arch_isa_flags. */
1212
1213 if (flag_code == CODE_16BIT)
1214 {
ccc9c027 1215 if (count > 8)
33fef721 1216 {
76bc74dc
L		 1217 memcpy (fragP->fr_literal + fragP->fr_fix,
1218 jump_31, count);
1219 /* Adjust jump offset. */
1220 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1221 }
76bc74dc
L		 1222 else
1223 memcpy (fragP->fr_literal + fragP->fr_fix,
1224 f16_patt[count - 1], count);
252b5132 1225 }
33fef721 1226 else
ccc9c027
L		 1227 {
1228 const char *const *patt = NULL;
1229
fbf3f584 1230 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1231 {
1232 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1233 switch (cpu_arch_tune)
1234 {
1235 case PROCESSOR_UNKNOWN:
1236 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1237 optimize with nops. */
1238 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1239 patt = alt_long_patt;
ccc9c027
L		 1240 else
1241 patt = f32_patt;
1242 break;
ccc9c027
L		 1243 case PROCESSOR_PENTIUM4:
1244 case PROCESSOR_NOCONA:
ef05d495 1245 case PROCESSOR_CORE:
76bc74dc 1246 case PROCESSOR_CORE2:
bd5295b2 1247 case PROCESSOR_COREI7:
3632d14b 1248 case PROCESSOR_L1OM:
7a9068fe 1249 case PROCESSOR_K1OM:
76bc74dc
L		 1250 case PROCESSOR_GENERIC64:
1251 patt = alt_long_patt;
1252 break;
ccc9c027
L		 1253 case PROCESSOR_K6:
1254 case PROCESSOR_ATHLON:
1255 case PROCESSOR_K8:
4eed87de 1256 case PROCESSOR_AMDFAM10:
8aedb9fe 1257 case PROCESSOR_BD:
7b458c12 1258 case PROCESSOR_BT:
ccc9c027
L		 1259 patt = alt_short_patt;
1260 break;
76bc74dc 1261 case PROCESSOR_I386:
ccc9c027
L		 1262 case PROCESSOR_I486:
1263 case PROCESSOR_PENTIUM:
2dde1948 1264 case PROCESSOR_PENTIUMPRO:
ccc9c027
L		 1265 case PROCESSOR_GENERIC32:
1266 patt = f32_patt;
1267 break;
4eed87de 1268 }
ccc9c027
L		 1269 }
1270 else
1271 {
fbf3f584 1272 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1273 {
1274 case PROCESSOR_UNKNOWN:
e6a14101 1275 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1276 PROCESSOR_UNKNOWN. */
1277 abort ();
1278 break;
1279
76bc74dc 1280 case PROCESSOR_I386:
ccc9c027
L		 1281 case PROCESSOR_I486:
1282 case PROCESSOR_PENTIUM:
ccc9c027
L		 1283 case PROCESSOR_K6:
1284 case PROCESSOR_ATHLON:
1285 case PROCESSOR_K8:
4eed87de 1286 case PROCESSOR_AMDFAM10:
8aedb9fe 1287 case PROCESSOR_BD:
7b458c12 1288 case PROCESSOR_BT:
ccc9c027
L		 1289 case PROCESSOR_GENERIC32:
1290 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1291 with nops. */
1292 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1293 patt = alt_short_patt;
1294 else
1295 patt = f32_patt;
1296 break;
76bc74dc
L		 1297 case PROCESSOR_PENTIUMPRO:
1298 case PROCESSOR_PENTIUM4:
1299 case PROCESSOR_NOCONA:
1300 case PROCESSOR_CORE:
ef05d495 1301 case PROCESSOR_CORE2:
bd5295b2 1302 case PROCESSOR_COREI7:
3632d14b 1303 case PROCESSOR_L1OM:
7a9068fe 1304 case PROCESSOR_K1OM:
22109423 1305 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1306 patt = alt_long_patt;
1307 else
1308 patt = f32_patt;
1309 break;
1310 case PROCESSOR_GENERIC64:
76bc74dc 1311 patt = alt_long_patt;
ccc9c027 1312 break;
4eed87de 1313 }
ccc9c027
L		 1314 }
1315
76bc74dc
L		 1316 if (patt == f32_patt)
1317 {
1318 /* If the padding is less than 15 bytes, we use the normal
1319 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1320 its offset. */
1321 int limit;
76ba9986 1322
711eedef
L		 1323 /* For 64bit, the limit is 3 bytes. */
1324 if (flag_code == CODE_64BIT
1325 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1326 limit = 3;
1327 else
1328 limit = 15;
1329 if (count < limit)
76bc74dc
L		 1330 memcpy (fragP->fr_literal + fragP->fr_fix,
1331 patt[count - 1], count);
1332 else
1333 {
1334 memcpy (fragP->fr_literal + fragP->fr_fix,
1335 jump_31, count);
1336 /* Adjust jump offset. */
1337 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1338 }
1339 }
1340 else
1341 {
1342 /* Maximum length of an instruction is 15 byte. If the
1343 padding is greater than 15 bytes and we don't use jump,
1344 we have to break it into smaller pieces. */
1345 int padding = count;
1346 while (padding > 15)
1347 {
1348 padding -= 15;
1349 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1350 patt [14], 15);
1351 }
1352
1353 if (padding)
1354 memcpy (fragP->fr_literal + fragP->fr_fix,
1355 patt [padding - 1], padding);
1356 }
ccc9c027 1357 }
33fef721 1358 fragP->fr_var = count;
252b5132
RH		 1359}
1360
c6fb90c8 1361static INLINE int
0dfbf9d7 1362operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1363{
0dfbf9d7 1364 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1365 {
1366 case 3:
0dfbf9d7 1367 if (x->array[2])
c6fb90c8
L		 1368 return 0;
1369 case 2:
0dfbf9d7 1370 if (x->array[1])
c6fb90c8
L		 1371 return 0;
1372 case 1:
0dfbf9d7 1373 return !x->array[0];
c6fb90c8
L		 1374 default:
1375 abort ();
1376 }
40fb9820
L		 1377}
1378
c6fb90c8 1379static INLINE void
0dfbf9d7 1380operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1381{
0dfbf9d7 1382 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1383 {
1384 case 3:
0dfbf9d7 1385 x->array[2] = v;
c6fb90c8 1386 case 2:
0dfbf9d7 1387 x->array[1] = v;
c6fb90c8 1388 case 1:
0dfbf9d7 1389 x->array[0] = v;
c6fb90c8
L		 1390 break;
1391 default:
1392 abort ();
1393 }
1394}
40fb9820 1395
c6fb90c8 1396static INLINE int
0dfbf9d7
L		 1397operand_type_equal (const union i386_operand_type *x,
1398 const union i386_operand_type *y)
c6fb90c8 1399{
0dfbf9d7 1400 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1401 {
1402 case 3:
0dfbf9d7 1403 if (x->array[2] != y->array[2])
c6fb90c8
L		 1404 return 0;
1405 case 2:
0dfbf9d7 1406 if (x->array[1] != y->array[1])
c6fb90c8
L		 1407 return 0;
1408 case 1:
0dfbf9d7 1409 return x->array[0] == y->array[0];
c6fb90c8
L		 1410 break;
1411 default:
1412 abort ();
1413 }
1414}
40fb9820 1415
0dfbf9d7
L		 1416static INLINE int
1417cpu_flags_all_zero (const union i386_cpu_flags *x)
1418{
1419 switch (ARRAY_SIZE(x->array))
1420 {
1421 case 3:
1422 if (x->array[2])
1423 return 0;
1424 case 2:
1425 if (x->array[1])
1426 return 0;
1427 case 1:
1428 return !x->array[0];
1429 default:
1430 abort ();
1431 }
1432}
1433
1434static INLINE void
1435cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1436{
1437 switch (ARRAY_SIZE(x->array))
1438 {
1439 case 3:
1440 x->array[2] = v;
1441 case 2:
1442 x->array[1] = v;
1443 case 1:
1444 x->array[0] = v;
1445 break;
1446 default:
1447 abort ();
1448 }
1449}
1450
1451static INLINE int
1452cpu_flags_equal (const union i386_cpu_flags *x,
1453 const union i386_cpu_flags *y)
1454{
1455 switch (ARRAY_SIZE(x->array))
1456 {
1457 case 3:
1458 if (x->array[2] != y->array[2])
1459 return 0;
1460 case 2:
1461 if (x->array[1] != y->array[1])
1462 return 0;
1463 case 1:
1464 return x->array[0] == y->array[0];
1465 break;
1466 default:
1467 abort ();
1468 }
1469}
c6fb90c8
L		 1470
1471static INLINE int
1472cpu_flags_check_cpu64 (i386_cpu_flags f)
1473{
1474 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1475 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1476}
1477
c6fb90c8
L		 1478static INLINE i386_cpu_flags
1479cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1480{
c6fb90c8
L		 1481 switch (ARRAY_SIZE (x.array))
1482 {
1483 case 3:
1484 x.array [2] &= y.array [2];
1485 case 2:
1486 x.array [1] &= y.array [1];
1487 case 1:
1488 x.array [0] &= y.array [0];
1489 break;
1490 default:
1491 abort ();
1492 }
1493 return x;
1494}
40fb9820 1495
c6fb90c8
L		 1496static INLINE i386_cpu_flags
1497cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1498{
c6fb90c8 1499 switch (ARRAY_SIZE (x.array))
40fb9820 1500 {
c6fb90c8
L		 1501 case 3:
1502 x.array [2] |= y.array [2];
1503 case 2:
1504 x.array [1] |= y.array [1];
1505 case 1:
1506 x.array [0] |= y.array [0];
40fb9820
L		 1507 break;
1508 default:
1509 abort ();
1510 }
40fb9820
L		 1511 return x;
1512}
1513
309d3373
JB		 1514static INLINE i386_cpu_flags
1515cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1516{
1517 switch (ARRAY_SIZE (x.array))
1518 {
1519 case 3:
1520 x.array [2] &= ~y.array [2];
1521 case 2:
1522 x.array [1] &= ~y.array [1];
1523 case 1:
1524 x.array [0] &= ~y.array [0];
1525 break;
1526 default:
1527 abort ();
1528 }
1529 return x;
1530}
1531
c0f3af97
L		 1532#define CPU_FLAGS_ARCH_MATCH 0x1
1533#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1534#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1535#define CPU_FLAGS_PCLMUL_MATCH 0x8
1536#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1537
a5ff0eb2 1538#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1539 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1540 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1541#define CPU_FLAGS_PERFECT_MATCH \
1542 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1543
1544/* Return CPU flags match bits. */
3629bb00 1545
40fb9820 1546static int
d3ce72d0 1547cpu_flags_match (const insn_template *t)
40fb9820 1548{
c0f3af97
L		 1549 i386_cpu_flags x = t->cpu_flags;
1550 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1551
1552 x.bitfield.cpu64 = 0;
1553 x.bitfield.cpuno64 = 0;
1554
0dfbf9d7 1555 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1556 {
1557 /* This instruction is available on all archs. */
1558 match |= CPU_FLAGS_32BIT_MATCH;
1559 }
3629bb00
L		 1560 else
1561 {
c0f3af97 1562 /* This instruction is available only on some archs. */
3629bb00
L		 1563 i386_cpu_flags cpu = cpu_arch_flags;
1564
1565 cpu.bitfield.cpu64 = 0;
1566 cpu.bitfield.cpuno64 = 0;
1567 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1568 if (!cpu_flags_all_zero (&cpu))
1569 {
a5ff0eb2
L		 1570 if (x.bitfield.cpuavx)
1571 {
ce2f5b3c 1572 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1573 if (cpu.bitfield.cpuavx)
1574 {
1575 /* Check SSE2AVX. */
1576 if (!t->opcode_modifier.sse2avx|| sse2avx)
1577 {
1578 match |= (CPU_FLAGS_ARCH_MATCH
1579 | CPU_FLAGS_AVX_MATCH);
1580 /* Check AES. */
1581 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1582 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1583 /* Check PCLMUL. */
1584 if (!x.bitfield.cpupclmul
1585 || cpu.bitfield.cpupclmul)
1586 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1587 }
1588 }
1589 else
1590 match |= CPU_FLAGS_ARCH_MATCH;
1591 }
1592 else
c0f3af97
L		 1593 match |= CPU_FLAGS_32BIT_MATCH;
1594 }
3629bb00 1595 }
c0f3af97 1596 return match;
40fb9820
L		 1597}
1598
c6fb90c8
L		 1599static INLINE i386_operand_type
1600operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1601{
c6fb90c8
L		 1602 switch (ARRAY_SIZE (x.array))
1603 {
1604 case 3:
1605 x.array [2] &= y.array [2];
1606 case 2:
1607 x.array [1] &= y.array [1];
1608 case 1:
1609 x.array [0] &= y.array [0];
1610 break;
1611 default:
1612 abort ();
1613 }
1614 return x;
40fb9820
L		 1615}
1616
c6fb90c8
L		 1617static INLINE i386_operand_type
1618operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1619{
c6fb90c8 1620 switch (ARRAY_SIZE (x.array))
40fb9820 1621 {
c6fb90c8
L		 1622 case 3:
1623 x.array [2] |= y.array [2];
1624 case 2:
1625 x.array [1] |= y.array [1];
1626 case 1:
1627 x.array [0] |= y.array [0];
40fb9820
L		 1628 break;
1629 default:
1630 abort ();
1631 }
c6fb90c8
L		 1632 return x;
1633}
40fb9820 1634
c6fb90c8
L		 1635static INLINE i386_operand_type
1636operand_type_xor (i386_operand_type x, i386_operand_type y)
1637{
1638 switch (ARRAY_SIZE (x.array))
1639 {
1640 case 3:
1641 x.array [2] ^= y.array [2];
1642 case 2:
1643 x.array [1] ^= y.array [1];
1644 case 1:
1645 x.array [0] ^= y.array [0];
1646 break;
1647 default:
1648 abort ();
1649 }
40fb9820
L		 1650 return x;
1651}
1652
1653static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1654static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1655static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1656static const i386_operand_type inoutportreg
1657 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1658static const i386_operand_type reg16_inoutportreg
1659 = OPERAND_TYPE_REG16_INOUTPORTREG;
1660static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1661static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1662static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1663static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1664static const i386_operand_type anydisp
1665 = OPERAND_TYPE_ANYDISP;
40fb9820 1666static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1667static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1668static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1669static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1670static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1671static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1672static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1673static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1674static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1675static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1676static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1677static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1678static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1679static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1680
1681enum operand_type
1682{
1683 reg,
40fb9820
L		 1684 imm,
1685 disp,
1686 anymem
1687};
1688
c6fb90c8 1689static INLINE int
40fb9820
L		 1690operand_type_check (i386_operand_type t, enum operand_type c)
1691{
1692 switch (c)
1693 {
1694 case reg:
1695 return (t.bitfield.reg8
1696 || t.bitfield.reg16
1697 || t.bitfield.reg32
1698 || t.bitfield.reg64);
1699
40fb9820
L		 1700 case imm:
1701 return (t.bitfield.imm8
1702 || t.bitfield.imm8s
1703 || t.bitfield.imm16
1704 || t.bitfield.imm32
1705 || t.bitfield.imm32s
1706 || t.bitfield.imm64);
1707
1708 case disp:
1709 return (t.bitfield.disp8
1710 || t.bitfield.disp16
1711 || t.bitfield.disp32
1712 || t.bitfield.disp32s
1713 || t.bitfield.disp64);
1714
1715 case anymem:
1716 return (t.bitfield.disp8
1717 || t.bitfield.disp16
1718 || t.bitfield.disp32
1719 || t.bitfield.disp32s
1720 || t.bitfield.disp64
1721 || t.bitfield.baseindex);
1722
1723 default:
1724 abort ();
1725 }
2cfe26b6
AM		 1726
1727 return 0;
40fb9820
L		 1728}
1729
5c07affc
L		 1730/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1731 operand J for instruction template T. */
1732
1733static INLINE int
d3ce72d0 1734match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1735{
1736 return !((i.types[j].bitfield.byte
1737 && !t->operand_types[j].bitfield.byte)
1738 || (i.types[j].bitfield.word
1739 && !t->operand_types[j].bitfield.word)
1740 || (i.types[j].bitfield.dword
1741 && !t->operand_types[j].bitfield.dword)
1742 || (i.types[j].bitfield.qword
1743 && !t->operand_types[j].bitfield.qword));
1744}
1745
1746/* Return 1 if there is no conflict in any size on operand J for
1747 instruction template T. */
1748
1749static INLINE int
d3ce72d0 1750match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1751{
1752 return (match_reg_size (t, j)
1753 && !((i.types[j].bitfield.unspecified
1754 && !t->operand_types[j].bitfield.unspecified)
1755 || (i.types[j].bitfield.fword
1756 && !t->operand_types[j].bitfield.fword)
1757 || (i.types[j].bitfield.tbyte
1758 && !t->operand_types[j].bitfield.tbyte)
1759 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1760 && !t->operand_types[j].bitfield.xmmword)
1761 || (i.types[j].bitfield.ymmword
43234a1e
L		 1762 && !t->operand_types[j].bitfield.ymmword)
1763 || (i.types[j].bitfield.zmmword
1764 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1765}
1766
1767/* Return 1 if there is no size conflict on any operands for
1768 instruction template T. */
1769
1770static INLINE int
d3ce72d0 1771operand_size_match (const insn_template *t)
5c07affc
L		 1772{
1773 unsigned int j;
1774 int match = 1;
1775
1776 /* Don't check jump instructions. */
1777 if (t->opcode_modifier.jump
1778 || t->opcode_modifier.jumpbyte
1779 || t->opcode_modifier.jumpdword
1780 || t->opcode_modifier.jumpintersegment)
1781 return match;
1782
1783 /* Check memory and accumulator operand size. */
1784 for (j = 0; j < i.operands; j++)
1785 {
1786 if (t->operand_types[j].bitfield.anysize)
1787 continue;
1788
1789 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1790 {
1791 match = 0;
1792 break;
1793 }
1794
1795 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1796 {
1797 match = 0;
1798 break;
1799 }
1800 }
1801
891edac4 1802 if (match)
5c07affc 1803 return match;
891edac4
L		 1804 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1805 {
1806mismatch:
86e026a4 1807 i.error = operand_size_mismatch;
891edac4
L		 1808 return 0;
1809 }
5c07affc
L		 1810
1811 /* Check reverse. */
9c2799c2 1812 gas_assert (i.operands == 2);
5c07affc
L		 1813
1814 match = 1;
1815 for (j = 0; j < 2; j++)
1816 {
1817 if (t->operand_types[j].bitfield.acc
1818 && !match_reg_size (t, j ? 0 : 1))
891edac4 1819 goto mismatch;
5c07affc
L		 1820
1821 if (i.types[j].bitfield.mem
1822 && !match_mem_size (t, j ? 0 : 1))
891edac4 1823 goto mismatch;
5c07affc
L		 1824 }
1825
1826 return match;
1827}
1828
c6fb90c8 1829static INLINE int
40fb9820
L		 1830operand_type_match (i386_operand_type overlap,
1831 i386_operand_type given)
1832{
1833 i386_operand_type temp = overlap;
1834
1835 temp.bitfield.jumpabsolute = 0;
7d5e4556 1836 temp.bitfield.unspecified = 0;
5c07affc
L		 1837 temp.bitfield.byte = 0;
1838 temp.bitfield.word = 0;
1839 temp.bitfield.dword = 0;
1840 temp.bitfield.fword = 0;
1841 temp.bitfield.qword = 0;
1842 temp.bitfield.tbyte = 0;
1843 temp.bitfield.xmmword = 0;
c0f3af97 1844 temp.bitfield.ymmword = 0;
43234a1e 1845 temp.bitfield.zmmword = 0;
0dfbf9d7 1846 if (operand_type_all_zero (&temp))
891edac4 1847 goto mismatch;
40fb9820 1848
891edac4
L		 1849 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1850 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1851 return 1;
1852
1853mismatch:
a65babc9 1854 i.error = operand_type_mismatch;
891edac4 1855 return 0;
40fb9820
L		 1856}
1857
7d5e4556 1858/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1859 unless the expected operand type register overlap is null.
1860 Note that Acc in a template matches every size of reg. */
1861
c6fb90c8 1862static INLINE int
40fb9820
L		 1863operand_type_register_match (i386_operand_type m0,
1864 i386_operand_type g0,
1865 i386_operand_type t0,
1866 i386_operand_type m1,
1867 i386_operand_type g1,
1868 i386_operand_type t1)
1869{
1870 if (!operand_type_check (g0, reg))
1871 return 1;
1872
1873 if (!operand_type_check (g1, reg))
1874 return 1;
1875
1876 if (g0.bitfield.reg8 == g1.bitfield.reg8
1877 && g0.bitfield.reg16 == g1.bitfield.reg16
1878 && g0.bitfield.reg32 == g1.bitfield.reg32
1879 && g0.bitfield.reg64 == g1.bitfield.reg64)
1880 return 1;
1881
1882 if (m0.bitfield.acc)
1883 {
1884 t0.bitfield.reg8 = 1;
1885 t0.bitfield.reg16 = 1;
1886 t0.bitfield.reg32 = 1;
1887 t0.bitfield.reg64 = 1;
1888 }
1889
1890 if (m1.bitfield.acc)
1891 {
1892 t1.bitfield.reg8 = 1;
1893 t1.bitfield.reg16 = 1;
1894 t1.bitfield.reg32 = 1;
1895 t1.bitfield.reg64 = 1;
1896 }
1897
891edac4
L		 1898 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1899 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1900 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1901 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1902 return 1;
1903
a65babc9 1904 i.error = register_type_mismatch;
891edac4
L		 1905
1906 return 0;
40fb9820
L		 1907}
1908
4c692bc7
JB		 1909static INLINE unsigned int
1910register_number (const reg_entry *r)
1911{
1912 unsigned int nr = r->reg_num;
1913
1914 if (r->reg_flags & RegRex)
1915 nr += 8;
1916
1917 return nr;
1918}
1919
252b5132 1920static INLINE unsigned int
40fb9820 1921mode_from_disp_size (i386_operand_type t)
252b5132 1922{
43234a1e 1923 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1924 return 1;
1925 else if (t.bitfield.disp16
1926 || t.bitfield.disp32
1927 || t.bitfield.disp32s)
1928 return 2;
1929 else
1930 return 0;
252b5132
RH		 1931}
1932
1933static INLINE int
e3bb37b5 1934fits_in_signed_byte (offsetT num)
252b5132
RH		 1935{
1936 return (num >= -128) && (num <= 127);
47926f60 1937}
252b5132
RH		 1938
1939static INLINE int
e3bb37b5 1940fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1941{
1942 return (num & 0xff) == num;
47926f60 1943}
252b5132
RH		 1944
1945static INLINE int
e3bb37b5 1946fits_in_unsigned_word (offsetT num)
252b5132
RH		 1947{
1948 return (num & 0xffff) == num;
47926f60 1949}
252b5132
RH		 1950
1951static INLINE int
e3bb37b5 1952fits_in_signed_word (offsetT num)
252b5132
RH		 1953{
1954 return (-32768 <= num) && (num <= 32767);
47926f60 1955}
2a962e6d 1956
3e73aa7c 1957static INLINE int
e3bb37b5 1958fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1959{
1960#ifndef BFD64
1961 return 1;
1962#else
1963 return (!(((offsetT) -1 << 31) & num)
1964 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1965#endif
1966} /* fits_in_signed_long() */
2a962e6d 1967
3e73aa7c 1968static INLINE int
e3bb37b5 1969fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1970{
1971#ifndef BFD64
1972 return 1;
1973#else
1974 return (num & (((offsetT) 2 << 31) - 1)) == num;
1975#endif
1976} /* fits_in_unsigned_long() */
252b5132 1977
43234a1e
L		 1978static INLINE int
1979fits_in_vec_disp8 (offsetT num)
1980{
1981 int shift = i.memshift;
1982 unsigned int mask;
1983
1984 if (shift == -1)
1985 abort ();
1986
1987 mask = (1 << shift) - 1;
1988
1989 /* Return 0 if NUM isn't properly aligned. */
1990 if ((num & mask))
1991 return 0;
1992
1993 /* Check if NUM will fit in 8bit after shift. */
1994 return fits_in_signed_byte (num >> shift);
1995}
1996
a683cc34
SP		 1997static INLINE int
1998fits_in_imm4 (offsetT num)
1999{
2000 return (num & 0xf) == num;
2001}
2002
40fb9820 2003static i386_operand_type
e3bb37b5 2004smallest_imm_type (offsetT num)
252b5132 2005{
40fb9820 2006 i386_operand_type t;
7ab9ffdd 2007
0dfbf9d7 2008 operand_type_set (&t, 0);
40fb9820
L		 2009 t.bitfield.imm64 = 1;
2010
2011 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2012 {
2013 /* This code is disabled on the 486 because all the Imm1 forms
2014 in the opcode table are slower on the i486. They're the
2015 versions with the implicitly specified single-position
2016 displacement, which has another syntax if you really want to
2017 use that form. */
40fb9820
L		 2018 t.bitfield.imm1 = 1;
2019 t.bitfield.imm8 = 1;
2020 t.bitfield.imm8s = 1;
2021 t.bitfield.imm16 = 1;
2022 t.bitfield.imm32 = 1;
2023 t.bitfield.imm32s = 1;
2024 }
2025 else if (fits_in_signed_byte (num))
2026 {
2027 t.bitfield.imm8 = 1;
2028 t.bitfield.imm8s = 1;
2029 t.bitfield.imm16 = 1;
2030 t.bitfield.imm32 = 1;
2031 t.bitfield.imm32s = 1;
2032 }
2033 else if (fits_in_unsigned_byte (num))
2034 {
2035 t.bitfield.imm8 = 1;
2036 t.bitfield.imm16 = 1;
2037 t.bitfield.imm32 = 1;
2038 t.bitfield.imm32s = 1;
2039 }
2040 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2041 {
2042 t.bitfield.imm16 = 1;
2043 t.bitfield.imm32 = 1;
2044 t.bitfield.imm32s = 1;
2045 }
2046 else if (fits_in_signed_long (num))
2047 {
2048 t.bitfield.imm32 = 1;
2049 t.bitfield.imm32s = 1;
2050 }
2051 else if (fits_in_unsigned_long (num))
2052 t.bitfield.imm32 = 1;
2053
2054 return t;
47926f60 2055}
252b5132 2056
847f7ad4 2057static offsetT
e3bb37b5 2058offset_in_range (offsetT val, int size)
847f7ad4 2059{
508866be 2060 addressT mask;
ba2adb93 2061
847f7ad4
AM		 2062 switch (size)
2063 {
508866be
L		 2064 case 1: mask = ((addressT) 1 << 8) - 1; break;
2065 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2066 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2067#ifdef BFD64
2068 case 8: mask = ((addressT) 2 << 63) - 1; break;
2069#endif
47926f60 2070 default: abort ();
847f7ad4
AM		 2071 }
2072
9de868bf
L		 2073#ifdef BFD64
2074 /* If BFD64, sign extend val for 32bit address mode. */
2075 if (flag_code != CODE_64BIT
2076 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2077 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2078 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2079#endif
ba2adb93 2080
47926f60 2081 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2082 {
2083 char buf1[40], buf2[40];
2084
2085 sprint_value (buf1, val);
2086 sprint_value (buf2, val & mask);
2087 as_warn (_("%s shortened to %s"), buf1, buf2);
2088 }
2089 return val & mask;
2090}
2091
c32fa91d
L		 2092enum PREFIX_GROUP
2093{
2094 PREFIX_EXIST = 0,
2095 PREFIX_LOCK,
2096 PREFIX_REP,
2097 PREFIX_OTHER
2098};
2099
2100/* Returns
2101 a. PREFIX_EXIST if attempting to add a prefix where one from the
2102 same class already exists.
2103 b. PREFIX_LOCK if lock prefix is added.
2104 c. PREFIX_REP if rep/repne prefix is added.
2105 d. PREFIX_OTHER if other prefix is added.
2106 */
2107
2108static enum PREFIX_GROUP
e3bb37b5 2109add_prefix (unsigned int prefix)
252b5132 2110{
c32fa91d 2111 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2112 unsigned int q;
252b5132 2113
29b0f896
AM		 2114 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2115 && flag_code == CODE_64BIT)
b1905489 2116 {
161a04f6
L		 2117 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2118 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2119 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2120 ret = PREFIX_EXIST;
b1905489
JB		 2121 q = REX_PREFIX;
2122 }
3e73aa7c 2123 else
b1905489
JB		 2124 {
2125 switch (prefix)
2126 {
2127 default:
2128 abort ();
2129
2130 case CS_PREFIX_OPCODE:
2131 case DS_PREFIX_OPCODE:
2132 case ES_PREFIX_OPCODE:
2133 case FS_PREFIX_OPCODE:
2134 case GS_PREFIX_OPCODE:
2135 case SS_PREFIX_OPCODE:
2136 q = SEG_PREFIX;
2137 break;
2138
2139 case REPNE_PREFIX_OPCODE:
2140 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2141 q = REP_PREFIX;
2142 ret = PREFIX_REP;
2143 break;
2144
b1905489 2145 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2146 q = LOCK_PREFIX;
2147 ret = PREFIX_LOCK;
b1905489
JB		 2148 break;
2149
2150 case FWAIT_OPCODE:
2151 q = WAIT_PREFIX;
2152 break;
2153
2154 case ADDR_PREFIX_OPCODE:
2155 q = ADDR_PREFIX;
2156 break;
2157
2158 case DATA_PREFIX_OPCODE:
2159 q = DATA_PREFIX;
2160 break;
2161 }
2162 if (i.prefix[q] != 0)
c32fa91d 2163 ret = PREFIX_EXIST;
b1905489 2164 }
252b5132 2165
b1905489 2166 if (ret)
252b5132 2167 {
b1905489
JB		 2168 if (!i.prefix[q])
2169 ++i.prefixes;
2170 i.prefix[q] |= prefix;
252b5132 2171 }
b1905489
JB		 2172 else
2173 as_bad (_("same type of prefix used twice"));
252b5132 2174
252b5132
RH		 2175 return ret;
2176}
2177
2178static void
78f12dd3 2179update_code_flag (int value, int check)
eecb386c 2180{
78f12dd3
L		 2181 PRINTF_LIKE ((*as_error));
2182
1e9cc1c2 2183 flag_code = (enum flag_code) value;
40fb9820
L		 2184 if (flag_code == CODE_64BIT)
2185 {
2186 cpu_arch_flags.bitfield.cpu64 = 1;
2187 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2188 }
2189 else
2190 {
2191 cpu_arch_flags.bitfield.cpu64 = 0;
2192 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2193 }
2194 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2195 {
78f12dd3
L		 2196 if (check)
2197 as_error = as_fatal;
2198 else
2199 as_error = as_bad;
2200 (*as_error) (_("64bit mode not supported on `%s'."),
2201 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2202 }
40fb9820 2203 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2204 {
78f12dd3
L		 2205 if (check)
2206 as_error = as_fatal;
2207 else
2208 as_error = as_bad;
2209 (*as_error) (_("32bit mode not supported on `%s'."),
2210 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2211 }
eecb386c
AM		 2212 stackop_size = '\0';
2213}
2214
78f12dd3
L		 2215static void
2216set_code_flag (int value)
2217{
2218 update_code_flag (value, 0);
2219}
2220
eecb386c 2221static void
e3bb37b5 2222set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2223{
1e9cc1c2 2224 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2225 if (flag_code != CODE_16BIT)
2226 abort ();
2227 cpu_arch_flags.bitfield.cpu64 = 0;
2228 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2229 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2230}
2231
2232static void
e3bb37b5 2233set_intel_syntax (int syntax_flag)
252b5132
RH		 2234{
2235 /* Find out if register prefixing is specified. */
2236 int ask_naked_reg = 0;
2237
2238 SKIP_WHITESPACE ();
29b0f896 2239 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2240 {
2241 char *string = input_line_pointer;
2242 int e = get_symbol_end ();
2243
47926f60 2244 if (strcmp (string, "prefix") == 0)
252b5132 2245 ask_naked_reg = 1;
47926f60 2246 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2247 ask_naked_reg = -1;
2248 else
d0b47220 2249 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2250 *input_line_pointer = e;
2251 }
2252 demand_empty_rest_of_line ();
c3332e24 2253
252b5132
RH		 2254 intel_syntax = syntax_flag;
2255
2256 if (ask_naked_reg == 0)
f86103b7
AM		 2257 allow_naked_reg = (intel_syntax
2258 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2259 else
2260 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2261
ee86248c 2262 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2263
e4a3b5a4 2264 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2265 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2266 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2267}
2268
1efbbeb4
L		 2269static void
2270set_intel_mnemonic (int mnemonic_flag)
2271{
e1d4d893 2272 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2273}
2274
db51cc60
L		 2275static void
2276set_allow_index_reg (int flag)
2277{
2278 allow_index_reg = flag;
2279}
2280
cb19c032 2281static void
7bab8ab5 2282set_check (int what)
cb19c032 2283{
7bab8ab5
JB		 2284 enum check_kind *kind;
2285 const char *str;
2286
2287 if (what)
2288 {
2289 kind = &operand_check;
2290 str = "operand";
2291 }
2292 else
2293 {
2294 kind = &sse_check;
2295 str = "sse";
2296 }
2297
cb19c032
L		 2298 SKIP_WHITESPACE ();
2299
2300 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2301 {
2302 char *string = input_line_pointer;
2303 int e = get_symbol_end ();
2304
2305 if (strcmp (string, "none") == 0)
7bab8ab5 2306 *kind = check_none;
cb19c032 2307 else if (strcmp (string, "warning") == 0)
7bab8ab5 2308 *kind = check_warning;
cb19c032 2309 else if (strcmp (string, "error") == 0)
7bab8ab5 2310 *kind = check_error;
cb19c032 2311 else
7bab8ab5 2312 as_bad (_("bad argument to %s_check directive."), str);
cb19c032
L		 2313 *input_line_pointer = e;
2314 }
2315 else
7bab8ab5 2316 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2317
2318 demand_empty_rest_of_line ();
2319}
2320
8a9036a4
L		 2321static void
2322check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2323 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2324{
2325#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2326 static const char *arch;
2327
2328 /* Intel LIOM is only supported on ELF. */
2329 if (!IS_ELF)
2330 return;
2331
2332 if (!arch)
2333 {
2334 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2335 use default_arch. */
2336 arch = cpu_arch_name;
2337 if (!arch)
2338 arch = default_arch;
2339 }
2340
3632d14b 2341 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2342 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2343 || new_flag.bitfield.cpul1om)
8a9036a4 2344 return;
76ba9986 2345
7a9068fe
L		 2346 /* If we are targeting Intel K1OM, we must enable it. */
2347 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2348 || new_flag.bitfield.cpuk1om)
2349 return;
2350
8a9036a4
L		 2351 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2352#endif
2353}
2354
e413e4e9 2355static void
e3bb37b5 2356set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2357{
47926f60 2358 SKIP_WHITESPACE ();
e413e4e9 2359
29b0f896 2360 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2361 {
2362 char *string = input_line_pointer;
2363 int e = get_symbol_end ();
91d6fa6a 2364 unsigned int j;
40fb9820 2365 i386_cpu_flags flags;
e413e4e9 2366
91d6fa6a 2367 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2368 {
91d6fa6a 2369 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2370 {
91d6fa6a 2371 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2372
5c6af06e
JB		 2373 if (*string != '.')
2374 {
91d6fa6a 2375 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2376 cpu_sub_arch_name = NULL;
91d6fa6a 2377 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2378 if (flag_code == CODE_64BIT)
2379 {
2380 cpu_arch_flags.bitfield.cpu64 = 1;
2381 cpu_arch_flags.bitfield.cpuno64 = 0;
2382 }
2383 else
2384 {
2385 cpu_arch_flags.bitfield.cpu64 = 0;
2386 cpu_arch_flags.bitfield.cpuno64 = 1;
2387 }
91d6fa6a
NC		 2388 cpu_arch_isa = cpu_arch[j].type;
2389 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2390 if (!cpu_arch_tune_set)
2391 {
2392 cpu_arch_tune = cpu_arch_isa;
2393 cpu_arch_tune_flags = cpu_arch_isa_flags;
2394 }
5c6af06e
JB		 2395 break;
2396 }
40fb9820 2397
22109423 2398 if (!cpu_arch[j].negated)
309d3373 2399 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2400 cpu_arch[j].flags);
309d3373
JB		 2401 else
2402 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2403 cpu_arch[j].flags);
0dfbf9d7 2404 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2405 {
6305a203
L		 2406 if (cpu_sub_arch_name)
2407 {
2408 char *name = cpu_sub_arch_name;
2409 cpu_sub_arch_name = concat (name,
91d6fa6a 2410 cpu_arch[j].name,
1bf57e9f 2411 (const char *) NULL);
6305a203
L		 2412 free (name);
2413 }
2414 else
91d6fa6a 2415 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2416 cpu_arch_flags = flags;
a586129e 2417 cpu_arch_isa_flags = flags;
5c6af06e
JB		 2418 }
2419 *input_line_pointer = e;
2420 demand_empty_rest_of_line ();
2421 return;
e413e4e9
AM		 2422 }
2423 }
91d6fa6a 2424 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2425 as_bad (_("no such architecture: `%s'"), string);
2426
2427 *input_line_pointer = e;
2428 }
2429 else
2430 as_bad (_("missing cpu architecture"));
2431
fddf5b5b
AM		 2432 no_cond_jump_promotion = 0;
2433 if (*input_line_pointer == ','
29b0f896 2434 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2435 {
2436 char *string = ++input_line_pointer;
2437 int e = get_symbol_end ();
2438
2439 if (strcmp (string, "nojumps") == 0)
2440 no_cond_jump_promotion = 1;
2441 else if (strcmp (string, "jumps") == 0)
2442 ;
2443 else
2444 as_bad (_("no such architecture modifier: `%s'"), string);
2445
2446 *input_line_pointer = e;
2447 }
2448
e413e4e9
AM		 2449 demand_empty_rest_of_line ();
2450}
2451
8a9036a4
L		 2452enum bfd_architecture
2453i386_arch (void)
2454{
3632d14b 2455 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2456 {
2457 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2458 || flag_code != CODE_64BIT)
2459 as_fatal (_("Intel L1OM is 64bit ELF only"));
2460 return bfd_arch_l1om;
2461 }
7a9068fe
L		 2462 else if (cpu_arch_isa == PROCESSOR_K1OM)
2463 {
2464 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2465 || flag_code != CODE_64BIT)
2466 as_fatal (_("Intel K1OM is 64bit ELF only"));
2467 return bfd_arch_k1om;
2468 }
8a9036a4
L		 2469 else
2470 return bfd_arch_i386;
2471}
2472
b9d79e03 2473unsigned long
7016a5d5 2474i386_mach (void)
b9d79e03 2475{
351f65ca 2476 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2477 {
3632d14b 2478 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2479 {
351f65ca
L		 2480 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2481 || default_arch[6] != '\0')
8a9036a4
L		 2482 as_fatal (_("Intel L1OM is 64bit ELF only"));
2483 return bfd_mach_l1om;
2484 }
7a9068fe
L		 2485 else if (cpu_arch_isa == PROCESSOR_K1OM)
2486 {
2487 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2488 || default_arch[6] != '\0')
2489 as_fatal (_("Intel K1OM is 64bit ELF only"));
2490 return bfd_mach_k1om;
2491 }
351f65ca 2492 else if (default_arch[6] == '\0')
8a9036a4 2493 return bfd_mach_x86_64;
351f65ca
L		 2494 else
2495 return bfd_mach_x64_32;
8a9036a4 2496 }
b9d79e03
JH		 2497 else if (!strcmp (default_arch, "i386"))
2498 return bfd_mach_i386_i386;
2499 else
2b5d6a91 2500 as_fatal (_("unknown architecture"));
b9d79e03 2501}
b9d79e03 2502\f
252b5132 2503void
7016a5d5 2504md_begin (void)
252b5132
RH		 2505{
2506 const char *hash_err;
2507
47926f60 2508 /* Initialize op_hash hash table. */
252b5132
RH		 2509 op_hash = hash_new ();
2510
2511 {
d3ce72d0 2512 const insn_template *optab;
29b0f896 2513 templates *core_optab;
252b5132 2514
47926f60
KH		 2515 /* Setup for loop. */
2516 optab = i386_optab;
252b5132
RH		 2517 core_optab = (templates *) xmalloc (sizeof (templates));
2518 core_optab->start = optab;
2519
2520 while (1)
2521 {
2522 ++optab;
2523 if (optab->name == NULL
2524 || strcmp (optab->name, (optab - 1)->name) != 0)
2525 {
2526 /* different name --> ship out current template list;
47926f60 2527 add to hash table; & begin anew. */
252b5132
RH		 2528 core_optab->end = optab;
2529 hash_err = hash_insert (op_hash,
2530 (optab - 1)->name,
5a49b8ac 2531 (void *) core_optab);
252b5132
RH		 2532 if (hash_err)
2533 {
b37df7c4 2534 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2535 (optab - 1)->name,
2536 hash_err);
2537 }
2538 if (optab->name == NULL)
2539 break;
2540 core_optab = (templates *) xmalloc (sizeof (templates));
2541 core_optab->start = optab;
2542 }
2543 }
2544 }
2545
47926f60 2546 /* Initialize reg_hash hash table. */
252b5132
RH		 2547 reg_hash = hash_new ();
2548 {
29b0f896 2549 const reg_entry *regtab;
c3fe08fa 2550 unsigned int regtab_size = i386_regtab_size;
252b5132 2551
c3fe08fa 2552 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2553 {
5a49b8ac 2554 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2555 if (hash_err)
b37df7c4 2556 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2557 regtab->reg_name,
2558 hash_err);
252b5132
RH		 2559 }
2560 }
2561
47926f60 2562 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2563 {
29b0f896
AM		 2564 int c;
2565 char *p;
252b5132
RH		 2566
2567 for (c = 0; c < 256; c++)
2568 {
3882b010 2569 if (ISDIGIT (c))
252b5132
RH		 2570 {
2571 digit_chars[c] = c;
2572 mnemonic_chars[c] = c;
2573 register_chars[c] = c;
2574 operand_chars[c] = c;
2575 }
3882b010 2576 else if (ISLOWER (c))
252b5132
RH		 2577 {
2578 mnemonic_chars[c] = c;
2579 register_chars[c] = c;
2580 operand_chars[c] = c;
2581 }
3882b010 2582 else if (ISUPPER (c))
252b5132 2583 {
3882b010 2584 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2585 register_chars[c] = mnemonic_chars[c];
2586 operand_chars[c] = c;
2587 }
43234a1e
L		 2588 else if (c == '{' || c == '}')
2589 operand_chars[c] = c;
252b5132 2590
3882b010 2591 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2592 identifier_chars[c] = c;
2593 else if (c >= 128)
2594 {
2595 identifier_chars[c] = c;
2596 operand_chars[c] = c;
2597 }
2598 }
2599
2600#ifdef LEX_AT
2601 identifier_chars['@'] = '@';
32137342
NC		 2602#endif
2603#ifdef LEX_QM
2604 identifier_chars['?'] = '?';
2605 operand_chars['?'] = '?';
252b5132 2606#endif
252b5132 2607 digit_chars['-'] = '-';
c0f3af97 2608 mnemonic_chars['_'] = '_';
791fe849 2609 mnemonic_chars['-'] = '-';
0003779b 2610 mnemonic_chars['.'] = '.';
252b5132
RH		 2611 identifier_chars['_'] = '_';
2612 identifier_chars['.'] = '.';
2613
2614 for (p = operand_special_chars; *p != '\0'; p++)
2615 operand_chars[(unsigned char) *p] = *p;
2616 }
2617
a4447b93
RH		 2618 if (flag_code == CODE_64BIT)
2619 {
ca19b261
KT		 2620#if defined (OBJ_COFF) && defined (TE_PE)
2621 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2622 ? 32 : 16);
2623#else
a4447b93 2624 x86_dwarf2_return_column = 16;
ca19b261 2625#endif
61ff971f 2626 x86_cie_data_alignment = -8;
a4447b93
RH		 2627 }
2628 else
2629 {
2630 x86_dwarf2_return_column = 8;
2631 x86_cie_data_alignment = -4;
2632 }
252b5132
RH		 2633}
2634
2635void
e3bb37b5 2636i386_print_statistics (FILE *file)
252b5132
RH		 2637{
2638 hash_print_statistics (file, "i386 opcode", op_hash);
2639 hash_print_statistics (file, "i386 register", reg_hash);
2640}
2641\f
252b5132
RH		 2642#ifdef DEBUG386
2643
ce8a8b2f 2644/* Debugging routines for md_assemble. */
d3ce72d0 2645static void pte (insn_template *);
40fb9820 2646static void pt (i386_operand_type);
e3bb37b5
L		 2647static void pe (expressionS *);
2648static void ps (symbolS *);
252b5132
RH		 2649
2650static void
e3bb37b5 2651pi (char *line, i386_insn *x)
252b5132 2652{
09137c09 2653 unsigned int j;
252b5132
RH		 2654
2655 fprintf (stdout, "%s: template ", line);
2656 pte (&x->tm);
09f131f2
JH		 2657 fprintf (stdout, " address: base %s index %s scale %x\n",
2658 x->base_reg ? x->base_reg->reg_name : "none",
2659 x->index_reg ? x->index_reg->reg_name : "none",
2660 x->log2_scale_factor);
2661 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2662 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2663 fprintf (stdout, " sib: base %x index %x scale %x\n",
2664 x->sib.base, x->sib.index, x->sib.scale);
2665 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2666 (x->rex & REX_W) != 0,
2667 (x->rex & REX_R) != 0,
2668 (x->rex & REX_X) != 0,
2669 (x->rex & REX_B) != 0);
09137c09 2670 for (j = 0; j < x->operands; j++)
252b5132 2671 {
09137c09
SP		 2672 fprintf (stdout, " #%d: ", j + 1);
2673 pt (x->types[j]);
252b5132 2674 fprintf (stdout, "\n");
09137c09
SP		 2675 if (x->types[j].bitfield.reg8
2676 || x->types[j].bitfield.reg16
2677 || x->types[j].bitfield.reg32
2678 || x->types[j].bitfield.reg64
2679 || x->types[j].bitfield.regmmx
2680 || x->types[j].bitfield.regxmm
2681 || x->types[j].bitfield.regymm
43234a1e 2682 || x->types[j].bitfield.regzmm
09137c09
SP		 2683 || x->types[j].bitfield.sreg2
2684 || x->types[j].bitfield.sreg3
2685 || x->types[j].bitfield.control
2686 || x->types[j].bitfield.debug
2687 || x->types[j].bitfield.test)
2688 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2689 if (operand_type_check (x->types[j], imm))
2690 pe (x->op[j].imms);
2691 if (operand_type_check (x->types[j], disp))
2692 pe (x->op[j].disps);
252b5132
RH		 2693 }
2694}
2695
2696static void
d3ce72d0 2697pte (insn_template *t)
252b5132 2698{
09137c09 2699 unsigned int j;
252b5132 2700 fprintf (stdout, " %d operands ", t->operands);
47926f60 2701 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2702 if (t->extension_opcode != None)
2703 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2704 if (t->opcode_modifier.d)
252b5132 2705 fprintf (stdout, "D");
40fb9820 2706 if (t->opcode_modifier.w)
252b5132
RH		 2707 fprintf (stdout, "W");
2708 fprintf (stdout, "\n");
09137c09 2709 for (j = 0; j < t->operands; j++)
252b5132 2710 {
09137c09
SP		 2711 fprintf (stdout, " #%d type ", j + 1);
2712 pt (t->operand_types[j]);
252b5132
RH		 2713 fprintf (stdout, "\n");
2714 }
2715}
2716
2717static void
e3bb37b5 2718pe (expressionS *e)
252b5132 2719{
24eab124 2720 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2721 fprintf (stdout, " add_number %ld (%lx)\n",
2722 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2723 if (e->X_add_symbol)
2724 {
2725 fprintf (stdout, " add_symbol ");
2726 ps (e->X_add_symbol);
2727 fprintf (stdout, "\n");
2728 }
2729 if (e->X_op_symbol)
2730 {
2731 fprintf (stdout, " op_symbol ");
2732 ps (e->X_op_symbol);
2733 fprintf (stdout, "\n");
2734 }
2735}
2736
2737static void
e3bb37b5 2738ps (symbolS *s)
252b5132
RH		 2739{
2740 fprintf (stdout, "%s type %s%s",
2741 S_GET_NAME (s),
2742 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2743 segment_name (S_GET_SEGMENT (s)));
2744}
2745
7b81dfbb 2746static struct type_name
252b5132 2747 {
40fb9820
L		 2748 i386_operand_type mask;
2749 const char *name;
252b5132 2750 }
7b81dfbb 2751const type_names[] =
252b5132 2752{
40fb9820
L		 2753 { OPERAND_TYPE_REG8, "r8" },
2754 { OPERAND_TYPE_REG16, "r16" },
2755 { OPERAND_TYPE_REG32, "r32" },
2756 { OPERAND_TYPE_REG64, "r64" },
2757 { OPERAND_TYPE_IMM8, "i8" },
2758 { OPERAND_TYPE_IMM8, "i8s" },
2759 { OPERAND_TYPE_IMM16, "i16" },
2760 { OPERAND_TYPE_IMM32, "i32" },
2761 { OPERAND_TYPE_IMM32S, "i32s" },
2762 { OPERAND_TYPE_IMM64, "i64" },
2763 { OPERAND_TYPE_IMM1, "i1" },
2764 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2765 { OPERAND_TYPE_DISP8, "d8" },
2766 { OPERAND_TYPE_DISP16, "d16" },
2767 { OPERAND_TYPE_DISP32, "d32" },
2768 { OPERAND_TYPE_DISP32S, "d32s" },
2769 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2770 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2771 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2772 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2773 { OPERAND_TYPE_CONTROL, "control reg" },
2774 { OPERAND_TYPE_TEST, "test reg" },
2775 { OPERAND_TYPE_DEBUG, "debug reg" },
2776 { OPERAND_TYPE_FLOATREG, "FReg" },
2777 { OPERAND_TYPE_FLOATACC, "FAcc" },
2778 { OPERAND_TYPE_SREG2, "SReg2" },
2779 { OPERAND_TYPE_SREG3, "SReg3" },
2780 { OPERAND_TYPE_ACC, "Acc" },
2781 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2782 { OPERAND_TYPE_REGMMX, "rMMX" },
2783 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2784 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2785 { OPERAND_TYPE_REGZMM, "rZMM" },
2786 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2787 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2788};
2789
2790static void
40fb9820 2791pt (i386_operand_type t)
252b5132 2792{
40fb9820 2793 unsigned int j;
c6fb90c8 2794 i386_operand_type a;
252b5132 2795
40fb9820 2796 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2797 {
2798 a = operand_type_and (t, type_names[j].mask);
0349dc08 2799 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2800 fprintf (stdout, "%s, ", type_names[j].name);
2801 }
252b5132
RH		 2802 fflush (stdout);
2803}
2804
2805#endif /* DEBUG386 */
2806\f
252b5132 2807static bfd_reloc_code_real_type
3956db08 2808reloc (unsigned int size,
64e74474
AM		 2809 int pcrel,
2810 int sign,
c3320543 2811 int bnd_prefix,
64e74474 2812 bfd_reloc_code_real_type other)
252b5132 2813{
47926f60 2814 if (other != NO_RELOC)
3956db08 2815 {
91d6fa6a 2816 reloc_howto_type *rel;
3956db08
JB		 2817
2818 if (size == 8)
2819 switch (other)
2820 {
64e74474
AM		 2821 case BFD_RELOC_X86_64_GOT32:
2822 return BFD_RELOC_X86_64_GOT64;
2823 break;
2824 case BFD_RELOC_X86_64_PLTOFF64:
2825 return BFD_RELOC_X86_64_PLTOFF64;
2826 break;
2827 case BFD_RELOC_X86_64_GOTPC32:
2828 other = BFD_RELOC_X86_64_GOTPC64;
2829 break;
2830 case BFD_RELOC_X86_64_GOTPCREL:
2831 other = BFD_RELOC_X86_64_GOTPCREL64;
2832 break;
2833 case BFD_RELOC_X86_64_TPOFF32:
2834 other = BFD_RELOC_X86_64_TPOFF64;
2835 break;
2836 case BFD_RELOC_X86_64_DTPOFF32:
2837 other = BFD_RELOC_X86_64_DTPOFF64;
2838 break;
2839 default:
2840 break;
3956db08 2841 }
e05278af 2842
8ce3d284 2843#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2844 if (other == BFD_RELOC_SIZE32)
2845 {
2846 if (size == 8)
2847 return BFD_RELOC_SIZE64;
2848 if (pcrel)
2849 as_bad (_("there are no pc-relative size relocations"));
2850 }
8ce3d284 2851#endif
8fd4256d 2852
e05278af 2853 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2854 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2855 sign = -1;
2856
91d6fa6a
NC		 2857 rel = bfd_reloc_type_lookup (stdoutput, other);
2858 if (!rel)
3956db08 2859 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2860 else if (size != bfd_get_reloc_size (rel))
3956db08 2861 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2862 bfd_get_reloc_size (rel),
3956db08 2863 size);
91d6fa6a 2864 else if (pcrel && !rel->pc_relative)
3956db08 2865 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2866 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2867 && !sign)
91d6fa6a 2868 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2869 && sign > 0))
3956db08
JB		 2870 as_bad (_("relocated field and relocation type differ in signedness"));
2871 else
2872 return other;
2873 return NO_RELOC;
2874 }
252b5132
RH		 2875
2876 if (pcrel)
2877 {
3e73aa7c 2878 if (!sign)
3956db08 2879 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2880 switch (size)
2881 {
2882 case 1: return BFD_RELOC_8_PCREL;
2883 case 2: return BFD_RELOC_16_PCREL;
c3320543
L		 2884 case 4: return (bnd_prefix && object_64bit
2885 ? BFD_RELOC_X86_64_PC32_BND
2886 : BFD_RELOC_32_PCREL);
d6ab8113 2887 case 8: return BFD_RELOC_64_PCREL;
252b5132 2888 }
3956db08 2889 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2890 }
2891 else
2892 {
3956db08 2893 if (sign > 0)
e5cb08ac 2894 switch (size)
3e73aa7c
JH		 2895 {
2896 case 4: return BFD_RELOC_X86_64_32S;
2897 }
2898 else
2899 switch (size)
2900 {
2901 case 1: return BFD_RELOC_8;
2902 case 2: return BFD_RELOC_16;
2903 case 4: return BFD_RELOC_32;
2904 case 8: return BFD_RELOC_64;
2905 }
3956db08
JB		 2906 as_bad (_("cannot do %s %u byte relocation"),
2907 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2908 }
2909
0cc9e1d3 2910 return NO_RELOC;
252b5132
RH		 2911}
2912
47926f60
KH		 2913/* Here we decide which fixups can be adjusted to make them relative to
2914 the beginning of the section instead of the symbol. Basically we need
2915 to make sure that the dynamic relocations are done correctly, so in
2916 some cases we force the original symbol to be used. */
2917
252b5132 2918int
e3bb37b5 2919tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2920{
6d249963 2921#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2922 if (!IS_ELF)
31312f95
AM		 2923 return 1;
2924
a161fe53
AM		 2925 /* Don't adjust pc-relative references to merge sections in 64-bit
2926 mode. */
2927 if (use_rela_relocations
2928 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2929 && fixP->fx_pcrel)
252b5132 2930 return 0;
31312f95 2931
8d01d9a9
AJ		 2932 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2933 and changed later by validate_fix. */
2934 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2935 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2936 return 0;
2937
8fd4256d
L		 2938 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2939 for size relocations. */
2940 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2941 || fixP->fx_r_type == BFD_RELOC_SIZE64
2942 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2943 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2944 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2945 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2946 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2947 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2948 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2949 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2950 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2951 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2952 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2953 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2954 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2955 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2956 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2957 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2958 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2959 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2960 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2961 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2962 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2963 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2964 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2965 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2966 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2967 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2968 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2969 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2970 return 0;
31312f95 2971#endif
252b5132
RH		 2972 return 1;
2973}
252b5132 2974
b4cac588 2975static int
e3bb37b5 2976intel_float_operand (const char *mnemonic)
252b5132 2977{
9306ca4a
JB		 2978 /* Note that the value returned is meaningful only for opcodes with (memory)
2979 operands, hence the code here is free to improperly handle opcodes that
2980 have no operands (for better performance and smaller code). */
2981
2982 if (mnemonic[0] != 'f')
2983 return 0; /* non-math */
2984
2985 switch (mnemonic[1])
2986 {
2987 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2988 the fs segment override prefix not currently handled because no
2989 call path can make opcodes without operands get here */
2990 case 'i':
2991 return 2 /* integer op */;
2992 case 'l':
2993 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2994 return 3; /* fldcw/fldenv */
2995 break;
2996 case 'n':
2997 if (mnemonic[2] != 'o' /* fnop */)
2998 return 3; /* non-waiting control op */
2999 break;
3000 case 'r':
3001 if (mnemonic[2] == 's')
3002 return 3; /* frstor/frstpm */
3003 break;
3004 case 's':
3005 if (mnemonic[2] == 'a')
3006 return 3; /* fsave */
3007 if (mnemonic[2] == 't')
3008 {
3009 switch (mnemonic[3])
3010 {
3011 case 'c': /* fstcw */
3012 case 'd': /* fstdw */
3013 case 'e': /* fstenv */
3014 case 's': /* fsts[gw] */
3015 return 3;
3016 }
3017 }
3018 break;
3019 case 'x':
3020 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3021 return 0; /* fxsave/fxrstor are not really math ops */
3022 break;
3023 }
252b5132 3024
9306ca4a 3025 return 1;
252b5132
RH		 3026}
3027
c0f3af97
L		 3028/* Build the VEX prefix. */
3029
3030static void
d3ce72d0 3031build_vex_prefix (const insn_template *t)
c0f3af97
L		 3032{
3033 unsigned int register_specifier;
3034 unsigned int implied_prefix;
3035 unsigned int vector_length;
3036
3037 /* Check register specifier. */
3038 if (i.vex.register_specifier)
43234a1e
L		 3039 {
3040 register_specifier =
3041 ~register_number (i.vex.register_specifier) & 0xf;
3042 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3043 }
c0f3af97
L		 3044 else
3045 register_specifier = 0xf;
3046
fa99fab2
L		 3047 /* Use 2-byte VEX prefix by swappping destination and source
3048 operand. */
3049 if (!i.swap_operand
3050 && i.operands == i.reg_operands
7f399153 3051 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3052 && i.tm.opcode_modifier.s
3053 && i.rex == REX_B)
3054 {
3055 unsigned int xchg = i.operands - 1;
3056 union i386_op temp_op;
3057 i386_operand_type temp_type;
3058
3059 temp_type = i.types[xchg];
3060 i.types[xchg] = i.types[0];
3061 i.types[0] = temp_type;
3062 temp_op = i.op[xchg];
3063 i.op[xchg] = i.op[0];
3064 i.op[0] = temp_op;
3065
9c2799c2 3066 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3067
3068 i.rex = REX_R;
3069 xchg = i.rm.regmem;
3070 i.rm.regmem = i.rm.reg;
3071 i.rm.reg = xchg;
3072
3073 /* Use the next insn. */
3074 i.tm = t[1];
3075 }
3076
539f890d
L		 3077 if (i.tm.opcode_modifier.vex == VEXScalar)
3078 vector_length = avxscalar;
3079 else
3080 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3081
3082 switch ((i.tm.base_opcode >> 8) & 0xff)
3083 {
3084 case 0:
3085 implied_prefix = 0;
3086 break;
3087 case DATA_PREFIX_OPCODE:
3088 implied_prefix = 1;
3089 break;
3090 case REPE_PREFIX_OPCODE:
3091 implied_prefix = 2;
3092 break;
3093 case REPNE_PREFIX_OPCODE:
3094 implied_prefix = 3;
3095 break;
3096 default:
3097 abort ();
3098 }
3099
3100 /* Use 2-byte VEX prefix if possible. */
7f399153 3101 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3102 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3103 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3104 {
3105 /* 2-byte VEX prefix. */
3106 unsigned int r;
3107
3108 i.vex.length = 2;
3109 i.vex.bytes[0] = 0xc5;
3110
3111 /* Check the REX.R bit. */
3112 r = (i.rex & REX_R) ? 0 : 1;
3113 i.vex.bytes[1] = (r << 7
3114 | register_specifier << 3
3115 | vector_length << 2
3116 | implied_prefix);
3117 }
3118 else
3119 {
3120 /* 3-byte VEX prefix. */
3121 unsigned int m, w;
3122
f88c9eb0 3123 i.vex.length = 3;
f88c9eb0 3124
7f399153 3125 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3126 {
7f399153
L		 3127 case VEX0F:
3128 m = 0x1;
80de6e00 3129 i.vex.bytes[0] = 0xc4;
7f399153
L		 3130 break;
3131 case VEX0F38:
3132 m = 0x2;
80de6e00 3133 i.vex.bytes[0] = 0xc4;
7f399153
L		 3134 break;
3135 case VEX0F3A:
3136 m = 0x3;
80de6e00 3137 i.vex.bytes[0] = 0xc4;
7f399153
L		 3138 break;
3139 case XOP08:
5dd85c99
SP		 3140 m = 0x8;
3141 i.vex.bytes[0] = 0x8f;
7f399153
L		 3142 break;
3143 case XOP09:
f88c9eb0
SP		 3144 m = 0x9;
3145 i.vex.bytes[0] = 0x8f;
7f399153
L		 3146 break;
3147 case XOP0A:
f88c9eb0
SP		 3148 m = 0xa;
3149 i.vex.bytes[0] = 0x8f;
7f399153
L		 3150 break;
3151 default:
3152 abort ();
f88c9eb0 3153 }
c0f3af97 3154
c0f3af97
L		 3155 /* The high 3 bits of the second VEX byte are 1's compliment
3156 of RXB bits from REX. */
3157 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3158
3159 /* Check the REX.W bit. */
3160 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 3161 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 3162 {
3163 if (w)
3164 abort ();
3165
1ef99a7b 3166 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 3167 w = 1;
3168 }
3169
3170 i.vex.bytes[2] = (w << 7
3171 | register_specifier << 3
3172 | vector_length << 2
3173 | implied_prefix);
3174 }
3175}
3176
43234a1e
L		 3177/* Build the EVEX prefix. */
3178
3179static void
3180build_evex_prefix (void)
3181{
3182 unsigned int register_specifier;
3183 unsigned int implied_prefix;
3184 unsigned int m, w;
3185 rex_byte vrex_used = 0;
3186
3187 /* Check register specifier. */
3188 if (i.vex.register_specifier)
3189 {
3190 gas_assert ((i.vrex & REX_X) == 0);
3191
3192 register_specifier = i.vex.register_specifier->reg_num;
3193 if ((i.vex.register_specifier->reg_flags & RegRex))
3194 register_specifier += 8;
3195 /* The upper 16 registers are encoded in the fourth byte of the
3196 EVEX prefix. */
3197 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3198 i.vex.bytes[3] = 0x8;
3199 register_specifier = ~register_specifier & 0xf;
3200 }
3201 else
3202 {
3203 register_specifier = 0xf;
3204
3205 /* Encode upper 16 vector index register in the fourth byte of
3206 the EVEX prefix. */
3207 if (!(i.vrex & REX_X))
3208 i.vex.bytes[3] = 0x8;
3209 else
3210 vrex_used |= REX_X;
3211 }
3212
3213 switch ((i.tm.base_opcode >> 8) & 0xff)
3214 {
3215 case 0:
3216 implied_prefix = 0;
3217 break;
3218 case DATA_PREFIX_OPCODE:
3219 implied_prefix = 1;
3220 break;
3221 case REPE_PREFIX_OPCODE:
3222 implied_prefix = 2;
3223 break;
3224 case REPNE_PREFIX_OPCODE:
3225 implied_prefix = 3;
3226 break;
3227 default:
3228 abort ();
3229 }
3230
3231 /* 4 byte EVEX prefix. */
3232 i.vex.length = 4;
3233 i.vex.bytes[0] = 0x62;
3234
3235 /* mmmm bits. */
3236 switch (i.tm.opcode_modifier.vexopcode)
3237 {
3238 case VEX0F:
3239 m = 1;
3240 break;
3241 case VEX0F38:
3242 m = 2;
3243 break;
3244 case VEX0F3A:
3245 m = 3;
3246 break;
3247 default:
3248 abort ();
3249 break;
3250 }
3251
3252 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3253 bits from REX. */
3254 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3255
3256 /* The fifth bit of the second EVEX byte is 1's compliment of the
3257 REX_R bit in VREX. */
3258 if (!(i.vrex & REX_R))
3259 i.vex.bytes[1] |= 0x10;
3260 else
3261 vrex_used |= REX_R;
3262
3263 if ((i.reg_operands + i.imm_operands) == i.operands)
3264 {
3265 /* When all operands are registers, the REX_X bit in REX is not
3266 used. We reuse it to encode the upper 16 registers, which is
3267 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3268 as 1's compliment. */
3269 if ((i.vrex & REX_B))
3270 {
3271 vrex_used |= REX_B;
3272 i.vex.bytes[1] &= ~0x40;
3273 }
3274 }
3275
3276 /* EVEX instructions shouldn't need the REX prefix. */
3277 i.vrex &= ~vrex_used;
3278 gas_assert (i.vrex == 0);
3279
3280 /* Check the REX.W bit. */
3281 w = (i.rex & REX_W) ? 1 : 0;
3282 if (i.tm.opcode_modifier.vexw)
3283 {
3284 if (i.tm.opcode_modifier.vexw == VEXW1)
3285 w = 1;
3286 }
3287 /* If w is not set it means we are dealing with WIG instruction. */
3288 else if (!w)
3289 {
3290 if (evexwig == evexw1)
3291 w = 1;
3292 }
3293
3294 /* Encode the U bit. */
3295 implied_prefix |= 0x4;
3296
3297 /* The third byte of the EVEX prefix. */
3298 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3299
3300 /* The fourth byte of the EVEX prefix. */
3301 /* The zeroing-masking bit. */
3302 if (i.mask && i.mask->zeroing)
3303 i.vex.bytes[3] |= 0x80;
3304
3305 /* Don't always set the broadcast bit if there is no RC. */
3306 if (!i.rounding)
3307 {
3308 /* Encode the vector length. */
3309 unsigned int vec_length;
3310
3311 switch (i.tm.opcode_modifier.evex)
3312 {
3313 case EVEXLIG: /* LL' is ignored */
3314 vec_length = evexlig << 5;
3315 break;
3316 case EVEX128:
3317 vec_length = 0 << 5;
3318 break;
3319 case EVEX256:
3320 vec_length = 1 << 5;
3321 break;
3322 case EVEX512:
3323 vec_length = 2 << 5;
3324 break;
3325 default:
3326 abort ();
3327 break;
3328 }
3329 i.vex.bytes[3] |= vec_length;
3330 /* Encode the broadcast bit. */
3331 if (i.broadcast)
3332 i.vex.bytes[3] |= 0x10;
3333 }
3334 else
3335 {
3336 if (i.rounding->type != saeonly)
3337 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3338 else
3339 i.vex.bytes[3] |= 0x10;
3340 }
3341
3342 if (i.mask && i.mask->mask)
3343 i.vex.bytes[3] |= i.mask->mask->reg_num;
3344}
3345
65da13b5
L		 3346static void
3347process_immext (void)
3348{
3349 expressionS *exp;
3350
4c692bc7
JB		 3351 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3352 && i.operands > 0)
65da13b5 3353 {
4c692bc7
JB		 3354 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3355 with an opcode suffix which is coded in the same place as an
3356 8-bit immediate field would be.
3357 Here we check those operands and remove them afterwards. */
65da13b5
L		 3358 unsigned int x;
3359
3360 for (x = 0; x < i.operands; x++)
4c692bc7 3361 if (register_number (i.op[x].regs) != x)
65da13b5 3362 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3363 register_prefix, i.op[x].regs->reg_name, x + 1,
3364 i.tm.name);
3365
3366 i.operands = 0;
65da13b5
L		 3367 }
3368
c0f3af97 3369 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3370 which is coded in the same place as an 8-bit immediate field
3371 would be. Here we fake an 8-bit immediate operand from the
3372 opcode suffix stored in tm.extension_opcode.
3373
c1e679ec 3374 AVX instructions also use this encoding, for some of
c0f3af97 3375 3 argument instructions. */
65da13b5 3376
43234a1e 3377 gas_assert (i.imm_operands <= 1
7ab9ffdd 3378 && (i.operands <= 2
43234a1e
L		 3379 || ((i.tm.opcode_modifier.vex
3380 || i.tm.opcode_modifier.evex)
7ab9ffdd 3381 && i.operands <= 4)));
65da13b5
L		 3382
3383 exp = &im_expressions[i.imm_operands++];
3384 i.op[i.operands].imms = exp;
3385 i.types[i.operands] = imm8;
3386 i.operands++;
3387 exp->X_op = O_constant;
3388 exp->X_add_number = i.tm.extension_opcode;
3389 i.tm.extension_opcode = None;
3390}
3391
42164a71
L		 3392
3393static int
3394check_hle (void)
3395{
3396 switch (i.tm.opcode_modifier.hleprefixok)
3397 {
3398 default:
3399 abort ();
82c2def5 3400 case HLEPrefixNone:
165de32a
L		 3401 as_bad (_("invalid instruction `%s' after `%s'"),
3402 i.tm.name, i.hle_prefix);
42164a71 3403 return 0;
82c2def5 3404 case HLEPrefixLock:
42164a71
L		 3405 if (i.prefix[LOCK_PREFIX])
3406 return 1;
165de32a 3407 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3408 return 0;
82c2def5 3409 case HLEPrefixAny:
42164a71 3410 return 1;
82c2def5 3411 case HLEPrefixRelease:
42164a71
L		 3412 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3413 {
3414 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3415 i.tm.name);
3416 return 0;
3417 }
3418 if (i.mem_operands == 0
3419 || !operand_type_check (i.types[i.operands - 1], anymem))
3420 {
3421 as_bad (_("memory destination needed for instruction `%s'"
3422 " after `xrelease'"), i.tm.name);
3423 return 0;
3424 }
3425 return 1;
3426 }
3427}
3428
252b5132
RH		 3429/* This is the guts of the machine-dependent assembler. LINE points to a
3430 machine dependent instruction. This function is supposed to emit
3431 the frags/bytes it assembles to. */
3432
3433void
65da13b5 3434md_assemble (char *line)
252b5132 3435{
40fb9820 3436 unsigned int j;
252b5132 3437 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3438 const insn_template *t;
252b5132 3439
47926f60 3440 /* Initialize globals. */
252b5132
RH		 3441 memset (&i, '\0', sizeof (i));
3442 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3443 i.reloc[j] = NO_RELOC;
252b5132
RH		 3444 memset (disp_expressions, '\0', sizeof (disp_expressions));
3445 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3446 save_stack_p = save_stack;
252b5132
RH		 3447
3448 /* First parse an instruction mnemonic & call i386_operand for the operands.
3449 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3450 start of a (possibly prefixed) mnemonic. */
252b5132 3451
29b0f896
AM		 3452 line = parse_insn (line, mnemonic);
3453 if (line == NULL)
3454 return;
252b5132 3455
29b0f896 3456 line = parse_operands (line, mnemonic);
ee86248c 3457 this_operand = -1;
29b0f896
AM		 3458 if (line == NULL)
3459 return;
252b5132 3460
29b0f896
AM		 3461 /* Now we've parsed the mnemonic into a set of templates, and have the
3462 operands at hand. */
3463
3464 /* All intel opcodes have reversed operands except for "bound" and
3465 "enter". We also don't reverse intersegment "jmp" and "call"
3466 instructions with 2 immediate operands so that the immediate segment
050dfa73 3467 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3468 if (intel_syntax
3469 && i.operands > 1
29b0f896 3470 && (strcmp (mnemonic, "bound") != 0)
30123838 3471 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3472 && !(operand_type_check (i.types[0], imm)
3473 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3474 swap_operands ();
3475
ec56d5c0
JB		 3476 /* The order of the immediates should be reversed
3477 for 2 immediates extrq and insertq instructions */
3478 if (i.imm_operands == 2
3479 && (strcmp (mnemonic, "extrq") == 0
3480 || strcmp (mnemonic, "insertq") == 0))
3481 swap_2_operands (0, 1);
3482
29b0f896
AM		 3483 if (i.imm_operands)
3484 optimize_imm ();
3485
b300c311
L		 3486 /* Don't optimize displacement for movabs since it only takes 64bit
3487 displacement. */
3488 if (i.disp_operands
a501d77e 3489 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3490 && (flag_code != CODE_64BIT
3491 || strcmp (mnemonic, "movabs") != 0))
3492 optimize_disp ();
29b0f896
AM		 3493
3494 /* Next, we find a template that matches the given insn,
3495 making sure the overlap of the given operands types is consistent
3496 with the template operand types. */
252b5132 3497
fa99fab2 3498 if (!(t = match_template ()))
29b0f896 3499 return;
252b5132 3500
7bab8ab5 3501 if (sse_check != check_none
81f8a913 3502 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3503 && (i.tm.cpu_flags.bitfield.cpusse
3504 || i.tm.cpu_flags.bitfield.cpusse2
3505 || i.tm.cpu_flags.bitfield.cpusse3
3506 || i.tm.cpu_flags.bitfield.cpussse3
3507 || i.tm.cpu_flags.bitfield.cpusse4_1
3508 || i.tm.cpu_flags.bitfield.cpusse4_2))
3509 {
7bab8ab5 3510 (sse_check == check_warning
daf50ae7
L		 3511 ? as_warn
3512 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3513 }
3514
321fd21e
L		 3515 /* Zap movzx and movsx suffix. The suffix has been set from
3516 "word ptr" or "byte ptr" on the source operand in Intel syntax
3517 or extracted from mnemonic in AT&T syntax. But we'll use
3518 the destination register to choose the suffix for encoding. */
3519 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3520 {
321fd21e
L		 3521 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3522 there is no suffix, the default will be byte extension. */
3523 if (i.reg_operands != 2
3524 && !i.suffix
7ab9ffdd 3525 && intel_syntax)
321fd21e
L		 3526 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3527
3528 i.suffix = 0;
cd61ebfe 3529 }
24eab124 3530
40fb9820 3531 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3532 if (!add_prefix (FWAIT_OPCODE))
3533 return;
252b5132 3534
d5de92cf
L		 3535 /* Check if REP prefix is OK. */
3536 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3537 {
3538 as_bad (_("invalid instruction `%s' after `%s'"),
3539 i.tm.name, i.rep_prefix);
3540 return;
3541 }
3542
c1ba0266
L		 3543 /* Check for lock without a lockable instruction. Destination operand
3544 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3545 if (i.prefix[LOCK_PREFIX]
3546 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3547 || i.mem_operands == 0
3548 || (i.tm.base_opcode != 0x86
3549 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3550 {
3551 as_bad (_("expecting lockable instruction after `lock'"));
3552 return;
3553 }
3554
42164a71 3555 /* Check if HLE prefix is OK. */
165de32a 3556 if (i.hle_prefix && !check_hle ())
42164a71
L		 3557 return;
3558
7e8b059b
L		 3559 /* Check BND prefix. */
3560 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3561 as_bad (_("expecting valid branch instruction after `bnd'"));
3562
3563 if (i.tm.cpu_flags.bitfield.cpumpx
3564 && flag_code == CODE_64BIT
3565 && i.prefix[ADDR_PREFIX])
3566 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3567
3568 /* Insert BND prefix. */
3569 if (add_bnd_prefix
3570 && i.tm.opcode_modifier.bndprefixok
3571 && !i.prefix[BND_PREFIX])
3572 add_prefix (BND_PREFIX_OPCODE);
3573
29b0f896 3574 /* Check string instruction segment overrides. */
40fb9820 3575 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3576 {
3577 if (!check_string ())
5dd0794d 3578 return;
fc0763e6 3579 i.disp_operands = 0;
29b0f896 3580 }
5dd0794d 3581
29b0f896
AM		 3582 if (!process_suffix ())
3583 return;
e413e4e9 3584
bc0844ae
L		 3585 /* Update operand types. */
3586 for (j = 0; j < i.operands; j++)
3587 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3588
29b0f896
AM		 3589 /* Make still unresolved immediate matches conform to size of immediate
3590 given in i.suffix. */
3591 if (!finalize_imm ())
3592 return;
252b5132 3593
40fb9820 3594 if (i.types[0].bitfield.imm1)
29b0f896 3595 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3596
9afe6eb8
L		 3597 /* We only need to check those implicit registers for instructions
3598 with 3 operands or less. */
3599 if (i.operands <= 3)
3600 for (j = 0; j < i.operands; j++)
3601 if (i.types[j].bitfield.inoutportreg
3602 || i.types[j].bitfield.shiftcount
3603 || i.types[j].bitfield.acc
3604 || i.types[j].bitfield.floatacc)
3605 i.reg_operands--;
40fb9820 3606
c0f3af97
L		 3607 /* ImmExt should be processed after SSE2AVX. */
3608 if (!i.tm.opcode_modifier.sse2avx
3609 && i.tm.opcode_modifier.immext)
65da13b5 3610 process_immext ();
252b5132 3611
29b0f896
AM		 3612 /* For insns with operands there are more diddles to do to the opcode. */
3613 if (i.operands)
3614 {
3615 if (!process_operands ())
3616 return;
3617 }
40fb9820 3618 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3619 {
3620 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3621 as_warn (_("translating to `%sp'"), i.tm.name);
3622 }
252b5132 3623
c0f3af97 3624 if (i.tm.opcode_modifier.vex)
fa99fab2 3625 build_vex_prefix (t);
c0f3af97 3626
43234a1e
L		 3627 if (i.tm.opcode_modifier.evex)
3628 build_evex_prefix ();
3629
5dd85c99
SP		 3630 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3631 instructions may define INT_OPCODE as well, so avoid this corner
3632 case for those instructions that use MODRM. */
3633 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3634 && !i.tm.opcode_modifier.modrm
3635 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3636 {
3637 i.tm.base_opcode = INT3_OPCODE;
3638 i.imm_operands = 0;
3639 }
252b5132 3640
40fb9820
L		 3641 if ((i.tm.opcode_modifier.jump
3642 || i.tm.opcode_modifier.jumpbyte
3643 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3644 && i.op[0].disps->X_op == O_constant)
3645 {
3646 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3647 the absolute address given by the constant. Since ix86 jumps and
3648 calls are pc relative, we need to generate a reloc. */
3649 i.op[0].disps->X_add_symbol = &abs_symbol;
3650 i.op[0].disps->X_op = O_symbol;
3651 }
252b5132 3652
40fb9820 3653 if (i.tm.opcode_modifier.rex64)
161a04f6 3654 i.rex |= REX_W;
252b5132 3655
29b0f896
AM		 3656 /* For 8 bit registers we need an empty rex prefix. Also if the
3657 instruction already has a prefix, we need to convert old
3658 registers to new ones. */
773f551c 3659
40fb9820 3660 if ((i.types[0].bitfield.reg8
29b0f896 3661 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3662 || (i.types[1].bitfield.reg8
29b0f896 3663 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3664 || ((i.types[0].bitfield.reg8
3665 || i.types[1].bitfield.reg8)
29b0f896
AM		 3666 && i.rex != 0))
3667 {
3668 int x;
726c5dcd 3669
29b0f896
AM		 3670 i.rex |= REX_OPCODE;
3671 for (x = 0; x < 2; x++)
3672 {
3673 /* Look for 8 bit operand that uses old registers. */
40fb9820 3674 if (i.types[x].bitfield.reg8
29b0f896 3675 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3676 {
29b0f896
AM		 3677 /* In case it is "hi" register, give up. */
3678 if (i.op[x].regs->reg_num > 3)
a540244d 3679 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3680 "instruction requiring REX prefix."),
a540244d 3681 register_prefix, i.op[x].regs->reg_name);
773f551c 3682
29b0f896
AM		 3683 /* Otherwise it is equivalent to the extended register.
3684 Since the encoding doesn't change this is merely
3685 cosmetic cleanup for debug output. */
3686
3687 i.op[x].regs = i.op[x].regs + 8;
773f551c 3688 }
29b0f896
AM		 3689 }
3690 }
773f551c 3691
7ab9ffdd 3692 if (i.rex != 0)
29b0f896
AM		 3693 add_prefix (REX_OPCODE | i.rex);
3694
3695 /* We are ready to output the insn. */
3696 output_insn ();
3697}
3698
3699static char *
e3bb37b5 3700parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3701{
3702 char *l = line;
3703 char *token_start = l;
3704 char *mnem_p;
5c6af06e 3705 int supported;
d3ce72d0 3706 const insn_template *t;
b6169b20 3707 char *dot_p = NULL;
29b0f896 3708
29b0f896
AM		 3709 while (1)
3710 {
3711 mnem_p = mnemonic;
3712 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3713 {
b6169b20
L		 3714 if (*mnem_p == '.')
3715 dot_p = mnem_p;
29b0f896
AM		 3716 mnem_p++;
3717 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3718 {
29b0f896
AM		 3719 as_bad (_("no such instruction: `%s'"), token_start);
3720 return NULL;
3721 }
3722 l++;
3723 }
3724 if (!is_space_char (*l)
3725 && *l != END_OF_INSN
e44823cf
JB		 3726 && (intel_syntax
3727 || (*l != PREFIX_SEPARATOR
3728 && *l != ',')))
29b0f896
AM		 3729 {
3730 as_bad (_("invalid character %s in mnemonic"),
3731 output_invalid (*l));
3732 return NULL;
3733 }
3734 if (token_start == l)
3735 {
e44823cf 3736 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3737 as_bad (_("expecting prefix; got nothing"));
3738 else
3739 as_bad (_("expecting mnemonic; got nothing"));
3740 return NULL;
3741 }
45288df1 3742
29b0f896 3743 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3744 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3745
29b0f896
AM		 3746 if (*l != END_OF_INSN
3747 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3748 && current_templates
40fb9820 3749 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3750 {
c6fb90c8 3751 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3752 {
3753 as_bad ((flag_code != CODE_64BIT
3754 ? _("`%s' is only supported in 64-bit mode")
3755 : _("`%s' is not supported in 64-bit mode")),
3756 current_templates->start->name);
3757 return NULL;
3758 }
29b0f896
AM		 3759 /* If we are in 16-bit mode, do not allow addr16 or data16.
3760 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3761 if ((current_templates->start->opcode_modifier.size16
3762 || current_templates->start->opcode_modifier.size32)
29b0f896 3763 && flag_code != CODE_64BIT
40fb9820 3764 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3765 ^ (flag_code == CODE_16BIT)))
3766 {
3767 as_bad (_("redundant %s prefix"),
3768 current_templates->start->name);
3769 return NULL;
45288df1 3770 }
29b0f896
AM		 3771 /* Add prefix, checking for repeated prefixes. */
3772 switch (add_prefix (current_templates->start->base_opcode))
3773 {
c32fa91d 3774 case PREFIX_EXIST:
29b0f896 3775 return NULL;
c32fa91d 3776 case PREFIX_REP:
42164a71 3777 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3778 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3779 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3780 i.bnd_prefix = current_templates->start->name;
42164a71 3781 else
d5de92cf 3782 i.rep_prefix = current_templates->start->name;
29b0f896 3783 break;
c32fa91d
L		 3784 default:
3785 break;
29b0f896
AM		 3786 }
3787 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3788 token_start = ++l;
3789 }
3790 else
3791 break;
3792 }
45288df1 3793
30a55f88 3794 if (!current_templates)
b6169b20 3795 {
f8a5c266
L		 3796 /* Check if we should swap operand or force 32bit displacement in
3797 encoding. */
30a55f88
L		 3798 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3799 i.swap_operand = 1;
8d63c93e 3800 else if (mnem_p - 3 == dot_p
a501d77e
L		 3801 && dot_p[1] == 'd'
3802 && dot_p[2] == '8')
3803 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3804 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3805 && dot_p[1] == 'd'
3806 && dot_p[2] == '3'
3807 && dot_p[3] == '2')
a501d77e 3808 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3809 else
3810 goto check_suffix;
3811 mnem_p = dot_p;
3812 *dot_p = '\0';
d3ce72d0 3813 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3814 }
3815
29b0f896
AM		 3816 if (!current_templates)
3817 {
b6169b20 3818check_suffix:
29b0f896
AM		 3819 /* See if we can get a match by trimming off a suffix. */
3820 switch (mnem_p[-1])
3821 {
3822 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3823 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3824 i.suffix = SHORT_MNEM_SUFFIX;
3825 else
29b0f896
AM		 3826 case BYTE_MNEM_SUFFIX:
3827 case QWORD_MNEM_SUFFIX:
3828 i.suffix = mnem_p[-1];
3829 mnem_p[-1] = '\0';
d3ce72d0
NC		 3830 current_templates = (const templates *) hash_find (op_hash,
3831 mnemonic);
29b0f896
AM		 3832 break;
3833 case SHORT_MNEM_SUFFIX:
3834 case LONG_MNEM_SUFFIX:
3835 if (!intel_syntax)
3836 {
3837 i.suffix = mnem_p[-1];
3838 mnem_p[-1] = '\0';
d3ce72d0
NC		 3839 current_templates = (const templates *) hash_find (op_hash,
3840 mnemonic);
29b0f896
AM		 3841 }
3842 break;
252b5132 3843
29b0f896
AM		 3844 /* Intel Syntax. */
3845 case 'd':
3846 if (intel_syntax)
3847 {
9306ca4a 3848 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3849 i.suffix = SHORT_MNEM_SUFFIX;
3850 else
3851 i.suffix = LONG_MNEM_SUFFIX;
3852 mnem_p[-1] = '\0';
d3ce72d0
NC		 3853 current_templates = (const templates *) hash_find (op_hash,
3854 mnemonic);
29b0f896
AM		 3855 }
3856 break;
3857 }
3858 if (!current_templates)
3859 {
3860 as_bad (_("no such instruction: `%s'"), token_start);
3861 return NULL;
3862 }
3863 }
252b5132 3864
40fb9820
L		 3865 if (current_templates->start->opcode_modifier.jump
3866 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3867 {
3868 /* Check for a branch hint. We allow ",pt" and ",pn" for
3869 predict taken and predict not taken respectively.
3870 I'm not sure that branch hints actually do anything on loop
3871 and jcxz insns (JumpByte) for current Pentium4 chips. They
3872 may work in the future and it doesn't hurt to accept them
3873 now. */
3874 if (l[0] == ',' && l[1] == 'p')
3875 {
3876 if (l[2] == 't')
3877 {
3878 if (!add_prefix (DS_PREFIX_OPCODE))
3879 return NULL;
3880 l += 3;
3881 }
3882 else if (l[2] == 'n')
3883 {
3884 if (!add_prefix (CS_PREFIX_OPCODE))
3885 return NULL;
3886 l += 3;
3887 }
3888 }
3889 }
3890 /* Any other comma loses. */
3891 if (*l == ',')
3892 {
3893 as_bad (_("invalid character %s in mnemonic"),
3894 output_invalid (*l));
3895 return NULL;
3896 }
252b5132 3897
29b0f896 3898 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3899 supported = 0;
3900 for (t = current_templates->start; t < current_templates->end; ++t)
3901 {
c0f3af97
L		 3902 supported |= cpu_flags_match (t);
3903 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3904 goto skip;
5c6af06e 3905 }
3629bb00 3906
c0f3af97 3907 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3908 {
3909 as_bad (flag_code == CODE_64BIT
3910 ? _("`%s' is not supported in 64-bit mode")
3911 : _("`%s' is only supported in 64-bit mode"),
3912 current_templates->start->name);
3913 return NULL;
3914 }
c0f3af97 3915 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3916 {
3629bb00 3917 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3918 current_templates->start->name,
41aacd83 3919 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3920 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3921 return NULL;
29b0f896 3922 }
3629bb00
L		 3923
3924skip:
3925 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3926 && (flag_code != CODE_16BIT))
29b0f896
AM		 3927 {
3928 as_warn (_("use .code16 to ensure correct addressing mode"));
3929 }
252b5132 3930
29b0f896
AM		 3931 return l;
3932}
252b5132 3933
29b0f896 3934static char *
e3bb37b5 3935parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3936{
3937 char *token_start;
3138f287 3938
29b0f896
AM		 3939 /* 1 if operand is pending after ','. */
3940 unsigned int expecting_operand = 0;
252b5132 3941
29b0f896
AM		 3942 /* Non-zero if operand parens not balanced. */
3943 unsigned int paren_not_balanced;
3944
3945 while (*l != END_OF_INSN)
3946 {
3947 /* Skip optional white space before operand. */
3948 if (is_space_char (*l))
3949 ++l;
3950 if (!is_operand_char (*l) && *l != END_OF_INSN)
3951 {
3952 as_bad (_("invalid character %s before operand %d"),
3953 output_invalid (*l),
3954 i.operands + 1);
3955 return NULL;
3956 }
3957 token_start = l; /* after white space */
3958 paren_not_balanced = 0;
3959 while (paren_not_balanced || *l != ',')
3960 {
3961 if (*l == END_OF_INSN)
3962 {
3963 if (paren_not_balanced)
3964 {
3965 if (!intel_syntax)
3966 as_bad (_("unbalanced parenthesis in operand %d."),
3967 i.operands + 1);
3968 else
3969 as_bad (_("unbalanced brackets in operand %d."),
3970 i.operands + 1);
3971 return NULL;
3972 }
3973 else
3974 break; /* we are done */
3975 }
3976 else if (!is_operand_char (*l) && !is_space_char (*l))
3977 {
3978 as_bad (_("invalid character %s in operand %d"),
3979 output_invalid (*l),
3980 i.operands + 1);
3981 return NULL;
3982 }
3983 if (!intel_syntax)
3984 {
3985 if (*l == '(')
3986 ++paren_not_balanced;
3987 if (*l == ')')
3988 --paren_not_balanced;
3989 }
3990 else
3991 {
3992 if (*l == '[')
3993 ++paren_not_balanced;
3994 if (*l == ']')
3995 --paren_not_balanced;
3996 }
3997 l++;
3998 }
3999 if (l != token_start)
4000 { /* Yes, we've read in another operand. */
4001 unsigned int operand_ok;
4002 this_operand = i.operands++;
7d5e4556 4003 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4004 if (i.operands > MAX_OPERANDS)
4005 {
4006 as_bad (_("spurious operands; (%d operands/instruction max)"),
4007 MAX_OPERANDS);
4008 return NULL;
4009 }
4010 /* Now parse operand adding info to 'i' as we go along. */
4011 END_STRING_AND_SAVE (l);
4012
4013 if (intel_syntax)
4014 operand_ok =
4015 i386_intel_operand (token_start,
4016 intel_float_operand (mnemonic));
4017 else
a7619375 4018 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4019
4020 RESTORE_END_STRING (l);
4021 if (!operand_ok)
4022 return NULL;
4023 }
4024 else
4025 {
4026 if (expecting_operand)
4027 {
4028 expecting_operand_after_comma:
4029 as_bad (_("expecting operand after ','; got nothing"));
4030 return NULL;
4031 }
4032 if (*l == ',')
4033 {
4034 as_bad (_("expecting operand before ','; got nothing"));
4035 return NULL;
4036 }
4037 }
7f3f1ea2 4038
29b0f896
AM		 4039 /* Now *l must be either ',' or END_OF_INSN. */
4040 if (*l == ',')
4041 {
4042 if (*++l == END_OF_INSN)
4043 {
4044 /* Just skip it, if it's \n complain. */
4045 goto expecting_operand_after_comma;
4046 }
4047 expecting_operand = 1;
4048 }
4049 }
4050 return l;
4051}
7f3f1ea2 4052
050dfa73 4053static void
4d456e3d 4054swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4055{
4056 union i386_op temp_op;
40fb9820 4057 i386_operand_type temp_type;
050dfa73 4058 enum bfd_reloc_code_real temp_reloc;
4eed87de 4059
050dfa73
MM		 4060 temp_type = i.types[xchg2];
4061 i.types[xchg2] = i.types[xchg1];
4062 i.types[xchg1] = temp_type;
4063 temp_op = i.op[xchg2];
4064 i.op[xchg2] = i.op[xchg1];
4065 i.op[xchg1] = temp_op;
4066 temp_reloc = i.reloc[xchg2];
4067 i.reloc[xchg2] = i.reloc[xchg1];
4068 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4069
4070 if (i.mask)
4071 {
4072 if (i.mask->operand == xchg1)
4073 i.mask->operand = xchg2;
4074 else if (i.mask->operand == xchg2)
4075 i.mask->operand = xchg1;
4076 }
4077 if (i.broadcast)
4078 {
4079 if (i.broadcast->operand == xchg1)
4080 i.broadcast->operand = xchg2;
4081 else if (i.broadcast->operand == xchg2)
4082 i.broadcast->operand = xchg1;
4083 }
4084 if (i.rounding)
4085 {
4086 if (i.rounding->operand == xchg1)
4087 i.rounding->operand = xchg2;
4088 else if (i.rounding->operand == xchg2)
4089 i.rounding->operand = xchg1;
4090 }
050dfa73
MM		 4091}
4092
29b0f896 4093static void
e3bb37b5 4094swap_operands (void)
29b0f896 4095{
b7c61d9a 4096 switch (i.operands)
050dfa73 4097 {
c0f3af97 4098 case 5:
b7c61d9a 4099 case 4:
4d456e3d 4100 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4101 case 3:
4102 case 2:
4d456e3d 4103 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4104 break;
4105 default:
4106 abort ();
29b0f896 4107 }
29b0f896
AM		 4108
4109 if (i.mem_operands == 2)
4110 {
4111 const seg_entry *temp_seg;
4112 temp_seg = i.seg[0];
4113 i.seg[0] = i.seg[1];
4114 i.seg[1] = temp_seg;
4115 }
4116}
252b5132 4117
29b0f896
AM		 4118/* Try to ensure constant immediates are represented in the smallest
4119 opcode possible. */
4120static void
e3bb37b5 4121optimize_imm (void)
29b0f896
AM		 4122{
4123 char guess_suffix = 0;
4124 int op;
252b5132 4125
29b0f896
AM		 4126 if (i.suffix)
4127 guess_suffix = i.suffix;
4128 else if (i.reg_operands)
4129 {
4130 /* Figure out a suffix from the last register operand specified.
4131 We can't do this properly yet, ie. excluding InOutPortReg,
4132 but the following works for instructions with immediates.
4133 In any case, we can't set i.suffix yet. */
4134 for (op = i.operands; --op >= 0;)
40fb9820 4135 if (i.types[op].bitfield.reg8)
7ab9ffdd 4136 {
40fb9820
L		 4137 guess_suffix = BYTE_MNEM_SUFFIX;
4138 break;
4139 }
4140 else if (i.types[op].bitfield.reg16)
252b5132 4141 {
40fb9820
L		 4142 guess_suffix = WORD_MNEM_SUFFIX;
4143 break;
4144 }
4145 else if (i.types[op].bitfield.reg32)
4146 {
4147 guess_suffix = LONG_MNEM_SUFFIX;
4148 break;
4149 }
4150 else if (i.types[op].bitfield.reg64)
4151 {
4152 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4153 break;
252b5132 4154 }
29b0f896
AM		 4155 }
4156 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4157 guess_suffix = WORD_MNEM_SUFFIX;
4158
4159 for (op = i.operands; --op >= 0;)
40fb9820 4160 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4161 {
4162 switch (i.op[op].imms->X_op)
252b5132 4163 {
29b0f896
AM		 4164 case O_constant:
4165 /* If a suffix is given, this operand may be shortened. */
4166 switch (guess_suffix)
252b5132 4167 {
29b0f896 4168 case LONG_MNEM_SUFFIX:
40fb9820
L		 4169 i.types[op].bitfield.imm32 = 1;
4170 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4171 break;
4172 case WORD_MNEM_SUFFIX:
40fb9820
L		 4173 i.types[op].bitfield.imm16 = 1;
4174 i.types[op].bitfield.imm32 = 1;
4175 i.types[op].bitfield.imm32s = 1;
4176 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4177 break;
4178 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4179 i.types[op].bitfield.imm8 = 1;
4180 i.types[op].bitfield.imm8s = 1;
4181 i.types[op].bitfield.imm16 = 1;
4182 i.types[op].bitfield.imm32 = 1;
4183 i.types[op].bitfield.imm32s = 1;
4184 i.types[op].bitfield.imm64 = 1;
29b0f896 4185 break;
252b5132 4186 }
252b5132 4187
29b0f896
AM		 4188 /* If this operand is at most 16 bits, convert it
4189 to a signed 16 bit number before trying to see
4190 whether it will fit in an even smaller size.
4191 This allows a 16-bit operand such as $0xffe0 to
4192 be recognised as within Imm8S range. */
40fb9820 4193 if ((i.types[op].bitfield.imm16)
29b0f896 4194 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4195 {
29b0f896
AM		 4196 i.op[op].imms->X_add_number =
4197 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4198 }
40fb9820 4199 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4200 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4201 == 0))
4202 {
4203 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4204 ^ ((offsetT) 1 << 31))
4205 - ((offsetT) 1 << 31));
4206 }
40fb9820 4207 i.types[op]
c6fb90c8
L		 4208 = operand_type_or (i.types[op],
4209 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4210
29b0f896
AM		 4211 /* We must avoid matching of Imm32 templates when 64bit
4212 only immediate is available. */
4213 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4214 i.types[op].bitfield.imm32 = 0;
29b0f896 4215 break;
252b5132 4216
29b0f896
AM		 4217 case O_absent:
4218 case O_register:
4219 abort ();
4220
4221 /* Symbols and expressions. */
4222 default:
9cd96992
JB		 4223 /* Convert symbolic operand to proper sizes for matching, but don't
4224 prevent matching a set of insns that only supports sizes other
4225 than those matching the insn suffix. */
4226 {
40fb9820 4227 i386_operand_type mask, allowed;
d3ce72d0 4228 const insn_template *t;
9cd96992 4229
0dfbf9d7
L		 4230 operand_type_set (&mask, 0);
4231 operand_type_set (&allowed, 0);
40fb9820 4232
4eed87de
AM		 4233 for (t = current_templates->start;
4234 t < current_templates->end;
4235 ++t)
c6fb90c8
L		 4236 allowed = operand_type_or (allowed,
4237 t->operand_types[op]);
9cd96992
JB		 4238 switch (guess_suffix)
4239 {
4240 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4241 mask.bitfield.imm64 = 1;
4242 mask.bitfield.imm32s = 1;
9cd96992
JB		 4243 break;
4244 case LONG_MNEM_SUFFIX:
40fb9820 4245 mask.bitfield.imm32 = 1;
9cd96992
JB		 4246 break;
4247 case WORD_MNEM_SUFFIX:
40fb9820 4248 mask.bitfield.imm16 = 1;
9cd96992
JB		 4249 break;
4250 case BYTE_MNEM_SUFFIX:
40fb9820 4251 mask.bitfield.imm8 = 1;
9cd96992
JB		 4252 break;
4253 default:
9cd96992
JB		 4254 break;
4255 }
c6fb90c8 4256 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4257 if (!operand_type_all_zero (&allowed))
c6fb90c8 4258 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4259 }
29b0f896 4260 break;
252b5132 4261 }
29b0f896
AM		 4262 }
4263}
47926f60 4264
29b0f896
AM		 4265/* Try to use the smallest displacement type too. */
4266static void
e3bb37b5 4267optimize_disp (void)
29b0f896
AM		 4268{
4269 int op;
3e73aa7c 4270
29b0f896 4271 for (op = i.operands; --op >= 0;)
40fb9820 4272 if (operand_type_check (i.types[op], disp))
252b5132 4273 {
b300c311 4274 if (i.op[op].disps->X_op == O_constant)
252b5132 4275 {
91d6fa6a 4276 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4277
40fb9820 4278 if (i.types[op].bitfield.disp16
91d6fa6a 4279 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4280 {
4281 /* If this operand is at most 16 bits, convert
4282 to a signed 16 bit number and don't use 64bit
4283 displacement. */
91d6fa6a 4284 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4285 i.types[op].bitfield.disp64 = 0;
b300c311 4286 }
40fb9820 4287 if (i.types[op].bitfield.disp32
91d6fa6a 4288 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4289 {
4290 /* If this operand is at most 32 bits, convert
4291 to a signed 32 bit number and don't use 64bit
4292 displacement. */
91d6fa6a
NC		 4293 op_disp &= (((offsetT) 2 << 31) - 1);
4294 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4295 i.types[op].bitfield.disp64 = 0;
b300c311 4296 }
91d6fa6a 4297 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4298 {
40fb9820
L		 4299 i.types[op].bitfield.disp8 = 0;
4300 i.types[op].bitfield.disp16 = 0;
4301 i.types[op].bitfield.disp32 = 0;
4302 i.types[op].bitfield.disp32s = 0;
4303 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4304 i.op[op].disps = 0;
4305 i.disp_operands--;
4306 }
4307 else if (flag_code == CODE_64BIT)
4308 {
91d6fa6a 4309 if (fits_in_signed_long (op_disp))
28a9d8f5 4310 {
40fb9820
L		 4311 i.types[op].bitfield.disp64 = 0;
4312 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4313 }
0e1147d9 4314 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4315 && fits_in_unsigned_long (op_disp))
40fb9820 4316 i.types[op].bitfield.disp32 = 1;
b300c311 4317 }
40fb9820
L		 4318 if ((i.types[op].bitfield.disp32
4319 || i.types[op].bitfield.disp32s
4320 || i.types[op].bitfield.disp16)
91d6fa6a 4321 && fits_in_signed_byte (op_disp))
40fb9820 4322 i.types[op].bitfield.disp8 = 1;
252b5132 4323 }
67a4f2b7
AO		 4324 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4325 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4326 {
4327 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4328 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4329 i.types[op].bitfield.disp8 = 0;
4330 i.types[op].bitfield.disp16 = 0;
4331 i.types[op].bitfield.disp32 = 0;
4332 i.types[op].bitfield.disp32s = 0;
4333 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4334 }
4335 else
b300c311 4336 /* We only support 64bit displacement on constants. */
40fb9820 4337 i.types[op].bitfield.disp64 = 0;
252b5132 4338 }
29b0f896
AM		 4339}
4340
6c30d220
L		 4341/* Check if operands are valid for the instruction. */
4342
4343static int
4344check_VecOperands (const insn_template *t)
4345{
43234a1e
L		 4346 unsigned int op;
4347
6c30d220
L		 4348 /* Without VSIB byte, we can't have a vector register for index. */
4349 if (!t->opcode_modifier.vecsib
4350 && i.index_reg
4351 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4352 || i.index_reg->reg_type.bitfield.regymm
4353 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4354 {
4355 i.error = unsupported_vector_index_register;
4356 return 1;
4357 }
4358
ad8ecc81
MZ		 4359 /* Check if default mask is allowed. */
4360 if (t->opcode_modifier.nodefmask
4361 && (!i.mask || i.mask->mask->reg_num == 0))
4362 {
4363 i.error = no_default_mask;
4364 return 1;
4365 }
4366
7bab8ab5
JB		 4367 /* For VSIB byte, we need a vector register for index, and all vector
4368 registers must be distinct. */
4369 if (t->opcode_modifier.vecsib)
4370 {
4371 if (!i.index_reg
6c30d220
L		 4372 || !((t->opcode_modifier.vecsib == VecSIB128
4373 && i.index_reg->reg_type.bitfield.regxmm)
4374 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4375 && i.index_reg->reg_type.bitfield.regymm)
4376 || (t->opcode_modifier.vecsib == VecSIB512
4377 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4378 {
4379 i.error = invalid_vsib_address;
4380 return 1;
4381 }
4382
43234a1e
L		 4383 gas_assert (i.reg_operands == 2 || i.mask);
4384 if (i.reg_operands == 2 && !i.mask)
4385 {
4386 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4387 || i.types[0].bitfield.regymm);
43234a1e 4388 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4389 || i.types[2].bitfield.regymm);
43234a1e
L		 4390 if (operand_check == check_none)
4391 return 0;
4392 if (register_number (i.op[0].regs)
4393 != register_number (i.index_reg)
4394 && register_number (i.op[2].regs)
4395 != register_number (i.index_reg)
4396 && register_number (i.op[0].regs)
4397 != register_number (i.op[2].regs))
4398 return 0;
4399 if (operand_check == check_error)
4400 {
4401 i.error = invalid_vector_register_set;
4402 return 1;
4403 }
4404 as_warn (_("mask, index, and destination registers should be distinct"));
4405 }
8444f82a
MZ		 4406 else if (i.reg_operands == 1 && i.mask)
4407 {
4408 if ((i.types[1].bitfield.regymm
4409 || i.types[1].bitfield.regzmm)
4410 && (register_number (i.op[1].regs)
4411 == register_number (i.index_reg)))
4412 {
4413 if (operand_check == check_error)
4414 {
4415 i.error = invalid_vector_register_set;
4416 return 1;
4417 }
4418 if (operand_check != check_none)
4419 as_warn (_("index and destination registers should be distinct"));
4420 }
4421 }
43234a1e 4422 }
7bab8ab5 4423
43234a1e
L		 4424 /* Check if broadcast is supported by the instruction and is applied
4425 to the memory operand. */
4426 if (i.broadcast)
4427 {
4428 int broadcasted_opnd_size;
4429
4430 /* Check if specified broadcast is supported in this instruction,
4431 and it's applied to memory operand of DWORD or QWORD type,
4432 depending on VecESize. */
4433 if (i.broadcast->type != t->opcode_modifier.broadcast
4434 || !i.types[i.broadcast->operand].bitfield.mem
4435 || (t->opcode_modifier.vecesize == 0
4436 && !i.types[i.broadcast->operand].bitfield.dword
4437 && !i.types[i.broadcast->operand].bitfield.unspecified)
4438 || (t->opcode_modifier.vecesize == 1
4439 && !i.types[i.broadcast->operand].bitfield.qword
4440 && !i.types[i.broadcast->operand].bitfield.unspecified))
4441 goto bad_broadcast;
4442
4443 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4444 if (i.broadcast->type == BROADCAST_1TO16)
4445 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4446 else if (i.broadcast->type == BROADCAST_1TO8)
4447 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
4448 else
4449 goto bad_broadcast;
4450
4451 if ((broadcasted_opnd_size == 256
4452 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4453 || (broadcasted_opnd_size == 512
4454 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4455 {
4456 bad_broadcast:
4457 i.error = unsupported_broadcast;
4458 return 1;
4459 }
4460 }
4461 /* If broadcast is supported in this instruction, we need to check if
4462 operand of one-element size isn't specified without broadcast. */
4463 else if (t->opcode_modifier.broadcast && i.mem_operands)
4464 {
4465 /* Find memory operand. */
4466 for (op = 0; op < i.operands; op++)
4467 if (operand_type_check (i.types[op], anymem))
4468 break;
4469 gas_assert (op < i.operands);
4470 /* Check size of the memory operand. */
4471 if ((t->opcode_modifier.vecesize == 0
4472 && i.types[op].bitfield.dword)
4473 || (t->opcode_modifier.vecesize == 1
4474 && i.types[op].bitfield.qword))
4475 {
4476 i.error = broadcast_needed;
4477 return 1;
4478 }
4479 }
4480
4481 /* Check if requested masking is supported. */
4482 if (i.mask
4483 && (!t->opcode_modifier.masking
4484 || (i.mask->zeroing
4485 && t->opcode_modifier.masking == MERGING_MASKING)))
4486 {
4487 i.error = unsupported_masking;
4488 return 1;
4489 }
4490
4491 /* Check if masking is applied to dest operand. */
4492 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4493 {
4494 i.error = mask_not_on_destination;
4495 return 1;
4496 }
4497
43234a1e
L		 4498 /* Check RC/SAE. */
4499 if (i.rounding)
4500 {
4501 if ((i.rounding->type != saeonly
4502 && !t->opcode_modifier.staticrounding)
4503 || (i.rounding->type == saeonly
4504 && (t->opcode_modifier.staticrounding
4505 || !t->opcode_modifier.sae)))
4506 {
4507 i.error = unsupported_rc_sae;
4508 return 1;
4509 }
4510 /* If the instruction has several immediate operands and one of
4511 them is rounding, the rounding operand should be the last
4512 immediate operand. */
4513 if (i.imm_operands > 1
4514 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4515 {
43234a1e 4516 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4517 return 1;
4518 }
6c30d220
L		 4519 }
4520
43234a1e
L		 4521 /* Check vector Disp8 operand. */
4522 if (t->opcode_modifier.disp8memshift)
4523 {
4524 if (i.broadcast)
4525 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4526 else
4527 i.memshift = t->opcode_modifier.disp8memshift;
4528
4529 for (op = 0; op < i.operands; op++)
4530 if (operand_type_check (i.types[op], disp)
4531 && i.op[op].disps->X_op == O_constant)
4532 {
4533 offsetT value = i.op[op].disps->X_add_number;
4534 int vec_disp8_ok = fits_in_vec_disp8 (value);
4535 if (t->operand_types [op].bitfield.vec_disp8)
4536 {
4537 if (vec_disp8_ok)
4538 i.types[op].bitfield.vec_disp8 = 1;
4539 else
4540 {
4541 /* Vector insn can only have Vec_Disp8/Disp32 in
4542 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4543 mode. */
4544 i.types[op].bitfield.disp8 = 0;
4545 if (flag_code != CODE_16BIT)
4546 i.types[op].bitfield.disp16 = 0;
4547 }
4548 }
4549 else if (flag_code != CODE_16BIT)
4550 {
4551 /* One form of this instruction supports vector Disp8.
4552 Try vector Disp8 if we need to use Disp32. */
4553 if (vec_disp8_ok && !fits_in_signed_byte (value))
4554 {
4555 i.error = try_vector_disp8;
4556 return 1;
4557 }
4558 }
4559 }
4560 }
4561 else
4562 i.memshift = -1;
4563
6c30d220
L		 4564 return 0;
4565}
4566
43f3e2ee 4567/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4568 operand types. */
4569
4570static int
4571VEX_check_operands (const insn_template *t)
4572{
43234a1e
L		 4573 /* VREX is only valid with EVEX prefix. */
4574 if (i.need_vrex && !t->opcode_modifier.evex)
4575 {
4576 i.error = invalid_register_operand;
4577 return 1;
4578 }
4579
a683cc34
SP		 4580 if (!t->opcode_modifier.vex)
4581 return 0;
4582
4583 /* Only check VEX_Imm4, which must be the first operand. */
4584 if (t->operand_types[0].bitfield.vec_imm4)
4585 {
4586 if (i.op[0].imms->X_op != O_constant
4587 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4588 {
a65babc9 4589 i.error = bad_imm4;
891edac4
L		 4590 return 1;
4591 }
a683cc34
SP		 4592
4593 /* Turn off Imm8 so that update_imm won't complain. */
4594 i.types[0] = vec_imm4;
4595 }
4596
4597 return 0;
4598}
4599
d3ce72d0 4600static const insn_template *
e3bb37b5 4601match_template (void)
29b0f896
AM		 4602{
4603 /* Points to template once we've found it. */
d3ce72d0 4604 const insn_template *t;
40fb9820 4605 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4606 i386_operand_type overlap4;
29b0f896 4607 unsigned int found_reverse_match;
40fb9820
L		 4608 i386_opcode_modifier suffix_check;
4609 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4610 int addr_prefix_disp;
a5c311ca 4611 unsigned int j;
3629bb00 4612 unsigned int found_cpu_match;
45664ddb 4613 unsigned int check_register;
5614d22c 4614 enum i386_error specific_error = 0;
29b0f896 4615
c0f3af97
L		 4616#if MAX_OPERANDS != 5
4617# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4618#endif
4619
29b0f896 4620 found_reverse_match = 0;
539e75ad 4621 addr_prefix_disp = -1;
40fb9820
L		 4622
4623 memset (&suffix_check, 0, sizeof (suffix_check));
4624 if (i.suffix == BYTE_MNEM_SUFFIX)
4625 suffix_check.no_bsuf = 1;
4626 else if (i.suffix == WORD_MNEM_SUFFIX)
4627 suffix_check.no_wsuf = 1;
4628 else if (i.suffix == SHORT_MNEM_SUFFIX)
4629 suffix_check.no_ssuf = 1;
4630 else if (i.suffix == LONG_MNEM_SUFFIX)
4631 suffix_check.no_lsuf = 1;
4632 else if (i.suffix == QWORD_MNEM_SUFFIX)
4633 suffix_check.no_qsuf = 1;
4634 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4635 suffix_check.no_ldsuf = 1;
29b0f896 4636
01559ecc
L		 4637 /* Must have right number of operands. */
4638 i.error = number_of_operands_mismatch;
4639
45aa61fe 4640 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4641 {
539e75ad
L		 4642 addr_prefix_disp = -1;
4643
29b0f896
AM		 4644 if (i.operands != t->operands)
4645 continue;
4646
50aecf8c 4647 /* Check processor support. */
a65babc9 4648 i.error = unsupported;
c0f3af97
L		 4649 found_cpu_match = (cpu_flags_match (t)
4650 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4651 if (!found_cpu_match)
4652 continue;
4653
e1d4d893 4654 /* Check old gcc support. */
a65babc9 4655 i.error = old_gcc_only;
e1d4d893
L		 4656 if (!old_gcc && t->opcode_modifier.oldgcc)
4657 continue;
4658
4659 /* Check AT&T mnemonic. */
a65babc9 4660 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4661 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4662 continue;
4663
891edac4 4664 /* Check AT&T/Intel syntax. */
a65babc9 4665 i.error = unsupported_syntax;
5c07affc
L		 4666 if ((intel_syntax && t->opcode_modifier.attsyntax)
4667 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4668 continue;
4669
20592a94 4670 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4671 i.error = invalid_instruction_suffix;
567e4e96
L		 4672 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4673 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4674 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4675 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4676 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4677 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4678 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4679 continue;
4680
5c07affc 4681 if (!operand_size_match (t))
7d5e4556 4682 continue;
539e75ad 4683
5c07affc
L		 4684 for (j = 0; j < MAX_OPERANDS; j++)
4685 operand_types[j] = t->operand_types[j];
4686
45aa61fe
AM		 4687 /* In general, don't allow 64-bit operands in 32-bit mode. */
4688 if (i.suffix == QWORD_MNEM_SUFFIX
4689 && flag_code != CODE_64BIT
4690 && (intel_syntax
40fb9820 4691 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4692 && !intel_float_operand (t->name))
4693 : intel_float_operand (t->name) != 2)
40fb9820 4694 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4695 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4696 && !operand_types[0].bitfield.regymm
4697 && !operand_types[0].bitfield.regzmm)
40fb9820 4698 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97 4699 && !!operand_types[t->operands > 1].bitfield.regxmm
43234a1e
L		 4700 && !!operand_types[t->operands > 1].bitfield.regymm
4701 && !!operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4702 && (t->base_opcode != 0x0fc7
4703 || t->extension_opcode != 1 /* cmpxchg8b */))
4704 continue;
4705
192dc9c6
JB		 4706 /* In general, don't allow 32-bit operands on pre-386. */
4707 else if (i.suffix == LONG_MNEM_SUFFIX
4708 && !cpu_arch_flags.bitfield.cpui386
4709 && (intel_syntax
4710 ? (!t->opcode_modifier.ignoresize
4711 && !intel_float_operand (t->name))
4712 : intel_float_operand (t->name) != 2)
4713 && ((!operand_types[0].bitfield.regmmx
4714 && !operand_types[0].bitfield.regxmm)
4715 || (!operand_types[t->operands > 1].bitfield.regmmx
4716 && !!operand_types[t->operands > 1].bitfield.regxmm)))
4717 continue;
4718
29b0f896 4719 /* Do not verify operands when there are none. */
50aecf8c 4720 else
29b0f896 4721 {
c6fb90c8 4722 if (!t->operands)
2dbab7d5
L		 4723 /* We've found a match; break out of loop. */
4724 break;
29b0f896 4725 }
252b5132 4726
539e75ad
L		 4727 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4728 into Disp32/Disp16/Disp32 operand. */
4729 if (i.prefix[ADDR_PREFIX] != 0)
4730 {
40fb9820 4731 /* There should be only one Disp operand. */
539e75ad
L		 4732 switch (flag_code)
4733 {
4734 case CODE_16BIT:
40fb9820
L		 4735 for (j = 0; j < MAX_OPERANDS; j++)
4736 {
4737 if (operand_types[j].bitfield.disp16)
4738 {
4739 addr_prefix_disp = j;
4740 operand_types[j].bitfield.disp32 = 1;
4741 operand_types[j].bitfield.disp16 = 0;
4742 break;
4743 }
4744 }
539e75ad
L		 4745 break;
4746 case CODE_32BIT:
40fb9820
L		 4747 for (j = 0; j < MAX_OPERANDS; j++)
4748 {
4749 if (operand_types[j].bitfield.disp32)
4750 {
4751 addr_prefix_disp = j;
4752 operand_types[j].bitfield.disp32 = 0;
4753 operand_types[j].bitfield.disp16 = 1;
4754 break;
4755 }
4756 }
539e75ad
L		 4757 break;
4758 case CODE_64BIT:
40fb9820
L		 4759 for (j = 0; j < MAX_OPERANDS; j++)
4760 {
4761 if (operand_types[j].bitfield.disp64)
4762 {
4763 addr_prefix_disp = j;
4764 operand_types[j].bitfield.disp64 = 0;
4765 operand_types[j].bitfield.disp32 = 1;
4766 break;
4767 }
4768 }
539e75ad
L		 4769 break;
4770 }
539e75ad
L		 4771 }
4772
56ffb741
L		 4773 /* We check register size if needed. */
4774 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4775 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4776 switch (t->operands)
4777 {
4778 case 1:
40fb9820 4779 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4780 continue;
4781 break;
4782 case 2:
8b38ad71
L		 4783 /* xchg %eax, %eax is a special case. It is an aliase for nop
4784 only in 32bit mode and we can use opcode 0x90. In 64bit
4785 mode, we can't use 0x90 for xchg %eax, %eax since it should
4786 zero-extend %eax to %rax. */
4787 if (flag_code == CODE_64BIT
4788 && t->base_opcode == 0x90
0dfbf9d7
L		 4789 && operand_type_equal (&i.types [0], &acc32)
4790 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4791 continue;
b6169b20
L		 4792 if (i.swap_operand)
4793 {
4794 /* If we swap operand in encoding, we either match
4795 the next one or reverse direction of operands. */
4796 if (t->opcode_modifier.s)
4797 continue;
4798 else if (t->opcode_modifier.d)
4799 goto check_reverse;
4800 }
4801
29b0f896 4802 case 3:
fa99fab2
L		 4803 /* If we swap operand in encoding, we match the next one. */
4804 if (i.swap_operand && t->opcode_modifier.s)
4805 continue;
f48ff2ae 4806 case 4:
c0f3af97 4807 case 5:
c6fb90c8 4808 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4809 if (!operand_type_match (overlap0, i.types[0])
4810 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4811 || (check_register
4812 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4813 operand_types[0],
4814 overlap1, i.types[1],
4815 operand_types[1])))
29b0f896
AM		 4816 {
4817 /* Check if other direction is valid ... */
40fb9820 4818 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4819 continue;
4820
b6169b20 4821check_reverse:
29b0f896 4822 /* Try reversing direction of operands. */
c6fb90c8
L		 4823 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4824 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4825 if (!operand_type_match (overlap0, i.types[0])
4826 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4827 || (check_register
4828 && !operand_type_register_match (overlap0,
4829 i.types[0],
4830 operand_types[1],
4831 overlap1,
4832 i.types[1],
4833 operand_types[0])))
29b0f896
AM		 4834 {
4835 /* Does not match either direction. */
4836 continue;
4837 }
4838 /* found_reverse_match holds which of D or FloatDR
4839 we've found. */
40fb9820 4840 if (t->opcode_modifier.d)
8a2ed489 4841 found_reverse_match = Opcode_D;
40fb9820 4842 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4843 found_reverse_match = Opcode_FloatD;
4844 else
4845 found_reverse_match = 0;
40fb9820 4846 if (t->opcode_modifier.floatr)
8a2ed489 4847 found_reverse_match |= Opcode_FloatR;
29b0f896 4848 }
f48ff2ae 4849 else
29b0f896 4850 {
f48ff2ae 4851 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4852 switch (t->operands)
4853 {
c0f3af97
L		 4854 case 5:
4855 overlap4 = operand_type_and (i.types[4],
4856 operand_types[4]);
d1cbb4db 4857 case 4:
c6fb90c8
L		 4858 overlap3 = operand_type_and (i.types[3],
4859 operand_types[3]);
d1cbb4db 4860 case 3:
c6fb90c8
L		 4861 overlap2 = operand_type_and (i.types[2],
4862 operand_types[2]);
d1cbb4db
L		 4863 break;
4864 }
29b0f896 4865
f48ff2ae
L		 4866 switch (t->operands)
4867 {
c0f3af97
L		 4868 case 5:
4869 if (!operand_type_match (overlap4, i.types[4])
4870 || !operand_type_register_match (overlap3,
4871 i.types[3],
4872 operand_types[3],
4873 overlap4,
4874 i.types[4],
4875 operand_types[4]))
4876 continue;
f48ff2ae 4877 case 4:
40fb9820 4878 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4879 || (check_register
4880 && !operand_type_register_match (overlap2,
4881 i.types[2],
4882 operand_types[2],
4883 overlap3,
4884 i.types[3],
4885 operand_types[3])))
f48ff2ae
L		 4886 continue;
4887 case 3:
4888 /* Here we make use of the fact that there are no
4889 reverse match 3 operand instructions, and all 3
4890 operand instructions only need to be checked for
4891 register consistency between operands 2 and 3. */
40fb9820 4892 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4893 || (check_register
4894 && !operand_type_register_match (overlap1,
4895 i.types[1],
4896 operand_types[1],
4897 overlap2,
4898 i.types[2],
4899 operand_types[2])))
f48ff2ae
L		 4900 continue;
4901 break;
4902 }
29b0f896 4903 }
f48ff2ae 4904 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4905 slip through to break. */
4906 }
3629bb00 4907 if (!found_cpu_match)
29b0f896
AM		 4908 {
4909 found_reverse_match = 0;
4910 continue;
4911 }
c0f3af97 4912
5614d22c
JB		 4913 /* Check if vector and VEX operands are valid. */
4914 if (check_VecOperands (t) || VEX_check_operands (t))
4915 {
4916 specific_error = i.error;
4917 continue;
4918 }
a683cc34 4919
29b0f896
AM		 4920 /* We've found a match; break out of loop. */
4921 break;
4922 }
4923
4924 if (t == current_templates->end)
4925 {
4926 /* We found no match. */
a65babc9 4927 const char *err_msg;
5614d22c 4928 switch (specific_error ? specific_error : i.error)
a65babc9
L		 4929 {
4930 default:
4931 abort ();
86e026a4 4932 case operand_size_mismatch:
a65babc9
L		 4933 err_msg = _("operand size mismatch");
4934 break;
4935 case operand_type_mismatch:
4936 err_msg = _("operand type mismatch");
4937 break;
4938 case register_type_mismatch:
4939 err_msg = _("register type mismatch");
4940 break;
4941 case number_of_operands_mismatch:
4942 err_msg = _("number of operands mismatch");
4943 break;
4944 case invalid_instruction_suffix:
4945 err_msg = _("invalid instruction suffix");
4946 break;
4947 case bad_imm4:
4a2608e3 4948 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 4949 break;
4950 case old_gcc_only:
4951 err_msg = _("only supported with old gcc");
4952 break;
4953 case unsupported_with_intel_mnemonic:
4954 err_msg = _("unsupported with Intel mnemonic");
4955 break;
4956 case unsupported_syntax:
4957 err_msg = _("unsupported syntax");
4958 break;
4959 case unsupported:
35262a23 4960 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 4961 current_templates->start->name);
4962 return NULL;
6c30d220
L		 4963 case invalid_vsib_address:
4964 err_msg = _("invalid VSIB address");
4965 break;
7bab8ab5
JB		 4966 case invalid_vector_register_set:
4967 err_msg = _("mask, index, and destination registers must be distinct");
4968 break;
6c30d220
L		 4969 case unsupported_vector_index_register:
4970 err_msg = _("unsupported vector index register");
4971 break;
43234a1e
L		 4972 case unsupported_broadcast:
4973 err_msg = _("unsupported broadcast");
4974 break;
4975 case broadcast_not_on_src_operand:
4976 err_msg = _("broadcast not on source memory operand");
4977 break;
4978 case broadcast_needed:
4979 err_msg = _("broadcast is needed for operand of such type");
4980 break;
4981 case unsupported_masking:
4982 err_msg = _("unsupported masking");
4983 break;
4984 case mask_not_on_destination:
4985 err_msg = _("mask not on destination operand");
4986 break;
4987 case no_default_mask:
4988 err_msg = _("default mask isn't allowed");
4989 break;
4990 case unsupported_rc_sae:
4991 err_msg = _("unsupported static rounding/sae");
4992 break;
4993 case rc_sae_operand_not_last_imm:
4994 if (intel_syntax)
4995 err_msg = _("RC/SAE operand must precede immediate operands");
4996 else
4997 err_msg = _("RC/SAE operand must follow immediate operands");
4998 break;
4999 case invalid_register_operand:
5000 err_msg = _("invalid register operand");
5001 break;
a65babc9
L		 5002 }
5003 as_bad (_("%s for `%s'"), err_msg,
891edac4 5004 current_templates->start->name);
fa99fab2 5005 return NULL;
29b0f896 5006 }
252b5132 5007
29b0f896
AM		 5008 if (!quiet_warnings)
5009 {
5010 if (!intel_syntax
40fb9820
L		 5011 && (i.types[0].bitfield.jumpabsolute
5012 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5013 {
5014 as_warn (_("indirect %s without `*'"), t->name);
5015 }
5016
40fb9820
L		 5017 if (t->opcode_modifier.isprefix
5018 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5019 {
5020 /* Warn them that a data or address size prefix doesn't
5021 affect assembly of the next line of code. */
5022 as_warn (_("stand-alone `%s' prefix"), t->name);
5023 }
5024 }
5025
5026 /* Copy the template we found. */
5027 i.tm = *t;
539e75ad
L		 5028
5029 if (addr_prefix_disp != -1)
5030 i.tm.operand_types[addr_prefix_disp]
5031 = operand_types[addr_prefix_disp];
5032
29b0f896
AM		 5033 if (found_reverse_match)
5034 {
5035 /* If we found a reverse match we must alter the opcode
5036 direction bit. found_reverse_match holds bits to change
5037 (different for int & float insns). */
5038
5039 i.tm.base_opcode ^= found_reverse_match;
5040
539e75ad
L		 5041 i.tm.operand_types[0] = operand_types[1];
5042 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5043 }
5044
fa99fab2 5045 return t;
29b0f896
AM		 5046}
5047
5048static int
e3bb37b5 5049check_string (void)
29b0f896 5050{
40fb9820
L		 5051 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5052 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5053 {
5054 if (i.seg[0] != NULL && i.seg[0] != &es)
5055 {
a87af027 5056 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5057 i.tm.name,
a87af027
JB		 5058 mem_op + 1,
5059 register_prefix);
29b0f896
AM		 5060 return 0;
5061 }
5062 /* There's only ever one segment override allowed per instruction.
5063 This instruction possibly has a legal segment override on the
5064 second operand, so copy the segment to where non-string
5065 instructions store it, allowing common code. */
5066 i.seg[0] = i.seg[1];
5067 }
40fb9820 5068 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5069 {
5070 if (i.seg[1] != NULL && i.seg[1] != &es)
5071 {
a87af027 5072 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5073 i.tm.name,
a87af027
JB		 5074 mem_op + 2,
5075 register_prefix);
29b0f896
AM		 5076 return 0;
5077 }
5078 }
5079 return 1;
5080}
5081
5082static int
543613e9 5083process_suffix (void)
29b0f896
AM		 5084{
5085 /* If matched instruction specifies an explicit instruction mnemonic
5086 suffix, use it. */
40fb9820
L		 5087 if (i.tm.opcode_modifier.size16)
5088 i.suffix = WORD_MNEM_SUFFIX;
5089 else if (i.tm.opcode_modifier.size32)
5090 i.suffix = LONG_MNEM_SUFFIX;
5091 else if (i.tm.opcode_modifier.size64)
5092 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5093 else if (i.reg_operands)
5094 {
5095 /* If there's no instruction mnemonic suffix we try to invent one
5096 based on register operands. */
5097 if (!i.suffix)
5098 {
5099 /* We take i.suffix from the last register operand specified,
5100 Destination register type is more significant than source
381d071f
L		 5101 register type. crc32 in SSE4.2 prefers source register
5102 type. */
5103 if (i.tm.base_opcode == 0xf20f38f1)
5104 {
40fb9820
L		 5105 if (i.types[0].bitfield.reg16)
5106 i.suffix = WORD_MNEM_SUFFIX;
5107 else if (i.types[0].bitfield.reg32)
5108 i.suffix = LONG_MNEM_SUFFIX;
5109 else if (i.types[0].bitfield.reg64)
5110 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5111 }
9344ff29 5112 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5113 {
40fb9820 5114 if (i.types[0].bitfield.reg8)
20592a94
L		 5115 i.suffix = BYTE_MNEM_SUFFIX;
5116 }
381d071f
L		 5117
5118 if (!i.suffix)
5119 {
5120 int op;
5121
20592a94
L		 5122 if (i.tm.base_opcode == 0xf20f38f1
5123 || i.tm.base_opcode == 0xf20f38f0)
5124 {
5125 /* We have to know the operand size for crc32. */
5126 as_bad (_("ambiguous memory operand size for `%s`"),
5127 i.tm.name);
5128 return 0;
5129 }
5130
381d071f 5131 for (op = i.operands; --op >= 0;)
40fb9820 5132 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5133 {
40fb9820
L		 5134 if (i.types[op].bitfield.reg8)
5135 {
5136 i.suffix = BYTE_MNEM_SUFFIX;
5137 break;
5138 }
5139 else if (i.types[op].bitfield.reg16)
5140 {
5141 i.suffix = WORD_MNEM_SUFFIX;
5142 break;
5143 }
5144 else if (i.types[op].bitfield.reg32)
5145 {
5146 i.suffix = LONG_MNEM_SUFFIX;
5147 break;
5148 }
5149 else if (i.types[op].bitfield.reg64)
5150 {
5151 i.suffix = QWORD_MNEM_SUFFIX;
5152 break;
5153 }
381d071f
L		 5154 }
5155 }
29b0f896
AM		 5156 }
5157 else if (i.suffix == BYTE_MNEM_SUFFIX)
5158 {
2eb952a4
L		 5159 if (intel_syntax
5160 && i.tm.opcode_modifier.ignoresize
5161 && i.tm.opcode_modifier.no_bsuf)
5162 i.suffix = 0;
5163 else if (!check_byte_reg ())
29b0f896
AM		 5164 return 0;
5165 }
5166 else if (i.suffix == LONG_MNEM_SUFFIX)
5167 {
2eb952a4
L		 5168 if (intel_syntax
5169 && i.tm.opcode_modifier.ignoresize
5170 && i.tm.opcode_modifier.no_lsuf)
5171 i.suffix = 0;
5172 else if (!check_long_reg ())
29b0f896
AM		 5173 return 0;
5174 }
5175 else if (i.suffix == QWORD_MNEM_SUFFIX)
5176 {
955e1e6a
L		 5177 if (intel_syntax
5178 && i.tm.opcode_modifier.ignoresize
5179 && i.tm.opcode_modifier.no_qsuf)
5180 i.suffix = 0;
5181 else if (!check_qword_reg ())
29b0f896
AM		 5182 return 0;
5183 }
5184 else if (i.suffix == WORD_MNEM_SUFFIX)
5185 {
2eb952a4
L		 5186 if (intel_syntax
5187 && i.tm.opcode_modifier.ignoresize
5188 && i.tm.opcode_modifier.no_wsuf)
5189 i.suffix = 0;
5190 else if (!check_word_reg ())
29b0f896
AM		 5191 return 0;
5192 }
c0f3af97 5193 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5194 || i.suffix == YMMWORD_MNEM_SUFFIX
5195 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5196 {
43234a1e 5197 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5198 should check if it is a valid suffix. */
5199 }
40fb9820 5200 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5201 /* Do nothing if the instruction is going to ignore the prefix. */
5202 ;
5203 else
5204 abort ();
5205 }
40fb9820 5206 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5207 && !i.suffix
5208 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5209 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5210 {
5211 i.suffix = stackop_size;
5212 }
9306ca4a
JB		 5213 else if (intel_syntax
5214 && !i.suffix
40fb9820
L		 5215 && (i.tm.operand_types[0].bitfield.jumpabsolute
5216 || i.tm.opcode_modifier.jumpbyte
5217 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5218 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5219 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5220 {
5221 switch (flag_code)
5222 {
5223 case CODE_64BIT:
40fb9820 5224 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5225 {
5226 i.suffix = QWORD_MNEM_SUFFIX;
5227 break;
5228 }
5229 case CODE_32BIT:
40fb9820 5230 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5231 i.suffix = LONG_MNEM_SUFFIX;
5232 break;
5233 case CODE_16BIT:
40fb9820 5234 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5235 i.suffix = WORD_MNEM_SUFFIX;
5236 break;
5237 }
5238 }
252b5132 5239
9306ca4a 5240 if (!i.suffix)
29b0f896 5241 {
9306ca4a
JB		 5242 if (!intel_syntax)
5243 {
40fb9820 5244 if (i.tm.opcode_modifier.w)
9306ca4a 5245 {
4eed87de
AM		 5246 as_bad (_("no instruction mnemonic suffix given and "
5247 "no register operands; can't size instruction"));
9306ca4a
JB		 5248 return 0;
5249 }
5250 }
5251 else
5252 {
40fb9820 5253 unsigned int suffixes;
7ab9ffdd 5254
40fb9820
L		 5255 suffixes = !i.tm.opcode_modifier.no_bsuf;
5256 if (!i.tm.opcode_modifier.no_wsuf)
5257 suffixes |= 1 << 1;
5258 if (!i.tm.opcode_modifier.no_lsuf)
5259 suffixes |= 1 << 2;
fc4adea1 5260 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5261 suffixes |= 1 << 3;
5262 if (!i.tm.opcode_modifier.no_ssuf)
5263 suffixes |= 1 << 4;
5264 if (!i.tm.opcode_modifier.no_qsuf)
5265 suffixes |= 1 << 5;
5266
5267 /* There are more than suffix matches. */
5268 if (i.tm.opcode_modifier.w
9306ca4a 5269 || ((suffixes & (suffixes - 1))
40fb9820
L		 5270 && !i.tm.opcode_modifier.defaultsize
5271 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5272 {
5273 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5274 return 0;
5275 }
5276 }
29b0f896 5277 }
252b5132 5278
9306ca4a
JB		 5279 /* Change the opcode based on the operand size given by i.suffix;
5280 We don't need to change things for byte insns. */
5281
582d5edd
L		 5282 if (i.suffix
5283 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5284 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5285 && i.suffix != YMMWORD_MNEM_SUFFIX
5286 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5287 {
5288 /* It's not a byte, select word/dword operation. */
40fb9820 5289 if (i.tm.opcode_modifier.w)
29b0f896 5290 {
40fb9820 5291 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5292 i.tm.base_opcode |= 8;
5293 else
5294 i.tm.base_opcode |= 1;
5295 }
0f3f3d8b 5296
29b0f896
AM		 5297 /* Now select between word & dword operations via the operand
5298 size prefix, except for instructions that will ignore this
5299 prefix anyway. */
ca61edf2 5300 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5301 {
ca61edf2
L		 5302 /* The address size override prefix changes the size of the
5303 first operand. */
40fb9820
L		 5304 if ((flag_code == CODE_32BIT
5305 && i.op->regs[0].reg_type.bitfield.reg16)
5306 || (flag_code != CODE_32BIT
5307 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5308 if (!add_prefix (ADDR_PREFIX_OPCODE))
5309 return 0;
5310 }
5311 else if (i.suffix != QWORD_MNEM_SUFFIX
5312 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5313 && !i.tm.opcode_modifier.ignoresize
5314 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5315 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5316 || (flag_code == CODE_64BIT
40fb9820 5317 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5318 {
5319 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5320
40fb9820 5321 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5322 prefix = ADDR_PREFIX_OPCODE;
252b5132 5323
29b0f896
AM		 5324 if (!add_prefix (prefix))
5325 return 0;
24eab124 5326 }
252b5132 5327
29b0f896
AM		 5328 /* Set mode64 for an operand. */
5329 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5330 && flag_code == CODE_64BIT
40fb9820 5331 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5332 {
5333 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5334 need rex64. cmpxchg8b is also a special case. */
5335 if (! (i.operands == 2
5336 && i.tm.base_opcode == 0x90
5337 && i.tm.extension_opcode == None
0dfbf9d7
L		 5338 && operand_type_equal (&i.types [0], &acc64)
5339 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5340 && ! (i.operands == 1
5341 && i.tm.base_opcode == 0xfc7
5342 && i.tm.extension_opcode == 1
40fb9820
L		 5343 && !operand_type_check (i.types [0], reg)
5344 && operand_type_check (i.types [0], anymem)))
f6bee062 5345 i.rex |= REX_W;
46e883c5 5346 }
3e73aa7c 5347
29b0f896
AM		 5348 /* Size floating point instruction. */
5349 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5350 if (i.tm.opcode_modifier.floatmf)
543613e9 5351 i.tm.base_opcode ^= 4;
29b0f896 5352 }
7ecd2f8b 5353
29b0f896
AM		 5354 return 1;
5355}
3e73aa7c 5356
29b0f896 5357static int
543613e9 5358check_byte_reg (void)
29b0f896
AM		 5359{
5360 int op;
543613e9 5361
29b0f896
AM		 5362 for (op = i.operands; --op >= 0;)
5363 {
5364 /* If this is an eight bit register, it's OK. If it's the 16 or
5365 32 bit version of an eight bit register, we will just use the
5366 low portion, and that's OK too. */
40fb9820 5367 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5368 continue;
5369
5a819eb9
JB		 5370 /* I/O port address operands are OK too. */
5371 if (i.tm.operand_types[op].bitfield.inoutportreg)
5372 continue;
5373
9344ff29
L		 5374 /* crc32 doesn't generate this warning. */
5375 if (i.tm.base_opcode == 0xf20f38f0)
5376 continue;
5377
40fb9820
L		 5378 if ((i.types[op].bitfield.reg16
5379 || i.types[op].bitfield.reg32
5380 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5381 && i.op[op].regs->reg_num < 4
5382 /* Prohibit these changes in 64bit mode, since the lowering
5383 would be more complicated. */
5384 && flag_code != CODE_64BIT)
29b0f896 5385 {
29b0f896 5386#if REGISTER_WARNINGS
5a819eb9 5387 if (!quiet_warnings)
a540244d
L		 5388 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5389 register_prefix,
40fb9820 5390 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5391 ? REGNAM_AL - REGNAM_AX
5392 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5393 register_prefix,
29b0f896
AM		 5394 i.op[op].regs->reg_name,
5395 i.suffix);
5396#endif
5397 continue;
5398 }
5399 /* Any other register is bad. */
40fb9820
L		 5400 if (i.types[op].bitfield.reg16
5401 || i.types[op].bitfield.reg32
5402 || i.types[op].bitfield.reg64
5403 || i.types[op].bitfield.regmmx
5404 || i.types[op].bitfield.regxmm
c0f3af97 5405 || i.types[op].bitfield.regymm
43234a1e 5406 || i.types[op].bitfield.regzmm
40fb9820
L		 5407 || i.types[op].bitfield.sreg2
5408 || i.types[op].bitfield.sreg3
5409 || i.types[op].bitfield.control
5410 || i.types[op].bitfield.debug
5411 || i.types[op].bitfield.test
5412 || i.types[op].bitfield.floatreg
5413 || i.types[op].bitfield.floatacc)
29b0f896 5414 {
a540244d
L		 5415 as_bad (_("`%s%s' not allowed with `%s%c'"),
5416 register_prefix,
29b0f896
AM		 5417 i.op[op].regs->reg_name,
5418 i.tm.name,
5419 i.suffix);
5420 return 0;
5421 }
5422 }
5423 return 1;
5424}
5425
5426static int
e3bb37b5 5427check_long_reg (void)
29b0f896
AM		 5428{
5429 int op;
5430
5431 for (op = i.operands; --op >= 0;)
5432 /* Reject eight bit registers, except where the template requires
5433 them. (eg. movzb) */
40fb9820
L		 5434 if (i.types[op].bitfield.reg8
5435 && (i.tm.operand_types[op].bitfield.reg16
5436 || i.tm.operand_types[op].bitfield.reg32
5437 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5438 {
a540244d
L		 5439 as_bad (_("`%s%s' not allowed with `%s%c'"),
5440 register_prefix,
29b0f896
AM		 5441 i.op[op].regs->reg_name,
5442 i.tm.name,
5443 i.suffix);
5444 return 0;
5445 }
e4630f71 5446 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5447 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5448 && i.types[op].bitfield.reg16
5449 && (i.tm.operand_types[op].bitfield.reg32
5450 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5451 {
5452 /* Prohibit these changes in the 64bit mode, since the
5453 lowering is more complicated. */
5454 if (flag_code == CODE_64BIT)
252b5132 5455 {
2b5d6a91 5456 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5457 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5458 i.suffix);
5459 return 0;
252b5132 5460 }
29b0f896 5461#if REGISTER_WARNINGS
cecf1424
JB		 5462 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5463 register_prefix,
5464 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5465 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5466#endif
252b5132 5467 }
e4630f71 5468 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5469 else if (i.types[op].bitfield.reg64
5470 && (i.tm.operand_types[op].bitfield.reg32
5471 || i.tm.operand_types[op].bitfield.acc))
252b5132 5472 {
34828aad 5473 if (intel_syntax
ca61edf2 5474 && i.tm.opcode_modifier.toqword
40fb9820 5475 && !i.types[0].bitfield.regxmm)
34828aad 5476 {
ca61edf2 5477 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5478 i.suffix = QWORD_MNEM_SUFFIX;
5479 }
5480 else
5481 {
2b5d6a91 5482 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5483 register_prefix, i.op[op].regs->reg_name,
5484 i.suffix);
5485 return 0;
5486 }
29b0f896
AM		 5487 }
5488 return 1;
5489}
252b5132 5490
29b0f896 5491static int
e3bb37b5 5492check_qword_reg (void)
29b0f896
AM		 5493{
5494 int op;
252b5132 5495
29b0f896
AM		 5496 for (op = i.operands; --op >= 0; )
5497 /* Reject eight bit registers, except where the template requires
5498 them. (eg. movzb) */
40fb9820
L		 5499 if (i.types[op].bitfield.reg8
5500 && (i.tm.operand_types[op].bitfield.reg16
5501 || i.tm.operand_types[op].bitfield.reg32
5502 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5503 {
a540244d
L		 5504 as_bad (_("`%s%s' not allowed with `%s%c'"),
5505 register_prefix,
29b0f896
AM		 5506 i.op[op].regs->reg_name,
5507 i.tm.name,
5508 i.suffix);
5509 return 0;
5510 }
e4630f71 5511 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5512 else if ((i.types[op].bitfield.reg16
5513 || i.types[op].bitfield.reg32)
5514 && (i.tm.operand_types[op].bitfield.reg32
5515 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5516 {
5517 /* Prohibit these changes in the 64bit mode, since the
5518 lowering is more complicated. */
34828aad 5519 if (intel_syntax
ca61edf2 5520 && i.tm.opcode_modifier.todword
40fb9820 5521 && !i.types[0].bitfield.regxmm)
34828aad 5522 {
ca61edf2 5523 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5524 i.suffix = LONG_MNEM_SUFFIX;
5525 }
5526 else
5527 {
2b5d6a91 5528 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5529 register_prefix, i.op[op].regs->reg_name,
5530 i.suffix);
5531 return 0;
5532 }
252b5132 5533 }
29b0f896
AM		 5534 return 1;
5535}
252b5132 5536
29b0f896 5537static int
e3bb37b5 5538check_word_reg (void)
29b0f896
AM		 5539{
5540 int op;
5541 for (op = i.operands; --op >= 0;)
5542 /* Reject eight bit registers, except where the template requires
5543 them. (eg. movzb) */
40fb9820
L		 5544 if (i.types[op].bitfield.reg8
5545 && (i.tm.operand_types[op].bitfield.reg16
5546 || i.tm.operand_types[op].bitfield.reg32
5547 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5548 {
a540244d
L		 5549 as_bad (_("`%s%s' not allowed with `%s%c'"),
5550 register_prefix,
29b0f896
AM		 5551 i.op[op].regs->reg_name,
5552 i.tm.name,
5553 i.suffix);
5554 return 0;
5555 }
e4630f71 5556 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5557 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5558 && (i.types[op].bitfield.reg32
5559 || i.types[op].bitfield.reg64)
40fb9820
L		 5560 && (i.tm.operand_types[op].bitfield.reg16
5561 || i.tm.operand_types[op].bitfield.acc))
252b5132 5562 {
29b0f896
AM		 5563 /* Prohibit these changes in the 64bit mode, since the
5564 lowering is more complicated. */
5565 if (flag_code == CODE_64BIT)
252b5132 5566 {
2b5d6a91 5567 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5568 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5569 i.suffix);
5570 return 0;
252b5132 5571 }
29b0f896 5572#if REGISTER_WARNINGS
cecf1424
JB		 5573 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5574 register_prefix,
5575 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5576 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5577#endif
5578 }
5579 return 1;
5580}
252b5132 5581
29b0f896 5582static int
40fb9820 5583update_imm (unsigned int j)
29b0f896 5584{
bc0844ae 5585 i386_operand_type overlap = i.types[j];
40fb9820
L		 5586 if ((overlap.bitfield.imm8
5587 || overlap.bitfield.imm8s
5588 || overlap.bitfield.imm16
5589 || overlap.bitfield.imm32
5590 || overlap.bitfield.imm32s
5591 || overlap.bitfield.imm64)
0dfbf9d7
L		 5592 && !operand_type_equal (&overlap, &imm8)
5593 && !operand_type_equal (&overlap, &imm8s)
5594 && !operand_type_equal (&overlap, &imm16)
5595 && !operand_type_equal (&overlap, &imm32)
5596 && !operand_type_equal (&overlap, &imm32s)
5597 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5598 {
5599 if (i.suffix)
5600 {
40fb9820
L		 5601 i386_operand_type temp;
5602
0dfbf9d7 5603 operand_type_set (&temp, 0);
7ab9ffdd 5604 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5605 {
5606 temp.bitfield.imm8 = overlap.bitfield.imm8;
5607 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5608 }
5609 else if (i.suffix == WORD_MNEM_SUFFIX)
5610 temp.bitfield.imm16 = overlap.bitfield.imm16;
5611 else if (i.suffix == QWORD_MNEM_SUFFIX)
5612 {
5613 temp.bitfield.imm64 = overlap.bitfield.imm64;
5614 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5615 }
5616 else
5617 temp.bitfield.imm32 = overlap.bitfield.imm32;
5618 overlap = temp;
29b0f896 5619 }
0dfbf9d7
L		 5620 else if (operand_type_equal (&overlap, &imm16_32_32s)
5621 || operand_type_equal (&overlap, &imm16_32)
5622 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5623 {
40fb9820 5624 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5625 overlap = imm16;
40fb9820 5626 else
65da13b5 5627 overlap = imm32s;
29b0f896 5628 }
0dfbf9d7
L		 5629 if (!operand_type_equal (&overlap, &imm8)
5630 && !operand_type_equal (&overlap, &imm8s)
5631 && !operand_type_equal (&overlap, &imm16)
5632 && !operand_type_equal (&overlap, &imm32)
5633 && !operand_type_equal (&overlap, &imm32s)
5634 && !operand_type_equal (&overlap, &imm64))
29b0f896 5635 {
4eed87de
AM		 5636 as_bad (_("no instruction mnemonic suffix given; "
5637 "can't determine immediate size"));
29b0f896
AM		 5638 return 0;
5639 }
5640 }
40fb9820 5641 i.types[j] = overlap;
29b0f896 5642
40fb9820
L		 5643 return 1;
5644}
5645
5646static int
5647finalize_imm (void)
5648{
bc0844ae 5649 unsigned int j, n;
29b0f896 5650
bc0844ae
L		 5651 /* Update the first 2 immediate operands. */
5652 n = i.operands > 2 ? 2 : i.operands;
5653 if (n)
5654 {
5655 for (j = 0; j < n; j++)
5656 if (update_imm (j) == 0)
5657 return 0;
40fb9820 5658
bc0844ae
L		 5659 /* The 3rd operand can't be immediate operand. */
5660 gas_assert (operand_type_check (i.types[2], imm) == 0);
5661 }
29b0f896
AM		 5662
5663 return 1;
5664}
5665
c0f3af97
L		 5666static int
5667bad_implicit_operand (int xmm)
5668{
91d6fa6a
NC		 5669 const char *ireg = xmm ? "xmm0" : "ymm0";
5670
c0f3af97
L		 5671 if (intel_syntax)
5672 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5673 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5674 else
5675 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5676 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5677 return 0;
5678}
5679
29b0f896 5680static int
e3bb37b5 5681process_operands (void)
29b0f896
AM		 5682{
5683 /* Default segment register this instruction will use for memory
5684 accesses. 0 means unknown. This is only for optimizing out
5685 unnecessary segment overrides. */
5686 const seg_entry *default_seg = 0;
5687
2426c15f 5688 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5689 {
91d6fa6a
NC		 5690 unsigned int dupl = i.operands;
5691 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5692 unsigned int j;
5693
c0f3af97 5694 /* The destination must be an xmm register. */
9c2799c2 5695 gas_assert (i.reg_operands
91d6fa6a 5696 && MAX_OPERANDS > dupl
7ab9ffdd 5697 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5698
5699 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5700 {
c0f3af97 5701 /* The first operand is implicit and must be xmm0. */
9c2799c2 5702 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5703 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5704 return bad_implicit_operand (1);
5705
8cd7925b 5706 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5707 {
5708 /* Keep xmm0 for instructions with VEX prefix and 3
5709 sources. */
5710 goto duplicate;
5711 }
e2ec9d29 5712 else
c0f3af97
L		 5713 {
5714 /* We remove the first xmm0 and keep the number of
5715 operands unchanged, which in fact duplicates the
5716 destination. */
5717 for (j = 1; j < i.operands; j++)
5718 {
5719 i.op[j - 1] = i.op[j];
5720 i.types[j - 1] = i.types[j];
5721 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5722 }
5723 }
5724 }
5725 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5726 {
91d6fa6a 5727 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5728 && (i.tm.opcode_modifier.vexsources
5729 == VEX3SOURCES));
c0f3af97
L		 5730
5731 /* Add the implicit xmm0 for instructions with VEX prefix
5732 and 3 sources. */
5733 for (j = i.operands; j > 0; j--)
5734 {
5735 i.op[j] = i.op[j - 1];
5736 i.types[j] = i.types[j - 1];
5737 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5738 }
5739 i.op[0].regs
5740 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5741 i.types[0] = regxmm;
c0f3af97
L		 5742 i.tm.operand_types[0] = regxmm;
5743
5744 i.operands += 2;
5745 i.reg_operands += 2;
5746 i.tm.operands += 2;
5747
91d6fa6a 5748 dupl++;
c0f3af97 5749 dest++;
91d6fa6a
NC		 5750 i.op[dupl] = i.op[dest];
5751 i.types[dupl] = i.types[dest];
5752 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5753 }
c0f3af97
L		 5754 else
5755 {
5756duplicate:
5757 i.operands++;
5758 i.reg_operands++;
5759 i.tm.operands++;
5760
91d6fa6a
NC		 5761 i.op[dupl] = i.op[dest];
5762 i.types[dupl] = i.types[dest];
5763 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5764 }
5765
5766 if (i.tm.opcode_modifier.immext)
5767 process_immext ();
5768 }
5769 else if (i.tm.opcode_modifier.firstxmm0)
5770 {
5771 unsigned int j;
5772
43234a1e 5773 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5774 gas_assert (i.reg_operands
7ab9ffdd 5775 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5776 || operand_type_equal (&i.types[0], &regymm)
5777 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5778 if (register_number (i.op[0].regs) != 0)
c0f3af97 5779 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5780
5781 for (j = 1; j < i.operands; j++)
5782 {
5783 i.op[j - 1] = i.op[j];
5784 i.types[j - 1] = i.types[j];
5785
5786 /* We need to adjust fields in i.tm since they are used by
5787 build_modrm_byte. */
5788 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5789 }
5790
e2ec9d29
L		 5791 i.operands--;
5792 i.reg_operands--;
e2ec9d29
L		 5793 i.tm.operands--;
5794 }
5795 else if (i.tm.opcode_modifier.regkludge)
5796 {
5797 /* The imul $imm, %reg instruction is converted into
5798 imul $imm, %reg, %reg, and the clr %reg instruction
5799 is converted into xor %reg, %reg. */
5800
5801 unsigned int first_reg_op;
5802
5803 if (operand_type_check (i.types[0], reg))
5804 first_reg_op = 0;
5805 else
5806 first_reg_op = 1;
5807 /* Pretend we saw the extra register operand. */
9c2799c2 5808 gas_assert (i.reg_operands == 1
7ab9ffdd 5809 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5810 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5811 i.types[first_reg_op + 1] = i.types[first_reg_op];
5812 i.operands++;
5813 i.reg_operands++;
29b0f896
AM		 5814 }
5815
40fb9820 5816 if (i.tm.opcode_modifier.shortform)
29b0f896 5817 {
40fb9820
L		 5818 if (i.types[0].bitfield.sreg2
5819 || i.types[0].bitfield.sreg3)
29b0f896 5820 {
4eed87de
AM		 5821 if (i.tm.base_opcode == POP_SEG_SHORT
5822 && i.op[0].regs->reg_num == 1)
29b0f896 5823 {
a87af027 5824 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5825 return 0;
29b0f896 5826 }
4eed87de
AM		 5827 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5828 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5829 i.rex |= REX_B;
4eed87de
AM		 5830 }
5831 else
5832 {
7ab9ffdd 5833 /* The register or float register operand is in operand
85f10a01 5834 0 or 1. */
40fb9820 5835 unsigned int op;
7ab9ffdd
L		 5836
5837 if (i.types[0].bitfield.floatreg
5838 || operand_type_check (i.types[0], reg))
5839 op = 0;
5840 else
5841 op = 1;
4eed87de
AM		 5842 /* Register goes in low 3 bits of opcode. */
5843 i.tm.base_opcode |= i.op[op].regs->reg_num;
5844 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5845 i.rex |= REX_B;
40fb9820 5846 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5847 {
4eed87de
AM		 5848 /* Warn about some common errors, but press on regardless.
5849 The first case can be generated by gcc (<= 2.8.1). */
5850 if (i.operands == 2)
5851 {
5852 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5853 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5854 register_prefix, i.op[!intel_syntax].regs->reg_name,
5855 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5856 }
5857 else
5858 {
5859 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5860 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5861 register_prefix, i.op[0].regs->reg_name);
4eed87de 5862 }
29b0f896
AM		 5863 }
5864 }
5865 }
40fb9820 5866 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5867 {
5868 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5869 must be put into the modrm byte). Now, we make the modrm and
5870 index base bytes based on all the info we've collected. */
29b0f896
AM		 5871
5872 default_seg = build_modrm_byte ();
5873 }
8a2ed489 5874 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5875 {
5876 default_seg = &ds;
5877 }
40fb9820 5878 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5879 {
5880 /* For the string instructions that allow a segment override
5881 on one of their operands, the default segment is ds. */
5882 default_seg = &ds;
5883 }
5884
75178d9d
L		 5885 if (i.tm.base_opcode == 0x8d /* lea */
5886 && i.seg[0]
5887 && !quiet_warnings)
30123838 5888 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5889
5890 /* If a segment was explicitly specified, and the specified segment
5891 is not the default, use an opcode prefix to select it. If we
5892 never figured out what the default segment is, then default_seg
5893 will be zero at this point, and the specified segment prefix will
5894 always be used. */
29b0f896
AM		 5895 if ((i.seg[0]) && (i.seg[0] != default_seg))
5896 {
5897 if (!add_prefix (i.seg[0]->seg_prefix))
5898 return 0;
5899 }
5900 return 1;
5901}
5902
5903static const seg_entry *
e3bb37b5 5904build_modrm_byte (void)
29b0f896
AM		 5905{
5906 const seg_entry *default_seg = 0;
c0f3af97 5907 unsigned int source, dest;
8cd7925b 5908 int vex_3_sources;
c0f3af97
L		 5909
5910 /* The first operand of instructions with VEX prefix and 3 sources
5911 must be VEX_Imm4. */
8cd7925b 5912 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5913 if (vex_3_sources)
5914 {
91d6fa6a 5915 unsigned int nds, reg_slot;
4c2c6516 5916 expressionS *exp;
c0f3af97 5917
922d8de8 5918 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5919 && i.tm.opcode_modifier.immext)
5920 {
5921 dest = i.operands - 2;
5922 gas_assert (dest == 3);
5923 }
922d8de8 5924 else
a683cc34 5925 dest = i.operands - 1;
c0f3af97 5926 nds = dest - 1;
922d8de8 5927
a683cc34
SP		 5928 /* There are 2 kinds of instructions:
5929 1. 5 operands: 4 register operands or 3 register operands
5930 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 5931 VexW0 or VexW1. The destination must be either XMM, YMM or
5932 ZMM register.
a683cc34
SP		 5933 2. 4 operands: 4 register operands or 3 register operands
5934 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5935 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5936 || (i.reg_operands == 3 && i.mem_operands == 1))
5937 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5938 && (i.tm.opcode_modifier.veximmext
5939 || (i.imm_operands == 1
5940 && i.types[0].bitfield.vec_imm4
5941 && (i.tm.opcode_modifier.vexw == VEXW0
5942 || i.tm.opcode_modifier.vexw == VEXW1)
5943 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 5944 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
5945 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 5946
5947 if (i.imm_operands == 0)
5948 {
5949 /* When there is no immediate operand, generate an 8bit
5950 immediate operand to encode the first operand. */
5951 exp = &im_expressions[i.imm_operands++];
5952 i.op[i.operands].imms = exp;
5953 i.types[i.operands] = imm8;
5954 i.operands++;
5955 /* If VexW1 is set, the first operand is the source and
5956 the second operand is encoded in the immediate operand. */
5957 if (i.tm.opcode_modifier.vexw == VEXW1)
5958 {
5959 source = 0;
5960 reg_slot = 1;
5961 }
5962 else
5963 {
5964 source = 1;
5965 reg_slot = 0;
5966 }
5967
5968 /* FMA swaps REG and NDS. */
5969 if (i.tm.cpu_flags.bitfield.cpufma)
5970 {
5971 unsigned int tmp;
5972 tmp = reg_slot;
5973 reg_slot = nds;
5974 nds = tmp;
5975 }
5976
24981e7b
L		 5977 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5978 &regxmm)
a683cc34 5979 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 5980 &regymm)
5981 || operand_type_equal (&i.tm.operand_types[reg_slot],
5982 &regzmm));
a683cc34 5983 exp->X_op = O_constant;
4c692bc7 5984 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 5985 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
5986 }
922d8de8 5987 else
a683cc34
SP		 5988 {
5989 unsigned int imm_slot;
5990
5991 if (i.tm.opcode_modifier.vexw == VEXW0)
5992 {
5993 /* If VexW0 is set, the third operand is the source and
5994 the second operand is encoded in the immediate
5995 operand. */
5996 source = 2;
5997 reg_slot = 1;
5998 }
5999 else
6000 {
6001 /* VexW1 is set, the second operand is the source and
6002 the third operand is encoded in the immediate
6003 operand. */
6004 source = 1;
6005 reg_slot = 2;
6006 }
6007
6008 if (i.tm.opcode_modifier.immext)
6009 {
6010 /* When ImmExt is set, the immdiate byte is the last
6011 operand. */
6012 imm_slot = i.operands - 1;
6013 source--;
6014 reg_slot--;
6015 }
6016 else
6017 {
6018 imm_slot = 0;
6019
6020 /* Turn on Imm8 so that output_imm will generate it. */
6021 i.types[imm_slot].bitfield.imm8 = 1;
6022 }
6023
24981e7b
L		 6024 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6025 &regxmm)
6026 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6027 &regymm)
6028 || operand_type_equal (&i.tm.operand_types[reg_slot],
6029 &regzmm));
a683cc34 6030 i.op[imm_slot].imms->X_add_number
4c692bc7 6031 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6032 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6033 }
6034
6035 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6036 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6037 &regymm)
6038 || operand_type_equal (&i.tm.operand_types[nds],
6039 &regzmm));
dae39acc 6040 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6041 }
6042 else
6043 source = dest = 0;
29b0f896
AM		 6044
6045 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6046 implicit registers do not count. If there are 3 register
6047 operands, it must be a instruction with VexNDS. For a
6048 instruction with VexNDD, the destination register is encoded
6049 in VEX prefix. If there are 4 register operands, it must be
6050 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6051 if (i.mem_operands == 0
6052 && ((i.reg_operands == 2
2426c15f 6053 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6054 || (i.reg_operands == 3
2426c15f 6055 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6056 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6057 {
cab737b9
L		 6058 switch (i.operands)
6059 {
6060 case 2:
6061 source = 0;
6062 break;
6063 case 3:
c81128dc
L		 6064 /* When there are 3 operands, one of them may be immediate,
6065 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6066 the first operand must be shift count register (cl) or it
6067 is an instruction with VexNDS. */
9c2799c2 6068 gas_assert (i.imm_operands == 1
7ab9ffdd 6069 || (i.imm_operands == 0
2426c15f 6070 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6071 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6072 if (operand_type_check (i.types[0], imm)
6073 || i.types[0].bitfield.shiftcount)
6074 source = 1;
6075 else
6076 source = 0;
cab737b9
L		 6077 break;
6078 case 4:
368d64cc
L		 6079 /* When there are 4 operands, the first two must be 8bit
6080 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6081 one.
6082
6083 For instructions with VexNDS, if the first operand
6084 an imm8, the source operand is the 2nd one. If the last
6085 operand is imm8, the source operand is the first one. */
9c2799c2 6086 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6087 && i.types[0].bitfield.imm8
6088 && i.types[1].bitfield.imm8)
2426c15f 6089 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6090 && i.imm_operands == 1
6091 && (i.types[0].bitfield.imm8
43234a1e
L		 6092 || i.types[i.operands - 1].bitfield.imm8
6093 || i.rounding)));
9f2670f2
L		 6094 if (i.imm_operands == 2)
6095 source = 2;
6096 else
c0f3af97
L		 6097 {
6098 if (i.types[0].bitfield.imm8)
6099 source = 1;
6100 else
6101 source = 0;
6102 }
c0f3af97
L		 6103 break;
6104 case 5:
43234a1e
L		 6105 if (i.tm.opcode_modifier.evex)
6106 {
6107 /* For EVEX instructions, when there are 5 operands, the
6108 first one must be immediate operand. If the second one
6109 is immediate operand, the source operand is the 3th
6110 one. If the last one is immediate operand, the source
6111 operand is the 2nd one. */
6112 gas_assert (i.imm_operands == 2
6113 && i.tm.opcode_modifier.sae
6114 && operand_type_check (i.types[0], imm));
6115 if (operand_type_check (i.types[1], imm))
6116 source = 2;
6117 else if (operand_type_check (i.types[4], imm))
6118 source = 1;
6119 else
6120 abort ();
6121 }
cab737b9
L		 6122 break;
6123 default:
6124 abort ();
6125 }
6126
c0f3af97
L		 6127 if (!vex_3_sources)
6128 {
6129 dest = source + 1;
6130
43234a1e
L		 6131 /* RC/SAE operand could be between DEST and SRC. That happens
6132 when one operand is GPR and the other one is XMM/YMM/ZMM
6133 register. */
6134 if (i.rounding && i.rounding->operand == (int) dest)
6135 dest++;
6136
2426c15f 6137 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6138 {
43234a1e
L		 6139 /* For instructions with VexNDS, the register-only source
6140 operand must be 32/64bit integer, XMM, YMM or ZMM
6141 register. It is encoded in VEX prefix. We need to
6142 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6143
6144 i386_operand_type op;
6145 unsigned int vvvv;
6146
6147 /* Check register-only source operand when two source
6148 operands are swapped. */
6149 if (!i.tm.operand_types[source].bitfield.baseindex
6150 && i.tm.operand_types[dest].bitfield.baseindex)
6151 {
6152 vvvv = source;
6153 source = dest;
6154 }
6155 else
6156 vvvv = dest;
6157
6158 op = i.tm.operand_types[vvvv];
fa99fab2 6159 op.bitfield.regmem = 0;
c0f3af97 6160 if ((dest + 1) >= i.operands
f12dc422
L		 6161 || (op.bitfield.reg32 != 1
6162 && !op.bitfield.reg64 != 1
6163 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6164 && !operand_type_equal (&op, &regymm)
6165 && !operand_type_equal (&op, &regzmm)
6166 && !operand_type_equal (&op, &regmask)))
c0f3af97 6167 abort ();
f12dc422 6168 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6169 dest++;
6170 }
6171 }
29b0f896
AM		 6172
6173 i.rm.mode = 3;
6174 /* One of the register operands will be encoded in the i.tm.reg
6175 field, the other in the combined i.tm.mode and i.tm.regmem
6176 fields. If no form of this instruction supports a memory
6177 destination operand, then we assume the source operand may
6178 sometimes be a memory operand and so we need to store the
6179 destination in the i.rm.reg field. */
40fb9820
L		 6180 if (!i.tm.operand_types[dest].bitfield.regmem
6181 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6182 {
6183 i.rm.reg = i.op[dest].regs->reg_num;
6184 i.rm.regmem = i.op[source].regs->reg_num;
6185 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6186 i.rex |= REX_R;
43234a1e
L		 6187 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6188 i.vrex |= REX_R;
29b0f896 6189 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6190 i.rex |= REX_B;
43234a1e
L		 6191 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6192 i.vrex |= REX_B;
29b0f896
AM		 6193 }
6194 else
6195 {
6196 i.rm.reg = i.op[source].regs->reg_num;
6197 i.rm.regmem = i.op[dest].regs->reg_num;
6198 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6199 i.rex |= REX_B;
43234a1e
L		 6200 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6201 i.vrex |= REX_B;
29b0f896 6202 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6203 i.rex |= REX_R;
43234a1e
L		 6204 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6205 i.vrex |= REX_R;
29b0f896 6206 }
161a04f6 6207 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6208 {
40fb9820
L		 6209 if (!i.types[0].bitfield.control
6210 && !i.types[1].bitfield.control)
c4a530c5 6211 abort ();
161a04f6 6212 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6213 add_prefix (LOCK_PREFIX_OPCODE);
6214 }
29b0f896
AM		 6215 }
6216 else
6217 { /* If it's not 2 reg operands... */
c0f3af97
L		 6218 unsigned int mem;
6219
29b0f896
AM		 6220 if (i.mem_operands)
6221 {
6222 unsigned int fake_zero_displacement = 0;
99018f42 6223 unsigned int op;
4eed87de 6224
7ab9ffdd
L		 6225 for (op = 0; op < i.operands; op++)
6226 if (operand_type_check (i.types[op], anymem))
6227 break;
7ab9ffdd 6228 gas_assert (op < i.operands);
29b0f896 6229
6c30d220
L		 6230 if (i.tm.opcode_modifier.vecsib)
6231 {
6232 if (i.index_reg->reg_num == RegEiz
6233 || i.index_reg->reg_num == RegRiz)
6234 abort ();
6235
6236 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6237 if (!i.base_reg)
6238 {
6239 i.sib.base = NO_BASE_REGISTER;
6240 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6241 /* No Vec_Disp8 if there is no base. */
6242 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6243 i.types[op].bitfield.disp8 = 0;
6244 i.types[op].bitfield.disp16 = 0;
6245 i.types[op].bitfield.disp64 = 0;
6246 if (flag_code != CODE_64BIT)
6247 {
6248 /* Must be 32 bit */
6249 i.types[op].bitfield.disp32 = 1;
6250 i.types[op].bitfield.disp32s = 0;
6251 }
6252 else
6253 {
6254 i.types[op].bitfield.disp32 = 0;
6255 i.types[op].bitfield.disp32s = 1;
6256 }
6257 }
6258 i.sib.index = i.index_reg->reg_num;
6259 if ((i.index_reg->reg_flags & RegRex) != 0)
6260 i.rex |= REX_X;
43234a1e
L		 6261 if ((i.index_reg->reg_flags & RegVRex) != 0)
6262 i.vrex |= REX_X;
6c30d220
L		 6263 }
6264
29b0f896
AM		 6265 default_seg = &ds;
6266
6267 if (i.base_reg == 0)
6268 {
6269 i.rm.mode = 0;
6270 if (!i.disp_operands)
6c30d220
L		 6271 {
6272 fake_zero_displacement = 1;
6273 /* Instructions with VSIB byte need 32bit displacement
6274 if there is no base register. */
6275 if (i.tm.opcode_modifier.vecsib)
6276 i.types[op].bitfield.disp32 = 1;
6277 }
29b0f896
AM		 6278 if (i.index_reg == 0)
6279 {
6c30d220 6280 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6281 /* Operand is just <disp> */
20f0a1fc 6282 if (flag_code == CODE_64BIT)
29b0f896
AM		 6283 {
6284 /* 64bit mode overwrites the 32bit absolute
6285 addressing by RIP relative addressing and
6286 absolute addressing is encoded by one of the
6287 redundant SIB forms. */
6288 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6289 i.sib.base = NO_BASE_REGISTER;
6290 i.sib.index = NO_INDEX_REGISTER;
fc225355 6291 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6292 ? disp32s : disp32);
20f0a1fc 6293 }
fc225355
L		 6294 else if ((flag_code == CODE_16BIT)
6295 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6296 {
6297 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6298 i.types[op] = disp16;
20f0a1fc
NC		 6299 }
6300 else
6301 {
6302 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6303 i.types[op] = disp32;
29b0f896
AM		 6304 }
6305 }
6c30d220 6306 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6307 {
6c30d220 6308 /* !i.base_reg && i.index_reg */
db51cc60
L		 6309 if (i.index_reg->reg_num == RegEiz
6310 || i.index_reg->reg_num == RegRiz)
6311 i.sib.index = NO_INDEX_REGISTER;
6312 else
6313 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6314 i.sib.base = NO_BASE_REGISTER;
6315 i.sib.scale = i.log2_scale_factor;
6316 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6317 /* No Vec_Disp8 if there is no base. */
6318 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6319 i.types[op].bitfield.disp8 = 0;
6320 i.types[op].bitfield.disp16 = 0;
6321 i.types[op].bitfield.disp64 = 0;
29b0f896 6322 if (flag_code != CODE_64BIT)
40fb9820
L		 6323 {
6324 /* Must be 32 bit */
6325 i.types[op].bitfield.disp32 = 1;
6326 i.types[op].bitfield.disp32s = 0;
6327 }
29b0f896 6328 else
40fb9820
L		 6329 {
6330 i.types[op].bitfield.disp32 = 0;
6331 i.types[op].bitfield.disp32s = 1;
6332 }
29b0f896 6333 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6334 i.rex |= REX_X;
29b0f896
AM		 6335 }
6336 }
6337 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6338 else if (i.base_reg->reg_num == RegRip ||
6339 i.base_reg->reg_num == RegEip)
29b0f896 6340 {
6c30d220 6341 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6342 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6343 i.types[op].bitfield.disp8 = 0;
6344 i.types[op].bitfield.disp16 = 0;
6345 i.types[op].bitfield.disp32 = 0;
6346 i.types[op].bitfield.disp32s = 1;
6347 i.types[op].bitfield.disp64 = 0;
43234a1e 6348 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6349 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6350 if (! i.disp_operands)
6351 fake_zero_displacement = 1;
29b0f896 6352 }
40fb9820 6353 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6354 {
6c30d220 6355 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6356 switch (i.base_reg->reg_num)
6357 {
6358 case 3: /* (%bx) */
6359 if (i.index_reg == 0)
6360 i.rm.regmem = 7;
6361 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6362 i.rm.regmem = i.index_reg->reg_num - 6;
6363 break;
6364 case 5: /* (%bp) */
6365 default_seg = &ss;
6366 if (i.index_reg == 0)
6367 {
6368 i.rm.regmem = 6;
40fb9820 6369 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6370 {
6371 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6372 if (i.tm.operand_types[op].bitfield.vec_disp8)
6373 i.types[op].bitfield.vec_disp8 = 1;
6374 else
6375 i.types[op].bitfield.disp8 = 1;
252b5132 6376 fake_zero_displacement = 1;
29b0f896
AM		 6377 }
6378 }
6379 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6380 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6381 break;
6382 default: /* (%si) -> 4 or (%di) -> 5 */
6383 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6384 }
6385 i.rm.mode = mode_from_disp_size (i.types[op]);
6386 }
6387 else /* i.base_reg and 32/64 bit mode */
6388 {
6389 if (flag_code == CODE_64BIT
40fb9820
L		 6390 && operand_type_check (i.types[op], disp))
6391 {
6392 i386_operand_type temp;
0dfbf9d7 6393 operand_type_set (&temp, 0);
40fb9820 6394 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6395 temp.bitfield.vec_disp8
6396 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6397 i.types[op] = temp;
6398 if (i.prefix[ADDR_PREFIX] == 0)
6399 i.types[op].bitfield.disp32s = 1;
6400 else
6401 i.types[op].bitfield.disp32 = 1;
6402 }
20f0a1fc 6403
6c30d220
L		 6404 if (!i.tm.opcode_modifier.vecsib)
6405 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6406 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6407 i.rex |= REX_B;
29b0f896
AM		 6408 i.sib.base = i.base_reg->reg_num;
6409 /* x86-64 ignores REX prefix bit here to avoid decoder
6410 complications. */
848930b2
JB		 6411 if (!(i.base_reg->reg_flags & RegRex)
6412 && (i.base_reg->reg_num == EBP_REG_NUM
6413 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6414 default_seg = &ss;
848930b2 6415 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6416 {
848930b2 6417 fake_zero_displacement = 1;
43234a1e
L		 6418 if (i.tm.operand_types [op].bitfield.vec_disp8)
6419 i.types[op].bitfield.vec_disp8 = 1;
6420 else
6421 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6422 }
6423 i.sib.scale = i.log2_scale_factor;
6424 if (i.index_reg == 0)
6425 {
6c30d220 6426 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6427 /* <disp>(%esp) becomes two byte modrm with no index
6428 register. We've already stored the code for esp
6429 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6430 Any base register besides %esp will not use the
6431 extra modrm byte. */
6432 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6433 }
6c30d220 6434 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6435 {
db51cc60
L		 6436 if (i.index_reg->reg_num == RegEiz
6437 || i.index_reg->reg_num == RegRiz)
6438 i.sib.index = NO_INDEX_REGISTER;
6439 else
6440 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6441 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6442 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6443 i.rex |= REX_X;
29b0f896 6444 }
67a4f2b7
AO		 6445
6446 if (i.disp_operands
6447 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6448 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6449 i.rm.mode = 0;
6450 else
a501d77e
L		 6451 {
6452 if (!fake_zero_displacement
6453 && !i.disp_operands
6454 && i.disp_encoding)
6455 {
6456 fake_zero_displacement = 1;
6457 if (i.disp_encoding == disp_encoding_8bit)
6458 i.types[op].bitfield.disp8 = 1;
6459 else
6460 i.types[op].bitfield.disp32 = 1;
6461 }
6462 i.rm.mode = mode_from_disp_size (i.types[op]);
6463 }
29b0f896 6464 }
252b5132 6465
29b0f896
AM		 6466 if (fake_zero_displacement)
6467 {
6468 /* Fakes a zero displacement assuming that i.types[op]
6469 holds the correct displacement size. */
6470 expressionS *exp;
6471
9c2799c2 6472 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6473 exp = &disp_expressions[i.disp_operands++];
6474 i.op[op].disps = exp;
6475 exp->X_op = O_constant;
6476 exp->X_add_number = 0;
6477 exp->X_add_symbol = (symbolS *) 0;
6478 exp->X_op_symbol = (symbolS *) 0;
6479 }
c0f3af97
L		 6480
6481 mem = op;
29b0f896 6482 }
c0f3af97
L		 6483 else
6484 mem = ~0;
252b5132 6485
8c43a48b 6486 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6487 {
6488 if (operand_type_check (i.types[0], imm))
6489 i.vex.register_specifier = NULL;
6490 else
6491 {
6492 /* VEX.vvvv encodes one of the sources when the first
6493 operand is not an immediate. */
1ef99a7b 6494 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6495 i.vex.register_specifier = i.op[0].regs;
6496 else
6497 i.vex.register_specifier = i.op[1].regs;
6498 }
6499
6500 /* Destination is a XMM register encoded in the ModRM.reg
6501 and VEX.R bit. */
6502 i.rm.reg = i.op[2].regs->reg_num;
6503 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6504 i.rex |= REX_R;
6505
6506 /* ModRM.rm and VEX.B encodes the other source. */
6507 if (!i.mem_operands)
6508 {
6509 i.rm.mode = 3;
6510
1ef99a7b 6511 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6512 i.rm.regmem = i.op[1].regs->reg_num;
6513 else
6514 i.rm.regmem = i.op[0].regs->reg_num;
6515
6516 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6517 i.rex |= REX_B;
6518 }
6519 }
2426c15f 6520 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6521 {
6522 i.vex.register_specifier = i.op[2].regs;
6523 if (!i.mem_operands)
6524 {
6525 i.rm.mode = 3;
6526 i.rm.regmem = i.op[1].regs->reg_num;
6527 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6528 i.rex |= REX_B;
6529 }
6530 }
29b0f896
AM		 6531 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6532 (if any) based on i.tm.extension_opcode. Again, we must be
6533 careful to make sure that segment/control/debug/test/MMX
6534 registers are coded into the i.rm.reg field. */
f88c9eb0 6535 else if (i.reg_operands)
29b0f896 6536 {
99018f42 6537 unsigned int op;
7ab9ffdd
L		 6538 unsigned int vex_reg = ~0;
6539
6540 for (op = 0; op < i.operands; op++)
6541 if (i.types[op].bitfield.reg8
6542 || i.types[op].bitfield.reg16
6543 || i.types[op].bitfield.reg32
6544 || i.types[op].bitfield.reg64
6545 || i.types[op].bitfield.regmmx
6546 || i.types[op].bitfield.regxmm
6547 || i.types[op].bitfield.regymm
7e8b059b 6548 || i.types[op].bitfield.regbnd
43234a1e
L		 6549 || i.types[op].bitfield.regzmm
6550 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6551 || i.types[op].bitfield.sreg2
6552 || i.types[op].bitfield.sreg3
6553 || i.types[op].bitfield.control
6554 || i.types[op].bitfield.debug
6555 || i.types[op].bitfield.test)
6556 break;
c0209578 6557
7ab9ffdd
L		 6558 if (vex_3_sources)
6559 op = dest;
2426c15f 6560 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6561 {
6562 /* For instructions with VexNDS, the register-only
6563 source operand is encoded in VEX prefix. */
6564 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6565
7ab9ffdd 6566 if (op > mem)
c0f3af97 6567 {
7ab9ffdd
L		 6568 vex_reg = op++;
6569 gas_assert (op < i.operands);
c0f3af97
L		 6570 }
6571 else
c0f3af97 6572 {
f12dc422
L		 6573 /* Check register-only source operand when two source
6574 operands are swapped. */
6575 if (!i.tm.operand_types[op].bitfield.baseindex
6576 && i.tm.operand_types[op + 1].bitfield.baseindex)
6577 {
6578 vex_reg = op;
6579 op += 2;
6580 gas_assert (mem == (vex_reg + 1)
6581 && op < i.operands);
6582 }
6583 else
6584 {
6585 vex_reg = op + 1;
6586 gas_assert (vex_reg < i.operands);
6587 }
c0f3af97 6588 }
7ab9ffdd 6589 }
2426c15f 6590 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6591 {
f12dc422 6592 /* For instructions with VexNDD, the register destination
7ab9ffdd 6593 is encoded in VEX prefix. */
f12dc422
L		 6594 if (i.mem_operands == 0)
6595 {
6596 /* There is no memory operand. */
6597 gas_assert ((op + 2) == i.operands);
6598 vex_reg = op + 1;
6599 }
6600 else
8d63c93e 6601 {
f12dc422
L		 6602 /* There are only 2 operands. */
6603 gas_assert (op < 2 && i.operands == 2);
6604 vex_reg = 1;
6605 }
7ab9ffdd
L		 6606 }
6607 else
6608 gas_assert (op < i.operands);
99018f42 6609
7ab9ffdd
L		 6610 if (vex_reg != (unsigned int) ~0)
6611 {
f12dc422 6612 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6613
f12dc422
L		 6614 if (type->bitfield.reg32 != 1
6615 && type->bitfield.reg64 != 1
6616 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6617 && !operand_type_equal (type, &regymm)
6618 && !operand_type_equal (type, &regzmm)
6619 && !operand_type_equal (type, &regmask))
7ab9ffdd 6620 abort ();
f88c9eb0 6621
7ab9ffdd
L		 6622 i.vex.register_specifier = i.op[vex_reg].regs;
6623 }
6624
1b9f0c97
L		 6625 /* Don't set OP operand twice. */
6626 if (vex_reg != op)
7ab9ffdd 6627 {
1b9f0c97
L		 6628 /* If there is an extension opcode to put here, the
6629 register number must be put into the regmem field. */
6630 if (i.tm.extension_opcode != None)
6631 {
6632 i.rm.regmem = i.op[op].regs->reg_num;
6633 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6634 i.rex |= REX_B;
43234a1e
L		 6635 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6636 i.vrex |= REX_B;
1b9f0c97
L		 6637 }
6638 else
6639 {
6640 i.rm.reg = i.op[op].regs->reg_num;
6641 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6642 i.rex |= REX_R;
43234a1e
L		 6643 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6644 i.vrex |= REX_R;
1b9f0c97 6645 }
7ab9ffdd 6646 }
252b5132 6647
29b0f896
AM		 6648 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6649 must set it to 3 to indicate this is a register operand
6650 in the regmem field. */
6651 if (!i.mem_operands)
6652 i.rm.mode = 3;
6653 }
252b5132 6654
29b0f896 6655 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6656 if (i.tm.extension_opcode != None)
29b0f896
AM		 6657 i.rm.reg = i.tm.extension_opcode;
6658 }
6659 return default_seg;
6660}
252b5132 6661
29b0f896 6662static void
e3bb37b5 6663output_branch (void)
29b0f896
AM		 6664{
6665 char *p;
f8a5c266 6666 int size;
29b0f896
AM		 6667 int code16;
6668 int prefix;
6669 relax_substateT subtype;
6670 symbolS *sym;
6671 offsetT off;
6672
f8a5c266 6673 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6674 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6675
6676 prefix = 0;
6677 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6678 {
29b0f896
AM		 6679 prefix = 1;
6680 i.prefixes -= 1;
6681 code16 ^= CODE16;
252b5132 6682 }
29b0f896
AM		 6683 /* Pentium4 branch hints. */
6684 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6685 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6686 {
29b0f896
AM		 6687 prefix++;
6688 i.prefixes--;
6689 }
6690 if (i.prefix[REX_PREFIX] != 0)
6691 {
6692 prefix++;
6693 i.prefixes--;
2f66722d
AM		 6694 }
6695
7e8b059b
L		 6696 /* BND prefixed jump. */
6697 if (i.prefix[BND_PREFIX] != 0)
6698 {
6699 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6700 i.prefixes -= 1;
6701 }
6702
29b0f896
AM		 6703 if (i.prefixes != 0 && !intel_syntax)
6704 as_warn (_("skipping prefixes on this instruction"));
6705
6706 /* It's always a symbol; End frag & setup for relax.
6707 Make sure there is enough room in this frag for the largest
6708 instruction we may generate in md_convert_frag. This is 2
6709 bytes for the opcode and room for the prefix and largest
6710 displacement. */
6711 frag_grow (prefix + 2 + 4);
6712 /* Prefix and 1 opcode byte go in fr_fix. */
6713 p = frag_more (prefix + 1);
6714 if (i.prefix[DATA_PREFIX] != 0)
6715 *p++ = DATA_PREFIX_OPCODE;
6716 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6717 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6718 *p++ = i.prefix[SEG_PREFIX];
6719 if (i.prefix[REX_PREFIX] != 0)
6720 *p++ = i.prefix[REX_PREFIX];
6721 *p = i.tm.base_opcode;
6722
6723 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6724 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6725 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6726 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6727 else
f8a5c266 6728 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6729 subtype |= code16;
3e73aa7c 6730
29b0f896
AM		 6731 sym = i.op[0].disps->X_add_symbol;
6732 off = i.op[0].disps->X_add_number;
3e73aa7c 6733
29b0f896
AM		 6734 if (i.op[0].disps->X_op != O_constant
6735 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6736 {
29b0f896
AM		 6737 /* Handle complex expressions. */
6738 sym = make_expr_symbol (i.op[0].disps);
6739 off = 0;
6740 }
3e73aa7c 6741
29b0f896
AM		 6742 /* 1 possible extra opcode + 4 byte displacement go in var part.
6743 Pass reloc in fr_var. */
c3320543
L		 6744 frag_var (rs_machine_dependent, 5,
6745 ((!object_64bit
6746 || i.reloc[0] != NO_RELOC
6747 || (i.bnd_prefix == NULL && !add_bnd_prefix))
6748 ? i.reloc[0]
6749 : BFD_RELOC_X86_64_PC32_BND),
6750 subtype, sym, off, p);
29b0f896 6751}
3e73aa7c 6752
29b0f896 6753static void
e3bb37b5 6754output_jump (void)
29b0f896
AM		 6755{
6756 char *p;
6757 int size;
3e02c1cc 6758 fixS *fixP;
29b0f896 6759
40fb9820 6760 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6761 {
6762 /* This is a loop or jecxz type instruction. */
6763 size = 1;
6764 if (i.prefix[ADDR_PREFIX] != 0)
6765 {
6766 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6767 i.prefixes -= 1;
6768 }
6769 /* Pentium4 branch hints. */
6770 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6771 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6772 {
6773 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6774 i.prefixes--;
3e73aa7c
JH		 6775 }
6776 }
29b0f896
AM		 6777 else
6778 {
6779 int code16;
3e73aa7c 6780
29b0f896
AM		 6781 code16 = 0;
6782 if (flag_code == CODE_16BIT)
6783 code16 = CODE16;
3e73aa7c 6784
29b0f896
AM		 6785 if (i.prefix[DATA_PREFIX] != 0)
6786 {
6787 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6788 i.prefixes -= 1;
6789 code16 ^= CODE16;
6790 }
252b5132 6791
29b0f896
AM		 6792 size = 4;
6793 if (code16)
6794 size = 2;
6795 }
9fcc94b6 6796
29b0f896
AM		 6797 if (i.prefix[REX_PREFIX] != 0)
6798 {
6799 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6800 i.prefixes -= 1;
6801 }
252b5132 6802
7e8b059b
L		 6803 /* BND prefixed jump. */
6804 if (i.prefix[BND_PREFIX] != 0)
6805 {
6806 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6807 i.prefixes -= 1;
6808 }
6809
29b0f896
AM		 6810 if (i.prefixes != 0 && !intel_syntax)
6811 as_warn (_("skipping prefixes on this instruction"));
e0890092 6812
42164a71
L		 6813 p = frag_more (i.tm.opcode_length + size);
6814 switch (i.tm.opcode_length)
6815 {
6816 case 2:
6817 *p++ = i.tm.base_opcode >> 8;
6818 case 1:
6819 *p++ = i.tm.base_opcode;
6820 break;
6821 default:
6822 abort ();
6823 }
e0890092 6824
3e02c1cc 6825 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
c3320543
L		 6826 i.op[0].disps, 1, reloc (size, 1, 1,
6827 (i.bnd_prefix != NULL
6828 || add_bnd_prefix),
6829 i.reloc[0]));
3e02c1cc
AM		 6830
6831 /* All jumps handled here are signed, but don't use a signed limit
6832 check for 32 and 16 bit jumps as we want to allow wrap around at
6833 4G and 64k respectively. */
6834 if (size == 1)
6835 fixP->fx_signed = 1;
29b0f896 6836}
e0890092 6837
29b0f896 6838static void
e3bb37b5 6839output_interseg_jump (void)
29b0f896
AM		 6840{
6841 char *p;
6842 int size;
6843 int prefix;
6844 int code16;
252b5132 6845
29b0f896
AM		 6846 code16 = 0;
6847 if (flag_code == CODE_16BIT)
6848 code16 = CODE16;
a217f122 6849
29b0f896
AM		 6850 prefix = 0;
6851 if (i.prefix[DATA_PREFIX] != 0)
6852 {
6853 prefix = 1;
6854 i.prefixes -= 1;
6855 code16 ^= CODE16;
6856 }
6857 if (i.prefix[REX_PREFIX] != 0)
6858 {
6859 prefix++;
6860 i.prefixes -= 1;
6861 }
252b5132 6862
29b0f896
AM		 6863 size = 4;
6864 if (code16)
6865 size = 2;
252b5132 6866
29b0f896
AM		 6867 if (i.prefixes != 0 && !intel_syntax)
6868 as_warn (_("skipping prefixes on this instruction"));
252b5132 6869
29b0f896
AM		 6870 /* 1 opcode; 2 segment; offset */
6871 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6872
29b0f896
AM		 6873 if (i.prefix[DATA_PREFIX] != 0)
6874 *p++ = DATA_PREFIX_OPCODE;
252b5132 6875
29b0f896
AM		 6876 if (i.prefix[REX_PREFIX] != 0)
6877 *p++ = i.prefix[REX_PREFIX];
252b5132 6878
29b0f896
AM		 6879 *p++ = i.tm.base_opcode;
6880 if (i.op[1].imms->X_op == O_constant)
6881 {
6882 offsetT n = i.op[1].imms->X_add_number;
252b5132 6883
29b0f896
AM		 6884 if (size == 2
6885 && !fits_in_unsigned_word (n)
6886 && !fits_in_signed_word (n))
6887 {
6888 as_bad (_("16-bit jump out of range"));
6889 return;
6890 }
6891 md_number_to_chars (p, n, size);
6892 }
6893 else
6894 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
c3320543 6895 i.op[1].imms, 0, reloc (size, 0, 0, 0, i.reloc[1]));
29b0f896
AM		 6896 if (i.op[0].imms->X_op != O_constant)
6897 as_bad (_("can't handle non absolute segment in `%s'"),
6898 i.tm.name);
6899 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6900}
a217f122 6901
29b0f896 6902static void
e3bb37b5 6903output_insn (void)
29b0f896 6904{
2bbd9c25
JJ		 6905 fragS *insn_start_frag;
6906 offsetT insn_start_off;
6907
29b0f896
AM		 6908 /* Tie dwarf2 debug info to the address at the start of the insn.
6909 We can't do this after the insn has been output as the current
6910 frag may have been closed off. eg. by frag_var. */
6911 dwarf2_emit_insn (0);
6912
2bbd9c25
JJ		 6913 insn_start_frag = frag_now;
6914 insn_start_off = frag_now_fix ();
6915
29b0f896 6916 /* Output jumps. */
40fb9820 6917 if (i.tm.opcode_modifier.jump)
29b0f896 6918 output_branch ();
40fb9820
L		 6919 else if (i.tm.opcode_modifier.jumpbyte
6920 || i.tm.opcode_modifier.jumpdword)
29b0f896 6921 output_jump ();
40fb9820 6922 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6923 output_interseg_jump ();
6924 else
6925 {
6926 /* Output normal instructions here. */
6927 char *p;
6928 unsigned char *q;
47465058 6929 unsigned int j;
331d2d0d 6930 unsigned int prefix;
4dffcebc 6931
43234a1e
L		 6932 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6933 don't need the explicit prefix. */
6934 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 6935 {
c0f3af97 6936 switch (i.tm.opcode_length)
bc4bd9ab 6937 {
c0f3af97
L		 6938 case 3:
6939 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6940 {
c0f3af97
L		 6941 prefix = (i.tm.base_opcode >> 24) & 0xff;
6942 goto check_prefix;
6943 }
6944 break;
6945 case 2:
6946 if ((i.tm.base_opcode & 0xff0000) != 0)
6947 {
6948 prefix = (i.tm.base_opcode >> 16) & 0xff;
6949 if (i.tm.cpu_flags.bitfield.cpupadlock)
6950 {
4dffcebc 6951check_prefix:
c0f3af97 6952 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6953 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6954 != REPE_PREFIX_OPCODE))
6955 add_prefix (prefix);
6956 }
6957 else
4dffcebc
L		 6958 add_prefix (prefix);
6959 }
c0f3af97
L		 6960 break;
6961 case 1:
6962 break;
6963 default:
6964 abort ();
bc4bd9ab 6965 }
c0f3af97
L		 6966
6967 /* The prefix bytes. */
6968 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
6969 if (*q)
6970 FRAG_APPEND_1_CHAR (*q);
0f10071e 6971 }
ae5c1c7b 6972 else
c0f3af97
L		 6973 {
6974 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
6975 if (*q)
6976 switch (j)
6977 {
6978 case REX_PREFIX:
6979 /* REX byte is encoded in VEX prefix. */
6980 break;
6981 case SEG_PREFIX:
6982 case ADDR_PREFIX:
6983 FRAG_APPEND_1_CHAR (*q);
6984 break;
6985 default:
6986 /* There should be no other prefixes for instructions
6987 with VEX prefix. */
6988 abort ();
6989 }
6990
43234a1e
L		 6991 /* For EVEX instructions i.vrex should become 0 after
6992 build_evex_prefix. For VEX instructions upper 16 registers
6993 aren't available, so VREX should be 0. */
6994 if (i.vrex)
6995 abort ();
c0f3af97
L		 6996 /* Now the VEX prefix. */
6997 p = frag_more (i.vex.length);
6998 for (j = 0; j < i.vex.length; j++)
6999 p[j] = i.vex.bytes[j];
7000 }
252b5132 7001
29b0f896 7002 /* Now the opcode; be careful about word order here! */
4dffcebc 7003 if (i.tm.opcode_length == 1)
29b0f896
AM		 7004 {
7005 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7006 }
7007 else
7008 {
4dffcebc 7009 switch (i.tm.opcode_length)
331d2d0d 7010 {
43234a1e
L		 7011 case 4:
7012 p = frag_more (4);
7013 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7014 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7015 break;
4dffcebc 7016 case 3:
331d2d0d
L		 7017 p = frag_more (3);
7018 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7019 break;
7020 case 2:
7021 p = frag_more (2);
7022 break;
7023 default:
7024 abort ();
7025 break;
331d2d0d 7026 }
0f10071e 7027
29b0f896
AM		 7028 /* Put out high byte first: can't use md_number_to_chars! */
7029 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7030 *p = i.tm.base_opcode & 0xff;
7031 }
3e73aa7c 7032
29b0f896 7033 /* Now the modrm byte and sib byte (if present). */
40fb9820 7034 if (i.tm.opcode_modifier.modrm)
29b0f896 7035 {
4a3523fa
L		 7036 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7037 | i.rm.reg << 3
7038 | i.rm.mode << 6));
29b0f896
AM		 7039 /* If i.rm.regmem == ESP (4)
7040 && i.rm.mode != (Register mode)
7041 && not 16 bit
7042 ==> need second modrm byte. */
7043 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7044 && i.rm.mode != 3
40fb9820 7045 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7046 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7047 | i.sib.index << 3
7048 | i.sib.scale << 6));
29b0f896 7049 }
3e73aa7c 7050
29b0f896 7051 if (i.disp_operands)
2bbd9c25 7052 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7053
29b0f896 7054 if (i.imm_operands)
2bbd9c25 7055 output_imm (insn_start_frag, insn_start_off);
29b0f896 7056 }
252b5132 7057
29b0f896
AM		 7058#ifdef DEBUG386
7059 if (flag_debug)
7060 {
7b81dfbb 7061 pi ("" /*line*/, &i);
29b0f896
AM		 7062 }
7063#endif /* DEBUG386 */
7064}
252b5132 7065
e205caa7
L		 7066/* Return the size of the displacement operand N. */
7067
7068static int
7069disp_size (unsigned int n)
7070{
7071 int size = 4;
43234a1e
L		 7072
7073 /* Vec_Disp8 has to be 8bit. */
7074 if (i.types[n].bitfield.vec_disp8)
7075 size = 1;
7076 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7077 size = 8;
7078 else if (i.types[n].bitfield.disp8)
7079 size = 1;
7080 else if (i.types[n].bitfield.disp16)
7081 size = 2;
e205caa7
L		 7082 return size;
7083}
7084
7085/* Return the size of the immediate operand N. */
7086
7087static int
7088imm_size (unsigned int n)
7089{
7090 int size = 4;
40fb9820
L		 7091 if (i.types[n].bitfield.imm64)
7092 size = 8;
7093 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7094 size = 1;
7095 else if (i.types[n].bitfield.imm16)
7096 size = 2;
e205caa7
L		 7097 return size;
7098}
7099
29b0f896 7100static void
64e74474 7101output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7102{
7103 char *p;
7104 unsigned int n;
252b5132 7105
29b0f896
AM		 7106 for (n = 0; n < i.operands; n++)
7107 {
43234a1e
L		 7108 if (i.types[n].bitfield.vec_disp8
7109 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7110 {
7111 if (i.op[n].disps->X_op == O_constant)
7112 {
e205caa7 7113 int size = disp_size (n);
43234a1e 7114 offsetT val = i.op[n].disps->X_add_number;
252b5132 7115
43234a1e
L		 7116 if (i.types[n].bitfield.vec_disp8)
7117 val >>= i.memshift;
7118 val = offset_in_range (val, size);
29b0f896
AM		 7119 p = frag_more (size);
7120 md_number_to_chars (p, val, size);
7121 }
7122 else
7123 {
f86103b7 7124 enum bfd_reloc_code_real reloc_type;
e205caa7 7125 int size = disp_size (n);
40fb9820 7126 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 7127 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7128
e205caa7 7129 /* We can't have 8 bit displacement here. */
9c2799c2 7130 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7131
29b0f896
AM		 7132 /* The PC relative address is computed relative
7133 to the instruction boundary, so in case immediate
7134 fields follows, we need to adjust the value. */
7135 if (pcrel && i.imm_operands)
7136 {
29b0f896 7137 unsigned int n1;
e205caa7 7138 int sz = 0;
252b5132 7139
29b0f896 7140 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7141 if (operand_type_check (i.types[n1], imm))
252b5132 7142 {
e205caa7
L		 7143 /* Only one immediate is allowed for PC
7144 relative address. */
9c2799c2 7145 gas_assert (sz == 0);
e205caa7
L		 7146 sz = imm_size (n1);
7147 i.op[n].disps->X_add_number -= sz;
252b5132 7148 }
29b0f896 7149 /* We should find the immediate. */
9c2799c2 7150 gas_assert (sz != 0);
29b0f896 7151 }
520dc8e8 7152
29b0f896 7153 p = frag_more (size);
c3320543
L		 7154 reloc_type = reloc (size, pcrel, sign,
7155 (i.bnd_prefix != NULL
7156 || add_bnd_prefix),
7157 i.reloc[n]);
d6ab8113 7158 if (GOT_symbol
2bbd9c25 7159 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7160 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7161 || reloc_type == BFD_RELOC_X86_64_32S
7162 || (reloc_type == BFD_RELOC_64
7163 && object_64bit))
d6ab8113
JB		 7164 && (i.op[n].disps->X_op == O_symbol
7165 || (i.op[n].disps->X_op == O_add
7166 && ((symbol_get_value_expression
7167 (i.op[n].disps->X_op_symbol)->X_op)
7168 == O_subtract))))
7169 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7170 {
7171 offsetT add;
7172
7173 if (insn_start_frag == frag_now)
7174 add = (p - frag_now->fr_literal) - insn_start_off;
7175 else
7176 {
7177 fragS *fr;
7178
7179 add = insn_start_frag->fr_fix - insn_start_off;
7180 for (fr = insn_start_frag->fr_next;
7181 fr && fr != frag_now; fr = fr->fr_next)
7182 add += fr->fr_fix;
7183 add += p - frag_now->fr_literal;
7184 }
7185
4fa24527 7186 if (!object_64bit)
7b81dfbb
AJ		 7187 {
7188 reloc_type = BFD_RELOC_386_GOTPC;
7189 i.op[n].imms->X_add_number += add;
7190 }
7191 else if (reloc_type == BFD_RELOC_64)
7192 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7193 else
7b81dfbb
AJ		 7194 /* Don't do the adjustment for x86-64, as there
7195 the pcrel addressing is relative to the _next_
7196 insn, and that is taken care of in other code. */
d6ab8113 7197 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7198 }
062cd5e7 7199 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 7200 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 7201 }
7202 }
7203 }
7204}
252b5132 7205
29b0f896 7206static void
64e74474 7207output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7208{
7209 char *p;
7210 unsigned int n;
252b5132 7211
29b0f896
AM		 7212 for (n = 0; n < i.operands; n++)
7213 {
43234a1e
L		 7214 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7215 if (i.rounding && (int) n == i.rounding->operand)
7216 continue;
7217
40fb9820 7218 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7219 {
7220 if (i.op[n].imms->X_op == O_constant)
7221 {
e205caa7 7222 int size = imm_size (n);
29b0f896 7223 offsetT val;
b4cac588 7224
29b0f896
AM		 7225 val = offset_in_range (i.op[n].imms->X_add_number,
7226 size);
7227 p = frag_more (size);
7228 md_number_to_chars (p, val, size);
7229 }
7230 else
7231 {
7232 /* Not absolute_section.
7233 Need a 32-bit fixup (don't support 8bit
7234 non-absolute imms). Try to support other
7235 sizes ... */
f86103b7 7236 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7237 int size = imm_size (n);
7238 int sign;
29b0f896 7239
40fb9820 7240 if (i.types[n].bitfield.imm32s
a7d61044 7241 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7242 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7243 sign = 1;
e205caa7
L		 7244 else
7245 sign = 0;
520dc8e8 7246
29b0f896 7247 p = frag_more (size);
c3320543 7248 reloc_type = reloc (size, 0, sign, 0, i.reloc[n]);
f86103b7 7249
2bbd9c25
JJ		 7250 /* This is tough to explain. We end up with this one if we
7251 * have operands that look like
7252 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7253 * obtain the absolute address of the GOT, and it is strongly
7254 * preferable from a performance point of view to avoid using
7255 * a runtime relocation for this. The actual sequence of
7256 * instructions often look something like:
7257 *
7258 * call .L66
7259 * .L66:
7260 * popl %ebx
7261 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7262 *
7263 * The call and pop essentially return the absolute address
7264 * of the label .L66 and store it in %ebx. The linker itself
7265 * will ultimately change the first operand of the addl so
7266 * that %ebx points to the GOT, but to keep things simple, the
7267 * .o file must have this operand set so that it generates not
7268 * the absolute address of .L66, but the absolute address of
7269 * itself. This allows the linker itself simply treat a GOTPC
7270 * relocation as asking for a pcrel offset to the GOT to be
7271 * added in, and the addend of the relocation is stored in the
7272 * operand field for the instruction itself.
7273 *
7274 * Our job here is to fix the operand so that it would add
7275 * the correct offset so that %ebx would point to itself. The
7276 * thing that is tricky is that .-.L66 will point to the
7277 * beginning of the instruction, so we need to further modify
7278 * the operand so that it will point to itself. There are
7279 * other cases where you have something like:
7280 *
7281 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7282 *
7283 * and here no correction would be required. Internally in
7284 * the assembler we treat operands of this form as not being
7285 * pcrel since the '.' is explicitly mentioned, and I wonder
7286 * whether it would simplify matters to do it this way. Who
7287 * knows. In earlier versions of the PIC patches, the
7288 * pcrel_adjust field was used to store the correction, but
7289 * since the expression is not pcrel, I felt it would be
7290 * confusing to do it this way. */
7291
d6ab8113 7292 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7293 || reloc_type == BFD_RELOC_X86_64_32S
7294 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7295 && GOT_symbol
7296 && GOT_symbol == i.op[n].imms->X_add_symbol
7297 && (i.op[n].imms->X_op == O_symbol
7298 || (i.op[n].imms->X_op == O_add
7299 && ((symbol_get_value_expression
7300 (i.op[n].imms->X_op_symbol)->X_op)
7301 == O_subtract))))
7302 {
2bbd9c25
JJ		 7303 offsetT add;
7304
7305 if (insn_start_frag == frag_now)
7306 add = (p - frag_now->fr_literal) - insn_start_off;
7307 else
7308 {
7309 fragS *fr;
7310
7311 add = insn_start_frag->fr_fix - insn_start_off;
7312 for (fr = insn_start_frag->fr_next;
7313 fr && fr != frag_now; fr = fr->fr_next)
7314 add += fr->fr_fix;
7315 add += p - frag_now->fr_literal;
7316 }
7317
4fa24527 7318 if (!object_64bit)
d6ab8113 7319 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7320 else if (size == 4)
d6ab8113 7321 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7322 else if (size == 8)
7323 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7324 i.op[n].imms->X_add_number += add;
29b0f896 7325 }
29b0f896
AM		 7326 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7327 i.op[n].imms, 0, reloc_type);
7328 }
7329 }
7330 }
252b5132
RH		 7331}
7332\f
d182319b
JB		 7333/* x86_cons_fix_new is called via the expression parsing code when a
7334 reloc is needed. We use this hook to get the correct .got reloc. */
7335static enum bfd_reloc_code_real got_reloc = NO_RELOC;
7336static int cons_sign = -1;
7337
7338void
e3bb37b5 7339x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 7340 expressionS *exp)
d182319b 7341{
c3320543 7342 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, 0, got_reloc);
d182319b
JB		 7343
7344 got_reloc = NO_RELOC;
7345
7346#ifdef TE_PE
7347 if (exp->X_op == O_secrel)
7348 {
7349 exp->X_op = O_symbol;
7350 r = BFD_RELOC_32_SECREL;
7351 }
7352#endif
7353
7354 fix_new_exp (frag, off, len, exp, 0, r);
7355}
7356
357d1bd8
L		 7357/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7358 purpose of the `.dc.a' internal pseudo-op. */
7359
7360int
7361x86_address_bytes (void)
7362{
7363 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7364 return 4;
7365 return stdoutput->arch_info->bits_per_address / 8;
7366}
7367
d382c579
TG		 7368#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7369 || defined (LEX_AT)
c06ec724 7370# define lex_got(reloc, adjust, types, bnd_prefix) NULL
718ddfc0 7371#else
f3c180ae
AM		 7372/* Parse operands of the form
7373 <symbol>@GOTOFF+<nnn>
7374 and similar .plt or .got references.
7375
7376 If we find one, set up the correct relocation in RELOC and copy the
7377 input string, minus the `@GOTOFF' into a malloc'd buffer for
7378 parsing by the calling routine. Return this buffer, and if ADJUST
7379 is non-null set it to the length of the string we removed from the
7380 input line. Otherwise return NULL. */
7381static char *
91d6fa6a 7382lex_got (enum bfd_reloc_code_real *rel,
64e74474 7383 int *adjust,
c3320543
L		 7384 i386_operand_type *types,
7385 int bnd_prefix)
f3c180ae 7386{
7b81dfbb
AJ		 7387 /* Some of the relocations depend on the size of what field is to
7388 be relocated. But in our callers i386_immediate and i386_displacement
7389 we don't yet know the operand size (this will be set by insn
7390 matching). Hence we record the word32 relocation here,
7391 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7392 static const struct {
7393 const char *str;
cff8d58a 7394 int len;
4fa24527 7395 const enum bfd_reloc_code_real rel[2];
40fb9820 7396 const i386_operand_type types64;
f3c180ae 7397 } gotrel[] = {
8ce3d284 7398#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7399 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7400 BFD_RELOC_SIZE32 },
7401 OPERAND_TYPE_IMM32_64 },
8ce3d284 7402#endif
cff8d58a
L		 7403 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7404 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7405 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7406 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7407 BFD_RELOC_X86_64_PLT32 },
40fb9820 7408 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7409 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7410 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7411 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7412 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7413 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7414 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7415 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7416 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7417 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7418 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7419 BFD_RELOC_X86_64_TLSGD },
40fb9820 7420 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7421 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7422 _dummy_first_bfd_reloc_code_real },
40fb9820 7423 OPERAND_TYPE_NONE },
cff8d58a
L		 7424 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7425 BFD_RELOC_X86_64_TLSLD },
40fb9820 7426 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7427 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7428 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7429 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7430 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7431 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7432 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7433 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7434 _dummy_first_bfd_reloc_code_real },
40fb9820 7435 OPERAND_TYPE_NONE },
cff8d58a
L		 7436 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7437 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7438 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7439 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7440 _dummy_first_bfd_reloc_code_real },
40fb9820 7441 OPERAND_TYPE_NONE },
cff8d58a
L		 7442 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7443 _dummy_first_bfd_reloc_code_real },
40fb9820 7444 OPERAND_TYPE_NONE },
cff8d58a
L		 7445 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7446 BFD_RELOC_X86_64_GOT32 },
40fb9820 7447 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7448 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7449 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7450 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7451 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7452 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7453 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7454 };
7455 char *cp;
7456 unsigned int j;
7457
d382c579 7458#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7459 if (!IS_ELF)
7460 return NULL;
d382c579 7461#endif
718ddfc0 7462
f3c180ae 7463 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7464 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7465 return NULL;
7466
47465058 7467 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7468 {
cff8d58a 7469 int len = gotrel[j].len;
28f81592 7470 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7471 {
4fa24527 7472 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7473 {
28f81592
AM		 7474 int first, second;
7475 char *tmpbuf, *past_reloc;
f3c180ae 7476
91d6fa6a 7477 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7478
3956db08
JB		 7479 if (types)
7480 {
7481 if (flag_code != CODE_64BIT)
40fb9820
L		 7482 {
7483 types->bitfield.imm32 = 1;
7484 types->bitfield.disp32 = 1;
7485 }
3956db08
JB		 7486 else
7487 *types = gotrel[j].types64;
7488 }
7489
8fd4256d 7490 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7491 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7492
28f81592 7493 /* The length of the first part of our input line. */
f3c180ae 7494 first = cp - input_line_pointer;
28f81592
AM		 7495
7496 /* The second part goes from after the reloc token until
67c11a9b 7497 (and including) an end_of_line char or comma. */
28f81592 7498 past_reloc = cp + 1 + len;
67c11a9b
AM		 7499 cp = past_reloc;
7500 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7501 ++cp;
7502 second = cp + 1 - past_reloc;
28f81592
AM		 7503
7504 /* Allocate and copy string. The trailing NUL shouldn't
7505 be necessary, but be safe. */
1e9cc1c2 7506 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 7507 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7508 if (second != 0 && *past_reloc != ' ')
7509 /* Replace the relocation token with ' ', so that
7510 errors like foo@GOTOFF1 will be detected. */
7511 tmpbuf[first++] = ' ';
af89796a
L		 7512 else
7513 /* Increment length by 1 if the relocation token is
7514 removed. */
7515 len++;
7516 if (adjust)
7517 *adjust = len;
0787a12d
AM		 7518 memcpy (tmpbuf + first, past_reloc, second);
7519 tmpbuf[first + second] = '\0';
c3320543
L		 7520 if (bnd_prefix && *rel == BFD_RELOC_X86_64_PLT32)
7521 *rel = BFD_RELOC_X86_64_PLT32_BND;
f3c180ae
AM		 7522 return tmpbuf;
7523 }
7524
4fa24527
JB		 7525 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7526 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7527 return NULL;
7528 }
7529 }
7530
7531 /* Might be a symbol version string. Don't as_bad here. */
7532 return NULL;
7533}
4e4f7c87 7534#endif
f3c180ae 7535
a988325c
NC		 7536#ifdef TE_PE
7537#ifdef lex_got
7538#undef lex_got
7539#endif
7540/* Parse operands of the form
7541 <symbol>@SECREL32+<nnn>
7542
7543 If we find one, set up the correct relocation in RELOC and copy the
7544 input string, minus the `@SECREL32' into a malloc'd buffer for
7545 parsing by the calling routine. Return this buffer, and if ADJUST
7546 is non-null set it to the length of the string we removed from the
34bca508
L		 7547 input line. Otherwise return NULL.
7548
a988325c
NC		 7549 This function is copied from the ELF version above adjusted for PE targets. */
7550
7551static char *
7552lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7553 int *adjust ATTRIBUTE_UNUSED,
c06ec724
L		 7554 i386_operand_type *types,
7555 int bnd_prefix ATTRIBUTE_UNUSED)
a988325c
NC		 7556{
7557 static const struct
7558 {
7559 const char *str;
7560 int len;
7561 const enum bfd_reloc_code_real rel[2];
7562 const i386_operand_type types64;
7563 }
7564 gotrel[] =
7565 {
7566 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7567 BFD_RELOC_32_SECREL },
7568 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7569 };
7570
7571 char *cp;
7572 unsigned j;
7573
7574 for (cp = input_line_pointer; *cp != '@'; cp++)
7575 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7576 return NULL;
7577
7578 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7579 {
7580 int len = gotrel[j].len;
7581
7582 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7583 {
7584 if (gotrel[j].rel[object_64bit] != 0)
7585 {
7586 int first, second;
7587 char *tmpbuf, *past_reloc;
7588
7589 *rel = gotrel[j].rel[object_64bit];
7590 if (adjust)
7591 *adjust = len;
7592
7593 if (types)
7594 {
7595 if (flag_code != CODE_64BIT)
7596 {
7597 types->bitfield.imm32 = 1;
7598 types->bitfield.disp32 = 1;
7599 }
7600 else
7601 *types = gotrel[j].types64;
7602 }
7603
7604 /* The length of the first part of our input line. */
7605 first = cp - input_line_pointer;
7606
7607 /* The second part goes from after the reloc token until
7608 (and including) an end_of_line char or comma. */
7609 past_reloc = cp + 1 + len;
7610 cp = past_reloc;
7611 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7612 ++cp;
7613 second = cp + 1 - past_reloc;
7614
7615 /* Allocate and copy string. The trailing NUL shouldn't
7616 be necessary, but be safe. */
7617 tmpbuf = (char *) xmalloc (first + second + 2);
7618 memcpy (tmpbuf, input_line_pointer, first);
7619 if (second != 0 && *past_reloc != ' ')
7620 /* Replace the relocation token with ' ', so that
7621 errors like foo@SECLREL321 will be detected. */
7622 tmpbuf[first++] = ' ';
7623 memcpy (tmpbuf + first, past_reloc, second);
7624 tmpbuf[first + second] = '\0';
7625 return tmpbuf;
7626 }
7627
7628 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7629 gotrel[j].str, 1 << (5 + object_64bit));
7630 return NULL;
7631 }
7632 }
7633
7634 /* Might be a symbol version string. Don't as_bad here. */
7635 return NULL;
7636}
7637
7638#endif /* TE_PE */
7639
f3c180ae 7640void
e3bb37b5 7641x86_cons (expressionS *exp, int size)
f3c180ae 7642{
ee86248c
JB		 7643 intel_syntax = -intel_syntax;
7644
3c7b9c2c 7645 exp->X_md = 0;
4fa24527 7646 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7647 {
7648 /* Handle @GOTOFF and the like in an expression. */
7649 char *save;
7650 char *gotfree_input_line;
4a57f2cf 7651 int adjust = 0;
f3c180ae
AM		 7652
7653 save = input_line_pointer;
c3320543 7654 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL, 0);
f3c180ae
AM		 7655 if (gotfree_input_line)
7656 input_line_pointer = gotfree_input_line;
7657
7658 expression (exp);
7659
7660 if (gotfree_input_line)
7661 {
7662 /* expression () has merrily parsed up to the end of line,
7663 or a comma - in the wrong buffer. Transfer how far
7664 input_line_pointer has moved to the right buffer. */
7665 input_line_pointer = (save
7666 + (input_line_pointer - gotfree_input_line)
7667 + adjust);
7668 free (gotfree_input_line);
3992d3b7
AM		 7669 if (exp->X_op == O_constant
7670 || exp->X_op == O_absent
7671 || exp->X_op == O_illegal
0398aac5 7672 || exp->X_op == O_register
3992d3b7
AM		 7673 || exp->X_op == O_big)
7674 {
7675 char c = *input_line_pointer;
7676 *input_line_pointer = 0;
7677 as_bad (_("missing or invalid expression `%s'"), save);
7678 *input_line_pointer = c;
7679 }
f3c180ae
AM		 7680 }
7681 }
7682 else
7683 expression (exp);
ee86248c
JB		 7684
7685 intel_syntax = -intel_syntax;
7686
7687 if (intel_syntax)
7688 i386_intel_simplify (exp);
f3c180ae 7689}
f3c180ae 7690
9f32dd5b
L		 7691static void
7692signed_cons (int size)
6482c264 7693{
d182319b
JB		 7694 if (flag_code == CODE_64BIT)
7695 cons_sign = 1;
7696 cons (size);
7697 cons_sign = -1;
6482c264
NC		 7698}
7699
d182319b 7700#ifdef TE_PE
6482c264 7701static void
7016a5d5 7702pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7703{
7704 expressionS exp;
7705
7706 do
7707 {
7708 expression (&exp);
7709 if (exp.X_op == O_symbol)
7710 exp.X_op = O_secrel;
7711
7712 emit_expr (&exp, 4);
7713 }
7714 while (*input_line_pointer++ == ',');
7715
7716 input_line_pointer--;
7717 demand_empty_rest_of_line ();
7718}
6482c264
NC		 7719#endif
7720
43234a1e
L		 7721/* Handle Vector operations. */
7722
7723static char *
7724check_VecOperations (char *op_string, char *op_end)
7725{
7726 const reg_entry *mask;
7727 const char *saved;
7728 char *end_op;
7729
7730 while (*op_string
7731 && (op_end == NULL || op_string < op_end))
7732 {
7733 saved = op_string;
7734 if (*op_string == '{')
7735 {
7736 op_string++;
7737
7738 /* Check broadcasts. */
7739 if (strncmp (op_string, "1to", 3) == 0)
7740 {
7741 int bcst_type;
7742
7743 if (i.broadcast)
7744 goto duplicated_vec_op;
7745
7746 op_string += 3;
7747 if (*op_string == '8')
7748 bcst_type = BROADCAST_1TO8;
7749 else if (*op_string == '1'
7750 && *(op_string+1) == '6')
7751 {
7752 bcst_type = BROADCAST_1TO16;
7753 op_string++;
7754 }
7755 else
7756 {
7757 as_bad (_("Unsupported broadcast: `%s'"), saved);
7758 return NULL;
7759 }
7760 op_string++;
7761
7762 broadcast_op.type = bcst_type;
7763 broadcast_op.operand = this_operand;
7764 i.broadcast = &broadcast_op;
7765 }
7766 /* Check masking operation. */
7767 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7768 {
7769 /* k0 can't be used for write mask. */
7770 if (mask->reg_num == 0)
7771 {
7772 as_bad (_("`%s' can't be used for write mask"),
7773 op_string);
7774 return NULL;
7775 }
7776
7777 if (!i.mask)
7778 {
7779 mask_op.mask = mask;
7780 mask_op.zeroing = 0;
7781 mask_op.operand = this_operand;
7782 i.mask = &mask_op;
7783 }
7784 else
7785 {
7786 if (i.mask->mask)
7787 goto duplicated_vec_op;
7788
7789 i.mask->mask = mask;
7790
7791 /* Only "{z}" is allowed here. No need to check
7792 zeroing mask explicitly. */
7793 if (i.mask->operand != this_operand)
7794 {
7795 as_bad (_("invalid write mask `%s'"), saved);
7796 return NULL;
7797 }
7798 }
7799
7800 op_string = end_op;
7801 }
7802 /* Check zeroing-flag for masking operation. */
7803 else if (*op_string == 'z')
7804 {
7805 if (!i.mask)
7806 {
7807 mask_op.mask = NULL;
7808 mask_op.zeroing = 1;
7809 mask_op.operand = this_operand;
7810 i.mask = &mask_op;
7811 }
7812 else
7813 {
7814 if (i.mask->zeroing)
7815 {
7816 duplicated_vec_op:
7817 as_bad (_("duplicated `%s'"), saved);
7818 return NULL;
7819 }
7820
7821 i.mask->zeroing = 1;
7822
7823 /* Only "{%k}" is allowed here. No need to check mask
7824 register explicitly. */
7825 if (i.mask->operand != this_operand)
7826 {
7827 as_bad (_("invalid zeroing-masking `%s'"),
7828 saved);
7829 return NULL;
7830 }
7831 }
7832
7833 op_string++;
7834 }
7835 else
7836 goto unknown_vec_op;
7837
7838 if (*op_string != '}')
7839 {
7840 as_bad (_("missing `}' in `%s'"), saved);
7841 return NULL;
7842 }
7843 op_string++;
7844 continue;
7845 }
7846 unknown_vec_op:
7847 /* We don't know this one. */
7848 as_bad (_("unknown vector operation: `%s'"), saved);
7849 return NULL;
7850 }
7851
7852 return op_string;
7853}
7854
252b5132 7855static int
70e41ade 7856i386_immediate (char *imm_start)
252b5132
RH		 7857{
7858 char *save_input_line_pointer;
f3c180ae 7859 char *gotfree_input_line;
252b5132 7860 segT exp_seg = 0;
47926f60 7861 expressionS *exp;
40fb9820
L		 7862 i386_operand_type types;
7863
0dfbf9d7 7864 operand_type_set (&types, ~0);
252b5132
RH		 7865
7866 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7867 {
31b2323c
L		 7868 as_bad (_("at most %d immediate operands are allowed"),
7869 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 7870 return 0;
7871 }
7872
7873 exp = &im_expressions[i.imm_operands++];
520dc8e8 7874 i.op[this_operand].imms = exp;
252b5132
RH		 7875
7876 if (is_space_char (*imm_start))
7877 ++imm_start;
7878
7879 save_input_line_pointer = input_line_pointer;
7880 input_line_pointer = imm_start;
7881
c3320543
L		 7882 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types,
7883 (i.bnd_prefix != NULL
7884 || add_bnd_prefix));
f3c180ae
AM		 7885 if (gotfree_input_line)
7886 input_line_pointer = gotfree_input_line;
252b5132
RH		 7887
7888 exp_seg = expression (exp);
7889
83183c0c 7890 SKIP_WHITESPACE ();
43234a1e
L		 7891
7892 /* Handle vector operations. */
7893 if (*input_line_pointer == '{')
7894 {
7895 input_line_pointer = check_VecOperations (input_line_pointer,
7896 NULL);
7897 if (input_line_pointer == NULL)
7898 return 0;
7899 }
7900
252b5132 7901 if (*input_line_pointer)
f3c180ae 7902 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 7903
7904 input_line_pointer = save_input_line_pointer;
f3c180ae 7905 if (gotfree_input_line)
ee86248c
JB		 7906 {
7907 free (gotfree_input_line);
7908
7909 if (exp->X_op == O_constant || exp->X_op == O_register)
7910 exp->X_op = O_illegal;
7911 }
7912
7913 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7914}
252b5132 7915
ee86248c
JB		 7916static int
7917i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7918 i386_operand_type types, const char *imm_start)
7919{
7920 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 7921 {
313c53d1
L		 7922 if (imm_start)
7923 as_bad (_("missing or invalid immediate expression `%s'"),
7924 imm_start);
3992d3b7 7925 return 0;
252b5132 7926 }
3e73aa7c 7927 else if (exp->X_op == O_constant)
252b5132 7928 {
47926f60 7929 /* Size it properly later. */
40fb9820 7930 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 7931 /* If not 64bit, sign extend val. */
7932 if (flag_code != CODE_64BIT
4eed87de
AM		 7933 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7934 exp->X_add_number
7935 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 7936 }
4c63da97 7937#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 7938 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 7939 && exp_seg != absolute_section
47926f60 7940 && exp_seg != text_section
24eab124
AM		 7941 && exp_seg != data_section
7942 && exp_seg != bss_section
7943 && exp_seg != undefined_section
f86103b7 7944 && !bfd_is_com_section (exp_seg))
252b5132 7945 {
d0b47220 7946 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 7947 return 0;
7948 }
7949#endif
bb8f5920
L		 7950 else if (!intel_syntax && exp->X_op == O_register)
7951 {
313c53d1
L		 7952 if (imm_start)
7953 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 7954 return 0;
7955 }
252b5132
RH		 7956 else
7957 {
7958 /* This is an address. The size of the address will be
24eab124 7959 determined later, depending on destination register,
3e73aa7c 7960 suffix, or the default for the section. */
40fb9820
L		 7961 i.types[this_operand].bitfield.imm8 = 1;
7962 i.types[this_operand].bitfield.imm16 = 1;
7963 i.types[this_operand].bitfield.imm32 = 1;
7964 i.types[this_operand].bitfield.imm32s = 1;
7965 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 7966 i.types[this_operand] = operand_type_and (i.types[this_operand],
7967 types);
252b5132
RH		 7968 }
7969
7970 return 1;
7971}
7972
551c1ca1 7973static char *
e3bb37b5 7974i386_scale (char *scale)
252b5132 7975{
551c1ca1
AM		 7976 offsetT val;
7977 char *save = input_line_pointer;
252b5132 7978
551c1ca1
AM		 7979 input_line_pointer = scale;
7980 val = get_absolute_expression ();
7981
7982 switch (val)
252b5132 7983 {
551c1ca1 7984 case 1:
252b5132
RH		 7985 i.log2_scale_factor = 0;
7986 break;
551c1ca1 7987 case 2:
252b5132
RH		 7988 i.log2_scale_factor = 1;
7989 break;
551c1ca1 7990 case 4:
252b5132
RH		 7991 i.log2_scale_factor = 2;
7992 break;
551c1ca1 7993 case 8:
252b5132
RH		 7994 i.log2_scale_factor = 3;
7995 break;
7996 default:
a724f0f4
JB		 7997 {
7998 char sep = *input_line_pointer;
7999
8000 *input_line_pointer = '\0';
8001 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8002 scale);
8003 *input_line_pointer = sep;
8004 input_line_pointer = save;
8005 return NULL;
8006 }
252b5132 8007 }
29b0f896 8008 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8009 {
8010 as_warn (_("scale factor of %d without an index register"),
24eab124 8011 1 << i.log2_scale_factor);
252b5132 8012 i.log2_scale_factor = 0;
252b5132 8013 }
551c1ca1
AM		 8014 scale = input_line_pointer;
8015 input_line_pointer = save;
8016 return scale;
252b5132
RH		 8017}
8018
252b5132 8019static int
e3bb37b5 8020i386_displacement (char *disp_start, char *disp_end)
252b5132 8021{
29b0f896 8022 expressionS *exp;
252b5132
RH		 8023 segT exp_seg = 0;
8024 char *save_input_line_pointer;
f3c180ae 8025 char *gotfree_input_line;
40fb9820
L		 8026 int override;
8027 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8028 int ret;
252b5132 8029
31b2323c
L		 8030 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8031 {
8032 as_bad (_("at most %d displacement operands are allowed"),
8033 MAX_MEMORY_OPERANDS);
8034 return 0;
8035 }
8036
0dfbf9d7 8037 operand_type_set (&bigdisp, 0);
40fb9820
L		 8038 if ((i.types[this_operand].bitfield.jumpabsolute)
8039 || (!current_templates->start->opcode_modifier.jump
8040 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8041 {
40fb9820 8042 bigdisp.bitfield.disp32 = 1;
e05278af 8043 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8044 if (flag_code == CODE_64BIT)
8045 {
8046 if (!override)
8047 {
8048 bigdisp.bitfield.disp32s = 1;
8049 bigdisp.bitfield.disp64 = 1;
8050 }
8051 }
8052 else if ((flag_code == CODE_16BIT) ^ override)
8053 {
8054 bigdisp.bitfield.disp32 = 0;
8055 bigdisp.bitfield.disp16 = 1;
8056 }
e05278af
JB		 8057 }
8058 else
8059 {
8060 /* For PC-relative branches, the width of the displacement
8061 is dependent upon data size, not address size. */
e05278af 8062 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8063 if (flag_code == CODE_64BIT)
8064 {
8065 if (override || i.suffix == WORD_MNEM_SUFFIX)
8066 bigdisp.bitfield.disp16 = 1;
8067 else
8068 {
8069 bigdisp.bitfield.disp32 = 1;
8070 bigdisp.bitfield.disp32s = 1;
8071 }
8072 }
8073 else
e05278af
JB		 8074 {
8075 if (!override)
8076 override = (i.suffix == (flag_code != CODE_16BIT
8077 ? WORD_MNEM_SUFFIX
8078 : LONG_MNEM_SUFFIX));
40fb9820
L		 8079 bigdisp.bitfield.disp32 = 1;
8080 if ((flag_code == CODE_16BIT) ^ override)
8081 {
8082 bigdisp.bitfield.disp32 = 0;
8083 bigdisp.bitfield.disp16 = 1;
8084 }
e05278af 8085 }
e05278af 8086 }
c6fb90c8
L		 8087 i.types[this_operand] = operand_type_or (i.types[this_operand],
8088 bigdisp);
252b5132
RH		 8089
8090 exp = &disp_expressions[i.disp_operands];
520dc8e8 8091 i.op[this_operand].disps = exp;
252b5132
RH		 8092 i.disp_operands++;
8093 save_input_line_pointer = input_line_pointer;
8094 input_line_pointer = disp_start;
8095 END_STRING_AND_SAVE (disp_end);
8096
8097#ifndef GCC_ASM_O_HACK
8098#define GCC_ASM_O_HACK 0
8099#endif
8100#if GCC_ASM_O_HACK
8101 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8102 if (i.types[this_operand].bitfield.baseIndex
24eab124 8103 && displacement_string_end[-1] == '+')
252b5132
RH		 8104 {
8105 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8106 constraint within gcc asm statements.
8107 For instance:
8108
8109 #define _set_tssldt_desc(n,addr,limit,type) \
8110 __asm__ __volatile__ ( \
8111 "movw %w2,%0\n\t" \
8112 "movw %w1,2+%0\n\t" \
8113 "rorl $16,%1\n\t" \
8114 "movb %b1,4+%0\n\t" \
8115 "movb %4,5+%0\n\t" \
8116 "movb $0,6+%0\n\t" \
8117 "movb %h1,7+%0\n\t" \
8118 "rorl $16,%1" \
8119 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8120
8121 This works great except that the output assembler ends
8122 up looking a bit weird if it turns out that there is
8123 no offset. You end up producing code that looks like:
8124
8125 #APP
8126 movw $235,(%eax)
8127 movw %dx,2+(%eax)
8128 rorl $16,%edx
8129 movb %dl,4+(%eax)
8130 movb $137,5+(%eax)
8131 movb $0,6+(%eax)
8132 movb %dh,7+(%eax)
8133 rorl $16,%edx
8134 #NO_APP
8135
47926f60 8136 So here we provide the missing zero. */
24eab124
AM		 8137
8138 *displacement_string_end = '0';
252b5132
RH		 8139 }
8140#endif
c3320543
L		 8141 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types,
8142 (i.bnd_prefix != NULL
8143 || add_bnd_prefix));
f3c180ae
AM		 8144 if (gotfree_input_line)
8145 input_line_pointer = gotfree_input_line;
252b5132 8146
24eab124 8147 exp_seg = expression (exp);
252b5132 8148
636c26b0
AM		 8149 SKIP_WHITESPACE ();
8150 if (*input_line_pointer)
8151 as_bad (_("junk `%s' after expression"), input_line_pointer);
8152#if GCC_ASM_O_HACK
8153 RESTORE_END_STRING (disp_end + 1);
8154#endif
636c26b0 8155 input_line_pointer = save_input_line_pointer;
636c26b0 8156 if (gotfree_input_line)
ee86248c
JB		 8157 {
8158 free (gotfree_input_line);
8159
8160 if (exp->X_op == O_constant || exp->X_op == O_register)
8161 exp->X_op = O_illegal;
8162 }
8163
8164 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8165
8166 RESTORE_END_STRING (disp_end);
8167
8168 return ret;
8169}
8170
8171static int
8172i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8173 i386_operand_type types, const char *disp_start)
8174{
8175 i386_operand_type bigdisp;
8176 int ret = 1;
636c26b0 8177
24eab124
AM		 8178 /* We do this to make sure that the section symbol is in
8179 the symbol table. We will ultimately change the relocation
47926f60 8180 to be relative to the beginning of the section. */
1ae12ab7 8181 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8182 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8183 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8184 {
636c26b0 8185 if (exp->X_op != O_symbol)
3992d3b7 8186 goto inv_disp;
636c26b0 8187
e5cb08ac 8188 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8189 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8190 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8191 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8192 exp->X_op = O_subtract;
8193 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8194 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8195 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8196 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8197 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8198 else
29b0f896 8199 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8200 }
252b5132 8201
3992d3b7
AM		 8202 else if (exp->X_op == O_absent
8203 || exp->X_op == O_illegal
ee86248c 8204 || exp->X_op == O_big)
2daf4fd8 8205 {
3992d3b7
AM		 8206 inv_disp:
8207 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8208 disp_start);
3992d3b7 8209 ret = 0;
2daf4fd8
AM		 8210 }
8211
0e1147d9
L		 8212 else if (flag_code == CODE_64BIT
8213 && !i.prefix[ADDR_PREFIX]
8214 && exp->X_op == O_constant)
8215 {
8216 /* Since displacement is signed extended to 64bit, don't allow
8217 disp32 and turn off disp32s if they are out of range. */
8218 i.types[this_operand].bitfield.disp32 = 0;
8219 if (!fits_in_signed_long (exp->X_add_number))
8220 {
8221 i.types[this_operand].bitfield.disp32s = 0;
8222 if (i.types[this_operand].bitfield.baseindex)
8223 {
8224 as_bad (_("0x%lx out range of signed 32bit displacement"),
8225 (long) exp->X_add_number);
8226 ret = 0;
8227 }
8228 }
8229 }
8230
4c63da97 8231#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8232 else if (exp->X_op != O_constant
8233 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8234 && exp_seg != absolute_section
8235 && exp_seg != text_section
8236 && exp_seg != data_section
8237 && exp_seg != bss_section
8238 && exp_seg != undefined_section
8239 && !bfd_is_com_section (exp_seg))
24eab124 8240 {
d0b47220 8241 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8242 ret = 0;
24eab124 8243 }
252b5132 8244#endif
3956db08 8245
40fb9820
L		 8246 /* Check if this is a displacement only operand. */
8247 bigdisp = i.types[this_operand];
8248 bigdisp.bitfield.disp8 = 0;
8249 bigdisp.bitfield.disp16 = 0;
8250 bigdisp.bitfield.disp32 = 0;
8251 bigdisp.bitfield.disp32s = 0;
8252 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8253 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8254 i.types[this_operand] = operand_type_and (i.types[this_operand],
8255 types);
3956db08 8256
3992d3b7 8257 return ret;
252b5132
RH		 8258}
8259
eecb386c 8260/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8261 Return 1 on success, 0 on a failure. */
8262
252b5132 8263static int
e3bb37b5 8264i386_index_check (const char *operand_string)
252b5132 8265{
fc0763e6 8266 const char *kind = "base/index";
be05d201
L		 8267 enum flag_code addr_mode;
8268
8269 if (i.prefix[ADDR_PREFIX])
8270 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8271 else
8272 {
8273 addr_mode = flag_code;
8274
24eab124 8275#if INFER_ADDR_PREFIX
be05d201
L		 8276 if (i.mem_operands == 0)
8277 {
8278 /* Infer address prefix from the first memory operand. */
8279 const reg_entry *addr_reg = i.base_reg;
8280
8281 if (addr_reg == NULL)
8282 addr_reg = i.index_reg;
eecb386c 8283
be05d201
L		 8284 if (addr_reg)
8285 {
8286 if (addr_reg->reg_num == RegEip
8287 || addr_reg->reg_num == RegEiz
8288 || addr_reg->reg_type.bitfield.reg32)
8289 addr_mode = CODE_32BIT;
8290 else if (flag_code != CODE_64BIT
8291 && addr_reg->reg_type.bitfield.reg16)
8292 addr_mode = CODE_16BIT;
8293
8294 if (addr_mode != flag_code)
8295 {
8296 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8297 i.prefixes += 1;
8298 /* Change the size of any displacement too. At most one
8299 of Disp16 or Disp32 is set.
8300 FIXME. There doesn't seem to be any real need for
8301 separate Disp16 and Disp32 flags. The same goes for
8302 Imm16 and Imm32. Removing them would probably clean
8303 up the code quite a lot. */
8304 if (flag_code != CODE_64BIT
8305 && (i.types[this_operand].bitfield.disp16
8306 || i.types[this_operand].bitfield.disp32))
8307 i.types[this_operand]
8308 = operand_type_xor (i.types[this_operand], disp16_32);
8309 }
8310 }
8311 }
24eab124 8312#endif
be05d201
L		 8313 }
8314
fc0763e6
JB		 8315 if (current_templates->start->opcode_modifier.isstring
8316 && !current_templates->start->opcode_modifier.immext
8317 && (current_templates->end[-1].opcode_modifier.isstring
8318 || i.mem_operands))
8319 {
8320 /* Memory operands of string insns are special in that they only allow
8321 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8322 const reg_entry *expected_reg;
8323 static const char *di_si[][2] =
8324 {
8325 { "esi", "edi" },
8326 { "si", "di" },
8327 { "rsi", "rdi" }
8328 };
8329 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8330
8331 kind = "string address";
8332
8333 if (current_templates->start->opcode_modifier.w)
8334 {
8335 i386_operand_type type = current_templates->end[-1].operand_types[0];
8336
8337 if (!type.bitfield.baseindex
8338 || ((!i.mem_operands != !intel_syntax)
8339 && current_templates->end[-1].operand_types[1]
8340 .bitfield.baseindex))
8341 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8342 expected_reg = hash_find (reg_hash,
8343 di_si[addr_mode][type.bitfield.esseg]);
8344
fc0763e6
JB		 8345 }
8346 else
be05d201 8347 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8348
be05d201
L		 8349 if (i.base_reg != expected_reg
8350 || i.index_reg
fc0763e6 8351 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8352 {
be05d201
L		 8353 /* The second memory operand must have the same size as
8354 the first one. */
8355 if (i.mem_operands
8356 && i.base_reg
8357 && !((addr_mode == CODE_64BIT
8358 && i.base_reg->reg_type.bitfield.reg64)
8359 || (addr_mode == CODE_32BIT
8360 ? i.base_reg->reg_type.bitfield.reg32
8361 : i.base_reg->reg_type.bitfield.reg16)))
8362 goto bad_address;
8363
fc0763e6
JB		 8364 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8365 operand_string,
8366 intel_syntax ? '[' : '(',
8367 register_prefix,
be05d201 8368 expected_reg->reg_name,
fc0763e6 8369 intel_syntax ? ']' : ')');
be05d201 8370 return 1;
fc0763e6 8371 }
be05d201
L		 8372 else
8373 return 1;
8374
8375bad_address:
8376 as_bad (_("`%s' is not a valid %s expression"),
8377 operand_string, kind);
8378 return 0;
3e73aa7c
JH		 8379 }
8380 else
8381 {
be05d201
L		 8382 if (addr_mode != CODE_16BIT)
8383 {
8384 /* 32-bit/64-bit checks. */
8385 if ((i.base_reg
8386 && (addr_mode == CODE_64BIT
8387 ? !i.base_reg->reg_type.bitfield.reg64
8388 : !i.base_reg->reg_type.bitfield.reg32)
8389 && (i.index_reg
8390 || (i.base_reg->reg_num
8391 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8392 || (i.index_reg
8393 && !i.index_reg->reg_type.bitfield.regxmm
8394 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8395 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8396 && ((addr_mode == CODE_64BIT
8397 ? !(i.index_reg->reg_type.bitfield.reg64
8398 || i.index_reg->reg_num == RegRiz)
8399 : !(i.index_reg->reg_type.bitfield.reg32
8400 || i.index_reg->reg_num == RegEiz))
8401 || !i.index_reg->reg_type.bitfield.baseindex)))
8402 goto bad_address;
8403 }
8404 else
3e73aa7c 8405 {
be05d201 8406 /* 16-bit checks. */
3e73aa7c 8407 if ((i.base_reg
40fb9820
L		 8408 && (!i.base_reg->reg_type.bitfield.reg16
8409 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8410 || (i.index_reg
40fb9820
L		 8411 && (!i.index_reg->reg_type.bitfield.reg16
8412 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8413 || !(i.base_reg
8414 && i.base_reg->reg_num < 6
8415 && i.index_reg->reg_num >= 6
8416 && i.log2_scale_factor == 0))))
be05d201 8417 goto bad_address;
3e73aa7c
JH		 8418 }
8419 }
be05d201 8420 return 1;
24eab124 8421}
252b5132 8422
43234a1e
L		 8423/* Handle vector immediates. */
8424
8425static int
8426RC_SAE_immediate (const char *imm_start)
8427{
8428 unsigned int match_found, j;
8429 const char *pstr = imm_start;
8430 expressionS *exp;
8431
8432 if (*pstr != '{')
8433 return 0;
8434
8435 pstr++;
8436 match_found = 0;
8437 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8438 {
8439 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8440 {
8441 if (!i.rounding)
8442 {
8443 rc_op.type = RC_NamesTable[j].type;
8444 rc_op.operand = this_operand;
8445 i.rounding = &rc_op;
8446 }
8447 else
8448 {
8449 as_bad (_("duplicated `%s'"), imm_start);
8450 return 0;
8451 }
8452 pstr += RC_NamesTable[j].len;
8453 match_found = 1;
8454 break;
8455 }
8456 }
8457 if (!match_found)
8458 return 0;
8459
8460 if (*pstr++ != '}')
8461 {
8462 as_bad (_("Missing '}': '%s'"), imm_start);
8463 return 0;
8464 }
8465 /* RC/SAE immediate string should contain nothing more. */;
8466 if (*pstr != 0)
8467 {
8468 as_bad (_("Junk after '}': '%s'"), imm_start);
8469 return 0;
8470 }
8471
8472 exp = &im_expressions[i.imm_operands++];
8473 i.op[this_operand].imms = exp;
8474
8475 exp->X_op = O_constant;
8476 exp->X_add_number = 0;
8477 exp->X_add_symbol = (symbolS *) 0;
8478 exp->X_op_symbol = (symbolS *) 0;
8479
8480 i.types[this_operand].bitfield.imm8 = 1;
8481 return 1;
8482}
8483
fc0763e6 8484/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8485 on error. */
252b5132 8486
252b5132 8487static int
a7619375 8488i386_att_operand (char *operand_string)
252b5132 8489{
af6bdddf
AM		 8490 const reg_entry *r;
8491 char *end_op;
24eab124 8492 char *op_string = operand_string;
252b5132 8493
24eab124 8494 if (is_space_char (*op_string))
252b5132
RH		 8495 ++op_string;
8496
24eab124 8497 /* We check for an absolute prefix (differentiating,
47926f60 8498 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8499 if (*op_string == ABSOLUTE_PREFIX)
8500 {
8501 ++op_string;
8502 if (is_space_char (*op_string))
8503 ++op_string;
40fb9820 8504 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8505 }
252b5132 8506
47926f60 8507 /* Check if operand is a register. */
4d1bb795 8508 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8509 {
40fb9820
L		 8510 i386_operand_type temp;
8511
24eab124
AM		 8512 /* Check for a segment override by searching for ':' after a
8513 segment register. */
8514 op_string = end_op;
8515 if (is_space_char (*op_string))
8516 ++op_string;
40fb9820
L		 8517 if (*op_string == ':'
8518 && (r->reg_type.bitfield.sreg2
8519 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8520 {
8521 switch (r->reg_num)
8522 {
8523 case 0:
8524 i.seg[i.mem_operands] = &es;
8525 break;
8526 case 1:
8527 i.seg[i.mem_operands] = &cs;
8528 break;
8529 case 2:
8530 i.seg[i.mem_operands] = &ss;
8531 break;
8532 case 3:
8533 i.seg[i.mem_operands] = &ds;
8534 break;
8535 case 4:
8536 i.seg[i.mem_operands] = &fs;
8537 break;
8538 case 5:
8539 i.seg[i.mem_operands] = &gs;
8540 break;
8541 }
252b5132 8542
24eab124 8543 /* Skip the ':' and whitespace. */
252b5132
RH		 8544 ++op_string;
8545 if (is_space_char (*op_string))
24eab124 8546 ++op_string;
252b5132 8547
24eab124
AM		 8548 if (!is_digit_char (*op_string)
8549 && !is_identifier_char (*op_string)
8550 && *op_string != '('
8551 && *op_string != ABSOLUTE_PREFIX)
8552 {
8553 as_bad (_("bad memory operand `%s'"), op_string);
8554 return 0;
8555 }
47926f60 8556 /* Handle case of %es:*foo. */
24eab124
AM		 8557 if (*op_string == ABSOLUTE_PREFIX)
8558 {
8559 ++op_string;
8560 if (is_space_char (*op_string))
8561 ++op_string;
40fb9820 8562 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8563 }
8564 goto do_memory_reference;
8565 }
43234a1e
L		 8566
8567 /* Handle vector operations. */
8568 if (*op_string == '{')
8569 {
8570 op_string = check_VecOperations (op_string, NULL);
8571 if (op_string == NULL)
8572 return 0;
8573 }
8574
24eab124
AM		 8575 if (*op_string)
8576 {
d0b47220 8577 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8578 return 0;
8579 }
40fb9820
L		 8580 temp = r->reg_type;
8581 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8582 i.types[this_operand] = operand_type_or (i.types[this_operand],
8583 temp);
7d5e4556 8584 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8585 i.op[this_operand].regs = r;
24eab124
AM		 8586 i.reg_operands++;
8587 }
af6bdddf
AM		 8588 else if (*op_string == REGISTER_PREFIX)
8589 {
8590 as_bad (_("bad register name `%s'"), op_string);
8591 return 0;
8592 }
24eab124 8593 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8594 {
24eab124 8595 ++op_string;
40fb9820 8596 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8597 {
d0b47220 8598 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8599 return 0;
8600 }
8601 if (!i386_immediate (op_string))
8602 return 0;
8603 }
43234a1e
L		 8604 else if (RC_SAE_immediate (operand_string))
8605 {
8606 /* If it is a RC or SAE immediate, do nothing. */
8607 ;
8608 }
24eab124
AM		 8609 else if (is_digit_char (*op_string)
8610 || is_identifier_char (*op_string)
e5cb08ac 8611 || *op_string == '(')
24eab124 8612 {
47926f60 8613 /* This is a memory reference of some sort. */
af6bdddf 8614 char *base_string;
252b5132 8615
47926f60 8616 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8617 char *displacement_string_start;
8618 char *displacement_string_end;
43234a1e 8619 char *vop_start;
252b5132 8620
24eab124 8621 do_memory_reference:
24eab124 8622 if ((i.mem_operands == 1
40fb9820 8623 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8624 || i.mem_operands == 2)
8625 {
8626 as_bad (_("too many memory references for `%s'"),
8627 current_templates->start->name);
8628 return 0;
8629 }
252b5132 8630
24eab124
AM		 8631 /* Check for base index form. We detect the base index form by
8632 looking for an ')' at the end of the operand, searching
8633 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8634 after the '('. */
af6bdddf 8635 base_string = op_string + strlen (op_string);
c3332e24 8636
43234a1e
L		 8637 /* Handle vector operations. */
8638 vop_start = strchr (op_string, '{');
8639 if (vop_start && vop_start < base_string)
8640 {
8641 if (check_VecOperations (vop_start, base_string) == NULL)
8642 return 0;
8643 base_string = vop_start;
8644 }
8645
af6bdddf
AM		 8646 --base_string;
8647 if (is_space_char (*base_string))
8648 --base_string;
252b5132 8649
47926f60 8650 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8651 displacement_string_start = op_string;
8652 displacement_string_end = base_string + 1;
252b5132 8653
24eab124
AM		 8654 if (*base_string == ')')
8655 {
af6bdddf 8656 char *temp_string;
24eab124
AM		 8657 unsigned int parens_balanced = 1;
8658 /* We've already checked that the number of left & right ()'s are
47926f60 8659 equal, so this loop will not be infinite. */
24eab124
AM		 8660 do
8661 {
8662 base_string--;
8663 if (*base_string == ')')
8664 parens_balanced++;
8665 if (*base_string == '(')
8666 parens_balanced--;
8667 }
8668 while (parens_balanced);
c3332e24 8669
af6bdddf 8670 temp_string = base_string;
c3332e24 8671
24eab124 8672 /* Skip past '(' and whitespace. */
252b5132
RH		 8673 ++base_string;
8674 if (is_space_char (*base_string))
24eab124 8675 ++base_string;
252b5132 8676
af6bdddf 8677 if (*base_string == ','
4eed87de
AM		 8678 || ((i.base_reg = parse_register (base_string, &end_op))
8679 != NULL))
252b5132 8680 {
af6bdddf 8681 displacement_string_end = temp_string;
252b5132 8682
40fb9820 8683 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8684
af6bdddf 8685 if (i.base_reg)
24eab124 8686 {
24eab124
AM		 8687 base_string = end_op;
8688 if (is_space_char (*base_string))
8689 ++base_string;
af6bdddf
AM		 8690 }
8691
8692 /* There may be an index reg or scale factor here. */
8693 if (*base_string == ',')
8694 {
8695 ++base_string;
8696 if (is_space_char (*base_string))
8697 ++base_string;
8698
4eed87de
AM		 8699 if ((i.index_reg = parse_register (base_string, &end_op))
8700 != NULL)
24eab124 8701 {
af6bdddf 8702 base_string = end_op;
24eab124
AM		 8703 if (is_space_char (*base_string))
8704 ++base_string;
af6bdddf
AM		 8705 if (*base_string == ',')
8706 {
8707 ++base_string;
8708 if (is_space_char (*base_string))
8709 ++base_string;
8710 }
e5cb08ac 8711 else if (*base_string != ')')
af6bdddf 8712 {
4eed87de
AM		 8713 as_bad (_("expecting `,' or `)' "
8714 "after index register in `%s'"),
af6bdddf
AM		 8715 operand_string);
8716 return 0;
8717 }
24eab124 8718 }
af6bdddf 8719 else if (*base_string == REGISTER_PREFIX)
24eab124 8720 {
f76bf5e0
L		 8721 end_op = strchr (base_string, ',');
8722 if (end_op)
8723 *end_op = '\0';
af6bdddf 8724 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8725 return 0;
8726 }
252b5132 8727
47926f60 8728 /* Check for scale factor. */
551c1ca1 8729 if (*base_string != ')')
af6bdddf 8730 {
551c1ca1
AM		 8731 char *end_scale = i386_scale (base_string);
8732
8733 if (!end_scale)
af6bdddf 8734 return 0;
24eab124 8735
551c1ca1 8736 base_string = end_scale;
af6bdddf
AM		 8737 if (is_space_char (*base_string))
8738 ++base_string;
8739 if (*base_string != ')')
8740 {
4eed87de
AM		 8741 as_bad (_("expecting `)' "
8742 "after scale factor in `%s'"),
af6bdddf
AM		 8743 operand_string);
8744 return 0;
8745 }
8746 }
8747 else if (!i.index_reg)
24eab124 8748 {
4eed87de
AM		 8749 as_bad (_("expecting index register or scale factor "
8750 "after `,'; got '%c'"),
af6bdddf 8751 *base_string);
24eab124
AM		 8752 return 0;
8753 }
8754 }
af6bdddf 8755 else if (*base_string != ')')
24eab124 8756 {
4eed87de
AM		 8757 as_bad (_("expecting `,' or `)' "
8758 "after base register in `%s'"),
af6bdddf 8759 operand_string);
24eab124
AM		 8760 return 0;
8761 }
c3332e24 8762 }
af6bdddf 8763 else if (*base_string == REGISTER_PREFIX)
c3332e24 8764 {
f76bf5e0
L		 8765 end_op = strchr (base_string, ',');
8766 if (end_op)
8767 *end_op = '\0';
af6bdddf 8768 as_bad (_("bad register name `%s'"), base_string);
24eab124 8769 return 0;
c3332e24 8770 }
24eab124
AM		 8771 }
8772
8773 /* If there's an expression beginning the operand, parse it,
8774 assuming displacement_string_start and
8775 displacement_string_end are meaningful. */
8776 if (displacement_string_start != displacement_string_end)
8777 {
8778 if (!i386_displacement (displacement_string_start,
8779 displacement_string_end))
8780 return 0;
8781 }
8782
8783 /* Special case for (%dx) while doing input/output op. */
8784 if (i.base_reg
0dfbf9d7
L		 8785 && operand_type_equal (&i.base_reg->reg_type,
8786 &reg16_inoutportreg)
24eab124
AM		 8787 && i.index_reg == 0
8788 && i.log2_scale_factor == 0
8789 && i.seg[i.mem_operands] == 0
40fb9820 8790 && !operand_type_check (i.types[this_operand], disp))
24eab124 8791 {
65da13b5 8792 i.types[this_operand] = inoutportreg;
24eab124
AM		 8793 return 1;
8794 }
8795
eecb386c
AM		 8796 if (i386_index_check (operand_string) == 0)
8797 return 0;
5c07affc 8798 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 8799 i.mem_operands++;
8800 }
8801 else
ce8a8b2f
AM		 8802 {
8803 /* It's not a memory operand; argh! */
24eab124
AM		 8804 as_bad (_("invalid char %s beginning operand %d `%s'"),
8805 output_invalid (*op_string),
8806 this_operand + 1,
8807 op_string);
8808 return 0;
8809 }
47926f60 8810 return 1; /* Normal return. */
252b5132
RH		 8811}
8812\f
fa94de6b
RM		 8813/* Calculate the maximum variable size (i.e., excluding fr_fix)
8814 that an rs_machine_dependent frag may reach. */
8815
8816unsigned int
8817i386_frag_max_var (fragS *frag)
8818{
8819 /* The only relaxable frags are for jumps.
8820 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8821 gas_assert (frag->fr_type == rs_machine_dependent);
8822 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8823}
8824
ee7fcc42
AM		 8825/* md_estimate_size_before_relax()
8826
8827 Called just before relax() for rs_machine_dependent frags. The x86
8828 assembler uses these frags to handle variable size jump
8829 instructions.
8830
8831 Any symbol that is now undefined will not become defined.
8832 Return the correct fr_subtype in the frag.
8833 Return the initial "guess for variable size of frag" to caller.
8834 The guess is actually the growth beyond the fixed part. Whatever
8835 we do to grow the fixed or variable part contributes to our
8836 returned value. */
8837
252b5132 8838int
7016a5d5 8839md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 8840{
252b5132 8841 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 8842 check for un-relaxable symbols. On an ELF system, we can't relax
8843 an externally visible symbol, because it may be overridden by a
8844 shared library. */
8845 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 8846#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8847 || (IS_ELF
31312f95 8848 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 8849 || S_IS_WEAK (fragP->fr_symbol)
8850 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
8851 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 8852#endif
8853#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 8854 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 8855 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 8856#endif
8857 )
252b5132 8858 {
b98ef147
AM		 8859 /* Symbol is undefined in this segment, or we need to keep a
8860 reloc so that weak symbols can be overridden. */
8861 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 8862 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 8863 unsigned char *opcode;
8864 int old_fr_fix;
f6af82bd 8865
ee7fcc42 8866 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 8867 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 8868 else if (size == 2)
f6af82bd
AM		 8869 reloc_type = BFD_RELOC_16_PCREL;
8870 else
8871 reloc_type = BFD_RELOC_32_PCREL;
252b5132 8872
ee7fcc42
AM		 8873 old_fr_fix = fragP->fr_fix;
8874 opcode = (unsigned char *) fragP->fr_opcode;
8875
fddf5b5b 8876 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 8877 {
fddf5b5b
AM		 8878 case UNCOND_JUMP:
8879 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 8880 opcode[0] = 0xe9;
252b5132 8881 fragP->fr_fix += size;
062cd5e7
AS		 8882 fix_new (fragP, old_fr_fix, size,
8883 fragP->fr_symbol,
8884 fragP->fr_offset, 1,
8885 reloc_type);
252b5132
RH		 8886 break;
8887
fddf5b5b 8888 case COND_JUMP86:
412167cb
AM		 8889 if (size == 2
8890 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 8891 {
8892 /* Negate the condition, and branch past an
8893 unconditional jump. */
8894 opcode[0] ^= 1;
8895 opcode[1] = 3;
8896 /* Insert an unconditional jump. */
8897 opcode[2] = 0xe9;
8898 /* We added two extra opcode bytes, and have a two byte
8899 offset. */
8900 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 8901 fix_new (fragP, old_fr_fix + 2, 2,
8902 fragP->fr_symbol,
8903 fragP->fr_offset, 1,
8904 reloc_type);
fddf5b5b
AM		 8905 break;
8906 }
8907 /* Fall through. */
8908
8909 case COND_JUMP:
412167cb
AM		 8910 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
8911 {
3e02c1cc
AM		 8912 fixS *fixP;
8913
412167cb 8914 fragP->fr_fix += 1;
3e02c1cc
AM		 8915 fixP = fix_new (fragP, old_fr_fix, 1,
8916 fragP->fr_symbol,
8917 fragP->fr_offset, 1,
8918 BFD_RELOC_8_PCREL);
8919 fixP->fx_signed = 1;
412167cb
AM		 8920 break;
8921 }
93c2a809 8922
24eab124 8923 /* This changes the byte-displacement jump 0x7N
fddf5b5b 8924 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 8925 opcode[1] = opcode[0] + 0x10;
f6af82bd 8926 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 8927 /* We've added an opcode byte. */
8928 fragP->fr_fix += 1 + size;
062cd5e7
AS		 8929 fix_new (fragP, old_fr_fix + 1, size,
8930 fragP->fr_symbol,
8931 fragP->fr_offset, 1,
8932 reloc_type);
252b5132 8933 break;
fddf5b5b
AM		 8934
8935 default:
8936 BAD_CASE (fragP->fr_subtype);
8937 break;
252b5132
RH		 8938 }
8939 frag_wane (fragP);
ee7fcc42 8940 return fragP->fr_fix - old_fr_fix;
252b5132 8941 }
93c2a809 8942
93c2a809
AM		 8943 /* Guess size depending on current relax state. Initially the relax
8944 state will correspond to a short jump and we return 1, because
8945 the variable part of the frag (the branch offset) is one byte
8946 long. However, we can relax a section more than once and in that
8947 case we must either set fr_subtype back to the unrelaxed state,
8948 or return the value for the appropriate branch. */
8949 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 8950}
8951
47926f60
KH		 8952/* Called after relax() is finished.
8953
8954 In: Address of frag.
8955 fr_type == rs_machine_dependent.
8956 fr_subtype is what the address relaxed to.
8957
8958 Out: Any fixSs and constants are set up.
8959 Caller will turn frag into a ".space 0". */
8960
252b5132 8961void
7016a5d5
TG		 8962md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
8963 fragS *fragP)
252b5132 8964{
29b0f896 8965 unsigned char *opcode;
252b5132 8966 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 8967 offsetT target_address;
8968 offsetT opcode_address;
252b5132 8969 unsigned int extension = 0;
847f7ad4 8970 offsetT displacement_from_opcode_start;
252b5132
RH		 8971
8972 opcode = (unsigned char *) fragP->fr_opcode;
8973
47926f60 8974 /* Address we want to reach in file space. */
252b5132 8975 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 8976
47926f60 8977 /* Address opcode resides at in file space. */
252b5132
RH		 8978 opcode_address = fragP->fr_address + fragP->fr_fix;
8979
47926f60 8980 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 8981 displacement_from_opcode_start = target_address - opcode_address;
8982
fddf5b5b 8983 if ((fragP->fr_subtype & BIG) == 0)
252b5132 8984 {
47926f60
KH		 8985 /* Don't have to change opcode. */
8986 extension = 1; /* 1 opcode + 1 displacement */
252b5132 8987 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 8988 }
8989 else
8990 {
8991 if (no_cond_jump_promotion
8992 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 8993 as_warn_where (fragP->fr_file, fragP->fr_line,
8994 _("long jump required"));
252b5132 8995
fddf5b5b
AM		 8996 switch (fragP->fr_subtype)
8997 {
8998 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
8999 extension = 4; /* 1 opcode + 4 displacement */
9000 opcode[0] = 0xe9;
9001 where_to_put_displacement = &opcode[1];
9002 break;
252b5132 9003
fddf5b5b
AM		 9004 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9005 extension = 2; /* 1 opcode + 2 displacement */
9006 opcode[0] = 0xe9;
9007 where_to_put_displacement = &opcode[1];
9008 break;
252b5132 9009
fddf5b5b
AM		 9010 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9011 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9012 extension = 5; /* 2 opcode + 4 displacement */
9013 opcode[1] = opcode[0] + 0x10;
9014 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9015 where_to_put_displacement = &opcode[2];
9016 break;
252b5132 9017
fddf5b5b
AM		 9018 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9019 extension = 3; /* 2 opcode + 2 displacement */
9020 opcode[1] = opcode[0] + 0x10;
9021 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9022 where_to_put_displacement = &opcode[2];
9023 break;
252b5132 9024
fddf5b5b
AM		 9025 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9026 extension = 4;
9027 opcode[0] ^= 1;
9028 opcode[1] = 3;
9029 opcode[2] = 0xe9;
9030 where_to_put_displacement = &opcode[3];
9031 break;
9032
9033 default:
9034 BAD_CASE (fragP->fr_subtype);
9035 break;
9036 }
252b5132 9037 }
fddf5b5b 9038
7b81dfbb
AJ		 9039 /* If size if less then four we are sure that the operand fits,
9040 but if it's 4, then it could be that the displacement is larger
9041 then -/+ 2GB. */
9042 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9043 && object_64bit
9044 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9045 + ((addressT) 1 << 31))
9046 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9047 {
9048 as_bad_where (fragP->fr_file, fragP->fr_line,
9049 _("jump target out of range"));
9050 /* Make us emit 0. */
9051 displacement_from_opcode_start = extension;
9052 }
47926f60 9053 /* Now put displacement after opcode. */
252b5132
RH		 9054 md_number_to_chars ((char *) where_to_put_displacement,
9055 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9056 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9057 fragP->fr_fix += extension;
9058}
9059\f
7016a5d5 9060/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9061 by our caller that we have all the info we need to fix it up.
9062
7016a5d5
TG		 9063 Parameter valP is the pointer to the value of the bits.
9064
252b5132
RH		 9065 On the 386, immediates, displacements, and data pointers are all in
9066 the same (little-endian) format, so we don't need to care about which
9067 we are handling. */
9068
94f592af 9069void
7016a5d5 9070md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9071{
94f592af 9072 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9073 valueT value = *valP;
252b5132 9074
f86103b7 9075#if !defined (TE_Mach)
93382f6d
AM		 9076 if (fixP->fx_pcrel)
9077 {
9078 switch (fixP->fx_r_type)
9079 {
5865bb77
ILT		 9080 default:
9081 break;
9082
d6ab8113
JB		 9083 case BFD_RELOC_64:
9084 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9085 break;
93382f6d 9086 case BFD_RELOC_32:
ae8887b5 9087 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9088 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9089 break;
9090 case BFD_RELOC_16:
9091 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9092 break;
9093 case BFD_RELOC_8:
9094 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9095 break;
9096 }
9097 }
252b5132 9098
a161fe53 9099 if (fixP->fx_addsy != NULL
31312f95 9100 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9101 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9102 || fixP->fx_r_type == BFD_RELOC_16_PCREL
c3320543
L		 9103 || fixP->fx_r_type == BFD_RELOC_8_PCREL
9104 || fixP->fx_r_type == BFD_RELOC_X86_64_PC32_BND)
31312f95 9105 && !use_rela_relocations)
252b5132 9106 {
31312f95
AM		 9107 /* This is a hack. There should be a better way to handle this.
9108 This covers for the fact that bfd_install_relocation will
9109 subtract the current location (for partial_inplace, PC relative
9110 relocations); see more below. */
252b5132 9111#ifndef OBJ_AOUT
718ddfc0 9112 if (IS_ELF
252b5132
RH		 9113#ifdef TE_PE
9114 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9115#endif
9116 )
9117 value += fixP->fx_where + fixP->fx_frag->fr_address;
9118#endif
9119#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9120 if (IS_ELF)
252b5132 9121 {
6539b54b 9122 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9123
6539b54b 9124 if ((sym_seg == seg
2f66722d 9125 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9126 && sym_seg != absolute_section))
af65af87 9127 && !generic_force_reloc (fixP))
2f66722d
AM		 9128 {
9129 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9130 bfd_install_relocation subtracts them out again. I think
9131 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9132 it. FIXME. */
9133 value += fixP->fx_where + fixP->fx_frag->fr_address;
9134 }
252b5132
RH		 9135 }
9136#endif
9137#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9138 /* For some reason, the PE format does not store a
9139 section address offset for a PC relative symbol. */
9140 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9141 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9142 value += md_pcrel_from (fixP);
9143#endif
9144 }
fbeb56a4
DK		 9145#if defined (OBJ_COFF) && defined (TE_PE)
9146 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9147 {
9148 value -= S_GET_VALUE (fixP->fx_addsy);
9149 }
9150#endif
252b5132
RH		 9151
9152 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9153 and we must not disappoint it. */
252b5132 9154#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9155 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9156 switch (fixP->fx_r_type)
9157 {
9158 case BFD_RELOC_386_PLT32:
3e73aa7c 9159 case BFD_RELOC_X86_64_PLT32:
c3320543 9160 case BFD_RELOC_X86_64_PLT32_BND:
47926f60
KH		 9161 /* Make the jump instruction point to the address of the operand. At
9162 runtime we merely add the offset to the actual PLT entry. */
9163 value = -4;
9164 break;
31312f95 9165
13ae64f3
JJ		 9166 case BFD_RELOC_386_TLS_GD:
9167 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9168 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9169 case BFD_RELOC_386_TLS_IE:
9170 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9171 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9172 case BFD_RELOC_X86_64_TLSGD:
9173 case BFD_RELOC_X86_64_TLSLD:
9174 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9175 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9176 value = 0; /* Fully resolved at runtime. No addend. */
9177 /* Fallthrough */
9178 case BFD_RELOC_386_TLS_LE:
9179 case BFD_RELOC_386_TLS_LDO_32:
9180 case BFD_RELOC_386_TLS_LE_32:
9181 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9182 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9183 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9184 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9185 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9186 break;
9187
67a4f2b7
AO		 9188 case BFD_RELOC_386_TLS_DESC_CALL:
9189 case BFD_RELOC_X86_64_TLSDESC_CALL:
9190 value = 0; /* Fully resolved at runtime. No addend. */
9191 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9192 fixP->fx_done = 0;
9193 return;
9194
00f7efb6
JJ		 9195 case BFD_RELOC_386_GOT32:
9196 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 9197 value = 0; /* Fully resolved at runtime. No addend. */
9198 break;
47926f60
KH		 9199
9200 case BFD_RELOC_VTABLE_INHERIT:
9201 case BFD_RELOC_VTABLE_ENTRY:
9202 fixP->fx_done = 0;
94f592af 9203 return;
47926f60
KH		 9204
9205 default:
9206 break;
9207 }
9208#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9209 *valP = value;
f86103b7 9210#endif /* !defined (TE_Mach) */
3e73aa7c 9211
3e73aa7c 9212 /* Are we finished with this relocation now? */
c6682705 9213 if (fixP->fx_addsy == NULL)
3e73aa7c 9214 fixP->fx_done = 1;
fbeb56a4
DK		 9215#if defined (OBJ_COFF) && defined (TE_PE)
9216 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9217 {
9218 fixP->fx_done = 0;
9219 /* Remember value for tc_gen_reloc. */
9220 fixP->fx_addnumber = value;
9221 /* Clear out the frag for now. */
9222 value = 0;
9223 }
9224#endif
3e73aa7c
JH		 9225 else if (use_rela_relocations)
9226 {
9227 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9228 /* Remember value for tc_gen_reloc. */
9229 fixP->fx_addnumber = value;
3e73aa7c
JH		 9230 value = 0;
9231 }
f86103b7 9232
94f592af 9233 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9234}
252b5132 9235\f
252b5132 9236char *
499ac353 9237md_atof (int type, char *litP, int *sizeP)
252b5132 9238{
499ac353
NC		 9239 /* This outputs the LITTLENUMs in REVERSE order;
9240 in accord with the bigendian 386. */
9241 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9242}
9243\f
2d545b82 9244static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9245
252b5132 9246static char *
e3bb37b5 9247output_invalid (int c)
252b5132 9248{
3882b010 9249 if (ISPRINT (c))
f9f21a03
L		 9250 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9251 "'%c'", c);
252b5132 9252 else
f9f21a03 9253 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9254 "(0x%x)", (unsigned char) c);
252b5132
RH		 9255 return output_invalid_buf;
9256}
9257
af6bdddf 9258/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9259
9260static const reg_entry *
4d1bb795 9261parse_real_register (char *reg_string, char **end_op)
252b5132 9262{
af6bdddf
AM		 9263 char *s = reg_string;
9264 char *p;
252b5132
RH		 9265 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9266 const reg_entry *r;
9267
9268 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9269 if (*s == REGISTER_PREFIX)
9270 ++s;
9271
9272 if (is_space_char (*s))
9273 ++s;
9274
9275 p = reg_name_given;
af6bdddf 9276 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9277 {
9278 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9279 return (const reg_entry *) NULL;
9280 s++;
252b5132
RH		 9281 }
9282
6588847e
DN		 9283 /* For naked regs, make sure that we are not dealing with an identifier.
9284 This prevents confusing an identifier like `eax_var' with register
9285 `eax'. */
9286 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9287 return (const reg_entry *) NULL;
9288
af6bdddf 9289 *end_op = s;
252b5132
RH		 9290
9291 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9292
5f47d35b 9293 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9294 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9295 {
5f47d35b
AM		 9296 if (is_space_char (*s))
9297 ++s;
9298 if (*s == '(')
9299 {
af6bdddf 9300 ++s;
5f47d35b
AM		 9301 if (is_space_char (*s))
9302 ++s;
9303 if (*s >= '0' && *s <= '7')
9304 {
db557034 9305 int fpr = *s - '0';
af6bdddf 9306 ++s;
5f47d35b
AM		 9307 if (is_space_char (*s))
9308 ++s;
9309 if (*s == ')')
9310 {
9311 *end_op = s + 1;
1e9cc1c2 9312 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9313 know (r);
9314 return r + fpr;
5f47d35b 9315 }
5f47d35b 9316 }
47926f60 9317 /* We have "%st(" then garbage. */
5f47d35b
AM		 9318 return (const reg_entry *) NULL;
9319 }
9320 }
9321
a60de03c
JB		 9322 if (r == NULL || allow_pseudo_reg)
9323 return r;
9324
0dfbf9d7 9325 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9326 return (const reg_entry *) NULL;
9327
192dc9c6
JB		 9328 if ((r->reg_type.bitfield.reg32
9329 || r->reg_type.bitfield.sreg3
9330 || r->reg_type.bitfield.control
9331 || r->reg_type.bitfield.debug
9332 || r->reg_type.bitfield.test)
9333 && !cpu_arch_flags.bitfield.cpui386)
9334 return (const reg_entry *) NULL;
9335
309d3373
JB		 9336 if (r->reg_type.bitfield.floatreg
9337 && !cpu_arch_flags.bitfield.cpu8087
9338 && !cpu_arch_flags.bitfield.cpu287
9339 && !cpu_arch_flags.bitfield.cpu387)
9340 return (const reg_entry *) NULL;
9341
192dc9c6
JB		 9342 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9343 return (const reg_entry *) NULL;
9344
9345 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9346 return (const reg_entry *) NULL;
9347
40f12533
L		 9348 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9349 return (const reg_entry *) NULL;
9350
43234a1e
L		 9351 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9352 && !cpu_arch_flags.bitfield.cpuavx512f)
9353 return (const reg_entry *) NULL;
9354
db51cc60 9355 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9356 if (!allow_index_reg
db51cc60
L		 9357 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9358 return (const reg_entry *) NULL;
9359
43234a1e
L		 9360 /* Upper 16 vector register is only available with VREX in 64bit
9361 mode. */
9362 if ((r->reg_flags & RegVRex))
9363 {
9364 if (!cpu_arch_flags.bitfield.cpuvrex
9365 || flag_code != CODE_64BIT)
9366 return (const reg_entry *) NULL;
9367
9368 i.need_vrex = 1;
9369 }
9370
a60de03c
JB		 9371 if (((r->reg_flags & (RegRex64 | RegRex))
9372 || r->reg_type.bitfield.reg64)
40fb9820 9373 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9374 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9375 && flag_code != CODE_64BIT)
20f0a1fc 9376 return (const reg_entry *) NULL;
1ae00879 9377
b7240065
JB		 9378 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9379 return (const reg_entry *) NULL;
9380
252b5132
RH		 9381 return r;
9382}
4d1bb795
JB		 9383
9384/* REG_STRING starts *before* REGISTER_PREFIX. */
9385
9386static const reg_entry *
9387parse_register (char *reg_string, char **end_op)
9388{
9389 const reg_entry *r;
9390
9391 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9392 r = parse_real_register (reg_string, end_op);
9393 else
9394 r = NULL;
9395 if (!r)
9396 {
9397 char *save = input_line_pointer;
9398 char c;
9399 symbolS *symbolP;
9400
9401 input_line_pointer = reg_string;
9402 c = get_symbol_end ();
9403 symbolP = symbol_find (reg_string);
9404 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9405 {
9406 const expressionS *e = symbol_get_value_expression (symbolP);
9407
0398aac5 9408 know (e->X_op == O_register);
4eed87de 9409 know (e->X_add_number >= 0
c3fe08fa 9410 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 9411 r = i386_regtab + e->X_add_number;
9412 *end_op = input_line_pointer;
9413 }
9414 *input_line_pointer = c;
9415 input_line_pointer = save;
9416 }
9417 return r;
9418}
9419
9420int
9421i386_parse_name (char *name, expressionS *e, char *nextcharP)
9422{
9423 const reg_entry *r;
9424 char *end = input_line_pointer;
9425
9426 *end = *nextcharP;
9427 r = parse_register (name, &input_line_pointer);
9428 if (r && end <= input_line_pointer)
9429 {
9430 *nextcharP = *input_line_pointer;
9431 *input_line_pointer = 0;
9432 e->X_op = O_register;
9433 e->X_add_number = r - i386_regtab;
9434 return 1;
9435 }
9436 input_line_pointer = end;
9437 *end = 0;
ee86248c 9438 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9439}
9440
9441void
9442md_operand (expressionS *e)
9443{
ee86248c
JB		 9444 char *end;
9445 const reg_entry *r;
4d1bb795 9446
ee86248c
JB		 9447 switch (*input_line_pointer)
9448 {
9449 case REGISTER_PREFIX:
9450 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9451 if (r)
9452 {
9453 e->X_op = O_register;
9454 e->X_add_number = r - i386_regtab;
9455 input_line_pointer = end;
9456 }
ee86248c
JB		 9457 break;
9458
9459 case '[':
9c2799c2 9460 gas_assert (intel_syntax);
ee86248c
JB		 9461 end = input_line_pointer++;
9462 expression (e);
9463 if (*input_line_pointer == ']')
9464 {
9465 ++input_line_pointer;
9466 e->X_op_symbol = make_expr_symbol (e);
9467 e->X_add_symbol = NULL;
9468 e->X_add_number = 0;
9469 e->X_op = O_index;
9470 }
9471 else
9472 {
9473 e->X_op = O_absent;
9474 input_line_pointer = end;
9475 }
9476 break;
4d1bb795
JB		 9477 }
9478}
9479
252b5132 9480\f
4cc782b5 9481#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9482const char *md_shortopts = "kVQ:sqn";
252b5132 9483#else
12b55ccc 9484const char *md_shortopts = "qn";
252b5132 9485#endif
6e0b89ee 9486
3e73aa7c 9487#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9488#define OPTION_64 (OPTION_MD_BASE + 1)
9489#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9490#define OPTION_MARCH (OPTION_MD_BASE + 3)
9491#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9492#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9493#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9494#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9495#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9496#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9497#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9498#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9499#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9500#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9501#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9502#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9503#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9504#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9505#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
b3b91714 9506
99ad8390
NC		 9507struct option md_longopts[] =
9508{
3e73aa7c 9509 {"32", no_argument, NULL, OPTION_32},
321098a5 9510#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9511 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9512 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9513#endif
9514#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9515 {"x32", no_argument, NULL, OPTION_X32},
6e0b89ee 9516#endif
b3b91714 9517 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9518 {"march", required_argument, NULL, OPTION_MARCH},
9519 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9520 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9521 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9522 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9523 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9524 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9525 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9526 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9527 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9528 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9529 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9530 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9531 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9532# if defined (TE_PE) || defined (TE_PEP)
9533 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9534#endif
252b5132
RH		 9535 {NULL, no_argument, NULL, 0}
9536};
9537size_t md_longopts_size = sizeof (md_longopts);
9538
9539int
9103f4f4 9540md_parse_option (int c, char *arg)
252b5132 9541{
91d6fa6a 9542 unsigned int j;
6305a203 9543 char *arch, *next;
9103f4f4 9544
252b5132
RH		 9545 switch (c)
9546 {
12b55ccc
L		 9547 case 'n':
9548 optimize_align_code = 0;
9549 break;
9550
a38cf1db
AM		 9551 case 'q':
9552 quiet_warnings = 1;
252b5132
RH		 9553 break;
9554
9555#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9556 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9557 should be emitted or not. FIXME: Not implemented. */
9558 case 'Q':
252b5132
RH		 9559 break;
9560
9561 /* -V: SVR4 argument to print version ID. */
9562 case 'V':
9563 print_version_id ();
9564 break;
9565
a38cf1db
AM		 9566 /* -k: Ignore for FreeBSD compatibility. */
9567 case 'k':
252b5132 9568 break;
4cc782b5
ILT		 9569
9570 case 's':
9571 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9572 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9573 break;
99ad8390 9574#endif
321098a5 9575#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9576 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9577 case OPTION_64:
9578 {
9579 const char **list, **l;
9580
3e73aa7c
JH		 9581 list = bfd_target_list ();
9582 for (l = list; *l != NULL; l++)
8620418b 9583 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9584 || strcmp (*l, "coff-x86-64") == 0
9585 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9586 || strcmp (*l, "pei-x86-64") == 0
9587 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9588 {
9589 default_arch = "x86_64";
9590 break;
9591 }
3e73aa7c 9592 if (*l == NULL)
2b5d6a91 9593 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9594 free (list);
9595 }
9596 break;
9597#endif
252b5132 9598
351f65ca 9599#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9600 case OPTION_X32:
351f65ca
L		 9601 if (IS_ELF)
9602 {
9603 const char **list, **l;
9604
9605 list = bfd_target_list ();
9606 for (l = list; *l != NULL; l++)
9607 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9608 {
9609 default_arch = "x86_64:32";
9610 break;
9611 }
9612 if (*l == NULL)
2b5d6a91 9613 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9614 free (list);
9615 }
9616 else
9617 as_fatal (_("32bit x86_64 is only supported for ELF"));
9618 break;
9619#endif
9620
6e0b89ee
AM		 9621 case OPTION_32:
9622 default_arch = "i386";
9623 break;
9624
b3b91714
AM		 9625 case OPTION_DIVIDE:
9626#ifdef SVR4_COMMENT_CHARS
9627 {
9628 char *n, *t;
9629 const char *s;
9630
9631 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
9632 t = n;
9633 for (s = i386_comment_chars; *s != '\0'; s++)
9634 if (*s != '/')
9635 *t++ = *s;
9636 *t = '\0';
9637 i386_comment_chars = n;
9638 }
9639#endif
9640 break;
9641
9103f4f4 9642 case OPTION_MARCH:
6305a203
L		 9643 arch = xstrdup (arg);
9644 do
9103f4f4 9645 {
6305a203 9646 if (*arch == '.')
2b5d6a91 9647 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9648 next = strchr (arch, '+');
9649 if (next)
9650 *next++ = '\0';
91d6fa6a 9651 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9652 {
91d6fa6a 9653 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9654 {
6305a203 9655 /* Processor. */
1ded5609
JB		 9656 if (! cpu_arch[j].flags.bitfield.cpui386)
9657 continue;
9658
91d6fa6a 9659 cpu_arch_name = cpu_arch[j].name;
6305a203 9660 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9661 cpu_arch_flags = cpu_arch[j].flags;
9662 cpu_arch_isa = cpu_arch[j].type;
9663 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9664 if (!cpu_arch_tune_set)
9665 {
9666 cpu_arch_tune = cpu_arch_isa;
9667 cpu_arch_tune_flags = cpu_arch_isa_flags;
9668 }
9669 break;
9670 }
91d6fa6a
NC		 9671 else if (*cpu_arch [j].name == '.'
9672 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9673 {
9674 /* ISA entension. */
9675 i386_cpu_flags flags;
309d3373 9676
49021df2 9677 if (!cpu_arch[j].negated)
309d3373 9678 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 9679 cpu_arch[j].flags);
309d3373
JB		 9680 else
9681 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 9682 cpu_arch[j].flags);
0dfbf9d7 9683 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 9684 {
9685 if (cpu_sub_arch_name)
9686 {
9687 char *name = cpu_sub_arch_name;
9688 cpu_sub_arch_name = concat (name,
91d6fa6a 9689 cpu_arch[j].name,
1bf57e9f 9690 (const char *) NULL);
6305a203
L		 9691 free (name);
9692 }
9693 else
91d6fa6a 9694 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 9695 cpu_arch_flags = flags;
a586129e 9696 cpu_arch_isa_flags = flags;
6305a203
L		 9697 }
9698 break;
ccc9c027 9699 }
9103f4f4 9700 }
6305a203 9701
91d6fa6a 9702 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9703 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9704
9705 arch = next;
9103f4f4 9706 }
6305a203 9707 while (next != NULL );
9103f4f4
L		 9708 break;
9709
9710 case OPTION_MTUNE:
9711 if (*arg == '.')
2b5d6a91 9712 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 9713 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9714 {
91d6fa6a 9715 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 9716 {
ccc9c027 9717 cpu_arch_tune_set = 1;
91d6fa6a
NC		 9718 cpu_arch_tune = cpu_arch [j].type;
9719 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 9720 break;
9721 }
9722 }
91d6fa6a 9723 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9724 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 9725 break;
9726
1efbbeb4
L		 9727 case OPTION_MMNEMONIC:
9728 if (strcasecmp (arg, "att") == 0)
9729 intel_mnemonic = 0;
9730 else if (strcasecmp (arg, "intel") == 0)
9731 intel_mnemonic = 1;
9732 else
2b5d6a91 9733 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 9734 break;
9735
9736 case OPTION_MSYNTAX:
9737 if (strcasecmp (arg, "att") == 0)
9738 intel_syntax = 0;
9739 else if (strcasecmp (arg, "intel") == 0)
9740 intel_syntax = 1;
9741 else
2b5d6a91 9742 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 9743 break;
9744
9745 case OPTION_MINDEX_REG:
9746 allow_index_reg = 1;
9747 break;
9748
9749 case OPTION_MNAKED_REG:
9750 allow_naked_reg = 1;
9751 break;
9752
9753 case OPTION_MOLD_GCC:
9754 old_gcc = 1;
1efbbeb4
L		 9755 break;
9756
c0f3af97
L		 9757 case OPTION_MSSE2AVX:
9758 sse2avx = 1;
9759 break;
9760
daf50ae7
L		 9761 case OPTION_MSSE_CHECK:
9762 if (strcasecmp (arg, "error") == 0)
7bab8ab5 9763 sse_check = check_error;
daf50ae7 9764 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 9765 sse_check = check_warning;
daf50ae7 9766 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 9767 sse_check = check_none;
daf50ae7 9768 else
2b5d6a91 9769 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 9770 break;
9771
7bab8ab5
JB		 9772 case OPTION_MOPERAND_CHECK:
9773 if (strcasecmp (arg, "error") == 0)
9774 operand_check = check_error;
9775 else if (strcasecmp (arg, "warning") == 0)
9776 operand_check = check_warning;
9777 else if (strcasecmp (arg, "none") == 0)
9778 operand_check = check_none;
9779 else
9780 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
9781 break;
9782
539f890d
L		 9783 case OPTION_MAVXSCALAR:
9784 if (strcasecmp (arg, "128") == 0)
9785 avxscalar = vex128;
9786 else if (strcasecmp (arg, "256") == 0)
9787 avxscalar = vex256;
9788 else
2b5d6a91 9789 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 9790 break;
9791
7e8b059b
L		 9792 case OPTION_MADD_BND_PREFIX:
9793 add_bnd_prefix = 1;
9794 break;
9795
43234a1e
L		 9796 case OPTION_MEVEXLIG:
9797 if (strcmp (arg, "128") == 0)
9798 evexlig = evexl128;
9799 else if (strcmp (arg, "256") == 0)
9800 evexlig = evexl256;
9801 else if (strcmp (arg, "512") == 0)
9802 evexlig = evexl512;
9803 else
9804 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
9805 break;
9806
9807 case OPTION_MEVEXWIG:
9808 if (strcmp (arg, "0") == 0)
9809 evexwig = evexw0;
9810 else if (strcmp (arg, "1") == 0)
9811 evexwig = evexw1;
9812 else
9813 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
9814 break;
9815
167ad85b
TG		 9816# if defined (TE_PE) || defined (TE_PEP)
9817 case OPTION_MBIG_OBJ:
9818 use_big_obj = 1;
9819 break;
9820#endif
9821
252b5132
RH		 9822 default:
9823 return 0;
9824 }
9825 return 1;
9826}
9827
8a2c8fef
L		 9828#define MESSAGE_TEMPLATE \
9829" "
9830
9831static void
1ded5609 9832show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 9833{
9834 static char message[] = MESSAGE_TEMPLATE;
9835 char *start = message + 27;
9836 char *p;
9837 int size = sizeof (MESSAGE_TEMPLATE);
9838 int left;
9839 const char *name;
9840 int len;
9841 unsigned int j;
9842
9843 p = start;
9844 left = size - (start - message);
9845 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9846 {
9847 /* Should it be skipped? */
9848 if (cpu_arch [j].skip)
9849 continue;
9850
9851 name = cpu_arch [j].name;
9852 len = cpu_arch [j].len;
9853 if (*name == '.')
9854 {
9855 /* It is an extension. Skip if we aren't asked to show it. */
9856 if (ext)
9857 {
9858 name++;
9859 len--;
9860 }
9861 else
9862 continue;
9863 }
9864 else if (ext)
9865 {
9866 /* It is an processor. Skip if we show only extension. */
9867 continue;
9868 }
1ded5609
JB		 9869 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
9870 {
9871 /* It is an impossible processor - skip. */
9872 continue;
9873 }
8a2c8fef
L		 9874
9875 /* Reserve 2 spaces for ", " or ",\0" */
9876 left -= len + 2;
9877
9878 /* Check if there is any room. */
9879 if (left >= 0)
9880 {
9881 if (p != start)
9882 {
9883 *p++ = ',';
9884 *p++ = ' ';
9885 }
9886 p = mempcpy (p, name, len);
9887 }
9888 else
9889 {
9890 /* Output the current message now and start a new one. */
9891 *p++ = ',';
9892 *p = '\0';
9893 fprintf (stream, "%s\n", message);
9894 p = start;
9895 left = size - (start - message) - len - 2;
8d63c93e 9896
8a2c8fef
L		 9897 gas_assert (left >= 0);
9898
9899 p = mempcpy (p, name, len);
9900 }
9901 }
9902
9903 *p = '\0';
9904 fprintf (stream, "%s\n", message);
9905}
9906
252b5132 9907void
8a2c8fef 9908md_show_usage (FILE *stream)
252b5132 9909{
4cc782b5
ILT		 9910#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9911 fprintf (stream, _("\
a38cf1db
AM		 9912 -Q ignored\n\
9913 -V print assembler version number\n\
b3b91714
AM		 9914 -k ignored\n"));
9915#endif
9916 fprintf (stream, _("\
12b55ccc 9917 -n Do not optimize code alignment\n\
b3b91714
AM		 9918 -q quieten some warnings\n"));
9919#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9920 fprintf (stream, _("\
a38cf1db 9921 -s ignored\n"));
b3b91714 9922#endif
321098a5
L		 9923#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9924 || defined (TE_PE) || defined (TE_PEP))
751d281c 9925 fprintf (stream, _("\
570561f7 9926 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 9927#endif
b3b91714
AM		 9928#ifdef SVR4_COMMENT_CHARS
9929 fprintf (stream, _("\
9930 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 9931#else
9932 fprintf (stream, _("\
b3b91714 9933 --divide ignored\n"));
4cc782b5 9934#endif
9103f4f4 9935 fprintf (stream, _("\
6305a203 9936 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 9937 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 9938 show_arch (stream, 0, 1);
8a2c8fef
L		 9939 fprintf (stream, _("\
9940 EXTENSION is combination of:\n"));
1ded5609 9941 show_arch (stream, 1, 0);
6305a203 9942 fprintf (stream, _("\
8a2c8fef 9943 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 9944 show_arch (stream, 0, 0);
ba104c83 9945 fprintf (stream, _("\
c0f3af97
L		 9946 -msse2avx encode SSE instructions with VEX prefix\n"));
9947 fprintf (stream, _("\
daf50ae7
L		 9948 -msse-check=[none|error|warning]\n\
9949 check SSE instructions\n"));
9950 fprintf (stream, _("\
7bab8ab5
JB		 9951 -moperand-check=[none|error|warning]\n\
9952 check operand combinations for validity\n"));
9953 fprintf (stream, _("\
539f890d
L		 9954 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
9955 length\n"));
9956 fprintf (stream, _("\
43234a1e
L		 9957 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
9958 length\n"));
9959 fprintf (stream, _("\
9960 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
9961 for EVEX.W bit ignored instructions\n"));
9962 fprintf (stream, _("\
ba104c83
L		 9963 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
9964 fprintf (stream, _("\
9965 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
9966 fprintf (stream, _("\
9967 -mindex-reg support pseudo index registers\n"));
9968 fprintf (stream, _("\
9969 -mnaked-reg don't require `%%' prefix for registers\n"));
9970 fprintf (stream, _("\
9971 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 9972 fprintf (stream, _("\
9973 -madd-bnd-prefix add BND prefix for all valid branches\n"));
167ad85b
TG		 9974# if defined (TE_PE) || defined (TE_PEP)
9975 fprintf (stream, _("\
9976 -mbig-obj generate big object files\n"));
9977#endif
252b5132
RH		 9978}
9979
3e73aa7c 9980#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 9981 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 9982 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 9983
9984/* Pick the target format to use. */
9985
47926f60 9986const char *
e3bb37b5 9987i386_target_format (void)
252b5132 9988{
351f65ca
L		 9989 if (!strncmp (default_arch, "x86_64", 6))
9990 {
9991 update_code_flag (CODE_64BIT, 1);
9992 if (default_arch[6] == '\0')
7f56bc95 9993 x86_elf_abi = X86_64_ABI;
351f65ca 9994 else
7f56bc95 9995 x86_elf_abi = X86_64_X32_ABI;
351f65ca 9996 }
3e73aa7c 9997 else if (!strcmp (default_arch, "i386"))
78f12dd3 9998 update_code_flag (CODE_32BIT, 1);
3e73aa7c 9999 else
2b5d6a91 10000 as_fatal (_("unknown architecture"));
89507696
JB		 10001
10002 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10003 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10004 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10005 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10006
252b5132
RH		 10007 switch (OUTPUT_FLAVOR)
10008 {
9384f2ff 10009#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10010 case bfd_target_aout_flavour:
47926f60 10011 return AOUT_TARGET_FORMAT;
4c63da97 10012#endif
9384f2ff
AM		 10013#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10014# if defined (TE_PE) || defined (TE_PEP)
10015 case bfd_target_coff_flavour:
167ad85b
TG		 10016 if (flag_code == CODE_64BIT)
10017 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10018 else
10019 return "pe-i386";
9384f2ff 10020# elif defined (TE_GO32)
0561d57c
JK		 10021 case bfd_target_coff_flavour:
10022 return "coff-go32";
9384f2ff 10023# else
252b5132
RH		 10024 case bfd_target_coff_flavour:
10025 return "coff-i386";
9384f2ff 10026# endif
4c63da97 10027#endif
3e73aa7c 10028#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10029 case bfd_target_elf_flavour:
3e73aa7c 10030 {
351f65ca
L		 10031 const char *format;
10032
10033 switch (x86_elf_abi)
4fa24527 10034 {
351f65ca
L		 10035 default:
10036 format = ELF_TARGET_FORMAT;
10037 break;
7f56bc95 10038 case X86_64_ABI:
351f65ca 10039 use_rela_relocations = 1;
4fa24527 10040 object_64bit = 1;
351f65ca
L		 10041 format = ELF_TARGET_FORMAT64;
10042 break;
7f56bc95 10043 case X86_64_X32_ABI:
4fa24527 10044 use_rela_relocations = 1;
351f65ca 10045 object_64bit = 1;
862be3fb 10046 disallow_64bit_reloc = 1;
351f65ca
L		 10047 format = ELF_TARGET_FORMAT32;
10048 break;
4fa24527 10049 }
3632d14b 10050 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10051 {
7f56bc95 10052 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10053 as_fatal (_("Intel L1OM is 64bit only"));
10054 return ELF_TARGET_L1OM_FORMAT;
10055 }
7a9068fe
L		 10056 if (cpu_arch_isa == PROCESSOR_K1OM)
10057 {
10058 if (x86_elf_abi != X86_64_ABI)
10059 as_fatal (_("Intel K1OM is 64bit only"));
10060 return ELF_TARGET_K1OM_FORMAT;
10061 }
8a9036a4 10062 else
351f65ca 10063 return format;
3e73aa7c 10064 }
e57f8c65
TG		 10065#endif
10066#if defined (OBJ_MACH_O)
10067 case bfd_target_mach_o_flavour:
d382c579
TG		 10068 if (flag_code == CODE_64BIT)
10069 {
10070 use_rela_relocations = 1;
10071 object_64bit = 1;
10072 return "mach-o-x86-64";
10073 }
10074 else
10075 return "mach-o-i386";
4c63da97 10076#endif
252b5132
RH		 10077 default:
10078 abort ();
10079 return NULL;
10080 }
10081}
10082
47926f60 10083#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 10084
10085#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 10086void
10087i386_elf_emit_arch_note (void)
a847613f 10088{
718ddfc0 10089 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 10090 {
10091 char *p;
10092 asection *seg = now_seg;
10093 subsegT subseg = now_subseg;
10094 Elf_Internal_Note i_note;
10095 Elf_External_Note e_note;
10096 asection *note_secp;
10097 int len;
10098
10099 /* Create the .note section. */
10100 note_secp = subseg_new (".note", 0);
10101 bfd_set_section_flags (stdoutput,
10102 note_secp,
10103 SEC_HAS_CONTENTS | SEC_READONLY);
10104
10105 /* Process the arch string. */
10106 len = strlen (cpu_arch_name);
10107
10108 i_note.namesz = len + 1;
10109 i_note.descsz = 0;
10110 i_note.type = NT_ARCH;
10111 p = frag_more (sizeof (e_note.namesz));
10112 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
10113 p = frag_more (sizeof (e_note.descsz));
10114 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
10115 p = frag_more (sizeof (e_note.type));
10116 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
10117 p = frag_more (len + 1);
10118 strcpy (p, cpu_arch_name);
10119
10120 frag_align (2, 0, 0);
10121
10122 subseg_set (seg, subseg);
10123 }
10124}
10125#endif
252b5132 10126\f
252b5132 10127symbolS *
7016a5d5 10128md_undefined_symbol (char *name)
252b5132 10129{
18dc2407
ILT		 10130 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10131 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10132 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10133 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10134 {
10135 if (!GOT_symbol)
10136 {
10137 if (symbol_find (name))
10138 as_bad (_("GOT already in symbol table"));
10139 GOT_symbol = symbol_new (name, undefined_section,
10140 (valueT) 0, &zero_address_frag);
10141 };
10142 return GOT_symbol;
10143 }
252b5132
RH		 10144 return 0;
10145}
10146
10147/* Round up a section size to the appropriate boundary. */
47926f60 10148
252b5132 10149valueT
7016a5d5 10150md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10151{
4c63da97
AM		 10152#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10153 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10154 {
10155 /* For a.out, force the section size to be aligned. If we don't do
10156 this, BFD will align it for us, but it will not write out the
10157 final bytes of the section. This may be a bug in BFD, but it is
10158 easier to fix it here since that is how the other a.out targets
10159 work. */
10160 int align;
10161
10162 align = bfd_get_section_alignment (stdoutput, segment);
10163 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
10164 }
252b5132
RH		 10165#endif
10166
10167 return size;
10168}
10169
10170/* On the i386, PC-relative offsets are relative to the start of the
10171 next instruction. That is, the address of the offset, plus its
10172 size, since the offset is always the last part of the insn. */
10173
10174long
e3bb37b5 10175md_pcrel_from (fixS *fixP)
252b5132
RH		 10176{
10177 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10178}
10179
10180#ifndef I386COFF
10181
10182static void
e3bb37b5 10183s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10184{
29b0f896 10185 int temp;
252b5132 10186
8a75718c
JB		 10187#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10188 if (IS_ELF)
10189 obj_elf_section_change_hook ();
10190#endif
252b5132
RH		 10191 temp = get_absolute_expression ();
10192 subseg_set (bss_section, (subsegT) temp);
10193 demand_empty_rest_of_line ();
10194}
10195
10196#endif
10197
252b5132 10198void
e3bb37b5 10199i386_validate_fix (fixS *fixp)
252b5132
RH		 10200{
10201 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
10202 {
23df1078
JH		 10203 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10204 {
4fa24527 10205 if (!object_64bit)
23df1078
JH		 10206 abort ();
10207 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10208 }
10209 else
10210 {
4fa24527 10211 if (!object_64bit)
d6ab8113
JB		 10212 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10213 else
10214 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 10215 }
252b5132
RH		 10216 fixp->fx_subsy = 0;
10217 }
10218}
10219
252b5132 10220arelent *
7016a5d5 10221tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10222{
10223 arelent *rel;
10224 bfd_reloc_code_real_type code;
10225
10226 switch (fixp->fx_r_type)
10227 {
8ce3d284 10228#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10229 case BFD_RELOC_SIZE32:
10230 case BFD_RELOC_SIZE64:
10231 if (S_IS_DEFINED (fixp->fx_addsy)
10232 && !S_IS_EXTERNAL (fixp->fx_addsy))
10233 {
10234 /* Resolve size relocation against local symbol to size of
10235 the symbol plus addend. */
10236 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10237 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10238 && !fits_in_unsigned_long (value))
10239 as_bad_where (fixp->fx_file, fixp->fx_line,
10240 _("symbol size computation overflow"));
10241 fixp->fx_addsy = NULL;
10242 fixp->fx_subsy = NULL;
10243 md_apply_fix (fixp, (valueT *) &value, NULL);
10244 return NULL;
10245 }
8ce3d284 10246#endif
8fd4256d 10247
3e73aa7c 10248 case BFD_RELOC_X86_64_PLT32:
c3320543 10249 case BFD_RELOC_X86_64_PLT32_BND:
3e73aa7c
JH		 10250 case BFD_RELOC_X86_64_GOT32:
10251 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 10252 case BFD_RELOC_386_PLT32:
10253 case BFD_RELOC_386_GOT32:
10254 case BFD_RELOC_386_GOTOFF:
10255 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10256 case BFD_RELOC_386_TLS_GD:
10257 case BFD_RELOC_386_TLS_LDM:
10258 case BFD_RELOC_386_TLS_LDO_32:
10259 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10260 case BFD_RELOC_386_TLS_IE:
10261 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10262 case BFD_RELOC_386_TLS_LE_32:
10263 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10264 case BFD_RELOC_386_TLS_GOTDESC:
10265 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10266 case BFD_RELOC_X86_64_TLSGD:
10267 case BFD_RELOC_X86_64_TLSLD:
10268 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10269 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10270 case BFD_RELOC_X86_64_GOTTPOFF:
10271 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10272 case BFD_RELOC_X86_64_TPOFF64:
10273 case BFD_RELOC_X86_64_GOTOFF64:
10274 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10275 case BFD_RELOC_X86_64_GOT64:
10276 case BFD_RELOC_X86_64_GOTPCREL64:
10277 case BFD_RELOC_X86_64_GOTPC64:
10278 case BFD_RELOC_X86_64_GOTPLT64:
10279 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10280 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10281 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10282 case BFD_RELOC_RVA:
10283 case BFD_RELOC_VTABLE_ENTRY:
10284 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10285#ifdef TE_PE
10286 case BFD_RELOC_32_SECREL:
10287#endif
252b5132
RH		 10288 code = fixp->fx_r_type;
10289 break;
dbbaec26
L		 10290 case BFD_RELOC_X86_64_32S:
10291 if (!fixp->fx_pcrel)
10292 {
10293 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10294 code = fixp->fx_r_type;
10295 break;
10296 }
252b5132 10297 default:
93382f6d 10298 if (fixp->fx_pcrel)
252b5132 10299 {
93382f6d
AM		 10300 switch (fixp->fx_size)
10301 {
10302 default:
b091f402
AM		 10303 as_bad_where (fixp->fx_file, fixp->fx_line,
10304 _("can not do %d byte pc-relative relocation"),
10305 fixp->fx_size);
93382f6d
AM		 10306 code = BFD_RELOC_32_PCREL;
10307 break;
10308 case 1: code = BFD_RELOC_8_PCREL; break;
10309 case 2: code = BFD_RELOC_16_PCREL; break;
c3320543
L		 10310 case 4:
10311 code = (fixp->fx_r_type == BFD_RELOC_X86_64_PC32_BND
10312 ? fixp-> fx_r_type : BFD_RELOC_32_PCREL);
10313 break;
d6ab8113
JB		 10314#ifdef BFD64
10315 case 8: code = BFD_RELOC_64_PCREL; break;
10316#endif
93382f6d
AM		 10317 }
10318 }
10319 else
10320 {
10321 switch (fixp->fx_size)
10322 {
10323 default:
b091f402
AM		 10324 as_bad_where (fixp->fx_file, fixp->fx_line,
10325 _("can not do %d byte relocation"),
10326 fixp->fx_size);
93382f6d
AM		 10327 code = BFD_RELOC_32;
10328 break;
10329 case 1: code = BFD_RELOC_8; break;
10330 case 2: code = BFD_RELOC_16; break;
10331 case 4: code = BFD_RELOC_32; break;
937149dd 10332#ifdef BFD64
3e73aa7c 10333 case 8: code = BFD_RELOC_64; break;
937149dd 10334#endif
93382f6d 10335 }
252b5132
RH		 10336 }
10337 break;
10338 }
252b5132 10339
d182319b
JB		 10340 if ((code == BFD_RELOC_32
10341 || code == BFD_RELOC_32_PCREL
10342 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10343 && GOT_symbol
10344 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10345 {
4fa24527 10346 if (!object_64bit)
d6ab8113
JB		 10347 code = BFD_RELOC_386_GOTPC;
10348 else
10349 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10350 }
7b81dfbb
AJ		 10351 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10352 && GOT_symbol
10353 && fixp->fx_addsy == GOT_symbol)
10354 {
10355 code = BFD_RELOC_X86_64_GOTPC64;
10356 }
252b5132
RH		 10357
10358 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 10359 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10360 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10361
10362 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10363
3e73aa7c
JH		 10364 if (!use_rela_relocations)
10365 {
10366 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10367 vtable entry to be used in the relocation's section offset. */
10368 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10369 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10370#if defined (OBJ_COFF) && defined (TE_PE)
10371 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10372 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10373 else
10374#endif
c6682705 10375 rel->addend = 0;
3e73aa7c
JH		 10376 }
10377 /* Use the rela in 64bit mode. */
252b5132 10378 else
3e73aa7c 10379 {
862be3fb
L		 10380 if (disallow_64bit_reloc)
10381 switch (code)
10382 {
862be3fb
L		 10383 case BFD_RELOC_X86_64_DTPOFF64:
10384 case BFD_RELOC_X86_64_TPOFF64:
10385 case BFD_RELOC_64_PCREL:
10386 case BFD_RELOC_X86_64_GOTOFF64:
10387 case BFD_RELOC_X86_64_GOT64:
10388 case BFD_RELOC_X86_64_GOTPCREL64:
10389 case BFD_RELOC_X86_64_GOTPC64:
10390 case BFD_RELOC_X86_64_GOTPLT64:
10391 case BFD_RELOC_X86_64_PLTOFF64:
10392 as_bad_where (fixp->fx_file, fixp->fx_line,
10393 _("cannot represent relocation type %s in x32 mode"),
10394 bfd_get_reloc_code_name (code));
10395 break;
10396 default:
10397 break;
10398 }
10399
062cd5e7
AS		 10400 if (!fixp->fx_pcrel)
10401 rel->addend = fixp->fx_offset;
10402 else
10403 switch (code)
10404 {
10405 case BFD_RELOC_X86_64_PLT32:
c3320543 10406 case BFD_RELOC_X86_64_PLT32_BND:
062cd5e7
AS		 10407 case BFD_RELOC_X86_64_GOT32:
10408 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 10409 case BFD_RELOC_X86_64_TLSGD:
10410 case BFD_RELOC_X86_64_TLSLD:
10411 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10412 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10413 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10414 rel->addend = fixp->fx_offset - fixp->fx_size;
10415 break;
10416 default:
10417 rel->addend = (section->vma
10418 - fixp->fx_size
10419 + fixp->fx_addnumber
10420 + md_pcrel_from (fixp));
10421 break;
10422 }
3e73aa7c
JH		 10423 }
10424
252b5132
RH		 10425 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10426 if (rel->howto == NULL)
10427 {
10428 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10429 _("cannot represent relocation type %s"),
252b5132
RH		 10430 bfd_get_reloc_code_name (code));
10431 /* Set howto to a garbage value so that we can keep going. */
10432 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10433 gas_assert (rel->howto != NULL);
252b5132
RH		 10434 }
10435
10436 return rel;
10437}
10438
ee86248c 10439#include "tc-i386-intel.c"
54cfded0 10440
a60de03c
JB		 10441void
10442tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10443{
a60de03c
JB		 10444 int saved_naked_reg;
10445 char saved_register_dot;
54cfded0 10446
a60de03c
JB		 10447 saved_naked_reg = allow_naked_reg;
10448 allow_naked_reg = 1;
10449 saved_register_dot = register_chars['.'];
10450 register_chars['.'] = '.';
10451 allow_pseudo_reg = 1;
10452 expression_and_evaluate (exp);
10453 allow_pseudo_reg = 0;
10454 register_chars['.'] = saved_register_dot;
10455 allow_naked_reg = saved_naked_reg;
10456
e96d56a1 10457 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10458 {
a60de03c
JB		 10459 if ((addressT) exp->X_add_number < i386_regtab_size)
10460 {
10461 exp->X_op = O_constant;
10462 exp->X_add_number = i386_regtab[exp->X_add_number]
10463 .dw2_regnum[flag_code >> 1];
10464 }
10465 else
10466 exp->X_op = O_illegal;
54cfded0 10467 }
54cfded0
AM		 10468}
10469
10470void
10471tc_x86_frame_initial_instructions (void)
10472{
a60de03c
JB		 10473 static unsigned int sp_regno[2];
10474
10475 if (!sp_regno[flag_code >> 1])
10476 {
10477 char *saved_input = input_line_pointer;
10478 char sp[][4] = {"esp", "rsp"};
10479 expressionS exp;
a4447b93 10480
a60de03c
JB		 10481 input_line_pointer = sp[flag_code >> 1];
10482 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10483 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10484 sp_regno[flag_code >> 1] = exp.X_add_number;
10485 input_line_pointer = saved_input;
10486 }
a4447b93 10487
61ff971f
L		 10488 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10489 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10490}
d2b2c203 10491
d7921315
L		 10492int
10493x86_dwarf2_addr_size (void)
10494{
10495#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10496 if (x86_elf_abi == X86_64_X32_ABI)
10497 return 4;
10498#endif
10499 return bfd_arch_bits_per_address (stdoutput) / 8;
10500}
10501
d2b2c203
DJ		 10502int
10503i386_elf_section_type (const char *str, size_t len)
10504{
10505 if (flag_code == CODE_64BIT
10506 && len == sizeof ("unwind") - 1
10507 && strncmp (str, "unwind", 6) == 0)
10508 return SHT_X86_64_UNWIND;
10509
10510 return -1;
10511}
bb41ade5 10512
ad5fec3b
EB		 10513#ifdef TE_SOLARIS
10514void
10515i386_solaris_fix_up_eh_frame (segT sec)
10516{
10517 if (flag_code == CODE_64BIT)
10518 elf_section_type (sec) = SHT_X86_64_UNWIND;
10519}
10520#endif
10521
bb41ade5
AM		 10522#ifdef TE_PE
10523void
10524tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10525{
91d6fa6a 10526 expressionS exp;
bb41ade5 10527
91d6fa6a
NC		 10528 exp.X_op = O_secrel;
10529 exp.X_add_symbol = symbol;
10530 exp.X_add_number = 0;
10531 emit_expr (&exp, size);
bb41ade5
AM		 10532}
10533#endif
3b22753a
L		 10534
10535#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10536/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10537
01e1a5bc 10538bfd_vma
3b22753a
L		 10539x86_64_section_letter (int letter, char **ptr_msg)
10540{
10541 if (flag_code == CODE_64BIT)
10542 {
10543 if (letter == 'l')
10544 return SHF_X86_64_LARGE;
10545
8f3bae45 10546 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10547 }
3b22753a 10548 else
8f3bae45 10549 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10550 return -1;
10551}
10552
01e1a5bc 10553bfd_vma
3b22753a
L		 10554x86_64_section_word (char *str, size_t len)
10555{
8620418b 10556 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10557 return SHF_X86_64_LARGE;
10558
10559 return -1;
10560}
10561
10562static void
10563handle_large_common (int small ATTRIBUTE_UNUSED)
10564{
10565 if (flag_code != CODE_64BIT)
10566 {
10567 s_comm_internal (0, elf_common_parse);
10568 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10569 }
10570 else
10571 {
10572 static segT lbss_section;
10573 asection *saved_com_section_ptr = elf_com_section_ptr;
10574 asection *saved_bss_section = bss_section;
10575
10576 if (lbss_section == NULL)
10577 {
10578 flagword applicable;
10579 segT seg = now_seg;
10580 subsegT subseg = now_subseg;
10581
10582 /* The .lbss section is for local .largecomm symbols. */
10583 lbss_section = subseg_new (".lbss", 0);
10584 applicable = bfd_applicable_section_flags (stdoutput);
10585 bfd_set_section_flags (stdoutput, lbss_section,
10586 applicable & SEC_ALLOC);
10587 seg_info (lbss_section)->bss = 1;
10588
10589 subseg_set (seg, subseg);
10590 }
10591
10592 elf_com_section_ptr = &_bfd_elf_large_com_section;
10593 bss_section = lbss_section;
10594
10595 s_comm_internal (0, elf_common_parse);
10596
10597 elf_com_section_ptr = saved_com_section_ptr;
10598 bss_section = saved_bss_section;
10599 }
10600}
10601#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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