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Regenerate configure in bfd/binutils/gas/gdb
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
b90efa5b 2 Copyright (C) 1989-2015 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
89e7505f
L		 36#ifdef TE_LINUX
37/* Default to compress debug sections for Linux. */
38int flag_compress_debug = 1;
39#endif
40
252b5132
RH		 41#ifndef REGISTER_WARNINGS
42#define REGISTER_WARNINGS 1
43#endif
44
c3332e24 45#ifndef INFER_ADDR_PREFIX
eecb386c 46#define INFER_ADDR_PREFIX 1
c3332e24
AM		 47#endif
48
29b0f896
AM		 49#ifndef DEFAULT_ARCH
50#define DEFAULT_ARCH "i386"
246fcdee 51#endif
252b5132 52
edde18a5
AM		 53#ifndef INLINE
54#if __GNUC__ >= 2
55#define INLINE __inline__
56#else
57#define INLINE
58#endif
59#endif
60
6305a203
L		 61/* Prefixes will be emitted in the order defined below.
62 WAIT_PREFIX must be the first prefix since FWAIT is really is an
63 instruction, and so must come before any prefixes.
64 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 65 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 66#define WAIT_PREFIX 0
67#define SEG_PREFIX 1
68#define ADDR_PREFIX 2
69#define DATA_PREFIX 3
c32fa91d 70#define REP_PREFIX 4
42164a71 71#define HLE_PREFIX REP_PREFIX
7e8b059b 72#define BND_PREFIX REP_PREFIX
c32fa91d
L		 73#define LOCK_PREFIX 5
74#define REX_PREFIX 6 /* must come last. */
75#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 76
77/* we define the syntax here (modulo base,index,scale syntax) */
78#define REGISTER_PREFIX '%'
79#define IMMEDIATE_PREFIX '$'
80#define ABSOLUTE_PREFIX '*'
81
82/* these are the instruction mnemonic suffixes in AT&T syntax or
83 memory operand size in Intel syntax. */
84#define WORD_MNEM_SUFFIX 'w'
85#define BYTE_MNEM_SUFFIX 'b'
86#define SHORT_MNEM_SUFFIX 's'
87#define LONG_MNEM_SUFFIX 'l'
88#define QWORD_MNEM_SUFFIX 'q'
89#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 90#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 91#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 92/* Intel Syntax. Use a non-ascii letter since since it never appears
93 in instructions. */
94#define LONG_DOUBLE_MNEM_SUFFIX '\1'
95
96#define END_OF_INSN '\0'
97
98/*
99 'templates' is for grouping together 'template' structures for opcodes
100 of the same name. This is only used for storing the insns in the grand
101 ole hash table of insns.
102 The templates themselves start at START and range up to (but not including)
103 END.
104 */
105typedef struct
106{
d3ce72d0
NC		 107 const insn_template *start;
108 const insn_template *end;
6305a203
L		 109}
110templates;
111
112/* 386 operand encoding bytes: see 386 book for details of this. */
113typedef struct
114{
115 unsigned int regmem; /* codes register or memory operand */
116 unsigned int reg; /* codes register operand (or extended opcode) */
117 unsigned int mode; /* how to interpret regmem & reg */
118}
119modrm_byte;
120
121/* x86-64 extension prefix. */
122typedef int rex_byte;
123
6305a203
L		 124/* 386 opcode byte to code indirect addressing. */
125typedef struct
126{
127 unsigned base;
128 unsigned index;
129 unsigned scale;
130}
131sib_byte;
132
6305a203
L		 133/* x86 arch names, types and features */
134typedef struct
135{
136 const char *name; /* arch name */
8a2c8fef 137 unsigned int len; /* arch string length */
6305a203
L		 138 enum processor_type type; /* arch type */
139 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 140 unsigned int skip; /* show_arch should skip this. */
22109423 141 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 142}
143arch_entry;
144
78f12dd3 145static void update_code_flag (int, int);
e3bb37b5
L		 146static void set_code_flag (int);
147static void set_16bit_gcc_code_flag (int);
148static void set_intel_syntax (int);
1efbbeb4 149static void set_intel_mnemonic (int);
db51cc60 150static void set_allow_index_reg (int);
7bab8ab5 151static void set_check (int);
e3bb37b5 152static void set_cpu_arch (int);
6482c264 153#ifdef TE_PE
e3bb37b5 154static void pe_directive_secrel (int);
6482c264 155#endif
e3bb37b5
L		 156static void signed_cons (int);
157static char *output_invalid (int c);
ee86248c
JB		 158static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
159 const char *);
160static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
161 const char *);
a7619375 162static int i386_att_operand (char *);
e3bb37b5 163static int i386_intel_operand (char *, int);
ee86248c
JB		 164static int i386_intel_simplify (expressionS *);
165static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 166static const reg_entry *parse_register (char *, char **);
167static char *parse_insn (char *, char *);
168static char *parse_operands (char *, const char *);
169static void swap_operands (void);
4d456e3d 170static void swap_2_operands (int, int);
e3bb37b5
L		 171static void optimize_imm (void);
172static void optimize_disp (void);
d3ce72d0 173static const insn_template *match_template (void);
e3bb37b5
L		 174static int check_string (void);
175static int process_suffix (void);
176static int check_byte_reg (void);
177static int check_long_reg (void);
178static int check_qword_reg (void);
179static int check_word_reg (void);
180static int finalize_imm (void);
181static int process_operands (void);
182static const seg_entry *build_modrm_byte (void);
183static void output_insn (void);
184static void output_imm (fragS *, offsetT);
185static void output_disp (fragS *, offsetT);
29b0f896 186#ifndef I386COFF
e3bb37b5 187static void s_bss (int);
252b5132 188#endif
17d4e2a2
L		 189#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190static void handle_large_common (int small ATTRIBUTE_UNUSED);
191#endif
252b5132 192
a847613f 193static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 194
43234a1e
L		 195/* This struct describes rounding control and SAE in the instruction. */
196struct RC_Operation
197{
198 enum rc_type
199 {
200 rne = 0,
201 rd,
202 ru,
203 rz,
204 saeonly
205 } type;
206 int operand;
207};
208
209static struct RC_Operation rc_op;
210
211/* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214struct Mask_Operation
215{
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
219 int operand;
220};
221
222static struct Mask_Operation mask_op;
223
224/* The struct describes broadcasting, applied to OPERAND. FACTOR is
225 broadcast factor. */
226struct Broadcast_Operation
227{
228 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
229 int type;
230
231 /* Index of broadcasted operand. */
232 int operand;
233};
234
235static struct Broadcast_Operation broadcast_op;
236
c0f3af97
L		 237/* VEX prefix. */
238typedef struct
239{
43234a1e
L		 240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes[4];
c0f3af97
L		 242 unsigned int length;
243 /* Destination or source register specifier. */
244 const reg_entry *register_specifier;
245} vex_prefix;
246
252b5132 247/* 'md_assemble ()' gathers together information and puts it into a
47926f60 248 i386_insn. */
252b5132 249
520dc8e8
AM		 250union i386_op
251 {
252 expressionS *disps;
253 expressionS *imms;
254 const reg_entry *regs;
255 };
256
a65babc9
L		 257enum i386_error
258 {
86e026a4 259 operand_size_mismatch,
a65babc9
L		 260 operand_type_mismatch,
261 register_type_mismatch,
262 number_of_operands_mismatch,
263 invalid_instruction_suffix,
264 bad_imm4,
265 old_gcc_only,
266 unsupported_with_intel_mnemonic,
267 unsupported_syntax,
6c30d220
L		 268 unsupported,
269 invalid_vsib_address,
7bab8ab5 270 invalid_vector_register_set,
43234a1e
L		 271 unsupported_vector_index_register,
272 unsupported_broadcast,
273 broadcast_not_on_src_operand,
274 broadcast_needed,
275 unsupported_masking,
276 mask_not_on_destination,
277 no_default_mask,
278 unsupported_rc_sae,
279 rc_sae_operand_not_last_imm,
280 invalid_register_operand,
281 try_vector_disp8
a65babc9
L		 282 };
283
252b5132
RH		 284struct _i386_insn
285 {
47926f60 286 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 287 insn_template tm;
252b5132 288
7d5e4556
L		 289 /* SUFFIX holds the instruction size suffix for byte, word, dword
290 or qword, if given. */
252b5132
RH		 291 char suffix;
292
47926f60 293 /* OPERANDS gives the number of given operands. */
252b5132
RH		 294 unsigned int operands;
295
296 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
297 of given register, displacement, memory operands and immediate
47926f60 298 operands. */
252b5132
RH		 299 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
300
301 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 302 use OP[i] for the corresponding operand. */
40fb9820 303 i386_operand_type types[MAX_OPERANDS];
252b5132 304
520dc8e8
AM		 305 /* Displacement expression, immediate expression, or register for each
306 operand. */
307 union i386_op op[MAX_OPERANDS];
252b5132 308
3e73aa7c
JH		 309 /* Flags for operands. */
310 unsigned int flags[MAX_OPERANDS];
311#define Operand_PCrel 1
312
252b5132 313 /* Relocation type for operand */
f86103b7 314 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 315
252b5132
RH		 316 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
317 the base index byte below. */
318 const reg_entry *base_reg;
319 const reg_entry *index_reg;
320 unsigned int log2_scale_factor;
321
322 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 323 explicit segment overrides are given. */
ce8a8b2f 324 const seg_entry *seg[2];
252b5132
RH		 325
326 /* PREFIX holds all the given prefix opcodes (usually null).
327 PREFIXES is the number of prefix opcodes. */
328 unsigned int prefixes;
329 unsigned char prefix[MAX_PREFIXES];
330
331 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 332 addressing modes of this insn are encoded. */
252b5132 333 modrm_byte rm;
3e73aa7c 334 rex_byte rex;
43234a1e 335 rex_byte vrex;
252b5132 336 sib_byte sib;
c0f3af97 337 vex_prefix vex;
b6169b20 338
43234a1e
L		 339 /* Masking attributes. */
340 struct Mask_Operation *mask;
341
342 /* Rounding control and SAE attributes. */
343 struct RC_Operation *rounding;
344
345 /* Broadcasting attributes. */
346 struct Broadcast_Operation *broadcast;
347
348 /* Compressed disp8*N attribute. */
349 unsigned int memshift;
350
b6169b20 351 /* Swap operand in encoding. */
4473e004 352 unsigned int swap_operand;
891edac4 353
a501d77e
L		 354 /* Prefer 8bit or 32bit displacement in encoding. */
355 enum
356 {
357 disp_encoding_default = 0,
358 disp_encoding_8bit,
359 disp_encoding_32bit
360 } disp_encoding;
f8a5c266 361
d5de92cf
L		 362 /* REP prefix. */
363 const char *rep_prefix;
364
165de32a
L		 365 /* HLE prefix. */
366 const char *hle_prefix;
42164a71 367
7e8b059b
L		 368 /* Have BND prefix. */
369 const char *bnd_prefix;
370
43234a1e
L		 371 /* Need VREX to support upper 16 registers. */
372 int need_vrex;
373
891edac4 374 /* Error message. */
a65babc9 375 enum i386_error error;
252b5132
RH		 376 };
377
378typedef struct _i386_insn i386_insn;
379
43234a1e
L		 380/* Link RC type with corresponding string, that'll be looked for in
381 asm. */
382struct RC_name
383{
384 enum rc_type type;
385 const char *name;
386 unsigned int len;
387};
388
389static const struct RC_name RC_NamesTable[] =
390{
391 { rne, STRING_COMMA_LEN ("rn-sae") },
392 { rd, STRING_COMMA_LEN ("rd-sae") },
393 { ru, STRING_COMMA_LEN ("ru-sae") },
394 { rz, STRING_COMMA_LEN ("rz-sae") },
395 { saeonly, STRING_COMMA_LEN ("sae") },
396};
397
252b5132
RH		 398/* List of chars besides those in app.c:symbol_chars that can start an
399 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 400const char extra_symbol_chars[] = "*%-([{"
252b5132 401#ifdef LEX_AT
32137342
NC		 402 "@"
403#endif
404#ifdef LEX_QM
405 "?"
252b5132 406#endif
32137342 407 ;
252b5132 408
29b0f896
AM		 409#if (defined (TE_I386AIX) \
410 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 411 && !defined (TE_GNU) \
29b0f896 412 && !defined (TE_LINUX) \
8d63c93e
RM		 413 && !defined (TE_NACL) \
414 && !defined (TE_NETWARE) \
29b0f896 415 && !defined (TE_FreeBSD) \
5b806d27 416 && !defined (TE_DragonFly) \
29b0f896 417 && !defined (TE_NetBSD)))
252b5132 418/* This array holds the chars that always start a comment. If the
b3b91714
AM		 419 pre-processor is disabled, these aren't very useful. The option
420 --divide will remove '/' from this list. */
421const char *i386_comment_chars = "#/";
422#define SVR4_COMMENT_CHARS 1
252b5132 423#define PREFIX_SEPARATOR '\\'
252b5132 424
b3b91714
AM		 425#else
426const char *i386_comment_chars = "#";
427#define PREFIX_SEPARATOR '/'
428#endif
429
252b5132
RH		 430/* This array holds the chars that only start a comment at the beginning of
431 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 432 .line and .file directives will appear in the pre-processed output.
433 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 434 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 435 #NO_APP at the beginning of its output.
436 Also note that comments started like this one will always work if
252b5132 437 '/' isn't otherwise defined. */
b3b91714 438const char line_comment_chars[] = "#/";
252b5132 439
63a0b638 440const char line_separator_chars[] = ";";
252b5132 441
ce8a8b2f
AM		 442/* Chars that can be used to separate mant from exp in floating point
443 nums. */
252b5132
RH		 444const char EXP_CHARS[] = "eE";
445
ce8a8b2f
AM		 446/* Chars that mean this number is a floating point constant
447 As in 0f12.456
448 or 0d1.2345e12. */
252b5132
RH		 449const char FLT_CHARS[] = "fFdDxX";
450
ce8a8b2f 451/* Tables for lexical analysis. */
252b5132
RH		 452static char mnemonic_chars[256];
453static char register_chars[256];
454static char operand_chars[256];
455static char identifier_chars[256];
456static char digit_chars[256];
457
ce8a8b2f 458/* Lexical macros. */
252b5132
RH		 459#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
460#define is_operand_char(x) (operand_chars[(unsigned char) x])
461#define is_register_char(x) (register_chars[(unsigned char) x])
462#define is_space_char(x) ((x) == ' ')
463#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
464#define is_digit_char(x) (digit_chars[(unsigned char) x])
465
0234cb7c 466/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 467static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
468
469/* md_assemble() always leaves the strings it's passed unaltered. To
470 effect this we maintain a stack of saved characters that we've smashed
471 with '\0's (indicating end of strings for various sub-fields of the
47926f60 472 assembler instruction). */
252b5132 473static char save_stack[32];
ce8a8b2f 474static char *save_stack_p;
252b5132
RH		 475#define END_STRING_AND_SAVE(s) \
476 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
477#define RESTORE_END_STRING(s) \
478 do { *(s) = *--save_stack_p; } while (0)
479
47926f60 480/* The instruction we're assembling. */
252b5132
RH		 481static i386_insn i;
482
483/* Possible templates for current insn. */
484static const templates *current_templates;
485
31b2323c
L		 486/* Per instruction expressionS buffers: max displacements & immediates. */
487static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
488static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 489
47926f60 490/* Current operand we are working on. */
ee86248c 491static int this_operand = -1;
252b5132 492
3e73aa7c
JH		 493/* We support four different modes. FLAG_CODE variable is used to distinguish
494 these. */
495
496enum flag_code {
497 CODE_32BIT,
498 CODE_16BIT,
499 CODE_64BIT };
500
501static enum flag_code flag_code;
4fa24527 502static unsigned int object_64bit;
862be3fb 503static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 504static int use_rela_relocations = 0;
505
7af8ed2d
NC		 506#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
507 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
508 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
509
351f65ca
L		 510/* The ELF ABI to use. */
511enum x86_elf_abi
512{
513 I386_ABI,
7f56bc95
L		 514 X86_64_ABI,
515 X86_64_X32_ABI
351f65ca
L		 516};
517
518static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 519#endif
351f65ca 520
167ad85b
TG		 521#if defined (TE_PE) || defined (TE_PEP)
522/* Use big object file format. */
523static int use_big_obj = 0;
524#endif
525
47926f60
KH		 526/* 1 for intel syntax,
527 0 if att syntax. */
528static int intel_syntax = 0;
252b5132 529
1efbbeb4
L		 530/* 1 for intel mnemonic,
531 0 if att mnemonic. */
532static int intel_mnemonic = !SYSV386_COMPAT;
533
5209009a 534/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 535static int old_gcc = OLDGCC_COMPAT;
536
a60de03c
JB		 537/* 1 if pseudo registers are permitted. */
538static int allow_pseudo_reg = 0;
539
47926f60
KH		 540/* 1 if register prefix % not required. */
541static int allow_naked_reg = 0;
252b5132 542
7e8b059b
L		 543/* 1 if the assembler should add BND prefix for all control-tranferring
544 instructions supporting it, even if this prefix wasn't specified
545 explicitly. */
546static int add_bnd_prefix = 0;
547
ba104c83 548/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 549static int allow_index_reg = 0;
550
d022bddd
IT		 551/* 1 if the assembler should ignore LOCK prefix, even if it was
552 specified explicitly. */
553static int omit_lock_prefix = 0;
554
7bab8ab5 555static enum check_kind
daf50ae7 556 {
7bab8ab5
JB		 557 check_none = 0,
558 check_warning,
559 check_error
daf50ae7 560 }
7bab8ab5 561sse_check, operand_check = check_warning;
daf50ae7 562
2ca3ace5
L		 563/* Register prefix used for error message. */
564static const char *register_prefix = "%";
565
47926f60
KH		 566/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
567 leave, push, and pop instructions so that gcc has the same stack
568 frame as in 32 bit mode. */
569static char stackop_size = '\0';
eecb386c 570
12b55ccc
L		 571/* Non-zero to optimize code alignment. */
572int optimize_align_code = 1;
573
47926f60
KH		 574/* Non-zero to quieten some warnings. */
575static int quiet_warnings = 0;
a38cf1db 576
47926f60
KH		 577/* CPU name. */
578static const char *cpu_arch_name = NULL;
6305a203 579static char *cpu_sub_arch_name = NULL;
a38cf1db 580
47926f60 581/* CPU feature flags. */
40fb9820
L		 582static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
583
ccc9c027
L		 584/* If we have selected a cpu we are generating instructions for. */
585static int cpu_arch_tune_set = 0;
586
9103f4f4 587/* Cpu we are generating instructions for. */
fbf3f584 588enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 589
590/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 591static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 592
ccc9c027 593/* CPU instruction set architecture used. */
fbf3f584 594enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 595
9103f4f4 596/* CPU feature flags of instruction set architecture used. */
fbf3f584 597i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 598
fddf5b5b
AM		 599/* If set, conditional jumps are not automatically promoted to handle
600 larger than a byte offset. */
601static unsigned int no_cond_jump_promotion = 0;
602
c0f3af97
L		 603/* Encode SSE instructions with VEX prefix. */
604static unsigned int sse2avx;
605
539f890d
L		 606/* Encode scalar AVX instructions with specific vector length. */
607static enum
608 {
609 vex128 = 0,
610 vex256
611 } avxscalar;
612
43234a1e
L		 613/* Encode scalar EVEX LIG instructions with specific vector length. */
614static enum
615 {
616 evexl128 = 0,
617 evexl256,
618 evexl512
619 } evexlig;
620
621/* Encode EVEX WIG instructions with specific evex.w. */
622static enum
623 {
624 evexw0 = 0,
625 evexw1
626 } evexwig;
627
d3d3c6db
IT		 628/* Value to encode in EVEX RC bits, for SAE-only instructions. */
629static enum rc_type evexrcig = rne;
630
29b0f896 631/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 632static symbolS *GOT_symbol;
29b0f896 633
a4447b93
RH		 634/* The dwarf2 return column, adjusted for 32 or 64 bit. */
635unsigned int x86_dwarf2_return_column;
636
637/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
638int x86_cie_data_alignment;
639
252b5132 640/* Interface to relax_segment.
fddf5b5b
AM		 641 There are 3 major relax states for 386 jump insns because the
642 different types of jumps add different sizes to frags when we're
643 figuring out what sort of jump to choose to reach a given label. */
252b5132 644
47926f60 645/* Types. */
93c2a809
AM		 646#define UNCOND_JUMP 0
647#define COND_JUMP 1
648#define COND_JUMP86 2
fddf5b5b 649
47926f60 650/* Sizes. */
252b5132
RH		 651#define CODE16 1
652#define SMALL 0
29b0f896 653#define SMALL16 (SMALL | CODE16)
252b5132 654#define BIG 2
29b0f896 655#define BIG16 (BIG | CODE16)
252b5132
RH		 656
657#ifndef INLINE
658#ifdef __GNUC__
659#define INLINE __inline__
660#else
661#define INLINE
662#endif
663#endif
664
fddf5b5b
AM		 665#define ENCODE_RELAX_STATE(type, size) \
666 ((relax_substateT) (((type) << 2) | (size)))
667#define TYPE_FROM_RELAX_STATE(s) \
668 ((s) >> 2)
669#define DISP_SIZE_FROM_RELAX_STATE(s) \
670 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 671
672/* This table is used by relax_frag to promote short jumps to long
673 ones where necessary. SMALL (short) jumps may be promoted to BIG
674 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
675 don't allow a short jump in a 32 bit code segment to be promoted to
676 a 16 bit offset jump because it's slower (requires data size
677 prefix), and doesn't work, unless the destination is in the bottom
678 64k of the code segment (The top 16 bits of eip are zeroed). */
679
680const relax_typeS md_relax_table[] =
681{
24eab124
AM		 682 /* The fields are:
683 1) most positive reach of this state,
684 2) most negative reach of this state,
93c2a809 685 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 686 4) which index into the table to try if we can't fit into this one. */
252b5132 687
fddf5b5b 688 /* UNCOND_JUMP states. */
93c2a809
AM		 689 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
690 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
691 /* dword jmp adds 4 bytes to frag:
692 0 extra opcode bytes, 4 displacement bytes. */
252b5132 693 {0, 0, 4, 0},
93c2a809
AM		 694 /* word jmp adds 2 byte2 to frag:
695 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 696 {0, 0, 2, 0},
697
93c2a809
AM		 698 /* COND_JUMP states. */
699 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
700 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
701 /* dword conditionals adds 5 bytes to frag:
702 1 extra opcode byte, 4 displacement bytes. */
703 {0, 0, 5, 0},
fddf5b5b 704 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 705 1 extra opcode byte, 2 displacement bytes. */
706 {0, 0, 3, 0},
707
708 /* COND_JUMP86 states. */
709 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
710 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
711 /* dword conditionals adds 5 bytes to frag:
712 1 extra opcode byte, 4 displacement bytes. */
713 {0, 0, 5, 0},
714 /* word conditionals add 4 bytes to frag:
715 1 displacement byte and a 3 byte long branch insn. */
716 {0, 0, 4, 0}
252b5132
RH		 717};
718
9103f4f4
L		 719static const arch_entry cpu_arch[] =
720{
89507696
JB		 721 /* Do not replace the first two entries - i386_target_format()
722 relies on them being there in this order. */
8a2c8fef 723 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 724 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 725 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 726 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 727 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 728 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 729 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 730 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 731 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 732 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 733 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 734 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 735 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 736 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 737 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 738 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 739 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 740 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 741 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 742 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 743 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 744 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 745 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 746 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 747 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 748 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 749 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 750 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 751 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 752 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 753 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 754 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 755 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 756 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 757 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 758 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 759 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 760 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 761 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 762 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 763 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 764 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 765 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 766 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 767 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
768 CPU_K1OM_FLAGS, 0, 0 },
8a2c8fef 769 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 770 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 771 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 772 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 773 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 774 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 775 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 776 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 777 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 778 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 779 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 780 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 781 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 782 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 783 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 784 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 785 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 786 CPU_BDVER2_FLAGS, 0, 0 },
5e5c50d3
NE		 787 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
788 CPU_BDVER3_FLAGS, 0, 0 },
c7b0bd56
SE		 789 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
790 CPU_BDVER4_FLAGS, 0, 0 },
029f3522
GG		 791 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
792 CPU_ZNVER1_FLAGS, 0, 0 },
7b458c12
L		 793 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
794 CPU_BTVER1_FLAGS, 0, 0 },
795 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
796 CPU_BTVER2_FLAGS, 0, 0 },
8a2c8fef 797 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 798 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 799 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 800 CPU_287_FLAGS, 0, 0 },
8a2c8fef 801 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 802 CPU_387_FLAGS, 0, 0 },
8a2c8fef 803 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 804 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 805 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 806 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 807 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 808 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 809 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 810 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 811 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 812 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 813 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 814 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 815 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 816 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 817 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 818 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 819 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 820 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 821 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 822 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 823 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 824 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 825 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 826 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 827 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
828 CPU_AVX2_FLAGS, 0, 0 },
43234a1e
L		 829 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
830 CPU_AVX512F_FLAGS, 0, 0 },
831 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
832 CPU_AVX512CD_FLAGS, 0, 0 },
833 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
834 CPU_AVX512ER_FLAGS, 0, 0 },
835 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
836 CPU_AVX512PF_FLAGS, 0, 0 },
1dfc6506
L		 837 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
838 CPU_AVX512DQ_FLAGS, 0, 0 },
839 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
840 CPU_AVX512BW_FLAGS, 0, 0 },
841 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
842 CPU_AVX512VL_FLAGS, 0, 0 },
8a2c8fef 843 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 844 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 845 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 846 CPU_VMX_FLAGS, 0, 0 },
8729a6f6
L		 847 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
848 CPU_VMFUNC_FLAGS, 0, 0 },
8a2c8fef 849 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 850 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 851 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 852 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 853 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 854 CPU_XSAVEOPT_FLAGS, 0, 0 },
1dfc6506
L		 855 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
856 CPU_XSAVEC_FLAGS, 0, 0 },
857 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
858 CPU_XSAVES_FLAGS, 0, 0 },
8a2c8fef 859 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 860 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 861 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 862 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 863 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 864 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 865 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 866 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 867 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 868 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 869 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 870 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 871 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
872 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 873 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 874 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 875 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 876 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 877 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 878 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 879 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 880 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 881 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 882 CPU_MOVBE_FLAGS, 0, 0 },
60aa667e
L		 883 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
884 CPU_CX16_FLAGS, 0, 0 },
8a2c8fef 885 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 886 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 887 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
888 CPU_LZCNT_FLAGS, 0, 0 },
42164a71
L		 889 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
890 CPU_HLE_FLAGS, 0, 0 },
891 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
892 CPU_RTM_FLAGS, 0, 0 },
6c30d220
L		 893 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
894 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 895 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 896 CPU_CLFLUSH_FLAGS, 0, 0 },
897 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
898 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 899 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 900 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 901 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 902 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 903 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 904 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 905 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 906 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 907 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 908 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 909 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 910 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 911 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 912 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 913 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 914 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 915 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 916 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 917 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
918 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 919 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
920 CPU_TBM_FLAGS, 0, 0 },
e2e1fcde
L		 921 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
922 CPU_ADX_FLAGS, 0, 0 },
923 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
924 CPU_RDSEED_FLAGS, 0, 0 },
925 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
926 CPU_PRFCHW_FLAGS, 0, 0 },
5c111e37
L		 927 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
928 CPU_SMAP_FLAGS, 0, 0 },
7e8b059b
L		 929 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
930 CPU_MPX_FLAGS, 0, 0 },
a0046408
L		 931 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
932 CPU_SHA_FLAGS, 0, 0 },
963f3586
IT		 933 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
934 CPU_CLFLUSHOPT_FLAGS, 0, 0 },
dcf893b5
IT		 935 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
936 CPU_PREFETCHWT1_FLAGS, 0, 0 },
2cf200a4
IT		 937 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
938 CPU_SE1_FLAGS, 0, 0 },
c5e7287a
IT		 939 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
940 CPU_CLWB_FLAGS, 0, 0 },
9d8596f0
IT		 941 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN,
942 CPU_PCOMMIT_FLAGS, 0, 0 },
2cc1b5aa
IT		 943 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
944 CPU_AVX512IFMA_FLAGS, 0, 0 },
14f195c9
IT		 945 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
946 CPU_AVX512VBMI_FLAGS, 0, 0 },
029f3522
GG		 947 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
948 CPU_CLZERO_FLAGS, 0, 0 },
e413e4e9
AM		 949};
950
704209c0 951#ifdef I386COFF
a6c24e68
NC		 952/* Like s_lcomm_internal in gas/read.c but the alignment string
953 is allowed to be optional. */
954
955static symbolS *
956pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
957{
958 addressT align = 0;
959
960 SKIP_WHITESPACE ();
961
7ab9ffdd 962 if (needs_align
a6c24e68
NC		 963 && *input_line_pointer == ',')
964 {
965 align = parse_align (needs_align - 1);
7ab9ffdd 966
a6c24e68
NC		 967 if (align == (addressT) -1)
968 return NULL;
969 }
970 else
971 {
972 if (size >= 8)
973 align = 3;
974 else if (size >= 4)
975 align = 2;
976 else if (size >= 2)
977 align = 1;
978 else
979 align = 0;
980 }
981
982 bss_alloc (symbolP, size, align);
983 return symbolP;
984}
985
704209c0 986static void
a6c24e68
NC		 987pe_lcomm (int needs_align)
988{
989 s_comm_internal (needs_align * 2, pe_lcomm_internal);
990}
704209c0 991#endif
a6c24e68 992
29b0f896
AM		 993const pseudo_typeS md_pseudo_table[] =
994{
995#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
996 {"align", s_align_bytes, 0},
997#else
998 {"align", s_align_ptwo, 0},
999#endif
1000 {"arch", set_cpu_arch, 0},
1001#ifndef I386COFF
1002 {"bss", s_bss, 0},
a6c24e68
NC		 1003#else
1004 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1005#endif
1006 {"ffloat", float_cons, 'f'},
1007 {"dfloat", float_cons, 'd'},
1008 {"tfloat", float_cons, 'x'},
1009 {"value", cons, 2},
d182319b 1010 {"slong", signed_cons, 4},
29b0f896
AM		 1011 {"noopt", s_ignore, 0},
1012 {"optim", s_ignore, 0},
1013 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1014 {"code16", set_code_flag, CODE_16BIT},
1015 {"code32", set_code_flag, CODE_32BIT},
1016 {"code64", set_code_flag, CODE_64BIT},
1017 {"intel_syntax", set_intel_syntax, 1},
1018 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1019 {"intel_mnemonic", set_intel_mnemonic, 1},
1020 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1021 {"allow_index_reg", set_allow_index_reg, 1},
1022 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1023 {"sse_check", set_check, 0},
1024 {"operand_check", set_check, 1},
3b22753a
L		 1025#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1026 {"largecomm", handle_large_common, 0},
07a53e5c 1027#else
e3bb37b5 1028 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1029 {"loc", dwarf2_directive_loc, 0},
1030 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1031#endif
6482c264
NC		 1032#ifdef TE_PE
1033 {"secrel32", pe_directive_secrel, 0},
1034#endif
29b0f896
AM		 1035 {0, 0, 0}
1036};
1037
1038/* For interface with expression (). */
1039extern char *input_line_pointer;
1040
1041/* Hash table for instruction mnemonic lookup. */
1042static struct hash_control *op_hash;
1043
1044/* Hash table for register lookup. */
1045static struct hash_control *reg_hash;
1046\f
252b5132 1047void
e3bb37b5 1048i386_align_code (fragS *fragP, int count)
252b5132 1049{
ce8a8b2f
AM		 1050 /* Various efficient no-op patterns for aligning code labels.
1051 Note: Don't try to assemble the instructions in the comments.
1052 0L and 0w are not legal. */
252b5132
RH		 1053 static const char f32_1[] =
1054 {0x90}; /* nop */
1055 static const char f32_2[] =
ccc9c027 1056 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 1057 static const char f32_3[] =
1058 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1059 static const char f32_4[] =
1060 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1061 static const char f32_5[] =
1062 {0x90, /* nop */
1063 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1064 static const char f32_6[] =
1065 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1066 static const char f32_7[] =
1067 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1068 static const char f32_8[] =
1069 {0x90, /* nop */
1070 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1071 static const char f32_9[] =
1072 {0x89,0xf6, /* movl %esi,%esi */
1073 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1074 static const char f32_10[] =
1075 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1076 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1077 static const char f32_11[] =
1078 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1079 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1080 static const char f32_12[] =
1081 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1082 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1083 static const char f32_13[] =
1084 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1085 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1086 static const char f32_14[] =
1087 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1088 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 1089 static const char f16_3[] =
1090 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 1091 static const char f16_4[] =
1092 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1093 static const char f16_5[] =
1094 {0x90, /* nop */
1095 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1096 static const char f16_6[] =
1097 {0x89,0xf6, /* mov %si,%si */
1098 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1099 static const char f16_7[] =
1100 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1101 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1102 static const char f16_8[] =
1103 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1104 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 1105 static const char jump_31[] =
1106 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1107 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1108 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1109 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 1110 static const char *const f32_patt[] = {
1111 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1112 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 1113 };
1114 static const char *const f16_patt[] = {
76bc74dc 1115 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1116 };
ccc9c027
L		 1117 /* nopl (%[re]ax) */
1118 static const char alt_3[] =
1119 {0x0f,0x1f,0x00};
1120 /* nopl 0(%[re]ax) */
1121 static const char alt_4[] =
1122 {0x0f,0x1f,0x40,0x00};
1123 /* nopl 0(%[re]ax,%[re]ax,1) */
1124 static const char alt_5[] =
1125 {0x0f,0x1f,0x44,0x00,0x00};
1126 /* nopw 0(%[re]ax,%[re]ax,1) */
1127 static const char alt_6[] =
1128 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1129 /* nopl 0L(%[re]ax) */
1130 static const char alt_7[] =
1131 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1132 /* nopl 0L(%[re]ax,%[re]ax,1) */
1133 static const char alt_8[] =
1134 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1135 /* nopw 0L(%[re]ax,%[re]ax,1) */
1136 static const char alt_9[] =
1137 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1138 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1139 static const char alt_10[] =
1140 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
80b8656c 1141 static const char *const alt_patt[] = {
ccc9c027 1142 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
80b8656c 1143 alt_9, alt_10
ccc9c027 1144 };
252b5132 1145
76bc74dc
L		 1146 /* Only align for at least a positive non-zero boundary. */
1147 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1148 return;
3e73aa7c 1149
ccc9c027
L		 1150 /* We need to decide which NOP sequence to use for 32bit and
1151 64bit. When -mtune= is used:
4eed87de 1152
76bc74dc
L		 1153 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1154 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1155 2. For the rest, alt_patt will be used.
1156
1157 When -mtune= isn't used, alt_patt will be used if
22109423 1158 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1159 be used.
ccc9c027
L		 1160
1161 When -march= or .arch is used, we can't use anything beyond
1162 cpu_arch_isa_flags. */
1163
1164 if (flag_code == CODE_16BIT)
1165 {
ccc9c027 1166 if (count > 8)
33fef721 1167 {
76bc74dc
L		 1168 memcpy (fragP->fr_literal + fragP->fr_fix,
1169 jump_31, count);
1170 /* Adjust jump offset. */
1171 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1172 }
76bc74dc
L		 1173 else
1174 memcpy (fragP->fr_literal + fragP->fr_fix,
1175 f16_patt[count - 1], count);
252b5132 1176 }
33fef721 1177 else
ccc9c027
L		 1178 {
1179 const char *const *patt = NULL;
1180
fbf3f584 1181 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1182 {
1183 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1184 switch (cpu_arch_tune)
1185 {
1186 case PROCESSOR_UNKNOWN:
1187 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1188 optimize with nops. */
1189 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1190 patt = alt_patt;
ccc9c027
L		 1191 else
1192 patt = f32_patt;
1193 break;
ccc9c027
L		 1194 case PROCESSOR_PENTIUM4:
1195 case PROCESSOR_NOCONA:
ef05d495 1196 case PROCESSOR_CORE:
76bc74dc 1197 case PROCESSOR_CORE2:
bd5295b2 1198 case PROCESSOR_COREI7:
3632d14b 1199 case PROCESSOR_L1OM:
7a9068fe 1200 case PROCESSOR_K1OM:
76bc74dc 1201 case PROCESSOR_GENERIC64:
ccc9c027
L		 1202 case PROCESSOR_K6:
1203 case PROCESSOR_ATHLON:
1204 case PROCESSOR_K8:
4eed87de 1205 case PROCESSOR_AMDFAM10:
8aedb9fe 1206 case PROCESSOR_BD:
029f3522 1207 case PROCESSOR_ZNVER:
7b458c12 1208 case PROCESSOR_BT:
80b8656c 1209 patt = alt_patt;
ccc9c027 1210 break;
76bc74dc 1211 case PROCESSOR_I386:
ccc9c027
L		 1212 case PROCESSOR_I486:
1213 case PROCESSOR_PENTIUM:
2dde1948 1214 case PROCESSOR_PENTIUMPRO:
ccc9c027
L		 1215 case PROCESSOR_GENERIC32:
1216 patt = f32_patt;
1217 break;
4eed87de 1218 }
ccc9c027
L		 1219 }
1220 else
1221 {
fbf3f584 1222 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1223 {
1224 case PROCESSOR_UNKNOWN:
e6a14101 1225 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1226 PROCESSOR_UNKNOWN. */
1227 abort ();
1228 break;
1229
76bc74dc 1230 case PROCESSOR_I386:
ccc9c027
L		 1231 case PROCESSOR_I486:
1232 case PROCESSOR_PENTIUM:
ccc9c027
L		 1233 case PROCESSOR_K6:
1234 case PROCESSOR_ATHLON:
1235 case PROCESSOR_K8:
4eed87de 1236 case PROCESSOR_AMDFAM10:
8aedb9fe 1237 case PROCESSOR_BD:
029f3522 1238 case PROCESSOR_ZNVER:
7b458c12 1239 case PROCESSOR_BT:
ccc9c027
L		 1240 case PROCESSOR_GENERIC32:
1241 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1242 with nops. */
1243 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1244 patt = alt_patt;
ccc9c027
L		 1245 else
1246 patt = f32_patt;
1247 break;
76bc74dc
L		 1248 case PROCESSOR_PENTIUMPRO:
1249 case PROCESSOR_PENTIUM4:
1250 case PROCESSOR_NOCONA:
1251 case PROCESSOR_CORE:
ef05d495 1252 case PROCESSOR_CORE2:
bd5295b2 1253 case PROCESSOR_COREI7:
3632d14b 1254 case PROCESSOR_L1OM:
7a9068fe 1255 case PROCESSOR_K1OM:
22109423 1256 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1257 patt = alt_patt;
ccc9c027
L		 1258 else
1259 patt = f32_patt;
1260 break;
1261 case PROCESSOR_GENERIC64:
80b8656c 1262 patt = alt_patt;
ccc9c027 1263 break;
4eed87de 1264 }
ccc9c027
L		 1265 }
1266
76bc74dc
L		 1267 if (patt == f32_patt)
1268 {
1269 /* If the padding is less than 15 bytes, we use the normal
1270 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1271 its offset. */
1272 int limit;
76ba9986 1273
711eedef
L		 1274 /* For 64bit, the limit is 3 bytes. */
1275 if (flag_code == CODE_64BIT
1276 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1277 limit = 3;
1278 else
1279 limit = 15;
1280 if (count < limit)
76bc74dc
L		 1281 memcpy (fragP->fr_literal + fragP->fr_fix,
1282 patt[count - 1], count);
1283 else
1284 {
1285 memcpy (fragP->fr_literal + fragP->fr_fix,
1286 jump_31, count);
1287 /* Adjust jump offset. */
1288 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1289 }
1290 }
1291 else
1292 {
80b8656c
L		 1293 /* Maximum length of an instruction is 10 byte. If the
1294 padding is greater than 10 bytes and we don't use jump,
76bc74dc
L		 1295 we have to break it into smaller pieces. */
1296 int padding = count;
80b8656c 1297 while (padding > 10)
76bc74dc 1298 {
80b8656c 1299 padding -= 10;
76bc74dc 1300 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
80b8656c 1301 patt [9], 10);
76bc74dc
L		 1302 }
1303
1304 if (padding)
1305 memcpy (fragP->fr_literal + fragP->fr_fix,
1306 patt [padding - 1], padding);
1307 }
ccc9c027 1308 }
33fef721 1309 fragP->fr_var = count;
252b5132
RH		 1310}
1311
c6fb90c8 1312static INLINE int
0dfbf9d7 1313operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1314{
0dfbf9d7 1315 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1316 {
1317 case 3:
0dfbf9d7 1318 if (x->array[2])
c6fb90c8
L		 1319 return 0;
1320 case 2:
0dfbf9d7 1321 if (x->array[1])
c6fb90c8
L		 1322 return 0;
1323 case 1:
0dfbf9d7 1324 return !x->array[0];
c6fb90c8
L		 1325 default:
1326 abort ();
1327 }
40fb9820
L		 1328}
1329
c6fb90c8 1330static INLINE void
0dfbf9d7 1331operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1332{
0dfbf9d7 1333 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1334 {
1335 case 3:
0dfbf9d7 1336 x->array[2] = v;
c6fb90c8 1337 case 2:
0dfbf9d7 1338 x->array[1] = v;
c6fb90c8 1339 case 1:
0dfbf9d7 1340 x->array[0] = v;
c6fb90c8
L		 1341 break;
1342 default:
1343 abort ();
1344 }
1345}
40fb9820 1346
c6fb90c8 1347static INLINE int
0dfbf9d7
L		 1348operand_type_equal (const union i386_operand_type *x,
1349 const union i386_operand_type *y)
c6fb90c8 1350{
0dfbf9d7 1351 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1352 {
1353 case 3:
0dfbf9d7 1354 if (x->array[2] != y->array[2])
c6fb90c8
L		 1355 return 0;
1356 case 2:
0dfbf9d7 1357 if (x->array[1] != y->array[1])
c6fb90c8
L		 1358 return 0;
1359 case 1:
0dfbf9d7 1360 return x->array[0] == y->array[0];
c6fb90c8
L		 1361 break;
1362 default:
1363 abort ();
1364 }
1365}
40fb9820 1366
0dfbf9d7
L		 1367static INLINE int
1368cpu_flags_all_zero (const union i386_cpu_flags *x)
1369{
1370 switch (ARRAY_SIZE(x->array))
1371 {
1372 case 3:
1373 if (x->array[2])
1374 return 0;
1375 case 2:
1376 if (x->array[1])
1377 return 0;
1378 case 1:
1379 return !x->array[0];
1380 default:
1381 abort ();
1382 }
1383}
1384
0dfbf9d7
L		 1385static INLINE int
1386cpu_flags_equal (const union i386_cpu_flags *x,
1387 const union i386_cpu_flags *y)
1388{
1389 switch (ARRAY_SIZE(x->array))
1390 {
1391 case 3:
1392 if (x->array[2] != y->array[2])
1393 return 0;
1394 case 2:
1395 if (x->array[1] != y->array[1])
1396 return 0;
1397 case 1:
1398 return x->array[0] == y->array[0];
1399 break;
1400 default:
1401 abort ();
1402 }
1403}
c6fb90c8
L		 1404
1405static INLINE int
1406cpu_flags_check_cpu64 (i386_cpu_flags f)
1407{
1408 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1409 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1410}
1411
c6fb90c8
L		 1412static INLINE i386_cpu_flags
1413cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1414{
c6fb90c8
L		 1415 switch (ARRAY_SIZE (x.array))
1416 {
1417 case 3:
1418 x.array [2] &= y.array [2];
1419 case 2:
1420 x.array [1] &= y.array [1];
1421 case 1:
1422 x.array [0] &= y.array [0];
1423 break;
1424 default:
1425 abort ();
1426 }
1427 return x;
1428}
40fb9820 1429
c6fb90c8
L		 1430static INLINE i386_cpu_flags
1431cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1432{
c6fb90c8 1433 switch (ARRAY_SIZE (x.array))
40fb9820 1434 {
c6fb90c8
L		 1435 case 3:
1436 x.array [2] |= y.array [2];
1437 case 2:
1438 x.array [1] |= y.array [1];
1439 case 1:
1440 x.array [0] |= y.array [0];
40fb9820
L		 1441 break;
1442 default:
1443 abort ();
1444 }
40fb9820
L		 1445 return x;
1446}
1447
309d3373
JB		 1448static INLINE i386_cpu_flags
1449cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1450{
1451 switch (ARRAY_SIZE (x.array))
1452 {
1453 case 3:
1454 x.array [2] &= ~y.array [2];
1455 case 2:
1456 x.array [1] &= ~y.array [1];
1457 case 1:
1458 x.array [0] &= ~y.array [0];
1459 break;
1460 default:
1461 abort ();
1462 }
1463 return x;
1464}
1465
c0f3af97
L		 1466#define CPU_FLAGS_ARCH_MATCH 0x1
1467#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1468#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1469#define CPU_FLAGS_PCLMUL_MATCH 0x8
1470#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1471
a5ff0eb2 1472#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1473 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1474 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1475#define CPU_FLAGS_PERFECT_MATCH \
1476 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1477
1478/* Return CPU flags match bits. */
3629bb00 1479
40fb9820 1480static int
d3ce72d0 1481cpu_flags_match (const insn_template *t)
40fb9820 1482{
c0f3af97
L		 1483 i386_cpu_flags x = t->cpu_flags;
1484 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1485
1486 x.bitfield.cpu64 = 0;
1487 x.bitfield.cpuno64 = 0;
1488
0dfbf9d7 1489 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1490 {
1491 /* This instruction is available on all archs. */
1492 match |= CPU_FLAGS_32BIT_MATCH;
1493 }
3629bb00
L		 1494 else
1495 {
c0f3af97 1496 /* This instruction is available only on some archs. */
3629bb00
L		 1497 i386_cpu_flags cpu = cpu_arch_flags;
1498
1499 cpu.bitfield.cpu64 = 0;
1500 cpu.bitfield.cpuno64 = 0;
1501 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1502 if (!cpu_flags_all_zero (&cpu))
1503 {
a5ff0eb2
L		 1504 if (x.bitfield.cpuavx)
1505 {
ce2f5b3c 1506 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1507 if (cpu.bitfield.cpuavx)
1508 {
1509 /* Check SSE2AVX. */
1510 if (!t->opcode_modifier.sse2avx|| sse2avx)
1511 {
1512 match |= (CPU_FLAGS_ARCH_MATCH
1513 | CPU_FLAGS_AVX_MATCH);
1514 /* Check AES. */
1515 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1516 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1517 /* Check PCLMUL. */
1518 if (!x.bitfield.cpupclmul
1519 || cpu.bitfield.cpupclmul)
1520 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1521 }
1522 }
1523 else
1524 match |= CPU_FLAGS_ARCH_MATCH;
1525 }
1526 else
c0f3af97
L		 1527 match |= CPU_FLAGS_32BIT_MATCH;
1528 }
3629bb00 1529 }
c0f3af97 1530 return match;
40fb9820
L		 1531}
1532
c6fb90c8
L		 1533static INLINE i386_operand_type
1534operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1535{
c6fb90c8
L		 1536 switch (ARRAY_SIZE (x.array))
1537 {
1538 case 3:
1539 x.array [2] &= y.array [2];
1540 case 2:
1541 x.array [1] &= y.array [1];
1542 case 1:
1543 x.array [0] &= y.array [0];
1544 break;
1545 default:
1546 abort ();
1547 }
1548 return x;
40fb9820
L		 1549}
1550
c6fb90c8
L		 1551static INLINE i386_operand_type
1552operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1553{
c6fb90c8 1554 switch (ARRAY_SIZE (x.array))
40fb9820 1555 {
c6fb90c8
L		 1556 case 3:
1557 x.array [2] |= y.array [2];
1558 case 2:
1559 x.array [1] |= y.array [1];
1560 case 1:
1561 x.array [0] |= y.array [0];
40fb9820
L		 1562 break;
1563 default:
1564 abort ();
1565 }
c6fb90c8
L		 1566 return x;
1567}
40fb9820 1568
c6fb90c8
L		 1569static INLINE i386_operand_type
1570operand_type_xor (i386_operand_type x, i386_operand_type y)
1571{
1572 switch (ARRAY_SIZE (x.array))
1573 {
1574 case 3:
1575 x.array [2] ^= y.array [2];
1576 case 2:
1577 x.array [1] ^= y.array [1];
1578 case 1:
1579 x.array [0] ^= y.array [0];
1580 break;
1581 default:
1582 abort ();
1583 }
40fb9820
L		 1584 return x;
1585}
1586
1587static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1588static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1589static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1590static const i386_operand_type inoutportreg
1591 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1592static const i386_operand_type reg16_inoutportreg
1593 = OPERAND_TYPE_REG16_INOUTPORTREG;
1594static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1595static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1596static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1597static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1598static const i386_operand_type anydisp
1599 = OPERAND_TYPE_ANYDISP;
40fb9820 1600static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1601static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1602static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1603static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1604static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1605static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1606static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1607static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1608static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1609static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1610static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1611static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1612static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1613static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1614
1615enum operand_type
1616{
1617 reg,
40fb9820
L		 1618 imm,
1619 disp,
1620 anymem
1621};
1622
c6fb90c8 1623static INLINE int
40fb9820
L		 1624operand_type_check (i386_operand_type t, enum operand_type c)
1625{
1626 switch (c)
1627 {
1628 case reg:
1629 return (t.bitfield.reg8
1630 || t.bitfield.reg16
1631 || t.bitfield.reg32
1632 || t.bitfield.reg64);
1633
40fb9820
L		 1634 case imm:
1635 return (t.bitfield.imm8
1636 || t.bitfield.imm8s
1637 || t.bitfield.imm16
1638 || t.bitfield.imm32
1639 || t.bitfield.imm32s
1640 || t.bitfield.imm64);
1641
1642 case disp:
1643 return (t.bitfield.disp8
1644 || t.bitfield.disp16
1645 || t.bitfield.disp32
1646 || t.bitfield.disp32s
1647 || t.bitfield.disp64);
1648
1649 case anymem:
1650 return (t.bitfield.disp8
1651 || t.bitfield.disp16
1652 || t.bitfield.disp32
1653 || t.bitfield.disp32s
1654 || t.bitfield.disp64
1655 || t.bitfield.baseindex);
1656
1657 default:
1658 abort ();
1659 }
2cfe26b6
AM		 1660
1661 return 0;
40fb9820
L		 1662}
1663
5c07affc
L		 1664/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1665 operand J for instruction template T. */
1666
1667static INLINE int
d3ce72d0 1668match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1669{
1670 return !((i.types[j].bitfield.byte
1671 && !t->operand_types[j].bitfield.byte)
1672 || (i.types[j].bitfield.word
1673 && !t->operand_types[j].bitfield.word)
1674 || (i.types[j].bitfield.dword
1675 && !t->operand_types[j].bitfield.dword)
1676 || (i.types[j].bitfield.qword
1677 && !t->operand_types[j].bitfield.qword));
1678}
1679
1680/* Return 1 if there is no conflict in any size on operand J for
1681 instruction template T. */
1682
1683static INLINE int
d3ce72d0 1684match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1685{
1686 return (match_reg_size (t, j)
1687 && !((i.types[j].bitfield.unspecified
1688 && !t->operand_types[j].bitfield.unspecified)
1689 || (i.types[j].bitfield.fword
1690 && !t->operand_types[j].bitfield.fword)
1691 || (i.types[j].bitfield.tbyte
1692 && !t->operand_types[j].bitfield.tbyte)
1693 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1694 && !t->operand_types[j].bitfield.xmmword)
1695 || (i.types[j].bitfield.ymmword
43234a1e
L		 1696 && !t->operand_types[j].bitfield.ymmword)
1697 || (i.types[j].bitfield.zmmword
1698 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1699}
1700
1701/* Return 1 if there is no size conflict on any operands for
1702 instruction template T. */
1703
1704static INLINE int
d3ce72d0 1705operand_size_match (const insn_template *t)
5c07affc
L		 1706{
1707 unsigned int j;
1708 int match = 1;
1709
1710 /* Don't check jump instructions. */
1711 if (t->opcode_modifier.jump
1712 || t->opcode_modifier.jumpbyte
1713 || t->opcode_modifier.jumpdword
1714 || t->opcode_modifier.jumpintersegment)
1715 return match;
1716
1717 /* Check memory and accumulator operand size. */
1718 for (j = 0; j < i.operands; j++)
1719 {
1720 if (t->operand_types[j].bitfield.anysize)
1721 continue;
1722
1723 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1724 {
1725 match = 0;
1726 break;
1727 }
1728
1729 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1730 {
1731 match = 0;
1732 break;
1733 }
1734 }
1735
891edac4 1736 if (match)
5c07affc 1737 return match;
891edac4
L		 1738 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1739 {
1740mismatch:
86e026a4 1741 i.error = operand_size_mismatch;
891edac4
L		 1742 return 0;
1743 }
5c07affc
L		 1744
1745 /* Check reverse. */
9c2799c2 1746 gas_assert (i.operands == 2);
5c07affc
L		 1747
1748 match = 1;
1749 for (j = 0; j < 2; j++)
1750 {
1751 if (t->operand_types[j].bitfield.acc
1752 && !match_reg_size (t, j ? 0 : 1))
891edac4 1753 goto mismatch;
5c07affc
L		 1754
1755 if (i.types[j].bitfield.mem
1756 && !match_mem_size (t, j ? 0 : 1))
891edac4 1757 goto mismatch;
5c07affc
L		 1758 }
1759
1760 return match;
1761}
1762
c6fb90c8 1763static INLINE int
40fb9820
L		 1764operand_type_match (i386_operand_type overlap,
1765 i386_operand_type given)
1766{
1767 i386_operand_type temp = overlap;
1768
1769 temp.bitfield.jumpabsolute = 0;
7d5e4556 1770 temp.bitfield.unspecified = 0;
5c07affc
L		 1771 temp.bitfield.byte = 0;
1772 temp.bitfield.word = 0;
1773 temp.bitfield.dword = 0;
1774 temp.bitfield.fword = 0;
1775 temp.bitfield.qword = 0;
1776 temp.bitfield.tbyte = 0;
1777 temp.bitfield.xmmword = 0;
c0f3af97 1778 temp.bitfield.ymmword = 0;
43234a1e 1779 temp.bitfield.zmmword = 0;
0dfbf9d7 1780 if (operand_type_all_zero (&temp))
891edac4 1781 goto mismatch;
40fb9820 1782
891edac4
L		 1783 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1784 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1785 return 1;
1786
1787mismatch:
a65babc9 1788 i.error = operand_type_mismatch;
891edac4 1789 return 0;
40fb9820
L		 1790}
1791
7d5e4556 1792/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1793 unless the expected operand type register overlap is null.
1794 Note that Acc in a template matches every size of reg. */
1795
c6fb90c8 1796static INLINE int
40fb9820
L		 1797operand_type_register_match (i386_operand_type m0,
1798 i386_operand_type g0,
1799 i386_operand_type t0,
1800 i386_operand_type m1,
1801 i386_operand_type g1,
1802 i386_operand_type t1)
1803{
1804 if (!operand_type_check (g0, reg))
1805 return 1;
1806
1807 if (!operand_type_check (g1, reg))
1808 return 1;
1809
1810 if (g0.bitfield.reg8 == g1.bitfield.reg8
1811 && g0.bitfield.reg16 == g1.bitfield.reg16
1812 && g0.bitfield.reg32 == g1.bitfield.reg32
1813 && g0.bitfield.reg64 == g1.bitfield.reg64)
1814 return 1;
1815
1816 if (m0.bitfield.acc)
1817 {
1818 t0.bitfield.reg8 = 1;
1819 t0.bitfield.reg16 = 1;
1820 t0.bitfield.reg32 = 1;
1821 t0.bitfield.reg64 = 1;
1822 }
1823
1824 if (m1.bitfield.acc)
1825 {
1826 t1.bitfield.reg8 = 1;
1827 t1.bitfield.reg16 = 1;
1828 t1.bitfield.reg32 = 1;
1829 t1.bitfield.reg64 = 1;
1830 }
1831
891edac4
L		 1832 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1833 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1834 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1835 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1836 return 1;
1837
a65babc9 1838 i.error = register_type_mismatch;
891edac4
L		 1839
1840 return 0;
40fb9820
L		 1841}
1842
4c692bc7
JB		 1843static INLINE unsigned int
1844register_number (const reg_entry *r)
1845{
1846 unsigned int nr = r->reg_num;
1847
1848 if (r->reg_flags & RegRex)
1849 nr += 8;
1850
1851 return nr;
1852}
1853
252b5132 1854static INLINE unsigned int
40fb9820 1855mode_from_disp_size (i386_operand_type t)
252b5132 1856{
43234a1e 1857 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1858 return 1;
1859 else if (t.bitfield.disp16
1860 || t.bitfield.disp32
1861 || t.bitfield.disp32s)
1862 return 2;
1863 else
1864 return 0;
252b5132
RH		 1865}
1866
1867static INLINE int
65879393 1868fits_in_signed_byte (addressT num)
252b5132 1869{
65879393 1870 return num + 0x80 <= 0xff;
47926f60 1871}
252b5132
RH		 1872
1873static INLINE int
65879393 1874fits_in_unsigned_byte (addressT num)
252b5132 1875{
65879393 1876 return num <= 0xff;
47926f60 1877}
252b5132
RH		 1878
1879static INLINE int
65879393 1880fits_in_unsigned_word (addressT num)
252b5132 1881{
65879393 1882 return num <= 0xffff;
47926f60 1883}
252b5132
RH		 1884
1885static INLINE int
65879393 1886fits_in_signed_word (addressT num)
252b5132 1887{
65879393 1888 return num + 0x8000 <= 0xffff;
47926f60 1889}
2a962e6d 1890
3e73aa7c 1891static INLINE int
65879393 1892fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1893{
1894#ifndef BFD64
1895 return 1;
1896#else
65879393 1897 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 1898#endif
1899} /* fits_in_signed_long() */
2a962e6d 1900
3e73aa7c 1901static INLINE int
65879393 1902fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1903{
1904#ifndef BFD64
1905 return 1;
1906#else
65879393 1907 return num <= 0xffffffff;
3e73aa7c
JH		 1908#endif
1909} /* fits_in_unsigned_long() */
252b5132 1910
43234a1e
L		 1911static INLINE int
1912fits_in_vec_disp8 (offsetT num)
1913{
1914 int shift = i.memshift;
1915 unsigned int mask;
1916
1917 if (shift == -1)
1918 abort ();
1919
1920 mask = (1 << shift) - 1;
1921
1922 /* Return 0 if NUM isn't properly aligned. */
1923 if ((num & mask))
1924 return 0;
1925
1926 /* Check if NUM will fit in 8bit after shift. */
1927 return fits_in_signed_byte (num >> shift);
1928}
1929
a683cc34
SP		 1930static INLINE int
1931fits_in_imm4 (offsetT num)
1932{
1933 return (num & 0xf) == num;
1934}
1935
40fb9820 1936static i386_operand_type
e3bb37b5 1937smallest_imm_type (offsetT num)
252b5132 1938{
40fb9820 1939 i386_operand_type t;
7ab9ffdd 1940
0dfbf9d7 1941 operand_type_set (&t, 0);
40fb9820
L		 1942 t.bitfield.imm64 = 1;
1943
1944 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1945 {
1946 /* This code is disabled on the 486 because all the Imm1 forms
1947 in the opcode table are slower on the i486. They're the
1948 versions with the implicitly specified single-position
1949 displacement, which has another syntax if you really want to
1950 use that form. */
40fb9820
L		 1951 t.bitfield.imm1 = 1;
1952 t.bitfield.imm8 = 1;
1953 t.bitfield.imm8s = 1;
1954 t.bitfield.imm16 = 1;
1955 t.bitfield.imm32 = 1;
1956 t.bitfield.imm32s = 1;
1957 }
1958 else if (fits_in_signed_byte (num))
1959 {
1960 t.bitfield.imm8 = 1;
1961 t.bitfield.imm8s = 1;
1962 t.bitfield.imm16 = 1;
1963 t.bitfield.imm32 = 1;
1964 t.bitfield.imm32s = 1;
1965 }
1966 else if (fits_in_unsigned_byte (num))
1967 {
1968 t.bitfield.imm8 = 1;
1969 t.bitfield.imm16 = 1;
1970 t.bitfield.imm32 = 1;
1971 t.bitfield.imm32s = 1;
1972 }
1973 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1974 {
1975 t.bitfield.imm16 = 1;
1976 t.bitfield.imm32 = 1;
1977 t.bitfield.imm32s = 1;
1978 }
1979 else if (fits_in_signed_long (num))
1980 {
1981 t.bitfield.imm32 = 1;
1982 t.bitfield.imm32s = 1;
1983 }
1984 else if (fits_in_unsigned_long (num))
1985 t.bitfield.imm32 = 1;
1986
1987 return t;
47926f60 1988}
252b5132 1989
847f7ad4 1990static offsetT
e3bb37b5 1991offset_in_range (offsetT val, int size)
847f7ad4 1992{
508866be 1993 addressT mask;
ba2adb93 1994
847f7ad4
AM		 1995 switch (size)
1996 {
508866be
L		 1997 case 1: mask = ((addressT) 1 << 8) - 1; break;
1998 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1999 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2000#ifdef BFD64
2001 case 8: mask = ((addressT) 2 << 63) - 1; break;
2002#endif
47926f60 2003 default: abort ();
847f7ad4
AM		 2004 }
2005
9de868bf
L		 2006#ifdef BFD64
2007 /* If BFD64, sign extend val for 32bit address mode. */
2008 if (flag_code != CODE_64BIT
2009 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2010 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2011 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2012#endif
ba2adb93 2013
47926f60 2014 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2015 {
2016 char buf1[40], buf2[40];
2017
2018 sprint_value (buf1, val);
2019 sprint_value (buf2, val & mask);
2020 as_warn (_("%s shortened to %s"), buf1, buf2);
2021 }
2022 return val & mask;
2023}
2024
c32fa91d
L		 2025enum PREFIX_GROUP
2026{
2027 PREFIX_EXIST = 0,
2028 PREFIX_LOCK,
2029 PREFIX_REP,
2030 PREFIX_OTHER
2031};
2032
2033/* Returns
2034 a. PREFIX_EXIST if attempting to add a prefix where one from the
2035 same class already exists.
2036 b. PREFIX_LOCK if lock prefix is added.
2037 c. PREFIX_REP if rep/repne prefix is added.
2038 d. PREFIX_OTHER if other prefix is added.
2039 */
2040
2041static enum PREFIX_GROUP
e3bb37b5 2042add_prefix (unsigned int prefix)
252b5132 2043{
c32fa91d 2044 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2045 unsigned int q;
252b5132 2046
29b0f896
AM		 2047 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2048 && flag_code == CODE_64BIT)
b1905489 2049 {
161a04f6
L		 2050 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2051 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2052 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2053 ret = PREFIX_EXIST;
b1905489
JB		 2054 q = REX_PREFIX;
2055 }
3e73aa7c 2056 else
b1905489
JB		 2057 {
2058 switch (prefix)
2059 {
2060 default:
2061 abort ();
2062
2063 case CS_PREFIX_OPCODE:
2064 case DS_PREFIX_OPCODE:
2065 case ES_PREFIX_OPCODE:
2066 case FS_PREFIX_OPCODE:
2067 case GS_PREFIX_OPCODE:
2068 case SS_PREFIX_OPCODE:
2069 q = SEG_PREFIX;
2070 break;
2071
2072 case REPNE_PREFIX_OPCODE:
2073 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2074 q = REP_PREFIX;
2075 ret = PREFIX_REP;
2076 break;
2077
b1905489 2078 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2079 q = LOCK_PREFIX;
2080 ret = PREFIX_LOCK;
b1905489
JB		 2081 break;
2082
2083 case FWAIT_OPCODE:
2084 q = WAIT_PREFIX;
2085 break;
2086
2087 case ADDR_PREFIX_OPCODE:
2088 q = ADDR_PREFIX;
2089 break;
2090
2091 case DATA_PREFIX_OPCODE:
2092 q = DATA_PREFIX;
2093 break;
2094 }
2095 if (i.prefix[q] != 0)
c32fa91d 2096 ret = PREFIX_EXIST;
b1905489 2097 }
252b5132 2098
b1905489 2099 if (ret)
252b5132 2100 {
b1905489
JB		 2101 if (!i.prefix[q])
2102 ++i.prefixes;
2103 i.prefix[q] |= prefix;
252b5132 2104 }
b1905489
JB		 2105 else
2106 as_bad (_("same type of prefix used twice"));
252b5132 2107
252b5132
RH		 2108 return ret;
2109}
2110
2111static void
78f12dd3 2112update_code_flag (int value, int check)
eecb386c 2113{
78f12dd3
L		 2114 PRINTF_LIKE ((*as_error));
2115
1e9cc1c2 2116 flag_code = (enum flag_code) value;
40fb9820
L		 2117 if (flag_code == CODE_64BIT)
2118 {
2119 cpu_arch_flags.bitfield.cpu64 = 1;
2120 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2121 }
2122 else
2123 {
2124 cpu_arch_flags.bitfield.cpu64 = 0;
2125 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2126 }
2127 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2128 {
78f12dd3
L		 2129 if (check)
2130 as_error = as_fatal;
2131 else
2132 as_error = as_bad;
2133 (*as_error) (_("64bit mode not supported on `%s'."),
2134 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2135 }
40fb9820 2136 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2137 {
78f12dd3
L		 2138 if (check)
2139 as_error = as_fatal;
2140 else
2141 as_error = as_bad;
2142 (*as_error) (_("32bit mode not supported on `%s'."),
2143 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2144 }
eecb386c
AM		 2145 stackop_size = '\0';
2146}
2147
78f12dd3
L		 2148static void
2149set_code_flag (int value)
2150{
2151 update_code_flag (value, 0);
2152}
2153
eecb386c 2154static void
e3bb37b5 2155set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2156{
1e9cc1c2 2157 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2158 if (flag_code != CODE_16BIT)
2159 abort ();
2160 cpu_arch_flags.bitfield.cpu64 = 0;
2161 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2162 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2163}
2164
2165static void
e3bb37b5 2166set_intel_syntax (int syntax_flag)
252b5132
RH		 2167{
2168 /* Find out if register prefixing is specified. */
2169 int ask_naked_reg = 0;
2170
2171 SKIP_WHITESPACE ();
29b0f896 2172 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2173 {
2174 char *string = input_line_pointer;
2175 int e = get_symbol_end ();
2176
47926f60 2177 if (strcmp (string, "prefix") == 0)
252b5132 2178 ask_naked_reg = 1;
47926f60 2179 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2180 ask_naked_reg = -1;
2181 else
d0b47220 2182 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2183 *input_line_pointer = e;
2184 }
2185 demand_empty_rest_of_line ();
c3332e24 2186
252b5132
RH		 2187 intel_syntax = syntax_flag;
2188
2189 if (ask_naked_reg == 0)
f86103b7
AM		 2190 allow_naked_reg = (intel_syntax
2191 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2192 else
2193 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2194
ee86248c 2195 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2196
e4a3b5a4 2197 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2198 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2199 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2200}
2201
1efbbeb4
L		 2202static void
2203set_intel_mnemonic (int mnemonic_flag)
2204{
e1d4d893 2205 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2206}
2207
db51cc60
L		 2208static void
2209set_allow_index_reg (int flag)
2210{
2211 allow_index_reg = flag;
2212}
2213
cb19c032 2214static void
7bab8ab5 2215set_check (int what)
cb19c032 2216{
7bab8ab5
JB		 2217 enum check_kind *kind;
2218 const char *str;
2219
2220 if (what)
2221 {
2222 kind = &operand_check;
2223 str = "operand";
2224 }
2225 else
2226 {
2227 kind = &sse_check;
2228 str = "sse";
2229 }
2230
cb19c032
L		 2231 SKIP_WHITESPACE ();
2232
2233 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2234 {
2235 char *string = input_line_pointer;
2236 int e = get_symbol_end ();
2237
2238 if (strcmp (string, "none") == 0)
7bab8ab5 2239 *kind = check_none;
cb19c032 2240 else if (strcmp (string, "warning") == 0)
7bab8ab5 2241 *kind = check_warning;
cb19c032 2242 else if (strcmp (string, "error") == 0)
7bab8ab5 2243 *kind = check_error;
cb19c032 2244 else
7bab8ab5 2245 as_bad (_("bad argument to %s_check directive."), str);
cb19c032
L		 2246 *input_line_pointer = e;
2247 }
2248 else
7bab8ab5 2249 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2250
2251 demand_empty_rest_of_line ();
2252}
2253
8a9036a4
L		 2254static void
2255check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2256 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2257{
2258#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2259 static const char *arch;
2260
2261 /* Intel LIOM is only supported on ELF. */
2262 if (!IS_ELF)
2263 return;
2264
2265 if (!arch)
2266 {
2267 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2268 use default_arch. */
2269 arch = cpu_arch_name;
2270 if (!arch)
2271 arch = default_arch;
2272 }
2273
3632d14b 2274 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2275 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2276 || new_flag.bitfield.cpul1om)
8a9036a4 2277 return;
76ba9986 2278
7a9068fe
L		 2279 /* If we are targeting Intel K1OM, we must enable it. */
2280 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2281 || new_flag.bitfield.cpuk1om)
2282 return;
2283
8a9036a4
L		 2284 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2285#endif
2286}
2287
e413e4e9 2288static void
e3bb37b5 2289set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2290{
47926f60 2291 SKIP_WHITESPACE ();
e413e4e9 2292
29b0f896 2293 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2294 {
2295 char *string = input_line_pointer;
2296 int e = get_symbol_end ();
91d6fa6a 2297 unsigned int j;
40fb9820 2298 i386_cpu_flags flags;
e413e4e9 2299
91d6fa6a 2300 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2301 {
91d6fa6a 2302 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2303 {
91d6fa6a 2304 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2305
5c6af06e
JB		 2306 if (*string != '.')
2307 {
91d6fa6a 2308 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2309 cpu_sub_arch_name = NULL;
91d6fa6a 2310 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2311 if (flag_code == CODE_64BIT)
2312 {
2313 cpu_arch_flags.bitfield.cpu64 = 1;
2314 cpu_arch_flags.bitfield.cpuno64 = 0;
2315 }
2316 else
2317 {
2318 cpu_arch_flags.bitfield.cpu64 = 0;
2319 cpu_arch_flags.bitfield.cpuno64 = 1;
2320 }
91d6fa6a
NC		 2321 cpu_arch_isa = cpu_arch[j].type;
2322 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2323 if (!cpu_arch_tune_set)
2324 {
2325 cpu_arch_tune = cpu_arch_isa;
2326 cpu_arch_tune_flags = cpu_arch_isa_flags;
2327 }
5c6af06e
JB		 2328 break;
2329 }
40fb9820 2330
22109423 2331 if (!cpu_arch[j].negated)
309d3373 2332 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2333 cpu_arch[j].flags);
309d3373
JB		 2334 else
2335 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2336 cpu_arch[j].flags);
0dfbf9d7 2337 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2338 {
6305a203
L		 2339 if (cpu_sub_arch_name)
2340 {
2341 char *name = cpu_sub_arch_name;
2342 cpu_sub_arch_name = concat (name,
91d6fa6a 2343 cpu_arch[j].name,
1bf57e9f 2344 (const char *) NULL);
6305a203
L		 2345 free (name);
2346 }
2347 else
91d6fa6a 2348 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2349 cpu_arch_flags = flags;
a586129e 2350 cpu_arch_isa_flags = flags;
5c6af06e
JB		 2351 }
2352 *input_line_pointer = e;
2353 demand_empty_rest_of_line ();
2354 return;
e413e4e9
AM		 2355 }
2356 }
91d6fa6a 2357 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2358 as_bad (_("no such architecture: `%s'"), string);
2359
2360 *input_line_pointer = e;
2361 }
2362 else
2363 as_bad (_("missing cpu architecture"));
2364
fddf5b5b
AM		 2365 no_cond_jump_promotion = 0;
2366 if (*input_line_pointer == ','
29b0f896 2367 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2368 {
2369 char *string = ++input_line_pointer;
2370 int e = get_symbol_end ();
2371
2372 if (strcmp (string, "nojumps") == 0)
2373 no_cond_jump_promotion = 1;
2374 else if (strcmp (string, "jumps") == 0)
2375 ;
2376 else
2377 as_bad (_("no such architecture modifier: `%s'"), string);
2378
2379 *input_line_pointer = e;
2380 }
2381
e413e4e9
AM		 2382 demand_empty_rest_of_line ();
2383}
2384
8a9036a4
L		 2385enum bfd_architecture
2386i386_arch (void)
2387{
3632d14b 2388 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2389 {
2390 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2391 || flag_code != CODE_64BIT)
2392 as_fatal (_("Intel L1OM is 64bit ELF only"));
2393 return bfd_arch_l1om;
2394 }
7a9068fe
L		 2395 else if (cpu_arch_isa == PROCESSOR_K1OM)
2396 {
2397 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2398 || flag_code != CODE_64BIT)
2399 as_fatal (_("Intel K1OM is 64bit ELF only"));
2400 return bfd_arch_k1om;
2401 }
8a9036a4
L		 2402 else
2403 return bfd_arch_i386;
2404}
2405
b9d79e03 2406unsigned long
7016a5d5 2407i386_mach (void)
b9d79e03 2408{
351f65ca 2409 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2410 {
3632d14b 2411 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2412 {
351f65ca
L		 2413 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2414 || default_arch[6] != '\0')
8a9036a4
L		 2415 as_fatal (_("Intel L1OM is 64bit ELF only"));
2416 return bfd_mach_l1om;
2417 }
7a9068fe
L		 2418 else if (cpu_arch_isa == PROCESSOR_K1OM)
2419 {
2420 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2421 || default_arch[6] != '\0')
2422 as_fatal (_("Intel K1OM is 64bit ELF only"));
2423 return bfd_mach_k1om;
2424 }
351f65ca 2425 else if (default_arch[6] == '\0')
8a9036a4 2426 return bfd_mach_x86_64;
351f65ca
L		 2427 else
2428 return bfd_mach_x64_32;
8a9036a4 2429 }
b9d79e03
JH		 2430 else if (!strcmp (default_arch, "i386"))
2431 return bfd_mach_i386_i386;
2432 else
2b5d6a91 2433 as_fatal (_("unknown architecture"));
b9d79e03 2434}
b9d79e03 2435\f
252b5132 2436void
7016a5d5 2437md_begin (void)
252b5132
RH		 2438{
2439 const char *hash_err;
2440
47926f60 2441 /* Initialize op_hash hash table. */
252b5132
RH		 2442 op_hash = hash_new ();
2443
2444 {
d3ce72d0 2445 const insn_template *optab;
29b0f896 2446 templates *core_optab;
252b5132 2447
47926f60
KH		 2448 /* Setup for loop. */
2449 optab = i386_optab;
252b5132
RH		 2450 core_optab = (templates *) xmalloc (sizeof (templates));
2451 core_optab->start = optab;
2452
2453 while (1)
2454 {
2455 ++optab;
2456 if (optab->name == NULL
2457 || strcmp (optab->name, (optab - 1)->name) != 0)
2458 {
2459 /* different name --> ship out current template list;
47926f60 2460 add to hash table; & begin anew. */
252b5132
RH		 2461 core_optab->end = optab;
2462 hash_err = hash_insert (op_hash,
2463 (optab - 1)->name,
5a49b8ac 2464 (void *) core_optab);
252b5132
RH		 2465 if (hash_err)
2466 {
b37df7c4 2467 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2468 (optab - 1)->name,
2469 hash_err);
2470 }
2471 if (optab->name == NULL)
2472 break;
2473 core_optab = (templates *) xmalloc (sizeof (templates));
2474 core_optab->start = optab;
2475 }
2476 }
2477 }
2478
47926f60 2479 /* Initialize reg_hash hash table. */
252b5132
RH		 2480 reg_hash = hash_new ();
2481 {
29b0f896 2482 const reg_entry *regtab;
c3fe08fa 2483 unsigned int regtab_size = i386_regtab_size;
252b5132 2484
c3fe08fa 2485 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2486 {
5a49b8ac 2487 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2488 if (hash_err)
b37df7c4 2489 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2490 regtab->reg_name,
2491 hash_err);
252b5132
RH		 2492 }
2493 }
2494
47926f60 2495 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2496 {
29b0f896
AM		 2497 int c;
2498 char *p;
252b5132
RH		 2499
2500 for (c = 0; c < 256; c++)
2501 {
3882b010 2502 if (ISDIGIT (c))
252b5132
RH		 2503 {
2504 digit_chars[c] = c;
2505 mnemonic_chars[c] = c;
2506 register_chars[c] = c;
2507 operand_chars[c] = c;
2508 }
3882b010 2509 else if (ISLOWER (c))
252b5132
RH		 2510 {
2511 mnemonic_chars[c] = c;
2512 register_chars[c] = c;
2513 operand_chars[c] = c;
2514 }
3882b010 2515 else if (ISUPPER (c))
252b5132 2516 {
3882b010 2517 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2518 register_chars[c] = mnemonic_chars[c];
2519 operand_chars[c] = c;
2520 }
43234a1e
L		 2521 else if (c == '{' || c == '}')
2522 operand_chars[c] = c;
252b5132 2523
3882b010 2524 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2525 identifier_chars[c] = c;
2526 else if (c >= 128)
2527 {
2528 identifier_chars[c] = c;
2529 operand_chars[c] = c;
2530 }
2531 }
2532
2533#ifdef LEX_AT
2534 identifier_chars['@'] = '@';
32137342
NC		 2535#endif
2536#ifdef LEX_QM
2537 identifier_chars['?'] = '?';
2538 operand_chars['?'] = '?';
252b5132 2539#endif
252b5132 2540 digit_chars['-'] = '-';
c0f3af97 2541 mnemonic_chars['_'] = '_';
791fe849 2542 mnemonic_chars['-'] = '-';
0003779b 2543 mnemonic_chars['.'] = '.';
252b5132
RH		 2544 identifier_chars['_'] = '_';
2545 identifier_chars['.'] = '.';
2546
2547 for (p = operand_special_chars; *p != '\0'; p++)
2548 operand_chars[(unsigned char) *p] = *p;
2549 }
2550
a4447b93
RH		 2551 if (flag_code == CODE_64BIT)
2552 {
ca19b261
KT		 2553#if defined (OBJ_COFF) && defined (TE_PE)
2554 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2555 ? 32 : 16);
2556#else
a4447b93 2557 x86_dwarf2_return_column = 16;
ca19b261 2558#endif
61ff971f 2559 x86_cie_data_alignment = -8;
a4447b93
RH		 2560 }
2561 else
2562 {
2563 x86_dwarf2_return_column = 8;
2564 x86_cie_data_alignment = -4;
2565 }
252b5132
RH		 2566}
2567
2568void
e3bb37b5 2569i386_print_statistics (FILE *file)
252b5132
RH		 2570{
2571 hash_print_statistics (file, "i386 opcode", op_hash);
2572 hash_print_statistics (file, "i386 register", reg_hash);
2573}
2574\f
252b5132
RH		 2575#ifdef DEBUG386
2576
ce8a8b2f 2577/* Debugging routines for md_assemble. */
d3ce72d0 2578static void pte (insn_template *);
40fb9820 2579static void pt (i386_operand_type);
e3bb37b5
L		 2580static void pe (expressionS *);
2581static void ps (symbolS *);
252b5132
RH		 2582
2583static void
e3bb37b5 2584pi (char *line, i386_insn *x)
252b5132 2585{
09137c09 2586 unsigned int j;
252b5132
RH		 2587
2588 fprintf (stdout, "%s: template ", line);
2589 pte (&x->tm);
09f131f2
JH		 2590 fprintf (stdout, " address: base %s index %s scale %x\n",
2591 x->base_reg ? x->base_reg->reg_name : "none",
2592 x->index_reg ? x->index_reg->reg_name : "none",
2593 x->log2_scale_factor);
2594 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2595 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2596 fprintf (stdout, " sib: base %x index %x scale %x\n",
2597 x->sib.base, x->sib.index, x->sib.scale);
2598 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2599 (x->rex & REX_W) != 0,
2600 (x->rex & REX_R) != 0,
2601 (x->rex & REX_X) != 0,
2602 (x->rex & REX_B) != 0);
09137c09 2603 for (j = 0; j < x->operands; j++)
252b5132 2604 {
09137c09
SP		 2605 fprintf (stdout, " #%d: ", j + 1);
2606 pt (x->types[j]);
252b5132 2607 fprintf (stdout, "\n");
09137c09
SP		 2608 if (x->types[j].bitfield.reg8
2609 || x->types[j].bitfield.reg16
2610 || x->types[j].bitfield.reg32
2611 || x->types[j].bitfield.reg64
2612 || x->types[j].bitfield.regmmx
2613 || x->types[j].bitfield.regxmm
2614 || x->types[j].bitfield.regymm
43234a1e 2615 || x->types[j].bitfield.regzmm
09137c09
SP		 2616 || x->types[j].bitfield.sreg2
2617 || x->types[j].bitfield.sreg3
2618 || x->types[j].bitfield.control
2619 || x->types[j].bitfield.debug
2620 || x->types[j].bitfield.test)
2621 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2622 if (operand_type_check (x->types[j], imm))
2623 pe (x->op[j].imms);
2624 if (operand_type_check (x->types[j], disp))
2625 pe (x->op[j].disps);
252b5132
RH		 2626 }
2627}
2628
2629static void
d3ce72d0 2630pte (insn_template *t)
252b5132 2631{
09137c09 2632 unsigned int j;
252b5132 2633 fprintf (stdout, " %d operands ", t->operands);
47926f60 2634 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2635 if (t->extension_opcode != None)
2636 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2637 if (t->opcode_modifier.d)
252b5132 2638 fprintf (stdout, "D");
40fb9820 2639 if (t->opcode_modifier.w)
252b5132
RH		 2640 fprintf (stdout, "W");
2641 fprintf (stdout, "\n");
09137c09 2642 for (j = 0; j < t->operands; j++)
252b5132 2643 {
09137c09
SP		 2644 fprintf (stdout, " #%d type ", j + 1);
2645 pt (t->operand_types[j]);
252b5132
RH		 2646 fprintf (stdout, "\n");
2647 }
2648}
2649
2650static void
e3bb37b5 2651pe (expressionS *e)
252b5132 2652{
24eab124 2653 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2654 fprintf (stdout, " add_number %ld (%lx)\n",
2655 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2656 if (e->X_add_symbol)
2657 {
2658 fprintf (stdout, " add_symbol ");
2659 ps (e->X_add_symbol);
2660 fprintf (stdout, "\n");
2661 }
2662 if (e->X_op_symbol)
2663 {
2664 fprintf (stdout, " op_symbol ");
2665 ps (e->X_op_symbol);
2666 fprintf (stdout, "\n");
2667 }
2668}
2669
2670static void
e3bb37b5 2671ps (symbolS *s)
252b5132
RH		 2672{
2673 fprintf (stdout, "%s type %s%s",
2674 S_GET_NAME (s),
2675 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2676 segment_name (S_GET_SEGMENT (s)));
2677}
2678
7b81dfbb 2679static struct type_name
252b5132 2680 {
40fb9820
L		 2681 i386_operand_type mask;
2682 const char *name;
252b5132 2683 }
7b81dfbb 2684const type_names[] =
252b5132 2685{
40fb9820
L		 2686 { OPERAND_TYPE_REG8, "r8" },
2687 { OPERAND_TYPE_REG16, "r16" },
2688 { OPERAND_TYPE_REG32, "r32" },
2689 { OPERAND_TYPE_REG64, "r64" },
2690 { OPERAND_TYPE_IMM8, "i8" },
2691 { OPERAND_TYPE_IMM8, "i8s" },
2692 { OPERAND_TYPE_IMM16, "i16" },
2693 { OPERAND_TYPE_IMM32, "i32" },
2694 { OPERAND_TYPE_IMM32S, "i32s" },
2695 { OPERAND_TYPE_IMM64, "i64" },
2696 { OPERAND_TYPE_IMM1, "i1" },
2697 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2698 { OPERAND_TYPE_DISP8, "d8" },
2699 { OPERAND_TYPE_DISP16, "d16" },
2700 { OPERAND_TYPE_DISP32, "d32" },
2701 { OPERAND_TYPE_DISP32S, "d32s" },
2702 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2703 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2704 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2705 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2706 { OPERAND_TYPE_CONTROL, "control reg" },
2707 { OPERAND_TYPE_TEST, "test reg" },
2708 { OPERAND_TYPE_DEBUG, "debug reg" },
2709 { OPERAND_TYPE_FLOATREG, "FReg" },
2710 { OPERAND_TYPE_FLOATACC, "FAcc" },
2711 { OPERAND_TYPE_SREG2, "SReg2" },
2712 { OPERAND_TYPE_SREG3, "SReg3" },
2713 { OPERAND_TYPE_ACC, "Acc" },
2714 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2715 { OPERAND_TYPE_REGMMX, "rMMX" },
2716 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2717 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2718 { OPERAND_TYPE_REGZMM, "rZMM" },
2719 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2720 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2721};
2722
2723static void
40fb9820 2724pt (i386_operand_type t)
252b5132 2725{
40fb9820 2726 unsigned int j;
c6fb90c8 2727 i386_operand_type a;
252b5132 2728
40fb9820 2729 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2730 {
2731 a = operand_type_and (t, type_names[j].mask);
0349dc08 2732 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2733 fprintf (stdout, "%s, ", type_names[j].name);
2734 }
252b5132
RH		 2735 fflush (stdout);
2736}
2737
2738#endif /* DEBUG386 */
2739\f
252b5132 2740static bfd_reloc_code_real_type
3956db08 2741reloc (unsigned int size,
64e74474
AM		 2742 int pcrel,
2743 int sign,
2744 bfd_reloc_code_real_type other)
252b5132 2745{
47926f60 2746 if (other != NO_RELOC)
3956db08 2747 {
91d6fa6a 2748 reloc_howto_type *rel;
3956db08
JB		 2749
2750 if (size == 8)
2751 switch (other)
2752 {
64e74474
AM		 2753 case BFD_RELOC_X86_64_GOT32:
2754 return BFD_RELOC_X86_64_GOT64;
2755 break;
553d1284
L		 2756 case BFD_RELOC_X86_64_GOTPLT64:
2757 return BFD_RELOC_X86_64_GOTPLT64;
2758 break;
64e74474
AM		 2759 case BFD_RELOC_X86_64_PLTOFF64:
2760 return BFD_RELOC_X86_64_PLTOFF64;
2761 break;
2762 case BFD_RELOC_X86_64_GOTPC32:
2763 other = BFD_RELOC_X86_64_GOTPC64;
2764 break;
2765 case BFD_RELOC_X86_64_GOTPCREL:
2766 other = BFD_RELOC_X86_64_GOTPCREL64;
2767 break;
2768 case BFD_RELOC_X86_64_TPOFF32:
2769 other = BFD_RELOC_X86_64_TPOFF64;
2770 break;
2771 case BFD_RELOC_X86_64_DTPOFF32:
2772 other = BFD_RELOC_X86_64_DTPOFF64;
2773 break;
2774 default:
2775 break;
3956db08 2776 }
e05278af 2777
8ce3d284 2778#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2779 if (other == BFD_RELOC_SIZE32)
2780 {
2781 if (size == 8)
1ab668bf 2782 other = BFD_RELOC_SIZE64;
8fd4256d 2783 if (pcrel)
1ab668bf
AM		 2784 {
2785 as_bad (_("there are no pc-relative size relocations"));
2786 return NO_RELOC;
2787 }
8fd4256d 2788 }
8ce3d284 2789#endif
8fd4256d 2790
e05278af 2791 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2792 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2793 sign = -1;
2794
91d6fa6a
NC		 2795 rel = bfd_reloc_type_lookup (stdoutput, other);
2796 if (!rel)
3956db08 2797 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2798 else if (size != bfd_get_reloc_size (rel))
3956db08 2799 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2800 bfd_get_reloc_size (rel),
3956db08 2801 size);
91d6fa6a 2802 else if (pcrel && !rel->pc_relative)
3956db08 2803 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2804 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2805 && !sign)
91d6fa6a 2806 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2807 && sign > 0))
3956db08
JB		 2808 as_bad (_("relocated field and relocation type differ in signedness"));
2809 else
2810 return other;
2811 return NO_RELOC;
2812 }
252b5132
RH		 2813
2814 if (pcrel)
2815 {
3e73aa7c 2816 if (!sign)
3956db08 2817 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2818 switch (size)
2819 {
2820 case 1: return BFD_RELOC_8_PCREL;
2821 case 2: return BFD_RELOC_16_PCREL;
d258b828 2822 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2823 case 8: return BFD_RELOC_64_PCREL;
252b5132 2824 }
3956db08 2825 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2826 }
2827 else
2828 {
3956db08 2829 if (sign > 0)
e5cb08ac 2830 switch (size)
3e73aa7c
JH		 2831 {
2832 case 4: return BFD_RELOC_X86_64_32S;
2833 }
2834 else
2835 switch (size)
2836 {
2837 case 1: return BFD_RELOC_8;
2838 case 2: return BFD_RELOC_16;
2839 case 4: return BFD_RELOC_32;
2840 case 8: return BFD_RELOC_64;
2841 }
3956db08
JB		 2842 as_bad (_("cannot do %s %u byte relocation"),
2843 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2844 }
2845
0cc9e1d3 2846 return NO_RELOC;
252b5132
RH		 2847}
2848
47926f60
KH		 2849/* Here we decide which fixups can be adjusted to make them relative to
2850 the beginning of the section instead of the symbol. Basically we need
2851 to make sure that the dynamic relocations are done correctly, so in
2852 some cases we force the original symbol to be used. */
2853
252b5132 2854int
e3bb37b5 2855tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2856{
6d249963 2857#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2858 if (!IS_ELF)
31312f95
AM		 2859 return 1;
2860
a161fe53
AM		 2861 /* Don't adjust pc-relative references to merge sections in 64-bit
2862 mode. */
2863 if (use_rela_relocations
2864 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2865 && fixP->fx_pcrel)
252b5132 2866 return 0;
31312f95 2867
8d01d9a9
AJ		 2868 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2869 and changed later by validate_fix. */
2870 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2871 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2872 return 0;
2873
8fd4256d
L		 2874 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2875 for size relocations. */
2876 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2877 || fixP->fx_r_type == BFD_RELOC_SIZE64
2878 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2879 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2880 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2881 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2882 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2883 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2884 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2885 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2886 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2887 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2888 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2889 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2890 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2891 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2892 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2893 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2894 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2895 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2896 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2897 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2898 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2899 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2900 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2901 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2902 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2903 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2904 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2905 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2906 return 0;
31312f95 2907#endif
252b5132
RH		 2908 return 1;
2909}
252b5132 2910
b4cac588 2911static int
e3bb37b5 2912intel_float_operand (const char *mnemonic)
252b5132 2913{
9306ca4a
JB		 2914 /* Note that the value returned is meaningful only for opcodes with (memory)
2915 operands, hence the code here is free to improperly handle opcodes that
2916 have no operands (for better performance and smaller code). */
2917
2918 if (mnemonic[0] != 'f')
2919 return 0; /* non-math */
2920
2921 switch (mnemonic[1])
2922 {
2923 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2924 the fs segment override prefix not currently handled because no
2925 call path can make opcodes without operands get here */
2926 case 'i':
2927 return 2 /* integer op */;
2928 case 'l':
2929 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2930 return 3; /* fldcw/fldenv */
2931 break;
2932 case 'n':
2933 if (mnemonic[2] != 'o' /* fnop */)
2934 return 3; /* non-waiting control op */
2935 break;
2936 case 'r':
2937 if (mnemonic[2] == 's')
2938 return 3; /* frstor/frstpm */
2939 break;
2940 case 's':
2941 if (mnemonic[2] == 'a')
2942 return 3; /* fsave */
2943 if (mnemonic[2] == 't')
2944 {
2945 switch (mnemonic[3])
2946 {
2947 case 'c': /* fstcw */
2948 case 'd': /* fstdw */
2949 case 'e': /* fstenv */
2950 case 's': /* fsts[gw] */
2951 return 3;
2952 }
2953 }
2954 break;
2955 case 'x':
2956 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2957 return 0; /* fxsave/fxrstor are not really math ops */
2958 break;
2959 }
252b5132 2960
9306ca4a 2961 return 1;
252b5132
RH		 2962}
2963
c0f3af97
L		 2964/* Build the VEX prefix. */
2965
2966static void
d3ce72d0 2967build_vex_prefix (const insn_template *t)
c0f3af97
L		 2968{
2969 unsigned int register_specifier;
2970 unsigned int implied_prefix;
2971 unsigned int vector_length;
2972
2973 /* Check register specifier. */
2974 if (i.vex.register_specifier)
43234a1e
L		 2975 {
2976 register_specifier =
2977 ~register_number (i.vex.register_specifier) & 0xf;
2978 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
2979 }
c0f3af97
L		 2980 else
2981 register_specifier = 0xf;
2982
fa99fab2
L		 2983 /* Use 2-byte VEX prefix by swappping destination and source
2984 operand. */
2985 if (!i.swap_operand
2986 && i.operands == i.reg_operands
7f399153 2987 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 2988 && i.tm.opcode_modifier.s
2989 && i.rex == REX_B)
2990 {
2991 unsigned int xchg = i.operands - 1;
2992 union i386_op temp_op;
2993 i386_operand_type temp_type;
2994
2995 temp_type = i.types[xchg];
2996 i.types[xchg] = i.types[0];
2997 i.types[0] = temp_type;
2998 temp_op = i.op[xchg];
2999 i.op[xchg] = i.op[0];
3000 i.op[0] = temp_op;
3001
9c2799c2 3002 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3003
3004 i.rex = REX_R;
3005 xchg = i.rm.regmem;
3006 i.rm.regmem = i.rm.reg;
3007 i.rm.reg = xchg;
3008
3009 /* Use the next insn. */
3010 i.tm = t[1];
3011 }
3012
539f890d
L		 3013 if (i.tm.opcode_modifier.vex == VEXScalar)
3014 vector_length = avxscalar;
3015 else
3016 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3017
3018 switch ((i.tm.base_opcode >> 8) & 0xff)
3019 {
3020 case 0:
3021 implied_prefix = 0;
3022 break;
3023 case DATA_PREFIX_OPCODE:
3024 implied_prefix = 1;
3025 break;
3026 case REPE_PREFIX_OPCODE:
3027 implied_prefix = 2;
3028 break;
3029 case REPNE_PREFIX_OPCODE:
3030 implied_prefix = 3;
3031 break;
3032 default:
3033 abort ();
3034 }
3035
3036 /* Use 2-byte VEX prefix if possible. */
7f399153 3037 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3038 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3039 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3040 {
3041 /* 2-byte VEX prefix. */
3042 unsigned int r;
3043
3044 i.vex.length = 2;
3045 i.vex.bytes[0] = 0xc5;
3046
3047 /* Check the REX.R bit. */
3048 r = (i.rex & REX_R) ? 0 : 1;
3049 i.vex.bytes[1] = (r << 7
3050 | register_specifier << 3
3051 | vector_length << 2
3052 | implied_prefix);
3053 }
3054 else
3055 {
3056 /* 3-byte VEX prefix. */
3057 unsigned int m, w;
3058
f88c9eb0 3059 i.vex.length = 3;
f88c9eb0 3060
7f399153 3061 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3062 {
7f399153
L		 3063 case VEX0F:
3064 m = 0x1;
80de6e00 3065 i.vex.bytes[0] = 0xc4;
7f399153
L		 3066 break;
3067 case VEX0F38:
3068 m = 0x2;
80de6e00 3069 i.vex.bytes[0] = 0xc4;
7f399153
L		 3070 break;
3071 case VEX0F3A:
3072 m = 0x3;
80de6e00 3073 i.vex.bytes[0] = 0xc4;
7f399153
L		 3074 break;
3075 case XOP08:
5dd85c99
SP		 3076 m = 0x8;
3077 i.vex.bytes[0] = 0x8f;
7f399153
L		 3078 break;
3079 case XOP09:
f88c9eb0
SP		 3080 m = 0x9;
3081 i.vex.bytes[0] = 0x8f;
7f399153
L		 3082 break;
3083 case XOP0A:
f88c9eb0
SP		 3084 m = 0xa;
3085 i.vex.bytes[0] = 0x8f;
7f399153
L		 3086 break;
3087 default:
3088 abort ();
f88c9eb0 3089 }
c0f3af97 3090
c0f3af97
L		 3091 /* The high 3 bits of the second VEX byte are 1's compliment
3092 of RXB bits from REX. */
3093 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3094
3095 /* Check the REX.W bit. */
3096 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3097 if (i.tm.opcode_modifier.vexw == VEXW1)
3098 w = 1;
c0f3af97
L		 3099
3100 i.vex.bytes[2] = (w << 7
3101 | register_specifier << 3
3102 | vector_length << 2
3103 | implied_prefix);
3104 }
3105}
3106
43234a1e
L		 3107/* Build the EVEX prefix. */
3108
3109static void
3110build_evex_prefix (void)
3111{
3112 unsigned int register_specifier;
3113 unsigned int implied_prefix;
3114 unsigned int m, w;
3115 rex_byte vrex_used = 0;
3116
3117 /* Check register specifier. */
3118 if (i.vex.register_specifier)
3119 {
3120 gas_assert ((i.vrex & REX_X) == 0);
3121
3122 register_specifier = i.vex.register_specifier->reg_num;
3123 if ((i.vex.register_specifier->reg_flags & RegRex))
3124 register_specifier += 8;
3125 /* The upper 16 registers are encoded in the fourth byte of the
3126 EVEX prefix. */
3127 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3128 i.vex.bytes[3] = 0x8;
3129 register_specifier = ~register_specifier & 0xf;
3130 }
3131 else
3132 {
3133 register_specifier = 0xf;
3134
3135 /* Encode upper 16 vector index register in the fourth byte of
3136 the EVEX prefix. */
3137 if (!(i.vrex & REX_X))
3138 i.vex.bytes[3] = 0x8;
3139 else
3140 vrex_used |= REX_X;
3141 }
3142
3143 switch ((i.tm.base_opcode >> 8) & 0xff)
3144 {
3145 case 0:
3146 implied_prefix = 0;
3147 break;
3148 case DATA_PREFIX_OPCODE:
3149 implied_prefix = 1;
3150 break;
3151 case REPE_PREFIX_OPCODE:
3152 implied_prefix = 2;
3153 break;
3154 case REPNE_PREFIX_OPCODE:
3155 implied_prefix = 3;
3156 break;
3157 default:
3158 abort ();
3159 }
3160
3161 /* 4 byte EVEX prefix. */
3162 i.vex.length = 4;
3163 i.vex.bytes[0] = 0x62;
3164
3165 /* mmmm bits. */
3166 switch (i.tm.opcode_modifier.vexopcode)
3167 {
3168 case VEX0F:
3169 m = 1;
3170 break;
3171 case VEX0F38:
3172 m = 2;
3173 break;
3174 case VEX0F3A:
3175 m = 3;
3176 break;
3177 default:
3178 abort ();
3179 break;
3180 }
3181
3182 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3183 bits from REX. */
3184 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3185
3186 /* The fifth bit of the second EVEX byte is 1's compliment of the
3187 REX_R bit in VREX. */
3188 if (!(i.vrex & REX_R))
3189 i.vex.bytes[1] |= 0x10;
3190 else
3191 vrex_used |= REX_R;
3192
3193 if ((i.reg_operands + i.imm_operands) == i.operands)
3194 {
3195 /* When all operands are registers, the REX_X bit in REX is not
3196 used. We reuse it to encode the upper 16 registers, which is
3197 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3198 as 1's compliment. */
3199 if ((i.vrex & REX_B))
3200 {
3201 vrex_used |= REX_B;
3202 i.vex.bytes[1] &= ~0x40;
3203 }
3204 }
3205
3206 /* EVEX instructions shouldn't need the REX prefix. */
3207 i.vrex &= ~vrex_used;
3208 gas_assert (i.vrex == 0);
3209
3210 /* Check the REX.W bit. */
3211 w = (i.rex & REX_W) ? 1 : 0;
3212 if (i.tm.opcode_modifier.vexw)
3213 {
3214 if (i.tm.opcode_modifier.vexw == VEXW1)
3215 w = 1;
3216 }
3217 /* If w is not set it means we are dealing with WIG instruction. */
3218 else if (!w)
3219 {
3220 if (evexwig == evexw1)
3221 w = 1;
3222 }
3223
3224 /* Encode the U bit. */
3225 implied_prefix |= 0x4;
3226
3227 /* The third byte of the EVEX prefix. */
3228 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3229
3230 /* The fourth byte of the EVEX prefix. */
3231 /* The zeroing-masking bit. */
3232 if (i.mask && i.mask->zeroing)
3233 i.vex.bytes[3] |= 0x80;
3234
3235 /* Don't always set the broadcast bit if there is no RC. */
3236 if (!i.rounding)
3237 {
3238 /* Encode the vector length. */
3239 unsigned int vec_length;
3240
3241 switch (i.tm.opcode_modifier.evex)
3242 {
3243 case EVEXLIG: /* LL' is ignored */
3244 vec_length = evexlig << 5;
3245 break;
3246 case EVEX128:
3247 vec_length = 0 << 5;
3248 break;
3249 case EVEX256:
3250 vec_length = 1 << 5;
3251 break;
3252 case EVEX512:
3253 vec_length = 2 << 5;
3254 break;
3255 default:
3256 abort ();
3257 break;
3258 }
3259 i.vex.bytes[3] |= vec_length;
3260 /* Encode the broadcast bit. */
3261 if (i.broadcast)
3262 i.vex.bytes[3] |= 0x10;
3263 }
3264 else
3265 {
3266 if (i.rounding->type != saeonly)
3267 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3268 else
d3d3c6db 3269 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3270 }
3271
3272 if (i.mask && i.mask->mask)
3273 i.vex.bytes[3] |= i.mask->mask->reg_num;
3274}
3275
65da13b5
L		 3276static void
3277process_immext (void)
3278{
3279 expressionS *exp;
3280
4c692bc7
JB		 3281 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3282 && i.operands > 0)
65da13b5 3283 {
4c692bc7
JB		 3284 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3285 with an opcode suffix which is coded in the same place as an
3286 8-bit immediate field would be.
3287 Here we check those operands and remove them afterwards. */
65da13b5
L		 3288 unsigned int x;
3289
3290 for (x = 0; x < i.operands; x++)
4c692bc7 3291 if (register_number (i.op[x].regs) != x)
65da13b5 3292 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3293 register_prefix, i.op[x].regs->reg_name, x + 1,
3294 i.tm.name);
3295
3296 i.operands = 0;
65da13b5
L		 3297 }
3298
c0f3af97 3299 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3300 which is coded in the same place as an 8-bit immediate field
3301 would be. Here we fake an 8-bit immediate operand from the
3302 opcode suffix stored in tm.extension_opcode.
3303
c1e679ec 3304 AVX instructions also use this encoding, for some of
c0f3af97 3305 3 argument instructions. */
65da13b5 3306
43234a1e 3307 gas_assert (i.imm_operands <= 1
7ab9ffdd 3308 && (i.operands <= 2
43234a1e
L		 3309 || ((i.tm.opcode_modifier.vex
3310 || i.tm.opcode_modifier.evex)
7ab9ffdd 3311 && i.operands <= 4)));
65da13b5
L		 3312
3313 exp = &im_expressions[i.imm_operands++];
3314 i.op[i.operands].imms = exp;
3315 i.types[i.operands] = imm8;
3316 i.operands++;
3317 exp->X_op = O_constant;
3318 exp->X_add_number = i.tm.extension_opcode;
3319 i.tm.extension_opcode = None;
3320}
3321
42164a71
L		 3322
3323static int
3324check_hle (void)
3325{
3326 switch (i.tm.opcode_modifier.hleprefixok)
3327 {
3328 default:
3329 abort ();
82c2def5 3330 case HLEPrefixNone:
165de32a
L		 3331 as_bad (_("invalid instruction `%s' after `%s'"),
3332 i.tm.name, i.hle_prefix);
42164a71 3333 return 0;
82c2def5 3334 case HLEPrefixLock:
42164a71
L		 3335 if (i.prefix[LOCK_PREFIX])
3336 return 1;
165de32a 3337 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3338 return 0;
82c2def5 3339 case HLEPrefixAny:
42164a71 3340 return 1;
82c2def5 3341 case HLEPrefixRelease:
42164a71
L		 3342 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3343 {
3344 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3345 i.tm.name);
3346 return 0;
3347 }
3348 if (i.mem_operands == 0
3349 || !operand_type_check (i.types[i.operands - 1], anymem))
3350 {
3351 as_bad (_("memory destination needed for instruction `%s'"
3352 " after `xrelease'"), i.tm.name);
3353 return 0;
3354 }
3355 return 1;
3356 }
3357}
3358
252b5132
RH		 3359/* This is the guts of the machine-dependent assembler. LINE points to a
3360 machine dependent instruction. This function is supposed to emit
3361 the frags/bytes it assembles to. */
3362
3363void
65da13b5 3364md_assemble (char *line)
252b5132 3365{
40fb9820 3366 unsigned int j;
252b5132 3367 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3368 const insn_template *t;
252b5132 3369
47926f60 3370 /* Initialize globals. */
252b5132
RH		 3371 memset (&i, '\0', sizeof (i));
3372 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3373 i.reloc[j] = NO_RELOC;
252b5132
RH		 3374 memset (disp_expressions, '\0', sizeof (disp_expressions));
3375 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3376 save_stack_p = save_stack;
252b5132
RH		 3377
3378 /* First parse an instruction mnemonic & call i386_operand for the operands.
3379 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3380 start of a (possibly prefixed) mnemonic. */
252b5132 3381
29b0f896
AM		 3382 line = parse_insn (line, mnemonic);
3383 if (line == NULL)
3384 return;
252b5132 3385
29b0f896 3386 line = parse_operands (line, mnemonic);
ee86248c 3387 this_operand = -1;
29b0f896
AM		 3388 if (line == NULL)
3389 return;
252b5132 3390
29b0f896
AM		 3391 /* Now we've parsed the mnemonic into a set of templates, and have the
3392 operands at hand. */
3393
3394 /* All intel opcodes have reversed operands except for "bound" and
3395 "enter". We also don't reverse intersegment "jmp" and "call"
3396 instructions with 2 immediate operands so that the immediate segment
050dfa73 3397 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3398 if (intel_syntax
3399 && i.operands > 1
29b0f896 3400 && (strcmp (mnemonic, "bound") != 0)
30123838 3401 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3402 && !(operand_type_check (i.types[0], imm)
3403 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3404 swap_operands ();
3405
ec56d5c0
JB		 3406 /* The order of the immediates should be reversed
3407 for 2 immediates extrq and insertq instructions */
3408 if (i.imm_operands == 2
3409 && (strcmp (mnemonic, "extrq") == 0
3410 || strcmp (mnemonic, "insertq") == 0))
3411 swap_2_operands (0, 1);
3412
29b0f896
AM		 3413 if (i.imm_operands)
3414 optimize_imm ();
3415
b300c311
L		 3416 /* Don't optimize displacement for movabs since it only takes 64bit
3417 displacement. */
3418 if (i.disp_operands
a501d77e 3419 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3420 && (flag_code != CODE_64BIT
3421 || strcmp (mnemonic, "movabs") != 0))
3422 optimize_disp ();
29b0f896
AM		 3423
3424 /* Next, we find a template that matches the given insn,
3425 making sure the overlap of the given operands types is consistent
3426 with the template operand types. */
252b5132 3427
fa99fab2 3428 if (!(t = match_template ()))
29b0f896 3429 return;
252b5132 3430
7bab8ab5 3431 if (sse_check != check_none
81f8a913 3432 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3433 && (i.tm.cpu_flags.bitfield.cpusse
3434 || i.tm.cpu_flags.bitfield.cpusse2
3435 || i.tm.cpu_flags.bitfield.cpusse3
3436 || i.tm.cpu_flags.bitfield.cpussse3
3437 || i.tm.cpu_flags.bitfield.cpusse4_1
3438 || i.tm.cpu_flags.bitfield.cpusse4_2))
3439 {
7bab8ab5 3440 (sse_check == check_warning
daf50ae7
L		 3441 ? as_warn
3442 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3443 }
3444
321fd21e
L		 3445 /* Zap movzx and movsx suffix. The suffix has been set from
3446 "word ptr" or "byte ptr" on the source operand in Intel syntax
3447 or extracted from mnemonic in AT&T syntax. But we'll use
3448 the destination register to choose the suffix for encoding. */
3449 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3450 {
321fd21e
L		 3451 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3452 there is no suffix, the default will be byte extension. */
3453 if (i.reg_operands != 2
3454 && !i.suffix
7ab9ffdd 3455 && intel_syntax)
321fd21e
L		 3456 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3457
3458 i.suffix = 0;
cd61ebfe 3459 }
24eab124 3460
40fb9820 3461 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3462 if (!add_prefix (FWAIT_OPCODE))
3463 return;
252b5132 3464
d5de92cf
L		 3465 /* Check if REP prefix is OK. */
3466 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3467 {
3468 as_bad (_("invalid instruction `%s' after `%s'"),
3469 i.tm.name, i.rep_prefix);
3470 return;
3471 }
3472
c1ba0266
L		 3473 /* Check for lock without a lockable instruction. Destination operand
3474 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3475 if (i.prefix[LOCK_PREFIX]
3476 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3477 || i.mem_operands == 0
3478 || (i.tm.base_opcode != 0x86
3479 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3480 {
3481 as_bad (_("expecting lockable instruction after `lock'"));
3482 return;
3483 }
3484
42164a71 3485 /* Check if HLE prefix is OK. */
165de32a 3486 if (i.hle_prefix && !check_hle ())
42164a71
L		 3487 return;
3488
7e8b059b
L		 3489 /* Check BND prefix. */
3490 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3491 as_bad (_("expecting valid branch instruction after `bnd'"));
3492
3493 if (i.tm.cpu_flags.bitfield.cpumpx
3494 && flag_code == CODE_64BIT
3495 && i.prefix[ADDR_PREFIX])
3496 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3497
3498 /* Insert BND prefix. */
3499 if (add_bnd_prefix
3500 && i.tm.opcode_modifier.bndprefixok
3501 && !i.prefix[BND_PREFIX])
3502 add_prefix (BND_PREFIX_OPCODE);
3503
29b0f896 3504 /* Check string instruction segment overrides. */
40fb9820 3505 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3506 {
3507 if (!check_string ())
5dd0794d 3508 return;
fc0763e6 3509 i.disp_operands = 0;
29b0f896 3510 }
5dd0794d 3511
29b0f896
AM		 3512 if (!process_suffix ())
3513 return;
e413e4e9 3514
bc0844ae
L		 3515 /* Update operand types. */
3516 for (j = 0; j < i.operands; j++)
3517 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3518
29b0f896
AM		 3519 /* Make still unresolved immediate matches conform to size of immediate
3520 given in i.suffix. */
3521 if (!finalize_imm ())
3522 return;
252b5132 3523
40fb9820 3524 if (i.types[0].bitfield.imm1)
29b0f896 3525 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3526
9afe6eb8
L		 3527 /* We only need to check those implicit registers for instructions
3528 with 3 operands or less. */
3529 if (i.operands <= 3)
3530 for (j = 0; j < i.operands; j++)
3531 if (i.types[j].bitfield.inoutportreg
3532 || i.types[j].bitfield.shiftcount
3533 || i.types[j].bitfield.acc
3534 || i.types[j].bitfield.floatacc)
3535 i.reg_operands--;
40fb9820 3536
c0f3af97
L		 3537 /* ImmExt should be processed after SSE2AVX. */
3538 if (!i.tm.opcode_modifier.sse2avx
3539 && i.tm.opcode_modifier.immext)
65da13b5 3540 process_immext ();
252b5132 3541
29b0f896
AM		 3542 /* For insns with operands there are more diddles to do to the opcode. */
3543 if (i.operands)
3544 {
3545 if (!process_operands ())
3546 return;
3547 }
40fb9820 3548 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3549 {
3550 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3551 as_warn (_("translating to `%sp'"), i.tm.name);
3552 }
252b5132 3553
9e5e5283
L		 3554 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3555 {
3556 if (flag_code == CODE_16BIT)
3557 {
3558 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3559 i.tm.name);
3560 return;
3561 }
c0f3af97 3562
9e5e5283
L		 3563 if (i.tm.opcode_modifier.vex)
3564 build_vex_prefix (t);
3565 else
3566 build_evex_prefix ();
3567 }
43234a1e 3568
5dd85c99
SP		 3569 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3570 instructions may define INT_OPCODE as well, so avoid this corner
3571 case for those instructions that use MODRM. */
3572 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3573 && !i.tm.opcode_modifier.modrm
3574 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3575 {
3576 i.tm.base_opcode = INT3_OPCODE;
3577 i.imm_operands = 0;
3578 }
252b5132 3579
40fb9820
L		 3580 if ((i.tm.opcode_modifier.jump
3581 || i.tm.opcode_modifier.jumpbyte
3582 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3583 && i.op[0].disps->X_op == O_constant)
3584 {
3585 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3586 the absolute address given by the constant. Since ix86 jumps and
3587 calls are pc relative, we need to generate a reloc. */
3588 i.op[0].disps->X_add_symbol = &abs_symbol;
3589 i.op[0].disps->X_op = O_symbol;
3590 }
252b5132 3591
40fb9820 3592 if (i.tm.opcode_modifier.rex64)
161a04f6 3593 i.rex |= REX_W;
252b5132 3594
29b0f896
AM		 3595 /* For 8 bit registers we need an empty rex prefix. Also if the
3596 instruction already has a prefix, we need to convert old
3597 registers to new ones. */
773f551c 3598
40fb9820 3599 if ((i.types[0].bitfield.reg8
29b0f896 3600 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3601 || (i.types[1].bitfield.reg8
29b0f896 3602 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3603 || ((i.types[0].bitfield.reg8
3604 || i.types[1].bitfield.reg8)
29b0f896
AM		 3605 && i.rex != 0))
3606 {
3607 int x;
726c5dcd 3608
29b0f896
AM		 3609 i.rex |= REX_OPCODE;
3610 for (x = 0; x < 2; x++)
3611 {
3612 /* Look for 8 bit operand that uses old registers. */
40fb9820 3613 if (i.types[x].bitfield.reg8
29b0f896 3614 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3615 {
29b0f896
AM		 3616 /* In case it is "hi" register, give up. */
3617 if (i.op[x].regs->reg_num > 3)
a540244d 3618 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3619 "instruction requiring REX prefix."),
a540244d 3620 register_prefix, i.op[x].regs->reg_name);
773f551c 3621
29b0f896
AM		 3622 /* Otherwise it is equivalent to the extended register.
3623 Since the encoding doesn't change this is merely
3624 cosmetic cleanup for debug output. */
3625
3626 i.op[x].regs = i.op[x].regs + 8;
773f551c 3627 }
29b0f896
AM		 3628 }
3629 }
773f551c 3630
7ab9ffdd 3631 if (i.rex != 0)
29b0f896
AM		 3632 add_prefix (REX_OPCODE | i.rex);
3633
3634 /* We are ready to output the insn. */
3635 output_insn ();
3636}
3637
3638static char *
e3bb37b5 3639parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3640{
3641 char *l = line;
3642 char *token_start = l;
3643 char *mnem_p;
5c6af06e 3644 int supported;
d3ce72d0 3645 const insn_template *t;
b6169b20 3646 char *dot_p = NULL;
29b0f896 3647
29b0f896
AM		 3648 while (1)
3649 {
3650 mnem_p = mnemonic;
3651 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3652 {
b6169b20
L		 3653 if (*mnem_p == '.')
3654 dot_p = mnem_p;
29b0f896
AM		 3655 mnem_p++;
3656 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3657 {
29b0f896
AM		 3658 as_bad (_("no such instruction: `%s'"), token_start);
3659 return NULL;
3660 }
3661 l++;
3662 }
3663 if (!is_space_char (*l)
3664 && *l != END_OF_INSN
e44823cf
JB		 3665 && (intel_syntax
3666 || (*l != PREFIX_SEPARATOR
3667 && *l != ',')))
29b0f896
AM		 3668 {
3669 as_bad (_("invalid character %s in mnemonic"),
3670 output_invalid (*l));
3671 return NULL;
3672 }
3673 if (token_start == l)
3674 {
e44823cf 3675 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3676 as_bad (_("expecting prefix; got nothing"));
3677 else
3678 as_bad (_("expecting mnemonic; got nothing"));
3679 return NULL;
3680 }
45288df1 3681
29b0f896 3682 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3683 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3684
29b0f896
AM		 3685 if (*l != END_OF_INSN
3686 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3687 && current_templates
40fb9820 3688 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3689 {
c6fb90c8 3690 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3691 {
3692 as_bad ((flag_code != CODE_64BIT
3693 ? _("`%s' is only supported in 64-bit mode")
3694 : _("`%s' is not supported in 64-bit mode")),
3695 current_templates->start->name);
3696 return NULL;
3697 }
29b0f896
AM		 3698 /* If we are in 16-bit mode, do not allow addr16 or data16.
3699 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3700 if ((current_templates->start->opcode_modifier.size16
3701 || current_templates->start->opcode_modifier.size32)
29b0f896 3702 && flag_code != CODE_64BIT
40fb9820 3703 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3704 ^ (flag_code == CODE_16BIT)))
3705 {
3706 as_bad (_("redundant %s prefix"),
3707 current_templates->start->name);
3708 return NULL;
45288df1 3709 }
29b0f896
AM		 3710 /* Add prefix, checking for repeated prefixes. */
3711 switch (add_prefix (current_templates->start->base_opcode))
3712 {
c32fa91d 3713 case PREFIX_EXIST:
29b0f896 3714 return NULL;
c32fa91d 3715 case PREFIX_REP:
42164a71 3716 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3717 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3718 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3719 i.bnd_prefix = current_templates->start->name;
42164a71 3720 else
d5de92cf 3721 i.rep_prefix = current_templates->start->name;
29b0f896 3722 break;
c32fa91d
L		 3723 default:
3724 break;
29b0f896
AM		 3725 }
3726 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3727 token_start = ++l;
3728 }
3729 else
3730 break;
3731 }
45288df1 3732
30a55f88 3733 if (!current_templates)
b6169b20 3734 {
f8a5c266
L		 3735 /* Check if we should swap operand or force 32bit displacement in
3736 encoding. */
30a55f88
L		 3737 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3738 i.swap_operand = 1;
8d63c93e 3739 else if (mnem_p - 3 == dot_p
a501d77e
L		 3740 && dot_p[1] == 'd'
3741 && dot_p[2] == '8')
3742 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3743 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3744 && dot_p[1] == 'd'
3745 && dot_p[2] == '3'
3746 && dot_p[3] == '2')
a501d77e 3747 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3748 else
3749 goto check_suffix;
3750 mnem_p = dot_p;
3751 *dot_p = '\0';
d3ce72d0 3752 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3753 }
3754
29b0f896
AM		 3755 if (!current_templates)
3756 {
b6169b20 3757check_suffix:
29b0f896
AM		 3758 /* See if we can get a match by trimming off a suffix. */
3759 switch (mnem_p[-1])
3760 {
3761 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3762 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3763 i.suffix = SHORT_MNEM_SUFFIX;
3764 else
29b0f896
AM		 3765 case BYTE_MNEM_SUFFIX:
3766 case QWORD_MNEM_SUFFIX:
3767 i.suffix = mnem_p[-1];
3768 mnem_p[-1] = '\0';
d3ce72d0
NC		 3769 current_templates = (const templates *) hash_find (op_hash,
3770 mnemonic);
29b0f896
AM		 3771 break;
3772 case SHORT_MNEM_SUFFIX:
3773 case LONG_MNEM_SUFFIX:
3774 if (!intel_syntax)
3775 {
3776 i.suffix = mnem_p[-1];
3777 mnem_p[-1] = '\0';
d3ce72d0
NC		 3778 current_templates = (const templates *) hash_find (op_hash,
3779 mnemonic);
29b0f896
AM		 3780 }
3781 break;
252b5132 3782
29b0f896
AM		 3783 /* Intel Syntax. */
3784 case 'd':
3785 if (intel_syntax)
3786 {
9306ca4a 3787 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3788 i.suffix = SHORT_MNEM_SUFFIX;
3789 else
3790 i.suffix = LONG_MNEM_SUFFIX;
3791 mnem_p[-1] = '\0';
d3ce72d0
NC		 3792 current_templates = (const templates *) hash_find (op_hash,
3793 mnemonic);
29b0f896
AM		 3794 }
3795 break;
3796 }
3797 if (!current_templates)
3798 {
3799 as_bad (_("no such instruction: `%s'"), token_start);
3800 return NULL;
3801 }
3802 }
252b5132 3803
40fb9820
L		 3804 if (current_templates->start->opcode_modifier.jump
3805 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3806 {
3807 /* Check for a branch hint. We allow ",pt" and ",pn" for
3808 predict taken and predict not taken respectively.
3809 I'm not sure that branch hints actually do anything on loop
3810 and jcxz insns (JumpByte) for current Pentium4 chips. They
3811 may work in the future and it doesn't hurt to accept them
3812 now. */
3813 if (l[0] == ',' && l[1] == 'p')
3814 {
3815 if (l[2] == 't')
3816 {
3817 if (!add_prefix (DS_PREFIX_OPCODE))
3818 return NULL;
3819 l += 3;
3820 }
3821 else if (l[2] == 'n')
3822 {
3823 if (!add_prefix (CS_PREFIX_OPCODE))
3824 return NULL;
3825 l += 3;
3826 }
3827 }
3828 }
3829 /* Any other comma loses. */
3830 if (*l == ',')
3831 {
3832 as_bad (_("invalid character %s in mnemonic"),
3833 output_invalid (*l));
3834 return NULL;
3835 }
252b5132 3836
29b0f896 3837 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3838 supported = 0;
3839 for (t = current_templates->start; t < current_templates->end; ++t)
3840 {
c0f3af97
L		 3841 supported |= cpu_flags_match (t);
3842 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3843 goto skip;
5c6af06e 3844 }
3629bb00 3845
c0f3af97 3846 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3847 {
3848 as_bad (flag_code == CODE_64BIT
3849 ? _("`%s' is not supported in 64-bit mode")
3850 : _("`%s' is only supported in 64-bit mode"),
3851 current_templates->start->name);
3852 return NULL;
3853 }
c0f3af97 3854 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3855 {
3629bb00 3856 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3857 current_templates->start->name,
41aacd83 3858 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3859 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3860 return NULL;
29b0f896 3861 }
3629bb00
L		 3862
3863skip:
3864 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3865 && (flag_code != CODE_16BIT))
29b0f896
AM		 3866 {
3867 as_warn (_("use .code16 to ensure correct addressing mode"));
3868 }
252b5132 3869
29b0f896
AM		 3870 return l;
3871}
252b5132 3872
29b0f896 3873static char *
e3bb37b5 3874parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3875{
3876 char *token_start;
3138f287 3877
29b0f896
AM		 3878 /* 1 if operand is pending after ','. */
3879 unsigned int expecting_operand = 0;
252b5132 3880
29b0f896
AM		 3881 /* Non-zero if operand parens not balanced. */
3882 unsigned int paren_not_balanced;
3883
3884 while (*l != END_OF_INSN)
3885 {
3886 /* Skip optional white space before operand. */
3887 if (is_space_char (*l))
3888 ++l;
3889 if (!is_operand_char (*l) && *l != END_OF_INSN)
3890 {
3891 as_bad (_("invalid character %s before operand %d"),
3892 output_invalid (*l),
3893 i.operands + 1);
3894 return NULL;
3895 }
3896 token_start = l; /* after white space */
3897 paren_not_balanced = 0;
3898 while (paren_not_balanced || *l != ',')
3899 {
3900 if (*l == END_OF_INSN)
3901 {
3902 if (paren_not_balanced)
3903 {
3904 if (!intel_syntax)
3905 as_bad (_("unbalanced parenthesis in operand %d."),
3906 i.operands + 1);
3907 else
3908 as_bad (_("unbalanced brackets in operand %d."),
3909 i.operands + 1);
3910 return NULL;
3911 }
3912 else
3913 break; /* we are done */
3914 }
3915 else if (!is_operand_char (*l) && !is_space_char (*l))
3916 {
3917 as_bad (_("invalid character %s in operand %d"),
3918 output_invalid (*l),
3919 i.operands + 1);
3920 return NULL;
3921 }
3922 if (!intel_syntax)
3923 {
3924 if (*l == '(')
3925 ++paren_not_balanced;
3926 if (*l == ')')
3927 --paren_not_balanced;
3928 }
3929 else
3930 {
3931 if (*l == '[')
3932 ++paren_not_balanced;
3933 if (*l == ']')
3934 --paren_not_balanced;
3935 }
3936 l++;
3937 }
3938 if (l != token_start)
3939 { /* Yes, we've read in another operand. */
3940 unsigned int operand_ok;
3941 this_operand = i.operands++;
7d5e4556 3942 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3943 if (i.operands > MAX_OPERANDS)
3944 {
3945 as_bad (_("spurious operands; (%d operands/instruction max)"),
3946 MAX_OPERANDS);
3947 return NULL;
3948 }
3949 /* Now parse operand adding info to 'i' as we go along. */
3950 END_STRING_AND_SAVE (l);
3951
3952 if (intel_syntax)
3953 operand_ok =
3954 i386_intel_operand (token_start,
3955 intel_float_operand (mnemonic));
3956 else
a7619375 3957 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3958
3959 RESTORE_END_STRING (l);
3960 if (!operand_ok)
3961 return NULL;
3962 }
3963 else
3964 {
3965 if (expecting_operand)
3966 {
3967 expecting_operand_after_comma:
3968 as_bad (_("expecting operand after ','; got nothing"));
3969 return NULL;
3970 }
3971 if (*l == ',')
3972 {
3973 as_bad (_("expecting operand before ','; got nothing"));
3974 return NULL;
3975 }
3976 }
7f3f1ea2 3977
29b0f896
AM		 3978 /* Now *l must be either ',' or END_OF_INSN. */
3979 if (*l == ',')
3980 {
3981 if (*++l == END_OF_INSN)
3982 {
3983 /* Just skip it, if it's \n complain. */
3984 goto expecting_operand_after_comma;
3985 }
3986 expecting_operand = 1;
3987 }
3988 }
3989 return l;
3990}
7f3f1ea2 3991
050dfa73 3992static void
4d456e3d 3993swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3994{
3995 union i386_op temp_op;
40fb9820 3996 i386_operand_type temp_type;
050dfa73 3997 enum bfd_reloc_code_real temp_reloc;
4eed87de 3998
050dfa73
MM		 3999 temp_type = i.types[xchg2];
4000 i.types[xchg2] = i.types[xchg1];
4001 i.types[xchg1] = temp_type;
4002 temp_op = i.op[xchg2];
4003 i.op[xchg2] = i.op[xchg1];
4004 i.op[xchg1] = temp_op;
4005 temp_reloc = i.reloc[xchg2];
4006 i.reloc[xchg2] = i.reloc[xchg1];
4007 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4008
4009 if (i.mask)
4010 {
4011 if (i.mask->operand == xchg1)
4012 i.mask->operand = xchg2;
4013 else if (i.mask->operand == xchg2)
4014 i.mask->operand = xchg1;
4015 }
4016 if (i.broadcast)
4017 {
4018 if (i.broadcast->operand == xchg1)
4019 i.broadcast->operand = xchg2;
4020 else if (i.broadcast->operand == xchg2)
4021 i.broadcast->operand = xchg1;
4022 }
4023 if (i.rounding)
4024 {
4025 if (i.rounding->operand == xchg1)
4026 i.rounding->operand = xchg2;
4027 else if (i.rounding->operand == xchg2)
4028 i.rounding->operand = xchg1;
4029 }
050dfa73
MM		 4030}
4031
29b0f896 4032static void
e3bb37b5 4033swap_operands (void)
29b0f896 4034{
b7c61d9a 4035 switch (i.operands)
050dfa73 4036 {
c0f3af97 4037 case 5:
b7c61d9a 4038 case 4:
4d456e3d 4039 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4040 case 3:
4041 case 2:
4d456e3d 4042 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4043 break;
4044 default:
4045 abort ();
29b0f896 4046 }
29b0f896
AM		 4047
4048 if (i.mem_operands == 2)
4049 {
4050 const seg_entry *temp_seg;
4051 temp_seg = i.seg[0];
4052 i.seg[0] = i.seg[1];
4053 i.seg[1] = temp_seg;
4054 }
4055}
252b5132 4056
29b0f896
AM		 4057/* Try to ensure constant immediates are represented in the smallest
4058 opcode possible. */
4059static void
e3bb37b5 4060optimize_imm (void)
29b0f896
AM		 4061{
4062 char guess_suffix = 0;
4063 int op;
252b5132 4064
29b0f896
AM		 4065 if (i.suffix)
4066 guess_suffix = i.suffix;
4067 else if (i.reg_operands)
4068 {
4069 /* Figure out a suffix from the last register operand specified.
4070 We can't do this properly yet, ie. excluding InOutPortReg,
4071 but the following works for instructions with immediates.
4072 In any case, we can't set i.suffix yet. */
4073 for (op = i.operands; --op >= 0;)
40fb9820 4074 if (i.types[op].bitfield.reg8)
7ab9ffdd 4075 {
40fb9820
L		 4076 guess_suffix = BYTE_MNEM_SUFFIX;
4077 break;
4078 }
4079 else if (i.types[op].bitfield.reg16)
252b5132 4080 {
40fb9820
L		 4081 guess_suffix = WORD_MNEM_SUFFIX;
4082 break;
4083 }
4084 else if (i.types[op].bitfield.reg32)
4085 {
4086 guess_suffix = LONG_MNEM_SUFFIX;
4087 break;
4088 }
4089 else if (i.types[op].bitfield.reg64)
4090 {
4091 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4092 break;
252b5132 4093 }
29b0f896
AM		 4094 }
4095 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4096 guess_suffix = WORD_MNEM_SUFFIX;
4097
4098 for (op = i.operands; --op >= 0;)
40fb9820 4099 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4100 {
4101 switch (i.op[op].imms->X_op)
252b5132 4102 {
29b0f896
AM		 4103 case O_constant:
4104 /* If a suffix is given, this operand may be shortened. */
4105 switch (guess_suffix)
252b5132 4106 {
29b0f896 4107 case LONG_MNEM_SUFFIX:
40fb9820
L		 4108 i.types[op].bitfield.imm32 = 1;
4109 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4110 break;
4111 case WORD_MNEM_SUFFIX:
40fb9820
L		 4112 i.types[op].bitfield.imm16 = 1;
4113 i.types[op].bitfield.imm32 = 1;
4114 i.types[op].bitfield.imm32s = 1;
4115 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4116 break;
4117 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4118 i.types[op].bitfield.imm8 = 1;
4119 i.types[op].bitfield.imm8s = 1;
4120 i.types[op].bitfield.imm16 = 1;
4121 i.types[op].bitfield.imm32 = 1;
4122 i.types[op].bitfield.imm32s = 1;
4123 i.types[op].bitfield.imm64 = 1;
29b0f896 4124 break;
252b5132 4125 }
252b5132 4126
29b0f896
AM		 4127 /* If this operand is at most 16 bits, convert it
4128 to a signed 16 bit number before trying to see
4129 whether it will fit in an even smaller size.
4130 This allows a 16-bit operand such as $0xffe0 to
4131 be recognised as within Imm8S range. */
40fb9820 4132 if ((i.types[op].bitfield.imm16)
29b0f896 4133 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4134 {
29b0f896
AM		 4135 i.op[op].imms->X_add_number =
4136 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4137 }
40fb9820 4138 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4139 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4140 == 0))
4141 {
4142 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4143 ^ ((offsetT) 1 << 31))
4144 - ((offsetT) 1 << 31));
4145 }
40fb9820 4146 i.types[op]
c6fb90c8
L		 4147 = operand_type_or (i.types[op],
4148 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4149
29b0f896
AM		 4150 /* We must avoid matching of Imm32 templates when 64bit
4151 only immediate is available. */
4152 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4153 i.types[op].bitfield.imm32 = 0;
29b0f896 4154 break;
252b5132 4155
29b0f896
AM		 4156 case O_absent:
4157 case O_register:
4158 abort ();
4159
4160 /* Symbols and expressions. */
4161 default:
9cd96992
JB		 4162 /* Convert symbolic operand to proper sizes for matching, but don't
4163 prevent matching a set of insns that only supports sizes other
4164 than those matching the insn suffix. */
4165 {
40fb9820 4166 i386_operand_type mask, allowed;
d3ce72d0 4167 const insn_template *t;
9cd96992 4168
0dfbf9d7
L		 4169 operand_type_set (&mask, 0);
4170 operand_type_set (&allowed, 0);
40fb9820 4171
4eed87de
AM		 4172 for (t = current_templates->start;
4173 t < current_templates->end;
4174 ++t)
c6fb90c8
L		 4175 allowed = operand_type_or (allowed,
4176 t->operand_types[op]);
9cd96992
JB		 4177 switch (guess_suffix)
4178 {
4179 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4180 mask.bitfield.imm64 = 1;
4181 mask.bitfield.imm32s = 1;
9cd96992
JB		 4182 break;
4183 case LONG_MNEM_SUFFIX:
40fb9820 4184 mask.bitfield.imm32 = 1;
9cd96992
JB		 4185 break;
4186 case WORD_MNEM_SUFFIX:
40fb9820 4187 mask.bitfield.imm16 = 1;
9cd96992
JB		 4188 break;
4189 case BYTE_MNEM_SUFFIX:
40fb9820 4190 mask.bitfield.imm8 = 1;
9cd96992
JB		 4191 break;
4192 default:
9cd96992
JB		 4193 break;
4194 }
c6fb90c8 4195 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4196 if (!operand_type_all_zero (&allowed))
c6fb90c8 4197 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4198 }
29b0f896 4199 break;
252b5132 4200 }
29b0f896
AM		 4201 }
4202}
47926f60 4203
29b0f896
AM		 4204/* Try to use the smallest displacement type too. */
4205static void
e3bb37b5 4206optimize_disp (void)
29b0f896
AM		 4207{
4208 int op;
3e73aa7c 4209
29b0f896 4210 for (op = i.operands; --op >= 0;)
40fb9820 4211 if (operand_type_check (i.types[op], disp))
252b5132 4212 {
b300c311 4213 if (i.op[op].disps->X_op == O_constant)
252b5132 4214 {
91d6fa6a 4215 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4216
40fb9820 4217 if (i.types[op].bitfield.disp16
91d6fa6a 4218 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4219 {
4220 /* If this operand is at most 16 bits, convert
4221 to a signed 16 bit number and don't use 64bit
4222 displacement. */
91d6fa6a 4223 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4224 i.types[op].bitfield.disp64 = 0;
b300c311 4225 }
40fb9820 4226 if (i.types[op].bitfield.disp32
91d6fa6a 4227 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4228 {
4229 /* If this operand is at most 32 bits, convert
4230 to a signed 32 bit number and don't use 64bit
4231 displacement. */
91d6fa6a
NC		 4232 op_disp &= (((offsetT) 2 << 31) - 1);
4233 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4234 i.types[op].bitfield.disp64 = 0;
b300c311 4235 }
91d6fa6a 4236 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4237 {
40fb9820
L		 4238 i.types[op].bitfield.disp8 = 0;
4239 i.types[op].bitfield.disp16 = 0;
4240 i.types[op].bitfield.disp32 = 0;
4241 i.types[op].bitfield.disp32s = 0;
4242 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4243 i.op[op].disps = 0;
4244 i.disp_operands--;
4245 }
4246 else if (flag_code == CODE_64BIT)
4247 {
91d6fa6a 4248 if (fits_in_signed_long (op_disp))
28a9d8f5 4249 {
40fb9820
L		 4250 i.types[op].bitfield.disp64 = 0;
4251 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4252 }
0e1147d9 4253 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4254 && fits_in_unsigned_long (op_disp))
40fb9820 4255 i.types[op].bitfield.disp32 = 1;
b300c311 4256 }
40fb9820
L		 4257 if ((i.types[op].bitfield.disp32
4258 || i.types[op].bitfield.disp32s
4259 || i.types[op].bitfield.disp16)
91d6fa6a 4260 && fits_in_signed_byte (op_disp))
40fb9820 4261 i.types[op].bitfield.disp8 = 1;
252b5132 4262 }
67a4f2b7
AO		 4263 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4264 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4265 {
4266 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4267 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4268 i.types[op].bitfield.disp8 = 0;
4269 i.types[op].bitfield.disp16 = 0;
4270 i.types[op].bitfield.disp32 = 0;
4271 i.types[op].bitfield.disp32s = 0;
4272 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4273 }
4274 else
b300c311 4275 /* We only support 64bit displacement on constants. */
40fb9820 4276 i.types[op].bitfield.disp64 = 0;
252b5132 4277 }
29b0f896
AM		 4278}
4279
6c30d220
L		 4280/* Check if operands are valid for the instruction. */
4281
4282static int
4283check_VecOperands (const insn_template *t)
4284{
43234a1e
L		 4285 unsigned int op;
4286
6c30d220
L		 4287 /* Without VSIB byte, we can't have a vector register for index. */
4288 if (!t->opcode_modifier.vecsib
4289 && i.index_reg
4290 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4291 || i.index_reg->reg_type.bitfield.regymm
4292 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4293 {
4294 i.error = unsupported_vector_index_register;
4295 return 1;
4296 }
4297
ad8ecc81
MZ		 4298 /* Check if default mask is allowed. */
4299 if (t->opcode_modifier.nodefmask
4300 && (!i.mask || i.mask->mask->reg_num == 0))
4301 {
4302 i.error = no_default_mask;
4303 return 1;
4304 }
4305
7bab8ab5
JB		 4306 /* For VSIB byte, we need a vector register for index, and all vector
4307 registers must be distinct. */
4308 if (t->opcode_modifier.vecsib)
4309 {
4310 if (!i.index_reg
6c30d220
L		 4311 || !((t->opcode_modifier.vecsib == VecSIB128
4312 && i.index_reg->reg_type.bitfield.regxmm)
4313 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4314 && i.index_reg->reg_type.bitfield.regymm)
4315 || (t->opcode_modifier.vecsib == VecSIB512
4316 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4317 {
4318 i.error = invalid_vsib_address;
4319 return 1;
4320 }
4321
43234a1e
L		 4322 gas_assert (i.reg_operands == 2 || i.mask);
4323 if (i.reg_operands == 2 && !i.mask)
4324 {
4325 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4326 || i.types[0].bitfield.regymm);
43234a1e 4327 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4328 || i.types[2].bitfield.regymm);
43234a1e
L		 4329 if (operand_check == check_none)
4330 return 0;
4331 if (register_number (i.op[0].regs)
4332 != register_number (i.index_reg)
4333 && register_number (i.op[2].regs)
4334 != register_number (i.index_reg)
4335 && register_number (i.op[0].regs)
4336 != register_number (i.op[2].regs))
4337 return 0;
4338 if (operand_check == check_error)
4339 {
4340 i.error = invalid_vector_register_set;
4341 return 1;
4342 }
4343 as_warn (_("mask, index, and destination registers should be distinct"));
4344 }
8444f82a
MZ		 4345 else if (i.reg_operands == 1 && i.mask)
4346 {
4347 if ((i.types[1].bitfield.regymm
4348 || i.types[1].bitfield.regzmm)
4349 && (register_number (i.op[1].regs)
4350 == register_number (i.index_reg)))
4351 {
4352 if (operand_check == check_error)
4353 {
4354 i.error = invalid_vector_register_set;
4355 return 1;
4356 }
4357 if (operand_check != check_none)
4358 as_warn (_("index and destination registers should be distinct"));
4359 }
4360 }
43234a1e 4361 }
7bab8ab5 4362
43234a1e
L		 4363 /* Check if broadcast is supported by the instruction and is applied
4364 to the memory operand. */
4365 if (i.broadcast)
4366 {
4367 int broadcasted_opnd_size;
4368
4369 /* Check if specified broadcast is supported in this instruction,
4370 and it's applied to memory operand of DWORD or QWORD type,
4371 depending on VecESize. */
4372 if (i.broadcast->type != t->opcode_modifier.broadcast
4373 || !i.types[i.broadcast->operand].bitfield.mem
4374 || (t->opcode_modifier.vecesize == 0
4375 && !i.types[i.broadcast->operand].bitfield.dword
4376 && !i.types[i.broadcast->operand].bitfield.unspecified)
4377 || (t->opcode_modifier.vecesize == 1
4378 && !i.types[i.broadcast->operand].bitfield.qword
4379 && !i.types[i.broadcast->operand].bitfield.unspecified))
4380 goto bad_broadcast;
4381
4382 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4383 if (i.broadcast->type == BROADCAST_1TO16)
4384 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4385 else if (i.broadcast->type == BROADCAST_1TO8)
4386 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4387 else if (i.broadcast->type == BROADCAST_1TO4)
4388 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4389 else if (i.broadcast->type == BROADCAST_1TO2)
4390 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4391 else
4392 goto bad_broadcast;
4393
4394 if ((broadcasted_opnd_size == 256
4395 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4396 || (broadcasted_opnd_size == 512
4397 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4398 {
4399 bad_broadcast:
4400 i.error = unsupported_broadcast;
4401 return 1;
4402 }
4403 }
4404 /* If broadcast is supported in this instruction, we need to check if
4405 operand of one-element size isn't specified without broadcast. */
4406 else if (t->opcode_modifier.broadcast && i.mem_operands)
4407 {
4408 /* Find memory operand. */
4409 for (op = 0; op < i.operands; op++)
4410 if (operand_type_check (i.types[op], anymem))
4411 break;
4412 gas_assert (op < i.operands);
4413 /* Check size of the memory operand. */
4414 if ((t->opcode_modifier.vecesize == 0
4415 && i.types[op].bitfield.dword)
4416 || (t->opcode_modifier.vecesize == 1
4417 && i.types[op].bitfield.qword))
4418 {
4419 i.error = broadcast_needed;
4420 return 1;
4421 }
4422 }
4423
4424 /* Check if requested masking is supported. */
4425 if (i.mask
4426 && (!t->opcode_modifier.masking
4427 || (i.mask->zeroing
4428 && t->opcode_modifier.masking == MERGING_MASKING)))
4429 {
4430 i.error = unsupported_masking;
4431 return 1;
4432 }
4433
4434 /* Check if masking is applied to dest operand. */
4435 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4436 {
4437 i.error = mask_not_on_destination;
4438 return 1;
4439 }
4440
43234a1e
L		 4441 /* Check RC/SAE. */
4442 if (i.rounding)
4443 {
4444 if ((i.rounding->type != saeonly
4445 && !t->opcode_modifier.staticrounding)
4446 || (i.rounding->type == saeonly
4447 && (t->opcode_modifier.staticrounding
4448 || !t->opcode_modifier.sae)))
4449 {
4450 i.error = unsupported_rc_sae;
4451 return 1;
4452 }
4453 /* If the instruction has several immediate operands and one of
4454 them is rounding, the rounding operand should be the last
4455 immediate operand. */
4456 if (i.imm_operands > 1
4457 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4458 {
43234a1e 4459 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4460 return 1;
4461 }
6c30d220
L		 4462 }
4463
43234a1e
L		 4464 /* Check vector Disp8 operand. */
4465 if (t->opcode_modifier.disp8memshift)
4466 {
4467 if (i.broadcast)
4468 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4469 else
4470 i.memshift = t->opcode_modifier.disp8memshift;
4471
4472 for (op = 0; op < i.operands; op++)
4473 if (operand_type_check (i.types[op], disp)
4474 && i.op[op].disps->X_op == O_constant)
4475 {
4476 offsetT value = i.op[op].disps->X_add_number;
4477 int vec_disp8_ok = fits_in_vec_disp8 (value);
4478 if (t->operand_types [op].bitfield.vec_disp8)
4479 {
4480 if (vec_disp8_ok)
4481 i.types[op].bitfield.vec_disp8 = 1;
4482 else
4483 {
4484 /* Vector insn can only have Vec_Disp8/Disp32 in
4485 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4486 mode. */
4487 i.types[op].bitfield.disp8 = 0;
4488 if (flag_code != CODE_16BIT)
4489 i.types[op].bitfield.disp16 = 0;
4490 }
4491 }
4492 else if (flag_code != CODE_16BIT)
4493 {
4494 /* One form of this instruction supports vector Disp8.
4495 Try vector Disp8 if we need to use Disp32. */
4496 if (vec_disp8_ok && !fits_in_signed_byte (value))
4497 {
4498 i.error = try_vector_disp8;
4499 return 1;
4500 }
4501 }
4502 }
4503 }
4504 else
4505 i.memshift = -1;
4506
6c30d220
L		 4507 return 0;
4508}
4509
43f3e2ee 4510/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4511 operand types. */
4512
4513static int
4514VEX_check_operands (const insn_template *t)
4515{
43234a1e
L		 4516 /* VREX is only valid with EVEX prefix. */
4517 if (i.need_vrex && !t->opcode_modifier.evex)
4518 {
4519 i.error = invalid_register_operand;
4520 return 1;
4521 }
4522
a683cc34
SP		 4523 if (!t->opcode_modifier.vex)
4524 return 0;
4525
4526 /* Only check VEX_Imm4, which must be the first operand. */
4527 if (t->operand_types[0].bitfield.vec_imm4)
4528 {
4529 if (i.op[0].imms->X_op != O_constant
4530 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4531 {
a65babc9 4532 i.error = bad_imm4;
891edac4
L		 4533 return 1;
4534 }
a683cc34
SP		 4535
4536 /* Turn off Imm8 so that update_imm won't complain. */
4537 i.types[0] = vec_imm4;
4538 }
4539
4540 return 0;
4541}
4542
d3ce72d0 4543static const insn_template *
e3bb37b5 4544match_template (void)
29b0f896
AM		 4545{
4546 /* Points to template once we've found it. */
d3ce72d0 4547 const insn_template *t;
40fb9820 4548 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4549 i386_operand_type overlap4;
29b0f896 4550 unsigned int found_reverse_match;
40fb9820
L		 4551 i386_opcode_modifier suffix_check;
4552 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4553 int addr_prefix_disp;
a5c311ca 4554 unsigned int j;
3629bb00 4555 unsigned int found_cpu_match;
45664ddb 4556 unsigned int check_register;
5614d22c 4557 enum i386_error specific_error = 0;
29b0f896 4558
c0f3af97
L		 4559#if MAX_OPERANDS != 5
4560# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4561#endif
4562
29b0f896 4563 found_reverse_match = 0;
539e75ad 4564 addr_prefix_disp = -1;
40fb9820
L		 4565
4566 memset (&suffix_check, 0, sizeof (suffix_check));
4567 if (i.suffix == BYTE_MNEM_SUFFIX)
4568 suffix_check.no_bsuf = 1;
4569 else if (i.suffix == WORD_MNEM_SUFFIX)
4570 suffix_check.no_wsuf = 1;
4571 else if (i.suffix == SHORT_MNEM_SUFFIX)
4572 suffix_check.no_ssuf = 1;
4573 else if (i.suffix == LONG_MNEM_SUFFIX)
4574 suffix_check.no_lsuf = 1;
4575 else if (i.suffix == QWORD_MNEM_SUFFIX)
4576 suffix_check.no_qsuf = 1;
4577 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4578 suffix_check.no_ldsuf = 1;
29b0f896 4579
01559ecc
L		 4580 /* Must have right number of operands. */
4581 i.error = number_of_operands_mismatch;
4582
45aa61fe 4583 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4584 {
539e75ad
L		 4585 addr_prefix_disp = -1;
4586
29b0f896
AM		 4587 if (i.operands != t->operands)
4588 continue;
4589
50aecf8c 4590 /* Check processor support. */
a65babc9 4591 i.error = unsupported;
c0f3af97
L		 4592 found_cpu_match = (cpu_flags_match (t)
4593 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4594 if (!found_cpu_match)
4595 continue;
4596
e1d4d893 4597 /* Check old gcc support. */
a65babc9 4598 i.error = old_gcc_only;
e1d4d893
L		 4599 if (!old_gcc && t->opcode_modifier.oldgcc)
4600 continue;
4601
4602 /* Check AT&T mnemonic. */
a65babc9 4603 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4604 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4605 continue;
4606
891edac4 4607 /* Check AT&T/Intel syntax. */
a65babc9 4608 i.error = unsupported_syntax;
5c07affc
L		 4609 if ((intel_syntax && t->opcode_modifier.attsyntax)
4610 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4611 continue;
4612
20592a94 4613 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4614 i.error = invalid_instruction_suffix;
567e4e96
L		 4615 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4616 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4617 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4618 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4619 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4620 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4621 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4622 continue;
4623
5c07affc 4624 if (!operand_size_match (t))
7d5e4556 4625 continue;
539e75ad 4626
5c07affc
L		 4627 for (j = 0; j < MAX_OPERANDS; j++)
4628 operand_types[j] = t->operand_types[j];
4629
45aa61fe
AM		 4630 /* In general, don't allow 64-bit operands in 32-bit mode. */
4631 if (i.suffix == QWORD_MNEM_SUFFIX
4632 && flag_code != CODE_64BIT
4633 && (intel_syntax
40fb9820 4634 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4635 && !intel_float_operand (t->name))
4636 : intel_float_operand (t->name) != 2)
40fb9820 4637 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4638 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4639 && !operand_types[0].bitfield.regymm
4640 && !operand_types[0].bitfield.regzmm)
40fb9820 4641 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4642 && operand_types[t->operands > 1].bitfield.regxmm
4643 && operand_types[t->operands > 1].bitfield.regymm
4644 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4645 && (t->base_opcode != 0x0fc7
4646 || t->extension_opcode != 1 /* cmpxchg8b */))
4647 continue;
4648
192dc9c6
JB		 4649 /* In general, don't allow 32-bit operands on pre-386. */
4650 else if (i.suffix == LONG_MNEM_SUFFIX
4651 && !cpu_arch_flags.bitfield.cpui386
4652 && (intel_syntax
4653 ? (!t->opcode_modifier.ignoresize
4654 && !intel_float_operand (t->name))
4655 : intel_float_operand (t->name) != 2)
4656 && ((!operand_types[0].bitfield.regmmx
4657 && !operand_types[0].bitfield.regxmm)
4658 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 4659 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 4660 continue;
4661
29b0f896 4662 /* Do not verify operands when there are none. */
50aecf8c 4663 else
29b0f896 4664 {
c6fb90c8 4665 if (!t->operands)
2dbab7d5
L		 4666 /* We've found a match; break out of loop. */
4667 break;
29b0f896 4668 }
252b5132 4669
539e75ad
L		 4670 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4671 into Disp32/Disp16/Disp32 operand. */
4672 if (i.prefix[ADDR_PREFIX] != 0)
4673 {
40fb9820 4674 /* There should be only one Disp operand. */
539e75ad
L		 4675 switch (flag_code)
4676 {
4677 case CODE_16BIT:
40fb9820
L		 4678 for (j = 0; j < MAX_OPERANDS; j++)
4679 {
4680 if (operand_types[j].bitfield.disp16)
4681 {
4682 addr_prefix_disp = j;
4683 operand_types[j].bitfield.disp32 = 1;
4684 operand_types[j].bitfield.disp16 = 0;
4685 break;
4686 }
4687 }
539e75ad
L		 4688 break;
4689 case CODE_32BIT:
40fb9820
L		 4690 for (j = 0; j < MAX_OPERANDS; j++)
4691 {
4692 if (operand_types[j].bitfield.disp32)
4693 {
4694 addr_prefix_disp = j;
4695 operand_types[j].bitfield.disp32 = 0;
4696 operand_types[j].bitfield.disp16 = 1;
4697 break;
4698 }
4699 }
539e75ad
L		 4700 break;
4701 case CODE_64BIT:
40fb9820
L		 4702 for (j = 0; j < MAX_OPERANDS; j++)
4703 {
4704 if (operand_types[j].bitfield.disp64)
4705 {
4706 addr_prefix_disp = j;
4707 operand_types[j].bitfield.disp64 = 0;
4708 operand_types[j].bitfield.disp32 = 1;
4709 break;
4710 }
4711 }
539e75ad
L		 4712 break;
4713 }
539e75ad
L		 4714 }
4715
56ffb741
L		 4716 /* We check register size if needed. */
4717 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4718 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4719 switch (t->operands)
4720 {
4721 case 1:
40fb9820 4722 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4723 continue;
4724 break;
4725 case 2:
8b38ad71
L		 4726 /* xchg %eax, %eax is a special case. It is an aliase for nop
4727 only in 32bit mode and we can use opcode 0x90. In 64bit
4728 mode, we can't use 0x90 for xchg %eax, %eax since it should
4729 zero-extend %eax to %rax. */
4730 if (flag_code == CODE_64BIT
4731 && t->base_opcode == 0x90
0dfbf9d7
L		 4732 && operand_type_equal (&i.types [0], &acc32)
4733 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4734 continue;
b6169b20
L		 4735 if (i.swap_operand)
4736 {
4737 /* If we swap operand in encoding, we either match
4738 the next one or reverse direction of operands. */
4739 if (t->opcode_modifier.s)
4740 continue;
4741 else if (t->opcode_modifier.d)
4742 goto check_reverse;
4743 }
4744
29b0f896 4745 case 3:
fa99fab2
L		 4746 /* If we swap operand in encoding, we match the next one. */
4747 if (i.swap_operand && t->opcode_modifier.s)
4748 continue;
f48ff2ae 4749 case 4:
c0f3af97 4750 case 5:
c6fb90c8 4751 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4752 if (!operand_type_match (overlap0, i.types[0])
4753 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4754 || (check_register
4755 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4756 operand_types[0],
4757 overlap1, i.types[1],
4758 operand_types[1])))
29b0f896
AM		 4759 {
4760 /* Check if other direction is valid ... */
40fb9820 4761 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4762 continue;
4763
b6169b20 4764check_reverse:
29b0f896 4765 /* Try reversing direction of operands. */
c6fb90c8
L		 4766 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4767 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4768 if (!operand_type_match (overlap0, i.types[0])
4769 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4770 || (check_register
4771 && !operand_type_register_match (overlap0,
4772 i.types[0],
4773 operand_types[1],
4774 overlap1,
4775 i.types[1],
4776 operand_types[0])))
29b0f896
AM		 4777 {
4778 /* Does not match either direction. */
4779 continue;
4780 }
4781 /* found_reverse_match holds which of D or FloatDR
4782 we've found. */
40fb9820 4783 if (t->opcode_modifier.d)
8a2ed489 4784 found_reverse_match = Opcode_D;
40fb9820 4785 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4786 found_reverse_match = Opcode_FloatD;
4787 else
4788 found_reverse_match = 0;
40fb9820 4789 if (t->opcode_modifier.floatr)
8a2ed489 4790 found_reverse_match |= Opcode_FloatR;
29b0f896 4791 }
f48ff2ae 4792 else
29b0f896 4793 {
f48ff2ae 4794 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4795 switch (t->operands)
4796 {
c0f3af97
L		 4797 case 5:
4798 overlap4 = operand_type_and (i.types[4],
4799 operand_types[4]);
d1cbb4db 4800 case 4:
c6fb90c8
L		 4801 overlap3 = operand_type_and (i.types[3],
4802 operand_types[3]);
d1cbb4db 4803 case 3:
c6fb90c8
L		 4804 overlap2 = operand_type_and (i.types[2],
4805 operand_types[2]);
d1cbb4db
L		 4806 break;
4807 }
29b0f896 4808
f48ff2ae
L		 4809 switch (t->operands)
4810 {
c0f3af97
L		 4811 case 5:
4812 if (!operand_type_match (overlap4, i.types[4])
4813 || !operand_type_register_match (overlap3,
4814 i.types[3],
4815 operand_types[3],
4816 overlap4,
4817 i.types[4],
4818 operand_types[4]))
4819 continue;
f48ff2ae 4820 case 4:
40fb9820 4821 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4822 || (check_register
4823 && !operand_type_register_match (overlap2,
4824 i.types[2],
4825 operand_types[2],
4826 overlap3,
4827 i.types[3],
4828 operand_types[3])))
f48ff2ae
L		 4829 continue;
4830 case 3:
4831 /* Here we make use of the fact that there are no
4832 reverse match 3 operand instructions, and all 3
4833 operand instructions only need to be checked for
4834 register consistency between operands 2 and 3. */
40fb9820 4835 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4836 || (check_register
4837 && !operand_type_register_match (overlap1,
4838 i.types[1],
4839 operand_types[1],
4840 overlap2,
4841 i.types[2],
4842 operand_types[2])))
f48ff2ae
L		 4843 continue;
4844 break;
4845 }
29b0f896 4846 }
f48ff2ae 4847 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4848 slip through to break. */
4849 }
3629bb00 4850 if (!found_cpu_match)
29b0f896
AM		 4851 {
4852 found_reverse_match = 0;
4853 continue;
4854 }
c0f3af97 4855
5614d22c
JB		 4856 /* Check if vector and VEX operands are valid. */
4857 if (check_VecOperands (t) || VEX_check_operands (t))
4858 {
4859 specific_error = i.error;
4860 continue;
4861 }
a683cc34 4862
29b0f896
AM		 4863 /* We've found a match; break out of loop. */
4864 break;
4865 }
4866
4867 if (t == current_templates->end)
4868 {
4869 /* We found no match. */
a65babc9 4870 const char *err_msg;
5614d22c 4871 switch (specific_error ? specific_error : i.error)
a65babc9
L		 4872 {
4873 default:
4874 abort ();
86e026a4 4875 case operand_size_mismatch:
a65babc9
L		 4876 err_msg = _("operand size mismatch");
4877 break;
4878 case operand_type_mismatch:
4879 err_msg = _("operand type mismatch");
4880 break;
4881 case register_type_mismatch:
4882 err_msg = _("register type mismatch");
4883 break;
4884 case number_of_operands_mismatch:
4885 err_msg = _("number of operands mismatch");
4886 break;
4887 case invalid_instruction_suffix:
4888 err_msg = _("invalid instruction suffix");
4889 break;
4890 case bad_imm4:
4a2608e3 4891 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 4892 break;
4893 case old_gcc_only:
4894 err_msg = _("only supported with old gcc");
4895 break;
4896 case unsupported_with_intel_mnemonic:
4897 err_msg = _("unsupported with Intel mnemonic");
4898 break;
4899 case unsupported_syntax:
4900 err_msg = _("unsupported syntax");
4901 break;
4902 case unsupported:
35262a23 4903 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 4904 current_templates->start->name);
4905 return NULL;
6c30d220
L		 4906 case invalid_vsib_address:
4907 err_msg = _("invalid VSIB address");
4908 break;
7bab8ab5
JB		 4909 case invalid_vector_register_set:
4910 err_msg = _("mask, index, and destination registers must be distinct");
4911 break;
6c30d220
L		 4912 case unsupported_vector_index_register:
4913 err_msg = _("unsupported vector index register");
4914 break;
43234a1e
L		 4915 case unsupported_broadcast:
4916 err_msg = _("unsupported broadcast");
4917 break;
4918 case broadcast_not_on_src_operand:
4919 err_msg = _("broadcast not on source memory operand");
4920 break;
4921 case broadcast_needed:
4922 err_msg = _("broadcast is needed for operand of such type");
4923 break;
4924 case unsupported_masking:
4925 err_msg = _("unsupported masking");
4926 break;
4927 case mask_not_on_destination:
4928 err_msg = _("mask not on destination operand");
4929 break;
4930 case no_default_mask:
4931 err_msg = _("default mask isn't allowed");
4932 break;
4933 case unsupported_rc_sae:
4934 err_msg = _("unsupported static rounding/sae");
4935 break;
4936 case rc_sae_operand_not_last_imm:
4937 if (intel_syntax)
4938 err_msg = _("RC/SAE operand must precede immediate operands");
4939 else
4940 err_msg = _("RC/SAE operand must follow immediate operands");
4941 break;
4942 case invalid_register_operand:
4943 err_msg = _("invalid register operand");
4944 break;
a65babc9
L		 4945 }
4946 as_bad (_("%s for `%s'"), err_msg,
891edac4 4947 current_templates->start->name);
fa99fab2 4948 return NULL;
29b0f896 4949 }
252b5132 4950
29b0f896
AM		 4951 if (!quiet_warnings)
4952 {
4953 if (!intel_syntax
40fb9820
L		 4954 && (i.types[0].bitfield.jumpabsolute
4955 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 4956 {
4957 as_warn (_("indirect %s without `*'"), t->name);
4958 }
4959
40fb9820
L		 4960 if (t->opcode_modifier.isprefix
4961 && t->opcode_modifier.ignoresize)
29b0f896
AM		 4962 {
4963 /* Warn them that a data or address size prefix doesn't
4964 affect assembly of the next line of code. */
4965 as_warn (_("stand-alone `%s' prefix"), t->name);
4966 }
4967 }
4968
4969 /* Copy the template we found. */
4970 i.tm = *t;
539e75ad
L		 4971
4972 if (addr_prefix_disp != -1)
4973 i.tm.operand_types[addr_prefix_disp]
4974 = operand_types[addr_prefix_disp];
4975
29b0f896
AM		 4976 if (found_reverse_match)
4977 {
4978 /* If we found a reverse match we must alter the opcode
4979 direction bit. found_reverse_match holds bits to change
4980 (different for int & float insns). */
4981
4982 i.tm.base_opcode ^= found_reverse_match;
4983
539e75ad
L		 4984 i.tm.operand_types[0] = operand_types[1];
4985 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 4986 }
4987
fa99fab2 4988 return t;
29b0f896
AM		 4989}
4990
4991static int
e3bb37b5 4992check_string (void)
29b0f896 4993{
40fb9820
L		 4994 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4995 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 4996 {
4997 if (i.seg[0] != NULL && i.seg[0] != &es)
4998 {
a87af027 4999 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5000 i.tm.name,
a87af027
JB		 5001 mem_op + 1,
5002 register_prefix);
29b0f896
AM		 5003 return 0;
5004 }
5005 /* There's only ever one segment override allowed per instruction.
5006 This instruction possibly has a legal segment override on the
5007 second operand, so copy the segment to where non-string
5008 instructions store it, allowing common code. */
5009 i.seg[0] = i.seg[1];
5010 }
40fb9820 5011 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5012 {
5013 if (i.seg[1] != NULL && i.seg[1] != &es)
5014 {
a87af027 5015 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5016 i.tm.name,
a87af027
JB		 5017 mem_op + 2,
5018 register_prefix);
29b0f896
AM		 5019 return 0;
5020 }
5021 }
5022 return 1;
5023}
5024
5025static int
543613e9 5026process_suffix (void)
29b0f896
AM		 5027{
5028 /* If matched instruction specifies an explicit instruction mnemonic
5029 suffix, use it. */
40fb9820
L		 5030 if (i.tm.opcode_modifier.size16)
5031 i.suffix = WORD_MNEM_SUFFIX;
5032 else if (i.tm.opcode_modifier.size32)
5033 i.suffix = LONG_MNEM_SUFFIX;
5034 else if (i.tm.opcode_modifier.size64)
5035 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5036 else if (i.reg_operands)
5037 {
5038 /* If there's no instruction mnemonic suffix we try to invent one
5039 based on register operands. */
5040 if (!i.suffix)
5041 {
5042 /* We take i.suffix from the last register operand specified,
5043 Destination register type is more significant than source
381d071f
L		 5044 register type. crc32 in SSE4.2 prefers source register
5045 type. */
5046 if (i.tm.base_opcode == 0xf20f38f1)
5047 {
40fb9820
L		 5048 if (i.types[0].bitfield.reg16)
5049 i.suffix = WORD_MNEM_SUFFIX;
5050 else if (i.types[0].bitfield.reg32)
5051 i.suffix = LONG_MNEM_SUFFIX;
5052 else if (i.types[0].bitfield.reg64)
5053 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5054 }
9344ff29 5055 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5056 {
40fb9820 5057 if (i.types[0].bitfield.reg8)
20592a94
L		 5058 i.suffix = BYTE_MNEM_SUFFIX;
5059 }
381d071f
L		 5060
5061 if (!i.suffix)
5062 {
5063 int op;
5064
20592a94
L		 5065 if (i.tm.base_opcode == 0xf20f38f1
5066 || i.tm.base_opcode == 0xf20f38f0)
5067 {
5068 /* We have to know the operand size for crc32. */
5069 as_bad (_("ambiguous memory operand size for `%s`"),
5070 i.tm.name);
5071 return 0;
5072 }
5073
381d071f 5074 for (op = i.operands; --op >= 0;)
40fb9820 5075 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5076 {
40fb9820
L		 5077 if (i.types[op].bitfield.reg8)
5078 {
5079 i.suffix = BYTE_MNEM_SUFFIX;
5080 break;
5081 }
5082 else if (i.types[op].bitfield.reg16)
5083 {
5084 i.suffix = WORD_MNEM_SUFFIX;
5085 break;
5086 }
5087 else if (i.types[op].bitfield.reg32)
5088 {
5089 i.suffix = LONG_MNEM_SUFFIX;
5090 break;
5091 }
5092 else if (i.types[op].bitfield.reg64)
5093 {
5094 i.suffix = QWORD_MNEM_SUFFIX;
5095 break;
5096 }
381d071f
L		 5097 }
5098 }
29b0f896
AM		 5099 }
5100 else if (i.suffix == BYTE_MNEM_SUFFIX)
5101 {
2eb952a4
L		 5102 if (intel_syntax
5103 && i.tm.opcode_modifier.ignoresize
5104 && i.tm.opcode_modifier.no_bsuf)
5105 i.suffix = 0;
5106 else if (!check_byte_reg ())
29b0f896
AM		 5107 return 0;
5108 }
5109 else if (i.suffix == LONG_MNEM_SUFFIX)
5110 {
2eb952a4
L		 5111 if (intel_syntax
5112 && i.tm.opcode_modifier.ignoresize
5113 && i.tm.opcode_modifier.no_lsuf)
5114 i.suffix = 0;
5115 else if (!check_long_reg ())
29b0f896
AM		 5116 return 0;
5117 }
5118 else if (i.suffix == QWORD_MNEM_SUFFIX)
5119 {
955e1e6a
L		 5120 if (intel_syntax
5121 && i.tm.opcode_modifier.ignoresize
5122 && i.tm.opcode_modifier.no_qsuf)
5123 i.suffix = 0;
5124 else if (!check_qword_reg ())
29b0f896
AM		 5125 return 0;
5126 }
5127 else if (i.suffix == WORD_MNEM_SUFFIX)
5128 {
2eb952a4
L		 5129 if (intel_syntax
5130 && i.tm.opcode_modifier.ignoresize
5131 && i.tm.opcode_modifier.no_wsuf)
5132 i.suffix = 0;
5133 else if (!check_word_reg ())
29b0f896
AM		 5134 return 0;
5135 }
c0f3af97 5136 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5137 || i.suffix == YMMWORD_MNEM_SUFFIX
5138 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5139 {
43234a1e 5140 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5141 should check if it is a valid suffix. */
5142 }
40fb9820 5143 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5144 /* Do nothing if the instruction is going to ignore the prefix. */
5145 ;
5146 else
5147 abort ();
5148 }
40fb9820 5149 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5150 && !i.suffix
5151 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5152 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5153 {
5154 i.suffix = stackop_size;
5155 }
9306ca4a
JB		 5156 else if (intel_syntax
5157 && !i.suffix
40fb9820
L		 5158 && (i.tm.operand_types[0].bitfield.jumpabsolute
5159 || i.tm.opcode_modifier.jumpbyte
5160 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5161 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5162 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5163 {
5164 switch (flag_code)
5165 {
5166 case CODE_64BIT:
40fb9820 5167 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5168 {
5169 i.suffix = QWORD_MNEM_SUFFIX;
5170 break;
5171 }
5172 case CODE_32BIT:
40fb9820 5173 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5174 i.suffix = LONG_MNEM_SUFFIX;
5175 break;
5176 case CODE_16BIT:
40fb9820 5177 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5178 i.suffix = WORD_MNEM_SUFFIX;
5179 break;
5180 }
5181 }
252b5132 5182
9306ca4a 5183 if (!i.suffix)
29b0f896 5184 {
9306ca4a
JB		 5185 if (!intel_syntax)
5186 {
40fb9820 5187 if (i.tm.opcode_modifier.w)
9306ca4a 5188 {
4eed87de
AM		 5189 as_bad (_("no instruction mnemonic suffix given and "
5190 "no register operands; can't size instruction"));
9306ca4a
JB		 5191 return 0;
5192 }
5193 }
5194 else
5195 {
40fb9820 5196 unsigned int suffixes;
7ab9ffdd 5197
40fb9820
L		 5198 suffixes = !i.tm.opcode_modifier.no_bsuf;
5199 if (!i.tm.opcode_modifier.no_wsuf)
5200 suffixes |= 1 << 1;
5201 if (!i.tm.opcode_modifier.no_lsuf)
5202 suffixes |= 1 << 2;
fc4adea1 5203 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5204 suffixes |= 1 << 3;
5205 if (!i.tm.opcode_modifier.no_ssuf)
5206 suffixes |= 1 << 4;
5207 if (!i.tm.opcode_modifier.no_qsuf)
5208 suffixes |= 1 << 5;
5209
5210 /* There are more than suffix matches. */
5211 if (i.tm.opcode_modifier.w
9306ca4a 5212 || ((suffixes & (suffixes - 1))
40fb9820
L		 5213 && !i.tm.opcode_modifier.defaultsize
5214 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5215 {
5216 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5217 return 0;
5218 }
5219 }
29b0f896 5220 }
252b5132 5221
9306ca4a
JB		 5222 /* Change the opcode based on the operand size given by i.suffix;
5223 We don't need to change things for byte insns. */
5224
582d5edd
L		 5225 if (i.suffix
5226 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5227 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5228 && i.suffix != YMMWORD_MNEM_SUFFIX
5229 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5230 {
5231 /* It's not a byte, select word/dword operation. */
40fb9820 5232 if (i.tm.opcode_modifier.w)
29b0f896 5233 {
40fb9820 5234 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5235 i.tm.base_opcode |= 8;
5236 else
5237 i.tm.base_opcode |= 1;
5238 }
0f3f3d8b 5239
29b0f896
AM		 5240 /* Now select between word & dword operations via the operand
5241 size prefix, except for instructions that will ignore this
5242 prefix anyway. */
ca61edf2 5243 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5244 {
ca61edf2
L		 5245 /* The address size override prefix changes the size of the
5246 first operand. */
40fb9820
L		 5247 if ((flag_code == CODE_32BIT
5248 && i.op->regs[0].reg_type.bitfield.reg16)
5249 || (flag_code != CODE_32BIT
5250 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5251 if (!add_prefix (ADDR_PREFIX_OPCODE))
5252 return 0;
5253 }
5254 else if (i.suffix != QWORD_MNEM_SUFFIX
5255 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5256 && !i.tm.opcode_modifier.ignoresize
5257 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5258 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5259 || (flag_code == CODE_64BIT
40fb9820 5260 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5261 {
5262 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5263
40fb9820 5264 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5265 prefix = ADDR_PREFIX_OPCODE;
252b5132 5266
29b0f896
AM		 5267 if (!add_prefix (prefix))
5268 return 0;
24eab124 5269 }
252b5132 5270
29b0f896
AM		 5271 /* Set mode64 for an operand. */
5272 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5273 && flag_code == CODE_64BIT
40fb9820 5274 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5275 {
5276 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5277 need rex64. cmpxchg8b is also a special case. */
5278 if (! (i.operands == 2
5279 && i.tm.base_opcode == 0x90
5280 && i.tm.extension_opcode == None
0dfbf9d7
L		 5281 && operand_type_equal (&i.types [0], &acc64)
5282 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5283 && ! (i.operands == 1
5284 && i.tm.base_opcode == 0xfc7
5285 && i.tm.extension_opcode == 1
40fb9820
L		 5286 && !operand_type_check (i.types [0], reg)
5287 && operand_type_check (i.types [0], anymem)))
f6bee062 5288 i.rex |= REX_W;
46e883c5 5289 }
3e73aa7c 5290
29b0f896
AM		 5291 /* Size floating point instruction. */
5292 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5293 if (i.tm.opcode_modifier.floatmf)
543613e9 5294 i.tm.base_opcode ^= 4;
29b0f896 5295 }
7ecd2f8b 5296
29b0f896
AM		 5297 return 1;
5298}
3e73aa7c 5299
29b0f896 5300static int
543613e9 5301check_byte_reg (void)
29b0f896
AM		 5302{
5303 int op;
543613e9 5304
29b0f896
AM		 5305 for (op = i.operands; --op >= 0;)
5306 {
5307 /* If this is an eight bit register, it's OK. If it's the 16 or
5308 32 bit version of an eight bit register, we will just use the
5309 low portion, and that's OK too. */
40fb9820 5310 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5311 continue;
5312
5a819eb9
JB		 5313 /* I/O port address operands are OK too. */
5314 if (i.tm.operand_types[op].bitfield.inoutportreg)
5315 continue;
5316
9344ff29
L		 5317 /* crc32 doesn't generate this warning. */
5318 if (i.tm.base_opcode == 0xf20f38f0)
5319 continue;
5320
40fb9820
L		 5321 if ((i.types[op].bitfield.reg16
5322 || i.types[op].bitfield.reg32
5323 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5324 && i.op[op].regs->reg_num < 4
5325 /* Prohibit these changes in 64bit mode, since the lowering
5326 would be more complicated. */
5327 && flag_code != CODE_64BIT)
29b0f896 5328 {
29b0f896 5329#if REGISTER_WARNINGS
5a819eb9 5330 if (!quiet_warnings)
a540244d
L		 5331 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5332 register_prefix,
40fb9820 5333 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5334 ? REGNAM_AL - REGNAM_AX
5335 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5336 register_prefix,
29b0f896
AM		 5337 i.op[op].regs->reg_name,
5338 i.suffix);
5339#endif
5340 continue;
5341 }
5342 /* Any other register is bad. */
40fb9820
L		 5343 if (i.types[op].bitfield.reg16
5344 || i.types[op].bitfield.reg32
5345 || i.types[op].bitfield.reg64
5346 || i.types[op].bitfield.regmmx
5347 || i.types[op].bitfield.regxmm
c0f3af97 5348 || i.types[op].bitfield.regymm
43234a1e 5349 || i.types[op].bitfield.regzmm
40fb9820
L		 5350 || i.types[op].bitfield.sreg2
5351 || i.types[op].bitfield.sreg3
5352 || i.types[op].bitfield.control
5353 || i.types[op].bitfield.debug
5354 || i.types[op].bitfield.test
5355 || i.types[op].bitfield.floatreg
5356 || i.types[op].bitfield.floatacc)
29b0f896 5357 {
a540244d
L		 5358 as_bad (_("`%s%s' not allowed with `%s%c'"),
5359 register_prefix,
29b0f896
AM		 5360 i.op[op].regs->reg_name,
5361 i.tm.name,
5362 i.suffix);
5363 return 0;
5364 }
5365 }
5366 return 1;
5367}
5368
5369static int
e3bb37b5 5370check_long_reg (void)
29b0f896
AM		 5371{
5372 int op;
5373
5374 for (op = i.operands; --op >= 0;)
5375 /* Reject eight bit registers, except where the template requires
5376 them. (eg. movzb) */
40fb9820
L		 5377 if (i.types[op].bitfield.reg8
5378 && (i.tm.operand_types[op].bitfield.reg16
5379 || i.tm.operand_types[op].bitfield.reg32
5380 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5381 {
a540244d
L		 5382 as_bad (_("`%s%s' not allowed with `%s%c'"),
5383 register_prefix,
29b0f896
AM		 5384 i.op[op].regs->reg_name,
5385 i.tm.name,
5386 i.suffix);
5387 return 0;
5388 }
e4630f71 5389 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5390 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5391 && i.types[op].bitfield.reg16
5392 && (i.tm.operand_types[op].bitfield.reg32
5393 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5394 {
5395 /* Prohibit these changes in the 64bit mode, since the
5396 lowering is more complicated. */
5397 if (flag_code == CODE_64BIT)
252b5132 5398 {
2b5d6a91 5399 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5400 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5401 i.suffix);
5402 return 0;
252b5132 5403 }
29b0f896 5404#if REGISTER_WARNINGS
cecf1424
JB		 5405 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5406 register_prefix,
5407 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5408 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5409#endif
252b5132 5410 }
e4630f71 5411 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5412 else if (i.types[op].bitfield.reg64
5413 && (i.tm.operand_types[op].bitfield.reg32
5414 || i.tm.operand_types[op].bitfield.acc))
252b5132 5415 {
34828aad 5416 if (intel_syntax
ca61edf2 5417 && i.tm.opcode_modifier.toqword
40fb9820 5418 && !i.types[0].bitfield.regxmm)
34828aad 5419 {
ca61edf2 5420 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5421 i.suffix = QWORD_MNEM_SUFFIX;
5422 }
5423 else
5424 {
2b5d6a91 5425 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5426 register_prefix, i.op[op].regs->reg_name,
5427 i.suffix);
5428 return 0;
5429 }
29b0f896
AM		 5430 }
5431 return 1;
5432}
252b5132 5433
29b0f896 5434static int
e3bb37b5 5435check_qword_reg (void)
29b0f896
AM		 5436{
5437 int op;
252b5132 5438
29b0f896
AM		 5439 for (op = i.operands; --op >= 0; )
5440 /* Reject eight bit registers, except where the template requires
5441 them. (eg. movzb) */
40fb9820
L		 5442 if (i.types[op].bitfield.reg8
5443 && (i.tm.operand_types[op].bitfield.reg16
5444 || i.tm.operand_types[op].bitfield.reg32
5445 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5446 {
a540244d
L		 5447 as_bad (_("`%s%s' not allowed with `%s%c'"),
5448 register_prefix,
29b0f896
AM		 5449 i.op[op].regs->reg_name,
5450 i.tm.name,
5451 i.suffix);
5452 return 0;
5453 }
e4630f71 5454 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5455 else if ((i.types[op].bitfield.reg16
5456 || i.types[op].bitfield.reg32)
5457 && (i.tm.operand_types[op].bitfield.reg32
5458 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5459 {
5460 /* Prohibit these changes in the 64bit mode, since the
5461 lowering is more complicated. */
34828aad 5462 if (intel_syntax
ca61edf2 5463 && i.tm.opcode_modifier.todword
40fb9820 5464 && !i.types[0].bitfield.regxmm)
34828aad 5465 {
ca61edf2 5466 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5467 i.suffix = LONG_MNEM_SUFFIX;
5468 }
5469 else
5470 {
2b5d6a91 5471 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5472 register_prefix, i.op[op].regs->reg_name,
5473 i.suffix);
5474 return 0;
5475 }
252b5132 5476 }
29b0f896
AM		 5477 return 1;
5478}
252b5132 5479
29b0f896 5480static int
e3bb37b5 5481check_word_reg (void)
29b0f896
AM		 5482{
5483 int op;
5484 for (op = i.operands; --op >= 0;)
5485 /* Reject eight bit registers, except where the template requires
5486 them. (eg. movzb) */
40fb9820
L		 5487 if (i.types[op].bitfield.reg8
5488 && (i.tm.operand_types[op].bitfield.reg16
5489 || i.tm.operand_types[op].bitfield.reg32
5490 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5491 {
a540244d
L		 5492 as_bad (_("`%s%s' not allowed with `%s%c'"),
5493 register_prefix,
29b0f896
AM		 5494 i.op[op].regs->reg_name,
5495 i.tm.name,
5496 i.suffix);
5497 return 0;
5498 }
e4630f71 5499 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5500 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5501 && (i.types[op].bitfield.reg32
5502 || i.types[op].bitfield.reg64)
40fb9820
L		 5503 && (i.tm.operand_types[op].bitfield.reg16
5504 || i.tm.operand_types[op].bitfield.acc))
252b5132 5505 {
29b0f896
AM		 5506 /* Prohibit these changes in the 64bit mode, since the
5507 lowering is more complicated. */
5508 if (flag_code == CODE_64BIT)
252b5132 5509 {
2b5d6a91 5510 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5511 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5512 i.suffix);
5513 return 0;
252b5132 5514 }
29b0f896 5515#if REGISTER_WARNINGS
cecf1424
JB		 5516 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5517 register_prefix,
5518 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5519 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5520#endif
5521 }
5522 return 1;
5523}
252b5132 5524
29b0f896 5525static int
40fb9820 5526update_imm (unsigned int j)
29b0f896 5527{
bc0844ae 5528 i386_operand_type overlap = i.types[j];
40fb9820
L		 5529 if ((overlap.bitfield.imm8
5530 || overlap.bitfield.imm8s
5531 || overlap.bitfield.imm16
5532 || overlap.bitfield.imm32
5533 || overlap.bitfield.imm32s
5534 || overlap.bitfield.imm64)
0dfbf9d7
L		 5535 && !operand_type_equal (&overlap, &imm8)
5536 && !operand_type_equal (&overlap, &imm8s)
5537 && !operand_type_equal (&overlap, &imm16)
5538 && !operand_type_equal (&overlap, &imm32)
5539 && !operand_type_equal (&overlap, &imm32s)
5540 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5541 {
5542 if (i.suffix)
5543 {
40fb9820
L		 5544 i386_operand_type temp;
5545
0dfbf9d7 5546 operand_type_set (&temp, 0);
7ab9ffdd 5547 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5548 {
5549 temp.bitfield.imm8 = overlap.bitfield.imm8;
5550 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5551 }
5552 else if (i.suffix == WORD_MNEM_SUFFIX)
5553 temp.bitfield.imm16 = overlap.bitfield.imm16;
5554 else if (i.suffix == QWORD_MNEM_SUFFIX)
5555 {
5556 temp.bitfield.imm64 = overlap.bitfield.imm64;
5557 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5558 }
5559 else
5560 temp.bitfield.imm32 = overlap.bitfield.imm32;
5561 overlap = temp;
29b0f896 5562 }
0dfbf9d7
L		 5563 else if (operand_type_equal (&overlap, &imm16_32_32s)
5564 || operand_type_equal (&overlap, &imm16_32)
5565 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5566 {
40fb9820 5567 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5568 overlap = imm16;
40fb9820 5569 else
65da13b5 5570 overlap = imm32s;
29b0f896 5571 }
0dfbf9d7
L		 5572 if (!operand_type_equal (&overlap, &imm8)
5573 && !operand_type_equal (&overlap, &imm8s)
5574 && !operand_type_equal (&overlap, &imm16)
5575 && !operand_type_equal (&overlap, &imm32)
5576 && !operand_type_equal (&overlap, &imm32s)
5577 && !operand_type_equal (&overlap, &imm64))
29b0f896 5578 {
4eed87de
AM		 5579 as_bad (_("no instruction mnemonic suffix given; "
5580 "can't determine immediate size"));
29b0f896
AM		 5581 return 0;
5582 }
5583 }
40fb9820 5584 i.types[j] = overlap;
29b0f896 5585
40fb9820
L		 5586 return 1;
5587}
5588
5589static int
5590finalize_imm (void)
5591{
bc0844ae 5592 unsigned int j, n;
29b0f896 5593
bc0844ae
L		 5594 /* Update the first 2 immediate operands. */
5595 n = i.operands > 2 ? 2 : i.operands;
5596 if (n)
5597 {
5598 for (j = 0; j < n; j++)
5599 if (update_imm (j) == 0)
5600 return 0;
40fb9820 5601
bc0844ae
L		 5602 /* The 3rd operand can't be immediate operand. */
5603 gas_assert (operand_type_check (i.types[2], imm) == 0);
5604 }
29b0f896
AM		 5605
5606 return 1;
5607}
5608
c0f3af97
L		 5609static int
5610bad_implicit_operand (int xmm)
5611{
91d6fa6a
NC		 5612 const char *ireg = xmm ? "xmm0" : "ymm0";
5613
c0f3af97
L		 5614 if (intel_syntax)
5615 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5616 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5617 else
5618 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5619 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5620 return 0;
5621}
5622
29b0f896 5623static int
e3bb37b5 5624process_operands (void)
29b0f896
AM		 5625{
5626 /* Default segment register this instruction will use for memory
5627 accesses. 0 means unknown. This is only for optimizing out
5628 unnecessary segment overrides. */
5629 const seg_entry *default_seg = 0;
5630
2426c15f 5631 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5632 {
91d6fa6a
NC		 5633 unsigned int dupl = i.operands;
5634 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5635 unsigned int j;
5636
c0f3af97 5637 /* The destination must be an xmm register. */
9c2799c2 5638 gas_assert (i.reg_operands
91d6fa6a 5639 && MAX_OPERANDS > dupl
7ab9ffdd 5640 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5641
5642 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5643 {
c0f3af97 5644 /* The first operand is implicit and must be xmm0. */
9c2799c2 5645 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5646 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5647 return bad_implicit_operand (1);
5648
8cd7925b 5649 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5650 {
5651 /* Keep xmm0 for instructions with VEX prefix and 3
5652 sources. */
5653 goto duplicate;
5654 }
e2ec9d29 5655 else
c0f3af97
L		 5656 {
5657 /* We remove the first xmm0 and keep the number of
5658 operands unchanged, which in fact duplicates the
5659 destination. */
5660 for (j = 1; j < i.operands; j++)
5661 {
5662 i.op[j - 1] = i.op[j];
5663 i.types[j - 1] = i.types[j];
5664 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5665 }
5666 }
5667 }
5668 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5669 {
91d6fa6a 5670 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5671 && (i.tm.opcode_modifier.vexsources
5672 == VEX3SOURCES));
c0f3af97
L		 5673
5674 /* Add the implicit xmm0 for instructions with VEX prefix
5675 and 3 sources. */
5676 for (j = i.operands; j > 0; j--)
5677 {
5678 i.op[j] = i.op[j - 1];
5679 i.types[j] = i.types[j - 1];
5680 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5681 }
5682 i.op[0].regs
5683 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5684 i.types[0] = regxmm;
c0f3af97
L		 5685 i.tm.operand_types[0] = regxmm;
5686
5687 i.operands += 2;
5688 i.reg_operands += 2;
5689 i.tm.operands += 2;
5690
91d6fa6a 5691 dupl++;
c0f3af97 5692 dest++;
91d6fa6a
NC		 5693 i.op[dupl] = i.op[dest];
5694 i.types[dupl] = i.types[dest];
5695 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5696 }
c0f3af97
L		 5697 else
5698 {
5699duplicate:
5700 i.operands++;
5701 i.reg_operands++;
5702 i.tm.operands++;
5703
91d6fa6a
NC		 5704 i.op[dupl] = i.op[dest];
5705 i.types[dupl] = i.types[dest];
5706 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5707 }
5708
5709 if (i.tm.opcode_modifier.immext)
5710 process_immext ();
5711 }
5712 else if (i.tm.opcode_modifier.firstxmm0)
5713 {
5714 unsigned int j;
5715
43234a1e 5716 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5717 gas_assert (i.reg_operands
7ab9ffdd 5718 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5719 || operand_type_equal (&i.types[0], &regymm)
5720 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5721 if (register_number (i.op[0].regs) != 0)
c0f3af97 5722 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5723
5724 for (j = 1; j < i.operands; j++)
5725 {
5726 i.op[j - 1] = i.op[j];
5727 i.types[j - 1] = i.types[j];
5728
5729 /* We need to adjust fields in i.tm since they are used by
5730 build_modrm_byte. */
5731 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5732 }
5733
e2ec9d29
L		 5734 i.operands--;
5735 i.reg_operands--;
e2ec9d29
L		 5736 i.tm.operands--;
5737 }
5738 else if (i.tm.opcode_modifier.regkludge)
5739 {
5740 /* The imul $imm, %reg instruction is converted into
5741 imul $imm, %reg, %reg, and the clr %reg instruction
5742 is converted into xor %reg, %reg. */
5743
5744 unsigned int first_reg_op;
5745
5746 if (operand_type_check (i.types[0], reg))
5747 first_reg_op = 0;
5748 else
5749 first_reg_op = 1;
5750 /* Pretend we saw the extra register operand. */
9c2799c2 5751 gas_assert (i.reg_operands == 1
7ab9ffdd 5752 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5753 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5754 i.types[first_reg_op + 1] = i.types[first_reg_op];
5755 i.operands++;
5756 i.reg_operands++;
29b0f896
AM		 5757 }
5758
40fb9820 5759 if (i.tm.opcode_modifier.shortform)
29b0f896 5760 {
40fb9820
L		 5761 if (i.types[0].bitfield.sreg2
5762 || i.types[0].bitfield.sreg3)
29b0f896 5763 {
4eed87de
AM		 5764 if (i.tm.base_opcode == POP_SEG_SHORT
5765 && i.op[0].regs->reg_num == 1)
29b0f896 5766 {
a87af027 5767 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5768 return 0;
29b0f896 5769 }
4eed87de
AM		 5770 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5771 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5772 i.rex |= REX_B;
4eed87de
AM		 5773 }
5774 else
5775 {
7ab9ffdd 5776 /* The register or float register operand is in operand
85f10a01 5777 0 or 1. */
40fb9820 5778 unsigned int op;
7ab9ffdd
L		 5779
5780 if (i.types[0].bitfield.floatreg
5781 || operand_type_check (i.types[0], reg))
5782 op = 0;
5783 else
5784 op = 1;
4eed87de
AM		 5785 /* Register goes in low 3 bits of opcode. */
5786 i.tm.base_opcode |= i.op[op].regs->reg_num;
5787 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5788 i.rex |= REX_B;
40fb9820 5789 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5790 {
4eed87de
AM		 5791 /* Warn about some common errors, but press on regardless.
5792 The first case can be generated by gcc (<= 2.8.1). */
5793 if (i.operands == 2)
5794 {
5795 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5796 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5797 register_prefix, i.op[!intel_syntax].regs->reg_name,
5798 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5799 }
5800 else
5801 {
5802 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5803 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5804 register_prefix, i.op[0].regs->reg_name);
4eed87de 5805 }
29b0f896
AM		 5806 }
5807 }
5808 }
40fb9820 5809 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5810 {
5811 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5812 must be put into the modrm byte). Now, we make the modrm and
5813 index base bytes based on all the info we've collected. */
29b0f896
AM		 5814
5815 default_seg = build_modrm_byte ();
5816 }
8a2ed489 5817 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5818 {
5819 default_seg = &ds;
5820 }
40fb9820 5821 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5822 {
5823 /* For the string instructions that allow a segment override
5824 on one of their operands, the default segment is ds. */
5825 default_seg = &ds;
5826 }
5827
75178d9d
L		 5828 if (i.tm.base_opcode == 0x8d /* lea */
5829 && i.seg[0]
5830 && !quiet_warnings)
30123838 5831 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5832
5833 /* If a segment was explicitly specified, and the specified segment
5834 is not the default, use an opcode prefix to select it. If we
5835 never figured out what the default segment is, then default_seg
5836 will be zero at this point, and the specified segment prefix will
5837 always be used. */
29b0f896
AM		 5838 if ((i.seg[0]) && (i.seg[0] != default_seg))
5839 {
5840 if (!add_prefix (i.seg[0]->seg_prefix))
5841 return 0;
5842 }
5843 return 1;
5844}
5845
5846static const seg_entry *
e3bb37b5 5847build_modrm_byte (void)
29b0f896
AM		 5848{
5849 const seg_entry *default_seg = 0;
c0f3af97 5850 unsigned int source, dest;
8cd7925b 5851 int vex_3_sources;
c0f3af97
L		 5852
5853 /* The first operand of instructions with VEX prefix and 3 sources
5854 must be VEX_Imm4. */
8cd7925b 5855 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5856 if (vex_3_sources)
5857 {
91d6fa6a 5858 unsigned int nds, reg_slot;
4c2c6516 5859 expressionS *exp;
c0f3af97 5860
922d8de8 5861 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5862 && i.tm.opcode_modifier.immext)
5863 {
5864 dest = i.operands - 2;
5865 gas_assert (dest == 3);
5866 }
922d8de8 5867 else
a683cc34 5868 dest = i.operands - 1;
c0f3af97 5869 nds = dest - 1;
922d8de8 5870
a683cc34
SP		 5871 /* There are 2 kinds of instructions:
5872 1. 5 operands: 4 register operands or 3 register operands
5873 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 5874 VexW0 or VexW1. The destination must be either XMM, YMM or
5875 ZMM register.
a683cc34
SP		 5876 2. 4 operands: 4 register operands or 3 register operands
5877 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5878 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5879 || (i.reg_operands == 3 && i.mem_operands == 1))
5880 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5881 && (i.tm.opcode_modifier.veximmext
5882 || (i.imm_operands == 1
5883 && i.types[0].bitfield.vec_imm4
5884 && (i.tm.opcode_modifier.vexw == VEXW0
5885 || i.tm.opcode_modifier.vexw == VEXW1)
5886 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 5887 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
5888 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 5889
5890 if (i.imm_operands == 0)
5891 {
5892 /* When there is no immediate operand, generate an 8bit
5893 immediate operand to encode the first operand. */
5894 exp = &im_expressions[i.imm_operands++];
5895 i.op[i.operands].imms = exp;
5896 i.types[i.operands] = imm8;
5897 i.operands++;
5898 /* If VexW1 is set, the first operand is the source and
5899 the second operand is encoded in the immediate operand. */
5900 if (i.tm.opcode_modifier.vexw == VEXW1)
5901 {
5902 source = 0;
5903 reg_slot = 1;
5904 }
5905 else
5906 {
5907 source = 1;
5908 reg_slot = 0;
5909 }
5910
5911 /* FMA swaps REG and NDS. */
5912 if (i.tm.cpu_flags.bitfield.cpufma)
5913 {
5914 unsigned int tmp;
5915 tmp = reg_slot;
5916 reg_slot = nds;
5917 nds = tmp;
5918 }
5919
24981e7b
L		 5920 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5921 &regxmm)
a683cc34 5922 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 5923 &regymm)
5924 || operand_type_equal (&i.tm.operand_types[reg_slot],
5925 &regzmm));
a683cc34 5926 exp->X_op = O_constant;
4c692bc7 5927 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 5928 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
5929 }
922d8de8 5930 else
a683cc34
SP		 5931 {
5932 unsigned int imm_slot;
5933
5934 if (i.tm.opcode_modifier.vexw == VEXW0)
5935 {
5936 /* If VexW0 is set, the third operand is the source and
5937 the second operand is encoded in the immediate
5938 operand. */
5939 source = 2;
5940 reg_slot = 1;
5941 }
5942 else
5943 {
5944 /* VexW1 is set, the second operand is the source and
5945 the third operand is encoded in the immediate
5946 operand. */
5947 source = 1;
5948 reg_slot = 2;
5949 }
5950
5951 if (i.tm.opcode_modifier.immext)
5952 {
5953 /* When ImmExt is set, the immdiate byte is the last
5954 operand. */
5955 imm_slot = i.operands - 1;
5956 source--;
5957 reg_slot--;
5958 }
5959 else
5960 {
5961 imm_slot = 0;
5962
5963 /* Turn on Imm8 so that output_imm will generate it. */
5964 i.types[imm_slot].bitfield.imm8 = 1;
5965 }
5966
24981e7b
L		 5967 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5968 &regxmm)
5969 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 5970 &regymm)
5971 || operand_type_equal (&i.tm.operand_types[reg_slot],
5972 &regzmm));
a683cc34 5973 i.op[imm_slot].imms->X_add_number
4c692bc7 5974 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 5975 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 5976 }
5977
5978 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
5979 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 5980 &regymm)
5981 || operand_type_equal (&i.tm.operand_types[nds],
5982 &regzmm));
dae39acc 5983 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 5984 }
5985 else
5986 source = dest = 0;
29b0f896
AM		 5987
5988 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5989 implicit registers do not count. If there are 3 register
5990 operands, it must be a instruction with VexNDS. For a
5991 instruction with VexNDD, the destination register is encoded
5992 in VEX prefix. If there are 4 register operands, it must be
5993 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 5994 if (i.mem_operands == 0
5995 && ((i.reg_operands == 2
2426c15f 5996 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 5997 || (i.reg_operands == 3
2426c15f 5998 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 5999 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6000 {
cab737b9
L		 6001 switch (i.operands)
6002 {
6003 case 2:
6004 source = 0;
6005 break;
6006 case 3:
c81128dc
L		 6007 /* When there are 3 operands, one of them may be immediate,
6008 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6009 the first operand must be shift count register (cl) or it
6010 is an instruction with VexNDS. */
9c2799c2 6011 gas_assert (i.imm_operands == 1
7ab9ffdd 6012 || (i.imm_operands == 0
2426c15f 6013 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6014 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6015 if (operand_type_check (i.types[0], imm)
6016 || i.types[0].bitfield.shiftcount)
6017 source = 1;
6018 else
6019 source = 0;
cab737b9
L		 6020 break;
6021 case 4:
368d64cc
L		 6022 /* When there are 4 operands, the first two must be 8bit
6023 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6024 one.
6025
6026 For instructions with VexNDS, if the first operand
6027 an imm8, the source operand is the 2nd one. If the last
6028 operand is imm8, the source operand is the first one. */
9c2799c2 6029 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6030 && i.types[0].bitfield.imm8
6031 && i.types[1].bitfield.imm8)
2426c15f 6032 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6033 && i.imm_operands == 1
6034 && (i.types[0].bitfield.imm8
43234a1e
L		 6035 || i.types[i.operands - 1].bitfield.imm8
6036 || i.rounding)));
9f2670f2
L		 6037 if (i.imm_operands == 2)
6038 source = 2;
6039 else
c0f3af97
L		 6040 {
6041 if (i.types[0].bitfield.imm8)
6042 source = 1;
6043 else
6044 source = 0;
6045 }
c0f3af97
L		 6046 break;
6047 case 5:
43234a1e
L		 6048 if (i.tm.opcode_modifier.evex)
6049 {
6050 /* For EVEX instructions, when there are 5 operands, the
6051 first one must be immediate operand. If the second one
6052 is immediate operand, the source operand is the 3th
6053 one. If the last one is immediate operand, the source
6054 operand is the 2nd one. */
6055 gas_assert (i.imm_operands == 2
6056 && i.tm.opcode_modifier.sae
6057 && operand_type_check (i.types[0], imm));
6058 if (operand_type_check (i.types[1], imm))
6059 source = 2;
6060 else if (operand_type_check (i.types[4], imm))
6061 source = 1;
6062 else
6063 abort ();
6064 }
cab737b9
L		 6065 break;
6066 default:
6067 abort ();
6068 }
6069
c0f3af97
L		 6070 if (!vex_3_sources)
6071 {
6072 dest = source + 1;
6073
43234a1e
L		 6074 /* RC/SAE operand could be between DEST and SRC. That happens
6075 when one operand is GPR and the other one is XMM/YMM/ZMM
6076 register. */
6077 if (i.rounding && i.rounding->operand == (int) dest)
6078 dest++;
6079
2426c15f 6080 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6081 {
43234a1e
L		 6082 /* For instructions with VexNDS, the register-only source
6083 operand must be 32/64bit integer, XMM, YMM or ZMM
6084 register. It is encoded in VEX prefix. We need to
6085 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6086
6087 i386_operand_type op;
6088 unsigned int vvvv;
6089
6090 /* Check register-only source operand when two source
6091 operands are swapped. */
6092 if (!i.tm.operand_types[source].bitfield.baseindex
6093 && i.tm.operand_types[dest].bitfield.baseindex)
6094 {
6095 vvvv = source;
6096 source = dest;
6097 }
6098 else
6099 vvvv = dest;
6100
6101 op = i.tm.operand_types[vvvv];
fa99fab2 6102 op.bitfield.regmem = 0;
c0f3af97 6103 if ((dest + 1) >= i.operands
ac4eb736
AM		 6104 || (!op.bitfield.reg32
6105 && op.bitfield.reg64
f12dc422 6106 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6107 && !operand_type_equal (&op, &regymm)
6108 && !operand_type_equal (&op, &regzmm)
6109 && !operand_type_equal (&op, &regmask)))
c0f3af97 6110 abort ();
f12dc422 6111 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6112 dest++;
6113 }
6114 }
29b0f896
AM		 6115
6116 i.rm.mode = 3;
6117 /* One of the register operands will be encoded in the i.tm.reg
6118 field, the other in the combined i.tm.mode and i.tm.regmem
6119 fields. If no form of this instruction supports a memory
6120 destination operand, then we assume the source operand may
6121 sometimes be a memory operand and so we need to store the
6122 destination in the i.rm.reg field. */
40fb9820
L		 6123 if (!i.tm.operand_types[dest].bitfield.regmem
6124 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6125 {
6126 i.rm.reg = i.op[dest].regs->reg_num;
6127 i.rm.regmem = i.op[source].regs->reg_num;
6128 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6129 i.rex |= REX_R;
43234a1e
L		 6130 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6131 i.vrex |= REX_R;
29b0f896 6132 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6133 i.rex |= REX_B;
43234a1e
L		 6134 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6135 i.vrex |= REX_B;
29b0f896
AM		 6136 }
6137 else
6138 {
6139 i.rm.reg = i.op[source].regs->reg_num;
6140 i.rm.regmem = i.op[dest].regs->reg_num;
6141 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6142 i.rex |= REX_B;
43234a1e
L		 6143 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6144 i.vrex |= REX_B;
29b0f896 6145 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6146 i.rex |= REX_R;
43234a1e
L		 6147 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6148 i.vrex |= REX_R;
29b0f896 6149 }
161a04f6 6150 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6151 {
40fb9820
L		 6152 if (!i.types[0].bitfield.control
6153 && !i.types[1].bitfield.control)
c4a530c5 6154 abort ();
161a04f6 6155 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6156 add_prefix (LOCK_PREFIX_OPCODE);
6157 }
29b0f896
AM		 6158 }
6159 else
6160 { /* If it's not 2 reg operands... */
c0f3af97
L		 6161 unsigned int mem;
6162
29b0f896
AM		 6163 if (i.mem_operands)
6164 {
6165 unsigned int fake_zero_displacement = 0;
99018f42 6166 unsigned int op;
4eed87de 6167
7ab9ffdd
L		 6168 for (op = 0; op < i.operands; op++)
6169 if (operand_type_check (i.types[op], anymem))
6170 break;
7ab9ffdd 6171 gas_assert (op < i.operands);
29b0f896 6172
6c30d220
L		 6173 if (i.tm.opcode_modifier.vecsib)
6174 {
6175 if (i.index_reg->reg_num == RegEiz
6176 || i.index_reg->reg_num == RegRiz)
6177 abort ();
6178
6179 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6180 if (!i.base_reg)
6181 {
6182 i.sib.base = NO_BASE_REGISTER;
6183 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6184 /* No Vec_Disp8 if there is no base. */
6185 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6186 i.types[op].bitfield.disp8 = 0;
6187 i.types[op].bitfield.disp16 = 0;
6188 i.types[op].bitfield.disp64 = 0;
6189 if (flag_code != CODE_64BIT)
6190 {
6191 /* Must be 32 bit */
6192 i.types[op].bitfield.disp32 = 1;
6193 i.types[op].bitfield.disp32s = 0;
6194 }
6195 else
6196 {
6197 i.types[op].bitfield.disp32 = 0;
6198 i.types[op].bitfield.disp32s = 1;
6199 }
6200 }
6201 i.sib.index = i.index_reg->reg_num;
6202 if ((i.index_reg->reg_flags & RegRex) != 0)
6203 i.rex |= REX_X;
43234a1e
L		 6204 if ((i.index_reg->reg_flags & RegVRex) != 0)
6205 i.vrex |= REX_X;
6c30d220
L		 6206 }
6207
29b0f896
AM		 6208 default_seg = &ds;
6209
6210 if (i.base_reg == 0)
6211 {
6212 i.rm.mode = 0;
6213 if (!i.disp_operands)
6c30d220
L		 6214 {
6215 fake_zero_displacement = 1;
6216 /* Instructions with VSIB byte need 32bit displacement
6217 if there is no base register. */
6218 if (i.tm.opcode_modifier.vecsib)
6219 i.types[op].bitfield.disp32 = 1;
6220 }
29b0f896
AM		 6221 if (i.index_reg == 0)
6222 {
6c30d220 6223 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6224 /* Operand is just <disp> */
20f0a1fc 6225 if (flag_code == CODE_64BIT)
29b0f896
AM		 6226 {
6227 /* 64bit mode overwrites the 32bit absolute
6228 addressing by RIP relative addressing and
6229 absolute addressing is encoded by one of the
6230 redundant SIB forms. */
6231 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6232 i.sib.base = NO_BASE_REGISTER;
6233 i.sib.index = NO_INDEX_REGISTER;
fc225355 6234 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6235 ? disp32s : disp32);
20f0a1fc 6236 }
fc225355
L		 6237 else if ((flag_code == CODE_16BIT)
6238 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6239 {
6240 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6241 i.types[op] = disp16;
20f0a1fc
NC		 6242 }
6243 else
6244 {
6245 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6246 i.types[op] = disp32;
29b0f896
AM		 6247 }
6248 }
6c30d220 6249 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6250 {
6c30d220 6251 /* !i.base_reg && i.index_reg */
db51cc60
L		 6252 if (i.index_reg->reg_num == RegEiz
6253 || i.index_reg->reg_num == RegRiz)
6254 i.sib.index = NO_INDEX_REGISTER;
6255 else
6256 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6257 i.sib.base = NO_BASE_REGISTER;
6258 i.sib.scale = i.log2_scale_factor;
6259 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6260 /* No Vec_Disp8 if there is no base. */
6261 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6262 i.types[op].bitfield.disp8 = 0;
6263 i.types[op].bitfield.disp16 = 0;
6264 i.types[op].bitfield.disp64 = 0;
29b0f896 6265 if (flag_code != CODE_64BIT)
40fb9820
L		 6266 {
6267 /* Must be 32 bit */
6268 i.types[op].bitfield.disp32 = 1;
6269 i.types[op].bitfield.disp32s = 0;
6270 }
29b0f896 6271 else
40fb9820
L		 6272 {
6273 i.types[op].bitfield.disp32 = 0;
6274 i.types[op].bitfield.disp32s = 1;
6275 }
29b0f896 6276 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6277 i.rex |= REX_X;
29b0f896
AM		 6278 }
6279 }
6280 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6281 else if (i.base_reg->reg_num == RegRip ||
6282 i.base_reg->reg_num == RegEip)
29b0f896 6283 {
6c30d220 6284 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6285 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6286 i.types[op].bitfield.disp8 = 0;
6287 i.types[op].bitfield.disp16 = 0;
6288 i.types[op].bitfield.disp32 = 0;
6289 i.types[op].bitfield.disp32s = 1;
6290 i.types[op].bitfield.disp64 = 0;
43234a1e 6291 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6292 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6293 if (! i.disp_operands)
6294 fake_zero_displacement = 1;
29b0f896 6295 }
40fb9820 6296 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6297 {
6c30d220 6298 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6299 switch (i.base_reg->reg_num)
6300 {
6301 case 3: /* (%bx) */
6302 if (i.index_reg == 0)
6303 i.rm.regmem = 7;
6304 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6305 i.rm.regmem = i.index_reg->reg_num - 6;
6306 break;
6307 case 5: /* (%bp) */
6308 default_seg = &ss;
6309 if (i.index_reg == 0)
6310 {
6311 i.rm.regmem = 6;
40fb9820 6312 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6313 {
6314 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6315 if (i.tm.operand_types[op].bitfield.vec_disp8)
6316 i.types[op].bitfield.vec_disp8 = 1;
6317 else
6318 i.types[op].bitfield.disp8 = 1;
252b5132 6319 fake_zero_displacement = 1;
29b0f896
AM		 6320 }
6321 }
6322 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6323 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6324 break;
6325 default: /* (%si) -> 4 or (%di) -> 5 */
6326 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6327 }
6328 i.rm.mode = mode_from_disp_size (i.types[op]);
6329 }
6330 else /* i.base_reg and 32/64 bit mode */
6331 {
6332 if (flag_code == CODE_64BIT
40fb9820
L		 6333 && operand_type_check (i.types[op], disp))
6334 {
6335 i386_operand_type temp;
0dfbf9d7 6336 operand_type_set (&temp, 0);
40fb9820 6337 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6338 temp.bitfield.vec_disp8
6339 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6340 i.types[op] = temp;
6341 if (i.prefix[ADDR_PREFIX] == 0)
6342 i.types[op].bitfield.disp32s = 1;
6343 else
6344 i.types[op].bitfield.disp32 = 1;
6345 }
20f0a1fc 6346
6c30d220
L		 6347 if (!i.tm.opcode_modifier.vecsib)
6348 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6349 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6350 i.rex |= REX_B;
29b0f896
AM		 6351 i.sib.base = i.base_reg->reg_num;
6352 /* x86-64 ignores REX prefix bit here to avoid decoder
6353 complications. */
848930b2
JB		 6354 if (!(i.base_reg->reg_flags & RegRex)
6355 && (i.base_reg->reg_num == EBP_REG_NUM
6356 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6357 default_seg = &ss;
848930b2 6358 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6359 {
848930b2 6360 fake_zero_displacement = 1;
43234a1e
L		 6361 if (i.tm.operand_types [op].bitfield.vec_disp8)
6362 i.types[op].bitfield.vec_disp8 = 1;
6363 else
6364 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6365 }
6366 i.sib.scale = i.log2_scale_factor;
6367 if (i.index_reg == 0)
6368 {
6c30d220 6369 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6370 /* <disp>(%esp) becomes two byte modrm with no index
6371 register. We've already stored the code for esp
6372 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6373 Any base register besides %esp will not use the
6374 extra modrm byte. */
6375 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6376 }
6c30d220 6377 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6378 {
db51cc60
L		 6379 if (i.index_reg->reg_num == RegEiz
6380 || i.index_reg->reg_num == RegRiz)
6381 i.sib.index = NO_INDEX_REGISTER;
6382 else
6383 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6384 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6385 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6386 i.rex |= REX_X;
29b0f896 6387 }
67a4f2b7
AO		 6388
6389 if (i.disp_operands
6390 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6391 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6392 i.rm.mode = 0;
6393 else
a501d77e
L		 6394 {
6395 if (!fake_zero_displacement
6396 && !i.disp_operands
6397 && i.disp_encoding)
6398 {
6399 fake_zero_displacement = 1;
6400 if (i.disp_encoding == disp_encoding_8bit)
6401 i.types[op].bitfield.disp8 = 1;
6402 else
6403 i.types[op].bitfield.disp32 = 1;
6404 }
6405 i.rm.mode = mode_from_disp_size (i.types[op]);
6406 }
29b0f896 6407 }
252b5132 6408
29b0f896
AM		 6409 if (fake_zero_displacement)
6410 {
6411 /* Fakes a zero displacement assuming that i.types[op]
6412 holds the correct displacement size. */
6413 expressionS *exp;
6414
9c2799c2 6415 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6416 exp = &disp_expressions[i.disp_operands++];
6417 i.op[op].disps = exp;
6418 exp->X_op = O_constant;
6419 exp->X_add_number = 0;
6420 exp->X_add_symbol = (symbolS *) 0;
6421 exp->X_op_symbol = (symbolS *) 0;
6422 }
c0f3af97
L		 6423
6424 mem = op;
29b0f896 6425 }
c0f3af97
L		 6426 else
6427 mem = ~0;
252b5132 6428
8c43a48b 6429 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6430 {
6431 if (operand_type_check (i.types[0], imm))
6432 i.vex.register_specifier = NULL;
6433 else
6434 {
6435 /* VEX.vvvv encodes one of the sources when the first
6436 operand is not an immediate. */
1ef99a7b 6437 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6438 i.vex.register_specifier = i.op[0].regs;
6439 else
6440 i.vex.register_specifier = i.op[1].regs;
6441 }
6442
6443 /* Destination is a XMM register encoded in the ModRM.reg
6444 and VEX.R bit. */
6445 i.rm.reg = i.op[2].regs->reg_num;
6446 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6447 i.rex |= REX_R;
6448
6449 /* ModRM.rm and VEX.B encodes the other source. */
6450 if (!i.mem_operands)
6451 {
6452 i.rm.mode = 3;
6453
1ef99a7b 6454 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6455 i.rm.regmem = i.op[1].regs->reg_num;
6456 else
6457 i.rm.regmem = i.op[0].regs->reg_num;
6458
6459 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6460 i.rex |= REX_B;
6461 }
6462 }
2426c15f 6463 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6464 {
6465 i.vex.register_specifier = i.op[2].regs;
6466 if (!i.mem_operands)
6467 {
6468 i.rm.mode = 3;
6469 i.rm.regmem = i.op[1].regs->reg_num;
6470 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6471 i.rex |= REX_B;
6472 }
6473 }
29b0f896
AM		 6474 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6475 (if any) based on i.tm.extension_opcode. Again, we must be
6476 careful to make sure that segment/control/debug/test/MMX
6477 registers are coded into the i.rm.reg field. */
f88c9eb0 6478 else if (i.reg_operands)
29b0f896 6479 {
99018f42 6480 unsigned int op;
7ab9ffdd
L		 6481 unsigned int vex_reg = ~0;
6482
6483 for (op = 0; op < i.operands; op++)
6484 if (i.types[op].bitfield.reg8
6485 || i.types[op].bitfield.reg16
6486 || i.types[op].bitfield.reg32
6487 || i.types[op].bitfield.reg64
6488 || i.types[op].bitfield.regmmx
6489 || i.types[op].bitfield.regxmm
6490 || i.types[op].bitfield.regymm
7e8b059b 6491 || i.types[op].bitfield.regbnd
43234a1e
L		 6492 || i.types[op].bitfield.regzmm
6493 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6494 || i.types[op].bitfield.sreg2
6495 || i.types[op].bitfield.sreg3
6496 || i.types[op].bitfield.control
6497 || i.types[op].bitfield.debug
6498 || i.types[op].bitfield.test)
6499 break;
c0209578 6500
7ab9ffdd
L		 6501 if (vex_3_sources)
6502 op = dest;
2426c15f 6503 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6504 {
6505 /* For instructions with VexNDS, the register-only
6506 source operand is encoded in VEX prefix. */
6507 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6508
7ab9ffdd 6509 if (op > mem)
c0f3af97 6510 {
7ab9ffdd
L		 6511 vex_reg = op++;
6512 gas_assert (op < i.operands);
c0f3af97
L		 6513 }
6514 else
c0f3af97 6515 {
f12dc422
L		 6516 /* Check register-only source operand when two source
6517 operands are swapped. */
6518 if (!i.tm.operand_types[op].bitfield.baseindex
6519 && i.tm.operand_types[op + 1].bitfield.baseindex)
6520 {
6521 vex_reg = op;
6522 op += 2;
6523 gas_assert (mem == (vex_reg + 1)
6524 && op < i.operands);
6525 }
6526 else
6527 {
6528 vex_reg = op + 1;
6529 gas_assert (vex_reg < i.operands);
6530 }
c0f3af97 6531 }
7ab9ffdd 6532 }
2426c15f 6533 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6534 {
f12dc422 6535 /* For instructions with VexNDD, the register destination
7ab9ffdd 6536 is encoded in VEX prefix. */
f12dc422
L		 6537 if (i.mem_operands == 0)
6538 {
6539 /* There is no memory operand. */
6540 gas_assert ((op + 2) == i.operands);
6541 vex_reg = op + 1;
6542 }
6543 else
8d63c93e 6544 {
f12dc422
L		 6545 /* There are only 2 operands. */
6546 gas_assert (op < 2 && i.operands == 2);
6547 vex_reg = 1;
6548 }
7ab9ffdd
L		 6549 }
6550 else
6551 gas_assert (op < i.operands);
99018f42 6552
7ab9ffdd
L		 6553 if (vex_reg != (unsigned int) ~0)
6554 {
f12dc422 6555 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6556
f12dc422
L		 6557 if (type->bitfield.reg32 != 1
6558 && type->bitfield.reg64 != 1
6559 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6560 && !operand_type_equal (type, &regymm)
6561 && !operand_type_equal (type, &regzmm)
6562 && !operand_type_equal (type, &regmask))
7ab9ffdd 6563 abort ();
f88c9eb0 6564
7ab9ffdd
L		 6565 i.vex.register_specifier = i.op[vex_reg].regs;
6566 }
6567
1b9f0c97
L		 6568 /* Don't set OP operand twice. */
6569 if (vex_reg != op)
7ab9ffdd 6570 {
1b9f0c97
L		 6571 /* If there is an extension opcode to put here, the
6572 register number must be put into the regmem field. */
6573 if (i.tm.extension_opcode != None)
6574 {
6575 i.rm.regmem = i.op[op].regs->reg_num;
6576 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6577 i.rex |= REX_B;
43234a1e
L		 6578 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6579 i.vrex |= REX_B;
1b9f0c97
L		 6580 }
6581 else
6582 {
6583 i.rm.reg = i.op[op].regs->reg_num;
6584 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6585 i.rex |= REX_R;
43234a1e
L		 6586 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6587 i.vrex |= REX_R;
1b9f0c97 6588 }
7ab9ffdd 6589 }
252b5132 6590
29b0f896
AM		 6591 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6592 must set it to 3 to indicate this is a register operand
6593 in the regmem field. */
6594 if (!i.mem_operands)
6595 i.rm.mode = 3;
6596 }
252b5132 6597
29b0f896 6598 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6599 if (i.tm.extension_opcode != None)
29b0f896
AM		 6600 i.rm.reg = i.tm.extension_opcode;
6601 }
6602 return default_seg;
6603}
252b5132 6604
29b0f896 6605static void
e3bb37b5 6606output_branch (void)
29b0f896
AM		 6607{
6608 char *p;
f8a5c266 6609 int size;
29b0f896
AM		 6610 int code16;
6611 int prefix;
6612 relax_substateT subtype;
6613 symbolS *sym;
6614 offsetT off;
6615
f8a5c266 6616 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6617 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6618
6619 prefix = 0;
6620 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6621 {
29b0f896
AM		 6622 prefix = 1;
6623 i.prefixes -= 1;
6624 code16 ^= CODE16;
252b5132 6625 }
29b0f896
AM		 6626 /* Pentium4 branch hints. */
6627 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6628 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6629 {
29b0f896
AM		 6630 prefix++;
6631 i.prefixes--;
6632 }
6633 if (i.prefix[REX_PREFIX] != 0)
6634 {
6635 prefix++;
6636 i.prefixes--;
2f66722d
AM		 6637 }
6638
7e8b059b
L		 6639 /* BND prefixed jump. */
6640 if (i.prefix[BND_PREFIX] != 0)
6641 {
6642 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6643 i.prefixes -= 1;
6644 }
6645
29b0f896
AM		 6646 if (i.prefixes != 0 && !intel_syntax)
6647 as_warn (_("skipping prefixes on this instruction"));
6648
6649 /* It's always a symbol; End frag & setup for relax.
6650 Make sure there is enough room in this frag for the largest
6651 instruction we may generate in md_convert_frag. This is 2
6652 bytes for the opcode and room for the prefix and largest
6653 displacement. */
6654 frag_grow (prefix + 2 + 4);
6655 /* Prefix and 1 opcode byte go in fr_fix. */
6656 p = frag_more (prefix + 1);
6657 if (i.prefix[DATA_PREFIX] != 0)
6658 *p++ = DATA_PREFIX_OPCODE;
6659 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6660 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6661 *p++ = i.prefix[SEG_PREFIX];
6662 if (i.prefix[REX_PREFIX] != 0)
6663 *p++ = i.prefix[REX_PREFIX];
6664 *p = i.tm.base_opcode;
6665
6666 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6667 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6668 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6669 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6670 else
f8a5c266 6671 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6672 subtype |= code16;
3e73aa7c 6673
29b0f896
AM		 6674 sym = i.op[0].disps->X_add_symbol;
6675 off = i.op[0].disps->X_add_number;
3e73aa7c 6676
29b0f896
AM		 6677 if (i.op[0].disps->X_op != O_constant
6678 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6679 {
29b0f896
AM		 6680 /* Handle complex expressions. */
6681 sym = make_expr_symbol (i.op[0].disps);
6682 off = 0;
6683 }
3e73aa7c 6684
29b0f896
AM		 6685 /* 1 possible extra opcode + 4 byte displacement go in var part.
6686 Pass reloc in fr_var. */
d258b828 6687 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 6688}
3e73aa7c 6689
29b0f896 6690static void
e3bb37b5 6691output_jump (void)
29b0f896
AM		 6692{
6693 char *p;
6694 int size;
3e02c1cc 6695 fixS *fixP;
29b0f896 6696
40fb9820 6697 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6698 {
6699 /* This is a loop or jecxz type instruction. */
6700 size = 1;
6701 if (i.prefix[ADDR_PREFIX] != 0)
6702 {
6703 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6704 i.prefixes -= 1;
6705 }
6706 /* Pentium4 branch hints. */
6707 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6708 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6709 {
6710 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6711 i.prefixes--;
3e73aa7c
JH		 6712 }
6713 }
29b0f896
AM		 6714 else
6715 {
6716 int code16;
3e73aa7c 6717
29b0f896
AM		 6718 code16 = 0;
6719 if (flag_code == CODE_16BIT)
6720 code16 = CODE16;
3e73aa7c 6721
29b0f896
AM		 6722 if (i.prefix[DATA_PREFIX] != 0)
6723 {
6724 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6725 i.prefixes -= 1;
6726 code16 ^= CODE16;
6727 }
252b5132 6728
29b0f896
AM		 6729 size = 4;
6730 if (code16)
6731 size = 2;
6732 }
9fcc94b6 6733
29b0f896
AM		 6734 if (i.prefix[REX_PREFIX] != 0)
6735 {
6736 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6737 i.prefixes -= 1;
6738 }
252b5132 6739
7e8b059b
L		 6740 /* BND prefixed jump. */
6741 if (i.prefix[BND_PREFIX] != 0)
6742 {
6743 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6744 i.prefixes -= 1;
6745 }
6746
29b0f896
AM		 6747 if (i.prefixes != 0 && !intel_syntax)
6748 as_warn (_("skipping prefixes on this instruction"));
e0890092 6749
42164a71
L		 6750 p = frag_more (i.tm.opcode_length + size);
6751 switch (i.tm.opcode_length)
6752 {
6753 case 2:
6754 *p++ = i.tm.base_opcode >> 8;
6755 case 1:
6756 *p++ = i.tm.base_opcode;
6757 break;
6758 default:
6759 abort ();
6760 }
e0890092 6761
3e02c1cc 6762 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6763 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 6764
6765 /* All jumps handled here are signed, but don't use a signed limit
6766 check for 32 and 16 bit jumps as we want to allow wrap around at
6767 4G and 64k respectively. */
6768 if (size == 1)
6769 fixP->fx_signed = 1;
29b0f896 6770}
e0890092 6771
29b0f896 6772static void
e3bb37b5 6773output_interseg_jump (void)
29b0f896
AM		 6774{
6775 char *p;
6776 int size;
6777 int prefix;
6778 int code16;
252b5132 6779
29b0f896
AM		 6780 code16 = 0;
6781 if (flag_code == CODE_16BIT)
6782 code16 = CODE16;
a217f122 6783
29b0f896
AM		 6784 prefix = 0;
6785 if (i.prefix[DATA_PREFIX] != 0)
6786 {
6787 prefix = 1;
6788 i.prefixes -= 1;
6789 code16 ^= CODE16;
6790 }
6791 if (i.prefix[REX_PREFIX] != 0)
6792 {
6793 prefix++;
6794 i.prefixes -= 1;
6795 }
252b5132 6796
29b0f896
AM		 6797 size = 4;
6798 if (code16)
6799 size = 2;
252b5132 6800
29b0f896
AM		 6801 if (i.prefixes != 0 && !intel_syntax)
6802 as_warn (_("skipping prefixes on this instruction"));
252b5132 6803
29b0f896
AM		 6804 /* 1 opcode; 2 segment; offset */
6805 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6806
29b0f896
AM		 6807 if (i.prefix[DATA_PREFIX] != 0)
6808 *p++ = DATA_PREFIX_OPCODE;
252b5132 6809
29b0f896
AM		 6810 if (i.prefix[REX_PREFIX] != 0)
6811 *p++ = i.prefix[REX_PREFIX];
252b5132 6812
29b0f896
AM		 6813 *p++ = i.tm.base_opcode;
6814 if (i.op[1].imms->X_op == O_constant)
6815 {
6816 offsetT n = i.op[1].imms->X_add_number;
252b5132 6817
29b0f896
AM		 6818 if (size == 2
6819 && !fits_in_unsigned_word (n)
6820 && !fits_in_signed_word (n))
6821 {
6822 as_bad (_("16-bit jump out of range"));
6823 return;
6824 }
6825 md_number_to_chars (p, n, size);
6826 }
6827 else
6828 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6829 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 6830 if (i.op[0].imms->X_op != O_constant)
6831 as_bad (_("can't handle non absolute segment in `%s'"),
6832 i.tm.name);
6833 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6834}
a217f122 6835
29b0f896 6836static void
e3bb37b5 6837output_insn (void)
29b0f896 6838{
2bbd9c25
JJ		 6839 fragS *insn_start_frag;
6840 offsetT insn_start_off;
6841
29b0f896
AM		 6842 /* Tie dwarf2 debug info to the address at the start of the insn.
6843 We can't do this after the insn has been output as the current
6844 frag may have been closed off. eg. by frag_var. */
6845 dwarf2_emit_insn (0);
6846
2bbd9c25
JJ		 6847 insn_start_frag = frag_now;
6848 insn_start_off = frag_now_fix ();
6849
29b0f896 6850 /* Output jumps. */
40fb9820 6851 if (i.tm.opcode_modifier.jump)
29b0f896 6852 output_branch ();
40fb9820
L		 6853 else if (i.tm.opcode_modifier.jumpbyte
6854 || i.tm.opcode_modifier.jumpdword)
29b0f896 6855 output_jump ();
40fb9820 6856 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6857 output_interseg_jump ();
6858 else
6859 {
6860 /* Output normal instructions here. */
6861 char *p;
6862 unsigned char *q;
47465058 6863 unsigned int j;
331d2d0d 6864 unsigned int prefix;
4dffcebc 6865
d022bddd
IT		 6866 /* Some processors fail on LOCK prefix. This options makes
6867 assembler ignore LOCK prefix and serves as a workaround. */
6868 if (omit_lock_prefix)
6869 {
6870 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
6871 return;
6872 i.prefix[LOCK_PREFIX] = 0;
6873 }
6874
43234a1e
L		 6875 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6876 don't need the explicit prefix. */
6877 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 6878 {
c0f3af97 6879 switch (i.tm.opcode_length)
bc4bd9ab 6880 {
c0f3af97
L		 6881 case 3:
6882 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6883 {
c0f3af97
L		 6884 prefix = (i.tm.base_opcode >> 24) & 0xff;
6885 goto check_prefix;
6886 }
6887 break;
6888 case 2:
6889 if ((i.tm.base_opcode & 0xff0000) != 0)
6890 {
6891 prefix = (i.tm.base_opcode >> 16) & 0xff;
6892 if (i.tm.cpu_flags.bitfield.cpupadlock)
6893 {
4dffcebc 6894check_prefix:
c0f3af97 6895 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6896 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6897 != REPE_PREFIX_OPCODE))
6898 add_prefix (prefix);
6899 }
6900 else
4dffcebc
L		 6901 add_prefix (prefix);
6902 }
c0f3af97
L		 6903 break;
6904 case 1:
6905 break;
6906 default:
6907 abort ();
bc4bd9ab 6908 }
c0f3af97 6909
6d19a37a 6910#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 6911 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
6912 R_X86_64_GOTTPOFF relocation so that linker can safely
6913 perform IE->LE optimization. */
6914 if (x86_elf_abi == X86_64_X32_ABI
6915 && i.operands == 2
6916 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
6917 && i.prefix[REX_PREFIX] == 0)
6918 add_prefix (REX_OPCODE);
6d19a37a 6919#endif
cf61b747 6920
c0f3af97
L		 6921 /* The prefix bytes. */
6922 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
6923 if (*q)
6924 FRAG_APPEND_1_CHAR (*q);
0f10071e 6925 }
ae5c1c7b 6926 else
c0f3af97
L		 6927 {
6928 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
6929 if (*q)
6930 switch (j)
6931 {
6932 case REX_PREFIX:
6933 /* REX byte is encoded in VEX prefix. */
6934 break;
6935 case SEG_PREFIX:
6936 case ADDR_PREFIX:
6937 FRAG_APPEND_1_CHAR (*q);
6938 break;
6939 default:
6940 /* There should be no other prefixes for instructions
6941 with VEX prefix. */
6942 abort ();
6943 }
6944
43234a1e
L		 6945 /* For EVEX instructions i.vrex should become 0 after
6946 build_evex_prefix. For VEX instructions upper 16 registers
6947 aren't available, so VREX should be 0. */
6948 if (i.vrex)
6949 abort ();
c0f3af97
L		 6950 /* Now the VEX prefix. */
6951 p = frag_more (i.vex.length);
6952 for (j = 0; j < i.vex.length; j++)
6953 p[j] = i.vex.bytes[j];
6954 }
252b5132 6955
29b0f896 6956 /* Now the opcode; be careful about word order here! */
4dffcebc 6957 if (i.tm.opcode_length == 1)
29b0f896
AM		 6958 {
6959 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
6960 }
6961 else
6962 {
4dffcebc 6963 switch (i.tm.opcode_length)
331d2d0d 6964 {
43234a1e
L		 6965 case 4:
6966 p = frag_more (4);
6967 *p++ = (i.tm.base_opcode >> 24) & 0xff;
6968 *p++ = (i.tm.base_opcode >> 16) & 0xff;
6969 break;
4dffcebc 6970 case 3:
331d2d0d
L		 6971 p = frag_more (3);
6972 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 6973 break;
6974 case 2:
6975 p = frag_more (2);
6976 break;
6977 default:
6978 abort ();
6979 break;
331d2d0d 6980 }
0f10071e 6981
29b0f896
AM		 6982 /* Put out high byte first: can't use md_number_to_chars! */
6983 *p++ = (i.tm.base_opcode >> 8) & 0xff;
6984 *p = i.tm.base_opcode & 0xff;
6985 }
3e73aa7c 6986
29b0f896 6987 /* Now the modrm byte and sib byte (if present). */
40fb9820 6988 if (i.tm.opcode_modifier.modrm)
29b0f896 6989 {
4a3523fa
L		 6990 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
6991 | i.rm.reg << 3
6992 | i.rm.mode << 6));
29b0f896
AM		 6993 /* If i.rm.regmem == ESP (4)
6994 && i.rm.mode != (Register mode)
6995 && not 16 bit
6996 ==> need second modrm byte. */
6997 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
6998 && i.rm.mode != 3
40fb9820 6999 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7000 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7001 | i.sib.index << 3
7002 | i.sib.scale << 6));
29b0f896 7003 }
3e73aa7c 7004
29b0f896 7005 if (i.disp_operands)
2bbd9c25 7006 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7007
29b0f896 7008 if (i.imm_operands)
2bbd9c25 7009 output_imm (insn_start_frag, insn_start_off);
29b0f896 7010 }
252b5132 7011
29b0f896
AM		 7012#ifdef DEBUG386
7013 if (flag_debug)
7014 {
7b81dfbb 7015 pi ("" /*line*/, &i);
29b0f896
AM		 7016 }
7017#endif /* DEBUG386 */
7018}
252b5132 7019
e205caa7
L		 7020/* Return the size of the displacement operand N. */
7021
7022static int
7023disp_size (unsigned int n)
7024{
7025 int size = 4;
43234a1e
L		 7026
7027 /* Vec_Disp8 has to be 8bit. */
7028 if (i.types[n].bitfield.vec_disp8)
7029 size = 1;
7030 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7031 size = 8;
7032 else if (i.types[n].bitfield.disp8)
7033 size = 1;
7034 else if (i.types[n].bitfield.disp16)
7035 size = 2;
e205caa7
L		 7036 return size;
7037}
7038
7039/* Return the size of the immediate operand N. */
7040
7041static int
7042imm_size (unsigned int n)
7043{
7044 int size = 4;
40fb9820
L		 7045 if (i.types[n].bitfield.imm64)
7046 size = 8;
7047 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7048 size = 1;
7049 else if (i.types[n].bitfield.imm16)
7050 size = 2;
e205caa7
L		 7051 return size;
7052}
7053
29b0f896 7054static void
64e74474 7055output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7056{
7057 char *p;
7058 unsigned int n;
252b5132 7059
29b0f896
AM		 7060 for (n = 0; n < i.operands; n++)
7061 {
43234a1e
L		 7062 if (i.types[n].bitfield.vec_disp8
7063 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7064 {
7065 if (i.op[n].disps->X_op == O_constant)
7066 {
e205caa7 7067 int size = disp_size (n);
43234a1e 7068 offsetT val = i.op[n].disps->X_add_number;
252b5132 7069
43234a1e
L		 7070 if (i.types[n].bitfield.vec_disp8)
7071 val >>= i.memshift;
7072 val = offset_in_range (val, size);
29b0f896
AM		 7073 p = frag_more (size);
7074 md_number_to_chars (p, val, size);
7075 }
7076 else
7077 {
f86103b7 7078 enum bfd_reloc_code_real reloc_type;
e205caa7 7079 int size = disp_size (n);
40fb9820 7080 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 7081 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7082
e205caa7 7083 /* We can't have 8 bit displacement here. */
9c2799c2 7084 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7085
29b0f896
AM		 7086 /* The PC relative address is computed relative
7087 to the instruction boundary, so in case immediate
7088 fields follows, we need to adjust the value. */
7089 if (pcrel && i.imm_operands)
7090 {
29b0f896 7091 unsigned int n1;
e205caa7 7092 int sz = 0;
252b5132 7093
29b0f896 7094 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7095 if (operand_type_check (i.types[n1], imm))
252b5132 7096 {
e205caa7
L		 7097 /* Only one immediate is allowed for PC
7098 relative address. */
9c2799c2 7099 gas_assert (sz == 0);
e205caa7
L		 7100 sz = imm_size (n1);
7101 i.op[n].disps->X_add_number -= sz;
252b5132 7102 }
29b0f896 7103 /* We should find the immediate. */
9c2799c2 7104 gas_assert (sz != 0);
29b0f896 7105 }
520dc8e8 7106
29b0f896 7107 p = frag_more (size);
d258b828 7108 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7109 if (GOT_symbol
2bbd9c25 7110 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7111 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7112 || reloc_type == BFD_RELOC_X86_64_32S
7113 || (reloc_type == BFD_RELOC_64
7114 && object_64bit))
d6ab8113
JB		 7115 && (i.op[n].disps->X_op == O_symbol
7116 || (i.op[n].disps->X_op == O_add
7117 && ((symbol_get_value_expression
7118 (i.op[n].disps->X_op_symbol)->X_op)
7119 == O_subtract))))
7120 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7121 {
7122 offsetT add;
7123
7124 if (insn_start_frag == frag_now)
7125 add = (p - frag_now->fr_literal) - insn_start_off;
7126 else
7127 {
7128 fragS *fr;
7129
7130 add = insn_start_frag->fr_fix - insn_start_off;
7131 for (fr = insn_start_frag->fr_next;
7132 fr && fr != frag_now; fr = fr->fr_next)
7133 add += fr->fr_fix;
7134 add += p - frag_now->fr_literal;
7135 }
7136
4fa24527 7137 if (!object_64bit)
7b81dfbb
AJ		 7138 {
7139 reloc_type = BFD_RELOC_386_GOTPC;
7140 i.op[n].imms->X_add_number += add;
7141 }
7142 else if (reloc_type == BFD_RELOC_64)
7143 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7144 else
7b81dfbb
AJ		 7145 /* Don't do the adjustment for x86-64, as there
7146 the pcrel addressing is relative to the _next_
7147 insn, and that is taken care of in other code. */
d6ab8113 7148 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7149 }
062cd5e7 7150 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 7151 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 7152 }
7153 }
7154 }
7155}
252b5132 7156
29b0f896 7157static void
64e74474 7158output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7159{
7160 char *p;
7161 unsigned int n;
252b5132 7162
29b0f896
AM		 7163 for (n = 0; n < i.operands; n++)
7164 {
43234a1e
L		 7165 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7166 if (i.rounding && (int) n == i.rounding->operand)
7167 continue;
7168
40fb9820 7169 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7170 {
7171 if (i.op[n].imms->X_op == O_constant)
7172 {
e205caa7 7173 int size = imm_size (n);
29b0f896 7174 offsetT val;
b4cac588 7175
29b0f896
AM		 7176 val = offset_in_range (i.op[n].imms->X_add_number,
7177 size);
7178 p = frag_more (size);
7179 md_number_to_chars (p, val, size);
7180 }
7181 else
7182 {
7183 /* Not absolute_section.
7184 Need a 32-bit fixup (don't support 8bit
7185 non-absolute imms). Try to support other
7186 sizes ... */
f86103b7 7187 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7188 int size = imm_size (n);
7189 int sign;
29b0f896 7190
40fb9820 7191 if (i.types[n].bitfield.imm32s
a7d61044 7192 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7193 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7194 sign = 1;
e205caa7
L		 7195 else
7196 sign = 0;
520dc8e8 7197
29b0f896 7198 p = frag_more (size);
d258b828 7199 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7200
2bbd9c25
JJ		 7201 /* This is tough to explain. We end up with this one if we
7202 * have operands that look like
7203 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7204 * obtain the absolute address of the GOT, and it is strongly
7205 * preferable from a performance point of view to avoid using
7206 * a runtime relocation for this. The actual sequence of
7207 * instructions often look something like:
7208 *
7209 * call .L66
7210 * .L66:
7211 * popl %ebx
7212 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7213 *
7214 * The call and pop essentially return the absolute address
7215 * of the label .L66 and store it in %ebx. The linker itself
7216 * will ultimately change the first operand of the addl so
7217 * that %ebx points to the GOT, but to keep things simple, the
7218 * .o file must have this operand set so that it generates not
7219 * the absolute address of .L66, but the absolute address of
7220 * itself. This allows the linker itself simply treat a GOTPC
7221 * relocation as asking for a pcrel offset to the GOT to be
7222 * added in, and the addend of the relocation is stored in the
7223 * operand field for the instruction itself.
7224 *
7225 * Our job here is to fix the operand so that it would add
7226 * the correct offset so that %ebx would point to itself. The
7227 * thing that is tricky is that .-.L66 will point to the
7228 * beginning of the instruction, so we need to further modify
7229 * the operand so that it will point to itself. There are
7230 * other cases where you have something like:
7231 *
7232 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7233 *
7234 * and here no correction would be required. Internally in
7235 * the assembler we treat operands of this form as not being
7236 * pcrel since the '.' is explicitly mentioned, and I wonder
7237 * whether it would simplify matters to do it this way. Who
7238 * knows. In earlier versions of the PIC patches, the
7239 * pcrel_adjust field was used to store the correction, but
7240 * since the expression is not pcrel, I felt it would be
7241 * confusing to do it this way. */
7242
d6ab8113 7243 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7244 || reloc_type == BFD_RELOC_X86_64_32S
7245 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7246 && GOT_symbol
7247 && GOT_symbol == i.op[n].imms->X_add_symbol
7248 && (i.op[n].imms->X_op == O_symbol
7249 || (i.op[n].imms->X_op == O_add
7250 && ((symbol_get_value_expression
7251 (i.op[n].imms->X_op_symbol)->X_op)
7252 == O_subtract))))
7253 {
2bbd9c25
JJ		 7254 offsetT add;
7255
7256 if (insn_start_frag == frag_now)
7257 add = (p - frag_now->fr_literal) - insn_start_off;
7258 else
7259 {
7260 fragS *fr;
7261
7262 add = insn_start_frag->fr_fix - insn_start_off;
7263 for (fr = insn_start_frag->fr_next;
7264 fr && fr != frag_now; fr = fr->fr_next)
7265 add += fr->fr_fix;
7266 add += p - frag_now->fr_literal;
7267 }
7268
4fa24527 7269 if (!object_64bit)
d6ab8113 7270 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7271 else if (size == 4)
d6ab8113 7272 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7273 else if (size == 8)
7274 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7275 i.op[n].imms->X_add_number += add;
29b0f896 7276 }
29b0f896
AM		 7277 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7278 i.op[n].imms, 0, reloc_type);
7279 }
7280 }
7281 }
252b5132
RH		 7282}
7283\f
d182319b
JB		 7284/* x86_cons_fix_new is called via the expression parsing code when a
7285 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7286static int cons_sign = -1;
7287
7288void
e3bb37b5 7289x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7290 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7291{
d258b828 7292 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7293
7294#ifdef TE_PE
7295 if (exp->X_op == O_secrel)
7296 {
7297 exp->X_op = O_symbol;
7298 r = BFD_RELOC_32_SECREL;
7299 }
7300#endif
7301
7302 fix_new_exp (frag, off, len, exp, 0, r);
7303}
7304
357d1bd8
L		 7305/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7306 purpose of the `.dc.a' internal pseudo-op. */
7307
7308int
7309x86_address_bytes (void)
7310{
7311 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7312 return 4;
7313 return stdoutput->arch_info->bits_per_address / 8;
7314}
7315
d382c579
TG		 7316#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7317 || defined (LEX_AT)
d258b828 7318# define lex_got(reloc, adjust, types) NULL
718ddfc0 7319#else
f3c180ae
AM		 7320/* Parse operands of the form
7321 <symbol>@GOTOFF+<nnn>
7322 and similar .plt or .got references.
7323
7324 If we find one, set up the correct relocation in RELOC and copy the
7325 input string, minus the `@GOTOFF' into a malloc'd buffer for
7326 parsing by the calling routine. Return this buffer, and if ADJUST
7327 is non-null set it to the length of the string we removed from the
7328 input line. Otherwise return NULL. */
7329static char *
91d6fa6a 7330lex_got (enum bfd_reloc_code_real *rel,
64e74474 7331 int *adjust,
d258b828 7332 i386_operand_type *types)
f3c180ae 7333{
7b81dfbb
AJ		 7334 /* Some of the relocations depend on the size of what field is to
7335 be relocated. But in our callers i386_immediate and i386_displacement
7336 we don't yet know the operand size (this will be set by insn
7337 matching). Hence we record the word32 relocation here,
7338 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7339 static const struct {
7340 const char *str;
cff8d58a 7341 int len;
4fa24527 7342 const enum bfd_reloc_code_real rel[2];
40fb9820 7343 const i386_operand_type types64;
f3c180ae 7344 } gotrel[] = {
8ce3d284 7345#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7346 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7347 BFD_RELOC_SIZE32 },
7348 OPERAND_TYPE_IMM32_64 },
8ce3d284 7349#endif
cff8d58a
L		 7350 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7351 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7352 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7353 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7354 BFD_RELOC_X86_64_PLT32 },
40fb9820 7355 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7356 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7357 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7358 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7359 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7360 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7361 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7362 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7363 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7364 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7365 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7366 BFD_RELOC_X86_64_TLSGD },
40fb9820 7367 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7368 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7369 _dummy_first_bfd_reloc_code_real },
40fb9820 7370 OPERAND_TYPE_NONE },
cff8d58a
L		 7371 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7372 BFD_RELOC_X86_64_TLSLD },
40fb9820 7373 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7374 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7375 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7376 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7377 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7378 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7379 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7380 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7381 _dummy_first_bfd_reloc_code_real },
40fb9820 7382 OPERAND_TYPE_NONE },
cff8d58a
L		 7383 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7384 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7385 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7386 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7387 _dummy_first_bfd_reloc_code_real },
40fb9820 7388 OPERAND_TYPE_NONE },
cff8d58a
L		 7389 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7390 _dummy_first_bfd_reloc_code_real },
40fb9820 7391 OPERAND_TYPE_NONE },
cff8d58a
L		 7392 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7393 BFD_RELOC_X86_64_GOT32 },
40fb9820 7394 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7395 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7396 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7397 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7398 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7399 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7400 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7401 };
7402 char *cp;
7403 unsigned int j;
7404
d382c579 7405#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7406 if (!IS_ELF)
7407 return NULL;
d382c579 7408#endif
718ddfc0 7409
f3c180ae 7410 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7411 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7412 return NULL;
7413
47465058 7414 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7415 {
cff8d58a 7416 int len = gotrel[j].len;
28f81592 7417 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7418 {
4fa24527 7419 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7420 {
28f81592
AM		 7421 int first, second;
7422 char *tmpbuf, *past_reloc;
f3c180ae 7423
91d6fa6a 7424 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7425
3956db08
JB		 7426 if (types)
7427 {
7428 if (flag_code != CODE_64BIT)
40fb9820
L		 7429 {
7430 types->bitfield.imm32 = 1;
7431 types->bitfield.disp32 = 1;
7432 }
3956db08
JB		 7433 else
7434 *types = gotrel[j].types64;
7435 }
7436
8fd4256d 7437 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7438 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7439
28f81592 7440 /* The length of the first part of our input line. */
f3c180ae 7441 first = cp - input_line_pointer;
28f81592
AM		 7442
7443 /* The second part goes from after the reloc token until
67c11a9b 7444 (and including) an end_of_line char or comma. */
28f81592 7445 past_reloc = cp + 1 + len;
67c11a9b
AM		 7446 cp = past_reloc;
7447 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7448 ++cp;
7449 second = cp + 1 - past_reloc;
28f81592
AM		 7450
7451 /* Allocate and copy string. The trailing NUL shouldn't
7452 be necessary, but be safe. */
1e9cc1c2 7453 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 7454 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7455 if (second != 0 && *past_reloc != ' ')
7456 /* Replace the relocation token with ' ', so that
7457 errors like foo@GOTOFF1 will be detected. */
7458 tmpbuf[first++] = ' ';
af89796a
L		 7459 else
7460 /* Increment length by 1 if the relocation token is
7461 removed. */
7462 len++;
7463 if (adjust)
7464 *adjust = len;
0787a12d
AM		 7465 memcpy (tmpbuf + first, past_reloc, second);
7466 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7467 return tmpbuf;
7468 }
7469
4fa24527
JB		 7470 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7471 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7472 return NULL;
7473 }
7474 }
7475
7476 /* Might be a symbol version string. Don't as_bad here. */
7477 return NULL;
7478}
4e4f7c87 7479#endif
f3c180ae 7480
a988325c
NC		 7481#ifdef TE_PE
7482#ifdef lex_got
7483#undef lex_got
7484#endif
7485/* Parse operands of the form
7486 <symbol>@SECREL32+<nnn>
7487
7488 If we find one, set up the correct relocation in RELOC and copy the
7489 input string, minus the `@SECREL32' into a malloc'd buffer for
7490 parsing by the calling routine. Return this buffer, and if ADJUST
7491 is non-null set it to the length of the string we removed from the
34bca508
L		 7492 input line. Otherwise return NULL.
7493
a988325c
NC		 7494 This function is copied from the ELF version above adjusted for PE targets. */
7495
7496static char *
7497lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7498 int *adjust ATTRIBUTE_UNUSED,
d258b828 7499 i386_operand_type *types)
a988325c
NC		 7500{
7501 static const struct
7502 {
7503 const char *str;
7504 int len;
7505 const enum bfd_reloc_code_real rel[2];
7506 const i386_operand_type types64;
7507 }
7508 gotrel[] =
7509 {
7510 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7511 BFD_RELOC_32_SECREL },
7512 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7513 };
7514
7515 char *cp;
7516 unsigned j;
7517
7518 for (cp = input_line_pointer; *cp != '@'; cp++)
7519 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7520 return NULL;
7521
7522 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7523 {
7524 int len = gotrel[j].len;
7525
7526 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7527 {
7528 if (gotrel[j].rel[object_64bit] != 0)
7529 {
7530 int first, second;
7531 char *tmpbuf, *past_reloc;
7532
7533 *rel = gotrel[j].rel[object_64bit];
7534 if (adjust)
7535 *adjust = len;
7536
7537 if (types)
7538 {
7539 if (flag_code != CODE_64BIT)
7540 {
7541 types->bitfield.imm32 = 1;
7542 types->bitfield.disp32 = 1;
7543 }
7544 else
7545 *types = gotrel[j].types64;
7546 }
7547
7548 /* The length of the first part of our input line. */
7549 first = cp - input_line_pointer;
7550
7551 /* The second part goes from after the reloc token until
7552 (and including) an end_of_line char or comma. */
7553 past_reloc = cp + 1 + len;
7554 cp = past_reloc;
7555 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7556 ++cp;
7557 second = cp + 1 - past_reloc;
7558
7559 /* Allocate and copy string. The trailing NUL shouldn't
7560 be necessary, but be safe. */
7561 tmpbuf = (char *) xmalloc (first + second + 2);
7562 memcpy (tmpbuf, input_line_pointer, first);
7563 if (second != 0 && *past_reloc != ' ')
7564 /* Replace the relocation token with ' ', so that
7565 errors like foo@SECLREL321 will be detected. */
7566 tmpbuf[first++] = ' ';
7567 memcpy (tmpbuf + first, past_reloc, second);
7568 tmpbuf[first + second] = '\0';
7569 return tmpbuf;
7570 }
7571
7572 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7573 gotrel[j].str, 1 << (5 + object_64bit));
7574 return NULL;
7575 }
7576 }
7577
7578 /* Might be a symbol version string. Don't as_bad here. */
7579 return NULL;
7580}
7581
7582#endif /* TE_PE */
7583
62ebcb5c 7584bfd_reloc_code_real_type
e3bb37b5 7585x86_cons (expressionS *exp, int size)
f3c180ae 7586{
62ebcb5c
AM		 7587 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7588
ee86248c
JB		 7589 intel_syntax = -intel_syntax;
7590
3c7b9c2c 7591 exp->X_md = 0;
4fa24527 7592 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7593 {
7594 /* Handle @GOTOFF and the like in an expression. */
7595 char *save;
7596 char *gotfree_input_line;
4a57f2cf 7597 int adjust = 0;
f3c180ae
AM		 7598
7599 save = input_line_pointer;
d258b828 7600 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 7601 if (gotfree_input_line)
7602 input_line_pointer = gotfree_input_line;
7603
7604 expression (exp);
7605
7606 if (gotfree_input_line)
7607 {
7608 /* expression () has merrily parsed up to the end of line,
7609 or a comma - in the wrong buffer. Transfer how far
7610 input_line_pointer has moved to the right buffer. */
7611 input_line_pointer = (save
7612 + (input_line_pointer - gotfree_input_line)
7613 + adjust);
7614 free (gotfree_input_line);
3992d3b7
AM		 7615 if (exp->X_op == O_constant
7616 || exp->X_op == O_absent
7617 || exp->X_op == O_illegal
0398aac5 7618 || exp->X_op == O_register
3992d3b7
AM		 7619 || exp->X_op == O_big)
7620 {
7621 char c = *input_line_pointer;
7622 *input_line_pointer = 0;
7623 as_bad (_("missing or invalid expression `%s'"), save);
7624 *input_line_pointer = c;
7625 }
f3c180ae
AM		 7626 }
7627 }
7628 else
7629 expression (exp);
ee86248c
JB		 7630
7631 intel_syntax = -intel_syntax;
7632
7633 if (intel_syntax)
7634 i386_intel_simplify (exp);
62ebcb5c
AM		 7635
7636 return got_reloc;
f3c180ae 7637}
f3c180ae 7638
9f32dd5b
L		 7639static void
7640signed_cons (int size)
6482c264 7641{
d182319b
JB		 7642 if (flag_code == CODE_64BIT)
7643 cons_sign = 1;
7644 cons (size);
7645 cons_sign = -1;
6482c264
NC		 7646}
7647
d182319b 7648#ifdef TE_PE
6482c264 7649static void
7016a5d5 7650pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7651{
7652 expressionS exp;
7653
7654 do
7655 {
7656 expression (&exp);
7657 if (exp.X_op == O_symbol)
7658 exp.X_op = O_secrel;
7659
7660 emit_expr (&exp, 4);
7661 }
7662 while (*input_line_pointer++ == ',');
7663
7664 input_line_pointer--;
7665 demand_empty_rest_of_line ();
7666}
6482c264
NC		 7667#endif
7668
43234a1e
L		 7669/* Handle Vector operations. */
7670
7671static char *
7672check_VecOperations (char *op_string, char *op_end)
7673{
7674 const reg_entry *mask;
7675 const char *saved;
7676 char *end_op;
7677
7678 while (*op_string
7679 && (op_end == NULL || op_string < op_end))
7680 {
7681 saved = op_string;
7682 if (*op_string == '{')
7683 {
7684 op_string++;
7685
7686 /* Check broadcasts. */
7687 if (strncmp (op_string, "1to", 3) == 0)
7688 {
7689 int bcst_type;
7690
7691 if (i.broadcast)
7692 goto duplicated_vec_op;
7693
7694 op_string += 3;
7695 if (*op_string == '8')
7696 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 7697 else if (*op_string == '4')
7698 bcst_type = BROADCAST_1TO4;
7699 else if (*op_string == '2')
7700 bcst_type = BROADCAST_1TO2;
43234a1e
L		 7701 else if (*op_string == '1'
7702 && *(op_string+1) == '6')
7703 {
7704 bcst_type = BROADCAST_1TO16;
7705 op_string++;
7706 }
7707 else
7708 {
7709 as_bad (_("Unsupported broadcast: `%s'"), saved);
7710 return NULL;
7711 }
7712 op_string++;
7713
7714 broadcast_op.type = bcst_type;
7715 broadcast_op.operand = this_operand;
7716 i.broadcast = &broadcast_op;
7717 }
7718 /* Check masking operation. */
7719 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7720 {
7721 /* k0 can't be used for write mask. */
7722 if (mask->reg_num == 0)
7723 {
7724 as_bad (_("`%s' can't be used for write mask"),
7725 op_string);
7726 return NULL;
7727 }
7728
7729 if (!i.mask)
7730 {
7731 mask_op.mask = mask;
7732 mask_op.zeroing = 0;
7733 mask_op.operand = this_operand;
7734 i.mask = &mask_op;
7735 }
7736 else
7737 {
7738 if (i.mask->mask)
7739 goto duplicated_vec_op;
7740
7741 i.mask->mask = mask;
7742
7743 /* Only "{z}" is allowed here. No need to check
7744 zeroing mask explicitly. */
7745 if (i.mask->operand != this_operand)
7746 {
7747 as_bad (_("invalid write mask `%s'"), saved);
7748 return NULL;
7749 }
7750 }
7751
7752 op_string = end_op;
7753 }
7754 /* Check zeroing-flag for masking operation. */
7755 else if (*op_string == 'z')
7756 {
7757 if (!i.mask)
7758 {
7759 mask_op.mask = NULL;
7760 mask_op.zeroing = 1;
7761 mask_op.operand = this_operand;
7762 i.mask = &mask_op;
7763 }
7764 else
7765 {
7766 if (i.mask->zeroing)
7767 {
7768 duplicated_vec_op:
7769 as_bad (_("duplicated `%s'"), saved);
7770 return NULL;
7771 }
7772
7773 i.mask->zeroing = 1;
7774
7775 /* Only "{%k}" is allowed here. No need to check mask
7776 register explicitly. */
7777 if (i.mask->operand != this_operand)
7778 {
7779 as_bad (_("invalid zeroing-masking `%s'"),
7780 saved);
7781 return NULL;
7782 }
7783 }
7784
7785 op_string++;
7786 }
7787 else
7788 goto unknown_vec_op;
7789
7790 if (*op_string != '}')
7791 {
7792 as_bad (_("missing `}' in `%s'"), saved);
7793 return NULL;
7794 }
7795 op_string++;
7796 continue;
7797 }
7798 unknown_vec_op:
7799 /* We don't know this one. */
7800 as_bad (_("unknown vector operation: `%s'"), saved);
7801 return NULL;
7802 }
7803
7804 return op_string;
7805}
7806
252b5132 7807static int
70e41ade 7808i386_immediate (char *imm_start)
252b5132
RH		 7809{
7810 char *save_input_line_pointer;
f3c180ae 7811 char *gotfree_input_line;
252b5132 7812 segT exp_seg = 0;
47926f60 7813 expressionS *exp;
40fb9820
L		 7814 i386_operand_type types;
7815
0dfbf9d7 7816 operand_type_set (&types, ~0);
252b5132
RH		 7817
7818 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7819 {
31b2323c
L		 7820 as_bad (_("at most %d immediate operands are allowed"),
7821 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 7822 return 0;
7823 }
7824
7825 exp = &im_expressions[i.imm_operands++];
520dc8e8 7826 i.op[this_operand].imms = exp;
252b5132
RH		 7827
7828 if (is_space_char (*imm_start))
7829 ++imm_start;
7830
7831 save_input_line_pointer = input_line_pointer;
7832 input_line_pointer = imm_start;
7833
d258b828 7834 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 7835 if (gotfree_input_line)
7836 input_line_pointer = gotfree_input_line;
252b5132
RH		 7837
7838 exp_seg = expression (exp);
7839
83183c0c 7840 SKIP_WHITESPACE ();
43234a1e
L		 7841
7842 /* Handle vector operations. */
7843 if (*input_line_pointer == '{')
7844 {
7845 input_line_pointer = check_VecOperations (input_line_pointer,
7846 NULL);
7847 if (input_line_pointer == NULL)
7848 return 0;
7849 }
7850
252b5132 7851 if (*input_line_pointer)
f3c180ae 7852 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 7853
7854 input_line_pointer = save_input_line_pointer;
f3c180ae 7855 if (gotfree_input_line)
ee86248c
JB		 7856 {
7857 free (gotfree_input_line);
7858
7859 if (exp->X_op == O_constant || exp->X_op == O_register)
7860 exp->X_op = O_illegal;
7861 }
7862
7863 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7864}
252b5132 7865
ee86248c
JB		 7866static int
7867i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7868 i386_operand_type types, const char *imm_start)
7869{
7870 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 7871 {
313c53d1
L		 7872 if (imm_start)
7873 as_bad (_("missing or invalid immediate expression `%s'"),
7874 imm_start);
3992d3b7 7875 return 0;
252b5132 7876 }
3e73aa7c 7877 else if (exp->X_op == O_constant)
252b5132 7878 {
47926f60 7879 /* Size it properly later. */
40fb9820 7880 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 7881 /* If not 64bit, sign extend val. */
7882 if (flag_code != CODE_64BIT
4eed87de
AM		 7883 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7884 exp->X_add_number
7885 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 7886 }
4c63da97 7887#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 7888 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 7889 && exp_seg != absolute_section
47926f60 7890 && exp_seg != text_section
24eab124
AM		 7891 && exp_seg != data_section
7892 && exp_seg != bss_section
7893 && exp_seg != undefined_section
f86103b7 7894 && !bfd_is_com_section (exp_seg))
252b5132 7895 {
d0b47220 7896 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 7897 return 0;
7898 }
7899#endif
a841bdf5 7900 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 7901 {
313c53d1
L		 7902 if (imm_start)
7903 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 7904 return 0;
7905 }
252b5132
RH		 7906 else
7907 {
7908 /* This is an address. The size of the address will be
24eab124 7909 determined later, depending on destination register,
3e73aa7c 7910 suffix, or the default for the section. */
40fb9820
L		 7911 i.types[this_operand].bitfield.imm8 = 1;
7912 i.types[this_operand].bitfield.imm16 = 1;
7913 i.types[this_operand].bitfield.imm32 = 1;
7914 i.types[this_operand].bitfield.imm32s = 1;
7915 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 7916 i.types[this_operand] = operand_type_and (i.types[this_operand],
7917 types);
252b5132
RH		 7918 }
7919
7920 return 1;
7921}
7922
551c1ca1 7923static char *
e3bb37b5 7924i386_scale (char *scale)
252b5132 7925{
551c1ca1
AM		 7926 offsetT val;
7927 char *save = input_line_pointer;
252b5132 7928
551c1ca1
AM		 7929 input_line_pointer = scale;
7930 val = get_absolute_expression ();
7931
7932 switch (val)
252b5132 7933 {
551c1ca1 7934 case 1:
252b5132
RH		 7935 i.log2_scale_factor = 0;
7936 break;
551c1ca1 7937 case 2:
252b5132
RH		 7938 i.log2_scale_factor = 1;
7939 break;
551c1ca1 7940 case 4:
252b5132
RH		 7941 i.log2_scale_factor = 2;
7942 break;
551c1ca1 7943 case 8:
252b5132
RH		 7944 i.log2_scale_factor = 3;
7945 break;
7946 default:
a724f0f4
JB		 7947 {
7948 char sep = *input_line_pointer;
7949
7950 *input_line_pointer = '\0';
7951 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
7952 scale);
7953 *input_line_pointer = sep;
7954 input_line_pointer = save;
7955 return NULL;
7956 }
252b5132 7957 }
29b0f896 7958 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 7959 {
7960 as_warn (_("scale factor of %d without an index register"),
24eab124 7961 1 << i.log2_scale_factor);
252b5132 7962 i.log2_scale_factor = 0;
252b5132 7963 }
551c1ca1
AM		 7964 scale = input_line_pointer;
7965 input_line_pointer = save;
7966 return scale;
252b5132
RH		 7967}
7968
252b5132 7969static int
e3bb37b5 7970i386_displacement (char *disp_start, char *disp_end)
252b5132 7971{
29b0f896 7972 expressionS *exp;
252b5132
RH		 7973 segT exp_seg = 0;
7974 char *save_input_line_pointer;
f3c180ae 7975 char *gotfree_input_line;
40fb9820
L		 7976 int override;
7977 i386_operand_type bigdisp, types = anydisp;
3992d3b7 7978 int ret;
252b5132 7979
31b2323c
L		 7980 if (i.disp_operands == MAX_MEMORY_OPERANDS)
7981 {
7982 as_bad (_("at most %d displacement operands are allowed"),
7983 MAX_MEMORY_OPERANDS);
7984 return 0;
7985 }
7986
0dfbf9d7 7987 operand_type_set (&bigdisp, 0);
40fb9820
L		 7988 if ((i.types[this_operand].bitfield.jumpabsolute)
7989 || (!current_templates->start->opcode_modifier.jump
7990 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 7991 {
40fb9820 7992 bigdisp.bitfield.disp32 = 1;
e05278af 7993 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 7994 if (flag_code == CODE_64BIT)
7995 {
7996 if (!override)
7997 {
7998 bigdisp.bitfield.disp32s = 1;
7999 bigdisp.bitfield.disp64 = 1;
8000 }
8001 }
8002 else if ((flag_code == CODE_16BIT) ^ override)
8003 {
8004 bigdisp.bitfield.disp32 = 0;
8005 bigdisp.bitfield.disp16 = 1;
8006 }
e05278af
JB		 8007 }
8008 else
8009 {
8010 /* For PC-relative branches, the width of the displacement
8011 is dependent upon data size, not address size. */
e05278af 8012 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8013 if (flag_code == CODE_64BIT)
8014 {
8015 if (override || i.suffix == WORD_MNEM_SUFFIX)
8016 bigdisp.bitfield.disp16 = 1;
8017 else
8018 {
8019 bigdisp.bitfield.disp32 = 1;
8020 bigdisp.bitfield.disp32s = 1;
8021 }
8022 }
8023 else
e05278af
JB		 8024 {
8025 if (!override)
8026 override = (i.suffix == (flag_code != CODE_16BIT
8027 ? WORD_MNEM_SUFFIX
8028 : LONG_MNEM_SUFFIX));
40fb9820
L		 8029 bigdisp.bitfield.disp32 = 1;
8030 if ((flag_code == CODE_16BIT) ^ override)
8031 {
8032 bigdisp.bitfield.disp32 = 0;
8033 bigdisp.bitfield.disp16 = 1;
8034 }
e05278af 8035 }
e05278af 8036 }
c6fb90c8
L		 8037 i.types[this_operand] = operand_type_or (i.types[this_operand],
8038 bigdisp);
252b5132
RH		 8039
8040 exp = &disp_expressions[i.disp_operands];
520dc8e8 8041 i.op[this_operand].disps = exp;
252b5132
RH		 8042 i.disp_operands++;
8043 save_input_line_pointer = input_line_pointer;
8044 input_line_pointer = disp_start;
8045 END_STRING_AND_SAVE (disp_end);
8046
8047#ifndef GCC_ASM_O_HACK
8048#define GCC_ASM_O_HACK 0
8049#endif
8050#if GCC_ASM_O_HACK
8051 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8052 if (i.types[this_operand].bitfield.baseIndex
24eab124 8053 && displacement_string_end[-1] == '+')
252b5132
RH		 8054 {
8055 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8056 constraint within gcc asm statements.
8057 For instance:
8058
8059 #define _set_tssldt_desc(n,addr,limit,type) \
8060 __asm__ __volatile__ ( \
8061 "movw %w2,%0\n\t" \
8062 "movw %w1,2+%0\n\t" \
8063 "rorl $16,%1\n\t" \
8064 "movb %b1,4+%0\n\t" \
8065 "movb %4,5+%0\n\t" \
8066 "movb $0,6+%0\n\t" \
8067 "movb %h1,7+%0\n\t" \
8068 "rorl $16,%1" \
8069 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8070
8071 This works great except that the output assembler ends
8072 up looking a bit weird if it turns out that there is
8073 no offset. You end up producing code that looks like:
8074
8075 #APP
8076 movw $235,(%eax)
8077 movw %dx,2+(%eax)
8078 rorl $16,%edx
8079 movb %dl,4+(%eax)
8080 movb $137,5+(%eax)
8081 movb $0,6+(%eax)
8082 movb %dh,7+(%eax)
8083 rorl $16,%edx
8084 #NO_APP
8085
47926f60 8086 So here we provide the missing zero. */
24eab124
AM		 8087
8088 *displacement_string_end = '0';
252b5132
RH		 8089 }
8090#endif
d258b828 8091 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8092 if (gotfree_input_line)
8093 input_line_pointer = gotfree_input_line;
252b5132 8094
24eab124 8095 exp_seg = expression (exp);
252b5132 8096
636c26b0
AM		 8097 SKIP_WHITESPACE ();
8098 if (*input_line_pointer)
8099 as_bad (_("junk `%s' after expression"), input_line_pointer);
8100#if GCC_ASM_O_HACK
8101 RESTORE_END_STRING (disp_end + 1);
8102#endif
636c26b0 8103 input_line_pointer = save_input_line_pointer;
636c26b0 8104 if (gotfree_input_line)
ee86248c
JB		 8105 {
8106 free (gotfree_input_line);
8107
8108 if (exp->X_op == O_constant || exp->X_op == O_register)
8109 exp->X_op = O_illegal;
8110 }
8111
8112 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8113
8114 RESTORE_END_STRING (disp_end);
8115
8116 return ret;
8117}
8118
8119static int
8120i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8121 i386_operand_type types, const char *disp_start)
8122{
8123 i386_operand_type bigdisp;
8124 int ret = 1;
636c26b0 8125
24eab124
AM		 8126 /* We do this to make sure that the section symbol is in
8127 the symbol table. We will ultimately change the relocation
47926f60 8128 to be relative to the beginning of the section. */
1ae12ab7 8129 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8130 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8131 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8132 {
636c26b0 8133 if (exp->X_op != O_symbol)
3992d3b7 8134 goto inv_disp;
636c26b0 8135
e5cb08ac 8136 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8137 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8138 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8139 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8140 exp->X_op = O_subtract;
8141 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8142 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8143 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8144 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8145 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8146 else
29b0f896 8147 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8148 }
252b5132 8149
3992d3b7
AM		 8150 else if (exp->X_op == O_absent
8151 || exp->X_op == O_illegal
ee86248c 8152 || exp->X_op == O_big)
2daf4fd8 8153 {
3992d3b7
AM		 8154 inv_disp:
8155 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8156 disp_start);
3992d3b7 8157 ret = 0;
2daf4fd8
AM		 8158 }
8159
0e1147d9
L		 8160 else if (flag_code == CODE_64BIT
8161 && !i.prefix[ADDR_PREFIX]
8162 && exp->X_op == O_constant)
8163 {
8164 /* Since displacement is signed extended to 64bit, don't allow
8165 disp32 and turn off disp32s if they are out of range. */
8166 i.types[this_operand].bitfield.disp32 = 0;
8167 if (!fits_in_signed_long (exp->X_add_number))
8168 {
8169 i.types[this_operand].bitfield.disp32s = 0;
8170 if (i.types[this_operand].bitfield.baseindex)
8171 {
8172 as_bad (_("0x%lx out range of signed 32bit displacement"),
8173 (long) exp->X_add_number);
8174 ret = 0;
8175 }
8176 }
8177 }
8178
4c63da97 8179#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8180 else if (exp->X_op != O_constant
8181 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8182 && exp_seg != absolute_section
8183 && exp_seg != text_section
8184 && exp_seg != data_section
8185 && exp_seg != bss_section
8186 && exp_seg != undefined_section
8187 && !bfd_is_com_section (exp_seg))
24eab124 8188 {
d0b47220 8189 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8190 ret = 0;
24eab124 8191 }
252b5132 8192#endif
3956db08 8193
40fb9820
L		 8194 /* Check if this is a displacement only operand. */
8195 bigdisp = i.types[this_operand];
8196 bigdisp.bitfield.disp8 = 0;
8197 bigdisp.bitfield.disp16 = 0;
8198 bigdisp.bitfield.disp32 = 0;
8199 bigdisp.bitfield.disp32s = 0;
8200 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8201 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8202 i.types[this_operand] = operand_type_and (i.types[this_operand],
8203 types);
3956db08 8204
3992d3b7 8205 return ret;
252b5132
RH		 8206}
8207
eecb386c 8208/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8209 Return 1 on success, 0 on a failure. */
8210
252b5132 8211static int
e3bb37b5 8212i386_index_check (const char *operand_string)
252b5132 8213{
fc0763e6 8214 const char *kind = "base/index";
be05d201
L		 8215 enum flag_code addr_mode;
8216
8217 if (i.prefix[ADDR_PREFIX])
8218 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8219 else
8220 {
8221 addr_mode = flag_code;
8222
24eab124 8223#if INFER_ADDR_PREFIX
be05d201
L		 8224 if (i.mem_operands == 0)
8225 {
8226 /* Infer address prefix from the first memory operand. */
8227 const reg_entry *addr_reg = i.base_reg;
8228
8229 if (addr_reg == NULL)
8230 addr_reg = i.index_reg;
eecb386c 8231
be05d201
L		 8232 if (addr_reg)
8233 {
8234 if (addr_reg->reg_num == RegEip
8235 || addr_reg->reg_num == RegEiz
8236 || addr_reg->reg_type.bitfield.reg32)
8237 addr_mode = CODE_32BIT;
8238 else if (flag_code != CODE_64BIT
8239 && addr_reg->reg_type.bitfield.reg16)
8240 addr_mode = CODE_16BIT;
8241
8242 if (addr_mode != flag_code)
8243 {
8244 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8245 i.prefixes += 1;
8246 /* Change the size of any displacement too. At most one
8247 of Disp16 or Disp32 is set.
8248 FIXME. There doesn't seem to be any real need for
8249 separate Disp16 and Disp32 flags. The same goes for
8250 Imm16 and Imm32. Removing them would probably clean
8251 up the code quite a lot. */
8252 if (flag_code != CODE_64BIT
8253 && (i.types[this_operand].bitfield.disp16
8254 || i.types[this_operand].bitfield.disp32))
8255 i.types[this_operand]
8256 = operand_type_xor (i.types[this_operand], disp16_32);
8257 }
8258 }
8259 }
24eab124 8260#endif
be05d201
L		 8261 }
8262
fc0763e6
JB		 8263 if (current_templates->start->opcode_modifier.isstring
8264 && !current_templates->start->opcode_modifier.immext
8265 && (current_templates->end[-1].opcode_modifier.isstring
8266 || i.mem_operands))
8267 {
8268 /* Memory operands of string insns are special in that they only allow
8269 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8270 const reg_entry *expected_reg;
8271 static const char *di_si[][2] =
8272 {
8273 { "esi", "edi" },
8274 { "si", "di" },
8275 { "rsi", "rdi" }
8276 };
8277 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8278
8279 kind = "string address";
8280
8281 if (current_templates->start->opcode_modifier.w)
8282 {
8283 i386_operand_type type = current_templates->end[-1].operand_types[0];
8284
8285 if (!type.bitfield.baseindex
8286 || ((!i.mem_operands != !intel_syntax)
8287 && current_templates->end[-1].operand_types[1]
8288 .bitfield.baseindex))
8289 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8290 expected_reg = hash_find (reg_hash,
8291 di_si[addr_mode][type.bitfield.esseg]);
8292
fc0763e6
JB		 8293 }
8294 else
be05d201 8295 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8296
be05d201
L		 8297 if (i.base_reg != expected_reg
8298 || i.index_reg
fc0763e6 8299 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8300 {
be05d201
L		 8301 /* The second memory operand must have the same size as
8302 the first one. */
8303 if (i.mem_operands
8304 && i.base_reg
8305 && !((addr_mode == CODE_64BIT
8306 && i.base_reg->reg_type.bitfield.reg64)
8307 || (addr_mode == CODE_32BIT
8308 ? i.base_reg->reg_type.bitfield.reg32
8309 : i.base_reg->reg_type.bitfield.reg16)))
8310 goto bad_address;
8311
fc0763e6
JB		 8312 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8313 operand_string,
8314 intel_syntax ? '[' : '(',
8315 register_prefix,
be05d201 8316 expected_reg->reg_name,
fc0763e6 8317 intel_syntax ? ']' : ')');
be05d201 8318 return 1;
fc0763e6 8319 }
be05d201
L		 8320 else
8321 return 1;
8322
8323bad_address:
8324 as_bad (_("`%s' is not a valid %s expression"),
8325 operand_string, kind);
8326 return 0;
3e73aa7c
JH		 8327 }
8328 else
8329 {
be05d201
L		 8330 if (addr_mode != CODE_16BIT)
8331 {
8332 /* 32-bit/64-bit checks. */
8333 if ((i.base_reg
8334 && (addr_mode == CODE_64BIT
8335 ? !i.base_reg->reg_type.bitfield.reg64
8336 : !i.base_reg->reg_type.bitfield.reg32)
8337 && (i.index_reg
8338 || (i.base_reg->reg_num
8339 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8340 || (i.index_reg
8341 && !i.index_reg->reg_type.bitfield.regxmm
8342 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8343 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8344 && ((addr_mode == CODE_64BIT
8345 ? !(i.index_reg->reg_type.bitfield.reg64
8346 || i.index_reg->reg_num == RegRiz)
8347 : !(i.index_reg->reg_type.bitfield.reg32
8348 || i.index_reg->reg_num == RegEiz))
8349 || !i.index_reg->reg_type.bitfield.baseindex)))
8350 goto bad_address;
8351 }
8352 else
3e73aa7c 8353 {
be05d201 8354 /* 16-bit checks. */
3e73aa7c 8355 if ((i.base_reg
40fb9820
L		 8356 && (!i.base_reg->reg_type.bitfield.reg16
8357 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8358 || (i.index_reg
40fb9820
L		 8359 && (!i.index_reg->reg_type.bitfield.reg16
8360 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8361 || !(i.base_reg
8362 && i.base_reg->reg_num < 6
8363 && i.index_reg->reg_num >= 6
8364 && i.log2_scale_factor == 0))))
be05d201 8365 goto bad_address;
3e73aa7c
JH		 8366 }
8367 }
be05d201 8368 return 1;
24eab124 8369}
252b5132 8370
43234a1e
L		 8371/* Handle vector immediates. */
8372
8373static int
8374RC_SAE_immediate (const char *imm_start)
8375{
8376 unsigned int match_found, j;
8377 const char *pstr = imm_start;
8378 expressionS *exp;
8379
8380 if (*pstr != '{')
8381 return 0;
8382
8383 pstr++;
8384 match_found = 0;
8385 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8386 {
8387 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8388 {
8389 if (!i.rounding)
8390 {
8391 rc_op.type = RC_NamesTable[j].type;
8392 rc_op.operand = this_operand;
8393 i.rounding = &rc_op;
8394 }
8395 else
8396 {
8397 as_bad (_("duplicated `%s'"), imm_start);
8398 return 0;
8399 }
8400 pstr += RC_NamesTable[j].len;
8401 match_found = 1;
8402 break;
8403 }
8404 }
8405 if (!match_found)
8406 return 0;
8407
8408 if (*pstr++ != '}')
8409 {
8410 as_bad (_("Missing '}': '%s'"), imm_start);
8411 return 0;
8412 }
8413 /* RC/SAE immediate string should contain nothing more. */;
8414 if (*pstr != 0)
8415 {
8416 as_bad (_("Junk after '}': '%s'"), imm_start);
8417 return 0;
8418 }
8419
8420 exp = &im_expressions[i.imm_operands++];
8421 i.op[this_operand].imms = exp;
8422
8423 exp->X_op = O_constant;
8424 exp->X_add_number = 0;
8425 exp->X_add_symbol = (symbolS *) 0;
8426 exp->X_op_symbol = (symbolS *) 0;
8427
8428 i.types[this_operand].bitfield.imm8 = 1;
8429 return 1;
8430}
8431
fc0763e6 8432/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8433 on error. */
252b5132 8434
252b5132 8435static int
a7619375 8436i386_att_operand (char *operand_string)
252b5132 8437{
af6bdddf
AM		 8438 const reg_entry *r;
8439 char *end_op;
24eab124 8440 char *op_string = operand_string;
252b5132 8441
24eab124 8442 if (is_space_char (*op_string))
252b5132
RH		 8443 ++op_string;
8444
24eab124 8445 /* We check for an absolute prefix (differentiating,
47926f60 8446 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8447 if (*op_string == ABSOLUTE_PREFIX)
8448 {
8449 ++op_string;
8450 if (is_space_char (*op_string))
8451 ++op_string;
40fb9820 8452 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8453 }
252b5132 8454
47926f60 8455 /* Check if operand is a register. */
4d1bb795 8456 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8457 {
40fb9820
L		 8458 i386_operand_type temp;
8459
24eab124
AM		 8460 /* Check for a segment override by searching for ':' after a
8461 segment register. */
8462 op_string = end_op;
8463 if (is_space_char (*op_string))
8464 ++op_string;
40fb9820
L		 8465 if (*op_string == ':'
8466 && (r->reg_type.bitfield.sreg2
8467 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8468 {
8469 switch (r->reg_num)
8470 {
8471 case 0:
8472 i.seg[i.mem_operands] = &es;
8473 break;
8474 case 1:
8475 i.seg[i.mem_operands] = &cs;
8476 break;
8477 case 2:
8478 i.seg[i.mem_operands] = &ss;
8479 break;
8480 case 3:
8481 i.seg[i.mem_operands] = &ds;
8482 break;
8483 case 4:
8484 i.seg[i.mem_operands] = &fs;
8485 break;
8486 case 5:
8487 i.seg[i.mem_operands] = &gs;
8488 break;
8489 }
252b5132 8490
24eab124 8491 /* Skip the ':' and whitespace. */
252b5132
RH		 8492 ++op_string;
8493 if (is_space_char (*op_string))
24eab124 8494 ++op_string;
252b5132 8495
24eab124
AM		 8496 if (!is_digit_char (*op_string)
8497 && !is_identifier_char (*op_string)
8498 && *op_string != '('
8499 && *op_string != ABSOLUTE_PREFIX)
8500 {
8501 as_bad (_("bad memory operand `%s'"), op_string);
8502 return 0;
8503 }
47926f60 8504 /* Handle case of %es:*foo. */
24eab124
AM		 8505 if (*op_string == ABSOLUTE_PREFIX)
8506 {
8507 ++op_string;
8508 if (is_space_char (*op_string))
8509 ++op_string;
40fb9820 8510 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8511 }
8512 goto do_memory_reference;
8513 }
43234a1e
L		 8514
8515 /* Handle vector operations. */
8516 if (*op_string == '{')
8517 {
8518 op_string = check_VecOperations (op_string, NULL);
8519 if (op_string == NULL)
8520 return 0;
8521 }
8522
24eab124
AM		 8523 if (*op_string)
8524 {
d0b47220 8525 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8526 return 0;
8527 }
40fb9820
L		 8528 temp = r->reg_type;
8529 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8530 i.types[this_operand] = operand_type_or (i.types[this_operand],
8531 temp);
7d5e4556 8532 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8533 i.op[this_operand].regs = r;
24eab124
AM		 8534 i.reg_operands++;
8535 }
af6bdddf
AM		 8536 else if (*op_string == REGISTER_PREFIX)
8537 {
8538 as_bad (_("bad register name `%s'"), op_string);
8539 return 0;
8540 }
24eab124 8541 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8542 {
24eab124 8543 ++op_string;
40fb9820 8544 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8545 {
d0b47220 8546 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8547 return 0;
8548 }
8549 if (!i386_immediate (op_string))
8550 return 0;
8551 }
43234a1e
L		 8552 else if (RC_SAE_immediate (operand_string))
8553 {
8554 /* If it is a RC or SAE immediate, do nothing. */
8555 ;
8556 }
24eab124
AM		 8557 else if (is_digit_char (*op_string)
8558 || is_identifier_char (*op_string)
e5cb08ac 8559 || *op_string == '(')
24eab124 8560 {
47926f60 8561 /* This is a memory reference of some sort. */
af6bdddf 8562 char *base_string;
252b5132 8563
47926f60 8564 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8565 char *displacement_string_start;
8566 char *displacement_string_end;
43234a1e 8567 char *vop_start;
252b5132 8568
24eab124 8569 do_memory_reference:
24eab124 8570 if ((i.mem_operands == 1
40fb9820 8571 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8572 || i.mem_operands == 2)
8573 {
8574 as_bad (_("too many memory references for `%s'"),
8575 current_templates->start->name);
8576 return 0;
8577 }
252b5132 8578
24eab124
AM		 8579 /* Check for base index form. We detect the base index form by
8580 looking for an ')' at the end of the operand, searching
8581 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8582 after the '('. */
af6bdddf 8583 base_string = op_string + strlen (op_string);
c3332e24 8584
43234a1e
L		 8585 /* Handle vector operations. */
8586 vop_start = strchr (op_string, '{');
8587 if (vop_start && vop_start < base_string)
8588 {
8589 if (check_VecOperations (vop_start, base_string) == NULL)
8590 return 0;
8591 base_string = vop_start;
8592 }
8593
af6bdddf
AM		 8594 --base_string;
8595 if (is_space_char (*base_string))
8596 --base_string;
252b5132 8597
47926f60 8598 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8599 displacement_string_start = op_string;
8600 displacement_string_end = base_string + 1;
252b5132 8601
24eab124
AM		 8602 if (*base_string == ')')
8603 {
af6bdddf 8604 char *temp_string;
24eab124
AM		 8605 unsigned int parens_balanced = 1;
8606 /* We've already checked that the number of left & right ()'s are
47926f60 8607 equal, so this loop will not be infinite. */
24eab124
AM		 8608 do
8609 {
8610 base_string--;
8611 if (*base_string == ')')
8612 parens_balanced++;
8613 if (*base_string == '(')
8614 parens_balanced--;
8615 }
8616 while (parens_balanced);
c3332e24 8617
af6bdddf 8618 temp_string = base_string;
c3332e24 8619
24eab124 8620 /* Skip past '(' and whitespace. */
252b5132
RH		 8621 ++base_string;
8622 if (is_space_char (*base_string))
24eab124 8623 ++base_string;
252b5132 8624
af6bdddf 8625 if (*base_string == ','
4eed87de
AM		 8626 || ((i.base_reg = parse_register (base_string, &end_op))
8627 != NULL))
252b5132 8628 {
af6bdddf 8629 displacement_string_end = temp_string;
252b5132 8630
40fb9820 8631 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8632
af6bdddf 8633 if (i.base_reg)
24eab124 8634 {
24eab124
AM		 8635 base_string = end_op;
8636 if (is_space_char (*base_string))
8637 ++base_string;
af6bdddf
AM		 8638 }
8639
8640 /* There may be an index reg or scale factor here. */
8641 if (*base_string == ',')
8642 {
8643 ++base_string;
8644 if (is_space_char (*base_string))
8645 ++base_string;
8646
4eed87de
AM		 8647 if ((i.index_reg = parse_register (base_string, &end_op))
8648 != NULL)
24eab124 8649 {
af6bdddf 8650 base_string = end_op;
24eab124
AM		 8651 if (is_space_char (*base_string))
8652 ++base_string;
af6bdddf
AM		 8653 if (*base_string == ',')
8654 {
8655 ++base_string;
8656 if (is_space_char (*base_string))
8657 ++base_string;
8658 }
e5cb08ac 8659 else if (*base_string != ')')
af6bdddf 8660 {
4eed87de
AM		 8661 as_bad (_("expecting `,' or `)' "
8662 "after index register in `%s'"),
af6bdddf
AM		 8663 operand_string);
8664 return 0;
8665 }
24eab124 8666 }
af6bdddf 8667 else if (*base_string == REGISTER_PREFIX)
24eab124 8668 {
f76bf5e0
L		 8669 end_op = strchr (base_string, ',');
8670 if (end_op)
8671 *end_op = '\0';
af6bdddf 8672 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8673 return 0;
8674 }
252b5132 8675
47926f60 8676 /* Check for scale factor. */
551c1ca1 8677 if (*base_string != ')')
af6bdddf 8678 {
551c1ca1
AM		 8679 char *end_scale = i386_scale (base_string);
8680
8681 if (!end_scale)
af6bdddf 8682 return 0;
24eab124 8683
551c1ca1 8684 base_string = end_scale;
af6bdddf
AM		 8685 if (is_space_char (*base_string))
8686 ++base_string;
8687 if (*base_string != ')')
8688 {
4eed87de
AM		 8689 as_bad (_("expecting `)' "
8690 "after scale factor in `%s'"),
af6bdddf
AM		 8691 operand_string);
8692 return 0;
8693 }
8694 }
8695 else if (!i.index_reg)
24eab124 8696 {
4eed87de
AM		 8697 as_bad (_("expecting index register or scale factor "
8698 "after `,'; got '%c'"),
af6bdddf 8699 *base_string);
24eab124
AM		 8700 return 0;
8701 }
8702 }
af6bdddf 8703 else if (*base_string != ')')
24eab124 8704 {
4eed87de
AM		 8705 as_bad (_("expecting `,' or `)' "
8706 "after base register in `%s'"),
af6bdddf 8707 operand_string);
24eab124
AM		 8708 return 0;
8709 }
c3332e24 8710 }
af6bdddf 8711 else if (*base_string == REGISTER_PREFIX)
c3332e24 8712 {
f76bf5e0
L		 8713 end_op = strchr (base_string, ',');
8714 if (end_op)
8715 *end_op = '\0';
af6bdddf 8716 as_bad (_("bad register name `%s'"), base_string);
24eab124 8717 return 0;
c3332e24 8718 }
24eab124
AM		 8719 }
8720
8721 /* If there's an expression beginning the operand, parse it,
8722 assuming displacement_string_start and
8723 displacement_string_end are meaningful. */
8724 if (displacement_string_start != displacement_string_end)
8725 {
8726 if (!i386_displacement (displacement_string_start,
8727 displacement_string_end))
8728 return 0;
8729 }
8730
8731 /* Special case for (%dx) while doing input/output op. */
8732 if (i.base_reg
0dfbf9d7
L		 8733 && operand_type_equal (&i.base_reg->reg_type,
8734 &reg16_inoutportreg)
24eab124
AM		 8735 && i.index_reg == 0
8736 && i.log2_scale_factor == 0
8737 && i.seg[i.mem_operands] == 0
40fb9820 8738 && !operand_type_check (i.types[this_operand], disp))
24eab124 8739 {
65da13b5 8740 i.types[this_operand] = inoutportreg;
24eab124
AM		 8741 return 1;
8742 }
8743
eecb386c
AM		 8744 if (i386_index_check (operand_string) == 0)
8745 return 0;
5c07affc 8746 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 8747 i.mem_operands++;
8748 }
8749 else
ce8a8b2f
AM		 8750 {
8751 /* It's not a memory operand; argh! */
24eab124
AM		 8752 as_bad (_("invalid char %s beginning operand %d `%s'"),
8753 output_invalid (*op_string),
8754 this_operand + 1,
8755 op_string);
8756 return 0;
8757 }
47926f60 8758 return 1; /* Normal return. */
252b5132
RH		 8759}
8760\f
fa94de6b
RM		 8761/* Calculate the maximum variable size (i.e., excluding fr_fix)
8762 that an rs_machine_dependent frag may reach. */
8763
8764unsigned int
8765i386_frag_max_var (fragS *frag)
8766{
8767 /* The only relaxable frags are for jumps.
8768 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8769 gas_assert (frag->fr_type == rs_machine_dependent);
8770 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8771}
8772
ee7fcc42
AM		 8773/* md_estimate_size_before_relax()
8774
8775 Called just before relax() for rs_machine_dependent frags. The x86
8776 assembler uses these frags to handle variable size jump
8777 instructions.
8778
8779 Any symbol that is now undefined will not become defined.
8780 Return the correct fr_subtype in the frag.
8781 Return the initial "guess for variable size of frag" to caller.
8782 The guess is actually the growth beyond the fixed part. Whatever
8783 we do to grow the fixed or variable part contributes to our
8784 returned value. */
8785
252b5132 8786int
7016a5d5 8787md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 8788{
252b5132 8789 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 8790 check for un-relaxable symbols. On an ELF system, we can't relax
8791 an externally visible symbol, because it may be overridden by a
8792 shared library. */
8793 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 8794#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8795 || (IS_ELF
31312f95 8796 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 8797 || S_IS_WEAK (fragP->fr_symbol)
8798 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
8799 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 8800#endif
8801#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 8802 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 8803 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 8804#endif
8805 )
252b5132 8806 {
b98ef147
AM		 8807 /* Symbol is undefined in this segment, or we need to keep a
8808 reloc so that weak symbols can be overridden. */
8809 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 8810 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 8811 unsigned char *opcode;
8812 int old_fr_fix;
f6af82bd 8813
ee7fcc42 8814 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 8815 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 8816 else if (size == 2)
f6af82bd
AM		 8817 reloc_type = BFD_RELOC_16_PCREL;
8818 else
8819 reloc_type = BFD_RELOC_32_PCREL;
252b5132 8820
ee7fcc42
AM		 8821 old_fr_fix = fragP->fr_fix;
8822 opcode = (unsigned char *) fragP->fr_opcode;
8823
fddf5b5b 8824 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 8825 {
fddf5b5b
AM		 8826 case UNCOND_JUMP:
8827 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 8828 opcode[0] = 0xe9;
252b5132 8829 fragP->fr_fix += size;
062cd5e7
AS		 8830 fix_new (fragP, old_fr_fix, size,
8831 fragP->fr_symbol,
8832 fragP->fr_offset, 1,
8833 reloc_type);
252b5132
RH		 8834 break;
8835
fddf5b5b 8836 case COND_JUMP86:
412167cb
AM		 8837 if (size == 2
8838 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 8839 {
8840 /* Negate the condition, and branch past an
8841 unconditional jump. */
8842 opcode[0] ^= 1;
8843 opcode[1] = 3;
8844 /* Insert an unconditional jump. */
8845 opcode[2] = 0xe9;
8846 /* We added two extra opcode bytes, and have a two byte
8847 offset. */
8848 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 8849 fix_new (fragP, old_fr_fix + 2, 2,
8850 fragP->fr_symbol,
8851 fragP->fr_offset, 1,
8852 reloc_type);
fddf5b5b
AM		 8853 break;
8854 }
8855 /* Fall through. */
8856
8857 case COND_JUMP:
412167cb
AM		 8858 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
8859 {
3e02c1cc
AM		 8860 fixS *fixP;
8861
412167cb 8862 fragP->fr_fix += 1;
3e02c1cc
AM		 8863 fixP = fix_new (fragP, old_fr_fix, 1,
8864 fragP->fr_symbol,
8865 fragP->fr_offset, 1,
8866 BFD_RELOC_8_PCREL);
8867 fixP->fx_signed = 1;
412167cb
AM		 8868 break;
8869 }
93c2a809 8870
24eab124 8871 /* This changes the byte-displacement jump 0x7N
fddf5b5b 8872 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 8873 opcode[1] = opcode[0] + 0x10;
f6af82bd 8874 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 8875 /* We've added an opcode byte. */
8876 fragP->fr_fix += 1 + size;
062cd5e7
AS		 8877 fix_new (fragP, old_fr_fix + 1, size,
8878 fragP->fr_symbol,
8879 fragP->fr_offset, 1,
8880 reloc_type);
252b5132 8881 break;
fddf5b5b
AM		 8882
8883 default:
8884 BAD_CASE (fragP->fr_subtype);
8885 break;
252b5132
RH		 8886 }
8887 frag_wane (fragP);
ee7fcc42 8888 return fragP->fr_fix - old_fr_fix;
252b5132 8889 }
93c2a809 8890
93c2a809
AM		 8891 /* Guess size depending on current relax state. Initially the relax
8892 state will correspond to a short jump and we return 1, because
8893 the variable part of the frag (the branch offset) is one byte
8894 long. However, we can relax a section more than once and in that
8895 case we must either set fr_subtype back to the unrelaxed state,
8896 or return the value for the appropriate branch. */
8897 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 8898}
8899
47926f60
KH		 8900/* Called after relax() is finished.
8901
8902 In: Address of frag.
8903 fr_type == rs_machine_dependent.
8904 fr_subtype is what the address relaxed to.
8905
8906 Out: Any fixSs and constants are set up.
8907 Caller will turn frag into a ".space 0". */
8908
252b5132 8909void
7016a5d5
TG		 8910md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
8911 fragS *fragP)
252b5132 8912{
29b0f896 8913 unsigned char *opcode;
252b5132 8914 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 8915 offsetT target_address;
8916 offsetT opcode_address;
252b5132 8917 unsigned int extension = 0;
847f7ad4 8918 offsetT displacement_from_opcode_start;
252b5132
RH		 8919
8920 opcode = (unsigned char *) fragP->fr_opcode;
8921
47926f60 8922 /* Address we want to reach in file space. */
252b5132 8923 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 8924
47926f60 8925 /* Address opcode resides at in file space. */
252b5132
RH		 8926 opcode_address = fragP->fr_address + fragP->fr_fix;
8927
47926f60 8928 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 8929 displacement_from_opcode_start = target_address - opcode_address;
8930
fddf5b5b 8931 if ((fragP->fr_subtype & BIG) == 0)
252b5132 8932 {
47926f60
KH		 8933 /* Don't have to change opcode. */
8934 extension = 1; /* 1 opcode + 1 displacement */
252b5132 8935 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 8936 }
8937 else
8938 {
8939 if (no_cond_jump_promotion
8940 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 8941 as_warn_where (fragP->fr_file, fragP->fr_line,
8942 _("long jump required"));
252b5132 8943
fddf5b5b
AM		 8944 switch (fragP->fr_subtype)
8945 {
8946 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
8947 extension = 4; /* 1 opcode + 4 displacement */
8948 opcode[0] = 0xe9;
8949 where_to_put_displacement = &opcode[1];
8950 break;
252b5132 8951
fddf5b5b
AM		 8952 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
8953 extension = 2; /* 1 opcode + 2 displacement */
8954 opcode[0] = 0xe9;
8955 where_to_put_displacement = &opcode[1];
8956 break;
252b5132 8957
fddf5b5b
AM		 8958 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
8959 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
8960 extension = 5; /* 2 opcode + 4 displacement */
8961 opcode[1] = opcode[0] + 0x10;
8962 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
8963 where_to_put_displacement = &opcode[2];
8964 break;
252b5132 8965
fddf5b5b
AM		 8966 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
8967 extension = 3; /* 2 opcode + 2 displacement */
8968 opcode[1] = opcode[0] + 0x10;
8969 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
8970 where_to_put_displacement = &opcode[2];
8971 break;
252b5132 8972
fddf5b5b
AM		 8973 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
8974 extension = 4;
8975 opcode[0] ^= 1;
8976 opcode[1] = 3;
8977 opcode[2] = 0xe9;
8978 where_to_put_displacement = &opcode[3];
8979 break;
8980
8981 default:
8982 BAD_CASE (fragP->fr_subtype);
8983 break;
8984 }
252b5132 8985 }
fddf5b5b 8986
7b81dfbb
AJ		 8987 /* If size if less then four we are sure that the operand fits,
8988 but if it's 4, then it could be that the displacement is larger
8989 then -/+ 2GB. */
8990 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
8991 && object_64bit
8992 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 8993 + ((addressT) 1 << 31))
8994 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 8995 {
8996 as_bad_where (fragP->fr_file, fragP->fr_line,
8997 _("jump target out of range"));
8998 /* Make us emit 0. */
8999 displacement_from_opcode_start = extension;
9000 }
47926f60 9001 /* Now put displacement after opcode. */
252b5132
RH		 9002 md_number_to_chars ((char *) where_to_put_displacement,
9003 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9004 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9005 fragP->fr_fix += extension;
9006}
9007\f
7016a5d5 9008/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9009 by our caller that we have all the info we need to fix it up.
9010
7016a5d5
TG		 9011 Parameter valP is the pointer to the value of the bits.
9012
252b5132
RH		 9013 On the 386, immediates, displacements, and data pointers are all in
9014 the same (little-endian) format, so we don't need to care about which
9015 we are handling. */
9016
94f592af 9017void
7016a5d5 9018md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9019{
94f592af 9020 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9021 valueT value = *valP;
252b5132 9022
f86103b7 9023#if !defined (TE_Mach)
93382f6d
AM		 9024 if (fixP->fx_pcrel)
9025 {
9026 switch (fixP->fx_r_type)
9027 {
5865bb77
ILT		 9028 default:
9029 break;
9030
d6ab8113
JB		 9031 case BFD_RELOC_64:
9032 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9033 break;
93382f6d 9034 case BFD_RELOC_32:
ae8887b5 9035 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9036 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9037 break;
9038 case BFD_RELOC_16:
9039 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9040 break;
9041 case BFD_RELOC_8:
9042 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9043 break;
9044 }
9045 }
252b5132 9046
a161fe53 9047 if (fixP->fx_addsy != NULL
31312f95 9048 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9049 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9050 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9051 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9052 && !use_rela_relocations)
252b5132 9053 {
31312f95
AM		 9054 /* This is a hack. There should be a better way to handle this.
9055 This covers for the fact that bfd_install_relocation will
9056 subtract the current location (for partial_inplace, PC relative
9057 relocations); see more below. */
252b5132 9058#ifndef OBJ_AOUT
718ddfc0 9059 if (IS_ELF
252b5132
RH		 9060#ifdef TE_PE
9061 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9062#endif
9063 )
9064 value += fixP->fx_where + fixP->fx_frag->fr_address;
9065#endif
9066#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9067 if (IS_ELF)
252b5132 9068 {
6539b54b 9069 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9070
6539b54b 9071 if ((sym_seg == seg
2f66722d 9072 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9073 && sym_seg != absolute_section))
af65af87 9074 && !generic_force_reloc (fixP))
2f66722d
AM		 9075 {
9076 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9077 bfd_install_relocation subtracts them out again. I think
9078 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9079 it. FIXME. */
9080 value += fixP->fx_where + fixP->fx_frag->fr_address;
9081 }
252b5132
RH		 9082 }
9083#endif
9084#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9085 /* For some reason, the PE format does not store a
9086 section address offset for a PC relative symbol. */
9087 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9088 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9089 value += md_pcrel_from (fixP);
9090#endif
9091 }
fbeb56a4 9092#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9093 if (fixP->fx_addsy != NULL
9094 && S_IS_WEAK (fixP->fx_addsy)
9095 /* PR 16858: Do not modify weak function references. */
9096 && ! fixP->fx_pcrel)
fbeb56a4 9097 {
296a8689
NC		 9098#if !defined (TE_PEP)
9099 /* For x86 PE weak function symbols are neither PC-relative
9100 nor do they set S_IS_FUNCTION. So the only reliable way
9101 to detect them is to check the flags of their containing
9102 section. */
9103 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9104 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9105 ;
9106 else
9107#endif
fbeb56a4
DK		 9108 value -= S_GET_VALUE (fixP->fx_addsy);
9109 }
9110#endif
252b5132
RH		 9111
9112 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9113 and we must not disappoint it. */
252b5132 9114#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9115 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9116 switch (fixP->fx_r_type)
9117 {
9118 case BFD_RELOC_386_PLT32:
3e73aa7c 9119 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9120 /* Make the jump instruction point to the address of the operand. At
9121 runtime we merely add the offset to the actual PLT entry. */
9122 value = -4;
9123 break;
31312f95 9124
13ae64f3
JJ		 9125 case BFD_RELOC_386_TLS_GD:
9126 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9127 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9128 case BFD_RELOC_386_TLS_IE:
9129 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9130 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9131 case BFD_RELOC_X86_64_TLSGD:
9132 case BFD_RELOC_X86_64_TLSLD:
9133 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9134 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9135 value = 0; /* Fully resolved at runtime. No addend. */
9136 /* Fallthrough */
9137 case BFD_RELOC_386_TLS_LE:
9138 case BFD_RELOC_386_TLS_LDO_32:
9139 case BFD_RELOC_386_TLS_LE_32:
9140 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9141 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9142 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9143 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9144 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9145 break;
9146
67a4f2b7
AO		 9147 case BFD_RELOC_386_TLS_DESC_CALL:
9148 case BFD_RELOC_X86_64_TLSDESC_CALL:
9149 value = 0; /* Fully resolved at runtime. No addend. */
9150 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9151 fixP->fx_done = 0;
9152 return;
9153
00f7efb6
JJ		 9154 case BFD_RELOC_386_GOT32:
9155 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 9156 value = 0; /* Fully resolved at runtime. No addend. */
9157 break;
47926f60
KH		 9158
9159 case BFD_RELOC_VTABLE_INHERIT:
9160 case BFD_RELOC_VTABLE_ENTRY:
9161 fixP->fx_done = 0;
94f592af 9162 return;
47926f60
KH		 9163
9164 default:
9165 break;
9166 }
9167#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9168 *valP = value;
f86103b7 9169#endif /* !defined (TE_Mach) */
3e73aa7c 9170
3e73aa7c 9171 /* Are we finished with this relocation now? */
c6682705 9172 if (fixP->fx_addsy == NULL)
3e73aa7c 9173 fixP->fx_done = 1;
fbeb56a4
DK		 9174#if defined (OBJ_COFF) && defined (TE_PE)
9175 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9176 {
9177 fixP->fx_done = 0;
9178 /* Remember value for tc_gen_reloc. */
9179 fixP->fx_addnumber = value;
9180 /* Clear out the frag for now. */
9181 value = 0;
9182 }
9183#endif
3e73aa7c
JH		 9184 else if (use_rela_relocations)
9185 {
9186 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9187 /* Remember value for tc_gen_reloc. */
9188 fixP->fx_addnumber = value;
3e73aa7c
JH		 9189 value = 0;
9190 }
f86103b7 9191
94f592af 9192 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9193}
252b5132 9194\f
252b5132 9195char *
499ac353 9196md_atof (int type, char *litP, int *sizeP)
252b5132 9197{
499ac353
NC		 9198 /* This outputs the LITTLENUMs in REVERSE order;
9199 in accord with the bigendian 386. */
9200 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9201}
9202\f
2d545b82 9203static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9204
252b5132 9205static char *
e3bb37b5 9206output_invalid (int c)
252b5132 9207{
3882b010 9208 if (ISPRINT (c))
f9f21a03
L		 9209 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9210 "'%c'", c);
252b5132 9211 else
f9f21a03 9212 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9213 "(0x%x)", (unsigned char) c);
252b5132
RH		 9214 return output_invalid_buf;
9215}
9216
af6bdddf 9217/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9218
9219static const reg_entry *
4d1bb795 9220parse_real_register (char *reg_string, char **end_op)
252b5132 9221{
af6bdddf
AM		 9222 char *s = reg_string;
9223 char *p;
252b5132
RH		 9224 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9225 const reg_entry *r;
9226
9227 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9228 if (*s == REGISTER_PREFIX)
9229 ++s;
9230
9231 if (is_space_char (*s))
9232 ++s;
9233
9234 p = reg_name_given;
af6bdddf 9235 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9236 {
9237 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9238 return (const reg_entry *) NULL;
9239 s++;
252b5132
RH		 9240 }
9241
6588847e
DN		 9242 /* For naked regs, make sure that we are not dealing with an identifier.
9243 This prevents confusing an identifier like `eax_var' with register
9244 `eax'. */
9245 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9246 return (const reg_entry *) NULL;
9247
af6bdddf 9248 *end_op = s;
252b5132
RH		 9249
9250 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9251
5f47d35b 9252 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9253 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9254 {
5f47d35b
AM		 9255 if (is_space_char (*s))
9256 ++s;
9257 if (*s == '(')
9258 {
af6bdddf 9259 ++s;
5f47d35b
AM		 9260 if (is_space_char (*s))
9261 ++s;
9262 if (*s >= '0' && *s <= '7')
9263 {
db557034 9264 int fpr = *s - '0';
af6bdddf 9265 ++s;
5f47d35b
AM		 9266 if (is_space_char (*s))
9267 ++s;
9268 if (*s == ')')
9269 {
9270 *end_op = s + 1;
1e9cc1c2 9271 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9272 know (r);
9273 return r + fpr;
5f47d35b 9274 }
5f47d35b 9275 }
47926f60 9276 /* We have "%st(" then garbage. */
5f47d35b
AM		 9277 return (const reg_entry *) NULL;
9278 }
9279 }
9280
a60de03c
JB		 9281 if (r == NULL || allow_pseudo_reg)
9282 return r;
9283
0dfbf9d7 9284 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9285 return (const reg_entry *) NULL;
9286
192dc9c6
JB		 9287 if ((r->reg_type.bitfield.reg32
9288 || r->reg_type.bitfield.sreg3
9289 || r->reg_type.bitfield.control
9290 || r->reg_type.bitfield.debug
9291 || r->reg_type.bitfield.test)
9292 && !cpu_arch_flags.bitfield.cpui386)
9293 return (const reg_entry *) NULL;
9294
309d3373
JB		 9295 if (r->reg_type.bitfield.floatreg
9296 && !cpu_arch_flags.bitfield.cpu8087
9297 && !cpu_arch_flags.bitfield.cpu287
9298 && !cpu_arch_flags.bitfield.cpu387)
9299 return (const reg_entry *) NULL;
9300
192dc9c6
JB		 9301 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9302 return (const reg_entry *) NULL;
9303
9304 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9305 return (const reg_entry *) NULL;
9306
40f12533
L		 9307 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9308 return (const reg_entry *) NULL;
9309
43234a1e
L		 9310 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9311 && !cpu_arch_flags.bitfield.cpuavx512f)
9312 return (const reg_entry *) NULL;
9313
db51cc60 9314 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9315 if (!allow_index_reg
db51cc60
L		 9316 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9317 return (const reg_entry *) NULL;
9318
43234a1e
L		 9319 /* Upper 16 vector register is only available with VREX in 64bit
9320 mode. */
9321 if ((r->reg_flags & RegVRex))
9322 {
9323 if (!cpu_arch_flags.bitfield.cpuvrex
9324 || flag_code != CODE_64BIT)
9325 return (const reg_entry *) NULL;
9326
9327 i.need_vrex = 1;
9328 }
9329
a60de03c
JB		 9330 if (((r->reg_flags & (RegRex64 | RegRex))
9331 || r->reg_type.bitfield.reg64)
40fb9820 9332 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9333 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9334 && flag_code != CODE_64BIT)
20f0a1fc 9335 return (const reg_entry *) NULL;
1ae00879 9336
b7240065
JB		 9337 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9338 return (const reg_entry *) NULL;
9339
252b5132
RH		 9340 return r;
9341}
4d1bb795
JB		 9342
9343/* REG_STRING starts *before* REGISTER_PREFIX. */
9344
9345static const reg_entry *
9346parse_register (char *reg_string, char **end_op)
9347{
9348 const reg_entry *r;
9349
9350 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9351 r = parse_real_register (reg_string, end_op);
9352 else
9353 r = NULL;
9354 if (!r)
9355 {
9356 char *save = input_line_pointer;
9357 char c;
9358 symbolS *symbolP;
9359
9360 input_line_pointer = reg_string;
9361 c = get_symbol_end ();
9362 symbolP = symbol_find (reg_string);
9363 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9364 {
9365 const expressionS *e = symbol_get_value_expression (symbolP);
9366
0398aac5 9367 know (e->X_op == O_register);
4eed87de 9368 know (e->X_add_number >= 0
c3fe08fa 9369 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9370 r = i386_regtab + e->X_add_number;
d3bb6b49
IT		 9371 if ((r->reg_flags & RegVRex))
9372 i.need_vrex = 1;
4d1bb795
JB		 9373 *end_op = input_line_pointer;
9374 }
9375 *input_line_pointer = c;
9376 input_line_pointer = save;
9377 }
9378 return r;
9379}
9380
9381int
9382i386_parse_name (char *name, expressionS *e, char *nextcharP)
9383{
9384 const reg_entry *r;
9385 char *end = input_line_pointer;
9386
9387 *end = *nextcharP;
9388 r = parse_register (name, &input_line_pointer);
9389 if (r && end <= input_line_pointer)
9390 {
9391 *nextcharP = *input_line_pointer;
9392 *input_line_pointer = 0;
9393 e->X_op = O_register;
9394 e->X_add_number = r - i386_regtab;
9395 return 1;
9396 }
9397 input_line_pointer = end;
9398 *end = 0;
ee86248c 9399 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9400}
9401
9402void
9403md_operand (expressionS *e)
9404{
ee86248c
JB		 9405 char *end;
9406 const reg_entry *r;
4d1bb795 9407
ee86248c
JB		 9408 switch (*input_line_pointer)
9409 {
9410 case REGISTER_PREFIX:
9411 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9412 if (r)
9413 {
9414 e->X_op = O_register;
9415 e->X_add_number = r - i386_regtab;
9416 input_line_pointer = end;
9417 }
ee86248c
JB		 9418 break;
9419
9420 case '[':
9c2799c2 9421 gas_assert (intel_syntax);
ee86248c
JB		 9422 end = input_line_pointer++;
9423 expression (e);
9424 if (*input_line_pointer == ']')
9425 {
9426 ++input_line_pointer;
9427 e->X_op_symbol = make_expr_symbol (e);
9428 e->X_add_symbol = NULL;
9429 e->X_add_number = 0;
9430 e->X_op = O_index;
9431 }
9432 else
9433 {
9434 e->X_op = O_absent;
9435 input_line_pointer = end;
9436 }
9437 break;
4d1bb795
JB		 9438 }
9439}
9440
252b5132 9441\f
4cc782b5 9442#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9443const char *md_shortopts = "kVQ:sqn";
252b5132 9444#else
12b55ccc 9445const char *md_shortopts = "qn";
252b5132 9446#endif
6e0b89ee 9447
3e73aa7c 9448#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9449#define OPTION_64 (OPTION_MD_BASE + 1)
9450#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9451#define OPTION_MARCH (OPTION_MD_BASE + 3)
9452#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9453#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9454#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9455#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9456#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9457#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9458#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9459#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9460#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9461#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9462#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9463#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9464#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9465#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9466#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
a5094208 9467#define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9468#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
b3b91714 9469
99ad8390
NC		 9470struct option md_longopts[] =
9471{
3e73aa7c 9472 {"32", no_argument, NULL, OPTION_32},
321098a5 9473#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9474 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9475 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9476#endif
9477#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9478 {"x32", no_argument, NULL, OPTION_X32},
6e0b89ee 9479#endif
b3b91714 9480 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9481 {"march", required_argument, NULL, OPTION_MARCH},
9482 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9483 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9484 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9485 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9486 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9487 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9488 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9489 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9490 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9491 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9492 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9493 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9494 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9495# if defined (TE_PE) || defined (TE_PEP)
9496 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9497#endif
a5094208 9498 {"momit-lock-prefix", required_argument, NULL, OPTION_OMIT_LOCK_PREFIX},
d3d3c6db 9499 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
252b5132
RH		 9500 {NULL, no_argument, NULL, 0}
9501};
9502size_t md_longopts_size = sizeof (md_longopts);
9503
9504int
9103f4f4 9505md_parse_option (int c, char *arg)
252b5132 9506{
91d6fa6a 9507 unsigned int j;
6305a203 9508 char *arch, *next;
9103f4f4 9509
252b5132
RH		 9510 switch (c)
9511 {
12b55ccc
L		 9512 case 'n':
9513 optimize_align_code = 0;
9514 break;
9515
a38cf1db
AM		 9516 case 'q':
9517 quiet_warnings = 1;
252b5132
RH		 9518 break;
9519
9520#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9521 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9522 should be emitted or not. FIXME: Not implemented. */
9523 case 'Q':
252b5132
RH		 9524 break;
9525
9526 /* -V: SVR4 argument to print version ID. */
9527 case 'V':
9528 print_version_id ();
9529 break;
9530
a38cf1db
AM		 9531 /* -k: Ignore for FreeBSD compatibility. */
9532 case 'k':
252b5132 9533 break;
4cc782b5
ILT		 9534
9535 case 's':
9536 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9537 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9538 break;
99ad8390 9539#endif
321098a5 9540#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9541 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9542 case OPTION_64:
9543 {
9544 const char **list, **l;
9545
3e73aa7c
JH		 9546 list = bfd_target_list ();
9547 for (l = list; *l != NULL; l++)
8620418b 9548 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9549 || strcmp (*l, "coff-x86-64") == 0
9550 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9551 || strcmp (*l, "pei-x86-64") == 0
9552 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9553 {
9554 default_arch = "x86_64";
9555 break;
9556 }
3e73aa7c 9557 if (*l == NULL)
2b5d6a91 9558 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9559 free (list);
9560 }
9561 break;
9562#endif
252b5132 9563
351f65ca 9564#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9565 case OPTION_X32:
351f65ca
L		 9566 if (IS_ELF)
9567 {
9568 const char **list, **l;
9569
9570 list = bfd_target_list ();
9571 for (l = list; *l != NULL; l++)
9572 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9573 {
9574 default_arch = "x86_64:32";
9575 break;
9576 }
9577 if (*l == NULL)
2b5d6a91 9578 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9579 free (list);
9580 }
9581 else
9582 as_fatal (_("32bit x86_64 is only supported for ELF"));
9583 break;
9584#endif
9585
6e0b89ee
AM		 9586 case OPTION_32:
9587 default_arch = "i386";
9588 break;
9589
b3b91714
AM		 9590 case OPTION_DIVIDE:
9591#ifdef SVR4_COMMENT_CHARS
9592 {
9593 char *n, *t;
9594 const char *s;
9595
9596 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
9597 t = n;
9598 for (s = i386_comment_chars; *s != '\0'; s++)
9599 if (*s != '/')
9600 *t++ = *s;
9601 *t = '\0';
9602 i386_comment_chars = n;
9603 }
9604#endif
9605 break;
9606
9103f4f4 9607 case OPTION_MARCH:
6305a203
L		 9608 arch = xstrdup (arg);
9609 do
9103f4f4 9610 {
6305a203 9611 if (*arch == '.')
2b5d6a91 9612 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9613 next = strchr (arch, '+');
9614 if (next)
9615 *next++ = '\0';
91d6fa6a 9616 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9617 {
91d6fa6a 9618 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9619 {
6305a203 9620 /* Processor. */
1ded5609
JB		 9621 if (! cpu_arch[j].flags.bitfield.cpui386)
9622 continue;
9623
91d6fa6a 9624 cpu_arch_name = cpu_arch[j].name;
6305a203 9625 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9626 cpu_arch_flags = cpu_arch[j].flags;
9627 cpu_arch_isa = cpu_arch[j].type;
9628 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9629 if (!cpu_arch_tune_set)
9630 {
9631 cpu_arch_tune = cpu_arch_isa;
9632 cpu_arch_tune_flags = cpu_arch_isa_flags;
9633 }
9634 break;
9635 }
91d6fa6a
NC		 9636 else if (*cpu_arch [j].name == '.'
9637 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9638 {
9639 /* ISA entension. */
9640 i386_cpu_flags flags;
309d3373 9641
49021df2 9642 if (!cpu_arch[j].negated)
309d3373 9643 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 9644 cpu_arch[j].flags);
309d3373
JB		 9645 else
9646 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 9647 cpu_arch[j].flags);
0dfbf9d7 9648 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 9649 {
9650 if (cpu_sub_arch_name)
9651 {
9652 char *name = cpu_sub_arch_name;
9653 cpu_sub_arch_name = concat (name,
91d6fa6a 9654 cpu_arch[j].name,
1bf57e9f 9655 (const char *) NULL);
6305a203
L		 9656 free (name);
9657 }
9658 else
91d6fa6a 9659 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 9660 cpu_arch_flags = flags;
a586129e 9661 cpu_arch_isa_flags = flags;
6305a203
L		 9662 }
9663 break;
ccc9c027 9664 }
9103f4f4 9665 }
6305a203 9666
91d6fa6a 9667 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9668 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9669
9670 arch = next;
9103f4f4 9671 }
6305a203 9672 while (next != NULL );
9103f4f4
L		 9673 break;
9674
9675 case OPTION_MTUNE:
9676 if (*arg == '.')
2b5d6a91 9677 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 9678 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9679 {
91d6fa6a 9680 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 9681 {
ccc9c027 9682 cpu_arch_tune_set = 1;
91d6fa6a
NC		 9683 cpu_arch_tune = cpu_arch [j].type;
9684 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 9685 break;
9686 }
9687 }
91d6fa6a 9688 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9689 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 9690 break;
9691
1efbbeb4
L		 9692 case OPTION_MMNEMONIC:
9693 if (strcasecmp (arg, "att") == 0)
9694 intel_mnemonic = 0;
9695 else if (strcasecmp (arg, "intel") == 0)
9696 intel_mnemonic = 1;
9697 else
2b5d6a91 9698 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 9699 break;
9700
9701 case OPTION_MSYNTAX:
9702 if (strcasecmp (arg, "att") == 0)
9703 intel_syntax = 0;
9704 else if (strcasecmp (arg, "intel") == 0)
9705 intel_syntax = 1;
9706 else
2b5d6a91 9707 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 9708 break;
9709
9710 case OPTION_MINDEX_REG:
9711 allow_index_reg = 1;
9712 break;
9713
9714 case OPTION_MNAKED_REG:
9715 allow_naked_reg = 1;
9716 break;
9717
9718 case OPTION_MOLD_GCC:
9719 old_gcc = 1;
1efbbeb4
L		 9720 break;
9721
c0f3af97
L		 9722 case OPTION_MSSE2AVX:
9723 sse2avx = 1;
9724 break;
9725
daf50ae7
L		 9726 case OPTION_MSSE_CHECK:
9727 if (strcasecmp (arg, "error") == 0)
7bab8ab5 9728 sse_check = check_error;
daf50ae7 9729 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 9730 sse_check = check_warning;
daf50ae7 9731 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 9732 sse_check = check_none;
daf50ae7 9733 else
2b5d6a91 9734 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 9735 break;
9736
7bab8ab5
JB		 9737 case OPTION_MOPERAND_CHECK:
9738 if (strcasecmp (arg, "error") == 0)
9739 operand_check = check_error;
9740 else if (strcasecmp (arg, "warning") == 0)
9741 operand_check = check_warning;
9742 else if (strcasecmp (arg, "none") == 0)
9743 operand_check = check_none;
9744 else
9745 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
9746 break;
9747
539f890d
L		 9748 case OPTION_MAVXSCALAR:
9749 if (strcasecmp (arg, "128") == 0)
9750 avxscalar = vex128;
9751 else if (strcasecmp (arg, "256") == 0)
9752 avxscalar = vex256;
9753 else
2b5d6a91 9754 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 9755 break;
9756
7e8b059b
L		 9757 case OPTION_MADD_BND_PREFIX:
9758 add_bnd_prefix = 1;
9759 break;
9760
43234a1e
L		 9761 case OPTION_MEVEXLIG:
9762 if (strcmp (arg, "128") == 0)
9763 evexlig = evexl128;
9764 else if (strcmp (arg, "256") == 0)
9765 evexlig = evexl256;
9766 else if (strcmp (arg, "512") == 0)
9767 evexlig = evexl512;
9768 else
9769 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
9770 break;
9771
d3d3c6db
IT		 9772 case OPTION_MEVEXRCIG:
9773 if (strcmp (arg, "rne") == 0)
9774 evexrcig = rne;
9775 else if (strcmp (arg, "rd") == 0)
9776 evexrcig = rd;
9777 else if (strcmp (arg, "ru") == 0)
9778 evexrcig = ru;
9779 else if (strcmp (arg, "rz") == 0)
9780 evexrcig = rz;
9781 else
9782 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
9783 break;
9784
43234a1e
L		 9785 case OPTION_MEVEXWIG:
9786 if (strcmp (arg, "0") == 0)
9787 evexwig = evexw0;
9788 else if (strcmp (arg, "1") == 0)
9789 evexwig = evexw1;
9790 else
9791 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
9792 break;
9793
167ad85b
TG		 9794# if defined (TE_PE) || defined (TE_PEP)
9795 case OPTION_MBIG_OBJ:
9796 use_big_obj = 1;
9797 break;
9798#endif
9799
a5094208 9800 case OPTION_OMIT_LOCK_PREFIX:
d022bddd
IT		 9801 if (strcasecmp (arg, "yes") == 0)
9802 omit_lock_prefix = 1;
9803 else if (strcasecmp (arg, "no") == 0)
9804 omit_lock_prefix = 0;
9805 else
9806 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
9807 break;
9808
252b5132
RH		 9809 default:
9810 return 0;
9811 }
9812 return 1;
9813}
9814
8a2c8fef
L		 9815#define MESSAGE_TEMPLATE \
9816" "
9817
9818static void
1ded5609 9819show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 9820{
9821 static char message[] = MESSAGE_TEMPLATE;
9822 char *start = message + 27;
9823 char *p;
9824 int size = sizeof (MESSAGE_TEMPLATE);
9825 int left;
9826 const char *name;
9827 int len;
9828 unsigned int j;
9829
9830 p = start;
9831 left = size - (start - message);
9832 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9833 {
9834 /* Should it be skipped? */
9835 if (cpu_arch [j].skip)
9836 continue;
9837
9838 name = cpu_arch [j].name;
9839 len = cpu_arch [j].len;
9840 if (*name == '.')
9841 {
9842 /* It is an extension. Skip if we aren't asked to show it. */
9843 if (ext)
9844 {
9845 name++;
9846 len--;
9847 }
9848 else
9849 continue;
9850 }
9851 else if (ext)
9852 {
9853 /* It is an processor. Skip if we show only extension. */
9854 continue;
9855 }
1ded5609
JB		 9856 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
9857 {
9858 /* It is an impossible processor - skip. */
9859 continue;
9860 }
8a2c8fef
L		 9861
9862 /* Reserve 2 spaces for ", " or ",\0" */
9863 left -= len + 2;
9864
9865 /* Check if there is any room. */
9866 if (left >= 0)
9867 {
9868 if (p != start)
9869 {
9870 *p++ = ',';
9871 *p++ = ' ';
9872 }
9873 p = mempcpy (p, name, len);
9874 }
9875 else
9876 {
9877 /* Output the current message now and start a new one. */
9878 *p++ = ',';
9879 *p = '\0';
9880 fprintf (stream, "%s\n", message);
9881 p = start;
9882 left = size - (start - message) - len - 2;
8d63c93e 9883
8a2c8fef
L		 9884 gas_assert (left >= 0);
9885
9886 p = mempcpy (p, name, len);
9887 }
9888 }
9889
9890 *p = '\0';
9891 fprintf (stream, "%s\n", message);
9892}
9893
252b5132 9894void
8a2c8fef 9895md_show_usage (FILE *stream)
252b5132 9896{
4cc782b5
ILT		 9897#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9898 fprintf (stream, _("\
a38cf1db
AM		 9899 -Q ignored\n\
9900 -V print assembler version number\n\
b3b91714
AM		 9901 -k ignored\n"));
9902#endif
9903 fprintf (stream, _("\
12b55ccc 9904 -n Do not optimize code alignment\n\
b3b91714
AM		 9905 -q quieten some warnings\n"));
9906#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9907 fprintf (stream, _("\
a38cf1db 9908 -s ignored\n"));
b3b91714 9909#endif
321098a5
L		 9910#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9911 || defined (TE_PE) || defined (TE_PEP))
751d281c 9912 fprintf (stream, _("\
570561f7 9913 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 9914#endif
b3b91714
AM		 9915#ifdef SVR4_COMMENT_CHARS
9916 fprintf (stream, _("\
9917 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 9918#else
9919 fprintf (stream, _("\
b3b91714 9920 --divide ignored\n"));
4cc782b5 9921#endif
9103f4f4 9922 fprintf (stream, _("\
6305a203 9923 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 9924 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 9925 show_arch (stream, 0, 1);
8a2c8fef
L		 9926 fprintf (stream, _("\
9927 EXTENSION is combination of:\n"));
1ded5609 9928 show_arch (stream, 1, 0);
6305a203 9929 fprintf (stream, _("\
8a2c8fef 9930 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 9931 show_arch (stream, 0, 0);
ba104c83 9932 fprintf (stream, _("\
c0f3af97
L		 9933 -msse2avx encode SSE instructions with VEX prefix\n"));
9934 fprintf (stream, _("\
daf50ae7
L		 9935 -msse-check=[none|error|warning]\n\
9936 check SSE instructions\n"));
9937 fprintf (stream, _("\
7bab8ab5
JB		 9938 -moperand-check=[none|error|warning]\n\
9939 check operand combinations for validity\n"));
9940 fprintf (stream, _("\
539f890d
L		 9941 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
9942 length\n"));
9943 fprintf (stream, _("\
43234a1e
L		 9944 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
9945 length\n"));
9946 fprintf (stream, _("\
9947 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
9948 for EVEX.W bit ignored instructions\n"));
9949 fprintf (stream, _("\
d3d3c6db
IT		 9950 -mevexrcig=[rne|rd|ru|rz]\n\
9951 encode EVEX instructions with specific EVEX.RC value\n\
9952 for SAE-only ignored instructions\n"));
9953 fprintf (stream, _("\
ba104c83
L		 9954 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
9955 fprintf (stream, _("\
9956 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
9957 fprintf (stream, _("\
9958 -mindex-reg support pseudo index registers\n"));
9959 fprintf (stream, _("\
9960 -mnaked-reg don't require `%%' prefix for registers\n"));
9961 fprintf (stream, _("\
9962 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 9963 fprintf (stream, _("\
9964 -madd-bnd-prefix add BND prefix for all valid branches\n"));
167ad85b
TG		 9965# if defined (TE_PE) || defined (TE_PEP)
9966 fprintf (stream, _("\
9967 -mbig-obj generate big object files\n"));
9968#endif
d022bddd
IT		 9969 fprintf (stream, _("\
9970 -momit-lock-prefix=[no|yes]\n\
9971 strip all lock prefixes\n"));
252b5132
RH		 9972}
9973
3e73aa7c 9974#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 9975 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 9976 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 9977
9978/* Pick the target format to use. */
9979
47926f60 9980const char *
e3bb37b5 9981i386_target_format (void)
252b5132 9982{
351f65ca
L		 9983 if (!strncmp (default_arch, "x86_64", 6))
9984 {
9985 update_code_flag (CODE_64BIT, 1);
9986 if (default_arch[6] == '\0')
7f56bc95 9987 x86_elf_abi = X86_64_ABI;
351f65ca 9988 else
7f56bc95 9989 x86_elf_abi = X86_64_X32_ABI;
351f65ca 9990 }
3e73aa7c 9991 else if (!strcmp (default_arch, "i386"))
78f12dd3 9992 update_code_flag (CODE_32BIT, 1);
3e73aa7c 9993 else
2b5d6a91 9994 as_fatal (_("unknown architecture"));
89507696
JB		 9995
9996 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
9997 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
9998 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
9999 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10000
252b5132
RH		 10001 switch (OUTPUT_FLAVOR)
10002 {
9384f2ff 10003#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10004 case bfd_target_aout_flavour:
47926f60 10005 return AOUT_TARGET_FORMAT;
4c63da97 10006#endif
9384f2ff
AM		 10007#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10008# if defined (TE_PE) || defined (TE_PEP)
10009 case bfd_target_coff_flavour:
167ad85b
TG		 10010 if (flag_code == CODE_64BIT)
10011 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10012 else
10013 return "pe-i386";
9384f2ff 10014# elif defined (TE_GO32)
0561d57c
JK		 10015 case bfd_target_coff_flavour:
10016 return "coff-go32";
9384f2ff 10017# else
252b5132
RH		 10018 case bfd_target_coff_flavour:
10019 return "coff-i386";
9384f2ff 10020# endif
4c63da97 10021#endif
3e73aa7c 10022#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10023 case bfd_target_elf_flavour:
3e73aa7c 10024 {
351f65ca
L		 10025 const char *format;
10026
10027 switch (x86_elf_abi)
4fa24527 10028 {
351f65ca
L		 10029 default:
10030 format = ELF_TARGET_FORMAT;
10031 break;
7f56bc95 10032 case X86_64_ABI:
351f65ca 10033 use_rela_relocations = 1;
4fa24527 10034 object_64bit = 1;
351f65ca
L		 10035 format = ELF_TARGET_FORMAT64;
10036 break;
7f56bc95 10037 case X86_64_X32_ABI:
4fa24527 10038 use_rela_relocations = 1;
351f65ca 10039 object_64bit = 1;
862be3fb 10040 disallow_64bit_reloc = 1;
351f65ca
L		 10041 format = ELF_TARGET_FORMAT32;
10042 break;
4fa24527 10043 }
3632d14b 10044 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10045 {
7f56bc95 10046 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10047 as_fatal (_("Intel L1OM is 64bit only"));
10048 return ELF_TARGET_L1OM_FORMAT;
10049 }
7a9068fe
L		 10050 if (cpu_arch_isa == PROCESSOR_K1OM)
10051 {
10052 if (x86_elf_abi != X86_64_ABI)
10053 as_fatal (_("Intel K1OM is 64bit only"));
10054 return ELF_TARGET_K1OM_FORMAT;
10055 }
8a9036a4 10056 else
351f65ca 10057 return format;
3e73aa7c 10058 }
e57f8c65
TG		 10059#endif
10060#if defined (OBJ_MACH_O)
10061 case bfd_target_mach_o_flavour:
d382c579
TG		 10062 if (flag_code == CODE_64BIT)
10063 {
10064 use_rela_relocations = 1;
10065 object_64bit = 1;
10066 return "mach-o-x86-64";
10067 }
10068 else
10069 return "mach-o-i386";
4c63da97 10070#endif
252b5132
RH		 10071 default:
10072 abort ();
10073 return NULL;
10074 }
10075}
10076
47926f60 10077#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 10078
10079#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 10080void
10081i386_elf_emit_arch_note (void)
a847613f 10082{
718ddfc0 10083 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 10084 {
10085 char *p;
10086 asection *seg = now_seg;
10087 subsegT subseg = now_subseg;
10088 Elf_Internal_Note i_note;
10089 Elf_External_Note e_note;
10090 asection *note_secp;
10091 int len;
10092
10093 /* Create the .note section. */
10094 note_secp = subseg_new (".note", 0);
10095 bfd_set_section_flags (stdoutput,
10096 note_secp,
10097 SEC_HAS_CONTENTS | SEC_READONLY);
10098
10099 /* Process the arch string. */
10100 len = strlen (cpu_arch_name);
10101
10102 i_note.namesz = len + 1;
10103 i_note.descsz = 0;
10104 i_note.type = NT_ARCH;
10105 p = frag_more (sizeof (e_note.namesz));
10106 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
10107 p = frag_more (sizeof (e_note.descsz));
10108 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
10109 p = frag_more (sizeof (e_note.type));
10110 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
10111 p = frag_more (len + 1);
10112 strcpy (p, cpu_arch_name);
10113
10114 frag_align (2, 0, 0);
10115
10116 subseg_set (seg, subseg);
10117 }
10118}
10119#endif
252b5132 10120\f
252b5132 10121symbolS *
7016a5d5 10122md_undefined_symbol (char *name)
252b5132 10123{
18dc2407
ILT		 10124 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10125 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10126 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10127 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10128 {
10129 if (!GOT_symbol)
10130 {
10131 if (symbol_find (name))
10132 as_bad (_("GOT already in symbol table"));
10133 GOT_symbol = symbol_new (name, undefined_section,
10134 (valueT) 0, &zero_address_frag);
10135 };
10136 return GOT_symbol;
10137 }
252b5132
RH		 10138 return 0;
10139}
10140
10141/* Round up a section size to the appropriate boundary. */
47926f60 10142
252b5132 10143valueT
7016a5d5 10144md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10145{
4c63da97
AM		 10146#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10147 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10148 {
10149 /* For a.out, force the section size to be aligned. If we don't do
10150 this, BFD will align it for us, but it will not write out the
10151 final bytes of the section. This may be a bug in BFD, but it is
10152 easier to fix it here since that is how the other a.out targets
10153 work. */
10154 int align;
10155
10156 align = bfd_get_section_alignment (stdoutput, segment);
10157 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
10158 }
252b5132
RH		 10159#endif
10160
10161 return size;
10162}
10163
10164/* On the i386, PC-relative offsets are relative to the start of the
10165 next instruction. That is, the address of the offset, plus its
10166 size, since the offset is always the last part of the insn. */
10167
10168long
e3bb37b5 10169md_pcrel_from (fixS *fixP)
252b5132
RH		 10170{
10171 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10172}
10173
10174#ifndef I386COFF
10175
10176static void
e3bb37b5 10177s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10178{
29b0f896 10179 int temp;
252b5132 10180
8a75718c
JB		 10181#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10182 if (IS_ELF)
10183 obj_elf_section_change_hook ();
10184#endif
252b5132
RH		 10185 temp = get_absolute_expression ();
10186 subseg_set (bss_section, (subsegT) temp);
10187 demand_empty_rest_of_line ();
10188}
10189
10190#endif
10191
252b5132 10192void
e3bb37b5 10193i386_validate_fix (fixS *fixp)
252b5132
RH		 10194{
10195 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
10196 {
23df1078
JH		 10197 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10198 {
4fa24527 10199 if (!object_64bit)
23df1078
JH		 10200 abort ();
10201 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10202 }
10203 else
10204 {
4fa24527 10205 if (!object_64bit)
d6ab8113
JB		 10206 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10207 else
10208 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 10209 }
252b5132
RH		 10210 fixp->fx_subsy = 0;
10211 }
10212}
10213
252b5132 10214arelent *
7016a5d5 10215tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10216{
10217 arelent *rel;
10218 bfd_reloc_code_real_type code;
10219
10220 switch (fixp->fx_r_type)
10221 {
8ce3d284 10222#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10223 case BFD_RELOC_SIZE32:
10224 case BFD_RELOC_SIZE64:
10225 if (S_IS_DEFINED (fixp->fx_addsy)
10226 && !S_IS_EXTERNAL (fixp->fx_addsy))
10227 {
10228 /* Resolve size relocation against local symbol to size of
10229 the symbol plus addend. */
10230 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10231 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10232 && !fits_in_unsigned_long (value))
10233 as_bad_where (fixp->fx_file, fixp->fx_line,
10234 _("symbol size computation overflow"));
10235 fixp->fx_addsy = NULL;
10236 fixp->fx_subsy = NULL;
10237 md_apply_fix (fixp, (valueT *) &value, NULL);
10238 return NULL;
10239 }
8ce3d284 10240#endif
8fd4256d 10241
3e73aa7c
JH		 10242 case BFD_RELOC_X86_64_PLT32:
10243 case BFD_RELOC_X86_64_GOT32:
10244 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 10245 case BFD_RELOC_386_PLT32:
10246 case BFD_RELOC_386_GOT32:
10247 case BFD_RELOC_386_GOTOFF:
10248 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10249 case BFD_RELOC_386_TLS_GD:
10250 case BFD_RELOC_386_TLS_LDM:
10251 case BFD_RELOC_386_TLS_LDO_32:
10252 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10253 case BFD_RELOC_386_TLS_IE:
10254 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10255 case BFD_RELOC_386_TLS_LE_32:
10256 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10257 case BFD_RELOC_386_TLS_GOTDESC:
10258 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10259 case BFD_RELOC_X86_64_TLSGD:
10260 case BFD_RELOC_X86_64_TLSLD:
10261 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10262 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10263 case BFD_RELOC_X86_64_GOTTPOFF:
10264 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10265 case BFD_RELOC_X86_64_TPOFF64:
10266 case BFD_RELOC_X86_64_GOTOFF64:
10267 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10268 case BFD_RELOC_X86_64_GOT64:
10269 case BFD_RELOC_X86_64_GOTPCREL64:
10270 case BFD_RELOC_X86_64_GOTPC64:
10271 case BFD_RELOC_X86_64_GOTPLT64:
10272 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10273 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10274 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10275 case BFD_RELOC_RVA:
10276 case BFD_RELOC_VTABLE_ENTRY:
10277 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10278#ifdef TE_PE
10279 case BFD_RELOC_32_SECREL:
10280#endif
252b5132
RH		 10281 code = fixp->fx_r_type;
10282 break;
dbbaec26
L		 10283 case BFD_RELOC_X86_64_32S:
10284 if (!fixp->fx_pcrel)
10285 {
10286 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10287 code = fixp->fx_r_type;
10288 break;
10289 }
252b5132 10290 default:
93382f6d 10291 if (fixp->fx_pcrel)
252b5132 10292 {
93382f6d
AM		 10293 switch (fixp->fx_size)
10294 {
10295 default:
b091f402
AM		 10296 as_bad_where (fixp->fx_file, fixp->fx_line,
10297 _("can not do %d byte pc-relative relocation"),
10298 fixp->fx_size);
93382f6d
AM		 10299 code = BFD_RELOC_32_PCREL;
10300 break;
10301 case 1: code = BFD_RELOC_8_PCREL; break;
10302 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10303 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10304#ifdef BFD64
10305 case 8: code = BFD_RELOC_64_PCREL; break;
10306#endif
93382f6d
AM		 10307 }
10308 }
10309 else
10310 {
10311 switch (fixp->fx_size)
10312 {
10313 default:
b091f402
AM		 10314 as_bad_where (fixp->fx_file, fixp->fx_line,
10315 _("can not do %d byte relocation"),
10316 fixp->fx_size);
93382f6d
AM		 10317 code = BFD_RELOC_32;
10318 break;
10319 case 1: code = BFD_RELOC_8; break;
10320 case 2: code = BFD_RELOC_16; break;
10321 case 4: code = BFD_RELOC_32; break;
937149dd 10322#ifdef BFD64
3e73aa7c 10323 case 8: code = BFD_RELOC_64; break;
937149dd 10324#endif
93382f6d 10325 }
252b5132
RH		 10326 }
10327 break;
10328 }
252b5132 10329
d182319b
JB		 10330 if ((code == BFD_RELOC_32
10331 || code == BFD_RELOC_32_PCREL
10332 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10333 && GOT_symbol
10334 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10335 {
4fa24527 10336 if (!object_64bit)
d6ab8113
JB		 10337 code = BFD_RELOC_386_GOTPC;
10338 else
10339 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10340 }
7b81dfbb
AJ		 10341 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10342 && GOT_symbol
10343 && fixp->fx_addsy == GOT_symbol)
10344 {
10345 code = BFD_RELOC_X86_64_GOTPC64;
10346 }
252b5132
RH		 10347
10348 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 10349 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10350 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10351
10352 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10353
3e73aa7c
JH		 10354 if (!use_rela_relocations)
10355 {
10356 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10357 vtable entry to be used in the relocation's section offset. */
10358 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10359 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10360#if defined (OBJ_COFF) && defined (TE_PE)
10361 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10362 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10363 else
10364#endif
c6682705 10365 rel->addend = 0;
3e73aa7c
JH		 10366 }
10367 /* Use the rela in 64bit mode. */
252b5132 10368 else
3e73aa7c 10369 {
862be3fb
L		 10370 if (disallow_64bit_reloc)
10371 switch (code)
10372 {
862be3fb
L		 10373 case BFD_RELOC_X86_64_DTPOFF64:
10374 case BFD_RELOC_X86_64_TPOFF64:
10375 case BFD_RELOC_64_PCREL:
10376 case BFD_RELOC_X86_64_GOTOFF64:
10377 case BFD_RELOC_X86_64_GOT64:
10378 case BFD_RELOC_X86_64_GOTPCREL64:
10379 case BFD_RELOC_X86_64_GOTPC64:
10380 case BFD_RELOC_X86_64_GOTPLT64:
10381 case BFD_RELOC_X86_64_PLTOFF64:
10382 as_bad_where (fixp->fx_file, fixp->fx_line,
10383 _("cannot represent relocation type %s in x32 mode"),
10384 bfd_get_reloc_code_name (code));
10385 break;
10386 default:
10387 break;
10388 }
10389
062cd5e7
AS		 10390 if (!fixp->fx_pcrel)
10391 rel->addend = fixp->fx_offset;
10392 else
10393 switch (code)
10394 {
10395 case BFD_RELOC_X86_64_PLT32:
10396 case BFD_RELOC_X86_64_GOT32:
10397 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 10398 case BFD_RELOC_X86_64_TLSGD:
10399 case BFD_RELOC_X86_64_TLSLD:
10400 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10401 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10402 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10403 rel->addend = fixp->fx_offset - fixp->fx_size;
10404 break;
10405 default:
10406 rel->addend = (section->vma
10407 - fixp->fx_size
10408 + fixp->fx_addnumber
10409 + md_pcrel_from (fixp));
10410 break;
10411 }
3e73aa7c
JH		 10412 }
10413
252b5132
RH		 10414 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10415 if (rel->howto == NULL)
10416 {
10417 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10418 _("cannot represent relocation type %s"),
252b5132
RH		 10419 bfd_get_reloc_code_name (code));
10420 /* Set howto to a garbage value so that we can keep going. */
10421 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10422 gas_assert (rel->howto != NULL);
252b5132
RH		 10423 }
10424
10425 return rel;
10426}
10427
ee86248c 10428#include "tc-i386-intel.c"
54cfded0 10429
a60de03c
JB		 10430void
10431tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10432{
a60de03c
JB		 10433 int saved_naked_reg;
10434 char saved_register_dot;
54cfded0 10435
a60de03c
JB		 10436 saved_naked_reg = allow_naked_reg;
10437 allow_naked_reg = 1;
10438 saved_register_dot = register_chars['.'];
10439 register_chars['.'] = '.';
10440 allow_pseudo_reg = 1;
10441 expression_and_evaluate (exp);
10442 allow_pseudo_reg = 0;
10443 register_chars['.'] = saved_register_dot;
10444 allow_naked_reg = saved_naked_reg;
10445
e96d56a1 10446 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10447 {
a60de03c
JB		 10448 if ((addressT) exp->X_add_number < i386_regtab_size)
10449 {
10450 exp->X_op = O_constant;
10451 exp->X_add_number = i386_regtab[exp->X_add_number]
10452 .dw2_regnum[flag_code >> 1];
10453 }
10454 else
10455 exp->X_op = O_illegal;
54cfded0 10456 }
54cfded0
AM		 10457}
10458
10459void
10460tc_x86_frame_initial_instructions (void)
10461{
a60de03c
JB		 10462 static unsigned int sp_regno[2];
10463
10464 if (!sp_regno[flag_code >> 1])
10465 {
10466 char *saved_input = input_line_pointer;
10467 char sp[][4] = {"esp", "rsp"};
10468 expressionS exp;
a4447b93 10469
a60de03c
JB		 10470 input_line_pointer = sp[flag_code >> 1];
10471 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10472 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10473 sp_regno[flag_code >> 1] = exp.X_add_number;
10474 input_line_pointer = saved_input;
10475 }
a4447b93 10476
61ff971f
L		 10477 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10478 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10479}
d2b2c203 10480
d7921315
L		 10481int
10482x86_dwarf2_addr_size (void)
10483{
10484#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10485 if (x86_elf_abi == X86_64_X32_ABI)
10486 return 4;
10487#endif
10488 return bfd_arch_bits_per_address (stdoutput) / 8;
10489}
10490
d2b2c203
DJ		 10491int
10492i386_elf_section_type (const char *str, size_t len)
10493{
10494 if (flag_code == CODE_64BIT
10495 && len == sizeof ("unwind") - 1
10496 && strncmp (str, "unwind", 6) == 0)
10497 return SHT_X86_64_UNWIND;
10498
10499 return -1;
10500}
bb41ade5 10501
ad5fec3b
EB		 10502#ifdef TE_SOLARIS
10503void
10504i386_solaris_fix_up_eh_frame (segT sec)
10505{
10506 if (flag_code == CODE_64BIT)
10507 elf_section_type (sec) = SHT_X86_64_UNWIND;
10508}
10509#endif
10510
bb41ade5
AM		 10511#ifdef TE_PE
10512void
10513tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10514{
91d6fa6a 10515 expressionS exp;
bb41ade5 10516
91d6fa6a
NC		 10517 exp.X_op = O_secrel;
10518 exp.X_add_symbol = symbol;
10519 exp.X_add_number = 0;
10520 emit_expr (&exp, size);
bb41ade5
AM		 10521}
10522#endif
3b22753a
L		 10523
10524#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10525/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10526
01e1a5bc 10527bfd_vma
3b22753a
L		 10528x86_64_section_letter (int letter, char **ptr_msg)
10529{
10530 if (flag_code == CODE_64BIT)
10531 {
10532 if (letter == 'l')
10533 return SHF_X86_64_LARGE;
10534
8f3bae45 10535 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10536 }
3b22753a 10537 else
8f3bae45 10538 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10539 return -1;
10540}
10541
01e1a5bc 10542bfd_vma
3b22753a
L		 10543x86_64_section_word (char *str, size_t len)
10544{
8620418b 10545 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10546 return SHF_X86_64_LARGE;
10547
10548 return -1;
10549}
10550
10551static void
10552handle_large_common (int small ATTRIBUTE_UNUSED)
10553{
10554 if (flag_code != CODE_64BIT)
10555 {
10556 s_comm_internal (0, elf_common_parse);
10557 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10558 }
10559 else
10560 {
10561 static segT lbss_section;
10562 asection *saved_com_section_ptr = elf_com_section_ptr;
10563 asection *saved_bss_section = bss_section;
10564
10565 if (lbss_section == NULL)
10566 {
10567 flagword applicable;
10568 segT seg = now_seg;
10569 subsegT subseg = now_subseg;
10570
10571 /* The .lbss section is for local .largecomm symbols. */
10572 lbss_section = subseg_new (".lbss", 0);
10573 applicable = bfd_applicable_section_flags (stdoutput);
10574 bfd_set_section_flags (stdoutput, lbss_section,
10575 applicable & SEC_ALLOC);
10576 seg_info (lbss_section)->bss = 1;
10577
10578 subseg_set (seg, subseg);
10579 }
10580
10581 elf_com_section_ptr = &_bfd_elf_large_com_section;
10582 bss_section = lbss_section;
10583
10584 s_comm_internal (0, elf_common_parse);
10585
10586 elf_com_section_ptr = saved_com_section_ptr;
10587 bss_section = saved_bss_section;
10588 }
10589}
10590#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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