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There were several cases where the registers in the REX encoded range
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
d382c579
TG		 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
4 2012
47926f60 5 Free Software Foundation, Inc.
252b5132
RH		 6
7 This file is part of GAS, the GNU Assembler.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
ec2655a6 11 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 12 any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 21 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
22 02110-1301, USA. */
252b5132 23
47926f60
KH		 24/* Intel 80386 machine specific gas.
25 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 26 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 28 Bugs & suggestions are completely welcome. This is free software.
29 Please help us make it better. */
252b5132 30
252b5132 31#include "as.h"
3882b010 32#include "safe-ctype.h"
252b5132 33#include "subsegs.h"
316e2c05 34#include "dwarf2dbg.h"
54cfded0 35#include "dw2gencfi.h"
d2b2c203 36#include "elf/x86-64.h"
40fb9820 37#include "opcodes/i386-init.h"
252b5132 38
252b5132
RH		 39#ifndef REGISTER_WARNINGS
40#define REGISTER_WARNINGS 1
41#endif
42
c3332e24 43#ifndef INFER_ADDR_PREFIX
eecb386c 44#define INFER_ADDR_PREFIX 1
c3332e24
AM		 45#endif
46
29b0f896
AM		 47#ifndef DEFAULT_ARCH
48#define DEFAULT_ARCH "i386"
246fcdee 49#endif
252b5132 50
edde18a5
AM		 51#ifndef INLINE
52#if __GNUC__ >= 2
53#define INLINE __inline__
54#else
55#define INLINE
56#endif
57#endif
58
6305a203
L		 59/* Prefixes will be emitted in the order defined below.
60 WAIT_PREFIX must be the first prefix since FWAIT is really is an
61 instruction, and so must come before any prefixes.
62 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 63 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 64#define WAIT_PREFIX 0
65#define SEG_PREFIX 1
66#define ADDR_PREFIX 2
67#define DATA_PREFIX 3
c32fa91d 68#define REP_PREFIX 4
42164a71 69#define HLE_PREFIX REP_PREFIX
c32fa91d
L		 70#define LOCK_PREFIX 5
71#define REX_PREFIX 6 /* must come last. */
72#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 73
74/* we define the syntax here (modulo base,index,scale syntax) */
75#define REGISTER_PREFIX '%'
76#define IMMEDIATE_PREFIX '$'
77#define ABSOLUTE_PREFIX '*'
78
79/* these are the instruction mnemonic suffixes in AT&T syntax or
80 memory operand size in Intel syntax. */
81#define WORD_MNEM_SUFFIX 'w'
82#define BYTE_MNEM_SUFFIX 'b'
83#define SHORT_MNEM_SUFFIX 's'
84#define LONG_MNEM_SUFFIX 'l'
85#define QWORD_MNEM_SUFFIX 'q'
86#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 87#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 88/* Intel Syntax. Use a non-ascii letter since since it never appears
89 in instructions. */
90#define LONG_DOUBLE_MNEM_SUFFIX '\1'
91
92#define END_OF_INSN '\0'
93
94/*
95 'templates' is for grouping together 'template' structures for opcodes
96 of the same name. This is only used for storing the insns in the grand
97 ole hash table of insns.
98 The templates themselves start at START and range up to (but not including)
99 END.
100 */
101typedef struct
102{
d3ce72d0
NC		 103 const insn_template *start;
104 const insn_template *end;
6305a203
L		 105}
106templates;
107
108/* 386 operand encoding bytes: see 386 book for details of this. */
109typedef struct
110{
111 unsigned int regmem; /* codes register or memory operand */
112 unsigned int reg; /* codes register operand (or extended opcode) */
113 unsigned int mode; /* how to interpret regmem & reg */
114}
115modrm_byte;
116
117/* x86-64 extension prefix. */
118typedef int rex_byte;
119
6305a203
L		 120/* 386 opcode byte to code indirect addressing. */
121typedef struct
122{
123 unsigned base;
124 unsigned index;
125 unsigned scale;
126}
127sib_byte;
128
6305a203
L		 129/* x86 arch names, types and features */
130typedef struct
131{
132 const char *name; /* arch name */
8a2c8fef 133 unsigned int len; /* arch string length */
6305a203
L		 134 enum processor_type type; /* arch type */
135 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 136 unsigned int skip; /* show_arch should skip this. */
22109423 137 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 138}
139arch_entry;
140
78f12dd3 141static void update_code_flag (int, int);
e3bb37b5
L		 142static void set_code_flag (int);
143static void set_16bit_gcc_code_flag (int);
144static void set_intel_syntax (int);
1efbbeb4 145static void set_intel_mnemonic (int);
db51cc60 146static void set_allow_index_reg (int);
cb19c032 147static void set_sse_check (int);
e3bb37b5 148static void set_cpu_arch (int);
6482c264 149#ifdef TE_PE
e3bb37b5 150static void pe_directive_secrel (int);
6482c264 151#endif
e3bb37b5
L		 152static void signed_cons (int);
153static char *output_invalid (int c);
ee86248c
JB		 154static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
155 const char *);
156static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
157 const char *);
a7619375 158static int i386_att_operand (char *);
e3bb37b5 159static int i386_intel_operand (char *, int);
ee86248c
JB		 160static int i386_intel_simplify (expressionS *);
161static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 162static const reg_entry *parse_register (char *, char **);
163static char *parse_insn (char *, char *);
164static char *parse_operands (char *, const char *);
165static void swap_operands (void);
4d456e3d 166static void swap_2_operands (int, int);
e3bb37b5
L		 167static void optimize_imm (void);
168static void optimize_disp (void);
d3ce72d0 169static const insn_template *match_template (void);
e3bb37b5
L		 170static int check_string (void);
171static int process_suffix (void);
172static int check_byte_reg (void);
173static int check_long_reg (void);
174static int check_qword_reg (void);
175static int check_word_reg (void);
176static int finalize_imm (void);
177static int process_operands (void);
178static const seg_entry *build_modrm_byte (void);
179static void output_insn (void);
180static void output_imm (fragS *, offsetT);
181static void output_disp (fragS *, offsetT);
29b0f896 182#ifndef I386COFF
e3bb37b5 183static void s_bss (int);
252b5132 184#endif
17d4e2a2
L		 185#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
186static void handle_large_common (int small ATTRIBUTE_UNUSED);
187#endif
252b5132 188
a847613f 189static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 190
c0f3af97
L		 191/* VEX prefix. */
192typedef struct
193{
194 /* VEX prefix is either 2 byte or 3 byte. */
195 unsigned char bytes[3];
196 unsigned int length;
197 /* Destination or source register specifier. */
198 const reg_entry *register_specifier;
199} vex_prefix;
200
252b5132 201/* 'md_assemble ()' gathers together information and puts it into a
47926f60 202 i386_insn. */
252b5132 203
520dc8e8
AM		 204union i386_op
205 {
206 expressionS *disps;
207 expressionS *imms;
208 const reg_entry *regs;
209 };
210
a65babc9
L		 211enum i386_error
212 {
86e026a4 213 operand_size_mismatch,
a65babc9
L		 214 operand_type_mismatch,
215 register_type_mismatch,
216 number_of_operands_mismatch,
217 invalid_instruction_suffix,
218 bad_imm4,
219 old_gcc_only,
220 unsupported_with_intel_mnemonic,
221 unsupported_syntax,
6c30d220
L		 222 unsupported,
223 invalid_vsib_address,
224 unsupported_vector_index_register
a65babc9
L		 225 };
226
252b5132
RH		 227struct _i386_insn
228 {
47926f60 229 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 230 insn_template tm;
252b5132 231
7d5e4556
L		 232 /* SUFFIX holds the instruction size suffix for byte, word, dword
233 or qword, if given. */
252b5132
RH		 234 char suffix;
235
47926f60 236 /* OPERANDS gives the number of given operands. */
252b5132
RH		 237 unsigned int operands;
238
239 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
240 of given register, displacement, memory operands and immediate
47926f60 241 operands. */
252b5132
RH		 242 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
243
244 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 245 use OP[i] for the corresponding operand. */
40fb9820 246 i386_operand_type types[MAX_OPERANDS];
252b5132 247
520dc8e8
AM		 248 /* Displacement expression, immediate expression, or register for each
249 operand. */
250 union i386_op op[MAX_OPERANDS];
252b5132 251
3e73aa7c
JH		 252 /* Flags for operands. */
253 unsigned int flags[MAX_OPERANDS];
254#define Operand_PCrel 1
255
252b5132 256 /* Relocation type for operand */
f86103b7 257 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 258
252b5132
RH		 259 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
260 the base index byte below. */
261 const reg_entry *base_reg;
262 const reg_entry *index_reg;
263 unsigned int log2_scale_factor;
264
265 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 266 explicit segment overrides are given. */
ce8a8b2f 267 const seg_entry *seg[2];
252b5132
RH		 268
269 /* PREFIX holds all the given prefix opcodes (usually null).
270 PREFIXES is the number of prefix opcodes. */
271 unsigned int prefixes;
272 unsigned char prefix[MAX_PREFIXES];
273
274 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 275 addressing modes of this insn are encoded. */
252b5132 276 modrm_byte rm;
3e73aa7c 277 rex_byte rex;
252b5132 278 sib_byte sib;
c0f3af97 279 vex_prefix vex;
b6169b20
L		 280
281 /* Swap operand in encoding. */
4473e004 282 unsigned int swap_operand;
891edac4 283
a501d77e
L		 284 /* Prefer 8bit or 32bit displacement in encoding. */
285 enum
286 {
287 disp_encoding_default = 0,
288 disp_encoding_8bit,
289 disp_encoding_32bit
290 } disp_encoding;
f8a5c266 291
42164a71
L		 292 /* Have HLE prefix. */
293 unsigned int have_hle;
294
891edac4 295 /* Error message. */
a65babc9 296 enum i386_error error;
252b5132
RH		 297 };
298
299typedef struct _i386_insn i386_insn;
300
301/* List of chars besides those in app.c:symbol_chars that can start an
302 operand. Used to prevent the scrubber eating vital white-space. */
32137342 303const char extra_symbol_chars[] = "*%-(["
252b5132 304#ifdef LEX_AT
32137342
NC		 305 "@"
306#endif
307#ifdef LEX_QM
308 "?"
252b5132 309#endif
32137342 310 ;
252b5132 311
29b0f896
AM		 312#if (defined (TE_I386AIX) \
313 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 314 && !defined (TE_GNU) \
29b0f896 315 && !defined (TE_LINUX) \
8d63c93e
RM		 316 && !defined (TE_NACL) \
317 && !defined (TE_NETWARE) \
29b0f896 318 && !defined (TE_FreeBSD) \
5b806d27 319 && !defined (TE_DragonFly) \
29b0f896 320 && !defined (TE_NetBSD)))
252b5132 321/* This array holds the chars that always start a comment. If the
b3b91714
AM		 322 pre-processor is disabled, these aren't very useful. The option
323 --divide will remove '/' from this list. */
324const char *i386_comment_chars = "#/";
325#define SVR4_COMMENT_CHARS 1
252b5132 326#define PREFIX_SEPARATOR '\\'
252b5132 327
b3b91714
AM		 328#else
329const char *i386_comment_chars = "#";
330#define PREFIX_SEPARATOR '/'
331#endif
332
252b5132
RH		 333/* This array holds the chars that only start a comment at the beginning of
334 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 335 .line and .file directives will appear in the pre-processed output.
336 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 337 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 338 #NO_APP at the beginning of its output.
339 Also note that comments started like this one will always work if
252b5132 340 '/' isn't otherwise defined. */
b3b91714 341const char line_comment_chars[] = "#/";
252b5132 342
63a0b638 343const char line_separator_chars[] = ";";
252b5132 344
ce8a8b2f
AM		 345/* Chars that can be used to separate mant from exp in floating point
346 nums. */
252b5132
RH		 347const char EXP_CHARS[] = "eE";
348
ce8a8b2f
AM		 349/* Chars that mean this number is a floating point constant
350 As in 0f12.456
351 or 0d1.2345e12. */
252b5132
RH		 352const char FLT_CHARS[] = "fFdDxX";
353
ce8a8b2f 354/* Tables for lexical analysis. */
252b5132
RH		 355static char mnemonic_chars[256];
356static char register_chars[256];
357static char operand_chars[256];
358static char identifier_chars[256];
359static char digit_chars[256];
360
ce8a8b2f 361/* Lexical macros. */
252b5132
RH		 362#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
363#define is_operand_char(x) (operand_chars[(unsigned char) x])
364#define is_register_char(x) (register_chars[(unsigned char) x])
365#define is_space_char(x) ((x) == ' ')
366#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
367#define is_digit_char(x) (digit_chars[(unsigned char) x])
368
0234cb7c 369/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 370static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
371
372/* md_assemble() always leaves the strings it's passed unaltered. To
373 effect this we maintain a stack of saved characters that we've smashed
374 with '\0's (indicating end of strings for various sub-fields of the
47926f60 375 assembler instruction). */
252b5132 376static char save_stack[32];
ce8a8b2f 377static char *save_stack_p;
252b5132
RH		 378#define END_STRING_AND_SAVE(s) \
379 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
380#define RESTORE_END_STRING(s) \
381 do { *(s) = *--save_stack_p; } while (0)
382
47926f60 383/* The instruction we're assembling. */
252b5132
RH		 384static i386_insn i;
385
386/* Possible templates for current insn. */
387static const templates *current_templates;
388
31b2323c
L		 389/* Per instruction expressionS buffers: max displacements & immediates. */
390static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
391static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 392
47926f60 393/* Current operand we are working on. */
ee86248c 394static int this_operand = -1;
252b5132 395
3e73aa7c
JH		 396/* We support four different modes. FLAG_CODE variable is used to distinguish
397 these. */
398
399enum flag_code {
400 CODE_32BIT,
401 CODE_16BIT,
402 CODE_64BIT };
403
404static enum flag_code flag_code;
4fa24527 405static unsigned int object_64bit;
862be3fb 406static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 407static int use_rela_relocations = 0;
408
7af8ed2d
NC		 409#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
410 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
411 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
412
351f65ca
L		 413/* The ELF ABI to use. */
414enum x86_elf_abi
415{
416 I386_ABI,
7f56bc95
L		 417 X86_64_ABI,
418 X86_64_X32_ABI
351f65ca
L		 419};
420
421static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 422#endif
351f65ca 423
3e73aa7c 424/* The names used to print error messages. */
b77a7acd 425static const char *flag_code_names[] =
3e73aa7c
JH		 426 {
427 "32",
428 "16",
429 "64"
430 };
252b5132 431
47926f60
KH		 432/* 1 for intel syntax,
433 0 if att syntax. */
434static int intel_syntax = 0;
252b5132 435
1efbbeb4
L		 436/* 1 for intel mnemonic,
437 0 if att mnemonic. */
438static int intel_mnemonic = !SYSV386_COMPAT;
439
5209009a 440/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 441static int old_gcc = OLDGCC_COMPAT;
442
a60de03c
JB		 443/* 1 if pseudo registers are permitted. */
444static int allow_pseudo_reg = 0;
445
47926f60
KH		 446/* 1 if register prefix % not required. */
447static int allow_naked_reg = 0;
252b5132 448
ba104c83 449/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 450static int allow_index_reg = 0;
451
daf50ae7
L		 452static enum
453 {
454 sse_check_none = 0,
455 sse_check_warning,
456 sse_check_error
457 }
458sse_check;
459
2ca3ace5
L		 460/* Register prefix used for error message. */
461static const char *register_prefix = "%";
462
47926f60
KH		 463/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
464 leave, push, and pop instructions so that gcc has the same stack
465 frame as in 32 bit mode. */
466static char stackop_size = '\0';
eecb386c 467
12b55ccc
L		 468/* Non-zero to optimize code alignment. */
469int optimize_align_code = 1;
470
47926f60
KH		 471/* Non-zero to quieten some warnings. */
472static int quiet_warnings = 0;
a38cf1db 473
47926f60
KH		 474/* CPU name. */
475static const char *cpu_arch_name = NULL;
6305a203 476static char *cpu_sub_arch_name = NULL;
a38cf1db 477
47926f60 478/* CPU feature flags. */
40fb9820
L		 479static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
480
ccc9c027
L		 481/* If we have selected a cpu we are generating instructions for. */
482static int cpu_arch_tune_set = 0;
483
9103f4f4 484/* Cpu we are generating instructions for. */
fbf3f584 485enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 486
487/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 488static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 489
ccc9c027 490/* CPU instruction set architecture used. */
fbf3f584 491enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 492
9103f4f4 493/* CPU feature flags of instruction set architecture used. */
fbf3f584 494i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 495
fddf5b5b
AM		 496/* If set, conditional jumps are not automatically promoted to handle
497 larger than a byte offset. */
498static unsigned int no_cond_jump_promotion = 0;
499
c0f3af97
L		 500/* Encode SSE instructions with VEX prefix. */
501static unsigned int sse2avx;
502
539f890d
L		 503/* Encode scalar AVX instructions with specific vector length. */
504static enum
505 {
506 vex128 = 0,
507 vex256
508 } avxscalar;
509
29b0f896 510/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 511static symbolS *GOT_symbol;
29b0f896 512
a4447b93
RH		 513/* The dwarf2 return column, adjusted for 32 or 64 bit. */
514unsigned int x86_dwarf2_return_column;
515
516/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
517int x86_cie_data_alignment;
518
252b5132 519/* Interface to relax_segment.
fddf5b5b
AM		 520 There are 3 major relax states for 386 jump insns because the
521 different types of jumps add different sizes to frags when we're
522 figuring out what sort of jump to choose to reach a given label. */
252b5132 523
47926f60 524/* Types. */
93c2a809
AM		 525#define UNCOND_JUMP 0
526#define COND_JUMP 1
527#define COND_JUMP86 2
fddf5b5b 528
47926f60 529/* Sizes. */
252b5132
RH		 530#define CODE16 1
531#define SMALL 0
29b0f896 532#define SMALL16 (SMALL | CODE16)
252b5132 533#define BIG 2
29b0f896 534#define BIG16 (BIG | CODE16)
252b5132
RH		 535
536#ifndef INLINE
537#ifdef __GNUC__
538#define INLINE __inline__
539#else
540#define INLINE
541#endif
542#endif
543
fddf5b5b
AM		 544#define ENCODE_RELAX_STATE(type, size) \
545 ((relax_substateT) (((type) << 2) | (size)))
546#define TYPE_FROM_RELAX_STATE(s) \
547 ((s) >> 2)
548#define DISP_SIZE_FROM_RELAX_STATE(s) \
549 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 550
551/* This table is used by relax_frag to promote short jumps to long
552 ones where necessary. SMALL (short) jumps may be promoted to BIG
553 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
554 don't allow a short jump in a 32 bit code segment to be promoted to
555 a 16 bit offset jump because it's slower (requires data size
556 prefix), and doesn't work, unless the destination is in the bottom
557 64k of the code segment (The top 16 bits of eip are zeroed). */
558
559const relax_typeS md_relax_table[] =
560{
24eab124
AM		 561 /* The fields are:
562 1) most positive reach of this state,
563 2) most negative reach of this state,
93c2a809 564 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 565 4) which index into the table to try if we can't fit into this one. */
252b5132 566
fddf5b5b 567 /* UNCOND_JUMP states. */
93c2a809
AM		 568 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
569 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
570 /* dword jmp adds 4 bytes to frag:
571 0 extra opcode bytes, 4 displacement bytes. */
252b5132 572 {0, 0, 4, 0},
93c2a809
AM		 573 /* word jmp adds 2 byte2 to frag:
574 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 575 {0, 0, 2, 0},
576
93c2a809
AM		 577 /* COND_JUMP states. */
578 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
579 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
580 /* dword conditionals adds 5 bytes to frag:
581 1 extra opcode byte, 4 displacement bytes. */
582 {0, 0, 5, 0},
fddf5b5b 583 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 584 1 extra opcode byte, 2 displacement bytes. */
585 {0, 0, 3, 0},
586
587 /* COND_JUMP86 states. */
588 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
589 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
590 /* dword conditionals adds 5 bytes to frag:
591 1 extra opcode byte, 4 displacement bytes. */
592 {0, 0, 5, 0},
593 /* word conditionals add 4 bytes to frag:
594 1 displacement byte and a 3 byte long branch insn. */
595 {0, 0, 4, 0}
252b5132
RH		 596};
597
9103f4f4
L		 598static const arch_entry cpu_arch[] =
599{
89507696
JB		 600 /* Do not replace the first two entries - i386_target_format()
601 relies on them being there in this order. */
8a2c8fef 602 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 603 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 604 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 605 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 606 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 607 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 608 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 609 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 610 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 611 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 612 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 613 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 614 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 615 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 616 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 617 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 618 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 619 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 620 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 621 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 622 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 623 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 624 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 625 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 626 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 627 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 628 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 629 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 630 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 631 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 632 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 633 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 634 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 635 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 636 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 637 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 638 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 639 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 640 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 641 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 642 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 643 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 644 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 645 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 646 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
647 CPU_K1OM_FLAGS, 0, 0 },
8a2c8fef 648 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 649 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 650 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 651 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 652 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 653 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 654 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 655 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 656 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 657 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 658 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 659 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 660 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 661 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 662 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 663 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 664 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 665 CPU_BDVER2_FLAGS, 0, 0 },
8a2c8fef 666 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 667 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 668 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 669 CPU_287_FLAGS, 0, 0 },
8a2c8fef 670 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 671 CPU_387_FLAGS, 0, 0 },
8a2c8fef 672 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 673 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 674 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 675 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 676 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 677 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 678 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 679 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 680 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 681 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 682 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 683 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 684 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 685 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 686 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 687 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 688 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 689 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 690 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 691 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 692 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 693 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 694 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 695 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 696 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
697 CPU_AVX2_FLAGS, 0, 0 },
8a2c8fef 698 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 699 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 700 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 701 CPU_VMX_FLAGS, 0, 0 },
8729a6f6
L		 702 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
703 CPU_VMFUNC_FLAGS, 0, 0 },
8a2c8fef 704 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 705 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 706 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 707 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 708 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 709 CPU_XSAVEOPT_FLAGS, 0, 0 },
8a2c8fef 710 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 711 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 712 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 713 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 714 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 715 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 716 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 717 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 718 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 719 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 720 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 721 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 722 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
723 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 724 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 725 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 726 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 727 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 728 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 729 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 730 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 731 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 732 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 733 CPU_MOVBE_FLAGS, 0, 0 },
8a2c8fef 734 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 735 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 736 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
737 CPU_LZCNT_FLAGS, 0, 0 },
42164a71
L		 738 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
739 CPU_HLE_FLAGS, 0, 0 },
740 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
741 CPU_RTM_FLAGS, 0, 0 },
6c30d220
L		 742 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
743 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 744 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 745 CPU_CLFLUSH_FLAGS, 0, 0 },
746 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
747 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 748 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 749 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 750 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 751 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 752 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 753 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 754 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 755 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 756 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 757 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 758 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 759 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 760 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 761 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 762 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 763 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 764 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 765 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 766 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
767 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 768 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
769 CPU_TBM_FLAGS, 0, 0 },
e2e1fcde
L		 770 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
771 CPU_ADX_FLAGS, 0, 0 },
772 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
773 CPU_RDSEED_FLAGS, 0, 0 },
774 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
775 CPU_PRFCHW_FLAGS, 0, 0 },
e413e4e9
AM		 776};
777
704209c0 778#ifdef I386COFF
a6c24e68
NC		 779/* Like s_lcomm_internal in gas/read.c but the alignment string
780 is allowed to be optional. */
781
782static symbolS *
783pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
784{
785 addressT align = 0;
786
787 SKIP_WHITESPACE ();
788
7ab9ffdd 789 if (needs_align
a6c24e68
NC		 790 && *input_line_pointer == ',')
791 {
792 align = parse_align (needs_align - 1);
7ab9ffdd 793
a6c24e68
NC		 794 if (align == (addressT) -1)
795 return NULL;
796 }
797 else
798 {
799 if (size >= 8)
800 align = 3;
801 else if (size >= 4)
802 align = 2;
803 else if (size >= 2)
804 align = 1;
805 else
806 align = 0;
807 }
808
809 bss_alloc (symbolP, size, align);
810 return symbolP;
811}
812
704209c0 813static void
a6c24e68
NC		 814pe_lcomm (int needs_align)
815{
816 s_comm_internal (needs_align * 2, pe_lcomm_internal);
817}
704209c0 818#endif
a6c24e68 819
29b0f896
AM		 820const pseudo_typeS md_pseudo_table[] =
821{
822#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
823 {"align", s_align_bytes, 0},
824#else
825 {"align", s_align_ptwo, 0},
826#endif
827 {"arch", set_cpu_arch, 0},
828#ifndef I386COFF
829 {"bss", s_bss, 0},
a6c24e68
NC		 830#else
831 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 832#endif
833 {"ffloat", float_cons, 'f'},
834 {"dfloat", float_cons, 'd'},
835 {"tfloat", float_cons, 'x'},
836 {"value", cons, 2},
d182319b 837 {"slong", signed_cons, 4},
29b0f896
AM		 838 {"noopt", s_ignore, 0},
839 {"optim", s_ignore, 0},
840 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
841 {"code16", set_code_flag, CODE_16BIT},
842 {"code32", set_code_flag, CODE_32BIT},
843 {"code64", set_code_flag, CODE_64BIT},
844 {"intel_syntax", set_intel_syntax, 1},
845 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 846 {"intel_mnemonic", set_intel_mnemonic, 1},
847 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 848 {"allow_index_reg", set_allow_index_reg, 1},
849 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 850 {"sse_check", set_sse_check, 0},
3b22753a
L		 851#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
852 {"largecomm", handle_large_common, 0},
07a53e5c 853#else
e3bb37b5 854 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 855 {"loc", dwarf2_directive_loc, 0},
856 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 857#endif
6482c264
NC		 858#ifdef TE_PE
859 {"secrel32", pe_directive_secrel, 0},
860#endif
29b0f896
AM		 861 {0, 0, 0}
862};
863
864/* For interface with expression (). */
865extern char *input_line_pointer;
866
867/* Hash table for instruction mnemonic lookup. */
868static struct hash_control *op_hash;
869
870/* Hash table for register lookup. */
871static struct hash_control *reg_hash;
872\f
252b5132 873void
e3bb37b5 874i386_align_code (fragS *fragP, int count)
252b5132 875{
ce8a8b2f
AM		 876 /* Various efficient no-op patterns for aligning code labels.
877 Note: Don't try to assemble the instructions in the comments.
878 0L and 0w are not legal. */
252b5132
RH		 879 static const char f32_1[] =
880 {0x90}; /* nop */
881 static const char f32_2[] =
ccc9c027 882 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 883 static const char f32_3[] =
884 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
885 static const char f32_4[] =
886 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
887 static const char f32_5[] =
888 {0x90, /* nop */
889 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
890 static const char f32_6[] =
891 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
892 static const char f32_7[] =
893 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
894 static const char f32_8[] =
895 {0x90, /* nop */
896 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
897 static const char f32_9[] =
898 {0x89,0xf6, /* movl %esi,%esi */
899 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
900 static const char f32_10[] =
901 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
902 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
903 static const char f32_11[] =
904 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
905 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
906 static const char f32_12[] =
907 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
908 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
909 static const char f32_13[] =
910 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
911 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
912 static const char f32_14[] =
913 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
914 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 915 static const char f16_3[] =
916 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 917 static const char f16_4[] =
918 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
919 static const char f16_5[] =
920 {0x90, /* nop */
921 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
922 static const char f16_6[] =
923 {0x89,0xf6, /* mov %si,%si */
924 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
925 static const char f16_7[] =
926 {0x8d,0x74,0x00, /* lea 0(%si),%si */
927 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
928 static const char f16_8[] =
929 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
930 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 931 static const char jump_31[] =
932 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
933 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
934 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
935 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 936 static const char *const f32_patt[] = {
937 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 938 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 939 };
940 static const char *const f16_patt[] = {
76bc74dc 941 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 942 };
ccc9c027
L		 943 /* nopl (%[re]ax) */
944 static const char alt_3[] =
945 {0x0f,0x1f,0x00};
946 /* nopl 0(%[re]ax) */
947 static const char alt_4[] =
948 {0x0f,0x1f,0x40,0x00};
949 /* nopl 0(%[re]ax,%[re]ax,1) */
950 static const char alt_5[] =
951 {0x0f,0x1f,0x44,0x00,0x00};
952 /* nopw 0(%[re]ax,%[re]ax,1) */
953 static const char alt_6[] =
954 {0x66,0x0f,0x1f,0x44,0x00,0x00};
955 /* nopl 0L(%[re]ax) */
956 static const char alt_7[] =
957 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
958 /* nopl 0L(%[re]ax,%[re]ax,1) */
959 static const char alt_8[] =
960 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
961 /* nopw 0L(%[re]ax,%[re]ax,1) */
962 static const char alt_9[] =
963 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
964 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
965 static const char alt_10[] =
966 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
967 /* data16
968 nopw %cs:0L(%[re]ax,%[re]ax,1) */
969 static const char alt_long_11[] =
970 {0x66,
971 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
972 /* data16
973 data16
974 nopw %cs:0L(%[re]ax,%[re]ax,1) */
975 static const char alt_long_12[] =
976 {0x66,
977 0x66,
978 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
979 /* data16
980 data16
981 data16
982 nopw %cs:0L(%[re]ax,%[re]ax,1) */
983 static const char alt_long_13[] =
984 {0x66,
985 0x66,
986 0x66,
987 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
988 /* data16
989 data16
990 data16
991 data16
992 nopw %cs:0L(%[re]ax,%[re]ax,1) */
993 static const char alt_long_14[] =
994 {0x66,
995 0x66,
996 0x66,
997 0x66,
998 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
999 /* data16
1000 data16
1001 data16
1002 data16
1003 data16
1004 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1005 static const char alt_long_15[] =
1006 {0x66,
1007 0x66,
1008 0x66,
1009 0x66,
1010 0x66,
1011 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1012 /* nopl 0(%[re]ax,%[re]ax,1)
1013 nopw 0(%[re]ax,%[re]ax,1) */
1014 static const char alt_short_11[] =
1015 {0x0f,0x1f,0x44,0x00,0x00,
1016 0x66,0x0f,0x1f,0x44,0x00,0x00};
1017 /* nopw 0(%[re]ax,%[re]ax,1)
1018 nopw 0(%[re]ax,%[re]ax,1) */
1019 static const char alt_short_12[] =
1020 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1021 0x66,0x0f,0x1f,0x44,0x00,0x00};
1022 /* nopw 0(%[re]ax,%[re]ax,1)
1023 nopl 0L(%[re]ax) */
1024 static const char alt_short_13[] =
1025 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1026 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1027 /* nopl 0L(%[re]ax)
1028 nopl 0L(%[re]ax) */
1029 static const char alt_short_14[] =
1030 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1031 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1032 /* nopl 0L(%[re]ax)
1033 nopl 0L(%[re]ax,%[re]ax,1) */
1034 static const char alt_short_15[] =
1035 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1036 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1037 static const char *const alt_short_patt[] = {
1038 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1039 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
1040 alt_short_14, alt_short_15
1041 };
1042 static const char *const alt_long_patt[] = {
1043 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1044 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1045 alt_long_14, alt_long_15
1046 };
252b5132 1047
76bc74dc
L		 1048 /* Only align for at least a positive non-zero boundary. */
1049 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1050 return;
3e73aa7c 1051
ccc9c027
L		 1052 /* We need to decide which NOP sequence to use for 32bit and
1053 64bit. When -mtune= is used:
4eed87de 1054
76bc74dc
L		 1055 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1056 PROCESSOR_GENERIC32, f32_patt will be used.
1057 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 1058 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1059 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 1060 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
8aedb9fe 1061 PROCESSOR_AMDFAM10, and PROCESSOR_BD, alt_short_patt
69dd9865 1062 will be used.
ccc9c027 1063
76bc74dc 1064 When -mtune= isn't used, alt_long_patt will be used if
22109423 1065 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1066 be used.
ccc9c027
L		 1067
1068 When -march= or .arch is used, we can't use anything beyond
1069 cpu_arch_isa_flags. */
1070
1071 if (flag_code == CODE_16BIT)
1072 {
ccc9c027 1073 if (count > 8)
33fef721 1074 {
76bc74dc
L		 1075 memcpy (fragP->fr_literal + fragP->fr_fix,
1076 jump_31, count);
1077 /* Adjust jump offset. */
1078 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1079 }
76bc74dc
L		 1080 else
1081 memcpy (fragP->fr_literal + fragP->fr_fix,
1082 f16_patt[count - 1], count);
252b5132 1083 }
33fef721 1084 else
ccc9c027
L		 1085 {
1086 const char *const *patt = NULL;
1087
fbf3f584 1088 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1089 {
1090 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1091 switch (cpu_arch_tune)
1092 {
1093 case PROCESSOR_UNKNOWN:
1094 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1095 optimize with nops. */
1096 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1097 patt = alt_long_patt;
ccc9c027
L		 1098 else
1099 patt = f32_patt;
1100 break;
ccc9c027
L		 1101 case PROCESSOR_PENTIUM4:
1102 case PROCESSOR_NOCONA:
ef05d495 1103 case PROCESSOR_CORE:
76bc74dc 1104 case PROCESSOR_CORE2:
bd5295b2 1105 case PROCESSOR_COREI7:
3632d14b 1106 case PROCESSOR_L1OM:
7a9068fe 1107 case PROCESSOR_K1OM:
76bc74dc
L		 1108 case PROCESSOR_GENERIC64:
1109 patt = alt_long_patt;
1110 break;
ccc9c027
L		 1111 case PROCESSOR_K6:
1112 case PROCESSOR_ATHLON:
1113 case PROCESSOR_K8:
4eed87de 1114 case PROCESSOR_AMDFAM10:
8aedb9fe 1115 case PROCESSOR_BD:
ccc9c027
L		 1116 patt = alt_short_patt;
1117 break;
76bc74dc 1118 case PROCESSOR_I386:
ccc9c027
L		 1119 case PROCESSOR_I486:
1120 case PROCESSOR_PENTIUM:
2dde1948 1121 case PROCESSOR_PENTIUMPRO:
ccc9c027
L		 1122 case PROCESSOR_GENERIC32:
1123 patt = f32_patt;
1124 break;
4eed87de 1125 }
ccc9c027
L		 1126 }
1127 else
1128 {
fbf3f584 1129 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1130 {
1131 case PROCESSOR_UNKNOWN:
e6a14101 1132 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1133 PROCESSOR_UNKNOWN. */
1134 abort ();
1135 break;
1136
76bc74dc 1137 case PROCESSOR_I386:
ccc9c027
L		 1138 case PROCESSOR_I486:
1139 case PROCESSOR_PENTIUM:
ccc9c027
L		 1140 case PROCESSOR_K6:
1141 case PROCESSOR_ATHLON:
1142 case PROCESSOR_K8:
4eed87de 1143 case PROCESSOR_AMDFAM10:
8aedb9fe 1144 case PROCESSOR_BD:
ccc9c027
L		 1145 case PROCESSOR_GENERIC32:
1146 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1147 with nops. */
1148 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1149 patt = alt_short_patt;
1150 else
1151 patt = f32_patt;
1152 break;
76bc74dc
L		 1153 case PROCESSOR_PENTIUMPRO:
1154 case PROCESSOR_PENTIUM4:
1155 case PROCESSOR_NOCONA:
1156 case PROCESSOR_CORE:
ef05d495 1157 case PROCESSOR_CORE2:
bd5295b2 1158 case PROCESSOR_COREI7:
3632d14b 1159 case PROCESSOR_L1OM:
7a9068fe 1160 case PROCESSOR_K1OM:
22109423 1161 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1162 patt = alt_long_patt;
1163 else
1164 patt = f32_patt;
1165 break;
1166 case PROCESSOR_GENERIC64:
76bc74dc 1167 patt = alt_long_patt;
ccc9c027 1168 break;
4eed87de 1169 }
ccc9c027
L		 1170 }
1171
76bc74dc
L		 1172 if (patt == f32_patt)
1173 {
1174 /* If the padding is less than 15 bytes, we use the normal
1175 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1176 its offset. */
1177 int limit;
76ba9986 1178
711eedef
L		 1179 /* For 64bit, the limit is 3 bytes. */
1180 if (flag_code == CODE_64BIT
1181 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1182 limit = 3;
1183 else
1184 limit = 15;
1185 if (count < limit)
76bc74dc
L		 1186 memcpy (fragP->fr_literal + fragP->fr_fix,
1187 patt[count - 1], count);
1188 else
1189 {
1190 memcpy (fragP->fr_literal + fragP->fr_fix,
1191 jump_31, count);
1192 /* Adjust jump offset. */
1193 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1194 }
1195 }
1196 else
1197 {
1198 /* Maximum length of an instruction is 15 byte. If the
1199 padding is greater than 15 bytes and we don't use jump,
1200 we have to break it into smaller pieces. */
1201 int padding = count;
1202 while (padding > 15)
1203 {
1204 padding -= 15;
1205 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1206 patt [14], 15);
1207 }
1208
1209 if (padding)
1210 memcpy (fragP->fr_literal + fragP->fr_fix,
1211 patt [padding - 1], padding);
1212 }
ccc9c027 1213 }
33fef721 1214 fragP->fr_var = count;
252b5132
RH		 1215}
1216
c6fb90c8 1217static INLINE int
0dfbf9d7 1218operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1219{
0dfbf9d7 1220 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1221 {
1222 case 3:
0dfbf9d7 1223 if (x->array[2])
c6fb90c8
L		 1224 return 0;
1225 case 2:
0dfbf9d7 1226 if (x->array[1])
c6fb90c8
L		 1227 return 0;
1228 case 1:
0dfbf9d7 1229 return !x->array[0];
c6fb90c8
L		 1230 default:
1231 abort ();
1232 }
40fb9820
L		 1233}
1234
c6fb90c8 1235static INLINE void
0dfbf9d7 1236operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1237{
0dfbf9d7 1238 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1239 {
1240 case 3:
0dfbf9d7 1241 x->array[2] = v;
c6fb90c8 1242 case 2:
0dfbf9d7 1243 x->array[1] = v;
c6fb90c8 1244 case 1:
0dfbf9d7 1245 x->array[0] = v;
c6fb90c8
L		 1246 break;
1247 default:
1248 abort ();
1249 }
1250}
40fb9820 1251
c6fb90c8 1252static INLINE int
0dfbf9d7
L		 1253operand_type_equal (const union i386_operand_type *x,
1254 const union i386_operand_type *y)
c6fb90c8 1255{
0dfbf9d7 1256 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1257 {
1258 case 3:
0dfbf9d7 1259 if (x->array[2] != y->array[2])
c6fb90c8
L		 1260 return 0;
1261 case 2:
0dfbf9d7 1262 if (x->array[1] != y->array[1])
c6fb90c8
L		 1263 return 0;
1264 case 1:
0dfbf9d7 1265 return x->array[0] == y->array[0];
c6fb90c8
L		 1266 break;
1267 default:
1268 abort ();
1269 }
1270}
40fb9820 1271
0dfbf9d7
L		 1272static INLINE int
1273cpu_flags_all_zero (const union i386_cpu_flags *x)
1274{
1275 switch (ARRAY_SIZE(x->array))
1276 {
1277 case 3:
1278 if (x->array[2])
1279 return 0;
1280 case 2:
1281 if (x->array[1])
1282 return 0;
1283 case 1:
1284 return !x->array[0];
1285 default:
1286 abort ();
1287 }
1288}
1289
1290static INLINE void
1291cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1292{
1293 switch (ARRAY_SIZE(x->array))
1294 {
1295 case 3:
1296 x->array[2] = v;
1297 case 2:
1298 x->array[1] = v;
1299 case 1:
1300 x->array[0] = v;
1301 break;
1302 default:
1303 abort ();
1304 }
1305}
1306
1307static INLINE int
1308cpu_flags_equal (const union i386_cpu_flags *x,
1309 const union i386_cpu_flags *y)
1310{
1311 switch (ARRAY_SIZE(x->array))
1312 {
1313 case 3:
1314 if (x->array[2] != y->array[2])
1315 return 0;
1316 case 2:
1317 if (x->array[1] != y->array[1])
1318 return 0;
1319 case 1:
1320 return x->array[0] == y->array[0];
1321 break;
1322 default:
1323 abort ();
1324 }
1325}
c6fb90c8
L		 1326
1327static INLINE int
1328cpu_flags_check_cpu64 (i386_cpu_flags f)
1329{
1330 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1331 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1332}
1333
c6fb90c8
L		 1334static INLINE i386_cpu_flags
1335cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1336{
c6fb90c8
L		 1337 switch (ARRAY_SIZE (x.array))
1338 {
1339 case 3:
1340 x.array [2] &= y.array [2];
1341 case 2:
1342 x.array [1] &= y.array [1];
1343 case 1:
1344 x.array [0] &= y.array [0];
1345 break;
1346 default:
1347 abort ();
1348 }
1349 return x;
1350}
40fb9820 1351
c6fb90c8
L		 1352static INLINE i386_cpu_flags
1353cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1354{
c6fb90c8 1355 switch (ARRAY_SIZE (x.array))
40fb9820 1356 {
c6fb90c8
L		 1357 case 3:
1358 x.array [2] |= y.array [2];
1359 case 2:
1360 x.array [1] |= y.array [1];
1361 case 1:
1362 x.array [0] |= y.array [0];
40fb9820
L		 1363 break;
1364 default:
1365 abort ();
1366 }
40fb9820
L		 1367 return x;
1368}
1369
309d3373
JB		 1370static INLINE i386_cpu_flags
1371cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1372{
1373 switch (ARRAY_SIZE (x.array))
1374 {
1375 case 3:
1376 x.array [2] &= ~y.array [2];
1377 case 2:
1378 x.array [1] &= ~y.array [1];
1379 case 1:
1380 x.array [0] &= ~y.array [0];
1381 break;
1382 default:
1383 abort ();
1384 }
1385 return x;
1386}
1387
c0f3af97
L		 1388#define CPU_FLAGS_ARCH_MATCH 0x1
1389#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1390#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1391#define CPU_FLAGS_PCLMUL_MATCH 0x8
1392#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1393
a5ff0eb2 1394#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1395 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1396 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1397#define CPU_FLAGS_PERFECT_MATCH \
1398 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1399
1400/* Return CPU flags match bits. */
3629bb00 1401
40fb9820 1402static int
d3ce72d0 1403cpu_flags_match (const insn_template *t)
40fb9820 1404{
c0f3af97
L		 1405 i386_cpu_flags x = t->cpu_flags;
1406 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1407
1408 x.bitfield.cpu64 = 0;
1409 x.bitfield.cpuno64 = 0;
1410
0dfbf9d7 1411 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1412 {
1413 /* This instruction is available on all archs. */
1414 match |= CPU_FLAGS_32BIT_MATCH;
1415 }
3629bb00
L		 1416 else
1417 {
c0f3af97 1418 /* This instruction is available only on some archs. */
3629bb00
L		 1419 i386_cpu_flags cpu = cpu_arch_flags;
1420
1421 cpu.bitfield.cpu64 = 0;
1422 cpu.bitfield.cpuno64 = 0;
1423 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1424 if (!cpu_flags_all_zero (&cpu))
1425 {
a5ff0eb2
L		 1426 if (x.bitfield.cpuavx)
1427 {
ce2f5b3c 1428 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1429 if (cpu.bitfield.cpuavx)
1430 {
1431 /* Check SSE2AVX. */
1432 if (!t->opcode_modifier.sse2avx|| sse2avx)
1433 {
1434 match |= (CPU_FLAGS_ARCH_MATCH
1435 | CPU_FLAGS_AVX_MATCH);
1436 /* Check AES. */
1437 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1438 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1439 /* Check PCLMUL. */
1440 if (!x.bitfield.cpupclmul
1441 || cpu.bitfield.cpupclmul)
1442 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1443 }
1444 }
1445 else
1446 match |= CPU_FLAGS_ARCH_MATCH;
1447 }
1448 else
c0f3af97
L		 1449 match |= CPU_FLAGS_32BIT_MATCH;
1450 }
3629bb00 1451 }
c0f3af97 1452 return match;
40fb9820
L		 1453}
1454
c6fb90c8
L		 1455static INLINE i386_operand_type
1456operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1457{
c6fb90c8
L		 1458 switch (ARRAY_SIZE (x.array))
1459 {
1460 case 3:
1461 x.array [2] &= y.array [2];
1462 case 2:
1463 x.array [1] &= y.array [1];
1464 case 1:
1465 x.array [0] &= y.array [0];
1466 break;
1467 default:
1468 abort ();
1469 }
1470 return x;
40fb9820
L		 1471}
1472
c6fb90c8
L		 1473static INLINE i386_operand_type
1474operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1475{
c6fb90c8 1476 switch (ARRAY_SIZE (x.array))
40fb9820 1477 {
c6fb90c8
L		 1478 case 3:
1479 x.array [2] |= y.array [2];
1480 case 2:
1481 x.array [1] |= y.array [1];
1482 case 1:
1483 x.array [0] |= y.array [0];
40fb9820
L		 1484 break;
1485 default:
1486 abort ();
1487 }
c6fb90c8
L		 1488 return x;
1489}
40fb9820 1490
c6fb90c8
L		 1491static INLINE i386_operand_type
1492operand_type_xor (i386_operand_type x, i386_operand_type y)
1493{
1494 switch (ARRAY_SIZE (x.array))
1495 {
1496 case 3:
1497 x.array [2] ^= y.array [2];
1498 case 2:
1499 x.array [1] ^= y.array [1];
1500 case 1:
1501 x.array [0] ^= y.array [0];
1502 break;
1503 default:
1504 abort ();
1505 }
40fb9820
L		 1506 return x;
1507}
1508
1509static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1510static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1511static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1512static const i386_operand_type inoutportreg
1513 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1514static const i386_operand_type reg16_inoutportreg
1515 = OPERAND_TYPE_REG16_INOUTPORTREG;
1516static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1517static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1518static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1519static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1520static const i386_operand_type anydisp
1521 = OPERAND_TYPE_ANYDISP;
40fb9820 1522static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1523static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1524static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1525static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1526static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1527static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1528static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1529static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1530static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1531static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1532static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1533static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1534
1535enum operand_type
1536{
1537 reg,
40fb9820
L		 1538 imm,
1539 disp,
1540 anymem
1541};
1542
c6fb90c8 1543static INLINE int
40fb9820
L		 1544operand_type_check (i386_operand_type t, enum operand_type c)
1545{
1546 switch (c)
1547 {
1548 case reg:
1549 return (t.bitfield.reg8
1550 || t.bitfield.reg16
1551 || t.bitfield.reg32
1552 || t.bitfield.reg64);
1553
40fb9820
L		 1554 case imm:
1555 return (t.bitfield.imm8
1556 || t.bitfield.imm8s
1557 || t.bitfield.imm16
1558 || t.bitfield.imm32
1559 || t.bitfield.imm32s
1560 || t.bitfield.imm64);
1561
1562 case disp:
1563 return (t.bitfield.disp8
1564 || t.bitfield.disp16
1565 || t.bitfield.disp32
1566 || t.bitfield.disp32s
1567 || t.bitfield.disp64);
1568
1569 case anymem:
1570 return (t.bitfield.disp8
1571 || t.bitfield.disp16
1572 || t.bitfield.disp32
1573 || t.bitfield.disp32s
1574 || t.bitfield.disp64
1575 || t.bitfield.baseindex);
1576
1577 default:
1578 abort ();
1579 }
2cfe26b6
AM		 1580
1581 return 0;
40fb9820
L		 1582}
1583
5c07affc
L		 1584/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1585 operand J for instruction template T. */
1586
1587static INLINE int
d3ce72d0 1588match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1589{
1590 return !((i.types[j].bitfield.byte
1591 && !t->operand_types[j].bitfield.byte)
1592 || (i.types[j].bitfield.word
1593 && !t->operand_types[j].bitfield.word)
1594 || (i.types[j].bitfield.dword
1595 && !t->operand_types[j].bitfield.dword)
1596 || (i.types[j].bitfield.qword
1597 && !t->operand_types[j].bitfield.qword));
1598}
1599
1600/* Return 1 if there is no conflict in any size on operand J for
1601 instruction template T. */
1602
1603static INLINE int
d3ce72d0 1604match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1605{
1606 return (match_reg_size (t, j)
1607 && !((i.types[j].bitfield.unspecified
1608 && !t->operand_types[j].bitfield.unspecified)
1609 || (i.types[j].bitfield.fword
1610 && !t->operand_types[j].bitfield.fword)
1611 || (i.types[j].bitfield.tbyte
1612 && !t->operand_types[j].bitfield.tbyte)
1613 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1614 && !t->operand_types[j].bitfield.xmmword)
1615 || (i.types[j].bitfield.ymmword
1616 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1617}
1618
1619/* Return 1 if there is no size conflict on any operands for
1620 instruction template T. */
1621
1622static INLINE int
d3ce72d0 1623operand_size_match (const insn_template *t)
5c07affc
L		 1624{
1625 unsigned int j;
1626 int match = 1;
1627
1628 /* Don't check jump instructions. */
1629 if (t->opcode_modifier.jump
1630 || t->opcode_modifier.jumpbyte
1631 || t->opcode_modifier.jumpdword
1632 || t->opcode_modifier.jumpintersegment)
1633 return match;
1634
1635 /* Check memory and accumulator operand size. */
1636 for (j = 0; j < i.operands; j++)
1637 {
1638 if (t->operand_types[j].bitfield.anysize)
1639 continue;
1640
1641 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1642 {
1643 match = 0;
1644 break;
1645 }
1646
1647 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1648 {
1649 match = 0;
1650 break;
1651 }
1652 }
1653
891edac4 1654 if (match)
5c07affc 1655 return match;
891edac4
L		 1656 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1657 {
1658mismatch:
86e026a4 1659 i.error = operand_size_mismatch;
891edac4
L		 1660 return 0;
1661 }
5c07affc
L		 1662
1663 /* Check reverse. */
9c2799c2 1664 gas_assert (i.operands == 2);
5c07affc
L		 1665
1666 match = 1;
1667 for (j = 0; j < 2; j++)
1668 {
1669 if (t->operand_types[j].bitfield.acc
1670 && !match_reg_size (t, j ? 0 : 1))
891edac4 1671 goto mismatch;
5c07affc
L		 1672
1673 if (i.types[j].bitfield.mem
1674 && !match_mem_size (t, j ? 0 : 1))
891edac4 1675 goto mismatch;
5c07affc
L		 1676 }
1677
1678 return match;
1679}
1680
c6fb90c8 1681static INLINE int
40fb9820
L		 1682operand_type_match (i386_operand_type overlap,
1683 i386_operand_type given)
1684{
1685 i386_operand_type temp = overlap;
1686
1687 temp.bitfield.jumpabsolute = 0;
7d5e4556 1688 temp.bitfield.unspecified = 0;
5c07affc
L		 1689 temp.bitfield.byte = 0;
1690 temp.bitfield.word = 0;
1691 temp.bitfield.dword = 0;
1692 temp.bitfield.fword = 0;
1693 temp.bitfield.qword = 0;
1694 temp.bitfield.tbyte = 0;
1695 temp.bitfield.xmmword = 0;
c0f3af97 1696 temp.bitfield.ymmword = 0;
0dfbf9d7 1697 if (operand_type_all_zero (&temp))
891edac4 1698 goto mismatch;
40fb9820 1699
891edac4
L		 1700 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1701 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1702 return 1;
1703
1704mismatch:
a65babc9 1705 i.error = operand_type_mismatch;
891edac4 1706 return 0;
40fb9820
L		 1707}
1708
7d5e4556 1709/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1710 unless the expected operand type register overlap is null.
1711 Note that Acc in a template matches every size of reg. */
1712
c6fb90c8 1713static INLINE int
40fb9820
L		 1714operand_type_register_match (i386_operand_type m0,
1715 i386_operand_type g0,
1716 i386_operand_type t0,
1717 i386_operand_type m1,
1718 i386_operand_type g1,
1719 i386_operand_type t1)
1720{
1721 if (!operand_type_check (g0, reg))
1722 return 1;
1723
1724 if (!operand_type_check (g1, reg))
1725 return 1;
1726
1727 if (g0.bitfield.reg8 == g1.bitfield.reg8
1728 && g0.bitfield.reg16 == g1.bitfield.reg16
1729 && g0.bitfield.reg32 == g1.bitfield.reg32
1730 && g0.bitfield.reg64 == g1.bitfield.reg64)
1731 return 1;
1732
1733 if (m0.bitfield.acc)
1734 {
1735 t0.bitfield.reg8 = 1;
1736 t0.bitfield.reg16 = 1;
1737 t0.bitfield.reg32 = 1;
1738 t0.bitfield.reg64 = 1;
1739 }
1740
1741 if (m1.bitfield.acc)
1742 {
1743 t1.bitfield.reg8 = 1;
1744 t1.bitfield.reg16 = 1;
1745 t1.bitfield.reg32 = 1;
1746 t1.bitfield.reg64 = 1;
1747 }
1748
891edac4
L		 1749 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1750 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1751 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1752 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1753 return 1;
1754
a65babc9 1755 i.error = register_type_mismatch;
891edac4
L		 1756
1757 return 0;
40fb9820
L		 1758}
1759
4c692bc7
JB		 1760static INLINE unsigned int
1761register_number (const reg_entry *r)
1762{
1763 unsigned int nr = r->reg_num;
1764
1765 if (r->reg_flags & RegRex)
1766 nr += 8;
1767
1768 return nr;
1769}
1770
252b5132 1771static INLINE unsigned int
40fb9820 1772mode_from_disp_size (i386_operand_type t)
252b5132 1773{
40fb9820
L		 1774 if (t.bitfield.disp8)
1775 return 1;
1776 else if (t.bitfield.disp16
1777 || t.bitfield.disp32
1778 || t.bitfield.disp32s)
1779 return 2;
1780 else
1781 return 0;
252b5132
RH		 1782}
1783
1784static INLINE int
e3bb37b5 1785fits_in_signed_byte (offsetT num)
252b5132
RH		 1786{
1787 return (num >= -128) && (num <= 127);
47926f60 1788}
252b5132
RH		 1789
1790static INLINE int
e3bb37b5 1791fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1792{
1793 return (num & 0xff) == num;
47926f60 1794}
252b5132
RH		 1795
1796static INLINE int
e3bb37b5 1797fits_in_unsigned_word (offsetT num)
252b5132
RH		 1798{
1799 return (num & 0xffff) == num;
47926f60 1800}
252b5132
RH		 1801
1802static INLINE int
e3bb37b5 1803fits_in_signed_word (offsetT num)
252b5132
RH		 1804{
1805 return (-32768 <= num) && (num <= 32767);
47926f60 1806}
2a962e6d 1807
3e73aa7c 1808static INLINE int
e3bb37b5 1809fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1810{
1811#ifndef BFD64
1812 return 1;
1813#else
1814 return (!(((offsetT) -1 << 31) & num)
1815 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1816#endif
1817} /* fits_in_signed_long() */
2a962e6d 1818
3e73aa7c 1819static INLINE int
e3bb37b5 1820fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1821{
1822#ifndef BFD64
1823 return 1;
1824#else
1825 return (num & (((offsetT) 2 << 31) - 1)) == num;
1826#endif
1827} /* fits_in_unsigned_long() */
252b5132 1828
a683cc34
SP		 1829static INLINE int
1830fits_in_imm4 (offsetT num)
1831{
1832 return (num & 0xf) == num;
1833}
1834
40fb9820 1835static i386_operand_type
e3bb37b5 1836smallest_imm_type (offsetT num)
252b5132 1837{
40fb9820 1838 i386_operand_type t;
7ab9ffdd 1839
0dfbf9d7 1840 operand_type_set (&t, 0);
40fb9820
L		 1841 t.bitfield.imm64 = 1;
1842
1843 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1844 {
1845 /* This code is disabled on the 486 because all the Imm1 forms
1846 in the opcode table are slower on the i486. They're the
1847 versions with the implicitly specified single-position
1848 displacement, which has another syntax if you really want to
1849 use that form. */
40fb9820
L		 1850 t.bitfield.imm1 = 1;
1851 t.bitfield.imm8 = 1;
1852 t.bitfield.imm8s = 1;
1853 t.bitfield.imm16 = 1;
1854 t.bitfield.imm32 = 1;
1855 t.bitfield.imm32s = 1;
1856 }
1857 else if (fits_in_signed_byte (num))
1858 {
1859 t.bitfield.imm8 = 1;
1860 t.bitfield.imm8s = 1;
1861 t.bitfield.imm16 = 1;
1862 t.bitfield.imm32 = 1;
1863 t.bitfield.imm32s = 1;
1864 }
1865 else if (fits_in_unsigned_byte (num))
1866 {
1867 t.bitfield.imm8 = 1;
1868 t.bitfield.imm16 = 1;
1869 t.bitfield.imm32 = 1;
1870 t.bitfield.imm32s = 1;
1871 }
1872 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1873 {
1874 t.bitfield.imm16 = 1;
1875 t.bitfield.imm32 = 1;
1876 t.bitfield.imm32s = 1;
1877 }
1878 else if (fits_in_signed_long (num))
1879 {
1880 t.bitfield.imm32 = 1;
1881 t.bitfield.imm32s = 1;
1882 }
1883 else if (fits_in_unsigned_long (num))
1884 t.bitfield.imm32 = 1;
1885
1886 return t;
47926f60 1887}
252b5132 1888
847f7ad4 1889static offsetT
e3bb37b5 1890offset_in_range (offsetT val, int size)
847f7ad4 1891{
508866be 1892 addressT mask;
ba2adb93 1893
847f7ad4
AM		 1894 switch (size)
1895 {
508866be
L		 1896 case 1: mask = ((addressT) 1 << 8) - 1; break;
1897 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1898 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1899#ifdef BFD64
1900 case 8: mask = ((addressT) 2 << 63) - 1; break;
1901#endif
47926f60 1902 default: abort ();
847f7ad4
AM		 1903 }
1904
9de868bf
L		 1905#ifdef BFD64
1906 /* If BFD64, sign extend val for 32bit address mode. */
1907 if (flag_code != CODE_64BIT
1908 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 1909 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1910 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 1911#endif
ba2adb93 1912
47926f60 1913 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1914 {
1915 char buf1[40], buf2[40];
1916
1917 sprint_value (buf1, val);
1918 sprint_value (buf2, val & mask);
1919 as_warn (_("%s shortened to %s"), buf1, buf2);
1920 }
1921 return val & mask;
1922}
1923
c32fa91d
L		 1924enum PREFIX_GROUP
1925{
1926 PREFIX_EXIST = 0,
1927 PREFIX_LOCK,
1928 PREFIX_REP,
1929 PREFIX_OTHER
1930};
1931
1932/* Returns
1933 a. PREFIX_EXIST if attempting to add a prefix where one from the
1934 same class already exists.
1935 b. PREFIX_LOCK if lock prefix is added.
1936 c. PREFIX_REP if rep/repne prefix is added.
1937 d. PREFIX_OTHER if other prefix is added.
1938 */
1939
1940static enum PREFIX_GROUP
e3bb37b5 1941add_prefix (unsigned int prefix)
252b5132 1942{
c32fa91d 1943 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 1944 unsigned int q;
252b5132 1945
29b0f896
AM		 1946 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1947 && flag_code == CODE_64BIT)
b1905489 1948 {
161a04f6
L		 1949 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1950 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1951 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 1952 ret = PREFIX_EXIST;
b1905489
JB		 1953 q = REX_PREFIX;
1954 }
3e73aa7c 1955 else
b1905489
JB		 1956 {
1957 switch (prefix)
1958 {
1959 default:
1960 abort ();
1961
1962 case CS_PREFIX_OPCODE:
1963 case DS_PREFIX_OPCODE:
1964 case ES_PREFIX_OPCODE:
1965 case FS_PREFIX_OPCODE:
1966 case GS_PREFIX_OPCODE:
1967 case SS_PREFIX_OPCODE:
1968 q = SEG_PREFIX;
1969 break;
1970
1971 case REPNE_PREFIX_OPCODE:
1972 case REPE_PREFIX_OPCODE:
c32fa91d
L		 1973 q = REP_PREFIX;
1974 ret = PREFIX_REP;
1975 break;
1976
b1905489 1977 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 1978 q = LOCK_PREFIX;
1979 ret = PREFIX_LOCK;
b1905489
JB		 1980 break;
1981
1982 case FWAIT_OPCODE:
1983 q = WAIT_PREFIX;
1984 break;
1985
1986 case ADDR_PREFIX_OPCODE:
1987 q = ADDR_PREFIX;
1988 break;
1989
1990 case DATA_PREFIX_OPCODE:
1991 q = DATA_PREFIX;
1992 break;
1993 }
1994 if (i.prefix[q] != 0)
c32fa91d 1995 ret = PREFIX_EXIST;
b1905489 1996 }
252b5132 1997
b1905489 1998 if (ret)
252b5132 1999 {
b1905489
JB		 2000 if (!i.prefix[q])
2001 ++i.prefixes;
2002 i.prefix[q] |= prefix;
252b5132 2003 }
b1905489
JB		 2004 else
2005 as_bad (_("same type of prefix used twice"));
252b5132 2006
252b5132
RH		 2007 return ret;
2008}
2009
2010static void
78f12dd3 2011update_code_flag (int value, int check)
eecb386c 2012{
78f12dd3
L		 2013 PRINTF_LIKE ((*as_error));
2014
1e9cc1c2 2015 flag_code = (enum flag_code) value;
40fb9820
L		 2016 if (flag_code == CODE_64BIT)
2017 {
2018 cpu_arch_flags.bitfield.cpu64 = 1;
2019 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2020 }
2021 else
2022 {
2023 cpu_arch_flags.bitfield.cpu64 = 0;
2024 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2025 }
2026 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2027 {
78f12dd3
L		 2028 if (check)
2029 as_error = as_fatal;
2030 else
2031 as_error = as_bad;
2032 (*as_error) (_("64bit mode not supported on `%s'."),
2033 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2034 }
40fb9820 2035 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2036 {
78f12dd3
L		 2037 if (check)
2038 as_error = as_fatal;
2039 else
2040 as_error = as_bad;
2041 (*as_error) (_("32bit mode not supported on `%s'."),
2042 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2043 }
eecb386c
AM		 2044 stackop_size = '\0';
2045}
2046
78f12dd3
L		 2047static void
2048set_code_flag (int value)
2049{
2050 update_code_flag (value, 0);
2051}
2052
eecb386c 2053static void
e3bb37b5 2054set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2055{
1e9cc1c2 2056 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2057 if (flag_code != CODE_16BIT)
2058 abort ();
2059 cpu_arch_flags.bitfield.cpu64 = 0;
2060 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2061 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2062}
2063
2064static void
e3bb37b5 2065set_intel_syntax (int syntax_flag)
252b5132
RH		 2066{
2067 /* Find out if register prefixing is specified. */
2068 int ask_naked_reg = 0;
2069
2070 SKIP_WHITESPACE ();
29b0f896 2071 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2072 {
2073 char *string = input_line_pointer;
2074 int e = get_symbol_end ();
2075
47926f60 2076 if (strcmp (string, "prefix") == 0)
252b5132 2077 ask_naked_reg = 1;
47926f60 2078 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2079 ask_naked_reg = -1;
2080 else
d0b47220 2081 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2082 *input_line_pointer = e;
2083 }
2084 demand_empty_rest_of_line ();
c3332e24 2085
252b5132
RH		 2086 intel_syntax = syntax_flag;
2087
2088 if (ask_naked_reg == 0)
f86103b7
AM		 2089 allow_naked_reg = (intel_syntax
2090 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2091 else
2092 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2093
ee86248c 2094 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2095
e4a3b5a4 2096 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2097 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2098 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2099}
2100
1efbbeb4
L		 2101static void
2102set_intel_mnemonic (int mnemonic_flag)
2103{
e1d4d893 2104 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2105}
2106
db51cc60
L		 2107static void
2108set_allow_index_reg (int flag)
2109{
2110 allow_index_reg = flag;
2111}
2112
cb19c032
L		 2113static void
2114set_sse_check (int dummy ATTRIBUTE_UNUSED)
2115{
2116 SKIP_WHITESPACE ();
2117
2118 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2119 {
2120 char *string = input_line_pointer;
2121 int e = get_symbol_end ();
2122
2123 if (strcmp (string, "none") == 0)
2124 sse_check = sse_check_none;
2125 else if (strcmp (string, "warning") == 0)
2126 sse_check = sse_check_warning;
2127 else if (strcmp (string, "error") == 0)
2128 sse_check = sse_check_error;
2129 else
2130 as_bad (_("bad argument to sse_check directive."));
2131 *input_line_pointer = e;
2132 }
2133 else
2134 as_bad (_("missing argument for sse_check directive"));
2135
2136 demand_empty_rest_of_line ();
2137}
2138
8a9036a4
L		 2139static void
2140check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2141 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2142{
2143#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2144 static const char *arch;
2145
2146 /* Intel LIOM is only supported on ELF. */
2147 if (!IS_ELF)
2148 return;
2149
2150 if (!arch)
2151 {
2152 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2153 use default_arch. */
2154 arch = cpu_arch_name;
2155 if (!arch)
2156 arch = default_arch;
2157 }
2158
3632d14b 2159 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2160 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2161 || new_flag.bitfield.cpul1om)
8a9036a4 2162 return;
76ba9986 2163
7a9068fe
L		 2164 /* If we are targeting Intel K1OM, we must enable it. */
2165 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2166 || new_flag.bitfield.cpuk1om)
2167 return;
2168
8a9036a4
L		 2169 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2170#endif
2171}
2172
e413e4e9 2173static void
e3bb37b5 2174set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2175{
47926f60 2176 SKIP_WHITESPACE ();
e413e4e9 2177
29b0f896 2178 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2179 {
2180 char *string = input_line_pointer;
2181 int e = get_symbol_end ();
91d6fa6a 2182 unsigned int j;
40fb9820 2183 i386_cpu_flags flags;
e413e4e9 2184
91d6fa6a 2185 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2186 {
91d6fa6a 2187 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2188 {
91d6fa6a 2189 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2190
5c6af06e
JB		 2191 if (*string != '.')
2192 {
91d6fa6a 2193 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2194 cpu_sub_arch_name = NULL;
91d6fa6a 2195 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2196 if (flag_code == CODE_64BIT)
2197 {
2198 cpu_arch_flags.bitfield.cpu64 = 1;
2199 cpu_arch_flags.bitfield.cpuno64 = 0;
2200 }
2201 else
2202 {
2203 cpu_arch_flags.bitfield.cpu64 = 0;
2204 cpu_arch_flags.bitfield.cpuno64 = 1;
2205 }
91d6fa6a
NC		 2206 cpu_arch_isa = cpu_arch[j].type;
2207 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2208 if (!cpu_arch_tune_set)
2209 {
2210 cpu_arch_tune = cpu_arch_isa;
2211 cpu_arch_tune_flags = cpu_arch_isa_flags;
2212 }
5c6af06e
JB		 2213 break;
2214 }
40fb9820 2215
22109423 2216 if (!cpu_arch[j].negated)
309d3373 2217 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2218 cpu_arch[j].flags);
309d3373
JB		 2219 else
2220 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2221 cpu_arch[j].flags);
0dfbf9d7 2222 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2223 {
6305a203
L		 2224 if (cpu_sub_arch_name)
2225 {
2226 char *name = cpu_sub_arch_name;
2227 cpu_sub_arch_name = concat (name,
91d6fa6a 2228 cpu_arch[j].name,
1bf57e9f 2229 (const char *) NULL);
6305a203
L		 2230 free (name);
2231 }
2232 else
91d6fa6a 2233 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2234 cpu_arch_flags = flags;
a586129e 2235 cpu_arch_isa_flags = flags;
5c6af06e
JB		 2236 }
2237 *input_line_pointer = e;
2238 demand_empty_rest_of_line ();
2239 return;
e413e4e9
AM		 2240 }
2241 }
91d6fa6a 2242 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2243 as_bad (_("no such architecture: `%s'"), string);
2244
2245 *input_line_pointer = e;
2246 }
2247 else
2248 as_bad (_("missing cpu architecture"));
2249
fddf5b5b
AM		 2250 no_cond_jump_promotion = 0;
2251 if (*input_line_pointer == ','
29b0f896 2252 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2253 {
2254 char *string = ++input_line_pointer;
2255 int e = get_symbol_end ();
2256
2257 if (strcmp (string, "nojumps") == 0)
2258 no_cond_jump_promotion = 1;
2259 else if (strcmp (string, "jumps") == 0)
2260 ;
2261 else
2262 as_bad (_("no such architecture modifier: `%s'"), string);
2263
2264 *input_line_pointer = e;
2265 }
2266
e413e4e9
AM		 2267 demand_empty_rest_of_line ();
2268}
2269
8a9036a4
L		 2270enum bfd_architecture
2271i386_arch (void)
2272{
3632d14b 2273 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2274 {
2275 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2276 || flag_code != CODE_64BIT)
2277 as_fatal (_("Intel L1OM is 64bit ELF only"));
2278 return bfd_arch_l1om;
2279 }
7a9068fe
L		 2280 else if (cpu_arch_isa == PROCESSOR_K1OM)
2281 {
2282 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2283 || flag_code != CODE_64BIT)
2284 as_fatal (_("Intel K1OM is 64bit ELF only"));
2285 return bfd_arch_k1om;
2286 }
8a9036a4
L		 2287 else
2288 return bfd_arch_i386;
2289}
2290
b9d79e03 2291unsigned long
7016a5d5 2292i386_mach (void)
b9d79e03 2293{
351f65ca 2294 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2295 {
3632d14b 2296 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2297 {
351f65ca
L		 2298 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2299 || default_arch[6] != '\0')
8a9036a4
L		 2300 as_fatal (_("Intel L1OM is 64bit ELF only"));
2301 return bfd_mach_l1om;
2302 }
7a9068fe
L		 2303 else if (cpu_arch_isa == PROCESSOR_K1OM)
2304 {
2305 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2306 || default_arch[6] != '\0')
2307 as_fatal (_("Intel K1OM is 64bit ELF only"));
2308 return bfd_mach_k1om;
2309 }
351f65ca 2310 else if (default_arch[6] == '\0')
8a9036a4 2311 return bfd_mach_x86_64;
351f65ca
L		 2312 else
2313 return bfd_mach_x64_32;
8a9036a4 2314 }
b9d79e03
JH		 2315 else if (!strcmp (default_arch, "i386"))
2316 return bfd_mach_i386_i386;
2317 else
2b5d6a91 2318 as_fatal (_("unknown architecture"));
b9d79e03 2319}
b9d79e03 2320\f
252b5132 2321void
7016a5d5 2322md_begin (void)
252b5132
RH		 2323{
2324 const char *hash_err;
2325
47926f60 2326 /* Initialize op_hash hash table. */
252b5132
RH		 2327 op_hash = hash_new ();
2328
2329 {
d3ce72d0 2330 const insn_template *optab;
29b0f896 2331 templates *core_optab;
252b5132 2332
47926f60
KH		 2333 /* Setup for loop. */
2334 optab = i386_optab;
252b5132
RH		 2335 core_optab = (templates *) xmalloc (sizeof (templates));
2336 core_optab->start = optab;
2337
2338 while (1)
2339 {
2340 ++optab;
2341 if (optab->name == NULL
2342 || strcmp (optab->name, (optab - 1)->name) != 0)
2343 {
2344 /* different name --> ship out current template list;
47926f60 2345 add to hash table; & begin anew. */
252b5132
RH		 2346 core_optab->end = optab;
2347 hash_err = hash_insert (op_hash,
2348 (optab - 1)->name,
5a49b8ac 2349 (void *) core_optab);
252b5132
RH		 2350 if (hash_err)
2351 {
2b5d6a91 2352 as_fatal (_("internal Error: Can't hash %s: %s"),
252b5132
RH		 2353 (optab - 1)->name,
2354 hash_err);
2355 }
2356 if (optab->name == NULL)
2357 break;
2358 core_optab = (templates *) xmalloc (sizeof (templates));
2359 core_optab->start = optab;
2360 }
2361 }
2362 }
2363
47926f60 2364 /* Initialize reg_hash hash table. */
252b5132
RH		 2365 reg_hash = hash_new ();
2366 {
29b0f896 2367 const reg_entry *regtab;
c3fe08fa 2368 unsigned int regtab_size = i386_regtab_size;
252b5132 2369
c3fe08fa 2370 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2371 {
5a49b8ac 2372 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2373 if (hash_err)
2b5d6a91 2374 as_fatal (_("internal Error: Can't hash %s: %s"),
3e73aa7c
JH		 2375 regtab->reg_name,
2376 hash_err);
252b5132
RH		 2377 }
2378 }
2379
47926f60 2380 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2381 {
29b0f896
AM		 2382 int c;
2383 char *p;
252b5132
RH		 2384
2385 for (c = 0; c < 256; c++)
2386 {
3882b010 2387 if (ISDIGIT (c))
252b5132
RH		 2388 {
2389 digit_chars[c] = c;
2390 mnemonic_chars[c] = c;
2391 register_chars[c] = c;
2392 operand_chars[c] = c;
2393 }
3882b010 2394 else if (ISLOWER (c))
252b5132
RH		 2395 {
2396 mnemonic_chars[c] = c;
2397 register_chars[c] = c;
2398 operand_chars[c] = c;
2399 }
3882b010 2400 else if (ISUPPER (c))
252b5132 2401 {
3882b010 2402 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2403 register_chars[c] = mnemonic_chars[c];
2404 operand_chars[c] = c;
2405 }
2406
3882b010 2407 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2408 identifier_chars[c] = c;
2409 else if (c >= 128)
2410 {
2411 identifier_chars[c] = c;
2412 operand_chars[c] = c;
2413 }
2414 }
2415
2416#ifdef LEX_AT
2417 identifier_chars['@'] = '@';
32137342
NC		 2418#endif
2419#ifdef LEX_QM
2420 identifier_chars['?'] = '?';
2421 operand_chars['?'] = '?';
252b5132 2422#endif
252b5132 2423 digit_chars['-'] = '-';
c0f3af97 2424 mnemonic_chars['_'] = '_';
791fe849 2425 mnemonic_chars['-'] = '-';
0003779b 2426 mnemonic_chars['.'] = '.';
252b5132
RH		 2427 identifier_chars['_'] = '_';
2428 identifier_chars['.'] = '.';
2429
2430 for (p = operand_special_chars; *p != '\0'; p++)
2431 operand_chars[(unsigned char) *p] = *p;
2432 }
2433
2434#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2435 if (IS_ELF)
252b5132
RH		 2436 {
2437 record_alignment (text_section, 2);
2438 record_alignment (data_section, 2);
2439 record_alignment (bss_section, 2);
2440 }
2441#endif
a4447b93
RH		 2442
2443 if (flag_code == CODE_64BIT)
2444 {
ca19b261
KT		 2445#if defined (OBJ_COFF) && defined (TE_PE)
2446 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2447 ? 32 : 16);
2448#else
a4447b93 2449 x86_dwarf2_return_column = 16;
ca19b261 2450#endif
61ff971f 2451 x86_cie_data_alignment = -8;
a4447b93
RH		 2452 }
2453 else
2454 {
2455 x86_dwarf2_return_column = 8;
2456 x86_cie_data_alignment = -4;
2457 }
252b5132
RH		 2458}
2459
2460void
e3bb37b5 2461i386_print_statistics (FILE *file)
252b5132
RH		 2462{
2463 hash_print_statistics (file, "i386 opcode", op_hash);
2464 hash_print_statistics (file, "i386 register", reg_hash);
2465}
2466\f
252b5132
RH		 2467#ifdef DEBUG386
2468
ce8a8b2f 2469/* Debugging routines for md_assemble. */
d3ce72d0 2470static void pte (insn_template *);
40fb9820 2471static void pt (i386_operand_type);
e3bb37b5
L		 2472static void pe (expressionS *);
2473static void ps (symbolS *);
252b5132
RH		 2474
2475static void
e3bb37b5 2476pi (char *line, i386_insn *x)
252b5132 2477{
09137c09 2478 unsigned int j;
252b5132
RH		 2479
2480 fprintf (stdout, "%s: template ", line);
2481 pte (&x->tm);
09f131f2
JH		 2482 fprintf (stdout, " address: base %s index %s scale %x\n",
2483 x->base_reg ? x->base_reg->reg_name : "none",
2484 x->index_reg ? x->index_reg->reg_name : "none",
2485 x->log2_scale_factor);
2486 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2487 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2488 fprintf (stdout, " sib: base %x index %x scale %x\n",
2489 x->sib.base, x->sib.index, x->sib.scale);
2490 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2491 (x->rex & REX_W) != 0,
2492 (x->rex & REX_R) != 0,
2493 (x->rex & REX_X) != 0,
2494 (x->rex & REX_B) != 0);
09137c09 2495 for (j = 0; j < x->operands; j++)
252b5132 2496 {
09137c09
SP		 2497 fprintf (stdout, " #%d: ", j + 1);
2498 pt (x->types[j]);
252b5132 2499 fprintf (stdout, "\n");
09137c09
SP		 2500 if (x->types[j].bitfield.reg8
2501 || x->types[j].bitfield.reg16
2502 || x->types[j].bitfield.reg32
2503 || x->types[j].bitfield.reg64
2504 || x->types[j].bitfield.regmmx
2505 || x->types[j].bitfield.regxmm
2506 || x->types[j].bitfield.regymm
2507 || x->types[j].bitfield.sreg2
2508 || x->types[j].bitfield.sreg3
2509 || x->types[j].bitfield.control
2510 || x->types[j].bitfield.debug
2511 || x->types[j].bitfield.test)
2512 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2513 if (operand_type_check (x->types[j], imm))
2514 pe (x->op[j].imms);
2515 if (operand_type_check (x->types[j], disp))
2516 pe (x->op[j].disps);
252b5132
RH		 2517 }
2518}
2519
2520static void
d3ce72d0 2521pte (insn_template *t)
252b5132 2522{
09137c09 2523 unsigned int j;
252b5132 2524 fprintf (stdout, " %d operands ", t->operands);
47926f60 2525 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2526 if (t->extension_opcode != None)
2527 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2528 if (t->opcode_modifier.d)
252b5132 2529 fprintf (stdout, "D");
40fb9820 2530 if (t->opcode_modifier.w)
252b5132
RH		 2531 fprintf (stdout, "W");
2532 fprintf (stdout, "\n");
09137c09 2533 for (j = 0; j < t->operands; j++)
252b5132 2534 {
09137c09
SP		 2535 fprintf (stdout, " #%d type ", j + 1);
2536 pt (t->operand_types[j]);
252b5132
RH		 2537 fprintf (stdout, "\n");
2538 }
2539}
2540
2541static void
e3bb37b5 2542pe (expressionS *e)
252b5132 2543{
24eab124 2544 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2545 fprintf (stdout, " add_number %ld (%lx)\n",
2546 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2547 if (e->X_add_symbol)
2548 {
2549 fprintf (stdout, " add_symbol ");
2550 ps (e->X_add_symbol);
2551 fprintf (stdout, "\n");
2552 }
2553 if (e->X_op_symbol)
2554 {
2555 fprintf (stdout, " op_symbol ");
2556 ps (e->X_op_symbol);
2557 fprintf (stdout, "\n");
2558 }
2559}
2560
2561static void
e3bb37b5 2562ps (symbolS *s)
252b5132
RH		 2563{
2564 fprintf (stdout, "%s type %s%s",
2565 S_GET_NAME (s),
2566 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2567 segment_name (S_GET_SEGMENT (s)));
2568}
2569
7b81dfbb 2570static struct type_name
252b5132 2571 {
40fb9820
L		 2572 i386_operand_type mask;
2573 const char *name;
252b5132 2574 }
7b81dfbb 2575const type_names[] =
252b5132 2576{
40fb9820
L		 2577 { OPERAND_TYPE_REG8, "r8" },
2578 { OPERAND_TYPE_REG16, "r16" },
2579 { OPERAND_TYPE_REG32, "r32" },
2580 { OPERAND_TYPE_REG64, "r64" },
2581 { OPERAND_TYPE_IMM8, "i8" },
2582 { OPERAND_TYPE_IMM8, "i8s" },
2583 { OPERAND_TYPE_IMM16, "i16" },
2584 { OPERAND_TYPE_IMM32, "i32" },
2585 { OPERAND_TYPE_IMM32S, "i32s" },
2586 { OPERAND_TYPE_IMM64, "i64" },
2587 { OPERAND_TYPE_IMM1, "i1" },
2588 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2589 { OPERAND_TYPE_DISP8, "d8" },
2590 { OPERAND_TYPE_DISP16, "d16" },
2591 { OPERAND_TYPE_DISP32, "d32" },
2592 { OPERAND_TYPE_DISP32S, "d32s" },
2593 { OPERAND_TYPE_DISP64, "d64" },
2594 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2595 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2596 { OPERAND_TYPE_CONTROL, "control reg" },
2597 { OPERAND_TYPE_TEST, "test reg" },
2598 { OPERAND_TYPE_DEBUG, "debug reg" },
2599 { OPERAND_TYPE_FLOATREG, "FReg" },
2600 { OPERAND_TYPE_FLOATACC, "FAcc" },
2601 { OPERAND_TYPE_SREG2, "SReg2" },
2602 { OPERAND_TYPE_SREG3, "SReg3" },
2603 { OPERAND_TYPE_ACC, "Acc" },
2604 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2605 { OPERAND_TYPE_REGMMX, "rMMX" },
2606 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2607 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2608 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2609};
2610
2611static void
40fb9820 2612pt (i386_operand_type t)
252b5132 2613{
40fb9820 2614 unsigned int j;
c6fb90c8 2615 i386_operand_type a;
252b5132 2616
40fb9820 2617 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2618 {
2619 a = operand_type_and (t, type_names[j].mask);
0349dc08 2620 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2621 fprintf (stdout, "%s, ", type_names[j].name);
2622 }
252b5132
RH		 2623 fflush (stdout);
2624}
2625
2626#endif /* DEBUG386 */
2627\f
252b5132 2628static bfd_reloc_code_real_type
3956db08 2629reloc (unsigned int size,
64e74474
AM		 2630 int pcrel,
2631 int sign,
2632 bfd_reloc_code_real_type other)
252b5132 2633{
47926f60 2634 if (other != NO_RELOC)
3956db08 2635 {
91d6fa6a 2636 reloc_howto_type *rel;
3956db08
JB		 2637
2638 if (size == 8)
2639 switch (other)
2640 {
64e74474
AM		 2641 case BFD_RELOC_X86_64_GOT32:
2642 return BFD_RELOC_X86_64_GOT64;
2643 break;
2644 case BFD_RELOC_X86_64_PLTOFF64:
2645 return BFD_RELOC_X86_64_PLTOFF64;
2646 break;
2647 case BFD_RELOC_X86_64_GOTPC32:
2648 other = BFD_RELOC_X86_64_GOTPC64;
2649 break;
2650 case BFD_RELOC_X86_64_GOTPCREL:
2651 other = BFD_RELOC_X86_64_GOTPCREL64;
2652 break;
2653 case BFD_RELOC_X86_64_TPOFF32:
2654 other = BFD_RELOC_X86_64_TPOFF64;
2655 break;
2656 case BFD_RELOC_X86_64_DTPOFF32:
2657 other = BFD_RELOC_X86_64_DTPOFF64;
2658 break;
2659 default:
2660 break;
3956db08 2661 }
e05278af
JB		 2662
2663 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2664 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2665 sign = -1;
2666
91d6fa6a
NC		 2667 rel = bfd_reloc_type_lookup (stdoutput, other);
2668 if (!rel)
3956db08 2669 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2670 else if (size != bfd_get_reloc_size (rel))
3956db08 2671 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2672 bfd_get_reloc_size (rel),
3956db08 2673 size);
91d6fa6a 2674 else if (pcrel && !rel->pc_relative)
3956db08 2675 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2676 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2677 && !sign)
91d6fa6a 2678 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2679 && sign > 0))
3956db08
JB		 2680 as_bad (_("relocated field and relocation type differ in signedness"));
2681 else
2682 return other;
2683 return NO_RELOC;
2684 }
252b5132
RH		 2685
2686 if (pcrel)
2687 {
3e73aa7c 2688 if (!sign)
3956db08 2689 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2690 switch (size)
2691 {
2692 case 1: return BFD_RELOC_8_PCREL;
2693 case 2: return BFD_RELOC_16_PCREL;
2694 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2695 case 8: return BFD_RELOC_64_PCREL;
252b5132 2696 }
3956db08 2697 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2698 }
2699 else
2700 {
3956db08 2701 if (sign > 0)
e5cb08ac 2702 switch (size)
3e73aa7c
JH		 2703 {
2704 case 4: return BFD_RELOC_X86_64_32S;
2705 }
2706 else
2707 switch (size)
2708 {
2709 case 1: return BFD_RELOC_8;
2710 case 2: return BFD_RELOC_16;
2711 case 4: return BFD_RELOC_32;
2712 case 8: return BFD_RELOC_64;
2713 }
3956db08
JB		 2714 as_bad (_("cannot do %s %u byte relocation"),
2715 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2716 }
2717
0cc9e1d3 2718 return NO_RELOC;
252b5132
RH		 2719}
2720
47926f60
KH		 2721/* Here we decide which fixups can be adjusted to make them relative to
2722 the beginning of the section instead of the symbol. Basically we need
2723 to make sure that the dynamic relocations are done correctly, so in
2724 some cases we force the original symbol to be used. */
2725
252b5132 2726int
e3bb37b5 2727tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2728{
6d249963 2729#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2730 if (!IS_ELF)
31312f95
AM		 2731 return 1;
2732
a161fe53
AM		 2733 /* Don't adjust pc-relative references to merge sections in 64-bit
2734 mode. */
2735 if (use_rela_relocations
2736 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2737 && fixP->fx_pcrel)
252b5132 2738 return 0;
31312f95 2739
8d01d9a9
AJ		 2740 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2741 and changed later by validate_fix. */
2742 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2743 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2744 return 0;
2745
ce8a8b2f 2746 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2747 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2748 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2749 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2750 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2751 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2752 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2753 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2754 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2755 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2756 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2757 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2758 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2759 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2760 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2761 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2762 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2763 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2764 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2765 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2766 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2767 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2768 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2769 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2770 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2771 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2772 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2773 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2774 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2775 return 0;
31312f95 2776#endif
252b5132
RH		 2777 return 1;
2778}
252b5132 2779
b4cac588 2780static int
e3bb37b5 2781intel_float_operand (const char *mnemonic)
252b5132 2782{
9306ca4a
JB		 2783 /* Note that the value returned is meaningful only for opcodes with (memory)
2784 operands, hence the code here is free to improperly handle opcodes that
2785 have no operands (for better performance and smaller code). */
2786
2787 if (mnemonic[0] != 'f')
2788 return 0; /* non-math */
2789
2790 switch (mnemonic[1])
2791 {
2792 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2793 the fs segment override prefix not currently handled because no
2794 call path can make opcodes without operands get here */
2795 case 'i':
2796 return 2 /* integer op */;
2797 case 'l':
2798 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2799 return 3; /* fldcw/fldenv */
2800 break;
2801 case 'n':
2802 if (mnemonic[2] != 'o' /* fnop */)
2803 return 3; /* non-waiting control op */
2804 break;
2805 case 'r':
2806 if (mnemonic[2] == 's')
2807 return 3; /* frstor/frstpm */
2808 break;
2809 case 's':
2810 if (mnemonic[2] == 'a')
2811 return 3; /* fsave */
2812 if (mnemonic[2] == 't')
2813 {
2814 switch (mnemonic[3])
2815 {
2816 case 'c': /* fstcw */
2817 case 'd': /* fstdw */
2818 case 'e': /* fstenv */
2819 case 's': /* fsts[gw] */
2820 return 3;
2821 }
2822 }
2823 break;
2824 case 'x':
2825 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2826 return 0; /* fxsave/fxrstor are not really math ops */
2827 break;
2828 }
252b5132 2829
9306ca4a 2830 return 1;
252b5132
RH		 2831}
2832
c0f3af97
L		 2833/* Build the VEX prefix. */
2834
2835static void
d3ce72d0 2836build_vex_prefix (const insn_template *t)
c0f3af97
L		 2837{
2838 unsigned int register_specifier;
2839 unsigned int implied_prefix;
2840 unsigned int vector_length;
2841
2842 /* Check register specifier. */
2843 if (i.vex.register_specifier)
4c692bc7 2844 register_specifier = ~register_number (i.vex.register_specifier) & 0xf;
c0f3af97
L		 2845 else
2846 register_specifier = 0xf;
2847
fa99fab2
L		 2848 /* Use 2-byte VEX prefix by swappping destination and source
2849 operand. */
2850 if (!i.swap_operand
2851 && i.operands == i.reg_operands
7f399153 2852 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 2853 && i.tm.opcode_modifier.s
2854 && i.rex == REX_B)
2855 {
2856 unsigned int xchg = i.operands - 1;
2857 union i386_op temp_op;
2858 i386_operand_type temp_type;
2859
2860 temp_type = i.types[xchg];
2861 i.types[xchg] = i.types[0];
2862 i.types[0] = temp_type;
2863 temp_op = i.op[xchg];
2864 i.op[xchg] = i.op[0];
2865 i.op[0] = temp_op;
2866
9c2799c2 2867 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2868
2869 i.rex = REX_R;
2870 xchg = i.rm.regmem;
2871 i.rm.regmem = i.rm.reg;
2872 i.rm.reg = xchg;
2873
2874 /* Use the next insn. */
2875 i.tm = t[1];
2876 }
2877
539f890d
L		 2878 if (i.tm.opcode_modifier.vex == VEXScalar)
2879 vector_length = avxscalar;
2880 else
2881 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 2882
2883 switch ((i.tm.base_opcode >> 8) & 0xff)
2884 {
2885 case 0:
2886 implied_prefix = 0;
2887 break;
2888 case DATA_PREFIX_OPCODE:
2889 implied_prefix = 1;
2890 break;
2891 case REPE_PREFIX_OPCODE:
2892 implied_prefix = 2;
2893 break;
2894 case REPNE_PREFIX_OPCODE:
2895 implied_prefix = 3;
2896 break;
2897 default:
2898 abort ();
2899 }
2900
2901 /* Use 2-byte VEX prefix if possible. */
7f399153 2902 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 2903 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 2904 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2905 {
2906 /* 2-byte VEX prefix. */
2907 unsigned int r;
2908
2909 i.vex.length = 2;
2910 i.vex.bytes[0] = 0xc5;
2911
2912 /* Check the REX.R bit. */
2913 r = (i.rex & REX_R) ? 0 : 1;
2914 i.vex.bytes[1] = (r << 7
2915 | register_specifier << 3
2916 | vector_length << 2
2917 | implied_prefix);
2918 }
2919 else
2920 {
2921 /* 3-byte VEX prefix. */
2922 unsigned int m, w;
2923
f88c9eb0 2924 i.vex.length = 3;
f88c9eb0 2925
7f399153 2926 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 2927 {
7f399153
L		 2928 case VEX0F:
2929 m = 0x1;
80de6e00 2930 i.vex.bytes[0] = 0xc4;
7f399153
L		 2931 break;
2932 case VEX0F38:
2933 m = 0x2;
80de6e00 2934 i.vex.bytes[0] = 0xc4;
7f399153
L		 2935 break;
2936 case VEX0F3A:
2937 m = 0x3;
80de6e00 2938 i.vex.bytes[0] = 0xc4;
7f399153
L		 2939 break;
2940 case XOP08:
5dd85c99
SP		 2941 m = 0x8;
2942 i.vex.bytes[0] = 0x8f;
7f399153
L		 2943 break;
2944 case XOP09:
f88c9eb0
SP		 2945 m = 0x9;
2946 i.vex.bytes[0] = 0x8f;
7f399153
L		 2947 break;
2948 case XOP0A:
f88c9eb0
SP		 2949 m = 0xa;
2950 i.vex.bytes[0] = 0x8f;
7f399153
L		 2951 break;
2952 default:
2953 abort ();
f88c9eb0 2954 }
c0f3af97 2955
c0f3af97
L		 2956 /* The high 3 bits of the second VEX byte are 1's compliment
2957 of RXB bits from REX. */
2958 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2959
2960 /* Check the REX.W bit. */
2961 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 2962 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 2963 {
2964 if (w)
2965 abort ();
2966
1ef99a7b 2967 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 2968 w = 1;
2969 }
2970
2971 i.vex.bytes[2] = (w << 7
2972 | register_specifier << 3
2973 | vector_length << 2
2974 | implied_prefix);
2975 }
2976}
2977
65da13b5
L		 2978static void
2979process_immext (void)
2980{
2981 expressionS *exp;
2982
4c692bc7
JB		 2983 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
2984 && i.operands > 0)
65da13b5 2985 {
4c692bc7
JB		 2986 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
2987 with an opcode suffix which is coded in the same place as an
2988 8-bit immediate field would be.
2989 Here we check those operands and remove them afterwards. */
65da13b5
L		 2990 unsigned int x;
2991
2992 for (x = 0; x < i.operands; x++)
4c692bc7 2993 if (register_number (i.op[x].regs) != x)
65da13b5 2994 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2995 register_prefix, i.op[x].regs->reg_name, x + 1,
2996 i.tm.name);
2997
2998 i.operands = 0;
65da13b5
L		 2999 }
3000
c0f3af97 3001 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3002 which is coded in the same place as an 8-bit immediate field
3003 would be. Here we fake an 8-bit immediate operand from the
3004 opcode suffix stored in tm.extension_opcode.
3005
c1e679ec 3006 AVX instructions also use this encoding, for some of
c0f3af97 3007 3 argument instructions. */
65da13b5 3008
9c2799c2 3009 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 3010 && (i.operands <= 2
3011 || (i.tm.opcode_modifier.vex
3012 && i.operands <= 4)));
65da13b5
L		 3013
3014 exp = &im_expressions[i.imm_operands++];
3015 i.op[i.operands].imms = exp;
3016 i.types[i.operands] = imm8;
3017 i.operands++;
3018 exp->X_op = O_constant;
3019 exp->X_add_number = i.tm.extension_opcode;
3020 i.tm.extension_opcode = None;
3021}
3022
42164a71
L		 3023
3024static int
3025check_hle (void)
3026{
3027 switch (i.tm.opcode_modifier.hleprefixok)
3028 {
3029 default:
3030 abort ();
82c2def5 3031 case HLEPrefixNone:
42164a71
L		 3032 if (i.prefix[HLE_PREFIX] == XACQUIRE_PREFIX_OPCODE)
3033 as_bad (_("invalid instruction `%s' after `xacquire'"),
3034 i.tm.name);
3035 else
3036 as_bad (_("invalid instruction `%s' after `xrelease'"),
3037 i.tm.name);
3038 return 0;
82c2def5 3039 case HLEPrefixLock:
42164a71
L		 3040 if (i.prefix[LOCK_PREFIX])
3041 return 1;
3042 if (i.prefix[HLE_PREFIX] == XACQUIRE_PREFIX_OPCODE)
3043 as_bad (_("missing `lock' with `xacquire'"));
3044 else
3045 as_bad (_("missing `lock' with `xrelease'"));
3046 return 0;
82c2def5 3047 case HLEPrefixAny:
42164a71 3048 return 1;
82c2def5 3049 case HLEPrefixRelease:
42164a71
L		 3050 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3051 {
3052 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3053 i.tm.name);
3054 return 0;
3055 }
3056 if (i.mem_operands == 0
3057 || !operand_type_check (i.types[i.operands - 1], anymem))
3058 {
3059 as_bad (_("memory destination needed for instruction `%s'"
3060 " after `xrelease'"), i.tm.name);
3061 return 0;
3062 }
3063 return 1;
3064 }
3065}
3066
252b5132
RH		 3067/* This is the guts of the machine-dependent assembler. LINE points to a
3068 machine dependent instruction. This function is supposed to emit
3069 the frags/bytes it assembles to. */
3070
3071void
65da13b5 3072md_assemble (char *line)
252b5132 3073{
40fb9820 3074 unsigned int j;
252b5132 3075 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3076 const insn_template *t;
252b5132 3077
47926f60 3078 /* Initialize globals. */
252b5132
RH		 3079 memset (&i, '\0', sizeof (i));
3080 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3081 i.reloc[j] = NO_RELOC;
252b5132
RH		 3082 memset (disp_expressions, '\0', sizeof (disp_expressions));
3083 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3084 save_stack_p = save_stack;
252b5132
RH		 3085
3086 /* First parse an instruction mnemonic & call i386_operand for the operands.
3087 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3088 start of a (possibly prefixed) mnemonic. */
252b5132 3089
29b0f896
AM		 3090 line = parse_insn (line, mnemonic);
3091 if (line == NULL)
3092 return;
252b5132 3093
29b0f896 3094 line = parse_operands (line, mnemonic);
ee86248c 3095 this_operand = -1;
29b0f896
AM		 3096 if (line == NULL)
3097 return;
252b5132 3098
29b0f896
AM		 3099 /* Now we've parsed the mnemonic into a set of templates, and have the
3100 operands at hand. */
3101
3102 /* All intel opcodes have reversed operands except for "bound" and
3103 "enter". We also don't reverse intersegment "jmp" and "call"
3104 instructions with 2 immediate operands so that the immediate segment
050dfa73 3105 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3106 if (intel_syntax
3107 && i.operands > 1
29b0f896 3108 && (strcmp (mnemonic, "bound") != 0)
30123838 3109 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3110 && !(operand_type_check (i.types[0], imm)
3111 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3112 swap_operands ();
3113
ec56d5c0
JB		 3114 /* The order of the immediates should be reversed
3115 for 2 immediates extrq and insertq instructions */
3116 if (i.imm_operands == 2
3117 && (strcmp (mnemonic, "extrq") == 0
3118 || strcmp (mnemonic, "insertq") == 0))
3119 swap_2_operands (0, 1);
3120
29b0f896
AM		 3121 if (i.imm_operands)
3122 optimize_imm ();
3123
b300c311
L		 3124 /* Don't optimize displacement for movabs since it only takes 64bit
3125 displacement. */
3126 if (i.disp_operands
a501d77e 3127 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3128 && (flag_code != CODE_64BIT
3129 || strcmp (mnemonic, "movabs") != 0))
3130 optimize_disp ();
29b0f896
AM		 3131
3132 /* Next, we find a template that matches the given insn,
3133 making sure the overlap of the given operands types is consistent
3134 with the template operand types. */
252b5132 3135
fa99fab2 3136 if (!(t = match_template ()))
29b0f896 3137 return;
252b5132 3138
daf50ae7 3139 if (sse_check != sse_check_none
81f8a913 3140 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3141 && (i.tm.cpu_flags.bitfield.cpusse
3142 || i.tm.cpu_flags.bitfield.cpusse2
3143 || i.tm.cpu_flags.bitfield.cpusse3
3144 || i.tm.cpu_flags.bitfield.cpussse3
3145 || i.tm.cpu_flags.bitfield.cpusse4_1
3146 || i.tm.cpu_flags.bitfield.cpusse4_2))
3147 {
3148 (sse_check == sse_check_warning
3149 ? as_warn
3150 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3151 }
3152
321fd21e
L		 3153 /* Zap movzx and movsx suffix. The suffix has been set from
3154 "word ptr" or "byte ptr" on the source operand in Intel syntax
3155 or extracted from mnemonic in AT&T syntax. But we'll use
3156 the destination register to choose the suffix for encoding. */
3157 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3158 {
321fd21e
L		 3159 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3160 there is no suffix, the default will be byte extension. */
3161 if (i.reg_operands != 2
3162 && !i.suffix
7ab9ffdd 3163 && intel_syntax)
321fd21e
L		 3164 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3165
3166 i.suffix = 0;
cd61ebfe 3167 }
24eab124 3168
40fb9820 3169 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3170 if (!add_prefix (FWAIT_OPCODE))
3171 return;
252b5132 3172
c1ba0266
L		 3173 /* Check for lock without a lockable instruction. Destination operand
3174 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3175 if (i.prefix[LOCK_PREFIX]
3176 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3177 || i.mem_operands == 0
3178 || (i.tm.base_opcode != 0x86
3179 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3180 {
3181 as_bad (_("expecting lockable instruction after `lock'"));
3182 return;
3183 }
3184
42164a71
L		 3185 /* Check if HLE prefix is OK. */
3186 if (i.have_hle && !check_hle ())
3187 return;
3188
29b0f896 3189 /* Check string instruction segment overrides. */
40fb9820 3190 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3191 {
3192 if (!check_string ())
5dd0794d 3193 return;
fc0763e6 3194 i.disp_operands = 0;
29b0f896 3195 }
5dd0794d 3196
29b0f896
AM		 3197 if (!process_suffix ())
3198 return;
e413e4e9 3199
bc0844ae
L		 3200 /* Update operand types. */
3201 for (j = 0; j < i.operands; j++)
3202 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3203
29b0f896
AM		 3204 /* Make still unresolved immediate matches conform to size of immediate
3205 given in i.suffix. */
3206 if (!finalize_imm ())
3207 return;
252b5132 3208
40fb9820 3209 if (i.types[0].bitfield.imm1)
29b0f896 3210 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3211
9afe6eb8
L		 3212 /* We only need to check those implicit registers for instructions
3213 with 3 operands or less. */
3214 if (i.operands <= 3)
3215 for (j = 0; j < i.operands; j++)
3216 if (i.types[j].bitfield.inoutportreg
3217 || i.types[j].bitfield.shiftcount
3218 || i.types[j].bitfield.acc
3219 || i.types[j].bitfield.floatacc)
3220 i.reg_operands--;
40fb9820 3221
c0f3af97
L		 3222 /* ImmExt should be processed after SSE2AVX. */
3223 if (!i.tm.opcode_modifier.sse2avx
3224 && i.tm.opcode_modifier.immext)
65da13b5 3225 process_immext ();
252b5132 3226
29b0f896
AM		 3227 /* For insns with operands there are more diddles to do to the opcode. */
3228 if (i.operands)
3229 {
3230 if (!process_operands ())
3231 return;
3232 }
40fb9820 3233 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3234 {
3235 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3236 as_warn (_("translating to `%sp'"), i.tm.name);
3237 }
252b5132 3238
c0f3af97 3239 if (i.tm.opcode_modifier.vex)
fa99fab2 3240 build_vex_prefix (t);
c0f3af97 3241
5dd85c99
SP		 3242 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3243 instructions may define INT_OPCODE as well, so avoid this corner
3244 case for those instructions that use MODRM. */
3245 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3246 && !i.tm.opcode_modifier.modrm
3247 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3248 {
3249 i.tm.base_opcode = INT3_OPCODE;
3250 i.imm_operands = 0;
3251 }
252b5132 3252
40fb9820
L		 3253 if ((i.tm.opcode_modifier.jump
3254 || i.tm.opcode_modifier.jumpbyte
3255 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3256 && i.op[0].disps->X_op == O_constant)
3257 {
3258 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3259 the absolute address given by the constant. Since ix86 jumps and
3260 calls are pc relative, we need to generate a reloc. */
3261 i.op[0].disps->X_add_symbol = &abs_symbol;
3262 i.op[0].disps->X_op = O_symbol;
3263 }
252b5132 3264
40fb9820 3265 if (i.tm.opcode_modifier.rex64)
161a04f6 3266 i.rex |= REX_W;
252b5132 3267
29b0f896
AM		 3268 /* For 8 bit registers we need an empty rex prefix. Also if the
3269 instruction already has a prefix, we need to convert old
3270 registers to new ones. */
773f551c 3271
40fb9820 3272 if ((i.types[0].bitfield.reg8
29b0f896 3273 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3274 || (i.types[1].bitfield.reg8
29b0f896 3275 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3276 || ((i.types[0].bitfield.reg8
3277 || i.types[1].bitfield.reg8)
29b0f896
AM		 3278 && i.rex != 0))
3279 {
3280 int x;
726c5dcd 3281
29b0f896
AM		 3282 i.rex |= REX_OPCODE;
3283 for (x = 0; x < 2; x++)
3284 {
3285 /* Look for 8 bit operand that uses old registers. */
40fb9820 3286 if (i.types[x].bitfield.reg8
29b0f896 3287 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3288 {
29b0f896
AM		 3289 /* In case it is "hi" register, give up. */
3290 if (i.op[x].regs->reg_num > 3)
a540244d 3291 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3292 "instruction requiring REX prefix."),
a540244d 3293 register_prefix, i.op[x].regs->reg_name);
773f551c 3294
29b0f896
AM		 3295 /* Otherwise it is equivalent to the extended register.
3296 Since the encoding doesn't change this is merely
3297 cosmetic cleanup for debug output. */
3298
3299 i.op[x].regs = i.op[x].regs + 8;
773f551c 3300 }
29b0f896
AM		 3301 }
3302 }
773f551c 3303
7ab9ffdd 3304 if (i.rex != 0)
29b0f896
AM		 3305 add_prefix (REX_OPCODE | i.rex);
3306
3307 /* We are ready to output the insn. */
3308 output_insn ();
3309}
3310
3311static char *
e3bb37b5 3312parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3313{
3314 char *l = line;
3315 char *token_start = l;
3316 char *mnem_p;
5c6af06e 3317 int supported;
d3ce72d0 3318 const insn_template *t;
b6169b20 3319 char *dot_p = NULL;
29b0f896
AM		 3320
3321 /* Non-zero if we found a prefix only acceptable with string insns. */
3322 const char *expecting_string_instruction = NULL;
45288df1 3323
29b0f896
AM		 3324 while (1)
3325 {
3326 mnem_p = mnemonic;
3327 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3328 {
b6169b20
L		 3329 if (*mnem_p == '.')
3330 dot_p = mnem_p;
29b0f896
AM		 3331 mnem_p++;
3332 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3333 {
29b0f896
AM		 3334 as_bad (_("no such instruction: `%s'"), token_start);
3335 return NULL;
3336 }
3337 l++;
3338 }
3339 if (!is_space_char (*l)
3340 && *l != END_OF_INSN
e44823cf
JB		 3341 && (intel_syntax
3342 || (*l != PREFIX_SEPARATOR
3343 && *l != ',')))
29b0f896
AM		 3344 {
3345 as_bad (_("invalid character %s in mnemonic"),
3346 output_invalid (*l));
3347 return NULL;
3348 }
3349 if (token_start == l)
3350 {
e44823cf 3351 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3352 as_bad (_("expecting prefix; got nothing"));
3353 else
3354 as_bad (_("expecting mnemonic; got nothing"));
3355 return NULL;
3356 }
45288df1 3357
29b0f896 3358 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3359 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3360
29b0f896
AM		 3361 if (*l != END_OF_INSN
3362 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3363 && current_templates
40fb9820 3364 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3365 {
c6fb90c8 3366 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3367 {
3368 as_bad ((flag_code != CODE_64BIT
3369 ? _("`%s' is only supported in 64-bit mode")
3370 : _("`%s' is not supported in 64-bit mode")),
3371 current_templates->start->name);
3372 return NULL;
3373 }
29b0f896
AM		 3374 /* If we are in 16-bit mode, do not allow addr16 or data16.
3375 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3376 if ((current_templates->start->opcode_modifier.size16
3377 || current_templates->start->opcode_modifier.size32)
29b0f896 3378 && flag_code != CODE_64BIT
40fb9820 3379 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3380 ^ (flag_code == CODE_16BIT)))
3381 {
3382 as_bad (_("redundant %s prefix"),
3383 current_templates->start->name);
3384 return NULL;
45288df1 3385 }
29b0f896
AM		 3386 /* Add prefix, checking for repeated prefixes. */
3387 switch (add_prefix (current_templates->start->base_opcode))
3388 {
c32fa91d 3389 case PREFIX_EXIST:
29b0f896 3390 return NULL;
c32fa91d 3391 case PREFIX_REP:
42164a71
L		 3392 if (current_templates->start->cpu_flags.bitfield.cpuhle)
3393 i.have_hle = 1;
3394 else
3395 expecting_string_instruction = current_templates->start->name;
29b0f896 3396 break;
c32fa91d
L		 3397 default:
3398 break;
29b0f896
AM		 3399 }
3400 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3401 token_start = ++l;
3402 }
3403 else
3404 break;
3405 }
45288df1 3406
30a55f88 3407 if (!current_templates)
b6169b20 3408 {
f8a5c266
L		 3409 /* Check if we should swap operand or force 32bit displacement in
3410 encoding. */
30a55f88
L		 3411 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3412 i.swap_operand = 1;
8d63c93e 3413 else if (mnem_p - 3 == dot_p
a501d77e
L		 3414 && dot_p[1] == 'd'
3415 && dot_p[2] == '8')
3416 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3417 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3418 && dot_p[1] == 'd'
3419 && dot_p[2] == '3'
3420 && dot_p[3] == '2')
a501d77e 3421 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3422 else
3423 goto check_suffix;
3424 mnem_p = dot_p;
3425 *dot_p = '\0';
d3ce72d0 3426 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3427 }
3428
29b0f896
AM		 3429 if (!current_templates)
3430 {
b6169b20 3431check_suffix:
29b0f896
AM		 3432 /* See if we can get a match by trimming off a suffix. */
3433 switch (mnem_p[-1])
3434 {
3435 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3436 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3437 i.suffix = SHORT_MNEM_SUFFIX;
3438 else
29b0f896
AM		 3439 case BYTE_MNEM_SUFFIX:
3440 case QWORD_MNEM_SUFFIX:
3441 i.suffix = mnem_p[-1];
3442 mnem_p[-1] = '\0';
d3ce72d0
NC		 3443 current_templates = (const templates *) hash_find (op_hash,
3444 mnemonic);
29b0f896
AM		 3445 break;
3446 case SHORT_MNEM_SUFFIX:
3447 case LONG_MNEM_SUFFIX:
3448 if (!intel_syntax)
3449 {
3450 i.suffix = mnem_p[-1];
3451 mnem_p[-1] = '\0';
d3ce72d0
NC		 3452 current_templates = (const templates *) hash_find (op_hash,
3453 mnemonic);
29b0f896
AM		 3454 }
3455 break;
252b5132 3456
29b0f896
AM		 3457 /* Intel Syntax. */
3458 case 'd':
3459 if (intel_syntax)
3460 {
9306ca4a 3461 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3462 i.suffix = SHORT_MNEM_SUFFIX;
3463 else
3464 i.suffix = LONG_MNEM_SUFFIX;
3465 mnem_p[-1] = '\0';
d3ce72d0
NC		 3466 current_templates = (const templates *) hash_find (op_hash,
3467 mnemonic);
29b0f896
AM		 3468 }
3469 break;
3470 }
3471 if (!current_templates)
3472 {
3473 as_bad (_("no such instruction: `%s'"), token_start);
3474 return NULL;
3475 }
3476 }
252b5132 3477
40fb9820
L		 3478 if (current_templates->start->opcode_modifier.jump
3479 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3480 {
3481 /* Check for a branch hint. We allow ",pt" and ",pn" for
3482 predict taken and predict not taken respectively.
3483 I'm not sure that branch hints actually do anything on loop
3484 and jcxz insns (JumpByte) for current Pentium4 chips. They
3485 may work in the future and it doesn't hurt to accept them
3486 now. */
3487 if (l[0] == ',' && l[1] == 'p')
3488 {
3489 if (l[2] == 't')
3490 {
3491 if (!add_prefix (DS_PREFIX_OPCODE))
3492 return NULL;
3493 l += 3;
3494 }
3495 else if (l[2] == 'n')
3496 {
3497 if (!add_prefix (CS_PREFIX_OPCODE))
3498 return NULL;
3499 l += 3;
3500 }
3501 }
3502 }
3503 /* Any other comma loses. */
3504 if (*l == ',')
3505 {
3506 as_bad (_("invalid character %s in mnemonic"),
3507 output_invalid (*l));
3508 return NULL;
3509 }
252b5132 3510
29b0f896 3511 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3512 supported = 0;
3513 for (t = current_templates->start; t < current_templates->end; ++t)
3514 {
c0f3af97
L		 3515 supported |= cpu_flags_match (t);
3516 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3517 goto skip;
5c6af06e 3518 }
3629bb00 3519
c0f3af97 3520 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3521 {
3522 as_bad (flag_code == CODE_64BIT
3523 ? _("`%s' is not supported in 64-bit mode")
3524 : _("`%s' is only supported in 64-bit mode"),
3525 current_templates->start->name);
3526 return NULL;
3527 }
c0f3af97 3528 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3529 {
3629bb00 3530 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3531 current_templates->start->name,
41aacd83 3532 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3533 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3534 return NULL;
29b0f896 3535 }
3629bb00
L		 3536
3537skip:
3538 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3539 && (flag_code != CODE_16BIT))
29b0f896
AM		 3540 {
3541 as_warn (_("use .code16 to ensure correct addressing mode"));
3542 }
252b5132 3543
29c048b6 3544 /* Check for rep/repne without a string (or other allowed) instruction. */
f41bbced 3545 if (expecting_string_instruction)
29b0f896 3546 {
f41bbced
JB		 3547 static templates override;
3548
3549 for (t = current_templates->start; t < current_templates->end; ++t)
29c048b6 3550 if (t->opcode_modifier.repprefixok)
f41bbced
JB		 3551 break;
3552 if (t >= current_templates->end)
3553 {
3554 as_bad (_("expecting string instruction after `%s'"),
64e74474 3555 expecting_string_instruction);
f41bbced
JB		 3556 return NULL;
3557 }
3558 for (override.start = t; t < current_templates->end; ++t)
29c048b6 3559 if (!t->opcode_modifier.repprefixok)
f41bbced
JB		 3560 break;
3561 override.end = t;
3562 current_templates = &override;
29b0f896 3563 }
252b5132 3564
29b0f896
AM		 3565 return l;
3566}
252b5132 3567
29b0f896 3568static char *
e3bb37b5 3569parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3570{
3571 char *token_start;
3138f287 3572
29b0f896
AM		 3573 /* 1 if operand is pending after ','. */
3574 unsigned int expecting_operand = 0;
252b5132 3575
29b0f896
AM		 3576 /* Non-zero if operand parens not balanced. */
3577 unsigned int paren_not_balanced;
3578
3579 while (*l != END_OF_INSN)
3580 {
3581 /* Skip optional white space before operand. */
3582 if (is_space_char (*l))
3583 ++l;
3584 if (!is_operand_char (*l) && *l != END_OF_INSN)
3585 {
3586 as_bad (_("invalid character %s before operand %d"),
3587 output_invalid (*l),
3588 i.operands + 1);
3589 return NULL;
3590 }
3591 token_start = l; /* after white space */
3592 paren_not_balanced = 0;
3593 while (paren_not_balanced || *l != ',')
3594 {
3595 if (*l == END_OF_INSN)
3596 {
3597 if (paren_not_balanced)
3598 {
3599 if (!intel_syntax)
3600 as_bad (_("unbalanced parenthesis in operand %d."),
3601 i.operands + 1);
3602 else
3603 as_bad (_("unbalanced brackets in operand %d."),
3604 i.operands + 1);
3605 return NULL;
3606 }
3607 else
3608 break; /* we are done */
3609 }
3610 else if (!is_operand_char (*l) && !is_space_char (*l))
3611 {
3612 as_bad (_("invalid character %s in operand %d"),
3613 output_invalid (*l),
3614 i.operands + 1);
3615 return NULL;
3616 }
3617 if (!intel_syntax)
3618 {
3619 if (*l == '(')
3620 ++paren_not_balanced;
3621 if (*l == ')')
3622 --paren_not_balanced;
3623 }
3624 else
3625 {
3626 if (*l == '[')
3627 ++paren_not_balanced;
3628 if (*l == ']')
3629 --paren_not_balanced;
3630 }
3631 l++;
3632 }
3633 if (l != token_start)
3634 { /* Yes, we've read in another operand. */
3635 unsigned int operand_ok;
3636 this_operand = i.operands++;
7d5e4556 3637 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3638 if (i.operands > MAX_OPERANDS)
3639 {
3640 as_bad (_("spurious operands; (%d operands/instruction max)"),
3641 MAX_OPERANDS);
3642 return NULL;
3643 }
3644 /* Now parse operand adding info to 'i' as we go along. */
3645 END_STRING_AND_SAVE (l);
3646
3647 if (intel_syntax)
3648 operand_ok =
3649 i386_intel_operand (token_start,
3650 intel_float_operand (mnemonic));
3651 else
a7619375 3652 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3653
3654 RESTORE_END_STRING (l);
3655 if (!operand_ok)
3656 return NULL;
3657 }
3658 else
3659 {
3660 if (expecting_operand)
3661 {
3662 expecting_operand_after_comma:
3663 as_bad (_("expecting operand after ','; got nothing"));
3664 return NULL;
3665 }
3666 if (*l == ',')
3667 {
3668 as_bad (_("expecting operand before ','; got nothing"));
3669 return NULL;
3670 }
3671 }
7f3f1ea2 3672
29b0f896
AM		 3673 /* Now *l must be either ',' or END_OF_INSN. */
3674 if (*l == ',')
3675 {
3676 if (*++l == END_OF_INSN)
3677 {
3678 /* Just skip it, if it's \n complain. */
3679 goto expecting_operand_after_comma;
3680 }
3681 expecting_operand = 1;
3682 }
3683 }
3684 return l;
3685}
7f3f1ea2 3686
050dfa73 3687static void
4d456e3d 3688swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3689{
3690 union i386_op temp_op;
40fb9820 3691 i386_operand_type temp_type;
050dfa73 3692 enum bfd_reloc_code_real temp_reloc;
4eed87de 3693
050dfa73
MM		 3694 temp_type = i.types[xchg2];
3695 i.types[xchg2] = i.types[xchg1];
3696 i.types[xchg1] = temp_type;
3697 temp_op = i.op[xchg2];
3698 i.op[xchg2] = i.op[xchg1];
3699 i.op[xchg1] = temp_op;
3700 temp_reloc = i.reloc[xchg2];
3701 i.reloc[xchg2] = i.reloc[xchg1];
3702 i.reloc[xchg1] = temp_reloc;
3703}
3704
29b0f896 3705static void
e3bb37b5 3706swap_operands (void)
29b0f896 3707{
b7c61d9a 3708 switch (i.operands)
050dfa73 3709 {
c0f3af97 3710 case 5:
b7c61d9a 3711 case 4:
4d456e3d 3712 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3713 case 3:
3714 case 2:
4d456e3d 3715 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3716 break;
3717 default:
3718 abort ();
29b0f896 3719 }
29b0f896
AM		 3720
3721 if (i.mem_operands == 2)
3722 {
3723 const seg_entry *temp_seg;
3724 temp_seg = i.seg[0];
3725 i.seg[0] = i.seg[1];
3726 i.seg[1] = temp_seg;
3727 }
3728}
252b5132 3729
29b0f896
AM		 3730/* Try to ensure constant immediates are represented in the smallest
3731 opcode possible. */
3732static void
e3bb37b5 3733optimize_imm (void)
29b0f896
AM		 3734{
3735 char guess_suffix = 0;
3736 int op;
252b5132 3737
29b0f896
AM		 3738 if (i.suffix)
3739 guess_suffix = i.suffix;
3740 else if (i.reg_operands)
3741 {
3742 /* Figure out a suffix from the last register operand specified.
3743 We can't do this properly yet, ie. excluding InOutPortReg,
3744 but the following works for instructions with immediates.
3745 In any case, we can't set i.suffix yet. */
3746 for (op = i.operands; --op >= 0;)
40fb9820 3747 if (i.types[op].bitfield.reg8)
7ab9ffdd 3748 {
40fb9820
L		 3749 guess_suffix = BYTE_MNEM_SUFFIX;
3750 break;
3751 }
3752 else if (i.types[op].bitfield.reg16)
252b5132 3753 {
40fb9820
L		 3754 guess_suffix = WORD_MNEM_SUFFIX;
3755 break;
3756 }
3757 else if (i.types[op].bitfield.reg32)
3758 {
3759 guess_suffix = LONG_MNEM_SUFFIX;
3760 break;
3761 }
3762 else if (i.types[op].bitfield.reg64)
3763 {
3764 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3765 break;
252b5132 3766 }
29b0f896
AM		 3767 }
3768 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3769 guess_suffix = WORD_MNEM_SUFFIX;
3770
3771 for (op = i.operands; --op >= 0;)
40fb9820 3772 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3773 {
3774 switch (i.op[op].imms->X_op)
252b5132 3775 {
29b0f896
AM		 3776 case O_constant:
3777 /* If a suffix is given, this operand may be shortened. */
3778 switch (guess_suffix)
252b5132 3779 {
29b0f896 3780 case LONG_MNEM_SUFFIX:
40fb9820
L		 3781 i.types[op].bitfield.imm32 = 1;
3782 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3783 break;
3784 case WORD_MNEM_SUFFIX:
40fb9820
L		 3785 i.types[op].bitfield.imm16 = 1;
3786 i.types[op].bitfield.imm32 = 1;
3787 i.types[op].bitfield.imm32s = 1;
3788 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3789 break;
3790 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3791 i.types[op].bitfield.imm8 = 1;
3792 i.types[op].bitfield.imm8s = 1;
3793 i.types[op].bitfield.imm16 = 1;
3794 i.types[op].bitfield.imm32 = 1;
3795 i.types[op].bitfield.imm32s = 1;
3796 i.types[op].bitfield.imm64 = 1;
29b0f896 3797 break;
252b5132 3798 }
252b5132 3799
29b0f896
AM		 3800 /* If this operand is at most 16 bits, convert it
3801 to a signed 16 bit number before trying to see
3802 whether it will fit in an even smaller size.
3803 This allows a 16-bit operand such as $0xffe0 to
3804 be recognised as within Imm8S range. */
40fb9820 3805 if ((i.types[op].bitfield.imm16)
29b0f896 3806 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3807 {
29b0f896
AM		 3808 i.op[op].imms->X_add_number =
3809 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3810 }
40fb9820 3811 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3812 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3813 == 0))
3814 {
3815 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3816 ^ ((offsetT) 1 << 31))
3817 - ((offsetT) 1 << 31));
3818 }
40fb9820 3819 i.types[op]
c6fb90c8
L		 3820 = operand_type_or (i.types[op],
3821 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3822
29b0f896
AM		 3823 /* We must avoid matching of Imm32 templates when 64bit
3824 only immediate is available. */
3825 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3826 i.types[op].bitfield.imm32 = 0;
29b0f896 3827 break;
252b5132 3828
29b0f896
AM		 3829 case O_absent:
3830 case O_register:
3831 abort ();
3832
3833 /* Symbols and expressions. */
3834 default:
9cd96992
JB		 3835 /* Convert symbolic operand to proper sizes for matching, but don't
3836 prevent matching a set of insns that only supports sizes other
3837 than those matching the insn suffix. */
3838 {
40fb9820 3839 i386_operand_type mask, allowed;
d3ce72d0 3840 const insn_template *t;
9cd96992 3841
0dfbf9d7
L		 3842 operand_type_set (&mask, 0);
3843 operand_type_set (&allowed, 0);
40fb9820 3844
4eed87de
AM		 3845 for (t = current_templates->start;
3846 t < current_templates->end;
3847 ++t)
c6fb90c8
L		 3848 allowed = operand_type_or (allowed,
3849 t->operand_types[op]);
9cd96992
JB		 3850 switch (guess_suffix)
3851 {
3852 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3853 mask.bitfield.imm64 = 1;
3854 mask.bitfield.imm32s = 1;
9cd96992
JB		 3855 break;
3856 case LONG_MNEM_SUFFIX:
40fb9820 3857 mask.bitfield.imm32 = 1;
9cd96992
JB		 3858 break;
3859 case WORD_MNEM_SUFFIX:
40fb9820 3860 mask.bitfield.imm16 = 1;
9cd96992
JB		 3861 break;
3862 case BYTE_MNEM_SUFFIX:
40fb9820 3863 mask.bitfield.imm8 = 1;
9cd96992
JB		 3864 break;
3865 default:
9cd96992
JB		 3866 break;
3867 }
c6fb90c8 3868 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3869 if (!operand_type_all_zero (&allowed))
c6fb90c8 3870 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3871 }
29b0f896 3872 break;
252b5132 3873 }
29b0f896
AM		 3874 }
3875}
47926f60 3876
29b0f896
AM		 3877/* Try to use the smallest displacement type too. */
3878static void
e3bb37b5 3879optimize_disp (void)
29b0f896
AM		 3880{
3881 int op;
3e73aa7c 3882
29b0f896 3883 for (op = i.operands; --op >= 0;)
40fb9820 3884 if (operand_type_check (i.types[op], disp))
252b5132 3885 {
b300c311 3886 if (i.op[op].disps->X_op == O_constant)
252b5132 3887 {
91d6fa6a 3888 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 3889
40fb9820 3890 if (i.types[op].bitfield.disp16
91d6fa6a 3891 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 3892 {
3893 /* If this operand is at most 16 bits, convert
3894 to a signed 16 bit number and don't use 64bit
3895 displacement. */
91d6fa6a 3896 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3897 i.types[op].bitfield.disp64 = 0;
b300c311 3898 }
40fb9820 3899 if (i.types[op].bitfield.disp32
91d6fa6a 3900 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 3901 {
3902 /* If this operand is at most 32 bits, convert
3903 to a signed 32 bit number and don't use 64bit
3904 displacement. */
91d6fa6a
NC		 3905 op_disp &= (((offsetT) 2 << 31) - 1);
3906 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3907 i.types[op].bitfield.disp64 = 0;
b300c311 3908 }
91d6fa6a 3909 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 3910 {
40fb9820
L		 3911 i.types[op].bitfield.disp8 = 0;
3912 i.types[op].bitfield.disp16 = 0;
3913 i.types[op].bitfield.disp32 = 0;
3914 i.types[op].bitfield.disp32s = 0;
3915 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3916 i.op[op].disps = 0;
3917 i.disp_operands--;
3918 }
3919 else if (flag_code == CODE_64BIT)
3920 {
91d6fa6a 3921 if (fits_in_signed_long (op_disp))
28a9d8f5 3922 {
40fb9820
L		 3923 i.types[op].bitfield.disp64 = 0;
3924 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3925 }
0e1147d9 3926 if (i.prefix[ADDR_PREFIX]
91d6fa6a 3927 && fits_in_unsigned_long (op_disp))
40fb9820 3928 i.types[op].bitfield.disp32 = 1;
b300c311 3929 }
40fb9820
L		 3930 if ((i.types[op].bitfield.disp32
3931 || i.types[op].bitfield.disp32s
3932 || i.types[op].bitfield.disp16)
91d6fa6a 3933 && fits_in_signed_byte (op_disp))
40fb9820 3934 i.types[op].bitfield.disp8 = 1;
252b5132 3935 }
67a4f2b7
AO		 3936 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3937 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3938 {
3939 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3940 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3941 i.types[op].bitfield.disp8 = 0;
3942 i.types[op].bitfield.disp16 = 0;
3943 i.types[op].bitfield.disp32 = 0;
3944 i.types[op].bitfield.disp32s = 0;
3945 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3946 }
3947 else
b300c311 3948 /* We only support 64bit displacement on constants. */
40fb9820 3949 i.types[op].bitfield.disp64 = 0;
252b5132 3950 }
29b0f896
AM		 3951}
3952
6c30d220
L		 3953/* Check if operands are valid for the instruction. */
3954
3955static int
3956check_VecOperands (const insn_template *t)
3957{
3958 /* Without VSIB byte, we can't have a vector register for index. */
3959 if (!t->opcode_modifier.vecsib
3960 && i.index_reg
3961 && (i.index_reg->reg_type.bitfield.regxmm
3962 || i.index_reg->reg_type.bitfield.regymm))
3963 {
3964 i.error = unsupported_vector_index_register;
3965 return 1;
3966 }
3967
3968 /* For VSIB byte, we need a vector register for index and no PC
3969 relative addressing is allowed. */
3970 if (t->opcode_modifier.vecsib
3971 && (!i.index_reg
3972 || !((t->opcode_modifier.vecsib == VecSIB128
3973 && i.index_reg->reg_type.bitfield.regxmm)
3974 || (t->opcode_modifier.vecsib == VecSIB256
3975 && i.index_reg->reg_type.bitfield.regymm))
3976 || (i.base_reg && i.base_reg->reg_num == RegRip)))
3977 {
3978 i.error = invalid_vsib_address;
3979 return 1;
3980 }
3981
3982 return 0;
3983}
3984
43f3e2ee 3985/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 3986 operand types. */
3987
3988static int
3989VEX_check_operands (const insn_template *t)
3990{
3991 if (!t->opcode_modifier.vex)
3992 return 0;
3993
3994 /* Only check VEX_Imm4, which must be the first operand. */
3995 if (t->operand_types[0].bitfield.vec_imm4)
3996 {
3997 if (i.op[0].imms->X_op != O_constant
3998 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 3999 {
a65babc9 4000 i.error = bad_imm4;
891edac4
L		 4001 return 1;
4002 }
a683cc34
SP		 4003
4004 /* Turn off Imm8 so that update_imm won't complain. */
4005 i.types[0] = vec_imm4;
4006 }
4007
4008 return 0;
4009}
4010
d3ce72d0 4011static const insn_template *
e3bb37b5 4012match_template (void)
29b0f896
AM		 4013{
4014 /* Points to template once we've found it. */
d3ce72d0 4015 const insn_template *t;
40fb9820 4016 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4017 i386_operand_type overlap4;
29b0f896 4018 unsigned int found_reverse_match;
40fb9820
L		 4019 i386_opcode_modifier suffix_check;
4020 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4021 int addr_prefix_disp;
a5c311ca 4022 unsigned int j;
3629bb00 4023 unsigned int found_cpu_match;
45664ddb 4024 unsigned int check_register;
5614d22c 4025 enum i386_error specific_error = 0;
29b0f896 4026
c0f3af97
L		 4027#if MAX_OPERANDS != 5
4028# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4029#endif
4030
29b0f896 4031 found_reverse_match = 0;
539e75ad 4032 addr_prefix_disp = -1;
40fb9820
L		 4033
4034 memset (&suffix_check, 0, sizeof (suffix_check));
4035 if (i.suffix == BYTE_MNEM_SUFFIX)
4036 suffix_check.no_bsuf = 1;
4037 else if (i.suffix == WORD_MNEM_SUFFIX)
4038 suffix_check.no_wsuf = 1;
4039 else if (i.suffix == SHORT_MNEM_SUFFIX)
4040 suffix_check.no_ssuf = 1;
4041 else if (i.suffix == LONG_MNEM_SUFFIX)
4042 suffix_check.no_lsuf = 1;
4043 else if (i.suffix == QWORD_MNEM_SUFFIX)
4044 suffix_check.no_qsuf = 1;
4045 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4046 suffix_check.no_ldsuf = 1;
29b0f896 4047
01559ecc
L		 4048 /* Must have right number of operands. */
4049 i.error = number_of_operands_mismatch;
4050
45aa61fe 4051 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4052 {
539e75ad
L		 4053 addr_prefix_disp = -1;
4054
29b0f896
AM		 4055 if (i.operands != t->operands)
4056 continue;
4057
50aecf8c 4058 /* Check processor support. */
a65babc9 4059 i.error = unsupported;
c0f3af97
L		 4060 found_cpu_match = (cpu_flags_match (t)
4061 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4062 if (!found_cpu_match)
4063 continue;
4064
e1d4d893 4065 /* Check old gcc support. */
a65babc9 4066 i.error = old_gcc_only;
e1d4d893
L		 4067 if (!old_gcc && t->opcode_modifier.oldgcc)
4068 continue;
4069
4070 /* Check AT&T mnemonic. */
a65babc9 4071 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4072 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4073 continue;
4074
891edac4 4075 /* Check AT&T/Intel syntax. */
a65babc9 4076 i.error = unsupported_syntax;
5c07affc
L		 4077 if ((intel_syntax && t->opcode_modifier.attsyntax)
4078 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4079 continue;
4080
20592a94 4081 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4082 i.error = invalid_instruction_suffix;
567e4e96
L		 4083 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4084 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4085 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4086 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4087 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4088 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4089 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4090 continue;
4091
5c07affc 4092 if (!operand_size_match (t))
7d5e4556 4093 continue;
539e75ad 4094
5c07affc
L		 4095 for (j = 0; j < MAX_OPERANDS; j++)
4096 operand_types[j] = t->operand_types[j];
4097
45aa61fe
AM		 4098 /* In general, don't allow 64-bit operands in 32-bit mode. */
4099 if (i.suffix == QWORD_MNEM_SUFFIX
4100 && flag_code != CODE_64BIT
4101 && (intel_syntax
40fb9820 4102 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4103 && !intel_float_operand (t->name))
4104 : intel_float_operand (t->name) != 2)
40fb9820 4105 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 4106 && !operand_types[0].bitfield.regxmm
4107 && !operand_types[0].bitfield.regymm)
40fb9820 4108 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 4109 && !!operand_types[t->operands > 1].bitfield.regxmm
4110 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 4111 && (t->base_opcode != 0x0fc7
4112 || t->extension_opcode != 1 /* cmpxchg8b */))
4113 continue;
4114
192dc9c6
JB		 4115 /* In general, don't allow 32-bit operands on pre-386. */
4116 else if (i.suffix == LONG_MNEM_SUFFIX
4117 && !cpu_arch_flags.bitfield.cpui386
4118 && (intel_syntax
4119 ? (!t->opcode_modifier.ignoresize
4120 && !intel_float_operand (t->name))
4121 : intel_float_operand (t->name) != 2)
4122 && ((!operand_types[0].bitfield.regmmx
4123 && !operand_types[0].bitfield.regxmm)
4124 || (!operand_types[t->operands > 1].bitfield.regmmx
4125 && !!operand_types[t->operands > 1].bitfield.regxmm)))
4126 continue;
4127
29b0f896 4128 /* Do not verify operands when there are none. */
50aecf8c 4129 else
29b0f896 4130 {
c6fb90c8 4131 if (!t->operands)
2dbab7d5
L		 4132 /* We've found a match; break out of loop. */
4133 break;
29b0f896 4134 }
252b5132 4135
539e75ad
L		 4136 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4137 into Disp32/Disp16/Disp32 operand. */
4138 if (i.prefix[ADDR_PREFIX] != 0)
4139 {
40fb9820 4140 /* There should be only one Disp operand. */
539e75ad
L		 4141 switch (flag_code)
4142 {
4143 case CODE_16BIT:
40fb9820
L		 4144 for (j = 0; j < MAX_OPERANDS; j++)
4145 {
4146 if (operand_types[j].bitfield.disp16)
4147 {
4148 addr_prefix_disp = j;
4149 operand_types[j].bitfield.disp32 = 1;
4150 operand_types[j].bitfield.disp16 = 0;
4151 break;
4152 }
4153 }
539e75ad
L		 4154 break;
4155 case CODE_32BIT:
40fb9820
L		 4156 for (j = 0; j < MAX_OPERANDS; j++)
4157 {
4158 if (operand_types[j].bitfield.disp32)
4159 {
4160 addr_prefix_disp = j;
4161 operand_types[j].bitfield.disp32 = 0;
4162 operand_types[j].bitfield.disp16 = 1;
4163 break;
4164 }
4165 }
539e75ad
L		 4166 break;
4167 case CODE_64BIT:
40fb9820
L		 4168 for (j = 0; j < MAX_OPERANDS; j++)
4169 {
4170 if (operand_types[j].bitfield.disp64)
4171 {
4172 addr_prefix_disp = j;
4173 operand_types[j].bitfield.disp64 = 0;
4174 operand_types[j].bitfield.disp32 = 1;
4175 break;
4176 }
4177 }
539e75ad
L		 4178 break;
4179 }
539e75ad
L		 4180 }
4181
56ffb741
L		 4182 /* We check register size if needed. */
4183 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4184 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4185 switch (t->operands)
4186 {
4187 case 1:
40fb9820 4188 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4189 continue;
4190 break;
4191 case 2:
8b38ad71
L		 4192 /* xchg %eax, %eax is a special case. It is an aliase for nop
4193 only in 32bit mode and we can use opcode 0x90. In 64bit
4194 mode, we can't use 0x90 for xchg %eax, %eax since it should
4195 zero-extend %eax to %rax. */
4196 if (flag_code == CODE_64BIT
4197 && t->base_opcode == 0x90
0dfbf9d7
L		 4198 && operand_type_equal (&i.types [0], &acc32)
4199 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4200 continue;
b6169b20
L		 4201 if (i.swap_operand)
4202 {
4203 /* If we swap operand in encoding, we either match
4204 the next one or reverse direction of operands. */
4205 if (t->opcode_modifier.s)
4206 continue;
4207 else if (t->opcode_modifier.d)
4208 goto check_reverse;
4209 }
4210
29b0f896 4211 case 3:
fa99fab2
L		 4212 /* If we swap operand in encoding, we match the next one. */
4213 if (i.swap_operand && t->opcode_modifier.s)
4214 continue;
f48ff2ae 4215 case 4:
c0f3af97 4216 case 5:
c6fb90c8 4217 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4218 if (!operand_type_match (overlap0, i.types[0])
4219 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4220 || (check_register
4221 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4222 operand_types[0],
4223 overlap1, i.types[1],
4224 operand_types[1])))
29b0f896
AM		 4225 {
4226 /* Check if other direction is valid ... */
40fb9820 4227 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4228 continue;
4229
b6169b20 4230check_reverse:
29b0f896 4231 /* Try reversing direction of operands. */
c6fb90c8
L		 4232 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4233 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4234 if (!operand_type_match (overlap0, i.types[0])
4235 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4236 || (check_register
4237 && !operand_type_register_match (overlap0,
4238 i.types[0],
4239 operand_types[1],
4240 overlap1,
4241 i.types[1],
4242 operand_types[0])))
29b0f896
AM		 4243 {
4244 /* Does not match either direction. */
4245 continue;
4246 }
4247 /* found_reverse_match holds which of D or FloatDR
4248 we've found. */
40fb9820 4249 if (t->opcode_modifier.d)
8a2ed489 4250 found_reverse_match = Opcode_D;
40fb9820 4251 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4252 found_reverse_match = Opcode_FloatD;
4253 else
4254 found_reverse_match = 0;
40fb9820 4255 if (t->opcode_modifier.floatr)
8a2ed489 4256 found_reverse_match |= Opcode_FloatR;
29b0f896 4257 }
f48ff2ae 4258 else
29b0f896 4259 {
f48ff2ae 4260 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4261 switch (t->operands)
4262 {
c0f3af97
L		 4263 case 5:
4264 overlap4 = operand_type_and (i.types[4],
4265 operand_types[4]);
d1cbb4db 4266 case 4:
c6fb90c8
L		 4267 overlap3 = operand_type_and (i.types[3],
4268 operand_types[3]);
d1cbb4db 4269 case 3:
c6fb90c8
L		 4270 overlap2 = operand_type_and (i.types[2],
4271 operand_types[2]);
d1cbb4db
L		 4272 break;
4273 }
29b0f896 4274
f48ff2ae
L		 4275 switch (t->operands)
4276 {
c0f3af97
L		 4277 case 5:
4278 if (!operand_type_match (overlap4, i.types[4])
4279 || !operand_type_register_match (overlap3,
4280 i.types[3],
4281 operand_types[3],
4282 overlap4,
4283 i.types[4],
4284 operand_types[4]))
4285 continue;
f48ff2ae 4286 case 4:
40fb9820 4287 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4288 || (check_register
4289 && !operand_type_register_match (overlap2,
4290 i.types[2],
4291 operand_types[2],
4292 overlap3,
4293 i.types[3],
4294 operand_types[3])))
f48ff2ae
L		 4295 continue;
4296 case 3:
4297 /* Here we make use of the fact that there are no
4298 reverse match 3 operand instructions, and all 3
4299 operand instructions only need to be checked for
4300 register consistency between operands 2 and 3. */
40fb9820 4301 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4302 || (check_register
4303 && !operand_type_register_match (overlap1,
4304 i.types[1],
4305 operand_types[1],
4306 overlap2,
4307 i.types[2],
4308 operand_types[2])))
f48ff2ae
L		 4309 continue;
4310 break;
4311 }
29b0f896 4312 }
f48ff2ae 4313 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4314 slip through to break. */
4315 }
3629bb00 4316 if (!found_cpu_match)
29b0f896
AM		 4317 {
4318 found_reverse_match = 0;
4319 continue;
4320 }
c0f3af97 4321
5614d22c
JB		 4322 /* Check if vector and VEX operands are valid. */
4323 if (check_VecOperands (t) || VEX_check_operands (t))
4324 {
4325 specific_error = i.error;
4326 continue;
4327 }
a683cc34 4328
29b0f896
AM		 4329 /* We've found a match; break out of loop. */
4330 break;
4331 }
4332
4333 if (t == current_templates->end)
4334 {
4335 /* We found no match. */
a65babc9 4336 const char *err_msg;
5614d22c 4337 switch (specific_error ? specific_error : i.error)
a65babc9
L		 4338 {
4339 default:
4340 abort ();
86e026a4 4341 case operand_size_mismatch:
a65babc9
L		 4342 err_msg = _("operand size mismatch");
4343 break;
4344 case operand_type_mismatch:
4345 err_msg = _("operand type mismatch");
4346 break;
4347 case register_type_mismatch:
4348 err_msg = _("register type mismatch");
4349 break;
4350 case number_of_operands_mismatch:
4351 err_msg = _("number of operands mismatch");
4352 break;
4353 case invalid_instruction_suffix:
4354 err_msg = _("invalid instruction suffix");
4355 break;
4356 case bad_imm4:
4a2608e3 4357 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 4358 break;
4359 case old_gcc_only:
4360 err_msg = _("only supported with old gcc");
4361 break;
4362 case unsupported_with_intel_mnemonic:
4363 err_msg = _("unsupported with Intel mnemonic");
4364 break;
4365 case unsupported_syntax:
4366 err_msg = _("unsupported syntax");
4367 break;
4368 case unsupported:
35262a23 4369 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 4370 current_templates->start->name);
4371 return NULL;
6c30d220
L		 4372 case invalid_vsib_address:
4373 err_msg = _("invalid VSIB address");
4374 break;
4375 case unsupported_vector_index_register:
4376 err_msg = _("unsupported vector index register");
4377 break;
a65babc9
L		 4378 }
4379 as_bad (_("%s for `%s'"), err_msg,
891edac4 4380 current_templates->start->name);
fa99fab2 4381 return NULL;
29b0f896 4382 }
252b5132 4383
29b0f896
AM		 4384 if (!quiet_warnings)
4385 {
4386 if (!intel_syntax
40fb9820
L		 4387 && (i.types[0].bitfield.jumpabsolute
4388 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 4389 {
4390 as_warn (_("indirect %s without `*'"), t->name);
4391 }
4392
40fb9820
L		 4393 if (t->opcode_modifier.isprefix
4394 && t->opcode_modifier.ignoresize)
29b0f896
AM		 4395 {
4396 /* Warn them that a data or address size prefix doesn't
4397 affect assembly of the next line of code. */
4398 as_warn (_("stand-alone `%s' prefix"), t->name);
4399 }
4400 }
4401
4402 /* Copy the template we found. */
4403 i.tm = *t;
539e75ad
L		 4404
4405 if (addr_prefix_disp != -1)
4406 i.tm.operand_types[addr_prefix_disp]
4407 = operand_types[addr_prefix_disp];
4408
29b0f896
AM		 4409 if (found_reverse_match)
4410 {
4411 /* If we found a reverse match we must alter the opcode
4412 direction bit. found_reverse_match holds bits to change
4413 (different for int & float insns). */
4414
4415 i.tm.base_opcode ^= found_reverse_match;
4416
539e75ad
L		 4417 i.tm.operand_types[0] = operand_types[1];
4418 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 4419 }
4420
fa99fab2 4421 return t;
29b0f896
AM		 4422}
4423
4424static int
e3bb37b5 4425check_string (void)
29b0f896 4426{
40fb9820
L		 4427 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4428 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 4429 {
4430 if (i.seg[0] != NULL && i.seg[0] != &es)
4431 {
a87af027 4432 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4433 i.tm.name,
a87af027
JB		 4434 mem_op + 1,
4435 register_prefix);
29b0f896
AM		 4436 return 0;
4437 }
4438 /* There's only ever one segment override allowed per instruction.
4439 This instruction possibly has a legal segment override on the
4440 second operand, so copy the segment to where non-string
4441 instructions store it, allowing common code. */
4442 i.seg[0] = i.seg[1];
4443 }
40fb9820 4444 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 4445 {
4446 if (i.seg[1] != NULL && i.seg[1] != &es)
4447 {
a87af027 4448 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4449 i.tm.name,
a87af027
JB		 4450 mem_op + 2,
4451 register_prefix);
29b0f896
AM		 4452 return 0;
4453 }
4454 }
4455 return 1;
4456}
4457
4458static int
543613e9 4459process_suffix (void)
29b0f896
AM		 4460{
4461 /* If matched instruction specifies an explicit instruction mnemonic
4462 suffix, use it. */
40fb9820
L		 4463 if (i.tm.opcode_modifier.size16)
4464 i.suffix = WORD_MNEM_SUFFIX;
4465 else if (i.tm.opcode_modifier.size32)
4466 i.suffix = LONG_MNEM_SUFFIX;
4467 else if (i.tm.opcode_modifier.size64)
4468 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 4469 else if (i.reg_operands)
4470 {
4471 /* If there's no instruction mnemonic suffix we try to invent one
4472 based on register operands. */
4473 if (!i.suffix)
4474 {
4475 /* We take i.suffix from the last register operand specified,
4476 Destination register type is more significant than source
381d071f
L		 4477 register type. crc32 in SSE4.2 prefers source register
4478 type. */
4479 if (i.tm.base_opcode == 0xf20f38f1)
4480 {
40fb9820
L		 4481 if (i.types[0].bitfield.reg16)
4482 i.suffix = WORD_MNEM_SUFFIX;
4483 else if (i.types[0].bitfield.reg32)
4484 i.suffix = LONG_MNEM_SUFFIX;
4485 else if (i.types[0].bitfield.reg64)
4486 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4487 }
9344ff29 4488 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4489 {
40fb9820 4490 if (i.types[0].bitfield.reg8)
20592a94
L		 4491 i.suffix = BYTE_MNEM_SUFFIX;
4492 }
381d071f
L		 4493
4494 if (!i.suffix)
4495 {
4496 int op;
4497
20592a94
L		 4498 if (i.tm.base_opcode == 0xf20f38f1
4499 || i.tm.base_opcode == 0xf20f38f0)
4500 {
4501 /* We have to know the operand size for crc32. */
4502 as_bad (_("ambiguous memory operand size for `%s`"),
4503 i.tm.name);
4504 return 0;
4505 }
4506
381d071f 4507 for (op = i.operands; --op >= 0;)
40fb9820 4508 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4509 {
40fb9820
L		 4510 if (i.types[op].bitfield.reg8)
4511 {
4512 i.suffix = BYTE_MNEM_SUFFIX;
4513 break;
4514 }
4515 else if (i.types[op].bitfield.reg16)
4516 {
4517 i.suffix = WORD_MNEM_SUFFIX;
4518 break;
4519 }
4520 else if (i.types[op].bitfield.reg32)
4521 {
4522 i.suffix = LONG_MNEM_SUFFIX;
4523 break;
4524 }
4525 else if (i.types[op].bitfield.reg64)
4526 {
4527 i.suffix = QWORD_MNEM_SUFFIX;
4528 break;
4529 }
381d071f
L		 4530 }
4531 }
29b0f896
AM		 4532 }
4533 else if (i.suffix == BYTE_MNEM_SUFFIX)
4534 {
2eb952a4
L		 4535 if (intel_syntax
4536 && i.tm.opcode_modifier.ignoresize
4537 && i.tm.opcode_modifier.no_bsuf)
4538 i.suffix = 0;
4539 else if (!check_byte_reg ())
29b0f896
AM		 4540 return 0;
4541 }
4542 else if (i.suffix == LONG_MNEM_SUFFIX)
4543 {
2eb952a4
L		 4544 if (intel_syntax
4545 && i.tm.opcode_modifier.ignoresize
4546 && i.tm.opcode_modifier.no_lsuf)
4547 i.suffix = 0;
4548 else if (!check_long_reg ())
29b0f896
AM		 4549 return 0;
4550 }
4551 else if (i.suffix == QWORD_MNEM_SUFFIX)
4552 {
955e1e6a
L		 4553 if (intel_syntax
4554 && i.tm.opcode_modifier.ignoresize
4555 && i.tm.opcode_modifier.no_qsuf)
4556 i.suffix = 0;
4557 else if (!check_qword_reg ())
29b0f896
AM		 4558 return 0;
4559 }
4560 else if (i.suffix == WORD_MNEM_SUFFIX)
4561 {
2eb952a4
L		 4562 if (intel_syntax
4563 && i.tm.opcode_modifier.ignoresize
4564 && i.tm.opcode_modifier.no_wsuf)
4565 i.suffix = 0;
4566 else if (!check_word_reg ())
29b0f896
AM		 4567 return 0;
4568 }
c0f3af97
L		 4569 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4570 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4571 {
c0f3af97 4572 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4573 should check if it is a valid suffix. */
4574 }
40fb9820 4575 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4576 /* Do nothing if the instruction is going to ignore the prefix. */
4577 ;
4578 else
4579 abort ();
4580 }
40fb9820 4581 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4582 && !i.suffix
4583 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4584 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4585 {
4586 i.suffix = stackop_size;
4587 }
9306ca4a
JB		 4588 else if (intel_syntax
4589 && !i.suffix
40fb9820
L		 4590 && (i.tm.operand_types[0].bitfield.jumpabsolute
4591 || i.tm.opcode_modifier.jumpbyte
4592 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4593 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4594 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4595 {
4596 switch (flag_code)
4597 {
4598 case CODE_64BIT:
40fb9820 4599 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4600 {
4601 i.suffix = QWORD_MNEM_SUFFIX;
4602 break;
4603 }
4604 case CODE_32BIT:
40fb9820 4605 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4606 i.suffix = LONG_MNEM_SUFFIX;
4607 break;
4608 case CODE_16BIT:
40fb9820 4609 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4610 i.suffix = WORD_MNEM_SUFFIX;
4611 break;
4612 }
4613 }
252b5132 4614
9306ca4a 4615 if (!i.suffix)
29b0f896 4616 {
9306ca4a
JB		 4617 if (!intel_syntax)
4618 {
40fb9820 4619 if (i.tm.opcode_modifier.w)
9306ca4a 4620 {
4eed87de
AM		 4621 as_bad (_("no instruction mnemonic suffix given and "
4622 "no register operands; can't size instruction"));
9306ca4a
JB		 4623 return 0;
4624 }
4625 }
4626 else
4627 {
40fb9820 4628 unsigned int suffixes;
7ab9ffdd 4629
40fb9820
L		 4630 suffixes = !i.tm.opcode_modifier.no_bsuf;
4631 if (!i.tm.opcode_modifier.no_wsuf)
4632 suffixes |= 1 << 1;
4633 if (!i.tm.opcode_modifier.no_lsuf)
4634 suffixes |= 1 << 2;
fc4adea1 4635 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4636 suffixes |= 1 << 3;
4637 if (!i.tm.opcode_modifier.no_ssuf)
4638 suffixes |= 1 << 4;
4639 if (!i.tm.opcode_modifier.no_qsuf)
4640 suffixes |= 1 << 5;
4641
4642 /* There are more than suffix matches. */
4643 if (i.tm.opcode_modifier.w
9306ca4a 4644 || ((suffixes & (suffixes - 1))
40fb9820
L		 4645 && !i.tm.opcode_modifier.defaultsize
4646 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4647 {
4648 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4649 return 0;
4650 }
4651 }
29b0f896 4652 }
252b5132 4653
9306ca4a
JB		 4654 /* Change the opcode based on the operand size given by i.suffix;
4655 We don't need to change things for byte insns. */
4656
582d5edd
L		 4657 if (i.suffix
4658 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4659 && i.suffix != XMMWORD_MNEM_SUFFIX
4660 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4661 {
4662 /* It's not a byte, select word/dword operation. */
40fb9820 4663 if (i.tm.opcode_modifier.w)
29b0f896 4664 {
40fb9820 4665 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4666 i.tm.base_opcode |= 8;
4667 else
4668 i.tm.base_opcode |= 1;
4669 }
0f3f3d8b 4670
29b0f896
AM		 4671 /* Now select between word & dword operations via the operand
4672 size prefix, except for instructions that will ignore this
4673 prefix anyway. */
ca61edf2 4674 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4675 {
ca61edf2
L		 4676 /* The address size override prefix changes the size of the
4677 first operand. */
40fb9820
L		 4678 if ((flag_code == CODE_32BIT
4679 && i.op->regs[0].reg_type.bitfield.reg16)
4680 || (flag_code != CODE_32BIT
4681 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4682 if (!add_prefix (ADDR_PREFIX_OPCODE))
4683 return 0;
4684 }
4685 else if (i.suffix != QWORD_MNEM_SUFFIX
4686 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4687 && !i.tm.opcode_modifier.ignoresize
4688 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4689 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4690 || (flag_code == CODE_64BIT
40fb9820 4691 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4692 {
4693 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4694
40fb9820 4695 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4696 prefix = ADDR_PREFIX_OPCODE;
252b5132 4697
29b0f896
AM		 4698 if (!add_prefix (prefix))
4699 return 0;
24eab124 4700 }
252b5132 4701
29b0f896
AM		 4702 /* Set mode64 for an operand. */
4703 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4704 && flag_code == CODE_64BIT
40fb9820 4705 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4706 {
4707 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4708 need rex64. cmpxchg8b is also a special case. */
4709 if (! (i.operands == 2
4710 && i.tm.base_opcode == 0x90
4711 && i.tm.extension_opcode == None
0dfbf9d7
L		 4712 && operand_type_equal (&i.types [0], &acc64)
4713 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4714 && ! (i.operands == 1
4715 && i.tm.base_opcode == 0xfc7
4716 && i.tm.extension_opcode == 1
40fb9820
L		 4717 && !operand_type_check (i.types [0], reg)
4718 && operand_type_check (i.types [0], anymem)))
f6bee062 4719 i.rex |= REX_W;
46e883c5 4720 }
3e73aa7c 4721
29b0f896
AM		 4722 /* Size floating point instruction. */
4723 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4724 if (i.tm.opcode_modifier.floatmf)
543613e9 4725 i.tm.base_opcode ^= 4;
29b0f896 4726 }
7ecd2f8b 4727
29b0f896
AM		 4728 return 1;
4729}
3e73aa7c 4730
29b0f896 4731static int
543613e9 4732check_byte_reg (void)
29b0f896
AM		 4733{
4734 int op;
543613e9 4735
29b0f896
AM		 4736 for (op = i.operands; --op >= 0;)
4737 {
4738 /* If this is an eight bit register, it's OK. If it's the 16 or
4739 32 bit version of an eight bit register, we will just use the
4740 low portion, and that's OK too. */
40fb9820 4741 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4742 continue;
4743
5a819eb9
JB		 4744 /* I/O port address operands are OK too. */
4745 if (i.tm.operand_types[op].bitfield.inoutportreg)
4746 continue;
4747
9344ff29
L		 4748 /* crc32 doesn't generate this warning. */
4749 if (i.tm.base_opcode == 0xf20f38f0)
4750 continue;
4751
40fb9820
L		 4752 if ((i.types[op].bitfield.reg16
4753 || i.types[op].bitfield.reg32
4754 || i.types[op].bitfield.reg64)
5a819eb9
JB		 4755 && i.op[op].regs->reg_num < 4
4756 /* Prohibit these changes in 64bit mode, since the lowering
4757 would be more complicated. */
4758 && flag_code != CODE_64BIT)
29b0f896 4759 {
29b0f896 4760#if REGISTER_WARNINGS
5a819eb9 4761 if (!quiet_warnings)
a540244d
L		 4762 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4763 register_prefix,
40fb9820 4764 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4765 ? REGNAM_AL - REGNAM_AX
4766 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4767 register_prefix,
29b0f896
AM		 4768 i.op[op].regs->reg_name,
4769 i.suffix);
4770#endif
4771 continue;
4772 }
4773 /* Any other register is bad. */
40fb9820
L		 4774 if (i.types[op].bitfield.reg16
4775 || i.types[op].bitfield.reg32
4776 || i.types[op].bitfield.reg64
4777 || i.types[op].bitfield.regmmx
4778 || i.types[op].bitfield.regxmm
c0f3af97 4779 || i.types[op].bitfield.regymm
40fb9820
L		 4780 || i.types[op].bitfield.sreg2
4781 || i.types[op].bitfield.sreg3
4782 || i.types[op].bitfield.control
4783 || i.types[op].bitfield.debug
4784 || i.types[op].bitfield.test
4785 || i.types[op].bitfield.floatreg
4786 || i.types[op].bitfield.floatacc)
29b0f896 4787 {
a540244d
L		 4788 as_bad (_("`%s%s' not allowed with `%s%c'"),
4789 register_prefix,
29b0f896
AM		 4790 i.op[op].regs->reg_name,
4791 i.tm.name,
4792 i.suffix);
4793 return 0;
4794 }
4795 }
4796 return 1;
4797}
4798
4799static int
e3bb37b5 4800check_long_reg (void)
29b0f896
AM		 4801{
4802 int op;
4803
4804 for (op = i.operands; --op >= 0;)
4805 /* Reject eight bit registers, except where the template requires
4806 them. (eg. movzb) */
40fb9820
L		 4807 if (i.types[op].bitfield.reg8
4808 && (i.tm.operand_types[op].bitfield.reg16
4809 || i.tm.operand_types[op].bitfield.reg32
4810 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4811 {
a540244d
L		 4812 as_bad (_("`%s%s' not allowed with `%s%c'"),
4813 register_prefix,
29b0f896
AM		 4814 i.op[op].regs->reg_name,
4815 i.tm.name,
4816 i.suffix);
4817 return 0;
4818 }
4819 /* Warn if the e prefix on a general reg is missing. */
4820 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4821 && i.types[op].bitfield.reg16
4822 && (i.tm.operand_types[op].bitfield.reg32
4823 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4824 {
4825 /* Prohibit these changes in the 64bit mode, since the
4826 lowering is more complicated. */
4827 if (flag_code == CODE_64BIT)
252b5132 4828 {
2b5d6a91 4829 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 4830 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4831 i.suffix);
4832 return 0;
252b5132 4833 }
29b0f896
AM		 4834#if REGISTER_WARNINGS
4835 else
a540244d
L		 4836 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4837 register_prefix,
29b0f896 4838 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4839 register_prefix,
29b0f896
AM		 4840 i.op[op].regs->reg_name,
4841 i.suffix);
4842#endif
252b5132 4843 }
29b0f896 4844 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4845 else if (i.types[op].bitfield.reg64
4846 && (i.tm.operand_types[op].bitfield.reg32
4847 || i.tm.operand_types[op].bitfield.acc))
252b5132 4848 {
34828aad 4849 if (intel_syntax
ca61edf2 4850 && i.tm.opcode_modifier.toqword
40fb9820 4851 && !i.types[0].bitfield.regxmm)
34828aad 4852 {
ca61edf2 4853 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4854 i.suffix = QWORD_MNEM_SUFFIX;
4855 }
4856 else
4857 {
2b5d6a91 4858 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 4859 register_prefix, i.op[op].regs->reg_name,
4860 i.suffix);
4861 return 0;
4862 }
29b0f896
AM		 4863 }
4864 return 1;
4865}
252b5132 4866
29b0f896 4867static int
e3bb37b5 4868check_qword_reg (void)
29b0f896
AM		 4869{
4870 int op;
252b5132 4871
29b0f896
AM		 4872 for (op = i.operands; --op >= 0; )
4873 /* Reject eight bit registers, except where the template requires
4874 them. (eg. movzb) */
40fb9820
L		 4875 if (i.types[op].bitfield.reg8
4876 && (i.tm.operand_types[op].bitfield.reg16
4877 || i.tm.operand_types[op].bitfield.reg32
4878 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4879 {
a540244d
L		 4880 as_bad (_("`%s%s' not allowed with `%s%c'"),
4881 register_prefix,
29b0f896
AM		 4882 i.op[op].regs->reg_name,
4883 i.tm.name,
4884 i.suffix);
4885 return 0;
4886 }
4887 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4888 else if ((i.types[op].bitfield.reg16
4889 || i.types[op].bitfield.reg32)
4890 && (i.tm.operand_types[op].bitfield.reg32
4891 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4892 {
4893 /* Prohibit these changes in the 64bit mode, since the
4894 lowering is more complicated. */
34828aad 4895 if (intel_syntax
ca61edf2 4896 && i.tm.opcode_modifier.todword
40fb9820 4897 && !i.types[0].bitfield.regxmm)
34828aad 4898 {
ca61edf2 4899 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4900 i.suffix = LONG_MNEM_SUFFIX;
4901 }
4902 else
4903 {
2b5d6a91 4904 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 4905 register_prefix, i.op[op].regs->reg_name,
4906 i.suffix);
4907 return 0;
4908 }
252b5132 4909 }
29b0f896
AM		 4910 return 1;
4911}
252b5132 4912
29b0f896 4913static int
e3bb37b5 4914check_word_reg (void)
29b0f896
AM		 4915{
4916 int op;
4917 for (op = i.operands; --op >= 0;)
4918 /* Reject eight bit registers, except where the template requires
4919 them. (eg. movzb) */
40fb9820
L		 4920 if (i.types[op].bitfield.reg8
4921 && (i.tm.operand_types[op].bitfield.reg16
4922 || i.tm.operand_types[op].bitfield.reg32
4923 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4924 {
a540244d
L		 4925 as_bad (_("`%s%s' not allowed with `%s%c'"),
4926 register_prefix,
29b0f896
AM		 4927 i.op[op].regs->reg_name,
4928 i.tm.name,
4929 i.suffix);
4930 return 0;
4931 }
4932 /* Warn if the e prefix on a general reg is present. */
4933 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4934 && i.types[op].bitfield.reg32
4935 && (i.tm.operand_types[op].bitfield.reg16
4936 || i.tm.operand_types[op].bitfield.acc))
252b5132 4937 {
29b0f896
AM		 4938 /* Prohibit these changes in the 64bit mode, since the
4939 lowering is more complicated. */
4940 if (flag_code == CODE_64BIT)
252b5132 4941 {
2b5d6a91 4942 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 4943 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4944 i.suffix);
4945 return 0;
252b5132 4946 }
29b0f896
AM		 4947 else
4948#if REGISTER_WARNINGS
a540244d
L		 4949 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4950 register_prefix,
29b0f896 4951 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4952 register_prefix,
29b0f896
AM		 4953 i.op[op].regs->reg_name,
4954 i.suffix);
4955#endif
4956 }
4957 return 1;
4958}
252b5132 4959
29b0f896 4960static int
40fb9820 4961update_imm (unsigned int j)
29b0f896 4962{
bc0844ae 4963 i386_operand_type overlap = i.types[j];
40fb9820
L		 4964 if ((overlap.bitfield.imm8
4965 || overlap.bitfield.imm8s
4966 || overlap.bitfield.imm16
4967 || overlap.bitfield.imm32
4968 || overlap.bitfield.imm32s
4969 || overlap.bitfield.imm64)
0dfbf9d7
L		 4970 && !operand_type_equal (&overlap, &imm8)
4971 && !operand_type_equal (&overlap, &imm8s)
4972 && !operand_type_equal (&overlap, &imm16)
4973 && !operand_type_equal (&overlap, &imm32)
4974 && !operand_type_equal (&overlap, &imm32s)
4975 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4976 {
4977 if (i.suffix)
4978 {
40fb9820
L		 4979 i386_operand_type temp;
4980
0dfbf9d7 4981 operand_type_set (&temp, 0);
7ab9ffdd 4982 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 4983 {
4984 temp.bitfield.imm8 = overlap.bitfield.imm8;
4985 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4986 }
4987 else if (i.suffix == WORD_MNEM_SUFFIX)
4988 temp.bitfield.imm16 = overlap.bitfield.imm16;
4989 else if (i.suffix == QWORD_MNEM_SUFFIX)
4990 {
4991 temp.bitfield.imm64 = overlap.bitfield.imm64;
4992 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4993 }
4994 else
4995 temp.bitfield.imm32 = overlap.bitfield.imm32;
4996 overlap = temp;
29b0f896 4997 }
0dfbf9d7
L		 4998 else if (operand_type_equal (&overlap, &imm16_32_32s)
4999 || operand_type_equal (&overlap, &imm16_32)
5000 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5001 {
40fb9820 5002 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5003 overlap = imm16;
40fb9820 5004 else
65da13b5 5005 overlap = imm32s;
29b0f896 5006 }
0dfbf9d7
L		 5007 if (!operand_type_equal (&overlap, &imm8)
5008 && !operand_type_equal (&overlap, &imm8s)
5009 && !operand_type_equal (&overlap, &imm16)
5010 && !operand_type_equal (&overlap, &imm32)
5011 && !operand_type_equal (&overlap, &imm32s)
5012 && !operand_type_equal (&overlap, &imm64))
29b0f896 5013 {
4eed87de
AM		 5014 as_bad (_("no instruction mnemonic suffix given; "
5015 "can't determine immediate size"));
29b0f896
AM		 5016 return 0;
5017 }
5018 }
40fb9820 5019 i.types[j] = overlap;
29b0f896 5020
40fb9820
L		 5021 return 1;
5022}
5023
5024static int
5025finalize_imm (void)
5026{
bc0844ae 5027 unsigned int j, n;
29b0f896 5028
bc0844ae
L		 5029 /* Update the first 2 immediate operands. */
5030 n = i.operands > 2 ? 2 : i.operands;
5031 if (n)
5032 {
5033 for (j = 0; j < n; j++)
5034 if (update_imm (j) == 0)
5035 return 0;
40fb9820 5036
bc0844ae
L		 5037 /* The 3rd operand can't be immediate operand. */
5038 gas_assert (operand_type_check (i.types[2], imm) == 0);
5039 }
29b0f896
AM		 5040
5041 return 1;
5042}
5043
c0f3af97
L		 5044static int
5045bad_implicit_operand (int xmm)
5046{
91d6fa6a
NC		 5047 const char *ireg = xmm ? "xmm0" : "ymm0";
5048
c0f3af97
L		 5049 if (intel_syntax)
5050 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5051 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5052 else
5053 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5054 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5055 return 0;
5056}
5057
29b0f896 5058static int
e3bb37b5 5059process_operands (void)
29b0f896
AM		 5060{
5061 /* Default segment register this instruction will use for memory
5062 accesses. 0 means unknown. This is only for optimizing out
5063 unnecessary segment overrides. */
5064 const seg_entry *default_seg = 0;
5065
2426c15f 5066 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5067 {
91d6fa6a
NC		 5068 unsigned int dupl = i.operands;
5069 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5070 unsigned int j;
5071
c0f3af97 5072 /* The destination must be an xmm register. */
9c2799c2 5073 gas_assert (i.reg_operands
91d6fa6a 5074 && MAX_OPERANDS > dupl
7ab9ffdd 5075 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5076
5077 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5078 {
c0f3af97 5079 /* The first operand is implicit and must be xmm0. */
9c2799c2 5080 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5081 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5082 return bad_implicit_operand (1);
5083
8cd7925b 5084 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5085 {
5086 /* Keep xmm0 for instructions with VEX prefix and 3
5087 sources. */
5088 goto duplicate;
5089 }
e2ec9d29 5090 else
c0f3af97
L		 5091 {
5092 /* We remove the first xmm0 and keep the number of
5093 operands unchanged, which in fact duplicates the
5094 destination. */
5095 for (j = 1; j < i.operands; j++)
5096 {
5097 i.op[j - 1] = i.op[j];
5098 i.types[j - 1] = i.types[j];
5099 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5100 }
5101 }
5102 }
5103 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5104 {
91d6fa6a 5105 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5106 && (i.tm.opcode_modifier.vexsources
5107 == VEX3SOURCES));
c0f3af97
L		 5108
5109 /* Add the implicit xmm0 for instructions with VEX prefix
5110 and 3 sources. */
5111 for (j = i.operands; j > 0; j--)
5112 {
5113 i.op[j] = i.op[j - 1];
5114 i.types[j] = i.types[j - 1];
5115 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5116 }
5117 i.op[0].regs
5118 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5119 i.types[0] = regxmm;
c0f3af97
L		 5120 i.tm.operand_types[0] = regxmm;
5121
5122 i.operands += 2;
5123 i.reg_operands += 2;
5124 i.tm.operands += 2;
5125
91d6fa6a 5126 dupl++;
c0f3af97 5127 dest++;
91d6fa6a
NC		 5128 i.op[dupl] = i.op[dest];
5129 i.types[dupl] = i.types[dest];
5130 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5131 }
c0f3af97
L		 5132 else
5133 {
5134duplicate:
5135 i.operands++;
5136 i.reg_operands++;
5137 i.tm.operands++;
5138
91d6fa6a
NC		 5139 i.op[dupl] = i.op[dest];
5140 i.types[dupl] = i.types[dest];
5141 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5142 }
5143
5144 if (i.tm.opcode_modifier.immext)
5145 process_immext ();
5146 }
5147 else if (i.tm.opcode_modifier.firstxmm0)
5148 {
5149 unsigned int j;
5150
5151 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 5152 gas_assert (i.reg_operands
7ab9ffdd
L		 5153 && (operand_type_equal (&i.types[0], &regxmm)
5154 || operand_type_equal (&i.types[0], &regymm)));
4c692bc7 5155 if (register_number (i.op[0].regs) != 0)
c0f3af97 5156 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5157
5158 for (j = 1; j < i.operands; j++)
5159 {
5160 i.op[j - 1] = i.op[j];
5161 i.types[j - 1] = i.types[j];
5162
5163 /* We need to adjust fields in i.tm since they are used by
5164 build_modrm_byte. */
5165 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5166 }
5167
e2ec9d29
L		 5168 i.operands--;
5169 i.reg_operands--;
e2ec9d29
L		 5170 i.tm.operands--;
5171 }
5172 else if (i.tm.opcode_modifier.regkludge)
5173 {
5174 /* The imul $imm, %reg instruction is converted into
5175 imul $imm, %reg, %reg, and the clr %reg instruction
5176 is converted into xor %reg, %reg. */
5177
5178 unsigned int first_reg_op;
5179
5180 if (operand_type_check (i.types[0], reg))
5181 first_reg_op = 0;
5182 else
5183 first_reg_op = 1;
5184 /* Pretend we saw the extra register operand. */
9c2799c2 5185 gas_assert (i.reg_operands == 1
7ab9ffdd 5186 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5187 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5188 i.types[first_reg_op + 1] = i.types[first_reg_op];
5189 i.operands++;
5190 i.reg_operands++;
29b0f896
AM		 5191 }
5192
40fb9820 5193 if (i.tm.opcode_modifier.shortform)
29b0f896 5194 {
40fb9820
L		 5195 if (i.types[0].bitfield.sreg2
5196 || i.types[0].bitfield.sreg3)
29b0f896 5197 {
4eed87de
AM		 5198 if (i.tm.base_opcode == POP_SEG_SHORT
5199 && i.op[0].regs->reg_num == 1)
29b0f896 5200 {
a87af027 5201 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5202 return 0;
29b0f896 5203 }
4eed87de
AM		 5204 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5205 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5206 i.rex |= REX_B;
4eed87de
AM		 5207 }
5208 else
5209 {
7ab9ffdd 5210 /* The register or float register operand is in operand
85f10a01 5211 0 or 1. */
40fb9820 5212 unsigned int op;
7ab9ffdd
L		 5213
5214 if (i.types[0].bitfield.floatreg
5215 || operand_type_check (i.types[0], reg))
5216 op = 0;
5217 else
5218 op = 1;
4eed87de
AM		 5219 /* Register goes in low 3 bits of opcode. */
5220 i.tm.base_opcode |= i.op[op].regs->reg_num;
5221 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5222 i.rex |= REX_B;
40fb9820 5223 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5224 {
4eed87de
AM		 5225 /* Warn about some common errors, but press on regardless.
5226 The first case can be generated by gcc (<= 2.8.1). */
5227 if (i.operands == 2)
5228 {
5229 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5230 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5231 register_prefix, i.op[!intel_syntax].regs->reg_name,
5232 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5233 }
5234 else
5235 {
5236 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5237 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5238 register_prefix, i.op[0].regs->reg_name);
4eed87de 5239 }
29b0f896
AM		 5240 }
5241 }
5242 }
40fb9820 5243 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5244 {
5245 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5246 must be put into the modrm byte). Now, we make the modrm and
5247 index base bytes based on all the info we've collected. */
29b0f896
AM		 5248
5249 default_seg = build_modrm_byte ();
5250 }
8a2ed489 5251 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5252 {
5253 default_seg = &ds;
5254 }
40fb9820 5255 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5256 {
5257 /* For the string instructions that allow a segment override
5258 on one of their operands, the default segment is ds. */
5259 default_seg = &ds;
5260 }
5261
75178d9d
L		 5262 if (i.tm.base_opcode == 0x8d /* lea */
5263 && i.seg[0]
5264 && !quiet_warnings)
30123838 5265 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5266
5267 /* If a segment was explicitly specified, and the specified segment
5268 is not the default, use an opcode prefix to select it. If we
5269 never figured out what the default segment is, then default_seg
5270 will be zero at this point, and the specified segment prefix will
5271 always be used. */
29b0f896
AM		 5272 if ((i.seg[0]) && (i.seg[0] != default_seg))
5273 {
5274 if (!add_prefix (i.seg[0]->seg_prefix))
5275 return 0;
5276 }
5277 return 1;
5278}
5279
5280static const seg_entry *
e3bb37b5 5281build_modrm_byte (void)
29b0f896
AM		 5282{
5283 const seg_entry *default_seg = 0;
c0f3af97 5284 unsigned int source, dest;
8cd7925b 5285 int vex_3_sources;
c0f3af97
L		 5286
5287 /* The first operand of instructions with VEX prefix and 3 sources
5288 must be VEX_Imm4. */
8cd7925b 5289 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5290 if (vex_3_sources)
5291 {
91d6fa6a 5292 unsigned int nds, reg_slot;
4c2c6516 5293 expressionS *exp;
c0f3af97 5294
922d8de8 5295 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5296 && i.tm.opcode_modifier.immext)
5297 {
5298 dest = i.operands - 2;
5299 gas_assert (dest == 3);
5300 }
922d8de8 5301 else
a683cc34 5302 dest = i.operands - 1;
c0f3af97 5303 nds = dest - 1;
922d8de8 5304
a683cc34
SP		 5305 /* There are 2 kinds of instructions:
5306 1. 5 operands: 4 register operands or 3 register operands
5307 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5308 VexW0 or VexW1. The destination must be either XMM or YMM
5309 register.
5310 2. 4 operands: 4 register operands or 3 register operands
5311 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5312 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5313 || (i.reg_operands == 3 && i.mem_operands == 1))
5314 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5315 && (i.tm.opcode_modifier.veximmext
5316 || (i.imm_operands == 1
5317 && i.types[0].bitfield.vec_imm4
5318 && (i.tm.opcode_modifier.vexw == VEXW0
5319 || i.tm.opcode_modifier.vexw == VEXW1)
5320 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
5321 || operand_type_equal (&i.tm.operand_types[dest], &regymm)))));
5322
5323 if (i.imm_operands == 0)
5324 {
5325 /* When there is no immediate operand, generate an 8bit
5326 immediate operand to encode the first operand. */
5327 exp = &im_expressions[i.imm_operands++];
5328 i.op[i.operands].imms = exp;
5329 i.types[i.operands] = imm8;
5330 i.operands++;
5331 /* If VexW1 is set, the first operand is the source and
5332 the second operand is encoded in the immediate operand. */
5333 if (i.tm.opcode_modifier.vexw == VEXW1)
5334 {
5335 source = 0;
5336 reg_slot = 1;
5337 }
5338 else
5339 {
5340 source = 1;
5341 reg_slot = 0;
5342 }
5343
5344 /* FMA swaps REG and NDS. */
5345 if (i.tm.cpu_flags.bitfield.cpufma)
5346 {
5347 unsigned int tmp;
5348 tmp = reg_slot;
5349 reg_slot = nds;
5350 nds = tmp;
5351 }
5352
24981e7b
L		 5353 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5354 &regxmm)
a683cc34
SP		 5355 || operand_type_equal (&i.tm.operand_types[reg_slot],
5356 &regymm));
5357 exp->X_op = O_constant;
4c692bc7 5358 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
a683cc34 5359 }
922d8de8 5360 else
a683cc34
SP		 5361 {
5362 unsigned int imm_slot;
5363
5364 if (i.tm.opcode_modifier.vexw == VEXW0)
5365 {
5366 /* If VexW0 is set, the third operand is the source and
5367 the second operand is encoded in the immediate
5368 operand. */
5369 source = 2;
5370 reg_slot = 1;
5371 }
5372 else
5373 {
5374 /* VexW1 is set, the second operand is the source and
5375 the third operand is encoded in the immediate
5376 operand. */
5377 source = 1;
5378 reg_slot = 2;
5379 }
5380
5381 if (i.tm.opcode_modifier.immext)
5382 {
5383 /* When ImmExt is set, the immdiate byte is the last
5384 operand. */
5385 imm_slot = i.operands - 1;
5386 source--;
5387 reg_slot--;
5388 }
5389 else
5390 {
5391 imm_slot = 0;
5392
5393 /* Turn on Imm8 so that output_imm will generate it. */
5394 i.types[imm_slot].bitfield.imm8 = 1;
5395 }
5396
24981e7b
L		 5397 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5398 &regxmm)
5399 || operand_type_equal (&i.tm.operand_types[reg_slot],
5400 &regymm));
a683cc34 5401 i.op[imm_slot].imms->X_add_number
4c692bc7 5402 |= register_number (i.op[reg_slot].regs) << 4;
a683cc34
SP		 5403 }
5404
5405 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
5406 || operand_type_equal (&i.tm.operand_types[nds],
5407 &regymm));
dae39acc 5408 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 5409 }
5410 else
5411 source = dest = 0;
29b0f896
AM		 5412
5413 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5414 implicit registers do not count. If there are 3 register
5415 operands, it must be a instruction with VexNDS. For a
5416 instruction with VexNDD, the destination register is encoded
5417 in VEX prefix. If there are 4 register operands, it must be
5418 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 5419 if (i.mem_operands == 0
5420 && ((i.reg_operands == 2
2426c15f 5421 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 5422 || (i.reg_operands == 3
2426c15f 5423 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 5424 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5425 {
cab737b9
L		 5426 switch (i.operands)
5427 {
5428 case 2:
5429 source = 0;
5430 break;
5431 case 3:
c81128dc
L		 5432 /* When there are 3 operands, one of them may be immediate,
5433 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5434 the first operand must be shift count register (cl) or it
5435 is an instruction with VexNDS. */
9c2799c2 5436 gas_assert (i.imm_operands == 1
7ab9ffdd 5437 || (i.imm_operands == 0
2426c15f 5438 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 5439 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5440 if (operand_type_check (i.types[0], imm)
5441 || i.types[0].bitfield.shiftcount)
5442 source = 1;
5443 else
5444 source = 0;
cab737b9
L		 5445 break;
5446 case 4:
368d64cc
L		 5447 /* When there are 4 operands, the first two must be 8bit
5448 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5449 one.
5450
5451 For instructions with VexNDS, if the first operand
5452 an imm8, the source operand is the 2nd one. If the last
5453 operand is imm8, the source operand is the first one. */
9c2799c2 5454 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 5455 && i.types[0].bitfield.imm8
5456 && i.types[1].bitfield.imm8)
2426c15f 5457 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 5458 && i.imm_operands == 1
5459 && (i.types[0].bitfield.imm8
5460 || i.types[i.operands - 1].bitfield.imm8)));
9f2670f2
L		 5461 if (i.imm_operands == 2)
5462 source = 2;
5463 else
c0f3af97
L		 5464 {
5465 if (i.types[0].bitfield.imm8)
5466 source = 1;
5467 else
5468 source = 0;
5469 }
c0f3af97
L		 5470 break;
5471 case 5:
cab737b9
L		 5472 break;
5473 default:
5474 abort ();
5475 }
5476
c0f3af97
L		 5477 if (!vex_3_sources)
5478 {
5479 dest = source + 1;
5480
2426c15f 5481 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97
L		 5482 {
5483 /* For instructions with VexNDS, the register-only
f12dc422
L		 5484 source operand must be 32/64bit integer, XMM or
5485 YMM register. It is encoded in VEX prefix. We
5486 need to clear RegMem bit before calling
5487 operand_type_equal. */
5488
5489 i386_operand_type op;
5490 unsigned int vvvv;
5491
5492 /* Check register-only source operand when two source
5493 operands are swapped. */
5494 if (!i.tm.operand_types[source].bitfield.baseindex
5495 && i.tm.operand_types[dest].bitfield.baseindex)
5496 {
5497 vvvv = source;
5498 source = dest;
5499 }
5500 else
5501 vvvv = dest;
5502
5503 op = i.tm.operand_types[vvvv];
fa99fab2 5504 op.bitfield.regmem = 0;
c0f3af97 5505 if ((dest + 1) >= i.operands
f12dc422
L		 5506 || (op.bitfield.reg32 != 1
5507 && !op.bitfield.reg64 != 1
5508 && !operand_type_equal (&op, &regxmm)
fa99fab2 5509 && !operand_type_equal (&op, &regymm)))
c0f3af97 5510 abort ();
f12dc422 5511 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 5512 dest++;
5513 }
5514 }
29b0f896
AM		 5515
5516 i.rm.mode = 3;
5517 /* One of the register operands will be encoded in the i.tm.reg
5518 field, the other in the combined i.tm.mode and i.tm.regmem
5519 fields. If no form of this instruction supports a memory
5520 destination operand, then we assume the source operand may
5521 sometimes be a memory operand and so we need to store the
5522 destination in the i.rm.reg field. */
40fb9820
L		 5523 if (!i.tm.operand_types[dest].bitfield.regmem
5524 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5525 {
5526 i.rm.reg = i.op[dest].regs->reg_num;
5527 i.rm.regmem = i.op[source].regs->reg_num;
5528 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5529 i.rex |= REX_R;
29b0f896 5530 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5531 i.rex |= REX_B;
29b0f896
AM		 5532 }
5533 else
5534 {
5535 i.rm.reg = i.op[source].regs->reg_num;
5536 i.rm.regmem = i.op[dest].regs->reg_num;
5537 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5538 i.rex |= REX_B;
29b0f896 5539 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5540 i.rex |= REX_R;
29b0f896 5541 }
161a04f6 5542 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5543 {
40fb9820
L		 5544 if (!i.types[0].bitfield.control
5545 && !i.types[1].bitfield.control)
c4a530c5 5546 abort ();
161a04f6 5547 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5548 add_prefix (LOCK_PREFIX_OPCODE);
5549 }
29b0f896
AM		 5550 }
5551 else
5552 { /* If it's not 2 reg operands... */
c0f3af97
L		 5553 unsigned int mem;
5554
29b0f896
AM		 5555 if (i.mem_operands)
5556 {
5557 unsigned int fake_zero_displacement = 0;
99018f42 5558 unsigned int op;
4eed87de 5559
7ab9ffdd
L		 5560 for (op = 0; op < i.operands; op++)
5561 if (operand_type_check (i.types[op], anymem))
5562 break;
7ab9ffdd 5563 gas_assert (op < i.operands);
29b0f896 5564
6c30d220
L		 5565 if (i.tm.opcode_modifier.vecsib)
5566 {
5567 if (i.index_reg->reg_num == RegEiz
5568 || i.index_reg->reg_num == RegRiz)
5569 abort ();
5570
5571 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5572 if (!i.base_reg)
5573 {
5574 i.sib.base = NO_BASE_REGISTER;
5575 i.sib.scale = i.log2_scale_factor;
5576 i.types[op].bitfield.disp8 = 0;
5577 i.types[op].bitfield.disp16 = 0;
5578 i.types[op].bitfield.disp64 = 0;
5579 if (flag_code != CODE_64BIT)
5580 {
5581 /* Must be 32 bit */
5582 i.types[op].bitfield.disp32 = 1;
5583 i.types[op].bitfield.disp32s = 0;
5584 }
5585 else
5586 {
5587 i.types[op].bitfield.disp32 = 0;
5588 i.types[op].bitfield.disp32s = 1;
5589 }
5590 }
5591 i.sib.index = i.index_reg->reg_num;
5592 if ((i.index_reg->reg_flags & RegRex) != 0)
5593 i.rex |= REX_X;
5594 }
5595
29b0f896
AM		 5596 default_seg = &ds;
5597
5598 if (i.base_reg == 0)
5599 {
5600 i.rm.mode = 0;
5601 if (!i.disp_operands)
6c30d220
L		 5602 {
5603 fake_zero_displacement = 1;
5604 /* Instructions with VSIB byte need 32bit displacement
5605 if there is no base register. */
5606 if (i.tm.opcode_modifier.vecsib)
5607 i.types[op].bitfield.disp32 = 1;
5608 }
29b0f896
AM		 5609 if (i.index_reg == 0)
5610 {
6c30d220 5611 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 5612 /* Operand is just <disp> */
20f0a1fc 5613 if (flag_code == CODE_64BIT)
29b0f896
AM		 5614 {
5615 /* 64bit mode overwrites the 32bit absolute
5616 addressing by RIP relative addressing and
5617 absolute addressing is encoded by one of the
5618 redundant SIB forms. */
5619 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5620 i.sib.base = NO_BASE_REGISTER;
5621 i.sib.index = NO_INDEX_REGISTER;
fc225355 5622 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5623 ? disp32s : disp32);
20f0a1fc 5624 }
fc225355
L		 5625 else if ((flag_code == CODE_16BIT)
5626 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5627 {
5628 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5629 i.types[op] = disp16;
20f0a1fc
NC		 5630 }
5631 else
5632 {
5633 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5634 i.types[op] = disp32;
29b0f896
AM		 5635 }
5636 }
6c30d220 5637 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 5638 {
6c30d220 5639 /* !i.base_reg && i.index_reg */
db51cc60
L		 5640 if (i.index_reg->reg_num == RegEiz
5641 || i.index_reg->reg_num == RegRiz)
5642 i.sib.index = NO_INDEX_REGISTER;
5643 else
5644 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5645 i.sib.base = NO_BASE_REGISTER;
5646 i.sib.scale = i.log2_scale_factor;
5647 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5648 i.types[op].bitfield.disp8 = 0;
5649 i.types[op].bitfield.disp16 = 0;
5650 i.types[op].bitfield.disp64 = 0;
29b0f896 5651 if (flag_code != CODE_64BIT)
40fb9820
L		 5652 {
5653 /* Must be 32 bit */
5654 i.types[op].bitfield.disp32 = 1;
5655 i.types[op].bitfield.disp32s = 0;
5656 }
29b0f896 5657 else
40fb9820
L		 5658 {
5659 i.types[op].bitfield.disp32 = 0;
5660 i.types[op].bitfield.disp32s = 1;
5661 }
29b0f896 5662 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5663 i.rex |= REX_X;
29b0f896
AM		 5664 }
5665 }
5666 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5667 else if (i.base_reg->reg_num == RegRip ||
5668 i.base_reg->reg_num == RegEip)
29b0f896 5669 {
6c30d220 5670 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 5671 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5672 i.types[op].bitfield.disp8 = 0;
5673 i.types[op].bitfield.disp16 = 0;
5674 i.types[op].bitfield.disp32 = 0;
5675 i.types[op].bitfield.disp32s = 1;
5676 i.types[op].bitfield.disp64 = 0;
71903a11 5677 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5678 if (! i.disp_operands)
5679 fake_zero_displacement = 1;
29b0f896 5680 }
40fb9820 5681 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 5682 {
6c30d220 5683 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 5684 switch (i.base_reg->reg_num)
5685 {
5686 case 3: /* (%bx) */
5687 if (i.index_reg == 0)
5688 i.rm.regmem = 7;
5689 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5690 i.rm.regmem = i.index_reg->reg_num - 6;
5691 break;
5692 case 5: /* (%bp) */
5693 default_seg = &ss;
5694 if (i.index_reg == 0)
5695 {
5696 i.rm.regmem = 6;
40fb9820 5697 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5698 {
5699 /* fake (%bp) into 0(%bp) */
40fb9820 5700 i.types[op].bitfield.disp8 = 1;
252b5132 5701 fake_zero_displacement = 1;
29b0f896
AM		 5702 }
5703 }
5704 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5705 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5706 break;
5707 default: /* (%si) -> 4 or (%di) -> 5 */
5708 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5709 }
5710 i.rm.mode = mode_from_disp_size (i.types[op]);
5711 }
5712 else /* i.base_reg and 32/64 bit mode */
5713 {
5714 if (flag_code == CODE_64BIT
40fb9820
L		 5715 && operand_type_check (i.types[op], disp))
5716 {
5717 i386_operand_type temp;
0dfbf9d7 5718 operand_type_set (&temp, 0);
40fb9820
L		 5719 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5720 i.types[op] = temp;
5721 if (i.prefix[ADDR_PREFIX] == 0)
5722 i.types[op].bitfield.disp32s = 1;
5723 else
5724 i.types[op].bitfield.disp32 = 1;
5725 }
20f0a1fc 5726
6c30d220
L		 5727 if (!i.tm.opcode_modifier.vecsib)
5728 i.rm.regmem = i.base_reg->reg_num;
29b0f896 5729 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5730 i.rex |= REX_B;
29b0f896
AM		 5731 i.sib.base = i.base_reg->reg_num;
5732 /* x86-64 ignores REX prefix bit here to avoid decoder
5733 complications. */
5734 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5735 {
5736 default_seg = &ss;
5737 if (i.disp_operands == 0)
5738 {
5739 fake_zero_displacement = 1;
40fb9820 5740 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5741 }
5742 }
5743 else if (i.base_reg->reg_num == ESP_REG_NUM)
5744 {
5745 default_seg = &ss;
5746 }
5747 i.sib.scale = i.log2_scale_factor;
5748 if (i.index_reg == 0)
5749 {
6c30d220 5750 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 5751 /* <disp>(%esp) becomes two byte modrm with no index
5752 register. We've already stored the code for esp
5753 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5754 Any base register besides %esp will not use the
5755 extra modrm byte. */
5756 i.sib.index = NO_INDEX_REGISTER;
29b0f896 5757 }
6c30d220 5758 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 5759 {
db51cc60
L		 5760 if (i.index_reg->reg_num == RegEiz
5761 || i.index_reg->reg_num == RegRiz)
5762 i.sib.index = NO_INDEX_REGISTER;
5763 else
5764 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5765 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5766 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5767 i.rex |= REX_X;
29b0f896 5768 }
67a4f2b7
AO		 5769
5770 if (i.disp_operands
5771 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5772 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5773 i.rm.mode = 0;
5774 else
a501d77e
L		 5775 {
5776 if (!fake_zero_displacement
5777 && !i.disp_operands
5778 && i.disp_encoding)
5779 {
5780 fake_zero_displacement = 1;
5781 if (i.disp_encoding == disp_encoding_8bit)
5782 i.types[op].bitfield.disp8 = 1;
5783 else
5784 i.types[op].bitfield.disp32 = 1;
5785 }
5786 i.rm.mode = mode_from_disp_size (i.types[op]);
5787 }
29b0f896 5788 }
252b5132 5789
29b0f896
AM		 5790 if (fake_zero_displacement)
5791 {
5792 /* Fakes a zero displacement assuming that i.types[op]
5793 holds the correct displacement size. */
5794 expressionS *exp;
5795
9c2799c2 5796 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5797 exp = &disp_expressions[i.disp_operands++];
5798 i.op[op].disps = exp;
5799 exp->X_op = O_constant;
5800 exp->X_add_number = 0;
5801 exp->X_add_symbol = (symbolS *) 0;
5802 exp->X_op_symbol = (symbolS *) 0;
5803 }
c0f3af97
L		 5804
5805 mem = op;
29b0f896 5806 }
c0f3af97
L		 5807 else
5808 mem = ~0;
252b5132 5809
8c43a48b 5810 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 5811 {
5812 if (operand_type_check (i.types[0], imm))
5813 i.vex.register_specifier = NULL;
5814 else
5815 {
5816 /* VEX.vvvv encodes one of the sources when the first
5817 operand is not an immediate. */
1ef99a7b 5818 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5819 i.vex.register_specifier = i.op[0].regs;
5820 else
5821 i.vex.register_specifier = i.op[1].regs;
5822 }
5823
5824 /* Destination is a XMM register encoded in the ModRM.reg
5825 and VEX.R bit. */
5826 i.rm.reg = i.op[2].regs->reg_num;
5827 if ((i.op[2].regs->reg_flags & RegRex) != 0)
5828 i.rex |= REX_R;
5829
5830 /* ModRM.rm and VEX.B encodes the other source. */
5831 if (!i.mem_operands)
5832 {
5833 i.rm.mode = 3;
5834
1ef99a7b 5835 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5836 i.rm.regmem = i.op[1].regs->reg_num;
5837 else
5838 i.rm.regmem = i.op[0].regs->reg_num;
5839
5840 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5841 i.rex |= REX_B;
5842 }
5843 }
2426c15f 5844 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 5845 {
5846 i.vex.register_specifier = i.op[2].regs;
5847 if (!i.mem_operands)
5848 {
5849 i.rm.mode = 3;
5850 i.rm.regmem = i.op[1].regs->reg_num;
5851 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5852 i.rex |= REX_B;
5853 }
5854 }
29b0f896
AM		 5855 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5856 (if any) based on i.tm.extension_opcode. Again, we must be
5857 careful to make sure that segment/control/debug/test/MMX
5858 registers are coded into the i.rm.reg field. */
f88c9eb0 5859 else if (i.reg_operands)
29b0f896 5860 {
99018f42 5861 unsigned int op;
7ab9ffdd
L		 5862 unsigned int vex_reg = ~0;
5863
5864 for (op = 0; op < i.operands; op++)
5865 if (i.types[op].bitfield.reg8
5866 || i.types[op].bitfield.reg16
5867 || i.types[op].bitfield.reg32
5868 || i.types[op].bitfield.reg64
5869 || i.types[op].bitfield.regmmx
5870 || i.types[op].bitfield.regxmm
5871 || i.types[op].bitfield.regymm
5872 || i.types[op].bitfield.sreg2
5873 || i.types[op].bitfield.sreg3
5874 || i.types[op].bitfield.control
5875 || i.types[op].bitfield.debug
5876 || i.types[op].bitfield.test)
5877 break;
c0209578 5878
7ab9ffdd
L		 5879 if (vex_3_sources)
5880 op = dest;
2426c15f 5881 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 5882 {
5883 /* For instructions with VexNDS, the register-only
5884 source operand is encoded in VEX prefix. */
5885 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5886
7ab9ffdd 5887 if (op > mem)
c0f3af97 5888 {
7ab9ffdd
L		 5889 vex_reg = op++;
5890 gas_assert (op < i.operands);
c0f3af97
L		 5891 }
5892 else
c0f3af97 5893 {
f12dc422
L		 5894 /* Check register-only source operand when two source
5895 operands are swapped. */
5896 if (!i.tm.operand_types[op].bitfield.baseindex
5897 && i.tm.operand_types[op + 1].bitfield.baseindex)
5898 {
5899 vex_reg = op;
5900 op += 2;
5901 gas_assert (mem == (vex_reg + 1)
5902 && op < i.operands);
5903 }
5904 else
5905 {
5906 vex_reg = op + 1;
5907 gas_assert (vex_reg < i.operands);
5908 }
c0f3af97 5909 }
7ab9ffdd 5910 }
2426c15f 5911 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 5912 {
f12dc422 5913 /* For instructions with VexNDD, the register destination
7ab9ffdd 5914 is encoded in VEX prefix. */
f12dc422
L		 5915 if (i.mem_operands == 0)
5916 {
5917 /* There is no memory operand. */
5918 gas_assert ((op + 2) == i.operands);
5919 vex_reg = op + 1;
5920 }
5921 else
8d63c93e 5922 {
f12dc422
L		 5923 /* There are only 2 operands. */
5924 gas_assert (op < 2 && i.operands == 2);
5925 vex_reg = 1;
5926 }
7ab9ffdd
L		 5927 }
5928 else
5929 gas_assert (op < i.operands);
99018f42 5930
7ab9ffdd
L		 5931 if (vex_reg != (unsigned int) ~0)
5932 {
f12dc422 5933 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 5934
f12dc422
L		 5935 if (type->bitfield.reg32 != 1
5936 && type->bitfield.reg64 != 1
5937 && !operand_type_equal (type, &regxmm)
5938 && !operand_type_equal (type, &regymm))
7ab9ffdd 5939 abort ();
f88c9eb0 5940
7ab9ffdd
L		 5941 i.vex.register_specifier = i.op[vex_reg].regs;
5942 }
5943
1b9f0c97
L		 5944 /* Don't set OP operand twice. */
5945 if (vex_reg != op)
7ab9ffdd 5946 {
1b9f0c97
L		 5947 /* If there is an extension opcode to put here, the
5948 register number must be put into the regmem field. */
5949 if (i.tm.extension_opcode != None)
5950 {
5951 i.rm.regmem = i.op[op].regs->reg_num;
5952 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5953 i.rex |= REX_B;
5954 }
5955 else
5956 {
5957 i.rm.reg = i.op[op].regs->reg_num;
5958 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5959 i.rex |= REX_R;
5960 }
7ab9ffdd 5961 }
252b5132 5962
29b0f896
AM		 5963 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5964 must set it to 3 to indicate this is a register operand
5965 in the regmem field. */
5966 if (!i.mem_operands)
5967 i.rm.mode = 3;
5968 }
252b5132 5969
29b0f896 5970 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 5971 if (i.tm.extension_opcode != None)
29b0f896
AM		 5972 i.rm.reg = i.tm.extension_opcode;
5973 }
5974 return default_seg;
5975}
252b5132 5976
29b0f896 5977static void
e3bb37b5 5978output_branch (void)
29b0f896
AM		 5979{
5980 char *p;
f8a5c266 5981 int size;
29b0f896
AM		 5982 int code16;
5983 int prefix;
5984 relax_substateT subtype;
5985 symbolS *sym;
5986 offsetT off;
5987
f8a5c266 5988 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 5989 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 5990
5991 prefix = 0;
5992 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5993 {
29b0f896
AM		 5994 prefix = 1;
5995 i.prefixes -= 1;
5996 code16 ^= CODE16;
252b5132 5997 }
29b0f896
AM		 5998 /* Pentium4 branch hints. */
5999 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6000 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6001 {
29b0f896
AM		 6002 prefix++;
6003 i.prefixes--;
6004 }
6005 if (i.prefix[REX_PREFIX] != 0)
6006 {
6007 prefix++;
6008 i.prefixes--;
2f66722d
AM		 6009 }
6010
29b0f896
AM		 6011 if (i.prefixes != 0 && !intel_syntax)
6012 as_warn (_("skipping prefixes on this instruction"));
6013
6014 /* It's always a symbol; End frag & setup for relax.
6015 Make sure there is enough room in this frag for the largest
6016 instruction we may generate in md_convert_frag. This is 2
6017 bytes for the opcode and room for the prefix and largest
6018 displacement. */
6019 frag_grow (prefix + 2 + 4);
6020 /* Prefix and 1 opcode byte go in fr_fix. */
6021 p = frag_more (prefix + 1);
6022 if (i.prefix[DATA_PREFIX] != 0)
6023 *p++ = DATA_PREFIX_OPCODE;
6024 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6025 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6026 *p++ = i.prefix[SEG_PREFIX];
6027 if (i.prefix[REX_PREFIX] != 0)
6028 *p++ = i.prefix[REX_PREFIX];
6029 *p = i.tm.base_opcode;
6030
6031 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6032 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6033 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6034 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6035 else
f8a5c266 6036 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6037 subtype |= code16;
3e73aa7c 6038
29b0f896
AM		 6039 sym = i.op[0].disps->X_add_symbol;
6040 off = i.op[0].disps->X_add_number;
3e73aa7c 6041
29b0f896
AM		 6042 if (i.op[0].disps->X_op != O_constant
6043 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6044 {
29b0f896
AM		 6045 /* Handle complex expressions. */
6046 sym = make_expr_symbol (i.op[0].disps);
6047 off = 0;
6048 }
3e73aa7c 6049
29b0f896
AM		 6050 /* 1 possible extra opcode + 4 byte displacement go in var part.
6051 Pass reloc in fr_var. */
6052 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
6053}
3e73aa7c 6054
29b0f896 6055static void
e3bb37b5 6056output_jump (void)
29b0f896
AM		 6057{
6058 char *p;
6059 int size;
3e02c1cc 6060 fixS *fixP;
29b0f896 6061
40fb9820 6062 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6063 {
6064 /* This is a loop or jecxz type instruction. */
6065 size = 1;
6066 if (i.prefix[ADDR_PREFIX] != 0)
6067 {
6068 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6069 i.prefixes -= 1;
6070 }
6071 /* Pentium4 branch hints. */
6072 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6073 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6074 {
6075 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6076 i.prefixes--;
3e73aa7c
JH		 6077 }
6078 }
29b0f896
AM		 6079 else
6080 {
6081 int code16;
3e73aa7c 6082
29b0f896
AM		 6083 code16 = 0;
6084 if (flag_code == CODE_16BIT)
6085 code16 = CODE16;
3e73aa7c 6086
29b0f896
AM		 6087 if (i.prefix[DATA_PREFIX] != 0)
6088 {
6089 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6090 i.prefixes -= 1;
6091 code16 ^= CODE16;
6092 }
252b5132 6093
29b0f896
AM		 6094 size = 4;
6095 if (code16)
6096 size = 2;
6097 }
9fcc94b6 6098
29b0f896
AM		 6099 if (i.prefix[REX_PREFIX] != 0)
6100 {
6101 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6102 i.prefixes -= 1;
6103 }
252b5132 6104
29b0f896
AM		 6105 if (i.prefixes != 0 && !intel_syntax)
6106 as_warn (_("skipping prefixes on this instruction"));
e0890092 6107
42164a71
L		 6108 p = frag_more (i.tm.opcode_length + size);
6109 switch (i.tm.opcode_length)
6110 {
6111 case 2:
6112 *p++ = i.tm.base_opcode >> 8;
6113 case 1:
6114 *p++ = i.tm.base_opcode;
6115 break;
6116 default:
6117 abort ();
6118 }
e0890092 6119
3e02c1cc
AM		 6120 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6121 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
6122
6123 /* All jumps handled here are signed, but don't use a signed limit
6124 check for 32 and 16 bit jumps as we want to allow wrap around at
6125 4G and 64k respectively. */
6126 if (size == 1)
6127 fixP->fx_signed = 1;
29b0f896 6128}
e0890092 6129
29b0f896 6130static void
e3bb37b5 6131output_interseg_jump (void)
29b0f896
AM		 6132{
6133 char *p;
6134 int size;
6135 int prefix;
6136 int code16;
252b5132 6137
29b0f896
AM		 6138 code16 = 0;
6139 if (flag_code == CODE_16BIT)
6140 code16 = CODE16;
a217f122 6141
29b0f896
AM		 6142 prefix = 0;
6143 if (i.prefix[DATA_PREFIX] != 0)
6144 {
6145 prefix = 1;
6146 i.prefixes -= 1;
6147 code16 ^= CODE16;
6148 }
6149 if (i.prefix[REX_PREFIX] != 0)
6150 {
6151 prefix++;
6152 i.prefixes -= 1;
6153 }
252b5132 6154
29b0f896
AM		 6155 size = 4;
6156 if (code16)
6157 size = 2;
252b5132 6158
29b0f896
AM		 6159 if (i.prefixes != 0 && !intel_syntax)
6160 as_warn (_("skipping prefixes on this instruction"));
252b5132 6161
29b0f896
AM		 6162 /* 1 opcode; 2 segment; offset */
6163 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6164
29b0f896
AM		 6165 if (i.prefix[DATA_PREFIX] != 0)
6166 *p++ = DATA_PREFIX_OPCODE;
252b5132 6167
29b0f896
AM		 6168 if (i.prefix[REX_PREFIX] != 0)
6169 *p++ = i.prefix[REX_PREFIX];
252b5132 6170
29b0f896
AM		 6171 *p++ = i.tm.base_opcode;
6172 if (i.op[1].imms->X_op == O_constant)
6173 {
6174 offsetT n = i.op[1].imms->X_add_number;
252b5132 6175
29b0f896
AM		 6176 if (size == 2
6177 && !fits_in_unsigned_word (n)
6178 && !fits_in_signed_word (n))
6179 {
6180 as_bad (_("16-bit jump out of range"));
6181 return;
6182 }
6183 md_number_to_chars (p, n, size);
6184 }
6185 else
6186 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6187 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
6188 if (i.op[0].imms->X_op != O_constant)
6189 as_bad (_("can't handle non absolute segment in `%s'"),
6190 i.tm.name);
6191 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6192}
a217f122 6193
29b0f896 6194static void
e3bb37b5 6195output_insn (void)
29b0f896 6196{
2bbd9c25
JJ		 6197 fragS *insn_start_frag;
6198 offsetT insn_start_off;
6199
29b0f896
AM		 6200 /* Tie dwarf2 debug info to the address at the start of the insn.
6201 We can't do this after the insn has been output as the current
6202 frag may have been closed off. eg. by frag_var. */
6203 dwarf2_emit_insn (0);
6204
2bbd9c25
JJ		 6205 insn_start_frag = frag_now;
6206 insn_start_off = frag_now_fix ();
6207
29b0f896 6208 /* Output jumps. */
40fb9820 6209 if (i.tm.opcode_modifier.jump)
29b0f896 6210 output_branch ();
40fb9820
L		 6211 else if (i.tm.opcode_modifier.jumpbyte
6212 || i.tm.opcode_modifier.jumpdword)
29b0f896 6213 output_jump ();
40fb9820 6214 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6215 output_interseg_jump ();
6216 else
6217 {
6218 /* Output normal instructions here. */
6219 char *p;
6220 unsigned char *q;
47465058 6221 unsigned int j;
331d2d0d 6222 unsigned int prefix;
4dffcebc 6223
c0f3af97 6224 /* Since the VEX prefix contains the implicit prefix, we don't
89e71f5c 6225 need the explicit prefix. */
c0f3af97 6226 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 6227 {
c0f3af97 6228 switch (i.tm.opcode_length)
bc4bd9ab 6229 {
c0f3af97
L		 6230 case 3:
6231 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6232 {
c0f3af97
L		 6233 prefix = (i.tm.base_opcode >> 24) & 0xff;
6234 goto check_prefix;
6235 }
6236 break;
6237 case 2:
6238 if ((i.tm.base_opcode & 0xff0000) != 0)
6239 {
6240 prefix = (i.tm.base_opcode >> 16) & 0xff;
6241 if (i.tm.cpu_flags.bitfield.cpupadlock)
6242 {
4dffcebc 6243check_prefix:
c0f3af97 6244 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6245 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6246 != REPE_PREFIX_OPCODE))
6247 add_prefix (prefix);
6248 }
6249 else
4dffcebc
L		 6250 add_prefix (prefix);
6251 }
c0f3af97
L		 6252 break;
6253 case 1:
6254 break;
6255 default:
6256 abort ();
bc4bd9ab 6257 }
c0f3af97
L		 6258
6259 /* The prefix bytes. */
6260 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
6261 if (*q)
6262 FRAG_APPEND_1_CHAR (*q);
0f10071e 6263 }
ae5c1c7b 6264 else
c0f3af97
L		 6265 {
6266 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
6267 if (*q)
6268 switch (j)
6269 {
6270 case REX_PREFIX:
6271 /* REX byte is encoded in VEX prefix. */
6272 break;
6273 case SEG_PREFIX:
6274 case ADDR_PREFIX:
6275 FRAG_APPEND_1_CHAR (*q);
6276 break;
6277 default:
6278 /* There should be no other prefixes for instructions
6279 with VEX prefix. */
6280 abort ();
6281 }
6282
6283 /* Now the VEX prefix. */
6284 p = frag_more (i.vex.length);
6285 for (j = 0; j < i.vex.length; j++)
6286 p[j] = i.vex.bytes[j];
6287 }
252b5132 6288
29b0f896 6289 /* Now the opcode; be careful about word order here! */
4dffcebc 6290 if (i.tm.opcode_length == 1)
29b0f896
AM		 6291 {
6292 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
6293 }
6294 else
6295 {
4dffcebc 6296 switch (i.tm.opcode_length)
331d2d0d 6297 {
4dffcebc 6298 case 3:
331d2d0d
L		 6299 p = frag_more (3);
6300 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 6301 break;
6302 case 2:
6303 p = frag_more (2);
6304 break;
6305 default:
6306 abort ();
6307 break;
331d2d0d 6308 }
0f10071e 6309
29b0f896
AM		 6310 /* Put out high byte first: can't use md_number_to_chars! */
6311 *p++ = (i.tm.base_opcode >> 8) & 0xff;
6312 *p = i.tm.base_opcode & 0xff;
6313 }
3e73aa7c 6314
29b0f896 6315 /* Now the modrm byte and sib byte (if present). */
40fb9820 6316 if (i.tm.opcode_modifier.modrm)
29b0f896 6317 {
4a3523fa
L		 6318 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
6319 | i.rm.reg << 3
6320 | i.rm.mode << 6));
29b0f896
AM		 6321 /* If i.rm.regmem == ESP (4)
6322 && i.rm.mode != (Register mode)
6323 && not 16 bit
6324 ==> need second modrm byte. */
6325 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
6326 && i.rm.mode != 3
40fb9820 6327 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 6328 FRAG_APPEND_1_CHAR ((i.sib.base << 0
6329 | i.sib.index << 3
6330 | i.sib.scale << 6));
29b0f896 6331 }
3e73aa7c 6332
29b0f896 6333 if (i.disp_operands)
2bbd9c25 6334 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 6335
29b0f896 6336 if (i.imm_operands)
2bbd9c25 6337 output_imm (insn_start_frag, insn_start_off);
29b0f896 6338 }
252b5132 6339
29b0f896
AM		 6340#ifdef DEBUG386
6341 if (flag_debug)
6342 {
7b81dfbb 6343 pi ("" /*line*/, &i);
29b0f896
AM		 6344 }
6345#endif /* DEBUG386 */
6346}
252b5132 6347
e205caa7
L		 6348/* Return the size of the displacement operand N. */
6349
6350static int
6351disp_size (unsigned int n)
6352{
6353 int size = 4;
40fb9820
L		 6354 if (i.types[n].bitfield.disp64)
6355 size = 8;
6356 else if (i.types[n].bitfield.disp8)
6357 size = 1;
6358 else if (i.types[n].bitfield.disp16)
6359 size = 2;
e205caa7
L		 6360 return size;
6361}
6362
6363/* Return the size of the immediate operand N. */
6364
6365static int
6366imm_size (unsigned int n)
6367{
6368 int size = 4;
40fb9820
L		 6369 if (i.types[n].bitfield.imm64)
6370 size = 8;
6371 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
6372 size = 1;
6373 else if (i.types[n].bitfield.imm16)
6374 size = 2;
e205caa7
L		 6375 return size;
6376}
6377
29b0f896 6378static void
64e74474 6379output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6380{
6381 char *p;
6382 unsigned int n;
252b5132 6383
29b0f896
AM		 6384 for (n = 0; n < i.operands; n++)
6385 {
40fb9820 6386 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 6387 {
6388 if (i.op[n].disps->X_op == O_constant)
6389 {
e205caa7 6390 int size = disp_size (n);
29b0f896 6391 offsetT val;
252b5132 6392
29b0f896
AM		 6393 val = offset_in_range (i.op[n].disps->X_add_number,
6394 size);
6395 p = frag_more (size);
6396 md_number_to_chars (p, val, size);
6397 }
6398 else
6399 {
f86103b7 6400 enum bfd_reloc_code_real reloc_type;
e205caa7 6401 int size = disp_size (n);
40fb9820 6402 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 6403 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6404
e205caa7 6405 /* We can't have 8 bit displacement here. */
9c2799c2 6406 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 6407
29b0f896
AM		 6408 /* The PC relative address is computed relative
6409 to the instruction boundary, so in case immediate
6410 fields follows, we need to adjust the value. */
6411 if (pcrel && i.imm_operands)
6412 {
29b0f896 6413 unsigned int n1;
e205caa7 6414 int sz = 0;
252b5132 6415
29b0f896 6416 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 6417 if (operand_type_check (i.types[n1], imm))
252b5132 6418 {
e205caa7
L		 6419 /* Only one immediate is allowed for PC
6420 relative address. */
9c2799c2 6421 gas_assert (sz == 0);
e205caa7
L		 6422 sz = imm_size (n1);
6423 i.op[n].disps->X_add_number -= sz;
252b5132 6424 }
29b0f896 6425 /* We should find the immediate. */
9c2799c2 6426 gas_assert (sz != 0);
29b0f896 6427 }
520dc8e8 6428
29b0f896 6429 p = frag_more (size);
2bbd9c25 6430 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 6431 if (GOT_symbol
2bbd9c25 6432 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 6433 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6434 || reloc_type == BFD_RELOC_X86_64_32S
6435 || (reloc_type == BFD_RELOC_64
6436 && object_64bit))
d6ab8113
JB		 6437 && (i.op[n].disps->X_op == O_symbol
6438 || (i.op[n].disps->X_op == O_add
6439 && ((symbol_get_value_expression
6440 (i.op[n].disps->X_op_symbol)->X_op)
6441 == O_subtract))))
6442 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 6443 {
6444 offsetT add;
6445
6446 if (insn_start_frag == frag_now)
6447 add = (p - frag_now->fr_literal) - insn_start_off;
6448 else
6449 {
6450 fragS *fr;
6451
6452 add = insn_start_frag->fr_fix - insn_start_off;
6453 for (fr = insn_start_frag->fr_next;
6454 fr && fr != frag_now; fr = fr->fr_next)
6455 add += fr->fr_fix;
6456 add += p - frag_now->fr_literal;
6457 }
6458
4fa24527 6459 if (!object_64bit)
7b81dfbb
AJ		 6460 {
6461 reloc_type = BFD_RELOC_386_GOTPC;
6462 i.op[n].imms->X_add_number += add;
6463 }
6464 else if (reloc_type == BFD_RELOC_64)
6465 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 6466 else
7b81dfbb
AJ		 6467 /* Don't do the adjustment for x86-64, as there
6468 the pcrel addressing is relative to the _next_
6469 insn, and that is taken care of in other code. */
d6ab8113 6470 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 6471 }
062cd5e7 6472 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 6473 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 6474 }
6475 }
6476 }
6477}
252b5132 6478
29b0f896 6479static void
64e74474 6480output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6481{
6482 char *p;
6483 unsigned int n;
252b5132 6484
29b0f896
AM		 6485 for (n = 0; n < i.operands; n++)
6486 {
40fb9820 6487 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 6488 {
6489 if (i.op[n].imms->X_op == O_constant)
6490 {
e205caa7 6491 int size = imm_size (n);
29b0f896 6492 offsetT val;
b4cac588 6493
29b0f896
AM		 6494 val = offset_in_range (i.op[n].imms->X_add_number,
6495 size);
6496 p = frag_more (size);
6497 md_number_to_chars (p, val, size);
6498 }
6499 else
6500 {
6501 /* Not absolute_section.
6502 Need a 32-bit fixup (don't support 8bit
6503 non-absolute imms). Try to support other
6504 sizes ... */
f86103b7 6505 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 6506 int size = imm_size (n);
6507 int sign;
29b0f896 6508
40fb9820 6509 if (i.types[n].bitfield.imm32s
a7d61044 6510 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6511 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6512 sign = 1;
e205caa7
L		 6513 else
6514 sign = 0;
520dc8e8 6515
29b0f896
AM		 6516 p = frag_more (size);
6517 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6518
2bbd9c25
JJ		 6519 /* This is tough to explain. We end up with this one if we
6520 * have operands that look like
6521 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6522 * obtain the absolute address of the GOT, and it is strongly
6523 * preferable from a performance point of view to avoid using
6524 * a runtime relocation for this. The actual sequence of
6525 * instructions often look something like:
6526 *
6527 * call .L66
6528 * .L66:
6529 * popl %ebx
6530 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6531 *
6532 * The call and pop essentially return the absolute address
6533 * of the label .L66 and store it in %ebx. The linker itself
6534 * will ultimately change the first operand of the addl so
6535 * that %ebx points to the GOT, but to keep things simple, the
6536 * .o file must have this operand set so that it generates not
6537 * the absolute address of .L66, but the absolute address of
6538 * itself. This allows the linker itself simply treat a GOTPC
6539 * relocation as asking for a pcrel offset to the GOT to be
6540 * added in, and the addend of the relocation is stored in the
6541 * operand field for the instruction itself.
6542 *
6543 * Our job here is to fix the operand so that it would add
6544 * the correct offset so that %ebx would point to itself. The
6545 * thing that is tricky is that .-.L66 will point to the
6546 * beginning of the instruction, so we need to further modify
6547 * the operand so that it will point to itself. There are
6548 * other cases where you have something like:
6549 *
6550 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6551 *
6552 * and here no correction would be required. Internally in
6553 * the assembler we treat operands of this form as not being
6554 * pcrel since the '.' is explicitly mentioned, and I wonder
6555 * whether it would simplify matters to do it this way. Who
6556 * knows. In earlier versions of the PIC patches, the
6557 * pcrel_adjust field was used to store the correction, but
6558 * since the expression is not pcrel, I felt it would be
6559 * confusing to do it this way. */
6560
d6ab8113 6561 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6562 || reloc_type == BFD_RELOC_X86_64_32S
6563 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6564 && GOT_symbol
6565 && GOT_symbol == i.op[n].imms->X_add_symbol
6566 && (i.op[n].imms->X_op == O_symbol
6567 || (i.op[n].imms->X_op == O_add
6568 && ((symbol_get_value_expression
6569 (i.op[n].imms->X_op_symbol)->X_op)
6570 == O_subtract))))
6571 {
2bbd9c25
JJ		 6572 offsetT add;
6573
6574 if (insn_start_frag == frag_now)
6575 add = (p - frag_now->fr_literal) - insn_start_off;
6576 else
6577 {
6578 fragS *fr;
6579
6580 add = insn_start_frag->fr_fix - insn_start_off;
6581 for (fr = insn_start_frag->fr_next;
6582 fr && fr != frag_now; fr = fr->fr_next)
6583 add += fr->fr_fix;
6584 add += p - frag_now->fr_literal;
6585 }
6586
4fa24527 6587 if (!object_64bit)
d6ab8113 6588 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6589 else if (size == 4)
d6ab8113 6590 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6591 else if (size == 8)
6592 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6593 i.op[n].imms->X_add_number += add;
29b0f896 6594 }
29b0f896
AM		 6595 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6596 i.op[n].imms, 0, reloc_type);
6597 }
6598 }
6599 }
252b5132
RH		 6600}
6601\f
d182319b
JB		 6602/* x86_cons_fix_new is called via the expression parsing code when a
6603 reloc is needed. We use this hook to get the correct .got reloc. */
6604static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6605static int cons_sign = -1;
6606
6607void
e3bb37b5 6608x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6609 expressionS *exp)
d182319b
JB		 6610{
6611 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6612
6613 got_reloc = NO_RELOC;
6614
6615#ifdef TE_PE
6616 if (exp->X_op == O_secrel)
6617 {
6618 exp->X_op = O_symbol;
6619 r = BFD_RELOC_32_SECREL;
6620 }
6621#endif
6622
6623 fix_new_exp (frag, off, len, exp, 0, r);
6624}
6625
357d1bd8
L		 6626/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
6627 purpose of the `.dc.a' internal pseudo-op. */
6628
6629int
6630x86_address_bytes (void)
6631{
6632 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
6633 return 4;
6634 return stdoutput->arch_info->bits_per_address / 8;
6635}
6636
d382c579
TG		 6637#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
6638 || defined (LEX_AT)
718ddfc0
JB		 6639# define lex_got(reloc, adjust, types) NULL
6640#else
f3c180ae
AM		 6641/* Parse operands of the form
6642 <symbol>@GOTOFF+<nnn>
6643 and similar .plt or .got references.
6644
6645 If we find one, set up the correct relocation in RELOC and copy the
6646 input string, minus the `@GOTOFF' into a malloc'd buffer for
6647 parsing by the calling routine. Return this buffer, and if ADJUST
6648 is non-null set it to the length of the string we removed from the
6649 input line. Otherwise return NULL. */
6650static char *
91d6fa6a 6651lex_got (enum bfd_reloc_code_real *rel,
64e74474 6652 int *adjust,
40fb9820 6653 i386_operand_type *types)
f3c180ae 6654{
7b81dfbb
AJ		 6655 /* Some of the relocations depend on the size of what field is to
6656 be relocated. But in our callers i386_immediate and i386_displacement
6657 we don't yet know the operand size (this will be set by insn
6658 matching). Hence we record the word32 relocation here,
6659 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6660 static const struct {
6661 const char *str;
cff8d58a 6662 int len;
4fa24527 6663 const enum bfd_reloc_code_real rel[2];
40fb9820 6664 const i386_operand_type types64;
f3c180ae 6665 } gotrel[] = {
cff8d58a
L		 6666 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
6667 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6668 OPERAND_TYPE_IMM64 },
cff8d58a
L		 6669 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
6670 BFD_RELOC_X86_64_PLT32 },
40fb9820 6671 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6672 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
6673 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6674 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6675 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
6676 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6677 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6678 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
6679 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6680 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6681 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
6682 BFD_RELOC_X86_64_TLSGD },
40fb9820 6683 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6684 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
6685 _dummy_first_bfd_reloc_code_real },
40fb9820 6686 OPERAND_TYPE_NONE },
cff8d58a
L		 6687 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
6688 BFD_RELOC_X86_64_TLSLD },
40fb9820 6689 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6690 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
6691 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6692 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6693 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
6694 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6695 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6696 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
6697 _dummy_first_bfd_reloc_code_real },
40fb9820 6698 OPERAND_TYPE_NONE },
cff8d58a
L		 6699 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
6700 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 6701 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6702 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
6703 _dummy_first_bfd_reloc_code_real },
40fb9820 6704 OPERAND_TYPE_NONE },
cff8d58a
L		 6705 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
6706 _dummy_first_bfd_reloc_code_real },
40fb9820 6707 OPERAND_TYPE_NONE },
cff8d58a
L		 6708 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
6709 BFD_RELOC_X86_64_GOT32 },
40fb9820 6710 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 6711 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
6712 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6713 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6714 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
6715 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6716 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6717 };
6718 char *cp;
6719 unsigned int j;
6720
d382c579 6721#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 6722 if (!IS_ELF)
6723 return NULL;
d382c579 6724#endif
718ddfc0 6725
f3c180ae 6726 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6727 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6728 return NULL;
6729
47465058 6730 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 6731 {
cff8d58a 6732 int len = gotrel[j].len;
28f81592 6733 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6734 {
4fa24527 6735 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6736 {
28f81592
AM		 6737 int first, second;
6738 char *tmpbuf, *past_reloc;
f3c180ae 6739
91d6fa6a 6740 *rel = gotrel[j].rel[object_64bit];
28f81592
AM		 6741 if (adjust)
6742 *adjust = len;
f3c180ae 6743
3956db08
JB		 6744 if (types)
6745 {
6746 if (flag_code != CODE_64BIT)
40fb9820
L		 6747 {
6748 types->bitfield.imm32 = 1;
6749 types->bitfield.disp32 = 1;
6750 }
3956db08
JB		 6751 else
6752 *types = gotrel[j].types64;
6753 }
6754
f3c180ae
AM		 6755 if (GOT_symbol == NULL)
6756 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6757
28f81592 6758 /* The length of the first part of our input line. */
f3c180ae 6759 first = cp - input_line_pointer;
28f81592
AM		 6760
6761 /* The second part goes from after the reloc token until
67c11a9b 6762 (and including) an end_of_line char or comma. */
28f81592 6763 past_reloc = cp + 1 + len;
67c11a9b
AM		 6764 cp = past_reloc;
6765 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6766 ++cp;
6767 second = cp + 1 - past_reloc;
28f81592
AM		 6768
6769 /* Allocate and copy string. The trailing NUL shouldn't
6770 be necessary, but be safe. */
1e9cc1c2 6771 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 6772 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6773 if (second != 0 && *past_reloc != ' ')
6774 /* Replace the relocation token with ' ', so that
6775 errors like foo@GOTOFF1 will be detected. */
6776 tmpbuf[first++] = ' ';
6777 memcpy (tmpbuf + first, past_reloc, second);
6778 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6779 return tmpbuf;
6780 }
6781
4fa24527
JB		 6782 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6783 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6784 return NULL;
6785 }
6786 }
6787
6788 /* Might be a symbol version string. Don't as_bad here. */
6789 return NULL;
6790}
4e4f7c87 6791#endif
f3c180ae 6792
a988325c
NC		 6793#ifdef TE_PE
6794#ifdef lex_got
6795#undef lex_got
6796#endif
6797/* Parse operands of the form
6798 <symbol>@SECREL32+<nnn>
6799
6800 If we find one, set up the correct relocation in RELOC and copy the
6801 input string, minus the `@SECREL32' into a malloc'd buffer for
6802 parsing by the calling routine. Return this buffer, and if ADJUST
6803 is non-null set it to the length of the string we removed from the
6804 input line. Otherwise return NULL.
6805
6806 This function is copied from the ELF version above adjusted for PE targets. */
6807
6808static char *
6809lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
6810 int *adjust ATTRIBUTE_UNUSED,
6811 i386_operand_type *types ATTRIBUTE_UNUSED)
6812{
6813 static const struct
6814 {
6815 const char *str;
6816 int len;
6817 const enum bfd_reloc_code_real rel[2];
6818 const i386_operand_type types64;
6819 }
6820 gotrel[] =
6821 {
6822 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
6823 BFD_RELOC_32_SECREL },
6824 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
6825 };
6826
6827 char *cp;
6828 unsigned j;
6829
6830 for (cp = input_line_pointer; *cp != '@'; cp++)
6831 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
6832 return NULL;
6833
6834 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
6835 {
6836 int len = gotrel[j].len;
6837
6838 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
6839 {
6840 if (gotrel[j].rel[object_64bit] != 0)
6841 {
6842 int first, second;
6843 char *tmpbuf, *past_reloc;
6844
6845 *rel = gotrel[j].rel[object_64bit];
6846 if (adjust)
6847 *adjust = len;
6848
6849 if (types)
6850 {
6851 if (flag_code != CODE_64BIT)
6852 {
6853 types->bitfield.imm32 = 1;
6854 types->bitfield.disp32 = 1;
6855 }
6856 else
6857 *types = gotrel[j].types64;
6858 }
6859
6860 /* The length of the first part of our input line. */
6861 first = cp - input_line_pointer;
6862
6863 /* The second part goes from after the reloc token until
6864 (and including) an end_of_line char or comma. */
6865 past_reloc = cp + 1 + len;
6866 cp = past_reloc;
6867 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6868 ++cp;
6869 second = cp + 1 - past_reloc;
6870
6871 /* Allocate and copy string. The trailing NUL shouldn't
6872 be necessary, but be safe. */
6873 tmpbuf = (char *) xmalloc (first + second + 2);
6874 memcpy (tmpbuf, input_line_pointer, first);
6875 if (second != 0 && *past_reloc != ' ')
6876 /* Replace the relocation token with ' ', so that
6877 errors like foo@SECLREL321 will be detected. */
6878 tmpbuf[first++] = ' ';
6879 memcpy (tmpbuf + first, past_reloc, second);
6880 tmpbuf[first + second] = '\0';
6881 return tmpbuf;
6882 }
6883
6884 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6885 gotrel[j].str, 1 << (5 + object_64bit));
6886 return NULL;
6887 }
6888 }
6889
6890 /* Might be a symbol version string. Don't as_bad here. */
6891 return NULL;
6892}
6893
6894#endif /* TE_PE */
6895
f3c180ae 6896void
e3bb37b5 6897x86_cons (expressionS *exp, int size)
f3c180ae 6898{
ee86248c
JB		 6899 intel_syntax = -intel_syntax;
6900
3c7b9c2c 6901 exp->X_md = 0;
4fa24527 6902 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6903 {
6904 /* Handle @GOTOFF and the like in an expression. */
6905 char *save;
6906 char *gotfree_input_line;
4a57f2cf 6907 int adjust = 0;
f3c180ae
AM		 6908
6909 save = input_line_pointer;
3956db08 6910 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6911 if (gotfree_input_line)
6912 input_line_pointer = gotfree_input_line;
6913
6914 expression (exp);
6915
6916 if (gotfree_input_line)
6917 {
6918 /* expression () has merrily parsed up to the end of line,
6919 or a comma - in the wrong buffer. Transfer how far
6920 input_line_pointer has moved to the right buffer. */
6921 input_line_pointer = (save
6922 + (input_line_pointer - gotfree_input_line)
6923 + adjust);
6924 free (gotfree_input_line);
3992d3b7
AM		 6925 if (exp->X_op == O_constant
6926 || exp->X_op == O_absent
6927 || exp->X_op == O_illegal
0398aac5 6928 || exp->X_op == O_register
3992d3b7
AM		 6929 || exp->X_op == O_big)
6930 {
6931 char c = *input_line_pointer;
6932 *input_line_pointer = 0;
6933 as_bad (_("missing or invalid expression `%s'"), save);
6934 *input_line_pointer = c;
6935 }
f3c180ae
AM		 6936 }
6937 }
6938 else
6939 expression (exp);
ee86248c
JB		 6940
6941 intel_syntax = -intel_syntax;
6942
6943 if (intel_syntax)
6944 i386_intel_simplify (exp);
f3c180ae 6945}
f3c180ae 6946
9f32dd5b
L		 6947static void
6948signed_cons (int size)
6482c264 6949{
d182319b
JB		 6950 if (flag_code == CODE_64BIT)
6951 cons_sign = 1;
6952 cons (size);
6953 cons_sign = -1;
6482c264
NC		 6954}
6955
d182319b 6956#ifdef TE_PE
6482c264 6957static void
7016a5d5 6958pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 6959{
6960 expressionS exp;
6961
6962 do
6963 {
6964 expression (&exp);
6965 if (exp.X_op == O_symbol)
6966 exp.X_op = O_secrel;
6967
6968 emit_expr (&exp, 4);
6969 }
6970 while (*input_line_pointer++ == ',');
6971
6972 input_line_pointer--;
6973 demand_empty_rest_of_line ();
6974}
6482c264
NC		 6975#endif
6976
252b5132 6977static int
70e41ade 6978i386_immediate (char *imm_start)
252b5132
RH		 6979{
6980 char *save_input_line_pointer;
f3c180ae 6981 char *gotfree_input_line;
252b5132 6982 segT exp_seg = 0;
47926f60 6983 expressionS *exp;
40fb9820
L		 6984 i386_operand_type types;
6985
0dfbf9d7 6986 operand_type_set (&types, ~0);
252b5132
RH		 6987
6988 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6989 {
31b2323c
L		 6990 as_bad (_("at most %d immediate operands are allowed"),
6991 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6992 return 0;
6993 }
6994
6995 exp = &im_expressions[i.imm_operands++];
520dc8e8 6996 i.op[this_operand].imms = exp;
252b5132
RH		 6997
6998 if (is_space_char (*imm_start))
6999 ++imm_start;
7000
7001 save_input_line_pointer = input_line_pointer;
7002 input_line_pointer = imm_start;
7003
3956db08 7004 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 7005 if (gotfree_input_line)
7006 input_line_pointer = gotfree_input_line;
252b5132
RH		 7007
7008 exp_seg = expression (exp);
7009
83183c0c 7010 SKIP_WHITESPACE ();
252b5132 7011 if (*input_line_pointer)
f3c180ae 7012 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 7013
7014 input_line_pointer = save_input_line_pointer;
f3c180ae 7015 if (gotfree_input_line)
ee86248c
JB		 7016 {
7017 free (gotfree_input_line);
7018
7019 if (exp->X_op == O_constant || exp->X_op == O_register)
7020 exp->X_op = O_illegal;
7021 }
7022
7023 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7024}
252b5132 7025
ee86248c
JB		 7026static int
7027i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7028 i386_operand_type types, const char *imm_start)
7029{
7030 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 7031 {
313c53d1
L		 7032 if (imm_start)
7033 as_bad (_("missing or invalid immediate expression `%s'"),
7034 imm_start);
3992d3b7 7035 return 0;
252b5132 7036 }
3e73aa7c 7037 else if (exp->X_op == O_constant)
252b5132 7038 {
47926f60 7039 /* Size it properly later. */
40fb9820 7040 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 7041 /* If not 64bit, sign extend val. */
7042 if (flag_code != CODE_64BIT
4eed87de
AM		 7043 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7044 exp->X_add_number
7045 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 7046 }
4c63da97 7047#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 7048 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 7049 && exp_seg != absolute_section
47926f60 7050 && exp_seg != text_section
24eab124
AM		 7051 && exp_seg != data_section
7052 && exp_seg != bss_section
7053 && exp_seg != undefined_section
f86103b7 7054 && !bfd_is_com_section (exp_seg))
252b5132 7055 {
d0b47220 7056 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 7057 return 0;
7058 }
7059#endif
bb8f5920
L		 7060 else if (!intel_syntax && exp->X_op == O_register)
7061 {
313c53d1
L		 7062 if (imm_start)
7063 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 7064 return 0;
7065 }
252b5132
RH		 7066 else
7067 {
7068 /* This is an address. The size of the address will be
24eab124 7069 determined later, depending on destination register,
3e73aa7c 7070 suffix, or the default for the section. */
40fb9820
L		 7071 i.types[this_operand].bitfield.imm8 = 1;
7072 i.types[this_operand].bitfield.imm16 = 1;
7073 i.types[this_operand].bitfield.imm32 = 1;
7074 i.types[this_operand].bitfield.imm32s = 1;
7075 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 7076 i.types[this_operand] = operand_type_and (i.types[this_operand],
7077 types);
252b5132
RH		 7078 }
7079
7080 return 1;
7081}
7082
551c1ca1 7083static char *
e3bb37b5 7084i386_scale (char *scale)
252b5132 7085{
551c1ca1
AM		 7086 offsetT val;
7087 char *save = input_line_pointer;
252b5132 7088
551c1ca1
AM		 7089 input_line_pointer = scale;
7090 val = get_absolute_expression ();
7091
7092 switch (val)
252b5132 7093 {
551c1ca1 7094 case 1:
252b5132
RH		 7095 i.log2_scale_factor = 0;
7096 break;
551c1ca1 7097 case 2:
252b5132
RH		 7098 i.log2_scale_factor = 1;
7099 break;
551c1ca1 7100 case 4:
252b5132
RH		 7101 i.log2_scale_factor = 2;
7102 break;
551c1ca1 7103 case 8:
252b5132
RH		 7104 i.log2_scale_factor = 3;
7105 break;
7106 default:
a724f0f4
JB		 7107 {
7108 char sep = *input_line_pointer;
7109
7110 *input_line_pointer = '\0';
7111 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
7112 scale);
7113 *input_line_pointer = sep;
7114 input_line_pointer = save;
7115 return NULL;
7116 }
252b5132 7117 }
29b0f896 7118 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 7119 {
7120 as_warn (_("scale factor of %d without an index register"),
24eab124 7121 1 << i.log2_scale_factor);
252b5132 7122 i.log2_scale_factor = 0;
252b5132 7123 }
551c1ca1
AM		 7124 scale = input_line_pointer;
7125 input_line_pointer = save;
7126 return scale;
252b5132
RH		 7127}
7128
252b5132 7129static int
e3bb37b5 7130i386_displacement (char *disp_start, char *disp_end)
252b5132 7131{
29b0f896 7132 expressionS *exp;
252b5132
RH		 7133 segT exp_seg = 0;
7134 char *save_input_line_pointer;
f3c180ae 7135 char *gotfree_input_line;
40fb9820
L		 7136 int override;
7137 i386_operand_type bigdisp, types = anydisp;
3992d3b7 7138 int ret;
252b5132 7139
31b2323c
L		 7140 if (i.disp_operands == MAX_MEMORY_OPERANDS)
7141 {
7142 as_bad (_("at most %d displacement operands are allowed"),
7143 MAX_MEMORY_OPERANDS);
7144 return 0;
7145 }
7146
0dfbf9d7 7147 operand_type_set (&bigdisp, 0);
40fb9820
L		 7148 if ((i.types[this_operand].bitfield.jumpabsolute)
7149 || (!current_templates->start->opcode_modifier.jump
7150 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 7151 {
40fb9820 7152 bigdisp.bitfield.disp32 = 1;
e05278af 7153 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 7154 if (flag_code == CODE_64BIT)
7155 {
7156 if (!override)
7157 {
7158 bigdisp.bitfield.disp32s = 1;
7159 bigdisp.bitfield.disp64 = 1;
7160 }
7161 }
7162 else if ((flag_code == CODE_16BIT) ^ override)
7163 {
7164 bigdisp.bitfield.disp32 = 0;
7165 bigdisp.bitfield.disp16 = 1;
7166 }
e05278af
JB		 7167 }
7168 else
7169 {
7170 /* For PC-relative branches, the width of the displacement
7171 is dependent upon data size, not address size. */
e05278af 7172 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 7173 if (flag_code == CODE_64BIT)
7174 {
7175 if (override || i.suffix == WORD_MNEM_SUFFIX)
7176 bigdisp.bitfield.disp16 = 1;
7177 else
7178 {
7179 bigdisp.bitfield.disp32 = 1;
7180 bigdisp.bitfield.disp32s = 1;
7181 }
7182 }
7183 else
e05278af
JB		 7184 {
7185 if (!override)
7186 override = (i.suffix == (flag_code != CODE_16BIT
7187 ? WORD_MNEM_SUFFIX
7188 : LONG_MNEM_SUFFIX));
40fb9820
L		 7189 bigdisp.bitfield.disp32 = 1;
7190 if ((flag_code == CODE_16BIT) ^ override)
7191 {
7192 bigdisp.bitfield.disp32 = 0;
7193 bigdisp.bitfield.disp16 = 1;
7194 }
e05278af 7195 }
e05278af 7196 }
c6fb90c8
L		 7197 i.types[this_operand] = operand_type_or (i.types[this_operand],
7198 bigdisp);
252b5132
RH		 7199
7200 exp = &disp_expressions[i.disp_operands];
520dc8e8 7201 i.op[this_operand].disps = exp;
252b5132
RH		 7202 i.disp_operands++;
7203 save_input_line_pointer = input_line_pointer;
7204 input_line_pointer = disp_start;
7205 END_STRING_AND_SAVE (disp_end);
7206
7207#ifndef GCC_ASM_O_HACK
7208#define GCC_ASM_O_HACK 0
7209#endif
7210#if GCC_ASM_O_HACK
7211 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 7212 if (i.types[this_operand].bitfield.baseIndex
24eab124 7213 && displacement_string_end[-1] == '+')
252b5132
RH		 7214 {
7215 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 7216 constraint within gcc asm statements.
7217 For instance:
7218
7219 #define _set_tssldt_desc(n,addr,limit,type) \
7220 __asm__ __volatile__ ( \
7221 "movw %w2,%0\n\t" \
7222 "movw %w1,2+%0\n\t" \
7223 "rorl $16,%1\n\t" \
7224 "movb %b1,4+%0\n\t" \
7225 "movb %4,5+%0\n\t" \
7226 "movb $0,6+%0\n\t" \
7227 "movb %h1,7+%0\n\t" \
7228 "rorl $16,%1" \
7229 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
7230
7231 This works great except that the output assembler ends
7232 up looking a bit weird if it turns out that there is
7233 no offset. You end up producing code that looks like:
7234
7235 #APP
7236 movw $235,(%eax)
7237 movw %dx,2+(%eax)
7238 rorl $16,%edx
7239 movb %dl,4+(%eax)
7240 movb $137,5+(%eax)
7241 movb $0,6+(%eax)
7242 movb %dh,7+(%eax)
7243 rorl $16,%edx
7244 #NO_APP
7245
47926f60 7246 So here we provide the missing zero. */
24eab124
AM		 7247
7248 *displacement_string_end = '0';
252b5132
RH		 7249 }
7250#endif
3956db08 7251 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 7252 if (gotfree_input_line)
7253 input_line_pointer = gotfree_input_line;
252b5132 7254
24eab124 7255 exp_seg = expression (exp);
252b5132 7256
636c26b0
AM		 7257 SKIP_WHITESPACE ();
7258 if (*input_line_pointer)
7259 as_bad (_("junk `%s' after expression"), input_line_pointer);
7260#if GCC_ASM_O_HACK
7261 RESTORE_END_STRING (disp_end + 1);
7262#endif
636c26b0 7263 input_line_pointer = save_input_line_pointer;
636c26b0 7264 if (gotfree_input_line)
ee86248c
JB		 7265 {
7266 free (gotfree_input_line);
7267
7268 if (exp->X_op == O_constant || exp->X_op == O_register)
7269 exp->X_op = O_illegal;
7270 }
7271
7272 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
7273
7274 RESTORE_END_STRING (disp_end);
7275
7276 return ret;
7277}
7278
7279static int
7280i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7281 i386_operand_type types, const char *disp_start)
7282{
7283 i386_operand_type bigdisp;
7284 int ret = 1;
636c26b0 7285
24eab124
AM		 7286 /* We do this to make sure that the section symbol is in
7287 the symbol table. We will ultimately change the relocation
47926f60 7288 to be relative to the beginning of the section. */
1ae12ab7 7289 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 7290 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
7291 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 7292 {
636c26b0 7293 if (exp->X_op != O_symbol)
3992d3b7 7294 goto inv_disp;
636c26b0 7295
e5cb08ac 7296 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 7297 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
7298 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 7299 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 7300 exp->X_op = O_subtract;
7301 exp->X_op_symbol = GOT_symbol;
1ae12ab7 7302 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 7303 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 7304 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
7305 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 7306 else
29b0f896 7307 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 7308 }
252b5132 7309
3992d3b7
AM		 7310 else if (exp->X_op == O_absent
7311 || exp->X_op == O_illegal
ee86248c 7312 || exp->X_op == O_big)
2daf4fd8 7313 {
3992d3b7
AM		 7314 inv_disp:
7315 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 7316 disp_start);
3992d3b7 7317 ret = 0;
2daf4fd8
AM		 7318 }
7319
0e1147d9
L		 7320 else if (flag_code == CODE_64BIT
7321 && !i.prefix[ADDR_PREFIX]
7322 && exp->X_op == O_constant)
7323 {
7324 /* Since displacement is signed extended to 64bit, don't allow
7325 disp32 and turn off disp32s if they are out of range. */
7326 i.types[this_operand].bitfield.disp32 = 0;
7327 if (!fits_in_signed_long (exp->X_add_number))
7328 {
7329 i.types[this_operand].bitfield.disp32s = 0;
7330 if (i.types[this_operand].bitfield.baseindex)
7331 {
7332 as_bad (_("0x%lx out range of signed 32bit displacement"),
7333 (long) exp->X_add_number);
7334 ret = 0;
7335 }
7336 }
7337 }
7338
4c63da97 7339#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 7340 else if (exp->X_op != O_constant
7341 && OUTPUT_FLAVOR == bfd_target_aout_flavour
7342 && exp_seg != absolute_section
7343 && exp_seg != text_section
7344 && exp_seg != data_section
7345 && exp_seg != bss_section
7346 && exp_seg != undefined_section
7347 && !bfd_is_com_section (exp_seg))
24eab124 7348 {
d0b47220 7349 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 7350 ret = 0;
24eab124 7351 }
252b5132 7352#endif
3956db08 7353
40fb9820
L		 7354 /* Check if this is a displacement only operand. */
7355 bigdisp = i.types[this_operand];
7356 bigdisp.bitfield.disp8 = 0;
7357 bigdisp.bitfield.disp16 = 0;
7358 bigdisp.bitfield.disp32 = 0;
7359 bigdisp.bitfield.disp32s = 0;
7360 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 7361 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 7362 i.types[this_operand] = operand_type_and (i.types[this_operand],
7363 types);
3956db08 7364
3992d3b7 7365 return ret;
252b5132
RH		 7366}
7367
eecb386c 7368/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 7369 Return 1 on success, 0 on a failure. */
7370
252b5132 7371static int
e3bb37b5 7372i386_index_check (const char *operand_string)
252b5132 7373{
3e73aa7c 7374 int ok;
fc0763e6 7375 const char *kind = "base/index";
24eab124 7376#if INFER_ADDR_PREFIX
eecb386c
AM		 7377 int fudged = 0;
7378
24eab124
AM		 7379 tryprefix:
7380#endif
3e73aa7c 7381 ok = 1;
fc0763e6
JB		 7382 if (current_templates->start->opcode_modifier.isstring
7383 && !current_templates->start->opcode_modifier.immext
7384 && (current_templates->end[-1].opcode_modifier.isstring
7385 || i.mem_operands))
7386 {
7387 /* Memory operands of string insns are special in that they only allow
7388 a single register (rDI, rSI, or rBX) as their memory address. */
7389 unsigned int expected;
7390
7391 kind = "string address";
7392
7393 if (current_templates->start->opcode_modifier.w)
7394 {
7395 i386_operand_type type = current_templates->end[-1].operand_types[0];
7396
7397 if (!type.bitfield.baseindex
7398 || ((!i.mem_operands != !intel_syntax)
7399 && current_templates->end[-1].operand_types[1]
7400 .bitfield.baseindex))
7401 type = current_templates->end[-1].operand_types[1];
7402 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
7403 }
7404 else
7405 expected = 3 /* rBX */;
7406
7407 if (!i.base_reg || i.index_reg
7408 || operand_type_check (i.types[this_operand], disp))
7409 ok = -1;
7410 else if (!(flag_code == CODE_64BIT
7411 ? i.prefix[ADDR_PREFIX]
7412 ? i.base_reg->reg_type.bitfield.reg32
7413 : i.base_reg->reg_type.bitfield.reg64
7414 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7415 ? i.base_reg->reg_type.bitfield.reg32
7416 : i.base_reg->reg_type.bitfield.reg16))
7417 ok = 0;
4c692bc7 7418 else if (register_number (i.base_reg) != expected)
fc0763e6
JB		 7419 ok = -1;
7420
7421 if (ok < 0)
7422 {
7423 unsigned int j;
7424
7425 for (j = 0; j < i386_regtab_size; ++j)
7426 if ((flag_code == CODE_64BIT
7427 ? i.prefix[ADDR_PREFIX]
7428 ? i386_regtab[j].reg_type.bitfield.reg32
7429 : i386_regtab[j].reg_type.bitfield.reg64
7430 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7431 ? i386_regtab[j].reg_type.bitfield.reg32
7432 : i386_regtab[j].reg_type.bitfield.reg16)
4c692bc7 7433 && register_number(i386_regtab + j) == expected)
fc0763e6 7434 break;
9c2799c2 7435 gas_assert (j < i386_regtab_size);
fc0763e6
JB		 7436 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7437 operand_string,
7438 intel_syntax ? '[' : '(',
7439 register_prefix,
7440 i386_regtab[j].reg_name,
7441 intel_syntax ? ']' : ')');
7442 ok = 1;
7443 }
7444 }
7445 else if (flag_code == CODE_64BIT)
64e74474 7446 {
64e74474 7447 if ((i.base_reg
40fb9820
L		 7448 && ((i.prefix[ADDR_PREFIX] == 0
7449 && !i.base_reg->reg_type.bitfield.reg64)
7450 || (i.prefix[ADDR_PREFIX]
7451 && !i.base_reg->reg_type.bitfield.reg32))
7452 && (i.index_reg
9a04903e
JB		 7453 || i.base_reg->reg_num !=
7454 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 7455 || (i.index_reg
6c30d220
L		 7456 && !(i.index_reg->reg_type.bitfield.regxmm
7457 || i.index_reg->reg_type.bitfield.regymm)
40fb9820
L		 7458 && (!i.index_reg->reg_type.bitfield.baseindex
7459 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 7460 && i.index_reg->reg_num != RegRiz
7461 && !i.index_reg->reg_type.bitfield.reg64
7462 )
40fb9820 7463 || (i.prefix[ADDR_PREFIX]
db51cc60 7464 && i.index_reg->reg_num != RegEiz
40fb9820 7465 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 7466 ok = 0;
3e73aa7c
JH		 7467 }
7468 else
7469 {
7470 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
7471 {
7472 /* 16bit checks. */
7473 if ((i.base_reg
40fb9820
L		 7474 && (!i.base_reg->reg_type.bitfield.reg16
7475 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 7476 || (i.index_reg
40fb9820
L		 7477 && (!i.index_reg->reg_type.bitfield.reg16
7478 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 7479 || !(i.base_reg
7480 && i.base_reg->reg_num < 6
7481 && i.index_reg->reg_num >= 6
7482 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 7483 ok = 0;
7484 }
7485 else
e5cb08ac 7486 {
3e73aa7c
JH		 7487 /* 32bit checks. */
7488 if ((i.base_reg
40fb9820 7489 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 7490 || (i.index_reg
6c30d220
L		 7491 && !i.index_reg->reg_type.bitfield.regxmm
7492 && !i.index_reg->reg_type.bitfield.regymm
db51cc60
L		 7493 && ((!i.index_reg->reg_type.bitfield.reg32
7494 && i.index_reg->reg_num != RegEiz)
40fb9820 7495 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 7496 ok = 0;
3e73aa7c
JH		 7497 }
7498 }
7499 if (!ok)
24eab124
AM		 7500 {
7501#if INFER_ADDR_PREFIX
fc0763e6 7502 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 7503 {
7504 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
7505 i.prefixes += 1;
b23bac36
AM		 7506 /* Change the size of any displacement too. At most one of
7507 Disp16 or Disp32 is set.
7508 FIXME. There doesn't seem to be any real need for separate
7509 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 7510 Removing them would probably clean up the code quite a lot. */
4eed87de 7511 if (flag_code != CODE_64BIT
40fb9820
L		 7512 && (i.types[this_operand].bitfield.disp16
7513 || i.types[this_operand].bitfield.disp32))
7514 i.types[this_operand]
c6fb90c8 7515 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 7516 fudged = 1;
24eab124
AM		 7517 goto tryprefix;
7518 }
eecb386c 7519 if (fudged)
fc0763e6
JB		 7520 as_bad (_("`%s' is not a valid %s expression"),
7521 operand_string,
7522 kind);
eecb386c 7523 else
c388dee8 7524#endif
fc0763e6 7525 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 7526 operand_string,
fc0763e6
JB		 7527 flag_code_names[i.prefix[ADDR_PREFIX]
7528 ? flag_code == CODE_32BIT
7529 ? CODE_16BIT
7530 : CODE_32BIT
7531 : flag_code],
7532 kind);
24eab124 7533 }
20f0a1fc 7534 return ok;
24eab124 7535}
252b5132 7536
fc0763e6 7537/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 7538 on error. */
252b5132 7539
252b5132 7540static int
a7619375 7541i386_att_operand (char *operand_string)
252b5132 7542{
af6bdddf
AM		 7543 const reg_entry *r;
7544 char *end_op;
24eab124 7545 char *op_string = operand_string;
252b5132 7546
24eab124 7547 if (is_space_char (*op_string))
252b5132
RH		 7548 ++op_string;
7549
24eab124 7550 /* We check for an absolute prefix (differentiating,
47926f60 7551 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 7552 if (*op_string == ABSOLUTE_PREFIX)
7553 {
7554 ++op_string;
7555 if (is_space_char (*op_string))
7556 ++op_string;
40fb9820 7557 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 7558 }
252b5132 7559
47926f60 7560 /* Check if operand is a register. */
4d1bb795 7561 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 7562 {
40fb9820
L		 7563 i386_operand_type temp;
7564
24eab124
AM		 7565 /* Check for a segment override by searching for ':' after a
7566 segment register. */
7567 op_string = end_op;
7568 if (is_space_char (*op_string))
7569 ++op_string;
40fb9820
L		 7570 if (*op_string == ':'
7571 && (r->reg_type.bitfield.sreg2
7572 || r->reg_type.bitfield.sreg3))
24eab124
AM		 7573 {
7574 switch (r->reg_num)
7575 {
7576 case 0:
7577 i.seg[i.mem_operands] = &es;
7578 break;
7579 case 1:
7580 i.seg[i.mem_operands] = &cs;
7581 break;
7582 case 2:
7583 i.seg[i.mem_operands] = &ss;
7584 break;
7585 case 3:
7586 i.seg[i.mem_operands] = &ds;
7587 break;
7588 case 4:
7589 i.seg[i.mem_operands] = &fs;
7590 break;
7591 case 5:
7592 i.seg[i.mem_operands] = &gs;
7593 break;
7594 }
252b5132 7595
24eab124 7596 /* Skip the ':' and whitespace. */
252b5132
RH		 7597 ++op_string;
7598 if (is_space_char (*op_string))
24eab124 7599 ++op_string;
252b5132 7600
24eab124
AM		 7601 if (!is_digit_char (*op_string)
7602 && !is_identifier_char (*op_string)
7603 && *op_string != '('
7604 && *op_string != ABSOLUTE_PREFIX)
7605 {
7606 as_bad (_("bad memory operand `%s'"), op_string);
7607 return 0;
7608 }
47926f60 7609 /* Handle case of %es:*foo. */
24eab124
AM		 7610 if (*op_string == ABSOLUTE_PREFIX)
7611 {
7612 ++op_string;
7613 if (is_space_char (*op_string))
7614 ++op_string;
40fb9820 7615 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 7616 }
7617 goto do_memory_reference;
7618 }
7619 if (*op_string)
7620 {
d0b47220 7621 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 7622 return 0;
7623 }
40fb9820
L		 7624 temp = r->reg_type;
7625 temp.bitfield.baseindex = 0;
c6fb90c8
L		 7626 i.types[this_operand] = operand_type_or (i.types[this_operand],
7627 temp);
7d5e4556 7628 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 7629 i.op[this_operand].regs = r;
24eab124
AM		 7630 i.reg_operands++;
7631 }
af6bdddf
AM		 7632 else if (*op_string == REGISTER_PREFIX)
7633 {
7634 as_bad (_("bad register name `%s'"), op_string);
7635 return 0;
7636 }
24eab124 7637 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7638 {
24eab124 7639 ++op_string;
40fb9820 7640 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7641 {
d0b47220 7642 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7643 return 0;
7644 }
7645 if (!i386_immediate (op_string))
7646 return 0;
7647 }
7648 else if (is_digit_char (*op_string)
7649 || is_identifier_char (*op_string)
e5cb08ac 7650 || *op_string == '(')
24eab124 7651 {
47926f60 7652 /* This is a memory reference of some sort. */
af6bdddf 7653 char *base_string;
252b5132 7654
47926f60 7655 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7656 char *displacement_string_start;
7657 char *displacement_string_end;
252b5132 7658
24eab124 7659 do_memory_reference:
24eab124 7660 if ((i.mem_operands == 1
40fb9820 7661 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7662 || i.mem_operands == 2)
7663 {
7664 as_bad (_("too many memory references for `%s'"),
7665 current_templates->start->name);
7666 return 0;
7667 }
252b5132 7668
24eab124
AM		 7669 /* Check for base index form. We detect the base index form by
7670 looking for an ')' at the end of the operand, searching
7671 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7672 after the '('. */
af6bdddf 7673 base_string = op_string + strlen (op_string);
c3332e24 7674
af6bdddf
AM		 7675 --base_string;
7676 if (is_space_char (*base_string))
7677 --base_string;
252b5132 7678
47926f60 7679 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7680 displacement_string_start = op_string;
7681 displacement_string_end = base_string + 1;
252b5132 7682
24eab124
AM		 7683 if (*base_string == ')')
7684 {
af6bdddf 7685 char *temp_string;
24eab124
AM		 7686 unsigned int parens_balanced = 1;
7687 /* We've already checked that the number of left & right ()'s are
47926f60 7688 equal, so this loop will not be infinite. */
24eab124
AM		 7689 do
7690 {
7691 base_string--;
7692 if (*base_string == ')')
7693 parens_balanced++;
7694 if (*base_string == '(')
7695 parens_balanced--;
7696 }
7697 while (parens_balanced);
c3332e24 7698
af6bdddf 7699 temp_string = base_string;
c3332e24 7700
24eab124 7701 /* Skip past '(' and whitespace. */
252b5132
RH		 7702 ++base_string;
7703 if (is_space_char (*base_string))
24eab124 7704 ++base_string;
252b5132 7705
af6bdddf 7706 if (*base_string == ','
4eed87de
AM		 7707 || ((i.base_reg = parse_register (base_string, &end_op))
7708 != NULL))
252b5132 7709 {
af6bdddf 7710 displacement_string_end = temp_string;
252b5132 7711
40fb9820 7712 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7713
af6bdddf 7714 if (i.base_reg)
24eab124 7715 {
24eab124
AM		 7716 base_string = end_op;
7717 if (is_space_char (*base_string))
7718 ++base_string;
af6bdddf
AM		 7719 }
7720
7721 /* There may be an index reg or scale factor here. */
7722 if (*base_string == ',')
7723 {
7724 ++base_string;
7725 if (is_space_char (*base_string))
7726 ++base_string;
7727
4eed87de
AM		 7728 if ((i.index_reg = parse_register (base_string, &end_op))
7729 != NULL)
24eab124 7730 {
af6bdddf 7731 base_string = end_op;
24eab124
AM		 7732 if (is_space_char (*base_string))
7733 ++base_string;
af6bdddf
AM		 7734 if (*base_string == ',')
7735 {
7736 ++base_string;
7737 if (is_space_char (*base_string))
7738 ++base_string;
7739 }
e5cb08ac 7740 else if (*base_string != ')')
af6bdddf 7741 {
4eed87de
AM		 7742 as_bad (_("expecting `,' or `)' "
7743 "after index register in `%s'"),
af6bdddf
AM		 7744 operand_string);
7745 return 0;
7746 }
24eab124 7747 }
af6bdddf 7748 else if (*base_string == REGISTER_PREFIX)
24eab124 7749 {
af6bdddf 7750 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7751 return 0;
7752 }
252b5132 7753
47926f60 7754 /* Check for scale factor. */
551c1ca1 7755 if (*base_string != ')')
af6bdddf 7756 {
551c1ca1
AM		 7757 char *end_scale = i386_scale (base_string);
7758
7759 if (!end_scale)
af6bdddf 7760 return 0;
24eab124 7761
551c1ca1 7762 base_string = end_scale;
af6bdddf
AM		 7763 if (is_space_char (*base_string))
7764 ++base_string;
7765 if (*base_string != ')')
7766 {
4eed87de
AM		 7767 as_bad (_("expecting `)' "
7768 "after scale factor in `%s'"),
af6bdddf
AM		 7769 operand_string);
7770 return 0;
7771 }
7772 }
7773 else if (!i.index_reg)
24eab124 7774 {
4eed87de
AM		 7775 as_bad (_("expecting index register or scale factor "
7776 "after `,'; got '%c'"),
af6bdddf 7777 *base_string);
24eab124
AM		 7778 return 0;
7779 }
7780 }
af6bdddf 7781 else if (*base_string != ')')
24eab124 7782 {
4eed87de
AM		 7783 as_bad (_("expecting `,' or `)' "
7784 "after base register in `%s'"),
af6bdddf 7785 operand_string);
24eab124
AM		 7786 return 0;
7787 }
c3332e24 7788 }
af6bdddf 7789 else if (*base_string == REGISTER_PREFIX)
c3332e24 7790 {
af6bdddf 7791 as_bad (_("bad register name `%s'"), base_string);
24eab124 7792 return 0;
c3332e24 7793 }
24eab124
AM		 7794 }
7795
7796 /* If there's an expression beginning the operand, parse it,
7797 assuming displacement_string_start and
7798 displacement_string_end are meaningful. */
7799 if (displacement_string_start != displacement_string_end)
7800 {
7801 if (!i386_displacement (displacement_string_start,
7802 displacement_string_end))
7803 return 0;
7804 }
7805
7806 /* Special case for (%dx) while doing input/output op. */
7807 if (i.base_reg
0dfbf9d7
L		 7808 && operand_type_equal (&i.base_reg->reg_type,
7809 &reg16_inoutportreg)
24eab124
AM		 7810 && i.index_reg == 0
7811 && i.log2_scale_factor == 0
7812 && i.seg[i.mem_operands] == 0
40fb9820 7813 && !operand_type_check (i.types[this_operand], disp))
24eab124 7814 {
65da13b5 7815 i.types[this_operand] = inoutportreg;
24eab124
AM		 7816 return 1;
7817 }
7818
eecb386c
AM		 7819 if (i386_index_check (operand_string) == 0)
7820 return 0;
5c07affc 7821 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7822 i.mem_operands++;
7823 }
7824 else
ce8a8b2f
AM		 7825 {
7826 /* It's not a memory operand; argh! */
24eab124
AM		 7827 as_bad (_("invalid char %s beginning operand %d `%s'"),
7828 output_invalid (*op_string),
7829 this_operand + 1,
7830 op_string);
7831 return 0;
7832 }
47926f60 7833 return 1; /* Normal return. */
252b5132
RH		 7834}
7835\f
fa94de6b
RM		 7836/* Calculate the maximum variable size (i.e., excluding fr_fix)
7837 that an rs_machine_dependent frag may reach. */
7838
7839unsigned int
7840i386_frag_max_var (fragS *frag)
7841{
7842 /* The only relaxable frags are for jumps.
7843 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
7844 gas_assert (frag->fr_type == rs_machine_dependent);
7845 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
7846}
7847
ee7fcc42
AM		 7848/* md_estimate_size_before_relax()
7849
7850 Called just before relax() for rs_machine_dependent frags. The x86
7851 assembler uses these frags to handle variable size jump
7852 instructions.
7853
7854 Any symbol that is now undefined will not become defined.
7855 Return the correct fr_subtype in the frag.
7856 Return the initial "guess for variable size of frag" to caller.
7857 The guess is actually the growth beyond the fixed part. Whatever
7858 we do to grow the fixed or variable part contributes to our
7859 returned value. */
7860
252b5132 7861int
7016a5d5 7862md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 7863{
252b5132 7864 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7865 check for un-relaxable symbols. On an ELF system, we can't relax
7866 an externally visible symbol, because it may be overridden by a
7867 shared library. */
7868 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7869#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7870 || (IS_ELF
31312f95 7871 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 7872 || S_IS_WEAK (fragP->fr_symbol)
7873 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7874 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 7875#endif
7876#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 7877 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 7878 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 7879#endif
7880 )
252b5132 7881 {
b98ef147
AM		 7882 /* Symbol is undefined in this segment, or we need to keep a
7883 reloc so that weak symbols can be overridden. */
7884 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7885 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7886 unsigned char *opcode;
7887 int old_fr_fix;
f6af82bd 7888
ee7fcc42 7889 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 7890 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 7891 else if (size == 2)
f6af82bd
AM		 7892 reloc_type = BFD_RELOC_16_PCREL;
7893 else
7894 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7895
ee7fcc42
AM		 7896 old_fr_fix = fragP->fr_fix;
7897 opcode = (unsigned char *) fragP->fr_opcode;
7898
fddf5b5b 7899 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7900 {
fddf5b5b
AM		 7901 case UNCOND_JUMP:
7902 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7903 opcode[0] = 0xe9;
252b5132 7904 fragP->fr_fix += size;
062cd5e7
AS		 7905 fix_new (fragP, old_fr_fix, size,
7906 fragP->fr_symbol,
7907 fragP->fr_offset, 1,
7908 reloc_type);
252b5132
RH		 7909 break;
7910
fddf5b5b 7911 case COND_JUMP86:
412167cb
AM		 7912 if (size == 2
7913 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7914 {
7915 /* Negate the condition, and branch past an
7916 unconditional jump. */
7917 opcode[0] ^= 1;
7918 opcode[1] = 3;
7919 /* Insert an unconditional jump. */
7920 opcode[2] = 0xe9;
7921 /* We added two extra opcode bytes, and have a two byte
7922 offset. */
7923 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7924 fix_new (fragP, old_fr_fix + 2, 2,
7925 fragP->fr_symbol,
7926 fragP->fr_offset, 1,
7927 reloc_type);
fddf5b5b
AM		 7928 break;
7929 }
7930 /* Fall through. */
7931
7932 case COND_JUMP:
412167cb
AM		 7933 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7934 {
3e02c1cc
AM		 7935 fixS *fixP;
7936
412167cb 7937 fragP->fr_fix += 1;
3e02c1cc
AM		 7938 fixP = fix_new (fragP, old_fr_fix, 1,
7939 fragP->fr_symbol,
7940 fragP->fr_offset, 1,
7941 BFD_RELOC_8_PCREL);
7942 fixP->fx_signed = 1;
412167cb
AM		 7943 break;
7944 }
93c2a809 7945
24eab124 7946 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7947 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7948 opcode[1] = opcode[0] + 0x10;
f6af82bd 7949 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7950 /* We've added an opcode byte. */
7951 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7952 fix_new (fragP, old_fr_fix + 1, size,
7953 fragP->fr_symbol,
7954 fragP->fr_offset, 1,
7955 reloc_type);
252b5132 7956 break;
fddf5b5b
AM		 7957
7958 default:
7959 BAD_CASE (fragP->fr_subtype);
7960 break;
252b5132
RH		 7961 }
7962 frag_wane (fragP);
ee7fcc42 7963 return fragP->fr_fix - old_fr_fix;
252b5132 7964 }
93c2a809 7965
93c2a809
AM		 7966 /* Guess size depending on current relax state. Initially the relax
7967 state will correspond to a short jump and we return 1, because
7968 the variable part of the frag (the branch offset) is one byte
7969 long. However, we can relax a section more than once and in that
7970 case we must either set fr_subtype back to the unrelaxed state,
7971 or return the value for the appropriate branch. */
7972 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7973}
7974
47926f60
KH		 7975/* Called after relax() is finished.
7976
7977 In: Address of frag.
7978 fr_type == rs_machine_dependent.
7979 fr_subtype is what the address relaxed to.
7980
7981 Out: Any fixSs and constants are set up.
7982 Caller will turn frag into a ".space 0". */
7983
252b5132 7984void
7016a5d5
TG		 7985md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
7986 fragS *fragP)
252b5132 7987{
29b0f896 7988 unsigned char *opcode;
252b5132 7989 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7990 offsetT target_address;
7991 offsetT opcode_address;
252b5132 7992 unsigned int extension = 0;
847f7ad4 7993 offsetT displacement_from_opcode_start;
252b5132
RH		 7994
7995 opcode = (unsigned char *) fragP->fr_opcode;
7996
47926f60 7997 /* Address we want to reach in file space. */
252b5132 7998 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7999
47926f60 8000 /* Address opcode resides at in file space. */
252b5132
RH		 8001 opcode_address = fragP->fr_address + fragP->fr_fix;
8002
47926f60 8003 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 8004 displacement_from_opcode_start = target_address - opcode_address;
8005
fddf5b5b 8006 if ((fragP->fr_subtype & BIG) == 0)
252b5132 8007 {
47926f60
KH		 8008 /* Don't have to change opcode. */
8009 extension = 1; /* 1 opcode + 1 displacement */
252b5132 8010 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 8011 }
8012 else
8013 {
8014 if (no_cond_jump_promotion
8015 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 8016 as_warn_where (fragP->fr_file, fragP->fr_line,
8017 _("long jump required"));
252b5132 8018
fddf5b5b
AM		 8019 switch (fragP->fr_subtype)
8020 {
8021 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
8022 extension = 4; /* 1 opcode + 4 displacement */
8023 opcode[0] = 0xe9;
8024 where_to_put_displacement = &opcode[1];
8025 break;
252b5132 8026
fddf5b5b
AM		 8027 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
8028 extension = 2; /* 1 opcode + 2 displacement */
8029 opcode[0] = 0xe9;
8030 where_to_put_displacement = &opcode[1];
8031 break;
252b5132 8032
fddf5b5b
AM		 8033 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
8034 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
8035 extension = 5; /* 2 opcode + 4 displacement */
8036 opcode[1] = opcode[0] + 0x10;
8037 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
8038 where_to_put_displacement = &opcode[2];
8039 break;
252b5132 8040
fddf5b5b
AM		 8041 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
8042 extension = 3; /* 2 opcode + 2 displacement */
8043 opcode[1] = opcode[0] + 0x10;
8044 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
8045 where_to_put_displacement = &opcode[2];
8046 break;
252b5132 8047
fddf5b5b
AM		 8048 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
8049 extension = 4;
8050 opcode[0] ^= 1;
8051 opcode[1] = 3;
8052 opcode[2] = 0xe9;
8053 where_to_put_displacement = &opcode[3];
8054 break;
8055
8056 default:
8057 BAD_CASE (fragP->fr_subtype);
8058 break;
8059 }
252b5132 8060 }
fddf5b5b 8061
7b81dfbb
AJ		 8062 /* If size if less then four we are sure that the operand fits,
8063 but if it's 4, then it could be that the displacement is larger
8064 then -/+ 2GB. */
8065 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
8066 && object_64bit
8067 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 8068 + ((addressT) 1 << 31))
8069 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 8070 {
8071 as_bad_where (fragP->fr_file, fragP->fr_line,
8072 _("jump target out of range"));
8073 /* Make us emit 0. */
8074 displacement_from_opcode_start = extension;
8075 }
47926f60 8076 /* Now put displacement after opcode. */
252b5132
RH		 8077 md_number_to_chars ((char *) where_to_put_displacement,
8078 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 8079 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 8080 fragP->fr_fix += extension;
8081}
8082\f
7016a5d5 8083/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 8084 by our caller that we have all the info we need to fix it up.
8085
7016a5d5
TG		 8086 Parameter valP is the pointer to the value of the bits.
8087
252b5132
RH		 8088 On the 386, immediates, displacements, and data pointers are all in
8089 the same (little-endian) format, so we don't need to care about which
8090 we are handling. */
8091
94f592af 8092void
7016a5d5 8093md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 8094{
94f592af 8095 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 8096 valueT value = *valP;
252b5132 8097
f86103b7 8098#if !defined (TE_Mach)
93382f6d
AM		 8099 if (fixP->fx_pcrel)
8100 {
8101 switch (fixP->fx_r_type)
8102 {
5865bb77
ILT		 8103 default:
8104 break;
8105
d6ab8113
JB		 8106 case BFD_RELOC_64:
8107 fixP->fx_r_type = BFD_RELOC_64_PCREL;
8108 break;
93382f6d 8109 case BFD_RELOC_32:
ae8887b5 8110 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 8111 fixP->fx_r_type = BFD_RELOC_32_PCREL;
8112 break;
8113 case BFD_RELOC_16:
8114 fixP->fx_r_type = BFD_RELOC_16_PCREL;
8115 break;
8116 case BFD_RELOC_8:
8117 fixP->fx_r_type = BFD_RELOC_8_PCREL;
8118 break;
8119 }
8120 }
252b5132 8121
a161fe53 8122 if (fixP->fx_addsy != NULL
31312f95 8123 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 8124 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 8125 || fixP->fx_r_type == BFD_RELOC_16_PCREL
8126 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
8127 && !use_rela_relocations)
252b5132 8128 {
31312f95
AM		 8129 /* This is a hack. There should be a better way to handle this.
8130 This covers for the fact that bfd_install_relocation will
8131 subtract the current location (for partial_inplace, PC relative
8132 relocations); see more below. */
252b5132 8133#ifndef OBJ_AOUT
718ddfc0 8134 if (IS_ELF
252b5132
RH		 8135#ifdef TE_PE
8136 || OUTPUT_FLAVOR == bfd_target_coff_flavour
8137#endif
8138 )
8139 value += fixP->fx_where + fixP->fx_frag->fr_address;
8140#endif
8141#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8142 if (IS_ELF)
252b5132 8143 {
6539b54b 8144 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 8145
6539b54b 8146 if ((sym_seg == seg
2f66722d 8147 || (symbol_section_p (fixP->fx_addsy)
6539b54b 8148 && sym_seg != absolute_section))
af65af87 8149 && !generic_force_reloc (fixP))
2f66722d
AM		 8150 {
8151 /* Yes, we add the values in twice. This is because
6539b54b
AM		 8152 bfd_install_relocation subtracts them out again. I think
8153 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 8154 it. FIXME. */
8155 value += fixP->fx_where + fixP->fx_frag->fr_address;
8156 }
252b5132
RH		 8157 }
8158#endif
8159#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 8160 /* For some reason, the PE format does not store a
8161 section address offset for a PC relative symbol. */
8162 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 8163 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 8164 value += md_pcrel_from (fixP);
8165#endif
8166 }
fbeb56a4
DK		 8167#if defined (OBJ_COFF) && defined (TE_PE)
8168 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
8169 {
8170 value -= S_GET_VALUE (fixP->fx_addsy);
8171 }
8172#endif
252b5132
RH		 8173
8174 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 8175 and we must not disappoint it. */
252b5132 8176#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8177 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 8178 switch (fixP->fx_r_type)
8179 {
8180 case BFD_RELOC_386_PLT32:
3e73aa7c 8181 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 8182 /* Make the jump instruction point to the address of the operand. At
8183 runtime we merely add the offset to the actual PLT entry. */
8184 value = -4;
8185 break;
31312f95 8186
13ae64f3
JJ		 8187 case BFD_RELOC_386_TLS_GD:
8188 case BFD_RELOC_386_TLS_LDM:
13ae64f3 8189 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8190 case BFD_RELOC_386_TLS_IE:
8191 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 8192 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 8193 case BFD_RELOC_X86_64_TLSGD:
8194 case BFD_RELOC_X86_64_TLSLD:
8195 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 8196 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 8197 value = 0; /* Fully resolved at runtime. No addend. */
8198 /* Fallthrough */
8199 case BFD_RELOC_386_TLS_LE:
8200 case BFD_RELOC_386_TLS_LDO_32:
8201 case BFD_RELOC_386_TLS_LE_32:
8202 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8203 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 8204 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 8205 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 8206 S_SET_THREAD_LOCAL (fixP->fx_addsy);
8207 break;
8208
67a4f2b7
AO		 8209 case BFD_RELOC_386_TLS_DESC_CALL:
8210 case BFD_RELOC_X86_64_TLSDESC_CALL:
8211 value = 0; /* Fully resolved at runtime. No addend. */
8212 S_SET_THREAD_LOCAL (fixP->fx_addsy);
8213 fixP->fx_done = 0;
8214 return;
8215
00f7efb6
JJ		 8216 case BFD_RELOC_386_GOT32:
8217 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 8218 value = 0; /* Fully resolved at runtime. No addend. */
8219 break;
47926f60
KH		 8220
8221 case BFD_RELOC_VTABLE_INHERIT:
8222 case BFD_RELOC_VTABLE_ENTRY:
8223 fixP->fx_done = 0;
94f592af 8224 return;
47926f60
KH		 8225
8226 default:
8227 break;
8228 }
8229#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 8230 *valP = value;
f86103b7 8231#endif /* !defined (TE_Mach) */
3e73aa7c 8232
3e73aa7c 8233 /* Are we finished with this relocation now? */
c6682705 8234 if (fixP->fx_addsy == NULL)
3e73aa7c 8235 fixP->fx_done = 1;
fbeb56a4
DK		 8236#if defined (OBJ_COFF) && defined (TE_PE)
8237 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
8238 {
8239 fixP->fx_done = 0;
8240 /* Remember value for tc_gen_reloc. */
8241 fixP->fx_addnumber = value;
8242 /* Clear out the frag for now. */
8243 value = 0;
8244 }
8245#endif
3e73aa7c
JH		 8246 else if (use_rela_relocations)
8247 {
8248 fixP->fx_no_overflow = 1;
062cd5e7
AS		 8249 /* Remember value for tc_gen_reloc. */
8250 fixP->fx_addnumber = value;
3e73aa7c
JH		 8251 value = 0;
8252 }
f86103b7 8253
94f592af 8254 md_number_to_chars (p, value, fixP->fx_size);
252b5132 8255}
252b5132 8256\f
252b5132 8257char *
499ac353 8258md_atof (int type, char *litP, int *sizeP)
252b5132 8259{
499ac353
NC		 8260 /* This outputs the LITTLENUMs in REVERSE order;
8261 in accord with the bigendian 386. */
8262 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 8263}
8264\f
2d545b82 8265static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 8266
252b5132 8267static char *
e3bb37b5 8268output_invalid (int c)
252b5132 8269{
3882b010 8270 if (ISPRINT (c))
f9f21a03
L		 8271 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
8272 "'%c'", c);
252b5132 8273 else
f9f21a03 8274 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 8275 "(0x%x)", (unsigned char) c);
252b5132
RH		 8276 return output_invalid_buf;
8277}
8278
af6bdddf 8279/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 8280
8281static const reg_entry *
4d1bb795 8282parse_real_register (char *reg_string, char **end_op)
252b5132 8283{
af6bdddf
AM		 8284 char *s = reg_string;
8285 char *p;
252b5132
RH		 8286 char reg_name_given[MAX_REG_NAME_SIZE + 1];
8287 const reg_entry *r;
8288
8289 /* Skip possible REGISTER_PREFIX and possible whitespace. */
8290 if (*s == REGISTER_PREFIX)
8291 ++s;
8292
8293 if (is_space_char (*s))
8294 ++s;
8295
8296 p = reg_name_given;
af6bdddf 8297 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 8298 {
8299 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 8300 return (const reg_entry *) NULL;
8301 s++;
252b5132
RH		 8302 }
8303
6588847e
DN		 8304 /* For naked regs, make sure that we are not dealing with an identifier.
8305 This prevents confusing an identifier like `eax_var' with register
8306 `eax'. */
8307 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
8308 return (const reg_entry *) NULL;
8309
af6bdddf 8310 *end_op = s;
252b5132
RH		 8311
8312 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
8313
5f47d35b 8314 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 8315 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 8316 {
5f47d35b
AM		 8317 if (is_space_char (*s))
8318 ++s;
8319 if (*s == '(')
8320 {
af6bdddf 8321 ++s;
5f47d35b
AM		 8322 if (is_space_char (*s))
8323 ++s;
8324 if (*s >= '0' && *s <= '7')
8325 {
db557034 8326 int fpr = *s - '0';
af6bdddf 8327 ++s;
5f47d35b
AM		 8328 if (is_space_char (*s))
8329 ++s;
8330 if (*s == ')')
8331 {
8332 *end_op = s + 1;
1e9cc1c2 8333 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 8334 know (r);
8335 return r + fpr;
5f47d35b 8336 }
5f47d35b 8337 }
47926f60 8338 /* We have "%st(" then garbage. */
5f47d35b
AM		 8339 return (const reg_entry *) NULL;
8340 }
8341 }
8342
a60de03c
JB		 8343 if (r == NULL || allow_pseudo_reg)
8344 return r;
8345
0dfbf9d7 8346 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 8347 return (const reg_entry *) NULL;
8348
192dc9c6
JB		 8349 if ((r->reg_type.bitfield.reg32
8350 || r->reg_type.bitfield.sreg3
8351 || r->reg_type.bitfield.control
8352 || r->reg_type.bitfield.debug
8353 || r->reg_type.bitfield.test)
8354 && !cpu_arch_flags.bitfield.cpui386)
8355 return (const reg_entry *) NULL;
8356
309d3373
JB		 8357 if (r->reg_type.bitfield.floatreg
8358 && !cpu_arch_flags.bitfield.cpu8087
8359 && !cpu_arch_flags.bitfield.cpu287
8360 && !cpu_arch_flags.bitfield.cpu387)
8361 return (const reg_entry *) NULL;
8362
192dc9c6
JB		 8363 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
8364 return (const reg_entry *) NULL;
8365
8366 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
8367 return (const reg_entry *) NULL;
8368
40f12533
L		 8369 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
8370 return (const reg_entry *) NULL;
8371
db51cc60 8372 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 8373 if (!allow_index_reg
db51cc60
L		 8374 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
8375 return (const reg_entry *) NULL;
8376
a60de03c
JB		 8377 if (((r->reg_flags & (RegRex64 | RegRex))
8378 || r->reg_type.bitfield.reg64)
40fb9820 8379 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 8380 || !operand_type_equal (&r->reg_type, &control))
1ae00879 8381 && flag_code != CODE_64BIT)
20f0a1fc 8382 return (const reg_entry *) NULL;
1ae00879 8383
b7240065
JB		 8384 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
8385 return (const reg_entry *) NULL;
8386
252b5132
RH		 8387 return r;
8388}
4d1bb795
JB		 8389
8390/* REG_STRING starts *before* REGISTER_PREFIX. */
8391
8392static const reg_entry *
8393parse_register (char *reg_string, char **end_op)
8394{
8395 const reg_entry *r;
8396
8397 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
8398 r = parse_real_register (reg_string, end_op);
8399 else
8400 r = NULL;
8401 if (!r)
8402 {
8403 char *save = input_line_pointer;
8404 char c;
8405 symbolS *symbolP;
8406
8407 input_line_pointer = reg_string;
8408 c = get_symbol_end ();
8409 symbolP = symbol_find (reg_string);
8410 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
8411 {
8412 const expressionS *e = symbol_get_value_expression (symbolP);
8413
0398aac5 8414 know (e->X_op == O_register);
4eed87de 8415 know (e->X_add_number >= 0
c3fe08fa 8416 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 8417 r = i386_regtab + e->X_add_number;
8418 *end_op = input_line_pointer;
8419 }
8420 *input_line_pointer = c;
8421 input_line_pointer = save;
8422 }
8423 return r;
8424}
8425
8426int
8427i386_parse_name (char *name, expressionS *e, char *nextcharP)
8428{
8429 const reg_entry *r;
8430 char *end = input_line_pointer;
8431
8432 *end = *nextcharP;
8433 r = parse_register (name, &input_line_pointer);
8434 if (r && end <= input_line_pointer)
8435 {
8436 *nextcharP = *input_line_pointer;
8437 *input_line_pointer = 0;
8438 e->X_op = O_register;
8439 e->X_add_number = r - i386_regtab;
8440 return 1;
8441 }
8442 input_line_pointer = end;
8443 *end = 0;
ee86248c 8444 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 8445}
8446
8447void
8448md_operand (expressionS *e)
8449{
ee86248c
JB		 8450 char *end;
8451 const reg_entry *r;
4d1bb795 8452
ee86248c
JB		 8453 switch (*input_line_pointer)
8454 {
8455 case REGISTER_PREFIX:
8456 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 8457 if (r)
8458 {
8459 e->X_op = O_register;
8460 e->X_add_number = r - i386_regtab;
8461 input_line_pointer = end;
8462 }
ee86248c
JB		 8463 break;
8464
8465 case '[':
9c2799c2 8466 gas_assert (intel_syntax);
ee86248c
JB		 8467 end = input_line_pointer++;
8468 expression (e);
8469 if (*input_line_pointer == ']')
8470 {
8471 ++input_line_pointer;
8472 e->X_op_symbol = make_expr_symbol (e);
8473 e->X_add_symbol = NULL;
8474 e->X_add_number = 0;
8475 e->X_op = O_index;
8476 }
8477 else
8478 {
8479 e->X_op = O_absent;
8480 input_line_pointer = end;
8481 }
8482 break;
4d1bb795
JB		 8483 }
8484}
8485
252b5132 8486\f
4cc782b5 8487#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 8488const char *md_shortopts = "kVQ:sqn";
252b5132 8489#else
12b55ccc 8490const char *md_shortopts = "qn";
252b5132 8491#endif
6e0b89ee 8492
3e73aa7c 8493#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 8494#define OPTION_64 (OPTION_MD_BASE + 1)
8495#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 8496#define OPTION_MARCH (OPTION_MD_BASE + 3)
8497#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 8498#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8499#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8500#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8501#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8502#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 8503#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 8504#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
40a9833c 8505#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 12)
570561f7 8506#define OPTION_X32 (OPTION_MD_BASE + 13)
b3b91714 8507
99ad8390
NC		 8508struct option md_longopts[] =
8509{
3e73aa7c 8510 {"32", no_argument, NULL, OPTION_32},
321098a5 8511#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 8512 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 8513 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 8514#endif
8515#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 8516 {"x32", no_argument, NULL, OPTION_X32},
6e0b89ee 8517#endif
b3b91714 8518 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 8519 {"march", required_argument, NULL, OPTION_MARCH},
8520 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 8521 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
8522 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
8523 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
8524 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
8525 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 8526 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 8527 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
539f890d 8528 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
252b5132
RH		 8529 {NULL, no_argument, NULL, 0}
8530};
8531size_t md_longopts_size = sizeof (md_longopts);
8532
8533int
9103f4f4 8534md_parse_option (int c, char *arg)
252b5132 8535{
91d6fa6a 8536 unsigned int j;
6305a203 8537 char *arch, *next;
9103f4f4 8538
252b5132
RH		 8539 switch (c)
8540 {
12b55ccc
L		 8541 case 'n':
8542 optimize_align_code = 0;
8543 break;
8544
a38cf1db
AM		 8545 case 'q':
8546 quiet_warnings = 1;
252b5132
RH		 8547 break;
8548
8549#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 8550 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8551 should be emitted or not. FIXME: Not implemented. */
8552 case 'Q':
252b5132
RH		 8553 break;
8554
8555 /* -V: SVR4 argument to print version ID. */
8556 case 'V':
8557 print_version_id ();
8558 break;
8559
a38cf1db
AM		 8560 /* -k: Ignore for FreeBSD compatibility. */
8561 case 'k':
252b5132 8562 break;
4cc782b5
ILT		 8563
8564 case 's':
8565 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 8566 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 8567 break;
99ad8390 8568#endif
321098a5 8569#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 8570 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 8571 case OPTION_64:
8572 {
8573 const char **list, **l;
8574
3e73aa7c
JH		 8575 list = bfd_target_list ();
8576 for (l = list; *l != NULL; l++)
8620418b 8577 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 8578 || strcmp (*l, "coff-x86-64") == 0
8579 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 8580 || strcmp (*l, "pei-x86-64") == 0
8581 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 8582 {
8583 default_arch = "x86_64";
8584 break;
8585 }
3e73aa7c 8586 if (*l == NULL)
2b5d6a91 8587 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 8588 free (list);
8589 }
8590 break;
8591#endif
252b5132 8592
351f65ca 8593#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 8594 case OPTION_X32:
351f65ca
L		 8595 if (IS_ELF)
8596 {
8597 const char **list, **l;
8598
8599 list = bfd_target_list ();
8600 for (l = list; *l != NULL; l++)
8601 if (CONST_STRNEQ (*l, "elf32-x86-64"))
8602 {
8603 default_arch = "x86_64:32";
8604 break;
8605 }
8606 if (*l == NULL)
2b5d6a91 8607 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 8608 free (list);
8609 }
8610 else
8611 as_fatal (_("32bit x86_64 is only supported for ELF"));
8612 break;
8613#endif
8614
6e0b89ee
AM		 8615 case OPTION_32:
8616 default_arch = "i386";
8617 break;
8618
b3b91714
AM		 8619 case OPTION_DIVIDE:
8620#ifdef SVR4_COMMENT_CHARS
8621 {
8622 char *n, *t;
8623 const char *s;
8624
8625 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
8626 t = n;
8627 for (s = i386_comment_chars; *s != '\0'; s++)
8628 if (*s != '/')
8629 *t++ = *s;
8630 *t = '\0';
8631 i386_comment_chars = n;
8632 }
8633#endif
8634 break;
8635
9103f4f4 8636 case OPTION_MARCH:
6305a203
L		 8637 arch = xstrdup (arg);
8638 do
9103f4f4 8639 {
6305a203 8640 if (*arch == '.')
2b5d6a91 8641 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 8642 next = strchr (arch, '+');
8643 if (next)
8644 *next++ = '\0';
91d6fa6a 8645 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8646 {
91d6fa6a 8647 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 8648 {
6305a203 8649 /* Processor. */
1ded5609
JB		 8650 if (! cpu_arch[j].flags.bitfield.cpui386)
8651 continue;
8652
91d6fa6a 8653 cpu_arch_name = cpu_arch[j].name;
6305a203 8654 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 8655 cpu_arch_flags = cpu_arch[j].flags;
8656 cpu_arch_isa = cpu_arch[j].type;
8657 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 8658 if (!cpu_arch_tune_set)
8659 {
8660 cpu_arch_tune = cpu_arch_isa;
8661 cpu_arch_tune_flags = cpu_arch_isa_flags;
8662 }
8663 break;
8664 }
91d6fa6a
NC		 8665 else if (*cpu_arch [j].name == '.'
8666 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 8667 {
8668 /* ISA entension. */
8669 i386_cpu_flags flags;
309d3373 8670
49021df2 8671 if (!cpu_arch[j].negated)
309d3373 8672 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 8673 cpu_arch[j].flags);
309d3373
JB		 8674 else
8675 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 8676 cpu_arch[j].flags);
0dfbf9d7 8677 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8678 {
8679 if (cpu_sub_arch_name)
8680 {
8681 char *name = cpu_sub_arch_name;
8682 cpu_sub_arch_name = concat (name,
91d6fa6a 8683 cpu_arch[j].name,
1bf57e9f 8684 (const char *) NULL);
6305a203
L		 8685 free (name);
8686 }
8687 else
91d6fa6a 8688 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 8689 cpu_arch_flags = flags;
a586129e 8690 cpu_arch_isa_flags = flags;
6305a203
L		 8691 }
8692 break;
ccc9c027 8693 }
9103f4f4 8694 }
6305a203 8695
91d6fa6a 8696 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 8697 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 8698
8699 arch = next;
9103f4f4 8700 }
6305a203 8701 while (next != NULL );
9103f4f4
L		 8702 break;
8703
8704 case OPTION_MTUNE:
8705 if (*arg == '.')
2b5d6a91 8706 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 8707 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8708 {
91d6fa6a 8709 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 8710 {
ccc9c027 8711 cpu_arch_tune_set = 1;
91d6fa6a
NC		 8712 cpu_arch_tune = cpu_arch [j].type;
8713 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 8714 break;
8715 }
8716 }
91d6fa6a 8717 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 8718 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 8719 break;
8720
1efbbeb4
L		 8721 case OPTION_MMNEMONIC:
8722 if (strcasecmp (arg, "att") == 0)
8723 intel_mnemonic = 0;
8724 else if (strcasecmp (arg, "intel") == 0)
8725 intel_mnemonic = 1;
8726 else
2b5d6a91 8727 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 8728 break;
8729
8730 case OPTION_MSYNTAX:
8731 if (strcasecmp (arg, "att") == 0)
8732 intel_syntax = 0;
8733 else if (strcasecmp (arg, "intel") == 0)
8734 intel_syntax = 1;
8735 else
2b5d6a91 8736 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 8737 break;
8738
8739 case OPTION_MINDEX_REG:
8740 allow_index_reg = 1;
8741 break;
8742
8743 case OPTION_MNAKED_REG:
8744 allow_naked_reg = 1;
8745 break;
8746
8747 case OPTION_MOLD_GCC:
8748 old_gcc = 1;
1efbbeb4
L		 8749 break;
8750
c0f3af97
L		 8751 case OPTION_MSSE2AVX:
8752 sse2avx = 1;
8753 break;
8754
daf50ae7
L		 8755 case OPTION_MSSE_CHECK:
8756 if (strcasecmp (arg, "error") == 0)
8757 sse_check = sse_check_error;
8758 else if (strcasecmp (arg, "warning") == 0)
8759 sse_check = sse_check_warning;
8760 else if (strcasecmp (arg, "none") == 0)
8761 sse_check = sse_check_none;
8762 else
2b5d6a91 8763 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 8764 break;
8765
539f890d
L		 8766 case OPTION_MAVXSCALAR:
8767 if (strcasecmp (arg, "128") == 0)
8768 avxscalar = vex128;
8769 else if (strcasecmp (arg, "256") == 0)
8770 avxscalar = vex256;
8771 else
2b5d6a91 8772 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 8773 break;
8774
252b5132
RH		 8775 default:
8776 return 0;
8777 }
8778 return 1;
8779}
8780
8a2c8fef
L		 8781#define MESSAGE_TEMPLATE \
8782" "
8783
8784static void
1ded5609 8785show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 8786{
8787 static char message[] = MESSAGE_TEMPLATE;
8788 char *start = message + 27;
8789 char *p;
8790 int size = sizeof (MESSAGE_TEMPLATE);
8791 int left;
8792 const char *name;
8793 int len;
8794 unsigned int j;
8795
8796 p = start;
8797 left = size - (start - message);
8798 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
8799 {
8800 /* Should it be skipped? */
8801 if (cpu_arch [j].skip)
8802 continue;
8803
8804 name = cpu_arch [j].name;
8805 len = cpu_arch [j].len;
8806 if (*name == '.')
8807 {
8808 /* It is an extension. Skip if we aren't asked to show it. */
8809 if (ext)
8810 {
8811 name++;
8812 len--;
8813 }
8814 else
8815 continue;
8816 }
8817 else if (ext)
8818 {
8819 /* It is an processor. Skip if we show only extension. */
8820 continue;
8821 }
1ded5609
JB		 8822 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
8823 {
8824 /* It is an impossible processor - skip. */
8825 continue;
8826 }
8a2c8fef
L		 8827
8828 /* Reserve 2 spaces for ", " or ",\0" */
8829 left -= len + 2;
8830
8831 /* Check if there is any room. */
8832 if (left >= 0)
8833 {
8834 if (p != start)
8835 {
8836 *p++ = ',';
8837 *p++ = ' ';
8838 }
8839 p = mempcpy (p, name, len);
8840 }
8841 else
8842 {
8843 /* Output the current message now and start a new one. */
8844 *p++ = ',';
8845 *p = '\0';
8846 fprintf (stream, "%s\n", message);
8847 p = start;
8848 left = size - (start - message) - len - 2;
8d63c93e 8849
8a2c8fef
L		 8850 gas_assert (left >= 0);
8851
8852 p = mempcpy (p, name, len);
8853 }
8854 }
8855
8856 *p = '\0';
8857 fprintf (stream, "%s\n", message);
8858}
8859
252b5132 8860void
8a2c8fef 8861md_show_usage (FILE *stream)
252b5132 8862{
4cc782b5
ILT		 8863#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8864 fprintf (stream, _("\
a38cf1db
AM		 8865 -Q ignored\n\
8866 -V print assembler version number\n\
b3b91714
AM		 8867 -k ignored\n"));
8868#endif
8869 fprintf (stream, _("\
12b55ccc 8870 -n Do not optimize code alignment\n\
b3b91714
AM		 8871 -q quieten some warnings\n"));
8872#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8873 fprintf (stream, _("\
a38cf1db 8874 -s ignored\n"));
b3b91714 8875#endif
321098a5
L		 8876#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8877 || defined (TE_PE) || defined (TE_PEP))
751d281c 8878 fprintf (stream, _("\
570561f7 8879 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 8880#endif
b3b91714
AM		 8881#ifdef SVR4_COMMENT_CHARS
8882 fprintf (stream, _("\
8883 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8884#else
8885 fprintf (stream, _("\
b3b91714 8886 --divide ignored\n"));
4cc782b5 8887#endif
9103f4f4 8888 fprintf (stream, _("\
6305a203 8889 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 8890 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 8891 show_arch (stream, 0, 1);
8a2c8fef
L		 8892 fprintf (stream, _("\
8893 EXTENSION is combination of:\n"));
1ded5609 8894 show_arch (stream, 1, 0);
6305a203 8895 fprintf (stream, _("\
8a2c8fef 8896 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 8897 show_arch (stream, 0, 0);
ba104c83 8898 fprintf (stream, _("\
c0f3af97
L		 8899 -msse2avx encode SSE instructions with VEX prefix\n"));
8900 fprintf (stream, _("\
daf50ae7
L		 8901 -msse-check=[none|error|warning]\n\
8902 check SSE instructions\n"));
8903 fprintf (stream, _("\
539f890d
L		 8904 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8905 length\n"));
8906 fprintf (stream, _("\
ba104c83
L		 8907 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8908 fprintf (stream, _("\
8909 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8910 fprintf (stream, _("\
8911 -mindex-reg support pseudo index registers\n"));
8912 fprintf (stream, _("\
8913 -mnaked-reg don't require `%%' prefix for registers\n"));
8914 fprintf (stream, _("\
8915 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8916}
8917
3e73aa7c 8918#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 8919 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 8920 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 8921
8922/* Pick the target format to use. */
8923
47926f60 8924const char *
e3bb37b5 8925i386_target_format (void)
252b5132 8926{
351f65ca
L		 8927 if (!strncmp (default_arch, "x86_64", 6))
8928 {
8929 update_code_flag (CODE_64BIT, 1);
8930 if (default_arch[6] == '\0')
7f56bc95 8931 x86_elf_abi = X86_64_ABI;
351f65ca 8932 else
7f56bc95 8933 x86_elf_abi = X86_64_X32_ABI;
351f65ca 8934 }
3e73aa7c 8935 else if (!strcmp (default_arch, "i386"))
78f12dd3 8936 update_code_flag (CODE_32BIT, 1);
3e73aa7c 8937 else
2b5d6a91 8938 as_fatal (_("unknown architecture"));
89507696
JB		 8939
8940 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
8941 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
8942 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
8943 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
8944
252b5132
RH		 8945 switch (OUTPUT_FLAVOR)
8946 {
9384f2ff 8947#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 8948 case bfd_target_aout_flavour:
47926f60 8949 return AOUT_TARGET_FORMAT;
4c63da97 8950#endif
9384f2ff
AM		 8951#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8952# if defined (TE_PE) || defined (TE_PEP)
8953 case bfd_target_coff_flavour:
8954 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
8955# elif defined (TE_GO32)
0561d57c
JK		 8956 case bfd_target_coff_flavour:
8957 return "coff-go32";
9384f2ff 8958# else
252b5132
RH		 8959 case bfd_target_coff_flavour:
8960 return "coff-i386";
9384f2ff 8961# endif
4c63da97 8962#endif
3e73aa7c 8963#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8964 case bfd_target_elf_flavour:
3e73aa7c 8965 {
351f65ca
L		 8966 const char *format;
8967
8968 switch (x86_elf_abi)
4fa24527 8969 {
351f65ca
L		 8970 default:
8971 format = ELF_TARGET_FORMAT;
8972 break;
7f56bc95 8973 case X86_64_ABI:
351f65ca 8974 use_rela_relocations = 1;
4fa24527 8975 object_64bit = 1;
351f65ca
L		 8976 format = ELF_TARGET_FORMAT64;
8977 break;
7f56bc95 8978 case X86_64_X32_ABI:
4fa24527 8979 use_rela_relocations = 1;
351f65ca 8980 object_64bit = 1;
862be3fb 8981 disallow_64bit_reloc = 1;
351f65ca
L		 8982 format = ELF_TARGET_FORMAT32;
8983 break;
4fa24527 8984 }
3632d14b 8985 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 8986 {
7f56bc95 8987 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 8988 as_fatal (_("Intel L1OM is 64bit only"));
8989 return ELF_TARGET_L1OM_FORMAT;
8990 }
7a9068fe
L		 8991 if (cpu_arch_isa == PROCESSOR_K1OM)
8992 {
8993 if (x86_elf_abi != X86_64_ABI)
8994 as_fatal (_("Intel K1OM is 64bit only"));
8995 return ELF_TARGET_K1OM_FORMAT;
8996 }
8a9036a4 8997 else
351f65ca 8998 return format;
3e73aa7c 8999 }
e57f8c65
TG		 9000#endif
9001#if defined (OBJ_MACH_O)
9002 case bfd_target_mach_o_flavour:
d382c579
TG		 9003 if (flag_code == CODE_64BIT)
9004 {
9005 use_rela_relocations = 1;
9006 object_64bit = 1;
9007 return "mach-o-x86-64";
9008 }
9009 else
9010 return "mach-o-i386";
4c63da97 9011#endif
252b5132
RH		 9012 default:
9013 abort ();
9014 return NULL;
9015 }
9016}
9017
47926f60 9018#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 9019
9020#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 9021void
9022i386_elf_emit_arch_note (void)
a847613f 9023{
718ddfc0 9024 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 9025 {
9026 char *p;
9027 asection *seg = now_seg;
9028 subsegT subseg = now_subseg;
9029 Elf_Internal_Note i_note;
9030 Elf_External_Note e_note;
9031 asection *note_secp;
9032 int len;
9033
9034 /* Create the .note section. */
9035 note_secp = subseg_new (".note", 0);
9036 bfd_set_section_flags (stdoutput,
9037 note_secp,
9038 SEC_HAS_CONTENTS | SEC_READONLY);
9039
9040 /* Process the arch string. */
9041 len = strlen (cpu_arch_name);
9042
9043 i_note.namesz = len + 1;
9044 i_note.descsz = 0;
9045 i_note.type = NT_ARCH;
9046 p = frag_more (sizeof (e_note.namesz));
9047 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
9048 p = frag_more (sizeof (e_note.descsz));
9049 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
9050 p = frag_more (sizeof (e_note.type));
9051 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
9052 p = frag_more (len + 1);
9053 strcpy (p, cpu_arch_name);
9054
9055 frag_align (2, 0, 0);
9056
9057 subseg_set (seg, subseg);
9058 }
9059}
9060#endif
252b5132 9061\f
252b5132 9062symbolS *
7016a5d5 9063md_undefined_symbol (char *name)
252b5132 9064{
18dc2407
ILT		 9065 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
9066 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
9067 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
9068 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 9069 {
9070 if (!GOT_symbol)
9071 {
9072 if (symbol_find (name))
9073 as_bad (_("GOT already in symbol table"));
9074 GOT_symbol = symbol_new (name, undefined_section,
9075 (valueT) 0, &zero_address_frag);
9076 };
9077 return GOT_symbol;
9078 }
252b5132
RH		 9079 return 0;
9080}
9081
9082/* Round up a section size to the appropriate boundary. */
47926f60 9083
252b5132 9084valueT
7016a5d5 9085md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 9086{
4c63da97
AM		 9087#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9088 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
9089 {
9090 /* For a.out, force the section size to be aligned. If we don't do
9091 this, BFD will align it for us, but it will not write out the
9092 final bytes of the section. This may be a bug in BFD, but it is
9093 easier to fix it here since that is how the other a.out targets
9094 work. */
9095 int align;
9096
9097 align = bfd_get_section_alignment (stdoutput, segment);
9098 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
9099 }
252b5132
RH		 9100#endif
9101
9102 return size;
9103}
9104
9105/* On the i386, PC-relative offsets are relative to the start of the
9106 next instruction. That is, the address of the offset, plus its
9107 size, since the offset is always the last part of the insn. */
9108
9109long
e3bb37b5 9110md_pcrel_from (fixS *fixP)
252b5132
RH		 9111{
9112 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
9113}
9114
9115#ifndef I386COFF
9116
9117static void
e3bb37b5 9118s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 9119{
29b0f896 9120 int temp;
252b5132 9121
8a75718c
JB		 9122#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9123 if (IS_ELF)
9124 obj_elf_section_change_hook ();
9125#endif
252b5132
RH		 9126 temp = get_absolute_expression ();
9127 subseg_set (bss_section, (subsegT) temp);
9128 demand_empty_rest_of_line ();
9129}
9130
9131#endif
9132
252b5132 9133void
e3bb37b5 9134i386_validate_fix (fixS *fixp)
252b5132
RH		 9135{
9136 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
9137 {
23df1078
JH		 9138 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
9139 {
4fa24527 9140 if (!object_64bit)
23df1078
JH		 9141 abort ();
9142 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
9143 }
9144 else
9145 {
4fa24527 9146 if (!object_64bit)
d6ab8113
JB		 9147 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
9148 else
9149 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 9150 }
252b5132
RH		 9151 fixp->fx_subsy = 0;
9152 }
9153}
9154
252b5132 9155arelent *
7016a5d5 9156tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 9157{
9158 arelent *rel;
9159 bfd_reloc_code_real_type code;
9160
9161 switch (fixp->fx_r_type)
9162 {
3e73aa7c
JH		 9163 case BFD_RELOC_X86_64_PLT32:
9164 case BFD_RELOC_X86_64_GOT32:
9165 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 9166 case BFD_RELOC_386_PLT32:
9167 case BFD_RELOC_386_GOT32:
9168 case BFD_RELOC_386_GOTOFF:
9169 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 9170 case BFD_RELOC_386_TLS_GD:
9171 case BFD_RELOC_386_TLS_LDM:
9172 case BFD_RELOC_386_TLS_LDO_32:
9173 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9174 case BFD_RELOC_386_TLS_IE:
9175 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 9176 case BFD_RELOC_386_TLS_LE_32:
9177 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 9178 case BFD_RELOC_386_TLS_GOTDESC:
9179 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 9180 case BFD_RELOC_X86_64_TLSGD:
9181 case BFD_RELOC_X86_64_TLSLD:
9182 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9183 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 9184 case BFD_RELOC_X86_64_GOTTPOFF:
9185 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 9186 case BFD_RELOC_X86_64_TPOFF64:
9187 case BFD_RELOC_X86_64_GOTOFF64:
9188 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 9189 case BFD_RELOC_X86_64_GOT64:
9190 case BFD_RELOC_X86_64_GOTPCREL64:
9191 case BFD_RELOC_X86_64_GOTPC64:
9192 case BFD_RELOC_X86_64_GOTPLT64:
9193 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 9194 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9195 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 9196 case BFD_RELOC_RVA:
9197 case BFD_RELOC_VTABLE_ENTRY:
9198 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 9199#ifdef TE_PE
9200 case BFD_RELOC_32_SECREL:
9201#endif
252b5132
RH		 9202 code = fixp->fx_r_type;
9203 break;
dbbaec26
L		 9204 case BFD_RELOC_X86_64_32S:
9205 if (!fixp->fx_pcrel)
9206 {
9207 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
9208 code = fixp->fx_r_type;
9209 break;
9210 }
252b5132 9211 default:
93382f6d 9212 if (fixp->fx_pcrel)
252b5132 9213 {
93382f6d
AM		 9214 switch (fixp->fx_size)
9215 {
9216 default:
b091f402
AM		 9217 as_bad_where (fixp->fx_file, fixp->fx_line,
9218 _("can not do %d byte pc-relative relocation"),
9219 fixp->fx_size);
93382f6d
AM		 9220 code = BFD_RELOC_32_PCREL;
9221 break;
9222 case 1: code = BFD_RELOC_8_PCREL; break;
9223 case 2: code = BFD_RELOC_16_PCREL; break;
9224 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 9225#ifdef BFD64
9226 case 8: code = BFD_RELOC_64_PCREL; break;
9227#endif
93382f6d
AM		 9228 }
9229 }
9230 else
9231 {
9232 switch (fixp->fx_size)
9233 {
9234 default:
b091f402
AM		 9235 as_bad_where (fixp->fx_file, fixp->fx_line,
9236 _("can not do %d byte relocation"),
9237 fixp->fx_size);
93382f6d
AM		 9238 code = BFD_RELOC_32;
9239 break;
9240 case 1: code = BFD_RELOC_8; break;
9241 case 2: code = BFD_RELOC_16; break;
9242 case 4: code = BFD_RELOC_32; break;
937149dd 9243#ifdef BFD64
3e73aa7c 9244 case 8: code = BFD_RELOC_64; break;
937149dd 9245#endif
93382f6d 9246 }
252b5132
RH		 9247 }
9248 break;
9249 }
252b5132 9250
d182319b
JB		 9251 if ((code == BFD_RELOC_32
9252 || code == BFD_RELOC_32_PCREL
9253 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 9254 && GOT_symbol
9255 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 9256 {
4fa24527 9257 if (!object_64bit)
d6ab8113
JB		 9258 code = BFD_RELOC_386_GOTPC;
9259 else
9260 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 9261 }
7b81dfbb
AJ		 9262 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
9263 && GOT_symbol
9264 && fixp->fx_addsy == GOT_symbol)
9265 {
9266 code = BFD_RELOC_X86_64_GOTPC64;
9267 }
252b5132
RH		 9268
9269 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 9270 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
9271 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 9272
9273 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 9274
3e73aa7c
JH		 9275 if (!use_rela_relocations)
9276 {
9277 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
9278 vtable entry to be used in the relocation's section offset. */
9279 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
9280 rel->address = fixp->fx_offset;
fbeb56a4
DK		 9281#if defined (OBJ_COFF) && defined (TE_PE)
9282 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
9283 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
9284 else
9285#endif
c6682705 9286 rel->addend = 0;
3e73aa7c
JH		 9287 }
9288 /* Use the rela in 64bit mode. */
252b5132 9289 else
3e73aa7c 9290 {
862be3fb
L		 9291 if (disallow_64bit_reloc)
9292 switch (code)
9293 {
862be3fb
L		 9294 case BFD_RELOC_X86_64_DTPOFF64:
9295 case BFD_RELOC_X86_64_TPOFF64:
9296 case BFD_RELOC_64_PCREL:
9297 case BFD_RELOC_X86_64_GOTOFF64:
9298 case BFD_RELOC_X86_64_GOT64:
9299 case BFD_RELOC_X86_64_GOTPCREL64:
9300 case BFD_RELOC_X86_64_GOTPC64:
9301 case BFD_RELOC_X86_64_GOTPLT64:
9302 case BFD_RELOC_X86_64_PLTOFF64:
9303 as_bad_where (fixp->fx_file, fixp->fx_line,
9304 _("cannot represent relocation type %s in x32 mode"),
9305 bfd_get_reloc_code_name (code));
9306 break;
9307 default:
9308 break;
9309 }
9310
062cd5e7
AS		 9311 if (!fixp->fx_pcrel)
9312 rel->addend = fixp->fx_offset;
9313 else
9314 switch (code)
9315 {
9316 case BFD_RELOC_X86_64_PLT32:
9317 case BFD_RELOC_X86_64_GOT32:
9318 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 9319 case BFD_RELOC_X86_64_TLSGD:
9320 case BFD_RELOC_X86_64_TLSLD:
9321 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 9322 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9323 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 9324 rel->addend = fixp->fx_offset - fixp->fx_size;
9325 break;
9326 default:
9327 rel->addend = (section->vma
9328 - fixp->fx_size
9329 + fixp->fx_addnumber
9330 + md_pcrel_from (fixp));
9331 break;
9332 }
3e73aa7c
JH		 9333 }
9334
252b5132
RH		 9335 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
9336 if (rel->howto == NULL)
9337 {
9338 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 9339 _("cannot represent relocation type %s"),
252b5132
RH		 9340 bfd_get_reloc_code_name (code));
9341 /* Set howto to a garbage value so that we can keep going. */
9342 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 9343 gas_assert (rel->howto != NULL);
252b5132
RH		 9344 }
9345
9346 return rel;
9347}
9348
ee86248c 9349#include "tc-i386-intel.c"
54cfded0 9350
a60de03c
JB		 9351void
9352tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 9353{
a60de03c
JB		 9354 int saved_naked_reg;
9355 char saved_register_dot;
54cfded0 9356
a60de03c
JB		 9357 saved_naked_reg = allow_naked_reg;
9358 allow_naked_reg = 1;
9359 saved_register_dot = register_chars['.'];
9360 register_chars['.'] = '.';
9361 allow_pseudo_reg = 1;
9362 expression_and_evaluate (exp);
9363 allow_pseudo_reg = 0;
9364 register_chars['.'] = saved_register_dot;
9365 allow_naked_reg = saved_naked_reg;
9366
e96d56a1 9367 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 9368 {
a60de03c
JB		 9369 if ((addressT) exp->X_add_number < i386_regtab_size)
9370 {
9371 exp->X_op = O_constant;
9372 exp->X_add_number = i386_regtab[exp->X_add_number]
9373 .dw2_regnum[flag_code >> 1];
9374 }
9375 else
9376 exp->X_op = O_illegal;
54cfded0 9377 }
54cfded0
AM		 9378}
9379
9380void
9381tc_x86_frame_initial_instructions (void)
9382{
a60de03c
JB		 9383 static unsigned int sp_regno[2];
9384
9385 if (!sp_regno[flag_code >> 1])
9386 {
9387 char *saved_input = input_line_pointer;
9388 char sp[][4] = {"esp", "rsp"};
9389 expressionS exp;
a4447b93 9390
a60de03c
JB		 9391 input_line_pointer = sp[flag_code >> 1];
9392 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 9393 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 9394 sp_regno[flag_code >> 1] = exp.X_add_number;
9395 input_line_pointer = saved_input;
9396 }
a4447b93 9397
61ff971f
L		 9398 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
9399 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 9400}
d2b2c203 9401
d7921315
L		 9402int
9403x86_dwarf2_addr_size (void)
9404{
9405#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9406 if (x86_elf_abi == X86_64_X32_ABI)
9407 return 4;
9408#endif
9409 return bfd_arch_bits_per_address (stdoutput) / 8;
9410}
9411
d2b2c203
DJ		 9412int
9413i386_elf_section_type (const char *str, size_t len)
9414{
9415 if (flag_code == CODE_64BIT
9416 && len == sizeof ("unwind") - 1
9417 && strncmp (str, "unwind", 6) == 0)
9418 return SHT_X86_64_UNWIND;
9419
9420 return -1;
9421}
bb41ade5 9422
ad5fec3b
EB		 9423#ifdef TE_SOLARIS
9424void
9425i386_solaris_fix_up_eh_frame (segT sec)
9426{
9427 if (flag_code == CODE_64BIT)
9428 elf_section_type (sec) = SHT_X86_64_UNWIND;
9429}
9430#endif
9431
bb41ade5
AM		 9432#ifdef TE_PE
9433void
9434tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
9435{
91d6fa6a 9436 expressionS exp;
bb41ade5 9437
91d6fa6a
NC		 9438 exp.X_op = O_secrel;
9439 exp.X_add_symbol = symbol;
9440 exp.X_add_number = 0;
9441 emit_expr (&exp, size);
bb41ade5
AM		 9442}
9443#endif
3b22753a
L		 9444
9445#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9446/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9447
01e1a5bc 9448bfd_vma
3b22753a
L		 9449x86_64_section_letter (int letter, char **ptr_msg)
9450{
9451 if (flag_code == CODE_64BIT)
9452 {
9453 if (letter == 'l')
9454 return SHF_X86_64_LARGE;
9455
8f3bae45 9456 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 9457 }
3b22753a 9458 else
8f3bae45 9459 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 9460 return -1;
9461}
9462
01e1a5bc 9463bfd_vma
3b22753a
L		 9464x86_64_section_word (char *str, size_t len)
9465{
8620418b 9466 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 9467 return SHF_X86_64_LARGE;
9468
9469 return -1;
9470}
9471
9472static void
9473handle_large_common (int small ATTRIBUTE_UNUSED)
9474{
9475 if (flag_code != CODE_64BIT)
9476 {
9477 s_comm_internal (0, elf_common_parse);
9478 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9479 }
9480 else
9481 {
9482 static segT lbss_section;
9483 asection *saved_com_section_ptr = elf_com_section_ptr;
9484 asection *saved_bss_section = bss_section;
9485
9486 if (lbss_section == NULL)
9487 {
9488 flagword applicable;
9489 segT seg = now_seg;
9490 subsegT subseg = now_subseg;
9491
9492 /* The .lbss section is for local .largecomm symbols. */
9493 lbss_section = subseg_new (".lbss", 0);
9494 applicable = bfd_applicable_section_flags (stdoutput);
9495 bfd_set_section_flags (stdoutput, lbss_section,
9496 applicable & SEC_ALLOC);
9497 seg_info (lbss_section)->bss = 1;
9498
9499 subseg_set (seg, subseg);
9500 }
9501
9502 elf_com_section_ptr = &_bfd_elf_large_com_section;
9503 bss_section = lbss_section;
9504
9505 s_comm_internal (0, elf_common_parse);
9506
9507 elf_com_section_ptr = saved_com_section_ptr;
9508 bss_section = saved_bss_section;
9509 }
9510}
9511#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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