Commit | Line | Data |
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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
f7e42eb4 | 2 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
d382c579 TG |
3 | 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, |
4 | 2012 | |
47926f60 | 5 | Free Software Foundation, Inc. |
252b5132 RH |
6 | |
7 | This file is part of GAS, the GNU Assembler. | |
8 | ||
9 | GAS is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 11 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
12 | any later version. |
13 | ||
14 | GAS is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
21 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
22 | 02110-1301, USA. */ | |
252b5132 | 23 | |
47926f60 KH |
24 | /* Intel 80386 machine specific gas. |
25 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 26 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 27 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
28 | Bugs & suggestions are completely welcome. This is free software. |
29 | Please help us make it better. */ | |
252b5132 | 30 | |
252b5132 | 31 | #include "as.h" |
3882b010 | 32 | #include "safe-ctype.h" |
252b5132 | 33 | #include "subsegs.h" |
316e2c05 | 34 | #include "dwarf2dbg.h" |
54cfded0 | 35 | #include "dw2gencfi.h" |
d2b2c203 | 36 | #include "elf/x86-64.h" |
40fb9820 | 37 | #include "opcodes/i386-init.h" |
252b5132 | 38 | |
252b5132 RH |
39 | #ifndef REGISTER_WARNINGS |
40 | #define REGISTER_WARNINGS 1 | |
41 | #endif | |
42 | ||
c3332e24 | 43 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 44 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
45 | #endif |
46 | ||
29b0f896 AM |
47 | #ifndef DEFAULT_ARCH |
48 | #define DEFAULT_ARCH "i386" | |
246fcdee | 49 | #endif |
252b5132 | 50 | |
edde18a5 AM |
51 | #ifndef INLINE |
52 | #if __GNUC__ >= 2 | |
53 | #define INLINE __inline__ | |
54 | #else | |
55 | #define INLINE | |
56 | #endif | |
57 | #endif | |
58 | ||
6305a203 L |
59 | /* Prefixes will be emitted in the order defined below. |
60 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
61 | instruction, and so must come before any prefixes. | |
62 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
42164a71 | 63 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
6305a203 L |
64 | #define WAIT_PREFIX 0 |
65 | #define SEG_PREFIX 1 | |
66 | #define ADDR_PREFIX 2 | |
67 | #define DATA_PREFIX 3 | |
c32fa91d | 68 | #define REP_PREFIX 4 |
42164a71 | 69 | #define HLE_PREFIX REP_PREFIX |
c32fa91d L |
70 | #define LOCK_PREFIX 5 |
71 | #define REX_PREFIX 6 /* must come last. */ | |
72 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ | |
6305a203 L |
73 | |
74 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
75 | #define REGISTER_PREFIX '%' | |
76 | #define IMMEDIATE_PREFIX '$' | |
77 | #define ABSOLUTE_PREFIX '*' | |
78 | ||
79 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
80 | memory operand size in Intel syntax. */ | |
81 | #define WORD_MNEM_SUFFIX 'w' | |
82 | #define BYTE_MNEM_SUFFIX 'b' | |
83 | #define SHORT_MNEM_SUFFIX 's' | |
84 | #define LONG_MNEM_SUFFIX 'l' | |
85 | #define QWORD_MNEM_SUFFIX 'q' | |
86 | #define XMMWORD_MNEM_SUFFIX 'x' | |
c0f3af97 | 87 | #define YMMWORD_MNEM_SUFFIX 'y' |
6305a203 L |
88 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
89 | in instructions. */ | |
90 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' | |
91 | ||
92 | #define END_OF_INSN '\0' | |
93 | ||
94 | /* | |
95 | 'templates' is for grouping together 'template' structures for opcodes | |
96 | of the same name. This is only used for storing the insns in the grand | |
97 | ole hash table of insns. | |
98 | The templates themselves start at START and range up to (but not including) | |
99 | END. | |
100 | */ | |
101 | typedef struct | |
102 | { | |
d3ce72d0 NC |
103 | const insn_template *start; |
104 | const insn_template *end; | |
6305a203 L |
105 | } |
106 | templates; | |
107 | ||
108 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
109 | typedef struct | |
110 | { | |
111 | unsigned int regmem; /* codes register or memory operand */ | |
112 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
113 | unsigned int mode; /* how to interpret regmem & reg */ | |
114 | } | |
115 | modrm_byte; | |
116 | ||
117 | /* x86-64 extension prefix. */ | |
118 | typedef int rex_byte; | |
119 | ||
6305a203 L |
120 | /* 386 opcode byte to code indirect addressing. */ |
121 | typedef struct | |
122 | { | |
123 | unsigned base; | |
124 | unsigned index; | |
125 | unsigned scale; | |
126 | } | |
127 | sib_byte; | |
128 | ||
6305a203 L |
129 | /* x86 arch names, types and features */ |
130 | typedef struct | |
131 | { | |
132 | const char *name; /* arch name */ | |
8a2c8fef | 133 | unsigned int len; /* arch string length */ |
6305a203 L |
134 | enum processor_type type; /* arch type */ |
135 | i386_cpu_flags flags; /* cpu feature flags */ | |
8a2c8fef | 136 | unsigned int skip; /* show_arch should skip this. */ |
22109423 | 137 | unsigned int negated; /* turn off indicated flags. */ |
6305a203 L |
138 | } |
139 | arch_entry; | |
140 | ||
78f12dd3 | 141 | static void update_code_flag (int, int); |
e3bb37b5 L |
142 | static void set_code_flag (int); |
143 | static void set_16bit_gcc_code_flag (int); | |
144 | static void set_intel_syntax (int); | |
1efbbeb4 | 145 | static void set_intel_mnemonic (int); |
db51cc60 | 146 | static void set_allow_index_reg (int); |
7bab8ab5 | 147 | static void set_check (int); |
e3bb37b5 | 148 | static void set_cpu_arch (int); |
6482c264 | 149 | #ifdef TE_PE |
e3bb37b5 | 150 | static void pe_directive_secrel (int); |
6482c264 | 151 | #endif |
e3bb37b5 L |
152 | static void signed_cons (int); |
153 | static char *output_invalid (int c); | |
ee86248c JB |
154 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
155 | const char *); | |
156 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
157 | const char *); | |
a7619375 | 158 | static int i386_att_operand (char *); |
e3bb37b5 | 159 | static int i386_intel_operand (char *, int); |
ee86248c JB |
160 | static int i386_intel_simplify (expressionS *); |
161 | static int i386_intel_parse_name (const char *, expressionS *); | |
e3bb37b5 L |
162 | static const reg_entry *parse_register (char *, char **); |
163 | static char *parse_insn (char *, char *); | |
164 | static char *parse_operands (char *, const char *); | |
165 | static void swap_operands (void); | |
4d456e3d | 166 | static void swap_2_operands (int, int); |
e3bb37b5 L |
167 | static void optimize_imm (void); |
168 | static void optimize_disp (void); | |
d3ce72d0 | 169 | static const insn_template *match_template (void); |
e3bb37b5 L |
170 | static int check_string (void); |
171 | static int process_suffix (void); | |
172 | static int check_byte_reg (void); | |
173 | static int check_long_reg (void); | |
174 | static int check_qword_reg (void); | |
175 | static int check_word_reg (void); | |
176 | static int finalize_imm (void); | |
177 | static int process_operands (void); | |
178 | static const seg_entry *build_modrm_byte (void); | |
179 | static void output_insn (void); | |
180 | static void output_imm (fragS *, offsetT); | |
181 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 182 | #ifndef I386COFF |
e3bb37b5 | 183 | static void s_bss (int); |
252b5132 | 184 | #endif |
17d4e2a2 L |
185 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
186 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
187 | #endif | |
252b5132 | 188 | |
a847613f | 189 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 190 | |
c0f3af97 L |
191 | /* VEX prefix. */ |
192 | typedef struct | |
193 | { | |
194 | /* VEX prefix is either 2 byte or 3 byte. */ | |
195 | unsigned char bytes[3]; | |
196 | unsigned int length; | |
197 | /* Destination or source register specifier. */ | |
198 | const reg_entry *register_specifier; | |
199 | } vex_prefix; | |
200 | ||
252b5132 | 201 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 202 | i386_insn. */ |
252b5132 | 203 | |
520dc8e8 AM |
204 | union i386_op |
205 | { | |
206 | expressionS *disps; | |
207 | expressionS *imms; | |
208 | const reg_entry *regs; | |
209 | }; | |
210 | ||
a65babc9 L |
211 | enum i386_error |
212 | { | |
86e026a4 | 213 | operand_size_mismatch, |
a65babc9 L |
214 | operand_type_mismatch, |
215 | register_type_mismatch, | |
216 | number_of_operands_mismatch, | |
217 | invalid_instruction_suffix, | |
218 | bad_imm4, | |
219 | old_gcc_only, | |
220 | unsupported_with_intel_mnemonic, | |
221 | unsupported_syntax, | |
6c30d220 L |
222 | unsupported, |
223 | invalid_vsib_address, | |
7bab8ab5 | 224 | invalid_vector_register_set, |
6c30d220 | 225 | unsupported_vector_index_register |
a65babc9 L |
226 | }; |
227 | ||
252b5132 RH |
228 | struct _i386_insn |
229 | { | |
47926f60 | 230 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 231 | insn_template tm; |
252b5132 | 232 | |
7d5e4556 L |
233 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
234 | or qword, if given. */ | |
252b5132 RH |
235 | char suffix; |
236 | ||
47926f60 | 237 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
238 | unsigned int operands; |
239 | ||
240 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
241 | of given register, displacement, memory operands and immediate | |
47926f60 | 242 | operands. */ |
252b5132 RH |
243 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
244 | ||
245 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 246 | use OP[i] for the corresponding operand. */ |
40fb9820 | 247 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 248 | |
520dc8e8 AM |
249 | /* Displacement expression, immediate expression, or register for each |
250 | operand. */ | |
251 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 252 | |
3e73aa7c JH |
253 | /* Flags for operands. */ |
254 | unsigned int flags[MAX_OPERANDS]; | |
255 | #define Operand_PCrel 1 | |
256 | ||
252b5132 | 257 | /* Relocation type for operand */ |
f86103b7 | 258 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 259 | |
252b5132 RH |
260 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
261 | the base index byte below. */ | |
262 | const reg_entry *base_reg; | |
263 | const reg_entry *index_reg; | |
264 | unsigned int log2_scale_factor; | |
265 | ||
266 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 267 | explicit segment overrides are given. */ |
ce8a8b2f | 268 | const seg_entry *seg[2]; |
252b5132 RH |
269 | |
270 | /* PREFIX holds all the given prefix opcodes (usually null). | |
271 | PREFIXES is the number of prefix opcodes. */ | |
272 | unsigned int prefixes; | |
273 | unsigned char prefix[MAX_PREFIXES]; | |
274 | ||
275 | /* RM and SIB are the modrm byte and the sib byte where the | |
c1e679ec | 276 | addressing modes of this insn are encoded. */ |
252b5132 | 277 | modrm_byte rm; |
3e73aa7c | 278 | rex_byte rex; |
252b5132 | 279 | sib_byte sib; |
c0f3af97 | 280 | vex_prefix vex; |
b6169b20 L |
281 | |
282 | /* Swap operand in encoding. */ | |
4473e004 | 283 | unsigned int swap_operand; |
891edac4 | 284 | |
a501d77e L |
285 | /* Prefer 8bit or 32bit displacement in encoding. */ |
286 | enum | |
287 | { | |
288 | disp_encoding_default = 0, | |
289 | disp_encoding_8bit, | |
290 | disp_encoding_32bit | |
291 | } disp_encoding; | |
f8a5c266 | 292 | |
42164a71 L |
293 | /* Have HLE prefix. */ |
294 | unsigned int have_hle; | |
295 | ||
891edac4 | 296 | /* Error message. */ |
a65babc9 | 297 | enum i386_error error; |
252b5132 RH |
298 | }; |
299 | ||
300 | typedef struct _i386_insn i386_insn; | |
301 | ||
302 | /* List of chars besides those in app.c:symbol_chars that can start an | |
303 | operand. Used to prevent the scrubber eating vital white-space. */ | |
32137342 | 304 | const char extra_symbol_chars[] = "*%-([" |
252b5132 | 305 | #ifdef LEX_AT |
32137342 NC |
306 | "@" |
307 | #endif | |
308 | #ifdef LEX_QM | |
309 | "?" | |
252b5132 | 310 | #endif |
32137342 | 311 | ; |
252b5132 | 312 | |
29b0f896 AM |
313 | #if (defined (TE_I386AIX) \ |
314 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
3896cfd5 | 315 | && !defined (TE_GNU) \ |
29b0f896 | 316 | && !defined (TE_LINUX) \ |
8d63c93e RM |
317 | && !defined (TE_NACL) \ |
318 | && !defined (TE_NETWARE) \ | |
29b0f896 | 319 | && !defined (TE_FreeBSD) \ |
5b806d27 | 320 | && !defined (TE_DragonFly) \ |
29b0f896 | 321 | && !defined (TE_NetBSD))) |
252b5132 | 322 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
323 | pre-processor is disabled, these aren't very useful. The option |
324 | --divide will remove '/' from this list. */ | |
325 | const char *i386_comment_chars = "#/"; | |
326 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 327 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 328 | |
b3b91714 AM |
329 | #else |
330 | const char *i386_comment_chars = "#"; | |
331 | #define PREFIX_SEPARATOR '/' | |
332 | #endif | |
333 | ||
252b5132 RH |
334 | /* This array holds the chars that only start a comment at the beginning of |
335 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
336 | .line and .file directives will appear in the pre-processed output. |
337 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 338 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
339 | #NO_APP at the beginning of its output. |
340 | Also note that comments started like this one will always work if | |
252b5132 | 341 | '/' isn't otherwise defined. */ |
b3b91714 | 342 | const char line_comment_chars[] = "#/"; |
252b5132 | 343 | |
63a0b638 | 344 | const char line_separator_chars[] = ";"; |
252b5132 | 345 | |
ce8a8b2f AM |
346 | /* Chars that can be used to separate mant from exp in floating point |
347 | nums. */ | |
252b5132 RH |
348 | const char EXP_CHARS[] = "eE"; |
349 | ||
ce8a8b2f AM |
350 | /* Chars that mean this number is a floating point constant |
351 | As in 0f12.456 | |
352 | or 0d1.2345e12. */ | |
252b5132 RH |
353 | const char FLT_CHARS[] = "fFdDxX"; |
354 | ||
ce8a8b2f | 355 | /* Tables for lexical analysis. */ |
252b5132 RH |
356 | static char mnemonic_chars[256]; |
357 | static char register_chars[256]; | |
358 | static char operand_chars[256]; | |
359 | static char identifier_chars[256]; | |
360 | static char digit_chars[256]; | |
361 | ||
ce8a8b2f | 362 | /* Lexical macros. */ |
252b5132 RH |
363 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
364 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
365 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
366 | #define is_space_char(x) ((x) == ' ') | |
367 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
368 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
369 | ||
0234cb7c | 370 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
371 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
372 | ||
373 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
374 | effect this we maintain a stack of saved characters that we've smashed | |
375 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 376 | assembler instruction). */ |
252b5132 | 377 | static char save_stack[32]; |
ce8a8b2f | 378 | static char *save_stack_p; |
252b5132 RH |
379 | #define END_STRING_AND_SAVE(s) \ |
380 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
381 | #define RESTORE_END_STRING(s) \ | |
382 | do { *(s) = *--save_stack_p; } while (0) | |
383 | ||
47926f60 | 384 | /* The instruction we're assembling. */ |
252b5132 RH |
385 | static i386_insn i; |
386 | ||
387 | /* Possible templates for current insn. */ | |
388 | static const templates *current_templates; | |
389 | ||
31b2323c L |
390 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
391 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
392 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 393 | |
47926f60 | 394 | /* Current operand we are working on. */ |
ee86248c | 395 | static int this_operand = -1; |
252b5132 | 396 | |
3e73aa7c JH |
397 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
398 | these. */ | |
399 | ||
400 | enum flag_code { | |
401 | CODE_32BIT, | |
402 | CODE_16BIT, | |
403 | CODE_64BIT }; | |
404 | ||
405 | static enum flag_code flag_code; | |
4fa24527 | 406 | static unsigned int object_64bit; |
862be3fb | 407 | static unsigned int disallow_64bit_reloc; |
3e73aa7c JH |
408 | static int use_rela_relocations = 0; |
409 | ||
7af8ed2d NC |
410 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
411 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ | |
412 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) | |
413 | ||
351f65ca L |
414 | /* The ELF ABI to use. */ |
415 | enum x86_elf_abi | |
416 | { | |
417 | I386_ABI, | |
7f56bc95 L |
418 | X86_64_ABI, |
419 | X86_64_X32_ABI | |
351f65ca L |
420 | }; |
421 | ||
422 | static enum x86_elf_abi x86_elf_abi = I386_ABI; | |
7af8ed2d | 423 | #endif |
351f65ca | 424 | |
3e73aa7c | 425 | /* The names used to print error messages. */ |
b77a7acd | 426 | static const char *flag_code_names[] = |
3e73aa7c JH |
427 | { |
428 | "32", | |
429 | "16", | |
430 | "64" | |
431 | }; | |
252b5132 | 432 | |
47926f60 KH |
433 | /* 1 for intel syntax, |
434 | 0 if att syntax. */ | |
435 | static int intel_syntax = 0; | |
252b5132 | 436 | |
1efbbeb4 L |
437 | /* 1 for intel mnemonic, |
438 | 0 if att mnemonic. */ | |
439 | static int intel_mnemonic = !SYSV386_COMPAT; | |
440 | ||
5209009a | 441 | /* 1 if support old (<= 2.8.1) versions of gcc. */ |
1efbbeb4 L |
442 | static int old_gcc = OLDGCC_COMPAT; |
443 | ||
a60de03c JB |
444 | /* 1 if pseudo registers are permitted. */ |
445 | static int allow_pseudo_reg = 0; | |
446 | ||
47926f60 KH |
447 | /* 1 if register prefix % not required. */ |
448 | static int allow_naked_reg = 0; | |
252b5132 | 449 | |
ba104c83 | 450 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
451 | static int allow_index_reg = 0; |
452 | ||
7bab8ab5 | 453 | static enum check_kind |
daf50ae7 | 454 | { |
7bab8ab5 JB |
455 | check_none = 0, |
456 | check_warning, | |
457 | check_error | |
daf50ae7 | 458 | } |
7bab8ab5 | 459 | sse_check, operand_check = check_warning; |
daf50ae7 | 460 | |
2ca3ace5 L |
461 | /* Register prefix used for error message. */ |
462 | static const char *register_prefix = "%"; | |
463 | ||
47926f60 KH |
464 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
465 | leave, push, and pop instructions so that gcc has the same stack | |
466 | frame as in 32 bit mode. */ | |
467 | static char stackop_size = '\0'; | |
eecb386c | 468 | |
12b55ccc L |
469 | /* Non-zero to optimize code alignment. */ |
470 | int optimize_align_code = 1; | |
471 | ||
47926f60 KH |
472 | /* Non-zero to quieten some warnings. */ |
473 | static int quiet_warnings = 0; | |
a38cf1db | 474 | |
47926f60 KH |
475 | /* CPU name. */ |
476 | static const char *cpu_arch_name = NULL; | |
6305a203 | 477 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 478 | |
47926f60 | 479 | /* CPU feature flags. */ |
40fb9820 L |
480 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
481 | ||
ccc9c027 L |
482 | /* If we have selected a cpu we are generating instructions for. */ |
483 | static int cpu_arch_tune_set = 0; | |
484 | ||
9103f4f4 | 485 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 486 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 L |
487 | |
488 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 489 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 490 | |
ccc9c027 | 491 | /* CPU instruction set architecture used. */ |
fbf3f584 | 492 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 493 | |
9103f4f4 | 494 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 495 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 496 | |
fddf5b5b AM |
497 | /* If set, conditional jumps are not automatically promoted to handle |
498 | larger than a byte offset. */ | |
499 | static unsigned int no_cond_jump_promotion = 0; | |
500 | ||
c0f3af97 L |
501 | /* Encode SSE instructions with VEX prefix. */ |
502 | static unsigned int sse2avx; | |
503 | ||
539f890d L |
504 | /* Encode scalar AVX instructions with specific vector length. */ |
505 | static enum | |
506 | { | |
507 | vex128 = 0, | |
508 | vex256 | |
509 | } avxscalar; | |
510 | ||
29b0f896 | 511 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 512 | static symbolS *GOT_symbol; |
29b0f896 | 513 | |
a4447b93 RH |
514 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
515 | unsigned int x86_dwarf2_return_column; | |
516 | ||
517 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
518 | int x86_cie_data_alignment; | |
519 | ||
252b5132 | 520 | /* Interface to relax_segment. |
fddf5b5b AM |
521 | There are 3 major relax states for 386 jump insns because the |
522 | different types of jumps add different sizes to frags when we're | |
523 | figuring out what sort of jump to choose to reach a given label. */ | |
252b5132 | 524 | |
47926f60 | 525 | /* Types. */ |
93c2a809 AM |
526 | #define UNCOND_JUMP 0 |
527 | #define COND_JUMP 1 | |
528 | #define COND_JUMP86 2 | |
fddf5b5b | 529 | |
47926f60 | 530 | /* Sizes. */ |
252b5132 RH |
531 | #define CODE16 1 |
532 | #define SMALL 0 | |
29b0f896 | 533 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 534 | #define BIG 2 |
29b0f896 | 535 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
536 | |
537 | #ifndef INLINE | |
538 | #ifdef __GNUC__ | |
539 | #define INLINE __inline__ | |
540 | #else | |
541 | #define INLINE | |
542 | #endif | |
543 | #endif | |
544 | ||
fddf5b5b AM |
545 | #define ENCODE_RELAX_STATE(type, size) \ |
546 | ((relax_substateT) (((type) << 2) | (size))) | |
547 | #define TYPE_FROM_RELAX_STATE(s) \ | |
548 | ((s) >> 2) | |
549 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
550 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
551 | |
552 | /* This table is used by relax_frag to promote short jumps to long | |
553 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
554 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
555 | don't allow a short jump in a 32 bit code segment to be promoted to | |
556 | a 16 bit offset jump because it's slower (requires data size | |
557 | prefix), and doesn't work, unless the destination is in the bottom | |
558 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
559 | ||
560 | const relax_typeS md_relax_table[] = | |
561 | { | |
24eab124 AM |
562 | /* The fields are: |
563 | 1) most positive reach of this state, | |
564 | 2) most negative reach of this state, | |
93c2a809 | 565 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 566 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 567 | |
fddf5b5b | 568 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
569 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
570 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
571 | /* dword jmp adds 4 bytes to frag: | |
572 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 573 | {0, 0, 4, 0}, |
93c2a809 AM |
574 | /* word jmp adds 2 byte2 to frag: |
575 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
576 | {0, 0, 2, 0}, |
577 | ||
93c2a809 AM |
578 | /* COND_JUMP states. */ |
579 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
580 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
581 | /* dword conditionals adds 5 bytes to frag: | |
582 | 1 extra opcode byte, 4 displacement bytes. */ | |
583 | {0, 0, 5, 0}, | |
fddf5b5b | 584 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
585 | 1 extra opcode byte, 2 displacement bytes. */ |
586 | {0, 0, 3, 0}, | |
587 | ||
588 | /* COND_JUMP86 states. */ | |
589 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
590 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
591 | /* dword conditionals adds 5 bytes to frag: | |
592 | 1 extra opcode byte, 4 displacement bytes. */ | |
593 | {0, 0, 5, 0}, | |
594 | /* word conditionals add 4 bytes to frag: | |
595 | 1 displacement byte and a 3 byte long branch insn. */ | |
596 | {0, 0, 4, 0} | |
252b5132 RH |
597 | }; |
598 | ||
9103f4f4 L |
599 | static const arch_entry cpu_arch[] = |
600 | { | |
89507696 JB |
601 | /* Do not replace the first two entries - i386_target_format() |
602 | relies on them being there in this order. */ | |
8a2c8fef | 603 | { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, |
22109423 | 604 | CPU_GENERIC32_FLAGS, 0, 0 }, |
8a2c8fef | 605 | { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, |
22109423 | 606 | CPU_GENERIC64_FLAGS, 0, 0 }, |
8a2c8fef | 607 | { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, |
22109423 | 608 | CPU_NONE_FLAGS, 0, 0 }, |
8a2c8fef | 609 | { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, |
22109423 | 610 | CPU_I186_FLAGS, 0, 0 }, |
8a2c8fef | 611 | { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, |
22109423 | 612 | CPU_I286_FLAGS, 0, 0 }, |
8a2c8fef | 613 | { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, |
22109423 | 614 | CPU_I386_FLAGS, 0, 0 }, |
8a2c8fef | 615 | { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, |
22109423 | 616 | CPU_I486_FLAGS, 0, 0 }, |
8a2c8fef | 617 | { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, |
22109423 | 618 | CPU_I586_FLAGS, 0, 0 }, |
8a2c8fef | 619 | { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, |
22109423 | 620 | CPU_I686_FLAGS, 0, 0 }, |
8a2c8fef | 621 | { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, |
22109423 | 622 | CPU_I586_FLAGS, 0, 0 }, |
8a2c8fef | 623 | { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, |
22109423 | 624 | CPU_PENTIUMPRO_FLAGS, 0, 0 }, |
8a2c8fef | 625 | { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, |
22109423 | 626 | CPU_P2_FLAGS, 0, 0 }, |
8a2c8fef | 627 | { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, |
22109423 | 628 | CPU_P3_FLAGS, 0, 0 }, |
8a2c8fef | 629 | { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, |
22109423 | 630 | CPU_P4_FLAGS, 0, 0 }, |
8a2c8fef | 631 | { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, |
22109423 | 632 | CPU_CORE_FLAGS, 0, 0 }, |
8a2c8fef | 633 | { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, |
22109423 | 634 | CPU_NOCONA_FLAGS, 0, 0 }, |
8a2c8fef | 635 | { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, |
22109423 | 636 | CPU_CORE_FLAGS, 1, 0 }, |
8a2c8fef | 637 | { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, |
22109423 | 638 | CPU_CORE_FLAGS, 0, 0 }, |
8a2c8fef | 639 | { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, |
22109423 | 640 | CPU_CORE2_FLAGS, 1, 0 }, |
8a2c8fef | 641 | { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, |
22109423 | 642 | CPU_CORE2_FLAGS, 0, 0 }, |
8a2c8fef | 643 | { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, |
22109423 | 644 | CPU_COREI7_FLAGS, 0, 0 }, |
8a2c8fef | 645 | { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, |
22109423 | 646 | CPU_L1OM_FLAGS, 0, 0 }, |
7a9068fe L |
647 | { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, |
648 | CPU_K1OM_FLAGS, 0, 0 }, | |
8a2c8fef | 649 | { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, |
22109423 | 650 | CPU_K6_FLAGS, 0, 0 }, |
8a2c8fef | 651 | { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, |
22109423 | 652 | CPU_K6_2_FLAGS, 0, 0 }, |
8a2c8fef | 653 | { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, |
22109423 | 654 | CPU_ATHLON_FLAGS, 0, 0 }, |
8a2c8fef | 655 | { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, |
22109423 | 656 | CPU_K8_FLAGS, 1, 0 }, |
8a2c8fef | 657 | { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, |
22109423 | 658 | CPU_K8_FLAGS, 0, 0 }, |
8a2c8fef | 659 | { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, |
22109423 | 660 | CPU_K8_FLAGS, 0, 0 }, |
8a2c8fef | 661 | { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, |
22109423 | 662 | CPU_AMDFAM10_FLAGS, 0, 0 }, |
8aedb9fe | 663 | { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, |
22109423 | 664 | CPU_BDVER1_FLAGS, 0, 0 }, |
8aedb9fe | 665 | { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, |
af2f724e | 666 | CPU_BDVER2_FLAGS, 0, 0 }, |
5e5c50d3 NE |
667 | { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD, |
668 | CPU_BDVER3_FLAGS, 0, 0 }, | |
7b458c12 L |
669 | { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, |
670 | CPU_BTVER1_FLAGS, 0, 0 }, | |
671 | { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, | |
672 | CPU_BTVER2_FLAGS, 0, 0 }, | |
8a2c8fef | 673 | { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, |
22109423 | 674 | CPU_8087_FLAGS, 0, 0 }, |
8a2c8fef | 675 | { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, |
22109423 | 676 | CPU_287_FLAGS, 0, 0 }, |
8a2c8fef | 677 | { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, |
22109423 | 678 | CPU_387_FLAGS, 0, 0 }, |
8a2c8fef | 679 | { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN, |
22109423 | 680 | CPU_ANY87_FLAGS, 0, 1 }, |
8a2c8fef | 681 | { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, |
22109423 | 682 | CPU_MMX_FLAGS, 0, 0 }, |
8a2c8fef | 683 | { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN, |
22109423 | 684 | CPU_3DNOWA_FLAGS, 0, 1 }, |
8a2c8fef | 685 | { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, |
22109423 | 686 | CPU_SSE_FLAGS, 0, 0 }, |
8a2c8fef | 687 | { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, |
22109423 | 688 | CPU_SSE2_FLAGS, 0, 0 }, |
8a2c8fef | 689 | { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, |
22109423 | 690 | CPU_SSE3_FLAGS, 0, 0 }, |
8a2c8fef | 691 | { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, |
22109423 | 692 | CPU_SSSE3_FLAGS, 0, 0 }, |
8a2c8fef | 693 | { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, |
22109423 | 694 | CPU_SSE4_1_FLAGS, 0, 0 }, |
8a2c8fef | 695 | { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, |
22109423 | 696 | CPU_SSE4_2_FLAGS, 0, 0 }, |
8a2c8fef | 697 | { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, |
22109423 | 698 | CPU_SSE4_2_FLAGS, 0, 0 }, |
8a2c8fef | 699 | { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN, |
22109423 | 700 | CPU_ANY_SSE_FLAGS, 0, 1 }, |
8a2c8fef | 701 | { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, |
22109423 | 702 | CPU_AVX_FLAGS, 0, 0 }, |
6c30d220 L |
703 | { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, |
704 | CPU_AVX2_FLAGS, 0, 0 }, | |
8a2c8fef | 705 | { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN, |
22109423 | 706 | CPU_ANY_AVX_FLAGS, 0, 1 }, |
8a2c8fef | 707 | { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, |
22109423 | 708 | CPU_VMX_FLAGS, 0, 0 }, |
8729a6f6 L |
709 | { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, |
710 | CPU_VMFUNC_FLAGS, 0, 0 }, | |
8a2c8fef | 711 | { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, |
22109423 | 712 | CPU_SMX_FLAGS, 0, 0 }, |
8a2c8fef | 713 | { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, |
22109423 | 714 | CPU_XSAVE_FLAGS, 0, 0 }, |
c7b8aa3a | 715 | { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, |
22109423 | 716 | CPU_XSAVEOPT_FLAGS, 0, 0 }, |
8a2c8fef | 717 | { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, |
22109423 | 718 | CPU_AES_FLAGS, 0, 0 }, |
8a2c8fef | 719 | { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, |
22109423 | 720 | CPU_PCLMUL_FLAGS, 0, 0 }, |
8a2c8fef | 721 | { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, |
22109423 | 722 | CPU_PCLMUL_FLAGS, 1, 0 }, |
c7b8aa3a | 723 | { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, |
22109423 | 724 | CPU_FSGSBASE_FLAGS, 0, 0 }, |
c7b8aa3a | 725 | { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, |
22109423 | 726 | CPU_RDRND_FLAGS, 0, 0 }, |
c7b8aa3a | 727 | { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, |
22109423 | 728 | CPU_F16C_FLAGS, 0, 0 }, |
6c30d220 L |
729 | { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, |
730 | CPU_BMI2_FLAGS, 0, 0 }, | |
8a2c8fef | 731 | { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, |
22109423 | 732 | CPU_FMA_FLAGS, 0, 0 }, |
8a2c8fef | 733 | { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, |
22109423 | 734 | CPU_FMA4_FLAGS, 0, 0 }, |
8a2c8fef | 735 | { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, |
22109423 | 736 | CPU_XOP_FLAGS, 0, 0 }, |
8a2c8fef | 737 | { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, |
22109423 | 738 | CPU_LWP_FLAGS, 0, 0 }, |
8a2c8fef | 739 | { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, |
22109423 | 740 | CPU_MOVBE_FLAGS, 0, 0 }, |
60aa667e L |
741 | { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN, |
742 | CPU_CX16_FLAGS, 0, 0 }, | |
8a2c8fef | 743 | { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, |
22109423 | 744 | CPU_EPT_FLAGS, 0, 0 }, |
6c30d220 L |
745 | { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, |
746 | CPU_LZCNT_FLAGS, 0, 0 }, | |
42164a71 L |
747 | { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, |
748 | CPU_HLE_FLAGS, 0, 0 }, | |
749 | { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, | |
750 | CPU_RTM_FLAGS, 0, 0 }, | |
6c30d220 L |
751 | { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, |
752 | CPU_INVPCID_FLAGS, 0, 0 }, | |
8a2c8fef | 753 | { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, |
22109423 L |
754 | CPU_CLFLUSH_FLAGS, 0, 0 }, |
755 | { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, | |
756 | CPU_NOP_FLAGS, 0, 0 }, | |
8a2c8fef | 757 | { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, |
22109423 | 758 | CPU_SYSCALL_FLAGS, 0, 0 }, |
8a2c8fef | 759 | { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, |
22109423 | 760 | CPU_RDTSCP_FLAGS, 0, 0 }, |
8a2c8fef | 761 | { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, |
22109423 | 762 | CPU_3DNOW_FLAGS, 0, 0 }, |
8a2c8fef | 763 | { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, |
22109423 | 764 | CPU_3DNOWA_FLAGS, 0, 0 }, |
8a2c8fef | 765 | { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, |
22109423 | 766 | CPU_PADLOCK_FLAGS, 0, 0 }, |
8a2c8fef | 767 | { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, |
22109423 | 768 | CPU_SVME_FLAGS, 1, 0 }, |
8a2c8fef | 769 | { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, |
22109423 | 770 | CPU_SVME_FLAGS, 0, 0 }, |
8a2c8fef | 771 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
22109423 | 772 | CPU_SSE4A_FLAGS, 0, 0 }, |
8a2c8fef | 773 | { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, |
22109423 | 774 | CPU_ABM_FLAGS, 0, 0 }, |
87973e9f QN |
775 | { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, |
776 | CPU_BMI_FLAGS, 0, 0 }, | |
2a2a0f38 QN |
777 | { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, |
778 | CPU_TBM_FLAGS, 0, 0 }, | |
e2e1fcde L |
779 | { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, |
780 | CPU_ADX_FLAGS, 0, 0 }, | |
781 | { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, | |
782 | CPU_RDSEED_FLAGS, 0, 0 }, | |
783 | { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, | |
784 | CPU_PRFCHW_FLAGS, 0, 0 }, | |
e413e4e9 AM |
785 | }; |
786 | ||
704209c0 | 787 | #ifdef I386COFF |
a6c24e68 NC |
788 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
789 | is allowed to be optional. */ | |
790 | ||
791 | static symbolS * | |
792 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
793 | { | |
794 | addressT align = 0; | |
795 | ||
796 | SKIP_WHITESPACE (); | |
797 | ||
7ab9ffdd | 798 | if (needs_align |
a6c24e68 NC |
799 | && *input_line_pointer == ',') |
800 | { | |
801 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 802 | |
a6c24e68 NC |
803 | if (align == (addressT) -1) |
804 | return NULL; | |
805 | } | |
806 | else | |
807 | { | |
808 | if (size >= 8) | |
809 | align = 3; | |
810 | else if (size >= 4) | |
811 | align = 2; | |
812 | else if (size >= 2) | |
813 | align = 1; | |
814 | else | |
815 | align = 0; | |
816 | } | |
817 | ||
818 | bss_alloc (symbolP, size, align); | |
819 | return symbolP; | |
820 | } | |
821 | ||
704209c0 | 822 | static void |
a6c24e68 NC |
823 | pe_lcomm (int needs_align) |
824 | { | |
825 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
826 | } | |
704209c0 | 827 | #endif |
a6c24e68 | 828 | |
29b0f896 AM |
829 | const pseudo_typeS md_pseudo_table[] = |
830 | { | |
831 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
832 | {"align", s_align_bytes, 0}, | |
833 | #else | |
834 | {"align", s_align_ptwo, 0}, | |
835 | #endif | |
836 | {"arch", set_cpu_arch, 0}, | |
837 | #ifndef I386COFF | |
838 | {"bss", s_bss, 0}, | |
a6c24e68 NC |
839 | #else |
840 | {"lcomm", pe_lcomm, 1}, | |
29b0f896 AM |
841 | #endif |
842 | {"ffloat", float_cons, 'f'}, | |
843 | {"dfloat", float_cons, 'd'}, | |
844 | {"tfloat", float_cons, 'x'}, | |
845 | {"value", cons, 2}, | |
d182319b | 846 | {"slong", signed_cons, 4}, |
29b0f896 AM |
847 | {"noopt", s_ignore, 0}, |
848 | {"optim", s_ignore, 0}, | |
849 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
850 | {"code16", set_code_flag, CODE_16BIT}, | |
851 | {"code32", set_code_flag, CODE_32BIT}, | |
852 | {"code64", set_code_flag, CODE_64BIT}, | |
853 | {"intel_syntax", set_intel_syntax, 1}, | |
854 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
855 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
856 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
857 | {"allow_index_reg", set_allow_index_reg, 1}, |
858 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
7bab8ab5 JB |
859 | {"sse_check", set_check, 0}, |
860 | {"operand_check", set_check, 1}, | |
3b22753a L |
861 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
862 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 863 | #else |
e3bb37b5 | 864 | {"file", (void (*) (int)) dwarf2_directive_file, 0}, |
07a53e5c RH |
865 | {"loc", dwarf2_directive_loc, 0}, |
866 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 867 | #endif |
6482c264 NC |
868 | #ifdef TE_PE |
869 | {"secrel32", pe_directive_secrel, 0}, | |
870 | #endif | |
29b0f896 AM |
871 | {0, 0, 0} |
872 | }; | |
873 | ||
874 | /* For interface with expression (). */ | |
875 | extern char *input_line_pointer; | |
876 | ||
877 | /* Hash table for instruction mnemonic lookup. */ | |
878 | static struct hash_control *op_hash; | |
879 | ||
880 | /* Hash table for register lookup. */ | |
881 | static struct hash_control *reg_hash; | |
882 | \f | |
252b5132 | 883 | void |
e3bb37b5 | 884 | i386_align_code (fragS *fragP, int count) |
252b5132 | 885 | { |
ce8a8b2f AM |
886 | /* Various efficient no-op patterns for aligning code labels. |
887 | Note: Don't try to assemble the instructions in the comments. | |
888 | 0L and 0w are not legal. */ | |
252b5132 RH |
889 | static const char f32_1[] = |
890 | {0x90}; /* nop */ | |
891 | static const char f32_2[] = | |
ccc9c027 | 892 | {0x66,0x90}; /* xchg %ax,%ax */ |
252b5132 RH |
893 | static const char f32_3[] = |
894 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
895 | static const char f32_4[] = | |
896 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
897 | static const char f32_5[] = | |
898 | {0x90, /* nop */ | |
899 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
900 | static const char f32_6[] = | |
901 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
902 | static const char f32_7[] = | |
903 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
904 | static const char f32_8[] = | |
905 | {0x90, /* nop */ | |
906 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
907 | static const char f32_9[] = | |
908 | {0x89,0xf6, /* movl %esi,%esi */ | |
909 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
910 | static const char f32_10[] = | |
911 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ | |
912 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
913 | static const char f32_11[] = | |
914 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ | |
915 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
916 | static const char f32_12[] = | |
917 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
918 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
919 | static const char f32_13[] = | |
920 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
921 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
922 | static const char f32_14[] = | |
923 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ | |
924 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
c3332e24 AM |
925 | static const char f16_3[] = |
926 | {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ | |
252b5132 RH |
927 | static const char f16_4[] = |
928 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
929 | static const char f16_5[] = | |
930 | {0x90, /* nop */ | |
931 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
932 | static const char f16_6[] = | |
933 | {0x89,0xf6, /* mov %si,%si */ | |
934 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
935 | static const char f16_7[] = | |
936 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ | |
937 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
938 | static const char f16_8[] = | |
939 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ | |
940 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
76bc74dc L |
941 | static const char jump_31[] = |
942 | {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */ | |
943 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, | |
944 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, | |
945 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
252b5132 RH |
946 | static const char *const f32_patt[] = { |
947 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, | |
76bc74dc | 948 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14 |
252b5132 RH |
949 | }; |
950 | static const char *const f16_patt[] = { | |
76bc74dc | 951 | f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8 |
252b5132 | 952 | }; |
ccc9c027 L |
953 | /* nopl (%[re]ax) */ |
954 | static const char alt_3[] = | |
955 | {0x0f,0x1f,0x00}; | |
956 | /* nopl 0(%[re]ax) */ | |
957 | static const char alt_4[] = | |
958 | {0x0f,0x1f,0x40,0x00}; | |
959 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
960 | static const char alt_5[] = | |
961 | {0x0f,0x1f,0x44,0x00,0x00}; | |
962 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
963 | static const char alt_6[] = | |
964 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
965 | /* nopl 0L(%[re]ax) */ | |
966 | static const char alt_7[] = | |
967 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
968 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
969 | static const char alt_8[] = | |
970 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
971 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
972 | static const char alt_9[] = | |
973 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
974 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
975 | static const char alt_10[] = | |
976 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
977 | /* data16 | |
978 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
979 | static const char alt_long_11[] = | |
980 | {0x66, | |
981 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
982 | /* data16 | |
983 | data16 | |
984 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
985 | static const char alt_long_12[] = | |
986 | {0x66, | |
987 | 0x66, | |
988 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
989 | /* data16 | |
990 | data16 | |
991 | data16 | |
992 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
993 | static const char alt_long_13[] = | |
994 | {0x66, | |
995 | 0x66, | |
996 | 0x66, | |
997 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
998 | /* data16 | |
999 | data16 | |
1000 | data16 | |
1001 | data16 | |
1002 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
1003 | static const char alt_long_14[] = | |
1004 | {0x66, | |
1005 | 0x66, | |
1006 | 0x66, | |
1007 | 0x66, | |
1008 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1009 | /* data16 | |
1010 | data16 | |
1011 | data16 | |
1012 | data16 | |
1013 | data16 | |
1014 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
1015 | static const char alt_long_15[] = | |
1016 | {0x66, | |
1017 | 0x66, | |
1018 | 0x66, | |
1019 | 0x66, | |
1020 | 0x66, | |
1021 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1022 | /* nopl 0(%[re]ax,%[re]ax,1) | |
1023 | nopw 0(%[re]ax,%[re]ax,1) */ | |
1024 | static const char alt_short_11[] = | |
1025 | {0x0f,0x1f,0x44,0x00,0x00, | |
1026 | 0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
1027 | /* nopw 0(%[re]ax,%[re]ax,1) | |
1028 | nopw 0(%[re]ax,%[re]ax,1) */ | |
1029 | static const char alt_short_12[] = | |
1030 | {0x66,0x0f,0x1f,0x44,0x00,0x00, | |
1031 | 0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
1032 | /* nopw 0(%[re]ax,%[re]ax,1) | |
1033 | nopl 0L(%[re]ax) */ | |
1034 | static const char alt_short_13[] = | |
1035 | {0x66,0x0f,0x1f,0x44,0x00,0x00, | |
1036 | 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
1037 | /* nopl 0L(%[re]ax) | |
1038 | nopl 0L(%[re]ax) */ | |
1039 | static const char alt_short_14[] = | |
1040 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00, | |
1041 | 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
1042 | /* nopl 0L(%[re]ax) | |
1043 | nopl 0L(%[re]ax,%[re]ax,1) */ | |
1044 | static const char alt_short_15[] = | |
1045 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00, | |
1046 | 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1047 | static const char *const alt_short_patt[] = { | |
1048 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
1049 | alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13, | |
1050 | alt_short_14, alt_short_15 | |
1051 | }; | |
1052 | static const char *const alt_long_patt[] = { | |
1053 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
1054 | alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13, | |
1055 | alt_long_14, alt_long_15 | |
1056 | }; | |
252b5132 | 1057 | |
76bc74dc L |
1058 | /* Only align for at least a positive non-zero boundary. */ |
1059 | if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE) | |
33fef721 | 1060 | return; |
3e73aa7c | 1061 | |
ccc9c027 L |
1062 | /* We need to decide which NOP sequence to use for 32bit and |
1063 | 64bit. When -mtune= is used: | |
4eed87de | 1064 | |
76bc74dc L |
1065 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
1066 | PROCESSOR_GENERIC32, f32_patt will be used. | |
1067 | 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA, | |
bd5295b2 L |
1068 | PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and |
1069 | PROCESSOR_GENERIC64, alt_long_patt will be used. | |
76bc74dc | 1070 | 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and |
7b458c12 | 1071 | PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt |
69dd9865 | 1072 | will be used. |
ccc9c027 | 1073 | |
76bc74dc | 1074 | When -mtune= isn't used, alt_long_patt will be used if |
22109423 | 1075 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will |
76bc74dc | 1076 | be used. |
ccc9c027 L |
1077 | |
1078 | When -march= or .arch is used, we can't use anything beyond | |
1079 | cpu_arch_isa_flags. */ | |
1080 | ||
1081 | if (flag_code == CODE_16BIT) | |
1082 | { | |
ccc9c027 | 1083 | if (count > 8) |
33fef721 | 1084 | { |
76bc74dc L |
1085 | memcpy (fragP->fr_literal + fragP->fr_fix, |
1086 | jump_31, count); | |
1087 | /* Adjust jump offset. */ | |
1088 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
252b5132 | 1089 | } |
76bc74dc L |
1090 | else |
1091 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1092 | f16_patt[count - 1], count); | |
252b5132 | 1093 | } |
33fef721 | 1094 | else |
ccc9c027 L |
1095 | { |
1096 | const char *const *patt = NULL; | |
1097 | ||
fbf3f584 | 1098 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 L |
1099 | { |
1100 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
1101 | switch (cpu_arch_tune) | |
1102 | { | |
1103 | case PROCESSOR_UNKNOWN: | |
1104 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
22109423 L |
1105 | optimize with nops. */ |
1106 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
76bc74dc | 1107 | patt = alt_long_patt; |
ccc9c027 L |
1108 | else |
1109 | patt = f32_patt; | |
1110 | break; | |
ccc9c027 L |
1111 | case PROCESSOR_PENTIUM4: |
1112 | case PROCESSOR_NOCONA: | |
ef05d495 | 1113 | case PROCESSOR_CORE: |
76bc74dc | 1114 | case PROCESSOR_CORE2: |
bd5295b2 | 1115 | case PROCESSOR_COREI7: |
3632d14b | 1116 | case PROCESSOR_L1OM: |
7a9068fe | 1117 | case PROCESSOR_K1OM: |
76bc74dc L |
1118 | case PROCESSOR_GENERIC64: |
1119 | patt = alt_long_patt; | |
1120 | break; | |
ccc9c027 L |
1121 | case PROCESSOR_K6: |
1122 | case PROCESSOR_ATHLON: | |
1123 | case PROCESSOR_K8: | |
4eed87de | 1124 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1125 | case PROCESSOR_BD: |
7b458c12 | 1126 | case PROCESSOR_BT: |
ccc9c027 L |
1127 | patt = alt_short_patt; |
1128 | break; | |
76bc74dc | 1129 | case PROCESSOR_I386: |
ccc9c027 L |
1130 | case PROCESSOR_I486: |
1131 | case PROCESSOR_PENTIUM: | |
2dde1948 | 1132 | case PROCESSOR_PENTIUMPRO: |
ccc9c027 L |
1133 | case PROCESSOR_GENERIC32: |
1134 | patt = f32_patt; | |
1135 | break; | |
4eed87de | 1136 | } |
ccc9c027 L |
1137 | } |
1138 | else | |
1139 | { | |
fbf3f584 | 1140 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1141 | { |
1142 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1143 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1144 | PROCESSOR_UNKNOWN. */ |
1145 | abort (); | |
1146 | break; | |
1147 | ||
76bc74dc | 1148 | case PROCESSOR_I386: |
ccc9c027 L |
1149 | case PROCESSOR_I486: |
1150 | case PROCESSOR_PENTIUM: | |
ccc9c027 L |
1151 | case PROCESSOR_K6: |
1152 | case PROCESSOR_ATHLON: | |
1153 | case PROCESSOR_K8: | |
4eed87de | 1154 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1155 | case PROCESSOR_BD: |
7b458c12 | 1156 | case PROCESSOR_BT: |
ccc9c027 L |
1157 | case PROCESSOR_GENERIC32: |
1158 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
22109423 L |
1159 | with nops. */ |
1160 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
ccc9c027 L |
1161 | patt = alt_short_patt; |
1162 | else | |
1163 | patt = f32_patt; | |
1164 | break; | |
76bc74dc L |
1165 | case PROCESSOR_PENTIUMPRO: |
1166 | case PROCESSOR_PENTIUM4: | |
1167 | case PROCESSOR_NOCONA: | |
1168 | case PROCESSOR_CORE: | |
ef05d495 | 1169 | case PROCESSOR_CORE2: |
bd5295b2 | 1170 | case PROCESSOR_COREI7: |
3632d14b | 1171 | case PROCESSOR_L1OM: |
7a9068fe | 1172 | case PROCESSOR_K1OM: |
22109423 | 1173 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
ccc9c027 L |
1174 | patt = alt_long_patt; |
1175 | else | |
1176 | patt = f32_patt; | |
1177 | break; | |
1178 | case PROCESSOR_GENERIC64: | |
76bc74dc | 1179 | patt = alt_long_patt; |
ccc9c027 | 1180 | break; |
4eed87de | 1181 | } |
ccc9c027 L |
1182 | } |
1183 | ||
76bc74dc L |
1184 | if (patt == f32_patt) |
1185 | { | |
1186 | /* If the padding is less than 15 bytes, we use the normal | |
1187 | ones. Otherwise, we use a jump instruction and adjust | |
711eedef L |
1188 | its offset. */ |
1189 | int limit; | |
76ba9986 | 1190 | |
711eedef L |
1191 | /* For 64bit, the limit is 3 bytes. */ |
1192 | if (flag_code == CODE_64BIT | |
1193 | && fragP->tc_frag_data.isa_flags.bitfield.cpulm) | |
1194 | limit = 3; | |
1195 | else | |
1196 | limit = 15; | |
1197 | if (count < limit) | |
76bc74dc L |
1198 | memcpy (fragP->fr_literal + fragP->fr_fix, |
1199 | patt[count - 1], count); | |
1200 | else | |
1201 | { | |
1202 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1203 | jump_31, count); | |
1204 | /* Adjust jump offset. */ | |
1205 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
1206 | } | |
1207 | } | |
1208 | else | |
1209 | { | |
1210 | /* Maximum length of an instruction is 15 byte. If the | |
1211 | padding is greater than 15 bytes and we don't use jump, | |
1212 | we have to break it into smaller pieces. */ | |
1213 | int padding = count; | |
1214 | while (padding > 15) | |
1215 | { | |
1216 | padding -= 15; | |
1217 | memcpy (fragP->fr_literal + fragP->fr_fix + padding, | |
1218 | patt [14], 15); | |
1219 | } | |
1220 | ||
1221 | if (padding) | |
1222 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1223 | patt [padding - 1], padding); | |
1224 | } | |
ccc9c027 | 1225 | } |
33fef721 | 1226 | fragP->fr_var = count; |
252b5132 RH |
1227 | } |
1228 | ||
c6fb90c8 | 1229 | static INLINE int |
0dfbf9d7 | 1230 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1231 | { |
0dfbf9d7 | 1232 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1233 | { |
1234 | case 3: | |
0dfbf9d7 | 1235 | if (x->array[2]) |
c6fb90c8 L |
1236 | return 0; |
1237 | case 2: | |
0dfbf9d7 | 1238 | if (x->array[1]) |
c6fb90c8 L |
1239 | return 0; |
1240 | case 1: | |
0dfbf9d7 | 1241 | return !x->array[0]; |
c6fb90c8 L |
1242 | default: |
1243 | abort (); | |
1244 | } | |
40fb9820 L |
1245 | } |
1246 | ||
c6fb90c8 | 1247 | static INLINE void |
0dfbf9d7 | 1248 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1249 | { |
0dfbf9d7 | 1250 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1251 | { |
1252 | case 3: | |
0dfbf9d7 | 1253 | x->array[2] = v; |
c6fb90c8 | 1254 | case 2: |
0dfbf9d7 | 1255 | x->array[1] = v; |
c6fb90c8 | 1256 | case 1: |
0dfbf9d7 | 1257 | x->array[0] = v; |
c6fb90c8 L |
1258 | break; |
1259 | default: | |
1260 | abort (); | |
1261 | } | |
1262 | } | |
40fb9820 | 1263 | |
c6fb90c8 | 1264 | static INLINE int |
0dfbf9d7 L |
1265 | operand_type_equal (const union i386_operand_type *x, |
1266 | const union i386_operand_type *y) | |
c6fb90c8 | 1267 | { |
0dfbf9d7 | 1268 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1269 | { |
1270 | case 3: | |
0dfbf9d7 | 1271 | if (x->array[2] != y->array[2]) |
c6fb90c8 L |
1272 | return 0; |
1273 | case 2: | |
0dfbf9d7 | 1274 | if (x->array[1] != y->array[1]) |
c6fb90c8 L |
1275 | return 0; |
1276 | case 1: | |
0dfbf9d7 | 1277 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1278 | break; |
1279 | default: | |
1280 | abort (); | |
1281 | } | |
1282 | } | |
40fb9820 | 1283 | |
0dfbf9d7 L |
1284 | static INLINE int |
1285 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1286 | { | |
1287 | switch (ARRAY_SIZE(x->array)) | |
1288 | { | |
1289 | case 3: | |
1290 | if (x->array[2]) | |
1291 | return 0; | |
1292 | case 2: | |
1293 | if (x->array[1]) | |
1294 | return 0; | |
1295 | case 1: | |
1296 | return !x->array[0]; | |
1297 | default: | |
1298 | abort (); | |
1299 | } | |
1300 | } | |
1301 | ||
1302 | static INLINE void | |
1303 | cpu_flags_set (union i386_cpu_flags *x, unsigned int v) | |
1304 | { | |
1305 | switch (ARRAY_SIZE(x->array)) | |
1306 | { | |
1307 | case 3: | |
1308 | x->array[2] = v; | |
1309 | case 2: | |
1310 | x->array[1] = v; | |
1311 | case 1: | |
1312 | x->array[0] = v; | |
1313 | break; | |
1314 | default: | |
1315 | abort (); | |
1316 | } | |
1317 | } | |
1318 | ||
1319 | static INLINE int | |
1320 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1321 | const union i386_cpu_flags *y) | |
1322 | { | |
1323 | switch (ARRAY_SIZE(x->array)) | |
1324 | { | |
1325 | case 3: | |
1326 | if (x->array[2] != y->array[2]) | |
1327 | return 0; | |
1328 | case 2: | |
1329 | if (x->array[1] != y->array[1]) | |
1330 | return 0; | |
1331 | case 1: | |
1332 | return x->array[0] == y->array[0]; | |
1333 | break; | |
1334 | default: | |
1335 | abort (); | |
1336 | } | |
1337 | } | |
c6fb90c8 L |
1338 | |
1339 | static INLINE int | |
1340 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1341 | { | |
1342 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1343 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1344 | } |
1345 | ||
c6fb90c8 L |
1346 | static INLINE i386_cpu_flags |
1347 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1348 | { |
c6fb90c8 L |
1349 | switch (ARRAY_SIZE (x.array)) |
1350 | { | |
1351 | case 3: | |
1352 | x.array [2] &= y.array [2]; | |
1353 | case 2: | |
1354 | x.array [1] &= y.array [1]; | |
1355 | case 1: | |
1356 | x.array [0] &= y.array [0]; | |
1357 | break; | |
1358 | default: | |
1359 | abort (); | |
1360 | } | |
1361 | return x; | |
1362 | } | |
40fb9820 | 1363 | |
c6fb90c8 L |
1364 | static INLINE i386_cpu_flags |
1365 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1366 | { |
c6fb90c8 | 1367 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1368 | { |
c6fb90c8 L |
1369 | case 3: |
1370 | x.array [2] |= y.array [2]; | |
1371 | case 2: | |
1372 | x.array [1] |= y.array [1]; | |
1373 | case 1: | |
1374 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1375 | break; |
1376 | default: | |
1377 | abort (); | |
1378 | } | |
40fb9820 L |
1379 | return x; |
1380 | } | |
1381 | ||
309d3373 JB |
1382 | static INLINE i386_cpu_flags |
1383 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1384 | { | |
1385 | switch (ARRAY_SIZE (x.array)) | |
1386 | { | |
1387 | case 3: | |
1388 | x.array [2] &= ~y.array [2]; | |
1389 | case 2: | |
1390 | x.array [1] &= ~y.array [1]; | |
1391 | case 1: | |
1392 | x.array [0] &= ~y.array [0]; | |
1393 | break; | |
1394 | default: | |
1395 | abort (); | |
1396 | } | |
1397 | return x; | |
1398 | } | |
1399 | ||
c0f3af97 L |
1400 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1401 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
a5ff0eb2 | 1402 | #define CPU_FLAGS_AES_MATCH 0x4 |
ce2f5b3c L |
1403 | #define CPU_FLAGS_PCLMUL_MATCH 0x8 |
1404 | #define CPU_FLAGS_AVX_MATCH 0x10 | |
c0f3af97 | 1405 | |
a5ff0eb2 | 1406 | #define CPU_FLAGS_32BIT_MATCH \ |
ce2f5b3c L |
1407 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \ |
1408 | | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH) | |
c0f3af97 L |
1409 | #define CPU_FLAGS_PERFECT_MATCH \ |
1410 | (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH) | |
1411 | ||
1412 | /* Return CPU flags match bits. */ | |
3629bb00 | 1413 | |
40fb9820 | 1414 | static int |
d3ce72d0 | 1415 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1416 | { |
c0f3af97 L |
1417 | i386_cpu_flags x = t->cpu_flags; |
1418 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; | |
40fb9820 L |
1419 | |
1420 | x.bitfield.cpu64 = 0; | |
1421 | x.bitfield.cpuno64 = 0; | |
1422 | ||
0dfbf9d7 | 1423 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1424 | { |
1425 | /* This instruction is available on all archs. */ | |
1426 | match |= CPU_FLAGS_32BIT_MATCH; | |
1427 | } | |
3629bb00 L |
1428 | else |
1429 | { | |
c0f3af97 | 1430 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1431 | i386_cpu_flags cpu = cpu_arch_flags; |
1432 | ||
1433 | cpu.bitfield.cpu64 = 0; | |
1434 | cpu.bitfield.cpuno64 = 0; | |
1435 | cpu = cpu_flags_and (x, cpu); | |
c0f3af97 L |
1436 | if (!cpu_flags_all_zero (&cpu)) |
1437 | { | |
a5ff0eb2 L |
1438 | if (x.bitfield.cpuavx) |
1439 | { | |
ce2f5b3c | 1440 | /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */ |
a5ff0eb2 L |
1441 | if (cpu.bitfield.cpuavx) |
1442 | { | |
1443 | /* Check SSE2AVX. */ | |
1444 | if (!t->opcode_modifier.sse2avx|| sse2avx) | |
1445 | { | |
1446 | match |= (CPU_FLAGS_ARCH_MATCH | |
1447 | | CPU_FLAGS_AVX_MATCH); | |
1448 | /* Check AES. */ | |
1449 | if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) | |
1450 | match |= CPU_FLAGS_AES_MATCH; | |
ce2f5b3c L |
1451 | /* Check PCLMUL. */ |
1452 | if (!x.bitfield.cpupclmul | |
1453 | || cpu.bitfield.cpupclmul) | |
1454 | match |= CPU_FLAGS_PCLMUL_MATCH; | |
a5ff0eb2 L |
1455 | } |
1456 | } | |
1457 | else | |
1458 | match |= CPU_FLAGS_ARCH_MATCH; | |
1459 | } | |
1460 | else | |
c0f3af97 L |
1461 | match |= CPU_FLAGS_32BIT_MATCH; |
1462 | } | |
3629bb00 | 1463 | } |
c0f3af97 | 1464 | return match; |
40fb9820 L |
1465 | } |
1466 | ||
c6fb90c8 L |
1467 | static INLINE i386_operand_type |
1468 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1469 | { |
c6fb90c8 L |
1470 | switch (ARRAY_SIZE (x.array)) |
1471 | { | |
1472 | case 3: | |
1473 | x.array [2] &= y.array [2]; | |
1474 | case 2: | |
1475 | x.array [1] &= y.array [1]; | |
1476 | case 1: | |
1477 | x.array [0] &= y.array [0]; | |
1478 | break; | |
1479 | default: | |
1480 | abort (); | |
1481 | } | |
1482 | return x; | |
40fb9820 L |
1483 | } |
1484 | ||
c6fb90c8 L |
1485 | static INLINE i386_operand_type |
1486 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1487 | { |
c6fb90c8 | 1488 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1489 | { |
c6fb90c8 L |
1490 | case 3: |
1491 | x.array [2] |= y.array [2]; | |
1492 | case 2: | |
1493 | x.array [1] |= y.array [1]; | |
1494 | case 1: | |
1495 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1496 | break; |
1497 | default: | |
1498 | abort (); | |
1499 | } | |
c6fb90c8 L |
1500 | return x; |
1501 | } | |
40fb9820 | 1502 | |
c6fb90c8 L |
1503 | static INLINE i386_operand_type |
1504 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
1505 | { | |
1506 | switch (ARRAY_SIZE (x.array)) | |
1507 | { | |
1508 | case 3: | |
1509 | x.array [2] ^= y.array [2]; | |
1510 | case 2: | |
1511 | x.array [1] ^= y.array [1]; | |
1512 | case 1: | |
1513 | x.array [0] ^= y.array [0]; | |
1514 | break; | |
1515 | default: | |
1516 | abort (); | |
1517 | } | |
40fb9820 L |
1518 | return x; |
1519 | } | |
1520 | ||
1521 | static const i386_operand_type acc32 = OPERAND_TYPE_ACC32; | |
1522 | static const i386_operand_type acc64 = OPERAND_TYPE_ACC64; | |
1523 | static const i386_operand_type control = OPERAND_TYPE_CONTROL; | |
65da13b5 L |
1524 | static const i386_operand_type inoutportreg |
1525 | = OPERAND_TYPE_INOUTPORTREG; | |
40fb9820 L |
1526 | static const i386_operand_type reg16_inoutportreg |
1527 | = OPERAND_TYPE_REG16_INOUTPORTREG; | |
1528 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; | |
1529 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; | |
1530 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; | |
1531 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; | |
1532 | static const i386_operand_type anydisp | |
1533 | = OPERAND_TYPE_ANYDISP; | |
40fb9820 | 1534 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
c0f3af97 | 1535 | static const i386_operand_type regymm = OPERAND_TYPE_REGYMM; |
40fb9820 L |
1536 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
1537 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; | |
1538 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; | |
1539 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
1540 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
1541 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; | |
1542 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; | |
1543 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
1544 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
a683cc34 | 1545 | static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4; |
40fb9820 L |
1546 | |
1547 | enum operand_type | |
1548 | { | |
1549 | reg, | |
40fb9820 L |
1550 | imm, |
1551 | disp, | |
1552 | anymem | |
1553 | }; | |
1554 | ||
c6fb90c8 | 1555 | static INLINE int |
40fb9820 L |
1556 | operand_type_check (i386_operand_type t, enum operand_type c) |
1557 | { | |
1558 | switch (c) | |
1559 | { | |
1560 | case reg: | |
1561 | return (t.bitfield.reg8 | |
1562 | || t.bitfield.reg16 | |
1563 | || t.bitfield.reg32 | |
1564 | || t.bitfield.reg64); | |
1565 | ||
40fb9820 L |
1566 | case imm: |
1567 | return (t.bitfield.imm8 | |
1568 | || t.bitfield.imm8s | |
1569 | || t.bitfield.imm16 | |
1570 | || t.bitfield.imm32 | |
1571 | || t.bitfield.imm32s | |
1572 | || t.bitfield.imm64); | |
1573 | ||
1574 | case disp: | |
1575 | return (t.bitfield.disp8 | |
1576 | || t.bitfield.disp16 | |
1577 | || t.bitfield.disp32 | |
1578 | || t.bitfield.disp32s | |
1579 | || t.bitfield.disp64); | |
1580 | ||
1581 | case anymem: | |
1582 | return (t.bitfield.disp8 | |
1583 | || t.bitfield.disp16 | |
1584 | || t.bitfield.disp32 | |
1585 | || t.bitfield.disp32s | |
1586 | || t.bitfield.disp64 | |
1587 | || t.bitfield.baseindex); | |
1588 | ||
1589 | default: | |
1590 | abort (); | |
1591 | } | |
2cfe26b6 AM |
1592 | |
1593 | return 0; | |
40fb9820 L |
1594 | } |
1595 | ||
5c07affc L |
1596 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on |
1597 | operand J for instruction template T. */ | |
1598 | ||
1599 | static INLINE int | |
d3ce72d0 | 1600 | match_reg_size (const insn_template *t, unsigned int j) |
5c07affc L |
1601 | { |
1602 | return !((i.types[j].bitfield.byte | |
1603 | && !t->operand_types[j].bitfield.byte) | |
1604 | || (i.types[j].bitfield.word | |
1605 | && !t->operand_types[j].bitfield.word) | |
1606 | || (i.types[j].bitfield.dword | |
1607 | && !t->operand_types[j].bitfield.dword) | |
1608 | || (i.types[j].bitfield.qword | |
1609 | && !t->operand_types[j].bitfield.qword)); | |
1610 | } | |
1611 | ||
1612 | /* Return 1 if there is no conflict in any size on operand J for | |
1613 | instruction template T. */ | |
1614 | ||
1615 | static INLINE int | |
d3ce72d0 | 1616 | match_mem_size (const insn_template *t, unsigned int j) |
5c07affc L |
1617 | { |
1618 | return (match_reg_size (t, j) | |
1619 | && !((i.types[j].bitfield.unspecified | |
1620 | && !t->operand_types[j].bitfield.unspecified) | |
1621 | || (i.types[j].bitfield.fword | |
1622 | && !t->operand_types[j].bitfield.fword) | |
1623 | || (i.types[j].bitfield.tbyte | |
1624 | && !t->operand_types[j].bitfield.tbyte) | |
1625 | || (i.types[j].bitfield.xmmword | |
c0f3af97 L |
1626 | && !t->operand_types[j].bitfield.xmmword) |
1627 | || (i.types[j].bitfield.ymmword | |
1628 | && !t->operand_types[j].bitfield.ymmword))); | |
5c07affc L |
1629 | } |
1630 | ||
1631 | /* Return 1 if there is no size conflict on any operands for | |
1632 | instruction template T. */ | |
1633 | ||
1634 | static INLINE int | |
d3ce72d0 | 1635 | operand_size_match (const insn_template *t) |
5c07affc L |
1636 | { |
1637 | unsigned int j; | |
1638 | int match = 1; | |
1639 | ||
1640 | /* Don't check jump instructions. */ | |
1641 | if (t->opcode_modifier.jump | |
1642 | || t->opcode_modifier.jumpbyte | |
1643 | || t->opcode_modifier.jumpdword | |
1644 | || t->opcode_modifier.jumpintersegment) | |
1645 | return match; | |
1646 | ||
1647 | /* Check memory and accumulator operand size. */ | |
1648 | for (j = 0; j < i.operands; j++) | |
1649 | { | |
1650 | if (t->operand_types[j].bitfield.anysize) | |
1651 | continue; | |
1652 | ||
1653 | if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j)) | |
1654 | { | |
1655 | match = 0; | |
1656 | break; | |
1657 | } | |
1658 | ||
1659 | if (i.types[j].bitfield.mem && !match_mem_size (t, j)) | |
1660 | { | |
1661 | match = 0; | |
1662 | break; | |
1663 | } | |
1664 | } | |
1665 | ||
891edac4 | 1666 | if (match) |
5c07affc | 1667 | return match; |
891edac4 L |
1668 | else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) |
1669 | { | |
1670 | mismatch: | |
86e026a4 | 1671 | i.error = operand_size_mismatch; |
891edac4 L |
1672 | return 0; |
1673 | } | |
5c07affc L |
1674 | |
1675 | /* Check reverse. */ | |
9c2799c2 | 1676 | gas_assert (i.operands == 2); |
5c07affc L |
1677 | |
1678 | match = 1; | |
1679 | for (j = 0; j < 2; j++) | |
1680 | { | |
1681 | if (t->operand_types[j].bitfield.acc | |
1682 | && !match_reg_size (t, j ? 0 : 1)) | |
891edac4 | 1683 | goto mismatch; |
5c07affc L |
1684 | |
1685 | if (i.types[j].bitfield.mem | |
1686 | && !match_mem_size (t, j ? 0 : 1)) | |
891edac4 | 1687 | goto mismatch; |
5c07affc L |
1688 | } |
1689 | ||
1690 | return match; | |
1691 | } | |
1692 | ||
c6fb90c8 | 1693 | static INLINE int |
40fb9820 L |
1694 | operand_type_match (i386_operand_type overlap, |
1695 | i386_operand_type given) | |
1696 | { | |
1697 | i386_operand_type temp = overlap; | |
1698 | ||
1699 | temp.bitfield.jumpabsolute = 0; | |
7d5e4556 | 1700 | temp.bitfield.unspecified = 0; |
5c07affc L |
1701 | temp.bitfield.byte = 0; |
1702 | temp.bitfield.word = 0; | |
1703 | temp.bitfield.dword = 0; | |
1704 | temp.bitfield.fword = 0; | |
1705 | temp.bitfield.qword = 0; | |
1706 | temp.bitfield.tbyte = 0; | |
1707 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 1708 | temp.bitfield.ymmword = 0; |
0dfbf9d7 | 1709 | if (operand_type_all_zero (&temp)) |
891edac4 | 1710 | goto mismatch; |
40fb9820 | 1711 | |
891edac4 L |
1712 | if (given.bitfield.baseindex == overlap.bitfield.baseindex |
1713 | && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute) | |
1714 | return 1; | |
1715 | ||
1716 | mismatch: | |
a65babc9 | 1717 | i.error = operand_type_mismatch; |
891edac4 | 1718 | return 0; |
40fb9820 L |
1719 | } |
1720 | ||
7d5e4556 | 1721 | /* If given types g0 and g1 are registers they must be of the same type |
40fb9820 L |
1722 | unless the expected operand type register overlap is null. |
1723 | Note that Acc in a template matches every size of reg. */ | |
1724 | ||
c6fb90c8 | 1725 | static INLINE int |
40fb9820 L |
1726 | operand_type_register_match (i386_operand_type m0, |
1727 | i386_operand_type g0, | |
1728 | i386_operand_type t0, | |
1729 | i386_operand_type m1, | |
1730 | i386_operand_type g1, | |
1731 | i386_operand_type t1) | |
1732 | { | |
1733 | if (!operand_type_check (g0, reg)) | |
1734 | return 1; | |
1735 | ||
1736 | if (!operand_type_check (g1, reg)) | |
1737 | return 1; | |
1738 | ||
1739 | if (g0.bitfield.reg8 == g1.bitfield.reg8 | |
1740 | && g0.bitfield.reg16 == g1.bitfield.reg16 | |
1741 | && g0.bitfield.reg32 == g1.bitfield.reg32 | |
1742 | && g0.bitfield.reg64 == g1.bitfield.reg64) | |
1743 | return 1; | |
1744 | ||
1745 | if (m0.bitfield.acc) | |
1746 | { | |
1747 | t0.bitfield.reg8 = 1; | |
1748 | t0.bitfield.reg16 = 1; | |
1749 | t0.bitfield.reg32 = 1; | |
1750 | t0.bitfield.reg64 = 1; | |
1751 | } | |
1752 | ||
1753 | if (m1.bitfield.acc) | |
1754 | { | |
1755 | t1.bitfield.reg8 = 1; | |
1756 | t1.bitfield.reg16 = 1; | |
1757 | t1.bitfield.reg32 = 1; | |
1758 | t1.bitfield.reg64 = 1; | |
1759 | } | |
1760 | ||
891edac4 L |
1761 | if (!(t0.bitfield.reg8 & t1.bitfield.reg8) |
1762 | && !(t0.bitfield.reg16 & t1.bitfield.reg16) | |
1763 | && !(t0.bitfield.reg32 & t1.bitfield.reg32) | |
1764 | && !(t0.bitfield.reg64 & t1.bitfield.reg64)) | |
1765 | return 1; | |
1766 | ||
a65babc9 | 1767 | i.error = register_type_mismatch; |
891edac4 L |
1768 | |
1769 | return 0; | |
40fb9820 L |
1770 | } |
1771 | ||
4c692bc7 JB |
1772 | static INLINE unsigned int |
1773 | register_number (const reg_entry *r) | |
1774 | { | |
1775 | unsigned int nr = r->reg_num; | |
1776 | ||
1777 | if (r->reg_flags & RegRex) | |
1778 | nr += 8; | |
1779 | ||
1780 | return nr; | |
1781 | } | |
1782 | ||
252b5132 | 1783 | static INLINE unsigned int |
40fb9820 | 1784 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 1785 | { |
40fb9820 L |
1786 | if (t.bitfield.disp8) |
1787 | return 1; | |
1788 | else if (t.bitfield.disp16 | |
1789 | || t.bitfield.disp32 | |
1790 | || t.bitfield.disp32s) | |
1791 | return 2; | |
1792 | else | |
1793 | return 0; | |
252b5132 RH |
1794 | } |
1795 | ||
1796 | static INLINE int | |
e3bb37b5 | 1797 | fits_in_signed_byte (offsetT num) |
252b5132 RH |
1798 | { |
1799 | return (num >= -128) && (num <= 127); | |
47926f60 | 1800 | } |
252b5132 RH |
1801 | |
1802 | static INLINE int | |
e3bb37b5 | 1803 | fits_in_unsigned_byte (offsetT num) |
252b5132 RH |
1804 | { |
1805 | return (num & 0xff) == num; | |
47926f60 | 1806 | } |
252b5132 RH |
1807 | |
1808 | static INLINE int | |
e3bb37b5 | 1809 | fits_in_unsigned_word (offsetT num) |
252b5132 RH |
1810 | { |
1811 | return (num & 0xffff) == num; | |
47926f60 | 1812 | } |
252b5132 RH |
1813 | |
1814 | static INLINE int | |
e3bb37b5 | 1815 | fits_in_signed_word (offsetT num) |
252b5132 RH |
1816 | { |
1817 | return (-32768 <= num) && (num <= 32767); | |
47926f60 | 1818 | } |
2a962e6d | 1819 | |
3e73aa7c | 1820 | static INLINE int |
e3bb37b5 | 1821 | fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
1822 | { |
1823 | #ifndef BFD64 | |
1824 | return 1; | |
1825 | #else | |
1826 | return (!(((offsetT) -1 << 31) & num) | |
1827 | || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31)); | |
1828 | #endif | |
1829 | } /* fits_in_signed_long() */ | |
2a962e6d | 1830 | |
3e73aa7c | 1831 | static INLINE int |
e3bb37b5 | 1832 | fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
1833 | { |
1834 | #ifndef BFD64 | |
1835 | return 1; | |
1836 | #else | |
1837 | return (num & (((offsetT) 2 << 31) - 1)) == num; | |
1838 | #endif | |
1839 | } /* fits_in_unsigned_long() */ | |
252b5132 | 1840 | |
a683cc34 SP |
1841 | static INLINE int |
1842 | fits_in_imm4 (offsetT num) | |
1843 | { | |
1844 | return (num & 0xf) == num; | |
1845 | } | |
1846 | ||
40fb9820 | 1847 | static i386_operand_type |
e3bb37b5 | 1848 | smallest_imm_type (offsetT num) |
252b5132 | 1849 | { |
40fb9820 | 1850 | i386_operand_type t; |
7ab9ffdd | 1851 | |
0dfbf9d7 | 1852 | operand_type_set (&t, 0); |
40fb9820 L |
1853 | t.bitfield.imm64 = 1; |
1854 | ||
1855 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
1856 | { |
1857 | /* This code is disabled on the 486 because all the Imm1 forms | |
1858 | in the opcode table are slower on the i486. They're the | |
1859 | versions with the implicitly specified single-position | |
1860 | displacement, which has another syntax if you really want to | |
1861 | use that form. */ | |
40fb9820 L |
1862 | t.bitfield.imm1 = 1; |
1863 | t.bitfield.imm8 = 1; | |
1864 | t.bitfield.imm8s = 1; | |
1865 | t.bitfield.imm16 = 1; | |
1866 | t.bitfield.imm32 = 1; | |
1867 | t.bitfield.imm32s = 1; | |
1868 | } | |
1869 | else if (fits_in_signed_byte (num)) | |
1870 | { | |
1871 | t.bitfield.imm8 = 1; | |
1872 | t.bitfield.imm8s = 1; | |
1873 | t.bitfield.imm16 = 1; | |
1874 | t.bitfield.imm32 = 1; | |
1875 | t.bitfield.imm32s = 1; | |
1876 | } | |
1877 | else if (fits_in_unsigned_byte (num)) | |
1878 | { | |
1879 | t.bitfield.imm8 = 1; | |
1880 | t.bitfield.imm16 = 1; | |
1881 | t.bitfield.imm32 = 1; | |
1882 | t.bitfield.imm32s = 1; | |
1883 | } | |
1884 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
1885 | { | |
1886 | t.bitfield.imm16 = 1; | |
1887 | t.bitfield.imm32 = 1; | |
1888 | t.bitfield.imm32s = 1; | |
1889 | } | |
1890 | else if (fits_in_signed_long (num)) | |
1891 | { | |
1892 | t.bitfield.imm32 = 1; | |
1893 | t.bitfield.imm32s = 1; | |
1894 | } | |
1895 | else if (fits_in_unsigned_long (num)) | |
1896 | t.bitfield.imm32 = 1; | |
1897 | ||
1898 | return t; | |
47926f60 | 1899 | } |
252b5132 | 1900 | |
847f7ad4 | 1901 | static offsetT |
e3bb37b5 | 1902 | offset_in_range (offsetT val, int size) |
847f7ad4 | 1903 | { |
508866be | 1904 | addressT mask; |
ba2adb93 | 1905 | |
847f7ad4 AM |
1906 | switch (size) |
1907 | { | |
508866be L |
1908 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
1909 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 1910 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
1911 | #ifdef BFD64 |
1912 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
1913 | #endif | |
47926f60 | 1914 | default: abort (); |
847f7ad4 AM |
1915 | } |
1916 | ||
9de868bf L |
1917 | #ifdef BFD64 |
1918 | /* If BFD64, sign extend val for 32bit address mode. */ | |
1919 | if (flag_code != CODE_64BIT | |
1920 | || i.prefix[ADDR_PREFIX]) | |
3e73aa7c JH |
1921 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) |
1922 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
fa289fb8 | 1923 | #endif |
ba2adb93 | 1924 | |
47926f60 | 1925 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
1926 | { |
1927 | char buf1[40], buf2[40]; | |
1928 | ||
1929 | sprint_value (buf1, val); | |
1930 | sprint_value (buf2, val & mask); | |
1931 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
1932 | } | |
1933 | return val & mask; | |
1934 | } | |
1935 | ||
c32fa91d L |
1936 | enum PREFIX_GROUP |
1937 | { | |
1938 | PREFIX_EXIST = 0, | |
1939 | PREFIX_LOCK, | |
1940 | PREFIX_REP, | |
1941 | PREFIX_OTHER | |
1942 | }; | |
1943 | ||
1944 | /* Returns | |
1945 | a. PREFIX_EXIST if attempting to add a prefix where one from the | |
1946 | same class already exists. | |
1947 | b. PREFIX_LOCK if lock prefix is added. | |
1948 | c. PREFIX_REP if rep/repne prefix is added. | |
1949 | d. PREFIX_OTHER if other prefix is added. | |
1950 | */ | |
1951 | ||
1952 | static enum PREFIX_GROUP | |
e3bb37b5 | 1953 | add_prefix (unsigned int prefix) |
252b5132 | 1954 | { |
c32fa91d | 1955 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
b1905489 | 1956 | unsigned int q; |
252b5132 | 1957 | |
29b0f896 AM |
1958 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
1959 | && flag_code == CODE_64BIT) | |
b1905489 | 1960 | { |
161a04f6 L |
1961 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
1962 | || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B)) | |
1963 | && (prefix & (REX_R | REX_X | REX_B)))) | |
c32fa91d | 1964 | ret = PREFIX_EXIST; |
b1905489 JB |
1965 | q = REX_PREFIX; |
1966 | } | |
3e73aa7c | 1967 | else |
b1905489 JB |
1968 | { |
1969 | switch (prefix) | |
1970 | { | |
1971 | default: | |
1972 | abort (); | |
1973 | ||
1974 | case CS_PREFIX_OPCODE: | |
1975 | case DS_PREFIX_OPCODE: | |
1976 | case ES_PREFIX_OPCODE: | |
1977 | case FS_PREFIX_OPCODE: | |
1978 | case GS_PREFIX_OPCODE: | |
1979 | case SS_PREFIX_OPCODE: | |
1980 | q = SEG_PREFIX; | |
1981 | break; | |
1982 | ||
1983 | case REPNE_PREFIX_OPCODE: | |
1984 | case REPE_PREFIX_OPCODE: | |
c32fa91d L |
1985 | q = REP_PREFIX; |
1986 | ret = PREFIX_REP; | |
1987 | break; | |
1988 | ||
b1905489 | 1989 | case LOCK_PREFIX_OPCODE: |
c32fa91d L |
1990 | q = LOCK_PREFIX; |
1991 | ret = PREFIX_LOCK; | |
b1905489 JB |
1992 | break; |
1993 | ||
1994 | case FWAIT_OPCODE: | |
1995 | q = WAIT_PREFIX; | |
1996 | break; | |
1997 | ||
1998 | case ADDR_PREFIX_OPCODE: | |
1999 | q = ADDR_PREFIX; | |
2000 | break; | |
2001 | ||
2002 | case DATA_PREFIX_OPCODE: | |
2003 | q = DATA_PREFIX; | |
2004 | break; | |
2005 | } | |
2006 | if (i.prefix[q] != 0) | |
c32fa91d | 2007 | ret = PREFIX_EXIST; |
b1905489 | 2008 | } |
252b5132 | 2009 | |
b1905489 | 2010 | if (ret) |
252b5132 | 2011 | { |
b1905489 JB |
2012 | if (!i.prefix[q]) |
2013 | ++i.prefixes; | |
2014 | i.prefix[q] |= prefix; | |
252b5132 | 2015 | } |
b1905489 JB |
2016 | else |
2017 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 2018 | |
252b5132 RH |
2019 | return ret; |
2020 | } | |
2021 | ||
2022 | static void | |
78f12dd3 | 2023 | update_code_flag (int value, int check) |
eecb386c | 2024 | { |
78f12dd3 L |
2025 | PRINTF_LIKE ((*as_error)); |
2026 | ||
1e9cc1c2 | 2027 | flag_code = (enum flag_code) value; |
40fb9820 L |
2028 | if (flag_code == CODE_64BIT) |
2029 | { | |
2030 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2031 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
2032 | } |
2033 | else | |
2034 | { | |
2035 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2036 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
2037 | } |
2038 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c | 2039 | { |
78f12dd3 L |
2040 | if (check) |
2041 | as_error = as_fatal; | |
2042 | else | |
2043 | as_error = as_bad; | |
2044 | (*as_error) (_("64bit mode not supported on `%s'."), | |
2045 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2046 | } |
40fb9820 | 2047 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c | 2048 | { |
78f12dd3 L |
2049 | if (check) |
2050 | as_error = as_fatal; | |
2051 | else | |
2052 | as_error = as_bad; | |
2053 | (*as_error) (_("32bit mode not supported on `%s'."), | |
2054 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2055 | } |
eecb386c AM |
2056 | stackop_size = '\0'; |
2057 | } | |
2058 | ||
78f12dd3 L |
2059 | static void |
2060 | set_code_flag (int value) | |
2061 | { | |
2062 | update_code_flag (value, 0); | |
2063 | } | |
2064 | ||
eecb386c | 2065 | static void |
e3bb37b5 | 2066 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 2067 | { |
1e9cc1c2 | 2068 | flag_code = (enum flag_code) new_code_flag; |
40fb9820 L |
2069 | if (flag_code != CODE_16BIT) |
2070 | abort (); | |
2071 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2072 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 2073 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
2074 | } |
2075 | ||
2076 | static void | |
e3bb37b5 | 2077 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
2078 | { |
2079 | /* Find out if register prefixing is specified. */ | |
2080 | int ask_naked_reg = 0; | |
2081 | ||
2082 | SKIP_WHITESPACE (); | |
29b0f896 | 2083 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 RH |
2084 | { |
2085 | char *string = input_line_pointer; | |
2086 | int e = get_symbol_end (); | |
2087 | ||
47926f60 | 2088 | if (strcmp (string, "prefix") == 0) |
252b5132 | 2089 | ask_naked_reg = 1; |
47926f60 | 2090 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
2091 | ask_naked_reg = -1; |
2092 | else | |
d0b47220 | 2093 | as_bad (_("bad argument to syntax directive.")); |
252b5132 RH |
2094 | *input_line_pointer = e; |
2095 | } | |
2096 | demand_empty_rest_of_line (); | |
c3332e24 | 2097 | |
252b5132 RH |
2098 | intel_syntax = syntax_flag; |
2099 | ||
2100 | if (ask_naked_reg == 0) | |
f86103b7 AM |
2101 | allow_naked_reg = (intel_syntax |
2102 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
2103 | else |
2104 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 2105 | |
ee86248c | 2106 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
7ab9ffdd | 2107 | |
e4a3b5a4 | 2108 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 2109 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 2110 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
2111 | } |
2112 | ||
1efbbeb4 L |
2113 | static void |
2114 | set_intel_mnemonic (int mnemonic_flag) | |
2115 | { | |
e1d4d893 | 2116 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
2117 | } |
2118 | ||
db51cc60 L |
2119 | static void |
2120 | set_allow_index_reg (int flag) | |
2121 | { | |
2122 | allow_index_reg = flag; | |
2123 | } | |
2124 | ||
cb19c032 | 2125 | static void |
7bab8ab5 | 2126 | set_check (int what) |
cb19c032 | 2127 | { |
7bab8ab5 JB |
2128 | enum check_kind *kind; |
2129 | const char *str; | |
2130 | ||
2131 | if (what) | |
2132 | { | |
2133 | kind = &operand_check; | |
2134 | str = "operand"; | |
2135 | } | |
2136 | else | |
2137 | { | |
2138 | kind = &sse_check; | |
2139 | str = "sse"; | |
2140 | } | |
2141 | ||
cb19c032 L |
2142 | SKIP_WHITESPACE (); |
2143 | ||
2144 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2145 | { | |
2146 | char *string = input_line_pointer; | |
2147 | int e = get_symbol_end (); | |
2148 | ||
2149 | if (strcmp (string, "none") == 0) | |
7bab8ab5 | 2150 | *kind = check_none; |
cb19c032 | 2151 | else if (strcmp (string, "warning") == 0) |
7bab8ab5 | 2152 | *kind = check_warning; |
cb19c032 | 2153 | else if (strcmp (string, "error") == 0) |
7bab8ab5 | 2154 | *kind = check_error; |
cb19c032 | 2155 | else |
7bab8ab5 | 2156 | as_bad (_("bad argument to %s_check directive."), str); |
cb19c032 L |
2157 | *input_line_pointer = e; |
2158 | } | |
2159 | else | |
7bab8ab5 | 2160 | as_bad (_("missing argument for %s_check directive"), str); |
cb19c032 L |
2161 | |
2162 | demand_empty_rest_of_line (); | |
2163 | } | |
2164 | ||
8a9036a4 L |
2165 | static void |
2166 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1e9cc1c2 | 2167 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
8a9036a4 L |
2168 | { |
2169 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2170 | static const char *arch; | |
2171 | ||
2172 | /* Intel LIOM is only supported on ELF. */ | |
2173 | if (!IS_ELF) | |
2174 | return; | |
2175 | ||
2176 | if (!arch) | |
2177 | { | |
2178 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
2179 | use default_arch. */ | |
2180 | arch = cpu_arch_name; | |
2181 | if (!arch) | |
2182 | arch = default_arch; | |
2183 | } | |
2184 | ||
3632d14b | 2185 | /* If we are targeting Intel L1OM, we must enable it. */ |
8a9036a4 | 2186 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM |
1e9cc1c2 | 2187 | || new_flag.bitfield.cpul1om) |
8a9036a4 | 2188 | return; |
76ba9986 | 2189 | |
7a9068fe L |
2190 | /* If we are targeting Intel K1OM, we must enable it. */ |
2191 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM | |
2192 | || new_flag.bitfield.cpuk1om) | |
2193 | return; | |
2194 | ||
8a9036a4 L |
2195 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
2196 | #endif | |
2197 | } | |
2198 | ||
e413e4e9 | 2199 | static void |
e3bb37b5 | 2200 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 2201 | { |
47926f60 | 2202 | SKIP_WHITESPACE (); |
e413e4e9 | 2203 | |
29b0f896 | 2204 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 AM |
2205 | { |
2206 | char *string = input_line_pointer; | |
2207 | int e = get_symbol_end (); | |
91d6fa6a | 2208 | unsigned int j; |
40fb9820 | 2209 | i386_cpu_flags flags; |
e413e4e9 | 2210 | |
91d6fa6a | 2211 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
e413e4e9 | 2212 | { |
91d6fa6a | 2213 | if (strcmp (string, cpu_arch[j].name) == 0) |
e413e4e9 | 2214 | { |
91d6fa6a | 2215 | check_cpu_arch_compatible (string, cpu_arch[j].flags); |
8a9036a4 | 2216 | |
5c6af06e JB |
2217 | if (*string != '.') |
2218 | { | |
91d6fa6a | 2219 | cpu_arch_name = cpu_arch[j].name; |
5c6af06e | 2220 | cpu_sub_arch_name = NULL; |
91d6fa6a | 2221 | cpu_arch_flags = cpu_arch[j].flags; |
40fb9820 L |
2222 | if (flag_code == CODE_64BIT) |
2223 | { | |
2224 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2225 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
2226 | } | |
2227 | else | |
2228 | { | |
2229 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2230 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
2231 | } | |
91d6fa6a NC |
2232 | cpu_arch_isa = cpu_arch[j].type; |
2233 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
ccc9c027 L |
2234 | if (!cpu_arch_tune_set) |
2235 | { | |
2236 | cpu_arch_tune = cpu_arch_isa; | |
2237 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2238 | } | |
5c6af06e JB |
2239 | break; |
2240 | } | |
40fb9820 | 2241 | |
22109423 | 2242 | if (!cpu_arch[j].negated) |
309d3373 | 2243 | flags = cpu_flags_or (cpu_arch_flags, |
91d6fa6a | 2244 | cpu_arch[j].flags); |
309d3373 JB |
2245 | else |
2246 | flags = cpu_flags_and_not (cpu_arch_flags, | |
49021df2 | 2247 | cpu_arch[j].flags); |
0dfbf9d7 | 2248 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
5c6af06e | 2249 | { |
6305a203 L |
2250 | if (cpu_sub_arch_name) |
2251 | { | |
2252 | char *name = cpu_sub_arch_name; | |
2253 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 2254 | cpu_arch[j].name, |
1bf57e9f | 2255 | (const char *) NULL); |
6305a203 L |
2256 | free (name); |
2257 | } | |
2258 | else | |
91d6fa6a | 2259 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
40fb9820 | 2260 | cpu_arch_flags = flags; |
a586129e | 2261 | cpu_arch_isa_flags = flags; |
5c6af06e JB |
2262 | } |
2263 | *input_line_pointer = e; | |
2264 | demand_empty_rest_of_line (); | |
2265 | return; | |
e413e4e9 AM |
2266 | } |
2267 | } | |
91d6fa6a | 2268 | if (j >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
2269 | as_bad (_("no such architecture: `%s'"), string); |
2270 | ||
2271 | *input_line_pointer = e; | |
2272 | } | |
2273 | else | |
2274 | as_bad (_("missing cpu architecture")); | |
2275 | ||
fddf5b5b AM |
2276 | no_cond_jump_promotion = 0; |
2277 | if (*input_line_pointer == ',' | |
29b0f896 | 2278 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b AM |
2279 | { |
2280 | char *string = ++input_line_pointer; | |
2281 | int e = get_symbol_end (); | |
2282 | ||
2283 | if (strcmp (string, "nojumps") == 0) | |
2284 | no_cond_jump_promotion = 1; | |
2285 | else if (strcmp (string, "jumps") == 0) | |
2286 | ; | |
2287 | else | |
2288 | as_bad (_("no such architecture modifier: `%s'"), string); | |
2289 | ||
2290 | *input_line_pointer = e; | |
2291 | } | |
2292 | ||
e413e4e9 AM |
2293 | demand_empty_rest_of_line (); |
2294 | } | |
2295 | ||
8a9036a4 L |
2296 | enum bfd_architecture |
2297 | i386_arch (void) | |
2298 | { | |
3632d14b | 2299 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 L |
2300 | { |
2301 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2302 | || flag_code != CODE_64BIT) | |
2303 | as_fatal (_("Intel L1OM is 64bit ELF only")); | |
2304 | return bfd_arch_l1om; | |
2305 | } | |
7a9068fe L |
2306 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2307 | { | |
2308 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2309 | || flag_code != CODE_64BIT) | |
2310 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2311 | return bfd_arch_k1om; | |
2312 | } | |
8a9036a4 L |
2313 | else |
2314 | return bfd_arch_i386; | |
2315 | } | |
2316 | ||
b9d79e03 | 2317 | unsigned long |
7016a5d5 | 2318 | i386_mach (void) |
b9d79e03 | 2319 | { |
351f65ca | 2320 | if (!strncmp (default_arch, "x86_64", 6)) |
8a9036a4 | 2321 | { |
3632d14b | 2322 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 2323 | { |
351f65ca L |
2324 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
2325 | || default_arch[6] != '\0') | |
8a9036a4 L |
2326 | as_fatal (_("Intel L1OM is 64bit ELF only")); |
2327 | return bfd_mach_l1om; | |
2328 | } | |
7a9068fe L |
2329 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2330 | { | |
2331 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2332 | || default_arch[6] != '\0') | |
2333 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2334 | return bfd_mach_k1om; | |
2335 | } | |
351f65ca | 2336 | else if (default_arch[6] == '\0') |
8a9036a4 | 2337 | return bfd_mach_x86_64; |
351f65ca L |
2338 | else |
2339 | return bfd_mach_x64_32; | |
8a9036a4 | 2340 | } |
b9d79e03 JH |
2341 | else if (!strcmp (default_arch, "i386")) |
2342 | return bfd_mach_i386_i386; | |
2343 | else | |
2b5d6a91 | 2344 | as_fatal (_("unknown architecture")); |
b9d79e03 | 2345 | } |
b9d79e03 | 2346 | \f |
252b5132 | 2347 | void |
7016a5d5 | 2348 | md_begin (void) |
252b5132 RH |
2349 | { |
2350 | const char *hash_err; | |
2351 | ||
47926f60 | 2352 | /* Initialize op_hash hash table. */ |
252b5132 RH |
2353 | op_hash = hash_new (); |
2354 | ||
2355 | { | |
d3ce72d0 | 2356 | const insn_template *optab; |
29b0f896 | 2357 | templates *core_optab; |
252b5132 | 2358 | |
47926f60 KH |
2359 | /* Setup for loop. */ |
2360 | optab = i386_optab; | |
252b5132 RH |
2361 | core_optab = (templates *) xmalloc (sizeof (templates)); |
2362 | core_optab->start = optab; | |
2363 | ||
2364 | while (1) | |
2365 | { | |
2366 | ++optab; | |
2367 | if (optab->name == NULL | |
2368 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
2369 | { | |
2370 | /* different name --> ship out current template list; | |
47926f60 | 2371 | add to hash table; & begin anew. */ |
252b5132 RH |
2372 | core_optab->end = optab; |
2373 | hash_err = hash_insert (op_hash, | |
2374 | (optab - 1)->name, | |
5a49b8ac | 2375 | (void *) core_optab); |
252b5132 RH |
2376 | if (hash_err) |
2377 | { | |
2b5d6a91 | 2378 | as_fatal (_("internal Error: Can't hash %s: %s"), |
252b5132 RH |
2379 | (optab - 1)->name, |
2380 | hash_err); | |
2381 | } | |
2382 | if (optab->name == NULL) | |
2383 | break; | |
2384 | core_optab = (templates *) xmalloc (sizeof (templates)); | |
2385 | core_optab->start = optab; | |
2386 | } | |
2387 | } | |
2388 | } | |
2389 | ||
47926f60 | 2390 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
2391 | reg_hash = hash_new (); |
2392 | { | |
29b0f896 | 2393 | const reg_entry *regtab; |
c3fe08fa | 2394 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 2395 | |
c3fe08fa | 2396 | for (regtab = i386_regtab; regtab_size--; regtab++) |
252b5132 | 2397 | { |
5a49b8ac | 2398 | hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); |
252b5132 | 2399 | if (hash_err) |
2b5d6a91 | 2400 | as_fatal (_("internal Error: Can't hash %s: %s"), |
3e73aa7c JH |
2401 | regtab->reg_name, |
2402 | hash_err); | |
252b5132 RH |
2403 | } |
2404 | } | |
2405 | ||
47926f60 | 2406 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 2407 | { |
29b0f896 AM |
2408 | int c; |
2409 | char *p; | |
252b5132 RH |
2410 | |
2411 | for (c = 0; c < 256; c++) | |
2412 | { | |
3882b010 | 2413 | if (ISDIGIT (c)) |
252b5132 RH |
2414 | { |
2415 | digit_chars[c] = c; | |
2416 | mnemonic_chars[c] = c; | |
2417 | register_chars[c] = c; | |
2418 | operand_chars[c] = c; | |
2419 | } | |
3882b010 | 2420 | else if (ISLOWER (c)) |
252b5132 RH |
2421 | { |
2422 | mnemonic_chars[c] = c; | |
2423 | register_chars[c] = c; | |
2424 | operand_chars[c] = c; | |
2425 | } | |
3882b010 | 2426 | else if (ISUPPER (c)) |
252b5132 | 2427 | { |
3882b010 | 2428 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
2429 | register_chars[c] = mnemonic_chars[c]; |
2430 | operand_chars[c] = c; | |
2431 | } | |
2432 | ||
3882b010 | 2433 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
2434 | identifier_chars[c] = c; |
2435 | else if (c >= 128) | |
2436 | { | |
2437 | identifier_chars[c] = c; | |
2438 | operand_chars[c] = c; | |
2439 | } | |
2440 | } | |
2441 | ||
2442 | #ifdef LEX_AT | |
2443 | identifier_chars['@'] = '@'; | |
32137342 NC |
2444 | #endif |
2445 | #ifdef LEX_QM | |
2446 | identifier_chars['?'] = '?'; | |
2447 | operand_chars['?'] = '?'; | |
252b5132 | 2448 | #endif |
252b5132 | 2449 | digit_chars['-'] = '-'; |
c0f3af97 | 2450 | mnemonic_chars['_'] = '_'; |
791fe849 | 2451 | mnemonic_chars['-'] = '-'; |
0003779b | 2452 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
2453 | identifier_chars['_'] = '_'; |
2454 | identifier_chars['.'] = '.'; | |
2455 | ||
2456 | for (p = operand_special_chars; *p != '\0'; p++) | |
2457 | operand_chars[(unsigned char) *p] = *p; | |
2458 | } | |
2459 | ||
2460 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 2461 | if (IS_ELF) |
252b5132 RH |
2462 | { |
2463 | record_alignment (text_section, 2); | |
2464 | record_alignment (data_section, 2); | |
2465 | record_alignment (bss_section, 2); | |
2466 | } | |
2467 | #endif | |
a4447b93 RH |
2468 | |
2469 | if (flag_code == CODE_64BIT) | |
2470 | { | |
ca19b261 KT |
2471 | #if defined (OBJ_COFF) && defined (TE_PE) |
2472 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour | |
2473 | ? 32 : 16); | |
2474 | #else | |
a4447b93 | 2475 | x86_dwarf2_return_column = 16; |
ca19b261 | 2476 | #endif |
61ff971f | 2477 | x86_cie_data_alignment = -8; |
a4447b93 RH |
2478 | } |
2479 | else | |
2480 | { | |
2481 | x86_dwarf2_return_column = 8; | |
2482 | x86_cie_data_alignment = -4; | |
2483 | } | |
252b5132 RH |
2484 | } |
2485 | ||
2486 | void | |
e3bb37b5 | 2487 | i386_print_statistics (FILE *file) |
252b5132 RH |
2488 | { |
2489 | hash_print_statistics (file, "i386 opcode", op_hash); | |
2490 | hash_print_statistics (file, "i386 register", reg_hash); | |
2491 | } | |
2492 | \f | |
252b5132 RH |
2493 | #ifdef DEBUG386 |
2494 | ||
ce8a8b2f | 2495 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 2496 | static void pte (insn_template *); |
40fb9820 | 2497 | static void pt (i386_operand_type); |
e3bb37b5 L |
2498 | static void pe (expressionS *); |
2499 | static void ps (symbolS *); | |
252b5132 RH |
2500 | |
2501 | static void | |
e3bb37b5 | 2502 | pi (char *line, i386_insn *x) |
252b5132 | 2503 | { |
09137c09 | 2504 | unsigned int j; |
252b5132 RH |
2505 | |
2506 | fprintf (stdout, "%s: template ", line); | |
2507 | pte (&x->tm); | |
09f131f2 JH |
2508 | fprintf (stdout, " address: base %s index %s scale %x\n", |
2509 | x->base_reg ? x->base_reg->reg_name : "none", | |
2510 | x->index_reg ? x->index_reg->reg_name : "none", | |
2511 | x->log2_scale_factor); | |
2512 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 2513 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
2514 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
2515 | x->sib.base, x->sib.index, x->sib.scale); | |
2516 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
2517 | (x->rex & REX_W) != 0, |
2518 | (x->rex & REX_R) != 0, | |
2519 | (x->rex & REX_X) != 0, | |
2520 | (x->rex & REX_B) != 0); | |
09137c09 | 2521 | for (j = 0; j < x->operands; j++) |
252b5132 | 2522 | { |
09137c09 SP |
2523 | fprintf (stdout, " #%d: ", j + 1); |
2524 | pt (x->types[j]); | |
252b5132 | 2525 | fprintf (stdout, "\n"); |
09137c09 SP |
2526 | if (x->types[j].bitfield.reg8 |
2527 | || x->types[j].bitfield.reg16 | |
2528 | || x->types[j].bitfield.reg32 | |
2529 | || x->types[j].bitfield.reg64 | |
2530 | || x->types[j].bitfield.regmmx | |
2531 | || x->types[j].bitfield.regxmm | |
2532 | || x->types[j].bitfield.regymm | |
2533 | || x->types[j].bitfield.sreg2 | |
2534 | || x->types[j].bitfield.sreg3 | |
2535 | || x->types[j].bitfield.control | |
2536 | || x->types[j].bitfield.debug | |
2537 | || x->types[j].bitfield.test) | |
2538 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); | |
2539 | if (operand_type_check (x->types[j], imm)) | |
2540 | pe (x->op[j].imms); | |
2541 | if (operand_type_check (x->types[j], disp)) | |
2542 | pe (x->op[j].disps); | |
252b5132 RH |
2543 | } |
2544 | } | |
2545 | ||
2546 | static void | |
d3ce72d0 | 2547 | pte (insn_template *t) |
252b5132 | 2548 | { |
09137c09 | 2549 | unsigned int j; |
252b5132 | 2550 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 2551 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
2552 | if (t->extension_opcode != None) |
2553 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 2554 | if (t->opcode_modifier.d) |
252b5132 | 2555 | fprintf (stdout, "D"); |
40fb9820 | 2556 | if (t->opcode_modifier.w) |
252b5132 RH |
2557 | fprintf (stdout, "W"); |
2558 | fprintf (stdout, "\n"); | |
09137c09 | 2559 | for (j = 0; j < t->operands; j++) |
252b5132 | 2560 | { |
09137c09 SP |
2561 | fprintf (stdout, " #%d type ", j + 1); |
2562 | pt (t->operand_types[j]); | |
252b5132 RH |
2563 | fprintf (stdout, "\n"); |
2564 | } | |
2565 | } | |
2566 | ||
2567 | static void | |
e3bb37b5 | 2568 | pe (expressionS *e) |
252b5132 | 2569 | { |
24eab124 | 2570 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
2571 | fprintf (stdout, " add_number %ld (%lx)\n", |
2572 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
2573 | if (e->X_add_symbol) |
2574 | { | |
2575 | fprintf (stdout, " add_symbol "); | |
2576 | ps (e->X_add_symbol); | |
2577 | fprintf (stdout, "\n"); | |
2578 | } | |
2579 | if (e->X_op_symbol) | |
2580 | { | |
2581 | fprintf (stdout, " op_symbol "); | |
2582 | ps (e->X_op_symbol); | |
2583 | fprintf (stdout, "\n"); | |
2584 | } | |
2585 | } | |
2586 | ||
2587 | static void | |
e3bb37b5 | 2588 | ps (symbolS *s) |
252b5132 RH |
2589 | { |
2590 | fprintf (stdout, "%s type %s%s", | |
2591 | S_GET_NAME (s), | |
2592 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
2593 | segment_name (S_GET_SEGMENT (s))); | |
2594 | } | |
2595 | ||
7b81dfbb | 2596 | static struct type_name |
252b5132 | 2597 | { |
40fb9820 L |
2598 | i386_operand_type mask; |
2599 | const char *name; | |
252b5132 | 2600 | } |
7b81dfbb | 2601 | const type_names[] = |
252b5132 | 2602 | { |
40fb9820 L |
2603 | { OPERAND_TYPE_REG8, "r8" }, |
2604 | { OPERAND_TYPE_REG16, "r16" }, | |
2605 | { OPERAND_TYPE_REG32, "r32" }, | |
2606 | { OPERAND_TYPE_REG64, "r64" }, | |
2607 | { OPERAND_TYPE_IMM8, "i8" }, | |
2608 | { OPERAND_TYPE_IMM8, "i8s" }, | |
2609 | { OPERAND_TYPE_IMM16, "i16" }, | |
2610 | { OPERAND_TYPE_IMM32, "i32" }, | |
2611 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
2612 | { OPERAND_TYPE_IMM64, "i64" }, | |
2613 | { OPERAND_TYPE_IMM1, "i1" }, | |
2614 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
2615 | { OPERAND_TYPE_DISP8, "d8" }, | |
2616 | { OPERAND_TYPE_DISP16, "d16" }, | |
2617 | { OPERAND_TYPE_DISP32, "d32" }, | |
2618 | { OPERAND_TYPE_DISP32S, "d32s" }, | |
2619 | { OPERAND_TYPE_DISP64, "d64" }, | |
2620 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, | |
2621 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
2622 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
2623 | { OPERAND_TYPE_TEST, "test reg" }, | |
2624 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
2625 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
2626 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
2627 | { OPERAND_TYPE_SREG2, "SReg2" }, | |
2628 | { OPERAND_TYPE_SREG3, "SReg3" }, | |
2629 | { OPERAND_TYPE_ACC, "Acc" }, | |
2630 | { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" }, | |
2631 | { OPERAND_TYPE_REGMMX, "rMMX" }, | |
2632 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
0349dc08 | 2633 | { OPERAND_TYPE_REGYMM, "rYMM" }, |
40fb9820 | 2634 | { OPERAND_TYPE_ESSEG, "es" }, |
252b5132 RH |
2635 | }; |
2636 | ||
2637 | static void | |
40fb9820 | 2638 | pt (i386_operand_type t) |
252b5132 | 2639 | { |
40fb9820 | 2640 | unsigned int j; |
c6fb90c8 | 2641 | i386_operand_type a; |
252b5132 | 2642 | |
40fb9820 | 2643 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
2644 | { |
2645 | a = operand_type_and (t, type_names[j].mask); | |
0349dc08 | 2646 | if (!operand_type_all_zero (&a)) |
c6fb90c8 L |
2647 | fprintf (stdout, "%s, ", type_names[j].name); |
2648 | } | |
252b5132 RH |
2649 | fflush (stdout); |
2650 | } | |
2651 | ||
2652 | #endif /* DEBUG386 */ | |
2653 | \f | |
252b5132 | 2654 | static bfd_reloc_code_real_type |
3956db08 | 2655 | reloc (unsigned int size, |
64e74474 AM |
2656 | int pcrel, |
2657 | int sign, | |
2658 | bfd_reloc_code_real_type other) | |
252b5132 | 2659 | { |
47926f60 | 2660 | if (other != NO_RELOC) |
3956db08 | 2661 | { |
91d6fa6a | 2662 | reloc_howto_type *rel; |
3956db08 JB |
2663 | |
2664 | if (size == 8) | |
2665 | switch (other) | |
2666 | { | |
64e74474 AM |
2667 | case BFD_RELOC_X86_64_GOT32: |
2668 | return BFD_RELOC_X86_64_GOT64; | |
2669 | break; | |
2670 | case BFD_RELOC_X86_64_PLTOFF64: | |
2671 | return BFD_RELOC_X86_64_PLTOFF64; | |
2672 | break; | |
2673 | case BFD_RELOC_X86_64_GOTPC32: | |
2674 | other = BFD_RELOC_X86_64_GOTPC64; | |
2675 | break; | |
2676 | case BFD_RELOC_X86_64_GOTPCREL: | |
2677 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
2678 | break; | |
2679 | case BFD_RELOC_X86_64_TPOFF32: | |
2680 | other = BFD_RELOC_X86_64_TPOFF64; | |
2681 | break; | |
2682 | case BFD_RELOC_X86_64_DTPOFF32: | |
2683 | other = BFD_RELOC_X86_64_DTPOFF64; | |
2684 | break; | |
2685 | default: | |
2686 | break; | |
3956db08 | 2687 | } |
e05278af JB |
2688 | |
2689 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ | |
f2d8a97c | 2690 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
e05278af JB |
2691 | sign = -1; |
2692 | ||
91d6fa6a NC |
2693 | rel = bfd_reloc_type_lookup (stdoutput, other); |
2694 | if (!rel) | |
3956db08 | 2695 | as_bad (_("unknown relocation (%u)"), other); |
91d6fa6a | 2696 | else if (size != bfd_get_reloc_size (rel)) |
3956db08 | 2697 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
91d6fa6a | 2698 | bfd_get_reloc_size (rel), |
3956db08 | 2699 | size); |
91d6fa6a | 2700 | else if (pcrel && !rel->pc_relative) |
3956db08 | 2701 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
91d6fa6a | 2702 | else if ((rel->complain_on_overflow == complain_overflow_signed |
3956db08 | 2703 | && !sign) |
91d6fa6a | 2704 | || (rel->complain_on_overflow == complain_overflow_unsigned |
64e74474 | 2705 | && sign > 0)) |
3956db08 JB |
2706 | as_bad (_("relocated field and relocation type differ in signedness")); |
2707 | else | |
2708 | return other; | |
2709 | return NO_RELOC; | |
2710 | } | |
252b5132 RH |
2711 | |
2712 | if (pcrel) | |
2713 | { | |
3e73aa7c | 2714 | if (!sign) |
3956db08 | 2715 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
2716 | switch (size) |
2717 | { | |
2718 | case 1: return BFD_RELOC_8_PCREL; | |
2719 | case 2: return BFD_RELOC_16_PCREL; | |
2720 | case 4: return BFD_RELOC_32_PCREL; | |
d6ab8113 | 2721 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 2722 | } |
3956db08 | 2723 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
2724 | } |
2725 | else | |
2726 | { | |
3956db08 | 2727 | if (sign > 0) |
e5cb08ac | 2728 | switch (size) |
3e73aa7c JH |
2729 | { |
2730 | case 4: return BFD_RELOC_X86_64_32S; | |
2731 | } | |
2732 | else | |
2733 | switch (size) | |
2734 | { | |
2735 | case 1: return BFD_RELOC_8; | |
2736 | case 2: return BFD_RELOC_16; | |
2737 | case 4: return BFD_RELOC_32; | |
2738 | case 8: return BFD_RELOC_64; | |
2739 | } | |
3956db08 JB |
2740 | as_bad (_("cannot do %s %u byte relocation"), |
2741 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
2742 | } |
2743 | ||
0cc9e1d3 | 2744 | return NO_RELOC; |
252b5132 RH |
2745 | } |
2746 | ||
47926f60 KH |
2747 | /* Here we decide which fixups can be adjusted to make them relative to |
2748 | the beginning of the section instead of the symbol. Basically we need | |
2749 | to make sure that the dynamic relocations are done correctly, so in | |
2750 | some cases we force the original symbol to be used. */ | |
2751 | ||
252b5132 | 2752 | int |
e3bb37b5 | 2753 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 2754 | { |
6d249963 | 2755 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 2756 | if (!IS_ELF) |
31312f95 AM |
2757 | return 1; |
2758 | ||
a161fe53 AM |
2759 | /* Don't adjust pc-relative references to merge sections in 64-bit |
2760 | mode. */ | |
2761 | if (use_rela_relocations | |
2762 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
2763 | && fixP->fx_pcrel) | |
252b5132 | 2764 | return 0; |
31312f95 | 2765 | |
8d01d9a9 AJ |
2766 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
2767 | and changed later by validate_fix. */ | |
2768 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
2769 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
2770 | return 0; | |
2771 | ||
ce8a8b2f | 2772 | /* adjust_reloc_syms doesn't know about the GOT. */ |
252b5132 RH |
2773 | if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF |
2774 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 | |
2775 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
13ae64f3 JJ |
2776 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
2777 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
2778 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
2779 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
2780 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
2781 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
2782 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
2783 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
2784 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
2785 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c JH |
2786 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
2787 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
80b3ee89 | 2788 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
bffbf940 JJ |
2789 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
2790 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
2791 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 2792 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
2793 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
2794 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
2795 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
2796 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
2797 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
2798 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
2799 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
2800 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
2801 | return 0; | |
31312f95 | 2802 | #endif |
252b5132 RH |
2803 | return 1; |
2804 | } | |
252b5132 | 2805 | |
b4cac588 | 2806 | static int |
e3bb37b5 | 2807 | intel_float_operand (const char *mnemonic) |
252b5132 | 2808 | { |
9306ca4a JB |
2809 | /* Note that the value returned is meaningful only for opcodes with (memory) |
2810 | operands, hence the code here is free to improperly handle opcodes that | |
2811 | have no operands (for better performance and smaller code). */ | |
2812 | ||
2813 | if (mnemonic[0] != 'f') | |
2814 | return 0; /* non-math */ | |
2815 | ||
2816 | switch (mnemonic[1]) | |
2817 | { | |
2818 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
2819 | the fs segment override prefix not currently handled because no | |
2820 | call path can make opcodes without operands get here */ | |
2821 | case 'i': | |
2822 | return 2 /* integer op */; | |
2823 | case 'l': | |
2824 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
2825 | return 3; /* fldcw/fldenv */ | |
2826 | break; | |
2827 | case 'n': | |
2828 | if (mnemonic[2] != 'o' /* fnop */) | |
2829 | return 3; /* non-waiting control op */ | |
2830 | break; | |
2831 | case 'r': | |
2832 | if (mnemonic[2] == 's') | |
2833 | return 3; /* frstor/frstpm */ | |
2834 | break; | |
2835 | case 's': | |
2836 | if (mnemonic[2] == 'a') | |
2837 | return 3; /* fsave */ | |
2838 | if (mnemonic[2] == 't') | |
2839 | { | |
2840 | switch (mnemonic[3]) | |
2841 | { | |
2842 | case 'c': /* fstcw */ | |
2843 | case 'd': /* fstdw */ | |
2844 | case 'e': /* fstenv */ | |
2845 | case 's': /* fsts[gw] */ | |
2846 | return 3; | |
2847 | } | |
2848 | } | |
2849 | break; | |
2850 | case 'x': | |
2851 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
2852 | return 0; /* fxsave/fxrstor are not really math ops */ | |
2853 | break; | |
2854 | } | |
252b5132 | 2855 | |
9306ca4a | 2856 | return 1; |
252b5132 RH |
2857 | } |
2858 | ||
c0f3af97 L |
2859 | /* Build the VEX prefix. */ |
2860 | ||
2861 | static void | |
d3ce72d0 | 2862 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
2863 | { |
2864 | unsigned int register_specifier; | |
2865 | unsigned int implied_prefix; | |
2866 | unsigned int vector_length; | |
2867 | ||
2868 | /* Check register specifier. */ | |
2869 | if (i.vex.register_specifier) | |
4c692bc7 | 2870 | register_specifier = ~register_number (i.vex.register_specifier) & 0xf; |
c0f3af97 L |
2871 | else |
2872 | register_specifier = 0xf; | |
2873 | ||
fa99fab2 L |
2874 | /* Use 2-byte VEX prefix by swappping destination and source |
2875 | operand. */ | |
2876 | if (!i.swap_operand | |
2877 | && i.operands == i.reg_operands | |
7f399153 | 2878 | && i.tm.opcode_modifier.vexopcode == VEX0F |
fa99fab2 L |
2879 | && i.tm.opcode_modifier.s |
2880 | && i.rex == REX_B) | |
2881 | { | |
2882 | unsigned int xchg = i.operands - 1; | |
2883 | union i386_op temp_op; | |
2884 | i386_operand_type temp_type; | |
2885 | ||
2886 | temp_type = i.types[xchg]; | |
2887 | i.types[xchg] = i.types[0]; | |
2888 | i.types[0] = temp_type; | |
2889 | temp_op = i.op[xchg]; | |
2890 | i.op[xchg] = i.op[0]; | |
2891 | i.op[0] = temp_op; | |
2892 | ||
9c2799c2 | 2893 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
2894 | |
2895 | i.rex = REX_R; | |
2896 | xchg = i.rm.regmem; | |
2897 | i.rm.regmem = i.rm.reg; | |
2898 | i.rm.reg = xchg; | |
2899 | ||
2900 | /* Use the next insn. */ | |
2901 | i.tm = t[1]; | |
2902 | } | |
2903 | ||
539f890d L |
2904 | if (i.tm.opcode_modifier.vex == VEXScalar) |
2905 | vector_length = avxscalar; | |
2906 | else | |
2907 | vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0; | |
c0f3af97 L |
2908 | |
2909 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
2910 | { | |
2911 | case 0: | |
2912 | implied_prefix = 0; | |
2913 | break; | |
2914 | case DATA_PREFIX_OPCODE: | |
2915 | implied_prefix = 1; | |
2916 | break; | |
2917 | case REPE_PREFIX_OPCODE: | |
2918 | implied_prefix = 2; | |
2919 | break; | |
2920 | case REPNE_PREFIX_OPCODE: | |
2921 | implied_prefix = 3; | |
2922 | break; | |
2923 | default: | |
2924 | abort (); | |
2925 | } | |
2926 | ||
2927 | /* Use 2-byte VEX prefix if possible. */ | |
7f399153 | 2928 | if (i.tm.opcode_modifier.vexopcode == VEX0F |
04251de0 | 2929 | && i.tm.opcode_modifier.vexw != VEXW1 |
c0f3af97 L |
2930 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
2931 | { | |
2932 | /* 2-byte VEX prefix. */ | |
2933 | unsigned int r; | |
2934 | ||
2935 | i.vex.length = 2; | |
2936 | i.vex.bytes[0] = 0xc5; | |
2937 | ||
2938 | /* Check the REX.R bit. */ | |
2939 | r = (i.rex & REX_R) ? 0 : 1; | |
2940 | i.vex.bytes[1] = (r << 7 | |
2941 | | register_specifier << 3 | |
2942 | | vector_length << 2 | |
2943 | | implied_prefix); | |
2944 | } | |
2945 | else | |
2946 | { | |
2947 | /* 3-byte VEX prefix. */ | |
2948 | unsigned int m, w; | |
2949 | ||
f88c9eb0 | 2950 | i.vex.length = 3; |
f88c9eb0 | 2951 | |
7f399153 | 2952 | switch (i.tm.opcode_modifier.vexopcode) |
5dd85c99 | 2953 | { |
7f399153 L |
2954 | case VEX0F: |
2955 | m = 0x1; | |
80de6e00 | 2956 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
2957 | break; |
2958 | case VEX0F38: | |
2959 | m = 0x2; | |
80de6e00 | 2960 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
2961 | break; |
2962 | case VEX0F3A: | |
2963 | m = 0x3; | |
80de6e00 | 2964 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
2965 | break; |
2966 | case XOP08: | |
5dd85c99 SP |
2967 | m = 0x8; |
2968 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
2969 | break; |
2970 | case XOP09: | |
f88c9eb0 SP |
2971 | m = 0x9; |
2972 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
2973 | break; |
2974 | case XOP0A: | |
f88c9eb0 SP |
2975 | m = 0xa; |
2976 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
2977 | break; |
2978 | default: | |
2979 | abort (); | |
f88c9eb0 | 2980 | } |
c0f3af97 | 2981 | |
c0f3af97 L |
2982 | /* The high 3 bits of the second VEX byte are 1's compliment |
2983 | of RXB bits from REX. */ | |
2984 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
2985 | ||
2986 | /* Check the REX.W bit. */ | |
2987 | w = (i.rex & REX_W) ? 1 : 0; | |
1ef99a7b | 2988 | if (i.tm.opcode_modifier.vexw) |
c0f3af97 L |
2989 | { |
2990 | if (w) | |
2991 | abort (); | |
2992 | ||
1ef99a7b | 2993 | if (i.tm.opcode_modifier.vexw == VEXW1) |
c0f3af97 L |
2994 | w = 1; |
2995 | } | |
2996 | ||
2997 | i.vex.bytes[2] = (w << 7 | |
2998 | | register_specifier << 3 | |
2999 | | vector_length << 2 | |
3000 | | implied_prefix); | |
3001 | } | |
3002 | } | |
3003 | ||
65da13b5 L |
3004 | static void |
3005 | process_immext (void) | |
3006 | { | |
3007 | expressionS *exp; | |
3008 | ||
4c692bc7 JB |
3009 | if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme) |
3010 | && i.operands > 0) | |
65da13b5 | 3011 | { |
4c692bc7 JB |
3012 | /* MONITOR/MWAIT as well as SVME instructions have fixed operands |
3013 | with an opcode suffix which is coded in the same place as an | |
3014 | 8-bit immediate field would be. | |
3015 | Here we check those operands and remove them afterwards. */ | |
65da13b5 L |
3016 | unsigned int x; |
3017 | ||
3018 | for (x = 0; x < i.operands; x++) | |
4c692bc7 | 3019 | if (register_number (i.op[x].regs) != x) |
65da13b5 | 3020 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), |
1fed0ba1 L |
3021 | register_prefix, i.op[x].regs->reg_name, x + 1, |
3022 | i.tm.name); | |
3023 | ||
3024 | i.operands = 0; | |
65da13b5 L |
3025 | } |
3026 | ||
c0f3af97 | 3027 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
3028 | which is coded in the same place as an 8-bit immediate field |
3029 | would be. Here we fake an 8-bit immediate operand from the | |
3030 | opcode suffix stored in tm.extension_opcode. | |
3031 | ||
c1e679ec | 3032 | AVX instructions also use this encoding, for some of |
c0f3af97 | 3033 | 3 argument instructions. */ |
65da13b5 | 3034 | |
9c2799c2 | 3035 | gas_assert (i.imm_operands == 0 |
7ab9ffdd L |
3036 | && (i.operands <= 2 |
3037 | || (i.tm.opcode_modifier.vex | |
3038 | && i.operands <= 4))); | |
65da13b5 L |
3039 | |
3040 | exp = &im_expressions[i.imm_operands++]; | |
3041 | i.op[i.operands].imms = exp; | |
3042 | i.types[i.operands] = imm8; | |
3043 | i.operands++; | |
3044 | exp->X_op = O_constant; | |
3045 | exp->X_add_number = i.tm.extension_opcode; | |
3046 | i.tm.extension_opcode = None; | |
3047 | } | |
3048 | ||
42164a71 L |
3049 | |
3050 | static int | |
3051 | check_hle (void) | |
3052 | { | |
3053 | switch (i.tm.opcode_modifier.hleprefixok) | |
3054 | { | |
3055 | default: | |
3056 | abort (); | |
82c2def5 | 3057 | case HLEPrefixNone: |
42164a71 L |
3058 | if (i.prefix[HLE_PREFIX] == XACQUIRE_PREFIX_OPCODE) |
3059 | as_bad (_("invalid instruction `%s' after `xacquire'"), | |
3060 | i.tm.name); | |
3061 | else | |
3062 | as_bad (_("invalid instruction `%s' after `xrelease'"), | |
3063 | i.tm.name); | |
3064 | return 0; | |
82c2def5 | 3065 | case HLEPrefixLock: |
42164a71 L |
3066 | if (i.prefix[LOCK_PREFIX]) |
3067 | return 1; | |
3068 | if (i.prefix[HLE_PREFIX] == XACQUIRE_PREFIX_OPCODE) | |
3069 | as_bad (_("missing `lock' with `xacquire'")); | |
3070 | else | |
3071 | as_bad (_("missing `lock' with `xrelease'")); | |
3072 | return 0; | |
82c2def5 | 3073 | case HLEPrefixAny: |
42164a71 | 3074 | return 1; |
82c2def5 | 3075 | case HLEPrefixRelease: |
42164a71 L |
3076 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
3077 | { | |
3078 | as_bad (_("instruction `%s' after `xacquire' not allowed"), | |
3079 | i.tm.name); | |
3080 | return 0; | |
3081 | } | |
3082 | if (i.mem_operands == 0 | |
3083 | || !operand_type_check (i.types[i.operands - 1], anymem)) | |
3084 | { | |
3085 | as_bad (_("memory destination needed for instruction `%s'" | |
3086 | " after `xrelease'"), i.tm.name); | |
3087 | return 0; | |
3088 | } | |
3089 | return 1; | |
3090 | } | |
3091 | } | |
3092 | ||
252b5132 RH |
3093 | /* This is the guts of the machine-dependent assembler. LINE points to a |
3094 | machine dependent instruction. This function is supposed to emit | |
3095 | the frags/bytes it assembles to. */ | |
3096 | ||
3097 | void | |
65da13b5 | 3098 | md_assemble (char *line) |
252b5132 | 3099 | { |
40fb9820 | 3100 | unsigned int j; |
252b5132 | 3101 | char mnemonic[MAX_MNEM_SIZE]; |
d3ce72d0 | 3102 | const insn_template *t; |
252b5132 | 3103 | |
47926f60 | 3104 | /* Initialize globals. */ |
252b5132 RH |
3105 | memset (&i, '\0', sizeof (i)); |
3106 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 3107 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
3108 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
3109 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 3110 | save_stack_p = save_stack; |
252b5132 RH |
3111 | |
3112 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
3113 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 3114 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 3115 | |
29b0f896 AM |
3116 | line = parse_insn (line, mnemonic); |
3117 | if (line == NULL) | |
3118 | return; | |
252b5132 | 3119 | |
29b0f896 | 3120 | line = parse_operands (line, mnemonic); |
ee86248c | 3121 | this_operand = -1; |
29b0f896 AM |
3122 | if (line == NULL) |
3123 | return; | |
252b5132 | 3124 | |
29b0f896 AM |
3125 | /* Now we've parsed the mnemonic into a set of templates, and have the |
3126 | operands at hand. */ | |
3127 | ||
3128 | /* All intel opcodes have reversed operands except for "bound" and | |
3129 | "enter". We also don't reverse intersegment "jmp" and "call" | |
3130 | instructions with 2 immediate operands so that the immediate segment | |
050dfa73 | 3131 | precedes the offset, as it does when in AT&T mode. */ |
4d456e3d L |
3132 | if (intel_syntax |
3133 | && i.operands > 1 | |
29b0f896 | 3134 | && (strcmp (mnemonic, "bound") != 0) |
30123838 | 3135 | && (strcmp (mnemonic, "invlpga") != 0) |
40fb9820 L |
3136 | && !(operand_type_check (i.types[0], imm) |
3137 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
3138 | swap_operands (); |
3139 | ||
ec56d5c0 JB |
3140 | /* The order of the immediates should be reversed |
3141 | for 2 immediates extrq and insertq instructions */ | |
3142 | if (i.imm_operands == 2 | |
3143 | && (strcmp (mnemonic, "extrq") == 0 | |
3144 | || strcmp (mnemonic, "insertq") == 0)) | |
3145 | swap_2_operands (0, 1); | |
3146 | ||
29b0f896 AM |
3147 | if (i.imm_operands) |
3148 | optimize_imm (); | |
3149 | ||
b300c311 L |
3150 | /* Don't optimize displacement for movabs since it only takes 64bit |
3151 | displacement. */ | |
3152 | if (i.disp_operands | |
a501d77e | 3153 | && i.disp_encoding != disp_encoding_32bit |
862be3fb L |
3154 | && (flag_code != CODE_64BIT |
3155 | || strcmp (mnemonic, "movabs") != 0)) | |
3156 | optimize_disp (); | |
29b0f896 AM |
3157 | |
3158 | /* Next, we find a template that matches the given insn, | |
3159 | making sure the overlap of the given operands types is consistent | |
3160 | with the template operand types. */ | |
252b5132 | 3161 | |
fa99fab2 | 3162 | if (!(t = match_template ())) |
29b0f896 | 3163 | return; |
252b5132 | 3164 | |
7bab8ab5 | 3165 | if (sse_check != check_none |
81f8a913 | 3166 | && !i.tm.opcode_modifier.noavx |
daf50ae7 L |
3167 | && (i.tm.cpu_flags.bitfield.cpusse |
3168 | || i.tm.cpu_flags.bitfield.cpusse2 | |
3169 | || i.tm.cpu_flags.bitfield.cpusse3 | |
3170 | || i.tm.cpu_flags.bitfield.cpussse3 | |
3171 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
3172 | || i.tm.cpu_flags.bitfield.cpusse4_2)) | |
3173 | { | |
7bab8ab5 | 3174 | (sse_check == check_warning |
daf50ae7 L |
3175 | ? as_warn |
3176 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); | |
3177 | } | |
3178 | ||
321fd21e L |
3179 | /* Zap movzx and movsx suffix. The suffix has been set from |
3180 | "word ptr" or "byte ptr" on the source operand in Intel syntax | |
3181 | or extracted from mnemonic in AT&T syntax. But we'll use | |
3182 | the destination register to choose the suffix for encoding. */ | |
3183 | if ((i.tm.base_opcode & ~9) == 0x0fb6) | |
cd61ebfe | 3184 | { |
321fd21e L |
3185 | /* In Intel syntax, there must be a suffix. In AT&T syntax, if |
3186 | there is no suffix, the default will be byte extension. */ | |
3187 | if (i.reg_operands != 2 | |
3188 | && !i.suffix | |
7ab9ffdd | 3189 | && intel_syntax) |
321fd21e L |
3190 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
3191 | ||
3192 | i.suffix = 0; | |
cd61ebfe | 3193 | } |
24eab124 | 3194 | |
40fb9820 | 3195 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
3196 | if (!add_prefix (FWAIT_OPCODE)) |
3197 | return; | |
252b5132 | 3198 | |
c1ba0266 L |
3199 | /* Check for lock without a lockable instruction. Destination operand |
3200 | must be memory unless it is xchg (0x86). */ | |
c32fa91d L |
3201 | if (i.prefix[LOCK_PREFIX] |
3202 | && (!i.tm.opcode_modifier.islockable | |
c1ba0266 L |
3203 | || i.mem_operands == 0 |
3204 | || (i.tm.base_opcode != 0x86 | |
3205 | && !operand_type_check (i.types[i.operands - 1], anymem)))) | |
c32fa91d L |
3206 | { |
3207 | as_bad (_("expecting lockable instruction after `lock'")); | |
3208 | return; | |
3209 | } | |
3210 | ||
42164a71 L |
3211 | /* Check if HLE prefix is OK. */ |
3212 | if (i.have_hle && !check_hle ()) | |
3213 | return; | |
3214 | ||
29b0f896 | 3215 | /* Check string instruction segment overrides. */ |
40fb9820 | 3216 | if (i.tm.opcode_modifier.isstring && i.mem_operands != 0) |
29b0f896 AM |
3217 | { |
3218 | if (!check_string ()) | |
5dd0794d | 3219 | return; |
fc0763e6 | 3220 | i.disp_operands = 0; |
29b0f896 | 3221 | } |
5dd0794d | 3222 | |
29b0f896 AM |
3223 | if (!process_suffix ()) |
3224 | return; | |
e413e4e9 | 3225 | |
bc0844ae L |
3226 | /* Update operand types. */ |
3227 | for (j = 0; j < i.operands; j++) | |
3228 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
3229 | ||
29b0f896 AM |
3230 | /* Make still unresolved immediate matches conform to size of immediate |
3231 | given in i.suffix. */ | |
3232 | if (!finalize_imm ()) | |
3233 | return; | |
252b5132 | 3234 | |
40fb9820 | 3235 | if (i.types[0].bitfield.imm1) |
29b0f896 | 3236 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 3237 | |
9afe6eb8 L |
3238 | /* We only need to check those implicit registers for instructions |
3239 | with 3 operands or less. */ | |
3240 | if (i.operands <= 3) | |
3241 | for (j = 0; j < i.operands; j++) | |
3242 | if (i.types[j].bitfield.inoutportreg | |
3243 | || i.types[j].bitfield.shiftcount | |
3244 | || i.types[j].bitfield.acc | |
3245 | || i.types[j].bitfield.floatacc) | |
3246 | i.reg_operands--; | |
40fb9820 | 3247 | |
c0f3af97 L |
3248 | /* ImmExt should be processed after SSE2AVX. */ |
3249 | if (!i.tm.opcode_modifier.sse2avx | |
3250 | && i.tm.opcode_modifier.immext) | |
65da13b5 | 3251 | process_immext (); |
252b5132 | 3252 | |
29b0f896 AM |
3253 | /* For insns with operands there are more diddles to do to the opcode. */ |
3254 | if (i.operands) | |
3255 | { | |
3256 | if (!process_operands ()) | |
3257 | return; | |
3258 | } | |
40fb9820 | 3259 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
3260 | { |
3261 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
3262 | as_warn (_("translating to `%sp'"), i.tm.name); | |
3263 | } | |
252b5132 | 3264 | |
c0f3af97 | 3265 | if (i.tm.opcode_modifier.vex) |
fa99fab2 | 3266 | build_vex_prefix (t); |
c0f3af97 | 3267 | |
5dd85c99 SP |
3268 | /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 |
3269 | instructions may define INT_OPCODE as well, so avoid this corner | |
3270 | case for those instructions that use MODRM. */ | |
3271 | if (i.tm.base_opcode == INT_OPCODE | |
a6461c02 SP |
3272 | && !i.tm.opcode_modifier.modrm |
3273 | && i.op[0].imms->X_add_number == 3) | |
29b0f896 AM |
3274 | { |
3275 | i.tm.base_opcode = INT3_OPCODE; | |
3276 | i.imm_operands = 0; | |
3277 | } | |
252b5132 | 3278 | |
40fb9820 L |
3279 | if ((i.tm.opcode_modifier.jump |
3280 | || i.tm.opcode_modifier.jumpbyte | |
3281 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 AM |
3282 | && i.op[0].disps->X_op == O_constant) |
3283 | { | |
3284 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
3285 | the absolute address given by the constant. Since ix86 jumps and | |
3286 | calls are pc relative, we need to generate a reloc. */ | |
3287 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
3288 | i.op[0].disps->X_op = O_symbol; | |
3289 | } | |
252b5132 | 3290 | |
40fb9820 | 3291 | if (i.tm.opcode_modifier.rex64) |
161a04f6 | 3292 | i.rex |= REX_W; |
252b5132 | 3293 | |
29b0f896 AM |
3294 | /* For 8 bit registers we need an empty rex prefix. Also if the |
3295 | instruction already has a prefix, we need to convert old | |
3296 | registers to new ones. */ | |
773f551c | 3297 | |
40fb9820 | 3298 | if ((i.types[0].bitfield.reg8 |
29b0f896 | 3299 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
40fb9820 | 3300 | || (i.types[1].bitfield.reg8 |
29b0f896 | 3301 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
40fb9820 L |
3302 | || ((i.types[0].bitfield.reg8 |
3303 | || i.types[1].bitfield.reg8) | |
29b0f896 AM |
3304 | && i.rex != 0)) |
3305 | { | |
3306 | int x; | |
726c5dcd | 3307 | |
29b0f896 AM |
3308 | i.rex |= REX_OPCODE; |
3309 | for (x = 0; x < 2; x++) | |
3310 | { | |
3311 | /* Look for 8 bit operand that uses old registers. */ | |
40fb9820 | 3312 | if (i.types[x].bitfield.reg8 |
29b0f896 | 3313 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 3314 | { |
29b0f896 AM |
3315 | /* In case it is "hi" register, give up. */ |
3316 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 3317 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 3318 | "instruction requiring REX prefix."), |
a540244d | 3319 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 3320 | |
29b0f896 AM |
3321 | /* Otherwise it is equivalent to the extended register. |
3322 | Since the encoding doesn't change this is merely | |
3323 | cosmetic cleanup for debug output. */ | |
3324 | ||
3325 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 3326 | } |
29b0f896 AM |
3327 | } |
3328 | } | |
773f551c | 3329 | |
7ab9ffdd | 3330 | if (i.rex != 0) |
29b0f896 AM |
3331 | add_prefix (REX_OPCODE | i.rex); |
3332 | ||
3333 | /* We are ready to output the insn. */ | |
3334 | output_insn (); | |
3335 | } | |
3336 | ||
3337 | static char * | |
e3bb37b5 | 3338 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
3339 | { |
3340 | char *l = line; | |
3341 | char *token_start = l; | |
3342 | char *mnem_p; | |
5c6af06e | 3343 | int supported; |
d3ce72d0 | 3344 | const insn_template *t; |
b6169b20 | 3345 | char *dot_p = NULL; |
29b0f896 AM |
3346 | |
3347 | /* Non-zero if we found a prefix only acceptable with string insns. */ | |
3348 | const char *expecting_string_instruction = NULL; | |
45288df1 | 3349 | |
29b0f896 AM |
3350 | while (1) |
3351 | { | |
3352 | mnem_p = mnemonic; | |
3353 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
3354 | { | |
b6169b20 L |
3355 | if (*mnem_p == '.') |
3356 | dot_p = mnem_p; | |
29b0f896 AM |
3357 | mnem_p++; |
3358 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 3359 | { |
29b0f896 AM |
3360 | as_bad (_("no such instruction: `%s'"), token_start); |
3361 | return NULL; | |
3362 | } | |
3363 | l++; | |
3364 | } | |
3365 | if (!is_space_char (*l) | |
3366 | && *l != END_OF_INSN | |
e44823cf JB |
3367 | && (intel_syntax |
3368 | || (*l != PREFIX_SEPARATOR | |
3369 | && *l != ','))) | |
29b0f896 AM |
3370 | { |
3371 | as_bad (_("invalid character %s in mnemonic"), | |
3372 | output_invalid (*l)); | |
3373 | return NULL; | |
3374 | } | |
3375 | if (token_start == l) | |
3376 | { | |
e44823cf | 3377 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
3378 | as_bad (_("expecting prefix; got nothing")); |
3379 | else | |
3380 | as_bad (_("expecting mnemonic; got nothing")); | |
3381 | return NULL; | |
3382 | } | |
45288df1 | 3383 | |
29b0f896 | 3384 | /* Look up instruction (or prefix) via hash table. */ |
d3ce72d0 | 3385 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
47926f60 | 3386 | |
29b0f896 AM |
3387 | if (*l != END_OF_INSN |
3388 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
3389 | && current_templates | |
40fb9820 | 3390 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 3391 | { |
c6fb90c8 | 3392 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
3393 | { |
3394 | as_bad ((flag_code != CODE_64BIT | |
3395 | ? _("`%s' is only supported in 64-bit mode") | |
3396 | : _("`%s' is not supported in 64-bit mode")), | |
3397 | current_templates->start->name); | |
3398 | return NULL; | |
3399 | } | |
29b0f896 AM |
3400 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
3401 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
40fb9820 L |
3402 | if ((current_templates->start->opcode_modifier.size16 |
3403 | || current_templates->start->opcode_modifier.size32) | |
29b0f896 | 3404 | && flag_code != CODE_64BIT |
40fb9820 | 3405 | && (current_templates->start->opcode_modifier.size32 |
29b0f896 AM |
3406 | ^ (flag_code == CODE_16BIT))) |
3407 | { | |
3408 | as_bad (_("redundant %s prefix"), | |
3409 | current_templates->start->name); | |
3410 | return NULL; | |
45288df1 | 3411 | } |
29b0f896 AM |
3412 | /* Add prefix, checking for repeated prefixes. */ |
3413 | switch (add_prefix (current_templates->start->base_opcode)) | |
3414 | { | |
c32fa91d | 3415 | case PREFIX_EXIST: |
29b0f896 | 3416 | return NULL; |
c32fa91d | 3417 | case PREFIX_REP: |
42164a71 L |
3418 | if (current_templates->start->cpu_flags.bitfield.cpuhle) |
3419 | i.have_hle = 1; | |
3420 | else | |
3421 | expecting_string_instruction = current_templates->start->name; | |
29b0f896 | 3422 | break; |
c32fa91d L |
3423 | default: |
3424 | break; | |
29b0f896 AM |
3425 | } |
3426 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
3427 | token_start = ++l; | |
3428 | } | |
3429 | else | |
3430 | break; | |
3431 | } | |
45288df1 | 3432 | |
30a55f88 | 3433 | if (!current_templates) |
b6169b20 | 3434 | { |
f8a5c266 L |
3435 | /* Check if we should swap operand or force 32bit displacement in |
3436 | encoding. */ | |
30a55f88 L |
3437 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
3438 | i.swap_operand = 1; | |
8d63c93e | 3439 | else if (mnem_p - 3 == dot_p |
a501d77e L |
3440 | && dot_p[1] == 'd' |
3441 | && dot_p[2] == '8') | |
3442 | i.disp_encoding = disp_encoding_8bit; | |
8d63c93e | 3443 | else if (mnem_p - 4 == dot_p |
f8a5c266 L |
3444 | && dot_p[1] == 'd' |
3445 | && dot_p[2] == '3' | |
3446 | && dot_p[3] == '2') | |
a501d77e | 3447 | i.disp_encoding = disp_encoding_32bit; |
30a55f88 L |
3448 | else |
3449 | goto check_suffix; | |
3450 | mnem_p = dot_p; | |
3451 | *dot_p = '\0'; | |
d3ce72d0 | 3452 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
b6169b20 L |
3453 | } |
3454 | ||
29b0f896 AM |
3455 | if (!current_templates) |
3456 | { | |
b6169b20 | 3457 | check_suffix: |
29b0f896 AM |
3458 | /* See if we can get a match by trimming off a suffix. */ |
3459 | switch (mnem_p[-1]) | |
3460 | { | |
3461 | case WORD_MNEM_SUFFIX: | |
9306ca4a JB |
3462 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) |
3463 | i.suffix = SHORT_MNEM_SUFFIX; | |
3464 | else | |
29b0f896 AM |
3465 | case BYTE_MNEM_SUFFIX: |
3466 | case QWORD_MNEM_SUFFIX: | |
3467 | i.suffix = mnem_p[-1]; | |
3468 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
3469 | current_templates = (const templates *) hash_find (op_hash, |
3470 | mnemonic); | |
29b0f896 AM |
3471 | break; |
3472 | case SHORT_MNEM_SUFFIX: | |
3473 | case LONG_MNEM_SUFFIX: | |
3474 | if (!intel_syntax) | |
3475 | { | |
3476 | i.suffix = mnem_p[-1]; | |
3477 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
3478 | current_templates = (const templates *) hash_find (op_hash, |
3479 | mnemonic); | |
29b0f896 AM |
3480 | } |
3481 | break; | |
252b5132 | 3482 | |
29b0f896 AM |
3483 | /* Intel Syntax. */ |
3484 | case 'd': | |
3485 | if (intel_syntax) | |
3486 | { | |
9306ca4a | 3487 | if (intel_float_operand (mnemonic) == 1) |
29b0f896 AM |
3488 | i.suffix = SHORT_MNEM_SUFFIX; |
3489 | else | |
3490 | i.suffix = LONG_MNEM_SUFFIX; | |
3491 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
3492 | current_templates = (const templates *) hash_find (op_hash, |
3493 | mnemonic); | |
29b0f896 AM |
3494 | } |
3495 | break; | |
3496 | } | |
3497 | if (!current_templates) | |
3498 | { | |
3499 | as_bad (_("no such instruction: `%s'"), token_start); | |
3500 | return NULL; | |
3501 | } | |
3502 | } | |
252b5132 | 3503 | |
40fb9820 L |
3504 | if (current_templates->start->opcode_modifier.jump |
3505 | || current_templates->start->opcode_modifier.jumpbyte) | |
29b0f896 AM |
3506 | { |
3507 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
3508 | predict taken and predict not taken respectively. | |
3509 | I'm not sure that branch hints actually do anything on loop | |
3510 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
3511 | may work in the future and it doesn't hurt to accept them | |
3512 | now. */ | |
3513 | if (l[0] == ',' && l[1] == 'p') | |
3514 | { | |
3515 | if (l[2] == 't') | |
3516 | { | |
3517 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
3518 | return NULL; | |
3519 | l += 3; | |
3520 | } | |
3521 | else if (l[2] == 'n') | |
3522 | { | |
3523 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
3524 | return NULL; | |
3525 | l += 3; | |
3526 | } | |
3527 | } | |
3528 | } | |
3529 | /* Any other comma loses. */ | |
3530 | if (*l == ',') | |
3531 | { | |
3532 | as_bad (_("invalid character %s in mnemonic"), | |
3533 | output_invalid (*l)); | |
3534 | return NULL; | |
3535 | } | |
252b5132 | 3536 | |
29b0f896 | 3537 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
3538 | supported = 0; |
3539 | for (t = current_templates->start; t < current_templates->end; ++t) | |
3540 | { | |
c0f3af97 L |
3541 | supported |= cpu_flags_match (t); |
3542 | if (supported == CPU_FLAGS_PERFECT_MATCH) | |
3629bb00 | 3543 | goto skip; |
5c6af06e | 3544 | } |
3629bb00 | 3545 | |
c0f3af97 | 3546 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
5c6af06e JB |
3547 | { |
3548 | as_bad (flag_code == CODE_64BIT | |
3549 | ? _("`%s' is not supported in 64-bit mode") | |
3550 | : _("`%s' is only supported in 64-bit mode"), | |
3551 | current_templates->start->name); | |
3552 | return NULL; | |
3553 | } | |
c0f3af97 | 3554 | if (supported != CPU_FLAGS_PERFECT_MATCH) |
29b0f896 | 3555 | { |
3629bb00 | 3556 | as_bad (_("`%s' is not supported on `%s%s'"), |
7ab9ffdd | 3557 | current_templates->start->name, |
41aacd83 | 3558 | cpu_arch_name ? cpu_arch_name : default_arch, |
3629bb00 L |
3559 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); |
3560 | return NULL; | |
29b0f896 | 3561 | } |
3629bb00 L |
3562 | |
3563 | skip: | |
3564 | if (!cpu_arch_flags.bitfield.cpui386 | |
40fb9820 | 3565 | && (flag_code != CODE_16BIT)) |
29b0f896 AM |
3566 | { |
3567 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
3568 | } | |
252b5132 | 3569 | |
29c048b6 | 3570 | /* Check for rep/repne without a string (or other allowed) instruction. */ |
f41bbced | 3571 | if (expecting_string_instruction) |
29b0f896 | 3572 | { |
f41bbced JB |
3573 | static templates override; |
3574 | ||
3575 | for (t = current_templates->start; t < current_templates->end; ++t) | |
29c048b6 | 3576 | if (t->opcode_modifier.repprefixok) |
f41bbced JB |
3577 | break; |
3578 | if (t >= current_templates->end) | |
3579 | { | |
3580 | as_bad (_("expecting string instruction after `%s'"), | |
64e74474 | 3581 | expecting_string_instruction); |
f41bbced JB |
3582 | return NULL; |
3583 | } | |
3584 | for (override.start = t; t < current_templates->end; ++t) | |
29c048b6 | 3585 | if (!t->opcode_modifier.repprefixok) |
f41bbced JB |
3586 | break; |
3587 | override.end = t; | |
3588 | current_templates = &override; | |
29b0f896 | 3589 | } |
252b5132 | 3590 | |
29b0f896 AM |
3591 | return l; |
3592 | } | |
252b5132 | 3593 | |
29b0f896 | 3594 | static char * |
e3bb37b5 | 3595 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
3596 | { |
3597 | char *token_start; | |
3138f287 | 3598 | |
29b0f896 AM |
3599 | /* 1 if operand is pending after ','. */ |
3600 | unsigned int expecting_operand = 0; | |
252b5132 | 3601 | |
29b0f896 AM |
3602 | /* Non-zero if operand parens not balanced. */ |
3603 | unsigned int paren_not_balanced; | |
3604 | ||
3605 | while (*l != END_OF_INSN) | |
3606 | { | |
3607 | /* Skip optional white space before operand. */ | |
3608 | if (is_space_char (*l)) | |
3609 | ++l; | |
3610 | if (!is_operand_char (*l) && *l != END_OF_INSN) | |
3611 | { | |
3612 | as_bad (_("invalid character %s before operand %d"), | |
3613 | output_invalid (*l), | |
3614 | i.operands + 1); | |
3615 | return NULL; | |
3616 | } | |
3617 | token_start = l; /* after white space */ | |
3618 | paren_not_balanced = 0; | |
3619 | while (paren_not_balanced || *l != ',') | |
3620 | { | |
3621 | if (*l == END_OF_INSN) | |
3622 | { | |
3623 | if (paren_not_balanced) | |
3624 | { | |
3625 | if (!intel_syntax) | |
3626 | as_bad (_("unbalanced parenthesis in operand %d."), | |
3627 | i.operands + 1); | |
3628 | else | |
3629 | as_bad (_("unbalanced brackets in operand %d."), | |
3630 | i.operands + 1); | |
3631 | return NULL; | |
3632 | } | |
3633 | else | |
3634 | break; /* we are done */ | |
3635 | } | |
3636 | else if (!is_operand_char (*l) && !is_space_char (*l)) | |
3637 | { | |
3638 | as_bad (_("invalid character %s in operand %d"), | |
3639 | output_invalid (*l), | |
3640 | i.operands + 1); | |
3641 | return NULL; | |
3642 | } | |
3643 | if (!intel_syntax) | |
3644 | { | |
3645 | if (*l == '(') | |
3646 | ++paren_not_balanced; | |
3647 | if (*l == ')') | |
3648 | --paren_not_balanced; | |
3649 | } | |
3650 | else | |
3651 | { | |
3652 | if (*l == '[') | |
3653 | ++paren_not_balanced; | |
3654 | if (*l == ']') | |
3655 | --paren_not_balanced; | |
3656 | } | |
3657 | l++; | |
3658 | } | |
3659 | if (l != token_start) | |
3660 | { /* Yes, we've read in another operand. */ | |
3661 | unsigned int operand_ok; | |
3662 | this_operand = i.operands++; | |
7d5e4556 | 3663 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
3664 | if (i.operands > MAX_OPERANDS) |
3665 | { | |
3666 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
3667 | MAX_OPERANDS); | |
3668 | return NULL; | |
3669 | } | |
3670 | /* Now parse operand adding info to 'i' as we go along. */ | |
3671 | END_STRING_AND_SAVE (l); | |
3672 | ||
3673 | if (intel_syntax) | |
3674 | operand_ok = | |
3675 | i386_intel_operand (token_start, | |
3676 | intel_float_operand (mnemonic)); | |
3677 | else | |
a7619375 | 3678 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
3679 | |
3680 | RESTORE_END_STRING (l); | |
3681 | if (!operand_ok) | |
3682 | return NULL; | |
3683 | } | |
3684 | else | |
3685 | { | |
3686 | if (expecting_operand) | |
3687 | { | |
3688 | expecting_operand_after_comma: | |
3689 | as_bad (_("expecting operand after ','; got nothing")); | |
3690 | return NULL; | |
3691 | } | |
3692 | if (*l == ',') | |
3693 | { | |
3694 | as_bad (_("expecting operand before ','; got nothing")); | |
3695 | return NULL; | |
3696 | } | |
3697 | } | |
7f3f1ea2 | 3698 | |
29b0f896 AM |
3699 | /* Now *l must be either ',' or END_OF_INSN. */ |
3700 | if (*l == ',') | |
3701 | { | |
3702 | if (*++l == END_OF_INSN) | |
3703 | { | |
3704 | /* Just skip it, if it's \n complain. */ | |
3705 | goto expecting_operand_after_comma; | |
3706 | } | |
3707 | expecting_operand = 1; | |
3708 | } | |
3709 | } | |
3710 | return l; | |
3711 | } | |
7f3f1ea2 | 3712 | |
050dfa73 | 3713 | static void |
4d456e3d | 3714 | swap_2_operands (int xchg1, int xchg2) |
050dfa73 MM |
3715 | { |
3716 | union i386_op temp_op; | |
40fb9820 | 3717 | i386_operand_type temp_type; |
050dfa73 | 3718 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 3719 | |
050dfa73 MM |
3720 | temp_type = i.types[xchg2]; |
3721 | i.types[xchg2] = i.types[xchg1]; | |
3722 | i.types[xchg1] = temp_type; | |
3723 | temp_op = i.op[xchg2]; | |
3724 | i.op[xchg2] = i.op[xchg1]; | |
3725 | i.op[xchg1] = temp_op; | |
3726 | temp_reloc = i.reloc[xchg2]; | |
3727 | i.reloc[xchg2] = i.reloc[xchg1]; | |
3728 | i.reloc[xchg1] = temp_reloc; | |
3729 | } | |
3730 | ||
29b0f896 | 3731 | static void |
e3bb37b5 | 3732 | swap_operands (void) |
29b0f896 | 3733 | { |
b7c61d9a | 3734 | switch (i.operands) |
050dfa73 | 3735 | { |
c0f3af97 | 3736 | case 5: |
b7c61d9a | 3737 | case 4: |
4d456e3d | 3738 | swap_2_operands (1, i.operands - 2); |
b7c61d9a L |
3739 | case 3: |
3740 | case 2: | |
4d456e3d | 3741 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
3742 | break; |
3743 | default: | |
3744 | abort (); | |
29b0f896 | 3745 | } |
29b0f896 AM |
3746 | |
3747 | if (i.mem_operands == 2) | |
3748 | { | |
3749 | const seg_entry *temp_seg; | |
3750 | temp_seg = i.seg[0]; | |
3751 | i.seg[0] = i.seg[1]; | |
3752 | i.seg[1] = temp_seg; | |
3753 | } | |
3754 | } | |
252b5132 | 3755 | |
29b0f896 AM |
3756 | /* Try to ensure constant immediates are represented in the smallest |
3757 | opcode possible. */ | |
3758 | static void | |
e3bb37b5 | 3759 | optimize_imm (void) |
29b0f896 AM |
3760 | { |
3761 | char guess_suffix = 0; | |
3762 | int op; | |
252b5132 | 3763 | |
29b0f896 AM |
3764 | if (i.suffix) |
3765 | guess_suffix = i.suffix; | |
3766 | else if (i.reg_operands) | |
3767 | { | |
3768 | /* Figure out a suffix from the last register operand specified. | |
3769 | We can't do this properly yet, ie. excluding InOutPortReg, | |
3770 | but the following works for instructions with immediates. | |
3771 | In any case, we can't set i.suffix yet. */ | |
3772 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 3773 | if (i.types[op].bitfield.reg8) |
7ab9ffdd | 3774 | { |
40fb9820 L |
3775 | guess_suffix = BYTE_MNEM_SUFFIX; |
3776 | break; | |
3777 | } | |
3778 | else if (i.types[op].bitfield.reg16) | |
252b5132 | 3779 | { |
40fb9820 L |
3780 | guess_suffix = WORD_MNEM_SUFFIX; |
3781 | break; | |
3782 | } | |
3783 | else if (i.types[op].bitfield.reg32) | |
3784 | { | |
3785 | guess_suffix = LONG_MNEM_SUFFIX; | |
3786 | break; | |
3787 | } | |
3788 | else if (i.types[op].bitfield.reg64) | |
3789 | { | |
3790 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 3791 | break; |
252b5132 | 3792 | } |
29b0f896 AM |
3793 | } |
3794 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
3795 | guess_suffix = WORD_MNEM_SUFFIX; | |
3796 | ||
3797 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 3798 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
3799 | { |
3800 | switch (i.op[op].imms->X_op) | |
252b5132 | 3801 | { |
29b0f896 AM |
3802 | case O_constant: |
3803 | /* If a suffix is given, this operand may be shortened. */ | |
3804 | switch (guess_suffix) | |
252b5132 | 3805 | { |
29b0f896 | 3806 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
3807 | i.types[op].bitfield.imm32 = 1; |
3808 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
3809 | break; |
3810 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
3811 | i.types[op].bitfield.imm16 = 1; |
3812 | i.types[op].bitfield.imm32 = 1; | |
3813 | i.types[op].bitfield.imm32s = 1; | |
3814 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
3815 | break; |
3816 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
3817 | i.types[op].bitfield.imm8 = 1; |
3818 | i.types[op].bitfield.imm8s = 1; | |
3819 | i.types[op].bitfield.imm16 = 1; | |
3820 | i.types[op].bitfield.imm32 = 1; | |
3821 | i.types[op].bitfield.imm32s = 1; | |
3822 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 3823 | break; |
252b5132 | 3824 | } |
252b5132 | 3825 | |
29b0f896 AM |
3826 | /* If this operand is at most 16 bits, convert it |
3827 | to a signed 16 bit number before trying to see | |
3828 | whether it will fit in an even smaller size. | |
3829 | This allows a 16-bit operand such as $0xffe0 to | |
3830 | be recognised as within Imm8S range. */ | |
40fb9820 | 3831 | if ((i.types[op].bitfield.imm16) |
29b0f896 | 3832 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
252b5132 | 3833 | { |
29b0f896 AM |
3834 | i.op[op].imms->X_add_number = |
3835 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
3836 | } | |
40fb9820 | 3837 | if ((i.types[op].bitfield.imm32) |
29b0f896 AM |
3838 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
3839 | == 0)) | |
3840 | { | |
3841 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
3842 | ^ ((offsetT) 1 << 31)) | |
3843 | - ((offsetT) 1 << 31)); | |
3844 | } | |
40fb9820 | 3845 | i.types[op] |
c6fb90c8 L |
3846 | = operand_type_or (i.types[op], |
3847 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 3848 | |
29b0f896 AM |
3849 | /* We must avoid matching of Imm32 templates when 64bit |
3850 | only immediate is available. */ | |
3851 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 3852 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 3853 | break; |
252b5132 | 3854 | |
29b0f896 AM |
3855 | case O_absent: |
3856 | case O_register: | |
3857 | abort (); | |
3858 | ||
3859 | /* Symbols and expressions. */ | |
3860 | default: | |
9cd96992 JB |
3861 | /* Convert symbolic operand to proper sizes for matching, but don't |
3862 | prevent matching a set of insns that only supports sizes other | |
3863 | than those matching the insn suffix. */ | |
3864 | { | |
40fb9820 | 3865 | i386_operand_type mask, allowed; |
d3ce72d0 | 3866 | const insn_template *t; |
9cd96992 | 3867 | |
0dfbf9d7 L |
3868 | operand_type_set (&mask, 0); |
3869 | operand_type_set (&allowed, 0); | |
40fb9820 | 3870 | |
4eed87de AM |
3871 | for (t = current_templates->start; |
3872 | t < current_templates->end; | |
3873 | ++t) | |
c6fb90c8 L |
3874 | allowed = operand_type_or (allowed, |
3875 | t->operand_types[op]); | |
9cd96992 JB |
3876 | switch (guess_suffix) |
3877 | { | |
3878 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
3879 | mask.bitfield.imm64 = 1; |
3880 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
3881 | break; |
3882 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 3883 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
3884 | break; |
3885 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 3886 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
3887 | break; |
3888 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 3889 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
3890 | break; |
3891 | default: | |
9cd96992 JB |
3892 | break; |
3893 | } | |
c6fb90c8 | 3894 | allowed = operand_type_and (mask, allowed); |
0dfbf9d7 | 3895 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 3896 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 3897 | } |
29b0f896 | 3898 | break; |
252b5132 | 3899 | } |
29b0f896 AM |
3900 | } |
3901 | } | |
47926f60 | 3902 | |
29b0f896 AM |
3903 | /* Try to use the smallest displacement type too. */ |
3904 | static void | |
e3bb37b5 | 3905 | optimize_disp (void) |
29b0f896 AM |
3906 | { |
3907 | int op; | |
3e73aa7c | 3908 | |
29b0f896 | 3909 | for (op = i.operands; --op >= 0;) |
40fb9820 | 3910 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 3911 | { |
b300c311 | 3912 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 3913 | { |
91d6fa6a | 3914 | offsetT op_disp = i.op[op].disps->X_add_number; |
29b0f896 | 3915 | |
40fb9820 | 3916 | if (i.types[op].bitfield.disp16 |
91d6fa6a | 3917 | && (op_disp & ~(offsetT) 0xffff) == 0) |
b300c311 L |
3918 | { |
3919 | /* If this operand is at most 16 bits, convert | |
3920 | to a signed 16 bit number and don't use 64bit | |
3921 | displacement. */ | |
91d6fa6a | 3922 | op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); |
40fb9820 | 3923 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 3924 | } |
40fb9820 | 3925 | if (i.types[op].bitfield.disp32 |
91d6fa6a | 3926 | && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
b300c311 L |
3927 | { |
3928 | /* If this operand is at most 32 bits, convert | |
3929 | to a signed 32 bit number and don't use 64bit | |
3930 | displacement. */ | |
91d6fa6a NC |
3931 | op_disp &= (((offsetT) 2 << 31) - 1); |
3932 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
40fb9820 | 3933 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 3934 | } |
91d6fa6a | 3935 | if (!op_disp && i.types[op].bitfield.baseindex) |
b300c311 | 3936 | { |
40fb9820 L |
3937 | i.types[op].bitfield.disp8 = 0; |
3938 | i.types[op].bitfield.disp16 = 0; | |
3939 | i.types[op].bitfield.disp32 = 0; | |
3940 | i.types[op].bitfield.disp32s = 0; | |
3941 | i.types[op].bitfield.disp64 = 0; | |
b300c311 L |
3942 | i.op[op].disps = 0; |
3943 | i.disp_operands--; | |
3944 | } | |
3945 | else if (flag_code == CODE_64BIT) | |
3946 | { | |
91d6fa6a | 3947 | if (fits_in_signed_long (op_disp)) |
28a9d8f5 | 3948 | { |
40fb9820 L |
3949 | i.types[op].bitfield.disp64 = 0; |
3950 | i.types[op].bitfield.disp32s = 1; | |
28a9d8f5 | 3951 | } |
0e1147d9 | 3952 | if (i.prefix[ADDR_PREFIX] |
91d6fa6a | 3953 | && fits_in_unsigned_long (op_disp)) |
40fb9820 | 3954 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 3955 | } |
40fb9820 L |
3956 | if ((i.types[op].bitfield.disp32 |
3957 | || i.types[op].bitfield.disp32s | |
3958 | || i.types[op].bitfield.disp16) | |
91d6fa6a | 3959 | && fits_in_signed_byte (op_disp)) |
40fb9820 | 3960 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 3961 | } |
67a4f2b7 AO |
3962 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
3963 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
3964 | { | |
3965 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
3966 | i.op[op].disps, 0, i.reloc[op]); | |
40fb9820 L |
3967 | i.types[op].bitfield.disp8 = 0; |
3968 | i.types[op].bitfield.disp16 = 0; | |
3969 | i.types[op].bitfield.disp32 = 0; | |
3970 | i.types[op].bitfield.disp32s = 0; | |
3971 | i.types[op].bitfield.disp64 = 0; | |
67a4f2b7 AO |
3972 | } |
3973 | else | |
b300c311 | 3974 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 3975 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 3976 | } |
29b0f896 AM |
3977 | } |
3978 | ||
6c30d220 L |
3979 | /* Check if operands are valid for the instruction. */ |
3980 | ||
3981 | static int | |
3982 | check_VecOperands (const insn_template *t) | |
3983 | { | |
3984 | /* Without VSIB byte, we can't have a vector register for index. */ | |
3985 | if (!t->opcode_modifier.vecsib | |
3986 | && i.index_reg | |
3987 | && (i.index_reg->reg_type.bitfield.regxmm | |
3988 | || i.index_reg->reg_type.bitfield.regymm)) | |
3989 | { | |
3990 | i.error = unsupported_vector_index_register; | |
3991 | return 1; | |
3992 | } | |
3993 | ||
7bab8ab5 JB |
3994 | /* For VSIB byte, we need a vector register for index, and all vector |
3995 | registers must be distinct. */ | |
3996 | if (t->opcode_modifier.vecsib) | |
3997 | { | |
3998 | if (!i.index_reg | |
6c30d220 L |
3999 | || !((t->opcode_modifier.vecsib == VecSIB128 |
4000 | && i.index_reg->reg_type.bitfield.regxmm) | |
4001 | || (t->opcode_modifier.vecsib == VecSIB256 | |
7bab8ab5 JB |
4002 | && i.index_reg->reg_type.bitfield.regymm))) |
4003 | { | |
4004 | i.error = invalid_vsib_address; | |
4005 | return 1; | |
4006 | } | |
4007 | ||
4008 | gas_assert (i.reg_operands == 2); | |
4009 | gas_assert (i.types[0].bitfield.regxmm | |
4010 | || i.types[0].bitfield.regymm); | |
4011 | gas_assert (i.types[2].bitfield.regxmm | |
4012 | || i.types[2].bitfield.regymm); | |
4013 | ||
4014 | if (operand_check == check_none) | |
4015 | return 0; | |
4016 | if (register_number (i.op[0].regs) != register_number (i.index_reg) | |
4017 | && register_number (i.op[2].regs) != register_number (i.index_reg) | |
4018 | && register_number (i.op[0].regs) != register_number (i.op[2].regs)) | |
4019 | return 0; | |
4020 | if (operand_check == check_error) | |
4021 | { | |
4022 | i.error = invalid_vector_register_set; | |
4023 | return 1; | |
4024 | } | |
4025 | as_warn (_("mask, index, and destination registers should be distinct")); | |
6c30d220 L |
4026 | } |
4027 | ||
4028 | return 0; | |
4029 | } | |
4030 | ||
43f3e2ee | 4031 | /* Check if operands are valid for the instruction. Update VEX |
a683cc34 SP |
4032 | operand types. */ |
4033 | ||
4034 | static int | |
4035 | VEX_check_operands (const insn_template *t) | |
4036 | { | |
4037 | if (!t->opcode_modifier.vex) | |
4038 | return 0; | |
4039 | ||
4040 | /* Only check VEX_Imm4, which must be the first operand. */ | |
4041 | if (t->operand_types[0].bitfield.vec_imm4) | |
4042 | { | |
4043 | if (i.op[0].imms->X_op != O_constant | |
4044 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
891edac4 | 4045 | { |
a65babc9 | 4046 | i.error = bad_imm4; |
891edac4 L |
4047 | return 1; |
4048 | } | |
a683cc34 SP |
4049 | |
4050 | /* Turn off Imm8 so that update_imm won't complain. */ | |
4051 | i.types[0] = vec_imm4; | |
4052 | } | |
4053 | ||
4054 | return 0; | |
4055 | } | |
4056 | ||
d3ce72d0 | 4057 | static const insn_template * |
e3bb37b5 | 4058 | match_template (void) |
29b0f896 AM |
4059 | { |
4060 | /* Points to template once we've found it. */ | |
d3ce72d0 | 4061 | const insn_template *t; |
40fb9820 | 4062 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 4063 | i386_operand_type overlap4; |
29b0f896 | 4064 | unsigned int found_reverse_match; |
40fb9820 L |
4065 | i386_opcode_modifier suffix_check; |
4066 | i386_operand_type operand_types [MAX_OPERANDS]; | |
539e75ad | 4067 | int addr_prefix_disp; |
a5c311ca | 4068 | unsigned int j; |
3629bb00 | 4069 | unsigned int found_cpu_match; |
45664ddb | 4070 | unsigned int check_register; |
5614d22c | 4071 | enum i386_error specific_error = 0; |
29b0f896 | 4072 | |
c0f3af97 L |
4073 | #if MAX_OPERANDS != 5 |
4074 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
4075 | #endif |
4076 | ||
29b0f896 | 4077 | found_reverse_match = 0; |
539e75ad | 4078 | addr_prefix_disp = -1; |
40fb9820 L |
4079 | |
4080 | memset (&suffix_check, 0, sizeof (suffix_check)); | |
4081 | if (i.suffix == BYTE_MNEM_SUFFIX) | |
4082 | suffix_check.no_bsuf = 1; | |
4083 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
4084 | suffix_check.no_wsuf = 1; | |
4085 | else if (i.suffix == SHORT_MNEM_SUFFIX) | |
4086 | suffix_check.no_ssuf = 1; | |
4087 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
4088 | suffix_check.no_lsuf = 1; | |
4089 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
4090 | suffix_check.no_qsuf = 1; | |
4091 | else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
7ce189b3 | 4092 | suffix_check.no_ldsuf = 1; |
29b0f896 | 4093 | |
01559ecc L |
4094 | /* Must have right number of operands. */ |
4095 | i.error = number_of_operands_mismatch; | |
4096 | ||
45aa61fe | 4097 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 4098 | { |
539e75ad L |
4099 | addr_prefix_disp = -1; |
4100 | ||
29b0f896 AM |
4101 | if (i.operands != t->operands) |
4102 | continue; | |
4103 | ||
50aecf8c | 4104 | /* Check processor support. */ |
a65babc9 | 4105 | i.error = unsupported; |
c0f3af97 L |
4106 | found_cpu_match = (cpu_flags_match (t) |
4107 | == CPU_FLAGS_PERFECT_MATCH); | |
50aecf8c L |
4108 | if (!found_cpu_match) |
4109 | continue; | |
4110 | ||
e1d4d893 | 4111 | /* Check old gcc support. */ |
a65babc9 | 4112 | i.error = old_gcc_only; |
e1d4d893 L |
4113 | if (!old_gcc && t->opcode_modifier.oldgcc) |
4114 | continue; | |
4115 | ||
4116 | /* Check AT&T mnemonic. */ | |
a65babc9 | 4117 | i.error = unsupported_with_intel_mnemonic; |
e1d4d893 | 4118 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) |
1efbbeb4 L |
4119 | continue; |
4120 | ||
891edac4 | 4121 | /* Check AT&T/Intel syntax. */ |
a65babc9 | 4122 | i.error = unsupported_syntax; |
5c07affc L |
4123 | if ((intel_syntax && t->opcode_modifier.attsyntax) |
4124 | || (!intel_syntax && t->opcode_modifier.intelsyntax)) | |
1efbbeb4 L |
4125 | continue; |
4126 | ||
20592a94 | 4127 | /* Check the suffix, except for some instructions in intel mode. */ |
a65babc9 | 4128 | i.error = invalid_instruction_suffix; |
567e4e96 L |
4129 | if ((!intel_syntax || !t->opcode_modifier.ignoresize) |
4130 | && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) | |
4131 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
4132 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
4133 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
4134 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
4135 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf))) | |
29b0f896 AM |
4136 | continue; |
4137 | ||
5c07affc | 4138 | if (!operand_size_match (t)) |
7d5e4556 | 4139 | continue; |
539e75ad | 4140 | |
5c07affc L |
4141 | for (j = 0; j < MAX_OPERANDS; j++) |
4142 | operand_types[j] = t->operand_types[j]; | |
4143 | ||
45aa61fe AM |
4144 | /* In general, don't allow 64-bit operands in 32-bit mode. */ |
4145 | if (i.suffix == QWORD_MNEM_SUFFIX | |
4146 | && flag_code != CODE_64BIT | |
4147 | && (intel_syntax | |
40fb9820 | 4148 | ? (!t->opcode_modifier.ignoresize |
45aa61fe AM |
4149 | && !intel_float_operand (t->name)) |
4150 | : intel_float_operand (t->name) != 2) | |
40fb9820 | 4151 | && ((!operand_types[0].bitfield.regmmx |
c0f3af97 L |
4152 | && !operand_types[0].bitfield.regxmm |
4153 | && !operand_types[0].bitfield.regymm) | |
40fb9820 | 4154 | || (!operand_types[t->operands > 1].bitfield.regmmx |
c0f3af97 L |
4155 | && !!operand_types[t->operands > 1].bitfield.regxmm |
4156 | && !!operand_types[t->operands > 1].bitfield.regymm)) | |
45aa61fe AM |
4157 | && (t->base_opcode != 0x0fc7 |
4158 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
4159 | continue; | |
4160 | ||
192dc9c6 JB |
4161 | /* In general, don't allow 32-bit operands on pre-386. */ |
4162 | else if (i.suffix == LONG_MNEM_SUFFIX | |
4163 | && !cpu_arch_flags.bitfield.cpui386 | |
4164 | && (intel_syntax | |
4165 | ? (!t->opcode_modifier.ignoresize | |
4166 | && !intel_float_operand (t->name)) | |
4167 | : intel_float_operand (t->name) != 2) | |
4168 | && ((!operand_types[0].bitfield.regmmx | |
4169 | && !operand_types[0].bitfield.regxmm) | |
4170 | || (!operand_types[t->operands > 1].bitfield.regmmx | |
4171 | && !!operand_types[t->operands > 1].bitfield.regxmm))) | |
4172 | continue; | |
4173 | ||
29b0f896 | 4174 | /* Do not verify operands when there are none. */ |
50aecf8c | 4175 | else |
29b0f896 | 4176 | { |
c6fb90c8 | 4177 | if (!t->operands) |
2dbab7d5 L |
4178 | /* We've found a match; break out of loop. */ |
4179 | break; | |
29b0f896 | 4180 | } |
252b5132 | 4181 | |
539e75ad L |
4182 | /* Address size prefix will turn Disp64/Disp32/Disp16 operand |
4183 | into Disp32/Disp16/Disp32 operand. */ | |
4184 | if (i.prefix[ADDR_PREFIX] != 0) | |
4185 | { | |
40fb9820 | 4186 | /* There should be only one Disp operand. */ |
539e75ad L |
4187 | switch (flag_code) |
4188 | { | |
4189 | case CODE_16BIT: | |
40fb9820 L |
4190 | for (j = 0; j < MAX_OPERANDS; j++) |
4191 | { | |
4192 | if (operand_types[j].bitfield.disp16) | |
4193 | { | |
4194 | addr_prefix_disp = j; | |
4195 | operand_types[j].bitfield.disp32 = 1; | |
4196 | operand_types[j].bitfield.disp16 = 0; | |
4197 | break; | |
4198 | } | |
4199 | } | |
539e75ad L |
4200 | break; |
4201 | case CODE_32BIT: | |
40fb9820 L |
4202 | for (j = 0; j < MAX_OPERANDS; j++) |
4203 | { | |
4204 | if (operand_types[j].bitfield.disp32) | |
4205 | { | |
4206 | addr_prefix_disp = j; | |
4207 | operand_types[j].bitfield.disp32 = 0; | |
4208 | operand_types[j].bitfield.disp16 = 1; | |
4209 | break; | |
4210 | } | |
4211 | } | |
539e75ad L |
4212 | break; |
4213 | case CODE_64BIT: | |
40fb9820 L |
4214 | for (j = 0; j < MAX_OPERANDS; j++) |
4215 | { | |
4216 | if (operand_types[j].bitfield.disp64) | |
4217 | { | |
4218 | addr_prefix_disp = j; | |
4219 | operand_types[j].bitfield.disp64 = 0; | |
4220 | operand_types[j].bitfield.disp32 = 1; | |
4221 | break; | |
4222 | } | |
4223 | } | |
539e75ad L |
4224 | break; |
4225 | } | |
539e75ad L |
4226 | } |
4227 | ||
56ffb741 L |
4228 | /* We check register size if needed. */ |
4229 | check_register = t->opcode_modifier.checkregsize; | |
c6fb90c8 | 4230 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
4231 | switch (t->operands) |
4232 | { | |
4233 | case 1: | |
40fb9820 | 4234 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
4235 | continue; |
4236 | break; | |
4237 | case 2: | |
8b38ad71 L |
4238 | /* xchg %eax, %eax is a special case. It is an aliase for nop |
4239 | only in 32bit mode and we can use opcode 0x90. In 64bit | |
4240 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
4241 | zero-extend %eax to %rax. */ | |
4242 | if (flag_code == CODE_64BIT | |
4243 | && t->base_opcode == 0x90 | |
0dfbf9d7 L |
4244 | && operand_type_equal (&i.types [0], &acc32) |
4245 | && operand_type_equal (&i.types [1], &acc32)) | |
8b38ad71 | 4246 | continue; |
b6169b20 L |
4247 | if (i.swap_operand) |
4248 | { | |
4249 | /* If we swap operand in encoding, we either match | |
4250 | the next one or reverse direction of operands. */ | |
4251 | if (t->opcode_modifier.s) | |
4252 | continue; | |
4253 | else if (t->opcode_modifier.d) | |
4254 | goto check_reverse; | |
4255 | } | |
4256 | ||
29b0f896 | 4257 | case 3: |
fa99fab2 L |
4258 | /* If we swap operand in encoding, we match the next one. */ |
4259 | if (i.swap_operand && t->opcode_modifier.s) | |
4260 | continue; | |
f48ff2ae | 4261 | case 4: |
c0f3af97 | 4262 | case 5: |
c6fb90c8 | 4263 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
4264 | if (!operand_type_match (overlap0, i.types[0]) |
4265 | || !operand_type_match (overlap1, i.types[1]) | |
45664ddb L |
4266 | || (check_register |
4267 | && !operand_type_register_match (overlap0, i.types[0], | |
40fb9820 L |
4268 | operand_types[0], |
4269 | overlap1, i.types[1], | |
4270 | operand_types[1]))) | |
29b0f896 AM |
4271 | { |
4272 | /* Check if other direction is valid ... */ | |
40fb9820 | 4273 | if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) |
29b0f896 AM |
4274 | continue; |
4275 | ||
b6169b20 | 4276 | check_reverse: |
29b0f896 | 4277 | /* Try reversing direction of operands. */ |
c6fb90c8 L |
4278 | overlap0 = operand_type_and (i.types[0], operand_types[1]); |
4279 | overlap1 = operand_type_and (i.types[1], operand_types[0]); | |
40fb9820 L |
4280 | if (!operand_type_match (overlap0, i.types[0]) |
4281 | || !operand_type_match (overlap1, i.types[1]) | |
45664ddb L |
4282 | || (check_register |
4283 | && !operand_type_register_match (overlap0, | |
4284 | i.types[0], | |
4285 | operand_types[1], | |
4286 | overlap1, | |
4287 | i.types[1], | |
4288 | operand_types[0]))) | |
29b0f896 AM |
4289 | { |
4290 | /* Does not match either direction. */ | |
4291 | continue; | |
4292 | } | |
4293 | /* found_reverse_match holds which of D or FloatDR | |
4294 | we've found. */ | |
40fb9820 | 4295 | if (t->opcode_modifier.d) |
8a2ed489 | 4296 | found_reverse_match = Opcode_D; |
40fb9820 | 4297 | else if (t->opcode_modifier.floatd) |
8a2ed489 L |
4298 | found_reverse_match = Opcode_FloatD; |
4299 | else | |
4300 | found_reverse_match = 0; | |
40fb9820 | 4301 | if (t->opcode_modifier.floatr) |
8a2ed489 | 4302 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 4303 | } |
f48ff2ae | 4304 | else |
29b0f896 | 4305 | { |
f48ff2ae | 4306 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
4307 | switch (t->operands) |
4308 | { | |
c0f3af97 L |
4309 | case 5: |
4310 | overlap4 = operand_type_and (i.types[4], | |
4311 | operand_types[4]); | |
d1cbb4db | 4312 | case 4: |
c6fb90c8 L |
4313 | overlap3 = operand_type_and (i.types[3], |
4314 | operand_types[3]); | |
d1cbb4db | 4315 | case 3: |
c6fb90c8 L |
4316 | overlap2 = operand_type_and (i.types[2], |
4317 | operand_types[2]); | |
d1cbb4db L |
4318 | break; |
4319 | } | |
29b0f896 | 4320 | |
f48ff2ae L |
4321 | switch (t->operands) |
4322 | { | |
c0f3af97 L |
4323 | case 5: |
4324 | if (!operand_type_match (overlap4, i.types[4]) | |
4325 | || !operand_type_register_match (overlap3, | |
4326 | i.types[3], | |
4327 | operand_types[3], | |
4328 | overlap4, | |
4329 | i.types[4], | |
4330 | operand_types[4])) | |
4331 | continue; | |
f48ff2ae | 4332 | case 4: |
40fb9820 | 4333 | if (!operand_type_match (overlap3, i.types[3]) |
45664ddb L |
4334 | || (check_register |
4335 | && !operand_type_register_match (overlap2, | |
4336 | i.types[2], | |
4337 | operand_types[2], | |
4338 | overlap3, | |
4339 | i.types[3], | |
4340 | operand_types[3]))) | |
f48ff2ae L |
4341 | continue; |
4342 | case 3: | |
4343 | /* Here we make use of the fact that there are no | |
4344 | reverse match 3 operand instructions, and all 3 | |
4345 | operand instructions only need to be checked for | |
4346 | register consistency between operands 2 and 3. */ | |
40fb9820 | 4347 | if (!operand_type_match (overlap2, i.types[2]) |
45664ddb L |
4348 | || (check_register |
4349 | && !operand_type_register_match (overlap1, | |
4350 | i.types[1], | |
4351 | operand_types[1], | |
4352 | overlap2, | |
4353 | i.types[2], | |
4354 | operand_types[2]))) | |
f48ff2ae L |
4355 | continue; |
4356 | break; | |
4357 | } | |
29b0f896 | 4358 | } |
f48ff2ae | 4359 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
4360 | slip through to break. */ |
4361 | } | |
3629bb00 | 4362 | if (!found_cpu_match) |
29b0f896 AM |
4363 | { |
4364 | found_reverse_match = 0; | |
4365 | continue; | |
4366 | } | |
c0f3af97 | 4367 | |
5614d22c JB |
4368 | /* Check if vector and VEX operands are valid. */ |
4369 | if (check_VecOperands (t) || VEX_check_operands (t)) | |
4370 | { | |
4371 | specific_error = i.error; | |
4372 | continue; | |
4373 | } | |
a683cc34 | 4374 | |
29b0f896 AM |
4375 | /* We've found a match; break out of loop. */ |
4376 | break; | |
4377 | } | |
4378 | ||
4379 | if (t == current_templates->end) | |
4380 | { | |
4381 | /* We found no match. */ | |
a65babc9 | 4382 | const char *err_msg; |
5614d22c | 4383 | switch (specific_error ? specific_error : i.error) |
a65babc9 L |
4384 | { |
4385 | default: | |
4386 | abort (); | |
86e026a4 | 4387 | case operand_size_mismatch: |
a65babc9 L |
4388 | err_msg = _("operand size mismatch"); |
4389 | break; | |
4390 | case operand_type_mismatch: | |
4391 | err_msg = _("operand type mismatch"); | |
4392 | break; | |
4393 | case register_type_mismatch: | |
4394 | err_msg = _("register type mismatch"); | |
4395 | break; | |
4396 | case number_of_operands_mismatch: | |
4397 | err_msg = _("number of operands mismatch"); | |
4398 | break; | |
4399 | case invalid_instruction_suffix: | |
4400 | err_msg = _("invalid instruction suffix"); | |
4401 | break; | |
4402 | case bad_imm4: | |
4a2608e3 | 4403 | err_msg = _("constant doesn't fit in 4 bits"); |
a65babc9 L |
4404 | break; |
4405 | case old_gcc_only: | |
4406 | err_msg = _("only supported with old gcc"); | |
4407 | break; | |
4408 | case unsupported_with_intel_mnemonic: | |
4409 | err_msg = _("unsupported with Intel mnemonic"); | |
4410 | break; | |
4411 | case unsupported_syntax: | |
4412 | err_msg = _("unsupported syntax"); | |
4413 | break; | |
4414 | case unsupported: | |
35262a23 | 4415 | as_bad (_("unsupported instruction `%s'"), |
10efe3f6 L |
4416 | current_templates->start->name); |
4417 | return NULL; | |
6c30d220 L |
4418 | case invalid_vsib_address: |
4419 | err_msg = _("invalid VSIB address"); | |
4420 | break; | |
7bab8ab5 JB |
4421 | case invalid_vector_register_set: |
4422 | err_msg = _("mask, index, and destination registers must be distinct"); | |
4423 | break; | |
6c30d220 L |
4424 | case unsupported_vector_index_register: |
4425 | err_msg = _("unsupported vector index register"); | |
4426 | break; | |
a65babc9 L |
4427 | } |
4428 | as_bad (_("%s for `%s'"), err_msg, | |
891edac4 | 4429 | current_templates->start->name); |
fa99fab2 | 4430 | return NULL; |
29b0f896 | 4431 | } |
252b5132 | 4432 | |
29b0f896 AM |
4433 | if (!quiet_warnings) |
4434 | { | |
4435 | if (!intel_syntax | |
40fb9820 L |
4436 | && (i.types[0].bitfield.jumpabsolute |
4437 | != operand_types[0].bitfield.jumpabsolute)) | |
29b0f896 AM |
4438 | { |
4439 | as_warn (_("indirect %s without `*'"), t->name); | |
4440 | } | |
4441 | ||
40fb9820 L |
4442 | if (t->opcode_modifier.isprefix |
4443 | && t->opcode_modifier.ignoresize) | |
29b0f896 AM |
4444 | { |
4445 | /* Warn them that a data or address size prefix doesn't | |
4446 | affect assembly of the next line of code. */ | |
4447 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
4448 | } | |
4449 | } | |
4450 | ||
4451 | /* Copy the template we found. */ | |
4452 | i.tm = *t; | |
539e75ad L |
4453 | |
4454 | if (addr_prefix_disp != -1) | |
4455 | i.tm.operand_types[addr_prefix_disp] | |
4456 | = operand_types[addr_prefix_disp]; | |
4457 | ||
29b0f896 AM |
4458 | if (found_reverse_match) |
4459 | { | |
4460 | /* If we found a reverse match we must alter the opcode | |
4461 | direction bit. found_reverse_match holds bits to change | |
4462 | (different for int & float insns). */ | |
4463 | ||
4464 | i.tm.base_opcode ^= found_reverse_match; | |
4465 | ||
539e75ad L |
4466 | i.tm.operand_types[0] = operand_types[1]; |
4467 | i.tm.operand_types[1] = operand_types[0]; | |
29b0f896 AM |
4468 | } |
4469 | ||
fa99fab2 | 4470 | return t; |
29b0f896 AM |
4471 | } |
4472 | ||
4473 | static int | |
e3bb37b5 | 4474 | check_string (void) |
29b0f896 | 4475 | { |
40fb9820 L |
4476 | int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1; |
4477 | if (i.tm.operand_types[mem_op].bitfield.esseg) | |
29b0f896 AM |
4478 | { |
4479 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
4480 | { | |
a87af027 | 4481 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 4482 | i.tm.name, |
a87af027 JB |
4483 | mem_op + 1, |
4484 | register_prefix); | |
29b0f896 AM |
4485 | return 0; |
4486 | } | |
4487 | /* There's only ever one segment override allowed per instruction. | |
4488 | This instruction possibly has a legal segment override on the | |
4489 | second operand, so copy the segment to where non-string | |
4490 | instructions store it, allowing common code. */ | |
4491 | i.seg[0] = i.seg[1]; | |
4492 | } | |
40fb9820 | 4493 | else if (i.tm.operand_types[mem_op + 1].bitfield.esseg) |
29b0f896 AM |
4494 | { |
4495 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
4496 | { | |
a87af027 | 4497 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 4498 | i.tm.name, |
a87af027 JB |
4499 | mem_op + 2, |
4500 | register_prefix); | |
29b0f896 AM |
4501 | return 0; |
4502 | } | |
4503 | } | |
4504 | return 1; | |
4505 | } | |
4506 | ||
4507 | static int | |
543613e9 | 4508 | process_suffix (void) |
29b0f896 AM |
4509 | { |
4510 | /* If matched instruction specifies an explicit instruction mnemonic | |
4511 | suffix, use it. */ | |
40fb9820 L |
4512 | if (i.tm.opcode_modifier.size16) |
4513 | i.suffix = WORD_MNEM_SUFFIX; | |
4514 | else if (i.tm.opcode_modifier.size32) | |
4515 | i.suffix = LONG_MNEM_SUFFIX; | |
4516 | else if (i.tm.opcode_modifier.size64) | |
4517 | i.suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 AM |
4518 | else if (i.reg_operands) |
4519 | { | |
4520 | /* If there's no instruction mnemonic suffix we try to invent one | |
4521 | based on register operands. */ | |
4522 | if (!i.suffix) | |
4523 | { | |
4524 | /* We take i.suffix from the last register operand specified, | |
4525 | Destination register type is more significant than source | |
381d071f L |
4526 | register type. crc32 in SSE4.2 prefers source register |
4527 | type. */ | |
4528 | if (i.tm.base_opcode == 0xf20f38f1) | |
4529 | { | |
40fb9820 L |
4530 | if (i.types[0].bitfield.reg16) |
4531 | i.suffix = WORD_MNEM_SUFFIX; | |
4532 | else if (i.types[0].bitfield.reg32) | |
4533 | i.suffix = LONG_MNEM_SUFFIX; | |
4534 | else if (i.types[0].bitfield.reg64) | |
4535 | i.suffix = QWORD_MNEM_SUFFIX; | |
381d071f | 4536 | } |
9344ff29 | 4537 | else if (i.tm.base_opcode == 0xf20f38f0) |
20592a94 | 4538 | { |
40fb9820 | 4539 | if (i.types[0].bitfield.reg8) |
20592a94 L |
4540 | i.suffix = BYTE_MNEM_SUFFIX; |
4541 | } | |
381d071f L |
4542 | |
4543 | if (!i.suffix) | |
4544 | { | |
4545 | int op; | |
4546 | ||
20592a94 L |
4547 | if (i.tm.base_opcode == 0xf20f38f1 |
4548 | || i.tm.base_opcode == 0xf20f38f0) | |
4549 | { | |
4550 | /* We have to know the operand size for crc32. */ | |
4551 | as_bad (_("ambiguous memory operand size for `%s`"), | |
4552 | i.tm.name); | |
4553 | return 0; | |
4554 | } | |
4555 | ||
381d071f | 4556 | for (op = i.operands; --op >= 0;) |
40fb9820 | 4557 | if (!i.tm.operand_types[op].bitfield.inoutportreg) |
381d071f | 4558 | { |
40fb9820 L |
4559 | if (i.types[op].bitfield.reg8) |
4560 | { | |
4561 | i.suffix = BYTE_MNEM_SUFFIX; | |
4562 | break; | |
4563 | } | |
4564 | else if (i.types[op].bitfield.reg16) | |
4565 | { | |
4566 | i.suffix = WORD_MNEM_SUFFIX; | |
4567 | break; | |
4568 | } | |
4569 | else if (i.types[op].bitfield.reg32) | |
4570 | { | |
4571 | i.suffix = LONG_MNEM_SUFFIX; | |
4572 | break; | |
4573 | } | |
4574 | else if (i.types[op].bitfield.reg64) | |
4575 | { | |
4576 | i.suffix = QWORD_MNEM_SUFFIX; | |
4577 | break; | |
4578 | } | |
381d071f L |
4579 | } |
4580 | } | |
29b0f896 AM |
4581 | } |
4582 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
4583 | { | |
2eb952a4 L |
4584 | if (intel_syntax |
4585 | && i.tm.opcode_modifier.ignoresize | |
4586 | && i.tm.opcode_modifier.no_bsuf) | |
4587 | i.suffix = 0; | |
4588 | else if (!check_byte_reg ()) | |
29b0f896 AM |
4589 | return 0; |
4590 | } | |
4591 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
4592 | { | |
2eb952a4 L |
4593 | if (intel_syntax |
4594 | && i.tm.opcode_modifier.ignoresize | |
4595 | && i.tm.opcode_modifier.no_lsuf) | |
4596 | i.suffix = 0; | |
4597 | else if (!check_long_reg ()) | |
29b0f896 AM |
4598 | return 0; |
4599 | } | |
4600 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
4601 | { | |
955e1e6a L |
4602 | if (intel_syntax |
4603 | && i.tm.opcode_modifier.ignoresize | |
4604 | && i.tm.opcode_modifier.no_qsuf) | |
4605 | i.suffix = 0; | |
4606 | else if (!check_qword_reg ()) | |
29b0f896 AM |
4607 | return 0; |
4608 | } | |
4609 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
4610 | { | |
2eb952a4 L |
4611 | if (intel_syntax |
4612 | && i.tm.opcode_modifier.ignoresize | |
4613 | && i.tm.opcode_modifier.no_wsuf) | |
4614 | i.suffix = 0; | |
4615 | else if (!check_word_reg ()) | |
29b0f896 AM |
4616 | return 0; |
4617 | } | |
c0f3af97 L |
4618 | else if (i.suffix == XMMWORD_MNEM_SUFFIX |
4619 | || i.suffix == YMMWORD_MNEM_SUFFIX) | |
582d5edd | 4620 | { |
c0f3af97 | 4621 | /* Skip if the instruction has x/y suffix. match_template |
582d5edd L |
4622 | should check if it is a valid suffix. */ |
4623 | } | |
40fb9820 | 4624 | else if (intel_syntax && i.tm.opcode_modifier.ignoresize) |
29b0f896 AM |
4625 | /* Do nothing if the instruction is going to ignore the prefix. */ |
4626 | ; | |
4627 | else | |
4628 | abort (); | |
4629 | } | |
40fb9820 | 4630 | else if (i.tm.opcode_modifier.defaultsize |
9306ca4a JB |
4631 | && !i.suffix |
4632 | /* exclude fldenv/frstor/fsave/fstenv */ | |
40fb9820 | 4633 | && i.tm.opcode_modifier.no_ssuf) |
29b0f896 AM |
4634 | { |
4635 | i.suffix = stackop_size; | |
4636 | } | |
9306ca4a JB |
4637 | else if (intel_syntax |
4638 | && !i.suffix | |
40fb9820 L |
4639 | && (i.tm.operand_types[0].bitfield.jumpabsolute |
4640 | || i.tm.opcode_modifier.jumpbyte | |
4641 | || i.tm.opcode_modifier.jumpintersegment | |
64e74474 AM |
4642 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
4643 | && i.tm.extension_opcode <= 3))) | |
9306ca4a JB |
4644 | { |
4645 | switch (flag_code) | |
4646 | { | |
4647 | case CODE_64BIT: | |
40fb9820 | 4648 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a JB |
4649 | { |
4650 | i.suffix = QWORD_MNEM_SUFFIX; | |
4651 | break; | |
4652 | } | |
4653 | case CODE_32BIT: | |
40fb9820 | 4654 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
4655 | i.suffix = LONG_MNEM_SUFFIX; |
4656 | break; | |
4657 | case CODE_16BIT: | |
40fb9820 | 4658 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
4659 | i.suffix = WORD_MNEM_SUFFIX; |
4660 | break; | |
4661 | } | |
4662 | } | |
252b5132 | 4663 | |
9306ca4a | 4664 | if (!i.suffix) |
29b0f896 | 4665 | { |
9306ca4a JB |
4666 | if (!intel_syntax) |
4667 | { | |
40fb9820 | 4668 | if (i.tm.opcode_modifier.w) |
9306ca4a | 4669 | { |
4eed87de AM |
4670 | as_bad (_("no instruction mnemonic suffix given and " |
4671 | "no register operands; can't size instruction")); | |
9306ca4a JB |
4672 | return 0; |
4673 | } | |
4674 | } | |
4675 | else | |
4676 | { | |
40fb9820 | 4677 | unsigned int suffixes; |
7ab9ffdd | 4678 | |
40fb9820 L |
4679 | suffixes = !i.tm.opcode_modifier.no_bsuf; |
4680 | if (!i.tm.opcode_modifier.no_wsuf) | |
4681 | suffixes |= 1 << 1; | |
4682 | if (!i.tm.opcode_modifier.no_lsuf) | |
4683 | suffixes |= 1 << 2; | |
fc4adea1 | 4684 | if (!i.tm.opcode_modifier.no_ldsuf) |
40fb9820 L |
4685 | suffixes |= 1 << 3; |
4686 | if (!i.tm.opcode_modifier.no_ssuf) | |
4687 | suffixes |= 1 << 4; | |
4688 | if (!i.tm.opcode_modifier.no_qsuf) | |
4689 | suffixes |= 1 << 5; | |
4690 | ||
4691 | /* There are more than suffix matches. */ | |
4692 | if (i.tm.opcode_modifier.w | |
9306ca4a | 4693 | || ((suffixes & (suffixes - 1)) |
40fb9820 L |
4694 | && !i.tm.opcode_modifier.defaultsize |
4695 | && !i.tm.opcode_modifier.ignoresize)) | |
9306ca4a JB |
4696 | { |
4697 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); | |
4698 | return 0; | |
4699 | } | |
4700 | } | |
29b0f896 | 4701 | } |
252b5132 | 4702 | |
9306ca4a JB |
4703 | /* Change the opcode based on the operand size given by i.suffix; |
4704 | We don't need to change things for byte insns. */ | |
4705 | ||
582d5edd L |
4706 | if (i.suffix |
4707 | && i.suffix != BYTE_MNEM_SUFFIX | |
c0f3af97 L |
4708 | && i.suffix != XMMWORD_MNEM_SUFFIX |
4709 | && i.suffix != YMMWORD_MNEM_SUFFIX) | |
29b0f896 AM |
4710 | { |
4711 | /* It's not a byte, select word/dword operation. */ | |
40fb9820 | 4712 | if (i.tm.opcode_modifier.w) |
29b0f896 | 4713 | { |
40fb9820 | 4714 | if (i.tm.opcode_modifier.shortform) |
29b0f896 AM |
4715 | i.tm.base_opcode |= 8; |
4716 | else | |
4717 | i.tm.base_opcode |= 1; | |
4718 | } | |
0f3f3d8b | 4719 | |
29b0f896 AM |
4720 | /* Now select between word & dword operations via the operand |
4721 | size prefix, except for instructions that will ignore this | |
4722 | prefix anyway. */ | |
ca61edf2 | 4723 | if (i.tm.opcode_modifier.addrprefixop0) |
cb712a9e | 4724 | { |
ca61edf2 L |
4725 | /* The address size override prefix changes the size of the |
4726 | first operand. */ | |
40fb9820 L |
4727 | if ((flag_code == CODE_32BIT |
4728 | && i.op->regs[0].reg_type.bitfield.reg16) | |
4729 | || (flag_code != CODE_32BIT | |
4730 | && i.op->regs[0].reg_type.bitfield.reg32)) | |
cb712a9e L |
4731 | if (!add_prefix (ADDR_PREFIX_OPCODE)) |
4732 | return 0; | |
4733 | } | |
4734 | else if (i.suffix != QWORD_MNEM_SUFFIX | |
4735 | && i.suffix != LONG_DOUBLE_MNEM_SUFFIX | |
40fb9820 L |
4736 | && !i.tm.opcode_modifier.ignoresize |
4737 | && !i.tm.opcode_modifier.floatmf | |
cb712a9e L |
4738 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) |
4739 | || (flag_code == CODE_64BIT | |
40fb9820 | 4740 | && i.tm.opcode_modifier.jumpbyte))) |
24eab124 AM |
4741 | { |
4742 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 4743 | |
40fb9820 | 4744 | if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */ |
29b0f896 | 4745 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 4746 | |
29b0f896 AM |
4747 | if (!add_prefix (prefix)) |
4748 | return 0; | |
24eab124 | 4749 | } |
252b5132 | 4750 | |
29b0f896 AM |
4751 | /* Set mode64 for an operand. */ |
4752 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 4753 | && flag_code == CODE_64BIT |
40fb9820 | 4754 | && !i.tm.opcode_modifier.norex64) |
46e883c5 L |
4755 | { |
4756 | /* Special case for xchg %rax,%rax. It is NOP and doesn't | |
d9a5e5e5 L |
4757 | need rex64. cmpxchg8b is also a special case. */ |
4758 | if (! (i.operands == 2 | |
4759 | && i.tm.base_opcode == 0x90 | |
4760 | && i.tm.extension_opcode == None | |
0dfbf9d7 L |
4761 | && operand_type_equal (&i.types [0], &acc64) |
4762 | && operand_type_equal (&i.types [1], &acc64)) | |
d9a5e5e5 L |
4763 | && ! (i.operands == 1 |
4764 | && i.tm.base_opcode == 0xfc7 | |
4765 | && i.tm.extension_opcode == 1 | |
40fb9820 L |
4766 | && !operand_type_check (i.types [0], reg) |
4767 | && operand_type_check (i.types [0], anymem))) | |
f6bee062 | 4768 | i.rex |= REX_W; |
46e883c5 | 4769 | } |
3e73aa7c | 4770 | |
29b0f896 AM |
4771 | /* Size floating point instruction. */ |
4772 | if (i.suffix == LONG_MNEM_SUFFIX) | |
40fb9820 | 4773 | if (i.tm.opcode_modifier.floatmf) |
543613e9 | 4774 | i.tm.base_opcode ^= 4; |
29b0f896 | 4775 | } |
7ecd2f8b | 4776 | |
29b0f896 AM |
4777 | return 1; |
4778 | } | |
3e73aa7c | 4779 | |
29b0f896 | 4780 | static int |
543613e9 | 4781 | check_byte_reg (void) |
29b0f896 AM |
4782 | { |
4783 | int op; | |
543613e9 | 4784 | |
29b0f896 AM |
4785 | for (op = i.operands; --op >= 0;) |
4786 | { | |
4787 | /* If this is an eight bit register, it's OK. If it's the 16 or | |
4788 | 32 bit version of an eight bit register, we will just use the | |
4789 | low portion, and that's OK too. */ | |
40fb9820 | 4790 | if (i.types[op].bitfield.reg8) |
29b0f896 AM |
4791 | continue; |
4792 | ||
5a819eb9 JB |
4793 | /* I/O port address operands are OK too. */ |
4794 | if (i.tm.operand_types[op].bitfield.inoutportreg) | |
4795 | continue; | |
4796 | ||
9344ff29 L |
4797 | /* crc32 doesn't generate this warning. */ |
4798 | if (i.tm.base_opcode == 0xf20f38f0) | |
4799 | continue; | |
4800 | ||
40fb9820 L |
4801 | if ((i.types[op].bitfield.reg16 |
4802 | || i.types[op].bitfield.reg32 | |
4803 | || i.types[op].bitfield.reg64) | |
5a819eb9 JB |
4804 | && i.op[op].regs->reg_num < 4 |
4805 | /* Prohibit these changes in 64bit mode, since the lowering | |
4806 | would be more complicated. */ | |
4807 | && flag_code != CODE_64BIT) | |
29b0f896 | 4808 | { |
29b0f896 | 4809 | #if REGISTER_WARNINGS |
5a819eb9 | 4810 | if (!quiet_warnings) |
a540244d L |
4811 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
4812 | register_prefix, | |
40fb9820 | 4813 | (i.op[op].regs + (i.types[op].bitfield.reg16 |
29b0f896 AM |
4814 | ? REGNAM_AL - REGNAM_AX |
4815 | : REGNAM_AL - REGNAM_EAX))->reg_name, | |
a540244d | 4816 | register_prefix, |
29b0f896 AM |
4817 | i.op[op].regs->reg_name, |
4818 | i.suffix); | |
4819 | #endif | |
4820 | continue; | |
4821 | } | |
4822 | /* Any other register is bad. */ | |
40fb9820 L |
4823 | if (i.types[op].bitfield.reg16 |
4824 | || i.types[op].bitfield.reg32 | |
4825 | || i.types[op].bitfield.reg64 | |
4826 | || i.types[op].bitfield.regmmx | |
4827 | || i.types[op].bitfield.regxmm | |
c0f3af97 | 4828 | || i.types[op].bitfield.regymm |
40fb9820 L |
4829 | || i.types[op].bitfield.sreg2 |
4830 | || i.types[op].bitfield.sreg3 | |
4831 | || i.types[op].bitfield.control | |
4832 | || i.types[op].bitfield.debug | |
4833 | || i.types[op].bitfield.test | |
4834 | || i.types[op].bitfield.floatreg | |
4835 | || i.types[op].bitfield.floatacc) | |
29b0f896 | 4836 | { |
a540244d L |
4837 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
4838 | register_prefix, | |
29b0f896 AM |
4839 | i.op[op].regs->reg_name, |
4840 | i.tm.name, | |
4841 | i.suffix); | |
4842 | return 0; | |
4843 | } | |
4844 | } | |
4845 | return 1; | |
4846 | } | |
4847 | ||
4848 | static int | |
e3bb37b5 | 4849 | check_long_reg (void) |
29b0f896 AM |
4850 | { |
4851 | int op; | |
4852 | ||
4853 | for (op = i.operands; --op >= 0;) | |
4854 | /* Reject eight bit registers, except where the template requires | |
4855 | them. (eg. movzb) */ | |
40fb9820 L |
4856 | if (i.types[op].bitfield.reg8 |
4857 | && (i.tm.operand_types[op].bitfield.reg16 | |
4858 | || i.tm.operand_types[op].bitfield.reg32 | |
4859 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 4860 | { |
a540244d L |
4861 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
4862 | register_prefix, | |
29b0f896 AM |
4863 | i.op[op].regs->reg_name, |
4864 | i.tm.name, | |
4865 | i.suffix); | |
4866 | return 0; | |
4867 | } | |
4868 | /* Warn if the e prefix on a general reg is missing. */ | |
4869 | else if ((!quiet_warnings || flag_code == CODE_64BIT) | |
40fb9820 L |
4870 | && i.types[op].bitfield.reg16 |
4871 | && (i.tm.operand_types[op].bitfield.reg32 | |
4872 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 AM |
4873 | { |
4874 | /* Prohibit these changes in the 64bit mode, since the | |
4875 | lowering is more complicated. */ | |
4876 | if (flag_code == CODE_64BIT) | |
252b5132 | 4877 | { |
2b5d6a91 | 4878 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 4879 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
4880 | i.suffix); |
4881 | return 0; | |
252b5132 | 4882 | } |
29b0f896 AM |
4883 | #if REGISTER_WARNINGS |
4884 | else | |
a540244d L |
4885 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
4886 | register_prefix, | |
29b0f896 | 4887 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, |
a540244d | 4888 | register_prefix, |
29b0f896 AM |
4889 | i.op[op].regs->reg_name, |
4890 | i.suffix); | |
4891 | #endif | |
252b5132 | 4892 | } |
29b0f896 | 4893 | /* Warn if the r prefix on a general reg is missing. */ |
40fb9820 L |
4894 | else if (i.types[op].bitfield.reg64 |
4895 | && (i.tm.operand_types[op].bitfield.reg32 | |
4896 | || i.tm.operand_types[op].bitfield.acc)) | |
252b5132 | 4897 | { |
34828aad | 4898 | if (intel_syntax |
ca61edf2 | 4899 | && i.tm.opcode_modifier.toqword |
40fb9820 | 4900 | && !i.types[0].bitfield.regxmm) |
34828aad | 4901 | { |
ca61edf2 | 4902 | /* Convert to QWORD. We want REX byte. */ |
34828aad L |
4903 | i.suffix = QWORD_MNEM_SUFFIX; |
4904 | } | |
4905 | else | |
4906 | { | |
2b5d6a91 | 4907 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
4908 | register_prefix, i.op[op].regs->reg_name, |
4909 | i.suffix); | |
4910 | return 0; | |
4911 | } | |
29b0f896 AM |
4912 | } |
4913 | return 1; | |
4914 | } | |
252b5132 | 4915 | |
29b0f896 | 4916 | static int |
e3bb37b5 | 4917 | check_qword_reg (void) |
29b0f896 AM |
4918 | { |
4919 | int op; | |
252b5132 | 4920 | |
29b0f896 AM |
4921 | for (op = i.operands; --op >= 0; ) |
4922 | /* Reject eight bit registers, except where the template requires | |
4923 | them. (eg. movzb) */ | |
40fb9820 L |
4924 | if (i.types[op].bitfield.reg8 |
4925 | && (i.tm.operand_types[op].bitfield.reg16 | |
4926 | || i.tm.operand_types[op].bitfield.reg32 | |
4927 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 4928 | { |
a540244d L |
4929 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
4930 | register_prefix, | |
29b0f896 AM |
4931 | i.op[op].regs->reg_name, |
4932 | i.tm.name, | |
4933 | i.suffix); | |
4934 | return 0; | |
4935 | } | |
4936 | /* Warn if the e prefix on a general reg is missing. */ | |
40fb9820 L |
4937 | else if ((i.types[op].bitfield.reg16 |
4938 | || i.types[op].bitfield.reg32) | |
4939 | && (i.tm.operand_types[op].bitfield.reg32 | |
4940 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 AM |
4941 | { |
4942 | /* Prohibit these changes in the 64bit mode, since the | |
4943 | lowering is more complicated. */ | |
34828aad | 4944 | if (intel_syntax |
ca61edf2 | 4945 | && i.tm.opcode_modifier.todword |
40fb9820 | 4946 | && !i.types[0].bitfield.regxmm) |
34828aad | 4947 | { |
ca61edf2 | 4948 | /* Convert to DWORD. We don't want REX byte. */ |
34828aad L |
4949 | i.suffix = LONG_MNEM_SUFFIX; |
4950 | } | |
4951 | else | |
4952 | { | |
2b5d6a91 | 4953 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
4954 | register_prefix, i.op[op].regs->reg_name, |
4955 | i.suffix); | |
4956 | return 0; | |
4957 | } | |
252b5132 | 4958 | } |
29b0f896 AM |
4959 | return 1; |
4960 | } | |
252b5132 | 4961 | |
29b0f896 | 4962 | static int |
e3bb37b5 | 4963 | check_word_reg (void) |
29b0f896 AM |
4964 | { |
4965 | int op; | |
4966 | for (op = i.operands; --op >= 0;) | |
4967 | /* Reject eight bit registers, except where the template requires | |
4968 | them. (eg. movzb) */ | |
40fb9820 L |
4969 | if (i.types[op].bitfield.reg8 |
4970 | && (i.tm.operand_types[op].bitfield.reg16 | |
4971 | || i.tm.operand_types[op].bitfield.reg32 | |
4972 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 4973 | { |
a540244d L |
4974 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
4975 | register_prefix, | |
29b0f896 AM |
4976 | i.op[op].regs->reg_name, |
4977 | i.tm.name, | |
4978 | i.suffix); | |
4979 | return 0; | |
4980 | } | |
4981 | /* Warn if the e prefix on a general reg is present. */ | |
4982 | else if ((!quiet_warnings || flag_code == CODE_64BIT) | |
40fb9820 L |
4983 | && i.types[op].bitfield.reg32 |
4984 | && (i.tm.operand_types[op].bitfield.reg16 | |
4985 | || i.tm.operand_types[op].bitfield.acc)) | |
252b5132 | 4986 | { |
29b0f896 AM |
4987 | /* Prohibit these changes in the 64bit mode, since the |
4988 | lowering is more complicated. */ | |
4989 | if (flag_code == CODE_64BIT) | |
252b5132 | 4990 | { |
2b5d6a91 | 4991 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 4992 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
4993 | i.suffix); |
4994 | return 0; | |
252b5132 | 4995 | } |
29b0f896 AM |
4996 | else |
4997 | #if REGISTER_WARNINGS | |
a540244d L |
4998 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
4999 | register_prefix, | |
29b0f896 | 5000 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, |
a540244d | 5001 | register_prefix, |
29b0f896 AM |
5002 | i.op[op].regs->reg_name, |
5003 | i.suffix); | |
5004 | #endif | |
5005 | } | |
5006 | return 1; | |
5007 | } | |
252b5132 | 5008 | |
29b0f896 | 5009 | static int |
40fb9820 | 5010 | update_imm (unsigned int j) |
29b0f896 | 5011 | { |
bc0844ae | 5012 | i386_operand_type overlap = i.types[j]; |
40fb9820 L |
5013 | if ((overlap.bitfield.imm8 |
5014 | || overlap.bitfield.imm8s | |
5015 | || overlap.bitfield.imm16 | |
5016 | || overlap.bitfield.imm32 | |
5017 | || overlap.bitfield.imm32s | |
5018 | || overlap.bitfield.imm64) | |
0dfbf9d7 L |
5019 | && !operand_type_equal (&overlap, &imm8) |
5020 | && !operand_type_equal (&overlap, &imm8s) | |
5021 | && !operand_type_equal (&overlap, &imm16) | |
5022 | && !operand_type_equal (&overlap, &imm32) | |
5023 | && !operand_type_equal (&overlap, &imm32s) | |
5024 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 AM |
5025 | { |
5026 | if (i.suffix) | |
5027 | { | |
40fb9820 L |
5028 | i386_operand_type temp; |
5029 | ||
0dfbf9d7 | 5030 | operand_type_set (&temp, 0); |
7ab9ffdd | 5031 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
5032 | { |
5033 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
5034 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
5035 | } | |
5036 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
5037 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
5038 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
5039 | { | |
5040 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
5041 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
5042 | } | |
5043 | else | |
5044 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
5045 | overlap = temp; | |
29b0f896 | 5046 | } |
0dfbf9d7 L |
5047 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
5048 | || operand_type_equal (&overlap, &imm16_32) | |
5049 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 5050 | { |
40fb9820 | 5051 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 5052 | overlap = imm16; |
40fb9820 | 5053 | else |
65da13b5 | 5054 | overlap = imm32s; |
29b0f896 | 5055 | } |
0dfbf9d7 L |
5056 | if (!operand_type_equal (&overlap, &imm8) |
5057 | && !operand_type_equal (&overlap, &imm8s) | |
5058 | && !operand_type_equal (&overlap, &imm16) | |
5059 | && !operand_type_equal (&overlap, &imm32) | |
5060 | && !operand_type_equal (&overlap, &imm32s) | |
5061 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 | 5062 | { |
4eed87de AM |
5063 | as_bad (_("no instruction mnemonic suffix given; " |
5064 | "can't determine immediate size")); | |
29b0f896 AM |
5065 | return 0; |
5066 | } | |
5067 | } | |
40fb9820 | 5068 | i.types[j] = overlap; |
29b0f896 | 5069 | |
40fb9820 L |
5070 | return 1; |
5071 | } | |
5072 | ||
5073 | static int | |
5074 | finalize_imm (void) | |
5075 | { | |
bc0844ae | 5076 | unsigned int j, n; |
29b0f896 | 5077 | |
bc0844ae L |
5078 | /* Update the first 2 immediate operands. */ |
5079 | n = i.operands > 2 ? 2 : i.operands; | |
5080 | if (n) | |
5081 | { | |
5082 | for (j = 0; j < n; j++) | |
5083 | if (update_imm (j) == 0) | |
5084 | return 0; | |
40fb9820 | 5085 | |
bc0844ae L |
5086 | /* The 3rd operand can't be immediate operand. */ |
5087 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
5088 | } | |
29b0f896 AM |
5089 | |
5090 | return 1; | |
5091 | } | |
5092 | ||
c0f3af97 L |
5093 | static int |
5094 | bad_implicit_operand (int xmm) | |
5095 | { | |
91d6fa6a NC |
5096 | const char *ireg = xmm ? "xmm0" : "ymm0"; |
5097 | ||
c0f3af97 L |
5098 | if (intel_syntax) |
5099 | as_bad (_("the last operand of `%s' must be `%s%s'"), | |
91d6fa6a | 5100 | i.tm.name, register_prefix, ireg); |
c0f3af97 L |
5101 | else |
5102 | as_bad (_("the first operand of `%s' must be `%s%s'"), | |
91d6fa6a | 5103 | i.tm.name, register_prefix, ireg); |
c0f3af97 L |
5104 | return 0; |
5105 | } | |
5106 | ||
29b0f896 | 5107 | static int |
e3bb37b5 | 5108 | process_operands (void) |
29b0f896 AM |
5109 | { |
5110 | /* Default segment register this instruction will use for memory | |
5111 | accesses. 0 means unknown. This is only for optimizing out | |
5112 | unnecessary segment overrides. */ | |
5113 | const seg_entry *default_seg = 0; | |
5114 | ||
2426c15f | 5115 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
29b0f896 | 5116 | { |
91d6fa6a NC |
5117 | unsigned int dupl = i.operands; |
5118 | unsigned int dest = dupl - 1; | |
9fcfb3d7 L |
5119 | unsigned int j; |
5120 | ||
c0f3af97 | 5121 | /* The destination must be an xmm register. */ |
9c2799c2 | 5122 | gas_assert (i.reg_operands |
91d6fa6a | 5123 | && MAX_OPERANDS > dupl |
7ab9ffdd | 5124 | && operand_type_equal (&i.types[dest], ®xmm)); |
c0f3af97 L |
5125 | |
5126 | if (i.tm.opcode_modifier.firstxmm0) | |
e2ec9d29 | 5127 | { |
c0f3af97 | 5128 | /* The first operand is implicit and must be xmm0. */ |
9c2799c2 | 5129 | gas_assert (operand_type_equal (&i.types[0], ®xmm)); |
4c692bc7 | 5130 | if (register_number (i.op[0].regs) != 0) |
c0f3af97 L |
5131 | return bad_implicit_operand (1); |
5132 | ||
8cd7925b | 5133 | if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) |
c0f3af97 L |
5134 | { |
5135 | /* Keep xmm0 for instructions with VEX prefix and 3 | |
5136 | sources. */ | |
5137 | goto duplicate; | |
5138 | } | |
e2ec9d29 | 5139 | else |
c0f3af97 L |
5140 | { |
5141 | /* We remove the first xmm0 and keep the number of | |
5142 | operands unchanged, which in fact duplicates the | |
5143 | destination. */ | |
5144 | for (j = 1; j < i.operands; j++) | |
5145 | { | |
5146 | i.op[j - 1] = i.op[j]; | |
5147 | i.types[j - 1] = i.types[j]; | |
5148 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; | |
5149 | } | |
5150 | } | |
5151 | } | |
5152 | else if (i.tm.opcode_modifier.implicit1stxmm0) | |
7ab9ffdd | 5153 | { |
91d6fa6a | 5154 | gas_assert ((MAX_OPERANDS - 1) > dupl |
8cd7925b L |
5155 | && (i.tm.opcode_modifier.vexsources |
5156 | == VEX3SOURCES)); | |
c0f3af97 L |
5157 | |
5158 | /* Add the implicit xmm0 for instructions with VEX prefix | |
5159 | and 3 sources. */ | |
5160 | for (j = i.operands; j > 0; j--) | |
5161 | { | |
5162 | i.op[j] = i.op[j - 1]; | |
5163 | i.types[j] = i.types[j - 1]; | |
5164 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
5165 | } | |
5166 | i.op[0].regs | |
5167 | = (const reg_entry *) hash_find (reg_hash, "xmm0"); | |
7ab9ffdd | 5168 | i.types[0] = regxmm; |
c0f3af97 L |
5169 | i.tm.operand_types[0] = regxmm; |
5170 | ||
5171 | i.operands += 2; | |
5172 | i.reg_operands += 2; | |
5173 | i.tm.operands += 2; | |
5174 | ||
91d6fa6a | 5175 | dupl++; |
c0f3af97 | 5176 | dest++; |
91d6fa6a NC |
5177 | i.op[dupl] = i.op[dest]; |
5178 | i.types[dupl] = i.types[dest]; | |
5179 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
e2ec9d29 | 5180 | } |
c0f3af97 L |
5181 | else |
5182 | { | |
5183 | duplicate: | |
5184 | i.operands++; | |
5185 | i.reg_operands++; | |
5186 | i.tm.operands++; | |
5187 | ||
91d6fa6a NC |
5188 | i.op[dupl] = i.op[dest]; |
5189 | i.types[dupl] = i.types[dest]; | |
5190 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
c0f3af97 L |
5191 | } |
5192 | ||
5193 | if (i.tm.opcode_modifier.immext) | |
5194 | process_immext (); | |
5195 | } | |
5196 | else if (i.tm.opcode_modifier.firstxmm0) | |
5197 | { | |
5198 | unsigned int j; | |
5199 | ||
5200 | /* The first operand is implicit and must be xmm0/ymm0. */ | |
9c2799c2 | 5201 | gas_assert (i.reg_operands |
7ab9ffdd L |
5202 | && (operand_type_equal (&i.types[0], ®xmm) |
5203 | || operand_type_equal (&i.types[0], ®ymm))); | |
4c692bc7 | 5204 | if (register_number (i.op[0].regs) != 0) |
c0f3af97 | 5205 | return bad_implicit_operand (i.types[0].bitfield.regxmm); |
9fcfb3d7 L |
5206 | |
5207 | for (j = 1; j < i.operands; j++) | |
5208 | { | |
5209 | i.op[j - 1] = i.op[j]; | |
5210 | i.types[j - 1] = i.types[j]; | |
5211 | ||
5212 | /* We need to adjust fields in i.tm since they are used by | |
5213 | build_modrm_byte. */ | |
5214 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
5215 | } | |
5216 | ||
e2ec9d29 L |
5217 | i.operands--; |
5218 | i.reg_operands--; | |
e2ec9d29 L |
5219 | i.tm.operands--; |
5220 | } | |
5221 | else if (i.tm.opcode_modifier.regkludge) | |
5222 | { | |
5223 | /* The imul $imm, %reg instruction is converted into | |
5224 | imul $imm, %reg, %reg, and the clr %reg instruction | |
5225 | is converted into xor %reg, %reg. */ | |
5226 | ||
5227 | unsigned int first_reg_op; | |
5228 | ||
5229 | if (operand_type_check (i.types[0], reg)) | |
5230 | first_reg_op = 0; | |
5231 | else | |
5232 | first_reg_op = 1; | |
5233 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 5234 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 5235 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
5236 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
5237 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
5238 | i.operands++; | |
5239 | i.reg_operands++; | |
29b0f896 AM |
5240 | } |
5241 | ||
40fb9820 | 5242 | if (i.tm.opcode_modifier.shortform) |
29b0f896 | 5243 | { |
40fb9820 L |
5244 | if (i.types[0].bitfield.sreg2 |
5245 | || i.types[0].bitfield.sreg3) | |
29b0f896 | 5246 | { |
4eed87de AM |
5247 | if (i.tm.base_opcode == POP_SEG_SHORT |
5248 | && i.op[0].regs->reg_num == 1) | |
29b0f896 | 5249 | { |
a87af027 | 5250 | as_bad (_("you can't `pop %scs'"), register_prefix); |
4eed87de | 5251 | return 0; |
29b0f896 | 5252 | } |
4eed87de AM |
5253 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
5254 | if ((i.op[0].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 5255 | i.rex |= REX_B; |
4eed87de AM |
5256 | } |
5257 | else | |
5258 | { | |
7ab9ffdd | 5259 | /* The register or float register operand is in operand |
85f10a01 | 5260 | 0 or 1. */ |
40fb9820 | 5261 | unsigned int op; |
7ab9ffdd L |
5262 | |
5263 | if (i.types[0].bitfield.floatreg | |
5264 | || operand_type_check (i.types[0], reg)) | |
5265 | op = 0; | |
5266 | else | |
5267 | op = 1; | |
4eed87de AM |
5268 | /* Register goes in low 3 bits of opcode. */ |
5269 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
5270 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 5271 | i.rex |= REX_B; |
40fb9820 | 5272 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 | 5273 | { |
4eed87de AM |
5274 | /* Warn about some common errors, but press on regardless. |
5275 | The first case can be generated by gcc (<= 2.8.1). */ | |
5276 | if (i.operands == 2) | |
5277 | { | |
5278 | /* Reversed arguments on faddp, fsubp, etc. */ | |
a540244d | 5279 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, |
d8a1b51e JB |
5280 | register_prefix, i.op[!intel_syntax].regs->reg_name, |
5281 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
4eed87de AM |
5282 | } |
5283 | else | |
5284 | { | |
5285 | /* Extraneous `l' suffix on fp insn. */ | |
a540244d L |
5286 | as_warn (_("translating to `%s %s%s'"), i.tm.name, |
5287 | register_prefix, i.op[0].regs->reg_name); | |
4eed87de | 5288 | } |
29b0f896 AM |
5289 | } |
5290 | } | |
5291 | } | |
40fb9820 | 5292 | else if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
5293 | { |
5294 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
5295 | must be put into the modrm byte). Now, we make the modrm and |
5296 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
5297 | |
5298 | default_seg = build_modrm_byte (); | |
5299 | } | |
8a2ed489 | 5300 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
29b0f896 AM |
5301 | { |
5302 | default_seg = &ds; | |
5303 | } | |
40fb9820 | 5304 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
5305 | { |
5306 | /* For the string instructions that allow a segment override | |
5307 | on one of their operands, the default segment is ds. */ | |
5308 | default_seg = &ds; | |
5309 | } | |
5310 | ||
75178d9d L |
5311 | if (i.tm.base_opcode == 0x8d /* lea */ |
5312 | && i.seg[0] | |
5313 | && !quiet_warnings) | |
30123838 | 5314 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); |
52271982 AM |
5315 | |
5316 | /* If a segment was explicitly specified, and the specified segment | |
5317 | is not the default, use an opcode prefix to select it. If we | |
5318 | never figured out what the default segment is, then default_seg | |
5319 | will be zero at this point, and the specified segment prefix will | |
5320 | always be used. */ | |
29b0f896 AM |
5321 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
5322 | { | |
5323 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
5324 | return 0; | |
5325 | } | |
5326 | return 1; | |
5327 | } | |
5328 | ||
5329 | static const seg_entry * | |
e3bb37b5 | 5330 | build_modrm_byte (void) |
29b0f896 AM |
5331 | { |
5332 | const seg_entry *default_seg = 0; | |
c0f3af97 | 5333 | unsigned int source, dest; |
8cd7925b | 5334 | int vex_3_sources; |
c0f3af97 L |
5335 | |
5336 | /* The first operand of instructions with VEX prefix and 3 sources | |
5337 | must be VEX_Imm4. */ | |
8cd7925b | 5338 | vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; |
c0f3af97 L |
5339 | if (vex_3_sources) |
5340 | { | |
91d6fa6a | 5341 | unsigned int nds, reg_slot; |
4c2c6516 | 5342 | expressionS *exp; |
c0f3af97 | 5343 | |
922d8de8 | 5344 | if (i.tm.opcode_modifier.veximmext |
a683cc34 SP |
5345 | && i.tm.opcode_modifier.immext) |
5346 | { | |
5347 | dest = i.operands - 2; | |
5348 | gas_assert (dest == 3); | |
5349 | } | |
922d8de8 | 5350 | else |
a683cc34 | 5351 | dest = i.operands - 1; |
c0f3af97 | 5352 | nds = dest - 1; |
922d8de8 | 5353 | |
a683cc34 SP |
5354 | /* There are 2 kinds of instructions: |
5355 | 1. 5 operands: 4 register operands or 3 register operands | |
5356 | plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and | |
5357 | VexW0 or VexW1. The destination must be either XMM or YMM | |
5358 | register. | |
5359 | 2. 4 operands: 4 register operands or 3 register operands | |
5360 | plus 1 memory operand, VexXDS, and VexImmExt */ | |
922d8de8 | 5361 | gas_assert ((i.reg_operands == 4 |
a683cc34 SP |
5362 | || (i.reg_operands == 3 && i.mem_operands == 1)) |
5363 | && i.tm.opcode_modifier.vexvvvv == VEXXDS | |
5364 | && (i.tm.opcode_modifier.veximmext | |
5365 | || (i.imm_operands == 1 | |
5366 | && i.types[0].bitfield.vec_imm4 | |
5367 | && (i.tm.opcode_modifier.vexw == VEXW0 | |
5368 | || i.tm.opcode_modifier.vexw == VEXW1) | |
5369 | && (operand_type_equal (&i.tm.operand_types[dest], ®xmm) | |
5370 | || operand_type_equal (&i.tm.operand_types[dest], ®ymm))))); | |
5371 | ||
5372 | if (i.imm_operands == 0) | |
5373 | { | |
5374 | /* When there is no immediate operand, generate an 8bit | |
5375 | immediate operand to encode the first operand. */ | |
5376 | exp = &im_expressions[i.imm_operands++]; | |
5377 | i.op[i.operands].imms = exp; | |
5378 | i.types[i.operands] = imm8; | |
5379 | i.operands++; | |
5380 | /* If VexW1 is set, the first operand is the source and | |
5381 | the second operand is encoded in the immediate operand. */ | |
5382 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
5383 | { | |
5384 | source = 0; | |
5385 | reg_slot = 1; | |
5386 | } | |
5387 | else | |
5388 | { | |
5389 | source = 1; | |
5390 | reg_slot = 0; | |
5391 | } | |
5392 | ||
5393 | /* FMA swaps REG and NDS. */ | |
5394 | if (i.tm.cpu_flags.bitfield.cpufma) | |
5395 | { | |
5396 | unsigned int tmp; | |
5397 | tmp = reg_slot; | |
5398 | reg_slot = nds; | |
5399 | nds = tmp; | |
5400 | } | |
5401 | ||
24981e7b L |
5402 | gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot], |
5403 | ®xmm) | |
a683cc34 SP |
5404 | || operand_type_equal (&i.tm.operand_types[reg_slot], |
5405 | ®ymm)); | |
5406 | exp->X_op = O_constant; | |
4c692bc7 | 5407 | exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; |
a683cc34 | 5408 | } |
922d8de8 | 5409 | else |
a683cc34 SP |
5410 | { |
5411 | unsigned int imm_slot; | |
5412 | ||
5413 | if (i.tm.opcode_modifier.vexw == VEXW0) | |
5414 | { | |
5415 | /* If VexW0 is set, the third operand is the source and | |
5416 | the second operand is encoded in the immediate | |
5417 | operand. */ | |
5418 | source = 2; | |
5419 | reg_slot = 1; | |
5420 | } | |
5421 | else | |
5422 | { | |
5423 | /* VexW1 is set, the second operand is the source and | |
5424 | the third operand is encoded in the immediate | |
5425 | operand. */ | |
5426 | source = 1; | |
5427 | reg_slot = 2; | |
5428 | } | |
5429 | ||
5430 | if (i.tm.opcode_modifier.immext) | |
5431 | { | |
5432 | /* When ImmExt is set, the immdiate byte is the last | |
5433 | operand. */ | |
5434 | imm_slot = i.operands - 1; | |
5435 | source--; | |
5436 | reg_slot--; | |
5437 | } | |
5438 | else | |
5439 | { | |
5440 | imm_slot = 0; | |
5441 | ||
5442 | /* Turn on Imm8 so that output_imm will generate it. */ | |
5443 | i.types[imm_slot].bitfield.imm8 = 1; | |
5444 | } | |
5445 | ||
24981e7b L |
5446 | gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot], |
5447 | ®xmm) | |
5448 | || operand_type_equal (&i.tm.operand_types[reg_slot], | |
5449 | ®ymm)); | |
a683cc34 | 5450 | i.op[imm_slot].imms->X_add_number |
4c692bc7 | 5451 | |= register_number (i.op[reg_slot].regs) << 4; |
a683cc34 SP |
5452 | } |
5453 | ||
5454 | gas_assert (operand_type_equal (&i.tm.operand_types[nds], ®xmm) | |
5455 | || operand_type_equal (&i.tm.operand_types[nds], | |
5456 | ®ymm)); | |
dae39acc | 5457 | i.vex.register_specifier = i.op[nds].regs; |
c0f3af97 L |
5458 | } |
5459 | else | |
5460 | source = dest = 0; | |
29b0f896 AM |
5461 | |
5462 | /* i.reg_operands MUST be the number of real register operands; | |
c0f3af97 L |
5463 | implicit registers do not count. If there are 3 register |
5464 | operands, it must be a instruction with VexNDS. For a | |
5465 | instruction with VexNDD, the destination register is encoded | |
5466 | in VEX prefix. If there are 4 register operands, it must be | |
5467 | a instruction with VEX prefix and 3 sources. */ | |
7ab9ffdd L |
5468 | if (i.mem_operands == 0 |
5469 | && ((i.reg_operands == 2 | |
2426c15f | 5470 | && i.tm.opcode_modifier.vexvvvv <= VEXXDS) |
7ab9ffdd | 5471 | || (i.reg_operands == 3 |
2426c15f | 5472 | && i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd | 5473 | || (i.reg_operands == 4 && vex_3_sources))) |
29b0f896 | 5474 | { |
cab737b9 L |
5475 | switch (i.operands) |
5476 | { | |
5477 | case 2: | |
5478 | source = 0; | |
5479 | break; | |
5480 | case 3: | |
c81128dc L |
5481 | /* When there are 3 operands, one of them may be immediate, |
5482 | which may be the first or the last operand. Otherwise, | |
c0f3af97 L |
5483 | the first operand must be shift count register (cl) or it |
5484 | is an instruction with VexNDS. */ | |
9c2799c2 | 5485 | gas_assert (i.imm_operands == 1 |
7ab9ffdd | 5486 | || (i.imm_operands == 0 |
2426c15f | 5487 | && (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd | 5488 | || i.types[0].bitfield.shiftcount))); |
40fb9820 L |
5489 | if (operand_type_check (i.types[0], imm) |
5490 | || i.types[0].bitfield.shiftcount) | |
5491 | source = 1; | |
5492 | else | |
5493 | source = 0; | |
cab737b9 L |
5494 | break; |
5495 | case 4: | |
368d64cc L |
5496 | /* When there are 4 operands, the first two must be 8bit |
5497 | immediate operands. The source operand will be the 3rd | |
c0f3af97 L |
5498 | one. |
5499 | ||
5500 | For instructions with VexNDS, if the first operand | |
5501 | an imm8, the source operand is the 2nd one. If the last | |
5502 | operand is imm8, the source operand is the first one. */ | |
9c2799c2 | 5503 | gas_assert ((i.imm_operands == 2 |
7ab9ffdd L |
5504 | && i.types[0].bitfield.imm8 |
5505 | && i.types[1].bitfield.imm8) | |
2426c15f | 5506 | || (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd L |
5507 | && i.imm_operands == 1 |
5508 | && (i.types[0].bitfield.imm8 | |
5509 | || i.types[i.operands - 1].bitfield.imm8))); | |
9f2670f2 L |
5510 | if (i.imm_operands == 2) |
5511 | source = 2; | |
5512 | else | |
c0f3af97 L |
5513 | { |
5514 | if (i.types[0].bitfield.imm8) | |
5515 | source = 1; | |
5516 | else | |
5517 | source = 0; | |
5518 | } | |
c0f3af97 L |
5519 | break; |
5520 | case 5: | |
cab737b9 L |
5521 | break; |
5522 | default: | |
5523 | abort (); | |
5524 | } | |
5525 | ||
c0f3af97 L |
5526 | if (!vex_3_sources) |
5527 | { | |
5528 | dest = source + 1; | |
5529 | ||
2426c15f | 5530 | if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
c0f3af97 L |
5531 | { |
5532 | /* For instructions with VexNDS, the register-only | |
f12dc422 L |
5533 | source operand must be 32/64bit integer, XMM or |
5534 | YMM register. It is encoded in VEX prefix. We | |
5535 | need to clear RegMem bit before calling | |
5536 | operand_type_equal. */ | |
5537 | ||
5538 | i386_operand_type op; | |
5539 | unsigned int vvvv; | |
5540 | ||
5541 | /* Check register-only source operand when two source | |
5542 | operands are swapped. */ | |
5543 | if (!i.tm.operand_types[source].bitfield.baseindex | |
5544 | && i.tm.operand_types[dest].bitfield.baseindex) | |
5545 | { | |
5546 | vvvv = source; | |
5547 | source = dest; | |
5548 | } | |
5549 | else | |
5550 | vvvv = dest; | |
5551 | ||
5552 | op = i.tm.operand_types[vvvv]; | |
fa99fab2 | 5553 | op.bitfield.regmem = 0; |
c0f3af97 | 5554 | if ((dest + 1) >= i.operands |
f12dc422 L |
5555 | || (op.bitfield.reg32 != 1 |
5556 | && !op.bitfield.reg64 != 1 | |
5557 | && !operand_type_equal (&op, ®xmm) | |
fa99fab2 | 5558 | && !operand_type_equal (&op, ®ymm))) |
c0f3af97 | 5559 | abort (); |
f12dc422 | 5560 | i.vex.register_specifier = i.op[vvvv].regs; |
c0f3af97 L |
5561 | dest++; |
5562 | } | |
5563 | } | |
29b0f896 AM |
5564 | |
5565 | i.rm.mode = 3; | |
5566 | /* One of the register operands will be encoded in the i.tm.reg | |
5567 | field, the other in the combined i.tm.mode and i.tm.regmem | |
5568 | fields. If no form of this instruction supports a memory | |
5569 | destination operand, then we assume the source operand may | |
5570 | sometimes be a memory operand and so we need to store the | |
5571 | destination in the i.rm.reg field. */ | |
40fb9820 L |
5572 | if (!i.tm.operand_types[dest].bitfield.regmem |
5573 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) | |
29b0f896 AM |
5574 | { |
5575 | i.rm.reg = i.op[dest].regs->reg_num; | |
5576 | i.rm.regmem = i.op[source].regs->reg_num; | |
5577 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 5578 | i.rex |= REX_R; |
29b0f896 | 5579 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 5580 | i.rex |= REX_B; |
29b0f896 AM |
5581 | } |
5582 | else | |
5583 | { | |
5584 | i.rm.reg = i.op[source].regs->reg_num; | |
5585 | i.rm.regmem = i.op[dest].regs->reg_num; | |
5586 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 5587 | i.rex |= REX_B; |
29b0f896 | 5588 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 5589 | i.rex |= REX_R; |
29b0f896 | 5590 | } |
161a04f6 | 5591 | if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B))) |
c4a530c5 | 5592 | { |
40fb9820 L |
5593 | if (!i.types[0].bitfield.control |
5594 | && !i.types[1].bitfield.control) | |
c4a530c5 | 5595 | abort (); |
161a04f6 | 5596 | i.rex &= ~(REX_R | REX_B); |
c4a530c5 JB |
5597 | add_prefix (LOCK_PREFIX_OPCODE); |
5598 | } | |
29b0f896 AM |
5599 | } |
5600 | else | |
5601 | { /* If it's not 2 reg operands... */ | |
c0f3af97 L |
5602 | unsigned int mem; |
5603 | ||
29b0f896 AM |
5604 | if (i.mem_operands) |
5605 | { | |
5606 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 5607 | unsigned int op; |
4eed87de | 5608 | |
7ab9ffdd L |
5609 | for (op = 0; op < i.operands; op++) |
5610 | if (operand_type_check (i.types[op], anymem)) | |
5611 | break; | |
7ab9ffdd | 5612 | gas_assert (op < i.operands); |
29b0f896 | 5613 | |
6c30d220 L |
5614 | if (i.tm.opcode_modifier.vecsib) |
5615 | { | |
5616 | if (i.index_reg->reg_num == RegEiz | |
5617 | || i.index_reg->reg_num == RegRiz) | |
5618 | abort (); | |
5619 | ||
5620 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
5621 | if (!i.base_reg) | |
5622 | { | |
5623 | i.sib.base = NO_BASE_REGISTER; | |
5624 | i.sib.scale = i.log2_scale_factor; | |
5625 | i.types[op].bitfield.disp8 = 0; | |
5626 | i.types[op].bitfield.disp16 = 0; | |
5627 | i.types[op].bitfield.disp64 = 0; | |
5628 | if (flag_code != CODE_64BIT) | |
5629 | { | |
5630 | /* Must be 32 bit */ | |
5631 | i.types[op].bitfield.disp32 = 1; | |
5632 | i.types[op].bitfield.disp32s = 0; | |
5633 | } | |
5634 | else | |
5635 | { | |
5636 | i.types[op].bitfield.disp32 = 0; | |
5637 | i.types[op].bitfield.disp32s = 1; | |
5638 | } | |
5639 | } | |
5640 | i.sib.index = i.index_reg->reg_num; | |
5641 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
5642 | i.rex |= REX_X; | |
5643 | } | |
5644 | ||
29b0f896 AM |
5645 | default_seg = &ds; |
5646 | ||
5647 | if (i.base_reg == 0) | |
5648 | { | |
5649 | i.rm.mode = 0; | |
5650 | if (!i.disp_operands) | |
6c30d220 L |
5651 | { |
5652 | fake_zero_displacement = 1; | |
5653 | /* Instructions with VSIB byte need 32bit displacement | |
5654 | if there is no base register. */ | |
5655 | if (i.tm.opcode_modifier.vecsib) | |
5656 | i.types[op].bitfield.disp32 = 1; | |
5657 | } | |
29b0f896 AM |
5658 | if (i.index_reg == 0) |
5659 | { | |
6c30d220 | 5660 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 5661 | /* Operand is just <disp> */ |
20f0a1fc | 5662 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
5663 | { |
5664 | /* 64bit mode overwrites the 32bit absolute | |
5665 | addressing by RIP relative addressing and | |
5666 | absolute addressing is encoded by one of the | |
5667 | redundant SIB forms. */ | |
5668 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
5669 | i.sib.base = NO_BASE_REGISTER; | |
5670 | i.sib.index = NO_INDEX_REGISTER; | |
fc225355 | 5671 | i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) |
40fb9820 | 5672 | ? disp32s : disp32); |
20f0a1fc | 5673 | } |
fc225355 L |
5674 | else if ((flag_code == CODE_16BIT) |
5675 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
5676 | { |
5677 | i.rm.regmem = NO_BASE_REGISTER_16; | |
40fb9820 | 5678 | i.types[op] = disp16; |
20f0a1fc NC |
5679 | } |
5680 | else | |
5681 | { | |
5682 | i.rm.regmem = NO_BASE_REGISTER; | |
40fb9820 | 5683 | i.types[op] = disp32; |
29b0f896 AM |
5684 | } |
5685 | } | |
6c30d220 | 5686 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 5687 | { |
6c30d220 | 5688 | /* !i.base_reg && i.index_reg */ |
db51cc60 L |
5689 | if (i.index_reg->reg_num == RegEiz |
5690 | || i.index_reg->reg_num == RegRiz) | |
5691 | i.sib.index = NO_INDEX_REGISTER; | |
5692 | else | |
5693 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
5694 | i.sib.base = NO_BASE_REGISTER; |
5695 | i.sib.scale = i.log2_scale_factor; | |
5696 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
40fb9820 L |
5697 | i.types[op].bitfield.disp8 = 0; |
5698 | i.types[op].bitfield.disp16 = 0; | |
5699 | i.types[op].bitfield.disp64 = 0; | |
29b0f896 | 5700 | if (flag_code != CODE_64BIT) |
40fb9820 L |
5701 | { |
5702 | /* Must be 32 bit */ | |
5703 | i.types[op].bitfield.disp32 = 1; | |
5704 | i.types[op].bitfield.disp32s = 0; | |
5705 | } | |
29b0f896 | 5706 | else |
40fb9820 L |
5707 | { |
5708 | i.types[op].bitfield.disp32 = 0; | |
5709 | i.types[op].bitfield.disp32s = 1; | |
5710 | } | |
29b0f896 | 5711 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 5712 | i.rex |= REX_X; |
29b0f896 AM |
5713 | } |
5714 | } | |
5715 | /* RIP addressing for 64bit mode. */ | |
9a04903e JB |
5716 | else if (i.base_reg->reg_num == RegRip || |
5717 | i.base_reg->reg_num == RegEip) | |
29b0f896 | 5718 | { |
6c30d220 | 5719 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 5720 | i.rm.regmem = NO_BASE_REGISTER; |
40fb9820 L |
5721 | i.types[op].bitfield.disp8 = 0; |
5722 | i.types[op].bitfield.disp16 = 0; | |
5723 | i.types[op].bitfield.disp32 = 0; | |
5724 | i.types[op].bitfield.disp32s = 1; | |
5725 | i.types[op].bitfield.disp64 = 0; | |
71903a11 | 5726 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
5727 | if (! i.disp_operands) |
5728 | fake_zero_displacement = 1; | |
29b0f896 | 5729 | } |
40fb9820 | 5730 | else if (i.base_reg->reg_type.bitfield.reg16) |
29b0f896 | 5731 | { |
6c30d220 | 5732 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
5733 | switch (i.base_reg->reg_num) |
5734 | { | |
5735 | case 3: /* (%bx) */ | |
5736 | if (i.index_reg == 0) | |
5737 | i.rm.regmem = 7; | |
5738 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
5739 | i.rm.regmem = i.index_reg->reg_num - 6; | |
5740 | break; | |
5741 | case 5: /* (%bp) */ | |
5742 | default_seg = &ss; | |
5743 | if (i.index_reg == 0) | |
5744 | { | |
5745 | i.rm.regmem = 6; | |
40fb9820 | 5746 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
5747 | { |
5748 | /* fake (%bp) into 0(%bp) */ | |
40fb9820 | 5749 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 5750 | fake_zero_displacement = 1; |
29b0f896 AM |
5751 | } |
5752 | } | |
5753 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
5754 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
5755 | break; | |
5756 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
5757 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
5758 | } | |
5759 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
5760 | } | |
5761 | else /* i.base_reg and 32/64 bit mode */ | |
5762 | { | |
5763 | if (flag_code == CODE_64BIT | |
40fb9820 L |
5764 | && operand_type_check (i.types[op], disp)) |
5765 | { | |
5766 | i386_operand_type temp; | |
0dfbf9d7 | 5767 | operand_type_set (&temp, 0); |
40fb9820 L |
5768 | temp.bitfield.disp8 = i.types[op].bitfield.disp8; |
5769 | i.types[op] = temp; | |
5770 | if (i.prefix[ADDR_PREFIX] == 0) | |
5771 | i.types[op].bitfield.disp32s = 1; | |
5772 | else | |
5773 | i.types[op].bitfield.disp32 = 1; | |
5774 | } | |
20f0a1fc | 5775 | |
6c30d220 L |
5776 | if (!i.tm.opcode_modifier.vecsib) |
5777 | i.rm.regmem = i.base_reg->reg_num; | |
29b0f896 | 5778 | if ((i.base_reg->reg_flags & RegRex) != 0) |
161a04f6 | 5779 | i.rex |= REX_B; |
29b0f896 AM |
5780 | i.sib.base = i.base_reg->reg_num; |
5781 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
5782 | complications. */ | |
848930b2 JB |
5783 | if (!(i.base_reg->reg_flags & RegRex) |
5784 | && (i.base_reg->reg_num == EBP_REG_NUM | |
5785 | || i.base_reg->reg_num == ESP_REG_NUM)) | |
29b0f896 | 5786 | default_seg = &ss; |
848930b2 | 5787 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
29b0f896 | 5788 | { |
848930b2 JB |
5789 | fake_zero_displacement = 1; |
5790 | i.types[op].bitfield.disp8 = 1; | |
29b0f896 AM |
5791 | } |
5792 | i.sib.scale = i.log2_scale_factor; | |
5793 | if (i.index_reg == 0) | |
5794 | { | |
6c30d220 | 5795 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
5796 | /* <disp>(%esp) becomes two byte modrm with no index |
5797 | register. We've already stored the code for esp | |
5798 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
5799 | Any base register besides %esp will not use the | |
5800 | extra modrm byte. */ | |
5801 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 | 5802 | } |
6c30d220 | 5803 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 5804 | { |
db51cc60 L |
5805 | if (i.index_reg->reg_num == RegEiz |
5806 | || i.index_reg->reg_num == RegRiz) | |
5807 | i.sib.index = NO_INDEX_REGISTER; | |
5808 | else | |
5809 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
5810 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
5811 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 5812 | i.rex |= REX_X; |
29b0f896 | 5813 | } |
67a4f2b7 AO |
5814 | |
5815 | if (i.disp_operands | |
5816 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
5817 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
5818 | i.rm.mode = 0; | |
5819 | else | |
a501d77e L |
5820 | { |
5821 | if (!fake_zero_displacement | |
5822 | && !i.disp_operands | |
5823 | && i.disp_encoding) | |
5824 | { | |
5825 | fake_zero_displacement = 1; | |
5826 | if (i.disp_encoding == disp_encoding_8bit) | |
5827 | i.types[op].bitfield.disp8 = 1; | |
5828 | else | |
5829 | i.types[op].bitfield.disp32 = 1; | |
5830 | } | |
5831 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
5832 | } | |
29b0f896 | 5833 | } |
252b5132 | 5834 | |
29b0f896 AM |
5835 | if (fake_zero_displacement) |
5836 | { | |
5837 | /* Fakes a zero displacement assuming that i.types[op] | |
5838 | holds the correct displacement size. */ | |
5839 | expressionS *exp; | |
5840 | ||
9c2799c2 | 5841 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
5842 | exp = &disp_expressions[i.disp_operands++]; |
5843 | i.op[op].disps = exp; | |
5844 | exp->X_op = O_constant; | |
5845 | exp->X_add_number = 0; | |
5846 | exp->X_add_symbol = (symbolS *) 0; | |
5847 | exp->X_op_symbol = (symbolS *) 0; | |
5848 | } | |
c0f3af97 L |
5849 | |
5850 | mem = op; | |
29b0f896 | 5851 | } |
c0f3af97 L |
5852 | else |
5853 | mem = ~0; | |
252b5132 | 5854 | |
8c43a48b | 5855 | if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) |
5dd85c99 SP |
5856 | { |
5857 | if (operand_type_check (i.types[0], imm)) | |
5858 | i.vex.register_specifier = NULL; | |
5859 | else | |
5860 | { | |
5861 | /* VEX.vvvv encodes one of the sources when the first | |
5862 | operand is not an immediate. */ | |
1ef99a7b | 5863 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
5864 | i.vex.register_specifier = i.op[0].regs; |
5865 | else | |
5866 | i.vex.register_specifier = i.op[1].regs; | |
5867 | } | |
5868 | ||
5869 | /* Destination is a XMM register encoded in the ModRM.reg | |
5870 | and VEX.R bit. */ | |
5871 | i.rm.reg = i.op[2].regs->reg_num; | |
5872 | if ((i.op[2].regs->reg_flags & RegRex) != 0) | |
5873 | i.rex |= REX_R; | |
5874 | ||
5875 | /* ModRM.rm and VEX.B encodes the other source. */ | |
5876 | if (!i.mem_operands) | |
5877 | { | |
5878 | i.rm.mode = 3; | |
5879 | ||
1ef99a7b | 5880 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
5881 | i.rm.regmem = i.op[1].regs->reg_num; |
5882 | else | |
5883 | i.rm.regmem = i.op[0].regs->reg_num; | |
5884 | ||
5885 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
5886 | i.rex |= REX_B; | |
5887 | } | |
5888 | } | |
2426c15f | 5889 | else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) |
f88c9eb0 SP |
5890 | { |
5891 | i.vex.register_specifier = i.op[2].regs; | |
5892 | if (!i.mem_operands) | |
5893 | { | |
5894 | i.rm.mode = 3; | |
5895 | i.rm.regmem = i.op[1].regs->reg_num; | |
5896 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
5897 | i.rex |= REX_B; | |
5898 | } | |
5899 | } | |
29b0f896 AM |
5900 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
5901 | (if any) based on i.tm.extension_opcode. Again, we must be | |
5902 | careful to make sure that segment/control/debug/test/MMX | |
5903 | registers are coded into the i.rm.reg field. */ | |
f88c9eb0 | 5904 | else if (i.reg_operands) |
29b0f896 | 5905 | { |
99018f42 | 5906 | unsigned int op; |
7ab9ffdd L |
5907 | unsigned int vex_reg = ~0; |
5908 | ||
5909 | for (op = 0; op < i.operands; op++) | |
5910 | if (i.types[op].bitfield.reg8 | |
5911 | || i.types[op].bitfield.reg16 | |
5912 | || i.types[op].bitfield.reg32 | |
5913 | || i.types[op].bitfield.reg64 | |
5914 | || i.types[op].bitfield.regmmx | |
5915 | || i.types[op].bitfield.regxmm | |
5916 | || i.types[op].bitfield.regymm | |
5917 | || i.types[op].bitfield.sreg2 | |
5918 | || i.types[op].bitfield.sreg3 | |
5919 | || i.types[op].bitfield.control | |
5920 | || i.types[op].bitfield.debug | |
5921 | || i.types[op].bitfield.test) | |
5922 | break; | |
c0209578 | 5923 | |
7ab9ffdd L |
5924 | if (vex_3_sources) |
5925 | op = dest; | |
2426c15f | 5926 | else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd L |
5927 | { |
5928 | /* For instructions with VexNDS, the register-only | |
5929 | source operand is encoded in VEX prefix. */ | |
5930 | gas_assert (mem != (unsigned int) ~0); | |
c0f3af97 | 5931 | |
7ab9ffdd | 5932 | if (op > mem) |
c0f3af97 | 5933 | { |
7ab9ffdd L |
5934 | vex_reg = op++; |
5935 | gas_assert (op < i.operands); | |
c0f3af97 L |
5936 | } |
5937 | else | |
c0f3af97 | 5938 | { |
f12dc422 L |
5939 | /* Check register-only source operand when two source |
5940 | operands are swapped. */ | |
5941 | if (!i.tm.operand_types[op].bitfield.baseindex | |
5942 | && i.tm.operand_types[op + 1].bitfield.baseindex) | |
5943 | { | |
5944 | vex_reg = op; | |
5945 | op += 2; | |
5946 | gas_assert (mem == (vex_reg + 1) | |
5947 | && op < i.operands); | |
5948 | } | |
5949 | else | |
5950 | { | |
5951 | vex_reg = op + 1; | |
5952 | gas_assert (vex_reg < i.operands); | |
5953 | } | |
c0f3af97 | 5954 | } |
7ab9ffdd | 5955 | } |
2426c15f | 5956 | else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) |
7ab9ffdd | 5957 | { |
f12dc422 | 5958 | /* For instructions with VexNDD, the register destination |
7ab9ffdd | 5959 | is encoded in VEX prefix. */ |
f12dc422 L |
5960 | if (i.mem_operands == 0) |
5961 | { | |
5962 | /* There is no memory operand. */ | |
5963 | gas_assert ((op + 2) == i.operands); | |
5964 | vex_reg = op + 1; | |
5965 | } | |
5966 | else | |
8d63c93e | 5967 | { |
f12dc422 L |
5968 | /* There are only 2 operands. */ |
5969 | gas_assert (op < 2 && i.operands == 2); | |
5970 | vex_reg = 1; | |
5971 | } | |
7ab9ffdd L |
5972 | } |
5973 | else | |
5974 | gas_assert (op < i.operands); | |
99018f42 | 5975 | |
7ab9ffdd L |
5976 | if (vex_reg != (unsigned int) ~0) |
5977 | { | |
f12dc422 | 5978 | i386_operand_type *type = &i.tm.operand_types[vex_reg]; |
7ab9ffdd | 5979 | |
f12dc422 L |
5980 | if (type->bitfield.reg32 != 1 |
5981 | && type->bitfield.reg64 != 1 | |
5982 | && !operand_type_equal (type, ®xmm) | |
5983 | && !operand_type_equal (type, ®ymm)) | |
7ab9ffdd | 5984 | abort (); |
f88c9eb0 | 5985 | |
7ab9ffdd L |
5986 | i.vex.register_specifier = i.op[vex_reg].regs; |
5987 | } | |
5988 | ||
1b9f0c97 L |
5989 | /* Don't set OP operand twice. */ |
5990 | if (vex_reg != op) | |
7ab9ffdd | 5991 | { |
1b9f0c97 L |
5992 | /* If there is an extension opcode to put here, the |
5993 | register number must be put into the regmem field. */ | |
5994 | if (i.tm.extension_opcode != None) | |
5995 | { | |
5996 | i.rm.regmem = i.op[op].regs->reg_num; | |
5997 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
5998 | i.rex |= REX_B; | |
5999 | } | |
6000 | else | |
6001 | { | |
6002 | i.rm.reg = i.op[op].regs->reg_num; | |
6003 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
6004 | i.rex |= REX_R; | |
6005 | } | |
7ab9ffdd | 6006 | } |
252b5132 | 6007 | |
29b0f896 AM |
6008 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
6009 | must set it to 3 to indicate this is a register operand | |
6010 | in the regmem field. */ | |
6011 | if (!i.mem_operands) | |
6012 | i.rm.mode = 3; | |
6013 | } | |
252b5132 | 6014 | |
29b0f896 | 6015 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
c1e679ec | 6016 | if (i.tm.extension_opcode != None) |
29b0f896 AM |
6017 | i.rm.reg = i.tm.extension_opcode; |
6018 | } | |
6019 | return default_seg; | |
6020 | } | |
252b5132 | 6021 | |
29b0f896 | 6022 | static void |
e3bb37b5 | 6023 | output_branch (void) |
29b0f896 AM |
6024 | { |
6025 | char *p; | |
f8a5c266 | 6026 | int size; |
29b0f896 AM |
6027 | int code16; |
6028 | int prefix; | |
6029 | relax_substateT subtype; | |
6030 | symbolS *sym; | |
6031 | offsetT off; | |
6032 | ||
f8a5c266 | 6033 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
a501d77e | 6034 | size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL; |
29b0f896 AM |
6035 | |
6036 | prefix = 0; | |
6037 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 6038 | { |
29b0f896 AM |
6039 | prefix = 1; |
6040 | i.prefixes -= 1; | |
6041 | code16 ^= CODE16; | |
252b5132 | 6042 | } |
29b0f896 AM |
6043 | /* Pentium4 branch hints. */ |
6044 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
6045 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 6046 | { |
29b0f896 AM |
6047 | prefix++; |
6048 | i.prefixes--; | |
6049 | } | |
6050 | if (i.prefix[REX_PREFIX] != 0) | |
6051 | { | |
6052 | prefix++; | |
6053 | i.prefixes--; | |
2f66722d AM |
6054 | } |
6055 | ||
29b0f896 AM |
6056 | if (i.prefixes != 0 && !intel_syntax) |
6057 | as_warn (_("skipping prefixes on this instruction")); | |
6058 | ||
6059 | /* It's always a symbol; End frag & setup for relax. | |
6060 | Make sure there is enough room in this frag for the largest | |
6061 | instruction we may generate in md_convert_frag. This is 2 | |
6062 | bytes for the opcode and room for the prefix and largest | |
6063 | displacement. */ | |
6064 | frag_grow (prefix + 2 + 4); | |
6065 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
6066 | p = frag_more (prefix + 1); | |
6067 | if (i.prefix[DATA_PREFIX] != 0) | |
6068 | *p++ = DATA_PREFIX_OPCODE; | |
6069 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
6070 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
6071 | *p++ = i.prefix[SEG_PREFIX]; | |
6072 | if (i.prefix[REX_PREFIX] != 0) | |
6073 | *p++ = i.prefix[REX_PREFIX]; | |
6074 | *p = i.tm.base_opcode; | |
6075 | ||
6076 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
f8a5c266 | 6077 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
40fb9820 | 6078 | else if (cpu_arch_flags.bitfield.cpui386) |
f8a5c266 | 6079 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
29b0f896 | 6080 | else |
f8a5c266 | 6081 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
29b0f896 | 6082 | subtype |= code16; |
3e73aa7c | 6083 | |
29b0f896 AM |
6084 | sym = i.op[0].disps->X_add_symbol; |
6085 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 6086 | |
29b0f896 AM |
6087 | if (i.op[0].disps->X_op != O_constant |
6088 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 6089 | { |
29b0f896 AM |
6090 | /* Handle complex expressions. */ |
6091 | sym = make_expr_symbol (i.op[0].disps); | |
6092 | off = 0; | |
6093 | } | |
3e73aa7c | 6094 | |
29b0f896 AM |
6095 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
6096 | Pass reloc in fr_var. */ | |
6097 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); | |
6098 | } | |
3e73aa7c | 6099 | |
29b0f896 | 6100 | static void |
e3bb37b5 | 6101 | output_jump (void) |
29b0f896 AM |
6102 | { |
6103 | char *p; | |
6104 | int size; | |
3e02c1cc | 6105 | fixS *fixP; |
29b0f896 | 6106 | |
40fb9820 | 6107 | if (i.tm.opcode_modifier.jumpbyte) |
29b0f896 AM |
6108 | { |
6109 | /* This is a loop or jecxz type instruction. */ | |
6110 | size = 1; | |
6111 | if (i.prefix[ADDR_PREFIX] != 0) | |
6112 | { | |
6113 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
6114 | i.prefixes -= 1; | |
6115 | } | |
6116 | /* Pentium4 branch hints. */ | |
6117 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
6118 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
6119 | { | |
6120 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
6121 | i.prefixes--; | |
3e73aa7c JH |
6122 | } |
6123 | } | |
29b0f896 AM |
6124 | else |
6125 | { | |
6126 | int code16; | |
3e73aa7c | 6127 | |
29b0f896 AM |
6128 | code16 = 0; |
6129 | if (flag_code == CODE_16BIT) | |
6130 | code16 = CODE16; | |
3e73aa7c | 6131 | |
29b0f896 AM |
6132 | if (i.prefix[DATA_PREFIX] != 0) |
6133 | { | |
6134 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
6135 | i.prefixes -= 1; | |
6136 | code16 ^= CODE16; | |
6137 | } | |
252b5132 | 6138 | |
29b0f896 AM |
6139 | size = 4; |
6140 | if (code16) | |
6141 | size = 2; | |
6142 | } | |
9fcc94b6 | 6143 | |
29b0f896 AM |
6144 | if (i.prefix[REX_PREFIX] != 0) |
6145 | { | |
6146 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); | |
6147 | i.prefixes -= 1; | |
6148 | } | |
252b5132 | 6149 | |
29b0f896 AM |
6150 | if (i.prefixes != 0 && !intel_syntax) |
6151 | as_warn (_("skipping prefixes on this instruction")); | |
e0890092 | 6152 | |
42164a71 L |
6153 | p = frag_more (i.tm.opcode_length + size); |
6154 | switch (i.tm.opcode_length) | |
6155 | { | |
6156 | case 2: | |
6157 | *p++ = i.tm.base_opcode >> 8; | |
6158 | case 1: | |
6159 | *p++ = i.tm.base_opcode; | |
6160 | break; | |
6161 | default: | |
6162 | abort (); | |
6163 | } | |
e0890092 | 6164 | |
3e02c1cc AM |
6165 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
6166 | i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0])); | |
6167 | ||
6168 | /* All jumps handled here are signed, but don't use a signed limit | |
6169 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
6170 | 4G and 64k respectively. */ | |
6171 | if (size == 1) | |
6172 | fixP->fx_signed = 1; | |
29b0f896 | 6173 | } |
e0890092 | 6174 | |
29b0f896 | 6175 | static void |
e3bb37b5 | 6176 | output_interseg_jump (void) |
29b0f896 AM |
6177 | { |
6178 | char *p; | |
6179 | int size; | |
6180 | int prefix; | |
6181 | int code16; | |
252b5132 | 6182 | |
29b0f896 AM |
6183 | code16 = 0; |
6184 | if (flag_code == CODE_16BIT) | |
6185 | code16 = CODE16; | |
a217f122 | 6186 | |
29b0f896 AM |
6187 | prefix = 0; |
6188 | if (i.prefix[DATA_PREFIX] != 0) | |
6189 | { | |
6190 | prefix = 1; | |
6191 | i.prefixes -= 1; | |
6192 | code16 ^= CODE16; | |
6193 | } | |
6194 | if (i.prefix[REX_PREFIX] != 0) | |
6195 | { | |
6196 | prefix++; | |
6197 | i.prefixes -= 1; | |
6198 | } | |
252b5132 | 6199 | |
29b0f896 AM |
6200 | size = 4; |
6201 | if (code16) | |
6202 | size = 2; | |
252b5132 | 6203 | |
29b0f896 AM |
6204 | if (i.prefixes != 0 && !intel_syntax) |
6205 | as_warn (_("skipping prefixes on this instruction")); | |
252b5132 | 6206 | |
29b0f896 AM |
6207 | /* 1 opcode; 2 segment; offset */ |
6208 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 6209 | |
29b0f896 AM |
6210 | if (i.prefix[DATA_PREFIX] != 0) |
6211 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 6212 | |
29b0f896 AM |
6213 | if (i.prefix[REX_PREFIX] != 0) |
6214 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 6215 | |
29b0f896 AM |
6216 | *p++ = i.tm.base_opcode; |
6217 | if (i.op[1].imms->X_op == O_constant) | |
6218 | { | |
6219 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 6220 | |
29b0f896 AM |
6221 | if (size == 2 |
6222 | && !fits_in_unsigned_word (n) | |
6223 | && !fits_in_signed_word (n)) | |
6224 | { | |
6225 | as_bad (_("16-bit jump out of range")); | |
6226 | return; | |
6227 | } | |
6228 | md_number_to_chars (p, n, size); | |
6229 | } | |
6230 | else | |
6231 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
6232 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); | |
6233 | if (i.op[0].imms->X_op != O_constant) | |
6234 | as_bad (_("can't handle non absolute segment in `%s'"), | |
6235 | i.tm.name); | |
6236 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
6237 | } | |
a217f122 | 6238 | |
29b0f896 | 6239 | static void |
e3bb37b5 | 6240 | output_insn (void) |
29b0f896 | 6241 | { |
2bbd9c25 JJ |
6242 | fragS *insn_start_frag; |
6243 | offsetT insn_start_off; | |
6244 | ||
29b0f896 AM |
6245 | /* Tie dwarf2 debug info to the address at the start of the insn. |
6246 | We can't do this after the insn has been output as the current | |
6247 | frag may have been closed off. eg. by frag_var. */ | |
6248 | dwarf2_emit_insn (0); | |
6249 | ||
2bbd9c25 JJ |
6250 | insn_start_frag = frag_now; |
6251 | insn_start_off = frag_now_fix (); | |
6252 | ||
29b0f896 | 6253 | /* Output jumps. */ |
40fb9820 | 6254 | if (i.tm.opcode_modifier.jump) |
29b0f896 | 6255 | output_branch (); |
40fb9820 L |
6256 | else if (i.tm.opcode_modifier.jumpbyte |
6257 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 | 6258 | output_jump (); |
40fb9820 | 6259 | else if (i.tm.opcode_modifier.jumpintersegment) |
29b0f896 AM |
6260 | output_interseg_jump (); |
6261 | else | |
6262 | { | |
6263 | /* Output normal instructions here. */ | |
6264 | char *p; | |
6265 | unsigned char *q; | |
47465058 | 6266 | unsigned int j; |
331d2d0d | 6267 | unsigned int prefix; |
4dffcebc | 6268 | |
c0f3af97 | 6269 | /* Since the VEX prefix contains the implicit prefix, we don't |
89e71f5c | 6270 | need the explicit prefix. */ |
c0f3af97 | 6271 | if (!i.tm.opcode_modifier.vex) |
bc4bd9ab | 6272 | { |
c0f3af97 | 6273 | switch (i.tm.opcode_length) |
bc4bd9ab | 6274 | { |
c0f3af97 L |
6275 | case 3: |
6276 | if (i.tm.base_opcode & 0xff000000) | |
4dffcebc | 6277 | { |
c0f3af97 L |
6278 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
6279 | goto check_prefix; | |
6280 | } | |
6281 | break; | |
6282 | case 2: | |
6283 | if ((i.tm.base_opcode & 0xff0000) != 0) | |
6284 | { | |
6285 | prefix = (i.tm.base_opcode >> 16) & 0xff; | |
6286 | if (i.tm.cpu_flags.bitfield.cpupadlock) | |
6287 | { | |
4dffcebc | 6288 | check_prefix: |
c0f3af97 | 6289 | if (prefix != REPE_PREFIX_OPCODE |
c32fa91d | 6290 | || (i.prefix[REP_PREFIX] |
c0f3af97 L |
6291 | != REPE_PREFIX_OPCODE)) |
6292 | add_prefix (prefix); | |
6293 | } | |
6294 | else | |
4dffcebc L |
6295 | add_prefix (prefix); |
6296 | } | |
c0f3af97 L |
6297 | break; |
6298 | case 1: | |
6299 | break; | |
6300 | default: | |
6301 | abort (); | |
bc4bd9ab | 6302 | } |
c0f3af97 L |
6303 | |
6304 | /* The prefix bytes. */ | |
6305 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
6306 | if (*q) | |
6307 | FRAG_APPEND_1_CHAR (*q); | |
0f10071e | 6308 | } |
ae5c1c7b | 6309 | else |
c0f3af97 L |
6310 | { |
6311 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
6312 | if (*q) | |
6313 | switch (j) | |
6314 | { | |
6315 | case REX_PREFIX: | |
6316 | /* REX byte is encoded in VEX prefix. */ | |
6317 | break; | |
6318 | case SEG_PREFIX: | |
6319 | case ADDR_PREFIX: | |
6320 | FRAG_APPEND_1_CHAR (*q); | |
6321 | break; | |
6322 | default: | |
6323 | /* There should be no other prefixes for instructions | |
6324 | with VEX prefix. */ | |
6325 | abort (); | |
6326 | } | |
6327 | ||
6328 | /* Now the VEX prefix. */ | |
6329 | p = frag_more (i.vex.length); | |
6330 | for (j = 0; j < i.vex.length; j++) | |
6331 | p[j] = i.vex.bytes[j]; | |
6332 | } | |
252b5132 | 6333 | |
29b0f896 | 6334 | /* Now the opcode; be careful about word order here! */ |
4dffcebc | 6335 | if (i.tm.opcode_length == 1) |
29b0f896 AM |
6336 | { |
6337 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
6338 | } | |
6339 | else | |
6340 | { | |
4dffcebc | 6341 | switch (i.tm.opcode_length) |
331d2d0d | 6342 | { |
4dffcebc | 6343 | case 3: |
331d2d0d L |
6344 | p = frag_more (3); |
6345 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
4dffcebc L |
6346 | break; |
6347 | case 2: | |
6348 | p = frag_more (2); | |
6349 | break; | |
6350 | default: | |
6351 | abort (); | |
6352 | break; | |
331d2d0d | 6353 | } |
0f10071e | 6354 | |
29b0f896 AM |
6355 | /* Put out high byte first: can't use md_number_to_chars! */ |
6356 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
6357 | *p = i.tm.base_opcode & 0xff; | |
6358 | } | |
3e73aa7c | 6359 | |
29b0f896 | 6360 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 6361 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 6362 | { |
4a3523fa L |
6363 | FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 |
6364 | | i.rm.reg << 3 | |
6365 | | i.rm.mode << 6)); | |
29b0f896 AM |
6366 | /* If i.rm.regmem == ESP (4) |
6367 | && i.rm.mode != (Register mode) | |
6368 | && not 16 bit | |
6369 | ==> need second modrm byte. */ | |
6370 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
6371 | && i.rm.mode != 3 | |
40fb9820 | 6372 | && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16)) |
4a3523fa L |
6373 | FRAG_APPEND_1_CHAR ((i.sib.base << 0 |
6374 | | i.sib.index << 3 | |
6375 | | i.sib.scale << 6)); | |
29b0f896 | 6376 | } |
3e73aa7c | 6377 | |
29b0f896 | 6378 | if (i.disp_operands) |
2bbd9c25 | 6379 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 6380 | |
29b0f896 | 6381 | if (i.imm_operands) |
2bbd9c25 | 6382 | output_imm (insn_start_frag, insn_start_off); |
29b0f896 | 6383 | } |
252b5132 | 6384 | |
29b0f896 AM |
6385 | #ifdef DEBUG386 |
6386 | if (flag_debug) | |
6387 | { | |
7b81dfbb | 6388 | pi ("" /*line*/, &i); |
29b0f896 AM |
6389 | } |
6390 | #endif /* DEBUG386 */ | |
6391 | } | |
252b5132 | 6392 | |
e205caa7 L |
6393 | /* Return the size of the displacement operand N. */ |
6394 | ||
6395 | static int | |
6396 | disp_size (unsigned int n) | |
6397 | { | |
6398 | int size = 4; | |
40fb9820 L |
6399 | if (i.types[n].bitfield.disp64) |
6400 | size = 8; | |
6401 | else if (i.types[n].bitfield.disp8) | |
6402 | size = 1; | |
6403 | else if (i.types[n].bitfield.disp16) | |
6404 | size = 2; | |
e205caa7 L |
6405 | return size; |
6406 | } | |
6407 | ||
6408 | /* Return the size of the immediate operand N. */ | |
6409 | ||
6410 | static int | |
6411 | imm_size (unsigned int n) | |
6412 | { | |
6413 | int size = 4; | |
40fb9820 L |
6414 | if (i.types[n].bitfield.imm64) |
6415 | size = 8; | |
6416 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
6417 | size = 1; | |
6418 | else if (i.types[n].bitfield.imm16) | |
6419 | size = 2; | |
e205caa7 L |
6420 | return size; |
6421 | } | |
6422 | ||
29b0f896 | 6423 | static void |
64e74474 | 6424 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
6425 | { |
6426 | char *p; | |
6427 | unsigned int n; | |
252b5132 | 6428 | |
29b0f896 AM |
6429 | for (n = 0; n < i.operands; n++) |
6430 | { | |
40fb9820 | 6431 | if (operand_type_check (i.types[n], disp)) |
29b0f896 AM |
6432 | { |
6433 | if (i.op[n].disps->X_op == O_constant) | |
6434 | { | |
e205caa7 | 6435 | int size = disp_size (n); |
29b0f896 | 6436 | offsetT val; |
252b5132 | 6437 | |
29b0f896 AM |
6438 | val = offset_in_range (i.op[n].disps->X_add_number, |
6439 | size); | |
6440 | p = frag_more (size); | |
6441 | md_number_to_chars (p, val, size); | |
6442 | } | |
6443 | else | |
6444 | { | |
f86103b7 | 6445 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 6446 | int size = disp_size (n); |
40fb9820 | 6447 | int sign = i.types[n].bitfield.disp32s; |
29b0f896 AM |
6448 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
6449 | ||
e205caa7 | 6450 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 6451 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 6452 | |
29b0f896 AM |
6453 | /* The PC relative address is computed relative |
6454 | to the instruction boundary, so in case immediate | |
6455 | fields follows, we need to adjust the value. */ | |
6456 | if (pcrel && i.imm_operands) | |
6457 | { | |
29b0f896 | 6458 | unsigned int n1; |
e205caa7 | 6459 | int sz = 0; |
252b5132 | 6460 | |
29b0f896 | 6461 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 6462 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 6463 | { |
e205caa7 L |
6464 | /* Only one immediate is allowed for PC |
6465 | relative address. */ | |
9c2799c2 | 6466 | gas_assert (sz == 0); |
e205caa7 L |
6467 | sz = imm_size (n1); |
6468 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 6469 | } |
29b0f896 | 6470 | /* We should find the immediate. */ |
9c2799c2 | 6471 | gas_assert (sz != 0); |
29b0f896 | 6472 | } |
520dc8e8 | 6473 | |
29b0f896 | 6474 | p = frag_more (size); |
2bbd9c25 | 6475 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 6476 | if (GOT_symbol |
2bbd9c25 | 6477 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 6478 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
6479 | || reloc_type == BFD_RELOC_X86_64_32S |
6480 | || (reloc_type == BFD_RELOC_64 | |
6481 | && object_64bit)) | |
d6ab8113 JB |
6482 | && (i.op[n].disps->X_op == O_symbol |
6483 | || (i.op[n].disps->X_op == O_add | |
6484 | && ((symbol_get_value_expression | |
6485 | (i.op[n].disps->X_op_symbol)->X_op) | |
6486 | == O_subtract)))) | |
6487 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 JJ |
6488 | { |
6489 | offsetT add; | |
6490 | ||
6491 | if (insn_start_frag == frag_now) | |
6492 | add = (p - frag_now->fr_literal) - insn_start_off; | |
6493 | else | |
6494 | { | |
6495 | fragS *fr; | |
6496 | ||
6497 | add = insn_start_frag->fr_fix - insn_start_off; | |
6498 | for (fr = insn_start_frag->fr_next; | |
6499 | fr && fr != frag_now; fr = fr->fr_next) | |
6500 | add += fr->fr_fix; | |
6501 | add += p - frag_now->fr_literal; | |
6502 | } | |
6503 | ||
4fa24527 | 6504 | if (!object_64bit) |
7b81dfbb AJ |
6505 | { |
6506 | reloc_type = BFD_RELOC_386_GOTPC; | |
6507 | i.op[n].imms->X_add_number += add; | |
6508 | } | |
6509 | else if (reloc_type == BFD_RELOC_64) | |
6510 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 6511 | else |
7b81dfbb AJ |
6512 | /* Don't do the adjustment for x86-64, as there |
6513 | the pcrel addressing is relative to the _next_ | |
6514 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 6515 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 6516 | } |
062cd5e7 | 6517 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
2bbd9c25 | 6518 | i.op[n].disps, pcrel, reloc_type); |
29b0f896 AM |
6519 | } |
6520 | } | |
6521 | } | |
6522 | } | |
252b5132 | 6523 | |
29b0f896 | 6524 | static void |
64e74474 | 6525 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
6526 | { |
6527 | char *p; | |
6528 | unsigned int n; | |
252b5132 | 6529 | |
29b0f896 AM |
6530 | for (n = 0; n < i.operands; n++) |
6531 | { | |
40fb9820 | 6532 | if (operand_type_check (i.types[n], imm)) |
29b0f896 AM |
6533 | { |
6534 | if (i.op[n].imms->X_op == O_constant) | |
6535 | { | |
e205caa7 | 6536 | int size = imm_size (n); |
29b0f896 | 6537 | offsetT val; |
b4cac588 | 6538 | |
29b0f896 AM |
6539 | val = offset_in_range (i.op[n].imms->X_add_number, |
6540 | size); | |
6541 | p = frag_more (size); | |
6542 | md_number_to_chars (p, val, size); | |
6543 | } | |
6544 | else | |
6545 | { | |
6546 | /* Not absolute_section. | |
6547 | Need a 32-bit fixup (don't support 8bit | |
6548 | non-absolute imms). Try to support other | |
6549 | sizes ... */ | |
f86103b7 | 6550 | enum bfd_reloc_code_real reloc_type; |
e205caa7 L |
6551 | int size = imm_size (n); |
6552 | int sign; | |
29b0f896 | 6553 | |
40fb9820 | 6554 | if (i.types[n].bitfield.imm32s |
a7d61044 | 6555 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 6556 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 6557 | sign = 1; |
e205caa7 L |
6558 | else |
6559 | sign = 0; | |
520dc8e8 | 6560 | |
29b0f896 AM |
6561 | p = frag_more (size); |
6562 | reloc_type = reloc (size, 0, sign, i.reloc[n]); | |
f86103b7 | 6563 | |
2bbd9c25 JJ |
6564 | /* This is tough to explain. We end up with this one if we |
6565 | * have operands that look like | |
6566 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
6567 | * obtain the absolute address of the GOT, and it is strongly | |
6568 | * preferable from a performance point of view to avoid using | |
6569 | * a runtime relocation for this. The actual sequence of | |
6570 | * instructions often look something like: | |
6571 | * | |
6572 | * call .L66 | |
6573 | * .L66: | |
6574 | * popl %ebx | |
6575 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
6576 | * | |
6577 | * The call and pop essentially return the absolute address | |
6578 | * of the label .L66 and store it in %ebx. The linker itself | |
6579 | * will ultimately change the first operand of the addl so | |
6580 | * that %ebx points to the GOT, but to keep things simple, the | |
6581 | * .o file must have this operand set so that it generates not | |
6582 | * the absolute address of .L66, but the absolute address of | |
6583 | * itself. This allows the linker itself simply treat a GOTPC | |
6584 | * relocation as asking for a pcrel offset to the GOT to be | |
6585 | * added in, and the addend of the relocation is stored in the | |
6586 | * operand field for the instruction itself. | |
6587 | * | |
6588 | * Our job here is to fix the operand so that it would add | |
6589 | * the correct offset so that %ebx would point to itself. The | |
6590 | * thing that is tricky is that .-.L66 will point to the | |
6591 | * beginning of the instruction, so we need to further modify | |
6592 | * the operand so that it will point to itself. There are | |
6593 | * other cases where you have something like: | |
6594 | * | |
6595 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
6596 | * | |
6597 | * and here no correction would be required. Internally in | |
6598 | * the assembler we treat operands of this form as not being | |
6599 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
6600 | * whether it would simplify matters to do it this way. Who | |
6601 | * knows. In earlier versions of the PIC patches, the | |
6602 | * pcrel_adjust field was used to store the correction, but | |
6603 | * since the expression is not pcrel, I felt it would be | |
6604 | * confusing to do it this way. */ | |
6605 | ||
d6ab8113 | 6606 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
6607 | || reloc_type == BFD_RELOC_X86_64_32S |
6608 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
6609 | && GOT_symbol |
6610 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
6611 | && (i.op[n].imms->X_op == O_symbol | |
6612 | || (i.op[n].imms->X_op == O_add | |
6613 | && ((symbol_get_value_expression | |
6614 | (i.op[n].imms->X_op_symbol)->X_op) | |
6615 | == O_subtract)))) | |
6616 | { | |
2bbd9c25 JJ |
6617 | offsetT add; |
6618 | ||
6619 | if (insn_start_frag == frag_now) | |
6620 | add = (p - frag_now->fr_literal) - insn_start_off; | |
6621 | else | |
6622 | { | |
6623 | fragS *fr; | |
6624 | ||
6625 | add = insn_start_frag->fr_fix - insn_start_off; | |
6626 | for (fr = insn_start_frag->fr_next; | |
6627 | fr && fr != frag_now; fr = fr->fr_next) | |
6628 | add += fr->fr_fix; | |
6629 | add += p - frag_now->fr_literal; | |
6630 | } | |
6631 | ||
4fa24527 | 6632 | if (!object_64bit) |
d6ab8113 | 6633 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 6634 | else if (size == 4) |
d6ab8113 | 6635 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
6636 | else if (size == 8) |
6637 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
2bbd9c25 | 6638 | i.op[n].imms->X_add_number += add; |
29b0f896 | 6639 | } |
29b0f896 AM |
6640 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
6641 | i.op[n].imms, 0, reloc_type); | |
6642 | } | |
6643 | } | |
6644 | } | |
252b5132 RH |
6645 | } |
6646 | \f | |
d182319b JB |
6647 | /* x86_cons_fix_new is called via the expression parsing code when a |
6648 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
6649 | static enum bfd_reloc_code_real got_reloc = NO_RELOC; | |
6650 | static int cons_sign = -1; | |
6651 | ||
6652 | void | |
e3bb37b5 | 6653 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
64e74474 | 6654 | expressionS *exp) |
d182319b JB |
6655 | { |
6656 | enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc); | |
6657 | ||
6658 | got_reloc = NO_RELOC; | |
6659 | ||
6660 | #ifdef TE_PE | |
6661 | if (exp->X_op == O_secrel) | |
6662 | { | |
6663 | exp->X_op = O_symbol; | |
6664 | r = BFD_RELOC_32_SECREL; | |
6665 | } | |
6666 | #endif | |
6667 | ||
6668 | fix_new_exp (frag, off, len, exp, 0, r); | |
6669 | } | |
6670 | ||
357d1bd8 L |
6671 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
6672 | purpose of the `.dc.a' internal pseudo-op. */ | |
6673 | ||
6674 | int | |
6675 | x86_address_bytes (void) | |
6676 | { | |
6677 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) | |
6678 | return 4; | |
6679 | return stdoutput->arch_info->bits_per_address / 8; | |
6680 | } | |
6681 | ||
d382c579 TG |
6682 | #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
6683 | || defined (LEX_AT) | |
718ddfc0 JB |
6684 | # define lex_got(reloc, adjust, types) NULL |
6685 | #else | |
f3c180ae AM |
6686 | /* Parse operands of the form |
6687 | <symbol>@GOTOFF+<nnn> | |
6688 | and similar .plt or .got references. | |
6689 | ||
6690 | If we find one, set up the correct relocation in RELOC and copy the | |
6691 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
6692 | parsing by the calling routine. Return this buffer, and if ADJUST | |
6693 | is non-null set it to the length of the string we removed from the | |
6694 | input line. Otherwise return NULL. */ | |
6695 | static char * | |
91d6fa6a | 6696 | lex_got (enum bfd_reloc_code_real *rel, |
64e74474 | 6697 | int *adjust, |
40fb9820 | 6698 | i386_operand_type *types) |
f3c180ae | 6699 | { |
7b81dfbb AJ |
6700 | /* Some of the relocations depend on the size of what field is to |
6701 | be relocated. But in our callers i386_immediate and i386_displacement | |
6702 | we don't yet know the operand size (this will be set by insn | |
6703 | matching). Hence we record the word32 relocation here, | |
6704 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
6705 | static const struct { |
6706 | const char *str; | |
cff8d58a | 6707 | int len; |
4fa24527 | 6708 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 6709 | const i386_operand_type types64; |
f3c180ae | 6710 | } gotrel[] = { |
cff8d58a L |
6711 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
6712 | BFD_RELOC_X86_64_PLTOFF64 }, | |
40fb9820 | 6713 | OPERAND_TYPE_IMM64 }, |
cff8d58a L |
6714 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
6715 | BFD_RELOC_X86_64_PLT32 }, | |
40fb9820 | 6716 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
6717 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
6718 | BFD_RELOC_X86_64_GOTPLT64 }, | |
40fb9820 | 6719 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
6720 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
6721 | BFD_RELOC_X86_64_GOTOFF64 }, | |
40fb9820 | 6722 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
6723 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
6724 | BFD_RELOC_X86_64_GOTPCREL }, | |
40fb9820 | 6725 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
6726 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
6727 | BFD_RELOC_X86_64_TLSGD }, | |
40fb9820 | 6728 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
6729 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
6730 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 6731 | OPERAND_TYPE_NONE }, |
cff8d58a L |
6732 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
6733 | BFD_RELOC_X86_64_TLSLD }, | |
40fb9820 | 6734 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
6735 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
6736 | BFD_RELOC_X86_64_GOTTPOFF }, | |
40fb9820 | 6737 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
6738 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
6739 | BFD_RELOC_X86_64_TPOFF32 }, | |
40fb9820 | 6740 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
6741 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
6742 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 6743 | OPERAND_TYPE_NONE }, |
cff8d58a L |
6744 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
6745 | BFD_RELOC_X86_64_DTPOFF32 }, | |
40fb9820 | 6746 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
6747 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
6748 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 6749 | OPERAND_TYPE_NONE }, |
cff8d58a L |
6750 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
6751 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 6752 | OPERAND_TYPE_NONE }, |
cff8d58a L |
6753 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
6754 | BFD_RELOC_X86_64_GOT32 }, | |
40fb9820 | 6755 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
cff8d58a L |
6756 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
6757 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
40fb9820 | 6758 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
6759 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
6760 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
40fb9820 | 6761 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
f3c180ae AM |
6762 | }; |
6763 | char *cp; | |
6764 | unsigned int j; | |
6765 | ||
d382c579 | 6766 | #if defined (OBJ_MAYBE_ELF) |
718ddfc0 JB |
6767 | if (!IS_ELF) |
6768 | return NULL; | |
d382c579 | 6769 | #endif |
718ddfc0 | 6770 | |
f3c180ae | 6771 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 6772 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
6773 | return NULL; |
6774 | ||
47465058 | 6775 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae | 6776 | { |
cff8d58a | 6777 | int len = gotrel[j].len; |
28f81592 | 6778 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 6779 | { |
4fa24527 | 6780 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 6781 | { |
28f81592 AM |
6782 | int first, second; |
6783 | char *tmpbuf, *past_reloc; | |
f3c180ae | 6784 | |
91d6fa6a | 6785 | *rel = gotrel[j].rel[object_64bit]; |
28f81592 AM |
6786 | if (adjust) |
6787 | *adjust = len; | |
f3c180ae | 6788 | |
3956db08 JB |
6789 | if (types) |
6790 | { | |
6791 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
6792 | { |
6793 | types->bitfield.imm32 = 1; | |
6794 | types->bitfield.disp32 = 1; | |
6795 | } | |
3956db08 JB |
6796 | else |
6797 | *types = gotrel[j].types64; | |
6798 | } | |
6799 | ||
f3c180ae AM |
6800 | if (GOT_symbol == NULL) |
6801 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
6802 | ||
28f81592 | 6803 | /* The length of the first part of our input line. */ |
f3c180ae | 6804 | first = cp - input_line_pointer; |
28f81592 AM |
6805 | |
6806 | /* The second part goes from after the reloc token until | |
67c11a9b | 6807 | (and including) an end_of_line char or comma. */ |
28f81592 | 6808 | past_reloc = cp + 1 + len; |
67c11a9b AM |
6809 | cp = past_reloc; |
6810 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
6811 | ++cp; | |
6812 | second = cp + 1 - past_reloc; | |
28f81592 AM |
6813 | |
6814 | /* Allocate and copy string. The trailing NUL shouldn't | |
6815 | be necessary, but be safe. */ | |
1e9cc1c2 | 6816 | tmpbuf = (char *) xmalloc (first + second + 2); |
f3c180ae | 6817 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
6818 | if (second != 0 && *past_reloc != ' ') |
6819 | /* Replace the relocation token with ' ', so that | |
6820 | errors like foo@GOTOFF1 will be detected. */ | |
6821 | tmpbuf[first++] = ' '; | |
6822 | memcpy (tmpbuf + first, past_reloc, second); | |
6823 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
6824 | return tmpbuf; |
6825 | } | |
6826 | ||
4fa24527 JB |
6827 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
6828 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
6829 | return NULL; |
6830 | } | |
6831 | } | |
6832 | ||
6833 | /* Might be a symbol version string. Don't as_bad here. */ | |
6834 | return NULL; | |
6835 | } | |
4e4f7c87 | 6836 | #endif |
f3c180ae | 6837 | |
a988325c NC |
6838 | #ifdef TE_PE |
6839 | #ifdef lex_got | |
6840 | #undef lex_got | |
6841 | #endif | |
6842 | /* Parse operands of the form | |
6843 | <symbol>@SECREL32+<nnn> | |
6844 | ||
6845 | If we find one, set up the correct relocation in RELOC and copy the | |
6846 | input string, minus the `@SECREL32' into a malloc'd buffer for | |
6847 | parsing by the calling routine. Return this buffer, and if ADJUST | |
6848 | is non-null set it to the length of the string we removed from the | |
6849 | input line. Otherwise return NULL. | |
6850 | ||
6851 | This function is copied from the ELF version above adjusted for PE targets. */ | |
6852 | ||
6853 | static char * | |
6854 | lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED, | |
6855 | int *adjust ATTRIBUTE_UNUSED, | |
6856 | i386_operand_type *types ATTRIBUTE_UNUSED) | |
6857 | { | |
6858 | static const struct | |
6859 | { | |
6860 | const char *str; | |
6861 | int len; | |
6862 | const enum bfd_reloc_code_real rel[2]; | |
6863 | const i386_operand_type types64; | |
6864 | } | |
6865 | gotrel[] = | |
6866 | { | |
6867 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, | |
6868 | BFD_RELOC_32_SECREL }, | |
6869 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, | |
6870 | }; | |
6871 | ||
6872 | char *cp; | |
6873 | unsigned j; | |
6874 | ||
6875 | for (cp = input_line_pointer; *cp != '@'; cp++) | |
6876 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') | |
6877 | return NULL; | |
6878 | ||
6879 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) | |
6880 | { | |
6881 | int len = gotrel[j].len; | |
6882 | ||
6883 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) | |
6884 | { | |
6885 | if (gotrel[j].rel[object_64bit] != 0) | |
6886 | { | |
6887 | int first, second; | |
6888 | char *tmpbuf, *past_reloc; | |
6889 | ||
6890 | *rel = gotrel[j].rel[object_64bit]; | |
6891 | if (adjust) | |
6892 | *adjust = len; | |
6893 | ||
6894 | if (types) | |
6895 | { | |
6896 | if (flag_code != CODE_64BIT) | |
6897 | { | |
6898 | types->bitfield.imm32 = 1; | |
6899 | types->bitfield.disp32 = 1; | |
6900 | } | |
6901 | else | |
6902 | *types = gotrel[j].types64; | |
6903 | } | |
6904 | ||
6905 | /* The length of the first part of our input line. */ | |
6906 | first = cp - input_line_pointer; | |
6907 | ||
6908 | /* The second part goes from after the reloc token until | |
6909 | (and including) an end_of_line char or comma. */ | |
6910 | past_reloc = cp + 1 + len; | |
6911 | cp = past_reloc; | |
6912 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
6913 | ++cp; | |
6914 | second = cp + 1 - past_reloc; | |
6915 | ||
6916 | /* Allocate and copy string. The trailing NUL shouldn't | |
6917 | be necessary, but be safe. */ | |
6918 | tmpbuf = (char *) xmalloc (first + second + 2); | |
6919 | memcpy (tmpbuf, input_line_pointer, first); | |
6920 | if (second != 0 && *past_reloc != ' ') | |
6921 | /* Replace the relocation token with ' ', so that | |
6922 | errors like foo@SECLREL321 will be detected. */ | |
6923 | tmpbuf[first++] = ' '; | |
6924 | memcpy (tmpbuf + first, past_reloc, second); | |
6925 | tmpbuf[first + second] = '\0'; | |
6926 | return tmpbuf; | |
6927 | } | |
6928 | ||
6929 | as_bad (_("@%s reloc is not supported with %d-bit output format"), | |
6930 | gotrel[j].str, 1 << (5 + object_64bit)); | |
6931 | return NULL; | |
6932 | } | |
6933 | } | |
6934 | ||
6935 | /* Might be a symbol version string. Don't as_bad here. */ | |
6936 | return NULL; | |
6937 | } | |
6938 | ||
6939 | #endif /* TE_PE */ | |
6940 | ||
f3c180ae | 6941 | void |
e3bb37b5 | 6942 | x86_cons (expressionS *exp, int size) |
f3c180ae | 6943 | { |
ee86248c JB |
6944 | intel_syntax = -intel_syntax; |
6945 | ||
3c7b9c2c | 6946 | exp->X_md = 0; |
4fa24527 | 6947 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
6948 | { |
6949 | /* Handle @GOTOFF and the like in an expression. */ | |
6950 | char *save; | |
6951 | char *gotfree_input_line; | |
4a57f2cf | 6952 | int adjust = 0; |
f3c180ae AM |
6953 | |
6954 | save = input_line_pointer; | |
3956db08 | 6955 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
6956 | if (gotfree_input_line) |
6957 | input_line_pointer = gotfree_input_line; | |
6958 | ||
6959 | expression (exp); | |
6960 | ||
6961 | if (gotfree_input_line) | |
6962 | { | |
6963 | /* expression () has merrily parsed up to the end of line, | |
6964 | or a comma - in the wrong buffer. Transfer how far | |
6965 | input_line_pointer has moved to the right buffer. */ | |
6966 | input_line_pointer = (save | |
6967 | + (input_line_pointer - gotfree_input_line) | |
6968 | + adjust); | |
6969 | free (gotfree_input_line); | |
3992d3b7 AM |
6970 | if (exp->X_op == O_constant |
6971 | || exp->X_op == O_absent | |
6972 | || exp->X_op == O_illegal | |
0398aac5 | 6973 | || exp->X_op == O_register |
3992d3b7 AM |
6974 | || exp->X_op == O_big) |
6975 | { | |
6976 | char c = *input_line_pointer; | |
6977 | *input_line_pointer = 0; | |
6978 | as_bad (_("missing or invalid expression `%s'"), save); | |
6979 | *input_line_pointer = c; | |
6980 | } | |
f3c180ae AM |
6981 | } |
6982 | } | |
6983 | else | |
6984 | expression (exp); | |
ee86248c JB |
6985 | |
6986 | intel_syntax = -intel_syntax; | |
6987 | ||
6988 | if (intel_syntax) | |
6989 | i386_intel_simplify (exp); | |
f3c180ae | 6990 | } |
f3c180ae | 6991 | |
9f32dd5b L |
6992 | static void |
6993 | signed_cons (int size) | |
6482c264 | 6994 | { |
d182319b JB |
6995 | if (flag_code == CODE_64BIT) |
6996 | cons_sign = 1; | |
6997 | cons (size); | |
6998 | cons_sign = -1; | |
6482c264 NC |
6999 | } |
7000 | ||
d182319b | 7001 | #ifdef TE_PE |
6482c264 | 7002 | static void |
7016a5d5 | 7003 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
6482c264 NC |
7004 | { |
7005 | expressionS exp; | |
7006 | ||
7007 | do | |
7008 | { | |
7009 | expression (&exp); | |
7010 | if (exp.X_op == O_symbol) | |
7011 | exp.X_op = O_secrel; | |
7012 | ||
7013 | emit_expr (&exp, 4); | |
7014 | } | |
7015 | while (*input_line_pointer++ == ','); | |
7016 | ||
7017 | input_line_pointer--; | |
7018 | demand_empty_rest_of_line (); | |
7019 | } | |
6482c264 NC |
7020 | #endif |
7021 | ||
252b5132 | 7022 | static int |
70e41ade | 7023 | i386_immediate (char *imm_start) |
252b5132 RH |
7024 | { |
7025 | char *save_input_line_pointer; | |
f3c180ae | 7026 | char *gotfree_input_line; |
252b5132 | 7027 | segT exp_seg = 0; |
47926f60 | 7028 | expressionS *exp; |
40fb9820 L |
7029 | i386_operand_type types; |
7030 | ||
0dfbf9d7 | 7031 | operand_type_set (&types, ~0); |
252b5132 RH |
7032 | |
7033 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
7034 | { | |
31b2323c L |
7035 | as_bad (_("at most %d immediate operands are allowed"), |
7036 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
7037 | return 0; |
7038 | } | |
7039 | ||
7040 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 7041 | i.op[this_operand].imms = exp; |
252b5132 RH |
7042 | |
7043 | if (is_space_char (*imm_start)) | |
7044 | ++imm_start; | |
7045 | ||
7046 | save_input_line_pointer = input_line_pointer; | |
7047 | input_line_pointer = imm_start; | |
7048 | ||
3956db08 | 7049 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
7050 | if (gotfree_input_line) |
7051 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
7052 | |
7053 | exp_seg = expression (exp); | |
7054 | ||
83183c0c | 7055 | SKIP_WHITESPACE (); |
252b5132 | 7056 | if (*input_line_pointer) |
f3c180ae | 7057 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
7058 | |
7059 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 7060 | if (gotfree_input_line) |
ee86248c JB |
7061 | { |
7062 | free (gotfree_input_line); | |
7063 | ||
7064 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
7065 | exp->X_op = O_illegal; | |
7066 | } | |
7067 | ||
7068 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); | |
7069 | } | |
252b5132 | 7070 | |
ee86248c JB |
7071 | static int |
7072 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
7073 | i386_operand_type types, const char *imm_start) | |
7074 | { | |
7075 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 7076 | { |
313c53d1 L |
7077 | if (imm_start) |
7078 | as_bad (_("missing or invalid immediate expression `%s'"), | |
7079 | imm_start); | |
3992d3b7 | 7080 | return 0; |
252b5132 | 7081 | } |
3e73aa7c | 7082 | else if (exp->X_op == O_constant) |
252b5132 | 7083 | { |
47926f60 | 7084 | /* Size it properly later. */ |
40fb9820 | 7085 | i.types[this_operand].bitfield.imm64 = 1; |
13f864ae L |
7086 | /* If not 64bit, sign extend val. */ |
7087 | if (flag_code != CODE_64BIT | |
4eed87de AM |
7088 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) |
7089 | exp->X_add_number | |
7090 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 7091 | } |
4c63da97 | 7092 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 7093 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 7094 | && exp_seg != absolute_section |
47926f60 | 7095 | && exp_seg != text_section |
24eab124 AM |
7096 | && exp_seg != data_section |
7097 | && exp_seg != bss_section | |
7098 | && exp_seg != undefined_section | |
f86103b7 | 7099 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 7100 | { |
d0b47220 | 7101 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
7102 | return 0; |
7103 | } | |
7104 | #endif | |
bb8f5920 L |
7105 | else if (!intel_syntax && exp->X_op == O_register) |
7106 | { | |
313c53d1 L |
7107 | if (imm_start) |
7108 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
bb8f5920 L |
7109 | return 0; |
7110 | } | |
252b5132 RH |
7111 | else |
7112 | { | |
7113 | /* This is an address. The size of the address will be | |
24eab124 | 7114 | determined later, depending on destination register, |
3e73aa7c | 7115 | suffix, or the default for the section. */ |
40fb9820 L |
7116 | i.types[this_operand].bitfield.imm8 = 1; |
7117 | i.types[this_operand].bitfield.imm16 = 1; | |
7118 | i.types[this_operand].bitfield.imm32 = 1; | |
7119 | i.types[this_operand].bitfield.imm32s = 1; | |
7120 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
7121 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
7122 | types); | |
252b5132 RH |
7123 | } |
7124 | ||
7125 | return 1; | |
7126 | } | |
7127 | ||
551c1ca1 | 7128 | static char * |
e3bb37b5 | 7129 | i386_scale (char *scale) |
252b5132 | 7130 | { |
551c1ca1 AM |
7131 | offsetT val; |
7132 | char *save = input_line_pointer; | |
252b5132 | 7133 | |
551c1ca1 AM |
7134 | input_line_pointer = scale; |
7135 | val = get_absolute_expression (); | |
7136 | ||
7137 | switch (val) | |
252b5132 | 7138 | { |
551c1ca1 | 7139 | case 1: |
252b5132 RH |
7140 | i.log2_scale_factor = 0; |
7141 | break; | |
551c1ca1 | 7142 | case 2: |
252b5132 RH |
7143 | i.log2_scale_factor = 1; |
7144 | break; | |
551c1ca1 | 7145 | case 4: |
252b5132 RH |
7146 | i.log2_scale_factor = 2; |
7147 | break; | |
551c1ca1 | 7148 | case 8: |
252b5132 RH |
7149 | i.log2_scale_factor = 3; |
7150 | break; | |
7151 | default: | |
a724f0f4 JB |
7152 | { |
7153 | char sep = *input_line_pointer; | |
7154 | ||
7155 | *input_line_pointer = '\0'; | |
7156 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
7157 | scale); | |
7158 | *input_line_pointer = sep; | |
7159 | input_line_pointer = save; | |
7160 | return NULL; | |
7161 | } | |
252b5132 | 7162 | } |
29b0f896 | 7163 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
7164 | { |
7165 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 7166 | 1 << i.log2_scale_factor); |
252b5132 | 7167 | i.log2_scale_factor = 0; |
252b5132 | 7168 | } |
551c1ca1 AM |
7169 | scale = input_line_pointer; |
7170 | input_line_pointer = save; | |
7171 | return scale; | |
252b5132 RH |
7172 | } |
7173 | ||
252b5132 | 7174 | static int |
e3bb37b5 | 7175 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 7176 | { |
29b0f896 | 7177 | expressionS *exp; |
252b5132 RH |
7178 | segT exp_seg = 0; |
7179 | char *save_input_line_pointer; | |
f3c180ae | 7180 | char *gotfree_input_line; |
40fb9820 L |
7181 | int override; |
7182 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 7183 | int ret; |
252b5132 | 7184 | |
31b2323c L |
7185 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
7186 | { | |
7187 | as_bad (_("at most %d displacement operands are allowed"), | |
7188 | MAX_MEMORY_OPERANDS); | |
7189 | return 0; | |
7190 | } | |
7191 | ||
0dfbf9d7 | 7192 | operand_type_set (&bigdisp, 0); |
40fb9820 L |
7193 | if ((i.types[this_operand].bitfield.jumpabsolute) |
7194 | || (!current_templates->start->opcode_modifier.jump | |
7195 | && !current_templates->start->opcode_modifier.jumpdword)) | |
e05278af | 7196 | { |
40fb9820 | 7197 | bigdisp.bitfield.disp32 = 1; |
e05278af | 7198 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
7199 | if (flag_code == CODE_64BIT) |
7200 | { | |
7201 | if (!override) | |
7202 | { | |
7203 | bigdisp.bitfield.disp32s = 1; | |
7204 | bigdisp.bitfield.disp64 = 1; | |
7205 | } | |
7206 | } | |
7207 | else if ((flag_code == CODE_16BIT) ^ override) | |
7208 | { | |
7209 | bigdisp.bitfield.disp32 = 0; | |
7210 | bigdisp.bitfield.disp16 = 1; | |
7211 | } | |
e05278af JB |
7212 | } |
7213 | else | |
7214 | { | |
7215 | /* For PC-relative branches, the width of the displacement | |
7216 | is dependent upon data size, not address size. */ | |
e05278af | 7217 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
7218 | if (flag_code == CODE_64BIT) |
7219 | { | |
7220 | if (override || i.suffix == WORD_MNEM_SUFFIX) | |
7221 | bigdisp.bitfield.disp16 = 1; | |
7222 | else | |
7223 | { | |
7224 | bigdisp.bitfield.disp32 = 1; | |
7225 | bigdisp.bitfield.disp32s = 1; | |
7226 | } | |
7227 | } | |
7228 | else | |
e05278af JB |
7229 | { |
7230 | if (!override) | |
7231 | override = (i.suffix == (flag_code != CODE_16BIT | |
7232 | ? WORD_MNEM_SUFFIX | |
7233 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
7234 | bigdisp.bitfield.disp32 = 1; |
7235 | if ((flag_code == CODE_16BIT) ^ override) | |
7236 | { | |
7237 | bigdisp.bitfield.disp32 = 0; | |
7238 | bigdisp.bitfield.disp16 = 1; | |
7239 | } | |
e05278af | 7240 | } |
e05278af | 7241 | } |
c6fb90c8 L |
7242 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
7243 | bigdisp); | |
252b5132 RH |
7244 | |
7245 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 7246 | i.op[this_operand].disps = exp; |
252b5132 RH |
7247 | i.disp_operands++; |
7248 | save_input_line_pointer = input_line_pointer; | |
7249 | input_line_pointer = disp_start; | |
7250 | END_STRING_AND_SAVE (disp_end); | |
7251 | ||
7252 | #ifndef GCC_ASM_O_HACK | |
7253 | #define GCC_ASM_O_HACK 0 | |
7254 | #endif | |
7255 | #if GCC_ASM_O_HACK | |
7256 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 7257 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 7258 | && displacement_string_end[-1] == '+') |
252b5132 RH |
7259 | { |
7260 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
7261 | constraint within gcc asm statements. |
7262 | For instance: | |
7263 | ||
7264 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
7265 | __asm__ __volatile__ ( \ | |
7266 | "movw %w2,%0\n\t" \ | |
7267 | "movw %w1,2+%0\n\t" \ | |
7268 | "rorl $16,%1\n\t" \ | |
7269 | "movb %b1,4+%0\n\t" \ | |
7270 | "movb %4,5+%0\n\t" \ | |
7271 | "movb $0,6+%0\n\t" \ | |
7272 | "movb %h1,7+%0\n\t" \ | |
7273 | "rorl $16,%1" \ | |
7274 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
7275 | ||
7276 | This works great except that the output assembler ends | |
7277 | up looking a bit weird if it turns out that there is | |
7278 | no offset. You end up producing code that looks like: | |
7279 | ||
7280 | #APP | |
7281 | movw $235,(%eax) | |
7282 | movw %dx,2+(%eax) | |
7283 | rorl $16,%edx | |
7284 | movb %dl,4+(%eax) | |
7285 | movb $137,5+(%eax) | |
7286 | movb $0,6+(%eax) | |
7287 | movb %dh,7+(%eax) | |
7288 | rorl $16,%edx | |
7289 | #NO_APP | |
7290 | ||
47926f60 | 7291 | So here we provide the missing zero. */ |
24eab124 AM |
7292 | |
7293 | *displacement_string_end = '0'; | |
252b5132 RH |
7294 | } |
7295 | #endif | |
3956db08 | 7296 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
7297 | if (gotfree_input_line) |
7298 | input_line_pointer = gotfree_input_line; | |
252b5132 | 7299 | |
24eab124 | 7300 | exp_seg = expression (exp); |
252b5132 | 7301 | |
636c26b0 AM |
7302 | SKIP_WHITESPACE (); |
7303 | if (*input_line_pointer) | |
7304 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
7305 | #if GCC_ASM_O_HACK | |
7306 | RESTORE_END_STRING (disp_end + 1); | |
7307 | #endif | |
636c26b0 | 7308 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 7309 | if (gotfree_input_line) |
ee86248c JB |
7310 | { |
7311 | free (gotfree_input_line); | |
7312 | ||
7313 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
7314 | exp->X_op = O_illegal; | |
7315 | } | |
7316 | ||
7317 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
7318 | ||
7319 | RESTORE_END_STRING (disp_end); | |
7320 | ||
7321 | return ret; | |
7322 | } | |
7323 | ||
7324 | static int | |
7325 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
7326 | i386_operand_type types, const char *disp_start) | |
7327 | { | |
7328 | i386_operand_type bigdisp; | |
7329 | int ret = 1; | |
636c26b0 | 7330 | |
24eab124 AM |
7331 | /* We do this to make sure that the section symbol is in |
7332 | the symbol table. We will ultimately change the relocation | |
47926f60 | 7333 | to be relative to the beginning of the section. */ |
1ae12ab7 | 7334 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
7335 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
7336 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 7337 | { |
636c26b0 | 7338 | if (exp->X_op != O_symbol) |
3992d3b7 | 7339 | goto inv_disp; |
636c26b0 | 7340 | |
e5cb08ac | 7341 | if (S_IS_LOCAL (exp->X_add_symbol) |
c64efb4b L |
7342 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
7343 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) | |
24eab124 | 7344 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
24eab124 AM |
7345 | exp->X_op = O_subtract; |
7346 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 7347 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 7348 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
7349 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
7350 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 7351 | else |
29b0f896 | 7352 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 7353 | } |
252b5132 | 7354 | |
3992d3b7 AM |
7355 | else if (exp->X_op == O_absent |
7356 | || exp->X_op == O_illegal | |
ee86248c | 7357 | || exp->X_op == O_big) |
2daf4fd8 | 7358 | { |
3992d3b7 AM |
7359 | inv_disp: |
7360 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 7361 | disp_start); |
3992d3b7 | 7362 | ret = 0; |
2daf4fd8 AM |
7363 | } |
7364 | ||
0e1147d9 L |
7365 | else if (flag_code == CODE_64BIT |
7366 | && !i.prefix[ADDR_PREFIX] | |
7367 | && exp->X_op == O_constant) | |
7368 | { | |
7369 | /* Since displacement is signed extended to 64bit, don't allow | |
7370 | disp32 and turn off disp32s if they are out of range. */ | |
7371 | i.types[this_operand].bitfield.disp32 = 0; | |
7372 | if (!fits_in_signed_long (exp->X_add_number)) | |
7373 | { | |
7374 | i.types[this_operand].bitfield.disp32s = 0; | |
7375 | if (i.types[this_operand].bitfield.baseindex) | |
7376 | { | |
7377 | as_bad (_("0x%lx out range of signed 32bit displacement"), | |
7378 | (long) exp->X_add_number); | |
7379 | ret = 0; | |
7380 | } | |
7381 | } | |
7382 | } | |
7383 | ||
4c63da97 | 7384 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3992d3b7 AM |
7385 | else if (exp->X_op != O_constant |
7386 | && OUTPUT_FLAVOR == bfd_target_aout_flavour | |
7387 | && exp_seg != absolute_section | |
7388 | && exp_seg != text_section | |
7389 | && exp_seg != data_section | |
7390 | && exp_seg != bss_section | |
7391 | && exp_seg != undefined_section | |
7392 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 7393 | { |
d0b47220 | 7394 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 7395 | ret = 0; |
24eab124 | 7396 | } |
252b5132 | 7397 | #endif |
3956db08 | 7398 | |
40fb9820 L |
7399 | /* Check if this is a displacement only operand. */ |
7400 | bigdisp = i.types[this_operand]; | |
7401 | bigdisp.bitfield.disp8 = 0; | |
7402 | bigdisp.bitfield.disp16 = 0; | |
7403 | bigdisp.bitfield.disp32 = 0; | |
7404 | bigdisp.bitfield.disp32s = 0; | |
7405 | bigdisp.bitfield.disp64 = 0; | |
0dfbf9d7 | 7406 | if (operand_type_all_zero (&bigdisp)) |
c6fb90c8 L |
7407 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
7408 | types); | |
3956db08 | 7409 | |
3992d3b7 | 7410 | return ret; |
252b5132 RH |
7411 | } |
7412 | ||
eecb386c | 7413 | /* Make sure the memory operand we've been dealt is valid. |
47926f60 KH |
7414 | Return 1 on success, 0 on a failure. */ |
7415 | ||
252b5132 | 7416 | static int |
e3bb37b5 | 7417 | i386_index_check (const char *operand_string) |
252b5132 | 7418 | { |
3e73aa7c | 7419 | int ok; |
fc0763e6 | 7420 | const char *kind = "base/index"; |
24eab124 | 7421 | #if INFER_ADDR_PREFIX |
eecb386c AM |
7422 | int fudged = 0; |
7423 | ||
24eab124 AM |
7424 | tryprefix: |
7425 | #endif | |
3e73aa7c | 7426 | ok = 1; |
fc0763e6 JB |
7427 | if (current_templates->start->opcode_modifier.isstring |
7428 | && !current_templates->start->opcode_modifier.immext | |
7429 | && (current_templates->end[-1].opcode_modifier.isstring | |
7430 | || i.mem_operands)) | |
7431 | { | |
7432 | /* Memory operands of string insns are special in that they only allow | |
7433 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
7434 | unsigned int expected; | |
7435 | ||
7436 | kind = "string address"; | |
7437 | ||
7438 | if (current_templates->start->opcode_modifier.w) | |
7439 | { | |
7440 | i386_operand_type type = current_templates->end[-1].operand_types[0]; | |
7441 | ||
7442 | if (!type.bitfield.baseindex | |
7443 | || ((!i.mem_operands != !intel_syntax) | |
7444 | && current_templates->end[-1].operand_types[1] | |
7445 | .bitfield.baseindex)) | |
7446 | type = current_templates->end[-1].operand_types[1]; | |
7447 | expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */; | |
7448 | } | |
7449 | else | |
7450 | expected = 3 /* rBX */; | |
7451 | ||
7452 | if (!i.base_reg || i.index_reg | |
7453 | || operand_type_check (i.types[this_operand], disp)) | |
7454 | ok = -1; | |
7455 | else if (!(flag_code == CODE_64BIT | |
7456 | ? i.prefix[ADDR_PREFIX] | |
7457 | ? i.base_reg->reg_type.bitfield.reg32 | |
7458 | : i.base_reg->reg_type.bitfield.reg64 | |
7459 | : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX] | |
7460 | ? i.base_reg->reg_type.bitfield.reg32 | |
7461 | : i.base_reg->reg_type.bitfield.reg16)) | |
7462 | ok = 0; | |
4c692bc7 | 7463 | else if (register_number (i.base_reg) != expected) |
fc0763e6 JB |
7464 | ok = -1; |
7465 | ||
7466 | if (ok < 0) | |
7467 | { | |
7468 | unsigned int j; | |
7469 | ||
7470 | for (j = 0; j < i386_regtab_size; ++j) | |
7471 | if ((flag_code == CODE_64BIT | |
7472 | ? i.prefix[ADDR_PREFIX] | |
7473 | ? i386_regtab[j].reg_type.bitfield.reg32 | |
7474 | : i386_regtab[j].reg_type.bitfield.reg64 | |
7475 | : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX] | |
7476 | ? i386_regtab[j].reg_type.bitfield.reg32 | |
7477 | : i386_regtab[j].reg_type.bitfield.reg16) | |
4c692bc7 | 7478 | && register_number(i386_regtab + j) == expected) |
fc0763e6 | 7479 | break; |
9c2799c2 | 7480 | gas_assert (j < i386_regtab_size); |
fc0763e6 JB |
7481 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
7482 | operand_string, | |
7483 | intel_syntax ? '[' : '(', | |
7484 | register_prefix, | |
7485 | i386_regtab[j].reg_name, | |
7486 | intel_syntax ? ']' : ')'); | |
7487 | ok = 1; | |
7488 | } | |
7489 | } | |
7490 | else if (flag_code == CODE_64BIT) | |
64e74474 | 7491 | { |
64e74474 | 7492 | if ((i.base_reg |
40fb9820 L |
7493 | && ((i.prefix[ADDR_PREFIX] == 0 |
7494 | && !i.base_reg->reg_type.bitfield.reg64) | |
7495 | || (i.prefix[ADDR_PREFIX] | |
7496 | && !i.base_reg->reg_type.bitfield.reg32)) | |
7497 | && (i.index_reg | |
9a04903e JB |
7498 | || i.base_reg->reg_num != |
7499 | (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip))) | |
64e74474 | 7500 | || (i.index_reg |
6c30d220 L |
7501 | && !(i.index_reg->reg_type.bitfield.regxmm |
7502 | || i.index_reg->reg_type.bitfield.regymm) | |
40fb9820 L |
7503 | && (!i.index_reg->reg_type.bitfield.baseindex |
7504 | || (i.prefix[ADDR_PREFIX] == 0 | |
db51cc60 L |
7505 | && i.index_reg->reg_num != RegRiz |
7506 | && !i.index_reg->reg_type.bitfield.reg64 | |
7507 | ) | |
40fb9820 | 7508 | || (i.prefix[ADDR_PREFIX] |
db51cc60 | 7509 | && i.index_reg->reg_num != RegEiz |
40fb9820 | 7510 | && !i.index_reg->reg_type.bitfield.reg32)))) |
64e74474 | 7511 | ok = 0; |
3e73aa7c JH |
7512 | } |
7513 | else | |
7514 | { | |
7515 | if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) | |
7516 | { | |
7517 | /* 16bit checks. */ | |
7518 | if ((i.base_reg | |
40fb9820 L |
7519 | && (!i.base_reg->reg_type.bitfield.reg16 |
7520 | || !i.base_reg->reg_type.bitfield.baseindex)) | |
3e73aa7c | 7521 | || (i.index_reg |
40fb9820 L |
7522 | && (!i.index_reg->reg_type.bitfield.reg16 |
7523 | || !i.index_reg->reg_type.bitfield.baseindex | |
29b0f896 AM |
7524 | || !(i.base_reg |
7525 | && i.base_reg->reg_num < 6 | |
7526 | && i.index_reg->reg_num >= 6 | |
7527 | && i.log2_scale_factor == 0)))) | |
3e73aa7c JH |
7528 | ok = 0; |
7529 | } | |
7530 | else | |
e5cb08ac | 7531 | { |
3e73aa7c JH |
7532 | /* 32bit checks. */ |
7533 | if ((i.base_reg | |
40fb9820 | 7534 | && !i.base_reg->reg_type.bitfield.reg32) |
3e73aa7c | 7535 | || (i.index_reg |
6c30d220 L |
7536 | && !i.index_reg->reg_type.bitfield.regxmm |
7537 | && !i.index_reg->reg_type.bitfield.regymm | |
db51cc60 L |
7538 | && ((!i.index_reg->reg_type.bitfield.reg32 |
7539 | && i.index_reg->reg_num != RegEiz) | |
40fb9820 | 7540 | || !i.index_reg->reg_type.bitfield.baseindex))) |
e5cb08ac | 7541 | ok = 0; |
3e73aa7c JH |
7542 | } |
7543 | } | |
7544 | if (!ok) | |
24eab124 AM |
7545 | { |
7546 | #if INFER_ADDR_PREFIX | |
fc0763e6 | 7547 | if (!i.mem_operands && !i.prefix[ADDR_PREFIX]) |
24eab124 AM |
7548 | { |
7549 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
7550 | i.prefixes += 1; | |
b23bac36 AM |
7551 | /* Change the size of any displacement too. At most one of |
7552 | Disp16 or Disp32 is set. | |
7553 | FIXME. There doesn't seem to be any real need for separate | |
7554 | Disp16 and Disp32 flags. The same goes for Imm16 and Imm32. | |
47926f60 | 7555 | Removing them would probably clean up the code quite a lot. */ |
4eed87de | 7556 | if (flag_code != CODE_64BIT |
40fb9820 L |
7557 | && (i.types[this_operand].bitfield.disp16 |
7558 | || i.types[this_operand].bitfield.disp32)) | |
7559 | i.types[this_operand] | |
c6fb90c8 | 7560 | = operand_type_xor (i.types[this_operand], disp16_32); |
eecb386c | 7561 | fudged = 1; |
24eab124 AM |
7562 | goto tryprefix; |
7563 | } | |
eecb386c | 7564 | if (fudged) |
fc0763e6 JB |
7565 | as_bad (_("`%s' is not a valid %s expression"), |
7566 | operand_string, | |
7567 | kind); | |
eecb386c | 7568 | else |
c388dee8 | 7569 | #endif |
fc0763e6 | 7570 | as_bad (_("`%s' is not a valid %s-bit %s expression"), |
eecb386c | 7571 | operand_string, |
fc0763e6 JB |
7572 | flag_code_names[i.prefix[ADDR_PREFIX] |
7573 | ? flag_code == CODE_32BIT | |
7574 | ? CODE_16BIT | |
7575 | : CODE_32BIT | |
7576 | : flag_code], | |
7577 | kind); | |
24eab124 | 7578 | } |
20f0a1fc | 7579 | return ok; |
24eab124 | 7580 | } |
252b5132 | 7581 | |
fc0763e6 | 7582 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 7583 | on error. */ |
252b5132 | 7584 | |
252b5132 | 7585 | static int |
a7619375 | 7586 | i386_att_operand (char *operand_string) |
252b5132 | 7587 | { |
af6bdddf AM |
7588 | const reg_entry *r; |
7589 | char *end_op; | |
24eab124 | 7590 | char *op_string = operand_string; |
252b5132 | 7591 | |
24eab124 | 7592 | if (is_space_char (*op_string)) |
252b5132 RH |
7593 | ++op_string; |
7594 | ||
24eab124 | 7595 | /* We check for an absolute prefix (differentiating, |
47926f60 | 7596 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
7597 | if (*op_string == ABSOLUTE_PREFIX) |
7598 | { | |
7599 | ++op_string; | |
7600 | if (is_space_char (*op_string)) | |
7601 | ++op_string; | |
40fb9820 | 7602 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 | 7603 | } |
252b5132 | 7604 | |
47926f60 | 7605 | /* Check if operand is a register. */ |
4d1bb795 | 7606 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 7607 | { |
40fb9820 L |
7608 | i386_operand_type temp; |
7609 | ||
24eab124 AM |
7610 | /* Check for a segment override by searching for ':' after a |
7611 | segment register. */ | |
7612 | op_string = end_op; | |
7613 | if (is_space_char (*op_string)) | |
7614 | ++op_string; | |
40fb9820 L |
7615 | if (*op_string == ':' |
7616 | && (r->reg_type.bitfield.sreg2 | |
7617 | || r->reg_type.bitfield.sreg3)) | |
24eab124 AM |
7618 | { |
7619 | switch (r->reg_num) | |
7620 | { | |
7621 | case 0: | |
7622 | i.seg[i.mem_operands] = &es; | |
7623 | break; | |
7624 | case 1: | |
7625 | i.seg[i.mem_operands] = &cs; | |
7626 | break; | |
7627 | case 2: | |
7628 | i.seg[i.mem_operands] = &ss; | |
7629 | break; | |
7630 | case 3: | |
7631 | i.seg[i.mem_operands] = &ds; | |
7632 | break; | |
7633 | case 4: | |
7634 | i.seg[i.mem_operands] = &fs; | |
7635 | break; | |
7636 | case 5: | |
7637 | i.seg[i.mem_operands] = &gs; | |
7638 | break; | |
7639 | } | |
252b5132 | 7640 | |
24eab124 | 7641 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
7642 | ++op_string; |
7643 | if (is_space_char (*op_string)) | |
24eab124 | 7644 | ++op_string; |
252b5132 | 7645 | |
24eab124 AM |
7646 | if (!is_digit_char (*op_string) |
7647 | && !is_identifier_char (*op_string) | |
7648 | && *op_string != '(' | |
7649 | && *op_string != ABSOLUTE_PREFIX) | |
7650 | { | |
7651 | as_bad (_("bad memory operand `%s'"), op_string); | |
7652 | return 0; | |
7653 | } | |
47926f60 | 7654 | /* Handle case of %es:*foo. */ |
24eab124 AM |
7655 | if (*op_string == ABSOLUTE_PREFIX) |
7656 | { | |
7657 | ++op_string; | |
7658 | if (is_space_char (*op_string)) | |
7659 | ++op_string; | |
40fb9820 | 7660 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 AM |
7661 | } |
7662 | goto do_memory_reference; | |
7663 | } | |
7664 | if (*op_string) | |
7665 | { | |
d0b47220 | 7666 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
7667 | return 0; |
7668 | } | |
40fb9820 L |
7669 | temp = r->reg_type; |
7670 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
7671 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
7672 | temp); | |
7d5e4556 | 7673 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 7674 | i.op[this_operand].regs = r; |
24eab124 AM |
7675 | i.reg_operands++; |
7676 | } | |
af6bdddf AM |
7677 | else if (*op_string == REGISTER_PREFIX) |
7678 | { | |
7679 | as_bad (_("bad register name `%s'"), op_string); | |
7680 | return 0; | |
7681 | } | |
24eab124 | 7682 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 7683 | { |
24eab124 | 7684 | ++op_string; |
40fb9820 | 7685 | if (i.types[this_operand].bitfield.jumpabsolute) |
24eab124 | 7686 | { |
d0b47220 | 7687 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
7688 | return 0; |
7689 | } | |
7690 | if (!i386_immediate (op_string)) | |
7691 | return 0; | |
7692 | } | |
7693 | else if (is_digit_char (*op_string) | |
7694 | || is_identifier_char (*op_string) | |
e5cb08ac | 7695 | || *op_string == '(') |
24eab124 | 7696 | { |
47926f60 | 7697 | /* This is a memory reference of some sort. */ |
af6bdddf | 7698 | char *base_string; |
252b5132 | 7699 | |
47926f60 | 7700 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
7701 | char *displacement_string_start; |
7702 | char *displacement_string_end; | |
252b5132 | 7703 | |
24eab124 | 7704 | do_memory_reference: |
24eab124 | 7705 | if ((i.mem_operands == 1 |
40fb9820 | 7706 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
7707 | || i.mem_operands == 2) |
7708 | { | |
7709 | as_bad (_("too many memory references for `%s'"), | |
7710 | current_templates->start->name); | |
7711 | return 0; | |
7712 | } | |
252b5132 | 7713 | |
24eab124 AM |
7714 | /* Check for base index form. We detect the base index form by |
7715 | looking for an ')' at the end of the operand, searching | |
7716 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
7717 | after the '('. */ | |
af6bdddf | 7718 | base_string = op_string + strlen (op_string); |
c3332e24 | 7719 | |
af6bdddf AM |
7720 | --base_string; |
7721 | if (is_space_char (*base_string)) | |
7722 | --base_string; | |
252b5132 | 7723 | |
47926f60 | 7724 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
7725 | displacement_string_start = op_string; |
7726 | displacement_string_end = base_string + 1; | |
252b5132 | 7727 | |
24eab124 AM |
7728 | if (*base_string == ')') |
7729 | { | |
af6bdddf | 7730 | char *temp_string; |
24eab124 AM |
7731 | unsigned int parens_balanced = 1; |
7732 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 7733 | equal, so this loop will not be infinite. */ |
24eab124 AM |
7734 | do |
7735 | { | |
7736 | base_string--; | |
7737 | if (*base_string == ')') | |
7738 | parens_balanced++; | |
7739 | if (*base_string == '(') | |
7740 | parens_balanced--; | |
7741 | } | |
7742 | while (parens_balanced); | |
c3332e24 | 7743 | |
af6bdddf | 7744 | temp_string = base_string; |
c3332e24 | 7745 | |
24eab124 | 7746 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
7747 | ++base_string; |
7748 | if (is_space_char (*base_string)) | |
24eab124 | 7749 | ++base_string; |
252b5132 | 7750 | |
af6bdddf | 7751 | if (*base_string == ',' |
4eed87de AM |
7752 | || ((i.base_reg = parse_register (base_string, &end_op)) |
7753 | != NULL)) | |
252b5132 | 7754 | { |
af6bdddf | 7755 | displacement_string_end = temp_string; |
252b5132 | 7756 | |
40fb9820 | 7757 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 7758 | |
af6bdddf | 7759 | if (i.base_reg) |
24eab124 | 7760 | { |
24eab124 AM |
7761 | base_string = end_op; |
7762 | if (is_space_char (*base_string)) | |
7763 | ++base_string; | |
af6bdddf AM |
7764 | } |
7765 | ||
7766 | /* There may be an index reg or scale factor here. */ | |
7767 | if (*base_string == ',') | |
7768 | { | |
7769 | ++base_string; | |
7770 | if (is_space_char (*base_string)) | |
7771 | ++base_string; | |
7772 | ||
4eed87de AM |
7773 | if ((i.index_reg = parse_register (base_string, &end_op)) |
7774 | != NULL) | |
24eab124 | 7775 | { |
af6bdddf | 7776 | base_string = end_op; |
24eab124 AM |
7777 | if (is_space_char (*base_string)) |
7778 | ++base_string; | |
af6bdddf AM |
7779 | if (*base_string == ',') |
7780 | { | |
7781 | ++base_string; | |
7782 | if (is_space_char (*base_string)) | |
7783 | ++base_string; | |
7784 | } | |
e5cb08ac | 7785 | else if (*base_string != ')') |
af6bdddf | 7786 | { |
4eed87de AM |
7787 | as_bad (_("expecting `,' or `)' " |
7788 | "after index register in `%s'"), | |
af6bdddf AM |
7789 | operand_string); |
7790 | return 0; | |
7791 | } | |
24eab124 | 7792 | } |
af6bdddf | 7793 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 7794 | { |
f76bf5e0 L |
7795 | end_op = strchr (base_string, ','); |
7796 | if (end_op) | |
7797 | *end_op = '\0'; | |
af6bdddf | 7798 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
7799 | return 0; |
7800 | } | |
252b5132 | 7801 | |
47926f60 | 7802 | /* Check for scale factor. */ |
551c1ca1 | 7803 | if (*base_string != ')') |
af6bdddf | 7804 | { |
551c1ca1 AM |
7805 | char *end_scale = i386_scale (base_string); |
7806 | ||
7807 | if (!end_scale) | |
af6bdddf | 7808 | return 0; |
24eab124 | 7809 | |
551c1ca1 | 7810 | base_string = end_scale; |
af6bdddf AM |
7811 | if (is_space_char (*base_string)) |
7812 | ++base_string; | |
7813 | if (*base_string != ')') | |
7814 | { | |
4eed87de AM |
7815 | as_bad (_("expecting `)' " |
7816 | "after scale factor in `%s'"), | |
af6bdddf AM |
7817 | operand_string); |
7818 | return 0; | |
7819 | } | |
7820 | } | |
7821 | else if (!i.index_reg) | |
24eab124 | 7822 | { |
4eed87de AM |
7823 | as_bad (_("expecting index register or scale factor " |
7824 | "after `,'; got '%c'"), | |
af6bdddf | 7825 | *base_string); |
24eab124 AM |
7826 | return 0; |
7827 | } | |
7828 | } | |
af6bdddf | 7829 | else if (*base_string != ')') |
24eab124 | 7830 | { |
4eed87de AM |
7831 | as_bad (_("expecting `,' or `)' " |
7832 | "after base register in `%s'"), | |
af6bdddf | 7833 | operand_string); |
24eab124 AM |
7834 | return 0; |
7835 | } | |
c3332e24 | 7836 | } |
af6bdddf | 7837 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 7838 | { |
f76bf5e0 L |
7839 | end_op = strchr (base_string, ','); |
7840 | if (end_op) | |
7841 | *end_op = '\0'; | |
af6bdddf | 7842 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 7843 | return 0; |
c3332e24 | 7844 | } |
24eab124 AM |
7845 | } |
7846 | ||
7847 | /* If there's an expression beginning the operand, parse it, | |
7848 | assuming displacement_string_start and | |
7849 | displacement_string_end are meaningful. */ | |
7850 | if (displacement_string_start != displacement_string_end) | |
7851 | { | |
7852 | if (!i386_displacement (displacement_string_start, | |
7853 | displacement_string_end)) | |
7854 | return 0; | |
7855 | } | |
7856 | ||
7857 | /* Special case for (%dx) while doing input/output op. */ | |
7858 | if (i.base_reg | |
0dfbf9d7 L |
7859 | && operand_type_equal (&i.base_reg->reg_type, |
7860 | ®16_inoutportreg) | |
24eab124 AM |
7861 | && i.index_reg == 0 |
7862 | && i.log2_scale_factor == 0 | |
7863 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 7864 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 7865 | { |
65da13b5 | 7866 | i.types[this_operand] = inoutportreg; |
24eab124 AM |
7867 | return 1; |
7868 | } | |
7869 | ||
eecb386c AM |
7870 | if (i386_index_check (operand_string) == 0) |
7871 | return 0; | |
5c07affc | 7872 | i.types[this_operand].bitfield.mem = 1; |
24eab124 AM |
7873 | i.mem_operands++; |
7874 | } | |
7875 | else | |
ce8a8b2f AM |
7876 | { |
7877 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
7878 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
7879 | output_invalid (*op_string), | |
7880 | this_operand + 1, | |
7881 | op_string); | |
7882 | return 0; | |
7883 | } | |
47926f60 | 7884 | return 1; /* Normal return. */ |
252b5132 RH |
7885 | } |
7886 | \f | |
fa94de6b RM |
7887 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
7888 | that an rs_machine_dependent frag may reach. */ | |
7889 | ||
7890 | unsigned int | |
7891 | i386_frag_max_var (fragS *frag) | |
7892 | { | |
7893 | /* The only relaxable frags are for jumps. | |
7894 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ | |
7895 | gas_assert (frag->fr_type == rs_machine_dependent); | |
7896 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; | |
7897 | } | |
7898 | ||
ee7fcc42 AM |
7899 | /* md_estimate_size_before_relax() |
7900 | ||
7901 | Called just before relax() for rs_machine_dependent frags. The x86 | |
7902 | assembler uses these frags to handle variable size jump | |
7903 | instructions. | |
7904 | ||
7905 | Any symbol that is now undefined will not become defined. | |
7906 | Return the correct fr_subtype in the frag. | |
7907 | Return the initial "guess for variable size of frag" to caller. | |
7908 | The guess is actually the growth beyond the fixed part. Whatever | |
7909 | we do to grow the fixed or variable part contributes to our | |
7910 | returned value. */ | |
7911 | ||
252b5132 | 7912 | int |
7016a5d5 | 7913 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 7914 | { |
252b5132 | 7915 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
7916 | check for un-relaxable symbols. On an ELF system, we can't relax |
7917 | an externally visible symbol, because it may be overridden by a | |
7918 | shared library. */ | |
7919 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 7920 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 7921 | || (IS_ELF |
31312f95 | 7922 | && (S_IS_EXTERNAL (fragP->fr_symbol) |
915bcca5 L |
7923 | || S_IS_WEAK (fragP->fr_symbol) |
7924 | || ((symbol_get_bfdsym (fragP->fr_symbol)->flags | |
7925 | & BSF_GNU_INDIRECT_FUNCTION)))) | |
fbeb56a4 DK |
7926 | #endif |
7927 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 7928 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 7929 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
7930 | #endif |
7931 | ) | |
252b5132 | 7932 | { |
b98ef147 AM |
7933 | /* Symbol is undefined in this segment, or we need to keep a |
7934 | reloc so that weak symbols can be overridden. */ | |
7935 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 7936 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
7937 | unsigned char *opcode; |
7938 | int old_fr_fix; | |
f6af82bd | 7939 | |
ee7fcc42 | 7940 | if (fragP->fr_var != NO_RELOC) |
1e9cc1c2 | 7941 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
b98ef147 | 7942 | else if (size == 2) |
f6af82bd AM |
7943 | reloc_type = BFD_RELOC_16_PCREL; |
7944 | else | |
7945 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 7946 | |
ee7fcc42 AM |
7947 | old_fr_fix = fragP->fr_fix; |
7948 | opcode = (unsigned char *) fragP->fr_opcode; | |
7949 | ||
fddf5b5b | 7950 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 7951 | { |
fddf5b5b AM |
7952 | case UNCOND_JUMP: |
7953 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 7954 | opcode[0] = 0xe9; |
252b5132 | 7955 | fragP->fr_fix += size; |
062cd5e7 AS |
7956 | fix_new (fragP, old_fr_fix, size, |
7957 | fragP->fr_symbol, | |
7958 | fragP->fr_offset, 1, | |
7959 | reloc_type); | |
252b5132 RH |
7960 | break; |
7961 | ||
fddf5b5b | 7962 | case COND_JUMP86: |
412167cb AM |
7963 | if (size == 2 |
7964 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
7965 | { |
7966 | /* Negate the condition, and branch past an | |
7967 | unconditional jump. */ | |
7968 | opcode[0] ^= 1; | |
7969 | opcode[1] = 3; | |
7970 | /* Insert an unconditional jump. */ | |
7971 | opcode[2] = 0xe9; | |
7972 | /* We added two extra opcode bytes, and have a two byte | |
7973 | offset. */ | |
7974 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
7975 | fix_new (fragP, old_fr_fix + 2, 2, |
7976 | fragP->fr_symbol, | |
7977 | fragP->fr_offset, 1, | |
7978 | reloc_type); | |
fddf5b5b AM |
7979 | break; |
7980 | } | |
7981 | /* Fall through. */ | |
7982 | ||
7983 | case COND_JUMP: | |
412167cb AM |
7984 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
7985 | { | |
3e02c1cc AM |
7986 | fixS *fixP; |
7987 | ||
412167cb | 7988 | fragP->fr_fix += 1; |
3e02c1cc AM |
7989 | fixP = fix_new (fragP, old_fr_fix, 1, |
7990 | fragP->fr_symbol, | |
7991 | fragP->fr_offset, 1, | |
7992 | BFD_RELOC_8_PCREL); | |
7993 | fixP->fx_signed = 1; | |
412167cb AM |
7994 | break; |
7995 | } | |
93c2a809 | 7996 | |
24eab124 | 7997 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 7998 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 7999 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 8000 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
8001 | /* We've added an opcode byte. */ |
8002 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
8003 | fix_new (fragP, old_fr_fix + 1, size, |
8004 | fragP->fr_symbol, | |
8005 | fragP->fr_offset, 1, | |
8006 | reloc_type); | |
252b5132 | 8007 | break; |
fddf5b5b AM |
8008 | |
8009 | default: | |
8010 | BAD_CASE (fragP->fr_subtype); | |
8011 | break; | |
252b5132 RH |
8012 | } |
8013 | frag_wane (fragP); | |
ee7fcc42 | 8014 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 8015 | } |
93c2a809 | 8016 | |
93c2a809 AM |
8017 | /* Guess size depending on current relax state. Initially the relax |
8018 | state will correspond to a short jump and we return 1, because | |
8019 | the variable part of the frag (the branch offset) is one byte | |
8020 | long. However, we can relax a section more than once and in that | |
8021 | case we must either set fr_subtype back to the unrelaxed state, | |
8022 | or return the value for the appropriate branch. */ | |
8023 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
8024 | } |
8025 | ||
47926f60 KH |
8026 | /* Called after relax() is finished. |
8027 | ||
8028 | In: Address of frag. | |
8029 | fr_type == rs_machine_dependent. | |
8030 | fr_subtype is what the address relaxed to. | |
8031 | ||
8032 | Out: Any fixSs and constants are set up. | |
8033 | Caller will turn frag into a ".space 0". */ | |
8034 | ||
252b5132 | 8035 | void |
7016a5d5 TG |
8036 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
8037 | fragS *fragP) | |
252b5132 | 8038 | { |
29b0f896 | 8039 | unsigned char *opcode; |
252b5132 | 8040 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
8041 | offsetT target_address; |
8042 | offsetT opcode_address; | |
252b5132 | 8043 | unsigned int extension = 0; |
847f7ad4 | 8044 | offsetT displacement_from_opcode_start; |
252b5132 RH |
8045 | |
8046 | opcode = (unsigned char *) fragP->fr_opcode; | |
8047 | ||
47926f60 | 8048 | /* Address we want to reach in file space. */ |
252b5132 | 8049 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 8050 | |
47926f60 | 8051 | /* Address opcode resides at in file space. */ |
252b5132 RH |
8052 | opcode_address = fragP->fr_address + fragP->fr_fix; |
8053 | ||
47926f60 | 8054 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
8055 | displacement_from_opcode_start = target_address - opcode_address; |
8056 | ||
fddf5b5b | 8057 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 8058 | { |
47926f60 KH |
8059 | /* Don't have to change opcode. */ |
8060 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 8061 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
8062 | } |
8063 | else | |
8064 | { | |
8065 | if (no_cond_jump_promotion | |
8066 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
8067 | as_warn_where (fragP->fr_file, fragP->fr_line, |
8068 | _("long jump required")); | |
252b5132 | 8069 | |
fddf5b5b AM |
8070 | switch (fragP->fr_subtype) |
8071 | { | |
8072 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
8073 | extension = 4; /* 1 opcode + 4 displacement */ | |
8074 | opcode[0] = 0xe9; | |
8075 | where_to_put_displacement = &opcode[1]; | |
8076 | break; | |
252b5132 | 8077 | |
fddf5b5b AM |
8078 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
8079 | extension = 2; /* 1 opcode + 2 displacement */ | |
8080 | opcode[0] = 0xe9; | |
8081 | where_to_put_displacement = &opcode[1]; | |
8082 | break; | |
252b5132 | 8083 | |
fddf5b5b AM |
8084 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
8085 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
8086 | extension = 5; /* 2 opcode + 4 displacement */ | |
8087 | opcode[1] = opcode[0] + 0x10; | |
8088 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
8089 | where_to_put_displacement = &opcode[2]; | |
8090 | break; | |
252b5132 | 8091 | |
fddf5b5b AM |
8092 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
8093 | extension = 3; /* 2 opcode + 2 displacement */ | |
8094 | opcode[1] = opcode[0] + 0x10; | |
8095 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
8096 | where_to_put_displacement = &opcode[2]; | |
8097 | break; | |
252b5132 | 8098 | |
fddf5b5b AM |
8099 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
8100 | extension = 4; | |
8101 | opcode[0] ^= 1; | |
8102 | opcode[1] = 3; | |
8103 | opcode[2] = 0xe9; | |
8104 | where_to_put_displacement = &opcode[3]; | |
8105 | break; | |
8106 | ||
8107 | default: | |
8108 | BAD_CASE (fragP->fr_subtype); | |
8109 | break; | |
8110 | } | |
252b5132 | 8111 | } |
fddf5b5b | 8112 | |
7b81dfbb AJ |
8113 | /* If size if less then four we are sure that the operand fits, |
8114 | but if it's 4, then it could be that the displacement is larger | |
8115 | then -/+ 2GB. */ | |
8116 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
8117 | && object_64bit | |
8118 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
8119 | + ((addressT) 1 << 31)) |
8120 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
8121 | { |
8122 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
8123 | _("jump target out of range")); | |
8124 | /* Make us emit 0. */ | |
8125 | displacement_from_opcode_start = extension; | |
8126 | } | |
47926f60 | 8127 | /* Now put displacement after opcode. */ |
252b5132 RH |
8128 | md_number_to_chars ((char *) where_to_put_displacement, |
8129 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 8130 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
8131 | fragP->fr_fix += extension; |
8132 | } | |
8133 | \f | |
7016a5d5 | 8134 | /* Apply a fixup (fixP) to segment data, once it has been determined |
252b5132 RH |
8135 | by our caller that we have all the info we need to fix it up. |
8136 | ||
7016a5d5 TG |
8137 | Parameter valP is the pointer to the value of the bits. |
8138 | ||
252b5132 RH |
8139 | On the 386, immediates, displacements, and data pointers are all in |
8140 | the same (little-endian) format, so we don't need to care about which | |
8141 | we are handling. */ | |
8142 | ||
94f592af | 8143 | void |
7016a5d5 | 8144 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 8145 | { |
94f592af | 8146 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 8147 | valueT value = *valP; |
252b5132 | 8148 | |
f86103b7 | 8149 | #if !defined (TE_Mach) |
93382f6d AM |
8150 | if (fixP->fx_pcrel) |
8151 | { | |
8152 | switch (fixP->fx_r_type) | |
8153 | { | |
5865bb77 ILT |
8154 | default: |
8155 | break; | |
8156 | ||
d6ab8113 JB |
8157 | case BFD_RELOC_64: |
8158 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
8159 | break; | |
93382f6d | 8160 | case BFD_RELOC_32: |
ae8887b5 | 8161 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
8162 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
8163 | break; | |
8164 | case BFD_RELOC_16: | |
8165 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
8166 | break; | |
8167 | case BFD_RELOC_8: | |
8168 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
8169 | break; | |
8170 | } | |
8171 | } | |
252b5132 | 8172 | |
a161fe53 | 8173 | if (fixP->fx_addsy != NULL |
31312f95 | 8174 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 8175 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 AM |
8176 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
8177 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) | |
8178 | && !use_rela_relocations) | |
252b5132 | 8179 | { |
31312f95 AM |
8180 | /* This is a hack. There should be a better way to handle this. |
8181 | This covers for the fact that bfd_install_relocation will | |
8182 | subtract the current location (for partial_inplace, PC relative | |
8183 | relocations); see more below. */ | |
252b5132 | 8184 | #ifndef OBJ_AOUT |
718ddfc0 | 8185 | if (IS_ELF |
252b5132 RH |
8186 | #ifdef TE_PE |
8187 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
8188 | #endif | |
8189 | ) | |
8190 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
8191 | #endif | |
8192 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 8193 | if (IS_ELF) |
252b5132 | 8194 | { |
6539b54b | 8195 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 8196 | |
6539b54b | 8197 | if ((sym_seg == seg |
2f66722d | 8198 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 8199 | && sym_seg != absolute_section)) |
af65af87 | 8200 | && !generic_force_reloc (fixP)) |
2f66722d AM |
8201 | { |
8202 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
8203 | bfd_install_relocation subtracts them out again. I think |
8204 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
8205 | it. FIXME. */ |
8206 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
8207 | } | |
252b5132 RH |
8208 | } |
8209 | #endif | |
8210 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
8211 | /* For some reason, the PE format does not store a |
8212 | section address offset for a PC relative symbol. */ | |
8213 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 8214 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
8215 | value += md_pcrel_from (fixP); |
8216 | #endif | |
8217 | } | |
fbeb56a4 DK |
8218 | #if defined (OBJ_COFF) && defined (TE_PE) |
8219 | if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
8220 | { | |
8221 | value -= S_GET_VALUE (fixP->fx_addsy); | |
8222 | } | |
8223 | #endif | |
252b5132 RH |
8224 | |
8225 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 8226 | and we must not disappoint it. */ |
252b5132 | 8227 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 8228 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
8229 | switch (fixP->fx_r_type) |
8230 | { | |
8231 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 8232 | case BFD_RELOC_X86_64_PLT32: |
47926f60 KH |
8233 | /* Make the jump instruction point to the address of the operand. At |
8234 | runtime we merely add the offset to the actual PLT entry. */ | |
8235 | value = -4; | |
8236 | break; | |
31312f95 | 8237 | |
13ae64f3 JJ |
8238 | case BFD_RELOC_386_TLS_GD: |
8239 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 8240 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
8241 | case BFD_RELOC_386_TLS_IE: |
8242 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 8243 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
8244 | case BFD_RELOC_X86_64_TLSGD: |
8245 | case BFD_RELOC_X86_64_TLSLD: | |
8246 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 8247 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
8248 | value = 0; /* Fully resolved at runtime. No addend. */ |
8249 | /* Fallthrough */ | |
8250 | case BFD_RELOC_386_TLS_LE: | |
8251 | case BFD_RELOC_386_TLS_LDO_32: | |
8252 | case BFD_RELOC_386_TLS_LE_32: | |
8253 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 8254 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 8255 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 8256 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
8257 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
8258 | break; | |
8259 | ||
67a4f2b7 AO |
8260 | case BFD_RELOC_386_TLS_DESC_CALL: |
8261 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
8262 | value = 0; /* Fully resolved at runtime. No addend. */ | |
8263 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
8264 | fixP->fx_done = 0; | |
8265 | return; | |
8266 | ||
00f7efb6 JJ |
8267 | case BFD_RELOC_386_GOT32: |
8268 | case BFD_RELOC_X86_64_GOT32: | |
47926f60 KH |
8269 | value = 0; /* Fully resolved at runtime. No addend. */ |
8270 | break; | |
47926f60 KH |
8271 | |
8272 | case BFD_RELOC_VTABLE_INHERIT: | |
8273 | case BFD_RELOC_VTABLE_ENTRY: | |
8274 | fixP->fx_done = 0; | |
94f592af | 8275 | return; |
47926f60 KH |
8276 | |
8277 | default: | |
8278 | break; | |
8279 | } | |
8280 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 8281 | *valP = value; |
f86103b7 | 8282 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 8283 | |
3e73aa7c | 8284 | /* Are we finished with this relocation now? */ |
c6682705 | 8285 | if (fixP->fx_addsy == NULL) |
3e73aa7c | 8286 | fixP->fx_done = 1; |
fbeb56a4 DK |
8287 | #if defined (OBJ_COFF) && defined (TE_PE) |
8288 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
8289 | { | |
8290 | fixP->fx_done = 0; | |
8291 | /* Remember value for tc_gen_reloc. */ | |
8292 | fixP->fx_addnumber = value; | |
8293 | /* Clear out the frag for now. */ | |
8294 | value = 0; | |
8295 | } | |
8296 | #endif | |
3e73aa7c JH |
8297 | else if (use_rela_relocations) |
8298 | { | |
8299 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
8300 | /* Remember value for tc_gen_reloc. */ |
8301 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
8302 | value = 0; |
8303 | } | |
f86103b7 | 8304 | |
94f592af | 8305 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 8306 | } |
252b5132 | 8307 | \f |
252b5132 | 8308 | char * |
499ac353 | 8309 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 8310 | { |
499ac353 NC |
8311 | /* This outputs the LITTLENUMs in REVERSE order; |
8312 | in accord with the bigendian 386. */ | |
8313 | return ieee_md_atof (type, litP, sizeP, FALSE); | |
252b5132 RH |
8314 | } |
8315 | \f | |
2d545b82 | 8316 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 8317 | |
252b5132 | 8318 | static char * |
e3bb37b5 | 8319 | output_invalid (int c) |
252b5132 | 8320 | { |
3882b010 | 8321 | if (ISPRINT (c)) |
f9f21a03 L |
8322 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
8323 | "'%c'", c); | |
252b5132 | 8324 | else |
f9f21a03 | 8325 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 8326 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
8327 | return output_invalid_buf; |
8328 | } | |
8329 | ||
af6bdddf | 8330 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
8331 | |
8332 | static const reg_entry * | |
4d1bb795 | 8333 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 8334 | { |
af6bdddf AM |
8335 | char *s = reg_string; |
8336 | char *p; | |
252b5132 RH |
8337 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
8338 | const reg_entry *r; | |
8339 | ||
8340 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
8341 | if (*s == REGISTER_PREFIX) | |
8342 | ++s; | |
8343 | ||
8344 | if (is_space_char (*s)) | |
8345 | ++s; | |
8346 | ||
8347 | p = reg_name_given; | |
af6bdddf | 8348 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
8349 | { |
8350 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
8351 | return (const reg_entry *) NULL; |
8352 | s++; | |
252b5132 RH |
8353 | } |
8354 | ||
6588847e DN |
8355 | /* For naked regs, make sure that we are not dealing with an identifier. |
8356 | This prevents confusing an identifier like `eax_var' with register | |
8357 | `eax'. */ | |
8358 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
8359 | return (const reg_entry *) NULL; | |
8360 | ||
af6bdddf | 8361 | *end_op = s; |
252b5132 RH |
8362 | |
8363 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
8364 | ||
5f47d35b | 8365 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 8366 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 8367 | { |
5f47d35b AM |
8368 | if (is_space_char (*s)) |
8369 | ++s; | |
8370 | if (*s == '(') | |
8371 | { | |
af6bdddf | 8372 | ++s; |
5f47d35b AM |
8373 | if (is_space_char (*s)) |
8374 | ++s; | |
8375 | if (*s >= '0' && *s <= '7') | |
8376 | { | |
db557034 | 8377 | int fpr = *s - '0'; |
af6bdddf | 8378 | ++s; |
5f47d35b AM |
8379 | if (is_space_char (*s)) |
8380 | ++s; | |
8381 | if (*s == ')') | |
8382 | { | |
8383 | *end_op = s + 1; | |
1e9cc1c2 | 8384 | r = (const reg_entry *) hash_find (reg_hash, "st(0)"); |
db557034 AM |
8385 | know (r); |
8386 | return r + fpr; | |
5f47d35b | 8387 | } |
5f47d35b | 8388 | } |
47926f60 | 8389 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
8390 | return (const reg_entry *) NULL; |
8391 | } | |
8392 | } | |
8393 | ||
a60de03c JB |
8394 | if (r == NULL || allow_pseudo_reg) |
8395 | return r; | |
8396 | ||
0dfbf9d7 | 8397 | if (operand_type_all_zero (&r->reg_type)) |
a60de03c JB |
8398 | return (const reg_entry *) NULL; |
8399 | ||
192dc9c6 JB |
8400 | if ((r->reg_type.bitfield.reg32 |
8401 | || r->reg_type.bitfield.sreg3 | |
8402 | || r->reg_type.bitfield.control | |
8403 | || r->reg_type.bitfield.debug | |
8404 | || r->reg_type.bitfield.test) | |
8405 | && !cpu_arch_flags.bitfield.cpui386) | |
8406 | return (const reg_entry *) NULL; | |
8407 | ||
309d3373 JB |
8408 | if (r->reg_type.bitfield.floatreg |
8409 | && !cpu_arch_flags.bitfield.cpu8087 | |
8410 | && !cpu_arch_flags.bitfield.cpu287 | |
8411 | && !cpu_arch_flags.bitfield.cpu387) | |
8412 | return (const reg_entry *) NULL; | |
8413 | ||
192dc9c6 JB |
8414 | if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx) |
8415 | return (const reg_entry *) NULL; | |
8416 | ||
8417 | if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse) | |
8418 | return (const reg_entry *) NULL; | |
8419 | ||
40f12533 L |
8420 | if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx) |
8421 | return (const reg_entry *) NULL; | |
8422 | ||
db51cc60 | 8423 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ |
a60de03c | 8424 | if (!allow_index_reg |
db51cc60 L |
8425 | && (r->reg_num == RegEiz || r->reg_num == RegRiz)) |
8426 | return (const reg_entry *) NULL; | |
8427 | ||
a60de03c JB |
8428 | if (((r->reg_flags & (RegRex64 | RegRex)) |
8429 | || r->reg_type.bitfield.reg64) | |
40fb9820 | 8430 | && (!cpu_arch_flags.bitfield.cpulm |
0dfbf9d7 | 8431 | || !operand_type_equal (&r->reg_type, &control)) |
1ae00879 | 8432 | && flag_code != CODE_64BIT) |
20f0a1fc | 8433 | return (const reg_entry *) NULL; |
1ae00879 | 8434 | |
b7240065 JB |
8435 | if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax) |
8436 | return (const reg_entry *) NULL; | |
8437 | ||
252b5132 RH |
8438 | return r; |
8439 | } | |
4d1bb795 JB |
8440 | |
8441 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
8442 | ||
8443 | static const reg_entry * | |
8444 | parse_register (char *reg_string, char **end_op) | |
8445 | { | |
8446 | const reg_entry *r; | |
8447 | ||
8448 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
8449 | r = parse_real_register (reg_string, end_op); | |
8450 | else | |
8451 | r = NULL; | |
8452 | if (!r) | |
8453 | { | |
8454 | char *save = input_line_pointer; | |
8455 | char c; | |
8456 | symbolS *symbolP; | |
8457 | ||
8458 | input_line_pointer = reg_string; | |
8459 | c = get_symbol_end (); | |
8460 | symbolP = symbol_find (reg_string); | |
8461 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
8462 | { | |
8463 | const expressionS *e = symbol_get_value_expression (symbolP); | |
8464 | ||
0398aac5 | 8465 | know (e->X_op == O_register); |
4eed87de | 8466 | know (e->X_add_number >= 0 |
c3fe08fa | 8467 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 JB |
8468 | r = i386_regtab + e->X_add_number; |
8469 | *end_op = input_line_pointer; | |
8470 | } | |
8471 | *input_line_pointer = c; | |
8472 | input_line_pointer = save; | |
8473 | } | |
8474 | return r; | |
8475 | } | |
8476 | ||
8477 | int | |
8478 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
8479 | { | |
8480 | const reg_entry *r; | |
8481 | char *end = input_line_pointer; | |
8482 | ||
8483 | *end = *nextcharP; | |
8484 | r = parse_register (name, &input_line_pointer); | |
8485 | if (r && end <= input_line_pointer) | |
8486 | { | |
8487 | *nextcharP = *input_line_pointer; | |
8488 | *input_line_pointer = 0; | |
8489 | e->X_op = O_register; | |
8490 | e->X_add_number = r - i386_regtab; | |
8491 | return 1; | |
8492 | } | |
8493 | input_line_pointer = end; | |
8494 | *end = 0; | |
ee86248c | 8495 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
8496 | } |
8497 | ||
8498 | void | |
8499 | md_operand (expressionS *e) | |
8500 | { | |
ee86248c JB |
8501 | char *end; |
8502 | const reg_entry *r; | |
4d1bb795 | 8503 | |
ee86248c JB |
8504 | switch (*input_line_pointer) |
8505 | { | |
8506 | case REGISTER_PREFIX: | |
8507 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
8508 | if (r) |
8509 | { | |
8510 | e->X_op = O_register; | |
8511 | e->X_add_number = r - i386_regtab; | |
8512 | input_line_pointer = end; | |
8513 | } | |
ee86248c JB |
8514 | break; |
8515 | ||
8516 | case '[': | |
9c2799c2 | 8517 | gas_assert (intel_syntax); |
ee86248c JB |
8518 | end = input_line_pointer++; |
8519 | expression (e); | |
8520 | if (*input_line_pointer == ']') | |
8521 | { | |
8522 | ++input_line_pointer; | |
8523 | e->X_op_symbol = make_expr_symbol (e); | |
8524 | e->X_add_symbol = NULL; | |
8525 | e->X_add_number = 0; | |
8526 | e->X_op = O_index; | |
8527 | } | |
8528 | else | |
8529 | { | |
8530 | e->X_op = O_absent; | |
8531 | input_line_pointer = end; | |
8532 | } | |
8533 | break; | |
4d1bb795 JB |
8534 | } |
8535 | } | |
8536 | ||
252b5132 | 8537 | \f |
4cc782b5 | 8538 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
12b55ccc | 8539 | const char *md_shortopts = "kVQ:sqn"; |
252b5132 | 8540 | #else |
12b55ccc | 8541 | const char *md_shortopts = "qn"; |
252b5132 | 8542 | #endif |
6e0b89ee | 8543 | |
3e73aa7c | 8544 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
8545 | #define OPTION_64 (OPTION_MD_BASE + 1) |
8546 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
8547 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
8548 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
8549 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
8550 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
8551 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
8552 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
8553 | #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9) | |
c0f3af97 | 8554 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 8555 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
7bab8ab5 JB |
8556 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
8557 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) | |
8558 | #define OPTION_X32 (OPTION_MD_BASE + 14) | |
b3b91714 | 8559 | |
99ad8390 NC |
8560 | struct option md_longopts[] = |
8561 | { | |
3e73aa7c | 8562 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 | 8563 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 8564 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c | 8565 | {"64", no_argument, NULL, OPTION_64}, |
351f65ca L |
8566 | #endif |
8567 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
570561f7 | 8568 | {"x32", no_argument, NULL, OPTION_X32}, |
6e0b89ee | 8569 | #endif |
b3b91714 | 8570 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
8571 | {"march", required_argument, NULL, OPTION_MARCH}, |
8572 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
8573 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
8574 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
8575 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
8576 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
8577 | {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC}, | |
c0f3af97 | 8578 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
daf50ae7 | 8579 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
7bab8ab5 | 8580 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
539f890d | 8581 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
252b5132 RH |
8582 | {NULL, no_argument, NULL, 0} |
8583 | }; | |
8584 | size_t md_longopts_size = sizeof (md_longopts); | |
8585 | ||
8586 | int | |
9103f4f4 | 8587 | md_parse_option (int c, char *arg) |
252b5132 | 8588 | { |
91d6fa6a | 8589 | unsigned int j; |
6305a203 | 8590 | char *arch, *next; |
9103f4f4 | 8591 | |
252b5132 RH |
8592 | switch (c) |
8593 | { | |
12b55ccc L |
8594 | case 'n': |
8595 | optimize_align_code = 0; | |
8596 | break; | |
8597 | ||
a38cf1db AM |
8598 | case 'q': |
8599 | quiet_warnings = 1; | |
252b5132 RH |
8600 | break; |
8601 | ||
8602 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
8603 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
8604 | should be emitted or not. FIXME: Not implemented. */ | |
8605 | case 'Q': | |
252b5132 RH |
8606 | break; |
8607 | ||
8608 | /* -V: SVR4 argument to print version ID. */ | |
8609 | case 'V': | |
8610 | print_version_id (); | |
8611 | break; | |
8612 | ||
a38cf1db AM |
8613 | /* -k: Ignore for FreeBSD compatibility. */ |
8614 | case 'k': | |
252b5132 | 8615 | break; |
4cc782b5 ILT |
8616 | |
8617 | case 's': | |
8618 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 8619 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 8620 | break; |
99ad8390 | 8621 | #endif |
321098a5 | 8622 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 8623 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c JH |
8624 | case OPTION_64: |
8625 | { | |
8626 | const char **list, **l; | |
8627 | ||
3e73aa7c JH |
8628 | list = bfd_target_list (); |
8629 | for (l = list; *l != NULL; l++) | |
8620418b | 8630 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
99ad8390 NC |
8631 | || strcmp (*l, "coff-x86-64") == 0 |
8632 | || strcmp (*l, "pe-x86-64") == 0 | |
d382c579 TG |
8633 | || strcmp (*l, "pei-x86-64") == 0 |
8634 | || strcmp (*l, "mach-o-x86-64") == 0) | |
6e0b89ee AM |
8635 | { |
8636 | default_arch = "x86_64"; | |
8637 | break; | |
8638 | } | |
3e73aa7c | 8639 | if (*l == NULL) |
2b5d6a91 | 8640 | as_fatal (_("no compiled in support for x86_64")); |
3e73aa7c JH |
8641 | free (list); |
8642 | } | |
8643 | break; | |
8644 | #endif | |
252b5132 | 8645 | |
351f65ca | 8646 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570561f7 | 8647 | case OPTION_X32: |
351f65ca L |
8648 | if (IS_ELF) |
8649 | { | |
8650 | const char **list, **l; | |
8651 | ||
8652 | list = bfd_target_list (); | |
8653 | for (l = list; *l != NULL; l++) | |
8654 | if (CONST_STRNEQ (*l, "elf32-x86-64")) | |
8655 | { | |
8656 | default_arch = "x86_64:32"; | |
8657 | break; | |
8658 | } | |
8659 | if (*l == NULL) | |
2b5d6a91 | 8660 | as_fatal (_("no compiled in support for 32bit x86_64")); |
351f65ca L |
8661 | free (list); |
8662 | } | |
8663 | else | |
8664 | as_fatal (_("32bit x86_64 is only supported for ELF")); | |
8665 | break; | |
8666 | #endif | |
8667 | ||
6e0b89ee AM |
8668 | case OPTION_32: |
8669 | default_arch = "i386"; | |
8670 | break; | |
8671 | ||
b3b91714 AM |
8672 | case OPTION_DIVIDE: |
8673 | #ifdef SVR4_COMMENT_CHARS | |
8674 | { | |
8675 | char *n, *t; | |
8676 | const char *s; | |
8677 | ||
8678 | n = (char *) xmalloc (strlen (i386_comment_chars) + 1); | |
8679 | t = n; | |
8680 | for (s = i386_comment_chars; *s != '\0'; s++) | |
8681 | if (*s != '/') | |
8682 | *t++ = *s; | |
8683 | *t = '\0'; | |
8684 | i386_comment_chars = n; | |
8685 | } | |
8686 | #endif | |
8687 | break; | |
8688 | ||
9103f4f4 | 8689 | case OPTION_MARCH: |
6305a203 L |
8690 | arch = xstrdup (arg); |
8691 | do | |
9103f4f4 | 8692 | { |
6305a203 | 8693 | if (*arch == '.') |
2b5d6a91 | 8694 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
8695 | next = strchr (arch, '+'); |
8696 | if (next) | |
8697 | *next++ = '\0'; | |
91d6fa6a | 8698 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 8699 | { |
91d6fa6a | 8700 | if (strcmp (arch, cpu_arch [j].name) == 0) |
ccc9c027 | 8701 | { |
6305a203 | 8702 | /* Processor. */ |
1ded5609 JB |
8703 | if (! cpu_arch[j].flags.bitfield.cpui386) |
8704 | continue; | |
8705 | ||
91d6fa6a | 8706 | cpu_arch_name = cpu_arch[j].name; |
6305a203 | 8707 | cpu_sub_arch_name = NULL; |
91d6fa6a NC |
8708 | cpu_arch_flags = cpu_arch[j].flags; |
8709 | cpu_arch_isa = cpu_arch[j].type; | |
8710 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
6305a203 L |
8711 | if (!cpu_arch_tune_set) |
8712 | { | |
8713 | cpu_arch_tune = cpu_arch_isa; | |
8714 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
8715 | } | |
8716 | break; | |
8717 | } | |
91d6fa6a NC |
8718 | else if (*cpu_arch [j].name == '.' |
8719 | && strcmp (arch, cpu_arch [j].name + 1) == 0) | |
6305a203 L |
8720 | { |
8721 | /* ISA entension. */ | |
8722 | i386_cpu_flags flags; | |
309d3373 | 8723 | |
49021df2 | 8724 | if (!cpu_arch[j].negated) |
309d3373 | 8725 | flags = cpu_flags_or (cpu_arch_flags, |
91d6fa6a | 8726 | cpu_arch[j].flags); |
309d3373 JB |
8727 | else |
8728 | flags = cpu_flags_and_not (cpu_arch_flags, | |
49021df2 | 8729 | cpu_arch[j].flags); |
0dfbf9d7 | 8730 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
6305a203 L |
8731 | { |
8732 | if (cpu_sub_arch_name) | |
8733 | { | |
8734 | char *name = cpu_sub_arch_name; | |
8735 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 8736 | cpu_arch[j].name, |
1bf57e9f | 8737 | (const char *) NULL); |
6305a203 L |
8738 | free (name); |
8739 | } | |
8740 | else | |
91d6fa6a | 8741 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
6305a203 | 8742 | cpu_arch_flags = flags; |
a586129e | 8743 | cpu_arch_isa_flags = flags; |
6305a203 L |
8744 | } |
8745 | break; | |
ccc9c027 | 8746 | } |
9103f4f4 | 8747 | } |
6305a203 | 8748 | |
91d6fa6a | 8749 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 8750 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
8751 | |
8752 | arch = next; | |
9103f4f4 | 8753 | } |
6305a203 | 8754 | while (next != NULL ); |
9103f4f4 L |
8755 | break; |
8756 | ||
8757 | case OPTION_MTUNE: | |
8758 | if (*arg == '.') | |
2b5d6a91 | 8759 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
91d6fa6a | 8760 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 8761 | { |
91d6fa6a | 8762 | if (strcmp (arg, cpu_arch [j].name) == 0) |
9103f4f4 | 8763 | { |
ccc9c027 | 8764 | cpu_arch_tune_set = 1; |
91d6fa6a NC |
8765 | cpu_arch_tune = cpu_arch [j].type; |
8766 | cpu_arch_tune_flags = cpu_arch[j].flags; | |
9103f4f4 L |
8767 | break; |
8768 | } | |
8769 | } | |
91d6fa6a | 8770 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 8771 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
9103f4f4 L |
8772 | break; |
8773 | ||
1efbbeb4 L |
8774 | case OPTION_MMNEMONIC: |
8775 | if (strcasecmp (arg, "att") == 0) | |
8776 | intel_mnemonic = 0; | |
8777 | else if (strcasecmp (arg, "intel") == 0) | |
8778 | intel_mnemonic = 1; | |
8779 | else | |
2b5d6a91 | 8780 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
1efbbeb4 L |
8781 | break; |
8782 | ||
8783 | case OPTION_MSYNTAX: | |
8784 | if (strcasecmp (arg, "att") == 0) | |
8785 | intel_syntax = 0; | |
8786 | else if (strcasecmp (arg, "intel") == 0) | |
8787 | intel_syntax = 1; | |
8788 | else | |
2b5d6a91 | 8789 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
1efbbeb4 L |
8790 | break; |
8791 | ||
8792 | case OPTION_MINDEX_REG: | |
8793 | allow_index_reg = 1; | |
8794 | break; | |
8795 | ||
8796 | case OPTION_MNAKED_REG: | |
8797 | allow_naked_reg = 1; | |
8798 | break; | |
8799 | ||
8800 | case OPTION_MOLD_GCC: | |
8801 | old_gcc = 1; | |
1efbbeb4 L |
8802 | break; |
8803 | ||
c0f3af97 L |
8804 | case OPTION_MSSE2AVX: |
8805 | sse2avx = 1; | |
8806 | break; | |
8807 | ||
daf50ae7 L |
8808 | case OPTION_MSSE_CHECK: |
8809 | if (strcasecmp (arg, "error") == 0) | |
7bab8ab5 | 8810 | sse_check = check_error; |
daf50ae7 | 8811 | else if (strcasecmp (arg, "warning") == 0) |
7bab8ab5 | 8812 | sse_check = check_warning; |
daf50ae7 | 8813 | else if (strcasecmp (arg, "none") == 0) |
7bab8ab5 | 8814 | sse_check = check_none; |
daf50ae7 | 8815 | else |
2b5d6a91 | 8816 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
daf50ae7 L |
8817 | break; |
8818 | ||
7bab8ab5 JB |
8819 | case OPTION_MOPERAND_CHECK: |
8820 | if (strcasecmp (arg, "error") == 0) | |
8821 | operand_check = check_error; | |
8822 | else if (strcasecmp (arg, "warning") == 0) | |
8823 | operand_check = check_warning; | |
8824 | else if (strcasecmp (arg, "none") == 0) | |
8825 | operand_check = check_none; | |
8826 | else | |
8827 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); | |
8828 | break; | |
8829 | ||
539f890d L |
8830 | case OPTION_MAVXSCALAR: |
8831 | if (strcasecmp (arg, "128") == 0) | |
8832 | avxscalar = vex128; | |
8833 | else if (strcasecmp (arg, "256") == 0) | |
8834 | avxscalar = vex256; | |
8835 | else | |
2b5d6a91 | 8836 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
539f890d L |
8837 | break; |
8838 | ||
252b5132 RH |
8839 | default: |
8840 | return 0; | |
8841 | } | |
8842 | return 1; | |
8843 | } | |
8844 | ||
8a2c8fef L |
8845 | #define MESSAGE_TEMPLATE \ |
8846 | " " | |
8847 | ||
8848 | static void | |
1ded5609 | 8849 | show_arch (FILE *stream, int ext, int check) |
8a2c8fef L |
8850 | { |
8851 | static char message[] = MESSAGE_TEMPLATE; | |
8852 | char *start = message + 27; | |
8853 | char *p; | |
8854 | int size = sizeof (MESSAGE_TEMPLATE); | |
8855 | int left; | |
8856 | const char *name; | |
8857 | int len; | |
8858 | unsigned int j; | |
8859 | ||
8860 | p = start; | |
8861 | left = size - (start - message); | |
8862 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) | |
8863 | { | |
8864 | /* Should it be skipped? */ | |
8865 | if (cpu_arch [j].skip) | |
8866 | continue; | |
8867 | ||
8868 | name = cpu_arch [j].name; | |
8869 | len = cpu_arch [j].len; | |
8870 | if (*name == '.') | |
8871 | { | |
8872 | /* It is an extension. Skip if we aren't asked to show it. */ | |
8873 | if (ext) | |
8874 | { | |
8875 | name++; | |
8876 | len--; | |
8877 | } | |
8878 | else | |
8879 | continue; | |
8880 | } | |
8881 | else if (ext) | |
8882 | { | |
8883 | /* It is an processor. Skip if we show only extension. */ | |
8884 | continue; | |
8885 | } | |
1ded5609 JB |
8886 | else if (check && ! cpu_arch[j].flags.bitfield.cpui386) |
8887 | { | |
8888 | /* It is an impossible processor - skip. */ | |
8889 | continue; | |
8890 | } | |
8a2c8fef L |
8891 | |
8892 | /* Reserve 2 spaces for ", " or ",\0" */ | |
8893 | left -= len + 2; | |
8894 | ||
8895 | /* Check if there is any room. */ | |
8896 | if (left >= 0) | |
8897 | { | |
8898 | if (p != start) | |
8899 | { | |
8900 | *p++ = ','; | |
8901 | *p++ = ' '; | |
8902 | } | |
8903 | p = mempcpy (p, name, len); | |
8904 | } | |
8905 | else | |
8906 | { | |
8907 | /* Output the current message now and start a new one. */ | |
8908 | *p++ = ','; | |
8909 | *p = '\0'; | |
8910 | fprintf (stream, "%s\n", message); | |
8911 | p = start; | |
8912 | left = size - (start - message) - len - 2; | |
8d63c93e | 8913 | |
8a2c8fef L |
8914 | gas_assert (left >= 0); |
8915 | ||
8916 | p = mempcpy (p, name, len); | |
8917 | } | |
8918 | } | |
8919 | ||
8920 | *p = '\0'; | |
8921 | fprintf (stream, "%s\n", message); | |
8922 | } | |
8923 | ||
252b5132 | 8924 | void |
8a2c8fef | 8925 | md_show_usage (FILE *stream) |
252b5132 | 8926 | { |
4cc782b5 ILT |
8927 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8928 | fprintf (stream, _("\ | |
a38cf1db AM |
8929 | -Q ignored\n\ |
8930 | -V print assembler version number\n\ | |
b3b91714 AM |
8931 | -k ignored\n")); |
8932 | #endif | |
8933 | fprintf (stream, _("\ | |
12b55ccc | 8934 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
8935 | -q quieten some warnings\n")); |
8936 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
8937 | fprintf (stream, _("\ | |
a38cf1db | 8938 | -s ignored\n")); |
b3b91714 | 8939 | #endif |
321098a5 L |
8940 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
8941 | || defined (TE_PE) || defined (TE_PEP)) | |
751d281c | 8942 | fprintf (stream, _("\ |
570561f7 | 8943 | --32/--64/--x32 generate 32bit/64bit/x32 code\n")); |
751d281c | 8944 | #endif |
b3b91714 AM |
8945 | #ifdef SVR4_COMMENT_CHARS |
8946 | fprintf (stream, _("\ | |
8947 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
8948 | #else |
8949 | fprintf (stream, _("\ | |
b3b91714 | 8950 | --divide ignored\n")); |
4cc782b5 | 8951 | #endif |
9103f4f4 | 8952 | fprintf (stream, _("\ |
6305a203 | 8953 | -march=CPU[,+EXTENSION...]\n\ |
8a2c8fef | 8954 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
1ded5609 | 8955 | show_arch (stream, 0, 1); |
8a2c8fef L |
8956 | fprintf (stream, _("\ |
8957 | EXTENSION is combination of:\n")); | |
1ded5609 | 8958 | show_arch (stream, 1, 0); |
6305a203 | 8959 | fprintf (stream, _("\ |
8a2c8fef | 8960 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
1ded5609 | 8961 | show_arch (stream, 0, 0); |
ba104c83 | 8962 | fprintf (stream, _("\ |
c0f3af97 L |
8963 | -msse2avx encode SSE instructions with VEX prefix\n")); |
8964 | fprintf (stream, _("\ | |
daf50ae7 L |
8965 | -msse-check=[none|error|warning]\n\ |
8966 | check SSE instructions\n")); | |
8967 | fprintf (stream, _("\ | |
7bab8ab5 JB |
8968 | -moperand-check=[none|error|warning]\n\ |
8969 | check operand combinations for validity\n")); | |
8970 | fprintf (stream, _("\ | |
539f890d L |
8971 | -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\ |
8972 | length\n")); | |
8973 | fprintf (stream, _("\ | |
ba104c83 L |
8974 | -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n")); |
8975 | fprintf (stream, _("\ | |
8976 | -msyntax=[att|intel] use AT&T/Intel syntax\n")); | |
8977 | fprintf (stream, _("\ | |
8978 | -mindex-reg support pseudo index registers\n")); | |
8979 | fprintf (stream, _("\ | |
8980 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
8981 | fprintf (stream, _("\ | |
8982 | -mold-gcc support old (<= 2.8.1) versions of gcc\n")); | |
252b5132 RH |
8983 | } |
8984 | ||
3e73aa7c | 8985 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 8986 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 8987 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
8988 | |
8989 | /* Pick the target format to use. */ | |
8990 | ||
47926f60 | 8991 | const char * |
e3bb37b5 | 8992 | i386_target_format (void) |
252b5132 | 8993 | { |
351f65ca L |
8994 | if (!strncmp (default_arch, "x86_64", 6)) |
8995 | { | |
8996 | update_code_flag (CODE_64BIT, 1); | |
8997 | if (default_arch[6] == '\0') | |
7f56bc95 | 8998 | x86_elf_abi = X86_64_ABI; |
351f65ca | 8999 | else |
7f56bc95 | 9000 | x86_elf_abi = X86_64_X32_ABI; |
351f65ca | 9001 | } |
3e73aa7c | 9002 | else if (!strcmp (default_arch, "i386")) |
78f12dd3 | 9003 | update_code_flag (CODE_32BIT, 1); |
3e73aa7c | 9004 | else |
2b5d6a91 | 9005 | as_fatal (_("unknown architecture")); |
89507696 JB |
9006 | |
9007 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) | |
9008 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
9009 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) | |
9010 | cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
9011 | ||
252b5132 RH |
9012 | switch (OUTPUT_FLAVOR) |
9013 | { | |
9384f2ff | 9014 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
4c63da97 | 9015 | case bfd_target_aout_flavour: |
47926f60 | 9016 | return AOUT_TARGET_FORMAT; |
4c63da97 | 9017 | #endif |
9384f2ff AM |
9018 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
9019 | # if defined (TE_PE) || defined (TE_PEP) | |
9020 | case bfd_target_coff_flavour: | |
9021 | return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386"; | |
9022 | # elif defined (TE_GO32) | |
0561d57c JK |
9023 | case bfd_target_coff_flavour: |
9024 | return "coff-go32"; | |
9384f2ff | 9025 | # else |
252b5132 RH |
9026 | case bfd_target_coff_flavour: |
9027 | return "coff-i386"; | |
9384f2ff | 9028 | # endif |
4c63da97 | 9029 | #endif |
3e73aa7c | 9030 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 9031 | case bfd_target_elf_flavour: |
3e73aa7c | 9032 | { |
351f65ca L |
9033 | const char *format; |
9034 | ||
9035 | switch (x86_elf_abi) | |
4fa24527 | 9036 | { |
351f65ca L |
9037 | default: |
9038 | format = ELF_TARGET_FORMAT; | |
9039 | break; | |
7f56bc95 | 9040 | case X86_64_ABI: |
351f65ca | 9041 | use_rela_relocations = 1; |
4fa24527 | 9042 | object_64bit = 1; |
351f65ca L |
9043 | format = ELF_TARGET_FORMAT64; |
9044 | break; | |
7f56bc95 | 9045 | case X86_64_X32_ABI: |
4fa24527 | 9046 | use_rela_relocations = 1; |
351f65ca | 9047 | object_64bit = 1; |
862be3fb | 9048 | disallow_64bit_reloc = 1; |
351f65ca L |
9049 | format = ELF_TARGET_FORMAT32; |
9050 | break; | |
4fa24527 | 9051 | } |
3632d14b | 9052 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 9053 | { |
7f56bc95 | 9054 | if (x86_elf_abi != X86_64_ABI) |
8a9036a4 L |
9055 | as_fatal (_("Intel L1OM is 64bit only")); |
9056 | return ELF_TARGET_L1OM_FORMAT; | |
9057 | } | |
7a9068fe L |
9058 | if (cpu_arch_isa == PROCESSOR_K1OM) |
9059 | { | |
9060 | if (x86_elf_abi != X86_64_ABI) | |
9061 | as_fatal (_("Intel K1OM is 64bit only")); | |
9062 | return ELF_TARGET_K1OM_FORMAT; | |
9063 | } | |
8a9036a4 | 9064 | else |
351f65ca | 9065 | return format; |
3e73aa7c | 9066 | } |
e57f8c65 TG |
9067 | #endif |
9068 | #if defined (OBJ_MACH_O) | |
9069 | case bfd_target_mach_o_flavour: | |
d382c579 TG |
9070 | if (flag_code == CODE_64BIT) |
9071 | { | |
9072 | use_rela_relocations = 1; | |
9073 | object_64bit = 1; | |
9074 | return "mach-o-x86-64"; | |
9075 | } | |
9076 | else | |
9077 | return "mach-o-i386"; | |
4c63da97 | 9078 | #endif |
252b5132 RH |
9079 | default: |
9080 | abort (); | |
9081 | return NULL; | |
9082 | } | |
9083 | } | |
9084 | ||
47926f60 | 9085 | #endif /* OBJ_MAYBE_ more than one */ |
a847613f AM |
9086 | |
9087 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) | |
e3bb37b5 L |
9088 | void |
9089 | i386_elf_emit_arch_note (void) | |
a847613f | 9090 | { |
718ddfc0 | 9091 | if (IS_ELF && cpu_arch_name != NULL) |
a847613f AM |
9092 | { |
9093 | char *p; | |
9094 | asection *seg = now_seg; | |
9095 | subsegT subseg = now_subseg; | |
9096 | Elf_Internal_Note i_note; | |
9097 | Elf_External_Note e_note; | |
9098 | asection *note_secp; | |
9099 | int len; | |
9100 | ||
9101 | /* Create the .note section. */ | |
9102 | note_secp = subseg_new (".note", 0); | |
9103 | bfd_set_section_flags (stdoutput, | |
9104 | note_secp, | |
9105 | SEC_HAS_CONTENTS | SEC_READONLY); | |
9106 | ||
9107 | /* Process the arch string. */ | |
9108 | len = strlen (cpu_arch_name); | |
9109 | ||
9110 | i_note.namesz = len + 1; | |
9111 | i_note.descsz = 0; | |
9112 | i_note.type = NT_ARCH; | |
9113 | p = frag_more (sizeof (e_note.namesz)); | |
9114 | md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz)); | |
9115 | p = frag_more (sizeof (e_note.descsz)); | |
9116 | md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz)); | |
9117 | p = frag_more (sizeof (e_note.type)); | |
9118 | md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type)); | |
9119 | p = frag_more (len + 1); | |
9120 | strcpy (p, cpu_arch_name); | |
9121 | ||
9122 | frag_align (2, 0, 0); | |
9123 | ||
9124 | subseg_set (seg, subseg); | |
9125 | } | |
9126 | } | |
9127 | #endif | |
252b5132 | 9128 | \f |
252b5132 | 9129 | symbolS * |
7016a5d5 | 9130 | md_undefined_symbol (char *name) |
252b5132 | 9131 | { |
18dc2407 ILT |
9132 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
9133 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
9134 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
9135 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
9136 | { |
9137 | if (!GOT_symbol) | |
9138 | { | |
9139 | if (symbol_find (name)) | |
9140 | as_bad (_("GOT already in symbol table")); | |
9141 | GOT_symbol = symbol_new (name, undefined_section, | |
9142 | (valueT) 0, &zero_address_frag); | |
9143 | }; | |
9144 | return GOT_symbol; | |
9145 | } | |
252b5132 RH |
9146 | return 0; |
9147 | } | |
9148 | ||
9149 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 9150 | |
252b5132 | 9151 | valueT |
7016a5d5 | 9152 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 | 9153 | { |
4c63da97 AM |
9154 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
9155 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
9156 | { | |
9157 | /* For a.out, force the section size to be aligned. If we don't do | |
9158 | this, BFD will align it for us, but it will not write out the | |
9159 | final bytes of the section. This may be a bug in BFD, but it is | |
9160 | easier to fix it here since that is how the other a.out targets | |
9161 | work. */ | |
9162 | int align; | |
9163 | ||
9164 | align = bfd_get_section_alignment (stdoutput, segment); | |
9165 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
9166 | } | |
252b5132 RH |
9167 | #endif |
9168 | ||
9169 | return size; | |
9170 | } | |
9171 | ||
9172 | /* On the i386, PC-relative offsets are relative to the start of the | |
9173 | next instruction. That is, the address of the offset, plus its | |
9174 | size, since the offset is always the last part of the insn. */ | |
9175 | ||
9176 | long | |
e3bb37b5 | 9177 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
9178 | { |
9179 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
9180 | } | |
9181 | ||
9182 | #ifndef I386COFF | |
9183 | ||
9184 | static void | |
e3bb37b5 | 9185 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 9186 | { |
29b0f896 | 9187 | int temp; |
252b5132 | 9188 | |
8a75718c JB |
9189 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
9190 | if (IS_ELF) | |
9191 | obj_elf_section_change_hook (); | |
9192 | #endif | |
252b5132 RH |
9193 | temp = get_absolute_expression (); |
9194 | subseg_set (bss_section, (subsegT) temp); | |
9195 | demand_empty_rest_of_line (); | |
9196 | } | |
9197 | ||
9198 | #endif | |
9199 | ||
252b5132 | 9200 | void |
e3bb37b5 | 9201 | i386_validate_fix (fixS *fixp) |
252b5132 RH |
9202 | { |
9203 | if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) | |
9204 | { | |
23df1078 JH |
9205 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
9206 | { | |
4fa24527 | 9207 | if (!object_64bit) |
23df1078 JH |
9208 | abort (); |
9209 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
9210 | } | |
9211 | else | |
9212 | { | |
4fa24527 | 9213 | if (!object_64bit) |
d6ab8113 JB |
9214 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; |
9215 | else | |
9216 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
23df1078 | 9217 | } |
252b5132 RH |
9218 | fixp->fx_subsy = 0; |
9219 | } | |
9220 | } | |
9221 | ||
252b5132 | 9222 | arelent * |
7016a5d5 | 9223 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
9224 | { |
9225 | arelent *rel; | |
9226 | bfd_reloc_code_real_type code; | |
9227 | ||
9228 | switch (fixp->fx_r_type) | |
9229 | { | |
3e73aa7c JH |
9230 | case BFD_RELOC_X86_64_PLT32: |
9231 | case BFD_RELOC_X86_64_GOT32: | |
9232 | case BFD_RELOC_X86_64_GOTPCREL: | |
252b5132 RH |
9233 | case BFD_RELOC_386_PLT32: |
9234 | case BFD_RELOC_386_GOT32: | |
9235 | case BFD_RELOC_386_GOTOFF: | |
9236 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
9237 | case BFD_RELOC_386_TLS_GD: |
9238 | case BFD_RELOC_386_TLS_LDM: | |
9239 | case BFD_RELOC_386_TLS_LDO_32: | |
9240 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
9241 | case BFD_RELOC_386_TLS_IE: |
9242 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
9243 | case BFD_RELOC_386_TLS_LE_32: |
9244 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
9245 | case BFD_RELOC_386_TLS_GOTDESC: |
9246 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
9247 | case BFD_RELOC_X86_64_TLSGD: |
9248 | case BFD_RELOC_X86_64_TLSLD: | |
9249 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 9250 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
9251 | case BFD_RELOC_X86_64_GOTTPOFF: |
9252 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
9253 | case BFD_RELOC_X86_64_TPOFF64: |
9254 | case BFD_RELOC_X86_64_GOTOFF64: | |
9255 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
9256 | case BFD_RELOC_X86_64_GOT64: |
9257 | case BFD_RELOC_X86_64_GOTPCREL64: | |
9258 | case BFD_RELOC_X86_64_GOTPC64: | |
9259 | case BFD_RELOC_X86_64_GOTPLT64: | |
9260 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
9261 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
9262 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
9263 | case BFD_RELOC_RVA: |
9264 | case BFD_RELOC_VTABLE_ENTRY: | |
9265 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
9266 | #ifdef TE_PE |
9267 | case BFD_RELOC_32_SECREL: | |
9268 | #endif | |
252b5132 RH |
9269 | code = fixp->fx_r_type; |
9270 | break; | |
dbbaec26 L |
9271 | case BFD_RELOC_X86_64_32S: |
9272 | if (!fixp->fx_pcrel) | |
9273 | { | |
9274 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
9275 | code = fixp->fx_r_type; | |
9276 | break; | |
9277 | } | |
252b5132 | 9278 | default: |
93382f6d | 9279 | if (fixp->fx_pcrel) |
252b5132 | 9280 | { |
93382f6d AM |
9281 | switch (fixp->fx_size) |
9282 | { | |
9283 | default: | |
b091f402 AM |
9284 | as_bad_where (fixp->fx_file, fixp->fx_line, |
9285 | _("can not do %d byte pc-relative relocation"), | |
9286 | fixp->fx_size); | |
93382f6d AM |
9287 | code = BFD_RELOC_32_PCREL; |
9288 | break; | |
9289 | case 1: code = BFD_RELOC_8_PCREL; break; | |
9290 | case 2: code = BFD_RELOC_16_PCREL; break; | |
9291 | case 4: code = BFD_RELOC_32_PCREL; break; | |
d6ab8113 JB |
9292 | #ifdef BFD64 |
9293 | case 8: code = BFD_RELOC_64_PCREL; break; | |
9294 | #endif | |
93382f6d AM |
9295 | } |
9296 | } | |
9297 | else | |
9298 | { | |
9299 | switch (fixp->fx_size) | |
9300 | { | |
9301 | default: | |
b091f402 AM |
9302 | as_bad_where (fixp->fx_file, fixp->fx_line, |
9303 | _("can not do %d byte relocation"), | |
9304 | fixp->fx_size); | |
93382f6d AM |
9305 | code = BFD_RELOC_32; |
9306 | break; | |
9307 | case 1: code = BFD_RELOC_8; break; | |
9308 | case 2: code = BFD_RELOC_16; break; | |
9309 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 9310 | #ifdef BFD64 |
3e73aa7c | 9311 | case 8: code = BFD_RELOC_64; break; |
937149dd | 9312 | #endif |
93382f6d | 9313 | } |
252b5132 RH |
9314 | } |
9315 | break; | |
9316 | } | |
252b5132 | 9317 | |
d182319b JB |
9318 | if ((code == BFD_RELOC_32 |
9319 | || code == BFD_RELOC_32_PCREL | |
9320 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
9321 | && GOT_symbol |
9322 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 9323 | { |
4fa24527 | 9324 | if (!object_64bit) |
d6ab8113 JB |
9325 | code = BFD_RELOC_386_GOTPC; |
9326 | else | |
9327 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 9328 | } |
7b81dfbb AJ |
9329 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
9330 | && GOT_symbol | |
9331 | && fixp->fx_addsy == GOT_symbol) | |
9332 | { | |
9333 | code = BFD_RELOC_X86_64_GOTPC64; | |
9334 | } | |
252b5132 RH |
9335 | |
9336 | rel = (arelent *) xmalloc (sizeof (arelent)); | |
49309057 ILT |
9337 | rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
9338 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
9339 | |
9340 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 9341 | |
3e73aa7c JH |
9342 | if (!use_rela_relocations) |
9343 | { | |
9344 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
9345 | vtable entry to be used in the relocation's section offset. */ | |
9346 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
9347 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
9348 | #if defined (OBJ_COFF) && defined (TE_PE) |
9349 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
9350 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
9351 | else | |
9352 | #endif | |
c6682705 | 9353 | rel->addend = 0; |
3e73aa7c JH |
9354 | } |
9355 | /* Use the rela in 64bit mode. */ | |
252b5132 | 9356 | else |
3e73aa7c | 9357 | { |
862be3fb L |
9358 | if (disallow_64bit_reloc) |
9359 | switch (code) | |
9360 | { | |
862be3fb L |
9361 | case BFD_RELOC_X86_64_DTPOFF64: |
9362 | case BFD_RELOC_X86_64_TPOFF64: | |
9363 | case BFD_RELOC_64_PCREL: | |
9364 | case BFD_RELOC_X86_64_GOTOFF64: | |
9365 | case BFD_RELOC_X86_64_GOT64: | |
9366 | case BFD_RELOC_X86_64_GOTPCREL64: | |
9367 | case BFD_RELOC_X86_64_GOTPC64: | |
9368 | case BFD_RELOC_X86_64_GOTPLT64: | |
9369 | case BFD_RELOC_X86_64_PLTOFF64: | |
9370 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
9371 | _("cannot represent relocation type %s in x32 mode"), | |
9372 | bfd_get_reloc_code_name (code)); | |
9373 | break; | |
9374 | default: | |
9375 | break; | |
9376 | } | |
9377 | ||
062cd5e7 AS |
9378 | if (!fixp->fx_pcrel) |
9379 | rel->addend = fixp->fx_offset; | |
9380 | else | |
9381 | switch (code) | |
9382 | { | |
9383 | case BFD_RELOC_X86_64_PLT32: | |
9384 | case BFD_RELOC_X86_64_GOT32: | |
9385 | case BFD_RELOC_X86_64_GOTPCREL: | |
bffbf940 JJ |
9386 | case BFD_RELOC_X86_64_TLSGD: |
9387 | case BFD_RELOC_X86_64_TLSLD: | |
9388 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
9389 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
9390 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
9391 | rel->addend = fixp->fx_offset - fixp->fx_size; |
9392 | break; | |
9393 | default: | |
9394 | rel->addend = (section->vma | |
9395 | - fixp->fx_size | |
9396 | + fixp->fx_addnumber | |
9397 | + md_pcrel_from (fixp)); | |
9398 | break; | |
9399 | } | |
3e73aa7c JH |
9400 | } |
9401 | ||
252b5132 RH |
9402 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
9403 | if (rel->howto == NULL) | |
9404 | { | |
9405 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 9406 | _("cannot represent relocation type %s"), |
252b5132 RH |
9407 | bfd_get_reloc_code_name (code)); |
9408 | /* Set howto to a garbage value so that we can keep going. */ | |
9409 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 9410 | gas_assert (rel->howto != NULL); |
252b5132 RH |
9411 | } |
9412 | ||
9413 | return rel; | |
9414 | } | |
9415 | ||
ee86248c | 9416 | #include "tc-i386-intel.c" |
54cfded0 | 9417 | |
a60de03c JB |
9418 | void |
9419 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 9420 | { |
a60de03c JB |
9421 | int saved_naked_reg; |
9422 | char saved_register_dot; | |
54cfded0 | 9423 | |
a60de03c JB |
9424 | saved_naked_reg = allow_naked_reg; |
9425 | allow_naked_reg = 1; | |
9426 | saved_register_dot = register_chars['.']; | |
9427 | register_chars['.'] = '.'; | |
9428 | allow_pseudo_reg = 1; | |
9429 | expression_and_evaluate (exp); | |
9430 | allow_pseudo_reg = 0; | |
9431 | register_chars['.'] = saved_register_dot; | |
9432 | allow_naked_reg = saved_naked_reg; | |
9433 | ||
e96d56a1 | 9434 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
54cfded0 | 9435 | { |
a60de03c JB |
9436 | if ((addressT) exp->X_add_number < i386_regtab_size) |
9437 | { | |
9438 | exp->X_op = O_constant; | |
9439 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
9440 | .dw2_regnum[flag_code >> 1]; | |
9441 | } | |
9442 | else | |
9443 | exp->X_op = O_illegal; | |
54cfded0 | 9444 | } |
54cfded0 AM |
9445 | } |
9446 | ||
9447 | void | |
9448 | tc_x86_frame_initial_instructions (void) | |
9449 | { | |
a60de03c JB |
9450 | static unsigned int sp_regno[2]; |
9451 | ||
9452 | if (!sp_regno[flag_code >> 1]) | |
9453 | { | |
9454 | char *saved_input = input_line_pointer; | |
9455 | char sp[][4] = {"esp", "rsp"}; | |
9456 | expressionS exp; | |
a4447b93 | 9457 | |
a60de03c JB |
9458 | input_line_pointer = sp[flag_code >> 1]; |
9459 | tc_x86_parse_to_dw2regnum (&exp); | |
9c2799c2 | 9460 | gas_assert (exp.X_op == O_constant); |
a60de03c JB |
9461 | sp_regno[flag_code >> 1] = exp.X_add_number; |
9462 | input_line_pointer = saved_input; | |
9463 | } | |
a4447b93 | 9464 | |
61ff971f L |
9465 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
9466 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 9467 | } |
d2b2c203 | 9468 | |
d7921315 L |
9469 | int |
9470 | x86_dwarf2_addr_size (void) | |
9471 | { | |
9472 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
9473 | if (x86_elf_abi == X86_64_X32_ABI) | |
9474 | return 4; | |
9475 | #endif | |
9476 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
9477 | } | |
9478 | ||
d2b2c203 DJ |
9479 | int |
9480 | i386_elf_section_type (const char *str, size_t len) | |
9481 | { | |
9482 | if (flag_code == CODE_64BIT | |
9483 | && len == sizeof ("unwind") - 1 | |
9484 | && strncmp (str, "unwind", 6) == 0) | |
9485 | return SHT_X86_64_UNWIND; | |
9486 | ||
9487 | return -1; | |
9488 | } | |
bb41ade5 | 9489 | |
ad5fec3b EB |
9490 | #ifdef TE_SOLARIS |
9491 | void | |
9492 | i386_solaris_fix_up_eh_frame (segT sec) | |
9493 | { | |
9494 | if (flag_code == CODE_64BIT) | |
9495 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
9496 | } | |
9497 | #endif | |
9498 | ||
bb41ade5 AM |
9499 | #ifdef TE_PE |
9500 | void | |
9501 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
9502 | { | |
91d6fa6a | 9503 | expressionS exp; |
bb41ade5 | 9504 | |
91d6fa6a NC |
9505 | exp.X_op = O_secrel; |
9506 | exp.X_add_symbol = symbol; | |
9507 | exp.X_add_number = 0; | |
9508 | emit_expr (&exp, size); | |
bb41ade5 AM |
9509 | } |
9510 | #endif | |
3b22753a L |
9511 | |
9512 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
9513 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
9514 | ||
01e1a5bc | 9515 | bfd_vma |
3b22753a L |
9516 | x86_64_section_letter (int letter, char **ptr_msg) |
9517 | { | |
9518 | if (flag_code == CODE_64BIT) | |
9519 | { | |
9520 | if (letter == 'l') | |
9521 | return SHF_X86_64_LARGE; | |
9522 | ||
8f3bae45 | 9523 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
64e74474 | 9524 | } |
3b22753a | 9525 | else |
8f3bae45 | 9526 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
9527 | return -1; |
9528 | } | |
9529 | ||
01e1a5bc | 9530 | bfd_vma |
3b22753a L |
9531 | x86_64_section_word (char *str, size_t len) |
9532 | { | |
8620418b | 9533 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
3b22753a L |
9534 | return SHF_X86_64_LARGE; |
9535 | ||
9536 | return -1; | |
9537 | } | |
9538 | ||
9539 | static void | |
9540 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
9541 | { | |
9542 | if (flag_code != CODE_64BIT) | |
9543 | { | |
9544 | s_comm_internal (0, elf_common_parse); | |
9545 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
9546 | } | |
9547 | else | |
9548 | { | |
9549 | static segT lbss_section; | |
9550 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
9551 | asection *saved_bss_section = bss_section; | |
9552 | ||
9553 | if (lbss_section == NULL) | |
9554 | { | |
9555 | flagword applicable; | |
9556 | segT seg = now_seg; | |
9557 | subsegT subseg = now_subseg; | |
9558 | ||
9559 | /* The .lbss section is for local .largecomm symbols. */ | |
9560 | lbss_section = subseg_new (".lbss", 0); | |
9561 | applicable = bfd_applicable_section_flags (stdoutput); | |
9562 | bfd_set_section_flags (stdoutput, lbss_section, | |
9563 | applicable & SEC_ALLOC); | |
9564 | seg_info (lbss_section)->bss = 1; | |
9565 | ||
9566 | subseg_set (seg, subseg); | |
9567 | } | |
9568 | ||
9569 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
9570 | bss_section = lbss_section; | |
9571 | ||
9572 | s_comm_internal (0, elf_common_parse); | |
9573 | ||
9574 | elf_com_section_ptr = saved_com_section_ptr; | |
9575 | bss_section = saved_bss_section; | |
9576 | } | |
9577 | } | |
9578 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |