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* hppa.h (pa_opcodes): Replace 'f' by 'v'. Prefix float register args
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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252b5132
RH		 1/* i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 1999
3 Free Software Foundation.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
21
22/*
23 Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better.
27 */
28
29#include <ctype.h>
30
31#include "as.h"
32#include "subsegs.h"
33#include "opcode/i386.h"
34
35#ifndef TC_RELOC
36#define TC_RELOC(X,Y) (Y)
37#endif
38
39#ifndef REGISTER_WARNINGS
40#define REGISTER_WARNINGS 1
41#endif
42
c3332e24 43#ifndef INFER_ADDR_PREFIX
eecb386c 44#define INFER_ADDR_PREFIX 1
c3332e24
AM		 45#endif
46
252b5132
RH		 47#ifndef SCALE1_WHEN_NO_INDEX
48/* Specifying a scale factor besides 1 when there is no index is
49 futile. eg. `mov (%ebx,2),%al' does exactly the same as
50 `mov (%ebx),%al'. To slavishly follow what the programmer
51 specified, set SCALE1_WHEN_NO_INDEX to 0. */
52#define SCALE1_WHEN_NO_INDEX 1
53#endif
54
55#define true 1
56#define false 0
57
58static unsigned int mode_from_disp_size PARAMS ((unsigned int));
59static int fits_in_signed_byte PARAMS ((long));
60static int fits_in_unsigned_byte PARAMS ((long));
61static int fits_in_unsigned_word PARAMS ((long));
62static int fits_in_signed_word PARAMS ((long));
63static int smallest_imm_type PARAMS ((long));
64static int add_prefix PARAMS ((unsigned int));
65static void set_16bit_code_flag PARAMS ((int));
eecb386c 66static void set_16bit_gcc_code_flag PARAMS((int));
252b5132
RH		 67static void set_intel_syntax PARAMS ((int));
68
69#ifdef BFD_ASSEMBLER
70static bfd_reloc_code_real_type reloc
71 PARAMS ((int, int, bfd_reloc_code_real_type));
72#endif
73
74/* 'md_assemble ()' gathers together information and puts it into a
75 i386_insn. */
76
77struct _i386_insn
78 {
79 /* TM holds the template for the insn were currently assembling. */
80 template tm;
81
82 /* SUFFIX holds the instruction mnemonic suffix if given.
83 (e.g. 'l' for 'movl') */
84 char suffix;
85
86 /* Operands are coded with OPERANDS, TYPES, DISPS, IMMS, and REGS. */
87
88 /* OPERANDS gives the number of given operands. */
89 unsigned int operands;
90
91 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
92 of given register, displacement, memory operands and immediate
93 operands. */
94 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
95
96 /* TYPES [i] is the type (see above #defines) which tells us how to
97 search through DISPS [i] & IMMS [i] & REGS [i] for the required
98 operand. */
99 unsigned int types[MAX_OPERANDS];
100
101 /* Displacements (if given) for each operand. */
102 expressionS *disps[MAX_OPERANDS];
103
104 /* Relocation type for operand */
105#ifdef BFD_ASSEMBLER
106 enum bfd_reloc_code_real disp_reloc[MAX_OPERANDS];
107#else
108 int disp_reloc[MAX_OPERANDS];
109#endif
110
111 /* Immediate operands (if given) for each operand. */
112 expressionS *imms[MAX_OPERANDS];
113
114 /* Register operands (if given) for each operand. */
115 const reg_entry *regs[MAX_OPERANDS];
116
117 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
118 the base index byte below. */
119 const reg_entry *base_reg;
120 const reg_entry *index_reg;
121 unsigned int log2_scale_factor;
122
123 /* SEG gives the seg_entries of this insn. They are zero unless
124 explicit segment overrides are given. */
125 const seg_entry *seg[2]; /* segments for memory operands (if given) */
126
127 /* PREFIX holds all the given prefix opcodes (usually null).
128 PREFIXES is the number of prefix opcodes. */
129 unsigned int prefixes;
130 unsigned char prefix[MAX_PREFIXES];
131
132 /* RM and SIB are the modrm byte and the sib byte where the
133 addressing modes of this insn are encoded. */
134
135 modrm_byte rm;
136 sib_byte sib;
137 };
138
139typedef struct _i386_insn i386_insn;
140
141/* List of chars besides those in app.c:symbol_chars that can start an
142 operand. Used to prevent the scrubber eating vital white-space. */
143#ifdef LEX_AT
144const char extra_symbol_chars[] = "*%-(@";
145#else
146const char extra_symbol_chars[] = "*%-(";
147#endif
148
149/* This array holds the chars that always start a comment. If the
150 pre-processor is disabled, these aren't very useful */
151#if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX))
152/* Putting '/' here makes it impossible to use the divide operator.
153 However, we need it for compatibility with SVR4 systems. */
154const char comment_chars[] = "#/";
155#define PREFIX_SEPARATOR '\\'
156#else
157const char comment_chars[] = "#";
158#define PREFIX_SEPARATOR '/'
159#endif
160
161/* This array holds the chars that only start a comment at the beginning of
162 a line. If the line seems to have the form '# 123 filename'
163 .line and .file directives will appear in the pre-processed output */
164/* Note that input_file.c hand checks for '#' at the beginning of the
165 first line of the input file. This is because the compiler outputs
166 #NO_APP at the beginning of its output. */
167/* Also note that comments started like this one will always work if
168 '/' isn't otherwise defined. */
169#if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX))
170const char line_comment_chars[] = "";
171#else
172const char line_comment_chars[] = "/";
173#endif
174
175const char line_separator_chars[] = "";
176
177/* Chars that can be used to separate mant from exp in floating point nums */
178const char EXP_CHARS[] = "eE";
179
180/* Chars that mean this number is a floating point constant */
181/* As in 0f12.456 */
182/* or 0d1.2345e12 */
183const char FLT_CHARS[] = "fFdDxX";
184
185/* tables for lexical analysis */
186static char mnemonic_chars[256];
187static char register_chars[256];
188static char operand_chars[256];
189static char identifier_chars[256];
190static char digit_chars[256];
191
192/* lexical macros */
193#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
194#define is_operand_char(x) (operand_chars[(unsigned char) x])
195#define is_register_char(x) (register_chars[(unsigned char) x])
196#define is_space_char(x) ((x) == ' ')
197#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
198#define is_digit_char(x) (digit_chars[(unsigned char) x])
199
200/* put here all non-digit non-letter charcters that may occur in an operand */
201static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
202
203/* md_assemble() always leaves the strings it's passed unaltered. To
204 effect this we maintain a stack of saved characters that we've smashed
205 with '\0's (indicating end of strings for various sub-fields of the
206 assembler instruction). */
207static char save_stack[32];
208static char *save_stack_p; /* stack pointer */
209#define END_STRING_AND_SAVE(s) \
210 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
211#define RESTORE_END_STRING(s) \
212 do { *(s) = *--save_stack_p; } while (0)
213
214/* The instruction we're assembling. */
215static i386_insn i;
216
217/* Possible templates for current insn. */
218static const templates *current_templates;
219
220/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
221static expressionS disp_expressions[2], im_expressions[2];
222
223static int this_operand; /* current operand we are working on */
224
225static int flag_do_long_jump; /* FIXME what does this do? */
226
227static int flag_16bit_code; /* 1 if we're writing 16-bit code, 0 if 32-bit */
228
229static int intel_syntax = 0; /* 1 for intel syntax, 0 if att syntax */
230
231static int allow_naked_reg = 0; /* 1 if register prefix % not required */
232
eecb386c
AM		 233static char stackop_size = '\0'; /* Used in 16 bit gcc mode to add an l
234 suffix to call, ret, enter, leave, push,
235 and pop instructions. */
236
252b5132
RH		 237/* Interface to relax_segment.
238 There are 2 relax states for 386 jump insns: one for conditional &
239 one for unconditional jumps. This is because the these two types
240 of jumps add different sizes to frags when we're figuring out what
241 sort of jump to choose to reach a given label. */
242
243/* types */
244#define COND_JUMP 1 /* conditional jump */
245#define UNCOND_JUMP 2 /* unconditional jump */
246/* sizes */
247#define CODE16 1
248#define SMALL 0
249#define SMALL16 (SMALL|CODE16)
250#define BIG 2
251#define BIG16 (BIG|CODE16)
252
253#ifndef INLINE
254#ifdef __GNUC__
255#define INLINE __inline__
256#else
257#define INLINE
258#endif
259#endif
260
261#define ENCODE_RELAX_STATE(type,size) \
262 ((relax_substateT)((type<<2) | (size)))
263#define SIZE_FROM_RELAX_STATE(s) \
264 ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) )
265
266/* This table is used by relax_frag to promote short jumps to long
267 ones where necessary. SMALL (short) jumps may be promoted to BIG
268 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
269 don't allow a short jump in a 32 bit code segment to be promoted to
270 a 16 bit offset jump because it's slower (requires data size
271 prefix), and doesn't work, unless the destination is in the bottom
272 64k of the code segment (The top 16 bits of eip are zeroed). */
273
274const relax_typeS md_relax_table[] =
275{
24eab124
AM		 276 /* The fields are:
277 1) most positive reach of this state,
278 2) most negative reach of this state,
279 3) how many bytes this mode will add to the size of the current frag
280 4) which index into the table to try if we can't fit into this one.
281 */
252b5132
RH		 282 {1, 1, 0, 0},
283 {1, 1, 0, 0},
284 {1, 1, 0, 0},
285 {1, 1, 0, 0},
286
287 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
288 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
289 /* dword conditionals adds 4 bytes to frag:
290 1 extra opcode byte, 3 extra displacement bytes. */
291 {0, 0, 4, 0},
292 /* word conditionals add 2 bytes to frag:
293 1 extra opcode byte, 1 extra displacement byte. */
294 {0, 0, 2, 0},
295
296 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
297 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
298 /* dword jmp adds 3 bytes to frag:
299 0 extra opcode bytes, 3 extra displacement bytes. */
300 {0, 0, 3, 0},
301 /* word jmp adds 1 byte to frag:
302 0 extra opcode bytes, 1 extra displacement byte. */
303 {0, 0, 1, 0}
304
305};
306
307
308void
309i386_align_code (fragP, count)
310 fragS *fragP;
311 int count;
312{
313 /* Various efficient no-op patterns for aligning code labels. */
314 /* Note: Don't try to assemble the instructions in the comments. */
315 /* 0L and 0w are not legal */
316 static const char f32_1[] =
317 {0x90}; /* nop */
318 static const char f32_2[] =
319 {0x89,0xf6}; /* movl %esi,%esi */
320 static const char f32_3[] =
321 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
322 static const char f32_4[] =
323 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
324 static const char f32_5[] =
325 {0x90, /* nop */
326 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
327 static const char f32_6[] =
328 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
329 static const char f32_7[] =
330 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
331 static const char f32_8[] =
332 {0x90, /* nop */
333 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
334 static const char f32_9[] =
335 {0x89,0xf6, /* movl %esi,%esi */
336 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
337 static const char f32_10[] =
338 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
339 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
340 static const char f32_11[] =
341 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
342 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
343 static const char f32_12[] =
344 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
345 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
346 static const char f32_13[] =
347 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
348 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
349 static const char f32_14[] =
350 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
351 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
352 static const char f32_15[] =
353 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
354 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 355 static const char f16_3[] =
356 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 357 static const char f16_4[] =
358 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
359 static const char f16_5[] =
360 {0x90, /* nop */
361 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
362 static const char f16_6[] =
363 {0x89,0xf6, /* mov %si,%si */
364 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
365 static const char f16_7[] =
366 {0x8d,0x74,0x00, /* lea 0(%si),%si */
367 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
368 static const char f16_8[] =
369 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
370 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
371 static const char *const f32_patt[] = {
372 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
373 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
374 };
375 static const char *const f16_patt[] = {
c3332e24 376 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 377 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
378 };
379
380 if (count > 0 && count <= 15)
381 {
382 if (flag_16bit_code)
383 {
384 memcpy(fragP->fr_literal + fragP->fr_fix,
385 f16_patt[count - 1], count);
386 if (count > 8) /* adjust jump offset */
387 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
388 }
389 else
390 memcpy(fragP->fr_literal + fragP->fr_fix,
391 f32_patt[count - 1], count);
392 fragP->fr_var = count;
393 }
394}
395
396static char *output_invalid PARAMS ((int c));
397static int i386_operand PARAMS ((char *operand_string));
398static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
399static const reg_entry *parse_register PARAMS ((char *reg_string,
400 char **end_op));
401
402#ifndef I386COFF
403static void s_bss PARAMS ((int));
404#endif
405
406symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
407
408static INLINE unsigned int
409mode_from_disp_size (t)
410 unsigned int t;
411{
412 return (t & Disp8) ? 1 : (t & (Disp16|Disp32)) ? 2 : 0;
413}
414
415static INLINE int
416fits_in_signed_byte (num)
417 long num;
418{
419 return (num >= -128) && (num <= 127);
420} /* fits_in_signed_byte() */
421
422static INLINE int
423fits_in_unsigned_byte (num)
424 long num;
425{
426 return (num & 0xff) == num;
427} /* fits_in_unsigned_byte() */
428
429static INLINE int
430fits_in_unsigned_word (num)
431 long num;
432{
433 return (num & 0xffff) == num;
434} /* fits_in_unsigned_word() */
435
436static INLINE int
437fits_in_signed_word (num)
438 long num;
439{
440 return (-32768 <= num) && (num <= 32767);
441} /* fits_in_signed_word() */
442
443static int
444smallest_imm_type (num)
445 long num;
446{
447#if 0
448 /* This code is disabled because all the Imm1 forms in the opcode table
449 are slower on the i486, and they're the versions with the implicitly
450 specified single-position displacement, which has another syntax if
451 you really want to use that form. If you really prefer to have the
452 one-byte-shorter Imm1 form despite these problems, re-enable this
453 code. */
454 if (num == 1)
455 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32;
456#endif
457 return (fits_in_signed_byte (num)
458 ? (Imm8S | Imm8 | Imm16 | Imm32)
459 : fits_in_unsigned_byte (num)
460 ? (Imm8 | Imm16 | Imm32)
461 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
462 ? (Imm16 | Imm32)
463 : (Imm32));
464} /* smallest_imm_type() */
465
466/* Returns 0 if attempting to add a prefix where one from the same
467 class already exists, 1 if non rep/repne added, 2 if rep/repne
468 added. */
469static int
470add_prefix (prefix)
471 unsigned int prefix;
472{
473 int ret = 1;
474 int q;
475
476 switch (prefix)
477 {
478 default:
479 abort ();
480
481 case CS_PREFIX_OPCODE:
482 case DS_PREFIX_OPCODE:
483 case ES_PREFIX_OPCODE:
484 case FS_PREFIX_OPCODE:
485 case GS_PREFIX_OPCODE:
486 case SS_PREFIX_OPCODE:
487 q = SEG_PREFIX;
488 break;
489
490 case REPNE_PREFIX_OPCODE:
491 case REPE_PREFIX_OPCODE:
492 ret = 2;
493 /* fall thru */
494 case LOCK_PREFIX_OPCODE:
495 q = LOCKREP_PREFIX;
496 break;
497
498 case FWAIT_OPCODE:
499 q = WAIT_PREFIX;
500 break;
501
502 case ADDR_PREFIX_OPCODE:
503 q = ADDR_PREFIX;
504 break;
505
506 case DATA_PREFIX_OPCODE:
507 q = DATA_PREFIX;
508 break;
509 }
510
511 if (i.prefix[q])
512 {
513 as_bad (_("same type of prefix used twice"));
514 return 0;
515 }
516
517 i.prefixes += 1;
518 i.prefix[q] = prefix;
519 return ret;
520}
521
522static void
523set_16bit_code_flag (new_16bit_code_flag)
eecb386c
AM		 524 int new_16bit_code_flag;
525{
526 flag_16bit_code = new_16bit_code_flag;
527 stackop_size = '\0';
528}
529
530static void
531set_16bit_gcc_code_flag (new_16bit_code_flag)
532 int new_16bit_code_flag;
252b5132
RH		 533{
534 flag_16bit_code = new_16bit_code_flag;
eecb386c 535 stackop_size = new_16bit_code_flag ? 'l' : '\0';
252b5132
RH		 536}
537
538static void
539set_intel_syntax (syntax_flag)
eecb386c 540 int syntax_flag;
252b5132
RH		 541{
542 /* Find out if register prefixing is specified. */
543 int ask_naked_reg = 0;
544
545 SKIP_WHITESPACE ();
546 if (! is_end_of_line[(unsigned char) *input_line_pointer])
547 {
548 char *string = input_line_pointer;
549 int e = get_symbol_end ();
550
551 if (strcmp(string, "prefix") == 0)
552 ask_naked_reg = 1;
553 else if (strcmp(string, "noprefix") == 0)
554 ask_naked_reg = -1;
555 else
556 as_bad (_("Bad argument to syntax directive."));
557 *input_line_pointer = e;
558 }
559 demand_empty_rest_of_line ();
c3332e24 560
252b5132
RH		 561 intel_syntax = syntax_flag;
562
563 if (ask_naked_reg == 0)
564 {
565#ifdef BFD_ASSEMBLER
566 allow_naked_reg = (intel_syntax
24eab124 567 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 568#else
569 allow_naked_reg = 0; /* conservative default */
570#endif
571 }
572 else
573 allow_naked_reg = (ask_naked_reg < 0);
574}
575
576const pseudo_typeS md_pseudo_table[] =
577{
578#ifndef I386COFF
579 {"bss", s_bss, 0},
580#endif
581#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
582 {"align", s_align_bytes, 0},
583#else
584 {"align", s_align_ptwo, 0},
585#endif
586 {"ffloat", float_cons, 'f'},
587 {"dfloat", float_cons, 'd'},
588 {"tfloat", float_cons, 'x'},
589 {"value", cons, 2},
590 {"noopt", s_ignore, 0},
591 {"optim", s_ignore, 0},
eecb386c 592 {"code16gcc", set_16bit_gcc_code_flag, 1},
252b5132
RH		 593 {"code16", set_16bit_code_flag, 1},
594 {"code32", set_16bit_code_flag, 0},
595 {"intel_syntax", set_intel_syntax, 1},
596 {"att_syntax", set_intel_syntax, 0},
597 {0, 0, 0}
598};
599
600/* for interface with expression () */
601extern char *input_line_pointer;
602
603/* hash table for instruction mnemonic lookup */
604static struct hash_control *op_hash;
605/* hash table for register lookup */
606static struct hash_control *reg_hash;
607\f
608
609void
610md_begin ()
611{
612 const char *hash_err;
613
614 /* initialize op_hash hash table */
615 op_hash = hash_new ();
616
617 {
618 register const template *optab;
619 register templates *core_optab;
620
621 optab = i386_optab; /* setup for loop */
622 core_optab = (templates *) xmalloc (sizeof (templates));
623 core_optab->start = optab;
624
625 while (1)
626 {
627 ++optab;
628 if (optab->name == NULL
629 || strcmp (optab->name, (optab - 1)->name) != 0)
630 {
631 /* different name --> ship out current template list;
632 add to hash table; & begin anew */
633 core_optab->end = optab;
634 hash_err = hash_insert (op_hash,
635 (optab - 1)->name,
636 (PTR) core_optab);
637 if (hash_err)
638 {
639 hash_error:
640 as_fatal (_("Internal Error: Can't hash %s: %s"),
641 (optab - 1)->name,
642 hash_err);
643 }
644 if (optab->name == NULL)
645 break;
646 core_optab = (templates *) xmalloc (sizeof (templates));
647 core_optab->start = optab;
648 }
649 }
650 }
651
652 /* initialize reg_hash hash table */
653 reg_hash = hash_new ();
654 {
655 register const reg_entry *regtab;
656
657 for (regtab = i386_regtab;
658 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
659 regtab++)
660 {
661 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
662 if (hash_err)
663 goto hash_error;
664 }
665 }
666
667 /* fill in lexical tables: mnemonic_chars, operand_chars. */
668 {
669 register int c;
670 register char *p;
671
672 for (c = 0; c < 256; c++)
673 {
674 if (isdigit (c))
675 {
676 digit_chars[c] = c;
677 mnemonic_chars[c] = c;
678 register_chars[c] = c;
679 operand_chars[c] = c;
680 }
681 else if (islower (c))
682 {
683 mnemonic_chars[c] = c;
684 register_chars[c] = c;
685 operand_chars[c] = c;
686 }
687 else if (isupper (c))
688 {
689 mnemonic_chars[c] = tolower (c);
690 register_chars[c] = mnemonic_chars[c];
691 operand_chars[c] = c;
692 }
693
694 if (isalpha (c) || isdigit (c))
695 identifier_chars[c] = c;
696 else if (c >= 128)
697 {
698 identifier_chars[c] = c;
699 operand_chars[c] = c;
700 }
701 }
702
703#ifdef LEX_AT
704 identifier_chars['@'] = '@';
705#endif
706 register_chars[')'] = ')';
707 register_chars['('] = '(';
708 digit_chars['-'] = '-';
709 identifier_chars['_'] = '_';
710 identifier_chars['.'] = '.';
711
712 for (p = operand_special_chars; *p != '\0'; p++)
713 operand_chars[(unsigned char) *p] = *p;
714 }
715
716#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
717 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
718 {
719 record_alignment (text_section, 2);
720 record_alignment (data_section, 2);
721 record_alignment (bss_section, 2);
722 }
723#endif
724}
725
726void
727i386_print_statistics (file)
728 FILE *file;
729{
730 hash_print_statistics (file, "i386 opcode", op_hash);
731 hash_print_statistics (file, "i386 register", reg_hash);
732}
733\f
734
735#ifdef DEBUG386
736
737/* debugging routines for md_assemble */
738static void pi PARAMS ((char *, i386_insn *));
739static void pte PARAMS ((template *));
740static void pt PARAMS ((unsigned int));
741static void pe PARAMS ((expressionS *));
742static void ps PARAMS ((symbolS *));
743
744static void
745pi (line, x)
746 char *line;
747 i386_insn *x;
748{
749 register template *p;
750 int i;
751
752 fprintf (stdout, "%s: template ", line);
753 pte (&x->tm);
754 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x",
755 x->rm.mode, x->rm.reg, x->rm.regmem);
756 fprintf (stdout, " base %x index %x scale %x\n",
757 x->bi.base, x->bi.index, x->bi.scale);
758 for (i = 0; i < x->operands; i++)
759 {
760 fprintf (stdout, " #%d: ", i + 1);
761 pt (x->types[i]);
762 fprintf (stdout, "\n");
763 if (x->types[i]
3f4438ab 764 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
252b5132
RH		 765 fprintf (stdout, "%s\n", x->regs[i]->reg_name);
766 if (x->types[i] & Imm)
767 pe (x->imms[i]);
768 if (x->types[i] & Disp)
769 pe (x->disps[i]);
770 }
771}
772
773static void
774pte (t)
775 template *t;
776{
777 int i;
778 fprintf (stdout, " %d operands ", t->operands);
779 fprintf (stdout, "opcode %x ",
780 t->base_opcode);
781 if (t->extension_opcode != None)
782 fprintf (stdout, "ext %x ", t->extension_opcode);
783 if (t->opcode_modifier & D)
784 fprintf (stdout, "D");
785 if (t->opcode_modifier & W)
786 fprintf (stdout, "W");
787 fprintf (stdout, "\n");
788 for (i = 0; i < t->operands; i++)
789 {
790 fprintf (stdout, " #%d type ", i + 1);
791 pt (t->operand_types[i]);
792 fprintf (stdout, "\n");
793 }
794}
795
796static void
797pe (e)
798 expressionS *e;
799{
24eab124 800 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 801 fprintf (stdout, " add_number %ld (%lx)\n",
802 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 803 if (e->X_add_symbol)
804 {
805 fprintf (stdout, " add_symbol ");
806 ps (e->X_add_symbol);
807 fprintf (stdout, "\n");
808 }
809 if (e->X_op_symbol)
810 {
811 fprintf (stdout, " op_symbol ");
812 ps (e->X_op_symbol);
813 fprintf (stdout, "\n");
814 }
815}
816
817static void
818ps (s)
819 symbolS *s;
820{
821 fprintf (stdout, "%s type %s%s",
822 S_GET_NAME (s),
823 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
824 segment_name (S_GET_SEGMENT (s)));
825}
826
827struct type_name
828 {
829 unsigned int mask;
830 char *tname;
831 }
832
833type_names[] =
834{
835 { Reg8, "r8" },
836 { Reg16, "r16" },
837 { Reg32, "r32" },
838 { Imm8, "i8" },
839 { Imm8S, "i8s" },
840 { Imm16, "i16" },
841 { Imm32, "i32" },
842 { Imm1, "i1" },
843 { BaseIndex, "BaseIndex" },
844 { Disp8, "d8" },
845 { Disp16, "d16" },
846 { Disp32, "d32" },
847 { InOutPortReg, "InOutPortReg" },
848 { ShiftCount, "ShiftCount" },
849 { Control, "control reg" },
850 { Test, "test reg" },
851 { Debug, "debug reg" },
852 { FloatReg, "FReg" },
853 { FloatAcc, "FAcc" },
854 { SReg2, "SReg2" },
855 { SReg3, "SReg3" },
856 { Acc, "Acc" },
857 { JumpAbsolute, "Jump Absolute" },
858 { RegMMX, "rMMX" },
3f4438ab 859 { RegXMM, "rXMM" },
252b5132
RH		 860 { EsSeg, "es" },
861 { 0, "" }
862};
863
864static void
865pt (t)
866 unsigned int t;
867{
868 register struct type_name *ty;
869
870 if (t == Unknown)
871 {
872 fprintf (stdout, _("Unknown"));
873 }
874 else
875 {
876 for (ty = type_names; ty->mask; ty++)
877 if (t & ty->mask)
878 fprintf (stdout, "%s, ", ty->tname);
879 }
880 fflush (stdout);
881}
882
883#endif /* DEBUG386 */
884\f
885int
886tc_i386_force_relocation (fixp)
887 struct fix *fixp;
888{
889#ifdef BFD_ASSEMBLER
890 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
891 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
892 return 1;
893 return 0;
894#else
895 /* For COFF */
896 return fixp->fx_r_type==7;
897#endif
898}
899
900#ifdef BFD_ASSEMBLER
901static bfd_reloc_code_real_type reloc
902 PARAMS ((int, int, bfd_reloc_code_real_type));
903
904static bfd_reloc_code_real_type
905reloc (size, pcrel, other)
906 int size;
907 int pcrel;
908 bfd_reloc_code_real_type other;
909{
910 if (other != NO_RELOC) return other;
911
912 if (pcrel)
913 {
914 switch (size)
915 {
916 case 1: return BFD_RELOC_8_PCREL;
917 case 2: return BFD_RELOC_16_PCREL;
918 case 4: return BFD_RELOC_32_PCREL;
919 }
920 as_bad (_("Can not do %d byte pc-relative relocation"), size);
921 }
922 else
923 {
924 switch (size)
925 {
926 case 1: return BFD_RELOC_8;
927 case 2: return BFD_RELOC_16;
928 case 4: return BFD_RELOC_32;
929 }
930 as_bad (_("Can not do %d byte relocation"), size);
931 }
932
933 return BFD_RELOC_NONE;
934}
935
936/*
937 * Here we decide which fixups can be adjusted to make them relative to
938 * the beginning of the section instead of the symbol. Basically we need
939 * to make sure that the dynamic relocations are done correctly, so in
940 * some cases we force the original symbol to be used.
941 */
942int
943tc_i386_fix_adjustable(fixP)
944 fixS * fixP;
945{
946#ifdef OBJ_ELF
947 /* Prevent all adjustments to global symbols. */
948 if (S_IS_EXTERN (fixP->fx_addsy))
949 return 0;
950 if (S_IS_WEAK (fixP->fx_addsy))
951 return 0;
952#endif
953 /* adjust_reloc_syms doesn't know about the GOT */
954 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
955 || fixP->fx_r_type == BFD_RELOC_386_PLT32
956 || fixP->fx_r_type == BFD_RELOC_386_GOT32
957 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
958 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
959 return 0;
960 return 1;
961}
962#else
963#define reloc(SIZE,PCREL,OTHER) 0
964#define BFD_RELOC_16 0
965#define BFD_RELOC_32 0
966#define BFD_RELOC_16_PCREL 0
967#define BFD_RELOC_32_PCREL 0
968#define BFD_RELOC_386_PLT32 0
969#define BFD_RELOC_386_GOT32 0
970#define BFD_RELOC_386_GOTOFF 0
971#endif
972
b4cac588
AM		 973static int
974intel_float_operand PARAMS ((char *mnemonic));
975
976static int
252b5132
RH		 977intel_float_operand (mnemonic)
978 char *mnemonic;
979{
980 if (mnemonic[0] == 'f' && mnemonic[1] =='i')
981 return 0;
982
983 if (mnemonic[0] == 'f')
984 return 1;
985
986 return 0;
987}
988
989/* This is the guts of the machine-dependent assembler. LINE points to a
990 machine dependent instruction. This function is supposed to emit
991 the frags/bytes it assembles to. */
992
993void
994md_assemble (line)
995 char *line;
996{
997 /* Points to template once we've found it. */
998 const template *t;
999
1000 /* Count the size of the instruction generated. */
1001 int insn_size = 0;
1002
1003 int j;
1004
1005 char mnemonic[MAX_MNEM_SIZE];
1006
1007 /* Initialize globals. */
1008 memset (&i, '\0', sizeof (i));
1009 for (j = 0; j < MAX_OPERANDS; j++)
1010 i.disp_reloc[j] = NO_RELOC;
1011 memset (disp_expressions, '\0', sizeof (disp_expressions));
1012 memset (im_expressions, '\0', sizeof (im_expressions));
1013 save_stack_p = save_stack; /* reset stack pointer */
1014
1015 /* First parse an instruction mnemonic & call i386_operand for the operands.
1016 We assume that the scrubber has arranged it so that line[0] is the valid
1017 start of a (possibly prefixed) mnemonic. */
1018 {
1019 char *l = line;
1020 char *token_start = l;
1021 char *mnem_p;
1022
1023 /* Non-zero if we found a prefix only acceptable with string insns. */
1024 const char *expecting_string_instruction = NULL;
1025
1026 while (1)
1027 {
1028 mnem_p = mnemonic;
1029 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1030 {
1031 mnem_p++;
1032 if (mnem_p >= mnemonic + sizeof (mnemonic))
1033 {
1034 as_bad (_("no such 386 instruction: `%s'"), token_start);
1035 return;
1036 }
1037 l++;
1038 }
1039 if (!is_space_char (*l)
1040 && *l != END_OF_INSN
1041 && *l != PREFIX_SEPARATOR)
1042 {
1043 as_bad (_("invalid character %s in mnemonic"),
1044 output_invalid (*l));
1045 return;
1046 }
1047 if (token_start == l)
1048 {
1049 if (*l == PREFIX_SEPARATOR)
1050 as_bad (_("expecting prefix; got nothing"));
1051 else
1052 as_bad (_("expecting mnemonic; got nothing"));
1053 return;
1054 }
1055
1056 /* Look up instruction (or prefix) via hash table. */
1057 current_templates = hash_find (op_hash, mnemonic);
1058
1059 if (*l != END_OF_INSN
1060 && (! is_space_char (*l) || l[1] != END_OF_INSN)
1061 && current_templates
1062 && (current_templates->start->opcode_modifier & IsPrefix))
1063 {
1064 /* If we are in 16-bit mode, do not allow addr16 or data16.
1065 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1066 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1067 && (((current_templates->start->opcode_modifier & Size32) != 0)
1068 ^ flag_16bit_code))
1069 {
1070 as_bad (_("redundant %s prefix"),
1071 current_templates->start->name);
1072 return;
1073 }
1074 /* Add prefix, checking for repeated prefixes. */
1075 switch (add_prefix (current_templates->start->base_opcode))
1076 {
1077 case 0:
1078 return;
1079 case 2:
1080 expecting_string_instruction =
1081 current_templates->start->name;
1082 break;
1083 }
1084 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1085 token_start = ++l;
1086 }
1087 else
1088 break;
1089 }
1090
1091 if (!current_templates)
1092 {
24eab124 1093 /* See if we can get a match by trimming off a suffix. */
252b5132
RH		 1094 switch (mnem_p[-1])
1095 {
1096 case DWORD_MNEM_SUFFIX:
1097 case WORD_MNEM_SUFFIX:
1098 case BYTE_MNEM_SUFFIX:
1099 case SHORT_MNEM_SUFFIX:
1100#if LONG_MNEM_SUFFIX != DWORD_MNEM_SUFFIX
1101 case LONG_MNEM_SUFFIX:
1102#endif
1103 i.suffix = mnem_p[-1];
1104 mnem_p[-1] = '\0';
1105 current_templates = hash_find (op_hash, mnemonic);
24eab124
AM		 1106 break;
1107
1108 /* Intel Syntax */
1109 case INTEL_DWORD_MNEM_SUFFIX:
1110 if (intel_syntax)
1111 {
1112 i.suffix = mnem_p[-1];
1113 mnem_p[-1] = '\0';
1114 current_templates = hash_find (op_hash, mnemonic);
1115 break;
1116 }
252b5132
RH		 1117 }
1118 if (!current_templates)
1119 {
1120 as_bad (_("no such 386 instruction: `%s'"), token_start);
1121 return;
1122 }
1123 }
1124
1125 /* check for rep/repne without a string instruction */
1126 if (expecting_string_instruction
1127 && !(current_templates->start->opcode_modifier & IsString))
1128 {
1129 as_bad (_("expecting string instruction after `%s'"),
1130 expecting_string_instruction);
1131 return;
1132 }
1133
1134 /* There may be operands to parse. */
1135 if (*l != END_OF_INSN)
1136 {
1137 /* parse operands */
1138
1139 /* 1 if operand is pending after ','. */
1140 unsigned int expecting_operand = 0;
1141
1142 /* Non-zero if operand parens not balanced. */
1143 unsigned int paren_not_balanced;
1144
1145 do
1146 {
1147 /* skip optional white space before operand */
1148 if (is_space_char (*l))
1149 ++l;
1150 if (!is_operand_char (*l) && *l != END_OF_INSN)
1151 {
1152 as_bad (_("invalid character %s before operand %d"),
1153 output_invalid (*l),
1154 i.operands + 1);
1155 return;
1156 }
1157 token_start = l; /* after white space */
1158 paren_not_balanced = 0;
1159 while (paren_not_balanced || *l != ',')
1160 {
1161 if (*l == END_OF_INSN)
1162 {
1163 if (paren_not_balanced)
1164 {
24eab124 1165 if (!intel_syntax)
252b5132
RH		 1166 as_bad (_("unbalanced parenthesis in operand %d."),
1167 i.operands + 1);
24eab124 1168 else
252b5132
RH		 1169 as_bad (_("unbalanced brackets in operand %d."),
1170 i.operands + 1);
1171 return;
1172 }
1173 else
1174 break; /* we are done */
1175 }
1176 else if (!is_operand_char (*l) && !is_space_char (*l))
1177 {
1178 as_bad (_("invalid character %s in operand %d"),
1179 output_invalid (*l),
1180 i.operands + 1);
1181 return;
1182 }
24eab124
AM		 1183 if (!intel_syntax)
1184 {
252b5132
RH		 1185 if (*l == '(')
1186 ++paren_not_balanced;
1187 if (*l == ')')
1188 --paren_not_balanced;
24eab124
AM		 1189 }
1190 else
1191 {
252b5132
RH		 1192 if (*l == '[')
1193 ++paren_not_balanced;
1194 if (*l == ']')
1195 --paren_not_balanced;
24eab124 1196 }
252b5132
RH		 1197 l++;
1198 }
1199 if (l != token_start)
1200 { /* yes, we've read in another operand */
1201 unsigned int operand_ok;
1202 this_operand = i.operands++;
1203 if (i.operands > MAX_OPERANDS)
1204 {
1205 as_bad (_("spurious operands; (%d operands/instruction max)"),
1206 MAX_OPERANDS);
1207 return;
1208 }
1209 /* now parse operand adding info to 'i' as we go along */
1210 END_STRING_AND_SAVE (l);
1211
24eab124
AM		 1212 if (intel_syntax)
1213 operand_ok = i386_intel_operand (token_start, intel_float_operand (mnemonic));
1214 else
1215 operand_ok = i386_operand (token_start);
252b5132
RH		 1216
1217 RESTORE_END_STRING (l); /* restore old contents */
1218 if (!operand_ok)
1219 return;
1220 }
1221 else
1222 {
1223 if (expecting_operand)
1224 {
1225 expecting_operand_after_comma:
1226 as_bad (_("expecting operand after ','; got nothing"));
1227 return;
1228 }
1229 if (*l == ',')
1230 {
1231 as_bad (_("expecting operand before ','; got nothing"));
1232 return;
1233 }
1234 }
1235
1236 /* now *l must be either ',' or END_OF_INSN */
1237 if (*l == ',')
1238 {
1239 if (*++l == END_OF_INSN)
1240 { /* just skip it, if it's \n complain */
1241 goto expecting_operand_after_comma;
1242 }
1243 expecting_operand = 1;
1244 }
1245 }
1246 while (*l != END_OF_INSN); /* until we get end of insn */
1247 }
1248 }
1249
1250 /* Now we've parsed the mnemonic into a set of templates, and have the
1251 operands at hand.
1252
1253 Next, we find a template that matches the given insn,
1254 making sure the overlap of the given operands types is consistent
1255 with the template operand types. */
1256
1257#define MATCH(overlap, given, template) \
1258 ((overlap) \
1259 && ((given) & BaseIndex) == ((overlap) & BaseIndex) \
1260 && ((given) & JumpAbsolute) == ((template) & JumpAbsolute))
1261
1262 /* If given types r0 and r1 are registers they must be of the same type
1263 unless the expected operand type register overlap is null.
1264 Note that Acc in a template matches every size of reg. */
1265#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1266 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1267 ((g0) & Reg) == ((g1) & Reg) || \
1268 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1269
1270 {
1271 register unsigned int overlap0, overlap1;
252b5132
RH		 1272 unsigned int overlap2;
1273 unsigned int found_reverse_match;
1274 int suffix_check;
1275
1276 /* All intel opcodes have reversed operands except for BOUND and ENTER */
1277 if (intel_syntax
24eab124
AM		 1278 && (strcmp (mnemonic, "enter") != 0)
1279 && (strcmp (mnemonic, "bound") != 0)
1280 && (strncmp (mnemonic, "fsub", 4) !=0)
1281 && (strncmp (mnemonic, "fdiv", 4) !=0))
252b5132 1282 {
24eab124
AM		 1283 const reg_entry *temp_reg = NULL;
1284 expressionS *temp_disp = NULL;
1285 expressionS *temp_imm = NULL;
1286 unsigned int temp_type;
1287 int xchg1 = 0;
ab9da554 1288 int xchg2 = 0;
252b5132 1289
24eab124
AM		 1290 if (i.operands == 2)
1291 {
1292 xchg1 = 0;
1293 xchg2 = 1;
1294 }
1295 else if (i.operands == 3)
1296 {
1297 xchg1 = 0;
1298 xchg2 = 2;
1299 }
1300
1301 if (i.operands > 1)
1302 {
1303 temp_type = i.types[xchg2];
1304 if (temp_type & (Reg | FloatReg))
1305 temp_reg = i.regs[xchg2];
1306 else if (temp_type & Imm)
1307 temp_imm = i.imms[xchg2];
1308 else if (temp_type & Disp)
1309 temp_disp = i.disps[xchg2];
1310
1311 i.types[xchg2] = i.types[xchg1];
1312
1313 if (i.types[xchg1] & (Reg | FloatReg))
1314 {
1315 i.regs[xchg2] = i.regs[xchg1];
1316 i.regs[xchg1] = NULL;
1317 }
1318 else if (i.types[xchg2] & Imm)
1319 {
1320 i.imms[xchg2] = i.imms[xchg1];
1321 i.imms[xchg1] = NULL;
1322 }
1323 else if (i.types[xchg2] & Disp)
1324 {
1325 i.disps[xchg2] = i.disps[xchg1];
1326 i.disps[xchg1] = NULL;
1327 }
1328
1329 if (temp_type & (Reg | FloatReg))
1330 {
1331 i.regs[xchg1] = temp_reg;
1332 if (! (i.types[xchg1] & (Reg | FloatReg)))
1333 i.regs[xchg2] = NULL;
1334 }
1335 else if (temp_type & Imm)
1336 {
1337 i.imms[xchg1] = temp_imm;
1338 if (! (i.types[xchg1] & Imm))
1339 i.imms[xchg2] = NULL;
1340 }
1341 else if (temp_type & Disp)
1342 {
1343 i.disps[xchg1] = temp_disp;
1344 if (! (i.types[xchg1] & Disp))
1345 i.disps[xchg2] = NULL;
1346 }
1347
1348 i.types[xchg1] = temp_type;
1349 }
1350 if (!strcmp(mnemonic,"jmp")
1351 || !strcmp (mnemonic, "call"))
1352 if ((i.types[0] & Reg) || i.types[0] & BaseIndex)
1353 i.types[0] |= JumpAbsolute;
1354
1355 }
252b5132
RH		 1356 overlap0 = 0;
1357 overlap1 = 0;
1358 overlap2 = 0;
1359 found_reverse_match = 0;
1360 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
1361 ? No_bSuf
1362 : (i.suffix == WORD_MNEM_SUFFIX
1363 ? No_wSuf
1364 : (i.suffix == SHORT_MNEM_SUFFIX
1365 ? No_sSuf
1366 : (i.suffix == LONG_MNEM_SUFFIX
24eab124
AM		 1367 ? No_lSuf
1368 : (i.suffix == INTEL_DWORD_MNEM_SUFFIX
1369 ? No_dSuf
1370 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX ? No_xSuf : 0))))));
252b5132
RH		 1371
1372 for (t = current_templates->start;
1373 t < current_templates->end;
1374 t++)
1375 {
1376 /* Must have right number of operands. */
1377 if (i.operands != t->operands)
1378 continue;
1379
24eab124
AM		 1380 /* For some opcodes, don't check the suffix */
1381 if (intel_syntax)
1382 {
1383 if (strcmp (t->name, "fnstcw")
1384 && strcmp (t->name, "fldcw")
1385 && (t->opcode_modifier & suffix_check))
1386 continue;
1387 }
1388 /* Must not have disallowed suffix. */
1389 else if ((t->opcode_modifier & suffix_check))
1390 continue;
252b5132
RH		 1391
1392 else if (!t->operands)
1393 break; /* 0 operands always matches */
1394
1395 overlap0 = i.types[0] & t->operand_types[0];
1396 switch (t->operands)
1397 {
1398 case 1:
1399 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
1400 continue;
1401 break;
1402 case 2:
1403 case 3:
1404 overlap1 = i.types[1] & t->operand_types[1];
1405 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
1406 || !MATCH (overlap1, i.types[1], t->operand_types[1])
1407 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
1408 t->operand_types[0],
1409 overlap1, i.types[1],
1410 t->operand_types[1]))
1411 {
1412
1413 /* check if other direction is valid ... */
1414 if ((t->opcode_modifier & (D|FloatD)) == 0)
1415 continue;
1416
1417 /* try reversing direction of operands */
1418 overlap0 = i.types[0] & t->operand_types[1];
1419 overlap1 = i.types[1] & t->operand_types[0];
1420 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
1421 || !MATCH (overlap1, i.types[1], t->operand_types[0])
1422 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
1423 t->operand_types[1],
1424 overlap1, i.types[1],
1425 t->operand_types[0]))
1426 {
1427 /* does not match either direction */
1428 continue;
1429 }
1430 /* found_reverse_match holds which of D or FloatDR
1431 we've found. */
1432 found_reverse_match = t->opcode_modifier & (D|FloatDR);
1433 break;
1434 }
1435 /* found a forward 2 operand match here */
1436 if (t->operands == 3)
1437 {
1438 /* Here we make use of the fact that there are no
1439 reverse match 3 operand instructions, and all 3
1440 operand instructions only need to be checked for
1441 register consistency between operands 2 and 3. */
1442 overlap2 = i.types[2] & t->operand_types[2];
1443 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
1444 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
1445 t->operand_types[1],
1446 overlap2, i.types[2],
24eab124 1447 t->operand_types[2]))
252b5132 1448
24eab124 1449 continue;
252b5132
RH		 1450 }
1451 /* found either forward/reverse 2 or 3 operand match here:
1452 slip through to break */
1453 }
1454 break; /* we've found a match; break out of loop */
1455 } /* for (t = ... */
1456 if (t == current_templates->end)
1457 { /* we found no match */
1458 as_bad (_("suffix or operands invalid for `%s'"),
1459 current_templates->start->name);
1460 return;
1461 }
1462
1463 if ((t->opcode_modifier & (IsPrefix|IgnoreSize)) == (IsPrefix|IgnoreSize))
1464 {
1465 /* Warn them that a data or address size prefix doesn't affect
1466 assembly of the next line of code. */
1467 as_warn (_("stand-alone `%s' prefix"), t->name);
1468 }
1469
1470 /* Copy the template we found. */
1471 i.tm = *t;
1472 if (found_reverse_match)
1473 {
1474 i.tm.operand_types[0] = t->operand_types[1];
1475 i.tm.operand_types[1] = t->operand_types[0];
1476 }
1477
1478
1479 if (i.tm.opcode_modifier & FWait)
1480 if (! add_prefix (FWAIT_OPCODE))
1481 return;
1482
1483 /* Check string instruction segment overrides */
1484 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1485 {
1486 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
1487 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
1488 {
1489 if (i.seg[0] != NULL && i.seg[0] != &es)
1490 {
1491 as_bad (_("`%s' operand %d must use `%%es' segment"),
1492 i.tm.name,
1493 mem_op + 1);
1494 return;
1495 }
1496 /* There's only ever one segment override allowed per instruction.
1497 This instruction possibly has a legal segment override on the
1498 second operand, so copy the segment to where non-string
1499 instructions store it, allowing common code. */
1500 i.seg[0] = i.seg[1];
1501 }
1502 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
1503 {
1504 if (i.seg[1] != NULL && i.seg[1] != &es)
1505 {
1506 as_bad (_("`%s' operand %d must use `%%es' segment"),
1507 i.tm.name,
1508 mem_op + 2);
1509 return;
1510 }
1511 }
1512 }
1513
1514 /* If matched instruction specifies an explicit instruction mnemonic
1515 suffix, use it. */
1516 if (i.tm.opcode_modifier & (Size16 | Size32))
1517 {
1518 if (i.tm.opcode_modifier & Size16)
1519 i.suffix = WORD_MNEM_SUFFIX;
1520 else
1521 i.suffix = DWORD_MNEM_SUFFIX;
1522 }
1523 else if (i.reg_operands)
1524 {
1525 /* If there's no instruction mnemonic suffix we try to invent one
1526 based on register operands. */
1527 if (!i.suffix)
1528 {
1529 /* We take i.suffix from the last register operand specified,
1530 Destination register type is more significant than source
1531 register type. */
1532 int op;
1533 for (op = i.operands; --op >= 0; )
1534 if (i.types[op] & Reg)
1535 {
1536 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
1537 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
1538 DWORD_MNEM_SUFFIX);
1539 break;
1540 }
1541 }
1542 else if (i.suffix == BYTE_MNEM_SUFFIX)
1543 {
1544 int op;
1545 for (op = i.operands; --op >= 0; )
1546 {
1547 /* If this is an eight bit register, it's OK. If it's
1548 the 16 or 32 bit version of an eight bit register,
1549 we will just use the low portion, and that's OK too. */
1550 if (i.types[op] & Reg8)
1551 continue;
1552
24eab124
AM		 1553 /* movzx and movsx should not generate this warning. */
1554 if (intel_syntax
1555 && (i.tm.base_opcode == 0xfb7
1556 || i.tm.base_opcode == 0xfb6
1557 || i.tm.base_opcode == 0xfbe
1558 || i.tm.base_opcode == 0xfbf))
1559 continue;
252b5132
RH		 1560
1561 if ((i.types[op] & WordReg) && i.regs[op]->reg_num < 4
1562#if 0
1563 /* Check that the template allows eight bit regs
1564 This kills insns such as `orb $1,%edx', which
1565 maybe should be allowed. */
1566 && (i.tm.operand_types[op] & (Reg8|InOutPortReg))
1567#endif
1568 )
1569 {
1570#if REGISTER_WARNINGS
1571 if ((i.tm.operand_types[op] & InOutPortReg) == 0)
1572 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1573 (i.regs[op] - (i.types[op] & Reg16 ? 8 : 16))->reg_name,
1574 i.regs[op]->reg_name,
1575 i.suffix);
1576#endif
1577 continue;
1578 }
1579 /* Any other register is bad */
3f4438ab
AM		 1580 if (i.types[op] & (Reg | RegMMX | RegXMM
1581 | SReg2 | SReg3
1582 | Control | Debug | Test
1583 | FloatReg | FloatAcc))
252b5132
RH		 1584 {
1585 as_bad (_("`%%%s' not allowed with `%s%c'"),
1586 i.regs[op]->reg_name,
1587 i.tm.name,
1588 i.suffix);
1589 return;
1590 }
1591 }
1592 }
1593 else if (i.suffix == DWORD_MNEM_SUFFIX)
1594 {
1595 int op;
1596 for (op = i.operands; --op >= 0; )
1597 /* Reject eight bit registers, except where the template
1598 requires them. (eg. movzb) */
1599 if ((i.types[op] & Reg8) != 0
1600 && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0)
1601 {
1602 as_bad (_("`%%%s' not allowed with `%s%c'"),
1603 i.regs[op]->reg_name,
1604 i.tm.name,
1605 i.suffix);
1606 return;
1607 }
1608#if REGISTER_WARNINGS
1609 /* Warn if the e prefix on a general reg is missing. */
1610 else if ((i.types[op] & Reg16) != 0
1611 && (i.tm.operand_types[op] & (Reg32|Acc)) != 0)
1612 {
1613 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1614 (i.regs[op] + 8)->reg_name,
1615 i.regs[op]->reg_name,
1616 i.suffix);
1617 }
1618#endif
1619 }
1620 else if (i.suffix == WORD_MNEM_SUFFIX)
1621 {
1622 int op;
1623 for (op = i.operands; --op >= 0; )
1624 /* Reject eight bit registers, except where the template
1625 requires them. (eg. movzb) */
1626 if ((i.types[op] & Reg8) != 0
1627 && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0)
1628 {
1629 as_bad (_("`%%%s' not allowed with `%s%c'"),
1630 i.regs[op]->reg_name,
1631 i.tm.name,
1632 i.suffix);
1633 return;
1634 }
1635#if REGISTER_WARNINGS
1636 /* Warn if the e prefix on a general reg is present. */
1637 else if ((i.types[op] & Reg32) != 0
1638 && (i.tm.operand_types[op] & (Reg16|Acc)) != 0)
1639 {
1640 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1641 (i.regs[op] - 8)->reg_name,
1642 i.regs[op]->reg_name,
1643 i.suffix);
1644 }
1645#endif
1646 }
1647 else
1648 abort();
1649 }
eecb386c
AM		 1650 else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix)
1651 {
1652 i.suffix = stackop_size;
1653 }
252b5132
RH		 1654
1655 /* Make still unresolved immediate matches conform to size of immediate
1656 given in i.suffix. Note: overlap2 cannot be an immediate! */
1657 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32))
1658 && overlap0 != Imm8 && overlap0 != Imm8S
1659 && overlap0 != Imm16 && overlap0 != Imm32)
1660 {
1661 if (i.suffix)
1662 {
24eab124
AM		 1663 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) :
1664 (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : Imm32));
252b5132
RH		 1665 }
1666 else if (overlap0 == (Imm16 | Imm32))
1667 {
24eab124 1668 overlap0 =
252b5132
RH		 1669 (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32;
1670 }
1671 else
1672 {
1673 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
1674 return;
1675 }
1676 }
1677 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32))
1678 && overlap1 != Imm8 && overlap1 != Imm8S
1679 && overlap1 != Imm16 && overlap1 != Imm32)
1680 {
1681 if (i.suffix)
1682 {
24eab124
AM		 1683 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) :
1684 (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : Imm32));
252b5132
RH		 1685 }
1686 else if (overlap1 == (Imm16 | Imm32))
1687 {
24eab124 1688 overlap1 =
252b5132
RH		 1689 (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32;
1690 }
1691 else
1692 {
1693 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
1694 return;
1695 }
1696 }
1697 assert ((overlap2 & Imm) == 0);
1698
1699 i.types[0] = overlap0;
1700 if (overlap0 & ImplicitRegister)
1701 i.reg_operands--;
1702 if (overlap0 & Imm1)
1703 i.imm_operands = 0; /* kludge for shift insns */
1704
1705 i.types[1] = overlap1;
1706 if (overlap1 & ImplicitRegister)
1707 i.reg_operands--;
1708
1709 i.types[2] = overlap2;
1710 if (overlap2 & ImplicitRegister)
1711 i.reg_operands--;
1712
1713 /* Finalize opcode. First, we change the opcode based on the operand
1714 size given by i.suffix: We need not change things for byte insns. */
1715
1716 if (!i.suffix && (i.tm.opcode_modifier & W))
1717 {
1718 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
1719 return;
1720 }
1721
1722 /* For movzx and movsx, need to check the register type */
1723 if (intel_syntax
24eab124 1724 && (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe))
252b5132 1725 if (i.suffix && i.suffix == BYTE_MNEM_SUFFIX)
24eab124
AM		 1726 {
1727 unsigned int prefix = DATA_PREFIX_OPCODE;
252b5132 1728
24eab124
AM		 1729 if ((i.regs[1]->reg_type & Reg16) != 0)
1730 if (!add_prefix (prefix))
1731 return;
1732 }
252b5132
RH		 1733
1734 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
1735 {
1736 /* It's not a byte, select word/dword operation. */
1737 if (i.tm.opcode_modifier & W)
1738 {
1739 if (i.tm.opcode_modifier & ShortForm)
1740 i.tm.base_opcode |= 8;
1741 else
1742 i.tm.base_opcode |= 1;
1743 }
1744 /* Now select between word & dword operations via the operand
1745 size prefix, except for instructions that will ignore this
1746 prefix anyway. */
1747 if (((intel_syntax && (i.suffix == INTEL_DWORD_MNEM_SUFFIX))
24eab124 1748 || i.suffix == DWORD_MNEM_SUFFIX
252b5132
RH		 1749 || i.suffix == LONG_MNEM_SUFFIX) == flag_16bit_code
1750 && !(i.tm.opcode_modifier & IgnoreSize))
1751 {
1752 unsigned int prefix = DATA_PREFIX_OPCODE;
1753 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
1754 prefix = ADDR_PREFIX_OPCODE;
1755
1756 if (! add_prefix (prefix))
1757 return;
1758 }
1759 /* Size floating point instruction. */
1760 if (i.suffix == LONG_MNEM_SUFFIX
24eab124 1761 || (intel_syntax && i.suffix == INTEL_DWORD_MNEM_SUFFIX))
252b5132
RH		 1762 {
1763 if (i.tm.opcode_modifier & FloatMF)
1764 i.tm.base_opcode ^= 4;
1765 }
252b5132
RH		 1766 }
1767
3f4438ab 1768 if (i.tm.opcode_modifier & ImmExt)
252b5132 1769 {
3f4438ab
AM		 1770 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1771 opcode suffix which is coded in the same place as an 8-bit
1772 immediate field would be. Here we fake an 8-bit immediate
1773 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132
RH		 1774
1775 expressionS *exp;
1776
1777 assert(i.imm_operands == 0 && i.operands <= 2);
1778
1779 exp = &im_expressions[i.imm_operands++];
1780 i.imms[i.operands] = exp;
1781 i.types[i.operands++] = Imm8;
1782 exp->X_op = O_constant;
1783 exp->X_add_number = i.tm.extension_opcode;
1784 i.tm.extension_opcode = None;
1785 }
1786
1787 /* For insns with operands there are more diddles to do to the opcode. */
1788 if (i.operands)
1789 {
24eab124 1790 /* Default segment register this instruction will use
252b5132
RH		 1791 for memory accesses. 0 means unknown.
1792 This is only for optimizing out unnecessary segment overrides. */
1793 const seg_entry *default_seg = 0;
1794
1795 /* If we found a reverse match we must alter the opcode
1796 direction bit. found_reverse_match holds bits to change
1797 (different for int & float insns). */
1798
1799 i.tm.base_opcode ^= found_reverse_match;
1800
1801 /* The imul $imm, %reg instruction is converted into
1802 imul $imm, %reg, %reg, and the clr %reg instruction
1803 is converted into xor %reg, %reg. */
1804 if (i.tm.opcode_modifier & regKludge)
1805 {
1806 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
1807 /* Pretend we saw the extra register operand. */
1808 i.regs[first_reg_op+1] = i.regs[first_reg_op];
1809 i.reg_operands = 2;
1810 }
1811
1812 if (i.tm.opcode_modifier & ShortForm)
1813 {
1814 /* The register or float register operand is in operand 0 or 1. */
1815 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
1816 /* Register goes in low 3 bits of opcode. */
1817 i.tm.base_opcode |= i.regs[op]->reg_num;
1818 if ((i.tm.opcode_modifier & Ugh) != 0)
1819 {
1820 /* Warn about some common errors, but press on regardless.
1821 The first case can be generated by gcc (<= 2.8.1). */
1822 if (i.operands == 2)
1823 {
1824 /* reversed arguments on faddp, fsubp, etc. */
1825 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
1826 i.regs[1]->reg_name,
1827 i.regs[0]->reg_name);
1828 }
1829 else
1830 {
1831 /* extraneous `l' suffix on fp insn */
1832 as_warn (_("translating to `%s %%%s'"), i.tm.name,
1833 i.regs[0]->reg_name);
1834 }
1835 }
1836 }
1837 else if (i.tm.opcode_modifier & Modrm)
1838 {
1839 /* The opcode is completed (modulo i.tm.extension_opcode which
1840 must be put into the modrm byte).
1841 Now, we make the modrm & index base bytes based on all the
1842 info we've collected. */
1843
1844 /* i.reg_operands MUST be the number of real register operands;
1845 implicit registers do not count. */
1846 if (i.reg_operands == 2)
1847 {
1848 unsigned int source, dest;
1849 source = ((i.types[0]
3f4438ab
AM		 1850 & (Reg | RegMMX | RegXMM
1851 | SReg2 | SReg3
1852 | Control | Debug | Test))
252b5132
RH		 1853 ? 0 : 1);
1854 dest = source + 1;
1855
252b5132 1856 i.rm.mode = 3;
3f4438ab
AM		 1857 /* One of the register operands will be encoded in the
1858 i.tm.reg field, the other in the combined i.tm.mode
1859 and i.tm.regmem fields. If no form of this
1860 instruction supports a memory destination operand,
1861 then we assume the source operand may sometimes be
1862 a memory operand and so we need to store the
1863 destination in the i.rm.reg field. */
1864 if ((i.tm.operand_types[dest] & AnyMem) == 0)
252b5132
RH		 1865 {
1866 i.rm.reg = i.regs[dest]->reg_num;
1867 i.rm.regmem = i.regs[source]->reg_num;
1868 }
1869 else
1870 {
1871 i.rm.reg = i.regs[source]->reg_num;
1872 i.rm.regmem = i.regs[dest]->reg_num;
1873 }
1874 }
1875 else
1876 { /* if it's not 2 reg operands... */
1877 if (i.mem_operands)
1878 {
1879 unsigned int fake_zero_displacement = 0;
1880 unsigned int op = ((i.types[0] & AnyMem)
1881 ? 0
1882 : (i.types[1] & AnyMem) ? 1 : 2);
1883
1884 default_seg = &ds;
1885
1886 if (! i.base_reg)
1887 {
1888 i.rm.mode = 0;
1889 if (! i.disp_operands)
1890 fake_zero_displacement = 1;
1891 if (! i.index_reg)
1892 {
1893 /* Operand is just <disp> */
1894 if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0))
1895 {
1896 i.rm.regmem = NO_BASE_REGISTER_16;
1897 i.types[op] &= ~Disp;
1898 i.types[op] |= Disp16;
1899 }
1900 else
1901 {
1902 i.rm.regmem = NO_BASE_REGISTER;
1903 i.types[op] &= ~Disp;
1904 i.types[op] |= Disp32;
1905 }
1906 }
1907 else /* ! i.base_reg && i.index_reg */
1908 {
1909 i.sib.index = i.index_reg->reg_num;
1910 i.sib.base = NO_BASE_REGISTER;
1911 i.sib.scale = i.log2_scale_factor;
1912 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
1913 i.types[op] &= ~Disp;
1914 i.types[op] |= Disp32; /* Must be 32 bit */
1915 }
1916 }
1917 else if (i.base_reg->reg_type & Reg16)
1918 {
1919 switch (i.base_reg->reg_num)
1920 {
1921 case 3: /* (%bx) */
1922 if (! i.index_reg)
1923 i.rm.regmem = 7;
1924 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
1925 i.rm.regmem = i.index_reg->reg_num - 6;
1926 break;
1927 case 5: /* (%bp) */
1928 default_seg = &ss;
1929 if (! i.index_reg)
1930 {
1931 i.rm.regmem = 6;
1932 if ((i.types[op] & Disp) == 0)
1933 {
1934 /* fake (%bp) into 0(%bp) */
1935 i.types[op] |= Disp8;
1936 fake_zero_displacement = 1;
1937 }
1938 }
1939 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
1940 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
1941 break;
1942 default: /* (%si) -> 4 or (%di) -> 5 */
1943 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
1944 }
1945 i.rm.mode = mode_from_disp_size (i.types[op]);
1946 }
1947 else /* i.base_reg and 32 bit mode */
1948 {
1949 i.rm.regmem = i.base_reg->reg_num;
1950 i.sib.base = i.base_reg->reg_num;
1951 if (i.base_reg->reg_num == EBP_REG_NUM)
1952 {
1953 default_seg = &ss;
1954 if (i.disp_operands == 0)
1955 {
1956 fake_zero_displacement = 1;
1957 i.types[op] |= Disp8;
1958 }
1959 }
1960 else if (i.base_reg->reg_num == ESP_REG_NUM)
1961 {
1962 default_seg = &ss;
1963 }
1964 i.sib.scale = i.log2_scale_factor;
1965 if (! i.index_reg)
1966 {
1967 /* <disp>(%esp) becomes two byte modrm
1968 with no index register. We've already
1969 stored the code for esp in i.rm.regmem
1970 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
1971 base register besides %esp will not use
1972 the extra modrm byte. */
1973 i.sib.index = NO_INDEX_REGISTER;
1974#if ! SCALE1_WHEN_NO_INDEX
1975 /* Another case where we force the second
1976 modrm byte. */
1977 if (i.log2_scale_factor)
1978 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
1979#endif
1980 }
1981 else
1982 {
1983 i.sib.index = i.index_reg->reg_num;
1984 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
1985 }
1986 i.rm.mode = mode_from_disp_size (i.types[op]);
1987 }
1988
1989 if (fake_zero_displacement)
1990 {
1991 /* Fakes a zero displacement assuming that i.types[op]
1992 holds the correct displacement size. */
b4cac588
AM		 1993 expressionS *exp;
1994
252b5132
RH		 1995 exp = &disp_expressions[i.disp_operands++];
1996 i.disps[op] = exp;
1997 exp->X_op = O_constant;
1998 exp->X_add_number = 0;
1999 exp->X_add_symbol = (symbolS *) 0;
2000 exp->X_op_symbol = (symbolS *) 0;
2001 }
2002 }
2003
2004 /* Fill in i.rm.reg or i.rm.regmem field with register
2005 operand (if any) based on i.tm.extension_opcode.
2006 Again, we must be careful to make sure that
2007 segment/control/debug/test/MMX registers are coded
2008 into the i.rm.reg field. */
2009 if (i.reg_operands)
2010 {
2011 unsigned int op =
2012 ((i.types[0]
3f4438ab
AM		 2013 & (Reg | RegMMX | RegXMM
2014 | SReg2 | SReg3
2015 | Control | Debug | Test))
252b5132
RH		 2016 ? 0
2017 : ((i.types[1]
3f4438ab
AM		 2018 & (Reg | RegMMX | RegXMM
2019 | SReg2 | SReg3
2020 | Control | Debug | Test))
252b5132
RH		 2021 ? 1
2022 : 2));
2023 /* If there is an extension opcode to put here, the
2024 register number must be put into the regmem field. */
2025 if (i.tm.extension_opcode != None)
2026 i.rm.regmem = i.regs[op]->reg_num;
2027 else
2028 i.rm.reg = i.regs[op]->reg_num;
2029
2030 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2031 we must set it to 3 to indicate this is a register
2032 operand in the regmem field. */
2033 if (!i.mem_operands)
2034 i.rm.mode = 3;
2035 }
2036
2037 /* Fill in i.rm.reg field with extension opcode (if any). */
2038 if (i.tm.extension_opcode != None)
2039 i.rm.reg = i.tm.extension_opcode;
2040 }
2041 }
2042 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2043 {
2044 if (i.tm.base_opcode == POP_SEG_SHORT && i.regs[0]->reg_num == 1)
2045 {
2046 as_bad (_("you can't `pop %%cs'"));
2047 return;
2048 }
2049 i.tm.base_opcode |= (i.regs[0]->reg_num << 3);
2050 }
2051 else if ((i.tm.base_opcode & ~(D|W)) == MOV_AX_DISP32)
2052 {
2053 default_seg = &ds;
2054 }
2055 else if ((i.tm.opcode_modifier & IsString) != 0)
2056 {
2057 /* For the string instructions that allow a segment override
2058 on one of their operands, the default segment is ds. */
2059 default_seg = &ds;
2060 }
2061
2062 /* If a segment was explicitly specified,
2063 and the specified segment is not the default,
2064 use an opcode prefix to select it.
2065 If we never figured out what the default segment is,
2066 then default_seg will be zero at this point,
2067 and the specified segment prefix will always be used. */
2068 if ((i.seg[0]) && (i.seg[0] != default_seg))
2069 {
2070 if (! add_prefix (i.seg[0]->seg_prefix))
2071 return;
2072 }
2073 }
2074 else if ((i.tm.opcode_modifier & Ugh) != 0)
2075 {
24eab124
AM		 2076 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2077 as_warn (_("translating to `%sp'"), i.tm.name);
252b5132
RH		 2078 }
2079 }
2080
2081 /* Handle conversion of 'int $3' --> special int3 insn. */
2082 if (i.tm.base_opcode == INT_OPCODE && i.imms[0]->X_add_number == 3)
2083 {
2084 i.tm.base_opcode = INT3_OPCODE;
2085 i.imm_operands = 0;
2086 }
2087
2088 /* We are ready to output the insn. */
2089 {
2090 register char *p;
2091
2092 /* Output jumps. */
2093 if (i.tm.opcode_modifier & Jump)
2094 {
2095 long n = (long) i.disps[0]->X_add_number;
2096 int prefix = (i.prefix[DATA_PREFIX] != 0);
2097 int code16 = 0;
2098
2099 if (prefix)
2100 {
2101 i.prefixes -= 1;
2102 code16 = CODE16;
2103 }
2104 if (flag_16bit_code)
2105 code16 ^= CODE16;
2106
2107 if (!intel_syntax && (i.prefixes != 0))
2108 as_warn (_("skipping prefixes on this instruction"));
2109
2110 if (i.disps[0]->X_op == O_constant)
2111 {
2112 if (fits_in_signed_byte (n))
2113 {
2114 insn_size += 2;
2115 p = frag_more (2);
2116 p[0] = i.tm.base_opcode;
2117 p[1] = n;
2118 }
2119 else
2120 {
24eab124 2121 /* Use 16-bit jumps only for 16-bit code,
252b5132 2122 because text segments are limited to 64K anyway;
24eab124 2123 Use 32-bit jumps for 32-bit code, because they're faster,
252b5132
RH		 2124 and a 16-bit jump will clear the top 16 bits of %eip. */
2125 int jmp_size = code16 ? 2 : 4;
24eab124 2126 if (code16 && !fits_in_signed_word (n))
252b5132
RH		 2127 {
2128 as_bad (_("16-bit jump out of range"));
2129 return;
2130 }
2131
2132 if (i.tm.base_opcode == JUMP_PC_RELATIVE)
2133 { /* pace */
2134 /* unconditional jump */
2135 insn_size += prefix + 1 + jmp_size;
2136 p = frag_more (prefix + 1 + jmp_size);
2137 if (prefix)
2138 *p++ = DATA_PREFIX_OPCODE;
2139 *p++ = (char) 0xe9;
2140 md_number_to_chars (p, (valueT) n, jmp_size);
2141 }
2142 else
2143 {
2144 /* conditional jump */
2145 insn_size += prefix + 2 + jmp_size;
2146 p = frag_more (prefix + 2 + jmp_size);
2147 if (prefix)
2148 *p++ = DATA_PREFIX_OPCODE;
2149 *p++ = TWO_BYTE_OPCODE_ESCAPE;
2150 *p++ = i.tm.base_opcode + 0x10;
2151 md_number_to_chars (p, (valueT) n, jmp_size);
2152 }
2153 }
2154 }
2155 else
2156 {
2157 int size = code16 ? 2 : 4;
2158
2159 /* It's a symbol; end frag & setup for relax.
2160 Make sure there are more than 6 chars left in the current frag;
2161 if not we'll have to start a new one. */
2162 frag_grow (prefix + 1 + 2 + size);
2163 insn_size += 1 + prefix;
2164 p = frag_more (1 + prefix);
2165 if (prefix)
2166 *p++ = DATA_PREFIX_OPCODE;
2167 *p = i.tm.base_opcode;
2168 frag_var (rs_machine_dependent,
2169 prefix + 2 + size, /* 2 opcode/prefix + displacement */
2170 1,
2171 ((unsigned char) *p == JUMP_PC_RELATIVE
2172 ? ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL) | code16
2173 : ENCODE_RELAX_STATE (COND_JUMP, SMALL) | code16),
2174 i.disps[0]->X_add_symbol,
2175 (offsetT) n, p);
2176 }
2177 }
2178 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
2179 {
2180 int size = (i.tm.opcode_modifier & JumpByte) ? 1 : 4;
2181 long n = (long) i.disps[0]->X_add_number;
2182
2183 if (size == 1) /* then this is a loop or jecxz type instruction */
2184 {
2185 if (i.prefix[ADDR_PREFIX])
2186 {
2187 insn_size += 1;
2188 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
2189 i.prefixes -= 1;
2190 }
2191 }
2192 else
2193 {
2194 int code16 = 0;
2195
2196 if (i.prefix[DATA_PREFIX])
2197 {
2198 insn_size += 1;
2199 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
2200 i.prefixes -= 1;
2201 code16 = CODE16;
2202 }
2203 if (flag_16bit_code)
2204 code16 ^= CODE16;
2205
2206 if (code16)
2207 size = 2;
2208 }
2209
2210 if (!intel_syntax && (i.prefixes != 0))
2211 as_warn (_("skipping prefixes on this instruction"));
2212
2213 if (fits_in_unsigned_byte (i.tm.base_opcode))
2214 {
2215 insn_size += 1 + size;
2216 p = frag_more (1 + size);
2217 }
2218 else
2219 {
2220 insn_size += 2 + size; /* opcode can be at most two bytes */
2221 p = frag_more (2 + size);
2222 *p++ = (i.tm.base_opcode >> 8) & 0xff;
2223 }
2224 *p++ = i.tm.base_opcode & 0xff;
2225
2226 if (i.disps[0]->X_op == O_constant)
2227 {
2228 if (size == 1 && !fits_in_signed_byte (n))
2229 {
2230 as_bad (_("`%s' only takes byte displacement; %ld shortened to %d"),
2231 i.tm.name, n, *p);
2232 }
2233 else if (size == 2 && !fits_in_signed_word (n))
2234 {
2235 as_bad (_("16-bit jump out of range"));
2236 return;
2237 }
2238 md_number_to_chars (p, (valueT) n, size);
2239 }
2240 else
2241 {
2242 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2243 i.disps[0], 1, reloc (size, 1, i.disp_reloc[0]));
2244
2245 }
2246 }
2247 else if (i.tm.opcode_modifier & JumpInterSegment)
2248 {
2249 int size;
2250 int reloc_type;
2251 int prefix = i.prefix[DATA_PREFIX] != 0;
2252 int code16 = 0;
2253
2254 if (prefix)
2255 {
2256 code16 = CODE16;
2257 i.prefixes -= 1;
2258 }
2259 if (flag_16bit_code)
2260 code16 ^= CODE16;
2261
2262 size = 4;
2263 reloc_type = BFD_RELOC_32;
2264 if (code16)
2265 {
2266 size = 2;
2267 reloc_type = BFD_RELOC_16;
2268 }
2269
2270 if (!intel_syntax && (i.prefixes != 0))
2271 as_warn (_("skipping prefixes on this instruction"));
2272
2273 insn_size += prefix + 1 + 2 + size; /* 1 opcode; 2 segment; offset */
2274 p = frag_more (prefix + 1 + 2 + size);
2275 if (prefix)
2276 *p++ = DATA_PREFIX_OPCODE;
2277 *p++ = i.tm.base_opcode;
2278 if (i.imms[1]->X_op == O_constant)
2279 {
2280 long n = (long) i.imms[1]->X_add_number;
2281
2282 if (size == 2 && !fits_in_unsigned_word (n))
2283 {
2284 as_bad (_("16-bit jump out of range"));
2285 return;
2286 }
2287 md_number_to_chars (p, (valueT) n, size);
2288 }
2289 else
2290 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2291 i.imms[1], 0, reloc_type);
2292 if (i.imms[0]->X_op != O_constant)
2293 as_bad (_("can't handle non absolute segment in `%s'"),
2294 i.tm.name);
2295 md_number_to_chars (p + size, (valueT) i.imms[0]->X_add_number, 2);
2296 }
2297 else
2298 {
2299 /* Output normal instructions here. */
2300 unsigned char *q;
2301
2302 /* The prefix bytes. */
2303 for (q = i.prefix;
2304 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
2305 q++)
2306 {
2307 if (*q)
2308 {
2309 insn_size += 1;
2310 p = frag_more (1);
2311 md_number_to_chars (p, (valueT) *q, 1);
2312 }
2313 }
2314
2315 /* Now the opcode; be careful about word order here! */
2316 if (fits_in_unsigned_byte (i.tm.base_opcode))
2317 {
2318 insn_size += 1;
2319 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
2320 }
2321 else if (fits_in_unsigned_word (i.tm.base_opcode))
2322 {
2323 insn_size += 2;
2324 p = frag_more (2);
2325 /* put out high byte first: can't use md_number_to_chars! */
2326 *p++ = (i.tm.base_opcode >> 8) & 0xff;
2327 *p = i.tm.base_opcode & 0xff;
2328 }
2329 else
2330 { /* opcode is either 3 or 4 bytes */
2331 if (i.tm.base_opcode & 0xff000000)
2332 {
2333 insn_size += 4;
2334 p = frag_more (4);
2335 *p++ = (i.tm.base_opcode >> 24) & 0xff;
2336 }
2337 else
2338 {
2339 insn_size += 3;
2340 p = frag_more (3);
2341 }
2342 *p++ = (i.tm.base_opcode >> 16) & 0xff;
2343 *p++ = (i.tm.base_opcode >> 8) & 0xff;
2344 *p = (i.tm.base_opcode) & 0xff;
2345 }
2346
2347 /* Now the modrm byte and sib byte (if present). */
2348 if (i.tm.opcode_modifier & Modrm)
2349 {
2350 insn_size += 1;
2351 p = frag_more (1);
2352 md_number_to_chars (p,
2353 (valueT) (i.rm.regmem << 0
2354 | i.rm.reg << 3
2355 | i.rm.mode << 6),
2356 1);
2357 /* If i.rm.regmem == ESP (4)
2358 && i.rm.mode != (Register mode)
2359 && not 16 bit
2360 ==> need second modrm byte. */
2361 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
2362 && i.rm.mode != 3
2363 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
2364 {
2365 insn_size += 1;
2366 p = frag_more (1);
2367 md_number_to_chars (p,
2368 (valueT) (i.sib.base << 0
2369 | i.sib.index << 3
2370 | i.sib.scale << 6),
2371 1);
2372 }
2373 }
2374
2375 if (i.disp_operands)
2376 {
2377 register unsigned int n;
2378
2379 for (n = 0; n < i.operands; n++)
2380 {
2381 if (i.disps[n])
2382 {
2383 if (i.disps[n]->X_op == O_constant)
2384 {
b4cac588
AM		 2385 int size = 4;
2386 long val = (long) i.disps[n]->X_add_number;
2387
2388 if (i.types[n] & (Disp8 | Disp16))
252b5132 2389 {
b4cac588
AM		 2390 long mask;
2391
2392 size = 2;
2393 mask = ~ (long) 0xffff;
2394 if (i.types[n] & Disp8)
2395 {
2396 size = 1;
2397 mask = ~ (long) 0xff;
2398 }
2399
2400 if ((val & mask) != 0 && (val & mask) != mask)
24eab124
AM		 2401 as_warn (_("%ld shortened to %ld"),
2402 val, val & ~mask);
252b5132 2403 }
b4cac588
AM		 2404 insn_size += size;
2405 p = frag_more (size);
2406 md_number_to_chars (p, (valueT) val, size);
252b5132
RH		 2407 }
2408 else if (i.types[n] & Disp32)
2409 {
2410 insn_size += 4;
2411 p = frag_more (4);
2412 fix_new_exp (frag_now, p - frag_now->fr_literal, 4,
2413 i.disps[n], 0,
2414 TC_RELOC (i.disp_reloc[n], BFD_RELOC_32));
2415 }
2416 else
2417 { /* must be Disp16 */
2418 insn_size += 2;
2419 p = frag_more (2);
2420 fix_new_exp (frag_now, p - frag_now->fr_literal, 2,
2421 i.disps[n], 0,
2422 TC_RELOC (i.disp_reloc[n], BFD_RELOC_16));
2423 }
2424 }
2425 }
2426 } /* end displacement output */
2427
2428 /* output immediate */
2429 if (i.imm_operands)
2430 {
2431 register unsigned int n;
2432
2433 for (n = 0; n < i.operands; n++)
2434 {
2435 if (i.imms[n])
2436 {
2437 if (i.imms[n]->X_op == O_constant)
2438 {
b4cac588
AM		 2439 int size = 4;
2440 long val = (long) i.imms[n]->X_add_number;
2441
2442 if (i.types[n] & (Imm8 | Imm8S | Imm16))
252b5132 2443 {
b4cac588
AM		 2444 long mask;
2445
2446 size = 2;
2447 mask = ~ (long) 0xffff;
2448 if (i.types[n] & (Imm8 | Imm8S))
2449 {
2450 size = 1;
2451 mask = ~ (long) 0xff;
2452 }
2453 if ((val & mask) != 0 && (val & mask) != mask)
24eab124
AM		 2454 as_warn (_("%ld shortened to %ld"),
2455 val, val & ~mask);
252b5132 2456 }
b4cac588
AM		 2457 insn_size += size;
2458 p = frag_more (size);
2459 md_number_to_chars (p, (valueT) val, size);
252b5132
RH		 2460 }
2461 else
2462 { /* not absolute_section */
2463 /* Need a 32-bit fixup (don't support 8bit
2464 non-absolute ims). Try to support other
2465 sizes ... */
2466 int r_type;
2467 int size;
2468 int pcrel = 0;
2469
2470 if (i.types[n] & (Imm8 | Imm8S))
2471 size = 1;
2472 else if (i.types[n] & Imm16)
2473 size = 2;
2474 else
2475 size = 4;
2476 insn_size += size;
2477 p = frag_more (size);
2478 r_type = reloc (size, 0, i.disp_reloc[0]);
2479#ifdef BFD_ASSEMBLER
2480 if (r_type == BFD_RELOC_32
2481 && GOT_symbol
2482 && GOT_symbol == i.imms[n]->X_add_symbol
2483 && (i.imms[n]->X_op == O_symbol
2484 || (i.imms[n]->X_op == O_add
49309057
ILT		 2485 && ((symbol_get_value_expression
2486 (i.imms[n]->X_op_symbol)->X_op)
252b5132
RH		 2487 == O_subtract))))
2488 {
2489 r_type = BFD_RELOC_386_GOTPC;
2490 i.imms[n]->X_add_number += 3;
2491 }
2492#endif
2493 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2494 i.imms[n], pcrel, r_type);
2495 }
2496 }
2497 }
2498 } /* end immediate output */
2499 }
2500
2501#ifdef DEBUG386
2502 if (flag_debug)
2503 {
2504 pi (line, &i);
2505 }
2506#endif /* DEBUG386 */
2507 }
2508}
2509\f
2510static int i386_is_reg PARAMS ((char *));
2511
2512static int
2513i386_is_reg (reg_string)
2514 char *reg_string;
2515{
2516 register char *s = reg_string;
2517 register char *p;
2518 char reg_name_given[MAX_REG_NAME_SIZE + 1];
2519
2520 if (is_space_char (*s))
2521 ++s;
2522
2523 p = reg_name_given;
2524 while ((*p++ = register_chars[(unsigned char) *s++]) != '\0')
2525 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
2526 return 0;
2527
2528 if (!hash_find (reg_hash, reg_name_given))
2529 return 0;
2530 else
2531 return 1;
2532}
c3332e24 2533
252b5132
RH		 2534static int i386_immediate PARAMS ((char *));
2535
2536static int
2537i386_immediate (imm_start)
2538 char *imm_start;
2539{
2540 char *save_input_line_pointer;
2541 segT exp_seg = 0;
2542 expressionS * exp;
2543
2544 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
2545 {
2546 as_bad (_("Only 1 or 2 immediate operands are allowed"));
2547 return 0;
2548 }
2549
2550 exp = &im_expressions[i.imm_operands++];
2551 i.imms[this_operand] = exp;
2552
2553 if (is_space_char (*imm_start))
2554 ++imm_start;
2555
2556 save_input_line_pointer = input_line_pointer;
2557 input_line_pointer = imm_start;
2558
2559#ifndef LEX_AT
24eab124
AM		 2560 {
2561 /*
2562 * We can have operands of the form
2563 * <symbol>@GOTOFF+<nnn>
2564 * Take the easy way out here and copy everything
2565 * into a temporary buffer...
2566 */
2567 register char *cp;
2568
2569 cp = strchr (input_line_pointer, '@');
2570 if (cp != NULL)
2571 {
2572 char *tmpbuf;
2573 int len = 0;
2574 int first;
2575
2576 /* GOT relocations are not supported in 16 bit mode */
2577 if (flag_16bit_code)
2578 as_bad (_("GOT relocations not supported in 16 bit mode"));
2579
2580 if (GOT_symbol == NULL)
2581 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
2582
2583 if (strncmp (cp + 1, "PLT", 3) == 0)
2584 {
2585 i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32;
2586 len = 3;
2587 }
2588 else if (strncmp (cp + 1, "GOTOFF", 6) == 0)
2589 {
2590 i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF;
2591 len = 6;
2592 }
2593 else if (strncmp (cp + 1, "GOT", 3) == 0)
2594 {
2595 i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32;
2596 len = 3;
2597 }
2598 else
2599 as_bad (_("Bad reloc specifier in expression"));
2600
2601 /* Replace the relocation token with ' ', so that errors like
2602 foo@GOTOFF1 will be detected. */
2603 first = cp - input_line_pointer;
2604 tmpbuf = (char *) alloca (strlen(input_line_pointer));
2605 memcpy (tmpbuf, input_line_pointer, first);
2606 tmpbuf[first] = ' ';
2607 strcpy (tmpbuf + first + 1, cp + 1 + len);
2608 input_line_pointer = tmpbuf;
2609 }
2610 }
252b5132
RH		 2611#endif
2612
2613 exp_seg = expression (exp);
2614
83183c0c 2615 SKIP_WHITESPACE ();
252b5132
RH		 2616 if (*input_line_pointer)
2617 as_bad (_("Ignoring junk `%s' after expression"), input_line_pointer);
2618
2619 input_line_pointer = save_input_line_pointer;
2620
2621 if (exp->X_op == O_absent)
2622 {
2623 /* missing or bad expr becomes absolute 0 */
2624 as_bad (_("Missing or invalid immediate expression `%s' taken as 0"),
24eab124 2625 imm_start);
252b5132
RH		 2626 exp->X_op = O_constant;
2627 exp->X_add_number = 0;
2628 exp->X_add_symbol = (symbolS *) 0;
2629 exp->X_op_symbol = (symbolS *) 0;
2630 i.types[this_operand] |= Imm;
2631 }
2632 else if (exp->X_op == O_constant)
2633 {
b4cac588
AM		 2634 int bigimm = Imm32;
2635 if (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0))
2636 bigimm = Imm16;
2637
252b5132 2638 i.types[this_operand] |=
b4cac588
AM		 2639 (bigimm | smallest_imm_type ((long) exp->X_add_number));
2640
252b5132
RH		 2641 /* If a suffix is given, this operand may be shortended. */
2642 switch (i.suffix)
24eab124
AM		 2643 {
2644 case WORD_MNEM_SUFFIX:
2645 i.types[this_operand] |= Imm16;
2646 break;
2647 case BYTE_MNEM_SUFFIX:
2648 i.types[this_operand] |= Imm16 | Imm8 | Imm8S;
2649 break;
2650 }
252b5132
RH		 2651 }
2652#ifdef OBJ_AOUT
2653 else if (exp_seg != text_section
24eab124
AM		 2654 && exp_seg != data_section
2655 && exp_seg != bss_section
2656 && exp_seg != undefined_section
252b5132 2657#ifdef BFD_ASSEMBLER
24eab124 2658 && !bfd_is_com_section (exp_seg)
252b5132 2659#endif
24eab124 2660 )
252b5132 2661 {
252b5132
RH		 2662 as_bad (_("Unimplemented segment type %d in operand"), exp_seg);
2663 return 0;
2664 }
2665#endif
2666 else
2667 {
2668 /* This is an address. The size of the address will be
24eab124
AM		 2669 determined later, depending on destination register,
2670 suffix, or the default for the section. We exclude
2671 Imm8S here so that `push $foo' and other instructions
2672 with an Imm8S form will use Imm16 or Imm32. */
252b5132
RH		 2673 i.types[this_operand] |= (Imm8 | Imm16 | Imm32);
2674 }
2675
2676 return 1;
2677}
2678
2679static int i386_scale PARAMS ((char *));
2680
2681static int
2682i386_scale (scale)
2683 char *scale;
2684{
2685 if (!isdigit (*scale))
2686 goto bad_scale;
2687
2688 switch (*scale)
2689 {
2690 case '0':
2691 case '1':
2692 i.log2_scale_factor = 0;
2693 break;
2694 case '2':
2695 i.log2_scale_factor = 1;
2696 break;
2697 case '4':
2698 i.log2_scale_factor = 2;
2699 break;
2700 case '8':
2701 i.log2_scale_factor = 3;
2702 break;
2703 default:
2704 bad_scale:
2705 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
24eab124 2706 scale);
252b5132
RH		 2707 return 0;
2708 }
2709 if (i.log2_scale_factor != 0 && ! i.index_reg)
2710 {
2711 as_warn (_("scale factor of %d without an index register"),
24eab124 2712 1 << i.log2_scale_factor);
252b5132
RH		 2713#if SCALE1_WHEN_NO_INDEX
2714 i.log2_scale_factor = 0;
2715#endif
2716 }
2717 return 1;
2718}
2719
2720static int i386_displacement PARAMS ((char *, char *));
2721
2722static int
2723i386_displacement (disp_start, disp_end)
2724 char *disp_start;
2725 char *disp_end;
2726{
2727 register expressionS *exp;
2728 segT exp_seg = 0;
2729 char *save_input_line_pointer;
2730 int bigdisp = Disp32;
2731
252b5132
RH		 2732 if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0))
2733 bigdisp = Disp16;
2734 i.types[this_operand] |= bigdisp;
2735
2736 exp = &disp_expressions[i.disp_operands];
2737 i.disps[this_operand] = exp;
2738 i.disp_reloc[this_operand] = NO_RELOC;
2739 i.disp_operands++;
2740 save_input_line_pointer = input_line_pointer;
2741 input_line_pointer = disp_start;
2742 END_STRING_AND_SAVE (disp_end);
2743
2744#ifndef GCC_ASM_O_HACK
2745#define GCC_ASM_O_HACK 0
2746#endif
2747#if GCC_ASM_O_HACK
2748 END_STRING_AND_SAVE (disp_end + 1);
2749 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 2750 && displacement_string_end[-1] == '+')
252b5132
RH		 2751 {
2752 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 2753 constraint within gcc asm statements.
2754 For instance:
2755
2756 #define _set_tssldt_desc(n,addr,limit,type) \
2757 __asm__ __volatile__ ( \
2758 "movw %w2,%0\n\t" \
2759 "movw %w1,2+%0\n\t" \
2760 "rorl $16,%1\n\t" \
2761 "movb %b1,4+%0\n\t" \
2762 "movb %4,5+%0\n\t" \
2763 "movb $0,6+%0\n\t" \
2764 "movb %h1,7+%0\n\t" \
2765 "rorl $16,%1" \
2766 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
2767
2768 This works great except that the output assembler ends
2769 up looking a bit weird if it turns out that there is
2770 no offset. You end up producing code that looks like:
2771
2772 #APP
2773 movw $235,(%eax)
2774 movw %dx,2+(%eax)
2775 rorl $16,%edx
2776 movb %dl,4+(%eax)
2777 movb $137,5+(%eax)
2778 movb $0,6+(%eax)
2779 movb %dh,7+(%eax)
2780 rorl $16,%edx
2781 #NO_APP
2782
2783 So here we provide the missing zero.
2784 */
2785
2786 *displacement_string_end = '0';
252b5132
RH		 2787 }
2788#endif
2789#ifndef LEX_AT
24eab124
AM		 2790 {
2791 /*
2792 * We can have operands of the form
2793 * <symbol>@GOTOFF+<nnn>
2794 * Take the easy way out here and copy everything
2795 * into a temporary buffer...
2796 */
2797 register char *cp;
2798
2799 cp = strchr (input_line_pointer, '@');
2800 if (cp != NULL)
2801 {
2802 char *tmpbuf;
2803 int len = 0;
2804 int first;
2805
2806 /* GOT relocations are not supported in 16 bit mode */
2807 if (flag_16bit_code)
2808 as_bad (_("GOT relocations not supported in 16 bit mode"));
2809
2810 if (GOT_symbol == NULL)
2811 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
2812
2813 if (strncmp (cp + 1, "PLT", 3) == 0)
2814 {
2815 i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32;
2816 len = 3;
2817 }
2818 else if (strncmp (cp + 1, "GOTOFF", 6) == 0)
2819 {
2820 i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF;
2821 len = 6;
2822 }
2823 else if (strncmp (cp + 1, "GOT", 3) == 0)
2824 {
2825 i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32;
2826 len = 3;
2827 }
2828 else
2829 as_bad (_("Bad reloc specifier in expression"));
2830
2831 /* Replace the relocation token with ' ', so that errors like
2832 foo@GOTOFF1 will be detected. */
2833 first = cp - input_line_pointer;
2834 tmpbuf = (char *) alloca (strlen(input_line_pointer));
2835 memcpy (tmpbuf, input_line_pointer, first);
2836 tmpbuf[first] = ' ';
2837 strcpy (tmpbuf + first + 1, cp + 1 + len);
2838 input_line_pointer = tmpbuf;
2839 }
2840 }
252b5132
RH		 2841#endif
2842
24eab124 2843 exp_seg = expression (exp);
252b5132
RH		 2844
2845#ifdef BFD_ASSEMBLER
24eab124
AM		 2846 /* We do this to make sure that the section symbol is in
2847 the symbol table. We will ultimately change the relocation
2848 to be relative to the beginning of the section */
2849 if (i.disp_reloc[this_operand] == BFD_RELOC_386_GOTOFF)
2850 {
2851 if (S_IS_LOCAL(exp->X_add_symbol)
2852 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
2853 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
2854 assert (exp->X_op == O_symbol);
2855 exp->X_op = O_subtract;
2856 exp->X_op_symbol = GOT_symbol;
2857 i.disp_reloc[this_operand] = BFD_RELOC_32;
2858 }
252b5132
RH		 2859#endif
2860
24eab124
AM		 2861 SKIP_WHITESPACE ();
2862 if (*input_line_pointer)
2863 as_bad (_("Ignoring junk `%s' after expression"),
2864 input_line_pointer);
252b5132 2865#if GCC_ASM_O_HACK
24eab124 2866 RESTORE_END_STRING (disp_end + 1);
252b5132 2867#endif
24eab124
AM		 2868 RESTORE_END_STRING (disp_end);
2869 input_line_pointer = save_input_line_pointer;
2870
2871 if (exp->X_op == O_constant)
2872 {
2873 if (fits_in_signed_byte (exp->X_add_number))
2874 i.types[this_operand] |= Disp8;
2875 }
252b5132 2876#ifdef OBJ_AOUT
24eab124
AM		 2877 else if (exp_seg != text_section
2878 && exp_seg != data_section
2879 && exp_seg != bss_section
2880 && exp_seg != undefined_section)
2881 {
2882 as_bad (_ ("Unimplemented segment type %d in operand"), exp_seg);
2883 return 0;
2884 }
252b5132
RH		 2885#endif
2886 return 1;
2887}
2888
2889static int i386_operand_modifier PARAMS ((char **, int));
2890
2891static int
2892i386_operand_modifier (op_string, got_a_float)
2893 char **op_string;
2894 int got_a_float;
2895{
24eab124
AM		 2896 if (!strncasecmp (*op_string, "BYTE PTR", 8))
2897 {
2898 i.suffix = BYTE_MNEM_SUFFIX;
2899 *op_string += 8;
2900 return BYTE_PTR;
252b5132 2901
24eab124
AM		 2902 }
2903 else if (!strncasecmp (*op_string, "WORD PTR", 8))
2904 {
2905 i.suffix = WORD_MNEM_SUFFIX;
2906 *op_string += 8;
2907 return WORD_PTR;
2908 }
252b5132 2909
24eab124
AM		 2910 else if (!strncasecmp (*op_string, "DWORD PTR", 9))
2911 {
2912 if (got_a_float)
2913 i.suffix = SHORT_MNEM_SUFFIX;
2914 else
2915 i.suffix = DWORD_MNEM_SUFFIX;
2916 *op_string += 9;
2917 return DWORD_PTR;
2918 }
252b5132 2919
24eab124
AM		 2920 else if (!strncasecmp (*op_string, "QWORD PTR", 9))
2921 {
2922 i.suffix = INTEL_DWORD_MNEM_SUFFIX;
2923 *op_string += 9;
2924 return QWORD_PTR;
2925 }
252b5132 2926
24eab124
AM		 2927 else if (!strncasecmp (*op_string, "XWORD PTR", 9))
2928 {
2929 i.suffix = LONG_DOUBLE_MNEM_SUFFIX;
2930 *op_string += 9;
2931 return XWORD_PTR;
2932 }
252b5132 2933
24eab124
AM		 2934 else if (!strncasecmp (*op_string, "SHORT", 5))
2935 {
2936 *op_string += 5;
2937 return SHORT;
2938 }
252b5132 2939
24eab124
AM		 2940 else if (!strncasecmp (*op_string, "OFFSET FLAT:", 12))
2941 {
2942 *op_string += 12;
2943 return OFFSET_FLAT;
2944 }
252b5132 2945
24eab124
AM		 2946 else if (!strncasecmp (*op_string, "FLAT", 4))
2947 {
2948 *op_string += 4;
2949 return FLAT;
2950 }
252b5132 2951
24eab124 2952 else return NONE_FOUND;
c3332e24 2953}
252b5132
RH		 2954
2955static char * build_displacement_string PARAMS ((int, char *));
2956
2957static char *
2958build_displacement_string (initial_disp, op_string)
2959 int initial_disp;
2960 char *op_string;
2961{
2962 char *temp_string = (char *) malloc (strlen (op_string) + 1);
2963 char *end_of_operand_string;
2964 char *tc;
2965 char *temp_disp;
2966
2967 temp_string[0] = '\0';
2968 tc = end_of_operand_string = strchr (op_string, '[');
2969 if ( initial_disp && !end_of_operand_string)
2970 {
2971 strcpy (temp_string, op_string);
2972 return (temp_string);
2973 }
2974
2975 /* Build the whole displacement string */
2976 if (initial_disp)
2977 {
2978 strncpy (temp_string, op_string, end_of_operand_string - op_string);
2979 temp_string[end_of_operand_string - op_string] = '\0';
2980 temp_disp = tc;
2981 }
c3332e24 2982 else
252b5132
RH		 2983 temp_disp = op_string;
2984
2985 while (*temp_disp != '\0')
2986 {
2987 int add_minus = (*temp_disp == '-');
2988
2989 if (*temp_disp == '+' || *temp_disp == '-' || *temp_disp == '[')
24eab124 2990 temp_disp++;
252b5132
RH		 2991
2992 if (is_space_char (*temp_disp))
24eab124 2993 temp_disp++;
252b5132
RH		 2994
2995 /* Don't consider registers */
2996 if (*temp_disp != REGISTER_PREFIX
24eab124
AM		 2997 && !(allow_naked_reg && i386_is_reg (temp_disp)))
2998 {
2999 char *string_start = temp_disp;
3000
3001 while (*temp_disp != ']'
3002 && *temp_disp != '+'
3003 && *temp_disp != '-'
3004 && *temp_disp != '*')
3005 ++temp_disp;
3006
3007 if (add_minus)
3008 strcat (temp_string, "-");
3009 else
3010 strcat (temp_string, "+");
3011
3012 strncat (temp_string, string_start, temp_disp - string_start);
3013 if (*temp_disp == '+' || *temp_disp == '-')
3014 --temp_disp;
3015 }
252b5132
RH		 3016
3017 while (*temp_disp != '\0'
24eab124
AM		 3018 && *temp_disp != '+'
3019 && *temp_disp != '-')
3020 ++temp_disp;
252b5132
RH		 3021 }
3022
3023 return temp_string;
3024}
3025
3026static int i386_parse_seg PARAMS ((char *));
3027
3028static int
3029i386_parse_seg (op_string)
3030 char *op_string;
3031{
3032 if (is_space_char (*op_string))
3033 ++op_string;
3034
3035 /* Should be one of es, cs, ss, ds fs or gs */
3036 switch (*op_string++)
3037 {
3038 case 'e':
3039 i.seg[i.mem_operands] = &es;
3040 break;
3041 case 'c':
3042 i.seg[i.mem_operands] = &cs;
3043 break;
3044 case 's':
3045 i.seg[i.mem_operands] = &ss;
3046 break;
3047 case 'd':
3048 i.seg[i.mem_operands] = &ds;
3049 break;
3050 case 'f':
3051 i.seg[i.mem_operands] = &fs;
3052 break;
3053 case 'g':
3054 i.seg[i.mem_operands] = &gs;
3055 break;
3056 default:
3057 as_bad (_("bad segment name `%s'"), op_string);
3058 return 0;
3059 }
3060
3061 if (*op_string++ != 's')
3062 {
24eab124
AM		 3063 as_bad (_("bad segment name `%s'"), op_string);
3064 return 0;
252b5132
RH		 3065 }
3066
3067 if (is_space_char (*op_string))
3068 ++op_string;
3069
3070 if (*op_string != ':')
3071 {
24eab124
AM		 3072 as_bad (_("bad segment name `%s'"), op_string);
3073 return 0;
252b5132
RH		 3074 }
3075
c3332e24
AM		 3076 return 1;
3077
252b5132
RH		 3078}
3079
eecb386c 3080static int i386_index_check PARAMS((const char *));
252b5132 3081
eecb386c
AM		 3082/* Make sure the memory operand we've been dealt is valid.
3083 Returns 1 on success, 0 on a failure.
3084*/
252b5132 3085static int
eecb386c
AM		 3086i386_index_check (operand_string)
3087 const char *operand_string;
252b5132 3088{
24eab124 3089#if INFER_ADDR_PREFIX
eecb386c
AM		 3090 int fudged = 0;
3091
24eab124
AM		 3092 tryprefix:
3093#endif
3094 if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0) ?
3095 /* 16 bit mode checks */
3096 ((i.base_reg
3097 && ((i.base_reg->reg_type & (Reg16|BaseIndex))
3098 != (Reg16|BaseIndex)))
3099 || (i.index_reg
3100 && (((i.index_reg->reg_type & (Reg16|BaseIndex))
3101 != (Reg16|BaseIndex))
3102 || ! (i.base_reg
3103 && i.base_reg->reg_num < 6
3104 && i.index_reg->reg_num >= 6
3105 && i.log2_scale_factor == 0)))) :
3106 /* 32 bit mode checks */
3107 ((i.base_reg
3108 && (i.base_reg->reg_type & Reg32) == 0)
3109 || (i.index_reg
3110 && ((i.index_reg->reg_type & (Reg32|BaseIndex))
3111 != (Reg32|BaseIndex)))))
3112 {
3113#if INFER_ADDR_PREFIX
eecb386c 3114 if (i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0')
24eab124
AM		 3115 {
3116 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
3117 i.prefixes += 1;
b23bac36
AM		 3118 /* Change the size of any displacement too. At most one of
3119 Disp16 or Disp32 is set.
3120 FIXME. There doesn't seem to be any real need for separate
3121 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3122 Removing them would probably clean up the code quite a lot.
3123 */
3124 if (i.types[this_operand] & (Disp16|Disp32))
3125 i.types[this_operand] ^= (Disp16|Disp32);
eecb386c 3126 fudged = 1;
24eab124
AM		 3127 goto tryprefix;
3128 }
24eab124 3129#endif
eecb386c
AM		 3130 if (fudged)
3131 as_bad (_("`%s' is not a valid base/index expression"),
3132 operand_string);
3133 else
3134 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3135 operand_string,
3136 flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0) ? "16" : "32");
3137 return 0;
24eab124
AM		 3138 }
3139 return 1;
3140}
252b5132 3141
24eab124
AM		 3142static int i386_intel_memory_operand PARAMS ((char *));
3143
3144static int
3145i386_intel_memory_operand (operand_string)
3146 char *operand_string;
3147{
3148 char *op_string = operand_string;
252b5132
RH		 3149 char *end_of_operand_string;
3150
24eab124
AM		 3151 if ((i.mem_operands == 1
3152 && (current_templates->start->opcode_modifier & IsString) == 0)
3153 || i.mem_operands == 2)
252b5132 3154 {
24eab124
AM		 3155 as_bad (_("too many memory references for `%s'"),
3156 current_templates->start->name);
3157 return 0;
252b5132
RH		 3158 }
3159
3160 /* Look for displacement preceding open bracket */
3161 if (*op_string != '[')
3162 {
3163 char *end_seg;
3164 char *temp_string;
3165
3166 end_seg = strchr (op_string, ':');
3167 if (end_seg)
24eab124
AM		 3168 {
3169 if (!i386_parse_seg (op_string))
3170 return 0;
3171 op_string = end_seg + 1;
3172 }
252b5132
RH		 3173
3174 temp_string = build_displacement_string (true, op_string);
24eab124
AM		 3175
3176 if (i.disp_operands == 0 &&
3177 !i386_displacement (temp_string, temp_string + strlen (temp_string)))
3178 return 0;
252b5132
RH		 3179
3180 end_of_operand_string = strchr (op_string, '[');
3181 if (!end_of_operand_string)
24eab124 3182 end_of_operand_string = op_string + strlen (op_string);
252b5132
RH		 3183
3184 if (is_space_char (*end_of_operand_string))
24eab124 3185 --end_of_operand_string;
252b5132
RH		 3186
3187 op_string = end_of_operand_string;
24eab124 3188 }
252b5132
RH		 3189
3190 if (*op_string == '[')
3191 {
3192 ++op_string;
3193
3194 /* Pick off each component and figure out where it belongs */
3195
3196 end_of_operand_string = op_string;
3197
3198 while (*op_string != ']')
24eab124
AM		 3199 {
3200
3201 while (*end_of_operand_string != '+'
3202 && *end_of_operand_string != '-'
3203 && *end_of_operand_string != '*'
3204 && *end_of_operand_string != ']')
3205 end_of_operand_string++;
3206
3207 if (*op_string == '+')
3208 {
3209 char *temp_string = op_string + 1;
3210 if (is_space_char (*temp_string))
3211 ++temp_string;
3212 if (*temp_string == REGISTER_PREFIX
3213 || (allow_naked_reg && i386_is_reg (temp_string)))
3214 ++op_string;
3215 }
3216
3217 if (*op_string == REGISTER_PREFIX
3218 || (allow_naked_reg && i386_is_reg (op_string)))
3219 {
3220 const reg_entry *temp_reg;
3221 char *end_op;
3222
3223 END_STRING_AND_SAVE (end_of_operand_string);
3224 temp_reg = parse_register (op_string, &end_op);
3225 RESTORE_END_STRING (end_of_operand_string);
3226
3227 if (temp_reg == NULL)
3228 return 0;
3229
3230 if (i.base_reg == NULL)
3231 i.base_reg = temp_reg;
3232 else
3233 i.index_reg = temp_reg;
3234
3235 i.types[this_operand] |= BaseIndex;
3236
3237 }
3238 else if (is_digit_char (*op_string) || *op_string == '+' || *op_string == '-')
3239 {
3240
3241 char *temp_string = build_displacement_string (false, op_string);
3242
3243 if (*temp_string == '+')
3244 ++temp_string;
3245
3246 if (i.disp_operands == 0 &&
3247 !i386_displacement (temp_string, temp_string + strlen (temp_string)))
3248 return 0;
3249
3250 ++op_string;
3251 end_of_operand_string = op_string;
3252 while (*end_of_operand_string != ']'
3253 && *end_of_operand_string != '+'
3254 && *end_of_operand_string != '-'
3255 && *end_of_operand_string != '*')
3256 ++end_of_operand_string;
3257 }
3258 else if (*op_string == '*')
3259 {
3260 ++op_string;
3261
3262 if (i.base_reg && !i.index_reg)
3263 {
3264 i.index_reg = i.base_reg;
3265 i.base_reg = 0;
3266 }
3267
3268 if (!i386_scale (op_string))
3269 return 0;
3270 }
3271 op_string = end_of_operand_string;
3272 ++end_of_operand_string;
3273 }
3274 }
3275
eecb386c
AM		 3276 if (i386_index_check (operand_string) == 0)
3277 return 0;
252b5132 3278
24eab124 3279 i.mem_operands++;
252b5132
RH		 3280 return 1;
3281}
3282
252b5132
RH		 3283static int
3284i386_intel_operand (operand_string, got_a_float)
3285 char *operand_string;
3286 int got_a_float;
3287{
3288 char *op_string = operand_string;
3289
3290 int operand_modifier = i386_operand_modifier (&op_string, got_a_float);
3291 if (is_space_char (*op_string))
3292 ++op_string;
3293
3294 switch (operand_modifier)
3295 {
3296 case BYTE_PTR:
3297 case WORD_PTR:
3298 case DWORD_PTR:
3299 case QWORD_PTR:
3300 case XWORD_PTR:
252b5132 3301 if (!i386_intel_memory_operand (op_string))
24eab124 3302 return 0;
252b5132
RH		 3303 break;
3304
3305 case FLAT:
252b5132
RH		 3306 case OFFSET_FLAT:
3307 if (!i386_immediate (op_string))
24eab124 3308 return 0;
252b5132
RH		 3309 break;
3310
3311 case SHORT:
252b5132 3312 case NONE_FOUND:
c3332e24
AM		 3313 /* Should be register or immediate */
3314 if (is_digit_char (*op_string)
3315 && strchr (op_string, '[') == 0)
3316 {
3317 if (!i386_immediate (op_string))
3318 return 0;
3319 }
3320 else if (*op_string == REGISTER_PREFIX
3321 || (allow_naked_reg
3322 && i386_is_reg (op_string)))
3323 {
c3332e24
AM		 3324 register const reg_entry * r;
3325 char *end_op;
252b5132 3326
c3332e24
AM		 3327 r = parse_register (op_string, &end_op);
3328 if (r == NULL)
3329 return 0;
252b5132 3330
c3332e24
AM		 3331 /* Check for a segment override by searching for ':' after a
3332 segment register. */
3333 op_string = end_op;
3334 if (is_space_char (*op_string))
3335 ++op_string;
3336 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
3337 {
3338 switch (r->reg_num)
3339 {
3340 case 0:
3341 i.seg[i.mem_operands] = &es;
3342 break;
3343 case 1:
3344 i.seg[i.mem_operands] = &cs;
3345 break;
3346 case 2:
3347 i.seg[i.mem_operands] = &ss;
3348 break;
3349 case 3:
3350 i.seg[i.mem_operands] = &ds;
3351 break;
3352 case 4:
3353 i.seg[i.mem_operands] = &fs;
3354 break;
3355 case 5:
3356 i.seg[i.mem_operands] = &gs;
3357 break;
3358 }
252b5132 3359
c3332e24
AM		 3360 }
3361 i.types[this_operand] |= r->reg_type & ~BaseIndex;
3362 i.regs[this_operand] = r;
3363 i.reg_operands++;
3364 }
c3332e24
AM		 3365 else
3366 {
c3332e24
AM		 3367 if (!i386_intel_memory_operand (op_string))
3368 return 0;
c3332e24
AM		 3369 }
3370 break;
c3332e24 3371 } /* end switch */
24eab124 3372
252b5132
RH		 3373 return 1;
3374}
3375
3376/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3377 on error. */
3378
252b5132
RH		 3379static int
3380i386_operand (operand_string)
3381 char *operand_string;
3382{
24eab124 3383 char *op_string = operand_string;
252b5132 3384
24eab124 3385 if (is_space_char (*op_string))
252b5132
RH		 3386 ++op_string;
3387
24eab124
AM		 3388 /* We check for an absolute prefix (differentiating,
3389 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3390 if (*op_string == ABSOLUTE_PREFIX)
3391 {
3392 ++op_string;
3393 if (is_space_char (*op_string))
3394 ++op_string;
3395 i.types[this_operand] |= JumpAbsolute;
3396 }
252b5132 3397
24eab124
AM		 3398 /* Check if operand is a register. */
3399 if (*op_string == REGISTER_PREFIX
3400 || (allow_naked_reg && i386_is_reg (op_string)))
3401 {
3402 register const reg_entry *r;
3403 char *end_op;
3404
3405 r = parse_register (op_string, &end_op);
3406 if (r == NULL)
3407 return 0;
3408
3409 /* Check for a segment override by searching for ':' after a
3410 segment register. */
3411 op_string = end_op;
3412 if (is_space_char (*op_string))
3413 ++op_string;
3414 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
3415 {
3416 switch (r->reg_num)
3417 {
3418 case 0:
3419 i.seg[i.mem_operands] = &es;
3420 break;
3421 case 1:
3422 i.seg[i.mem_operands] = &cs;
3423 break;
3424 case 2:
3425 i.seg[i.mem_operands] = &ss;
3426 break;
3427 case 3:
3428 i.seg[i.mem_operands] = &ds;
3429 break;
3430 case 4:
3431 i.seg[i.mem_operands] = &fs;
3432 break;
3433 case 5:
3434 i.seg[i.mem_operands] = &gs;
3435 break;
3436 }
252b5132 3437
24eab124 3438 /* Skip the ':' and whitespace. */
252b5132
RH		 3439 ++op_string;
3440 if (is_space_char (*op_string))
24eab124 3441 ++op_string;
252b5132 3442
24eab124
AM		 3443 if (!is_digit_char (*op_string)
3444 && !is_identifier_char (*op_string)
3445 && *op_string != '('
3446 && *op_string != ABSOLUTE_PREFIX)
3447 {
3448 as_bad (_("bad memory operand `%s'"), op_string);
3449 return 0;
3450 }
3451 /* Handle case of %es:*foo. */
3452 if (*op_string == ABSOLUTE_PREFIX)
3453 {
3454 ++op_string;
3455 if (is_space_char (*op_string))
3456 ++op_string;
3457 i.types[this_operand] |= JumpAbsolute;
3458 }
3459 goto do_memory_reference;
3460 }
3461 if (*op_string)
3462 {
3463 as_bad (_("Junk `%s' after register"), op_string);
3464 return 0;
3465 }
3466 i.types[this_operand] |= r->reg_type & ~BaseIndex;
3467 i.regs[this_operand] = r;
3468 i.reg_operands++;
3469 }
3470 else if (*op_string == IMMEDIATE_PREFIX)
3471 { /* ... or an immediate */
3472 ++op_string;
3473 if (i.types[this_operand] & JumpAbsolute)
3474 {
3475 as_bad (_("Immediate operand illegal with absolute jump"));
3476 return 0;
3477 }
3478 if (!i386_immediate (op_string))
3479 return 0;
3480 }
3481 else if (is_digit_char (*op_string)
3482 || is_identifier_char (*op_string)
3483 || *op_string == '(' )
3484 {
3485 /* This is a memory reference of some sort. */
3486 char *end_of_operand_string;
3487 register char *base_string;
3488 int found_base_index_form;
252b5132 3489
24eab124 3490 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 3491 char *displacement_string_start;
3492 char *displacement_string_end;
252b5132 3493
24eab124 3494 do_memory_reference:
eecb386c
AM		 3495 displacement_string_start = NULL;
3496 displacement_string_end = NULL;
252b5132 3497
24eab124
AM		 3498 if ((i.mem_operands == 1
3499 && (current_templates->start->opcode_modifier & IsString) == 0)
3500 || i.mem_operands == 2)
3501 {
3502 as_bad (_("too many memory references for `%s'"),
3503 current_templates->start->name);
3504 return 0;
3505 }
252b5132 3506
24eab124
AM		 3507 /* Check for base index form. We detect the base index form by
3508 looking for an ')' at the end of the operand, searching
3509 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3510 after the '('. */
3511 found_base_index_form = 0;
3512 end_of_operand_string = op_string + strlen (op_string);
c3332e24 3513
24eab124
AM		 3514 --end_of_operand_string;
3515 if (is_space_char (*end_of_operand_string))
3516 --end_of_operand_string;
252b5132 3517
24eab124 3518 base_string = end_of_operand_string;
252b5132 3519
24eab124
AM		 3520 if (*base_string == ')')
3521 {
3522 unsigned int parens_balanced = 1;
3523 /* We've already checked that the number of left & right ()'s are
3524 equal, so this loop will not be infinite. */
3525 do
3526 {
3527 base_string--;
3528 if (*base_string == ')')
3529 parens_balanced++;
3530 if (*base_string == '(')
3531 parens_balanced--;
3532 }
3533 while (parens_balanced);
c3332e24 3534
24eab124
AM		 3535 /* If there is a displacement set-up for it to be parsed later. */
3536 displacement_string_start = op_string;
3537 displacement_string_end = base_string;
c3332e24 3538
24eab124 3539 /* Skip past '(' and whitespace. */
252b5132
RH		 3540 ++base_string;
3541 if (is_space_char (*base_string))
24eab124 3542 ++base_string;
252b5132
RH		 3543
3544 if (*base_string == REGISTER_PREFIX
24eab124
AM		 3545 || (allow_naked_reg && i386_is_reg (base_string))
3546 || *base_string == ',')
3547 found_base_index_form = 1;
3548 }
3549
3550 /* If we can't parse a base index register expression, we've found
3551 a pure displacement expression. We set up displacement_string_start
3552 and displacement_string_end for the code below. */
3553 if (!found_base_index_form)
3554 {
3555 displacement_string_start = op_string;
3556 displacement_string_end = end_of_operand_string + 1;
3557 }
3558 else
3559 {
3560 i.types[this_operand] |= BaseIndex;
3561
3562 /* Find base register (if any). */
3563 if (*base_string != ',')
252b5132 3564 {
24eab124 3565 char *end_op;
252b5132 3566
24eab124
AM		 3567 /* Trim off the closing ')' so that parse_register won't
3568 see it. */
3569 END_STRING_AND_SAVE (end_of_operand_string);
3570 i.base_reg = parse_register (base_string, &end_op);
3571 RESTORE_END_STRING (end_of_operand_string);
252b5132 3572
24eab124 3573 if (i.base_reg == NULL)
252b5132
RH		 3574 return 0;
3575
24eab124
AM		 3576 base_string = end_op;
3577 if (is_space_char (*base_string))
c3332e24 3578 ++base_string;
252b5132
RH		 3579 }
3580
24eab124
AM		 3581 /* There may be an index reg or scale factor here. */
3582 if (*base_string == ',')
252b5132 3583 {
24eab124
AM		 3584 ++base_string;
3585 if (is_space_char (*base_string))
c3332e24 3586 ++base_string;
252b5132 3587
24eab124
AM		 3588 if (*base_string == REGISTER_PREFIX
3589 || (allow_naked_reg && i386_is_reg (base_string)))
3590 {
3591 char *end_op;
3592
3593 END_STRING_AND_SAVE (end_of_operand_string);
3594 i.index_reg = parse_register (base_string, &end_op);
3595 RESTORE_END_STRING (end_of_operand_string);
3596
3597 if (i.index_reg == NULL)
3598 return 0;
3599
3600 base_string = end_op;
3601 if (is_space_char (*base_string))
3602 ++base_string;
3603 if (*base_string == ',')
3604 {
3605 ++base_string;
3606 if (is_space_char (*base_string))
3607 ++base_string;
3608 }
3609 else if (*base_string != ')' )
3610 {
3611 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3612 operand_string);
3613 return 0;
3614 }
3615 }
252b5132 3616
24eab124
AM		 3617 /* Check for scale factor. */
3618 if (isdigit ((unsigned char) *base_string))
3619 {
3620 if (!i386_scale (base_string))
3621 return 0;
3622
3623 ++base_string;
3624 if (is_space_char (*base_string))
3625 ++base_string;
3626 if (*base_string != ')')
3627 {
3628 as_bad (_("expecting `)' after scale factor in `%s'"),
3629 operand_string);
3630 return 0;
3631 }
3632 }
3633 else if (!i.index_reg)
3634 {
3635 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3636 *base_string);
3637 return 0;
3638 }
c3332e24 3639 }
24eab124 3640 else if (*base_string != ')')
c3332e24 3641 {
24eab124
AM		 3642 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3643 operand_string);
3644 return 0;
c3332e24 3645 }
24eab124
AM		 3646 }
3647
3648 /* If there's an expression beginning the operand, parse it,
3649 assuming displacement_string_start and
3650 displacement_string_end are meaningful. */
3651 if (displacement_string_start != displacement_string_end)
3652 {
3653 if (!i386_displacement (displacement_string_start,
3654 displacement_string_end))
3655 return 0;
3656 }
3657
3658 /* Special case for (%dx) while doing input/output op. */
3659 if (i.base_reg
3660 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
3661 && i.index_reg == 0
3662 && i.log2_scale_factor == 0
3663 && i.seg[i.mem_operands] == 0
3664 && (i.types[this_operand] & Disp) == 0)
3665 {
3666 i.types[this_operand] = InOutPortReg;
3667 return 1;
3668 }
3669
eecb386c
AM		 3670 if (i386_index_check (operand_string) == 0)
3671 return 0;
24eab124
AM		 3672 i.mem_operands++;
3673 }
3674 else
3675 { /* it's not a memory operand; argh! */
3676 as_bad (_("invalid char %s beginning operand %d `%s'"),
3677 output_invalid (*op_string),
3678 this_operand + 1,
3679 op_string);
3680 return 0;
3681 }
3682 return 1; /* normal return */
252b5132
RH		 3683}
3684\f
3685/*
24eab124 3686 * md_estimate_size_before_relax()
252b5132
RH		 3687 *
3688 * Called just before relax().
3689 * Any symbol that is now undefined will not become defined.
3690 * Return the correct fr_subtype in the frag.
3691 * Return the initial "guess for fr_var" to caller.
3692 * The guess for fr_var is ACTUALLY the growth beyond fr_fix.
3693 * Whatever we do to grow fr_fix or fr_var contributes to our returned value.
3694 * Although it may not be explicit in the frag, pretend fr_var starts with a
3695 * 0 value.
3696 */
3697int
3698md_estimate_size_before_relax (fragP, segment)
3699 register fragS *fragP;
3700 register segT segment;
3701{
3702 register unsigned char *opcode;
3703 register int old_fr_fix;
3704
3705 old_fr_fix = fragP->fr_fix;
3706 opcode = (unsigned char *) fragP->fr_opcode;
3707 /* We've already got fragP->fr_subtype right; all we have to do is
3708 check for un-relaxable symbols. */
3709 if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
3710 {
3711 /* symbol is undefined in this segment */
3712 int code16 = fragP->fr_subtype & CODE16;
3713 int size = code16 ? 2 : 4;
3714 int pcrel_reloc = code16 ? BFD_RELOC_16_PCREL : BFD_RELOC_32_PCREL;
3715
3716 switch (opcode[0])
3717 {
3718 case JUMP_PC_RELATIVE: /* make jmp (0xeb) a dword displacement jump */
3719 opcode[0] = 0xe9; /* dword disp jmp */
3720 fragP->fr_fix += size;
3721 fix_new (fragP, old_fr_fix, size,
3722 fragP->fr_symbol,
3723 fragP->fr_offset, 1,
3724 (GOT_symbol && /* Not quite right - we should switch on
3725 presence of @PLT, but I cannot see how
3726 to get to that from here. We should have
3727 done this in md_assemble to really
3728 get it right all of the time, but I
3729 think it does not matter that much, as
3730 this will be right most of the time. ERY*/
3731 S_GET_SEGMENT(fragP->fr_symbol) == undefined_section)
3732 ? BFD_RELOC_386_PLT32 : pcrel_reloc);
3733 break;
3734
3735 default:
24eab124
AM		 3736 /* This changes the byte-displacement jump 0x7N
3737 to the dword-displacement jump 0x0f8N. */
252b5132
RH		 3738 opcode[1] = opcode[0] + 0x10;
3739 opcode[0] = TWO_BYTE_OPCODE_ESCAPE; /* two-byte escape */
3740 fragP->fr_fix += 1 + size; /* we've added an opcode byte */
3741 fix_new (fragP, old_fr_fix + 1, size,
3742 fragP->fr_symbol,
3743 fragP->fr_offset, 1,
3744 (GOT_symbol && /* Not quite right - we should switch on
24eab124
AM		 3745 presence of @PLT, but I cannot see how
3746 to get to that from here. ERY */
252b5132
RH		 3747 S_GET_SEGMENT(fragP->fr_symbol) == undefined_section)
3748 ? BFD_RELOC_386_PLT32 : pcrel_reloc);
3749 break;
3750 }
3751 frag_wane (fragP);
3752 }
3753 return (fragP->fr_var + fragP->fr_fix - old_fr_fix);
3754} /* md_estimate_size_before_relax() */
3755\f
3756/*
3757 * md_convert_frag();
3758 *
3759 * Called after relax() is finished.
3760 * In: Address of frag.
3761 * fr_type == rs_machine_dependent.
3762 * fr_subtype is what the address relaxed to.
3763 *
3764 * Out: Any fixSs and constants are set up.
3765 * Caller will turn frag into a ".space 0".
3766 */
3767#ifndef BFD_ASSEMBLER
3768void
3769md_convert_frag (headers, sec, fragP)
a04b544b
ILT		 3770 object_headers *headers ATTRIBUTE_UNUSED;
3771 segT sec ATTRIBUTE_UNUSED;
252b5132
RH		 3772 register fragS *fragP;
3773#else
3774void
3775md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 3776 bfd *abfd ATTRIBUTE_UNUSED;
3777 segT sec ATTRIBUTE_UNUSED;
252b5132
RH		 3778 register fragS *fragP;
3779#endif
3780{
3781 register unsigned char *opcode;
3782 unsigned char *where_to_put_displacement = NULL;
3783 unsigned int target_address;
3784 unsigned int opcode_address;
3785 unsigned int extension = 0;
3786 int displacement_from_opcode_start;
3787
3788 opcode = (unsigned char *) fragP->fr_opcode;
3789
3790 /* Address we want to reach in file space. */
3791 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
3792#ifdef BFD_ASSEMBLER /* not needed otherwise? */
49309057 3793 target_address += symbol_get_frag (fragP->fr_symbol)->fr_address;
252b5132
RH		 3794#endif
3795
3796 /* Address opcode resides at in file space. */
3797 opcode_address = fragP->fr_address + fragP->fr_fix;
3798
3799 /* Displacement from opcode start to fill into instruction. */
3800 displacement_from_opcode_start = target_address - opcode_address;
3801
3802 switch (fragP->fr_subtype)
3803 {
3804 case ENCODE_RELAX_STATE (COND_JUMP, SMALL):
3805 case ENCODE_RELAX_STATE (COND_JUMP, SMALL16):
3806 case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL):
3807 case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL16):
3808 /* don't have to change opcode */
3809 extension = 1; /* 1 opcode + 1 displacement */
3810 where_to_put_displacement = &opcode[1];
3811 break;
3812
3813 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
3814 extension = 5; /* 2 opcode + 4 displacement */
3815 opcode[1] = opcode[0] + 0x10;
3816 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
3817 where_to_put_displacement = &opcode[2];
3818 break;
3819
3820 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
3821 extension = 4; /* 1 opcode + 4 displacement */
3822 opcode[0] = 0xe9;
3823 where_to_put_displacement = &opcode[1];
3824 break;
3825
3826 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
3827 extension = 3; /* 2 opcode + 2 displacement */
3828 opcode[1] = opcode[0] + 0x10;
3829 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
3830 where_to_put_displacement = &opcode[2];
3831 break;
3832
3833 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
3834 extension = 2; /* 1 opcode + 2 displacement */
3835 opcode[0] = 0xe9;
3836 where_to_put_displacement = &opcode[1];
3837 break;
3838
3839 default:
3840 BAD_CASE (fragP->fr_subtype);
3841 break;
3842 }
3843 /* now put displacement after opcode */
3844 md_number_to_chars ((char *) where_to_put_displacement,
3845 (valueT) (displacement_from_opcode_start - extension),
3846 SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
3847 fragP->fr_fix += extension;
3848}
3849\f
3850
3851int md_short_jump_size = 2; /* size of byte displacement jmp */
3852int md_long_jump_size = 5; /* size of dword displacement jmp */
3853const int md_reloc_size = 8; /* Size of relocation record */
3854
3855void
3856md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
3857 char *ptr;
3858 addressT from_addr, to_addr;
ab9da554
ILT		 3859 fragS *frag ATTRIBUTE_UNUSED;
3860 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132
RH		 3861{
3862 long offset;
3863
3864 offset = to_addr - (from_addr + 2);
3865 md_number_to_chars (ptr, (valueT) 0xeb, 1); /* opcode for byte-disp jump */
3866 md_number_to_chars (ptr + 1, (valueT) offset, 1);
3867}
3868
3869void
3870md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
3871 char *ptr;
3872 addressT from_addr, to_addr;
3873 fragS *frag;
3874 symbolS *to_symbol;
3875{
3876 long offset;
3877
3878 if (flag_do_long_jump)
3879 {
3880 offset = to_addr - S_GET_VALUE (to_symbol);
3881 md_number_to_chars (ptr, (valueT) 0xe9, 1);/* opcode for long jmp */
3882 md_number_to_chars (ptr + 1, (valueT) offset, 4);
3883 fix_new (frag, (ptr + 1) - frag->fr_literal, 4,
3884 to_symbol, (offsetT) 0, 0, BFD_RELOC_32);
3885 }
3886 else
3887 {
3888 offset = to_addr - (from_addr + 5);
3889 md_number_to_chars (ptr, (valueT) 0xe9, 1);
3890 md_number_to_chars (ptr + 1, (valueT) offset, 4);
3891 }
3892}
3893\f
3894/* Apply a fixup (fixS) to segment data, once it has been determined
3895 by our caller that we have all the info we need to fix it up.
3896
3897 On the 386, immediates, displacements, and data pointers are all in
3898 the same (little-endian) format, so we don't need to care about which
3899 we are handling. */
3900
3901int
3902md_apply_fix3 (fixP, valp, seg)
3903 fixS *fixP; /* The fix we're to put in. */
3904 valueT *valp; /* Pointer to the value of the bits. */
a04b544b 3905 segT seg ATTRIBUTE_UNUSED; /* Segment fix is from. */
252b5132
RH		 3906{
3907 register char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
3908 valueT value = *valp;
3909
e1b283bb 3910#if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
93382f6d
AM		 3911 if (fixP->fx_pcrel)
3912 {
3913 switch (fixP->fx_r_type)
3914 {
5865bb77
ILT		 3915 default:
3916 break;
3917
93382f6d
AM		 3918 case BFD_RELOC_32:
3919 fixP->fx_r_type = BFD_RELOC_32_PCREL;
3920 break;
3921 case BFD_RELOC_16:
3922 fixP->fx_r_type = BFD_RELOC_16_PCREL;
3923 break;
3924 case BFD_RELOC_8:
3925 fixP->fx_r_type = BFD_RELOC_8_PCREL;
3926 break;
3927 }
3928 }
252b5132 3929
252b5132
RH		 3930 /*
3931 * This is a hack. There should be a better way to
3932 * handle this.
3933 */
93382f6d
AM		 3934 if ((fixP->fx_r_type == BFD_RELOC_32_PCREL
3935 || fixP->fx_r_type == BFD_RELOC_16_PCREL
3936 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
3937 && fixP->fx_addsy)
252b5132
RH		 3938 {
3939#ifndef OBJ_AOUT
3940 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
3941#ifdef TE_PE
3942 || OUTPUT_FLAVOR == bfd_target_coff_flavour
3943#endif
3944 )
3945 value += fixP->fx_where + fixP->fx_frag->fr_address;
3946#endif
3947#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3948 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
3949 && (S_GET_SEGMENT (fixP->fx_addsy) == seg
49309057 3950 || symbol_section_p (fixP->fx_addsy))
252b5132
RH		 3951 && ! S_IS_EXTERNAL (fixP->fx_addsy)
3952 && ! S_IS_WEAK (fixP->fx_addsy)
3953 && S_IS_DEFINED (fixP->fx_addsy)
3954 && ! S_IS_COMMON (fixP->fx_addsy))
3955 {
3956 /* Yes, we add the values in twice. This is because
3957 bfd_perform_relocation subtracts them out again. I think
3958 bfd_perform_relocation is broken, but I don't dare change
3959 it. FIXME. */
3960 value += fixP->fx_where + fixP->fx_frag->fr_address;
3961 }
3962#endif
3963#if defined (OBJ_COFF) && defined (TE_PE)
3964 /* For some reason, the PE format does not store a section
24eab124 3965 address offset for a PC relative symbol. */
252b5132
RH		 3966 if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
3967 value += md_pcrel_from (fixP);
3968#endif
3969 }
3970
3971 /* Fix a few things - the dynamic linker expects certain values here,
3972 and we must not dissappoint it. */
3973#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3974 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
3975 && fixP->fx_addsy)
3976 switch (fixP->fx_r_type) {
3977 case BFD_RELOC_386_PLT32:
3978 /* Make the jump instruction point to the address of the operand. At
3979 runtime we merely add the offset to the actual PLT entry. */
3980 value = 0xfffffffc;
3981 break;
3982 case BFD_RELOC_386_GOTPC:
3983/*
24eab124 3984 * This is tough to explain. We end up with this one if we have
252b5132
RH		 3985 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
3986 * here is to obtain the absolute address of the GOT, and it is strongly
3987 * preferable from a performance point of view to avoid using a runtime
c3332e24 3988 * relocation for this. The actual sequence of instructions often look
252b5132 3989 * something like:
c3332e24 3990 *
24eab124 3991 * call .L66
252b5132 3992 * .L66:
24eab124
AM		 3993 * popl %ebx
3994 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
c3332e24 3995 *
24eab124 3996 * The call and pop essentially return the absolute address of
252b5132
RH		 3997 * the label .L66 and store it in %ebx. The linker itself will
3998 * ultimately change the first operand of the addl so that %ebx points to
3999 * the GOT, but to keep things simple, the .o file must have this operand
4000 * set so that it generates not the absolute address of .L66, but the
4001 * absolute address of itself. This allows the linker itself simply
4002 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4003 * added in, and the addend of the relocation is stored in the operand
4004 * field for the instruction itself.
c3332e24 4005 *
24eab124 4006 * Our job here is to fix the operand so that it would add the correct
252b5132
RH		 4007 * offset so that %ebx would point to itself. The thing that is tricky is
4008 * that .-.L66 will point to the beginning of the instruction, so we need
4009 * to further modify the operand so that it will point to itself.
4010 * There are other cases where you have something like:
c3332e24 4011 *
24eab124 4012 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
c3332e24 4013 *
252b5132 4014 * and here no correction would be required. Internally in the assembler
c3332e24 4015 * we treat operands of this form as not being pcrel since the '.' is
252b5132
RH		 4016 * explicitly mentioned, and I wonder whether it would simplify matters
4017 * to do it this way. Who knows. In earlier versions of the PIC patches,
4018 * the pcrel_adjust field was used to store the correction, but since the
4019 * expression is not pcrel, I felt it would be confusing to do it this way.
4020 */
4021 value -= 1;
4022 break;
4023 case BFD_RELOC_386_GOT32:
24eab124 4024 value = 0; /* Fully resolved at runtime. No addend. */
252b5132
RH		 4025 break;
4026 case BFD_RELOC_386_GOTOFF:
4027 break;
4028
4029 case BFD_RELOC_VTABLE_INHERIT:
4030 case BFD_RELOC_VTABLE_ENTRY:
4031 fixP->fx_done = 0;
4032 return 1;
4033
4034 default:
4035 break;
4036 }
93382f6d
AM		 4037#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4038 *valp = value;
4039#endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
252b5132
RH		 4040 md_number_to_chars (p, value, fixP->fx_size);
4041
4042 return 1;
4043}
4044
4045#if 0
4046/* This is never used. */
4047long /* Knows about the byte order in a word. */
4048md_chars_to_number (con, nbytes)
4049 unsigned char con[]; /* Low order byte 1st. */
4050 int nbytes; /* Number of bytes in the input. */
4051{
4052 long retval;
4053 for (retval = 0, con += nbytes - 1; nbytes--; con--)
4054 {
4055 retval <<= BITS_PER_CHAR;
4056 retval |= *con;
4057 }
4058 return retval;
4059}
4060#endif /* 0 */
4061\f
4062
4063#define MAX_LITTLENUMS 6
4064
4065/* Turn the string pointed to by litP into a floating point constant of type
4066 type, and emit the appropriate bytes. The number of LITTLENUMS emitted
4067 is stored in *sizeP . An error message is returned, or NULL on OK. */
4068char *
4069md_atof (type, litP, sizeP)
4070 char type;
4071 char *litP;
4072 int *sizeP;
4073{
4074 int prec;
4075 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4076 LITTLENUM_TYPE *wordP;
4077 char *t;
4078
4079 switch (type)
4080 {
4081 case 'f':
4082 case 'F':
4083 prec = 2;
4084 break;
4085
4086 case 'd':
4087 case 'D':
4088 prec = 4;
4089 break;
4090
4091 case 'x':
4092 case 'X':
4093 prec = 5;
4094 break;
4095
4096 default:
4097 *sizeP = 0;
4098 return _("Bad call to md_atof ()");
4099 }
4100 t = atof_ieee (input_line_pointer, type, words);
4101 if (t)
4102 input_line_pointer = t;
4103
4104 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4105 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4106 the bigendian 386. */
4107 for (wordP = words + prec - 1; prec--;)
4108 {
4109 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
4110 litP += sizeof (LITTLENUM_TYPE);
4111 }
4112 return 0;
4113}
4114\f
4115char output_invalid_buf[8];
4116
4117static char * output_invalid PARAMS ((int));
4118
4119static char *
4120output_invalid (c)
4121 int c;
4122{
4123 if (isprint (c))
4124 sprintf (output_invalid_buf, "'%c'", c);
4125 else
4126 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
4127 return output_invalid_buf;
4128}
4129
4130/* REG_STRING starts *before* REGISTER_PREFIX. */
4131
4132static const reg_entry * parse_register PARAMS ((char *, char **));
4133
4134static const reg_entry *
4135parse_register (reg_string, end_op)
4136 char *reg_string;
4137 char **end_op;
4138{
4139 register char *s = reg_string;
4140 register char *p;
4141 char reg_name_given[MAX_REG_NAME_SIZE + 1];
4142 const reg_entry *r;
4143
4144 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4145 if (*s == REGISTER_PREFIX)
4146 ++s;
4147
4148 if (is_space_char (*s))
4149 ++s;
4150
4151 p = reg_name_given;
4152 while ((*p++ = register_chars[(unsigned char) *s++]) != '\0')
4153 {
4154 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
4155 {
24eab124
AM		 4156 if (!allow_naked_reg)
4157 {
252b5132
RH		 4158 *p = '\0';
4159 as_bad (_("bad register name `%s'"), reg_name_given);
24eab124 4160 }
252b5132
RH		 4161 return (const reg_entry *) NULL;
4162 }
4163 }
4164
4165 *end_op = s - 1;
4166
4167 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
4168
4169 if (r == NULL)
4170 {
4171 if (!allow_naked_reg)
24eab124 4172 as_bad (_("bad register name `%s'"), reg_name_given);
252b5132
RH		 4173 return (const reg_entry *) NULL;
4174 }
4175
4176 return r;
4177}
4178\f
4179#ifdef OBJ_ELF
4180CONST char *md_shortopts = "kmVQ:";
4181#else
4182CONST char *md_shortopts = "m";
4183#endif
4184struct option md_longopts[] = {
4185 {NULL, no_argument, NULL, 0}
4186};
4187size_t md_longopts_size = sizeof (md_longopts);
4188
4189int
4190md_parse_option (c, arg)
4191 int c;
ab9da554 4192 char *arg ATTRIBUTE_UNUSED;
252b5132
RH		 4193{
4194 switch (c)
4195 {
4196 case 'm':
4197 flag_do_long_jump = 1;
4198 break;
4199
4200#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4201 /* -k: Ignore for FreeBSD compatibility. */
4202 case 'k':
4203 break;
4204
4205 /* -V: SVR4 argument to print version ID. */
4206 case 'V':
4207 print_version_id ();
4208 break;
4209
4210 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4211 should be emitted or not. FIXME: Not implemented. */
4212 case 'Q':
4213 break;
4214#endif
4215
4216 default:
4217 return 0;
4218 }
4219 return 1;
4220}
4221
4222void
4223md_show_usage (stream)
4224 FILE *stream;
4225{
4226 fprintf (stream, _("\
4227-m do long jump\n"));
4228}
4229
4230#ifdef BFD_ASSEMBLER
4231#ifdef OBJ_MAYBE_ELF
4232#ifdef OBJ_MAYBE_COFF
4233
4234/* Pick the target format to use. */
4235
4236const char *
4237i386_target_format ()
4238{
4239 switch (OUTPUT_FLAVOR)
4240 {
4241 case bfd_target_coff_flavour:
4242 return "coff-i386";
4243 case bfd_target_elf_flavour:
4244 return "elf32-i386";
4245 default:
4246 abort ();
4247 return NULL;
4248 }
4249}
4250
4251#endif /* OBJ_MAYBE_COFF */
4252#endif /* OBJ_MAYBE_ELF */
4253#endif /* BFD_ASSEMBLER */
4254\f
4255/* ARGSUSED */
4256symbolS *
4257md_undefined_symbol (name)
4258 char *name;
4259{
24eab124
AM		 4260 if (*name == '_' && *(name+1) == 'G'
4261 && strcmp(name, GLOBAL_OFFSET_TABLE_NAME) == 0)
4262 {
4263 if (!GOT_symbol)
4264 {
4265 if (symbol_find (name))
4266 as_bad (_("GOT already in symbol table"));
4267 GOT_symbol = symbol_new (name, undefined_section,
4268 (valueT) 0, &zero_address_frag);
4269 };
4270 return GOT_symbol;
4271 }
252b5132
RH		 4272 return 0;
4273}
4274
4275/* Round up a section size to the appropriate boundary. */
4276valueT
4277md_section_align (segment, size)
ab9da554 4278 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 4279 valueT size;
4280{
4281#ifdef OBJ_AOUT
4282#ifdef BFD_ASSEMBLER
4283 /* For a.out, force the section size to be aligned. If we don't do
4284 this, BFD will align it for us, but it will not write out the
4285 final bytes of the section. This may be a bug in BFD, but it is
4286 easier to fix it here since that is how the other a.out targets
4287 work. */
4288 int align;
4289
4290 align = bfd_get_section_alignment (stdoutput, segment);
4291 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
4292#endif
4293#endif
4294
4295 return size;
4296}
4297
4298/* On the i386, PC-relative offsets are relative to the start of the
4299 next instruction. That is, the address of the offset, plus its
4300 size, since the offset is always the last part of the insn. */
4301
4302long
4303md_pcrel_from (fixP)
4304 fixS *fixP;
4305{
4306 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
4307}
4308
4309#ifndef I386COFF
4310
4311static void
4312s_bss (ignore)
ab9da554 4313 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 4314{
4315 register int temp;
4316
4317 temp = get_absolute_expression ();
4318 subseg_set (bss_section, (subsegT) temp);
4319 demand_empty_rest_of_line ();
4320}
4321
4322#endif
4323
4324
4325#ifdef BFD_ASSEMBLER
4326
4327void
4328i386_validate_fix (fixp)
4329 fixS *fixp;
4330{
4331 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
4332 {
4333 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
4334 fixp->fx_subsy = 0;
4335 }
4336}
4337
252b5132
RH		 4338arelent *
4339tc_gen_reloc (section, fixp)
ab9da554 4340 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 4341 fixS *fixp;
4342{
4343 arelent *rel;
4344 bfd_reloc_code_real_type code;
4345
4346 switch (fixp->fx_r_type)
4347 {
4348 case BFD_RELOC_386_PLT32:
4349 case BFD_RELOC_386_GOT32:
4350 case BFD_RELOC_386_GOTOFF:
4351 case BFD_RELOC_386_GOTPC:
4352 case BFD_RELOC_RVA:
4353 case BFD_RELOC_VTABLE_ENTRY:
4354 case BFD_RELOC_VTABLE_INHERIT:
4355 code = fixp->fx_r_type;
4356 break;
4357 default:
93382f6d 4358 if (fixp->fx_pcrel)
252b5132 4359 {
93382f6d
AM		 4360 switch (fixp->fx_size)
4361 {
4362 default:
4363 as_bad (_("Can not do %d byte pc-relative relocation"),
4364 fixp->fx_size);
4365 code = BFD_RELOC_32_PCREL;
4366 break;
4367 case 1: code = BFD_RELOC_8_PCREL; break;
4368 case 2: code = BFD_RELOC_16_PCREL; break;
4369 case 4: code = BFD_RELOC_32_PCREL; break;
4370 }
4371 }
4372 else
4373 {
4374 switch (fixp->fx_size)
4375 {
4376 default:
4377 as_bad (_("Can not do %d byte relocation"), fixp->fx_size);
4378 code = BFD_RELOC_32;
4379 break;
4380 case 1: code = BFD_RELOC_8; break;
4381 case 2: code = BFD_RELOC_16; break;
4382 case 4: code = BFD_RELOC_32; break;
4383 }
252b5132
RH		 4384 }
4385 break;
4386 }
252b5132
RH		 4387
4388 if (code == BFD_RELOC_32
4389 && GOT_symbol
4390 && fixp->fx_addsy == GOT_symbol)
4391 code = BFD_RELOC_386_GOTPC;
4392
4393 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 4394 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
4395 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 4396
4397 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
4398 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4399 vtable entry to be used in the relocation's section offset. */
4400 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4401 rel->address = fixp->fx_offset;
4402
4403 if (fixp->fx_pcrel)
4404 rel->addend = fixp->fx_addnumber;
4405 else
4406 rel->addend = 0;
4407
4408 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
4409 if (rel->howto == NULL)
4410 {
4411 as_bad_where (fixp->fx_file, fixp->fx_line,
4412 _("Cannot represent relocation type %s"),
4413 bfd_get_reloc_code_name (code));
4414 /* Set howto to a garbage value so that we can keep going. */
4415 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
4416 assert (rel->howto != NULL);
4417 }
4418
4419 return rel;
4420}
4421
4422#else /* ! BFD_ASSEMBLER */
4423
4424#if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4425void
4426tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4427 char *where;
4428 fixS *fixP;
4429 relax_addressT segment_address_in_file;
4430{
4431 /*
4432 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4433 * Out: GNU LD relocation length code: 0, 1, or 2.
4434 */
4435
4436 static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4437 long r_symbolnum;
4438
4439 know (fixP->fx_addsy != NULL);
4440
4441 md_number_to_chars (where,
4442 (valueT) (fixP->fx_frag->fr_address
4443 + fixP->fx_where - segment_address_in_file),
4444 4);
4445
4446 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4447 ? S_GET_TYPE (fixP->fx_addsy)
4448 : fixP->fx_addsy->sy_number);
4449
4450 where[6] = (r_symbolnum >> 16) & 0x0ff;
4451 where[5] = (r_symbolnum >> 8) & 0x0ff;
4452 where[4] = r_symbolnum & 0x0ff;
4453 where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08)
4454 | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06)
4455 | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f));
4456}
4457
4458#endif /* OBJ_AOUT or OBJ_BOUT */
4459
4460#if defined (I386COFF)
4461
4462short
4463tc_coff_fix2rtype (fixP)
4464 fixS *fixP;
4465{
4466 if (fixP->fx_r_type == R_IMAGEBASE)
4467 return R_IMAGEBASE;
4468
4469 return (fixP->fx_pcrel ?
4470 (fixP->fx_size == 1 ? R_PCRBYTE :
4471 fixP->fx_size == 2 ? R_PCRWORD :
4472 R_PCRLONG) :
4473 (fixP->fx_size == 1 ? R_RELBYTE :
4474 fixP->fx_size == 2 ? R_RELWORD :
4475 R_DIR32));
4476}
4477
4478int
4479tc_coff_sizemachdep (frag)
4480 fragS *frag;
4481{
4482 if (frag->fr_next)
4483 return (frag->fr_next->fr_address - frag->fr_address);
4484 else
4485 return 0;
4486}
4487
4488#endif /* I386COFF */
4489
93382f6d 4490#endif /* ! BFD_ASSEMBLER */
252b5132
RH		 4491\f
4492/* end of tc-i386.c */
GDB Binutils - Deliverables
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