Commit | Line | Data |
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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
f7e42eb4 | 2 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
0bfee649 | 3 | 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
47926f60 | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | |
6 | This file is part of GAS, the GNU Assembler. | |
7 | ||
8 | GAS is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
11 | any later version. |
12 | ||
13 | GAS is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
20 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
21 | 02110-1301, USA. */ | |
252b5132 | 22 | |
47926f60 KH |
23 | /* Intel 80386 machine specific gas. |
24 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 25 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
27 | Bugs & suggestions are completely welcome. This is free software. |
28 | Please help us make it better. */ | |
252b5132 | 29 | |
252b5132 | 30 | #include "as.h" |
3882b010 | 31 | #include "safe-ctype.h" |
252b5132 | 32 | #include "subsegs.h" |
316e2c05 | 33 | #include "dwarf2dbg.h" |
54cfded0 | 34 | #include "dw2gencfi.h" |
d2b2c203 | 35 | #include "elf/x86-64.h" |
40fb9820 | 36 | #include "opcodes/i386-init.h" |
252b5132 | 37 | |
252b5132 RH |
38 | #ifndef REGISTER_WARNINGS |
39 | #define REGISTER_WARNINGS 1 | |
40 | #endif | |
41 | ||
c3332e24 | 42 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 43 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
44 | #endif |
45 | ||
29b0f896 AM |
46 | #ifndef DEFAULT_ARCH |
47 | #define DEFAULT_ARCH "i386" | |
246fcdee | 48 | #endif |
252b5132 | 49 | |
edde18a5 AM |
50 | #ifndef INLINE |
51 | #if __GNUC__ >= 2 | |
52 | #define INLINE __inline__ | |
53 | #else | |
54 | #define INLINE | |
55 | #endif | |
56 | #endif | |
57 | ||
6305a203 L |
58 | /* Prefixes will be emitted in the order defined below. |
59 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
60 | instruction, and so must come before any prefixes. | |
61 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
62 | LOCKREP_PREFIX. */ | |
63 | #define WAIT_PREFIX 0 | |
64 | #define SEG_PREFIX 1 | |
65 | #define ADDR_PREFIX 2 | |
66 | #define DATA_PREFIX 3 | |
67 | #define LOCKREP_PREFIX 4 | |
68 | #define REX_PREFIX 5 /* must come last. */ | |
69 | #define MAX_PREFIXES 6 /* max prefixes per opcode */ | |
70 | ||
71 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
72 | #define REGISTER_PREFIX '%' | |
73 | #define IMMEDIATE_PREFIX '$' | |
74 | #define ABSOLUTE_PREFIX '*' | |
75 | ||
76 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
77 | memory operand size in Intel syntax. */ | |
78 | #define WORD_MNEM_SUFFIX 'w' | |
79 | #define BYTE_MNEM_SUFFIX 'b' | |
80 | #define SHORT_MNEM_SUFFIX 's' | |
81 | #define LONG_MNEM_SUFFIX 'l' | |
82 | #define QWORD_MNEM_SUFFIX 'q' | |
83 | #define XMMWORD_MNEM_SUFFIX 'x' | |
c0f3af97 | 84 | #define YMMWORD_MNEM_SUFFIX 'y' |
6305a203 L |
85 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
86 | in instructions. */ | |
87 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' | |
88 | ||
89 | #define END_OF_INSN '\0' | |
90 | ||
91 | /* | |
92 | 'templates' is for grouping together 'template' structures for opcodes | |
93 | of the same name. This is only used for storing the insns in the grand | |
94 | ole hash table of insns. | |
95 | The templates themselves start at START and range up to (but not including) | |
96 | END. | |
97 | */ | |
98 | typedef struct | |
99 | { | |
d3ce72d0 NC |
100 | const insn_template *start; |
101 | const insn_template *end; | |
6305a203 L |
102 | } |
103 | templates; | |
104 | ||
105 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
106 | typedef struct | |
107 | { | |
108 | unsigned int regmem; /* codes register or memory operand */ | |
109 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
110 | unsigned int mode; /* how to interpret regmem & reg */ | |
111 | } | |
112 | modrm_byte; | |
113 | ||
114 | /* x86-64 extension prefix. */ | |
115 | typedef int rex_byte; | |
116 | ||
6305a203 L |
117 | /* 386 opcode byte to code indirect addressing. */ |
118 | typedef struct | |
119 | { | |
120 | unsigned base; | |
121 | unsigned index; | |
122 | unsigned scale; | |
123 | } | |
124 | sib_byte; | |
125 | ||
6305a203 L |
126 | /* x86 arch names, types and features */ |
127 | typedef struct | |
128 | { | |
129 | const char *name; /* arch name */ | |
130 | enum processor_type type; /* arch type */ | |
131 | i386_cpu_flags flags; /* cpu feature flags */ | |
132 | } | |
133 | arch_entry; | |
134 | ||
e3bb37b5 L |
135 | static void set_code_flag (int); |
136 | static void set_16bit_gcc_code_flag (int); | |
137 | static void set_intel_syntax (int); | |
1efbbeb4 | 138 | static void set_intel_mnemonic (int); |
db51cc60 | 139 | static void set_allow_index_reg (int); |
cb19c032 | 140 | static void set_sse_check (int); |
e3bb37b5 | 141 | static void set_cpu_arch (int); |
6482c264 | 142 | #ifdef TE_PE |
e3bb37b5 | 143 | static void pe_directive_secrel (int); |
6482c264 | 144 | #endif |
e3bb37b5 L |
145 | static void signed_cons (int); |
146 | static char *output_invalid (int c); | |
ee86248c JB |
147 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
148 | const char *); | |
149 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
150 | const char *); | |
a7619375 | 151 | static int i386_att_operand (char *); |
e3bb37b5 | 152 | static int i386_intel_operand (char *, int); |
ee86248c JB |
153 | static int i386_intel_simplify (expressionS *); |
154 | static int i386_intel_parse_name (const char *, expressionS *); | |
e3bb37b5 L |
155 | static const reg_entry *parse_register (char *, char **); |
156 | static char *parse_insn (char *, char *); | |
157 | static char *parse_operands (char *, const char *); | |
158 | static void swap_operands (void); | |
4d456e3d | 159 | static void swap_2_operands (int, int); |
e3bb37b5 L |
160 | static void optimize_imm (void); |
161 | static void optimize_disp (void); | |
d3ce72d0 | 162 | static const insn_template *match_template (void); |
e3bb37b5 L |
163 | static int check_string (void); |
164 | static int process_suffix (void); | |
165 | static int check_byte_reg (void); | |
166 | static int check_long_reg (void); | |
167 | static int check_qword_reg (void); | |
168 | static int check_word_reg (void); | |
169 | static int finalize_imm (void); | |
170 | static int process_operands (void); | |
171 | static const seg_entry *build_modrm_byte (void); | |
172 | static void output_insn (void); | |
173 | static void output_imm (fragS *, offsetT); | |
174 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 175 | #ifndef I386COFF |
e3bb37b5 | 176 | static void s_bss (int); |
252b5132 | 177 | #endif |
17d4e2a2 L |
178 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
179 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
180 | #endif | |
252b5132 | 181 | |
a847613f | 182 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 183 | |
c0f3af97 L |
184 | /* VEX prefix. */ |
185 | typedef struct | |
186 | { | |
187 | /* VEX prefix is either 2 byte or 3 byte. */ | |
188 | unsigned char bytes[3]; | |
189 | unsigned int length; | |
190 | /* Destination or source register specifier. */ | |
191 | const reg_entry *register_specifier; | |
192 | } vex_prefix; | |
193 | ||
252b5132 | 194 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 195 | i386_insn. */ |
252b5132 | 196 | |
520dc8e8 AM |
197 | union i386_op |
198 | { | |
199 | expressionS *disps; | |
200 | expressionS *imms; | |
201 | const reg_entry *regs; | |
202 | }; | |
203 | ||
252b5132 RH |
204 | struct _i386_insn |
205 | { | |
47926f60 | 206 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 207 | insn_template tm; |
252b5132 | 208 | |
7d5e4556 L |
209 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
210 | or qword, if given. */ | |
252b5132 RH |
211 | char suffix; |
212 | ||
47926f60 | 213 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
214 | unsigned int operands; |
215 | ||
216 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
217 | of given register, displacement, memory operands and immediate | |
47926f60 | 218 | operands. */ |
252b5132 RH |
219 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
220 | ||
221 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 222 | use OP[i] for the corresponding operand. */ |
40fb9820 | 223 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 224 | |
520dc8e8 AM |
225 | /* Displacement expression, immediate expression, or register for each |
226 | operand. */ | |
227 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 228 | |
3e73aa7c JH |
229 | /* Flags for operands. */ |
230 | unsigned int flags[MAX_OPERANDS]; | |
231 | #define Operand_PCrel 1 | |
232 | ||
252b5132 | 233 | /* Relocation type for operand */ |
f86103b7 | 234 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 235 | |
252b5132 RH |
236 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
237 | the base index byte below. */ | |
238 | const reg_entry *base_reg; | |
239 | const reg_entry *index_reg; | |
240 | unsigned int log2_scale_factor; | |
241 | ||
242 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 243 | explicit segment overrides are given. */ |
ce8a8b2f | 244 | const seg_entry *seg[2]; |
252b5132 RH |
245 | |
246 | /* PREFIX holds all the given prefix opcodes (usually null). | |
247 | PREFIXES is the number of prefix opcodes. */ | |
248 | unsigned int prefixes; | |
249 | unsigned char prefix[MAX_PREFIXES]; | |
250 | ||
251 | /* RM and SIB are the modrm byte and the sib byte where the | |
c1e679ec | 252 | addressing modes of this insn are encoded. */ |
252b5132 | 253 | modrm_byte rm; |
3e73aa7c | 254 | rex_byte rex; |
252b5132 | 255 | sib_byte sib; |
c0f3af97 | 256 | vex_prefix vex; |
b6169b20 L |
257 | |
258 | /* Swap operand in encoding. */ | |
259 | unsigned int swap_operand : 1; | |
252b5132 RH |
260 | }; |
261 | ||
262 | typedef struct _i386_insn i386_insn; | |
263 | ||
264 | /* List of chars besides those in app.c:symbol_chars that can start an | |
265 | operand. Used to prevent the scrubber eating vital white-space. */ | |
32137342 | 266 | const char extra_symbol_chars[] = "*%-([" |
252b5132 | 267 | #ifdef LEX_AT |
32137342 NC |
268 | "@" |
269 | #endif | |
270 | #ifdef LEX_QM | |
271 | "?" | |
252b5132 | 272 | #endif |
32137342 | 273 | ; |
252b5132 | 274 | |
29b0f896 AM |
275 | #if (defined (TE_I386AIX) \ |
276 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
3896cfd5 | 277 | && !defined (TE_GNU) \ |
29b0f896 | 278 | && !defined (TE_LINUX) \ |
32137342 | 279 | && !defined (TE_NETWARE) \ |
29b0f896 AM |
280 | && !defined (TE_FreeBSD) \ |
281 | && !defined (TE_NetBSD))) | |
252b5132 | 282 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
283 | pre-processor is disabled, these aren't very useful. The option |
284 | --divide will remove '/' from this list. */ | |
285 | const char *i386_comment_chars = "#/"; | |
286 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 287 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 288 | |
b3b91714 AM |
289 | #else |
290 | const char *i386_comment_chars = "#"; | |
291 | #define PREFIX_SEPARATOR '/' | |
292 | #endif | |
293 | ||
252b5132 RH |
294 | /* This array holds the chars that only start a comment at the beginning of |
295 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
296 | .line and .file directives will appear in the pre-processed output. |
297 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 298 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
299 | #NO_APP at the beginning of its output. |
300 | Also note that comments started like this one will always work if | |
252b5132 | 301 | '/' isn't otherwise defined. */ |
b3b91714 | 302 | const char line_comment_chars[] = "#/"; |
252b5132 | 303 | |
63a0b638 | 304 | const char line_separator_chars[] = ";"; |
252b5132 | 305 | |
ce8a8b2f AM |
306 | /* Chars that can be used to separate mant from exp in floating point |
307 | nums. */ | |
252b5132 RH |
308 | const char EXP_CHARS[] = "eE"; |
309 | ||
ce8a8b2f AM |
310 | /* Chars that mean this number is a floating point constant |
311 | As in 0f12.456 | |
312 | or 0d1.2345e12. */ | |
252b5132 RH |
313 | const char FLT_CHARS[] = "fFdDxX"; |
314 | ||
ce8a8b2f | 315 | /* Tables for lexical analysis. */ |
252b5132 RH |
316 | static char mnemonic_chars[256]; |
317 | static char register_chars[256]; | |
318 | static char operand_chars[256]; | |
319 | static char identifier_chars[256]; | |
320 | static char digit_chars[256]; | |
321 | ||
ce8a8b2f | 322 | /* Lexical macros. */ |
252b5132 RH |
323 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
324 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
325 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
326 | #define is_space_char(x) ((x) == ' ') | |
327 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
328 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
329 | ||
0234cb7c | 330 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
331 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
332 | ||
333 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
334 | effect this we maintain a stack of saved characters that we've smashed | |
335 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 336 | assembler instruction). */ |
252b5132 | 337 | static char save_stack[32]; |
ce8a8b2f | 338 | static char *save_stack_p; |
252b5132 RH |
339 | #define END_STRING_AND_SAVE(s) \ |
340 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
341 | #define RESTORE_END_STRING(s) \ | |
342 | do { *(s) = *--save_stack_p; } while (0) | |
343 | ||
47926f60 | 344 | /* The instruction we're assembling. */ |
252b5132 RH |
345 | static i386_insn i; |
346 | ||
347 | /* Possible templates for current insn. */ | |
348 | static const templates *current_templates; | |
349 | ||
31b2323c L |
350 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
351 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
352 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 353 | |
47926f60 | 354 | /* Current operand we are working on. */ |
ee86248c | 355 | static int this_operand = -1; |
252b5132 | 356 | |
3e73aa7c JH |
357 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
358 | these. */ | |
359 | ||
360 | enum flag_code { | |
361 | CODE_32BIT, | |
362 | CODE_16BIT, | |
363 | CODE_64BIT }; | |
364 | ||
365 | static enum flag_code flag_code; | |
4fa24527 | 366 | static unsigned int object_64bit; |
3e73aa7c JH |
367 | static int use_rela_relocations = 0; |
368 | ||
369 | /* The names used to print error messages. */ | |
b77a7acd | 370 | static const char *flag_code_names[] = |
3e73aa7c JH |
371 | { |
372 | "32", | |
373 | "16", | |
374 | "64" | |
375 | }; | |
252b5132 | 376 | |
47926f60 KH |
377 | /* 1 for intel syntax, |
378 | 0 if att syntax. */ | |
379 | static int intel_syntax = 0; | |
252b5132 | 380 | |
1efbbeb4 L |
381 | /* 1 for intel mnemonic, |
382 | 0 if att mnemonic. */ | |
383 | static int intel_mnemonic = !SYSV386_COMPAT; | |
384 | ||
5209009a | 385 | /* 1 if support old (<= 2.8.1) versions of gcc. */ |
1efbbeb4 L |
386 | static int old_gcc = OLDGCC_COMPAT; |
387 | ||
a60de03c JB |
388 | /* 1 if pseudo registers are permitted. */ |
389 | static int allow_pseudo_reg = 0; | |
390 | ||
47926f60 KH |
391 | /* 1 if register prefix % not required. */ |
392 | static int allow_naked_reg = 0; | |
252b5132 | 393 | |
ba104c83 | 394 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
395 | static int allow_index_reg = 0; |
396 | ||
daf50ae7 L |
397 | static enum |
398 | { | |
399 | sse_check_none = 0, | |
400 | sse_check_warning, | |
401 | sse_check_error | |
402 | } | |
403 | sse_check; | |
404 | ||
2ca3ace5 L |
405 | /* Register prefix used for error message. */ |
406 | static const char *register_prefix = "%"; | |
407 | ||
47926f60 KH |
408 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
409 | leave, push, and pop instructions so that gcc has the same stack | |
410 | frame as in 32 bit mode. */ | |
411 | static char stackop_size = '\0'; | |
eecb386c | 412 | |
12b55ccc L |
413 | /* Non-zero to optimize code alignment. */ |
414 | int optimize_align_code = 1; | |
415 | ||
47926f60 KH |
416 | /* Non-zero to quieten some warnings. */ |
417 | static int quiet_warnings = 0; | |
a38cf1db | 418 | |
47926f60 KH |
419 | /* CPU name. */ |
420 | static const char *cpu_arch_name = NULL; | |
6305a203 | 421 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 422 | |
47926f60 | 423 | /* CPU feature flags. */ |
40fb9820 L |
424 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
425 | ||
ccc9c027 L |
426 | /* If we have selected a cpu we are generating instructions for. */ |
427 | static int cpu_arch_tune_set = 0; | |
428 | ||
9103f4f4 | 429 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 430 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 L |
431 | |
432 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 433 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 434 | |
ccc9c027 | 435 | /* CPU instruction set architecture used. */ |
fbf3f584 | 436 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 437 | |
9103f4f4 | 438 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 439 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 440 | |
fddf5b5b AM |
441 | /* If set, conditional jumps are not automatically promoted to handle |
442 | larger than a byte offset. */ | |
443 | static unsigned int no_cond_jump_promotion = 0; | |
444 | ||
c0f3af97 L |
445 | /* Encode SSE instructions with VEX prefix. */ |
446 | static unsigned int sse2avx; | |
447 | ||
29b0f896 | 448 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 449 | static symbolS *GOT_symbol; |
29b0f896 | 450 | |
a4447b93 RH |
451 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
452 | unsigned int x86_dwarf2_return_column; | |
453 | ||
454 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
455 | int x86_cie_data_alignment; | |
456 | ||
252b5132 | 457 | /* Interface to relax_segment. |
fddf5b5b AM |
458 | There are 3 major relax states for 386 jump insns because the |
459 | different types of jumps add different sizes to frags when we're | |
460 | figuring out what sort of jump to choose to reach a given label. */ | |
252b5132 | 461 | |
47926f60 | 462 | /* Types. */ |
93c2a809 AM |
463 | #define UNCOND_JUMP 0 |
464 | #define COND_JUMP 1 | |
465 | #define COND_JUMP86 2 | |
fddf5b5b | 466 | |
47926f60 | 467 | /* Sizes. */ |
252b5132 RH |
468 | #define CODE16 1 |
469 | #define SMALL 0 | |
29b0f896 | 470 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 471 | #define BIG 2 |
29b0f896 | 472 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
473 | |
474 | #ifndef INLINE | |
475 | #ifdef __GNUC__ | |
476 | #define INLINE __inline__ | |
477 | #else | |
478 | #define INLINE | |
479 | #endif | |
480 | #endif | |
481 | ||
fddf5b5b AM |
482 | #define ENCODE_RELAX_STATE(type, size) \ |
483 | ((relax_substateT) (((type) << 2) | (size))) | |
484 | #define TYPE_FROM_RELAX_STATE(s) \ | |
485 | ((s) >> 2) | |
486 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
487 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
488 | |
489 | /* This table is used by relax_frag to promote short jumps to long | |
490 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
491 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
492 | don't allow a short jump in a 32 bit code segment to be promoted to | |
493 | a 16 bit offset jump because it's slower (requires data size | |
494 | prefix), and doesn't work, unless the destination is in the bottom | |
495 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
496 | ||
497 | const relax_typeS md_relax_table[] = | |
498 | { | |
24eab124 AM |
499 | /* The fields are: |
500 | 1) most positive reach of this state, | |
501 | 2) most negative reach of this state, | |
93c2a809 | 502 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 503 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 504 | |
fddf5b5b | 505 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
506 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
507 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
508 | /* dword jmp adds 4 bytes to frag: | |
509 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 510 | {0, 0, 4, 0}, |
93c2a809 AM |
511 | /* word jmp adds 2 byte2 to frag: |
512 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
513 | {0, 0, 2, 0}, |
514 | ||
93c2a809 AM |
515 | /* COND_JUMP states. */ |
516 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
517 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
518 | /* dword conditionals adds 5 bytes to frag: | |
519 | 1 extra opcode byte, 4 displacement bytes. */ | |
520 | {0, 0, 5, 0}, | |
fddf5b5b | 521 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
522 | 1 extra opcode byte, 2 displacement bytes. */ |
523 | {0, 0, 3, 0}, | |
524 | ||
525 | /* COND_JUMP86 states. */ | |
526 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
527 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
528 | /* dword conditionals adds 5 bytes to frag: | |
529 | 1 extra opcode byte, 4 displacement bytes. */ | |
530 | {0, 0, 5, 0}, | |
531 | /* word conditionals add 4 bytes to frag: | |
532 | 1 displacement byte and a 3 byte long branch insn. */ | |
533 | {0, 0, 4, 0} | |
252b5132 RH |
534 | }; |
535 | ||
9103f4f4 L |
536 | static const arch_entry cpu_arch[] = |
537 | { | |
6305a203 L |
538 | { "generic32", PROCESSOR_GENERIC32, |
539 | CPU_GENERIC32_FLAGS }, | |
540 | { "generic64", PROCESSOR_GENERIC64, | |
541 | CPU_GENERIC64_FLAGS }, | |
542 | { "i8086", PROCESSOR_UNKNOWN, | |
543 | CPU_NONE_FLAGS }, | |
544 | { "i186", PROCESSOR_UNKNOWN, | |
545 | CPU_I186_FLAGS }, | |
546 | { "i286", PROCESSOR_UNKNOWN, | |
547 | CPU_I286_FLAGS }, | |
548 | { "i386", PROCESSOR_I386, | |
549 | CPU_I386_FLAGS }, | |
550 | { "i486", PROCESSOR_I486, | |
551 | CPU_I486_FLAGS }, | |
552 | { "i586", PROCESSOR_PENTIUM, | |
553 | CPU_I586_FLAGS }, | |
554 | { "i686", PROCESSOR_PENTIUMPRO, | |
555 | CPU_I686_FLAGS }, | |
556 | { "pentium", PROCESSOR_PENTIUM, | |
557 | CPU_I586_FLAGS }, | |
558 | { "pentiumpro", PROCESSOR_PENTIUMPRO, | |
559 | CPU_I686_FLAGS }, | |
560 | { "pentiumii", PROCESSOR_PENTIUMPRO, | |
561 | CPU_P2_FLAGS }, | |
562 | { "pentiumiii",PROCESSOR_PENTIUMPRO, | |
563 | CPU_P3_FLAGS }, | |
564 | { "pentium4", PROCESSOR_PENTIUM4, | |
565 | CPU_P4_FLAGS }, | |
566 | { "prescott", PROCESSOR_NOCONA, | |
567 | CPU_CORE_FLAGS }, | |
568 | { "nocona", PROCESSOR_NOCONA, | |
569 | CPU_NOCONA_FLAGS }, | |
570 | { "yonah", PROCESSOR_CORE, | |
571 | CPU_CORE_FLAGS }, | |
572 | { "core", PROCESSOR_CORE, | |
573 | CPU_CORE_FLAGS }, | |
574 | { "merom", PROCESSOR_CORE2, | |
575 | CPU_CORE2_FLAGS }, | |
576 | { "core2", PROCESSOR_CORE2, | |
577 | CPU_CORE2_FLAGS }, | |
bd5295b2 L |
578 | { "corei7", PROCESSOR_COREI7, |
579 | CPU_COREI7_FLAGS }, | |
3632d14b | 580 | { "l1om", PROCESSOR_L1OM, |
8a9036a4 | 581 | CPU_L1OM_FLAGS }, |
6305a203 L |
582 | { "k6", PROCESSOR_K6, |
583 | CPU_K6_FLAGS }, | |
584 | { "k6_2", PROCESSOR_K6, | |
585 | CPU_K6_2_FLAGS }, | |
586 | { "athlon", PROCESSOR_ATHLON, | |
587 | CPU_ATHLON_FLAGS }, | |
588 | { "sledgehammer", PROCESSOR_K8, | |
589 | CPU_K8_FLAGS }, | |
590 | { "opteron", PROCESSOR_K8, | |
591 | CPU_K8_FLAGS }, | |
592 | { "k8", PROCESSOR_K8, | |
593 | CPU_K8_FLAGS }, | |
594 | { "amdfam10", PROCESSOR_AMDFAM10, | |
595 | CPU_AMDFAM10_FLAGS }, | |
309d3373 JB |
596 | { ".8087", PROCESSOR_UNKNOWN, |
597 | CPU_8087_FLAGS }, | |
598 | { ".287", PROCESSOR_UNKNOWN, | |
599 | CPU_287_FLAGS }, | |
600 | { ".387", PROCESSOR_UNKNOWN, | |
601 | CPU_387_FLAGS }, | |
602 | { ".no87", PROCESSOR_UNKNOWN, | |
603 | CPU_ANY87_FLAGS }, | |
6305a203 L |
604 | { ".mmx", PROCESSOR_UNKNOWN, |
605 | CPU_MMX_FLAGS }, | |
309d3373 JB |
606 | { ".nommx", PROCESSOR_UNKNOWN, |
607 | CPU_3DNOWA_FLAGS }, | |
6305a203 L |
608 | { ".sse", PROCESSOR_UNKNOWN, |
609 | CPU_SSE_FLAGS }, | |
610 | { ".sse2", PROCESSOR_UNKNOWN, | |
611 | CPU_SSE2_FLAGS }, | |
612 | { ".sse3", PROCESSOR_UNKNOWN, | |
613 | CPU_SSE3_FLAGS }, | |
614 | { ".ssse3", PROCESSOR_UNKNOWN, | |
615 | CPU_SSSE3_FLAGS }, | |
616 | { ".sse4.1", PROCESSOR_UNKNOWN, | |
617 | CPU_SSE4_1_FLAGS }, | |
618 | { ".sse4.2", PROCESSOR_UNKNOWN, | |
619 | CPU_SSE4_2_FLAGS }, | |
620 | { ".sse4", PROCESSOR_UNKNOWN, | |
621 | CPU_SSE4_2_FLAGS }, | |
309d3373 JB |
622 | { ".nosse", PROCESSOR_UNKNOWN, |
623 | CPU_ANY_SSE_FLAGS }, | |
c0f3af97 L |
624 | { ".avx", PROCESSOR_UNKNOWN, |
625 | CPU_AVX_FLAGS }, | |
309d3373 JB |
626 | { ".noavx", PROCESSOR_UNKNOWN, |
627 | CPU_ANY_AVX_FLAGS }, | |
6305a203 L |
628 | { ".vmx", PROCESSOR_UNKNOWN, |
629 | CPU_VMX_FLAGS }, | |
630 | { ".smx", PROCESSOR_UNKNOWN, | |
631 | CPU_SMX_FLAGS }, | |
f03fe4c1 L |
632 | { ".xsave", PROCESSOR_UNKNOWN, |
633 | CPU_XSAVE_FLAGS }, | |
c0f3af97 L |
634 | { ".aes", PROCESSOR_UNKNOWN, |
635 | CPU_AES_FLAGS }, | |
594ab6a3 L |
636 | { ".pclmul", PROCESSOR_UNKNOWN, |
637 | CPU_PCLMUL_FLAGS }, | |
c0f3af97 | 638 | { ".clmul", PROCESSOR_UNKNOWN, |
594ab6a3 | 639 | CPU_PCLMUL_FLAGS }, |
c0f3af97 L |
640 | { ".fma", PROCESSOR_UNKNOWN, |
641 | CPU_FMA_FLAGS }, | |
922d8de8 DR |
642 | { ".fma4", PROCESSOR_UNKNOWN, |
643 | CPU_FMA4_FLAGS }, | |
f1f8f695 L |
644 | { ".movbe", PROCESSOR_UNKNOWN, |
645 | CPU_MOVBE_FLAGS }, | |
646 | { ".ept", PROCESSOR_UNKNOWN, | |
647 | CPU_EPT_FLAGS }, | |
bd5295b2 L |
648 | { ".clflush", PROCESSOR_UNKNOWN, |
649 | CPU_CLFLUSH_FLAGS }, | |
650 | { ".syscall", PROCESSOR_UNKNOWN, | |
651 | CPU_SYSCALL_FLAGS }, | |
1b7f3fb0 L |
652 | { ".rdtscp", PROCESSOR_UNKNOWN, |
653 | CPU_RDTSCP_FLAGS }, | |
6305a203 L |
654 | { ".3dnow", PROCESSOR_UNKNOWN, |
655 | CPU_3DNOW_FLAGS }, | |
656 | { ".3dnowa", PROCESSOR_UNKNOWN, | |
657 | CPU_3DNOWA_FLAGS }, | |
658 | { ".padlock", PROCESSOR_UNKNOWN, | |
659 | CPU_PADLOCK_FLAGS }, | |
660 | { ".pacifica", PROCESSOR_UNKNOWN, | |
661 | CPU_SVME_FLAGS }, | |
662 | { ".svme", PROCESSOR_UNKNOWN, | |
663 | CPU_SVME_FLAGS }, | |
664 | { ".sse4a", PROCESSOR_UNKNOWN, | |
665 | CPU_SSE4A_FLAGS }, | |
666 | { ".abm", PROCESSOR_UNKNOWN, | |
667 | CPU_ABM_FLAGS }, | |
e413e4e9 AM |
668 | }; |
669 | ||
704209c0 | 670 | #ifdef I386COFF |
a6c24e68 NC |
671 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
672 | is allowed to be optional. */ | |
673 | ||
674 | static symbolS * | |
675 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
676 | { | |
677 | addressT align = 0; | |
678 | ||
679 | SKIP_WHITESPACE (); | |
680 | ||
7ab9ffdd | 681 | if (needs_align |
a6c24e68 NC |
682 | && *input_line_pointer == ',') |
683 | { | |
684 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 685 | |
a6c24e68 NC |
686 | if (align == (addressT) -1) |
687 | return NULL; | |
688 | } | |
689 | else | |
690 | { | |
691 | if (size >= 8) | |
692 | align = 3; | |
693 | else if (size >= 4) | |
694 | align = 2; | |
695 | else if (size >= 2) | |
696 | align = 1; | |
697 | else | |
698 | align = 0; | |
699 | } | |
700 | ||
701 | bss_alloc (symbolP, size, align); | |
702 | return symbolP; | |
703 | } | |
704 | ||
704209c0 | 705 | static void |
a6c24e68 NC |
706 | pe_lcomm (int needs_align) |
707 | { | |
708 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
709 | } | |
704209c0 | 710 | #endif |
a6c24e68 | 711 | |
29b0f896 AM |
712 | const pseudo_typeS md_pseudo_table[] = |
713 | { | |
714 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
715 | {"align", s_align_bytes, 0}, | |
716 | #else | |
717 | {"align", s_align_ptwo, 0}, | |
718 | #endif | |
719 | {"arch", set_cpu_arch, 0}, | |
720 | #ifndef I386COFF | |
721 | {"bss", s_bss, 0}, | |
a6c24e68 NC |
722 | #else |
723 | {"lcomm", pe_lcomm, 1}, | |
29b0f896 AM |
724 | #endif |
725 | {"ffloat", float_cons, 'f'}, | |
726 | {"dfloat", float_cons, 'd'}, | |
727 | {"tfloat", float_cons, 'x'}, | |
728 | {"value", cons, 2}, | |
d182319b | 729 | {"slong", signed_cons, 4}, |
29b0f896 AM |
730 | {"noopt", s_ignore, 0}, |
731 | {"optim", s_ignore, 0}, | |
732 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
733 | {"code16", set_code_flag, CODE_16BIT}, | |
734 | {"code32", set_code_flag, CODE_32BIT}, | |
735 | {"code64", set_code_flag, CODE_64BIT}, | |
736 | {"intel_syntax", set_intel_syntax, 1}, | |
737 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
738 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
739 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
740 | {"allow_index_reg", set_allow_index_reg, 1}, |
741 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
cb19c032 | 742 | {"sse_check", set_sse_check, 0}, |
3b22753a L |
743 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
744 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 745 | #else |
e3bb37b5 | 746 | {"file", (void (*) (int)) dwarf2_directive_file, 0}, |
07a53e5c RH |
747 | {"loc", dwarf2_directive_loc, 0}, |
748 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 749 | #endif |
6482c264 NC |
750 | #ifdef TE_PE |
751 | {"secrel32", pe_directive_secrel, 0}, | |
752 | #endif | |
29b0f896 AM |
753 | {0, 0, 0} |
754 | }; | |
755 | ||
756 | /* For interface with expression (). */ | |
757 | extern char *input_line_pointer; | |
758 | ||
759 | /* Hash table for instruction mnemonic lookup. */ | |
760 | static struct hash_control *op_hash; | |
761 | ||
762 | /* Hash table for register lookup. */ | |
763 | static struct hash_control *reg_hash; | |
764 | \f | |
252b5132 | 765 | void |
e3bb37b5 | 766 | i386_align_code (fragS *fragP, int count) |
252b5132 | 767 | { |
ce8a8b2f AM |
768 | /* Various efficient no-op patterns for aligning code labels. |
769 | Note: Don't try to assemble the instructions in the comments. | |
770 | 0L and 0w are not legal. */ | |
252b5132 RH |
771 | static const char f32_1[] = |
772 | {0x90}; /* nop */ | |
773 | static const char f32_2[] = | |
ccc9c027 | 774 | {0x66,0x90}; /* xchg %ax,%ax */ |
252b5132 RH |
775 | static const char f32_3[] = |
776 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
777 | static const char f32_4[] = | |
778 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
779 | static const char f32_5[] = | |
780 | {0x90, /* nop */ | |
781 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
782 | static const char f32_6[] = | |
783 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
784 | static const char f32_7[] = | |
785 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
786 | static const char f32_8[] = | |
787 | {0x90, /* nop */ | |
788 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
789 | static const char f32_9[] = | |
790 | {0x89,0xf6, /* movl %esi,%esi */ | |
791 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
792 | static const char f32_10[] = | |
793 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ | |
794 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
795 | static const char f32_11[] = | |
796 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ | |
797 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
798 | static const char f32_12[] = | |
799 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
800 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
801 | static const char f32_13[] = | |
802 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
803 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
804 | static const char f32_14[] = | |
805 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ | |
806 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
c3332e24 AM |
807 | static const char f16_3[] = |
808 | {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ | |
252b5132 RH |
809 | static const char f16_4[] = |
810 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
811 | static const char f16_5[] = | |
812 | {0x90, /* nop */ | |
813 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
814 | static const char f16_6[] = | |
815 | {0x89,0xf6, /* mov %si,%si */ | |
816 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
817 | static const char f16_7[] = | |
818 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ | |
819 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
820 | static const char f16_8[] = | |
821 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ | |
822 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
76bc74dc L |
823 | static const char jump_31[] = |
824 | {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */ | |
825 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, | |
826 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, | |
827 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
252b5132 RH |
828 | static const char *const f32_patt[] = { |
829 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, | |
76bc74dc | 830 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14 |
252b5132 RH |
831 | }; |
832 | static const char *const f16_patt[] = { | |
76bc74dc | 833 | f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8 |
252b5132 | 834 | }; |
ccc9c027 L |
835 | /* nopl (%[re]ax) */ |
836 | static const char alt_3[] = | |
837 | {0x0f,0x1f,0x00}; | |
838 | /* nopl 0(%[re]ax) */ | |
839 | static const char alt_4[] = | |
840 | {0x0f,0x1f,0x40,0x00}; | |
841 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
842 | static const char alt_5[] = | |
843 | {0x0f,0x1f,0x44,0x00,0x00}; | |
844 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
845 | static const char alt_6[] = | |
846 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
847 | /* nopl 0L(%[re]ax) */ | |
848 | static const char alt_7[] = | |
849 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
850 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
851 | static const char alt_8[] = | |
852 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
853 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
854 | static const char alt_9[] = | |
855 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
856 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
857 | static const char alt_10[] = | |
858 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
859 | /* data16 | |
860 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
861 | static const char alt_long_11[] = | |
862 | {0x66, | |
863 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
864 | /* data16 | |
865 | data16 | |
866 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
867 | static const char alt_long_12[] = | |
868 | {0x66, | |
869 | 0x66, | |
870 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
871 | /* data16 | |
872 | data16 | |
873 | data16 | |
874 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
875 | static const char alt_long_13[] = | |
876 | {0x66, | |
877 | 0x66, | |
878 | 0x66, | |
879 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
880 | /* data16 | |
881 | data16 | |
882 | data16 | |
883 | data16 | |
884 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
885 | static const char alt_long_14[] = | |
886 | {0x66, | |
887 | 0x66, | |
888 | 0x66, | |
889 | 0x66, | |
890 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
891 | /* data16 | |
892 | data16 | |
893 | data16 | |
894 | data16 | |
895 | data16 | |
896 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
897 | static const char alt_long_15[] = | |
898 | {0x66, | |
899 | 0x66, | |
900 | 0x66, | |
901 | 0x66, | |
902 | 0x66, | |
903 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
904 | /* nopl 0(%[re]ax,%[re]ax,1) | |
905 | nopw 0(%[re]ax,%[re]ax,1) */ | |
906 | static const char alt_short_11[] = | |
907 | {0x0f,0x1f,0x44,0x00,0x00, | |
908 | 0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
909 | /* nopw 0(%[re]ax,%[re]ax,1) | |
910 | nopw 0(%[re]ax,%[re]ax,1) */ | |
911 | static const char alt_short_12[] = | |
912 | {0x66,0x0f,0x1f,0x44,0x00,0x00, | |
913 | 0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
914 | /* nopw 0(%[re]ax,%[re]ax,1) | |
915 | nopl 0L(%[re]ax) */ | |
916 | static const char alt_short_13[] = | |
917 | {0x66,0x0f,0x1f,0x44,0x00,0x00, | |
918 | 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
919 | /* nopl 0L(%[re]ax) | |
920 | nopl 0L(%[re]ax) */ | |
921 | static const char alt_short_14[] = | |
922 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00, | |
923 | 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
924 | /* nopl 0L(%[re]ax) | |
925 | nopl 0L(%[re]ax,%[re]ax,1) */ | |
926 | static const char alt_short_15[] = | |
927 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00, | |
928 | 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
929 | static const char *const alt_short_patt[] = { | |
930 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
931 | alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13, | |
932 | alt_short_14, alt_short_15 | |
933 | }; | |
934 | static const char *const alt_long_patt[] = { | |
935 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
936 | alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13, | |
937 | alt_long_14, alt_long_15 | |
938 | }; | |
252b5132 | 939 | |
76bc74dc L |
940 | /* Only align for at least a positive non-zero boundary. */ |
941 | if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE) | |
33fef721 | 942 | return; |
3e73aa7c | 943 | |
ccc9c027 L |
944 | /* We need to decide which NOP sequence to use for 32bit and |
945 | 64bit. When -mtune= is used: | |
4eed87de | 946 | |
76bc74dc L |
947 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
948 | PROCESSOR_GENERIC32, f32_patt will be used. | |
949 | 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA, | |
bd5295b2 L |
950 | PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and |
951 | PROCESSOR_GENERIC64, alt_long_patt will be used. | |
76bc74dc L |
952 | 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and |
953 | PROCESSOR_AMDFAM10, alt_short_patt will be used. | |
ccc9c027 | 954 | |
76bc74dc L |
955 | When -mtune= isn't used, alt_long_patt will be used if |
956 | cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will | |
957 | be used. | |
ccc9c027 L |
958 | |
959 | When -march= or .arch is used, we can't use anything beyond | |
960 | cpu_arch_isa_flags. */ | |
961 | ||
962 | if (flag_code == CODE_16BIT) | |
963 | { | |
ccc9c027 | 964 | if (count > 8) |
33fef721 | 965 | { |
76bc74dc L |
966 | memcpy (fragP->fr_literal + fragP->fr_fix, |
967 | jump_31, count); | |
968 | /* Adjust jump offset. */ | |
969 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
252b5132 | 970 | } |
76bc74dc L |
971 | else |
972 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
973 | f16_patt[count - 1], count); | |
252b5132 | 974 | } |
33fef721 | 975 | else |
ccc9c027 L |
976 | { |
977 | const char *const *patt = NULL; | |
978 | ||
fbf3f584 | 979 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 L |
980 | { |
981 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
982 | switch (cpu_arch_tune) | |
983 | { | |
984 | case PROCESSOR_UNKNOWN: | |
985 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
986 | optimize for Cpu686. */ | |
fbf3f584 | 987 | if (fragP->tc_frag_data.isa_flags.bitfield.cpui686) |
76bc74dc | 988 | patt = alt_long_patt; |
ccc9c027 L |
989 | else |
990 | patt = f32_patt; | |
991 | break; | |
ccc9c027 L |
992 | case PROCESSOR_PENTIUMPRO: |
993 | case PROCESSOR_PENTIUM4: | |
994 | case PROCESSOR_NOCONA: | |
ef05d495 | 995 | case PROCESSOR_CORE: |
76bc74dc | 996 | case PROCESSOR_CORE2: |
bd5295b2 | 997 | case PROCESSOR_COREI7: |
3632d14b | 998 | case PROCESSOR_L1OM: |
76bc74dc L |
999 | case PROCESSOR_GENERIC64: |
1000 | patt = alt_long_patt; | |
1001 | break; | |
ccc9c027 L |
1002 | case PROCESSOR_K6: |
1003 | case PROCESSOR_ATHLON: | |
1004 | case PROCESSOR_K8: | |
4eed87de | 1005 | case PROCESSOR_AMDFAM10: |
ccc9c027 L |
1006 | patt = alt_short_patt; |
1007 | break; | |
76bc74dc | 1008 | case PROCESSOR_I386: |
ccc9c027 L |
1009 | case PROCESSOR_I486: |
1010 | case PROCESSOR_PENTIUM: | |
1011 | case PROCESSOR_GENERIC32: | |
1012 | patt = f32_patt; | |
1013 | break; | |
4eed87de | 1014 | } |
ccc9c027 L |
1015 | } |
1016 | else | |
1017 | { | |
fbf3f584 | 1018 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1019 | { |
1020 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1021 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1022 | PROCESSOR_UNKNOWN. */ |
1023 | abort (); | |
1024 | break; | |
1025 | ||
76bc74dc | 1026 | case PROCESSOR_I386: |
ccc9c027 L |
1027 | case PROCESSOR_I486: |
1028 | case PROCESSOR_PENTIUM: | |
ccc9c027 L |
1029 | case PROCESSOR_K6: |
1030 | case PROCESSOR_ATHLON: | |
1031 | case PROCESSOR_K8: | |
4eed87de | 1032 | case PROCESSOR_AMDFAM10: |
ccc9c027 L |
1033 | case PROCESSOR_GENERIC32: |
1034 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
1035 | for Cpu686. */ | |
fbf3f584 | 1036 | if (fragP->tc_frag_data.isa_flags.bitfield.cpui686) |
ccc9c027 L |
1037 | patt = alt_short_patt; |
1038 | else | |
1039 | patt = f32_patt; | |
1040 | break; | |
76bc74dc L |
1041 | case PROCESSOR_PENTIUMPRO: |
1042 | case PROCESSOR_PENTIUM4: | |
1043 | case PROCESSOR_NOCONA: | |
1044 | case PROCESSOR_CORE: | |
ef05d495 | 1045 | case PROCESSOR_CORE2: |
bd5295b2 | 1046 | case PROCESSOR_COREI7: |
3632d14b | 1047 | case PROCESSOR_L1OM: |
fbf3f584 | 1048 | if (fragP->tc_frag_data.isa_flags.bitfield.cpui686) |
ccc9c027 L |
1049 | patt = alt_long_patt; |
1050 | else | |
1051 | patt = f32_patt; | |
1052 | break; | |
1053 | case PROCESSOR_GENERIC64: | |
76bc74dc | 1054 | patt = alt_long_patt; |
ccc9c027 | 1055 | break; |
4eed87de | 1056 | } |
ccc9c027 L |
1057 | } |
1058 | ||
76bc74dc L |
1059 | if (patt == f32_patt) |
1060 | { | |
1061 | /* If the padding is less than 15 bytes, we use the normal | |
1062 | ones. Otherwise, we use a jump instruction and adjust | |
711eedef L |
1063 | its offset. */ |
1064 | int limit; | |
1065 | ||
1066 | /* For 64bit, the limit is 3 bytes. */ | |
1067 | if (flag_code == CODE_64BIT | |
1068 | && fragP->tc_frag_data.isa_flags.bitfield.cpulm) | |
1069 | limit = 3; | |
1070 | else | |
1071 | limit = 15; | |
1072 | if (count < limit) | |
76bc74dc L |
1073 | memcpy (fragP->fr_literal + fragP->fr_fix, |
1074 | patt[count - 1], count); | |
1075 | else | |
1076 | { | |
1077 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1078 | jump_31, count); | |
1079 | /* Adjust jump offset. */ | |
1080 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
1081 | } | |
1082 | } | |
1083 | else | |
1084 | { | |
1085 | /* Maximum length of an instruction is 15 byte. If the | |
1086 | padding is greater than 15 bytes and we don't use jump, | |
1087 | we have to break it into smaller pieces. */ | |
1088 | int padding = count; | |
1089 | while (padding > 15) | |
1090 | { | |
1091 | padding -= 15; | |
1092 | memcpy (fragP->fr_literal + fragP->fr_fix + padding, | |
1093 | patt [14], 15); | |
1094 | } | |
1095 | ||
1096 | if (padding) | |
1097 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1098 | patt [padding - 1], padding); | |
1099 | } | |
ccc9c027 | 1100 | } |
33fef721 | 1101 | fragP->fr_var = count; |
252b5132 RH |
1102 | } |
1103 | ||
c6fb90c8 | 1104 | static INLINE int |
0dfbf9d7 | 1105 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1106 | { |
0dfbf9d7 | 1107 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1108 | { |
1109 | case 3: | |
0dfbf9d7 | 1110 | if (x->array[2]) |
c6fb90c8 L |
1111 | return 0; |
1112 | case 2: | |
0dfbf9d7 | 1113 | if (x->array[1]) |
c6fb90c8 L |
1114 | return 0; |
1115 | case 1: | |
0dfbf9d7 | 1116 | return !x->array[0]; |
c6fb90c8 L |
1117 | default: |
1118 | abort (); | |
1119 | } | |
40fb9820 L |
1120 | } |
1121 | ||
c6fb90c8 | 1122 | static INLINE void |
0dfbf9d7 | 1123 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1124 | { |
0dfbf9d7 | 1125 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1126 | { |
1127 | case 3: | |
0dfbf9d7 | 1128 | x->array[2] = v; |
c6fb90c8 | 1129 | case 2: |
0dfbf9d7 | 1130 | x->array[1] = v; |
c6fb90c8 | 1131 | case 1: |
0dfbf9d7 | 1132 | x->array[0] = v; |
c6fb90c8 L |
1133 | break; |
1134 | default: | |
1135 | abort (); | |
1136 | } | |
1137 | } | |
40fb9820 | 1138 | |
c6fb90c8 | 1139 | static INLINE int |
0dfbf9d7 L |
1140 | operand_type_equal (const union i386_operand_type *x, |
1141 | const union i386_operand_type *y) | |
c6fb90c8 | 1142 | { |
0dfbf9d7 | 1143 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1144 | { |
1145 | case 3: | |
0dfbf9d7 | 1146 | if (x->array[2] != y->array[2]) |
c6fb90c8 L |
1147 | return 0; |
1148 | case 2: | |
0dfbf9d7 | 1149 | if (x->array[1] != y->array[1]) |
c6fb90c8 L |
1150 | return 0; |
1151 | case 1: | |
0dfbf9d7 | 1152 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1153 | break; |
1154 | default: | |
1155 | abort (); | |
1156 | } | |
1157 | } | |
40fb9820 | 1158 | |
0dfbf9d7 L |
1159 | static INLINE int |
1160 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1161 | { | |
1162 | switch (ARRAY_SIZE(x->array)) | |
1163 | { | |
1164 | case 3: | |
1165 | if (x->array[2]) | |
1166 | return 0; | |
1167 | case 2: | |
1168 | if (x->array[1]) | |
1169 | return 0; | |
1170 | case 1: | |
1171 | return !x->array[0]; | |
1172 | default: | |
1173 | abort (); | |
1174 | } | |
1175 | } | |
1176 | ||
1177 | static INLINE void | |
1178 | cpu_flags_set (union i386_cpu_flags *x, unsigned int v) | |
1179 | { | |
1180 | switch (ARRAY_SIZE(x->array)) | |
1181 | { | |
1182 | case 3: | |
1183 | x->array[2] = v; | |
1184 | case 2: | |
1185 | x->array[1] = v; | |
1186 | case 1: | |
1187 | x->array[0] = v; | |
1188 | break; | |
1189 | default: | |
1190 | abort (); | |
1191 | } | |
1192 | } | |
1193 | ||
1194 | static INLINE int | |
1195 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1196 | const union i386_cpu_flags *y) | |
1197 | { | |
1198 | switch (ARRAY_SIZE(x->array)) | |
1199 | { | |
1200 | case 3: | |
1201 | if (x->array[2] != y->array[2]) | |
1202 | return 0; | |
1203 | case 2: | |
1204 | if (x->array[1] != y->array[1]) | |
1205 | return 0; | |
1206 | case 1: | |
1207 | return x->array[0] == y->array[0]; | |
1208 | break; | |
1209 | default: | |
1210 | abort (); | |
1211 | } | |
1212 | } | |
c6fb90c8 L |
1213 | |
1214 | static INLINE int | |
1215 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1216 | { | |
1217 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1218 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1219 | } |
1220 | ||
c6fb90c8 L |
1221 | static INLINE i386_cpu_flags |
1222 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1223 | { |
c6fb90c8 L |
1224 | switch (ARRAY_SIZE (x.array)) |
1225 | { | |
1226 | case 3: | |
1227 | x.array [2] &= y.array [2]; | |
1228 | case 2: | |
1229 | x.array [1] &= y.array [1]; | |
1230 | case 1: | |
1231 | x.array [0] &= y.array [0]; | |
1232 | break; | |
1233 | default: | |
1234 | abort (); | |
1235 | } | |
1236 | return x; | |
1237 | } | |
40fb9820 | 1238 | |
c6fb90c8 L |
1239 | static INLINE i386_cpu_flags |
1240 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1241 | { |
c6fb90c8 | 1242 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1243 | { |
c6fb90c8 L |
1244 | case 3: |
1245 | x.array [2] |= y.array [2]; | |
1246 | case 2: | |
1247 | x.array [1] |= y.array [1]; | |
1248 | case 1: | |
1249 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1250 | break; |
1251 | default: | |
1252 | abort (); | |
1253 | } | |
40fb9820 L |
1254 | return x; |
1255 | } | |
1256 | ||
309d3373 JB |
1257 | static INLINE i386_cpu_flags |
1258 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1259 | { | |
1260 | switch (ARRAY_SIZE (x.array)) | |
1261 | { | |
1262 | case 3: | |
1263 | x.array [2] &= ~y.array [2]; | |
1264 | case 2: | |
1265 | x.array [1] &= ~y.array [1]; | |
1266 | case 1: | |
1267 | x.array [0] &= ~y.array [0]; | |
1268 | break; | |
1269 | default: | |
1270 | abort (); | |
1271 | } | |
1272 | return x; | |
1273 | } | |
1274 | ||
c0f3af97 L |
1275 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1276 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
a5ff0eb2 | 1277 | #define CPU_FLAGS_AES_MATCH 0x4 |
ce2f5b3c L |
1278 | #define CPU_FLAGS_PCLMUL_MATCH 0x8 |
1279 | #define CPU_FLAGS_AVX_MATCH 0x10 | |
c0f3af97 | 1280 | |
a5ff0eb2 | 1281 | #define CPU_FLAGS_32BIT_MATCH \ |
ce2f5b3c L |
1282 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \ |
1283 | | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH) | |
c0f3af97 L |
1284 | #define CPU_FLAGS_PERFECT_MATCH \ |
1285 | (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH) | |
1286 | ||
1287 | /* Return CPU flags match bits. */ | |
3629bb00 | 1288 | |
40fb9820 | 1289 | static int |
d3ce72d0 | 1290 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1291 | { |
c0f3af97 L |
1292 | i386_cpu_flags x = t->cpu_flags; |
1293 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; | |
40fb9820 L |
1294 | |
1295 | x.bitfield.cpu64 = 0; | |
1296 | x.bitfield.cpuno64 = 0; | |
1297 | ||
0dfbf9d7 | 1298 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1299 | { |
1300 | /* This instruction is available on all archs. */ | |
1301 | match |= CPU_FLAGS_32BIT_MATCH; | |
1302 | } | |
3629bb00 L |
1303 | else |
1304 | { | |
c0f3af97 | 1305 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1306 | i386_cpu_flags cpu = cpu_arch_flags; |
1307 | ||
1308 | cpu.bitfield.cpu64 = 0; | |
1309 | cpu.bitfield.cpuno64 = 0; | |
1310 | cpu = cpu_flags_and (x, cpu); | |
c0f3af97 L |
1311 | if (!cpu_flags_all_zero (&cpu)) |
1312 | { | |
a5ff0eb2 L |
1313 | if (x.bitfield.cpuavx) |
1314 | { | |
ce2f5b3c | 1315 | /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */ |
a5ff0eb2 L |
1316 | if (cpu.bitfield.cpuavx) |
1317 | { | |
1318 | /* Check SSE2AVX. */ | |
1319 | if (!t->opcode_modifier.sse2avx|| sse2avx) | |
1320 | { | |
1321 | match |= (CPU_FLAGS_ARCH_MATCH | |
1322 | | CPU_FLAGS_AVX_MATCH); | |
1323 | /* Check AES. */ | |
1324 | if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) | |
1325 | match |= CPU_FLAGS_AES_MATCH; | |
ce2f5b3c L |
1326 | /* Check PCLMUL. */ |
1327 | if (!x.bitfield.cpupclmul | |
1328 | || cpu.bitfield.cpupclmul) | |
1329 | match |= CPU_FLAGS_PCLMUL_MATCH; | |
a5ff0eb2 L |
1330 | } |
1331 | } | |
1332 | else | |
1333 | match |= CPU_FLAGS_ARCH_MATCH; | |
1334 | } | |
1335 | else | |
c0f3af97 L |
1336 | match |= CPU_FLAGS_32BIT_MATCH; |
1337 | } | |
3629bb00 | 1338 | } |
c0f3af97 | 1339 | return match; |
40fb9820 L |
1340 | } |
1341 | ||
c6fb90c8 L |
1342 | static INLINE i386_operand_type |
1343 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1344 | { |
c6fb90c8 L |
1345 | switch (ARRAY_SIZE (x.array)) |
1346 | { | |
1347 | case 3: | |
1348 | x.array [2] &= y.array [2]; | |
1349 | case 2: | |
1350 | x.array [1] &= y.array [1]; | |
1351 | case 1: | |
1352 | x.array [0] &= y.array [0]; | |
1353 | break; | |
1354 | default: | |
1355 | abort (); | |
1356 | } | |
1357 | return x; | |
40fb9820 L |
1358 | } |
1359 | ||
c6fb90c8 L |
1360 | static INLINE i386_operand_type |
1361 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1362 | { |
c6fb90c8 | 1363 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1364 | { |
c6fb90c8 L |
1365 | case 3: |
1366 | x.array [2] |= y.array [2]; | |
1367 | case 2: | |
1368 | x.array [1] |= y.array [1]; | |
1369 | case 1: | |
1370 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1371 | break; |
1372 | default: | |
1373 | abort (); | |
1374 | } | |
c6fb90c8 L |
1375 | return x; |
1376 | } | |
40fb9820 | 1377 | |
c6fb90c8 L |
1378 | static INLINE i386_operand_type |
1379 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
1380 | { | |
1381 | switch (ARRAY_SIZE (x.array)) | |
1382 | { | |
1383 | case 3: | |
1384 | x.array [2] ^= y.array [2]; | |
1385 | case 2: | |
1386 | x.array [1] ^= y.array [1]; | |
1387 | case 1: | |
1388 | x.array [0] ^= y.array [0]; | |
1389 | break; | |
1390 | default: | |
1391 | abort (); | |
1392 | } | |
40fb9820 L |
1393 | return x; |
1394 | } | |
1395 | ||
1396 | static const i386_operand_type acc32 = OPERAND_TYPE_ACC32; | |
1397 | static const i386_operand_type acc64 = OPERAND_TYPE_ACC64; | |
1398 | static const i386_operand_type control = OPERAND_TYPE_CONTROL; | |
65da13b5 L |
1399 | static const i386_operand_type inoutportreg |
1400 | = OPERAND_TYPE_INOUTPORTREG; | |
40fb9820 L |
1401 | static const i386_operand_type reg16_inoutportreg |
1402 | = OPERAND_TYPE_REG16_INOUTPORTREG; | |
1403 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; | |
1404 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; | |
1405 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; | |
1406 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; | |
1407 | static const i386_operand_type anydisp | |
1408 | = OPERAND_TYPE_ANYDISP; | |
40fb9820 | 1409 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
c0f3af97 | 1410 | static const i386_operand_type regymm = OPERAND_TYPE_REGYMM; |
40fb9820 L |
1411 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
1412 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; | |
1413 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; | |
1414 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
1415 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
1416 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; | |
1417 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; | |
1418 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
1419 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
1420 | ||
1421 | enum operand_type | |
1422 | { | |
1423 | reg, | |
40fb9820 L |
1424 | imm, |
1425 | disp, | |
1426 | anymem | |
1427 | }; | |
1428 | ||
c6fb90c8 | 1429 | static INLINE int |
40fb9820 L |
1430 | operand_type_check (i386_operand_type t, enum operand_type c) |
1431 | { | |
1432 | switch (c) | |
1433 | { | |
1434 | case reg: | |
1435 | return (t.bitfield.reg8 | |
1436 | || t.bitfield.reg16 | |
1437 | || t.bitfield.reg32 | |
1438 | || t.bitfield.reg64); | |
1439 | ||
40fb9820 L |
1440 | case imm: |
1441 | return (t.bitfield.imm8 | |
1442 | || t.bitfield.imm8s | |
1443 | || t.bitfield.imm16 | |
1444 | || t.bitfield.imm32 | |
1445 | || t.bitfield.imm32s | |
1446 | || t.bitfield.imm64); | |
1447 | ||
1448 | case disp: | |
1449 | return (t.bitfield.disp8 | |
1450 | || t.bitfield.disp16 | |
1451 | || t.bitfield.disp32 | |
1452 | || t.bitfield.disp32s | |
1453 | || t.bitfield.disp64); | |
1454 | ||
1455 | case anymem: | |
1456 | return (t.bitfield.disp8 | |
1457 | || t.bitfield.disp16 | |
1458 | || t.bitfield.disp32 | |
1459 | || t.bitfield.disp32s | |
1460 | || t.bitfield.disp64 | |
1461 | || t.bitfield.baseindex); | |
1462 | ||
1463 | default: | |
1464 | abort (); | |
1465 | } | |
2cfe26b6 AM |
1466 | |
1467 | return 0; | |
40fb9820 L |
1468 | } |
1469 | ||
5c07affc L |
1470 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on |
1471 | operand J for instruction template T. */ | |
1472 | ||
1473 | static INLINE int | |
d3ce72d0 | 1474 | match_reg_size (const insn_template *t, unsigned int j) |
5c07affc L |
1475 | { |
1476 | return !((i.types[j].bitfield.byte | |
1477 | && !t->operand_types[j].bitfield.byte) | |
1478 | || (i.types[j].bitfield.word | |
1479 | && !t->operand_types[j].bitfield.word) | |
1480 | || (i.types[j].bitfield.dword | |
1481 | && !t->operand_types[j].bitfield.dword) | |
1482 | || (i.types[j].bitfield.qword | |
1483 | && !t->operand_types[j].bitfield.qword)); | |
1484 | } | |
1485 | ||
1486 | /* Return 1 if there is no conflict in any size on operand J for | |
1487 | instruction template T. */ | |
1488 | ||
1489 | static INLINE int | |
d3ce72d0 | 1490 | match_mem_size (const insn_template *t, unsigned int j) |
5c07affc L |
1491 | { |
1492 | return (match_reg_size (t, j) | |
1493 | && !((i.types[j].bitfield.unspecified | |
1494 | && !t->operand_types[j].bitfield.unspecified) | |
1495 | || (i.types[j].bitfield.fword | |
1496 | && !t->operand_types[j].bitfield.fword) | |
1497 | || (i.types[j].bitfield.tbyte | |
1498 | && !t->operand_types[j].bitfield.tbyte) | |
1499 | || (i.types[j].bitfield.xmmword | |
c0f3af97 L |
1500 | && !t->operand_types[j].bitfield.xmmword) |
1501 | || (i.types[j].bitfield.ymmword | |
1502 | && !t->operand_types[j].bitfield.ymmword))); | |
5c07affc L |
1503 | } |
1504 | ||
1505 | /* Return 1 if there is no size conflict on any operands for | |
1506 | instruction template T. */ | |
1507 | ||
1508 | static INLINE int | |
d3ce72d0 | 1509 | operand_size_match (const insn_template *t) |
5c07affc L |
1510 | { |
1511 | unsigned int j; | |
1512 | int match = 1; | |
1513 | ||
1514 | /* Don't check jump instructions. */ | |
1515 | if (t->opcode_modifier.jump | |
1516 | || t->opcode_modifier.jumpbyte | |
1517 | || t->opcode_modifier.jumpdword | |
1518 | || t->opcode_modifier.jumpintersegment) | |
1519 | return match; | |
1520 | ||
1521 | /* Check memory and accumulator operand size. */ | |
1522 | for (j = 0; j < i.operands; j++) | |
1523 | { | |
1524 | if (t->operand_types[j].bitfield.anysize) | |
1525 | continue; | |
1526 | ||
1527 | if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j)) | |
1528 | { | |
1529 | match = 0; | |
1530 | break; | |
1531 | } | |
1532 | ||
1533 | if (i.types[j].bitfield.mem && !match_mem_size (t, j)) | |
1534 | { | |
1535 | match = 0; | |
1536 | break; | |
1537 | } | |
1538 | } | |
1539 | ||
1540 | if (match | |
1541 | || (!t->opcode_modifier.d && !t->opcode_modifier.floatd)) | |
1542 | return match; | |
1543 | ||
1544 | /* Check reverse. */ | |
9c2799c2 | 1545 | gas_assert (i.operands == 2); |
5c07affc L |
1546 | |
1547 | match = 1; | |
1548 | for (j = 0; j < 2; j++) | |
1549 | { | |
1550 | if (t->operand_types[j].bitfield.acc | |
1551 | && !match_reg_size (t, j ? 0 : 1)) | |
1552 | { | |
1553 | match = 0; | |
1554 | break; | |
1555 | } | |
1556 | ||
1557 | if (i.types[j].bitfield.mem | |
1558 | && !match_mem_size (t, j ? 0 : 1)) | |
1559 | { | |
1560 | match = 0; | |
1561 | break; | |
1562 | } | |
1563 | } | |
1564 | ||
1565 | return match; | |
1566 | } | |
1567 | ||
c6fb90c8 | 1568 | static INLINE int |
40fb9820 L |
1569 | operand_type_match (i386_operand_type overlap, |
1570 | i386_operand_type given) | |
1571 | { | |
1572 | i386_operand_type temp = overlap; | |
1573 | ||
1574 | temp.bitfield.jumpabsolute = 0; | |
7d5e4556 | 1575 | temp.bitfield.unspecified = 0; |
5c07affc L |
1576 | temp.bitfield.byte = 0; |
1577 | temp.bitfield.word = 0; | |
1578 | temp.bitfield.dword = 0; | |
1579 | temp.bitfield.fword = 0; | |
1580 | temp.bitfield.qword = 0; | |
1581 | temp.bitfield.tbyte = 0; | |
1582 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 1583 | temp.bitfield.ymmword = 0; |
0dfbf9d7 | 1584 | if (operand_type_all_zero (&temp)) |
40fb9820 L |
1585 | return 0; |
1586 | ||
1587 | return (given.bitfield.baseindex == overlap.bitfield.baseindex | |
1588 | && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute); | |
1589 | } | |
1590 | ||
7d5e4556 | 1591 | /* If given types g0 and g1 are registers they must be of the same type |
40fb9820 L |
1592 | unless the expected operand type register overlap is null. |
1593 | Note that Acc in a template matches every size of reg. */ | |
1594 | ||
c6fb90c8 | 1595 | static INLINE int |
40fb9820 L |
1596 | operand_type_register_match (i386_operand_type m0, |
1597 | i386_operand_type g0, | |
1598 | i386_operand_type t0, | |
1599 | i386_operand_type m1, | |
1600 | i386_operand_type g1, | |
1601 | i386_operand_type t1) | |
1602 | { | |
1603 | if (!operand_type_check (g0, reg)) | |
1604 | return 1; | |
1605 | ||
1606 | if (!operand_type_check (g1, reg)) | |
1607 | return 1; | |
1608 | ||
1609 | if (g0.bitfield.reg8 == g1.bitfield.reg8 | |
1610 | && g0.bitfield.reg16 == g1.bitfield.reg16 | |
1611 | && g0.bitfield.reg32 == g1.bitfield.reg32 | |
1612 | && g0.bitfield.reg64 == g1.bitfield.reg64) | |
1613 | return 1; | |
1614 | ||
1615 | if (m0.bitfield.acc) | |
1616 | { | |
1617 | t0.bitfield.reg8 = 1; | |
1618 | t0.bitfield.reg16 = 1; | |
1619 | t0.bitfield.reg32 = 1; | |
1620 | t0.bitfield.reg64 = 1; | |
1621 | } | |
1622 | ||
1623 | if (m1.bitfield.acc) | |
1624 | { | |
1625 | t1.bitfield.reg8 = 1; | |
1626 | t1.bitfield.reg16 = 1; | |
1627 | t1.bitfield.reg32 = 1; | |
1628 | t1.bitfield.reg64 = 1; | |
1629 | } | |
1630 | ||
1631 | return (!(t0.bitfield.reg8 & t1.bitfield.reg8) | |
1632 | && !(t0.bitfield.reg16 & t1.bitfield.reg16) | |
1633 | && !(t0.bitfield.reg32 & t1.bitfield.reg32) | |
1634 | && !(t0.bitfield.reg64 & t1.bitfield.reg64)); | |
1635 | } | |
1636 | ||
252b5132 | 1637 | static INLINE unsigned int |
40fb9820 | 1638 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 1639 | { |
40fb9820 L |
1640 | if (t.bitfield.disp8) |
1641 | return 1; | |
1642 | else if (t.bitfield.disp16 | |
1643 | || t.bitfield.disp32 | |
1644 | || t.bitfield.disp32s) | |
1645 | return 2; | |
1646 | else | |
1647 | return 0; | |
252b5132 RH |
1648 | } |
1649 | ||
1650 | static INLINE int | |
e3bb37b5 | 1651 | fits_in_signed_byte (offsetT num) |
252b5132 RH |
1652 | { |
1653 | return (num >= -128) && (num <= 127); | |
47926f60 | 1654 | } |
252b5132 RH |
1655 | |
1656 | static INLINE int | |
e3bb37b5 | 1657 | fits_in_unsigned_byte (offsetT num) |
252b5132 RH |
1658 | { |
1659 | return (num & 0xff) == num; | |
47926f60 | 1660 | } |
252b5132 RH |
1661 | |
1662 | static INLINE int | |
e3bb37b5 | 1663 | fits_in_unsigned_word (offsetT num) |
252b5132 RH |
1664 | { |
1665 | return (num & 0xffff) == num; | |
47926f60 | 1666 | } |
252b5132 RH |
1667 | |
1668 | static INLINE int | |
e3bb37b5 | 1669 | fits_in_signed_word (offsetT num) |
252b5132 RH |
1670 | { |
1671 | return (-32768 <= num) && (num <= 32767); | |
47926f60 | 1672 | } |
2a962e6d | 1673 | |
3e73aa7c | 1674 | static INLINE int |
e3bb37b5 | 1675 | fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
1676 | { |
1677 | #ifndef BFD64 | |
1678 | return 1; | |
1679 | #else | |
1680 | return (!(((offsetT) -1 << 31) & num) | |
1681 | || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31)); | |
1682 | #endif | |
1683 | } /* fits_in_signed_long() */ | |
2a962e6d | 1684 | |
3e73aa7c | 1685 | static INLINE int |
e3bb37b5 | 1686 | fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
1687 | { |
1688 | #ifndef BFD64 | |
1689 | return 1; | |
1690 | #else | |
1691 | return (num & (((offsetT) 2 << 31) - 1)) == num; | |
1692 | #endif | |
1693 | } /* fits_in_unsigned_long() */ | |
252b5132 | 1694 | |
40fb9820 | 1695 | static i386_operand_type |
e3bb37b5 | 1696 | smallest_imm_type (offsetT num) |
252b5132 | 1697 | { |
40fb9820 | 1698 | i386_operand_type t; |
7ab9ffdd | 1699 | |
0dfbf9d7 | 1700 | operand_type_set (&t, 0); |
40fb9820 L |
1701 | t.bitfield.imm64 = 1; |
1702 | ||
1703 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
1704 | { |
1705 | /* This code is disabled on the 486 because all the Imm1 forms | |
1706 | in the opcode table are slower on the i486. They're the | |
1707 | versions with the implicitly specified single-position | |
1708 | displacement, which has another syntax if you really want to | |
1709 | use that form. */ | |
40fb9820 L |
1710 | t.bitfield.imm1 = 1; |
1711 | t.bitfield.imm8 = 1; | |
1712 | t.bitfield.imm8s = 1; | |
1713 | t.bitfield.imm16 = 1; | |
1714 | t.bitfield.imm32 = 1; | |
1715 | t.bitfield.imm32s = 1; | |
1716 | } | |
1717 | else if (fits_in_signed_byte (num)) | |
1718 | { | |
1719 | t.bitfield.imm8 = 1; | |
1720 | t.bitfield.imm8s = 1; | |
1721 | t.bitfield.imm16 = 1; | |
1722 | t.bitfield.imm32 = 1; | |
1723 | t.bitfield.imm32s = 1; | |
1724 | } | |
1725 | else if (fits_in_unsigned_byte (num)) | |
1726 | { | |
1727 | t.bitfield.imm8 = 1; | |
1728 | t.bitfield.imm16 = 1; | |
1729 | t.bitfield.imm32 = 1; | |
1730 | t.bitfield.imm32s = 1; | |
1731 | } | |
1732 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
1733 | { | |
1734 | t.bitfield.imm16 = 1; | |
1735 | t.bitfield.imm32 = 1; | |
1736 | t.bitfield.imm32s = 1; | |
1737 | } | |
1738 | else if (fits_in_signed_long (num)) | |
1739 | { | |
1740 | t.bitfield.imm32 = 1; | |
1741 | t.bitfield.imm32s = 1; | |
1742 | } | |
1743 | else if (fits_in_unsigned_long (num)) | |
1744 | t.bitfield.imm32 = 1; | |
1745 | ||
1746 | return t; | |
47926f60 | 1747 | } |
252b5132 | 1748 | |
847f7ad4 | 1749 | static offsetT |
e3bb37b5 | 1750 | offset_in_range (offsetT val, int size) |
847f7ad4 | 1751 | { |
508866be | 1752 | addressT mask; |
ba2adb93 | 1753 | |
847f7ad4 AM |
1754 | switch (size) |
1755 | { | |
508866be L |
1756 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
1757 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 1758 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
1759 | #ifdef BFD64 |
1760 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
1761 | #endif | |
47926f60 | 1762 | default: abort (); |
847f7ad4 AM |
1763 | } |
1764 | ||
ba2adb93 | 1765 | /* If BFD64, sign extend val. */ |
3e73aa7c JH |
1766 | if (!use_rela_relocations) |
1767 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) | |
1768 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
ba2adb93 | 1769 | |
47926f60 | 1770 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
1771 | { |
1772 | char buf1[40], buf2[40]; | |
1773 | ||
1774 | sprint_value (buf1, val); | |
1775 | sprint_value (buf2, val & mask); | |
1776 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
1777 | } | |
1778 | return val & mask; | |
1779 | } | |
1780 | ||
252b5132 RH |
1781 | /* Returns 0 if attempting to add a prefix where one from the same |
1782 | class already exists, 1 if non rep/repne added, 2 if rep/repne | |
1783 | added. */ | |
1784 | static int | |
e3bb37b5 | 1785 | add_prefix (unsigned int prefix) |
252b5132 RH |
1786 | { |
1787 | int ret = 1; | |
b1905489 | 1788 | unsigned int q; |
252b5132 | 1789 | |
29b0f896 AM |
1790 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
1791 | && flag_code == CODE_64BIT) | |
b1905489 | 1792 | { |
161a04f6 L |
1793 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
1794 | || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B)) | |
1795 | && (prefix & (REX_R | REX_X | REX_B)))) | |
b1905489 JB |
1796 | ret = 0; |
1797 | q = REX_PREFIX; | |
1798 | } | |
3e73aa7c | 1799 | else |
b1905489 JB |
1800 | { |
1801 | switch (prefix) | |
1802 | { | |
1803 | default: | |
1804 | abort (); | |
1805 | ||
1806 | case CS_PREFIX_OPCODE: | |
1807 | case DS_PREFIX_OPCODE: | |
1808 | case ES_PREFIX_OPCODE: | |
1809 | case FS_PREFIX_OPCODE: | |
1810 | case GS_PREFIX_OPCODE: | |
1811 | case SS_PREFIX_OPCODE: | |
1812 | q = SEG_PREFIX; | |
1813 | break; | |
1814 | ||
1815 | case REPNE_PREFIX_OPCODE: | |
1816 | case REPE_PREFIX_OPCODE: | |
1817 | ret = 2; | |
1818 | /* fall thru */ | |
1819 | case LOCK_PREFIX_OPCODE: | |
1820 | q = LOCKREP_PREFIX; | |
1821 | break; | |
1822 | ||
1823 | case FWAIT_OPCODE: | |
1824 | q = WAIT_PREFIX; | |
1825 | break; | |
1826 | ||
1827 | case ADDR_PREFIX_OPCODE: | |
1828 | q = ADDR_PREFIX; | |
1829 | break; | |
1830 | ||
1831 | case DATA_PREFIX_OPCODE: | |
1832 | q = DATA_PREFIX; | |
1833 | break; | |
1834 | } | |
1835 | if (i.prefix[q] != 0) | |
1836 | ret = 0; | |
1837 | } | |
252b5132 | 1838 | |
b1905489 | 1839 | if (ret) |
252b5132 | 1840 | { |
b1905489 JB |
1841 | if (!i.prefix[q]) |
1842 | ++i.prefixes; | |
1843 | i.prefix[q] |= prefix; | |
252b5132 | 1844 | } |
b1905489 JB |
1845 | else |
1846 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 1847 | |
252b5132 RH |
1848 | return ret; |
1849 | } | |
1850 | ||
1851 | static void | |
e3bb37b5 | 1852 | set_code_flag (int value) |
eecb386c | 1853 | { |
3e73aa7c | 1854 | flag_code = value; |
40fb9820 L |
1855 | if (flag_code == CODE_64BIT) |
1856 | { | |
1857 | cpu_arch_flags.bitfield.cpu64 = 1; | |
1858 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
1859 | } |
1860 | else | |
1861 | { | |
1862 | cpu_arch_flags.bitfield.cpu64 = 0; | |
1863 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
1864 | } |
1865 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c JH |
1866 | { |
1867 | as_bad (_("64bit mode not supported on this CPU.")); | |
1868 | } | |
40fb9820 | 1869 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c JH |
1870 | { |
1871 | as_bad (_("32bit mode not supported on this CPU.")); | |
1872 | } | |
eecb386c AM |
1873 | stackop_size = '\0'; |
1874 | } | |
1875 | ||
1876 | static void | |
e3bb37b5 | 1877 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 1878 | { |
3e73aa7c | 1879 | flag_code = new_code_flag; |
40fb9820 L |
1880 | if (flag_code != CODE_16BIT) |
1881 | abort (); | |
1882 | cpu_arch_flags.bitfield.cpu64 = 0; | |
1883 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 1884 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
1885 | } |
1886 | ||
1887 | static void | |
e3bb37b5 | 1888 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
1889 | { |
1890 | /* Find out if register prefixing is specified. */ | |
1891 | int ask_naked_reg = 0; | |
1892 | ||
1893 | SKIP_WHITESPACE (); | |
29b0f896 | 1894 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 RH |
1895 | { |
1896 | char *string = input_line_pointer; | |
1897 | int e = get_symbol_end (); | |
1898 | ||
47926f60 | 1899 | if (strcmp (string, "prefix") == 0) |
252b5132 | 1900 | ask_naked_reg = 1; |
47926f60 | 1901 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
1902 | ask_naked_reg = -1; |
1903 | else | |
d0b47220 | 1904 | as_bad (_("bad argument to syntax directive.")); |
252b5132 RH |
1905 | *input_line_pointer = e; |
1906 | } | |
1907 | demand_empty_rest_of_line (); | |
c3332e24 | 1908 | |
252b5132 RH |
1909 | intel_syntax = syntax_flag; |
1910 | ||
1911 | if (ask_naked_reg == 0) | |
f86103b7 AM |
1912 | allow_naked_reg = (intel_syntax |
1913 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
1914 | else |
1915 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 1916 | |
ee86248c | 1917 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
7ab9ffdd | 1918 | |
e4a3b5a4 | 1919 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 1920 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 1921 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
1922 | } |
1923 | ||
1efbbeb4 L |
1924 | static void |
1925 | set_intel_mnemonic (int mnemonic_flag) | |
1926 | { | |
e1d4d893 | 1927 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
1928 | } |
1929 | ||
db51cc60 L |
1930 | static void |
1931 | set_allow_index_reg (int flag) | |
1932 | { | |
1933 | allow_index_reg = flag; | |
1934 | } | |
1935 | ||
cb19c032 L |
1936 | static void |
1937 | set_sse_check (int dummy ATTRIBUTE_UNUSED) | |
1938 | { | |
1939 | SKIP_WHITESPACE (); | |
1940 | ||
1941 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
1942 | { | |
1943 | char *string = input_line_pointer; | |
1944 | int e = get_symbol_end (); | |
1945 | ||
1946 | if (strcmp (string, "none") == 0) | |
1947 | sse_check = sse_check_none; | |
1948 | else if (strcmp (string, "warning") == 0) | |
1949 | sse_check = sse_check_warning; | |
1950 | else if (strcmp (string, "error") == 0) | |
1951 | sse_check = sse_check_error; | |
1952 | else | |
1953 | as_bad (_("bad argument to sse_check directive.")); | |
1954 | *input_line_pointer = e; | |
1955 | } | |
1956 | else | |
1957 | as_bad (_("missing argument for sse_check directive")); | |
1958 | ||
1959 | demand_empty_rest_of_line (); | |
1960 | } | |
1961 | ||
8a9036a4 L |
1962 | static void |
1963 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1964 | i386_cpu_flags new ATTRIBUTE_UNUSED) | |
1965 | { | |
1966 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
1967 | static const char *arch; | |
1968 | ||
1969 | /* Intel LIOM is only supported on ELF. */ | |
1970 | if (!IS_ELF) | |
1971 | return; | |
1972 | ||
1973 | if (!arch) | |
1974 | { | |
1975 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
1976 | use default_arch. */ | |
1977 | arch = cpu_arch_name; | |
1978 | if (!arch) | |
1979 | arch = default_arch; | |
1980 | } | |
1981 | ||
3632d14b | 1982 | /* If we are targeting Intel L1OM, we must enable it. */ |
8a9036a4 L |
1983 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM |
1984 | || new.bitfield.cpul1om) | |
1985 | return; | |
1986 | ||
1987 | as_bad (_("`%s' is not supported on `%s'"), name, arch); | |
1988 | #endif | |
1989 | } | |
1990 | ||
e413e4e9 | 1991 | static void |
e3bb37b5 | 1992 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 1993 | { |
47926f60 | 1994 | SKIP_WHITESPACE (); |
e413e4e9 | 1995 | |
29b0f896 | 1996 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 AM |
1997 | { |
1998 | char *string = input_line_pointer; | |
1999 | int e = get_symbol_end (); | |
9103f4f4 | 2000 | unsigned int i; |
40fb9820 | 2001 | i386_cpu_flags flags; |
e413e4e9 | 2002 | |
9103f4f4 | 2003 | for (i = 0; i < ARRAY_SIZE (cpu_arch); i++) |
e413e4e9 AM |
2004 | { |
2005 | if (strcmp (string, cpu_arch[i].name) == 0) | |
2006 | { | |
8a9036a4 L |
2007 | check_cpu_arch_compatible (string, cpu_arch[i].flags); |
2008 | ||
5c6af06e JB |
2009 | if (*string != '.') |
2010 | { | |
2011 | cpu_arch_name = cpu_arch[i].name; | |
2012 | cpu_sub_arch_name = NULL; | |
40fb9820 L |
2013 | cpu_arch_flags = cpu_arch[i].flags; |
2014 | if (flag_code == CODE_64BIT) | |
2015 | { | |
2016 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2017 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
2018 | } | |
2019 | else | |
2020 | { | |
2021 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2022 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
2023 | } | |
ccc9c027 | 2024 | cpu_arch_isa = cpu_arch[i].type; |
9103f4f4 | 2025 | cpu_arch_isa_flags = cpu_arch[i].flags; |
ccc9c027 L |
2026 | if (!cpu_arch_tune_set) |
2027 | { | |
2028 | cpu_arch_tune = cpu_arch_isa; | |
2029 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2030 | } | |
5c6af06e JB |
2031 | break; |
2032 | } | |
40fb9820 | 2033 | |
309d3373 JB |
2034 | if (strncmp (string + 1, "no", 2)) |
2035 | flags = cpu_flags_or (cpu_arch_flags, | |
2036 | cpu_arch[i].flags); | |
2037 | else | |
2038 | flags = cpu_flags_and_not (cpu_arch_flags, | |
2039 | cpu_arch[i].flags); | |
0dfbf9d7 | 2040 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
5c6af06e | 2041 | { |
6305a203 L |
2042 | if (cpu_sub_arch_name) |
2043 | { | |
2044 | char *name = cpu_sub_arch_name; | |
2045 | cpu_sub_arch_name = concat (name, | |
2046 | cpu_arch[i].name, | |
1bf57e9f | 2047 | (const char *) NULL); |
6305a203 L |
2048 | free (name); |
2049 | } | |
2050 | else | |
2051 | cpu_sub_arch_name = xstrdup (cpu_arch[i].name); | |
40fb9820 | 2052 | cpu_arch_flags = flags; |
5c6af06e JB |
2053 | } |
2054 | *input_line_pointer = e; | |
2055 | demand_empty_rest_of_line (); | |
2056 | return; | |
e413e4e9 AM |
2057 | } |
2058 | } | |
9103f4f4 | 2059 | if (i >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
2060 | as_bad (_("no such architecture: `%s'"), string); |
2061 | ||
2062 | *input_line_pointer = e; | |
2063 | } | |
2064 | else | |
2065 | as_bad (_("missing cpu architecture")); | |
2066 | ||
fddf5b5b AM |
2067 | no_cond_jump_promotion = 0; |
2068 | if (*input_line_pointer == ',' | |
29b0f896 | 2069 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b AM |
2070 | { |
2071 | char *string = ++input_line_pointer; | |
2072 | int e = get_symbol_end (); | |
2073 | ||
2074 | if (strcmp (string, "nojumps") == 0) | |
2075 | no_cond_jump_promotion = 1; | |
2076 | else if (strcmp (string, "jumps") == 0) | |
2077 | ; | |
2078 | else | |
2079 | as_bad (_("no such architecture modifier: `%s'"), string); | |
2080 | ||
2081 | *input_line_pointer = e; | |
2082 | } | |
2083 | ||
e413e4e9 AM |
2084 | demand_empty_rest_of_line (); |
2085 | } | |
2086 | ||
8a9036a4 L |
2087 | enum bfd_architecture |
2088 | i386_arch (void) | |
2089 | { | |
3632d14b | 2090 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 L |
2091 | { |
2092 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2093 | || flag_code != CODE_64BIT) | |
2094 | as_fatal (_("Intel L1OM is 64bit ELF only")); | |
2095 | return bfd_arch_l1om; | |
2096 | } | |
2097 | else | |
2098 | return bfd_arch_i386; | |
2099 | } | |
2100 | ||
b9d79e03 JH |
2101 | unsigned long |
2102 | i386_mach () | |
2103 | { | |
2104 | if (!strcmp (default_arch, "x86_64")) | |
8a9036a4 | 2105 | { |
3632d14b | 2106 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 L |
2107 | { |
2108 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
2109 | as_fatal (_("Intel L1OM is 64bit ELF only")); | |
2110 | return bfd_mach_l1om; | |
2111 | } | |
2112 | else | |
2113 | return bfd_mach_x86_64; | |
2114 | } | |
b9d79e03 JH |
2115 | else if (!strcmp (default_arch, "i386")) |
2116 | return bfd_mach_i386_i386; | |
2117 | else | |
2118 | as_fatal (_("Unknown architecture")); | |
2119 | } | |
b9d79e03 | 2120 | \f |
252b5132 RH |
2121 | void |
2122 | md_begin () | |
2123 | { | |
2124 | const char *hash_err; | |
2125 | ||
47926f60 | 2126 | /* Initialize op_hash hash table. */ |
252b5132 RH |
2127 | op_hash = hash_new (); |
2128 | ||
2129 | { | |
d3ce72d0 | 2130 | const insn_template *optab; |
29b0f896 | 2131 | templates *core_optab; |
252b5132 | 2132 | |
47926f60 KH |
2133 | /* Setup for loop. */ |
2134 | optab = i386_optab; | |
252b5132 RH |
2135 | core_optab = (templates *) xmalloc (sizeof (templates)); |
2136 | core_optab->start = optab; | |
2137 | ||
2138 | while (1) | |
2139 | { | |
2140 | ++optab; | |
2141 | if (optab->name == NULL | |
2142 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
2143 | { | |
2144 | /* different name --> ship out current template list; | |
47926f60 | 2145 | add to hash table; & begin anew. */ |
252b5132 RH |
2146 | core_optab->end = optab; |
2147 | hash_err = hash_insert (op_hash, | |
2148 | (optab - 1)->name, | |
5a49b8ac | 2149 | (void *) core_optab); |
252b5132 RH |
2150 | if (hash_err) |
2151 | { | |
252b5132 RH |
2152 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
2153 | (optab - 1)->name, | |
2154 | hash_err); | |
2155 | } | |
2156 | if (optab->name == NULL) | |
2157 | break; | |
2158 | core_optab = (templates *) xmalloc (sizeof (templates)); | |
2159 | core_optab->start = optab; | |
2160 | } | |
2161 | } | |
2162 | } | |
2163 | ||
47926f60 | 2164 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
2165 | reg_hash = hash_new (); |
2166 | { | |
29b0f896 | 2167 | const reg_entry *regtab; |
c3fe08fa | 2168 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 2169 | |
c3fe08fa | 2170 | for (regtab = i386_regtab; regtab_size--; regtab++) |
252b5132 | 2171 | { |
5a49b8ac | 2172 | hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); |
252b5132 | 2173 | if (hash_err) |
3e73aa7c JH |
2174 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
2175 | regtab->reg_name, | |
2176 | hash_err); | |
252b5132 RH |
2177 | } |
2178 | } | |
2179 | ||
47926f60 | 2180 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 2181 | { |
29b0f896 AM |
2182 | int c; |
2183 | char *p; | |
252b5132 RH |
2184 | |
2185 | for (c = 0; c < 256; c++) | |
2186 | { | |
3882b010 | 2187 | if (ISDIGIT (c)) |
252b5132 RH |
2188 | { |
2189 | digit_chars[c] = c; | |
2190 | mnemonic_chars[c] = c; | |
2191 | register_chars[c] = c; | |
2192 | operand_chars[c] = c; | |
2193 | } | |
3882b010 | 2194 | else if (ISLOWER (c)) |
252b5132 RH |
2195 | { |
2196 | mnemonic_chars[c] = c; | |
2197 | register_chars[c] = c; | |
2198 | operand_chars[c] = c; | |
2199 | } | |
3882b010 | 2200 | else if (ISUPPER (c)) |
252b5132 | 2201 | { |
3882b010 | 2202 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
2203 | register_chars[c] = mnemonic_chars[c]; |
2204 | operand_chars[c] = c; | |
2205 | } | |
2206 | ||
3882b010 | 2207 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
2208 | identifier_chars[c] = c; |
2209 | else if (c >= 128) | |
2210 | { | |
2211 | identifier_chars[c] = c; | |
2212 | operand_chars[c] = c; | |
2213 | } | |
2214 | } | |
2215 | ||
2216 | #ifdef LEX_AT | |
2217 | identifier_chars['@'] = '@'; | |
32137342 NC |
2218 | #endif |
2219 | #ifdef LEX_QM | |
2220 | identifier_chars['?'] = '?'; | |
2221 | operand_chars['?'] = '?'; | |
252b5132 | 2222 | #endif |
252b5132 | 2223 | digit_chars['-'] = '-'; |
c0f3af97 | 2224 | mnemonic_chars['_'] = '_'; |
791fe849 | 2225 | mnemonic_chars['-'] = '-'; |
0003779b | 2226 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
2227 | identifier_chars['_'] = '_'; |
2228 | identifier_chars['.'] = '.'; | |
2229 | ||
2230 | for (p = operand_special_chars; *p != '\0'; p++) | |
2231 | operand_chars[(unsigned char) *p] = *p; | |
2232 | } | |
2233 | ||
2234 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 2235 | if (IS_ELF) |
252b5132 RH |
2236 | { |
2237 | record_alignment (text_section, 2); | |
2238 | record_alignment (data_section, 2); | |
2239 | record_alignment (bss_section, 2); | |
2240 | } | |
2241 | #endif | |
a4447b93 RH |
2242 | |
2243 | if (flag_code == CODE_64BIT) | |
2244 | { | |
2245 | x86_dwarf2_return_column = 16; | |
2246 | x86_cie_data_alignment = -8; | |
2247 | } | |
2248 | else | |
2249 | { | |
2250 | x86_dwarf2_return_column = 8; | |
2251 | x86_cie_data_alignment = -4; | |
2252 | } | |
252b5132 RH |
2253 | } |
2254 | ||
2255 | void | |
e3bb37b5 | 2256 | i386_print_statistics (FILE *file) |
252b5132 RH |
2257 | { |
2258 | hash_print_statistics (file, "i386 opcode", op_hash); | |
2259 | hash_print_statistics (file, "i386 register", reg_hash); | |
2260 | } | |
2261 | \f | |
252b5132 RH |
2262 | #ifdef DEBUG386 |
2263 | ||
ce8a8b2f | 2264 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 2265 | static void pte (insn_template *); |
40fb9820 | 2266 | static void pt (i386_operand_type); |
e3bb37b5 L |
2267 | static void pe (expressionS *); |
2268 | static void ps (symbolS *); | |
252b5132 RH |
2269 | |
2270 | static void | |
e3bb37b5 | 2271 | pi (char *line, i386_insn *x) |
252b5132 | 2272 | { |
09f131f2 | 2273 | unsigned int i; |
252b5132 RH |
2274 | |
2275 | fprintf (stdout, "%s: template ", line); | |
2276 | pte (&x->tm); | |
09f131f2 JH |
2277 | fprintf (stdout, " address: base %s index %s scale %x\n", |
2278 | x->base_reg ? x->base_reg->reg_name : "none", | |
2279 | x->index_reg ? x->index_reg->reg_name : "none", | |
2280 | x->log2_scale_factor); | |
2281 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 2282 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
2283 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
2284 | x->sib.base, x->sib.index, x->sib.scale); | |
2285 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
2286 | (x->rex & REX_W) != 0, |
2287 | (x->rex & REX_R) != 0, | |
2288 | (x->rex & REX_X) != 0, | |
2289 | (x->rex & REX_B) != 0); | |
252b5132 RH |
2290 | for (i = 0; i < x->operands; i++) |
2291 | { | |
2292 | fprintf (stdout, " #%d: ", i + 1); | |
2293 | pt (x->types[i]); | |
2294 | fprintf (stdout, "\n"); | |
40fb9820 L |
2295 | if (x->types[i].bitfield.reg8 |
2296 | || x->types[i].bitfield.reg16 | |
2297 | || x->types[i].bitfield.reg32 | |
2298 | || x->types[i].bitfield.reg64 | |
2299 | || x->types[i].bitfield.regmmx | |
2300 | || x->types[i].bitfield.regxmm | |
c0f3af97 | 2301 | || x->types[i].bitfield.regymm |
40fb9820 L |
2302 | || x->types[i].bitfield.sreg2 |
2303 | || x->types[i].bitfield.sreg3 | |
2304 | || x->types[i].bitfield.control | |
2305 | || x->types[i].bitfield.debug | |
2306 | || x->types[i].bitfield.test) | |
520dc8e8 | 2307 | fprintf (stdout, "%s\n", x->op[i].regs->reg_name); |
40fb9820 | 2308 | if (operand_type_check (x->types[i], imm)) |
520dc8e8 | 2309 | pe (x->op[i].imms); |
40fb9820 | 2310 | if (operand_type_check (x->types[i], disp)) |
520dc8e8 | 2311 | pe (x->op[i].disps); |
252b5132 RH |
2312 | } |
2313 | } | |
2314 | ||
2315 | static void | |
d3ce72d0 | 2316 | pte (insn_template *t) |
252b5132 | 2317 | { |
09f131f2 | 2318 | unsigned int i; |
252b5132 | 2319 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 2320 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
2321 | if (t->extension_opcode != None) |
2322 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 2323 | if (t->opcode_modifier.d) |
252b5132 | 2324 | fprintf (stdout, "D"); |
40fb9820 | 2325 | if (t->opcode_modifier.w) |
252b5132 RH |
2326 | fprintf (stdout, "W"); |
2327 | fprintf (stdout, "\n"); | |
2328 | for (i = 0; i < t->operands; i++) | |
2329 | { | |
2330 | fprintf (stdout, " #%d type ", i + 1); | |
2331 | pt (t->operand_types[i]); | |
2332 | fprintf (stdout, "\n"); | |
2333 | } | |
2334 | } | |
2335 | ||
2336 | static void | |
e3bb37b5 | 2337 | pe (expressionS *e) |
252b5132 | 2338 | { |
24eab124 | 2339 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
2340 | fprintf (stdout, " add_number %ld (%lx)\n", |
2341 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
2342 | if (e->X_add_symbol) |
2343 | { | |
2344 | fprintf (stdout, " add_symbol "); | |
2345 | ps (e->X_add_symbol); | |
2346 | fprintf (stdout, "\n"); | |
2347 | } | |
2348 | if (e->X_op_symbol) | |
2349 | { | |
2350 | fprintf (stdout, " op_symbol "); | |
2351 | ps (e->X_op_symbol); | |
2352 | fprintf (stdout, "\n"); | |
2353 | } | |
2354 | } | |
2355 | ||
2356 | static void | |
e3bb37b5 | 2357 | ps (symbolS *s) |
252b5132 RH |
2358 | { |
2359 | fprintf (stdout, "%s type %s%s", | |
2360 | S_GET_NAME (s), | |
2361 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
2362 | segment_name (S_GET_SEGMENT (s))); | |
2363 | } | |
2364 | ||
7b81dfbb | 2365 | static struct type_name |
252b5132 | 2366 | { |
40fb9820 L |
2367 | i386_operand_type mask; |
2368 | const char *name; | |
252b5132 | 2369 | } |
7b81dfbb | 2370 | const type_names[] = |
252b5132 | 2371 | { |
40fb9820 L |
2372 | { OPERAND_TYPE_REG8, "r8" }, |
2373 | { OPERAND_TYPE_REG16, "r16" }, | |
2374 | { OPERAND_TYPE_REG32, "r32" }, | |
2375 | { OPERAND_TYPE_REG64, "r64" }, | |
2376 | { OPERAND_TYPE_IMM8, "i8" }, | |
2377 | { OPERAND_TYPE_IMM8, "i8s" }, | |
2378 | { OPERAND_TYPE_IMM16, "i16" }, | |
2379 | { OPERAND_TYPE_IMM32, "i32" }, | |
2380 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
2381 | { OPERAND_TYPE_IMM64, "i64" }, | |
2382 | { OPERAND_TYPE_IMM1, "i1" }, | |
2383 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
2384 | { OPERAND_TYPE_DISP8, "d8" }, | |
2385 | { OPERAND_TYPE_DISP16, "d16" }, | |
2386 | { OPERAND_TYPE_DISP32, "d32" }, | |
2387 | { OPERAND_TYPE_DISP32S, "d32s" }, | |
2388 | { OPERAND_TYPE_DISP64, "d64" }, | |
2389 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, | |
2390 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
2391 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
2392 | { OPERAND_TYPE_TEST, "test reg" }, | |
2393 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
2394 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
2395 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
2396 | { OPERAND_TYPE_SREG2, "SReg2" }, | |
2397 | { OPERAND_TYPE_SREG3, "SReg3" }, | |
2398 | { OPERAND_TYPE_ACC, "Acc" }, | |
2399 | { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" }, | |
2400 | { OPERAND_TYPE_REGMMX, "rMMX" }, | |
2401 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
0349dc08 | 2402 | { OPERAND_TYPE_REGYMM, "rYMM" }, |
40fb9820 | 2403 | { OPERAND_TYPE_ESSEG, "es" }, |
252b5132 RH |
2404 | }; |
2405 | ||
2406 | static void | |
40fb9820 | 2407 | pt (i386_operand_type t) |
252b5132 | 2408 | { |
40fb9820 | 2409 | unsigned int j; |
c6fb90c8 | 2410 | i386_operand_type a; |
252b5132 | 2411 | |
40fb9820 | 2412 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
2413 | { |
2414 | a = operand_type_and (t, type_names[j].mask); | |
0349dc08 | 2415 | if (!operand_type_all_zero (&a)) |
c6fb90c8 L |
2416 | fprintf (stdout, "%s, ", type_names[j].name); |
2417 | } | |
252b5132 RH |
2418 | fflush (stdout); |
2419 | } | |
2420 | ||
2421 | #endif /* DEBUG386 */ | |
2422 | \f | |
252b5132 | 2423 | static bfd_reloc_code_real_type |
3956db08 | 2424 | reloc (unsigned int size, |
64e74474 AM |
2425 | int pcrel, |
2426 | int sign, | |
2427 | bfd_reloc_code_real_type other) | |
252b5132 | 2428 | { |
47926f60 | 2429 | if (other != NO_RELOC) |
3956db08 JB |
2430 | { |
2431 | reloc_howto_type *reloc; | |
2432 | ||
2433 | if (size == 8) | |
2434 | switch (other) | |
2435 | { | |
64e74474 AM |
2436 | case BFD_RELOC_X86_64_GOT32: |
2437 | return BFD_RELOC_X86_64_GOT64; | |
2438 | break; | |
2439 | case BFD_RELOC_X86_64_PLTOFF64: | |
2440 | return BFD_RELOC_X86_64_PLTOFF64; | |
2441 | break; | |
2442 | case BFD_RELOC_X86_64_GOTPC32: | |
2443 | other = BFD_RELOC_X86_64_GOTPC64; | |
2444 | break; | |
2445 | case BFD_RELOC_X86_64_GOTPCREL: | |
2446 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
2447 | break; | |
2448 | case BFD_RELOC_X86_64_TPOFF32: | |
2449 | other = BFD_RELOC_X86_64_TPOFF64; | |
2450 | break; | |
2451 | case BFD_RELOC_X86_64_DTPOFF32: | |
2452 | other = BFD_RELOC_X86_64_DTPOFF64; | |
2453 | break; | |
2454 | default: | |
2455 | break; | |
3956db08 | 2456 | } |
e05278af JB |
2457 | |
2458 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ | |
2459 | if (size == 4 && flag_code != CODE_64BIT) | |
2460 | sign = -1; | |
2461 | ||
3956db08 JB |
2462 | reloc = bfd_reloc_type_lookup (stdoutput, other); |
2463 | if (!reloc) | |
2464 | as_bad (_("unknown relocation (%u)"), other); | |
2465 | else if (size != bfd_get_reloc_size (reloc)) | |
2466 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), | |
2467 | bfd_get_reloc_size (reloc), | |
2468 | size); | |
2469 | else if (pcrel && !reloc->pc_relative) | |
2470 | as_bad (_("non-pc-relative relocation for pc-relative field")); | |
2471 | else if ((reloc->complain_on_overflow == complain_overflow_signed | |
2472 | && !sign) | |
2473 | || (reloc->complain_on_overflow == complain_overflow_unsigned | |
64e74474 | 2474 | && sign > 0)) |
3956db08 JB |
2475 | as_bad (_("relocated field and relocation type differ in signedness")); |
2476 | else | |
2477 | return other; | |
2478 | return NO_RELOC; | |
2479 | } | |
252b5132 RH |
2480 | |
2481 | if (pcrel) | |
2482 | { | |
3e73aa7c | 2483 | if (!sign) |
3956db08 | 2484 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
2485 | switch (size) |
2486 | { | |
2487 | case 1: return BFD_RELOC_8_PCREL; | |
2488 | case 2: return BFD_RELOC_16_PCREL; | |
2489 | case 4: return BFD_RELOC_32_PCREL; | |
d6ab8113 | 2490 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 2491 | } |
3956db08 | 2492 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
2493 | } |
2494 | else | |
2495 | { | |
3956db08 | 2496 | if (sign > 0) |
e5cb08ac | 2497 | switch (size) |
3e73aa7c JH |
2498 | { |
2499 | case 4: return BFD_RELOC_X86_64_32S; | |
2500 | } | |
2501 | else | |
2502 | switch (size) | |
2503 | { | |
2504 | case 1: return BFD_RELOC_8; | |
2505 | case 2: return BFD_RELOC_16; | |
2506 | case 4: return BFD_RELOC_32; | |
2507 | case 8: return BFD_RELOC_64; | |
2508 | } | |
3956db08 JB |
2509 | as_bad (_("cannot do %s %u byte relocation"), |
2510 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
2511 | } |
2512 | ||
0cc9e1d3 | 2513 | return NO_RELOC; |
252b5132 RH |
2514 | } |
2515 | ||
47926f60 KH |
2516 | /* Here we decide which fixups can be adjusted to make them relative to |
2517 | the beginning of the section instead of the symbol. Basically we need | |
2518 | to make sure that the dynamic relocations are done correctly, so in | |
2519 | some cases we force the original symbol to be used. */ | |
2520 | ||
252b5132 | 2521 | int |
e3bb37b5 | 2522 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 2523 | { |
6d249963 | 2524 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 2525 | if (!IS_ELF) |
31312f95 AM |
2526 | return 1; |
2527 | ||
a161fe53 AM |
2528 | /* Don't adjust pc-relative references to merge sections in 64-bit |
2529 | mode. */ | |
2530 | if (use_rela_relocations | |
2531 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
2532 | && fixP->fx_pcrel) | |
252b5132 | 2533 | return 0; |
31312f95 | 2534 | |
8d01d9a9 AJ |
2535 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
2536 | and changed later by validate_fix. */ | |
2537 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
2538 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
2539 | return 0; | |
2540 | ||
ce8a8b2f | 2541 | /* adjust_reloc_syms doesn't know about the GOT. */ |
252b5132 RH |
2542 | if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF |
2543 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 | |
2544 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
13ae64f3 JJ |
2545 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
2546 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
2547 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
2548 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
2549 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
2550 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
2551 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
2552 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
2553 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
2554 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c JH |
2555 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
2556 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
80b3ee89 | 2557 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
bffbf940 JJ |
2558 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
2559 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
2560 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 2561 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
2562 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
2563 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
2564 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
2565 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
2566 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
2567 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
2568 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
2569 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
2570 | return 0; | |
31312f95 | 2571 | #endif |
252b5132 RH |
2572 | return 1; |
2573 | } | |
252b5132 | 2574 | |
b4cac588 | 2575 | static int |
e3bb37b5 | 2576 | intel_float_operand (const char *mnemonic) |
252b5132 | 2577 | { |
9306ca4a JB |
2578 | /* Note that the value returned is meaningful only for opcodes with (memory) |
2579 | operands, hence the code here is free to improperly handle opcodes that | |
2580 | have no operands (for better performance and smaller code). */ | |
2581 | ||
2582 | if (mnemonic[0] != 'f') | |
2583 | return 0; /* non-math */ | |
2584 | ||
2585 | switch (mnemonic[1]) | |
2586 | { | |
2587 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
2588 | the fs segment override prefix not currently handled because no | |
2589 | call path can make opcodes without operands get here */ | |
2590 | case 'i': | |
2591 | return 2 /* integer op */; | |
2592 | case 'l': | |
2593 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
2594 | return 3; /* fldcw/fldenv */ | |
2595 | break; | |
2596 | case 'n': | |
2597 | if (mnemonic[2] != 'o' /* fnop */) | |
2598 | return 3; /* non-waiting control op */ | |
2599 | break; | |
2600 | case 'r': | |
2601 | if (mnemonic[2] == 's') | |
2602 | return 3; /* frstor/frstpm */ | |
2603 | break; | |
2604 | case 's': | |
2605 | if (mnemonic[2] == 'a') | |
2606 | return 3; /* fsave */ | |
2607 | if (mnemonic[2] == 't') | |
2608 | { | |
2609 | switch (mnemonic[3]) | |
2610 | { | |
2611 | case 'c': /* fstcw */ | |
2612 | case 'd': /* fstdw */ | |
2613 | case 'e': /* fstenv */ | |
2614 | case 's': /* fsts[gw] */ | |
2615 | return 3; | |
2616 | } | |
2617 | } | |
2618 | break; | |
2619 | case 'x': | |
2620 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
2621 | return 0; /* fxsave/fxrstor are not really math ops */ | |
2622 | break; | |
2623 | } | |
252b5132 | 2624 | |
9306ca4a | 2625 | return 1; |
252b5132 RH |
2626 | } |
2627 | ||
c0f3af97 L |
2628 | /* Build the VEX prefix. */ |
2629 | ||
2630 | static void | |
d3ce72d0 | 2631 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
2632 | { |
2633 | unsigned int register_specifier; | |
2634 | unsigned int implied_prefix; | |
2635 | unsigned int vector_length; | |
2636 | ||
2637 | /* Check register specifier. */ | |
2638 | if (i.vex.register_specifier) | |
2639 | { | |
2640 | register_specifier = i.vex.register_specifier->reg_num; | |
2641 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
2642 | register_specifier += 8; | |
2643 | register_specifier = ~register_specifier & 0xf; | |
2644 | } | |
2645 | else | |
2646 | register_specifier = 0xf; | |
2647 | ||
fa99fab2 L |
2648 | /* Use 2-byte VEX prefix by swappping destination and source |
2649 | operand. */ | |
2650 | if (!i.swap_operand | |
2651 | && i.operands == i.reg_operands | |
2652 | && i.tm.opcode_modifier.vex0f | |
2653 | && i.tm.opcode_modifier.s | |
2654 | && i.rex == REX_B) | |
2655 | { | |
2656 | unsigned int xchg = i.operands - 1; | |
2657 | union i386_op temp_op; | |
2658 | i386_operand_type temp_type; | |
2659 | ||
2660 | temp_type = i.types[xchg]; | |
2661 | i.types[xchg] = i.types[0]; | |
2662 | i.types[0] = temp_type; | |
2663 | temp_op = i.op[xchg]; | |
2664 | i.op[xchg] = i.op[0]; | |
2665 | i.op[0] = temp_op; | |
2666 | ||
9c2799c2 | 2667 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
2668 | |
2669 | i.rex = REX_R; | |
2670 | xchg = i.rm.regmem; | |
2671 | i.rm.regmem = i.rm.reg; | |
2672 | i.rm.reg = xchg; | |
2673 | ||
2674 | /* Use the next insn. */ | |
2675 | i.tm = t[1]; | |
2676 | } | |
2677 | ||
c0f3af97 L |
2678 | vector_length = i.tm.opcode_modifier.vex256 ? 1 : 0; |
2679 | ||
2680 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
2681 | { | |
2682 | case 0: | |
2683 | implied_prefix = 0; | |
2684 | break; | |
2685 | case DATA_PREFIX_OPCODE: | |
2686 | implied_prefix = 1; | |
2687 | break; | |
2688 | case REPE_PREFIX_OPCODE: | |
2689 | implied_prefix = 2; | |
2690 | break; | |
2691 | case REPNE_PREFIX_OPCODE: | |
2692 | implied_prefix = 3; | |
2693 | break; | |
2694 | default: | |
2695 | abort (); | |
2696 | } | |
2697 | ||
2698 | /* Use 2-byte VEX prefix if possible. */ | |
2699 | if (i.tm.opcode_modifier.vex0f | |
2700 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) | |
2701 | { | |
2702 | /* 2-byte VEX prefix. */ | |
2703 | unsigned int r; | |
2704 | ||
2705 | i.vex.length = 2; | |
2706 | i.vex.bytes[0] = 0xc5; | |
2707 | ||
2708 | /* Check the REX.R bit. */ | |
2709 | r = (i.rex & REX_R) ? 0 : 1; | |
2710 | i.vex.bytes[1] = (r << 7 | |
2711 | | register_specifier << 3 | |
2712 | | vector_length << 2 | |
2713 | | implied_prefix); | |
2714 | } | |
2715 | else | |
2716 | { | |
2717 | /* 3-byte VEX prefix. */ | |
2718 | unsigned int m, w; | |
2719 | ||
2720 | if (i.tm.opcode_modifier.vex0f) | |
2721 | m = 0x1; | |
2722 | else if (i.tm.opcode_modifier.vex0f38) | |
2723 | m = 0x2; | |
2724 | else if (i.tm.opcode_modifier.vex0f3a) | |
2725 | m = 0x3; | |
2726 | else | |
2727 | abort (); | |
2728 | ||
2729 | i.vex.length = 3; | |
2730 | i.vex.bytes[0] = 0xc4; | |
2731 | ||
2732 | /* The high 3 bits of the second VEX byte are 1's compliment | |
2733 | of RXB bits from REX. */ | |
2734 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
2735 | ||
2736 | /* Check the REX.W bit. */ | |
2737 | w = (i.rex & REX_W) ? 1 : 0; | |
2738 | if (i.tm.opcode_modifier.vexw0 || i.tm.opcode_modifier.vexw1) | |
2739 | { | |
2740 | if (w) | |
2741 | abort (); | |
2742 | ||
2743 | if (i.tm.opcode_modifier.vexw1) | |
2744 | w = 1; | |
2745 | } | |
2746 | ||
2747 | i.vex.bytes[2] = (w << 7 | |
2748 | | register_specifier << 3 | |
2749 | | vector_length << 2 | |
2750 | | implied_prefix); | |
2751 | } | |
2752 | } | |
2753 | ||
65da13b5 L |
2754 | static void |
2755 | process_immext (void) | |
2756 | { | |
2757 | expressionS *exp; | |
2758 | ||
2759 | if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0) | |
2760 | { | |
1fed0ba1 L |
2761 | /* SSE3 Instructions have the fixed operands with an opcode |
2762 | suffix which is coded in the same place as an 8-bit immediate | |
2763 | field would be. Here we check those operands and remove them | |
2764 | afterwards. */ | |
65da13b5 L |
2765 | unsigned int x; |
2766 | ||
2767 | for (x = 0; x < i.operands; x++) | |
2768 | if (i.op[x].regs->reg_num != x) | |
2769 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), | |
1fed0ba1 L |
2770 | register_prefix, i.op[x].regs->reg_name, x + 1, |
2771 | i.tm.name); | |
2772 | ||
2773 | i.operands = 0; | |
65da13b5 L |
2774 | } |
2775 | ||
c0f3af97 | 2776 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
2777 | which is coded in the same place as an 8-bit immediate field |
2778 | would be. Here we fake an 8-bit immediate operand from the | |
2779 | opcode suffix stored in tm.extension_opcode. | |
2780 | ||
c1e679ec | 2781 | AVX instructions also use this encoding, for some of |
c0f3af97 | 2782 | 3 argument instructions. */ |
65da13b5 | 2783 | |
9c2799c2 | 2784 | gas_assert (i.imm_operands == 0 |
7ab9ffdd L |
2785 | && (i.operands <= 2 |
2786 | || (i.tm.opcode_modifier.vex | |
2787 | && i.operands <= 4))); | |
65da13b5 L |
2788 | |
2789 | exp = &im_expressions[i.imm_operands++]; | |
2790 | i.op[i.operands].imms = exp; | |
2791 | i.types[i.operands] = imm8; | |
2792 | i.operands++; | |
2793 | exp->X_op = O_constant; | |
2794 | exp->X_add_number = i.tm.extension_opcode; | |
2795 | i.tm.extension_opcode = None; | |
2796 | } | |
2797 | ||
252b5132 RH |
2798 | /* This is the guts of the machine-dependent assembler. LINE points to a |
2799 | machine dependent instruction. This function is supposed to emit | |
2800 | the frags/bytes it assembles to. */ | |
2801 | ||
2802 | void | |
65da13b5 | 2803 | md_assemble (char *line) |
252b5132 | 2804 | { |
40fb9820 | 2805 | unsigned int j; |
252b5132 | 2806 | char mnemonic[MAX_MNEM_SIZE]; |
d3ce72d0 | 2807 | const insn_template *t; |
252b5132 | 2808 | |
47926f60 | 2809 | /* Initialize globals. */ |
252b5132 RH |
2810 | memset (&i, '\0', sizeof (i)); |
2811 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 2812 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
2813 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
2814 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 2815 | save_stack_p = save_stack; |
252b5132 RH |
2816 | |
2817 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
2818 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 2819 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 2820 | |
29b0f896 AM |
2821 | line = parse_insn (line, mnemonic); |
2822 | if (line == NULL) | |
2823 | return; | |
252b5132 | 2824 | |
29b0f896 | 2825 | line = parse_operands (line, mnemonic); |
ee86248c | 2826 | this_operand = -1; |
29b0f896 AM |
2827 | if (line == NULL) |
2828 | return; | |
252b5132 | 2829 | |
29b0f896 AM |
2830 | /* Now we've parsed the mnemonic into a set of templates, and have the |
2831 | operands at hand. */ | |
2832 | ||
2833 | /* All intel opcodes have reversed operands except for "bound" and | |
2834 | "enter". We also don't reverse intersegment "jmp" and "call" | |
2835 | instructions with 2 immediate operands so that the immediate segment | |
050dfa73 | 2836 | precedes the offset, as it does when in AT&T mode. */ |
4d456e3d L |
2837 | if (intel_syntax |
2838 | && i.operands > 1 | |
29b0f896 | 2839 | && (strcmp (mnemonic, "bound") != 0) |
30123838 | 2840 | && (strcmp (mnemonic, "invlpga") != 0) |
40fb9820 L |
2841 | && !(operand_type_check (i.types[0], imm) |
2842 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
2843 | swap_operands (); |
2844 | ||
ec56d5c0 JB |
2845 | /* The order of the immediates should be reversed |
2846 | for 2 immediates extrq and insertq instructions */ | |
2847 | if (i.imm_operands == 2 | |
2848 | && (strcmp (mnemonic, "extrq") == 0 | |
2849 | || strcmp (mnemonic, "insertq") == 0)) | |
2850 | swap_2_operands (0, 1); | |
2851 | ||
29b0f896 AM |
2852 | if (i.imm_operands) |
2853 | optimize_imm (); | |
2854 | ||
b300c311 L |
2855 | /* Don't optimize displacement for movabs since it only takes 64bit |
2856 | displacement. */ | |
2857 | if (i.disp_operands | |
2858 | && (flag_code != CODE_64BIT | |
2859 | || strcmp (mnemonic, "movabs") != 0)) | |
29b0f896 AM |
2860 | optimize_disp (); |
2861 | ||
2862 | /* Next, we find a template that matches the given insn, | |
2863 | making sure the overlap of the given operands types is consistent | |
2864 | with the template operand types. */ | |
252b5132 | 2865 | |
fa99fab2 | 2866 | if (!(t = match_template ())) |
29b0f896 | 2867 | return; |
252b5132 | 2868 | |
daf50ae7 | 2869 | if (sse_check != sse_check_none |
81f8a913 | 2870 | && !i.tm.opcode_modifier.noavx |
daf50ae7 L |
2871 | && (i.tm.cpu_flags.bitfield.cpusse |
2872 | || i.tm.cpu_flags.bitfield.cpusse2 | |
2873 | || i.tm.cpu_flags.bitfield.cpusse3 | |
2874 | || i.tm.cpu_flags.bitfield.cpussse3 | |
2875 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
2876 | || i.tm.cpu_flags.bitfield.cpusse4_2)) | |
2877 | { | |
2878 | (sse_check == sse_check_warning | |
2879 | ? as_warn | |
2880 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); | |
2881 | } | |
2882 | ||
321fd21e L |
2883 | /* Zap movzx and movsx suffix. The suffix has been set from |
2884 | "word ptr" or "byte ptr" on the source operand in Intel syntax | |
2885 | or extracted from mnemonic in AT&T syntax. But we'll use | |
2886 | the destination register to choose the suffix for encoding. */ | |
2887 | if ((i.tm.base_opcode & ~9) == 0x0fb6) | |
cd61ebfe | 2888 | { |
321fd21e L |
2889 | /* In Intel syntax, there must be a suffix. In AT&T syntax, if |
2890 | there is no suffix, the default will be byte extension. */ | |
2891 | if (i.reg_operands != 2 | |
2892 | && !i.suffix | |
7ab9ffdd | 2893 | && intel_syntax) |
321fd21e L |
2894 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
2895 | ||
2896 | i.suffix = 0; | |
cd61ebfe | 2897 | } |
24eab124 | 2898 | |
40fb9820 | 2899 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
2900 | if (!add_prefix (FWAIT_OPCODE)) |
2901 | return; | |
252b5132 | 2902 | |
29b0f896 | 2903 | /* Check string instruction segment overrides. */ |
40fb9820 | 2904 | if (i.tm.opcode_modifier.isstring && i.mem_operands != 0) |
29b0f896 AM |
2905 | { |
2906 | if (!check_string ()) | |
5dd0794d | 2907 | return; |
fc0763e6 | 2908 | i.disp_operands = 0; |
29b0f896 | 2909 | } |
5dd0794d | 2910 | |
29b0f896 AM |
2911 | if (!process_suffix ()) |
2912 | return; | |
e413e4e9 | 2913 | |
bc0844ae L |
2914 | /* Update operand types. */ |
2915 | for (j = 0; j < i.operands; j++) | |
2916 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
2917 | ||
29b0f896 AM |
2918 | /* Make still unresolved immediate matches conform to size of immediate |
2919 | given in i.suffix. */ | |
2920 | if (!finalize_imm ()) | |
2921 | return; | |
252b5132 | 2922 | |
40fb9820 | 2923 | if (i.types[0].bitfield.imm1) |
29b0f896 | 2924 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 2925 | |
9afe6eb8 L |
2926 | /* We only need to check those implicit registers for instructions |
2927 | with 3 operands or less. */ | |
2928 | if (i.operands <= 3) | |
2929 | for (j = 0; j < i.operands; j++) | |
2930 | if (i.types[j].bitfield.inoutportreg | |
2931 | || i.types[j].bitfield.shiftcount | |
2932 | || i.types[j].bitfield.acc | |
2933 | || i.types[j].bitfield.floatacc) | |
2934 | i.reg_operands--; | |
40fb9820 | 2935 | |
c0f3af97 L |
2936 | /* ImmExt should be processed after SSE2AVX. */ |
2937 | if (!i.tm.opcode_modifier.sse2avx | |
2938 | && i.tm.opcode_modifier.immext) | |
65da13b5 | 2939 | process_immext (); |
252b5132 | 2940 | |
29b0f896 AM |
2941 | /* For insns with operands there are more diddles to do to the opcode. */ |
2942 | if (i.operands) | |
2943 | { | |
2944 | if (!process_operands ()) | |
2945 | return; | |
2946 | } | |
40fb9820 | 2947 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
2948 | { |
2949 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
2950 | as_warn (_("translating to `%sp'"), i.tm.name); | |
2951 | } | |
252b5132 | 2952 | |
c0f3af97 | 2953 | if (i.tm.opcode_modifier.vex) |
fa99fab2 | 2954 | build_vex_prefix (t); |
c0f3af97 | 2955 | |
29b0f896 AM |
2956 | /* Handle conversion of 'int $3' --> special int3 insn. */ |
2957 | if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3) | |
2958 | { | |
2959 | i.tm.base_opcode = INT3_OPCODE; | |
2960 | i.imm_operands = 0; | |
2961 | } | |
252b5132 | 2962 | |
40fb9820 L |
2963 | if ((i.tm.opcode_modifier.jump |
2964 | || i.tm.opcode_modifier.jumpbyte | |
2965 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 AM |
2966 | && i.op[0].disps->X_op == O_constant) |
2967 | { | |
2968 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
2969 | the absolute address given by the constant. Since ix86 jumps and | |
2970 | calls are pc relative, we need to generate a reloc. */ | |
2971 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
2972 | i.op[0].disps->X_op = O_symbol; | |
2973 | } | |
252b5132 | 2974 | |
40fb9820 | 2975 | if (i.tm.opcode_modifier.rex64) |
161a04f6 | 2976 | i.rex |= REX_W; |
252b5132 | 2977 | |
29b0f896 AM |
2978 | /* For 8 bit registers we need an empty rex prefix. Also if the |
2979 | instruction already has a prefix, we need to convert old | |
2980 | registers to new ones. */ | |
773f551c | 2981 | |
40fb9820 | 2982 | if ((i.types[0].bitfield.reg8 |
29b0f896 | 2983 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
40fb9820 | 2984 | || (i.types[1].bitfield.reg8 |
29b0f896 | 2985 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
40fb9820 L |
2986 | || ((i.types[0].bitfield.reg8 |
2987 | || i.types[1].bitfield.reg8) | |
29b0f896 AM |
2988 | && i.rex != 0)) |
2989 | { | |
2990 | int x; | |
726c5dcd | 2991 | |
29b0f896 AM |
2992 | i.rex |= REX_OPCODE; |
2993 | for (x = 0; x < 2; x++) | |
2994 | { | |
2995 | /* Look for 8 bit operand that uses old registers. */ | |
40fb9820 | 2996 | if (i.types[x].bitfield.reg8 |
29b0f896 | 2997 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 2998 | { |
29b0f896 AM |
2999 | /* In case it is "hi" register, give up. */ |
3000 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 3001 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 3002 | "instruction requiring REX prefix."), |
a540244d | 3003 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 3004 | |
29b0f896 AM |
3005 | /* Otherwise it is equivalent to the extended register. |
3006 | Since the encoding doesn't change this is merely | |
3007 | cosmetic cleanup for debug output. */ | |
3008 | ||
3009 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 3010 | } |
29b0f896 AM |
3011 | } |
3012 | } | |
773f551c | 3013 | |
7ab9ffdd | 3014 | if (i.rex != 0) |
29b0f896 AM |
3015 | add_prefix (REX_OPCODE | i.rex); |
3016 | ||
3017 | /* We are ready to output the insn. */ | |
3018 | output_insn (); | |
3019 | } | |
3020 | ||
3021 | static char * | |
e3bb37b5 | 3022 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
3023 | { |
3024 | char *l = line; | |
3025 | char *token_start = l; | |
3026 | char *mnem_p; | |
5c6af06e | 3027 | int supported; |
d3ce72d0 | 3028 | const insn_template *t; |
b6169b20 | 3029 | char *dot_p = NULL; |
29b0f896 AM |
3030 | |
3031 | /* Non-zero if we found a prefix only acceptable with string insns. */ | |
3032 | const char *expecting_string_instruction = NULL; | |
45288df1 | 3033 | |
29b0f896 AM |
3034 | while (1) |
3035 | { | |
3036 | mnem_p = mnemonic; | |
3037 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
3038 | { | |
b6169b20 L |
3039 | if (*mnem_p == '.') |
3040 | dot_p = mnem_p; | |
29b0f896 AM |
3041 | mnem_p++; |
3042 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 3043 | { |
29b0f896 AM |
3044 | as_bad (_("no such instruction: `%s'"), token_start); |
3045 | return NULL; | |
3046 | } | |
3047 | l++; | |
3048 | } | |
3049 | if (!is_space_char (*l) | |
3050 | && *l != END_OF_INSN | |
e44823cf JB |
3051 | && (intel_syntax |
3052 | || (*l != PREFIX_SEPARATOR | |
3053 | && *l != ','))) | |
29b0f896 AM |
3054 | { |
3055 | as_bad (_("invalid character %s in mnemonic"), | |
3056 | output_invalid (*l)); | |
3057 | return NULL; | |
3058 | } | |
3059 | if (token_start == l) | |
3060 | { | |
e44823cf | 3061 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
3062 | as_bad (_("expecting prefix; got nothing")); |
3063 | else | |
3064 | as_bad (_("expecting mnemonic; got nothing")); | |
3065 | return NULL; | |
3066 | } | |
45288df1 | 3067 | |
29b0f896 | 3068 | /* Look up instruction (or prefix) via hash table. */ |
d3ce72d0 | 3069 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
47926f60 | 3070 | |
29b0f896 AM |
3071 | if (*l != END_OF_INSN |
3072 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
3073 | && current_templates | |
40fb9820 | 3074 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 3075 | { |
c6fb90c8 | 3076 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
3077 | { |
3078 | as_bad ((flag_code != CODE_64BIT | |
3079 | ? _("`%s' is only supported in 64-bit mode") | |
3080 | : _("`%s' is not supported in 64-bit mode")), | |
3081 | current_templates->start->name); | |
3082 | return NULL; | |
3083 | } | |
29b0f896 AM |
3084 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
3085 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
40fb9820 L |
3086 | if ((current_templates->start->opcode_modifier.size16 |
3087 | || current_templates->start->opcode_modifier.size32) | |
29b0f896 | 3088 | && flag_code != CODE_64BIT |
40fb9820 | 3089 | && (current_templates->start->opcode_modifier.size32 |
29b0f896 AM |
3090 | ^ (flag_code == CODE_16BIT))) |
3091 | { | |
3092 | as_bad (_("redundant %s prefix"), | |
3093 | current_templates->start->name); | |
3094 | return NULL; | |
45288df1 | 3095 | } |
29b0f896 AM |
3096 | /* Add prefix, checking for repeated prefixes. */ |
3097 | switch (add_prefix (current_templates->start->base_opcode)) | |
3098 | { | |
3099 | case 0: | |
3100 | return NULL; | |
3101 | case 2: | |
3102 | expecting_string_instruction = current_templates->start->name; | |
3103 | break; | |
3104 | } | |
3105 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
3106 | token_start = ++l; | |
3107 | } | |
3108 | else | |
3109 | break; | |
3110 | } | |
45288df1 | 3111 | |
30a55f88 | 3112 | if (!current_templates) |
b6169b20 | 3113 | { |
30a55f88 L |
3114 | /* Check if we should swap operand in encoding. */ |
3115 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') | |
3116 | i.swap_operand = 1; | |
3117 | else | |
3118 | goto check_suffix; | |
3119 | mnem_p = dot_p; | |
3120 | *dot_p = '\0'; | |
d3ce72d0 | 3121 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
b6169b20 L |
3122 | } |
3123 | ||
29b0f896 AM |
3124 | if (!current_templates) |
3125 | { | |
b6169b20 | 3126 | check_suffix: |
29b0f896 AM |
3127 | /* See if we can get a match by trimming off a suffix. */ |
3128 | switch (mnem_p[-1]) | |
3129 | { | |
3130 | case WORD_MNEM_SUFFIX: | |
9306ca4a JB |
3131 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) |
3132 | i.suffix = SHORT_MNEM_SUFFIX; | |
3133 | else | |
29b0f896 AM |
3134 | case BYTE_MNEM_SUFFIX: |
3135 | case QWORD_MNEM_SUFFIX: | |
3136 | i.suffix = mnem_p[-1]; | |
3137 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
3138 | current_templates = (const templates *) hash_find (op_hash, |
3139 | mnemonic); | |
29b0f896 AM |
3140 | break; |
3141 | case SHORT_MNEM_SUFFIX: | |
3142 | case LONG_MNEM_SUFFIX: | |
3143 | if (!intel_syntax) | |
3144 | { | |
3145 | i.suffix = mnem_p[-1]; | |
3146 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
3147 | current_templates = (const templates *) hash_find (op_hash, |
3148 | mnemonic); | |
29b0f896 AM |
3149 | } |
3150 | break; | |
252b5132 | 3151 | |
29b0f896 AM |
3152 | /* Intel Syntax. */ |
3153 | case 'd': | |
3154 | if (intel_syntax) | |
3155 | { | |
9306ca4a | 3156 | if (intel_float_operand (mnemonic) == 1) |
29b0f896 AM |
3157 | i.suffix = SHORT_MNEM_SUFFIX; |
3158 | else | |
3159 | i.suffix = LONG_MNEM_SUFFIX; | |
3160 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
3161 | current_templates = (const templates *) hash_find (op_hash, |
3162 | mnemonic); | |
29b0f896 AM |
3163 | } |
3164 | break; | |
3165 | } | |
3166 | if (!current_templates) | |
3167 | { | |
3168 | as_bad (_("no such instruction: `%s'"), token_start); | |
3169 | return NULL; | |
3170 | } | |
3171 | } | |
252b5132 | 3172 | |
40fb9820 L |
3173 | if (current_templates->start->opcode_modifier.jump |
3174 | || current_templates->start->opcode_modifier.jumpbyte) | |
29b0f896 AM |
3175 | { |
3176 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
3177 | predict taken and predict not taken respectively. | |
3178 | I'm not sure that branch hints actually do anything on loop | |
3179 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
3180 | may work in the future and it doesn't hurt to accept them | |
3181 | now. */ | |
3182 | if (l[0] == ',' && l[1] == 'p') | |
3183 | { | |
3184 | if (l[2] == 't') | |
3185 | { | |
3186 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
3187 | return NULL; | |
3188 | l += 3; | |
3189 | } | |
3190 | else if (l[2] == 'n') | |
3191 | { | |
3192 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
3193 | return NULL; | |
3194 | l += 3; | |
3195 | } | |
3196 | } | |
3197 | } | |
3198 | /* Any other comma loses. */ | |
3199 | if (*l == ',') | |
3200 | { | |
3201 | as_bad (_("invalid character %s in mnemonic"), | |
3202 | output_invalid (*l)); | |
3203 | return NULL; | |
3204 | } | |
252b5132 | 3205 | |
29b0f896 | 3206 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
3207 | supported = 0; |
3208 | for (t = current_templates->start; t < current_templates->end; ++t) | |
3209 | { | |
c0f3af97 L |
3210 | supported |= cpu_flags_match (t); |
3211 | if (supported == CPU_FLAGS_PERFECT_MATCH) | |
3629bb00 | 3212 | goto skip; |
5c6af06e | 3213 | } |
3629bb00 | 3214 | |
c0f3af97 | 3215 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
5c6af06e JB |
3216 | { |
3217 | as_bad (flag_code == CODE_64BIT | |
3218 | ? _("`%s' is not supported in 64-bit mode") | |
3219 | : _("`%s' is only supported in 64-bit mode"), | |
3220 | current_templates->start->name); | |
3221 | return NULL; | |
3222 | } | |
c0f3af97 | 3223 | if (supported != CPU_FLAGS_PERFECT_MATCH) |
29b0f896 | 3224 | { |
3629bb00 | 3225 | as_bad (_("`%s' is not supported on `%s%s'"), |
7ab9ffdd | 3226 | current_templates->start->name, |
41aacd83 | 3227 | cpu_arch_name ? cpu_arch_name : default_arch, |
3629bb00 L |
3228 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); |
3229 | return NULL; | |
29b0f896 | 3230 | } |
3629bb00 L |
3231 | |
3232 | skip: | |
3233 | if (!cpu_arch_flags.bitfield.cpui386 | |
40fb9820 | 3234 | && (flag_code != CODE_16BIT)) |
29b0f896 AM |
3235 | { |
3236 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
3237 | } | |
252b5132 | 3238 | |
29b0f896 | 3239 | /* Check for rep/repne without a string instruction. */ |
f41bbced | 3240 | if (expecting_string_instruction) |
29b0f896 | 3241 | { |
f41bbced JB |
3242 | static templates override; |
3243 | ||
3244 | for (t = current_templates->start; t < current_templates->end; ++t) | |
40fb9820 | 3245 | if (t->opcode_modifier.isstring) |
f41bbced JB |
3246 | break; |
3247 | if (t >= current_templates->end) | |
3248 | { | |
3249 | as_bad (_("expecting string instruction after `%s'"), | |
64e74474 | 3250 | expecting_string_instruction); |
f41bbced JB |
3251 | return NULL; |
3252 | } | |
3253 | for (override.start = t; t < current_templates->end; ++t) | |
40fb9820 | 3254 | if (!t->opcode_modifier.isstring) |
f41bbced JB |
3255 | break; |
3256 | override.end = t; | |
3257 | current_templates = &override; | |
29b0f896 | 3258 | } |
252b5132 | 3259 | |
29b0f896 AM |
3260 | return l; |
3261 | } | |
252b5132 | 3262 | |
29b0f896 | 3263 | static char * |
e3bb37b5 | 3264 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
3265 | { |
3266 | char *token_start; | |
3138f287 | 3267 | |
29b0f896 AM |
3268 | /* 1 if operand is pending after ','. */ |
3269 | unsigned int expecting_operand = 0; | |
252b5132 | 3270 | |
29b0f896 AM |
3271 | /* Non-zero if operand parens not balanced. */ |
3272 | unsigned int paren_not_balanced; | |
3273 | ||
3274 | while (*l != END_OF_INSN) | |
3275 | { | |
3276 | /* Skip optional white space before operand. */ | |
3277 | if (is_space_char (*l)) | |
3278 | ++l; | |
3279 | if (!is_operand_char (*l) && *l != END_OF_INSN) | |
3280 | { | |
3281 | as_bad (_("invalid character %s before operand %d"), | |
3282 | output_invalid (*l), | |
3283 | i.operands + 1); | |
3284 | return NULL; | |
3285 | } | |
3286 | token_start = l; /* after white space */ | |
3287 | paren_not_balanced = 0; | |
3288 | while (paren_not_balanced || *l != ',') | |
3289 | { | |
3290 | if (*l == END_OF_INSN) | |
3291 | { | |
3292 | if (paren_not_balanced) | |
3293 | { | |
3294 | if (!intel_syntax) | |
3295 | as_bad (_("unbalanced parenthesis in operand %d."), | |
3296 | i.operands + 1); | |
3297 | else | |
3298 | as_bad (_("unbalanced brackets in operand %d."), | |
3299 | i.operands + 1); | |
3300 | return NULL; | |
3301 | } | |
3302 | else | |
3303 | break; /* we are done */ | |
3304 | } | |
3305 | else if (!is_operand_char (*l) && !is_space_char (*l)) | |
3306 | { | |
3307 | as_bad (_("invalid character %s in operand %d"), | |
3308 | output_invalid (*l), | |
3309 | i.operands + 1); | |
3310 | return NULL; | |
3311 | } | |
3312 | if (!intel_syntax) | |
3313 | { | |
3314 | if (*l == '(') | |
3315 | ++paren_not_balanced; | |
3316 | if (*l == ')') | |
3317 | --paren_not_balanced; | |
3318 | } | |
3319 | else | |
3320 | { | |
3321 | if (*l == '[') | |
3322 | ++paren_not_balanced; | |
3323 | if (*l == ']') | |
3324 | --paren_not_balanced; | |
3325 | } | |
3326 | l++; | |
3327 | } | |
3328 | if (l != token_start) | |
3329 | { /* Yes, we've read in another operand. */ | |
3330 | unsigned int operand_ok; | |
3331 | this_operand = i.operands++; | |
7d5e4556 | 3332 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
3333 | if (i.operands > MAX_OPERANDS) |
3334 | { | |
3335 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
3336 | MAX_OPERANDS); | |
3337 | return NULL; | |
3338 | } | |
3339 | /* Now parse operand adding info to 'i' as we go along. */ | |
3340 | END_STRING_AND_SAVE (l); | |
3341 | ||
3342 | if (intel_syntax) | |
3343 | operand_ok = | |
3344 | i386_intel_operand (token_start, | |
3345 | intel_float_operand (mnemonic)); | |
3346 | else | |
a7619375 | 3347 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
3348 | |
3349 | RESTORE_END_STRING (l); | |
3350 | if (!operand_ok) | |
3351 | return NULL; | |
3352 | } | |
3353 | else | |
3354 | { | |
3355 | if (expecting_operand) | |
3356 | { | |
3357 | expecting_operand_after_comma: | |
3358 | as_bad (_("expecting operand after ','; got nothing")); | |
3359 | return NULL; | |
3360 | } | |
3361 | if (*l == ',') | |
3362 | { | |
3363 | as_bad (_("expecting operand before ','; got nothing")); | |
3364 | return NULL; | |
3365 | } | |
3366 | } | |
7f3f1ea2 | 3367 | |
29b0f896 AM |
3368 | /* Now *l must be either ',' or END_OF_INSN. */ |
3369 | if (*l == ',') | |
3370 | { | |
3371 | if (*++l == END_OF_INSN) | |
3372 | { | |
3373 | /* Just skip it, if it's \n complain. */ | |
3374 | goto expecting_operand_after_comma; | |
3375 | } | |
3376 | expecting_operand = 1; | |
3377 | } | |
3378 | } | |
3379 | return l; | |
3380 | } | |
7f3f1ea2 | 3381 | |
050dfa73 | 3382 | static void |
4d456e3d | 3383 | swap_2_operands (int xchg1, int xchg2) |
050dfa73 MM |
3384 | { |
3385 | union i386_op temp_op; | |
40fb9820 | 3386 | i386_operand_type temp_type; |
050dfa73 | 3387 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 3388 | |
050dfa73 MM |
3389 | temp_type = i.types[xchg2]; |
3390 | i.types[xchg2] = i.types[xchg1]; | |
3391 | i.types[xchg1] = temp_type; | |
3392 | temp_op = i.op[xchg2]; | |
3393 | i.op[xchg2] = i.op[xchg1]; | |
3394 | i.op[xchg1] = temp_op; | |
3395 | temp_reloc = i.reloc[xchg2]; | |
3396 | i.reloc[xchg2] = i.reloc[xchg1]; | |
3397 | i.reloc[xchg1] = temp_reloc; | |
3398 | } | |
3399 | ||
29b0f896 | 3400 | static void |
e3bb37b5 | 3401 | swap_operands (void) |
29b0f896 | 3402 | { |
b7c61d9a | 3403 | switch (i.operands) |
050dfa73 | 3404 | { |
c0f3af97 | 3405 | case 5: |
b7c61d9a | 3406 | case 4: |
4d456e3d | 3407 | swap_2_operands (1, i.operands - 2); |
b7c61d9a L |
3408 | case 3: |
3409 | case 2: | |
4d456e3d | 3410 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
3411 | break; |
3412 | default: | |
3413 | abort (); | |
29b0f896 | 3414 | } |
29b0f896 AM |
3415 | |
3416 | if (i.mem_operands == 2) | |
3417 | { | |
3418 | const seg_entry *temp_seg; | |
3419 | temp_seg = i.seg[0]; | |
3420 | i.seg[0] = i.seg[1]; | |
3421 | i.seg[1] = temp_seg; | |
3422 | } | |
3423 | } | |
252b5132 | 3424 | |
29b0f896 AM |
3425 | /* Try to ensure constant immediates are represented in the smallest |
3426 | opcode possible. */ | |
3427 | static void | |
e3bb37b5 | 3428 | optimize_imm (void) |
29b0f896 AM |
3429 | { |
3430 | char guess_suffix = 0; | |
3431 | int op; | |
252b5132 | 3432 | |
29b0f896 AM |
3433 | if (i.suffix) |
3434 | guess_suffix = i.suffix; | |
3435 | else if (i.reg_operands) | |
3436 | { | |
3437 | /* Figure out a suffix from the last register operand specified. | |
3438 | We can't do this properly yet, ie. excluding InOutPortReg, | |
3439 | but the following works for instructions with immediates. | |
3440 | In any case, we can't set i.suffix yet. */ | |
3441 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 3442 | if (i.types[op].bitfield.reg8) |
7ab9ffdd | 3443 | { |
40fb9820 L |
3444 | guess_suffix = BYTE_MNEM_SUFFIX; |
3445 | break; | |
3446 | } | |
3447 | else if (i.types[op].bitfield.reg16) | |
252b5132 | 3448 | { |
40fb9820 L |
3449 | guess_suffix = WORD_MNEM_SUFFIX; |
3450 | break; | |
3451 | } | |
3452 | else if (i.types[op].bitfield.reg32) | |
3453 | { | |
3454 | guess_suffix = LONG_MNEM_SUFFIX; | |
3455 | break; | |
3456 | } | |
3457 | else if (i.types[op].bitfield.reg64) | |
3458 | { | |
3459 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 3460 | break; |
252b5132 | 3461 | } |
29b0f896 AM |
3462 | } |
3463 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
3464 | guess_suffix = WORD_MNEM_SUFFIX; | |
3465 | ||
3466 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 3467 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
3468 | { |
3469 | switch (i.op[op].imms->X_op) | |
252b5132 | 3470 | { |
29b0f896 AM |
3471 | case O_constant: |
3472 | /* If a suffix is given, this operand may be shortened. */ | |
3473 | switch (guess_suffix) | |
252b5132 | 3474 | { |
29b0f896 | 3475 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
3476 | i.types[op].bitfield.imm32 = 1; |
3477 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
3478 | break; |
3479 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
3480 | i.types[op].bitfield.imm16 = 1; |
3481 | i.types[op].bitfield.imm32 = 1; | |
3482 | i.types[op].bitfield.imm32s = 1; | |
3483 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
3484 | break; |
3485 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
3486 | i.types[op].bitfield.imm8 = 1; |
3487 | i.types[op].bitfield.imm8s = 1; | |
3488 | i.types[op].bitfield.imm16 = 1; | |
3489 | i.types[op].bitfield.imm32 = 1; | |
3490 | i.types[op].bitfield.imm32s = 1; | |
3491 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 3492 | break; |
252b5132 | 3493 | } |
252b5132 | 3494 | |
29b0f896 AM |
3495 | /* If this operand is at most 16 bits, convert it |
3496 | to a signed 16 bit number before trying to see | |
3497 | whether it will fit in an even smaller size. | |
3498 | This allows a 16-bit operand such as $0xffe0 to | |
3499 | be recognised as within Imm8S range. */ | |
40fb9820 | 3500 | if ((i.types[op].bitfield.imm16) |
29b0f896 | 3501 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
252b5132 | 3502 | { |
29b0f896 AM |
3503 | i.op[op].imms->X_add_number = |
3504 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
3505 | } | |
40fb9820 | 3506 | if ((i.types[op].bitfield.imm32) |
29b0f896 AM |
3507 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
3508 | == 0)) | |
3509 | { | |
3510 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
3511 | ^ ((offsetT) 1 << 31)) | |
3512 | - ((offsetT) 1 << 31)); | |
3513 | } | |
40fb9820 | 3514 | i.types[op] |
c6fb90c8 L |
3515 | = operand_type_or (i.types[op], |
3516 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 3517 | |
29b0f896 AM |
3518 | /* We must avoid matching of Imm32 templates when 64bit |
3519 | only immediate is available. */ | |
3520 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 3521 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 3522 | break; |
252b5132 | 3523 | |
29b0f896 AM |
3524 | case O_absent: |
3525 | case O_register: | |
3526 | abort (); | |
3527 | ||
3528 | /* Symbols and expressions. */ | |
3529 | default: | |
9cd96992 JB |
3530 | /* Convert symbolic operand to proper sizes for matching, but don't |
3531 | prevent matching a set of insns that only supports sizes other | |
3532 | than those matching the insn suffix. */ | |
3533 | { | |
40fb9820 | 3534 | i386_operand_type mask, allowed; |
d3ce72d0 | 3535 | const insn_template *t; |
9cd96992 | 3536 | |
0dfbf9d7 L |
3537 | operand_type_set (&mask, 0); |
3538 | operand_type_set (&allowed, 0); | |
40fb9820 | 3539 | |
4eed87de AM |
3540 | for (t = current_templates->start; |
3541 | t < current_templates->end; | |
3542 | ++t) | |
c6fb90c8 L |
3543 | allowed = operand_type_or (allowed, |
3544 | t->operand_types[op]); | |
9cd96992 JB |
3545 | switch (guess_suffix) |
3546 | { | |
3547 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
3548 | mask.bitfield.imm64 = 1; |
3549 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
3550 | break; |
3551 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 3552 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
3553 | break; |
3554 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 3555 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
3556 | break; |
3557 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 3558 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
3559 | break; |
3560 | default: | |
9cd96992 JB |
3561 | break; |
3562 | } | |
c6fb90c8 | 3563 | allowed = operand_type_and (mask, allowed); |
0dfbf9d7 | 3564 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 3565 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 3566 | } |
29b0f896 | 3567 | break; |
252b5132 | 3568 | } |
29b0f896 AM |
3569 | } |
3570 | } | |
47926f60 | 3571 | |
29b0f896 AM |
3572 | /* Try to use the smallest displacement type too. */ |
3573 | static void | |
e3bb37b5 | 3574 | optimize_disp (void) |
29b0f896 AM |
3575 | { |
3576 | int op; | |
3e73aa7c | 3577 | |
29b0f896 | 3578 | for (op = i.operands; --op >= 0;) |
40fb9820 | 3579 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 3580 | { |
b300c311 | 3581 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 3582 | { |
b300c311 | 3583 | offsetT disp = i.op[op].disps->X_add_number; |
29b0f896 | 3584 | |
40fb9820 | 3585 | if (i.types[op].bitfield.disp16 |
b300c311 L |
3586 | && (disp & ~(offsetT) 0xffff) == 0) |
3587 | { | |
3588 | /* If this operand is at most 16 bits, convert | |
3589 | to a signed 16 bit number and don't use 64bit | |
3590 | displacement. */ | |
3591 | disp = (((disp & 0xffff) ^ 0x8000) - 0x8000); | |
40fb9820 | 3592 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 3593 | } |
40fb9820 | 3594 | if (i.types[op].bitfield.disp32 |
b300c311 L |
3595 | && (disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
3596 | { | |
3597 | /* If this operand is at most 32 bits, convert | |
3598 | to a signed 32 bit number and don't use 64bit | |
3599 | displacement. */ | |
3600 | disp &= (((offsetT) 2 << 31) - 1); | |
3601 | disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
40fb9820 | 3602 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 3603 | } |
40fb9820 | 3604 | if (!disp && i.types[op].bitfield.baseindex) |
b300c311 | 3605 | { |
40fb9820 L |
3606 | i.types[op].bitfield.disp8 = 0; |
3607 | i.types[op].bitfield.disp16 = 0; | |
3608 | i.types[op].bitfield.disp32 = 0; | |
3609 | i.types[op].bitfield.disp32s = 0; | |
3610 | i.types[op].bitfield.disp64 = 0; | |
b300c311 L |
3611 | i.op[op].disps = 0; |
3612 | i.disp_operands--; | |
3613 | } | |
3614 | else if (flag_code == CODE_64BIT) | |
3615 | { | |
3616 | if (fits_in_signed_long (disp)) | |
28a9d8f5 | 3617 | { |
40fb9820 L |
3618 | i.types[op].bitfield.disp64 = 0; |
3619 | i.types[op].bitfield.disp32s = 1; | |
28a9d8f5 | 3620 | } |
b300c311 | 3621 | if (fits_in_unsigned_long (disp)) |
40fb9820 | 3622 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 3623 | } |
40fb9820 L |
3624 | if ((i.types[op].bitfield.disp32 |
3625 | || i.types[op].bitfield.disp32s | |
3626 | || i.types[op].bitfield.disp16) | |
b300c311 | 3627 | && fits_in_signed_byte (disp)) |
40fb9820 | 3628 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 3629 | } |
67a4f2b7 AO |
3630 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
3631 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
3632 | { | |
3633 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
3634 | i.op[op].disps, 0, i.reloc[op]); | |
40fb9820 L |
3635 | i.types[op].bitfield.disp8 = 0; |
3636 | i.types[op].bitfield.disp16 = 0; | |
3637 | i.types[op].bitfield.disp32 = 0; | |
3638 | i.types[op].bitfield.disp32s = 0; | |
3639 | i.types[op].bitfield.disp64 = 0; | |
67a4f2b7 AO |
3640 | } |
3641 | else | |
b300c311 | 3642 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 3643 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 3644 | } |
29b0f896 AM |
3645 | } |
3646 | ||
d3ce72d0 | 3647 | static const insn_template * |
e3bb37b5 | 3648 | match_template (void) |
29b0f896 AM |
3649 | { |
3650 | /* Points to template once we've found it. */ | |
d3ce72d0 | 3651 | const insn_template *t; |
40fb9820 | 3652 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 3653 | i386_operand_type overlap4; |
29b0f896 | 3654 | unsigned int found_reverse_match; |
40fb9820 L |
3655 | i386_opcode_modifier suffix_check; |
3656 | i386_operand_type operand_types [MAX_OPERANDS]; | |
539e75ad | 3657 | int addr_prefix_disp; |
a5c311ca | 3658 | unsigned int j; |
3629bb00 | 3659 | unsigned int found_cpu_match; |
45664ddb | 3660 | unsigned int check_register; |
29b0f896 | 3661 | |
c0f3af97 L |
3662 | #if MAX_OPERANDS != 5 |
3663 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
3664 | #endif |
3665 | ||
29b0f896 | 3666 | found_reverse_match = 0; |
539e75ad | 3667 | addr_prefix_disp = -1; |
40fb9820 L |
3668 | |
3669 | memset (&suffix_check, 0, sizeof (suffix_check)); | |
3670 | if (i.suffix == BYTE_MNEM_SUFFIX) | |
3671 | suffix_check.no_bsuf = 1; | |
3672 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
3673 | suffix_check.no_wsuf = 1; | |
3674 | else if (i.suffix == SHORT_MNEM_SUFFIX) | |
3675 | suffix_check.no_ssuf = 1; | |
3676 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
3677 | suffix_check.no_lsuf = 1; | |
3678 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
3679 | suffix_check.no_qsuf = 1; | |
3680 | else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
7ce189b3 | 3681 | suffix_check.no_ldsuf = 1; |
29b0f896 | 3682 | |
45aa61fe | 3683 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 3684 | { |
539e75ad L |
3685 | addr_prefix_disp = -1; |
3686 | ||
29b0f896 AM |
3687 | /* Must have right number of operands. */ |
3688 | if (i.operands != t->operands) | |
3689 | continue; | |
3690 | ||
50aecf8c | 3691 | /* Check processor support. */ |
c0f3af97 L |
3692 | found_cpu_match = (cpu_flags_match (t) |
3693 | == CPU_FLAGS_PERFECT_MATCH); | |
50aecf8c L |
3694 | if (!found_cpu_match) |
3695 | continue; | |
3696 | ||
e1d4d893 L |
3697 | /* Check old gcc support. */ |
3698 | if (!old_gcc && t->opcode_modifier.oldgcc) | |
3699 | continue; | |
3700 | ||
3701 | /* Check AT&T mnemonic. */ | |
3702 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) | |
1efbbeb4 L |
3703 | continue; |
3704 | ||
5c07affc L |
3705 | /* Check AT&T syntax Intel syntax. */ |
3706 | if ((intel_syntax && t->opcode_modifier.attsyntax) | |
3707 | || (!intel_syntax && t->opcode_modifier.intelsyntax)) | |
1efbbeb4 L |
3708 | continue; |
3709 | ||
20592a94 | 3710 | /* Check the suffix, except for some instructions in intel mode. */ |
567e4e96 L |
3711 | if ((!intel_syntax || !t->opcode_modifier.ignoresize) |
3712 | && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) | |
3713 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
3714 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
3715 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
3716 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
3717 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf))) | |
29b0f896 AM |
3718 | continue; |
3719 | ||
5c07affc | 3720 | if (!operand_size_match (t)) |
7d5e4556 | 3721 | continue; |
539e75ad | 3722 | |
5c07affc L |
3723 | for (j = 0; j < MAX_OPERANDS; j++) |
3724 | operand_types[j] = t->operand_types[j]; | |
3725 | ||
45aa61fe AM |
3726 | /* In general, don't allow 64-bit operands in 32-bit mode. */ |
3727 | if (i.suffix == QWORD_MNEM_SUFFIX | |
3728 | && flag_code != CODE_64BIT | |
3729 | && (intel_syntax | |
40fb9820 | 3730 | ? (!t->opcode_modifier.ignoresize |
45aa61fe AM |
3731 | && !intel_float_operand (t->name)) |
3732 | : intel_float_operand (t->name) != 2) | |
40fb9820 | 3733 | && ((!operand_types[0].bitfield.regmmx |
c0f3af97 L |
3734 | && !operand_types[0].bitfield.regxmm |
3735 | && !operand_types[0].bitfield.regymm) | |
40fb9820 | 3736 | || (!operand_types[t->operands > 1].bitfield.regmmx |
c0f3af97 L |
3737 | && !!operand_types[t->operands > 1].bitfield.regxmm |
3738 | && !!operand_types[t->operands > 1].bitfield.regymm)) | |
45aa61fe AM |
3739 | && (t->base_opcode != 0x0fc7 |
3740 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
3741 | continue; | |
3742 | ||
192dc9c6 JB |
3743 | /* In general, don't allow 32-bit operands on pre-386. */ |
3744 | else if (i.suffix == LONG_MNEM_SUFFIX | |
3745 | && !cpu_arch_flags.bitfield.cpui386 | |
3746 | && (intel_syntax | |
3747 | ? (!t->opcode_modifier.ignoresize | |
3748 | && !intel_float_operand (t->name)) | |
3749 | : intel_float_operand (t->name) != 2) | |
3750 | && ((!operand_types[0].bitfield.regmmx | |
3751 | && !operand_types[0].bitfield.regxmm) | |
3752 | || (!operand_types[t->operands > 1].bitfield.regmmx | |
3753 | && !!operand_types[t->operands > 1].bitfield.regxmm))) | |
3754 | continue; | |
3755 | ||
29b0f896 | 3756 | /* Do not verify operands when there are none. */ |
50aecf8c | 3757 | else |
29b0f896 | 3758 | { |
c6fb90c8 | 3759 | if (!t->operands) |
2dbab7d5 L |
3760 | /* We've found a match; break out of loop. */ |
3761 | break; | |
29b0f896 | 3762 | } |
252b5132 | 3763 | |
539e75ad L |
3764 | /* Address size prefix will turn Disp64/Disp32/Disp16 operand |
3765 | into Disp32/Disp16/Disp32 operand. */ | |
3766 | if (i.prefix[ADDR_PREFIX] != 0) | |
3767 | { | |
40fb9820 | 3768 | /* There should be only one Disp operand. */ |
539e75ad L |
3769 | switch (flag_code) |
3770 | { | |
3771 | case CODE_16BIT: | |
40fb9820 L |
3772 | for (j = 0; j < MAX_OPERANDS; j++) |
3773 | { | |
3774 | if (operand_types[j].bitfield.disp16) | |
3775 | { | |
3776 | addr_prefix_disp = j; | |
3777 | operand_types[j].bitfield.disp32 = 1; | |
3778 | operand_types[j].bitfield.disp16 = 0; | |
3779 | break; | |
3780 | } | |
3781 | } | |
539e75ad L |
3782 | break; |
3783 | case CODE_32BIT: | |
40fb9820 L |
3784 | for (j = 0; j < MAX_OPERANDS; j++) |
3785 | { | |
3786 | if (operand_types[j].bitfield.disp32) | |
3787 | { | |
3788 | addr_prefix_disp = j; | |
3789 | operand_types[j].bitfield.disp32 = 0; | |
3790 | operand_types[j].bitfield.disp16 = 1; | |
3791 | break; | |
3792 | } | |
3793 | } | |
539e75ad L |
3794 | break; |
3795 | case CODE_64BIT: | |
40fb9820 L |
3796 | for (j = 0; j < MAX_OPERANDS; j++) |
3797 | { | |
3798 | if (operand_types[j].bitfield.disp64) | |
3799 | { | |
3800 | addr_prefix_disp = j; | |
3801 | operand_types[j].bitfield.disp64 = 0; | |
3802 | operand_types[j].bitfield.disp32 = 1; | |
3803 | break; | |
3804 | } | |
3805 | } | |
539e75ad L |
3806 | break; |
3807 | } | |
539e75ad L |
3808 | } |
3809 | ||
45664ddb L |
3810 | /* We check register size only if size of operands can be |
3811 | encoded the canonical way. */ | |
3812 | check_register = t->opcode_modifier.w; | |
c6fb90c8 | 3813 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
3814 | switch (t->operands) |
3815 | { | |
3816 | case 1: | |
40fb9820 | 3817 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
3818 | continue; |
3819 | break; | |
3820 | case 2: | |
8b38ad71 L |
3821 | /* xchg %eax, %eax is a special case. It is an aliase for nop |
3822 | only in 32bit mode and we can use opcode 0x90. In 64bit | |
3823 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
3824 | zero-extend %eax to %rax. */ | |
3825 | if (flag_code == CODE_64BIT | |
3826 | && t->base_opcode == 0x90 | |
0dfbf9d7 L |
3827 | && operand_type_equal (&i.types [0], &acc32) |
3828 | && operand_type_equal (&i.types [1], &acc32)) | |
8b38ad71 | 3829 | continue; |
b6169b20 L |
3830 | if (i.swap_operand) |
3831 | { | |
3832 | /* If we swap operand in encoding, we either match | |
3833 | the next one or reverse direction of operands. */ | |
3834 | if (t->opcode_modifier.s) | |
3835 | continue; | |
3836 | else if (t->opcode_modifier.d) | |
3837 | goto check_reverse; | |
3838 | } | |
3839 | ||
29b0f896 | 3840 | case 3: |
fa99fab2 L |
3841 | /* If we swap operand in encoding, we match the next one. */ |
3842 | if (i.swap_operand && t->opcode_modifier.s) | |
3843 | continue; | |
f48ff2ae | 3844 | case 4: |
c0f3af97 | 3845 | case 5: |
c6fb90c8 | 3846 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
3847 | if (!operand_type_match (overlap0, i.types[0]) |
3848 | || !operand_type_match (overlap1, i.types[1]) | |
45664ddb L |
3849 | || (check_register |
3850 | && !operand_type_register_match (overlap0, i.types[0], | |
40fb9820 L |
3851 | operand_types[0], |
3852 | overlap1, i.types[1], | |
3853 | operand_types[1]))) | |
29b0f896 AM |
3854 | { |
3855 | /* Check if other direction is valid ... */ | |
40fb9820 | 3856 | if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) |
29b0f896 AM |
3857 | continue; |
3858 | ||
b6169b20 | 3859 | check_reverse: |
29b0f896 | 3860 | /* Try reversing direction of operands. */ |
c6fb90c8 L |
3861 | overlap0 = operand_type_and (i.types[0], operand_types[1]); |
3862 | overlap1 = operand_type_and (i.types[1], operand_types[0]); | |
40fb9820 L |
3863 | if (!operand_type_match (overlap0, i.types[0]) |
3864 | || !operand_type_match (overlap1, i.types[1]) | |
45664ddb L |
3865 | || (check_register |
3866 | && !operand_type_register_match (overlap0, | |
3867 | i.types[0], | |
3868 | operand_types[1], | |
3869 | overlap1, | |
3870 | i.types[1], | |
3871 | operand_types[0]))) | |
29b0f896 AM |
3872 | { |
3873 | /* Does not match either direction. */ | |
3874 | continue; | |
3875 | } | |
3876 | /* found_reverse_match holds which of D or FloatDR | |
3877 | we've found. */ | |
40fb9820 | 3878 | if (t->opcode_modifier.d) |
8a2ed489 | 3879 | found_reverse_match = Opcode_D; |
40fb9820 | 3880 | else if (t->opcode_modifier.floatd) |
8a2ed489 L |
3881 | found_reverse_match = Opcode_FloatD; |
3882 | else | |
3883 | found_reverse_match = 0; | |
40fb9820 | 3884 | if (t->opcode_modifier.floatr) |
8a2ed489 | 3885 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 3886 | } |
f48ff2ae | 3887 | else |
29b0f896 | 3888 | { |
f48ff2ae | 3889 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
3890 | switch (t->operands) |
3891 | { | |
c0f3af97 L |
3892 | case 5: |
3893 | overlap4 = operand_type_and (i.types[4], | |
3894 | operand_types[4]); | |
d1cbb4db | 3895 | case 4: |
c6fb90c8 L |
3896 | overlap3 = operand_type_and (i.types[3], |
3897 | operand_types[3]); | |
d1cbb4db | 3898 | case 3: |
c6fb90c8 L |
3899 | overlap2 = operand_type_and (i.types[2], |
3900 | operand_types[2]); | |
d1cbb4db L |
3901 | break; |
3902 | } | |
29b0f896 | 3903 | |
f48ff2ae L |
3904 | switch (t->operands) |
3905 | { | |
c0f3af97 L |
3906 | case 5: |
3907 | if (!operand_type_match (overlap4, i.types[4]) | |
3908 | || !operand_type_register_match (overlap3, | |
3909 | i.types[3], | |
3910 | operand_types[3], | |
3911 | overlap4, | |
3912 | i.types[4], | |
3913 | operand_types[4])) | |
3914 | continue; | |
f48ff2ae | 3915 | case 4: |
40fb9820 | 3916 | if (!operand_type_match (overlap3, i.types[3]) |
45664ddb L |
3917 | || (check_register |
3918 | && !operand_type_register_match (overlap2, | |
3919 | i.types[2], | |
3920 | operand_types[2], | |
3921 | overlap3, | |
3922 | i.types[3], | |
3923 | operand_types[3]))) | |
f48ff2ae L |
3924 | continue; |
3925 | case 3: | |
3926 | /* Here we make use of the fact that there are no | |
3927 | reverse match 3 operand instructions, and all 3 | |
3928 | operand instructions only need to be checked for | |
3929 | register consistency between operands 2 and 3. */ | |
40fb9820 | 3930 | if (!operand_type_match (overlap2, i.types[2]) |
45664ddb L |
3931 | || (check_register |
3932 | && !operand_type_register_match (overlap1, | |
3933 | i.types[1], | |
3934 | operand_types[1], | |
3935 | overlap2, | |
3936 | i.types[2], | |
3937 | operand_types[2]))) | |
f48ff2ae L |
3938 | continue; |
3939 | break; | |
3940 | } | |
29b0f896 | 3941 | } |
f48ff2ae | 3942 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
3943 | slip through to break. */ |
3944 | } | |
3629bb00 | 3945 | if (!found_cpu_match) |
29b0f896 AM |
3946 | { |
3947 | found_reverse_match = 0; | |
3948 | continue; | |
3949 | } | |
c0f3af97 | 3950 | |
29b0f896 AM |
3951 | /* We've found a match; break out of loop. */ |
3952 | break; | |
3953 | } | |
3954 | ||
3955 | if (t == current_templates->end) | |
3956 | { | |
3957 | /* We found no match. */ | |
95f283e8 L |
3958 | if (intel_syntax) |
3959 | as_bad (_("ambiguous operand size or operands invalid for `%s'"), | |
3960 | current_templates->start->name); | |
3961 | else | |
3962 | as_bad (_("suffix or operands invalid for `%s'"), | |
3963 | current_templates->start->name); | |
fa99fab2 | 3964 | return NULL; |
29b0f896 | 3965 | } |
252b5132 | 3966 | |
29b0f896 AM |
3967 | if (!quiet_warnings) |
3968 | { | |
3969 | if (!intel_syntax | |
40fb9820 L |
3970 | && (i.types[0].bitfield.jumpabsolute |
3971 | != operand_types[0].bitfield.jumpabsolute)) | |
29b0f896 AM |
3972 | { |
3973 | as_warn (_("indirect %s without `*'"), t->name); | |
3974 | } | |
3975 | ||
40fb9820 L |
3976 | if (t->opcode_modifier.isprefix |
3977 | && t->opcode_modifier.ignoresize) | |
29b0f896 AM |
3978 | { |
3979 | /* Warn them that a data or address size prefix doesn't | |
3980 | affect assembly of the next line of code. */ | |
3981 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
3982 | } | |
3983 | } | |
3984 | ||
3985 | /* Copy the template we found. */ | |
3986 | i.tm = *t; | |
539e75ad L |
3987 | |
3988 | if (addr_prefix_disp != -1) | |
3989 | i.tm.operand_types[addr_prefix_disp] | |
3990 | = operand_types[addr_prefix_disp]; | |
3991 | ||
29b0f896 AM |
3992 | if (found_reverse_match) |
3993 | { | |
3994 | /* If we found a reverse match we must alter the opcode | |
3995 | direction bit. found_reverse_match holds bits to change | |
3996 | (different for int & float insns). */ | |
3997 | ||
3998 | i.tm.base_opcode ^= found_reverse_match; | |
3999 | ||
539e75ad L |
4000 | i.tm.operand_types[0] = operand_types[1]; |
4001 | i.tm.operand_types[1] = operand_types[0]; | |
29b0f896 AM |
4002 | } |
4003 | ||
fa99fab2 | 4004 | return t; |
29b0f896 AM |
4005 | } |
4006 | ||
4007 | static int | |
e3bb37b5 | 4008 | check_string (void) |
29b0f896 | 4009 | { |
40fb9820 L |
4010 | int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1; |
4011 | if (i.tm.operand_types[mem_op].bitfield.esseg) | |
29b0f896 AM |
4012 | { |
4013 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
4014 | { | |
a87af027 | 4015 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 4016 | i.tm.name, |
a87af027 JB |
4017 | mem_op + 1, |
4018 | register_prefix); | |
29b0f896 AM |
4019 | return 0; |
4020 | } | |
4021 | /* There's only ever one segment override allowed per instruction. | |
4022 | This instruction possibly has a legal segment override on the | |
4023 | second operand, so copy the segment to where non-string | |
4024 | instructions store it, allowing common code. */ | |
4025 | i.seg[0] = i.seg[1]; | |
4026 | } | |
40fb9820 | 4027 | else if (i.tm.operand_types[mem_op + 1].bitfield.esseg) |
29b0f896 AM |
4028 | { |
4029 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
4030 | { | |
a87af027 | 4031 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 4032 | i.tm.name, |
a87af027 JB |
4033 | mem_op + 2, |
4034 | register_prefix); | |
29b0f896 AM |
4035 | return 0; |
4036 | } | |
4037 | } | |
4038 | return 1; | |
4039 | } | |
4040 | ||
4041 | static int | |
543613e9 | 4042 | process_suffix (void) |
29b0f896 AM |
4043 | { |
4044 | /* If matched instruction specifies an explicit instruction mnemonic | |
4045 | suffix, use it. */ | |
40fb9820 L |
4046 | if (i.tm.opcode_modifier.size16) |
4047 | i.suffix = WORD_MNEM_SUFFIX; | |
4048 | else if (i.tm.opcode_modifier.size32) | |
4049 | i.suffix = LONG_MNEM_SUFFIX; | |
4050 | else if (i.tm.opcode_modifier.size64) | |
4051 | i.suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 AM |
4052 | else if (i.reg_operands) |
4053 | { | |
4054 | /* If there's no instruction mnemonic suffix we try to invent one | |
4055 | based on register operands. */ | |
4056 | if (!i.suffix) | |
4057 | { | |
4058 | /* We take i.suffix from the last register operand specified, | |
4059 | Destination register type is more significant than source | |
381d071f L |
4060 | register type. crc32 in SSE4.2 prefers source register |
4061 | type. */ | |
4062 | if (i.tm.base_opcode == 0xf20f38f1) | |
4063 | { | |
40fb9820 L |
4064 | if (i.types[0].bitfield.reg16) |
4065 | i.suffix = WORD_MNEM_SUFFIX; | |
4066 | else if (i.types[0].bitfield.reg32) | |
4067 | i.suffix = LONG_MNEM_SUFFIX; | |
4068 | else if (i.types[0].bitfield.reg64) | |
4069 | i.suffix = QWORD_MNEM_SUFFIX; | |
381d071f | 4070 | } |
9344ff29 | 4071 | else if (i.tm.base_opcode == 0xf20f38f0) |
20592a94 | 4072 | { |
40fb9820 | 4073 | if (i.types[0].bitfield.reg8) |
20592a94 L |
4074 | i.suffix = BYTE_MNEM_SUFFIX; |
4075 | } | |
381d071f L |
4076 | |
4077 | if (!i.suffix) | |
4078 | { | |
4079 | int op; | |
4080 | ||
20592a94 L |
4081 | if (i.tm.base_opcode == 0xf20f38f1 |
4082 | || i.tm.base_opcode == 0xf20f38f0) | |
4083 | { | |
4084 | /* We have to know the operand size for crc32. */ | |
4085 | as_bad (_("ambiguous memory operand size for `%s`"), | |
4086 | i.tm.name); | |
4087 | return 0; | |
4088 | } | |
4089 | ||
381d071f | 4090 | for (op = i.operands; --op >= 0;) |
40fb9820 | 4091 | if (!i.tm.operand_types[op].bitfield.inoutportreg) |
381d071f | 4092 | { |
40fb9820 L |
4093 | if (i.types[op].bitfield.reg8) |
4094 | { | |
4095 | i.suffix = BYTE_MNEM_SUFFIX; | |
4096 | break; | |
4097 | } | |
4098 | else if (i.types[op].bitfield.reg16) | |
4099 | { | |
4100 | i.suffix = WORD_MNEM_SUFFIX; | |
4101 | break; | |
4102 | } | |
4103 | else if (i.types[op].bitfield.reg32) | |
4104 | { | |
4105 | i.suffix = LONG_MNEM_SUFFIX; | |
4106 | break; | |
4107 | } | |
4108 | else if (i.types[op].bitfield.reg64) | |
4109 | { | |
4110 | i.suffix = QWORD_MNEM_SUFFIX; | |
4111 | break; | |
4112 | } | |
381d071f L |
4113 | } |
4114 | } | |
29b0f896 AM |
4115 | } |
4116 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
4117 | { | |
4118 | if (!check_byte_reg ()) | |
4119 | return 0; | |
4120 | } | |
4121 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
4122 | { | |
4123 | if (!check_long_reg ()) | |
4124 | return 0; | |
4125 | } | |
4126 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
4127 | { | |
955e1e6a L |
4128 | if (intel_syntax |
4129 | && i.tm.opcode_modifier.ignoresize | |
4130 | && i.tm.opcode_modifier.no_qsuf) | |
4131 | i.suffix = 0; | |
4132 | else if (!check_qword_reg ()) | |
29b0f896 AM |
4133 | return 0; |
4134 | } | |
4135 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
4136 | { | |
4137 | if (!check_word_reg ()) | |
4138 | return 0; | |
4139 | } | |
c0f3af97 L |
4140 | else if (i.suffix == XMMWORD_MNEM_SUFFIX |
4141 | || i.suffix == YMMWORD_MNEM_SUFFIX) | |
582d5edd | 4142 | { |
c0f3af97 | 4143 | /* Skip if the instruction has x/y suffix. match_template |
582d5edd L |
4144 | should check if it is a valid suffix. */ |
4145 | } | |
40fb9820 | 4146 | else if (intel_syntax && i.tm.opcode_modifier.ignoresize) |
29b0f896 AM |
4147 | /* Do nothing if the instruction is going to ignore the prefix. */ |
4148 | ; | |
4149 | else | |
4150 | abort (); | |
4151 | } | |
40fb9820 | 4152 | else if (i.tm.opcode_modifier.defaultsize |
9306ca4a JB |
4153 | && !i.suffix |
4154 | /* exclude fldenv/frstor/fsave/fstenv */ | |
40fb9820 | 4155 | && i.tm.opcode_modifier.no_ssuf) |
29b0f896 AM |
4156 | { |
4157 | i.suffix = stackop_size; | |
4158 | } | |
9306ca4a JB |
4159 | else if (intel_syntax |
4160 | && !i.suffix | |
40fb9820 L |
4161 | && (i.tm.operand_types[0].bitfield.jumpabsolute |
4162 | || i.tm.opcode_modifier.jumpbyte | |
4163 | || i.tm.opcode_modifier.jumpintersegment | |
64e74474 AM |
4164 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
4165 | && i.tm.extension_opcode <= 3))) | |
9306ca4a JB |
4166 | { |
4167 | switch (flag_code) | |
4168 | { | |
4169 | case CODE_64BIT: | |
40fb9820 | 4170 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a JB |
4171 | { |
4172 | i.suffix = QWORD_MNEM_SUFFIX; | |
4173 | break; | |
4174 | } | |
4175 | case CODE_32BIT: | |
40fb9820 | 4176 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
4177 | i.suffix = LONG_MNEM_SUFFIX; |
4178 | break; | |
4179 | case CODE_16BIT: | |
40fb9820 | 4180 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
4181 | i.suffix = WORD_MNEM_SUFFIX; |
4182 | break; | |
4183 | } | |
4184 | } | |
252b5132 | 4185 | |
9306ca4a | 4186 | if (!i.suffix) |
29b0f896 | 4187 | { |
9306ca4a JB |
4188 | if (!intel_syntax) |
4189 | { | |
40fb9820 | 4190 | if (i.tm.opcode_modifier.w) |
9306ca4a | 4191 | { |
4eed87de AM |
4192 | as_bad (_("no instruction mnemonic suffix given and " |
4193 | "no register operands; can't size instruction")); | |
9306ca4a JB |
4194 | return 0; |
4195 | } | |
4196 | } | |
4197 | else | |
4198 | { | |
40fb9820 | 4199 | unsigned int suffixes; |
7ab9ffdd | 4200 | |
40fb9820 L |
4201 | suffixes = !i.tm.opcode_modifier.no_bsuf; |
4202 | if (!i.tm.opcode_modifier.no_wsuf) | |
4203 | suffixes |= 1 << 1; | |
4204 | if (!i.tm.opcode_modifier.no_lsuf) | |
4205 | suffixes |= 1 << 2; | |
fc4adea1 | 4206 | if (!i.tm.opcode_modifier.no_ldsuf) |
40fb9820 L |
4207 | suffixes |= 1 << 3; |
4208 | if (!i.tm.opcode_modifier.no_ssuf) | |
4209 | suffixes |= 1 << 4; | |
4210 | if (!i.tm.opcode_modifier.no_qsuf) | |
4211 | suffixes |= 1 << 5; | |
4212 | ||
4213 | /* There are more than suffix matches. */ | |
4214 | if (i.tm.opcode_modifier.w | |
9306ca4a | 4215 | || ((suffixes & (suffixes - 1)) |
40fb9820 L |
4216 | && !i.tm.opcode_modifier.defaultsize |
4217 | && !i.tm.opcode_modifier.ignoresize)) | |
9306ca4a JB |
4218 | { |
4219 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); | |
4220 | return 0; | |
4221 | } | |
4222 | } | |
29b0f896 | 4223 | } |
252b5132 | 4224 | |
9306ca4a JB |
4225 | /* Change the opcode based on the operand size given by i.suffix; |
4226 | We don't need to change things for byte insns. */ | |
4227 | ||
582d5edd L |
4228 | if (i.suffix |
4229 | && i.suffix != BYTE_MNEM_SUFFIX | |
c0f3af97 L |
4230 | && i.suffix != XMMWORD_MNEM_SUFFIX |
4231 | && i.suffix != YMMWORD_MNEM_SUFFIX) | |
29b0f896 AM |
4232 | { |
4233 | /* It's not a byte, select word/dword operation. */ | |
40fb9820 | 4234 | if (i.tm.opcode_modifier.w) |
29b0f896 | 4235 | { |
40fb9820 | 4236 | if (i.tm.opcode_modifier.shortform) |
29b0f896 AM |
4237 | i.tm.base_opcode |= 8; |
4238 | else | |
4239 | i.tm.base_opcode |= 1; | |
4240 | } | |
0f3f3d8b | 4241 | |
29b0f896 AM |
4242 | /* Now select between word & dword operations via the operand |
4243 | size prefix, except for instructions that will ignore this | |
4244 | prefix anyway. */ | |
ca61edf2 | 4245 | if (i.tm.opcode_modifier.addrprefixop0) |
cb712a9e | 4246 | { |
ca61edf2 L |
4247 | /* The address size override prefix changes the size of the |
4248 | first operand. */ | |
40fb9820 L |
4249 | if ((flag_code == CODE_32BIT |
4250 | && i.op->regs[0].reg_type.bitfield.reg16) | |
4251 | || (flag_code != CODE_32BIT | |
4252 | && i.op->regs[0].reg_type.bitfield.reg32)) | |
cb712a9e L |
4253 | if (!add_prefix (ADDR_PREFIX_OPCODE)) |
4254 | return 0; | |
4255 | } | |
4256 | else if (i.suffix != QWORD_MNEM_SUFFIX | |
4257 | && i.suffix != LONG_DOUBLE_MNEM_SUFFIX | |
40fb9820 L |
4258 | && !i.tm.opcode_modifier.ignoresize |
4259 | && !i.tm.opcode_modifier.floatmf | |
cb712a9e L |
4260 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) |
4261 | || (flag_code == CODE_64BIT | |
40fb9820 | 4262 | && i.tm.opcode_modifier.jumpbyte))) |
24eab124 AM |
4263 | { |
4264 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 4265 | |
40fb9820 | 4266 | if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */ |
29b0f896 | 4267 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 4268 | |
29b0f896 AM |
4269 | if (!add_prefix (prefix)) |
4270 | return 0; | |
24eab124 | 4271 | } |
252b5132 | 4272 | |
29b0f896 AM |
4273 | /* Set mode64 for an operand. */ |
4274 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 4275 | && flag_code == CODE_64BIT |
40fb9820 | 4276 | && !i.tm.opcode_modifier.norex64) |
46e883c5 L |
4277 | { |
4278 | /* Special case for xchg %rax,%rax. It is NOP and doesn't | |
d9a5e5e5 L |
4279 | need rex64. cmpxchg8b is also a special case. */ |
4280 | if (! (i.operands == 2 | |
4281 | && i.tm.base_opcode == 0x90 | |
4282 | && i.tm.extension_opcode == None | |
0dfbf9d7 L |
4283 | && operand_type_equal (&i.types [0], &acc64) |
4284 | && operand_type_equal (&i.types [1], &acc64)) | |
d9a5e5e5 L |
4285 | && ! (i.operands == 1 |
4286 | && i.tm.base_opcode == 0xfc7 | |
4287 | && i.tm.extension_opcode == 1 | |
40fb9820 L |
4288 | && !operand_type_check (i.types [0], reg) |
4289 | && operand_type_check (i.types [0], anymem))) | |
f6bee062 | 4290 | i.rex |= REX_W; |
46e883c5 | 4291 | } |
3e73aa7c | 4292 | |
29b0f896 AM |
4293 | /* Size floating point instruction. */ |
4294 | if (i.suffix == LONG_MNEM_SUFFIX) | |
40fb9820 | 4295 | if (i.tm.opcode_modifier.floatmf) |
543613e9 | 4296 | i.tm.base_opcode ^= 4; |
29b0f896 | 4297 | } |
7ecd2f8b | 4298 | |
29b0f896 AM |
4299 | return 1; |
4300 | } | |
3e73aa7c | 4301 | |
29b0f896 | 4302 | static int |
543613e9 | 4303 | check_byte_reg (void) |
29b0f896 AM |
4304 | { |
4305 | int op; | |
543613e9 | 4306 | |
29b0f896 AM |
4307 | for (op = i.operands; --op >= 0;) |
4308 | { | |
4309 | /* If this is an eight bit register, it's OK. If it's the 16 or | |
4310 | 32 bit version of an eight bit register, we will just use the | |
4311 | low portion, and that's OK too. */ | |
40fb9820 | 4312 | if (i.types[op].bitfield.reg8) |
29b0f896 AM |
4313 | continue; |
4314 | ||
ca61edf2 L |
4315 | /* Don't generate this warning if not needed. */ |
4316 | if (intel_syntax && i.tm.opcode_modifier.byteokintel) | |
29b0f896 AM |
4317 | continue; |
4318 | ||
9344ff29 L |
4319 | /* crc32 doesn't generate this warning. */ |
4320 | if (i.tm.base_opcode == 0xf20f38f0) | |
4321 | continue; | |
4322 | ||
40fb9820 L |
4323 | if ((i.types[op].bitfield.reg16 |
4324 | || i.types[op].bitfield.reg32 | |
4325 | || i.types[op].bitfield.reg64) | |
4326 | && i.op[op].regs->reg_num < 4) | |
29b0f896 AM |
4327 | { |
4328 | /* Prohibit these changes in the 64bit mode, since the | |
4329 | lowering is more complicated. */ | |
4330 | if (flag_code == CODE_64BIT | |
40fb9820 | 4331 | && !i.tm.operand_types[op].bitfield.inoutportreg) |
29b0f896 | 4332 | { |
2ca3ace5 L |
4333 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), |
4334 | register_prefix, i.op[op].regs->reg_name, | |
29b0f896 AM |
4335 | i.suffix); |
4336 | return 0; | |
4337 | } | |
4338 | #if REGISTER_WARNINGS | |
4339 | if (!quiet_warnings | |
40fb9820 | 4340 | && !i.tm.operand_types[op].bitfield.inoutportreg) |
a540244d L |
4341 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
4342 | register_prefix, | |
40fb9820 | 4343 | (i.op[op].regs + (i.types[op].bitfield.reg16 |
29b0f896 AM |
4344 | ? REGNAM_AL - REGNAM_AX |
4345 | : REGNAM_AL - REGNAM_EAX))->reg_name, | |
a540244d | 4346 | register_prefix, |
29b0f896 AM |
4347 | i.op[op].regs->reg_name, |
4348 | i.suffix); | |
4349 | #endif | |
4350 | continue; | |
4351 | } | |
4352 | /* Any other register is bad. */ | |
40fb9820 L |
4353 | if (i.types[op].bitfield.reg16 |
4354 | || i.types[op].bitfield.reg32 | |
4355 | || i.types[op].bitfield.reg64 | |
4356 | || i.types[op].bitfield.regmmx | |
4357 | || i.types[op].bitfield.regxmm | |
c0f3af97 | 4358 | || i.types[op].bitfield.regymm |
40fb9820 L |
4359 | || i.types[op].bitfield.sreg2 |
4360 | || i.types[op].bitfield.sreg3 | |
4361 | || i.types[op].bitfield.control | |
4362 | || i.types[op].bitfield.debug | |
4363 | || i.types[op].bitfield.test | |
4364 | || i.types[op].bitfield.floatreg | |
4365 | || i.types[op].bitfield.floatacc) | |
29b0f896 | 4366 | { |
a540244d L |
4367 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
4368 | register_prefix, | |
29b0f896 AM |
4369 | i.op[op].regs->reg_name, |
4370 | i.tm.name, | |
4371 | i.suffix); | |
4372 | return 0; | |
4373 | } | |
4374 | } | |
4375 | return 1; | |
4376 | } | |
4377 | ||
4378 | static int | |
e3bb37b5 | 4379 | check_long_reg (void) |
29b0f896 AM |
4380 | { |
4381 | int op; | |
4382 | ||
4383 | for (op = i.operands; --op >= 0;) | |
4384 | /* Reject eight bit registers, except where the template requires | |
4385 | them. (eg. movzb) */ | |
40fb9820 L |
4386 | if (i.types[op].bitfield.reg8 |
4387 | && (i.tm.operand_types[op].bitfield.reg16 | |
4388 | || i.tm.operand_types[op].bitfield.reg32 | |
4389 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 4390 | { |
a540244d L |
4391 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
4392 | register_prefix, | |
29b0f896 AM |
4393 | i.op[op].regs->reg_name, |
4394 | i.tm.name, | |
4395 | i.suffix); | |
4396 | return 0; | |
4397 | } | |
4398 | /* Warn if the e prefix on a general reg is missing. */ | |
4399 | else if ((!quiet_warnings || flag_code == CODE_64BIT) | |
40fb9820 L |
4400 | && i.types[op].bitfield.reg16 |
4401 | && (i.tm.operand_types[op].bitfield.reg32 | |
4402 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 AM |
4403 | { |
4404 | /* Prohibit these changes in the 64bit mode, since the | |
4405 | lowering is more complicated. */ | |
4406 | if (flag_code == CODE_64BIT) | |
252b5132 | 4407 | { |
2ca3ace5 L |
4408 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), |
4409 | register_prefix, i.op[op].regs->reg_name, | |
29b0f896 AM |
4410 | i.suffix); |
4411 | return 0; | |
252b5132 | 4412 | } |
29b0f896 AM |
4413 | #if REGISTER_WARNINGS |
4414 | else | |
a540244d L |
4415 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
4416 | register_prefix, | |
29b0f896 | 4417 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, |
a540244d | 4418 | register_prefix, |
29b0f896 AM |
4419 | i.op[op].regs->reg_name, |
4420 | i.suffix); | |
4421 | #endif | |
252b5132 | 4422 | } |
29b0f896 | 4423 | /* Warn if the r prefix on a general reg is missing. */ |
40fb9820 L |
4424 | else if (i.types[op].bitfield.reg64 |
4425 | && (i.tm.operand_types[op].bitfield.reg32 | |
4426 | || i.tm.operand_types[op].bitfield.acc)) | |
252b5132 | 4427 | { |
34828aad | 4428 | if (intel_syntax |
ca61edf2 | 4429 | && i.tm.opcode_modifier.toqword |
40fb9820 | 4430 | && !i.types[0].bitfield.regxmm) |
34828aad | 4431 | { |
ca61edf2 | 4432 | /* Convert to QWORD. We want REX byte. */ |
34828aad L |
4433 | i.suffix = QWORD_MNEM_SUFFIX; |
4434 | } | |
4435 | else | |
4436 | { | |
4437 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), | |
4438 | register_prefix, i.op[op].regs->reg_name, | |
4439 | i.suffix); | |
4440 | return 0; | |
4441 | } | |
29b0f896 AM |
4442 | } |
4443 | return 1; | |
4444 | } | |
252b5132 | 4445 | |
29b0f896 | 4446 | static int |
e3bb37b5 | 4447 | check_qword_reg (void) |
29b0f896 AM |
4448 | { |
4449 | int op; | |
252b5132 | 4450 | |
29b0f896 AM |
4451 | for (op = i.operands; --op >= 0; ) |
4452 | /* Reject eight bit registers, except where the template requires | |
4453 | them. (eg. movzb) */ | |
40fb9820 L |
4454 | if (i.types[op].bitfield.reg8 |
4455 | && (i.tm.operand_types[op].bitfield.reg16 | |
4456 | || i.tm.operand_types[op].bitfield.reg32 | |
4457 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 4458 | { |
a540244d L |
4459 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
4460 | register_prefix, | |
29b0f896 AM |
4461 | i.op[op].regs->reg_name, |
4462 | i.tm.name, | |
4463 | i.suffix); | |
4464 | return 0; | |
4465 | } | |
4466 | /* Warn if the e prefix on a general reg is missing. */ | |
40fb9820 L |
4467 | else if ((i.types[op].bitfield.reg16 |
4468 | || i.types[op].bitfield.reg32) | |
4469 | && (i.tm.operand_types[op].bitfield.reg32 | |
4470 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 AM |
4471 | { |
4472 | /* Prohibit these changes in the 64bit mode, since the | |
4473 | lowering is more complicated. */ | |
34828aad | 4474 | if (intel_syntax |
ca61edf2 | 4475 | && i.tm.opcode_modifier.todword |
40fb9820 | 4476 | && !i.types[0].bitfield.regxmm) |
34828aad | 4477 | { |
ca61edf2 | 4478 | /* Convert to DWORD. We don't want REX byte. */ |
34828aad L |
4479 | i.suffix = LONG_MNEM_SUFFIX; |
4480 | } | |
4481 | else | |
4482 | { | |
4483 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), | |
4484 | register_prefix, i.op[op].regs->reg_name, | |
4485 | i.suffix); | |
4486 | return 0; | |
4487 | } | |
252b5132 | 4488 | } |
29b0f896 AM |
4489 | return 1; |
4490 | } | |
252b5132 | 4491 | |
29b0f896 | 4492 | static int |
e3bb37b5 | 4493 | check_word_reg (void) |
29b0f896 AM |
4494 | { |
4495 | int op; | |
4496 | for (op = i.operands; --op >= 0;) | |
4497 | /* Reject eight bit registers, except where the template requires | |
4498 | them. (eg. movzb) */ | |
40fb9820 L |
4499 | if (i.types[op].bitfield.reg8 |
4500 | && (i.tm.operand_types[op].bitfield.reg16 | |
4501 | || i.tm.operand_types[op].bitfield.reg32 | |
4502 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 4503 | { |
a540244d L |
4504 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
4505 | register_prefix, | |
29b0f896 AM |
4506 | i.op[op].regs->reg_name, |
4507 | i.tm.name, | |
4508 | i.suffix); | |
4509 | return 0; | |
4510 | } | |
4511 | /* Warn if the e prefix on a general reg is present. */ | |
4512 | else if ((!quiet_warnings || flag_code == CODE_64BIT) | |
40fb9820 L |
4513 | && i.types[op].bitfield.reg32 |
4514 | && (i.tm.operand_types[op].bitfield.reg16 | |
4515 | || i.tm.operand_types[op].bitfield.acc)) | |
252b5132 | 4516 | { |
29b0f896 AM |
4517 | /* Prohibit these changes in the 64bit mode, since the |
4518 | lowering is more complicated. */ | |
4519 | if (flag_code == CODE_64BIT) | |
252b5132 | 4520 | { |
2ca3ace5 L |
4521 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), |
4522 | register_prefix, i.op[op].regs->reg_name, | |
29b0f896 AM |
4523 | i.suffix); |
4524 | return 0; | |
252b5132 | 4525 | } |
29b0f896 AM |
4526 | else |
4527 | #if REGISTER_WARNINGS | |
a540244d L |
4528 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
4529 | register_prefix, | |
29b0f896 | 4530 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, |
a540244d | 4531 | register_prefix, |
29b0f896 AM |
4532 | i.op[op].regs->reg_name, |
4533 | i.suffix); | |
4534 | #endif | |
4535 | } | |
4536 | return 1; | |
4537 | } | |
252b5132 | 4538 | |
29b0f896 | 4539 | static int |
40fb9820 | 4540 | update_imm (unsigned int j) |
29b0f896 | 4541 | { |
bc0844ae | 4542 | i386_operand_type overlap = i.types[j]; |
40fb9820 L |
4543 | if ((overlap.bitfield.imm8 |
4544 | || overlap.bitfield.imm8s | |
4545 | || overlap.bitfield.imm16 | |
4546 | || overlap.bitfield.imm32 | |
4547 | || overlap.bitfield.imm32s | |
4548 | || overlap.bitfield.imm64) | |
0dfbf9d7 L |
4549 | && !operand_type_equal (&overlap, &imm8) |
4550 | && !operand_type_equal (&overlap, &imm8s) | |
4551 | && !operand_type_equal (&overlap, &imm16) | |
4552 | && !operand_type_equal (&overlap, &imm32) | |
4553 | && !operand_type_equal (&overlap, &imm32s) | |
4554 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 AM |
4555 | { |
4556 | if (i.suffix) | |
4557 | { | |
40fb9820 L |
4558 | i386_operand_type temp; |
4559 | ||
0dfbf9d7 | 4560 | operand_type_set (&temp, 0); |
7ab9ffdd | 4561 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
4562 | { |
4563 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
4564 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
4565 | } | |
4566 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
4567 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
4568 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
4569 | { | |
4570 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
4571 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
4572 | } | |
4573 | else | |
4574 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
4575 | overlap = temp; | |
29b0f896 | 4576 | } |
0dfbf9d7 L |
4577 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
4578 | || operand_type_equal (&overlap, &imm16_32) | |
4579 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 4580 | { |
40fb9820 | 4581 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 4582 | overlap = imm16; |
40fb9820 | 4583 | else |
65da13b5 | 4584 | overlap = imm32s; |
29b0f896 | 4585 | } |
0dfbf9d7 L |
4586 | if (!operand_type_equal (&overlap, &imm8) |
4587 | && !operand_type_equal (&overlap, &imm8s) | |
4588 | && !operand_type_equal (&overlap, &imm16) | |
4589 | && !operand_type_equal (&overlap, &imm32) | |
4590 | && !operand_type_equal (&overlap, &imm32s) | |
4591 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 | 4592 | { |
4eed87de AM |
4593 | as_bad (_("no instruction mnemonic suffix given; " |
4594 | "can't determine immediate size")); | |
29b0f896 AM |
4595 | return 0; |
4596 | } | |
4597 | } | |
40fb9820 | 4598 | i.types[j] = overlap; |
29b0f896 | 4599 | |
40fb9820 L |
4600 | return 1; |
4601 | } | |
4602 | ||
4603 | static int | |
4604 | finalize_imm (void) | |
4605 | { | |
bc0844ae | 4606 | unsigned int j, n; |
29b0f896 | 4607 | |
bc0844ae L |
4608 | /* Update the first 2 immediate operands. */ |
4609 | n = i.operands > 2 ? 2 : i.operands; | |
4610 | if (n) | |
4611 | { | |
4612 | for (j = 0; j < n; j++) | |
4613 | if (update_imm (j) == 0) | |
4614 | return 0; | |
40fb9820 | 4615 | |
bc0844ae L |
4616 | /* The 3rd operand can't be immediate operand. */ |
4617 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
4618 | } | |
29b0f896 AM |
4619 | |
4620 | return 1; | |
4621 | } | |
4622 | ||
c0f3af97 L |
4623 | static int |
4624 | bad_implicit_operand (int xmm) | |
4625 | { | |
4626 | const char *reg = xmm ? "xmm0" : "ymm0"; | |
4627 | if (intel_syntax) | |
4628 | as_bad (_("the last operand of `%s' must be `%s%s'"), | |
4629 | i.tm.name, register_prefix, reg); | |
4630 | else | |
4631 | as_bad (_("the first operand of `%s' must be `%s%s'"), | |
4632 | i.tm.name, register_prefix, reg); | |
4633 | return 0; | |
4634 | } | |
4635 | ||
29b0f896 | 4636 | static int |
e3bb37b5 | 4637 | process_operands (void) |
29b0f896 AM |
4638 | { |
4639 | /* Default segment register this instruction will use for memory | |
4640 | accesses. 0 means unknown. This is only for optimizing out | |
4641 | unnecessary segment overrides. */ | |
4642 | const seg_entry *default_seg = 0; | |
4643 | ||
c0f3af97 L |
4644 | if (i.tm.opcode_modifier.sse2avx |
4645 | && (i.tm.opcode_modifier.vexnds | |
4646 | || i.tm.opcode_modifier.vexndd)) | |
29b0f896 | 4647 | { |
c0f3af97 L |
4648 | unsigned int dup = i.operands; |
4649 | unsigned int dest = dup - 1; | |
9fcfb3d7 L |
4650 | unsigned int j; |
4651 | ||
c0f3af97 | 4652 | /* The destination must be an xmm register. */ |
9c2799c2 | 4653 | gas_assert (i.reg_operands |
7ab9ffdd L |
4654 | && MAX_OPERANDS > dup |
4655 | && operand_type_equal (&i.types[dest], ®xmm)); | |
c0f3af97 L |
4656 | |
4657 | if (i.tm.opcode_modifier.firstxmm0) | |
e2ec9d29 | 4658 | { |
c0f3af97 | 4659 | /* The first operand is implicit and must be xmm0. */ |
9c2799c2 | 4660 | gas_assert (operand_type_equal (&i.types[0], ®xmm)); |
c0f3af97 L |
4661 | if (i.op[0].regs->reg_num != 0) |
4662 | return bad_implicit_operand (1); | |
4663 | ||
4664 | if (i.tm.opcode_modifier.vex3sources) | |
4665 | { | |
4666 | /* Keep xmm0 for instructions with VEX prefix and 3 | |
4667 | sources. */ | |
4668 | goto duplicate; | |
4669 | } | |
e2ec9d29 | 4670 | else |
c0f3af97 L |
4671 | { |
4672 | /* We remove the first xmm0 and keep the number of | |
4673 | operands unchanged, which in fact duplicates the | |
4674 | destination. */ | |
4675 | for (j = 1; j < i.operands; j++) | |
4676 | { | |
4677 | i.op[j - 1] = i.op[j]; | |
4678 | i.types[j - 1] = i.types[j]; | |
4679 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; | |
4680 | } | |
4681 | } | |
4682 | } | |
4683 | else if (i.tm.opcode_modifier.implicit1stxmm0) | |
7ab9ffdd | 4684 | { |
9c2799c2 | 4685 | gas_assert ((MAX_OPERANDS - 1) > dup |
7ab9ffdd | 4686 | && i.tm.opcode_modifier.vex3sources); |
c0f3af97 L |
4687 | |
4688 | /* Add the implicit xmm0 for instructions with VEX prefix | |
4689 | and 3 sources. */ | |
4690 | for (j = i.operands; j > 0; j--) | |
4691 | { | |
4692 | i.op[j] = i.op[j - 1]; | |
4693 | i.types[j] = i.types[j - 1]; | |
4694 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
4695 | } | |
4696 | i.op[0].regs | |
4697 | = (const reg_entry *) hash_find (reg_hash, "xmm0"); | |
7ab9ffdd | 4698 | i.types[0] = regxmm; |
c0f3af97 L |
4699 | i.tm.operand_types[0] = regxmm; |
4700 | ||
4701 | i.operands += 2; | |
4702 | i.reg_operands += 2; | |
4703 | i.tm.operands += 2; | |
4704 | ||
4705 | dup++; | |
4706 | dest++; | |
4707 | i.op[dup] = i.op[dest]; | |
4708 | i.types[dup] = i.types[dest]; | |
4709 | i.tm.operand_types[dup] = i.tm.operand_types[dest]; | |
e2ec9d29 | 4710 | } |
c0f3af97 L |
4711 | else |
4712 | { | |
4713 | duplicate: | |
4714 | i.operands++; | |
4715 | i.reg_operands++; | |
4716 | i.tm.operands++; | |
4717 | ||
4718 | i.op[dup] = i.op[dest]; | |
4719 | i.types[dup] = i.types[dest]; | |
4720 | i.tm.operand_types[dup] = i.tm.operand_types[dest]; | |
4721 | } | |
4722 | ||
4723 | if (i.tm.opcode_modifier.immext) | |
4724 | process_immext (); | |
4725 | } | |
4726 | else if (i.tm.opcode_modifier.firstxmm0) | |
4727 | { | |
4728 | unsigned int j; | |
4729 | ||
4730 | /* The first operand is implicit and must be xmm0/ymm0. */ | |
9c2799c2 | 4731 | gas_assert (i.reg_operands |
7ab9ffdd L |
4732 | && (operand_type_equal (&i.types[0], ®xmm) |
4733 | || operand_type_equal (&i.types[0], ®ymm))); | |
c0f3af97 L |
4734 | if (i.op[0].regs->reg_num != 0) |
4735 | return bad_implicit_operand (i.types[0].bitfield.regxmm); | |
9fcfb3d7 L |
4736 | |
4737 | for (j = 1; j < i.operands; j++) | |
4738 | { | |
4739 | i.op[j - 1] = i.op[j]; | |
4740 | i.types[j - 1] = i.types[j]; | |
4741 | ||
4742 | /* We need to adjust fields in i.tm since they are used by | |
4743 | build_modrm_byte. */ | |
4744 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
4745 | } | |
4746 | ||
e2ec9d29 L |
4747 | i.operands--; |
4748 | i.reg_operands--; | |
e2ec9d29 L |
4749 | i.tm.operands--; |
4750 | } | |
4751 | else if (i.tm.opcode_modifier.regkludge) | |
4752 | { | |
4753 | /* The imul $imm, %reg instruction is converted into | |
4754 | imul $imm, %reg, %reg, and the clr %reg instruction | |
4755 | is converted into xor %reg, %reg. */ | |
4756 | ||
4757 | unsigned int first_reg_op; | |
4758 | ||
4759 | if (operand_type_check (i.types[0], reg)) | |
4760 | first_reg_op = 0; | |
4761 | else | |
4762 | first_reg_op = 1; | |
4763 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 4764 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 4765 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
4766 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
4767 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
4768 | i.operands++; | |
4769 | i.reg_operands++; | |
29b0f896 AM |
4770 | } |
4771 | ||
40fb9820 | 4772 | if (i.tm.opcode_modifier.shortform) |
29b0f896 | 4773 | { |
40fb9820 L |
4774 | if (i.types[0].bitfield.sreg2 |
4775 | || i.types[0].bitfield.sreg3) | |
29b0f896 | 4776 | { |
4eed87de AM |
4777 | if (i.tm.base_opcode == POP_SEG_SHORT |
4778 | && i.op[0].regs->reg_num == 1) | |
29b0f896 | 4779 | { |
a87af027 | 4780 | as_bad (_("you can't `pop %scs'"), register_prefix); |
4eed87de | 4781 | return 0; |
29b0f896 | 4782 | } |
4eed87de AM |
4783 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
4784 | if ((i.op[0].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 4785 | i.rex |= REX_B; |
4eed87de AM |
4786 | } |
4787 | else | |
4788 | { | |
7ab9ffdd | 4789 | /* The register or float register operand is in operand |
85f10a01 | 4790 | 0 or 1. */ |
40fb9820 | 4791 | unsigned int op; |
7ab9ffdd L |
4792 | |
4793 | if (i.types[0].bitfield.floatreg | |
4794 | || operand_type_check (i.types[0], reg)) | |
4795 | op = 0; | |
4796 | else | |
4797 | op = 1; | |
4eed87de AM |
4798 | /* Register goes in low 3 bits of opcode. */ |
4799 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
4800 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 4801 | i.rex |= REX_B; |
40fb9820 | 4802 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 | 4803 | { |
4eed87de AM |
4804 | /* Warn about some common errors, but press on regardless. |
4805 | The first case can be generated by gcc (<= 2.8.1). */ | |
4806 | if (i.operands == 2) | |
4807 | { | |
4808 | /* Reversed arguments on faddp, fsubp, etc. */ | |
a540244d | 4809 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, |
d8a1b51e JB |
4810 | register_prefix, i.op[!intel_syntax].regs->reg_name, |
4811 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
4eed87de AM |
4812 | } |
4813 | else | |
4814 | { | |
4815 | /* Extraneous `l' suffix on fp insn. */ | |
a540244d L |
4816 | as_warn (_("translating to `%s %s%s'"), i.tm.name, |
4817 | register_prefix, i.op[0].regs->reg_name); | |
4eed87de | 4818 | } |
29b0f896 AM |
4819 | } |
4820 | } | |
4821 | } | |
40fb9820 | 4822 | else if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
4823 | { |
4824 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
4825 | must be put into the modrm byte). Now, we make the modrm and |
4826 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
4827 | |
4828 | default_seg = build_modrm_byte (); | |
4829 | } | |
8a2ed489 | 4830 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
29b0f896 AM |
4831 | { |
4832 | default_seg = &ds; | |
4833 | } | |
40fb9820 | 4834 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
4835 | { |
4836 | /* For the string instructions that allow a segment override | |
4837 | on one of their operands, the default segment is ds. */ | |
4838 | default_seg = &ds; | |
4839 | } | |
4840 | ||
75178d9d L |
4841 | if (i.tm.base_opcode == 0x8d /* lea */ |
4842 | && i.seg[0] | |
4843 | && !quiet_warnings) | |
30123838 | 4844 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); |
52271982 AM |
4845 | |
4846 | /* If a segment was explicitly specified, and the specified segment | |
4847 | is not the default, use an opcode prefix to select it. If we | |
4848 | never figured out what the default segment is, then default_seg | |
4849 | will be zero at this point, and the specified segment prefix will | |
4850 | always be used. */ | |
29b0f896 AM |
4851 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
4852 | { | |
4853 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
4854 | return 0; | |
4855 | } | |
4856 | return 1; | |
4857 | } | |
4858 | ||
4859 | static const seg_entry * | |
e3bb37b5 | 4860 | build_modrm_byte (void) |
29b0f896 AM |
4861 | { |
4862 | const seg_entry *default_seg = 0; | |
c0f3af97 | 4863 | unsigned int source, dest; |
7ab9ffdd | 4864 | int vex_3_sources; |
c0f3af97 L |
4865 | |
4866 | /* The first operand of instructions with VEX prefix and 3 sources | |
4867 | must be VEX_Imm4. */ | |
4868 | vex_3_sources = i.tm.opcode_modifier.vex3sources; | |
4869 | if (vex_3_sources) | |
4870 | { | |
4871 | unsigned int nds, reg; | |
4872 | ||
922d8de8 DR |
4873 | if (i.tm.opcode_modifier.veximmext |
4874 | && i.tm.opcode_modifier.immext) | |
4875 | { | |
4876 | dest = i.operands - 2; | |
4877 | gas_assert (dest == 3); | |
4878 | } | |
4879 | else | |
0bfee649 | 4880 | dest = i.operands - 1; |
c0f3af97 | 4881 | nds = dest - 1; |
922d8de8 DR |
4882 | |
4883 | /* This instruction must have 4 register operands | |
4884 | or 3 register operands plus 1 memory operand. | |
4885 | It must have VexNDS and VexImmExt. */ | |
4886 | gas_assert ((i.reg_operands == 4 | |
7ab9ffdd L |
4887 | || (i.reg_operands == 3 && i.mem_operands == 1)) |
4888 | && i.tm.opcode_modifier.vexnds | |
4889 | && i.tm.opcode_modifier.veximmext | |
922d8de8 DR |
4890 | && (operand_type_equal (&i.tm.operand_types[dest], ®xmm) |
4891 | || operand_type_equal (&i.tm.operand_types[dest], ®ymm))); | |
c0f3af97 | 4892 | |
0bfee649 L |
4893 | /* Generate an 8bit immediate operand to encode the register |
4894 | operand. */ | |
4895 | expressionS *exp = &im_expressions[i.imm_operands++]; | |
4896 | i.op[i.operands].imms = exp; | |
4897 | i.types[i.operands] = imm8; | |
4898 | i.operands++; | |
922d8de8 DR |
4899 | /* If VexW1 is set, the first operand is the source and |
4900 | the second operand is encoded in the immediate operand. */ | |
4901 | if (i.tm.opcode_modifier.vexw1) | |
4902 | { | |
4903 | source = 0; | |
4904 | reg = 1; | |
4905 | } | |
4906 | else | |
4907 | { | |
4908 | source = 1; | |
4909 | reg = 0; | |
4910 | } | |
4911 | /* FMA4 swaps REG and NDS. */ | |
4912 | if (i.tm.cpu_flags.bitfield.cpufma4) | |
4913 | { | |
4914 | unsigned int tmp; | |
4915 | tmp = reg; | |
4916 | reg = nds; | |
4917 | nds = tmp; | |
4918 | } | |
4919 | gas_assert ((operand_type_equal (&i.tm.operand_types[reg], ®xmm) | |
4920 | || operand_type_equal (&i.tm.operand_types[reg], | |
4921 | ®ymm)) | |
4922 | && (operand_type_equal (&i.tm.operand_types[nds], ®xmm) | |
4923 | || operand_type_equal (&i.tm.operand_types[nds], | |
4924 | ®ymm))); | |
0bfee649 L |
4925 | exp->X_op = O_constant; |
4926 | exp->X_add_number | |
922d8de8 DR |
4927 | = ((i.op[reg].regs->reg_num |
4928 | + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4); | |
dae39acc | 4929 | i.vex.register_specifier = i.op[nds].regs; |
c0f3af97 L |
4930 | } |
4931 | else | |
4932 | source = dest = 0; | |
29b0f896 AM |
4933 | |
4934 | /* i.reg_operands MUST be the number of real register operands; | |
c0f3af97 L |
4935 | implicit registers do not count. If there are 3 register |
4936 | operands, it must be a instruction with VexNDS. For a | |
4937 | instruction with VexNDD, the destination register is encoded | |
4938 | in VEX prefix. If there are 4 register operands, it must be | |
4939 | a instruction with VEX prefix and 3 sources. */ | |
7ab9ffdd L |
4940 | if (i.mem_operands == 0 |
4941 | && ((i.reg_operands == 2 | |
4942 | && !i.tm.opcode_modifier.vexndd) | |
4943 | || (i.reg_operands == 3 | |
4944 | && i.tm.opcode_modifier.vexnds) | |
4945 | || (i.reg_operands == 4 && vex_3_sources))) | |
29b0f896 | 4946 | { |
cab737b9 L |
4947 | switch (i.operands) |
4948 | { | |
4949 | case 2: | |
4950 | source = 0; | |
4951 | break; | |
4952 | case 3: | |
c81128dc L |
4953 | /* When there are 3 operands, one of them may be immediate, |
4954 | which may be the first or the last operand. Otherwise, | |
c0f3af97 L |
4955 | the first operand must be shift count register (cl) or it |
4956 | is an instruction with VexNDS. */ | |
9c2799c2 | 4957 | gas_assert (i.imm_operands == 1 |
7ab9ffdd L |
4958 | || (i.imm_operands == 0 |
4959 | && (i.tm.opcode_modifier.vexnds | |
4960 | || i.types[0].bitfield.shiftcount))); | |
40fb9820 L |
4961 | if (operand_type_check (i.types[0], imm) |
4962 | || i.types[0].bitfield.shiftcount) | |
4963 | source = 1; | |
4964 | else | |
4965 | source = 0; | |
cab737b9 L |
4966 | break; |
4967 | case 4: | |
368d64cc L |
4968 | /* When there are 4 operands, the first two must be 8bit |
4969 | immediate operands. The source operand will be the 3rd | |
c0f3af97 L |
4970 | one. |
4971 | ||
4972 | For instructions with VexNDS, if the first operand | |
4973 | an imm8, the source operand is the 2nd one. If the last | |
4974 | operand is imm8, the source operand is the first one. */ | |
9c2799c2 | 4975 | gas_assert ((i.imm_operands == 2 |
7ab9ffdd L |
4976 | && i.types[0].bitfield.imm8 |
4977 | && i.types[1].bitfield.imm8) | |
4978 | || (i.tm.opcode_modifier.vexnds | |
4979 | && i.imm_operands == 1 | |
4980 | && (i.types[0].bitfield.imm8 | |
4981 | || i.types[i.operands - 1].bitfield.imm8))); | |
c0f3af97 L |
4982 | if (i.tm.opcode_modifier.vexnds) |
4983 | { | |
4984 | if (i.types[0].bitfield.imm8) | |
4985 | source = 1; | |
4986 | else | |
4987 | source = 0; | |
4988 | } | |
4989 | else | |
4990 | source = 2; | |
4991 | break; | |
4992 | case 5: | |
cab737b9 L |
4993 | break; |
4994 | default: | |
4995 | abort (); | |
4996 | } | |
4997 | ||
c0f3af97 L |
4998 | if (!vex_3_sources) |
4999 | { | |
5000 | dest = source + 1; | |
5001 | ||
5002 | if (i.tm.opcode_modifier.vexnds) | |
5003 | { | |
5004 | /* For instructions with VexNDS, the register-only | |
5005 | source operand must be XMM or YMM register. It is | |
fa99fab2 L |
5006 | encoded in VEX prefix. We need to clear RegMem bit |
5007 | before calling operand_type_equal. */ | |
5008 | i386_operand_type op = i.tm.operand_types[dest]; | |
5009 | op.bitfield.regmem = 0; | |
c0f3af97 | 5010 | if ((dest + 1) >= i.operands |
fa99fab2 L |
5011 | || (!operand_type_equal (&op, ®xmm) |
5012 | && !operand_type_equal (&op, ®ymm))) | |
c0f3af97 L |
5013 | abort (); |
5014 | i.vex.register_specifier = i.op[dest].regs; | |
5015 | dest++; | |
5016 | } | |
5017 | } | |
29b0f896 AM |
5018 | |
5019 | i.rm.mode = 3; | |
5020 | /* One of the register operands will be encoded in the i.tm.reg | |
5021 | field, the other in the combined i.tm.mode and i.tm.regmem | |
5022 | fields. If no form of this instruction supports a memory | |
5023 | destination operand, then we assume the source operand may | |
5024 | sometimes be a memory operand and so we need to store the | |
5025 | destination in the i.rm.reg field. */ | |
40fb9820 L |
5026 | if (!i.tm.operand_types[dest].bitfield.regmem |
5027 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) | |
29b0f896 AM |
5028 | { |
5029 | i.rm.reg = i.op[dest].regs->reg_num; | |
5030 | i.rm.regmem = i.op[source].regs->reg_num; | |
5031 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 5032 | i.rex |= REX_R; |
29b0f896 | 5033 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 5034 | i.rex |= REX_B; |
29b0f896 AM |
5035 | } |
5036 | else | |
5037 | { | |
5038 | i.rm.reg = i.op[source].regs->reg_num; | |
5039 | i.rm.regmem = i.op[dest].regs->reg_num; | |
5040 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 5041 | i.rex |= REX_B; |
29b0f896 | 5042 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 5043 | i.rex |= REX_R; |
29b0f896 | 5044 | } |
161a04f6 | 5045 | if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B))) |
c4a530c5 | 5046 | { |
40fb9820 L |
5047 | if (!i.types[0].bitfield.control |
5048 | && !i.types[1].bitfield.control) | |
c4a530c5 | 5049 | abort (); |
161a04f6 | 5050 | i.rex &= ~(REX_R | REX_B); |
c4a530c5 JB |
5051 | add_prefix (LOCK_PREFIX_OPCODE); |
5052 | } | |
29b0f896 AM |
5053 | } |
5054 | else | |
5055 | { /* If it's not 2 reg operands... */ | |
c0f3af97 L |
5056 | unsigned int mem; |
5057 | ||
29b0f896 AM |
5058 | if (i.mem_operands) |
5059 | { | |
5060 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 5061 | unsigned int op; |
4eed87de | 5062 | |
7ab9ffdd L |
5063 | for (op = 0; op < i.operands; op++) |
5064 | if (operand_type_check (i.types[op], anymem)) | |
5065 | break; | |
7ab9ffdd | 5066 | gas_assert (op < i.operands); |
29b0f896 AM |
5067 | |
5068 | default_seg = &ds; | |
5069 | ||
5070 | if (i.base_reg == 0) | |
5071 | { | |
5072 | i.rm.mode = 0; | |
5073 | if (!i.disp_operands) | |
5074 | fake_zero_displacement = 1; | |
5075 | if (i.index_reg == 0) | |
5076 | { | |
5077 | /* Operand is just <disp> */ | |
20f0a1fc | 5078 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
5079 | { |
5080 | /* 64bit mode overwrites the 32bit absolute | |
5081 | addressing by RIP relative addressing and | |
5082 | absolute addressing is encoded by one of the | |
5083 | redundant SIB forms. */ | |
5084 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
5085 | i.sib.base = NO_BASE_REGISTER; | |
5086 | i.sib.index = NO_INDEX_REGISTER; | |
fc225355 | 5087 | i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) |
40fb9820 | 5088 | ? disp32s : disp32); |
20f0a1fc | 5089 | } |
fc225355 L |
5090 | else if ((flag_code == CODE_16BIT) |
5091 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
5092 | { |
5093 | i.rm.regmem = NO_BASE_REGISTER_16; | |
40fb9820 | 5094 | i.types[op] = disp16; |
20f0a1fc NC |
5095 | } |
5096 | else | |
5097 | { | |
5098 | i.rm.regmem = NO_BASE_REGISTER; | |
40fb9820 | 5099 | i.types[op] = disp32; |
29b0f896 AM |
5100 | } |
5101 | } | |
5102 | else /* !i.base_reg && i.index_reg */ | |
5103 | { | |
db51cc60 L |
5104 | if (i.index_reg->reg_num == RegEiz |
5105 | || i.index_reg->reg_num == RegRiz) | |
5106 | i.sib.index = NO_INDEX_REGISTER; | |
5107 | else | |
5108 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
5109 | i.sib.base = NO_BASE_REGISTER; |
5110 | i.sib.scale = i.log2_scale_factor; | |
5111 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
40fb9820 L |
5112 | i.types[op].bitfield.disp8 = 0; |
5113 | i.types[op].bitfield.disp16 = 0; | |
5114 | i.types[op].bitfield.disp64 = 0; | |
29b0f896 | 5115 | if (flag_code != CODE_64BIT) |
40fb9820 L |
5116 | { |
5117 | /* Must be 32 bit */ | |
5118 | i.types[op].bitfield.disp32 = 1; | |
5119 | i.types[op].bitfield.disp32s = 0; | |
5120 | } | |
29b0f896 | 5121 | else |
40fb9820 L |
5122 | { |
5123 | i.types[op].bitfield.disp32 = 0; | |
5124 | i.types[op].bitfield.disp32s = 1; | |
5125 | } | |
29b0f896 | 5126 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 5127 | i.rex |= REX_X; |
29b0f896 AM |
5128 | } |
5129 | } | |
5130 | /* RIP addressing for 64bit mode. */ | |
9a04903e JB |
5131 | else if (i.base_reg->reg_num == RegRip || |
5132 | i.base_reg->reg_num == RegEip) | |
29b0f896 AM |
5133 | { |
5134 | i.rm.regmem = NO_BASE_REGISTER; | |
40fb9820 L |
5135 | i.types[op].bitfield.disp8 = 0; |
5136 | i.types[op].bitfield.disp16 = 0; | |
5137 | i.types[op].bitfield.disp32 = 0; | |
5138 | i.types[op].bitfield.disp32s = 1; | |
5139 | i.types[op].bitfield.disp64 = 0; | |
71903a11 | 5140 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
5141 | if (! i.disp_operands) |
5142 | fake_zero_displacement = 1; | |
29b0f896 | 5143 | } |
40fb9820 | 5144 | else if (i.base_reg->reg_type.bitfield.reg16) |
29b0f896 AM |
5145 | { |
5146 | switch (i.base_reg->reg_num) | |
5147 | { | |
5148 | case 3: /* (%bx) */ | |
5149 | if (i.index_reg == 0) | |
5150 | i.rm.regmem = 7; | |
5151 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
5152 | i.rm.regmem = i.index_reg->reg_num - 6; | |
5153 | break; | |
5154 | case 5: /* (%bp) */ | |
5155 | default_seg = &ss; | |
5156 | if (i.index_reg == 0) | |
5157 | { | |
5158 | i.rm.regmem = 6; | |
40fb9820 | 5159 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
5160 | { |
5161 | /* fake (%bp) into 0(%bp) */ | |
40fb9820 | 5162 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 5163 | fake_zero_displacement = 1; |
29b0f896 AM |
5164 | } |
5165 | } | |
5166 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
5167 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
5168 | break; | |
5169 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
5170 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
5171 | } | |
5172 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
5173 | } | |
5174 | else /* i.base_reg and 32/64 bit mode */ | |
5175 | { | |
5176 | if (flag_code == CODE_64BIT | |
40fb9820 L |
5177 | && operand_type_check (i.types[op], disp)) |
5178 | { | |
5179 | i386_operand_type temp; | |
0dfbf9d7 | 5180 | operand_type_set (&temp, 0); |
40fb9820 L |
5181 | temp.bitfield.disp8 = i.types[op].bitfield.disp8; |
5182 | i.types[op] = temp; | |
5183 | if (i.prefix[ADDR_PREFIX] == 0) | |
5184 | i.types[op].bitfield.disp32s = 1; | |
5185 | else | |
5186 | i.types[op].bitfield.disp32 = 1; | |
5187 | } | |
20f0a1fc | 5188 | |
29b0f896 AM |
5189 | i.rm.regmem = i.base_reg->reg_num; |
5190 | if ((i.base_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 5191 | i.rex |= REX_B; |
29b0f896 AM |
5192 | i.sib.base = i.base_reg->reg_num; |
5193 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
5194 | complications. */ | |
5195 | if ((i.base_reg->reg_num & 7) == EBP_REG_NUM) | |
5196 | { | |
5197 | default_seg = &ss; | |
5198 | if (i.disp_operands == 0) | |
5199 | { | |
5200 | fake_zero_displacement = 1; | |
40fb9820 | 5201 | i.types[op].bitfield.disp8 = 1; |
29b0f896 AM |
5202 | } |
5203 | } | |
5204 | else if (i.base_reg->reg_num == ESP_REG_NUM) | |
5205 | { | |
5206 | default_seg = &ss; | |
5207 | } | |
5208 | i.sib.scale = i.log2_scale_factor; | |
5209 | if (i.index_reg == 0) | |
5210 | { | |
5211 | /* <disp>(%esp) becomes two byte modrm with no index | |
5212 | register. We've already stored the code for esp | |
5213 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
5214 | Any base register besides %esp will not use the | |
5215 | extra modrm byte. */ | |
5216 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 AM |
5217 | } |
5218 | else | |
5219 | { | |
db51cc60 L |
5220 | if (i.index_reg->reg_num == RegEiz |
5221 | || i.index_reg->reg_num == RegRiz) | |
5222 | i.sib.index = NO_INDEX_REGISTER; | |
5223 | else | |
5224 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
5225 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
5226 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 5227 | i.rex |= REX_X; |
29b0f896 | 5228 | } |
67a4f2b7 AO |
5229 | |
5230 | if (i.disp_operands | |
5231 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
5232 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
5233 | i.rm.mode = 0; | |
5234 | else | |
5235 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
29b0f896 | 5236 | } |
252b5132 | 5237 | |
29b0f896 AM |
5238 | if (fake_zero_displacement) |
5239 | { | |
5240 | /* Fakes a zero displacement assuming that i.types[op] | |
5241 | holds the correct displacement size. */ | |
5242 | expressionS *exp; | |
5243 | ||
9c2799c2 | 5244 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
5245 | exp = &disp_expressions[i.disp_operands++]; |
5246 | i.op[op].disps = exp; | |
5247 | exp->X_op = O_constant; | |
5248 | exp->X_add_number = 0; | |
5249 | exp->X_add_symbol = (symbolS *) 0; | |
5250 | exp->X_op_symbol = (symbolS *) 0; | |
5251 | } | |
c0f3af97 L |
5252 | |
5253 | mem = op; | |
29b0f896 | 5254 | } |
c0f3af97 L |
5255 | else |
5256 | mem = ~0; | |
252b5132 | 5257 | |
29b0f896 AM |
5258 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
5259 | (if any) based on i.tm.extension_opcode. Again, we must be | |
5260 | careful to make sure that segment/control/debug/test/MMX | |
5261 | registers are coded into the i.rm.reg field. */ | |
5262 | if (i.reg_operands) | |
5263 | { | |
99018f42 | 5264 | unsigned int op; |
7ab9ffdd L |
5265 | unsigned int vex_reg = ~0; |
5266 | ||
5267 | for (op = 0; op < i.operands; op++) | |
5268 | if (i.types[op].bitfield.reg8 | |
5269 | || i.types[op].bitfield.reg16 | |
5270 | || i.types[op].bitfield.reg32 | |
5271 | || i.types[op].bitfield.reg64 | |
5272 | || i.types[op].bitfield.regmmx | |
5273 | || i.types[op].bitfield.regxmm | |
5274 | || i.types[op].bitfield.regymm | |
5275 | || i.types[op].bitfield.sreg2 | |
5276 | || i.types[op].bitfield.sreg3 | |
5277 | || i.types[op].bitfield.control | |
5278 | || i.types[op].bitfield.debug | |
5279 | || i.types[op].bitfield.test) | |
5280 | break; | |
c0209578 | 5281 | |
7ab9ffdd L |
5282 | if (vex_3_sources) |
5283 | op = dest; | |
5284 | else if (i.tm.opcode_modifier.vexnds) | |
5285 | { | |
5286 | /* For instructions with VexNDS, the register-only | |
5287 | source operand is encoded in VEX prefix. */ | |
5288 | gas_assert (mem != (unsigned int) ~0); | |
c0f3af97 | 5289 | |
7ab9ffdd | 5290 | if (op > mem) |
c0f3af97 | 5291 | { |
7ab9ffdd L |
5292 | vex_reg = op++; |
5293 | gas_assert (op < i.operands); | |
c0f3af97 L |
5294 | } |
5295 | else | |
c0f3af97 | 5296 | { |
7ab9ffdd L |
5297 | vex_reg = op + 1; |
5298 | gas_assert (vex_reg < i.operands); | |
c0f3af97 | 5299 | } |
7ab9ffdd L |
5300 | } |
5301 | else if (i.tm.opcode_modifier.vexndd) | |
5302 | { | |
5303 | /* For instructions with VexNDD, there should be | |
5304 | no memory operand and the register destination | |
5305 | is encoded in VEX prefix. */ | |
5306 | gas_assert (i.mem_operands == 0 | |
5307 | && (op + 2) == i.operands); | |
5308 | vex_reg = op + 1; | |
5309 | } | |
5310 | else | |
5311 | gas_assert (op < i.operands); | |
99018f42 | 5312 | |
7ab9ffdd L |
5313 | if (vex_reg != (unsigned int) ~0) |
5314 | { | |
5315 | gas_assert (i.reg_operands == 2); | |
5316 | ||
5317 | if (!operand_type_equal (&i.tm.operand_types[vex_reg], | |
5318 | & regxmm) | |
5319 | && !operand_type_equal (&i.tm.operand_types[vex_reg], | |
5320 | ®ymm)) | |
5321 | abort (); | |
5322 | i.vex.register_specifier = i.op[vex_reg].regs; | |
5323 | } | |
5324 | ||
5325 | /* If there is an extension opcode to put here, the | |
5326 | register number must be put into the regmem field. */ | |
5327 | if (i.tm.extension_opcode != None) | |
5328 | { | |
5329 | i.rm.regmem = i.op[op].regs->reg_num; | |
5330 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
5331 | i.rex |= REX_B; | |
5332 | } | |
5333 | else | |
5334 | { | |
5335 | i.rm.reg = i.op[op].regs->reg_num; | |
5336 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
5337 | i.rex |= REX_R; | |
5338 | } | |
252b5132 | 5339 | |
29b0f896 AM |
5340 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
5341 | must set it to 3 to indicate this is a register operand | |
5342 | in the regmem field. */ | |
5343 | if (!i.mem_operands) | |
5344 | i.rm.mode = 3; | |
5345 | } | |
252b5132 | 5346 | |
29b0f896 | 5347 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
c1e679ec | 5348 | if (i.tm.extension_opcode != None) |
29b0f896 AM |
5349 | i.rm.reg = i.tm.extension_opcode; |
5350 | } | |
5351 | return default_seg; | |
5352 | } | |
252b5132 | 5353 | |
29b0f896 | 5354 | static void |
e3bb37b5 | 5355 | output_branch (void) |
29b0f896 AM |
5356 | { |
5357 | char *p; | |
5358 | int code16; | |
5359 | int prefix; | |
5360 | relax_substateT subtype; | |
5361 | symbolS *sym; | |
5362 | offsetT off; | |
5363 | ||
5364 | code16 = 0; | |
5365 | if (flag_code == CODE_16BIT) | |
5366 | code16 = CODE16; | |
5367 | ||
5368 | prefix = 0; | |
5369 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 5370 | { |
29b0f896 AM |
5371 | prefix = 1; |
5372 | i.prefixes -= 1; | |
5373 | code16 ^= CODE16; | |
252b5132 | 5374 | } |
29b0f896 AM |
5375 | /* Pentium4 branch hints. */ |
5376 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
5377 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 5378 | { |
29b0f896 AM |
5379 | prefix++; |
5380 | i.prefixes--; | |
5381 | } | |
5382 | if (i.prefix[REX_PREFIX] != 0) | |
5383 | { | |
5384 | prefix++; | |
5385 | i.prefixes--; | |
2f66722d AM |
5386 | } |
5387 | ||
29b0f896 AM |
5388 | if (i.prefixes != 0 && !intel_syntax) |
5389 | as_warn (_("skipping prefixes on this instruction")); | |
5390 | ||
5391 | /* It's always a symbol; End frag & setup for relax. | |
5392 | Make sure there is enough room in this frag for the largest | |
5393 | instruction we may generate in md_convert_frag. This is 2 | |
5394 | bytes for the opcode and room for the prefix and largest | |
5395 | displacement. */ | |
5396 | frag_grow (prefix + 2 + 4); | |
5397 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
5398 | p = frag_more (prefix + 1); | |
5399 | if (i.prefix[DATA_PREFIX] != 0) | |
5400 | *p++ = DATA_PREFIX_OPCODE; | |
5401 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
5402 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
5403 | *p++ = i.prefix[SEG_PREFIX]; | |
5404 | if (i.prefix[REX_PREFIX] != 0) | |
5405 | *p++ = i.prefix[REX_PREFIX]; | |
5406 | *p = i.tm.base_opcode; | |
5407 | ||
5408 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
5409 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL); | |
40fb9820 | 5410 | else if (cpu_arch_flags.bitfield.cpui386) |
29b0f896 AM |
5411 | subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL); |
5412 | else | |
5413 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL); | |
5414 | subtype |= code16; | |
3e73aa7c | 5415 | |
29b0f896 AM |
5416 | sym = i.op[0].disps->X_add_symbol; |
5417 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 5418 | |
29b0f896 AM |
5419 | if (i.op[0].disps->X_op != O_constant |
5420 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 5421 | { |
29b0f896 AM |
5422 | /* Handle complex expressions. */ |
5423 | sym = make_expr_symbol (i.op[0].disps); | |
5424 | off = 0; | |
5425 | } | |
3e73aa7c | 5426 | |
29b0f896 AM |
5427 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
5428 | Pass reloc in fr_var. */ | |
5429 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); | |
5430 | } | |
3e73aa7c | 5431 | |
29b0f896 | 5432 | static void |
e3bb37b5 | 5433 | output_jump (void) |
29b0f896 AM |
5434 | { |
5435 | char *p; | |
5436 | int size; | |
3e02c1cc | 5437 | fixS *fixP; |
29b0f896 | 5438 | |
40fb9820 | 5439 | if (i.tm.opcode_modifier.jumpbyte) |
29b0f896 AM |
5440 | { |
5441 | /* This is a loop or jecxz type instruction. */ | |
5442 | size = 1; | |
5443 | if (i.prefix[ADDR_PREFIX] != 0) | |
5444 | { | |
5445 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
5446 | i.prefixes -= 1; | |
5447 | } | |
5448 | /* Pentium4 branch hints. */ | |
5449 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
5450 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
5451 | { | |
5452 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
5453 | i.prefixes--; | |
3e73aa7c JH |
5454 | } |
5455 | } | |
29b0f896 AM |
5456 | else |
5457 | { | |
5458 | int code16; | |
3e73aa7c | 5459 | |
29b0f896 AM |
5460 | code16 = 0; |
5461 | if (flag_code == CODE_16BIT) | |
5462 | code16 = CODE16; | |
3e73aa7c | 5463 | |
29b0f896 AM |
5464 | if (i.prefix[DATA_PREFIX] != 0) |
5465 | { | |
5466 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
5467 | i.prefixes -= 1; | |
5468 | code16 ^= CODE16; | |
5469 | } | |
252b5132 | 5470 | |
29b0f896 AM |
5471 | size = 4; |
5472 | if (code16) | |
5473 | size = 2; | |
5474 | } | |
9fcc94b6 | 5475 | |
29b0f896 AM |
5476 | if (i.prefix[REX_PREFIX] != 0) |
5477 | { | |
5478 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); | |
5479 | i.prefixes -= 1; | |
5480 | } | |
252b5132 | 5481 | |
29b0f896 AM |
5482 | if (i.prefixes != 0 && !intel_syntax) |
5483 | as_warn (_("skipping prefixes on this instruction")); | |
e0890092 | 5484 | |
29b0f896 AM |
5485 | p = frag_more (1 + size); |
5486 | *p++ = i.tm.base_opcode; | |
e0890092 | 5487 | |
3e02c1cc AM |
5488 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
5489 | i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0])); | |
5490 | ||
5491 | /* All jumps handled here are signed, but don't use a signed limit | |
5492 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
5493 | 4G and 64k respectively. */ | |
5494 | if (size == 1) | |
5495 | fixP->fx_signed = 1; | |
29b0f896 | 5496 | } |
e0890092 | 5497 | |
29b0f896 | 5498 | static void |
e3bb37b5 | 5499 | output_interseg_jump (void) |
29b0f896 AM |
5500 | { |
5501 | char *p; | |
5502 | int size; | |
5503 | int prefix; | |
5504 | int code16; | |
252b5132 | 5505 | |
29b0f896 AM |
5506 | code16 = 0; |
5507 | if (flag_code == CODE_16BIT) | |
5508 | code16 = CODE16; | |
a217f122 | 5509 | |
29b0f896 AM |
5510 | prefix = 0; |
5511 | if (i.prefix[DATA_PREFIX] != 0) | |
5512 | { | |
5513 | prefix = 1; | |
5514 | i.prefixes -= 1; | |
5515 | code16 ^= CODE16; | |
5516 | } | |
5517 | if (i.prefix[REX_PREFIX] != 0) | |
5518 | { | |
5519 | prefix++; | |
5520 | i.prefixes -= 1; | |
5521 | } | |
252b5132 | 5522 | |
29b0f896 AM |
5523 | size = 4; |
5524 | if (code16) | |
5525 | size = 2; | |
252b5132 | 5526 | |
29b0f896 AM |
5527 | if (i.prefixes != 0 && !intel_syntax) |
5528 | as_warn (_("skipping prefixes on this instruction")); | |
252b5132 | 5529 | |
29b0f896 AM |
5530 | /* 1 opcode; 2 segment; offset */ |
5531 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 5532 | |
29b0f896 AM |
5533 | if (i.prefix[DATA_PREFIX] != 0) |
5534 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 5535 | |
29b0f896 AM |
5536 | if (i.prefix[REX_PREFIX] != 0) |
5537 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 5538 | |
29b0f896 AM |
5539 | *p++ = i.tm.base_opcode; |
5540 | if (i.op[1].imms->X_op == O_constant) | |
5541 | { | |
5542 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 5543 | |
29b0f896 AM |
5544 | if (size == 2 |
5545 | && !fits_in_unsigned_word (n) | |
5546 | && !fits_in_signed_word (n)) | |
5547 | { | |
5548 | as_bad (_("16-bit jump out of range")); | |
5549 | return; | |
5550 | } | |
5551 | md_number_to_chars (p, n, size); | |
5552 | } | |
5553 | else | |
5554 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
5555 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); | |
5556 | if (i.op[0].imms->X_op != O_constant) | |
5557 | as_bad (_("can't handle non absolute segment in `%s'"), | |
5558 | i.tm.name); | |
5559 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
5560 | } | |
a217f122 | 5561 | |
29b0f896 | 5562 | static void |
e3bb37b5 | 5563 | output_insn (void) |
29b0f896 | 5564 | { |
2bbd9c25 JJ |
5565 | fragS *insn_start_frag; |
5566 | offsetT insn_start_off; | |
5567 | ||
29b0f896 AM |
5568 | /* Tie dwarf2 debug info to the address at the start of the insn. |
5569 | We can't do this after the insn has been output as the current | |
5570 | frag may have been closed off. eg. by frag_var. */ | |
5571 | dwarf2_emit_insn (0); | |
5572 | ||
2bbd9c25 JJ |
5573 | insn_start_frag = frag_now; |
5574 | insn_start_off = frag_now_fix (); | |
5575 | ||
29b0f896 | 5576 | /* Output jumps. */ |
40fb9820 | 5577 | if (i.tm.opcode_modifier.jump) |
29b0f896 | 5578 | output_branch (); |
40fb9820 L |
5579 | else if (i.tm.opcode_modifier.jumpbyte |
5580 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 | 5581 | output_jump (); |
40fb9820 | 5582 | else if (i.tm.opcode_modifier.jumpintersegment) |
29b0f896 AM |
5583 | output_interseg_jump (); |
5584 | else | |
5585 | { | |
5586 | /* Output normal instructions here. */ | |
5587 | char *p; | |
5588 | unsigned char *q; | |
47465058 | 5589 | unsigned int j; |
331d2d0d | 5590 | unsigned int prefix; |
4dffcebc | 5591 | |
c0f3af97 L |
5592 | /* Since the VEX prefix contains the implicit prefix, we don't |
5593 | need the explicit prefix. */ | |
5594 | if (!i.tm.opcode_modifier.vex) | |
bc4bd9ab | 5595 | { |
c0f3af97 | 5596 | switch (i.tm.opcode_length) |
bc4bd9ab | 5597 | { |
c0f3af97 L |
5598 | case 3: |
5599 | if (i.tm.base_opcode & 0xff000000) | |
4dffcebc | 5600 | { |
c0f3af97 L |
5601 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
5602 | goto check_prefix; | |
5603 | } | |
5604 | break; | |
5605 | case 2: | |
5606 | if ((i.tm.base_opcode & 0xff0000) != 0) | |
5607 | { | |
5608 | prefix = (i.tm.base_opcode >> 16) & 0xff; | |
5609 | if (i.tm.cpu_flags.bitfield.cpupadlock) | |
5610 | { | |
4dffcebc | 5611 | check_prefix: |
c0f3af97 L |
5612 | if (prefix != REPE_PREFIX_OPCODE |
5613 | || (i.prefix[LOCKREP_PREFIX] | |
5614 | != REPE_PREFIX_OPCODE)) | |
5615 | add_prefix (prefix); | |
5616 | } | |
5617 | else | |
4dffcebc L |
5618 | add_prefix (prefix); |
5619 | } | |
c0f3af97 L |
5620 | break; |
5621 | case 1: | |
5622 | break; | |
5623 | default: | |
5624 | abort (); | |
bc4bd9ab | 5625 | } |
c0f3af97 L |
5626 | |
5627 | /* The prefix bytes. */ | |
5628 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
5629 | if (*q) | |
5630 | FRAG_APPEND_1_CHAR (*q); | |
0f10071e | 5631 | } |
252b5132 | 5632 | |
c0f3af97 L |
5633 | if (i.tm.opcode_modifier.vex) |
5634 | { | |
5635 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
5636 | if (*q) | |
5637 | switch (j) | |
5638 | { | |
5639 | case REX_PREFIX: | |
5640 | /* REX byte is encoded in VEX prefix. */ | |
5641 | break; | |
5642 | case SEG_PREFIX: | |
5643 | case ADDR_PREFIX: | |
5644 | FRAG_APPEND_1_CHAR (*q); | |
5645 | break; | |
5646 | default: | |
5647 | /* There should be no other prefixes for instructions | |
5648 | with VEX prefix. */ | |
5649 | abort (); | |
5650 | } | |
5651 | ||
5652 | /* Now the VEX prefix. */ | |
5653 | p = frag_more (i.vex.length); | |
5654 | for (j = 0; j < i.vex.length; j++) | |
5655 | p[j] = i.vex.bytes[j]; | |
5656 | } | |
252b5132 | 5657 | |
29b0f896 | 5658 | /* Now the opcode; be careful about word order here! */ |
4dffcebc | 5659 | if (i.tm.opcode_length == 1) |
29b0f896 AM |
5660 | { |
5661 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
5662 | } | |
5663 | else | |
5664 | { | |
4dffcebc | 5665 | switch (i.tm.opcode_length) |
331d2d0d | 5666 | { |
4dffcebc | 5667 | case 3: |
331d2d0d L |
5668 | p = frag_more (3); |
5669 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
4dffcebc L |
5670 | break; |
5671 | case 2: | |
5672 | p = frag_more (2); | |
5673 | break; | |
5674 | default: | |
5675 | abort (); | |
5676 | break; | |
331d2d0d | 5677 | } |
0f10071e | 5678 | |
29b0f896 AM |
5679 | /* Put out high byte first: can't use md_number_to_chars! */ |
5680 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
5681 | *p = i.tm.base_opcode & 0xff; | |
5682 | } | |
3e73aa7c | 5683 | |
29b0f896 | 5684 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 5685 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 5686 | { |
4a3523fa L |
5687 | FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 |
5688 | | i.rm.reg << 3 | |
5689 | | i.rm.mode << 6)); | |
29b0f896 AM |
5690 | /* If i.rm.regmem == ESP (4) |
5691 | && i.rm.mode != (Register mode) | |
5692 | && not 16 bit | |
5693 | ==> need second modrm byte. */ | |
5694 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
5695 | && i.rm.mode != 3 | |
40fb9820 | 5696 | && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16)) |
4a3523fa L |
5697 | FRAG_APPEND_1_CHAR ((i.sib.base << 0 |
5698 | | i.sib.index << 3 | |
5699 | | i.sib.scale << 6)); | |
29b0f896 | 5700 | } |
3e73aa7c | 5701 | |
29b0f896 | 5702 | if (i.disp_operands) |
2bbd9c25 | 5703 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 5704 | |
29b0f896 | 5705 | if (i.imm_operands) |
2bbd9c25 | 5706 | output_imm (insn_start_frag, insn_start_off); |
29b0f896 | 5707 | } |
252b5132 | 5708 | |
29b0f896 AM |
5709 | #ifdef DEBUG386 |
5710 | if (flag_debug) | |
5711 | { | |
7b81dfbb | 5712 | pi ("" /*line*/, &i); |
29b0f896 AM |
5713 | } |
5714 | #endif /* DEBUG386 */ | |
5715 | } | |
252b5132 | 5716 | |
e205caa7 L |
5717 | /* Return the size of the displacement operand N. */ |
5718 | ||
5719 | static int | |
5720 | disp_size (unsigned int n) | |
5721 | { | |
5722 | int size = 4; | |
40fb9820 L |
5723 | if (i.types[n].bitfield.disp64) |
5724 | size = 8; | |
5725 | else if (i.types[n].bitfield.disp8) | |
5726 | size = 1; | |
5727 | else if (i.types[n].bitfield.disp16) | |
5728 | size = 2; | |
e205caa7 L |
5729 | return size; |
5730 | } | |
5731 | ||
5732 | /* Return the size of the immediate operand N. */ | |
5733 | ||
5734 | static int | |
5735 | imm_size (unsigned int n) | |
5736 | { | |
5737 | int size = 4; | |
40fb9820 L |
5738 | if (i.types[n].bitfield.imm64) |
5739 | size = 8; | |
5740 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
5741 | size = 1; | |
5742 | else if (i.types[n].bitfield.imm16) | |
5743 | size = 2; | |
e205caa7 L |
5744 | return size; |
5745 | } | |
5746 | ||
29b0f896 | 5747 | static void |
64e74474 | 5748 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
5749 | { |
5750 | char *p; | |
5751 | unsigned int n; | |
252b5132 | 5752 | |
29b0f896 AM |
5753 | for (n = 0; n < i.operands; n++) |
5754 | { | |
40fb9820 | 5755 | if (operand_type_check (i.types[n], disp)) |
29b0f896 AM |
5756 | { |
5757 | if (i.op[n].disps->X_op == O_constant) | |
5758 | { | |
e205caa7 | 5759 | int size = disp_size (n); |
29b0f896 | 5760 | offsetT val; |
252b5132 | 5761 | |
29b0f896 AM |
5762 | val = offset_in_range (i.op[n].disps->X_add_number, |
5763 | size); | |
5764 | p = frag_more (size); | |
5765 | md_number_to_chars (p, val, size); | |
5766 | } | |
5767 | else | |
5768 | { | |
f86103b7 | 5769 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 5770 | int size = disp_size (n); |
40fb9820 | 5771 | int sign = i.types[n].bitfield.disp32s; |
29b0f896 AM |
5772 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
5773 | ||
e205caa7 | 5774 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 5775 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 5776 | |
29b0f896 AM |
5777 | /* The PC relative address is computed relative |
5778 | to the instruction boundary, so in case immediate | |
5779 | fields follows, we need to adjust the value. */ | |
5780 | if (pcrel && i.imm_operands) | |
5781 | { | |
29b0f896 | 5782 | unsigned int n1; |
e205caa7 | 5783 | int sz = 0; |
252b5132 | 5784 | |
29b0f896 | 5785 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 5786 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 5787 | { |
e205caa7 L |
5788 | /* Only one immediate is allowed for PC |
5789 | relative address. */ | |
9c2799c2 | 5790 | gas_assert (sz == 0); |
e205caa7 L |
5791 | sz = imm_size (n1); |
5792 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 5793 | } |
29b0f896 | 5794 | /* We should find the immediate. */ |
9c2799c2 | 5795 | gas_assert (sz != 0); |
29b0f896 | 5796 | } |
520dc8e8 | 5797 | |
29b0f896 | 5798 | p = frag_more (size); |
2bbd9c25 | 5799 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 5800 | if (GOT_symbol |
2bbd9c25 | 5801 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 5802 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
5803 | || reloc_type == BFD_RELOC_X86_64_32S |
5804 | || (reloc_type == BFD_RELOC_64 | |
5805 | && object_64bit)) | |
d6ab8113 JB |
5806 | && (i.op[n].disps->X_op == O_symbol |
5807 | || (i.op[n].disps->X_op == O_add | |
5808 | && ((symbol_get_value_expression | |
5809 | (i.op[n].disps->X_op_symbol)->X_op) | |
5810 | == O_subtract)))) | |
5811 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 JJ |
5812 | { |
5813 | offsetT add; | |
5814 | ||
5815 | if (insn_start_frag == frag_now) | |
5816 | add = (p - frag_now->fr_literal) - insn_start_off; | |
5817 | else | |
5818 | { | |
5819 | fragS *fr; | |
5820 | ||
5821 | add = insn_start_frag->fr_fix - insn_start_off; | |
5822 | for (fr = insn_start_frag->fr_next; | |
5823 | fr && fr != frag_now; fr = fr->fr_next) | |
5824 | add += fr->fr_fix; | |
5825 | add += p - frag_now->fr_literal; | |
5826 | } | |
5827 | ||
4fa24527 | 5828 | if (!object_64bit) |
7b81dfbb AJ |
5829 | { |
5830 | reloc_type = BFD_RELOC_386_GOTPC; | |
5831 | i.op[n].imms->X_add_number += add; | |
5832 | } | |
5833 | else if (reloc_type == BFD_RELOC_64) | |
5834 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 5835 | else |
7b81dfbb AJ |
5836 | /* Don't do the adjustment for x86-64, as there |
5837 | the pcrel addressing is relative to the _next_ | |
5838 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 5839 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 5840 | } |
062cd5e7 | 5841 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
2bbd9c25 | 5842 | i.op[n].disps, pcrel, reloc_type); |
29b0f896 AM |
5843 | } |
5844 | } | |
5845 | } | |
5846 | } | |
252b5132 | 5847 | |
29b0f896 | 5848 | static void |
64e74474 | 5849 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
5850 | { |
5851 | char *p; | |
5852 | unsigned int n; | |
252b5132 | 5853 | |
29b0f896 AM |
5854 | for (n = 0; n < i.operands; n++) |
5855 | { | |
40fb9820 | 5856 | if (operand_type_check (i.types[n], imm)) |
29b0f896 AM |
5857 | { |
5858 | if (i.op[n].imms->X_op == O_constant) | |
5859 | { | |
e205caa7 | 5860 | int size = imm_size (n); |
29b0f896 | 5861 | offsetT val; |
b4cac588 | 5862 | |
29b0f896 AM |
5863 | val = offset_in_range (i.op[n].imms->X_add_number, |
5864 | size); | |
5865 | p = frag_more (size); | |
5866 | md_number_to_chars (p, val, size); | |
5867 | } | |
5868 | else | |
5869 | { | |
5870 | /* Not absolute_section. | |
5871 | Need a 32-bit fixup (don't support 8bit | |
5872 | non-absolute imms). Try to support other | |
5873 | sizes ... */ | |
f86103b7 | 5874 | enum bfd_reloc_code_real reloc_type; |
e205caa7 L |
5875 | int size = imm_size (n); |
5876 | int sign; | |
29b0f896 | 5877 | |
40fb9820 | 5878 | if (i.types[n].bitfield.imm32s |
a7d61044 | 5879 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 5880 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 5881 | sign = 1; |
e205caa7 L |
5882 | else |
5883 | sign = 0; | |
520dc8e8 | 5884 | |
29b0f896 AM |
5885 | p = frag_more (size); |
5886 | reloc_type = reloc (size, 0, sign, i.reloc[n]); | |
f86103b7 | 5887 | |
2bbd9c25 JJ |
5888 | /* This is tough to explain. We end up with this one if we |
5889 | * have operands that look like | |
5890 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
5891 | * obtain the absolute address of the GOT, and it is strongly | |
5892 | * preferable from a performance point of view to avoid using | |
5893 | * a runtime relocation for this. The actual sequence of | |
5894 | * instructions often look something like: | |
5895 | * | |
5896 | * call .L66 | |
5897 | * .L66: | |
5898 | * popl %ebx | |
5899 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
5900 | * | |
5901 | * The call and pop essentially return the absolute address | |
5902 | * of the label .L66 and store it in %ebx. The linker itself | |
5903 | * will ultimately change the first operand of the addl so | |
5904 | * that %ebx points to the GOT, but to keep things simple, the | |
5905 | * .o file must have this operand set so that it generates not | |
5906 | * the absolute address of .L66, but the absolute address of | |
5907 | * itself. This allows the linker itself simply treat a GOTPC | |
5908 | * relocation as asking for a pcrel offset to the GOT to be | |
5909 | * added in, and the addend of the relocation is stored in the | |
5910 | * operand field for the instruction itself. | |
5911 | * | |
5912 | * Our job here is to fix the operand so that it would add | |
5913 | * the correct offset so that %ebx would point to itself. The | |
5914 | * thing that is tricky is that .-.L66 will point to the | |
5915 | * beginning of the instruction, so we need to further modify | |
5916 | * the operand so that it will point to itself. There are | |
5917 | * other cases where you have something like: | |
5918 | * | |
5919 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
5920 | * | |
5921 | * and here no correction would be required. Internally in | |
5922 | * the assembler we treat operands of this form as not being | |
5923 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
5924 | * whether it would simplify matters to do it this way. Who | |
5925 | * knows. In earlier versions of the PIC patches, the | |
5926 | * pcrel_adjust field was used to store the correction, but | |
5927 | * since the expression is not pcrel, I felt it would be | |
5928 | * confusing to do it this way. */ | |
5929 | ||
d6ab8113 | 5930 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
5931 | || reloc_type == BFD_RELOC_X86_64_32S |
5932 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
5933 | && GOT_symbol |
5934 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
5935 | && (i.op[n].imms->X_op == O_symbol | |
5936 | || (i.op[n].imms->X_op == O_add | |
5937 | && ((symbol_get_value_expression | |
5938 | (i.op[n].imms->X_op_symbol)->X_op) | |
5939 | == O_subtract)))) | |
5940 | { | |
2bbd9c25 JJ |
5941 | offsetT add; |
5942 | ||
5943 | if (insn_start_frag == frag_now) | |
5944 | add = (p - frag_now->fr_literal) - insn_start_off; | |
5945 | else | |
5946 | { | |
5947 | fragS *fr; | |
5948 | ||
5949 | add = insn_start_frag->fr_fix - insn_start_off; | |
5950 | for (fr = insn_start_frag->fr_next; | |
5951 | fr && fr != frag_now; fr = fr->fr_next) | |
5952 | add += fr->fr_fix; | |
5953 | add += p - frag_now->fr_literal; | |
5954 | } | |
5955 | ||
4fa24527 | 5956 | if (!object_64bit) |
d6ab8113 | 5957 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 5958 | else if (size == 4) |
d6ab8113 | 5959 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
5960 | else if (size == 8) |
5961 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
2bbd9c25 | 5962 | i.op[n].imms->X_add_number += add; |
29b0f896 | 5963 | } |
29b0f896 AM |
5964 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
5965 | i.op[n].imms, 0, reloc_type); | |
5966 | } | |
5967 | } | |
5968 | } | |
252b5132 RH |
5969 | } |
5970 | \f | |
d182319b JB |
5971 | /* x86_cons_fix_new is called via the expression parsing code when a |
5972 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
5973 | static enum bfd_reloc_code_real got_reloc = NO_RELOC; | |
5974 | static int cons_sign = -1; | |
5975 | ||
5976 | void | |
e3bb37b5 | 5977 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
64e74474 | 5978 | expressionS *exp) |
d182319b JB |
5979 | { |
5980 | enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc); | |
5981 | ||
5982 | got_reloc = NO_RELOC; | |
5983 | ||
5984 | #ifdef TE_PE | |
5985 | if (exp->X_op == O_secrel) | |
5986 | { | |
5987 | exp->X_op = O_symbol; | |
5988 | r = BFD_RELOC_32_SECREL; | |
5989 | } | |
5990 | #endif | |
5991 | ||
5992 | fix_new_exp (frag, off, len, exp, 0, r); | |
5993 | } | |
5994 | ||
718ddfc0 JB |
5995 | #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT) |
5996 | # define lex_got(reloc, adjust, types) NULL | |
5997 | #else | |
f3c180ae AM |
5998 | /* Parse operands of the form |
5999 | <symbol>@GOTOFF+<nnn> | |
6000 | and similar .plt or .got references. | |
6001 | ||
6002 | If we find one, set up the correct relocation in RELOC and copy the | |
6003 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
6004 | parsing by the calling routine. Return this buffer, and if ADJUST | |
6005 | is non-null set it to the length of the string we removed from the | |
6006 | input line. Otherwise return NULL. */ | |
6007 | static char * | |
3956db08 | 6008 | lex_got (enum bfd_reloc_code_real *reloc, |
64e74474 | 6009 | int *adjust, |
40fb9820 | 6010 | i386_operand_type *types) |
f3c180ae | 6011 | { |
7b81dfbb AJ |
6012 | /* Some of the relocations depend on the size of what field is to |
6013 | be relocated. But in our callers i386_immediate and i386_displacement | |
6014 | we don't yet know the operand size (this will be set by insn | |
6015 | matching). Hence we record the word32 relocation here, | |
6016 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
6017 | static const struct { |
6018 | const char *str; | |
4fa24527 | 6019 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 6020 | const i386_operand_type types64; |
f3c180ae | 6021 | } gotrel[] = { |
4eed87de AM |
6022 | { "PLTOFF", { 0, |
6023 | BFD_RELOC_X86_64_PLTOFF64 }, | |
40fb9820 | 6024 | OPERAND_TYPE_IMM64 }, |
4eed87de AM |
6025 | { "PLT", { BFD_RELOC_386_PLT32, |
6026 | BFD_RELOC_X86_64_PLT32 }, | |
40fb9820 | 6027 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
6028 | { "GOTPLT", { 0, |
6029 | BFD_RELOC_X86_64_GOTPLT64 }, | |
40fb9820 | 6030 | OPERAND_TYPE_IMM64_DISP64 }, |
4eed87de AM |
6031 | { "GOTOFF", { BFD_RELOC_386_GOTOFF, |
6032 | BFD_RELOC_X86_64_GOTOFF64 }, | |
40fb9820 | 6033 | OPERAND_TYPE_IMM64_DISP64 }, |
4eed87de AM |
6034 | { "GOTPCREL", { 0, |
6035 | BFD_RELOC_X86_64_GOTPCREL }, | |
40fb9820 | 6036 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
6037 | { "TLSGD", { BFD_RELOC_386_TLS_GD, |
6038 | BFD_RELOC_X86_64_TLSGD }, | |
40fb9820 | 6039 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
6040 | { "TLSLDM", { BFD_RELOC_386_TLS_LDM, |
6041 | 0 }, | |
40fb9820 | 6042 | OPERAND_TYPE_NONE }, |
4eed87de AM |
6043 | { "TLSLD", { 0, |
6044 | BFD_RELOC_X86_64_TLSLD }, | |
40fb9820 | 6045 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
6046 | { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, |
6047 | BFD_RELOC_X86_64_GOTTPOFF }, | |
40fb9820 | 6048 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
6049 | { "TPOFF", { BFD_RELOC_386_TLS_LE_32, |
6050 | BFD_RELOC_X86_64_TPOFF32 }, | |
40fb9820 | 6051 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
4eed87de AM |
6052 | { "NTPOFF", { BFD_RELOC_386_TLS_LE, |
6053 | 0 }, | |
40fb9820 | 6054 | OPERAND_TYPE_NONE }, |
4eed87de AM |
6055 | { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, |
6056 | BFD_RELOC_X86_64_DTPOFF32 }, | |
7ab9ffdd | 6057 | |
40fb9820 | 6058 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
4eed87de AM |
6059 | { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, |
6060 | 0 }, | |
40fb9820 | 6061 | OPERAND_TYPE_NONE }, |
4eed87de AM |
6062 | { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, |
6063 | 0 }, | |
40fb9820 | 6064 | OPERAND_TYPE_NONE }, |
4eed87de AM |
6065 | { "GOT", { BFD_RELOC_386_GOT32, |
6066 | BFD_RELOC_X86_64_GOT32 }, | |
40fb9820 | 6067 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
4eed87de AM |
6068 | { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, |
6069 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
40fb9820 | 6070 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
6071 | { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, |
6072 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
40fb9820 | 6073 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
f3c180ae AM |
6074 | }; |
6075 | char *cp; | |
6076 | unsigned int j; | |
6077 | ||
718ddfc0 JB |
6078 | if (!IS_ELF) |
6079 | return NULL; | |
6080 | ||
f3c180ae | 6081 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 6082 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
6083 | return NULL; |
6084 | ||
47465058 | 6085 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae AM |
6086 | { |
6087 | int len; | |
6088 | ||
6089 | len = strlen (gotrel[j].str); | |
28f81592 | 6090 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 6091 | { |
4fa24527 | 6092 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 6093 | { |
28f81592 AM |
6094 | int first, second; |
6095 | char *tmpbuf, *past_reloc; | |
f3c180ae | 6096 | |
4fa24527 | 6097 | *reloc = gotrel[j].rel[object_64bit]; |
28f81592 AM |
6098 | if (adjust) |
6099 | *adjust = len; | |
f3c180ae | 6100 | |
3956db08 JB |
6101 | if (types) |
6102 | { | |
6103 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
6104 | { |
6105 | types->bitfield.imm32 = 1; | |
6106 | types->bitfield.disp32 = 1; | |
6107 | } | |
3956db08 JB |
6108 | else |
6109 | *types = gotrel[j].types64; | |
6110 | } | |
6111 | ||
f3c180ae AM |
6112 | if (GOT_symbol == NULL) |
6113 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
6114 | ||
28f81592 | 6115 | /* The length of the first part of our input line. */ |
f3c180ae | 6116 | first = cp - input_line_pointer; |
28f81592 AM |
6117 | |
6118 | /* The second part goes from after the reloc token until | |
67c11a9b | 6119 | (and including) an end_of_line char or comma. */ |
28f81592 | 6120 | past_reloc = cp + 1 + len; |
67c11a9b AM |
6121 | cp = past_reloc; |
6122 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
6123 | ++cp; | |
6124 | second = cp + 1 - past_reloc; | |
28f81592 AM |
6125 | |
6126 | /* Allocate and copy string. The trailing NUL shouldn't | |
6127 | be necessary, but be safe. */ | |
6128 | tmpbuf = xmalloc (first + second + 2); | |
f3c180ae | 6129 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
6130 | if (second != 0 && *past_reloc != ' ') |
6131 | /* Replace the relocation token with ' ', so that | |
6132 | errors like foo@GOTOFF1 will be detected. */ | |
6133 | tmpbuf[first++] = ' '; | |
6134 | memcpy (tmpbuf + first, past_reloc, second); | |
6135 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
6136 | return tmpbuf; |
6137 | } | |
6138 | ||
4fa24527 JB |
6139 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
6140 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
6141 | return NULL; |
6142 | } | |
6143 | } | |
6144 | ||
6145 | /* Might be a symbol version string. Don't as_bad here. */ | |
6146 | return NULL; | |
6147 | } | |
6148 | ||
f3c180ae | 6149 | void |
e3bb37b5 | 6150 | x86_cons (expressionS *exp, int size) |
f3c180ae | 6151 | { |
ee86248c JB |
6152 | intel_syntax = -intel_syntax; |
6153 | ||
4fa24527 | 6154 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
6155 | { |
6156 | /* Handle @GOTOFF and the like in an expression. */ | |
6157 | char *save; | |
6158 | char *gotfree_input_line; | |
6159 | int adjust; | |
6160 | ||
6161 | save = input_line_pointer; | |
3956db08 | 6162 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
6163 | if (gotfree_input_line) |
6164 | input_line_pointer = gotfree_input_line; | |
6165 | ||
6166 | expression (exp); | |
6167 | ||
6168 | if (gotfree_input_line) | |
6169 | { | |
6170 | /* expression () has merrily parsed up to the end of line, | |
6171 | or a comma - in the wrong buffer. Transfer how far | |
6172 | input_line_pointer has moved to the right buffer. */ | |
6173 | input_line_pointer = (save | |
6174 | + (input_line_pointer - gotfree_input_line) | |
6175 | + adjust); | |
6176 | free (gotfree_input_line); | |
3992d3b7 AM |
6177 | if (exp->X_op == O_constant |
6178 | || exp->X_op == O_absent | |
6179 | || exp->X_op == O_illegal | |
6180 | || exp->X_op == O_register | |
6181 | || exp->X_op == O_big) | |
6182 | { | |
6183 | char c = *input_line_pointer; | |
6184 | *input_line_pointer = 0; | |
6185 | as_bad (_("missing or invalid expression `%s'"), save); | |
6186 | *input_line_pointer = c; | |
6187 | } | |
f3c180ae AM |
6188 | } |
6189 | } | |
6190 | else | |
6191 | expression (exp); | |
ee86248c JB |
6192 | |
6193 | intel_syntax = -intel_syntax; | |
6194 | ||
6195 | if (intel_syntax) | |
6196 | i386_intel_simplify (exp); | |
f3c180ae AM |
6197 | } |
6198 | #endif | |
6199 | ||
d182319b | 6200 | static void signed_cons (int size) |
6482c264 | 6201 | { |
d182319b JB |
6202 | if (flag_code == CODE_64BIT) |
6203 | cons_sign = 1; | |
6204 | cons (size); | |
6205 | cons_sign = -1; | |
6482c264 NC |
6206 | } |
6207 | ||
d182319b | 6208 | #ifdef TE_PE |
6482c264 NC |
6209 | static void |
6210 | pe_directive_secrel (dummy) | |
6211 | int dummy ATTRIBUTE_UNUSED; | |
6212 | { | |
6213 | expressionS exp; | |
6214 | ||
6215 | do | |
6216 | { | |
6217 | expression (&exp); | |
6218 | if (exp.X_op == O_symbol) | |
6219 | exp.X_op = O_secrel; | |
6220 | ||
6221 | emit_expr (&exp, 4); | |
6222 | } | |
6223 | while (*input_line_pointer++ == ','); | |
6224 | ||
6225 | input_line_pointer--; | |
6226 | demand_empty_rest_of_line (); | |
6227 | } | |
6482c264 NC |
6228 | #endif |
6229 | ||
252b5132 | 6230 | static int |
70e41ade | 6231 | i386_immediate (char *imm_start) |
252b5132 RH |
6232 | { |
6233 | char *save_input_line_pointer; | |
f3c180ae | 6234 | char *gotfree_input_line; |
252b5132 | 6235 | segT exp_seg = 0; |
47926f60 | 6236 | expressionS *exp; |
40fb9820 L |
6237 | i386_operand_type types; |
6238 | ||
0dfbf9d7 | 6239 | operand_type_set (&types, ~0); |
252b5132 RH |
6240 | |
6241 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
6242 | { | |
31b2323c L |
6243 | as_bad (_("at most %d immediate operands are allowed"), |
6244 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
6245 | return 0; |
6246 | } | |
6247 | ||
6248 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 6249 | i.op[this_operand].imms = exp; |
252b5132 RH |
6250 | |
6251 | if (is_space_char (*imm_start)) | |
6252 | ++imm_start; | |
6253 | ||
6254 | save_input_line_pointer = input_line_pointer; | |
6255 | input_line_pointer = imm_start; | |
6256 | ||
3956db08 | 6257 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
6258 | if (gotfree_input_line) |
6259 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
6260 | |
6261 | exp_seg = expression (exp); | |
6262 | ||
83183c0c | 6263 | SKIP_WHITESPACE (); |
252b5132 | 6264 | if (*input_line_pointer) |
f3c180ae | 6265 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
6266 | |
6267 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 6268 | if (gotfree_input_line) |
ee86248c JB |
6269 | { |
6270 | free (gotfree_input_line); | |
6271 | ||
6272 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
6273 | exp->X_op = O_illegal; | |
6274 | } | |
6275 | ||
6276 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); | |
6277 | } | |
252b5132 | 6278 | |
ee86248c JB |
6279 | static int |
6280 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
6281 | i386_operand_type types, const char *imm_start) | |
6282 | { | |
6283 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 6284 | { |
3992d3b7 | 6285 | as_bad (_("missing or invalid immediate expression `%s'"), |
24eab124 | 6286 | imm_start); |
3992d3b7 | 6287 | return 0; |
252b5132 | 6288 | } |
3e73aa7c | 6289 | else if (exp->X_op == O_constant) |
252b5132 | 6290 | { |
47926f60 | 6291 | /* Size it properly later. */ |
40fb9820 | 6292 | i.types[this_operand].bitfield.imm64 = 1; |
3e73aa7c | 6293 | /* If BFD64, sign extend val. */ |
4eed87de AM |
6294 | if (!use_rela_relocations |
6295 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) | |
6296 | exp->X_add_number | |
6297 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 6298 | } |
4c63da97 | 6299 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 6300 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 6301 | && exp_seg != absolute_section |
47926f60 | 6302 | && exp_seg != text_section |
24eab124 AM |
6303 | && exp_seg != data_section |
6304 | && exp_seg != bss_section | |
6305 | && exp_seg != undefined_section | |
f86103b7 | 6306 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 6307 | { |
d0b47220 | 6308 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
6309 | return 0; |
6310 | } | |
6311 | #endif | |
bb8f5920 L |
6312 | else if (!intel_syntax && exp->X_op == O_register) |
6313 | { | |
6314 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
6315 | return 0; | |
6316 | } | |
252b5132 RH |
6317 | else |
6318 | { | |
6319 | /* This is an address. The size of the address will be | |
24eab124 | 6320 | determined later, depending on destination register, |
3e73aa7c | 6321 | suffix, or the default for the section. */ |
40fb9820 L |
6322 | i.types[this_operand].bitfield.imm8 = 1; |
6323 | i.types[this_operand].bitfield.imm16 = 1; | |
6324 | i.types[this_operand].bitfield.imm32 = 1; | |
6325 | i.types[this_operand].bitfield.imm32s = 1; | |
6326 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
6327 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
6328 | types); | |
252b5132 RH |
6329 | } |
6330 | ||
6331 | return 1; | |
6332 | } | |
6333 | ||
551c1ca1 | 6334 | static char * |
e3bb37b5 | 6335 | i386_scale (char *scale) |
252b5132 | 6336 | { |
551c1ca1 AM |
6337 | offsetT val; |
6338 | char *save = input_line_pointer; | |
252b5132 | 6339 | |
551c1ca1 AM |
6340 | input_line_pointer = scale; |
6341 | val = get_absolute_expression (); | |
6342 | ||
6343 | switch (val) | |
252b5132 | 6344 | { |
551c1ca1 | 6345 | case 1: |
252b5132 RH |
6346 | i.log2_scale_factor = 0; |
6347 | break; | |
551c1ca1 | 6348 | case 2: |
252b5132 RH |
6349 | i.log2_scale_factor = 1; |
6350 | break; | |
551c1ca1 | 6351 | case 4: |
252b5132 RH |
6352 | i.log2_scale_factor = 2; |
6353 | break; | |
551c1ca1 | 6354 | case 8: |
252b5132 RH |
6355 | i.log2_scale_factor = 3; |
6356 | break; | |
6357 | default: | |
a724f0f4 JB |
6358 | { |
6359 | char sep = *input_line_pointer; | |
6360 | ||
6361 | *input_line_pointer = '\0'; | |
6362 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
6363 | scale); | |
6364 | *input_line_pointer = sep; | |
6365 | input_line_pointer = save; | |
6366 | return NULL; | |
6367 | } | |
252b5132 | 6368 | } |
29b0f896 | 6369 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
6370 | { |
6371 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 6372 | 1 << i.log2_scale_factor); |
252b5132 | 6373 | i.log2_scale_factor = 0; |
252b5132 | 6374 | } |
551c1ca1 AM |
6375 | scale = input_line_pointer; |
6376 | input_line_pointer = save; | |
6377 | return scale; | |
252b5132 RH |
6378 | } |
6379 | ||
252b5132 | 6380 | static int |
e3bb37b5 | 6381 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 6382 | { |
29b0f896 | 6383 | expressionS *exp; |
252b5132 RH |
6384 | segT exp_seg = 0; |
6385 | char *save_input_line_pointer; | |
f3c180ae | 6386 | char *gotfree_input_line; |
40fb9820 L |
6387 | int override; |
6388 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 6389 | int ret; |
252b5132 | 6390 | |
31b2323c L |
6391 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
6392 | { | |
6393 | as_bad (_("at most %d displacement operands are allowed"), | |
6394 | MAX_MEMORY_OPERANDS); | |
6395 | return 0; | |
6396 | } | |
6397 | ||
0dfbf9d7 | 6398 | operand_type_set (&bigdisp, 0); |
40fb9820 L |
6399 | if ((i.types[this_operand].bitfield.jumpabsolute) |
6400 | || (!current_templates->start->opcode_modifier.jump | |
6401 | && !current_templates->start->opcode_modifier.jumpdword)) | |
e05278af | 6402 | { |
40fb9820 | 6403 | bigdisp.bitfield.disp32 = 1; |
e05278af | 6404 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
6405 | if (flag_code == CODE_64BIT) |
6406 | { | |
6407 | if (!override) | |
6408 | { | |
6409 | bigdisp.bitfield.disp32s = 1; | |
6410 | bigdisp.bitfield.disp64 = 1; | |
6411 | } | |
6412 | } | |
6413 | else if ((flag_code == CODE_16BIT) ^ override) | |
6414 | { | |
6415 | bigdisp.bitfield.disp32 = 0; | |
6416 | bigdisp.bitfield.disp16 = 1; | |
6417 | } | |
e05278af JB |
6418 | } |
6419 | else | |
6420 | { | |
6421 | /* For PC-relative branches, the width of the displacement | |
6422 | is dependent upon data size, not address size. */ | |
e05278af | 6423 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
6424 | if (flag_code == CODE_64BIT) |
6425 | { | |
6426 | if (override || i.suffix == WORD_MNEM_SUFFIX) | |
6427 | bigdisp.bitfield.disp16 = 1; | |
6428 | else | |
6429 | { | |
6430 | bigdisp.bitfield.disp32 = 1; | |
6431 | bigdisp.bitfield.disp32s = 1; | |
6432 | } | |
6433 | } | |
6434 | else | |
e05278af JB |
6435 | { |
6436 | if (!override) | |
6437 | override = (i.suffix == (flag_code != CODE_16BIT | |
6438 | ? WORD_MNEM_SUFFIX | |
6439 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
6440 | bigdisp.bitfield.disp32 = 1; |
6441 | if ((flag_code == CODE_16BIT) ^ override) | |
6442 | { | |
6443 | bigdisp.bitfield.disp32 = 0; | |
6444 | bigdisp.bitfield.disp16 = 1; | |
6445 | } | |
e05278af | 6446 | } |
e05278af | 6447 | } |
c6fb90c8 L |
6448 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
6449 | bigdisp); | |
252b5132 RH |
6450 | |
6451 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 6452 | i.op[this_operand].disps = exp; |
252b5132 RH |
6453 | i.disp_operands++; |
6454 | save_input_line_pointer = input_line_pointer; | |
6455 | input_line_pointer = disp_start; | |
6456 | END_STRING_AND_SAVE (disp_end); | |
6457 | ||
6458 | #ifndef GCC_ASM_O_HACK | |
6459 | #define GCC_ASM_O_HACK 0 | |
6460 | #endif | |
6461 | #if GCC_ASM_O_HACK | |
6462 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 6463 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 6464 | && displacement_string_end[-1] == '+') |
252b5132 RH |
6465 | { |
6466 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
6467 | constraint within gcc asm statements. |
6468 | For instance: | |
6469 | ||
6470 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
6471 | __asm__ __volatile__ ( \ | |
6472 | "movw %w2,%0\n\t" \ | |
6473 | "movw %w1,2+%0\n\t" \ | |
6474 | "rorl $16,%1\n\t" \ | |
6475 | "movb %b1,4+%0\n\t" \ | |
6476 | "movb %4,5+%0\n\t" \ | |
6477 | "movb $0,6+%0\n\t" \ | |
6478 | "movb %h1,7+%0\n\t" \ | |
6479 | "rorl $16,%1" \ | |
6480 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
6481 | ||
6482 | This works great except that the output assembler ends | |
6483 | up looking a bit weird if it turns out that there is | |
6484 | no offset. You end up producing code that looks like: | |
6485 | ||
6486 | #APP | |
6487 | movw $235,(%eax) | |
6488 | movw %dx,2+(%eax) | |
6489 | rorl $16,%edx | |
6490 | movb %dl,4+(%eax) | |
6491 | movb $137,5+(%eax) | |
6492 | movb $0,6+(%eax) | |
6493 | movb %dh,7+(%eax) | |
6494 | rorl $16,%edx | |
6495 | #NO_APP | |
6496 | ||
47926f60 | 6497 | So here we provide the missing zero. */ |
24eab124 AM |
6498 | |
6499 | *displacement_string_end = '0'; | |
252b5132 RH |
6500 | } |
6501 | #endif | |
3956db08 | 6502 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
6503 | if (gotfree_input_line) |
6504 | input_line_pointer = gotfree_input_line; | |
252b5132 | 6505 | |
24eab124 | 6506 | exp_seg = expression (exp); |
252b5132 | 6507 | |
636c26b0 AM |
6508 | SKIP_WHITESPACE (); |
6509 | if (*input_line_pointer) | |
6510 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
6511 | #if GCC_ASM_O_HACK | |
6512 | RESTORE_END_STRING (disp_end + 1); | |
6513 | #endif | |
636c26b0 | 6514 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 6515 | if (gotfree_input_line) |
ee86248c JB |
6516 | { |
6517 | free (gotfree_input_line); | |
6518 | ||
6519 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
6520 | exp->X_op = O_illegal; | |
6521 | } | |
6522 | ||
6523 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
6524 | ||
6525 | RESTORE_END_STRING (disp_end); | |
6526 | ||
6527 | return ret; | |
6528 | } | |
6529 | ||
6530 | static int | |
6531 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
6532 | i386_operand_type types, const char *disp_start) | |
6533 | { | |
6534 | i386_operand_type bigdisp; | |
6535 | int ret = 1; | |
636c26b0 | 6536 | |
24eab124 AM |
6537 | /* We do this to make sure that the section symbol is in |
6538 | the symbol table. We will ultimately change the relocation | |
47926f60 | 6539 | to be relative to the beginning of the section. */ |
1ae12ab7 | 6540 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
6541 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
6542 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 6543 | { |
636c26b0 | 6544 | if (exp->X_op != O_symbol) |
3992d3b7 | 6545 | goto inv_disp; |
636c26b0 | 6546 | |
e5cb08ac | 6547 | if (S_IS_LOCAL (exp->X_add_symbol) |
24eab124 AM |
6548 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section) |
6549 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); | |
24eab124 AM |
6550 | exp->X_op = O_subtract; |
6551 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 6552 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 6553 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
6554 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
6555 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 6556 | else |
29b0f896 | 6557 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 6558 | } |
252b5132 | 6559 | |
3992d3b7 AM |
6560 | else if (exp->X_op == O_absent |
6561 | || exp->X_op == O_illegal | |
ee86248c | 6562 | || exp->X_op == O_big) |
2daf4fd8 | 6563 | { |
3992d3b7 AM |
6564 | inv_disp: |
6565 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 6566 | disp_start); |
3992d3b7 | 6567 | ret = 0; |
2daf4fd8 AM |
6568 | } |
6569 | ||
4c63da97 | 6570 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3992d3b7 AM |
6571 | else if (exp->X_op != O_constant |
6572 | && OUTPUT_FLAVOR == bfd_target_aout_flavour | |
6573 | && exp_seg != absolute_section | |
6574 | && exp_seg != text_section | |
6575 | && exp_seg != data_section | |
6576 | && exp_seg != bss_section | |
6577 | && exp_seg != undefined_section | |
6578 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 6579 | { |
d0b47220 | 6580 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 6581 | ret = 0; |
24eab124 | 6582 | } |
252b5132 | 6583 | #endif |
3956db08 | 6584 | |
40fb9820 L |
6585 | /* Check if this is a displacement only operand. */ |
6586 | bigdisp = i.types[this_operand]; | |
6587 | bigdisp.bitfield.disp8 = 0; | |
6588 | bigdisp.bitfield.disp16 = 0; | |
6589 | bigdisp.bitfield.disp32 = 0; | |
6590 | bigdisp.bitfield.disp32s = 0; | |
6591 | bigdisp.bitfield.disp64 = 0; | |
0dfbf9d7 | 6592 | if (operand_type_all_zero (&bigdisp)) |
c6fb90c8 L |
6593 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
6594 | types); | |
3956db08 | 6595 | |
3992d3b7 | 6596 | return ret; |
252b5132 RH |
6597 | } |
6598 | ||
eecb386c | 6599 | /* Make sure the memory operand we've been dealt is valid. |
47926f60 KH |
6600 | Return 1 on success, 0 on a failure. */ |
6601 | ||
252b5132 | 6602 | static int |
e3bb37b5 | 6603 | i386_index_check (const char *operand_string) |
252b5132 | 6604 | { |
3e73aa7c | 6605 | int ok; |
fc0763e6 | 6606 | const char *kind = "base/index"; |
24eab124 | 6607 | #if INFER_ADDR_PREFIX |
eecb386c AM |
6608 | int fudged = 0; |
6609 | ||
24eab124 AM |
6610 | tryprefix: |
6611 | #endif | |
3e73aa7c | 6612 | ok = 1; |
fc0763e6 JB |
6613 | if (current_templates->start->opcode_modifier.isstring |
6614 | && !current_templates->start->opcode_modifier.immext | |
6615 | && (current_templates->end[-1].opcode_modifier.isstring | |
6616 | || i.mem_operands)) | |
6617 | { | |
6618 | /* Memory operands of string insns are special in that they only allow | |
6619 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
6620 | unsigned int expected; | |
6621 | ||
6622 | kind = "string address"; | |
6623 | ||
6624 | if (current_templates->start->opcode_modifier.w) | |
6625 | { | |
6626 | i386_operand_type type = current_templates->end[-1].operand_types[0]; | |
6627 | ||
6628 | if (!type.bitfield.baseindex | |
6629 | || ((!i.mem_operands != !intel_syntax) | |
6630 | && current_templates->end[-1].operand_types[1] | |
6631 | .bitfield.baseindex)) | |
6632 | type = current_templates->end[-1].operand_types[1]; | |
6633 | expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */; | |
6634 | } | |
6635 | else | |
6636 | expected = 3 /* rBX */; | |
6637 | ||
6638 | if (!i.base_reg || i.index_reg | |
6639 | || operand_type_check (i.types[this_operand], disp)) | |
6640 | ok = -1; | |
6641 | else if (!(flag_code == CODE_64BIT | |
6642 | ? i.prefix[ADDR_PREFIX] | |
6643 | ? i.base_reg->reg_type.bitfield.reg32 | |
6644 | : i.base_reg->reg_type.bitfield.reg64 | |
6645 | : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX] | |
6646 | ? i.base_reg->reg_type.bitfield.reg32 | |
6647 | : i.base_reg->reg_type.bitfield.reg16)) | |
6648 | ok = 0; | |
6649 | else if (i.base_reg->reg_num != expected) | |
6650 | ok = -1; | |
6651 | ||
6652 | if (ok < 0) | |
6653 | { | |
6654 | unsigned int j; | |
6655 | ||
6656 | for (j = 0; j < i386_regtab_size; ++j) | |
6657 | if ((flag_code == CODE_64BIT | |
6658 | ? i.prefix[ADDR_PREFIX] | |
6659 | ? i386_regtab[j].reg_type.bitfield.reg32 | |
6660 | : i386_regtab[j].reg_type.bitfield.reg64 | |
6661 | : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX] | |
6662 | ? i386_regtab[j].reg_type.bitfield.reg32 | |
6663 | : i386_regtab[j].reg_type.bitfield.reg16) | |
6664 | && i386_regtab[j].reg_num == expected) | |
6665 | break; | |
9c2799c2 | 6666 | gas_assert (j < i386_regtab_size); |
fc0763e6 JB |
6667 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
6668 | operand_string, | |
6669 | intel_syntax ? '[' : '(', | |
6670 | register_prefix, | |
6671 | i386_regtab[j].reg_name, | |
6672 | intel_syntax ? ']' : ')'); | |
6673 | ok = 1; | |
6674 | } | |
6675 | } | |
6676 | else if (flag_code == CODE_64BIT) | |
64e74474 | 6677 | { |
64e74474 | 6678 | if ((i.base_reg |
40fb9820 L |
6679 | && ((i.prefix[ADDR_PREFIX] == 0 |
6680 | && !i.base_reg->reg_type.bitfield.reg64) | |
6681 | || (i.prefix[ADDR_PREFIX] | |
6682 | && !i.base_reg->reg_type.bitfield.reg32)) | |
6683 | && (i.index_reg | |
9a04903e JB |
6684 | || i.base_reg->reg_num != |
6685 | (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip))) | |
64e74474 | 6686 | || (i.index_reg |
40fb9820 L |
6687 | && (!i.index_reg->reg_type.bitfield.baseindex |
6688 | || (i.prefix[ADDR_PREFIX] == 0 | |
db51cc60 L |
6689 | && i.index_reg->reg_num != RegRiz |
6690 | && !i.index_reg->reg_type.bitfield.reg64 | |
6691 | ) | |
40fb9820 | 6692 | || (i.prefix[ADDR_PREFIX] |
db51cc60 | 6693 | && i.index_reg->reg_num != RegEiz |
40fb9820 | 6694 | && !i.index_reg->reg_type.bitfield.reg32)))) |
64e74474 | 6695 | ok = 0; |
3e73aa7c JH |
6696 | } |
6697 | else | |
6698 | { | |
6699 | if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) | |
6700 | { | |
6701 | /* 16bit checks. */ | |
6702 | if ((i.base_reg | |
40fb9820 L |
6703 | && (!i.base_reg->reg_type.bitfield.reg16 |
6704 | || !i.base_reg->reg_type.bitfield.baseindex)) | |
3e73aa7c | 6705 | || (i.index_reg |
40fb9820 L |
6706 | && (!i.index_reg->reg_type.bitfield.reg16 |
6707 | || !i.index_reg->reg_type.bitfield.baseindex | |
29b0f896 AM |
6708 | || !(i.base_reg |
6709 | && i.base_reg->reg_num < 6 | |
6710 | && i.index_reg->reg_num >= 6 | |
6711 | && i.log2_scale_factor == 0)))) | |
3e73aa7c JH |
6712 | ok = 0; |
6713 | } | |
6714 | else | |
e5cb08ac | 6715 | { |
3e73aa7c JH |
6716 | /* 32bit checks. */ |
6717 | if ((i.base_reg | |
40fb9820 | 6718 | && !i.base_reg->reg_type.bitfield.reg32) |
3e73aa7c | 6719 | || (i.index_reg |
db51cc60 L |
6720 | && ((!i.index_reg->reg_type.bitfield.reg32 |
6721 | && i.index_reg->reg_num != RegEiz) | |
40fb9820 | 6722 | || !i.index_reg->reg_type.bitfield.baseindex))) |
e5cb08ac | 6723 | ok = 0; |
3e73aa7c JH |
6724 | } |
6725 | } | |
6726 | if (!ok) | |
24eab124 AM |
6727 | { |
6728 | #if INFER_ADDR_PREFIX | |
fc0763e6 | 6729 | if (!i.mem_operands && !i.prefix[ADDR_PREFIX]) |
24eab124 AM |
6730 | { |
6731 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
6732 | i.prefixes += 1; | |
b23bac36 AM |
6733 | /* Change the size of any displacement too. At most one of |
6734 | Disp16 or Disp32 is set. | |
6735 | FIXME. There doesn't seem to be any real need for separate | |
6736 | Disp16 and Disp32 flags. The same goes for Imm16 and Imm32. | |
47926f60 | 6737 | Removing them would probably clean up the code quite a lot. */ |
4eed87de | 6738 | if (flag_code != CODE_64BIT |
40fb9820 L |
6739 | && (i.types[this_operand].bitfield.disp16 |
6740 | || i.types[this_operand].bitfield.disp32)) | |
6741 | i.types[this_operand] | |
c6fb90c8 | 6742 | = operand_type_xor (i.types[this_operand], disp16_32); |
eecb386c | 6743 | fudged = 1; |
24eab124 AM |
6744 | goto tryprefix; |
6745 | } | |
eecb386c | 6746 | if (fudged) |
fc0763e6 JB |
6747 | as_bad (_("`%s' is not a valid %s expression"), |
6748 | operand_string, | |
6749 | kind); | |
eecb386c | 6750 | else |
c388dee8 | 6751 | #endif |
fc0763e6 | 6752 | as_bad (_("`%s' is not a valid %s-bit %s expression"), |
eecb386c | 6753 | operand_string, |
fc0763e6 JB |
6754 | flag_code_names[i.prefix[ADDR_PREFIX] |
6755 | ? flag_code == CODE_32BIT | |
6756 | ? CODE_16BIT | |
6757 | : CODE_32BIT | |
6758 | : flag_code], | |
6759 | kind); | |
24eab124 | 6760 | } |
20f0a1fc | 6761 | return ok; |
24eab124 | 6762 | } |
252b5132 | 6763 | |
fc0763e6 | 6764 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 6765 | on error. */ |
252b5132 | 6766 | |
252b5132 | 6767 | static int |
a7619375 | 6768 | i386_att_operand (char *operand_string) |
252b5132 | 6769 | { |
af6bdddf AM |
6770 | const reg_entry *r; |
6771 | char *end_op; | |
24eab124 | 6772 | char *op_string = operand_string; |
252b5132 | 6773 | |
24eab124 | 6774 | if (is_space_char (*op_string)) |
252b5132 RH |
6775 | ++op_string; |
6776 | ||
24eab124 | 6777 | /* We check for an absolute prefix (differentiating, |
47926f60 | 6778 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
6779 | if (*op_string == ABSOLUTE_PREFIX) |
6780 | { | |
6781 | ++op_string; | |
6782 | if (is_space_char (*op_string)) | |
6783 | ++op_string; | |
40fb9820 | 6784 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 | 6785 | } |
252b5132 | 6786 | |
47926f60 | 6787 | /* Check if operand is a register. */ |
4d1bb795 | 6788 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 6789 | { |
40fb9820 L |
6790 | i386_operand_type temp; |
6791 | ||
24eab124 AM |
6792 | /* Check for a segment override by searching for ':' after a |
6793 | segment register. */ | |
6794 | op_string = end_op; | |
6795 | if (is_space_char (*op_string)) | |
6796 | ++op_string; | |
40fb9820 L |
6797 | if (*op_string == ':' |
6798 | && (r->reg_type.bitfield.sreg2 | |
6799 | || r->reg_type.bitfield.sreg3)) | |
24eab124 AM |
6800 | { |
6801 | switch (r->reg_num) | |
6802 | { | |
6803 | case 0: | |
6804 | i.seg[i.mem_operands] = &es; | |
6805 | break; | |
6806 | case 1: | |
6807 | i.seg[i.mem_operands] = &cs; | |
6808 | break; | |
6809 | case 2: | |
6810 | i.seg[i.mem_operands] = &ss; | |
6811 | break; | |
6812 | case 3: | |
6813 | i.seg[i.mem_operands] = &ds; | |
6814 | break; | |
6815 | case 4: | |
6816 | i.seg[i.mem_operands] = &fs; | |
6817 | break; | |
6818 | case 5: | |
6819 | i.seg[i.mem_operands] = &gs; | |
6820 | break; | |
6821 | } | |
252b5132 | 6822 | |
24eab124 | 6823 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
6824 | ++op_string; |
6825 | if (is_space_char (*op_string)) | |
24eab124 | 6826 | ++op_string; |
252b5132 | 6827 | |
24eab124 AM |
6828 | if (!is_digit_char (*op_string) |
6829 | && !is_identifier_char (*op_string) | |
6830 | && *op_string != '(' | |
6831 | && *op_string != ABSOLUTE_PREFIX) | |
6832 | { | |
6833 | as_bad (_("bad memory operand `%s'"), op_string); | |
6834 | return 0; | |
6835 | } | |
47926f60 | 6836 | /* Handle case of %es:*foo. */ |
24eab124 AM |
6837 | if (*op_string == ABSOLUTE_PREFIX) |
6838 | { | |
6839 | ++op_string; | |
6840 | if (is_space_char (*op_string)) | |
6841 | ++op_string; | |
40fb9820 | 6842 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 AM |
6843 | } |
6844 | goto do_memory_reference; | |
6845 | } | |
6846 | if (*op_string) | |
6847 | { | |
d0b47220 | 6848 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
6849 | return 0; |
6850 | } | |
40fb9820 L |
6851 | temp = r->reg_type; |
6852 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
6853 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
6854 | temp); | |
7d5e4556 | 6855 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 6856 | i.op[this_operand].regs = r; |
24eab124 AM |
6857 | i.reg_operands++; |
6858 | } | |
af6bdddf AM |
6859 | else if (*op_string == REGISTER_PREFIX) |
6860 | { | |
6861 | as_bad (_("bad register name `%s'"), op_string); | |
6862 | return 0; | |
6863 | } | |
24eab124 | 6864 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 6865 | { |
24eab124 | 6866 | ++op_string; |
40fb9820 | 6867 | if (i.types[this_operand].bitfield.jumpabsolute) |
24eab124 | 6868 | { |
d0b47220 | 6869 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
6870 | return 0; |
6871 | } | |
6872 | if (!i386_immediate (op_string)) | |
6873 | return 0; | |
6874 | } | |
6875 | else if (is_digit_char (*op_string) | |
6876 | || is_identifier_char (*op_string) | |
e5cb08ac | 6877 | || *op_string == '(') |
24eab124 | 6878 | { |
47926f60 | 6879 | /* This is a memory reference of some sort. */ |
af6bdddf | 6880 | char *base_string; |
252b5132 | 6881 | |
47926f60 | 6882 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
6883 | char *displacement_string_start; |
6884 | char *displacement_string_end; | |
252b5132 | 6885 | |
24eab124 | 6886 | do_memory_reference: |
24eab124 | 6887 | if ((i.mem_operands == 1 |
40fb9820 | 6888 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
6889 | || i.mem_operands == 2) |
6890 | { | |
6891 | as_bad (_("too many memory references for `%s'"), | |
6892 | current_templates->start->name); | |
6893 | return 0; | |
6894 | } | |
252b5132 | 6895 | |
24eab124 AM |
6896 | /* Check for base index form. We detect the base index form by |
6897 | looking for an ')' at the end of the operand, searching | |
6898 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
6899 | after the '('. */ | |
af6bdddf | 6900 | base_string = op_string + strlen (op_string); |
c3332e24 | 6901 | |
af6bdddf AM |
6902 | --base_string; |
6903 | if (is_space_char (*base_string)) | |
6904 | --base_string; | |
252b5132 | 6905 | |
47926f60 | 6906 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
6907 | displacement_string_start = op_string; |
6908 | displacement_string_end = base_string + 1; | |
252b5132 | 6909 | |
24eab124 AM |
6910 | if (*base_string == ')') |
6911 | { | |
af6bdddf | 6912 | char *temp_string; |
24eab124 AM |
6913 | unsigned int parens_balanced = 1; |
6914 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 6915 | equal, so this loop will not be infinite. */ |
24eab124 AM |
6916 | do |
6917 | { | |
6918 | base_string--; | |
6919 | if (*base_string == ')') | |
6920 | parens_balanced++; | |
6921 | if (*base_string == '(') | |
6922 | parens_balanced--; | |
6923 | } | |
6924 | while (parens_balanced); | |
c3332e24 | 6925 | |
af6bdddf | 6926 | temp_string = base_string; |
c3332e24 | 6927 | |
24eab124 | 6928 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
6929 | ++base_string; |
6930 | if (is_space_char (*base_string)) | |
24eab124 | 6931 | ++base_string; |
252b5132 | 6932 | |
af6bdddf | 6933 | if (*base_string == ',' |
4eed87de AM |
6934 | || ((i.base_reg = parse_register (base_string, &end_op)) |
6935 | != NULL)) | |
252b5132 | 6936 | { |
af6bdddf | 6937 | displacement_string_end = temp_string; |
252b5132 | 6938 | |
40fb9820 | 6939 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 6940 | |
af6bdddf | 6941 | if (i.base_reg) |
24eab124 | 6942 | { |
24eab124 AM |
6943 | base_string = end_op; |
6944 | if (is_space_char (*base_string)) | |
6945 | ++base_string; | |
af6bdddf AM |
6946 | } |
6947 | ||
6948 | /* There may be an index reg or scale factor here. */ | |
6949 | if (*base_string == ',') | |
6950 | { | |
6951 | ++base_string; | |
6952 | if (is_space_char (*base_string)) | |
6953 | ++base_string; | |
6954 | ||
4eed87de AM |
6955 | if ((i.index_reg = parse_register (base_string, &end_op)) |
6956 | != NULL) | |
24eab124 | 6957 | { |
af6bdddf | 6958 | base_string = end_op; |
24eab124 AM |
6959 | if (is_space_char (*base_string)) |
6960 | ++base_string; | |
af6bdddf AM |
6961 | if (*base_string == ',') |
6962 | { | |
6963 | ++base_string; | |
6964 | if (is_space_char (*base_string)) | |
6965 | ++base_string; | |
6966 | } | |
e5cb08ac | 6967 | else if (*base_string != ')') |
af6bdddf | 6968 | { |
4eed87de AM |
6969 | as_bad (_("expecting `,' or `)' " |
6970 | "after index register in `%s'"), | |
af6bdddf AM |
6971 | operand_string); |
6972 | return 0; | |
6973 | } | |
24eab124 | 6974 | } |
af6bdddf | 6975 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 6976 | { |
af6bdddf | 6977 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
6978 | return 0; |
6979 | } | |
252b5132 | 6980 | |
47926f60 | 6981 | /* Check for scale factor. */ |
551c1ca1 | 6982 | if (*base_string != ')') |
af6bdddf | 6983 | { |
551c1ca1 AM |
6984 | char *end_scale = i386_scale (base_string); |
6985 | ||
6986 | if (!end_scale) | |
af6bdddf | 6987 | return 0; |
24eab124 | 6988 | |
551c1ca1 | 6989 | base_string = end_scale; |
af6bdddf AM |
6990 | if (is_space_char (*base_string)) |
6991 | ++base_string; | |
6992 | if (*base_string != ')') | |
6993 | { | |
4eed87de AM |
6994 | as_bad (_("expecting `)' " |
6995 | "after scale factor in `%s'"), | |
af6bdddf AM |
6996 | operand_string); |
6997 | return 0; | |
6998 | } | |
6999 | } | |
7000 | else if (!i.index_reg) | |
24eab124 | 7001 | { |
4eed87de AM |
7002 | as_bad (_("expecting index register or scale factor " |
7003 | "after `,'; got '%c'"), | |
af6bdddf | 7004 | *base_string); |
24eab124 AM |
7005 | return 0; |
7006 | } | |
7007 | } | |
af6bdddf | 7008 | else if (*base_string != ')') |
24eab124 | 7009 | { |
4eed87de AM |
7010 | as_bad (_("expecting `,' or `)' " |
7011 | "after base register in `%s'"), | |
af6bdddf | 7012 | operand_string); |
24eab124 AM |
7013 | return 0; |
7014 | } | |
c3332e24 | 7015 | } |
af6bdddf | 7016 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 7017 | { |
af6bdddf | 7018 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 7019 | return 0; |
c3332e24 | 7020 | } |
24eab124 AM |
7021 | } |
7022 | ||
7023 | /* If there's an expression beginning the operand, parse it, | |
7024 | assuming displacement_string_start and | |
7025 | displacement_string_end are meaningful. */ | |
7026 | if (displacement_string_start != displacement_string_end) | |
7027 | { | |
7028 | if (!i386_displacement (displacement_string_start, | |
7029 | displacement_string_end)) | |
7030 | return 0; | |
7031 | } | |
7032 | ||
7033 | /* Special case for (%dx) while doing input/output op. */ | |
7034 | if (i.base_reg | |
0dfbf9d7 L |
7035 | && operand_type_equal (&i.base_reg->reg_type, |
7036 | ®16_inoutportreg) | |
24eab124 AM |
7037 | && i.index_reg == 0 |
7038 | && i.log2_scale_factor == 0 | |
7039 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 7040 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 7041 | { |
65da13b5 | 7042 | i.types[this_operand] = inoutportreg; |
24eab124 AM |
7043 | return 1; |
7044 | } | |
7045 | ||
eecb386c AM |
7046 | if (i386_index_check (operand_string) == 0) |
7047 | return 0; | |
5c07affc | 7048 | i.types[this_operand].bitfield.mem = 1; |
24eab124 AM |
7049 | i.mem_operands++; |
7050 | } | |
7051 | else | |
ce8a8b2f AM |
7052 | { |
7053 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
7054 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
7055 | output_invalid (*op_string), | |
7056 | this_operand + 1, | |
7057 | op_string); | |
7058 | return 0; | |
7059 | } | |
47926f60 | 7060 | return 1; /* Normal return. */ |
252b5132 RH |
7061 | } |
7062 | \f | |
ee7fcc42 AM |
7063 | /* md_estimate_size_before_relax() |
7064 | ||
7065 | Called just before relax() for rs_machine_dependent frags. The x86 | |
7066 | assembler uses these frags to handle variable size jump | |
7067 | instructions. | |
7068 | ||
7069 | Any symbol that is now undefined will not become defined. | |
7070 | Return the correct fr_subtype in the frag. | |
7071 | Return the initial "guess for variable size of frag" to caller. | |
7072 | The guess is actually the growth beyond the fixed part. Whatever | |
7073 | we do to grow the fixed or variable part contributes to our | |
7074 | returned value. */ | |
7075 | ||
252b5132 RH |
7076 | int |
7077 | md_estimate_size_before_relax (fragP, segment) | |
29b0f896 AM |
7078 | fragS *fragP; |
7079 | segT segment; | |
252b5132 | 7080 | { |
252b5132 | 7081 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
7082 | check for un-relaxable symbols. On an ELF system, we can't relax |
7083 | an externally visible symbol, because it may be overridden by a | |
7084 | shared library. */ | |
7085 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 7086 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 7087 | || (IS_ELF |
31312f95 | 7088 | && (S_IS_EXTERNAL (fragP->fr_symbol) |
915bcca5 L |
7089 | || S_IS_WEAK (fragP->fr_symbol) |
7090 | || ((symbol_get_bfdsym (fragP->fr_symbol)->flags | |
7091 | & BSF_GNU_INDIRECT_FUNCTION)))) | |
fbeb56a4 DK |
7092 | #endif |
7093 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 7094 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 7095 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
7096 | #endif |
7097 | ) | |
252b5132 | 7098 | { |
b98ef147 AM |
7099 | /* Symbol is undefined in this segment, or we need to keep a |
7100 | reloc so that weak symbols can be overridden. */ | |
7101 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 7102 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
7103 | unsigned char *opcode; |
7104 | int old_fr_fix; | |
f6af82bd | 7105 | |
ee7fcc42 AM |
7106 | if (fragP->fr_var != NO_RELOC) |
7107 | reloc_type = fragP->fr_var; | |
b98ef147 | 7108 | else if (size == 2) |
f6af82bd AM |
7109 | reloc_type = BFD_RELOC_16_PCREL; |
7110 | else | |
7111 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 7112 | |
ee7fcc42 AM |
7113 | old_fr_fix = fragP->fr_fix; |
7114 | opcode = (unsigned char *) fragP->fr_opcode; | |
7115 | ||
fddf5b5b | 7116 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 7117 | { |
fddf5b5b AM |
7118 | case UNCOND_JUMP: |
7119 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 7120 | opcode[0] = 0xe9; |
252b5132 | 7121 | fragP->fr_fix += size; |
062cd5e7 AS |
7122 | fix_new (fragP, old_fr_fix, size, |
7123 | fragP->fr_symbol, | |
7124 | fragP->fr_offset, 1, | |
7125 | reloc_type); | |
252b5132 RH |
7126 | break; |
7127 | ||
fddf5b5b | 7128 | case COND_JUMP86: |
412167cb AM |
7129 | if (size == 2 |
7130 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
7131 | { |
7132 | /* Negate the condition, and branch past an | |
7133 | unconditional jump. */ | |
7134 | opcode[0] ^= 1; | |
7135 | opcode[1] = 3; | |
7136 | /* Insert an unconditional jump. */ | |
7137 | opcode[2] = 0xe9; | |
7138 | /* We added two extra opcode bytes, and have a two byte | |
7139 | offset. */ | |
7140 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
7141 | fix_new (fragP, old_fr_fix + 2, 2, |
7142 | fragP->fr_symbol, | |
7143 | fragP->fr_offset, 1, | |
7144 | reloc_type); | |
fddf5b5b AM |
7145 | break; |
7146 | } | |
7147 | /* Fall through. */ | |
7148 | ||
7149 | case COND_JUMP: | |
412167cb AM |
7150 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
7151 | { | |
3e02c1cc AM |
7152 | fixS *fixP; |
7153 | ||
412167cb | 7154 | fragP->fr_fix += 1; |
3e02c1cc AM |
7155 | fixP = fix_new (fragP, old_fr_fix, 1, |
7156 | fragP->fr_symbol, | |
7157 | fragP->fr_offset, 1, | |
7158 | BFD_RELOC_8_PCREL); | |
7159 | fixP->fx_signed = 1; | |
412167cb AM |
7160 | break; |
7161 | } | |
93c2a809 | 7162 | |
24eab124 | 7163 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 7164 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 7165 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 7166 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
7167 | /* We've added an opcode byte. */ |
7168 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
7169 | fix_new (fragP, old_fr_fix + 1, size, |
7170 | fragP->fr_symbol, | |
7171 | fragP->fr_offset, 1, | |
7172 | reloc_type); | |
252b5132 | 7173 | break; |
fddf5b5b AM |
7174 | |
7175 | default: | |
7176 | BAD_CASE (fragP->fr_subtype); | |
7177 | break; | |
252b5132 RH |
7178 | } |
7179 | frag_wane (fragP); | |
ee7fcc42 | 7180 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 7181 | } |
93c2a809 | 7182 | |
93c2a809 AM |
7183 | /* Guess size depending on current relax state. Initially the relax |
7184 | state will correspond to a short jump and we return 1, because | |
7185 | the variable part of the frag (the branch offset) is one byte | |
7186 | long. However, we can relax a section more than once and in that | |
7187 | case we must either set fr_subtype back to the unrelaxed state, | |
7188 | or return the value for the appropriate branch. */ | |
7189 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
7190 | } |
7191 | ||
47926f60 KH |
7192 | /* Called after relax() is finished. |
7193 | ||
7194 | In: Address of frag. | |
7195 | fr_type == rs_machine_dependent. | |
7196 | fr_subtype is what the address relaxed to. | |
7197 | ||
7198 | Out: Any fixSs and constants are set up. | |
7199 | Caller will turn frag into a ".space 0". */ | |
7200 | ||
252b5132 RH |
7201 | void |
7202 | md_convert_frag (abfd, sec, fragP) | |
ab9da554 ILT |
7203 | bfd *abfd ATTRIBUTE_UNUSED; |
7204 | segT sec ATTRIBUTE_UNUSED; | |
29b0f896 | 7205 | fragS *fragP; |
252b5132 | 7206 | { |
29b0f896 | 7207 | unsigned char *opcode; |
252b5132 | 7208 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
7209 | offsetT target_address; |
7210 | offsetT opcode_address; | |
252b5132 | 7211 | unsigned int extension = 0; |
847f7ad4 | 7212 | offsetT displacement_from_opcode_start; |
252b5132 RH |
7213 | |
7214 | opcode = (unsigned char *) fragP->fr_opcode; | |
7215 | ||
47926f60 | 7216 | /* Address we want to reach in file space. */ |
252b5132 | 7217 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 7218 | |
47926f60 | 7219 | /* Address opcode resides at in file space. */ |
252b5132 RH |
7220 | opcode_address = fragP->fr_address + fragP->fr_fix; |
7221 | ||
47926f60 | 7222 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
7223 | displacement_from_opcode_start = target_address - opcode_address; |
7224 | ||
fddf5b5b | 7225 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 7226 | { |
47926f60 KH |
7227 | /* Don't have to change opcode. */ |
7228 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 7229 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
7230 | } |
7231 | else | |
7232 | { | |
7233 | if (no_cond_jump_promotion | |
7234 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
7235 | as_warn_where (fragP->fr_file, fragP->fr_line, |
7236 | _("long jump required")); | |
252b5132 | 7237 | |
fddf5b5b AM |
7238 | switch (fragP->fr_subtype) |
7239 | { | |
7240 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
7241 | extension = 4; /* 1 opcode + 4 displacement */ | |
7242 | opcode[0] = 0xe9; | |
7243 | where_to_put_displacement = &opcode[1]; | |
7244 | break; | |
252b5132 | 7245 | |
fddf5b5b AM |
7246 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
7247 | extension = 2; /* 1 opcode + 2 displacement */ | |
7248 | opcode[0] = 0xe9; | |
7249 | where_to_put_displacement = &opcode[1]; | |
7250 | break; | |
252b5132 | 7251 | |
fddf5b5b AM |
7252 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
7253 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
7254 | extension = 5; /* 2 opcode + 4 displacement */ | |
7255 | opcode[1] = opcode[0] + 0x10; | |
7256 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
7257 | where_to_put_displacement = &opcode[2]; | |
7258 | break; | |
252b5132 | 7259 | |
fddf5b5b AM |
7260 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
7261 | extension = 3; /* 2 opcode + 2 displacement */ | |
7262 | opcode[1] = opcode[0] + 0x10; | |
7263 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
7264 | where_to_put_displacement = &opcode[2]; | |
7265 | break; | |
252b5132 | 7266 | |
fddf5b5b AM |
7267 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
7268 | extension = 4; | |
7269 | opcode[0] ^= 1; | |
7270 | opcode[1] = 3; | |
7271 | opcode[2] = 0xe9; | |
7272 | where_to_put_displacement = &opcode[3]; | |
7273 | break; | |
7274 | ||
7275 | default: | |
7276 | BAD_CASE (fragP->fr_subtype); | |
7277 | break; | |
7278 | } | |
252b5132 | 7279 | } |
fddf5b5b | 7280 | |
7b81dfbb AJ |
7281 | /* If size if less then four we are sure that the operand fits, |
7282 | but if it's 4, then it could be that the displacement is larger | |
7283 | then -/+ 2GB. */ | |
7284 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
7285 | && object_64bit | |
7286 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
7287 | + ((addressT) 1 << 31)) |
7288 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
7289 | { |
7290 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
7291 | _("jump target out of range")); | |
7292 | /* Make us emit 0. */ | |
7293 | displacement_from_opcode_start = extension; | |
7294 | } | |
47926f60 | 7295 | /* Now put displacement after opcode. */ |
252b5132 RH |
7296 | md_number_to_chars ((char *) where_to_put_displacement, |
7297 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 7298 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
7299 | fragP->fr_fix += extension; |
7300 | } | |
7301 | \f | |
252b5132 RH |
7302 | /* Apply a fixup (fixS) to segment data, once it has been determined |
7303 | by our caller that we have all the info we need to fix it up. | |
7304 | ||
7305 | On the 386, immediates, displacements, and data pointers are all in | |
7306 | the same (little-endian) format, so we don't need to care about which | |
7307 | we are handling. */ | |
7308 | ||
94f592af | 7309 | void |
55cf6793 | 7310 | md_apply_fix (fixP, valP, seg) |
47926f60 KH |
7311 | /* The fix we're to put in. */ |
7312 | fixS *fixP; | |
47926f60 | 7313 | /* Pointer to the value of the bits. */ |
c6682705 | 7314 | valueT *valP; |
47926f60 KH |
7315 | /* Segment fix is from. */ |
7316 | segT seg ATTRIBUTE_UNUSED; | |
252b5132 | 7317 | { |
94f592af | 7318 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 7319 | valueT value = *valP; |
252b5132 | 7320 | |
f86103b7 | 7321 | #if !defined (TE_Mach) |
93382f6d AM |
7322 | if (fixP->fx_pcrel) |
7323 | { | |
7324 | switch (fixP->fx_r_type) | |
7325 | { | |
5865bb77 ILT |
7326 | default: |
7327 | break; | |
7328 | ||
d6ab8113 JB |
7329 | case BFD_RELOC_64: |
7330 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
7331 | break; | |
93382f6d | 7332 | case BFD_RELOC_32: |
ae8887b5 | 7333 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
7334 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
7335 | break; | |
7336 | case BFD_RELOC_16: | |
7337 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
7338 | break; | |
7339 | case BFD_RELOC_8: | |
7340 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
7341 | break; | |
7342 | } | |
7343 | } | |
252b5132 | 7344 | |
a161fe53 | 7345 | if (fixP->fx_addsy != NULL |
31312f95 | 7346 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 7347 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 AM |
7348 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
7349 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) | |
7350 | && !use_rela_relocations) | |
252b5132 | 7351 | { |
31312f95 AM |
7352 | /* This is a hack. There should be a better way to handle this. |
7353 | This covers for the fact that bfd_install_relocation will | |
7354 | subtract the current location (for partial_inplace, PC relative | |
7355 | relocations); see more below. */ | |
252b5132 | 7356 | #ifndef OBJ_AOUT |
718ddfc0 | 7357 | if (IS_ELF |
252b5132 RH |
7358 | #ifdef TE_PE |
7359 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
7360 | #endif | |
7361 | ) | |
7362 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
7363 | #endif | |
7364 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 7365 | if (IS_ELF) |
252b5132 | 7366 | { |
6539b54b | 7367 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 7368 | |
6539b54b | 7369 | if ((sym_seg == seg |
2f66722d | 7370 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 7371 | && sym_seg != absolute_section)) |
af65af87 | 7372 | && !generic_force_reloc (fixP)) |
2f66722d AM |
7373 | { |
7374 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
7375 | bfd_install_relocation subtracts them out again. I think |
7376 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
7377 | it. FIXME. */ |
7378 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
7379 | } | |
252b5132 RH |
7380 | } |
7381 | #endif | |
7382 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
7383 | /* For some reason, the PE format does not store a |
7384 | section address offset for a PC relative symbol. */ | |
7385 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 7386 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
7387 | value += md_pcrel_from (fixP); |
7388 | #endif | |
7389 | } | |
fbeb56a4 DK |
7390 | #if defined (OBJ_COFF) && defined (TE_PE) |
7391 | if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
7392 | { | |
7393 | value -= S_GET_VALUE (fixP->fx_addsy); | |
7394 | } | |
7395 | #endif | |
252b5132 RH |
7396 | |
7397 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 7398 | and we must not disappoint it. */ |
252b5132 | 7399 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 7400 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
7401 | switch (fixP->fx_r_type) |
7402 | { | |
7403 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 7404 | case BFD_RELOC_X86_64_PLT32: |
47926f60 KH |
7405 | /* Make the jump instruction point to the address of the operand. At |
7406 | runtime we merely add the offset to the actual PLT entry. */ | |
7407 | value = -4; | |
7408 | break; | |
31312f95 | 7409 | |
13ae64f3 JJ |
7410 | case BFD_RELOC_386_TLS_GD: |
7411 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 7412 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
7413 | case BFD_RELOC_386_TLS_IE: |
7414 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 7415 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
7416 | case BFD_RELOC_X86_64_TLSGD: |
7417 | case BFD_RELOC_X86_64_TLSLD: | |
7418 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 7419 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
7420 | value = 0; /* Fully resolved at runtime. No addend. */ |
7421 | /* Fallthrough */ | |
7422 | case BFD_RELOC_386_TLS_LE: | |
7423 | case BFD_RELOC_386_TLS_LDO_32: | |
7424 | case BFD_RELOC_386_TLS_LE_32: | |
7425 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 7426 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 7427 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 7428 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
7429 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
7430 | break; | |
7431 | ||
67a4f2b7 AO |
7432 | case BFD_RELOC_386_TLS_DESC_CALL: |
7433 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
7434 | value = 0; /* Fully resolved at runtime. No addend. */ | |
7435 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
7436 | fixP->fx_done = 0; | |
7437 | return; | |
7438 | ||
00f7efb6 JJ |
7439 | case BFD_RELOC_386_GOT32: |
7440 | case BFD_RELOC_X86_64_GOT32: | |
47926f60 KH |
7441 | value = 0; /* Fully resolved at runtime. No addend. */ |
7442 | break; | |
47926f60 KH |
7443 | |
7444 | case BFD_RELOC_VTABLE_INHERIT: | |
7445 | case BFD_RELOC_VTABLE_ENTRY: | |
7446 | fixP->fx_done = 0; | |
94f592af | 7447 | return; |
47926f60 KH |
7448 | |
7449 | default: | |
7450 | break; | |
7451 | } | |
7452 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 7453 | *valP = value; |
f86103b7 | 7454 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 7455 | |
3e73aa7c | 7456 | /* Are we finished with this relocation now? */ |
c6682705 | 7457 | if (fixP->fx_addsy == NULL) |
3e73aa7c | 7458 | fixP->fx_done = 1; |
fbeb56a4 DK |
7459 | #if defined (OBJ_COFF) && defined (TE_PE) |
7460 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
7461 | { | |
7462 | fixP->fx_done = 0; | |
7463 | /* Remember value for tc_gen_reloc. */ | |
7464 | fixP->fx_addnumber = value; | |
7465 | /* Clear out the frag for now. */ | |
7466 | value = 0; | |
7467 | } | |
7468 | #endif | |
3e73aa7c JH |
7469 | else if (use_rela_relocations) |
7470 | { | |
7471 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
7472 | /* Remember value for tc_gen_reloc. */ |
7473 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
7474 | value = 0; |
7475 | } | |
f86103b7 | 7476 | |
94f592af | 7477 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 7478 | } |
252b5132 | 7479 | \f |
252b5132 | 7480 | char * |
499ac353 | 7481 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 7482 | { |
499ac353 NC |
7483 | /* This outputs the LITTLENUMs in REVERSE order; |
7484 | in accord with the bigendian 386. */ | |
7485 | return ieee_md_atof (type, litP, sizeP, FALSE); | |
252b5132 RH |
7486 | } |
7487 | \f | |
2d545b82 | 7488 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 7489 | |
252b5132 | 7490 | static char * |
e3bb37b5 | 7491 | output_invalid (int c) |
252b5132 | 7492 | { |
3882b010 | 7493 | if (ISPRINT (c)) |
f9f21a03 L |
7494 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
7495 | "'%c'", c); | |
252b5132 | 7496 | else |
f9f21a03 | 7497 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 7498 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
7499 | return output_invalid_buf; |
7500 | } | |
7501 | ||
af6bdddf | 7502 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
7503 | |
7504 | static const reg_entry * | |
4d1bb795 | 7505 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 7506 | { |
af6bdddf AM |
7507 | char *s = reg_string; |
7508 | char *p; | |
252b5132 RH |
7509 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
7510 | const reg_entry *r; | |
7511 | ||
7512 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
7513 | if (*s == REGISTER_PREFIX) | |
7514 | ++s; | |
7515 | ||
7516 | if (is_space_char (*s)) | |
7517 | ++s; | |
7518 | ||
7519 | p = reg_name_given; | |
af6bdddf | 7520 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
7521 | { |
7522 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
7523 | return (const reg_entry *) NULL; |
7524 | s++; | |
252b5132 RH |
7525 | } |
7526 | ||
6588847e DN |
7527 | /* For naked regs, make sure that we are not dealing with an identifier. |
7528 | This prevents confusing an identifier like `eax_var' with register | |
7529 | `eax'. */ | |
7530 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
7531 | return (const reg_entry *) NULL; | |
7532 | ||
af6bdddf | 7533 | *end_op = s; |
252b5132 RH |
7534 | |
7535 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
7536 | ||
5f47d35b | 7537 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 7538 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 7539 | { |
5f47d35b AM |
7540 | if (is_space_char (*s)) |
7541 | ++s; | |
7542 | if (*s == '(') | |
7543 | { | |
af6bdddf | 7544 | ++s; |
5f47d35b AM |
7545 | if (is_space_char (*s)) |
7546 | ++s; | |
7547 | if (*s >= '0' && *s <= '7') | |
7548 | { | |
db557034 | 7549 | int fpr = *s - '0'; |
af6bdddf | 7550 | ++s; |
5f47d35b AM |
7551 | if (is_space_char (*s)) |
7552 | ++s; | |
7553 | if (*s == ')') | |
7554 | { | |
7555 | *end_op = s + 1; | |
db557034 AM |
7556 | r = hash_find (reg_hash, "st(0)"); |
7557 | know (r); | |
7558 | return r + fpr; | |
5f47d35b | 7559 | } |
5f47d35b | 7560 | } |
47926f60 | 7561 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
7562 | return (const reg_entry *) NULL; |
7563 | } | |
7564 | } | |
7565 | ||
a60de03c JB |
7566 | if (r == NULL || allow_pseudo_reg) |
7567 | return r; | |
7568 | ||
0dfbf9d7 | 7569 | if (operand_type_all_zero (&r->reg_type)) |
a60de03c JB |
7570 | return (const reg_entry *) NULL; |
7571 | ||
192dc9c6 JB |
7572 | if ((r->reg_type.bitfield.reg32 |
7573 | || r->reg_type.bitfield.sreg3 | |
7574 | || r->reg_type.bitfield.control | |
7575 | || r->reg_type.bitfield.debug | |
7576 | || r->reg_type.bitfield.test) | |
7577 | && !cpu_arch_flags.bitfield.cpui386) | |
7578 | return (const reg_entry *) NULL; | |
7579 | ||
309d3373 JB |
7580 | if (r->reg_type.bitfield.floatreg |
7581 | && !cpu_arch_flags.bitfield.cpu8087 | |
7582 | && !cpu_arch_flags.bitfield.cpu287 | |
7583 | && !cpu_arch_flags.bitfield.cpu387) | |
7584 | return (const reg_entry *) NULL; | |
7585 | ||
192dc9c6 JB |
7586 | if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx) |
7587 | return (const reg_entry *) NULL; | |
7588 | ||
7589 | if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse) | |
7590 | return (const reg_entry *) NULL; | |
7591 | ||
40f12533 L |
7592 | if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx) |
7593 | return (const reg_entry *) NULL; | |
7594 | ||
db51cc60 | 7595 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ |
a60de03c | 7596 | if (!allow_index_reg |
db51cc60 L |
7597 | && (r->reg_num == RegEiz || r->reg_num == RegRiz)) |
7598 | return (const reg_entry *) NULL; | |
7599 | ||
a60de03c JB |
7600 | if (((r->reg_flags & (RegRex64 | RegRex)) |
7601 | || r->reg_type.bitfield.reg64) | |
40fb9820 | 7602 | && (!cpu_arch_flags.bitfield.cpulm |
0dfbf9d7 | 7603 | || !operand_type_equal (&r->reg_type, &control)) |
1ae00879 | 7604 | && flag_code != CODE_64BIT) |
20f0a1fc | 7605 | return (const reg_entry *) NULL; |
1ae00879 | 7606 | |
b7240065 JB |
7607 | if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax) |
7608 | return (const reg_entry *) NULL; | |
7609 | ||
252b5132 RH |
7610 | return r; |
7611 | } | |
4d1bb795 JB |
7612 | |
7613 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
7614 | ||
7615 | static const reg_entry * | |
7616 | parse_register (char *reg_string, char **end_op) | |
7617 | { | |
7618 | const reg_entry *r; | |
7619 | ||
7620 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
7621 | r = parse_real_register (reg_string, end_op); | |
7622 | else | |
7623 | r = NULL; | |
7624 | if (!r) | |
7625 | { | |
7626 | char *save = input_line_pointer; | |
7627 | char c; | |
7628 | symbolS *symbolP; | |
7629 | ||
7630 | input_line_pointer = reg_string; | |
7631 | c = get_symbol_end (); | |
7632 | symbolP = symbol_find (reg_string); | |
7633 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
7634 | { | |
7635 | const expressionS *e = symbol_get_value_expression (symbolP); | |
7636 | ||
7637 | know (e->X_op == O_register); | |
4eed87de | 7638 | know (e->X_add_number >= 0 |
c3fe08fa | 7639 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 JB |
7640 | r = i386_regtab + e->X_add_number; |
7641 | *end_op = input_line_pointer; | |
7642 | } | |
7643 | *input_line_pointer = c; | |
7644 | input_line_pointer = save; | |
7645 | } | |
7646 | return r; | |
7647 | } | |
7648 | ||
7649 | int | |
7650 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
7651 | { | |
7652 | const reg_entry *r; | |
7653 | char *end = input_line_pointer; | |
7654 | ||
7655 | *end = *nextcharP; | |
7656 | r = parse_register (name, &input_line_pointer); | |
7657 | if (r && end <= input_line_pointer) | |
7658 | { | |
7659 | *nextcharP = *input_line_pointer; | |
7660 | *input_line_pointer = 0; | |
7661 | e->X_op = O_register; | |
7662 | e->X_add_number = r - i386_regtab; | |
7663 | return 1; | |
7664 | } | |
7665 | input_line_pointer = end; | |
7666 | *end = 0; | |
ee86248c | 7667 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
7668 | } |
7669 | ||
7670 | void | |
7671 | md_operand (expressionS *e) | |
7672 | { | |
ee86248c JB |
7673 | char *end; |
7674 | const reg_entry *r; | |
4d1bb795 | 7675 | |
ee86248c JB |
7676 | switch (*input_line_pointer) |
7677 | { | |
7678 | case REGISTER_PREFIX: | |
7679 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
7680 | if (r) |
7681 | { | |
7682 | e->X_op = O_register; | |
7683 | e->X_add_number = r - i386_regtab; | |
7684 | input_line_pointer = end; | |
7685 | } | |
ee86248c JB |
7686 | break; |
7687 | ||
7688 | case '[': | |
9c2799c2 | 7689 | gas_assert (intel_syntax); |
ee86248c JB |
7690 | end = input_line_pointer++; |
7691 | expression (e); | |
7692 | if (*input_line_pointer == ']') | |
7693 | { | |
7694 | ++input_line_pointer; | |
7695 | e->X_op_symbol = make_expr_symbol (e); | |
7696 | e->X_add_symbol = NULL; | |
7697 | e->X_add_number = 0; | |
7698 | e->X_op = O_index; | |
7699 | } | |
7700 | else | |
7701 | { | |
7702 | e->X_op = O_absent; | |
7703 | input_line_pointer = end; | |
7704 | } | |
7705 | break; | |
4d1bb795 JB |
7706 | } |
7707 | } | |
7708 | ||
252b5132 | 7709 | \f |
4cc782b5 | 7710 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
12b55ccc | 7711 | const char *md_shortopts = "kVQ:sqn"; |
252b5132 | 7712 | #else |
12b55ccc | 7713 | const char *md_shortopts = "qn"; |
252b5132 | 7714 | #endif |
6e0b89ee | 7715 | |
3e73aa7c | 7716 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
7717 | #define OPTION_64 (OPTION_MD_BASE + 1) |
7718 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
7719 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
7720 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
7721 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
7722 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
7723 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
7724 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
7725 | #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9) | |
c0f3af97 | 7726 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 7727 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
b3b91714 | 7728 | |
99ad8390 NC |
7729 | struct option md_longopts[] = |
7730 | { | |
3e73aa7c | 7731 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 L |
7732 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
7733 | || defined (TE_PE) || defined (TE_PEP)) | |
3e73aa7c | 7734 | {"64", no_argument, NULL, OPTION_64}, |
6e0b89ee | 7735 | #endif |
b3b91714 | 7736 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
7737 | {"march", required_argument, NULL, OPTION_MARCH}, |
7738 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
7739 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
7740 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
7741 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
7742 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
7743 | {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC}, | |
c0f3af97 | 7744 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
daf50ae7 | 7745 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
252b5132 RH |
7746 | {NULL, no_argument, NULL, 0} |
7747 | }; | |
7748 | size_t md_longopts_size = sizeof (md_longopts); | |
7749 | ||
7750 | int | |
9103f4f4 | 7751 | md_parse_option (int c, char *arg) |
252b5132 | 7752 | { |
9103f4f4 | 7753 | unsigned int i; |
6305a203 | 7754 | char *arch, *next; |
9103f4f4 | 7755 | |
252b5132 RH |
7756 | switch (c) |
7757 | { | |
12b55ccc L |
7758 | case 'n': |
7759 | optimize_align_code = 0; | |
7760 | break; | |
7761 | ||
a38cf1db AM |
7762 | case 'q': |
7763 | quiet_warnings = 1; | |
252b5132 RH |
7764 | break; |
7765 | ||
7766 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
7767 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
7768 | should be emitted or not. FIXME: Not implemented. */ | |
7769 | case 'Q': | |
252b5132 RH |
7770 | break; |
7771 | ||
7772 | /* -V: SVR4 argument to print version ID. */ | |
7773 | case 'V': | |
7774 | print_version_id (); | |
7775 | break; | |
7776 | ||
a38cf1db AM |
7777 | /* -k: Ignore for FreeBSD compatibility. */ |
7778 | case 'k': | |
252b5132 | 7779 | break; |
4cc782b5 ILT |
7780 | |
7781 | case 's': | |
7782 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 7783 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 7784 | break; |
99ad8390 | 7785 | #endif |
321098a5 L |
7786 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
7787 | || defined (TE_PE) || defined (TE_PEP)) | |
3e73aa7c JH |
7788 | case OPTION_64: |
7789 | { | |
7790 | const char **list, **l; | |
7791 | ||
3e73aa7c JH |
7792 | list = bfd_target_list (); |
7793 | for (l = list; *l != NULL; l++) | |
8620418b | 7794 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
99ad8390 NC |
7795 | || strcmp (*l, "coff-x86-64") == 0 |
7796 | || strcmp (*l, "pe-x86-64") == 0 | |
7797 | || strcmp (*l, "pei-x86-64") == 0) | |
6e0b89ee AM |
7798 | { |
7799 | default_arch = "x86_64"; | |
7800 | break; | |
7801 | } | |
3e73aa7c | 7802 | if (*l == NULL) |
6e0b89ee | 7803 | as_fatal (_("No compiled in support for x86_64")); |
3e73aa7c JH |
7804 | free (list); |
7805 | } | |
7806 | break; | |
7807 | #endif | |
252b5132 | 7808 | |
6e0b89ee AM |
7809 | case OPTION_32: |
7810 | default_arch = "i386"; | |
7811 | break; | |
7812 | ||
b3b91714 AM |
7813 | case OPTION_DIVIDE: |
7814 | #ifdef SVR4_COMMENT_CHARS | |
7815 | { | |
7816 | char *n, *t; | |
7817 | const char *s; | |
7818 | ||
7819 | n = (char *) xmalloc (strlen (i386_comment_chars) + 1); | |
7820 | t = n; | |
7821 | for (s = i386_comment_chars; *s != '\0'; s++) | |
7822 | if (*s != '/') | |
7823 | *t++ = *s; | |
7824 | *t = '\0'; | |
7825 | i386_comment_chars = n; | |
7826 | } | |
7827 | #endif | |
7828 | break; | |
7829 | ||
9103f4f4 | 7830 | case OPTION_MARCH: |
6305a203 L |
7831 | arch = xstrdup (arg); |
7832 | do | |
9103f4f4 | 7833 | { |
6305a203 L |
7834 | if (*arch == '.') |
7835 | as_fatal (_("Invalid -march= option: `%s'"), arg); | |
7836 | next = strchr (arch, '+'); | |
7837 | if (next) | |
7838 | *next++ = '\0'; | |
7839 | for (i = 0; i < ARRAY_SIZE (cpu_arch); i++) | |
9103f4f4 | 7840 | { |
6305a203 | 7841 | if (strcmp (arch, cpu_arch [i].name) == 0) |
ccc9c027 | 7842 | { |
6305a203 L |
7843 | /* Processor. */ |
7844 | cpu_arch_name = cpu_arch[i].name; | |
7845 | cpu_sub_arch_name = NULL; | |
7846 | cpu_arch_flags = cpu_arch[i].flags; | |
7847 | cpu_arch_isa = cpu_arch[i].type; | |
7848 | cpu_arch_isa_flags = cpu_arch[i].flags; | |
7849 | if (!cpu_arch_tune_set) | |
7850 | { | |
7851 | cpu_arch_tune = cpu_arch_isa; | |
7852 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
7853 | } | |
7854 | break; | |
7855 | } | |
7856 | else if (*cpu_arch [i].name == '.' | |
7857 | && strcmp (arch, cpu_arch [i].name + 1) == 0) | |
7858 | { | |
7859 | /* ISA entension. */ | |
7860 | i386_cpu_flags flags; | |
309d3373 JB |
7861 | |
7862 | if (strncmp (arch, "no", 2)) | |
7863 | flags = cpu_flags_or (cpu_arch_flags, | |
7864 | cpu_arch[i].flags); | |
7865 | else | |
7866 | flags = cpu_flags_and_not (cpu_arch_flags, | |
7867 | cpu_arch[i].flags); | |
0dfbf9d7 | 7868 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
6305a203 L |
7869 | { |
7870 | if (cpu_sub_arch_name) | |
7871 | { | |
7872 | char *name = cpu_sub_arch_name; | |
7873 | cpu_sub_arch_name = concat (name, | |
7874 | cpu_arch[i].name, | |
1bf57e9f | 7875 | (const char *) NULL); |
6305a203 L |
7876 | free (name); |
7877 | } | |
7878 | else | |
7879 | cpu_sub_arch_name = xstrdup (cpu_arch[i].name); | |
7880 | cpu_arch_flags = flags; | |
7881 | } | |
7882 | break; | |
ccc9c027 | 7883 | } |
9103f4f4 | 7884 | } |
6305a203 L |
7885 | |
7886 | if (i >= ARRAY_SIZE (cpu_arch)) | |
7887 | as_fatal (_("Invalid -march= option: `%s'"), arg); | |
7888 | ||
7889 | arch = next; | |
9103f4f4 | 7890 | } |
6305a203 | 7891 | while (next != NULL ); |
9103f4f4 L |
7892 | break; |
7893 | ||
7894 | case OPTION_MTUNE: | |
7895 | if (*arg == '.') | |
7896 | as_fatal (_("Invalid -mtune= option: `%s'"), arg); | |
7897 | for (i = 0; i < ARRAY_SIZE (cpu_arch); i++) | |
7898 | { | |
7899 | if (strcmp (arg, cpu_arch [i].name) == 0) | |
7900 | { | |
ccc9c027 | 7901 | cpu_arch_tune_set = 1; |
9103f4f4 L |
7902 | cpu_arch_tune = cpu_arch [i].type; |
7903 | cpu_arch_tune_flags = cpu_arch[i].flags; | |
7904 | break; | |
7905 | } | |
7906 | } | |
7907 | if (i >= ARRAY_SIZE (cpu_arch)) | |
7908 | as_fatal (_("Invalid -mtune= option: `%s'"), arg); | |
7909 | break; | |
7910 | ||
1efbbeb4 L |
7911 | case OPTION_MMNEMONIC: |
7912 | if (strcasecmp (arg, "att") == 0) | |
7913 | intel_mnemonic = 0; | |
7914 | else if (strcasecmp (arg, "intel") == 0) | |
7915 | intel_mnemonic = 1; | |
7916 | else | |
7917 | as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg); | |
7918 | break; | |
7919 | ||
7920 | case OPTION_MSYNTAX: | |
7921 | if (strcasecmp (arg, "att") == 0) | |
7922 | intel_syntax = 0; | |
7923 | else if (strcasecmp (arg, "intel") == 0) | |
7924 | intel_syntax = 1; | |
7925 | else | |
7926 | as_fatal (_("Invalid -msyntax= option: `%s'"), arg); | |
7927 | break; | |
7928 | ||
7929 | case OPTION_MINDEX_REG: | |
7930 | allow_index_reg = 1; | |
7931 | break; | |
7932 | ||
7933 | case OPTION_MNAKED_REG: | |
7934 | allow_naked_reg = 1; | |
7935 | break; | |
7936 | ||
7937 | case OPTION_MOLD_GCC: | |
7938 | old_gcc = 1; | |
1efbbeb4 L |
7939 | break; |
7940 | ||
c0f3af97 L |
7941 | case OPTION_MSSE2AVX: |
7942 | sse2avx = 1; | |
7943 | break; | |
7944 | ||
daf50ae7 L |
7945 | case OPTION_MSSE_CHECK: |
7946 | if (strcasecmp (arg, "error") == 0) | |
7947 | sse_check = sse_check_error; | |
7948 | else if (strcasecmp (arg, "warning") == 0) | |
7949 | sse_check = sse_check_warning; | |
7950 | else if (strcasecmp (arg, "none") == 0) | |
7951 | sse_check = sse_check_none; | |
7952 | else | |
7953 | as_fatal (_("Invalid -msse-check= option: `%s'"), arg); | |
7954 | break; | |
7955 | ||
252b5132 RH |
7956 | default: |
7957 | return 0; | |
7958 | } | |
7959 | return 1; | |
7960 | } | |
7961 | ||
7962 | void | |
7963 | md_show_usage (stream) | |
7964 | FILE *stream; | |
7965 | { | |
4cc782b5 ILT |
7966 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
7967 | fprintf (stream, _("\ | |
a38cf1db AM |
7968 | -Q ignored\n\ |
7969 | -V print assembler version number\n\ | |
b3b91714 AM |
7970 | -k ignored\n")); |
7971 | #endif | |
7972 | fprintf (stream, _("\ | |
12b55ccc | 7973 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
7974 | -q quieten some warnings\n")); |
7975 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
7976 | fprintf (stream, _("\ | |
a38cf1db | 7977 | -s ignored\n")); |
b3b91714 | 7978 | #endif |
321098a5 L |
7979 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
7980 | || defined (TE_PE) || defined (TE_PEP)) | |
751d281c L |
7981 | fprintf (stream, _("\ |
7982 | --32/--64 generate 32bit/64bit code\n")); | |
7983 | #endif | |
b3b91714 AM |
7984 | #ifdef SVR4_COMMENT_CHARS |
7985 | fprintf (stream, _("\ | |
7986 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
7987 | #else |
7988 | fprintf (stream, _("\ | |
b3b91714 | 7989 | --divide ignored\n")); |
4cc782b5 | 7990 | #endif |
9103f4f4 | 7991 | fprintf (stream, _("\ |
6305a203 L |
7992 | -march=CPU[,+EXTENSION...]\n\ |
7993 | generate code for CPU and EXTENSION, CPU is one of:\n\ | |
2cb4f3d5 L |
7994 | i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\ |
7995 | pentiumii, pentiumiii, pentium4, prescott, nocona,\n\ | |
8a9036a4 L |
7996 | core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\ |
7997 | amdfam10, generic32, generic64\n\ | |
599121aa | 7998 | EXTENSION is combination of:\n\ |
309d3373 JB |
7999 | 8087, 287, 387, no87, mmx, nommx, sse, sse2, sse3,\n\ |
8000 | ssse3, sse4.1, sse4.2, sse4, nosse, avx, noavx,\n\ | |
8001 | vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\ | |
bd5295b2 | 8002 | clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\ |
922d8de8 | 8003 | svme, abm, padlock, fma4\n")); |
6305a203 | 8004 | fprintf (stream, _("\ |
2cb4f3d5 L |
8005 | -mtune=CPU optimize for CPU, CPU is one of:\n\ |
8006 | i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\ | |
8007 | pentiumii, pentiumiii, pentium4, prescott, nocona,\n\ | |
8a9036a4 L |
8008 | core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\ |
8009 | amdfam10, generic32, generic64\n")); | |
ba104c83 | 8010 | fprintf (stream, _("\ |
c0f3af97 L |
8011 | -msse2avx encode SSE instructions with VEX prefix\n")); |
8012 | fprintf (stream, _("\ | |
daf50ae7 L |
8013 | -msse-check=[none|error|warning]\n\ |
8014 | check SSE instructions\n")); | |
8015 | fprintf (stream, _("\ | |
ba104c83 L |
8016 | -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n")); |
8017 | fprintf (stream, _("\ | |
8018 | -msyntax=[att|intel] use AT&T/Intel syntax\n")); | |
8019 | fprintf (stream, _("\ | |
8020 | -mindex-reg support pseudo index registers\n")); | |
8021 | fprintf (stream, _("\ | |
8022 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
8023 | fprintf (stream, _("\ | |
8024 | -mold-gcc support old (<= 2.8.1) versions of gcc\n")); | |
252b5132 RH |
8025 | } |
8026 | ||
3e73aa7c | 8027 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 8028 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 8029 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
8030 | |
8031 | /* Pick the target format to use. */ | |
8032 | ||
47926f60 | 8033 | const char * |
e3bb37b5 | 8034 | i386_target_format (void) |
252b5132 | 8035 | { |
3e73aa7c | 8036 | if (!strcmp (default_arch, "x86_64")) |
9103f4f4 L |
8037 | { |
8038 | set_code_flag (CODE_64BIT); | |
0dfbf9d7 | 8039 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) |
40fb9820 L |
8040 | { |
8041 | cpu_arch_isa_flags.bitfield.cpui186 = 1; | |
8042 | cpu_arch_isa_flags.bitfield.cpui286 = 1; | |
8043 | cpu_arch_isa_flags.bitfield.cpui386 = 1; | |
8044 | cpu_arch_isa_flags.bitfield.cpui486 = 1; | |
8045 | cpu_arch_isa_flags.bitfield.cpui586 = 1; | |
8046 | cpu_arch_isa_flags.bitfield.cpui686 = 1; | |
bd5295b2 | 8047 | cpu_arch_isa_flags.bitfield.cpuclflush = 1; |
40fb9820 | 8048 | cpu_arch_isa_flags.bitfield.cpummx= 1; |
40fb9820 L |
8049 | cpu_arch_isa_flags.bitfield.cpusse = 1; |
8050 | cpu_arch_isa_flags.bitfield.cpusse2 = 1; | |
711eedef | 8051 | cpu_arch_isa_flags.bitfield.cpulm = 1; |
40fb9820 | 8052 | } |
0dfbf9d7 | 8053 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) |
40fb9820 L |
8054 | { |
8055 | cpu_arch_tune_flags.bitfield.cpui186 = 1; | |
8056 | cpu_arch_tune_flags.bitfield.cpui286 = 1; | |
8057 | cpu_arch_tune_flags.bitfield.cpui386 = 1; | |
8058 | cpu_arch_tune_flags.bitfield.cpui486 = 1; | |
8059 | cpu_arch_tune_flags.bitfield.cpui586 = 1; | |
8060 | cpu_arch_tune_flags.bitfield.cpui686 = 1; | |
bd5295b2 | 8061 | cpu_arch_tune_flags.bitfield.cpuclflush = 1; |
40fb9820 | 8062 | cpu_arch_tune_flags.bitfield.cpummx= 1; |
40fb9820 L |
8063 | cpu_arch_tune_flags.bitfield.cpusse = 1; |
8064 | cpu_arch_tune_flags.bitfield.cpusse2 = 1; | |
8065 | } | |
9103f4f4 | 8066 | } |
3e73aa7c | 8067 | else if (!strcmp (default_arch, "i386")) |
9103f4f4 L |
8068 | { |
8069 | set_code_flag (CODE_32BIT); | |
0dfbf9d7 | 8070 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) |
40fb9820 L |
8071 | { |
8072 | cpu_arch_isa_flags.bitfield.cpui186 = 1; | |
8073 | cpu_arch_isa_flags.bitfield.cpui286 = 1; | |
8074 | cpu_arch_isa_flags.bitfield.cpui386 = 1; | |
8075 | } | |
0dfbf9d7 | 8076 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) |
40fb9820 L |
8077 | { |
8078 | cpu_arch_tune_flags.bitfield.cpui186 = 1; | |
8079 | cpu_arch_tune_flags.bitfield.cpui286 = 1; | |
8080 | cpu_arch_tune_flags.bitfield.cpui386 = 1; | |
8081 | } | |
9103f4f4 | 8082 | } |
3e73aa7c JH |
8083 | else |
8084 | as_fatal (_("Unknown architecture")); | |
252b5132 RH |
8085 | switch (OUTPUT_FLAVOR) |
8086 | { | |
321098a5 | 8087 | #if defined (TE_PE) || defined (TE_PEP) |
872ce6ff | 8088 | case bfd_target_coff_flavour: |
321098a5 | 8089 | return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386"; |
872ce6ff | 8090 | #endif |
4c63da97 AM |
8091 | #ifdef OBJ_MAYBE_AOUT |
8092 | case bfd_target_aout_flavour: | |
47926f60 | 8093 | return AOUT_TARGET_FORMAT; |
4c63da97 | 8094 | #endif |
0561d57c JK |
8095 | #ifdef TE_GO32 |
8096 | case bfd_target_coff_flavour: | |
8097 | return "coff-go32"; | |
8098 | #elif defined (OBJ_MAYBE_COFF) | |
252b5132 RH |
8099 | case bfd_target_coff_flavour: |
8100 | return "coff-i386"; | |
4c63da97 | 8101 | #endif |
3e73aa7c | 8102 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 8103 | case bfd_target_elf_flavour: |
3e73aa7c | 8104 | { |
e5cb08ac | 8105 | if (flag_code == CODE_64BIT) |
4fa24527 JB |
8106 | { |
8107 | object_64bit = 1; | |
8108 | use_rela_relocations = 1; | |
8109 | } | |
3632d14b | 8110 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 L |
8111 | { |
8112 | if (flag_code != CODE_64BIT) | |
8113 | as_fatal (_("Intel L1OM is 64bit only")); | |
8114 | return ELF_TARGET_L1OM_FORMAT; | |
8115 | } | |
8116 | else | |
8117 | return (flag_code == CODE_64BIT | |
8118 | ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT); | |
3e73aa7c | 8119 | } |
e57f8c65 TG |
8120 | #endif |
8121 | #if defined (OBJ_MACH_O) | |
8122 | case bfd_target_mach_o_flavour: | |
8123 | return flag_code == CODE_64BIT ? "mach-o-x86-64" : "mach-o-i386"; | |
4c63da97 | 8124 | #endif |
252b5132 RH |
8125 | default: |
8126 | abort (); | |
8127 | return NULL; | |
8128 | } | |
8129 | } | |
8130 | ||
47926f60 | 8131 | #endif /* OBJ_MAYBE_ more than one */ |
a847613f AM |
8132 | |
8133 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) | |
e3bb37b5 L |
8134 | void |
8135 | i386_elf_emit_arch_note (void) | |
a847613f | 8136 | { |
718ddfc0 | 8137 | if (IS_ELF && cpu_arch_name != NULL) |
a847613f AM |
8138 | { |
8139 | char *p; | |
8140 | asection *seg = now_seg; | |
8141 | subsegT subseg = now_subseg; | |
8142 | Elf_Internal_Note i_note; | |
8143 | Elf_External_Note e_note; | |
8144 | asection *note_secp; | |
8145 | int len; | |
8146 | ||
8147 | /* Create the .note section. */ | |
8148 | note_secp = subseg_new (".note", 0); | |
8149 | bfd_set_section_flags (stdoutput, | |
8150 | note_secp, | |
8151 | SEC_HAS_CONTENTS | SEC_READONLY); | |
8152 | ||
8153 | /* Process the arch string. */ | |
8154 | len = strlen (cpu_arch_name); | |
8155 | ||
8156 | i_note.namesz = len + 1; | |
8157 | i_note.descsz = 0; | |
8158 | i_note.type = NT_ARCH; | |
8159 | p = frag_more (sizeof (e_note.namesz)); | |
8160 | md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz)); | |
8161 | p = frag_more (sizeof (e_note.descsz)); | |
8162 | md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz)); | |
8163 | p = frag_more (sizeof (e_note.type)); | |
8164 | md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type)); | |
8165 | p = frag_more (len + 1); | |
8166 | strcpy (p, cpu_arch_name); | |
8167 | ||
8168 | frag_align (2, 0, 0); | |
8169 | ||
8170 | subseg_set (seg, subseg); | |
8171 | } | |
8172 | } | |
8173 | #endif | |
252b5132 | 8174 | \f |
252b5132 RH |
8175 | symbolS * |
8176 | md_undefined_symbol (name) | |
8177 | char *name; | |
8178 | { | |
18dc2407 ILT |
8179 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
8180 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
8181 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
8182 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
8183 | { |
8184 | if (!GOT_symbol) | |
8185 | { | |
8186 | if (symbol_find (name)) | |
8187 | as_bad (_("GOT already in symbol table")); | |
8188 | GOT_symbol = symbol_new (name, undefined_section, | |
8189 | (valueT) 0, &zero_address_frag); | |
8190 | }; | |
8191 | return GOT_symbol; | |
8192 | } | |
252b5132 RH |
8193 | return 0; |
8194 | } | |
8195 | ||
8196 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 8197 | |
252b5132 RH |
8198 | valueT |
8199 | md_section_align (segment, size) | |
ab9da554 | 8200 | segT segment ATTRIBUTE_UNUSED; |
252b5132 RH |
8201 | valueT size; |
8202 | { | |
4c63da97 AM |
8203 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
8204 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
8205 | { | |
8206 | /* For a.out, force the section size to be aligned. If we don't do | |
8207 | this, BFD will align it for us, but it will not write out the | |
8208 | final bytes of the section. This may be a bug in BFD, but it is | |
8209 | easier to fix it here since that is how the other a.out targets | |
8210 | work. */ | |
8211 | int align; | |
8212 | ||
8213 | align = bfd_get_section_alignment (stdoutput, segment); | |
8214 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
8215 | } | |
252b5132 RH |
8216 | #endif |
8217 | ||
8218 | return size; | |
8219 | } | |
8220 | ||
8221 | /* On the i386, PC-relative offsets are relative to the start of the | |
8222 | next instruction. That is, the address of the offset, plus its | |
8223 | size, since the offset is always the last part of the insn. */ | |
8224 | ||
8225 | long | |
e3bb37b5 | 8226 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
8227 | { |
8228 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
8229 | } | |
8230 | ||
8231 | #ifndef I386COFF | |
8232 | ||
8233 | static void | |
e3bb37b5 | 8234 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 8235 | { |
29b0f896 | 8236 | int temp; |
252b5132 | 8237 | |
8a75718c JB |
8238 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8239 | if (IS_ELF) | |
8240 | obj_elf_section_change_hook (); | |
8241 | #endif | |
252b5132 RH |
8242 | temp = get_absolute_expression (); |
8243 | subseg_set (bss_section, (subsegT) temp); | |
8244 | demand_empty_rest_of_line (); | |
8245 | } | |
8246 | ||
8247 | #endif | |
8248 | ||
252b5132 | 8249 | void |
e3bb37b5 | 8250 | i386_validate_fix (fixS *fixp) |
252b5132 RH |
8251 | { |
8252 | if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) | |
8253 | { | |
23df1078 JH |
8254 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
8255 | { | |
4fa24527 | 8256 | if (!object_64bit) |
23df1078 JH |
8257 | abort (); |
8258 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
8259 | } | |
8260 | else | |
8261 | { | |
4fa24527 | 8262 | if (!object_64bit) |
d6ab8113 JB |
8263 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; |
8264 | else | |
8265 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
23df1078 | 8266 | } |
252b5132 RH |
8267 | fixp->fx_subsy = 0; |
8268 | } | |
8269 | } | |
8270 | ||
252b5132 RH |
8271 | arelent * |
8272 | tc_gen_reloc (section, fixp) | |
ab9da554 | 8273 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
8274 | fixS *fixp; |
8275 | { | |
8276 | arelent *rel; | |
8277 | bfd_reloc_code_real_type code; | |
8278 | ||
8279 | switch (fixp->fx_r_type) | |
8280 | { | |
3e73aa7c JH |
8281 | case BFD_RELOC_X86_64_PLT32: |
8282 | case BFD_RELOC_X86_64_GOT32: | |
8283 | case BFD_RELOC_X86_64_GOTPCREL: | |
252b5132 RH |
8284 | case BFD_RELOC_386_PLT32: |
8285 | case BFD_RELOC_386_GOT32: | |
8286 | case BFD_RELOC_386_GOTOFF: | |
8287 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
8288 | case BFD_RELOC_386_TLS_GD: |
8289 | case BFD_RELOC_386_TLS_LDM: | |
8290 | case BFD_RELOC_386_TLS_LDO_32: | |
8291 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
8292 | case BFD_RELOC_386_TLS_IE: |
8293 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
8294 | case BFD_RELOC_386_TLS_LE_32: |
8295 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
8296 | case BFD_RELOC_386_TLS_GOTDESC: |
8297 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
8298 | case BFD_RELOC_X86_64_TLSGD: |
8299 | case BFD_RELOC_X86_64_TLSLD: | |
8300 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 8301 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
8302 | case BFD_RELOC_X86_64_GOTTPOFF: |
8303 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
8304 | case BFD_RELOC_X86_64_TPOFF64: |
8305 | case BFD_RELOC_X86_64_GOTOFF64: | |
8306 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
8307 | case BFD_RELOC_X86_64_GOT64: |
8308 | case BFD_RELOC_X86_64_GOTPCREL64: | |
8309 | case BFD_RELOC_X86_64_GOTPC64: | |
8310 | case BFD_RELOC_X86_64_GOTPLT64: | |
8311 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
8312 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
8313 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
8314 | case BFD_RELOC_RVA: |
8315 | case BFD_RELOC_VTABLE_ENTRY: | |
8316 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
8317 | #ifdef TE_PE |
8318 | case BFD_RELOC_32_SECREL: | |
8319 | #endif | |
252b5132 RH |
8320 | code = fixp->fx_r_type; |
8321 | break; | |
dbbaec26 L |
8322 | case BFD_RELOC_X86_64_32S: |
8323 | if (!fixp->fx_pcrel) | |
8324 | { | |
8325 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
8326 | code = fixp->fx_r_type; | |
8327 | break; | |
8328 | } | |
252b5132 | 8329 | default: |
93382f6d | 8330 | if (fixp->fx_pcrel) |
252b5132 | 8331 | { |
93382f6d AM |
8332 | switch (fixp->fx_size) |
8333 | { | |
8334 | default: | |
b091f402 AM |
8335 | as_bad_where (fixp->fx_file, fixp->fx_line, |
8336 | _("can not do %d byte pc-relative relocation"), | |
8337 | fixp->fx_size); | |
93382f6d AM |
8338 | code = BFD_RELOC_32_PCREL; |
8339 | break; | |
8340 | case 1: code = BFD_RELOC_8_PCREL; break; | |
8341 | case 2: code = BFD_RELOC_16_PCREL; break; | |
8342 | case 4: code = BFD_RELOC_32_PCREL; break; | |
d6ab8113 JB |
8343 | #ifdef BFD64 |
8344 | case 8: code = BFD_RELOC_64_PCREL; break; | |
8345 | #endif | |
93382f6d AM |
8346 | } |
8347 | } | |
8348 | else | |
8349 | { | |
8350 | switch (fixp->fx_size) | |
8351 | { | |
8352 | default: | |
b091f402 AM |
8353 | as_bad_where (fixp->fx_file, fixp->fx_line, |
8354 | _("can not do %d byte relocation"), | |
8355 | fixp->fx_size); | |
93382f6d AM |
8356 | code = BFD_RELOC_32; |
8357 | break; | |
8358 | case 1: code = BFD_RELOC_8; break; | |
8359 | case 2: code = BFD_RELOC_16; break; | |
8360 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 8361 | #ifdef BFD64 |
3e73aa7c | 8362 | case 8: code = BFD_RELOC_64; break; |
937149dd | 8363 | #endif |
93382f6d | 8364 | } |
252b5132 RH |
8365 | } |
8366 | break; | |
8367 | } | |
252b5132 | 8368 | |
d182319b JB |
8369 | if ((code == BFD_RELOC_32 |
8370 | || code == BFD_RELOC_32_PCREL | |
8371 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
8372 | && GOT_symbol |
8373 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 8374 | { |
4fa24527 | 8375 | if (!object_64bit) |
d6ab8113 JB |
8376 | code = BFD_RELOC_386_GOTPC; |
8377 | else | |
8378 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 8379 | } |
7b81dfbb AJ |
8380 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
8381 | && GOT_symbol | |
8382 | && fixp->fx_addsy == GOT_symbol) | |
8383 | { | |
8384 | code = BFD_RELOC_X86_64_GOTPC64; | |
8385 | } | |
252b5132 RH |
8386 | |
8387 | rel = (arelent *) xmalloc (sizeof (arelent)); | |
49309057 ILT |
8388 | rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
8389 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
8390 | |
8391 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 8392 | |
3e73aa7c JH |
8393 | if (!use_rela_relocations) |
8394 | { | |
8395 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
8396 | vtable entry to be used in the relocation's section offset. */ | |
8397 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
8398 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
8399 | #if defined (OBJ_COFF) && defined (TE_PE) |
8400 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
8401 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
8402 | else | |
8403 | #endif | |
c6682705 | 8404 | rel->addend = 0; |
3e73aa7c JH |
8405 | } |
8406 | /* Use the rela in 64bit mode. */ | |
252b5132 | 8407 | else |
3e73aa7c | 8408 | { |
062cd5e7 AS |
8409 | if (!fixp->fx_pcrel) |
8410 | rel->addend = fixp->fx_offset; | |
8411 | else | |
8412 | switch (code) | |
8413 | { | |
8414 | case BFD_RELOC_X86_64_PLT32: | |
8415 | case BFD_RELOC_X86_64_GOT32: | |
8416 | case BFD_RELOC_X86_64_GOTPCREL: | |
bffbf940 JJ |
8417 | case BFD_RELOC_X86_64_TLSGD: |
8418 | case BFD_RELOC_X86_64_TLSLD: | |
8419 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
8420 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
8421 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
8422 | rel->addend = fixp->fx_offset - fixp->fx_size; |
8423 | break; | |
8424 | default: | |
8425 | rel->addend = (section->vma | |
8426 | - fixp->fx_size | |
8427 | + fixp->fx_addnumber | |
8428 | + md_pcrel_from (fixp)); | |
8429 | break; | |
8430 | } | |
3e73aa7c JH |
8431 | } |
8432 | ||
252b5132 RH |
8433 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
8434 | if (rel->howto == NULL) | |
8435 | { | |
8436 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 8437 | _("cannot represent relocation type %s"), |
252b5132 RH |
8438 | bfd_get_reloc_code_name (code)); |
8439 | /* Set howto to a garbage value so that we can keep going. */ | |
8440 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 8441 | gas_assert (rel->howto != NULL); |
252b5132 RH |
8442 | } |
8443 | ||
8444 | return rel; | |
8445 | } | |
8446 | ||
ee86248c | 8447 | #include "tc-i386-intel.c" |
54cfded0 | 8448 | |
a60de03c JB |
8449 | void |
8450 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 8451 | { |
a60de03c JB |
8452 | int saved_naked_reg; |
8453 | char saved_register_dot; | |
54cfded0 | 8454 | |
a60de03c JB |
8455 | saved_naked_reg = allow_naked_reg; |
8456 | allow_naked_reg = 1; | |
8457 | saved_register_dot = register_chars['.']; | |
8458 | register_chars['.'] = '.'; | |
8459 | allow_pseudo_reg = 1; | |
8460 | expression_and_evaluate (exp); | |
8461 | allow_pseudo_reg = 0; | |
8462 | register_chars['.'] = saved_register_dot; | |
8463 | allow_naked_reg = saved_naked_reg; | |
8464 | ||
8465 | if (exp->X_op == O_register && exp->X_add_number >= 0) | |
54cfded0 | 8466 | { |
a60de03c JB |
8467 | if ((addressT) exp->X_add_number < i386_regtab_size) |
8468 | { | |
8469 | exp->X_op = O_constant; | |
8470 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
8471 | .dw2_regnum[flag_code >> 1]; | |
8472 | } | |
8473 | else | |
8474 | exp->X_op = O_illegal; | |
54cfded0 | 8475 | } |
54cfded0 AM |
8476 | } |
8477 | ||
8478 | void | |
8479 | tc_x86_frame_initial_instructions (void) | |
8480 | { | |
a60de03c JB |
8481 | static unsigned int sp_regno[2]; |
8482 | ||
8483 | if (!sp_regno[flag_code >> 1]) | |
8484 | { | |
8485 | char *saved_input = input_line_pointer; | |
8486 | char sp[][4] = {"esp", "rsp"}; | |
8487 | expressionS exp; | |
a4447b93 | 8488 | |
a60de03c JB |
8489 | input_line_pointer = sp[flag_code >> 1]; |
8490 | tc_x86_parse_to_dw2regnum (&exp); | |
9c2799c2 | 8491 | gas_assert (exp.X_op == O_constant); |
a60de03c JB |
8492 | sp_regno[flag_code >> 1] = exp.X_add_number; |
8493 | input_line_pointer = saved_input; | |
8494 | } | |
a4447b93 | 8495 | |
a60de03c | 8496 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
a4447b93 | 8497 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); |
54cfded0 | 8498 | } |
d2b2c203 DJ |
8499 | |
8500 | int | |
8501 | i386_elf_section_type (const char *str, size_t len) | |
8502 | { | |
8503 | if (flag_code == CODE_64BIT | |
8504 | && len == sizeof ("unwind") - 1 | |
8505 | && strncmp (str, "unwind", 6) == 0) | |
8506 | return SHT_X86_64_UNWIND; | |
8507 | ||
8508 | return -1; | |
8509 | } | |
bb41ade5 | 8510 | |
ad5fec3b EB |
8511 | #ifdef TE_SOLARIS |
8512 | void | |
8513 | i386_solaris_fix_up_eh_frame (segT sec) | |
8514 | { | |
8515 | if (flag_code == CODE_64BIT) | |
8516 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
8517 | } | |
8518 | #endif | |
8519 | ||
bb41ade5 AM |
8520 | #ifdef TE_PE |
8521 | void | |
8522 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
8523 | { | |
8524 | expressionS expr; | |
8525 | ||
8526 | expr.X_op = O_secrel; | |
8527 | expr.X_add_symbol = symbol; | |
8528 | expr.X_add_number = 0; | |
8529 | emit_expr (&expr, size); | |
8530 | } | |
8531 | #endif | |
3b22753a L |
8532 | |
8533 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
8534 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
8535 | ||
01e1a5bc | 8536 | bfd_vma |
3b22753a L |
8537 | x86_64_section_letter (int letter, char **ptr_msg) |
8538 | { | |
8539 | if (flag_code == CODE_64BIT) | |
8540 | { | |
8541 | if (letter == 'l') | |
8542 | return SHF_X86_64_LARGE; | |
8543 | ||
8544 | *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string"); | |
64e74474 | 8545 | } |
3b22753a | 8546 | else |
64e74474 | 8547 | *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
8548 | return -1; |
8549 | } | |
8550 | ||
01e1a5bc | 8551 | bfd_vma |
3b22753a L |
8552 | x86_64_section_word (char *str, size_t len) |
8553 | { | |
8620418b | 8554 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
3b22753a L |
8555 | return SHF_X86_64_LARGE; |
8556 | ||
8557 | return -1; | |
8558 | } | |
8559 | ||
8560 | static void | |
8561 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
8562 | { | |
8563 | if (flag_code != CODE_64BIT) | |
8564 | { | |
8565 | s_comm_internal (0, elf_common_parse); | |
8566 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
8567 | } | |
8568 | else | |
8569 | { | |
8570 | static segT lbss_section; | |
8571 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
8572 | asection *saved_bss_section = bss_section; | |
8573 | ||
8574 | if (lbss_section == NULL) | |
8575 | { | |
8576 | flagword applicable; | |
8577 | segT seg = now_seg; | |
8578 | subsegT subseg = now_subseg; | |
8579 | ||
8580 | /* The .lbss section is for local .largecomm symbols. */ | |
8581 | lbss_section = subseg_new (".lbss", 0); | |
8582 | applicable = bfd_applicable_section_flags (stdoutput); | |
8583 | bfd_set_section_flags (stdoutput, lbss_section, | |
8584 | applicable & SEC_ALLOC); | |
8585 | seg_info (lbss_section)->bss = 1; | |
8586 | ||
8587 | subseg_set (seg, subseg); | |
8588 | } | |
8589 | ||
8590 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
8591 | bss_section = lbss_section; | |
8592 | ||
8593 | s_comm_internal (0, elf_common_parse); | |
8594 | ||
8595 | elf_com_section_ptr = saved_com_section_ptr; | |
8596 | bss_section = saved_bss_section; | |
8597 | } | |
8598 | } | |
8599 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |