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2005-12-12 Paul Brook <paul@codesourcery.com>
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
aef6203b 3 2000, 2001, 2002, 2003, 2004, 2005
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
252b5132 35#include "opcode/i386.h"
d2b2c203 36#include "elf/x86-64.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
29b0f896
AM		 66static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70static INLINE int fits_in_signed_word PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 73static int smallest_imm_type PARAMS ((offsetT));
74static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 75static int add_prefix PARAMS ((unsigned int));
3e73aa7c 76static void set_code_flag PARAMS ((int));
47926f60 77static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 78static void set_intel_syntax PARAMS ((int));
e413e4e9 79static void set_cpu_arch PARAMS ((int));
6482c264
NC		 80#ifdef TE_PE
81static void pe_directive_secrel PARAMS ((int));
82#endif
d182319b 83static void signed_cons PARAMS ((int));
29b0f896
AM		 84static char *output_invalid PARAMS ((int c));
85static int i386_operand PARAMS ((char *operand_string));
86static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
87static const reg_entry *parse_register PARAMS ((char *reg_string,
88 char **end_op));
89static char *parse_insn PARAMS ((char *, char *));
90static char *parse_operands PARAMS ((char *, const char *));
91static void swap_operands PARAMS ((void));
92static void optimize_imm PARAMS ((void));
93static void optimize_disp PARAMS ((void));
94static int match_template PARAMS ((void));
95static int check_string PARAMS ((void));
96static int process_suffix PARAMS ((void));
97static int check_byte_reg PARAMS ((void));
98static int check_long_reg PARAMS ((void));
99static int check_qword_reg PARAMS ((void));
100static int check_word_reg PARAMS ((void));
101static int finalize_imm PARAMS ((void));
102static int process_operands PARAMS ((void));
103static const seg_entry *build_modrm_byte PARAMS ((void));
104static void output_insn PARAMS ((void));
105static void output_branch PARAMS ((void));
106static void output_jump PARAMS ((void));
107static void output_interseg_jump PARAMS ((void));
2bbd9c25
JJ		 108static void output_imm PARAMS ((fragS *insn_start_frag,
109 offsetT insn_start_off));
110static void output_disp PARAMS ((fragS *insn_start_frag,
111 offsetT insn_start_off));
29b0f896
AM		 112#ifndef I386COFF
113static void s_bss PARAMS ((int));
252b5132 114#endif
17d4e2a2
L		 115#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
116static void handle_large_common (int small ATTRIBUTE_UNUSED);
117#endif
252b5132 118
a847613f 119static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 120
252b5132 121/* 'md_assemble ()' gathers together information and puts it into a
47926f60 122 i386_insn. */
252b5132 123
520dc8e8
AM		 124union i386_op
125 {
126 expressionS *disps;
127 expressionS *imms;
128 const reg_entry *regs;
129 };
130
252b5132
RH		 131struct _i386_insn
132 {
47926f60 133 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 134 template tm;
135
136 /* SUFFIX holds the instruction mnemonic suffix if given.
137 (e.g. 'l' for 'movl') */
138 char suffix;
139
47926f60 140 /* OPERANDS gives the number of given operands. */
252b5132
RH		 141 unsigned int operands;
142
143 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
144 of given register, displacement, memory operands and immediate
47926f60 145 operands. */
252b5132
RH		 146 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
147
148 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 149 use OP[i] for the corresponding operand. */
252b5132
RH		 150 unsigned int types[MAX_OPERANDS];
151
520dc8e8
AM		 152 /* Displacement expression, immediate expression, or register for each
153 operand. */
154 union i386_op op[MAX_OPERANDS];
252b5132 155
3e73aa7c
JH		 156 /* Flags for operands. */
157 unsigned int flags[MAX_OPERANDS];
158#define Operand_PCrel 1
159
252b5132 160 /* Relocation type for operand */
f86103b7 161 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 162
252b5132
RH		 163 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
164 the base index byte below. */
165 const reg_entry *base_reg;
166 const reg_entry *index_reg;
167 unsigned int log2_scale_factor;
168
169 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 170 explicit segment overrides are given. */
ce8a8b2f 171 const seg_entry *seg[2];
252b5132
RH		 172
173 /* PREFIX holds all the given prefix opcodes (usually null).
174 PREFIXES is the number of prefix opcodes. */
175 unsigned int prefixes;
176 unsigned char prefix[MAX_PREFIXES];
177
178 /* RM and SIB are the modrm byte and the sib byte where the
179 addressing modes of this insn are encoded. */
180
181 modrm_byte rm;
3e73aa7c 182 rex_byte rex;
252b5132
RH		 183 sib_byte sib;
184 };
185
186typedef struct _i386_insn i386_insn;
187
188/* List of chars besides those in app.c:symbol_chars that can start an
189 operand. Used to prevent the scrubber eating vital white-space. */
32137342 190const char extra_symbol_chars[] = "*%-(["
252b5132 191#ifdef LEX_AT
32137342
NC		 192 "@"
193#endif
194#ifdef LEX_QM
195 "?"
252b5132 196#endif
32137342 197 ;
252b5132 198
29b0f896
AM		 199#if (defined (TE_I386AIX) \
200 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 201 && !defined (TE_GNU) \
29b0f896 202 && !defined (TE_LINUX) \
32137342 203 && !defined (TE_NETWARE) \
29b0f896
AM		 204 && !defined (TE_FreeBSD) \
205 && !defined (TE_NetBSD)))
252b5132 206/* This array holds the chars that always start a comment. If the
b3b91714
AM		 207 pre-processor is disabled, these aren't very useful. The option
208 --divide will remove '/' from this list. */
209const char *i386_comment_chars = "#/";
210#define SVR4_COMMENT_CHARS 1
252b5132 211#define PREFIX_SEPARATOR '\\'
252b5132 212
b3b91714
AM		 213#else
214const char *i386_comment_chars = "#";
215#define PREFIX_SEPARATOR '/'
216#endif
217
252b5132
RH		 218/* This array holds the chars that only start a comment at the beginning of
219 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 220 .line and .file directives will appear in the pre-processed output.
221 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 222 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 223 #NO_APP at the beginning of its output.
224 Also note that comments started like this one will always work if
252b5132 225 '/' isn't otherwise defined. */
b3b91714 226const char line_comment_chars[] = "#/";
252b5132 227
63a0b638 228const char line_separator_chars[] = ";";
252b5132 229
ce8a8b2f
AM		 230/* Chars that can be used to separate mant from exp in floating point
231 nums. */
252b5132
RH		 232const char EXP_CHARS[] = "eE";
233
ce8a8b2f
AM		 234/* Chars that mean this number is a floating point constant
235 As in 0f12.456
236 or 0d1.2345e12. */
252b5132
RH		 237const char FLT_CHARS[] = "fFdDxX";
238
ce8a8b2f 239/* Tables for lexical analysis. */
252b5132
RH		 240static char mnemonic_chars[256];
241static char register_chars[256];
242static char operand_chars[256];
243static char identifier_chars[256];
244static char digit_chars[256];
245
ce8a8b2f 246/* Lexical macros. */
252b5132
RH		 247#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
248#define is_operand_char(x) (operand_chars[(unsigned char) x])
249#define is_register_char(x) (register_chars[(unsigned char) x])
250#define is_space_char(x) ((x) == ' ')
251#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
252#define is_digit_char(x) (digit_chars[(unsigned char) x])
253
0234cb7c 254/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 255static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
256
257/* md_assemble() always leaves the strings it's passed unaltered. To
258 effect this we maintain a stack of saved characters that we've smashed
259 with '\0's (indicating end of strings for various sub-fields of the
47926f60 260 assembler instruction). */
252b5132 261static char save_stack[32];
ce8a8b2f 262static char *save_stack_p;
252b5132
RH		 263#define END_STRING_AND_SAVE(s) \
264 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
265#define RESTORE_END_STRING(s) \
266 do { *(s) = *--save_stack_p; } while (0)
267
47926f60 268/* The instruction we're assembling. */
252b5132
RH		 269static i386_insn i;
270
271/* Possible templates for current insn. */
272static const templates *current_templates;
273
47926f60 274/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 275static expressionS disp_expressions[2], im_expressions[2];
276
47926f60
KH		 277/* Current operand we are working on. */
278static int this_operand;
252b5132 279
3e73aa7c
JH		 280/* We support four different modes. FLAG_CODE variable is used to distinguish
281 these. */
282
283enum flag_code {
284 CODE_32BIT,
285 CODE_16BIT,
286 CODE_64BIT };
f3c180ae 287#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 288
289static enum flag_code flag_code;
4fa24527 290static unsigned int object_64bit;
3e73aa7c
JH		 291static int use_rela_relocations = 0;
292
293/* The names used to print error messages. */
b77a7acd 294static const char *flag_code_names[] =
3e73aa7c
JH		 295 {
296 "32",
297 "16",
298 "64"
299 };
252b5132 300
47926f60
KH		 301/* 1 for intel syntax,
302 0 if att syntax. */
303static int intel_syntax = 0;
252b5132 304
47926f60
KH		 305/* 1 if register prefix % not required. */
306static int allow_naked_reg = 0;
252b5132 307
47926f60
KH		 308/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
309 leave, push, and pop instructions so that gcc has the same stack
310 frame as in 32 bit mode. */
311static char stackop_size = '\0';
eecb386c 312
12b55ccc
L		 313/* Non-zero to optimize code alignment. */
314int optimize_align_code = 1;
315
47926f60
KH		 316/* Non-zero to quieten some warnings. */
317static int quiet_warnings = 0;
a38cf1db 318
47926f60
KH		 319/* CPU name. */
320static const char *cpu_arch_name = NULL;
5c6af06e 321static const char *cpu_sub_arch_name = NULL;
a38cf1db 322
47926f60 323/* CPU feature flags. */
29b0f896 324static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 325
fddf5b5b
AM		 326/* If set, conditional jumps are not automatically promoted to handle
327 larger than a byte offset. */
328static unsigned int no_cond_jump_promotion = 0;
329
29b0f896 330/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 331static symbolS *GOT_symbol;
29b0f896 332
a4447b93
RH		 333/* The dwarf2 return column, adjusted for 32 or 64 bit. */
334unsigned int x86_dwarf2_return_column;
335
336/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
337int x86_cie_data_alignment;
338
252b5132 339/* Interface to relax_segment.
fddf5b5b
AM		 340 There are 3 major relax states for 386 jump insns because the
341 different types of jumps add different sizes to frags when we're
342 figuring out what sort of jump to choose to reach a given label. */
252b5132 343
47926f60 344/* Types. */
93c2a809
AM		 345#define UNCOND_JUMP 0
346#define COND_JUMP 1
347#define COND_JUMP86 2
fddf5b5b 348
47926f60 349/* Sizes. */
252b5132
RH		 350#define CODE16 1
351#define SMALL 0
29b0f896 352#define SMALL16 (SMALL | CODE16)
252b5132 353#define BIG 2
29b0f896 354#define BIG16 (BIG | CODE16)
252b5132
RH		 355
356#ifndef INLINE
357#ifdef __GNUC__
358#define INLINE __inline__
359#else
360#define INLINE
361#endif
362#endif
363
fddf5b5b
AM		 364#define ENCODE_RELAX_STATE(type, size) \
365 ((relax_substateT) (((type) << 2) | (size)))
366#define TYPE_FROM_RELAX_STATE(s) \
367 ((s) >> 2)
368#define DISP_SIZE_FROM_RELAX_STATE(s) \
369 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 370
371/* This table is used by relax_frag to promote short jumps to long
372 ones where necessary. SMALL (short) jumps may be promoted to BIG
373 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
374 don't allow a short jump in a 32 bit code segment to be promoted to
375 a 16 bit offset jump because it's slower (requires data size
376 prefix), and doesn't work, unless the destination is in the bottom
377 64k of the code segment (The top 16 bits of eip are zeroed). */
378
379const relax_typeS md_relax_table[] =
380{
24eab124
AM		 381 /* The fields are:
382 1) most positive reach of this state,
383 2) most negative reach of this state,
93c2a809 384 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 385 4) which index into the table to try if we can't fit into this one. */
252b5132 386
fddf5b5b 387 /* UNCOND_JUMP states. */
93c2a809
AM		 388 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
389 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
390 /* dword jmp adds 4 bytes to frag:
391 0 extra opcode bytes, 4 displacement bytes. */
252b5132 392 {0, 0, 4, 0},
93c2a809
AM		 393 /* word jmp adds 2 byte2 to frag:
394 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 395 {0, 0, 2, 0},
396
93c2a809
AM		 397 /* COND_JUMP states. */
398 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
399 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
400 /* dword conditionals adds 5 bytes to frag:
401 1 extra opcode byte, 4 displacement bytes. */
402 {0, 0, 5, 0},
fddf5b5b 403 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 404 1 extra opcode byte, 2 displacement bytes. */
405 {0, 0, 3, 0},
406
407 /* COND_JUMP86 states. */
408 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
409 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
410 /* dword conditionals adds 5 bytes to frag:
411 1 extra opcode byte, 4 displacement bytes. */
412 {0, 0, 5, 0},
413 /* word conditionals add 4 bytes to frag:
414 1 displacement byte and a 3 byte long branch insn. */
415 {0, 0, 4, 0}
252b5132
RH		 416};
417
e413e4e9
AM		 418static const arch_entry cpu_arch[] = {
419 {"i8086", Cpu086 },
420 {"i186", Cpu086|Cpu186 },
421 {"i286", Cpu086|Cpu186|Cpu286 },
422 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
423 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
5c6af06e
JB		 424 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
425 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
426 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
427 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
428 {"pentiumii", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX },
429 {"pentiumiii",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE },
430 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
431 {"prescott", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI },
432 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX },
433 {"k6_2", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
434 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
435 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
30123838 436 {"opteron", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
5c6af06e
JB		 437 {".mmx", CpuMMX },
438 {".sse", CpuMMX|CpuMMX2|CpuSSE },
439 {".sse2", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
bf50992e 440 {".sse3", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3 },
5c6af06e
JB		 441 {".3dnow", CpuMMX|Cpu3dnow },
442 {".3dnowa", CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
443 {".padlock", CpuPadLock },
30123838
JB		 444 {".pacifica", CpuSVME },
445 {".svme", CpuSVME },
e413e4e9
AM		 446 {NULL, 0 }
447};
448
29b0f896
AM		 449const pseudo_typeS md_pseudo_table[] =
450{
451#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
452 {"align", s_align_bytes, 0},
453#else
454 {"align", s_align_ptwo, 0},
455#endif
456 {"arch", set_cpu_arch, 0},
457#ifndef I386COFF
458 {"bss", s_bss, 0},
459#endif
460 {"ffloat", float_cons, 'f'},
461 {"dfloat", float_cons, 'd'},
462 {"tfloat", float_cons, 'x'},
463 {"value", cons, 2},
d182319b 464 {"slong", signed_cons, 4},
29b0f896
AM		 465 {"noopt", s_ignore, 0},
466 {"optim", s_ignore, 0},
467 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
468 {"code16", set_code_flag, CODE_16BIT},
469 {"code32", set_code_flag, CODE_32BIT},
470 {"code64", set_code_flag, CODE_64BIT},
471 {"intel_syntax", set_intel_syntax, 1},
472 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 473#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
474 {"largecomm", handle_large_common, 0},
07a53e5c
RH		 475#else
476 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
477 {"loc", dwarf2_directive_loc, 0},
478 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 479#endif
6482c264
NC		 480#ifdef TE_PE
481 {"secrel32", pe_directive_secrel, 0},
482#endif
29b0f896
AM		 483 {0, 0, 0}
484};
485
486/* For interface with expression (). */
487extern char *input_line_pointer;
488
489/* Hash table for instruction mnemonic lookup. */
490static struct hash_control *op_hash;
491
492/* Hash table for register lookup. */
493static struct hash_control *reg_hash;
494\f
252b5132
RH		 495void
496i386_align_code (fragP, count)
497 fragS *fragP;
498 int count;
499{
ce8a8b2f
AM		 500 /* Various efficient no-op patterns for aligning code labels.
501 Note: Don't try to assemble the instructions in the comments.
502 0L and 0w are not legal. */
252b5132
RH		 503 static const char f32_1[] =
504 {0x90}; /* nop */
505 static const char f32_2[] =
506 {0x89,0xf6}; /* movl %esi,%esi */
507 static const char f32_3[] =
508 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
509 static const char f32_4[] =
510 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
511 static const char f32_5[] =
512 {0x90, /* nop */
513 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
514 static const char f32_6[] =
515 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
516 static const char f32_7[] =
517 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
518 static const char f32_8[] =
519 {0x90, /* nop */
520 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
521 static const char f32_9[] =
522 {0x89,0xf6, /* movl %esi,%esi */
523 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
524 static const char f32_10[] =
525 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
526 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
527 static const char f32_11[] =
528 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
529 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
530 static const char f32_12[] =
531 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
532 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
533 static const char f32_13[] =
534 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
535 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
536 static const char f32_14[] =
537 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
538 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
539 static const char f32_15[] =
540 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
541 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 542 static const char f16_3[] =
543 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 544 static const char f16_4[] =
545 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
546 static const char f16_5[] =
547 {0x90, /* nop */
548 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
549 static const char f16_6[] =
550 {0x89,0xf6, /* mov %si,%si */
551 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
552 static const char f16_7[] =
553 {0x8d,0x74,0x00, /* lea 0(%si),%si */
554 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
555 static const char f16_8[] =
556 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
557 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
558 static const char *const f32_patt[] = {
559 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
560 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
561 };
562 static const char *const f16_patt[] = {
c3332e24 563 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 564 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
565 };
566
33fef721
JH		 567 if (count <= 0 || count > 15)
568 return;
3e73aa7c 569
33fef721
JH		 570 /* The recommended way to pad 64bit code is to use NOPs preceded by
571 maximally four 0x66 prefixes. Balance the size of nops. */
572 if (flag_code == CODE_64BIT)
252b5132 573 {
33fef721
JH		 574 int i;
575 int nnops = (count + 3) / 4;
576 int len = count / nnops;
577 int remains = count - nnops * len;
578 int pos = 0;
579
580 for (i = 0; i < remains; i++)
252b5132 581 {
33fef721
JH		 582 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
583 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
584 pos += len + 1;
585 }
586 for (; i < nnops; i++)
587 {
588 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
589 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
590 pos += len;
252b5132 591 }
252b5132 592 }
33fef721
JH		 593 else
594 if (flag_code == CODE_16BIT)
595 {
596 memcpy (fragP->fr_literal + fragP->fr_fix,
597 f16_patt[count - 1], count);
598 if (count > 8)
599 /* Adjust jump offset. */
600 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
601 }
602 else
603 memcpy (fragP->fr_literal + fragP->fr_fix,
604 f32_patt[count - 1], count);
605 fragP->fr_var = count;
252b5132
RH		 606}
607
252b5132
RH		 608static INLINE unsigned int
609mode_from_disp_size (t)
610 unsigned int t;
611{
3e73aa7c 612 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 613}
614
615static INLINE int
616fits_in_signed_byte (num)
847f7ad4 617 offsetT num;
252b5132
RH		 618{
619 return (num >= -128) && (num <= 127);
47926f60 620}
252b5132
RH		 621
622static INLINE int
623fits_in_unsigned_byte (num)
847f7ad4 624 offsetT num;
252b5132
RH		 625{
626 return (num & 0xff) == num;
47926f60 627}
252b5132
RH		 628
629static INLINE int
630fits_in_unsigned_word (num)
847f7ad4 631 offsetT num;
252b5132
RH		 632{
633 return (num & 0xffff) == num;
47926f60 634}
252b5132
RH		 635
636static INLINE int
637fits_in_signed_word (num)
847f7ad4 638 offsetT num;
252b5132
RH		 639{
640 return (-32768 <= num) && (num <= 32767);
47926f60 641}
3e73aa7c
JH		 642static INLINE int
643fits_in_signed_long (num)
644 offsetT num ATTRIBUTE_UNUSED;
645{
646#ifndef BFD64
647 return 1;
648#else
649 return (!(((offsetT) -1 << 31) & num)
650 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
651#endif
652} /* fits_in_signed_long() */
653static INLINE int
654fits_in_unsigned_long (num)
655 offsetT num ATTRIBUTE_UNUSED;
656{
657#ifndef BFD64
658 return 1;
659#else
660 return (num & (((offsetT) 2 << 31) - 1)) == num;
661#endif
662} /* fits_in_unsigned_long() */
252b5132
RH		 663
664static int
665smallest_imm_type (num)
847f7ad4 666 offsetT num;
252b5132 667{
a847613f 668 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 669 {
670 /* This code is disabled on the 486 because all the Imm1 forms
671 in the opcode table are slower on the i486. They're the
672 versions with the implicitly specified single-position
673 displacement, which has another syntax if you really want to
674 use that form. */
675 if (num == 1)
3e73aa7c 676 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 677 }
252b5132 678 return (fits_in_signed_byte (num)
3e73aa7c 679 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 680 : fits_in_unsigned_byte (num)
3e73aa7c 681 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 682 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 683 ? (Imm16 | Imm32 | Imm32S | Imm64)
684 : fits_in_signed_long (num)
685 ? (Imm32 | Imm32S | Imm64)
686 : fits_in_unsigned_long (num)
687 ? (Imm32 | Imm64)
688 : Imm64);
47926f60 689}
252b5132 690
847f7ad4
AM		 691static offsetT
692offset_in_range (val, size)
693 offsetT val;
694 int size;
695{
508866be 696 addressT mask;
ba2adb93 697
847f7ad4
AM		 698 switch (size)
699 {
508866be
L		 700 case 1: mask = ((addressT) 1 << 8) - 1; break;
701 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 702 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 703#ifdef BFD64
704 case 8: mask = ((addressT) 2 << 63) - 1; break;
705#endif
47926f60 706 default: abort ();
847f7ad4
AM		 707 }
708
ba2adb93 709 /* If BFD64, sign extend val. */
3e73aa7c
JH		 710 if (!use_rela_relocations)
711 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
712 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 713
47926f60 714 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 715 {
716 char buf1[40], buf2[40];
717
718 sprint_value (buf1, val);
719 sprint_value (buf2, val & mask);
720 as_warn (_("%s shortened to %s"), buf1, buf2);
721 }
722 return val & mask;
723}
724
252b5132
RH		 725/* Returns 0 if attempting to add a prefix where one from the same
726 class already exists, 1 if non rep/repne added, 2 if rep/repne
727 added. */
728static int
729add_prefix (prefix)
730 unsigned int prefix;
731{
732 int ret = 1;
733 int q;
734
29b0f896
AM		 735 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
736 && flag_code == CODE_64BIT)
3e73aa7c
JH		 737 q = REX_PREFIX;
738 else
739 switch (prefix)
740 {
741 default:
742 abort ();
743
744 case CS_PREFIX_OPCODE:
745 case DS_PREFIX_OPCODE:
746 case ES_PREFIX_OPCODE:
747 case FS_PREFIX_OPCODE:
748 case GS_PREFIX_OPCODE:
749 case SS_PREFIX_OPCODE:
750 q = SEG_PREFIX;
751 break;
252b5132 752
3e73aa7c
JH		 753 case REPNE_PREFIX_OPCODE:
754 case REPE_PREFIX_OPCODE:
755 ret = 2;
756 /* fall thru */
757 case LOCK_PREFIX_OPCODE:
758 q = LOCKREP_PREFIX;
759 break;
252b5132 760
3e73aa7c
JH		 761 case FWAIT_OPCODE:
762 q = WAIT_PREFIX;
763 break;
252b5132 764
3e73aa7c
JH		 765 case ADDR_PREFIX_OPCODE:
766 q = ADDR_PREFIX;
767 break;
252b5132 768
3e73aa7c
JH		 769 case DATA_PREFIX_OPCODE:
770 q = DATA_PREFIX;
771 break;
772 }
252b5132 773
29b0f896 774 if (i.prefix[q] != 0)
252b5132
RH		 775 {
776 as_bad (_("same type of prefix used twice"));
777 return 0;
778 }
779
780 i.prefixes += 1;
781 i.prefix[q] = prefix;
782 return ret;
783}
784
785static void
3e73aa7c 786set_code_flag (value)
e5cb08ac 787 int value;
eecb386c 788{
3e73aa7c
JH		 789 flag_code = value;
790 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
791 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
792 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
793 {
794 as_bad (_("64bit mode not supported on this CPU."));
795 }
796 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
797 {
798 as_bad (_("32bit mode not supported on this CPU."));
799 }
eecb386c
AM		 800 stackop_size = '\0';
801}
802
803static void
3e73aa7c
JH		 804set_16bit_gcc_code_flag (new_code_flag)
805 int new_code_flag;
252b5132 806{
3e73aa7c
JH		 807 flag_code = new_code_flag;
808 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
809 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 810 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 811}
812
813static void
814set_intel_syntax (syntax_flag)
eecb386c 815 int syntax_flag;
252b5132
RH		 816{
817 /* Find out if register prefixing is specified. */
818 int ask_naked_reg = 0;
819
820 SKIP_WHITESPACE ();
29b0f896 821 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 822 {
823 char *string = input_line_pointer;
824 int e = get_symbol_end ();
825
47926f60 826 if (strcmp (string, "prefix") == 0)
252b5132 827 ask_naked_reg = 1;
47926f60 828 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 829 ask_naked_reg = -1;
830 else
d0b47220 831 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 832 *input_line_pointer = e;
833 }
834 demand_empty_rest_of_line ();
c3332e24 835
252b5132
RH		 836 intel_syntax = syntax_flag;
837
838 if (ask_naked_reg == 0)
f86103b7
AM		 839 allow_naked_reg = (intel_syntax
840 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 841 else
842 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a
JB		 843
844 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
845 identifier_chars['$'] = intel_syntax ? '$' : 0;
252b5132
RH		 846}
847
e413e4e9
AM		 848static void
849set_cpu_arch (dummy)
47926f60 850 int dummy ATTRIBUTE_UNUSED;
e413e4e9 851{
47926f60 852 SKIP_WHITESPACE ();
e413e4e9 853
29b0f896 854 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 855 {
856 char *string = input_line_pointer;
857 int e = get_symbol_end ();
858 int i;
859
860 for (i = 0; cpu_arch[i].name; i++)
861 {
862 if (strcmp (string, cpu_arch[i].name) == 0)
863 {
5c6af06e
JB		 864 if (*string != '.')
865 {
866 cpu_arch_name = cpu_arch[i].name;
867 cpu_sub_arch_name = NULL;
868 cpu_arch_flags = (cpu_arch[i].flags
869 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
870 break;
871 }
872 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
873 {
874 cpu_sub_arch_name = cpu_arch[i].name;
875 cpu_arch_flags |= cpu_arch[i].flags;
876 }
877 *input_line_pointer = e;
878 demand_empty_rest_of_line ();
879 return;
e413e4e9
AM		 880 }
881 }
882 if (!cpu_arch[i].name)
883 as_bad (_("no such architecture: `%s'"), string);
884
885 *input_line_pointer = e;
886 }
887 else
888 as_bad (_("missing cpu architecture"));
889
fddf5b5b
AM		 890 no_cond_jump_promotion = 0;
891 if (*input_line_pointer == ','
29b0f896 892 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 893 {
894 char *string = ++input_line_pointer;
895 int e = get_symbol_end ();
896
897 if (strcmp (string, "nojumps") == 0)
898 no_cond_jump_promotion = 1;
899 else if (strcmp (string, "jumps") == 0)
900 ;
901 else
902 as_bad (_("no such architecture modifier: `%s'"), string);
903
904 *input_line_pointer = e;
905 }
906
e413e4e9
AM		 907 demand_empty_rest_of_line ();
908}
909
b9d79e03
JH		 910unsigned long
911i386_mach ()
912{
913 if (!strcmp (default_arch, "x86_64"))
914 return bfd_mach_x86_64;
915 else if (!strcmp (default_arch, "i386"))
916 return bfd_mach_i386_i386;
917 else
918 as_fatal (_("Unknown architecture"));
919}
b9d79e03 920\f
252b5132
RH		 921void
922md_begin ()
923{
924 const char *hash_err;
925
47926f60 926 /* Initialize op_hash hash table. */
252b5132
RH		 927 op_hash = hash_new ();
928
929 {
29b0f896
AM		 930 const template *optab;
931 templates *core_optab;
252b5132 932
47926f60
KH		 933 /* Setup for loop. */
934 optab = i386_optab;
252b5132
RH		 935 core_optab = (templates *) xmalloc (sizeof (templates));
936 core_optab->start = optab;
937
938 while (1)
939 {
940 ++optab;
941 if (optab->name == NULL
942 || strcmp (optab->name, (optab - 1)->name) != 0)
943 {
944 /* different name --> ship out current template list;
47926f60 945 add to hash table; & begin anew. */
252b5132
RH		 946 core_optab->end = optab;
947 hash_err = hash_insert (op_hash,
948 (optab - 1)->name,
949 (PTR) core_optab);
950 if (hash_err)
951 {
252b5132
RH		 952 as_fatal (_("Internal Error: Can't hash %s: %s"),
953 (optab - 1)->name,
954 hash_err);
955 }
956 if (optab->name == NULL)
957 break;
958 core_optab = (templates *) xmalloc (sizeof (templates));
959 core_optab->start = optab;
960 }
961 }
962 }
963
47926f60 964 /* Initialize reg_hash hash table. */
252b5132
RH		 965 reg_hash = hash_new ();
966 {
29b0f896 967 const reg_entry *regtab;
252b5132
RH		 968
969 for (regtab = i386_regtab;
970 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
971 regtab++)
972 {
973 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
974 if (hash_err)
3e73aa7c
JH		 975 as_fatal (_("Internal Error: Can't hash %s: %s"),
976 regtab->reg_name,
977 hash_err);
252b5132
RH		 978 }
979 }
980
47926f60 981 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 982 {
29b0f896
AM		 983 int c;
984 char *p;
252b5132
RH		 985
986 for (c = 0; c < 256; c++)
987 {
3882b010 988 if (ISDIGIT (c))
252b5132
RH		 989 {
990 digit_chars[c] = c;
991 mnemonic_chars[c] = c;
992 register_chars[c] = c;
993 operand_chars[c] = c;
994 }
3882b010 995 else if (ISLOWER (c))
252b5132
RH		 996 {
997 mnemonic_chars[c] = c;
998 register_chars[c] = c;
999 operand_chars[c] = c;
1000 }
3882b010 1001 else if (ISUPPER (c))
252b5132 1002 {
3882b010 1003 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1004 register_chars[c] = mnemonic_chars[c];
1005 operand_chars[c] = c;
1006 }
1007
3882b010 1008 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1009 identifier_chars[c] = c;
1010 else if (c >= 128)
1011 {
1012 identifier_chars[c] = c;
1013 operand_chars[c] = c;
1014 }
1015 }
1016
1017#ifdef LEX_AT
1018 identifier_chars['@'] = '@';
32137342
NC		 1019#endif
1020#ifdef LEX_QM
1021 identifier_chars['?'] = '?';
1022 operand_chars['?'] = '?';
252b5132 1023#endif
252b5132 1024 digit_chars['-'] = '-';
791fe849 1025 mnemonic_chars['-'] = '-';
252b5132
RH		 1026 identifier_chars['_'] = '_';
1027 identifier_chars['.'] = '.';
1028
1029 for (p = operand_special_chars; *p != '\0'; p++)
1030 operand_chars[(unsigned char) *p] = *p;
1031 }
1032
1033#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1034 if (IS_ELF)
252b5132
RH		 1035 {
1036 record_alignment (text_section, 2);
1037 record_alignment (data_section, 2);
1038 record_alignment (bss_section, 2);
1039 }
1040#endif
a4447b93
RH		 1041
1042 if (flag_code == CODE_64BIT)
1043 {
1044 x86_dwarf2_return_column = 16;
1045 x86_cie_data_alignment = -8;
1046 }
1047 else
1048 {
1049 x86_dwarf2_return_column = 8;
1050 x86_cie_data_alignment = -4;
1051 }
252b5132
RH		 1052}
1053
1054void
1055i386_print_statistics (file)
1056 FILE *file;
1057{
1058 hash_print_statistics (file, "i386 opcode", op_hash);
1059 hash_print_statistics (file, "i386 register", reg_hash);
1060}
1061\f
252b5132
RH		 1062#ifdef DEBUG386
1063
ce8a8b2f 1064/* Debugging routines for md_assemble. */
252b5132
RH		 1065static void pi PARAMS ((char *, i386_insn *));
1066static void pte PARAMS ((template *));
1067static void pt PARAMS ((unsigned int));
1068static void pe PARAMS ((expressionS *));
1069static void ps PARAMS ((symbolS *));
1070
1071static void
1072pi (line, x)
1073 char *line;
1074 i386_insn *x;
1075{
09f131f2 1076 unsigned int i;
252b5132
RH		 1077
1078 fprintf (stdout, "%s: template ", line);
1079 pte (&x->tm);
09f131f2
JH		 1080 fprintf (stdout, " address: base %s index %s scale %x\n",
1081 x->base_reg ? x->base_reg->reg_name : "none",
1082 x->index_reg ? x->index_reg->reg_name : "none",
1083 x->log2_scale_factor);
1084 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1085 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1086 fprintf (stdout, " sib: base %x index %x scale %x\n",
1087 x->sib.base, x->sib.index, x->sib.scale);
1088 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1089 (x->rex & REX_MODE64) != 0,
1090 (x->rex & REX_EXTX) != 0,
1091 (x->rex & REX_EXTY) != 0,
1092 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1093 for (i = 0; i < x->operands; i++)
1094 {
1095 fprintf (stdout, " #%d: ", i + 1);
1096 pt (x->types[i]);
1097 fprintf (stdout, "\n");
1098 if (x->types[i]
3f4438ab 1099 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1100 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1101 if (x->types[i] & Imm)
520dc8e8 1102 pe (x->op[i].imms);
252b5132 1103 if (x->types[i] & Disp)
520dc8e8 1104 pe (x->op[i].disps);
252b5132
RH		 1105 }
1106}
1107
1108static void
1109pte (t)
1110 template *t;
1111{
09f131f2 1112 unsigned int i;
252b5132 1113 fprintf (stdout, " %d operands ", t->operands);
47926f60 1114 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1115 if (t->extension_opcode != None)
1116 fprintf (stdout, "ext %x ", t->extension_opcode);
1117 if (t->opcode_modifier & D)
1118 fprintf (stdout, "D");
1119 if (t->opcode_modifier & W)
1120 fprintf (stdout, "W");
1121 fprintf (stdout, "\n");
1122 for (i = 0; i < t->operands; i++)
1123 {
1124 fprintf (stdout, " #%d type ", i + 1);
1125 pt (t->operand_types[i]);
1126 fprintf (stdout, "\n");
1127 }
1128}
1129
1130static void
1131pe (e)
1132 expressionS *e;
1133{
24eab124 1134 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1135 fprintf (stdout, " add_number %ld (%lx)\n",
1136 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1137 if (e->X_add_symbol)
1138 {
1139 fprintf (stdout, " add_symbol ");
1140 ps (e->X_add_symbol);
1141 fprintf (stdout, "\n");
1142 }
1143 if (e->X_op_symbol)
1144 {
1145 fprintf (stdout, " op_symbol ");
1146 ps (e->X_op_symbol);
1147 fprintf (stdout, "\n");
1148 }
1149}
1150
1151static void
1152ps (s)
1153 symbolS *s;
1154{
1155 fprintf (stdout, "%s type %s%s",
1156 S_GET_NAME (s),
1157 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1158 segment_name (S_GET_SEGMENT (s)));
1159}
1160
1161struct type_name
1162 {
1163 unsigned int mask;
1164 char *tname;
1165 }
1166
29b0f896 1167static const type_names[] =
252b5132
RH		 1168{
1169 { Reg8, "r8" },
1170 { Reg16, "r16" },
1171 { Reg32, "r32" },
09f131f2 1172 { Reg64, "r64" },
252b5132
RH		 1173 { Imm8, "i8" },
1174 { Imm8S, "i8s" },
1175 { Imm16, "i16" },
1176 { Imm32, "i32" },
09f131f2
JH		 1177 { Imm32S, "i32s" },
1178 { Imm64, "i64" },
252b5132
RH		 1179 { Imm1, "i1" },
1180 { BaseIndex, "BaseIndex" },
1181 { Disp8, "d8" },
1182 { Disp16, "d16" },
1183 { Disp32, "d32" },
09f131f2
JH		 1184 { Disp32S, "d32s" },
1185 { Disp64, "d64" },
252b5132
RH		 1186 { InOutPortReg, "InOutPortReg" },
1187 { ShiftCount, "ShiftCount" },
1188 { Control, "control reg" },
1189 { Test, "test reg" },
1190 { Debug, "debug reg" },
1191 { FloatReg, "FReg" },
1192 { FloatAcc, "FAcc" },
1193 { SReg2, "SReg2" },
1194 { SReg3, "SReg3" },
1195 { Acc, "Acc" },
1196 { JumpAbsolute, "Jump Absolute" },
1197 { RegMMX, "rMMX" },
3f4438ab 1198 { RegXMM, "rXMM" },
252b5132
RH		 1199 { EsSeg, "es" },
1200 { 0, "" }
1201};
1202
1203static void
1204pt (t)
1205 unsigned int t;
1206{
29b0f896 1207 const struct type_name *ty;
252b5132 1208
09f131f2
JH		 1209 for (ty = type_names; ty->mask; ty++)
1210 if (t & ty->mask)
1211 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1212 fflush (stdout);
1213}
1214
1215#endif /* DEBUG386 */
1216\f
252b5132 1217static bfd_reloc_code_real_type
3956db08
JB		 1218reloc (unsigned int size,
1219 int pcrel,
1220 int sign,
1221 bfd_reloc_code_real_type other)
252b5132 1222{
47926f60 1223 if (other != NO_RELOC)
3956db08
JB		 1224 {
1225 reloc_howto_type *reloc;
1226
1227 if (size == 8)
1228 switch (other)
1229 {
1230 case BFD_RELOC_X86_64_TPOFF32:
1231 other = BFD_RELOC_X86_64_TPOFF64;
1232 break;
1233 case BFD_RELOC_X86_64_DTPOFF32:
1234 other = BFD_RELOC_X86_64_DTPOFF64;
1235 break;
1236 default:
1237 break;
1238 }
e05278af
JB		 1239
1240 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1241 if (size == 4 && flag_code != CODE_64BIT)
1242 sign = -1;
1243
3956db08
JB		 1244 reloc = bfd_reloc_type_lookup (stdoutput, other);
1245 if (!reloc)
1246 as_bad (_("unknown relocation (%u)"), other);
1247 else if (size != bfd_get_reloc_size (reloc))
1248 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1249 bfd_get_reloc_size (reloc),
1250 size);
1251 else if (pcrel && !reloc->pc_relative)
1252 as_bad (_("non-pc-relative relocation for pc-relative field"));
1253 else if ((reloc->complain_on_overflow == complain_overflow_signed
1254 && !sign)
1255 || (reloc->complain_on_overflow == complain_overflow_unsigned
1256 && sign > 0))
1257 as_bad (_("relocated field and relocation type differ in signedness"));
1258 else
1259 return other;
1260 return NO_RELOC;
1261 }
252b5132
RH		 1262
1263 if (pcrel)
1264 {
3e73aa7c 1265 if (!sign)
3956db08 1266 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1267 switch (size)
1268 {
1269 case 1: return BFD_RELOC_8_PCREL;
1270 case 2: return BFD_RELOC_16_PCREL;
1271 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1272 case 8: return BFD_RELOC_64_PCREL;
252b5132 1273 }
3956db08 1274 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1275 }
1276 else
1277 {
3956db08 1278 if (sign > 0)
e5cb08ac 1279 switch (size)
3e73aa7c
JH		 1280 {
1281 case 4: return BFD_RELOC_X86_64_32S;
1282 }
1283 else
1284 switch (size)
1285 {
1286 case 1: return BFD_RELOC_8;
1287 case 2: return BFD_RELOC_16;
1288 case 4: return BFD_RELOC_32;
1289 case 8: return BFD_RELOC_64;
1290 }
3956db08
JB		 1291 as_bad (_("cannot do %s %u byte relocation"),
1292 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1293 }
1294
bfb32b52 1295 abort ();
252b5132
RH		 1296 return BFD_RELOC_NONE;
1297}
1298
47926f60
KH		 1299/* Here we decide which fixups can be adjusted to make them relative to
1300 the beginning of the section instead of the symbol. Basically we need
1301 to make sure that the dynamic relocations are done correctly, so in
1302 some cases we force the original symbol to be used. */
1303
252b5132 1304int
c0c949c7 1305tc_i386_fix_adjustable (fixP)
31312f95 1306 fixS *fixP ATTRIBUTE_UNUSED;
252b5132 1307{
6d249963 1308#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1309 if (!IS_ELF)
31312f95
AM		 1310 return 1;
1311
a161fe53
AM		 1312 /* Don't adjust pc-relative references to merge sections in 64-bit
1313 mode. */
1314 if (use_rela_relocations
1315 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1316 && fixP->fx_pcrel)
252b5132 1317 return 0;
31312f95 1318
8d01d9a9
AJ		 1319 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1320 and changed later by validate_fix. */
1321 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1322 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1323 return 0;
1324
ce8a8b2f 1325 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1326 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1327 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1328 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1329 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1330 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1331 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1332 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1333 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1334 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1335 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1336 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3e73aa7c
JH		 1337 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1338 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1339 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1340 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1341 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1342 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1343 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1344 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1345 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1346 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1347 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
252b5132
RH		 1348 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1349 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1350 return 0;
31312f95 1351#endif
252b5132
RH		 1352 return 1;
1353}
252b5132 1354
29b0f896 1355static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1356
1357static int
252b5132 1358intel_float_operand (mnemonic)
29b0f896 1359 const char *mnemonic;
252b5132 1360{
9306ca4a
JB		 1361 /* Note that the value returned is meaningful only for opcodes with (memory)
1362 operands, hence the code here is free to improperly handle opcodes that
1363 have no operands (for better performance and smaller code). */
1364
1365 if (mnemonic[0] != 'f')
1366 return 0; /* non-math */
1367
1368 switch (mnemonic[1])
1369 {
1370 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1371 the fs segment override prefix not currently handled because no
1372 call path can make opcodes without operands get here */
1373 case 'i':
1374 return 2 /* integer op */;
1375 case 'l':
1376 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1377 return 3; /* fldcw/fldenv */
1378 break;
1379 case 'n':
1380 if (mnemonic[2] != 'o' /* fnop */)
1381 return 3; /* non-waiting control op */
1382 break;
1383 case 'r':
1384 if (mnemonic[2] == 's')
1385 return 3; /* frstor/frstpm */
1386 break;
1387 case 's':
1388 if (mnemonic[2] == 'a')
1389 return 3; /* fsave */
1390 if (mnemonic[2] == 't')
1391 {
1392 switch (mnemonic[3])
1393 {
1394 case 'c': /* fstcw */
1395 case 'd': /* fstdw */
1396 case 'e': /* fstenv */
1397 case 's': /* fsts[gw] */
1398 return 3;
1399 }
1400 }
1401 break;
1402 case 'x':
1403 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1404 return 0; /* fxsave/fxrstor are not really math ops */
1405 break;
1406 }
252b5132 1407
9306ca4a 1408 return 1;
252b5132
RH		 1409}
1410
1411/* This is the guts of the machine-dependent assembler. LINE points to a
1412 machine dependent instruction. This function is supposed to emit
1413 the frags/bytes it assembles to. */
1414
1415void
1416md_assemble (line)
1417 char *line;
1418{
252b5132 1419 int j;
252b5132
RH		 1420 char mnemonic[MAX_MNEM_SIZE];
1421
47926f60 1422 /* Initialize globals. */
252b5132
RH		 1423 memset (&i, '\0', sizeof (i));
1424 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1425 i.reloc[j] = NO_RELOC;
252b5132
RH		 1426 memset (disp_expressions, '\0', sizeof (disp_expressions));
1427 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1428 save_stack_p = save_stack;
252b5132
RH		 1429
1430 /* First parse an instruction mnemonic & call i386_operand for the operands.
1431 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1432 start of a (possibly prefixed) mnemonic. */
252b5132 1433
29b0f896
AM		 1434 line = parse_insn (line, mnemonic);
1435 if (line == NULL)
1436 return;
252b5132 1437
29b0f896
AM		 1438 line = parse_operands (line, mnemonic);
1439 if (line == NULL)
1440 return;
252b5132 1441
29b0f896
AM		 1442 /* Now we've parsed the mnemonic into a set of templates, and have the
1443 operands at hand. */
1444
1445 /* All intel opcodes have reversed operands except for "bound" and
1446 "enter". We also don't reverse intersegment "jmp" and "call"
1447 instructions with 2 immediate operands so that the immediate segment
1448 precedes the offset, as it does when in AT&T mode. "enter" and the
1449 intersegment "jmp" and "call" instructions are the only ones that
1450 have two immediate operands. */
1451 if (intel_syntax && i.operands > 1
1452 && (strcmp (mnemonic, "bound") != 0)
30123838 1453 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1454 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1455 swap_operands ();
1456
1457 if (i.imm_operands)
1458 optimize_imm ();
1459
b300c311
L		 1460 /* Don't optimize displacement for movabs since it only takes 64bit
1461 displacement. */
1462 if (i.disp_operands
1463 && (flag_code != CODE_64BIT
1464 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1465 optimize_disp ();
1466
1467 /* Next, we find a template that matches the given insn,
1468 making sure the overlap of the given operands types is consistent
1469 with the template operand types. */
252b5132 1470
29b0f896
AM		 1471 if (!match_template ())
1472 return;
252b5132 1473
cd61ebfe
AM		 1474 if (intel_syntax)
1475 {
1476 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1477 if (SYSV386_COMPAT
1478 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1479 i.tm.base_opcode ^= FloatR;
1480
1481 /* Zap movzx and movsx suffix. The suffix may have been set from
1482 "word ptr" or "byte ptr" on the source operand, but we'll use
1483 the suffix later to choose the destination register. */
1484 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1485 {
1486 if (i.reg_operands < 2
1487 && !i.suffix
1488 && (~i.tm.opcode_modifier
1489 & (No_bSuf
1490 | No_wSuf
1491 | No_lSuf
1492 | No_sSuf
1493 | No_xSuf
1494 | No_qSuf)))
1495 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1496
1497 i.suffix = 0;
1498 }
cd61ebfe 1499 }
24eab124 1500
29b0f896
AM		 1501 if (i.tm.opcode_modifier & FWait)
1502 if (!add_prefix (FWAIT_OPCODE))
1503 return;
252b5132 1504
29b0f896
AM		 1505 /* Check string instruction segment overrides. */
1506 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1507 {
1508 if (!check_string ())
5dd0794d 1509 return;
29b0f896 1510 }
5dd0794d 1511
29b0f896
AM		 1512 if (!process_suffix ())
1513 return;
e413e4e9 1514
29b0f896
AM		 1515 /* Make still unresolved immediate matches conform to size of immediate
1516 given in i.suffix. */
1517 if (!finalize_imm ())
1518 return;
252b5132 1519
29b0f896
AM		 1520 if (i.types[0] & Imm1)
1521 i.imm_operands = 0; /* kludge for shift insns. */
1522 if (i.types[0] & ImplicitRegister)
1523 i.reg_operands--;
1524 if (i.types[1] & ImplicitRegister)
1525 i.reg_operands--;
1526 if (i.types[2] & ImplicitRegister)
1527 i.reg_operands--;
252b5132 1528
29b0f896
AM		 1529 if (i.tm.opcode_modifier & ImmExt)
1530 {
02fc3089
L		 1531 expressionS *exp;
1532
ca164297
L		 1533 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
1534 {
67c1ffbe 1535 /* These Intel Prescott New Instructions have the fixed
ca164297
L		 1536 operands with an opcode suffix which is coded in the same
1537 place as an 8-bit immediate field would be. Here we check
1538 those operands and remove them afterwards. */
1539 unsigned int x;
1540
a4622f40 1541 for (x = 0; x < i.operands; x++)
ca164297
L		 1542 if (i.op[x].regs->reg_num != x)
1543 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1544 i.op[x].regs->reg_name, x + 1, i.tm.name);
1545 i.operands = 0;
1546 }
1547
29b0f896
AM		 1548 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1549 opcode suffix which is coded in the same place as an 8-bit
1550 immediate field would be. Here we fake an 8-bit immediate
1551 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1552
29b0f896 1553 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1554
29b0f896
AM		 1555 exp = &im_expressions[i.imm_operands++];
1556 i.op[i.operands].imms = exp;
1557 i.types[i.operands++] = Imm8;
1558 exp->X_op = O_constant;
1559 exp->X_add_number = i.tm.extension_opcode;
1560 i.tm.extension_opcode = None;
1561 }
252b5132 1562
29b0f896
AM		 1563 /* For insns with operands there are more diddles to do to the opcode. */
1564 if (i.operands)
1565 {
1566 if (!process_operands ())
1567 return;
1568 }
1569 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1570 {
1571 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1572 as_warn (_("translating to `%sp'"), i.tm.name);
1573 }
252b5132 1574
29b0f896
AM		 1575 /* Handle conversion of 'int $3' --> special int3 insn. */
1576 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1577 {
1578 i.tm.base_opcode = INT3_OPCODE;
1579 i.imm_operands = 0;
1580 }
252b5132 1581
29b0f896
AM		 1582 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1583 && i.op[0].disps->X_op == O_constant)
1584 {
1585 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1586 the absolute address given by the constant. Since ix86 jumps and
1587 calls are pc relative, we need to generate a reloc. */
1588 i.op[0].disps->X_add_symbol = &abs_symbol;
1589 i.op[0].disps->X_op = O_symbol;
1590 }
252b5132 1591
29b0f896
AM		 1592 if ((i.tm.opcode_modifier & Rex64) != 0)
1593 i.rex |= REX_MODE64;
252b5132 1594
29b0f896
AM		 1595 /* For 8 bit registers we need an empty rex prefix. Also if the
1596 instruction already has a prefix, we need to convert old
1597 registers to new ones. */
773f551c 1598
29b0f896
AM		 1599 if (((i.types[0] & Reg8) != 0
1600 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1601 || ((i.types[1] & Reg8) != 0
1602 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1603 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1604 && i.rex != 0))
1605 {
1606 int x;
726c5dcd 1607
29b0f896
AM		 1608 i.rex |= REX_OPCODE;
1609 for (x = 0; x < 2; x++)
1610 {
1611 /* Look for 8 bit operand that uses old registers. */
1612 if ((i.types[x] & Reg8) != 0
1613 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1614 {
29b0f896
AM		 1615 /* In case it is "hi" register, give up. */
1616 if (i.op[x].regs->reg_num > 3)
0477af35 1617 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
29b0f896 1618 i.op[x].regs->reg_name);
773f551c 1619
29b0f896
AM		 1620 /* Otherwise it is equivalent to the extended register.
1621 Since the encoding doesn't change this is merely
1622 cosmetic cleanup for debug output. */
1623
1624 i.op[x].regs = i.op[x].regs + 8;
773f551c 1625 }
29b0f896
AM		 1626 }
1627 }
773f551c 1628
29b0f896
AM		 1629 if (i.rex != 0)
1630 add_prefix (REX_OPCODE | i.rex);
1631
1632 /* We are ready to output the insn. */
1633 output_insn ();
1634}
1635
1636static char *
1637parse_insn (line, mnemonic)
1638 char *line;
1639 char *mnemonic;
1640{
1641 char *l = line;
1642 char *token_start = l;
1643 char *mnem_p;
5c6af06e
JB		 1644 int supported;
1645 const template *t;
29b0f896
AM		 1646
1647 /* Non-zero if we found a prefix only acceptable with string insns. */
1648 const char *expecting_string_instruction = NULL;
45288df1 1649
29b0f896
AM		 1650 while (1)
1651 {
1652 mnem_p = mnemonic;
1653 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1654 {
1655 mnem_p++;
1656 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1657 {
29b0f896
AM		 1658 as_bad (_("no such instruction: `%s'"), token_start);
1659 return NULL;
1660 }
1661 l++;
1662 }
1663 if (!is_space_char (*l)
1664 && *l != END_OF_INSN
e44823cf
JB		 1665 && (intel_syntax
1666 || (*l != PREFIX_SEPARATOR
1667 && *l != ',')))
29b0f896
AM		 1668 {
1669 as_bad (_("invalid character %s in mnemonic"),
1670 output_invalid (*l));
1671 return NULL;
1672 }
1673 if (token_start == l)
1674 {
e44823cf 1675 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 1676 as_bad (_("expecting prefix; got nothing"));
1677 else
1678 as_bad (_("expecting mnemonic; got nothing"));
1679 return NULL;
1680 }
45288df1 1681
29b0f896
AM		 1682 /* Look up instruction (or prefix) via hash table. */
1683 current_templates = hash_find (op_hash, mnemonic);
47926f60 1684
29b0f896
AM		 1685 if (*l != END_OF_INSN
1686 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1687 && current_templates
1688 && (current_templates->start->opcode_modifier & IsPrefix))
1689 {
2dd88dca
JB		 1690 if (current_templates->start->cpu_flags
1691 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1692 {
1693 as_bad ((flag_code != CODE_64BIT
1694 ? _("`%s' is only supported in 64-bit mode")
1695 : _("`%s' is not supported in 64-bit mode")),
1696 current_templates->start->name);
1697 return NULL;
1698 }
29b0f896
AM		 1699 /* If we are in 16-bit mode, do not allow addr16 or data16.
1700 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1701 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1702 && flag_code != CODE_64BIT
1703 && (((current_templates->start->opcode_modifier & Size32) != 0)
1704 ^ (flag_code == CODE_16BIT)))
1705 {
1706 as_bad (_("redundant %s prefix"),
1707 current_templates->start->name);
1708 return NULL;
45288df1 1709 }
29b0f896
AM		 1710 /* Add prefix, checking for repeated prefixes. */
1711 switch (add_prefix (current_templates->start->base_opcode))
1712 {
1713 case 0:
1714 return NULL;
1715 case 2:
1716 expecting_string_instruction = current_templates->start->name;
1717 break;
1718 }
1719 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1720 token_start = ++l;
1721 }
1722 else
1723 break;
1724 }
45288df1 1725
29b0f896
AM		 1726 if (!current_templates)
1727 {
1728 /* See if we can get a match by trimming off a suffix. */
1729 switch (mnem_p[-1])
1730 {
1731 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 1732 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
1733 i.suffix = SHORT_MNEM_SUFFIX;
1734 else
29b0f896
AM		 1735 case BYTE_MNEM_SUFFIX:
1736 case QWORD_MNEM_SUFFIX:
1737 i.suffix = mnem_p[-1];
1738 mnem_p[-1] = '\0';
1739 current_templates = hash_find (op_hash, mnemonic);
1740 break;
1741 case SHORT_MNEM_SUFFIX:
1742 case LONG_MNEM_SUFFIX:
1743 if (!intel_syntax)
1744 {
1745 i.suffix = mnem_p[-1];
1746 mnem_p[-1] = '\0';
1747 current_templates = hash_find (op_hash, mnemonic);
1748 }
1749 break;
252b5132 1750
29b0f896
AM		 1751 /* Intel Syntax. */
1752 case 'd':
1753 if (intel_syntax)
1754 {
9306ca4a 1755 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 1756 i.suffix = SHORT_MNEM_SUFFIX;
1757 else
1758 i.suffix = LONG_MNEM_SUFFIX;
1759 mnem_p[-1] = '\0';
1760 current_templates = hash_find (op_hash, mnemonic);
1761 }
1762 break;
1763 }
1764 if (!current_templates)
1765 {
1766 as_bad (_("no such instruction: `%s'"), token_start);
1767 return NULL;
1768 }
1769 }
252b5132 1770
29b0f896
AM		 1771 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1772 {
1773 /* Check for a branch hint. We allow ",pt" and ",pn" for
1774 predict taken and predict not taken respectively.
1775 I'm not sure that branch hints actually do anything on loop
1776 and jcxz insns (JumpByte) for current Pentium4 chips. They
1777 may work in the future and it doesn't hurt to accept them
1778 now. */
1779 if (l[0] == ',' && l[1] == 'p')
1780 {
1781 if (l[2] == 't')
1782 {
1783 if (!add_prefix (DS_PREFIX_OPCODE))
1784 return NULL;
1785 l += 3;
1786 }
1787 else if (l[2] == 'n')
1788 {
1789 if (!add_prefix (CS_PREFIX_OPCODE))
1790 return NULL;
1791 l += 3;
1792 }
1793 }
1794 }
1795 /* Any other comma loses. */
1796 if (*l == ',')
1797 {
1798 as_bad (_("invalid character %s in mnemonic"),
1799 output_invalid (*l));
1800 return NULL;
1801 }
252b5132 1802
29b0f896 1803 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 1804 supported = 0;
1805 for (t = current_templates->start; t < current_templates->end; ++t)
1806 {
1807 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
1808 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
1809 supported |= 1;
1810 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
1811 supported |= 2;
1812 }
1813 if (!(supported & 2))
1814 {
1815 as_bad (flag_code == CODE_64BIT
1816 ? _("`%s' is not supported in 64-bit mode")
1817 : _("`%s' is only supported in 64-bit mode"),
1818 current_templates->start->name);
1819 return NULL;
1820 }
1821 if (!(supported & 1))
29b0f896 1822 {
5c6af06e
JB		 1823 as_warn (_("`%s' is not supported on `%s%s'"),
1824 current_templates->start->name,
1825 cpu_arch_name,
1826 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 1827 }
1828 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1829 {
1830 as_warn (_("use .code16 to ensure correct addressing mode"));
1831 }
252b5132 1832
29b0f896 1833 /* Check for rep/repne without a string instruction. */
f41bbced 1834 if (expecting_string_instruction)
29b0f896 1835 {
f41bbced
JB		 1836 static templates override;
1837
1838 for (t = current_templates->start; t < current_templates->end; ++t)
1839 if (t->opcode_modifier & IsString)
1840 break;
1841 if (t >= current_templates->end)
1842 {
1843 as_bad (_("expecting string instruction after `%s'"),
1844 expecting_string_instruction);
1845 return NULL;
1846 }
1847 for (override.start = t; t < current_templates->end; ++t)
1848 if (!(t->opcode_modifier & IsString))
1849 break;
1850 override.end = t;
1851 current_templates = &override;
29b0f896 1852 }
252b5132 1853
29b0f896
AM		 1854 return l;
1855}
252b5132 1856
29b0f896
AM		 1857static char *
1858parse_operands (l, mnemonic)
1859 char *l;
1860 const char *mnemonic;
1861{
1862 char *token_start;
3138f287 1863
29b0f896
AM		 1864 /* 1 if operand is pending after ','. */
1865 unsigned int expecting_operand = 0;
252b5132 1866
29b0f896
AM		 1867 /* Non-zero if operand parens not balanced. */
1868 unsigned int paren_not_balanced;
1869
1870 while (*l != END_OF_INSN)
1871 {
1872 /* Skip optional white space before operand. */
1873 if (is_space_char (*l))
1874 ++l;
1875 if (!is_operand_char (*l) && *l != END_OF_INSN)
1876 {
1877 as_bad (_("invalid character %s before operand %d"),
1878 output_invalid (*l),
1879 i.operands + 1);
1880 return NULL;
1881 }
1882 token_start = l; /* after white space */
1883 paren_not_balanced = 0;
1884 while (paren_not_balanced || *l != ',')
1885 {
1886 if (*l == END_OF_INSN)
1887 {
1888 if (paren_not_balanced)
1889 {
1890 if (!intel_syntax)
1891 as_bad (_("unbalanced parenthesis in operand %d."),
1892 i.operands + 1);
1893 else
1894 as_bad (_("unbalanced brackets in operand %d."),
1895 i.operands + 1);
1896 return NULL;
1897 }
1898 else
1899 break; /* we are done */
1900 }
1901 else if (!is_operand_char (*l) && !is_space_char (*l))
1902 {
1903 as_bad (_("invalid character %s in operand %d"),
1904 output_invalid (*l),
1905 i.operands + 1);
1906 return NULL;
1907 }
1908 if (!intel_syntax)
1909 {
1910 if (*l == '(')
1911 ++paren_not_balanced;
1912 if (*l == ')')
1913 --paren_not_balanced;
1914 }
1915 else
1916 {
1917 if (*l == '[')
1918 ++paren_not_balanced;
1919 if (*l == ']')
1920 --paren_not_balanced;
1921 }
1922 l++;
1923 }
1924 if (l != token_start)
1925 { /* Yes, we've read in another operand. */
1926 unsigned int operand_ok;
1927 this_operand = i.operands++;
1928 if (i.operands > MAX_OPERANDS)
1929 {
1930 as_bad (_("spurious operands; (%d operands/instruction max)"),
1931 MAX_OPERANDS);
1932 return NULL;
1933 }
1934 /* Now parse operand adding info to 'i' as we go along. */
1935 END_STRING_AND_SAVE (l);
1936
1937 if (intel_syntax)
1938 operand_ok =
1939 i386_intel_operand (token_start,
1940 intel_float_operand (mnemonic));
1941 else
1942 operand_ok = i386_operand (token_start);
1943
1944 RESTORE_END_STRING (l);
1945 if (!operand_ok)
1946 return NULL;
1947 }
1948 else
1949 {
1950 if (expecting_operand)
1951 {
1952 expecting_operand_after_comma:
1953 as_bad (_("expecting operand after ','; got nothing"));
1954 return NULL;
1955 }
1956 if (*l == ',')
1957 {
1958 as_bad (_("expecting operand before ','; got nothing"));
1959 return NULL;
1960 }
1961 }
7f3f1ea2 1962
29b0f896
AM		 1963 /* Now *l must be either ',' or END_OF_INSN. */
1964 if (*l == ',')
1965 {
1966 if (*++l == END_OF_INSN)
1967 {
1968 /* Just skip it, if it's \n complain. */
1969 goto expecting_operand_after_comma;
1970 }
1971 expecting_operand = 1;
1972 }
1973 }
1974 return l;
1975}
7f3f1ea2 1976
29b0f896
AM		 1977static void
1978swap_operands ()
1979{
1980 union i386_op temp_op;
1981 unsigned int temp_type;
f86103b7 1982 enum bfd_reloc_code_real temp_reloc;
29b0f896
AM		 1983 int xchg1 = 0;
1984 int xchg2 = 0;
252b5132 1985
29b0f896
AM		 1986 if (i.operands == 2)
1987 {
1988 xchg1 = 0;
1989 xchg2 = 1;
1990 }
1991 else if (i.operands == 3)
1992 {
1993 xchg1 = 0;
1994 xchg2 = 2;
1995 }
1996 temp_type = i.types[xchg2];
1997 i.types[xchg2] = i.types[xchg1];
1998 i.types[xchg1] = temp_type;
1999 temp_op = i.op[xchg2];
2000 i.op[xchg2] = i.op[xchg1];
2001 i.op[xchg1] = temp_op;
2002 temp_reloc = i.reloc[xchg2];
2003 i.reloc[xchg2] = i.reloc[xchg1];
2004 i.reloc[xchg1] = temp_reloc;
2005
2006 if (i.mem_operands == 2)
2007 {
2008 const seg_entry *temp_seg;
2009 temp_seg = i.seg[0];
2010 i.seg[0] = i.seg[1];
2011 i.seg[1] = temp_seg;
2012 }
2013}
252b5132 2014
29b0f896
AM		 2015/* Try to ensure constant immediates are represented in the smallest
2016 opcode possible. */
2017static void
2018optimize_imm ()
2019{
2020 char guess_suffix = 0;
2021 int op;
252b5132 2022
29b0f896
AM		 2023 if (i.suffix)
2024 guess_suffix = i.suffix;
2025 else if (i.reg_operands)
2026 {
2027 /* Figure out a suffix from the last register operand specified.
2028 We can't do this properly yet, ie. excluding InOutPortReg,
2029 but the following works for instructions with immediates.
2030 In any case, we can't set i.suffix yet. */
2031 for (op = i.operands; --op >= 0;)
2032 if (i.types[op] & Reg)
252b5132 2033 {
29b0f896
AM		 2034 if (i.types[op] & Reg8)
2035 guess_suffix = BYTE_MNEM_SUFFIX;
2036 else if (i.types[op] & Reg16)
2037 guess_suffix = WORD_MNEM_SUFFIX;
2038 else if (i.types[op] & Reg32)
2039 guess_suffix = LONG_MNEM_SUFFIX;
2040 else if (i.types[op] & Reg64)
2041 guess_suffix = QWORD_MNEM_SUFFIX;
2042 break;
252b5132 2043 }
29b0f896
AM		 2044 }
2045 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2046 guess_suffix = WORD_MNEM_SUFFIX;
2047
2048 for (op = i.operands; --op >= 0;)
2049 if (i.types[op] & Imm)
2050 {
2051 switch (i.op[op].imms->X_op)
252b5132 2052 {
29b0f896
AM		 2053 case O_constant:
2054 /* If a suffix is given, this operand may be shortened. */
2055 switch (guess_suffix)
252b5132 2056 {
29b0f896
AM		 2057 case LONG_MNEM_SUFFIX:
2058 i.types[op] |= Imm32 | Imm64;
2059 break;
2060 case WORD_MNEM_SUFFIX:
2061 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2062 break;
2063 case BYTE_MNEM_SUFFIX:
2064 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2065 break;
252b5132 2066 }
252b5132 2067
29b0f896
AM		 2068 /* If this operand is at most 16 bits, convert it
2069 to a signed 16 bit number before trying to see
2070 whether it will fit in an even smaller size.
2071 This allows a 16-bit operand such as $0xffe0 to
2072 be recognised as within Imm8S range. */
2073 if ((i.types[op] & Imm16)
2074 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2075 {
29b0f896
AM		 2076 i.op[op].imms->X_add_number =
2077 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2078 }
2079 if ((i.types[op] & Imm32)
2080 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2081 == 0))
2082 {
2083 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2084 ^ ((offsetT) 1 << 31))
2085 - ((offsetT) 1 << 31));
2086 }
2087 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2088
29b0f896
AM		 2089 /* We must avoid matching of Imm32 templates when 64bit
2090 only immediate is available. */
2091 if (guess_suffix == QWORD_MNEM_SUFFIX)
2092 i.types[op] &= ~Imm32;
2093 break;
252b5132 2094
29b0f896
AM		 2095 case O_absent:
2096 case O_register:
2097 abort ();
2098
2099 /* Symbols and expressions. */
2100 default:
9cd96992
JB		 2101 /* Convert symbolic operand to proper sizes for matching, but don't
2102 prevent matching a set of insns that only supports sizes other
2103 than those matching the insn suffix. */
2104 {
2105 unsigned int mask, allowed = 0;
2106 const template *t;
2107
2108 for (t = current_templates->start; t < current_templates->end; ++t)
2109 allowed |= t->operand_types[op];
2110 switch (guess_suffix)
2111 {
2112 case QWORD_MNEM_SUFFIX:
2113 mask = Imm64 | Imm32S;
2114 break;
2115 case LONG_MNEM_SUFFIX:
2116 mask = Imm32;
2117 break;
2118 case WORD_MNEM_SUFFIX:
2119 mask = Imm16;
2120 break;
2121 case BYTE_MNEM_SUFFIX:
2122 mask = Imm8;
2123 break;
2124 default:
2125 mask = 0;
2126 break;
2127 }
2128 if (mask & allowed)
2129 i.types[op] &= mask;
2130 }
29b0f896 2131 break;
252b5132 2132 }
29b0f896
AM		 2133 }
2134}
47926f60 2135
29b0f896
AM		 2136/* Try to use the smallest displacement type too. */
2137static void
2138optimize_disp ()
2139{
2140 int op;
3e73aa7c 2141
29b0f896 2142 for (op = i.operands; --op >= 0;)
b300c311 2143 if (i.types[op] & Disp)
252b5132 2144 {
b300c311 2145 if (i.op[op].disps->X_op == O_constant)
252b5132 2146 {
b300c311 2147 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2148
b300c311
L		 2149 if ((i.types[op] & Disp16)
2150 && (disp & ~(offsetT) 0xffff) == 0)
2151 {
2152 /* If this operand is at most 16 bits, convert
2153 to a signed 16 bit number and don't use 64bit
2154 displacement. */
2155 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2156 i.types[op] &= ~Disp64;
2157 }
2158 if ((i.types[op] & Disp32)
2159 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2160 {
2161 /* If this operand is at most 32 bits, convert
2162 to a signed 32 bit number and don't use 64bit
2163 displacement. */
2164 disp &= (((offsetT) 2 << 31) - 1);
2165 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2166 i.types[op] &= ~Disp64;
2167 }
2168 if (!disp && (i.types[op] & BaseIndex))
2169 {
2170 i.types[op] &= ~Disp;
2171 i.op[op].disps = 0;
2172 i.disp_operands--;
2173 }
2174 else if (flag_code == CODE_64BIT)
2175 {
2176 if (fits_in_signed_long (disp))
28a9d8f5
L		 2177 {
2178 i.types[op] &= ~Disp64;
2179 i.types[op] |= Disp32S;
2180 }
b300c311
L		 2181 if (fits_in_unsigned_long (disp))
2182 i.types[op] |= Disp32;
2183 }
2184 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2185 && fits_in_signed_byte (disp))
2186 i.types[op] |= Disp8;
252b5132 2187 }
b300c311
L		 2188 else
2189 /* We only support 64bit displacement on constants. */
2190 i.types[op] &= ~Disp64;
252b5132 2191 }
29b0f896
AM		 2192}
2193
2194static int
2195match_template ()
2196{
2197 /* Points to template once we've found it. */
2198 const template *t;
2199 unsigned int overlap0, overlap1, overlap2;
2200 unsigned int found_reverse_match;
2201 int suffix_check;
2202
2203#define MATCH(overlap, given, template) \
2204 ((overlap & ~JumpAbsolute) \
2205 && (((given) & (BaseIndex | JumpAbsolute)) \
2206 == ((overlap) & (BaseIndex | JumpAbsolute))))
2207
2208 /* If given types r0 and r1 are registers they must be of the same type
2209 unless the expected operand type register overlap is null.
2210 Note that Acc in a template matches every size of reg. */
2211#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2212 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2213 || ((g0) & Reg) == ((g1) & Reg) \
2214 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2215
2216 overlap0 = 0;
2217 overlap1 = 0;
2218 overlap2 = 0;
2219 found_reverse_match = 0;
2220 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2221 ? No_bSuf
2222 : (i.suffix == WORD_MNEM_SUFFIX
2223 ? No_wSuf
2224 : (i.suffix == SHORT_MNEM_SUFFIX
2225 ? No_sSuf
2226 : (i.suffix == LONG_MNEM_SUFFIX
2227 ? No_lSuf
2228 : (i.suffix == QWORD_MNEM_SUFFIX
2229 ? No_qSuf
2230 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2231 ? No_xSuf : 0))))));
2232
20f0a1fc
NC		 2233 t = current_templates->start;
2234 if (i.suffix == QWORD_MNEM_SUFFIX
2235 && flag_code != CODE_64BIT
9306ca4a
JB		 2236 && (intel_syntax
2237 ? !(t->opcode_modifier & IgnoreSize)
2238 && !intel_float_operand (t->name)
2239 : intel_float_operand (t->name) != 2)
20f0a1fc
NC		 2240 && (!(t->operand_types[0] & (RegMMX | RegXMM))
2241 || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2242 && (t->base_opcode != 0x0fc7
2243 || t->extension_opcode != 1 /* cmpxchg8b */))
2244 t = current_templates->end;
2245 for (; t < current_templates->end; t++)
29b0f896
AM		 2246 {
2247 /* Must have right number of operands. */
2248 if (i.operands != t->operands)
2249 continue;
2250
2251 /* Check the suffix, except for some instructions in intel mode. */
2252 if ((t->opcode_modifier & suffix_check)
2253 && !(intel_syntax
9306ca4a 2254 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2255 continue;
2256
2257 /* Do not verify operands when there are none. */
2258 else if (!t->operands)
2259 {
2260 if (t->cpu_flags & ~cpu_arch_flags)
2261 continue;
2262 /* We've found a match; break out of loop. */
2263 break;
2264 }
252b5132 2265
29b0f896
AM		 2266 overlap0 = i.types[0] & t->operand_types[0];
2267 switch (t->operands)
2268 {
2269 case 1:
2270 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2271 continue;
2272 break;
2273 case 2:
2274 case 3:
2275 overlap1 = i.types[1] & t->operand_types[1];
2276 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2277 || !MATCH (overlap1, i.types[1], t->operand_types[1])
cb712a9e
L		 2278 /* monitor in SSE3 is a very special case. The first
2279 register and the second register may have differnet
2280 sizes. */
2281 || !((t->base_opcode == 0x0f01
2282 && t->extension_opcode == 0xc8)
2283 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2284 t->operand_types[0],
2285 overlap1, i.types[1],
2286 t->operand_types[1])))
29b0f896
AM		 2287 {
2288 /* Check if other direction is valid ... */
2289 if ((t->opcode_modifier & (D | FloatD)) == 0)
2290 continue;
2291
2292 /* Try reversing direction of operands. */
2293 overlap0 = i.types[0] & t->operand_types[1];
2294 overlap1 = i.types[1] & t->operand_types[0];
2295 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2296 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2297 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2298 t->operand_types[1],
2299 overlap1, i.types[1],
2300 t->operand_types[0]))
2301 {
2302 /* Does not match either direction. */
2303 continue;
2304 }
2305 /* found_reverse_match holds which of D or FloatDR
2306 we've found. */
2307 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2308 }
2309 /* Found a forward 2 operand match here. */
2310 else if (t->operands == 3)
2311 {
2312 /* Here we make use of the fact that there are no
2313 reverse match 3 operand instructions, and all 3
2314 operand instructions only need to be checked for
2315 register consistency between operands 2 and 3. */
2316 overlap2 = i.types[2] & t->operand_types[2];
2317 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2318 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2319 t->operand_types[1],
2320 overlap2, i.types[2],
2321 t->operand_types[2]))
2322
2323 continue;
2324 }
2325 /* Found either forward/reverse 2 or 3 operand match here:
2326 slip through to break. */
2327 }
2328 if (t->cpu_flags & ~cpu_arch_flags)
2329 {
2330 found_reverse_match = 0;
2331 continue;
2332 }
2333 /* We've found a match; break out of loop. */
2334 break;
2335 }
2336
2337 if (t == current_templates->end)
2338 {
2339 /* We found no match. */
2340 as_bad (_("suffix or operands invalid for `%s'"),
2341 current_templates->start->name);
2342 return 0;
2343 }
252b5132 2344
29b0f896
AM		 2345 if (!quiet_warnings)
2346 {
2347 if (!intel_syntax
2348 && ((i.types[0] & JumpAbsolute)
2349 != (t->operand_types[0] & JumpAbsolute)))
2350 {
2351 as_warn (_("indirect %s without `*'"), t->name);
2352 }
2353
2354 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2355 == (IsPrefix | IgnoreSize))
2356 {
2357 /* Warn them that a data or address size prefix doesn't
2358 affect assembly of the next line of code. */
2359 as_warn (_("stand-alone `%s' prefix"), t->name);
2360 }
2361 }
2362
2363 /* Copy the template we found. */
2364 i.tm = *t;
2365 if (found_reverse_match)
2366 {
2367 /* If we found a reverse match we must alter the opcode
2368 direction bit. found_reverse_match holds bits to change
2369 (different for int & float insns). */
2370
2371 i.tm.base_opcode ^= found_reverse_match;
2372
2373 i.tm.operand_types[0] = t->operand_types[1];
2374 i.tm.operand_types[1] = t->operand_types[0];
2375 }
2376
2377 return 1;
2378}
2379
2380static int
2381check_string ()
2382{
2383 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2384 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2385 {
2386 if (i.seg[0] != NULL && i.seg[0] != &es)
2387 {
2388 as_bad (_("`%s' operand %d must use `%%es' segment"),
2389 i.tm.name,
2390 mem_op + 1);
2391 return 0;
2392 }
2393 /* There's only ever one segment override allowed per instruction.
2394 This instruction possibly has a legal segment override on the
2395 second operand, so copy the segment to where non-string
2396 instructions store it, allowing common code. */
2397 i.seg[0] = i.seg[1];
2398 }
2399 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2400 {
2401 if (i.seg[1] != NULL && i.seg[1] != &es)
2402 {
2403 as_bad (_("`%s' operand %d must use `%%es' segment"),
2404 i.tm.name,
2405 mem_op + 2);
2406 return 0;
2407 }
2408 }
2409 return 1;
2410}
2411
2412static int
543613e9 2413process_suffix (void)
29b0f896
AM		 2414{
2415 /* If matched instruction specifies an explicit instruction mnemonic
2416 suffix, use it. */
2417 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2418 {
2419 if (i.tm.opcode_modifier & Size16)
2420 i.suffix = WORD_MNEM_SUFFIX;
2421 else if (i.tm.opcode_modifier & Size64)
2422 i.suffix = QWORD_MNEM_SUFFIX;
2423 else
2424 i.suffix = LONG_MNEM_SUFFIX;
2425 }
2426 else if (i.reg_operands)
2427 {
2428 /* If there's no instruction mnemonic suffix we try to invent one
2429 based on register operands. */
2430 if (!i.suffix)
2431 {
2432 /* We take i.suffix from the last register operand specified,
2433 Destination register type is more significant than source
2434 register type. */
2435 int op;
543613e9 2436
29b0f896
AM		 2437 for (op = i.operands; --op >= 0;)
2438 if ((i.types[op] & Reg)
2439 && !(i.tm.operand_types[op] & InOutPortReg))
2440 {
2441 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2442 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2443 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2444 LONG_MNEM_SUFFIX);
2445 break;
2446 }
2447 }
2448 else if (i.suffix == BYTE_MNEM_SUFFIX)
2449 {
2450 if (!check_byte_reg ())
2451 return 0;
2452 }
2453 else if (i.suffix == LONG_MNEM_SUFFIX)
2454 {
2455 if (!check_long_reg ())
2456 return 0;
2457 }
2458 else if (i.suffix == QWORD_MNEM_SUFFIX)
2459 {
2460 if (!check_qword_reg ())
2461 return 0;
2462 }
2463 else if (i.suffix == WORD_MNEM_SUFFIX)
2464 {
2465 if (!check_word_reg ())
2466 return 0;
2467 }
2468 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2469 /* Do nothing if the instruction is going to ignore the prefix. */
2470 ;
2471 else
2472 abort ();
2473 }
9306ca4a
JB		 2474 else if ((i.tm.opcode_modifier & DefaultSize)
2475 && !i.suffix
2476 /* exclude fldenv/frstor/fsave/fstenv */
2477 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2478 {
2479 i.suffix = stackop_size;
2480 }
9306ca4a
JB		 2481 else if (intel_syntax
2482 && !i.suffix
2483 && ((i.tm.operand_types[0] & JumpAbsolute)
2484 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2485 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2486 && i.tm.extension_opcode <= 3)))
2487 {
2488 switch (flag_code)
2489 {
2490 case CODE_64BIT:
2491 if (!(i.tm.opcode_modifier & No_qSuf))
2492 {
2493 i.suffix = QWORD_MNEM_SUFFIX;
2494 break;
2495 }
2496 case CODE_32BIT:
2497 if (!(i.tm.opcode_modifier & No_lSuf))
2498 i.suffix = LONG_MNEM_SUFFIX;
2499 break;
2500 case CODE_16BIT:
2501 if (!(i.tm.opcode_modifier & No_wSuf))
2502 i.suffix = WORD_MNEM_SUFFIX;
2503 break;
2504 }
2505 }
252b5132 2506
9306ca4a 2507 if (!i.suffix)
29b0f896 2508 {
9306ca4a
JB		 2509 if (!intel_syntax)
2510 {
2511 if (i.tm.opcode_modifier & W)
2512 {
2513 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2514 return 0;
2515 }
2516 }
2517 else
2518 {
2519 unsigned int suffixes = ~i.tm.opcode_modifier
2520 & (No_bSuf
2521 | No_wSuf
2522 | No_lSuf
2523 | No_sSuf
2524 | No_xSuf
2525 | No_qSuf);
2526
2527 if ((i.tm.opcode_modifier & W)
2528 || ((suffixes & (suffixes - 1))
2529 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2530 {
2531 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2532 return 0;
2533 }
2534 }
29b0f896 2535 }
252b5132 2536
9306ca4a
JB		 2537 /* Change the opcode based on the operand size given by i.suffix;
2538 We don't need to change things for byte insns. */
2539
29b0f896
AM		 2540 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2541 {
2542 /* It's not a byte, select word/dword operation. */
2543 if (i.tm.opcode_modifier & W)
2544 {
2545 if (i.tm.opcode_modifier & ShortForm)
2546 i.tm.base_opcode |= 8;
2547 else
2548 i.tm.base_opcode |= 1;
2549 }
0f3f3d8b 2550
29b0f896
AM		 2551 /* Now select between word & dword operations via the operand
2552 size prefix, except for instructions that will ignore this
2553 prefix anyway. */
cb712a9e
L		 2554 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
2555 {
2556 /* monitor in SSE3 is a very special case. The default size
2557 of AX is the size of mode. The address size override
2558 prefix will change the size of AX. */
2559 if (i.op->regs[0].reg_type &
2560 (flag_code == CODE_32BIT ? Reg16 : Reg32))
2561 if (!add_prefix (ADDR_PREFIX_OPCODE))
2562 return 0;
2563 }
2564 else if (i.suffix != QWORD_MNEM_SUFFIX
2565 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2566 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2567 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2568 || (flag_code == CODE_64BIT
2569 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2570 {
2571 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 2572
29b0f896
AM		 2573 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2574 prefix = ADDR_PREFIX_OPCODE;
252b5132 2575
29b0f896
AM		 2576 if (!add_prefix (prefix))
2577 return 0;
24eab124 2578 }
252b5132 2579
29b0f896
AM		 2580 /* Set mode64 for an operand. */
2581 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2582 && flag_code == CODE_64BIT
29b0f896 2583 && (i.tm.opcode_modifier & NoRex64) == 0)
9146926a 2584 i.rex |= REX_MODE64;
3e73aa7c 2585
29b0f896
AM		 2586 /* Size floating point instruction. */
2587 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 2588 if (i.tm.opcode_modifier & FloatMF)
2589 i.tm.base_opcode ^= 4;
29b0f896 2590 }
7ecd2f8b 2591
29b0f896
AM		 2592 return 1;
2593}
3e73aa7c 2594
29b0f896 2595static int
543613e9 2596check_byte_reg (void)
29b0f896
AM		 2597{
2598 int op;
543613e9 2599
29b0f896
AM		 2600 for (op = i.operands; --op >= 0;)
2601 {
2602 /* If this is an eight bit register, it's OK. If it's the 16 or
2603 32 bit version of an eight bit register, we will just use the
2604 low portion, and that's OK too. */
2605 if (i.types[op] & Reg8)
2606 continue;
2607
2608 /* movzx and movsx should not generate this warning. */
2609 if (intel_syntax
2610 && (i.tm.base_opcode == 0xfb7
2611 || i.tm.base_opcode == 0xfb6
2612 || i.tm.base_opcode == 0x63
2613 || i.tm.base_opcode == 0xfbe
2614 || i.tm.base_opcode == 0xfbf))
2615 continue;
2616
65ec77d2 2617 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 2618 {
2619 /* Prohibit these changes in the 64bit mode, since the
2620 lowering is more complicated. */
2621 if (flag_code == CODE_64BIT
2622 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2623 {
0f3f3d8b 2624 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2625 i.op[op].regs->reg_name,
2626 i.suffix);
2627 return 0;
2628 }
2629#if REGISTER_WARNINGS
2630 if (!quiet_warnings
2631 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2632 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2633 (i.op[op].regs + (i.types[op] & Reg16
2634 ? REGNAM_AL - REGNAM_AX
2635 : REGNAM_AL - REGNAM_EAX))->reg_name,
2636 i.op[op].regs->reg_name,
2637 i.suffix);
2638#endif
2639 continue;
2640 }
2641 /* Any other register is bad. */
2642 if (i.types[op] & (Reg | RegMMX | RegXMM
2643 | SReg2 | SReg3
2644 | Control | Debug | Test
2645 | FloatReg | FloatAcc))
2646 {
2647 as_bad (_("`%%%s' not allowed with `%s%c'"),
2648 i.op[op].regs->reg_name,
2649 i.tm.name,
2650 i.suffix);
2651 return 0;
2652 }
2653 }
2654 return 1;
2655}
2656
2657static int
2658check_long_reg ()
2659{
2660 int op;
2661
2662 for (op = i.operands; --op >= 0;)
2663 /* Reject eight bit registers, except where the template requires
2664 them. (eg. movzb) */
2665 if ((i.types[op] & Reg8) != 0
2666 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2667 {
2668 as_bad (_("`%%%s' not allowed with `%s%c'"),
2669 i.op[op].regs->reg_name,
2670 i.tm.name,
2671 i.suffix);
2672 return 0;
2673 }
2674 /* Warn if the e prefix on a general reg is missing. */
2675 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2676 && (i.types[op] & Reg16) != 0
2677 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2678 {
2679 /* Prohibit these changes in the 64bit mode, since the
2680 lowering is more complicated. */
2681 if (flag_code == CODE_64BIT)
252b5132 2682 {
0f3f3d8b 2683 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2684 i.op[op].regs->reg_name,
2685 i.suffix);
2686 return 0;
252b5132 2687 }
29b0f896
AM		 2688#if REGISTER_WARNINGS
2689 else
2690 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2691 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2692 i.op[op].regs->reg_name,
2693 i.suffix);
2694#endif
252b5132 2695 }
29b0f896
AM		 2696 /* Warn if the r prefix on a general reg is missing. */
2697 else if ((i.types[op] & Reg64) != 0
2698 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 2699 {
0f3f3d8b 2700 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2701 i.op[op].regs->reg_name,
2702 i.suffix);
2703 return 0;
2704 }
2705 return 1;
2706}
252b5132 2707
29b0f896
AM		 2708static int
2709check_qword_reg ()
2710{
2711 int op;
252b5132 2712
29b0f896
AM		 2713 for (op = i.operands; --op >= 0; )
2714 /* Reject eight bit registers, except where the template requires
2715 them. (eg. movzb) */
2716 if ((i.types[op] & Reg8) != 0
2717 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2718 {
2719 as_bad (_("`%%%s' not allowed with `%s%c'"),
2720 i.op[op].regs->reg_name,
2721 i.tm.name,
2722 i.suffix);
2723 return 0;
2724 }
2725 /* Warn if the e prefix on a general reg is missing. */
2726 else if (((i.types[op] & Reg16) != 0
2727 || (i.types[op] & Reg32) != 0)
2728 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2729 {
2730 /* Prohibit these changes in the 64bit mode, since the
2731 lowering is more complicated. */
0f3f3d8b 2732 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2733 i.op[op].regs->reg_name,
2734 i.suffix);
2735 return 0;
252b5132 2736 }
29b0f896
AM		 2737 return 1;
2738}
252b5132 2739
29b0f896
AM		 2740static int
2741check_word_reg ()
2742{
2743 int op;
2744 for (op = i.operands; --op >= 0;)
2745 /* Reject eight bit registers, except where the template requires
2746 them. (eg. movzb) */
2747 if ((i.types[op] & Reg8) != 0
2748 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2749 {
2750 as_bad (_("`%%%s' not allowed with `%s%c'"),
2751 i.op[op].regs->reg_name,
2752 i.tm.name,
2753 i.suffix);
2754 return 0;
2755 }
2756 /* Warn if the e prefix on a general reg is present. */
2757 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2758 && (i.types[op] & Reg32) != 0
2759 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 2760 {
29b0f896
AM		 2761 /* Prohibit these changes in the 64bit mode, since the
2762 lowering is more complicated. */
2763 if (flag_code == CODE_64BIT)
252b5132 2764 {
0f3f3d8b 2765 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2766 i.op[op].regs->reg_name,
2767 i.suffix);
2768 return 0;
252b5132 2769 }
29b0f896
AM		 2770 else
2771#if REGISTER_WARNINGS
2772 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2773 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2774 i.op[op].regs->reg_name,
2775 i.suffix);
2776#endif
2777 }
2778 return 1;
2779}
252b5132 2780
29b0f896
AM		 2781static int
2782finalize_imm ()
2783{
2784 unsigned int overlap0, overlap1, overlap2;
2785
2786 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 2787 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 2788 && overlap0 != Imm8 && overlap0 != Imm8S
2789 && overlap0 != Imm16 && overlap0 != Imm32S
2790 && overlap0 != Imm32 && overlap0 != Imm64)
2791 {
2792 if (i.suffix)
2793 {
2794 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2795 ? Imm8 | Imm8S
2796 : (i.suffix == WORD_MNEM_SUFFIX
2797 ? Imm16
2798 : (i.suffix == QWORD_MNEM_SUFFIX
2799 ? Imm64 | Imm32S
2800 : Imm32)));
2801 }
2802 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2803 || overlap0 == (Imm16 | Imm32)
2804 || overlap0 == (Imm16 | Imm32S))
2805 {
2806 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2807 ? Imm16 : Imm32S);
2808 }
2809 if (overlap0 != Imm8 && overlap0 != Imm8S
2810 && overlap0 != Imm16 && overlap0 != Imm32S
2811 && overlap0 != Imm32 && overlap0 != Imm64)
2812 {
2813 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2814 return 0;
2815 }
2816 }
2817 i.types[0] = overlap0;
2818
2819 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 2820 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 2821 && overlap1 != Imm8 && overlap1 != Imm8S
2822 && overlap1 != Imm16 && overlap1 != Imm32S
2823 && overlap1 != Imm32 && overlap1 != Imm64)
2824 {
2825 if (i.suffix)
2826 {
2827 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2828 ? Imm8 | Imm8S
2829 : (i.suffix == WORD_MNEM_SUFFIX
2830 ? Imm16
2831 : (i.suffix == QWORD_MNEM_SUFFIX
2832 ? Imm64 | Imm32S
2833 : Imm32)));
2834 }
2835 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2836 || overlap1 == (Imm16 | Imm32)
2837 || overlap1 == (Imm16 | Imm32S))
2838 {
2839 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2840 ? Imm16 : Imm32S);
2841 }
2842 if (overlap1 != Imm8 && overlap1 != Imm8S
2843 && overlap1 != Imm16 && overlap1 != Imm32S
2844 && overlap1 != Imm32 && overlap1 != Imm64)
2845 {
2846 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2847 return 0;
2848 }
2849 }
2850 i.types[1] = overlap1;
2851
2852 overlap2 = i.types[2] & i.tm.operand_types[2];
2853 assert ((overlap2 & Imm) == 0);
2854 i.types[2] = overlap2;
2855
2856 return 1;
2857}
2858
2859static int
2860process_operands ()
2861{
2862 /* Default segment register this instruction will use for memory
2863 accesses. 0 means unknown. This is only for optimizing out
2864 unnecessary segment overrides. */
2865 const seg_entry *default_seg = 0;
2866
2867 /* The imul $imm, %reg instruction is converted into
2868 imul $imm, %reg, %reg, and the clr %reg instruction
2869 is converted into xor %reg, %reg. */
2870 if (i.tm.opcode_modifier & regKludge)
2871 {
2872 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2873 /* Pretend we saw the extra register operand. */
2874 assert (i.op[first_reg_op + 1].regs == 0);
2875 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2876 i.types[first_reg_op + 1] = i.types[first_reg_op];
2877 i.reg_operands = 2;
2878 }
2879
2880 if (i.tm.opcode_modifier & ShortForm)
2881 {
2882 /* The register or float register operand is in operand 0 or 1. */
2883 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2884 /* Register goes in low 3 bits of opcode. */
2885 i.tm.base_opcode |= i.op[op].regs->reg_num;
2886 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2887 i.rex |= REX_EXTZ;
2888 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2889 {
2890 /* Warn about some common errors, but press on regardless.
2891 The first case can be generated by gcc (<= 2.8.1). */
2892 if (i.operands == 2)
2893 {
2894 /* Reversed arguments on faddp, fsubp, etc. */
2895 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2896 i.op[1].regs->reg_name,
2897 i.op[0].regs->reg_name);
2898 }
2899 else
2900 {
2901 /* Extraneous `l' suffix on fp insn. */
2902 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2903 i.op[0].regs->reg_name);
2904 }
2905 }
2906 }
2907 else if (i.tm.opcode_modifier & Modrm)
2908 {
2909 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 2910 must be put into the modrm byte). Now, we make the modrm and
2911 index base bytes based on all the info we've collected. */
29b0f896
AM		 2912
2913 default_seg = build_modrm_byte ();
2914 }
2915 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2916 {
2917 if (i.tm.base_opcode == POP_SEG_SHORT
2918 && i.op[0].regs->reg_num == 1)
2919 {
2920 as_bad (_("you can't `pop %%cs'"));
2921 return 0;
2922 }
2923 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2924 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2925 i.rex |= REX_EXTZ;
2926 }
2927 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2928 {
2929 default_seg = &ds;
2930 }
2931 else if ((i.tm.opcode_modifier & IsString) != 0)
2932 {
2933 /* For the string instructions that allow a segment override
2934 on one of their operands, the default segment is ds. */
2935 default_seg = &ds;
2936 }
2937
30123838
JB		 2938 if ((i.tm.base_opcode == 0x8d /* lea */
2939 || (i.tm.cpu_flags & CpuSVME))
2940 && i.seg[0] && !quiet_warnings)
2941 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 2942
2943 /* If a segment was explicitly specified, and the specified segment
2944 is not the default, use an opcode prefix to select it. If we
2945 never figured out what the default segment is, then default_seg
2946 will be zero at this point, and the specified segment prefix will
2947 always be used. */
29b0f896
AM		 2948 if ((i.seg[0]) && (i.seg[0] != default_seg))
2949 {
2950 if (!add_prefix (i.seg[0]->seg_prefix))
2951 return 0;
2952 }
2953 return 1;
2954}
2955
2956static const seg_entry *
2957build_modrm_byte ()
2958{
2959 const seg_entry *default_seg = 0;
2960
2961 /* i.reg_operands MUST be the number of real register operands;
2962 implicit registers do not count. */
2963 if (i.reg_operands == 2)
2964 {
2965 unsigned int source, dest;
2966 source = ((i.types[0]
2967 & (Reg | RegMMX | RegXMM
2968 | SReg2 | SReg3
2969 | Control | Debug | Test))
2970 ? 0 : 1);
2971 dest = source + 1;
2972
2973 i.rm.mode = 3;
2974 /* One of the register operands will be encoded in the i.tm.reg
2975 field, the other in the combined i.tm.mode and i.tm.regmem
2976 fields. If no form of this instruction supports a memory
2977 destination operand, then we assume the source operand may
2978 sometimes be a memory operand and so we need to store the
2979 destination in the i.rm.reg field. */
2980 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2981 {
2982 i.rm.reg = i.op[dest].regs->reg_num;
2983 i.rm.regmem = i.op[source].regs->reg_num;
2984 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2985 i.rex |= REX_EXTX;
2986 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2987 i.rex |= REX_EXTZ;
2988 }
2989 else
2990 {
2991 i.rm.reg = i.op[source].regs->reg_num;
2992 i.rm.regmem = i.op[dest].regs->reg_num;
2993 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2994 i.rex |= REX_EXTZ;
2995 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2996 i.rex |= REX_EXTX;
2997 }
c4a530c5
JB		 2998 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
2999 {
3000 if (!((i.types[0] | i.types[1]) & Control))
3001 abort ();
3002 i.rex &= ~(REX_EXTX | REX_EXTZ);
3003 add_prefix (LOCK_PREFIX_OPCODE);
3004 }
29b0f896
AM		 3005 }
3006 else
3007 { /* If it's not 2 reg operands... */
3008 if (i.mem_operands)
3009 {
3010 unsigned int fake_zero_displacement = 0;
3011 unsigned int op = ((i.types[0] & AnyMem)
3012 ? 0
3013 : (i.types[1] & AnyMem) ? 1 : 2);
3014
3015 default_seg = &ds;
3016
3017 if (i.base_reg == 0)
3018 {
3019 i.rm.mode = 0;
3020 if (!i.disp_operands)
3021 fake_zero_displacement = 1;
3022 if (i.index_reg == 0)
3023 {
3024 /* Operand is just <disp> */
20f0a1fc 3025 if (flag_code == CODE_64BIT)
29b0f896
AM		 3026 {
3027 /* 64bit mode overwrites the 32bit absolute
3028 addressing by RIP relative addressing and
3029 absolute addressing is encoded by one of the
3030 redundant SIB forms. */
3031 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3032 i.sib.base = NO_BASE_REGISTER;
3033 i.sib.index = NO_INDEX_REGISTER;
20f0a1fc
NC		 3034 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
3035 }
3036 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3037 {
3038 i.rm.regmem = NO_BASE_REGISTER_16;
3039 i.types[op] = Disp16;
3040 }
3041 else
3042 {
3043 i.rm.regmem = NO_BASE_REGISTER;
3044 i.types[op] = Disp32;
29b0f896
AM		 3045 }
3046 }
3047 else /* !i.base_reg && i.index_reg */
3048 {
3049 i.sib.index = i.index_reg->reg_num;
3050 i.sib.base = NO_BASE_REGISTER;
3051 i.sib.scale = i.log2_scale_factor;
3052 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3053 i.types[op] &= ~Disp;
3054 if (flag_code != CODE_64BIT)
3055 i.types[op] |= Disp32; /* Must be 32 bit */
3056 else
3057 i.types[op] |= Disp32S;
3058 if ((i.index_reg->reg_flags & RegRex) != 0)
3059 i.rex |= REX_EXTY;
3060 }
3061 }
3062 /* RIP addressing for 64bit mode. */
3063 else if (i.base_reg->reg_type == BaseIndex)
3064 {
3065 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3066 i.types[op] &= ~ Disp;
29b0f896
AM		 3067 i.types[op] |= Disp32S;
3068 i.flags[op] = Operand_PCrel;
20f0a1fc
NC		 3069 if (! i.disp_operands)
3070 fake_zero_displacement = 1;
29b0f896
AM		 3071 }
3072 else if (i.base_reg->reg_type & Reg16)
3073 {
3074 switch (i.base_reg->reg_num)
3075 {
3076 case 3: /* (%bx) */
3077 if (i.index_reg == 0)
3078 i.rm.regmem = 7;
3079 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3080 i.rm.regmem = i.index_reg->reg_num - 6;
3081 break;
3082 case 5: /* (%bp) */
3083 default_seg = &ss;
3084 if (i.index_reg == 0)
3085 {
3086 i.rm.regmem = 6;
3087 if ((i.types[op] & Disp) == 0)
3088 {
3089 /* fake (%bp) into 0(%bp) */
3090 i.types[op] |= Disp8;
252b5132 3091 fake_zero_displacement = 1;
29b0f896
AM		 3092 }
3093 }
3094 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3095 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3096 break;
3097 default: /* (%si) -> 4 or (%di) -> 5 */
3098 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3099 }
3100 i.rm.mode = mode_from_disp_size (i.types[op]);
3101 }
3102 else /* i.base_reg and 32/64 bit mode */
3103 {
3104 if (flag_code == CODE_64BIT
3105 && (i.types[op] & Disp))
20f0a1fc
NC		 3106 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
3107
29b0f896
AM		 3108 i.rm.regmem = i.base_reg->reg_num;
3109 if ((i.base_reg->reg_flags & RegRex) != 0)
3110 i.rex |= REX_EXTZ;
3111 i.sib.base = i.base_reg->reg_num;
3112 /* x86-64 ignores REX prefix bit here to avoid decoder
3113 complications. */
3114 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3115 {
3116 default_seg = &ss;
3117 if (i.disp_operands == 0)
3118 {
3119 fake_zero_displacement = 1;
3120 i.types[op] |= Disp8;
3121 }
3122 }
3123 else if (i.base_reg->reg_num == ESP_REG_NUM)
3124 {
3125 default_seg = &ss;
3126 }
3127 i.sib.scale = i.log2_scale_factor;
3128 if (i.index_reg == 0)
3129 {
3130 /* <disp>(%esp) becomes two byte modrm with no index
3131 register. We've already stored the code for esp
3132 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3133 Any base register besides %esp will not use the
3134 extra modrm byte. */
3135 i.sib.index = NO_INDEX_REGISTER;
3136#if !SCALE1_WHEN_NO_INDEX
3137 /* Another case where we force the second modrm byte. */
3138 if (i.log2_scale_factor)
3139 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3140#endif
29b0f896
AM		 3141 }
3142 else
3143 {
3144 i.sib.index = i.index_reg->reg_num;
3145 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3146 if ((i.index_reg->reg_flags & RegRex) != 0)
3147 i.rex |= REX_EXTY;
3148 }
3149 i.rm.mode = mode_from_disp_size (i.types[op]);
3150 }
252b5132 3151
29b0f896
AM		 3152 if (fake_zero_displacement)
3153 {
3154 /* Fakes a zero displacement assuming that i.types[op]
3155 holds the correct displacement size. */
3156 expressionS *exp;
3157
3158 assert (i.op[op].disps == 0);
3159 exp = &disp_expressions[i.disp_operands++];
3160 i.op[op].disps = exp;
3161 exp->X_op = O_constant;
3162 exp->X_add_number = 0;
3163 exp->X_add_symbol = (symbolS *) 0;
3164 exp->X_op_symbol = (symbolS *) 0;
3165 }
3166 }
252b5132 3167
29b0f896
AM		 3168 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3169 (if any) based on i.tm.extension_opcode. Again, we must be
3170 careful to make sure that segment/control/debug/test/MMX
3171 registers are coded into the i.rm.reg field. */
3172 if (i.reg_operands)
3173 {
3174 unsigned int op =
3175 ((i.types[0]
3176 & (Reg | RegMMX | RegXMM
3177 | SReg2 | SReg3
3178 | Control | Debug | Test))
3179 ? 0
3180 : ((i.types[1]
3181 & (Reg | RegMMX | RegXMM
3182 | SReg2 | SReg3
3183 | Control | Debug | Test))
3184 ? 1
3185 : 2));
3186 /* If there is an extension opcode to put here, the register
3187 number must be put into the regmem field. */
3188 if (i.tm.extension_opcode != None)
3189 {
3190 i.rm.regmem = i.op[op].regs->reg_num;
3191 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3192 i.rex |= REX_EXTZ;
3193 }
3194 else
3195 {
3196 i.rm.reg = i.op[op].regs->reg_num;
3197 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3198 i.rex |= REX_EXTX;
3199 }
252b5132 3200
29b0f896
AM		 3201 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3202 must set it to 3 to indicate this is a register operand
3203 in the regmem field. */
3204 if (!i.mem_operands)
3205 i.rm.mode = 3;
3206 }
252b5132 3207
29b0f896
AM		 3208 /* Fill in i.rm.reg field with extension opcode (if any). */
3209 if (i.tm.extension_opcode != None)
3210 i.rm.reg = i.tm.extension_opcode;
3211 }
3212 return default_seg;
3213}
252b5132 3214
29b0f896
AM		 3215static void
3216output_branch ()
3217{
3218 char *p;
3219 int code16;
3220 int prefix;
3221 relax_substateT subtype;
3222 symbolS *sym;
3223 offsetT off;
3224
3225 code16 = 0;
3226 if (flag_code == CODE_16BIT)
3227 code16 = CODE16;
3228
3229 prefix = 0;
3230 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3231 {
29b0f896
AM		 3232 prefix = 1;
3233 i.prefixes -= 1;
3234 code16 ^= CODE16;
252b5132 3235 }
29b0f896
AM		 3236 /* Pentium4 branch hints. */
3237 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3238 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3239 {
29b0f896
AM		 3240 prefix++;
3241 i.prefixes--;
3242 }
3243 if (i.prefix[REX_PREFIX] != 0)
3244 {
3245 prefix++;
3246 i.prefixes--;
2f66722d
AM		 3247 }
3248
29b0f896
AM		 3249 if (i.prefixes != 0 && !intel_syntax)
3250 as_warn (_("skipping prefixes on this instruction"));
3251
3252 /* It's always a symbol; End frag & setup for relax.
3253 Make sure there is enough room in this frag for the largest
3254 instruction we may generate in md_convert_frag. This is 2
3255 bytes for the opcode and room for the prefix and largest
3256 displacement. */
3257 frag_grow (prefix + 2 + 4);
3258 /* Prefix and 1 opcode byte go in fr_fix. */
3259 p = frag_more (prefix + 1);
3260 if (i.prefix[DATA_PREFIX] != 0)
3261 *p++ = DATA_PREFIX_OPCODE;
3262 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3263 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3264 *p++ = i.prefix[SEG_PREFIX];
3265 if (i.prefix[REX_PREFIX] != 0)
3266 *p++ = i.prefix[REX_PREFIX];
3267 *p = i.tm.base_opcode;
3268
3269 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3270 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3271 else if ((cpu_arch_flags & Cpu386) != 0)
3272 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3273 else
3274 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3275 subtype |= code16;
3e73aa7c 3276
29b0f896
AM		 3277 sym = i.op[0].disps->X_add_symbol;
3278 off = i.op[0].disps->X_add_number;
3e73aa7c 3279
29b0f896
AM		 3280 if (i.op[0].disps->X_op != O_constant
3281 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3282 {
29b0f896
AM		 3283 /* Handle complex expressions. */
3284 sym = make_expr_symbol (i.op[0].disps);
3285 off = 0;
3286 }
3e73aa7c 3287
29b0f896
AM		 3288 /* 1 possible extra opcode + 4 byte displacement go in var part.
3289 Pass reloc in fr_var. */
3290 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3291}
3e73aa7c 3292
29b0f896
AM		 3293static void
3294output_jump ()
3295{
3296 char *p;
3297 int size;
3e02c1cc 3298 fixS *fixP;
29b0f896
AM		 3299
3300 if (i.tm.opcode_modifier & JumpByte)
3301 {
3302 /* This is a loop or jecxz type instruction. */
3303 size = 1;
3304 if (i.prefix[ADDR_PREFIX] != 0)
3305 {
3306 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3307 i.prefixes -= 1;
3308 }
3309 /* Pentium4 branch hints. */
3310 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3311 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3312 {
3313 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3314 i.prefixes--;
3e73aa7c
JH		 3315 }
3316 }
29b0f896
AM		 3317 else
3318 {
3319 int code16;
3e73aa7c 3320
29b0f896
AM		 3321 code16 = 0;
3322 if (flag_code == CODE_16BIT)
3323 code16 = CODE16;
3e73aa7c 3324
29b0f896
AM		 3325 if (i.prefix[DATA_PREFIX] != 0)
3326 {
3327 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3328 i.prefixes -= 1;
3329 code16 ^= CODE16;
3330 }
252b5132 3331
29b0f896
AM		 3332 size = 4;
3333 if (code16)
3334 size = 2;
3335 }
9fcc94b6 3336
29b0f896
AM		 3337 if (i.prefix[REX_PREFIX] != 0)
3338 {
3339 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3340 i.prefixes -= 1;
3341 }
252b5132 3342
29b0f896
AM		 3343 if (i.prefixes != 0 && !intel_syntax)
3344 as_warn (_("skipping prefixes on this instruction"));
e0890092 3345
29b0f896
AM		 3346 p = frag_more (1 + size);
3347 *p++ = i.tm.base_opcode;
e0890092 3348
3e02c1cc
AM		 3349 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3350 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3351
3352 /* All jumps handled here are signed, but don't use a signed limit
3353 check for 32 and 16 bit jumps as we want to allow wrap around at
3354 4G and 64k respectively. */
3355 if (size == 1)
3356 fixP->fx_signed = 1;
29b0f896 3357}
e0890092 3358
29b0f896
AM		 3359static void
3360output_interseg_jump ()
3361{
3362 char *p;
3363 int size;
3364 int prefix;
3365 int code16;
252b5132 3366
29b0f896
AM		 3367 code16 = 0;
3368 if (flag_code == CODE_16BIT)
3369 code16 = CODE16;
a217f122 3370
29b0f896
AM		 3371 prefix = 0;
3372 if (i.prefix[DATA_PREFIX] != 0)
3373 {
3374 prefix = 1;
3375 i.prefixes -= 1;
3376 code16 ^= CODE16;
3377 }
3378 if (i.prefix[REX_PREFIX] != 0)
3379 {
3380 prefix++;
3381 i.prefixes -= 1;
3382 }
252b5132 3383
29b0f896
AM		 3384 size = 4;
3385 if (code16)
3386 size = 2;
252b5132 3387
29b0f896
AM		 3388 if (i.prefixes != 0 && !intel_syntax)
3389 as_warn (_("skipping prefixes on this instruction"));
252b5132 3390
29b0f896
AM		 3391 /* 1 opcode; 2 segment; offset */
3392 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3393
29b0f896
AM		 3394 if (i.prefix[DATA_PREFIX] != 0)
3395 *p++ = DATA_PREFIX_OPCODE;
252b5132 3396
29b0f896
AM		 3397 if (i.prefix[REX_PREFIX] != 0)
3398 *p++ = i.prefix[REX_PREFIX];
252b5132 3399
29b0f896
AM		 3400 *p++ = i.tm.base_opcode;
3401 if (i.op[1].imms->X_op == O_constant)
3402 {
3403 offsetT n = i.op[1].imms->X_add_number;
252b5132 3404
29b0f896
AM		 3405 if (size == 2
3406 && !fits_in_unsigned_word (n)
3407 && !fits_in_signed_word (n))
3408 {
3409 as_bad (_("16-bit jump out of range"));
3410 return;
3411 }
3412 md_number_to_chars (p, n, size);
3413 }
3414 else
3415 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3416 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3417 if (i.op[0].imms->X_op != O_constant)
3418 as_bad (_("can't handle non absolute segment in `%s'"),
3419 i.tm.name);
3420 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3421}
a217f122 3422
29b0f896
AM		 3423static void
3424output_insn ()
3425{
2bbd9c25
JJ		 3426 fragS *insn_start_frag;
3427 offsetT insn_start_off;
3428
29b0f896
AM		 3429 /* Tie dwarf2 debug info to the address at the start of the insn.
3430 We can't do this after the insn has been output as the current
3431 frag may have been closed off. eg. by frag_var. */
3432 dwarf2_emit_insn (0);
3433
2bbd9c25
JJ		 3434 insn_start_frag = frag_now;
3435 insn_start_off = frag_now_fix ();
3436
29b0f896
AM		 3437 /* Output jumps. */
3438 if (i.tm.opcode_modifier & Jump)
3439 output_branch ();
3440 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3441 output_jump ();
3442 else if (i.tm.opcode_modifier & JumpInterSegment)
3443 output_interseg_jump ();
3444 else
3445 {
3446 /* Output normal instructions here. */
3447 char *p;
3448 unsigned char *q;
252b5132 3449
bc4bd9ab
MK		 3450 /* All opcodes on i386 have either 1 or 2 bytes. We may use one
3451 more higher byte to specify a prefix the instruction
3452 requires. */
3453 if ((i.tm.base_opcode & 0xff0000) != 0)
3454 {
3455 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3456 {
3457 unsigned int prefix;
3458 prefix = (i.tm.base_opcode >> 16) & 0xff;
3459
3460 if (prefix != REPE_PREFIX_OPCODE
3461 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3462 add_prefix (prefix);
3463 }
3464 else
3465 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
0f10071e 3466 }
252b5132 3467
29b0f896
AM		 3468 /* The prefix bytes. */
3469 for (q = i.prefix;
3470 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3471 q++)
3472 {
3473 if (*q)
3474 {
3475 p = frag_more (1);
3476 md_number_to_chars (p, (valueT) *q, 1);
3477 }
3478 }
252b5132 3479
29b0f896
AM		 3480 /* Now the opcode; be careful about word order here! */
3481 if (fits_in_unsigned_byte (i.tm.base_opcode))
3482 {
3483 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3484 }
3485 else
3486 {
bc4bd9ab 3487 p = frag_more (2);
0f10071e 3488
29b0f896
AM		 3489 /* Put out high byte first: can't use md_number_to_chars! */
3490 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3491 *p = i.tm.base_opcode & 0xff;
3492 }
3e73aa7c 3493
29b0f896
AM		 3494 /* Now the modrm byte and sib byte (if present). */
3495 if (i.tm.opcode_modifier & Modrm)
3496 {
3497 p = frag_more (1);
3498 md_number_to_chars (p,
3499 (valueT) (i.rm.regmem << 0
3500 | i.rm.reg << 3
3501 | i.rm.mode << 6),
3502 1);
3503 /* If i.rm.regmem == ESP (4)
3504 && i.rm.mode != (Register mode)
3505 && not 16 bit
3506 ==> need second modrm byte. */
3507 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3508 && i.rm.mode != 3
3509 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3510 {
3511 p = frag_more (1);
3512 md_number_to_chars (p,
3513 (valueT) (i.sib.base << 0
3514 | i.sib.index << 3
3515 | i.sib.scale << 6),
3516 1);
3517 }
3518 }
3e73aa7c 3519
29b0f896 3520 if (i.disp_operands)
2bbd9c25 3521 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3522
29b0f896 3523 if (i.imm_operands)
2bbd9c25 3524 output_imm (insn_start_frag, insn_start_off);
29b0f896 3525 }
252b5132 3526
29b0f896
AM		 3527#ifdef DEBUG386
3528 if (flag_debug)
3529 {
3530 pi (line, &i);
3531 }
3532#endif /* DEBUG386 */
3533}
252b5132 3534
29b0f896 3535static void
2bbd9c25
JJ		 3536output_disp (insn_start_frag, insn_start_off)
3537 fragS *insn_start_frag;
3538 offsetT insn_start_off;
29b0f896
AM		 3539{
3540 char *p;
3541 unsigned int n;
252b5132 3542
29b0f896
AM		 3543 for (n = 0; n < i.operands; n++)
3544 {
3545 if (i.types[n] & Disp)
3546 {
3547 if (i.op[n].disps->X_op == O_constant)
3548 {
3549 int size;
3550 offsetT val;
252b5132 3551
29b0f896
AM		 3552 size = 4;
3553 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3554 {
3555 size = 2;
3556 if (i.types[n] & Disp8)
3557 size = 1;
3558 if (i.types[n] & Disp64)
3559 size = 8;
3560 }
3561 val = offset_in_range (i.op[n].disps->X_add_number,
3562 size);
3563 p = frag_more (size);
3564 md_number_to_chars (p, val, size);
3565 }
3566 else
3567 {
f86103b7 3568 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3569 int size = 4;
3570 int sign = 0;
3571 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3572
3573 /* The PC relative address is computed relative
3574 to the instruction boundary, so in case immediate
3575 fields follows, we need to adjust the value. */
3576 if (pcrel && i.imm_operands)
3577 {
3578 int imm_size = 4;
3579 unsigned int n1;
252b5132 3580
29b0f896
AM		 3581 for (n1 = 0; n1 < i.operands; n1++)
3582 if (i.types[n1] & Imm)
252b5132 3583 {
29b0f896 3584 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 3585 {
29b0f896
AM		 3586 imm_size = 2;
3587 if (i.types[n1] & (Imm8 | Imm8S))
3588 imm_size = 1;
3589 if (i.types[n1] & Imm64)
3590 imm_size = 8;
252b5132 3591 }
29b0f896 3592 break;
252b5132 3593 }
29b0f896
AM		 3594 /* We should find the immediate. */
3595 if (n1 == i.operands)
3596 abort ();
3597 i.op[n].disps->X_add_number -= imm_size;
3598 }
520dc8e8 3599
29b0f896
AM		 3600 if (i.types[n] & Disp32S)
3601 sign = 1;
3e73aa7c 3602
29b0f896
AM		 3603 if (i.types[n] & (Disp16 | Disp64))
3604 {
3605 size = 2;
3606 if (i.types[n] & Disp64)
3607 size = 8;
3608 }
520dc8e8 3609
29b0f896 3610 p = frag_more (size);
2bbd9c25 3611 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 3612 if (GOT_symbol
2bbd9c25 3613 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113
JB		 3614 && (((reloc_type == BFD_RELOC_32
3615 || reloc_type == BFD_RELOC_X86_64_32S)
3616 && (i.op[n].disps->X_op == O_symbol
3617 || (i.op[n].disps->X_op == O_add
3618 && ((symbol_get_value_expression
3619 (i.op[n].disps->X_op_symbol)->X_op)
3620 == O_subtract))))
3621 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 3622 {
3623 offsetT add;
3624
3625 if (insn_start_frag == frag_now)
3626 add = (p - frag_now->fr_literal) - insn_start_off;
3627 else
3628 {
3629 fragS *fr;
3630
3631 add = insn_start_frag->fr_fix - insn_start_off;
3632 for (fr = insn_start_frag->fr_next;
3633 fr && fr != frag_now; fr = fr->fr_next)
3634 add += fr->fr_fix;
3635 add += p - frag_now->fr_literal;
3636 }
3637
4fa24527 3638 if (!object_64bit)
d6ab8113
JB		 3639 reloc_type = BFD_RELOC_386_GOTPC;
3640 else
3641 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25
JJ		 3642 i.op[n].disps->X_add_number += add;
3643 }
062cd5e7 3644 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 3645 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 3646 }
3647 }
3648 }
3649}
252b5132 3650
29b0f896 3651static void
2bbd9c25
JJ		 3652output_imm (insn_start_frag, insn_start_off)
3653 fragS *insn_start_frag;
3654 offsetT insn_start_off;
29b0f896
AM		 3655{
3656 char *p;
3657 unsigned int n;
252b5132 3658
29b0f896
AM		 3659 for (n = 0; n < i.operands; n++)
3660 {
3661 if (i.types[n] & Imm)
3662 {
3663 if (i.op[n].imms->X_op == O_constant)
3664 {
3665 int size;
3666 offsetT val;
b4cac588 3667
29b0f896
AM		 3668 size = 4;
3669 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3670 {
3671 size = 2;
3672 if (i.types[n] & (Imm8 | Imm8S))
3673 size = 1;
3674 else if (i.types[n] & Imm64)
3675 size = 8;
3676 }
3677 val = offset_in_range (i.op[n].imms->X_add_number,
3678 size);
3679 p = frag_more (size);
3680 md_number_to_chars (p, val, size);
3681 }
3682 else
3683 {
3684 /* Not absolute_section.
3685 Need a 32-bit fixup (don't support 8bit
3686 non-absolute imms). Try to support other
3687 sizes ... */
f86103b7 3688 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3689 int size = 4;
3690 int sign = 0;
3691
3692 if ((i.types[n] & (Imm32S))
a7d61044
JB		 3693 && (i.suffix == QWORD_MNEM_SUFFIX
3694 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 3695 sign = 1;
3696 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3697 {
3698 size = 2;
3699 if (i.types[n] & (Imm8 | Imm8S))
3700 size = 1;
3701 if (i.types[n] & Imm64)
3702 size = 8;
3703 }
520dc8e8 3704
29b0f896
AM		 3705 p = frag_more (size);
3706 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 3707
2bbd9c25
JJ		 3708 /* This is tough to explain. We end up with this one if we
3709 * have operands that look like
3710 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3711 * obtain the absolute address of the GOT, and it is strongly
3712 * preferable from a performance point of view to avoid using
3713 * a runtime relocation for this. The actual sequence of
3714 * instructions often look something like:
3715 *
3716 * call .L66
3717 * .L66:
3718 * popl %ebx
3719 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3720 *
3721 * The call and pop essentially return the absolute address
3722 * of the label .L66 and store it in %ebx. The linker itself
3723 * will ultimately change the first operand of the addl so
3724 * that %ebx points to the GOT, but to keep things simple, the
3725 * .o file must have this operand set so that it generates not
3726 * the absolute address of .L66, but the absolute address of
3727 * itself. This allows the linker itself simply treat a GOTPC
3728 * relocation as asking for a pcrel offset to the GOT to be
3729 * added in, and the addend of the relocation is stored in the
3730 * operand field for the instruction itself.
3731 *
3732 * Our job here is to fix the operand so that it would add
3733 * the correct offset so that %ebx would point to itself. The
3734 * thing that is tricky is that .-.L66 will point to the
3735 * beginning of the instruction, so we need to further modify
3736 * the operand so that it will point to itself. There are
3737 * other cases where you have something like:
3738 *
3739 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3740 *
3741 * and here no correction would be required. Internally in
3742 * the assembler we treat operands of this form as not being
3743 * pcrel since the '.' is explicitly mentioned, and I wonder
3744 * whether it would simplify matters to do it this way. Who
3745 * knows. In earlier versions of the PIC patches, the
3746 * pcrel_adjust field was used to store the correction, but
3747 * since the expression is not pcrel, I felt it would be
3748 * confusing to do it this way. */
3749
d6ab8113
JB		 3750 if ((reloc_type == BFD_RELOC_32
3751 || reloc_type == BFD_RELOC_X86_64_32S)
29b0f896
AM		 3752 && GOT_symbol
3753 && GOT_symbol == i.op[n].imms->X_add_symbol
3754 && (i.op[n].imms->X_op == O_symbol
3755 || (i.op[n].imms->X_op == O_add
3756 && ((symbol_get_value_expression
3757 (i.op[n].imms->X_op_symbol)->X_op)
3758 == O_subtract))))
3759 {
2bbd9c25
JJ		 3760 offsetT add;
3761
3762 if (insn_start_frag == frag_now)
3763 add = (p - frag_now->fr_literal) - insn_start_off;
3764 else
3765 {
3766 fragS *fr;
3767
3768 add = insn_start_frag->fr_fix - insn_start_off;
3769 for (fr = insn_start_frag->fr_next;
3770 fr && fr != frag_now; fr = fr->fr_next)
3771 add += fr->fr_fix;
3772 add += p - frag_now->fr_literal;
3773 }
3774
4fa24527 3775 if (!object_64bit)
d6ab8113
JB		 3776 reloc_type = BFD_RELOC_386_GOTPC;
3777 else
3778 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 3779 i.op[n].imms->X_add_number += add;
29b0f896 3780 }
29b0f896
AM		 3781 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3782 i.op[n].imms, 0, reloc_type);
3783 }
3784 }
3785 }
252b5132
RH		 3786}
3787\f
d182319b
JB		 3788/* x86_cons_fix_new is called via the expression parsing code when a
3789 reloc is needed. We use this hook to get the correct .got reloc. */
3790static enum bfd_reloc_code_real got_reloc = NO_RELOC;
3791static int cons_sign = -1;
3792
3793void
3794x86_cons_fix_new (fragS *frag,
3795 unsigned int off,
3796 unsigned int len,
3797 expressionS *exp)
3798{
3799 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
3800
3801 got_reloc = NO_RELOC;
3802
3803#ifdef TE_PE
3804 if (exp->X_op == O_secrel)
3805 {
3806 exp->X_op = O_symbol;
3807 r = BFD_RELOC_32_SECREL;
3808 }
3809#endif
3810
3811 fix_new_exp (frag, off, len, exp, 0, r);
3812}
3813
718ddfc0
JB		 3814#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
3815# define lex_got(reloc, adjust, types) NULL
3816#else
f3c180ae
AM		 3817/* Parse operands of the form
3818 <symbol>@GOTOFF+<nnn>
3819 and similar .plt or .got references.
3820
3821 If we find one, set up the correct relocation in RELOC and copy the
3822 input string, minus the `@GOTOFF' into a malloc'd buffer for
3823 parsing by the calling routine. Return this buffer, and if ADJUST
3824 is non-null set it to the length of the string we removed from the
3825 input line. Otherwise return NULL. */
3826static char *
3956db08
JB		 3827lex_got (enum bfd_reloc_code_real *reloc,
3828 int *adjust,
3829 unsigned int *types)
f3c180ae 3830{
f3c180ae
AM		 3831 static const struct {
3832 const char *str;
4fa24527 3833 const enum bfd_reloc_code_real rel[2];
3956db08 3834 const unsigned int types64;
f3c180ae 3835 } gotrel[] = {
4fa24527
JB		 3836 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
3837 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
3838 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
3839 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
3840 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 },
3841 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
3842 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
3843 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
3844 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 },
3845 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
3846 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 },
3847 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 },
3848 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32 }
f3c180ae
AM		 3849 };
3850 char *cp;
3851 unsigned int j;
3852
718ddfc0
JB		 3853 if (!IS_ELF)
3854 return NULL;
3855
f3c180ae
AM		 3856 for (cp = input_line_pointer; *cp != '@'; cp++)
3857 if (is_end_of_line[(unsigned char) *cp])
3858 return NULL;
3859
3860 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3861 {
3862 int len;
3863
3864 len = strlen (gotrel[j].str);
28f81592 3865 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 3866 {
4fa24527 3867 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 3868 {
28f81592
AM		 3869 int first, second;
3870 char *tmpbuf, *past_reloc;
f3c180ae 3871
4fa24527 3872 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 3873 if (adjust)
3874 *adjust = len;
f3c180ae 3875
3956db08
JB		 3876 if (types)
3877 {
3878 if (flag_code != CODE_64BIT)
3879 *types = Imm32|Disp32;
3880 else
3881 *types = gotrel[j].types64;
3882 }
3883
f3c180ae
AM		 3884 if (GOT_symbol == NULL)
3885 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3886
3887 /* Replace the relocation token with ' ', so that
3888 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 3889
3890 /* The length of the first part of our input line. */
f3c180ae 3891 first = cp - input_line_pointer;
28f81592
AM		 3892
3893 /* The second part goes from after the reloc token until
3894 (and including) an end_of_line char. Don't use strlen
3895 here as the end_of_line char may not be a NUL. */
3896 past_reloc = cp + 1 + len;
3897 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3898 ;
3899 second = cp - past_reloc;
3900
3901 /* Allocate and copy string. The trailing NUL shouldn't
3902 be necessary, but be safe. */
3903 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 3904 memcpy (tmpbuf, input_line_pointer, first);
3905 tmpbuf[first] = ' ';
28f81592
AM		 3906 memcpy (tmpbuf + first + 1, past_reloc, second);
3907 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 3908 return tmpbuf;
3909 }
3910
4fa24527
JB		 3911 as_bad (_("@%s reloc is not supported with %d-bit output format"),
3912 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 3913 return NULL;
3914 }
3915 }
3916
3917 /* Might be a symbol version string. Don't as_bad here. */
3918 return NULL;
3919}
3920
f3c180ae
AM		 3921void
3922x86_cons (exp, size)
3923 expressionS *exp;
3924 int size;
3925{
4fa24527 3926 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 3927 {
3928 /* Handle @GOTOFF and the like in an expression. */
3929 char *save;
3930 char *gotfree_input_line;
3931 int adjust;
3932
3933 save = input_line_pointer;
3956db08 3934 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 3935 if (gotfree_input_line)
3936 input_line_pointer = gotfree_input_line;
3937
3938 expression (exp);
3939
3940 if (gotfree_input_line)
3941 {
3942 /* expression () has merrily parsed up to the end of line,
3943 or a comma - in the wrong buffer. Transfer how far
3944 input_line_pointer has moved to the right buffer. */
3945 input_line_pointer = (save
3946 + (input_line_pointer - gotfree_input_line)
3947 + adjust);
3948 free (gotfree_input_line);
3949 }
3950 }
3951 else
3952 expression (exp);
3953}
3954#endif
3955
d182319b 3956static void signed_cons (int size)
6482c264 3957{
d182319b
JB		 3958 if (flag_code == CODE_64BIT)
3959 cons_sign = 1;
3960 cons (size);
3961 cons_sign = -1;
6482c264
NC		 3962}
3963
d182319b 3964#ifdef TE_PE
6482c264
NC		 3965static void
3966pe_directive_secrel (dummy)
3967 int dummy ATTRIBUTE_UNUSED;
3968{
3969 expressionS exp;
3970
3971 do
3972 {
3973 expression (&exp);
3974 if (exp.X_op == O_symbol)
3975 exp.X_op = O_secrel;
3976
3977 emit_expr (&exp, 4);
3978 }
3979 while (*input_line_pointer++ == ',');
3980
3981 input_line_pointer--;
3982 demand_empty_rest_of_line ();
3983}
6482c264
NC		 3984#endif
3985
252b5132
RH		 3986static int i386_immediate PARAMS ((char *));
3987
3988static int
3989i386_immediate (imm_start)
3990 char *imm_start;
3991{
3992 char *save_input_line_pointer;
f3c180ae 3993 char *gotfree_input_line;
252b5132 3994 segT exp_seg = 0;
47926f60 3995 expressionS *exp;
3956db08 3996 unsigned int types = ~0U;
252b5132
RH		 3997
3998 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3999 {
d0b47220 4000 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 4001 return 0;
4002 }
4003
4004 exp = &im_expressions[i.imm_operands++];
520dc8e8 4005 i.op[this_operand].imms = exp;
252b5132
RH		 4006
4007 if (is_space_char (*imm_start))
4008 ++imm_start;
4009
4010 save_input_line_pointer = input_line_pointer;
4011 input_line_pointer = imm_start;
4012
3956db08 4013 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4014 if (gotfree_input_line)
4015 input_line_pointer = gotfree_input_line;
252b5132
RH		 4016
4017 exp_seg = expression (exp);
4018
83183c0c 4019 SKIP_WHITESPACE ();
252b5132 4020 if (*input_line_pointer)
f3c180ae 4021 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 4022
4023 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4024 if (gotfree_input_line)
4025 free (gotfree_input_line);
252b5132 4026
2daf4fd8 4027 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 4028 {
47926f60 4029 /* Missing or bad expr becomes absolute 0. */
d0b47220 4030 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 4031 imm_start);
252b5132
RH		 4032 exp->X_op = O_constant;
4033 exp->X_add_number = 0;
4034 exp->X_add_symbol = (symbolS *) 0;
4035 exp->X_op_symbol = (symbolS *) 0;
252b5132 4036 }
3e73aa7c 4037 else if (exp->X_op == O_constant)
252b5132 4038 {
47926f60 4039 /* Size it properly later. */
3e73aa7c
JH		 4040 i.types[this_operand] |= Imm64;
4041 /* If BFD64, sign extend val. */
4042 if (!use_rela_relocations)
4043 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4044 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4045 }
4c63da97 4046#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4047 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4048 && exp_seg != absolute_section
47926f60 4049 && exp_seg != text_section
24eab124
AM		 4050 && exp_seg != data_section
4051 && exp_seg != bss_section
4052 && exp_seg != undefined_section
f86103b7 4053 && !bfd_is_com_section (exp_seg))
252b5132 4054 {
d0b47220 4055 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4056 return 0;
4057 }
4058#endif
4059 else
4060 {
4061 /* This is an address. The size of the address will be
24eab124 4062 determined later, depending on destination register,
3e73aa7c
JH		 4063 suffix, or the default for the section. */
4064 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4065 i.types[this_operand] &= types;
252b5132
RH		 4066 }
4067
4068 return 1;
4069}
4070
551c1ca1 4071static char *i386_scale PARAMS ((char *));
252b5132 4072
551c1ca1 4073static char *
252b5132
RH		 4074i386_scale (scale)
4075 char *scale;
4076{
551c1ca1
AM		 4077 offsetT val;
4078 char *save = input_line_pointer;
252b5132 4079
551c1ca1
AM		 4080 input_line_pointer = scale;
4081 val = get_absolute_expression ();
4082
4083 switch (val)
252b5132 4084 {
551c1ca1 4085 case 1:
252b5132
RH		 4086 i.log2_scale_factor = 0;
4087 break;
551c1ca1 4088 case 2:
252b5132
RH		 4089 i.log2_scale_factor = 1;
4090 break;
551c1ca1 4091 case 4:
252b5132
RH		 4092 i.log2_scale_factor = 2;
4093 break;
551c1ca1 4094 case 8:
252b5132
RH		 4095 i.log2_scale_factor = 3;
4096 break;
4097 default:
a724f0f4
JB		 4098 {
4099 char sep = *input_line_pointer;
4100
4101 *input_line_pointer = '\0';
4102 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4103 scale);
4104 *input_line_pointer = sep;
4105 input_line_pointer = save;
4106 return NULL;
4107 }
252b5132 4108 }
29b0f896 4109 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4110 {
4111 as_warn (_("scale factor of %d without an index register"),
24eab124 4112 1 << i.log2_scale_factor);
252b5132
RH		 4113#if SCALE1_WHEN_NO_INDEX
4114 i.log2_scale_factor = 0;
4115#endif
4116 }
551c1ca1
AM		 4117 scale = input_line_pointer;
4118 input_line_pointer = save;
4119 return scale;
252b5132
RH		 4120}
4121
4122static int i386_displacement PARAMS ((char *, char *));
4123
4124static int
4125i386_displacement (disp_start, disp_end)
4126 char *disp_start;
4127 char *disp_end;
4128{
29b0f896 4129 expressionS *exp;
252b5132
RH		 4130 segT exp_seg = 0;
4131 char *save_input_line_pointer;
f3c180ae 4132 char *gotfree_input_line;
e05278af 4133 int bigdisp, override;
3956db08 4134 unsigned int types = Disp;
252b5132 4135
e05278af
JB		 4136 if ((i.types[this_operand] & JumpAbsolute)
4137 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4138 {
4139 bigdisp = Disp32;
4140 override = (i.prefix[ADDR_PREFIX] != 0);
4141 }
4142 else
4143 {
4144 /* For PC-relative branches, the width of the displacement
4145 is dependent upon data size, not address size. */
4146 bigdisp = 0;
4147 override = (i.prefix[DATA_PREFIX] != 0);
4148 }
3e73aa7c 4149 if (flag_code == CODE_64BIT)
7ecd2f8b 4150 {
e05278af
JB		 4151 if (!bigdisp)
4152 bigdisp = (override || i.suffix == WORD_MNEM_SUFFIX)
4153 ? Disp16
4154 : Disp32S | Disp32;
4155 else if (!override)
3956db08 4156 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b 4157 }
e05278af
JB		 4158 else
4159 {
4160 if (!bigdisp)
4161 {
4162 if (!override)
4163 override = (i.suffix == (flag_code != CODE_16BIT
4164 ? WORD_MNEM_SUFFIX
4165 : LONG_MNEM_SUFFIX));
4166 bigdisp = Disp32;
4167 }
4168 if ((flag_code == CODE_16BIT) ^ override)
4169 bigdisp = Disp16;
4170 }
252b5132
RH		 4171 i.types[this_operand] |= bigdisp;
4172
4173 exp = &disp_expressions[i.disp_operands];
520dc8e8 4174 i.op[this_operand].disps = exp;
252b5132
RH		 4175 i.disp_operands++;
4176 save_input_line_pointer = input_line_pointer;
4177 input_line_pointer = disp_start;
4178 END_STRING_AND_SAVE (disp_end);
4179
4180#ifndef GCC_ASM_O_HACK
4181#define GCC_ASM_O_HACK 0
4182#endif
4183#if GCC_ASM_O_HACK
4184 END_STRING_AND_SAVE (disp_end + 1);
4185 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4186 && displacement_string_end[-1] == '+')
252b5132
RH		 4187 {
4188 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4189 constraint within gcc asm statements.
4190 For instance:
4191
4192 #define _set_tssldt_desc(n,addr,limit,type) \
4193 __asm__ __volatile__ ( \
4194 "movw %w2,%0\n\t" \
4195 "movw %w1,2+%0\n\t" \
4196 "rorl $16,%1\n\t" \
4197 "movb %b1,4+%0\n\t" \
4198 "movb %4,5+%0\n\t" \
4199 "movb $0,6+%0\n\t" \
4200 "movb %h1,7+%0\n\t" \
4201 "rorl $16,%1" \
4202 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4203
4204 This works great except that the output assembler ends
4205 up looking a bit weird if it turns out that there is
4206 no offset. You end up producing code that looks like:
4207
4208 #APP
4209 movw $235,(%eax)
4210 movw %dx,2+(%eax)
4211 rorl $16,%edx
4212 movb %dl,4+(%eax)
4213 movb $137,5+(%eax)
4214 movb $0,6+(%eax)
4215 movb %dh,7+(%eax)
4216 rorl $16,%edx
4217 #NO_APP
4218
47926f60 4219 So here we provide the missing zero. */
24eab124
AM		 4220
4221 *displacement_string_end = '0';
252b5132
RH		 4222 }
4223#endif
3956db08 4224 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4225 if (gotfree_input_line)
4226 input_line_pointer = gotfree_input_line;
252b5132 4227
24eab124 4228 exp_seg = expression (exp);
252b5132 4229
636c26b0
AM		 4230 SKIP_WHITESPACE ();
4231 if (*input_line_pointer)
4232 as_bad (_("junk `%s' after expression"), input_line_pointer);
4233#if GCC_ASM_O_HACK
4234 RESTORE_END_STRING (disp_end + 1);
4235#endif
4236 RESTORE_END_STRING (disp_end);
4237 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4238 if (gotfree_input_line)
4239 free (gotfree_input_line);
636c26b0 4240
24eab124
AM		 4241 /* We do this to make sure that the section symbol is in
4242 the symbol table. We will ultimately change the relocation
47926f60 4243 to be relative to the beginning of the section. */
1ae12ab7 4244 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4245 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4246 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4247 {
636c26b0
AM		 4248 if (exp->X_op != O_symbol)
4249 {
4250 as_bad (_("bad expression used with @%s"),
4251 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4252 ? "GOTPCREL"
4253 : "GOTOFF"));
4254 return 0;
4255 }
4256
e5cb08ac 4257 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4258 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4259 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4260 exp->X_op = O_subtract;
4261 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4262 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4263 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4264 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4265 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4266 else
29b0f896 4267 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4268 }
252b5132 4269
2daf4fd8
AM		 4270 if (exp->X_op == O_absent || exp->X_op == O_big)
4271 {
47926f60 4272 /* Missing or bad expr becomes absolute 0. */
d0b47220 4273 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4274 disp_start);
4275 exp->X_op = O_constant;
4276 exp->X_add_number = 0;
4277 exp->X_add_symbol = (symbolS *) 0;
4278 exp->X_op_symbol = (symbolS *) 0;
4279 }
4280
4c63da97 4281#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4282 if (exp->X_op != O_constant
45288df1 4283 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4284 && exp_seg != absolute_section
45288df1
AM		 4285 && exp_seg != text_section
4286 && exp_seg != data_section
4287 && exp_seg != bss_section
31312f95 4288 && exp_seg != undefined_section
f86103b7 4289 && !bfd_is_com_section (exp_seg))
24eab124 4290 {
d0b47220 4291 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4292 return 0;
4293 }
252b5132 4294#endif
3956db08
JB		 4295
4296 if (!(i.types[this_operand] & ~Disp))
4297 i.types[this_operand] &= types;
4298
252b5132
RH		 4299 return 1;
4300}
4301
e5cb08ac 4302static int i386_index_check PARAMS ((const char *));
252b5132 4303
eecb386c 4304/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4305 Return 1 on success, 0 on a failure. */
4306
252b5132 4307static int
eecb386c
AM		 4308i386_index_check (operand_string)
4309 const char *operand_string;
252b5132 4310{
3e73aa7c 4311 int ok;
24eab124 4312#if INFER_ADDR_PREFIX
eecb386c
AM		 4313 int fudged = 0;
4314
24eab124
AM		 4315 tryprefix:
4316#endif
3e73aa7c 4317 ok = 1;
30123838
JB		 4318 if ((current_templates->start->cpu_flags & CpuSVME)
4319 && current_templates->end[-1].operand_types[0] == AnyMem)
4320 {
4321 /* Memory operands of SVME insns are special in that they only allow
4322 rAX as their memory address and ignore any segment override. */
4323 unsigned RegXX;
4324
4325 /* SKINIT is even more restrictive: it always requires EAX. */
4326 if (strcmp (current_templates->start->name, "skinit") == 0)
4327 RegXX = Reg32;
4328 else if (flag_code == CODE_64BIT)
4329 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4330 else
4331 RegXX = (flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4332 ? Reg16
4333 : Reg32;
4334 if (!i.base_reg
4335 || !(i.base_reg->reg_type & Acc)
4336 || !(i.base_reg->reg_type & RegXX)
4337 || i.index_reg
4338 || (i.types[0] & Disp))
4339 ok = 0;
4340 }
4341 else if (flag_code == CODE_64BIT)
20f0a1fc
NC		 4342 {
4343 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4344
4345 if ((i.base_reg
4346 && ((i.base_reg->reg_type & RegXX) == 0)
4347 && (i.base_reg->reg_type != BaseIndex
4348 || i.index_reg))
4349 || (i.index_reg
4350 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4351 != (RegXX | BaseIndex))))
4352 ok = 0;
3e73aa7c
JH		 4353 }
4354 else
4355 {
4356 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4357 {
4358 /* 16bit checks. */
4359 if ((i.base_reg
29b0f896
AM		 4360 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4361 != (Reg16 | BaseIndex)))
3e73aa7c 4362 || (i.index_reg
29b0f896
AM		 4363 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4364 != (Reg16 | BaseIndex))
4365 || !(i.base_reg
4366 && i.base_reg->reg_num < 6
4367 && i.index_reg->reg_num >= 6
4368 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4369 ok = 0;
4370 }
4371 else
e5cb08ac 4372 {
3e73aa7c
JH		 4373 /* 32bit checks. */
4374 if ((i.base_reg
4375 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4376 || (i.index_reg
29b0f896
AM		 4377 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4378 != (Reg32 | BaseIndex))))
e5cb08ac 4379 ok = 0;
3e73aa7c
JH		 4380 }
4381 }
4382 if (!ok)
24eab124
AM		 4383 {
4384#if INFER_ADDR_PREFIX
20f0a1fc 4385 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4386 {
4387 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4388 i.prefixes += 1;
b23bac36
AM		 4389 /* Change the size of any displacement too. At most one of
4390 Disp16 or Disp32 is set.
4391 FIXME. There doesn't seem to be any real need for separate
4392 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4393 Removing them would probably clean up the code quite a lot. */
20f0a1fc 4394 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
29b0f896 4395 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4396 fudged = 1;
24eab124
AM		 4397 goto tryprefix;
4398 }
eecb386c
AM		 4399 if (fudged)
4400 as_bad (_("`%s' is not a valid base/index expression"),
4401 operand_string);
4402 else
c388dee8 4403#endif
eecb386c
AM		 4404 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4405 operand_string,
3e73aa7c 4406 flag_code_names[flag_code]);
24eab124 4407 }
20f0a1fc 4408 return ok;
24eab124 4409}
252b5132 4410
252b5132 4411/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4412 on error. */
252b5132 4413
252b5132
RH		 4414static int
4415i386_operand (operand_string)
4416 char *operand_string;
4417{
af6bdddf
AM		 4418 const reg_entry *r;
4419 char *end_op;
24eab124 4420 char *op_string = operand_string;
252b5132 4421
24eab124 4422 if (is_space_char (*op_string))
252b5132
RH		 4423 ++op_string;
4424
24eab124 4425 /* We check for an absolute prefix (differentiating,
47926f60 4426 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4427 if (*op_string == ABSOLUTE_PREFIX)
4428 {
4429 ++op_string;
4430 if (is_space_char (*op_string))
4431 ++op_string;
4432 i.types[this_operand] |= JumpAbsolute;
4433 }
252b5132 4434
47926f60 4435 /* Check if operand is a register. */
4d1bb795 4436 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 4437 {
24eab124
AM		 4438 /* Check for a segment override by searching for ':' after a
4439 segment register. */
4440 op_string = end_op;
4441 if (is_space_char (*op_string))
4442 ++op_string;
4443 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4444 {
4445 switch (r->reg_num)
4446 {
4447 case 0:
4448 i.seg[i.mem_operands] = &es;
4449 break;
4450 case 1:
4451 i.seg[i.mem_operands] = &cs;
4452 break;
4453 case 2:
4454 i.seg[i.mem_operands] = &ss;
4455 break;
4456 case 3:
4457 i.seg[i.mem_operands] = &ds;
4458 break;
4459 case 4:
4460 i.seg[i.mem_operands] = &fs;
4461 break;
4462 case 5:
4463 i.seg[i.mem_operands] = &gs;
4464 break;
4465 }
252b5132 4466
24eab124 4467 /* Skip the ':' and whitespace. */
252b5132
RH		 4468 ++op_string;
4469 if (is_space_char (*op_string))
24eab124 4470 ++op_string;
252b5132 4471
24eab124
AM		 4472 if (!is_digit_char (*op_string)
4473 && !is_identifier_char (*op_string)
4474 && *op_string != '('
4475 && *op_string != ABSOLUTE_PREFIX)
4476 {
4477 as_bad (_("bad memory operand `%s'"), op_string);
4478 return 0;
4479 }
47926f60 4480 /* Handle case of %es:*foo. */
24eab124
AM		 4481 if (*op_string == ABSOLUTE_PREFIX)
4482 {
4483 ++op_string;
4484 if (is_space_char (*op_string))
4485 ++op_string;
4486 i.types[this_operand] |= JumpAbsolute;
4487 }
4488 goto do_memory_reference;
4489 }
4490 if (*op_string)
4491 {
d0b47220 4492 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4493 return 0;
4494 }
4495 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 4496 i.op[this_operand].regs = r;
24eab124
AM		 4497 i.reg_operands++;
4498 }
af6bdddf
AM		 4499 else if (*op_string == REGISTER_PREFIX)
4500 {
4501 as_bad (_("bad register name `%s'"), op_string);
4502 return 0;
4503 }
24eab124 4504 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 4505 {
24eab124
AM		 4506 ++op_string;
4507 if (i.types[this_operand] & JumpAbsolute)
4508 {
d0b47220 4509 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4510 return 0;
4511 }
4512 if (!i386_immediate (op_string))
4513 return 0;
4514 }
4515 else if (is_digit_char (*op_string)
4516 || is_identifier_char (*op_string)
e5cb08ac 4517 || *op_string == '(')
24eab124 4518 {
47926f60 4519 /* This is a memory reference of some sort. */
af6bdddf 4520 char *base_string;
252b5132 4521
47926f60 4522 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 4523 char *displacement_string_start;
4524 char *displacement_string_end;
252b5132 4525
24eab124 4526 do_memory_reference:
24eab124
AM		 4527 if ((i.mem_operands == 1
4528 && (current_templates->start->opcode_modifier & IsString) == 0)
4529 || i.mem_operands == 2)
4530 {
4531 as_bad (_("too many memory references for `%s'"),
4532 current_templates->start->name);
4533 return 0;
4534 }
252b5132 4535
24eab124
AM		 4536 /* Check for base index form. We detect the base index form by
4537 looking for an ')' at the end of the operand, searching
4538 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4539 after the '('. */
af6bdddf 4540 base_string = op_string + strlen (op_string);
c3332e24 4541
af6bdddf
AM		 4542 --base_string;
4543 if (is_space_char (*base_string))
4544 --base_string;
252b5132 4545
47926f60 4546 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 4547 displacement_string_start = op_string;
4548 displacement_string_end = base_string + 1;
252b5132 4549
24eab124
AM		 4550 if (*base_string == ')')
4551 {
af6bdddf 4552 char *temp_string;
24eab124
AM		 4553 unsigned int parens_balanced = 1;
4554 /* We've already checked that the number of left & right ()'s are
47926f60 4555 equal, so this loop will not be infinite. */
24eab124
AM		 4556 do
4557 {
4558 base_string--;
4559 if (*base_string == ')')
4560 parens_balanced++;
4561 if (*base_string == '(')
4562 parens_balanced--;
4563 }
4564 while (parens_balanced);
c3332e24 4565
af6bdddf 4566 temp_string = base_string;
c3332e24 4567
24eab124 4568 /* Skip past '(' and whitespace. */
252b5132
RH		 4569 ++base_string;
4570 if (is_space_char (*base_string))
24eab124 4571 ++base_string;
252b5132 4572
af6bdddf 4573 if (*base_string == ','
4d1bb795 4574 || ((i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 4575 {
af6bdddf 4576 displacement_string_end = temp_string;
252b5132 4577
af6bdddf 4578 i.types[this_operand] |= BaseIndex;
252b5132 4579
af6bdddf 4580 if (i.base_reg)
24eab124 4581 {
24eab124
AM		 4582 base_string = end_op;
4583 if (is_space_char (*base_string))
4584 ++base_string;
af6bdddf
AM		 4585 }
4586
4587 /* There may be an index reg or scale factor here. */
4588 if (*base_string == ',')
4589 {
4590 ++base_string;
4591 if (is_space_char (*base_string))
4592 ++base_string;
4593
4d1bb795 4594 if ((i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 4595 {
af6bdddf 4596 base_string = end_op;
24eab124
AM		 4597 if (is_space_char (*base_string))
4598 ++base_string;
af6bdddf
AM		 4599 if (*base_string == ',')
4600 {
4601 ++base_string;
4602 if (is_space_char (*base_string))
4603 ++base_string;
4604 }
e5cb08ac 4605 else if (*base_string != ')')
af6bdddf
AM		 4606 {
4607 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4608 operand_string);
4609 return 0;
4610 }
24eab124 4611 }
af6bdddf 4612 else if (*base_string == REGISTER_PREFIX)
24eab124 4613 {
af6bdddf 4614 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 4615 return 0;
4616 }
252b5132 4617
47926f60 4618 /* Check for scale factor. */
551c1ca1 4619 if (*base_string != ')')
af6bdddf 4620 {
551c1ca1
AM		 4621 char *end_scale = i386_scale (base_string);
4622
4623 if (!end_scale)
af6bdddf 4624 return 0;
24eab124 4625
551c1ca1 4626 base_string = end_scale;
af6bdddf
AM		 4627 if (is_space_char (*base_string))
4628 ++base_string;
4629 if (*base_string != ')')
4630 {
4631 as_bad (_("expecting `)' after scale factor in `%s'"),
4632 operand_string);
4633 return 0;
4634 }
4635 }
4636 else if (!i.index_reg)
24eab124 4637 {
af6bdddf
AM		 4638 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4639 *base_string);
24eab124
AM		 4640 return 0;
4641 }
4642 }
af6bdddf 4643 else if (*base_string != ')')
24eab124 4644 {
af6bdddf
AM		 4645 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4646 operand_string);
24eab124
AM		 4647 return 0;
4648 }
c3332e24 4649 }
af6bdddf 4650 else if (*base_string == REGISTER_PREFIX)
c3332e24 4651 {
af6bdddf 4652 as_bad (_("bad register name `%s'"), base_string);
24eab124 4653 return 0;
c3332e24 4654 }
24eab124
AM		 4655 }
4656
4657 /* If there's an expression beginning the operand, parse it,
4658 assuming displacement_string_start and
4659 displacement_string_end are meaningful. */
4660 if (displacement_string_start != displacement_string_end)
4661 {
4662 if (!i386_displacement (displacement_string_start,
4663 displacement_string_end))
4664 return 0;
4665 }
4666
4667 /* Special case for (%dx) while doing input/output op. */
4668 if (i.base_reg
4669 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4670 && i.index_reg == 0
4671 && i.log2_scale_factor == 0
4672 && i.seg[i.mem_operands] == 0
4673 && (i.types[this_operand] & Disp) == 0)
4674 {
4675 i.types[this_operand] = InOutPortReg;
4676 return 1;
4677 }
4678
eecb386c
AM		 4679 if (i386_index_check (operand_string) == 0)
4680 return 0;
24eab124
AM		 4681 i.mem_operands++;
4682 }
4683 else
ce8a8b2f
AM		 4684 {
4685 /* It's not a memory operand; argh! */
24eab124
AM		 4686 as_bad (_("invalid char %s beginning operand %d `%s'"),
4687 output_invalid (*op_string),
4688 this_operand + 1,
4689 op_string);
4690 return 0;
4691 }
47926f60 4692 return 1; /* Normal return. */
252b5132
RH		 4693}
4694\f
ee7fcc42
AM		 4695/* md_estimate_size_before_relax()
4696
4697 Called just before relax() for rs_machine_dependent frags. The x86
4698 assembler uses these frags to handle variable size jump
4699 instructions.
4700
4701 Any symbol that is now undefined will not become defined.
4702 Return the correct fr_subtype in the frag.
4703 Return the initial "guess for variable size of frag" to caller.
4704 The guess is actually the growth beyond the fixed part. Whatever
4705 we do to grow the fixed or variable part contributes to our
4706 returned value. */
4707
252b5132
RH		 4708int
4709md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 4710 fragS *fragP;
4711 segT segment;
252b5132 4712{
252b5132 4713 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 4714 check for un-relaxable symbols. On an ELF system, we can't relax
4715 an externally visible symbol, because it may be overridden by a
4716 shared library. */
4717 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 4718#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 4719 || (IS_ELF
31312f95
AM		 4720 && (S_IS_EXTERNAL (fragP->fr_symbol)
4721 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 4722#endif
4723 )
252b5132 4724 {
b98ef147
AM		 4725 /* Symbol is undefined in this segment, or we need to keep a
4726 reloc so that weak symbols can be overridden. */
4727 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 4728 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 4729 unsigned char *opcode;
4730 int old_fr_fix;
f6af82bd 4731
ee7fcc42
AM		 4732 if (fragP->fr_var != NO_RELOC)
4733 reloc_type = fragP->fr_var;
b98ef147 4734 else if (size == 2)
f6af82bd
AM		 4735 reloc_type = BFD_RELOC_16_PCREL;
4736 else
4737 reloc_type = BFD_RELOC_32_PCREL;
252b5132 4738
ee7fcc42
AM		 4739 old_fr_fix = fragP->fr_fix;
4740 opcode = (unsigned char *) fragP->fr_opcode;
4741
fddf5b5b 4742 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 4743 {
fddf5b5b
AM		 4744 case UNCOND_JUMP:
4745 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 4746 opcode[0] = 0xe9;
252b5132 4747 fragP->fr_fix += size;
062cd5e7
AS		 4748 fix_new (fragP, old_fr_fix, size,
4749 fragP->fr_symbol,
4750 fragP->fr_offset, 1,
4751 reloc_type);
252b5132
RH		 4752 break;
4753
fddf5b5b 4754 case COND_JUMP86:
412167cb
AM		 4755 if (size == 2
4756 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 4757 {
4758 /* Negate the condition, and branch past an
4759 unconditional jump. */
4760 opcode[0] ^= 1;
4761 opcode[1] = 3;
4762 /* Insert an unconditional jump. */
4763 opcode[2] = 0xe9;
4764 /* We added two extra opcode bytes, and have a two byte
4765 offset. */
4766 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 4767 fix_new (fragP, old_fr_fix + 2, 2,
4768 fragP->fr_symbol,
4769 fragP->fr_offset, 1,
4770 reloc_type);
fddf5b5b
AM		 4771 break;
4772 }
4773 /* Fall through. */
4774
4775 case COND_JUMP:
412167cb
AM		 4776 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4777 {
3e02c1cc
AM		 4778 fixS *fixP;
4779
412167cb 4780 fragP->fr_fix += 1;
3e02c1cc
AM		 4781 fixP = fix_new (fragP, old_fr_fix, 1,
4782 fragP->fr_symbol,
4783 fragP->fr_offset, 1,
4784 BFD_RELOC_8_PCREL);
4785 fixP->fx_signed = 1;
412167cb
AM		 4786 break;
4787 }
93c2a809 4788
24eab124 4789 /* This changes the byte-displacement jump 0x7N
fddf5b5b 4790 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 4791 opcode[1] = opcode[0] + 0x10;
f6af82bd 4792 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 4793 /* We've added an opcode byte. */
4794 fragP->fr_fix += 1 + size;
062cd5e7
AS		 4795 fix_new (fragP, old_fr_fix + 1, size,
4796 fragP->fr_symbol,
4797 fragP->fr_offset, 1,
4798 reloc_type);
252b5132 4799 break;
fddf5b5b
AM		 4800
4801 default:
4802 BAD_CASE (fragP->fr_subtype);
4803 break;
252b5132
RH		 4804 }
4805 frag_wane (fragP);
ee7fcc42 4806 return fragP->fr_fix - old_fr_fix;
252b5132 4807 }
93c2a809 4808
93c2a809
AM		 4809 /* Guess size depending on current relax state. Initially the relax
4810 state will correspond to a short jump and we return 1, because
4811 the variable part of the frag (the branch offset) is one byte
4812 long. However, we can relax a section more than once and in that
4813 case we must either set fr_subtype back to the unrelaxed state,
4814 or return the value for the appropriate branch. */
4815 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 4816}
4817
47926f60
KH		 4818/* Called after relax() is finished.
4819
4820 In: Address of frag.
4821 fr_type == rs_machine_dependent.
4822 fr_subtype is what the address relaxed to.
4823
4824 Out: Any fixSs and constants are set up.
4825 Caller will turn frag into a ".space 0". */
4826
252b5132
RH		 4827void
4828md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 4829 bfd *abfd ATTRIBUTE_UNUSED;
4830 segT sec ATTRIBUTE_UNUSED;
29b0f896 4831 fragS *fragP;
252b5132 4832{
29b0f896 4833 unsigned char *opcode;
252b5132 4834 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 4835 offsetT target_address;
4836 offsetT opcode_address;
252b5132 4837 unsigned int extension = 0;
847f7ad4 4838 offsetT displacement_from_opcode_start;
252b5132
RH		 4839
4840 opcode = (unsigned char *) fragP->fr_opcode;
4841
47926f60 4842 /* Address we want to reach in file space. */
252b5132 4843 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 4844
47926f60 4845 /* Address opcode resides at in file space. */
252b5132
RH		 4846 opcode_address = fragP->fr_address + fragP->fr_fix;
4847
47926f60 4848 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 4849 displacement_from_opcode_start = target_address - opcode_address;
4850
fddf5b5b 4851 if ((fragP->fr_subtype & BIG) == 0)
252b5132 4852 {
47926f60
KH		 4853 /* Don't have to change opcode. */
4854 extension = 1; /* 1 opcode + 1 displacement */
252b5132 4855 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 4856 }
4857 else
4858 {
4859 if (no_cond_jump_promotion
4860 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4861 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 4862
fddf5b5b
AM		 4863 switch (fragP->fr_subtype)
4864 {
4865 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4866 extension = 4; /* 1 opcode + 4 displacement */
4867 opcode[0] = 0xe9;
4868 where_to_put_displacement = &opcode[1];
4869 break;
252b5132 4870
fddf5b5b
AM		 4871 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4872 extension = 2; /* 1 opcode + 2 displacement */
4873 opcode[0] = 0xe9;
4874 where_to_put_displacement = &opcode[1];
4875 break;
252b5132 4876
fddf5b5b
AM		 4877 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4878 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4879 extension = 5; /* 2 opcode + 4 displacement */
4880 opcode[1] = opcode[0] + 0x10;
4881 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4882 where_to_put_displacement = &opcode[2];
4883 break;
252b5132 4884
fddf5b5b
AM		 4885 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4886 extension = 3; /* 2 opcode + 2 displacement */
4887 opcode[1] = opcode[0] + 0x10;
4888 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4889 where_to_put_displacement = &opcode[2];
4890 break;
252b5132 4891
fddf5b5b
AM		 4892 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4893 extension = 4;
4894 opcode[0] ^= 1;
4895 opcode[1] = 3;
4896 opcode[2] = 0xe9;
4897 where_to_put_displacement = &opcode[3];
4898 break;
4899
4900 default:
4901 BAD_CASE (fragP->fr_subtype);
4902 break;
4903 }
252b5132 4904 }
fddf5b5b 4905
47926f60 4906 /* Now put displacement after opcode. */
252b5132
RH		 4907 md_number_to_chars ((char *) where_to_put_displacement,
4908 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 4909 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 4910 fragP->fr_fix += extension;
4911}
4912\f
47926f60
KH		 4913/* Size of byte displacement jmp. */
4914int md_short_jump_size = 2;
4915
4916/* Size of dword displacement jmp. */
4917int md_long_jump_size = 5;
252b5132 4918
252b5132
RH		 4919void
4920md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4921 char *ptr;
4922 addressT from_addr, to_addr;
ab9da554
ILT		 4923 fragS *frag ATTRIBUTE_UNUSED;
4924 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4925{
847f7ad4 4926 offsetT offset;
252b5132
RH		 4927
4928 offset = to_addr - (from_addr + 2);
47926f60
KH		 4929 /* Opcode for byte-disp jump. */
4930 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 4931 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4932}
4933
4934void
4935md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4936 char *ptr;
4937 addressT from_addr, to_addr;
a38cf1db
AM		 4938 fragS *frag ATTRIBUTE_UNUSED;
4939 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4940{
847f7ad4 4941 offsetT offset;
252b5132 4942
a38cf1db
AM		 4943 offset = to_addr - (from_addr + 5);
4944 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4945 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 4946}
4947\f
4948/* Apply a fixup (fixS) to segment data, once it has been determined
4949 by our caller that we have all the info we need to fix it up.
4950
4951 On the 386, immediates, displacements, and data pointers are all in
4952 the same (little-endian) format, so we don't need to care about which
4953 we are handling. */
4954
94f592af 4955void
55cf6793 4956md_apply_fix (fixP, valP, seg)
47926f60
KH		 4957 /* The fix we're to put in. */
4958 fixS *fixP;
47926f60 4959 /* Pointer to the value of the bits. */
c6682705 4960 valueT *valP;
47926f60
KH		 4961 /* Segment fix is from. */
4962 segT seg ATTRIBUTE_UNUSED;
252b5132 4963{
94f592af 4964 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 4965 valueT value = *valP;
252b5132 4966
f86103b7 4967#if !defined (TE_Mach)
93382f6d
AM		 4968 if (fixP->fx_pcrel)
4969 {
4970 switch (fixP->fx_r_type)
4971 {
5865bb77
ILT		 4972 default:
4973 break;
4974
d6ab8113
JB		 4975 case BFD_RELOC_64:
4976 fixP->fx_r_type = BFD_RELOC_64_PCREL;
4977 break;
93382f6d 4978 case BFD_RELOC_32:
ae8887b5 4979 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 4980 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4981 break;
4982 case BFD_RELOC_16:
4983 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4984 break;
4985 case BFD_RELOC_8:
4986 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4987 break;
4988 }
4989 }
252b5132 4990
a161fe53 4991 if (fixP->fx_addsy != NULL
31312f95 4992 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 4993 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 4994 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4995 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4996 && !use_rela_relocations)
252b5132 4997 {
31312f95
AM		 4998 /* This is a hack. There should be a better way to handle this.
4999 This covers for the fact that bfd_install_relocation will
5000 subtract the current location (for partial_inplace, PC relative
5001 relocations); see more below. */
252b5132 5002#ifndef OBJ_AOUT
718ddfc0 5003 if (IS_ELF
252b5132
RH		 5004#ifdef TE_PE
5005 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5006#endif
5007 )
5008 value += fixP->fx_where + fixP->fx_frag->fr_address;
5009#endif
5010#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5011 if (IS_ELF)
252b5132 5012 {
6539b54b 5013 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 5014
6539b54b 5015 if ((sym_seg == seg
2f66722d 5016 || (symbol_section_p (fixP->fx_addsy)
6539b54b 5017 && sym_seg != absolute_section))
ae6063d4 5018 && !generic_force_reloc (fixP))
2f66722d
AM		 5019 {
5020 /* Yes, we add the values in twice. This is because
6539b54b
AM		 5021 bfd_install_relocation subtracts them out again. I think
5022 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 5023 it. FIXME. */
5024 value += fixP->fx_where + fixP->fx_frag->fr_address;
5025 }
252b5132
RH		 5026 }
5027#endif
5028#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 5029 /* For some reason, the PE format does not store a
5030 section address offset for a PC relative symbol. */
5031 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 5032 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 5033 value += md_pcrel_from (fixP);
5034#endif
5035 }
5036
5037 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 5038 and we must not disappoint it. */
252b5132 5039#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5040 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 5041 switch (fixP->fx_r_type)
5042 {
5043 case BFD_RELOC_386_PLT32:
3e73aa7c 5044 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 5045 /* Make the jump instruction point to the address of the operand. At
5046 runtime we merely add the offset to the actual PLT entry. */
5047 value = -4;
5048 break;
31312f95 5049
13ae64f3
JJ		 5050 case BFD_RELOC_386_TLS_GD:
5051 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5052 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5053 case BFD_RELOC_386_TLS_IE:
5054 case BFD_RELOC_386_TLS_GOTIE:
bffbf940
JJ		 5055 case BFD_RELOC_X86_64_TLSGD:
5056 case BFD_RELOC_X86_64_TLSLD:
5057 case BFD_RELOC_X86_64_GOTTPOFF:
00f7efb6
JJ		 5058 value = 0; /* Fully resolved at runtime. No addend. */
5059 /* Fallthrough */
5060 case BFD_RELOC_386_TLS_LE:
5061 case BFD_RELOC_386_TLS_LDO_32:
5062 case BFD_RELOC_386_TLS_LE_32:
5063 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5064 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5065 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5066 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5067 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5068 break;
5069
5070 case BFD_RELOC_386_GOT32:
5071 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5072 value = 0; /* Fully resolved at runtime. No addend. */
5073 break;
47926f60
KH		 5074
5075 case BFD_RELOC_VTABLE_INHERIT:
5076 case BFD_RELOC_VTABLE_ENTRY:
5077 fixP->fx_done = 0;
94f592af 5078 return;
47926f60
KH		 5079
5080 default:
5081 break;
5082 }
5083#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5084 *valP = value;
f86103b7 5085#endif /* !defined (TE_Mach) */
3e73aa7c 5086
3e73aa7c 5087 /* Are we finished with this relocation now? */
c6682705 5088 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5089 fixP->fx_done = 1;
5090 else if (use_rela_relocations)
5091 {
5092 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5093 /* Remember value for tc_gen_reloc. */
5094 fixP->fx_addnumber = value;
3e73aa7c
JH		 5095 value = 0;
5096 }
f86103b7 5097
94f592af 5098 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5099}
252b5132 5100\f
252b5132
RH		 5101#define MAX_LITTLENUMS 6
5102
47926f60
KH		 5103/* Turn the string pointed to by litP into a floating point constant
5104 of type TYPE, and emit the appropriate bytes. The number of
5105 LITTLENUMS emitted is stored in *SIZEP. An error message is
5106 returned, or NULL on OK. */
5107
252b5132
RH		 5108char *
5109md_atof (type, litP, sizeP)
2ab9b79e 5110 int type;
252b5132
RH		 5111 char *litP;
5112 int *sizeP;
5113{
5114 int prec;
5115 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5116 LITTLENUM_TYPE *wordP;
5117 char *t;
5118
5119 switch (type)
5120 {
5121 case 'f':
5122 case 'F':
5123 prec = 2;
5124 break;
5125
5126 case 'd':
5127 case 'D':
5128 prec = 4;
5129 break;
5130
5131 case 'x':
5132 case 'X':
5133 prec = 5;
5134 break;
5135
5136 default:
5137 *sizeP = 0;
5138 return _("Bad call to md_atof ()");
5139 }
5140 t = atof_ieee (input_line_pointer, type, words);
5141 if (t)
5142 input_line_pointer = t;
5143
5144 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5145 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5146 the bigendian 386. */
5147 for (wordP = words + prec - 1; prec--;)
5148 {
5149 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5150 litP += sizeof (LITTLENUM_TYPE);
5151 }
5152 return 0;
5153}
5154\f
87c245cc 5155static char output_invalid_buf[8];
252b5132 5156
252b5132
RH		 5157static char *
5158output_invalid (c)
5159 int c;
5160{
3882b010 5161 if (ISPRINT (c))
252b5132
RH		 5162 sprintf (output_invalid_buf, "'%c'", c);
5163 else
5164 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
5165 return output_invalid_buf;
5166}
5167
af6bdddf 5168/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5169
5170static const reg_entry *
4d1bb795 5171parse_real_register (char *reg_string, char **end_op)
252b5132 5172{
af6bdddf
AM		 5173 char *s = reg_string;
5174 char *p;
252b5132
RH		 5175 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5176 const reg_entry *r;
5177
5178 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5179 if (*s == REGISTER_PREFIX)
5180 ++s;
5181
5182 if (is_space_char (*s))
5183 ++s;
5184
5185 p = reg_name_given;
af6bdddf 5186 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5187 {
5188 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5189 return (const reg_entry *) NULL;
5190 s++;
252b5132
RH		 5191 }
5192
6588847e
DN		 5193 /* For naked regs, make sure that we are not dealing with an identifier.
5194 This prevents confusing an identifier like `eax_var' with register
5195 `eax'. */
5196 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5197 return (const reg_entry *) NULL;
5198
af6bdddf 5199 *end_op = s;
252b5132
RH		 5200
5201 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5202
5f47d35b 5203 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5204 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5205 {
5f47d35b
AM		 5206 if (is_space_char (*s))
5207 ++s;
5208 if (*s == '(')
5209 {
af6bdddf 5210 ++s;
5f47d35b
AM		 5211 if (is_space_char (*s))
5212 ++s;
5213 if (*s >= '0' && *s <= '7')
5214 {
5215 r = &i386_float_regtab[*s - '0'];
af6bdddf 5216 ++s;
5f47d35b
AM		 5217 if (is_space_char (*s))
5218 ++s;
5219 if (*s == ')')
5220 {
5221 *end_op = s + 1;
5222 return r;
5223 }
5f47d35b 5224 }
47926f60 5225 /* We have "%st(" then garbage. */
5f47d35b
AM		 5226 return (const reg_entry *) NULL;
5227 }
5228 }
5229
1ae00879 5230 if (r != NULL
20f0a1fc 5231 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5232 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5233 && flag_code != CODE_64BIT)
20f0a1fc 5234 return (const reg_entry *) NULL;
1ae00879 5235
252b5132
RH		 5236 return r;
5237}
4d1bb795
JB		 5238
5239/* REG_STRING starts *before* REGISTER_PREFIX. */
5240
5241static const reg_entry *
5242parse_register (char *reg_string, char **end_op)
5243{
5244 const reg_entry *r;
5245
5246 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5247 r = parse_real_register (reg_string, end_op);
5248 else
5249 r = NULL;
5250 if (!r)
5251 {
5252 char *save = input_line_pointer;
5253 char c;
5254 symbolS *symbolP;
5255
5256 input_line_pointer = reg_string;
5257 c = get_symbol_end ();
5258 symbolP = symbol_find (reg_string);
5259 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5260 {
5261 const expressionS *e = symbol_get_value_expression (symbolP);
5262
5263 know (e->X_op == O_register);
5264 know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab));
5265 r = i386_regtab + e->X_add_number;
5266 *end_op = input_line_pointer;
5267 }
5268 *input_line_pointer = c;
5269 input_line_pointer = save;
5270 }
5271 return r;
5272}
5273
5274int
5275i386_parse_name (char *name, expressionS *e, char *nextcharP)
5276{
5277 const reg_entry *r;
5278 char *end = input_line_pointer;
5279
5280 *end = *nextcharP;
5281 r = parse_register (name, &input_line_pointer);
5282 if (r && end <= input_line_pointer)
5283 {
5284 *nextcharP = *input_line_pointer;
5285 *input_line_pointer = 0;
5286 e->X_op = O_register;
5287 e->X_add_number = r - i386_regtab;
5288 return 1;
5289 }
5290 input_line_pointer = end;
5291 *end = 0;
5292 return 0;
5293}
5294
5295void
5296md_operand (expressionS *e)
5297{
5298 if (*input_line_pointer == REGISTER_PREFIX)
5299 {
5300 char *end;
5301 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5302
5303 if (r)
5304 {
5305 e->X_op = O_register;
5306 e->X_add_number = r - i386_regtab;
5307 input_line_pointer = end;
5308 }
5309 }
5310}
5311
252b5132 5312\f
4cc782b5 5313#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5314const char *md_shortopts = "kVQ:sqn";
252b5132 5315#else
12b55ccc 5316const char *md_shortopts = "qn";
252b5132 5317#endif
6e0b89ee 5318
3e73aa7c 5319#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 5320#define OPTION_64 (OPTION_MD_BASE + 1)
5321#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
5322
5323struct option md_longopts[] = {
3e73aa7c 5324 {"32", no_argument, NULL, OPTION_32},
6e0b89ee 5325#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3e73aa7c 5326 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5327#endif
b3b91714 5328 {"divide", no_argument, NULL, OPTION_DIVIDE},
252b5132
RH		 5329 {NULL, no_argument, NULL, 0}
5330};
5331size_t md_longopts_size = sizeof (md_longopts);
5332
5333int
5334md_parse_option (c, arg)
5335 int c;
ab9da554 5336 char *arg ATTRIBUTE_UNUSED;
252b5132
RH		 5337{
5338 switch (c)
5339 {
12b55ccc
L		 5340 case 'n':
5341 optimize_align_code = 0;
5342 break;
5343
a38cf1db
AM		 5344 case 'q':
5345 quiet_warnings = 1;
252b5132
RH		 5346 break;
5347
5348#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5349 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5350 should be emitted or not. FIXME: Not implemented. */
5351 case 'Q':
252b5132
RH		 5352 break;
5353
5354 /* -V: SVR4 argument to print version ID. */
5355 case 'V':
5356 print_version_id ();
5357 break;
5358
a38cf1db
AM		 5359 /* -k: Ignore for FreeBSD compatibility. */
5360 case 'k':
252b5132 5361 break;
4cc782b5
ILT		 5362
5363 case 's':
5364 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5365 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5366 break;
6e0b89ee 5367
3e73aa7c
JH		 5368 case OPTION_64:
5369 {
5370 const char **list, **l;
5371
3e73aa7c
JH		 5372 list = bfd_target_list ();
5373 for (l = list; *l != NULL; l++)
6e0b89ee
AM		 5374 if (strcmp (*l, "elf64-x86-64") == 0)
5375 {
5376 default_arch = "x86_64";
5377 break;
5378 }
3e73aa7c 5379 if (*l == NULL)
6e0b89ee 5380 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5381 free (list);
5382 }
5383 break;
5384#endif
252b5132 5385
6e0b89ee
AM		 5386 case OPTION_32:
5387 default_arch = "i386";
5388 break;
5389
b3b91714
AM		 5390 case OPTION_DIVIDE:
5391#ifdef SVR4_COMMENT_CHARS
5392 {
5393 char *n, *t;
5394 const char *s;
5395
5396 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5397 t = n;
5398 for (s = i386_comment_chars; *s != '\0'; s++)
5399 if (*s != '/')
5400 *t++ = *s;
5401 *t = '\0';
5402 i386_comment_chars = n;
5403 }
5404#endif
5405 break;
5406
252b5132
RH		 5407 default:
5408 return 0;
5409 }
5410 return 1;
5411}
5412
5413void
5414md_show_usage (stream)
5415 FILE *stream;
5416{
4cc782b5
ILT		 5417#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5418 fprintf (stream, _("\
a38cf1db
AM		 5419 -Q ignored\n\
5420 -V print assembler version number\n\
b3b91714
AM		 5421 -k ignored\n"));
5422#endif
5423 fprintf (stream, _("\
12b55ccc 5424 -n Do not optimize code alignment\n\
b3b91714
AM		 5425 -q quieten some warnings\n"));
5426#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5427 fprintf (stream, _("\
a38cf1db 5428 -s ignored\n"));
b3b91714
AM		 5429#endif
5430#ifdef SVR4_COMMENT_CHARS
5431 fprintf (stream, _("\
5432 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 5433#else
5434 fprintf (stream, _("\
b3b91714 5435 --divide ignored\n"));
4cc782b5 5436#endif
252b5132
RH		 5437}
5438
3e73aa7c
JH		 5439#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5440 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 5441
5442/* Pick the target format to use. */
5443
47926f60 5444const char *
252b5132
RH		 5445i386_target_format ()
5446{
3e73aa7c
JH		 5447 if (!strcmp (default_arch, "x86_64"))
5448 set_code_flag (CODE_64BIT);
5449 else if (!strcmp (default_arch, "i386"))
5450 set_code_flag (CODE_32BIT);
5451 else
5452 as_fatal (_("Unknown architecture"));
252b5132
RH		 5453 switch (OUTPUT_FLAVOR)
5454 {
4c63da97
AM		 5455#ifdef OBJ_MAYBE_AOUT
5456 case bfd_target_aout_flavour:
47926f60 5457 return AOUT_TARGET_FORMAT;
4c63da97
AM		 5458#endif
5459#ifdef OBJ_MAYBE_COFF
252b5132
RH		 5460 case bfd_target_coff_flavour:
5461 return "coff-i386";
4c63da97 5462#endif
3e73aa7c 5463#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 5464 case bfd_target_elf_flavour:
3e73aa7c 5465 {
e5cb08ac 5466 if (flag_code == CODE_64BIT)
4fa24527
JB		 5467 {
5468 object_64bit = 1;
5469 use_rela_relocations = 1;
5470 }
4ada7262 5471 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
3e73aa7c 5472 }
4c63da97 5473#endif
252b5132
RH		 5474 default:
5475 abort ();
5476 return NULL;
5477 }
5478}
5479
47926f60 5480#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 5481
5482#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5483void i386_elf_emit_arch_note ()
5484{
718ddfc0 5485 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 5486 {
5487 char *p;
5488 asection *seg = now_seg;
5489 subsegT subseg = now_subseg;
5490 Elf_Internal_Note i_note;
5491 Elf_External_Note e_note;
5492 asection *note_secp;
5493 int len;
5494
5495 /* Create the .note section. */
5496 note_secp = subseg_new (".note", 0);
5497 bfd_set_section_flags (stdoutput,
5498 note_secp,
5499 SEC_HAS_CONTENTS | SEC_READONLY);
5500
5501 /* Process the arch string. */
5502 len = strlen (cpu_arch_name);
5503
5504 i_note.namesz = len + 1;
5505 i_note.descsz = 0;
5506 i_note.type = NT_ARCH;
5507 p = frag_more (sizeof (e_note.namesz));
5508 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
5509 p = frag_more (sizeof (e_note.descsz));
5510 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
5511 p = frag_more (sizeof (e_note.type));
5512 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
5513 p = frag_more (len + 1);
5514 strcpy (p, cpu_arch_name);
5515
5516 frag_align (2, 0, 0);
5517
5518 subseg_set (seg, subseg);
5519 }
5520}
5521#endif
252b5132 5522\f
252b5132
RH		 5523symbolS *
5524md_undefined_symbol (name)
5525 char *name;
5526{
18dc2407
ILT		 5527 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
5528 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
5529 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
5530 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 5531 {
5532 if (!GOT_symbol)
5533 {
5534 if (symbol_find (name))
5535 as_bad (_("GOT already in symbol table"));
5536 GOT_symbol = symbol_new (name, undefined_section,
5537 (valueT) 0, &zero_address_frag);
5538 };
5539 return GOT_symbol;
5540 }
252b5132
RH		 5541 return 0;
5542}
5543
5544/* Round up a section size to the appropriate boundary. */
47926f60 5545
252b5132
RH		 5546valueT
5547md_section_align (segment, size)
ab9da554 5548 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 5549 valueT size;
5550{
4c63da97
AM		 5551#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5552 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
5553 {
5554 /* For a.out, force the section size to be aligned. If we don't do
5555 this, BFD will align it for us, but it will not write out the
5556 final bytes of the section. This may be a bug in BFD, but it is
5557 easier to fix it here since that is how the other a.out targets
5558 work. */
5559 int align;
5560
5561 align = bfd_get_section_alignment (stdoutput, segment);
5562 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
5563 }
252b5132
RH		 5564#endif
5565
5566 return size;
5567}
5568
5569/* On the i386, PC-relative offsets are relative to the start of the
5570 next instruction. That is, the address of the offset, plus its
5571 size, since the offset is always the last part of the insn. */
5572
5573long
5574md_pcrel_from (fixP)
5575 fixS *fixP;
5576{
5577 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5578}
5579
5580#ifndef I386COFF
5581
5582static void
5583s_bss (ignore)
ab9da554 5584 int ignore ATTRIBUTE_UNUSED;
252b5132 5585{
29b0f896 5586 int temp;
252b5132 5587
8a75718c
JB		 5588#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5589 if (IS_ELF)
5590 obj_elf_section_change_hook ();
5591#endif
252b5132
RH		 5592 temp = get_absolute_expression ();
5593 subseg_set (bss_section, (subsegT) temp);
5594 demand_empty_rest_of_line ();
5595}
5596
5597#endif
5598
252b5132
RH		 5599void
5600i386_validate_fix (fixp)
5601 fixS *fixp;
5602{
5603 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5604 {
23df1078
JH		 5605 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5606 {
4fa24527 5607 if (!object_64bit)
23df1078
JH		 5608 abort ();
5609 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5610 }
5611 else
5612 {
4fa24527 5613 if (!object_64bit)
d6ab8113
JB		 5614 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5615 else
5616 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 5617 }
252b5132
RH		 5618 fixp->fx_subsy = 0;
5619 }
5620}
5621
252b5132
RH		 5622arelent *
5623tc_gen_reloc (section, fixp)
ab9da554 5624 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 5625 fixS *fixp;
5626{
5627 arelent *rel;
5628 bfd_reloc_code_real_type code;
5629
5630 switch (fixp->fx_r_type)
5631 {
3e73aa7c
JH		 5632 case BFD_RELOC_X86_64_PLT32:
5633 case BFD_RELOC_X86_64_GOT32:
5634 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 5635 case BFD_RELOC_386_PLT32:
5636 case BFD_RELOC_386_GOT32:
5637 case BFD_RELOC_386_GOTOFF:
5638 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 5639 case BFD_RELOC_386_TLS_GD:
5640 case BFD_RELOC_386_TLS_LDM:
5641 case BFD_RELOC_386_TLS_LDO_32:
5642 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5643 case BFD_RELOC_386_TLS_IE:
5644 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 5645 case BFD_RELOC_386_TLS_LE_32:
5646 case BFD_RELOC_386_TLS_LE:
bffbf940
JJ		 5647 case BFD_RELOC_X86_64_TLSGD:
5648 case BFD_RELOC_X86_64_TLSLD:
5649 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5650 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 5651 case BFD_RELOC_X86_64_GOTTPOFF:
5652 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 5653 case BFD_RELOC_X86_64_TPOFF64:
5654 case BFD_RELOC_X86_64_GOTOFF64:
5655 case BFD_RELOC_X86_64_GOTPC32:
252b5132
RH		 5656 case BFD_RELOC_RVA:
5657 case BFD_RELOC_VTABLE_ENTRY:
5658 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 5659#ifdef TE_PE
5660 case BFD_RELOC_32_SECREL:
5661#endif
252b5132
RH		 5662 code = fixp->fx_r_type;
5663 break;
dbbaec26
L		 5664 case BFD_RELOC_X86_64_32S:
5665 if (!fixp->fx_pcrel)
5666 {
5667 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
5668 code = fixp->fx_r_type;
5669 break;
5670 }
252b5132 5671 default:
93382f6d 5672 if (fixp->fx_pcrel)
252b5132 5673 {
93382f6d
AM		 5674 switch (fixp->fx_size)
5675 {
5676 default:
b091f402
AM		 5677 as_bad_where (fixp->fx_file, fixp->fx_line,
5678 _("can not do %d byte pc-relative relocation"),
5679 fixp->fx_size);
93382f6d
AM		 5680 code = BFD_RELOC_32_PCREL;
5681 break;
5682 case 1: code = BFD_RELOC_8_PCREL; break;
5683 case 2: code = BFD_RELOC_16_PCREL; break;
5684 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 5685#ifdef BFD64
5686 case 8: code = BFD_RELOC_64_PCREL; break;
5687#endif
93382f6d
AM		 5688 }
5689 }
5690 else
5691 {
5692 switch (fixp->fx_size)
5693 {
5694 default:
b091f402
AM		 5695 as_bad_where (fixp->fx_file, fixp->fx_line,
5696 _("can not do %d byte relocation"),
5697 fixp->fx_size);
93382f6d
AM		 5698 code = BFD_RELOC_32;
5699 break;
5700 case 1: code = BFD_RELOC_8; break;
5701 case 2: code = BFD_RELOC_16; break;
5702 case 4: code = BFD_RELOC_32; break;
937149dd 5703#ifdef BFD64
3e73aa7c 5704 case 8: code = BFD_RELOC_64; break;
937149dd 5705#endif
93382f6d 5706 }
252b5132
RH		 5707 }
5708 break;
5709 }
252b5132 5710
d182319b
JB		 5711 if ((code == BFD_RELOC_32
5712 || code == BFD_RELOC_32_PCREL
5713 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 5714 && GOT_symbol
5715 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 5716 {
4fa24527 5717 if (!object_64bit)
d6ab8113
JB		 5718 code = BFD_RELOC_386_GOTPC;
5719 else
5720 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 5721 }
252b5132
RH		 5722
5723 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 5724 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5725 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 5726
5727 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 5728
3e73aa7c
JH		 5729 if (!use_rela_relocations)
5730 {
5731 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5732 vtable entry to be used in the relocation's section offset. */
5733 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5734 rel->address = fixp->fx_offset;
252b5132 5735
c6682705 5736 rel->addend = 0;
3e73aa7c
JH		 5737 }
5738 /* Use the rela in 64bit mode. */
252b5132 5739 else
3e73aa7c 5740 {
062cd5e7
AS		 5741 if (!fixp->fx_pcrel)
5742 rel->addend = fixp->fx_offset;
5743 else
5744 switch (code)
5745 {
5746 case BFD_RELOC_X86_64_PLT32:
5747 case BFD_RELOC_X86_64_GOT32:
5748 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 5749 case BFD_RELOC_X86_64_TLSGD:
5750 case BFD_RELOC_X86_64_TLSLD:
5751 case BFD_RELOC_X86_64_GOTTPOFF:
062cd5e7
AS		 5752 rel->addend = fixp->fx_offset - fixp->fx_size;
5753 break;
5754 default:
5755 rel->addend = (section->vma
5756 - fixp->fx_size
5757 + fixp->fx_addnumber
5758 + md_pcrel_from (fixp));
5759 break;
5760 }
3e73aa7c
JH		 5761 }
5762
252b5132
RH		 5763 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5764 if (rel->howto == NULL)
5765 {
5766 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 5767 _("cannot represent relocation type %s"),
252b5132
RH		 5768 bfd_get_reloc_code_name (code));
5769 /* Set howto to a garbage value so that we can keep going. */
5770 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5771 assert (rel->howto != NULL);
5772 }
5773
5774 return rel;
5775}
5776
64a0c779
DN		 5777\f
5778/* Parse operands using Intel syntax. This implements a recursive descent
5779 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5780 Programmer's Guide.
5781
5782 FIXME: We do not recognize the full operand grammar defined in the MASM
5783 documentation. In particular, all the structure/union and
5784 high-level macro operands are missing.
5785
5786 Uppercase words are terminals, lower case words are non-terminals.
5787 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5788 bars '|' denote choices. Most grammar productions are implemented in
5789 functions called 'intel_<production>'.
5790
5791 Initial production is 'expr'.
5792
9306ca4a 5793 addOp + | -
64a0c779
DN		 5794
5795 alpha [a-zA-Z]
5796
9306ca4a
JB		 5797 binOp & | AND | \| | OR | ^ | XOR
5798
64a0c779
DN		 5799 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5800
5801 constant digits [[ radixOverride ]]
5802
9306ca4a 5803 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 5804
5805 digits decdigit
b77a7acd
AJ		 5806 | digits decdigit
5807 | digits hexdigit
64a0c779
DN		 5808
5809 decdigit [0-9]
5810
9306ca4a
JB		 5811 e04 e04 addOp e05
5812 | e05
5813
5814 e05 e05 binOp e06
b77a7acd 5815 | e06
64a0c779
DN		 5816
5817 e06 e06 mulOp e09
b77a7acd 5818 | e09
64a0c779
DN		 5819
5820 e09 OFFSET e10
a724f0f4
JB		 5821 | SHORT e10
5822 | + e10
5823 | - e10
9306ca4a
JB		 5824 | ~ e10
5825 | NOT e10
64a0c779
DN		 5826 | e09 PTR e10
5827 | e09 : e10
5828 | e10
5829
5830 e10 e10 [ expr ]
b77a7acd 5831 | e11
64a0c779
DN		 5832
5833 e11 ( expr )
b77a7acd 5834 | [ expr ]
64a0c779
DN		 5835 | constant
5836 | dataType
5837 | id
5838 | $
5839 | register
5840
a724f0f4 5841 => expr expr cmpOp e04
9306ca4a 5842 | e04
64a0c779
DN		 5843
5844 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 5845 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 5846
5847 hexdigit a | b | c | d | e | f
b77a7acd 5848 | A | B | C | D | E | F
64a0c779
DN		 5849
5850 id alpha
b77a7acd 5851 | id alpha
64a0c779
DN		 5852 | id decdigit
5853
9306ca4a 5854 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 5855
5856 quote " | '
5857
5858 register specialRegister
b77a7acd 5859 | gpRegister
64a0c779
DN		 5860 | byteRegister
5861
5862 segmentRegister CS | DS | ES | FS | GS | SS
5863
9306ca4a 5864 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 5865 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 5866 | TR3 | TR4 | TR5 | TR6 | TR7
5867
64a0c779
DN		 5868 We simplify the grammar in obvious places (e.g., register parsing is
5869 done by calling parse_register) and eliminate immediate left recursion
5870 to implement a recursive-descent parser.
5871
a724f0f4
JB		 5872 expr e04 expr'
5873
5874 expr' cmpOp e04 expr'
5875 | Empty
9306ca4a
JB		 5876
5877 e04 e05 e04'
5878
5879 e04' addOp e05 e04'
5880 | Empty
64a0c779
DN		 5881
5882 e05 e06 e05'
5883
9306ca4a 5884 e05' binOp e06 e05'
b77a7acd 5885 | Empty
64a0c779
DN		 5886
5887 e06 e09 e06'
5888
5889 e06' mulOp e09 e06'
b77a7acd 5890 | Empty
64a0c779
DN		 5891
5892 e09 OFFSET e10 e09'
a724f0f4
JB		 5893 | SHORT e10'
5894 | + e10'
5895 | - e10'
5896 | ~ e10'
5897 | NOT e10'
b77a7acd 5898 | e10 e09'
64a0c779
DN		 5899
5900 e09' PTR e10 e09'
b77a7acd 5901 | : e10 e09'
64a0c779
DN		 5902 | Empty
5903
5904 e10 e11 e10'
5905
5906 e10' [ expr ] e10'
b77a7acd 5907 | Empty
64a0c779
DN		 5908
5909 e11 ( expr )
b77a7acd 5910 | [ expr ]
64a0c779
DN		 5911 | BYTE
5912 | WORD
5913 | DWORD
9306ca4a 5914 | FWORD
64a0c779 5915 | QWORD
9306ca4a
JB		 5916 | TBYTE
5917 | OWORD
5918 | XMMWORD
64a0c779
DN		 5919 | .
5920 | $
5921 | register
5922 | id
5923 | constant */
5924
5925/* Parsing structure for the intel syntax parser. Used to implement the
5926 semantic actions for the operand grammar. */
5927struct intel_parser_s
5928 {
5929 char *op_string; /* The string being parsed. */
5930 int got_a_float; /* Whether the operand is a float. */
4a1805b1 5931 int op_modifier; /* Operand modifier. */
64a0c779 5932 int is_mem; /* 1 if operand is memory reference. */
a724f0f4
JB		 5933 int in_offset; /* >=1 if parsing operand of offset. */
5934 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 5935 const reg_entry *reg; /* Last register reference found. */
5936 char *disp; /* Displacement string being built. */
a724f0f4 5937 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 5938 };
5939
5940static struct intel_parser_s intel_parser;
5941
5942/* Token structure for parsing intel syntax. */
5943struct intel_token
5944 {
5945 int code; /* Token code. */
5946 const reg_entry *reg; /* Register entry for register tokens. */
5947 char *str; /* String representation. */
5948 };
5949
5950static struct intel_token cur_token, prev_token;
5951
50705ef4
AM		 5952/* Token codes for the intel parser. Since T_SHORT is already used
5953 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 5954#define T_NIL -1
5955#define T_CONST 1
5956#define T_REG 2
5957#define T_BYTE 3
5958#define T_WORD 4
9306ca4a
JB		 5959#define T_DWORD 5
5960#define T_FWORD 6
5961#define T_QWORD 7
5962#define T_TBYTE 8
5963#define T_XMMWORD 9
50705ef4 5964#undef T_SHORT
9306ca4a
JB		 5965#define T_SHORT 10
5966#define T_OFFSET 11
5967#define T_PTR 12
5968#define T_ID 13
5969#define T_SHL 14
5970#define T_SHR 15
64a0c779
DN		 5971
5972/* Prototypes for intel parser functions. */
5973static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 5974static void intel_get_token PARAMS ((void));
5975static void intel_putback_token PARAMS ((void));
5976static int intel_expr PARAMS ((void));
9306ca4a 5977static int intel_e04 PARAMS ((void));
cce0cbdc 5978static int intel_e05 PARAMS ((void));
cce0cbdc 5979static int intel_e06 PARAMS ((void));
cce0cbdc 5980static int intel_e09 PARAMS ((void));
a724f0f4 5981static int intel_bracket_expr PARAMS ((void));
cce0cbdc 5982static int intel_e10 PARAMS ((void));
cce0cbdc 5983static int intel_e11 PARAMS ((void));
64a0c779 5984
64a0c779
DN		 5985static int
5986i386_intel_operand (operand_string, got_a_float)
5987 char *operand_string;
5988 int got_a_float;
5989{
5990 int ret;
5991 char *p;
5992
a724f0f4
JB		 5993 p = intel_parser.op_string = xstrdup (operand_string);
5994 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
5995
5996 for (;;)
64a0c779 5997 {
a724f0f4
JB		 5998 /* Initialize token holders. */
5999 cur_token.code = prev_token.code = T_NIL;
6000 cur_token.reg = prev_token.reg = NULL;
6001 cur_token.str = prev_token.str = NULL;
6002
6003 /* Initialize parser structure. */
6004 intel_parser.got_a_float = got_a_float;
6005 intel_parser.op_modifier = 0;
6006 intel_parser.is_mem = 0;
6007 intel_parser.in_offset = 0;
6008 intel_parser.in_bracket = 0;
6009 intel_parser.reg = NULL;
6010 intel_parser.disp[0] = '\0';
6011 intel_parser.next_operand = NULL;
6012
6013 /* Read the first token and start the parser. */
6014 intel_get_token ();
6015 ret = intel_expr ();
6016
6017 if (!ret)
6018 break;
6019
9306ca4a
JB		 6020 if (cur_token.code != T_NIL)
6021 {
6022 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6023 current_templates->start->name, cur_token.str);
6024 ret = 0;
6025 }
64a0c779
DN		 6026 /* If we found a memory reference, hand it over to i386_displacement
6027 to fill in the rest of the operand fields. */
9306ca4a 6028 else if (intel_parser.is_mem)
64a0c779
DN		 6029 {
6030 if ((i.mem_operands == 1
6031 && (current_templates->start->opcode_modifier & IsString) == 0)
6032 || i.mem_operands == 2)
6033 {
6034 as_bad (_("too many memory references for '%s'"),
6035 current_templates->start->name);
6036 ret = 0;
6037 }
6038 else
6039 {
6040 char *s = intel_parser.disp;
6041 i.mem_operands++;
6042
a724f0f4
JB		 6043 if (!quiet_warnings && intel_parser.is_mem < 0)
6044 /* See the comments in intel_bracket_expr. */
6045 as_warn (_("Treating `%s' as memory reference"), operand_string);
6046
64a0c779
DN		 6047 /* Add the displacement expression. */
6048 if (*s != '\0')
a4622f40
AM		 6049 ret = i386_displacement (s, s + strlen (s));
6050 if (ret)
a724f0f4
JB		 6051 {
6052 /* Swap base and index in 16-bit memory operands like
6053 [si+bx]. Since i386_index_check is also used in AT&T
6054 mode we have to do that here. */
6055 if (i.base_reg
6056 && i.index_reg
6057 && (i.base_reg->reg_type & Reg16)
6058 && (i.index_reg->reg_type & Reg16)
6059 && i.base_reg->reg_num >= 6
6060 && i.index_reg->reg_num < 6)
6061 {
6062 const reg_entry *base = i.index_reg;
6063
6064 i.index_reg = i.base_reg;
6065 i.base_reg = base;
6066 }
6067 ret = i386_index_check (operand_string);
6068 }
64a0c779
DN		 6069 }
6070 }
6071
6072 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 6073 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 6074 || intel_parser.reg == NULL)
6075 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 6076
6077 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
6078 ret = 0;
6079 if (!ret || !intel_parser.next_operand)
6080 break;
6081 intel_parser.op_string = intel_parser.next_operand;
6082 this_operand = i.operands++;
64a0c779
DN		 6083 }
6084
6085 free (p);
6086 free (intel_parser.disp);
6087
6088 return ret;
6089}
6090
a724f0f4
JB		 6091#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6092
6093/* expr e04 expr'
6094
6095 expr' cmpOp e04 expr'
6096 | Empty */
64a0c779
DN		 6097static int
6098intel_expr ()
6099{
a724f0f4
JB		 6100 /* XXX Implement the comparison operators. */
6101 return intel_e04 ();
9306ca4a
JB		 6102}
6103
a724f0f4 6104/* e04 e05 e04'
9306ca4a 6105
a724f0f4 6106 e04' addOp e05 e04'
9306ca4a
JB		 6107 | Empty */
6108static int
6109intel_e04 ()
6110{
a724f0f4 6111 int nregs = -1;
9306ca4a 6112
a724f0f4 6113 for (;;)
9306ca4a 6114 {
a724f0f4
JB		 6115 if (!intel_e05())
6116 return 0;
9306ca4a 6117
a724f0f4
JB		 6118 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6119 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 6120
a724f0f4
JB		 6121 if (cur_token.code == '+')
6122 nregs = -1;
6123 else if (cur_token.code == '-')
6124 nregs = NUM_ADDRESS_REGS;
6125 else
6126 return 1;
64a0c779 6127
a724f0f4
JB		 6128 strcat (intel_parser.disp, cur_token.str);
6129 intel_match_token (cur_token.code);
6130 }
64a0c779
DN		 6131}
6132
64a0c779
DN		 6133/* e05 e06 e05'
6134
9306ca4a 6135 e05' binOp e06 e05'
64a0c779
DN		 6136 | Empty */
6137static int
6138intel_e05 ()
6139{
a724f0f4 6140 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6141
a724f0f4 6142 for (;;)
64a0c779 6143 {
a724f0f4
JB		 6144 if (!intel_e06())
6145 return 0;
6146
6147 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6148 {
6149 char str[2];
6150
6151 str[0] = cur_token.code;
6152 str[1] = 0;
6153 strcat (intel_parser.disp, str);
6154 }
6155 else
6156 break;
9306ca4a 6157
64a0c779
DN		 6158 intel_match_token (cur_token.code);
6159
a724f0f4
JB		 6160 if (nregs < 0)
6161 nregs = ~nregs;
64a0c779 6162 }
a724f0f4
JB		 6163 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6164 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6165 return 1;
4a1805b1 6166}
64a0c779
DN		 6167
6168/* e06 e09 e06'
6169
6170 e06' mulOp e09 e06'
b77a7acd 6171 | Empty */
64a0c779
DN		 6172static int
6173intel_e06 ()
6174{
a724f0f4 6175 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6176
a724f0f4 6177 for (;;)
64a0c779 6178 {
a724f0f4
JB		 6179 if (!intel_e09())
6180 return 0;
9306ca4a 6181
a724f0f4
JB		 6182 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6183 {
6184 char str[2];
9306ca4a 6185
a724f0f4
JB		 6186 str[0] = cur_token.code;
6187 str[1] = 0;
6188 strcat (intel_parser.disp, str);
6189 }
6190 else if (cur_token.code == T_SHL)
6191 strcat (intel_parser.disp, "<<");
6192 else if (cur_token.code == T_SHR)
6193 strcat (intel_parser.disp, ">>");
6194 else
6195 break;
9306ca4a 6196
a724f0f4 6197 intel_match_token (cur_token.code);
64a0c779 6198
a724f0f4
JB		 6199 if (nregs < 0)
6200 nregs = ~nregs;
64a0c779 6201 }
a724f0f4
JB		 6202 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6203 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6204 return 1;
64a0c779
DN		 6205}
6206
a724f0f4
JB		 6207/* e09 OFFSET e09
6208 | SHORT e09
6209 | + e09
6210 | - e09
6211 | ~ e09
6212 | NOT e09
9306ca4a
JB		 6213 | e10 e09'
6214
64a0c779 6215 e09' PTR e10 e09'
b77a7acd 6216 | : e10 e09'
64a0c779
DN		 6217 | Empty */
6218static int
6219intel_e09 ()
6220{
a724f0f4
JB		 6221 int nregs = ~NUM_ADDRESS_REGS;
6222 int in_offset = 0;
6223
6224 for (;;)
64a0c779 6225 {
a724f0f4
JB		 6226 /* Don't consume constants here. */
6227 if (cur_token.code == '+' || cur_token.code == '-')
6228 {
6229 /* Need to look one token ahead - if the next token
6230 is a constant, the current token is its sign. */
6231 int next_code;
6232
6233 intel_match_token (cur_token.code);
6234 next_code = cur_token.code;
6235 intel_putback_token ();
6236 if (next_code == T_CONST)
6237 break;
6238 }
6239
6240 /* e09 OFFSET e09 */
6241 if (cur_token.code == T_OFFSET)
6242 {
6243 if (!in_offset++)
6244 ++intel_parser.in_offset;
6245 }
6246
6247 /* e09 SHORT e09 */
6248 else if (cur_token.code == T_SHORT)
6249 intel_parser.op_modifier |= 1 << T_SHORT;
6250
6251 /* e09 + e09 */
6252 else if (cur_token.code == '+')
6253 strcat (intel_parser.disp, "+");
6254
6255 /* e09 - e09
6256 | ~ e09
6257 | NOT e09 */
6258 else if (cur_token.code == '-' || cur_token.code == '~')
6259 {
6260 char str[2];
64a0c779 6261
a724f0f4
JB		 6262 if (nregs < 0)
6263 nregs = ~nregs;
6264 str[0] = cur_token.code;
6265 str[1] = 0;
6266 strcat (intel_parser.disp, str);
6267 }
6268
6269 /* e09 e10 e09' */
6270 else
6271 break;
6272
6273 intel_match_token (cur_token.code);
64a0c779
DN		 6274 }
6275
a724f0f4 6276 for (;;)
9306ca4a 6277 {
a724f0f4
JB		 6278 if (!intel_e10 ())
6279 return 0;
9306ca4a 6280
a724f0f4
JB		 6281 /* e09' PTR e10 e09' */
6282 if (cur_token.code == T_PTR)
6283 {
6284 char suffix;
9306ca4a 6285
a724f0f4
JB		 6286 if (prev_token.code == T_BYTE)
6287 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 6288
a724f0f4
JB		 6289 else if (prev_token.code == T_WORD)
6290 {
6291 if (current_templates->start->name[0] == 'l'
6292 && current_templates->start->name[2] == 's'
6293 && current_templates->start->name[3] == 0)
6294 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6295 else if (intel_parser.got_a_float == 2) /* "fi..." */
6296 suffix = SHORT_MNEM_SUFFIX;
6297 else
6298 suffix = WORD_MNEM_SUFFIX;
6299 }
64a0c779 6300
a724f0f4
JB		 6301 else if (prev_token.code == T_DWORD)
6302 {
6303 if (current_templates->start->name[0] == 'l'
6304 && current_templates->start->name[2] == 's'
6305 && current_templates->start->name[3] == 0)
6306 suffix = WORD_MNEM_SUFFIX;
6307 else if (flag_code == CODE_16BIT
6308 && (current_templates->start->opcode_modifier
435acd52 6309 & (Jump | JumpDword)))
a724f0f4
JB		 6310 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6311 else if (intel_parser.got_a_float == 1) /* "f..." */
6312 suffix = SHORT_MNEM_SUFFIX;
6313 else
6314 suffix = LONG_MNEM_SUFFIX;
6315 }
9306ca4a 6316
a724f0f4
JB		 6317 else if (prev_token.code == T_FWORD)
6318 {
6319 if (current_templates->start->name[0] == 'l'
6320 && current_templates->start->name[2] == 's'
6321 && current_templates->start->name[3] == 0)
6322 suffix = LONG_MNEM_SUFFIX;
6323 else if (!intel_parser.got_a_float)
6324 {
6325 if (flag_code == CODE_16BIT)
6326 add_prefix (DATA_PREFIX_OPCODE);
6327 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6328 }
6329 else
6330 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6331 }
64a0c779 6332
a724f0f4
JB		 6333 else if (prev_token.code == T_QWORD)
6334 {
6335 if (intel_parser.got_a_float == 1) /* "f..." */
6336 suffix = LONG_MNEM_SUFFIX;
6337 else
6338 suffix = QWORD_MNEM_SUFFIX;
6339 }
64a0c779 6340
a724f0f4
JB		 6341 else if (prev_token.code == T_TBYTE)
6342 {
6343 if (intel_parser.got_a_float == 1)
6344 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6345 else
6346 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6347 }
9306ca4a 6348
a724f0f4 6349 else if (prev_token.code == T_XMMWORD)
9306ca4a 6350 {
a724f0f4
JB		 6351 /* XXX ignored for now, but accepted since gcc uses it */
6352 suffix = 0;
9306ca4a 6353 }
64a0c779 6354
f16b83df 6355 else
a724f0f4
JB		 6356 {
6357 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6358 return 0;
6359 }
6360
435acd52
JB		 6361 /* Operands for jump/call using 'ptr' notation denote absolute
6362 addresses. */
6363 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6364 i.types[this_operand] |= JumpAbsolute;
6365
a724f0f4
JB		 6366 if (current_templates->start->base_opcode == 0x8d /* lea */)
6367 ;
6368 else if (!i.suffix)
6369 i.suffix = suffix;
6370 else if (i.suffix != suffix)
6371 {
6372 as_bad (_("Conflicting operand modifiers"));
6373 return 0;
6374 }
64a0c779 6375
9306ca4a
JB		 6376 }
6377
a724f0f4
JB		 6378 /* e09' : e10 e09' */
6379 else if (cur_token.code == ':')
9306ca4a 6380 {
a724f0f4
JB		 6381 if (prev_token.code != T_REG)
6382 {
6383 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6384 segment/group identifier (which we don't have), using comma
6385 as the operand separator there is even less consistent, since
6386 there all branches only have a single operand. */
6387 if (this_operand != 0
6388 || intel_parser.in_offset
6389 || intel_parser.in_bracket
6390 || (!(current_templates->start->opcode_modifier
6391 & (Jump|JumpDword|JumpInterSegment))
6392 && !(current_templates->start->operand_types[0]
6393 & JumpAbsolute)))
6394 return intel_match_token (T_NIL);
6395 /* Remember the start of the 2nd operand and terminate 1st
6396 operand here.
6397 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6398 another expression), but it gets at least the simplest case
6399 (a plain number or symbol on the left side) right. */
6400 intel_parser.next_operand = intel_parser.op_string;
6401 *--intel_parser.op_string = '\0';
6402 return intel_match_token (':');
6403 }
9306ca4a 6404 }
64a0c779 6405
a724f0f4 6406 /* e09' Empty */
64a0c779 6407 else
a724f0f4 6408 break;
64a0c779 6409
a724f0f4
JB		 6410 intel_match_token (cur_token.code);
6411
6412 }
6413
6414 if (in_offset)
6415 {
6416 --intel_parser.in_offset;
6417 if (nregs < 0)
6418 nregs = ~nregs;
6419 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 6420 {
a724f0f4 6421 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 6422 return 0;
6423 }
a724f0f4
JB		 6424 intel_parser.op_modifier |= 1 << T_OFFSET;
6425 }
9306ca4a 6426
a724f0f4
JB		 6427 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6428 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
6429 return 1;
6430}
64a0c779 6431
a724f0f4
JB		 6432static int
6433intel_bracket_expr ()
6434{
6435 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
6436 const char *start = intel_parser.op_string;
6437 int len;
6438
6439 if (i.op[this_operand].regs)
6440 return intel_match_token (T_NIL);
6441
6442 intel_match_token ('[');
6443
6444 /* Mark as a memory operand only if it's not already known to be an
6445 offset expression. If it's an offset expression, we need to keep
6446 the brace in. */
6447 if (!intel_parser.in_offset)
6448 {
6449 ++intel_parser.in_bracket;
435acd52
JB		 6450
6451 /* Operands for jump/call inside brackets denote absolute addresses. */
6452 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6453 i.types[this_operand] |= JumpAbsolute;
6454
a724f0f4
JB		 6455 /* Unfortunately gas always diverged from MASM in a respect that can't
6456 be easily fixed without risking to break code sequences likely to be
6457 encountered (the testsuite even check for this): MASM doesn't consider
6458 an expression inside brackets unconditionally as a memory reference.
6459 When that is e.g. a constant, an offset expression, or the sum of the
6460 two, this is still taken as a constant load. gas, however, always
6461 treated these as memory references. As a compromise, we'll try to make
6462 offset expressions inside brackets work the MASM way (since that's
6463 less likely to be found in real world code), but make constants alone
6464 continue to work the traditional gas way. In either case, issue a
6465 warning. */
6466 intel_parser.op_modifier &= ~was_offset;
64a0c779 6467 }
a724f0f4
JB		 6468 else
6469 strcat (intel_parser.disp, "[");
6470
6471 /* Add a '+' to the displacement string if necessary. */
6472 if (*intel_parser.disp != '\0'
6473 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
6474 strcat (intel_parser.disp, "+");
64a0c779 6475
a724f0f4
JB		 6476 if (intel_expr ()
6477 && (len = intel_parser.op_string - start - 1,
6478 intel_match_token (']')))
64a0c779 6479 {
a724f0f4
JB		 6480 /* Preserve brackets when the operand is an offset expression. */
6481 if (intel_parser.in_offset)
6482 strcat (intel_parser.disp, "]");
6483 else
6484 {
6485 --intel_parser.in_bracket;
6486 if (i.base_reg || i.index_reg)
6487 intel_parser.is_mem = 1;
6488 if (!intel_parser.is_mem)
6489 {
6490 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
6491 /* Defer the warning until all of the operand was parsed. */
6492 intel_parser.is_mem = -1;
6493 else if (!quiet_warnings)
6494 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
6495 }
6496 }
6497 intel_parser.op_modifier |= was_offset;
64a0c779 6498
a724f0f4 6499 return 1;
64a0c779 6500 }
a724f0f4 6501 return 0;
64a0c779
DN		 6502}
6503
6504/* e10 e11 e10'
6505
6506 e10' [ expr ] e10'
b77a7acd 6507 | Empty */
64a0c779
DN		 6508static int
6509intel_e10 ()
6510{
a724f0f4
JB		 6511 if (!intel_e11 ())
6512 return 0;
64a0c779 6513
a724f0f4 6514 while (cur_token.code == '[')
64a0c779 6515 {
a724f0f4 6516 if (!intel_bracket_expr ())
21d6c4af 6517 return 0;
64a0c779
DN		 6518 }
6519
a724f0f4 6520 return 1;
64a0c779
DN		 6521}
6522
64a0c779 6523/* e11 ( expr )
b77a7acd 6524 | [ expr ]
64a0c779
DN		 6525 | BYTE
6526 | WORD
6527 | DWORD
9306ca4a 6528 | FWORD
64a0c779 6529 | QWORD
9306ca4a
JB		 6530 | TBYTE
6531 | OWORD
6532 | XMMWORD
4a1805b1 6533 | $
64a0c779
DN		 6534 | .
6535 | register
6536 | id
6537 | constant */
6538static int
6539intel_e11 ()
6540{
a724f0f4 6541 switch (cur_token.code)
64a0c779 6542 {
a724f0f4
JB		 6543 /* e11 ( expr ) */
6544 case '(':
64a0c779
DN		 6545 intel_match_token ('(');
6546 strcat (intel_parser.disp, "(");
6547
6548 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 6549 {
6550 strcat (intel_parser.disp, ")");
6551 return 1;
6552 }
a724f0f4 6553 return 0;
4a1805b1 6554
a724f0f4
JB		 6555 /* e11 [ expr ] */
6556 case '[':
a724f0f4 6557 return intel_bracket_expr ();
64a0c779 6558
a724f0f4
JB		 6559 /* e11 $
6560 | . */
6561 case '.':
64a0c779
DN		 6562 strcat (intel_parser.disp, cur_token.str);
6563 intel_match_token (cur_token.code);
21d6c4af
DN		 6564
6565 /* Mark as a memory operand only if it's not already known to be an
6566 offset expression. */
a724f0f4 6567 if (!intel_parser.in_offset)
21d6c4af 6568 intel_parser.is_mem = 1;
64a0c779
DN		 6569
6570 return 1;
64a0c779 6571
a724f0f4
JB		 6572 /* e11 register */
6573 case T_REG:
6574 {
6575 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 6576
a724f0f4 6577 intel_match_token (T_REG);
64a0c779 6578
a724f0f4
JB		 6579 /* Check for segment change. */
6580 if (cur_token.code == ':')
6581 {
6582 if (!(reg->reg_type & (SReg2 | SReg3)))
6583 {
6584 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
6585 return 0;
6586 }
6587 else if (i.seg[i.mem_operands])
6588 as_warn (_("Extra segment override ignored"));
6589 else
6590 {
6591 if (!intel_parser.in_offset)
6592 intel_parser.is_mem = 1;
6593 switch (reg->reg_num)
6594 {
6595 case 0:
6596 i.seg[i.mem_operands] = &es;
6597 break;
6598 case 1:
6599 i.seg[i.mem_operands] = &cs;
6600 break;
6601 case 2:
6602 i.seg[i.mem_operands] = &ss;
6603 break;
6604 case 3:
6605 i.seg[i.mem_operands] = &ds;
6606 break;
6607 case 4:
6608 i.seg[i.mem_operands] = &fs;
6609 break;
6610 case 5:
6611 i.seg[i.mem_operands] = &gs;
6612 break;
6613 }
6614 }
6615 }
64a0c779 6616
a724f0f4
JB		 6617 /* Not a segment register. Check for register scaling. */
6618 else if (cur_token.code == '*')
6619 {
6620 if (!intel_parser.in_bracket)
6621 {
6622 as_bad (_("Register scaling only allowed in memory operands"));
6623 return 0;
6624 }
64a0c779 6625
a724f0f4
JB		 6626 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
6627 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6628 else if (i.index_reg)
6629 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 6630
a724f0f4
JB		 6631 /* What follows must be a valid scale. */
6632 intel_match_token ('*');
6633 i.index_reg = reg;
6634 i.types[this_operand] |= BaseIndex;
64a0c779 6635
a724f0f4
JB		 6636 /* Set the scale after setting the register (otherwise,
6637 i386_scale will complain) */
6638 if (cur_token.code == '+' || cur_token.code == '-')
6639 {
6640 char *str, sign = cur_token.code;
6641 intel_match_token (cur_token.code);
6642 if (cur_token.code != T_CONST)
6643 {
6644 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6645 cur_token.str);
6646 return 0;
6647 }
6648 str = (char *) xmalloc (strlen (cur_token.str) + 2);
6649 strcpy (str + 1, cur_token.str);
6650 *str = sign;
6651 if (!i386_scale (str))
6652 return 0;
6653 free (str);
6654 }
6655 else if (!i386_scale (cur_token.str))
64a0c779 6656 return 0;
a724f0f4
JB		 6657 intel_match_token (cur_token.code);
6658 }
64a0c779 6659
a724f0f4
JB		 6660 /* No scaling. If this is a memory operand, the register is either a
6661 base register (first occurrence) or an index register (second
6662 occurrence). */
7b0441f6 6663 else if (intel_parser.in_bracket)
a724f0f4 6664 {
64a0c779 6665
a724f0f4
JB		 6666 if (!i.base_reg)
6667 i.base_reg = reg;
6668 else if (!i.index_reg)
6669 i.index_reg = reg;
6670 else
6671 {
6672 as_bad (_("Too many register references in memory operand"));
6673 return 0;
6674 }
64a0c779 6675
a724f0f4
JB		 6676 i.types[this_operand] |= BaseIndex;
6677 }
4a1805b1 6678
4d1bb795
JB		 6679 /* It's neither base nor index. */
6680 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4
JB		 6681 {
6682 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
6683 i.op[this_operand].regs = reg;
6684 i.reg_operands++;
6685 }
6686 else
6687 {
6688 as_bad (_("Invalid use of register"));
6689 return 0;
6690 }
64a0c779 6691
a724f0f4
JB		 6692 /* Since registers are not part of the displacement string (except
6693 when we're parsing offset operands), we may need to remove any
6694 preceding '+' from the displacement string. */
6695 if (*intel_parser.disp != '\0'
6696 && !intel_parser.in_offset)
6697 {
6698 char *s = intel_parser.disp;
6699 s += strlen (s) - 1;
6700 if (*s == '+')
6701 *s = '\0';
6702 }
4a1805b1 6703
a724f0f4
JB		 6704 return 1;
6705 }
6706
6707 /* e11 BYTE
6708 | WORD
6709 | DWORD
6710 | FWORD
6711 | QWORD
6712 | TBYTE
6713 | OWORD
6714 | XMMWORD */
6715 case T_BYTE:
6716 case T_WORD:
6717 case T_DWORD:
6718 case T_FWORD:
6719 case T_QWORD:
6720 case T_TBYTE:
6721 case T_XMMWORD:
6722 intel_match_token (cur_token.code);
64a0c779 6723
a724f0f4
JB		 6724 if (cur_token.code == T_PTR)
6725 return 1;
6726
6727 /* It must have been an identifier. */
6728 intel_putback_token ();
6729 cur_token.code = T_ID;
6730 /* FALLTHRU */
6731
6732 /* e11 id
6733 | constant */
6734 case T_ID:
6735 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 6736 {
6737 symbolS *symbolP;
6738
a724f0f4
JB		 6739 /* The identifier represents a memory reference only if it's not
6740 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 6741 symbolP = symbol_find(cur_token.str);
6742 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
6743 intel_parser.is_mem = 1;
6744 }
a724f0f4 6745 /* FALLTHRU */
64a0c779 6746
a724f0f4
JB		 6747 case T_CONST:
6748 case '-':
6749 case '+':
6750 {
6751 char *save_str, sign = 0;
64a0c779 6752
a724f0f4
JB		 6753 /* Allow constants that start with `+' or `-'. */
6754 if (cur_token.code == '-' || cur_token.code == '+')
6755 {
6756 sign = cur_token.code;
6757 intel_match_token (cur_token.code);
6758 if (cur_token.code != T_CONST)
6759 {
6760 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6761 cur_token.str);
6762 return 0;
6763 }
6764 }
64a0c779 6765
a724f0f4
JB		 6766 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
6767 strcpy (save_str + !!sign, cur_token.str);
6768 if (sign)
6769 *save_str = sign;
64a0c779 6770
a724f0f4
JB		 6771 /* Get the next token to check for register scaling. */
6772 intel_match_token (cur_token.code);
64a0c779 6773
a724f0f4
JB		 6774 /* Check if this constant is a scaling factor for an index register. */
6775 if (cur_token.code == '*')
6776 {
6777 if (intel_match_token ('*') && cur_token.code == T_REG)
6778 {
6779 const reg_entry *reg = cur_token.reg;
6780
6781 if (!intel_parser.in_bracket)
6782 {
6783 as_bad (_("Register scaling only allowed in memory operands"));
6784 return 0;
6785 }
6786
6787 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
6788 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6789 else if (i.index_reg)
6790 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
6791
6792 /* The constant is followed by `* reg', so it must be
6793 a valid scale. */
6794 i.index_reg = reg;
6795 i.types[this_operand] |= BaseIndex;
6796
6797 /* Set the scale after setting the register (otherwise,
6798 i386_scale will complain) */
6799 if (!i386_scale (save_str))
64a0c779 6800 return 0;
a724f0f4
JB		 6801 intel_match_token (T_REG);
6802
6803 /* Since registers are not part of the displacement
6804 string, we may need to remove any preceding '+' from
6805 the displacement string. */
6806 if (*intel_parser.disp != '\0')
6807 {
6808 char *s = intel_parser.disp;
6809 s += strlen (s) - 1;
6810 if (*s == '+')
6811 *s = '\0';
6812 }
6813
6814 free (save_str);
6815
6816 return 1;
6817 }
64a0c779 6818
a724f0f4
JB		 6819 /* The constant was not used for register scaling. Since we have
6820 already consumed the token following `*' we now need to put it
6821 back in the stream. */
64a0c779 6822 intel_putback_token ();
a724f0f4 6823 }
64a0c779 6824
a724f0f4
JB		 6825 /* Add the constant to the displacement string. */
6826 strcat (intel_parser.disp, save_str);
6827 free (save_str);
64a0c779 6828
a724f0f4
JB		 6829 return 1;
6830 }
64a0c779
DN		 6831 }
6832
64a0c779
DN		 6833 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6834 return 0;
6835}
6836
64a0c779
DN		 6837/* Match the given token against cur_token. If they match, read the next
6838 token from the operand string. */
6839static int
6840intel_match_token (code)
e5cb08ac 6841 int code;
64a0c779
DN		 6842{
6843 if (cur_token.code == code)
6844 {
6845 intel_get_token ();
6846 return 1;
6847 }
6848 else
6849 {
0477af35 6850 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 6851 return 0;
6852 }
6853}
6854
64a0c779
DN		 6855/* Read a new token from intel_parser.op_string and store it in cur_token. */
6856static void
6857intel_get_token ()
6858{
6859 char *end_op;
6860 const reg_entry *reg;
6861 struct intel_token new_token;
6862
6863 new_token.code = T_NIL;
6864 new_token.reg = NULL;
6865 new_token.str = NULL;
6866
4a1805b1 6867 /* Free the memory allocated to the previous token and move
64a0c779
DN		 6868 cur_token to prev_token. */
6869 if (prev_token.str)
6870 free (prev_token.str);
6871
6872 prev_token = cur_token;
6873
6874 /* Skip whitespace. */
6875 while (is_space_char (*intel_parser.op_string))
6876 intel_parser.op_string++;
6877
6878 /* Return an empty token if we find nothing else on the line. */
6879 if (*intel_parser.op_string == '\0')
6880 {
6881 cur_token = new_token;
6882 return;
6883 }
6884
6885 /* The new token cannot be larger than the remainder of the operand
6886 string. */
a724f0f4 6887 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 6888 new_token.str[0] = '\0';
6889
6890 if (strchr ("0123456789", *intel_parser.op_string))
6891 {
6892 char *p = new_token.str;
6893 char *q = intel_parser.op_string;
6894 new_token.code = T_CONST;
6895
6896 /* Allow any kind of identifier char to encompass floating point and
6897 hexadecimal numbers. */
6898 while (is_identifier_char (*q))
6899 *p++ = *q++;
6900 *p = '\0';
6901
6902 /* Recognize special symbol names [0-9][bf]. */
6903 if (strlen (intel_parser.op_string) == 2
4a1805b1 6904 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 6905 || intel_parser.op_string[1] == 'f'))
6906 new_token.code = T_ID;
6907 }
6908
4d1bb795 6909 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 6910 {
4d1bb795
JB		 6911 size_t len = end_op - intel_parser.op_string;
6912
64a0c779
DN		 6913 new_token.code = T_REG;
6914 new_token.reg = reg;
6915
4d1bb795
JB		 6916 memcpy (new_token.str, intel_parser.op_string, len);
6917 new_token.str[len] = '\0';
64a0c779
DN		 6918 }
6919
6920 else if (is_identifier_char (*intel_parser.op_string))
6921 {
6922 char *p = new_token.str;
6923 char *q = intel_parser.op_string;
6924
6925 /* A '.' or '$' followed by an identifier char is an identifier.
6926 Otherwise, it's operator '.' followed by an expression. */
6927 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6928 {
9306ca4a
JB		 6929 new_token.code = '.';
6930 new_token.str[0] = '.';
64a0c779
DN		 6931 new_token.str[1] = '\0';
6932 }
6933 else
6934 {
6935 while (is_identifier_char (*q) || *q == '@')
6936 *p++ = *q++;
6937 *p = '\0';
6938
9306ca4a
JB		 6939 if (strcasecmp (new_token.str, "NOT") == 0)
6940 new_token.code = '~';
6941
6942 else if (strcasecmp (new_token.str, "MOD") == 0)
6943 new_token.code = '%';
6944
6945 else if (strcasecmp (new_token.str, "AND") == 0)
6946 new_token.code = '&';
6947
6948 else if (strcasecmp (new_token.str, "OR") == 0)
6949 new_token.code = '|';
6950
6951 else if (strcasecmp (new_token.str, "XOR") == 0)
6952 new_token.code = '^';
6953
6954 else if (strcasecmp (new_token.str, "SHL") == 0)
6955 new_token.code = T_SHL;
6956
6957 else if (strcasecmp (new_token.str, "SHR") == 0)
6958 new_token.code = T_SHR;
6959
6960 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 6961 new_token.code = T_BYTE;
6962
6963 else if (strcasecmp (new_token.str, "WORD") == 0)
6964 new_token.code = T_WORD;
6965
6966 else if (strcasecmp (new_token.str, "DWORD") == 0)
6967 new_token.code = T_DWORD;
6968
9306ca4a
JB		 6969 else if (strcasecmp (new_token.str, "FWORD") == 0)
6970 new_token.code = T_FWORD;
6971
64a0c779
DN		 6972 else if (strcasecmp (new_token.str, "QWORD") == 0)
6973 new_token.code = T_QWORD;
6974
9306ca4a
JB		 6975 else if (strcasecmp (new_token.str, "TBYTE") == 0
6976 /* XXX remove (gcc still uses it) */
6977 || strcasecmp (new_token.str, "XWORD") == 0)
6978 new_token.code = T_TBYTE;
6979
6980 else if (strcasecmp (new_token.str, "XMMWORD") == 0
6981 || strcasecmp (new_token.str, "OWORD") == 0)
6982 new_token.code = T_XMMWORD;
64a0c779
DN		 6983
6984 else if (strcasecmp (new_token.str, "PTR") == 0)
6985 new_token.code = T_PTR;
6986
6987 else if (strcasecmp (new_token.str, "SHORT") == 0)
6988 new_token.code = T_SHORT;
6989
6990 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6991 {
6992 new_token.code = T_OFFSET;
6993
6994 /* ??? This is not mentioned in the MASM grammar but gcc
6995 makes use of it with -mintel-syntax. OFFSET may be
6996 followed by FLAT: */
6997 if (strncasecmp (q, " FLAT:", 6) == 0)
6998 strcat (new_token.str, " FLAT:");
6999 }
7000
7001 /* ??? This is not mentioned in the MASM grammar. */
7002 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 7003 {
7004 new_token.code = T_OFFSET;
7005 if (*q == ':')
7006 strcat (new_token.str, ":");
7007 else
7008 as_bad (_("`:' expected"));
7009 }
64a0c779
DN		 7010
7011 else
7012 new_token.code = T_ID;
7013 }
7014 }
7015
9306ca4a
JB		 7016 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7017 {
7018 new_token.code = *intel_parser.op_string;
7019 new_token.str[0] = *intel_parser.op_string;
7020 new_token.str[1] = '\0';
7021 }
7022
7023 else if (strchr ("<>", *intel_parser.op_string)
7024 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7025 {
7026 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7027 new_token.str[0] = *intel_parser.op_string;
7028 new_token.str[1] = *intel_parser.op_string;
7029 new_token.str[2] = '\0';
7030 }
7031
64a0c779 7032 else
0477af35 7033 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 7034
7035 intel_parser.op_string += strlen (new_token.str);
7036 cur_token = new_token;
7037}
7038
64a0c779
DN		 7039/* Put cur_token back into the token stream and make cur_token point to
7040 prev_token. */
7041static void
7042intel_putback_token ()
7043{
a724f0f4
JB		 7044 if (cur_token.code != T_NIL)
7045 {
7046 intel_parser.op_string -= strlen (cur_token.str);
7047 free (cur_token.str);
7048 }
64a0c779 7049 cur_token = prev_token;
4a1805b1 7050
64a0c779
DN		 7051 /* Forget prev_token. */
7052 prev_token.code = T_NIL;
7053 prev_token.reg = NULL;
7054 prev_token.str = NULL;
7055}
54cfded0 7056
a4447b93 7057int
54cfded0
AM		 7058tc_x86_regname_to_dw2regnum (const char *regname)
7059{
7060 unsigned int regnum;
7061 unsigned int regnames_count;
089dfecd 7062 static const char *const regnames_32[] =
54cfded0 7063 {
a4447b93
RH		 7064 "eax", "ecx", "edx", "ebx",
7065 "esp", "ebp", "esi", "edi",
089dfecd
JB		 7066 "eip", "eflags", NULL,
7067 "st0", "st1", "st2", "st3",
7068 "st4", "st5", "st6", "st7",
7069 NULL, NULL,
7070 "xmm0", "xmm1", "xmm2", "xmm3",
7071 "xmm4", "xmm5", "xmm6", "xmm7",
7072 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7073 "mm4", "mm5", "mm6", "mm7",
7074 "fcw", "fsw", "mxcsr",
7075 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7076 "tr", "ldtr"
54cfded0 7077 };
089dfecd 7078 static const char *const regnames_64[] =
54cfded0 7079 {
089dfecd
JB		 7080 "rax", "rdx", "rcx", "rbx",
7081 "rsi", "rdi", "rbp", "rsp",
7082 "r8", "r9", "r10", "r11",
54cfded0 7083 "r12", "r13", "r14", "r15",
089dfecd
JB		 7084 "rip",
7085 "xmm0", "xmm1", "xmm2", "xmm3",
7086 "xmm4", "xmm5", "xmm6", "xmm7",
7087 "xmm8", "xmm9", "xmm10", "xmm11",
7088 "xmm12", "xmm13", "xmm14", "xmm15",
7089 "st0", "st1", "st2", "st3",
7090 "st4", "st5", "st6", "st7",
7091 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7092 "mm4", "mm5", "mm6", "mm7",
7093 "rflags",
7094 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7095 "fs.base", "gs.base", NULL, NULL,
7096 "tr", "ldtr",
7097 "mxcsr", "fcw", "fsw"
54cfded0 7098 };
089dfecd 7099 const char *const *regnames;
54cfded0
AM		 7100
7101 if (flag_code == CODE_64BIT)
7102 {
7103 regnames = regnames_64;
0cea6190 7104 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 7105 }
7106 else
7107 {
7108 regnames = regnames_32;
0cea6190 7109 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 7110 }
7111
7112 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 7113 if (regnames[regnum] != NULL
7114 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 7115 return regnum;
7116
54cfded0
AM		 7117 return -1;
7118}
7119
7120void
7121tc_x86_frame_initial_instructions (void)
7122{
a4447b93
RH		 7123 static unsigned int sp_regno;
7124
7125 if (!sp_regno)
7126 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7127 ? "rsp" : "esp");
7128
7129 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7130 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 7131}
d2b2c203
DJ		 7132
7133int
7134i386_elf_section_type (const char *str, size_t len)
7135{
7136 if (flag_code == CODE_64BIT
7137 && len == sizeof ("unwind") - 1
7138 && strncmp (str, "unwind", 6) == 0)
7139 return SHT_X86_64_UNWIND;
7140
7141 return -1;
7142}
bb41ade5
AM		 7143
7144#ifdef TE_PE
7145void
7146tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7147{
7148 expressionS expr;
7149
7150 expr.X_op = O_secrel;
7151 expr.X_add_symbol = symbol;
7152 expr.X_add_number = 0;
7153 emit_expr (&expr, size);
7154}
7155#endif
3b22753a
L		 7156
7157#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7158/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7159
7160int
7161x86_64_section_letter (int letter, char **ptr_msg)
7162{
7163 if (flag_code == CODE_64BIT)
7164 {
7165 if (letter == 'l')
7166 return SHF_X86_64_LARGE;
7167
7168 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7169 }
7170 else
7171 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
7172 return -1;
7173}
7174
7175int
7176x86_64_section_word (char *str, size_t len)
7177{
7178 if (len == 5 && flag_code == CODE_64BIT && strncmp (str, "large", 5) == 0)
7179 return SHF_X86_64_LARGE;
7180
7181 return -1;
7182}
7183
7184static void
7185handle_large_common (int small ATTRIBUTE_UNUSED)
7186{
7187 if (flag_code != CODE_64BIT)
7188 {
7189 s_comm_internal (0, elf_common_parse);
7190 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7191 }
7192 else
7193 {
7194 static segT lbss_section;
7195 asection *saved_com_section_ptr = elf_com_section_ptr;
7196 asection *saved_bss_section = bss_section;
7197
7198 if (lbss_section == NULL)
7199 {
7200 flagword applicable;
7201 segT seg = now_seg;
7202 subsegT subseg = now_subseg;
7203
7204 /* The .lbss section is for local .largecomm symbols. */
7205 lbss_section = subseg_new (".lbss", 0);
7206 applicable = bfd_applicable_section_flags (stdoutput);
7207 bfd_set_section_flags (stdoutput, lbss_section,
7208 applicable & SEC_ALLOC);
7209 seg_info (lbss_section)->bss = 1;
7210
7211 subseg_set (seg, subseg);
7212 }
7213
7214 elf_com_section_ptr = &_bfd_elf_large_com_section;
7215 bss_section = lbss_section;
7216
7217 s_comm_internal (0, elf_common_parse);
7218
7219 elf_com_section_ptr = saved_com_section_ptr;
7220 bss_section = saved_bss_section;
7221 }
7222}
7223#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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