Commit | Line | Data |
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252b5132 | 1 | /* i386.c -- Assemble code for the Intel 80386 |
f7e42eb4 NC |
2 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
3 | 2000, 2001 | |
47926f60 | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | |
6 | This file is part of GAS, the GNU Assembler. | |
7 | ||
8 | GAS is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GAS is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GAS; see the file COPYING. If not, write to the Free | |
20 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
21 | 02111-1307, USA. */ | |
22 | ||
47926f60 KH |
23 | /* Intel 80386 machine specific gas. |
24 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 25 | x86_64 support by Jan Hubicka (jh@suse.cz) |
47926f60 KH |
26 | Bugs & suggestions are completely welcome. This is free software. |
27 | Please help us make it better. */ | |
252b5132 | 28 | |
252b5132 | 29 | #include "as.h" |
3882b010 | 30 | #include "safe-ctype.h" |
252b5132 | 31 | #include "subsegs.h" |
316e2c05 | 32 | #include "dwarf2dbg.h" |
252b5132 RH |
33 | #include "opcode/i386.h" |
34 | ||
252b5132 RH |
35 | #ifndef REGISTER_WARNINGS |
36 | #define REGISTER_WARNINGS 1 | |
37 | #endif | |
38 | ||
c3332e24 | 39 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 40 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
41 | #endif |
42 | ||
252b5132 RH |
43 | #ifndef SCALE1_WHEN_NO_INDEX |
44 | /* Specifying a scale factor besides 1 when there is no index is | |
45 | futile. eg. `mov (%ebx,2),%al' does exactly the same as | |
46 | `mov (%ebx),%al'. To slavishly follow what the programmer | |
47 | specified, set SCALE1_WHEN_NO_INDEX to 0. */ | |
48 | #define SCALE1_WHEN_NO_INDEX 1 | |
49 | #endif | |
50 | ||
51 | #define true 1 | |
52 | #define false 0 | |
53 | ||
54 | static unsigned int mode_from_disp_size PARAMS ((unsigned int)); | |
847f7ad4 AM |
55 | static int fits_in_signed_byte PARAMS ((offsetT)); |
56 | static int fits_in_unsigned_byte PARAMS ((offsetT)); | |
57 | static int fits_in_unsigned_word PARAMS ((offsetT)); | |
58 | static int fits_in_signed_word PARAMS ((offsetT)); | |
3e73aa7c JH |
59 | static int fits_in_unsigned_long PARAMS ((offsetT)); |
60 | static int fits_in_signed_long PARAMS ((offsetT)); | |
847f7ad4 AM |
61 | static int smallest_imm_type PARAMS ((offsetT)); |
62 | static offsetT offset_in_range PARAMS ((offsetT, int)); | |
252b5132 | 63 | static int add_prefix PARAMS ((unsigned int)); |
3e73aa7c | 64 | static void set_code_flag PARAMS ((int)); |
47926f60 | 65 | static void set_16bit_gcc_code_flag PARAMS ((int)); |
252b5132 | 66 | static void set_intel_syntax PARAMS ((int)); |
e413e4e9 | 67 | static void set_cpu_arch PARAMS ((int)); |
252b5132 RH |
68 | |
69 | #ifdef BFD_ASSEMBLER | |
70 | static bfd_reloc_code_real_type reloc | |
3e73aa7c | 71 | PARAMS ((int, int, int, bfd_reloc_code_real_type)); |
f3c180ae AM |
72 | #define RELOC_ENUM enum bfd_reloc_code_real |
73 | #else | |
74 | #define RELOC_ENUM int | |
252b5132 RH |
75 | #endif |
76 | ||
3e73aa7c JH |
77 | #ifndef DEFAULT_ARCH |
78 | #define DEFAULT_ARCH "i386" | |
79 | #endif | |
a847613f | 80 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 81 | |
252b5132 | 82 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 83 | i386_insn. */ |
252b5132 | 84 | |
520dc8e8 AM |
85 | union i386_op |
86 | { | |
87 | expressionS *disps; | |
88 | expressionS *imms; | |
89 | const reg_entry *regs; | |
90 | }; | |
91 | ||
252b5132 RH |
92 | struct _i386_insn |
93 | { | |
47926f60 | 94 | /* TM holds the template for the insn were currently assembling. */ |
252b5132 RH |
95 | template tm; |
96 | ||
97 | /* SUFFIX holds the instruction mnemonic suffix if given. | |
98 | (e.g. 'l' for 'movl') */ | |
99 | char suffix; | |
100 | ||
47926f60 | 101 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
102 | unsigned int operands; |
103 | ||
104 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
105 | of given register, displacement, memory operands and immediate | |
47926f60 | 106 | operands. */ |
252b5132 RH |
107 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
108 | ||
109 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 110 | use OP[i] for the corresponding operand. */ |
252b5132 RH |
111 | unsigned int types[MAX_OPERANDS]; |
112 | ||
520dc8e8 AM |
113 | /* Displacement expression, immediate expression, or register for each |
114 | operand. */ | |
115 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 116 | |
3e73aa7c JH |
117 | /* Flags for operands. */ |
118 | unsigned int flags[MAX_OPERANDS]; | |
119 | #define Operand_PCrel 1 | |
120 | ||
252b5132 | 121 | /* Relocation type for operand */ |
f3c180ae | 122 | RELOC_ENUM reloc[MAX_OPERANDS]; |
252b5132 | 123 | |
252b5132 RH |
124 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
125 | the base index byte below. */ | |
126 | const reg_entry *base_reg; | |
127 | const reg_entry *index_reg; | |
128 | unsigned int log2_scale_factor; | |
129 | ||
130 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 131 | explicit segment overrides are given. */ |
ce8a8b2f | 132 | const seg_entry *seg[2]; |
252b5132 RH |
133 | |
134 | /* PREFIX holds all the given prefix opcodes (usually null). | |
135 | PREFIXES is the number of prefix opcodes. */ | |
136 | unsigned int prefixes; | |
137 | unsigned char prefix[MAX_PREFIXES]; | |
138 | ||
139 | /* RM and SIB are the modrm byte and the sib byte where the | |
140 | addressing modes of this insn are encoded. */ | |
141 | ||
142 | modrm_byte rm; | |
3e73aa7c | 143 | rex_byte rex; |
252b5132 RH |
144 | sib_byte sib; |
145 | }; | |
146 | ||
147 | typedef struct _i386_insn i386_insn; | |
148 | ||
149 | /* List of chars besides those in app.c:symbol_chars that can start an | |
150 | operand. Used to prevent the scrubber eating vital white-space. */ | |
151 | #ifdef LEX_AT | |
152 | const char extra_symbol_chars[] = "*%-(@"; | |
153 | #else | |
154 | const char extra_symbol_chars[] = "*%-("; | |
155 | #endif | |
156 | ||
157 | /* This array holds the chars that always start a comment. If the | |
ce8a8b2f | 158 | pre-processor is disabled, these aren't very useful. */ |
5bae9b28 | 159 | #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD) && !defined(TE_NetBSD)) |
252b5132 RH |
160 | /* Putting '/' here makes it impossible to use the divide operator. |
161 | However, we need it for compatibility with SVR4 systems. */ | |
162 | const char comment_chars[] = "#/"; | |
163 | #define PREFIX_SEPARATOR '\\' | |
164 | #else | |
165 | const char comment_chars[] = "#"; | |
166 | #define PREFIX_SEPARATOR '/' | |
167 | #endif | |
168 | ||
169 | /* This array holds the chars that only start a comment at the beginning of | |
170 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
171 | .line and .file directives will appear in the pre-processed output. |
172 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 173 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
174 | #NO_APP at the beginning of its output. |
175 | Also note that comments started like this one will always work if | |
252b5132 | 176 | '/' isn't otherwise defined. */ |
5bae9b28 | 177 | #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD) && !defined(TE_NetBSD)) |
252b5132 RH |
178 | const char line_comment_chars[] = ""; |
179 | #else | |
180 | const char line_comment_chars[] = "/"; | |
181 | #endif | |
182 | ||
63a0b638 | 183 | const char line_separator_chars[] = ";"; |
252b5132 | 184 | |
ce8a8b2f AM |
185 | /* Chars that can be used to separate mant from exp in floating point |
186 | nums. */ | |
252b5132 RH |
187 | const char EXP_CHARS[] = "eE"; |
188 | ||
ce8a8b2f AM |
189 | /* Chars that mean this number is a floating point constant |
190 | As in 0f12.456 | |
191 | or 0d1.2345e12. */ | |
252b5132 RH |
192 | const char FLT_CHARS[] = "fFdDxX"; |
193 | ||
ce8a8b2f | 194 | /* Tables for lexical analysis. */ |
252b5132 RH |
195 | static char mnemonic_chars[256]; |
196 | static char register_chars[256]; | |
197 | static char operand_chars[256]; | |
198 | static char identifier_chars[256]; | |
199 | static char digit_chars[256]; | |
200 | ||
ce8a8b2f | 201 | /* Lexical macros. */ |
252b5132 RH |
202 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
203 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
204 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
205 | #define is_space_char(x) ((x) == ' ') | |
206 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
207 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
208 | ||
ce8a8b2f | 209 | /* All non-digit non-letter charcters that may occur in an operand. */ |
252b5132 RH |
210 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
211 | ||
212 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
213 | effect this we maintain a stack of saved characters that we've smashed | |
214 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 215 | assembler instruction). */ |
252b5132 | 216 | static char save_stack[32]; |
ce8a8b2f | 217 | static char *save_stack_p; |
252b5132 RH |
218 | #define END_STRING_AND_SAVE(s) \ |
219 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
220 | #define RESTORE_END_STRING(s) \ | |
221 | do { *(s) = *--save_stack_p; } while (0) | |
222 | ||
47926f60 | 223 | /* The instruction we're assembling. */ |
252b5132 RH |
224 | static i386_insn i; |
225 | ||
226 | /* Possible templates for current insn. */ | |
227 | static const templates *current_templates; | |
228 | ||
47926f60 | 229 | /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */ |
252b5132 RH |
230 | static expressionS disp_expressions[2], im_expressions[2]; |
231 | ||
47926f60 KH |
232 | /* Current operand we are working on. */ |
233 | static int this_operand; | |
252b5132 | 234 | |
3e73aa7c JH |
235 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
236 | these. */ | |
237 | ||
238 | enum flag_code { | |
239 | CODE_32BIT, | |
240 | CODE_16BIT, | |
241 | CODE_64BIT }; | |
f3c180ae | 242 | #define NUM_FLAG_CODE ((int) CODE_64BIT + 1) |
3e73aa7c JH |
243 | |
244 | static enum flag_code flag_code; | |
245 | static int use_rela_relocations = 0; | |
246 | ||
247 | /* The names used to print error messages. */ | |
b77a7acd | 248 | static const char *flag_code_names[] = |
3e73aa7c JH |
249 | { |
250 | "32", | |
251 | "16", | |
252 | "64" | |
253 | }; | |
252b5132 | 254 | |
47926f60 KH |
255 | /* 1 for intel syntax, |
256 | 0 if att syntax. */ | |
257 | static int intel_syntax = 0; | |
252b5132 | 258 | |
47926f60 KH |
259 | /* 1 if register prefix % not required. */ |
260 | static int allow_naked_reg = 0; | |
252b5132 | 261 | |
47926f60 KH |
262 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
263 | leave, push, and pop instructions so that gcc has the same stack | |
264 | frame as in 32 bit mode. */ | |
265 | static char stackop_size = '\0'; | |
eecb386c | 266 | |
47926f60 KH |
267 | /* Non-zero to quieten some warnings. */ |
268 | static int quiet_warnings = 0; | |
a38cf1db | 269 | |
47926f60 KH |
270 | /* CPU name. */ |
271 | static const char *cpu_arch_name = NULL; | |
a38cf1db | 272 | |
47926f60 | 273 | /* CPU feature flags. */ |
3e73aa7c | 274 | static unsigned int cpu_arch_flags = CpuUnknownFlags|CpuNo64; |
a38cf1db | 275 | |
fddf5b5b AM |
276 | /* If set, conditional jumps are not automatically promoted to handle |
277 | larger than a byte offset. */ | |
278 | static unsigned int no_cond_jump_promotion = 0; | |
279 | ||
252b5132 | 280 | /* Interface to relax_segment. |
fddf5b5b AM |
281 | There are 3 major relax states for 386 jump insns because the |
282 | different types of jumps add different sizes to frags when we're | |
283 | figuring out what sort of jump to choose to reach a given label. */ | |
252b5132 | 284 | |
47926f60 | 285 | /* Types. */ |
93c2a809 AM |
286 | #define UNCOND_JUMP 0 |
287 | #define COND_JUMP 1 | |
288 | #define COND_JUMP86 2 | |
fddf5b5b | 289 | |
47926f60 | 290 | /* Sizes. */ |
252b5132 RH |
291 | #define CODE16 1 |
292 | #define SMALL 0 | |
293 | #define SMALL16 (SMALL|CODE16) | |
294 | #define BIG 2 | |
295 | #define BIG16 (BIG|CODE16) | |
296 | ||
297 | #ifndef INLINE | |
298 | #ifdef __GNUC__ | |
299 | #define INLINE __inline__ | |
300 | #else | |
301 | #define INLINE | |
302 | #endif | |
303 | #endif | |
304 | ||
fddf5b5b AM |
305 | #define ENCODE_RELAX_STATE(type, size) \ |
306 | ((relax_substateT) (((type) << 2) | (size))) | |
307 | #define TYPE_FROM_RELAX_STATE(s) \ | |
308 | ((s) >> 2) | |
309 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
310 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
311 | |
312 | /* This table is used by relax_frag to promote short jumps to long | |
313 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
314 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
315 | don't allow a short jump in a 32 bit code segment to be promoted to | |
316 | a 16 bit offset jump because it's slower (requires data size | |
317 | prefix), and doesn't work, unless the destination is in the bottom | |
318 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
319 | ||
320 | const relax_typeS md_relax_table[] = | |
321 | { | |
24eab124 AM |
322 | /* The fields are: |
323 | 1) most positive reach of this state, | |
324 | 2) most negative reach of this state, | |
93c2a809 | 325 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 326 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 327 | |
fddf5b5b | 328 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
329 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
330 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
331 | /* dword jmp adds 4 bytes to frag: | |
332 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 333 | {0, 0, 4, 0}, |
93c2a809 AM |
334 | /* word jmp adds 2 byte2 to frag: |
335 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
336 | {0, 0, 2, 0}, |
337 | ||
93c2a809 AM |
338 | /* COND_JUMP states. */ |
339 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
340 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
341 | /* dword conditionals adds 5 bytes to frag: | |
342 | 1 extra opcode byte, 4 displacement bytes. */ | |
343 | {0, 0, 5, 0}, | |
fddf5b5b | 344 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
345 | 1 extra opcode byte, 2 displacement bytes. */ |
346 | {0, 0, 3, 0}, | |
347 | ||
348 | /* COND_JUMP86 states. */ | |
349 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
350 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
351 | /* dword conditionals adds 5 bytes to frag: | |
352 | 1 extra opcode byte, 4 displacement bytes. */ | |
353 | {0, 0, 5, 0}, | |
354 | /* word conditionals add 4 bytes to frag: | |
355 | 1 displacement byte and a 3 byte long branch insn. */ | |
356 | {0, 0, 4, 0} | |
252b5132 RH |
357 | }; |
358 | ||
e413e4e9 AM |
359 | static const arch_entry cpu_arch[] = { |
360 | {"i8086", Cpu086 }, | |
361 | {"i186", Cpu086|Cpu186 }, | |
362 | {"i286", Cpu086|Cpu186|Cpu286 }, | |
363 | {"i386", Cpu086|Cpu186|Cpu286|Cpu386 }, | |
364 | {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 }, | |
365 | {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX }, | |
366 | {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE }, | |
367 | {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX }, | |
368 | {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE }, | |
a167610d | 369 | {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 }, |
3e73aa7c JH |
370 | {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow }, |
371 | {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow }, | |
a167610d | 372 | {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 }, |
e413e4e9 AM |
373 | {NULL, 0 } |
374 | }; | |
375 | ||
252b5132 RH |
376 | void |
377 | i386_align_code (fragP, count) | |
378 | fragS *fragP; | |
379 | int count; | |
380 | { | |
ce8a8b2f AM |
381 | /* Various efficient no-op patterns for aligning code labels. |
382 | Note: Don't try to assemble the instructions in the comments. | |
383 | 0L and 0w are not legal. */ | |
252b5132 RH |
384 | static const char f32_1[] = |
385 | {0x90}; /* nop */ | |
386 | static const char f32_2[] = | |
387 | {0x89,0xf6}; /* movl %esi,%esi */ | |
388 | static const char f32_3[] = | |
389 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
390 | static const char f32_4[] = | |
391 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
392 | static const char f32_5[] = | |
393 | {0x90, /* nop */ | |
394 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
395 | static const char f32_6[] = | |
396 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
397 | static const char f32_7[] = | |
398 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
399 | static const char f32_8[] = | |
400 | {0x90, /* nop */ | |
401 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
402 | static const char f32_9[] = | |
403 | {0x89,0xf6, /* movl %esi,%esi */ | |
404 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
405 | static const char f32_10[] = | |
406 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ | |
407 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
408 | static const char f32_11[] = | |
409 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ | |
410 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
411 | static const char f32_12[] = | |
412 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
413 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
414 | static const char f32_13[] = | |
415 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
416 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
417 | static const char f32_14[] = | |
418 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ | |
419 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
420 | static const char f32_15[] = | |
421 | {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */ | |
422 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
c3332e24 AM |
423 | static const char f16_3[] = |
424 | {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ | |
252b5132 RH |
425 | static const char f16_4[] = |
426 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
427 | static const char f16_5[] = | |
428 | {0x90, /* nop */ | |
429 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
430 | static const char f16_6[] = | |
431 | {0x89,0xf6, /* mov %si,%si */ | |
432 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
433 | static const char f16_7[] = | |
434 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ | |
435 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
436 | static const char f16_8[] = | |
437 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ | |
438 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
439 | static const char *const f32_patt[] = { | |
440 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, | |
441 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15 | |
442 | }; | |
443 | static const char *const f16_patt[] = { | |
c3332e24 | 444 | f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8, |
252b5132 RH |
445 | f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15 |
446 | }; | |
447 | ||
3e73aa7c JH |
448 | /* ??? We can't use these fillers for x86_64, since they often kills the |
449 | upper halves. Solve later. */ | |
450 | if (flag_code == CODE_64BIT) | |
451 | count = 1; | |
452 | ||
252b5132 RH |
453 | if (count > 0 && count <= 15) |
454 | { | |
3e73aa7c | 455 | if (flag_code == CODE_16BIT) |
252b5132 | 456 | { |
47926f60 KH |
457 | memcpy (fragP->fr_literal + fragP->fr_fix, |
458 | f16_patt[count - 1], count); | |
459 | if (count > 8) | |
460 | /* Adjust jump offset. */ | |
252b5132 RH |
461 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; |
462 | } | |
463 | else | |
47926f60 KH |
464 | memcpy (fragP->fr_literal + fragP->fr_fix, |
465 | f32_patt[count - 1], count); | |
252b5132 RH |
466 | fragP->fr_var = count; |
467 | } | |
468 | } | |
469 | ||
470 | static char *output_invalid PARAMS ((int c)); | |
471 | static int i386_operand PARAMS ((char *operand_string)); | |
472 | static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float)); | |
473 | static const reg_entry *parse_register PARAMS ((char *reg_string, | |
474 | char **end_op)); | |
475 | ||
476 | #ifndef I386COFF | |
477 | static void s_bss PARAMS ((int)); | |
478 | #endif | |
479 | ||
ce8a8b2f | 480 | symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
252b5132 RH |
481 | |
482 | static INLINE unsigned int | |
483 | mode_from_disp_size (t) | |
484 | unsigned int t; | |
485 | { | |
3e73aa7c | 486 | return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0; |
252b5132 RH |
487 | } |
488 | ||
489 | static INLINE int | |
490 | fits_in_signed_byte (num) | |
847f7ad4 | 491 | offsetT num; |
252b5132 RH |
492 | { |
493 | return (num >= -128) && (num <= 127); | |
47926f60 | 494 | } |
252b5132 RH |
495 | |
496 | static INLINE int | |
497 | fits_in_unsigned_byte (num) | |
847f7ad4 | 498 | offsetT num; |
252b5132 RH |
499 | { |
500 | return (num & 0xff) == num; | |
47926f60 | 501 | } |
252b5132 RH |
502 | |
503 | static INLINE int | |
504 | fits_in_unsigned_word (num) | |
847f7ad4 | 505 | offsetT num; |
252b5132 RH |
506 | { |
507 | return (num & 0xffff) == num; | |
47926f60 | 508 | } |
252b5132 RH |
509 | |
510 | static INLINE int | |
511 | fits_in_signed_word (num) | |
847f7ad4 | 512 | offsetT num; |
252b5132 RH |
513 | { |
514 | return (-32768 <= num) && (num <= 32767); | |
47926f60 | 515 | } |
3e73aa7c JH |
516 | static INLINE int |
517 | fits_in_signed_long (num) | |
518 | offsetT num ATTRIBUTE_UNUSED; | |
519 | { | |
520 | #ifndef BFD64 | |
521 | return 1; | |
522 | #else | |
523 | return (!(((offsetT) -1 << 31) & num) | |
524 | || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31)); | |
525 | #endif | |
526 | } /* fits_in_signed_long() */ | |
527 | static INLINE int | |
528 | fits_in_unsigned_long (num) | |
529 | offsetT num ATTRIBUTE_UNUSED; | |
530 | { | |
531 | #ifndef BFD64 | |
532 | return 1; | |
533 | #else | |
534 | return (num & (((offsetT) 2 << 31) - 1)) == num; | |
535 | #endif | |
536 | } /* fits_in_unsigned_long() */ | |
252b5132 RH |
537 | |
538 | static int | |
539 | smallest_imm_type (num) | |
847f7ad4 | 540 | offsetT num; |
252b5132 | 541 | { |
a847613f | 542 | if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64)) |
e413e4e9 AM |
543 | { |
544 | /* This code is disabled on the 486 because all the Imm1 forms | |
545 | in the opcode table are slower on the i486. They're the | |
546 | versions with the implicitly specified single-position | |
547 | displacement, which has another syntax if you really want to | |
548 | use that form. */ | |
549 | if (num == 1) | |
3e73aa7c | 550 | return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64; |
e413e4e9 | 551 | } |
252b5132 | 552 | return (fits_in_signed_byte (num) |
3e73aa7c | 553 | ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64) |
252b5132 | 554 | : fits_in_unsigned_byte (num) |
3e73aa7c | 555 | ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64) |
252b5132 | 556 | : (fits_in_signed_word (num) || fits_in_unsigned_word (num)) |
3e73aa7c JH |
557 | ? (Imm16 | Imm32 | Imm32S | Imm64) |
558 | : fits_in_signed_long (num) | |
559 | ? (Imm32 | Imm32S | Imm64) | |
560 | : fits_in_unsigned_long (num) | |
561 | ? (Imm32 | Imm64) | |
562 | : Imm64); | |
47926f60 | 563 | } |
252b5132 | 564 | |
847f7ad4 AM |
565 | static offsetT |
566 | offset_in_range (val, size) | |
567 | offsetT val; | |
568 | int size; | |
569 | { | |
508866be | 570 | addressT mask; |
ba2adb93 | 571 | |
847f7ad4 AM |
572 | switch (size) |
573 | { | |
508866be L |
574 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
575 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 576 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
577 | #ifdef BFD64 |
578 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
579 | #endif | |
47926f60 | 580 | default: abort (); |
847f7ad4 AM |
581 | } |
582 | ||
ba2adb93 | 583 | /* If BFD64, sign extend val. */ |
3e73aa7c JH |
584 | if (!use_rela_relocations) |
585 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) | |
586 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
ba2adb93 | 587 | |
47926f60 | 588 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
589 | { |
590 | char buf1[40], buf2[40]; | |
591 | ||
592 | sprint_value (buf1, val); | |
593 | sprint_value (buf2, val & mask); | |
594 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
595 | } | |
596 | return val & mask; | |
597 | } | |
598 | ||
252b5132 RH |
599 | /* Returns 0 if attempting to add a prefix where one from the same |
600 | class already exists, 1 if non rep/repne added, 2 if rep/repne | |
601 | added. */ | |
602 | static int | |
603 | add_prefix (prefix) | |
604 | unsigned int prefix; | |
605 | { | |
606 | int ret = 1; | |
607 | int q; | |
608 | ||
3e73aa7c JH |
609 | if (prefix >= 0x40 && prefix < 0x50 && flag_code == CODE_64BIT) |
610 | q = REX_PREFIX; | |
611 | else | |
612 | switch (prefix) | |
613 | { | |
614 | default: | |
615 | abort (); | |
616 | ||
617 | case CS_PREFIX_OPCODE: | |
618 | case DS_PREFIX_OPCODE: | |
619 | case ES_PREFIX_OPCODE: | |
620 | case FS_PREFIX_OPCODE: | |
621 | case GS_PREFIX_OPCODE: | |
622 | case SS_PREFIX_OPCODE: | |
623 | q = SEG_PREFIX; | |
624 | break; | |
252b5132 | 625 | |
3e73aa7c JH |
626 | case REPNE_PREFIX_OPCODE: |
627 | case REPE_PREFIX_OPCODE: | |
628 | ret = 2; | |
629 | /* fall thru */ | |
630 | case LOCK_PREFIX_OPCODE: | |
631 | q = LOCKREP_PREFIX; | |
632 | break; | |
252b5132 | 633 | |
3e73aa7c JH |
634 | case FWAIT_OPCODE: |
635 | q = WAIT_PREFIX; | |
636 | break; | |
252b5132 | 637 | |
3e73aa7c JH |
638 | case ADDR_PREFIX_OPCODE: |
639 | q = ADDR_PREFIX; | |
640 | break; | |
252b5132 | 641 | |
3e73aa7c JH |
642 | case DATA_PREFIX_OPCODE: |
643 | q = DATA_PREFIX; | |
644 | break; | |
645 | } | |
252b5132 RH |
646 | |
647 | if (i.prefix[q]) | |
648 | { | |
649 | as_bad (_("same type of prefix used twice")); | |
650 | return 0; | |
651 | } | |
652 | ||
653 | i.prefixes += 1; | |
654 | i.prefix[q] = prefix; | |
655 | return ret; | |
656 | } | |
657 | ||
658 | static void | |
3e73aa7c | 659 | set_code_flag (value) |
e5cb08ac | 660 | int value; |
eecb386c | 661 | { |
3e73aa7c JH |
662 | flag_code = value; |
663 | cpu_arch_flags &= ~(Cpu64 | CpuNo64); | |
664 | cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64); | |
665 | if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer)) | |
666 | { | |
667 | as_bad (_("64bit mode not supported on this CPU.")); | |
668 | } | |
669 | if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386)) | |
670 | { | |
671 | as_bad (_("32bit mode not supported on this CPU.")); | |
672 | } | |
eecb386c AM |
673 | stackop_size = '\0'; |
674 | } | |
675 | ||
676 | static void | |
3e73aa7c JH |
677 | set_16bit_gcc_code_flag (new_code_flag) |
678 | int new_code_flag; | |
252b5132 | 679 | { |
3e73aa7c JH |
680 | flag_code = new_code_flag; |
681 | cpu_arch_flags &= ~(Cpu64 | CpuNo64); | |
682 | cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64); | |
683 | stackop_size = 'l'; | |
252b5132 RH |
684 | } |
685 | ||
686 | static void | |
687 | set_intel_syntax (syntax_flag) | |
eecb386c | 688 | int syntax_flag; |
252b5132 RH |
689 | { |
690 | /* Find out if register prefixing is specified. */ | |
691 | int ask_naked_reg = 0; | |
692 | ||
693 | SKIP_WHITESPACE (); | |
694 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
695 | { | |
696 | char *string = input_line_pointer; | |
697 | int e = get_symbol_end (); | |
698 | ||
47926f60 | 699 | if (strcmp (string, "prefix") == 0) |
252b5132 | 700 | ask_naked_reg = 1; |
47926f60 | 701 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
702 | ask_naked_reg = -1; |
703 | else | |
d0b47220 | 704 | as_bad (_("bad argument to syntax directive.")); |
252b5132 RH |
705 | *input_line_pointer = e; |
706 | } | |
707 | demand_empty_rest_of_line (); | |
c3332e24 | 708 | |
252b5132 RH |
709 | intel_syntax = syntax_flag; |
710 | ||
711 | if (ask_naked_reg == 0) | |
712 | { | |
713 | #ifdef BFD_ASSEMBLER | |
714 | allow_naked_reg = (intel_syntax | |
24eab124 | 715 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); |
252b5132 | 716 | #else |
47926f60 KH |
717 | /* Conservative default. */ |
718 | allow_naked_reg = 0; | |
252b5132 RH |
719 | #endif |
720 | } | |
721 | else | |
722 | allow_naked_reg = (ask_naked_reg < 0); | |
723 | } | |
724 | ||
e413e4e9 AM |
725 | static void |
726 | set_cpu_arch (dummy) | |
47926f60 | 727 | int dummy ATTRIBUTE_UNUSED; |
e413e4e9 | 728 | { |
47926f60 | 729 | SKIP_WHITESPACE (); |
e413e4e9 AM |
730 | |
731 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
732 | { | |
733 | char *string = input_line_pointer; | |
734 | int e = get_symbol_end (); | |
735 | int i; | |
736 | ||
737 | for (i = 0; cpu_arch[i].name; i++) | |
738 | { | |
739 | if (strcmp (string, cpu_arch[i].name) == 0) | |
740 | { | |
741 | cpu_arch_name = cpu_arch[i].name; | |
fddf5b5b AM |
742 | cpu_arch_flags = (cpu_arch[i].flags |
743 | | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64)); | |
e413e4e9 AM |
744 | break; |
745 | } | |
746 | } | |
747 | if (!cpu_arch[i].name) | |
748 | as_bad (_("no such architecture: `%s'"), string); | |
749 | ||
750 | *input_line_pointer = e; | |
751 | } | |
752 | else | |
753 | as_bad (_("missing cpu architecture")); | |
754 | ||
fddf5b5b AM |
755 | no_cond_jump_promotion = 0; |
756 | if (*input_line_pointer == ',' | |
757 | && ! is_end_of_line[(unsigned char) input_line_pointer[1]]) | |
758 | { | |
759 | char *string = ++input_line_pointer; | |
760 | int e = get_symbol_end (); | |
761 | ||
762 | if (strcmp (string, "nojumps") == 0) | |
763 | no_cond_jump_promotion = 1; | |
764 | else if (strcmp (string, "jumps") == 0) | |
765 | ; | |
766 | else | |
767 | as_bad (_("no such architecture modifier: `%s'"), string); | |
768 | ||
769 | *input_line_pointer = e; | |
770 | } | |
771 | ||
e413e4e9 AM |
772 | demand_empty_rest_of_line (); |
773 | } | |
774 | ||
252b5132 RH |
775 | const pseudo_typeS md_pseudo_table[] = |
776 | { | |
252b5132 RH |
777 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) |
778 | {"align", s_align_bytes, 0}, | |
779 | #else | |
780 | {"align", s_align_ptwo, 0}, | |
e413e4e9 AM |
781 | #endif |
782 | {"arch", set_cpu_arch, 0}, | |
783 | #ifndef I386COFF | |
784 | {"bss", s_bss, 0}, | |
252b5132 RH |
785 | #endif |
786 | {"ffloat", float_cons, 'f'}, | |
787 | {"dfloat", float_cons, 'd'}, | |
788 | {"tfloat", float_cons, 'x'}, | |
789 | {"value", cons, 2}, | |
790 | {"noopt", s_ignore, 0}, | |
791 | {"optim", s_ignore, 0}, | |
3e73aa7c JH |
792 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, |
793 | {"code16", set_code_flag, CODE_16BIT}, | |
794 | {"code32", set_code_flag, CODE_32BIT}, | |
795 | {"code64", set_code_flag, CODE_64BIT}, | |
252b5132 RH |
796 | {"intel_syntax", set_intel_syntax, 1}, |
797 | {"att_syntax", set_intel_syntax, 0}, | |
316e2c05 RH |
798 | {"file", dwarf2_directive_file, 0}, |
799 | {"loc", dwarf2_directive_loc, 0}, | |
252b5132 RH |
800 | {0, 0, 0} |
801 | }; | |
802 | ||
47926f60 | 803 | /* For interface with expression (). */ |
252b5132 RH |
804 | extern char *input_line_pointer; |
805 | ||
47926f60 | 806 | /* Hash table for instruction mnemonic lookup. */ |
252b5132 | 807 | static struct hash_control *op_hash; |
47926f60 KH |
808 | |
809 | /* Hash table for register lookup. */ | |
252b5132 RH |
810 | static struct hash_control *reg_hash; |
811 | \f | |
b9d79e03 JH |
812 | #ifdef BFD_ASSEMBLER |
813 | unsigned long | |
814 | i386_mach () | |
815 | { | |
816 | if (!strcmp (default_arch, "x86_64")) | |
817 | return bfd_mach_x86_64; | |
818 | else if (!strcmp (default_arch, "i386")) | |
819 | return bfd_mach_i386_i386; | |
820 | else | |
821 | as_fatal (_("Unknown architecture")); | |
822 | } | |
823 | #endif | |
824 | \f | |
252b5132 RH |
825 | void |
826 | md_begin () | |
827 | { | |
828 | const char *hash_err; | |
829 | ||
47926f60 | 830 | /* Initialize op_hash hash table. */ |
252b5132 RH |
831 | op_hash = hash_new (); |
832 | ||
833 | { | |
834 | register const template *optab; | |
835 | register templates *core_optab; | |
836 | ||
47926f60 KH |
837 | /* Setup for loop. */ |
838 | optab = i386_optab; | |
252b5132 RH |
839 | core_optab = (templates *) xmalloc (sizeof (templates)); |
840 | core_optab->start = optab; | |
841 | ||
842 | while (1) | |
843 | { | |
844 | ++optab; | |
845 | if (optab->name == NULL | |
846 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
847 | { | |
848 | /* different name --> ship out current template list; | |
47926f60 | 849 | add to hash table; & begin anew. */ |
252b5132 RH |
850 | core_optab->end = optab; |
851 | hash_err = hash_insert (op_hash, | |
852 | (optab - 1)->name, | |
853 | (PTR) core_optab); | |
854 | if (hash_err) | |
855 | { | |
252b5132 RH |
856 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
857 | (optab - 1)->name, | |
858 | hash_err); | |
859 | } | |
860 | if (optab->name == NULL) | |
861 | break; | |
862 | core_optab = (templates *) xmalloc (sizeof (templates)); | |
863 | core_optab->start = optab; | |
864 | } | |
865 | } | |
866 | } | |
867 | ||
47926f60 | 868 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
869 | reg_hash = hash_new (); |
870 | { | |
871 | register const reg_entry *regtab; | |
872 | ||
873 | for (regtab = i386_regtab; | |
874 | regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]); | |
875 | regtab++) | |
876 | { | |
877 | hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab); | |
878 | if (hash_err) | |
3e73aa7c JH |
879 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
880 | regtab->reg_name, | |
881 | hash_err); | |
252b5132 RH |
882 | } |
883 | } | |
884 | ||
47926f60 | 885 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 RH |
886 | { |
887 | register int c; | |
888 | register char *p; | |
889 | ||
890 | for (c = 0; c < 256; c++) | |
891 | { | |
3882b010 | 892 | if (ISDIGIT (c)) |
252b5132 RH |
893 | { |
894 | digit_chars[c] = c; | |
895 | mnemonic_chars[c] = c; | |
896 | register_chars[c] = c; | |
897 | operand_chars[c] = c; | |
898 | } | |
3882b010 | 899 | else if (ISLOWER (c)) |
252b5132 RH |
900 | { |
901 | mnemonic_chars[c] = c; | |
902 | register_chars[c] = c; | |
903 | operand_chars[c] = c; | |
904 | } | |
3882b010 | 905 | else if (ISUPPER (c)) |
252b5132 | 906 | { |
3882b010 | 907 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
908 | register_chars[c] = mnemonic_chars[c]; |
909 | operand_chars[c] = c; | |
910 | } | |
911 | ||
3882b010 | 912 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
913 | identifier_chars[c] = c; |
914 | else if (c >= 128) | |
915 | { | |
916 | identifier_chars[c] = c; | |
917 | operand_chars[c] = c; | |
918 | } | |
919 | } | |
920 | ||
921 | #ifdef LEX_AT | |
922 | identifier_chars['@'] = '@'; | |
923 | #endif | |
252b5132 RH |
924 | digit_chars['-'] = '-'; |
925 | identifier_chars['_'] = '_'; | |
926 | identifier_chars['.'] = '.'; | |
927 | ||
928 | for (p = operand_special_chars; *p != '\0'; p++) | |
929 | operand_chars[(unsigned char) *p] = *p; | |
930 | } | |
931 | ||
932 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
933 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
934 | { | |
935 | record_alignment (text_section, 2); | |
936 | record_alignment (data_section, 2); | |
937 | record_alignment (bss_section, 2); | |
938 | } | |
939 | #endif | |
940 | } | |
941 | ||
942 | void | |
943 | i386_print_statistics (file) | |
944 | FILE *file; | |
945 | { | |
946 | hash_print_statistics (file, "i386 opcode", op_hash); | |
947 | hash_print_statistics (file, "i386 register", reg_hash); | |
948 | } | |
949 | \f | |
252b5132 RH |
950 | #ifdef DEBUG386 |
951 | ||
ce8a8b2f | 952 | /* Debugging routines for md_assemble. */ |
252b5132 RH |
953 | static void pi PARAMS ((char *, i386_insn *)); |
954 | static void pte PARAMS ((template *)); | |
955 | static void pt PARAMS ((unsigned int)); | |
956 | static void pe PARAMS ((expressionS *)); | |
957 | static void ps PARAMS ((symbolS *)); | |
958 | ||
959 | static void | |
960 | pi (line, x) | |
961 | char *line; | |
962 | i386_insn *x; | |
963 | { | |
09f131f2 | 964 | unsigned int i; |
252b5132 RH |
965 | |
966 | fprintf (stdout, "%s: template ", line); | |
967 | pte (&x->tm); | |
09f131f2 JH |
968 | fprintf (stdout, " address: base %s index %s scale %x\n", |
969 | x->base_reg ? x->base_reg->reg_name : "none", | |
970 | x->index_reg ? x->index_reg->reg_name : "none", | |
971 | x->log2_scale_factor); | |
972 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 973 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
974 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
975 | x->sib.base, x->sib.index, x->sib.scale); | |
976 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
977 | x->rex.mode64, x->rex.extX, x->rex.extY, x->rex.extZ); | |
252b5132 RH |
978 | for (i = 0; i < x->operands; i++) |
979 | { | |
980 | fprintf (stdout, " #%d: ", i + 1); | |
981 | pt (x->types[i]); | |
982 | fprintf (stdout, "\n"); | |
983 | if (x->types[i] | |
3f4438ab | 984 | & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM)) |
520dc8e8 | 985 | fprintf (stdout, "%s\n", x->op[i].regs->reg_name); |
252b5132 | 986 | if (x->types[i] & Imm) |
520dc8e8 | 987 | pe (x->op[i].imms); |
252b5132 | 988 | if (x->types[i] & Disp) |
520dc8e8 | 989 | pe (x->op[i].disps); |
252b5132 RH |
990 | } |
991 | } | |
992 | ||
993 | static void | |
994 | pte (t) | |
995 | template *t; | |
996 | { | |
09f131f2 | 997 | unsigned int i; |
252b5132 | 998 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 999 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
1000 | if (t->extension_opcode != None) |
1001 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
1002 | if (t->opcode_modifier & D) | |
1003 | fprintf (stdout, "D"); | |
1004 | if (t->opcode_modifier & W) | |
1005 | fprintf (stdout, "W"); | |
1006 | fprintf (stdout, "\n"); | |
1007 | for (i = 0; i < t->operands; i++) | |
1008 | { | |
1009 | fprintf (stdout, " #%d type ", i + 1); | |
1010 | pt (t->operand_types[i]); | |
1011 | fprintf (stdout, "\n"); | |
1012 | } | |
1013 | } | |
1014 | ||
1015 | static void | |
1016 | pe (e) | |
1017 | expressionS *e; | |
1018 | { | |
24eab124 | 1019 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
1020 | fprintf (stdout, " add_number %ld (%lx)\n", |
1021 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
1022 | if (e->X_add_symbol) |
1023 | { | |
1024 | fprintf (stdout, " add_symbol "); | |
1025 | ps (e->X_add_symbol); | |
1026 | fprintf (stdout, "\n"); | |
1027 | } | |
1028 | if (e->X_op_symbol) | |
1029 | { | |
1030 | fprintf (stdout, " op_symbol "); | |
1031 | ps (e->X_op_symbol); | |
1032 | fprintf (stdout, "\n"); | |
1033 | } | |
1034 | } | |
1035 | ||
1036 | static void | |
1037 | ps (s) | |
1038 | symbolS *s; | |
1039 | { | |
1040 | fprintf (stdout, "%s type %s%s", | |
1041 | S_GET_NAME (s), | |
1042 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
1043 | segment_name (S_GET_SEGMENT (s))); | |
1044 | } | |
1045 | ||
1046 | struct type_name | |
1047 | { | |
1048 | unsigned int mask; | |
1049 | char *tname; | |
1050 | } | |
1051 | ||
1052 | type_names[] = | |
1053 | { | |
1054 | { Reg8, "r8" }, | |
1055 | { Reg16, "r16" }, | |
1056 | { Reg32, "r32" }, | |
09f131f2 | 1057 | { Reg64, "r64" }, |
252b5132 RH |
1058 | { Imm8, "i8" }, |
1059 | { Imm8S, "i8s" }, | |
1060 | { Imm16, "i16" }, | |
1061 | { Imm32, "i32" }, | |
09f131f2 JH |
1062 | { Imm32S, "i32s" }, |
1063 | { Imm64, "i64" }, | |
252b5132 RH |
1064 | { Imm1, "i1" }, |
1065 | { BaseIndex, "BaseIndex" }, | |
1066 | { Disp8, "d8" }, | |
1067 | { Disp16, "d16" }, | |
1068 | { Disp32, "d32" }, | |
09f131f2 JH |
1069 | { Disp32S, "d32s" }, |
1070 | { Disp64, "d64" }, | |
252b5132 RH |
1071 | { InOutPortReg, "InOutPortReg" }, |
1072 | { ShiftCount, "ShiftCount" }, | |
1073 | { Control, "control reg" }, | |
1074 | { Test, "test reg" }, | |
1075 | { Debug, "debug reg" }, | |
1076 | { FloatReg, "FReg" }, | |
1077 | { FloatAcc, "FAcc" }, | |
1078 | { SReg2, "SReg2" }, | |
1079 | { SReg3, "SReg3" }, | |
1080 | { Acc, "Acc" }, | |
1081 | { JumpAbsolute, "Jump Absolute" }, | |
1082 | { RegMMX, "rMMX" }, | |
3f4438ab | 1083 | { RegXMM, "rXMM" }, |
252b5132 RH |
1084 | { EsSeg, "es" }, |
1085 | { 0, "" } | |
1086 | }; | |
1087 | ||
1088 | static void | |
1089 | pt (t) | |
1090 | unsigned int t; | |
1091 | { | |
1092 | register struct type_name *ty; | |
1093 | ||
09f131f2 JH |
1094 | for (ty = type_names; ty->mask; ty++) |
1095 | if (t & ty->mask) | |
1096 | fprintf (stdout, "%s, ", ty->tname); | |
252b5132 RH |
1097 | fflush (stdout); |
1098 | } | |
1099 | ||
1100 | #endif /* DEBUG386 */ | |
1101 | \f | |
1102 | int | |
1103 | tc_i386_force_relocation (fixp) | |
1104 | struct fix *fixp; | |
1105 | { | |
1106 | #ifdef BFD_ASSEMBLER | |
1107 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
1108 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1109 | return 1; | |
1110 | return 0; | |
1111 | #else | |
ce8a8b2f | 1112 | /* For COFF. */ |
f6af82bd | 1113 | return fixp->fx_r_type == 7; |
252b5132 RH |
1114 | #endif |
1115 | } | |
1116 | ||
1117 | #ifdef BFD_ASSEMBLER | |
252b5132 RH |
1118 | |
1119 | static bfd_reloc_code_real_type | |
3e73aa7c | 1120 | reloc (size, pcrel, sign, other) |
252b5132 RH |
1121 | int size; |
1122 | int pcrel; | |
3e73aa7c | 1123 | int sign; |
252b5132 RH |
1124 | bfd_reloc_code_real_type other; |
1125 | { | |
47926f60 KH |
1126 | if (other != NO_RELOC) |
1127 | return other; | |
252b5132 RH |
1128 | |
1129 | if (pcrel) | |
1130 | { | |
3e73aa7c | 1131 | if (!sign) |
e5cb08ac | 1132 | as_bad (_("There are no unsigned pc-relative relocations")); |
252b5132 RH |
1133 | switch (size) |
1134 | { | |
1135 | case 1: return BFD_RELOC_8_PCREL; | |
1136 | case 2: return BFD_RELOC_16_PCREL; | |
1137 | case 4: return BFD_RELOC_32_PCREL; | |
1138 | } | |
d0b47220 | 1139 | as_bad (_("can not do %d byte pc-relative relocation"), size); |
252b5132 RH |
1140 | } |
1141 | else | |
1142 | { | |
3e73aa7c | 1143 | if (sign) |
e5cb08ac | 1144 | switch (size) |
3e73aa7c JH |
1145 | { |
1146 | case 4: return BFD_RELOC_X86_64_32S; | |
1147 | } | |
1148 | else | |
1149 | switch (size) | |
1150 | { | |
1151 | case 1: return BFD_RELOC_8; | |
1152 | case 2: return BFD_RELOC_16; | |
1153 | case 4: return BFD_RELOC_32; | |
1154 | case 8: return BFD_RELOC_64; | |
1155 | } | |
1156 | as_bad (_("can not do %s %d byte relocation"), | |
1157 | sign ? "signed" : "unsigned", size); | |
252b5132 RH |
1158 | } |
1159 | ||
bfb32b52 | 1160 | abort (); |
252b5132 RH |
1161 | return BFD_RELOC_NONE; |
1162 | } | |
1163 | ||
47926f60 KH |
1164 | /* Here we decide which fixups can be adjusted to make them relative to |
1165 | the beginning of the section instead of the symbol. Basically we need | |
1166 | to make sure that the dynamic relocations are done correctly, so in | |
1167 | some cases we force the original symbol to be used. */ | |
1168 | ||
252b5132 | 1169 | int |
c0c949c7 | 1170 | tc_i386_fix_adjustable (fixP) |
47926f60 | 1171 | fixS *fixP; |
252b5132 | 1172 | { |
6d249963 | 1173 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
79d292aa ILT |
1174 | /* Prevent all adjustments to global symbols, or else dynamic |
1175 | linking will not work correctly. */ | |
b98ef147 AM |
1176 | if (S_IS_EXTERNAL (fixP->fx_addsy) |
1177 | || S_IS_WEAK (fixP->fx_addsy)) | |
252b5132 RH |
1178 | return 0; |
1179 | #endif | |
ce8a8b2f | 1180 | /* adjust_reloc_syms doesn't know about the GOT. */ |
252b5132 RH |
1181 | if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF |
1182 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 | |
1183 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
3e73aa7c JH |
1184 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
1185 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
80b3ee89 | 1186 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
252b5132 RH |
1187 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
1188 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1189 | return 0; | |
1190 | return 1; | |
1191 | } | |
1192 | #else | |
ec56dfb4 L |
1193 | #define reloc(SIZE,PCREL,SIGN,OTHER) 0 |
1194 | #define BFD_RELOC_16 0 | |
1195 | #define BFD_RELOC_32 0 | |
1196 | #define BFD_RELOC_16_PCREL 0 | |
1197 | #define BFD_RELOC_32_PCREL 0 | |
1198 | #define BFD_RELOC_386_PLT32 0 | |
1199 | #define BFD_RELOC_386_GOT32 0 | |
1200 | #define BFD_RELOC_386_GOTOFF 0 | |
1201 | #define BFD_RELOC_X86_64_PLT32 0 | |
1202 | #define BFD_RELOC_X86_64_GOT32 0 | |
1203 | #define BFD_RELOC_X86_64_GOTPCREL 0 | |
252b5132 RH |
1204 | #endif |
1205 | ||
47926f60 | 1206 | static int intel_float_operand PARAMS ((char *mnemonic)); |
b4cac588 AM |
1207 | |
1208 | static int | |
252b5132 RH |
1209 | intel_float_operand (mnemonic) |
1210 | char *mnemonic; | |
1211 | { | |
47926f60 | 1212 | if (mnemonic[0] == 'f' && mnemonic[1] == 'i') |
cc5ca5ce | 1213 | return 2; |
252b5132 RH |
1214 | |
1215 | if (mnemonic[0] == 'f') | |
1216 | return 1; | |
1217 | ||
1218 | return 0; | |
1219 | } | |
1220 | ||
1221 | /* This is the guts of the machine-dependent assembler. LINE points to a | |
1222 | machine dependent instruction. This function is supposed to emit | |
1223 | the frags/bytes it assembles to. */ | |
1224 | ||
1225 | void | |
1226 | md_assemble (line) | |
1227 | char *line; | |
1228 | { | |
47926f60 | 1229 | /* Points to template once we've found it. */ |
252b5132 RH |
1230 | const template *t; |
1231 | ||
252b5132 RH |
1232 | int j; |
1233 | ||
1234 | char mnemonic[MAX_MNEM_SIZE]; | |
1235 | ||
47926f60 | 1236 | /* Initialize globals. */ |
252b5132 RH |
1237 | memset (&i, '\0', sizeof (i)); |
1238 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 1239 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
1240 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
1241 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 1242 | save_stack_p = save_stack; |
252b5132 RH |
1243 | |
1244 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
1245 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 1246 | start of a (possibly prefixed) mnemonic. */ |
252b5132 RH |
1247 | { |
1248 | char *l = line; | |
1249 | char *token_start = l; | |
1250 | char *mnem_p; | |
1251 | ||
47926f60 | 1252 | /* Non-zero if we found a prefix only acceptable with string insns. */ |
252b5132 RH |
1253 | const char *expecting_string_instruction = NULL; |
1254 | ||
1255 | while (1) | |
1256 | { | |
1257 | mnem_p = mnemonic; | |
1258 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
1259 | { | |
1260 | mnem_p++; | |
1261 | if (mnem_p >= mnemonic + sizeof (mnemonic)) | |
1262 | { | |
e413e4e9 | 1263 | as_bad (_("no such instruction: `%s'"), token_start); |
252b5132 RH |
1264 | return; |
1265 | } | |
1266 | l++; | |
1267 | } | |
1268 | if (!is_space_char (*l) | |
1269 | && *l != END_OF_INSN | |
5dd0794d AM |
1270 | && *l != PREFIX_SEPARATOR |
1271 | && *l != ',') | |
252b5132 RH |
1272 | { |
1273 | as_bad (_("invalid character %s in mnemonic"), | |
1274 | output_invalid (*l)); | |
1275 | return; | |
1276 | } | |
1277 | if (token_start == l) | |
1278 | { | |
1279 | if (*l == PREFIX_SEPARATOR) | |
1280 | as_bad (_("expecting prefix; got nothing")); | |
1281 | else | |
1282 | as_bad (_("expecting mnemonic; got nothing")); | |
1283 | return; | |
1284 | } | |
1285 | ||
1286 | /* Look up instruction (or prefix) via hash table. */ | |
1287 | current_templates = hash_find (op_hash, mnemonic); | |
1288 | ||
1289 | if (*l != END_OF_INSN | |
1290 | && (! is_space_char (*l) || l[1] != END_OF_INSN) | |
1291 | && current_templates | |
1292 | && (current_templates->start->opcode_modifier & IsPrefix)) | |
1293 | { | |
1294 | /* If we are in 16-bit mode, do not allow addr16 or data16. | |
1295 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
1296 | if ((current_templates->start->opcode_modifier & (Size16 | Size32)) | |
1297 | && (((current_templates->start->opcode_modifier & Size32) != 0) | |
3e73aa7c | 1298 | ^ (flag_code == CODE_16BIT))) |
252b5132 RH |
1299 | { |
1300 | as_bad (_("redundant %s prefix"), | |
1301 | current_templates->start->name); | |
1302 | return; | |
1303 | } | |
1304 | /* Add prefix, checking for repeated prefixes. */ | |
1305 | switch (add_prefix (current_templates->start->base_opcode)) | |
1306 | { | |
1307 | case 0: | |
1308 | return; | |
1309 | case 2: | |
47926f60 | 1310 | expecting_string_instruction = current_templates->start->name; |
252b5132 RH |
1311 | break; |
1312 | } | |
1313 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
1314 | token_start = ++l; | |
1315 | } | |
1316 | else | |
1317 | break; | |
1318 | } | |
1319 | ||
1320 | if (!current_templates) | |
1321 | { | |
24eab124 | 1322 | /* See if we can get a match by trimming off a suffix. */ |
252b5132 RH |
1323 | switch (mnem_p[-1]) |
1324 | { | |
252b5132 RH |
1325 | case WORD_MNEM_SUFFIX: |
1326 | case BYTE_MNEM_SUFFIX: | |
3e73aa7c | 1327 | case QWORD_MNEM_SUFFIX: |
252b5132 RH |
1328 | i.suffix = mnem_p[-1]; |
1329 | mnem_p[-1] = '\0'; | |
1330 | current_templates = hash_find (op_hash, mnemonic); | |
24eab124 | 1331 | break; |
f16b83df JH |
1332 | case SHORT_MNEM_SUFFIX: |
1333 | case LONG_MNEM_SUFFIX: | |
1334 | if (!intel_syntax) | |
1335 | { | |
1336 | i.suffix = mnem_p[-1]; | |
1337 | mnem_p[-1] = '\0'; | |
1338 | current_templates = hash_find (op_hash, mnemonic); | |
1339 | } | |
1340 | break; | |
24eab124 | 1341 | |
ce8a8b2f | 1342 | /* Intel Syntax. */ |
f16b83df | 1343 | case 'd': |
24eab124 AM |
1344 | if (intel_syntax) |
1345 | { | |
f16b83df JH |
1346 | if (intel_float_operand (mnemonic)) |
1347 | i.suffix = SHORT_MNEM_SUFFIX; | |
1348 | else | |
1349 | i.suffix = LONG_MNEM_SUFFIX; | |
24eab124 AM |
1350 | mnem_p[-1] = '\0'; |
1351 | current_templates = hash_find (op_hash, mnemonic); | |
24eab124 | 1352 | } |
f16b83df | 1353 | break; |
252b5132 RH |
1354 | } |
1355 | if (!current_templates) | |
1356 | { | |
e413e4e9 | 1357 | as_bad (_("no such instruction: `%s'"), token_start); |
252b5132 RH |
1358 | return; |
1359 | } | |
1360 | } | |
1361 | ||
5dd0794d AM |
1362 | if (current_templates->start->opcode_modifier & (Jump | JumpByte)) |
1363 | { | |
1364 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
1365 | predict taken and predict not taken respectively. | |
1366 | I'm not sure that branch hints actually do anything on loop | |
1367 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
1368 | may work in the future and it doesn't hurt to accept them | |
1369 | now. */ | |
1370 | if (l[0] == ',' && l[1] == 'p') | |
1371 | { | |
1372 | if (l[2] == 't') | |
1373 | { | |
1374 | if (! add_prefix (DS_PREFIX_OPCODE)) | |
1375 | return; | |
1376 | l += 3; | |
1377 | } | |
1378 | else if (l[2] == 'n') | |
1379 | { | |
1380 | if (! add_prefix (CS_PREFIX_OPCODE)) | |
1381 | return; | |
1382 | l += 3; | |
1383 | } | |
1384 | } | |
1385 | } | |
1386 | /* Any other comma loses. */ | |
1387 | if (*l == ',') | |
1388 | { | |
1389 | as_bad (_("invalid character %s in mnemonic"), | |
1390 | output_invalid (*l)); | |
1391 | return; | |
1392 | } | |
1393 | ||
e413e4e9 | 1394 | /* Check if instruction is supported on specified architecture. */ |
a847613f AM |
1395 | if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64)) |
1396 | & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))) | |
e413e4e9 | 1397 | { |
a847613f AM |
1398 | as_warn (_("`%s' is not supported on `%s'"), |
1399 | current_templates->start->name, cpu_arch_name); | |
1400 | } | |
1401 | else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT)) | |
1402 | { | |
1403 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
e413e4e9 AM |
1404 | } |
1405 | ||
ce8a8b2f | 1406 | /* Check for rep/repne without a string instruction. */ |
252b5132 RH |
1407 | if (expecting_string_instruction |
1408 | && !(current_templates->start->opcode_modifier & IsString)) | |
1409 | { | |
1410 | as_bad (_("expecting string instruction after `%s'"), | |
1411 | expecting_string_instruction); | |
1412 | return; | |
1413 | } | |
1414 | ||
47926f60 | 1415 | /* There may be operands to parse. */ |
252b5132 RH |
1416 | if (*l != END_OF_INSN) |
1417 | { | |
47926f60 | 1418 | /* 1 if operand is pending after ','. */ |
252b5132 RH |
1419 | unsigned int expecting_operand = 0; |
1420 | ||
47926f60 | 1421 | /* Non-zero if operand parens not balanced. */ |
252b5132 RH |
1422 | unsigned int paren_not_balanced; |
1423 | ||
1424 | do | |
1425 | { | |
ce8a8b2f | 1426 | /* Skip optional white space before operand. */ |
252b5132 RH |
1427 | if (is_space_char (*l)) |
1428 | ++l; | |
1429 | if (!is_operand_char (*l) && *l != END_OF_INSN) | |
1430 | { | |
1431 | as_bad (_("invalid character %s before operand %d"), | |
1432 | output_invalid (*l), | |
1433 | i.operands + 1); | |
1434 | return; | |
1435 | } | |
1436 | token_start = l; /* after white space */ | |
1437 | paren_not_balanced = 0; | |
1438 | while (paren_not_balanced || *l != ',') | |
1439 | { | |
1440 | if (*l == END_OF_INSN) | |
1441 | { | |
1442 | if (paren_not_balanced) | |
1443 | { | |
24eab124 | 1444 | if (!intel_syntax) |
252b5132 RH |
1445 | as_bad (_("unbalanced parenthesis in operand %d."), |
1446 | i.operands + 1); | |
24eab124 | 1447 | else |
252b5132 RH |
1448 | as_bad (_("unbalanced brackets in operand %d."), |
1449 | i.operands + 1); | |
1450 | return; | |
1451 | } | |
1452 | else | |
1453 | break; /* we are done */ | |
1454 | } | |
1455 | else if (!is_operand_char (*l) && !is_space_char (*l)) | |
1456 | { | |
1457 | as_bad (_("invalid character %s in operand %d"), | |
1458 | output_invalid (*l), | |
1459 | i.operands + 1); | |
1460 | return; | |
1461 | } | |
24eab124 AM |
1462 | if (!intel_syntax) |
1463 | { | |
252b5132 RH |
1464 | if (*l == '(') |
1465 | ++paren_not_balanced; | |
1466 | if (*l == ')') | |
1467 | --paren_not_balanced; | |
24eab124 AM |
1468 | } |
1469 | else | |
1470 | { | |
252b5132 RH |
1471 | if (*l == '[') |
1472 | ++paren_not_balanced; | |
1473 | if (*l == ']') | |
1474 | --paren_not_balanced; | |
24eab124 | 1475 | } |
252b5132 RH |
1476 | l++; |
1477 | } | |
1478 | if (l != token_start) | |
47926f60 | 1479 | { /* Yes, we've read in another operand. */ |
252b5132 RH |
1480 | unsigned int operand_ok; |
1481 | this_operand = i.operands++; | |
1482 | if (i.operands > MAX_OPERANDS) | |
1483 | { | |
1484 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
1485 | MAX_OPERANDS); | |
1486 | return; | |
1487 | } | |
47926f60 | 1488 | /* Now parse operand adding info to 'i' as we go along. */ |
252b5132 RH |
1489 | END_STRING_AND_SAVE (l); |
1490 | ||
24eab124 | 1491 | if (intel_syntax) |
47926f60 KH |
1492 | operand_ok = |
1493 | i386_intel_operand (token_start, | |
1494 | intel_float_operand (mnemonic)); | |
24eab124 AM |
1495 | else |
1496 | operand_ok = i386_operand (token_start); | |
252b5132 | 1497 | |
ce8a8b2f | 1498 | RESTORE_END_STRING (l); |
252b5132 RH |
1499 | if (!operand_ok) |
1500 | return; | |
1501 | } | |
1502 | else | |
1503 | { | |
1504 | if (expecting_operand) | |
1505 | { | |
1506 | expecting_operand_after_comma: | |
1507 | as_bad (_("expecting operand after ','; got nothing")); | |
1508 | return; | |
1509 | } | |
1510 | if (*l == ',') | |
1511 | { | |
1512 | as_bad (_("expecting operand before ','; got nothing")); | |
1513 | return; | |
1514 | } | |
1515 | } | |
1516 | ||
ce8a8b2f | 1517 | /* Now *l must be either ',' or END_OF_INSN. */ |
252b5132 RH |
1518 | if (*l == ',') |
1519 | { | |
1520 | if (*++l == END_OF_INSN) | |
ce8a8b2f AM |
1521 | { |
1522 | /* Just skip it, if it's \n complain. */ | |
252b5132 RH |
1523 | goto expecting_operand_after_comma; |
1524 | } | |
1525 | expecting_operand = 1; | |
1526 | } | |
1527 | } | |
ce8a8b2f | 1528 | while (*l != END_OF_INSN); |
252b5132 RH |
1529 | } |
1530 | } | |
1531 | ||
1532 | /* Now we've parsed the mnemonic into a set of templates, and have the | |
1533 | operands at hand. | |
1534 | ||
1535 | Next, we find a template that matches the given insn, | |
1536 | making sure the overlap of the given operands types is consistent | |
47926f60 | 1537 | with the template operand types. */ |
252b5132 RH |
1538 | |
1539 | #define MATCH(overlap, given, template) \ | |
3138f287 AM |
1540 | ((overlap & ~JumpAbsolute) \ |
1541 | && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute))) | |
252b5132 RH |
1542 | |
1543 | /* If given types r0 and r1 are registers they must be of the same type | |
1544 | unless the expected operand type register overlap is null. | |
1545 | Note that Acc in a template matches every size of reg. */ | |
1546 | #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \ | |
1547 | ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \ | |
1548 | ((g0) & Reg) == ((g1) & Reg) || \ | |
1549 | ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 ) | |
1550 | ||
1551 | { | |
1552 | register unsigned int overlap0, overlap1; | |
252b5132 RH |
1553 | unsigned int overlap2; |
1554 | unsigned int found_reverse_match; | |
1555 | int suffix_check; | |
1556 | ||
cc5ca5ce AM |
1557 | /* All intel opcodes have reversed operands except for "bound" and |
1558 | "enter". We also don't reverse intersegment "jmp" and "call" | |
1559 | instructions with 2 immediate operands so that the immediate segment | |
1560 | precedes the offset, as it does when in AT&T mode. "enter" and the | |
1561 | intersegment "jmp" and "call" instructions are the only ones that | |
1562 | have two immediate operands. */ | |
520dc8e8 | 1563 | if (intel_syntax && i.operands > 1 |
cc5ca5ce AM |
1564 | && (strcmp (mnemonic, "bound") != 0) |
1565 | && !((i.types[0] & Imm) && (i.types[1] & Imm))) | |
252b5132 | 1566 | { |
520dc8e8 | 1567 | union i386_op temp_op; |
24eab124 | 1568 | unsigned int temp_type; |
f3c180ae | 1569 | RELOC_ENUM temp_reloc; |
24eab124 | 1570 | int xchg1 = 0; |
ab9da554 | 1571 | int xchg2 = 0; |
252b5132 | 1572 | |
24eab124 AM |
1573 | if (i.operands == 2) |
1574 | { | |
1575 | xchg1 = 0; | |
1576 | xchg2 = 1; | |
1577 | } | |
1578 | else if (i.operands == 3) | |
1579 | { | |
1580 | xchg1 = 0; | |
1581 | xchg2 = 2; | |
1582 | } | |
520dc8e8 AM |
1583 | temp_type = i.types[xchg2]; |
1584 | i.types[xchg2] = i.types[xchg1]; | |
1585 | i.types[xchg1] = temp_type; | |
1586 | temp_op = i.op[xchg2]; | |
1587 | i.op[xchg2] = i.op[xchg1]; | |
1588 | i.op[xchg1] = temp_op; | |
1ae12ab7 AM |
1589 | temp_reloc = i.reloc[xchg2]; |
1590 | i.reloc[xchg2] = i.reloc[xchg1]; | |
1591 | i.reloc[xchg1] = temp_reloc; | |
36bf8ab9 AM |
1592 | |
1593 | if (i.mem_operands == 2) | |
1594 | { | |
1595 | const seg_entry *temp_seg; | |
1596 | temp_seg = i.seg[0]; | |
1597 | i.seg[0] = i.seg[1]; | |
1598 | i.seg[1] = temp_seg; | |
1599 | } | |
24eab124 | 1600 | } |
773f551c AM |
1601 | |
1602 | if (i.imm_operands) | |
1603 | { | |
1604 | /* Try to ensure constant immediates are represented in the smallest | |
1605 | opcode possible. */ | |
1606 | char guess_suffix = 0; | |
1607 | int op; | |
1608 | ||
1609 | if (i.suffix) | |
1610 | guess_suffix = i.suffix; | |
1611 | else if (i.reg_operands) | |
1612 | { | |
1613 | /* Figure out a suffix from the last register operand specified. | |
1614 | We can't do this properly yet, ie. excluding InOutPortReg, | |
1615 | but the following works for instructions with immediates. | |
1616 | In any case, we can't set i.suffix yet. */ | |
47926f60 | 1617 | for (op = i.operands; --op >= 0;) |
773f551c AM |
1618 | if (i.types[op] & Reg) |
1619 | { | |
1620 | if (i.types[op] & Reg8) | |
1621 | guess_suffix = BYTE_MNEM_SUFFIX; | |
1622 | else if (i.types[op] & Reg16) | |
1623 | guess_suffix = WORD_MNEM_SUFFIX; | |
3e73aa7c JH |
1624 | else if (i.types[op] & Reg32) |
1625 | guess_suffix = LONG_MNEM_SUFFIX; | |
1626 | else if (i.types[op] & Reg64) | |
1627 | guess_suffix = QWORD_MNEM_SUFFIX; | |
773f551c AM |
1628 | break; |
1629 | } | |
1630 | } | |
3e73aa7c | 1631 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
726c5dcd AM |
1632 | guess_suffix = WORD_MNEM_SUFFIX; |
1633 | ||
47926f60 | 1634 | for (op = i.operands; --op >= 0;) |
3e73aa7c | 1635 | if (i.types[op] & Imm) |
773f551c | 1636 | { |
3e73aa7c | 1637 | switch (i.op[op].imms->X_op) |
e5cb08ac | 1638 | { |
3e73aa7c JH |
1639 | case O_constant: |
1640 | /* If a suffix is given, this operand may be shortened. */ | |
1641 | switch (guess_suffix) | |
1642 | { | |
1643 | case LONG_MNEM_SUFFIX: | |
1644 | i.types[op] |= Imm32 | Imm64; | |
1645 | break; | |
1646 | case WORD_MNEM_SUFFIX: | |
1647 | i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64; | |
1648 | break; | |
1649 | case BYTE_MNEM_SUFFIX: | |
1650 | i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64; | |
1651 | break; | |
1652 | } | |
773f551c | 1653 | |
e5cb08ac KH |
1654 | /* If this operand is at most 16 bits, convert it |
1655 | to a signed 16 bit number before trying to see | |
1656 | whether it will fit in an even smaller size. | |
1657 | This allows a 16-bit operand such as $0xffe0 to | |
1658 | be recognised as within Imm8S range. */ | |
3e73aa7c | 1659 | if ((i.types[op] & Imm16) |
e5cb08ac | 1660 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
3e73aa7c JH |
1661 | { |
1662 | i.op[op].imms->X_add_number = | |
1663 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
1664 | } | |
1665 | if ((i.types[op] & Imm32) | |
1666 | && (i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) == 0) | |
1667 | { | |
1668 | i.op[op].imms->X_add_number = | |
1669 | (i.op[op].imms->X_add_number ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
1670 | } | |
1671 | i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number); | |
1672 | /* We must avoid matching of Imm32 templates when 64bit only immediate is available. */ | |
1673 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
1674 | i.types[op] &= ~Imm32; | |
1675 | break; | |
1676 | case O_absent: | |
1677 | case O_register: | |
bfb32b52 | 1678 | abort (); |
3e73aa7c JH |
1679 | /* Symbols and expressions. */ |
1680 | default: | |
1681 | /* Convert symbolic operand to proper sizes for matching. */ | |
1682 | switch (guess_suffix) | |
1683 | { | |
1684 | case QWORD_MNEM_SUFFIX: | |
1685 | i.types[op] = Imm64 | Imm32S; | |
1686 | break; | |
1687 | case LONG_MNEM_SUFFIX: | |
1688 | i.types[op] = Imm32 | Imm64; | |
1689 | break; | |
1690 | case WORD_MNEM_SUFFIX: | |
1691 | i.types[op] = Imm16 | Imm32 | Imm64; | |
1692 | break; | |
1693 | break; | |
1694 | case BYTE_MNEM_SUFFIX: | |
1695 | i.types[op] = Imm8 | Imm8S | Imm16 | Imm32S | Imm32; | |
1696 | break; | |
1697 | break; | |
1698 | } | |
1699 | break; | |
773f551c | 1700 | } |
773f551c AM |
1701 | } |
1702 | } | |
1703 | ||
45288df1 AM |
1704 | if (i.disp_operands) |
1705 | { | |
1706 | /* Try to use the smallest displacement type too. */ | |
1707 | int op; | |
1708 | ||
47926f60 | 1709 | for (op = i.operands; --op >= 0;) |
45288df1 | 1710 | if ((i.types[op] & Disp) |
1ae12ab7 | 1711 | && i.op[op].disps->X_op == O_constant) |
45288df1 AM |
1712 | { |
1713 | offsetT disp = i.op[op].disps->X_add_number; | |
1714 | ||
1715 | if (i.types[op] & Disp16) | |
1716 | { | |
1717 | /* We know this operand is at most 16 bits, so | |
1718 | convert to a signed 16 bit number before trying | |
1719 | to see whether it will fit in an even smaller | |
1720 | size. */ | |
47926f60 | 1721 | |
45288df1 AM |
1722 | disp = (((disp & 0xffff) ^ 0x8000) - 0x8000); |
1723 | } | |
3e73aa7c JH |
1724 | else if (i.types[op] & Disp32) |
1725 | { | |
1726 | /* We know this operand is at most 32 bits, so convert to a | |
1727 | signed 32 bit number before trying to see whether it will | |
1728 | fit in an even smaller size. */ | |
1729 | disp &= (((offsetT) 2 << 31) - 1); | |
1730 | disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
1731 | } | |
1732 | if (flag_code == CODE_64BIT) | |
1733 | { | |
1734 | if (fits_in_signed_long (disp)) | |
1735 | i.types[op] |= Disp32S; | |
1736 | if (fits_in_unsigned_long (disp)) | |
1737 | i.types[op] |= Disp32; | |
1738 | } | |
1739 | if ((i.types[op] & (Disp32 | Disp32S | Disp16)) | |
1740 | && fits_in_signed_byte (disp)) | |
45288df1 AM |
1741 | i.types[op] |= Disp8; |
1742 | } | |
1743 | } | |
1744 | ||
252b5132 RH |
1745 | overlap0 = 0; |
1746 | overlap1 = 0; | |
1747 | overlap2 = 0; | |
1748 | found_reverse_match = 0; | |
1749 | suffix_check = (i.suffix == BYTE_MNEM_SUFFIX | |
1750 | ? No_bSuf | |
1751 | : (i.suffix == WORD_MNEM_SUFFIX | |
1752 | ? No_wSuf | |
1753 | : (i.suffix == SHORT_MNEM_SUFFIX | |
1754 | ? No_sSuf | |
1755 | : (i.suffix == LONG_MNEM_SUFFIX | |
24eab124 | 1756 | ? No_lSuf |
3e73aa7c JH |
1757 | : (i.suffix == QWORD_MNEM_SUFFIX |
1758 | ? No_qSuf | |
1759 | : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX ? No_xSuf : 0)))))); | |
252b5132 RH |
1760 | |
1761 | for (t = current_templates->start; | |
1762 | t < current_templates->end; | |
1763 | t++) | |
1764 | { | |
47926f60 | 1765 | /* Must have right number of operands. */ |
252b5132 RH |
1766 | if (i.operands != t->operands) |
1767 | continue; | |
1768 | ||
7f3f1ea2 AM |
1769 | /* Check the suffix, except for some instructions in intel mode. */ |
1770 | if ((t->opcode_modifier & suffix_check) | |
fa2255cb DN |
1771 | && !(intel_syntax |
1772 | && (t->opcode_modifier & IgnoreSize)) | |
7f3f1ea2 AM |
1773 | && !(intel_syntax |
1774 | && t->base_opcode == 0xd9 | |
ce8a8b2f AM |
1775 | && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */ |
1776 | || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */ | |
24eab124 | 1777 | continue; |
252b5132 | 1778 | |
e2914f48 | 1779 | /* Do not verify operands when there are none. */ |
252b5132 | 1780 | else if (!t->operands) |
e2914f48 JH |
1781 | { |
1782 | if (t->cpu_flags & ~cpu_arch_flags) | |
1783 | continue; | |
1784 | /* We've found a match; break out of loop. */ | |
1785 | break; | |
e5cb08ac | 1786 | } |
252b5132 RH |
1787 | |
1788 | overlap0 = i.types[0] & t->operand_types[0]; | |
1789 | switch (t->operands) | |
1790 | { | |
1791 | case 1: | |
1792 | if (!MATCH (overlap0, i.types[0], t->operand_types[0])) | |
1793 | continue; | |
1794 | break; | |
1795 | case 2: | |
1796 | case 3: | |
1797 | overlap1 = i.types[1] & t->operand_types[1]; | |
1798 | if (!MATCH (overlap0, i.types[0], t->operand_types[0]) | |
1799 | || !MATCH (overlap1, i.types[1], t->operand_types[1]) | |
1800 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], | |
1801 | t->operand_types[0], | |
1802 | overlap1, i.types[1], | |
1803 | t->operand_types[1])) | |
1804 | { | |
47926f60 | 1805 | /* Check if other direction is valid ... */ |
252b5132 RH |
1806 | if ((t->opcode_modifier & (D|FloatD)) == 0) |
1807 | continue; | |
1808 | ||
47926f60 | 1809 | /* Try reversing direction of operands. */ |
252b5132 RH |
1810 | overlap0 = i.types[0] & t->operand_types[1]; |
1811 | overlap1 = i.types[1] & t->operand_types[0]; | |
1812 | if (!MATCH (overlap0, i.types[0], t->operand_types[1]) | |
1813 | || !MATCH (overlap1, i.types[1], t->operand_types[0]) | |
1814 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], | |
1815 | t->operand_types[1], | |
1816 | overlap1, i.types[1], | |
1817 | t->operand_types[0])) | |
1818 | { | |
47926f60 | 1819 | /* Does not match either direction. */ |
252b5132 RH |
1820 | continue; |
1821 | } | |
1822 | /* found_reverse_match holds which of D or FloatDR | |
1823 | we've found. */ | |
1824 | found_reverse_match = t->opcode_modifier & (D|FloatDR); | |
252b5132 | 1825 | } |
47926f60 | 1826 | /* Found a forward 2 operand match here. */ |
3e73aa7c | 1827 | else if (t->operands == 3) |
252b5132 RH |
1828 | { |
1829 | /* Here we make use of the fact that there are no | |
1830 | reverse match 3 operand instructions, and all 3 | |
1831 | operand instructions only need to be checked for | |
1832 | register consistency between operands 2 and 3. */ | |
1833 | overlap2 = i.types[2] & t->operand_types[2]; | |
1834 | if (!MATCH (overlap2, i.types[2], t->operand_types[2]) | |
1835 | || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1], | |
1836 | t->operand_types[1], | |
1837 | overlap2, i.types[2], | |
24eab124 | 1838 | t->operand_types[2])) |
252b5132 | 1839 | |
24eab124 | 1840 | continue; |
252b5132 | 1841 | } |
47926f60 | 1842 | /* Found either forward/reverse 2 or 3 operand match here: |
ce8a8b2f | 1843 | slip through to break. */ |
252b5132 | 1844 | } |
3e73aa7c JH |
1845 | if (t->cpu_flags & ~cpu_arch_flags) |
1846 | { | |
1847 | found_reverse_match = 0; | |
1848 | continue; | |
1849 | } | |
47926f60 KH |
1850 | /* We've found a match; break out of loop. */ |
1851 | break; | |
ce8a8b2f | 1852 | } |
252b5132 | 1853 | if (t == current_templates->end) |
47926f60 KH |
1854 | { |
1855 | /* We found no match. */ | |
252b5132 RH |
1856 | as_bad (_("suffix or operands invalid for `%s'"), |
1857 | current_templates->start->name); | |
1858 | return; | |
1859 | } | |
1860 | ||
a38cf1db | 1861 | if (!quiet_warnings) |
3138f287 | 1862 | { |
a38cf1db AM |
1863 | if (!intel_syntax |
1864 | && ((i.types[0] & JumpAbsolute) | |
1865 | != (t->operand_types[0] & JumpAbsolute))) | |
1866 | { | |
1867 | as_warn (_("indirect %s without `*'"), t->name); | |
1868 | } | |
3138f287 | 1869 | |
a38cf1db AM |
1870 | if ((t->opcode_modifier & (IsPrefix|IgnoreSize)) |
1871 | == (IsPrefix|IgnoreSize)) | |
1872 | { | |
1873 | /* Warn them that a data or address size prefix doesn't | |
1874 | affect assembly of the next line of code. */ | |
1875 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
1876 | } | |
252b5132 RH |
1877 | } |
1878 | ||
1879 | /* Copy the template we found. */ | |
1880 | i.tm = *t; | |
1881 | if (found_reverse_match) | |
1882 | { | |
7f3f1ea2 AM |
1883 | /* If we found a reverse match we must alter the opcode |
1884 | direction bit. found_reverse_match holds bits to change | |
1885 | (different for int & float insns). */ | |
1886 | ||
1887 | i.tm.base_opcode ^= found_reverse_match; | |
1888 | ||
252b5132 RH |
1889 | i.tm.operand_types[0] = t->operand_types[1]; |
1890 | i.tm.operand_types[1] = t->operand_types[0]; | |
1891 | } | |
1892 | ||
d0b47220 | 1893 | /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */ |
e5cb08ac KH |
1894 | if (SYSV386_COMPAT |
1895 | && intel_syntax | |
1896 | && (i.tm.base_opcode & 0xfffffde0) == 0xdce0) | |
1897 | i.tm.base_opcode ^= FloatR; | |
252b5132 RH |
1898 | |
1899 | if (i.tm.opcode_modifier & FWait) | |
1900 | if (! add_prefix (FWAIT_OPCODE)) | |
1901 | return; | |
1902 | ||
ce8a8b2f | 1903 | /* Check string instruction segment overrides. */ |
252b5132 RH |
1904 | if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0) |
1905 | { | |
1906 | int mem_op = (i.types[0] & AnyMem) ? 0 : 1; | |
1907 | if ((i.tm.operand_types[mem_op] & EsSeg) != 0) | |
1908 | { | |
1909 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
1910 | { | |
1911 | as_bad (_("`%s' operand %d must use `%%es' segment"), | |
1912 | i.tm.name, | |
1913 | mem_op + 1); | |
1914 | return; | |
1915 | } | |
1916 | /* There's only ever one segment override allowed per instruction. | |
1917 | This instruction possibly has a legal segment override on the | |
1918 | second operand, so copy the segment to where non-string | |
1919 | instructions store it, allowing common code. */ | |
1920 | i.seg[0] = i.seg[1]; | |
1921 | } | |
1922 | else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0) | |
1923 | { | |
1924 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
1925 | { | |
1926 | as_bad (_("`%s' operand %d must use `%%es' segment"), | |
1927 | i.tm.name, | |
1928 | mem_op + 2); | |
1929 | return; | |
1930 | } | |
1931 | } | |
1932 | } | |
1933 | ||
1934 | /* If matched instruction specifies an explicit instruction mnemonic | |
1935 | suffix, use it. */ | |
3e73aa7c | 1936 | if (i.tm.opcode_modifier & (Size16 | Size32 | Size64)) |
252b5132 RH |
1937 | { |
1938 | if (i.tm.opcode_modifier & Size16) | |
1939 | i.suffix = WORD_MNEM_SUFFIX; | |
3e73aa7c JH |
1940 | else if (i.tm.opcode_modifier & Size64) |
1941 | i.suffix = QWORD_MNEM_SUFFIX; | |
252b5132 | 1942 | else |
add0c677 | 1943 | i.suffix = LONG_MNEM_SUFFIX; |
252b5132 RH |
1944 | } |
1945 | else if (i.reg_operands) | |
1946 | { | |
1947 | /* If there's no instruction mnemonic suffix we try to invent one | |
47926f60 | 1948 | based on register operands. */ |
252b5132 RH |
1949 | if (!i.suffix) |
1950 | { | |
1951 | /* We take i.suffix from the last register operand specified, | |
1952 | Destination register type is more significant than source | |
1953 | register type. */ | |
1954 | int op; | |
47926f60 | 1955 | for (op = i.operands; --op >= 0;) |
cc5ca5ce AM |
1956 | if ((i.types[op] & Reg) |
1957 | && !(i.tm.operand_types[op] & InOutPortReg)) | |
252b5132 RH |
1958 | { |
1959 | i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX : | |
1960 | (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX : | |
3e73aa7c | 1961 | (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX : |
add0c677 | 1962 | LONG_MNEM_SUFFIX); |
252b5132 RH |
1963 | break; |
1964 | } | |
1965 | } | |
1966 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
1967 | { | |
1968 | int op; | |
47926f60 | 1969 | for (op = i.operands; --op >= 0;) |
252b5132 RH |
1970 | { |
1971 | /* If this is an eight bit register, it's OK. If it's | |
1972 | the 16 or 32 bit version of an eight bit register, | |
47926f60 | 1973 | we will just use the low portion, and that's OK too. */ |
252b5132 RH |
1974 | if (i.types[op] & Reg8) |
1975 | continue; | |
1976 | ||
47926f60 | 1977 | /* movzx and movsx should not generate this warning. */ |
24eab124 AM |
1978 | if (intel_syntax |
1979 | && (i.tm.base_opcode == 0xfb7 | |
1980 | || i.tm.base_opcode == 0xfb6 | |
3e73aa7c | 1981 | || i.tm.base_opcode == 0x63 |
24eab124 AM |
1982 | || i.tm.base_opcode == 0xfbe |
1983 | || i.tm.base_opcode == 0xfbf)) | |
1984 | continue; | |
252b5132 | 1985 | |
520dc8e8 | 1986 | if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4 |
252b5132 RH |
1987 | #if 0 |
1988 | /* Check that the template allows eight bit regs | |
1989 | This kills insns such as `orb $1,%edx', which | |
1990 | maybe should be allowed. */ | |
1991 | && (i.tm.operand_types[op] & (Reg8|InOutPortReg)) | |
1992 | #endif | |
1993 | ) | |
1994 | { | |
3e73aa7c JH |
1995 | /* Prohibit these changes in the 64bit mode, since |
1996 | the lowering is more complicated. */ | |
1997 | if (flag_code == CODE_64BIT | |
1998 | && (i.tm.operand_types[op] & InOutPortReg) == 0) | |
1999 | as_bad (_("Incorrect register `%%%s' used with`%c' suffix"), | |
2000 | i.op[op].regs->reg_name, | |
2001 | i.suffix); | |
252b5132 | 2002 | #if REGISTER_WARNINGS |
a38cf1db AM |
2003 | if (!quiet_warnings |
2004 | && (i.tm.operand_types[op] & InOutPortReg) == 0) | |
252b5132 | 2005 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), |
2e98d2de AM |
2006 | (i.op[op].regs |
2007 | + (i.types[op] & Reg16 | |
2008 | ? REGNAM_AL - REGNAM_AX | |
2009 | : REGNAM_AL - REGNAM_EAX))->reg_name, | |
520dc8e8 | 2010 | i.op[op].regs->reg_name, |
252b5132 RH |
2011 | i.suffix); |
2012 | #endif | |
2013 | continue; | |
2014 | } | |
ce8a8b2f | 2015 | /* Any other register is bad. */ |
3f4438ab AM |
2016 | if (i.types[op] & (Reg | RegMMX | RegXMM |
2017 | | SReg2 | SReg3 | |
2018 | | Control | Debug | Test | |
2019 | | FloatReg | FloatAcc)) | |
252b5132 RH |
2020 | { |
2021 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
520dc8e8 | 2022 | i.op[op].regs->reg_name, |
252b5132 RH |
2023 | i.tm.name, |
2024 | i.suffix); | |
2025 | return; | |
2026 | } | |
2027 | } | |
2028 | } | |
add0c677 | 2029 | else if (i.suffix == LONG_MNEM_SUFFIX) |
252b5132 RH |
2030 | { |
2031 | int op; | |
47926f60 KH |
2032 | |
2033 | for (op = i.operands; --op >= 0;) | |
252b5132 RH |
2034 | /* Reject eight bit registers, except where the template |
2035 | requires them. (eg. movzb) */ | |
2036 | if ((i.types[op] & Reg8) != 0 | |
47926f60 | 2037 | && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) |
252b5132 RH |
2038 | { |
2039 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
520dc8e8 | 2040 | i.op[op].regs->reg_name, |
252b5132 RH |
2041 | i.tm.name, |
2042 | i.suffix); | |
2043 | return; | |
2044 | } | |
252b5132 | 2045 | /* Warn if the e prefix on a general reg is missing. */ |
3e73aa7c | 2046 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
a38cf1db | 2047 | && (i.types[op] & Reg16) != 0 |
252b5132 RH |
2048 | && (i.tm.operand_types[op] & (Reg32|Acc)) != 0) |
2049 | { | |
3e73aa7c JH |
2050 | /* Prohibit these changes in the 64bit mode, since |
2051 | the lowering is more complicated. */ | |
2052 | if (flag_code == CODE_64BIT) | |
2053 | as_bad (_("Incorrect register `%%%s' used with`%c' suffix"), | |
2054 | i.op[op].regs->reg_name, | |
2055 | i.suffix); | |
2056 | #if REGISTER_WARNINGS | |
2057 | else | |
2058 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
2e98d2de | 2059 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, |
3e73aa7c JH |
2060 | i.op[op].regs->reg_name, |
2061 | i.suffix); | |
252b5132 | 2062 | #endif |
3e73aa7c JH |
2063 | } |
2064 | /* Warn if the r prefix on a general reg is missing. */ | |
2065 | else if ((i.types[op] & Reg64) != 0 | |
2066 | && (i.tm.operand_types[op] & (Reg32|Acc)) != 0) | |
2067 | { | |
2068 | as_bad (_("Incorrect register `%%%s' used with`%c' suffix"), | |
2069 | i.op[op].regs->reg_name, | |
2070 | i.suffix); | |
2071 | } | |
2072 | } | |
2073 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
2074 | { | |
2075 | int op; | |
3e73aa7c JH |
2076 | |
2077 | for (op = i.operands; --op >= 0; ) | |
2078 | /* Reject eight bit registers, except where the template | |
2079 | requires them. (eg. movzb) */ | |
2080 | if ((i.types[op] & Reg8) != 0 | |
2081 | && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0) | |
2082 | { | |
2083 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
2084 | i.op[op].regs->reg_name, | |
2085 | i.tm.name, | |
2086 | i.suffix); | |
2087 | return; | |
2088 | } | |
2089 | /* Warn if the e prefix on a general reg is missing. */ | |
2090 | else if (((i.types[op] & Reg16) != 0 | |
2091 | || (i.types[op] & Reg32) != 0) | |
2092 | && (i.tm.operand_types[op] & (Reg32|Acc)) != 0) | |
2093 | { | |
2094 | /* Prohibit these changes in the 64bit mode, since | |
2095 | the lowering is more complicated. */ | |
2096 | as_bad (_("Incorrect register `%%%s' used with`%c' suffix"), | |
2097 | i.op[op].regs->reg_name, | |
2098 | i.suffix); | |
2099 | } | |
252b5132 RH |
2100 | } |
2101 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
2102 | { | |
2103 | int op; | |
47926f60 | 2104 | for (op = i.operands; --op >= 0;) |
252b5132 RH |
2105 | /* Reject eight bit registers, except where the template |
2106 | requires them. (eg. movzb) */ | |
2107 | if ((i.types[op] & Reg8) != 0 | |
2108 | && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0) | |
2109 | { | |
2110 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
520dc8e8 | 2111 | i.op[op].regs->reg_name, |
252b5132 RH |
2112 | i.tm.name, |
2113 | i.suffix); | |
2114 | return; | |
2115 | } | |
252b5132 | 2116 | /* Warn if the e prefix on a general reg is present. */ |
3e73aa7c | 2117 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
a38cf1db | 2118 | && (i.types[op] & Reg32) != 0 |
252b5132 RH |
2119 | && (i.tm.operand_types[op] & (Reg16|Acc)) != 0) |
2120 | { | |
3e73aa7c JH |
2121 | /* Prohibit these changes in the 64bit mode, since |
2122 | the lowering is more complicated. */ | |
2123 | if (flag_code == CODE_64BIT) | |
2124 | as_bad (_("Incorrect register `%%%s' used with`%c' suffix"), | |
2125 | i.op[op].regs->reg_name, | |
2126 | i.suffix); | |
2127 | else | |
2128 | #if REGISTER_WARNINGS | |
2129 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
2e98d2de | 2130 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, |
3e73aa7c JH |
2131 | i.op[op].regs->reg_name, |
2132 | i.suffix); | |
252b5132 | 2133 | #endif |
3e73aa7c | 2134 | } |
252b5132 | 2135 | } |
fa2255cb DN |
2136 | else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize)) |
2137 | /* Do nothing if the instruction is going to ignore the prefix. */ | |
2138 | ; | |
252b5132 | 2139 | else |
47926f60 | 2140 | abort (); |
252b5132 | 2141 | } |
eecb386c AM |
2142 | else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix) |
2143 | { | |
2144 | i.suffix = stackop_size; | |
2145 | } | |
252b5132 RH |
2146 | /* Make still unresolved immediate matches conform to size of immediate |
2147 | given in i.suffix. Note: overlap2 cannot be an immediate! */ | |
3e73aa7c | 2148 | if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S)) |
252b5132 | 2149 | && overlap0 != Imm8 && overlap0 != Imm8S |
e5cb08ac | 2150 | && overlap0 != Imm16 && overlap0 != Imm32S |
b77a7acd | 2151 | && overlap0 != Imm32 && overlap0 != Imm64) |
252b5132 RH |
2152 | { |
2153 | if (i.suffix) | |
2154 | { | |
24eab124 | 2155 | overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) : |
b77a7acd | 2156 | (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : |
3e73aa7c | 2157 | (i.suffix == QWORD_MNEM_SUFFIX ? Imm64 | Imm32S : Imm32))); |
252b5132 | 2158 | } |
3e73aa7c JH |
2159 | else if (overlap0 == (Imm16 | Imm32S | Imm32) |
2160 | || overlap0 == (Imm16 | Imm32) | |
2161 | || overlap0 == (Imm16 | Imm32S)) | |
252b5132 | 2162 | { |
24eab124 | 2163 | overlap0 = |
3e73aa7c | 2164 | ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32S; |
252b5132 | 2165 | } |
3e73aa7c JH |
2166 | if (overlap0 != Imm8 && overlap0 != Imm8S |
2167 | && overlap0 != Imm16 && overlap0 != Imm32S | |
2168 | && overlap0 != Imm32 && overlap0 != Imm64) | |
252b5132 RH |
2169 | { |
2170 | as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")); | |
2171 | return; | |
2172 | } | |
2173 | } | |
3e73aa7c | 2174 | if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32)) |
252b5132 | 2175 | && overlap1 != Imm8 && overlap1 != Imm8S |
e5cb08ac | 2176 | && overlap1 != Imm16 && overlap1 != Imm32S |
b77a7acd | 2177 | && overlap1 != Imm32 && overlap1 != Imm64) |
252b5132 RH |
2178 | { |
2179 | if (i.suffix) | |
2180 | { | |
24eab124 | 2181 | overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) : |
b77a7acd AJ |
2182 | (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : |
2183 | (i.suffix == QWORD_MNEM_SUFFIX ? Imm64 | Imm32S : Imm32))); | |
252b5132 | 2184 | } |
3e73aa7c JH |
2185 | else if (overlap1 == (Imm16 | Imm32 | Imm32S) |
2186 | || overlap1 == (Imm16 | Imm32) | |
2187 | || overlap1 == (Imm16 | Imm32S)) | |
252b5132 | 2188 | { |
24eab124 | 2189 | overlap1 = |
3e73aa7c | 2190 | ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32S; |
252b5132 | 2191 | } |
3e73aa7c JH |
2192 | if (overlap1 != Imm8 && overlap1 != Imm8S |
2193 | && overlap1 != Imm16 && overlap1 != Imm32S | |
2194 | && overlap1 != Imm32 && overlap1 != Imm64) | |
252b5132 | 2195 | { |
3e73aa7c | 2196 | as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix); |
252b5132 RH |
2197 | return; |
2198 | } | |
2199 | } | |
2200 | assert ((overlap2 & Imm) == 0); | |
2201 | ||
2202 | i.types[0] = overlap0; | |
2203 | if (overlap0 & ImplicitRegister) | |
2204 | i.reg_operands--; | |
2205 | if (overlap0 & Imm1) | |
ce8a8b2f | 2206 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 RH |
2207 | |
2208 | i.types[1] = overlap1; | |
2209 | if (overlap1 & ImplicitRegister) | |
2210 | i.reg_operands--; | |
2211 | ||
2212 | i.types[2] = overlap2; | |
2213 | if (overlap2 & ImplicitRegister) | |
2214 | i.reg_operands--; | |
2215 | ||
2216 | /* Finalize opcode. First, we change the opcode based on the operand | |
2217 | size given by i.suffix: We need not change things for byte insns. */ | |
2218 | ||
2219 | if (!i.suffix && (i.tm.opcode_modifier & W)) | |
2220 | { | |
2221 | as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction")); | |
2222 | return; | |
2223 | } | |
2224 | ||
ce8a8b2f | 2225 | /* For movzx and movsx, need to check the register type. */ |
252b5132 | 2226 | if (intel_syntax |
24eab124 | 2227 | && (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe)) |
252b5132 | 2228 | if (i.suffix && i.suffix == BYTE_MNEM_SUFFIX) |
24eab124 AM |
2229 | { |
2230 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
252b5132 | 2231 | |
520dc8e8 | 2232 | if ((i.op[1].regs->reg_type & Reg16) != 0) |
24eab124 AM |
2233 | if (!add_prefix (prefix)) |
2234 | return; | |
2235 | } | |
252b5132 RH |
2236 | |
2237 | if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX) | |
2238 | { | |
2239 | /* It's not a byte, select word/dword operation. */ | |
2240 | if (i.tm.opcode_modifier & W) | |
2241 | { | |
2242 | if (i.tm.opcode_modifier & ShortForm) | |
2243 | i.tm.base_opcode |= 8; | |
2244 | else | |
2245 | i.tm.base_opcode |= 1; | |
2246 | } | |
2247 | /* Now select between word & dword operations via the operand | |
2248 | size prefix, except for instructions that will ignore this | |
2249 | prefix anyway. */ | |
3e73aa7c JH |
2250 | if (i.suffix != QWORD_MNEM_SUFFIX |
2251 | && (i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) | |
252b5132 RH |
2252 | && !(i.tm.opcode_modifier & IgnoreSize)) |
2253 | { | |
2254 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
2255 | if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */ | |
2256 | prefix = ADDR_PREFIX_OPCODE; | |
2257 | ||
2258 | if (! add_prefix (prefix)) | |
2259 | return; | |
2260 | } | |
3e73aa7c JH |
2261 | |
2262 | /* Set mode64 for an operand. */ | |
2263 | if (i.suffix == QWORD_MNEM_SUFFIX | |
2264 | && !(i.tm.opcode_modifier & NoRex64)) | |
b96d3a20 | 2265 | { |
3e73aa7c | 2266 | i.rex.mode64 = 1; |
b96d3a20 JH |
2267 | if (flag_code < CODE_64BIT) |
2268 | { | |
e5cb08ac KH |
2269 | as_bad (_("64bit operations available only in 64bit modes.")); |
2270 | return; | |
b96d3a20 JH |
2271 | } |
2272 | } | |
3e73aa7c | 2273 | |
252b5132 | 2274 | /* Size floating point instruction. */ |
f16b83df | 2275 | if (i.suffix == LONG_MNEM_SUFFIX) |
252b5132 RH |
2276 | { |
2277 | if (i.tm.opcode_modifier & FloatMF) | |
2278 | i.tm.base_opcode ^= 4; | |
2279 | } | |
252b5132 RH |
2280 | } |
2281 | ||
3f4438ab | 2282 | if (i.tm.opcode_modifier & ImmExt) |
252b5132 | 2283 | { |
3f4438ab AM |
2284 | /* These AMD 3DNow! and Intel Katmai New Instructions have an |
2285 | opcode suffix which is coded in the same place as an 8-bit | |
2286 | immediate field would be. Here we fake an 8-bit immediate | |
2287 | operand from the opcode suffix stored in tm.extension_opcode. */ | |
252b5132 RH |
2288 | |
2289 | expressionS *exp; | |
2290 | ||
47926f60 | 2291 | assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS); |
252b5132 RH |
2292 | |
2293 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 2294 | i.op[i.operands].imms = exp; |
252b5132 RH |
2295 | i.types[i.operands++] = Imm8; |
2296 | exp->X_op = O_constant; | |
2297 | exp->X_add_number = i.tm.extension_opcode; | |
2298 | i.tm.extension_opcode = None; | |
2299 | } | |
2300 | ||
47926f60 | 2301 | /* For insns with operands there are more diddles to do to the opcode. */ |
252b5132 RH |
2302 | if (i.operands) |
2303 | { | |
24eab124 | 2304 | /* Default segment register this instruction will use |
252b5132 RH |
2305 | for memory accesses. 0 means unknown. |
2306 | This is only for optimizing out unnecessary segment overrides. */ | |
2307 | const seg_entry *default_seg = 0; | |
2308 | ||
252b5132 RH |
2309 | /* The imul $imm, %reg instruction is converted into |
2310 | imul $imm, %reg, %reg, and the clr %reg instruction | |
2311 | is converted into xor %reg, %reg. */ | |
2312 | if (i.tm.opcode_modifier & regKludge) | |
2313 | { | |
2314 | unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1; | |
47926f60 KH |
2315 | /* Pretend we saw the extra register operand. */ |
2316 | assert (i.op[first_reg_op + 1].regs == 0); | |
2317 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; | |
2318 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
252b5132 RH |
2319 | i.reg_operands = 2; |
2320 | } | |
2321 | ||
2322 | if (i.tm.opcode_modifier & ShortForm) | |
2323 | { | |
47926f60 | 2324 | /* The register or float register operand is in operand 0 or 1. */ |
252b5132 | 2325 | unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1; |
47926f60 | 2326 | /* Register goes in low 3 bits of opcode. */ |
520dc8e8 | 2327 | i.tm.base_opcode |= i.op[op].regs->reg_num; |
3e73aa7c | 2328 | if (i.op[op].regs->reg_flags & RegRex) |
e5cb08ac | 2329 | i.rex.extZ = 1; |
a38cf1db | 2330 | if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) |
252b5132 RH |
2331 | { |
2332 | /* Warn about some common errors, but press on regardless. | |
2333 | The first case can be generated by gcc (<= 2.8.1). */ | |
2334 | if (i.operands == 2) | |
2335 | { | |
47926f60 | 2336 | /* Reversed arguments on faddp, fsubp, etc. */ |
252b5132 | 2337 | as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name, |
520dc8e8 AM |
2338 | i.op[1].regs->reg_name, |
2339 | i.op[0].regs->reg_name); | |
252b5132 RH |
2340 | } |
2341 | else | |
2342 | { | |
47926f60 | 2343 | /* Extraneous `l' suffix on fp insn. */ |
252b5132 | 2344 | as_warn (_("translating to `%s %%%s'"), i.tm.name, |
520dc8e8 | 2345 | i.op[0].regs->reg_name); |
252b5132 RH |
2346 | } |
2347 | } | |
2348 | } | |
2349 | else if (i.tm.opcode_modifier & Modrm) | |
2350 | { | |
2351 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
2352 | must be put into the modrm byte). | |
2353 | Now, we make the modrm & index base bytes based on all the | |
47926f60 | 2354 | info we've collected. */ |
252b5132 RH |
2355 | |
2356 | /* i.reg_operands MUST be the number of real register operands; | |
47926f60 | 2357 | implicit registers do not count. */ |
252b5132 RH |
2358 | if (i.reg_operands == 2) |
2359 | { | |
2360 | unsigned int source, dest; | |
2361 | source = ((i.types[0] | |
3f4438ab AM |
2362 | & (Reg | RegMMX | RegXMM |
2363 | | SReg2 | SReg3 | |
2364 | | Control | Debug | Test)) | |
252b5132 RH |
2365 | ? 0 : 1); |
2366 | dest = source + 1; | |
2367 | ||
252b5132 | 2368 | i.rm.mode = 3; |
3f4438ab AM |
2369 | /* One of the register operands will be encoded in the |
2370 | i.tm.reg field, the other in the combined i.tm.mode | |
2371 | and i.tm.regmem fields. If no form of this | |
2372 | instruction supports a memory destination operand, | |
2373 | then we assume the source operand may sometimes be | |
2374 | a memory operand and so we need to store the | |
2375 | destination in the i.rm.reg field. */ | |
2376 | if ((i.tm.operand_types[dest] & AnyMem) == 0) | |
252b5132 | 2377 | { |
520dc8e8 AM |
2378 | i.rm.reg = i.op[dest].regs->reg_num; |
2379 | i.rm.regmem = i.op[source].regs->reg_num; | |
3e73aa7c | 2380 | if (i.op[dest].regs->reg_flags & RegRex) |
e5cb08ac | 2381 | i.rex.extX = 1; |
3e73aa7c | 2382 | if (i.op[source].regs->reg_flags & RegRex) |
e5cb08ac | 2383 | i.rex.extZ = 1; |
252b5132 RH |
2384 | } |
2385 | else | |
2386 | { | |
520dc8e8 AM |
2387 | i.rm.reg = i.op[source].regs->reg_num; |
2388 | i.rm.regmem = i.op[dest].regs->reg_num; | |
3e73aa7c | 2389 | if (i.op[dest].regs->reg_flags & RegRex) |
e5cb08ac | 2390 | i.rex.extZ = 1; |
3e73aa7c | 2391 | if (i.op[source].regs->reg_flags & RegRex) |
e5cb08ac | 2392 | i.rex.extX = 1; |
252b5132 RH |
2393 | } |
2394 | } | |
2395 | else | |
47926f60 | 2396 | { /* If it's not 2 reg operands... */ |
252b5132 RH |
2397 | if (i.mem_operands) |
2398 | { | |
2399 | unsigned int fake_zero_displacement = 0; | |
2400 | unsigned int op = ((i.types[0] & AnyMem) | |
2401 | ? 0 | |
2402 | : (i.types[1] & AnyMem) ? 1 : 2); | |
2403 | ||
2404 | default_seg = &ds; | |
2405 | ||
2406 | if (! i.base_reg) | |
2407 | { | |
2408 | i.rm.mode = 0; | |
2409 | if (! i.disp_operands) | |
2410 | fake_zero_displacement = 1; | |
2411 | if (! i.index_reg) | |
2412 | { | |
47926f60 | 2413 | /* Operand is just <disp> */ |
3e73aa7c | 2414 | if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) |
252b5132 RH |
2415 | { |
2416 | i.rm.regmem = NO_BASE_REGISTER_16; | |
2417 | i.types[op] &= ~Disp; | |
2418 | i.types[op] |= Disp16; | |
2419 | } | |
3e73aa7c | 2420 | else if (flag_code != CODE_64BIT) |
252b5132 RH |
2421 | { |
2422 | i.rm.regmem = NO_BASE_REGISTER; | |
2423 | i.types[op] &= ~Disp; | |
2424 | i.types[op] |= Disp32; | |
2425 | } | |
3e73aa7c JH |
2426 | else |
2427 | { | |
e5cb08ac KH |
2428 | /* 64bit mode overwrites the 32bit |
2429 | absolute addressing by RIP relative | |
2430 | addressing and absolute addressing | |
2431 | is encoded by one of the redundant | |
2432 | SIB forms. */ | |
3e73aa7c JH |
2433 | |
2434 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2435 | i.sib.base = NO_BASE_REGISTER; | |
2436 | i.sib.index = NO_INDEX_REGISTER; | |
2437 | i.types[op] &= ~Disp; | |
2438 | i.types[op] |= Disp32S; | |
2439 | } | |
252b5132 | 2440 | } |
47926f60 | 2441 | else /* ! i.base_reg && i.index_reg */ |
252b5132 RH |
2442 | { |
2443 | i.sib.index = i.index_reg->reg_num; | |
2444 | i.sib.base = NO_BASE_REGISTER; | |
2445 | i.sib.scale = i.log2_scale_factor; | |
2446 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2447 | i.types[op] &= ~Disp; | |
3e73aa7c JH |
2448 | if (flag_code != CODE_64BIT) |
2449 | i.types[op] |= Disp32; /* Must be 32 bit */ | |
2450 | else | |
2451 | i.types[op] |= Disp32S; | |
2452 | if (i.index_reg->reg_flags & RegRex) | |
e5cb08ac | 2453 | i.rex.extY = 1; |
252b5132 RH |
2454 | } |
2455 | } | |
3e73aa7c JH |
2456 | /* RIP addressing for 64bit mode. */ |
2457 | else if (i.base_reg->reg_type == BaseIndex) | |
2458 | { | |
2459 | i.rm.regmem = NO_BASE_REGISTER; | |
2460 | i.types[op] &= ~Disp; | |
2461 | i.types[op] |= Disp32S; | |
2462 | i.flags[op] = Operand_PCrel; | |
2463 | } | |
252b5132 RH |
2464 | else if (i.base_reg->reg_type & Reg16) |
2465 | { | |
2466 | switch (i.base_reg->reg_num) | |
2467 | { | |
47926f60 | 2468 | case 3: /* (%bx) */ |
252b5132 RH |
2469 | if (! i.index_reg) |
2470 | i.rm.regmem = 7; | |
47926f60 | 2471 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ |
252b5132 RH |
2472 | i.rm.regmem = i.index_reg->reg_num - 6; |
2473 | break; | |
47926f60 | 2474 | case 5: /* (%bp) */ |
252b5132 RH |
2475 | default_seg = &ss; |
2476 | if (! i.index_reg) | |
2477 | { | |
2478 | i.rm.regmem = 6; | |
2479 | if ((i.types[op] & Disp) == 0) | |
2480 | { | |
47926f60 | 2481 | /* fake (%bp) into 0(%bp) */ |
252b5132 RH |
2482 | i.types[op] |= Disp8; |
2483 | fake_zero_displacement = 1; | |
2484 | } | |
2485 | } | |
47926f60 | 2486 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ |
252b5132 RH |
2487 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; |
2488 | break; | |
47926f60 | 2489 | default: /* (%si) -> 4 or (%di) -> 5 */ |
252b5132 RH |
2490 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; |
2491 | } | |
2492 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
2493 | } | |
3e73aa7c | 2494 | else /* i.base_reg and 32/64 bit mode */ |
252b5132 | 2495 | { |
3e73aa7c JH |
2496 | if (flag_code == CODE_64BIT |
2497 | && (i.types[op] & Disp)) | |
2498 | { | |
2499 | if (i.types[op] & Disp8) | |
2500 | i.types[op] = Disp8 | Disp32S; | |
2501 | else | |
2502 | i.types[op] = Disp32S; | |
2503 | } | |
252b5132 | 2504 | i.rm.regmem = i.base_reg->reg_num; |
3e73aa7c | 2505 | if (i.base_reg->reg_flags & RegRex) |
e5cb08ac | 2506 | i.rex.extZ = 1; |
252b5132 | 2507 | i.sib.base = i.base_reg->reg_num; |
3e73aa7c JH |
2508 | /* x86-64 ignores REX prefix bit here to avoid |
2509 | decoder complications. */ | |
2510 | if ((i.base_reg->reg_num & 7) == EBP_REG_NUM) | |
252b5132 RH |
2511 | { |
2512 | default_seg = &ss; | |
2513 | if (i.disp_operands == 0) | |
2514 | { | |
2515 | fake_zero_displacement = 1; | |
2516 | i.types[op] |= Disp8; | |
2517 | } | |
2518 | } | |
2519 | else if (i.base_reg->reg_num == ESP_REG_NUM) | |
2520 | { | |
2521 | default_seg = &ss; | |
2522 | } | |
2523 | i.sib.scale = i.log2_scale_factor; | |
2524 | if (! i.index_reg) | |
2525 | { | |
2526 | /* <disp>(%esp) becomes two byte modrm | |
2527 | with no index register. We've already | |
2528 | stored the code for esp in i.rm.regmem | |
2529 | ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any | |
2530 | base register besides %esp will not use | |
2531 | the extra modrm byte. */ | |
2532 | i.sib.index = NO_INDEX_REGISTER; | |
2533 | #if ! SCALE1_WHEN_NO_INDEX | |
2534 | /* Another case where we force the second | |
2535 | modrm byte. */ | |
2536 | if (i.log2_scale_factor) | |
2537 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2538 | #endif | |
2539 | } | |
2540 | else | |
2541 | { | |
2542 | i.sib.index = i.index_reg->reg_num; | |
2543 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
3e73aa7c | 2544 | if (i.index_reg->reg_flags & RegRex) |
e5cb08ac | 2545 | i.rex.extY = 1; |
252b5132 RH |
2546 | } |
2547 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
2548 | } | |
2549 | ||
2550 | if (fake_zero_displacement) | |
2551 | { | |
2552 | /* Fakes a zero displacement assuming that i.types[op] | |
47926f60 | 2553 | holds the correct displacement size. */ |
b4cac588 AM |
2554 | expressionS *exp; |
2555 | ||
520dc8e8 | 2556 | assert (i.op[op].disps == 0); |
252b5132 | 2557 | exp = &disp_expressions[i.disp_operands++]; |
520dc8e8 | 2558 | i.op[op].disps = exp; |
252b5132 RH |
2559 | exp->X_op = O_constant; |
2560 | exp->X_add_number = 0; | |
2561 | exp->X_add_symbol = (symbolS *) 0; | |
2562 | exp->X_op_symbol = (symbolS *) 0; | |
2563 | } | |
2564 | } | |
2565 | ||
2566 | /* Fill in i.rm.reg or i.rm.regmem field with register | |
2567 | operand (if any) based on i.tm.extension_opcode. | |
2568 | Again, we must be careful to make sure that | |
2569 | segment/control/debug/test/MMX registers are coded | |
47926f60 | 2570 | into the i.rm.reg field. */ |
252b5132 RH |
2571 | if (i.reg_operands) |
2572 | { | |
2573 | unsigned int op = | |
2574 | ((i.types[0] | |
3f4438ab AM |
2575 | & (Reg | RegMMX | RegXMM |
2576 | | SReg2 | SReg3 | |
2577 | | Control | Debug | Test)) | |
252b5132 RH |
2578 | ? 0 |
2579 | : ((i.types[1] | |
3f4438ab AM |
2580 | & (Reg | RegMMX | RegXMM |
2581 | | SReg2 | SReg3 | |
2582 | | Control | Debug | Test)) | |
252b5132 RH |
2583 | ? 1 |
2584 | : 2)); | |
2585 | /* If there is an extension opcode to put here, the | |
47926f60 | 2586 | register number must be put into the regmem field. */ |
252b5132 | 2587 | if (i.tm.extension_opcode != None) |
3e73aa7c JH |
2588 | { |
2589 | i.rm.regmem = i.op[op].regs->reg_num; | |
2590 | if (i.op[op].regs->reg_flags & RegRex) | |
e5cb08ac | 2591 | i.rex.extZ = 1; |
3e73aa7c | 2592 | } |
252b5132 | 2593 | else |
3e73aa7c JH |
2594 | { |
2595 | i.rm.reg = i.op[op].regs->reg_num; | |
2596 | if (i.op[op].regs->reg_flags & RegRex) | |
e5cb08ac | 2597 | i.rex.extX = 1; |
3e73aa7c | 2598 | } |
252b5132 RH |
2599 | |
2600 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 | |
2601 | we must set it to 3 to indicate this is a register | |
2602 | operand in the regmem field. */ | |
2603 | if (!i.mem_operands) | |
2604 | i.rm.mode = 3; | |
2605 | } | |
2606 | ||
47926f60 | 2607 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
252b5132 RH |
2608 | if (i.tm.extension_opcode != None) |
2609 | i.rm.reg = i.tm.extension_opcode; | |
2610 | } | |
2611 | } | |
2612 | else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm)) | |
2613 | { | |
47926f60 KH |
2614 | if (i.tm.base_opcode == POP_SEG_SHORT |
2615 | && i.op[0].regs->reg_num == 1) | |
252b5132 RH |
2616 | { |
2617 | as_bad (_("you can't `pop %%cs'")); | |
2618 | return; | |
2619 | } | |
520dc8e8 | 2620 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
3e73aa7c JH |
2621 | if (i.op[0].regs->reg_flags & RegRex) |
2622 | i.rex.extZ = 1; | |
252b5132 RH |
2623 | } |
2624 | else if ((i.tm.base_opcode & ~(D|W)) == MOV_AX_DISP32) | |
2625 | { | |
2626 | default_seg = &ds; | |
2627 | } | |
2628 | else if ((i.tm.opcode_modifier & IsString) != 0) | |
2629 | { | |
2630 | /* For the string instructions that allow a segment override | |
2631 | on one of their operands, the default segment is ds. */ | |
2632 | default_seg = &ds; | |
2633 | } | |
2634 | ||
2635 | /* If a segment was explicitly specified, | |
2636 | and the specified segment is not the default, | |
2637 | use an opcode prefix to select it. | |
2638 | If we never figured out what the default segment is, | |
2639 | then default_seg will be zero at this point, | |
2640 | and the specified segment prefix will always be used. */ | |
2641 | if ((i.seg[0]) && (i.seg[0] != default_seg)) | |
2642 | { | |
2643 | if (! add_prefix (i.seg[0]->seg_prefix)) | |
2644 | return; | |
2645 | } | |
2646 | } | |
a38cf1db | 2647 | else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) |
252b5132 | 2648 | { |
24eab124 AM |
2649 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ |
2650 | as_warn (_("translating to `%sp'"), i.tm.name); | |
252b5132 RH |
2651 | } |
2652 | } | |
2653 | ||
47926f60 | 2654 | /* Handle conversion of 'int $3' --> special int3 insn. */ |
520dc8e8 | 2655 | if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3) |
252b5132 RH |
2656 | { |
2657 | i.tm.base_opcode = INT3_OPCODE; | |
2658 | i.imm_operands = 0; | |
2659 | } | |
2660 | ||
2f66722d | 2661 | if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword)) |
520dc8e8 | 2662 | && i.op[0].disps->X_op == O_constant) |
2f66722d AM |
2663 | { |
2664 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
2665 | the absolute address given by the constant. Since ix86 jumps and | |
2666 | calls are pc relative, we need to generate a reloc. */ | |
520dc8e8 AM |
2667 | i.op[0].disps->X_add_symbol = &abs_symbol; |
2668 | i.op[0].disps->X_op = O_symbol; | |
2f66722d AM |
2669 | } |
2670 | ||
3e73aa7c JH |
2671 | if (i.tm.opcode_modifier & Rex64) |
2672 | i.rex.mode64 = 1; | |
2673 | ||
2674 | /* For 8bit registers we would need an empty rex prefix. | |
2675 | Also in the case instruction is already having prefix, | |
2676 | we need to convert old registers to new ones. */ | |
2677 | ||
2678 | if (((i.types[0] & Reg8) && (i.op[0].regs->reg_flags & RegRex64)) | |
2679 | || ((i.types[1] & Reg8) && (i.op[1].regs->reg_flags & RegRex64)) | |
2680 | || ((i.rex.mode64 || i.rex.extX || i.rex.extY || i.rex.extZ || i.rex.empty) | |
2681 | && ((i.types[0] & Reg8) || (i.types[1] & Reg8)))) | |
2682 | { | |
2683 | int x; | |
e5cb08ac | 2684 | i.rex.empty = 1; |
3e73aa7c JH |
2685 | for (x = 0; x < 2; x++) |
2686 | { | |
2687 | /* Look for 8bit operand that does use old registers. */ | |
2688 | if (i.types[x] & Reg8 | |
2689 | && !(i.op[x].regs->reg_flags & RegRex64)) | |
2690 | { | |
2691 | /* In case it is "hi" register, give up. */ | |
2692 | if (i.op[x].regs->reg_num > 3) | |
2693 | as_bad (_("Can't encode registers '%%%s' in the instruction requiring REX prefix.\n"), | |
2694 | i.op[x].regs->reg_name); | |
2695 | ||
2696 | /* Otherwise it is equivalent to the extended register. | |
2697 | Since the encoding don't change this is merely cosmetical | |
2698 | cleanup for debug output. */ | |
2699 | ||
2700 | i.op[x].regs = i.op[x].regs + 8; | |
2701 | } | |
2702 | } | |
2703 | } | |
2704 | ||
2705 | if (i.rex.mode64 || i.rex.extX || i.rex.extY || i.rex.extZ || i.rex.empty) | |
2706 | add_prefix (0x40 | |
2707 | | (i.rex.mode64 ? 8 : 0) | |
2708 | | (i.rex.extX ? 4 : 0) | |
2709 | | (i.rex.extY ? 2 : 0) | |
2710 | | (i.rex.extZ ? 1 : 0)); | |
2711 | ||
47926f60 | 2712 | /* We are ready to output the insn. */ |
252b5132 RH |
2713 | { |
2714 | register char *p; | |
2715 | ||
9fcc94b6 AM |
2716 | /* Tie dwarf2 debug info to the address at the start of the insn. |
2717 | We can't do this after the insn has been output as the current | |
2718 | frag may have been closed off. eg. by frag_var. */ | |
2719 | dwarf2_emit_insn (0); | |
2720 | ||
47926f60 | 2721 | /* Output jumps. */ |
252b5132 RH |
2722 | if (i.tm.opcode_modifier & Jump) |
2723 | { | |
a217f122 AM |
2724 | int code16; |
2725 | int prefix; | |
e0890092 AM |
2726 | relax_substateT subtype; |
2727 | symbolS *sym; | |
2728 | offsetT off; | |
252b5132 | 2729 | |
a217f122 | 2730 | code16 = 0; |
3e73aa7c | 2731 | if (flag_code == CODE_16BIT) |
a217f122 AM |
2732 | code16 = CODE16; |
2733 | ||
2734 | prefix = 0; | |
2735 | if (i.prefix[DATA_PREFIX]) | |
252b5132 | 2736 | { |
a217f122 | 2737 | prefix = 1; |
252b5132 | 2738 | i.prefixes -= 1; |
a217f122 | 2739 | code16 ^= CODE16; |
252b5132 | 2740 | } |
cb9401fc AM |
2741 | /* Pentium4 branch hints. */ |
2742 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
2743 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2744 | { | |
2745 | prefix++; | |
2746 | i.prefixes--; | |
2747 | } | |
3e73aa7c JH |
2748 | if (i.prefix[REX_PREFIX]) |
2749 | { | |
2750 | prefix++; | |
e5cb08ac | 2751 | i.prefixes--; |
3e73aa7c | 2752 | } |
252b5132 | 2753 | |
a217f122 | 2754 | if (i.prefixes != 0 && !intel_syntax) |
252b5132 RH |
2755 | as_warn (_("skipping prefixes on this instruction")); |
2756 | ||
2f66722d AM |
2757 | /* It's always a symbol; End frag & setup for relax. |
2758 | Make sure there is enough room in this frag for the largest | |
2759 | instruction we may generate in md_convert_frag. This is 2 | |
2760 | bytes for the opcode and room for the prefix and largest | |
2761 | displacement. */ | |
fddf5b5b | 2762 | frag_grow (prefix + 2 + 4); |
2f66722d AM |
2763 | /* Prefix and 1 opcode byte go in fr_fix. */ |
2764 | p = frag_more (prefix + 1); | |
3e73aa7c | 2765 | if (i.prefix[DATA_PREFIX]) |
2f66722d | 2766 | *p++ = DATA_PREFIX_OPCODE; |
cb9401fc AM |
2767 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE |
2768 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
2769 | *p++ = i.prefix[SEG_PREFIX]; | |
3e73aa7c JH |
2770 | if (i.prefix[REX_PREFIX]) |
2771 | *p++ = i.prefix[REX_PREFIX]; | |
2f66722d | 2772 | *p = i.tm.base_opcode; |
e0890092 AM |
2773 | |
2774 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
2775 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL); | |
2776 | else if ((cpu_arch_flags & Cpu386) != 0) | |
2777 | subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL); | |
2778 | else | |
2779 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL); | |
2780 | subtype |= code16; | |
2781 | ||
2782 | sym = i.op[0].disps->X_add_symbol; | |
2783 | off = i.op[0].disps->X_add_number; | |
2784 | ||
2785 | if (i.op[0].disps->X_op != O_constant | |
2786 | && i.op[0].disps->X_op != O_symbol) | |
2787 | { | |
2788 | /* Handle complex expressions. */ | |
2789 | sym = make_expr_symbol (i.op[0].disps); | |
2790 | off = 0; | |
2791 | } | |
2792 | ||
2793 | /* 1 possible extra opcode + 4 byte displacement go in var part. | |
ee7fcc42 | 2794 | Pass reloc in fr_var. */ |
e0890092 | 2795 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
252b5132 RH |
2796 | } |
2797 | else if (i.tm.opcode_modifier & (JumpByte | JumpDword)) | |
2798 | { | |
a217f122 | 2799 | int size; |
252b5132 | 2800 | |
a217f122 | 2801 | if (i.tm.opcode_modifier & JumpByte) |
252b5132 | 2802 | { |
a217f122 AM |
2803 | /* This is a loop or jecxz type instruction. */ |
2804 | size = 1; | |
252b5132 RH |
2805 | if (i.prefix[ADDR_PREFIX]) |
2806 | { | |
252b5132 RH |
2807 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); |
2808 | i.prefixes -= 1; | |
2809 | } | |
cb9401fc AM |
2810 | /* Pentium4 branch hints. */ |
2811 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
2812 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2813 | { | |
2814 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
2815 | i.prefixes--; | |
2816 | } | |
252b5132 RH |
2817 | } |
2818 | else | |
2819 | { | |
a217f122 AM |
2820 | int code16; |
2821 | ||
2822 | code16 = 0; | |
3e73aa7c | 2823 | if (flag_code == CODE_16BIT) |
a217f122 | 2824 | code16 = CODE16; |
252b5132 RH |
2825 | |
2826 | if (i.prefix[DATA_PREFIX]) | |
2827 | { | |
252b5132 RH |
2828 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); |
2829 | i.prefixes -= 1; | |
a217f122 | 2830 | code16 ^= CODE16; |
252b5132 | 2831 | } |
252b5132 | 2832 | |
a217f122 | 2833 | size = 4; |
252b5132 RH |
2834 | if (code16) |
2835 | size = 2; | |
2836 | } | |
2837 | ||
3e73aa7c JH |
2838 | if (i.prefix[REX_PREFIX]) |
2839 | { | |
2840 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); | |
3e73aa7c JH |
2841 | i.prefixes -= 1; |
2842 | } | |
2843 | ||
a217f122 | 2844 | if (i.prefixes != 0 && !intel_syntax) |
252b5132 RH |
2845 | as_warn (_("skipping prefixes on this instruction")); |
2846 | ||
cb9401fc AM |
2847 | p = frag_more (1 + size); |
2848 | *p++ = i.tm.base_opcode; | |
252b5132 | 2849 | |
2f66722d | 2850 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
1ae12ab7 | 2851 | i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0])); |
252b5132 RH |
2852 | } |
2853 | else if (i.tm.opcode_modifier & JumpInterSegment) | |
2854 | { | |
2855 | int size; | |
a217f122 AM |
2856 | int prefix; |
2857 | int code16; | |
252b5132 | 2858 | |
a217f122 | 2859 | code16 = 0; |
3e73aa7c | 2860 | if (flag_code == CODE_16BIT) |
a217f122 AM |
2861 | code16 = CODE16; |
2862 | ||
2863 | prefix = 0; | |
2864 | if (i.prefix[DATA_PREFIX]) | |
252b5132 | 2865 | { |
a217f122 | 2866 | prefix = 1; |
252b5132 | 2867 | i.prefixes -= 1; |
a217f122 | 2868 | code16 ^= CODE16; |
252b5132 | 2869 | } |
3e73aa7c JH |
2870 | if (i.prefix[REX_PREFIX]) |
2871 | { | |
2872 | prefix++; | |
2873 | i.prefixes -= 1; | |
2874 | } | |
252b5132 RH |
2875 | |
2876 | size = 4; | |
252b5132 | 2877 | if (code16) |
f6af82bd | 2878 | size = 2; |
252b5132 | 2879 | |
a217f122 | 2880 | if (i.prefixes != 0 && !intel_syntax) |
252b5132 RH |
2881 | as_warn (_("skipping prefixes on this instruction")); |
2882 | ||
47926f60 | 2883 | /* 1 opcode; 2 segment; offset */ |
252b5132 | 2884 | p = frag_more (prefix + 1 + 2 + size); |
3e73aa7c JH |
2885 | |
2886 | if (i.prefix[DATA_PREFIX]) | |
252b5132 | 2887 | *p++ = DATA_PREFIX_OPCODE; |
3e73aa7c JH |
2888 | |
2889 | if (i.prefix[REX_PREFIX]) | |
2890 | *p++ = i.prefix[REX_PREFIX]; | |
2891 | ||
252b5132 | 2892 | *p++ = i.tm.base_opcode; |
520dc8e8 | 2893 | if (i.op[1].imms->X_op == O_constant) |
252b5132 | 2894 | { |
847f7ad4 | 2895 | offsetT n = i.op[1].imms->X_add_number; |
252b5132 | 2896 | |
773f551c AM |
2897 | if (size == 2 |
2898 | && !fits_in_unsigned_word (n) | |
2899 | && !fits_in_signed_word (n)) | |
252b5132 RH |
2900 | { |
2901 | as_bad (_("16-bit jump out of range")); | |
2902 | return; | |
2903 | } | |
847f7ad4 | 2904 | md_number_to_chars (p, n, size); |
252b5132 RH |
2905 | } |
2906 | else | |
2907 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
1ae12ab7 | 2908 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
520dc8e8 | 2909 | if (i.op[0].imms->X_op != O_constant) |
252b5132 RH |
2910 | as_bad (_("can't handle non absolute segment in `%s'"), |
2911 | i.tm.name); | |
520dc8e8 | 2912 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); |
252b5132 RH |
2913 | } |
2914 | else | |
2915 | { | |
47926f60 | 2916 | /* Output normal instructions here. */ |
252b5132 RH |
2917 | unsigned char *q; |
2918 | ||
7bc70a8e JH |
2919 | /* All opcodes on i386 have eighter 1 or 2 bytes. We may use third |
2920 | byte for the SSE instructions to specify prefix they require. */ | |
2921 | if (i.tm.base_opcode & 0xff0000) | |
2922 | add_prefix ((i.tm.base_opcode >> 16) & 0xff); | |
2923 | ||
47926f60 | 2924 | /* The prefix bytes. */ |
252b5132 RH |
2925 | for (q = i.prefix; |
2926 | q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]); | |
2927 | q++) | |
2928 | { | |
2929 | if (*q) | |
2930 | { | |
252b5132 RH |
2931 | p = frag_more (1); |
2932 | md_number_to_chars (p, (valueT) *q, 1); | |
2933 | } | |
2934 | } | |
2935 | ||
47926f60 | 2936 | /* Now the opcode; be careful about word order here! */ |
252b5132 RH |
2937 | if (fits_in_unsigned_byte (i.tm.base_opcode)) |
2938 | { | |
252b5132 RH |
2939 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); |
2940 | } | |
7bc70a8e | 2941 | else |
252b5132 | 2942 | { |
252b5132 | 2943 | p = frag_more (2); |
47926f60 | 2944 | /* Put out high byte first: can't use md_number_to_chars! */ |
252b5132 RH |
2945 | *p++ = (i.tm.base_opcode >> 8) & 0xff; |
2946 | *p = i.tm.base_opcode & 0xff; | |
2947 | } | |
252b5132 RH |
2948 | |
2949 | /* Now the modrm byte and sib byte (if present). */ | |
2950 | if (i.tm.opcode_modifier & Modrm) | |
2951 | { | |
252b5132 RH |
2952 | p = frag_more (1); |
2953 | md_number_to_chars (p, | |
2954 | (valueT) (i.rm.regmem << 0 | |
2955 | | i.rm.reg << 3 | |
2956 | | i.rm.mode << 6), | |
2957 | 1); | |
2958 | /* If i.rm.regmem == ESP (4) | |
2959 | && i.rm.mode != (Register mode) | |
2960 | && not 16 bit | |
2961 | ==> need second modrm byte. */ | |
2962 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
2963 | && i.rm.mode != 3 | |
2964 | && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0)) | |
2965 | { | |
252b5132 RH |
2966 | p = frag_more (1); |
2967 | md_number_to_chars (p, | |
2968 | (valueT) (i.sib.base << 0 | |
2969 | | i.sib.index << 3 | |
2970 | | i.sib.scale << 6), | |
2971 | 1); | |
2972 | } | |
2973 | } | |
2974 | ||
2975 | if (i.disp_operands) | |
2976 | { | |
2977 | register unsigned int n; | |
2978 | ||
2979 | for (n = 0; n < i.operands; n++) | |
2980 | { | |
520dc8e8 | 2981 | if (i.types[n] & Disp) |
252b5132 | 2982 | { |
520dc8e8 | 2983 | if (i.op[n].disps->X_op == O_constant) |
252b5132 | 2984 | { |
847f7ad4 AM |
2985 | int size; |
2986 | offsetT val; | |
b4cac588 | 2987 | |
847f7ad4 | 2988 | size = 4; |
3e73aa7c | 2989 | if (i.types[n] & (Disp8 | Disp16 | Disp64)) |
252b5132 | 2990 | { |
b4cac588 | 2991 | size = 2; |
b4cac588 | 2992 | if (i.types[n] & Disp8) |
847f7ad4 | 2993 | size = 1; |
3e73aa7c JH |
2994 | if (i.types[n] & Disp64) |
2995 | size = 8; | |
252b5132 | 2996 | } |
847f7ad4 AM |
2997 | val = offset_in_range (i.op[n].disps->X_add_number, |
2998 | size); | |
b4cac588 | 2999 | p = frag_more (size); |
847f7ad4 | 3000 | md_number_to_chars (p, val, size); |
252b5132 | 3001 | } |
252b5132 | 3002 | else |
520dc8e8 AM |
3003 | { |
3004 | int size = 4; | |
3e73aa7c JH |
3005 | int sign = 0; |
3006 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; | |
3007 | ||
3008 | /* The PC relative address is computed relative | |
3009 | to the instruction boundary, so in case immediate | |
3010 | fields follows, we need to adjust the value. */ | |
3011 | if (pcrel && i.imm_operands) | |
3012 | { | |
3013 | int imm_size = 4; | |
3014 | register unsigned int n1; | |
3015 | ||
3016 | for (n1 = 0; n1 < i.operands; n1++) | |
3017 | if (i.types[n1] & Imm) | |
3018 | { | |
3019 | if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64)) | |
3020 | { | |
3021 | imm_size = 2; | |
3022 | if (i.types[n1] & (Imm8 | Imm8S)) | |
3023 | imm_size = 1; | |
3024 | if (i.types[n1] & Imm64) | |
3025 | imm_size = 8; | |
3026 | } | |
3027 | break; | |
3028 | } | |
3029 | /* We should find the immediate. */ | |
3030 | if (n1 == i.operands) | |
bfb32b52 | 3031 | abort (); |
3e73aa7c JH |
3032 | i.op[n].disps->X_add_number -= imm_size; |
3033 | } | |
520dc8e8 | 3034 | |
3e73aa7c JH |
3035 | if (i.types[n] & Disp32S) |
3036 | sign = 1; | |
3037 | ||
e5cb08ac | 3038 | if (i.types[n] & (Disp16 | Disp64)) |
3e73aa7c JH |
3039 | { |
3040 | size = 2; | |
3041 | if (i.types[n] & Disp64) | |
3042 | size = 8; | |
3043 | } | |
520dc8e8 | 3044 | |
520dc8e8 AM |
3045 | p = frag_more (size); |
3046 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
3e73aa7c | 3047 | i.op[n].disps, pcrel, |
1ae12ab7 | 3048 | reloc (size, pcrel, sign, i.reloc[n])); |
252b5132 RH |
3049 | } |
3050 | } | |
3051 | } | |
ce8a8b2f | 3052 | } |
252b5132 | 3053 | |
47926f60 | 3054 | /* Output immediate. */ |
252b5132 RH |
3055 | if (i.imm_operands) |
3056 | { | |
3057 | register unsigned int n; | |
3058 | ||
3059 | for (n = 0; n < i.operands; n++) | |
3060 | { | |
520dc8e8 | 3061 | if (i.types[n] & Imm) |
252b5132 | 3062 | { |
520dc8e8 | 3063 | if (i.op[n].imms->X_op == O_constant) |
252b5132 | 3064 | { |
847f7ad4 AM |
3065 | int size; |
3066 | offsetT val; | |
b4cac588 | 3067 | |
847f7ad4 | 3068 | size = 4; |
3e73aa7c | 3069 | if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64)) |
252b5132 | 3070 | { |
b4cac588 | 3071 | size = 2; |
b4cac588 | 3072 | if (i.types[n] & (Imm8 | Imm8S)) |
847f7ad4 | 3073 | size = 1; |
3e73aa7c JH |
3074 | else if (i.types[n] & Imm64) |
3075 | size = 8; | |
252b5132 | 3076 | } |
847f7ad4 AM |
3077 | val = offset_in_range (i.op[n].imms->X_add_number, |
3078 | size); | |
b4cac588 | 3079 | p = frag_more (size); |
847f7ad4 | 3080 | md_number_to_chars (p, val, size); |
252b5132 RH |
3081 | } |
3082 | else | |
ce8a8b2f AM |
3083 | { |
3084 | /* Not absolute_section. | |
3085 | Need a 32-bit fixup (don't support 8bit | |
520dc8e8 | 3086 | non-absolute imms). Try to support other |
47926f60 | 3087 | sizes ... */ |
f3c180ae | 3088 | RELOC_ENUM reloc_type; |
520dc8e8 | 3089 | int size = 4; |
3e73aa7c | 3090 | int sign = 0; |
252b5132 | 3091 | |
3e73aa7c JH |
3092 | if ((i.types[n] & (Imm32S)) |
3093 | && i.suffix == QWORD_MNEM_SUFFIX) | |
3094 | sign = 1; | |
3095 | if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64)) | |
3096 | { | |
3097 | size = 2; | |
3098 | if (i.types[n] & (Imm8 | Imm8S)) | |
3099 | size = 1; | |
3100 | if (i.types[n] & Imm64) | |
3101 | size = 8; | |
3102 | } | |
520dc8e8 | 3103 | |
252b5132 | 3104 | p = frag_more (size); |
1ae12ab7 | 3105 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
252b5132 | 3106 | #ifdef BFD_ASSEMBLER |
f6af82bd | 3107 | if (reloc_type == BFD_RELOC_32 |
252b5132 | 3108 | && GOT_symbol |
520dc8e8 AM |
3109 | && GOT_symbol == i.op[n].imms->X_add_symbol |
3110 | && (i.op[n].imms->X_op == O_symbol | |
3111 | || (i.op[n].imms->X_op == O_add | |
49309057 | 3112 | && ((symbol_get_value_expression |
520dc8e8 | 3113 | (i.op[n].imms->X_op_symbol)->X_op) |
252b5132 RH |
3114 | == O_subtract)))) |
3115 | { | |
3e73aa7c JH |
3116 | /* We don't support dynamic linking on x86-64 yet. */ |
3117 | if (flag_code == CODE_64BIT) | |
bfb32b52 | 3118 | abort (); |
f6af82bd | 3119 | reloc_type = BFD_RELOC_386_GOTPC; |
520dc8e8 | 3120 | i.op[n].imms->X_add_number += 3; |
252b5132 RH |
3121 | } |
3122 | #endif | |
3123 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
520dc8e8 | 3124 | i.op[n].imms, 0, reloc_type); |
252b5132 RH |
3125 | } |
3126 | } | |
3127 | } | |
ce8a8b2f | 3128 | } |
252b5132 RH |
3129 | } |
3130 | ||
3131 | #ifdef DEBUG386 | |
3132 | if (flag_debug) | |
3133 | { | |
3134 | pi (line, &i); | |
3135 | } | |
47926f60 | 3136 | #endif /* DEBUG386 */ |
252b5132 RH |
3137 | } |
3138 | } | |
3139 | \f | |
f3c180ae AM |
3140 | #ifndef LEX_AT |
3141 | static char *lex_got PARAMS ((RELOC_ENUM *, int *)); | |
3142 | ||
3143 | /* Parse operands of the form | |
3144 | <symbol>@GOTOFF+<nnn> | |
3145 | and similar .plt or .got references. | |
3146 | ||
3147 | If we find one, set up the correct relocation in RELOC and copy the | |
3148 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
3149 | parsing by the calling routine. Return this buffer, and if ADJUST | |
3150 | is non-null set it to the length of the string we removed from the | |
3151 | input line. Otherwise return NULL. */ | |
3152 | static char * | |
3153 | lex_got (reloc, adjust) | |
3154 | RELOC_ENUM *reloc; | |
3155 | int *adjust; | |
3156 | { | |
3157 | static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" }; | |
3158 | static const struct { | |
3159 | const char *str; | |
3160 | const RELOC_ENUM rel[NUM_FLAG_CODE]; | |
3161 | } gotrel[] = { | |
3162 | { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } }, | |
3163 | { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } }, | |
3164 | { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } }, | |
3165 | { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } } | |
3166 | }; | |
3167 | char *cp; | |
3168 | unsigned int j; | |
3169 | ||
3170 | for (cp = input_line_pointer; *cp != '@'; cp++) | |
3171 | if (is_end_of_line[(unsigned char) *cp]) | |
3172 | return NULL; | |
3173 | ||
3174 | for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++) | |
3175 | { | |
3176 | int len; | |
3177 | ||
3178 | len = strlen (gotrel[j].str); | |
28f81592 | 3179 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae AM |
3180 | { |
3181 | if (gotrel[j].rel[(unsigned int) flag_code] != 0) | |
3182 | { | |
28f81592 AM |
3183 | int first, second; |
3184 | char *tmpbuf, *past_reloc; | |
f3c180ae AM |
3185 | |
3186 | *reloc = gotrel[j].rel[(unsigned int) flag_code]; | |
28f81592 AM |
3187 | if (adjust) |
3188 | *adjust = len; | |
f3c180ae AM |
3189 | |
3190 | if (GOT_symbol == NULL) | |
3191 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
3192 | ||
3193 | /* Replace the relocation token with ' ', so that | |
3194 | errors like foo@GOTOFF1 will be detected. */ | |
28f81592 AM |
3195 | |
3196 | /* The length of the first part of our input line. */ | |
f3c180ae | 3197 | first = cp - input_line_pointer; |
28f81592 AM |
3198 | |
3199 | /* The second part goes from after the reloc token until | |
3200 | (and including) an end_of_line char. Don't use strlen | |
3201 | here as the end_of_line char may not be a NUL. */ | |
3202 | past_reloc = cp + 1 + len; | |
3203 | for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; ) | |
3204 | ; | |
3205 | second = cp - past_reloc; | |
3206 | ||
3207 | /* Allocate and copy string. The trailing NUL shouldn't | |
3208 | be necessary, but be safe. */ | |
3209 | tmpbuf = xmalloc (first + second + 2); | |
f3c180ae AM |
3210 | memcpy (tmpbuf, input_line_pointer, first); |
3211 | tmpbuf[first] = ' '; | |
28f81592 AM |
3212 | memcpy (tmpbuf + first + 1, past_reloc, second); |
3213 | tmpbuf[first + second + 1] = '\0'; | |
f3c180ae AM |
3214 | return tmpbuf; |
3215 | } | |
3216 | ||
3217 | as_bad (_("@%s reloc is not supported in %s bit mode"), | |
3218 | gotrel[j].str, mode_name[(unsigned int) flag_code]); | |
3219 | return NULL; | |
3220 | } | |
3221 | } | |
3222 | ||
3223 | /* Might be a symbol version string. Don't as_bad here. */ | |
3224 | return NULL; | |
3225 | } | |
3226 | ||
3227 | /* x86_cons_fix_new is called via the expression parsing code when a | |
3228 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
3229 | static RELOC_ENUM got_reloc = NO_RELOC; | |
3230 | ||
3231 | void | |
3232 | x86_cons_fix_new (frag, off, len, exp) | |
3233 | fragS *frag; | |
3234 | unsigned int off; | |
3235 | unsigned int len; | |
3236 | expressionS *exp; | |
3237 | { | |
3238 | RELOC_ENUM r = reloc (len, 0, 0, got_reloc); | |
3239 | got_reloc = NO_RELOC; | |
3240 | fix_new_exp (frag, off, len, exp, 0, r); | |
3241 | } | |
3242 | ||
3243 | void | |
3244 | x86_cons (exp, size) | |
3245 | expressionS *exp; | |
3246 | int size; | |
3247 | { | |
3248 | if (size == 4) | |
3249 | { | |
3250 | /* Handle @GOTOFF and the like in an expression. */ | |
3251 | char *save; | |
3252 | char *gotfree_input_line; | |
3253 | int adjust; | |
3254 | ||
3255 | save = input_line_pointer; | |
3256 | gotfree_input_line = lex_got (&got_reloc, &adjust); | |
3257 | if (gotfree_input_line) | |
3258 | input_line_pointer = gotfree_input_line; | |
3259 | ||
3260 | expression (exp); | |
3261 | ||
3262 | if (gotfree_input_line) | |
3263 | { | |
3264 | /* expression () has merrily parsed up to the end of line, | |
3265 | or a comma - in the wrong buffer. Transfer how far | |
3266 | input_line_pointer has moved to the right buffer. */ | |
3267 | input_line_pointer = (save | |
3268 | + (input_line_pointer - gotfree_input_line) | |
3269 | + adjust); | |
3270 | free (gotfree_input_line); | |
3271 | } | |
3272 | } | |
3273 | else | |
3274 | expression (exp); | |
3275 | } | |
3276 | #endif | |
3277 | ||
252b5132 RH |
3278 | static int i386_immediate PARAMS ((char *)); |
3279 | ||
3280 | static int | |
3281 | i386_immediate (imm_start) | |
3282 | char *imm_start; | |
3283 | { | |
3284 | char *save_input_line_pointer; | |
f3c180ae AM |
3285 | #ifndef LEX_AT |
3286 | char *gotfree_input_line; | |
3287 | #endif | |
252b5132 | 3288 | segT exp_seg = 0; |
47926f60 | 3289 | expressionS *exp; |
252b5132 RH |
3290 | |
3291 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
3292 | { | |
d0b47220 | 3293 | as_bad (_("only 1 or 2 immediate operands are allowed")); |
252b5132 RH |
3294 | return 0; |
3295 | } | |
3296 | ||
3297 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 3298 | i.op[this_operand].imms = exp; |
252b5132 RH |
3299 | |
3300 | if (is_space_char (*imm_start)) | |
3301 | ++imm_start; | |
3302 | ||
3303 | save_input_line_pointer = input_line_pointer; | |
3304 | input_line_pointer = imm_start; | |
3305 | ||
3306 | #ifndef LEX_AT | |
f3c180ae AM |
3307 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL); |
3308 | if (gotfree_input_line) | |
3309 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
3310 | #endif |
3311 | ||
3312 | exp_seg = expression (exp); | |
3313 | ||
83183c0c | 3314 | SKIP_WHITESPACE (); |
252b5132 | 3315 | if (*input_line_pointer) |
f3c180ae | 3316 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
3317 | |
3318 | input_line_pointer = save_input_line_pointer; | |
f3c180ae AM |
3319 | #ifndef LEX_AT |
3320 | if (gotfree_input_line) | |
3321 | free (gotfree_input_line); | |
3322 | #endif | |
252b5132 | 3323 | |
2daf4fd8 | 3324 | if (exp->X_op == O_absent || exp->X_op == O_big) |
252b5132 | 3325 | { |
47926f60 | 3326 | /* Missing or bad expr becomes absolute 0. */ |
d0b47220 | 3327 | as_bad (_("missing or invalid immediate expression `%s' taken as 0"), |
24eab124 | 3328 | imm_start); |
252b5132 RH |
3329 | exp->X_op = O_constant; |
3330 | exp->X_add_number = 0; | |
3331 | exp->X_add_symbol = (symbolS *) 0; | |
3332 | exp->X_op_symbol = (symbolS *) 0; | |
252b5132 | 3333 | } |
3e73aa7c | 3334 | else if (exp->X_op == O_constant) |
252b5132 | 3335 | { |
47926f60 | 3336 | /* Size it properly later. */ |
3e73aa7c JH |
3337 | i.types[this_operand] |= Imm64; |
3338 | /* If BFD64, sign extend val. */ | |
3339 | if (!use_rela_relocations) | |
3340 | if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) | |
3341 | exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 3342 | } |
4c63da97 | 3343 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
47926f60 | 3344 | else if (1 |
4c63da97 | 3345 | #ifdef BFD_ASSEMBLER |
47926f60 | 3346 | && OUTPUT_FLAVOR == bfd_target_aout_flavour |
4c63da97 | 3347 | #endif |
47926f60 | 3348 | && exp_seg != text_section |
24eab124 AM |
3349 | && exp_seg != data_section |
3350 | && exp_seg != bss_section | |
3351 | && exp_seg != undefined_section | |
252b5132 | 3352 | #ifdef BFD_ASSEMBLER |
24eab124 | 3353 | && !bfd_is_com_section (exp_seg) |
252b5132 | 3354 | #endif |
24eab124 | 3355 | ) |
252b5132 | 3356 | { |
4c63da97 | 3357 | #ifdef BFD_ASSEMBLER |
d0b47220 | 3358 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
4c63da97 | 3359 | #else |
d0b47220 | 3360 | as_bad (_("unimplemented segment type %d in operand"), exp_seg); |
4c63da97 | 3361 | #endif |
252b5132 RH |
3362 | return 0; |
3363 | } | |
3364 | #endif | |
3365 | else | |
3366 | { | |
3367 | /* This is an address. The size of the address will be | |
24eab124 | 3368 | determined later, depending on destination register, |
3e73aa7c JH |
3369 | suffix, or the default for the section. */ |
3370 | i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64; | |
252b5132 RH |
3371 | } |
3372 | ||
3373 | return 1; | |
3374 | } | |
3375 | ||
551c1ca1 | 3376 | static char *i386_scale PARAMS ((char *)); |
252b5132 | 3377 | |
551c1ca1 | 3378 | static char * |
252b5132 RH |
3379 | i386_scale (scale) |
3380 | char *scale; | |
3381 | { | |
551c1ca1 AM |
3382 | offsetT val; |
3383 | char *save = input_line_pointer; | |
252b5132 | 3384 | |
551c1ca1 AM |
3385 | input_line_pointer = scale; |
3386 | val = get_absolute_expression (); | |
3387 | ||
3388 | switch (val) | |
252b5132 | 3389 | { |
551c1ca1 AM |
3390 | case 0: |
3391 | case 1: | |
252b5132 RH |
3392 | i.log2_scale_factor = 0; |
3393 | break; | |
551c1ca1 | 3394 | case 2: |
252b5132 RH |
3395 | i.log2_scale_factor = 1; |
3396 | break; | |
551c1ca1 | 3397 | case 4: |
252b5132 RH |
3398 | i.log2_scale_factor = 2; |
3399 | break; | |
551c1ca1 | 3400 | case 8: |
252b5132 RH |
3401 | i.log2_scale_factor = 3; |
3402 | break; | |
3403 | default: | |
252b5132 | 3404 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), |
24eab124 | 3405 | scale); |
551c1ca1 AM |
3406 | input_line_pointer = save; |
3407 | return NULL; | |
252b5132 RH |
3408 | } |
3409 | if (i.log2_scale_factor != 0 && ! i.index_reg) | |
3410 | { | |
3411 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 3412 | 1 << i.log2_scale_factor); |
252b5132 RH |
3413 | #if SCALE1_WHEN_NO_INDEX |
3414 | i.log2_scale_factor = 0; | |
3415 | #endif | |
3416 | } | |
551c1ca1 AM |
3417 | scale = input_line_pointer; |
3418 | input_line_pointer = save; | |
3419 | return scale; | |
252b5132 RH |
3420 | } |
3421 | ||
3422 | static int i386_displacement PARAMS ((char *, char *)); | |
3423 | ||
3424 | static int | |
3425 | i386_displacement (disp_start, disp_end) | |
3426 | char *disp_start; | |
3427 | char *disp_end; | |
3428 | { | |
3429 | register expressionS *exp; | |
3430 | segT exp_seg = 0; | |
3431 | char *save_input_line_pointer; | |
f3c180ae AM |
3432 | #ifndef LEX_AT |
3433 | char *gotfree_input_line; | |
3434 | #endif | |
252b5132 RH |
3435 | int bigdisp = Disp32; |
3436 | ||
3e73aa7c | 3437 | if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) |
252b5132 | 3438 | bigdisp = Disp16; |
3e73aa7c JH |
3439 | if (flag_code == CODE_64BIT) |
3440 | bigdisp = Disp64; | |
252b5132 RH |
3441 | i.types[this_operand] |= bigdisp; |
3442 | ||
3443 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 3444 | i.op[this_operand].disps = exp; |
252b5132 RH |
3445 | i.disp_operands++; |
3446 | save_input_line_pointer = input_line_pointer; | |
3447 | input_line_pointer = disp_start; | |
3448 | END_STRING_AND_SAVE (disp_end); | |
3449 | ||
3450 | #ifndef GCC_ASM_O_HACK | |
3451 | #define GCC_ASM_O_HACK 0 | |
3452 | #endif | |
3453 | #if GCC_ASM_O_HACK | |
3454 | END_STRING_AND_SAVE (disp_end + 1); | |
3455 | if ((i.types[this_operand] & BaseIndex) != 0 | |
24eab124 | 3456 | && displacement_string_end[-1] == '+') |
252b5132 RH |
3457 | { |
3458 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
3459 | constraint within gcc asm statements. |
3460 | For instance: | |
3461 | ||
3462 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
3463 | __asm__ __volatile__ ( \ | |
3464 | "movw %w2,%0\n\t" \ | |
3465 | "movw %w1,2+%0\n\t" \ | |
3466 | "rorl $16,%1\n\t" \ | |
3467 | "movb %b1,4+%0\n\t" \ | |
3468 | "movb %4,5+%0\n\t" \ | |
3469 | "movb $0,6+%0\n\t" \ | |
3470 | "movb %h1,7+%0\n\t" \ | |
3471 | "rorl $16,%1" \ | |
3472 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
3473 | ||
3474 | This works great except that the output assembler ends | |
3475 | up looking a bit weird if it turns out that there is | |
3476 | no offset. You end up producing code that looks like: | |
3477 | ||
3478 | #APP | |
3479 | movw $235,(%eax) | |
3480 | movw %dx,2+(%eax) | |
3481 | rorl $16,%edx | |
3482 | movb %dl,4+(%eax) | |
3483 | movb $137,5+(%eax) | |
3484 | movb $0,6+(%eax) | |
3485 | movb %dh,7+(%eax) | |
3486 | rorl $16,%edx | |
3487 | #NO_APP | |
3488 | ||
47926f60 | 3489 | So here we provide the missing zero. */ |
24eab124 AM |
3490 | |
3491 | *displacement_string_end = '0'; | |
252b5132 RH |
3492 | } |
3493 | #endif | |
3494 | #ifndef LEX_AT | |
f3c180ae AM |
3495 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL); |
3496 | if (gotfree_input_line) | |
3497 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
3498 | #endif |
3499 | ||
24eab124 | 3500 | exp_seg = expression (exp); |
252b5132 | 3501 | |
636c26b0 AM |
3502 | SKIP_WHITESPACE (); |
3503 | if (*input_line_pointer) | |
3504 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
3505 | #if GCC_ASM_O_HACK | |
3506 | RESTORE_END_STRING (disp_end + 1); | |
3507 | #endif | |
3508 | RESTORE_END_STRING (disp_end); | |
3509 | input_line_pointer = save_input_line_pointer; | |
3510 | #ifndef LEX_AT | |
3511 | if (gotfree_input_line) | |
3512 | free (gotfree_input_line); | |
3513 | #endif | |
3514 | ||
252b5132 | 3515 | #ifdef BFD_ASSEMBLER |
24eab124 AM |
3516 | /* We do this to make sure that the section symbol is in |
3517 | the symbol table. We will ultimately change the relocation | |
47926f60 | 3518 | to be relative to the beginning of the section. */ |
1ae12ab7 AM |
3519 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
3520 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) | |
24eab124 | 3521 | { |
636c26b0 AM |
3522 | if (exp->X_op != O_symbol) |
3523 | { | |
3524 | as_bad (_("bad expression used with @%s"), | |
3525 | (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL | |
3526 | ? "GOTPCREL" | |
3527 | : "GOTOFF")); | |
3528 | return 0; | |
3529 | } | |
3530 | ||
e5cb08ac | 3531 | if (S_IS_LOCAL (exp->X_add_symbol) |
24eab124 AM |
3532 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section) |
3533 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); | |
24eab124 AM |
3534 | exp->X_op = O_subtract; |
3535 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 AM |
3536 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
3537 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; | |
23df1078 | 3538 | else |
1ae12ab7 | 3539 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 3540 | } |
252b5132 RH |
3541 | #endif |
3542 | ||
2daf4fd8 AM |
3543 | if (exp->X_op == O_absent || exp->X_op == O_big) |
3544 | { | |
47926f60 | 3545 | /* Missing or bad expr becomes absolute 0. */ |
d0b47220 | 3546 | as_bad (_("missing or invalid displacement expression `%s' taken as 0"), |
2daf4fd8 AM |
3547 | disp_start); |
3548 | exp->X_op = O_constant; | |
3549 | exp->X_add_number = 0; | |
3550 | exp->X_add_symbol = (symbolS *) 0; | |
3551 | exp->X_op_symbol = (symbolS *) 0; | |
3552 | } | |
3553 | ||
4c63da97 | 3554 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
45288df1 | 3555 | if (exp->X_op != O_constant |
4c63da97 | 3556 | #ifdef BFD_ASSEMBLER |
45288df1 | 3557 | && OUTPUT_FLAVOR == bfd_target_aout_flavour |
4c63da97 | 3558 | #endif |
45288df1 AM |
3559 | && exp_seg != text_section |
3560 | && exp_seg != data_section | |
3561 | && exp_seg != bss_section | |
3562 | && exp_seg != undefined_section) | |
24eab124 | 3563 | { |
4c63da97 | 3564 | #ifdef BFD_ASSEMBLER |
d0b47220 | 3565 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
4c63da97 | 3566 | #else |
d0b47220 | 3567 | as_bad (_("unimplemented segment type %d in operand"), exp_seg); |
4c63da97 | 3568 | #endif |
24eab124 AM |
3569 | return 0; |
3570 | } | |
252b5132 | 3571 | #endif |
3e73aa7c JH |
3572 | else if (flag_code == CODE_64BIT) |
3573 | i.types[this_operand] |= Disp32S | Disp32; | |
252b5132 RH |
3574 | return 1; |
3575 | } | |
3576 | ||
e5cb08ac | 3577 | static int i386_index_check PARAMS ((const char *)); |
252b5132 | 3578 | |
eecb386c | 3579 | /* Make sure the memory operand we've been dealt is valid. |
47926f60 KH |
3580 | Return 1 on success, 0 on a failure. */ |
3581 | ||
252b5132 | 3582 | static int |
eecb386c AM |
3583 | i386_index_check (operand_string) |
3584 | const char *operand_string; | |
252b5132 | 3585 | { |
3e73aa7c | 3586 | int ok; |
24eab124 | 3587 | #if INFER_ADDR_PREFIX |
eecb386c AM |
3588 | int fudged = 0; |
3589 | ||
24eab124 AM |
3590 | tryprefix: |
3591 | #endif | |
3e73aa7c JH |
3592 | ok = 1; |
3593 | if (flag_code == CODE_64BIT) | |
3594 | { | |
3595 | /* 64bit checks. */ | |
3596 | if ((i.base_reg | |
3597 | && ((i.base_reg->reg_type & Reg64) == 0) | |
3598 | && (i.base_reg->reg_type != BaseIndex | |
3599 | || i.index_reg)) | |
3600 | || (i.index_reg | |
3601 | && ((i.index_reg->reg_type & (Reg64|BaseIndex)) | |
3602 | != (Reg64|BaseIndex)))) | |
3603 | ok = 0; | |
3604 | } | |
3605 | else | |
3606 | { | |
3607 | if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) | |
3608 | { | |
3609 | /* 16bit checks. */ | |
3610 | if ((i.base_reg | |
3611 | && ((i.base_reg->reg_type & (Reg16|BaseIndex|RegRex)) | |
3612 | != (Reg16|BaseIndex))) | |
3613 | || (i.index_reg | |
3614 | && (((i.index_reg->reg_type & (Reg16|BaseIndex)) | |
3615 | != (Reg16|BaseIndex)) | |
3616 | || ! (i.base_reg | |
3617 | && i.base_reg->reg_num < 6 | |
3618 | && i.index_reg->reg_num >= 6 | |
3619 | && i.log2_scale_factor == 0)))) | |
3620 | ok = 0; | |
3621 | } | |
3622 | else | |
e5cb08ac | 3623 | { |
3e73aa7c JH |
3624 | /* 32bit checks. */ |
3625 | if ((i.base_reg | |
3626 | && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32) | |
3627 | || (i.index_reg | |
3628 | && ((i.index_reg->reg_type & (Reg32|BaseIndex|RegRex)) | |
3629 | != (Reg32|BaseIndex)))) | |
e5cb08ac | 3630 | ok = 0; |
3e73aa7c JH |
3631 | } |
3632 | } | |
3633 | if (!ok) | |
24eab124 AM |
3634 | { |
3635 | #if INFER_ADDR_PREFIX | |
3e73aa7c JH |
3636 | if (flag_code != CODE_64BIT |
3637 | && i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0') | |
24eab124 AM |
3638 | { |
3639 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
3640 | i.prefixes += 1; | |
b23bac36 AM |
3641 | /* Change the size of any displacement too. At most one of |
3642 | Disp16 or Disp32 is set. | |
3643 | FIXME. There doesn't seem to be any real need for separate | |
3644 | Disp16 and Disp32 flags. The same goes for Imm16 and Imm32. | |
47926f60 | 3645 | Removing them would probably clean up the code quite a lot. */ |
b23bac36 AM |
3646 | if (i.types[this_operand] & (Disp16|Disp32)) |
3647 | i.types[this_operand] ^= (Disp16|Disp32); | |
eecb386c | 3648 | fudged = 1; |
24eab124 AM |
3649 | goto tryprefix; |
3650 | } | |
eecb386c AM |
3651 | if (fudged) |
3652 | as_bad (_("`%s' is not a valid base/index expression"), | |
3653 | operand_string); | |
3654 | else | |
c388dee8 | 3655 | #endif |
eecb386c AM |
3656 | as_bad (_("`%s' is not a valid %s bit base/index expression"), |
3657 | operand_string, | |
3e73aa7c | 3658 | flag_code_names[flag_code]); |
eecb386c | 3659 | return 0; |
24eab124 AM |
3660 | } |
3661 | return 1; | |
3662 | } | |
252b5132 | 3663 | |
252b5132 | 3664 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero |
47926f60 | 3665 | on error. */ |
252b5132 | 3666 | |
252b5132 RH |
3667 | static int |
3668 | i386_operand (operand_string) | |
3669 | char *operand_string; | |
3670 | { | |
af6bdddf AM |
3671 | const reg_entry *r; |
3672 | char *end_op; | |
24eab124 | 3673 | char *op_string = operand_string; |
252b5132 | 3674 | |
24eab124 | 3675 | if (is_space_char (*op_string)) |
252b5132 RH |
3676 | ++op_string; |
3677 | ||
24eab124 | 3678 | /* We check for an absolute prefix (differentiating, |
47926f60 | 3679 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
3680 | if (*op_string == ABSOLUTE_PREFIX) |
3681 | { | |
3682 | ++op_string; | |
3683 | if (is_space_char (*op_string)) | |
3684 | ++op_string; | |
3685 | i.types[this_operand] |= JumpAbsolute; | |
3686 | } | |
252b5132 | 3687 | |
47926f60 | 3688 | /* Check if operand is a register. */ |
af6bdddf AM |
3689 | if ((*op_string == REGISTER_PREFIX || allow_naked_reg) |
3690 | && (r = parse_register (op_string, &end_op)) != NULL) | |
24eab124 | 3691 | { |
24eab124 AM |
3692 | /* Check for a segment override by searching for ':' after a |
3693 | segment register. */ | |
3694 | op_string = end_op; | |
3695 | if (is_space_char (*op_string)) | |
3696 | ++op_string; | |
3697 | if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3))) | |
3698 | { | |
3699 | switch (r->reg_num) | |
3700 | { | |
3701 | case 0: | |
3702 | i.seg[i.mem_operands] = &es; | |
3703 | break; | |
3704 | case 1: | |
3705 | i.seg[i.mem_operands] = &cs; | |
3706 | break; | |
3707 | case 2: | |
3708 | i.seg[i.mem_operands] = &ss; | |
3709 | break; | |
3710 | case 3: | |
3711 | i.seg[i.mem_operands] = &ds; | |
3712 | break; | |
3713 | case 4: | |
3714 | i.seg[i.mem_operands] = &fs; | |
3715 | break; | |
3716 | case 5: | |
3717 | i.seg[i.mem_operands] = &gs; | |
3718 | break; | |
3719 | } | |
252b5132 | 3720 | |
24eab124 | 3721 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
3722 | ++op_string; |
3723 | if (is_space_char (*op_string)) | |
24eab124 | 3724 | ++op_string; |
252b5132 | 3725 | |
24eab124 AM |
3726 | if (!is_digit_char (*op_string) |
3727 | && !is_identifier_char (*op_string) | |
3728 | && *op_string != '(' | |
3729 | && *op_string != ABSOLUTE_PREFIX) | |
3730 | { | |
3731 | as_bad (_("bad memory operand `%s'"), op_string); | |
3732 | return 0; | |
3733 | } | |
47926f60 | 3734 | /* Handle case of %es:*foo. */ |
24eab124 AM |
3735 | if (*op_string == ABSOLUTE_PREFIX) |
3736 | { | |
3737 | ++op_string; | |
3738 | if (is_space_char (*op_string)) | |
3739 | ++op_string; | |
3740 | i.types[this_operand] |= JumpAbsolute; | |
3741 | } | |
3742 | goto do_memory_reference; | |
3743 | } | |
3744 | if (*op_string) | |
3745 | { | |
d0b47220 | 3746 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
3747 | return 0; |
3748 | } | |
3749 | i.types[this_operand] |= r->reg_type & ~BaseIndex; | |
520dc8e8 | 3750 | i.op[this_operand].regs = r; |
24eab124 AM |
3751 | i.reg_operands++; |
3752 | } | |
af6bdddf AM |
3753 | else if (*op_string == REGISTER_PREFIX) |
3754 | { | |
3755 | as_bad (_("bad register name `%s'"), op_string); | |
3756 | return 0; | |
3757 | } | |
24eab124 | 3758 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 3759 | { |
24eab124 AM |
3760 | ++op_string; |
3761 | if (i.types[this_operand] & JumpAbsolute) | |
3762 | { | |
d0b47220 | 3763 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
3764 | return 0; |
3765 | } | |
3766 | if (!i386_immediate (op_string)) | |
3767 | return 0; | |
3768 | } | |
3769 | else if (is_digit_char (*op_string) | |
3770 | || is_identifier_char (*op_string) | |
e5cb08ac | 3771 | || *op_string == '(') |
24eab124 | 3772 | { |
47926f60 | 3773 | /* This is a memory reference of some sort. */ |
af6bdddf | 3774 | char *base_string; |
252b5132 | 3775 | |
47926f60 | 3776 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
3777 | char *displacement_string_start; |
3778 | char *displacement_string_end; | |
252b5132 | 3779 | |
24eab124 | 3780 | do_memory_reference: |
24eab124 AM |
3781 | if ((i.mem_operands == 1 |
3782 | && (current_templates->start->opcode_modifier & IsString) == 0) | |
3783 | || i.mem_operands == 2) | |
3784 | { | |
3785 | as_bad (_("too many memory references for `%s'"), | |
3786 | current_templates->start->name); | |
3787 | return 0; | |
3788 | } | |
252b5132 | 3789 | |
24eab124 AM |
3790 | /* Check for base index form. We detect the base index form by |
3791 | looking for an ')' at the end of the operand, searching | |
3792 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
3793 | after the '('. */ | |
af6bdddf | 3794 | base_string = op_string + strlen (op_string); |
c3332e24 | 3795 | |
af6bdddf AM |
3796 | --base_string; |
3797 | if (is_space_char (*base_string)) | |
3798 | --base_string; | |
252b5132 | 3799 | |
47926f60 | 3800 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
3801 | displacement_string_start = op_string; |
3802 | displacement_string_end = base_string + 1; | |
252b5132 | 3803 | |
24eab124 AM |
3804 | if (*base_string == ')') |
3805 | { | |
af6bdddf | 3806 | char *temp_string; |
24eab124 AM |
3807 | unsigned int parens_balanced = 1; |
3808 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 3809 | equal, so this loop will not be infinite. */ |
24eab124 AM |
3810 | do |
3811 | { | |
3812 | base_string--; | |
3813 | if (*base_string == ')') | |
3814 | parens_balanced++; | |
3815 | if (*base_string == '(') | |
3816 | parens_balanced--; | |
3817 | } | |
3818 | while (parens_balanced); | |
c3332e24 | 3819 | |
af6bdddf | 3820 | temp_string = base_string; |
c3332e24 | 3821 | |
24eab124 | 3822 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
3823 | ++base_string; |
3824 | if (is_space_char (*base_string)) | |
24eab124 | 3825 | ++base_string; |
252b5132 | 3826 | |
af6bdddf AM |
3827 | if (*base_string == ',' |
3828 | || ((*base_string == REGISTER_PREFIX || allow_naked_reg) | |
3829 | && (i.base_reg = parse_register (base_string, &end_op)) != NULL)) | |
252b5132 | 3830 | { |
af6bdddf | 3831 | displacement_string_end = temp_string; |
252b5132 | 3832 | |
af6bdddf | 3833 | i.types[this_operand] |= BaseIndex; |
252b5132 | 3834 | |
af6bdddf | 3835 | if (i.base_reg) |
24eab124 | 3836 | { |
24eab124 AM |
3837 | base_string = end_op; |
3838 | if (is_space_char (*base_string)) | |
3839 | ++base_string; | |
af6bdddf AM |
3840 | } |
3841 | ||
3842 | /* There may be an index reg or scale factor here. */ | |
3843 | if (*base_string == ',') | |
3844 | { | |
3845 | ++base_string; | |
3846 | if (is_space_char (*base_string)) | |
3847 | ++base_string; | |
3848 | ||
3849 | if ((*base_string == REGISTER_PREFIX || allow_naked_reg) | |
3850 | && (i.index_reg = parse_register (base_string, &end_op)) != NULL) | |
24eab124 | 3851 | { |
af6bdddf | 3852 | base_string = end_op; |
24eab124 AM |
3853 | if (is_space_char (*base_string)) |
3854 | ++base_string; | |
af6bdddf AM |
3855 | if (*base_string == ',') |
3856 | { | |
3857 | ++base_string; | |
3858 | if (is_space_char (*base_string)) | |
3859 | ++base_string; | |
3860 | } | |
e5cb08ac | 3861 | else if (*base_string != ')') |
af6bdddf AM |
3862 | { |
3863 | as_bad (_("expecting `,' or `)' after index register in `%s'"), | |
3864 | operand_string); | |
3865 | return 0; | |
3866 | } | |
24eab124 | 3867 | } |
af6bdddf | 3868 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 3869 | { |
af6bdddf | 3870 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
3871 | return 0; |
3872 | } | |
252b5132 | 3873 | |
47926f60 | 3874 | /* Check for scale factor. */ |
551c1ca1 | 3875 | if (*base_string != ')') |
af6bdddf | 3876 | { |
551c1ca1 AM |
3877 | char *end_scale = i386_scale (base_string); |
3878 | ||
3879 | if (!end_scale) | |
af6bdddf | 3880 | return 0; |
24eab124 | 3881 | |
551c1ca1 | 3882 | base_string = end_scale; |
af6bdddf AM |
3883 | if (is_space_char (*base_string)) |
3884 | ++base_string; | |
3885 | if (*base_string != ')') | |
3886 | { | |
3887 | as_bad (_("expecting `)' after scale factor in `%s'"), | |
3888 | operand_string); | |
3889 | return 0; | |
3890 | } | |
3891 | } | |
3892 | else if (!i.index_reg) | |
24eab124 | 3893 | { |
af6bdddf AM |
3894 | as_bad (_("expecting index register or scale factor after `,'; got '%c'"), |
3895 | *base_string); | |
24eab124 AM |
3896 | return 0; |
3897 | } | |
3898 | } | |
af6bdddf | 3899 | else if (*base_string != ')') |
24eab124 | 3900 | { |
af6bdddf AM |
3901 | as_bad (_("expecting `,' or `)' after base register in `%s'"), |
3902 | operand_string); | |
24eab124 AM |
3903 | return 0; |
3904 | } | |
c3332e24 | 3905 | } |
af6bdddf | 3906 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 3907 | { |
af6bdddf | 3908 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 3909 | return 0; |
c3332e24 | 3910 | } |
24eab124 AM |
3911 | } |
3912 | ||
3913 | /* If there's an expression beginning the operand, parse it, | |
3914 | assuming displacement_string_start and | |
3915 | displacement_string_end are meaningful. */ | |
3916 | if (displacement_string_start != displacement_string_end) | |
3917 | { | |
3918 | if (!i386_displacement (displacement_string_start, | |
3919 | displacement_string_end)) | |
3920 | return 0; | |
3921 | } | |
3922 | ||
3923 | /* Special case for (%dx) while doing input/output op. */ | |
3924 | if (i.base_reg | |
3925 | && i.base_reg->reg_type == (Reg16 | InOutPortReg) | |
3926 | && i.index_reg == 0 | |
3927 | && i.log2_scale_factor == 0 | |
3928 | && i.seg[i.mem_operands] == 0 | |
3929 | && (i.types[this_operand] & Disp) == 0) | |
3930 | { | |
3931 | i.types[this_operand] = InOutPortReg; | |
3932 | return 1; | |
3933 | } | |
3934 | ||
eecb386c AM |
3935 | if (i386_index_check (operand_string) == 0) |
3936 | return 0; | |
24eab124 AM |
3937 | i.mem_operands++; |
3938 | } | |
3939 | else | |
ce8a8b2f AM |
3940 | { |
3941 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
3942 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
3943 | output_invalid (*op_string), | |
3944 | this_operand + 1, | |
3945 | op_string); | |
3946 | return 0; | |
3947 | } | |
47926f60 | 3948 | return 1; /* Normal return. */ |
252b5132 RH |
3949 | } |
3950 | \f | |
ee7fcc42 AM |
3951 | /* md_estimate_size_before_relax() |
3952 | ||
3953 | Called just before relax() for rs_machine_dependent frags. The x86 | |
3954 | assembler uses these frags to handle variable size jump | |
3955 | instructions. | |
3956 | ||
3957 | Any symbol that is now undefined will not become defined. | |
3958 | Return the correct fr_subtype in the frag. | |
3959 | Return the initial "guess for variable size of frag" to caller. | |
3960 | The guess is actually the growth beyond the fixed part. Whatever | |
3961 | we do to grow the fixed or variable part contributes to our | |
3962 | returned value. */ | |
3963 | ||
252b5132 RH |
3964 | int |
3965 | md_estimate_size_before_relax (fragP, segment) | |
3966 | register fragS *fragP; | |
3967 | register segT segment; | |
3968 | { | |
252b5132 | 3969 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
3970 | check for un-relaxable symbols. On an ELF system, we can't relax |
3971 | an externally visible symbol, because it may be overridden by a | |
3972 | shared library. */ | |
3973 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 3974 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
b98ef147 AM |
3975 | || S_IS_EXTERNAL (fragP->fr_symbol) |
3976 | || S_IS_WEAK (fragP->fr_symbol) | |
3977 | #endif | |
3978 | ) | |
252b5132 | 3979 | { |
b98ef147 AM |
3980 | /* Symbol is undefined in this segment, or we need to keep a |
3981 | reloc so that weak symbols can be overridden. */ | |
3982 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f3c180ae | 3983 | RELOC_ENUM reloc_type; |
ee7fcc42 AM |
3984 | unsigned char *opcode; |
3985 | int old_fr_fix; | |
f6af82bd | 3986 | |
ee7fcc42 AM |
3987 | if (fragP->fr_var != NO_RELOC) |
3988 | reloc_type = fragP->fr_var; | |
b98ef147 | 3989 | else if (size == 2) |
f6af82bd AM |
3990 | reloc_type = BFD_RELOC_16_PCREL; |
3991 | else | |
3992 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 3993 | |
ee7fcc42 AM |
3994 | old_fr_fix = fragP->fr_fix; |
3995 | opcode = (unsigned char *) fragP->fr_opcode; | |
3996 | ||
fddf5b5b | 3997 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 3998 | { |
fddf5b5b AM |
3999 | case UNCOND_JUMP: |
4000 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 4001 | opcode[0] = 0xe9; |
252b5132 RH |
4002 | fragP->fr_fix += size; |
4003 | fix_new (fragP, old_fr_fix, size, | |
4004 | fragP->fr_symbol, | |
4005 | fragP->fr_offset, 1, | |
f6af82bd | 4006 | reloc_type); |
252b5132 RH |
4007 | break; |
4008 | ||
fddf5b5b AM |
4009 | case COND_JUMP86: |
4010 | if (no_cond_jump_promotion) | |
93c2a809 AM |
4011 | goto relax_guess; |
4012 | ||
fddf5b5b AM |
4013 | if (size == 2) |
4014 | { | |
4015 | /* Negate the condition, and branch past an | |
4016 | unconditional jump. */ | |
4017 | opcode[0] ^= 1; | |
4018 | opcode[1] = 3; | |
4019 | /* Insert an unconditional jump. */ | |
4020 | opcode[2] = 0xe9; | |
4021 | /* We added two extra opcode bytes, and have a two byte | |
4022 | offset. */ | |
4023 | fragP->fr_fix += 2 + 2; | |
4024 | fix_new (fragP, old_fr_fix + 2, 2, | |
4025 | fragP->fr_symbol, | |
4026 | fragP->fr_offset, 1, | |
4027 | reloc_type); | |
4028 | break; | |
4029 | } | |
4030 | /* Fall through. */ | |
4031 | ||
4032 | case COND_JUMP: | |
4033 | if (no_cond_jump_promotion) | |
93c2a809 AM |
4034 | goto relax_guess; |
4035 | ||
24eab124 | 4036 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 4037 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 4038 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 4039 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
4040 | /* We've added an opcode byte. */ |
4041 | fragP->fr_fix += 1 + size; | |
252b5132 RH |
4042 | fix_new (fragP, old_fr_fix + 1, size, |
4043 | fragP->fr_symbol, | |
4044 | fragP->fr_offset, 1, | |
f6af82bd | 4045 | reloc_type); |
252b5132 | 4046 | break; |
fddf5b5b AM |
4047 | |
4048 | default: | |
4049 | BAD_CASE (fragP->fr_subtype); | |
4050 | break; | |
252b5132 RH |
4051 | } |
4052 | frag_wane (fragP); | |
ee7fcc42 | 4053 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 4054 | } |
93c2a809 AM |
4055 | |
4056 | relax_guess: | |
4057 | /* Guess size depending on current relax state. Initially the relax | |
4058 | state will correspond to a short jump and we return 1, because | |
4059 | the variable part of the frag (the branch offset) is one byte | |
4060 | long. However, we can relax a section more than once and in that | |
4061 | case we must either set fr_subtype back to the unrelaxed state, | |
4062 | or return the value for the appropriate branch. */ | |
4063 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
4064 | } |
4065 | ||
47926f60 KH |
4066 | /* Called after relax() is finished. |
4067 | ||
4068 | In: Address of frag. | |
4069 | fr_type == rs_machine_dependent. | |
4070 | fr_subtype is what the address relaxed to. | |
4071 | ||
4072 | Out: Any fixSs and constants are set up. | |
4073 | Caller will turn frag into a ".space 0". */ | |
4074 | ||
252b5132 RH |
4075 | #ifndef BFD_ASSEMBLER |
4076 | void | |
4077 | md_convert_frag (headers, sec, fragP) | |
a04b544b ILT |
4078 | object_headers *headers ATTRIBUTE_UNUSED; |
4079 | segT sec ATTRIBUTE_UNUSED; | |
252b5132 RH |
4080 | register fragS *fragP; |
4081 | #else | |
4082 | void | |
4083 | md_convert_frag (abfd, sec, fragP) | |
ab9da554 ILT |
4084 | bfd *abfd ATTRIBUTE_UNUSED; |
4085 | segT sec ATTRIBUTE_UNUSED; | |
252b5132 RH |
4086 | register fragS *fragP; |
4087 | #endif | |
4088 | { | |
4089 | register unsigned char *opcode; | |
4090 | unsigned char *where_to_put_displacement = NULL; | |
847f7ad4 AM |
4091 | offsetT target_address; |
4092 | offsetT opcode_address; | |
252b5132 | 4093 | unsigned int extension = 0; |
847f7ad4 | 4094 | offsetT displacement_from_opcode_start; |
252b5132 RH |
4095 | |
4096 | opcode = (unsigned char *) fragP->fr_opcode; | |
4097 | ||
47926f60 | 4098 | /* Address we want to reach in file space. */ |
252b5132 | 4099 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 4100 | |
47926f60 | 4101 | /* Address opcode resides at in file space. */ |
252b5132 RH |
4102 | opcode_address = fragP->fr_address + fragP->fr_fix; |
4103 | ||
47926f60 | 4104 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
4105 | displacement_from_opcode_start = target_address - opcode_address; |
4106 | ||
fddf5b5b | 4107 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 4108 | { |
47926f60 KH |
4109 | /* Don't have to change opcode. */ |
4110 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 4111 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
4112 | } |
4113 | else | |
4114 | { | |
4115 | if (no_cond_jump_promotion | |
4116 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4117 | as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required")); | |
252b5132 | 4118 | |
fddf5b5b AM |
4119 | switch (fragP->fr_subtype) |
4120 | { | |
4121 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
4122 | extension = 4; /* 1 opcode + 4 displacement */ | |
4123 | opcode[0] = 0xe9; | |
4124 | where_to_put_displacement = &opcode[1]; | |
4125 | break; | |
252b5132 | 4126 | |
fddf5b5b AM |
4127 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
4128 | extension = 2; /* 1 opcode + 2 displacement */ | |
4129 | opcode[0] = 0xe9; | |
4130 | where_to_put_displacement = &opcode[1]; | |
4131 | break; | |
252b5132 | 4132 | |
fddf5b5b AM |
4133 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
4134 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
4135 | extension = 5; /* 2 opcode + 4 displacement */ | |
4136 | opcode[1] = opcode[0] + 0x10; | |
4137 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
4138 | where_to_put_displacement = &opcode[2]; | |
4139 | break; | |
252b5132 | 4140 | |
fddf5b5b AM |
4141 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
4142 | extension = 3; /* 2 opcode + 2 displacement */ | |
4143 | opcode[1] = opcode[0] + 0x10; | |
4144 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
4145 | where_to_put_displacement = &opcode[2]; | |
4146 | break; | |
252b5132 | 4147 | |
fddf5b5b AM |
4148 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
4149 | extension = 4; | |
4150 | opcode[0] ^= 1; | |
4151 | opcode[1] = 3; | |
4152 | opcode[2] = 0xe9; | |
4153 | where_to_put_displacement = &opcode[3]; | |
4154 | break; | |
4155 | ||
4156 | default: | |
4157 | BAD_CASE (fragP->fr_subtype); | |
4158 | break; | |
4159 | } | |
252b5132 | 4160 | } |
fddf5b5b | 4161 | |
47926f60 | 4162 | /* Now put displacement after opcode. */ |
252b5132 RH |
4163 | md_number_to_chars ((char *) where_to_put_displacement, |
4164 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 4165 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
4166 | fragP->fr_fix += extension; |
4167 | } | |
4168 | \f | |
47926f60 KH |
4169 | /* Size of byte displacement jmp. */ |
4170 | int md_short_jump_size = 2; | |
4171 | ||
4172 | /* Size of dword displacement jmp. */ | |
4173 | int md_long_jump_size = 5; | |
252b5132 | 4174 | |
47926f60 KH |
4175 | /* Size of relocation record. */ |
4176 | const int md_reloc_size = 8; | |
252b5132 RH |
4177 | |
4178 | void | |
4179 | md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
4180 | char *ptr; | |
4181 | addressT from_addr, to_addr; | |
ab9da554 ILT |
4182 | fragS *frag ATTRIBUTE_UNUSED; |
4183 | symbolS *to_symbol ATTRIBUTE_UNUSED; | |
252b5132 | 4184 | { |
847f7ad4 | 4185 | offsetT offset; |
252b5132 RH |
4186 | |
4187 | offset = to_addr - (from_addr + 2); | |
47926f60 KH |
4188 | /* Opcode for byte-disp jump. */ |
4189 | md_number_to_chars (ptr, (valueT) 0xeb, 1); | |
252b5132 RH |
4190 | md_number_to_chars (ptr + 1, (valueT) offset, 1); |
4191 | } | |
4192 | ||
4193 | void | |
4194 | md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
4195 | char *ptr; | |
4196 | addressT from_addr, to_addr; | |
a38cf1db AM |
4197 | fragS *frag ATTRIBUTE_UNUSED; |
4198 | symbolS *to_symbol ATTRIBUTE_UNUSED; | |
252b5132 | 4199 | { |
847f7ad4 | 4200 | offsetT offset; |
252b5132 | 4201 | |
a38cf1db AM |
4202 | offset = to_addr - (from_addr + 5); |
4203 | md_number_to_chars (ptr, (valueT) 0xe9, 1); | |
4204 | md_number_to_chars (ptr + 1, (valueT) offset, 4); | |
252b5132 RH |
4205 | } |
4206 | \f | |
4207 | /* Apply a fixup (fixS) to segment data, once it has been determined | |
4208 | by our caller that we have all the info we need to fix it up. | |
4209 | ||
4210 | On the 386, immediates, displacements, and data pointers are all in | |
4211 | the same (little-endian) format, so we don't need to care about which | |
4212 | we are handling. */ | |
4213 | ||
94f592af NC |
4214 | void |
4215 | md_apply_fix3 (fixP, valP, seg) | |
47926f60 KH |
4216 | /* The fix we're to put in. */ |
4217 | fixS *fixP; | |
47926f60 | 4218 | /* Pointer to the value of the bits. */ |
94f592af | 4219 | valueT * valP; |
47926f60 KH |
4220 | /* Segment fix is from. */ |
4221 | segT seg ATTRIBUTE_UNUSED; | |
252b5132 | 4222 | { |
94f592af NC |
4223 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
4224 | valueT value = * valP; | |
252b5132 | 4225 | |
e1b283bb | 4226 | #if defined (BFD_ASSEMBLER) && !defined (TE_Mach) |
93382f6d AM |
4227 | if (fixP->fx_pcrel) |
4228 | { | |
4229 | switch (fixP->fx_r_type) | |
4230 | { | |
5865bb77 ILT |
4231 | default: |
4232 | break; | |
4233 | ||
93382f6d AM |
4234 | case BFD_RELOC_32: |
4235 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
4236 | break; | |
4237 | case BFD_RELOC_16: | |
4238 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
4239 | break; | |
4240 | case BFD_RELOC_8: | |
4241 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
4242 | break; | |
4243 | } | |
4244 | } | |
252b5132 | 4245 | |
0723899b ILT |
4246 | /* This is a hack. There should be a better way to handle this. |
4247 | This covers for the fact that bfd_install_relocation will | |
4248 | subtract the current location (for partial_inplace, PC relative | |
4249 | relocations); see more below. */ | |
93382f6d AM |
4250 | if ((fixP->fx_r_type == BFD_RELOC_32_PCREL |
4251 | || fixP->fx_r_type == BFD_RELOC_16_PCREL | |
4252 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) | |
7c44d1d3 | 4253 | && fixP->fx_addsy && !use_rela_relocations) |
252b5132 RH |
4254 | { |
4255 | #ifndef OBJ_AOUT | |
4256 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
4257 | #ifdef TE_PE | |
4258 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
4259 | #endif | |
4260 | ) | |
4261 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
4262 | #endif | |
4263 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2f66722d | 4264 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
252b5132 | 4265 | { |
2f66722d AM |
4266 | segT fseg = S_GET_SEGMENT (fixP->fx_addsy); |
4267 | ||
4268 | if ((fseg == seg | |
4269 | || (symbol_section_p (fixP->fx_addsy) | |
4270 | && fseg != absolute_section)) | |
4271 | && ! S_IS_EXTERNAL (fixP->fx_addsy) | |
4272 | && ! S_IS_WEAK (fixP->fx_addsy) | |
4273 | && S_IS_DEFINED (fixP->fx_addsy) | |
4274 | && ! S_IS_COMMON (fixP->fx_addsy)) | |
4275 | { | |
4276 | /* Yes, we add the values in twice. This is because | |
4277 | bfd_perform_relocation subtracts them out again. I think | |
4278 | bfd_perform_relocation is broken, but I don't dare change | |
4279 | it. FIXME. */ | |
4280 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
4281 | } | |
252b5132 RH |
4282 | } |
4283 | #endif | |
4284 | #if defined (OBJ_COFF) && defined (TE_PE) | |
4285 | /* For some reason, the PE format does not store a section | |
24eab124 | 4286 | address offset for a PC relative symbol. */ |
252b5132 RH |
4287 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg) |
4288 | value += md_pcrel_from (fixP); | |
4289 | #endif | |
4290 | } | |
4291 | ||
4292 | /* Fix a few things - the dynamic linker expects certain values here, | |
47926f60 | 4293 | and we must not dissappoint it. */ |
252b5132 RH |
4294 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
4295 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
4296 | && fixP->fx_addsy) | |
47926f60 KH |
4297 | switch (fixP->fx_r_type) |
4298 | { | |
4299 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 4300 | case BFD_RELOC_X86_64_PLT32: |
47926f60 KH |
4301 | /* Make the jump instruction point to the address of the operand. At |
4302 | runtime we merely add the offset to the actual PLT entry. */ | |
4303 | value = -4; | |
4304 | break; | |
4305 | case BFD_RELOC_386_GOTPC: | |
4306 | ||
4307 | /* This is tough to explain. We end up with this one if we have | |
252b5132 RH |
4308 | * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal |
4309 | * here is to obtain the absolute address of the GOT, and it is strongly | |
4310 | * preferable from a performance point of view to avoid using a runtime | |
c3332e24 | 4311 | * relocation for this. The actual sequence of instructions often look |
252b5132 | 4312 | * something like: |
c3332e24 | 4313 | * |
24eab124 | 4314 | * call .L66 |
252b5132 | 4315 | * .L66: |
24eab124 AM |
4316 | * popl %ebx |
4317 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
c3332e24 | 4318 | * |
24eab124 | 4319 | * The call and pop essentially return the absolute address of |
252b5132 RH |
4320 | * the label .L66 and store it in %ebx. The linker itself will |
4321 | * ultimately change the first operand of the addl so that %ebx points to | |
4322 | * the GOT, but to keep things simple, the .o file must have this operand | |
4323 | * set so that it generates not the absolute address of .L66, but the | |
4324 | * absolute address of itself. This allows the linker itself simply | |
4325 | * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be | |
4326 | * added in, and the addend of the relocation is stored in the operand | |
4327 | * field for the instruction itself. | |
c3332e24 | 4328 | * |
24eab124 | 4329 | * Our job here is to fix the operand so that it would add the correct |
252b5132 RH |
4330 | * offset so that %ebx would point to itself. The thing that is tricky is |
4331 | * that .-.L66 will point to the beginning of the instruction, so we need | |
4332 | * to further modify the operand so that it will point to itself. | |
4333 | * There are other cases where you have something like: | |
c3332e24 | 4334 | * |
24eab124 | 4335 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] |
c3332e24 | 4336 | * |
252b5132 | 4337 | * and here no correction would be required. Internally in the assembler |
c3332e24 | 4338 | * we treat operands of this form as not being pcrel since the '.' is |
252b5132 RH |
4339 | * explicitly mentioned, and I wonder whether it would simplify matters |
4340 | * to do it this way. Who knows. In earlier versions of the PIC patches, | |
4341 | * the pcrel_adjust field was used to store the correction, but since the | |
47926f60 KH |
4342 | * expression is not pcrel, I felt it would be confusing to do it this |
4343 | * way. */ | |
4344 | ||
4345 | value -= 1; | |
4346 | break; | |
4347 | case BFD_RELOC_386_GOT32: | |
3e73aa7c | 4348 | case BFD_RELOC_X86_64_GOT32: |
47926f60 KH |
4349 | value = 0; /* Fully resolved at runtime. No addend. */ |
4350 | break; | |
4351 | case BFD_RELOC_386_GOTOFF: | |
3e73aa7c | 4352 | case BFD_RELOC_X86_64_GOTPCREL: |
47926f60 KH |
4353 | break; |
4354 | ||
4355 | case BFD_RELOC_VTABLE_INHERIT: | |
4356 | case BFD_RELOC_VTABLE_ENTRY: | |
4357 | fixP->fx_done = 0; | |
94f592af | 4358 | return; |
47926f60 KH |
4359 | |
4360 | default: | |
4361 | break; | |
4362 | } | |
4363 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
94f592af | 4364 | * valP = value; |
47926f60 | 4365 | #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */ |
3e73aa7c | 4366 | |
3e73aa7c | 4367 | /* Are we finished with this relocation now? */ |
94f592af | 4368 | if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0) |
3e73aa7c | 4369 | fixP->fx_done = 1; |
94f592af | 4370 | #ifdef BFD_ASSEMBLER |
3e73aa7c JH |
4371 | else if (use_rela_relocations) |
4372 | { | |
4373 | fixP->fx_no_overflow = 1; | |
4374 | value = 0; | |
4375 | } | |
3e73aa7c | 4376 | #endif |
94f592af | 4377 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 4378 | } |
252b5132 | 4379 | \f |
252b5132 RH |
4380 | #define MAX_LITTLENUMS 6 |
4381 | ||
47926f60 KH |
4382 | /* Turn the string pointed to by litP into a floating point constant |
4383 | of type TYPE, and emit the appropriate bytes. The number of | |
4384 | LITTLENUMS emitted is stored in *SIZEP. An error message is | |
4385 | returned, or NULL on OK. */ | |
4386 | ||
252b5132 RH |
4387 | char * |
4388 | md_atof (type, litP, sizeP) | |
2ab9b79e | 4389 | int type; |
252b5132 RH |
4390 | char *litP; |
4391 | int *sizeP; | |
4392 | { | |
4393 | int prec; | |
4394 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
4395 | LITTLENUM_TYPE *wordP; | |
4396 | char *t; | |
4397 | ||
4398 | switch (type) | |
4399 | { | |
4400 | case 'f': | |
4401 | case 'F': | |
4402 | prec = 2; | |
4403 | break; | |
4404 | ||
4405 | case 'd': | |
4406 | case 'D': | |
4407 | prec = 4; | |
4408 | break; | |
4409 | ||
4410 | case 'x': | |
4411 | case 'X': | |
4412 | prec = 5; | |
4413 | break; | |
4414 | ||
4415 | default: | |
4416 | *sizeP = 0; | |
4417 | return _("Bad call to md_atof ()"); | |
4418 | } | |
4419 | t = atof_ieee (input_line_pointer, type, words); | |
4420 | if (t) | |
4421 | input_line_pointer = t; | |
4422 | ||
4423 | *sizeP = prec * sizeof (LITTLENUM_TYPE); | |
4424 | /* This loops outputs the LITTLENUMs in REVERSE order; in accord with | |
4425 | the bigendian 386. */ | |
4426 | for (wordP = words + prec - 1; prec--;) | |
4427 | { | |
4428 | md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE)); | |
4429 | litP += sizeof (LITTLENUM_TYPE); | |
4430 | } | |
4431 | return 0; | |
4432 | } | |
4433 | \f | |
4434 | char output_invalid_buf[8]; | |
4435 | ||
252b5132 RH |
4436 | static char * |
4437 | output_invalid (c) | |
4438 | int c; | |
4439 | { | |
3882b010 | 4440 | if (ISPRINT (c)) |
252b5132 RH |
4441 | sprintf (output_invalid_buf, "'%c'", c); |
4442 | else | |
4443 | sprintf (output_invalid_buf, "(0x%x)", (unsigned) c); | |
4444 | return output_invalid_buf; | |
4445 | } | |
4446 | ||
af6bdddf | 4447 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
4448 | |
4449 | static const reg_entry * | |
4450 | parse_register (reg_string, end_op) | |
4451 | char *reg_string; | |
4452 | char **end_op; | |
4453 | { | |
af6bdddf AM |
4454 | char *s = reg_string; |
4455 | char *p; | |
252b5132 RH |
4456 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
4457 | const reg_entry *r; | |
4458 | ||
4459 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
4460 | if (*s == REGISTER_PREFIX) | |
4461 | ++s; | |
4462 | ||
4463 | if (is_space_char (*s)) | |
4464 | ++s; | |
4465 | ||
4466 | p = reg_name_given; | |
af6bdddf | 4467 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
4468 | { |
4469 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
4470 | return (const reg_entry *) NULL; |
4471 | s++; | |
252b5132 RH |
4472 | } |
4473 | ||
6588847e DN |
4474 | /* For naked regs, make sure that we are not dealing with an identifier. |
4475 | This prevents confusing an identifier like `eax_var' with register | |
4476 | `eax'. */ | |
4477 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
4478 | return (const reg_entry *) NULL; | |
4479 | ||
af6bdddf | 4480 | *end_op = s; |
252b5132 RH |
4481 | |
4482 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
4483 | ||
5f47d35b | 4484 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 4485 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 4486 | { |
5f47d35b AM |
4487 | if (is_space_char (*s)) |
4488 | ++s; | |
4489 | if (*s == '(') | |
4490 | { | |
af6bdddf | 4491 | ++s; |
5f47d35b AM |
4492 | if (is_space_char (*s)) |
4493 | ++s; | |
4494 | if (*s >= '0' && *s <= '7') | |
4495 | { | |
4496 | r = &i386_float_regtab[*s - '0']; | |
af6bdddf | 4497 | ++s; |
5f47d35b AM |
4498 | if (is_space_char (*s)) |
4499 | ++s; | |
4500 | if (*s == ')') | |
4501 | { | |
4502 | *end_op = s + 1; | |
4503 | return r; | |
4504 | } | |
5f47d35b | 4505 | } |
47926f60 | 4506 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
4507 | return (const reg_entry *) NULL; |
4508 | } | |
4509 | } | |
4510 | ||
1ae00879 AM |
4511 | if (r != NULL |
4512 | && r->reg_flags & (RegRex64|RegRex) | |
4513 | && flag_code != CODE_64BIT) | |
4514 | { | |
4515 | return (const reg_entry *) NULL; | |
4516 | } | |
4517 | ||
252b5132 RH |
4518 | return r; |
4519 | } | |
4520 | \f | |
4cc782b5 | 4521 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
65172ab8 | 4522 | const char *md_shortopts = "kVQ:sq"; |
252b5132 | 4523 | #else |
65172ab8 | 4524 | const char *md_shortopts = "q"; |
252b5132 | 4525 | #endif |
6e0b89ee | 4526 | |
252b5132 | 4527 | struct option md_longopts[] = { |
3e73aa7c JH |
4528 | #define OPTION_32 (OPTION_MD_BASE + 0) |
4529 | {"32", no_argument, NULL, OPTION_32}, | |
6e0b89ee | 4530 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3e73aa7c JH |
4531 | #define OPTION_64 (OPTION_MD_BASE + 1) |
4532 | {"64", no_argument, NULL, OPTION_64}, | |
6e0b89ee | 4533 | #endif |
252b5132 RH |
4534 | {NULL, no_argument, NULL, 0} |
4535 | }; | |
4536 | size_t md_longopts_size = sizeof (md_longopts); | |
4537 | ||
4538 | int | |
4539 | md_parse_option (c, arg) | |
4540 | int c; | |
ab9da554 | 4541 | char *arg ATTRIBUTE_UNUSED; |
252b5132 RH |
4542 | { |
4543 | switch (c) | |
4544 | { | |
a38cf1db AM |
4545 | case 'q': |
4546 | quiet_warnings = 1; | |
252b5132 RH |
4547 | break; |
4548 | ||
4549 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
4550 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
4551 | should be emitted or not. FIXME: Not implemented. */ | |
4552 | case 'Q': | |
252b5132 RH |
4553 | break; |
4554 | ||
4555 | /* -V: SVR4 argument to print version ID. */ | |
4556 | case 'V': | |
4557 | print_version_id (); | |
4558 | break; | |
4559 | ||
a38cf1db AM |
4560 | /* -k: Ignore for FreeBSD compatibility. */ |
4561 | case 'k': | |
252b5132 | 4562 | break; |
4cc782b5 ILT |
4563 | |
4564 | case 's': | |
4565 | /* -s: On i386 Solaris, this tells the native assembler to use | |
4566 | .stab instead of .stab.excl. We always use .stab anyhow. */ | |
4567 | break; | |
6e0b89ee | 4568 | |
3e73aa7c JH |
4569 | case OPTION_64: |
4570 | { | |
4571 | const char **list, **l; | |
4572 | ||
3e73aa7c JH |
4573 | list = bfd_target_list (); |
4574 | for (l = list; *l != NULL; l++) | |
6e0b89ee AM |
4575 | if (strcmp (*l, "elf64-x86-64") == 0) |
4576 | { | |
4577 | default_arch = "x86_64"; | |
4578 | break; | |
4579 | } | |
3e73aa7c | 4580 | if (*l == NULL) |
6e0b89ee | 4581 | as_fatal (_("No compiled in support for x86_64")); |
3e73aa7c JH |
4582 | free (list); |
4583 | } | |
4584 | break; | |
4585 | #endif | |
252b5132 | 4586 | |
6e0b89ee AM |
4587 | case OPTION_32: |
4588 | default_arch = "i386"; | |
4589 | break; | |
4590 | ||
252b5132 RH |
4591 | default: |
4592 | return 0; | |
4593 | } | |
4594 | return 1; | |
4595 | } | |
4596 | ||
4597 | void | |
4598 | md_show_usage (stream) | |
4599 | FILE *stream; | |
4600 | { | |
4cc782b5 ILT |
4601 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
4602 | fprintf (stream, _("\ | |
a38cf1db AM |
4603 | -Q ignored\n\ |
4604 | -V print assembler version number\n\ | |
4605 | -k ignored\n\ | |
4606 | -q quieten some warnings\n\ | |
4607 | -s ignored\n")); | |
4608 | #else | |
4609 | fprintf (stream, _("\ | |
4610 | -q quieten some warnings\n")); | |
4cc782b5 | 4611 | #endif |
252b5132 RH |
4612 | } |
4613 | ||
4614 | #ifdef BFD_ASSEMBLER | |
3e73aa7c JH |
4615 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
4616 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) | |
252b5132 RH |
4617 | |
4618 | /* Pick the target format to use. */ | |
4619 | ||
47926f60 | 4620 | const char * |
252b5132 RH |
4621 | i386_target_format () |
4622 | { | |
3e73aa7c JH |
4623 | if (!strcmp (default_arch, "x86_64")) |
4624 | set_code_flag (CODE_64BIT); | |
4625 | else if (!strcmp (default_arch, "i386")) | |
4626 | set_code_flag (CODE_32BIT); | |
4627 | else | |
4628 | as_fatal (_("Unknown architecture")); | |
252b5132 RH |
4629 | switch (OUTPUT_FLAVOR) |
4630 | { | |
4c63da97 AM |
4631 | #ifdef OBJ_MAYBE_AOUT |
4632 | case bfd_target_aout_flavour: | |
47926f60 | 4633 | return AOUT_TARGET_FORMAT; |
4c63da97 AM |
4634 | #endif |
4635 | #ifdef OBJ_MAYBE_COFF | |
252b5132 RH |
4636 | case bfd_target_coff_flavour: |
4637 | return "coff-i386"; | |
4c63da97 | 4638 | #endif |
3e73aa7c | 4639 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 4640 | case bfd_target_elf_flavour: |
3e73aa7c | 4641 | { |
e5cb08ac KH |
4642 | if (flag_code == CODE_64BIT) |
4643 | use_rela_relocations = 1; | |
4644 | return flag_code == CODE_64BIT ? "elf64-x86-64" : "elf32-i386"; | |
3e73aa7c | 4645 | } |
4c63da97 | 4646 | #endif |
252b5132 RH |
4647 | default: |
4648 | abort (); | |
4649 | return NULL; | |
4650 | } | |
4651 | } | |
4652 | ||
47926f60 | 4653 | #endif /* OBJ_MAYBE_ more than one */ |
a847613f AM |
4654 | |
4655 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) | |
4656 | void i386_elf_emit_arch_note () | |
4657 | { | |
4658 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
4659 | && cpu_arch_name != NULL) | |
4660 | { | |
4661 | char *p; | |
4662 | asection *seg = now_seg; | |
4663 | subsegT subseg = now_subseg; | |
4664 | Elf_Internal_Note i_note; | |
4665 | Elf_External_Note e_note; | |
4666 | asection *note_secp; | |
4667 | int len; | |
4668 | ||
4669 | /* Create the .note section. */ | |
4670 | note_secp = subseg_new (".note", 0); | |
4671 | bfd_set_section_flags (stdoutput, | |
4672 | note_secp, | |
4673 | SEC_HAS_CONTENTS | SEC_READONLY); | |
4674 | ||
4675 | /* Process the arch string. */ | |
4676 | len = strlen (cpu_arch_name); | |
4677 | ||
4678 | i_note.namesz = len + 1; | |
4679 | i_note.descsz = 0; | |
4680 | i_note.type = NT_ARCH; | |
4681 | p = frag_more (sizeof (e_note.namesz)); | |
4682 | md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz)); | |
4683 | p = frag_more (sizeof (e_note.descsz)); | |
4684 | md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz)); | |
4685 | p = frag_more (sizeof (e_note.type)); | |
4686 | md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type)); | |
4687 | p = frag_more (len + 1); | |
4688 | strcpy (p, cpu_arch_name); | |
4689 | ||
4690 | frag_align (2, 0, 0); | |
4691 | ||
4692 | subseg_set (seg, subseg); | |
4693 | } | |
4694 | } | |
4695 | #endif | |
47926f60 | 4696 | #endif /* BFD_ASSEMBLER */ |
252b5132 | 4697 | \f |
252b5132 RH |
4698 | symbolS * |
4699 | md_undefined_symbol (name) | |
4700 | char *name; | |
4701 | { | |
18dc2407 ILT |
4702 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
4703 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
4704 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
4705 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
4706 | { |
4707 | if (!GOT_symbol) | |
4708 | { | |
4709 | if (symbol_find (name)) | |
4710 | as_bad (_("GOT already in symbol table")); | |
4711 | GOT_symbol = symbol_new (name, undefined_section, | |
4712 | (valueT) 0, &zero_address_frag); | |
4713 | }; | |
4714 | return GOT_symbol; | |
4715 | } | |
252b5132 RH |
4716 | return 0; |
4717 | } | |
4718 | ||
4719 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 4720 | |
252b5132 RH |
4721 | valueT |
4722 | md_section_align (segment, size) | |
ab9da554 | 4723 | segT segment ATTRIBUTE_UNUSED; |
252b5132 RH |
4724 | valueT size; |
4725 | { | |
252b5132 | 4726 | #ifdef BFD_ASSEMBLER |
4c63da97 AM |
4727 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
4728 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
4729 | { | |
4730 | /* For a.out, force the section size to be aligned. If we don't do | |
4731 | this, BFD will align it for us, but it will not write out the | |
4732 | final bytes of the section. This may be a bug in BFD, but it is | |
4733 | easier to fix it here since that is how the other a.out targets | |
4734 | work. */ | |
4735 | int align; | |
4736 | ||
4737 | align = bfd_get_section_alignment (stdoutput, segment); | |
4738 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
4739 | } | |
252b5132 RH |
4740 | #endif |
4741 | #endif | |
4742 | ||
4743 | return size; | |
4744 | } | |
4745 | ||
4746 | /* On the i386, PC-relative offsets are relative to the start of the | |
4747 | next instruction. That is, the address of the offset, plus its | |
4748 | size, since the offset is always the last part of the insn. */ | |
4749 | ||
4750 | long | |
4751 | md_pcrel_from (fixP) | |
4752 | fixS *fixP; | |
4753 | { | |
4754 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
4755 | } | |
4756 | ||
4757 | #ifndef I386COFF | |
4758 | ||
4759 | static void | |
4760 | s_bss (ignore) | |
ab9da554 | 4761 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
4762 | { |
4763 | register int temp; | |
4764 | ||
4765 | temp = get_absolute_expression (); | |
4766 | subseg_set (bss_section, (subsegT) temp); | |
4767 | demand_empty_rest_of_line (); | |
4768 | } | |
4769 | ||
4770 | #endif | |
4771 | ||
252b5132 RH |
4772 | #ifdef BFD_ASSEMBLER |
4773 | ||
4774 | void | |
4775 | i386_validate_fix (fixp) | |
4776 | fixS *fixp; | |
4777 | { | |
4778 | if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) | |
4779 | { | |
3e73aa7c | 4780 | /* GOTOFF relocation are nonsense in 64bit mode. */ |
23df1078 JH |
4781 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
4782 | { | |
4783 | if (flag_code != CODE_64BIT) | |
4784 | abort (); | |
4785 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
4786 | } | |
4787 | else | |
4788 | { | |
4789 | if (flag_code == CODE_64BIT) | |
4790 | abort (); | |
4791 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
4792 | } | |
252b5132 RH |
4793 | fixp->fx_subsy = 0; |
4794 | } | |
4795 | } | |
4796 | ||
252b5132 RH |
4797 | arelent * |
4798 | tc_gen_reloc (section, fixp) | |
ab9da554 | 4799 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
4800 | fixS *fixp; |
4801 | { | |
4802 | arelent *rel; | |
4803 | bfd_reloc_code_real_type code; | |
4804 | ||
4805 | switch (fixp->fx_r_type) | |
4806 | { | |
3e73aa7c JH |
4807 | case BFD_RELOC_X86_64_PLT32: |
4808 | case BFD_RELOC_X86_64_GOT32: | |
4809 | case BFD_RELOC_X86_64_GOTPCREL: | |
252b5132 RH |
4810 | case BFD_RELOC_386_PLT32: |
4811 | case BFD_RELOC_386_GOT32: | |
4812 | case BFD_RELOC_386_GOTOFF: | |
4813 | case BFD_RELOC_386_GOTPC: | |
3e73aa7c | 4814 | case BFD_RELOC_X86_64_32S: |
252b5132 RH |
4815 | case BFD_RELOC_RVA: |
4816 | case BFD_RELOC_VTABLE_ENTRY: | |
4817 | case BFD_RELOC_VTABLE_INHERIT: | |
4818 | code = fixp->fx_r_type; | |
4819 | break; | |
4820 | default: | |
93382f6d | 4821 | if (fixp->fx_pcrel) |
252b5132 | 4822 | { |
93382f6d AM |
4823 | switch (fixp->fx_size) |
4824 | { | |
4825 | default: | |
b091f402 AM |
4826 | as_bad_where (fixp->fx_file, fixp->fx_line, |
4827 | _("can not do %d byte pc-relative relocation"), | |
4828 | fixp->fx_size); | |
93382f6d AM |
4829 | code = BFD_RELOC_32_PCREL; |
4830 | break; | |
4831 | case 1: code = BFD_RELOC_8_PCREL; break; | |
4832 | case 2: code = BFD_RELOC_16_PCREL; break; | |
4833 | case 4: code = BFD_RELOC_32_PCREL; break; | |
4834 | } | |
4835 | } | |
4836 | else | |
4837 | { | |
4838 | switch (fixp->fx_size) | |
4839 | { | |
4840 | default: | |
b091f402 AM |
4841 | as_bad_where (fixp->fx_file, fixp->fx_line, |
4842 | _("can not do %d byte relocation"), | |
4843 | fixp->fx_size); | |
93382f6d AM |
4844 | code = BFD_RELOC_32; |
4845 | break; | |
4846 | case 1: code = BFD_RELOC_8; break; | |
4847 | case 2: code = BFD_RELOC_16; break; | |
4848 | case 4: code = BFD_RELOC_32; break; | |
3e73aa7c | 4849 | case 8: code = BFD_RELOC_64; break; |
93382f6d | 4850 | } |
252b5132 RH |
4851 | } |
4852 | break; | |
4853 | } | |
252b5132 RH |
4854 | |
4855 | if (code == BFD_RELOC_32 | |
4856 | && GOT_symbol | |
4857 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c JH |
4858 | { |
4859 | /* We don't support GOTPC on 64bit targets. */ | |
4860 | if (flag_code == CODE_64BIT) | |
bfb32b52 | 4861 | abort (); |
3e73aa7c JH |
4862 | code = BFD_RELOC_386_GOTPC; |
4863 | } | |
252b5132 RH |
4864 | |
4865 | rel = (arelent *) xmalloc (sizeof (arelent)); | |
49309057 ILT |
4866 | rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
4867 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
4868 | |
4869 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
3e73aa7c JH |
4870 | if (!use_rela_relocations) |
4871 | { | |
4872 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
4873 | vtable entry to be used in the relocation's section offset. */ | |
4874 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
4875 | rel->address = fixp->fx_offset; | |
252b5132 | 4876 | |
3e73aa7c JH |
4877 | if (fixp->fx_pcrel) |
4878 | rel->addend = fixp->fx_addnumber; | |
4879 | else | |
4880 | rel->addend = 0; | |
4881 | } | |
4882 | /* Use the rela in 64bit mode. */ | |
252b5132 | 4883 | else |
3e73aa7c JH |
4884 | { |
4885 | rel->addend = fixp->fx_offset; | |
3e73aa7c JH |
4886 | if (fixp->fx_pcrel) |
4887 | rel->addend -= fixp->fx_size; | |
4888 | } | |
4889 | ||
252b5132 RH |
4890 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
4891 | if (rel->howto == NULL) | |
4892 | { | |
4893 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 4894 | _("cannot represent relocation type %s"), |
252b5132 RH |
4895 | bfd_get_reloc_code_name (code)); |
4896 | /* Set howto to a garbage value so that we can keep going. */ | |
4897 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
4898 | assert (rel->howto != NULL); | |
4899 | } | |
4900 | ||
4901 | return rel; | |
4902 | } | |
4903 | ||
47926f60 | 4904 | #else /* ! BFD_ASSEMBLER */ |
252b5132 RH |
4905 | |
4906 | #if (defined(OBJ_AOUT) | defined(OBJ_BOUT)) | |
4907 | void | |
4908 | tc_aout_fix_to_chars (where, fixP, segment_address_in_file) | |
4909 | char *where; | |
4910 | fixS *fixP; | |
4911 | relax_addressT segment_address_in_file; | |
4912 | { | |
47926f60 KH |
4913 | /* In: length of relocation (or of address) in chars: 1, 2 or 4. |
4914 | Out: GNU LD relocation length code: 0, 1, or 2. */ | |
252b5132 | 4915 | |
47926f60 | 4916 | static const unsigned char nbytes_r_length[] = { 42, 0, 1, 42, 2 }; |
252b5132 RH |
4917 | long r_symbolnum; |
4918 | ||
4919 | know (fixP->fx_addsy != NULL); | |
4920 | ||
4921 | md_number_to_chars (where, | |
4922 | (valueT) (fixP->fx_frag->fr_address | |
4923 | + fixP->fx_where - segment_address_in_file), | |
4924 | 4); | |
4925 | ||
4926 | r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy) | |
4927 | ? S_GET_TYPE (fixP->fx_addsy) | |
4928 | : fixP->fx_addsy->sy_number); | |
4929 | ||
4930 | where[6] = (r_symbolnum >> 16) & 0x0ff; | |
4931 | where[5] = (r_symbolnum >> 8) & 0x0ff; | |
4932 | where[4] = r_symbolnum & 0x0ff; | |
4933 | where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08) | |
4934 | | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06) | |
4935 | | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f)); | |
4936 | } | |
4937 | ||
47926f60 | 4938 | #endif /* OBJ_AOUT or OBJ_BOUT. */ |
252b5132 RH |
4939 | |
4940 | #if defined (I386COFF) | |
4941 | ||
4942 | short | |
4943 | tc_coff_fix2rtype (fixP) | |
4944 | fixS *fixP; | |
4945 | { | |
4946 | if (fixP->fx_r_type == R_IMAGEBASE) | |
4947 | return R_IMAGEBASE; | |
4948 | ||
4949 | return (fixP->fx_pcrel ? | |
4950 | (fixP->fx_size == 1 ? R_PCRBYTE : | |
4951 | fixP->fx_size == 2 ? R_PCRWORD : | |
4952 | R_PCRLONG) : | |
4953 | (fixP->fx_size == 1 ? R_RELBYTE : | |
4954 | fixP->fx_size == 2 ? R_RELWORD : | |
4955 | R_DIR32)); | |
4956 | } | |
4957 | ||
4958 | int | |
4959 | tc_coff_sizemachdep (frag) | |
4960 | fragS *frag; | |
4961 | { | |
4962 | if (frag->fr_next) | |
4963 | return (frag->fr_next->fr_address - frag->fr_address); | |
4964 | else | |
4965 | return 0; | |
4966 | } | |
4967 | ||
47926f60 | 4968 | #endif /* I386COFF */ |
252b5132 | 4969 | |
47926f60 | 4970 | #endif /* ! BFD_ASSEMBLER */ |
64a0c779 DN |
4971 | \f |
4972 | /* Parse operands using Intel syntax. This implements a recursive descent | |
4973 | parser based on the BNF grammar published in Appendix B of the MASM 6.1 | |
4974 | Programmer's Guide. | |
4975 | ||
4976 | FIXME: We do not recognize the full operand grammar defined in the MASM | |
4977 | documentation. In particular, all the structure/union and | |
4978 | high-level macro operands are missing. | |
4979 | ||
4980 | Uppercase words are terminals, lower case words are non-terminals. | |
4981 | Objects surrounded by double brackets '[[' ']]' are optional. Vertical | |
4982 | bars '|' denote choices. Most grammar productions are implemented in | |
4983 | functions called 'intel_<production>'. | |
4984 | ||
4985 | Initial production is 'expr'. | |
4986 | ||
64a0c779 DN |
4987 | addOp + | - |
4988 | ||
4989 | alpha [a-zA-Z] | |
4990 | ||
4991 | byteRegister AL | AH | BL | BH | CL | CH | DL | DH | |
4992 | ||
4993 | constant digits [[ radixOverride ]] | |
4994 | ||
4995 | dataType BYTE | WORD | DWORD | QWORD | XWORD | |
4996 | ||
4997 | digits decdigit | |
b77a7acd AJ |
4998 | | digits decdigit |
4999 | | digits hexdigit | |
64a0c779 DN |
5000 | |
5001 | decdigit [0-9] | |
5002 | ||
5003 | e05 e05 addOp e06 | |
b77a7acd | 5004 | | e06 |
64a0c779 DN |
5005 | |
5006 | e06 e06 mulOp e09 | |
b77a7acd | 5007 | | e09 |
64a0c779 DN |
5008 | |
5009 | e09 OFFSET e10 | |
5010 | | e09 PTR e10 | |
5011 | | e09 : e10 | |
5012 | | e10 | |
5013 | ||
5014 | e10 e10 [ expr ] | |
b77a7acd | 5015 | | e11 |
64a0c779 DN |
5016 | |
5017 | e11 ( expr ) | |
b77a7acd | 5018 | | [ expr ] |
64a0c779 DN |
5019 | | constant |
5020 | | dataType | |
5021 | | id | |
5022 | | $ | |
5023 | | register | |
5024 | ||
5025 | => expr SHORT e05 | |
b77a7acd | 5026 | | e05 |
64a0c779 DN |
5027 | |
5028 | gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX | |
b77a7acd | 5029 | | BP | EBP | SP | ESP | DI | EDI | SI | ESI |
64a0c779 DN |
5030 | |
5031 | hexdigit a | b | c | d | e | f | |
b77a7acd | 5032 | | A | B | C | D | E | F |
64a0c779 DN |
5033 | |
5034 | id alpha | |
b77a7acd | 5035 | | id alpha |
64a0c779 DN |
5036 | | id decdigit |
5037 | ||
5038 | mulOp * | / | MOD | |
5039 | ||
5040 | quote " | ' | |
5041 | ||
5042 | register specialRegister | |
b77a7acd | 5043 | | gpRegister |
64a0c779 DN |
5044 | | byteRegister |
5045 | ||
5046 | segmentRegister CS | DS | ES | FS | GS | SS | |
5047 | ||
5048 | specialRegister CR0 | CR2 | CR3 | |
b77a7acd | 5049 | | DR0 | DR1 | DR2 | DR3 | DR6 | DR7 |
64a0c779 DN |
5050 | | TR3 | TR4 | TR5 | TR6 | TR7 |
5051 | ||
64a0c779 DN |
5052 | We simplify the grammar in obvious places (e.g., register parsing is |
5053 | done by calling parse_register) and eliminate immediate left recursion | |
5054 | to implement a recursive-descent parser. | |
5055 | ||
5056 | expr SHORT e05 | |
b77a7acd | 5057 | | e05 |
64a0c779 DN |
5058 | |
5059 | e05 e06 e05' | |
5060 | ||
5061 | e05' addOp e06 e05' | |
b77a7acd | 5062 | | Empty |
64a0c779 DN |
5063 | |
5064 | e06 e09 e06' | |
5065 | ||
5066 | e06' mulOp e09 e06' | |
b77a7acd | 5067 | | Empty |
64a0c779 DN |
5068 | |
5069 | e09 OFFSET e10 e09' | |
b77a7acd | 5070 | | e10 e09' |
64a0c779 DN |
5071 | |
5072 | e09' PTR e10 e09' | |
b77a7acd | 5073 | | : e10 e09' |
64a0c779 DN |
5074 | | Empty |
5075 | ||
5076 | e10 e11 e10' | |
5077 | ||
5078 | e10' [ expr ] e10' | |
b77a7acd | 5079 | | Empty |
64a0c779 DN |
5080 | |
5081 | e11 ( expr ) | |
b77a7acd | 5082 | | [ expr ] |
64a0c779 DN |
5083 | | BYTE |
5084 | | WORD | |
5085 | | DWORD | |
5086 | | QWORD | |
5087 | | XWORD | |
5088 | | . | |
5089 | | $ | |
5090 | | register | |
5091 | | id | |
5092 | | constant */ | |
5093 | ||
5094 | /* Parsing structure for the intel syntax parser. Used to implement the | |
5095 | semantic actions for the operand grammar. */ | |
5096 | struct intel_parser_s | |
5097 | { | |
5098 | char *op_string; /* The string being parsed. */ | |
5099 | int got_a_float; /* Whether the operand is a float. */ | |
4a1805b1 | 5100 | int op_modifier; /* Operand modifier. */ |
64a0c779 DN |
5101 | int is_mem; /* 1 if operand is memory reference. */ |
5102 | const reg_entry *reg; /* Last register reference found. */ | |
5103 | char *disp; /* Displacement string being built. */ | |
5104 | }; | |
5105 | ||
5106 | static struct intel_parser_s intel_parser; | |
5107 | ||
5108 | /* Token structure for parsing intel syntax. */ | |
5109 | struct intel_token | |
5110 | { | |
5111 | int code; /* Token code. */ | |
5112 | const reg_entry *reg; /* Register entry for register tokens. */ | |
5113 | char *str; /* String representation. */ | |
5114 | }; | |
5115 | ||
5116 | static struct intel_token cur_token, prev_token; | |
5117 | ||
50705ef4 AM |
5118 | /* Token codes for the intel parser. Since T_SHORT is already used |
5119 | by COFF, undefine it first to prevent a warning. */ | |
64a0c779 DN |
5120 | #define T_NIL -1 |
5121 | #define T_CONST 1 | |
5122 | #define T_REG 2 | |
5123 | #define T_BYTE 3 | |
5124 | #define T_WORD 4 | |
5125 | #define T_DWORD 5 | |
5126 | #define T_QWORD 6 | |
5127 | #define T_XWORD 7 | |
50705ef4 | 5128 | #undef T_SHORT |
64a0c779 DN |
5129 | #define T_SHORT 8 |
5130 | #define T_OFFSET 9 | |
5131 | #define T_PTR 10 | |
5132 | #define T_ID 11 | |
5133 | ||
5134 | /* Prototypes for intel parser functions. */ | |
5135 | static int intel_match_token PARAMS ((int code)); | |
cce0cbdc DN |
5136 | static void intel_get_token PARAMS ((void)); |
5137 | static void intel_putback_token PARAMS ((void)); | |
5138 | static int intel_expr PARAMS ((void)); | |
5139 | static int intel_e05 PARAMS ((void)); | |
5140 | static int intel_e05_1 PARAMS ((void)); | |
5141 | static int intel_e06 PARAMS ((void)); | |
5142 | static int intel_e06_1 PARAMS ((void)); | |
5143 | static int intel_e09 PARAMS ((void)); | |
5144 | static int intel_e09_1 PARAMS ((void)); | |
5145 | static int intel_e10 PARAMS ((void)); | |
5146 | static int intel_e10_1 PARAMS ((void)); | |
5147 | static int intel_e11 PARAMS ((void)); | |
64a0c779 | 5148 | |
64a0c779 DN |
5149 | static int |
5150 | i386_intel_operand (operand_string, got_a_float) | |
5151 | char *operand_string; | |
5152 | int got_a_float; | |
5153 | { | |
5154 | int ret; | |
5155 | char *p; | |
5156 | ||
5157 | /* Initialize token holders. */ | |
5158 | cur_token.code = prev_token.code = T_NIL; | |
5159 | cur_token.reg = prev_token.reg = NULL; | |
5160 | cur_token.str = prev_token.str = NULL; | |
5161 | ||
5162 | /* Initialize parser structure. */ | |
e5cb08ac | 5163 | p = intel_parser.op_string = (char *) malloc (strlen (operand_string) + 1); |
64a0c779 DN |
5164 | if (p == NULL) |
5165 | abort (); | |
5166 | strcpy (intel_parser.op_string, operand_string); | |
5167 | intel_parser.got_a_float = got_a_float; | |
5168 | intel_parser.op_modifier = -1; | |
5169 | intel_parser.is_mem = 0; | |
5170 | intel_parser.reg = NULL; | |
e5cb08ac | 5171 | intel_parser.disp = (char *) malloc (strlen (operand_string) + 1); |
64a0c779 DN |
5172 | if (intel_parser.disp == NULL) |
5173 | abort (); | |
5174 | intel_parser.disp[0] = '\0'; | |
5175 | ||
5176 | /* Read the first token and start the parser. */ | |
5177 | intel_get_token (); | |
5178 | ret = intel_expr (); | |
5179 | ||
5180 | if (ret) | |
5181 | { | |
5182 | /* If we found a memory reference, hand it over to i386_displacement | |
5183 | to fill in the rest of the operand fields. */ | |
5184 | if (intel_parser.is_mem) | |
5185 | { | |
5186 | if ((i.mem_operands == 1 | |
5187 | && (current_templates->start->opcode_modifier & IsString) == 0) | |
5188 | || i.mem_operands == 2) | |
5189 | { | |
5190 | as_bad (_("too many memory references for '%s'"), | |
5191 | current_templates->start->name); | |
5192 | ret = 0; | |
5193 | } | |
5194 | else | |
5195 | { | |
5196 | char *s = intel_parser.disp; | |
5197 | i.mem_operands++; | |
5198 | ||
5199 | /* Add the displacement expression. */ | |
5200 | if (*s != '\0') | |
5201 | ret = i386_displacement (s, s + strlen (s)) | |
5202 | && i386_index_check (s); | |
5203 | } | |
5204 | } | |
5205 | ||
5206 | /* Constant and OFFSET expressions are handled by i386_immediate. */ | |
5207 | else if (intel_parser.op_modifier == OFFSET_FLAT | |
5208 | || intel_parser.reg == NULL) | |
5209 | ret = i386_immediate (intel_parser.disp); | |
5210 | } | |
5211 | ||
5212 | free (p); | |
5213 | free (intel_parser.disp); | |
5214 | ||
5215 | return ret; | |
5216 | } | |
5217 | ||
64a0c779 | 5218 | /* expr SHORT e05 |
b77a7acd | 5219 | | e05 */ |
64a0c779 DN |
5220 | static int |
5221 | intel_expr () | |
5222 | { | |
5223 | /* expr SHORT e05 */ | |
5224 | if (cur_token.code == T_SHORT) | |
5225 | { | |
5226 | intel_parser.op_modifier = SHORT; | |
5227 | intel_match_token (T_SHORT); | |
5228 | ||
5229 | return (intel_e05 ()); | |
5230 | } | |
5231 | ||
5232 | /* expr e05 */ | |
5233 | else | |
5234 | return intel_e05 (); | |
5235 | } | |
5236 | ||
64a0c779 DN |
5237 | /* e05 e06 e05' |
5238 | ||
4a1805b1 | 5239 | e05' addOp e06 e05' |
64a0c779 DN |
5240 | | Empty */ |
5241 | static int | |
5242 | intel_e05 () | |
5243 | { | |
5244 | return (intel_e06 () && intel_e05_1 ()); | |
5245 | } | |
5246 | ||
5247 | static int | |
5248 | intel_e05_1 () | |
5249 | { | |
5250 | /* e05' addOp e06 e05' */ | |
5251 | if (cur_token.code == '+' || cur_token.code == '-') | |
5252 | { | |
5253 | strcat (intel_parser.disp, cur_token.str); | |
5254 | intel_match_token (cur_token.code); | |
5255 | ||
5256 | return (intel_e06 () && intel_e05_1 ()); | |
5257 | } | |
5258 | ||
5259 | /* e05' Empty */ | |
5260 | else | |
5261 | return 1; | |
4a1805b1 | 5262 | } |
64a0c779 DN |
5263 | |
5264 | /* e06 e09 e06' | |
5265 | ||
5266 | e06' mulOp e09 e06' | |
b77a7acd | 5267 | | Empty */ |
64a0c779 DN |
5268 | static int |
5269 | intel_e06 () | |
5270 | { | |
5271 | return (intel_e09 () && intel_e06_1 ()); | |
5272 | } | |
5273 | ||
5274 | static int | |
5275 | intel_e06_1 () | |
5276 | { | |
5277 | /* e06' mulOp e09 e06' */ | |
5278 | if (cur_token.code == '*' || cur_token.code == '/') | |
5279 | { | |
5280 | strcat (intel_parser.disp, cur_token.str); | |
5281 | intel_match_token (cur_token.code); | |
5282 | ||
5283 | return (intel_e09 () && intel_e06_1 ()); | |
5284 | } | |
4a1805b1 | 5285 | |
64a0c779 | 5286 | /* e06' Empty */ |
4a1805b1 | 5287 | else |
64a0c779 DN |
5288 | return 1; |
5289 | } | |
5290 | ||
64a0c779 | 5291 | /* e09 OFFSET e10 e09' |
b77a7acd | 5292 | | e10 e09' |
64a0c779 DN |
5293 | |
5294 | e09' PTR e10 e09' | |
b77a7acd | 5295 | | : e10 e09' |
64a0c779 DN |
5296 | | Empty */ |
5297 | static int | |
5298 | intel_e09 () | |
5299 | { | |
5300 | /* e09 OFFSET e10 e09' */ | |
5301 | if (cur_token.code == T_OFFSET) | |
5302 | { | |
5303 | intel_parser.is_mem = 0; | |
5304 | intel_parser.op_modifier = OFFSET_FLAT; | |
5305 | intel_match_token (T_OFFSET); | |
5306 | ||
5307 | return (intel_e10 () && intel_e09_1 ()); | |
5308 | } | |
5309 | ||
5310 | /* e09 e10 e09' */ | |
5311 | else | |
5312 | return (intel_e10 () && intel_e09_1 ()); | |
5313 | } | |
5314 | ||
5315 | static int | |
5316 | intel_e09_1 () | |
5317 | { | |
5318 | /* e09' PTR e10 e09' */ | |
5319 | if (cur_token.code == T_PTR) | |
5320 | { | |
5321 | if (prev_token.code == T_BYTE) | |
5322 | i.suffix = BYTE_MNEM_SUFFIX; | |
5323 | ||
5324 | else if (prev_token.code == T_WORD) | |
5325 | { | |
5326 | if (intel_parser.got_a_float == 2) /* "fi..." */ | |
5327 | i.suffix = SHORT_MNEM_SUFFIX; | |
5328 | else | |
5329 | i.suffix = WORD_MNEM_SUFFIX; | |
5330 | } | |
5331 | ||
5332 | else if (prev_token.code == T_DWORD) | |
5333 | { | |
5334 | if (intel_parser.got_a_float == 1) /* "f..." */ | |
5335 | i.suffix = SHORT_MNEM_SUFFIX; | |
5336 | else | |
5337 | i.suffix = LONG_MNEM_SUFFIX; | |
5338 | } | |
5339 | ||
5340 | else if (prev_token.code == T_QWORD) | |
f16b83df JH |
5341 | { |
5342 | if (intel_parser.got_a_float == 1) /* "f..." */ | |
5343 | i.suffix = LONG_MNEM_SUFFIX; | |
5344 | else | |
3e73aa7c | 5345 | i.suffix = QWORD_MNEM_SUFFIX; |
f16b83df | 5346 | } |
64a0c779 DN |
5347 | |
5348 | else if (prev_token.code == T_XWORD) | |
5349 | i.suffix = LONG_DOUBLE_MNEM_SUFFIX; | |
5350 | ||
5351 | else | |
5352 | { | |
5353 | as_bad (_("Unknown operand modifier `%s'\n"), prev_token.str); | |
5354 | return 0; | |
5355 | } | |
5356 | ||
5357 | intel_match_token (T_PTR); | |
5358 | ||
5359 | return (intel_e10 () && intel_e09_1 ()); | |
5360 | } | |
5361 | ||
5362 | /* e09 : e10 e09' */ | |
5363 | else if (cur_token.code == ':') | |
5364 | { | |
21d6c4af DN |
5365 | /* Mark as a memory operand only if it's not already known to be an |
5366 | offset expression. */ | |
5367 | if (intel_parser.op_modifier != OFFSET_FLAT) | |
5368 | intel_parser.is_mem = 1; | |
64a0c779 DN |
5369 | |
5370 | return (intel_match_token (':') && intel_e10 () && intel_e09_1 ()); | |
5371 | } | |
5372 | ||
5373 | /* e09' Empty */ | |
5374 | else | |
5375 | return 1; | |
5376 | } | |
5377 | ||
5378 | /* e10 e11 e10' | |
5379 | ||
5380 | e10' [ expr ] e10' | |
b77a7acd | 5381 | | Empty */ |
64a0c779 DN |
5382 | static int |
5383 | intel_e10 () | |
5384 | { | |
5385 | return (intel_e11 () && intel_e10_1 ()); | |
5386 | } | |
5387 | ||
5388 | static int | |
5389 | intel_e10_1 () | |
5390 | { | |
5391 | /* e10' [ expr ] e10' */ | |
5392 | if (cur_token.code == '[') | |
5393 | { | |
5394 | intel_match_token ('['); | |
21d6c4af DN |
5395 | |
5396 | /* Mark as a memory operand only if it's not already known to be an | |
5397 | offset expression. If it's an offset expression, we need to keep | |
5398 | the brace in. */ | |
5399 | if (intel_parser.op_modifier != OFFSET_FLAT) | |
5400 | intel_parser.is_mem = 1; | |
5401 | else | |
5402 | strcat (intel_parser.disp, "["); | |
4a1805b1 | 5403 | |
64a0c779 | 5404 | /* Add a '+' to the displacement string if necessary. */ |
21d6c4af DN |
5405 | if (*intel_parser.disp != '\0' |
5406 | && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+') | |
64a0c779 DN |
5407 | strcat (intel_parser.disp, "+"); |
5408 | ||
21d6c4af DN |
5409 | if (intel_expr () && intel_match_token (']')) |
5410 | { | |
5411 | /* Preserve brackets when the operand is an offset expression. */ | |
5412 | if (intel_parser.op_modifier == OFFSET_FLAT) | |
5413 | strcat (intel_parser.disp, "]"); | |
5414 | ||
5415 | return intel_e10_1 (); | |
5416 | } | |
5417 | else | |
5418 | return 0; | |
64a0c779 DN |
5419 | } |
5420 | ||
5421 | /* e10' Empty */ | |
5422 | else | |
5423 | return 1; | |
5424 | } | |
5425 | ||
64a0c779 | 5426 | /* e11 ( expr ) |
b77a7acd | 5427 | | [ expr ] |
64a0c779 DN |
5428 | | BYTE |
5429 | | WORD | |
5430 | | DWORD | |
5431 | | QWORD | |
5432 | | XWORD | |
4a1805b1 | 5433 | | $ |
64a0c779 DN |
5434 | | . |
5435 | | register | |
5436 | | id | |
5437 | | constant */ | |
5438 | static int | |
5439 | intel_e11 () | |
5440 | { | |
5441 | /* e11 ( expr ) */ | |
5442 | if (cur_token.code == '(') | |
5443 | { | |
5444 | intel_match_token ('('); | |
5445 | strcat (intel_parser.disp, "("); | |
5446 | ||
5447 | if (intel_expr () && intel_match_token (')')) | |
e5cb08ac KH |
5448 | { |
5449 | strcat (intel_parser.disp, ")"); | |
5450 | return 1; | |
5451 | } | |
64a0c779 DN |
5452 | else |
5453 | return 0; | |
5454 | } | |
5455 | ||
5456 | /* e11 [ expr ] */ | |
5457 | else if (cur_token.code == '[') | |
5458 | { | |
5459 | intel_match_token ('['); | |
21d6c4af DN |
5460 | |
5461 | /* Mark as a memory operand only if it's not already known to be an | |
5462 | offset expression. If it's an offset expression, we need to keep | |
5463 | the brace in. */ | |
5464 | if (intel_parser.op_modifier != OFFSET_FLAT) | |
5465 | intel_parser.is_mem = 1; | |
5466 | else | |
5467 | strcat (intel_parser.disp, "["); | |
4a1805b1 | 5468 | |
64a0c779 DN |
5469 | /* Operands for jump/call inside brackets denote absolute addresses. */ |
5470 | if (current_templates->start->opcode_modifier & Jump | |
5471 | || current_templates->start->opcode_modifier & JumpDword | |
5472 | || current_templates->start->opcode_modifier & JumpByte | |
5473 | || current_templates->start->opcode_modifier & JumpInterSegment) | |
5474 | i.types[this_operand] |= JumpAbsolute; | |
5475 | ||
5476 | /* Add a '+' to the displacement string if necessary. */ | |
21d6c4af DN |
5477 | if (*intel_parser.disp != '\0' |
5478 | && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+') | |
64a0c779 DN |
5479 | strcat (intel_parser.disp, "+"); |
5480 | ||
21d6c4af DN |
5481 | if (intel_expr () && intel_match_token (']')) |
5482 | { | |
5483 | /* Preserve brackets when the operand is an offset expression. */ | |
5484 | if (intel_parser.op_modifier == OFFSET_FLAT) | |
5485 | strcat (intel_parser.disp, "]"); | |
5486 | ||
5487 | return 1; | |
5488 | } | |
5489 | else | |
5490 | return 0; | |
64a0c779 DN |
5491 | } |
5492 | ||
4a1805b1 | 5493 | /* e11 BYTE |
64a0c779 DN |
5494 | | WORD |
5495 | | DWORD | |
5496 | | QWORD | |
5497 | | XWORD */ | |
5498 | else if (cur_token.code == T_BYTE | |
5499 | || cur_token.code == T_WORD | |
5500 | || cur_token.code == T_DWORD | |
5501 | || cur_token.code == T_QWORD | |
5502 | || cur_token.code == T_XWORD) | |
5503 | { | |
5504 | intel_match_token (cur_token.code); | |
5505 | ||
5506 | return 1; | |
5507 | } | |
5508 | ||
5509 | /* e11 $ | |
5510 | | . */ | |
5511 | else if (cur_token.code == '$' || cur_token.code == '.') | |
5512 | { | |
5513 | strcat (intel_parser.disp, cur_token.str); | |
5514 | intel_match_token (cur_token.code); | |
21d6c4af DN |
5515 | |
5516 | /* Mark as a memory operand only if it's not already known to be an | |
5517 | offset expression. */ | |
5518 | if (intel_parser.op_modifier != OFFSET_FLAT) | |
5519 | intel_parser.is_mem = 1; | |
64a0c779 DN |
5520 | |
5521 | return 1; | |
5522 | } | |
5523 | ||
5524 | /* e11 register */ | |
5525 | else if (cur_token.code == T_REG) | |
5526 | { | |
5527 | const reg_entry *reg = intel_parser.reg = cur_token.reg; | |
5528 | ||
5529 | intel_match_token (T_REG); | |
5530 | ||
5531 | /* Check for segment change. */ | |
5532 | if (cur_token.code == ':') | |
5533 | { | |
5534 | if (reg->reg_type & (SReg2 | SReg3)) | |
5535 | { | |
5536 | switch (reg->reg_num) | |
5537 | { | |
5538 | case 0: | |
5539 | i.seg[i.mem_operands] = &es; | |
5540 | break; | |
5541 | case 1: | |
5542 | i.seg[i.mem_operands] = &cs; | |
5543 | break; | |
5544 | case 2: | |
5545 | i.seg[i.mem_operands] = &ss; | |
5546 | break; | |
5547 | case 3: | |
5548 | i.seg[i.mem_operands] = &ds; | |
5549 | break; | |
5550 | case 4: | |
5551 | i.seg[i.mem_operands] = &fs; | |
5552 | break; | |
5553 | case 5: | |
5554 | i.seg[i.mem_operands] = &gs; | |
5555 | break; | |
5556 | } | |
5557 | } | |
5558 | else | |
5559 | { | |
5560 | as_bad (_("`%s' is not a valid segment register"), reg->reg_name); | |
5561 | return 0; | |
5562 | } | |
5563 | } | |
5564 | ||
5565 | /* Not a segment register. Check for register scaling. */ | |
5566 | else if (cur_token.code == '*') | |
5567 | { | |
5568 | if (!intel_parser.is_mem) | |
5569 | { | |
5570 | as_bad (_("Register scaling only allowed in memory operands.")); | |
5571 | return 0; | |
5572 | } | |
5573 | ||
4a1805b1 | 5574 | /* What follows must be a valid scale. */ |
64a0c779 DN |
5575 | if (intel_match_token ('*') |
5576 | && strchr ("01248", *cur_token.str)) | |
5577 | { | |
5578 | i.index_reg = reg; | |
5579 | i.types[this_operand] |= BaseIndex; | |
5580 | ||
5581 | /* Set the scale after setting the register (otherwise, | |
5582 | i386_scale will complain) */ | |
5583 | i386_scale (cur_token.str); | |
5584 | intel_match_token (T_CONST); | |
5585 | } | |
5586 | else | |
5587 | { | |
5588 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
5589 | cur_token.str); | |
5590 | return 0; | |
5591 | } | |
5592 | } | |
5593 | ||
5594 | /* No scaling. If this is a memory operand, the register is either a | |
5595 | base register (first occurrence) or an index register (second | |
5596 | occurrence). */ | |
5597 | else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3))) | |
5598 | { | |
5599 | if (i.base_reg && i.index_reg) | |
5600 | { | |
5601 | as_bad (_("Too many register references in memory operand.\n")); | |
5602 | return 0; | |
5603 | } | |
5604 | ||
5605 | if (i.base_reg == NULL) | |
5606 | i.base_reg = reg; | |
5607 | else | |
5608 | i.index_reg = reg; | |
5609 | ||
5610 | i.types[this_operand] |= BaseIndex; | |
5611 | } | |
5612 | ||
5613 | /* Offset modifier. Add the register to the displacement string to be | |
5614 | parsed as an immediate expression after we're done. */ | |
5615 | else if (intel_parser.op_modifier == OFFSET_FLAT) | |
5616 | strcat (intel_parser.disp, reg->reg_name); | |
4a1805b1 | 5617 | |
64a0c779 DN |
5618 | /* It's neither base nor index nor offset. */ |
5619 | else | |
5620 | { | |
5621 | i.types[this_operand] |= reg->reg_type & ~BaseIndex; | |
5622 | i.op[this_operand].regs = reg; | |
5623 | i.reg_operands++; | |
5624 | } | |
5625 | ||
5626 | /* Since registers are not part of the displacement string (except | |
5627 | when we're parsing offset operands), we may need to remove any | |
5628 | preceding '+' from the displacement string. */ | |
5629 | if (*intel_parser.disp != '\0' | |
5630 | && intel_parser.op_modifier != OFFSET_FLAT) | |
5631 | { | |
5632 | char *s = intel_parser.disp; | |
5633 | s += strlen (s) - 1; | |
5634 | if (*s == '+') | |
5635 | *s = '\0'; | |
5636 | } | |
5637 | ||
5638 | return 1; | |
5639 | } | |
4a1805b1 | 5640 | |
64a0c779 DN |
5641 | /* e11 id */ |
5642 | else if (cur_token.code == T_ID) | |
5643 | { | |
5644 | /* Add the identifier to the displacement string. */ | |
5645 | strcat (intel_parser.disp, cur_token.str); | |
5646 | intel_match_token (T_ID); | |
5647 | ||
5648 | /* The identifier represents a memory reference only if it's not | |
5649 | preceded by an offset modifier. */ | |
21d6c4af | 5650 | if (intel_parser.op_modifier != OFFSET_FLAT) |
64a0c779 DN |
5651 | intel_parser.is_mem = 1; |
5652 | ||
5653 | return 1; | |
5654 | } | |
5655 | ||
5656 | /* e11 constant */ | |
5657 | else if (cur_token.code == T_CONST | |
e5cb08ac | 5658 | || cur_token.code == '-' |
64a0c779 DN |
5659 | || cur_token.code == '+') |
5660 | { | |
5661 | char *save_str; | |
5662 | ||
5663 | /* Allow constants that start with `+' or `-'. */ | |
5664 | if (cur_token.code == '-' || cur_token.code == '+') | |
5665 | { | |
5666 | strcat (intel_parser.disp, cur_token.str); | |
5667 | intel_match_token (cur_token.code); | |
5668 | if (cur_token.code != T_CONST) | |
5669 | { | |
5670 | as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"), | |
5671 | cur_token.str); | |
5672 | return 0; | |
5673 | } | |
5674 | } | |
5675 | ||
e5cb08ac | 5676 | save_str = (char *) malloc (strlen (cur_token.str) + 1); |
64a0c779 | 5677 | if (save_str == NULL) |
bc805888 | 5678 | abort (); |
64a0c779 DN |
5679 | strcpy (save_str, cur_token.str); |
5680 | ||
5681 | /* Get the next token to check for register scaling. */ | |
5682 | intel_match_token (cur_token.code); | |
5683 | ||
5684 | /* Check if this constant is a scaling factor for an index register. */ | |
5685 | if (cur_token.code == '*') | |
5686 | { | |
5687 | if (intel_match_token ('*') && cur_token.code == T_REG) | |
5688 | { | |
5689 | if (!intel_parser.is_mem) | |
5690 | { | |
5691 | as_bad (_("Register scaling only allowed in memory operands.")); | |
5692 | return 0; | |
5693 | } | |
5694 | ||
4a1805b1 | 5695 | /* The constant is followed by `* reg', so it must be |
64a0c779 DN |
5696 | a valid scale. */ |
5697 | if (strchr ("01248", *save_str)) | |
5698 | { | |
5699 | i.index_reg = cur_token.reg; | |
5700 | i.types[this_operand] |= BaseIndex; | |
5701 | ||
5702 | /* Set the scale after setting the register (otherwise, | |
5703 | i386_scale will complain) */ | |
5704 | i386_scale (save_str); | |
5705 | intel_match_token (T_REG); | |
5706 | ||
5707 | /* Since registers are not part of the displacement | |
5708 | string, we may need to remove any preceding '+' from | |
5709 | the displacement string. */ | |
5710 | if (*intel_parser.disp != '\0') | |
5711 | { | |
5712 | char *s = intel_parser.disp; | |
5713 | s += strlen (s) - 1; | |
5714 | if (*s == '+') | |
5715 | *s = '\0'; | |
5716 | } | |
5717 | ||
5718 | free (save_str); | |
5719 | ||
5720 | return 1; | |
5721 | } | |
5722 | else | |
5723 | return 0; | |
5724 | } | |
5725 | ||
5726 | /* The constant was not used for register scaling. Since we have | |
5727 | already consumed the token following `*' we now need to put it | |
5728 | back in the stream. */ | |
5729 | else | |
5730 | intel_putback_token (); | |
5731 | } | |
5732 | ||
5733 | /* Add the constant to the displacement string. */ | |
5734 | strcat (intel_parser.disp, save_str); | |
5735 | free (save_str); | |
5736 | ||
5737 | return 1; | |
5738 | } | |
5739 | ||
64a0c779 DN |
5740 | as_bad (_("Unrecognized token '%s'"), cur_token.str); |
5741 | return 0; | |
5742 | } | |
5743 | ||
64a0c779 DN |
5744 | /* Match the given token against cur_token. If they match, read the next |
5745 | token from the operand string. */ | |
5746 | static int | |
5747 | intel_match_token (code) | |
e5cb08ac | 5748 | int code; |
64a0c779 DN |
5749 | { |
5750 | if (cur_token.code == code) | |
5751 | { | |
5752 | intel_get_token (); | |
5753 | return 1; | |
5754 | } | |
5755 | else | |
5756 | { | |
5757 | as_bad (_("Unexpected token `%s'\n"), cur_token.str); | |
5758 | return 0; | |
5759 | } | |
5760 | } | |
5761 | ||
64a0c779 DN |
5762 | /* Read a new token from intel_parser.op_string and store it in cur_token. */ |
5763 | static void | |
5764 | intel_get_token () | |
5765 | { | |
5766 | char *end_op; | |
5767 | const reg_entry *reg; | |
5768 | struct intel_token new_token; | |
5769 | ||
5770 | new_token.code = T_NIL; | |
5771 | new_token.reg = NULL; | |
5772 | new_token.str = NULL; | |
5773 | ||
4a1805b1 | 5774 | /* Free the memory allocated to the previous token and move |
64a0c779 DN |
5775 | cur_token to prev_token. */ |
5776 | if (prev_token.str) | |
5777 | free (prev_token.str); | |
5778 | ||
5779 | prev_token = cur_token; | |
5780 | ||
5781 | /* Skip whitespace. */ | |
5782 | while (is_space_char (*intel_parser.op_string)) | |
5783 | intel_parser.op_string++; | |
5784 | ||
5785 | /* Return an empty token if we find nothing else on the line. */ | |
5786 | if (*intel_parser.op_string == '\0') | |
5787 | { | |
5788 | cur_token = new_token; | |
5789 | return; | |
5790 | } | |
5791 | ||
5792 | /* The new token cannot be larger than the remainder of the operand | |
5793 | string. */ | |
e5cb08ac | 5794 | new_token.str = (char *) malloc (strlen (intel_parser.op_string) + 1); |
64a0c779 | 5795 | if (new_token.str == NULL) |
bc805888 | 5796 | abort (); |
64a0c779 DN |
5797 | new_token.str[0] = '\0'; |
5798 | ||
5799 | if (strchr ("0123456789", *intel_parser.op_string)) | |
5800 | { | |
5801 | char *p = new_token.str; | |
5802 | char *q = intel_parser.op_string; | |
5803 | new_token.code = T_CONST; | |
5804 | ||
5805 | /* Allow any kind of identifier char to encompass floating point and | |
5806 | hexadecimal numbers. */ | |
5807 | while (is_identifier_char (*q)) | |
5808 | *p++ = *q++; | |
5809 | *p = '\0'; | |
5810 | ||
5811 | /* Recognize special symbol names [0-9][bf]. */ | |
5812 | if (strlen (intel_parser.op_string) == 2 | |
4a1805b1 | 5813 | && (intel_parser.op_string[1] == 'b' |
64a0c779 DN |
5814 | || intel_parser.op_string[1] == 'f')) |
5815 | new_token.code = T_ID; | |
5816 | } | |
5817 | ||
5818 | else if (strchr ("+-/*:[]()", *intel_parser.op_string)) | |
5819 | { | |
5820 | new_token.code = *intel_parser.op_string; | |
5821 | new_token.str[0] = *intel_parser.op_string; | |
5822 | new_token.str[1] = '\0'; | |
5823 | } | |
5824 | ||
5825 | else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg) | |
5826 | && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)) | |
5827 | { | |
5828 | new_token.code = T_REG; | |
5829 | new_token.reg = reg; | |
5830 | ||
5831 | if (*intel_parser.op_string == REGISTER_PREFIX) | |
5832 | { | |
5833 | new_token.str[0] = REGISTER_PREFIX; | |
5834 | new_token.str[1] = '\0'; | |
5835 | } | |
5836 | ||
5837 | strcat (new_token.str, reg->reg_name); | |
5838 | } | |
5839 | ||
5840 | else if (is_identifier_char (*intel_parser.op_string)) | |
5841 | { | |
5842 | char *p = new_token.str; | |
5843 | char *q = intel_parser.op_string; | |
5844 | ||
5845 | /* A '.' or '$' followed by an identifier char is an identifier. | |
5846 | Otherwise, it's operator '.' followed by an expression. */ | |
5847 | if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1))) | |
5848 | { | |
5849 | new_token.code = *q; | |
5850 | new_token.str[0] = *q; | |
5851 | new_token.str[1] = '\0'; | |
5852 | } | |
5853 | else | |
5854 | { | |
5855 | while (is_identifier_char (*q) || *q == '@') | |
5856 | *p++ = *q++; | |
5857 | *p = '\0'; | |
5858 | ||
5859 | if (strcasecmp (new_token.str, "BYTE") == 0) | |
5860 | new_token.code = T_BYTE; | |
5861 | ||
5862 | else if (strcasecmp (new_token.str, "WORD") == 0) | |
5863 | new_token.code = T_WORD; | |
5864 | ||
5865 | else if (strcasecmp (new_token.str, "DWORD") == 0) | |
5866 | new_token.code = T_DWORD; | |
5867 | ||
5868 | else if (strcasecmp (new_token.str, "QWORD") == 0) | |
5869 | new_token.code = T_QWORD; | |
5870 | ||
5871 | else if (strcasecmp (new_token.str, "XWORD") == 0) | |
5872 | new_token.code = T_XWORD; | |
5873 | ||
5874 | else if (strcasecmp (new_token.str, "PTR") == 0) | |
5875 | new_token.code = T_PTR; | |
5876 | ||
5877 | else if (strcasecmp (new_token.str, "SHORT") == 0) | |
5878 | new_token.code = T_SHORT; | |
5879 | ||
5880 | else if (strcasecmp (new_token.str, "OFFSET") == 0) | |
5881 | { | |
5882 | new_token.code = T_OFFSET; | |
5883 | ||
5884 | /* ??? This is not mentioned in the MASM grammar but gcc | |
5885 | makes use of it with -mintel-syntax. OFFSET may be | |
5886 | followed by FLAT: */ | |
5887 | if (strncasecmp (q, " FLAT:", 6) == 0) | |
5888 | strcat (new_token.str, " FLAT:"); | |
5889 | } | |
5890 | ||
5891 | /* ??? This is not mentioned in the MASM grammar. */ | |
5892 | else if (strcasecmp (new_token.str, "FLAT") == 0) | |
5893 | new_token.code = T_OFFSET; | |
5894 | ||
5895 | else | |
5896 | new_token.code = T_ID; | |
5897 | } | |
5898 | } | |
5899 | ||
5900 | else | |
5901 | as_bad (_("Unrecognized token `%s'\n"), intel_parser.op_string); | |
5902 | ||
5903 | intel_parser.op_string += strlen (new_token.str); | |
5904 | cur_token = new_token; | |
5905 | } | |
5906 | ||
64a0c779 DN |
5907 | /* Put cur_token back into the token stream and make cur_token point to |
5908 | prev_token. */ | |
5909 | static void | |
5910 | intel_putback_token () | |
5911 | { | |
5912 | intel_parser.op_string -= strlen (cur_token.str); | |
5913 | free (cur_token.str); | |
5914 | cur_token = prev_token; | |
4a1805b1 | 5915 | |
64a0c779 DN |
5916 | /* Forget prev_token. */ |
5917 | prev_token.code = T_NIL; | |
5918 | prev_token.reg = NULL; | |
5919 | prev_token.str = NULL; | |
5920 | } |