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i386: Append ".p2align 4,0" to gas tests
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
219d1afa 2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d 68#define LOCK_PREFIX 5
4e9ac44a
L		 69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
6305a203
L		 84/* Intel Syntax. Use a non-ascii letter since since it never appears
85 in instructions. */
86#define LONG_DOUBLE_MNEM_SUFFIX '\1'
87
88#define END_OF_INSN '\0'
89
90/*
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
95 END.
96 */
97typedef struct
98{
d3ce72d0
NC		 99 const insn_template *start;
100 const insn_template *end;
6305a203
L		 101}
102templates;
103
104/* 386 operand encoding bytes: see 386 book for details of this. */
105typedef struct
106{
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
110}
111modrm_byte;
112
113/* x86-64 extension prefix. */
114typedef int rex_byte;
115
6305a203
L		 116/* 386 opcode byte to code indirect addressing. */
117typedef struct
118{
119 unsigned base;
120 unsigned index;
121 unsigned scale;
122}
123sib_byte;
124
6305a203
L		 125/* x86 arch names, types and features */
126typedef struct
127{
128 const char *name; /* arch name */
8a2c8fef 129 unsigned int len; /* arch string length */
6305a203
L		 130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 132 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 133}
134arch_entry;
135
293f5f65
L		 136/* Used to turn off indicated flags. */
137typedef struct
138{
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
142}
143noarch_entry;
144
78f12dd3 145static void update_code_flag (int, int);
e3bb37b5
L		 146static void set_code_flag (int);
147static void set_16bit_gcc_code_flag (int);
148static void set_intel_syntax (int);
1efbbeb4 149static void set_intel_mnemonic (int);
db51cc60 150static void set_allow_index_reg (int);
7bab8ab5 151static void set_check (int);
e3bb37b5 152static void set_cpu_arch (int);
6482c264 153#ifdef TE_PE
e3bb37b5 154static void pe_directive_secrel (int);
6482c264 155#endif
e3bb37b5
L		 156static void signed_cons (int);
157static char *output_invalid (int c);
ee86248c
JB		 158static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
159 const char *);
160static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
161 const char *);
a7619375 162static int i386_att_operand (char *);
e3bb37b5 163static int i386_intel_operand (char *, int);
ee86248c
JB		 164static int i386_intel_simplify (expressionS *);
165static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 166static const reg_entry *parse_register (char *, char **);
167static char *parse_insn (char *, char *);
168static char *parse_operands (char *, const char *);
169static void swap_operands (void);
4d456e3d 170static void swap_2_operands (int, int);
e3bb37b5
L		 171static void optimize_imm (void);
172static void optimize_disp (void);
83b16ac6 173static const insn_template *match_template (char);
e3bb37b5
L		 174static int check_string (void);
175static int process_suffix (void);
176static int check_byte_reg (void);
177static int check_long_reg (void);
178static int check_qword_reg (void);
179static int check_word_reg (void);
180static int finalize_imm (void);
181static int process_operands (void);
182static const seg_entry *build_modrm_byte (void);
183static void output_insn (void);
184static void output_imm (fragS *, offsetT);
185static void output_disp (fragS *, offsetT);
29b0f896 186#ifndef I386COFF
e3bb37b5 187static void s_bss (int);
252b5132 188#endif
17d4e2a2
L		 189#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190static void handle_large_common (int small ATTRIBUTE_UNUSED);
191#endif
252b5132 192
a847613f 193static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 194
43234a1e
L		 195/* This struct describes rounding control and SAE in the instruction. */
196struct RC_Operation
197{
198 enum rc_type
199 {
200 rne = 0,
201 rd,
202 ru,
203 rz,
204 saeonly
205 } type;
206 int operand;
207};
208
209static struct RC_Operation rc_op;
210
211/* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214struct Mask_Operation
215{
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
219 int operand;
220};
221
222static struct Mask_Operation mask_op;
223
224/* The struct describes broadcasting, applied to OPERAND. FACTOR is
225 broadcast factor. */
226struct Broadcast_Operation
227{
8e6e0792 228 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
43234a1e
L		 229 int type;
230
231 /* Index of broadcasted operand. */
232 int operand;
233};
234
235static struct Broadcast_Operation broadcast_op;
236
c0f3af97
L		 237/* VEX prefix. */
238typedef struct
239{
43234a1e
L		 240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes[4];
c0f3af97
L		 242 unsigned int length;
243 /* Destination or source register specifier. */
244 const reg_entry *register_specifier;
245} vex_prefix;
246
252b5132 247/* 'md_assemble ()' gathers together information and puts it into a
47926f60 248 i386_insn. */
252b5132 249
520dc8e8
AM		 250union i386_op
251 {
252 expressionS *disps;
253 expressionS *imms;
254 const reg_entry *regs;
255 };
256
a65babc9
L		 257enum i386_error
258 {
86e026a4 259 operand_size_mismatch,
a65babc9
L		 260 operand_type_mismatch,
261 register_type_mismatch,
262 number_of_operands_mismatch,
263 invalid_instruction_suffix,
264 bad_imm4,
a65babc9
L		 265 unsupported_with_intel_mnemonic,
266 unsupported_syntax,
6c30d220
L		 267 unsupported,
268 invalid_vsib_address,
7bab8ab5 269 invalid_vector_register_set,
43234a1e
L		 270 unsupported_vector_index_register,
271 unsupported_broadcast,
272 broadcast_not_on_src_operand,
273 broadcast_needed,
274 unsupported_masking,
275 mask_not_on_destination,
276 no_default_mask,
277 unsupported_rc_sae,
278 rc_sae_operand_not_last_imm,
279 invalid_register_operand,
a65babc9
L		 280 };
281
252b5132
RH		 282struct _i386_insn
283 {
47926f60 284 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 285 insn_template tm;
252b5132 286
7d5e4556
L		 287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
252b5132
RH		 289 char suffix;
290
47926f60 291 /* OPERANDS gives the number of given operands. */
252b5132
RH		 292 unsigned int operands;
293
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
47926f60 296 operands. */
252b5132
RH		 297 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
298
299 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 300 use OP[i] for the corresponding operand. */
40fb9820 301 i386_operand_type types[MAX_OPERANDS];
252b5132 302
520dc8e8
AM		 303 /* Displacement expression, immediate expression, or register for each
304 operand. */
305 union i386_op op[MAX_OPERANDS];
252b5132 306
3e73aa7c
JH		 307 /* Flags for operands. */
308 unsigned int flags[MAX_OPERANDS];
309#define Operand_PCrel 1
310
252b5132 311 /* Relocation type for operand */
f86103b7 312 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 313
252b5132
RH		 314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry *base_reg;
317 const reg_entry *index_reg;
318 unsigned int log2_scale_factor;
319
320 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 321 explicit segment overrides are given. */
ce8a8b2f 322 const seg_entry *seg[2];
252b5132 323
8325cc63
JB		 324 /* Copied first memory operand string, for re-checking. */
325 char *memop1_string;
326
252b5132
RH		 327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes;
330 unsigned char prefix[MAX_PREFIXES];
331
332 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 333 addressing modes of this insn are encoded. */
252b5132 334 modrm_byte rm;
3e73aa7c 335 rex_byte rex;
43234a1e 336 rex_byte vrex;
252b5132 337 sib_byte sib;
c0f3af97 338 vex_prefix vex;
b6169b20 339
43234a1e
L		 340 /* Masking attributes. */
341 struct Mask_Operation *mask;
342
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation *rounding;
345
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation *broadcast;
348
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift;
351
86fa6981
L		 352 /* Prefer load or store in encoding. */
353 enum
354 {
355 dir_encoding_default = 0,
356 dir_encoding_load,
357 dir_encoding_store
358 } dir_encoding;
891edac4 359
a501d77e
L		 360 /* Prefer 8bit or 32bit displacement in encoding. */
361 enum
362 {
363 disp_encoding_default = 0,
364 disp_encoding_8bit,
365 disp_encoding_32bit
366 } disp_encoding;
f8a5c266 367
6b6b6807
L		 368 /* Prefer the REX byte in encoding. */
369 bfd_boolean rex_encoding;
370
b6f8c7c4
L		 371 /* Disable instruction size optimization. */
372 bfd_boolean no_optimize;
373
86fa6981
L		 374 /* How to encode vector instructions. */
375 enum
376 {
377 vex_encoding_default = 0,
378 vex_encoding_vex2,
379 vex_encoding_vex3,
380 vex_encoding_evex
381 } vec_encoding;
382
d5de92cf
L		 383 /* REP prefix. */
384 const char *rep_prefix;
385
165de32a
L		 386 /* HLE prefix. */
387 const char *hle_prefix;
42164a71 388
7e8b059b
L		 389 /* Have BND prefix. */
390 const char *bnd_prefix;
391
04ef582a
L		 392 /* Have NOTRACK prefix. */
393 const char *notrack_prefix;
394
891edac4 395 /* Error message. */
a65babc9 396 enum i386_error error;
252b5132
RH		 397 };
398
399typedef struct _i386_insn i386_insn;
400
43234a1e
L		 401/* Link RC type with corresponding string, that'll be looked for in
402 asm. */
403struct RC_name
404{
405 enum rc_type type;
406 const char *name;
407 unsigned int len;
408};
409
410static const struct RC_name RC_NamesTable[] =
411{
412 { rne, STRING_COMMA_LEN ("rn-sae") },
413 { rd, STRING_COMMA_LEN ("rd-sae") },
414 { ru, STRING_COMMA_LEN ("ru-sae") },
415 { rz, STRING_COMMA_LEN ("rz-sae") },
416 { saeonly, STRING_COMMA_LEN ("sae") },
417};
418
252b5132
RH		 419/* List of chars besides those in app.c:symbol_chars that can start an
420 operand. Used to prevent the scrubber eating vital white-space. */
86fa6981 421const char extra_symbol_chars[] = "*%-([{}"
252b5132 422#ifdef LEX_AT
32137342
NC		 423 "@"
424#endif
425#ifdef LEX_QM
426 "?"
252b5132 427#endif
32137342 428 ;
252b5132 429
29b0f896
AM		 430#if (defined (TE_I386AIX) \
431 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 432 && !defined (TE_GNU) \
29b0f896 433 && !defined (TE_LINUX) \
8d63c93e 434 && !defined (TE_NACL) \
29b0f896 435 && !defined (TE_FreeBSD) \
5b806d27 436 && !defined (TE_DragonFly) \
29b0f896 437 && !defined (TE_NetBSD)))
252b5132 438/* This array holds the chars that always start a comment. If the
b3b91714
AM		 439 pre-processor is disabled, these aren't very useful. The option
440 --divide will remove '/' from this list. */
441const char *i386_comment_chars = "#/";
442#define SVR4_COMMENT_CHARS 1
252b5132 443#define PREFIX_SEPARATOR '\\'
252b5132 444
b3b91714
AM		 445#else
446const char *i386_comment_chars = "#";
447#define PREFIX_SEPARATOR '/'
448#endif
449
252b5132
RH		 450/* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 452 .line and .file directives will appear in the pre-processed output.
453 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 454 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 455 #NO_APP at the beginning of its output.
456 Also note that comments started like this one will always work if
252b5132 457 '/' isn't otherwise defined. */
b3b91714 458const char line_comment_chars[] = "#/";
252b5132 459
63a0b638 460const char line_separator_chars[] = ";";
252b5132 461
ce8a8b2f
AM		 462/* Chars that can be used to separate mant from exp in floating point
463 nums. */
252b5132
RH		 464const char EXP_CHARS[] = "eE";
465
ce8a8b2f
AM		 466/* Chars that mean this number is a floating point constant
467 As in 0f12.456
468 or 0d1.2345e12. */
252b5132
RH		 469const char FLT_CHARS[] = "fFdDxX";
470
ce8a8b2f 471/* Tables for lexical analysis. */
252b5132
RH		 472static char mnemonic_chars[256];
473static char register_chars[256];
474static char operand_chars[256];
475static char identifier_chars[256];
476static char digit_chars[256];
477
ce8a8b2f 478/* Lexical macros. */
252b5132
RH		 479#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
480#define is_operand_char(x) (operand_chars[(unsigned char) x])
481#define is_register_char(x) (register_chars[(unsigned char) x])
482#define is_space_char(x) ((x) == ' ')
483#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
484#define is_digit_char(x) (digit_chars[(unsigned char) x])
485
0234cb7c 486/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 487static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
488
489/* md_assemble() always leaves the strings it's passed unaltered. To
490 effect this we maintain a stack of saved characters that we've smashed
491 with '\0's (indicating end of strings for various sub-fields of the
47926f60 492 assembler instruction). */
252b5132 493static char save_stack[32];
ce8a8b2f 494static char *save_stack_p;
252b5132
RH		 495#define END_STRING_AND_SAVE(s) \
496 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
497#define RESTORE_END_STRING(s) \
498 do { *(s) = *--save_stack_p; } while (0)
499
47926f60 500/* The instruction we're assembling. */
252b5132
RH		 501static i386_insn i;
502
503/* Possible templates for current insn. */
504static const templates *current_templates;
505
31b2323c
L		 506/* Per instruction expressionS buffers: max displacements & immediates. */
507static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
508static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 509
47926f60 510/* Current operand we are working on. */
ee86248c 511static int this_operand = -1;
252b5132 512
3e73aa7c
JH		 513/* We support four different modes. FLAG_CODE variable is used to distinguish
514 these. */
515
516enum flag_code {
517 CODE_32BIT,
518 CODE_16BIT,
519 CODE_64BIT };
520
521static enum flag_code flag_code;
4fa24527 522static unsigned int object_64bit;
862be3fb 523static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 524static int use_rela_relocations = 0;
525
7af8ed2d
NC		 526#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
527 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
528 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
529
351f65ca
L		 530/* The ELF ABI to use. */
531enum x86_elf_abi
532{
533 I386_ABI,
7f56bc95
L		 534 X86_64_ABI,
535 X86_64_X32_ABI
351f65ca
L		 536};
537
538static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 539#endif
351f65ca 540
167ad85b
TG		 541#if defined (TE_PE) || defined (TE_PEP)
542/* Use big object file format. */
543static int use_big_obj = 0;
544#endif
545
8dcea932
L		 546#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547/* 1 if generating code for a shared library. */
548static int shared = 0;
549#endif
550
47926f60
KH		 551/* 1 for intel syntax,
552 0 if att syntax. */
553static int intel_syntax = 0;
252b5132 554
e89c5eaa
L		 555/* 1 for Intel64 ISA,
556 0 if AMD64 ISA. */
557static int intel64;
558
1efbbeb4
L		 559/* 1 for intel mnemonic,
560 0 if att mnemonic. */
561static int intel_mnemonic = !SYSV386_COMPAT;
562
a60de03c
JB		 563/* 1 if pseudo registers are permitted. */
564static int allow_pseudo_reg = 0;
565
47926f60
KH		 566/* 1 if register prefix % not required. */
567static int allow_naked_reg = 0;
252b5132 568
33eaf5de 569/* 1 if the assembler should add BND prefix for all control-transferring
7e8b059b
L		 570 instructions supporting it, even if this prefix wasn't specified
571 explicitly. */
572static int add_bnd_prefix = 0;
573
ba104c83 574/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 575static int allow_index_reg = 0;
576
d022bddd
IT		 577/* 1 if the assembler should ignore LOCK prefix, even if it was
578 specified explicitly. */
579static int omit_lock_prefix = 0;
580
e4e00185
AS		 581/* 1 if the assembler should encode lfence, mfence, and sfence as
582 "lock addl $0, (%{re}sp)". */
583static int avoid_fence = 0;
584
0cb4071e
L		 585/* 1 if the assembler should generate relax relocations. */
586
587static int generate_relax_relocations
588 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
589
7bab8ab5 590static enum check_kind
daf50ae7 591 {
7bab8ab5
JB		 592 check_none = 0,
593 check_warning,
594 check_error
daf50ae7 595 }
7bab8ab5 596sse_check, operand_check = check_warning;
daf50ae7 597
b6f8c7c4
L		 598/* Optimization:
599 1. Clear the REX_W bit with register operand if possible.
600 2. Above plus use 128bit vector instruction to clear the full vector
601 register.
602 */
603static int optimize = 0;
604
605/* Optimization:
606 1. Clear the REX_W bit with register operand if possible.
607 2. Above plus use 128bit vector instruction to clear the full vector
608 register.
609 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
610 "testb $imm7,%r8".
611 */
612static int optimize_for_space = 0;
613
2ca3ace5
L		 614/* Register prefix used for error message. */
615static const char *register_prefix = "%";
616
47926f60
KH		 617/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
618 leave, push, and pop instructions so that gcc has the same stack
619 frame as in 32 bit mode. */
620static char stackop_size = '\0';
eecb386c 621
12b55ccc
L		 622/* Non-zero to optimize code alignment. */
623int optimize_align_code = 1;
624
47926f60
KH		 625/* Non-zero to quieten some warnings. */
626static int quiet_warnings = 0;
a38cf1db 627
47926f60
KH		 628/* CPU name. */
629static const char *cpu_arch_name = NULL;
6305a203 630static char *cpu_sub_arch_name = NULL;
a38cf1db 631
47926f60 632/* CPU feature flags. */
40fb9820
L		 633static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
634
ccc9c027
L		 635/* If we have selected a cpu we are generating instructions for. */
636static int cpu_arch_tune_set = 0;
637
9103f4f4 638/* Cpu we are generating instructions for. */
fbf3f584 639enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 640
641/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 642static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 643
ccc9c027 644/* CPU instruction set architecture used. */
fbf3f584 645enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 646
9103f4f4 647/* CPU feature flags of instruction set architecture used. */
fbf3f584 648i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 649
fddf5b5b
AM		 650/* If set, conditional jumps are not automatically promoted to handle
651 larger than a byte offset. */
652static unsigned int no_cond_jump_promotion = 0;
653
c0f3af97
L		 654/* Encode SSE instructions with VEX prefix. */
655static unsigned int sse2avx;
656
539f890d
L		 657/* Encode scalar AVX instructions with specific vector length. */
658static enum
659 {
660 vex128 = 0,
661 vex256
662 } avxscalar;
663
43234a1e
L		 664/* Encode scalar EVEX LIG instructions with specific vector length. */
665static enum
666 {
667 evexl128 = 0,
668 evexl256,
669 evexl512
670 } evexlig;
671
672/* Encode EVEX WIG instructions with specific evex.w. */
673static enum
674 {
675 evexw0 = 0,
676 evexw1
677 } evexwig;
678
d3d3c6db
IT		 679/* Value to encode in EVEX RC bits, for SAE-only instructions. */
680static enum rc_type evexrcig = rne;
681
29b0f896 682/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 683static symbolS *GOT_symbol;
29b0f896 684
a4447b93
RH		 685/* The dwarf2 return column, adjusted for 32 or 64 bit. */
686unsigned int x86_dwarf2_return_column;
687
688/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
689int x86_cie_data_alignment;
690
252b5132 691/* Interface to relax_segment.
fddf5b5b
AM		 692 There are 3 major relax states for 386 jump insns because the
693 different types of jumps add different sizes to frags when we're
694 figuring out what sort of jump to choose to reach a given label. */
252b5132 695
47926f60 696/* Types. */
93c2a809
AM		 697#define UNCOND_JUMP 0
698#define COND_JUMP 1
699#define COND_JUMP86 2
fddf5b5b 700
47926f60 701/* Sizes. */
252b5132
RH		 702#define CODE16 1
703#define SMALL 0
29b0f896 704#define SMALL16 (SMALL | CODE16)
252b5132 705#define BIG 2
29b0f896 706#define BIG16 (BIG | CODE16)
252b5132
RH		 707
708#ifndef INLINE
709#ifdef __GNUC__
710#define INLINE __inline__
711#else
712#define INLINE
713#endif
714#endif
715
fddf5b5b
AM		 716#define ENCODE_RELAX_STATE(type, size) \
717 ((relax_substateT) (((type) << 2) | (size)))
718#define TYPE_FROM_RELAX_STATE(s) \
719 ((s) >> 2)
720#define DISP_SIZE_FROM_RELAX_STATE(s) \
721 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 722
723/* This table is used by relax_frag to promote short jumps to long
724 ones where necessary. SMALL (short) jumps may be promoted to BIG
725 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
726 don't allow a short jump in a 32 bit code segment to be promoted to
727 a 16 bit offset jump because it's slower (requires data size
728 prefix), and doesn't work, unless the destination is in the bottom
729 64k of the code segment (The top 16 bits of eip are zeroed). */
730
731const relax_typeS md_relax_table[] =
732{
24eab124
AM		 733 /* The fields are:
734 1) most positive reach of this state,
735 2) most negative reach of this state,
93c2a809 736 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 737 4) which index into the table to try if we can't fit into this one. */
252b5132 738
fddf5b5b 739 /* UNCOND_JUMP states. */
93c2a809
AM		 740 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
741 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
742 /* dword jmp adds 4 bytes to frag:
743 0 extra opcode bytes, 4 displacement bytes. */
252b5132 744 {0, 0, 4, 0},
93c2a809
AM		 745 /* word jmp adds 2 byte2 to frag:
746 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 747 {0, 0, 2, 0},
748
93c2a809
AM		 749 /* COND_JUMP states. */
750 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
751 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
752 /* dword conditionals adds 5 bytes to frag:
753 1 extra opcode byte, 4 displacement bytes. */
754 {0, 0, 5, 0},
fddf5b5b 755 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 756 1 extra opcode byte, 2 displacement bytes. */
757 {0, 0, 3, 0},
758
759 /* COND_JUMP86 states. */
760 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
761 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
762 /* dword conditionals adds 5 bytes to frag:
763 1 extra opcode byte, 4 displacement bytes. */
764 {0, 0, 5, 0},
765 /* word conditionals add 4 bytes to frag:
766 1 displacement byte and a 3 byte long branch insn. */
767 {0, 0, 4, 0}
252b5132
RH		 768};
769
9103f4f4
L		 770static const arch_entry cpu_arch[] =
771{
89507696
JB		 772 /* Do not replace the first two entries - i386_target_format()
773 relies on them being there in this order. */
8a2c8fef 774 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 775 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 776 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 777 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 778 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 779 CPU_NONE_FLAGS, 0 },
8a2c8fef 780 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 781 CPU_I186_FLAGS, 0 },
8a2c8fef 782 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 783 CPU_I286_FLAGS, 0 },
8a2c8fef 784 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 785 CPU_I386_FLAGS, 0 },
8a2c8fef 786 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 787 CPU_I486_FLAGS, 0 },
8a2c8fef 788 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 789 CPU_I586_FLAGS, 0 },
8a2c8fef 790 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 791 CPU_I686_FLAGS, 0 },
8a2c8fef 792 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 793 CPU_I586_FLAGS, 0 },
8a2c8fef 794 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 795 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 796 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 797 CPU_P2_FLAGS, 0 },
8a2c8fef 798 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 799 CPU_P3_FLAGS, 0 },
8a2c8fef 800 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 801 CPU_P4_FLAGS, 0 },
8a2c8fef 802 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 803 CPU_CORE_FLAGS, 0 },
8a2c8fef 804 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 805 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 806 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 807 CPU_CORE_FLAGS, 1 },
8a2c8fef 808 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 809 CPU_CORE_FLAGS, 0 },
8a2c8fef 810 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 811 CPU_CORE2_FLAGS, 1 },
8a2c8fef 812 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 813 CPU_CORE2_FLAGS, 0 },
8a2c8fef 814 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 815 CPU_COREI7_FLAGS, 0 },
8a2c8fef 816 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 817 CPU_L1OM_FLAGS, 0 },
7a9068fe 818 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 819 CPU_K1OM_FLAGS, 0 },
81486035 820 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 821 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 822 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 823 CPU_K6_FLAGS, 0 },
8a2c8fef 824 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 825 CPU_K6_2_FLAGS, 0 },
8a2c8fef 826 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 827 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 828 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 829 CPU_K8_FLAGS, 1 },
8a2c8fef 830 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 831 CPU_K8_FLAGS, 0 },
8a2c8fef 832 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 833 CPU_K8_FLAGS, 0 },
8a2c8fef 834 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 835 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 836 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 837 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 838 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 839 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 840 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 841 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 842 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 843 CPU_BDVER4_FLAGS, 0 },
029f3522 844 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 845 CPU_ZNVER1_FLAGS, 0 },
7b458c12 846 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 847 CPU_BTVER1_FLAGS, 0 },
7b458c12 848 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 849 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 850 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 851 CPU_8087_FLAGS, 0 },
8a2c8fef 852 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 853 CPU_287_FLAGS, 0 },
8a2c8fef 854 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 855 CPU_387_FLAGS, 0 },
1848e567
L		 856 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
857 CPU_687_FLAGS, 0 },
8a2c8fef 858 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 859 CPU_MMX_FLAGS, 0 },
8a2c8fef 860 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 861 CPU_SSE_FLAGS, 0 },
8a2c8fef 862 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 863 CPU_SSE2_FLAGS, 0 },
8a2c8fef 864 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 865 CPU_SSE3_FLAGS, 0 },
8a2c8fef 866 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 867 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 868 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 869 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 870 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 871 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 872 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 873 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 874 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 875 CPU_AVX_FLAGS, 0 },
6c30d220 876 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 877 CPU_AVX2_FLAGS, 0 },
43234a1e 878 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 879 CPU_AVX512F_FLAGS, 0 },
43234a1e 880 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 881 CPU_AVX512CD_FLAGS, 0 },
43234a1e 882 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 883 CPU_AVX512ER_FLAGS, 0 },
43234a1e 884 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 885 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 886 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 887 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 888 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 889 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 890 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 891 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 892 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 893 CPU_VMX_FLAGS, 0 },
8729a6f6 894 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 895 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 896 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 897 CPU_SMX_FLAGS, 0 },
8a2c8fef 898 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 899 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 900 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 901 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 902 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 903 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 904 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 905 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 906 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 907 CPU_AES_FLAGS, 0 },
8a2c8fef 908 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 909 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 910 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 911 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 912 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 913 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 914 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 915 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 916 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 917 CPU_F16C_FLAGS, 0 },
6c30d220 918 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 919 CPU_BMI2_FLAGS, 0 },
8a2c8fef 920 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 921 CPU_FMA_FLAGS, 0 },
8a2c8fef 922 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 923 CPU_FMA4_FLAGS, 0 },
8a2c8fef 924 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 925 CPU_XOP_FLAGS, 0 },
8a2c8fef 926 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 927 CPU_LWP_FLAGS, 0 },
8a2c8fef 928 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 929 CPU_MOVBE_FLAGS, 0 },
60aa667e 930 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 931 CPU_CX16_FLAGS, 0 },
8a2c8fef 932 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 933 CPU_EPT_FLAGS, 0 },
6c30d220 934 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 935 CPU_LZCNT_FLAGS, 0 },
42164a71 936 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 937 CPU_HLE_FLAGS, 0 },
42164a71 938 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 939 CPU_RTM_FLAGS, 0 },
6c30d220 940 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 941 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 942 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 943 CPU_CLFLUSH_FLAGS, 0 },
22109423 944 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 945 CPU_NOP_FLAGS, 0 },
8a2c8fef 946 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 947 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 948 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 949 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 950 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 951 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 952 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 953 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 954 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 955 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 956 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 957 CPU_SVME_FLAGS, 1 },
8a2c8fef 958 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 959 CPU_SVME_FLAGS, 0 },
8a2c8fef 960 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 961 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 962 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 963 CPU_ABM_FLAGS, 0 },
87973e9f 964 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 965 CPU_BMI_FLAGS, 0 },
2a2a0f38 966 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 967 CPU_TBM_FLAGS, 0 },
e2e1fcde 968 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 969 CPU_ADX_FLAGS, 0 },
e2e1fcde 970 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 971 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 972 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 973 CPU_PRFCHW_FLAGS, 0 },
5c111e37 974 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 975 CPU_SMAP_FLAGS, 0 },
7e8b059b 976 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 977 CPU_MPX_FLAGS, 0 },
a0046408 978 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 979 CPU_SHA_FLAGS, 0 },
963f3586 980 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 981 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 982 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 983 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 984 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 985 CPU_SE1_FLAGS, 0 },
c5e7287a 986 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 987 CPU_CLWB_FLAGS, 0 },
2cc1b5aa 988 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 989 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 990 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 991 CPU_AVX512VBMI_FLAGS, 0 },
920d2ddc
IT		 992 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
993 CPU_AVX512_4FMAPS_FLAGS, 0 },
47acf0bd
IT		 994 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
995 CPU_AVX512_4VNNIW_FLAGS, 0 },
620214f7
IT		 996 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
997 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
53467f57
IT		 998 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
999 CPU_AVX512_VBMI2_FLAGS, 0 },
8cfcb765
IT		 1000 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1001 CPU_AVX512_VNNI_FLAGS, 0 },
ee6872be
IT		 1002 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1003 CPU_AVX512_BITALG_FLAGS, 0 },
029f3522 1004 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 1005 CPU_CLZERO_FLAGS, 0 },
9916071f 1006 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 1007 CPU_MWAITX_FLAGS, 0 },
8eab4136 1008 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 1009 CPU_OSPKE_FLAGS, 0 },
8bc52696 1010 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65 1011 CPU_RDPID_FLAGS, 0 },
6b40c462
L		 1012 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1013 CPU_PTWRITE_FLAGS, 0 },
d777820b
IT		 1014 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1015 CPU_IBT_FLAGS, 0 },
1016 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1017 CPU_SHSTK_FLAGS, 0 },
48521003
IT		 1018 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1019 CPU_GFNI_FLAGS, 0 },
8dcf1fad
IT		 1020 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1021 CPU_VAES_FLAGS, 0 },
ff1982d5
IT		 1022 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1023 CPU_VPCLMULQDQ_FLAGS, 0 },
3233d7d0
IT		 1024 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1025 CPU_WBNOINVD_FLAGS, 0 },
be3a8dca
IT		 1026 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1027 CPU_PCONFIG_FLAGS, 0 },
de89d0a3
IT		 1028 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN,
1029 CPU_WAITPKG_FLAGS, 0 },
c48935d7
IT		 1030 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN,
1031 CPU_CLDEMOTE_FLAGS, 0 },
293f5f65
L		 1032};
1033
1034static const noarch_entry cpu_noarch[] =
1035{
1036 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1848e567
L		 1037 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1038 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1039 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
293f5f65
L		 1040 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1041 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1848e567
L		 1042 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1043 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1044 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1045 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1046 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1047 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
293f5f65 1048 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1848e567 1049 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
144b71e2
L		 1050 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1051 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1052 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1053 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1054 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1055 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1056 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1057 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
920d2ddc 1059 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
47acf0bd 1060 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
620214f7 1061 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
53467f57 1062 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
8cfcb765 1063 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
ee6872be 1064 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
d777820b
IT		 1065 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1066 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
e413e4e9
AM		 1067};
1068
704209c0 1069#ifdef I386COFF
a6c24e68
NC		 1070/* Like s_lcomm_internal in gas/read.c but the alignment string
1071 is allowed to be optional. */
1072
1073static symbolS *
1074pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1075{
1076 addressT align = 0;
1077
1078 SKIP_WHITESPACE ();
1079
7ab9ffdd 1080 if (needs_align
a6c24e68
NC		 1081 && *input_line_pointer == ',')
1082 {
1083 align = parse_align (needs_align - 1);
7ab9ffdd 1084
a6c24e68
NC		 1085 if (align == (addressT) -1)
1086 return NULL;
1087 }
1088 else
1089 {
1090 if (size >= 8)
1091 align = 3;
1092 else if (size >= 4)
1093 align = 2;
1094 else if (size >= 2)
1095 align = 1;
1096 else
1097 align = 0;
1098 }
1099
1100 bss_alloc (symbolP, size, align);
1101 return symbolP;
1102}
1103
704209c0 1104static void
a6c24e68
NC		 1105pe_lcomm (int needs_align)
1106{
1107 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1108}
704209c0 1109#endif
a6c24e68 1110
29b0f896
AM		 1111const pseudo_typeS md_pseudo_table[] =
1112{
1113#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1114 {"align", s_align_bytes, 0},
1115#else
1116 {"align", s_align_ptwo, 0},
1117#endif
1118 {"arch", set_cpu_arch, 0},
1119#ifndef I386COFF
1120 {"bss", s_bss, 0},
a6c24e68
NC		 1121#else
1122 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1123#endif
1124 {"ffloat", float_cons, 'f'},
1125 {"dfloat", float_cons, 'd'},
1126 {"tfloat", float_cons, 'x'},
1127 {"value", cons, 2},
d182319b 1128 {"slong", signed_cons, 4},
29b0f896
AM		 1129 {"noopt", s_ignore, 0},
1130 {"optim", s_ignore, 0},
1131 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1132 {"code16", set_code_flag, CODE_16BIT},
1133 {"code32", set_code_flag, CODE_32BIT},
da5f19a2 1134#ifdef BFD64
29b0f896 1135 {"code64", set_code_flag, CODE_64BIT},
da5f19a2 1136#endif
29b0f896
AM		 1137 {"intel_syntax", set_intel_syntax, 1},
1138 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1139 {"intel_mnemonic", set_intel_mnemonic, 1},
1140 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1141 {"allow_index_reg", set_allow_index_reg, 1},
1142 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1143 {"sse_check", set_check, 0},
1144 {"operand_check", set_check, 1},
3b22753a
L		 1145#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1146 {"largecomm", handle_large_common, 0},
07a53e5c 1147#else
68d20676 1148 {"file", dwarf2_directive_file, 0},
07a53e5c
RH		 1149 {"loc", dwarf2_directive_loc, 0},
1150 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1151#endif
6482c264
NC		 1152#ifdef TE_PE
1153 {"secrel32", pe_directive_secrel, 0},
1154#endif
29b0f896
AM		 1155 {0, 0, 0}
1156};
1157
1158/* For interface with expression (). */
1159extern char *input_line_pointer;
1160
1161/* Hash table for instruction mnemonic lookup. */
1162static struct hash_control *op_hash;
1163
1164/* Hash table for register lookup. */
1165static struct hash_control *reg_hash;
1166\f
ce8a8b2f
AM		 1167 /* Various efficient no-op patterns for aligning code labels.
1168 Note: Don't try to assemble the instructions in the comments.
1169 0L and 0w are not legal. */
62a02d25
L		 1170static const unsigned char f32_1[] =
1171 {0x90}; /* nop */
1172static const unsigned char f32_2[] =
1173 {0x66,0x90}; /* xchg %ax,%ax */
1174static const unsigned char f32_3[] =
1175 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1176static const unsigned char f32_4[] =
1177 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
62a02d25
L		 1178static const unsigned char f32_6[] =
1179 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1180static const unsigned char f32_7[] =
1181 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
62a02d25 1182static const unsigned char f16_3[] =
3ae729d5 1183 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
62a02d25 1184static const unsigned char f16_4[] =
3ae729d5
L		 1185 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1186static const unsigned char jump_disp8[] =
1187 {0xeb}; /* jmp disp8 */
1188static const unsigned char jump32_disp32[] =
1189 {0xe9}; /* jmp disp32 */
1190static const unsigned char jump16_disp32[] =
1191 {0x66,0xe9}; /* jmp disp32 */
62a02d25
L		 1192/* 32-bit NOPs patterns. */
1193static const unsigned char *const f32_patt[] = {
3ae729d5 1194 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
62a02d25
L		 1195};
1196/* 16-bit NOPs patterns. */
1197static const unsigned char *const f16_patt[] = {
3ae729d5 1198 f32_1, f32_2, f16_3, f16_4
62a02d25
L		 1199};
1200/* nopl (%[re]ax) */
1201static const unsigned char alt_3[] =
1202 {0x0f,0x1f,0x00};
1203/* nopl 0(%[re]ax) */
1204static const unsigned char alt_4[] =
1205 {0x0f,0x1f,0x40,0x00};
1206/* nopl 0(%[re]ax,%[re]ax,1) */
1207static const unsigned char alt_5[] =
1208 {0x0f,0x1f,0x44,0x00,0x00};
1209/* nopw 0(%[re]ax,%[re]ax,1) */
1210static const unsigned char alt_6[] =
1211 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1212/* nopl 0L(%[re]ax) */
1213static const unsigned char alt_7[] =
1214 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1215/* nopl 0L(%[re]ax,%[re]ax,1) */
1216static const unsigned char alt_8[] =
1217 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1218/* nopw 0L(%[re]ax,%[re]ax,1) */
1219static const unsigned char alt_9[] =
1220 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1221/* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1222static const unsigned char alt_10[] =
1223 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
3ae729d5
L		 1224/* data16 nopw %cs:0L(%eax,%eax,1) */
1225static const unsigned char alt_11[] =
1226 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
62a02d25
L		 1227/* 32-bit and 64-bit NOPs patterns. */
1228static const unsigned char *const alt_patt[] = {
1229 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
3ae729d5 1230 alt_9, alt_10, alt_11
62a02d25
L		 1231};
1232
1233/* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1234 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1235
1236static void
1237i386_output_nops (char *where, const unsigned char *const *patt,
1238 int count, int max_single_nop_size)
1239
1240{
3ae729d5
L		 1241 /* Place the longer NOP first. */
1242 int last;
1243 int offset;
1244 const unsigned char *nops = patt[max_single_nop_size - 1];
1245
1246 /* Use the smaller one if the requsted one isn't available. */
1247 if (nops == NULL)
62a02d25 1248 {
3ae729d5
L		 1249 max_single_nop_size--;
1250 nops = patt[max_single_nop_size - 1];
62a02d25
L		 1251 }
1252
3ae729d5
L		 1253 last = count % max_single_nop_size;
1254
1255 count -= last;
1256 for (offset = 0; offset < count; offset += max_single_nop_size)
1257 memcpy (where + offset, nops, max_single_nop_size);
1258
1259 if (last)
1260 {
1261 nops = patt[last - 1];
1262 if (nops == NULL)
1263 {
1264 /* Use the smaller one plus one-byte NOP if the needed one
1265 isn't available. */
1266 last--;
1267 nops = patt[last - 1];
1268 memcpy (where + offset, nops, last);
1269 where[offset + last] = *patt[0];
1270 }
1271 else
1272 memcpy (where + offset, nops, last);
1273 }
62a02d25
L		 1274}
1275
3ae729d5
L		 1276static INLINE int
1277fits_in_imm7 (offsetT num)
1278{
1279 return (num & 0x7f) == num;
1280}
1281
1282static INLINE int
1283fits_in_imm31 (offsetT num)
1284{
1285 return (num & 0x7fffffff) == num;
1286}
62a02d25
L		 1287
1288/* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1289 single NOP instruction LIMIT. */
1290
1291void
3ae729d5 1292i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
62a02d25 1293{
3ae729d5 1294 const unsigned char *const *patt = NULL;
62a02d25 1295 int max_single_nop_size;
3ae729d5
L		 1296 /* Maximum number of NOPs before switching to jump over NOPs. */
1297 int max_number_of_nops;
62a02d25 1298
3ae729d5 1299 switch (fragP->fr_type)
62a02d25 1300 {
3ae729d5
L		 1301 case rs_fill_nop:
1302 case rs_align_code:
1303 break;
1304 default:
62a02d25
L		 1305 return;
1306 }
1307
ccc9c027
L		 1308 /* We need to decide which NOP sequence to use for 32bit and
1309 64bit. When -mtune= is used:
4eed87de 1310
76bc74dc
L		 1311 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1312 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1313 2. For the rest, alt_patt will be used.
1314
1315 When -mtune= isn't used, alt_patt will be used if
22109423 1316 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1317 be used.
ccc9c027
L		 1318
1319 When -march= or .arch is used, we can't use anything beyond
1320 cpu_arch_isa_flags. */
1321
1322 if (flag_code == CODE_16BIT)
1323 {
3ae729d5
L		 1324 patt = f16_patt;
1325 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1326 /* Limit number of NOPs to 2 in 16-bit mode. */
1327 max_number_of_nops = 2;
252b5132 1328 }
33fef721 1329 else
ccc9c027 1330 {
fbf3f584 1331 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1332 {
1333 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1334 switch (cpu_arch_tune)
1335 {
1336 case PROCESSOR_UNKNOWN:
1337 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1338 optimize with nops. */
1339 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1340 patt = alt_patt;
ccc9c027
L		 1341 else
1342 patt = f32_patt;
1343 break;
ccc9c027
L		 1344 case PROCESSOR_PENTIUM4:
1345 case PROCESSOR_NOCONA:
ef05d495 1346 case PROCESSOR_CORE:
76bc74dc 1347 case PROCESSOR_CORE2:
bd5295b2 1348 case PROCESSOR_COREI7:
3632d14b 1349 case PROCESSOR_L1OM:
7a9068fe 1350 case PROCESSOR_K1OM:
76bc74dc 1351 case PROCESSOR_GENERIC64:
ccc9c027
L		 1352 case PROCESSOR_K6:
1353 case PROCESSOR_ATHLON:
1354 case PROCESSOR_K8:
4eed87de 1355 case PROCESSOR_AMDFAM10:
8aedb9fe 1356 case PROCESSOR_BD:
029f3522 1357 case PROCESSOR_ZNVER:
7b458c12 1358 case PROCESSOR_BT:
80b8656c 1359 patt = alt_patt;
ccc9c027 1360 break;
76bc74dc 1361 case PROCESSOR_I386:
ccc9c027
L		 1362 case PROCESSOR_I486:
1363 case PROCESSOR_PENTIUM:
2dde1948 1364 case PROCESSOR_PENTIUMPRO:
81486035 1365 case PROCESSOR_IAMCU:
ccc9c027
L		 1366 case PROCESSOR_GENERIC32:
1367 patt = f32_patt;
1368 break;
4eed87de 1369 }
ccc9c027
L		 1370 }
1371 else
1372 {
fbf3f584 1373 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1374 {
1375 case PROCESSOR_UNKNOWN:
e6a14101 1376 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1377 PROCESSOR_UNKNOWN. */
1378 abort ();
1379 break;
1380
76bc74dc 1381 case PROCESSOR_I386:
ccc9c027
L		 1382 case PROCESSOR_I486:
1383 case PROCESSOR_PENTIUM:
81486035 1384 case PROCESSOR_IAMCU:
ccc9c027
L		 1385 case PROCESSOR_K6:
1386 case PROCESSOR_ATHLON:
1387 case PROCESSOR_K8:
4eed87de 1388 case PROCESSOR_AMDFAM10:
8aedb9fe 1389 case PROCESSOR_BD:
029f3522 1390 case PROCESSOR_ZNVER:
7b458c12 1391 case PROCESSOR_BT:
ccc9c027
L		 1392 case PROCESSOR_GENERIC32:
1393 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1394 with nops. */
1395 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1396 patt = alt_patt;
ccc9c027
L		 1397 else
1398 patt = f32_patt;
1399 break;
76bc74dc
L		 1400 case PROCESSOR_PENTIUMPRO:
1401 case PROCESSOR_PENTIUM4:
1402 case PROCESSOR_NOCONA:
1403 case PROCESSOR_CORE:
ef05d495 1404 case PROCESSOR_CORE2:
bd5295b2 1405 case PROCESSOR_COREI7:
3632d14b 1406 case PROCESSOR_L1OM:
7a9068fe 1407 case PROCESSOR_K1OM:
22109423 1408 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1409 patt = alt_patt;
ccc9c027
L		 1410 else
1411 patt = f32_patt;
1412 break;
1413 case PROCESSOR_GENERIC64:
80b8656c 1414 patt = alt_patt;
ccc9c027 1415 break;
4eed87de 1416 }
ccc9c027
L		 1417 }
1418
76bc74dc
L		 1419 if (patt == f32_patt)
1420 {
3ae729d5
L		 1421 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1422 /* Limit number of NOPs to 2 for older processors. */
1423 max_number_of_nops = 2;
76bc74dc
L		 1424 }
1425 else
1426 {
3ae729d5
L		 1427 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1428 /* Limit number of NOPs to 7 for newer processors. */
1429 max_number_of_nops = 7;
1430 }
1431 }
1432
1433 if (limit == 0)
1434 limit = max_single_nop_size;
1435
1436 if (fragP->fr_type == rs_fill_nop)
1437 {
1438 /* Output NOPs for .nop directive. */
1439 if (limit > max_single_nop_size)
1440 {
1441 as_bad_where (fragP->fr_file, fragP->fr_line,
1442 _("invalid single nop size: %d "
1443 "(expect within [0, %d])"),
1444 limit, max_single_nop_size);
1445 return;
1446 }
1447 }
1448 else
1449 fragP->fr_var = count;
1450
1451 if ((count / max_single_nop_size) > max_number_of_nops)
1452 {
1453 /* Generate jump over NOPs. */
1454 offsetT disp = count - 2;
1455 if (fits_in_imm7 (disp))
1456 {
1457 /* Use "jmp disp8" if possible. */
1458 count = disp;
1459 where[0] = jump_disp8[0];
1460 where[1] = count;
1461 where += 2;
1462 }
1463 else
1464 {
1465 unsigned int size_of_jump;
1466
1467 if (flag_code == CODE_16BIT)
1468 {
1469 where[0] = jump16_disp32[0];
1470 where[1] = jump16_disp32[1];
1471 size_of_jump = 2;
1472 }
1473 else
1474 {
1475 where[0] = jump32_disp32[0];
1476 size_of_jump = 1;
1477 }
1478
1479 count -= size_of_jump + 4;
1480 if (!fits_in_imm31 (count))
1481 {
1482 as_bad_where (fragP->fr_file, fragP->fr_line,
1483 _("jump over nop padding out of range"));
1484 return;
1485 }
1486
1487 md_number_to_chars (where + size_of_jump, count, 4);
1488 where += size_of_jump + 4;
76bc74dc 1489 }
ccc9c027 1490 }
3ae729d5
L		 1491
1492 /* Generate multiple NOPs. */
1493 i386_output_nops (where, patt, count, limit);
252b5132
RH		 1494}
1495
c6fb90c8 1496static INLINE int
0dfbf9d7 1497operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1498{
0dfbf9d7 1499 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1500 {
1501 case 3:
0dfbf9d7 1502 if (x->array[2])
c6fb90c8 1503 return 0;
1a0670f3 1504 /* Fall through. */
c6fb90c8 1505 case 2:
0dfbf9d7 1506 if (x->array[1])
c6fb90c8 1507 return 0;
1a0670f3 1508 /* Fall through. */
c6fb90c8 1509 case 1:
0dfbf9d7 1510 return !x->array[0];
c6fb90c8
L		 1511 default:
1512 abort ();
1513 }
40fb9820
L		 1514}
1515
c6fb90c8 1516static INLINE void
0dfbf9d7 1517operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1518{
0dfbf9d7 1519 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1520 {
1521 case 3:
0dfbf9d7 1522 x->array[2] = v;
1a0670f3 1523 /* Fall through. */
c6fb90c8 1524 case 2:
0dfbf9d7 1525 x->array[1] = v;
1a0670f3 1526 /* Fall through. */
c6fb90c8 1527 case 1:
0dfbf9d7 1528 x->array[0] = v;
1a0670f3 1529 /* Fall through. */
c6fb90c8
L		 1530 break;
1531 default:
1532 abort ();
1533 }
1534}
40fb9820 1535
c6fb90c8 1536static INLINE int
0dfbf9d7
L		 1537operand_type_equal (const union i386_operand_type *x,
1538 const union i386_operand_type *y)
c6fb90c8 1539{
0dfbf9d7 1540 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1541 {
1542 case 3:
0dfbf9d7 1543 if (x->array[2] != y->array[2])
c6fb90c8 1544 return 0;
1a0670f3 1545 /* Fall through. */
c6fb90c8 1546 case 2:
0dfbf9d7 1547 if (x->array[1] != y->array[1])
c6fb90c8 1548 return 0;
1a0670f3 1549 /* Fall through. */
c6fb90c8 1550 case 1:
0dfbf9d7 1551 return x->array[0] == y->array[0];
c6fb90c8
L		 1552 break;
1553 default:
1554 abort ();
1555 }
1556}
40fb9820 1557
0dfbf9d7
L		 1558static INLINE int
1559cpu_flags_all_zero (const union i386_cpu_flags *x)
1560{
1561 switch (ARRAY_SIZE(x->array))
1562 {
53467f57
IT		 1563 case 4:
1564 if (x->array[3])
1565 return 0;
1566 /* Fall through. */
0dfbf9d7
L		 1567 case 3:
1568 if (x->array[2])
1569 return 0;
1a0670f3 1570 /* Fall through. */
0dfbf9d7
L		 1571 case 2:
1572 if (x->array[1])
1573 return 0;
1a0670f3 1574 /* Fall through. */
0dfbf9d7
L		 1575 case 1:
1576 return !x->array[0];
1577 default:
1578 abort ();
1579 }
1580}
1581
0dfbf9d7
L		 1582static INLINE int
1583cpu_flags_equal (const union i386_cpu_flags *x,
1584 const union i386_cpu_flags *y)
1585{
1586 switch (ARRAY_SIZE(x->array))
1587 {
53467f57
IT		 1588 case 4:
1589 if (x->array[3] != y->array[3])
1590 return 0;
1591 /* Fall through. */
0dfbf9d7
L		 1592 case 3:
1593 if (x->array[2] != y->array[2])
1594 return 0;
1a0670f3 1595 /* Fall through. */
0dfbf9d7
L		 1596 case 2:
1597 if (x->array[1] != y->array[1])
1598 return 0;
1a0670f3 1599 /* Fall through. */
0dfbf9d7
L		 1600 case 1:
1601 return x->array[0] == y->array[0];
1602 break;
1603 default:
1604 abort ();
1605 }
1606}
c6fb90c8
L		 1607
1608static INLINE int
1609cpu_flags_check_cpu64 (i386_cpu_flags f)
1610{
1611 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1612 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1613}
1614
c6fb90c8
L		 1615static INLINE i386_cpu_flags
1616cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1617{
c6fb90c8
L		 1618 switch (ARRAY_SIZE (x.array))
1619 {
53467f57
IT		 1620 case 4:
1621 x.array [3] &= y.array [3];
1622 /* Fall through. */
c6fb90c8
L		 1623 case 3:
1624 x.array [2] &= y.array [2];
1a0670f3 1625 /* Fall through. */
c6fb90c8
L		 1626 case 2:
1627 x.array [1] &= y.array [1];
1a0670f3 1628 /* Fall through. */
c6fb90c8
L		 1629 case 1:
1630 x.array [0] &= y.array [0];
1631 break;
1632 default:
1633 abort ();
1634 }
1635 return x;
1636}
40fb9820 1637
c6fb90c8
L		 1638static INLINE i386_cpu_flags
1639cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1640{
c6fb90c8 1641 switch (ARRAY_SIZE (x.array))
40fb9820 1642 {
53467f57
IT		 1643 case 4:
1644 x.array [3] |= y.array [3];
1645 /* Fall through. */
c6fb90c8
L		 1646 case 3:
1647 x.array [2] |= y.array [2];
1a0670f3 1648 /* Fall through. */
c6fb90c8
L		 1649 case 2:
1650 x.array [1] |= y.array [1];
1a0670f3 1651 /* Fall through. */
c6fb90c8
L		 1652 case 1:
1653 x.array [0] |= y.array [0];
40fb9820
L		 1654 break;
1655 default:
1656 abort ();
1657 }
40fb9820
L		 1658 return x;
1659}
1660
309d3373
JB		 1661static INLINE i386_cpu_flags
1662cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1663{
1664 switch (ARRAY_SIZE (x.array))
1665 {
53467f57
IT		 1666 case 4:
1667 x.array [3] &= ~y.array [3];
1668 /* Fall through. */
309d3373
JB		 1669 case 3:
1670 x.array [2] &= ~y.array [2];
1a0670f3 1671 /* Fall through. */
309d3373
JB		 1672 case 2:
1673 x.array [1] &= ~y.array [1];
1a0670f3 1674 /* Fall through. */
309d3373
JB		 1675 case 1:
1676 x.array [0] &= ~y.array [0];
1677 break;
1678 default:
1679 abort ();
1680 }
1681 return x;
1682}
1683
c0f3af97
L		 1684#define CPU_FLAGS_ARCH_MATCH 0x1
1685#define CPU_FLAGS_64BIT_MATCH 0x2
1686
c0f3af97 1687#define CPU_FLAGS_PERFECT_MATCH \
db12e14e 1688 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
c0f3af97
L		 1689
1690/* Return CPU flags match bits. */
3629bb00 1691
40fb9820 1692static int
d3ce72d0 1693cpu_flags_match (const insn_template *t)
40fb9820 1694{
c0f3af97
L		 1695 i386_cpu_flags x = t->cpu_flags;
1696 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1697
1698 x.bitfield.cpu64 = 0;
1699 x.bitfield.cpuno64 = 0;
1700
0dfbf9d7 1701 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1702 {
1703 /* This instruction is available on all archs. */
db12e14e 1704 match |= CPU_FLAGS_ARCH_MATCH;
c0f3af97 1705 }
3629bb00
L		 1706 else
1707 {
c0f3af97 1708 /* This instruction is available only on some archs. */
3629bb00
L		 1709 i386_cpu_flags cpu = cpu_arch_flags;
1710
ab592e75
JB		 1711 /* AVX512VL is no standalone feature - match it and then strip it. */
1712 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1713 return match;
1714 x.bitfield.cpuavx512vl = 0;
1715
3629bb00 1716 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1717 if (!cpu_flags_all_zero (&cpu))
1718 {
a5ff0eb2
L		 1719 if (x.bitfield.cpuavx)
1720 {
929f69fa 1721 /* We need to check a few extra flags with AVX. */
b9d49817
JB		 1722 if (cpu.bitfield.cpuavx
1723 && (!t->opcode_modifier.sse2avx || sse2avx)
1724 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
929f69fa 1725 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
b9d49817
JB		 1726 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1727 match |= CPU_FLAGS_ARCH_MATCH;
a5ff0eb2 1728 }
929f69fa
JB		 1729 else if (x.bitfield.cpuavx512f)
1730 {
1731 /* We need to check a few extra flags with AVX512F. */
1732 if (cpu.bitfield.cpuavx512f
1733 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1734 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1735 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1736 match |= CPU_FLAGS_ARCH_MATCH;
1737 }
a5ff0eb2 1738 else
db12e14e 1739 match |= CPU_FLAGS_ARCH_MATCH;
c0f3af97 1740 }
3629bb00 1741 }
c0f3af97 1742 return match;
40fb9820
L		 1743}
1744
c6fb90c8
L		 1745static INLINE i386_operand_type
1746operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1747{
c6fb90c8
L		 1748 switch (ARRAY_SIZE (x.array))
1749 {
1750 case 3:
1751 x.array [2] &= y.array [2];
1a0670f3 1752 /* Fall through. */
c6fb90c8
L		 1753 case 2:
1754 x.array [1] &= y.array [1];
1a0670f3 1755 /* Fall through. */
c6fb90c8
L		 1756 case 1:
1757 x.array [0] &= y.array [0];
1758 break;
1759 default:
1760 abort ();
1761 }
1762 return x;
40fb9820
L		 1763}
1764
73053c1f
JB		 1765static INLINE i386_operand_type
1766operand_type_and_not (i386_operand_type x, i386_operand_type y)
1767{
1768 switch (ARRAY_SIZE (x.array))
1769 {
1770 case 3:
1771 x.array [2] &= ~y.array [2];
1772 /* Fall through. */
1773 case 2:
1774 x.array [1] &= ~y.array [1];
1775 /* Fall through. */
1776 case 1:
1777 x.array [0] &= ~y.array [0];
1778 break;
1779 default:
1780 abort ();
1781 }
1782 return x;
1783}
1784
c6fb90c8
L		 1785static INLINE i386_operand_type
1786operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1787{
c6fb90c8 1788 switch (ARRAY_SIZE (x.array))
40fb9820 1789 {
c6fb90c8
L		 1790 case 3:
1791 x.array [2] |= y.array [2];
1a0670f3 1792 /* Fall through. */
c6fb90c8
L		 1793 case 2:
1794 x.array [1] |= y.array [1];
1a0670f3 1795 /* Fall through. */
c6fb90c8
L		 1796 case 1:
1797 x.array [0] |= y.array [0];
40fb9820
L		 1798 break;
1799 default:
1800 abort ();
1801 }
c6fb90c8
L		 1802 return x;
1803}
40fb9820 1804
c6fb90c8
L		 1805static INLINE i386_operand_type
1806operand_type_xor (i386_operand_type x, i386_operand_type y)
1807{
1808 switch (ARRAY_SIZE (x.array))
1809 {
1810 case 3:
1811 x.array [2] ^= y.array [2];
1a0670f3 1812 /* Fall through. */
c6fb90c8
L		 1813 case 2:
1814 x.array [1] ^= y.array [1];
1a0670f3 1815 /* Fall through. */
c6fb90c8
L		 1816 case 1:
1817 x.array [0] ^= y.array [0];
1818 break;
1819 default:
1820 abort ();
1821 }
40fb9820
L		 1822 return x;
1823}
1824
1825static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1826static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1827static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1828static const i386_operand_type inoutportreg
1829 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1830static const i386_operand_type reg16_inoutportreg
1831 = OPERAND_TYPE_REG16_INOUTPORTREG;
1832static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1833static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1834static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1835static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1836static const i386_operand_type anydisp
1837 = OPERAND_TYPE_ANYDISP;
40fb9820 1838static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
43234a1e 1839static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1840static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1841static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1842static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1843static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1844static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1845static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1846static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1847static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1848static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1849static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1850
1851enum operand_type
1852{
1853 reg,
40fb9820
L		 1854 imm,
1855 disp,
1856 anymem
1857};
1858
c6fb90c8 1859static INLINE int
40fb9820
L		 1860operand_type_check (i386_operand_type t, enum operand_type c)
1861{
1862 switch (c)
1863 {
1864 case reg:
dc821c5f 1865 return t.bitfield.reg;
40fb9820 1866
40fb9820
L		 1867 case imm:
1868 return (t.bitfield.imm8
1869 || t.bitfield.imm8s
1870 || t.bitfield.imm16
1871 || t.bitfield.imm32
1872 || t.bitfield.imm32s
1873 || t.bitfield.imm64);
1874
1875 case disp:
1876 return (t.bitfield.disp8
1877 || t.bitfield.disp16
1878 || t.bitfield.disp32
1879 || t.bitfield.disp32s
1880 || t.bitfield.disp64);
1881
1882 case anymem:
1883 return (t.bitfield.disp8
1884 || t.bitfield.disp16
1885 || t.bitfield.disp32
1886 || t.bitfield.disp32s
1887 || t.bitfield.disp64
1888 || t.bitfield.baseindex);
1889
1890 default:
1891 abort ();
1892 }
2cfe26b6
AM		 1893
1894 return 0;
40fb9820
L		 1895}
1896
ca0d63fe 1897/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
5c07affc
L		 1898 operand J for instruction template T. */
1899
1900static INLINE int
d3ce72d0 1901match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1902{
1903 return !((i.types[j].bitfield.byte
1904 && !t->operand_types[j].bitfield.byte)
1905 || (i.types[j].bitfield.word
1906 && !t->operand_types[j].bitfield.word)
1907 || (i.types[j].bitfield.dword
1908 && !t->operand_types[j].bitfield.dword)
1909 || (i.types[j].bitfield.qword
ca0d63fe
JB		 1910 && !t->operand_types[j].bitfield.qword)
1911 || (i.types[j].bitfield.tbyte
1912 && !t->operand_types[j].bitfield.tbyte));
5c07affc
L		 1913}
1914
1b54b8d7
JB		 1915/* Return 1 if there is no conflict in SIMD register on
1916 operand J for instruction template T. */
1917
1918static INLINE int
1919match_simd_size (const insn_template *t, unsigned int j)
1920{
1921 return !((i.types[j].bitfield.xmmword
1922 && !t->operand_types[j].bitfield.xmmword)
1923 || (i.types[j].bitfield.ymmword
1924 && !t->operand_types[j].bitfield.ymmword)
1925 || (i.types[j].bitfield.zmmword
1926 && !t->operand_types[j].bitfield.zmmword));
1927}
1928
5c07affc
L		 1929/* Return 1 if there is no conflict in any size on operand J for
1930 instruction template T. */
1931
1932static INLINE int
d3ce72d0 1933match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1934{
1935 return (match_reg_size (t, j)
1936 && !((i.types[j].bitfield.unspecified
af508cb9 1937 && !i.broadcast
5c07affc
L		 1938 && !t->operand_types[j].bitfield.unspecified)
1939 || (i.types[j].bitfield.fword
1940 && !t->operand_types[j].bitfield.fword)
1b54b8d7
JB		 1941 /* For scalar opcode templates to allow register and memory
1942 operands at the same time, some special casing is needed
d6793fa1
JB		 1943 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1944 down-conversion vpmov*. */
1b54b8d7
JB		 1945 || ((t->operand_types[j].bitfield.regsimd
1946 && !t->opcode_modifier.broadcast
d6793fa1
JB		 1947 && (t->operand_types[j].bitfield.byte
1948 || t->operand_types[j].bitfield.word
1949 || t->operand_types[j].bitfield.dword
1b54b8d7
JB		 1950 || t->operand_types[j].bitfield.qword))
1951 ? (i.types[j].bitfield.xmmword
1952 || i.types[j].bitfield.ymmword
1953 || i.types[j].bitfield.zmmword)
1954 : !match_simd_size(t, j))));
5c07affc
L		 1955}
1956
1957/* Return 1 if there is no size conflict on any operands for
1958 instruction template T. */
1959
1960static INLINE int
d3ce72d0 1961operand_size_match (const insn_template *t)
5c07affc
L		 1962{
1963 unsigned int j;
1964 int match = 1;
1965
1966 /* Don't check jump instructions. */
1967 if (t->opcode_modifier.jump
1968 || t->opcode_modifier.jumpbyte
1969 || t->opcode_modifier.jumpdword
1970 || t->opcode_modifier.jumpintersegment)
1971 return match;
1972
1973 /* Check memory and accumulator operand size. */
1974 for (j = 0; j < i.operands; j++)
1975 {
1b54b8d7
JB		 1976 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1977 && t->operand_types[j].bitfield.anysize)
5c07affc
L		 1978 continue;
1979
1b54b8d7 1980 if (t->operand_types[j].bitfield.reg
dc821c5f 1981 && !match_reg_size (t, j))
5c07affc
L		 1982 {
1983 match = 0;
1984 break;
1985 }
1986
1b54b8d7
JB		 1987 if (t->operand_types[j].bitfield.regsimd
1988 && !match_simd_size (t, j))
1989 {
1990 match = 0;
1991 break;
1992 }
1993
1994 if (t->operand_types[j].bitfield.acc
1995 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
1996 {
1997 match = 0;
1998 break;
1999 }
2000
5c07affc
L		 2001 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
2002 {
2003 match = 0;
2004 break;
2005 }
2006 }
2007
891edac4 2008 if (match)
5c07affc 2009 return match;
38e314eb 2010 else if (!t->opcode_modifier.d)
891edac4
L		 2011 {
2012mismatch:
86e026a4 2013 i.error = operand_size_mismatch;
891edac4
L		 2014 return 0;
2015 }
5c07affc
L		 2016
2017 /* Check reverse. */
9c2799c2 2018 gas_assert (i.operands == 2);
5c07affc
L		 2019
2020 match = 1;
2021 for (j = 0; j < 2; j++)
2022 {
dc821c5f
JB		 2023 if ((t->operand_types[j].bitfield.reg
2024 || t->operand_types[j].bitfield.acc)
5c07affc 2025 && !match_reg_size (t, j ? 0 : 1))
891edac4 2026 goto mismatch;
5c07affc
L		 2027
2028 if (i.types[j].bitfield.mem
2029 && !match_mem_size (t, j ? 0 : 1))
891edac4 2030 goto mismatch;
5c07affc
L		 2031 }
2032
2033 return match;
2034}
2035
c6fb90c8 2036static INLINE int
40fb9820
L		 2037operand_type_match (i386_operand_type overlap,
2038 i386_operand_type given)
2039{
2040 i386_operand_type temp = overlap;
2041
2042 temp.bitfield.jumpabsolute = 0;
7d5e4556 2043 temp.bitfield.unspecified = 0;
5c07affc
L		 2044 temp.bitfield.byte = 0;
2045 temp.bitfield.word = 0;
2046 temp.bitfield.dword = 0;
2047 temp.bitfield.fword = 0;
2048 temp.bitfield.qword = 0;
2049 temp.bitfield.tbyte = 0;
2050 temp.bitfield.xmmword = 0;
c0f3af97 2051 temp.bitfield.ymmword = 0;
43234a1e 2052 temp.bitfield.zmmword = 0;
0dfbf9d7 2053 if (operand_type_all_zero (&temp))
891edac4 2054 goto mismatch;
40fb9820 2055
891edac4
L		 2056 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2057 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2058 return 1;
2059
2060mismatch:
a65babc9 2061 i.error = operand_type_mismatch;
891edac4 2062 return 0;
40fb9820
L		 2063}
2064
7d5e4556 2065/* If given types g0 and g1 are registers they must be of the same type
10c17abd
JB		 2066 unless the expected operand type register overlap is null.
2067 Memory operand size of certain SIMD instructions is also being checked
2068 here. */
40fb9820 2069
c6fb90c8 2070static INLINE int
dc821c5f 2071operand_type_register_match (i386_operand_type g0,
40fb9820 2072 i386_operand_type t0,
40fb9820
L		 2073 i386_operand_type g1,
2074 i386_operand_type t1)
2075{
10c17abd
JB		 2076 if (!g0.bitfield.reg
2077 && !g0.bitfield.regsimd
2078 && (!operand_type_check (g0, anymem)
2079 || g0.bitfield.unspecified
2080 || !t0.bitfield.regsimd))
40fb9820
L		 2081 return 1;
2082
10c17abd
JB		 2083 if (!g1.bitfield.reg
2084 && !g1.bitfield.regsimd
2085 && (!operand_type_check (g1, anymem)
2086 || g1.bitfield.unspecified
2087 || !t1.bitfield.regsimd))
40fb9820
L		 2088 return 1;
2089
dc821c5f
JB		 2090 if (g0.bitfield.byte == g1.bitfield.byte
2091 && g0.bitfield.word == g1.bitfield.word
2092 && g0.bitfield.dword == g1.bitfield.dword
10c17abd
JB		 2093 && g0.bitfield.qword == g1.bitfield.qword
2094 && g0.bitfield.xmmword == g1.bitfield.xmmword
2095 && g0.bitfield.ymmword == g1.bitfield.ymmword
2096 && g0.bitfield.zmmword == g1.bitfield.zmmword)
40fb9820
L		 2097 return 1;
2098
dc821c5f
JB		 2099 if (!(t0.bitfield.byte & t1.bitfield.byte)
2100 && !(t0.bitfield.word & t1.bitfield.word)
2101 && !(t0.bitfield.dword & t1.bitfield.dword)
10c17abd
JB		 2102 && !(t0.bitfield.qword & t1.bitfield.qword)
2103 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2104 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2105 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
891edac4
L		 2106 return 1;
2107
a65babc9 2108 i.error = register_type_mismatch;
891edac4
L		 2109
2110 return 0;
40fb9820
L		 2111}
2112
4c692bc7
JB		 2113static INLINE unsigned int
2114register_number (const reg_entry *r)
2115{
2116 unsigned int nr = r->reg_num;
2117
2118 if (r->reg_flags & RegRex)
2119 nr += 8;
2120
200cbe0f
L		 2121 if (r->reg_flags & RegVRex)
2122 nr += 16;
2123
4c692bc7
JB		 2124 return nr;
2125}
2126
252b5132 2127static INLINE unsigned int
40fb9820 2128mode_from_disp_size (i386_operand_type t)
252b5132 2129{
b5014f7a 2130 if (t.bitfield.disp8)
40fb9820
L		 2131 return 1;
2132 else if (t.bitfield.disp16
2133 || t.bitfield.disp32
2134 || t.bitfield.disp32s)
2135 return 2;
2136 else
2137 return 0;
252b5132
RH		 2138}
2139
2140static INLINE int
65879393 2141fits_in_signed_byte (addressT num)
252b5132 2142{
65879393 2143 return num + 0x80 <= 0xff;
47926f60 2144}
252b5132
RH		 2145
2146static INLINE int
65879393 2147fits_in_unsigned_byte (addressT num)
252b5132 2148{
65879393 2149 return num <= 0xff;
47926f60 2150}
252b5132
RH		 2151
2152static INLINE int
65879393 2153fits_in_unsigned_word (addressT num)
252b5132 2154{
65879393 2155 return num <= 0xffff;
47926f60 2156}
252b5132
RH		 2157
2158static INLINE int
65879393 2159fits_in_signed_word (addressT num)
252b5132 2160{
65879393 2161 return num + 0x8000 <= 0xffff;
47926f60 2162}
2a962e6d 2163
3e73aa7c 2164static INLINE int
65879393 2165fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2166{
2167#ifndef BFD64
2168 return 1;
2169#else
65879393 2170 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 2171#endif
2172} /* fits_in_signed_long() */
2a962e6d 2173
3e73aa7c 2174static INLINE int
65879393 2175fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2176{
2177#ifndef BFD64
2178 return 1;
2179#else
65879393 2180 return num <= 0xffffffff;
3e73aa7c
JH		 2181#endif
2182} /* fits_in_unsigned_long() */
252b5132 2183
43234a1e 2184static INLINE int
b5014f7a 2185fits_in_disp8 (offsetT num)
43234a1e
L		 2186{
2187 int shift = i.memshift;
2188 unsigned int mask;
2189
2190 if (shift == -1)
2191 abort ();
2192
2193 mask = (1 << shift) - 1;
2194
2195 /* Return 0 if NUM isn't properly aligned. */
2196 if ((num & mask))
2197 return 0;
2198
2199 /* Check if NUM will fit in 8bit after shift. */
2200 return fits_in_signed_byte (num >> shift);
2201}
2202
a683cc34
SP		 2203static INLINE int
2204fits_in_imm4 (offsetT num)
2205{
2206 return (num & 0xf) == num;
2207}
2208
40fb9820 2209static i386_operand_type
e3bb37b5 2210smallest_imm_type (offsetT num)
252b5132 2211{
40fb9820 2212 i386_operand_type t;
7ab9ffdd 2213
0dfbf9d7 2214 operand_type_set (&t, 0);
40fb9820
L		 2215 t.bitfield.imm64 = 1;
2216
2217 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2218 {
2219 /* This code is disabled on the 486 because all the Imm1 forms
2220 in the opcode table are slower on the i486. They're the
2221 versions with the implicitly specified single-position
2222 displacement, which has another syntax if you really want to
2223 use that form. */
40fb9820
L		 2224 t.bitfield.imm1 = 1;
2225 t.bitfield.imm8 = 1;
2226 t.bitfield.imm8s = 1;
2227 t.bitfield.imm16 = 1;
2228 t.bitfield.imm32 = 1;
2229 t.bitfield.imm32s = 1;
2230 }
2231 else if (fits_in_signed_byte (num))
2232 {
2233 t.bitfield.imm8 = 1;
2234 t.bitfield.imm8s = 1;
2235 t.bitfield.imm16 = 1;
2236 t.bitfield.imm32 = 1;
2237 t.bitfield.imm32s = 1;
2238 }
2239 else if (fits_in_unsigned_byte (num))
2240 {
2241 t.bitfield.imm8 = 1;
2242 t.bitfield.imm16 = 1;
2243 t.bitfield.imm32 = 1;
2244 t.bitfield.imm32s = 1;
2245 }
2246 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2247 {
2248 t.bitfield.imm16 = 1;
2249 t.bitfield.imm32 = 1;
2250 t.bitfield.imm32s = 1;
2251 }
2252 else if (fits_in_signed_long (num))
2253 {
2254 t.bitfield.imm32 = 1;
2255 t.bitfield.imm32s = 1;
2256 }
2257 else if (fits_in_unsigned_long (num))
2258 t.bitfield.imm32 = 1;
2259
2260 return t;
47926f60 2261}
252b5132 2262
847f7ad4 2263static offsetT
e3bb37b5 2264offset_in_range (offsetT val, int size)
847f7ad4 2265{
508866be 2266 addressT mask;
ba2adb93 2267
847f7ad4
AM		 2268 switch (size)
2269 {
508866be
L		 2270 case 1: mask = ((addressT) 1 << 8) - 1; break;
2271 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2272 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2273#ifdef BFD64
2274 case 8: mask = ((addressT) 2 << 63) - 1; break;
2275#endif
47926f60 2276 default: abort ();
847f7ad4
AM		 2277 }
2278
9de868bf
L		 2279#ifdef BFD64
2280 /* If BFD64, sign extend val for 32bit address mode. */
2281 if (flag_code != CODE_64BIT
2282 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2283 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2284 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2285#endif
ba2adb93 2286
47926f60 2287 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2288 {
2289 char buf1[40], buf2[40];
2290
2291 sprint_value (buf1, val);
2292 sprint_value (buf2, val & mask);
2293 as_warn (_("%s shortened to %s"), buf1, buf2);
2294 }
2295 return val & mask;
2296}
2297
c32fa91d
L		 2298enum PREFIX_GROUP
2299{
2300 PREFIX_EXIST = 0,
2301 PREFIX_LOCK,
2302 PREFIX_REP,
04ef582a 2303 PREFIX_DS,
c32fa91d
L		 2304 PREFIX_OTHER
2305};
2306
2307/* Returns
2308 a. PREFIX_EXIST if attempting to add a prefix where one from the
2309 same class already exists.
2310 b. PREFIX_LOCK if lock prefix is added.
2311 c. PREFIX_REP if rep/repne prefix is added.
04ef582a
L		 2312 d. PREFIX_DS if ds prefix is added.
2313 e. PREFIX_OTHER if other prefix is added.
c32fa91d
L		 2314 */
2315
2316static enum PREFIX_GROUP
e3bb37b5 2317add_prefix (unsigned int prefix)
252b5132 2318{
c32fa91d 2319 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2320 unsigned int q;
252b5132 2321
29b0f896
AM		 2322 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2323 && flag_code == CODE_64BIT)
b1905489 2324 {
161a04f6
L		 2325 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2326 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2327 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2328 ret = PREFIX_EXIST;
b1905489
JB		 2329 q = REX_PREFIX;
2330 }
3e73aa7c 2331 else
b1905489
JB		 2332 {
2333 switch (prefix)
2334 {
2335 default:
2336 abort ();
2337
b1905489 2338 case DS_PREFIX_OPCODE:
04ef582a
L		 2339 ret = PREFIX_DS;
2340 /* Fall through. */
2341 case CS_PREFIX_OPCODE:
b1905489
JB		 2342 case ES_PREFIX_OPCODE:
2343 case FS_PREFIX_OPCODE:
2344 case GS_PREFIX_OPCODE:
2345 case SS_PREFIX_OPCODE:
2346 q = SEG_PREFIX;
2347 break;
2348
2349 case REPNE_PREFIX_OPCODE:
2350 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2351 q = REP_PREFIX;
2352 ret = PREFIX_REP;
2353 break;
2354
b1905489 2355 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2356 q = LOCK_PREFIX;
2357 ret = PREFIX_LOCK;
b1905489
JB		 2358 break;
2359
2360 case FWAIT_OPCODE:
2361 q = WAIT_PREFIX;
2362 break;
2363
2364 case ADDR_PREFIX_OPCODE:
2365 q = ADDR_PREFIX;
2366 break;
2367
2368 case DATA_PREFIX_OPCODE:
2369 q = DATA_PREFIX;
2370 break;
2371 }
2372 if (i.prefix[q] != 0)
c32fa91d 2373 ret = PREFIX_EXIST;
b1905489 2374 }
252b5132 2375
b1905489 2376 if (ret)
252b5132 2377 {
b1905489
JB		 2378 if (!i.prefix[q])
2379 ++i.prefixes;
2380 i.prefix[q] |= prefix;
252b5132 2381 }
b1905489
JB		 2382 else
2383 as_bad (_("same type of prefix used twice"));
252b5132 2384
252b5132
RH		 2385 return ret;
2386}
2387
2388static void
78f12dd3 2389update_code_flag (int value, int check)
eecb386c 2390{
78f12dd3
L		 2391 PRINTF_LIKE ((*as_error));
2392
1e9cc1c2 2393 flag_code = (enum flag_code) value;
40fb9820
L		 2394 if (flag_code == CODE_64BIT)
2395 {
2396 cpu_arch_flags.bitfield.cpu64 = 1;
2397 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2398 }
2399 else
2400 {
2401 cpu_arch_flags.bitfield.cpu64 = 0;
2402 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2403 }
2404 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2405 {
78f12dd3
L		 2406 if (check)
2407 as_error = as_fatal;
2408 else
2409 as_error = as_bad;
2410 (*as_error) (_("64bit mode not supported on `%s'."),
2411 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2412 }
40fb9820 2413 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2414 {
78f12dd3
L		 2415 if (check)
2416 as_error = as_fatal;
2417 else
2418 as_error = as_bad;
2419 (*as_error) (_("32bit mode not supported on `%s'."),
2420 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2421 }
eecb386c
AM		 2422 stackop_size = '\0';
2423}
2424
78f12dd3
L		 2425static void
2426set_code_flag (int value)
2427{
2428 update_code_flag (value, 0);
2429}
2430
eecb386c 2431static void
e3bb37b5 2432set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2433{
1e9cc1c2 2434 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2435 if (flag_code != CODE_16BIT)
2436 abort ();
2437 cpu_arch_flags.bitfield.cpu64 = 0;
2438 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2439 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2440}
2441
2442static void
e3bb37b5 2443set_intel_syntax (int syntax_flag)
252b5132
RH		 2444{
2445 /* Find out if register prefixing is specified. */
2446 int ask_naked_reg = 0;
2447
2448 SKIP_WHITESPACE ();
29b0f896 2449 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2450 {
d02603dc
NC		 2451 char *string;
2452 int e = get_symbol_name (&string);
252b5132 2453
47926f60 2454 if (strcmp (string, "prefix") == 0)
252b5132 2455 ask_naked_reg = 1;
47926f60 2456 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2457 ask_naked_reg = -1;
2458 else
d0b47220 2459 as_bad (_("bad argument to syntax directive."));
d02603dc 2460 (void) restore_line_pointer (e);
252b5132
RH		 2461 }
2462 demand_empty_rest_of_line ();
c3332e24 2463
252b5132
RH		 2464 intel_syntax = syntax_flag;
2465
2466 if (ask_naked_reg == 0)
f86103b7
AM		 2467 allow_naked_reg = (intel_syntax
2468 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2469 else
2470 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2471
ee86248c 2472 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2473
e4a3b5a4 2474 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2475 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2476 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2477}
2478
1efbbeb4
L		 2479static void
2480set_intel_mnemonic (int mnemonic_flag)
2481{
e1d4d893 2482 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2483}
2484
db51cc60
L		 2485static void
2486set_allow_index_reg (int flag)
2487{
2488 allow_index_reg = flag;
2489}
2490
cb19c032 2491static void
7bab8ab5 2492set_check (int what)
cb19c032 2493{
7bab8ab5
JB		 2494 enum check_kind *kind;
2495 const char *str;
2496
2497 if (what)
2498 {
2499 kind = &operand_check;
2500 str = "operand";
2501 }
2502 else
2503 {
2504 kind = &sse_check;
2505 str = "sse";
2506 }
2507
cb19c032
L		 2508 SKIP_WHITESPACE ();
2509
2510 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2511 {
d02603dc
NC		 2512 char *string;
2513 int e = get_symbol_name (&string);
cb19c032
L		 2514
2515 if (strcmp (string, "none") == 0)
7bab8ab5 2516 *kind = check_none;
cb19c032 2517 else if (strcmp (string, "warning") == 0)
7bab8ab5 2518 *kind = check_warning;
cb19c032 2519 else if (strcmp (string, "error") == 0)
7bab8ab5 2520 *kind = check_error;
cb19c032 2521 else
7bab8ab5 2522 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2523 (void) restore_line_pointer (e);
cb19c032
L		 2524 }
2525 else
7bab8ab5 2526 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2527
2528 demand_empty_rest_of_line ();
2529}
2530
8a9036a4
L		 2531static void
2532check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2533 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2534{
2535#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2536 static const char *arch;
2537
2538 /* Intel LIOM is only supported on ELF. */
2539 if (!IS_ELF)
2540 return;
2541
2542 if (!arch)
2543 {
2544 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2545 use default_arch. */
2546 arch = cpu_arch_name;
2547 if (!arch)
2548 arch = default_arch;
2549 }
2550
81486035
L		 2551 /* If we are targeting Intel MCU, we must enable it. */
2552 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2553 || new_flag.bitfield.cpuiamcu)
2554 return;
2555
3632d14b 2556 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2557 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2558 || new_flag.bitfield.cpul1om)
8a9036a4 2559 return;
76ba9986 2560
7a9068fe
L		 2561 /* If we are targeting Intel K1OM, we must enable it. */
2562 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2563 || new_flag.bitfield.cpuk1om)
2564 return;
2565
8a9036a4
L		 2566 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2567#endif
2568}
2569
e413e4e9 2570static void
e3bb37b5 2571set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2572{
47926f60 2573 SKIP_WHITESPACE ();
e413e4e9 2574
29b0f896 2575 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2576 {
d02603dc
NC		 2577 char *string;
2578 int e = get_symbol_name (&string);
91d6fa6a 2579 unsigned int j;
40fb9820 2580 i386_cpu_flags flags;
e413e4e9 2581
91d6fa6a 2582 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2583 {
91d6fa6a 2584 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2585 {
91d6fa6a 2586 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2587
5c6af06e
JB		 2588 if (*string != '.')
2589 {
91d6fa6a 2590 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2591 cpu_sub_arch_name = NULL;
91d6fa6a 2592 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2593 if (flag_code == CODE_64BIT)
2594 {
2595 cpu_arch_flags.bitfield.cpu64 = 1;
2596 cpu_arch_flags.bitfield.cpuno64 = 0;
2597 }
2598 else
2599 {
2600 cpu_arch_flags.bitfield.cpu64 = 0;
2601 cpu_arch_flags.bitfield.cpuno64 = 1;
2602 }
91d6fa6a
NC		 2603 cpu_arch_isa = cpu_arch[j].type;
2604 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2605 if (!cpu_arch_tune_set)
2606 {
2607 cpu_arch_tune = cpu_arch_isa;
2608 cpu_arch_tune_flags = cpu_arch_isa_flags;
2609 }
5c6af06e
JB		 2610 break;
2611 }
40fb9820 2612
293f5f65
L		 2613 flags = cpu_flags_or (cpu_arch_flags,
2614 cpu_arch[j].flags);
81486035 2615
5b64d091 2616 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2617 {
6305a203
L		 2618 if (cpu_sub_arch_name)
2619 {
2620 char *name = cpu_sub_arch_name;
2621 cpu_sub_arch_name = concat (name,
91d6fa6a 2622 cpu_arch[j].name,
1bf57e9f 2623 (const char *) NULL);
6305a203
L		 2624 free (name);
2625 }
2626 else
91d6fa6a 2627 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2628 cpu_arch_flags = flags;
a586129e 2629 cpu_arch_isa_flags = flags;
5c6af06e 2630 }
0089dace
L		 2631 else
2632 cpu_arch_isa_flags
2633 = cpu_flags_or (cpu_arch_isa_flags,
2634 cpu_arch[j].flags);
d02603dc 2635 (void) restore_line_pointer (e);
5c6af06e
JB		 2636 demand_empty_rest_of_line ();
2637 return;
e413e4e9
AM		 2638 }
2639 }
293f5f65
L		 2640
2641 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2642 {
33eaf5de 2643 /* Disable an ISA extension. */
293f5f65
L		 2644 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2645 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2646 {
2647 flags = cpu_flags_and_not (cpu_arch_flags,
2648 cpu_noarch[j].flags);
2649 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2650 {
2651 if (cpu_sub_arch_name)
2652 {
2653 char *name = cpu_sub_arch_name;
2654 cpu_sub_arch_name = concat (name, string,
2655 (const char *) NULL);
2656 free (name);
2657 }
2658 else
2659 cpu_sub_arch_name = xstrdup (string);
2660 cpu_arch_flags = flags;
2661 cpu_arch_isa_flags = flags;
2662 }
2663 (void) restore_line_pointer (e);
2664 demand_empty_rest_of_line ();
2665 return;
2666 }
2667
2668 j = ARRAY_SIZE (cpu_arch);
2669 }
2670
91d6fa6a 2671 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2672 as_bad (_("no such architecture: `%s'"), string);
2673
2674 *input_line_pointer = e;
2675 }
2676 else
2677 as_bad (_("missing cpu architecture"));
2678
fddf5b5b
AM		 2679 no_cond_jump_promotion = 0;
2680 if (*input_line_pointer == ','
29b0f896 2681 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2682 {
d02603dc
NC		 2683 char *string;
2684 char e;
2685
2686 ++input_line_pointer;
2687 e = get_symbol_name (&string);
fddf5b5b
AM		 2688
2689 if (strcmp (string, "nojumps") == 0)
2690 no_cond_jump_promotion = 1;
2691 else if (strcmp (string, "jumps") == 0)
2692 ;
2693 else
2694 as_bad (_("no such architecture modifier: `%s'"), string);
2695
d02603dc 2696 (void) restore_line_pointer (e);
fddf5b5b
AM		 2697 }
2698
e413e4e9
AM		 2699 demand_empty_rest_of_line ();
2700}
2701
8a9036a4
L		 2702enum bfd_architecture
2703i386_arch (void)
2704{
3632d14b 2705 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2706 {
2707 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2708 || flag_code != CODE_64BIT)
2709 as_fatal (_("Intel L1OM is 64bit ELF only"));
2710 return bfd_arch_l1om;
2711 }
7a9068fe
L		 2712 else if (cpu_arch_isa == PROCESSOR_K1OM)
2713 {
2714 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2715 || flag_code != CODE_64BIT)
2716 as_fatal (_("Intel K1OM is 64bit ELF only"));
2717 return bfd_arch_k1om;
2718 }
81486035
L		 2719 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2720 {
2721 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2722 || flag_code == CODE_64BIT)
2723 as_fatal (_("Intel MCU is 32bit ELF only"));
2724 return bfd_arch_iamcu;
2725 }
8a9036a4
L		 2726 else
2727 return bfd_arch_i386;
2728}
2729
b9d79e03 2730unsigned long
7016a5d5 2731i386_mach (void)
b9d79e03 2732{
351f65ca 2733 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2734 {
3632d14b 2735 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2736 {
351f65ca
L		 2737 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2738 || default_arch[6] != '\0')
8a9036a4
L		 2739 as_fatal (_("Intel L1OM is 64bit ELF only"));
2740 return bfd_mach_l1om;
2741 }
7a9068fe
L		 2742 else if (cpu_arch_isa == PROCESSOR_K1OM)
2743 {
2744 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2745 || default_arch[6] != '\0')
2746 as_fatal (_("Intel K1OM is 64bit ELF only"));
2747 return bfd_mach_k1om;
2748 }
351f65ca 2749 else if (default_arch[6] == '\0')
8a9036a4 2750 return bfd_mach_x86_64;
351f65ca
L		 2751 else
2752 return bfd_mach_x64_32;
8a9036a4 2753 }
5197d474
L		 2754 else if (!strcmp (default_arch, "i386")
2755 || !strcmp (default_arch, "iamcu"))
81486035
L		 2756 {
2757 if (cpu_arch_isa == PROCESSOR_IAMCU)
2758 {
2759 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2760 as_fatal (_("Intel MCU is 32bit ELF only"));
2761 return bfd_mach_i386_iamcu;
2762 }
2763 else
2764 return bfd_mach_i386_i386;
2765 }
b9d79e03 2766 else
2b5d6a91 2767 as_fatal (_("unknown architecture"));
b9d79e03 2768}
b9d79e03 2769\f
252b5132 2770void
7016a5d5 2771md_begin (void)
252b5132
RH		 2772{
2773 const char *hash_err;
2774
86fa6981
L		 2775 /* Support pseudo prefixes like {disp32}. */
2776 lex_type ['{'] = LEX_BEGIN_NAME;
2777
47926f60 2778 /* Initialize op_hash hash table. */
252b5132
RH		 2779 op_hash = hash_new ();
2780
2781 {
d3ce72d0 2782 const insn_template *optab;
29b0f896 2783 templates *core_optab;
252b5132 2784
47926f60
KH		 2785 /* Setup for loop. */
2786 optab = i386_optab;
add39d23 2787 core_optab = XNEW (templates);
252b5132
RH		 2788 core_optab->start = optab;
2789
2790 while (1)
2791 {
2792 ++optab;
2793 if (optab->name == NULL
2794 || strcmp (optab->name, (optab - 1)->name) != 0)
2795 {
2796 /* different name --> ship out current template list;
47926f60 2797 add to hash table; & begin anew. */
252b5132
RH		 2798 core_optab->end = optab;
2799 hash_err = hash_insert (op_hash,
2800 (optab - 1)->name,
5a49b8ac 2801 (void *) core_optab);
252b5132
RH		 2802 if (hash_err)
2803 {
b37df7c4 2804 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2805 (optab - 1)->name,
2806 hash_err);
2807 }
2808 if (optab->name == NULL)
2809 break;
add39d23 2810 core_optab = XNEW (templates);
252b5132
RH		 2811 core_optab->start = optab;
2812 }
2813 }
2814 }
2815
47926f60 2816 /* Initialize reg_hash hash table. */
252b5132
RH		 2817 reg_hash = hash_new ();
2818 {
29b0f896 2819 const reg_entry *regtab;
c3fe08fa 2820 unsigned int regtab_size = i386_regtab_size;
252b5132 2821
c3fe08fa 2822 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2823 {
5a49b8ac 2824 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2825 if (hash_err)
b37df7c4 2826 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2827 regtab->reg_name,
2828 hash_err);
252b5132
RH		 2829 }
2830 }
2831
47926f60 2832 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2833 {
29b0f896
AM		 2834 int c;
2835 char *p;
252b5132
RH		 2836
2837 for (c = 0; c < 256; c++)
2838 {
3882b010 2839 if (ISDIGIT (c))
252b5132
RH		 2840 {
2841 digit_chars[c] = c;
2842 mnemonic_chars[c] = c;
2843 register_chars[c] = c;
2844 operand_chars[c] = c;
2845 }
3882b010 2846 else if (ISLOWER (c))
252b5132
RH		 2847 {
2848 mnemonic_chars[c] = c;
2849 register_chars[c] = c;
2850 operand_chars[c] = c;
2851 }
3882b010 2852 else if (ISUPPER (c))
252b5132 2853 {
3882b010 2854 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2855 register_chars[c] = mnemonic_chars[c];
2856 operand_chars[c] = c;
2857 }
43234a1e 2858 else if (c == '{' || c == '}')
86fa6981
L		 2859 {
2860 mnemonic_chars[c] = c;
2861 operand_chars[c] = c;
2862 }
252b5132 2863
3882b010 2864 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2865 identifier_chars[c] = c;
2866 else if (c >= 128)
2867 {
2868 identifier_chars[c] = c;
2869 operand_chars[c] = c;
2870 }
2871 }
2872
2873#ifdef LEX_AT
2874 identifier_chars['@'] = '@';
32137342
NC		 2875#endif
2876#ifdef LEX_QM
2877 identifier_chars['?'] = '?';
2878 operand_chars['?'] = '?';
252b5132 2879#endif
252b5132 2880 digit_chars['-'] = '-';
c0f3af97 2881 mnemonic_chars['_'] = '_';
791fe849 2882 mnemonic_chars['-'] = '-';
0003779b 2883 mnemonic_chars['.'] = '.';
252b5132
RH		 2884 identifier_chars['_'] = '_';
2885 identifier_chars['.'] = '.';
2886
2887 for (p = operand_special_chars; *p != '\0'; p++)
2888 operand_chars[(unsigned char) *p] = *p;
2889 }
2890
a4447b93
RH		 2891 if (flag_code == CODE_64BIT)
2892 {
ca19b261
KT		 2893#if defined (OBJ_COFF) && defined (TE_PE)
2894 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2895 ? 32 : 16);
2896#else
a4447b93 2897 x86_dwarf2_return_column = 16;
ca19b261 2898#endif
61ff971f 2899 x86_cie_data_alignment = -8;
a4447b93
RH		 2900 }
2901 else
2902 {
2903 x86_dwarf2_return_column = 8;
2904 x86_cie_data_alignment = -4;
2905 }
252b5132
RH		 2906}
2907
2908void
e3bb37b5 2909i386_print_statistics (FILE *file)
252b5132
RH		 2910{
2911 hash_print_statistics (file, "i386 opcode", op_hash);
2912 hash_print_statistics (file, "i386 register", reg_hash);
2913}
2914\f
252b5132
RH		 2915#ifdef DEBUG386
2916
ce8a8b2f 2917/* Debugging routines for md_assemble. */
d3ce72d0 2918static void pte (insn_template *);
40fb9820 2919static void pt (i386_operand_type);
e3bb37b5
L		 2920static void pe (expressionS *);
2921static void ps (symbolS *);
252b5132
RH		 2922
2923static void
e3bb37b5 2924pi (char *line, i386_insn *x)
252b5132 2925{
09137c09 2926 unsigned int j;
252b5132
RH		 2927
2928 fprintf (stdout, "%s: template ", line);
2929 pte (&x->tm);
09f131f2
JH		 2930 fprintf (stdout, " address: base %s index %s scale %x\n",
2931 x->base_reg ? x->base_reg->reg_name : "none",
2932 x->index_reg ? x->index_reg->reg_name : "none",
2933 x->log2_scale_factor);
2934 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2935 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2936 fprintf (stdout, " sib: base %x index %x scale %x\n",
2937 x->sib.base, x->sib.index, x->sib.scale);
2938 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2939 (x->rex & REX_W) != 0,
2940 (x->rex & REX_R) != 0,
2941 (x->rex & REX_X) != 0,
2942 (x->rex & REX_B) != 0);
09137c09 2943 for (j = 0; j < x->operands; j++)
252b5132 2944 {
09137c09
SP		 2945 fprintf (stdout, " #%d: ", j + 1);
2946 pt (x->types[j]);
252b5132 2947 fprintf (stdout, "\n");
dc821c5f 2948 if (x->types[j].bitfield.reg
09137c09 2949 || x->types[j].bitfield.regmmx
1b54b8d7 2950 || x->types[j].bitfield.regsimd
09137c09
SP		 2951 || x->types[j].bitfield.sreg2
2952 || x->types[j].bitfield.sreg3
2953 || x->types[j].bitfield.control
2954 || x->types[j].bitfield.debug
2955 || x->types[j].bitfield.test)
2956 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2957 if (operand_type_check (x->types[j], imm))
2958 pe (x->op[j].imms);
2959 if (operand_type_check (x->types[j], disp))
2960 pe (x->op[j].disps);
252b5132
RH		 2961 }
2962}
2963
2964static void
d3ce72d0 2965pte (insn_template *t)
252b5132 2966{
09137c09 2967 unsigned int j;
252b5132 2968 fprintf (stdout, " %d operands ", t->operands);
47926f60 2969 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2970 if (t->extension_opcode != None)
2971 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2972 if (t->opcode_modifier.d)
252b5132 2973 fprintf (stdout, "D");
40fb9820 2974 if (t->opcode_modifier.w)
252b5132
RH		 2975 fprintf (stdout, "W");
2976 fprintf (stdout, "\n");
09137c09 2977 for (j = 0; j < t->operands; j++)
252b5132 2978 {
09137c09
SP		 2979 fprintf (stdout, " #%d type ", j + 1);
2980 pt (t->operand_types[j]);
252b5132
RH		 2981 fprintf (stdout, "\n");
2982 }
2983}
2984
2985static void
e3bb37b5 2986pe (expressionS *e)
252b5132 2987{
24eab124 2988 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2989 fprintf (stdout, " add_number %ld (%lx)\n",
2990 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2991 if (e->X_add_symbol)
2992 {
2993 fprintf (stdout, " add_symbol ");
2994 ps (e->X_add_symbol);
2995 fprintf (stdout, "\n");
2996 }
2997 if (e->X_op_symbol)
2998 {
2999 fprintf (stdout, " op_symbol ");
3000 ps (e->X_op_symbol);
3001 fprintf (stdout, "\n");
3002 }
3003}
3004
3005static void
e3bb37b5 3006ps (symbolS *s)
252b5132
RH		 3007{
3008 fprintf (stdout, "%s type %s%s",
3009 S_GET_NAME (s),
3010 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3011 segment_name (S_GET_SEGMENT (s)));
3012}
3013
7b81dfbb 3014static struct type_name
252b5132 3015 {
40fb9820
L		 3016 i386_operand_type mask;
3017 const char *name;
252b5132 3018 }
7b81dfbb 3019const type_names[] =
252b5132 3020{
40fb9820
L		 3021 { OPERAND_TYPE_REG8, "r8" },
3022 { OPERAND_TYPE_REG16, "r16" },
3023 { OPERAND_TYPE_REG32, "r32" },
3024 { OPERAND_TYPE_REG64, "r64" },
3025 { OPERAND_TYPE_IMM8, "i8" },
3026 { OPERAND_TYPE_IMM8, "i8s" },
3027 { OPERAND_TYPE_IMM16, "i16" },
3028 { OPERAND_TYPE_IMM32, "i32" },
3029 { OPERAND_TYPE_IMM32S, "i32s" },
3030 { OPERAND_TYPE_IMM64, "i64" },
3031 { OPERAND_TYPE_IMM1, "i1" },
3032 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3033 { OPERAND_TYPE_DISP8, "d8" },
3034 { OPERAND_TYPE_DISP16, "d16" },
3035 { OPERAND_TYPE_DISP32, "d32" },
3036 { OPERAND_TYPE_DISP32S, "d32s" },
3037 { OPERAND_TYPE_DISP64, "d64" },
3038 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3039 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3040 { OPERAND_TYPE_CONTROL, "control reg" },
3041 { OPERAND_TYPE_TEST, "test reg" },
3042 { OPERAND_TYPE_DEBUG, "debug reg" },
3043 { OPERAND_TYPE_FLOATREG, "FReg" },
3044 { OPERAND_TYPE_FLOATACC, "FAcc" },
3045 { OPERAND_TYPE_SREG2, "SReg2" },
3046 { OPERAND_TYPE_SREG3, "SReg3" },
3047 { OPERAND_TYPE_ACC, "Acc" },
3048 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3049 { OPERAND_TYPE_REGMMX, "rMMX" },
3050 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 3051 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 3052 { OPERAND_TYPE_REGZMM, "rZMM" },
3053 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 3054 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 3055};
3056
3057static void
40fb9820 3058pt (i386_operand_type t)
252b5132 3059{
40fb9820 3060 unsigned int j;
c6fb90c8 3061 i386_operand_type a;
252b5132 3062
40fb9820 3063 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 3064 {
3065 a = operand_type_and (t, type_names[j].mask);
0349dc08 3066 if (!operand_type_all_zero (&a))
c6fb90c8
L		 3067 fprintf (stdout, "%s, ", type_names[j].name);
3068 }
252b5132
RH		 3069 fflush (stdout);
3070}
3071
3072#endif /* DEBUG386 */
3073\f
252b5132 3074static bfd_reloc_code_real_type
3956db08 3075reloc (unsigned int size,
64e74474
AM		 3076 int pcrel,
3077 int sign,
3078 bfd_reloc_code_real_type other)
252b5132 3079{
47926f60 3080 if (other != NO_RELOC)
3956db08 3081 {
91d6fa6a 3082 reloc_howto_type *rel;
3956db08
JB		 3083
3084 if (size == 8)
3085 switch (other)
3086 {
64e74474
AM		 3087 case BFD_RELOC_X86_64_GOT32:
3088 return BFD_RELOC_X86_64_GOT64;
3089 break;
553d1284
L		 3090 case BFD_RELOC_X86_64_GOTPLT64:
3091 return BFD_RELOC_X86_64_GOTPLT64;
3092 break;
64e74474
AM		 3093 case BFD_RELOC_X86_64_PLTOFF64:
3094 return BFD_RELOC_X86_64_PLTOFF64;
3095 break;
3096 case BFD_RELOC_X86_64_GOTPC32:
3097 other = BFD_RELOC_X86_64_GOTPC64;
3098 break;
3099 case BFD_RELOC_X86_64_GOTPCREL:
3100 other = BFD_RELOC_X86_64_GOTPCREL64;
3101 break;
3102 case BFD_RELOC_X86_64_TPOFF32:
3103 other = BFD_RELOC_X86_64_TPOFF64;
3104 break;
3105 case BFD_RELOC_X86_64_DTPOFF32:
3106 other = BFD_RELOC_X86_64_DTPOFF64;
3107 break;
3108 default:
3109 break;
3956db08 3110 }
e05278af 3111
8ce3d284 3112#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 3113 if (other == BFD_RELOC_SIZE32)
3114 {
3115 if (size == 8)
1ab668bf 3116 other = BFD_RELOC_SIZE64;
8fd4256d 3117 if (pcrel)
1ab668bf
AM		 3118 {
3119 as_bad (_("there are no pc-relative size relocations"));
3120 return NO_RELOC;
3121 }
8fd4256d 3122 }
8ce3d284 3123#endif
8fd4256d 3124
e05278af 3125 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 3126 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 3127 sign = -1;
3128
91d6fa6a
NC		 3129 rel = bfd_reloc_type_lookup (stdoutput, other);
3130 if (!rel)
3956db08 3131 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 3132 else if (size != bfd_get_reloc_size (rel))
3956db08 3133 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 3134 bfd_get_reloc_size (rel),
3956db08 3135 size);
91d6fa6a 3136 else if (pcrel && !rel->pc_relative)
3956db08 3137 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 3138 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 3139 && !sign)
91d6fa6a 3140 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 3141 && sign > 0))
3956db08
JB		 3142 as_bad (_("relocated field and relocation type differ in signedness"));
3143 else
3144 return other;
3145 return NO_RELOC;
3146 }
252b5132
RH		 3147
3148 if (pcrel)
3149 {
3e73aa7c 3150 if (!sign)
3956db08 3151 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 3152 switch (size)
3153 {
3154 case 1: return BFD_RELOC_8_PCREL;
3155 case 2: return BFD_RELOC_16_PCREL;
d258b828 3156 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 3157 case 8: return BFD_RELOC_64_PCREL;
252b5132 3158 }
3956db08 3159 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 3160 }
3161 else
3162 {
3956db08 3163 if (sign > 0)
e5cb08ac 3164 switch (size)
3e73aa7c
JH		 3165 {
3166 case 4: return BFD_RELOC_X86_64_32S;
3167 }
3168 else
3169 switch (size)
3170 {
3171 case 1: return BFD_RELOC_8;
3172 case 2: return BFD_RELOC_16;
3173 case 4: return BFD_RELOC_32;
3174 case 8: return BFD_RELOC_64;
3175 }
3956db08
JB		 3176 as_bad (_("cannot do %s %u byte relocation"),
3177 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 3178 }
3179
0cc9e1d3 3180 return NO_RELOC;
252b5132
RH		 3181}
3182
47926f60
KH		 3183/* Here we decide which fixups can be adjusted to make them relative to
3184 the beginning of the section instead of the symbol. Basically we need
3185 to make sure that the dynamic relocations are done correctly, so in
3186 some cases we force the original symbol to be used. */
3187
252b5132 3188int
e3bb37b5 3189tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 3190{
6d249963 3191#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 3192 if (!IS_ELF)
31312f95
AM		 3193 return 1;
3194
a161fe53
AM		 3195 /* Don't adjust pc-relative references to merge sections in 64-bit
3196 mode. */
3197 if (use_rela_relocations
3198 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3199 && fixP->fx_pcrel)
252b5132 3200 return 0;
31312f95 3201
8d01d9a9
AJ		 3202 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3203 and changed later by validate_fix. */
3204 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3205 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3206 return 0;
3207
8fd4256d
L		 3208 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3209 for size relocations. */
3210 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3211 || fixP->fx_r_type == BFD_RELOC_SIZE64
3212 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 3213 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3214 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 3215 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3216 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3217 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3218 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3219 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3220 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3221 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3222 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3223 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3224 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3225 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3226 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3227 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3228 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3229 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3230 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3231 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3232 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3233 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3234 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3235 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3236 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3237 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3238 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3239 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3240 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3241 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3242 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3243 return 0;
31312f95 3244#endif
252b5132
RH		 3245 return 1;
3246}
252b5132 3247
b4cac588 3248static int
e3bb37b5 3249intel_float_operand (const char *mnemonic)
252b5132 3250{
9306ca4a
JB		 3251 /* Note that the value returned is meaningful only for opcodes with (memory)
3252 operands, hence the code here is free to improperly handle opcodes that
3253 have no operands (for better performance and smaller code). */
3254
3255 if (mnemonic[0] != 'f')
3256 return 0; /* non-math */
3257
3258 switch (mnemonic[1])
3259 {
3260 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3261 the fs segment override prefix not currently handled because no
3262 call path can make opcodes without operands get here */
3263 case 'i':
3264 return 2 /* integer op */;
3265 case 'l':
3266 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3267 return 3; /* fldcw/fldenv */
3268 break;
3269 case 'n':
3270 if (mnemonic[2] != 'o' /* fnop */)
3271 return 3; /* non-waiting control op */
3272 break;
3273 case 'r':
3274 if (mnemonic[2] == 's')
3275 return 3; /* frstor/frstpm */
3276 break;
3277 case 's':
3278 if (mnemonic[2] == 'a')
3279 return 3; /* fsave */
3280 if (mnemonic[2] == 't')
3281 {
3282 switch (mnemonic[3])
3283 {
3284 case 'c': /* fstcw */
3285 case 'd': /* fstdw */
3286 case 'e': /* fstenv */
3287 case 's': /* fsts[gw] */
3288 return 3;
3289 }
3290 }
3291 break;
3292 case 'x':
3293 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3294 return 0; /* fxsave/fxrstor are not really math ops */
3295 break;
3296 }
252b5132 3297
9306ca4a 3298 return 1;
252b5132
RH		 3299}
3300
c0f3af97
L		 3301/* Build the VEX prefix. */
3302
3303static void
d3ce72d0 3304build_vex_prefix (const insn_template *t)
c0f3af97
L		 3305{
3306 unsigned int register_specifier;
3307 unsigned int implied_prefix;
3308 unsigned int vector_length;
3309
3310 /* Check register specifier. */
3311 if (i.vex.register_specifier)
43234a1e
L		 3312 {
3313 register_specifier =
3314 ~register_number (i.vex.register_specifier) & 0xf;
3315 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3316 }
c0f3af97
L		 3317 else
3318 register_specifier = 0xf;
3319
33eaf5de 3320 /* Use 2-byte VEX prefix by swapping destination and source
fa99fab2 3321 operand. */
86fa6981
L		 3322 if (i.vec_encoding != vex_encoding_vex3
3323 && i.dir_encoding == dir_encoding_default
fa99fab2 3324 && i.operands == i.reg_operands
7f399153 3325 && i.tm.opcode_modifier.vexopcode == VEX0F
86fa6981 3326 && i.tm.opcode_modifier.load
fa99fab2
L		 3327 && i.rex == REX_B)
3328 {
3329 unsigned int xchg = i.operands - 1;
3330 union i386_op temp_op;
3331 i386_operand_type temp_type;
3332
3333 temp_type = i.types[xchg];
3334 i.types[xchg] = i.types[0];
3335 i.types[0] = temp_type;
3336 temp_op = i.op[xchg];
3337 i.op[xchg] = i.op[0];
3338 i.op[0] = temp_op;
3339
9c2799c2 3340 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3341
3342 i.rex = REX_R;
3343 xchg = i.rm.regmem;
3344 i.rm.regmem = i.rm.reg;
3345 i.rm.reg = xchg;
3346
3347 /* Use the next insn. */
3348 i.tm = t[1];
3349 }
3350
539f890d
L		 3351 if (i.tm.opcode_modifier.vex == VEXScalar)
3352 vector_length = avxscalar;
10c17abd
JB		 3353 else if (i.tm.opcode_modifier.vex == VEX256)
3354 vector_length = 1;
539f890d 3355 else
10c17abd
JB		 3356 {
3357 unsigned int op;
3358
3359 vector_length = 0;
3360 for (op = 0; op < t->operands; ++op)
3361 if (t->operand_types[op].bitfield.xmmword
3362 && t->operand_types[op].bitfield.ymmword
3363 && i.types[op].bitfield.ymmword)
3364 {
3365 vector_length = 1;
3366 break;
3367 }
3368 }
c0f3af97
L		 3369
3370 switch ((i.tm.base_opcode >> 8) & 0xff)
3371 {
3372 case 0:
3373 implied_prefix = 0;
3374 break;
3375 case DATA_PREFIX_OPCODE:
3376 implied_prefix = 1;
3377 break;
3378 case REPE_PREFIX_OPCODE:
3379 implied_prefix = 2;
3380 break;
3381 case REPNE_PREFIX_OPCODE:
3382 implied_prefix = 3;
3383 break;
3384 default:
3385 abort ();
3386 }
3387
3388 /* Use 2-byte VEX prefix if possible. */
86fa6981
L		 3389 if (i.vec_encoding != vex_encoding_vex3
3390 && i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3391 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3392 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3393 {
3394 /* 2-byte VEX prefix. */
3395 unsigned int r;
3396
3397 i.vex.length = 2;
3398 i.vex.bytes[0] = 0xc5;
3399
3400 /* Check the REX.R bit. */
3401 r = (i.rex & REX_R) ? 0 : 1;
3402 i.vex.bytes[1] = (r << 7
3403 | register_specifier << 3
3404 | vector_length << 2
3405 | implied_prefix);
3406 }
3407 else
3408 {
3409 /* 3-byte VEX prefix. */
3410 unsigned int m, w;
3411
f88c9eb0 3412 i.vex.length = 3;
f88c9eb0 3413
7f399153 3414 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3415 {
7f399153
L		 3416 case VEX0F:
3417 m = 0x1;
80de6e00 3418 i.vex.bytes[0] = 0xc4;
7f399153
L		 3419 break;
3420 case VEX0F38:
3421 m = 0x2;
80de6e00 3422 i.vex.bytes[0] = 0xc4;
7f399153
L		 3423 break;
3424 case VEX0F3A:
3425 m = 0x3;
80de6e00 3426 i.vex.bytes[0] = 0xc4;
7f399153
L		 3427 break;
3428 case XOP08:
5dd85c99
SP		 3429 m = 0x8;
3430 i.vex.bytes[0] = 0x8f;
7f399153
L		 3431 break;
3432 case XOP09:
f88c9eb0
SP		 3433 m = 0x9;
3434 i.vex.bytes[0] = 0x8f;
7f399153
L		 3435 break;
3436 case XOP0A:
f88c9eb0
SP		 3437 m = 0xa;
3438 i.vex.bytes[0] = 0x8f;
7f399153
L		 3439 break;
3440 default:
3441 abort ();
f88c9eb0 3442 }
c0f3af97 3443
c0f3af97
L		 3444 /* The high 3 bits of the second VEX byte are 1's compliment
3445 of RXB bits from REX. */
3446 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3447
3448 /* Check the REX.W bit. */
3449 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3450 if (i.tm.opcode_modifier.vexw == VEXW1)
3451 w = 1;
c0f3af97
L		 3452
3453 i.vex.bytes[2] = (w << 7
3454 | register_specifier << 3
3455 | vector_length << 2
3456 | implied_prefix);
3457 }
3458}
3459
e771e7c9
JB		 3460static INLINE bfd_boolean
3461is_evex_encoding (const insn_template *t)
3462{
3463 return t->opcode_modifier.evex
3464 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3465 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3466}
3467
43234a1e
L		 3468/* Build the EVEX prefix. */
3469
3470static void
3471build_evex_prefix (void)
3472{
3473 unsigned int register_specifier;
3474 unsigned int implied_prefix;
3475 unsigned int m, w;
3476 rex_byte vrex_used = 0;
3477
3478 /* Check register specifier. */
3479 if (i.vex.register_specifier)
3480 {
3481 gas_assert ((i.vrex & REX_X) == 0);
3482
3483 register_specifier = i.vex.register_specifier->reg_num;
3484 if ((i.vex.register_specifier->reg_flags & RegRex))
3485 register_specifier += 8;
3486 /* The upper 16 registers are encoded in the fourth byte of the
3487 EVEX prefix. */
3488 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3489 i.vex.bytes[3] = 0x8;
3490 register_specifier = ~register_specifier & 0xf;
3491 }
3492 else
3493 {
3494 register_specifier = 0xf;
3495
3496 /* Encode upper 16 vector index register in the fourth byte of
3497 the EVEX prefix. */
3498 if (!(i.vrex & REX_X))
3499 i.vex.bytes[3] = 0x8;
3500 else
3501 vrex_used |= REX_X;
3502 }
3503
3504 switch ((i.tm.base_opcode >> 8) & 0xff)
3505 {
3506 case 0:
3507 implied_prefix = 0;
3508 break;
3509 case DATA_PREFIX_OPCODE:
3510 implied_prefix = 1;
3511 break;
3512 case REPE_PREFIX_OPCODE:
3513 implied_prefix = 2;
3514 break;
3515 case REPNE_PREFIX_OPCODE:
3516 implied_prefix = 3;
3517 break;
3518 default:
3519 abort ();
3520 }
3521
3522 /* 4 byte EVEX prefix. */
3523 i.vex.length = 4;
3524 i.vex.bytes[0] = 0x62;
3525
3526 /* mmmm bits. */
3527 switch (i.tm.opcode_modifier.vexopcode)
3528 {
3529 case VEX0F:
3530 m = 1;
3531 break;
3532 case VEX0F38:
3533 m = 2;
3534 break;
3535 case VEX0F3A:
3536 m = 3;
3537 break;
3538 default:
3539 abort ();
3540 break;
3541 }
3542
3543 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3544 bits from REX. */
3545 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3546
3547 /* The fifth bit of the second EVEX byte is 1's compliment of the
3548 REX_R bit in VREX. */
3549 if (!(i.vrex & REX_R))
3550 i.vex.bytes[1] |= 0x10;
3551 else
3552 vrex_used |= REX_R;
3553
3554 if ((i.reg_operands + i.imm_operands) == i.operands)
3555 {
3556 /* When all operands are registers, the REX_X bit in REX is not
3557 used. We reuse it to encode the upper 16 registers, which is
3558 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3559 as 1's compliment. */
3560 if ((i.vrex & REX_B))
3561 {
3562 vrex_used |= REX_B;
3563 i.vex.bytes[1] &= ~0x40;
3564 }
3565 }
3566
3567 /* EVEX instructions shouldn't need the REX prefix. */
3568 i.vrex &= ~vrex_used;
3569 gas_assert (i.vrex == 0);
3570
3571 /* Check the REX.W bit. */
3572 w = (i.rex & REX_W) ? 1 : 0;
3573 if (i.tm.opcode_modifier.vexw)
3574 {
3575 if (i.tm.opcode_modifier.vexw == VEXW1)
3576 w = 1;
3577 }
3578 /* If w is not set it means we are dealing with WIG instruction. */
3579 else if (!w)
3580 {
3581 if (evexwig == evexw1)
3582 w = 1;
3583 }
3584
3585 /* Encode the U bit. */
3586 implied_prefix |= 0x4;
3587
3588 /* The third byte of the EVEX prefix. */
3589 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3590
3591 /* The fourth byte of the EVEX prefix. */
3592 /* The zeroing-masking bit. */
3593 if (i.mask && i.mask->zeroing)
3594 i.vex.bytes[3] |= 0x80;
3595
3596 /* Don't always set the broadcast bit if there is no RC. */
3597 if (!i.rounding)
3598 {
3599 /* Encode the vector length. */
3600 unsigned int vec_length;
3601
e771e7c9
JB		 3602 if (!i.tm.opcode_modifier.evex
3603 || i.tm.opcode_modifier.evex == EVEXDYN)
3604 {
3605 unsigned int op;
3606
3607 vec_length = 0;
3608 for (op = 0; op < i.tm.operands; ++op)
3609 if (i.tm.operand_types[op].bitfield.xmmword
3610 + i.tm.operand_types[op].bitfield.ymmword
3611 + i.tm.operand_types[op].bitfield.zmmword > 1)
3612 {
3613 if (i.types[op].bitfield.zmmword)
3614 i.tm.opcode_modifier.evex = EVEX512;
3615 else if (i.types[op].bitfield.ymmword)
3616 i.tm.opcode_modifier.evex = EVEX256;
3617 else if (i.types[op].bitfield.xmmword)
3618 i.tm.opcode_modifier.evex = EVEX128;
3619 else
3620 continue;
3621 break;
3622 }
3623 }
3624
43234a1e
L		 3625 switch (i.tm.opcode_modifier.evex)
3626 {
3627 case EVEXLIG: /* LL' is ignored */
3628 vec_length = evexlig << 5;
3629 break;
3630 case EVEX128:
3631 vec_length = 0 << 5;
3632 break;
3633 case EVEX256:
3634 vec_length = 1 << 5;
3635 break;
3636 case EVEX512:
3637 vec_length = 2 << 5;
3638 break;
3639 default:
3640 abort ();
3641 break;
3642 }
3643 i.vex.bytes[3] |= vec_length;
3644 /* Encode the broadcast bit. */
3645 if (i.broadcast)
3646 i.vex.bytes[3] |= 0x10;
3647 }
3648 else
3649 {
3650 if (i.rounding->type != saeonly)
3651 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3652 else
d3d3c6db 3653 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3654 }
3655
3656 if (i.mask && i.mask->mask)
3657 i.vex.bytes[3] |= i.mask->mask->reg_num;
3658}
3659
65da13b5
L		 3660static void
3661process_immext (void)
3662{
3663 expressionS *exp;
3664
4c692bc7
JB		 3665 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3666 && i.operands > 0)
65da13b5 3667 {
4c692bc7
JB		 3668 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3669 with an opcode suffix which is coded in the same place as an
3670 8-bit immediate field would be.
3671 Here we check those operands and remove them afterwards. */
65da13b5
L		 3672 unsigned int x;
3673
3674 for (x = 0; x < i.operands; x++)
4c692bc7 3675 if (register_number (i.op[x].regs) != x)
65da13b5 3676 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3677 register_prefix, i.op[x].regs->reg_name, x + 1,
3678 i.tm.name);
3679
3680 i.operands = 0;
65da13b5
L		 3681 }
3682
9916071f
AP		 3683 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3684 {
3685 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3686 suffix which is coded in the same place as an 8-bit immediate
3687 field would be.
3688 Here we check those operands and remove them afterwards. */
3689 unsigned int x;
3690
3691 if (i.operands != 3)
3692 abort();
3693
3694 for (x = 0; x < 2; x++)
3695 if (register_number (i.op[x].regs) != x)
3696 goto bad_register_operand;
3697
3698 /* Check for third operand for mwaitx/monitorx insn. */
3699 if (register_number (i.op[x].regs)
3700 != (x + (i.tm.extension_opcode == 0xfb)))
3701 {
3702bad_register_operand:
3703 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3704 register_prefix, i.op[x].regs->reg_name, x+1,
3705 i.tm.name);
3706 }
3707
3708 i.operands = 0;
3709 }
3710
c0f3af97 3711 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3712 which is coded in the same place as an 8-bit immediate field
3713 would be. Here we fake an 8-bit immediate operand from the
3714 opcode suffix stored in tm.extension_opcode.
3715
c1e679ec 3716 AVX instructions also use this encoding, for some of
c0f3af97 3717 3 argument instructions. */
65da13b5 3718
43234a1e 3719 gas_assert (i.imm_operands <= 1
7ab9ffdd 3720 && (i.operands <= 2
43234a1e 3721 || ((i.tm.opcode_modifier.vex
e771e7c9
JB		 3722 || i.tm.opcode_modifier.vexopcode
3723 || is_evex_encoding (&i.tm))
7ab9ffdd 3724 && i.operands <= 4)));
65da13b5
L		 3725
3726 exp = &im_expressions[i.imm_operands++];
3727 i.op[i.operands].imms = exp;
3728 i.types[i.operands] = imm8;
3729 i.operands++;
3730 exp->X_op = O_constant;
3731 exp->X_add_number = i.tm.extension_opcode;
3732 i.tm.extension_opcode = None;
3733}
3734
42164a71
L		 3735
3736static int
3737check_hle (void)
3738{
3739 switch (i.tm.opcode_modifier.hleprefixok)
3740 {
3741 default:
3742 abort ();
82c2def5 3743 case HLEPrefixNone:
165de32a
L		 3744 as_bad (_("invalid instruction `%s' after `%s'"),
3745 i.tm.name, i.hle_prefix);
42164a71 3746 return 0;
82c2def5 3747 case HLEPrefixLock:
42164a71
L		 3748 if (i.prefix[LOCK_PREFIX])
3749 return 1;
165de32a 3750 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3751 return 0;
82c2def5 3752 case HLEPrefixAny:
42164a71 3753 return 1;
82c2def5 3754 case HLEPrefixRelease:
42164a71
L		 3755 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3756 {
3757 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3758 i.tm.name);
3759 return 0;
3760 }
3761 if (i.mem_operands == 0
3762 || !operand_type_check (i.types[i.operands - 1], anymem))
3763 {
3764 as_bad (_("memory destination needed for instruction `%s'"
3765 " after `xrelease'"), i.tm.name);
3766 return 0;
3767 }
3768 return 1;
3769 }
3770}
3771
b6f8c7c4
L		 3772/* Try the shortest encoding by shortening operand size. */
3773
3774static void
3775optimize_encoding (void)
3776{
3777 int j;
3778
3779 if (optimize_for_space
3780 && i.reg_operands == 1
3781 && i.imm_operands == 1
3782 && !i.types[1].bitfield.byte
3783 && i.op[0].imms->X_op == O_constant
3784 && fits_in_imm7 (i.op[0].imms->X_add_number)
3785 && ((i.tm.base_opcode == 0xa8
3786 && i.tm.extension_opcode == None)
3787 || (i.tm.base_opcode == 0xf6
3788 && i.tm.extension_opcode == 0x0)))
3789 {
3790 /* Optimize: -Os:
3791 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3792 */
3793 unsigned int base_regnum = i.op[1].regs->reg_num;
3794 if (flag_code == CODE_64BIT || base_regnum < 4)
3795 {
3796 i.types[1].bitfield.byte = 1;
3797 /* Ignore the suffix. */
3798 i.suffix = 0;
3799 if (base_regnum >= 4
3800 && !(i.op[1].regs->reg_flags & RegRex))
3801 {
3802 /* Handle SP, BP, SI and DI registers. */
3803 if (i.types[1].bitfield.word)
3804 j = 16;
3805 else if (i.types[1].bitfield.dword)
3806 j = 32;
3807 else
3808 j = 48;
3809 i.op[1].regs -= j;
3810 }
3811 }
3812 }
3813 else if (flag_code == CODE_64BIT
d3d50934
L		 3814 && ((i.types[1].bitfield.qword
3815 && i.reg_operands == 1
b6f8c7c4
L		 3816 && i.imm_operands == 1
3817 && i.op[0].imms->X_op == O_constant
3818 && ((i.tm.base_opcode == 0xb0
3819 && i.tm.extension_opcode == None
3820 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3821 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3822 && (((i.tm.base_opcode == 0x24
3823 || i.tm.base_opcode == 0xa8)
3824 && i.tm.extension_opcode == None)
3825 || (i.tm.base_opcode == 0x80
3826 && i.tm.extension_opcode == 0x4)
3827 || ((i.tm.base_opcode == 0xf6
3828 || i.tm.base_opcode == 0xc6)
3829 && i.tm.extension_opcode == 0x0)))))
d3d50934
L		 3830 || (i.types[0].bitfield.qword
3831 && ((i.reg_operands == 2
3832 && i.op[0].regs == i.op[1].regs
3833 && ((i.tm.base_opcode == 0x30
3834 || i.tm.base_opcode == 0x28)
3835 && i.tm.extension_opcode == None))
3836 || (i.reg_operands == 1
3837 && i.operands == 1
3838 && i.tm.base_opcode == 0x30
3839 && i.tm.extension_opcode == None)))))
b6f8c7c4
L		 3840 {
3841 /* Optimize: -O:
3842 andq $imm31, %r64 -> andl $imm31, %r32
3843 testq $imm31, %r64 -> testl $imm31, %r32
3844 xorq %r64, %r64 -> xorl %r32, %r32
3845 subq %r64, %r64 -> subl %r32, %r32
3846 movq $imm31, %r64 -> movl $imm31, %r32
3847 movq $imm32, %r64 -> movl $imm32, %r32
3848 */
3849 i.tm.opcode_modifier.norex64 = 1;
3850 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3851 {
3852 /* Handle
3853 movq $imm31, %r64 -> movl $imm31, %r32
3854 movq $imm32, %r64 -> movl $imm32, %r32
3855 */
3856 i.tm.operand_types[0].bitfield.imm32 = 1;
3857 i.tm.operand_types[0].bitfield.imm32s = 0;
3858 i.tm.operand_types[0].bitfield.imm64 = 0;
3859 i.types[0].bitfield.imm32 = 1;
3860 i.types[0].bitfield.imm32s = 0;
3861 i.types[0].bitfield.imm64 = 0;
3862 i.types[1].bitfield.dword = 1;
3863 i.types[1].bitfield.qword = 0;
3864 if (i.tm.base_opcode == 0xc6)
3865 {
3866 /* Handle
3867 movq $imm31, %r64 -> movl $imm31, %r32
3868 */
3869 i.tm.base_opcode = 0xb0;
3870 i.tm.extension_opcode = None;
3871 i.tm.opcode_modifier.shortform = 1;
3872 i.tm.opcode_modifier.modrm = 0;
3873 }
3874 }
3875 }
3876 else if (optimize > 1
3877 && i.reg_operands == 3
3878 && i.op[0].regs == i.op[1].regs
3879 && !i.types[2].bitfield.xmmword
3880 && (i.tm.opcode_modifier.vex
7a69eac3 3881 || ((!i.mask || i.mask->zeroing)
b6f8c7c4 3882 && !i.rounding
e771e7c9 3883 && is_evex_encoding (&i.tm)
80c34c38
L		 3884 && (i.vec_encoding != vex_encoding_evex
3885 || i.tm.cpu_flags.bitfield.cpuavx512vl
0089dace 3886 || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
b6f8c7c4
L		 3887 && ((i.tm.base_opcode == 0x55
3888 || i.tm.base_opcode == 0x6655
3889 || i.tm.base_opcode == 0x66df
3890 || i.tm.base_opcode == 0x57
3891 || i.tm.base_opcode == 0x6657
8305403a
L		 3892 || i.tm.base_opcode == 0x66ef
3893 || i.tm.base_opcode == 0x66f8
3894 || i.tm.base_opcode == 0x66f9
3895 || i.tm.base_opcode == 0x66fa
3896 || i.tm.base_opcode == 0x66fb)
b6f8c7c4
L		 3897 && i.tm.extension_opcode == None))
3898 {
3899 /* Optimize: -O2:
8305403a
L		 3900 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3901 vpsubq and vpsubw:
b6f8c7c4
L		 3902 EVEX VOP %zmmM, %zmmM, %zmmN
3903 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3904 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3905 EVEX VOP %ymmM, %ymmM, %ymmN
3906 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3907 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3908 VEX VOP %ymmM, %ymmM, %ymmN
3909 -> VEX VOP %xmmM, %xmmM, %xmmN
3910 VOP, one of vpandn and vpxor:
3911 VEX VOP %ymmM, %ymmM, %ymmN
3912 -> VEX VOP %xmmM, %xmmM, %xmmN
3913 VOP, one of vpandnd and vpandnq:
3914 EVEX VOP %zmmM, %zmmM, %zmmN
3915 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3916 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3917 EVEX VOP %ymmM, %ymmM, %ymmN
3918 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3919 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3920 VOP, one of vpxord and vpxorq:
3921 EVEX VOP %zmmM, %zmmM, %zmmN
3922 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3923 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3924 EVEX VOP %ymmM, %ymmM, %ymmN
3925 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3926 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3927 */
e771e7c9 3928 if (is_evex_encoding (&i.tm))
b6f8c7c4 3929 {
0089dace 3930 if (i.vec_encoding == vex_encoding_evex)
b6f8c7c4
L		 3931 i.tm.opcode_modifier.evex = EVEX128;
3932 else
3933 {
3934 i.tm.opcode_modifier.vex = VEX128;
3935 i.tm.opcode_modifier.vexw = VEXW0;
3936 i.tm.opcode_modifier.evex = 0;
3937 }
3938 }
3939 else
3940 i.tm.opcode_modifier.vex = VEX128;
3941
3942 if (i.tm.opcode_modifier.vex)
3943 for (j = 0; j < 3; j++)
3944 {
3945 i.types[j].bitfield.xmmword = 1;
3946 i.types[j].bitfield.ymmword = 0;
3947 }
3948 }
3949}
3950
252b5132
RH		 3951/* This is the guts of the machine-dependent assembler. LINE points to a
3952 machine dependent instruction. This function is supposed to emit
3953 the frags/bytes it assembles to. */
3954
3955void
65da13b5 3956md_assemble (char *line)
252b5132 3957{
40fb9820 3958 unsigned int j;
83b16ac6 3959 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
d3ce72d0 3960 const insn_template *t;
252b5132 3961
47926f60 3962 /* Initialize globals. */
252b5132
RH		 3963 memset (&i, '\0', sizeof (i));
3964 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3965 i.reloc[j] = NO_RELOC;
252b5132
RH		 3966 memset (disp_expressions, '\0', sizeof (disp_expressions));
3967 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3968 save_stack_p = save_stack;
252b5132
RH		 3969
3970 /* First parse an instruction mnemonic & call i386_operand for the operands.
3971 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3972 start of a (possibly prefixed) mnemonic. */
252b5132 3973
29b0f896
AM		 3974 line = parse_insn (line, mnemonic);
3975 if (line == NULL)
3976 return;
83b16ac6 3977 mnem_suffix = i.suffix;
252b5132 3978
29b0f896 3979 line = parse_operands (line, mnemonic);
ee86248c 3980 this_operand = -1;
8325cc63
JB		 3981 xfree (i.memop1_string);
3982 i.memop1_string = NULL;
29b0f896
AM		 3983 if (line == NULL)
3984 return;
252b5132 3985
29b0f896
AM		 3986 /* Now we've parsed the mnemonic into a set of templates, and have the
3987 operands at hand. */
3988
3989 /* All intel opcodes have reversed operands except for "bound" and
3990 "enter". We also don't reverse intersegment "jmp" and "call"
3991 instructions with 2 immediate operands so that the immediate segment
050dfa73 3992 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3993 if (intel_syntax
3994 && i.operands > 1
29b0f896 3995 && (strcmp (mnemonic, "bound") != 0)
30123838 3996 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3997 && !(operand_type_check (i.types[0], imm)
3998 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3999 swap_operands ();
4000
ec56d5c0
JB		 4001 /* The order of the immediates should be reversed
4002 for 2 immediates extrq and insertq instructions */
4003 if (i.imm_operands == 2
4004 && (strcmp (mnemonic, "extrq") == 0
4005 || strcmp (mnemonic, "insertq") == 0))
4006 swap_2_operands (0, 1);
4007
29b0f896
AM		 4008 if (i.imm_operands)
4009 optimize_imm ();
4010
b300c311
L		 4011 /* Don't optimize displacement for movabs since it only takes 64bit
4012 displacement. */
4013 if (i.disp_operands
a501d77e 4014 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 4015 && (flag_code != CODE_64BIT
4016 || strcmp (mnemonic, "movabs") != 0))
4017 optimize_disp ();
29b0f896
AM		 4018
4019 /* Next, we find a template that matches the given insn,
4020 making sure the overlap of the given operands types is consistent
4021 with the template operand types. */
252b5132 4022
83b16ac6 4023 if (!(t = match_template (mnem_suffix)))
29b0f896 4024 return;
252b5132 4025
7bab8ab5 4026 if (sse_check != check_none
81f8a913 4027 && !i.tm.opcode_modifier.noavx
6e3e5c9e 4028 && !i.tm.cpu_flags.bitfield.cpuavx
daf50ae7
L		 4029 && (i.tm.cpu_flags.bitfield.cpusse
4030 || i.tm.cpu_flags.bitfield.cpusse2
4031 || i.tm.cpu_flags.bitfield.cpusse3
4032 || i.tm.cpu_flags.bitfield.cpussse3
4033 || i.tm.cpu_flags.bitfield.cpusse4_1
6e3e5c9e
JB		 4034 || i.tm.cpu_flags.bitfield.cpusse4_2
4035 || i.tm.cpu_flags.bitfield.cpupclmul
4036 || i.tm.cpu_flags.bitfield.cpuaes
4037 || i.tm.cpu_flags.bitfield.cpugfni))
daf50ae7 4038 {
7bab8ab5 4039 (sse_check == check_warning
daf50ae7
L		 4040 ? as_warn
4041 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4042 }
4043
321fd21e
L		 4044 /* Zap movzx and movsx suffix. The suffix has been set from
4045 "word ptr" or "byte ptr" on the source operand in Intel syntax
4046 or extracted from mnemonic in AT&T syntax. But we'll use
4047 the destination register to choose the suffix for encoding. */
4048 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 4049 {
321fd21e
L		 4050 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4051 there is no suffix, the default will be byte extension. */
4052 if (i.reg_operands != 2
4053 && !i.suffix
7ab9ffdd 4054 && intel_syntax)
321fd21e
L		 4055 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4056
4057 i.suffix = 0;
cd61ebfe 4058 }
24eab124 4059
40fb9820 4060 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 4061 if (!add_prefix (FWAIT_OPCODE))
4062 return;
252b5132 4063
d5de92cf
L		 4064 /* Check if REP prefix is OK. */
4065 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4066 {
4067 as_bad (_("invalid instruction `%s' after `%s'"),
4068 i.tm.name, i.rep_prefix);
4069 return;
4070 }
4071
c1ba0266
L		 4072 /* Check for lock without a lockable instruction. Destination operand
4073 must be memory unless it is xchg (0x86). */
c32fa91d
L		 4074 if (i.prefix[LOCK_PREFIX]
4075 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 4076 || i.mem_operands == 0
4077 || (i.tm.base_opcode != 0x86
4078 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 4079 {
4080 as_bad (_("expecting lockable instruction after `lock'"));
4081 return;
4082 }
4083
42164a71 4084 /* Check if HLE prefix is OK. */
165de32a 4085 if (i.hle_prefix && !check_hle ())
42164a71
L		 4086 return;
4087
7e8b059b
L		 4088 /* Check BND prefix. */
4089 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4090 as_bad (_("expecting valid branch instruction after `bnd'"));
4091
04ef582a 4092 /* Check NOTRACK prefix. */
9fef80d6
L		 4093 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4094 as_bad (_("expecting indirect branch instruction after `notrack'"));
04ef582a 4095
327e8c42
JB		 4096 if (i.tm.cpu_flags.bitfield.cpumpx)
4097 {
4098 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4099 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4100 else if (flag_code != CODE_16BIT
4101 ? i.prefix[ADDR_PREFIX]
4102 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4103 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4104 }
7e8b059b
L		 4105
4106 /* Insert BND prefix. */
4107 if (add_bnd_prefix
4108 && i.tm.opcode_modifier.bndprefixok
4109 && !i.prefix[BND_PREFIX])
4110 add_prefix (BND_PREFIX_OPCODE);
4111
29b0f896 4112 /* Check string instruction segment overrides. */
40fb9820 4113 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 4114 {
4115 if (!check_string ())
5dd0794d 4116 return;
fc0763e6 4117 i.disp_operands = 0;
29b0f896 4118 }
5dd0794d 4119
b6f8c7c4
L		 4120 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4121 optimize_encoding ();
4122
29b0f896
AM		 4123 if (!process_suffix ())
4124 return;
e413e4e9 4125
bc0844ae
L		 4126 /* Update operand types. */
4127 for (j = 0; j < i.operands; j++)
4128 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4129
29b0f896
AM		 4130 /* Make still unresolved immediate matches conform to size of immediate
4131 given in i.suffix. */
4132 if (!finalize_imm ())
4133 return;
252b5132 4134
40fb9820 4135 if (i.types[0].bitfield.imm1)
29b0f896 4136 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 4137
9afe6eb8
L		 4138 /* We only need to check those implicit registers for instructions
4139 with 3 operands or less. */
4140 if (i.operands <= 3)
4141 for (j = 0; j < i.operands; j++)
4142 if (i.types[j].bitfield.inoutportreg
4143 || i.types[j].bitfield.shiftcount
1b54b8d7 4144 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
9afe6eb8 4145 i.reg_operands--;
40fb9820 4146
c0f3af97
L		 4147 /* ImmExt should be processed after SSE2AVX. */
4148 if (!i.tm.opcode_modifier.sse2avx
4149 && i.tm.opcode_modifier.immext)
65da13b5 4150 process_immext ();
252b5132 4151
29b0f896
AM		 4152 /* For insns with operands there are more diddles to do to the opcode. */
4153 if (i.operands)
4154 {
4155 if (!process_operands ())
4156 return;
4157 }
40fb9820 4158 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 4159 {
4160 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4161 as_warn (_("translating to `%sp'"), i.tm.name);
4162 }
252b5132 4163
e771e7c9
JB		 4164 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.vexopcode
4165 || is_evex_encoding (&i.tm))
9e5e5283
L		 4166 {
4167 if (flag_code == CODE_16BIT)
4168 {
4169 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4170 i.tm.name);
4171 return;
4172 }
c0f3af97 4173
9e5e5283
L		 4174 if (i.tm.opcode_modifier.vex)
4175 build_vex_prefix (t);
4176 else
4177 build_evex_prefix ();
4178 }
43234a1e 4179
5dd85c99
SP		 4180 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4181 instructions may define INT_OPCODE as well, so avoid this corner
4182 case for those instructions that use MODRM. */
4183 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 4184 && !i.tm.opcode_modifier.modrm
4185 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 4186 {
4187 i.tm.base_opcode = INT3_OPCODE;
4188 i.imm_operands = 0;
4189 }
252b5132 4190
40fb9820
L		 4191 if ((i.tm.opcode_modifier.jump
4192 || i.tm.opcode_modifier.jumpbyte
4193 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 4194 && i.op[0].disps->X_op == O_constant)
4195 {
4196 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4197 the absolute address given by the constant. Since ix86 jumps and
4198 calls are pc relative, we need to generate a reloc. */
4199 i.op[0].disps->X_add_symbol = &abs_symbol;
4200 i.op[0].disps->X_op = O_symbol;
4201 }
252b5132 4202
40fb9820 4203 if (i.tm.opcode_modifier.rex64)
161a04f6 4204 i.rex |= REX_W;
252b5132 4205
29b0f896
AM		 4206 /* For 8 bit registers we need an empty rex prefix. Also if the
4207 instruction already has a prefix, we need to convert old
4208 registers to new ones. */
773f551c 4209
dc821c5f 4210 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
29b0f896 4211 && (i.op[0].regs->reg_flags & RegRex64) != 0)
dc821c5f 4212 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
29b0f896 4213 && (i.op[1].regs->reg_flags & RegRex64) != 0)
dc821c5f
JB		 4214 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4215 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
29b0f896
AM		 4216 && i.rex != 0))
4217 {
4218 int x;
726c5dcd 4219
29b0f896
AM		 4220 i.rex |= REX_OPCODE;
4221 for (x = 0; x < 2; x++)
4222 {
4223 /* Look for 8 bit operand that uses old registers. */
dc821c5f 4224 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
29b0f896 4225 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 4226 {
29b0f896
AM		 4227 /* In case it is "hi" register, give up. */
4228 if (i.op[x].regs->reg_num > 3)
a540244d 4229 as_bad (_("can't encode register '%s%s' in an "
4eed87de 4230 "instruction requiring REX prefix."),
a540244d 4231 register_prefix, i.op[x].regs->reg_name);
773f551c 4232
29b0f896
AM		 4233 /* Otherwise it is equivalent to the extended register.
4234 Since the encoding doesn't change this is merely
4235 cosmetic cleanup for debug output. */
4236
4237 i.op[x].regs = i.op[x].regs + 8;
773f551c 4238 }
29b0f896
AM		 4239 }
4240 }
773f551c 4241
6b6b6807
L		 4242 if (i.rex == 0 && i.rex_encoding)
4243 {
4244 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4245 that uses legacy register. If it is "hi" register, don't add
4246 the REX_OPCODE byte. */
4247 int x;
4248 for (x = 0; x < 2; x++)
4249 if (i.types[x].bitfield.reg
4250 && i.types[x].bitfield.byte
4251 && (i.op[x].regs->reg_flags & RegRex64) == 0
4252 && i.op[x].regs->reg_num > 3)
4253 {
4254 i.rex_encoding = FALSE;
4255 break;
4256 }
4257
4258 if (i.rex_encoding)
4259 i.rex = REX_OPCODE;
4260 }
4261
7ab9ffdd 4262 if (i.rex != 0)
29b0f896
AM		 4263 add_prefix (REX_OPCODE | i.rex);
4264
4265 /* We are ready to output the insn. */
4266 output_insn ();
4267}
4268
4269static char *
e3bb37b5 4270parse_insn (char *line, char *mnemonic)
29b0f896
AM		 4271{
4272 char *l = line;
4273 char *token_start = l;
4274 char *mnem_p;
5c6af06e 4275 int supported;
d3ce72d0 4276 const insn_template *t;
b6169b20 4277 char *dot_p = NULL;
29b0f896 4278
29b0f896
AM		 4279 while (1)
4280 {
4281 mnem_p = mnemonic;
4282 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4283 {
b6169b20
L		 4284 if (*mnem_p == '.')
4285 dot_p = mnem_p;
29b0f896
AM		 4286 mnem_p++;
4287 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 4288 {
29b0f896
AM		 4289 as_bad (_("no such instruction: `%s'"), token_start);
4290 return NULL;
4291 }
4292 l++;
4293 }
4294 if (!is_space_char (*l)
4295 && *l != END_OF_INSN
e44823cf
JB		 4296 && (intel_syntax
4297 || (*l != PREFIX_SEPARATOR
4298 && *l != ',')))
29b0f896
AM		 4299 {
4300 as_bad (_("invalid character %s in mnemonic"),
4301 output_invalid (*l));
4302 return NULL;
4303 }
4304 if (token_start == l)
4305 {
e44823cf 4306 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 4307 as_bad (_("expecting prefix; got nothing"));
4308 else
4309 as_bad (_("expecting mnemonic; got nothing"));
4310 return NULL;
4311 }
45288df1 4312
29b0f896 4313 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 4314 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 4315
29b0f896
AM		 4316 if (*l != END_OF_INSN
4317 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4318 && current_templates
40fb9820 4319 && current_templates->start->opcode_modifier.isprefix)
29b0f896 4320 {
c6fb90c8 4321 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 4322 {
4323 as_bad ((flag_code != CODE_64BIT
4324 ? _("`%s' is only supported in 64-bit mode")
4325 : _("`%s' is not supported in 64-bit mode")),
4326 current_templates->start->name);
4327 return NULL;
4328 }
29b0f896
AM		 4329 /* If we are in 16-bit mode, do not allow addr16 or data16.
4330 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 4331 if ((current_templates->start->opcode_modifier.size16
4332 || current_templates->start->opcode_modifier.size32)
29b0f896 4333 && flag_code != CODE_64BIT
40fb9820 4334 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 4335 ^ (flag_code == CODE_16BIT)))
4336 {
4337 as_bad (_("redundant %s prefix"),
4338 current_templates->start->name);
4339 return NULL;
45288df1 4340 }
86fa6981 4341 if (current_templates->start->opcode_length == 0)
29b0f896 4342 {
86fa6981
L		 4343 /* Handle pseudo prefixes. */
4344 switch (current_templates->start->base_opcode)
4345 {
4346 case 0x0:
4347 /* {disp8} */
4348 i.disp_encoding = disp_encoding_8bit;
4349 break;
4350 case 0x1:
4351 /* {disp32} */
4352 i.disp_encoding = disp_encoding_32bit;
4353 break;
4354 case 0x2:
4355 /* {load} */
4356 i.dir_encoding = dir_encoding_load;
4357 break;
4358 case 0x3:
4359 /* {store} */
4360 i.dir_encoding = dir_encoding_store;
4361 break;
4362 case 0x4:
4363 /* {vex2} */
4364 i.vec_encoding = vex_encoding_vex2;
4365 break;
4366 case 0x5:
4367 /* {vex3} */
4368 i.vec_encoding = vex_encoding_vex3;
4369 break;
4370 case 0x6:
4371 /* {evex} */
4372 i.vec_encoding = vex_encoding_evex;
4373 break;
6b6b6807
L		 4374 case 0x7:
4375 /* {rex} */
4376 i.rex_encoding = TRUE;
4377 break;
b6f8c7c4
L		 4378 case 0x8:
4379 /* {nooptimize} */
4380 i.no_optimize = TRUE;
4381 break;
86fa6981
L		 4382 default:
4383 abort ();
4384 }
4385 }
4386 else
4387 {
4388 /* Add prefix, checking for repeated prefixes. */
4e9ac44a 4389 switch (add_prefix (current_templates->start->base_opcode))
86fa6981 4390 {
4e9ac44a
L		 4391 case PREFIX_EXIST:
4392 return NULL;
4393 case PREFIX_DS:
d777820b 4394 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4e9ac44a
L		 4395 i.notrack_prefix = current_templates->start->name;
4396 break;
4397 case PREFIX_REP:
4398 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4399 i.hle_prefix = current_templates->start->name;
4400 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4401 i.bnd_prefix = current_templates->start->name;
4402 else
4403 i.rep_prefix = current_templates->start->name;
4404 break;
4405 default:
4406 break;
86fa6981 4407 }
29b0f896
AM		 4408 }
4409 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4410 token_start = ++l;
4411 }
4412 else
4413 break;
4414 }
45288df1 4415
30a55f88 4416 if (!current_templates)
b6169b20 4417 {
f8a5c266
L		 4418 /* Check if we should swap operand or force 32bit displacement in
4419 encoding. */
30a55f88 4420 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
86fa6981 4421 i.dir_encoding = dir_encoding_store;
8d63c93e 4422 else if (mnem_p - 3 == dot_p
a501d77e
L		 4423 && dot_p[1] == 'd'
4424 && dot_p[2] == '8')
4425 i.disp_encoding = disp_encoding_8bit;
8d63c93e 4426 else if (mnem_p - 4 == dot_p
f8a5c266
L		 4427 && dot_p[1] == 'd'
4428 && dot_p[2] == '3'
4429 && dot_p[3] == '2')
a501d77e 4430 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 4431 else
4432 goto check_suffix;
4433 mnem_p = dot_p;
4434 *dot_p = '\0';
d3ce72d0 4435 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 4436 }
4437
29b0f896
AM		 4438 if (!current_templates)
4439 {
b6169b20 4440check_suffix:
29b0f896
AM		 4441 /* See if we can get a match by trimming off a suffix. */
4442 switch (mnem_p[-1])
4443 {
4444 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 4445 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4446 i.suffix = SHORT_MNEM_SUFFIX;
4447 else
1a0670f3 4448 /* Fall through. */
29b0f896
AM		 4449 case BYTE_MNEM_SUFFIX:
4450 case QWORD_MNEM_SUFFIX:
4451 i.suffix = mnem_p[-1];
4452 mnem_p[-1] = '\0';
d3ce72d0
NC		 4453 current_templates = (const templates *) hash_find (op_hash,
4454 mnemonic);
29b0f896
AM		 4455 break;
4456 case SHORT_MNEM_SUFFIX:
4457 case LONG_MNEM_SUFFIX:
4458 if (!intel_syntax)
4459 {
4460 i.suffix = mnem_p[-1];
4461 mnem_p[-1] = '\0';
d3ce72d0
NC		 4462 current_templates = (const templates *) hash_find (op_hash,
4463 mnemonic);
29b0f896
AM		 4464 }
4465 break;
252b5132 4466
29b0f896
AM		 4467 /* Intel Syntax. */
4468 case 'd':
4469 if (intel_syntax)
4470 {
9306ca4a 4471 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 4472 i.suffix = SHORT_MNEM_SUFFIX;
4473 else
4474 i.suffix = LONG_MNEM_SUFFIX;
4475 mnem_p[-1] = '\0';
d3ce72d0
NC		 4476 current_templates = (const templates *) hash_find (op_hash,
4477 mnemonic);
29b0f896
AM		 4478 }
4479 break;
4480 }
4481 if (!current_templates)
4482 {
4483 as_bad (_("no such instruction: `%s'"), token_start);
4484 return NULL;
4485 }
4486 }
252b5132 4487
40fb9820
L		 4488 if (current_templates->start->opcode_modifier.jump
4489 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 4490 {
4491 /* Check for a branch hint. We allow ",pt" and ",pn" for
4492 predict taken and predict not taken respectively.
4493 I'm not sure that branch hints actually do anything on loop
4494 and jcxz insns (JumpByte) for current Pentium4 chips. They
4495 may work in the future and it doesn't hurt to accept them
4496 now. */
4497 if (l[0] == ',' && l[1] == 'p')
4498 {
4499 if (l[2] == 't')
4500 {
4501 if (!add_prefix (DS_PREFIX_OPCODE))
4502 return NULL;
4503 l += 3;
4504 }
4505 else if (l[2] == 'n')
4506 {
4507 if (!add_prefix (CS_PREFIX_OPCODE))
4508 return NULL;
4509 l += 3;
4510 }
4511 }
4512 }
4513 /* Any other comma loses. */
4514 if (*l == ',')
4515 {
4516 as_bad (_("invalid character %s in mnemonic"),
4517 output_invalid (*l));
4518 return NULL;
4519 }
252b5132 4520
29b0f896 4521 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 4522 supported = 0;
4523 for (t = current_templates->start; t < current_templates->end; ++t)
4524 {
c0f3af97
L		 4525 supported |= cpu_flags_match (t);
4526 if (supported == CPU_FLAGS_PERFECT_MATCH)
548d0ee6
JB		 4527 {
4528 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4529 as_warn (_("use .code16 to ensure correct addressing mode"));
3629bb00 4530
548d0ee6
JB		 4531 return l;
4532 }
29b0f896 4533 }
3629bb00 4534
548d0ee6
JB		 4535 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4536 as_bad (flag_code == CODE_64BIT
4537 ? _("`%s' is not supported in 64-bit mode")
4538 : _("`%s' is only supported in 64-bit mode"),
4539 current_templates->start->name);
4540 else
4541 as_bad (_("`%s' is not supported on `%s%s'"),
4542 current_templates->start->name,
4543 cpu_arch_name ? cpu_arch_name : default_arch,
4544 cpu_sub_arch_name ? cpu_sub_arch_name : "");
252b5132 4545
548d0ee6 4546 return NULL;
29b0f896 4547}
252b5132 4548
29b0f896 4549static char *
e3bb37b5 4550parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4551{
4552 char *token_start;
3138f287 4553
29b0f896
AM		 4554 /* 1 if operand is pending after ','. */
4555 unsigned int expecting_operand = 0;
252b5132 4556
29b0f896
AM		 4557 /* Non-zero if operand parens not balanced. */
4558 unsigned int paren_not_balanced;
4559
4560 while (*l != END_OF_INSN)
4561 {
4562 /* Skip optional white space before operand. */
4563 if (is_space_char (*l))
4564 ++l;
d02603dc 4565 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4566 {
4567 as_bad (_("invalid character %s before operand %d"),
4568 output_invalid (*l),
4569 i.operands + 1);
4570 return NULL;
4571 }
d02603dc 4572 token_start = l; /* After white space. */
29b0f896
AM		 4573 paren_not_balanced = 0;
4574 while (paren_not_balanced || *l != ',')
4575 {
4576 if (*l == END_OF_INSN)
4577 {
4578 if (paren_not_balanced)
4579 {
4580 if (!intel_syntax)
4581 as_bad (_("unbalanced parenthesis in operand %d."),
4582 i.operands + 1);
4583 else
4584 as_bad (_("unbalanced brackets in operand %d."),
4585 i.operands + 1);
4586 return NULL;
4587 }
4588 else
4589 break; /* we are done */
4590 }
d02603dc 4591 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4592 {
4593 as_bad (_("invalid character %s in operand %d"),
4594 output_invalid (*l),
4595 i.operands + 1);
4596 return NULL;
4597 }
4598 if (!intel_syntax)
4599 {
4600 if (*l == '(')
4601 ++paren_not_balanced;
4602 if (*l == ')')
4603 --paren_not_balanced;
4604 }
4605 else
4606 {
4607 if (*l == '[')
4608 ++paren_not_balanced;
4609 if (*l == ']')
4610 --paren_not_balanced;
4611 }
4612 l++;
4613 }
4614 if (l != token_start)
4615 { /* Yes, we've read in another operand. */
4616 unsigned int operand_ok;
4617 this_operand = i.operands++;
4618 if (i.operands > MAX_OPERANDS)
4619 {
4620 as_bad (_("spurious operands; (%d operands/instruction max)"),
4621 MAX_OPERANDS);
4622 return NULL;
4623 }
9d46ce34 4624 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4625 /* Now parse operand adding info to 'i' as we go along. */
4626 END_STRING_AND_SAVE (l);
4627
4628 if (intel_syntax)
4629 operand_ok =
4630 i386_intel_operand (token_start,
4631 intel_float_operand (mnemonic));
4632 else
a7619375 4633 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4634
4635 RESTORE_END_STRING (l);
4636 if (!operand_ok)
4637 return NULL;
4638 }
4639 else
4640 {
4641 if (expecting_operand)
4642 {
4643 expecting_operand_after_comma:
4644 as_bad (_("expecting operand after ','; got nothing"));
4645 return NULL;
4646 }
4647 if (*l == ',')
4648 {
4649 as_bad (_("expecting operand before ','; got nothing"));
4650 return NULL;
4651 }
4652 }
7f3f1ea2 4653
29b0f896
AM		 4654 /* Now *l must be either ',' or END_OF_INSN. */
4655 if (*l == ',')
4656 {
4657 if (*++l == END_OF_INSN)
4658 {
4659 /* Just skip it, if it's \n complain. */
4660 goto expecting_operand_after_comma;
4661 }
4662 expecting_operand = 1;
4663 }
4664 }
4665 return l;
4666}
7f3f1ea2 4667
050dfa73 4668static void
4d456e3d 4669swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4670{
4671 union i386_op temp_op;
40fb9820 4672 i386_operand_type temp_type;
050dfa73 4673 enum bfd_reloc_code_real temp_reloc;
4eed87de 4674
050dfa73
MM		 4675 temp_type = i.types[xchg2];
4676 i.types[xchg2] = i.types[xchg1];
4677 i.types[xchg1] = temp_type;
4678 temp_op = i.op[xchg2];
4679 i.op[xchg2] = i.op[xchg1];
4680 i.op[xchg1] = temp_op;
4681 temp_reloc = i.reloc[xchg2];
4682 i.reloc[xchg2] = i.reloc[xchg1];
4683 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4684
4685 if (i.mask)
4686 {
4687 if (i.mask->operand == xchg1)
4688 i.mask->operand = xchg2;
4689 else if (i.mask->operand == xchg2)
4690 i.mask->operand = xchg1;
4691 }
4692 if (i.broadcast)
4693 {
4694 if (i.broadcast->operand == xchg1)
4695 i.broadcast->operand = xchg2;
4696 else if (i.broadcast->operand == xchg2)
4697 i.broadcast->operand = xchg1;
4698 }
4699 if (i.rounding)
4700 {
4701 if (i.rounding->operand == xchg1)
4702 i.rounding->operand = xchg2;
4703 else if (i.rounding->operand == xchg2)
4704 i.rounding->operand = xchg1;
4705 }
050dfa73
MM		 4706}
4707
29b0f896 4708static void
e3bb37b5 4709swap_operands (void)
29b0f896 4710{
b7c61d9a 4711 switch (i.operands)
050dfa73 4712 {
c0f3af97 4713 case 5:
b7c61d9a 4714 case 4:
4d456e3d 4715 swap_2_operands (1, i.operands - 2);
1a0670f3 4716 /* Fall through. */
b7c61d9a
L		 4717 case 3:
4718 case 2:
4d456e3d 4719 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4720 break;
4721 default:
4722 abort ();
29b0f896 4723 }
29b0f896
AM		 4724
4725 if (i.mem_operands == 2)
4726 {
4727 const seg_entry *temp_seg;
4728 temp_seg = i.seg[0];
4729 i.seg[0] = i.seg[1];
4730 i.seg[1] = temp_seg;
4731 }
4732}
252b5132 4733
29b0f896
AM		 4734/* Try to ensure constant immediates are represented in the smallest
4735 opcode possible. */
4736static void
e3bb37b5 4737optimize_imm (void)
29b0f896
AM		 4738{
4739 char guess_suffix = 0;
4740 int op;
252b5132 4741
29b0f896
AM		 4742 if (i.suffix)
4743 guess_suffix = i.suffix;
4744 else if (i.reg_operands)
4745 {
4746 /* Figure out a suffix from the last register operand specified.
4747 We can't do this properly yet, ie. excluding InOutPortReg,
4748 but the following works for instructions with immediates.
4749 In any case, we can't set i.suffix yet. */
4750 for (op = i.operands; --op >= 0;)
dc821c5f 4751 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
7ab9ffdd 4752 {
40fb9820
L		 4753 guess_suffix = BYTE_MNEM_SUFFIX;
4754 break;
4755 }
dc821c5f 4756 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
252b5132 4757 {
40fb9820
L		 4758 guess_suffix = WORD_MNEM_SUFFIX;
4759 break;
4760 }
dc821c5f 4761 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
40fb9820
L		 4762 {
4763 guess_suffix = LONG_MNEM_SUFFIX;
4764 break;
4765 }
dc821c5f 4766 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
40fb9820
L		 4767 {
4768 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4769 break;
252b5132 4770 }
29b0f896
AM		 4771 }
4772 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4773 guess_suffix = WORD_MNEM_SUFFIX;
4774
4775 for (op = i.operands; --op >= 0;)
40fb9820 4776 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4777 {
4778 switch (i.op[op].imms->X_op)
252b5132 4779 {
29b0f896
AM		 4780 case O_constant:
4781 /* If a suffix is given, this operand may be shortened. */
4782 switch (guess_suffix)
252b5132 4783 {
29b0f896 4784 case LONG_MNEM_SUFFIX:
40fb9820
L		 4785 i.types[op].bitfield.imm32 = 1;
4786 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4787 break;
4788 case WORD_MNEM_SUFFIX:
40fb9820
L		 4789 i.types[op].bitfield.imm16 = 1;
4790 i.types[op].bitfield.imm32 = 1;
4791 i.types[op].bitfield.imm32s = 1;
4792 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4793 break;
4794 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4795 i.types[op].bitfield.imm8 = 1;
4796 i.types[op].bitfield.imm8s = 1;
4797 i.types[op].bitfield.imm16 = 1;
4798 i.types[op].bitfield.imm32 = 1;
4799 i.types[op].bitfield.imm32s = 1;
4800 i.types[op].bitfield.imm64 = 1;
29b0f896 4801 break;
252b5132 4802 }
252b5132 4803
29b0f896
AM		 4804 /* If this operand is at most 16 bits, convert it
4805 to a signed 16 bit number before trying to see
4806 whether it will fit in an even smaller size.
4807 This allows a 16-bit operand such as $0xffe0 to
4808 be recognised as within Imm8S range. */
40fb9820 4809 if ((i.types[op].bitfield.imm16)
29b0f896 4810 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4811 {
29b0f896
AM		 4812 i.op[op].imms->X_add_number =
4813 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4814 }
a28def75
L		 4815#ifdef BFD64
4816 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4817 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4818 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4819 == 0))
4820 {
4821 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4822 ^ ((offsetT) 1 << 31))
4823 - ((offsetT) 1 << 31));
4824 }
a28def75 4825#endif
40fb9820 4826 i.types[op]
c6fb90c8
L		 4827 = operand_type_or (i.types[op],
4828 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4829
29b0f896
AM		 4830 /* We must avoid matching of Imm32 templates when 64bit
4831 only immediate is available. */
4832 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4833 i.types[op].bitfield.imm32 = 0;
29b0f896 4834 break;
252b5132 4835
29b0f896
AM		 4836 case O_absent:
4837 case O_register:
4838 abort ();
4839
4840 /* Symbols and expressions. */
4841 default:
9cd96992
JB		 4842 /* Convert symbolic operand to proper sizes for matching, but don't
4843 prevent matching a set of insns that only supports sizes other
4844 than those matching the insn suffix. */
4845 {
40fb9820 4846 i386_operand_type mask, allowed;
d3ce72d0 4847 const insn_template *t;
9cd96992 4848
0dfbf9d7
L		 4849 operand_type_set (&mask, 0);
4850 operand_type_set (&allowed, 0);
40fb9820 4851
4eed87de
AM		 4852 for (t = current_templates->start;
4853 t < current_templates->end;
4854 ++t)
c6fb90c8
L		 4855 allowed = operand_type_or (allowed,
4856 t->operand_types[op]);
9cd96992
JB		 4857 switch (guess_suffix)
4858 {
4859 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4860 mask.bitfield.imm64 = 1;
4861 mask.bitfield.imm32s = 1;
9cd96992
JB		 4862 break;
4863 case LONG_MNEM_SUFFIX:
40fb9820 4864 mask.bitfield.imm32 = 1;
9cd96992
JB		 4865 break;
4866 case WORD_MNEM_SUFFIX:
40fb9820 4867 mask.bitfield.imm16 = 1;
9cd96992
JB		 4868 break;
4869 case BYTE_MNEM_SUFFIX:
40fb9820 4870 mask.bitfield.imm8 = 1;
9cd96992
JB		 4871 break;
4872 default:
9cd96992
JB		 4873 break;
4874 }
c6fb90c8 4875 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4876 if (!operand_type_all_zero (&allowed))
c6fb90c8 4877 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4878 }
29b0f896 4879 break;
252b5132 4880 }
29b0f896
AM		 4881 }
4882}
47926f60 4883
29b0f896
AM		 4884/* Try to use the smallest displacement type too. */
4885static void
e3bb37b5 4886optimize_disp (void)
29b0f896
AM		 4887{
4888 int op;
3e73aa7c 4889
29b0f896 4890 for (op = i.operands; --op >= 0;)
40fb9820 4891 if (operand_type_check (i.types[op], disp))
252b5132 4892 {
b300c311 4893 if (i.op[op].disps->X_op == O_constant)
252b5132 4894 {
91d6fa6a 4895 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4896
40fb9820 4897 if (i.types[op].bitfield.disp16
91d6fa6a 4898 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4899 {
4900 /* If this operand is at most 16 bits, convert
4901 to a signed 16 bit number and don't use 64bit
4902 displacement. */
91d6fa6a 4903 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4904 i.types[op].bitfield.disp64 = 0;
b300c311 4905 }
a28def75
L		 4906#ifdef BFD64
4907 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4908 if (i.types[op].bitfield.disp32
91d6fa6a 4909 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4910 {
4911 /* If this operand is at most 32 bits, convert
4912 to a signed 32 bit number and don't use 64bit
4913 displacement. */
91d6fa6a
NC		 4914 op_disp &= (((offsetT) 2 << 31) - 1);
4915 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4916 i.types[op].bitfield.disp64 = 0;
b300c311 4917 }
a28def75 4918#endif
91d6fa6a 4919 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4920 {
40fb9820
L		 4921 i.types[op].bitfield.disp8 = 0;
4922 i.types[op].bitfield.disp16 = 0;
4923 i.types[op].bitfield.disp32 = 0;
4924 i.types[op].bitfield.disp32s = 0;
4925 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4926 i.op[op].disps = 0;
4927 i.disp_operands--;
4928 }
4929 else if (flag_code == CODE_64BIT)
4930 {
91d6fa6a 4931 if (fits_in_signed_long (op_disp))
28a9d8f5 4932 {
40fb9820
L		 4933 i.types[op].bitfield.disp64 = 0;
4934 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4935 }
0e1147d9 4936 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4937 && fits_in_unsigned_long (op_disp))
40fb9820 4938 i.types[op].bitfield.disp32 = 1;
b300c311 4939 }
40fb9820
L		 4940 if ((i.types[op].bitfield.disp32
4941 || i.types[op].bitfield.disp32s
4942 || i.types[op].bitfield.disp16)
b5014f7a 4943 && fits_in_disp8 (op_disp))
40fb9820 4944 i.types[op].bitfield.disp8 = 1;
252b5132 4945 }
67a4f2b7
AO		 4946 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4947 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4948 {
4949 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4950 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4951 i.types[op].bitfield.disp8 = 0;
4952 i.types[op].bitfield.disp16 = 0;
4953 i.types[op].bitfield.disp32 = 0;
4954 i.types[op].bitfield.disp32s = 0;
4955 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4956 }
4957 else
b300c311 4958 /* We only support 64bit displacement on constants. */
40fb9820 4959 i.types[op].bitfield.disp64 = 0;
252b5132 4960 }
29b0f896
AM		 4961}
4962
6c30d220
L		 4963/* Check if operands are valid for the instruction. */
4964
4965static int
4966check_VecOperands (const insn_template *t)
4967{
43234a1e 4968 unsigned int op;
e2195274
JB		 4969 i386_cpu_flags cpu;
4970 static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
4971
4972 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
4973 any one operand are implicity requiring AVX512VL support if the actual
4974 operand size is YMMword or XMMword. Since this function runs after
4975 template matching, there's no need to check for YMMword/XMMword in
4976 the template. */
4977 cpu = cpu_flags_and (t->cpu_flags, avx512);
4978 if (!cpu_flags_all_zero (&cpu)
4979 && !t->cpu_flags.bitfield.cpuavx512vl
4980 && !cpu_arch_flags.bitfield.cpuavx512vl)
4981 {
4982 for (op = 0; op < t->operands; ++op)
4983 {
4984 if (t->operand_types[op].bitfield.zmmword
4985 && (i.types[op].bitfield.ymmword
4986 || i.types[op].bitfield.xmmword))
4987 {
4988 i.error = unsupported;
4989 return 1;
4990 }
4991 }
4992 }
43234a1e 4993
6c30d220
L		 4994 /* Without VSIB byte, we can't have a vector register for index. */
4995 if (!t->opcode_modifier.vecsib
4996 && i.index_reg
1b54b8d7
JB		 4997 && (i.index_reg->reg_type.bitfield.xmmword
4998 || i.index_reg->reg_type.bitfield.ymmword
4999 || i.index_reg->reg_type.bitfield.zmmword))
6c30d220
L		 5000 {
5001 i.error = unsupported_vector_index_register;
5002 return 1;
5003 }
5004
ad8ecc81
MZ		 5005 /* Check if default mask is allowed. */
5006 if (t->opcode_modifier.nodefmask
5007 && (!i.mask || i.mask->mask->reg_num == 0))
5008 {
5009 i.error = no_default_mask;
5010 return 1;
5011 }
5012
7bab8ab5
JB		 5013 /* For VSIB byte, we need a vector register for index, and all vector
5014 registers must be distinct. */
5015 if (t->opcode_modifier.vecsib)
5016 {
5017 if (!i.index_reg
6c30d220 5018 || !((t->opcode_modifier.vecsib == VecSIB128
1b54b8d7 5019 && i.index_reg->reg_type.bitfield.xmmword)
6c30d220 5020 || (t->opcode_modifier.vecsib == VecSIB256
1b54b8d7 5021 && i.index_reg->reg_type.bitfield.ymmword)
43234a1e 5022 || (t->opcode_modifier.vecsib == VecSIB512
1b54b8d7 5023 && i.index_reg->reg_type.bitfield.zmmword)))
7bab8ab5
JB		 5024 {
5025 i.error = invalid_vsib_address;
5026 return 1;
5027 }
5028
43234a1e
L		 5029 gas_assert (i.reg_operands == 2 || i.mask);
5030 if (i.reg_operands == 2 && !i.mask)
5031 {
1b54b8d7
JB		 5032 gas_assert (i.types[0].bitfield.regsimd);
5033 gas_assert (i.types[0].bitfield.xmmword
5034 || i.types[0].bitfield.ymmword);
5035 gas_assert (i.types[2].bitfield.regsimd);
5036 gas_assert (i.types[2].bitfield.xmmword
5037 || i.types[2].bitfield.ymmword);
43234a1e
L		 5038 if (operand_check == check_none)
5039 return 0;
5040 if (register_number (i.op[0].regs)
5041 != register_number (i.index_reg)
5042 && register_number (i.op[2].regs)
5043 != register_number (i.index_reg)
5044 && register_number (i.op[0].regs)
5045 != register_number (i.op[2].regs))
5046 return 0;
5047 if (operand_check == check_error)
5048 {
5049 i.error = invalid_vector_register_set;
5050 return 1;
5051 }
5052 as_warn (_("mask, index, and destination registers should be distinct"));
5053 }
8444f82a
MZ		 5054 else if (i.reg_operands == 1 && i.mask)
5055 {
1b54b8d7
JB		 5056 if (i.types[1].bitfield.regsimd
5057 && (i.types[1].bitfield.xmmword
5058 || i.types[1].bitfield.ymmword
5059 || i.types[1].bitfield.zmmword)
8444f82a
MZ		 5060 && (register_number (i.op[1].regs)
5061 == register_number (i.index_reg)))
5062 {
5063 if (operand_check == check_error)
5064 {
5065 i.error = invalid_vector_register_set;
5066 return 1;
5067 }
5068 if (operand_check != check_none)
5069 as_warn (_("index and destination registers should be distinct"));
5070 }
5071 }
43234a1e 5072 }
7bab8ab5 5073
43234a1e
L		 5074 /* Check if broadcast is supported by the instruction and is applied
5075 to the memory operand. */
5076 if (i.broadcast)
5077 {
8e6e0792 5078 i386_operand_type type, overlap;
43234a1e
L		 5079
5080 /* Check if specified broadcast is supported in this instruction,
c39e5b26 5081 and it's applied to memory operand of DWORD or QWORD type. */
32546502 5082 op = i.broadcast->operand;
8e6e0792 5083 if (!t->opcode_modifier.broadcast
32546502 5084 || !i.types[op].bitfield.mem
c39e5b26
JB		 5085 || (!i.types[op].bitfield.unspecified
5086 && (t->operand_types[op].bitfield.dword
5087 ? !i.types[op].bitfield.dword
5088 : !i.types[op].bitfield.qword)))
43234a1e
L		 5089 {
5090 bad_broadcast:
5091 i.error = unsupported_broadcast;
5092 return 1;
5093 }
8e6e0792
JB		 5094
5095 operand_type_set (&type, 0);
c39e5b26 5096 switch ((t->operand_types[op].bitfield.dword ? 4 : 8) * i.broadcast->type)
8e6e0792
JB		 5097 {
5098 case 8:
5099 type.bitfield.qword = 1;
5100 break;
5101 case 16:
5102 type.bitfield.xmmword = 1;
5103 break;
5104 case 32:
5105 type.bitfield.ymmword = 1;
5106 break;
5107 case 64:
5108 type.bitfield.zmmword = 1;
5109 break;
5110 default:
5111 goto bad_broadcast;
5112 }
5113
5114 overlap = operand_type_and (type, t->operand_types[op]);
5115 if (operand_type_all_zero (&overlap))
5116 goto bad_broadcast;
5117
5118 if (t->opcode_modifier.checkregsize)
5119 {
5120 unsigned int j;
5121
e2195274 5122 type.bitfield.baseindex = 1;
8e6e0792
JB		 5123 for (j = 0; j < i.operands; ++j)
5124 {
5125 if (j != op
5126 && !operand_type_register_match(i.types[j],
5127 t->operand_types[j],
5128 type,
5129 t->operand_types[op]))
5130 goto bad_broadcast;
5131 }
5132 }
43234a1e
L		 5133 }
5134 /* If broadcast is supported in this instruction, we need to check if
5135 operand of one-element size isn't specified without broadcast. */
5136 else if (t->opcode_modifier.broadcast && i.mem_operands)
5137 {
5138 /* Find memory operand. */
5139 for (op = 0; op < i.operands; op++)
5140 if (operand_type_check (i.types[op], anymem))
5141 break;
5142 gas_assert (op < i.operands);
5143 /* Check size of the memory operand. */
c39e5b26
JB		 5144 if (t->operand_types[op].bitfield.dword
5145 ? i.types[op].bitfield.dword
5146 : i.types[op].bitfield.qword)
43234a1e
L		 5147 {
5148 i.error = broadcast_needed;
5149 return 1;
5150 }
5151 }
c39e5b26
JB		 5152 else
5153 op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
43234a1e
L		 5154
5155 /* Check if requested masking is supported. */
5156 if (i.mask
5157 && (!t->opcode_modifier.masking
5158 || (i.mask->zeroing
5159 && t->opcode_modifier.masking == MERGING_MASKING)))
5160 {
5161 i.error = unsupported_masking;
5162 return 1;
5163 }
5164
5165 /* Check if masking is applied to dest operand. */
5166 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5167 {
5168 i.error = mask_not_on_destination;
5169 return 1;
5170 }
5171
43234a1e
L		 5172 /* Check RC/SAE. */
5173 if (i.rounding)
5174 {
5175 if ((i.rounding->type != saeonly
5176 && !t->opcode_modifier.staticrounding)
5177 || (i.rounding->type == saeonly
5178 && (t->opcode_modifier.staticrounding
5179 || !t->opcode_modifier.sae)))
5180 {
5181 i.error = unsupported_rc_sae;
5182 return 1;
5183 }
5184 /* If the instruction has several immediate operands and one of
5185 them is rounding, the rounding operand should be the last
5186 immediate operand. */
5187 if (i.imm_operands > 1
5188 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 5189 {
43234a1e 5190 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 5191 return 1;
5192 }
6c30d220
L		 5193 }
5194
43234a1e 5195 /* Check vector Disp8 operand. */
b5014f7a
JB		 5196 if (t->opcode_modifier.disp8memshift
5197 && i.disp_encoding != disp_encoding_32bit)
43234a1e
L		 5198 {
5199 if (i.broadcast)
c39e5b26 5200 i.memshift = t->operand_types[op].bitfield.dword ? 2 : 3;
43234a1e
L		 5201 else
5202 i.memshift = t->opcode_modifier.disp8memshift;
5203
5204 for (op = 0; op < i.operands; op++)
5205 if (operand_type_check (i.types[op], disp)
5206 && i.op[op].disps->X_op == O_constant)
5207 {
b5014f7a 5208 if (fits_in_disp8 (i.op[op].disps->X_add_number))
43234a1e 5209 {
b5014f7a
JB		 5210 i.types[op].bitfield.disp8 = 1;
5211 return 0;
43234a1e 5212 }
b5014f7a 5213 i.types[op].bitfield.disp8 = 0;
43234a1e
L		 5214 }
5215 }
b5014f7a
JB		 5216
5217 i.memshift = 0;
43234a1e 5218
6c30d220
L		 5219 return 0;
5220}
5221
43f3e2ee 5222/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 5223 operand types. */
5224
5225static int
5226VEX_check_operands (const insn_template *t)
5227{
86fa6981 5228 if (i.vec_encoding == vex_encoding_evex)
43234a1e 5229 {
86fa6981 5230 /* This instruction must be encoded with EVEX prefix. */
e771e7c9 5231 if (!is_evex_encoding (t))
86fa6981
L		 5232 {
5233 i.error = unsupported;
5234 return 1;
5235 }
5236 return 0;
43234a1e
L		 5237 }
5238
a683cc34 5239 if (!t->opcode_modifier.vex)
86fa6981
L		 5240 {
5241 /* This instruction template doesn't have VEX prefix. */
5242 if (i.vec_encoding != vex_encoding_default)
5243 {
5244 i.error = unsupported;
5245 return 1;
5246 }
5247 return 0;
5248 }
a683cc34
SP		 5249
5250 /* Only check VEX_Imm4, which must be the first operand. */
5251 if (t->operand_types[0].bitfield.vec_imm4)
5252 {
5253 if (i.op[0].imms->X_op != O_constant
5254 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 5255 {
a65babc9 5256 i.error = bad_imm4;
891edac4
L		 5257 return 1;
5258 }
a683cc34
SP		 5259
5260 /* Turn off Imm8 so that update_imm won't complain. */
5261 i.types[0] = vec_imm4;
5262 }
5263
5264 return 0;
5265}
5266
d3ce72d0 5267static const insn_template *
83b16ac6 5268match_template (char mnem_suffix)
29b0f896
AM		 5269{
5270 /* Points to template once we've found it. */
d3ce72d0 5271 const insn_template *t;
40fb9820 5272 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 5273 i386_operand_type overlap4;
29b0f896 5274 unsigned int found_reverse_match;
83b16ac6 5275 i386_opcode_modifier suffix_check, mnemsuf_check;
40fb9820 5276 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 5277 int addr_prefix_disp;
a5c311ca 5278 unsigned int j;
3629bb00 5279 unsigned int found_cpu_match;
45664ddb 5280 unsigned int check_register;
5614d22c 5281 enum i386_error specific_error = 0;
29b0f896 5282
c0f3af97
L		 5283#if MAX_OPERANDS != 5
5284# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 5285#endif
5286
29b0f896 5287 found_reverse_match = 0;
539e75ad 5288 addr_prefix_disp = -1;
40fb9820
L		 5289
5290 memset (&suffix_check, 0, sizeof (suffix_check));
e2195274
JB		 5291 if (intel_syntax && i.broadcast)
5292 /* nothing */;
5293 else if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5294 suffix_check.no_bsuf = 1;
5295 else if (i.suffix == WORD_MNEM_SUFFIX)
5296 suffix_check.no_wsuf = 1;
5297 else if (i.suffix == SHORT_MNEM_SUFFIX)
5298 suffix_check.no_ssuf = 1;
5299 else if (i.suffix == LONG_MNEM_SUFFIX)
5300 suffix_check.no_lsuf = 1;
5301 else if (i.suffix == QWORD_MNEM_SUFFIX)
5302 suffix_check.no_qsuf = 1;
5303 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 5304 suffix_check.no_ldsuf = 1;
29b0f896 5305
83b16ac6
JB		 5306 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5307 if (intel_syntax)
5308 {
5309 switch (mnem_suffix)
5310 {
5311 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5312 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5313 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5314 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5315 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5316 }
5317 }
5318
01559ecc
L		 5319 /* Must have right number of operands. */
5320 i.error = number_of_operands_mismatch;
5321
45aa61fe 5322 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 5323 {
539e75ad
L		 5324 addr_prefix_disp = -1;
5325
29b0f896
AM		 5326 if (i.operands != t->operands)
5327 continue;
5328
50aecf8c 5329 /* Check processor support. */
a65babc9 5330 i.error = unsupported;
c0f3af97
L		 5331 found_cpu_match = (cpu_flags_match (t)
5332 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 5333 if (!found_cpu_match)
5334 continue;
5335
e1d4d893 5336 /* Check AT&T mnemonic. */
a65babc9 5337 i.error = unsupported_with_intel_mnemonic;
e1d4d893 5338 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 5339 continue;
5340
e92bae62 5341 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
a65babc9 5342 i.error = unsupported_syntax;
5c07affc 5343 if ((intel_syntax && t->opcode_modifier.attsyntax)
e92bae62
L		 5344 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5345 || (intel64 && t->opcode_modifier.amd64)
5346 || (!intel64 && t->opcode_modifier.intel64))
1efbbeb4
L		 5347 continue;
5348
20592a94 5349 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 5350 i.error = invalid_instruction_suffix;
567e4e96
L		 5351 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5352 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5353 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5354 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5355 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5356 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5357 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896 5358 continue;
83b16ac6
JB		 5359 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5360 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5361 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5362 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5363 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5364 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5365 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5366 continue;
29b0f896 5367
5c07affc 5368 if (!operand_size_match (t))
7d5e4556 5369 continue;
539e75ad 5370
5c07affc
L		 5371 for (j = 0; j < MAX_OPERANDS; j++)
5372 operand_types[j] = t->operand_types[j];
5373
45aa61fe
AM		 5374 /* In general, don't allow 64-bit operands in 32-bit mode. */
5375 if (i.suffix == QWORD_MNEM_SUFFIX
5376 && flag_code != CODE_64BIT
5377 && (intel_syntax
40fb9820 5378 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 5379 && !intel_float_operand (t->name))
5380 : intel_float_operand (t->name) != 2)
40fb9820 5381 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5382 && !operand_types[0].bitfield.regsimd)
40fb9820 5383 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5384 && !operand_types[t->operands > 1].bitfield.regsimd))
45aa61fe
AM		 5385 && (t->base_opcode != 0x0fc7
5386 || t->extension_opcode != 1 /* cmpxchg8b */))
5387 continue;
5388
192dc9c6
JB		 5389 /* In general, don't allow 32-bit operands on pre-386. */
5390 else if (i.suffix == LONG_MNEM_SUFFIX
5391 && !cpu_arch_flags.bitfield.cpui386
5392 && (intel_syntax
5393 ? (!t->opcode_modifier.ignoresize
5394 && !intel_float_operand (t->name))
5395 : intel_float_operand (t->name) != 2)
5396 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5397 && !operand_types[0].bitfield.regsimd)
192dc9c6 5398 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5399 && !operand_types[t->operands > 1].bitfield.regsimd)))
192dc9c6
JB		 5400 continue;
5401
29b0f896 5402 /* Do not verify operands when there are none. */
50aecf8c 5403 else
29b0f896 5404 {
c6fb90c8 5405 if (!t->operands)
2dbab7d5
L		 5406 /* We've found a match; break out of loop. */
5407 break;
29b0f896 5408 }
252b5132 5409
539e75ad
L		 5410 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5411 into Disp32/Disp16/Disp32 operand. */
5412 if (i.prefix[ADDR_PREFIX] != 0)
5413 {
40fb9820 5414 /* There should be only one Disp operand. */
539e75ad
L		 5415 switch (flag_code)
5416 {
5417 case CODE_16BIT:
40fb9820
L		 5418 for (j = 0; j < MAX_OPERANDS; j++)
5419 {
5420 if (operand_types[j].bitfield.disp16)
5421 {
5422 addr_prefix_disp = j;
5423 operand_types[j].bitfield.disp32 = 1;
5424 operand_types[j].bitfield.disp16 = 0;
5425 break;
5426 }
5427 }
539e75ad
L		 5428 break;
5429 case CODE_32BIT:
40fb9820
L		 5430 for (j = 0; j < MAX_OPERANDS; j++)
5431 {
5432 if (operand_types[j].bitfield.disp32)
5433 {
5434 addr_prefix_disp = j;
5435 operand_types[j].bitfield.disp32 = 0;
5436 operand_types[j].bitfield.disp16 = 1;
5437 break;
5438 }
5439 }
539e75ad
L		 5440 break;
5441 case CODE_64BIT:
40fb9820
L		 5442 for (j = 0; j < MAX_OPERANDS; j++)
5443 {
5444 if (operand_types[j].bitfield.disp64)
5445 {
5446 addr_prefix_disp = j;
5447 operand_types[j].bitfield.disp64 = 0;
5448 operand_types[j].bitfield.disp32 = 1;
5449 break;
5450 }
5451 }
539e75ad
L		 5452 break;
5453 }
539e75ad
L		 5454 }
5455
02a86693
L		 5456 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5457 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5458 continue;
5459
56ffb741 5460 /* We check register size if needed. */
e2195274
JB		 5461 if (t->opcode_modifier.checkregsize)
5462 {
5463 check_register = (1 << t->operands) - 1;
5464 if (i.broadcast)
5465 check_register &= ~(1 << i.broadcast->operand);
5466 }
5467 else
5468 check_register = 0;
5469
c6fb90c8 5470 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 5471 switch (t->operands)
5472 {
5473 case 1:
40fb9820 5474 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 5475 continue;
5476 break;
5477 case 2:
33eaf5de 5478 /* xchg %eax, %eax is a special case. It is an alias for nop
8b38ad71
L		 5479 only in 32bit mode and we can use opcode 0x90. In 64bit
5480 mode, we can't use 0x90 for xchg %eax, %eax since it should
5481 zero-extend %eax to %rax. */
5482 if (flag_code == CODE_64BIT
5483 && t->base_opcode == 0x90
0dfbf9d7
L		 5484 && operand_type_equal (&i.types [0], &acc32)
5485 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 5486 continue;
1212781b
JB		 5487 /* xrelease mov %eax, <disp> is another special case. It must not
5488 match the accumulator-only encoding of mov. */
5489 if (flag_code != CODE_64BIT
5490 && i.hle_prefix
5491 && t->base_opcode == 0xa0
5492 && i.types[0].bitfield.acc
5493 && operand_type_check (i.types[1], anymem))
5494 continue;
86fa6981
L		 5495 /* If we want store form, we reverse direction of operands. */
5496 if (i.dir_encoding == dir_encoding_store
5497 && t->opcode_modifier.d)
5498 goto check_reverse;
1a0670f3 5499 /* Fall through. */
b6169b20 5500
29b0f896 5501 case 3:
86fa6981
L		 5502 /* If we want store form, we skip the current load. */
5503 if (i.dir_encoding == dir_encoding_store
5504 && i.mem_operands == 0
5505 && t->opcode_modifier.load)
fa99fab2 5506 continue;
1a0670f3 5507 /* Fall through. */
f48ff2ae 5508 case 4:
c0f3af97 5509 case 5:
c6fb90c8 5510 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 5511 if (!operand_type_match (overlap0, i.types[0])
5512 || !operand_type_match (overlap1, i.types[1])
e2195274 5513 || ((check_register & 3) == 3
dc821c5f 5514 && !operand_type_register_match (i.types[0],
40fb9820 5515 operand_types[0],
dc821c5f 5516 i.types[1],
40fb9820 5517 operand_types[1])))
29b0f896
AM		 5518 {
5519 /* Check if other direction is valid ... */
38e314eb 5520 if (!t->opcode_modifier.d)
29b0f896
AM		 5521 continue;
5522
b6169b20 5523check_reverse:
29b0f896 5524 /* Try reversing direction of operands. */
c6fb90c8
L		 5525 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5526 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 5527 if (!operand_type_match (overlap0, i.types[0])
5528 || !operand_type_match (overlap1, i.types[1])
45664ddb 5529 || (check_register
dc821c5f 5530 && !operand_type_register_match (i.types[0],
45664ddb 5531 operand_types[1],
45664ddb
L		 5532 i.types[1],
5533 operand_types[0])))
29b0f896
AM		 5534 {
5535 /* Does not match either direction. */
5536 continue;
5537 }
38e314eb 5538 /* found_reverse_match holds which of D or FloatR
29b0f896 5539 we've found. */
38e314eb
JB		 5540 if (!t->opcode_modifier.d)
5541 found_reverse_match = 0;
5542 else if (operand_types[0].bitfield.tbyte)
8a2ed489
L		 5543 found_reverse_match = Opcode_FloatD;
5544 else
38e314eb 5545 found_reverse_match = Opcode_D;
40fb9820 5546 if (t->opcode_modifier.floatr)
8a2ed489 5547 found_reverse_match |= Opcode_FloatR;
29b0f896 5548 }
f48ff2ae 5549 else
29b0f896 5550 {
f48ff2ae 5551 /* Found a forward 2 operand match here. */
d1cbb4db
L		 5552 switch (t->operands)
5553 {
c0f3af97
L		 5554 case 5:
5555 overlap4 = operand_type_and (i.types[4],
5556 operand_types[4]);
1a0670f3 5557 /* Fall through. */
d1cbb4db 5558 case 4:
c6fb90c8
L		 5559 overlap3 = operand_type_and (i.types[3],
5560 operand_types[3]);
1a0670f3 5561 /* Fall through. */
d1cbb4db 5562 case 3:
c6fb90c8
L		 5563 overlap2 = operand_type_and (i.types[2],
5564 operand_types[2]);
d1cbb4db
L		 5565 break;
5566 }
29b0f896 5567
f48ff2ae
L		 5568 switch (t->operands)
5569 {
c0f3af97
L		 5570 case 5:
5571 if (!operand_type_match (overlap4, i.types[4])
dc821c5f 5572 || !operand_type_register_match (i.types[3],
c0f3af97 5573 operand_types[3],
c0f3af97
L		 5574 i.types[4],
5575 operand_types[4]))
5576 continue;
1a0670f3 5577 /* Fall through. */
f48ff2ae 5578 case 4:
40fb9820 5579 if (!operand_type_match (overlap3, i.types[3])
e2195274
JB		 5580 || ((check_register & 0xa) == 0xa
5581 && !operand_type_register_match (i.types[1],
f7768225
JB		 5582 operand_types[1],
5583 i.types[3],
e2195274
JB		 5584 operand_types[3]))
5585 || ((check_register & 0xc) == 0xc
5586 && !operand_type_register_match (i.types[2],
5587 operand_types[2],
5588 i.types[3],
5589 operand_types[3])))
f48ff2ae 5590 continue;
1a0670f3 5591 /* Fall through. */
f48ff2ae
L		 5592 case 3:
5593 /* Here we make use of the fact that there are no
23e42951 5594 reverse match 3 operand instructions. */
40fb9820 5595 if (!operand_type_match (overlap2, i.types[2])
e2195274
JB		 5596 || ((check_register & 5) == 5
5597 && !operand_type_register_match (i.types[0],
23e42951
JB		 5598 operand_types[0],
5599 i.types[2],
e2195274
JB		 5600 operand_types[2]))
5601 || ((check_register & 6) == 6
5602 && !operand_type_register_match (i.types[1],
5603 operand_types[1],
5604 i.types[2],
5605 operand_types[2])))
f48ff2ae
L		 5606 continue;
5607 break;
5608 }
29b0f896 5609 }
f48ff2ae 5610 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5611 slip through to break. */
5612 }
3629bb00 5613 if (!found_cpu_match)
29b0f896
AM		 5614 {
5615 found_reverse_match = 0;
5616 continue;
5617 }
c0f3af97 5618
5614d22c
JB		 5619 /* Check if vector and VEX operands are valid. */
5620 if (check_VecOperands (t) || VEX_check_operands (t))
5621 {
5622 specific_error = i.error;
5623 continue;
5624 }
a683cc34 5625
29b0f896
AM		 5626 /* We've found a match; break out of loop. */
5627 break;
5628 }
5629
5630 if (t == current_templates->end)
5631 {
5632 /* We found no match. */
a65babc9 5633 const char *err_msg;
5614d22c 5634 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5635 {
5636 default:
5637 abort ();
86e026a4 5638 case operand_size_mismatch:
a65babc9
L		 5639 err_msg = _("operand size mismatch");
5640 break;
5641 case operand_type_mismatch:
5642 err_msg = _("operand type mismatch");
5643 break;
5644 case register_type_mismatch:
5645 err_msg = _("register type mismatch");
5646 break;
5647 case number_of_operands_mismatch:
5648 err_msg = _("number of operands mismatch");
5649 break;
5650 case invalid_instruction_suffix:
5651 err_msg = _("invalid instruction suffix");
5652 break;
5653 case bad_imm4:
4a2608e3 5654 err_msg = _("constant doesn't fit in 4 bits");
a65babc9 5655 break;
a65babc9
L		 5656 case unsupported_with_intel_mnemonic:
5657 err_msg = _("unsupported with Intel mnemonic");
5658 break;
5659 case unsupported_syntax:
5660 err_msg = _("unsupported syntax");
5661 break;
5662 case unsupported:
35262a23 5663 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5664 current_templates->start->name);
5665 return NULL;
6c30d220
L		 5666 case invalid_vsib_address:
5667 err_msg = _("invalid VSIB address");
5668 break;
7bab8ab5
JB		 5669 case invalid_vector_register_set:
5670 err_msg = _("mask, index, and destination registers must be distinct");
5671 break;
6c30d220
L		 5672 case unsupported_vector_index_register:
5673 err_msg = _("unsupported vector index register");
5674 break;
43234a1e
L		 5675 case unsupported_broadcast:
5676 err_msg = _("unsupported broadcast");
5677 break;
5678 case broadcast_not_on_src_operand:
5679 err_msg = _("broadcast not on source memory operand");
5680 break;
5681 case broadcast_needed:
5682 err_msg = _("broadcast is needed for operand of such type");
5683 break;
5684 case unsupported_masking:
5685 err_msg = _("unsupported masking");
5686 break;
5687 case mask_not_on_destination:
5688 err_msg = _("mask not on destination operand");
5689 break;
5690 case no_default_mask:
5691 err_msg = _("default mask isn't allowed");
5692 break;
5693 case unsupported_rc_sae:
5694 err_msg = _("unsupported static rounding/sae");
5695 break;
5696 case rc_sae_operand_not_last_imm:
5697 if (intel_syntax)
5698 err_msg = _("RC/SAE operand must precede immediate operands");
5699 else
5700 err_msg = _("RC/SAE operand must follow immediate operands");
5701 break;
5702 case invalid_register_operand:
5703 err_msg = _("invalid register operand");
5704 break;
a65babc9
L		 5705 }
5706 as_bad (_("%s for `%s'"), err_msg,
891edac4 5707 current_templates->start->name);
fa99fab2 5708 return NULL;
29b0f896 5709 }
252b5132 5710
29b0f896
AM		 5711 if (!quiet_warnings)
5712 {
5713 if (!intel_syntax
40fb9820
L		 5714 && (i.types[0].bitfield.jumpabsolute
5715 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5716 {
5717 as_warn (_("indirect %s without `*'"), t->name);
5718 }
5719
40fb9820
L		 5720 if (t->opcode_modifier.isprefix
5721 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5722 {
5723 /* Warn them that a data or address size prefix doesn't
5724 affect assembly of the next line of code. */
5725 as_warn (_("stand-alone `%s' prefix"), t->name);
5726 }
5727 }
5728
5729 /* Copy the template we found. */
5730 i.tm = *t;
539e75ad
L		 5731
5732 if (addr_prefix_disp != -1)
5733 i.tm.operand_types[addr_prefix_disp]
5734 = operand_types[addr_prefix_disp];
5735
29b0f896
AM		 5736 if (found_reverse_match)
5737 {
5738 /* If we found a reverse match we must alter the opcode
5739 direction bit. found_reverse_match holds bits to change
5740 (different for int & float insns). */
5741
5742 i.tm.base_opcode ^= found_reverse_match;
5743
539e75ad
L		 5744 i.tm.operand_types[0] = operand_types[1];
5745 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5746 }
5747
fa99fab2 5748 return t;
29b0f896
AM		 5749}
5750
5751static int
e3bb37b5 5752check_string (void)
29b0f896 5753{
40fb9820
L		 5754 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5755 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5756 {
5757 if (i.seg[0] != NULL && i.seg[0] != &es)
5758 {
a87af027 5759 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5760 i.tm.name,
a87af027
JB		 5761 mem_op + 1,
5762 register_prefix);
29b0f896
AM		 5763 return 0;
5764 }
5765 /* There's only ever one segment override allowed per instruction.
5766 This instruction possibly has a legal segment override on the
5767 second operand, so copy the segment to where non-string
5768 instructions store it, allowing common code. */
5769 i.seg[0] = i.seg[1];
5770 }
40fb9820 5771 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5772 {
5773 if (i.seg[1] != NULL && i.seg[1] != &es)
5774 {
a87af027 5775 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5776 i.tm.name,
a87af027
JB		 5777 mem_op + 2,
5778 register_prefix);
29b0f896
AM		 5779 return 0;
5780 }
5781 }
5782 return 1;
5783}
5784
5785static int
543613e9 5786process_suffix (void)
29b0f896
AM		 5787{
5788 /* If matched instruction specifies an explicit instruction mnemonic
5789 suffix, use it. */
40fb9820
L		 5790 if (i.tm.opcode_modifier.size16)
5791 i.suffix = WORD_MNEM_SUFFIX;
5792 else if (i.tm.opcode_modifier.size32)
5793 i.suffix = LONG_MNEM_SUFFIX;
5794 else if (i.tm.opcode_modifier.size64)
5795 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5796 else if (i.reg_operands)
5797 {
5798 /* If there's no instruction mnemonic suffix we try to invent one
5799 based on register operands. */
5800 if (!i.suffix)
5801 {
5802 /* We take i.suffix from the last register operand specified,
5803 Destination register type is more significant than source
381d071f
L		 5804 register type. crc32 in SSE4.2 prefers source register
5805 type. */
5806 if (i.tm.base_opcode == 0xf20f38f1)
5807 {
dc821c5f 5808 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
40fb9820 5809 i.suffix = WORD_MNEM_SUFFIX;
dc821c5f 5810 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
40fb9820 5811 i.suffix = LONG_MNEM_SUFFIX;
dc821c5f 5812 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
40fb9820 5813 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5814 }
9344ff29 5815 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5816 {
dc821c5f 5817 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
20592a94
L		 5818 i.suffix = BYTE_MNEM_SUFFIX;
5819 }
381d071f
L		 5820
5821 if (!i.suffix)
5822 {
5823 int op;
5824
20592a94
L		 5825 if (i.tm.base_opcode == 0xf20f38f1
5826 || i.tm.base_opcode == 0xf20f38f0)
5827 {
5828 /* We have to know the operand size for crc32. */
5829 as_bad (_("ambiguous memory operand size for `%s`"),
5830 i.tm.name);
5831 return 0;
5832 }
5833
381d071f 5834 for (op = i.operands; --op >= 0;)
b76bc5d5
JB		 5835 if (!i.tm.operand_types[op].bitfield.inoutportreg
5836 && !i.tm.operand_types[op].bitfield.shiftcount)
381d071f 5837 {
8819ada6
JB		 5838 if (!i.types[op].bitfield.reg)
5839 continue;
5840 if (i.types[op].bitfield.byte)
5841 i.suffix = BYTE_MNEM_SUFFIX;
5842 else if (i.types[op].bitfield.word)
5843 i.suffix = WORD_MNEM_SUFFIX;
5844 else if (i.types[op].bitfield.dword)
5845 i.suffix = LONG_MNEM_SUFFIX;
5846 else if (i.types[op].bitfield.qword)
5847 i.suffix = QWORD_MNEM_SUFFIX;
5848 else
5849 continue;
5850 break;
381d071f
L		 5851 }
5852 }
29b0f896
AM		 5853 }
5854 else if (i.suffix == BYTE_MNEM_SUFFIX)
5855 {
2eb952a4
L		 5856 if (intel_syntax
5857 && i.tm.opcode_modifier.ignoresize
5858 && i.tm.opcode_modifier.no_bsuf)
5859 i.suffix = 0;
5860 else if (!check_byte_reg ())
29b0f896
AM		 5861 return 0;
5862 }
5863 else if (i.suffix == LONG_MNEM_SUFFIX)
5864 {
2eb952a4
L		 5865 if (intel_syntax
5866 && i.tm.opcode_modifier.ignoresize
9f123b91
JB		 5867 && i.tm.opcode_modifier.no_lsuf
5868 && !i.tm.opcode_modifier.todword
5869 && !i.tm.opcode_modifier.toqword)
2eb952a4
L		 5870 i.suffix = 0;
5871 else if (!check_long_reg ())
29b0f896
AM		 5872 return 0;
5873 }
5874 else if (i.suffix == QWORD_MNEM_SUFFIX)
5875 {
955e1e6a
L		 5876 if (intel_syntax
5877 && i.tm.opcode_modifier.ignoresize
9f123b91
JB		 5878 && i.tm.opcode_modifier.no_qsuf
5879 && !i.tm.opcode_modifier.todword
5880 && !i.tm.opcode_modifier.toqword)
955e1e6a
L		 5881 i.suffix = 0;
5882 else if (!check_qword_reg ())
29b0f896
AM		 5883 return 0;
5884 }
5885 else if (i.suffix == WORD_MNEM_SUFFIX)
5886 {
2eb952a4
L		 5887 if (intel_syntax
5888 && i.tm.opcode_modifier.ignoresize
5889 && i.tm.opcode_modifier.no_wsuf)
5890 i.suffix = 0;
5891 else if (!check_word_reg ())
29b0f896
AM		 5892 return 0;
5893 }
40fb9820 5894 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5895 /* Do nothing if the instruction is going to ignore the prefix. */
5896 ;
5897 else
5898 abort ();
5899 }
40fb9820 5900 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5901 && !i.suffix
5902 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5903 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5904 {
5905 i.suffix = stackop_size;
5906 }
9306ca4a
JB		 5907 else if (intel_syntax
5908 && !i.suffix
40fb9820
L		 5909 && (i.tm.operand_types[0].bitfield.jumpabsolute
5910 || i.tm.opcode_modifier.jumpbyte
5911 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5912 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5913 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5914 {
5915 switch (flag_code)
5916 {
5917 case CODE_64BIT:
40fb9820 5918 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5919 {
5920 i.suffix = QWORD_MNEM_SUFFIX;
5921 break;
5922 }
1a0670f3 5923 /* Fall through. */
9306ca4a 5924 case CODE_32BIT:
40fb9820 5925 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5926 i.suffix = LONG_MNEM_SUFFIX;
5927 break;
5928 case CODE_16BIT:
40fb9820 5929 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5930 i.suffix = WORD_MNEM_SUFFIX;
5931 break;
5932 }
5933 }
252b5132 5934
9306ca4a 5935 if (!i.suffix)
29b0f896 5936 {
9306ca4a
JB		 5937 if (!intel_syntax)
5938 {
40fb9820 5939 if (i.tm.opcode_modifier.w)
9306ca4a 5940 {
4eed87de
AM		 5941 as_bad (_("no instruction mnemonic suffix given and "
5942 "no register operands; can't size instruction"));
9306ca4a
JB		 5943 return 0;
5944 }
5945 }
5946 else
5947 {
40fb9820 5948 unsigned int suffixes;
7ab9ffdd 5949
40fb9820
L		 5950 suffixes = !i.tm.opcode_modifier.no_bsuf;
5951 if (!i.tm.opcode_modifier.no_wsuf)
5952 suffixes |= 1 << 1;
5953 if (!i.tm.opcode_modifier.no_lsuf)
5954 suffixes |= 1 << 2;
fc4adea1 5955 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5956 suffixes |= 1 << 3;
5957 if (!i.tm.opcode_modifier.no_ssuf)
5958 suffixes |= 1 << 4;
c2b9da16 5959 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
40fb9820
L		 5960 suffixes |= 1 << 5;
5961
5962 /* There are more than suffix matches. */
5963 if (i.tm.opcode_modifier.w
9306ca4a 5964 || ((suffixes & (suffixes - 1))
40fb9820
L		 5965 && !i.tm.opcode_modifier.defaultsize
5966 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5967 {
5968 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5969 return 0;
5970 }
5971 }
29b0f896 5972 }
252b5132 5973
d2224064
JB		 5974 /* Change the opcode based on the operand size given by i.suffix. */
5975 switch (i.suffix)
29b0f896 5976 {
d2224064
JB		 5977 /* Size floating point instruction. */
5978 case LONG_MNEM_SUFFIX:
5979 if (i.tm.opcode_modifier.floatmf)
5980 {
5981 i.tm.base_opcode ^= 4;
5982 break;
5983 }
5984 /* fall through */
5985 case WORD_MNEM_SUFFIX:
5986 case QWORD_MNEM_SUFFIX:
29b0f896 5987 /* It's not a byte, select word/dword operation. */
40fb9820 5988 if (i.tm.opcode_modifier.w)
29b0f896 5989 {
40fb9820 5990 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5991 i.tm.base_opcode |= 8;
5992 else
5993 i.tm.base_opcode |= 1;
5994 }
d2224064
JB		 5995 /* fall through */
5996 case SHORT_MNEM_SUFFIX:
29b0f896
AM		 5997 /* Now select between word & dword operations via the operand
5998 size prefix, except for instructions that will ignore this
5999 prefix anyway. */
ca61edf2 6000 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 6001 {
ca61edf2
L		 6002 /* The address size override prefix changes the size of the
6003 first operand. */
40fb9820 6004 if ((flag_code == CODE_32BIT
dc821c5f 6005 && i.op->regs[0].reg_type.bitfield.word)
40fb9820 6006 || (flag_code != CODE_32BIT
dc821c5f 6007 && i.op->regs[0].reg_type.bitfield.dword))
cb712a9e
L		 6008 if (!add_prefix (ADDR_PREFIX_OPCODE))
6009 return 0;
6010 }
6011 else if (i.suffix != QWORD_MNEM_SUFFIX
40fb9820
L		 6012 && !i.tm.opcode_modifier.ignoresize
6013 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 6014 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
6015 || (flag_code == CODE_64BIT
40fb9820 6016 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 6017 {
6018 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 6019
40fb9820 6020 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 6021 prefix = ADDR_PREFIX_OPCODE;
252b5132 6022
29b0f896
AM		 6023 if (!add_prefix (prefix))
6024 return 0;
24eab124 6025 }
252b5132 6026
29b0f896
AM		 6027 /* Set mode64 for an operand. */
6028 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 6029 && flag_code == CODE_64BIT
d2224064 6030 && !i.tm.opcode_modifier.norex64
46e883c5 6031 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d2224064
JB		 6032 need rex64. */
6033 && ! (i.operands == 2
6034 && i.tm.base_opcode == 0x90
6035 && i.tm.extension_opcode == None
6036 && operand_type_equal (&i.types [0], &acc64)
6037 && operand_type_equal (&i.types [1], &acc64)))
6038 i.rex |= REX_W;
3e73aa7c 6039
d2224064 6040 break;
29b0f896 6041 }
7ecd2f8b 6042
29b0f896
AM		 6043 return 1;
6044}
3e73aa7c 6045
29b0f896 6046static int
543613e9 6047check_byte_reg (void)
29b0f896
AM		 6048{
6049 int op;
543613e9 6050
29b0f896
AM		 6051 for (op = i.operands; --op >= 0;)
6052 {
dc821c5f
JB		 6053 /* Skip non-register operands. */
6054 if (!i.types[op].bitfield.reg)
6055 continue;
6056
29b0f896
AM		 6057 /* If this is an eight bit register, it's OK. If it's the 16 or
6058 32 bit version of an eight bit register, we will just use the
6059 low portion, and that's OK too. */
dc821c5f 6060 if (i.types[op].bitfield.byte)
29b0f896
AM		 6061 continue;
6062
5a819eb9
JB		 6063 /* I/O port address operands are OK too. */
6064 if (i.tm.operand_types[op].bitfield.inoutportreg)
6065 continue;
6066
9344ff29
L		 6067 /* crc32 doesn't generate this warning. */
6068 if (i.tm.base_opcode == 0xf20f38f0)
6069 continue;
6070
dc821c5f
JB		 6071 if ((i.types[op].bitfield.word
6072 || i.types[op].bitfield.dword
6073 || i.types[op].bitfield.qword)
5a819eb9
JB		 6074 && i.op[op].regs->reg_num < 4
6075 /* Prohibit these changes in 64bit mode, since the lowering
6076 would be more complicated. */
6077 && flag_code != CODE_64BIT)
29b0f896 6078 {
29b0f896 6079#if REGISTER_WARNINGS
5a819eb9 6080 if (!quiet_warnings)
a540244d
L		 6081 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6082 register_prefix,
dc821c5f 6083 (i.op[op].regs + (i.types[op].bitfield.word
29b0f896
AM		 6084 ? REGNAM_AL - REGNAM_AX
6085 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 6086 register_prefix,
29b0f896
AM		 6087 i.op[op].regs->reg_name,
6088 i.suffix);
6089#endif
6090 continue;
6091 }
6092 /* Any other register is bad. */
dc821c5f 6093 if (i.types[op].bitfield.reg
40fb9820 6094 || i.types[op].bitfield.regmmx
1b54b8d7 6095 || i.types[op].bitfield.regsimd
40fb9820
L		 6096 || i.types[op].bitfield.sreg2
6097 || i.types[op].bitfield.sreg3
6098 || i.types[op].bitfield.control
6099 || i.types[op].bitfield.debug
ca0d63fe 6100 || i.types[op].bitfield.test)
29b0f896 6101 {
a540244d
L		 6102 as_bad (_("`%s%s' not allowed with `%s%c'"),
6103 register_prefix,
29b0f896
AM		 6104 i.op[op].regs->reg_name,
6105 i.tm.name,
6106 i.suffix);
6107 return 0;
6108 }
6109 }
6110 return 1;
6111}
6112
6113static int
e3bb37b5 6114check_long_reg (void)
29b0f896
AM		 6115{
6116 int op;
6117
6118 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 6119 /* Skip non-register operands. */
6120 if (!i.types[op].bitfield.reg)
6121 continue;
29b0f896
AM		 6122 /* Reject eight bit registers, except where the template requires
6123 them. (eg. movzb) */
dc821c5f
JB		 6124 else if (i.types[op].bitfield.byte
6125 && (i.tm.operand_types[op].bitfield.reg
6126 || i.tm.operand_types[op].bitfield.acc)
6127 && (i.tm.operand_types[op].bitfield.word
6128 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6129 {
a540244d
L		 6130 as_bad (_("`%s%s' not allowed with `%s%c'"),
6131 register_prefix,
29b0f896
AM		 6132 i.op[op].regs->reg_name,
6133 i.tm.name,
6134 i.suffix);
6135 return 0;
6136 }
e4630f71 6137 /* Warn if the e prefix on a general reg is missing. */
29b0f896 6138 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 6139 && i.types[op].bitfield.word
6140 && (i.tm.operand_types[op].bitfield.reg
6141 || i.tm.operand_types[op].bitfield.acc)
6142 && i.tm.operand_types[op].bitfield.dword)
29b0f896
AM		 6143 {
6144 /* Prohibit these changes in the 64bit mode, since the
6145 lowering is more complicated. */
6146 if (flag_code == CODE_64BIT)
252b5132 6147 {
2b5d6a91 6148 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 6149 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 6150 i.suffix);
6151 return 0;
252b5132 6152 }
29b0f896 6153#if REGISTER_WARNINGS
cecf1424
JB		 6154 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6155 register_prefix,
6156 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6157 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 6158#endif
252b5132 6159 }
e4630f71 6160 /* Warn if the r prefix on a general reg is present. */
dc821c5f
JB		 6161 else if (i.types[op].bitfield.qword
6162 && (i.tm.operand_types[op].bitfield.reg
6163 || i.tm.operand_types[op].bitfield.acc)
6164 && i.tm.operand_types[op].bitfield.dword)
252b5132 6165 {
34828aad 6166 if (intel_syntax
ca61edf2 6167 && i.tm.opcode_modifier.toqword
1b54b8d7 6168 && !i.types[0].bitfield.regsimd)
34828aad 6169 {
ca61edf2 6170 /* Convert to QWORD. We want REX byte. */
34828aad
L		 6171 i.suffix = QWORD_MNEM_SUFFIX;
6172 }
6173 else
6174 {
2b5d6a91 6175 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 6176 register_prefix, i.op[op].regs->reg_name,
6177 i.suffix);
6178 return 0;
6179 }
29b0f896
AM		 6180 }
6181 return 1;
6182}
252b5132 6183
29b0f896 6184static int
e3bb37b5 6185check_qword_reg (void)
29b0f896
AM		 6186{
6187 int op;
252b5132 6188
29b0f896 6189 for (op = i.operands; --op >= 0; )
dc821c5f
JB		 6190 /* Skip non-register operands. */
6191 if (!i.types[op].bitfield.reg)
6192 continue;
29b0f896
AM		 6193 /* Reject eight bit registers, except where the template requires
6194 them. (eg. movzb) */
dc821c5f
JB		 6195 else if (i.types[op].bitfield.byte
6196 && (i.tm.operand_types[op].bitfield.reg
6197 || i.tm.operand_types[op].bitfield.acc)
6198 && (i.tm.operand_types[op].bitfield.word
6199 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6200 {
a540244d
L		 6201 as_bad (_("`%s%s' not allowed with `%s%c'"),
6202 register_prefix,
29b0f896
AM		 6203 i.op[op].regs->reg_name,
6204 i.tm.name,
6205 i.suffix);
6206 return 0;
6207 }
e4630f71 6208 /* Warn if the r prefix on a general reg is missing. */
dc821c5f
JB		 6209 else if ((i.types[op].bitfield.word
6210 || i.types[op].bitfield.dword)
6211 && (i.tm.operand_types[op].bitfield.reg
6212 || i.tm.operand_types[op].bitfield.acc)
6213 && i.tm.operand_types[op].bitfield.qword)
29b0f896
AM		 6214 {
6215 /* Prohibit these changes in the 64bit mode, since the
6216 lowering is more complicated. */
34828aad 6217 if (intel_syntax
ca61edf2 6218 && i.tm.opcode_modifier.todword
1b54b8d7 6219 && !i.types[0].bitfield.regsimd)
34828aad 6220 {
ca61edf2 6221 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 6222 i.suffix = LONG_MNEM_SUFFIX;
6223 }
6224 else
6225 {
2b5d6a91 6226 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 6227 register_prefix, i.op[op].regs->reg_name,
6228 i.suffix);
6229 return 0;
6230 }
252b5132 6231 }
29b0f896
AM		 6232 return 1;
6233}
252b5132 6234
29b0f896 6235static int
e3bb37b5 6236check_word_reg (void)
29b0f896
AM		 6237{
6238 int op;
6239 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 6240 /* Skip non-register operands. */
6241 if (!i.types[op].bitfield.reg)
6242 continue;
29b0f896
AM		 6243 /* Reject eight bit registers, except where the template requires
6244 them. (eg. movzb) */
dc821c5f
JB		 6245 else if (i.types[op].bitfield.byte
6246 && (i.tm.operand_types[op].bitfield.reg
6247 || i.tm.operand_types[op].bitfield.acc)
6248 && (i.tm.operand_types[op].bitfield.word
6249 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6250 {
a540244d
L		 6251 as_bad (_("`%s%s' not allowed with `%s%c'"),
6252 register_prefix,
29b0f896
AM		 6253 i.op[op].regs->reg_name,
6254 i.tm.name,
6255 i.suffix);
6256 return 0;
6257 }
e4630f71 6258 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 6259 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 6260 && (i.types[op].bitfield.dword
6261 || i.types[op].bitfield.qword)
6262 && (i.tm.operand_types[op].bitfield.reg
6263 || i.tm.operand_types[op].bitfield.acc)
6264 && i.tm.operand_types[op].bitfield.word)
252b5132 6265 {
29b0f896
AM		 6266 /* Prohibit these changes in the 64bit mode, since the
6267 lowering is more complicated. */
6268 if (flag_code == CODE_64BIT)
252b5132 6269 {
2b5d6a91 6270 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 6271 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 6272 i.suffix);
6273 return 0;
252b5132 6274 }
29b0f896 6275#if REGISTER_WARNINGS
cecf1424
JB		 6276 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6277 register_prefix,
6278 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6279 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 6280#endif
6281 }
6282 return 1;
6283}
252b5132 6284
29b0f896 6285static int
40fb9820 6286update_imm (unsigned int j)
29b0f896 6287{
bc0844ae 6288 i386_operand_type overlap = i.types[j];
40fb9820
L		 6289 if ((overlap.bitfield.imm8
6290 || overlap.bitfield.imm8s
6291 || overlap.bitfield.imm16
6292 || overlap.bitfield.imm32
6293 || overlap.bitfield.imm32s
6294 || overlap.bitfield.imm64)
0dfbf9d7
L		 6295 && !operand_type_equal (&overlap, &imm8)
6296 && !operand_type_equal (&overlap, &imm8s)
6297 && !operand_type_equal (&overlap, &imm16)
6298 && !operand_type_equal (&overlap, &imm32)
6299 && !operand_type_equal (&overlap, &imm32s)
6300 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 6301 {
6302 if (i.suffix)
6303 {
40fb9820
L		 6304 i386_operand_type temp;
6305
0dfbf9d7 6306 operand_type_set (&temp, 0);
7ab9ffdd 6307 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 6308 {
6309 temp.bitfield.imm8 = overlap.bitfield.imm8;
6310 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6311 }
6312 else if (i.suffix == WORD_MNEM_SUFFIX)
6313 temp.bitfield.imm16 = overlap.bitfield.imm16;
6314 else if (i.suffix == QWORD_MNEM_SUFFIX)
6315 {
6316 temp.bitfield.imm64 = overlap.bitfield.imm64;
6317 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6318 }
6319 else
6320 temp.bitfield.imm32 = overlap.bitfield.imm32;
6321 overlap = temp;
29b0f896 6322 }
0dfbf9d7
L		 6323 else if (operand_type_equal (&overlap, &imm16_32_32s)
6324 || operand_type_equal (&overlap, &imm16_32)
6325 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 6326 {
40fb9820 6327 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 6328 overlap = imm16;
40fb9820 6329 else
65da13b5 6330 overlap = imm32s;
29b0f896 6331 }
0dfbf9d7
L		 6332 if (!operand_type_equal (&overlap, &imm8)
6333 && !operand_type_equal (&overlap, &imm8s)
6334 && !operand_type_equal (&overlap, &imm16)
6335 && !operand_type_equal (&overlap, &imm32)
6336 && !operand_type_equal (&overlap, &imm32s)
6337 && !operand_type_equal (&overlap, &imm64))
29b0f896 6338 {
4eed87de
AM		 6339 as_bad (_("no instruction mnemonic suffix given; "
6340 "can't determine immediate size"));
29b0f896
AM		 6341 return 0;
6342 }
6343 }
40fb9820 6344 i.types[j] = overlap;
29b0f896 6345
40fb9820
L		 6346 return 1;
6347}
6348
6349static int
6350finalize_imm (void)
6351{
bc0844ae 6352 unsigned int j, n;
29b0f896 6353
bc0844ae
L		 6354 /* Update the first 2 immediate operands. */
6355 n = i.operands > 2 ? 2 : i.operands;
6356 if (n)
6357 {
6358 for (j = 0; j < n; j++)
6359 if (update_imm (j) == 0)
6360 return 0;
40fb9820 6361
bc0844ae
L		 6362 /* The 3rd operand can't be immediate operand. */
6363 gas_assert (operand_type_check (i.types[2], imm) == 0);
6364 }
29b0f896
AM		 6365
6366 return 1;
6367}
6368
6369static int
e3bb37b5 6370process_operands (void)
29b0f896
AM		 6371{
6372 /* Default segment register this instruction will use for memory
6373 accesses. 0 means unknown. This is only for optimizing out
6374 unnecessary segment overrides. */
6375 const seg_entry *default_seg = 0;
6376
2426c15f 6377 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 6378 {
91d6fa6a
NC		 6379 unsigned int dupl = i.operands;
6380 unsigned int dest = dupl - 1;
9fcfb3d7
L		 6381 unsigned int j;
6382
c0f3af97 6383 /* The destination must be an xmm register. */
9c2799c2 6384 gas_assert (i.reg_operands
91d6fa6a 6385 && MAX_OPERANDS > dupl
7ab9ffdd 6386 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97 6387
1b54b8d7
JB		 6388 if (i.tm.operand_types[0].bitfield.acc
6389 && i.tm.operand_types[0].bitfield.xmmword)
e2ec9d29 6390 {
8cd7925b 6391 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 6392 {
6393 /* Keep xmm0 for instructions with VEX prefix and 3
6394 sources. */
1b54b8d7
JB		 6395 i.tm.operand_types[0].bitfield.acc = 0;
6396 i.tm.operand_types[0].bitfield.regsimd = 1;
c0f3af97
L		 6397 goto duplicate;
6398 }
e2ec9d29 6399 else
c0f3af97
L		 6400 {
6401 /* We remove the first xmm0 and keep the number of
6402 operands unchanged, which in fact duplicates the
6403 destination. */
6404 for (j = 1; j < i.operands; j++)
6405 {
6406 i.op[j - 1] = i.op[j];
6407 i.types[j - 1] = i.types[j];
6408 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6409 }
6410 }
6411 }
6412 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 6413 {
91d6fa6a 6414 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 6415 && (i.tm.opcode_modifier.vexsources
6416 == VEX3SOURCES));
c0f3af97
L		 6417
6418 /* Add the implicit xmm0 for instructions with VEX prefix
6419 and 3 sources. */
6420 for (j = i.operands; j > 0; j--)
6421 {
6422 i.op[j] = i.op[j - 1];
6423 i.types[j] = i.types[j - 1];
6424 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6425 }
6426 i.op[0].regs
6427 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 6428 i.types[0] = regxmm;
c0f3af97
L		 6429 i.tm.operand_types[0] = regxmm;
6430
6431 i.operands += 2;
6432 i.reg_operands += 2;
6433 i.tm.operands += 2;
6434
91d6fa6a 6435 dupl++;
c0f3af97 6436 dest++;
91d6fa6a
NC		 6437 i.op[dupl] = i.op[dest];
6438 i.types[dupl] = i.types[dest];
6439 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 6440 }
c0f3af97
L		 6441 else
6442 {
6443duplicate:
6444 i.operands++;
6445 i.reg_operands++;
6446 i.tm.operands++;
6447
91d6fa6a
NC		 6448 i.op[dupl] = i.op[dest];
6449 i.types[dupl] = i.types[dest];
6450 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 6451 }
6452
6453 if (i.tm.opcode_modifier.immext)
6454 process_immext ();
6455 }
1b54b8d7
JB		 6456 else if (i.tm.operand_types[0].bitfield.acc
6457 && i.tm.operand_types[0].bitfield.xmmword)
c0f3af97
L		 6458 {
6459 unsigned int j;
6460
9fcfb3d7
L		 6461 for (j = 1; j < i.operands; j++)
6462 {
6463 i.op[j - 1] = i.op[j];
6464 i.types[j - 1] = i.types[j];
6465
6466 /* We need to adjust fields in i.tm since they are used by
6467 build_modrm_byte. */
6468 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6469 }
6470
e2ec9d29
L		 6471 i.operands--;
6472 i.reg_operands--;
e2ec9d29
L		 6473 i.tm.operands--;
6474 }
920d2ddc
IT		 6475 else if (i.tm.opcode_modifier.implicitquadgroup)
6476 {
a477a8c4
JB		 6477 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6478
920d2ddc 6479 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
10c17abd 6480 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
a477a8c4
JB		 6481 regnum = register_number (i.op[1].regs);
6482 first_reg_in_group = regnum & ~3;
6483 last_reg_in_group = first_reg_in_group + 3;
6484 if (regnum != first_reg_in_group)
6485 as_warn (_("source register `%s%s' implicitly denotes"
6486 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6487 register_prefix, i.op[1].regs->reg_name,
6488 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6489 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6490 i.tm.name);
6491 }
e2ec9d29
L		 6492 else if (i.tm.opcode_modifier.regkludge)
6493 {
6494 /* The imul $imm, %reg instruction is converted into
6495 imul $imm, %reg, %reg, and the clr %reg instruction
6496 is converted into xor %reg, %reg. */
6497
6498 unsigned int first_reg_op;
6499
6500 if (operand_type_check (i.types[0], reg))
6501 first_reg_op = 0;
6502 else
6503 first_reg_op = 1;
6504 /* Pretend we saw the extra register operand. */
9c2799c2 6505 gas_assert (i.reg_operands == 1
7ab9ffdd 6506 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 6507 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6508 i.types[first_reg_op + 1] = i.types[first_reg_op];
6509 i.operands++;
6510 i.reg_operands++;
29b0f896
AM		 6511 }
6512
40fb9820 6513 if (i.tm.opcode_modifier.shortform)
29b0f896 6514 {
40fb9820
L		 6515 if (i.types[0].bitfield.sreg2
6516 || i.types[0].bitfield.sreg3)
29b0f896 6517 {
4eed87de
AM		 6518 if (i.tm.base_opcode == POP_SEG_SHORT
6519 && i.op[0].regs->reg_num == 1)
29b0f896 6520 {
a87af027 6521 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 6522 return 0;
29b0f896 6523 }
4eed87de
AM		 6524 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6525 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 6526 i.rex |= REX_B;
4eed87de
AM		 6527 }
6528 else
6529 {
7ab9ffdd 6530 /* The register or float register operand is in operand
85f10a01 6531 0 or 1. */
40fb9820 6532 unsigned int op;
7ab9ffdd 6533
ca0d63fe 6534 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
7ab9ffdd
L		 6535 || operand_type_check (i.types[0], reg))
6536 op = 0;
6537 else
6538 op = 1;
4eed87de
AM		 6539 /* Register goes in low 3 bits of opcode. */
6540 i.tm.base_opcode |= i.op[op].regs->reg_num;
6541 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 6542 i.rex |= REX_B;
40fb9820 6543 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 6544 {
4eed87de
AM		 6545 /* Warn about some common errors, but press on regardless.
6546 The first case can be generated by gcc (<= 2.8.1). */
6547 if (i.operands == 2)
6548 {
6549 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 6550 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 6551 register_prefix, i.op[!intel_syntax].regs->reg_name,
6552 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 6553 }
6554 else
6555 {
6556 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 6557 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6558 register_prefix, i.op[0].regs->reg_name);
4eed87de 6559 }
29b0f896
AM		 6560 }
6561 }
6562 }
40fb9820 6563 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 6564 {
6565 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 6566 must be put into the modrm byte). Now, we make the modrm and
6567 index base bytes based on all the info we've collected. */
29b0f896
AM		 6568
6569 default_seg = build_modrm_byte ();
6570 }
8a2ed489 6571 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 6572 {
6573 default_seg = &ds;
6574 }
40fb9820 6575 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 6576 {
6577 /* For the string instructions that allow a segment override
6578 on one of their operands, the default segment is ds. */
6579 default_seg = &ds;
6580 }
6581
75178d9d
L		 6582 if (i.tm.base_opcode == 0x8d /* lea */
6583 && i.seg[0]
6584 && !quiet_warnings)
30123838 6585 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 6586
6587 /* If a segment was explicitly specified, and the specified segment
6588 is not the default, use an opcode prefix to select it. If we
6589 never figured out what the default segment is, then default_seg
6590 will be zero at this point, and the specified segment prefix will
6591 always be used. */
29b0f896
AM		 6592 if ((i.seg[0]) && (i.seg[0] != default_seg))
6593 {
6594 if (!add_prefix (i.seg[0]->seg_prefix))
6595 return 0;
6596 }
6597 return 1;
6598}
6599
6600static const seg_entry *
e3bb37b5 6601build_modrm_byte (void)
29b0f896
AM		 6602{
6603 const seg_entry *default_seg = 0;
c0f3af97 6604 unsigned int source, dest;
8cd7925b 6605 int vex_3_sources;
c0f3af97 6606
8cd7925b 6607 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6608 if (vex_3_sources)
6609 {
91d6fa6a 6610 unsigned int nds, reg_slot;
4c2c6516 6611 expressionS *exp;
c0f3af97 6612
6b8d3588 6613 dest = i.operands - 1;
c0f3af97 6614 nds = dest - 1;
922d8de8 6615
a683cc34 6616 /* There are 2 kinds of instructions:
bed3d976
JB		 6617 1. 5 operands: 4 register operands or 3 register operands
6618 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6619 VexW0 or VexW1. The destination must be either XMM, YMM or
43234a1e 6620 ZMM register.
bed3d976 6621 2. 4 operands: 4 register operands or 3 register operands
2f1bada2 6622 plus 1 memory operand, with VexXDS. */
922d8de8 6623 gas_assert ((i.reg_operands == 4
bed3d976
JB		 6624 || (i.reg_operands == 3 && i.mem_operands == 1))
6625 && i.tm.opcode_modifier.vexvvvv == VEXXDS
dcd7e323
JB		 6626 && i.tm.opcode_modifier.vexw
6627 && i.tm.operand_types[dest].bitfield.regsimd);
a683cc34 6628
48db9223
JB		 6629 /* If VexW1 is set, the first non-immediate operand is the source and
6630 the second non-immediate one is encoded in the immediate operand. */
6631 if (i.tm.opcode_modifier.vexw == VEXW1)
6632 {
6633 source = i.imm_operands;
6634 reg_slot = i.imm_operands + 1;
6635 }
6636 else
6637 {
6638 source = i.imm_operands + 1;
6639 reg_slot = i.imm_operands;
6640 }
6641
a683cc34 6642 if (i.imm_operands == 0)
bed3d976
JB		 6643 {
6644 /* When there is no immediate operand, generate an 8bit
6645 immediate operand to encode the first operand. */
6646 exp = &im_expressions[i.imm_operands++];
6647 i.op[i.operands].imms = exp;
6648 i.types[i.operands] = imm8;
6649 i.operands++;
6650
6651 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6652 exp->X_op = O_constant;
6653 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6654 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6655 }
922d8de8 6656 else
bed3d976
JB		 6657 {
6658 unsigned int imm_slot;
a683cc34 6659
2f1bada2
JB		 6660 gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4);
6661
bed3d976
JB		 6662 if (i.tm.opcode_modifier.immext)
6663 {
6664 /* When ImmExt is set, the immediate byte is the last
6665 operand. */
6666 imm_slot = i.operands - 1;
6667 source--;
6668 reg_slot--;
6669 }
6670 else
6671 {
6672 imm_slot = 0;
6673
6674 /* Turn on Imm8 so that output_imm will generate it. */
6675 i.types[imm_slot].bitfield.imm8 = 1;
6676 }
6677
6678 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6679 i.op[imm_slot].imms->X_add_number
6680 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6681 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
bed3d976 6682 }
a683cc34 6683
10c17abd 6684 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
dae39acc 6685 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6686 }
6687 else
6688 source = dest = 0;
29b0f896
AM		 6689
6690 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6691 implicit registers do not count. If there are 3 register
6692 operands, it must be a instruction with VexNDS. For a
6693 instruction with VexNDD, the destination register is encoded
6694 in VEX prefix. If there are 4 register operands, it must be
6695 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6696 if (i.mem_operands == 0
6697 && ((i.reg_operands == 2
2426c15f 6698 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6699 || (i.reg_operands == 3
2426c15f 6700 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6701 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6702 {
cab737b9
L		 6703 switch (i.operands)
6704 {
6705 case 2:
6706 source = 0;
6707 break;
6708 case 3:
c81128dc
L		 6709 /* When there are 3 operands, one of them may be immediate,
6710 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6711 the first operand must be shift count register (cl) or it
6712 is an instruction with VexNDS. */
9c2799c2 6713 gas_assert (i.imm_operands == 1
7ab9ffdd 6714 || (i.imm_operands == 0
2426c15f 6715 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6716 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6717 if (operand_type_check (i.types[0], imm)
6718 || i.types[0].bitfield.shiftcount)
6719 source = 1;
6720 else
6721 source = 0;
cab737b9
L		 6722 break;
6723 case 4:
368d64cc
L		 6724 /* When there are 4 operands, the first two must be 8bit
6725 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6726 one.
6727
6728 For instructions with VexNDS, if the first operand
6729 an imm8, the source operand is the 2nd one. If the last
6730 operand is imm8, the source operand is the first one. */
9c2799c2 6731 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6732 && i.types[0].bitfield.imm8
6733 && i.types[1].bitfield.imm8)
2426c15f 6734 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6735 && i.imm_operands == 1
6736 && (i.types[0].bitfield.imm8
43234a1e
L		 6737 || i.types[i.operands - 1].bitfield.imm8
6738 || i.rounding)));
9f2670f2
L		 6739 if (i.imm_operands == 2)
6740 source = 2;
6741 else
c0f3af97
L		 6742 {
6743 if (i.types[0].bitfield.imm8)
6744 source = 1;
6745 else
6746 source = 0;
6747 }
c0f3af97
L		 6748 break;
6749 case 5:
e771e7c9 6750 if (is_evex_encoding (&i.tm))
43234a1e
L		 6751 {
6752 /* For EVEX instructions, when there are 5 operands, the
6753 first one must be immediate operand. If the second one
6754 is immediate operand, the source operand is the 3th
6755 one. If the last one is immediate operand, the source
6756 operand is the 2nd one. */
6757 gas_assert (i.imm_operands == 2
6758 && i.tm.opcode_modifier.sae
6759 && operand_type_check (i.types[0], imm));
6760 if (operand_type_check (i.types[1], imm))
6761 source = 2;
6762 else if (operand_type_check (i.types[4], imm))
6763 source = 1;
6764 else
6765 abort ();
6766 }
cab737b9
L		 6767 break;
6768 default:
6769 abort ();
6770 }
6771
c0f3af97
L		 6772 if (!vex_3_sources)
6773 {
6774 dest = source + 1;
6775
43234a1e
L		 6776 /* RC/SAE operand could be between DEST and SRC. That happens
6777 when one operand is GPR and the other one is XMM/YMM/ZMM
6778 register. */
6779 if (i.rounding && i.rounding->operand == (int) dest)
6780 dest++;
6781
2426c15f 6782 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6783 {
43234a1e 6784 /* For instructions with VexNDS, the register-only source
c5d0745b 6785 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
43234a1e
L		 6786 register. It is encoded in VEX prefix. We need to
6787 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6788
6789 i386_operand_type op;
6790 unsigned int vvvv;
6791
6792 /* Check register-only source operand when two source
6793 operands are swapped. */
6794 if (!i.tm.operand_types[source].bitfield.baseindex
6795 && i.tm.operand_types[dest].bitfield.baseindex)
6796 {
6797 vvvv = source;
6798 source = dest;
6799 }
6800 else
6801 vvvv = dest;
6802
6803 op = i.tm.operand_types[vvvv];
fa99fab2 6804 op.bitfield.regmem = 0;
c0f3af97 6805 if ((dest + 1) >= i.operands
dc821c5f
JB		 6806 || ((!op.bitfield.reg
6807 || (!op.bitfield.dword && !op.bitfield.qword))
10c17abd 6808 && !op.bitfield.regsimd
43234a1e 6809 && !operand_type_equal (&op, &regmask)))
c0f3af97 6810 abort ();
f12dc422 6811 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6812 dest++;
6813 }
6814 }
29b0f896
AM		 6815
6816 i.rm.mode = 3;
6817 /* One of the register operands will be encoded in the i.tm.reg
6818 field, the other in the combined i.tm.mode and i.tm.regmem
6819 fields. If no form of this instruction supports a memory
6820 destination operand, then we assume the source operand may
6821 sometimes be a memory operand and so we need to store the
6822 destination in the i.rm.reg field. */
40fb9820
L		 6823 if (!i.tm.operand_types[dest].bitfield.regmem
6824 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6825 {
6826 i.rm.reg = i.op[dest].regs->reg_num;
6827 i.rm.regmem = i.op[source].regs->reg_num;
6828 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6829 i.rex |= REX_R;
43234a1e
L		 6830 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6831 i.vrex |= REX_R;
29b0f896 6832 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6833 i.rex |= REX_B;
43234a1e
L		 6834 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6835 i.vrex |= REX_B;
29b0f896
AM		 6836 }
6837 else
6838 {
6839 i.rm.reg = i.op[source].regs->reg_num;
6840 i.rm.regmem = i.op[dest].regs->reg_num;
6841 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6842 i.rex |= REX_B;
43234a1e
L		 6843 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6844 i.vrex |= REX_B;
29b0f896 6845 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6846 i.rex |= REX_R;
43234a1e
L		 6847 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6848 i.vrex |= REX_R;
29b0f896 6849 }
161a04f6 6850 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6851 {
40fb9820
L		 6852 if (!i.types[0].bitfield.control
6853 && !i.types[1].bitfield.control)
c4a530c5 6854 abort ();
161a04f6 6855 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6856 add_prefix (LOCK_PREFIX_OPCODE);
6857 }
29b0f896
AM		 6858 }
6859 else
6860 { /* If it's not 2 reg operands... */
c0f3af97
L		 6861 unsigned int mem;
6862
29b0f896
AM		 6863 if (i.mem_operands)
6864 {
6865 unsigned int fake_zero_displacement = 0;
99018f42 6866 unsigned int op;
4eed87de 6867
7ab9ffdd
L		 6868 for (op = 0; op < i.operands; op++)
6869 if (operand_type_check (i.types[op], anymem))
6870 break;
7ab9ffdd 6871 gas_assert (op < i.operands);
29b0f896 6872
6c30d220
L		 6873 if (i.tm.opcode_modifier.vecsib)
6874 {
6875 if (i.index_reg->reg_num == RegEiz
6876 || i.index_reg->reg_num == RegRiz)
6877 abort ();
6878
6879 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6880 if (!i.base_reg)
6881 {
6882 i.sib.base = NO_BASE_REGISTER;
6883 i.sib.scale = i.log2_scale_factor;
6884 i.types[op].bitfield.disp8 = 0;
6885 i.types[op].bitfield.disp16 = 0;
6886 i.types[op].bitfield.disp64 = 0;
43083a50 6887 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6c30d220
L		 6888 {
6889 /* Must be 32 bit */
6890 i.types[op].bitfield.disp32 = 1;
6891 i.types[op].bitfield.disp32s = 0;
6892 }
6893 else
6894 {
6895 i.types[op].bitfield.disp32 = 0;
6896 i.types[op].bitfield.disp32s = 1;
6897 }
6898 }
6899 i.sib.index = i.index_reg->reg_num;
6900 if ((i.index_reg->reg_flags & RegRex) != 0)
6901 i.rex |= REX_X;
43234a1e
L		 6902 if ((i.index_reg->reg_flags & RegVRex) != 0)
6903 i.vrex |= REX_X;
6c30d220
L		 6904 }
6905
29b0f896
AM		 6906 default_seg = &ds;
6907
6908 if (i.base_reg == 0)
6909 {
6910 i.rm.mode = 0;
6911 if (!i.disp_operands)
9bb129e8 6912 fake_zero_displacement = 1;
29b0f896
AM		 6913 if (i.index_reg == 0)
6914 {
73053c1f
JB		 6915 i386_operand_type newdisp;
6916
6c30d220 6917 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6918 /* Operand is just <disp> */
20f0a1fc 6919 if (flag_code == CODE_64BIT)
29b0f896
AM		 6920 {
6921 /* 64bit mode overwrites the 32bit absolute
6922 addressing by RIP relative addressing and
6923 absolute addressing is encoded by one of the
6924 redundant SIB forms. */
6925 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6926 i.sib.base = NO_BASE_REGISTER;
6927 i.sib.index = NO_INDEX_REGISTER;
73053c1f 6928 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
20f0a1fc 6929 }
fc225355
L		 6930 else if ((flag_code == CODE_16BIT)
6931 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6932 {
6933 i.rm.regmem = NO_BASE_REGISTER_16;
73053c1f 6934 newdisp = disp16;
20f0a1fc
NC		 6935 }
6936 else
6937 {
6938 i.rm.regmem = NO_BASE_REGISTER;
73053c1f 6939 newdisp = disp32;
29b0f896 6940 }
73053c1f
JB		 6941 i.types[op] = operand_type_and_not (i.types[op], anydisp);
6942 i.types[op] = operand_type_or (i.types[op], newdisp);
29b0f896 6943 }
6c30d220 6944 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6945 {
6c30d220 6946 /* !i.base_reg && i.index_reg */
db51cc60
L		 6947 if (i.index_reg->reg_num == RegEiz
6948 || i.index_reg->reg_num == RegRiz)
6949 i.sib.index = NO_INDEX_REGISTER;
6950 else
6951 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6952 i.sib.base = NO_BASE_REGISTER;
6953 i.sib.scale = i.log2_scale_factor;
6954 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 6955 i.types[op].bitfield.disp8 = 0;
6956 i.types[op].bitfield.disp16 = 0;
6957 i.types[op].bitfield.disp64 = 0;
43083a50 6958 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
40fb9820
L		 6959 {
6960 /* Must be 32 bit */
6961 i.types[op].bitfield.disp32 = 1;
6962 i.types[op].bitfield.disp32s = 0;
6963 }
29b0f896 6964 else
40fb9820
L		 6965 {
6966 i.types[op].bitfield.disp32 = 0;
6967 i.types[op].bitfield.disp32s = 1;
6968 }
29b0f896 6969 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6970 i.rex |= REX_X;
29b0f896
AM		 6971 }
6972 }
6973 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6974 else if (i.base_reg->reg_num == RegRip ||
6975 i.base_reg->reg_num == RegEip)
29b0f896 6976 {
6c30d220 6977 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6978 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6979 i.types[op].bitfield.disp8 = 0;
6980 i.types[op].bitfield.disp16 = 0;
6981 i.types[op].bitfield.disp32 = 0;
6982 i.types[op].bitfield.disp32s = 1;
6983 i.types[op].bitfield.disp64 = 0;
71903a11 6984 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6985 if (! i.disp_operands)
6986 fake_zero_displacement = 1;
29b0f896 6987 }
dc821c5f 6988 else if (i.base_reg->reg_type.bitfield.word)
29b0f896 6989 {
6c30d220 6990 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6991 switch (i.base_reg->reg_num)
6992 {
6993 case 3: /* (%bx) */
6994 if (i.index_reg == 0)
6995 i.rm.regmem = 7;
6996 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6997 i.rm.regmem = i.index_reg->reg_num - 6;
6998 break;
6999 case 5: /* (%bp) */
7000 default_seg = &ss;
7001 if (i.index_reg == 0)
7002 {
7003 i.rm.regmem = 6;
40fb9820 7004 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 7005 {
7006 /* fake (%bp) into 0(%bp) */
b5014f7a 7007 i.types[op].bitfield.disp8 = 1;
252b5132 7008 fake_zero_displacement = 1;
29b0f896
AM		 7009 }
7010 }
7011 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7012 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
7013 break;
7014 default: /* (%si) -> 4 or (%di) -> 5 */
7015 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
7016 }
7017 i.rm.mode = mode_from_disp_size (i.types[op]);
7018 }
7019 else /* i.base_reg and 32/64 bit mode */
7020 {
7021 if (flag_code == CODE_64BIT
40fb9820
L		 7022 && operand_type_check (i.types[op], disp))
7023 {
73053c1f
JB		 7024 i.types[op].bitfield.disp16 = 0;
7025 i.types[op].bitfield.disp64 = 0;
40fb9820 7026 if (i.prefix[ADDR_PREFIX] == 0)
73053c1f
JB		 7027 {
7028 i.types[op].bitfield.disp32 = 0;
7029 i.types[op].bitfield.disp32s = 1;
7030 }
40fb9820 7031 else
73053c1f
JB		 7032 {
7033 i.types[op].bitfield.disp32 = 1;
7034 i.types[op].bitfield.disp32s = 0;
7035 }
40fb9820 7036 }
20f0a1fc 7037
6c30d220
L		 7038 if (!i.tm.opcode_modifier.vecsib)
7039 i.rm.regmem = i.base_reg->reg_num;
29b0f896 7040 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 7041 i.rex |= REX_B;
29b0f896
AM		 7042 i.sib.base = i.base_reg->reg_num;
7043 /* x86-64 ignores REX prefix bit here to avoid decoder
7044 complications. */
848930b2
JB		 7045 if (!(i.base_reg->reg_flags & RegRex)
7046 && (i.base_reg->reg_num == EBP_REG_NUM
7047 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 7048 default_seg = &ss;
848930b2 7049 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 7050 {
848930b2 7051 fake_zero_displacement = 1;
b5014f7a 7052 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 7053 }
7054 i.sib.scale = i.log2_scale_factor;
7055 if (i.index_reg == 0)
7056 {
6c30d220 7057 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 7058 /* <disp>(%esp) becomes two byte modrm with no index
7059 register. We've already stored the code for esp
7060 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7061 Any base register besides %esp will not use the
7062 extra modrm byte. */
7063 i.sib.index = NO_INDEX_REGISTER;
29b0f896 7064 }
6c30d220 7065 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 7066 {
db51cc60
L		 7067 if (i.index_reg->reg_num == RegEiz
7068 || i.index_reg->reg_num == RegRiz)
7069 i.sib.index = NO_INDEX_REGISTER;
7070 else
7071 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 7072 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7073 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 7074 i.rex |= REX_X;
29b0f896 7075 }
67a4f2b7
AO		 7076
7077 if (i.disp_operands
7078 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7079 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7080 i.rm.mode = 0;
7081 else
a501d77e
L		 7082 {
7083 if (!fake_zero_displacement
7084 && !i.disp_operands
7085 && i.disp_encoding)
7086 {
7087 fake_zero_displacement = 1;
7088 if (i.disp_encoding == disp_encoding_8bit)
7089 i.types[op].bitfield.disp8 = 1;
7090 else
7091 i.types[op].bitfield.disp32 = 1;
7092 }
7093 i.rm.mode = mode_from_disp_size (i.types[op]);
7094 }
29b0f896 7095 }
252b5132 7096
29b0f896
AM		 7097 if (fake_zero_displacement)
7098 {
7099 /* Fakes a zero displacement assuming that i.types[op]
7100 holds the correct displacement size. */
7101 expressionS *exp;
7102
9c2799c2 7103 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 7104 exp = &disp_expressions[i.disp_operands++];
7105 i.op[op].disps = exp;
7106 exp->X_op = O_constant;
7107 exp->X_add_number = 0;
7108 exp->X_add_symbol = (symbolS *) 0;
7109 exp->X_op_symbol = (symbolS *) 0;
7110 }
c0f3af97
L		 7111
7112 mem = op;
29b0f896 7113 }
c0f3af97
L		 7114 else
7115 mem = ~0;
252b5132 7116
8c43a48b 7117 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 7118 {
7119 if (operand_type_check (i.types[0], imm))
7120 i.vex.register_specifier = NULL;
7121 else
7122 {
7123 /* VEX.vvvv encodes one of the sources when the first
7124 operand is not an immediate. */
1ef99a7b 7125 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 7126 i.vex.register_specifier = i.op[0].regs;
7127 else
7128 i.vex.register_specifier = i.op[1].regs;
7129 }
7130
7131 /* Destination is a XMM register encoded in the ModRM.reg
7132 and VEX.R bit. */
7133 i.rm.reg = i.op[2].regs->reg_num;
7134 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7135 i.rex |= REX_R;
7136
7137 /* ModRM.rm and VEX.B encodes the other source. */
7138 if (!i.mem_operands)
7139 {
7140 i.rm.mode = 3;
7141
1ef99a7b 7142 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 7143 i.rm.regmem = i.op[1].regs->reg_num;
7144 else
7145 i.rm.regmem = i.op[0].regs->reg_num;
7146
7147 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7148 i.rex |= REX_B;
7149 }
7150 }
2426c15f 7151 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 7152 {
7153 i.vex.register_specifier = i.op[2].regs;
7154 if (!i.mem_operands)
7155 {
7156 i.rm.mode = 3;
7157 i.rm.regmem = i.op[1].regs->reg_num;
7158 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7159 i.rex |= REX_B;
7160 }
7161 }
29b0f896
AM		 7162 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7163 (if any) based on i.tm.extension_opcode. Again, we must be
7164 careful to make sure that segment/control/debug/test/MMX
7165 registers are coded into the i.rm.reg field. */
f88c9eb0 7166 else if (i.reg_operands)
29b0f896 7167 {
99018f42 7168 unsigned int op;
7ab9ffdd
L		 7169 unsigned int vex_reg = ~0;
7170
7171 for (op = 0; op < i.operands; op++)
dc821c5f 7172 if (i.types[op].bitfield.reg
7ab9ffdd 7173 || i.types[op].bitfield.regmmx
1b54b8d7 7174 || i.types[op].bitfield.regsimd
7e8b059b 7175 || i.types[op].bitfield.regbnd
43234a1e 7176 || i.types[op].bitfield.regmask
7ab9ffdd
L		 7177 || i.types[op].bitfield.sreg2
7178 || i.types[op].bitfield.sreg3
7179 || i.types[op].bitfield.control
7180 || i.types[op].bitfield.debug
7181 || i.types[op].bitfield.test)
7182 break;
c0209578 7183
7ab9ffdd
L		 7184 if (vex_3_sources)
7185 op = dest;
2426c15f 7186 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 7187 {
7188 /* For instructions with VexNDS, the register-only
7189 source operand is encoded in VEX prefix. */
7190 gas_assert (mem != (unsigned int) ~0);
c0f3af97 7191
7ab9ffdd 7192 if (op > mem)
c0f3af97 7193 {
7ab9ffdd
L		 7194 vex_reg = op++;
7195 gas_assert (op < i.operands);
c0f3af97
L		 7196 }
7197 else
c0f3af97 7198 {
f12dc422
L		 7199 /* Check register-only source operand when two source
7200 operands are swapped. */
7201 if (!i.tm.operand_types[op].bitfield.baseindex
7202 && i.tm.operand_types[op + 1].bitfield.baseindex)
7203 {
7204 vex_reg = op;
7205 op += 2;
7206 gas_assert (mem == (vex_reg + 1)
7207 && op < i.operands);
7208 }
7209 else
7210 {
7211 vex_reg = op + 1;
7212 gas_assert (vex_reg < i.operands);
7213 }
c0f3af97 7214 }
7ab9ffdd 7215 }
2426c15f 7216 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 7217 {
f12dc422 7218 /* For instructions with VexNDD, the register destination
7ab9ffdd 7219 is encoded in VEX prefix. */
f12dc422
L		 7220 if (i.mem_operands == 0)
7221 {
7222 /* There is no memory operand. */
7223 gas_assert ((op + 2) == i.operands);
7224 vex_reg = op + 1;
7225 }
7226 else
8d63c93e 7227 {
ed438a93
JB		 7228 /* There are only 2 non-immediate operands. */
7229 gas_assert (op < i.imm_operands + 2
7230 && i.operands == i.imm_operands + 2);
7231 vex_reg = i.imm_operands + 1;
f12dc422 7232 }
7ab9ffdd
L		 7233 }
7234 else
7235 gas_assert (op < i.operands);
99018f42 7236
7ab9ffdd
L		 7237 if (vex_reg != (unsigned int) ~0)
7238 {
f12dc422 7239 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 7240
dc821c5f
JB		 7241 if ((!type->bitfield.reg
7242 || (!type->bitfield.dword && !type->bitfield.qword))
10c17abd 7243 && !type->bitfield.regsimd
43234a1e 7244 && !operand_type_equal (type, &regmask))
7ab9ffdd 7245 abort ();
f88c9eb0 7246
7ab9ffdd
L		 7247 i.vex.register_specifier = i.op[vex_reg].regs;
7248 }
7249
1b9f0c97
L		 7250 /* Don't set OP operand twice. */
7251 if (vex_reg != op)
7ab9ffdd 7252 {
1b9f0c97
L		 7253 /* If there is an extension opcode to put here, the
7254 register number must be put into the regmem field. */
7255 if (i.tm.extension_opcode != None)
7256 {
7257 i.rm.regmem = i.op[op].regs->reg_num;
7258 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7259 i.rex |= REX_B;
43234a1e
L		 7260 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7261 i.vrex |= REX_B;
1b9f0c97
L		 7262 }
7263 else
7264 {
7265 i.rm.reg = i.op[op].regs->reg_num;
7266 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7267 i.rex |= REX_R;
43234a1e
L		 7268 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7269 i.vrex |= REX_R;
1b9f0c97 7270 }
7ab9ffdd 7271 }
252b5132 7272
29b0f896
AM		 7273 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7274 must set it to 3 to indicate this is a register operand
7275 in the regmem field. */
7276 if (!i.mem_operands)
7277 i.rm.mode = 3;
7278 }
252b5132 7279
29b0f896 7280 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 7281 if (i.tm.extension_opcode != None)
29b0f896
AM		 7282 i.rm.reg = i.tm.extension_opcode;
7283 }
7284 return default_seg;
7285}
252b5132 7286
29b0f896 7287static void
e3bb37b5 7288output_branch (void)
29b0f896
AM		 7289{
7290 char *p;
f8a5c266 7291 int size;
29b0f896
AM		 7292 int code16;
7293 int prefix;
7294 relax_substateT subtype;
7295 symbolS *sym;
7296 offsetT off;
7297
f8a5c266 7298 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 7299 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 7300
7301 prefix = 0;
7302 if (i.prefix[DATA_PREFIX] != 0)
252b5132 7303 {
29b0f896
AM		 7304 prefix = 1;
7305 i.prefixes -= 1;
7306 code16 ^= CODE16;
252b5132 7307 }
29b0f896
AM		 7308 /* Pentium4 branch hints. */
7309 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7310 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 7311 {
29b0f896
AM		 7312 prefix++;
7313 i.prefixes--;
7314 }
7315 if (i.prefix[REX_PREFIX] != 0)
7316 {
7317 prefix++;
7318 i.prefixes--;
2f66722d
AM		 7319 }
7320
7e8b059b
L		 7321 /* BND prefixed jump. */
7322 if (i.prefix[BND_PREFIX] != 0)
7323 {
7324 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7325 i.prefixes -= 1;
7326 }
7327
29b0f896
AM		 7328 if (i.prefixes != 0 && !intel_syntax)
7329 as_warn (_("skipping prefixes on this instruction"));
7330
7331 /* It's always a symbol; End frag & setup for relax.
7332 Make sure there is enough room in this frag for the largest
7333 instruction we may generate in md_convert_frag. This is 2
7334 bytes for the opcode and room for the prefix and largest
7335 displacement. */
7336 frag_grow (prefix + 2 + 4);
7337 /* Prefix and 1 opcode byte go in fr_fix. */
7338 p = frag_more (prefix + 1);
7339 if (i.prefix[DATA_PREFIX] != 0)
7340 *p++ = DATA_PREFIX_OPCODE;
7341 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7342 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7343 *p++ = i.prefix[SEG_PREFIX];
7344 if (i.prefix[REX_PREFIX] != 0)
7345 *p++ = i.prefix[REX_PREFIX];
7346 *p = i.tm.base_opcode;
7347
7348 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 7349 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 7350 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 7351 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 7352 else
f8a5c266 7353 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 7354 subtype |= code16;
3e73aa7c 7355
29b0f896
AM		 7356 sym = i.op[0].disps->X_add_symbol;
7357 off = i.op[0].disps->X_add_number;
3e73aa7c 7358
29b0f896
AM		 7359 if (i.op[0].disps->X_op != O_constant
7360 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 7361 {
29b0f896
AM		 7362 /* Handle complex expressions. */
7363 sym = make_expr_symbol (i.op[0].disps);
7364 off = 0;
7365 }
3e73aa7c 7366
29b0f896
AM		 7367 /* 1 possible extra opcode + 4 byte displacement go in var part.
7368 Pass reloc in fr_var. */
d258b828 7369 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 7370}
3e73aa7c 7371
bd7ab16b
L		 7372#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7373/* Return TRUE iff PLT32 relocation should be used for branching to
7374 symbol S. */
7375
7376static bfd_boolean
7377need_plt32_p (symbolS *s)
7378{
7379 /* PLT32 relocation is ELF only. */
7380 if (!IS_ELF)
7381 return FALSE;
7382
7383 /* Since there is no need to prepare for PLT branch on x86-64, we
7384 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7385 be used as a marker for 32-bit PC-relative branches. */
7386 if (!object_64bit)
7387 return FALSE;
7388
7389 /* Weak or undefined symbol need PLT32 relocation. */
7390 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7391 return TRUE;
7392
7393 /* Non-global symbol doesn't need PLT32 relocation. */
7394 if (! S_IS_EXTERNAL (s))
7395 return FALSE;
7396
7397 /* Other global symbols need PLT32 relocation. NB: Symbol with
7398 non-default visibilities are treated as normal global symbol
7399 so that PLT32 relocation can be used as a marker for 32-bit
7400 PC-relative branches. It is useful for linker relaxation. */
7401 return TRUE;
7402}
7403#endif
7404
29b0f896 7405static void
e3bb37b5 7406output_jump (void)
29b0f896
AM		 7407{
7408 char *p;
7409 int size;
3e02c1cc 7410 fixS *fixP;
bd7ab16b 7411 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
29b0f896 7412
40fb9820 7413 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 7414 {
7415 /* This is a loop or jecxz type instruction. */
7416 size = 1;
7417 if (i.prefix[ADDR_PREFIX] != 0)
7418 {
7419 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7420 i.prefixes -= 1;
7421 }
7422 /* Pentium4 branch hints. */
7423 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7424 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7425 {
7426 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7427 i.prefixes--;
3e73aa7c
JH		 7428 }
7429 }
29b0f896
AM		 7430 else
7431 {
7432 int code16;
3e73aa7c 7433
29b0f896
AM		 7434 code16 = 0;
7435 if (flag_code == CODE_16BIT)
7436 code16 = CODE16;
3e73aa7c 7437
29b0f896
AM		 7438 if (i.prefix[DATA_PREFIX] != 0)
7439 {
7440 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7441 i.prefixes -= 1;
7442 code16 ^= CODE16;
7443 }
252b5132 7444
29b0f896
AM		 7445 size = 4;
7446 if (code16)
7447 size = 2;
7448 }
9fcc94b6 7449
29b0f896
AM		 7450 if (i.prefix[REX_PREFIX] != 0)
7451 {
7452 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7453 i.prefixes -= 1;
7454 }
252b5132 7455
7e8b059b
L		 7456 /* BND prefixed jump. */
7457 if (i.prefix[BND_PREFIX] != 0)
7458 {
7459 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7460 i.prefixes -= 1;
7461 }
7462
29b0f896
AM		 7463 if (i.prefixes != 0 && !intel_syntax)
7464 as_warn (_("skipping prefixes on this instruction"));
e0890092 7465
42164a71
L		 7466 p = frag_more (i.tm.opcode_length + size);
7467 switch (i.tm.opcode_length)
7468 {
7469 case 2:
7470 *p++ = i.tm.base_opcode >> 8;
1a0670f3 7471 /* Fall through. */
42164a71
L		 7472 case 1:
7473 *p++ = i.tm.base_opcode;
7474 break;
7475 default:
7476 abort ();
7477 }
e0890092 7478
bd7ab16b
L		 7479#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7480 if (size == 4
7481 && jump_reloc == NO_RELOC
7482 && need_plt32_p (i.op[0].disps->X_add_symbol))
7483 jump_reloc = BFD_RELOC_X86_64_PLT32;
7484#endif
7485
7486 jump_reloc = reloc (size, 1, 1, jump_reloc);
7487
3e02c1cc 7488 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
bd7ab16b 7489 i.op[0].disps, 1, jump_reloc);
3e02c1cc
AM		 7490
7491 /* All jumps handled here are signed, but don't use a signed limit
7492 check for 32 and 16 bit jumps as we want to allow wrap around at
7493 4G and 64k respectively. */
7494 if (size == 1)
7495 fixP->fx_signed = 1;
29b0f896 7496}
e0890092 7497
29b0f896 7498static void
e3bb37b5 7499output_interseg_jump (void)
29b0f896
AM		 7500{
7501 char *p;
7502 int size;
7503 int prefix;
7504 int code16;
252b5132 7505
29b0f896
AM		 7506 code16 = 0;
7507 if (flag_code == CODE_16BIT)
7508 code16 = CODE16;
a217f122 7509
29b0f896
AM		 7510 prefix = 0;
7511 if (i.prefix[DATA_PREFIX] != 0)
7512 {
7513 prefix = 1;
7514 i.prefixes -= 1;
7515 code16 ^= CODE16;
7516 }
7517 if (i.prefix[REX_PREFIX] != 0)
7518 {
7519 prefix++;
7520 i.prefixes -= 1;
7521 }
252b5132 7522
29b0f896
AM		 7523 size = 4;
7524 if (code16)
7525 size = 2;
252b5132 7526
29b0f896
AM		 7527 if (i.prefixes != 0 && !intel_syntax)
7528 as_warn (_("skipping prefixes on this instruction"));
252b5132 7529
29b0f896
AM		 7530 /* 1 opcode; 2 segment; offset */
7531 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 7532
29b0f896
AM		 7533 if (i.prefix[DATA_PREFIX] != 0)
7534 *p++ = DATA_PREFIX_OPCODE;
252b5132 7535
29b0f896
AM		 7536 if (i.prefix[REX_PREFIX] != 0)
7537 *p++ = i.prefix[REX_PREFIX];
252b5132 7538
29b0f896
AM		 7539 *p++ = i.tm.base_opcode;
7540 if (i.op[1].imms->X_op == O_constant)
7541 {
7542 offsetT n = i.op[1].imms->X_add_number;
252b5132 7543
29b0f896
AM		 7544 if (size == 2
7545 && !fits_in_unsigned_word (n)
7546 && !fits_in_signed_word (n))
7547 {
7548 as_bad (_("16-bit jump out of range"));
7549 return;
7550 }
7551 md_number_to_chars (p, n, size);
7552 }
7553 else
7554 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7555 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 7556 if (i.op[0].imms->X_op != O_constant)
7557 as_bad (_("can't handle non absolute segment in `%s'"),
7558 i.tm.name);
7559 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7560}
a217f122 7561
29b0f896 7562static void
e3bb37b5 7563output_insn (void)
29b0f896 7564{
2bbd9c25
JJ		 7565 fragS *insn_start_frag;
7566 offsetT insn_start_off;
7567
29b0f896
AM		 7568 /* Tie dwarf2 debug info to the address at the start of the insn.
7569 We can't do this after the insn has been output as the current
7570 frag may have been closed off. eg. by frag_var. */
7571 dwarf2_emit_insn (0);
7572
2bbd9c25
JJ		 7573 insn_start_frag = frag_now;
7574 insn_start_off = frag_now_fix ();
7575
29b0f896 7576 /* Output jumps. */
40fb9820 7577 if (i.tm.opcode_modifier.jump)
29b0f896 7578 output_branch ();
40fb9820
L		 7579 else if (i.tm.opcode_modifier.jumpbyte
7580 || i.tm.opcode_modifier.jumpdword)
29b0f896 7581 output_jump ();
40fb9820 7582 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7583 output_interseg_jump ();
7584 else
7585 {
7586 /* Output normal instructions here. */
7587 char *p;
7588 unsigned char *q;
47465058 7589 unsigned int j;
331d2d0d 7590 unsigned int prefix;
4dffcebc 7591
e4e00185
AS		 7592 if (avoid_fence
7593 && i.tm.base_opcode == 0xfae
7594 && i.operands == 1
7595 && i.imm_operands == 1
7596 && (i.op[0].imms->X_add_number == 0xe8
7597 || i.op[0].imms->X_add_number == 0xf0
7598 || i.op[0].imms->X_add_number == 0xf8))
7599 {
7600 /* Encode lfence, mfence, and sfence as
7601 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7602 offsetT val = 0x240483f0ULL;
7603 p = frag_more (5);
7604 md_number_to_chars (p, val, 5);
7605 return;
7606 }
7607
d022bddd
IT		 7608 /* Some processors fail on LOCK prefix. This options makes
7609 assembler ignore LOCK prefix and serves as a workaround. */
7610 if (omit_lock_prefix)
7611 {
7612 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7613 return;
7614 i.prefix[LOCK_PREFIX] = 0;
7615 }
7616
43234a1e
L		 7617 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7618 don't need the explicit prefix. */
7619 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7620 {
c0f3af97 7621 switch (i.tm.opcode_length)
bc4bd9ab 7622 {
c0f3af97
L		 7623 case 3:
7624 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7625 {
c0f3af97
L		 7626 prefix = (i.tm.base_opcode >> 24) & 0xff;
7627 goto check_prefix;
7628 }
7629 break;
7630 case 2:
7631 if ((i.tm.base_opcode & 0xff0000) != 0)
7632 {
7633 prefix = (i.tm.base_opcode >> 16) & 0xff;
7634 if (i.tm.cpu_flags.bitfield.cpupadlock)
7635 {
4dffcebc 7636check_prefix:
c0f3af97 7637 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 7638 || (i.prefix[REP_PREFIX]
c0f3af97
L		 7639 != REPE_PREFIX_OPCODE))
7640 add_prefix (prefix);
7641 }
7642 else
4dffcebc
L		 7643 add_prefix (prefix);
7644 }
c0f3af97
L		 7645 break;
7646 case 1:
7647 break;
390c91cf
L		 7648 case 0:
7649 /* Check for pseudo prefixes. */
7650 as_bad_where (insn_start_frag->fr_file,
7651 insn_start_frag->fr_line,
7652 _("pseudo prefix without instruction"));
7653 return;
c0f3af97
L		 7654 default:
7655 abort ();
bc4bd9ab 7656 }
c0f3af97 7657
6d19a37a 7658#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7659 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7660 R_X86_64_GOTTPOFF relocation so that linker can safely
7661 perform IE->LE optimization. */
7662 if (x86_elf_abi == X86_64_X32_ABI
7663 && i.operands == 2
7664 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7665 && i.prefix[REX_PREFIX] == 0)
7666 add_prefix (REX_OPCODE);
6d19a37a 7667#endif
cf61b747 7668
c0f3af97
L		 7669 /* The prefix bytes. */
7670 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7671 if (*q)
7672 FRAG_APPEND_1_CHAR (*q);
0f10071e 7673 }
ae5c1c7b 7674 else
c0f3af97
L		 7675 {
7676 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7677 if (*q)
7678 switch (j)
7679 {
7680 case REX_PREFIX:
7681 /* REX byte is encoded in VEX prefix. */
7682 break;
7683 case SEG_PREFIX:
7684 case ADDR_PREFIX:
7685 FRAG_APPEND_1_CHAR (*q);
7686 break;
7687 default:
7688 /* There should be no other prefixes for instructions
7689 with VEX prefix. */
7690 abort ();
7691 }
7692
43234a1e
L		 7693 /* For EVEX instructions i.vrex should become 0 after
7694 build_evex_prefix. For VEX instructions upper 16 registers
7695 aren't available, so VREX should be 0. */
7696 if (i.vrex)
7697 abort ();
c0f3af97
L		 7698 /* Now the VEX prefix. */
7699 p = frag_more (i.vex.length);
7700 for (j = 0; j < i.vex.length; j++)
7701 p[j] = i.vex.bytes[j];
7702 }
252b5132 7703
29b0f896 7704 /* Now the opcode; be careful about word order here! */
4dffcebc 7705 if (i.tm.opcode_length == 1)
29b0f896
AM		 7706 {
7707 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7708 }
7709 else
7710 {
4dffcebc 7711 switch (i.tm.opcode_length)
331d2d0d 7712 {
43234a1e
L		 7713 case 4:
7714 p = frag_more (4);
7715 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7716 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7717 break;
4dffcebc 7718 case 3:
331d2d0d
L		 7719 p = frag_more (3);
7720 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7721 break;
7722 case 2:
7723 p = frag_more (2);
7724 break;
7725 default:
7726 abort ();
7727 break;
331d2d0d 7728 }
0f10071e 7729
29b0f896
AM		 7730 /* Put out high byte first: can't use md_number_to_chars! */
7731 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7732 *p = i.tm.base_opcode & 0xff;
7733 }
3e73aa7c 7734
29b0f896 7735 /* Now the modrm byte and sib byte (if present). */
40fb9820 7736 if (i.tm.opcode_modifier.modrm)
29b0f896 7737 {
4a3523fa
L		 7738 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7739 | i.rm.reg << 3
7740 | i.rm.mode << 6));
29b0f896
AM		 7741 /* If i.rm.regmem == ESP (4)
7742 && i.rm.mode != (Register mode)
7743 && not 16 bit
7744 ==> need second modrm byte. */
7745 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7746 && i.rm.mode != 3
dc821c5f 7747 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
4a3523fa
L		 7748 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7749 | i.sib.index << 3
7750 | i.sib.scale << 6));
29b0f896 7751 }
3e73aa7c 7752
29b0f896 7753 if (i.disp_operands)
2bbd9c25 7754 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7755
29b0f896 7756 if (i.imm_operands)
2bbd9c25 7757 output_imm (insn_start_frag, insn_start_off);
29b0f896 7758 }
252b5132 7759
29b0f896
AM		 7760#ifdef DEBUG386
7761 if (flag_debug)
7762 {
7b81dfbb 7763 pi ("" /*line*/, &i);
29b0f896
AM		 7764 }
7765#endif /* DEBUG386 */
7766}
252b5132 7767
e205caa7
L		 7768/* Return the size of the displacement operand N. */
7769
7770static int
7771disp_size (unsigned int n)
7772{
7773 int size = 4;
43234a1e 7774
b5014f7a 7775 if (i.types[n].bitfield.disp64)
40fb9820
L		 7776 size = 8;
7777 else if (i.types[n].bitfield.disp8)
7778 size = 1;
7779 else if (i.types[n].bitfield.disp16)
7780 size = 2;
e205caa7
L		 7781 return size;
7782}
7783
7784/* Return the size of the immediate operand N. */
7785
7786static int
7787imm_size (unsigned int n)
7788{
7789 int size = 4;
40fb9820
L		 7790 if (i.types[n].bitfield.imm64)
7791 size = 8;
7792 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7793 size = 1;
7794 else if (i.types[n].bitfield.imm16)
7795 size = 2;
e205caa7
L		 7796 return size;
7797}
7798
29b0f896 7799static void
64e74474 7800output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7801{
7802 char *p;
7803 unsigned int n;
252b5132 7804
29b0f896
AM		 7805 for (n = 0; n < i.operands; n++)
7806 {
b5014f7a 7807 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 7808 {
7809 if (i.op[n].disps->X_op == O_constant)
7810 {
e205caa7 7811 int size = disp_size (n);
43234a1e 7812 offsetT val = i.op[n].disps->X_add_number;
252b5132 7813
b5014f7a 7814 val = offset_in_range (val >> i.memshift, size);
29b0f896
AM		 7815 p = frag_more (size);
7816 md_number_to_chars (p, val, size);
7817 }
7818 else
7819 {
f86103b7 7820 enum bfd_reloc_code_real reloc_type;
e205caa7 7821 int size = disp_size (n);
40fb9820 7822 int sign = i.types[n].bitfield.disp32s;
29b0f896 7823 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7824 fixS *fixP;
29b0f896 7825
e205caa7 7826 /* We can't have 8 bit displacement here. */
9c2799c2 7827 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7828
29b0f896
AM		 7829 /* The PC relative address is computed relative
7830 to the instruction boundary, so in case immediate
7831 fields follows, we need to adjust the value. */
7832 if (pcrel && i.imm_operands)
7833 {
29b0f896 7834 unsigned int n1;
e205caa7 7835 int sz = 0;
252b5132 7836
29b0f896 7837 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7838 if (operand_type_check (i.types[n1], imm))
252b5132 7839 {
e205caa7
L		 7840 /* Only one immediate is allowed for PC
7841 relative address. */
9c2799c2 7842 gas_assert (sz == 0);
e205caa7
L		 7843 sz = imm_size (n1);
7844 i.op[n].disps->X_add_number -= sz;
252b5132 7845 }
29b0f896 7846 /* We should find the immediate. */
9c2799c2 7847 gas_assert (sz != 0);
29b0f896 7848 }
520dc8e8 7849
29b0f896 7850 p = frag_more (size);
d258b828 7851 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7852 if (GOT_symbol
2bbd9c25 7853 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7854 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7855 || reloc_type == BFD_RELOC_X86_64_32S
7856 || (reloc_type == BFD_RELOC_64
7857 && object_64bit))
d6ab8113
JB		 7858 && (i.op[n].disps->X_op == O_symbol
7859 || (i.op[n].disps->X_op == O_add
7860 && ((symbol_get_value_expression
7861 (i.op[n].disps->X_op_symbol)->X_op)
7862 == O_subtract))))
7863 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7864 {
7865 offsetT add;
7866
7867 if (insn_start_frag == frag_now)
7868 add = (p - frag_now->fr_literal) - insn_start_off;
7869 else
7870 {
7871 fragS *fr;
7872
7873 add = insn_start_frag->fr_fix - insn_start_off;
7874 for (fr = insn_start_frag->fr_next;
7875 fr && fr != frag_now; fr = fr->fr_next)
7876 add += fr->fr_fix;
7877 add += p - frag_now->fr_literal;
7878 }
7879
4fa24527 7880 if (!object_64bit)
7b81dfbb
AJ		 7881 {
7882 reloc_type = BFD_RELOC_386_GOTPC;
7883 i.op[n].imms->X_add_number += add;
7884 }
7885 else if (reloc_type == BFD_RELOC_64)
7886 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7887 else
7b81dfbb
AJ		 7888 /* Don't do the adjustment for x86-64, as there
7889 the pcrel addressing is relative to the _next_
7890 insn, and that is taken care of in other code. */
d6ab8113 7891 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7892 }
02a86693
L		 7893 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7894 size, i.op[n].disps, pcrel,
7895 reloc_type);
7896 /* Check for "call/jmp *mem", "mov mem, %reg",
7897 "test %reg, mem" and "binop mem, %reg" where binop
7898 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 7899 instructions. Always generate R_386_GOT32X for
7900 "sym*GOT" operand in 32-bit mode. */
7901 if ((generate_relax_relocations
7902 || (!object_64bit
7903 && i.rm.mode == 0
7904 && i.rm.regmem == 5))
7905 && (i.rm.mode == 2
7906 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 7907 && ((i.operands == 1
7908 && i.tm.base_opcode == 0xff
7909 && (i.rm.reg == 2 || i.rm.reg == 4))
7910 || (i.operands == 2
7911 && (i.tm.base_opcode == 0x8b
7912 || i.tm.base_opcode == 0x85
7913 || (i.tm.base_opcode & 0xc7) == 0x03))))
7914 {
7915 if (object_64bit)
7916 {
7917 fixP->fx_tcbit = i.rex != 0;
7918 if (i.base_reg
7919 && (i.base_reg->reg_num == RegRip
7920 || i.base_reg->reg_num == RegEip))
7921 fixP->fx_tcbit2 = 1;
7922 }
7923 else
7924 fixP->fx_tcbit2 = 1;
7925 }
29b0f896
AM		 7926 }
7927 }
7928 }
7929}
252b5132 7930
29b0f896 7931static void
64e74474 7932output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7933{
7934 char *p;
7935 unsigned int n;
252b5132 7936
29b0f896
AM		 7937 for (n = 0; n < i.operands; n++)
7938 {
43234a1e
L		 7939 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7940 if (i.rounding && (int) n == i.rounding->operand)
7941 continue;
7942
40fb9820 7943 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7944 {
7945 if (i.op[n].imms->X_op == O_constant)
7946 {
e205caa7 7947 int size = imm_size (n);
29b0f896 7948 offsetT val;
b4cac588 7949
29b0f896
AM		 7950 val = offset_in_range (i.op[n].imms->X_add_number,
7951 size);
7952 p = frag_more (size);
7953 md_number_to_chars (p, val, size);
7954 }
7955 else
7956 {
7957 /* Not absolute_section.
7958 Need a 32-bit fixup (don't support 8bit
7959 non-absolute imms). Try to support other
7960 sizes ... */
f86103b7 7961 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7962 int size = imm_size (n);
7963 int sign;
29b0f896 7964
40fb9820 7965 if (i.types[n].bitfield.imm32s
a7d61044 7966 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7967 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7968 sign = 1;
e205caa7
L		 7969 else
7970 sign = 0;
520dc8e8 7971
29b0f896 7972 p = frag_more (size);
d258b828 7973 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7974
2bbd9c25
JJ		 7975 /* This is tough to explain. We end up with this one if we
7976 * have operands that look like
7977 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7978 * obtain the absolute address of the GOT, and it is strongly
7979 * preferable from a performance point of view to avoid using
7980 * a runtime relocation for this. The actual sequence of
7981 * instructions often look something like:
7982 *
7983 * call .L66
7984 * .L66:
7985 * popl %ebx
7986 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7987 *
7988 * The call and pop essentially return the absolute address
7989 * of the label .L66 and store it in %ebx. The linker itself
7990 * will ultimately change the first operand of the addl so
7991 * that %ebx points to the GOT, but to keep things simple, the
7992 * .o file must have this operand set so that it generates not
7993 * the absolute address of .L66, but the absolute address of
7994 * itself. This allows the linker itself simply treat a GOTPC
7995 * relocation as asking for a pcrel offset to the GOT to be
7996 * added in, and the addend of the relocation is stored in the
7997 * operand field for the instruction itself.
7998 *
7999 * Our job here is to fix the operand so that it would add
8000 * the correct offset so that %ebx would point to itself. The
8001 * thing that is tricky is that .-.L66 will point to the
8002 * beginning of the instruction, so we need to further modify
8003 * the operand so that it will point to itself. There are
8004 * other cases where you have something like:
8005 *
8006 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8007 *
8008 * and here no correction would be required. Internally in
8009 * the assembler we treat operands of this form as not being
8010 * pcrel since the '.' is explicitly mentioned, and I wonder
8011 * whether it would simplify matters to do it this way. Who
8012 * knows. In earlier versions of the PIC patches, the
8013 * pcrel_adjust field was used to store the correction, but
8014 * since the expression is not pcrel, I felt it would be
8015 * confusing to do it this way. */
8016
d6ab8113 8017 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 8018 || reloc_type == BFD_RELOC_X86_64_32S
8019 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 8020 && GOT_symbol
8021 && GOT_symbol == i.op[n].imms->X_add_symbol
8022 && (i.op[n].imms->X_op == O_symbol
8023 || (i.op[n].imms->X_op == O_add
8024 && ((symbol_get_value_expression
8025 (i.op[n].imms->X_op_symbol)->X_op)
8026 == O_subtract))))
8027 {
2bbd9c25
JJ		 8028 offsetT add;
8029
8030 if (insn_start_frag == frag_now)
8031 add = (p - frag_now->fr_literal) - insn_start_off;
8032 else
8033 {
8034 fragS *fr;
8035
8036 add = insn_start_frag->fr_fix - insn_start_off;
8037 for (fr = insn_start_frag->fr_next;
8038 fr && fr != frag_now; fr = fr->fr_next)
8039 add += fr->fr_fix;
8040 add += p - frag_now->fr_literal;
8041 }
8042
4fa24527 8043 if (!object_64bit)
d6ab8113 8044 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 8045 else if (size == 4)
d6ab8113 8046 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 8047 else if (size == 8)
8048 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 8049 i.op[n].imms->X_add_number += add;
29b0f896 8050 }
29b0f896
AM		 8051 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8052 i.op[n].imms, 0, reloc_type);
8053 }
8054 }
8055 }
252b5132
RH		 8056}
8057\f
d182319b
JB		 8058/* x86_cons_fix_new is called via the expression parsing code when a
8059 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 8060static int cons_sign = -1;
8061
8062void
e3bb37b5 8063x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 8064 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 8065{
d258b828 8066 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 8067
8068#ifdef TE_PE
8069 if (exp->X_op == O_secrel)
8070 {
8071 exp->X_op = O_symbol;
8072 r = BFD_RELOC_32_SECREL;
8073 }
8074#endif
8075
8076 fix_new_exp (frag, off, len, exp, 0, r);
8077}
8078
357d1bd8
L		 8079/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8080 purpose of the `.dc.a' internal pseudo-op. */
8081
8082int
8083x86_address_bytes (void)
8084{
8085 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8086 return 4;
8087 return stdoutput->arch_info->bits_per_address / 8;
8088}
8089
d382c579
TG		 8090#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8091 || defined (LEX_AT)
d258b828 8092# define lex_got(reloc, adjust, types) NULL
718ddfc0 8093#else
f3c180ae
AM		 8094/* Parse operands of the form
8095 <symbol>@GOTOFF+<nnn>
8096 and similar .plt or .got references.
8097
8098 If we find one, set up the correct relocation in RELOC and copy the
8099 input string, minus the `@GOTOFF' into a malloc'd buffer for
8100 parsing by the calling routine. Return this buffer, and if ADJUST
8101 is non-null set it to the length of the string we removed from the
8102 input line. Otherwise return NULL. */
8103static char *
91d6fa6a 8104lex_got (enum bfd_reloc_code_real *rel,
64e74474 8105 int *adjust,
d258b828 8106 i386_operand_type *types)
f3c180ae 8107{
7b81dfbb
AJ		 8108 /* Some of the relocations depend on the size of what field is to
8109 be relocated. But in our callers i386_immediate and i386_displacement
8110 we don't yet know the operand size (this will be set by insn
8111 matching). Hence we record the word32 relocation here,
8112 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 8113 static const struct {
8114 const char *str;
cff8d58a 8115 int len;
4fa24527 8116 const enum bfd_reloc_code_real rel[2];
40fb9820 8117 const i386_operand_type types64;
f3c180ae 8118 } gotrel[] = {
8ce3d284 8119#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 8120 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8121 BFD_RELOC_SIZE32 },
8122 OPERAND_TYPE_IMM32_64 },
8ce3d284 8123#endif
cff8d58a
L		 8124 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8125 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 8126 OPERAND_TYPE_IMM64 },
cff8d58a
L		 8127 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8128 BFD_RELOC_X86_64_PLT32 },
40fb9820 8129 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8130 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8131 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 8132 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 8133 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8134 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 8135 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 8136 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8137 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 8138 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8139 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8140 BFD_RELOC_X86_64_TLSGD },
40fb9820 8141 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8142 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8143 _dummy_first_bfd_reloc_code_real },
40fb9820 8144 OPERAND_TYPE_NONE },
cff8d58a
L		 8145 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8146 BFD_RELOC_X86_64_TLSLD },
40fb9820 8147 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8148 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8149 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 8150 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8151 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8152 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 8153 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 8154 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8155 _dummy_first_bfd_reloc_code_real },
40fb9820 8156 OPERAND_TYPE_NONE },
cff8d58a
L		 8157 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8158 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 8159 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 8160 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8161 _dummy_first_bfd_reloc_code_real },
40fb9820 8162 OPERAND_TYPE_NONE },
cff8d58a
L		 8163 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8164 _dummy_first_bfd_reloc_code_real },
40fb9820 8165 OPERAND_TYPE_NONE },
cff8d58a
L		 8166 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8167 BFD_RELOC_X86_64_GOT32 },
40fb9820 8168 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 8169 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8170 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 8171 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8172 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8173 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 8174 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 8175 };
8176 char *cp;
8177 unsigned int j;
8178
d382c579 8179#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 8180 if (!IS_ELF)
8181 return NULL;
d382c579 8182#endif
718ddfc0 8183
f3c180ae 8184 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 8185 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 8186 return NULL;
8187
47465058 8188 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 8189 {
cff8d58a 8190 int len = gotrel[j].len;
28f81592 8191 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 8192 {
4fa24527 8193 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 8194 {
28f81592
AM		 8195 int first, second;
8196 char *tmpbuf, *past_reloc;
f3c180ae 8197
91d6fa6a 8198 *rel = gotrel[j].rel[object_64bit];
f3c180ae 8199
3956db08
JB		 8200 if (types)
8201 {
8202 if (flag_code != CODE_64BIT)
40fb9820
L		 8203 {
8204 types->bitfield.imm32 = 1;
8205 types->bitfield.disp32 = 1;
8206 }
3956db08
JB		 8207 else
8208 *types = gotrel[j].types64;
8209 }
8210
8fd4256d 8211 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 8212 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8213
28f81592 8214 /* The length of the first part of our input line. */
f3c180ae 8215 first = cp - input_line_pointer;
28f81592
AM		 8216
8217 /* The second part goes from after the reloc token until
67c11a9b 8218 (and including) an end_of_line char or comma. */
28f81592 8219 past_reloc = cp + 1 + len;
67c11a9b
AM		 8220 cp = past_reloc;
8221 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8222 ++cp;
8223 second = cp + 1 - past_reloc;
28f81592
AM		 8224
8225 /* Allocate and copy string. The trailing NUL shouldn't
8226 be necessary, but be safe. */
add39d23 8227 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 8228 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 8229 if (second != 0 && *past_reloc != ' ')
8230 /* Replace the relocation token with ' ', so that
8231 errors like foo@GOTOFF1 will be detected. */
8232 tmpbuf[first++] = ' ';
af89796a
L		 8233 else
8234 /* Increment length by 1 if the relocation token is
8235 removed. */
8236 len++;
8237 if (adjust)
8238 *adjust = len;
0787a12d
AM		 8239 memcpy (tmpbuf + first, past_reloc, second);
8240 tmpbuf[first + second] = '\0';
f3c180ae
AM		 8241 return tmpbuf;
8242 }
8243
4fa24527
JB		 8244 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8245 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 8246 return NULL;
8247 }
8248 }
8249
8250 /* Might be a symbol version string. Don't as_bad here. */
8251 return NULL;
8252}
4e4f7c87 8253#endif
f3c180ae 8254
a988325c
NC		 8255#ifdef TE_PE
8256#ifdef lex_got
8257#undef lex_got
8258#endif
8259/* Parse operands of the form
8260 <symbol>@SECREL32+<nnn>
8261
8262 If we find one, set up the correct relocation in RELOC and copy the
8263 input string, minus the `@SECREL32' into a malloc'd buffer for
8264 parsing by the calling routine. Return this buffer, and if ADJUST
8265 is non-null set it to the length of the string we removed from the
34bca508
L		 8266 input line. Otherwise return NULL.
8267
a988325c
NC		 8268 This function is copied from the ELF version above adjusted for PE targets. */
8269
8270static char *
8271lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8272 int *adjust ATTRIBUTE_UNUSED,
d258b828 8273 i386_operand_type *types)
a988325c
NC		 8274{
8275 static const struct
8276 {
8277 const char *str;
8278 int len;
8279 const enum bfd_reloc_code_real rel[2];
8280 const i386_operand_type types64;
8281 }
8282 gotrel[] =
8283 {
8284 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8285 BFD_RELOC_32_SECREL },
8286 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8287 };
8288
8289 char *cp;
8290 unsigned j;
8291
8292 for (cp = input_line_pointer; *cp != '@'; cp++)
8293 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8294 return NULL;
8295
8296 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8297 {
8298 int len = gotrel[j].len;
8299
8300 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8301 {
8302 if (gotrel[j].rel[object_64bit] != 0)
8303 {
8304 int first, second;
8305 char *tmpbuf, *past_reloc;
8306
8307 *rel = gotrel[j].rel[object_64bit];
8308 if (adjust)
8309 *adjust = len;
8310
8311 if (types)
8312 {
8313 if (flag_code != CODE_64BIT)
8314 {
8315 types->bitfield.imm32 = 1;
8316 types->bitfield.disp32 = 1;
8317 }
8318 else
8319 *types = gotrel[j].types64;
8320 }
8321
8322 /* The length of the first part of our input line. */
8323 first = cp - input_line_pointer;
8324
8325 /* The second part goes from after the reloc token until
8326 (and including) an end_of_line char or comma. */
8327 past_reloc = cp + 1 + len;
8328 cp = past_reloc;
8329 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8330 ++cp;
8331 second = cp + 1 - past_reloc;
8332
8333 /* Allocate and copy string. The trailing NUL shouldn't
8334 be necessary, but be safe. */
add39d23 8335 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 8336 memcpy (tmpbuf, input_line_pointer, first);
8337 if (second != 0 && *past_reloc != ' ')
8338 /* Replace the relocation token with ' ', so that
8339 errors like foo@SECLREL321 will be detected. */
8340 tmpbuf[first++] = ' ';
8341 memcpy (tmpbuf + first, past_reloc, second);
8342 tmpbuf[first + second] = '\0';
8343 return tmpbuf;
8344 }
8345
8346 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8347 gotrel[j].str, 1 << (5 + object_64bit));
8348 return NULL;
8349 }
8350 }
8351
8352 /* Might be a symbol version string. Don't as_bad here. */
8353 return NULL;
8354}
8355
8356#endif /* TE_PE */
8357
62ebcb5c 8358bfd_reloc_code_real_type
e3bb37b5 8359x86_cons (expressionS *exp, int size)
f3c180ae 8360{
62ebcb5c
AM		 8361 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8362
ee86248c
JB		 8363 intel_syntax = -intel_syntax;
8364
3c7b9c2c 8365 exp->X_md = 0;
4fa24527 8366 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 8367 {
8368 /* Handle @GOTOFF and the like in an expression. */
8369 char *save;
8370 char *gotfree_input_line;
4a57f2cf 8371 int adjust = 0;
f3c180ae
AM		 8372
8373 save = input_line_pointer;
d258b828 8374 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 8375 if (gotfree_input_line)
8376 input_line_pointer = gotfree_input_line;
8377
8378 expression (exp);
8379
8380 if (gotfree_input_line)
8381 {
8382 /* expression () has merrily parsed up to the end of line,
8383 or a comma - in the wrong buffer. Transfer how far
8384 input_line_pointer has moved to the right buffer. */
8385 input_line_pointer = (save
8386 + (input_line_pointer - gotfree_input_line)
8387 + adjust);
8388 free (gotfree_input_line);
3992d3b7
AM		 8389 if (exp->X_op == O_constant
8390 || exp->X_op == O_absent
8391 || exp->X_op == O_illegal
0398aac5 8392 || exp->X_op == O_register
3992d3b7
AM		 8393 || exp->X_op == O_big)
8394 {
8395 char c = *input_line_pointer;
8396 *input_line_pointer = 0;
8397 as_bad (_("missing or invalid expression `%s'"), save);
8398 *input_line_pointer = c;
8399 }
f3c180ae
AM		 8400 }
8401 }
8402 else
8403 expression (exp);
ee86248c
JB		 8404
8405 intel_syntax = -intel_syntax;
8406
8407 if (intel_syntax)
8408 i386_intel_simplify (exp);
62ebcb5c
AM		 8409
8410 return got_reloc;
f3c180ae 8411}
f3c180ae 8412
9f32dd5b
L		 8413static void
8414signed_cons (int size)
6482c264 8415{
d182319b
JB		 8416 if (flag_code == CODE_64BIT)
8417 cons_sign = 1;
8418 cons (size);
8419 cons_sign = -1;
6482c264
NC		 8420}
8421
d182319b 8422#ifdef TE_PE
6482c264 8423static void
7016a5d5 8424pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 8425{
8426 expressionS exp;
8427
8428 do
8429 {
8430 expression (&exp);
8431 if (exp.X_op == O_symbol)
8432 exp.X_op = O_secrel;
8433
8434 emit_expr (&exp, 4);
8435 }
8436 while (*input_line_pointer++ == ',');
8437
8438 input_line_pointer--;
8439 demand_empty_rest_of_line ();
8440}
6482c264
NC		 8441#endif
8442
43234a1e
L		 8443/* Handle Vector operations. */
8444
8445static char *
8446check_VecOperations (char *op_string, char *op_end)
8447{
8448 const reg_entry *mask;
8449 const char *saved;
8450 char *end_op;
8451
8452 while (*op_string
8453 && (op_end == NULL || op_string < op_end))
8454 {
8455 saved = op_string;
8456 if (*op_string == '{')
8457 {
8458 op_string++;
8459
8460 /* Check broadcasts. */
8461 if (strncmp (op_string, "1to", 3) == 0)
8462 {
8463 int bcst_type;
8464
8465 if (i.broadcast)
8466 goto duplicated_vec_op;
8467
8468 op_string += 3;
8469 if (*op_string == '8')
8e6e0792 8470 bcst_type = 8;
b28d1bda 8471 else if (*op_string == '4')
8e6e0792 8472 bcst_type = 4;
b28d1bda 8473 else if (*op_string == '2')
8e6e0792 8474 bcst_type = 2;
43234a1e
L		 8475 else if (*op_string == '1'
8476 && *(op_string+1) == '6')
8477 {
8e6e0792 8478 bcst_type = 16;
43234a1e
L		 8479 op_string++;
8480 }
8481 else
8482 {
8483 as_bad (_("Unsupported broadcast: `%s'"), saved);
8484 return NULL;
8485 }
8486 op_string++;
8487
8488 broadcast_op.type = bcst_type;
8489 broadcast_op.operand = this_operand;
8490 i.broadcast = &broadcast_op;
8491 }
8492 /* Check masking operation. */
8493 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8494 {
8495 /* k0 can't be used for write mask. */
6d2cd6b2 8496 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
43234a1e 8497 {
6d2cd6b2
JB		 8498 as_bad (_("`%s%s' can't be used for write mask"),
8499 register_prefix, mask->reg_name);
43234a1e
L		 8500 return NULL;
8501 }
8502
8503 if (!i.mask)
8504 {
8505 mask_op.mask = mask;
8506 mask_op.zeroing = 0;
8507 mask_op.operand = this_operand;
8508 i.mask = &mask_op;
8509 }
8510 else
8511 {
8512 if (i.mask->mask)
8513 goto duplicated_vec_op;
8514
8515 i.mask->mask = mask;
8516
8517 /* Only "{z}" is allowed here. No need to check
8518 zeroing mask explicitly. */
8519 if (i.mask->operand != this_operand)
8520 {
8521 as_bad (_("invalid write mask `%s'"), saved);
8522 return NULL;
8523 }
8524 }
8525
8526 op_string = end_op;
8527 }
8528 /* Check zeroing-flag for masking operation. */
8529 else if (*op_string == 'z')
8530 {
8531 if (!i.mask)
8532 {
8533 mask_op.mask = NULL;
8534 mask_op.zeroing = 1;
8535 mask_op.operand = this_operand;
8536 i.mask = &mask_op;
8537 }
8538 else
8539 {
8540 if (i.mask->zeroing)
8541 {
8542 duplicated_vec_op:
8543 as_bad (_("duplicated `%s'"), saved);
8544 return NULL;
8545 }
8546
8547 i.mask->zeroing = 1;
8548
8549 /* Only "{%k}" is allowed here. No need to check mask
8550 register explicitly. */
8551 if (i.mask->operand != this_operand)
8552 {
8553 as_bad (_("invalid zeroing-masking `%s'"),
8554 saved);
8555 return NULL;
8556 }
8557 }
8558
8559 op_string++;
8560 }
8561 else
8562 goto unknown_vec_op;
8563
8564 if (*op_string != '}')
8565 {
8566 as_bad (_("missing `}' in `%s'"), saved);
8567 return NULL;
8568 }
8569 op_string++;
0ba3a731
L		 8570
8571 /* Strip whitespace since the addition of pseudo prefixes
8572 changed how the scrubber treats '{'. */
8573 if (is_space_char (*op_string))
8574 ++op_string;
8575
43234a1e
L		 8576 continue;
8577 }
8578 unknown_vec_op:
8579 /* We don't know this one. */
8580 as_bad (_("unknown vector operation: `%s'"), saved);
8581 return NULL;
8582 }
8583
6d2cd6b2
JB		 8584 if (i.mask && i.mask->zeroing && !i.mask->mask)
8585 {
8586 as_bad (_("zeroing-masking only allowed with write mask"));
8587 return NULL;
8588 }
8589
43234a1e
L		 8590 return op_string;
8591}
8592
252b5132 8593static int
70e41ade 8594i386_immediate (char *imm_start)
252b5132
RH		 8595{
8596 char *save_input_line_pointer;
f3c180ae 8597 char *gotfree_input_line;
252b5132 8598 segT exp_seg = 0;
47926f60 8599 expressionS *exp;
40fb9820
L		 8600 i386_operand_type types;
8601
0dfbf9d7 8602 operand_type_set (&types, ~0);
252b5132
RH		 8603
8604 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8605 {
31b2323c
L		 8606 as_bad (_("at most %d immediate operands are allowed"),
8607 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8608 return 0;
8609 }
8610
8611 exp = &im_expressions[i.imm_operands++];
520dc8e8 8612 i.op[this_operand].imms = exp;
252b5132
RH		 8613
8614 if (is_space_char (*imm_start))
8615 ++imm_start;
8616
8617 save_input_line_pointer = input_line_pointer;
8618 input_line_pointer = imm_start;
8619
d258b828 8620 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8621 if (gotfree_input_line)
8622 input_line_pointer = gotfree_input_line;
252b5132
RH		 8623
8624 exp_seg = expression (exp);
8625
83183c0c 8626 SKIP_WHITESPACE ();
43234a1e
L		 8627
8628 /* Handle vector operations. */
8629 if (*input_line_pointer == '{')
8630 {
8631 input_line_pointer = check_VecOperations (input_line_pointer,
8632 NULL);
8633 if (input_line_pointer == NULL)
8634 return 0;
8635 }
8636
252b5132 8637 if (*input_line_pointer)
f3c180ae 8638 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8639
8640 input_line_pointer = save_input_line_pointer;
f3c180ae 8641 if (gotfree_input_line)
ee86248c
JB		 8642 {
8643 free (gotfree_input_line);
8644
8645 if (exp->X_op == O_constant || exp->X_op == O_register)
8646 exp->X_op = O_illegal;
8647 }
8648
8649 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8650}
252b5132 8651
ee86248c
JB		 8652static int
8653i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8654 i386_operand_type types, const char *imm_start)
8655{
8656 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8657 {
313c53d1
L		 8658 if (imm_start)
8659 as_bad (_("missing or invalid immediate expression `%s'"),
8660 imm_start);
3992d3b7 8661 return 0;
252b5132 8662 }
3e73aa7c 8663 else if (exp->X_op == O_constant)
252b5132 8664 {
47926f60 8665 /* Size it properly later. */
40fb9820 8666 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8667 /* If not 64bit, sign extend val. */
8668 if (flag_code != CODE_64BIT
4eed87de
AM		 8669 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8670 exp->X_add_number
8671 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8672 }
4c63da97 8673#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8674 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8675 && exp_seg != absolute_section
47926f60 8676 && exp_seg != text_section
24eab124
AM		 8677 && exp_seg != data_section
8678 && exp_seg != bss_section
8679 && exp_seg != undefined_section
f86103b7 8680 && !bfd_is_com_section (exp_seg))
252b5132 8681 {
d0b47220 8682 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8683 return 0;
8684 }
8685#endif
a841bdf5 8686 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8687 {
313c53d1
L		 8688 if (imm_start)
8689 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8690 return 0;
8691 }
252b5132
RH		 8692 else
8693 {
8694 /* This is an address. The size of the address will be
24eab124 8695 determined later, depending on destination register,
3e73aa7c 8696 suffix, or the default for the section. */
40fb9820
L		 8697 i.types[this_operand].bitfield.imm8 = 1;
8698 i.types[this_operand].bitfield.imm16 = 1;
8699 i.types[this_operand].bitfield.imm32 = 1;
8700 i.types[this_operand].bitfield.imm32s = 1;
8701 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8702 i.types[this_operand] = operand_type_and (i.types[this_operand],
8703 types);
252b5132
RH		 8704 }
8705
8706 return 1;
8707}
8708
551c1ca1 8709static char *
e3bb37b5 8710i386_scale (char *scale)
252b5132 8711{
551c1ca1
AM		 8712 offsetT val;
8713 char *save = input_line_pointer;
252b5132 8714
551c1ca1
AM		 8715 input_line_pointer = scale;
8716 val = get_absolute_expression ();
8717
8718 switch (val)
252b5132 8719 {
551c1ca1 8720 case 1:
252b5132
RH		 8721 i.log2_scale_factor = 0;
8722 break;
551c1ca1 8723 case 2:
252b5132
RH		 8724 i.log2_scale_factor = 1;
8725 break;
551c1ca1 8726 case 4:
252b5132
RH		 8727 i.log2_scale_factor = 2;
8728 break;
551c1ca1 8729 case 8:
252b5132
RH		 8730 i.log2_scale_factor = 3;
8731 break;
8732 default:
a724f0f4
JB		 8733 {
8734 char sep = *input_line_pointer;
8735
8736 *input_line_pointer = '\0';
8737 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8738 scale);
8739 *input_line_pointer = sep;
8740 input_line_pointer = save;
8741 return NULL;
8742 }
252b5132 8743 }
29b0f896 8744 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8745 {
8746 as_warn (_("scale factor of %d without an index register"),
24eab124 8747 1 << i.log2_scale_factor);
252b5132 8748 i.log2_scale_factor = 0;
252b5132 8749 }
551c1ca1
AM		 8750 scale = input_line_pointer;
8751 input_line_pointer = save;
8752 return scale;
252b5132
RH		 8753}
8754
252b5132 8755static int
e3bb37b5 8756i386_displacement (char *disp_start, char *disp_end)
252b5132 8757{
29b0f896 8758 expressionS *exp;
252b5132
RH		 8759 segT exp_seg = 0;
8760 char *save_input_line_pointer;
f3c180ae 8761 char *gotfree_input_line;
40fb9820
L		 8762 int override;
8763 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8764 int ret;
252b5132 8765
31b2323c
L		 8766 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8767 {
8768 as_bad (_("at most %d displacement operands are allowed"),
8769 MAX_MEMORY_OPERANDS);
8770 return 0;
8771 }
8772
0dfbf9d7 8773 operand_type_set (&bigdisp, 0);
40fb9820
L		 8774 if ((i.types[this_operand].bitfield.jumpabsolute)
8775 || (!current_templates->start->opcode_modifier.jump
8776 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8777 {
40fb9820 8778 bigdisp.bitfield.disp32 = 1;
e05278af 8779 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8780 if (flag_code == CODE_64BIT)
8781 {
8782 if (!override)
8783 {
8784 bigdisp.bitfield.disp32s = 1;
8785 bigdisp.bitfield.disp64 = 1;
8786 }
8787 }
8788 else if ((flag_code == CODE_16BIT) ^ override)
8789 {
8790 bigdisp.bitfield.disp32 = 0;
8791 bigdisp.bitfield.disp16 = 1;
8792 }
e05278af
JB		 8793 }
8794 else
8795 {
8796 /* For PC-relative branches, the width of the displacement
8797 is dependent upon data size, not address size. */
e05278af 8798 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8799 if (flag_code == CODE_64BIT)
8800 {
8801 if (override || i.suffix == WORD_MNEM_SUFFIX)
8802 bigdisp.bitfield.disp16 = 1;
8803 else
8804 {
8805 bigdisp.bitfield.disp32 = 1;
8806 bigdisp.bitfield.disp32s = 1;
8807 }
8808 }
8809 else
e05278af
JB		 8810 {
8811 if (!override)
8812 override = (i.suffix == (flag_code != CODE_16BIT
8813 ? WORD_MNEM_SUFFIX
8814 : LONG_MNEM_SUFFIX));
40fb9820
L		 8815 bigdisp.bitfield.disp32 = 1;
8816 if ((flag_code == CODE_16BIT) ^ override)
8817 {
8818 bigdisp.bitfield.disp32 = 0;
8819 bigdisp.bitfield.disp16 = 1;
8820 }
e05278af 8821 }
e05278af 8822 }
c6fb90c8
L		 8823 i.types[this_operand] = operand_type_or (i.types[this_operand],
8824 bigdisp);
252b5132
RH		 8825
8826 exp = &disp_expressions[i.disp_operands];
520dc8e8 8827 i.op[this_operand].disps = exp;
252b5132
RH		 8828 i.disp_operands++;
8829 save_input_line_pointer = input_line_pointer;
8830 input_line_pointer = disp_start;
8831 END_STRING_AND_SAVE (disp_end);
8832
8833#ifndef GCC_ASM_O_HACK
8834#define GCC_ASM_O_HACK 0
8835#endif
8836#if GCC_ASM_O_HACK
8837 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8838 if (i.types[this_operand].bitfield.baseIndex
24eab124 8839 && displacement_string_end[-1] == '+')
252b5132
RH		 8840 {
8841 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8842 constraint within gcc asm statements.
8843 For instance:
8844
8845 #define _set_tssldt_desc(n,addr,limit,type) \
8846 __asm__ __volatile__ ( \
8847 "movw %w2,%0\n\t" \
8848 "movw %w1,2+%0\n\t" \
8849 "rorl $16,%1\n\t" \
8850 "movb %b1,4+%0\n\t" \
8851 "movb %4,5+%0\n\t" \
8852 "movb $0,6+%0\n\t" \
8853 "movb %h1,7+%0\n\t" \
8854 "rorl $16,%1" \
8855 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8856
8857 This works great except that the output assembler ends
8858 up looking a bit weird if it turns out that there is
8859 no offset. You end up producing code that looks like:
8860
8861 #APP
8862 movw $235,(%eax)
8863 movw %dx,2+(%eax)
8864 rorl $16,%edx
8865 movb %dl,4+(%eax)
8866 movb $137,5+(%eax)
8867 movb $0,6+(%eax)
8868 movb %dh,7+(%eax)
8869 rorl $16,%edx
8870 #NO_APP
8871
47926f60 8872 So here we provide the missing zero. */
24eab124
AM		 8873
8874 *displacement_string_end = '0';
252b5132
RH		 8875 }
8876#endif
d258b828 8877 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8878 if (gotfree_input_line)
8879 input_line_pointer = gotfree_input_line;
252b5132 8880
24eab124 8881 exp_seg = expression (exp);
252b5132 8882
636c26b0
AM		 8883 SKIP_WHITESPACE ();
8884 if (*input_line_pointer)
8885 as_bad (_("junk `%s' after expression"), input_line_pointer);
8886#if GCC_ASM_O_HACK
8887 RESTORE_END_STRING (disp_end + 1);
8888#endif
636c26b0 8889 input_line_pointer = save_input_line_pointer;
636c26b0 8890 if (gotfree_input_line)
ee86248c
JB		 8891 {
8892 free (gotfree_input_line);
8893
8894 if (exp->X_op == O_constant || exp->X_op == O_register)
8895 exp->X_op = O_illegal;
8896 }
8897
8898 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8899
8900 RESTORE_END_STRING (disp_end);
8901
8902 return ret;
8903}
8904
8905static int
8906i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8907 i386_operand_type types, const char *disp_start)
8908{
8909 i386_operand_type bigdisp;
8910 int ret = 1;
636c26b0 8911
24eab124
AM		 8912 /* We do this to make sure that the section symbol is in
8913 the symbol table. We will ultimately change the relocation
47926f60 8914 to be relative to the beginning of the section. */
1ae12ab7 8915 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8916 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8917 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8918 {
636c26b0 8919 if (exp->X_op != O_symbol)
3992d3b7 8920 goto inv_disp;
636c26b0 8921
e5cb08ac 8922 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8923 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8924 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8925 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8926 exp->X_op = O_subtract;
8927 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8928 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8929 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8930 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8931 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8932 else
29b0f896 8933 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8934 }
252b5132 8935
3992d3b7
AM		 8936 else if (exp->X_op == O_absent
8937 || exp->X_op == O_illegal
ee86248c 8938 || exp->X_op == O_big)
2daf4fd8 8939 {
3992d3b7
AM		 8940 inv_disp:
8941 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8942 disp_start);
3992d3b7 8943 ret = 0;
2daf4fd8
AM		 8944 }
8945
0e1147d9
L		 8946 else if (flag_code == CODE_64BIT
8947 && !i.prefix[ADDR_PREFIX]
8948 && exp->X_op == O_constant)
8949 {
8950 /* Since displacement is signed extended to 64bit, don't allow
8951 disp32 and turn off disp32s if they are out of range. */
8952 i.types[this_operand].bitfield.disp32 = 0;
8953 if (!fits_in_signed_long (exp->X_add_number))
8954 {
8955 i.types[this_operand].bitfield.disp32s = 0;
8956 if (i.types[this_operand].bitfield.baseindex)
8957 {
8958 as_bad (_("0x%lx out range of signed 32bit displacement"),
8959 (long) exp->X_add_number);
8960 ret = 0;
8961 }
8962 }
8963 }
8964
4c63da97 8965#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8966 else if (exp->X_op != O_constant
8967 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8968 && exp_seg != absolute_section
8969 && exp_seg != text_section
8970 && exp_seg != data_section
8971 && exp_seg != bss_section
8972 && exp_seg != undefined_section
8973 && !bfd_is_com_section (exp_seg))
24eab124 8974 {
d0b47220 8975 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8976 ret = 0;
24eab124 8977 }
252b5132 8978#endif
3956db08 8979
40fb9820
L		 8980 /* Check if this is a displacement only operand. */
8981 bigdisp = i.types[this_operand];
8982 bigdisp.bitfield.disp8 = 0;
8983 bigdisp.bitfield.disp16 = 0;
8984 bigdisp.bitfield.disp32 = 0;
8985 bigdisp.bitfield.disp32s = 0;
8986 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8987 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8988 i.types[this_operand] = operand_type_and (i.types[this_operand],
8989 types);
3956db08 8990
3992d3b7 8991 return ret;
252b5132
RH		 8992}
8993
2abc2bec
JB		 8994/* Return the active addressing mode, taking address override and
8995 registers forming the address into consideration. Update the
8996 address override prefix if necessary. */
47926f60 8997
2abc2bec
JB		 8998static enum flag_code
8999i386_addressing_mode (void)
252b5132 9000{
be05d201
L		 9001 enum flag_code addr_mode;
9002
9003 if (i.prefix[ADDR_PREFIX])
9004 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
9005 else
9006 {
9007 addr_mode = flag_code;
9008
24eab124 9009#if INFER_ADDR_PREFIX
be05d201
L		 9010 if (i.mem_operands == 0)
9011 {
9012 /* Infer address prefix from the first memory operand. */
9013 const reg_entry *addr_reg = i.base_reg;
9014
9015 if (addr_reg == NULL)
9016 addr_reg = i.index_reg;
eecb386c 9017
be05d201
L		 9018 if (addr_reg)
9019 {
9020 if (addr_reg->reg_num == RegEip
9021 || addr_reg->reg_num == RegEiz
dc821c5f 9022 || addr_reg->reg_type.bitfield.dword)
be05d201
L		 9023 addr_mode = CODE_32BIT;
9024 else if (flag_code != CODE_64BIT
dc821c5f 9025 && addr_reg->reg_type.bitfield.word)
be05d201
L		 9026 addr_mode = CODE_16BIT;
9027
9028 if (addr_mode != flag_code)
9029 {
9030 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
9031 i.prefixes += 1;
9032 /* Change the size of any displacement too. At most one
9033 of Disp16 or Disp32 is set.
9034 FIXME. There doesn't seem to be any real need for
9035 separate Disp16 and Disp32 flags. The same goes for
9036 Imm16 and Imm32. Removing them would probably clean
9037 up the code quite a lot. */
9038 if (flag_code != CODE_64BIT
9039 && (i.types[this_operand].bitfield.disp16
9040 || i.types[this_operand].bitfield.disp32))
9041 i.types[this_operand]
9042 = operand_type_xor (i.types[this_operand], disp16_32);
9043 }
9044 }
9045 }
24eab124 9046#endif
be05d201
L		 9047 }
9048
2abc2bec
JB		 9049 return addr_mode;
9050}
9051
9052/* Make sure the memory operand we've been dealt is valid.
9053 Return 1 on success, 0 on a failure. */
9054
9055static int
9056i386_index_check (const char *operand_string)
9057{
9058 const char *kind = "base/index";
9059 enum flag_code addr_mode = i386_addressing_mode ();
9060
fc0763e6
JB		 9061 if (current_templates->start->opcode_modifier.isstring
9062 && !current_templates->start->opcode_modifier.immext
9063 && (current_templates->end[-1].opcode_modifier.isstring
9064 || i.mem_operands))
9065 {
9066 /* Memory operands of string insns are special in that they only allow
9067 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 9068 const reg_entry *expected_reg;
9069 static const char *di_si[][2] =
9070 {
9071 { "esi", "edi" },
9072 { "si", "di" },
9073 { "rsi", "rdi" }
9074 };
9075 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 9076
9077 kind = "string address";
9078
8325cc63 9079 if (current_templates->start->opcode_modifier.repprefixok)
fc0763e6
JB		 9080 {
9081 i386_operand_type type = current_templates->end[-1].operand_types[0];
9082
9083 if (!type.bitfield.baseindex
9084 || ((!i.mem_operands != !intel_syntax)
9085 && current_templates->end[-1].operand_types[1]
9086 .bitfield.baseindex))
9087 type = current_templates->end[-1].operand_types[1];
be05d201
L		 9088 expected_reg = hash_find (reg_hash,
9089 di_si[addr_mode][type.bitfield.esseg]);
9090
fc0763e6
JB		 9091 }
9092 else
be05d201 9093 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 9094
be05d201
L		 9095 if (i.base_reg != expected_reg
9096 || i.index_reg
fc0763e6 9097 || operand_type_check (i.types[this_operand], disp))
fc0763e6 9098 {
be05d201
L		 9099 /* The second memory operand must have the same size as
9100 the first one. */
9101 if (i.mem_operands
9102 && i.base_reg
9103 && !((addr_mode == CODE_64BIT
dc821c5f 9104 && i.base_reg->reg_type.bitfield.qword)
be05d201 9105 || (addr_mode == CODE_32BIT
dc821c5f
JB		 9106 ? i.base_reg->reg_type.bitfield.dword
9107 : i.base_reg->reg_type.bitfield.word)))
be05d201
L		 9108 goto bad_address;
9109
fc0763e6
JB		 9110 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9111 operand_string,
9112 intel_syntax ? '[' : '(',
9113 register_prefix,
be05d201 9114 expected_reg->reg_name,
fc0763e6 9115 intel_syntax ? ']' : ')');
be05d201 9116 return 1;
fc0763e6 9117 }
be05d201
L		 9118 else
9119 return 1;
9120
9121bad_address:
9122 as_bad (_("`%s' is not a valid %s expression"),
9123 operand_string, kind);
9124 return 0;
3e73aa7c
JH		 9125 }
9126 else
9127 {
be05d201
L		 9128 if (addr_mode != CODE_16BIT)
9129 {
9130 /* 32-bit/64-bit checks. */
9131 if ((i.base_reg
9132 && (addr_mode == CODE_64BIT
dc821c5f
JB		 9133 ? !i.base_reg->reg_type.bitfield.qword
9134 : !i.base_reg->reg_type.bitfield.dword)
be05d201
L		 9135 && (i.index_reg
9136 || (i.base_reg->reg_num
9137 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9138 || (i.index_reg
1b54b8d7
JB		 9139 && !i.index_reg->reg_type.bitfield.xmmword
9140 && !i.index_reg->reg_type.bitfield.ymmword
9141 && !i.index_reg->reg_type.bitfield.zmmword
be05d201 9142 && ((addr_mode == CODE_64BIT
dc821c5f 9143 ? !(i.index_reg->reg_type.bitfield.qword
be05d201 9144 || i.index_reg->reg_num == RegRiz)
dc821c5f 9145 : !(i.index_reg->reg_type.bitfield.dword
be05d201
L		 9146 || i.index_reg->reg_num == RegEiz))
9147 || !i.index_reg->reg_type.bitfield.baseindex)))
9148 goto bad_address;
8178be5b
JB		 9149
9150 /* bndmk, bndldx, and bndstx have special restrictions. */
9151 if (current_templates->start->base_opcode == 0xf30f1b
9152 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9153 {
9154 /* They cannot use RIP-relative addressing. */
9155 if (i.base_reg && i.base_reg->reg_num == RegRip)
9156 {
9157 as_bad (_("`%s' cannot be used here"), operand_string);
9158 return 0;
9159 }
9160
9161 /* bndldx and bndstx ignore their scale factor. */
9162 if (current_templates->start->base_opcode != 0xf30f1b
9163 && i.log2_scale_factor)
9164 as_warn (_("register scaling is being ignored here"));
9165 }
be05d201
L		 9166 }
9167 else
3e73aa7c 9168 {
be05d201 9169 /* 16-bit checks. */
3e73aa7c 9170 if ((i.base_reg
dc821c5f 9171 && (!i.base_reg->reg_type.bitfield.word
40fb9820 9172 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 9173 || (i.index_reg
dc821c5f 9174 && (!i.index_reg->reg_type.bitfield.word
40fb9820 9175 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 9176 || !(i.base_reg
9177 && i.base_reg->reg_num < 6
9178 && i.index_reg->reg_num >= 6
9179 && i.log2_scale_factor == 0))))
be05d201 9180 goto bad_address;
3e73aa7c
JH		 9181 }
9182 }
be05d201 9183 return 1;
24eab124 9184}
252b5132 9185
43234a1e
L		 9186/* Handle vector immediates. */
9187
9188static int
9189RC_SAE_immediate (const char *imm_start)
9190{
9191 unsigned int match_found, j;
9192 const char *pstr = imm_start;
9193 expressionS *exp;
9194
9195 if (*pstr != '{')
9196 return 0;
9197
9198 pstr++;
9199 match_found = 0;
9200 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9201 {
9202 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9203 {
9204 if (!i.rounding)
9205 {
9206 rc_op.type = RC_NamesTable[j].type;
9207 rc_op.operand = this_operand;
9208 i.rounding = &rc_op;
9209 }
9210 else
9211 {
9212 as_bad (_("duplicated `%s'"), imm_start);
9213 return 0;
9214 }
9215 pstr += RC_NamesTable[j].len;
9216 match_found = 1;
9217 break;
9218 }
9219 }
9220 if (!match_found)
9221 return 0;
9222
9223 if (*pstr++ != '}')
9224 {
9225 as_bad (_("Missing '}': '%s'"), imm_start);
9226 return 0;
9227 }
9228 /* RC/SAE immediate string should contain nothing more. */;
9229 if (*pstr != 0)
9230 {
9231 as_bad (_("Junk after '}': '%s'"), imm_start);
9232 return 0;
9233 }
9234
9235 exp = &im_expressions[i.imm_operands++];
9236 i.op[this_operand].imms = exp;
9237
9238 exp->X_op = O_constant;
9239 exp->X_add_number = 0;
9240 exp->X_add_symbol = (symbolS *) 0;
9241 exp->X_op_symbol = (symbolS *) 0;
9242
9243 i.types[this_operand].bitfield.imm8 = 1;
9244 return 1;
9245}
9246
8325cc63
JB		 9247/* Only string instructions can have a second memory operand, so
9248 reduce current_templates to just those if it contains any. */
9249static int
9250maybe_adjust_templates (void)
9251{
9252 const insn_template *t;
9253
9254 gas_assert (i.mem_operands == 1);
9255
9256 for (t = current_templates->start; t < current_templates->end; ++t)
9257 if (t->opcode_modifier.isstring)
9258 break;
9259
9260 if (t < current_templates->end)
9261 {
9262 static templates aux_templates;
9263 bfd_boolean recheck;
9264
9265 aux_templates.start = t;
9266 for (; t < current_templates->end; ++t)
9267 if (!t->opcode_modifier.isstring)
9268 break;
9269 aux_templates.end = t;
9270
9271 /* Determine whether to re-check the first memory operand. */
9272 recheck = (aux_templates.start != current_templates->start
9273 || t != current_templates->end);
9274
9275 current_templates = &aux_templates;
9276
9277 if (recheck)
9278 {
9279 i.mem_operands = 0;
9280 if (i.memop1_string != NULL
9281 && i386_index_check (i.memop1_string) == 0)
9282 return 0;
9283 i.mem_operands = 1;
9284 }
9285 }
9286
9287 return 1;
9288}
9289
fc0763e6 9290/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 9291 on error. */
252b5132 9292
252b5132 9293static int
a7619375 9294i386_att_operand (char *operand_string)
252b5132 9295{
af6bdddf
AM		 9296 const reg_entry *r;
9297 char *end_op;
24eab124 9298 char *op_string = operand_string;
252b5132 9299
24eab124 9300 if (is_space_char (*op_string))
252b5132
RH		 9301 ++op_string;
9302
24eab124 9303 /* We check for an absolute prefix (differentiating,
47926f60 9304 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 9305 if (*op_string == ABSOLUTE_PREFIX)
9306 {
9307 ++op_string;
9308 if (is_space_char (*op_string))
9309 ++op_string;
40fb9820 9310 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 9311 }
252b5132 9312
47926f60 9313 /* Check if operand is a register. */
4d1bb795 9314 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 9315 {
40fb9820
L		 9316 i386_operand_type temp;
9317
24eab124
AM		 9318 /* Check for a segment override by searching for ':' after a
9319 segment register. */
9320 op_string = end_op;
9321 if (is_space_char (*op_string))
9322 ++op_string;
40fb9820
L		 9323 if (*op_string == ':'
9324 && (r->reg_type.bitfield.sreg2
9325 || r->reg_type.bitfield.sreg3))
24eab124
AM		 9326 {
9327 switch (r->reg_num)
9328 {
9329 case 0:
9330 i.seg[i.mem_operands] = &es;
9331 break;
9332 case 1:
9333 i.seg[i.mem_operands] = &cs;
9334 break;
9335 case 2:
9336 i.seg[i.mem_operands] = &ss;
9337 break;
9338 case 3:
9339 i.seg[i.mem_operands] = &ds;
9340 break;
9341 case 4:
9342 i.seg[i.mem_operands] = &fs;
9343 break;
9344 case 5:
9345 i.seg[i.mem_operands] = &gs;
9346 break;
9347 }
252b5132 9348
24eab124 9349 /* Skip the ':' and whitespace. */
252b5132
RH		 9350 ++op_string;
9351 if (is_space_char (*op_string))
24eab124 9352 ++op_string;
252b5132 9353
24eab124
AM		 9354 if (!is_digit_char (*op_string)
9355 && !is_identifier_char (*op_string)
9356 && *op_string != '('
9357 && *op_string != ABSOLUTE_PREFIX)
9358 {
9359 as_bad (_("bad memory operand `%s'"), op_string);
9360 return 0;
9361 }
47926f60 9362 /* Handle case of %es:*foo. */
24eab124
AM		 9363 if (*op_string == ABSOLUTE_PREFIX)
9364 {
9365 ++op_string;
9366 if (is_space_char (*op_string))
9367 ++op_string;
40fb9820 9368 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 9369 }
9370 goto do_memory_reference;
9371 }
43234a1e
L		 9372
9373 /* Handle vector operations. */
9374 if (*op_string == '{')
9375 {
9376 op_string = check_VecOperations (op_string, NULL);
9377 if (op_string == NULL)
9378 return 0;
9379 }
9380
24eab124
AM		 9381 if (*op_string)
9382 {
d0b47220 9383 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 9384 return 0;
9385 }
40fb9820
L		 9386 temp = r->reg_type;
9387 temp.bitfield.baseindex = 0;
c6fb90c8
L		 9388 i.types[this_operand] = operand_type_or (i.types[this_operand],
9389 temp);
7d5e4556 9390 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 9391 i.op[this_operand].regs = r;
24eab124
AM		 9392 i.reg_operands++;
9393 }
af6bdddf
AM		 9394 else if (*op_string == REGISTER_PREFIX)
9395 {
9396 as_bad (_("bad register name `%s'"), op_string);
9397 return 0;
9398 }
24eab124 9399 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 9400 {
24eab124 9401 ++op_string;
40fb9820 9402 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 9403 {
d0b47220 9404 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 9405 return 0;
9406 }
9407 if (!i386_immediate (op_string))
9408 return 0;
9409 }
43234a1e
L		 9410 else if (RC_SAE_immediate (operand_string))
9411 {
9412 /* If it is a RC or SAE immediate, do nothing. */
9413 ;
9414 }
24eab124
AM		 9415 else if (is_digit_char (*op_string)
9416 || is_identifier_char (*op_string)
d02603dc 9417 || *op_string == '"'
e5cb08ac 9418 || *op_string == '(')
24eab124 9419 {
47926f60 9420 /* This is a memory reference of some sort. */
af6bdddf 9421 char *base_string;
252b5132 9422
47926f60 9423 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 9424 char *displacement_string_start;
9425 char *displacement_string_end;
43234a1e 9426 char *vop_start;
252b5132 9427
24eab124 9428 do_memory_reference:
8325cc63
JB		 9429 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9430 return 0;
24eab124 9431 if ((i.mem_operands == 1
40fb9820 9432 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 9433 || i.mem_operands == 2)
9434 {
9435 as_bad (_("too many memory references for `%s'"),
9436 current_templates->start->name);
9437 return 0;
9438 }
252b5132 9439
24eab124
AM		 9440 /* Check for base index form. We detect the base index form by
9441 looking for an ')' at the end of the operand, searching
9442 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9443 after the '('. */
af6bdddf 9444 base_string = op_string + strlen (op_string);
c3332e24 9445
43234a1e
L		 9446 /* Handle vector operations. */
9447 vop_start = strchr (op_string, '{');
9448 if (vop_start && vop_start < base_string)
9449 {
9450 if (check_VecOperations (vop_start, base_string) == NULL)
9451 return 0;
9452 base_string = vop_start;
9453 }
9454
af6bdddf
AM		 9455 --base_string;
9456 if (is_space_char (*base_string))
9457 --base_string;
252b5132 9458
47926f60 9459 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 9460 displacement_string_start = op_string;
9461 displacement_string_end = base_string + 1;
252b5132 9462
24eab124
AM		 9463 if (*base_string == ')')
9464 {
af6bdddf 9465 char *temp_string;
24eab124
AM		 9466 unsigned int parens_balanced = 1;
9467 /* We've already checked that the number of left & right ()'s are
47926f60 9468 equal, so this loop will not be infinite. */
24eab124
AM		 9469 do
9470 {
9471 base_string--;
9472 if (*base_string == ')')
9473 parens_balanced++;
9474 if (*base_string == '(')
9475 parens_balanced--;
9476 }
9477 while (parens_balanced);
c3332e24 9478
af6bdddf 9479 temp_string = base_string;
c3332e24 9480
24eab124 9481 /* Skip past '(' and whitespace. */
252b5132
RH		 9482 ++base_string;
9483 if (is_space_char (*base_string))
24eab124 9484 ++base_string;
252b5132 9485
af6bdddf 9486 if (*base_string == ','
4eed87de
AM		 9487 || ((i.base_reg = parse_register (base_string, &end_op))
9488 != NULL))
252b5132 9489 {
af6bdddf 9490 displacement_string_end = temp_string;
252b5132 9491
40fb9820 9492 i.types[this_operand].bitfield.baseindex = 1;
252b5132 9493
af6bdddf 9494 if (i.base_reg)
24eab124 9495 {
24eab124
AM		 9496 base_string = end_op;
9497 if (is_space_char (*base_string))
9498 ++base_string;
af6bdddf
AM		 9499 }
9500
9501 /* There may be an index reg or scale factor here. */
9502 if (*base_string == ',')
9503 {
9504 ++base_string;
9505 if (is_space_char (*base_string))
9506 ++base_string;
9507
4eed87de
AM		 9508 if ((i.index_reg = parse_register (base_string, &end_op))
9509 != NULL)
24eab124 9510 {
af6bdddf 9511 base_string = end_op;
24eab124
AM		 9512 if (is_space_char (*base_string))
9513 ++base_string;
af6bdddf
AM		 9514 if (*base_string == ',')
9515 {
9516 ++base_string;
9517 if (is_space_char (*base_string))
9518 ++base_string;
9519 }
e5cb08ac 9520 else if (*base_string != ')')
af6bdddf 9521 {
4eed87de
AM		 9522 as_bad (_("expecting `,' or `)' "
9523 "after index register in `%s'"),
af6bdddf
AM		 9524 operand_string);
9525 return 0;
9526 }
24eab124 9527 }
af6bdddf 9528 else if (*base_string == REGISTER_PREFIX)
24eab124 9529 {
f76bf5e0
L		 9530 end_op = strchr (base_string, ',');
9531 if (end_op)
9532 *end_op = '\0';
af6bdddf 9533 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 9534 return 0;
9535 }
252b5132 9536
47926f60 9537 /* Check for scale factor. */
551c1ca1 9538 if (*base_string != ')')
af6bdddf 9539 {
551c1ca1
AM		 9540 char *end_scale = i386_scale (base_string);
9541
9542 if (!end_scale)
af6bdddf 9543 return 0;
24eab124 9544
551c1ca1 9545 base_string = end_scale;
af6bdddf
AM		 9546 if (is_space_char (*base_string))
9547 ++base_string;
9548 if (*base_string != ')')
9549 {
4eed87de
AM		 9550 as_bad (_("expecting `)' "
9551 "after scale factor in `%s'"),
af6bdddf
AM		 9552 operand_string);
9553 return 0;
9554 }
9555 }
9556 else if (!i.index_reg)
24eab124 9557 {
4eed87de
AM		 9558 as_bad (_("expecting index register or scale factor "
9559 "after `,'; got '%c'"),
af6bdddf 9560 *base_string);
24eab124
AM		 9561 return 0;
9562 }
9563 }
af6bdddf 9564 else if (*base_string != ')')
24eab124 9565 {
4eed87de
AM		 9566 as_bad (_("expecting `,' or `)' "
9567 "after base register in `%s'"),
af6bdddf 9568 operand_string);
24eab124
AM		 9569 return 0;
9570 }
c3332e24 9571 }
af6bdddf 9572 else if (*base_string == REGISTER_PREFIX)
c3332e24 9573 {
f76bf5e0
L		 9574 end_op = strchr (base_string, ',');
9575 if (end_op)
9576 *end_op = '\0';
af6bdddf 9577 as_bad (_("bad register name `%s'"), base_string);
24eab124 9578 return 0;
c3332e24 9579 }
24eab124
AM		 9580 }
9581
9582 /* If there's an expression beginning the operand, parse it,
9583 assuming displacement_string_start and
9584 displacement_string_end are meaningful. */
9585 if (displacement_string_start != displacement_string_end)
9586 {
9587 if (!i386_displacement (displacement_string_start,
9588 displacement_string_end))
9589 return 0;
9590 }
9591
9592 /* Special case for (%dx) while doing input/output op. */
9593 if (i.base_reg
0dfbf9d7
L		 9594 && operand_type_equal (&i.base_reg->reg_type,
9595 &reg16_inoutportreg)
24eab124
AM		 9596 && i.index_reg == 0
9597 && i.log2_scale_factor == 0
9598 && i.seg[i.mem_operands] == 0
40fb9820 9599 && !operand_type_check (i.types[this_operand], disp))
24eab124 9600 {
65da13b5 9601 i.types[this_operand] = inoutportreg;
24eab124
AM		 9602 return 1;
9603 }
9604
eecb386c
AM		 9605 if (i386_index_check (operand_string) == 0)
9606 return 0;
5c07affc 9607 i.types[this_operand].bitfield.mem = 1;
8325cc63
JB		 9608 if (i.mem_operands == 0)
9609 i.memop1_string = xstrdup (operand_string);
24eab124
AM		 9610 i.mem_operands++;
9611 }
9612 else
ce8a8b2f
AM		 9613 {
9614 /* It's not a memory operand; argh! */
24eab124
AM		 9615 as_bad (_("invalid char %s beginning operand %d `%s'"),
9616 output_invalid (*op_string),
9617 this_operand + 1,
9618 op_string);
9619 return 0;
9620 }
47926f60 9621 return 1; /* Normal return. */
252b5132
RH		 9622}
9623\f
fa94de6b
RM		 9624/* Calculate the maximum variable size (i.e., excluding fr_fix)
9625 that an rs_machine_dependent frag may reach. */
9626
9627unsigned int
9628i386_frag_max_var (fragS *frag)
9629{
9630 /* The only relaxable frags are for jumps.
9631 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9632 gas_assert (frag->fr_type == rs_machine_dependent);
9633 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9634}
9635
b084df0b
L		 9636#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9637static int
8dcea932 9638elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 9639{
9640 /* STT_GNU_IFUNC symbol must go through PLT. */
9641 if ((symbol_get_bfdsym (fr_symbol)->flags
9642 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9643 return 0;
9644
9645 if (!S_IS_EXTERNAL (fr_symbol))
9646 /* Symbol may be weak or local. */
9647 return !S_IS_WEAK (fr_symbol);
9648
8dcea932
L		 9649 /* Global symbols with non-default visibility can't be preempted. */
9650 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9651 return 1;
9652
9653 if (fr_var != NO_RELOC)
9654 switch ((enum bfd_reloc_code_real) fr_var)
9655 {
9656 case BFD_RELOC_386_PLT32:
9657 case BFD_RELOC_X86_64_PLT32:
33eaf5de 9658 /* Symbol with PLT relocation may be preempted. */
8dcea932
L		 9659 return 0;
9660 default:
9661 abort ();
9662 }
9663
b084df0b
L		 9664 /* Global symbols with default visibility in a shared library may be
9665 preempted by another definition. */
8dcea932 9666 return !shared;
b084df0b
L		 9667}
9668#endif
9669
ee7fcc42
AM		 9670/* md_estimate_size_before_relax()
9671
9672 Called just before relax() for rs_machine_dependent frags. The x86
9673 assembler uses these frags to handle variable size jump
9674 instructions.
9675
9676 Any symbol that is now undefined will not become defined.
9677 Return the correct fr_subtype in the frag.
9678 Return the initial "guess for variable size of frag" to caller.
9679 The guess is actually the growth beyond the fixed part. Whatever
9680 we do to grow the fixed or variable part contributes to our
9681 returned value. */
9682
252b5132 9683int
7016a5d5 9684md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9685{
252b5132 9686 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9687 check for un-relaxable symbols. On an ELF system, we can't relax
9688 an externally visible symbol, because it may be overridden by a
9689 shared library. */
9690 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9691#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9692 || (IS_ELF
8dcea932
L		 9693 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9694 fragP->fr_var))
fbeb56a4
DK		 9695#endif
9696#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9697 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9698 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9699#endif
9700 )
252b5132 9701 {
b98ef147
AM		 9702 /* Symbol is undefined in this segment, or we need to keep a
9703 reloc so that weak symbols can be overridden. */
9704 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9705 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9706 unsigned char *opcode;
9707 int old_fr_fix;
f6af82bd 9708
ee7fcc42 9709 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9710 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9711 else if (size == 2)
f6af82bd 9712 reloc_type = BFD_RELOC_16_PCREL;
bd7ab16b
L		 9713#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9714 else if (need_plt32_p (fragP->fr_symbol))
9715 reloc_type = BFD_RELOC_X86_64_PLT32;
9716#endif
f6af82bd
AM		 9717 else
9718 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9719
ee7fcc42
AM		 9720 old_fr_fix = fragP->fr_fix;
9721 opcode = (unsigned char *) fragP->fr_opcode;
9722
fddf5b5b 9723 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9724 {
fddf5b5b
AM		 9725 case UNCOND_JUMP:
9726 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9727 opcode[0] = 0xe9;
252b5132 9728 fragP->fr_fix += size;
062cd5e7
AS		 9729 fix_new (fragP, old_fr_fix, size,
9730 fragP->fr_symbol,
9731 fragP->fr_offset, 1,
9732 reloc_type);
252b5132
RH		 9733 break;
9734
fddf5b5b 9735 case COND_JUMP86:
412167cb
AM		 9736 if (size == 2
9737 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9738 {
9739 /* Negate the condition, and branch past an
9740 unconditional jump. */
9741 opcode[0] ^= 1;
9742 opcode[1] = 3;
9743 /* Insert an unconditional jump. */
9744 opcode[2] = 0xe9;
9745 /* We added two extra opcode bytes, and have a two byte
9746 offset. */
9747 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9748 fix_new (fragP, old_fr_fix + 2, 2,
9749 fragP->fr_symbol,
9750 fragP->fr_offset, 1,
9751 reloc_type);
fddf5b5b
AM		 9752 break;
9753 }
9754 /* Fall through. */
9755
9756 case COND_JUMP:
412167cb
AM		 9757 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9758 {
3e02c1cc
AM		 9759 fixS *fixP;
9760
412167cb 9761 fragP->fr_fix += 1;
3e02c1cc
AM		 9762 fixP = fix_new (fragP, old_fr_fix, 1,
9763 fragP->fr_symbol,
9764 fragP->fr_offset, 1,
9765 BFD_RELOC_8_PCREL);
9766 fixP->fx_signed = 1;
412167cb
AM		 9767 break;
9768 }
93c2a809 9769
24eab124 9770 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9771 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9772 opcode[1] = opcode[0] + 0x10;
f6af82bd 9773 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9774 /* We've added an opcode byte. */
9775 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9776 fix_new (fragP, old_fr_fix + 1, size,
9777 fragP->fr_symbol,
9778 fragP->fr_offset, 1,
9779 reloc_type);
252b5132 9780 break;
fddf5b5b
AM		 9781
9782 default:
9783 BAD_CASE (fragP->fr_subtype);
9784 break;
252b5132
RH		 9785 }
9786 frag_wane (fragP);
ee7fcc42 9787 return fragP->fr_fix - old_fr_fix;
252b5132 9788 }
93c2a809 9789
93c2a809
AM		 9790 /* Guess size depending on current relax state. Initially the relax
9791 state will correspond to a short jump and we return 1, because
9792 the variable part of the frag (the branch offset) is one byte
9793 long. However, we can relax a section more than once and in that
9794 case we must either set fr_subtype back to the unrelaxed state,
9795 or return the value for the appropriate branch. */
9796 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9797}
9798
47926f60
KH		 9799/* Called after relax() is finished.
9800
9801 In: Address of frag.
9802 fr_type == rs_machine_dependent.
9803 fr_subtype is what the address relaxed to.
9804
9805 Out: Any fixSs and constants are set up.
9806 Caller will turn frag into a ".space 0". */
9807
252b5132 9808void
7016a5d5
TG		 9809md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9810 fragS *fragP)
252b5132 9811{
29b0f896 9812 unsigned char *opcode;
252b5132 9813 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9814 offsetT target_address;
9815 offsetT opcode_address;
252b5132 9816 unsigned int extension = 0;
847f7ad4 9817 offsetT displacement_from_opcode_start;
252b5132
RH		 9818
9819 opcode = (unsigned char *) fragP->fr_opcode;
9820
47926f60 9821 /* Address we want to reach in file space. */
252b5132 9822 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9823
47926f60 9824 /* Address opcode resides at in file space. */
252b5132
RH		 9825 opcode_address = fragP->fr_address + fragP->fr_fix;
9826
47926f60 9827 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9828 displacement_from_opcode_start = target_address - opcode_address;
9829
fddf5b5b 9830 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9831 {
47926f60
KH		 9832 /* Don't have to change opcode. */
9833 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9834 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9835 }
9836 else
9837 {
9838 if (no_cond_jump_promotion
9839 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9840 as_warn_where (fragP->fr_file, fragP->fr_line,
9841 _("long jump required"));
252b5132 9842
fddf5b5b
AM		 9843 switch (fragP->fr_subtype)
9844 {
9845 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9846 extension = 4; /* 1 opcode + 4 displacement */
9847 opcode[0] = 0xe9;
9848 where_to_put_displacement = &opcode[1];
9849 break;
252b5132 9850
fddf5b5b
AM		 9851 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9852 extension = 2; /* 1 opcode + 2 displacement */
9853 opcode[0] = 0xe9;
9854 where_to_put_displacement = &opcode[1];
9855 break;
252b5132 9856
fddf5b5b
AM		 9857 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9858 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9859 extension = 5; /* 2 opcode + 4 displacement */
9860 opcode[1] = opcode[0] + 0x10;
9861 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9862 where_to_put_displacement = &opcode[2];
9863 break;
252b5132 9864
fddf5b5b
AM		 9865 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9866 extension = 3; /* 2 opcode + 2 displacement */
9867 opcode[1] = opcode[0] + 0x10;
9868 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9869 where_to_put_displacement = &opcode[2];
9870 break;
252b5132 9871
fddf5b5b
AM		 9872 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9873 extension = 4;
9874 opcode[0] ^= 1;
9875 opcode[1] = 3;
9876 opcode[2] = 0xe9;
9877 where_to_put_displacement = &opcode[3];
9878 break;
9879
9880 default:
9881 BAD_CASE (fragP->fr_subtype);
9882 break;
9883 }
252b5132 9884 }
fddf5b5b 9885
7b81dfbb
AJ		 9886 /* If size if less then four we are sure that the operand fits,
9887 but if it's 4, then it could be that the displacement is larger
9888 then -/+ 2GB. */
9889 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9890 && object_64bit
9891 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9892 + ((addressT) 1 << 31))
9893 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9894 {
9895 as_bad_where (fragP->fr_file, fragP->fr_line,
9896 _("jump target out of range"));
9897 /* Make us emit 0. */
9898 displacement_from_opcode_start = extension;
9899 }
47926f60 9900 /* Now put displacement after opcode. */
252b5132
RH		 9901 md_number_to_chars ((char *) where_to_put_displacement,
9902 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9903 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9904 fragP->fr_fix += extension;
9905}
9906\f
7016a5d5 9907/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9908 by our caller that we have all the info we need to fix it up.
9909
7016a5d5
TG		 9910 Parameter valP is the pointer to the value of the bits.
9911
252b5132
RH		 9912 On the 386, immediates, displacements, and data pointers are all in
9913 the same (little-endian) format, so we don't need to care about which
9914 we are handling. */
9915
94f592af 9916void
7016a5d5 9917md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9918{
94f592af 9919 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9920 valueT value = *valP;
252b5132 9921
f86103b7 9922#if !defined (TE_Mach)
93382f6d
AM		 9923 if (fixP->fx_pcrel)
9924 {
9925 switch (fixP->fx_r_type)
9926 {
5865bb77
ILT		 9927 default:
9928 break;
9929
d6ab8113
JB		 9930 case BFD_RELOC_64:
9931 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9932 break;
93382f6d 9933 case BFD_RELOC_32:
ae8887b5 9934 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9935 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9936 break;
9937 case BFD_RELOC_16:
9938 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9939 break;
9940 case BFD_RELOC_8:
9941 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9942 break;
9943 }
9944 }
252b5132 9945
a161fe53 9946 if (fixP->fx_addsy != NULL
31312f95 9947 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9948 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9949 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9950 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9951 && !use_rela_relocations)
252b5132 9952 {
31312f95
AM		 9953 /* This is a hack. There should be a better way to handle this.
9954 This covers for the fact that bfd_install_relocation will
9955 subtract the current location (for partial_inplace, PC relative
9956 relocations); see more below. */
252b5132 9957#ifndef OBJ_AOUT
718ddfc0 9958 if (IS_ELF
252b5132
RH		 9959#ifdef TE_PE
9960 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9961#endif
9962 )
9963 value += fixP->fx_where + fixP->fx_frag->fr_address;
9964#endif
9965#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9966 if (IS_ELF)
252b5132 9967 {
6539b54b 9968 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9969
6539b54b 9970 if ((sym_seg == seg
2f66722d 9971 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9972 && sym_seg != absolute_section))
af65af87 9973 && !generic_force_reloc (fixP))
2f66722d
AM		 9974 {
9975 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9976 bfd_install_relocation subtracts them out again. I think
9977 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9978 it. FIXME. */
9979 value += fixP->fx_where + fixP->fx_frag->fr_address;
9980 }
252b5132
RH		 9981 }
9982#endif
9983#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9984 /* For some reason, the PE format does not store a
9985 section address offset for a PC relative symbol. */
9986 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9987 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9988 value += md_pcrel_from (fixP);
9989#endif
9990 }
fbeb56a4 9991#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9992 if (fixP->fx_addsy != NULL
9993 && S_IS_WEAK (fixP->fx_addsy)
9994 /* PR 16858: Do not modify weak function references. */
9995 && ! fixP->fx_pcrel)
fbeb56a4 9996 {
296a8689
NC		 9997#if !defined (TE_PEP)
9998 /* For x86 PE weak function symbols are neither PC-relative
9999 nor do they set S_IS_FUNCTION. So the only reliable way
10000 to detect them is to check the flags of their containing
10001 section. */
10002 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
10003 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
10004 ;
10005 else
10006#endif
fbeb56a4
DK		 10007 value -= S_GET_VALUE (fixP->fx_addsy);
10008 }
10009#endif
252b5132
RH		 10010
10011 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 10012 and we must not disappoint it. */
252b5132 10013#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 10014 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 10015 switch (fixP->fx_r_type)
10016 {
10017 case BFD_RELOC_386_PLT32:
3e73aa7c 10018 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 10019 /* Make the jump instruction point to the address of the operand. At
10020 runtime we merely add the offset to the actual PLT entry. */
10021 value = -4;
10022 break;
31312f95 10023
13ae64f3
JJ		 10024 case BFD_RELOC_386_TLS_GD:
10025 case BFD_RELOC_386_TLS_LDM:
13ae64f3 10026 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10027 case BFD_RELOC_386_TLS_IE:
10028 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 10029 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 10030 case BFD_RELOC_X86_64_TLSGD:
10031 case BFD_RELOC_X86_64_TLSLD:
10032 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 10033 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 10034 value = 0; /* Fully resolved at runtime. No addend. */
10035 /* Fallthrough */
10036 case BFD_RELOC_386_TLS_LE:
10037 case BFD_RELOC_386_TLS_LDO_32:
10038 case BFD_RELOC_386_TLS_LE_32:
10039 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10040 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 10041 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 10042 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 10043 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10044 break;
10045
67a4f2b7
AO		 10046 case BFD_RELOC_386_TLS_DESC_CALL:
10047 case BFD_RELOC_X86_64_TLSDESC_CALL:
10048 value = 0; /* Fully resolved at runtime. No addend. */
10049 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10050 fixP->fx_done = 0;
10051 return;
10052
47926f60
KH		 10053 case BFD_RELOC_VTABLE_INHERIT:
10054 case BFD_RELOC_VTABLE_ENTRY:
10055 fixP->fx_done = 0;
94f592af 10056 return;
47926f60
KH		 10057
10058 default:
10059 break;
10060 }
10061#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 10062 *valP = value;
f86103b7 10063#endif /* !defined (TE_Mach) */
3e73aa7c 10064
3e73aa7c 10065 /* Are we finished with this relocation now? */
c6682705 10066 if (fixP->fx_addsy == NULL)
3e73aa7c 10067 fixP->fx_done = 1;
fbeb56a4
DK		 10068#if defined (OBJ_COFF) && defined (TE_PE)
10069 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10070 {
10071 fixP->fx_done = 0;
10072 /* Remember value for tc_gen_reloc. */
10073 fixP->fx_addnumber = value;
10074 /* Clear out the frag for now. */
10075 value = 0;
10076 }
10077#endif
3e73aa7c
JH		 10078 else if (use_rela_relocations)
10079 {
10080 fixP->fx_no_overflow = 1;
062cd5e7
AS		 10081 /* Remember value for tc_gen_reloc. */
10082 fixP->fx_addnumber = value;
3e73aa7c
JH		 10083 value = 0;
10084 }
f86103b7 10085
94f592af 10086 md_number_to_chars (p, value, fixP->fx_size);
252b5132 10087}
252b5132 10088\f
6d4af3c2 10089const char *
499ac353 10090md_atof (int type, char *litP, int *sizeP)
252b5132 10091{
499ac353
NC		 10092 /* This outputs the LITTLENUMs in REVERSE order;
10093 in accord with the bigendian 386. */
10094 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 10095}
10096\f
2d545b82 10097static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 10098
252b5132 10099static char *
e3bb37b5 10100output_invalid (int c)
252b5132 10101{
3882b010 10102 if (ISPRINT (c))
f9f21a03
L		 10103 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10104 "'%c'", c);
252b5132 10105 else
f9f21a03 10106 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 10107 "(0x%x)", (unsigned char) c);
252b5132
RH		 10108 return output_invalid_buf;
10109}
10110
af6bdddf 10111/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 10112
10113static const reg_entry *
4d1bb795 10114parse_real_register (char *reg_string, char **end_op)
252b5132 10115{
af6bdddf
AM		 10116 char *s = reg_string;
10117 char *p;
252b5132
RH		 10118 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10119 const reg_entry *r;
10120
10121 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10122 if (*s == REGISTER_PREFIX)
10123 ++s;
10124
10125 if (is_space_char (*s))
10126 ++s;
10127
10128 p = reg_name_given;
af6bdddf 10129 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 10130 {
10131 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 10132 return (const reg_entry *) NULL;
10133 s++;
252b5132
RH		 10134 }
10135
6588847e
DN		 10136 /* For naked regs, make sure that we are not dealing with an identifier.
10137 This prevents confusing an identifier like `eax_var' with register
10138 `eax'. */
10139 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10140 return (const reg_entry *) NULL;
10141
af6bdddf 10142 *end_op = s;
252b5132
RH		 10143
10144 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10145
5f47d35b 10146 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 10147 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 10148 {
0e0eea78
JB		 10149 if (!cpu_arch_flags.bitfield.cpu8087
10150 && !cpu_arch_flags.bitfield.cpu287
10151 && !cpu_arch_flags.bitfield.cpu387)
10152 return (const reg_entry *) NULL;
10153
5f47d35b
AM		 10154 if (is_space_char (*s))
10155 ++s;
10156 if (*s == '(')
10157 {
af6bdddf 10158 ++s;
5f47d35b
AM		 10159 if (is_space_char (*s))
10160 ++s;
10161 if (*s >= '0' && *s <= '7')
10162 {
db557034 10163 int fpr = *s - '0';
af6bdddf 10164 ++s;
5f47d35b
AM		 10165 if (is_space_char (*s))
10166 ++s;
10167 if (*s == ')')
10168 {
10169 *end_op = s + 1;
1e9cc1c2 10170 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 10171 know (r);
10172 return r + fpr;
5f47d35b 10173 }
5f47d35b 10174 }
47926f60 10175 /* We have "%st(" then garbage. */
5f47d35b
AM		 10176 return (const reg_entry *) NULL;
10177 }
10178 }
10179
a60de03c
JB		 10180 if (r == NULL || allow_pseudo_reg)
10181 return r;
10182
0dfbf9d7 10183 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 10184 return (const reg_entry *) NULL;
10185
dc821c5f 10186 if ((r->reg_type.bitfield.dword
192dc9c6
JB		 10187 || r->reg_type.bitfield.sreg3
10188 || r->reg_type.bitfield.control
10189 || r->reg_type.bitfield.debug
10190 || r->reg_type.bitfield.test)
10191 && !cpu_arch_flags.bitfield.cpui386)
10192 return (const reg_entry *) NULL;
10193
6e041cf4 10194 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
192dc9c6
JB		 10195 return (const reg_entry *) NULL;
10196
6e041cf4
JB		 10197 if (!cpu_arch_flags.bitfield.cpuavx512f)
10198 {
10199 if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask)
10200 return (const reg_entry *) NULL;
40f12533 10201
6e041cf4
JB		 10202 if (!cpu_arch_flags.bitfield.cpuavx)
10203 {
10204 if (r->reg_type.bitfield.ymmword)
10205 return (const reg_entry *) NULL;
1848e567 10206
6e041cf4
JB		 10207 if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword)
10208 return (const reg_entry *) NULL;
10209 }
10210 }
43234a1e 10211
1adf7f56
JB		 10212 if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx)
10213 return (const reg_entry *) NULL;
10214
db51cc60 10215 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 10216 if (!allow_index_reg
db51cc60
L		 10217 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10218 return (const reg_entry *) NULL;
10219
1d3f8286
JB		 10220 /* Upper 16 vector registers are only available with VREX in 64bit
10221 mode, and require EVEX encoding. */
10222 if (r->reg_flags & RegVRex)
43234a1e
L		 10223 {
10224 if (!cpu_arch_flags.bitfield.cpuvrex
10225 || flag_code != CODE_64BIT)
10226 return (const reg_entry *) NULL;
1d3f8286
JB		 10227
10228 i.vec_encoding = vex_encoding_evex;
43234a1e
L		 10229 }
10230
a60de03c 10231 if (((r->reg_flags & (RegRex64 | RegRex))
dc821c5f 10232 || r->reg_type.bitfield.qword)
40fb9820 10233 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 10234 || !operand_type_equal (&r->reg_type, &control))
1ae00879 10235 && flag_code != CODE_64BIT)
20f0a1fc 10236 return (const reg_entry *) NULL;
1ae00879 10237
b7240065
JB		 10238 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10239 return (const reg_entry *) NULL;
10240
252b5132
RH		 10241 return r;
10242}
4d1bb795
JB		 10243
10244/* REG_STRING starts *before* REGISTER_PREFIX. */
10245
10246static const reg_entry *
10247parse_register (char *reg_string, char **end_op)
10248{
10249 const reg_entry *r;
10250
10251 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10252 r = parse_real_register (reg_string, end_op);
10253 else
10254 r = NULL;
10255 if (!r)
10256 {
10257 char *save = input_line_pointer;
10258 char c;
10259 symbolS *symbolP;
10260
10261 input_line_pointer = reg_string;
d02603dc 10262 c = get_symbol_name (&reg_string);
4d1bb795
JB		 10263 symbolP = symbol_find (reg_string);
10264 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10265 {
10266 const expressionS *e = symbol_get_value_expression (symbolP);
10267
0398aac5 10268 know (e->X_op == O_register);
4eed87de 10269 know (e->X_add_number >= 0
c3fe08fa 10270 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 10271 r = i386_regtab + e->X_add_number;
d3bb6b49 10272 if ((r->reg_flags & RegVRex))
86fa6981 10273 i.vec_encoding = vex_encoding_evex;
4d1bb795
JB		 10274 *end_op = input_line_pointer;
10275 }
10276 *input_line_pointer = c;
10277 input_line_pointer = save;
10278 }
10279 return r;
10280}
10281
10282int
10283i386_parse_name (char *name, expressionS *e, char *nextcharP)
10284{
10285 const reg_entry *r;
10286 char *end = input_line_pointer;
10287
10288 *end = *nextcharP;
10289 r = parse_register (name, &input_line_pointer);
10290 if (r && end <= input_line_pointer)
10291 {
10292 *nextcharP = *input_line_pointer;
10293 *input_line_pointer = 0;
10294 e->X_op = O_register;
10295 e->X_add_number = r - i386_regtab;
10296 return 1;
10297 }
10298 input_line_pointer = end;
10299 *end = 0;
ee86248c 10300 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 10301}
10302
10303void
10304md_operand (expressionS *e)
10305{
ee86248c
JB		 10306 char *end;
10307 const reg_entry *r;
4d1bb795 10308
ee86248c
JB		 10309 switch (*input_line_pointer)
10310 {
10311 case REGISTER_PREFIX:
10312 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 10313 if (r)
10314 {
10315 e->X_op = O_register;
10316 e->X_add_number = r - i386_regtab;
10317 input_line_pointer = end;
10318 }
ee86248c
JB		 10319 break;
10320
10321 case '[':
9c2799c2 10322 gas_assert (intel_syntax);
ee86248c
JB		 10323 end = input_line_pointer++;
10324 expression (e);
10325 if (*input_line_pointer == ']')
10326 {
10327 ++input_line_pointer;
10328 e->X_op_symbol = make_expr_symbol (e);
10329 e->X_add_symbol = NULL;
10330 e->X_add_number = 0;
10331 e->X_op = O_index;
10332 }
10333 else
10334 {
10335 e->X_op = O_absent;
10336 input_line_pointer = end;
10337 }
10338 break;
4d1bb795
JB		 10339 }
10340}
10341
252b5132 10342\f
4cc782b5 10343#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
b6f8c7c4 10344const char *md_shortopts = "kVQ:sqnO::";
252b5132 10345#else
b6f8c7c4 10346const char *md_shortopts = "qnO::";
252b5132 10347#endif
6e0b89ee 10348
3e73aa7c 10349#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 10350#define OPTION_64 (OPTION_MD_BASE + 1)
10351#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 10352#define OPTION_MARCH (OPTION_MD_BASE + 3)
10353#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 10354#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10355#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10356#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10357#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
bd5dea88 10358#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
c0f3af97 10359#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 10360#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 10361#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10362#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10363#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 10364#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 10365#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10366#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 10367#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 10368#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 10369#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 10370#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 10371#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10372#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 10373#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
b3b91714 10374
99ad8390
NC		 10375struct option md_longopts[] =
10376{
3e73aa7c 10377 {"32", no_argument, NULL, OPTION_32},
321098a5 10378#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10379 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 10380 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 10381#endif
10382#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10383 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 10384 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 10385#endif
b3b91714 10386 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 10387 {"march", required_argument, NULL, OPTION_MARCH},
10388 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 10389 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10390 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10391 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10392 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
c0f3af97 10393 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 10394 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 10395 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 10396 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 10397 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 10398 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10399 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 10400# if defined (TE_PE) || defined (TE_PEP)
10401 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10402#endif
d1982f93 10403 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 10404 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 10405 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 10406 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 10407 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10408 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 10409 {NULL, no_argument, NULL, 0}
10410};
10411size_t md_longopts_size = sizeof (md_longopts);
10412
10413int
17b9d67d 10414md_parse_option (int c, const char *arg)
252b5132 10415{
91d6fa6a 10416 unsigned int j;
293f5f65 10417 char *arch, *next, *saved;
9103f4f4 10418
252b5132
RH		 10419 switch (c)
10420 {
12b55ccc
L		 10421 case 'n':
10422 optimize_align_code = 0;
10423 break;
10424
a38cf1db
AM		 10425 case 'q':
10426 quiet_warnings = 1;
252b5132
RH		 10427 break;
10428
10429#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 10430 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10431 should be emitted or not. FIXME: Not implemented. */
10432 case 'Q':
252b5132
RH		 10433 break;
10434
10435 /* -V: SVR4 argument to print version ID. */
10436 case 'V':
10437 print_version_id ();
10438 break;
10439
a38cf1db
AM		 10440 /* -k: Ignore for FreeBSD compatibility. */
10441 case 'k':
252b5132 10442 break;
4cc782b5
ILT		 10443
10444 case 's':
10445 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 10446 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 10447 break;
8dcea932
L		 10448
10449 case OPTION_MSHARED:
10450 shared = 1;
10451 break;
99ad8390 10452#endif
321098a5 10453#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10454 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 10455 case OPTION_64:
10456 {
10457 const char **list, **l;
10458
3e73aa7c
JH		 10459 list = bfd_target_list ();
10460 for (l = list; *l != NULL; l++)
8620418b 10461 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 10462 || strcmp (*l, "coff-x86-64") == 0
10463 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 10464 || strcmp (*l, "pei-x86-64") == 0
10465 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 10466 {
10467 default_arch = "x86_64";
10468 break;
10469 }
3e73aa7c 10470 if (*l == NULL)
2b5d6a91 10471 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 10472 free (list);
10473 }
10474 break;
10475#endif
252b5132 10476
351f65ca 10477#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10478 case OPTION_X32:
351f65ca
L		 10479 if (IS_ELF)
10480 {
10481 const char **list, **l;
10482
10483 list = bfd_target_list ();
10484 for (l = list; *l != NULL; l++)
10485 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10486 {
10487 default_arch = "x86_64:32";
10488 break;
10489 }
10490 if (*l == NULL)
2b5d6a91 10491 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 10492 free (list);
10493 }
10494 else
10495 as_fatal (_("32bit x86_64 is only supported for ELF"));
10496 break;
10497#endif
10498
6e0b89ee
AM		 10499 case OPTION_32:
10500 default_arch = "i386";
10501 break;
10502
b3b91714
AM		 10503 case OPTION_DIVIDE:
10504#ifdef SVR4_COMMENT_CHARS
10505 {
10506 char *n, *t;
10507 const char *s;
10508
add39d23 10509 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 10510 t = n;
10511 for (s = i386_comment_chars; *s != '\0'; s++)
10512 if (*s != '/')
10513 *t++ = *s;
10514 *t = '\0';
10515 i386_comment_chars = n;
10516 }
10517#endif
10518 break;
10519
9103f4f4 10520 case OPTION_MARCH:
293f5f65
L		 10521 saved = xstrdup (arg);
10522 arch = saved;
10523 /* Allow -march=+nosse. */
10524 if (*arch == '+')
10525 arch++;
6305a203 10526 do
9103f4f4 10527 {
6305a203 10528 if (*arch == '.')
2b5d6a91 10529 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10530 next = strchr (arch, '+');
10531 if (next)
10532 *next++ = '\0';
91d6fa6a 10533 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10534 {
91d6fa6a 10535 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 10536 {
6305a203 10537 /* Processor. */
1ded5609
JB		 10538 if (! cpu_arch[j].flags.bitfield.cpui386)
10539 continue;
10540
91d6fa6a 10541 cpu_arch_name = cpu_arch[j].name;
6305a203 10542 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 10543 cpu_arch_flags = cpu_arch[j].flags;
10544 cpu_arch_isa = cpu_arch[j].type;
10545 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 10546 if (!cpu_arch_tune_set)
10547 {
10548 cpu_arch_tune = cpu_arch_isa;
10549 cpu_arch_tune_flags = cpu_arch_isa_flags;
10550 }
10551 break;
10552 }
91d6fa6a
NC		 10553 else if (*cpu_arch [j].name == '.'
10554 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203 10555 {
33eaf5de 10556 /* ISA extension. */
6305a203 10557 i386_cpu_flags flags;
309d3373 10558
293f5f65
L		 10559 flags = cpu_flags_or (cpu_arch_flags,
10560 cpu_arch[j].flags);
81486035 10561
5b64d091 10562 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 10563 {
10564 if (cpu_sub_arch_name)
10565 {
10566 char *name = cpu_sub_arch_name;
10567 cpu_sub_arch_name = concat (name,
91d6fa6a 10568 cpu_arch[j].name,
1bf57e9f 10569 (const char *) NULL);
6305a203
L		 10570 free (name);
10571 }
10572 else
91d6fa6a 10573 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 10574 cpu_arch_flags = flags;
a586129e 10575 cpu_arch_isa_flags = flags;
6305a203 10576 }
0089dace
L		 10577 else
10578 cpu_arch_isa_flags
10579 = cpu_flags_or (cpu_arch_isa_flags,
10580 cpu_arch[j].flags);
6305a203 10581 break;
ccc9c027 10582 }
9103f4f4 10583 }
6305a203 10584
293f5f65
L		 10585 if (j >= ARRAY_SIZE (cpu_arch))
10586 {
33eaf5de 10587 /* Disable an ISA extension. */
293f5f65
L		 10588 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10589 if (strcmp (arch, cpu_noarch [j].name) == 0)
10590 {
10591 i386_cpu_flags flags;
10592
10593 flags = cpu_flags_and_not (cpu_arch_flags,
10594 cpu_noarch[j].flags);
10595 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10596 {
10597 if (cpu_sub_arch_name)
10598 {
10599 char *name = cpu_sub_arch_name;
10600 cpu_sub_arch_name = concat (arch,
10601 (const char *) NULL);
10602 free (name);
10603 }
10604 else
10605 cpu_sub_arch_name = xstrdup (arch);
10606 cpu_arch_flags = flags;
10607 cpu_arch_isa_flags = flags;
10608 }
10609 break;
10610 }
10611
10612 if (j >= ARRAY_SIZE (cpu_noarch))
10613 j = ARRAY_SIZE (cpu_arch);
10614 }
10615
91d6fa6a 10616 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10617 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10618
10619 arch = next;
9103f4f4 10620 }
293f5f65
L		 10621 while (next != NULL);
10622 free (saved);
9103f4f4
L		 10623 break;
10624
10625 case OPTION_MTUNE:
10626 if (*arg == '.')
2b5d6a91 10627 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 10628 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10629 {
91d6fa6a 10630 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 10631 {
ccc9c027 10632 cpu_arch_tune_set = 1;
91d6fa6a
NC		 10633 cpu_arch_tune = cpu_arch [j].type;
10634 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 10635 break;
10636 }
10637 }
91d6fa6a 10638 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10639 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 10640 break;
10641
1efbbeb4
L		 10642 case OPTION_MMNEMONIC:
10643 if (strcasecmp (arg, "att") == 0)
10644 intel_mnemonic = 0;
10645 else if (strcasecmp (arg, "intel") == 0)
10646 intel_mnemonic = 1;
10647 else
2b5d6a91 10648 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 10649 break;
10650
10651 case OPTION_MSYNTAX:
10652 if (strcasecmp (arg, "att") == 0)
10653 intel_syntax = 0;
10654 else if (strcasecmp (arg, "intel") == 0)
10655 intel_syntax = 1;
10656 else
2b5d6a91 10657 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 10658 break;
10659
10660 case OPTION_MINDEX_REG:
10661 allow_index_reg = 1;
10662 break;
10663
10664 case OPTION_MNAKED_REG:
10665 allow_naked_reg = 1;
10666 break;
10667
c0f3af97
L		 10668 case OPTION_MSSE2AVX:
10669 sse2avx = 1;
10670 break;
10671
daf50ae7
L		 10672 case OPTION_MSSE_CHECK:
10673 if (strcasecmp (arg, "error") == 0)
7bab8ab5 10674 sse_check = check_error;
daf50ae7 10675 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 10676 sse_check = check_warning;
daf50ae7 10677 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10678 sse_check = check_none;
daf50ae7 10679 else
2b5d6a91 10680 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10681 break;
10682
7bab8ab5
JB		 10683 case OPTION_MOPERAND_CHECK:
10684 if (strcasecmp (arg, "error") == 0)
10685 operand_check = check_error;
10686 else if (strcasecmp (arg, "warning") == 0)
10687 operand_check = check_warning;
10688 else if (strcasecmp (arg, "none") == 0)
10689 operand_check = check_none;
10690 else
10691 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10692 break;
10693
539f890d
L		 10694 case OPTION_MAVXSCALAR:
10695 if (strcasecmp (arg, "128") == 0)
10696 avxscalar = vex128;
10697 else if (strcasecmp (arg, "256") == 0)
10698 avxscalar = vex256;
10699 else
2b5d6a91 10700 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10701 break;
10702
7e8b059b
L		 10703 case OPTION_MADD_BND_PREFIX:
10704 add_bnd_prefix = 1;
10705 break;
10706
43234a1e
L		 10707 case OPTION_MEVEXLIG:
10708 if (strcmp (arg, "128") == 0)
10709 evexlig = evexl128;
10710 else if (strcmp (arg, "256") == 0)
10711 evexlig = evexl256;
10712 else if (strcmp (arg, "512") == 0)
10713 evexlig = evexl512;
10714 else
10715 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10716 break;
10717
d3d3c6db
IT		 10718 case OPTION_MEVEXRCIG:
10719 if (strcmp (arg, "rne") == 0)
10720 evexrcig = rne;
10721 else if (strcmp (arg, "rd") == 0)
10722 evexrcig = rd;
10723 else if (strcmp (arg, "ru") == 0)
10724 evexrcig = ru;
10725 else if (strcmp (arg, "rz") == 0)
10726 evexrcig = rz;
10727 else
10728 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10729 break;
10730
43234a1e
L		 10731 case OPTION_MEVEXWIG:
10732 if (strcmp (arg, "0") == 0)
10733 evexwig = evexw0;
10734 else if (strcmp (arg, "1") == 0)
10735 evexwig = evexw1;
10736 else
10737 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10738 break;
10739
167ad85b
TG		 10740# if defined (TE_PE) || defined (TE_PEP)
10741 case OPTION_MBIG_OBJ:
10742 use_big_obj = 1;
10743 break;
10744#endif
10745
d1982f93 10746 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10747 if (strcasecmp (arg, "yes") == 0)
10748 omit_lock_prefix = 1;
10749 else if (strcasecmp (arg, "no") == 0)
10750 omit_lock_prefix = 0;
10751 else
10752 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10753 break;
10754
e4e00185
AS		 10755 case OPTION_MFENCE_AS_LOCK_ADD:
10756 if (strcasecmp (arg, "yes") == 0)
10757 avoid_fence = 1;
10758 else if (strcasecmp (arg, "no") == 0)
10759 avoid_fence = 0;
10760 else
10761 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10762 break;
10763
0cb4071e
L		 10764 case OPTION_MRELAX_RELOCATIONS:
10765 if (strcasecmp (arg, "yes") == 0)
10766 generate_relax_relocations = 1;
10767 else if (strcasecmp (arg, "no") == 0)
10768 generate_relax_relocations = 0;
10769 else
10770 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10771 break;
10772
5db04b09 10773 case OPTION_MAMD64:
e89c5eaa 10774 intel64 = 0;
5db04b09
L		 10775 break;
10776
10777 case OPTION_MINTEL64:
e89c5eaa 10778 intel64 = 1;
5db04b09
L		 10779 break;
10780
b6f8c7c4
L		 10781 case 'O':
10782 if (arg == NULL)
10783 {
10784 optimize = 1;
10785 /* Turn off -Os. */
10786 optimize_for_space = 0;
10787 }
10788 else if (*arg == 's')
10789 {
10790 optimize_for_space = 1;
10791 /* Turn on all encoding optimizations. */
10792 optimize = -1;
10793 }
10794 else
10795 {
10796 optimize = atoi (arg);
10797 /* Turn off -Os. */
10798 optimize_for_space = 0;
10799 }
10800 break;
10801
252b5132
RH		 10802 default:
10803 return 0;
10804 }
10805 return 1;
10806}
10807
8a2c8fef
L		 10808#define MESSAGE_TEMPLATE \
10809" "
10810
293f5f65
L		 10811static char *
10812output_message (FILE *stream, char *p, char *message, char *start,
10813 int *left_p, const char *name, int len)
10814{
10815 int size = sizeof (MESSAGE_TEMPLATE);
10816 int left = *left_p;
10817
10818 /* Reserve 2 spaces for ", " or ",\0" */
10819 left -= len + 2;
10820
10821 /* Check if there is any room. */
10822 if (left >= 0)
10823 {
10824 if (p != start)
10825 {
10826 *p++ = ',';
10827 *p++ = ' ';
10828 }
10829 p = mempcpy (p, name, len);
10830 }
10831 else
10832 {
10833 /* Output the current message now and start a new one. */
10834 *p++ = ',';
10835 *p = '\0';
10836 fprintf (stream, "%s\n", message);
10837 p = start;
10838 left = size - (start - message) - len - 2;
10839
10840 gas_assert (left >= 0);
10841
10842 p = mempcpy (p, name, len);
10843 }
10844
10845 *left_p = left;
10846 return p;
10847}
10848
8a2c8fef 10849static void
1ded5609 10850show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10851{
10852 static char message[] = MESSAGE_TEMPLATE;
10853 char *start = message + 27;
10854 char *p;
10855 int size = sizeof (MESSAGE_TEMPLATE);
10856 int left;
10857 const char *name;
10858 int len;
10859 unsigned int j;
10860
10861 p = start;
10862 left = size - (start - message);
10863 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10864 {
10865 /* Should it be skipped? */
10866 if (cpu_arch [j].skip)
10867 continue;
10868
10869 name = cpu_arch [j].name;
10870 len = cpu_arch [j].len;
10871 if (*name == '.')
10872 {
10873 /* It is an extension. Skip if we aren't asked to show it. */
10874 if (ext)
10875 {
10876 name++;
10877 len--;
10878 }
10879 else
10880 continue;
10881 }
10882 else if (ext)
10883 {
10884 /* It is an processor. Skip if we show only extension. */
10885 continue;
10886 }
1ded5609
JB		 10887 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10888 {
10889 /* It is an impossible processor - skip. */
10890 continue;
10891 }
8a2c8fef 10892
293f5f65 10893 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 10894 }
10895
293f5f65
L		 10896 /* Display disabled extensions. */
10897 if (ext)
10898 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10899 {
10900 name = cpu_noarch [j].name;
10901 len = cpu_noarch [j].len;
10902 p = output_message (stream, p, message, start, &left, name,
10903 len);
10904 }
10905
8a2c8fef
L		 10906 *p = '\0';
10907 fprintf (stream, "%s\n", message);
10908}
10909
252b5132 10910void
8a2c8fef 10911md_show_usage (FILE *stream)
252b5132 10912{
4cc782b5
ILT		 10913#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10914 fprintf (stream, _("\
a38cf1db
AM		 10915 -Q ignored\n\
10916 -V print assembler version number\n\
b3b91714
AM		 10917 -k ignored\n"));
10918#endif
10919 fprintf (stream, _("\
12b55ccc 10920 -n Do not optimize code alignment\n\
b3b91714
AM		 10921 -q quieten some warnings\n"));
10922#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10923 fprintf (stream, _("\
a38cf1db 10924 -s ignored\n"));
b3b91714 10925#endif
321098a5
L		 10926#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10927 || defined (TE_PE) || defined (TE_PEP))
751d281c 10928 fprintf (stream, _("\
570561f7 10929 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10930#endif
b3b91714
AM		 10931#ifdef SVR4_COMMENT_CHARS
10932 fprintf (stream, _("\
10933 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10934#else
10935 fprintf (stream, _("\
b3b91714 10936 --divide ignored\n"));
4cc782b5 10937#endif
9103f4f4 10938 fprintf (stream, _("\
6305a203 10939 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10940 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10941 show_arch (stream, 0, 1);
8a2c8fef
L		 10942 fprintf (stream, _("\
10943 EXTENSION is combination of:\n"));
1ded5609 10944 show_arch (stream, 1, 0);
6305a203 10945 fprintf (stream, _("\
8a2c8fef 10946 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10947 show_arch (stream, 0, 0);
ba104c83 10948 fprintf (stream, _("\
c0f3af97
L		 10949 -msse2avx encode SSE instructions with VEX prefix\n"));
10950 fprintf (stream, _("\
daf50ae7
L		 10951 -msse-check=[none|error|warning]\n\
10952 check SSE instructions\n"));
10953 fprintf (stream, _("\
7bab8ab5
JB		 10954 -moperand-check=[none|error|warning]\n\
10955 check operand combinations for validity\n"));
10956 fprintf (stream, _("\
539f890d
L		 10957 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10958 length\n"));
10959 fprintf (stream, _("\
43234a1e
L		 10960 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10961 length\n"));
10962 fprintf (stream, _("\
10963 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10964 for EVEX.W bit ignored instructions\n"));
10965 fprintf (stream, _("\
d3d3c6db
IT		 10966 -mevexrcig=[rne|rd|ru|rz]\n\
10967 encode EVEX instructions with specific EVEX.RC value\n\
10968 for SAE-only ignored instructions\n"));
10969 fprintf (stream, _("\
ba104c83
L		 10970 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10971 fprintf (stream, _("\
10972 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10973 fprintf (stream, _("\
10974 -mindex-reg support pseudo index registers\n"));
10975 fprintf (stream, _("\
10976 -mnaked-reg don't require `%%' prefix for registers\n"));
10977 fprintf (stream, _("\
7e8b059b 10978 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10979 fprintf (stream, _("\
10980 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10981# if defined (TE_PE) || defined (TE_PEP)
10982 fprintf (stream, _("\
10983 -mbig-obj generate big object files\n"));
10984#endif
d022bddd
IT		 10985 fprintf (stream, _("\
10986 -momit-lock-prefix=[no|yes]\n\
10987 strip all lock prefixes\n"));
5db04b09 10988 fprintf (stream, _("\
e4e00185
AS		 10989 -mfence-as-lock-add=[no|yes]\n\
10990 encode lfence, mfence and sfence as\n\
10991 lock addl $0x0, (%%{re}sp)\n"));
10992 fprintf (stream, _("\
0cb4071e
L		 10993 -mrelax-relocations=[no|yes]\n\
10994 generate relax relocations\n"));
10995 fprintf (stream, _("\
5db04b09
L		 10996 -mamd64 accept only AMD64 ISA\n"));
10997 fprintf (stream, _("\
10998 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10999}
11000
3e73aa7c 11001#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 11002 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 11003 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 11004
11005/* Pick the target format to use. */
11006
47926f60 11007const char *
e3bb37b5 11008i386_target_format (void)
252b5132 11009{
351f65ca
L		 11010 if (!strncmp (default_arch, "x86_64", 6))
11011 {
11012 update_code_flag (CODE_64BIT, 1);
11013 if (default_arch[6] == '\0')
7f56bc95 11014 x86_elf_abi = X86_64_ABI;
351f65ca 11015 else
7f56bc95 11016 x86_elf_abi = X86_64_X32_ABI;
351f65ca 11017 }
3e73aa7c 11018 else if (!strcmp (default_arch, "i386"))
78f12dd3 11019 update_code_flag (CODE_32BIT, 1);
5197d474
L		 11020 else if (!strcmp (default_arch, "iamcu"))
11021 {
11022 update_code_flag (CODE_32BIT, 1);
11023 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
11024 {
11025 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
11026 cpu_arch_name = "iamcu";
11027 cpu_sub_arch_name = NULL;
11028 cpu_arch_flags = iamcu_flags;
11029 cpu_arch_isa = PROCESSOR_IAMCU;
11030 cpu_arch_isa_flags = iamcu_flags;
11031 if (!cpu_arch_tune_set)
11032 {
11033 cpu_arch_tune = cpu_arch_isa;
11034 cpu_arch_tune_flags = cpu_arch_isa_flags;
11035 }
11036 }
8d471ec1 11037 else if (cpu_arch_isa != PROCESSOR_IAMCU)
5197d474
L		 11038 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11039 cpu_arch_name);
11040 }
3e73aa7c 11041 else
2b5d6a91 11042 as_fatal (_("unknown architecture"));
89507696
JB		 11043
11044 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11045 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11046 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11047 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11048
252b5132
RH		 11049 switch (OUTPUT_FLAVOR)
11050 {
9384f2ff 11051#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 11052 case bfd_target_aout_flavour:
47926f60 11053 return AOUT_TARGET_FORMAT;
4c63da97 11054#endif
9384f2ff
AM		 11055#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11056# if defined (TE_PE) || defined (TE_PEP)
11057 case bfd_target_coff_flavour:
167ad85b
TG		 11058 if (flag_code == CODE_64BIT)
11059 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11060 else
11061 return "pe-i386";
9384f2ff 11062# elif defined (TE_GO32)
0561d57c
JK		 11063 case bfd_target_coff_flavour:
11064 return "coff-go32";
9384f2ff 11065# else
252b5132
RH		 11066 case bfd_target_coff_flavour:
11067 return "coff-i386";
9384f2ff 11068# endif
4c63da97 11069#endif
3e73aa7c 11070#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 11071 case bfd_target_elf_flavour:
3e73aa7c 11072 {
351f65ca
L		 11073 const char *format;
11074
11075 switch (x86_elf_abi)
4fa24527 11076 {
351f65ca
L		 11077 default:
11078 format = ELF_TARGET_FORMAT;
11079 break;
7f56bc95 11080 case X86_64_ABI:
351f65ca 11081 use_rela_relocations = 1;
4fa24527 11082 object_64bit = 1;
351f65ca
L		 11083 format = ELF_TARGET_FORMAT64;
11084 break;
7f56bc95 11085 case X86_64_X32_ABI:
4fa24527 11086 use_rela_relocations = 1;
351f65ca 11087 object_64bit = 1;
862be3fb 11088 disallow_64bit_reloc = 1;
351f65ca
L		 11089 format = ELF_TARGET_FORMAT32;
11090 break;
4fa24527 11091 }
3632d14b 11092 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 11093 {
7f56bc95 11094 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 11095 as_fatal (_("Intel L1OM is 64bit only"));
11096 return ELF_TARGET_L1OM_FORMAT;
11097 }
b49f93f6 11098 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 11099 {
11100 if (x86_elf_abi != X86_64_ABI)
11101 as_fatal (_("Intel K1OM is 64bit only"));
11102 return ELF_TARGET_K1OM_FORMAT;
11103 }
81486035
L		 11104 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11105 {
11106 if (x86_elf_abi != I386_ABI)
11107 as_fatal (_("Intel MCU is 32bit only"));
11108 return ELF_TARGET_IAMCU_FORMAT;
11109 }
8a9036a4 11110 else
351f65ca 11111 return format;
3e73aa7c 11112 }
e57f8c65
TG		 11113#endif
11114#if defined (OBJ_MACH_O)
11115 case bfd_target_mach_o_flavour:
d382c579
TG		 11116 if (flag_code == CODE_64BIT)
11117 {
11118 use_rela_relocations = 1;
11119 object_64bit = 1;
11120 return "mach-o-x86-64";
11121 }
11122 else
11123 return "mach-o-i386";
4c63da97 11124#endif
252b5132
RH		 11125 default:
11126 abort ();
11127 return NULL;
11128 }
11129}
11130
47926f60 11131#endif /* OBJ_MAYBE_ more than one */
252b5132 11132\f
252b5132 11133symbolS *
7016a5d5 11134md_undefined_symbol (char *name)
252b5132 11135{
18dc2407
ILT		 11136 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11137 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11138 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11139 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 11140 {
11141 if (!GOT_symbol)
11142 {
11143 if (symbol_find (name))
11144 as_bad (_("GOT already in symbol table"));
11145 GOT_symbol = symbol_new (name, undefined_section,
11146 (valueT) 0, &zero_address_frag);
11147 };
11148 return GOT_symbol;
11149 }
252b5132
RH		 11150 return 0;
11151}
11152
11153/* Round up a section size to the appropriate boundary. */
47926f60 11154
252b5132 11155valueT
7016a5d5 11156md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 11157{
4c63da97
AM		 11158#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11159 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11160 {
11161 /* For a.out, force the section size to be aligned. If we don't do
11162 this, BFD will align it for us, but it will not write out the
11163 final bytes of the section. This may be a bug in BFD, but it is
11164 easier to fix it here since that is how the other a.out targets
11165 work. */
11166 int align;
11167
11168 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 11169 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 11170 }
252b5132
RH		 11171#endif
11172
11173 return size;
11174}
11175
11176/* On the i386, PC-relative offsets are relative to the start of the
11177 next instruction. That is, the address of the offset, plus its
11178 size, since the offset is always the last part of the insn. */
11179
11180long
e3bb37b5 11181md_pcrel_from (fixS *fixP)
252b5132
RH		 11182{
11183 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11184}
11185
11186#ifndef I386COFF
11187
11188static void
e3bb37b5 11189s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 11190{
29b0f896 11191 int temp;
252b5132 11192
8a75718c
JB		 11193#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11194 if (IS_ELF)
11195 obj_elf_section_change_hook ();
11196#endif
252b5132
RH		 11197 temp = get_absolute_expression ();
11198 subseg_set (bss_section, (subsegT) temp);
11199 demand_empty_rest_of_line ();
11200}
11201
11202#endif
11203
252b5132 11204void
e3bb37b5 11205i386_validate_fix (fixS *fixp)
252b5132 11206{
02a86693 11207 if (fixp->fx_subsy)
252b5132 11208 {
02a86693 11209 if (fixp->fx_subsy == GOT_symbol)
23df1078 11210 {
02a86693
L		 11211 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11212 {
11213 if (!object_64bit)
11214 abort ();
11215#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11216 if (fixp->fx_tcbit2)
56ceb5b5
L		 11217 fixp->fx_r_type = (fixp->fx_tcbit
11218 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11219 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 11220 else
11221#endif
11222 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11223 }
d6ab8113 11224 else
02a86693
L		 11225 {
11226 if (!object_64bit)
11227 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11228 else
11229 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11230 }
11231 fixp->fx_subsy = 0;
23df1078 11232 }
252b5132 11233 }
02a86693
L		 11234#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11235 else if (!object_64bit)
11236 {
11237 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11238 && fixp->fx_tcbit2)
11239 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11240 }
11241#endif
252b5132
RH		 11242}
11243
252b5132 11244arelent *
7016a5d5 11245tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 11246{
11247 arelent *rel;
11248 bfd_reloc_code_real_type code;
11249
11250 switch (fixp->fx_r_type)
11251 {
8ce3d284 11252#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 11253 case BFD_RELOC_SIZE32:
11254 case BFD_RELOC_SIZE64:
11255 if (S_IS_DEFINED (fixp->fx_addsy)
11256 && !S_IS_EXTERNAL (fixp->fx_addsy))
11257 {
11258 /* Resolve size relocation against local symbol to size of
11259 the symbol plus addend. */
11260 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11261 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11262 && !fits_in_unsigned_long (value))
11263 as_bad_where (fixp->fx_file, fixp->fx_line,
11264 _("symbol size computation overflow"));
11265 fixp->fx_addsy = NULL;
11266 fixp->fx_subsy = NULL;
11267 md_apply_fix (fixp, (valueT *) &value, NULL);
11268 return NULL;
11269 }
8ce3d284 11270#endif
1a0670f3 11271 /* Fall through. */
8fd4256d 11272
3e73aa7c
JH		 11273 case BFD_RELOC_X86_64_PLT32:
11274 case BFD_RELOC_X86_64_GOT32:
11275 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11276 case BFD_RELOC_X86_64_GOTPCRELX:
11277 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 11278 case BFD_RELOC_386_PLT32:
11279 case BFD_RELOC_386_GOT32:
02a86693 11280 case BFD_RELOC_386_GOT32X:
252b5132
RH		 11281 case BFD_RELOC_386_GOTOFF:
11282 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 11283 case BFD_RELOC_386_TLS_GD:
11284 case BFD_RELOC_386_TLS_LDM:
11285 case BFD_RELOC_386_TLS_LDO_32:
11286 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 11287 case BFD_RELOC_386_TLS_IE:
11288 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 11289 case BFD_RELOC_386_TLS_LE_32:
11290 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 11291 case BFD_RELOC_386_TLS_GOTDESC:
11292 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 11293 case BFD_RELOC_X86_64_TLSGD:
11294 case BFD_RELOC_X86_64_TLSLD:
11295 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 11296 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 11297 case BFD_RELOC_X86_64_GOTTPOFF:
11298 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 11299 case BFD_RELOC_X86_64_TPOFF64:
11300 case BFD_RELOC_X86_64_GOTOFF64:
11301 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 11302 case BFD_RELOC_X86_64_GOT64:
11303 case BFD_RELOC_X86_64_GOTPCREL64:
11304 case BFD_RELOC_X86_64_GOTPC64:
11305 case BFD_RELOC_X86_64_GOTPLT64:
11306 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 11307 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11308 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 11309 case BFD_RELOC_RVA:
11310 case BFD_RELOC_VTABLE_ENTRY:
11311 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 11312#ifdef TE_PE
11313 case BFD_RELOC_32_SECREL:
11314#endif
252b5132
RH		 11315 code = fixp->fx_r_type;
11316 break;
dbbaec26
L		 11317 case BFD_RELOC_X86_64_32S:
11318 if (!fixp->fx_pcrel)
11319 {
11320 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11321 code = fixp->fx_r_type;
11322 break;
11323 }
1a0670f3 11324 /* Fall through. */
252b5132 11325 default:
93382f6d 11326 if (fixp->fx_pcrel)
252b5132 11327 {
93382f6d
AM		 11328 switch (fixp->fx_size)
11329 {
11330 default:
b091f402
AM		 11331 as_bad_where (fixp->fx_file, fixp->fx_line,
11332 _("can not do %d byte pc-relative relocation"),
11333 fixp->fx_size);
93382f6d
AM		 11334 code = BFD_RELOC_32_PCREL;
11335 break;
11336 case 1: code = BFD_RELOC_8_PCREL; break;
11337 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 11338 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 11339#ifdef BFD64
11340 case 8: code = BFD_RELOC_64_PCREL; break;
11341#endif
93382f6d
AM		 11342 }
11343 }
11344 else
11345 {
11346 switch (fixp->fx_size)
11347 {
11348 default:
b091f402
AM		 11349 as_bad_where (fixp->fx_file, fixp->fx_line,
11350 _("can not do %d byte relocation"),
11351 fixp->fx_size);
93382f6d
AM		 11352 code = BFD_RELOC_32;
11353 break;
11354 case 1: code = BFD_RELOC_8; break;
11355 case 2: code = BFD_RELOC_16; break;
11356 case 4: code = BFD_RELOC_32; break;
937149dd 11357#ifdef BFD64
3e73aa7c 11358 case 8: code = BFD_RELOC_64; break;
937149dd 11359#endif
93382f6d 11360 }
252b5132
RH		 11361 }
11362 break;
11363 }
252b5132 11364
d182319b
JB		 11365 if ((code == BFD_RELOC_32
11366 || code == BFD_RELOC_32_PCREL
11367 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 11368 && GOT_symbol
11369 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 11370 {
4fa24527 11371 if (!object_64bit)
d6ab8113
JB		 11372 code = BFD_RELOC_386_GOTPC;
11373 else
11374 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 11375 }
7b81dfbb
AJ		 11376 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11377 && GOT_symbol
11378 && fixp->fx_addsy == GOT_symbol)
11379 {
11380 code = BFD_RELOC_X86_64_GOTPC64;
11381 }
252b5132 11382
add39d23
TS		 11383 rel = XNEW (arelent);
11384 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 11385 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 11386
11387 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 11388
3e73aa7c
JH		 11389 if (!use_rela_relocations)
11390 {
11391 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11392 vtable entry to be used in the relocation's section offset. */
11393 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11394 rel->address = fixp->fx_offset;
fbeb56a4
DK		 11395#if defined (OBJ_COFF) && defined (TE_PE)
11396 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11397 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11398 else
11399#endif
c6682705 11400 rel->addend = 0;
3e73aa7c
JH		 11401 }
11402 /* Use the rela in 64bit mode. */
252b5132 11403 else
3e73aa7c 11404 {
862be3fb
L		 11405 if (disallow_64bit_reloc)
11406 switch (code)
11407 {
862be3fb
L		 11408 case BFD_RELOC_X86_64_DTPOFF64:
11409 case BFD_RELOC_X86_64_TPOFF64:
11410 case BFD_RELOC_64_PCREL:
11411 case BFD_RELOC_X86_64_GOTOFF64:
11412 case BFD_RELOC_X86_64_GOT64:
11413 case BFD_RELOC_X86_64_GOTPCREL64:
11414 case BFD_RELOC_X86_64_GOTPC64:
11415 case BFD_RELOC_X86_64_GOTPLT64:
11416 case BFD_RELOC_X86_64_PLTOFF64:
11417 as_bad_where (fixp->fx_file, fixp->fx_line,
11418 _("cannot represent relocation type %s in x32 mode"),
11419 bfd_get_reloc_code_name (code));
11420 break;
11421 default:
11422 break;
11423 }
11424
062cd5e7
AS		 11425 if (!fixp->fx_pcrel)
11426 rel->addend = fixp->fx_offset;
11427 else
11428 switch (code)
11429 {
11430 case BFD_RELOC_X86_64_PLT32:
11431 case BFD_RELOC_X86_64_GOT32:
11432 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11433 case BFD_RELOC_X86_64_GOTPCRELX:
11434 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 11435 case BFD_RELOC_X86_64_TLSGD:
11436 case BFD_RELOC_X86_64_TLSLD:
11437 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 11438 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11439 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 11440 rel->addend = fixp->fx_offset - fixp->fx_size;
11441 break;
11442 default:
11443 rel->addend = (section->vma
11444 - fixp->fx_size
11445 + fixp->fx_addnumber
11446 + md_pcrel_from (fixp));
11447 break;
11448 }
3e73aa7c
JH		 11449 }
11450
252b5132
RH		 11451 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11452 if (rel->howto == NULL)
11453 {
11454 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 11455 _("cannot represent relocation type %s"),
252b5132
RH		 11456 bfd_get_reloc_code_name (code));
11457 /* Set howto to a garbage value so that we can keep going. */
11458 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 11459 gas_assert (rel->howto != NULL);
252b5132
RH		 11460 }
11461
11462 return rel;
11463}
11464
ee86248c 11465#include "tc-i386-intel.c"
54cfded0 11466
a60de03c
JB		 11467void
11468tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 11469{
a60de03c
JB		 11470 int saved_naked_reg;
11471 char saved_register_dot;
54cfded0 11472
a60de03c
JB		 11473 saved_naked_reg = allow_naked_reg;
11474 allow_naked_reg = 1;
11475 saved_register_dot = register_chars['.'];
11476 register_chars['.'] = '.';
11477 allow_pseudo_reg = 1;
11478 expression_and_evaluate (exp);
11479 allow_pseudo_reg = 0;
11480 register_chars['.'] = saved_register_dot;
11481 allow_naked_reg = saved_naked_reg;
11482
e96d56a1 11483 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 11484 {
a60de03c
JB		 11485 if ((addressT) exp->X_add_number < i386_regtab_size)
11486 {
11487 exp->X_op = O_constant;
11488 exp->X_add_number = i386_regtab[exp->X_add_number]
11489 .dw2_regnum[flag_code >> 1];
11490 }
11491 else
11492 exp->X_op = O_illegal;
54cfded0 11493 }
54cfded0
AM		 11494}
11495
11496void
11497tc_x86_frame_initial_instructions (void)
11498{
a60de03c
JB		 11499 static unsigned int sp_regno[2];
11500
11501 if (!sp_regno[flag_code >> 1])
11502 {
11503 char *saved_input = input_line_pointer;
11504 char sp[][4] = {"esp", "rsp"};
11505 expressionS exp;
a4447b93 11506
a60de03c
JB		 11507 input_line_pointer = sp[flag_code >> 1];
11508 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 11509 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 11510 sp_regno[flag_code >> 1] = exp.X_add_number;
11511 input_line_pointer = saved_input;
11512 }
a4447b93 11513
61ff971f
L		 11514 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11515 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 11516}
d2b2c203 11517
d7921315
L		 11518int
11519x86_dwarf2_addr_size (void)
11520{
11521#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11522 if (x86_elf_abi == X86_64_X32_ABI)
11523 return 4;
11524#endif
11525 return bfd_arch_bits_per_address (stdoutput) / 8;
11526}
11527
d2b2c203
DJ		 11528int
11529i386_elf_section_type (const char *str, size_t len)
11530{
11531 if (flag_code == CODE_64BIT
11532 && len == sizeof ("unwind") - 1
11533 && strncmp (str, "unwind", 6) == 0)
11534 return SHT_X86_64_UNWIND;
11535
11536 return -1;
11537}
bb41ade5 11538
ad5fec3b
EB		 11539#ifdef TE_SOLARIS
11540void
11541i386_solaris_fix_up_eh_frame (segT sec)
11542{
11543 if (flag_code == CODE_64BIT)
11544 elf_section_type (sec) = SHT_X86_64_UNWIND;
11545}
11546#endif
11547
bb41ade5
AM		 11548#ifdef TE_PE
11549void
11550tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11551{
91d6fa6a 11552 expressionS exp;
bb41ade5 11553
91d6fa6a
NC		 11554 exp.X_op = O_secrel;
11555 exp.X_add_symbol = symbol;
11556 exp.X_add_number = 0;
11557 emit_expr (&exp, size);
bb41ade5
AM		 11558}
11559#endif
3b22753a
L		 11560
11561#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11562/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11563
01e1a5bc 11564bfd_vma
6d4af3c2 11565x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 11566{
11567 if (flag_code == CODE_64BIT)
11568 {
11569 if (letter == 'l')
11570 return SHF_X86_64_LARGE;
11571
8f3bae45 11572 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 11573 }
3b22753a 11574 else
8f3bae45 11575 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 11576 return -1;
11577}
11578
01e1a5bc 11579bfd_vma
3b22753a
L		 11580x86_64_section_word (char *str, size_t len)
11581{
8620418b 11582 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 11583 return SHF_X86_64_LARGE;
11584
11585 return -1;
11586}
11587
11588static void
11589handle_large_common (int small ATTRIBUTE_UNUSED)
11590{
11591 if (flag_code != CODE_64BIT)
11592 {
11593 s_comm_internal (0, elf_common_parse);
11594 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11595 }
11596 else
11597 {
11598 static segT lbss_section;
11599 asection *saved_com_section_ptr = elf_com_section_ptr;
11600 asection *saved_bss_section = bss_section;
11601
11602 if (lbss_section == NULL)
11603 {
11604 flagword applicable;
11605 segT seg = now_seg;
11606 subsegT subseg = now_subseg;
11607
11608 /* The .lbss section is for local .largecomm symbols. */
11609 lbss_section = subseg_new (".lbss", 0);
11610 applicable = bfd_applicable_section_flags (stdoutput);
11611 bfd_set_section_flags (stdoutput, lbss_section,
11612 applicable & SEC_ALLOC);
11613 seg_info (lbss_section)->bss = 1;
11614
11615 subseg_set (seg, subseg);
11616 }
11617
11618 elf_com_section_ptr = &_bfd_elf_large_com_section;
11619 bss_section = lbss_section;
11620
11621 s_comm_internal (0, elf_common_parse);
11622
11623 elf_com_section_ptr = saved_com_section_ptr;
11624 bss_section = saved_bss_section;
11625 }
11626}
11627#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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