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Fixes a problem exposed by the aarcg64/illegal.s test case - where the assembler was
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
4b95cf5c 2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d
L		 68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
22109423 136 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 137}
138arch_entry;
139
78f12dd3 140static void update_code_flag (int, int);
e3bb37b5
L		 141static void set_code_flag (int);
142static void set_16bit_gcc_code_flag (int);
143static void set_intel_syntax (int);
1efbbeb4 144static void set_intel_mnemonic (int);
db51cc60 145static void set_allow_index_reg (int);
7bab8ab5 146static void set_check (int);
e3bb37b5 147static void set_cpu_arch (int);
6482c264 148#ifdef TE_PE
e3bb37b5 149static void pe_directive_secrel (int);
6482c264 150#endif
e3bb37b5
L		 151static void signed_cons (int);
152static char *output_invalid (int c);
ee86248c
JB		 153static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
154 const char *);
155static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
156 const char *);
a7619375 157static int i386_att_operand (char *);
e3bb37b5 158static int i386_intel_operand (char *, int);
ee86248c
JB		 159static int i386_intel_simplify (expressionS *);
160static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 161static const reg_entry *parse_register (char *, char **);
162static char *parse_insn (char *, char *);
163static char *parse_operands (char *, const char *);
164static void swap_operands (void);
4d456e3d 165static void swap_2_operands (int, int);
e3bb37b5
L		 166static void optimize_imm (void);
167static void optimize_disp (void);
d3ce72d0 168static const insn_template *match_template (void);
e3bb37b5
L		 169static int check_string (void);
170static int process_suffix (void);
171static int check_byte_reg (void);
172static int check_long_reg (void);
173static int check_qword_reg (void);
174static int check_word_reg (void);
175static int finalize_imm (void);
176static int process_operands (void);
177static const seg_entry *build_modrm_byte (void);
178static void output_insn (void);
179static void output_imm (fragS *, offsetT);
180static void output_disp (fragS *, offsetT);
29b0f896 181#ifndef I386COFF
e3bb37b5 182static void s_bss (int);
252b5132 183#endif
17d4e2a2
L		 184#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185static void handle_large_common (int small ATTRIBUTE_UNUSED);
186#endif
252b5132 187
a847613f 188static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 189
43234a1e
L		 190/* This struct describes rounding control and SAE in the instruction. */
191struct RC_Operation
192{
193 enum rc_type
194 {
195 rne = 0,
196 rd,
197 ru,
198 rz,
199 saeonly
200 } type;
201 int operand;
202};
203
204static struct RC_Operation rc_op;
205
206/* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209struct Mask_Operation
210{
211 const reg_entry *mask;
212 unsigned int zeroing;
213 /* The operand where this operation is associated. */
214 int operand;
215};
216
217static struct Mask_Operation mask_op;
218
219/* The struct describes broadcasting, applied to OPERAND. FACTOR is
220 broadcast factor. */
221struct Broadcast_Operation
222{
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
224 int type;
225
226 /* Index of broadcasted operand. */
227 int operand;
228};
229
230static struct Broadcast_Operation broadcast_op;
231
c0f3af97
L		 232/* VEX prefix. */
233typedef struct
234{
43234a1e
L		 235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes[4];
c0f3af97
L		 237 unsigned int length;
238 /* Destination or source register specifier. */
239 const reg_entry *register_specifier;
240} vex_prefix;
241
252b5132 242/* 'md_assemble ()' gathers together information and puts it into a
47926f60 243 i386_insn. */
252b5132 244
520dc8e8
AM		 245union i386_op
246 {
247 expressionS *disps;
248 expressionS *imms;
249 const reg_entry *regs;
250 };
251
a65babc9
L		 252enum i386_error
253 {
86e026a4 254 operand_size_mismatch,
a65babc9
L		 255 operand_type_mismatch,
256 register_type_mismatch,
257 number_of_operands_mismatch,
258 invalid_instruction_suffix,
259 bad_imm4,
260 old_gcc_only,
261 unsupported_with_intel_mnemonic,
262 unsupported_syntax,
6c30d220
L		 263 unsupported,
264 invalid_vsib_address,
7bab8ab5 265 invalid_vector_register_set,
43234a1e
L		 266 unsupported_vector_index_register,
267 unsupported_broadcast,
268 broadcast_not_on_src_operand,
269 broadcast_needed,
270 unsupported_masking,
271 mask_not_on_destination,
272 no_default_mask,
273 unsupported_rc_sae,
274 rc_sae_operand_not_last_imm,
275 invalid_register_operand,
276 try_vector_disp8
a65babc9
L		 277 };
278
252b5132
RH		 279struct _i386_insn
280 {
47926f60 281 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 282 insn_template tm;
252b5132 283
7d5e4556
L		 284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
252b5132
RH		 286 char suffix;
287
47926f60 288 /* OPERANDS gives the number of given operands. */
252b5132
RH		 289 unsigned int operands;
290
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
47926f60 293 operands. */
252b5132
RH		 294 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
295
296 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 297 use OP[i] for the corresponding operand. */
40fb9820 298 i386_operand_type types[MAX_OPERANDS];
252b5132 299
520dc8e8
AM		 300 /* Displacement expression, immediate expression, or register for each
301 operand. */
302 union i386_op op[MAX_OPERANDS];
252b5132 303
3e73aa7c
JH		 304 /* Flags for operands. */
305 unsigned int flags[MAX_OPERANDS];
306#define Operand_PCrel 1
307
252b5132 308 /* Relocation type for operand */
f86103b7 309 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 310
252b5132
RH		 311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry *base_reg;
314 const reg_entry *index_reg;
315 unsigned int log2_scale_factor;
316
317 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 318 explicit segment overrides are given. */
ce8a8b2f 319 const seg_entry *seg[2];
252b5132
RH		 320
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes;
324 unsigned char prefix[MAX_PREFIXES];
325
326 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 327 addressing modes of this insn are encoded. */
252b5132 328 modrm_byte rm;
3e73aa7c 329 rex_byte rex;
43234a1e 330 rex_byte vrex;
252b5132 331 sib_byte sib;
c0f3af97 332 vex_prefix vex;
b6169b20 333
43234a1e
L		 334 /* Masking attributes. */
335 struct Mask_Operation *mask;
336
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation *rounding;
339
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation *broadcast;
342
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift;
345
b6169b20 346 /* Swap operand in encoding. */
4473e004 347 unsigned int swap_operand;
891edac4 348
a501d77e
L		 349 /* Prefer 8bit or 32bit displacement in encoding. */
350 enum
351 {
352 disp_encoding_default = 0,
353 disp_encoding_8bit,
354 disp_encoding_32bit
355 } disp_encoding;
f8a5c266 356
d5de92cf
L		 357 /* REP prefix. */
358 const char *rep_prefix;
359
165de32a
L		 360 /* HLE prefix. */
361 const char *hle_prefix;
42164a71 362
7e8b059b
L		 363 /* Have BND prefix. */
364 const char *bnd_prefix;
365
43234a1e
L		 366 /* Need VREX to support upper 16 registers. */
367 int need_vrex;
368
891edac4 369 /* Error message. */
a65babc9 370 enum i386_error error;
252b5132
RH		 371 };
372
373typedef struct _i386_insn i386_insn;
374
43234a1e
L		 375/* Link RC type with corresponding string, that'll be looked for in
376 asm. */
377struct RC_name
378{
379 enum rc_type type;
380 const char *name;
381 unsigned int len;
382};
383
384static const struct RC_name RC_NamesTable[] =
385{
386 { rne, STRING_COMMA_LEN ("rn-sae") },
387 { rd, STRING_COMMA_LEN ("rd-sae") },
388 { ru, STRING_COMMA_LEN ("ru-sae") },
389 { rz, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly, STRING_COMMA_LEN ("sae") },
391};
392
252b5132
RH		 393/* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 395const char extra_symbol_chars[] = "*%-([{"
252b5132 396#ifdef LEX_AT
32137342
NC		 397 "@"
398#endif
399#ifdef LEX_QM
400 "?"
252b5132 401#endif
32137342 402 ;
252b5132 403
29b0f896
AM		 404#if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 406 && !defined (TE_GNU) \
29b0f896 407 && !defined (TE_LINUX) \
8d63c93e
RM		 408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
29b0f896 410 && !defined (TE_FreeBSD) \
5b806d27 411 && !defined (TE_DragonFly) \
29b0f896 412 && !defined (TE_NetBSD)))
252b5132 413/* This array holds the chars that always start a comment. If the
b3b91714
AM		 414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416const char *i386_comment_chars = "#/";
417#define SVR4_COMMENT_CHARS 1
252b5132 418#define PREFIX_SEPARATOR '\\'
252b5132 419
b3b91714
AM		 420#else
421const char *i386_comment_chars = "#";
422#define PREFIX_SEPARATOR '/'
423#endif
424
252b5132
RH		 425/* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 429 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
252b5132 432 '/' isn't otherwise defined. */
b3b91714 433const char line_comment_chars[] = "#/";
252b5132 434
63a0b638 435const char line_separator_chars[] = ";";
252b5132 436
ce8a8b2f
AM		 437/* Chars that can be used to separate mant from exp in floating point
438 nums. */
252b5132
RH		 439const char EXP_CHARS[] = "eE";
440
ce8a8b2f
AM		 441/* Chars that mean this number is a floating point constant
442 As in 0f12.456
443 or 0d1.2345e12. */
252b5132
RH		 444const char FLT_CHARS[] = "fFdDxX";
445
ce8a8b2f 446/* Tables for lexical analysis. */
252b5132
RH		 447static char mnemonic_chars[256];
448static char register_chars[256];
449static char operand_chars[256];
450static char identifier_chars[256];
451static char digit_chars[256];
452
ce8a8b2f 453/* Lexical macros. */
252b5132
RH		 454#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455#define is_operand_char(x) (operand_chars[(unsigned char) x])
456#define is_register_char(x) (register_chars[(unsigned char) x])
457#define is_space_char(x) ((x) == ' ')
458#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459#define is_digit_char(x) (digit_chars[(unsigned char) x])
460
0234cb7c 461/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 462static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
463
464/* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
47926f60 467 assembler instruction). */
252b5132 468static char save_stack[32];
ce8a8b2f 469static char *save_stack_p;
252b5132
RH		 470#define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472#define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
474
47926f60 475/* The instruction we're assembling. */
252b5132
RH		 476static i386_insn i;
477
478/* Possible templates for current insn. */
479static const templates *current_templates;
480
31b2323c
L		 481/* Per instruction expressionS buffers: max displacements & immediates. */
482static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
483static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 484
47926f60 485/* Current operand we are working on. */
ee86248c 486static int this_operand = -1;
252b5132 487
3e73aa7c
JH		 488/* We support four different modes. FLAG_CODE variable is used to distinguish
489 these. */
490
491enum flag_code {
492 CODE_32BIT,
493 CODE_16BIT,
494 CODE_64BIT };
495
496static enum flag_code flag_code;
4fa24527 497static unsigned int object_64bit;
862be3fb 498static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 499static int use_rela_relocations = 0;
500
7af8ed2d
NC		 501#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
504
351f65ca
L		 505/* The ELF ABI to use. */
506enum x86_elf_abi
507{
508 I386_ABI,
7f56bc95
L		 509 X86_64_ABI,
510 X86_64_X32_ABI
351f65ca
L		 511};
512
513static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 514#endif
351f65ca 515
167ad85b
TG		 516#if defined (TE_PE) || defined (TE_PEP)
517/* Use big object file format. */
518static int use_big_obj = 0;
519#endif
520
47926f60
KH		 521/* 1 for intel syntax,
522 0 if att syntax. */
523static int intel_syntax = 0;
252b5132 524
1efbbeb4
L		 525/* 1 for intel mnemonic,
526 0 if att mnemonic. */
527static int intel_mnemonic = !SYSV386_COMPAT;
528
5209009a 529/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 530static int old_gcc = OLDGCC_COMPAT;
531
a60de03c
JB		 532/* 1 if pseudo registers are permitted. */
533static int allow_pseudo_reg = 0;
534
47926f60
KH		 535/* 1 if register prefix % not required. */
536static int allow_naked_reg = 0;
252b5132 537
7e8b059b
L		 538/* 1 if the assembler should add BND prefix for all control-tranferring
539 instructions supporting it, even if this prefix wasn't specified
540 explicitly. */
541static int add_bnd_prefix = 0;
542
ba104c83 543/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 544static int allow_index_reg = 0;
545
7bab8ab5 546static enum check_kind
daf50ae7 547 {
7bab8ab5
JB		 548 check_none = 0,
549 check_warning,
550 check_error
daf50ae7 551 }
7bab8ab5 552sse_check, operand_check = check_warning;
daf50ae7 553
2ca3ace5
L		 554/* Register prefix used for error message. */
555static const char *register_prefix = "%";
556
47926f60
KH		 557/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
558 leave, push, and pop instructions so that gcc has the same stack
559 frame as in 32 bit mode. */
560static char stackop_size = '\0';
eecb386c 561
12b55ccc
L		 562/* Non-zero to optimize code alignment. */
563int optimize_align_code = 1;
564
47926f60
KH		 565/* Non-zero to quieten some warnings. */
566static int quiet_warnings = 0;
a38cf1db 567
47926f60
KH		 568/* CPU name. */
569static const char *cpu_arch_name = NULL;
6305a203 570static char *cpu_sub_arch_name = NULL;
a38cf1db 571
47926f60 572/* CPU feature flags. */
40fb9820
L		 573static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
574
ccc9c027
L		 575/* If we have selected a cpu we are generating instructions for. */
576static int cpu_arch_tune_set = 0;
577
9103f4f4 578/* Cpu we are generating instructions for. */
fbf3f584 579enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 580
581/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 582static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 583
ccc9c027 584/* CPU instruction set architecture used. */
fbf3f584 585enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 586
9103f4f4 587/* CPU feature flags of instruction set architecture used. */
fbf3f584 588i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 589
fddf5b5b
AM		 590/* If set, conditional jumps are not automatically promoted to handle
591 larger than a byte offset. */
592static unsigned int no_cond_jump_promotion = 0;
593
c0f3af97
L		 594/* Encode SSE instructions with VEX prefix. */
595static unsigned int sse2avx;
596
539f890d
L		 597/* Encode scalar AVX instructions with specific vector length. */
598static enum
599 {
600 vex128 = 0,
601 vex256
602 } avxscalar;
603
43234a1e
L		 604/* Encode scalar EVEX LIG instructions with specific vector length. */
605static enum
606 {
607 evexl128 = 0,
608 evexl256,
609 evexl512
610 } evexlig;
611
612/* Encode EVEX WIG instructions with specific evex.w. */
613static enum
614 {
615 evexw0 = 0,
616 evexw1
617 } evexwig;
618
29b0f896 619/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 620static symbolS *GOT_symbol;
29b0f896 621
a4447b93
RH		 622/* The dwarf2 return column, adjusted for 32 or 64 bit. */
623unsigned int x86_dwarf2_return_column;
624
625/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
626int x86_cie_data_alignment;
627
252b5132 628/* Interface to relax_segment.
fddf5b5b
AM		 629 There are 3 major relax states for 386 jump insns because the
630 different types of jumps add different sizes to frags when we're
631 figuring out what sort of jump to choose to reach a given label. */
252b5132 632
47926f60 633/* Types. */
93c2a809
AM		 634#define UNCOND_JUMP 0
635#define COND_JUMP 1
636#define COND_JUMP86 2
fddf5b5b 637
47926f60 638/* Sizes. */
252b5132
RH		 639#define CODE16 1
640#define SMALL 0
29b0f896 641#define SMALL16 (SMALL | CODE16)
252b5132 642#define BIG 2
29b0f896 643#define BIG16 (BIG | CODE16)
252b5132
RH		 644
645#ifndef INLINE
646#ifdef __GNUC__
647#define INLINE __inline__
648#else
649#define INLINE
650#endif
651#endif
652
fddf5b5b
AM		 653#define ENCODE_RELAX_STATE(type, size) \
654 ((relax_substateT) (((type) << 2) | (size)))
655#define TYPE_FROM_RELAX_STATE(s) \
656 ((s) >> 2)
657#define DISP_SIZE_FROM_RELAX_STATE(s) \
658 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 659
660/* This table is used by relax_frag to promote short jumps to long
661 ones where necessary. SMALL (short) jumps may be promoted to BIG
662 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
663 don't allow a short jump in a 32 bit code segment to be promoted to
664 a 16 bit offset jump because it's slower (requires data size
665 prefix), and doesn't work, unless the destination is in the bottom
666 64k of the code segment (The top 16 bits of eip are zeroed). */
667
668const relax_typeS md_relax_table[] =
669{
24eab124
AM		 670 /* The fields are:
671 1) most positive reach of this state,
672 2) most negative reach of this state,
93c2a809 673 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 674 4) which index into the table to try if we can't fit into this one. */
252b5132 675
fddf5b5b 676 /* UNCOND_JUMP states. */
93c2a809
AM		 677 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
678 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
679 /* dword jmp adds 4 bytes to frag:
680 0 extra opcode bytes, 4 displacement bytes. */
252b5132 681 {0, 0, 4, 0},
93c2a809
AM		 682 /* word jmp adds 2 byte2 to frag:
683 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 684 {0, 0, 2, 0},
685
93c2a809
AM		 686 /* COND_JUMP states. */
687 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
688 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
689 /* dword conditionals adds 5 bytes to frag:
690 1 extra opcode byte, 4 displacement bytes. */
691 {0, 0, 5, 0},
fddf5b5b 692 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 693 1 extra opcode byte, 2 displacement bytes. */
694 {0, 0, 3, 0},
695
696 /* COND_JUMP86 states. */
697 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
698 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
699 /* dword conditionals adds 5 bytes to frag:
700 1 extra opcode byte, 4 displacement bytes. */
701 {0, 0, 5, 0},
702 /* word conditionals add 4 bytes to frag:
703 1 displacement byte and a 3 byte long branch insn. */
704 {0, 0, 4, 0}
252b5132
RH		 705};
706
9103f4f4
L		 707static const arch_entry cpu_arch[] =
708{
89507696
JB		 709 /* Do not replace the first two entries - i386_target_format()
710 relies on them being there in this order. */
8a2c8fef 711 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 712 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 713 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 714 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 715 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 716 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 717 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 718 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 719 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 720 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 721 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 722 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 723 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 724 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 725 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 726 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 727 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 728 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 729 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 730 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 731 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 732 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 733 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 734 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 735 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 736 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 737 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 738 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 739 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 740 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 741 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 742 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 743 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 744 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 745 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 746 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 747 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 748 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 749 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 750 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 751 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 752 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 753 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 754 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 755 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
756 CPU_K1OM_FLAGS, 0, 0 },
8a2c8fef 757 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 758 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 759 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 760 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 761 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 762 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 763 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 764 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 765 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 766 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 767 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 768 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 769 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 770 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 771 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 772 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 773 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 774 CPU_BDVER2_FLAGS, 0, 0 },
5e5c50d3
NE		 775 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
776 CPU_BDVER3_FLAGS, 0, 0 },
c7b0bd56
SE		 777 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
778 CPU_BDVER4_FLAGS, 0, 0 },
7b458c12
L		 779 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
780 CPU_BTVER1_FLAGS, 0, 0 },
781 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
782 CPU_BTVER2_FLAGS, 0, 0 },
8a2c8fef 783 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 784 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 785 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 786 CPU_287_FLAGS, 0, 0 },
8a2c8fef 787 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 788 CPU_387_FLAGS, 0, 0 },
8a2c8fef 789 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 790 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 791 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 792 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 793 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 794 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 795 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 796 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 797 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 798 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 799 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 800 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 801 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 802 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 803 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 804 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 805 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 806 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 807 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 808 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 809 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 810 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 811 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 812 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 813 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
814 CPU_AVX2_FLAGS, 0, 0 },
43234a1e
L		 815 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
816 CPU_AVX512F_FLAGS, 0, 0 },
817 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
818 CPU_AVX512CD_FLAGS, 0, 0 },
819 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
820 CPU_AVX512ER_FLAGS, 0, 0 },
821 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
822 CPU_AVX512PF_FLAGS, 0, 0 },
8a2c8fef 823 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 824 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 825 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 826 CPU_VMX_FLAGS, 0, 0 },
8729a6f6
L		 827 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
828 CPU_VMFUNC_FLAGS, 0, 0 },
8a2c8fef 829 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 830 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 831 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 832 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 833 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 834 CPU_XSAVEOPT_FLAGS, 0, 0 },
8a2c8fef 835 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 836 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 837 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 838 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 839 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 840 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 841 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 842 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 843 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 844 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 845 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 846 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 847 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
848 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 849 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 850 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 851 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 852 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 853 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 854 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 855 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 856 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 857 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 858 CPU_MOVBE_FLAGS, 0, 0 },
60aa667e
L		 859 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
860 CPU_CX16_FLAGS, 0, 0 },
8a2c8fef 861 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 862 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 863 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
864 CPU_LZCNT_FLAGS, 0, 0 },
42164a71
L		 865 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
866 CPU_HLE_FLAGS, 0, 0 },
867 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
868 CPU_RTM_FLAGS, 0, 0 },
6c30d220
L		 869 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
870 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 871 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 872 CPU_CLFLUSH_FLAGS, 0, 0 },
873 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
874 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 875 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 876 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 877 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 878 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 879 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 880 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 881 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 882 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 883 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 884 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 885 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 886 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 887 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 888 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 889 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 890 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 891 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 892 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 893 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
894 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 895 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
896 CPU_TBM_FLAGS, 0, 0 },
e2e1fcde
L		 897 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
898 CPU_ADX_FLAGS, 0, 0 },
899 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
900 CPU_RDSEED_FLAGS, 0, 0 },
901 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
902 CPU_PRFCHW_FLAGS, 0, 0 },
5c111e37
L		 903 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
904 CPU_SMAP_FLAGS, 0, 0 },
7e8b059b
L		 905 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
906 CPU_MPX_FLAGS, 0, 0 },
a0046408
L		 907 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
908 CPU_SHA_FLAGS, 0, 0 },
963f3586
IT		 909 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
910 CPU_CLFLUSHOPT_FLAGS, 0, 0 },
911 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
912 CPU_XSAVEC_FLAGS, 0, 0 },
913 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
914 CPU_XSAVES_FLAGS, 0, 0 },
dcf893b5
IT		 915 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
916 CPU_PREFETCHWT1_FLAGS, 0, 0 },
2cf200a4
IT		 917 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
918 CPU_SE1_FLAGS, 0, 0 },
e413e4e9
AM		 919};
920
704209c0 921#ifdef I386COFF
a6c24e68
NC		 922/* Like s_lcomm_internal in gas/read.c but the alignment string
923 is allowed to be optional. */
924
925static symbolS *
926pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
927{
928 addressT align = 0;
929
930 SKIP_WHITESPACE ();
931
7ab9ffdd 932 if (needs_align
a6c24e68
NC		 933 && *input_line_pointer == ',')
934 {
935 align = parse_align (needs_align - 1);
7ab9ffdd 936
a6c24e68
NC		 937 if (align == (addressT) -1)
938 return NULL;
939 }
940 else
941 {
942 if (size >= 8)
943 align = 3;
944 else if (size >= 4)
945 align = 2;
946 else if (size >= 2)
947 align = 1;
948 else
949 align = 0;
950 }
951
952 bss_alloc (symbolP, size, align);
953 return symbolP;
954}
955
704209c0 956static void
a6c24e68
NC		 957pe_lcomm (int needs_align)
958{
959 s_comm_internal (needs_align * 2, pe_lcomm_internal);
960}
704209c0 961#endif
a6c24e68 962
29b0f896
AM		 963const pseudo_typeS md_pseudo_table[] =
964{
965#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
966 {"align", s_align_bytes, 0},
967#else
968 {"align", s_align_ptwo, 0},
969#endif
970 {"arch", set_cpu_arch, 0},
971#ifndef I386COFF
972 {"bss", s_bss, 0},
a6c24e68
NC		 973#else
974 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 975#endif
976 {"ffloat", float_cons, 'f'},
977 {"dfloat", float_cons, 'd'},
978 {"tfloat", float_cons, 'x'},
979 {"value", cons, 2},
d182319b 980 {"slong", signed_cons, 4},
29b0f896
AM		 981 {"noopt", s_ignore, 0},
982 {"optim", s_ignore, 0},
983 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
984 {"code16", set_code_flag, CODE_16BIT},
985 {"code32", set_code_flag, CODE_32BIT},
986 {"code64", set_code_flag, CODE_64BIT},
987 {"intel_syntax", set_intel_syntax, 1},
988 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 989 {"intel_mnemonic", set_intel_mnemonic, 1},
990 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 991 {"allow_index_reg", set_allow_index_reg, 1},
992 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 993 {"sse_check", set_check, 0},
994 {"operand_check", set_check, 1},
3b22753a
L		 995#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
996 {"largecomm", handle_large_common, 0},
07a53e5c 997#else
e3bb37b5 998 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 999 {"loc", dwarf2_directive_loc, 0},
1000 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1001#endif
6482c264
NC		 1002#ifdef TE_PE
1003 {"secrel32", pe_directive_secrel, 0},
1004#endif
29b0f896
AM		 1005 {0, 0, 0}
1006};
1007
1008/* For interface with expression (). */
1009extern char *input_line_pointer;
1010
1011/* Hash table for instruction mnemonic lookup. */
1012static struct hash_control *op_hash;
1013
1014/* Hash table for register lookup. */
1015static struct hash_control *reg_hash;
1016\f
252b5132 1017void
e3bb37b5 1018i386_align_code (fragS *fragP, int count)
252b5132 1019{
ce8a8b2f
AM		 1020 /* Various efficient no-op patterns for aligning code labels.
1021 Note: Don't try to assemble the instructions in the comments.
1022 0L and 0w are not legal. */
252b5132
RH		 1023 static const char f32_1[] =
1024 {0x90}; /* nop */
1025 static const char f32_2[] =
ccc9c027 1026 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 1027 static const char f32_3[] =
1028 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1029 static const char f32_4[] =
1030 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1031 static const char f32_5[] =
1032 {0x90, /* nop */
1033 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1034 static const char f32_6[] =
1035 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1036 static const char f32_7[] =
1037 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1038 static const char f32_8[] =
1039 {0x90, /* nop */
1040 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1041 static const char f32_9[] =
1042 {0x89,0xf6, /* movl %esi,%esi */
1043 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1044 static const char f32_10[] =
1045 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1046 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1047 static const char f32_11[] =
1048 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1049 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1050 static const char f32_12[] =
1051 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1052 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1053 static const char f32_13[] =
1054 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1055 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1056 static const char f32_14[] =
1057 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1058 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 1059 static const char f16_3[] =
1060 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 1061 static const char f16_4[] =
1062 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1063 static const char f16_5[] =
1064 {0x90, /* nop */
1065 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1066 static const char f16_6[] =
1067 {0x89,0xf6, /* mov %si,%si */
1068 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1069 static const char f16_7[] =
1070 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1071 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1072 static const char f16_8[] =
1073 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1074 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 1075 static const char jump_31[] =
1076 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1077 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1078 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1079 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 1080 static const char *const f32_patt[] = {
1081 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1082 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 1083 };
1084 static const char *const f16_patt[] = {
76bc74dc 1085 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1086 };
ccc9c027
L		 1087 /* nopl (%[re]ax) */
1088 static const char alt_3[] =
1089 {0x0f,0x1f,0x00};
1090 /* nopl 0(%[re]ax) */
1091 static const char alt_4[] =
1092 {0x0f,0x1f,0x40,0x00};
1093 /* nopl 0(%[re]ax,%[re]ax,1) */
1094 static const char alt_5[] =
1095 {0x0f,0x1f,0x44,0x00,0x00};
1096 /* nopw 0(%[re]ax,%[re]ax,1) */
1097 static const char alt_6[] =
1098 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1099 /* nopl 0L(%[re]ax) */
1100 static const char alt_7[] =
1101 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1102 /* nopl 0L(%[re]ax,%[re]ax,1) */
1103 static const char alt_8[] =
1104 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1105 /* nopw 0L(%[re]ax,%[re]ax,1) */
1106 static const char alt_9[] =
1107 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1108 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1109 static const char alt_10[] =
1110 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1111 /* data16
1112 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1113 static const char alt_long_11[] =
1114 {0x66,
1115 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1116 /* data16
1117 data16
1118 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1119 static const char alt_long_12[] =
1120 {0x66,
1121 0x66,
1122 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1123 /* data16
1124 data16
1125 data16
1126 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1127 static const char alt_long_13[] =
1128 {0x66,
1129 0x66,
1130 0x66,
1131 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1132 /* data16
1133 data16
1134 data16
1135 data16
1136 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1137 static const char alt_long_14[] =
1138 {0x66,
1139 0x66,
1140 0x66,
1141 0x66,
1142 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1143 /* data16
1144 data16
1145 data16
1146 data16
1147 data16
1148 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1149 static const char alt_long_15[] =
1150 {0x66,
1151 0x66,
1152 0x66,
1153 0x66,
1154 0x66,
1155 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1156 /* nopl 0(%[re]ax,%[re]ax,1)
1157 nopw 0(%[re]ax,%[re]ax,1) */
1158 static const char alt_short_11[] =
1159 {0x0f,0x1f,0x44,0x00,0x00,
1160 0x66,0x0f,0x1f,0x44,0x00,0x00};
1161 /* nopw 0(%[re]ax,%[re]ax,1)
1162 nopw 0(%[re]ax,%[re]ax,1) */
1163 static const char alt_short_12[] =
1164 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1165 0x66,0x0f,0x1f,0x44,0x00,0x00};
1166 /* nopw 0(%[re]ax,%[re]ax,1)
1167 nopl 0L(%[re]ax) */
1168 static const char alt_short_13[] =
1169 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1170 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1171 /* nopl 0L(%[re]ax)
1172 nopl 0L(%[re]ax) */
1173 static const char alt_short_14[] =
1174 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1175 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1176 /* nopl 0L(%[re]ax)
1177 nopl 0L(%[re]ax,%[re]ax,1) */
1178 static const char alt_short_15[] =
1179 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1180 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1181 static const char *const alt_short_patt[] = {
1182 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1183 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
1184 alt_short_14, alt_short_15
1185 };
1186 static const char *const alt_long_patt[] = {
1187 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1188 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1189 alt_long_14, alt_long_15
1190 };
252b5132 1191
76bc74dc
L		 1192 /* Only align for at least a positive non-zero boundary. */
1193 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1194 return;
3e73aa7c 1195
ccc9c027
L		 1196 /* We need to decide which NOP sequence to use for 32bit and
1197 64bit. When -mtune= is used:
4eed87de 1198
76bc74dc
L		 1199 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1200 PROCESSOR_GENERIC32, f32_patt will be used.
1201 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 1202 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1203 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 1204 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
7b458c12 1205 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
69dd9865 1206 will be used.
ccc9c027 1207
76bc74dc 1208 When -mtune= isn't used, alt_long_patt will be used if
22109423 1209 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1210 be used.
ccc9c027
L		 1211
1212 When -march= or .arch is used, we can't use anything beyond
1213 cpu_arch_isa_flags. */
1214
1215 if (flag_code == CODE_16BIT)
1216 {
ccc9c027 1217 if (count > 8)
33fef721 1218 {
76bc74dc
L		 1219 memcpy (fragP->fr_literal + fragP->fr_fix,
1220 jump_31, count);
1221 /* Adjust jump offset. */
1222 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1223 }
76bc74dc
L		 1224 else
1225 memcpy (fragP->fr_literal + fragP->fr_fix,
1226 f16_patt[count - 1], count);
252b5132 1227 }
33fef721 1228 else
ccc9c027
L		 1229 {
1230 const char *const *patt = NULL;
1231
fbf3f584 1232 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1233 {
1234 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1235 switch (cpu_arch_tune)
1236 {
1237 case PROCESSOR_UNKNOWN:
1238 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1239 optimize with nops. */
1240 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1241 patt = alt_long_patt;
ccc9c027
L		 1242 else
1243 patt = f32_patt;
1244 break;
ccc9c027
L		 1245 case PROCESSOR_PENTIUM4:
1246 case PROCESSOR_NOCONA:
ef05d495 1247 case PROCESSOR_CORE:
76bc74dc 1248 case PROCESSOR_CORE2:
bd5295b2 1249 case PROCESSOR_COREI7:
3632d14b 1250 case PROCESSOR_L1OM:
7a9068fe 1251 case PROCESSOR_K1OM:
76bc74dc
L		 1252 case PROCESSOR_GENERIC64:
1253 patt = alt_long_patt;
1254 break;
ccc9c027
L		 1255 case PROCESSOR_K6:
1256 case PROCESSOR_ATHLON:
1257 case PROCESSOR_K8:
4eed87de 1258 case PROCESSOR_AMDFAM10:
8aedb9fe 1259 case PROCESSOR_BD:
7b458c12 1260 case PROCESSOR_BT:
ccc9c027
L		 1261 patt = alt_short_patt;
1262 break;
76bc74dc 1263 case PROCESSOR_I386:
ccc9c027
L		 1264 case PROCESSOR_I486:
1265 case PROCESSOR_PENTIUM:
2dde1948 1266 case PROCESSOR_PENTIUMPRO:
ccc9c027
L		 1267 case PROCESSOR_GENERIC32:
1268 patt = f32_patt;
1269 break;
4eed87de 1270 }
ccc9c027
L		 1271 }
1272 else
1273 {
fbf3f584 1274 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1275 {
1276 case PROCESSOR_UNKNOWN:
e6a14101 1277 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1278 PROCESSOR_UNKNOWN. */
1279 abort ();
1280 break;
1281
76bc74dc 1282 case PROCESSOR_I386:
ccc9c027
L		 1283 case PROCESSOR_I486:
1284 case PROCESSOR_PENTIUM:
ccc9c027
L		 1285 case PROCESSOR_K6:
1286 case PROCESSOR_ATHLON:
1287 case PROCESSOR_K8:
4eed87de 1288 case PROCESSOR_AMDFAM10:
8aedb9fe 1289 case PROCESSOR_BD:
7b458c12 1290 case PROCESSOR_BT:
ccc9c027
L		 1291 case PROCESSOR_GENERIC32:
1292 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1293 with nops. */
1294 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1295 patt = alt_short_patt;
1296 else
1297 patt = f32_patt;
1298 break;
76bc74dc
L		 1299 case PROCESSOR_PENTIUMPRO:
1300 case PROCESSOR_PENTIUM4:
1301 case PROCESSOR_NOCONA:
1302 case PROCESSOR_CORE:
ef05d495 1303 case PROCESSOR_CORE2:
bd5295b2 1304 case PROCESSOR_COREI7:
3632d14b 1305 case PROCESSOR_L1OM:
7a9068fe 1306 case PROCESSOR_K1OM:
22109423 1307 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1308 patt = alt_long_patt;
1309 else
1310 patt = f32_patt;
1311 break;
1312 case PROCESSOR_GENERIC64:
76bc74dc 1313 patt = alt_long_patt;
ccc9c027 1314 break;
4eed87de 1315 }
ccc9c027
L		 1316 }
1317
76bc74dc
L		 1318 if (patt == f32_patt)
1319 {
1320 /* If the padding is less than 15 bytes, we use the normal
1321 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1322 its offset. */
1323 int limit;
76ba9986 1324
711eedef
L		 1325 /* For 64bit, the limit is 3 bytes. */
1326 if (flag_code == CODE_64BIT
1327 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1328 limit = 3;
1329 else
1330 limit = 15;
1331 if (count < limit)
76bc74dc
L		 1332 memcpy (fragP->fr_literal + fragP->fr_fix,
1333 patt[count - 1], count);
1334 else
1335 {
1336 memcpy (fragP->fr_literal + fragP->fr_fix,
1337 jump_31, count);
1338 /* Adjust jump offset. */
1339 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1340 }
1341 }
1342 else
1343 {
1344 /* Maximum length of an instruction is 15 byte. If the
1345 padding is greater than 15 bytes and we don't use jump,
1346 we have to break it into smaller pieces. */
1347 int padding = count;
1348 while (padding > 15)
1349 {
1350 padding -= 15;
1351 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1352 patt [14], 15);
1353 }
1354
1355 if (padding)
1356 memcpy (fragP->fr_literal + fragP->fr_fix,
1357 patt [padding - 1], padding);
1358 }
ccc9c027 1359 }
33fef721 1360 fragP->fr_var = count;
252b5132
RH		 1361}
1362
c6fb90c8 1363static INLINE int
0dfbf9d7 1364operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1365{
0dfbf9d7 1366 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1367 {
1368 case 3:
0dfbf9d7 1369 if (x->array[2])
c6fb90c8
L		 1370 return 0;
1371 case 2:
0dfbf9d7 1372 if (x->array[1])
c6fb90c8
L		 1373 return 0;
1374 case 1:
0dfbf9d7 1375 return !x->array[0];
c6fb90c8
L		 1376 default:
1377 abort ();
1378 }
40fb9820
L		 1379}
1380
c6fb90c8 1381static INLINE void
0dfbf9d7 1382operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1383{
0dfbf9d7 1384 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1385 {
1386 case 3:
0dfbf9d7 1387 x->array[2] = v;
c6fb90c8 1388 case 2:
0dfbf9d7 1389 x->array[1] = v;
c6fb90c8 1390 case 1:
0dfbf9d7 1391 x->array[0] = v;
c6fb90c8
L		 1392 break;
1393 default:
1394 abort ();
1395 }
1396}
40fb9820 1397
c6fb90c8 1398static INLINE int
0dfbf9d7
L		 1399operand_type_equal (const union i386_operand_type *x,
1400 const union i386_operand_type *y)
c6fb90c8 1401{
0dfbf9d7 1402 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1403 {
1404 case 3:
0dfbf9d7 1405 if (x->array[2] != y->array[2])
c6fb90c8
L		 1406 return 0;
1407 case 2:
0dfbf9d7 1408 if (x->array[1] != y->array[1])
c6fb90c8
L		 1409 return 0;
1410 case 1:
0dfbf9d7 1411 return x->array[0] == y->array[0];
c6fb90c8
L		 1412 break;
1413 default:
1414 abort ();
1415 }
1416}
40fb9820 1417
0dfbf9d7
L		 1418static INLINE int
1419cpu_flags_all_zero (const union i386_cpu_flags *x)
1420{
1421 switch (ARRAY_SIZE(x->array))
1422 {
1423 case 3:
1424 if (x->array[2])
1425 return 0;
1426 case 2:
1427 if (x->array[1])
1428 return 0;
1429 case 1:
1430 return !x->array[0];
1431 default:
1432 abort ();
1433 }
1434}
1435
1436static INLINE void
1437cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1438{
1439 switch (ARRAY_SIZE(x->array))
1440 {
1441 case 3:
1442 x->array[2] = v;
1443 case 2:
1444 x->array[1] = v;
1445 case 1:
1446 x->array[0] = v;
1447 break;
1448 default:
1449 abort ();
1450 }
1451}
1452
1453static INLINE int
1454cpu_flags_equal (const union i386_cpu_flags *x,
1455 const union i386_cpu_flags *y)
1456{
1457 switch (ARRAY_SIZE(x->array))
1458 {
1459 case 3:
1460 if (x->array[2] != y->array[2])
1461 return 0;
1462 case 2:
1463 if (x->array[1] != y->array[1])
1464 return 0;
1465 case 1:
1466 return x->array[0] == y->array[0];
1467 break;
1468 default:
1469 abort ();
1470 }
1471}
c6fb90c8
L		 1472
1473static INLINE int
1474cpu_flags_check_cpu64 (i386_cpu_flags f)
1475{
1476 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1477 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1478}
1479
c6fb90c8
L		 1480static INLINE i386_cpu_flags
1481cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1482{
c6fb90c8
L		 1483 switch (ARRAY_SIZE (x.array))
1484 {
1485 case 3:
1486 x.array [2] &= y.array [2];
1487 case 2:
1488 x.array [1] &= y.array [1];
1489 case 1:
1490 x.array [0] &= y.array [0];
1491 break;
1492 default:
1493 abort ();
1494 }
1495 return x;
1496}
40fb9820 1497
c6fb90c8
L		 1498static INLINE i386_cpu_flags
1499cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1500{
c6fb90c8 1501 switch (ARRAY_SIZE (x.array))
40fb9820 1502 {
c6fb90c8
L		 1503 case 3:
1504 x.array [2] |= y.array [2];
1505 case 2:
1506 x.array [1] |= y.array [1];
1507 case 1:
1508 x.array [0] |= y.array [0];
40fb9820
L		 1509 break;
1510 default:
1511 abort ();
1512 }
40fb9820
L		 1513 return x;
1514}
1515
309d3373
JB		 1516static INLINE i386_cpu_flags
1517cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1518{
1519 switch (ARRAY_SIZE (x.array))
1520 {
1521 case 3:
1522 x.array [2] &= ~y.array [2];
1523 case 2:
1524 x.array [1] &= ~y.array [1];
1525 case 1:
1526 x.array [0] &= ~y.array [0];
1527 break;
1528 default:
1529 abort ();
1530 }
1531 return x;
1532}
1533
c0f3af97
L		 1534#define CPU_FLAGS_ARCH_MATCH 0x1
1535#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1536#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1537#define CPU_FLAGS_PCLMUL_MATCH 0x8
1538#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1539
a5ff0eb2 1540#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1541 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1542 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1543#define CPU_FLAGS_PERFECT_MATCH \
1544 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1545
1546/* Return CPU flags match bits. */
3629bb00 1547
40fb9820 1548static int
d3ce72d0 1549cpu_flags_match (const insn_template *t)
40fb9820 1550{
c0f3af97
L		 1551 i386_cpu_flags x = t->cpu_flags;
1552 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1553
1554 x.bitfield.cpu64 = 0;
1555 x.bitfield.cpuno64 = 0;
1556
0dfbf9d7 1557 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1558 {
1559 /* This instruction is available on all archs. */
1560 match |= CPU_FLAGS_32BIT_MATCH;
1561 }
3629bb00
L		 1562 else
1563 {
c0f3af97 1564 /* This instruction is available only on some archs. */
3629bb00
L		 1565 i386_cpu_flags cpu = cpu_arch_flags;
1566
1567 cpu.bitfield.cpu64 = 0;
1568 cpu.bitfield.cpuno64 = 0;
1569 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1570 if (!cpu_flags_all_zero (&cpu))
1571 {
a5ff0eb2
L		 1572 if (x.bitfield.cpuavx)
1573 {
ce2f5b3c 1574 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1575 if (cpu.bitfield.cpuavx)
1576 {
1577 /* Check SSE2AVX. */
1578 if (!t->opcode_modifier.sse2avx|| sse2avx)
1579 {
1580 match |= (CPU_FLAGS_ARCH_MATCH
1581 | CPU_FLAGS_AVX_MATCH);
1582 /* Check AES. */
1583 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1584 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1585 /* Check PCLMUL. */
1586 if (!x.bitfield.cpupclmul
1587 || cpu.bitfield.cpupclmul)
1588 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1589 }
1590 }
1591 else
1592 match |= CPU_FLAGS_ARCH_MATCH;
1593 }
1594 else
c0f3af97
L		 1595 match |= CPU_FLAGS_32BIT_MATCH;
1596 }
3629bb00 1597 }
c0f3af97 1598 return match;
40fb9820
L		 1599}
1600
c6fb90c8
L		 1601static INLINE i386_operand_type
1602operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1603{
c6fb90c8
L		 1604 switch (ARRAY_SIZE (x.array))
1605 {
1606 case 3:
1607 x.array [2] &= y.array [2];
1608 case 2:
1609 x.array [1] &= y.array [1];
1610 case 1:
1611 x.array [0] &= y.array [0];
1612 break;
1613 default:
1614 abort ();
1615 }
1616 return x;
40fb9820
L		 1617}
1618
c6fb90c8
L		 1619static INLINE i386_operand_type
1620operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1621{
c6fb90c8 1622 switch (ARRAY_SIZE (x.array))
40fb9820 1623 {
c6fb90c8
L		 1624 case 3:
1625 x.array [2] |= y.array [2];
1626 case 2:
1627 x.array [1] |= y.array [1];
1628 case 1:
1629 x.array [0] |= y.array [0];
40fb9820
L		 1630 break;
1631 default:
1632 abort ();
1633 }
c6fb90c8
L		 1634 return x;
1635}
40fb9820 1636
c6fb90c8
L		 1637static INLINE i386_operand_type
1638operand_type_xor (i386_operand_type x, i386_operand_type y)
1639{
1640 switch (ARRAY_SIZE (x.array))
1641 {
1642 case 3:
1643 x.array [2] ^= y.array [2];
1644 case 2:
1645 x.array [1] ^= y.array [1];
1646 case 1:
1647 x.array [0] ^= y.array [0];
1648 break;
1649 default:
1650 abort ();
1651 }
40fb9820
L		 1652 return x;
1653}
1654
1655static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1656static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1657static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1658static const i386_operand_type inoutportreg
1659 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1660static const i386_operand_type reg16_inoutportreg
1661 = OPERAND_TYPE_REG16_INOUTPORTREG;
1662static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1663static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1664static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1665static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1666static const i386_operand_type anydisp
1667 = OPERAND_TYPE_ANYDISP;
40fb9820 1668static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1669static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1670static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1671static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1672static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1673static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1674static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1675static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1676static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1677static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1678static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1679static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1680static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1681static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1682
1683enum operand_type
1684{
1685 reg,
40fb9820
L		 1686 imm,
1687 disp,
1688 anymem
1689};
1690
c6fb90c8 1691static INLINE int
40fb9820
L		 1692operand_type_check (i386_operand_type t, enum operand_type c)
1693{
1694 switch (c)
1695 {
1696 case reg:
1697 return (t.bitfield.reg8
1698 || t.bitfield.reg16
1699 || t.bitfield.reg32
1700 || t.bitfield.reg64);
1701
40fb9820
L		 1702 case imm:
1703 return (t.bitfield.imm8
1704 || t.bitfield.imm8s
1705 || t.bitfield.imm16
1706 || t.bitfield.imm32
1707 || t.bitfield.imm32s
1708 || t.bitfield.imm64);
1709
1710 case disp:
1711 return (t.bitfield.disp8
1712 || t.bitfield.disp16
1713 || t.bitfield.disp32
1714 || t.bitfield.disp32s
1715 || t.bitfield.disp64);
1716
1717 case anymem:
1718 return (t.bitfield.disp8
1719 || t.bitfield.disp16
1720 || t.bitfield.disp32
1721 || t.bitfield.disp32s
1722 || t.bitfield.disp64
1723 || t.bitfield.baseindex);
1724
1725 default:
1726 abort ();
1727 }
2cfe26b6
AM		 1728
1729 return 0;
40fb9820
L		 1730}
1731
5c07affc
L		 1732/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1733 operand J for instruction template T. */
1734
1735static INLINE int
d3ce72d0 1736match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1737{
1738 return !((i.types[j].bitfield.byte
1739 && !t->operand_types[j].bitfield.byte)
1740 || (i.types[j].bitfield.word
1741 && !t->operand_types[j].bitfield.word)
1742 || (i.types[j].bitfield.dword
1743 && !t->operand_types[j].bitfield.dword)
1744 || (i.types[j].bitfield.qword
1745 && !t->operand_types[j].bitfield.qword));
1746}
1747
1748/* Return 1 if there is no conflict in any size on operand J for
1749 instruction template T. */
1750
1751static INLINE int
d3ce72d0 1752match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1753{
1754 return (match_reg_size (t, j)
1755 && !((i.types[j].bitfield.unspecified
1756 && !t->operand_types[j].bitfield.unspecified)
1757 || (i.types[j].bitfield.fword
1758 && !t->operand_types[j].bitfield.fword)
1759 || (i.types[j].bitfield.tbyte
1760 && !t->operand_types[j].bitfield.tbyte)
1761 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1762 && !t->operand_types[j].bitfield.xmmword)
1763 || (i.types[j].bitfield.ymmword
43234a1e
L		 1764 && !t->operand_types[j].bitfield.ymmword)
1765 || (i.types[j].bitfield.zmmword
1766 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1767}
1768
1769/* Return 1 if there is no size conflict on any operands for
1770 instruction template T. */
1771
1772static INLINE int
d3ce72d0 1773operand_size_match (const insn_template *t)
5c07affc
L		 1774{
1775 unsigned int j;
1776 int match = 1;
1777
1778 /* Don't check jump instructions. */
1779 if (t->opcode_modifier.jump
1780 || t->opcode_modifier.jumpbyte
1781 || t->opcode_modifier.jumpdword
1782 || t->opcode_modifier.jumpintersegment)
1783 return match;
1784
1785 /* Check memory and accumulator operand size. */
1786 for (j = 0; j < i.operands; j++)
1787 {
1788 if (t->operand_types[j].bitfield.anysize)
1789 continue;
1790
1791 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1792 {
1793 match = 0;
1794 break;
1795 }
1796
1797 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1798 {
1799 match = 0;
1800 break;
1801 }
1802 }
1803
891edac4 1804 if (match)
5c07affc 1805 return match;
891edac4
L		 1806 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1807 {
1808mismatch:
86e026a4 1809 i.error = operand_size_mismatch;
891edac4
L		 1810 return 0;
1811 }
5c07affc
L		 1812
1813 /* Check reverse. */
9c2799c2 1814 gas_assert (i.operands == 2);
5c07affc
L		 1815
1816 match = 1;
1817 for (j = 0; j < 2; j++)
1818 {
1819 if (t->operand_types[j].bitfield.acc
1820 && !match_reg_size (t, j ? 0 : 1))
891edac4 1821 goto mismatch;
5c07affc
L		 1822
1823 if (i.types[j].bitfield.mem
1824 && !match_mem_size (t, j ? 0 : 1))
891edac4 1825 goto mismatch;
5c07affc
L		 1826 }
1827
1828 return match;
1829}
1830
c6fb90c8 1831static INLINE int
40fb9820
L		 1832operand_type_match (i386_operand_type overlap,
1833 i386_operand_type given)
1834{
1835 i386_operand_type temp = overlap;
1836
1837 temp.bitfield.jumpabsolute = 0;
7d5e4556 1838 temp.bitfield.unspecified = 0;
5c07affc
L		 1839 temp.bitfield.byte = 0;
1840 temp.bitfield.word = 0;
1841 temp.bitfield.dword = 0;
1842 temp.bitfield.fword = 0;
1843 temp.bitfield.qword = 0;
1844 temp.bitfield.tbyte = 0;
1845 temp.bitfield.xmmword = 0;
c0f3af97 1846 temp.bitfield.ymmword = 0;
43234a1e 1847 temp.bitfield.zmmword = 0;
0dfbf9d7 1848 if (operand_type_all_zero (&temp))
891edac4 1849 goto mismatch;
40fb9820 1850
891edac4
L		 1851 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1852 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1853 return 1;
1854
1855mismatch:
a65babc9 1856 i.error = operand_type_mismatch;
891edac4 1857 return 0;
40fb9820
L		 1858}
1859
7d5e4556 1860/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1861 unless the expected operand type register overlap is null.
1862 Note that Acc in a template matches every size of reg. */
1863
c6fb90c8 1864static INLINE int
40fb9820
L		 1865operand_type_register_match (i386_operand_type m0,
1866 i386_operand_type g0,
1867 i386_operand_type t0,
1868 i386_operand_type m1,
1869 i386_operand_type g1,
1870 i386_operand_type t1)
1871{
1872 if (!operand_type_check (g0, reg))
1873 return 1;
1874
1875 if (!operand_type_check (g1, reg))
1876 return 1;
1877
1878 if (g0.bitfield.reg8 == g1.bitfield.reg8
1879 && g0.bitfield.reg16 == g1.bitfield.reg16
1880 && g0.bitfield.reg32 == g1.bitfield.reg32
1881 && g0.bitfield.reg64 == g1.bitfield.reg64)
1882 return 1;
1883
1884 if (m0.bitfield.acc)
1885 {
1886 t0.bitfield.reg8 = 1;
1887 t0.bitfield.reg16 = 1;
1888 t0.bitfield.reg32 = 1;
1889 t0.bitfield.reg64 = 1;
1890 }
1891
1892 if (m1.bitfield.acc)
1893 {
1894 t1.bitfield.reg8 = 1;
1895 t1.bitfield.reg16 = 1;
1896 t1.bitfield.reg32 = 1;
1897 t1.bitfield.reg64 = 1;
1898 }
1899
891edac4
L		 1900 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1901 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1902 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1903 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1904 return 1;
1905
a65babc9 1906 i.error = register_type_mismatch;
891edac4
L		 1907
1908 return 0;
40fb9820
L		 1909}
1910
4c692bc7
JB		 1911static INLINE unsigned int
1912register_number (const reg_entry *r)
1913{
1914 unsigned int nr = r->reg_num;
1915
1916 if (r->reg_flags & RegRex)
1917 nr += 8;
1918
1919 return nr;
1920}
1921
252b5132 1922static INLINE unsigned int
40fb9820 1923mode_from_disp_size (i386_operand_type t)
252b5132 1924{
43234a1e 1925 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1926 return 1;
1927 else if (t.bitfield.disp16
1928 || t.bitfield.disp32
1929 || t.bitfield.disp32s)
1930 return 2;
1931 else
1932 return 0;
252b5132
RH		 1933}
1934
1935static INLINE int
e3bb37b5 1936fits_in_signed_byte (offsetT num)
252b5132
RH		 1937{
1938 return (num >= -128) && (num <= 127);
47926f60 1939}
252b5132
RH		 1940
1941static INLINE int
e3bb37b5 1942fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1943{
1944 return (num & 0xff) == num;
47926f60 1945}
252b5132
RH		 1946
1947static INLINE int
e3bb37b5 1948fits_in_unsigned_word (offsetT num)
252b5132
RH		 1949{
1950 return (num & 0xffff) == num;
47926f60 1951}
252b5132
RH		 1952
1953static INLINE int
e3bb37b5 1954fits_in_signed_word (offsetT num)
252b5132
RH		 1955{
1956 return (-32768 <= num) && (num <= 32767);
47926f60 1957}
2a962e6d 1958
3e73aa7c 1959static INLINE int
e3bb37b5 1960fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1961{
1962#ifndef BFD64
1963 return 1;
1964#else
1965 return (!(((offsetT) -1 << 31) & num)
1966 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1967#endif
1968} /* fits_in_signed_long() */
2a962e6d 1969
3e73aa7c 1970static INLINE int
e3bb37b5 1971fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1972{
1973#ifndef BFD64
1974 return 1;
1975#else
1976 return (num & (((offsetT) 2 << 31) - 1)) == num;
1977#endif
1978} /* fits_in_unsigned_long() */
252b5132 1979
43234a1e
L		 1980static INLINE int
1981fits_in_vec_disp8 (offsetT num)
1982{
1983 int shift = i.memshift;
1984 unsigned int mask;
1985
1986 if (shift == -1)
1987 abort ();
1988
1989 mask = (1 << shift) - 1;
1990
1991 /* Return 0 if NUM isn't properly aligned. */
1992 if ((num & mask))
1993 return 0;
1994
1995 /* Check if NUM will fit in 8bit after shift. */
1996 return fits_in_signed_byte (num >> shift);
1997}
1998
a683cc34
SP		 1999static INLINE int
2000fits_in_imm4 (offsetT num)
2001{
2002 return (num & 0xf) == num;
2003}
2004
40fb9820 2005static i386_operand_type
e3bb37b5 2006smallest_imm_type (offsetT num)
252b5132 2007{
40fb9820 2008 i386_operand_type t;
7ab9ffdd 2009
0dfbf9d7 2010 operand_type_set (&t, 0);
40fb9820
L		 2011 t.bitfield.imm64 = 1;
2012
2013 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2014 {
2015 /* This code is disabled on the 486 because all the Imm1 forms
2016 in the opcode table are slower on the i486. They're the
2017 versions with the implicitly specified single-position
2018 displacement, which has another syntax if you really want to
2019 use that form. */
40fb9820
L		 2020 t.bitfield.imm1 = 1;
2021 t.bitfield.imm8 = 1;
2022 t.bitfield.imm8s = 1;
2023 t.bitfield.imm16 = 1;
2024 t.bitfield.imm32 = 1;
2025 t.bitfield.imm32s = 1;
2026 }
2027 else if (fits_in_signed_byte (num))
2028 {
2029 t.bitfield.imm8 = 1;
2030 t.bitfield.imm8s = 1;
2031 t.bitfield.imm16 = 1;
2032 t.bitfield.imm32 = 1;
2033 t.bitfield.imm32s = 1;
2034 }
2035 else if (fits_in_unsigned_byte (num))
2036 {
2037 t.bitfield.imm8 = 1;
2038 t.bitfield.imm16 = 1;
2039 t.bitfield.imm32 = 1;
2040 t.bitfield.imm32s = 1;
2041 }
2042 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2043 {
2044 t.bitfield.imm16 = 1;
2045 t.bitfield.imm32 = 1;
2046 t.bitfield.imm32s = 1;
2047 }
2048 else if (fits_in_signed_long (num))
2049 {
2050 t.bitfield.imm32 = 1;
2051 t.bitfield.imm32s = 1;
2052 }
2053 else if (fits_in_unsigned_long (num))
2054 t.bitfield.imm32 = 1;
2055
2056 return t;
47926f60 2057}
252b5132 2058
847f7ad4 2059static offsetT
e3bb37b5 2060offset_in_range (offsetT val, int size)
847f7ad4 2061{
508866be 2062 addressT mask;
ba2adb93 2063
847f7ad4
AM		 2064 switch (size)
2065 {
508866be
L		 2066 case 1: mask = ((addressT) 1 << 8) - 1; break;
2067 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2068 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2069#ifdef BFD64
2070 case 8: mask = ((addressT) 2 << 63) - 1; break;
2071#endif
47926f60 2072 default: abort ();
847f7ad4
AM		 2073 }
2074
9de868bf
L		 2075#ifdef BFD64
2076 /* If BFD64, sign extend val for 32bit address mode. */
2077 if (flag_code != CODE_64BIT
2078 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2079 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2080 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2081#endif
ba2adb93 2082
47926f60 2083 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2084 {
2085 char buf1[40], buf2[40];
2086
2087 sprint_value (buf1, val);
2088 sprint_value (buf2, val & mask);
2089 as_warn (_("%s shortened to %s"), buf1, buf2);
2090 }
2091 return val & mask;
2092}
2093
c32fa91d
L		 2094enum PREFIX_GROUP
2095{
2096 PREFIX_EXIST = 0,
2097 PREFIX_LOCK,
2098 PREFIX_REP,
2099 PREFIX_OTHER
2100};
2101
2102/* Returns
2103 a. PREFIX_EXIST if attempting to add a prefix where one from the
2104 same class already exists.
2105 b. PREFIX_LOCK if lock prefix is added.
2106 c. PREFIX_REP if rep/repne prefix is added.
2107 d. PREFIX_OTHER if other prefix is added.
2108 */
2109
2110static enum PREFIX_GROUP
e3bb37b5 2111add_prefix (unsigned int prefix)
252b5132 2112{
c32fa91d 2113 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2114 unsigned int q;
252b5132 2115
29b0f896
AM		 2116 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2117 && flag_code == CODE_64BIT)
b1905489 2118 {
161a04f6
L		 2119 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2120 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2121 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2122 ret = PREFIX_EXIST;
b1905489
JB		 2123 q = REX_PREFIX;
2124 }
3e73aa7c 2125 else
b1905489
JB		 2126 {
2127 switch (prefix)
2128 {
2129 default:
2130 abort ();
2131
2132 case CS_PREFIX_OPCODE:
2133 case DS_PREFIX_OPCODE:
2134 case ES_PREFIX_OPCODE:
2135 case FS_PREFIX_OPCODE:
2136 case GS_PREFIX_OPCODE:
2137 case SS_PREFIX_OPCODE:
2138 q = SEG_PREFIX;
2139 break;
2140
2141 case REPNE_PREFIX_OPCODE:
2142 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2143 q = REP_PREFIX;
2144 ret = PREFIX_REP;
2145 break;
2146
b1905489 2147 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2148 q = LOCK_PREFIX;
2149 ret = PREFIX_LOCK;
b1905489
JB		 2150 break;
2151
2152 case FWAIT_OPCODE:
2153 q = WAIT_PREFIX;
2154 break;
2155
2156 case ADDR_PREFIX_OPCODE:
2157 q = ADDR_PREFIX;
2158 break;
2159
2160 case DATA_PREFIX_OPCODE:
2161 q = DATA_PREFIX;
2162 break;
2163 }
2164 if (i.prefix[q] != 0)
c32fa91d 2165 ret = PREFIX_EXIST;
b1905489 2166 }
252b5132 2167
b1905489 2168 if (ret)
252b5132 2169 {
b1905489
JB		 2170 if (!i.prefix[q])
2171 ++i.prefixes;
2172 i.prefix[q] |= prefix;
252b5132 2173 }
b1905489
JB		 2174 else
2175 as_bad (_("same type of prefix used twice"));
252b5132 2176
252b5132
RH		 2177 return ret;
2178}
2179
2180static void
78f12dd3 2181update_code_flag (int value, int check)
eecb386c 2182{
78f12dd3
L		 2183 PRINTF_LIKE ((*as_error));
2184
1e9cc1c2 2185 flag_code = (enum flag_code) value;
40fb9820
L		 2186 if (flag_code == CODE_64BIT)
2187 {
2188 cpu_arch_flags.bitfield.cpu64 = 1;
2189 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2190 }
2191 else
2192 {
2193 cpu_arch_flags.bitfield.cpu64 = 0;
2194 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2195 }
2196 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2197 {
78f12dd3
L		 2198 if (check)
2199 as_error = as_fatal;
2200 else
2201 as_error = as_bad;
2202 (*as_error) (_("64bit mode not supported on `%s'."),
2203 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2204 }
40fb9820 2205 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2206 {
78f12dd3
L		 2207 if (check)
2208 as_error = as_fatal;
2209 else
2210 as_error = as_bad;
2211 (*as_error) (_("32bit mode not supported on `%s'."),
2212 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2213 }
eecb386c
AM		 2214 stackop_size = '\0';
2215}
2216
78f12dd3
L		 2217static void
2218set_code_flag (int value)
2219{
2220 update_code_flag (value, 0);
2221}
2222
eecb386c 2223static void
e3bb37b5 2224set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2225{
1e9cc1c2 2226 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2227 if (flag_code != CODE_16BIT)
2228 abort ();
2229 cpu_arch_flags.bitfield.cpu64 = 0;
2230 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2231 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2232}
2233
2234static void
e3bb37b5 2235set_intel_syntax (int syntax_flag)
252b5132
RH		 2236{
2237 /* Find out if register prefixing is specified. */
2238 int ask_naked_reg = 0;
2239
2240 SKIP_WHITESPACE ();
29b0f896 2241 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2242 {
2243 char *string = input_line_pointer;
2244 int e = get_symbol_end ();
2245
47926f60 2246 if (strcmp (string, "prefix") == 0)
252b5132 2247 ask_naked_reg = 1;
47926f60 2248 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2249 ask_naked_reg = -1;
2250 else
d0b47220 2251 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2252 *input_line_pointer = e;
2253 }
2254 demand_empty_rest_of_line ();
c3332e24 2255
252b5132
RH		 2256 intel_syntax = syntax_flag;
2257
2258 if (ask_naked_reg == 0)
f86103b7
AM		 2259 allow_naked_reg = (intel_syntax
2260 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2261 else
2262 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2263
ee86248c 2264 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2265
e4a3b5a4 2266 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2267 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2268 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2269}
2270
1efbbeb4
L		 2271static void
2272set_intel_mnemonic (int mnemonic_flag)
2273{
e1d4d893 2274 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2275}
2276
db51cc60
L		 2277static void
2278set_allow_index_reg (int flag)
2279{
2280 allow_index_reg = flag;
2281}
2282
cb19c032 2283static void
7bab8ab5 2284set_check (int what)
cb19c032 2285{
7bab8ab5
JB		 2286 enum check_kind *kind;
2287 const char *str;
2288
2289 if (what)
2290 {
2291 kind = &operand_check;
2292 str = "operand";
2293 }
2294 else
2295 {
2296 kind = &sse_check;
2297 str = "sse";
2298 }
2299
cb19c032
L		 2300 SKIP_WHITESPACE ();
2301
2302 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2303 {
2304 char *string = input_line_pointer;
2305 int e = get_symbol_end ();
2306
2307 if (strcmp (string, "none") == 0)
7bab8ab5 2308 *kind = check_none;
cb19c032 2309 else if (strcmp (string, "warning") == 0)
7bab8ab5 2310 *kind = check_warning;
cb19c032 2311 else if (strcmp (string, "error") == 0)
7bab8ab5 2312 *kind = check_error;
cb19c032 2313 else
7bab8ab5 2314 as_bad (_("bad argument to %s_check directive."), str);
cb19c032
L		 2315 *input_line_pointer = e;
2316 }
2317 else
7bab8ab5 2318 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2319
2320 demand_empty_rest_of_line ();
2321}
2322
8a9036a4
L		 2323static void
2324check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2325 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2326{
2327#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2328 static const char *arch;
2329
2330 /* Intel LIOM is only supported on ELF. */
2331 if (!IS_ELF)
2332 return;
2333
2334 if (!arch)
2335 {
2336 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2337 use default_arch. */
2338 arch = cpu_arch_name;
2339 if (!arch)
2340 arch = default_arch;
2341 }
2342
3632d14b 2343 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2344 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2345 || new_flag.bitfield.cpul1om)
8a9036a4 2346 return;
76ba9986 2347
7a9068fe
L		 2348 /* If we are targeting Intel K1OM, we must enable it. */
2349 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2350 || new_flag.bitfield.cpuk1om)
2351 return;
2352
8a9036a4
L		 2353 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2354#endif
2355}
2356
e413e4e9 2357static void
e3bb37b5 2358set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2359{
47926f60 2360 SKIP_WHITESPACE ();
e413e4e9 2361
29b0f896 2362 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2363 {
2364 char *string = input_line_pointer;
2365 int e = get_symbol_end ();
91d6fa6a 2366 unsigned int j;
40fb9820 2367 i386_cpu_flags flags;
e413e4e9 2368
91d6fa6a 2369 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2370 {
91d6fa6a 2371 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2372 {
91d6fa6a 2373 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2374
5c6af06e
JB		 2375 if (*string != '.')
2376 {
91d6fa6a 2377 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2378 cpu_sub_arch_name = NULL;
91d6fa6a 2379 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2380 if (flag_code == CODE_64BIT)
2381 {
2382 cpu_arch_flags.bitfield.cpu64 = 1;
2383 cpu_arch_flags.bitfield.cpuno64 = 0;
2384 }
2385 else
2386 {
2387 cpu_arch_flags.bitfield.cpu64 = 0;
2388 cpu_arch_flags.bitfield.cpuno64 = 1;
2389 }
91d6fa6a
NC		 2390 cpu_arch_isa = cpu_arch[j].type;
2391 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2392 if (!cpu_arch_tune_set)
2393 {
2394 cpu_arch_tune = cpu_arch_isa;
2395 cpu_arch_tune_flags = cpu_arch_isa_flags;
2396 }
5c6af06e
JB		 2397 break;
2398 }
40fb9820 2399
22109423 2400 if (!cpu_arch[j].negated)
309d3373 2401 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2402 cpu_arch[j].flags);
309d3373
JB		 2403 else
2404 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2405 cpu_arch[j].flags);
0dfbf9d7 2406 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2407 {
6305a203
L		 2408 if (cpu_sub_arch_name)
2409 {
2410 char *name = cpu_sub_arch_name;
2411 cpu_sub_arch_name = concat (name,
91d6fa6a 2412 cpu_arch[j].name,
1bf57e9f 2413 (const char *) NULL);
6305a203
L		 2414 free (name);
2415 }
2416 else
91d6fa6a 2417 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2418 cpu_arch_flags = flags;
a586129e 2419 cpu_arch_isa_flags = flags;
5c6af06e
JB		 2420 }
2421 *input_line_pointer = e;
2422 demand_empty_rest_of_line ();
2423 return;
e413e4e9
AM		 2424 }
2425 }
91d6fa6a 2426 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2427 as_bad (_("no such architecture: `%s'"), string);
2428
2429 *input_line_pointer = e;
2430 }
2431 else
2432 as_bad (_("missing cpu architecture"));
2433
fddf5b5b
AM		 2434 no_cond_jump_promotion = 0;
2435 if (*input_line_pointer == ','
29b0f896 2436 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2437 {
2438 char *string = ++input_line_pointer;
2439 int e = get_symbol_end ();
2440
2441 if (strcmp (string, "nojumps") == 0)
2442 no_cond_jump_promotion = 1;
2443 else if (strcmp (string, "jumps") == 0)
2444 ;
2445 else
2446 as_bad (_("no such architecture modifier: `%s'"), string);
2447
2448 *input_line_pointer = e;
2449 }
2450
e413e4e9
AM		 2451 demand_empty_rest_of_line ();
2452}
2453
8a9036a4
L		 2454enum bfd_architecture
2455i386_arch (void)
2456{
3632d14b 2457 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2458 {
2459 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2460 || flag_code != CODE_64BIT)
2461 as_fatal (_("Intel L1OM is 64bit ELF only"));
2462 return bfd_arch_l1om;
2463 }
7a9068fe
L		 2464 else if (cpu_arch_isa == PROCESSOR_K1OM)
2465 {
2466 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2467 || flag_code != CODE_64BIT)
2468 as_fatal (_("Intel K1OM is 64bit ELF only"));
2469 return bfd_arch_k1om;
2470 }
8a9036a4
L		 2471 else
2472 return bfd_arch_i386;
2473}
2474
b9d79e03 2475unsigned long
7016a5d5 2476i386_mach (void)
b9d79e03 2477{
351f65ca 2478 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2479 {
3632d14b 2480 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2481 {
351f65ca
L		 2482 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2483 || default_arch[6] != '\0')
8a9036a4
L		 2484 as_fatal (_("Intel L1OM is 64bit ELF only"));
2485 return bfd_mach_l1om;
2486 }
7a9068fe
L		 2487 else if (cpu_arch_isa == PROCESSOR_K1OM)
2488 {
2489 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2490 || default_arch[6] != '\0')
2491 as_fatal (_("Intel K1OM is 64bit ELF only"));
2492 return bfd_mach_k1om;
2493 }
351f65ca 2494 else if (default_arch[6] == '\0')
8a9036a4 2495 return bfd_mach_x86_64;
351f65ca
L		 2496 else
2497 return bfd_mach_x64_32;
8a9036a4 2498 }
b9d79e03
JH		 2499 else if (!strcmp (default_arch, "i386"))
2500 return bfd_mach_i386_i386;
2501 else
2b5d6a91 2502 as_fatal (_("unknown architecture"));
b9d79e03 2503}
b9d79e03 2504\f
252b5132 2505void
7016a5d5 2506md_begin (void)
252b5132
RH		 2507{
2508 const char *hash_err;
2509
47926f60 2510 /* Initialize op_hash hash table. */
252b5132
RH		 2511 op_hash = hash_new ();
2512
2513 {
d3ce72d0 2514 const insn_template *optab;
29b0f896 2515 templates *core_optab;
252b5132 2516
47926f60
KH		 2517 /* Setup for loop. */
2518 optab = i386_optab;
252b5132
RH		 2519 core_optab = (templates *) xmalloc (sizeof (templates));
2520 core_optab->start = optab;
2521
2522 while (1)
2523 {
2524 ++optab;
2525 if (optab->name == NULL
2526 || strcmp (optab->name, (optab - 1)->name) != 0)
2527 {
2528 /* different name --> ship out current template list;
47926f60 2529 add to hash table; & begin anew. */
252b5132
RH		 2530 core_optab->end = optab;
2531 hash_err = hash_insert (op_hash,
2532 (optab - 1)->name,
5a49b8ac 2533 (void *) core_optab);
252b5132
RH		 2534 if (hash_err)
2535 {
b37df7c4 2536 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2537 (optab - 1)->name,
2538 hash_err);
2539 }
2540 if (optab->name == NULL)
2541 break;
2542 core_optab = (templates *) xmalloc (sizeof (templates));
2543 core_optab->start = optab;
2544 }
2545 }
2546 }
2547
47926f60 2548 /* Initialize reg_hash hash table. */
252b5132
RH		 2549 reg_hash = hash_new ();
2550 {
29b0f896 2551 const reg_entry *regtab;
c3fe08fa 2552 unsigned int regtab_size = i386_regtab_size;
252b5132 2553
c3fe08fa 2554 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2555 {
5a49b8ac 2556 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2557 if (hash_err)
b37df7c4 2558 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2559 regtab->reg_name,
2560 hash_err);
252b5132
RH		 2561 }
2562 }
2563
47926f60 2564 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2565 {
29b0f896
AM		 2566 int c;
2567 char *p;
252b5132
RH		 2568
2569 for (c = 0; c < 256; c++)
2570 {
3882b010 2571 if (ISDIGIT (c))
252b5132
RH		 2572 {
2573 digit_chars[c] = c;
2574 mnemonic_chars[c] = c;
2575 register_chars[c] = c;
2576 operand_chars[c] = c;
2577 }
3882b010 2578 else if (ISLOWER (c))
252b5132
RH		 2579 {
2580 mnemonic_chars[c] = c;
2581 register_chars[c] = c;
2582 operand_chars[c] = c;
2583 }
3882b010 2584 else if (ISUPPER (c))
252b5132 2585 {
3882b010 2586 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2587 register_chars[c] = mnemonic_chars[c];
2588 operand_chars[c] = c;
2589 }
43234a1e
L		 2590 else if (c == '{' || c == '}')
2591 operand_chars[c] = c;
252b5132 2592
3882b010 2593 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2594 identifier_chars[c] = c;
2595 else if (c >= 128)
2596 {
2597 identifier_chars[c] = c;
2598 operand_chars[c] = c;
2599 }
2600 }
2601
2602#ifdef LEX_AT
2603 identifier_chars['@'] = '@';
32137342
NC		 2604#endif
2605#ifdef LEX_QM
2606 identifier_chars['?'] = '?';
2607 operand_chars['?'] = '?';
252b5132 2608#endif
252b5132 2609 digit_chars['-'] = '-';
c0f3af97 2610 mnemonic_chars['_'] = '_';
791fe849 2611 mnemonic_chars['-'] = '-';
0003779b 2612 mnemonic_chars['.'] = '.';
252b5132
RH		 2613 identifier_chars['_'] = '_';
2614 identifier_chars['.'] = '.';
2615
2616 for (p = operand_special_chars; *p != '\0'; p++)
2617 operand_chars[(unsigned char) *p] = *p;
2618 }
2619
a4447b93
RH		 2620 if (flag_code == CODE_64BIT)
2621 {
ca19b261
KT		 2622#if defined (OBJ_COFF) && defined (TE_PE)
2623 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2624 ? 32 : 16);
2625#else
a4447b93 2626 x86_dwarf2_return_column = 16;
ca19b261 2627#endif
61ff971f 2628 x86_cie_data_alignment = -8;
a4447b93
RH		 2629 }
2630 else
2631 {
2632 x86_dwarf2_return_column = 8;
2633 x86_cie_data_alignment = -4;
2634 }
252b5132
RH		 2635}
2636
2637void
e3bb37b5 2638i386_print_statistics (FILE *file)
252b5132
RH		 2639{
2640 hash_print_statistics (file, "i386 opcode", op_hash);
2641 hash_print_statistics (file, "i386 register", reg_hash);
2642}
2643\f
252b5132
RH		 2644#ifdef DEBUG386
2645
ce8a8b2f 2646/* Debugging routines for md_assemble. */
d3ce72d0 2647static void pte (insn_template *);
40fb9820 2648static void pt (i386_operand_type);
e3bb37b5
L		 2649static void pe (expressionS *);
2650static void ps (symbolS *);
252b5132
RH		 2651
2652static void
e3bb37b5 2653pi (char *line, i386_insn *x)
252b5132 2654{
09137c09 2655 unsigned int j;
252b5132
RH		 2656
2657 fprintf (stdout, "%s: template ", line);
2658 pte (&x->tm);
09f131f2
JH		 2659 fprintf (stdout, " address: base %s index %s scale %x\n",
2660 x->base_reg ? x->base_reg->reg_name : "none",
2661 x->index_reg ? x->index_reg->reg_name : "none",
2662 x->log2_scale_factor);
2663 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2664 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2665 fprintf (stdout, " sib: base %x index %x scale %x\n",
2666 x->sib.base, x->sib.index, x->sib.scale);
2667 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2668 (x->rex & REX_W) != 0,
2669 (x->rex & REX_R) != 0,
2670 (x->rex & REX_X) != 0,
2671 (x->rex & REX_B) != 0);
09137c09 2672 for (j = 0; j < x->operands; j++)
252b5132 2673 {
09137c09
SP		 2674 fprintf (stdout, " #%d: ", j + 1);
2675 pt (x->types[j]);
252b5132 2676 fprintf (stdout, "\n");
09137c09
SP		 2677 if (x->types[j].bitfield.reg8
2678 || x->types[j].bitfield.reg16
2679 || x->types[j].bitfield.reg32
2680 || x->types[j].bitfield.reg64
2681 || x->types[j].bitfield.regmmx
2682 || x->types[j].bitfield.regxmm
2683 || x->types[j].bitfield.regymm
43234a1e 2684 || x->types[j].bitfield.regzmm
09137c09
SP		 2685 || x->types[j].bitfield.sreg2
2686 || x->types[j].bitfield.sreg3
2687 || x->types[j].bitfield.control
2688 || x->types[j].bitfield.debug
2689 || x->types[j].bitfield.test)
2690 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2691 if (operand_type_check (x->types[j], imm))
2692 pe (x->op[j].imms);
2693 if (operand_type_check (x->types[j], disp))
2694 pe (x->op[j].disps);
252b5132
RH		 2695 }
2696}
2697
2698static void
d3ce72d0 2699pte (insn_template *t)
252b5132 2700{
09137c09 2701 unsigned int j;
252b5132 2702 fprintf (stdout, " %d operands ", t->operands);
47926f60 2703 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2704 if (t->extension_opcode != None)
2705 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2706 if (t->opcode_modifier.d)
252b5132 2707 fprintf (stdout, "D");
40fb9820 2708 if (t->opcode_modifier.w)
252b5132
RH		 2709 fprintf (stdout, "W");
2710 fprintf (stdout, "\n");
09137c09 2711 for (j = 0; j < t->operands; j++)
252b5132 2712 {
09137c09
SP		 2713 fprintf (stdout, " #%d type ", j + 1);
2714 pt (t->operand_types[j]);
252b5132
RH		 2715 fprintf (stdout, "\n");
2716 }
2717}
2718
2719static void
e3bb37b5 2720pe (expressionS *e)
252b5132 2721{
24eab124 2722 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2723 fprintf (stdout, " add_number %ld (%lx)\n",
2724 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2725 if (e->X_add_symbol)
2726 {
2727 fprintf (stdout, " add_symbol ");
2728 ps (e->X_add_symbol);
2729 fprintf (stdout, "\n");
2730 }
2731 if (e->X_op_symbol)
2732 {
2733 fprintf (stdout, " op_symbol ");
2734 ps (e->X_op_symbol);
2735 fprintf (stdout, "\n");
2736 }
2737}
2738
2739static void
e3bb37b5 2740ps (symbolS *s)
252b5132
RH		 2741{
2742 fprintf (stdout, "%s type %s%s",
2743 S_GET_NAME (s),
2744 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2745 segment_name (S_GET_SEGMENT (s)));
2746}
2747
7b81dfbb 2748static struct type_name
252b5132 2749 {
40fb9820
L		 2750 i386_operand_type mask;
2751 const char *name;
252b5132 2752 }
7b81dfbb 2753const type_names[] =
252b5132 2754{
40fb9820
L		 2755 { OPERAND_TYPE_REG8, "r8" },
2756 { OPERAND_TYPE_REG16, "r16" },
2757 { OPERAND_TYPE_REG32, "r32" },
2758 { OPERAND_TYPE_REG64, "r64" },
2759 { OPERAND_TYPE_IMM8, "i8" },
2760 { OPERAND_TYPE_IMM8, "i8s" },
2761 { OPERAND_TYPE_IMM16, "i16" },
2762 { OPERAND_TYPE_IMM32, "i32" },
2763 { OPERAND_TYPE_IMM32S, "i32s" },
2764 { OPERAND_TYPE_IMM64, "i64" },
2765 { OPERAND_TYPE_IMM1, "i1" },
2766 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2767 { OPERAND_TYPE_DISP8, "d8" },
2768 { OPERAND_TYPE_DISP16, "d16" },
2769 { OPERAND_TYPE_DISP32, "d32" },
2770 { OPERAND_TYPE_DISP32S, "d32s" },
2771 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2772 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2773 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2774 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2775 { OPERAND_TYPE_CONTROL, "control reg" },
2776 { OPERAND_TYPE_TEST, "test reg" },
2777 { OPERAND_TYPE_DEBUG, "debug reg" },
2778 { OPERAND_TYPE_FLOATREG, "FReg" },
2779 { OPERAND_TYPE_FLOATACC, "FAcc" },
2780 { OPERAND_TYPE_SREG2, "SReg2" },
2781 { OPERAND_TYPE_SREG3, "SReg3" },
2782 { OPERAND_TYPE_ACC, "Acc" },
2783 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2784 { OPERAND_TYPE_REGMMX, "rMMX" },
2785 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2786 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2787 { OPERAND_TYPE_REGZMM, "rZMM" },
2788 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2789 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2790};
2791
2792static void
40fb9820 2793pt (i386_operand_type t)
252b5132 2794{
40fb9820 2795 unsigned int j;
c6fb90c8 2796 i386_operand_type a;
252b5132 2797
40fb9820 2798 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2799 {
2800 a = operand_type_and (t, type_names[j].mask);
0349dc08 2801 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2802 fprintf (stdout, "%s, ", type_names[j].name);
2803 }
252b5132
RH		 2804 fflush (stdout);
2805}
2806
2807#endif /* DEBUG386 */
2808\f
252b5132 2809static bfd_reloc_code_real_type
3956db08 2810reloc (unsigned int size,
64e74474
AM		 2811 int pcrel,
2812 int sign,
c3320543 2813 int bnd_prefix,
64e74474 2814 bfd_reloc_code_real_type other)
252b5132 2815{
47926f60 2816 if (other != NO_RELOC)
3956db08 2817 {
91d6fa6a 2818 reloc_howto_type *rel;
3956db08
JB		 2819
2820 if (size == 8)
2821 switch (other)
2822 {
64e74474
AM		 2823 case BFD_RELOC_X86_64_GOT32:
2824 return BFD_RELOC_X86_64_GOT64;
2825 break;
2826 case BFD_RELOC_X86_64_PLTOFF64:
2827 return BFD_RELOC_X86_64_PLTOFF64;
2828 break;
2829 case BFD_RELOC_X86_64_GOTPC32:
2830 other = BFD_RELOC_X86_64_GOTPC64;
2831 break;
2832 case BFD_RELOC_X86_64_GOTPCREL:
2833 other = BFD_RELOC_X86_64_GOTPCREL64;
2834 break;
2835 case BFD_RELOC_X86_64_TPOFF32:
2836 other = BFD_RELOC_X86_64_TPOFF64;
2837 break;
2838 case BFD_RELOC_X86_64_DTPOFF32:
2839 other = BFD_RELOC_X86_64_DTPOFF64;
2840 break;
2841 default:
2842 break;
3956db08 2843 }
e05278af 2844
8ce3d284 2845#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2846 if (other == BFD_RELOC_SIZE32)
2847 {
2848 if (size == 8)
1ab668bf 2849 other = BFD_RELOC_SIZE64;
8fd4256d 2850 if (pcrel)
1ab668bf
AM		 2851 {
2852 as_bad (_("there are no pc-relative size relocations"));
2853 return NO_RELOC;
2854 }
8fd4256d 2855 }
8ce3d284 2856#endif
8fd4256d 2857
e05278af 2858 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2859 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2860 sign = -1;
2861
91d6fa6a
NC		 2862 rel = bfd_reloc_type_lookup (stdoutput, other);
2863 if (!rel)
3956db08 2864 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2865 else if (size != bfd_get_reloc_size (rel))
3956db08 2866 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2867 bfd_get_reloc_size (rel),
3956db08 2868 size);
91d6fa6a 2869 else if (pcrel && !rel->pc_relative)
3956db08 2870 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2871 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2872 && !sign)
91d6fa6a 2873 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2874 && sign > 0))
3956db08
JB		 2875 as_bad (_("relocated field and relocation type differ in signedness"));
2876 else
2877 return other;
2878 return NO_RELOC;
2879 }
252b5132
RH		 2880
2881 if (pcrel)
2882 {
3e73aa7c 2883 if (!sign)
3956db08 2884 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2885 switch (size)
2886 {
2887 case 1: return BFD_RELOC_8_PCREL;
2888 case 2: return BFD_RELOC_16_PCREL;
c3320543
L		 2889 case 4: return (bnd_prefix && object_64bit
2890 ? BFD_RELOC_X86_64_PC32_BND
2891 : BFD_RELOC_32_PCREL);
d6ab8113 2892 case 8: return BFD_RELOC_64_PCREL;
252b5132 2893 }
3956db08 2894 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2895 }
2896 else
2897 {
3956db08 2898 if (sign > 0)
e5cb08ac 2899 switch (size)
3e73aa7c
JH		 2900 {
2901 case 4: return BFD_RELOC_X86_64_32S;
2902 }
2903 else
2904 switch (size)
2905 {
2906 case 1: return BFD_RELOC_8;
2907 case 2: return BFD_RELOC_16;
2908 case 4: return BFD_RELOC_32;
2909 case 8: return BFD_RELOC_64;
2910 }
3956db08
JB		 2911 as_bad (_("cannot do %s %u byte relocation"),
2912 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2913 }
2914
0cc9e1d3 2915 return NO_RELOC;
252b5132
RH		 2916}
2917
47926f60
KH		 2918/* Here we decide which fixups can be adjusted to make them relative to
2919 the beginning of the section instead of the symbol. Basically we need
2920 to make sure that the dynamic relocations are done correctly, so in
2921 some cases we force the original symbol to be used. */
2922
252b5132 2923int
e3bb37b5 2924tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2925{
6d249963 2926#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2927 if (!IS_ELF)
31312f95
AM		 2928 return 1;
2929
a161fe53
AM		 2930 /* Don't adjust pc-relative references to merge sections in 64-bit
2931 mode. */
2932 if (use_rela_relocations
2933 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2934 && fixP->fx_pcrel)
252b5132 2935 return 0;
31312f95 2936
8d01d9a9
AJ		 2937 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2938 and changed later by validate_fix. */
2939 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2940 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2941 return 0;
2942
8fd4256d
L		 2943 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2944 for size relocations. */
2945 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2946 || fixP->fx_r_type == BFD_RELOC_SIZE64
2947 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2948 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2949 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2950 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2951 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2952 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2953 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2954 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2955 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2956 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2957 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2958 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2959 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2960 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2961 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2962 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2963 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2964 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2965 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2966 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2967 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2968 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2969 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2970 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2971 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2972 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2973 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2974 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2975 return 0;
31312f95 2976#endif
252b5132
RH		 2977 return 1;
2978}
252b5132 2979
b4cac588 2980static int
e3bb37b5 2981intel_float_operand (const char *mnemonic)
252b5132 2982{
9306ca4a
JB		 2983 /* Note that the value returned is meaningful only for opcodes with (memory)
2984 operands, hence the code here is free to improperly handle opcodes that
2985 have no operands (for better performance and smaller code). */
2986
2987 if (mnemonic[0] != 'f')
2988 return 0; /* non-math */
2989
2990 switch (mnemonic[1])
2991 {
2992 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2993 the fs segment override prefix not currently handled because no
2994 call path can make opcodes without operands get here */
2995 case 'i':
2996 return 2 /* integer op */;
2997 case 'l':
2998 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2999 return 3; /* fldcw/fldenv */
3000 break;
3001 case 'n':
3002 if (mnemonic[2] != 'o' /* fnop */)
3003 return 3; /* non-waiting control op */
3004 break;
3005 case 'r':
3006 if (mnemonic[2] == 's')
3007 return 3; /* frstor/frstpm */
3008 break;
3009 case 's':
3010 if (mnemonic[2] == 'a')
3011 return 3; /* fsave */
3012 if (mnemonic[2] == 't')
3013 {
3014 switch (mnemonic[3])
3015 {
3016 case 'c': /* fstcw */
3017 case 'd': /* fstdw */
3018 case 'e': /* fstenv */
3019 case 's': /* fsts[gw] */
3020 return 3;
3021 }
3022 }
3023 break;
3024 case 'x':
3025 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3026 return 0; /* fxsave/fxrstor are not really math ops */
3027 break;
3028 }
252b5132 3029
9306ca4a 3030 return 1;
252b5132
RH		 3031}
3032
c0f3af97
L		 3033/* Build the VEX prefix. */
3034
3035static void
d3ce72d0 3036build_vex_prefix (const insn_template *t)
c0f3af97
L		 3037{
3038 unsigned int register_specifier;
3039 unsigned int implied_prefix;
3040 unsigned int vector_length;
3041
3042 /* Check register specifier. */
3043 if (i.vex.register_specifier)
43234a1e
L		 3044 {
3045 register_specifier =
3046 ~register_number (i.vex.register_specifier) & 0xf;
3047 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3048 }
c0f3af97
L		 3049 else
3050 register_specifier = 0xf;
3051
fa99fab2
L		 3052 /* Use 2-byte VEX prefix by swappping destination and source
3053 operand. */
3054 if (!i.swap_operand
3055 && i.operands == i.reg_operands
7f399153 3056 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3057 && i.tm.opcode_modifier.s
3058 && i.rex == REX_B)
3059 {
3060 unsigned int xchg = i.operands - 1;
3061 union i386_op temp_op;
3062 i386_operand_type temp_type;
3063
3064 temp_type = i.types[xchg];
3065 i.types[xchg] = i.types[0];
3066 i.types[0] = temp_type;
3067 temp_op = i.op[xchg];
3068 i.op[xchg] = i.op[0];
3069 i.op[0] = temp_op;
3070
9c2799c2 3071 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3072
3073 i.rex = REX_R;
3074 xchg = i.rm.regmem;
3075 i.rm.regmem = i.rm.reg;
3076 i.rm.reg = xchg;
3077
3078 /* Use the next insn. */
3079 i.tm = t[1];
3080 }
3081
539f890d
L		 3082 if (i.tm.opcode_modifier.vex == VEXScalar)
3083 vector_length = avxscalar;
3084 else
3085 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3086
3087 switch ((i.tm.base_opcode >> 8) & 0xff)
3088 {
3089 case 0:
3090 implied_prefix = 0;
3091 break;
3092 case DATA_PREFIX_OPCODE:
3093 implied_prefix = 1;
3094 break;
3095 case REPE_PREFIX_OPCODE:
3096 implied_prefix = 2;
3097 break;
3098 case REPNE_PREFIX_OPCODE:
3099 implied_prefix = 3;
3100 break;
3101 default:
3102 abort ();
3103 }
3104
3105 /* Use 2-byte VEX prefix if possible. */
7f399153 3106 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3107 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3108 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3109 {
3110 /* 2-byte VEX prefix. */
3111 unsigned int r;
3112
3113 i.vex.length = 2;
3114 i.vex.bytes[0] = 0xc5;
3115
3116 /* Check the REX.R bit. */
3117 r = (i.rex & REX_R) ? 0 : 1;
3118 i.vex.bytes[1] = (r << 7
3119 | register_specifier << 3
3120 | vector_length << 2
3121 | implied_prefix);
3122 }
3123 else
3124 {
3125 /* 3-byte VEX prefix. */
3126 unsigned int m, w;
3127
f88c9eb0 3128 i.vex.length = 3;
f88c9eb0 3129
7f399153 3130 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3131 {
7f399153
L		 3132 case VEX0F:
3133 m = 0x1;
80de6e00 3134 i.vex.bytes[0] = 0xc4;
7f399153
L		 3135 break;
3136 case VEX0F38:
3137 m = 0x2;
80de6e00 3138 i.vex.bytes[0] = 0xc4;
7f399153
L		 3139 break;
3140 case VEX0F3A:
3141 m = 0x3;
80de6e00 3142 i.vex.bytes[0] = 0xc4;
7f399153
L		 3143 break;
3144 case XOP08:
5dd85c99
SP		 3145 m = 0x8;
3146 i.vex.bytes[0] = 0x8f;
7f399153
L		 3147 break;
3148 case XOP09:
f88c9eb0
SP		 3149 m = 0x9;
3150 i.vex.bytes[0] = 0x8f;
7f399153
L		 3151 break;
3152 case XOP0A:
f88c9eb0
SP		 3153 m = 0xa;
3154 i.vex.bytes[0] = 0x8f;
7f399153
L		 3155 break;
3156 default:
3157 abort ();
f88c9eb0 3158 }
c0f3af97 3159
c0f3af97
L		 3160 /* The high 3 bits of the second VEX byte are 1's compliment
3161 of RXB bits from REX. */
3162 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3163
3164 /* Check the REX.W bit. */
3165 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 3166 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 3167 {
3168 if (w)
3169 abort ();
3170
1ef99a7b 3171 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 3172 w = 1;
3173 }
3174
3175 i.vex.bytes[2] = (w << 7
3176 | register_specifier << 3
3177 | vector_length << 2
3178 | implied_prefix);
3179 }
3180}
3181
43234a1e
L		 3182/* Build the EVEX prefix. */
3183
3184static void
3185build_evex_prefix (void)
3186{
3187 unsigned int register_specifier;
3188 unsigned int implied_prefix;
3189 unsigned int m, w;
3190 rex_byte vrex_used = 0;
3191
3192 /* Check register specifier. */
3193 if (i.vex.register_specifier)
3194 {
3195 gas_assert ((i.vrex & REX_X) == 0);
3196
3197 register_specifier = i.vex.register_specifier->reg_num;
3198 if ((i.vex.register_specifier->reg_flags & RegRex))
3199 register_specifier += 8;
3200 /* The upper 16 registers are encoded in the fourth byte of the
3201 EVEX prefix. */
3202 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3203 i.vex.bytes[3] = 0x8;
3204 register_specifier = ~register_specifier & 0xf;
3205 }
3206 else
3207 {
3208 register_specifier = 0xf;
3209
3210 /* Encode upper 16 vector index register in the fourth byte of
3211 the EVEX prefix. */
3212 if (!(i.vrex & REX_X))
3213 i.vex.bytes[3] = 0x8;
3214 else
3215 vrex_used |= REX_X;
3216 }
3217
3218 switch ((i.tm.base_opcode >> 8) & 0xff)
3219 {
3220 case 0:
3221 implied_prefix = 0;
3222 break;
3223 case DATA_PREFIX_OPCODE:
3224 implied_prefix = 1;
3225 break;
3226 case REPE_PREFIX_OPCODE:
3227 implied_prefix = 2;
3228 break;
3229 case REPNE_PREFIX_OPCODE:
3230 implied_prefix = 3;
3231 break;
3232 default:
3233 abort ();
3234 }
3235
3236 /* 4 byte EVEX prefix. */
3237 i.vex.length = 4;
3238 i.vex.bytes[0] = 0x62;
3239
3240 /* mmmm bits. */
3241 switch (i.tm.opcode_modifier.vexopcode)
3242 {
3243 case VEX0F:
3244 m = 1;
3245 break;
3246 case VEX0F38:
3247 m = 2;
3248 break;
3249 case VEX0F3A:
3250 m = 3;
3251 break;
3252 default:
3253 abort ();
3254 break;
3255 }
3256
3257 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3258 bits from REX. */
3259 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3260
3261 /* The fifth bit of the second EVEX byte is 1's compliment of the
3262 REX_R bit in VREX. */
3263 if (!(i.vrex & REX_R))
3264 i.vex.bytes[1] |= 0x10;
3265 else
3266 vrex_used |= REX_R;
3267
3268 if ((i.reg_operands + i.imm_operands) == i.operands)
3269 {
3270 /* When all operands are registers, the REX_X bit in REX is not
3271 used. We reuse it to encode the upper 16 registers, which is
3272 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3273 as 1's compliment. */
3274 if ((i.vrex & REX_B))
3275 {
3276 vrex_used |= REX_B;
3277 i.vex.bytes[1] &= ~0x40;
3278 }
3279 }
3280
3281 /* EVEX instructions shouldn't need the REX prefix. */
3282 i.vrex &= ~vrex_used;
3283 gas_assert (i.vrex == 0);
3284
3285 /* Check the REX.W bit. */
3286 w = (i.rex & REX_W) ? 1 : 0;
3287 if (i.tm.opcode_modifier.vexw)
3288 {
3289 if (i.tm.opcode_modifier.vexw == VEXW1)
3290 w = 1;
3291 }
3292 /* If w is not set it means we are dealing with WIG instruction. */
3293 else if (!w)
3294 {
3295 if (evexwig == evexw1)
3296 w = 1;
3297 }
3298
3299 /* Encode the U bit. */
3300 implied_prefix |= 0x4;
3301
3302 /* The third byte of the EVEX prefix. */
3303 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3304
3305 /* The fourth byte of the EVEX prefix. */
3306 /* The zeroing-masking bit. */
3307 if (i.mask && i.mask->zeroing)
3308 i.vex.bytes[3] |= 0x80;
3309
3310 /* Don't always set the broadcast bit if there is no RC. */
3311 if (!i.rounding)
3312 {
3313 /* Encode the vector length. */
3314 unsigned int vec_length;
3315
3316 switch (i.tm.opcode_modifier.evex)
3317 {
3318 case EVEXLIG: /* LL' is ignored */
3319 vec_length = evexlig << 5;
3320 break;
3321 case EVEX128:
3322 vec_length = 0 << 5;
3323 break;
3324 case EVEX256:
3325 vec_length = 1 << 5;
3326 break;
3327 case EVEX512:
3328 vec_length = 2 << 5;
3329 break;
3330 default:
3331 abort ();
3332 break;
3333 }
3334 i.vex.bytes[3] |= vec_length;
3335 /* Encode the broadcast bit. */
3336 if (i.broadcast)
3337 i.vex.bytes[3] |= 0x10;
3338 }
3339 else
3340 {
3341 if (i.rounding->type != saeonly)
3342 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3343 else
3344 i.vex.bytes[3] |= 0x10;
3345 }
3346
3347 if (i.mask && i.mask->mask)
3348 i.vex.bytes[3] |= i.mask->mask->reg_num;
3349}
3350
65da13b5
L		 3351static void
3352process_immext (void)
3353{
3354 expressionS *exp;
3355
4c692bc7
JB		 3356 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3357 && i.operands > 0)
65da13b5 3358 {
4c692bc7
JB		 3359 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3360 with an opcode suffix which is coded in the same place as an
3361 8-bit immediate field would be.
3362 Here we check those operands and remove them afterwards. */
65da13b5
L		 3363 unsigned int x;
3364
3365 for (x = 0; x < i.operands; x++)
4c692bc7 3366 if (register_number (i.op[x].regs) != x)
65da13b5 3367 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3368 register_prefix, i.op[x].regs->reg_name, x + 1,
3369 i.tm.name);
3370
3371 i.operands = 0;
65da13b5
L		 3372 }
3373
c0f3af97 3374 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3375 which is coded in the same place as an 8-bit immediate field
3376 would be. Here we fake an 8-bit immediate operand from the
3377 opcode suffix stored in tm.extension_opcode.
3378
c1e679ec 3379 AVX instructions also use this encoding, for some of
c0f3af97 3380 3 argument instructions. */
65da13b5 3381
43234a1e 3382 gas_assert (i.imm_operands <= 1
7ab9ffdd 3383 && (i.operands <= 2
43234a1e
L		 3384 || ((i.tm.opcode_modifier.vex
3385 || i.tm.opcode_modifier.evex)
7ab9ffdd 3386 && i.operands <= 4)));
65da13b5
L		 3387
3388 exp = &im_expressions[i.imm_operands++];
3389 i.op[i.operands].imms = exp;
3390 i.types[i.operands] = imm8;
3391 i.operands++;
3392 exp->X_op = O_constant;
3393 exp->X_add_number = i.tm.extension_opcode;
3394 i.tm.extension_opcode = None;
3395}
3396
42164a71
L		 3397
3398static int
3399check_hle (void)
3400{
3401 switch (i.tm.opcode_modifier.hleprefixok)
3402 {
3403 default:
3404 abort ();
82c2def5 3405 case HLEPrefixNone:
165de32a
L		 3406 as_bad (_("invalid instruction `%s' after `%s'"),
3407 i.tm.name, i.hle_prefix);
42164a71 3408 return 0;
82c2def5 3409 case HLEPrefixLock:
42164a71
L		 3410 if (i.prefix[LOCK_PREFIX])
3411 return 1;
165de32a 3412 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3413 return 0;
82c2def5 3414 case HLEPrefixAny:
42164a71 3415 return 1;
82c2def5 3416 case HLEPrefixRelease:
42164a71
L		 3417 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3418 {
3419 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3420 i.tm.name);
3421 return 0;
3422 }
3423 if (i.mem_operands == 0
3424 || !operand_type_check (i.types[i.operands - 1], anymem))
3425 {
3426 as_bad (_("memory destination needed for instruction `%s'"
3427 " after `xrelease'"), i.tm.name);
3428 return 0;
3429 }
3430 return 1;
3431 }
3432}
3433
252b5132
RH		 3434/* This is the guts of the machine-dependent assembler. LINE points to a
3435 machine dependent instruction. This function is supposed to emit
3436 the frags/bytes it assembles to. */
3437
3438void
65da13b5 3439md_assemble (char *line)
252b5132 3440{
40fb9820 3441 unsigned int j;
252b5132 3442 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3443 const insn_template *t;
252b5132 3444
47926f60 3445 /* Initialize globals. */
252b5132
RH		 3446 memset (&i, '\0', sizeof (i));
3447 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3448 i.reloc[j] = NO_RELOC;
252b5132
RH		 3449 memset (disp_expressions, '\0', sizeof (disp_expressions));
3450 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3451 save_stack_p = save_stack;
252b5132
RH		 3452
3453 /* First parse an instruction mnemonic & call i386_operand for the operands.
3454 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3455 start of a (possibly prefixed) mnemonic. */
252b5132 3456
29b0f896
AM		 3457 line = parse_insn (line, mnemonic);
3458 if (line == NULL)
3459 return;
252b5132 3460
29b0f896 3461 line = parse_operands (line, mnemonic);
ee86248c 3462 this_operand = -1;
29b0f896
AM		 3463 if (line == NULL)
3464 return;
252b5132 3465
29b0f896
AM		 3466 /* Now we've parsed the mnemonic into a set of templates, and have the
3467 operands at hand. */
3468
3469 /* All intel opcodes have reversed operands except for "bound" and
3470 "enter". We also don't reverse intersegment "jmp" and "call"
3471 instructions with 2 immediate operands so that the immediate segment
050dfa73 3472 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3473 if (intel_syntax
3474 && i.operands > 1
29b0f896 3475 && (strcmp (mnemonic, "bound") != 0)
30123838 3476 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3477 && !(operand_type_check (i.types[0], imm)
3478 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3479 swap_operands ();
3480
ec56d5c0
JB		 3481 /* The order of the immediates should be reversed
3482 for 2 immediates extrq and insertq instructions */
3483 if (i.imm_operands == 2
3484 && (strcmp (mnemonic, "extrq") == 0
3485 || strcmp (mnemonic, "insertq") == 0))
3486 swap_2_operands (0, 1);
3487
29b0f896
AM		 3488 if (i.imm_operands)
3489 optimize_imm ();
3490
b300c311
L		 3491 /* Don't optimize displacement for movabs since it only takes 64bit
3492 displacement. */
3493 if (i.disp_operands
a501d77e 3494 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3495 && (flag_code != CODE_64BIT
3496 || strcmp (mnemonic, "movabs") != 0))
3497 optimize_disp ();
29b0f896
AM		 3498
3499 /* Next, we find a template that matches the given insn,
3500 making sure the overlap of the given operands types is consistent
3501 with the template operand types. */
252b5132 3502
fa99fab2 3503 if (!(t = match_template ()))
29b0f896 3504 return;
252b5132 3505
7bab8ab5 3506 if (sse_check != check_none
81f8a913 3507 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3508 && (i.tm.cpu_flags.bitfield.cpusse
3509 || i.tm.cpu_flags.bitfield.cpusse2
3510 || i.tm.cpu_flags.bitfield.cpusse3
3511 || i.tm.cpu_flags.bitfield.cpussse3
3512 || i.tm.cpu_flags.bitfield.cpusse4_1
3513 || i.tm.cpu_flags.bitfield.cpusse4_2))
3514 {
7bab8ab5 3515 (sse_check == check_warning
daf50ae7
L		 3516 ? as_warn
3517 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3518 }
3519
321fd21e
L		 3520 /* Zap movzx and movsx suffix. The suffix has been set from
3521 "word ptr" or "byte ptr" on the source operand in Intel syntax
3522 or extracted from mnemonic in AT&T syntax. But we'll use
3523 the destination register to choose the suffix for encoding. */
3524 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3525 {
321fd21e
L		 3526 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3527 there is no suffix, the default will be byte extension. */
3528 if (i.reg_operands != 2
3529 && !i.suffix
7ab9ffdd 3530 && intel_syntax)
321fd21e
L		 3531 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3532
3533 i.suffix = 0;
cd61ebfe 3534 }
24eab124 3535
40fb9820 3536 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3537 if (!add_prefix (FWAIT_OPCODE))
3538 return;
252b5132 3539
d5de92cf
L		 3540 /* Check if REP prefix is OK. */
3541 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3542 {
3543 as_bad (_("invalid instruction `%s' after `%s'"),
3544 i.tm.name, i.rep_prefix);
3545 return;
3546 }
3547
c1ba0266
L		 3548 /* Check for lock without a lockable instruction. Destination operand
3549 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3550 if (i.prefix[LOCK_PREFIX]
3551 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3552 || i.mem_operands == 0
3553 || (i.tm.base_opcode != 0x86
3554 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3555 {
3556 as_bad (_("expecting lockable instruction after `lock'"));
3557 return;
3558 }
3559
42164a71 3560 /* Check if HLE prefix is OK. */
165de32a 3561 if (i.hle_prefix && !check_hle ())
42164a71
L		 3562 return;
3563
7e8b059b
L		 3564 /* Check BND prefix. */
3565 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3566 as_bad (_("expecting valid branch instruction after `bnd'"));
3567
3568 if (i.tm.cpu_flags.bitfield.cpumpx
3569 && flag_code == CODE_64BIT
3570 && i.prefix[ADDR_PREFIX])
3571 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3572
3573 /* Insert BND prefix. */
3574 if (add_bnd_prefix
3575 && i.tm.opcode_modifier.bndprefixok
3576 && !i.prefix[BND_PREFIX])
3577 add_prefix (BND_PREFIX_OPCODE);
3578
29b0f896 3579 /* Check string instruction segment overrides. */
40fb9820 3580 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3581 {
3582 if (!check_string ())
5dd0794d 3583 return;
fc0763e6 3584 i.disp_operands = 0;
29b0f896 3585 }
5dd0794d 3586
29b0f896
AM		 3587 if (!process_suffix ())
3588 return;
e413e4e9 3589
bc0844ae
L		 3590 /* Update operand types. */
3591 for (j = 0; j < i.operands; j++)
3592 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3593
29b0f896
AM		 3594 /* Make still unresolved immediate matches conform to size of immediate
3595 given in i.suffix. */
3596 if (!finalize_imm ())
3597 return;
252b5132 3598
40fb9820 3599 if (i.types[0].bitfield.imm1)
29b0f896 3600 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3601
9afe6eb8
L		 3602 /* We only need to check those implicit registers for instructions
3603 with 3 operands or less. */
3604 if (i.operands <= 3)
3605 for (j = 0; j < i.operands; j++)
3606 if (i.types[j].bitfield.inoutportreg
3607 || i.types[j].bitfield.shiftcount
3608 || i.types[j].bitfield.acc
3609 || i.types[j].bitfield.floatacc)
3610 i.reg_operands--;
40fb9820 3611
c0f3af97
L		 3612 /* ImmExt should be processed after SSE2AVX. */
3613 if (!i.tm.opcode_modifier.sse2avx
3614 && i.tm.opcode_modifier.immext)
65da13b5 3615 process_immext ();
252b5132 3616
29b0f896
AM		 3617 /* For insns with operands there are more diddles to do to the opcode. */
3618 if (i.operands)
3619 {
3620 if (!process_operands ())
3621 return;
3622 }
40fb9820 3623 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3624 {
3625 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3626 as_warn (_("translating to `%sp'"), i.tm.name);
3627 }
252b5132 3628
c0f3af97 3629 if (i.tm.opcode_modifier.vex)
fa99fab2 3630 build_vex_prefix (t);
c0f3af97 3631
43234a1e
L		 3632 if (i.tm.opcode_modifier.evex)
3633 build_evex_prefix ();
3634
5dd85c99
SP		 3635 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3636 instructions may define INT_OPCODE as well, so avoid this corner
3637 case for those instructions that use MODRM. */
3638 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3639 && !i.tm.opcode_modifier.modrm
3640 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3641 {
3642 i.tm.base_opcode = INT3_OPCODE;
3643 i.imm_operands = 0;
3644 }
252b5132 3645
40fb9820
L		 3646 if ((i.tm.opcode_modifier.jump
3647 || i.tm.opcode_modifier.jumpbyte
3648 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3649 && i.op[0].disps->X_op == O_constant)
3650 {
3651 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3652 the absolute address given by the constant. Since ix86 jumps and
3653 calls are pc relative, we need to generate a reloc. */
3654 i.op[0].disps->X_add_symbol = &abs_symbol;
3655 i.op[0].disps->X_op = O_symbol;
3656 }
252b5132 3657
40fb9820 3658 if (i.tm.opcode_modifier.rex64)
161a04f6 3659 i.rex |= REX_W;
252b5132 3660
29b0f896
AM		 3661 /* For 8 bit registers we need an empty rex prefix. Also if the
3662 instruction already has a prefix, we need to convert old
3663 registers to new ones. */
773f551c 3664
40fb9820 3665 if ((i.types[0].bitfield.reg8
29b0f896 3666 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3667 || (i.types[1].bitfield.reg8
29b0f896 3668 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3669 || ((i.types[0].bitfield.reg8
3670 || i.types[1].bitfield.reg8)
29b0f896
AM		 3671 && i.rex != 0))
3672 {
3673 int x;
726c5dcd 3674
29b0f896
AM		 3675 i.rex |= REX_OPCODE;
3676 for (x = 0; x < 2; x++)
3677 {
3678 /* Look for 8 bit operand that uses old registers. */
40fb9820 3679 if (i.types[x].bitfield.reg8
29b0f896 3680 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3681 {
29b0f896
AM		 3682 /* In case it is "hi" register, give up. */
3683 if (i.op[x].regs->reg_num > 3)
a540244d 3684 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3685 "instruction requiring REX prefix."),
a540244d 3686 register_prefix, i.op[x].regs->reg_name);
773f551c 3687
29b0f896
AM		 3688 /* Otherwise it is equivalent to the extended register.
3689 Since the encoding doesn't change this is merely
3690 cosmetic cleanup for debug output. */
3691
3692 i.op[x].regs = i.op[x].regs + 8;
773f551c 3693 }
29b0f896
AM		 3694 }
3695 }
773f551c 3696
7ab9ffdd 3697 if (i.rex != 0)
29b0f896
AM		 3698 add_prefix (REX_OPCODE | i.rex);
3699
3700 /* We are ready to output the insn. */
3701 output_insn ();
3702}
3703
3704static char *
e3bb37b5 3705parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3706{
3707 char *l = line;
3708 char *token_start = l;
3709 char *mnem_p;
5c6af06e 3710 int supported;
d3ce72d0 3711 const insn_template *t;
b6169b20 3712 char *dot_p = NULL;
29b0f896 3713
29b0f896
AM		 3714 while (1)
3715 {
3716 mnem_p = mnemonic;
3717 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3718 {
b6169b20
L		 3719 if (*mnem_p == '.')
3720 dot_p = mnem_p;
29b0f896
AM		 3721 mnem_p++;
3722 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3723 {
29b0f896
AM		 3724 as_bad (_("no such instruction: `%s'"), token_start);
3725 return NULL;
3726 }
3727 l++;
3728 }
3729 if (!is_space_char (*l)
3730 && *l != END_OF_INSN
e44823cf
JB		 3731 && (intel_syntax
3732 || (*l != PREFIX_SEPARATOR
3733 && *l != ',')))
29b0f896
AM		 3734 {
3735 as_bad (_("invalid character %s in mnemonic"),
3736 output_invalid (*l));
3737 return NULL;
3738 }
3739 if (token_start == l)
3740 {
e44823cf 3741 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3742 as_bad (_("expecting prefix; got nothing"));
3743 else
3744 as_bad (_("expecting mnemonic; got nothing"));
3745 return NULL;
3746 }
45288df1 3747
29b0f896 3748 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3749 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3750
29b0f896
AM		 3751 if (*l != END_OF_INSN
3752 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3753 && current_templates
40fb9820 3754 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3755 {
c6fb90c8 3756 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3757 {
3758 as_bad ((flag_code != CODE_64BIT
3759 ? _("`%s' is only supported in 64-bit mode")
3760 : _("`%s' is not supported in 64-bit mode")),
3761 current_templates->start->name);
3762 return NULL;
3763 }
29b0f896
AM		 3764 /* If we are in 16-bit mode, do not allow addr16 or data16.
3765 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3766 if ((current_templates->start->opcode_modifier.size16
3767 || current_templates->start->opcode_modifier.size32)
29b0f896 3768 && flag_code != CODE_64BIT
40fb9820 3769 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3770 ^ (flag_code == CODE_16BIT)))
3771 {
3772 as_bad (_("redundant %s prefix"),
3773 current_templates->start->name);
3774 return NULL;
45288df1 3775 }
29b0f896
AM		 3776 /* Add prefix, checking for repeated prefixes. */
3777 switch (add_prefix (current_templates->start->base_opcode))
3778 {
c32fa91d 3779 case PREFIX_EXIST:
29b0f896 3780 return NULL;
c32fa91d 3781 case PREFIX_REP:
42164a71 3782 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3783 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3784 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3785 i.bnd_prefix = current_templates->start->name;
42164a71 3786 else
d5de92cf 3787 i.rep_prefix = current_templates->start->name;
29b0f896 3788 break;
c32fa91d
L		 3789 default:
3790 break;
29b0f896
AM		 3791 }
3792 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3793 token_start = ++l;
3794 }
3795 else
3796 break;
3797 }
45288df1 3798
30a55f88 3799 if (!current_templates)
b6169b20 3800 {
f8a5c266
L		 3801 /* Check if we should swap operand or force 32bit displacement in
3802 encoding. */
30a55f88
L		 3803 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3804 i.swap_operand = 1;
8d63c93e 3805 else if (mnem_p - 3 == dot_p
a501d77e
L		 3806 && dot_p[1] == 'd'
3807 && dot_p[2] == '8')
3808 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3809 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3810 && dot_p[1] == 'd'
3811 && dot_p[2] == '3'
3812 && dot_p[3] == '2')
a501d77e 3813 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3814 else
3815 goto check_suffix;
3816 mnem_p = dot_p;
3817 *dot_p = '\0';
d3ce72d0 3818 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3819 }
3820
29b0f896
AM		 3821 if (!current_templates)
3822 {
b6169b20 3823check_suffix:
29b0f896
AM		 3824 /* See if we can get a match by trimming off a suffix. */
3825 switch (mnem_p[-1])
3826 {
3827 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3828 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3829 i.suffix = SHORT_MNEM_SUFFIX;
3830 else
29b0f896
AM		 3831 case BYTE_MNEM_SUFFIX:
3832 case QWORD_MNEM_SUFFIX:
3833 i.suffix = mnem_p[-1];
3834 mnem_p[-1] = '\0';
d3ce72d0
NC		 3835 current_templates = (const templates *) hash_find (op_hash,
3836 mnemonic);
29b0f896
AM		 3837 break;
3838 case SHORT_MNEM_SUFFIX:
3839 case LONG_MNEM_SUFFIX:
3840 if (!intel_syntax)
3841 {
3842 i.suffix = mnem_p[-1];
3843 mnem_p[-1] = '\0';
d3ce72d0
NC		 3844 current_templates = (const templates *) hash_find (op_hash,
3845 mnemonic);
29b0f896
AM		 3846 }
3847 break;
252b5132 3848
29b0f896
AM		 3849 /* Intel Syntax. */
3850 case 'd':
3851 if (intel_syntax)
3852 {
9306ca4a 3853 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3854 i.suffix = SHORT_MNEM_SUFFIX;
3855 else
3856 i.suffix = LONG_MNEM_SUFFIX;
3857 mnem_p[-1] = '\0';
d3ce72d0
NC		 3858 current_templates = (const templates *) hash_find (op_hash,
3859 mnemonic);
29b0f896
AM		 3860 }
3861 break;
3862 }
3863 if (!current_templates)
3864 {
3865 as_bad (_("no such instruction: `%s'"), token_start);
3866 return NULL;
3867 }
3868 }
252b5132 3869
40fb9820
L		 3870 if (current_templates->start->opcode_modifier.jump
3871 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3872 {
3873 /* Check for a branch hint. We allow ",pt" and ",pn" for
3874 predict taken and predict not taken respectively.
3875 I'm not sure that branch hints actually do anything on loop
3876 and jcxz insns (JumpByte) for current Pentium4 chips. They
3877 may work in the future and it doesn't hurt to accept them
3878 now. */
3879 if (l[0] == ',' && l[1] == 'p')
3880 {
3881 if (l[2] == 't')
3882 {
3883 if (!add_prefix (DS_PREFIX_OPCODE))
3884 return NULL;
3885 l += 3;
3886 }
3887 else if (l[2] == 'n')
3888 {
3889 if (!add_prefix (CS_PREFIX_OPCODE))
3890 return NULL;
3891 l += 3;
3892 }
3893 }
3894 }
3895 /* Any other comma loses. */
3896 if (*l == ',')
3897 {
3898 as_bad (_("invalid character %s in mnemonic"),
3899 output_invalid (*l));
3900 return NULL;
3901 }
252b5132 3902
29b0f896 3903 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3904 supported = 0;
3905 for (t = current_templates->start; t < current_templates->end; ++t)
3906 {
c0f3af97
L		 3907 supported |= cpu_flags_match (t);
3908 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3909 goto skip;
5c6af06e 3910 }
3629bb00 3911
c0f3af97 3912 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3913 {
3914 as_bad (flag_code == CODE_64BIT
3915 ? _("`%s' is not supported in 64-bit mode")
3916 : _("`%s' is only supported in 64-bit mode"),
3917 current_templates->start->name);
3918 return NULL;
3919 }
c0f3af97 3920 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3921 {
3629bb00 3922 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3923 current_templates->start->name,
41aacd83 3924 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3925 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3926 return NULL;
29b0f896 3927 }
3629bb00
L		 3928
3929skip:
3930 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3931 && (flag_code != CODE_16BIT))
29b0f896
AM		 3932 {
3933 as_warn (_("use .code16 to ensure correct addressing mode"));
3934 }
252b5132 3935
29b0f896
AM		 3936 return l;
3937}
252b5132 3938
29b0f896 3939static char *
e3bb37b5 3940parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3941{
3942 char *token_start;
3138f287 3943
29b0f896
AM		 3944 /* 1 if operand is pending after ','. */
3945 unsigned int expecting_operand = 0;
252b5132 3946
29b0f896
AM		 3947 /* Non-zero if operand parens not balanced. */
3948 unsigned int paren_not_balanced;
3949
3950 while (*l != END_OF_INSN)
3951 {
3952 /* Skip optional white space before operand. */
3953 if (is_space_char (*l))
3954 ++l;
3955 if (!is_operand_char (*l) && *l != END_OF_INSN)
3956 {
3957 as_bad (_("invalid character %s before operand %d"),
3958 output_invalid (*l),
3959 i.operands + 1);
3960 return NULL;
3961 }
3962 token_start = l; /* after white space */
3963 paren_not_balanced = 0;
3964 while (paren_not_balanced || *l != ',')
3965 {
3966 if (*l == END_OF_INSN)
3967 {
3968 if (paren_not_balanced)
3969 {
3970 if (!intel_syntax)
3971 as_bad (_("unbalanced parenthesis in operand %d."),
3972 i.operands + 1);
3973 else
3974 as_bad (_("unbalanced brackets in operand %d."),
3975 i.operands + 1);
3976 return NULL;
3977 }
3978 else
3979 break; /* we are done */
3980 }
3981 else if (!is_operand_char (*l) && !is_space_char (*l))
3982 {
3983 as_bad (_("invalid character %s in operand %d"),
3984 output_invalid (*l),
3985 i.operands + 1);
3986 return NULL;
3987 }
3988 if (!intel_syntax)
3989 {
3990 if (*l == '(')
3991 ++paren_not_balanced;
3992 if (*l == ')')
3993 --paren_not_balanced;
3994 }
3995 else
3996 {
3997 if (*l == '[')
3998 ++paren_not_balanced;
3999 if (*l == ']')
4000 --paren_not_balanced;
4001 }
4002 l++;
4003 }
4004 if (l != token_start)
4005 { /* Yes, we've read in another operand. */
4006 unsigned int operand_ok;
4007 this_operand = i.operands++;
7d5e4556 4008 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4009 if (i.operands > MAX_OPERANDS)
4010 {
4011 as_bad (_("spurious operands; (%d operands/instruction max)"),
4012 MAX_OPERANDS);
4013 return NULL;
4014 }
4015 /* Now parse operand adding info to 'i' as we go along. */
4016 END_STRING_AND_SAVE (l);
4017
4018 if (intel_syntax)
4019 operand_ok =
4020 i386_intel_operand (token_start,
4021 intel_float_operand (mnemonic));
4022 else
a7619375 4023 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4024
4025 RESTORE_END_STRING (l);
4026 if (!operand_ok)
4027 return NULL;
4028 }
4029 else
4030 {
4031 if (expecting_operand)
4032 {
4033 expecting_operand_after_comma:
4034 as_bad (_("expecting operand after ','; got nothing"));
4035 return NULL;
4036 }
4037 if (*l == ',')
4038 {
4039 as_bad (_("expecting operand before ','; got nothing"));
4040 return NULL;
4041 }
4042 }
7f3f1ea2 4043
29b0f896
AM		 4044 /* Now *l must be either ',' or END_OF_INSN. */
4045 if (*l == ',')
4046 {
4047 if (*++l == END_OF_INSN)
4048 {
4049 /* Just skip it, if it's \n complain. */
4050 goto expecting_operand_after_comma;
4051 }
4052 expecting_operand = 1;
4053 }
4054 }
4055 return l;
4056}
7f3f1ea2 4057
050dfa73 4058static void
4d456e3d 4059swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4060{
4061 union i386_op temp_op;
40fb9820 4062 i386_operand_type temp_type;
050dfa73 4063 enum bfd_reloc_code_real temp_reloc;
4eed87de 4064
050dfa73
MM		 4065 temp_type = i.types[xchg2];
4066 i.types[xchg2] = i.types[xchg1];
4067 i.types[xchg1] = temp_type;
4068 temp_op = i.op[xchg2];
4069 i.op[xchg2] = i.op[xchg1];
4070 i.op[xchg1] = temp_op;
4071 temp_reloc = i.reloc[xchg2];
4072 i.reloc[xchg2] = i.reloc[xchg1];
4073 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4074
4075 if (i.mask)
4076 {
4077 if (i.mask->operand == xchg1)
4078 i.mask->operand = xchg2;
4079 else if (i.mask->operand == xchg2)
4080 i.mask->operand = xchg1;
4081 }
4082 if (i.broadcast)
4083 {
4084 if (i.broadcast->operand == xchg1)
4085 i.broadcast->operand = xchg2;
4086 else if (i.broadcast->operand == xchg2)
4087 i.broadcast->operand = xchg1;
4088 }
4089 if (i.rounding)
4090 {
4091 if (i.rounding->operand == xchg1)
4092 i.rounding->operand = xchg2;
4093 else if (i.rounding->operand == xchg2)
4094 i.rounding->operand = xchg1;
4095 }
050dfa73
MM		 4096}
4097
29b0f896 4098static void
e3bb37b5 4099swap_operands (void)
29b0f896 4100{
b7c61d9a 4101 switch (i.operands)
050dfa73 4102 {
c0f3af97 4103 case 5:
b7c61d9a 4104 case 4:
4d456e3d 4105 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4106 case 3:
4107 case 2:
4d456e3d 4108 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4109 break;
4110 default:
4111 abort ();
29b0f896 4112 }
29b0f896
AM		 4113
4114 if (i.mem_operands == 2)
4115 {
4116 const seg_entry *temp_seg;
4117 temp_seg = i.seg[0];
4118 i.seg[0] = i.seg[1];
4119 i.seg[1] = temp_seg;
4120 }
4121}
252b5132 4122
29b0f896
AM		 4123/* Try to ensure constant immediates are represented in the smallest
4124 opcode possible. */
4125static void
e3bb37b5 4126optimize_imm (void)
29b0f896
AM		 4127{
4128 char guess_suffix = 0;
4129 int op;
252b5132 4130
29b0f896
AM		 4131 if (i.suffix)
4132 guess_suffix = i.suffix;
4133 else if (i.reg_operands)
4134 {
4135 /* Figure out a suffix from the last register operand specified.
4136 We can't do this properly yet, ie. excluding InOutPortReg,
4137 but the following works for instructions with immediates.
4138 In any case, we can't set i.suffix yet. */
4139 for (op = i.operands; --op >= 0;)
40fb9820 4140 if (i.types[op].bitfield.reg8)
7ab9ffdd 4141 {
40fb9820
L		 4142 guess_suffix = BYTE_MNEM_SUFFIX;
4143 break;
4144 }
4145 else if (i.types[op].bitfield.reg16)
252b5132 4146 {
40fb9820
L		 4147 guess_suffix = WORD_MNEM_SUFFIX;
4148 break;
4149 }
4150 else if (i.types[op].bitfield.reg32)
4151 {
4152 guess_suffix = LONG_MNEM_SUFFIX;
4153 break;
4154 }
4155 else if (i.types[op].bitfield.reg64)
4156 {
4157 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4158 break;
252b5132 4159 }
29b0f896
AM		 4160 }
4161 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4162 guess_suffix = WORD_MNEM_SUFFIX;
4163
4164 for (op = i.operands; --op >= 0;)
40fb9820 4165 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4166 {
4167 switch (i.op[op].imms->X_op)
252b5132 4168 {
29b0f896
AM		 4169 case O_constant:
4170 /* If a suffix is given, this operand may be shortened. */
4171 switch (guess_suffix)
252b5132 4172 {
29b0f896 4173 case LONG_MNEM_SUFFIX:
40fb9820
L		 4174 i.types[op].bitfield.imm32 = 1;
4175 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4176 break;
4177 case WORD_MNEM_SUFFIX:
40fb9820
L		 4178 i.types[op].bitfield.imm16 = 1;
4179 i.types[op].bitfield.imm32 = 1;
4180 i.types[op].bitfield.imm32s = 1;
4181 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4182 break;
4183 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4184 i.types[op].bitfield.imm8 = 1;
4185 i.types[op].bitfield.imm8s = 1;
4186 i.types[op].bitfield.imm16 = 1;
4187 i.types[op].bitfield.imm32 = 1;
4188 i.types[op].bitfield.imm32s = 1;
4189 i.types[op].bitfield.imm64 = 1;
29b0f896 4190 break;
252b5132 4191 }
252b5132 4192
29b0f896
AM		 4193 /* If this operand is at most 16 bits, convert it
4194 to a signed 16 bit number before trying to see
4195 whether it will fit in an even smaller size.
4196 This allows a 16-bit operand such as $0xffe0 to
4197 be recognised as within Imm8S range. */
40fb9820 4198 if ((i.types[op].bitfield.imm16)
29b0f896 4199 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4200 {
29b0f896
AM		 4201 i.op[op].imms->X_add_number =
4202 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4203 }
40fb9820 4204 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4205 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4206 == 0))
4207 {
4208 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4209 ^ ((offsetT) 1 << 31))
4210 - ((offsetT) 1 << 31));
4211 }
40fb9820 4212 i.types[op]
c6fb90c8
L		 4213 = operand_type_or (i.types[op],
4214 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4215
29b0f896
AM		 4216 /* We must avoid matching of Imm32 templates when 64bit
4217 only immediate is available. */
4218 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4219 i.types[op].bitfield.imm32 = 0;
29b0f896 4220 break;
252b5132 4221
29b0f896
AM		 4222 case O_absent:
4223 case O_register:
4224 abort ();
4225
4226 /* Symbols and expressions. */
4227 default:
9cd96992
JB		 4228 /* Convert symbolic operand to proper sizes for matching, but don't
4229 prevent matching a set of insns that only supports sizes other
4230 than those matching the insn suffix. */
4231 {
40fb9820 4232 i386_operand_type mask, allowed;
d3ce72d0 4233 const insn_template *t;
9cd96992 4234
0dfbf9d7
L		 4235 operand_type_set (&mask, 0);
4236 operand_type_set (&allowed, 0);
40fb9820 4237
4eed87de
AM		 4238 for (t = current_templates->start;
4239 t < current_templates->end;
4240 ++t)
c6fb90c8
L		 4241 allowed = operand_type_or (allowed,
4242 t->operand_types[op]);
9cd96992
JB		 4243 switch (guess_suffix)
4244 {
4245 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4246 mask.bitfield.imm64 = 1;
4247 mask.bitfield.imm32s = 1;
9cd96992
JB		 4248 break;
4249 case LONG_MNEM_SUFFIX:
40fb9820 4250 mask.bitfield.imm32 = 1;
9cd96992
JB		 4251 break;
4252 case WORD_MNEM_SUFFIX:
40fb9820 4253 mask.bitfield.imm16 = 1;
9cd96992
JB		 4254 break;
4255 case BYTE_MNEM_SUFFIX:
40fb9820 4256 mask.bitfield.imm8 = 1;
9cd96992
JB		 4257 break;
4258 default:
9cd96992
JB		 4259 break;
4260 }
c6fb90c8 4261 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4262 if (!operand_type_all_zero (&allowed))
c6fb90c8 4263 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4264 }
29b0f896 4265 break;
252b5132 4266 }
29b0f896
AM		 4267 }
4268}
47926f60 4269
29b0f896
AM		 4270/* Try to use the smallest displacement type too. */
4271static void
e3bb37b5 4272optimize_disp (void)
29b0f896
AM		 4273{
4274 int op;
3e73aa7c 4275
29b0f896 4276 for (op = i.operands; --op >= 0;)
40fb9820 4277 if (operand_type_check (i.types[op], disp))
252b5132 4278 {
b300c311 4279 if (i.op[op].disps->X_op == O_constant)
252b5132 4280 {
91d6fa6a 4281 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4282
40fb9820 4283 if (i.types[op].bitfield.disp16
91d6fa6a 4284 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4285 {
4286 /* If this operand is at most 16 bits, convert
4287 to a signed 16 bit number and don't use 64bit
4288 displacement. */
91d6fa6a 4289 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4290 i.types[op].bitfield.disp64 = 0;
b300c311 4291 }
40fb9820 4292 if (i.types[op].bitfield.disp32
91d6fa6a 4293 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4294 {
4295 /* If this operand is at most 32 bits, convert
4296 to a signed 32 bit number and don't use 64bit
4297 displacement. */
91d6fa6a
NC		 4298 op_disp &= (((offsetT) 2 << 31) - 1);
4299 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4300 i.types[op].bitfield.disp64 = 0;
b300c311 4301 }
91d6fa6a 4302 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4303 {
40fb9820
L		 4304 i.types[op].bitfield.disp8 = 0;
4305 i.types[op].bitfield.disp16 = 0;
4306 i.types[op].bitfield.disp32 = 0;
4307 i.types[op].bitfield.disp32s = 0;
4308 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4309 i.op[op].disps = 0;
4310 i.disp_operands--;
4311 }
4312 else if (flag_code == CODE_64BIT)
4313 {
91d6fa6a 4314 if (fits_in_signed_long (op_disp))
28a9d8f5 4315 {
40fb9820
L		 4316 i.types[op].bitfield.disp64 = 0;
4317 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4318 }
0e1147d9 4319 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4320 && fits_in_unsigned_long (op_disp))
40fb9820 4321 i.types[op].bitfield.disp32 = 1;
b300c311 4322 }
40fb9820
L		 4323 if ((i.types[op].bitfield.disp32
4324 || i.types[op].bitfield.disp32s
4325 || i.types[op].bitfield.disp16)
91d6fa6a 4326 && fits_in_signed_byte (op_disp))
40fb9820 4327 i.types[op].bitfield.disp8 = 1;
252b5132 4328 }
67a4f2b7
AO		 4329 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4330 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4331 {
4332 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4333 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4334 i.types[op].bitfield.disp8 = 0;
4335 i.types[op].bitfield.disp16 = 0;
4336 i.types[op].bitfield.disp32 = 0;
4337 i.types[op].bitfield.disp32s = 0;
4338 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4339 }
4340 else
b300c311 4341 /* We only support 64bit displacement on constants. */
40fb9820 4342 i.types[op].bitfield.disp64 = 0;
252b5132 4343 }
29b0f896
AM		 4344}
4345
6c30d220
L		 4346/* Check if operands are valid for the instruction. */
4347
4348static int
4349check_VecOperands (const insn_template *t)
4350{
43234a1e
L		 4351 unsigned int op;
4352
6c30d220
L		 4353 /* Without VSIB byte, we can't have a vector register for index. */
4354 if (!t->opcode_modifier.vecsib
4355 && i.index_reg
4356 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4357 || i.index_reg->reg_type.bitfield.regymm
4358 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4359 {
4360 i.error = unsupported_vector_index_register;
4361 return 1;
4362 }
4363
ad8ecc81
MZ		 4364 /* Check if default mask is allowed. */
4365 if (t->opcode_modifier.nodefmask
4366 && (!i.mask || i.mask->mask->reg_num == 0))
4367 {
4368 i.error = no_default_mask;
4369 return 1;
4370 }
4371
7bab8ab5
JB		 4372 /* For VSIB byte, we need a vector register for index, and all vector
4373 registers must be distinct. */
4374 if (t->opcode_modifier.vecsib)
4375 {
4376 if (!i.index_reg
6c30d220
L		 4377 || !((t->opcode_modifier.vecsib == VecSIB128
4378 && i.index_reg->reg_type.bitfield.regxmm)
4379 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4380 && i.index_reg->reg_type.bitfield.regymm)
4381 || (t->opcode_modifier.vecsib == VecSIB512
4382 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4383 {
4384 i.error = invalid_vsib_address;
4385 return 1;
4386 }
4387
43234a1e
L		 4388 gas_assert (i.reg_operands == 2 || i.mask);
4389 if (i.reg_operands == 2 && !i.mask)
4390 {
4391 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4392 || i.types[0].bitfield.regymm);
43234a1e 4393 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4394 || i.types[2].bitfield.regymm);
43234a1e
L		 4395 if (operand_check == check_none)
4396 return 0;
4397 if (register_number (i.op[0].regs)
4398 != register_number (i.index_reg)
4399 && register_number (i.op[2].regs)
4400 != register_number (i.index_reg)
4401 && register_number (i.op[0].regs)
4402 != register_number (i.op[2].regs))
4403 return 0;
4404 if (operand_check == check_error)
4405 {
4406 i.error = invalid_vector_register_set;
4407 return 1;
4408 }
4409 as_warn (_("mask, index, and destination registers should be distinct"));
4410 }
8444f82a
MZ		 4411 else if (i.reg_operands == 1 && i.mask)
4412 {
4413 if ((i.types[1].bitfield.regymm
4414 || i.types[1].bitfield.regzmm)
4415 && (register_number (i.op[1].regs)
4416 == register_number (i.index_reg)))
4417 {
4418 if (operand_check == check_error)
4419 {
4420 i.error = invalid_vector_register_set;
4421 return 1;
4422 }
4423 if (operand_check != check_none)
4424 as_warn (_("index and destination registers should be distinct"));
4425 }
4426 }
43234a1e 4427 }
7bab8ab5 4428
43234a1e
L		 4429 /* Check if broadcast is supported by the instruction and is applied
4430 to the memory operand. */
4431 if (i.broadcast)
4432 {
4433 int broadcasted_opnd_size;
4434
4435 /* Check if specified broadcast is supported in this instruction,
4436 and it's applied to memory operand of DWORD or QWORD type,
4437 depending on VecESize. */
4438 if (i.broadcast->type != t->opcode_modifier.broadcast
4439 || !i.types[i.broadcast->operand].bitfield.mem
4440 || (t->opcode_modifier.vecesize == 0
4441 && !i.types[i.broadcast->operand].bitfield.dword
4442 && !i.types[i.broadcast->operand].bitfield.unspecified)
4443 || (t->opcode_modifier.vecesize == 1
4444 && !i.types[i.broadcast->operand].bitfield.qword
4445 && !i.types[i.broadcast->operand].bitfield.unspecified))
4446 goto bad_broadcast;
4447
4448 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4449 if (i.broadcast->type == BROADCAST_1TO16)
4450 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4451 else if (i.broadcast->type == BROADCAST_1TO8)
4452 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
4453 else
4454 goto bad_broadcast;
4455
4456 if ((broadcasted_opnd_size == 256
4457 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4458 || (broadcasted_opnd_size == 512
4459 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4460 {
4461 bad_broadcast:
4462 i.error = unsupported_broadcast;
4463 return 1;
4464 }
4465 }
4466 /* If broadcast is supported in this instruction, we need to check if
4467 operand of one-element size isn't specified without broadcast. */
4468 else if (t->opcode_modifier.broadcast && i.mem_operands)
4469 {
4470 /* Find memory operand. */
4471 for (op = 0; op < i.operands; op++)
4472 if (operand_type_check (i.types[op], anymem))
4473 break;
4474 gas_assert (op < i.operands);
4475 /* Check size of the memory operand. */
4476 if ((t->opcode_modifier.vecesize == 0
4477 && i.types[op].bitfield.dword)
4478 || (t->opcode_modifier.vecesize == 1
4479 && i.types[op].bitfield.qword))
4480 {
4481 i.error = broadcast_needed;
4482 return 1;
4483 }
4484 }
4485
4486 /* Check if requested masking is supported. */
4487 if (i.mask
4488 && (!t->opcode_modifier.masking
4489 || (i.mask->zeroing
4490 && t->opcode_modifier.masking == MERGING_MASKING)))
4491 {
4492 i.error = unsupported_masking;
4493 return 1;
4494 }
4495
4496 /* Check if masking is applied to dest operand. */
4497 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4498 {
4499 i.error = mask_not_on_destination;
4500 return 1;
4501 }
4502
43234a1e
L		 4503 /* Check RC/SAE. */
4504 if (i.rounding)
4505 {
4506 if ((i.rounding->type != saeonly
4507 && !t->opcode_modifier.staticrounding)
4508 || (i.rounding->type == saeonly
4509 && (t->opcode_modifier.staticrounding
4510 || !t->opcode_modifier.sae)))
4511 {
4512 i.error = unsupported_rc_sae;
4513 return 1;
4514 }
4515 /* If the instruction has several immediate operands and one of
4516 them is rounding, the rounding operand should be the last
4517 immediate operand. */
4518 if (i.imm_operands > 1
4519 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4520 {
43234a1e 4521 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4522 return 1;
4523 }
6c30d220
L		 4524 }
4525
43234a1e
L		 4526 /* Check vector Disp8 operand. */
4527 if (t->opcode_modifier.disp8memshift)
4528 {
4529 if (i.broadcast)
4530 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4531 else
4532 i.memshift = t->opcode_modifier.disp8memshift;
4533
4534 for (op = 0; op < i.operands; op++)
4535 if (operand_type_check (i.types[op], disp)
4536 && i.op[op].disps->X_op == O_constant)
4537 {
4538 offsetT value = i.op[op].disps->X_add_number;
4539 int vec_disp8_ok = fits_in_vec_disp8 (value);
4540 if (t->operand_types [op].bitfield.vec_disp8)
4541 {
4542 if (vec_disp8_ok)
4543 i.types[op].bitfield.vec_disp8 = 1;
4544 else
4545 {
4546 /* Vector insn can only have Vec_Disp8/Disp32 in
4547 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4548 mode. */
4549 i.types[op].bitfield.disp8 = 0;
4550 if (flag_code != CODE_16BIT)
4551 i.types[op].bitfield.disp16 = 0;
4552 }
4553 }
4554 else if (flag_code != CODE_16BIT)
4555 {
4556 /* One form of this instruction supports vector Disp8.
4557 Try vector Disp8 if we need to use Disp32. */
4558 if (vec_disp8_ok && !fits_in_signed_byte (value))
4559 {
4560 i.error = try_vector_disp8;
4561 return 1;
4562 }
4563 }
4564 }
4565 }
4566 else
4567 i.memshift = -1;
4568
6c30d220
L		 4569 return 0;
4570}
4571
43f3e2ee 4572/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4573 operand types. */
4574
4575static int
4576VEX_check_operands (const insn_template *t)
4577{
43234a1e
L		 4578 /* VREX is only valid with EVEX prefix. */
4579 if (i.need_vrex && !t->opcode_modifier.evex)
4580 {
4581 i.error = invalid_register_operand;
4582 return 1;
4583 }
4584
a683cc34
SP		 4585 if (!t->opcode_modifier.vex)
4586 return 0;
4587
4588 /* Only check VEX_Imm4, which must be the first operand. */
4589 if (t->operand_types[0].bitfield.vec_imm4)
4590 {
4591 if (i.op[0].imms->X_op != O_constant
4592 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4593 {
a65babc9 4594 i.error = bad_imm4;
891edac4
L		 4595 return 1;
4596 }
a683cc34
SP		 4597
4598 /* Turn off Imm8 so that update_imm won't complain. */
4599 i.types[0] = vec_imm4;
4600 }
4601
4602 return 0;
4603}
4604
d3ce72d0 4605static const insn_template *
e3bb37b5 4606match_template (void)
29b0f896
AM		 4607{
4608 /* Points to template once we've found it. */
d3ce72d0 4609 const insn_template *t;
40fb9820 4610 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4611 i386_operand_type overlap4;
29b0f896 4612 unsigned int found_reverse_match;
40fb9820
L		 4613 i386_opcode_modifier suffix_check;
4614 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4615 int addr_prefix_disp;
a5c311ca 4616 unsigned int j;
3629bb00 4617 unsigned int found_cpu_match;
45664ddb 4618 unsigned int check_register;
5614d22c 4619 enum i386_error specific_error = 0;
29b0f896 4620
c0f3af97
L		 4621#if MAX_OPERANDS != 5
4622# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4623#endif
4624
29b0f896 4625 found_reverse_match = 0;
539e75ad 4626 addr_prefix_disp = -1;
40fb9820
L		 4627
4628 memset (&suffix_check, 0, sizeof (suffix_check));
4629 if (i.suffix == BYTE_MNEM_SUFFIX)
4630 suffix_check.no_bsuf = 1;
4631 else if (i.suffix == WORD_MNEM_SUFFIX)
4632 suffix_check.no_wsuf = 1;
4633 else if (i.suffix == SHORT_MNEM_SUFFIX)
4634 suffix_check.no_ssuf = 1;
4635 else if (i.suffix == LONG_MNEM_SUFFIX)
4636 suffix_check.no_lsuf = 1;
4637 else if (i.suffix == QWORD_MNEM_SUFFIX)
4638 suffix_check.no_qsuf = 1;
4639 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4640 suffix_check.no_ldsuf = 1;
29b0f896 4641
01559ecc
L		 4642 /* Must have right number of operands. */
4643 i.error = number_of_operands_mismatch;
4644
45aa61fe 4645 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4646 {
539e75ad
L		 4647 addr_prefix_disp = -1;
4648
29b0f896
AM		 4649 if (i.operands != t->operands)
4650 continue;
4651
50aecf8c 4652 /* Check processor support. */
a65babc9 4653 i.error = unsupported;
c0f3af97
L		 4654 found_cpu_match = (cpu_flags_match (t)
4655 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4656 if (!found_cpu_match)
4657 continue;
4658
e1d4d893 4659 /* Check old gcc support. */
a65babc9 4660 i.error = old_gcc_only;
e1d4d893
L		 4661 if (!old_gcc && t->opcode_modifier.oldgcc)
4662 continue;
4663
4664 /* Check AT&T mnemonic. */
a65babc9 4665 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4666 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4667 continue;
4668
891edac4 4669 /* Check AT&T/Intel syntax. */
a65babc9 4670 i.error = unsupported_syntax;
5c07affc
L		 4671 if ((intel_syntax && t->opcode_modifier.attsyntax)
4672 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4673 continue;
4674
20592a94 4675 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4676 i.error = invalid_instruction_suffix;
567e4e96
L		 4677 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4678 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4679 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4680 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4681 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4682 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4683 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4684 continue;
4685
5c07affc 4686 if (!operand_size_match (t))
7d5e4556 4687 continue;
539e75ad 4688
5c07affc
L		 4689 for (j = 0; j < MAX_OPERANDS; j++)
4690 operand_types[j] = t->operand_types[j];
4691
45aa61fe
AM		 4692 /* In general, don't allow 64-bit operands in 32-bit mode. */
4693 if (i.suffix == QWORD_MNEM_SUFFIX
4694 && flag_code != CODE_64BIT
4695 && (intel_syntax
40fb9820 4696 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4697 && !intel_float_operand (t->name))
4698 : intel_float_operand (t->name) != 2)
40fb9820 4699 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4700 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4701 && !operand_types[0].bitfield.regymm
4702 && !operand_types[0].bitfield.regzmm)
40fb9820 4703 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97 4704 && !!operand_types[t->operands > 1].bitfield.regxmm
43234a1e
L		 4705 && !!operand_types[t->operands > 1].bitfield.regymm
4706 && !!operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4707 && (t->base_opcode != 0x0fc7
4708 || t->extension_opcode != 1 /* cmpxchg8b */))
4709 continue;
4710
192dc9c6
JB		 4711 /* In general, don't allow 32-bit operands on pre-386. */
4712 else if (i.suffix == LONG_MNEM_SUFFIX
4713 && !cpu_arch_flags.bitfield.cpui386
4714 && (intel_syntax
4715 ? (!t->opcode_modifier.ignoresize
4716 && !intel_float_operand (t->name))
4717 : intel_float_operand (t->name) != 2)
4718 && ((!operand_types[0].bitfield.regmmx
4719 && !operand_types[0].bitfield.regxmm)
4720 || (!operand_types[t->operands > 1].bitfield.regmmx
4721 && !!operand_types[t->operands > 1].bitfield.regxmm)))
4722 continue;
4723
29b0f896 4724 /* Do not verify operands when there are none. */
50aecf8c 4725 else
29b0f896 4726 {
c6fb90c8 4727 if (!t->operands)
2dbab7d5
L		 4728 /* We've found a match; break out of loop. */
4729 break;
29b0f896 4730 }
252b5132 4731
539e75ad
L		 4732 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4733 into Disp32/Disp16/Disp32 operand. */
4734 if (i.prefix[ADDR_PREFIX] != 0)
4735 {
40fb9820 4736 /* There should be only one Disp operand. */
539e75ad
L		 4737 switch (flag_code)
4738 {
4739 case CODE_16BIT:
40fb9820
L		 4740 for (j = 0; j < MAX_OPERANDS; j++)
4741 {
4742 if (operand_types[j].bitfield.disp16)
4743 {
4744 addr_prefix_disp = j;
4745 operand_types[j].bitfield.disp32 = 1;
4746 operand_types[j].bitfield.disp16 = 0;
4747 break;
4748 }
4749 }
539e75ad
L		 4750 break;
4751 case CODE_32BIT:
40fb9820
L		 4752 for (j = 0; j < MAX_OPERANDS; j++)
4753 {
4754 if (operand_types[j].bitfield.disp32)
4755 {
4756 addr_prefix_disp = j;
4757 operand_types[j].bitfield.disp32 = 0;
4758 operand_types[j].bitfield.disp16 = 1;
4759 break;
4760 }
4761 }
539e75ad
L		 4762 break;
4763 case CODE_64BIT:
40fb9820
L		 4764 for (j = 0; j < MAX_OPERANDS; j++)
4765 {
4766 if (operand_types[j].bitfield.disp64)
4767 {
4768 addr_prefix_disp = j;
4769 operand_types[j].bitfield.disp64 = 0;
4770 operand_types[j].bitfield.disp32 = 1;
4771 break;
4772 }
4773 }
539e75ad
L		 4774 break;
4775 }
539e75ad
L		 4776 }
4777
56ffb741
L		 4778 /* We check register size if needed. */
4779 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4780 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4781 switch (t->operands)
4782 {
4783 case 1:
40fb9820 4784 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4785 continue;
4786 break;
4787 case 2:
8b38ad71
L		 4788 /* xchg %eax, %eax is a special case. It is an aliase for nop
4789 only in 32bit mode and we can use opcode 0x90. In 64bit
4790 mode, we can't use 0x90 for xchg %eax, %eax since it should
4791 zero-extend %eax to %rax. */
4792 if (flag_code == CODE_64BIT
4793 && t->base_opcode == 0x90
0dfbf9d7
L		 4794 && operand_type_equal (&i.types [0], &acc32)
4795 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4796 continue;
b6169b20
L		 4797 if (i.swap_operand)
4798 {
4799 /* If we swap operand in encoding, we either match
4800 the next one or reverse direction of operands. */
4801 if (t->opcode_modifier.s)
4802 continue;
4803 else if (t->opcode_modifier.d)
4804 goto check_reverse;
4805 }
4806
29b0f896 4807 case 3:
fa99fab2
L		 4808 /* If we swap operand in encoding, we match the next one. */
4809 if (i.swap_operand && t->opcode_modifier.s)
4810 continue;
f48ff2ae 4811 case 4:
c0f3af97 4812 case 5:
c6fb90c8 4813 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4814 if (!operand_type_match (overlap0, i.types[0])
4815 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4816 || (check_register
4817 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4818 operand_types[0],
4819 overlap1, i.types[1],
4820 operand_types[1])))
29b0f896
AM		 4821 {
4822 /* Check if other direction is valid ... */
40fb9820 4823 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4824 continue;
4825
b6169b20 4826check_reverse:
29b0f896 4827 /* Try reversing direction of operands. */
c6fb90c8
L		 4828 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4829 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4830 if (!operand_type_match (overlap0, i.types[0])
4831 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4832 || (check_register
4833 && !operand_type_register_match (overlap0,
4834 i.types[0],
4835 operand_types[1],
4836 overlap1,
4837 i.types[1],
4838 operand_types[0])))
29b0f896
AM		 4839 {
4840 /* Does not match either direction. */
4841 continue;
4842 }
4843 /* found_reverse_match holds which of D or FloatDR
4844 we've found. */
40fb9820 4845 if (t->opcode_modifier.d)
8a2ed489 4846 found_reverse_match = Opcode_D;
40fb9820 4847 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4848 found_reverse_match = Opcode_FloatD;
4849 else
4850 found_reverse_match = 0;
40fb9820 4851 if (t->opcode_modifier.floatr)
8a2ed489 4852 found_reverse_match |= Opcode_FloatR;
29b0f896 4853 }
f48ff2ae 4854 else
29b0f896 4855 {
f48ff2ae 4856 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4857 switch (t->operands)
4858 {
c0f3af97
L		 4859 case 5:
4860 overlap4 = operand_type_and (i.types[4],
4861 operand_types[4]);
d1cbb4db 4862 case 4:
c6fb90c8
L		 4863 overlap3 = operand_type_and (i.types[3],
4864 operand_types[3]);
d1cbb4db 4865 case 3:
c6fb90c8
L		 4866 overlap2 = operand_type_and (i.types[2],
4867 operand_types[2]);
d1cbb4db
L		 4868 break;
4869 }
29b0f896 4870
f48ff2ae
L		 4871 switch (t->operands)
4872 {
c0f3af97
L		 4873 case 5:
4874 if (!operand_type_match (overlap4, i.types[4])
4875 || !operand_type_register_match (overlap3,
4876 i.types[3],
4877 operand_types[3],
4878 overlap4,
4879 i.types[4],
4880 operand_types[4]))
4881 continue;
f48ff2ae 4882 case 4:
40fb9820 4883 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4884 || (check_register
4885 && !operand_type_register_match (overlap2,
4886 i.types[2],
4887 operand_types[2],
4888 overlap3,
4889 i.types[3],
4890 operand_types[3])))
f48ff2ae
L		 4891 continue;
4892 case 3:
4893 /* Here we make use of the fact that there are no
4894 reverse match 3 operand instructions, and all 3
4895 operand instructions only need to be checked for
4896 register consistency between operands 2 and 3. */
40fb9820 4897 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4898 || (check_register
4899 && !operand_type_register_match (overlap1,
4900 i.types[1],
4901 operand_types[1],
4902 overlap2,
4903 i.types[2],
4904 operand_types[2])))
f48ff2ae
L		 4905 continue;
4906 break;
4907 }
29b0f896 4908 }
f48ff2ae 4909 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4910 slip through to break. */
4911 }
3629bb00 4912 if (!found_cpu_match)
29b0f896
AM		 4913 {
4914 found_reverse_match = 0;
4915 continue;
4916 }
c0f3af97 4917
5614d22c
JB		 4918 /* Check if vector and VEX operands are valid. */
4919 if (check_VecOperands (t) || VEX_check_operands (t))
4920 {
4921 specific_error = i.error;
4922 continue;
4923 }
a683cc34 4924
29b0f896
AM		 4925 /* We've found a match; break out of loop. */
4926 break;
4927 }
4928
4929 if (t == current_templates->end)
4930 {
4931 /* We found no match. */
a65babc9 4932 const char *err_msg;
5614d22c 4933 switch (specific_error ? specific_error : i.error)
a65babc9
L		 4934 {
4935 default:
4936 abort ();
86e026a4 4937 case operand_size_mismatch:
a65babc9
L		 4938 err_msg = _("operand size mismatch");
4939 break;
4940 case operand_type_mismatch:
4941 err_msg = _("operand type mismatch");
4942 break;
4943 case register_type_mismatch:
4944 err_msg = _("register type mismatch");
4945 break;
4946 case number_of_operands_mismatch:
4947 err_msg = _("number of operands mismatch");
4948 break;
4949 case invalid_instruction_suffix:
4950 err_msg = _("invalid instruction suffix");
4951 break;
4952 case bad_imm4:
4a2608e3 4953 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 4954 break;
4955 case old_gcc_only:
4956 err_msg = _("only supported with old gcc");
4957 break;
4958 case unsupported_with_intel_mnemonic:
4959 err_msg = _("unsupported with Intel mnemonic");
4960 break;
4961 case unsupported_syntax:
4962 err_msg = _("unsupported syntax");
4963 break;
4964 case unsupported:
35262a23 4965 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 4966 current_templates->start->name);
4967 return NULL;
6c30d220
L		 4968 case invalid_vsib_address:
4969 err_msg = _("invalid VSIB address");
4970 break;
7bab8ab5
JB		 4971 case invalid_vector_register_set:
4972 err_msg = _("mask, index, and destination registers must be distinct");
4973 break;
6c30d220
L		 4974 case unsupported_vector_index_register:
4975 err_msg = _("unsupported vector index register");
4976 break;
43234a1e
L		 4977 case unsupported_broadcast:
4978 err_msg = _("unsupported broadcast");
4979 break;
4980 case broadcast_not_on_src_operand:
4981 err_msg = _("broadcast not on source memory operand");
4982 break;
4983 case broadcast_needed:
4984 err_msg = _("broadcast is needed for operand of such type");
4985 break;
4986 case unsupported_masking:
4987 err_msg = _("unsupported masking");
4988 break;
4989 case mask_not_on_destination:
4990 err_msg = _("mask not on destination operand");
4991 break;
4992 case no_default_mask:
4993 err_msg = _("default mask isn't allowed");
4994 break;
4995 case unsupported_rc_sae:
4996 err_msg = _("unsupported static rounding/sae");
4997 break;
4998 case rc_sae_operand_not_last_imm:
4999 if (intel_syntax)
5000 err_msg = _("RC/SAE operand must precede immediate operands");
5001 else
5002 err_msg = _("RC/SAE operand must follow immediate operands");
5003 break;
5004 case invalid_register_operand:
5005 err_msg = _("invalid register operand");
5006 break;
a65babc9
L		 5007 }
5008 as_bad (_("%s for `%s'"), err_msg,
891edac4 5009 current_templates->start->name);
fa99fab2 5010 return NULL;
29b0f896 5011 }
252b5132 5012
29b0f896
AM		 5013 if (!quiet_warnings)
5014 {
5015 if (!intel_syntax
40fb9820
L		 5016 && (i.types[0].bitfield.jumpabsolute
5017 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5018 {
5019 as_warn (_("indirect %s without `*'"), t->name);
5020 }
5021
40fb9820
L		 5022 if (t->opcode_modifier.isprefix
5023 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5024 {
5025 /* Warn them that a data or address size prefix doesn't
5026 affect assembly of the next line of code. */
5027 as_warn (_("stand-alone `%s' prefix"), t->name);
5028 }
5029 }
5030
5031 /* Copy the template we found. */
5032 i.tm = *t;
539e75ad
L		 5033
5034 if (addr_prefix_disp != -1)
5035 i.tm.operand_types[addr_prefix_disp]
5036 = operand_types[addr_prefix_disp];
5037
29b0f896
AM		 5038 if (found_reverse_match)
5039 {
5040 /* If we found a reverse match we must alter the opcode
5041 direction bit. found_reverse_match holds bits to change
5042 (different for int & float insns). */
5043
5044 i.tm.base_opcode ^= found_reverse_match;
5045
539e75ad
L		 5046 i.tm.operand_types[0] = operand_types[1];
5047 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5048 }
5049
fa99fab2 5050 return t;
29b0f896
AM		 5051}
5052
5053static int
e3bb37b5 5054check_string (void)
29b0f896 5055{
40fb9820
L		 5056 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5057 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5058 {
5059 if (i.seg[0] != NULL && i.seg[0] != &es)
5060 {
a87af027 5061 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5062 i.tm.name,
a87af027
JB		 5063 mem_op + 1,
5064 register_prefix);
29b0f896
AM		 5065 return 0;
5066 }
5067 /* There's only ever one segment override allowed per instruction.
5068 This instruction possibly has a legal segment override on the
5069 second operand, so copy the segment to where non-string
5070 instructions store it, allowing common code. */
5071 i.seg[0] = i.seg[1];
5072 }
40fb9820 5073 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5074 {
5075 if (i.seg[1] != NULL && i.seg[1] != &es)
5076 {
a87af027 5077 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5078 i.tm.name,
a87af027
JB		 5079 mem_op + 2,
5080 register_prefix);
29b0f896
AM		 5081 return 0;
5082 }
5083 }
5084 return 1;
5085}
5086
5087static int
543613e9 5088process_suffix (void)
29b0f896
AM		 5089{
5090 /* If matched instruction specifies an explicit instruction mnemonic
5091 suffix, use it. */
40fb9820
L		 5092 if (i.tm.opcode_modifier.size16)
5093 i.suffix = WORD_MNEM_SUFFIX;
5094 else if (i.tm.opcode_modifier.size32)
5095 i.suffix = LONG_MNEM_SUFFIX;
5096 else if (i.tm.opcode_modifier.size64)
5097 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5098 else if (i.reg_operands)
5099 {
5100 /* If there's no instruction mnemonic suffix we try to invent one
5101 based on register operands. */
5102 if (!i.suffix)
5103 {
5104 /* We take i.suffix from the last register operand specified,
5105 Destination register type is more significant than source
381d071f
L		 5106 register type. crc32 in SSE4.2 prefers source register
5107 type. */
5108 if (i.tm.base_opcode == 0xf20f38f1)
5109 {
40fb9820
L		 5110 if (i.types[0].bitfield.reg16)
5111 i.suffix = WORD_MNEM_SUFFIX;
5112 else if (i.types[0].bitfield.reg32)
5113 i.suffix = LONG_MNEM_SUFFIX;
5114 else if (i.types[0].bitfield.reg64)
5115 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5116 }
9344ff29 5117 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5118 {
40fb9820 5119 if (i.types[0].bitfield.reg8)
20592a94
L		 5120 i.suffix = BYTE_MNEM_SUFFIX;
5121 }
381d071f
L		 5122
5123 if (!i.suffix)
5124 {
5125 int op;
5126
20592a94
L		 5127 if (i.tm.base_opcode == 0xf20f38f1
5128 || i.tm.base_opcode == 0xf20f38f0)
5129 {
5130 /* We have to know the operand size for crc32. */
5131 as_bad (_("ambiguous memory operand size for `%s`"),
5132 i.tm.name);
5133 return 0;
5134 }
5135
381d071f 5136 for (op = i.operands; --op >= 0;)
40fb9820 5137 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5138 {
40fb9820
L		 5139 if (i.types[op].bitfield.reg8)
5140 {
5141 i.suffix = BYTE_MNEM_SUFFIX;
5142 break;
5143 }
5144 else if (i.types[op].bitfield.reg16)
5145 {
5146 i.suffix = WORD_MNEM_SUFFIX;
5147 break;
5148 }
5149 else if (i.types[op].bitfield.reg32)
5150 {
5151 i.suffix = LONG_MNEM_SUFFIX;
5152 break;
5153 }
5154 else if (i.types[op].bitfield.reg64)
5155 {
5156 i.suffix = QWORD_MNEM_SUFFIX;
5157 break;
5158 }
381d071f
L		 5159 }
5160 }
29b0f896
AM		 5161 }
5162 else if (i.suffix == BYTE_MNEM_SUFFIX)
5163 {
2eb952a4
L		 5164 if (intel_syntax
5165 && i.tm.opcode_modifier.ignoresize
5166 && i.tm.opcode_modifier.no_bsuf)
5167 i.suffix = 0;
5168 else if (!check_byte_reg ())
29b0f896
AM		 5169 return 0;
5170 }
5171 else if (i.suffix == LONG_MNEM_SUFFIX)
5172 {
2eb952a4
L		 5173 if (intel_syntax
5174 && i.tm.opcode_modifier.ignoresize
5175 && i.tm.opcode_modifier.no_lsuf)
5176 i.suffix = 0;
5177 else if (!check_long_reg ())
29b0f896
AM		 5178 return 0;
5179 }
5180 else if (i.suffix == QWORD_MNEM_SUFFIX)
5181 {
955e1e6a
L		 5182 if (intel_syntax
5183 && i.tm.opcode_modifier.ignoresize
5184 && i.tm.opcode_modifier.no_qsuf)
5185 i.suffix = 0;
5186 else if (!check_qword_reg ())
29b0f896
AM		 5187 return 0;
5188 }
5189 else if (i.suffix == WORD_MNEM_SUFFIX)
5190 {
2eb952a4
L		 5191 if (intel_syntax
5192 && i.tm.opcode_modifier.ignoresize
5193 && i.tm.opcode_modifier.no_wsuf)
5194 i.suffix = 0;
5195 else if (!check_word_reg ())
29b0f896
AM		 5196 return 0;
5197 }
c0f3af97 5198 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5199 || i.suffix == YMMWORD_MNEM_SUFFIX
5200 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5201 {
43234a1e 5202 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5203 should check if it is a valid suffix. */
5204 }
40fb9820 5205 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5206 /* Do nothing if the instruction is going to ignore the prefix. */
5207 ;
5208 else
5209 abort ();
5210 }
40fb9820 5211 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5212 && !i.suffix
5213 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5214 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5215 {
5216 i.suffix = stackop_size;
5217 }
9306ca4a
JB		 5218 else if (intel_syntax
5219 && !i.suffix
40fb9820
L		 5220 && (i.tm.operand_types[0].bitfield.jumpabsolute
5221 || i.tm.opcode_modifier.jumpbyte
5222 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5223 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5224 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5225 {
5226 switch (flag_code)
5227 {
5228 case CODE_64BIT:
40fb9820 5229 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5230 {
5231 i.suffix = QWORD_MNEM_SUFFIX;
5232 break;
5233 }
5234 case CODE_32BIT:
40fb9820 5235 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5236 i.suffix = LONG_MNEM_SUFFIX;
5237 break;
5238 case CODE_16BIT:
40fb9820 5239 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5240 i.suffix = WORD_MNEM_SUFFIX;
5241 break;
5242 }
5243 }
252b5132 5244
9306ca4a 5245 if (!i.suffix)
29b0f896 5246 {
9306ca4a
JB		 5247 if (!intel_syntax)
5248 {
40fb9820 5249 if (i.tm.opcode_modifier.w)
9306ca4a 5250 {
4eed87de
AM		 5251 as_bad (_("no instruction mnemonic suffix given and "
5252 "no register operands; can't size instruction"));
9306ca4a
JB		 5253 return 0;
5254 }
5255 }
5256 else
5257 {
40fb9820 5258 unsigned int suffixes;
7ab9ffdd 5259
40fb9820
L		 5260 suffixes = !i.tm.opcode_modifier.no_bsuf;
5261 if (!i.tm.opcode_modifier.no_wsuf)
5262 suffixes |= 1 << 1;
5263 if (!i.tm.opcode_modifier.no_lsuf)
5264 suffixes |= 1 << 2;
fc4adea1 5265 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5266 suffixes |= 1 << 3;
5267 if (!i.tm.opcode_modifier.no_ssuf)
5268 suffixes |= 1 << 4;
5269 if (!i.tm.opcode_modifier.no_qsuf)
5270 suffixes |= 1 << 5;
5271
5272 /* There are more than suffix matches. */
5273 if (i.tm.opcode_modifier.w
9306ca4a 5274 || ((suffixes & (suffixes - 1))
40fb9820
L		 5275 && !i.tm.opcode_modifier.defaultsize
5276 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5277 {
5278 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5279 return 0;
5280 }
5281 }
29b0f896 5282 }
252b5132 5283
9306ca4a
JB		 5284 /* Change the opcode based on the operand size given by i.suffix;
5285 We don't need to change things for byte insns. */
5286
582d5edd
L		 5287 if (i.suffix
5288 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5289 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5290 && i.suffix != YMMWORD_MNEM_SUFFIX
5291 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5292 {
5293 /* It's not a byte, select word/dword operation. */
40fb9820 5294 if (i.tm.opcode_modifier.w)
29b0f896 5295 {
40fb9820 5296 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5297 i.tm.base_opcode |= 8;
5298 else
5299 i.tm.base_opcode |= 1;
5300 }
0f3f3d8b 5301
29b0f896
AM		 5302 /* Now select between word & dword operations via the operand
5303 size prefix, except for instructions that will ignore this
5304 prefix anyway. */
ca61edf2 5305 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5306 {
ca61edf2
L		 5307 /* The address size override prefix changes the size of the
5308 first operand. */
40fb9820
L		 5309 if ((flag_code == CODE_32BIT
5310 && i.op->regs[0].reg_type.bitfield.reg16)
5311 || (flag_code != CODE_32BIT
5312 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5313 if (!add_prefix (ADDR_PREFIX_OPCODE))
5314 return 0;
5315 }
5316 else if (i.suffix != QWORD_MNEM_SUFFIX
5317 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5318 && !i.tm.opcode_modifier.ignoresize
5319 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5320 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5321 || (flag_code == CODE_64BIT
40fb9820 5322 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5323 {
5324 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5325
40fb9820 5326 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5327 prefix = ADDR_PREFIX_OPCODE;
252b5132 5328
29b0f896
AM		 5329 if (!add_prefix (prefix))
5330 return 0;
24eab124 5331 }
252b5132 5332
29b0f896
AM		 5333 /* Set mode64 for an operand. */
5334 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5335 && flag_code == CODE_64BIT
40fb9820 5336 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5337 {
5338 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5339 need rex64. cmpxchg8b is also a special case. */
5340 if (! (i.operands == 2
5341 && i.tm.base_opcode == 0x90
5342 && i.tm.extension_opcode == None
0dfbf9d7
L		 5343 && operand_type_equal (&i.types [0], &acc64)
5344 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5345 && ! (i.operands == 1
5346 && i.tm.base_opcode == 0xfc7
5347 && i.tm.extension_opcode == 1
40fb9820
L		 5348 && !operand_type_check (i.types [0], reg)
5349 && operand_type_check (i.types [0], anymem)))
f6bee062 5350 i.rex |= REX_W;
46e883c5 5351 }
3e73aa7c 5352
29b0f896
AM		 5353 /* Size floating point instruction. */
5354 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5355 if (i.tm.opcode_modifier.floatmf)
543613e9 5356 i.tm.base_opcode ^= 4;
29b0f896 5357 }
7ecd2f8b 5358
29b0f896
AM		 5359 return 1;
5360}
3e73aa7c 5361
29b0f896 5362static int
543613e9 5363check_byte_reg (void)
29b0f896
AM		 5364{
5365 int op;
543613e9 5366
29b0f896
AM		 5367 for (op = i.operands; --op >= 0;)
5368 {
5369 /* If this is an eight bit register, it's OK. If it's the 16 or
5370 32 bit version of an eight bit register, we will just use the
5371 low portion, and that's OK too. */
40fb9820 5372 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5373 continue;
5374
5a819eb9
JB		 5375 /* I/O port address operands are OK too. */
5376 if (i.tm.operand_types[op].bitfield.inoutportreg)
5377 continue;
5378
9344ff29
L		 5379 /* crc32 doesn't generate this warning. */
5380 if (i.tm.base_opcode == 0xf20f38f0)
5381 continue;
5382
40fb9820
L		 5383 if ((i.types[op].bitfield.reg16
5384 || i.types[op].bitfield.reg32
5385 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5386 && i.op[op].regs->reg_num < 4
5387 /* Prohibit these changes in 64bit mode, since the lowering
5388 would be more complicated. */
5389 && flag_code != CODE_64BIT)
29b0f896 5390 {
29b0f896 5391#if REGISTER_WARNINGS
5a819eb9 5392 if (!quiet_warnings)
a540244d
L		 5393 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5394 register_prefix,
40fb9820 5395 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5396 ? REGNAM_AL - REGNAM_AX
5397 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5398 register_prefix,
29b0f896
AM		 5399 i.op[op].regs->reg_name,
5400 i.suffix);
5401#endif
5402 continue;
5403 }
5404 /* Any other register is bad. */
40fb9820
L		 5405 if (i.types[op].bitfield.reg16
5406 || i.types[op].bitfield.reg32
5407 || i.types[op].bitfield.reg64
5408 || i.types[op].bitfield.regmmx
5409 || i.types[op].bitfield.regxmm
c0f3af97 5410 || i.types[op].bitfield.regymm
43234a1e 5411 || i.types[op].bitfield.regzmm
40fb9820
L		 5412 || i.types[op].bitfield.sreg2
5413 || i.types[op].bitfield.sreg3
5414 || i.types[op].bitfield.control
5415 || i.types[op].bitfield.debug
5416 || i.types[op].bitfield.test
5417 || i.types[op].bitfield.floatreg
5418 || i.types[op].bitfield.floatacc)
29b0f896 5419 {
a540244d
L		 5420 as_bad (_("`%s%s' not allowed with `%s%c'"),
5421 register_prefix,
29b0f896
AM		 5422 i.op[op].regs->reg_name,
5423 i.tm.name,
5424 i.suffix);
5425 return 0;
5426 }
5427 }
5428 return 1;
5429}
5430
5431static int
e3bb37b5 5432check_long_reg (void)
29b0f896
AM		 5433{
5434 int op;
5435
5436 for (op = i.operands; --op >= 0;)
5437 /* Reject eight bit registers, except where the template requires
5438 them. (eg. movzb) */
40fb9820
L		 5439 if (i.types[op].bitfield.reg8
5440 && (i.tm.operand_types[op].bitfield.reg16
5441 || i.tm.operand_types[op].bitfield.reg32
5442 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5443 {
a540244d
L		 5444 as_bad (_("`%s%s' not allowed with `%s%c'"),
5445 register_prefix,
29b0f896
AM		 5446 i.op[op].regs->reg_name,
5447 i.tm.name,
5448 i.suffix);
5449 return 0;
5450 }
e4630f71 5451 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5452 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5453 && i.types[op].bitfield.reg16
5454 && (i.tm.operand_types[op].bitfield.reg32
5455 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5456 {
5457 /* Prohibit these changes in the 64bit mode, since the
5458 lowering is more complicated. */
5459 if (flag_code == CODE_64BIT)
252b5132 5460 {
2b5d6a91 5461 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5462 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5463 i.suffix);
5464 return 0;
252b5132 5465 }
29b0f896 5466#if REGISTER_WARNINGS
cecf1424
JB		 5467 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5468 register_prefix,
5469 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5470 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5471#endif
252b5132 5472 }
e4630f71 5473 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5474 else if (i.types[op].bitfield.reg64
5475 && (i.tm.operand_types[op].bitfield.reg32
5476 || i.tm.operand_types[op].bitfield.acc))
252b5132 5477 {
34828aad 5478 if (intel_syntax
ca61edf2 5479 && i.tm.opcode_modifier.toqword
40fb9820 5480 && !i.types[0].bitfield.regxmm)
34828aad 5481 {
ca61edf2 5482 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5483 i.suffix = QWORD_MNEM_SUFFIX;
5484 }
5485 else
5486 {
2b5d6a91 5487 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5488 register_prefix, i.op[op].regs->reg_name,
5489 i.suffix);
5490 return 0;
5491 }
29b0f896
AM		 5492 }
5493 return 1;
5494}
252b5132 5495
29b0f896 5496static int
e3bb37b5 5497check_qword_reg (void)
29b0f896
AM		 5498{
5499 int op;
252b5132 5500
29b0f896
AM		 5501 for (op = i.operands; --op >= 0; )
5502 /* Reject eight bit registers, except where the template requires
5503 them. (eg. movzb) */
40fb9820
L		 5504 if (i.types[op].bitfield.reg8
5505 && (i.tm.operand_types[op].bitfield.reg16
5506 || i.tm.operand_types[op].bitfield.reg32
5507 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5508 {
a540244d
L		 5509 as_bad (_("`%s%s' not allowed with `%s%c'"),
5510 register_prefix,
29b0f896
AM		 5511 i.op[op].regs->reg_name,
5512 i.tm.name,
5513 i.suffix);
5514 return 0;
5515 }
e4630f71 5516 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5517 else if ((i.types[op].bitfield.reg16
5518 || i.types[op].bitfield.reg32)
5519 && (i.tm.operand_types[op].bitfield.reg32
5520 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5521 {
5522 /* Prohibit these changes in the 64bit mode, since the
5523 lowering is more complicated. */
34828aad 5524 if (intel_syntax
ca61edf2 5525 && i.tm.opcode_modifier.todword
40fb9820 5526 && !i.types[0].bitfield.regxmm)
34828aad 5527 {
ca61edf2 5528 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5529 i.suffix = LONG_MNEM_SUFFIX;
5530 }
5531 else
5532 {
2b5d6a91 5533 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5534 register_prefix, i.op[op].regs->reg_name,
5535 i.suffix);
5536 return 0;
5537 }
252b5132 5538 }
29b0f896
AM		 5539 return 1;
5540}
252b5132 5541
29b0f896 5542static int
e3bb37b5 5543check_word_reg (void)
29b0f896
AM		 5544{
5545 int op;
5546 for (op = i.operands; --op >= 0;)
5547 /* Reject eight bit registers, except where the template requires
5548 them. (eg. movzb) */
40fb9820
L		 5549 if (i.types[op].bitfield.reg8
5550 && (i.tm.operand_types[op].bitfield.reg16
5551 || i.tm.operand_types[op].bitfield.reg32
5552 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5553 {
a540244d
L		 5554 as_bad (_("`%s%s' not allowed with `%s%c'"),
5555 register_prefix,
29b0f896
AM		 5556 i.op[op].regs->reg_name,
5557 i.tm.name,
5558 i.suffix);
5559 return 0;
5560 }
e4630f71 5561 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5562 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5563 && (i.types[op].bitfield.reg32
5564 || i.types[op].bitfield.reg64)
40fb9820
L		 5565 && (i.tm.operand_types[op].bitfield.reg16
5566 || i.tm.operand_types[op].bitfield.acc))
252b5132 5567 {
29b0f896
AM		 5568 /* Prohibit these changes in the 64bit mode, since the
5569 lowering is more complicated. */
5570 if (flag_code == CODE_64BIT)
252b5132 5571 {
2b5d6a91 5572 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5573 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5574 i.suffix);
5575 return 0;
252b5132 5576 }
29b0f896 5577#if REGISTER_WARNINGS
cecf1424
JB		 5578 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5579 register_prefix,
5580 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5581 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5582#endif
5583 }
5584 return 1;
5585}
252b5132 5586
29b0f896 5587static int
40fb9820 5588update_imm (unsigned int j)
29b0f896 5589{
bc0844ae 5590 i386_operand_type overlap = i.types[j];
40fb9820
L		 5591 if ((overlap.bitfield.imm8
5592 || overlap.bitfield.imm8s
5593 || overlap.bitfield.imm16
5594 || overlap.bitfield.imm32
5595 || overlap.bitfield.imm32s
5596 || overlap.bitfield.imm64)
0dfbf9d7
L		 5597 && !operand_type_equal (&overlap, &imm8)
5598 && !operand_type_equal (&overlap, &imm8s)
5599 && !operand_type_equal (&overlap, &imm16)
5600 && !operand_type_equal (&overlap, &imm32)
5601 && !operand_type_equal (&overlap, &imm32s)
5602 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5603 {
5604 if (i.suffix)
5605 {
40fb9820
L		 5606 i386_operand_type temp;
5607
0dfbf9d7 5608 operand_type_set (&temp, 0);
7ab9ffdd 5609 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5610 {
5611 temp.bitfield.imm8 = overlap.bitfield.imm8;
5612 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5613 }
5614 else if (i.suffix == WORD_MNEM_SUFFIX)
5615 temp.bitfield.imm16 = overlap.bitfield.imm16;
5616 else if (i.suffix == QWORD_MNEM_SUFFIX)
5617 {
5618 temp.bitfield.imm64 = overlap.bitfield.imm64;
5619 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5620 }
5621 else
5622 temp.bitfield.imm32 = overlap.bitfield.imm32;
5623 overlap = temp;
29b0f896 5624 }
0dfbf9d7
L		 5625 else if (operand_type_equal (&overlap, &imm16_32_32s)
5626 || operand_type_equal (&overlap, &imm16_32)
5627 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5628 {
40fb9820 5629 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5630 overlap = imm16;
40fb9820 5631 else
65da13b5 5632 overlap = imm32s;
29b0f896 5633 }
0dfbf9d7
L		 5634 if (!operand_type_equal (&overlap, &imm8)
5635 && !operand_type_equal (&overlap, &imm8s)
5636 && !operand_type_equal (&overlap, &imm16)
5637 && !operand_type_equal (&overlap, &imm32)
5638 && !operand_type_equal (&overlap, &imm32s)
5639 && !operand_type_equal (&overlap, &imm64))
29b0f896 5640 {
4eed87de
AM		 5641 as_bad (_("no instruction mnemonic suffix given; "
5642 "can't determine immediate size"));
29b0f896
AM		 5643 return 0;
5644 }
5645 }
40fb9820 5646 i.types[j] = overlap;
29b0f896 5647
40fb9820
L		 5648 return 1;
5649}
5650
5651static int
5652finalize_imm (void)
5653{
bc0844ae 5654 unsigned int j, n;
29b0f896 5655
bc0844ae
L		 5656 /* Update the first 2 immediate operands. */
5657 n = i.operands > 2 ? 2 : i.operands;
5658 if (n)
5659 {
5660 for (j = 0; j < n; j++)
5661 if (update_imm (j) == 0)
5662 return 0;
40fb9820 5663
bc0844ae
L		 5664 /* The 3rd operand can't be immediate operand. */
5665 gas_assert (operand_type_check (i.types[2], imm) == 0);
5666 }
29b0f896
AM		 5667
5668 return 1;
5669}
5670
c0f3af97
L		 5671static int
5672bad_implicit_operand (int xmm)
5673{
91d6fa6a
NC		 5674 const char *ireg = xmm ? "xmm0" : "ymm0";
5675
c0f3af97
L		 5676 if (intel_syntax)
5677 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5678 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5679 else
5680 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5681 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5682 return 0;
5683}
5684
29b0f896 5685static int
e3bb37b5 5686process_operands (void)
29b0f896
AM		 5687{
5688 /* Default segment register this instruction will use for memory
5689 accesses. 0 means unknown. This is only for optimizing out
5690 unnecessary segment overrides. */
5691 const seg_entry *default_seg = 0;
5692
2426c15f 5693 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5694 {
91d6fa6a
NC		 5695 unsigned int dupl = i.operands;
5696 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5697 unsigned int j;
5698
c0f3af97 5699 /* The destination must be an xmm register. */
9c2799c2 5700 gas_assert (i.reg_operands
91d6fa6a 5701 && MAX_OPERANDS > dupl
7ab9ffdd 5702 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5703
5704 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5705 {
c0f3af97 5706 /* The first operand is implicit and must be xmm0. */
9c2799c2 5707 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5708 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5709 return bad_implicit_operand (1);
5710
8cd7925b 5711 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5712 {
5713 /* Keep xmm0 for instructions with VEX prefix and 3
5714 sources. */
5715 goto duplicate;
5716 }
e2ec9d29 5717 else
c0f3af97
L		 5718 {
5719 /* We remove the first xmm0 and keep the number of
5720 operands unchanged, which in fact duplicates the
5721 destination. */
5722 for (j = 1; j < i.operands; j++)
5723 {
5724 i.op[j - 1] = i.op[j];
5725 i.types[j - 1] = i.types[j];
5726 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5727 }
5728 }
5729 }
5730 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5731 {
91d6fa6a 5732 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5733 && (i.tm.opcode_modifier.vexsources
5734 == VEX3SOURCES));
c0f3af97
L		 5735
5736 /* Add the implicit xmm0 for instructions with VEX prefix
5737 and 3 sources. */
5738 for (j = i.operands; j > 0; j--)
5739 {
5740 i.op[j] = i.op[j - 1];
5741 i.types[j] = i.types[j - 1];
5742 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5743 }
5744 i.op[0].regs
5745 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5746 i.types[0] = regxmm;
c0f3af97
L		 5747 i.tm.operand_types[0] = regxmm;
5748
5749 i.operands += 2;
5750 i.reg_operands += 2;
5751 i.tm.operands += 2;
5752
91d6fa6a 5753 dupl++;
c0f3af97 5754 dest++;
91d6fa6a
NC		 5755 i.op[dupl] = i.op[dest];
5756 i.types[dupl] = i.types[dest];
5757 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5758 }
c0f3af97
L		 5759 else
5760 {
5761duplicate:
5762 i.operands++;
5763 i.reg_operands++;
5764 i.tm.operands++;
5765
91d6fa6a
NC		 5766 i.op[dupl] = i.op[dest];
5767 i.types[dupl] = i.types[dest];
5768 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5769 }
5770
5771 if (i.tm.opcode_modifier.immext)
5772 process_immext ();
5773 }
5774 else if (i.tm.opcode_modifier.firstxmm0)
5775 {
5776 unsigned int j;
5777
43234a1e 5778 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5779 gas_assert (i.reg_operands
7ab9ffdd 5780 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5781 || operand_type_equal (&i.types[0], &regymm)
5782 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5783 if (register_number (i.op[0].regs) != 0)
c0f3af97 5784 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5785
5786 for (j = 1; j < i.operands; j++)
5787 {
5788 i.op[j - 1] = i.op[j];
5789 i.types[j - 1] = i.types[j];
5790
5791 /* We need to adjust fields in i.tm since they are used by
5792 build_modrm_byte. */
5793 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5794 }
5795
e2ec9d29
L		 5796 i.operands--;
5797 i.reg_operands--;
e2ec9d29
L		 5798 i.tm.operands--;
5799 }
5800 else if (i.tm.opcode_modifier.regkludge)
5801 {
5802 /* The imul $imm, %reg instruction is converted into
5803 imul $imm, %reg, %reg, and the clr %reg instruction
5804 is converted into xor %reg, %reg. */
5805
5806 unsigned int first_reg_op;
5807
5808 if (operand_type_check (i.types[0], reg))
5809 first_reg_op = 0;
5810 else
5811 first_reg_op = 1;
5812 /* Pretend we saw the extra register operand. */
9c2799c2 5813 gas_assert (i.reg_operands == 1
7ab9ffdd 5814 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5815 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5816 i.types[first_reg_op + 1] = i.types[first_reg_op];
5817 i.operands++;
5818 i.reg_operands++;
29b0f896
AM		 5819 }
5820
40fb9820 5821 if (i.tm.opcode_modifier.shortform)
29b0f896 5822 {
40fb9820
L		 5823 if (i.types[0].bitfield.sreg2
5824 || i.types[0].bitfield.sreg3)
29b0f896 5825 {
4eed87de
AM		 5826 if (i.tm.base_opcode == POP_SEG_SHORT
5827 && i.op[0].regs->reg_num == 1)
29b0f896 5828 {
a87af027 5829 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5830 return 0;
29b0f896 5831 }
4eed87de
AM		 5832 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5833 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5834 i.rex |= REX_B;
4eed87de
AM		 5835 }
5836 else
5837 {
7ab9ffdd 5838 /* The register or float register operand is in operand
85f10a01 5839 0 or 1. */
40fb9820 5840 unsigned int op;
7ab9ffdd
L		 5841
5842 if (i.types[0].bitfield.floatreg
5843 || operand_type_check (i.types[0], reg))
5844 op = 0;
5845 else
5846 op = 1;
4eed87de
AM		 5847 /* Register goes in low 3 bits of opcode. */
5848 i.tm.base_opcode |= i.op[op].regs->reg_num;
5849 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5850 i.rex |= REX_B;
40fb9820 5851 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5852 {
4eed87de
AM		 5853 /* Warn about some common errors, but press on regardless.
5854 The first case can be generated by gcc (<= 2.8.1). */
5855 if (i.operands == 2)
5856 {
5857 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5858 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5859 register_prefix, i.op[!intel_syntax].regs->reg_name,
5860 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5861 }
5862 else
5863 {
5864 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5865 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5866 register_prefix, i.op[0].regs->reg_name);
4eed87de 5867 }
29b0f896
AM		 5868 }
5869 }
5870 }
40fb9820 5871 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5872 {
5873 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5874 must be put into the modrm byte). Now, we make the modrm and
5875 index base bytes based on all the info we've collected. */
29b0f896
AM		 5876
5877 default_seg = build_modrm_byte ();
5878 }
8a2ed489 5879 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5880 {
5881 default_seg = &ds;
5882 }
40fb9820 5883 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5884 {
5885 /* For the string instructions that allow a segment override
5886 on one of their operands, the default segment is ds. */
5887 default_seg = &ds;
5888 }
5889
75178d9d
L		 5890 if (i.tm.base_opcode == 0x8d /* lea */
5891 && i.seg[0]
5892 && !quiet_warnings)
30123838 5893 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5894
5895 /* If a segment was explicitly specified, and the specified segment
5896 is not the default, use an opcode prefix to select it. If we
5897 never figured out what the default segment is, then default_seg
5898 will be zero at this point, and the specified segment prefix will
5899 always be used. */
29b0f896
AM		 5900 if ((i.seg[0]) && (i.seg[0] != default_seg))
5901 {
5902 if (!add_prefix (i.seg[0]->seg_prefix))
5903 return 0;
5904 }
5905 return 1;
5906}
5907
5908static const seg_entry *
e3bb37b5 5909build_modrm_byte (void)
29b0f896
AM		 5910{
5911 const seg_entry *default_seg = 0;
c0f3af97 5912 unsigned int source, dest;
8cd7925b 5913 int vex_3_sources;
c0f3af97
L		 5914
5915 /* The first operand of instructions with VEX prefix and 3 sources
5916 must be VEX_Imm4. */
8cd7925b 5917 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5918 if (vex_3_sources)
5919 {
91d6fa6a 5920 unsigned int nds, reg_slot;
4c2c6516 5921 expressionS *exp;
c0f3af97 5922
922d8de8 5923 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5924 && i.tm.opcode_modifier.immext)
5925 {
5926 dest = i.operands - 2;
5927 gas_assert (dest == 3);
5928 }
922d8de8 5929 else
a683cc34 5930 dest = i.operands - 1;
c0f3af97 5931 nds = dest - 1;
922d8de8 5932
a683cc34
SP		 5933 /* There are 2 kinds of instructions:
5934 1. 5 operands: 4 register operands or 3 register operands
5935 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 5936 VexW0 or VexW1. The destination must be either XMM, YMM or
5937 ZMM register.
a683cc34
SP		 5938 2. 4 operands: 4 register operands or 3 register operands
5939 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5940 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5941 || (i.reg_operands == 3 && i.mem_operands == 1))
5942 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5943 && (i.tm.opcode_modifier.veximmext
5944 || (i.imm_operands == 1
5945 && i.types[0].bitfield.vec_imm4
5946 && (i.tm.opcode_modifier.vexw == VEXW0
5947 || i.tm.opcode_modifier.vexw == VEXW1)
5948 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 5949 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
5950 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 5951
5952 if (i.imm_operands == 0)
5953 {
5954 /* When there is no immediate operand, generate an 8bit
5955 immediate operand to encode the first operand. */
5956 exp = &im_expressions[i.imm_operands++];
5957 i.op[i.operands].imms = exp;
5958 i.types[i.operands] = imm8;
5959 i.operands++;
5960 /* If VexW1 is set, the first operand is the source and
5961 the second operand is encoded in the immediate operand. */
5962 if (i.tm.opcode_modifier.vexw == VEXW1)
5963 {
5964 source = 0;
5965 reg_slot = 1;
5966 }
5967 else
5968 {
5969 source = 1;
5970 reg_slot = 0;
5971 }
5972
5973 /* FMA swaps REG and NDS. */
5974 if (i.tm.cpu_flags.bitfield.cpufma)
5975 {
5976 unsigned int tmp;
5977 tmp = reg_slot;
5978 reg_slot = nds;
5979 nds = tmp;
5980 }
5981
24981e7b
L		 5982 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5983 &regxmm)
a683cc34 5984 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 5985 &regymm)
5986 || operand_type_equal (&i.tm.operand_types[reg_slot],
5987 &regzmm));
a683cc34 5988 exp->X_op = O_constant;
4c692bc7 5989 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 5990 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
5991 }
922d8de8 5992 else
a683cc34
SP		 5993 {
5994 unsigned int imm_slot;
5995
5996 if (i.tm.opcode_modifier.vexw == VEXW0)
5997 {
5998 /* If VexW0 is set, the third operand is the source and
5999 the second operand is encoded in the immediate
6000 operand. */
6001 source = 2;
6002 reg_slot = 1;
6003 }
6004 else
6005 {
6006 /* VexW1 is set, the second operand is the source and
6007 the third operand is encoded in the immediate
6008 operand. */
6009 source = 1;
6010 reg_slot = 2;
6011 }
6012
6013 if (i.tm.opcode_modifier.immext)
6014 {
6015 /* When ImmExt is set, the immdiate byte is the last
6016 operand. */
6017 imm_slot = i.operands - 1;
6018 source--;
6019 reg_slot--;
6020 }
6021 else
6022 {
6023 imm_slot = 0;
6024
6025 /* Turn on Imm8 so that output_imm will generate it. */
6026 i.types[imm_slot].bitfield.imm8 = 1;
6027 }
6028
24981e7b
L		 6029 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6030 &regxmm)
6031 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6032 &regymm)
6033 || operand_type_equal (&i.tm.operand_types[reg_slot],
6034 &regzmm));
a683cc34 6035 i.op[imm_slot].imms->X_add_number
4c692bc7 6036 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6037 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6038 }
6039
6040 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6041 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6042 &regymm)
6043 || operand_type_equal (&i.tm.operand_types[nds],
6044 &regzmm));
dae39acc 6045 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6046 }
6047 else
6048 source = dest = 0;
29b0f896
AM		 6049
6050 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6051 implicit registers do not count. If there are 3 register
6052 operands, it must be a instruction with VexNDS. For a
6053 instruction with VexNDD, the destination register is encoded
6054 in VEX prefix. If there are 4 register operands, it must be
6055 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6056 if (i.mem_operands == 0
6057 && ((i.reg_operands == 2
2426c15f 6058 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6059 || (i.reg_operands == 3
2426c15f 6060 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6061 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6062 {
cab737b9
L		 6063 switch (i.operands)
6064 {
6065 case 2:
6066 source = 0;
6067 break;
6068 case 3:
c81128dc
L		 6069 /* When there are 3 operands, one of them may be immediate,
6070 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6071 the first operand must be shift count register (cl) or it
6072 is an instruction with VexNDS. */
9c2799c2 6073 gas_assert (i.imm_operands == 1
7ab9ffdd 6074 || (i.imm_operands == 0
2426c15f 6075 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6076 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6077 if (operand_type_check (i.types[0], imm)
6078 || i.types[0].bitfield.shiftcount)
6079 source = 1;
6080 else
6081 source = 0;
cab737b9
L		 6082 break;
6083 case 4:
368d64cc
L		 6084 /* When there are 4 operands, the first two must be 8bit
6085 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6086 one.
6087
6088 For instructions with VexNDS, if the first operand
6089 an imm8, the source operand is the 2nd one. If the last
6090 operand is imm8, the source operand is the first one. */
9c2799c2 6091 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6092 && i.types[0].bitfield.imm8
6093 && i.types[1].bitfield.imm8)
2426c15f 6094 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6095 && i.imm_operands == 1
6096 && (i.types[0].bitfield.imm8
43234a1e
L		 6097 || i.types[i.operands - 1].bitfield.imm8
6098 || i.rounding)));
9f2670f2
L		 6099 if (i.imm_operands == 2)
6100 source = 2;
6101 else
c0f3af97
L		 6102 {
6103 if (i.types[0].bitfield.imm8)
6104 source = 1;
6105 else
6106 source = 0;
6107 }
c0f3af97
L		 6108 break;
6109 case 5:
43234a1e
L		 6110 if (i.tm.opcode_modifier.evex)
6111 {
6112 /* For EVEX instructions, when there are 5 operands, the
6113 first one must be immediate operand. If the second one
6114 is immediate operand, the source operand is the 3th
6115 one. If the last one is immediate operand, the source
6116 operand is the 2nd one. */
6117 gas_assert (i.imm_operands == 2
6118 && i.tm.opcode_modifier.sae
6119 && operand_type_check (i.types[0], imm));
6120 if (operand_type_check (i.types[1], imm))
6121 source = 2;
6122 else if (operand_type_check (i.types[4], imm))
6123 source = 1;
6124 else
6125 abort ();
6126 }
cab737b9
L		 6127 break;
6128 default:
6129 abort ();
6130 }
6131
c0f3af97
L		 6132 if (!vex_3_sources)
6133 {
6134 dest = source + 1;
6135
43234a1e
L		 6136 /* RC/SAE operand could be between DEST and SRC. That happens
6137 when one operand is GPR and the other one is XMM/YMM/ZMM
6138 register. */
6139 if (i.rounding && i.rounding->operand == (int) dest)
6140 dest++;
6141
2426c15f 6142 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6143 {
43234a1e
L		 6144 /* For instructions with VexNDS, the register-only source
6145 operand must be 32/64bit integer, XMM, YMM or ZMM
6146 register. It is encoded in VEX prefix. We need to
6147 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6148
6149 i386_operand_type op;
6150 unsigned int vvvv;
6151
6152 /* Check register-only source operand when two source
6153 operands are swapped. */
6154 if (!i.tm.operand_types[source].bitfield.baseindex
6155 && i.tm.operand_types[dest].bitfield.baseindex)
6156 {
6157 vvvv = source;
6158 source = dest;
6159 }
6160 else
6161 vvvv = dest;
6162
6163 op = i.tm.operand_types[vvvv];
fa99fab2 6164 op.bitfield.regmem = 0;
c0f3af97 6165 if ((dest + 1) >= i.operands
f12dc422
L		 6166 || (op.bitfield.reg32 != 1
6167 && !op.bitfield.reg64 != 1
6168 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6169 && !operand_type_equal (&op, &regymm)
6170 && !operand_type_equal (&op, &regzmm)
6171 && !operand_type_equal (&op, &regmask)))
c0f3af97 6172 abort ();
f12dc422 6173 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6174 dest++;
6175 }
6176 }
29b0f896
AM		 6177
6178 i.rm.mode = 3;
6179 /* One of the register operands will be encoded in the i.tm.reg
6180 field, the other in the combined i.tm.mode and i.tm.regmem
6181 fields. If no form of this instruction supports a memory
6182 destination operand, then we assume the source operand may
6183 sometimes be a memory operand and so we need to store the
6184 destination in the i.rm.reg field. */
40fb9820
L		 6185 if (!i.tm.operand_types[dest].bitfield.regmem
6186 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6187 {
6188 i.rm.reg = i.op[dest].regs->reg_num;
6189 i.rm.regmem = i.op[source].regs->reg_num;
6190 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6191 i.rex |= REX_R;
43234a1e
L		 6192 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6193 i.vrex |= REX_R;
29b0f896 6194 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6195 i.rex |= REX_B;
43234a1e
L		 6196 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6197 i.vrex |= REX_B;
29b0f896
AM		 6198 }
6199 else
6200 {
6201 i.rm.reg = i.op[source].regs->reg_num;
6202 i.rm.regmem = i.op[dest].regs->reg_num;
6203 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6204 i.rex |= REX_B;
43234a1e
L		 6205 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6206 i.vrex |= REX_B;
29b0f896 6207 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6208 i.rex |= REX_R;
43234a1e
L		 6209 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6210 i.vrex |= REX_R;
29b0f896 6211 }
161a04f6 6212 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6213 {
40fb9820
L		 6214 if (!i.types[0].bitfield.control
6215 && !i.types[1].bitfield.control)
c4a530c5 6216 abort ();
161a04f6 6217 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6218 add_prefix (LOCK_PREFIX_OPCODE);
6219 }
29b0f896
AM		 6220 }
6221 else
6222 { /* If it's not 2 reg operands... */
c0f3af97
L		 6223 unsigned int mem;
6224
29b0f896
AM		 6225 if (i.mem_operands)
6226 {
6227 unsigned int fake_zero_displacement = 0;
99018f42 6228 unsigned int op;
4eed87de 6229
7ab9ffdd
L		 6230 for (op = 0; op < i.operands; op++)
6231 if (operand_type_check (i.types[op], anymem))
6232 break;
7ab9ffdd 6233 gas_assert (op < i.operands);
29b0f896 6234
6c30d220
L		 6235 if (i.tm.opcode_modifier.vecsib)
6236 {
6237 if (i.index_reg->reg_num == RegEiz
6238 || i.index_reg->reg_num == RegRiz)
6239 abort ();
6240
6241 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6242 if (!i.base_reg)
6243 {
6244 i.sib.base = NO_BASE_REGISTER;
6245 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6246 /* No Vec_Disp8 if there is no base. */
6247 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6248 i.types[op].bitfield.disp8 = 0;
6249 i.types[op].bitfield.disp16 = 0;
6250 i.types[op].bitfield.disp64 = 0;
6251 if (flag_code != CODE_64BIT)
6252 {
6253 /* Must be 32 bit */
6254 i.types[op].bitfield.disp32 = 1;
6255 i.types[op].bitfield.disp32s = 0;
6256 }
6257 else
6258 {
6259 i.types[op].bitfield.disp32 = 0;
6260 i.types[op].bitfield.disp32s = 1;
6261 }
6262 }
6263 i.sib.index = i.index_reg->reg_num;
6264 if ((i.index_reg->reg_flags & RegRex) != 0)
6265 i.rex |= REX_X;
43234a1e
L		 6266 if ((i.index_reg->reg_flags & RegVRex) != 0)
6267 i.vrex |= REX_X;
6c30d220
L		 6268 }
6269
29b0f896
AM		 6270 default_seg = &ds;
6271
6272 if (i.base_reg == 0)
6273 {
6274 i.rm.mode = 0;
6275 if (!i.disp_operands)
6c30d220
L		 6276 {
6277 fake_zero_displacement = 1;
6278 /* Instructions with VSIB byte need 32bit displacement
6279 if there is no base register. */
6280 if (i.tm.opcode_modifier.vecsib)
6281 i.types[op].bitfield.disp32 = 1;
6282 }
29b0f896
AM		 6283 if (i.index_reg == 0)
6284 {
6c30d220 6285 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6286 /* Operand is just <disp> */
20f0a1fc 6287 if (flag_code == CODE_64BIT)
29b0f896
AM		 6288 {
6289 /* 64bit mode overwrites the 32bit absolute
6290 addressing by RIP relative addressing and
6291 absolute addressing is encoded by one of the
6292 redundant SIB forms. */
6293 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6294 i.sib.base = NO_BASE_REGISTER;
6295 i.sib.index = NO_INDEX_REGISTER;
fc225355 6296 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6297 ? disp32s : disp32);
20f0a1fc 6298 }
fc225355
L		 6299 else if ((flag_code == CODE_16BIT)
6300 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6301 {
6302 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6303 i.types[op] = disp16;
20f0a1fc
NC		 6304 }
6305 else
6306 {
6307 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6308 i.types[op] = disp32;
29b0f896
AM		 6309 }
6310 }
6c30d220 6311 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6312 {
6c30d220 6313 /* !i.base_reg && i.index_reg */
db51cc60
L		 6314 if (i.index_reg->reg_num == RegEiz
6315 || i.index_reg->reg_num == RegRiz)
6316 i.sib.index = NO_INDEX_REGISTER;
6317 else
6318 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6319 i.sib.base = NO_BASE_REGISTER;
6320 i.sib.scale = i.log2_scale_factor;
6321 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6322 /* No Vec_Disp8 if there is no base. */
6323 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6324 i.types[op].bitfield.disp8 = 0;
6325 i.types[op].bitfield.disp16 = 0;
6326 i.types[op].bitfield.disp64 = 0;
29b0f896 6327 if (flag_code != CODE_64BIT)
40fb9820
L		 6328 {
6329 /* Must be 32 bit */
6330 i.types[op].bitfield.disp32 = 1;
6331 i.types[op].bitfield.disp32s = 0;
6332 }
29b0f896 6333 else
40fb9820
L		 6334 {
6335 i.types[op].bitfield.disp32 = 0;
6336 i.types[op].bitfield.disp32s = 1;
6337 }
29b0f896 6338 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6339 i.rex |= REX_X;
29b0f896
AM		 6340 }
6341 }
6342 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6343 else if (i.base_reg->reg_num == RegRip ||
6344 i.base_reg->reg_num == RegEip)
29b0f896 6345 {
6c30d220 6346 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6347 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6348 i.types[op].bitfield.disp8 = 0;
6349 i.types[op].bitfield.disp16 = 0;
6350 i.types[op].bitfield.disp32 = 0;
6351 i.types[op].bitfield.disp32s = 1;
6352 i.types[op].bitfield.disp64 = 0;
43234a1e 6353 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6354 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6355 if (! i.disp_operands)
6356 fake_zero_displacement = 1;
29b0f896 6357 }
40fb9820 6358 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6359 {
6c30d220 6360 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6361 switch (i.base_reg->reg_num)
6362 {
6363 case 3: /* (%bx) */
6364 if (i.index_reg == 0)
6365 i.rm.regmem = 7;
6366 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6367 i.rm.regmem = i.index_reg->reg_num - 6;
6368 break;
6369 case 5: /* (%bp) */
6370 default_seg = &ss;
6371 if (i.index_reg == 0)
6372 {
6373 i.rm.regmem = 6;
40fb9820 6374 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6375 {
6376 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6377 if (i.tm.operand_types[op].bitfield.vec_disp8)
6378 i.types[op].bitfield.vec_disp8 = 1;
6379 else
6380 i.types[op].bitfield.disp8 = 1;
252b5132 6381 fake_zero_displacement = 1;
29b0f896
AM		 6382 }
6383 }
6384 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6385 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6386 break;
6387 default: /* (%si) -> 4 or (%di) -> 5 */
6388 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6389 }
6390 i.rm.mode = mode_from_disp_size (i.types[op]);
6391 }
6392 else /* i.base_reg and 32/64 bit mode */
6393 {
6394 if (flag_code == CODE_64BIT
40fb9820
L		 6395 && operand_type_check (i.types[op], disp))
6396 {
6397 i386_operand_type temp;
0dfbf9d7 6398 operand_type_set (&temp, 0);
40fb9820 6399 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6400 temp.bitfield.vec_disp8
6401 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6402 i.types[op] = temp;
6403 if (i.prefix[ADDR_PREFIX] == 0)
6404 i.types[op].bitfield.disp32s = 1;
6405 else
6406 i.types[op].bitfield.disp32 = 1;
6407 }
20f0a1fc 6408
6c30d220
L		 6409 if (!i.tm.opcode_modifier.vecsib)
6410 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6411 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6412 i.rex |= REX_B;
29b0f896
AM		 6413 i.sib.base = i.base_reg->reg_num;
6414 /* x86-64 ignores REX prefix bit here to avoid decoder
6415 complications. */
848930b2
JB		 6416 if (!(i.base_reg->reg_flags & RegRex)
6417 && (i.base_reg->reg_num == EBP_REG_NUM
6418 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6419 default_seg = &ss;
848930b2 6420 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6421 {
848930b2 6422 fake_zero_displacement = 1;
43234a1e
L		 6423 if (i.tm.operand_types [op].bitfield.vec_disp8)
6424 i.types[op].bitfield.vec_disp8 = 1;
6425 else
6426 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6427 }
6428 i.sib.scale = i.log2_scale_factor;
6429 if (i.index_reg == 0)
6430 {
6c30d220 6431 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6432 /* <disp>(%esp) becomes two byte modrm with no index
6433 register. We've already stored the code for esp
6434 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6435 Any base register besides %esp will not use the
6436 extra modrm byte. */
6437 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6438 }
6c30d220 6439 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6440 {
db51cc60
L		 6441 if (i.index_reg->reg_num == RegEiz
6442 || i.index_reg->reg_num == RegRiz)
6443 i.sib.index = NO_INDEX_REGISTER;
6444 else
6445 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6446 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6447 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6448 i.rex |= REX_X;
29b0f896 6449 }
67a4f2b7
AO		 6450
6451 if (i.disp_operands
6452 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6453 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6454 i.rm.mode = 0;
6455 else
a501d77e
L		 6456 {
6457 if (!fake_zero_displacement
6458 && !i.disp_operands
6459 && i.disp_encoding)
6460 {
6461 fake_zero_displacement = 1;
6462 if (i.disp_encoding == disp_encoding_8bit)
6463 i.types[op].bitfield.disp8 = 1;
6464 else
6465 i.types[op].bitfield.disp32 = 1;
6466 }
6467 i.rm.mode = mode_from_disp_size (i.types[op]);
6468 }
29b0f896 6469 }
252b5132 6470
29b0f896
AM		 6471 if (fake_zero_displacement)
6472 {
6473 /* Fakes a zero displacement assuming that i.types[op]
6474 holds the correct displacement size. */
6475 expressionS *exp;
6476
9c2799c2 6477 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6478 exp = &disp_expressions[i.disp_operands++];
6479 i.op[op].disps = exp;
6480 exp->X_op = O_constant;
6481 exp->X_add_number = 0;
6482 exp->X_add_symbol = (symbolS *) 0;
6483 exp->X_op_symbol = (symbolS *) 0;
6484 }
c0f3af97
L		 6485
6486 mem = op;
29b0f896 6487 }
c0f3af97
L		 6488 else
6489 mem = ~0;
252b5132 6490
8c43a48b 6491 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6492 {
6493 if (operand_type_check (i.types[0], imm))
6494 i.vex.register_specifier = NULL;
6495 else
6496 {
6497 /* VEX.vvvv encodes one of the sources when the first
6498 operand is not an immediate. */
1ef99a7b 6499 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6500 i.vex.register_specifier = i.op[0].regs;
6501 else
6502 i.vex.register_specifier = i.op[1].regs;
6503 }
6504
6505 /* Destination is a XMM register encoded in the ModRM.reg
6506 and VEX.R bit. */
6507 i.rm.reg = i.op[2].regs->reg_num;
6508 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6509 i.rex |= REX_R;
6510
6511 /* ModRM.rm and VEX.B encodes the other source. */
6512 if (!i.mem_operands)
6513 {
6514 i.rm.mode = 3;
6515
1ef99a7b 6516 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6517 i.rm.regmem = i.op[1].regs->reg_num;
6518 else
6519 i.rm.regmem = i.op[0].regs->reg_num;
6520
6521 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6522 i.rex |= REX_B;
6523 }
6524 }
2426c15f 6525 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6526 {
6527 i.vex.register_specifier = i.op[2].regs;
6528 if (!i.mem_operands)
6529 {
6530 i.rm.mode = 3;
6531 i.rm.regmem = i.op[1].regs->reg_num;
6532 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6533 i.rex |= REX_B;
6534 }
6535 }
29b0f896
AM		 6536 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6537 (if any) based on i.tm.extension_opcode. Again, we must be
6538 careful to make sure that segment/control/debug/test/MMX
6539 registers are coded into the i.rm.reg field. */
f88c9eb0 6540 else if (i.reg_operands)
29b0f896 6541 {
99018f42 6542 unsigned int op;
7ab9ffdd
L		 6543 unsigned int vex_reg = ~0;
6544
6545 for (op = 0; op < i.operands; op++)
6546 if (i.types[op].bitfield.reg8
6547 || i.types[op].bitfield.reg16
6548 || i.types[op].bitfield.reg32
6549 || i.types[op].bitfield.reg64
6550 || i.types[op].bitfield.regmmx
6551 || i.types[op].bitfield.regxmm
6552 || i.types[op].bitfield.regymm
7e8b059b 6553 || i.types[op].bitfield.regbnd
43234a1e
L		 6554 || i.types[op].bitfield.regzmm
6555 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6556 || i.types[op].bitfield.sreg2
6557 || i.types[op].bitfield.sreg3
6558 || i.types[op].bitfield.control
6559 || i.types[op].bitfield.debug
6560 || i.types[op].bitfield.test)
6561 break;
c0209578 6562
7ab9ffdd
L		 6563 if (vex_3_sources)
6564 op = dest;
2426c15f 6565 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6566 {
6567 /* For instructions with VexNDS, the register-only
6568 source operand is encoded in VEX prefix. */
6569 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6570
7ab9ffdd 6571 if (op > mem)
c0f3af97 6572 {
7ab9ffdd
L		 6573 vex_reg = op++;
6574 gas_assert (op < i.operands);
c0f3af97
L		 6575 }
6576 else
c0f3af97 6577 {
f12dc422
L		 6578 /* Check register-only source operand when two source
6579 operands are swapped. */
6580 if (!i.tm.operand_types[op].bitfield.baseindex
6581 && i.tm.operand_types[op + 1].bitfield.baseindex)
6582 {
6583 vex_reg = op;
6584 op += 2;
6585 gas_assert (mem == (vex_reg + 1)
6586 && op < i.operands);
6587 }
6588 else
6589 {
6590 vex_reg = op + 1;
6591 gas_assert (vex_reg < i.operands);
6592 }
c0f3af97 6593 }
7ab9ffdd 6594 }
2426c15f 6595 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6596 {
f12dc422 6597 /* For instructions with VexNDD, the register destination
7ab9ffdd 6598 is encoded in VEX prefix. */
f12dc422
L		 6599 if (i.mem_operands == 0)
6600 {
6601 /* There is no memory operand. */
6602 gas_assert ((op + 2) == i.operands);
6603 vex_reg = op + 1;
6604 }
6605 else
8d63c93e 6606 {
f12dc422
L		 6607 /* There are only 2 operands. */
6608 gas_assert (op < 2 && i.operands == 2);
6609 vex_reg = 1;
6610 }
7ab9ffdd
L		 6611 }
6612 else
6613 gas_assert (op < i.operands);
99018f42 6614
7ab9ffdd
L		 6615 if (vex_reg != (unsigned int) ~0)
6616 {
f12dc422 6617 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6618
f12dc422
L		 6619 if (type->bitfield.reg32 != 1
6620 && type->bitfield.reg64 != 1
6621 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6622 && !operand_type_equal (type, &regymm)
6623 && !operand_type_equal (type, &regzmm)
6624 && !operand_type_equal (type, &regmask))
7ab9ffdd 6625 abort ();
f88c9eb0 6626
7ab9ffdd
L		 6627 i.vex.register_specifier = i.op[vex_reg].regs;
6628 }
6629
1b9f0c97
L		 6630 /* Don't set OP operand twice. */
6631 if (vex_reg != op)
7ab9ffdd 6632 {
1b9f0c97
L		 6633 /* If there is an extension opcode to put here, the
6634 register number must be put into the regmem field. */
6635 if (i.tm.extension_opcode != None)
6636 {
6637 i.rm.regmem = i.op[op].regs->reg_num;
6638 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6639 i.rex |= REX_B;
43234a1e
L		 6640 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6641 i.vrex |= REX_B;
1b9f0c97
L		 6642 }
6643 else
6644 {
6645 i.rm.reg = i.op[op].regs->reg_num;
6646 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6647 i.rex |= REX_R;
43234a1e
L		 6648 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6649 i.vrex |= REX_R;
1b9f0c97 6650 }
7ab9ffdd 6651 }
252b5132 6652
29b0f896
AM		 6653 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6654 must set it to 3 to indicate this is a register operand
6655 in the regmem field. */
6656 if (!i.mem_operands)
6657 i.rm.mode = 3;
6658 }
252b5132 6659
29b0f896 6660 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6661 if (i.tm.extension_opcode != None)
29b0f896
AM		 6662 i.rm.reg = i.tm.extension_opcode;
6663 }
6664 return default_seg;
6665}
252b5132 6666
29b0f896 6667static void
e3bb37b5 6668output_branch (void)
29b0f896
AM		 6669{
6670 char *p;
f8a5c266 6671 int size;
29b0f896
AM		 6672 int code16;
6673 int prefix;
6674 relax_substateT subtype;
6675 symbolS *sym;
6676 offsetT off;
6677
f8a5c266 6678 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6679 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6680
6681 prefix = 0;
6682 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6683 {
29b0f896
AM		 6684 prefix = 1;
6685 i.prefixes -= 1;
6686 code16 ^= CODE16;
252b5132 6687 }
29b0f896
AM		 6688 /* Pentium4 branch hints. */
6689 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6690 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6691 {
29b0f896
AM		 6692 prefix++;
6693 i.prefixes--;
6694 }
6695 if (i.prefix[REX_PREFIX] != 0)
6696 {
6697 prefix++;
6698 i.prefixes--;
2f66722d
AM		 6699 }
6700
7e8b059b
L		 6701 /* BND prefixed jump. */
6702 if (i.prefix[BND_PREFIX] != 0)
6703 {
6704 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6705 i.prefixes -= 1;
6706 }
6707
29b0f896
AM		 6708 if (i.prefixes != 0 && !intel_syntax)
6709 as_warn (_("skipping prefixes on this instruction"));
6710
6711 /* It's always a symbol; End frag & setup for relax.
6712 Make sure there is enough room in this frag for the largest
6713 instruction we may generate in md_convert_frag. This is 2
6714 bytes for the opcode and room for the prefix and largest
6715 displacement. */
6716 frag_grow (prefix + 2 + 4);
6717 /* Prefix and 1 opcode byte go in fr_fix. */
6718 p = frag_more (prefix + 1);
6719 if (i.prefix[DATA_PREFIX] != 0)
6720 *p++ = DATA_PREFIX_OPCODE;
6721 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6722 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6723 *p++ = i.prefix[SEG_PREFIX];
6724 if (i.prefix[REX_PREFIX] != 0)
6725 *p++ = i.prefix[REX_PREFIX];
6726 *p = i.tm.base_opcode;
6727
6728 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6729 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6730 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6731 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6732 else
f8a5c266 6733 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6734 subtype |= code16;
3e73aa7c 6735
29b0f896
AM		 6736 sym = i.op[0].disps->X_add_symbol;
6737 off = i.op[0].disps->X_add_number;
3e73aa7c 6738
29b0f896
AM		 6739 if (i.op[0].disps->X_op != O_constant
6740 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6741 {
29b0f896
AM		 6742 /* Handle complex expressions. */
6743 sym = make_expr_symbol (i.op[0].disps);
6744 off = 0;
6745 }
3e73aa7c 6746
29b0f896
AM		 6747 /* 1 possible extra opcode + 4 byte displacement go in var part.
6748 Pass reloc in fr_var. */
c3320543
L		 6749 frag_var (rs_machine_dependent, 5,
6750 ((!object_64bit
6751 || i.reloc[0] != NO_RELOC
6752 || (i.bnd_prefix == NULL && !add_bnd_prefix))
6753 ? i.reloc[0]
6754 : BFD_RELOC_X86_64_PC32_BND),
6755 subtype, sym, off, p);
29b0f896 6756}
3e73aa7c 6757
29b0f896 6758static void
e3bb37b5 6759output_jump (void)
29b0f896
AM		 6760{
6761 char *p;
6762 int size;
3e02c1cc 6763 fixS *fixP;
29b0f896 6764
40fb9820 6765 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6766 {
6767 /* This is a loop or jecxz type instruction. */
6768 size = 1;
6769 if (i.prefix[ADDR_PREFIX] != 0)
6770 {
6771 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6772 i.prefixes -= 1;
6773 }
6774 /* Pentium4 branch hints. */
6775 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6776 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6777 {
6778 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6779 i.prefixes--;
3e73aa7c
JH		 6780 }
6781 }
29b0f896
AM		 6782 else
6783 {
6784 int code16;
3e73aa7c 6785
29b0f896
AM		 6786 code16 = 0;
6787 if (flag_code == CODE_16BIT)
6788 code16 = CODE16;
3e73aa7c 6789
29b0f896
AM		 6790 if (i.prefix[DATA_PREFIX] != 0)
6791 {
6792 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6793 i.prefixes -= 1;
6794 code16 ^= CODE16;
6795 }
252b5132 6796
29b0f896
AM		 6797 size = 4;
6798 if (code16)
6799 size = 2;
6800 }
9fcc94b6 6801
29b0f896
AM		 6802 if (i.prefix[REX_PREFIX] != 0)
6803 {
6804 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6805 i.prefixes -= 1;
6806 }
252b5132 6807
7e8b059b
L		 6808 /* BND prefixed jump. */
6809 if (i.prefix[BND_PREFIX] != 0)
6810 {
6811 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6812 i.prefixes -= 1;
6813 }
6814
29b0f896
AM		 6815 if (i.prefixes != 0 && !intel_syntax)
6816 as_warn (_("skipping prefixes on this instruction"));
e0890092 6817
42164a71
L		 6818 p = frag_more (i.tm.opcode_length + size);
6819 switch (i.tm.opcode_length)
6820 {
6821 case 2:
6822 *p++ = i.tm.base_opcode >> 8;
6823 case 1:
6824 *p++ = i.tm.base_opcode;
6825 break;
6826 default:
6827 abort ();
6828 }
e0890092 6829
3e02c1cc 6830 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
c3320543
L		 6831 i.op[0].disps, 1, reloc (size, 1, 1,
6832 (i.bnd_prefix != NULL
6833 || add_bnd_prefix),
6834 i.reloc[0]));
3e02c1cc
AM		 6835
6836 /* All jumps handled here are signed, but don't use a signed limit
6837 check for 32 and 16 bit jumps as we want to allow wrap around at
6838 4G and 64k respectively. */
6839 if (size == 1)
6840 fixP->fx_signed = 1;
29b0f896 6841}
e0890092 6842
29b0f896 6843static void
e3bb37b5 6844output_interseg_jump (void)
29b0f896
AM		 6845{
6846 char *p;
6847 int size;
6848 int prefix;
6849 int code16;
252b5132 6850
29b0f896
AM		 6851 code16 = 0;
6852 if (flag_code == CODE_16BIT)
6853 code16 = CODE16;
a217f122 6854
29b0f896
AM		 6855 prefix = 0;
6856 if (i.prefix[DATA_PREFIX] != 0)
6857 {
6858 prefix = 1;
6859 i.prefixes -= 1;
6860 code16 ^= CODE16;
6861 }
6862 if (i.prefix[REX_PREFIX] != 0)
6863 {
6864 prefix++;
6865 i.prefixes -= 1;
6866 }
252b5132 6867
29b0f896
AM		 6868 size = 4;
6869 if (code16)
6870 size = 2;
252b5132 6871
29b0f896
AM		 6872 if (i.prefixes != 0 && !intel_syntax)
6873 as_warn (_("skipping prefixes on this instruction"));
252b5132 6874
29b0f896
AM		 6875 /* 1 opcode; 2 segment; offset */
6876 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6877
29b0f896
AM		 6878 if (i.prefix[DATA_PREFIX] != 0)
6879 *p++ = DATA_PREFIX_OPCODE;
252b5132 6880
29b0f896
AM		 6881 if (i.prefix[REX_PREFIX] != 0)
6882 *p++ = i.prefix[REX_PREFIX];
252b5132 6883
29b0f896
AM		 6884 *p++ = i.tm.base_opcode;
6885 if (i.op[1].imms->X_op == O_constant)
6886 {
6887 offsetT n = i.op[1].imms->X_add_number;
252b5132 6888
29b0f896
AM		 6889 if (size == 2
6890 && !fits_in_unsigned_word (n)
6891 && !fits_in_signed_word (n))
6892 {
6893 as_bad (_("16-bit jump out of range"));
6894 return;
6895 }
6896 md_number_to_chars (p, n, size);
6897 }
6898 else
6899 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
c3320543 6900 i.op[1].imms, 0, reloc (size, 0, 0, 0, i.reloc[1]));
29b0f896
AM		 6901 if (i.op[0].imms->X_op != O_constant)
6902 as_bad (_("can't handle non absolute segment in `%s'"),
6903 i.tm.name);
6904 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6905}
a217f122 6906
29b0f896 6907static void
e3bb37b5 6908output_insn (void)
29b0f896 6909{
2bbd9c25
JJ		 6910 fragS *insn_start_frag;
6911 offsetT insn_start_off;
6912
29b0f896
AM		 6913 /* Tie dwarf2 debug info to the address at the start of the insn.
6914 We can't do this after the insn has been output as the current
6915 frag may have been closed off. eg. by frag_var. */
6916 dwarf2_emit_insn (0);
6917
2bbd9c25
JJ		 6918 insn_start_frag = frag_now;
6919 insn_start_off = frag_now_fix ();
6920
29b0f896 6921 /* Output jumps. */
40fb9820 6922 if (i.tm.opcode_modifier.jump)
29b0f896 6923 output_branch ();
40fb9820
L		 6924 else if (i.tm.opcode_modifier.jumpbyte
6925 || i.tm.opcode_modifier.jumpdword)
29b0f896 6926 output_jump ();
40fb9820 6927 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6928 output_interseg_jump ();
6929 else
6930 {
6931 /* Output normal instructions here. */
6932 char *p;
6933 unsigned char *q;
47465058 6934 unsigned int j;
331d2d0d 6935 unsigned int prefix;
4dffcebc 6936
43234a1e
L		 6937 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6938 don't need the explicit prefix. */
6939 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 6940 {
c0f3af97 6941 switch (i.tm.opcode_length)
bc4bd9ab 6942 {
c0f3af97
L		 6943 case 3:
6944 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6945 {
c0f3af97
L		 6946 prefix = (i.tm.base_opcode >> 24) & 0xff;
6947 goto check_prefix;
6948 }
6949 break;
6950 case 2:
6951 if ((i.tm.base_opcode & 0xff0000) != 0)
6952 {
6953 prefix = (i.tm.base_opcode >> 16) & 0xff;
6954 if (i.tm.cpu_flags.bitfield.cpupadlock)
6955 {
4dffcebc 6956check_prefix:
c0f3af97 6957 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6958 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6959 != REPE_PREFIX_OPCODE))
6960 add_prefix (prefix);
6961 }
6962 else
4dffcebc
L		 6963 add_prefix (prefix);
6964 }
c0f3af97
L		 6965 break;
6966 case 1:
6967 break;
6968 default:
6969 abort ();
bc4bd9ab 6970 }
c0f3af97
L		 6971
6972 /* The prefix bytes. */
6973 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
6974 if (*q)
6975 FRAG_APPEND_1_CHAR (*q);
0f10071e 6976 }
ae5c1c7b 6977 else
c0f3af97
L		 6978 {
6979 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
6980 if (*q)
6981 switch (j)
6982 {
6983 case REX_PREFIX:
6984 /* REX byte is encoded in VEX prefix. */
6985 break;
6986 case SEG_PREFIX:
6987 case ADDR_PREFIX:
6988 FRAG_APPEND_1_CHAR (*q);
6989 break;
6990 default:
6991 /* There should be no other prefixes for instructions
6992 with VEX prefix. */
6993 abort ();
6994 }
6995
43234a1e
L		 6996 /* For EVEX instructions i.vrex should become 0 after
6997 build_evex_prefix. For VEX instructions upper 16 registers
6998 aren't available, so VREX should be 0. */
6999 if (i.vrex)
7000 abort ();
c0f3af97
L		 7001 /* Now the VEX prefix. */
7002 p = frag_more (i.vex.length);
7003 for (j = 0; j < i.vex.length; j++)
7004 p[j] = i.vex.bytes[j];
7005 }
252b5132 7006
29b0f896 7007 /* Now the opcode; be careful about word order here! */
4dffcebc 7008 if (i.tm.opcode_length == 1)
29b0f896
AM		 7009 {
7010 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7011 }
7012 else
7013 {
4dffcebc 7014 switch (i.tm.opcode_length)
331d2d0d 7015 {
43234a1e
L		 7016 case 4:
7017 p = frag_more (4);
7018 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7019 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7020 break;
4dffcebc 7021 case 3:
331d2d0d
L		 7022 p = frag_more (3);
7023 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7024 break;
7025 case 2:
7026 p = frag_more (2);
7027 break;
7028 default:
7029 abort ();
7030 break;
331d2d0d 7031 }
0f10071e 7032
29b0f896
AM		 7033 /* Put out high byte first: can't use md_number_to_chars! */
7034 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7035 *p = i.tm.base_opcode & 0xff;
7036 }
3e73aa7c 7037
29b0f896 7038 /* Now the modrm byte and sib byte (if present). */
40fb9820 7039 if (i.tm.opcode_modifier.modrm)
29b0f896 7040 {
4a3523fa
L		 7041 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7042 | i.rm.reg << 3
7043 | i.rm.mode << 6));
29b0f896
AM		 7044 /* If i.rm.regmem == ESP (4)
7045 && i.rm.mode != (Register mode)
7046 && not 16 bit
7047 ==> need second modrm byte. */
7048 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7049 && i.rm.mode != 3
40fb9820 7050 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7051 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7052 | i.sib.index << 3
7053 | i.sib.scale << 6));
29b0f896 7054 }
3e73aa7c 7055
29b0f896 7056 if (i.disp_operands)
2bbd9c25 7057 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7058
29b0f896 7059 if (i.imm_operands)
2bbd9c25 7060 output_imm (insn_start_frag, insn_start_off);
29b0f896 7061 }
252b5132 7062
29b0f896
AM		 7063#ifdef DEBUG386
7064 if (flag_debug)
7065 {
7b81dfbb 7066 pi ("" /*line*/, &i);
29b0f896
AM		 7067 }
7068#endif /* DEBUG386 */
7069}
252b5132 7070
e205caa7
L		 7071/* Return the size of the displacement operand N. */
7072
7073static int
7074disp_size (unsigned int n)
7075{
7076 int size = 4;
43234a1e
L		 7077
7078 /* Vec_Disp8 has to be 8bit. */
7079 if (i.types[n].bitfield.vec_disp8)
7080 size = 1;
7081 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7082 size = 8;
7083 else if (i.types[n].bitfield.disp8)
7084 size = 1;
7085 else if (i.types[n].bitfield.disp16)
7086 size = 2;
e205caa7
L		 7087 return size;
7088}
7089
7090/* Return the size of the immediate operand N. */
7091
7092static int
7093imm_size (unsigned int n)
7094{
7095 int size = 4;
40fb9820
L		 7096 if (i.types[n].bitfield.imm64)
7097 size = 8;
7098 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7099 size = 1;
7100 else if (i.types[n].bitfield.imm16)
7101 size = 2;
e205caa7
L		 7102 return size;
7103}
7104
29b0f896 7105static void
64e74474 7106output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7107{
7108 char *p;
7109 unsigned int n;
252b5132 7110
29b0f896
AM		 7111 for (n = 0; n < i.operands; n++)
7112 {
43234a1e
L		 7113 if (i.types[n].bitfield.vec_disp8
7114 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7115 {
7116 if (i.op[n].disps->X_op == O_constant)
7117 {
e205caa7 7118 int size = disp_size (n);
43234a1e 7119 offsetT val = i.op[n].disps->X_add_number;
252b5132 7120
43234a1e
L		 7121 if (i.types[n].bitfield.vec_disp8)
7122 val >>= i.memshift;
7123 val = offset_in_range (val, size);
29b0f896
AM		 7124 p = frag_more (size);
7125 md_number_to_chars (p, val, size);
7126 }
7127 else
7128 {
f86103b7 7129 enum bfd_reloc_code_real reloc_type;
e205caa7 7130 int size = disp_size (n);
40fb9820 7131 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 7132 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7133
e205caa7 7134 /* We can't have 8 bit displacement here. */
9c2799c2 7135 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7136
29b0f896
AM		 7137 /* The PC relative address is computed relative
7138 to the instruction boundary, so in case immediate
7139 fields follows, we need to adjust the value. */
7140 if (pcrel && i.imm_operands)
7141 {
29b0f896 7142 unsigned int n1;
e205caa7 7143 int sz = 0;
252b5132 7144
29b0f896 7145 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7146 if (operand_type_check (i.types[n1], imm))
252b5132 7147 {
e205caa7
L		 7148 /* Only one immediate is allowed for PC
7149 relative address. */
9c2799c2 7150 gas_assert (sz == 0);
e205caa7
L		 7151 sz = imm_size (n1);
7152 i.op[n].disps->X_add_number -= sz;
252b5132 7153 }
29b0f896 7154 /* We should find the immediate. */
9c2799c2 7155 gas_assert (sz != 0);
29b0f896 7156 }
520dc8e8 7157
29b0f896 7158 p = frag_more (size);
c3320543
L		 7159 reloc_type = reloc (size, pcrel, sign,
7160 (i.bnd_prefix != NULL
7161 || add_bnd_prefix),
7162 i.reloc[n]);
d6ab8113 7163 if (GOT_symbol
2bbd9c25 7164 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7165 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7166 || reloc_type == BFD_RELOC_X86_64_32S
7167 || (reloc_type == BFD_RELOC_64
7168 && object_64bit))
d6ab8113
JB		 7169 && (i.op[n].disps->X_op == O_symbol
7170 || (i.op[n].disps->X_op == O_add
7171 && ((symbol_get_value_expression
7172 (i.op[n].disps->X_op_symbol)->X_op)
7173 == O_subtract))))
7174 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7175 {
7176 offsetT add;
7177
7178 if (insn_start_frag == frag_now)
7179 add = (p - frag_now->fr_literal) - insn_start_off;
7180 else
7181 {
7182 fragS *fr;
7183
7184 add = insn_start_frag->fr_fix - insn_start_off;
7185 for (fr = insn_start_frag->fr_next;
7186 fr && fr != frag_now; fr = fr->fr_next)
7187 add += fr->fr_fix;
7188 add += p - frag_now->fr_literal;
7189 }
7190
4fa24527 7191 if (!object_64bit)
7b81dfbb
AJ		 7192 {
7193 reloc_type = BFD_RELOC_386_GOTPC;
7194 i.op[n].imms->X_add_number += add;
7195 }
7196 else if (reloc_type == BFD_RELOC_64)
7197 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7198 else
7b81dfbb
AJ		 7199 /* Don't do the adjustment for x86-64, as there
7200 the pcrel addressing is relative to the _next_
7201 insn, and that is taken care of in other code. */
d6ab8113 7202 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7203 }
062cd5e7 7204 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 7205 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 7206 }
7207 }
7208 }
7209}
252b5132 7210
29b0f896 7211static void
64e74474 7212output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7213{
7214 char *p;
7215 unsigned int n;
252b5132 7216
29b0f896
AM		 7217 for (n = 0; n < i.operands; n++)
7218 {
43234a1e
L		 7219 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7220 if (i.rounding && (int) n == i.rounding->operand)
7221 continue;
7222
40fb9820 7223 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7224 {
7225 if (i.op[n].imms->X_op == O_constant)
7226 {
e205caa7 7227 int size = imm_size (n);
29b0f896 7228 offsetT val;
b4cac588 7229
29b0f896
AM		 7230 val = offset_in_range (i.op[n].imms->X_add_number,
7231 size);
7232 p = frag_more (size);
7233 md_number_to_chars (p, val, size);
7234 }
7235 else
7236 {
7237 /* Not absolute_section.
7238 Need a 32-bit fixup (don't support 8bit
7239 non-absolute imms). Try to support other
7240 sizes ... */
f86103b7 7241 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7242 int size = imm_size (n);
7243 int sign;
29b0f896 7244
40fb9820 7245 if (i.types[n].bitfield.imm32s
a7d61044 7246 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7247 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7248 sign = 1;
e205caa7
L		 7249 else
7250 sign = 0;
520dc8e8 7251
29b0f896 7252 p = frag_more (size);
c3320543 7253 reloc_type = reloc (size, 0, sign, 0, i.reloc[n]);
f86103b7 7254
2bbd9c25
JJ		 7255 /* This is tough to explain. We end up with this one if we
7256 * have operands that look like
7257 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7258 * obtain the absolute address of the GOT, and it is strongly
7259 * preferable from a performance point of view to avoid using
7260 * a runtime relocation for this. The actual sequence of
7261 * instructions often look something like:
7262 *
7263 * call .L66
7264 * .L66:
7265 * popl %ebx
7266 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7267 *
7268 * The call and pop essentially return the absolute address
7269 * of the label .L66 and store it in %ebx. The linker itself
7270 * will ultimately change the first operand of the addl so
7271 * that %ebx points to the GOT, but to keep things simple, the
7272 * .o file must have this operand set so that it generates not
7273 * the absolute address of .L66, but the absolute address of
7274 * itself. This allows the linker itself simply treat a GOTPC
7275 * relocation as asking for a pcrel offset to the GOT to be
7276 * added in, and the addend of the relocation is stored in the
7277 * operand field for the instruction itself.
7278 *
7279 * Our job here is to fix the operand so that it would add
7280 * the correct offset so that %ebx would point to itself. The
7281 * thing that is tricky is that .-.L66 will point to the
7282 * beginning of the instruction, so we need to further modify
7283 * the operand so that it will point to itself. There are
7284 * other cases where you have something like:
7285 *
7286 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7287 *
7288 * and here no correction would be required. Internally in
7289 * the assembler we treat operands of this form as not being
7290 * pcrel since the '.' is explicitly mentioned, and I wonder
7291 * whether it would simplify matters to do it this way. Who
7292 * knows. In earlier versions of the PIC patches, the
7293 * pcrel_adjust field was used to store the correction, but
7294 * since the expression is not pcrel, I felt it would be
7295 * confusing to do it this way. */
7296
d6ab8113 7297 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7298 || reloc_type == BFD_RELOC_X86_64_32S
7299 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7300 && GOT_symbol
7301 && GOT_symbol == i.op[n].imms->X_add_symbol
7302 && (i.op[n].imms->X_op == O_symbol
7303 || (i.op[n].imms->X_op == O_add
7304 && ((symbol_get_value_expression
7305 (i.op[n].imms->X_op_symbol)->X_op)
7306 == O_subtract))))
7307 {
2bbd9c25
JJ		 7308 offsetT add;
7309
7310 if (insn_start_frag == frag_now)
7311 add = (p - frag_now->fr_literal) - insn_start_off;
7312 else
7313 {
7314 fragS *fr;
7315
7316 add = insn_start_frag->fr_fix - insn_start_off;
7317 for (fr = insn_start_frag->fr_next;
7318 fr && fr != frag_now; fr = fr->fr_next)
7319 add += fr->fr_fix;
7320 add += p - frag_now->fr_literal;
7321 }
7322
4fa24527 7323 if (!object_64bit)
d6ab8113 7324 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7325 else if (size == 4)
d6ab8113 7326 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7327 else if (size == 8)
7328 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7329 i.op[n].imms->X_add_number += add;
29b0f896 7330 }
29b0f896
AM		 7331 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7332 i.op[n].imms, 0, reloc_type);
7333 }
7334 }
7335 }
252b5132
RH		 7336}
7337\f
d182319b
JB		 7338/* x86_cons_fix_new is called via the expression parsing code when a
7339 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7340static int cons_sign = -1;
7341
7342void
e3bb37b5 7343x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7344 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7345{
62ebcb5c 7346 r = reloc (len, 0, cons_sign, 0, r);
d182319b
JB		 7347
7348#ifdef TE_PE
7349 if (exp->X_op == O_secrel)
7350 {
7351 exp->X_op = O_symbol;
7352 r = BFD_RELOC_32_SECREL;
7353 }
7354#endif
7355
7356 fix_new_exp (frag, off, len, exp, 0, r);
7357}
7358
357d1bd8
L		 7359/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7360 purpose of the `.dc.a' internal pseudo-op. */
7361
7362int
7363x86_address_bytes (void)
7364{
7365 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7366 return 4;
7367 return stdoutput->arch_info->bits_per_address / 8;
7368}
7369
d382c579
TG		 7370#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7371 || defined (LEX_AT)
c06ec724 7372# define lex_got(reloc, adjust, types, bnd_prefix) NULL
718ddfc0 7373#else
f3c180ae
AM		 7374/* Parse operands of the form
7375 <symbol>@GOTOFF+<nnn>
7376 and similar .plt or .got references.
7377
7378 If we find one, set up the correct relocation in RELOC and copy the
7379 input string, minus the `@GOTOFF' into a malloc'd buffer for
7380 parsing by the calling routine. Return this buffer, and if ADJUST
7381 is non-null set it to the length of the string we removed from the
7382 input line. Otherwise return NULL. */
7383static char *
91d6fa6a 7384lex_got (enum bfd_reloc_code_real *rel,
64e74474 7385 int *adjust,
c3320543
L		 7386 i386_operand_type *types,
7387 int bnd_prefix)
f3c180ae 7388{
7b81dfbb
AJ		 7389 /* Some of the relocations depend on the size of what field is to
7390 be relocated. But in our callers i386_immediate and i386_displacement
7391 we don't yet know the operand size (this will be set by insn
7392 matching). Hence we record the word32 relocation here,
7393 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7394 static const struct {
7395 const char *str;
cff8d58a 7396 int len;
4fa24527 7397 const enum bfd_reloc_code_real rel[2];
40fb9820 7398 const i386_operand_type types64;
f3c180ae 7399 } gotrel[] = {
8ce3d284 7400#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7401 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7402 BFD_RELOC_SIZE32 },
7403 OPERAND_TYPE_IMM32_64 },
8ce3d284 7404#endif
cff8d58a
L		 7405 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7406 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7407 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7408 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7409 BFD_RELOC_X86_64_PLT32 },
40fb9820 7410 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7411 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7412 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7413 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7414 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7415 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7416 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7417 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7418 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7419 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7420 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7421 BFD_RELOC_X86_64_TLSGD },
40fb9820 7422 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7423 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7424 _dummy_first_bfd_reloc_code_real },
40fb9820 7425 OPERAND_TYPE_NONE },
cff8d58a
L		 7426 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7427 BFD_RELOC_X86_64_TLSLD },
40fb9820 7428 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7429 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7430 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7431 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7432 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7433 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7434 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7435 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7436 _dummy_first_bfd_reloc_code_real },
40fb9820 7437 OPERAND_TYPE_NONE },
cff8d58a
L		 7438 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7439 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7440 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7441 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7442 _dummy_first_bfd_reloc_code_real },
40fb9820 7443 OPERAND_TYPE_NONE },
cff8d58a
L		 7444 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7445 _dummy_first_bfd_reloc_code_real },
40fb9820 7446 OPERAND_TYPE_NONE },
cff8d58a
L		 7447 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7448 BFD_RELOC_X86_64_GOT32 },
40fb9820 7449 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7450 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7451 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7452 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7453 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7454 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7455 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7456 };
7457 char *cp;
7458 unsigned int j;
7459
d382c579 7460#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7461 if (!IS_ELF)
7462 return NULL;
d382c579 7463#endif
718ddfc0 7464
f3c180ae 7465 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7466 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7467 return NULL;
7468
47465058 7469 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7470 {
cff8d58a 7471 int len = gotrel[j].len;
28f81592 7472 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7473 {
4fa24527 7474 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7475 {
28f81592
AM		 7476 int first, second;
7477 char *tmpbuf, *past_reloc;
f3c180ae 7478
91d6fa6a 7479 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7480
3956db08
JB		 7481 if (types)
7482 {
7483 if (flag_code != CODE_64BIT)
40fb9820
L		 7484 {
7485 types->bitfield.imm32 = 1;
7486 types->bitfield.disp32 = 1;
7487 }
3956db08
JB		 7488 else
7489 *types = gotrel[j].types64;
7490 }
7491
8fd4256d 7492 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7493 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7494
28f81592 7495 /* The length of the first part of our input line. */
f3c180ae 7496 first = cp - input_line_pointer;
28f81592
AM		 7497
7498 /* The second part goes from after the reloc token until
67c11a9b 7499 (and including) an end_of_line char or comma. */
28f81592 7500 past_reloc = cp + 1 + len;
67c11a9b
AM		 7501 cp = past_reloc;
7502 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7503 ++cp;
7504 second = cp + 1 - past_reloc;
28f81592
AM		 7505
7506 /* Allocate and copy string. The trailing NUL shouldn't
7507 be necessary, but be safe. */
1e9cc1c2 7508 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 7509 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7510 if (second != 0 && *past_reloc != ' ')
7511 /* Replace the relocation token with ' ', so that
7512 errors like foo@GOTOFF1 will be detected. */
7513 tmpbuf[first++] = ' ';
af89796a
L		 7514 else
7515 /* Increment length by 1 if the relocation token is
7516 removed. */
7517 len++;
7518 if (adjust)
7519 *adjust = len;
0787a12d
AM		 7520 memcpy (tmpbuf + first, past_reloc, second);
7521 tmpbuf[first + second] = '\0';
c3320543
L		 7522 if (bnd_prefix && *rel == BFD_RELOC_X86_64_PLT32)
7523 *rel = BFD_RELOC_X86_64_PLT32_BND;
f3c180ae
AM		 7524 return tmpbuf;
7525 }
7526
4fa24527
JB		 7527 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7528 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7529 return NULL;
7530 }
7531 }
7532
7533 /* Might be a symbol version string. Don't as_bad here. */
7534 return NULL;
7535}
4e4f7c87 7536#endif
f3c180ae 7537
a988325c
NC		 7538#ifdef TE_PE
7539#ifdef lex_got
7540#undef lex_got
7541#endif
7542/* Parse operands of the form
7543 <symbol>@SECREL32+<nnn>
7544
7545 If we find one, set up the correct relocation in RELOC and copy the
7546 input string, minus the `@SECREL32' into a malloc'd buffer for
7547 parsing by the calling routine. Return this buffer, and if ADJUST
7548 is non-null set it to the length of the string we removed from the
34bca508
L		 7549 input line. Otherwise return NULL.
7550
a988325c
NC		 7551 This function is copied from the ELF version above adjusted for PE targets. */
7552
7553static char *
7554lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7555 int *adjust ATTRIBUTE_UNUSED,
c06ec724
L		 7556 i386_operand_type *types,
7557 int bnd_prefix ATTRIBUTE_UNUSED)
a988325c
NC		 7558{
7559 static const struct
7560 {
7561 const char *str;
7562 int len;
7563 const enum bfd_reloc_code_real rel[2];
7564 const i386_operand_type types64;
7565 }
7566 gotrel[] =
7567 {
7568 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7569 BFD_RELOC_32_SECREL },
7570 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7571 };
7572
7573 char *cp;
7574 unsigned j;
7575
7576 for (cp = input_line_pointer; *cp != '@'; cp++)
7577 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7578 return NULL;
7579
7580 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7581 {
7582 int len = gotrel[j].len;
7583
7584 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7585 {
7586 if (gotrel[j].rel[object_64bit] != 0)
7587 {
7588 int first, second;
7589 char *tmpbuf, *past_reloc;
7590
7591 *rel = gotrel[j].rel[object_64bit];
7592 if (adjust)
7593 *adjust = len;
7594
7595 if (types)
7596 {
7597 if (flag_code != CODE_64BIT)
7598 {
7599 types->bitfield.imm32 = 1;
7600 types->bitfield.disp32 = 1;
7601 }
7602 else
7603 *types = gotrel[j].types64;
7604 }
7605
7606 /* The length of the first part of our input line. */
7607 first = cp - input_line_pointer;
7608
7609 /* The second part goes from after the reloc token until
7610 (and including) an end_of_line char or comma. */
7611 past_reloc = cp + 1 + len;
7612 cp = past_reloc;
7613 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7614 ++cp;
7615 second = cp + 1 - past_reloc;
7616
7617 /* Allocate and copy string. The trailing NUL shouldn't
7618 be necessary, but be safe. */
7619 tmpbuf = (char *) xmalloc (first + second + 2);
7620 memcpy (tmpbuf, input_line_pointer, first);
7621 if (second != 0 && *past_reloc != ' ')
7622 /* Replace the relocation token with ' ', so that
7623 errors like foo@SECLREL321 will be detected. */
7624 tmpbuf[first++] = ' ';
7625 memcpy (tmpbuf + first, past_reloc, second);
7626 tmpbuf[first + second] = '\0';
7627 return tmpbuf;
7628 }
7629
7630 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7631 gotrel[j].str, 1 << (5 + object_64bit));
7632 return NULL;
7633 }
7634 }
7635
7636 /* Might be a symbol version string. Don't as_bad here. */
7637 return NULL;
7638}
7639
7640#endif /* TE_PE */
7641
62ebcb5c 7642bfd_reloc_code_real_type
e3bb37b5 7643x86_cons (expressionS *exp, int size)
f3c180ae 7644{
62ebcb5c
AM		 7645 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7646
ee86248c
JB		 7647 intel_syntax = -intel_syntax;
7648
3c7b9c2c 7649 exp->X_md = 0;
4fa24527 7650 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7651 {
7652 /* Handle @GOTOFF and the like in an expression. */
7653 char *save;
7654 char *gotfree_input_line;
4a57f2cf 7655 int adjust = 0;
f3c180ae
AM		 7656
7657 save = input_line_pointer;
c3320543 7658 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL, 0);
f3c180ae
AM		 7659 if (gotfree_input_line)
7660 input_line_pointer = gotfree_input_line;
7661
7662 expression (exp);
7663
7664 if (gotfree_input_line)
7665 {
7666 /* expression () has merrily parsed up to the end of line,
7667 or a comma - in the wrong buffer. Transfer how far
7668 input_line_pointer has moved to the right buffer. */
7669 input_line_pointer = (save
7670 + (input_line_pointer - gotfree_input_line)
7671 + adjust);
7672 free (gotfree_input_line);
3992d3b7
AM		 7673 if (exp->X_op == O_constant
7674 || exp->X_op == O_absent
7675 || exp->X_op == O_illegal
0398aac5 7676 || exp->X_op == O_register
3992d3b7
AM		 7677 || exp->X_op == O_big)
7678 {
7679 char c = *input_line_pointer;
7680 *input_line_pointer = 0;
7681 as_bad (_("missing or invalid expression `%s'"), save);
7682 *input_line_pointer = c;
7683 }
f3c180ae
AM		 7684 }
7685 }
7686 else
7687 expression (exp);
ee86248c
JB		 7688
7689 intel_syntax = -intel_syntax;
7690
7691 if (intel_syntax)
7692 i386_intel_simplify (exp);
62ebcb5c
AM		 7693
7694 return got_reloc;
f3c180ae 7695}
f3c180ae 7696
9f32dd5b
L		 7697static void
7698signed_cons (int size)
6482c264 7699{
d182319b
JB		 7700 if (flag_code == CODE_64BIT)
7701 cons_sign = 1;
7702 cons (size);
7703 cons_sign = -1;
6482c264
NC		 7704}
7705
d182319b 7706#ifdef TE_PE
6482c264 7707static void
7016a5d5 7708pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7709{
7710 expressionS exp;
7711
7712 do
7713 {
7714 expression (&exp);
7715 if (exp.X_op == O_symbol)
7716 exp.X_op = O_secrel;
7717
7718 emit_expr (&exp, 4);
7719 }
7720 while (*input_line_pointer++ == ',');
7721
7722 input_line_pointer--;
7723 demand_empty_rest_of_line ();
7724}
6482c264
NC		 7725#endif
7726
43234a1e
L		 7727/* Handle Vector operations. */
7728
7729static char *
7730check_VecOperations (char *op_string, char *op_end)
7731{
7732 const reg_entry *mask;
7733 const char *saved;
7734 char *end_op;
7735
7736 while (*op_string
7737 && (op_end == NULL || op_string < op_end))
7738 {
7739 saved = op_string;
7740 if (*op_string == '{')
7741 {
7742 op_string++;
7743
7744 /* Check broadcasts. */
7745 if (strncmp (op_string, "1to", 3) == 0)
7746 {
7747 int bcst_type;
7748
7749 if (i.broadcast)
7750 goto duplicated_vec_op;
7751
7752 op_string += 3;
7753 if (*op_string == '8')
7754 bcst_type = BROADCAST_1TO8;
7755 else if (*op_string == '1'
7756 && *(op_string+1) == '6')
7757 {
7758 bcst_type = BROADCAST_1TO16;
7759 op_string++;
7760 }
7761 else
7762 {
7763 as_bad (_("Unsupported broadcast: `%s'"), saved);
7764 return NULL;
7765 }
7766 op_string++;
7767
7768 broadcast_op.type = bcst_type;
7769 broadcast_op.operand = this_operand;
7770 i.broadcast = &broadcast_op;
7771 }
7772 /* Check masking operation. */
7773 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7774 {
7775 /* k0 can't be used for write mask. */
7776 if (mask->reg_num == 0)
7777 {
7778 as_bad (_("`%s' can't be used for write mask"),
7779 op_string);
7780 return NULL;
7781 }
7782
7783 if (!i.mask)
7784 {
7785 mask_op.mask = mask;
7786 mask_op.zeroing = 0;
7787 mask_op.operand = this_operand;
7788 i.mask = &mask_op;
7789 }
7790 else
7791 {
7792 if (i.mask->mask)
7793 goto duplicated_vec_op;
7794
7795 i.mask->mask = mask;
7796
7797 /* Only "{z}" is allowed here. No need to check
7798 zeroing mask explicitly. */
7799 if (i.mask->operand != this_operand)
7800 {
7801 as_bad (_("invalid write mask `%s'"), saved);
7802 return NULL;
7803 }
7804 }
7805
7806 op_string = end_op;
7807 }
7808 /* Check zeroing-flag for masking operation. */
7809 else if (*op_string == 'z')
7810 {
7811 if (!i.mask)
7812 {
7813 mask_op.mask = NULL;
7814 mask_op.zeroing = 1;
7815 mask_op.operand = this_operand;
7816 i.mask = &mask_op;
7817 }
7818 else
7819 {
7820 if (i.mask->zeroing)
7821 {
7822 duplicated_vec_op:
7823 as_bad (_("duplicated `%s'"), saved);
7824 return NULL;
7825 }
7826
7827 i.mask->zeroing = 1;
7828
7829 /* Only "{%k}" is allowed here. No need to check mask
7830 register explicitly. */
7831 if (i.mask->operand != this_operand)
7832 {
7833 as_bad (_("invalid zeroing-masking `%s'"),
7834 saved);
7835 return NULL;
7836 }
7837 }
7838
7839 op_string++;
7840 }
7841 else
7842 goto unknown_vec_op;
7843
7844 if (*op_string != '}')
7845 {
7846 as_bad (_("missing `}' in `%s'"), saved);
7847 return NULL;
7848 }
7849 op_string++;
7850 continue;
7851 }
7852 unknown_vec_op:
7853 /* We don't know this one. */
7854 as_bad (_("unknown vector operation: `%s'"), saved);
7855 return NULL;
7856 }
7857
7858 return op_string;
7859}
7860
252b5132 7861static int
70e41ade 7862i386_immediate (char *imm_start)
252b5132
RH		 7863{
7864 char *save_input_line_pointer;
f3c180ae 7865 char *gotfree_input_line;
252b5132 7866 segT exp_seg = 0;
47926f60 7867 expressionS *exp;
40fb9820
L		 7868 i386_operand_type types;
7869
0dfbf9d7 7870 operand_type_set (&types, ~0);
252b5132
RH		 7871
7872 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7873 {
31b2323c
L		 7874 as_bad (_("at most %d immediate operands are allowed"),
7875 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 7876 return 0;
7877 }
7878
7879 exp = &im_expressions[i.imm_operands++];
520dc8e8 7880 i.op[this_operand].imms = exp;
252b5132
RH		 7881
7882 if (is_space_char (*imm_start))
7883 ++imm_start;
7884
7885 save_input_line_pointer = input_line_pointer;
7886 input_line_pointer = imm_start;
7887
c3320543
L		 7888 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types,
7889 (i.bnd_prefix != NULL
7890 || add_bnd_prefix));
f3c180ae
AM		 7891 if (gotfree_input_line)
7892 input_line_pointer = gotfree_input_line;
252b5132
RH		 7893
7894 exp_seg = expression (exp);
7895
83183c0c 7896 SKIP_WHITESPACE ();
43234a1e
L		 7897
7898 /* Handle vector operations. */
7899 if (*input_line_pointer == '{')
7900 {
7901 input_line_pointer = check_VecOperations (input_line_pointer,
7902 NULL);
7903 if (input_line_pointer == NULL)
7904 return 0;
7905 }
7906
252b5132 7907 if (*input_line_pointer)
f3c180ae 7908 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 7909
7910 input_line_pointer = save_input_line_pointer;
f3c180ae 7911 if (gotfree_input_line)
ee86248c
JB		 7912 {
7913 free (gotfree_input_line);
7914
7915 if (exp->X_op == O_constant || exp->X_op == O_register)
7916 exp->X_op = O_illegal;
7917 }
7918
7919 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7920}
252b5132 7921
ee86248c
JB		 7922static int
7923i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7924 i386_operand_type types, const char *imm_start)
7925{
7926 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 7927 {
313c53d1
L		 7928 if (imm_start)
7929 as_bad (_("missing or invalid immediate expression `%s'"),
7930 imm_start);
3992d3b7 7931 return 0;
252b5132 7932 }
3e73aa7c 7933 else if (exp->X_op == O_constant)
252b5132 7934 {
47926f60 7935 /* Size it properly later. */
40fb9820 7936 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 7937 /* If not 64bit, sign extend val. */
7938 if (flag_code != CODE_64BIT
4eed87de
AM		 7939 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7940 exp->X_add_number
7941 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 7942 }
4c63da97 7943#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 7944 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 7945 && exp_seg != absolute_section
47926f60 7946 && exp_seg != text_section
24eab124
AM		 7947 && exp_seg != data_section
7948 && exp_seg != bss_section
7949 && exp_seg != undefined_section
f86103b7 7950 && !bfd_is_com_section (exp_seg))
252b5132 7951 {
d0b47220 7952 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 7953 return 0;
7954 }
7955#endif
bb8f5920
L		 7956 else if (!intel_syntax && exp->X_op == O_register)
7957 {
313c53d1
L		 7958 if (imm_start)
7959 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 7960 return 0;
7961 }
252b5132
RH		 7962 else
7963 {
7964 /* This is an address. The size of the address will be
24eab124 7965 determined later, depending on destination register,
3e73aa7c 7966 suffix, or the default for the section. */
40fb9820
L		 7967 i.types[this_operand].bitfield.imm8 = 1;
7968 i.types[this_operand].bitfield.imm16 = 1;
7969 i.types[this_operand].bitfield.imm32 = 1;
7970 i.types[this_operand].bitfield.imm32s = 1;
7971 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 7972 i.types[this_operand] = operand_type_and (i.types[this_operand],
7973 types);
252b5132
RH		 7974 }
7975
7976 return 1;
7977}
7978
551c1ca1 7979static char *
e3bb37b5 7980i386_scale (char *scale)
252b5132 7981{
551c1ca1
AM		 7982 offsetT val;
7983 char *save = input_line_pointer;
252b5132 7984
551c1ca1
AM		 7985 input_line_pointer = scale;
7986 val = get_absolute_expression ();
7987
7988 switch (val)
252b5132 7989 {
551c1ca1 7990 case 1:
252b5132
RH		 7991 i.log2_scale_factor = 0;
7992 break;
551c1ca1 7993 case 2:
252b5132
RH		 7994 i.log2_scale_factor = 1;
7995 break;
551c1ca1 7996 case 4:
252b5132
RH		 7997 i.log2_scale_factor = 2;
7998 break;
551c1ca1 7999 case 8:
252b5132
RH		 8000 i.log2_scale_factor = 3;
8001 break;
8002 default:
a724f0f4
JB		 8003 {
8004 char sep = *input_line_pointer;
8005
8006 *input_line_pointer = '\0';
8007 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8008 scale);
8009 *input_line_pointer = sep;
8010 input_line_pointer = save;
8011 return NULL;
8012 }
252b5132 8013 }
29b0f896 8014 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8015 {
8016 as_warn (_("scale factor of %d without an index register"),
24eab124 8017 1 << i.log2_scale_factor);
252b5132 8018 i.log2_scale_factor = 0;
252b5132 8019 }
551c1ca1
AM		 8020 scale = input_line_pointer;
8021 input_line_pointer = save;
8022 return scale;
252b5132
RH		 8023}
8024
252b5132 8025static int
e3bb37b5 8026i386_displacement (char *disp_start, char *disp_end)
252b5132 8027{
29b0f896 8028 expressionS *exp;
252b5132
RH		 8029 segT exp_seg = 0;
8030 char *save_input_line_pointer;
f3c180ae 8031 char *gotfree_input_line;
40fb9820
L		 8032 int override;
8033 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8034 int ret;
252b5132 8035
31b2323c
L		 8036 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8037 {
8038 as_bad (_("at most %d displacement operands are allowed"),
8039 MAX_MEMORY_OPERANDS);
8040 return 0;
8041 }
8042
0dfbf9d7 8043 operand_type_set (&bigdisp, 0);
40fb9820
L		 8044 if ((i.types[this_operand].bitfield.jumpabsolute)
8045 || (!current_templates->start->opcode_modifier.jump
8046 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8047 {
40fb9820 8048 bigdisp.bitfield.disp32 = 1;
e05278af 8049 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8050 if (flag_code == CODE_64BIT)
8051 {
8052 if (!override)
8053 {
8054 bigdisp.bitfield.disp32s = 1;
8055 bigdisp.bitfield.disp64 = 1;
8056 }
8057 }
8058 else if ((flag_code == CODE_16BIT) ^ override)
8059 {
8060 bigdisp.bitfield.disp32 = 0;
8061 bigdisp.bitfield.disp16 = 1;
8062 }
e05278af
JB		 8063 }
8064 else
8065 {
8066 /* For PC-relative branches, the width of the displacement
8067 is dependent upon data size, not address size. */
e05278af 8068 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8069 if (flag_code == CODE_64BIT)
8070 {
8071 if (override || i.suffix == WORD_MNEM_SUFFIX)
8072 bigdisp.bitfield.disp16 = 1;
8073 else
8074 {
8075 bigdisp.bitfield.disp32 = 1;
8076 bigdisp.bitfield.disp32s = 1;
8077 }
8078 }
8079 else
e05278af
JB		 8080 {
8081 if (!override)
8082 override = (i.suffix == (flag_code != CODE_16BIT
8083 ? WORD_MNEM_SUFFIX
8084 : LONG_MNEM_SUFFIX));
40fb9820
L		 8085 bigdisp.bitfield.disp32 = 1;
8086 if ((flag_code == CODE_16BIT) ^ override)
8087 {
8088 bigdisp.bitfield.disp32 = 0;
8089 bigdisp.bitfield.disp16 = 1;
8090 }
e05278af 8091 }
e05278af 8092 }
c6fb90c8
L		 8093 i.types[this_operand] = operand_type_or (i.types[this_operand],
8094 bigdisp);
252b5132
RH		 8095
8096 exp = &disp_expressions[i.disp_operands];
520dc8e8 8097 i.op[this_operand].disps = exp;
252b5132
RH		 8098 i.disp_operands++;
8099 save_input_line_pointer = input_line_pointer;
8100 input_line_pointer = disp_start;
8101 END_STRING_AND_SAVE (disp_end);
8102
8103#ifndef GCC_ASM_O_HACK
8104#define GCC_ASM_O_HACK 0
8105#endif
8106#if GCC_ASM_O_HACK
8107 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8108 if (i.types[this_operand].bitfield.baseIndex
24eab124 8109 && displacement_string_end[-1] == '+')
252b5132
RH		 8110 {
8111 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8112 constraint within gcc asm statements.
8113 For instance:
8114
8115 #define _set_tssldt_desc(n,addr,limit,type) \
8116 __asm__ __volatile__ ( \
8117 "movw %w2,%0\n\t" \
8118 "movw %w1,2+%0\n\t" \
8119 "rorl $16,%1\n\t" \
8120 "movb %b1,4+%0\n\t" \
8121 "movb %4,5+%0\n\t" \
8122 "movb $0,6+%0\n\t" \
8123 "movb %h1,7+%0\n\t" \
8124 "rorl $16,%1" \
8125 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8126
8127 This works great except that the output assembler ends
8128 up looking a bit weird if it turns out that there is
8129 no offset. You end up producing code that looks like:
8130
8131 #APP
8132 movw $235,(%eax)
8133 movw %dx,2+(%eax)
8134 rorl $16,%edx
8135 movb %dl,4+(%eax)
8136 movb $137,5+(%eax)
8137 movb $0,6+(%eax)
8138 movb %dh,7+(%eax)
8139 rorl $16,%edx
8140 #NO_APP
8141
47926f60 8142 So here we provide the missing zero. */
24eab124
AM		 8143
8144 *displacement_string_end = '0';
252b5132
RH		 8145 }
8146#endif
c3320543
L		 8147 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types,
8148 (i.bnd_prefix != NULL
8149 || add_bnd_prefix));
f3c180ae
AM		 8150 if (gotfree_input_line)
8151 input_line_pointer = gotfree_input_line;
252b5132 8152
24eab124 8153 exp_seg = expression (exp);
252b5132 8154
636c26b0
AM		 8155 SKIP_WHITESPACE ();
8156 if (*input_line_pointer)
8157 as_bad (_("junk `%s' after expression"), input_line_pointer);
8158#if GCC_ASM_O_HACK
8159 RESTORE_END_STRING (disp_end + 1);
8160#endif
636c26b0 8161 input_line_pointer = save_input_line_pointer;
636c26b0 8162 if (gotfree_input_line)
ee86248c
JB		 8163 {
8164 free (gotfree_input_line);
8165
8166 if (exp->X_op == O_constant || exp->X_op == O_register)
8167 exp->X_op = O_illegal;
8168 }
8169
8170 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8171
8172 RESTORE_END_STRING (disp_end);
8173
8174 return ret;
8175}
8176
8177static int
8178i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8179 i386_operand_type types, const char *disp_start)
8180{
8181 i386_operand_type bigdisp;
8182 int ret = 1;
636c26b0 8183
24eab124
AM		 8184 /* We do this to make sure that the section symbol is in
8185 the symbol table. We will ultimately change the relocation
47926f60 8186 to be relative to the beginning of the section. */
1ae12ab7 8187 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8188 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8189 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8190 {
636c26b0 8191 if (exp->X_op != O_symbol)
3992d3b7 8192 goto inv_disp;
636c26b0 8193
e5cb08ac 8194 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8195 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8196 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8197 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8198 exp->X_op = O_subtract;
8199 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8200 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8201 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8202 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8203 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8204 else
29b0f896 8205 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8206 }
252b5132 8207
3992d3b7
AM		 8208 else if (exp->X_op == O_absent
8209 || exp->X_op == O_illegal
ee86248c 8210 || exp->X_op == O_big)
2daf4fd8 8211 {
3992d3b7
AM		 8212 inv_disp:
8213 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8214 disp_start);
3992d3b7 8215 ret = 0;
2daf4fd8
AM		 8216 }
8217
0e1147d9
L		 8218 else if (flag_code == CODE_64BIT
8219 && !i.prefix[ADDR_PREFIX]
8220 && exp->X_op == O_constant)
8221 {
8222 /* Since displacement is signed extended to 64bit, don't allow
8223 disp32 and turn off disp32s if they are out of range. */
8224 i.types[this_operand].bitfield.disp32 = 0;
8225 if (!fits_in_signed_long (exp->X_add_number))
8226 {
8227 i.types[this_operand].bitfield.disp32s = 0;
8228 if (i.types[this_operand].bitfield.baseindex)
8229 {
8230 as_bad (_("0x%lx out range of signed 32bit displacement"),
8231 (long) exp->X_add_number);
8232 ret = 0;
8233 }
8234 }
8235 }
8236
4c63da97 8237#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8238 else if (exp->X_op != O_constant
8239 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8240 && exp_seg != absolute_section
8241 && exp_seg != text_section
8242 && exp_seg != data_section
8243 && exp_seg != bss_section
8244 && exp_seg != undefined_section
8245 && !bfd_is_com_section (exp_seg))
24eab124 8246 {
d0b47220 8247 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8248 ret = 0;
24eab124 8249 }
252b5132 8250#endif
3956db08 8251
40fb9820
L		 8252 /* Check if this is a displacement only operand. */
8253 bigdisp = i.types[this_operand];
8254 bigdisp.bitfield.disp8 = 0;
8255 bigdisp.bitfield.disp16 = 0;
8256 bigdisp.bitfield.disp32 = 0;
8257 bigdisp.bitfield.disp32s = 0;
8258 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8259 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8260 i.types[this_operand] = operand_type_and (i.types[this_operand],
8261 types);
3956db08 8262
3992d3b7 8263 return ret;
252b5132
RH		 8264}
8265
eecb386c 8266/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8267 Return 1 on success, 0 on a failure. */
8268
252b5132 8269static int
e3bb37b5 8270i386_index_check (const char *operand_string)
252b5132 8271{
fc0763e6 8272 const char *kind = "base/index";
be05d201
L		 8273 enum flag_code addr_mode;
8274
8275 if (i.prefix[ADDR_PREFIX])
8276 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8277 else
8278 {
8279 addr_mode = flag_code;
8280
24eab124 8281#if INFER_ADDR_PREFIX
be05d201
L		 8282 if (i.mem_operands == 0)
8283 {
8284 /* Infer address prefix from the first memory operand. */
8285 const reg_entry *addr_reg = i.base_reg;
8286
8287 if (addr_reg == NULL)
8288 addr_reg = i.index_reg;
eecb386c 8289
be05d201
L		 8290 if (addr_reg)
8291 {
8292 if (addr_reg->reg_num == RegEip
8293 || addr_reg->reg_num == RegEiz
8294 || addr_reg->reg_type.bitfield.reg32)
8295 addr_mode = CODE_32BIT;
8296 else if (flag_code != CODE_64BIT
8297 && addr_reg->reg_type.bitfield.reg16)
8298 addr_mode = CODE_16BIT;
8299
8300 if (addr_mode != flag_code)
8301 {
8302 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8303 i.prefixes += 1;
8304 /* Change the size of any displacement too. At most one
8305 of Disp16 or Disp32 is set.
8306 FIXME. There doesn't seem to be any real need for
8307 separate Disp16 and Disp32 flags. The same goes for
8308 Imm16 and Imm32. Removing them would probably clean
8309 up the code quite a lot. */
8310 if (flag_code != CODE_64BIT
8311 && (i.types[this_operand].bitfield.disp16
8312 || i.types[this_operand].bitfield.disp32))
8313 i.types[this_operand]
8314 = operand_type_xor (i.types[this_operand], disp16_32);
8315 }
8316 }
8317 }
24eab124 8318#endif
be05d201
L		 8319 }
8320
fc0763e6
JB		 8321 if (current_templates->start->opcode_modifier.isstring
8322 && !current_templates->start->opcode_modifier.immext
8323 && (current_templates->end[-1].opcode_modifier.isstring
8324 || i.mem_operands))
8325 {
8326 /* Memory operands of string insns are special in that they only allow
8327 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8328 const reg_entry *expected_reg;
8329 static const char *di_si[][2] =
8330 {
8331 { "esi", "edi" },
8332 { "si", "di" },
8333 { "rsi", "rdi" }
8334 };
8335 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8336
8337 kind = "string address";
8338
8339 if (current_templates->start->opcode_modifier.w)
8340 {
8341 i386_operand_type type = current_templates->end[-1].operand_types[0];
8342
8343 if (!type.bitfield.baseindex
8344 || ((!i.mem_operands != !intel_syntax)
8345 && current_templates->end[-1].operand_types[1]
8346 .bitfield.baseindex))
8347 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8348 expected_reg = hash_find (reg_hash,
8349 di_si[addr_mode][type.bitfield.esseg]);
8350
fc0763e6
JB		 8351 }
8352 else
be05d201 8353 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8354
be05d201
L		 8355 if (i.base_reg != expected_reg
8356 || i.index_reg
fc0763e6 8357 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8358 {
be05d201
L		 8359 /* The second memory operand must have the same size as
8360 the first one. */
8361 if (i.mem_operands
8362 && i.base_reg
8363 && !((addr_mode == CODE_64BIT
8364 && i.base_reg->reg_type.bitfield.reg64)
8365 || (addr_mode == CODE_32BIT
8366 ? i.base_reg->reg_type.bitfield.reg32
8367 : i.base_reg->reg_type.bitfield.reg16)))
8368 goto bad_address;
8369
fc0763e6
JB		 8370 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8371 operand_string,
8372 intel_syntax ? '[' : '(',
8373 register_prefix,
be05d201 8374 expected_reg->reg_name,
fc0763e6 8375 intel_syntax ? ']' : ')');
be05d201 8376 return 1;
fc0763e6 8377 }
be05d201
L		 8378 else
8379 return 1;
8380
8381bad_address:
8382 as_bad (_("`%s' is not a valid %s expression"),
8383 operand_string, kind);
8384 return 0;
3e73aa7c
JH		 8385 }
8386 else
8387 {
be05d201
L		 8388 if (addr_mode != CODE_16BIT)
8389 {
8390 /* 32-bit/64-bit checks. */
8391 if ((i.base_reg
8392 && (addr_mode == CODE_64BIT
8393 ? !i.base_reg->reg_type.bitfield.reg64
8394 : !i.base_reg->reg_type.bitfield.reg32)
8395 && (i.index_reg
8396 || (i.base_reg->reg_num
8397 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8398 || (i.index_reg
8399 && !i.index_reg->reg_type.bitfield.regxmm
8400 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8401 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8402 && ((addr_mode == CODE_64BIT
8403 ? !(i.index_reg->reg_type.bitfield.reg64
8404 || i.index_reg->reg_num == RegRiz)
8405 : !(i.index_reg->reg_type.bitfield.reg32
8406 || i.index_reg->reg_num == RegEiz))
8407 || !i.index_reg->reg_type.bitfield.baseindex)))
8408 goto bad_address;
8409 }
8410 else
3e73aa7c 8411 {
be05d201 8412 /* 16-bit checks. */
3e73aa7c 8413 if ((i.base_reg
40fb9820
L		 8414 && (!i.base_reg->reg_type.bitfield.reg16
8415 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8416 || (i.index_reg
40fb9820
L		 8417 && (!i.index_reg->reg_type.bitfield.reg16
8418 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8419 || !(i.base_reg
8420 && i.base_reg->reg_num < 6
8421 && i.index_reg->reg_num >= 6
8422 && i.log2_scale_factor == 0))))
be05d201 8423 goto bad_address;
3e73aa7c
JH		 8424 }
8425 }
be05d201 8426 return 1;
24eab124 8427}
252b5132 8428
43234a1e
L		 8429/* Handle vector immediates. */
8430
8431static int
8432RC_SAE_immediate (const char *imm_start)
8433{
8434 unsigned int match_found, j;
8435 const char *pstr = imm_start;
8436 expressionS *exp;
8437
8438 if (*pstr != '{')
8439 return 0;
8440
8441 pstr++;
8442 match_found = 0;
8443 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8444 {
8445 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8446 {
8447 if (!i.rounding)
8448 {
8449 rc_op.type = RC_NamesTable[j].type;
8450 rc_op.operand = this_operand;
8451 i.rounding = &rc_op;
8452 }
8453 else
8454 {
8455 as_bad (_("duplicated `%s'"), imm_start);
8456 return 0;
8457 }
8458 pstr += RC_NamesTable[j].len;
8459 match_found = 1;
8460 break;
8461 }
8462 }
8463 if (!match_found)
8464 return 0;
8465
8466 if (*pstr++ != '}')
8467 {
8468 as_bad (_("Missing '}': '%s'"), imm_start);
8469 return 0;
8470 }
8471 /* RC/SAE immediate string should contain nothing more. */;
8472 if (*pstr != 0)
8473 {
8474 as_bad (_("Junk after '}': '%s'"), imm_start);
8475 return 0;
8476 }
8477
8478 exp = &im_expressions[i.imm_operands++];
8479 i.op[this_operand].imms = exp;
8480
8481 exp->X_op = O_constant;
8482 exp->X_add_number = 0;
8483 exp->X_add_symbol = (symbolS *) 0;
8484 exp->X_op_symbol = (symbolS *) 0;
8485
8486 i.types[this_operand].bitfield.imm8 = 1;
8487 return 1;
8488}
8489
fc0763e6 8490/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8491 on error. */
252b5132 8492
252b5132 8493static int
a7619375 8494i386_att_operand (char *operand_string)
252b5132 8495{
af6bdddf
AM		 8496 const reg_entry *r;
8497 char *end_op;
24eab124 8498 char *op_string = operand_string;
252b5132 8499
24eab124 8500 if (is_space_char (*op_string))
252b5132
RH		 8501 ++op_string;
8502
24eab124 8503 /* We check for an absolute prefix (differentiating,
47926f60 8504 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8505 if (*op_string == ABSOLUTE_PREFIX)
8506 {
8507 ++op_string;
8508 if (is_space_char (*op_string))
8509 ++op_string;
40fb9820 8510 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8511 }
252b5132 8512
47926f60 8513 /* Check if operand is a register. */
4d1bb795 8514 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8515 {
40fb9820
L		 8516 i386_operand_type temp;
8517
24eab124
AM		 8518 /* Check for a segment override by searching for ':' after a
8519 segment register. */
8520 op_string = end_op;
8521 if (is_space_char (*op_string))
8522 ++op_string;
40fb9820
L		 8523 if (*op_string == ':'
8524 && (r->reg_type.bitfield.sreg2
8525 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8526 {
8527 switch (r->reg_num)
8528 {
8529 case 0:
8530 i.seg[i.mem_operands] = &es;
8531 break;
8532 case 1:
8533 i.seg[i.mem_operands] = &cs;
8534 break;
8535 case 2:
8536 i.seg[i.mem_operands] = &ss;
8537 break;
8538 case 3:
8539 i.seg[i.mem_operands] = &ds;
8540 break;
8541 case 4:
8542 i.seg[i.mem_operands] = &fs;
8543 break;
8544 case 5:
8545 i.seg[i.mem_operands] = &gs;
8546 break;
8547 }
252b5132 8548
24eab124 8549 /* Skip the ':' and whitespace. */
252b5132
RH		 8550 ++op_string;
8551 if (is_space_char (*op_string))
24eab124 8552 ++op_string;
252b5132 8553
24eab124
AM		 8554 if (!is_digit_char (*op_string)
8555 && !is_identifier_char (*op_string)
8556 && *op_string != '('
8557 && *op_string != ABSOLUTE_PREFIX)
8558 {
8559 as_bad (_("bad memory operand `%s'"), op_string);
8560 return 0;
8561 }
47926f60 8562 /* Handle case of %es:*foo. */
24eab124
AM		 8563 if (*op_string == ABSOLUTE_PREFIX)
8564 {
8565 ++op_string;
8566 if (is_space_char (*op_string))
8567 ++op_string;
40fb9820 8568 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8569 }
8570 goto do_memory_reference;
8571 }
43234a1e
L		 8572
8573 /* Handle vector operations. */
8574 if (*op_string == '{')
8575 {
8576 op_string = check_VecOperations (op_string, NULL);
8577 if (op_string == NULL)
8578 return 0;
8579 }
8580
24eab124
AM		 8581 if (*op_string)
8582 {
d0b47220 8583 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8584 return 0;
8585 }
40fb9820
L		 8586 temp = r->reg_type;
8587 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8588 i.types[this_operand] = operand_type_or (i.types[this_operand],
8589 temp);
7d5e4556 8590 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8591 i.op[this_operand].regs = r;
24eab124
AM		 8592 i.reg_operands++;
8593 }
af6bdddf
AM		 8594 else if (*op_string == REGISTER_PREFIX)
8595 {
8596 as_bad (_("bad register name `%s'"), op_string);
8597 return 0;
8598 }
24eab124 8599 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8600 {
24eab124 8601 ++op_string;
40fb9820 8602 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8603 {
d0b47220 8604 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8605 return 0;
8606 }
8607 if (!i386_immediate (op_string))
8608 return 0;
8609 }
43234a1e
L		 8610 else if (RC_SAE_immediate (operand_string))
8611 {
8612 /* If it is a RC or SAE immediate, do nothing. */
8613 ;
8614 }
24eab124
AM		 8615 else if (is_digit_char (*op_string)
8616 || is_identifier_char (*op_string)
e5cb08ac 8617 || *op_string == '(')
24eab124 8618 {
47926f60 8619 /* This is a memory reference of some sort. */
af6bdddf 8620 char *base_string;
252b5132 8621
47926f60 8622 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8623 char *displacement_string_start;
8624 char *displacement_string_end;
43234a1e 8625 char *vop_start;
252b5132 8626
24eab124 8627 do_memory_reference:
24eab124 8628 if ((i.mem_operands == 1
40fb9820 8629 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8630 || i.mem_operands == 2)
8631 {
8632 as_bad (_("too many memory references for `%s'"),
8633 current_templates->start->name);
8634 return 0;
8635 }
252b5132 8636
24eab124
AM		 8637 /* Check for base index form. We detect the base index form by
8638 looking for an ')' at the end of the operand, searching
8639 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8640 after the '('. */
af6bdddf 8641 base_string = op_string + strlen (op_string);
c3332e24 8642
43234a1e
L		 8643 /* Handle vector operations. */
8644 vop_start = strchr (op_string, '{');
8645 if (vop_start && vop_start < base_string)
8646 {
8647 if (check_VecOperations (vop_start, base_string) == NULL)
8648 return 0;
8649 base_string = vop_start;
8650 }
8651
af6bdddf
AM		 8652 --base_string;
8653 if (is_space_char (*base_string))
8654 --base_string;
252b5132 8655
47926f60 8656 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8657 displacement_string_start = op_string;
8658 displacement_string_end = base_string + 1;
252b5132 8659
24eab124
AM		 8660 if (*base_string == ')')
8661 {
af6bdddf 8662 char *temp_string;
24eab124
AM		 8663 unsigned int parens_balanced = 1;
8664 /* We've already checked that the number of left & right ()'s are
47926f60 8665 equal, so this loop will not be infinite. */
24eab124
AM		 8666 do
8667 {
8668 base_string--;
8669 if (*base_string == ')')
8670 parens_balanced++;
8671 if (*base_string == '(')
8672 parens_balanced--;
8673 }
8674 while (parens_balanced);
c3332e24 8675
af6bdddf 8676 temp_string = base_string;
c3332e24 8677
24eab124 8678 /* Skip past '(' and whitespace. */
252b5132
RH		 8679 ++base_string;
8680 if (is_space_char (*base_string))
24eab124 8681 ++base_string;
252b5132 8682
af6bdddf 8683 if (*base_string == ','
4eed87de
AM		 8684 || ((i.base_reg = parse_register (base_string, &end_op))
8685 != NULL))
252b5132 8686 {
af6bdddf 8687 displacement_string_end = temp_string;
252b5132 8688
40fb9820 8689 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8690
af6bdddf 8691 if (i.base_reg)
24eab124 8692 {
24eab124
AM		 8693 base_string = end_op;
8694 if (is_space_char (*base_string))
8695 ++base_string;
af6bdddf
AM		 8696 }
8697
8698 /* There may be an index reg or scale factor here. */
8699 if (*base_string == ',')
8700 {
8701 ++base_string;
8702 if (is_space_char (*base_string))
8703 ++base_string;
8704
4eed87de
AM		 8705 if ((i.index_reg = parse_register (base_string, &end_op))
8706 != NULL)
24eab124 8707 {
af6bdddf 8708 base_string = end_op;
24eab124
AM		 8709 if (is_space_char (*base_string))
8710 ++base_string;
af6bdddf
AM		 8711 if (*base_string == ',')
8712 {
8713 ++base_string;
8714 if (is_space_char (*base_string))
8715 ++base_string;
8716 }
e5cb08ac 8717 else if (*base_string != ')')
af6bdddf 8718 {
4eed87de
AM		 8719 as_bad (_("expecting `,' or `)' "
8720 "after index register in `%s'"),
af6bdddf
AM		 8721 operand_string);
8722 return 0;
8723 }
24eab124 8724 }
af6bdddf 8725 else if (*base_string == REGISTER_PREFIX)
24eab124 8726 {
f76bf5e0
L		 8727 end_op = strchr (base_string, ',');
8728 if (end_op)
8729 *end_op = '\0';
af6bdddf 8730 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8731 return 0;
8732 }
252b5132 8733
47926f60 8734 /* Check for scale factor. */
551c1ca1 8735 if (*base_string != ')')
af6bdddf 8736 {
551c1ca1
AM		 8737 char *end_scale = i386_scale (base_string);
8738
8739 if (!end_scale)
af6bdddf 8740 return 0;
24eab124 8741
551c1ca1 8742 base_string = end_scale;
af6bdddf
AM		 8743 if (is_space_char (*base_string))
8744 ++base_string;
8745 if (*base_string != ')')
8746 {
4eed87de
AM		 8747 as_bad (_("expecting `)' "
8748 "after scale factor in `%s'"),
af6bdddf
AM		 8749 operand_string);
8750 return 0;
8751 }
8752 }
8753 else if (!i.index_reg)
24eab124 8754 {
4eed87de
AM		 8755 as_bad (_("expecting index register or scale factor "
8756 "after `,'; got '%c'"),
af6bdddf 8757 *base_string);
24eab124
AM		 8758 return 0;
8759 }
8760 }
af6bdddf 8761 else if (*base_string != ')')
24eab124 8762 {
4eed87de
AM		 8763 as_bad (_("expecting `,' or `)' "
8764 "after base register in `%s'"),
af6bdddf 8765 operand_string);
24eab124
AM		 8766 return 0;
8767 }
c3332e24 8768 }
af6bdddf 8769 else if (*base_string == REGISTER_PREFIX)
c3332e24 8770 {
f76bf5e0
L		 8771 end_op = strchr (base_string, ',');
8772 if (end_op)
8773 *end_op = '\0';
af6bdddf 8774 as_bad (_("bad register name `%s'"), base_string);
24eab124 8775 return 0;
c3332e24 8776 }
24eab124
AM		 8777 }
8778
8779 /* If there's an expression beginning the operand, parse it,
8780 assuming displacement_string_start and
8781 displacement_string_end are meaningful. */
8782 if (displacement_string_start != displacement_string_end)
8783 {
8784 if (!i386_displacement (displacement_string_start,
8785 displacement_string_end))
8786 return 0;
8787 }
8788
8789 /* Special case for (%dx) while doing input/output op. */
8790 if (i.base_reg
0dfbf9d7
L		 8791 && operand_type_equal (&i.base_reg->reg_type,
8792 &reg16_inoutportreg)
24eab124
AM		 8793 && i.index_reg == 0
8794 && i.log2_scale_factor == 0
8795 && i.seg[i.mem_operands] == 0
40fb9820 8796 && !operand_type_check (i.types[this_operand], disp))
24eab124 8797 {
65da13b5 8798 i.types[this_operand] = inoutportreg;
24eab124
AM		 8799 return 1;
8800 }
8801
eecb386c
AM		 8802 if (i386_index_check (operand_string) == 0)
8803 return 0;
5c07affc 8804 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 8805 i.mem_operands++;
8806 }
8807 else
ce8a8b2f
AM		 8808 {
8809 /* It's not a memory operand; argh! */
24eab124
AM		 8810 as_bad (_("invalid char %s beginning operand %d `%s'"),
8811 output_invalid (*op_string),
8812 this_operand + 1,
8813 op_string);
8814 return 0;
8815 }
47926f60 8816 return 1; /* Normal return. */
252b5132
RH		 8817}
8818\f
fa94de6b
RM		 8819/* Calculate the maximum variable size (i.e., excluding fr_fix)
8820 that an rs_machine_dependent frag may reach. */
8821
8822unsigned int
8823i386_frag_max_var (fragS *frag)
8824{
8825 /* The only relaxable frags are for jumps.
8826 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8827 gas_assert (frag->fr_type == rs_machine_dependent);
8828 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8829}
8830
ee7fcc42
AM		 8831/* md_estimate_size_before_relax()
8832
8833 Called just before relax() for rs_machine_dependent frags. The x86
8834 assembler uses these frags to handle variable size jump
8835 instructions.
8836
8837 Any symbol that is now undefined will not become defined.
8838 Return the correct fr_subtype in the frag.
8839 Return the initial "guess for variable size of frag" to caller.
8840 The guess is actually the growth beyond the fixed part. Whatever
8841 we do to grow the fixed or variable part contributes to our
8842 returned value. */
8843
252b5132 8844int
7016a5d5 8845md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 8846{
252b5132 8847 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 8848 check for un-relaxable symbols. On an ELF system, we can't relax
8849 an externally visible symbol, because it may be overridden by a
8850 shared library. */
8851 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 8852#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8853 || (IS_ELF
31312f95 8854 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 8855 || S_IS_WEAK (fragP->fr_symbol)
8856 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
8857 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 8858#endif
8859#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 8860 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 8861 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 8862#endif
8863 )
252b5132 8864 {
b98ef147
AM		 8865 /* Symbol is undefined in this segment, or we need to keep a
8866 reloc so that weak symbols can be overridden. */
8867 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 8868 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 8869 unsigned char *opcode;
8870 int old_fr_fix;
f6af82bd 8871
ee7fcc42 8872 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 8873 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 8874 else if (size == 2)
f6af82bd
AM		 8875 reloc_type = BFD_RELOC_16_PCREL;
8876 else
8877 reloc_type = BFD_RELOC_32_PCREL;
252b5132 8878
ee7fcc42
AM		 8879 old_fr_fix = fragP->fr_fix;
8880 opcode = (unsigned char *) fragP->fr_opcode;
8881
fddf5b5b 8882 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 8883 {
fddf5b5b
AM		 8884 case UNCOND_JUMP:
8885 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 8886 opcode[0] = 0xe9;
252b5132 8887 fragP->fr_fix += size;
062cd5e7
AS		 8888 fix_new (fragP, old_fr_fix, size,
8889 fragP->fr_symbol,
8890 fragP->fr_offset, 1,
8891 reloc_type);
252b5132
RH		 8892 break;
8893
fddf5b5b 8894 case COND_JUMP86:
412167cb
AM		 8895 if (size == 2
8896 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 8897 {
8898 /* Negate the condition, and branch past an
8899 unconditional jump. */
8900 opcode[0] ^= 1;
8901 opcode[1] = 3;
8902 /* Insert an unconditional jump. */
8903 opcode[2] = 0xe9;
8904 /* We added two extra opcode bytes, and have a two byte
8905 offset. */
8906 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 8907 fix_new (fragP, old_fr_fix + 2, 2,
8908 fragP->fr_symbol,
8909 fragP->fr_offset, 1,
8910 reloc_type);
fddf5b5b
AM		 8911 break;
8912 }
8913 /* Fall through. */
8914
8915 case COND_JUMP:
412167cb
AM		 8916 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
8917 {
3e02c1cc
AM		 8918 fixS *fixP;
8919
412167cb 8920 fragP->fr_fix += 1;
3e02c1cc
AM		 8921 fixP = fix_new (fragP, old_fr_fix, 1,
8922 fragP->fr_symbol,
8923 fragP->fr_offset, 1,
8924 BFD_RELOC_8_PCREL);
8925 fixP->fx_signed = 1;
412167cb
AM		 8926 break;
8927 }
93c2a809 8928
24eab124 8929 /* This changes the byte-displacement jump 0x7N
fddf5b5b 8930 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 8931 opcode[1] = opcode[0] + 0x10;
f6af82bd 8932 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 8933 /* We've added an opcode byte. */
8934 fragP->fr_fix += 1 + size;
062cd5e7
AS		 8935 fix_new (fragP, old_fr_fix + 1, size,
8936 fragP->fr_symbol,
8937 fragP->fr_offset, 1,
8938 reloc_type);
252b5132 8939 break;
fddf5b5b
AM		 8940
8941 default:
8942 BAD_CASE (fragP->fr_subtype);
8943 break;
252b5132
RH		 8944 }
8945 frag_wane (fragP);
ee7fcc42 8946 return fragP->fr_fix - old_fr_fix;
252b5132 8947 }
93c2a809 8948
93c2a809
AM		 8949 /* Guess size depending on current relax state. Initially the relax
8950 state will correspond to a short jump and we return 1, because
8951 the variable part of the frag (the branch offset) is one byte
8952 long. However, we can relax a section more than once and in that
8953 case we must either set fr_subtype back to the unrelaxed state,
8954 or return the value for the appropriate branch. */
8955 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 8956}
8957
47926f60
KH		 8958/* Called after relax() is finished.
8959
8960 In: Address of frag.
8961 fr_type == rs_machine_dependent.
8962 fr_subtype is what the address relaxed to.
8963
8964 Out: Any fixSs and constants are set up.
8965 Caller will turn frag into a ".space 0". */
8966
252b5132 8967void
7016a5d5
TG		 8968md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
8969 fragS *fragP)
252b5132 8970{
29b0f896 8971 unsigned char *opcode;
252b5132 8972 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 8973 offsetT target_address;
8974 offsetT opcode_address;
252b5132 8975 unsigned int extension = 0;
847f7ad4 8976 offsetT displacement_from_opcode_start;
252b5132
RH		 8977
8978 opcode = (unsigned char *) fragP->fr_opcode;
8979
47926f60 8980 /* Address we want to reach in file space. */
252b5132 8981 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 8982
47926f60 8983 /* Address opcode resides at in file space. */
252b5132
RH		 8984 opcode_address = fragP->fr_address + fragP->fr_fix;
8985
47926f60 8986 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 8987 displacement_from_opcode_start = target_address - opcode_address;
8988
fddf5b5b 8989 if ((fragP->fr_subtype & BIG) == 0)
252b5132 8990 {
47926f60
KH		 8991 /* Don't have to change opcode. */
8992 extension = 1; /* 1 opcode + 1 displacement */
252b5132 8993 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 8994 }
8995 else
8996 {
8997 if (no_cond_jump_promotion
8998 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 8999 as_warn_where (fragP->fr_file, fragP->fr_line,
9000 _("long jump required"));
252b5132 9001
fddf5b5b
AM		 9002 switch (fragP->fr_subtype)
9003 {
9004 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9005 extension = 4; /* 1 opcode + 4 displacement */
9006 opcode[0] = 0xe9;
9007 where_to_put_displacement = &opcode[1];
9008 break;
252b5132 9009
fddf5b5b
AM		 9010 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9011 extension = 2; /* 1 opcode + 2 displacement */
9012 opcode[0] = 0xe9;
9013 where_to_put_displacement = &opcode[1];
9014 break;
252b5132 9015
fddf5b5b
AM		 9016 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9017 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9018 extension = 5; /* 2 opcode + 4 displacement */
9019 opcode[1] = opcode[0] + 0x10;
9020 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9021 where_to_put_displacement = &opcode[2];
9022 break;
252b5132 9023
fddf5b5b
AM		 9024 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9025 extension = 3; /* 2 opcode + 2 displacement */
9026 opcode[1] = opcode[0] + 0x10;
9027 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9028 where_to_put_displacement = &opcode[2];
9029 break;
252b5132 9030
fddf5b5b
AM		 9031 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9032 extension = 4;
9033 opcode[0] ^= 1;
9034 opcode[1] = 3;
9035 opcode[2] = 0xe9;
9036 where_to_put_displacement = &opcode[3];
9037 break;
9038
9039 default:
9040 BAD_CASE (fragP->fr_subtype);
9041 break;
9042 }
252b5132 9043 }
fddf5b5b 9044
7b81dfbb
AJ		 9045 /* If size if less then four we are sure that the operand fits,
9046 but if it's 4, then it could be that the displacement is larger
9047 then -/+ 2GB. */
9048 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9049 && object_64bit
9050 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9051 + ((addressT) 1 << 31))
9052 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9053 {
9054 as_bad_where (fragP->fr_file, fragP->fr_line,
9055 _("jump target out of range"));
9056 /* Make us emit 0. */
9057 displacement_from_opcode_start = extension;
9058 }
47926f60 9059 /* Now put displacement after opcode. */
252b5132
RH		 9060 md_number_to_chars ((char *) where_to_put_displacement,
9061 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9062 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9063 fragP->fr_fix += extension;
9064}
9065\f
7016a5d5 9066/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9067 by our caller that we have all the info we need to fix it up.
9068
7016a5d5
TG		 9069 Parameter valP is the pointer to the value of the bits.
9070
252b5132
RH		 9071 On the 386, immediates, displacements, and data pointers are all in
9072 the same (little-endian) format, so we don't need to care about which
9073 we are handling. */
9074
94f592af 9075void
7016a5d5 9076md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9077{
94f592af 9078 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9079 valueT value = *valP;
252b5132 9080
f86103b7 9081#if !defined (TE_Mach)
93382f6d
AM		 9082 if (fixP->fx_pcrel)
9083 {
9084 switch (fixP->fx_r_type)
9085 {
5865bb77
ILT		 9086 default:
9087 break;
9088
d6ab8113
JB		 9089 case BFD_RELOC_64:
9090 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9091 break;
93382f6d 9092 case BFD_RELOC_32:
ae8887b5 9093 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9094 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9095 break;
9096 case BFD_RELOC_16:
9097 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9098 break;
9099 case BFD_RELOC_8:
9100 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9101 break;
9102 }
9103 }
252b5132 9104
a161fe53 9105 if (fixP->fx_addsy != NULL
31312f95 9106 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9107 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9108 || fixP->fx_r_type == BFD_RELOC_16_PCREL
c3320543
L		 9109 || fixP->fx_r_type == BFD_RELOC_8_PCREL
9110 || fixP->fx_r_type == BFD_RELOC_X86_64_PC32_BND)
31312f95 9111 && !use_rela_relocations)
252b5132 9112 {
31312f95
AM		 9113 /* This is a hack. There should be a better way to handle this.
9114 This covers for the fact that bfd_install_relocation will
9115 subtract the current location (for partial_inplace, PC relative
9116 relocations); see more below. */
252b5132 9117#ifndef OBJ_AOUT
718ddfc0 9118 if (IS_ELF
252b5132
RH		 9119#ifdef TE_PE
9120 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9121#endif
9122 )
9123 value += fixP->fx_where + fixP->fx_frag->fr_address;
9124#endif
9125#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9126 if (IS_ELF)
252b5132 9127 {
6539b54b 9128 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9129
6539b54b 9130 if ((sym_seg == seg
2f66722d 9131 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9132 && sym_seg != absolute_section))
af65af87 9133 && !generic_force_reloc (fixP))
2f66722d
AM		 9134 {
9135 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9136 bfd_install_relocation subtracts them out again. I think
9137 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9138 it. FIXME. */
9139 value += fixP->fx_where + fixP->fx_frag->fr_address;
9140 }
252b5132
RH		 9141 }
9142#endif
9143#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9144 /* For some reason, the PE format does not store a
9145 section address offset for a PC relative symbol. */
9146 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9147 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9148 value += md_pcrel_from (fixP);
9149#endif
9150 }
fbeb56a4 9151#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9152 if (fixP->fx_addsy != NULL
9153 && S_IS_WEAK (fixP->fx_addsy)
9154 /* PR 16858: Do not modify weak function references. */
9155 && ! fixP->fx_pcrel)
fbeb56a4 9156 {
296a8689
NC		 9157#if !defined (TE_PEP)
9158 /* For x86 PE weak function symbols are neither PC-relative
9159 nor do they set S_IS_FUNCTION. So the only reliable way
9160 to detect them is to check the flags of their containing
9161 section. */
9162 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9163 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9164 ;
9165 else
9166#endif
fbeb56a4
DK		 9167 value -= S_GET_VALUE (fixP->fx_addsy);
9168 }
9169#endif
252b5132
RH		 9170
9171 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9172 and we must not disappoint it. */
252b5132 9173#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9174 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9175 switch (fixP->fx_r_type)
9176 {
9177 case BFD_RELOC_386_PLT32:
3e73aa7c 9178 case BFD_RELOC_X86_64_PLT32:
c3320543 9179 case BFD_RELOC_X86_64_PLT32_BND:
47926f60
KH		 9180 /* Make the jump instruction point to the address of the operand. At
9181 runtime we merely add the offset to the actual PLT entry. */
9182 value = -4;
9183 break;
31312f95 9184
13ae64f3
JJ		 9185 case BFD_RELOC_386_TLS_GD:
9186 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9187 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9188 case BFD_RELOC_386_TLS_IE:
9189 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9190 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9191 case BFD_RELOC_X86_64_TLSGD:
9192 case BFD_RELOC_X86_64_TLSLD:
9193 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9194 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9195 value = 0; /* Fully resolved at runtime. No addend. */
9196 /* Fallthrough */
9197 case BFD_RELOC_386_TLS_LE:
9198 case BFD_RELOC_386_TLS_LDO_32:
9199 case BFD_RELOC_386_TLS_LE_32:
9200 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9201 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9202 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9203 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9204 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9205 break;
9206
67a4f2b7
AO		 9207 case BFD_RELOC_386_TLS_DESC_CALL:
9208 case BFD_RELOC_X86_64_TLSDESC_CALL:
9209 value = 0; /* Fully resolved at runtime. No addend. */
9210 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9211 fixP->fx_done = 0;
9212 return;
9213
00f7efb6
JJ		 9214 case BFD_RELOC_386_GOT32:
9215 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 9216 value = 0; /* Fully resolved at runtime. No addend. */
9217 break;
47926f60
KH		 9218
9219 case BFD_RELOC_VTABLE_INHERIT:
9220 case BFD_RELOC_VTABLE_ENTRY:
9221 fixP->fx_done = 0;
94f592af 9222 return;
47926f60
KH		 9223
9224 default:
9225 break;
9226 }
9227#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9228 *valP = value;
f86103b7 9229#endif /* !defined (TE_Mach) */
3e73aa7c 9230
3e73aa7c 9231 /* Are we finished with this relocation now? */
c6682705 9232 if (fixP->fx_addsy == NULL)
3e73aa7c 9233 fixP->fx_done = 1;
fbeb56a4
DK		 9234#if defined (OBJ_COFF) && defined (TE_PE)
9235 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9236 {
9237 fixP->fx_done = 0;
9238 /* Remember value for tc_gen_reloc. */
9239 fixP->fx_addnumber = value;
9240 /* Clear out the frag for now. */
9241 value = 0;
9242 }
9243#endif
3e73aa7c
JH		 9244 else if (use_rela_relocations)
9245 {
9246 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9247 /* Remember value for tc_gen_reloc. */
9248 fixP->fx_addnumber = value;
3e73aa7c
JH		 9249 value = 0;
9250 }
f86103b7 9251
94f592af 9252 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9253}
252b5132 9254\f
252b5132 9255char *
499ac353 9256md_atof (int type, char *litP, int *sizeP)
252b5132 9257{
499ac353
NC		 9258 /* This outputs the LITTLENUMs in REVERSE order;
9259 in accord with the bigendian 386. */
9260 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9261}
9262\f
2d545b82 9263static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9264
252b5132 9265static char *
e3bb37b5 9266output_invalid (int c)
252b5132 9267{
3882b010 9268 if (ISPRINT (c))
f9f21a03
L		 9269 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9270 "'%c'", c);
252b5132 9271 else
f9f21a03 9272 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9273 "(0x%x)", (unsigned char) c);
252b5132
RH		 9274 return output_invalid_buf;
9275}
9276
af6bdddf 9277/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9278
9279static const reg_entry *
4d1bb795 9280parse_real_register (char *reg_string, char **end_op)
252b5132 9281{
af6bdddf
AM		 9282 char *s = reg_string;
9283 char *p;
252b5132
RH		 9284 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9285 const reg_entry *r;
9286
9287 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9288 if (*s == REGISTER_PREFIX)
9289 ++s;
9290
9291 if (is_space_char (*s))
9292 ++s;
9293
9294 p = reg_name_given;
af6bdddf 9295 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9296 {
9297 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9298 return (const reg_entry *) NULL;
9299 s++;
252b5132
RH		 9300 }
9301
6588847e
DN		 9302 /* For naked regs, make sure that we are not dealing with an identifier.
9303 This prevents confusing an identifier like `eax_var' with register
9304 `eax'. */
9305 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9306 return (const reg_entry *) NULL;
9307
af6bdddf 9308 *end_op = s;
252b5132
RH		 9309
9310 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9311
5f47d35b 9312 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9313 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9314 {
5f47d35b
AM		 9315 if (is_space_char (*s))
9316 ++s;
9317 if (*s == '(')
9318 {
af6bdddf 9319 ++s;
5f47d35b
AM		 9320 if (is_space_char (*s))
9321 ++s;
9322 if (*s >= '0' && *s <= '7')
9323 {
db557034 9324 int fpr = *s - '0';
af6bdddf 9325 ++s;
5f47d35b
AM		 9326 if (is_space_char (*s))
9327 ++s;
9328 if (*s == ')')
9329 {
9330 *end_op = s + 1;
1e9cc1c2 9331 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9332 know (r);
9333 return r + fpr;
5f47d35b 9334 }
5f47d35b 9335 }
47926f60 9336 /* We have "%st(" then garbage. */
5f47d35b
AM		 9337 return (const reg_entry *) NULL;
9338 }
9339 }
9340
a60de03c
JB		 9341 if (r == NULL || allow_pseudo_reg)
9342 return r;
9343
0dfbf9d7 9344 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9345 return (const reg_entry *) NULL;
9346
192dc9c6
JB		 9347 if ((r->reg_type.bitfield.reg32
9348 || r->reg_type.bitfield.sreg3
9349 || r->reg_type.bitfield.control
9350 || r->reg_type.bitfield.debug
9351 || r->reg_type.bitfield.test)
9352 && !cpu_arch_flags.bitfield.cpui386)
9353 return (const reg_entry *) NULL;
9354
309d3373
JB		 9355 if (r->reg_type.bitfield.floatreg
9356 && !cpu_arch_flags.bitfield.cpu8087
9357 && !cpu_arch_flags.bitfield.cpu287
9358 && !cpu_arch_flags.bitfield.cpu387)
9359 return (const reg_entry *) NULL;
9360
192dc9c6
JB		 9361 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9362 return (const reg_entry *) NULL;
9363
9364 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9365 return (const reg_entry *) NULL;
9366
40f12533
L		 9367 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9368 return (const reg_entry *) NULL;
9369
43234a1e
L		 9370 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9371 && !cpu_arch_flags.bitfield.cpuavx512f)
9372 return (const reg_entry *) NULL;
9373
db51cc60 9374 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9375 if (!allow_index_reg
db51cc60
L		 9376 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9377 return (const reg_entry *) NULL;
9378
43234a1e
L		 9379 /* Upper 16 vector register is only available with VREX in 64bit
9380 mode. */
9381 if ((r->reg_flags & RegVRex))
9382 {
9383 if (!cpu_arch_flags.bitfield.cpuvrex
9384 || flag_code != CODE_64BIT)
9385 return (const reg_entry *) NULL;
9386
9387 i.need_vrex = 1;
9388 }
9389
a60de03c
JB		 9390 if (((r->reg_flags & (RegRex64 | RegRex))
9391 || r->reg_type.bitfield.reg64)
40fb9820 9392 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9393 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9394 && flag_code != CODE_64BIT)
20f0a1fc 9395 return (const reg_entry *) NULL;
1ae00879 9396
b7240065
JB		 9397 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9398 return (const reg_entry *) NULL;
9399
252b5132
RH		 9400 return r;
9401}
4d1bb795
JB		 9402
9403/* REG_STRING starts *before* REGISTER_PREFIX. */
9404
9405static const reg_entry *
9406parse_register (char *reg_string, char **end_op)
9407{
9408 const reg_entry *r;
9409
9410 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9411 r = parse_real_register (reg_string, end_op);
9412 else
9413 r = NULL;
9414 if (!r)
9415 {
9416 char *save = input_line_pointer;
9417 char c;
9418 symbolS *symbolP;
9419
9420 input_line_pointer = reg_string;
9421 c = get_symbol_end ();
9422 symbolP = symbol_find (reg_string);
9423 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9424 {
9425 const expressionS *e = symbol_get_value_expression (symbolP);
9426
0398aac5 9427 know (e->X_op == O_register);
4eed87de 9428 know (e->X_add_number >= 0
c3fe08fa 9429 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 9430 r = i386_regtab + e->X_add_number;
9431 *end_op = input_line_pointer;
9432 }
9433 *input_line_pointer = c;
9434 input_line_pointer = save;
9435 }
9436 return r;
9437}
9438
9439int
9440i386_parse_name (char *name, expressionS *e, char *nextcharP)
9441{
9442 const reg_entry *r;
9443 char *end = input_line_pointer;
9444
9445 *end = *nextcharP;
9446 r = parse_register (name, &input_line_pointer);
9447 if (r && end <= input_line_pointer)
9448 {
9449 *nextcharP = *input_line_pointer;
9450 *input_line_pointer = 0;
9451 e->X_op = O_register;
9452 e->X_add_number = r - i386_regtab;
9453 return 1;
9454 }
9455 input_line_pointer = end;
9456 *end = 0;
ee86248c 9457 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9458}
9459
9460void
9461md_operand (expressionS *e)
9462{
ee86248c
JB		 9463 char *end;
9464 const reg_entry *r;
4d1bb795 9465
ee86248c
JB		 9466 switch (*input_line_pointer)
9467 {
9468 case REGISTER_PREFIX:
9469 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9470 if (r)
9471 {
9472 e->X_op = O_register;
9473 e->X_add_number = r - i386_regtab;
9474 input_line_pointer = end;
9475 }
ee86248c
JB		 9476 break;
9477
9478 case '[':
9c2799c2 9479 gas_assert (intel_syntax);
ee86248c
JB		 9480 end = input_line_pointer++;
9481 expression (e);
9482 if (*input_line_pointer == ']')
9483 {
9484 ++input_line_pointer;
9485 e->X_op_symbol = make_expr_symbol (e);
9486 e->X_add_symbol = NULL;
9487 e->X_add_number = 0;
9488 e->X_op = O_index;
9489 }
9490 else
9491 {
9492 e->X_op = O_absent;
9493 input_line_pointer = end;
9494 }
9495 break;
4d1bb795
JB		 9496 }
9497}
9498
252b5132 9499\f
4cc782b5 9500#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9501const char *md_shortopts = "kVQ:sqn";
252b5132 9502#else
12b55ccc 9503const char *md_shortopts = "qn";
252b5132 9504#endif
6e0b89ee 9505
3e73aa7c 9506#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9507#define OPTION_64 (OPTION_MD_BASE + 1)
9508#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9509#define OPTION_MARCH (OPTION_MD_BASE + 3)
9510#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9511#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9512#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9513#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9514#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9515#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9516#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9517#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9518#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9519#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9520#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9521#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9522#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9523#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9524#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
b3b91714 9525
99ad8390
NC		 9526struct option md_longopts[] =
9527{
3e73aa7c 9528 {"32", no_argument, NULL, OPTION_32},
321098a5 9529#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9530 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9531 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9532#endif
9533#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9534 {"x32", no_argument, NULL, OPTION_X32},
6e0b89ee 9535#endif
b3b91714 9536 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9537 {"march", required_argument, NULL, OPTION_MARCH},
9538 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9539 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9540 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9541 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9542 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9543 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9544 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9545 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9546 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9547 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9548 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9549 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9550 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9551# if defined (TE_PE) || defined (TE_PEP)
9552 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9553#endif
252b5132
RH		 9554 {NULL, no_argument, NULL, 0}
9555};
9556size_t md_longopts_size = sizeof (md_longopts);
9557
9558int
9103f4f4 9559md_parse_option (int c, char *arg)
252b5132 9560{
91d6fa6a 9561 unsigned int j;
6305a203 9562 char *arch, *next;
9103f4f4 9563
252b5132
RH		 9564 switch (c)
9565 {
12b55ccc
L		 9566 case 'n':
9567 optimize_align_code = 0;
9568 break;
9569
a38cf1db
AM		 9570 case 'q':
9571 quiet_warnings = 1;
252b5132
RH		 9572 break;
9573
9574#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9575 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9576 should be emitted or not. FIXME: Not implemented. */
9577 case 'Q':
252b5132
RH		 9578 break;
9579
9580 /* -V: SVR4 argument to print version ID. */
9581 case 'V':
9582 print_version_id ();
9583 break;
9584
a38cf1db
AM		 9585 /* -k: Ignore for FreeBSD compatibility. */
9586 case 'k':
252b5132 9587 break;
4cc782b5
ILT		 9588
9589 case 's':
9590 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9591 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9592 break;
99ad8390 9593#endif
321098a5 9594#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9595 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9596 case OPTION_64:
9597 {
9598 const char **list, **l;
9599
3e73aa7c
JH		 9600 list = bfd_target_list ();
9601 for (l = list; *l != NULL; l++)
8620418b 9602 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9603 || strcmp (*l, "coff-x86-64") == 0
9604 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9605 || strcmp (*l, "pei-x86-64") == 0
9606 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9607 {
9608 default_arch = "x86_64";
9609 break;
9610 }
3e73aa7c 9611 if (*l == NULL)
2b5d6a91 9612 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9613 free (list);
9614 }
9615 break;
9616#endif
252b5132 9617
351f65ca 9618#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9619 case OPTION_X32:
351f65ca
L		 9620 if (IS_ELF)
9621 {
9622 const char **list, **l;
9623
9624 list = bfd_target_list ();
9625 for (l = list; *l != NULL; l++)
9626 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9627 {
9628 default_arch = "x86_64:32";
9629 break;
9630 }
9631 if (*l == NULL)
2b5d6a91 9632 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9633 free (list);
9634 }
9635 else
9636 as_fatal (_("32bit x86_64 is only supported for ELF"));
9637 break;
9638#endif
9639
6e0b89ee
AM		 9640 case OPTION_32:
9641 default_arch = "i386";
9642 break;
9643
b3b91714
AM		 9644 case OPTION_DIVIDE:
9645#ifdef SVR4_COMMENT_CHARS
9646 {
9647 char *n, *t;
9648 const char *s;
9649
9650 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
9651 t = n;
9652 for (s = i386_comment_chars; *s != '\0'; s++)
9653 if (*s != '/')
9654 *t++ = *s;
9655 *t = '\0';
9656 i386_comment_chars = n;
9657 }
9658#endif
9659 break;
9660
9103f4f4 9661 case OPTION_MARCH:
6305a203
L		 9662 arch = xstrdup (arg);
9663 do
9103f4f4 9664 {
6305a203 9665 if (*arch == '.')
2b5d6a91 9666 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9667 next = strchr (arch, '+');
9668 if (next)
9669 *next++ = '\0';
91d6fa6a 9670 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9671 {
91d6fa6a 9672 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9673 {
6305a203 9674 /* Processor. */
1ded5609
JB		 9675 if (! cpu_arch[j].flags.bitfield.cpui386)
9676 continue;
9677
91d6fa6a 9678 cpu_arch_name = cpu_arch[j].name;
6305a203 9679 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9680 cpu_arch_flags = cpu_arch[j].flags;
9681 cpu_arch_isa = cpu_arch[j].type;
9682 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9683 if (!cpu_arch_tune_set)
9684 {
9685 cpu_arch_tune = cpu_arch_isa;
9686 cpu_arch_tune_flags = cpu_arch_isa_flags;
9687 }
9688 break;
9689 }
91d6fa6a
NC		 9690 else if (*cpu_arch [j].name == '.'
9691 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9692 {
9693 /* ISA entension. */
9694 i386_cpu_flags flags;
309d3373 9695
49021df2 9696 if (!cpu_arch[j].negated)
309d3373 9697 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 9698 cpu_arch[j].flags);
309d3373
JB		 9699 else
9700 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 9701 cpu_arch[j].flags);
0dfbf9d7 9702 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 9703 {
9704 if (cpu_sub_arch_name)
9705 {
9706 char *name = cpu_sub_arch_name;
9707 cpu_sub_arch_name = concat (name,
91d6fa6a 9708 cpu_arch[j].name,
1bf57e9f 9709 (const char *) NULL);
6305a203
L		 9710 free (name);
9711 }
9712 else
91d6fa6a 9713 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 9714 cpu_arch_flags = flags;
a586129e 9715 cpu_arch_isa_flags = flags;
6305a203
L		 9716 }
9717 break;
ccc9c027 9718 }
9103f4f4 9719 }
6305a203 9720
91d6fa6a 9721 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9722 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9723
9724 arch = next;
9103f4f4 9725 }
6305a203 9726 while (next != NULL );
9103f4f4
L		 9727 break;
9728
9729 case OPTION_MTUNE:
9730 if (*arg == '.')
2b5d6a91 9731 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 9732 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9733 {
91d6fa6a 9734 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 9735 {
ccc9c027 9736 cpu_arch_tune_set = 1;
91d6fa6a
NC		 9737 cpu_arch_tune = cpu_arch [j].type;
9738 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 9739 break;
9740 }
9741 }
91d6fa6a 9742 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9743 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 9744 break;
9745
1efbbeb4
L		 9746 case OPTION_MMNEMONIC:
9747 if (strcasecmp (arg, "att") == 0)
9748 intel_mnemonic = 0;
9749 else if (strcasecmp (arg, "intel") == 0)
9750 intel_mnemonic = 1;
9751 else
2b5d6a91 9752 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 9753 break;
9754
9755 case OPTION_MSYNTAX:
9756 if (strcasecmp (arg, "att") == 0)
9757 intel_syntax = 0;
9758 else if (strcasecmp (arg, "intel") == 0)
9759 intel_syntax = 1;
9760 else
2b5d6a91 9761 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 9762 break;
9763
9764 case OPTION_MINDEX_REG:
9765 allow_index_reg = 1;
9766 break;
9767
9768 case OPTION_MNAKED_REG:
9769 allow_naked_reg = 1;
9770 break;
9771
9772 case OPTION_MOLD_GCC:
9773 old_gcc = 1;
1efbbeb4
L		 9774 break;
9775
c0f3af97
L		 9776 case OPTION_MSSE2AVX:
9777 sse2avx = 1;
9778 break;
9779
daf50ae7
L		 9780 case OPTION_MSSE_CHECK:
9781 if (strcasecmp (arg, "error") == 0)
7bab8ab5 9782 sse_check = check_error;
daf50ae7 9783 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 9784 sse_check = check_warning;
daf50ae7 9785 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 9786 sse_check = check_none;
daf50ae7 9787 else
2b5d6a91 9788 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 9789 break;
9790
7bab8ab5
JB		 9791 case OPTION_MOPERAND_CHECK:
9792 if (strcasecmp (arg, "error") == 0)
9793 operand_check = check_error;
9794 else if (strcasecmp (arg, "warning") == 0)
9795 operand_check = check_warning;
9796 else if (strcasecmp (arg, "none") == 0)
9797 operand_check = check_none;
9798 else
9799 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
9800 break;
9801
539f890d
L		 9802 case OPTION_MAVXSCALAR:
9803 if (strcasecmp (arg, "128") == 0)
9804 avxscalar = vex128;
9805 else if (strcasecmp (arg, "256") == 0)
9806 avxscalar = vex256;
9807 else
2b5d6a91 9808 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 9809 break;
9810
7e8b059b
L		 9811 case OPTION_MADD_BND_PREFIX:
9812 add_bnd_prefix = 1;
9813 break;
9814
43234a1e
L		 9815 case OPTION_MEVEXLIG:
9816 if (strcmp (arg, "128") == 0)
9817 evexlig = evexl128;
9818 else if (strcmp (arg, "256") == 0)
9819 evexlig = evexl256;
9820 else if (strcmp (arg, "512") == 0)
9821 evexlig = evexl512;
9822 else
9823 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
9824 break;
9825
9826 case OPTION_MEVEXWIG:
9827 if (strcmp (arg, "0") == 0)
9828 evexwig = evexw0;
9829 else if (strcmp (arg, "1") == 0)
9830 evexwig = evexw1;
9831 else
9832 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
9833 break;
9834
167ad85b
TG		 9835# if defined (TE_PE) || defined (TE_PEP)
9836 case OPTION_MBIG_OBJ:
9837 use_big_obj = 1;
9838 break;
9839#endif
9840
252b5132
RH		 9841 default:
9842 return 0;
9843 }
9844 return 1;
9845}
9846
8a2c8fef
L		 9847#define MESSAGE_TEMPLATE \
9848" "
9849
9850static void
1ded5609 9851show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 9852{
9853 static char message[] = MESSAGE_TEMPLATE;
9854 char *start = message + 27;
9855 char *p;
9856 int size = sizeof (MESSAGE_TEMPLATE);
9857 int left;
9858 const char *name;
9859 int len;
9860 unsigned int j;
9861
9862 p = start;
9863 left = size - (start - message);
9864 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9865 {
9866 /* Should it be skipped? */
9867 if (cpu_arch [j].skip)
9868 continue;
9869
9870 name = cpu_arch [j].name;
9871 len = cpu_arch [j].len;
9872 if (*name == '.')
9873 {
9874 /* It is an extension. Skip if we aren't asked to show it. */
9875 if (ext)
9876 {
9877 name++;
9878 len--;
9879 }
9880 else
9881 continue;
9882 }
9883 else if (ext)
9884 {
9885 /* It is an processor. Skip if we show only extension. */
9886 continue;
9887 }
1ded5609
JB		 9888 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
9889 {
9890 /* It is an impossible processor - skip. */
9891 continue;
9892 }
8a2c8fef
L		 9893
9894 /* Reserve 2 spaces for ", " or ",\0" */
9895 left -= len + 2;
9896
9897 /* Check if there is any room. */
9898 if (left >= 0)
9899 {
9900 if (p != start)
9901 {
9902 *p++ = ',';
9903 *p++ = ' ';
9904 }
9905 p = mempcpy (p, name, len);
9906 }
9907 else
9908 {
9909 /* Output the current message now and start a new one. */
9910 *p++ = ',';
9911 *p = '\0';
9912 fprintf (stream, "%s\n", message);
9913 p = start;
9914 left = size - (start - message) - len - 2;
8d63c93e 9915
8a2c8fef
L		 9916 gas_assert (left >= 0);
9917
9918 p = mempcpy (p, name, len);
9919 }
9920 }
9921
9922 *p = '\0';
9923 fprintf (stream, "%s\n", message);
9924}
9925
252b5132 9926void
8a2c8fef 9927md_show_usage (FILE *stream)
252b5132 9928{
4cc782b5
ILT		 9929#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9930 fprintf (stream, _("\
a38cf1db
AM		 9931 -Q ignored\n\
9932 -V print assembler version number\n\
b3b91714
AM		 9933 -k ignored\n"));
9934#endif
9935 fprintf (stream, _("\
12b55ccc 9936 -n Do not optimize code alignment\n\
b3b91714
AM		 9937 -q quieten some warnings\n"));
9938#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9939 fprintf (stream, _("\
a38cf1db 9940 -s ignored\n"));
b3b91714 9941#endif
321098a5
L		 9942#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9943 || defined (TE_PE) || defined (TE_PEP))
751d281c 9944 fprintf (stream, _("\
570561f7 9945 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 9946#endif
b3b91714
AM		 9947#ifdef SVR4_COMMENT_CHARS
9948 fprintf (stream, _("\
9949 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 9950#else
9951 fprintf (stream, _("\
b3b91714 9952 --divide ignored\n"));
4cc782b5 9953#endif
9103f4f4 9954 fprintf (stream, _("\
6305a203 9955 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 9956 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 9957 show_arch (stream, 0, 1);
8a2c8fef
L		 9958 fprintf (stream, _("\
9959 EXTENSION is combination of:\n"));
1ded5609 9960 show_arch (stream, 1, 0);
6305a203 9961 fprintf (stream, _("\
8a2c8fef 9962 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 9963 show_arch (stream, 0, 0);
ba104c83 9964 fprintf (stream, _("\
c0f3af97
L		 9965 -msse2avx encode SSE instructions with VEX prefix\n"));
9966 fprintf (stream, _("\
daf50ae7
L		 9967 -msse-check=[none|error|warning]\n\
9968 check SSE instructions\n"));
9969 fprintf (stream, _("\
7bab8ab5
JB		 9970 -moperand-check=[none|error|warning]\n\
9971 check operand combinations for validity\n"));
9972 fprintf (stream, _("\
539f890d
L		 9973 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
9974 length\n"));
9975 fprintf (stream, _("\
43234a1e
L		 9976 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
9977 length\n"));
9978 fprintf (stream, _("\
9979 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
9980 for EVEX.W bit ignored instructions\n"));
9981 fprintf (stream, _("\
ba104c83
L		 9982 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
9983 fprintf (stream, _("\
9984 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
9985 fprintf (stream, _("\
9986 -mindex-reg support pseudo index registers\n"));
9987 fprintf (stream, _("\
9988 -mnaked-reg don't require `%%' prefix for registers\n"));
9989 fprintf (stream, _("\
9990 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 9991 fprintf (stream, _("\
9992 -madd-bnd-prefix add BND prefix for all valid branches\n"));
167ad85b
TG		 9993# if defined (TE_PE) || defined (TE_PEP)
9994 fprintf (stream, _("\
9995 -mbig-obj generate big object files\n"));
9996#endif
252b5132
RH		 9997}
9998
3e73aa7c 9999#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10000 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10001 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10002
10003/* Pick the target format to use. */
10004
47926f60 10005const char *
e3bb37b5 10006i386_target_format (void)
252b5132 10007{
351f65ca
L		 10008 if (!strncmp (default_arch, "x86_64", 6))
10009 {
10010 update_code_flag (CODE_64BIT, 1);
10011 if (default_arch[6] == '\0')
7f56bc95 10012 x86_elf_abi = X86_64_ABI;
351f65ca 10013 else
7f56bc95 10014 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10015 }
3e73aa7c 10016 else if (!strcmp (default_arch, "i386"))
78f12dd3 10017 update_code_flag (CODE_32BIT, 1);
3e73aa7c 10018 else
2b5d6a91 10019 as_fatal (_("unknown architecture"));
89507696
JB		 10020
10021 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10022 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10023 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10024 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10025
252b5132
RH		 10026 switch (OUTPUT_FLAVOR)
10027 {
9384f2ff 10028#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10029 case bfd_target_aout_flavour:
47926f60 10030 return AOUT_TARGET_FORMAT;
4c63da97 10031#endif
9384f2ff
AM		 10032#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10033# if defined (TE_PE) || defined (TE_PEP)
10034 case bfd_target_coff_flavour:
167ad85b
TG		 10035 if (flag_code == CODE_64BIT)
10036 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10037 else
10038 return "pe-i386";
9384f2ff 10039# elif defined (TE_GO32)
0561d57c
JK		 10040 case bfd_target_coff_flavour:
10041 return "coff-go32";
9384f2ff 10042# else
252b5132
RH		 10043 case bfd_target_coff_flavour:
10044 return "coff-i386";
9384f2ff 10045# endif
4c63da97 10046#endif
3e73aa7c 10047#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10048 case bfd_target_elf_flavour:
3e73aa7c 10049 {
351f65ca
L		 10050 const char *format;
10051
10052 switch (x86_elf_abi)
4fa24527 10053 {
351f65ca
L		 10054 default:
10055 format = ELF_TARGET_FORMAT;
10056 break;
7f56bc95 10057 case X86_64_ABI:
351f65ca 10058 use_rela_relocations = 1;
4fa24527 10059 object_64bit = 1;
351f65ca
L		 10060 format = ELF_TARGET_FORMAT64;
10061 break;
7f56bc95 10062 case X86_64_X32_ABI:
4fa24527 10063 use_rela_relocations = 1;
351f65ca 10064 object_64bit = 1;
862be3fb 10065 disallow_64bit_reloc = 1;
351f65ca
L		 10066 format = ELF_TARGET_FORMAT32;
10067 break;
4fa24527 10068 }
3632d14b 10069 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10070 {
7f56bc95 10071 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10072 as_fatal (_("Intel L1OM is 64bit only"));
10073 return ELF_TARGET_L1OM_FORMAT;
10074 }
7a9068fe
L		 10075 if (cpu_arch_isa == PROCESSOR_K1OM)
10076 {
10077 if (x86_elf_abi != X86_64_ABI)
10078 as_fatal (_("Intel K1OM is 64bit only"));
10079 return ELF_TARGET_K1OM_FORMAT;
10080 }
8a9036a4 10081 else
351f65ca 10082 return format;
3e73aa7c 10083 }
e57f8c65
TG		 10084#endif
10085#if defined (OBJ_MACH_O)
10086 case bfd_target_mach_o_flavour:
d382c579
TG		 10087 if (flag_code == CODE_64BIT)
10088 {
10089 use_rela_relocations = 1;
10090 object_64bit = 1;
10091 return "mach-o-x86-64";
10092 }
10093 else
10094 return "mach-o-i386";
4c63da97 10095#endif
252b5132
RH		 10096 default:
10097 abort ();
10098 return NULL;
10099 }
10100}
10101
47926f60 10102#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 10103
10104#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 10105void
10106i386_elf_emit_arch_note (void)
a847613f 10107{
718ddfc0 10108 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 10109 {
10110 char *p;
10111 asection *seg = now_seg;
10112 subsegT subseg = now_subseg;
10113 Elf_Internal_Note i_note;
10114 Elf_External_Note e_note;
10115 asection *note_secp;
10116 int len;
10117
10118 /* Create the .note section. */
10119 note_secp = subseg_new (".note", 0);
10120 bfd_set_section_flags (stdoutput,
10121 note_secp,
10122 SEC_HAS_CONTENTS | SEC_READONLY);
10123
10124 /* Process the arch string. */
10125 len = strlen (cpu_arch_name);
10126
10127 i_note.namesz = len + 1;
10128 i_note.descsz = 0;
10129 i_note.type = NT_ARCH;
10130 p = frag_more (sizeof (e_note.namesz));
10131 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
10132 p = frag_more (sizeof (e_note.descsz));
10133 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
10134 p = frag_more (sizeof (e_note.type));
10135 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
10136 p = frag_more (len + 1);
10137 strcpy (p, cpu_arch_name);
10138
10139 frag_align (2, 0, 0);
10140
10141 subseg_set (seg, subseg);
10142 }
10143}
10144#endif
252b5132 10145\f
252b5132 10146symbolS *
7016a5d5 10147md_undefined_symbol (char *name)
252b5132 10148{
18dc2407
ILT		 10149 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10150 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10151 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10152 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10153 {
10154 if (!GOT_symbol)
10155 {
10156 if (symbol_find (name))
10157 as_bad (_("GOT already in symbol table"));
10158 GOT_symbol = symbol_new (name, undefined_section,
10159 (valueT) 0, &zero_address_frag);
10160 };
10161 return GOT_symbol;
10162 }
252b5132
RH		 10163 return 0;
10164}
10165
10166/* Round up a section size to the appropriate boundary. */
47926f60 10167
252b5132 10168valueT
7016a5d5 10169md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10170{
4c63da97
AM		 10171#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10172 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10173 {
10174 /* For a.out, force the section size to be aligned. If we don't do
10175 this, BFD will align it for us, but it will not write out the
10176 final bytes of the section. This may be a bug in BFD, but it is
10177 easier to fix it here since that is how the other a.out targets
10178 work. */
10179 int align;
10180
10181 align = bfd_get_section_alignment (stdoutput, segment);
10182 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
10183 }
252b5132
RH		 10184#endif
10185
10186 return size;
10187}
10188
10189/* On the i386, PC-relative offsets are relative to the start of the
10190 next instruction. That is, the address of the offset, plus its
10191 size, since the offset is always the last part of the insn. */
10192
10193long
e3bb37b5 10194md_pcrel_from (fixS *fixP)
252b5132
RH		 10195{
10196 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10197}
10198
10199#ifndef I386COFF
10200
10201static void
e3bb37b5 10202s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10203{
29b0f896 10204 int temp;
252b5132 10205
8a75718c
JB		 10206#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10207 if (IS_ELF)
10208 obj_elf_section_change_hook ();
10209#endif
252b5132
RH		 10210 temp = get_absolute_expression ();
10211 subseg_set (bss_section, (subsegT) temp);
10212 demand_empty_rest_of_line ();
10213}
10214
10215#endif
10216
252b5132 10217void
e3bb37b5 10218i386_validate_fix (fixS *fixp)
252b5132
RH		 10219{
10220 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
10221 {
23df1078
JH		 10222 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10223 {
4fa24527 10224 if (!object_64bit)
23df1078
JH		 10225 abort ();
10226 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10227 }
10228 else
10229 {
4fa24527 10230 if (!object_64bit)
d6ab8113
JB		 10231 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10232 else
10233 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 10234 }
252b5132
RH		 10235 fixp->fx_subsy = 0;
10236 }
10237}
10238
252b5132 10239arelent *
7016a5d5 10240tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10241{
10242 arelent *rel;
10243 bfd_reloc_code_real_type code;
10244
10245 switch (fixp->fx_r_type)
10246 {
8ce3d284 10247#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10248 case BFD_RELOC_SIZE32:
10249 case BFD_RELOC_SIZE64:
10250 if (S_IS_DEFINED (fixp->fx_addsy)
10251 && !S_IS_EXTERNAL (fixp->fx_addsy))
10252 {
10253 /* Resolve size relocation against local symbol to size of
10254 the symbol plus addend. */
10255 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10256 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10257 && !fits_in_unsigned_long (value))
10258 as_bad_where (fixp->fx_file, fixp->fx_line,
10259 _("symbol size computation overflow"));
10260 fixp->fx_addsy = NULL;
10261 fixp->fx_subsy = NULL;
10262 md_apply_fix (fixp, (valueT *) &value, NULL);
10263 return NULL;
10264 }
8ce3d284 10265#endif
8fd4256d 10266
3e73aa7c 10267 case BFD_RELOC_X86_64_PLT32:
c3320543 10268 case BFD_RELOC_X86_64_PLT32_BND:
3e73aa7c
JH		 10269 case BFD_RELOC_X86_64_GOT32:
10270 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 10271 case BFD_RELOC_386_PLT32:
10272 case BFD_RELOC_386_GOT32:
10273 case BFD_RELOC_386_GOTOFF:
10274 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10275 case BFD_RELOC_386_TLS_GD:
10276 case BFD_RELOC_386_TLS_LDM:
10277 case BFD_RELOC_386_TLS_LDO_32:
10278 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10279 case BFD_RELOC_386_TLS_IE:
10280 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10281 case BFD_RELOC_386_TLS_LE_32:
10282 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10283 case BFD_RELOC_386_TLS_GOTDESC:
10284 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10285 case BFD_RELOC_X86_64_TLSGD:
10286 case BFD_RELOC_X86_64_TLSLD:
10287 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10288 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10289 case BFD_RELOC_X86_64_GOTTPOFF:
10290 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10291 case BFD_RELOC_X86_64_TPOFF64:
10292 case BFD_RELOC_X86_64_GOTOFF64:
10293 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10294 case BFD_RELOC_X86_64_GOT64:
10295 case BFD_RELOC_X86_64_GOTPCREL64:
10296 case BFD_RELOC_X86_64_GOTPC64:
10297 case BFD_RELOC_X86_64_GOTPLT64:
10298 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10299 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10300 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10301 case BFD_RELOC_RVA:
10302 case BFD_RELOC_VTABLE_ENTRY:
10303 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10304#ifdef TE_PE
10305 case BFD_RELOC_32_SECREL:
10306#endif
252b5132
RH		 10307 code = fixp->fx_r_type;
10308 break;
dbbaec26
L		 10309 case BFD_RELOC_X86_64_32S:
10310 if (!fixp->fx_pcrel)
10311 {
10312 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10313 code = fixp->fx_r_type;
10314 break;
10315 }
252b5132 10316 default:
93382f6d 10317 if (fixp->fx_pcrel)
252b5132 10318 {
93382f6d
AM		 10319 switch (fixp->fx_size)
10320 {
10321 default:
b091f402
AM		 10322 as_bad_where (fixp->fx_file, fixp->fx_line,
10323 _("can not do %d byte pc-relative relocation"),
10324 fixp->fx_size);
93382f6d
AM		 10325 code = BFD_RELOC_32_PCREL;
10326 break;
10327 case 1: code = BFD_RELOC_8_PCREL; break;
10328 case 2: code = BFD_RELOC_16_PCREL; break;
c3320543
L		 10329 case 4:
10330 code = (fixp->fx_r_type == BFD_RELOC_X86_64_PC32_BND
10331 ? fixp-> fx_r_type : BFD_RELOC_32_PCREL);
10332 break;
d6ab8113
JB		 10333#ifdef BFD64
10334 case 8: code = BFD_RELOC_64_PCREL; break;
10335#endif
93382f6d
AM		 10336 }
10337 }
10338 else
10339 {
10340 switch (fixp->fx_size)
10341 {
10342 default:
b091f402
AM		 10343 as_bad_where (fixp->fx_file, fixp->fx_line,
10344 _("can not do %d byte relocation"),
10345 fixp->fx_size);
93382f6d
AM		 10346 code = BFD_RELOC_32;
10347 break;
10348 case 1: code = BFD_RELOC_8; break;
10349 case 2: code = BFD_RELOC_16; break;
10350 case 4: code = BFD_RELOC_32; break;
937149dd 10351#ifdef BFD64
3e73aa7c 10352 case 8: code = BFD_RELOC_64; break;
937149dd 10353#endif
93382f6d 10354 }
252b5132
RH		 10355 }
10356 break;
10357 }
252b5132 10358
d182319b
JB		 10359 if ((code == BFD_RELOC_32
10360 || code == BFD_RELOC_32_PCREL
10361 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10362 && GOT_symbol
10363 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10364 {
4fa24527 10365 if (!object_64bit)
d6ab8113
JB		 10366 code = BFD_RELOC_386_GOTPC;
10367 else
10368 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10369 }
7b81dfbb
AJ		 10370 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10371 && GOT_symbol
10372 && fixp->fx_addsy == GOT_symbol)
10373 {
10374 code = BFD_RELOC_X86_64_GOTPC64;
10375 }
252b5132
RH		 10376
10377 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 10378 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10379 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10380
10381 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10382
3e73aa7c
JH		 10383 if (!use_rela_relocations)
10384 {
10385 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10386 vtable entry to be used in the relocation's section offset. */
10387 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10388 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10389#if defined (OBJ_COFF) && defined (TE_PE)
10390 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10391 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10392 else
10393#endif
c6682705 10394 rel->addend = 0;
3e73aa7c
JH		 10395 }
10396 /* Use the rela in 64bit mode. */
252b5132 10397 else
3e73aa7c 10398 {
862be3fb
L		 10399 if (disallow_64bit_reloc)
10400 switch (code)
10401 {
862be3fb
L		 10402 case BFD_RELOC_X86_64_DTPOFF64:
10403 case BFD_RELOC_X86_64_TPOFF64:
10404 case BFD_RELOC_64_PCREL:
10405 case BFD_RELOC_X86_64_GOTOFF64:
10406 case BFD_RELOC_X86_64_GOT64:
10407 case BFD_RELOC_X86_64_GOTPCREL64:
10408 case BFD_RELOC_X86_64_GOTPC64:
10409 case BFD_RELOC_X86_64_GOTPLT64:
10410 case BFD_RELOC_X86_64_PLTOFF64:
10411 as_bad_where (fixp->fx_file, fixp->fx_line,
10412 _("cannot represent relocation type %s in x32 mode"),
10413 bfd_get_reloc_code_name (code));
10414 break;
10415 default:
10416 break;
10417 }
10418
062cd5e7
AS		 10419 if (!fixp->fx_pcrel)
10420 rel->addend = fixp->fx_offset;
10421 else
10422 switch (code)
10423 {
10424 case BFD_RELOC_X86_64_PLT32:
c3320543 10425 case BFD_RELOC_X86_64_PLT32_BND:
062cd5e7
AS		 10426 case BFD_RELOC_X86_64_GOT32:
10427 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 10428 case BFD_RELOC_X86_64_TLSGD:
10429 case BFD_RELOC_X86_64_TLSLD:
10430 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10431 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10432 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10433 rel->addend = fixp->fx_offset - fixp->fx_size;
10434 break;
10435 default:
10436 rel->addend = (section->vma
10437 - fixp->fx_size
10438 + fixp->fx_addnumber
10439 + md_pcrel_from (fixp));
10440 break;
10441 }
3e73aa7c
JH		 10442 }
10443
252b5132
RH		 10444 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10445 if (rel->howto == NULL)
10446 {
10447 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10448 _("cannot represent relocation type %s"),
252b5132
RH		 10449 bfd_get_reloc_code_name (code));
10450 /* Set howto to a garbage value so that we can keep going. */
10451 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10452 gas_assert (rel->howto != NULL);
252b5132
RH		 10453 }
10454
10455 return rel;
10456}
10457
ee86248c 10458#include "tc-i386-intel.c"
54cfded0 10459
a60de03c
JB		 10460void
10461tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10462{
a60de03c
JB		 10463 int saved_naked_reg;
10464 char saved_register_dot;
54cfded0 10465
a60de03c
JB		 10466 saved_naked_reg = allow_naked_reg;
10467 allow_naked_reg = 1;
10468 saved_register_dot = register_chars['.'];
10469 register_chars['.'] = '.';
10470 allow_pseudo_reg = 1;
10471 expression_and_evaluate (exp);
10472 allow_pseudo_reg = 0;
10473 register_chars['.'] = saved_register_dot;
10474 allow_naked_reg = saved_naked_reg;
10475
e96d56a1 10476 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10477 {
a60de03c
JB		 10478 if ((addressT) exp->X_add_number < i386_regtab_size)
10479 {
10480 exp->X_op = O_constant;
10481 exp->X_add_number = i386_regtab[exp->X_add_number]
10482 .dw2_regnum[flag_code >> 1];
10483 }
10484 else
10485 exp->X_op = O_illegal;
54cfded0 10486 }
54cfded0
AM		 10487}
10488
10489void
10490tc_x86_frame_initial_instructions (void)
10491{
a60de03c
JB		 10492 static unsigned int sp_regno[2];
10493
10494 if (!sp_regno[flag_code >> 1])
10495 {
10496 char *saved_input = input_line_pointer;
10497 char sp[][4] = {"esp", "rsp"};
10498 expressionS exp;
a4447b93 10499
a60de03c
JB		 10500 input_line_pointer = sp[flag_code >> 1];
10501 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10502 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10503 sp_regno[flag_code >> 1] = exp.X_add_number;
10504 input_line_pointer = saved_input;
10505 }
a4447b93 10506
61ff971f
L		 10507 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10508 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10509}
d2b2c203 10510
d7921315
L		 10511int
10512x86_dwarf2_addr_size (void)
10513{
10514#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10515 if (x86_elf_abi == X86_64_X32_ABI)
10516 return 4;
10517#endif
10518 return bfd_arch_bits_per_address (stdoutput) / 8;
10519}
10520
d2b2c203
DJ		 10521int
10522i386_elf_section_type (const char *str, size_t len)
10523{
10524 if (flag_code == CODE_64BIT
10525 && len == sizeof ("unwind") - 1
10526 && strncmp (str, "unwind", 6) == 0)
10527 return SHT_X86_64_UNWIND;
10528
10529 return -1;
10530}
bb41ade5 10531
ad5fec3b
EB		 10532#ifdef TE_SOLARIS
10533void
10534i386_solaris_fix_up_eh_frame (segT sec)
10535{
10536 if (flag_code == CODE_64BIT)
10537 elf_section_type (sec) = SHT_X86_64_UNWIND;
10538}
10539#endif
10540
bb41ade5
AM		 10541#ifdef TE_PE
10542void
10543tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10544{
91d6fa6a 10545 expressionS exp;
bb41ade5 10546
91d6fa6a
NC		 10547 exp.X_op = O_secrel;
10548 exp.X_add_symbol = symbol;
10549 exp.X_add_number = 0;
10550 emit_expr (&exp, size);
bb41ade5
AM		 10551}
10552#endif
3b22753a
L		 10553
10554#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10555/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10556
01e1a5bc 10557bfd_vma
3b22753a
L		 10558x86_64_section_letter (int letter, char **ptr_msg)
10559{
10560 if (flag_code == CODE_64BIT)
10561 {
10562 if (letter == 'l')
10563 return SHF_X86_64_LARGE;
10564
8f3bae45 10565 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10566 }
3b22753a 10567 else
8f3bae45 10568 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10569 return -1;
10570}
10571
01e1a5bc 10572bfd_vma
3b22753a
L		 10573x86_64_section_word (char *str, size_t len)
10574{
8620418b 10575 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10576 return SHF_X86_64_LARGE;
10577
10578 return -1;
10579}
10580
10581static void
10582handle_large_common (int small ATTRIBUTE_UNUSED)
10583{
10584 if (flag_code != CODE_64BIT)
10585 {
10586 s_comm_internal (0, elf_common_parse);
10587 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10588 }
10589 else
10590 {
10591 static segT lbss_section;
10592 asection *saved_com_section_ptr = elf_com_section_ptr;
10593 asection *saved_bss_section = bss_section;
10594
10595 if (lbss_section == NULL)
10596 {
10597 flagword applicable;
10598 segT seg = now_seg;
10599 subsegT subseg = now_subseg;
10600
10601 /* The .lbss section is for local .largecomm symbols. */
10602 lbss_section = subseg_new (".lbss", 0);
10603 applicable = bfd_applicable_section_flags (stdoutput);
10604 bfd_set_section_flags (stdoutput, lbss_section,
10605 applicable & SEC_ALLOC);
10606 seg_info (lbss_section)->bss = 1;
10607
10608 subseg_set (seg, subseg);
10609 }
10610
10611 elf_com_section_ptr = &_bfd_elf_large_com_section;
10612 bss_section = lbss_section;
10613
10614 s_comm_internal (0, elf_common_parse);
10615
10616 elf_com_section_ptr = saved_com_section_ptr;
10617 bss_section = saved_bss_section;
10618 }
10619}
10620#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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