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This adjusts equate handling by
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
aef6203b 3 2000, 2001, 2002, 2003, 2004, 2005
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
252b5132 35#include "opcode/i386.h"
d2b2c203 36#include "elf/x86-64.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
29b0f896
AM		 66static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70static INLINE int fits_in_signed_word PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 73static int smallest_imm_type PARAMS ((offsetT));
74static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 75static int add_prefix PARAMS ((unsigned int));
3e73aa7c 76static void set_code_flag PARAMS ((int));
47926f60 77static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 78static void set_intel_syntax PARAMS ((int));
e413e4e9 79static void set_cpu_arch PARAMS ((int));
6482c264
NC		 80#ifdef TE_PE
81static void pe_directive_secrel PARAMS ((int));
82#endif
d182319b 83static void signed_cons PARAMS ((int));
29b0f896
AM		 84static char *output_invalid PARAMS ((int c));
85static int i386_operand PARAMS ((char *operand_string));
86static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
87static const reg_entry *parse_register PARAMS ((char *reg_string,
88 char **end_op));
89static char *parse_insn PARAMS ((char *, char *));
90static char *parse_operands PARAMS ((char *, const char *));
91static void swap_operands PARAMS ((void));
92static void optimize_imm PARAMS ((void));
93static void optimize_disp PARAMS ((void));
94static int match_template PARAMS ((void));
95static int check_string PARAMS ((void));
96static int process_suffix PARAMS ((void));
97static int check_byte_reg PARAMS ((void));
98static int check_long_reg PARAMS ((void));
99static int check_qword_reg PARAMS ((void));
100static int check_word_reg PARAMS ((void));
101static int finalize_imm PARAMS ((void));
102static int process_operands PARAMS ((void));
103static const seg_entry *build_modrm_byte PARAMS ((void));
104static void output_insn PARAMS ((void));
105static void output_branch PARAMS ((void));
106static void output_jump PARAMS ((void));
107static void output_interseg_jump PARAMS ((void));
2bbd9c25
JJ		 108static void output_imm PARAMS ((fragS *insn_start_frag,
109 offsetT insn_start_off));
110static void output_disp PARAMS ((fragS *insn_start_frag,
111 offsetT insn_start_off));
29b0f896
AM		 112#ifndef I386COFF
113static void s_bss PARAMS ((int));
252b5132 114#endif
17d4e2a2
L		 115#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
116static void handle_large_common (int small ATTRIBUTE_UNUSED);
117#endif
252b5132 118
a847613f 119static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 120
252b5132 121/* 'md_assemble ()' gathers together information and puts it into a
47926f60 122 i386_insn. */
252b5132 123
520dc8e8
AM		 124union i386_op
125 {
126 expressionS *disps;
127 expressionS *imms;
128 const reg_entry *regs;
129 };
130
252b5132
RH		 131struct _i386_insn
132 {
47926f60 133 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 134 template tm;
135
136 /* SUFFIX holds the instruction mnemonic suffix if given.
137 (e.g. 'l' for 'movl') */
138 char suffix;
139
47926f60 140 /* OPERANDS gives the number of given operands. */
252b5132
RH		 141 unsigned int operands;
142
143 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
144 of given register, displacement, memory operands and immediate
47926f60 145 operands. */
252b5132
RH		 146 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
147
148 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 149 use OP[i] for the corresponding operand. */
252b5132
RH		 150 unsigned int types[MAX_OPERANDS];
151
520dc8e8
AM		 152 /* Displacement expression, immediate expression, or register for each
153 operand. */
154 union i386_op op[MAX_OPERANDS];
252b5132 155
3e73aa7c
JH		 156 /* Flags for operands. */
157 unsigned int flags[MAX_OPERANDS];
158#define Operand_PCrel 1
159
252b5132 160 /* Relocation type for operand */
f86103b7 161 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 162
252b5132
RH		 163 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
164 the base index byte below. */
165 const reg_entry *base_reg;
166 const reg_entry *index_reg;
167 unsigned int log2_scale_factor;
168
169 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 170 explicit segment overrides are given. */
ce8a8b2f 171 const seg_entry *seg[2];
252b5132
RH		 172
173 /* PREFIX holds all the given prefix opcodes (usually null).
174 PREFIXES is the number of prefix opcodes. */
175 unsigned int prefixes;
176 unsigned char prefix[MAX_PREFIXES];
177
178 /* RM and SIB are the modrm byte and the sib byte where the
179 addressing modes of this insn are encoded. */
180
181 modrm_byte rm;
3e73aa7c 182 rex_byte rex;
252b5132
RH		 183 sib_byte sib;
184 };
185
186typedef struct _i386_insn i386_insn;
187
188/* List of chars besides those in app.c:symbol_chars that can start an
189 operand. Used to prevent the scrubber eating vital white-space. */
32137342 190const char extra_symbol_chars[] = "*%-(["
252b5132 191#ifdef LEX_AT
32137342
NC		 192 "@"
193#endif
194#ifdef LEX_QM
195 "?"
252b5132 196#endif
32137342 197 ;
252b5132 198
29b0f896
AM		 199#if (defined (TE_I386AIX) \
200 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
201 && !defined (TE_LINUX) \
32137342 202 && !defined (TE_NETWARE) \
29b0f896
AM		 203 && !defined (TE_FreeBSD) \
204 && !defined (TE_NetBSD)))
252b5132 205/* This array holds the chars that always start a comment. If the
ce8a8b2f 206 pre-processor is disabled, these aren't very useful. */
252b5132
RH		 207const char comment_chars[] = "#/";
208#define PREFIX_SEPARATOR '\\'
252b5132
RH		 209
210/* This array holds the chars that only start a comment at the beginning of
211 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 212 .line and .file directives will appear in the pre-processed output.
213 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 214 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 215 #NO_APP at the beginning of its output.
216 Also note that comments started like this one will always work if
252b5132 217 '/' isn't otherwise defined. */
0d9f6d04 218const char line_comment_chars[] = "#";
29b0f896 219
252b5132 220#else
29b0f896
AM		 221/* Putting '/' here makes it impossible to use the divide operator.
222 However, we need it for compatibility with SVR4 systems. */
223const char comment_chars[] = "#";
224#define PREFIX_SEPARATOR '/'
225
0d9f6d04 226const char line_comment_chars[] = "/#";
252b5132
RH		 227#endif
228
63a0b638 229const char line_separator_chars[] = ";";
252b5132 230
ce8a8b2f
AM		 231/* Chars that can be used to separate mant from exp in floating point
232 nums. */
252b5132
RH		 233const char EXP_CHARS[] = "eE";
234
ce8a8b2f
AM		 235/* Chars that mean this number is a floating point constant
236 As in 0f12.456
237 or 0d1.2345e12. */
252b5132
RH		 238const char FLT_CHARS[] = "fFdDxX";
239
ce8a8b2f 240/* Tables for lexical analysis. */
252b5132
RH		 241static char mnemonic_chars[256];
242static char register_chars[256];
243static char operand_chars[256];
244static char identifier_chars[256];
245static char digit_chars[256];
246
ce8a8b2f 247/* Lexical macros. */
252b5132
RH		 248#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
249#define is_operand_char(x) (operand_chars[(unsigned char) x])
250#define is_register_char(x) (register_chars[(unsigned char) x])
251#define is_space_char(x) ((x) == ' ')
252#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
253#define is_digit_char(x) (digit_chars[(unsigned char) x])
254
0234cb7c 255/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 256static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
257
258/* md_assemble() always leaves the strings it's passed unaltered. To
259 effect this we maintain a stack of saved characters that we've smashed
260 with '\0's (indicating end of strings for various sub-fields of the
47926f60 261 assembler instruction). */
252b5132 262static char save_stack[32];
ce8a8b2f 263static char *save_stack_p;
252b5132
RH		 264#define END_STRING_AND_SAVE(s) \
265 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
266#define RESTORE_END_STRING(s) \
267 do { *(s) = *--save_stack_p; } while (0)
268
47926f60 269/* The instruction we're assembling. */
252b5132
RH		 270static i386_insn i;
271
272/* Possible templates for current insn. */
273static const templates *current_templates;
274
47926f60 275/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 276static expressionS disp_expressions[2], im_expressions[2];
277
47926f60
KH		 278/* Current operand we are working on. */
279static int this_operand;
252b5132 280
3e73aa7c
JH		 281/* We support four different modes. FLAG_CODE variable is used to distinguish
282 these. */
283
284enum flag_code {
285 CODE_32BIT,
286 CODE_16BIT,
287 CODE_64BIT };
f3c180ae 288#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 289
290static enum flag_code flag_code;
4fa24527 291static unsigned int object_64bit;
3e73aa7c
JH		 292static int use_rela_relocations = 0;
293
294/* The names used to print error messages. */
b77a7acd 295static const char *flag_code_names[] =
3e73aa7c
JH		 296 {
297 "32",
298 "16",
299 "64"
300 };
252b5132 301
47926f60
KH		 302/* 1 for intel syntax,
303 0 if att syntax. */
304static int intel_syntax = 0;
252b5132 305
47926f60
KH		 306/* 1 if register prefix % not required. */
307static int allow_naked_reg = 0;
252b5132 308
47926f60
KH		 309/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
310 leave, push, and pop instructions so that gcc has the same stack
311 frame as in 32 bit mode. */
312static char stackop_size = '\0';
eecb386c 313
12b55ccc
L		 314/* Non-zero to optimize code alignment. */
315int optimize_align_code = 1;
316
47926f60
KH		 317/* Non-zero to quieten some warnings. */
318static int quiet_warnings = 0;
a38cf1db 319
47926f60
KH		 320/* CPU name. */
321static const char *cpu_arch_name = NULL;
5c6af06e 322static const char *cpu_sub_arch_name = NULL;
a38cf1db 323
47926f60 324/* CPU feature flags. */
29b0f896 325static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 326
fddf5b5b
AM		 327/* If set, conditional jumps are not automatically promoted to handle
328 larger than a byte offset. */
329static unsigned int no_cond_jump_promotion = 0;
330
29b0f896 331/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 332static symbolS *GOT_symbol;
29b0f896 333
a4447b93
RH		 334/* The dwarf2 return column, adjusted for 32 or 64 bit. */
335unsigned int x86_dwarf2_return_column;
336
337/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
338int x86_cie_data_alignment;
339
252b5132 340/* Interface to relax_segment.
fddf5b5b
AM		 341 There are 3 major relax states for 386 jump insns because the
342 different types of jumps add different sizes to frags when we're
343 figuring out what sort of jump to choose to reach a given label. */
252b5132 344
47926f60 345/* Types. */
93c2a809
AM		 346#define UNCOND_JUMP 0
347#define COND_JUMP 1
348#define COND_JUMP86 2
fddf5b5b 349
47926f60 350/* Sizes. */
252b5132
RH		 351#define CODE16 1
352#define SMALL 0
29b0f896 353#define SMALL16 (SMALL | CODE16)
252b5132 354#define BIG 2
29b0f896 355#define BIG16 (BIG | CODE16)
252b5132
RH		 356
357#ifndef INLINE
358#ifdef __GNUC__
359#define INLINE __inline__
360#else
361#define INLINE
362#endif
363#endif
364
fddf5b5b
AM		 365#define ENCODE_RELAX_STATE(type, size) \
366 ((relax_substateT) (((type) << 2) | (size)))
367#define TYPE_FROM_RELAX_STATE(s) \
368 ((s) >> 2)
369#define DISP_SIZE_FROM_RELAX_STATE(s) \
370 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 371
372/* This table is used by relax_frag to promote short jumps to long
373 ones where necessary. SMALL (short) jumps may be promoted to BIG
374 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
375 don't allow a short jump in a 32 bit code segment to be promoted to
376 a 16 bit offset jump because it's slower (requires data size
377 prefix), and doesn't work, unless the destination is in the bottom
378 64k of the code segment (The top 16 bits of eip are zeroed). */
379
380const relax_typeS md_relax_table[] =
381{
24eab124
AM		 382 /* The fields are:
383 1) most positive reach of this state,
384 2) most negative reach of this state,
93c2a809 385 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 386 4) which index into the table to try if we can't fit into this one. */
252b5132 387
fddf5b5b 388 /* UNCOND_JUMP states. */
93c2a809
AM		 389 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
390 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
391 /* dword jmp adds 4 bytes to frag:
392 0 extra opcode bytes, 4 displacement bytes. */
252b5132 393 {0, 0, 4, 0},
93c2a809
AM		 394 /* word jmp adds 2 byte2 to frag:
395 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 396 {0, 0, 2, 0},
397
93c2a809
AM		 398 /* COND_JUMP states. */
399 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
400 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
401 /* dword conditionals adds 5 bytes to frag:
402 1 extra opcode byte, 4 displacement bytes. */
403 {0, 0, 5, 0},
fddf5b5b 404 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 405 1 extra opcode byte, 2 displacement bytes. */
406 {0, 0, 3, 0},
407
408 /* COND_JUMP86 states. */
409 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
410 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
411 /* dword conditionals adds 5 bytes to frag:
412 1 extra opcode byte, 4 displacement bytes. */
413 {0, 0, 5, 0},
414 /* word conditionals add 4 bytes to frag:
415 1 displacement byte and a 3 byte long branch insn. */
416 {0, 0, 4, 0}
252b5132
RH		 417};
418
e413e4e9
AM		 419static const arch_entry cpu_arch[] = {
420 {"i8086", Cpu086 },
421 {"i186", Cpu086|Cpu186 },
422 {"i286", Cpu086|Cpu186|Cpu286 },
423 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
424 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
5c6af06e
JB		 425 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
426 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
427 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
428 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
429 {"pentiumii", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX },
430 {"pentiumiii",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE },
431 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
432 {"prescott", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI },
433 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX },
434 {"k6_2", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
435 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
436 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
30123838 437 {"opteron", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
5c6af06e
JB		 438 {".mmx", CpuMMX },
439 {".sse", CpuMMX|CpuMMX2|CpuSSE },
440 {".sse2", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
bf50992e 441 {".sse3", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3 },
5c6af06e
JB		 442 {".3dnow", CpuMMX|Cpu3dnow },
443 {".3dnowa", CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
444 {".padlock", CpuPadLock },
30123838
JB		 445 {".pacifica", CpuSVME },
446 {".svme", CpuSVME },
e413e4e9
AM		 447 {NULL, 0 }
448};
449
29b0f896
AM		 450const pseudo_typeS md_pseudo_table[] =
451{
452#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
453 {"align", s_align_bytes, 0},
454#else
455 {"align", s_align_ptwo, 0},
456#endif
457 {"arch", set_cpu_arch, 0},
458#ifndef I386COFF
459 {"bss", s_bss, 0},
460#endif
461 {"ffloat", float_cons, 'f'},
462 {"dfloat", float_cons, 'd'},
463 {"tfloat", float_cons, 'x'},
464 {"value", cons, 2},
d182319b 465 {"slong", signed_cons, 4},
29b0f896
AM		 466 {"noopt", s_ignore, 0},
467 {"optim", s_ignore, 0},
468 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
469 {"code16", set_code_flag, CODE_16BIT},
470 {"code32", set_code_flag, CODE_32BIT},
471 {"code64", set_code_flag, CODE_64BIT},
472 {"intel_syntax", set_intel_syntax, 1},
473 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 474#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
475 {"largecomm", handle_large_common, 0},
07a53e5c
RH		 476#else
477 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
478 {"loc", dwarf2_directive_loc, 0},
479 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 480#endif
6482c264
NC		 481#ifdef TE_PE
482 {"secrel32", pe_directive_secrel, 0},
483#endif
29b0f896
AM		 484 {0, 0, 0}
485};
486
487/* For interface with expression (). */
488extern char *input_line_pointer;
489
490/* Hash table for instruction mnemonic lookup. */
491static struct hash_control *op_hash;
492
493/* Hash table for register lookup. */
494static struct hash_control *reg_hash;
495\f
252b5132
RH		 496void
497i386_align_code (fragP, count)
498 fragS *fragP;
499 int count;
500{
ce8a8b2f
AM		 501 /* Various efficient no-op patterns for aligning code labels.
502 Note: Don't try to assemble the instructions in the comments.
503 0L and 0w are not legal. */
252b5132
RH		 504 static const char f32_1[] =
505 {0x90}; /* nop */
506 static const char f32_2[] =
507 {0x89,0xf6}; /* movl %esi,%esi */
508 static const char f32_3[] =
509 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
510 static const char f32_4[] =
511 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
512 static const char f32_5[] =
513 {0x90, /* nop */
514 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
515 static const char f32_6[] =
516 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
517 static const char f32_7[] =
518 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
519 static const char f32_8[] =
520 {0x90, /* nop */
521 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
522 static const char f32_9[] =
523 {0x89,0xf6, /* movl %esi,%esi */
524 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
525 static const char f32_10[] =
526 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
527 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
528 static const char f32_11[] =
529 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
530 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
531 static const char f32_12[] =
532 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
533 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
534 static const char f32_13[] =
535 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
536 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
537 static const char f32_14[] =
538 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
539 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
540 static const char f32_15[] =
541 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
542 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 543 static const char f16_3[] =
544 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 545 static const char f16_4[] =
546 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
547 static const char f16_5[] =
548 {0x90, /* nop */
549 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
550 static const char f16_6[] =
551 {0x89,0xf6, /* mov %si,%si */
552 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
553 static const char f16_7[] =
554 {0x8d,0x74,0x00, /* lea 0(%si),%si */
555 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
556 static const char f16_8[] =
557 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
558 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
559 static const char *const f32_patt[] = {
560 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
561 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
562 };
563 static const char *const f16_patt[] = {
c3332e24 564 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 565 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
566 };
567
33fef721
JH		 568 if (count <= 0 || count > 15)
569 return;
3e73aa7c 570
33fef721
JH		 571 /* The recommended way to pad 64bit code is to use NOPs preceded by
572 maximally four 0x66 prefixes. Balance the size of nops. */
573 if (flag_code == CODE_64BIT)
252b5132 574 {
33fef721
JH		 575 int i;
576 int nnops = (count + 3) / 4;
577 int len = count / nnops;
578 int remains = count - nnops * len;
579 int pos = 0;
580
581 for (i = 0; i < remains; i++)
252b5132 582 {
33fef721
JH		 583 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
584 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
585 pos += len + 1;
586 }
587 for (; i < nnops; i++)
588 {
589 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
590 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
591 pos += len;
252b5132 592 }
252b5132 593 }
33fef721
JH		 594 else
595 if (flag_code == CODE_16BIT)
596 {
597 memcpy (fragP->fr_literal + fragP->fr_fix,
598 f16_patt[count - 1], count);
599 if (count > 8)
600 /* Adjust jump offset. */
601 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
602 }
603 else
604 memcpy (fragP->fr_literal + fragP->fr_fix,
605 f32_patt[count - 1], count);
606 fragP->fr_var = count;
252b5132
RH		 607}
608
252b5132
RH		 609static INLINE unsigned int
610mode_from_disp_size (t)
611 unsigned int t;
612{
3e73aa7c 613 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 614}
615
616static INLINE int
617fits_in_signed_byte (num)
847f7ad4 618 offsetT num;
252b5132
RH		 619{
620 return (num >= -128) && (num <= 127);
47926f60 621}
252b5132
RH		 622
623static INLINE int
624fits_in_unsigned_byte (num)
847f7ad4 625 offsetT num;
252b5132
RH		 626{
627 return (num & 0xff) == num;
47926f60 628}
252b5132
RH		 629
630static INLINE int
631fits_in_unsigned_word (num)
847f7ad4 632 offsetT num;
252b5132
RH		 633{
634 return (num & 0xffff) == num;
47926f60 635}
252b5132
RH		 636
637static INLINE int
638fits_in_signed_word (num)
847f7ad4 639 offsetT num;
252b5132
RH		 640{
641 return (-32768 <= num) && (num <= 32767);
47926f60 642}
3e73aa7c
JH		 643static INLINE int
644fits_in_signed_long (num)
645 offsetT num ATTRIBUTE_UNUSED;
646{
647#ifndef BFD64
648 return 1;
649#else
650 return (!(((offsetT) -1 << 31) & num)
651 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
652#endif
653} /* fits_in_signed_long() */
654static INLINE int
655fits_in_unsigned_long (num)
656 offsetT num ATTRIBUTE_UNUSED;
657{
658#ifndef BFD64
659 return 1;
660#else
661 return (num & (((offsetT) 2 << 31) - 1)) == num;
662#endif
663} /* fits_in_unsigned_long() */
252b5132
RH		 664
665static int
666smallest_imm_type (num)
847f7ad4 667 offsetT num;
252b5132 668{
a847613f 669 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 670 {
671 /* This code is disabled on the 486 because all the Imm1 forms
672 in the opcode table are slower on the i486. They're the
673 versions with the implicitly specified single-position
674 displacement, which has another syntax if you really want to
675 use that form. */
676 if (num == 1)
3e73aa7c 677 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 678 }
252b5132 679 return (fits_in_signed_byte (num)
3e73aa7c 680 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 681 : fits_in_unsigned_byte (num)
3e73aa7c 682 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 683 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 684 ? (Imm16 | Imm32 | Imm32S | Imm64)
685 : fits_in_signed_long (num)
686 ? (Imm32 | Imm32S | Imm64)
687 : fits_in_unsigned_long (num)
688 ? (Imm32 | Imm64)
689 : Imm64);
47926f60 690}
252b5132 691
847f7ad4
AM		 692static offsetT
693offset_in_range (val, size)
694 offsetT val;
695 int size;
696{
508866be 697 addressT mask;
ba2adb93 698
847f7ad4
AM		 699 switch (size)
700 {
508866be
L		 701 case 1: mask = ((addressT) 1 << 8) - 1; break;
702 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 703 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 704#ifdef BFD64
705 case 8: mask = ((addressT) 2 << 63) - 1; break;
706#endif
47926f60 707 default: abort ();
847f7ad4
AM		 708 }
709
ba2adb93 710 /* If BFD64, sign extend val. */
3e73aa7c
JH		 711 if (!use_rela_relocations)
712 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
713 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 714
47926f60 715 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 716 {
717 char buf1[40], buf2[40];
718
719 sprint_value (buf1, val);
720 sprint_value (buf2, val & mask);
721 as_warn (_("%s shortened to %s"), buf1, buf2);
722 }
723 return val & mask;
724}
725
252b5132
RH		 726/* Returns 0 if attempting to add a prefix where one from the same
727 class already exists, 1 if non rep/repne added, 2 if rep/repne
728 added. */
729static int
730add_prefix (prefix)
731 unsigned int prefix;
732{
733 int ret = 1;
734 int q;
735
29b0f896
AM		 736 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
737 && flag_code == CODE_64BIT)
3e73aa7c
JH		 738 q = REX_PREFIX;
739 else
740 switch (prefix)
741 {
742 default:
743 abort ();
744
745 case CS_PREFIX_OPCODE:
746 case DS_PREFIX_OPCODE:
747 case ES_PREFIX_OPCODE:
748 case FS_PREFIX_OPCODE:
749 case GS_PREFIX_OPCODE:
750 case SS_PREFIX_OPCODE:
751 q = SEG_PREFIX;
752 break;
252b5132 753
3e73aa7c
JH		 754 case REPNE_PREFIX_OPCODE:
755 case REPE_PREFIX_OPCODE:
756 ret = 2;
757 /* fall thru */
758 case LOCK_PREFIX_OPCODE:
759 q = LOCKREP_PREFIX;
760 break;
252b5132 761
3e73aa7c
JH		 762 case FWAIT_OPCODE:
763 q = WAIT_PREFIX;
764 break;
252b5132 765
3e73aa7c
JH		 766 case ADDR_PREFIX_OPCODE:
767 q = ADDR_PREFIX;
768 break;
252b5132 769
3e73aa7c
JH		 770 case DATA_PREFIX_OPCODE:
771 q = DATA_PREFIX;
772 break;
773 }
252b5132 774
29b0f896 775 if (i.prefix[q] != 0)
252b5132
RH		 776 {
777 as_bad (_("same type of prefix used twice"));
778 return 0;
779 }
780
781 i.prefixes += 1;
782 i.prefix[q] = prefix;
783 return ret;
784}
785
786static void
3e73aa7c 787set_code_flag (value)
e5cb08ac 788 int value;
eecb386c 789{
3e73aa7c
JH		 790 flag_code = value;
791 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
792 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
793 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
794 {
795 as_bad (_("64bit mode not supported on this CPU."));
796 }
797 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
798 {
799 as_bad (_("32bit mode not supported on this CPU."));
800 }
eecb386c
AM		 801 stackop_size = '\0';
802}
803
804static void
3e73aa7c
JH		 805set_16bit_gcc_code_flag (new_code_flag)
806 int new_code_flag;
252b5132 807{
3e73aa7c
JH		 808 flag_code = new_code_flag;
809 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
810 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 811 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 812}
813
814static void
815set_intel_syntax (syntax_flag)
eecb386c 816 int syntax_flag;
252b5132
RH		 817{
818 /* Find out if register prefixing is specified. */
819 int ask_naked_reg = 0;
820
821 SKIP_WHITESPACE ();
29b0f896 822 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 823 {
824 char *string = input_line_pointer;
825 int e = get_symbol_end ();
826
47926f60 827 if (strcmp (string, "prefix") == 0)
252b5132 828 ask_naked_reg = 1;
47926f60 829 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 830 ask_naked_reg = -1;
831 else
d0b47220 832 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 833 *input_line_pointer = e;
834 }
835 demand_empty_rest_of_line ();
c3332e24 836
252b5132
RH		 837 intel_syntax = syntax_flag;
838
839 if (ask_naked_reg == 0)
f86103b7
AM		 840 allow_naked_reg = (intel_syntax
841 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 842 else
843 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a
JB		 844
845 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
846 identifier_chars['$'] = intel_syntax ? '$' : 0;
252b5132
RH		 847}
848
e413e4e9
AM		 849static void
850set_cpu_arch (dummy)
47926f60 851 int dummy ATTRIBUTE_UNUSED;
e413e4e9 852{
47926f60 853 SKIP_WHITESPACE ();
e413e4e9 854
29b0f896 855 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 856 {
857 char *string = input_line_pointer;
858 int e = get_symbol_end ();
859 int i;
860
861 for (i = 0; cpu_arch[i].name; i++)
862 {
863 if (strcmp (string, cpu_arch[i].name) == 0)
864 {
5c6af06e
JB		 865 if (*string != '.')
866 {
867 cpu_arch_name = cpu_arch[i].name;
868 cpu_sub_arch_name = NULL;
869 cpu_arch_flags = (cpu_arch[i].flags
870 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
871 break;
872 }
873 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
874 {
875 cpu_sub_arch_name = cpu_arch[i].name;
876 cpu_arch_flags |= cpu_arch[i].flags;
877 }
878 *input_line_pointer = e;
879 demand_empty_rest_of_line ();
880 return;
e413e4e9
AM		 881 }
882 }
883 if (!cpu_arch[i].name)
884 as_bad (_("no such architecture: `%s'"), string);
885
886 *input_line_pointer = e;
887 }
888 else
889 as_bad (_("missing cpu architecture"));
890
fddf5b5b
AM		 891 no_cond_jump_promotion = 0;
892 if (*input_line_pointer == ','
29b0f896 893 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 894 {
895 char *string = ++input_line_pointer;
896 int e = get_symbol_end ();
897
898 if (strcmp (string, "nojumps") == 0)
899 no_cond_jump_promotion = 1;
900 else if (strcmp (string, "jumps") == 0)
901 ;
902 else
903 as_bad (_("no such architecture modifier: `%s'"), string);
904
905 *input_line_pointer = e;
906 }
907
e413e4e9
AM		 908 demand_empty_rest_of_line ();
909}
910
b9d79e03
JH		 911unsigned long
912i386_mach ()
913{
914 if (!strcmp (default_arch, "x86_64"))
915 return bfd_mach_x86_64;
916 else if (!strcmp (default_arch, "i386"))
917 return bfd_mach_i386_i386;
918 else
919 as_fatal (_("Unknown architecture"));
920}
b9d79e03 921\f
252b5132
RH		 922void
923md_begin ()
924{
925 const char *hash_err;
926
47926f60 927 /* Initialize op_hash hash table. */
252b5132
RH		 928 op_hash = hash_new ();
929
930 {
29b0f896
AM		 931 const template *optab;
932 templates *core_optab;
252b5132 933
47926f60
KH		 934 /* Setup for loop. */
935 optab = i386_optab;
252b5132
RH		 936 core_optab = (templates *) xmalloc (sizeof (templates));
937 core_optab->start = optab;
938
939 while (1)
940 {
941 ++optab;
942 if (optab->name == NULL
943 || strcmp (optab->name, (optab - 1)->name) != 0)
944 {
945 /* different name --> ship out current template list;
47926f60 946 add to hash table; & begin anew. */
252b5132
RH		 947 core_optab->end = optab;
948 hash_err = hash_insert (op_hash,
949 (optab - 1)->name,
950 (PTR) core_optab);
951 if (hash_err)
952 {
252b5132
RH		 953 as_fatal (_("Internal Error: Can't hash %s: %s"),
954 (optab - 1)->name,
955 hash_err);
956 }
957 if (optab->name == NULL)
958 break;
959 core_optab = (templates *) xmalloc (sizeof (templates));
960 core_optab->start = optab;
961 }
962 }
963 }
964
47926f60 965 /* Initialize reg_hash hash table. */
252b5132
RH		 966 reg_hash = hash_new ();
967 {
29b0f896 968 const reg_entry *regtab;
252b5132
RH		 969
970 for (regtab = i386_regtab;
971 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
972 regtab++)
973 {
974 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
975 if (hash_err)
3e73aa7c
JH		 976 as_fatal (_("Internal Error: Can't hash %s: %s"),
977 regtab->reg_name,
978 hash_err);
252b5132
RH		 979 }
980 }
981
47926f60 982 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 983 {
29b0f896
AM		 984 int c;
985 char *p;
252b5132
RH		 986
987 for (c = 0; c < 256; c++)
988 {
3882b010 989 if (ISDIGIT (c))
252b5132
RH		 990 {
991 digit_chars[c] = c;
992 mnemonic_chars[c] = c;
993 register_chars[c] = c;
994 operand_chars[c] = c;
995 }
3882b010 996 else if (ISLOWER (c))
252b5132
RH		 997 {
998 mnemonic_chars[c] = c;
999 register_chars[c] = c;
1000 operand_chars[c] = c;
1001 }
3882b010 1002 else if (ISUPPER (c))
252b5132 1003 {
3882b010 1004 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1005 register_chars[c] = mnemonic_chars[c];
1006 operand_chars[c] = c;
1007 }
1008
3882b010 1009 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1010 identifier_chars[c] = c;
1011 else if (c >= 128)
1012 {
1013 identifier_chars[c] = c;
1014 operand_chars[c] = c;
1015 }
1016 }
1017
1018#ifdef LEX_AT
1019 identifier_chars['@'] = '@';
32137342
NC		 1020#endif
1021#ifdef LEX_QM
1022 identifier_chars['?'] = '?';
1023 operand_chars['?'] = '?';
252b5132 1024#endif
252b5132 1025 digit_chars['-'] = '-';
791fe849 1026 mnemonic_chars['-'] = '-';
252b5132
RH		 1027 identifier_chars['_'] = '_';
1028 identifier_chars['.'] = '.';
1029
1030 for (p = operand_special_chars; *p != '\0'; p++)
1031 operand_chars[(unsigned char) *p] = *p;
1032 }
1033
1034#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1035 if (IS_ELF)
252b5132
RH		 1036 {
1037 record_alignment (text_section, 2);
1038 record_alignment (data_section, 2);
1039 record_alignment (bss_section, 2);
1040 }
1041#endif
a4447b93
RH		 1042
1043 if (flag_code == CODE_64BIT)
1044 {
1045 x86_dwarf2_return_column = 16;
1046 x86_cie_data_alignment = -8;
1047 }
1048 else
1049 {
1050 x86_dwarf2_return_column = 8;
1051 x86_cie_data_alignment = -4;
1052 }
252b5132
RH		 1053}
1054
1055void
1056i386_print_statistics (file)
1057 FILE *file;
1058{
1059 hash_print_statistics (file, "i386 opcode", op_hash);
1060 hash_print_statistics (file, "i386 register", reg_hash);
1061}
1062\f
252b5132
RH		 1063#ifdef DEBUG386
1064
ce8a8b2f 1065/* Debugging routines for md_assemble. */
252b5132
RH		 1066static void pi PARAMS ((char *, i386_insn *));
1067static void pte PARAMS ((template *));
1068static void pt PARAMS ((unsigned int));
1069static void pe PARAMS ((expressionS *));
1070static void ps PARAMS ((symbolS *));
1071
1072static void
1073pi (line, x)
1074 char *line;
1075 i386_insn *x;
1076{
09f131f2 1077 unsigned int i;
252b5132
RH		 1078
1079 fprintf (stdout, "%s: template ", line);
1080 pte (&x->tm);
09f131f2
JH		 1081 fprintf (stdout, " address: base %s index %s scale %x\n",
1082 x->base_reg ? x->base_reg->reg_name : "none",
1083 x->index_reg ? x->index_reg->reg_name : "none",
1084 x->log2_scale_factor);
1085 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1086 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1087 fprintf (stdout, " sib: base %x index %x scale %x\n",
1088 x->sib.base, x->sib.index, x->sib.scale);
1089 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1090 (x->rex & REX_MODE64) != 0,
1091 (x->rex & REX_EXTX) != 0,
1092 (x->rex & REX_EXTY) != 0,
1093 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1094 for (i = 0; i < x->operands; i++)
1095 {
1096 fprintf (stdout, " #%d: ", i + 1);
1097 pt (x->types[i]);
1098 fprintf (stdout, "\n");
1099 if (x->types[i]
3f4438ab 1100 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1101 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1102 if (x->types[i] & Imm)
520dc8e8 1103 pe (x->op[i].imms);
252b5132 1104 if (x->types[i] & Disp)
520dc8e8 1105 pe (x->op[i].disps);
252b5132
RH		 1106 }
1107}
1108
1109static void
1110pte (t)
1111 template *t;
1112{
09f131f2 1113 unsigned int i;
252b5132 1114 fprintf (stdout, " %d operands ", t->operands);
47926f60 1115 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1116 if (t->extension_opcode != None)
1117 fprintf (stdout, "ext %x ", t->extension_opcode);
1118 if (t->opcode_modifier & D)
1119 fprintf (stdout, "D");
1120 if (t->opcode_modifier & W)
1121 fprintf (stdout, "W");
1122 fprintf (stdout, "\n");
1123 for (i = 0; i < t->operands; i++)
1124 {
1125 fprintf (stdout, " #%d type ", i + 1);
1126 pt (t->operand_types[i]);
1127 fprintf (stdout, "\n");
1128 }
1129}
1130
1131static void
1132pe (e)
1133 expressionS *e;
1134{
24eab124 1135 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1136 fprintf (stdout, " add_number %ld (%lx)\n",
1137 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1138 if (e->X_add_symbol)
1139 {
1140 fprintf (stdout, " add_symbol ");
1141 ps (e->X_add_symbol);
1142 fprintf (stdout, "\n");
1143 }
1144 if (e->X_op_symbol)
1145 {
1146 fprintf (stdout, " op_symbol ");
1147 ps (e->X_op_symbol);
1148 fprintf (stdout, "\n");
1149 }
1150}
1151
1152static void
1153ps (s)
1154 symbolS *s;
1155{
1156 fprintf (stdout, "%s type %s%s",
1157 S_GET_NAME (s),
1158 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1159 segment_name (S_GET_SEGMENT (s)));
1160}
1161
1162struct type_name
1163 {
1164 unsigned int mask;
1165 char *tname;
1166 }
1167
29b0f896 1168static const type_names[] =
252b5132
RH		 1169{
1170 { Reg8, "r8" },
1171 { Reg16, "r16" },
1172 { Reg32, "r32" },
09f131f2 1173 { Reg64, "r64" },
252b5132
RH		 1174 { Imm8, "i8" },
1175 { Imm8S, "i8s" },
1176 { Imm16, "i16" },
1177 { Imm32, "i32" },
09f131f2
JH		 1178 { Imm32S, "i32s" },
1179 { Imm64, "i64" },
252b5132
RH		 1180 { Imm1, "i1" },
1181 { BaseIndex, "BaseIndex" },
1182 { Disp8, "d8" },
1183 { Disp16, "d16" },
1184 { Disp32, "d32" },
09f131f2
JH		 1185 { Disp32S, "d32s" },
1186 { Disp64, "d64" },
252b5132
RH		 1187 { InOutPortReg, "InOutPortReg" },
1188 { ShiftCount, "ShiftCount" },
1189 { Control, "control reg" },
1190 { Test, "test reg" },
1191 { Debug, "debug reg" },
1192 { FloatReg, "FReg" },
1193 { FloatAcc, "FAcc" },
1194 { SReg2, "SReg2" },
1195 { SReg3, "SReg3" },
1196 { Acc, "Acc" },
1197 { JumpAbsolute, "Jump Absolute" },
1198 { RegMMX, "rMMX" },
3f4438ab 1199 { RegXMM, "rXMM" },
252b5132
RH		 1200 { EsSeg, "es" },
1201 { 0, "" }
1202};
1203
1204static void
1205pt (t)
1206 unsigned int t;
1207{
29b0f896 1208 const struct type_name *ty;
252b5132 1209
09f131f2
JH		 1210 for (ty = type_names; ty->mask; ty++)
1211 if (t & ty->mask)
1212 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1213 fflush (stdout);
1214}
1215
1216#endif /* DEBUG386 */
1217\f
252b5132 1218static bfd_reloc_code_real_type
3956db08
JB		 1219reloc (unsigned int size,
1220 int pcrel,
1221 int sign,
1222 bfd_reloc_code_real_type other)
252b5132 1223{
47926f60 1224 if (other != NO_RELOC)
3956db08
JB		 1225 {
1226 reloc_howto_type *reloc;
1227
1228 if (size == 8)
1229 switch (other)
1230 {
1231 case BFD_RELOC_X86_64_TPOFF32:
1232 other = BFD_RELOC_X86_64_TPOFF64;
1233 break;
1234 case BFD_RELOC_X86_64_DTPOFF32:
1235 other = BFD_RELOC_X86_64_DTPOFF64;
1236 break;
1237 default:
1238 break;
1239 }
e05278af
JB		 1240
1241 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1242 if (size == 4 && flag_code != CODE_64BIT)
1243 sign = -1;
1244
3956db08
JB		 1245 reloc = bfd_reloc_type_lookup (stdoutput, other);
1246 if (!reloc)
1247 as_bad (_("unknown relocation (%u)"), other);
1248 else if (size != bfd_get_reloc_size (reloc))
1249 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1250 bfd_get_reloc_size (reloc),
1251 size);
1252 else if (pcrel && !reloc->pc_relative)
1253 as_bad (_("non-pc-relative relocation for pc-relative field"));
1254 else if ((reloc->complain_on_overflow == complain_overflow_signed
1255 && !sign)
1256 || (reloc->complain_on_overflow == complain_overflow_unsigned
1257 && sign > 0))
1258 as_bad (_("relocated field and relocation type differ in signedness"));
1259 else
1260 return other;
1261 return NO_RELOC;
1262 }
252b5132
RH		 1263
1264 if (pcrel)
1265 {
3e73aa7c 1266 if (!sign)
3956db08 1267 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1268 switch (size)
1269 {
1270 case 1: return BFD_RELOC_8_PCREL;
1271 case 2: return BFD_RELOC_16_PCREL;
1272 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1273 case 8: return BFD_RELOC_64_PCREL;
252b5132 1274 }
3956db08 1275 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1276 }
1277 else
1278 {
3956db08 1279 if (sign > 0)
e5cb08ac 1280 switch (size)
3e73aa7c
JH		 1281 {
1282 case 4: return BFD_RELOC_X86_64_32S;
1283 }
1284 else
1285 switch (size)
1286 {
1287 case 1: return BFD_RELOC_8;
1288 case 2: return BFD_RELOC_16;
1289 case 4: return BFD_RELOC_32;
1290 case 8: return BFD_RELOC_64;
1291 }
3956db08
JB		 1292 as_bad (_("cannot do %s %u byte relocation"),
1293 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1294 }
1295
bfb32b52 1296 abort ();
252b5132
RH		 1297 return BFD_RELOC_NONE;
1298}
1299
47926f60
KH		 1300/* Here we decide which fixups can be adjusted to make them relative to
1301 the beginning of the section instead of the symbol. Basically we need
1302 to make sure that the dynamic relocations are done correctly, so in
1303 some cases we force the original symbol to be used. */
1304
252b5132 1305int
c0c949c7 1306tc_i386_fix_adjustable (fixP)
31312f95 1307 fixS *fixP ATTRIBUTE_UNUSED;
252b5132 1308{
6d249963 1309#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1310 if (!IS_ELF)
31312f95
AM		 1311 return 1;
1312
a161fe53
AM		 1313 /* Don't adjust pc-relative references to merge sections in 64-bit
1314 mode. */
1315 if (use_rela_relocations
1316 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1317 && fixP->fx_pcrel)
252b5132 1318 return 0;
31312f95 1319
8d01d9a9
AJ		 1320 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1321 and changed later by validate_fix. */
1322 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1323 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1324 return 0;
1325
ce8a8b2f 1326 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1327 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1328 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1329 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1330 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1331 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1332 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1333 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1334 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1335 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1336 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1337 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3e73aa7c
JH		 1338 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1339 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1340 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1341 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1342 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1343 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1344 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1345 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1346 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1347 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1348 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
252b5132
RH		 1349 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1350 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1351 return 0;
31312f95 1352#endif
252b5132
RH		 1353 return 1;
1354}
252b5132 1355
29b0f896 1356static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1357
1358static int
252b5132 1359intel_float_operand (mnemonic)
29b0f896 1360 const char *mnemonic;
252b5132 1361{
9306ca4a
JB		 1362 /* Note that the value returned is meaningful only for opcodes with (memory)
1363 operands, hence the code here is free to improperly handle opcodes that
1364 have no operands (for better performance and smaller code). */
1365
1366 if (mnemonic[0] != 'f')
1367 return 0; /* non-math */
1368
1369 switch (mnemonic[1])
1370 {
1371 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1372 the fs segment override prefix not currently handled because no
1373 call path can make opcodes without operands get here */
1374 case 'i':
1375 return 2 /* integer op */;
1376 case 'l':
1377 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1378 return 3; /* fldcw/fldenv */
1379 break;
1380 case 'n':
1381 if (mnemonic[2] != 'o' /* fnop */)
1382 return 3; /* non-waiting control op */
1383 break;
1384 case 'r':
1385 if (mnemonic[2] == 's')
1386 return 3; /* frstor/frstpm */
1387 break;
1388 case 's':
1389 if (mnemonic[2] == 'a')
1390 return 3; /* fsave */
1391 if (mnemonic[2] == 't')
1392 {
1393 switch (mnemonic[3])
1394 {
1395 case 'c': /* fstcw */
1396 case 'd': /* fstdw */
1397 case 'e': /* fstenv */
1398 case 's': /* fsts[gw] */
1399 return 3;
1400 }
1401 }
1402 break;
1403 case 'x':
1404 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1405 return 0; /* fxsave/fxrstor are not really math ops */
1406 break;
1407 }
252b5132 1408
9306ca4a 1409 return 1;
252b5132
RH		 1410}
1411
1412/* This is the guts of the machine-dependent assembler. LINE points to a
1413 machine dependent instruction. This function is supposed to emit
1414 the frags/bytes it assembles to. */
1415
1416void
1417md_assemble (line)
1418 char *line;
1419{
252b5132 1420 int j;
252b5132
RH		 1421 char mnemonic[MAX_MNEM_SIZE];
1422
47926f60 1423 /* Initialize globals. */
252b5132
RH		 1424 memset (&i, '\0', sizeof (i));
1425 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1426 i.reloc[j] = NO_RELOC;
252b5132
RH		 1427 memset (disp_expressions, '\0', sizeof (disp_expressions));
1428 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1429 save_stack_p = save_stack;
252b5132
RH		 1430
1431 /* First parse an instruction mnemonic & call i386_operand for the operands.
1432 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1433 start of a (possibly prefixed) mnemonic. */
252b5132 1434
29b0f896
AM		 1435 line = parse_insn (line, mnemonic);
1436 if (line == NULL)
1437 return;
252b5132 1438
29b0f896
AM		 1439 line = parse_operands (line, mnemonic);
1440 if (line == NULL)
1441 return;
252b5132 1442
29b0f896
AM		 1443 /* Now we've parsed the mnemonic into a set of templates, and have the
1444 operands at hand. */
1445
1446 /* All intel opcodes have reversed operands except for "bound" and
1447 "enter". We also don't reverse intersegment "jmp" and "call"
1448 instructions with 2 immediate operands so that the immediate segment
1449 precedes the offset, as it does when in AT&T mode. "enter" and the
1450 intersegment "jmp" and "call" instructions are the only ones that
1451 have two immediate operands. */
1452 if (intel_syntax && i.operands > 1
1453 && (strcmp (mnemonic, "bound") != 0)
30123838 1454 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1455 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1456 swap_operands ();
1457
1458 if (i.imm_operands)
1459 optimize_imm ();
1460
b300c311
L		 1461 /* Don't optimize displacement for movabs since it only takes 64bit
1462 displacement. */
1463 if (i.disp_operands
1464 && (flag_code != CODE_64BIT
1465 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1466 optimize_disp ();
1467
1468 /* Next, we find a template that matches the given insn,
1469 making sure the overlap of the given operands types is consistent
1470 with the template operand types. */
252b5132 1471
29b0f896
AM		 1472 if (!match_template ())
1473 return;
252b5132 1474
cd61ebfe
AM		 1475 if (intel_syntax)
1476 {
1477 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1478 if (SYSV386_COMPAT
1479 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1480 i.tm.base_opcode ^= FloatR;
1481
1482 /* Zap movzx and movsx suffix. The suffix may have been set from
1483 "word ptr" or "byte ptr" on the source operand, but we'll use
1484 the suffix later to choose the destination register. */
1485 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1486 {
1487 if (i.reg_operands < 2
1488 && !i.suffix
1489 && (~i.tm.opcode_modifier
1490 & (No_bSuf
1491 | No_wSuf
1492 | No_lSuf
1493 | No_sSuf
1494 | No_xSuf
1495 | No_qSuf)))
1496 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1497
1498 i.suffix = 0;
1499 }
cd61ebfe 1500 }
24eab124 1501
29b0f896
AM		 1502 if (i.tm.opcode_modifier & FWait)
1503 if (!add_prefix (FWAIT_OPCODE))
1504 return;
252b5132 1505
29b0f896
AM		 1506 /* Check string instruction segment overrides. */
1507 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1508 {
1509 if (!check_string ())
5dd0794d 1510 return;
29b0f896 1511 }
5dd0794d 1512
29b0f896
AM		 1513 if (!process_suffix ())
1514 return;
e413e4e9 1515
29b0f896
AM		 1516 /* Make still unresolved immediate matches conform to size of immediate
1517 given in i.suffix. */
1518 if (!finalize_imm ())
1519 return;
252b5132 1520
29b0f896
AM		 1521 if (i.types[0] & Imm1)
1522 i.imm_operands = 0; /* kludge for shift insns. */
1523 if (i.types[0] & ImplicitRegister)
1524 i.reg_operands--;
1525 if (i.types[1] & ImplicitRegister)
1526 i.reg_operands--;
1527 if (i.types[2] & ImplicitRegister)
1528 i.reg_operands--;
252b5132 1529
29b0f896
AM		 1530 if (i.tm.opcode_modifier & ImmExt)
1531 {
02fc3089
L		 1532 expressionS *exp;
1533
ca164297
L		 1534 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
1535 {
67c1ffbe 1536 /* These Intel Prescott New Instructions have the fixed
ca164297
L		 1537 operands with an opcode suffix which is coded in the same
1538 place as an 8-bit immediate field would be. Here we check
1539 those operands and remove them afterwards. */
1540 unsigned int x;
1541
a4622f40 1542 for (x = 0; x < i.operands; x++)
ca164297
L		 1543 if (i.op[x].regs->reg_num != x)
1544 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1545 i.op[x].regs->reg_name, x + 1, i.tm.name);
1546 i.operands = 0;
1547 }
1548
29b0f896
AM		 1549 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1550 opcode suffix which is coded in the same place as an 8-bit
1551 immediate field would be. Here we fake an 8-bit immediate
1552 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1553
29b0f896 1554 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1555
29b0f896
AM		 1556 exp = &im_expressions[i.imm_operands++];
1557 i.op[i.operands].imms = exp;
1558 i.types[i.operands++] = Imm8;
1559 exp->X_op = O_constant;
1560 exp->X_add_number = i.tm.extension_opcode;
1561 i.tm.extension_opcode = None;
1562 }
252b5132 1563
29b0f896
AM		 1564 /* For insns with operands there are more diddles to do to the opcode. */
1565 if (i.operands)
1566 {
1567 if (!process_operands ())
1568 return;
1569 }
1570 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1571 {
1572 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1573 as_warn (_("translating to `%sp'"), i.tm.name);
1574 }
252b5132 1575
29b0f896
AM		 1576 /* Handle conversion of 'int $3' --> special int3 insn. */
1577 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1578 {
1579 i.tm.base_opcode = INT3_OPCODE;
1580 i.imm_operands = 0;
1581 }
252b5132 1582
29b0f896
AM		 1583 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1584 && i.op[0].disps->X_op == O_constant)
1585 {
1586 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1587 the absolute address given by the constant. Since ix86 jumps and
1588 calls are pc relative, we need to generate a reloc. */
1589 i.op[0].disps->X_add_symbol = &abs_symbol;
1590 i.op[0].disps->X_op = O_symbol;
1591 }
252b5132 1592
29b0f896
AM		 1593 if ((i.tm.opcode_modifier & Rex64) != 0)
1594 i.rex |= REX_MODE64;
252b5132 1595
29b0f896
AM		 1596 /* For 8 bit registers we need an empty rex prefix. Also if the
1597 instruction already has a prefix, we need to convert old
1598 registers to new ones. */
773f551c 1599
29b0f896
AM		 1600 if (((i.types[0] & Reg8) != 0
1601 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1602 || ((i.types[1] & Reg8) != 0
1603 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1604 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1605 && i.rex != 0))
1606 {
1607 int x;
726c5dcd 1608
29b0f896
AM		 1609 i.rex |= REX_OPCODE;
1610 for (x = 0; x < 2; x++)
1611 {
1612 /* Look for 8 bit operand that uses old registers. */
1613 if ((i.types[x] & Reg8) != 0
1614 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1615 {
29b0f896
AM		 1616 /* In case it is "hi" register, give up. */
1617 if (i.op[x].regs->reg_num > 3)
0477af35 1618 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
29b0f896 1619 i.op[x].regs->reg_name);
773f551c 1620
29b0f896
AM		 1621 /* Otherwise it is equivalent to the extended register.
1622 Since the encoding doesn't change this is merely
1623 cosmetic cleanup for debug output. */
1624
1625 i.op[x].regs = i.op[x].regs + 8;
773f551c 1626 }
29b0f896
AM		 1627 }
1628 }
773f551c 1629
29b0f896
AM		 1630 if (i.rex != 0)
1631 add_prefix (REX_OPCODE | i.rex);
1632
1633 /* We are ready to output the insn. */
1634 output_insn ();
1635}
1636
1637static char *
1638parse_insn (line, mnemonic)
1639 char *line;
1640 char *mnemonic;
1641{
1642 char *l = line;
1643 char *token_start = l;
1644 char *mnem_p;
5c6af06e
JB		 1645 int supported;
1646 const template *t;
29b0f896
AM		 1647
1648 /* Non-zero if we found a prefix only acceptable with string insns. */
1649 const char *expecting_string_instruction = NULL;
45288df1 1650
29b0f896
AM		 1651 while (1)
1652 {
1653 mnem_p = mnemonic;
1654 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1655 {
1656 mnem_p++;
1657 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1658 {
29b0f896
AM		 1659 as_bad (_("no such instruction: `%s'"), token_start);
1660 return NULL;
1661 }
1662 l++;
1663 }
1664 if (!is_space_char (*l)
1665 && *l != END_OF_INSN
e44823cf
JB		 1666 && (intel_syntax
1667 || (*l != PREFIX_SEPARATOR
1668 && *l != ',')))
29b0f896
AM		 1669 {
1670 as_bad (_("invalid character %s in mnemonic"),
1671 output_invalid (*l));
1672 return NULL;
1673 }
1674 if (token_start == l)
1675 {
e44823cf 1676 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 1677 as_bad (_("expecting prefix; got nothing"));
1678 else
1679 as_bad (_("expecting mnemonic; got nothing"));
1680 return NULL;
1681 }
45288df1 1682
29b0f896
AM		 1683 /* Look up instruction (or prefix) via hash table. */
1684 current_templates = hash_find (op_hash, mnemonic);
47926f60 1685
29b0f896
AM		 1686 if (*l != END_OF_INSN
1687 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1688 && current_templates
1689 && (current_templates->start->opcode_modifier & IsPrefix))
1690 {
2dd88dca
JB		 1691 if (current_templates->start->cpu_flags
1692 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1693 {
1694 as_bad ((flag_code != CODE_64BIT
1695 ? _("`%s' is only supported in 64-bit mode")
1696 : _("`%s' is not supported in 64-bit mode")),
1697 current_templates->start->name);
1698 return NULL;
1699 }
29b0f896
AM		 1700 /* If we are in 16-bit mode, do not allow addr16 or data16.
1701 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1702 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1703 && flag_code != CODE_64BIT
1704 && (((current_templates->start->opcode_modifier & Size32) != 0)
1705 ^ (flag_code == CODE_16BIT)))
1706 {
1707 as_bad (_("redundant %s prefix"),
1708 current_templates->start->name);
1709 return NULL;
45288df1 1710 }
29b0f896
AM		 1711 /* Add prefix, checking for repeated prefixes. */
1712 switch (add_prefix (current_templates->start->base_opcode))
1713 {
1714 case 0:
1715 return NULL;
1716 case 2:
1717 expecting_string_instruction = current_templates->start->name;
1718 break;
1719 }
1720 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1721 token_start = ++l;
1722 }
1723 else
1724 break;
1725 }
45288df1 1726
29b0f896
AM		 1727 if (!current_templates)
1728 {
1729 /* See if we can get a match by trimming off a suffix. */
1730 switch (mnem_p[-1])
1731 {
1732 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 1733 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
1734 i.suffix = SHORT_MNEM_SUFFIX;
1735 else
29b0f896
AM		 1736 case BYTE_MNEM_SUFFIX:
1737 case QWORD_MNEM_SUFFIX:
1738 i.suffix = mnem_p[-1];
1739 mnem_p[-1] = '\0';
1740 current_templates = hash_find (op_hash, mnemonic);
1741 break;
1742 case SHORT_MNEM_SUFFIX:
1743 case LONG_MNEM_SUFFIX:
1744 if (!intel_syntax)
1745 {
1746 i.suffix = mnem_p[-1];
1747 mnem_p[-1] = '\0';
1748 current_templates = hash_find (op_hash, mnemonic);
1749 }
1750 break;
252b5132 1751
29b0f896
AM		 1752 /* Intel Syntax. */
1753 case 'd':
1754 if (intel_syntax)
1755 {
9306ca4a 1756 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 1757 i.suffix = SHORT_MNEM_SUFFIX;
1758 else
1759 i.suffix = LONG_MNEM_SUFFIX;
1760 mnem_p[-1] = '\0';
1761 current_templates = hash_find (op_hash, mnemonic);
1762 }
1763 break;
1764 }
1765 if (!current_templates)
1766 {
1767 as_bad (_("no such instruction: `%s'"), token_start);
1768 return NULL;
1769 }
1770 }
252b5132 1771
29b0f896
AM		 1772 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1773 {
1774 /* Check for a branch hint. We allow ",pt" and ",pn" for
1775 predict taken and predict not taken respectively.
1776 I'm not sure that branch hints actually do anything on loop
1777 and jcxz insns (JumpByte) for current Pentium4 chips. They
1778 may work in the future and it doesn't hurt to accept them
1779 now. */
1780 if (l[0] == ',' && l[1] == 'p')
1781 {
1782 if (l[2] == 't')
1783 {
1784 if (!add_prefix (DS_PREFIX_OPCODE))
1785 return NULL;
1786 l += 3;
1787 }
1788 else if (l[2] == 'n')
1789 {
1790 if (!add_prefix (CS_PREFIX_OPCODE))
1791 return NULL;
1792 l += 3;
1793 }
1794 }
1795 }
1796 /* Any other comma loses. */
1797 if (*l == ',')
1798 {
1799 as_bad (_("invalid character %s in mnemonic"),
1800 output_invalid (*l));
1801 return NULL;
1802 }
252b5132 1803
29b0f896 1804 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 1805 supported = 0;
1806 for (t = current_templates->start; t < current_templates->end; ++t)
1807 {
1808 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
1809 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
1810 supported |= 1;
1811 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
1812 supported |= 2;
1813 }
1814 if (!(supported & 2))
1815 {
1816 as_bad (flag_code == CODE_64BIT
1817 ? _("`%s' is not supported in 64-bit mode")
1818 : _("`%s' is only supported in 64-bit mode"),
1819 current_templates->start->name);
1820 return NULL;
1821 }
1822 if (!(supported & 1))
29b0f896 1823 {
5c6af06e
JB		 1824 as_warn (_("`%s' is not supported on `%s%s'"),
1825 current_templates->start->name,
1826 cpu_arch_name,
1827 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 1828 }
1829 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1830 {
1831 as_warn (_("use .code16 to ensure correct addressing mode"));
1832 }
252b5132 1833
29b0f896 1834 /* Check for rep/repne without a string instruction. */
f41bbced 1835 if (expecting_string_instruction)
29b0f896 1836 {
f41bbced
JB		 1837 static templates override;
1838
1839 for (t = current_templates->start; t < current_templates->end; ++t)
1840 if (t->opcode_modifier & IsString)
1841 break;
1842 if (t >= current_templates->end)
1843 {
1844 as_bad (_("expecting string instruction after `%s'"),
1845 expecting_string_instruction);
1846 return NULL;
1847 }
1848 for (override.start = t; t < current_templates->end; ++t)
1849 if (!(t->opcode_modifier & IsString))
1850 break;
1851 override.end = t;
1852 current_templates = &override;
29b0f896 1853 }
252b5132 1854
29b0f896
AM		 1855 return l;
1856}
252b5132 1857
29b0f896
AM		 1858static char *
1859parse_operands (l, mnemonic)
1860 char *l;
1861 const char *mnemonic;
1862{
1863 char *token_start;
3138f287 1864
29b0f896
AM		 1865 /* 1 if operand is pending after ','. */
1866 unsigned int expecting_operand = 0;
252b5132 1867
29b0f896
AM		 1868 /* Non-zero if operand parens not balanced. */
1869 unsigned int paren_not_balanced;
1870
1871 while (*l != END_OF_INSN)
1872 {
1873 /* Skip optional white space before operand. */
1874 if (is_space_char (*l))
1875 ++l;
1876 if (!is_operand_char (*l) && *l != END_OF_INSN)
1877 {
1878 as_bad (_("invalid character %s before operand %d"),
1879 output_invalid (*l),
1880 i.operands + 1);
1881 return NULL;
1882 }
1883 token_start = l; /* after white space */
1884 paren_not_balanced = 0;
1885 while (paren_not_balanced || *l != ',')
1886 {
1887 if (*l == END_OF_INSN)
1888 {
1889 if (paren_not_balanced)
1890 {
1891 if (!intel_syntax)
1892 as_bad (_("unbalanced parenthesis in operand %d."),
1893 i.operands + 1);
1894 else
1895 as_bad (_("unbalanced brackets in operand %d."),
1896 i.operands + 1);
1897 return NULL;
1898 }
1899 else
1900 break; /* we are done */
1901 }
1902 else if (!is_operand_char (*l) && !is_space_char (*l))
1903 {
1904 as_bad (_("invalid character %s in operand %d"),
1905 output_invalid (*l),
1906 i.operands + 1);
1907 return NULL;
1908 }
1909 if (!intel_syntax)
1910 {
1911 if (*l == '(')
1912 ++paren_not_balanced;
1913 if (*l == ')')
1914 --paren_not_balanced;
1915 }
1916 else
1917 {
1918 if (*l == '[')
1919 ++paren_not_balanced;
1920 if (*l == ']')
1921 --paren_not_balanced;
1922 }
1923 l++;
1924 }
1925 if (l != token_start)
1926 { /* Yes, we've read in another operand. */
1927 unsigned int operand_ok;
1928 this_operand = i.operands++;
1929 if (i.operands > MAX_OPERANDS)
1930 {
1931 as_bad (_("spurious operands; (%d operands/instruction max)"),
1932 MAX_OPERANDS);
1933 return NULL;
1934 }
1935 /* Now parse operand adding info to 'i' as we go along. */
1936 END_STRING_AND_SAVE (l);
1937
1938 if (intel_syntax)
1939 operand_ok =
1940 i386_intel_operand (token_start,
1941 intel_float_operand (mnemonic));
1942 else
1943 operand_ok = i386_operand (token_start);
1944
1945 RESTORE_END_STRING (l);
1946 if (!operand_ok)
1947 return NULL;
1948 }
1949 else
1950 {
1951 if (expecting_operand)
1952 {
1953 expecting_operand_after_comma:
1954 as_bad (_("expecting operand after ','; got nothing"));
1955 return NULL;
1956 }
1957 if (*l == ',')
1958 {
1959 as_bad (_("expecting operand before ','; got nothing"));
1960 return NULL;
1961 }
1962 }
7f3f1ea2 1963
29b0f896
AM		 1964 /* Now *l must be either ',' or END_OF_INSN. */
1965 if (*l == ',')
1966 {
1967 if (*++l == END_OF_INSN)
1968 {
1969 /* Just skip it, if it's \n complain. */
1970 goto expecting_operand_after_comma;
1971 }
1972 expecting_operand = 1;
1973 }
1974 }
1975 return l;
1976}
7f3f1ea2 1977
29b0f896
AM		 1978static void
1979swap_operands ()
1980{
1981 union i386_op temp_op;
1982 unsigned int temp_type;
f86103b7 1983 enum bfd_reloc_code_real temp_reloc;
29b0f896
AM		 1984 int xchg1 = 0;
1985 int xchg2 = 0;
252b5132 1986
29b0f896
AM		 1987 if (i.operands == 2)
1988 {
1989 xchg1 = 0;
1990 xchg2 = 1;
1991 }
1992 else if (i.operands == 3)
1993 {
1994 xchg1 = 0;
1995 xchg2 = 2;
1996 }
1997 temp_type = i.types[xchg2];
1998 i.types[xchg2] = i.types[xchg1];
1999 i.types[xchg1] = temp_type;
2000 temp_op = i.op[xchg2];
2001 i.op[xchg2] = i.op[xchg1];
2002 i.op[xchg1] = temp_op;
2003 temp_reloc = i.reloc[xchg2];
2004 i.reloc[xchg2] = i.reloc[xchg1];
2005 i.reloc[xchg1] = temp_reloc;
2006
2007 if (i.mem_operands == 2)
2008 {
2009 const seg_entry *temp_seg;
2010 temp_seg = i.seg[0];
2011 i.seg[0] = i.seg[1];
2012 i.seg[1] = temp_seg;
2013 }
2014}
252b5132 2015
29b0f896
AM		 2016/* Try to ensure constant immediates are represented in the smallest
2017 opcode possible. */
2018static void
2019optimize_imm ()
2020{
2021 char guess_suffix = 0;
2022 int op;
252b5132 2023
29b0f896
AM		 2024 if (i.suffix)
2025 guess_suffix = i.suffix;
2026 else if (i.reg_operands)
2027 {
2028 /* Figure out a suffix from the last register operand specified.
2029 We can't do this properly yet, ie. excluding InOutPortReg,
2030 but the following works for instructions with immediates.
2031 In any case, we can't set i.suffix yet. */
2032 for (op = i.operands; --op >= 0;)
2033 if (i.types[op] & Reg)
252b5132 2034 {
29b0f896
AM		 2035 if (i.types[op] & Reg8)
2036 guess_suffix = BYTE_MNEM_SUFFIX;
2037 else if (i.types[op] & Reg16)
2038 guess_suffix = WORD_MNEM_SUFFIX;
2039 else if (i.types[op] & Reg32)
2040 guess_suffix = LONG_MNEM_SUFFIX;
2041 else if (i.types[op] & Reg64)
2042 guess_suffix = QWORD_MNEM_SUFFIX;
2043 break;
252b5132 2044 }
29b0f896
AM		 2045 }
2046 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2047 guess_suffix = WORD_MNEM_SUFFIX;
2048
2049 for (op = i.operands; --op >= 0;)
2050 if (i.types[op] & Imm)
2051 {
2052 switch (i.op[op].imms->X_op)
252b5132 2053 {
29b0f896
AM		 2054 case O_constant:
2055 /* If a suffix is given, this operand may be shortened. */
2056 switch (guess_suffix)
252b5132 2057 {
29b0f896
AM		 2058 case LONG_MNEM_SUFFIX:
2059 i.types[op] |= Imm32 | Imm64;
2060 break;
2061 case WORD_MNEM_SUFFIX:
2062 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2063 break;
2064 case BYTE_MNEM_SUFFIX:
2065 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2066 break;
252b5132 2067 }
252b5132 2068
29b0f896
AM		 2069 /* If this operand is at most 16 bits, convert it
2070 to a signed 16 bit number before trying to see
2071 whether it will fit in an even smaller size.
2072 This allows a 16-bit operand such as $0xffe0 to
2073 be recognised as within Imm8S range. */
2074 if ((i.types[op] & Imm16)
2075 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2076 {
29b0f896
AM		 2077 i.op[op].imms->X_add_number =
2078 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2079 }
2080 if ((i.types[op] & Imm32)
2081 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2082 == 0))
2083 {
2084 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2085 ^ ((offsetT) 1 << 31))
2086 - ((offsetT) 1 << 31));
2087 }
2088 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2089
29b0f896
AM		 2090 /* We must avoid matching of Imm32 templates when 64bit
2091 only immediate is available. */
2092 if (guess_suffix == QWORD_MNEM_SUFFIX)
2093 i.types[op] &= ~Imm32;
2094 break;
252b5132 2095
29b0f896
AM		 2096 case O_absent:
2097 case O_register:
2098 abort ();
2099
2100 /* Symbols and expressions. */
2101 default:
9cd96992
JB		 2102 /* Convert symbolic operand to proper sizes for matching, but don't
2103 prevent matching a set of insns that only supports sizes other
2104 than those matching the insn suffix. */
2105 {
2106 unsigned int mask, allowed = 0;
2107 const template *t;
2108
2109 for (t = current_templates->start; t < current_templates->end; ++t)
2110 allowed |= t->operand_types[op];
2111 switch (guess_suffix)
2112 {
2113 case QWORD_MNEM_SUFFIX:
2114 mask = Imm64 | Imm32S;
2115 break;
2116 case LONG_MNEM_SUFFIX:
2117 mask = Imm32;
2118 break;
2119 case WORD_MNEM_SUFFIX:
2120 mask = Imm16;
2121 break;
2122 case BYTE_MNEM_SUFFIX:
2123 mask = Imm8;
2124 break;
2125 default:
2126 mask = 0;
2127 break;
2128 }
2129 if (mask & allowed)
2130 i.types[op] &= mask;
2131 }
29b0f896 2132 break;
252b5132 2133 }
29b0f896
AM		 2134 }
2135}
47926f60 2136
29b0f896
AM		 2137/* Try to use the smallest displacement type too. */
2138static void
2139optimize_disp ()
2140{
2141 int op;
3e73aa7c 2142
29b0f896 2143 for (op = i.operands; --op >= 0;)
b300c311 2144 if (i.types[op] & Disp)
252b5132 2145 {
b300c311 2146 if (i.op[op].disps->X_op == O_constant)
252b5132 2147 {
b300c311 2148 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2149
b300c311
L		 2150 if ((i.types[op] & Disp16)
2151 && (disp & ~(offsetT) 0xffff) == 0)
2152 {
2153 /* If this operand is at most 16 bits, convert
2154 to a signed 16 bit number and don't use 64bit
2155 displacement. */
2156 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2157 i.types[op] &= ~Disp64;
2158 }
2159 if ((i.types[op] & Disp32)
2160 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2161 {
2162 /* If this operand is at most 32 bits, convert
2163 to a signed 32 bit number and don't use 64bit
2164 displacement. */
2165 disp &= (((offsetT) 2 << 31) - 1);
2166 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2167 i.types[op] &= ~Disp64;
2168 }
2169 if (!disp && (i.types[op] & BaseIndex))
2170 {
2171 i.types[op] &= ~Disp;
2172 i.op[op].disps = 0;
2173 i.disp_operands--;
2174 }
2175 else if (flag_code == CODE_64BIT)
2176 {
2177 if (fits_in_signed_long (disp))
28a9d8f5
L		 2178 {
2179 i.types[op] &= ~Disp64;
2180 i.types[op] |= Disp32S;
2181 }
b300c311
L		 2182 if (fits_in_unsigned_long (disp))
2183 i.types[op] |= Disp32;
2184 }
2185 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2186 && fits_in_signed_byte (disp))
2187 i.types[op] |= Disp8;
252b5132 2188 }
b300c311
L		 2189 else
2190 /* We only support 64bit displacement on constants. */
2191 i.types[op] &= ~Disp64;
252b5132 2192 }
29b0f896
AM		 2193}
2194
2195static int
2196match_template ()
2197{
2198 /* Points to template once we've found it. */
2199 const template *t;
2200 unsigned int overlap0, overlap1, overlap2;
2201 unsigned int found_reverse_match;
2202 int suffix_check;
2203
2204#define MATCH(overlap, given, template) \
2205 ((overlap & ~JumpAbsolute) \
2206 && (((given) & (BaseIndex | JumpAbsolute)) \
2207 == ((overlap) & (BaseIndex | JumpAbsolute))))
2208
2209 /* If given types r0 and r1 are registers they must be of the same type
2210 unless the expected operand type register overlap is null.
2211 Note that Acc in a template matches every size of reg. */
2212#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2213 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2214 || ((g0) & Reg) == ((g1) & Reg) \
2215 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2216
2217 overlap0 = 0;
2218 overlap1 = 0;
2219 overlap2 = 0;
2220 found_reverse_match = 0;
2221 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2222 ? No_bSuf
2223 : (i.suffix == WORD_MNEM_SUFFIX
2224 ? No_wSuf
2225 : (i.suffix == SHORT_MNEM_SUFFIX
2226 ? No_sSuf
2227 : (i.suffix == LONG_MNEM_SUFFIX
2228 ? No_lSuf
2229 : (i.suffix == QWORD_MNEM_SUFFIX
2230 ? No_qSuf
2231 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2232 ? No_xSuf : 0))))));
2233
20f0a1fc
NC		 2234 t = current_templates->start;
2235 if (i.suffix == QWORD_MNEM_SUFFIX
2236 && flag_code != CODE_64BIT
9306ca4a
JB		 2237 && (intel_syntax
2238 ? !(t->opcode_modifier & IgnoreSize)
2239 && !intel_float_operand (t->name)
2240 : intel_float_operand (t->name) != 2)
20f0a1fc
NC		 2241 && (!(t->operand_types[0] & (RegMMX | RegXMM))
2242 || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2243 && (t->base_opcode != 0x0fc7
2244 || t->extension_opcode != 1 /* cmpxchg8b */))
2245 t = current_templates->end;
2246 for (; t < current_templates->end; t++)
29b0f896
AM		 2247 {
2248 /* Must have right number of operands. */
2249 if (i.operands != t->operands)
2250 continue;
2251
2252 /* Check the suffix, except for some instructions in intel mode. */
2253 if ((t->opcode_modifier & suffix_check)
2254 && !(intel_syntax
9306ca4a 2255 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2256 continue;
2257
2258 /* Do not verify operands when there are none. */
2259 else if (!t->operands)
2260 {
2261 if (t->cpu_flags & ~cpu_arch_flags)
2262 continue;
2263 /* We've found a match; break out of loop. */
2264 break;
2265 }
252b5132 2266
29b0f896
AM		 2267 overlap0 = i.types[0] & t->operand_types[0];
2268 switch (t->operands)
2269 {
2270 case 1:
2271 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2272 continue;
2273 break;
2274 case 2:
2275 case 3:
2276 overlap1 = i.types[1] & t->operand_types[1];
2277 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2278 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2279 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2280 t->operand_types[0],
2281 overlap1, i.types[1],
2282 t->operand_types[1]))
2283 {
2284 /* Check if other direction is valid ... */
2285 if ((t->opcode_modifier & (D | FloatD)) == 0)
2286 continue;
2287
2288 /* Try reversing direction of operands. */
2289 overlap0 = i.types[0] & t->operand_types[1];
2290 overlap1 = i.types[1] & t->operand_types[0];
2291 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2292 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2293 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2294 t->operand_types[1],
2295 overlap1, i.types[1],
2296 t->operand_types[0]))
2297 {
2298 /* Does not match either direction. */
2299 continue;
2300 }
2301 /* found_reverse_match holds which of D or FloatDR
2302 we've found. */
2303 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2304 }
2305 /* Found a forward 2 operand match here. */
2306 else if (t->operands == 3)
2307 {
2308 /* Here we make use of the fact that there are no
2309 reverse match 3 operand instructions, and all 3
2310 operand instructions only need to be checked for
2311 register consistency between operands 2 and 3. */
2312 overlap2 = i.types[2] & t->operand_types[2];
2313 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2314 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2315 t->operand_types[1],
2316 overlap2, i.types[2],
2317 t->operand_types[2]))
2318
2319 continue;
2320 }
2321 /* Found either forward/reverse 2 or 3 operand match here:
2322 slip through to break. */
2323 }
2324 if (t->cpu_flags & ~cpu_arch_flags)
2325 {
2326 found_reverse_match = 0;
2327 continue;
2328 }
2329 /* We've found a match; break out of loop. */
2330 break;
2331 }
2332
2333 if (t == current_templates->end)
2334 {
2335 /* We found no match. */
2336 as_bad (_("suffix or operands invalid for `%s'"),
2337 current_templates->start->name);
2338 return 0;
2339 }
252b5132 2340
29b0f896
AM		 2341 if (!quiet_warnings)
2342 {
2343 if (!intel_syntax
2344 && ((i.types[0] & JumpAbsolute)
2345 != (t->operand_types[0] & JumpAbsolute)))
2346 {
2347 as_warn (_("indirect %s without `*'"), t->name);
2348 }
2349
2350 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2351 == (IsPrefix | IgnoreSize))
2352 {
2353 /* Warn them that a data or address size prefix doesn't
2354 affect assembly of the next line of code. */
2355 as_warn (_("stand-alone `%s' prefix"), t->name);
2356 }
2357 }
2358
2359 /* Copy the template we found. */
2360 i.tm = *t;
2361 if (found_reverse_match)
2362 {
2363 /* If we found a reverse match we must alter the opcode
2364 direction bit. found_reverse_match holds bits to change
2365 (different for int & float insns). */
2366
2367 i.tm.base_opcode ^= found_reverse_match;
2368
2369 i.tm.operand_types[0] = t->operand_types[1];
2370 i.tm.operand_types[1] = t->operand_types[0];
2371 }
2372
2373 return 1;
2374}
2375
2376static int
2377check_string ()
2378{
2379 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2380 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2381 {
2382 if (i.seg[0] != NULL && i.seg[0] != &es)
2383 {
2384 as_bad (_("`%s' operand %d must use `%%es' segment"),
2385 i.tm.name,
2386 mem_op + 1);
2387 return 0;
2388 }
2389 /* There's only ever one segment override allowed per instruction.
2390 This instruction possibly has a legal segment override on the
2391 second operand, so copy the segment to where non-string
2392 instructions store it, allowing common code. */
2393 i.seg[0] = i.seg[1];
2394 }
2395 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2396 {
2397 if (i.seg[1] != NULL && i.seg[1] != &es)
2398 {
2399 as_bad (_("`%s' operand %d must use `%%es' segment"),
2400 i.tm.name,
2401 mem_op + 2);
2402 return 0;
2403 }
2404 }
2405 return 1;
2406}
2407
2408static int
543613e9 2409process_suffix (void)
29b0f896
AM		 2410{
2411 /* If matched instruction specifies an explicit instruction mnemonic
2412 suffix, use it. */
2413 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2414 {
2415 if (i.tm.opcode_modifier & Size16)
2416 i.suffix = WORD_MNEM_SUFFIX;
2417 else if (i.tm.opcode_modifier & Size64)
2418 i.suffix = QWORD_MNEM_SUFFIX;
2419 else
2420 i.suffix = LONG_MNEM_SUFFIX;
2421 }
2422 else if (i.reg_operands)
2423 {
2424 /* If there's no instruction mnemonic suffix we try to invent one
2425 based on register operands. */
2426 if (!i.suffix)
2427 {
2428 /* We take i.suffix from the last register operand specified,
2429 Destination register type is more significant than source
2430 register type. */
2431 int op;
543613e9 2432
29b0f896
AM		 2433 for (op = i.operands; --op >= 0;)
2434 if ((i.types[op] & Reg)
2435 && !(i.tm.operand_types[op] & InOutPortReg))
2436 {
2437 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2438 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2439 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2440 LONG_MNEM_SUFFIX);
2441 break;
2442 }
2443 }
2444 else if (i.suffix == BYTE_MNEM_SUFFIX)
2445 {
2446 if (!check_byte_reg ())
2447 return 0;
2448 }
2449 else if (i.suffix == LONG_MNEM_SUFFIX)
2450 {
2451 if (!check_long_reg ())
2452 return 0;
2453 }
2454 else if (i.suffix == QWORD_MNEM_SUFFIX)
2455 {
2456 if (!check_qword_reg ())
2457 return 0;
2458 }
2459 else if (i.suffix == WORD_MNEM_SUFFIX)
2460 {
2461 if (!check_word_reg ())
2462 return 0;
2463 }
2464 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2465 /* Do nothing if the instruction is going to ignore the prefix. */
2466 ;
2467 else
2468 abort ();
2469 }
9306ca4a
JB		 2470 else if ((i.tm.opcode_modifier & DefaultSize)
2471 && !i.suffix
2472 /* exclude fldenv/frstor/fsave/fstenv */
2473 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2474 {
2475 i.suffix = stackop_size;
2476 }
9306ca4a
JB		 2477 else if (intel_syntax
2478 && !i.suffix
2479 && ((i.tm.operand_types[0] & JumpAbsolute)
2480 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2481 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2482 && i.tm.extension_opcode <= 3)))
2483 {
2484 switch (flag_code)
2485 {
2486 case CODE_64BIT:
2487 if (!(i.tm.opcode_modifier & No_qSuf))
2488 {
2489 i.suffix = QWORD_MNEM_SUFFIX;
2490 break;
2491 }
2492 case CODE_32BIT:
2493 if (!(i.tm.opcode_modifier & No_lSuf))
2494 i.suffix = LONG_MNEM_SUFFIX;
2495 break;
2496 case CODE_16BIT:
2497 if (!(i.tm.opcode_modifier & No_wSuf))
2498 i.suffix = WORD_MNEM_SUFFIX;
2499 break;
2500 }
2501 }
252b5132 2502
9306ca4a 2503 if (!i.suffix)
29b0f896 2504 {
9306ca4a
JB		 2505 if (!intel_syntax)
2506 {
2507 if (i.tm.opcode_modifier & W)
2508 {
2509 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2510 return 0;
2511 }
2512 }
2513 else
2514 {
2515 unsigned int suffixes = ~i.tm.opcode_modifier
2516 & (No_bSuf
2517 | No_wSuf
2518 | No_lSuf
2519 | No_sSuf
2520 | No_xSuf
2521 | No_qSuf);
2522
2523 if ((i.tm.opcode_modifier & W)
2524 || ((suffixes & (suffixes - 1))
2525 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2526 {
2527 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2528 return 0;
2529 }
2530 }
29b0f896 2531 }
252b5132 2532
9306ca4a
JB		 2533 /* Change the opcode based on the operand size given by i.suffix;
2534 We don't need to change things for byte insns. */
2535
29b0f896
AM		 2536 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2537 {
2538 /* It's not a byte, select word/dword operation. */
2539 if (i.tm.opcode_modifier & W)
2540 {
2541 if (i.tm.opcode_modifier & ShortForm)
2542 i.tm.base_opcode |= 8;
2543 else
2544 i.tm.base_opcode |= 1;
2545 }
0f3f3d8b 2546
29b0f896
AM		 2547 /* Now select between word & dword operations via the operand
2548 size prefix, except for instructions that will ignore this
2549 prefix anyway. */
2550 if (i.suffix != QWORD_MNEM_SUFFIX
9306ca4a
JB		 2551 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2552 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
9146926a
AM		 2553 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2554 || (flag_code == CODE_64BIT
2555 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2556 {
2557 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 2558
29b0f896
AM		 2559 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2560 prefix = ADDR_PREFIX_OPCODE;
252b5132 2561
29b0f896
AM		 2562 if (!add_prefix (prefix))
2563 return 0;
24eab124 2564 }
252b5132 2565
29b0f896
AM		 2566 /* Set mode64 for an operand. */
2567 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2568 && flag_code == CODE_64BIT
29b0f896 2569 && (i.tm.opcode_modifier & NoRex64) == 0)
9146926a 2570 i.rex |= REX_MODE64;
3e73aa7c 2571
29b0f896
AM		 2572 /* Size floating point instruction. */
2573 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 2574 if (i.tm.opcode_modifier & FloatMF)
2575 i.tm.base_opcode ^= 4;
29b0f896 2576 }
7ecd2f8b 2577
29b0f896
AM		 2578 return 1;
2579}
3e73aa7c 2580
29b0f896 2581static int
543613e9 2582check_byte_reg (void)
29b0f896
AM		 2583{
2584 int op;
543613e9 2585
29b0f896
AM		 2586 for (op = i.operands; --op >= 0;)
2587 {
2588 /* If this is an eight bit register, it's OK. If it's the 16 or
2589 32 bit version of an eight bit register, we will just use the
2590 low portion, and that's OK too. */
2591 if (i.types[op] & Reg8)
2592 continue;
2593
2594 /* movzx and movsx should not generate this warning. */
2595 if (intel_syntax
2596 && (i.tm.base_opcode == 0xfb7
2597 || i.tm.base_opcode == 0xfb6
2598 || i.tm.base_opcode == 0x63
2599 || i.tm.base_opcode == 0xfbe
2600 || i.tm.base_opcode == 0xfbf))
2601 continue;
2602
65ec77d2 2603 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 2604 {
2605 /* Prohibit these changes in the 64bit mode, since the
2606 lowering is more complicated. */
2607 if (flag_code == CODE_64BIT
2608 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2609 {
0f3f3d8b 2610 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2611 i.op[op].regs->reg_name,
2612 i.suffix);
2613 return 0;
2614 }
2615#if REGISTER_WARNINGS
2616 if (!quiet_warnings
2617 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2618 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2619 (i.op[op].regs + (i.types[op] & Reg16
2620 ? REGNAM_AL - REGNAM_AX
2621 : REGNAM_AL - REGNAM_EAX))->reg_name,
2622 i.op[op].regs->reg_name,
2623 i.suffix);
2624#endif
2625 continue;
2626 }
2627 /* Any other register is bad. */
2628 if (i.types[op] & (Reg | RegMMX | RegXMM
2629 | SReg2 | SReg3
2630 | Control | Debug | Test
2631 | FloatReg | FloatAcc))
2632 {
2633 as_bad (_("`%%%s' not allowed with `%s%c'"),
2634 i.op[op].regs->reg_name,
2635 i.tm.name,
2636 i.suffix);
2637 return 0;
2638 }
2639 }
2640 return 1;
2641}
2642
2643static int
2644check_long_reg ()
2645{
2646 int op;
2647
2648 for (op = i.operands; --op >= 0;)
2649 /* Reject eight bit registers, except where the template requires
2650 them. (eg. movzb) */
2651 if ((i.types[op] & Reg8) != 0
2652 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2653 {
2654 as_bad (_("`%%%s' not allowed with `%s%c'"),
2655 i.op[op].regs->reg_name,
2656 i.tm.name,
2657 i.suffix);
2658 return 0;
2659 }
2660 /* Warn if the e prefix on a general reg is missing. */
2661 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2662 && (i.types[op] & Reg16) != 0
2663 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2664 {
2665 /* Prohibit these changes in the 64bit mode, since the
2666 lowering is more complicated. */
2667 if (flag_code == CODE_64BIT)
252b5132 2668 {
0f3f3d8b 2669 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2670 i.op[op].regs->reg_name,
2671 i.suffix);
2672 return 0;
252b5132 2673 }
29b0f896
AM		 2674#if REGISTER_WARNINGS
2675 else
2676 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2677 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2678 i.op[op].regs->reg_name,
2679 i.suffix);
2680#endif
252b5132 2681 }
29b0f896
AM		 2682 /* Warn if the r prefix on a general reg is missing. */
2683 else if ((i.types[op] & Reg64) != 0
2684 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 2685 {
0f3f3d8b 2686 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2687 i.op[op].regs->reg_name,
2688 i.suffix);
2689 return 0;
2690 }
2691 return 1;
2692}
252b5132 2693
29b0f896
AM		 2694static int
2695check_qword_reg ()
2696{
2697 int op;
252b5132 2698
29b0f896
AM		 2699 for (op = i.operands; --op >= 0; )
2700 /* Reject eight bit registers, except where the template requires
2701 them. (eg. movzb) */
2702 if ((i.types[op] & Reg8) != 0
2703 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2704 {
2705 as_bad (_("`%%%s' not allowed with `%s%c'"),
2706 i.op[op].regs->reg_name,
2707 i.tm.name,
2708 i.suffix);
2709 return 0;
2710 }
2711 /* Warn if the e prefix on a general reg is missing. */
2712 else if (((i.types[op] & Reg16) != 0
2713 || (i.types[op] & Reg32) != 0)
2714 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2715 {
2716 /* Prohibit these changes in the 64bit mode, since the
2717 lowering is more complicated. */
0f3f3d8b 2718 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2719 i.op[op].regs->reg_name,
2720 i.suffix);
2721 return 0;
252b5132 2722 }
29b0f896
AM		 2723 return 1;
2724}
252b5132 2725
29b0f896
AM		 2726static int
2727check_word_reg ()
2728{
2729 int op;
2730 for (op = i.operands; --op >= 0;)
2731 /* Reject eight bit registers, except where the template requires
2732 them. (eg. movzb) */
2733 if ((i.types[op] & Reg8) != 0
2734 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2735 {
2736 as_bad (_("`%%%s' not allowed with `%s%c'"),
2737 i.op[op].regs->reg_name,
2738 i.tm.name,
2739 i.suffix);
2740 return 0;
2741 }
2742 /* Warn if the e prefix on a general reg is present. */
2743 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2744 && (i.types[op] & Reg32) != 0
2745 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 2746 {
29b0f896
AM		 2747 /* Prohibit these changes in the 64bit mode, since the
2748 lowering is more complicated. */
2749 if (flag_code == CODE_64BIT)
252b5132 2750 {
0f3f3d8b 2751 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2752 i.op[op].regs->reg_name,
2753 i.suffix);
2754 return 0;
252b5132 2755 }
29b0f896
AM		 2756 else
2757#if REGISTER_WARNINGS
2758 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2759 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2760 i.op[op].regs->reg_name,
2761 i.suffix);
2762#endif
2763 }
2764 return 1;
2765}
252b5132 2766
29b0f896
AM		 2767static int
2768finalize_imm ()
2769{
2770 unsigned int overlap0, overlap1, overlap2;
2771
2772 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 2773 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 2774 && overlap0 != Imm8 && overlap0 != Imm8S
2775 && overlap0 != Imm16 && overlap0 != Imm32S
2776 && overlap0 != Imm32 && overlap0 != Imm64)
2777 {
2778 if (i.suffix)
2779 {
2780 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2781 ? Imm8 | Imm8S
2782 : (i.suffix == WORD_MNEM_SUFFIX
2783 ? Imm16
2784 : (i.suffix == QWORD_MNEM_SUFFIX
2785 ? Imm64 | Imm32S
2786 : Imm32)));
2787 }
2788 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2789 || overlap0 == (Imm16 | Imm32)
2790 || overlap0 == (Imm16 | Imm32S))
2791 {
2792 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2793 ? Imm16 : Imm32S);
2794 }
2795 if (overlap0 != Imm8 && overlap0 != Imm8S
2796 && overlap0 != Imm16 && overlap0 != Imm32S
2797 && overlap0 != Imm32 && overlap0 != Imm64)
2798 {
2799 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2800 return 0;
2801 }
2802 }
2803 i.types[0] = overlap0;
2804
2805 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 2806 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 2807 && overlap1 != Imm8 && overlap1 != Imm8S
2808 && overlap1 != Imm16 && overlap1 != Imm32S
2809 && overlap1 != Imm32 && overlap1 != Imm64)
2810 {
2811 if (i.suffix)
2812 {
2813 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2814 ? Imm8 | Imm8S
2815 : (i.suffix == WORD_MNEM_SUFFIX
2816 ? Imm16
2817 : (i.suffix == QWORD_MNEM_SUFFIX
2818 ? Imm64 | Imm32S
2819 : Imm32)));
2820 }
2821 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2822 || overlap1 == (Imm16 | Imm32)
2823 || overlap1 == (Imm16 | Imm32S))
2824 {
2825 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2826 ? Imm16 : Imm32S);
2827 }
2828 if (overlap1 != Imm8 && overlap1 != Imm8S
2829 && overlap1 != Imm16 && overlap1 != Imm32S
2830 && overlap1 != Imm32 && overlap1 != Imm64)
2831 {
2832 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2833 return 0;
2834 }
2835 }
2836 i.types[1] = overlap1;
2837
2838 overlap2 = i.types[2] & i.tm.operand_types[2];
2839 assert ((overlap2 & Imm) == 0);
2840 i.types[2] = overlap2;
2841
2842 return 1;
2843}
2844
2845static int
2846process_operands ()
2847{
2848 /* Default segment register this instruction will use for memory
2849 accesses. 0 means unknown. This is only for optimizing out
2850 unnecessary segment overrides. */
2851 const seg_entry *default_seg = 0;
2852
2853 /* The imul $imm, %reg instruction is converted into
2854 imul $imm, %reg, %reg, and the clr %reg instruction
2855 is converted into xor %reg, %reg. */
2856 if (i.tm.opcode_modifier & regKludge)
2857 {
2858 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2859 /* Pretend we saw the extra register operand. */
2860 assert (i.op[first_reg_op + 1].regs == 0);
2861 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2862 i.types[first_reg_op + 1] = i.types[first_reg_op];
2863 i.reg_operands = 2;
2864 }
2865
2866 if (i.tm.opcode_modifier & ShortForm)
2867 {
2868 /* The register or float register operand is in operand 0 or 1. */
2869 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2870 /* Register goes in low 3 bits of opcode. */
2871 i.tm.base_opcode |= i.op[op].regs->reg_num;
2872 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2873 i.rex |= REX_EXTZ;
2874 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2875 {
2876 /* Warn about some common errors, but press on regardless.
2877 The first case can be generated by gcc (<= 2.8.1). */
2878 if (i.operands == 2)
2879 {
2880 /* Reversed arguments on faddp, fsubp, etc. */
2881 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2882 i.op[1].regs->reg_name,
2883 i.op[0].regs->reg_name);
2884 }
2885 else
2886 {
2887 /* Extraneous `l' suffix on fp insn. */
2888 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2889 i.op[0].regs->reg_name);
2890 }
2891 }
2892 }
2893 else if (i.tm.opcode_modifier & Modrm)
2894 {
2895 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 2896 must be put into the modrm byte). Now, we make the modrm and
2897 index base bytes based on all the info we've collected. */
29b0f896
AM		 2898
2899 default_seg = build_modrm_byte ();
2900 }
2901 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2902 {
2903 if (i.tm.base_opcode == POP_SEG_SHORT
2904 && i.op[0].regs->reg_num == 1)
2905 {
2906 as_bad (_("you can't `pop %%cs'"));
2907 return 0;
2908 }
2909 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2910 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2911 i.rex |= REX_EXTZ;
2912 }
2913 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2914 {
2915 default_seg = &ds;
2916 }
2917 else if ((i.tm.opcode_modifier & IsString) != 0)
2918 {
2919 /* For the string instructions that allow a segment override
2920 on one of their operands, the default segment is ds. */
2921 default_seg = &ds;
2922 }
2923
30123838
JB		 2924 if ((i.tm.base_opcode == 0x8d /* lea */
2925 || (i.tm.cpu_flags & CpuSVME))
2926 && i.seg[0] && !quiet_warnings)
2927 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 2928
2929 /* If a segment was explicitly specified, and the specified segment
2930 is not the default, use an opcode prefix to select it. If we
2931 never figured out what the default segment is, then default_seg
2932 will be zero at this point, and the specified segment prefix will
2933 always be used. */
29b0f896
AM		 2934 if ((i.seg[0]) && (i.seg[0] != default_seg))
2935 {
2936 if (!add_prefix (i.seg[0]->seg_prefix))
2937 return 0;
2938 }
2939 return 1;
2940}
2941
2942static const seg_entry *
2943build_modrm_byte ()
2944{
2945 const seg_entry *default_seg = 0;
2946
2947 /* i.reg_operands MUST be the number of real register operands;
2948 implicit registers do not count. */
2949 if (i.reg_operands == 2)
2950 {
2951 unsigned int source, dest;
2952 source = ((i.types[0]
2953 & (Reg | RegMMX | RegXMM
2954 | SReg2 | SReg3
2955 | Control | Debug | Test))
2956 ? 0 : 1);
2957 dest = source + 1;
2958
2959 i.rm.mode = 3;
2960 /* One of the register operands will be encoded in the i.tm.reg
2961 field, the other in the combined i.tm.mode and i.tm.regmem
2962 fields. If no form of this instruction supports a memory
2963 destination operand, then we assume the source operand may
2964 sometimes be a memory operand and so we need to store the
2965 destination in the i.rm.reg field. */
2966 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2967 {
2968 i.rm.reg = i.op[dest].regs->reg_num;
2969 i.rm.regmem = i.op[source].regs->reg_num;
2970 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2971 i.rex |= REX_EXTX;
2972 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2973 i.rex |= REX_EXTZ;
2974 }
2975 else
2976 {
2977 i.rm.reg = i.op[source].regs->reg_num;
2978 i.rm.regmem = i.op[dest].regs->reg_num;
2979 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2980 i.rex |= REX_EXTZ;
2981 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2982 i.rex |= REX_EXTX;
2983 }
c4a530c5
JB		 2984 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
2985 {
2986 if (!((i.types[0] | i.types[1]) & Control))
2987 abort ();
2988 i.rex &= ~(REX_EXTX | REX_EXTZ);
2989 add_prefix (LOCK_PREFIX_OPCODE);
2990 }
29b0f896
AM		 2991 }
2992 else
2993 { /* If it's not 2 reg operands... */
2994 if (i.mem_operands)
2995 {
2996 unsigned int fake_zero_displacement = 0;
2997 unsigned int op = ((i.types[0] & AnyMem)
2998 ? 0
2999 : (i.types[1] & AnyMem) ? 1 : 2);
3000
3001 default_seg = &ds;
3002
3003 if (i.base_reg == 0)
3004 {
3005 i.rm.mode = 0;
3006 if (!i.disp_operands)
3007 fake_zero_displacement = 1;
3008 if (i.index_reg == 0)
3009 {
3010 /* Operand is just <disp> */
20f0a1fc 3011 if (flag_code == CODE_64BIT)
29b0f896
AM		 3012 {
3013 /* 64bit mode overwrites the 32bit absolute
3014 addressing by RIP relative addressing and
3015 absolute addressing is encoded by one of the
3016 redundant SIB forms. */
3017 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3018 i.sib.base = NO_BASE_REGISTER;
3019 i.sib.index = NO_INDEX_REGISTER;
20f0a1fc
NC		 3020 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
3021 }
3022 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3023 {
3024 i.rm.regmem = NO_BASE_REGISTER_16;
3025 i.types[op] = Disp16;
3026 }
3027 else
3028 {
3029 i.rm.regmem = NO_BASE_REGISTER;
3030 i.types[op] = Disp32;
29b0f896
AM		 3031 }
3032 }
3033 else /* !i.base_reg && i.index_reg */
3034 {
3035 i.sib.index = i.index_reg->reg_num;
3036 i.sib.base = NO_BASE_REGISTER;
3037 i.sib.scale = i.log2_scale_factor;
3038 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3039 i.types[op] &= ~Disp;
3040 if (flag_code != CODE_64BIT)
3041 i.types[op] |= Disp32; /* Must be 32 bit */
3042 else
3043 i.types[op] |= Disp32S;
3044 if ((i.index_reg->reg_flags & RegRex) != 0)
3045 i.rex |= REX_EXTY;
3046 }
3047 }
3048 /* RIP addressing for 64bit mode. */
3049 else if (i.base_reg->reg_type == BaseIndex)
3050 {
3051 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3052 i.types[op] &= ~ Disp;
29b0f896
AM		 3053 i.types[op] |= Disp32S;
3054 i.flags[op] = Operand_PCrel;
20f0a1fc
NC		 3055 if (! i.disp_operands)
3056 fake_zero_displacement = 1;
29b0f896
AM		 3057 }
3058 else if (i.base_reg->reg_type & Reg16)
3059 {
3060 switch (i.base_reg->reg_num)
3061 {
3062 case 3: /* (%bx) */
3063 if (i.index_reg == 0)
3064 i.rm.regmem = 7;
3065 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3066 i.rm.regmem = i.index_reg->reg_num - 6;
3067 break;
3068 case 5: /* (%bp) */
3069 default_seg = &ss;
3070 if (i.index_reg == 0)
3071 {
3072 i.rm.regmem = 6;
3073 if ((i.types[op] & Disp) == 0)
3074 {
3075 /* fake (%bp) into 0(%bp) */
3076 i.types[op] |= Disp8;
252b5132 3077 fake_zero_displacement = 1;
29b0f896
AM		 3078 }
3079 }
3080 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3081 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3082 break;
3083 default: /* (%si) -> 4 or (%di) -> 5 */
3084 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3085 }
3086 i.rm.mode = mode_from_disp_size (i.types[op]);
3087 }
3088 else /* i.base_reg and 32/64 bit mode */
3089 {
3090 if (flag_code == CODE_64BIT
3091 && (i.types[op] & Disp))
20f0a1fc
NC		 3092 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
3093
29b0f896
AM		 3094 i.rm.regmem = i.base_reg->reg_num;
3095 if ((i.base_reg->reg_flags & RegRex) != 0)
3096 i.rex |= REX_EXTZ;
3097 i.sib.base = i.base_reg->reg_num;
3098 /* x86-64 ignores REX prefix bit here to avoid decoder
3099 complications. */
3100 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3101 {
3102 default_seg = &ss;
3103 if (i.disp_operands == 0)
3104 {
3105 fake_zero_displacement = 1;
3106 i.types[op] |= Disp8;
3107 }
3108 }
3109 else if (i.base_reg->reg_num == ESP_REG_NUM)
3110 {
3111 default_seg = &ss;
3112 }
3113 i.sib.scale = i.log2_scale_factor;
3114 if (i.index_reg == 0)
3115 {
3116 /* <disp>(%esp) becomes two byte modrm with no index
3117 register. We've already stored the code for esp
3118 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3119 Any base register besides %esp will not use the
3120 extra modrm byte. */
3121 i.sib.index = NO_INDEX_REGISTER;
3122#if !SCALE1_WHEN_NO_INDEX
3123 /* Another case where we force the second modrm byte. */
3124 if (i.log2_scale_factor)
3125 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3126#endif
29b0f896
AM		 3127 }
3128 else
3129 {
3130 i.sib.index = i.index_reg->reg_num;
3131 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3132 if ((i.index_reg->reg_flags & RegRex) != 0)
3133 i.rex |= REX_EXTY;
3134 }
3135 i.rm.mode = mode_from_disp_size (i.types[op]);
3136 }
252b5132 3137
29b0f896
AM		 3138 if (fake_zero_displacement)
3139 {
3140 /* Fakes a zero displacement assuming that i.types[op]
3141 holds the correct displacement size. */
3142 expressionS *exp;
3143
3144 assert (i.op[op].disps == 0);
3145 exp = &disp_expressions[i.disp_operands++];
3146 i.op[op].disps = exp;
3147 exp->X_op = O_constant;
3148 exp->X_add_number = 0;
3149 exp->X_add_symbol = (symbolS *) 0;
3150 exp->X_op_symbol = (symbolS *) 0;
3151 }
3152 }
252b5132 3153
29b0f896
AM		 3154 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3155 (if any) based on i.tm.extension_opcode. Again, we must be
3156 careful to make sure that segment/control/debug/test/MMX
3157 registers are coded into the i.rm.reg field. */
3158 if (i.reg_operands)
3159 {
3160 unsigned int op =
3161 ((i.types[0]
3162 & (Reg | RegMMX | RegXMM
3163 | SReg2 | SReg3
3164 | Control | Debug | Test))
3165 ? 0
3166 : ((i.types[1]
3167 & (Reg | RegMMX | RegXMM
3168 | SReg2 | SReg3
3169 | Control | Debug | Test))
3170 ? 1
3171 : 2));
3172 /* If there is an extension opcode to put here, the register
3173 number must be put into the regmem field. */
3174 if (i.tm.extension_opcode != None)
3175 {
3176 i.rm.regmem = i.op[op].regs->reg_num;
3177 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3178 i.rex |= REX_EXTZ;
3179 }
3180 else
3181 {
3182 i.rm.reg = i.op[op].regs->reg_num;
3183 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3184 i.rex |= REX_EXTX;
3185 }
252b5132 3186
29b0f896
AM		 3187 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3188 must set it to 3 to indicate this is a register operand
3189 in the regmem field. */
3190 if (!i.mem_operands)
3191 i.rm.mode = 3;
3192 }
252b5132 3193
29b0f896
AM		 3194 /* Fill in i.rm.reg field with extension opcode (if any). */
3195 if (i.tm.extension_opcode != None)
3196 i.rm.reg = i.tm.extension_opcode;
3197 }
3198 return default_seg;
3199}
252b5132 3200
29b0f896
AM		 3201static void
3202output_branch ()
3203{
3204 char *p;
3205 int code16;
3206 int prefix;
3207 relax_substateT subtype;
3208 symbolS *sym;
3209 offsetT off;
3210
3211 code16 = 0;
3212 if (flag_code == CODE_16BIT)
3213 code16 = CODE16;
3214
3215 prefix = 0;
3216 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3217 {
29b0f896
AM		 3218 prefix = 1;
3219 i.prefixes -= 1;
3220 code16 ^= CODE16;
252b5132 3221 }
29b0f896
AM		 3222 /* Pentium4 branch hints. */
3223 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3224 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3225 {
29b0f896
AM		 3226 prefix++;
3227 i.prefixes--;
3228 }
3229 if (i.prefix[REX_PREFIX] != 0)
3230 {
3231 prefix++;
3232 i.prefixes--;
2f66722d
AM		 3233 }
3234
29b0f896
AM		 3235 if (i.prefixes != 0 && !intel_syntax)
3236 as_warn (_("skipping prefixes on this instruction"));
3237
3238 /* It's always a symbol; End frag & setup for relax.
3239 Make sure there is enough room in this frag for the largest
3240 instruction we may generate in md_convert_frag. This is 2
3241 bytes for the opcode and room for the prefix and largest
3242 displacement. */
3243 frag_grow (prefix + 2 + 4);
3244 /* Prefix and 1 opcode byte go in fr_fix. */
3245 p = frag_more (prefix + 1);
3246 if (i.prefix[DATA_PREFIX] != 0)
3247 *p++ = DATA_PREFIX_OPCODE;
3248 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3249 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3250 *p++ = i.prefix[SEG_PREFIX];
3251 if (i.prefix[REX_PREFIX] != 0)
3252 *p++ = i.prefix[REX_PREFIX];
3253 *p = i.tm.base_opcode;
3254
3255 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3256 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3257 else if ((cpu_arch_flags & Cpu386) != 0)
3258 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3259 else
3260 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3261 subtype |= code16;
3e73aa7c 3262
29b0f896
AM		 3263 sym = i.op[0].disps->X_add_symbol;
3264 off = i.op[0].disps->X_add_number;
3e73aa7c 3265
29b0f896
AM		 3266 if (i.op[0].disps->X_op != O_constant
3267 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3268 {
29b0f896
AM		 3269 /* Handle complex expressions. */
3270 sym = make_expr_symbol (i.op[0].disps);
3271 off = 0;
3272 }
3e73aa7c 3273
29b0f896
AM		 3274 /* 1 possible extra opcode + 4 byte displacement go in var part.
3275 Pass reloc in fr_var. */
3276 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3277}
3e73aa7c 3278
29b0f896
AM		 3279static void
3280output_jump ()
3281{
3282 char *p;
3283 int size;
3e02c1cc 3284 fixS *fixP;
29b0f896
AM		 3285
3286 if (i.tm.opcode_modifier & JumpByte)
3287 {
3288 /* This is a loop or jecxz type instruction. */
3289 size = 1;
3290 if (i.prefix[ADDR_PREFIX] != 0)
3291 {
3292 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3293 i.prefixes -= 1;
3294 }
3295 /* Pentium4 branch hints. */
3296 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3297 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3298 {
3299 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3300 i.prefixes--;
3e73aa7c
JH		 3301 }
3302 }
29b0f896
AM		 3303 else
3304 {
3305 int code16;
3e73aa7c 3306
29b0f896
AM		 3307 code16 = 0;
3308 if (flag_code == CODE_16BIT)
3309 code16 = CODE16;
3e73aa7c 3310
29b0f896
AM		 3311 if (i.prefix[DATA_PREFIX] != 0)
3312 {
3313 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3314 i.prefixes -= 1;
3315 code16 ^= CODE16;
3316 }
252b5132 3317
29b0f896
AM		 3318 size = 4;
3319 if (code16)
3320 size = 2;
3321 }
9fcc94b6 3322
29b0f896
AM		 3323 if (i.prefix[REX_PREFIX] != 0)
3324 {
3325 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3326 i.prefixes -= 1;
3327 }
252b5132 3328
29b0f896
AM		 3329 if (i.prefixes != 0 && !intel_syntax)
3330 as_warn (_("skipping prefixes on this instruction"));
e0890092 3331
29b0f896
AM		 3332 p = frag_more (1 + size);
3333 *p++ = i.tm.base_opcode;
e0890092 3334
3e02c1cc
AM		 3335 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3336 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3337
3338 /* All jumps handled here are signed, but don't use a signed limit
3339 check for 32 and 16 bit jumps as we want to allow wrap around at
3340 4G and 64k respectively. */
3341 if (size == 1)
3342 fixP->fx_signed = 1;
29b0f896 3343}
e0890092 3344
29b0f896
AM		 3345static void
3346output_interseg_jump ()
3347{
3348 char *p;
3349 int size;
3350 int prefix;
3351 int code16;
252b5132 3352
29b0f896
AM		 3353 code16 = 0;
3354 if (flag_code == CODE_16BIT)
3355 code16 = CODE16;
a217f122 3356
29b0f896
AM		 3357 prefix = 0;
3358 if (i.prefix[DATA_PREFIX] != 0)
3359 {
3360 prefix = 1;
3361 i.prefixes -= 1;
3362 code16 ^= CODE16;
3363 }
3364 if (i.prefix[REX_PREFIX] != 0)
3365 {
3366 prefix++;
3367 i.prefixes -= 1;
3368 }
252b5132 3369
29b0f896
AM		 3370 size = 4;
3371 if (code16)
3372 size = 2;
252b5132 3373
29b0f896
AM		 3374 if (i.prefixes != 0 && !intel_syntax)
3375 as_warn (_("skipping prefixes on this instruction"));
252b5132 3376
29b0f896
AM		 3377 /* 1 opcode; 2 segment; offset */
3378 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3379
29b0f896
AM		 3380 if (i.prefix[DATA_PREFIX] != 0)
3381 *p++ = DATA_PREFIX_OPCODE;
252b5132 3382
29b0f896
AM		 3383 if (i.prefix[REX_PREFIX] != 0)
3384 *p++ = i.prefix[REX_PREFIX];
252b5132 3385
29b0f896
AM		 3386 *p++ = i.tm.base_opcode;
3387 if (i.op[1].imms->X_op == O_constant)
3388 {
3389 offsetT n = i.op[1].imms->X_add_number;
252b5132 3390
29b0f896
AM		 3391 if (size == 2
3392 && !fits_in_unsigned_word (n)
3393 && !fits_in_signed_word (n))
3394 {
3395 as_bad (_("16-bit jump out of range"));
3396 return;
3397 }
3398 md_number_to_chars (p, n, size);
3399 }
3400 else
3401 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3402 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3403 if (i.op[0].imms->X_op != O_constant)
3404 as_bad (_("can't handle non absolute segment in `%s'"),
3405 i.tm.name);
3406 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3407}
a217f122 3408
29b0f896
AM		 3409static void
3410output_insn ()
3411{
2bbd9c25
JJ		 3412 fragS *insn_start_frag;
3413 offsetT insn_start_off;
3414
29b0f896
AM		 3415 /* Tie dwarf2 debug info to the address at the start of the insn.
3416 We can't do this after the insn has been output as the current
3417 frag may have been closed off. eg. by frag_var. */
3418 dwarf2_emit_insn (0);
3419
2bbd9c25
JJ		 3420 insn_start_frag = frag_now;
3421 insn_start_off = frag_now_fix ();
3422
29b0f896
AM		 3423 /* Output jumps. */
3424 if (i.tm.opcode_modifier & Jump)
3425 output_branch ();
3426 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3427 output_jump ();
3428 else if (i.tm.opcode_modifier & JumpInterSegment)
3429 output_interseg_jump ();
3430 else
3431 {
3432 /* Output normal instructions here. */
3433 char *p;
3434 unsigned char *q;
252b5132 3435
bc4bd9ab
MK		 3436 /* All opcodes on i386 have either 1 or 2 bytes. We may use one
3437 more higher byte to specify a prefix the instruction
3438 requires. */
3439 if ((i.tm.base_opcode & 0xff0000) != 0)
3440 {
3441 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3442 {
3443 unsigned int prefix;
3444 prefix = (i.tm.base_opcode >> 16) & 0xff;
3445
3446 if (prefix != REPE_PREFIX_OPCODE
3447 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3448 add_prefix (prefix);
3449 }
3450 else
3451 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
0f10071e 3452 }
252b5132 3453
29b0f896
AM		 3454 /* The prefix bytes. */
3455 for (q = i.prefix;
3456 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3457 q++)
3458 {
3459 if (*q)
3460 {
3461 p = frag_more (1);
3462 md_number_to_chars (p, (valueT) *q, 1);
3463 }
3464 }
252b5132 3465
29b0f896
AM		 3466 /* Now the opcode; be careful about word order here! */
3467 if (fits_in_unsigned_byte (i.tm.base_opcode))
3468 {
3469 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3470 }
3471 else
3472 {
bc4bd9ab 3473 p = frag_more (2);
0f10071e 3474
29b0f896
AM		 3475 /* Put out high byte first: can't use md_number_to_chars! */
3476 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3477 *p = i.tm.base_opcode & 0xff;
3478 }
3e73aa7c 3479
29b0f896
AM		 3480 /* Now the modrm byte and sib byte (if present). */
3481 if (i.tm.opcode_modifier & Modrm)
3482 {
3483 p = frag_more (1);
3484 md_number_to_chars (p,
3485 (valueT) (i.rm.regmem << 0
3486 | i.rm.reg << 3
3487 | i.rm.mode << 6),
3488 1);
3489 /* If i.rm.regmem == ESP (4)
3490 && i.rm.mode != (Register mode)
3491 && not 16 bit
3492 ==> need second modrm byte. */
3493 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3494 && i.rm.mode != 3
3495 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3496 {
3497 p = frag_more (1);
3498 md_number_to_chars (p,
3499 (valueT) (i.sib.base << 0
3500 | i.sib.index << 3
3501 | i.sib.scale << 6),
3502 1);
3503 }
3504 }
3e73aa7c 3505
29b0f896 3506 if (i.disp_operands)
2bbd9c25 3507 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3508
29b0f896 3509 if (i.imm_operands)
2bbd9c25 3510 output_imm (insn_start_frag, insn_start_off);
29b0f896 3511 }
252b5132 3512
29b0f896
AM		 3513#ifdef DEBUG386
3514 if (flag_debug)
3515 {
3516 pi (line, &i);
3517 }
3518#endif /* DEBUG386 */
3519}
252b5132 3520
29b0f896 3521static void
2bbd9c25
JJ		 3522output_disp (insn_start_frag, insn_start_off)
3523 fragS *insn_start_frag;
3524 offsetT insn_start_off;
29b0f896
AM		 3525{
3526 char *p;
3527 unsigned int n;
252b5132 3528
29b0f896
AM		 3529 for (n = 0; n < i.operands; n++)
3530 {
3531 if (i.types[n] & Disp)
3532 {
3533 if (i.op[n].disps->X_op == O_constant)
3534 {
3535 int size;
3536 offsetT val;
252b5132 3537
29b0f896
AM		 3538 size = 4;
3539 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3540 {
3541 size = 2;
3542 if (i.types[n] & Disp8)
3543 size = 1;
3544 if (i.types[n] & Disp64)
3545 size = 8;
3546 }
3547 val = offset_in_range (i.op[n].disps->X_add_number,
3548 size);
3549 p = frag_more (size);
3550 md_number_to_chars (p, val, size);
3551 }
3552 else
3553 {
f86103b7 3554 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3555 int size = 4;
3556 int sign = 0;
3557 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3558
3559 /* The PC relative address is computed relative
3560 to the instruction boundary, so in case immediate
3561 fields follows, we need to adjust the value. */
3562 if (pcrel && i.imm_operands)
3563 {
3564 int imm_size = 4;
3565 unsigned int n1;
252b5132 3566
29b0f896
AM		 3567 for (n1 = 0; n1 < i.operands; n1++)
3568 if (i.types[n1] & Imm)
252b5132 3569 {
29b0f896 3570 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 3571 {
29b0f896
AM		 3572 imm_size = 2;
3573 if (i.types[n1] & (Imm8 | Imm8S))
3574 imm_size = 1;
3575 if (i.types[n1] & Imm64)
3576 imm_size = 8;
252b5132 3577 }
29b0f896 3578 break;
252b5132 3579 }
29b0f896
AM		 3580 /* We should find the immediate. */
3581 if (n1 == i.operands)
3582 abort ();
3583 i.op[n].disps->X_add_number -= imm_size;
3584 }
520dc8e8 3585
29b0f896
AM		 3586 if (i.types[n] & Disp32S)
3587 sign = 1;
3e73aa7c 3588
29b0f896
AM		 3589 if (i.types[n] & (Disp16 | Disp64))
3590 {
3591 size = 2;
3592 if (i.types[n] & Disp64)
3593 size = 8;
3594 }
520dc8e8 3595
29b0f896 3596 p = frag_more (size);
2bbd9c25 3597 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 3598 if (GOT_symbol
2bbd9c25 3599 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113
JB		 3600 && (((reloc_type == BFD_RELOC_32
3601 || reloc_type == BFD_RELOC_X86_64_32S)
3602 && (i.op[n].disps->X_op == O_symbol
3603 || (i.op[n].disps->X_op == O_add
3604 && ((symbol_get_value_expression
3605 (i.op[n].disps->X_op_symbol)->X_op)
3606 == O_subtract))))
3607 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 3608 {
3609 offsetT add;
3610
3611 if (insn_start_frag == frag_now)
3612 add = (p - frag_now->fr_literal) - insn_start_off;
3613 else
3614 {
3615 fragS *fr;
3616
3617 add = insn_start_frag->fr_fix - insn_start_off;
3618 for (fr = insn_start_frag->fr_next;
3619 fr && fr != frag_now; fr = fr->fr_next)
3620 add += fr->fr_fix;
3621 add += p - frag_now->fr_literal;
3622 }
3623
4fa24527 3624 if (!object_64bit)
d6ab8113
JB		 3625 reloc_type = BFD_RELOC_386_GOTPC;
3626 else
3627 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25
JJ		 3628 i.op[n].disps->X_add_number += add;
3629 }
062cd5e7 3630 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 3631 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 3632 }
3633 }
3634 }
3635}
252b5132 3636
29b0f896 3637static void
2bbd9c25
JJ		 3638output_imm (insn_start_frag, insn_start_off)
3639 fragS *insn_start_frag;
3640 offsetT insn_start_off;
29b0f896
AM		 3641{
3642 char *p;
3643 unsigned int n;
252b5132 3644
29b0f896
AM		 3645 for (n = 0; n < i.operands; n++)
3646 {
3647 if (i.types[n] & Imm)
3648 {
3649 if (i.op[n].imms->X_op == O_constant)
3650 {
3651 int size;
3652 offsetT val;
b4cac588 3653
29b0f896
AM		 3654 size = 4;
3655 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3656 {
3657 size = 2;
3658 if (i.types[n] & (Imm8 | Imm8S))
3659 size = 1;
3660 else if (i.types[n] & Imm64)
3661 size = 8;
3662 }
3663 val = offset_in_range (i.op[n].imms->X_add_number,
3664 size);
3665 p = frag_more (size);
3666 md_number_to_chars (p, val, size);
3667 }
3668 else
3669 {
3670 /* Not absolute_section.
3671 Need a 32-bit fixup (don't support 8bit
3672 non-absolute imms). Try to support other
3673 sizes ... */
f86103b7 3674 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3675 int size = 4;
3676 int sign = 0;
3677
3678 if ((i.types[n] & (Imm32S))
a7d61044
JB		 3679 && (i.suffix == QWORD_MNEM_SUFFIX
3680 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 3681 sign = 1;
3682 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3683 {
3684 size = 2;
3685 if (i.types[n] & (Imm8 | Imm8S))
3686 size = 1;
3687 if (i.types[n] & Imm64)
3688 size = 8;
3689 }
520dc8e8 3690
29b0f896
AM		 3691 p = frag_more (size);
3692 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 3693
2bbd9c25
JJ		 3694 /* This is tough to explain. We end up with this one if we
3695 * have operands that look like
3696 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3697 * obtain the absolute address of the GOT, and it is strongly
3698 * preferable from a performance point of view to avoid using
3699 * a runtime relocation for this. The actual sequence of
3700 * instructions often look something like:
3701 *
3702 * call .L66
3703 * .L66:
3704 * popl %ebx
3705 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3706 *
3707 * The call and pop essentially return the absolute address
3708 * of the label .L66 and store it in %ebx. The linker itself
3709 * will ultimately change the first operand of the addl so
3710 * that %ebx points to the GOT, but to keep things simple, the
3711 * .o file must have this operand set so that it generates not
3712 * the absolute address of .L66, but the absolute address of
3713 * itself. This allows the linker itself simply treat a GOTPC
3714 * relocation as asking for a pcrel offset to the GOT to be
3715 * added in, and the addend of the relocation is stored in the
3716 * operand field for the instruction itself.
3717 *
3718 * Our job here is to fix the operand so that it would add
3719 * the correct offset so that %ebx would point to itself. The
3720 * thing that is tricky is that .-.L66 will point to the
3721 * beginning of the instruction, so we need to further modify
3722 * the operand so that it will point to itself. There are
3723 * other cases where you have something like:
3724 *
3725 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3726 *
3727 * and here no correction would be required. Internally in
3728 * the assembler we treat operands of this form as not being
3729 * pcrel since the '.' is explicitly mentioned, and I wonder
3730 * whether it would simplify matters to do it this way. Who
3731 * knows. In earlier versions of the PIC patches, the
3732 * pcrel_adjust field was used to store the correction, but
3733 * since the expression is not pcrel, I felt it would be
3734 * confusing to do it this way. */
3735
d6ab8113
JB		 3736 if ((reloc_type == BFD_RELOC_32
3737 || reloc_type == BFD_RELOC_X86_64_32S)
29b0f896
AM		 3738 && GOT_symbol
3739 && GOT_symbol == i.op[n].imms->X_add_symbol
3740 && (i.op[n].imms->X_op == O_symbol
3741 || (i.op[n].imms->X_op == O_add
3742 && ((symbol_get_value_expression
3743 (i.op[n].imms->X_op_symbol)->X_op)
3744 == O_subtract))))
3745 {
2bbd9c25
JJ		 3746 offsetT add;
3747
3748 if (insn_start_frag == frag_now)
3749 add = (p - frag_now->fr_literal) - insn_start_off;
3750 else
3751 {
3752 fragS *fr;
3753
3754 add = insn_start_frag->fr_fix - insn_start_off;
3755 for (fr = insn_start_frag->fr_next;
3756 fr && fr != frag_now; fr = fr->fr_next)
3757 add += fr->fr_fix;
3758 add += p - frag_now->fr_literal;
3759 }
3760
4fa24527 3761 if (!object_64bit)
d6ab8113
JB		 3762 reloc_type = BFD_RELOC_386_GOTPC;
3763 else
3764 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 3765 i.op[n].imms->X_add_number += add;
29b0f896 3766 }
29b0f896
AM		 3767 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3768 i.op[n].imms, 0, reloc_type);
3769 }
3770 }
3771 }
252b5132
RH		 3772}
3773\f
d182319b
JB		 3774/* x86_cons_fix_new is called via the expression parsing code when a
3775 reloc is needed. We use this hook to get the correct .got reloc. */
3776static enum bfd_reloc_code_real got_reloc = NO_RELOC;
3777static int cons_sign = -1;
3778
3779void
3780x86_cons_fix_new (fragS *frag,
3781 unsigned int off,
3782 unsigned int len,
3783 expressionS *exp)
3784{
3785 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
3786
3787 got_reloc = NO_RELOC;
3788
3789#ifdef TE_PE
3790 if (exp->X_op == O_secrel)
3791 {
3792 exp->X_op = O_symbol;
3793 r = BFD_RELOC_32_SECREL;
3794 }
3795#endif
3796
3797 fix_new_exp (frag, off, len, exp, 0, r);
3798}
3799
718ddfc0
JB		 3800#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
3801# define lex_got(reloc, adjust, types) NULL
3802#else
f3c180ae
AM		 3803/* Parse operands of the form
3804 <symbol>@GOTOFF+<nnn>
3805 and similar .plt or .got references.
3806
3807 If we find one, set up the correct relocation in RELOC and copy the
3808 input string, minus the `@GOTOFF' into a malloc'd buffer for
3809 parsing by the calling routine. Return this buffer, and if ADJUST
3810 is non-null set it to the length of the string we removed from the
3811 input line. Otherwise return NULL. */
3812static char *
3956db08
JB		 3813lex_got (enum bfd_reloc_code_real *reloc,
3814 int *adjust,
3815 unsigned int *types)
f3c180ae 3816{
f3c180ae
AM		 3817 static const struct {
3818 const char *str;
4fa24527 3819 const enum bfd_reloc_code_real rel[2];
3956db08 3820 const unsigned int types64;
f3c180ae 3821 } gotrel[] = {
4fa24527
JB		 3822 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
3823 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
3824 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
3825 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
3826 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 },
3827 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
3828 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
3829 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
3830 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 },
3831 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
3832 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 },
3833 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 },
3834 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32 }
f3c180ae
AM		 3835 };
3836 char *cp;
3837 unsigned int j;
3838
718ddfc0
JB		 3839 if (!IS_ELF)
3840 return NULL;
3841
f3c180ae
AM		 3842 for (cp = input_line_pointer; *cp != '@'; cp++)
3843 if (is_end_of_line[(unsigned char) *cp])
3844 return NULL;
3845
3846 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3847 {
3848 int len;
3849
3850 len = strlen (gotrel[j].str);
28f81592 3851 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 3852 {
4fa24527 3853 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 3854 {
28f81592
AM		 3855 int first, second;
3856 char *tmpbuf, *past_reloc;
f3c180ae 3857
4fa24527 3858 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 3859 if (adjust)
3860 *adjust = len;
f3c180ae 3861
3956db08
JB		 3862 if (types)
3863 {
3864 if (flag_code != CODE_64BIT)
3865 *types = Imm32|Disp32;
3866 else
3867 *types = gotrel[j].types64;
3868 }
3869
f3c180ae
AM		 3870 if (GOT_symbol == NULL)
3871 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3872
3873 /* Replace the relocation token with ' ', so that
3874 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 3875
3876 /* The length of the first part of our input line. */
f3c180ae 3877 first = cp - input_line_pointer;
28f81592
AM		 3878
3879 /* The second part goes from after the reloc token until
3880 (and including) an end_of_line char. Don't use strlen
3881 here as the end_of_line char may not be a NUL. */
3882 past_reloc = cp + 1 + len;
3883 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3884 ;
3885 second = cp - past_reloc;
3886
3887 /* Allocate and copy string. The trailing NUL shouldn't
3888 be necessary, but be safe. */
3889 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 3890 memcpy (tmpbuf, input_line_pointer, first);
3891 tmpbuf[first] = ' ';
28f81592
AM		 3892 memcpy (tmpbuf + first + 1, past_reloc, second);
3893 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 3894 return tmpbuf;
3895 }
3896
4fa24527
JB		 3897 as_bad (_("@%s reloc is not supported with %d-bit output format"),
3898 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 3899 return NULL;
3900 }
3901 }
3902
3903 /* Might be a symbol version string. Don't as_bad here. */
3904 return NULL;
3905}
3906
f3c180ae
AM		 3907void
3908x86_cons (exp, size)
3909 expressionS *exp;
3910 int size;
3911{
4fa24527 3912 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 3913 {
3914 /* Handle @GOTOFF and the like in an expression. */
3915 char *save;
3916 char *gotfree_input_line;
3917 int adjust;
3918
3919 save = input_line_pointer;
3956db08 3920 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 3921 if (gotfree_input_line)
3922 input_line_pointer = gotfree_input_line;
3923
3924 expression (exp);
3925
3926 if (gotfree_input_line)
3927 {
3928 /* expression () has merrily parsed up to the end of line,
3929 or a comma - in the wrong buffer. Transfer how far
3930 input_line_pointer has moved to the right buffer. */
3931 input_line_pointer = (save
3932 + (input_line_pointer - gotfree_input_line)
3933 + adjust);
3934 free (gotfree_input_line);
3935 }
3936 }
3937 else
3938 expression (exp);
3939}
3940#endif
3941
d182319b 3942static void signed_cons (int size)
6482c264 3943{
d182319b
JB		 3944 if (flag_code == CODE_64BIT)
3945 cons_sign = 1;
3946 cons (size);
3947 cons_sign = -1;
6482c264
NC		 3948}
3949
d182319b 3950#ifdef TE_PE
6482c264
NC		 3951static void
3952pe_directive_secrel (dummy)
3953 int dummy ATTRIBUTE_UNUSED;
3954{
3955 expressionS exp;
3956
3957 do
3958 {
3959 expression (&exp);
3960 if (exp.X_op == O_symbol)
3961 exp.X_op = O_secrel;
3962
3963 emit_expr (&exp, 4);
3964 }
3965 while (*input_line_pointer++ == ',');
3966
3967 input_line_pointer--;
3968 demand_empty_rest_of_line ();
3969}
6482c264
NC		 3970#endif
3971
252b5132
RH		 3972static int i386_immediate PARAMS ((char *));
3973
3974static int
3975i386_immediate (imm_start)
3976 char *imm_start;
3977{
3978 char *save_input_line_pointer;
f3c180ae 3979 char *gotfree_input_line;
252b5132 3980 segT exp_seg = 0;
47926f60 3981 expressionS *exp;
3956db08 3982 unsigned int types = ~0U;
252b5132
RH		 3983
3984 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3985 {
d0b47220 3986 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 3987 return 0;
3988 }
3989
3990 exp = &im_expressions[i.imm_operands++];
520dc8e8 3991 i.op[this_operand].imms = exp;
252b5132
RH		 3992
3993 if (is_space_char (*imm_start))
3994 ++imm_start;
3995
3996 save_input_line_pointer = input_line_pointer;
3997 input_line_pointer = imm_start;
3998
3956db08 3999 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4000 if (gotfree_input_line)
4001 input_line_pointer = gotfree_input_line;
252b5132
RH		 4002
4003 exp_seg = expression (exp);
4004
83183c0c 4005 SKIP_WHITESPACE ();
252b5132 4006 if (*input_line_pointer)
f3c180ae 4007 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 4008
4009 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4010 if (gotfree_input_line)
4011 free (gotfree_input_line);
252b5132 4012
2daf4fd8 4013 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 4014 {
47926f60 4015 /* Missing or bad expr becomes absolute 0. */
d0b47220 4016 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 4017 imm_start);
252b5132
RH		 4018 exp->X_op = O_constant;
4019 exp->X_add_number = 0;
4020 exp->X_add_symbol = (symbolS *) 0;
4021 exp->X_op_symbol = (symbolS *) 0;
252b5132 4022 }
3e73aa7c 4023 else if (exp->X_op == O_constant)
252b5132 4024 {
47926f60 4025 /* Size it properly later. */
3e73aa7c
JH		 4026 i.types[this_operand] |= Imm64;
4027 /* If BFD64, sign extend val. */
4028 if (!use_rela_relocations)
4029 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4030 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4031 }
4c63da97 4032#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4033 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4034 && exp_seg != absolute_section
47926f60 4035 && exp_seg != text_section
24eab124
AM		 4036 && exp_seg != data_section
4037 && exp_seg != bss_section
4038 && exp_seg != undefined_section
f86103b7 4039 && !bfd_is_com_section (exp_seg))
252b5132 4040 {
d0b47220 4041 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4042 return 0;
4043 }
4044#endif
4045 else
4046 {
4047 /* This is an address. The size of the address will be
24eab124 4048 determined later, depending on destination register,
3e73aa7c
JH		 4049 suffix, or the default for the section. */
4050 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4051 i.types[this_operand] &= types;
252b5132
RH		 4052 }
4053
4054 return 1;
4055}
4056
551c1ca1 4057static char *i386_scale PARAMS ((char *));
252b5132 4058
551c1ca1 4059static char *
252b5132
RH		 4060i386_scale (scale)
4061 char *scale;
4062{
551c1ca1
AM		 4063 offsetT val;
4064 char *save = input_line_pointer;
252b5132 4065
551c1ca1
AM		 4066 input_line_pointer = scale;
4067 val = get_absolute_expression ();
4068
4069 switch (val)
252b5132 4070 {
551c1ca1 4071 case 1:
252b5132
RH		 4072 i.log2_scale_factor = 0;
4073 break;
551c1ca1 4074 case 2:
252b5132
RH		 4075 i.log2_scale_factor = 1;
4076 break;
551c1ca1 4077 case 4:
252b5132
RH		 4078 i.log2_scale_factor = 2;
4079 break;
551c1ca1 4080 case 8:
252b5132
RH		 4081 i.log2_scale_factor = 3;
4082 break;
4083 default:
a724f0f4
JB		 4084 {
4085 char sep = *input_line_pointer;
4086
4087 *input_line_pointer = '\0';
4088 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4089 scale);
4090 *input_line_pointer = sep;
4091 input_line_pointer = save;
4092 return NULL;
4093 }
252b5132 4094 }
29b0f896 4095 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4096 {
4097 as_warn (_("scale factor of %d without an index register"),
24eab124 4098 1 << i.log2_scale_factor);
252b5132
RH		 4099#if SCALE1_WHEN_NO_INDEX
4100 i.log2_scale_factor = 0;
4101#endif
4102 }
551c1ca1
AM		 4103 scale = input_line_pointer;
4104 input_line_pointer = save;
4105 return scale;
252b5132
RH		 4106}
4107
4108static int i386_displacement PARAMS ((char *, char *));
4109
4110static int
4111i386_displacement (disp_start, disp_end)
4112 char *disp_start;
4113 char *disp_end;
4114{
29b0f896 4115 expressionS *exp;
252b5132
RH		 4116 segT exp_seg = 0;
4117 char *save_input_line_pointer;
f3c180ae 4118 char *gotfree_input_line;
e05278af 4119 int bigdisp, override;
3956db08 4120 unsigned int types = Disp;
252b5132 4121
e05278af
JB		 4122 if ((i.types[this_operand] & JumpAbsolute)
4123 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4124 {
4125 bigdisp = Disp32;
4126 override = (i.prefix[ADDR_PREFIX] != 0);
4127 }
4128 else
4129 {
4130 /* For PC-relative branches, the width of the displacement
4131 is dependent upon data size, not address size. */
4132 bigdisp = 0;
4133 override = (i.prefix[DATA_PREFIX] != 0);
4134 }
3e73aa7c 4135 if (flag_code == CODE_64BIT)
7ecd2f8b 4136 {
e05278af
JB		 4137 if (!bigdisp)
4138 bigdisp = (override || i.suffix == WORD_MNEM_SUFFIX)
4139 ? Disp16
4140 : Disp32S | Disp32;
4141 else if (!override)
3956db08 4142 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b 4143 }
e05278af
JB		 4144 else
4145 {
4146 if (!bigdisp)
4147 {
4148 if (!override)
4149 override = (i.suffix == (flag_code != CODE_16BIT
4150 ? WORD_MNEM_SUFFIX
4151 : LONG_MNEM_SUFFIX));
4152 bigdisp = Disp32;
4153 }
4154 if ((flag_code == CODE_16BIT) ^ override)
4155 bigdisp = Disp16;
4156 }
252b5132
RH		 4157 i.types[this_operand] |= bigdisp;
4158
4159 exp = &disp_expressions[i.disp_operands];
520dc8e8 4160 i.op[this_operand].disps = exp;
252b5132
RH		 4161 i.disp_operands++;
4162 save_input_line_pointer = input_line_pointer;
4163 input_line_pointer = disp_start;
4164 END_STRING_AND_SAVE (disp_end);
4165
4166#ifndef GCC_ASM_O_HACK
4167#define GCC_ASM_O_HACK 0
4168#endif
4169#if GCC_ASM_O_HACK
4170 END_STRING_AND_SAVE (disp_end + 1);
4171 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4172 && displacement_string_end[-1] == '+')
252b5132
RH		 4173 {
4174 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4175 constraint within gcc asm statements.
4176 For instance:
4177
4178 #define _set_tssldt_desc(n,addr,limit,type) \
4179 __asm__ __volatile__ ( \
4180 "movw %w2,%0\n\t" \
4181 "movw %w1,2+%0\n\t" \
4182 "rorl $16,%1\n\t" \
4183 "movb %b1,4+%0\n\t" \
4184 "movb %4,5+%0\n\t" \
4185 "movb $0,6+%0\n\t" \
4186 "movb %h1,7+%0\n\t" \
4187 "rorl $16,%1" \
4188 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4189
4190 This works great except that the output assembler ends
4191 up looking a bit weird if it turns out that there is
4192 no offset. You end up producing code that looks like:
4193
4194 #APP
4195 movw $235,(%eax)
4196 movw %dx,2+(%eax)
4197 rorl $16,%edx
4198 movb %dl,4+(%eax)
4199 movb $137,5+(%eax)
4200 movb $0,6+(%eax)
4201 movb %dh,7+(%eax)
4202 rorl $16,%edx
4203 #NO_APP
4204
47926f60 4205 So here we provide the missing zero. */
24eab124
AM		 4206
4207 *displacement_string_end = '0';
252b5132
RH		 4208 }
4209#endif
3956db08 4210 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4211 if (gotfree_input_line)
4212 input_line_pointer = gotfree_input_line;
252b5132 4213
24eab124 4214 exp_seg = expression (exp);
252b5132 4215
636c26b0
AM		 4216 SKIP_WHITESPACE ();
4217 if (*input_line_pointer)
4218 as_bad (_("junk `%s' after expression"), input_line_pointer);
4219#if GCC_ASM_O_HACK
4220 RESTORE_END_STRING (disp_end + 1);
4221#endif
4222 RESTORE_END_STRING (disp_end);
4223 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4224 if (gotfree_input_line)
4225 free (gotfree_input_line);
636c26b0 4226
24eab124
AM		 4227 /* We do this to make sure that the section symbol is in
4228 the symbol table. We will ultimately change the relocation
47926f60 4229 to be relative to the beginning of the section. */
1ae12ab7 4230 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4231 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4232 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4233 {
636c26b0
AM		 4234 if (exp->X_op != O_symbol)
4235 {
4236 as_bad (_("bad expression used with @%s"),
4237 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4238 ? "GOTPCREL"
4239 : "GOTOFF"));
4240 return 0;
4241 }
4242
e5cb08ac 4243 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4244 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4245 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4246 exp->X_op = O_subtract;
4247 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4248 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4249 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4250 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4251 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4252 else
29b0f896 4253 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4254 }
252b5132 4255
2daf4fd8
AM		 4256 if (exp->X_op == O_absent || exp->X_op == O_big)
4257 {
47926f60 4258 /* Missing or bad expr becomes absolute 0. */
d0b47220 4259 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4260 disp_start);
4261 exp->X_op = O_constant;
4262 exp->X_add_number = 0;
4263 exp->X_add_symbol = (symbolS *) 0;
4264 exp->X_op_symbol = (symbolS *) 0;
4265 }
4266
4c63da97 4267#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4268 if (exp->X_op != O_constant
45288df1 4269 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4270 && exp_seg != absolute_section
45288df1
AM		 4271 && exp_seg != text_section
4272 && exp_seg != data_section
4273 && exp_seg != bss_section
31312f95 4274 && exp_seg != undefined_section
f86103b7 4275 && !bfd_is_com_section (exp_seg))
24eab124 4276 {
d0b47220 4277 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4278 return 0;
4279 }
252b5132 4280#endif
3956db08
JB		 4281
4282 if (!(i.types[this_operand] & ~Disp))
4283 i.types[this_operand] &= types;
4284
252b5132
RH		 4285 return 1;
4286}
4287
e5cb08ac 4288static int i386_index_check PARAMS ((const char *));
252b5132 4289
eecb386c 4290/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4291 Return 1 on success, 0 on a failure. */
4292
252b5132 4293static int
eecb386c
AM		 4294i386_index_check (operand_string)
4295 const char *operand_string;
252b5132 4296{
3e73aa7c 4297 int ok;
24eab124 4298#if INFER_ADDR_PREFIX
eecb386c
AM		 4299 int fudged = 0;
4300
24eab124
AM		 4301 tryprefix:
4302#endif
3e73aa7c 4303 ok = 1;
30123838
JB		 4304 if ((current_templates->start->cpu_flags & CpuSVME)
4305 && current_templates->end[-1].operand_types[0] == AnyMem)
4306 {
4307 /* Memory operands of SVME insns are special in that they only allow
4308 rAX as their memory address and ignore any segment override. */
4309 unsigned RegXX;
4310
4311 /* SKINIT is even more restrictive: it always requires EAX. */
4312 if (strcmp (current_templates->start->name, "skinit") == 0)
4313 RegXX = Reg32;
4314 else if (flag_code == CODE_64BIT)
4315 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4316 else
4317 RegXX = (flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4318 ? Reg16
4319 : Reg32;
4320 if (!i.base_reg
4321 || !(i.base_reg->reg_type & Acc)
4322 || !(i.base_reg->reg_type & RegXX)
4323 || i.index_reg
4324 || (i.types[0] & Disp))
4325 ok = 0;
4326 }
4327 else if (flag_code == CODE_64BIT)
20f0a1fc
NC		 4328 {
4329 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4330
4331 if ((i.base_reg
4332 && ((i.base_reg->reg_type & RegXX) == 0)
4333 && (i.base_reg->reg_type != BaseIndex
4334 || i.index_reg))
4335 || (i.index_reg
4336 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4337 != (RegXX | BaseIndex))))
4338 ok = 0;
3e73aa7c
JH		 4339 }
4340 else
4341 {
4342 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4343 {
4344 /* 16bit checks. */
4345 if ((i.base_reg
29b0f896
AM		 4346 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4347 != (Reg16 | BaseIndex)))
3e73aa7c 4348 || (i.index_reg
29b0f896
AM		 4349 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4350 != (Reg16 | BaseIndex))
4351 || !(i.base_reg
4352 && i.base_reg->reg_num < 6
4353 && i.index_reg->reg_num >= 6
4354 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4355 ok = 0;
4356 }
4357 else
e5cb08ac 4358 {
3e73aa7c
JH		 4359 /* 32bit checks. */
4360 if ((i.base_reg
4361 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4362 || (i.index_reg
29b0f896
AM		 4363 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4364 != (Reg32 | BaseIndex))))
e5cb08ac 4365 ok = 0;
3e73aa7c
JH		 4366 }
4367 }
4368 if (!ok)
24eab124
AM		 4369 {
4370#if INFER_ADDR_PREFIX
20f0a1fc 4371 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4372 {
4373 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4374 i.prefixes += 1;
b23bac36
AM		 4375 /* Change the size of any displacement too. At most one of
4376 Disp16 or Disp32 is set.
4377 FIXME. There doesn't seem to be any real need for separate
4378 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4379 Removing them would probably clean up the code quite a lot. */
20f0a1fc 4380 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
29b0f896 4381 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4382 fudged = 1;
24eab124
AM		 4383 goto tryprefix;
4384 }
eecb386c
AM		 4385 if (fudged)
4386 as_bad (_("`%s' is not a valid base/index expression"),
4387 operand_string);
4388 else
c388dee8 4389#endif
eecb386c
AM		 4390 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4391 operand_string,
3e73aa7c 4392 flag_code_names[flag_code]);
24eab124 4393 }
20f0a1fc 4394 return ok;
24eab124 4395}
252b5132 4396
252b5132 4397/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4398 on error. */
252b5132 4399
252b5132
RH		 4400static int
4401i386_operand (operand_string)
4402 char *operand_string;
4403{
af6bdddf
AM		 4404 const reg_entry *r;
4405 char *end_op;
24eab124 4406 char *op_string = operand_string;
252b5132 4407
24eab124 4408 if (is_space_char (*op_string))
252b5132
RH		 4409 ++op_string;
4410
24eab124 4411 /* We check for an absolute prefix (differentiating,
47926f60 4412 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4413 if (*op_string == ABSOLUTE_PREFIX)
4414 {
4415 ++op_string;
4416 if (is_space_char (*op_string))
4417 ++op_string;
4418 i.types[this_operand] |= JumpAbsolute;
4419 }
252b5132 4420
47926f60 4421 /* Check if operand is a register. */
af6bdddf
AM		 4422 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
4423 && (r = parse_register (op_string, &end_op)) != NULL)
24eab124 4424 {
24eab124
AM		 4425 /* Check for a segment override by searching for ':' after a
4426 segment register. */
4427 op_string = end_op;
4428 if (is_space_char (*op_string))
4429 ++op_string;
4430 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4431 {
4432 switch (r->reg_num)
4433 {
4434 case 0:
4435 i.seg[i.mem_operands] = &es;
4436 break;
4437 case 1:
4438 i.seg[i.mem_operands] = &cs;
4439 break;
4440 case 2:
4441 i.seg[i.mem_operands] = &ss;
4442 break;
4443 case 3:
4444 i.seg[i.mem_operands] = &ds;
4445 break;
4446 case 4:
4447 i.seg[i.mem_operands] = &fs;
4448 break;
4449 case 5:
4450 i.seg[i.mem_operands] = &gs;
4451 break;
4452 }
252b5132 4453
24eab124 4454 /* Skip the ':' and whitespace. */
252b5132
RH		 4455 ++op_string;
4456 if (is_space_char (*op_string))
24eab124 4457 ++op_string;
252b5132 4458
24eab124
AM		 4459 if (!is_digit_char (*op_string)
4460 && !is_identifier_char (*op_string)
4461 && *op_string != '('
4462 && *op_string != ABSOLUTE_PREFIX)
4463 {
4464 as_bad (_("bad memory operand `%s'"), op_string);
4465 return 0;
4466 }
47926f60 4467 /* Handle case of %es:*foo. */
24eab124
AM		 4468 if (*op_string == ABSOLUTE_PREFIX)
4469 {
4470 ++op_string;
4471 if (is_space_char (*op_string))
4472 ++op_string;
4473 i.types[this_operand] |= JumpAbsolute;
4474 }
4475 goto do_memory_reference;
4476 }
4477 if (*op_string)
4478 {
d0b47220 4479 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4480 return 0;
4481 }
4482 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 4483 i.op[this_operand].regs = r;
24eab124
AM		 4484 i.reg_operands++;
4485 }
af6bdddf
AM		 4486 else if (*op_string == REGISTER_PREFIX)
4487 {
4488 as_bad (_("bad register name `%s'"), op_string);
4489 return 0;
4490 }
24eab124 4491 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 4492 {
24eab124
AM		 4493 ++op_string;
4494 if (i.types[this_operand] & JumpAbsolute)
4495 {
d0b47220 4496 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4497 return 0;
4498 }
4499 if (!i386_immediate (op_string))
4500 return 0;
4501 }
4502 else if (is_digit_char (*op_string)
4503 || is_identifier_char (*op_string)
e5cb08ac 4504 || *op_string == '(')
24eab124 4505 {
47926f60 4506 /* This is a memory reference of some sort. */
af6bdddf 4507 char *base_string;
252b5132 4508
47926f60 4509 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 4510 char *displacement_string_start;
4511 char *displacement_string_end;
252b5132 4512
24eab124 4513 do_memory_reference:
24eab124
AM		 4514 if ((i.mem_operands == 1
4515 && (current_templates->start->opcode_modifier & IsString) == 0)
4516 || i.mem_operands == 2)
4517 {
4518 as_bad (_("too many memory references for `%s'"),
4519 current_templates->start->name);
4520 return 0;
4521 }
252b5132 4522
24eab124
AM		 4523 /* Check for base index form. We detect the base index form by
4524 looking for an ')' at the end of the operand, searching
4525 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4526 after the '('. */
af6bdddf 4527 base_string = op_string + strlen (op_string);
c3332e24 4528
af6bdddf
AM		 4529 --base_string;
4530 if (is_space_char (*base_string))
4531 --base_string;
252b5132 4532
47926f60 4533 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 4534 displacement_string_start = op_string;
4535 displacement_string_end = base_string + 1;
252b5132 4536
24eab124
AM		 4537 if (*base_string == ')')
4538 {
af6bdddf 4539 char *temp_string;
24eab124
AM		 4540 unsigned int parens_balanced = 1;
4541 /* We've already checked that the number of left & right ()'s are
47926f60 4542 equal, so this loop will not be infinite. */
24eab124
AM		 4543 do
4544 {
4545 base_string--;
4546 if (*base_string == ')')
4547 parens_balanced++;
4548 if (*base_string == '(')
4549 parens_balanced--;
4550 }
4551 while (parens_balanced);
c3332e24 4552
af6bdddf 4553 temp_string = base_string;
c3332e24 4554
24eab124 4555 /* Skip past '(' and whitespace. */
252b5132
RH		 4556 ++base_string;
4557 if (is_space_char (*base_string))
24eab124 4558 ++base_string;
252b5132 4559
af6bdddf
AM		 4560 if (*base_string == ','
4561 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4562 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 4563 {
af6bdddf 4564 displacement_string_end = temp_string;
252b5132 4565
af6bdddf 4566 i.types[this_operand] |= BaseIndex;
252b5132 4567
af6bdddf 4568 if (i.base_reg)
24eab124 4569 {
24eab124
AM		 4570 base_string = end_op;
4571 if (is_space_char (*base_string))
4572 ++base_string;
af6bdddf
AM		 4573 }
4574
4575 /* There may be an index reg or scale factor here. */
4576 if (*base_string == ',')
4577 {
4578 ++base_string;
4579 if (is_space_char (*base_string))
4580 ++base_string;
4581
4582 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4583 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 4584 {
af6bdddf 4585 base_string = end_op;
24eab124
AM		 4586 if (is_space_char (*base_string))
4587 ++base_string;
af6bdddf
AM		 4588 if (*base_string == ',')
4589 {
4590 ++base_string;
4591 if (is_space_char (*base_string))
4592 ++base_string;
4593 }
e5cb08ac 4594 else if (*base_string != ')')
af6bdddf
AM		 4595 {
4596 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4597 operand_string);
4598 return 0;
4599 }
24eab124 4600 }
af6bdddf 4601 else if (*base_string == REGISTER_PREFIX)
24eab124 4602 {
af6bdddf 4603 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 4604 return 0;
4605 }
252b5132 4606
47926f60 4607 /* Check for scale factor. */
551c1ca1 4608 if (*base_string != ')')
af6bdddf 4609 {
551c1ca1
AM		 4610 char *end_scale = i386_scale (base_string);
4611
4612 if (!end_scale)
af6bdddf 4613 return 0;
24eab124 4614
551c1ca1 4615 base_string = end_scale;
af6bdddf
AM		 4616 if (is_space_char (*base_string))
4617 ++base_string;
4618 if (*base_string != ')')
4619 {
4620 as_bad (_("expecting `)' after scale factor in `%s'"),
4621 operand_string);
4622 return 0;
4623 }
4624 }
4625 else if (!i.index_reg)
24eab124 4626 {
af6bdddf
AM		 4627 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4628 *base_string);
24eab124
AM		 4629 return 0;
4630 }
4631 }
af6bdddf 4632 else if (*base_string != ')')
24eab124 4633 {
af6bdddf
AM		 4634 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4635 operand_string);
24eab124
AM		 4636 return 0;
4637 }
c3332e24 4638 }
af6bdddf 4639 else if (*base_string == REGISTER_PREFIX)
c3332e24 4640 {
af6bdddf 4641 as_bad (_("bad register name `%s'"), base_string);
24eab124 4642 return 0;
c3332e24 4643 }
24eab124
AM		 4644 }
4645
4646 /* If there's an expression beginning the operand, parse it,
4647 assuming displacement_string_start and
4648 displacement_string_end are meaningful. */
4649 if (displacement_string_start != displacement_string_end)
4650 {
4651 if (!i386_displacement (displacement_string_start,
4652 displacement_string_end))
4653 return 0;
4654 }
4655
4656 /* Special case for (%dx) while doing input/output op. */
4657 if (i.base_reg
4658 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4659 && i.index_reg == 0
4660 && i.log2_scale_factor == 0
4661 && i.seg[i.mem_operands] == 0
4662 && (i.types[this_operand] & Disp) == 0)
4663 {
4664 i.types[this_operand] = InOutPortReg;
4665 return 1;
4666 }
4667
eecb386c
AM		 4668 if (i386_index_check (operand_string) == 0)
4669 return 0;
24eab124
AM		 4670 i.mem_operands++;
4671 }
4672 else
ce8a8b2f
AM		 4673 {
4674 /* It's not a memory operand; argh! */
24eab124
AM		 4675 as_bad (_("invalid char %s beginning operand %d `%s'"),
4676 output_invalid (*op_string),
4677 this_operand + 1,
4678 op_string);
4679 return 0;
4680 }
47926f60 4681 return 1; /* Normal return. */
252b5132
RH		 4682}
4683\f
ee7fcc42
AM		 4684/* md_estimate_size_before_relax()
4685
4686 Called just before relax() for rs_machine_dependent frags. The x86
4687 assembler uses these frags to handle variable size jump
4688 instructions.
4689
4690 Any symbol that is now undefined will not become defined.
4691 Return the correct fr_subtype in the frag.
4692 Return the initial "guess for variable size of frag" to caller.
4693 The guess is actually the growth beyond the fixed part. Whatever
4694 we do to grow the fixed or variable part contributes to our
4695 returned value. */
4696
252b5132
RH		 4697int
4698md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 4699 fragS *fragP;
4700 segT segment;
252b5132 4701{
252b5132 4702 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 4703 check for un-relaxable symbols. On an ELF system, we can't relax
4704 an externally visible symbol, because it may be overridden by a
4705 shared library. */
4706 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 4707#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 4708 || (IS_ELF
31312f95
AM		 4709 && (S_IS_EXTERNAL (fragP->fr_symbol)
4710 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 4711#endif
4712 )
252b5132 4713 {
b98ef147
AM		 4714 /* Symbol is undefined in this segment, or we need to keep a
4715 reloc so that weak symbols can be overridden. */
4716 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 4717 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 4718 unsigned char *opcode;
4719 int old_fr_fix;
f6af82bd 4720
ee7fcc42
AM		 4721 if (fragP->fr_var != NO_RELOC)
4722 reloc_type = fragP->fr_var;
b98ef147 4723 else if (size == 2)
f6af82bd
AM		 4724 reloc_type = BFD_RELOC_16_PCREL;
4725 else
4726 reloc_type = BFD_RELOC_32_PCREL;
252b5132 4727
ee7fcc42
AM		 4728 old_fr_fix = fragP->fr_fix;
4729 opcode = (unsigned char *) fragP->fr_opcode;
4730
fddf5b5b 4731 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 4732 {
fddf5b5b
AM		 4733 case UNCOND_JUMP:
4734 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 4735 opcode[0] = 0xe9;
252b5132 4736 fragP->fr_fix += size;
062cd5e7
AS		 4737 fix_new (fragP, old_fr_fix, size,
4738 fragP->fr_symbol,
4739 fragP->fr_offset, 1,
4740 reloc_type);
252b5132
RH		 4741 break;
4742
fddf5b5b 4743 case COND_JUMP86:
412167cb
AM		 4744 if (size == 2
4745 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 4746 {
4747 /* Negate the condition, and branch past an
4748 unconditional jump. */
4749 opcode[0] ^= 1;
4750 opcode[1] = 3;
4751 /* Insert an unconditional jump. */
4752 opcode[2] = 0xe9;
4753 /* We added two extra opcode bytes, and have a two byte
4754 offset. */
4755 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 4756 fix_new (fragP, old_fr_fix + 2, 2,
4757 fragP->fr_symbol,
4758 fragP->fr_offset, 1,
4759 reloc_type);
fddf5b5b
AM		 4760 break;
4761 }
4762 /* Fall through. */
4763
4764 case COND_JUMP:
412167cb
AM		 4765 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4766 {
3e02c1cc
AM		 4767 fixS *fixP;
4768
412167cb 4769 fragP->fr_fix += 1;
3e02c1cc
AM		 4770 fixP = fix_new (fragP, old_fr_fix, 1,
4771 fragP->fr_symbol,
4772 fragP->fr_offset, 1,
4773 BFD_RELOC_8_PCREL);
4774 fixP->fx_signed = 1;
412167cb
AM		 4775 break;
4776 }
93c2a809 4777
24eab124 4778 /* This changes the byte-displacement jump 0x7N
fddf5b5b 4779 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 4780 opcode[1] = opcode[0] + 0x10;
f6af82bd 4781 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 4782 /* We've added an opcode byte. */
4783 fragP->fr_fix += 1 + size;
062cd5e7
AS		 4784 fix_new (fragP, old_fr_fix + 1, size,
4785 fragP->fr_symbol,
4786 fragP->fr_offset, 1,
4787 reloc_type);
252b5132 4788 break;
fddf5b5b
AM		 4789
4790 default:
4791 BAD_CASE (fragP->fr_subtype);
4792 break;
252b5132
RH		 4793 }
4794 frag_wane (fragP);
ee7fcc42 4795 return fragP->fr_fix - old_fr_fix;
252b5132 4796 }
93c2a809 4797
93c2a809
AM		 4798 /* Guess size depending on current relax state. Initially the relax
4799 state will correspond to a short jump and we return 1, because
4800 the variable part of the frag (the branch offset) is one byte
4801 long. However, we can relax a section more than once and in that
4802 case we must either set fr_subtype back to the unrelaxed state,
4803 or return the value for the appropriate branch. */
4804 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 4805}
4806
47926f60
KH		 4807/* Called after relax() is finished.
4808
4809 In: Address of frag.
4810 fr_type == rs_machine_dependent.
4811 fr_subtype is what the address relaxed to.
4812
4813 Out: Any fixSs and constants are set up.
4814 Caller will turn frag into a ".space 0". */
4815
252b5132
RH		 4816void
4817md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 4818 bfd *abfd ATTRIBUTE_UNUSED;
4819 segT sec ATTRIBUTE_UNUSED;
29b0f896 4820 fragS *fragP;
252b5132 4821{
29b0f896 4822 unsigned char *opcode;
252b5132 4823 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 4824 offsetT target_address;
4825 offsetT opcode_address;
252b5132 4826 unsigned int extension = 0;
847f7ad4 4827 offsetT displacement_from_opcode_start;
252b5132
RH		 4828
4829 opcode = (unsigned char *) fragP->fr_opcode;
4830
47926f60 4831 /* Address we want to reach in file space. */
252b5132 4832 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 4833
47926f60 4834 /* Address opcode resides at in file space. */
252b5132
RH		 4835 opcode_address = fragP->fr_address + fragP->fr_fix;
4836
47926f60 4837 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 4838 displacement_from_opcode_start = target_address - opcode_address;
4839
fddf5b5b 4840 if ((fragP->fr_subtype & BIG) == 0)
252b5132 4841 {
47926f60
KH		 4842 /* Don't have to change opcode. */
4843 extension = 1; /* 1 opcode + 1 displacement */
252b5132 4844 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 4845 }
4846 else
4847 {
4848 if (no_cond_jump_promotion
4849 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4850 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 4851
fddf5b5b
AM		 4852 switch (fragP->fr_subtype)
4853 {
4854 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4855 extension = 4; /* 1 opcode + 4 displacement */
4856 opcode[0] = 0xe9;
4857 where_to_put_displacement = &opcode[1];
4858 break;
252b5132 4859
fddf5b5b
AM		 4860 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4861 extension = 2; /* 1 opcode + 2 displacement */
4862 opcode[0] = 0xe9;
4863 where_to_put_displacement = &opcode[1];
4864 break;
252b5132 4865
fddf5b5b
AM		 4866 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4867 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4868 extension = 5; /* 2 opcode + 4 displacement */
4869 opcode[1] = opcode[0] + 0x10;
4870 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4871 where_to_put_displacement = &opcode[2];
4872 break;
252b5132 4873
fddf5b5b
AM		 4874 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4875 extension = 3; /* 2 opcode + 2 displacement */
4876 opcode[1] = opcode[0] + 0x10;
4877 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4878 where_to_put_displacement = &opcode[2];
4879 break;
252b5132 4880
fddf5b5b
AM		 4881 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4882 extension = 4;
4883 opcode[0] ^= 1;
4884 opcode[1] = 3;
4885 opcode[2] = 0xe9;
4886 where_to_put_displacement = &opcode[3];
4887 break;
4888
4889 default:
4890 BAD_CASE (fragP->fr_subtype);
4891 break;
4892 }
252b5132 4893 }
fddf5b5b 4894
47926f60 4895 /* Now put displacement after opcode. */
252b5132
RH		 4896 md_number_to_chars ((char *) where_to_put_displacement,
4897 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 4898 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 4899 fragP->fr_fix += extension;
4900}
4901\f
47926f60
KH		 4902/* Size of byte displacement jmp. */
4903int md_short_jump_size = 2;
4904
4905/* Size of dword displacement jmp. */
4906int md_long_jump_size = 5;
252b5132 4907
252b5132
RH		 4908void
4909md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4910 char *ptr;
4911 addressT from_addr, to_addr;
ab9da554
ILT		 4912 fragS *frag ATTRIBUTE_UNUSED;
4913 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4914{
847f7ad4 4915 offsetT offset;
252b5132
RH		 4916
4917 offset = to_addr - (from_addr + 2);
47926f60
KH		 4918 /* Opcode for byte-disp jump. */
4919 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 4920 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4921}
4922
4923void
4924md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4925 char *ptr;
4926 addressT from_addr, to_addr;
a38cf1db
AM		 4927 fragS *frag ATTRIBUTE_UNUSED;
4928 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4929{
847f7ad4 4930 offsetT offset;
252b5132 4931
a38cf1db
AM		 4932 offset = to_addr - (from_addr + 5);
4933 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4934 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 4935}
4936\f
4937/* Apply a fixup (fixS) to segment data, once it has been determined
4938 by our caller that we have all the info we need to fix it up.
4939
4940 On the 386, immediates, displacements, and data pointers are all in
4941 the same (little-endian) format, so we don't need to care about which
4942 we are handling. */
4943
94f592af 4944void
55cf6793 4945md_apply_fix (fixP, valP, seg)
47926f60
KH		 4946 /* The fix we're to put in. */
4947 fixS *fixP;
47926f60 4948 /* Pointer to the value of the bits. */
c6682705 4949 valueT *valP;
47926f60
KH		 4950 /* Segment fix is from. */
4951 segT seg ATTRIBUTE_UNUSED;
252b5132 4952{
94f592af 4953 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 4954 valueT value = *valP;
252b5132 4955
f86103b7 4956#if !defined (TE_Mach)
93382f6d
AM		 4957 if (fixP->fx_pcrel)
4958 {
4959 switch (fixP->fx_r_type)
4960 {
5865bb77
ILT		 4961 default:
4962 break;
4963
d6ab8113
JB		 4964 case BFD_RELOC_64:
4965 fixP->fx_r_type = BFD_RELOC_64_PCREL;
4966 break;
93382f6d 4967 case BFD_RELOC_32:
ae8887b5 4968 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 4969 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4970 break;
4971 case BFD_RELOC_16:
4972 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4973 break;
4974 case BFD_RELOC_8:
4975 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4976 break;
4977 }
4978 }
252b5132 4979
a161fe53 4980 if (fixP->fx_addsy != NULL
31312f95 4981 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 4982 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 4983 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4984 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4985 && !use_rela_relocations)
252b5132 4986 {
31312f95
AM		 4987 /* This is a hack. There should be a better way to handle this.
4988 This covers for the fact that bfd_install_relocation will
4989 subtract the current location (for partial_inplace, PC relative
4990 relocations); see more below. */
252b5132 4991#ifndef OBJ_AOUT
718ddfc0 4992 if (IS_ELF
252b5132
RH		 4993#ifdef TE_PE
4994 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4995#endif
4996 )
4997 value += fixP->fx_where + fixP->fx_frag->fr_address;
4998#endif
4999#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5000 if (IS_ELF)
252b5132 5001 {
6539b54b 5002 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 5003
6539b54b 5004 if ((sym_seg == seg
2f66722d 5005 || (symbol_section_p (fixP->fx_addsy)
6539b54b 5006 && sym_seg != absolute_section))
ae6063d4 5007 && !generic_force_reloc (fixP))
2f66722d
AM		 5008 {
5009 /* Yes, we add the values in twice. This is because
6539b54b
AM		 5010 bfd_install_relocation subtracts them out again. I think
5011 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 5012 it. FIXME. */
5013 value += fixP->fx_where + fixP->fx_frag->fr_address;
5014 }
252b5132
RH		 5015 }
5016#endif
5017#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 5018 /* For some reason, the PE format does not store a
5019 section address offset for a PC relative symbol. */
5020 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 5021 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 5022 value += md_pcrel_from (fixP);
5023#endif
5024 }
5025
5026 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 5027 and we must not disappoint it. */
252b5132 5028#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5029 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 5030 switch (fixP->fx_r_type)
5031 {
5032 case BFD_RELOC_386_PLT32:
3e73aa7c 5033 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 5034 /* Make the jump instruction point to the address of the operand. At
5035 runtime we merely add the offset to the actual PLT entry. */
5036 value = -4;
5037 break;
31312f95 5038
13ae64f3
JJ		 5039 case BFD_RELOC_386_TLS_GD:
5040 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5041 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5042 case BFD_RELOC_386_TLS_IE:
5043 case BFD_RELOC_386_TLS_GOTIE:
bffbf940
JJ		 5044 case BFD_RELOC_X86_64_TLSGD:
5045 case BFD_RELOC_X86_64_TLSLD:
5046 case BFD_RELOC_X86_64_GOTTPOFF:
00f7efb6
JJ		 5047 value = 0; /* Fully resolved at runtime. No addend. */
5048 /* Fallthrough */
5049 case BFD_RELOC_386_TLS_LE:
5050 case BFD_RELOC_386_TLS_LDO_32:
5051 case BFD_RELOC_386_TLS_LE_32:
5052 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5053 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5054 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5055 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5056 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5057 break;
5058
5059 case BFD_RELOC_386_GOT32:
5060 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5061 value = 0; /* Fully resolved at runtime. No addend. */
5062 break;
47926f60
KH		 5063
5064 case BFD_RELOC_VTABLE_INHERIT:
5065 case BFD_RELOC_VTABLE_ENTRY:
5066 fixP->fx_done = 0;
94f592af 5067 return;
47926f60
KH		 5068
5069 default:
5070 break;
5071 }
5072#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5073 *valP = value;
f86103b7 5074#endif /* !defined (TE_Mach) */
3e73aa7c 5075
3e73aa7c 5076 /* Are we finished with this relocation now? */
c6682705 5077 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5078 fixP->fx_done = 1;
5079 else if (use_rela_relocations)
5080 {
5081 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5082 /* Remember value for tc_gen_reloc. */
5083 fixP->fx_addnumber = value;
3e73aa7c
JH		 5084 value = 0;
5085 }
f86103b7 5086
94f592af 5087 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5088}
252b5132 5089\f
252b5132
RH		 5090#define MAX_LITTLENUMS 6
5091
47926f60
KH		 5092/* Turn the string pointed to by litP into a floating point constant
5093 of type TYPE, and emit the appropriate bytes. The number of
5094 LITTLENUMS emitted is stored in *SIZEP. An error message is
5095 returned, or NULL on OK. */
5096
252b5132
RH		 5097char *
5098md_atof (type, litP, sizeP)
2ab9b79e 5099 int type;
252b5132
RH		 5100 char *litP;
5101 int *sizeP;
5102{
5103 int prec;
5104 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5105 LITTLENUM_TYPE *wordP;
5106 char *t;
5107
5108 switch (type)
5109 {
5110 case 'f':
5111 case 'F':
5112 prec = 2;
5113 break;
5114
5115 case 'd':
5116 case 'D':
5117 prec = 4;
5118 break;
5119
5120 case 'x':
5121 case 'X':
5122 prec = 5;
5123 break;
5124
5125 default:
5126 *sizeP = 0;
5127 return _("Bad call to md_atof ()");
5128 }
5129 t = atof_ieee (input_line_pointer, type, words);
5130 if (t)
5131 input_line_pointer = t;
5132
5133 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5134 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5135 the bigendian 386. */
5136 for (wordP = words + prec - 1; prec--;)
5137 {
5138 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5139 litP += sizeof (LITTLENUM_TYPE);
5140 }
5141 return 0;
5142}
5143\f
87c245cc 5144static char output_invalid_buf[8];
252b5132 5145
252b5132
RH		 5146static char *
5147output_invalid (c)
5148 int c;
5149{
3882b010 5150 if (ISPRINT (c))
252b5132
RH		 5151 sprintf (output_invalid_buf, "'%c'", c);
5152 else
5153 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
5154 return output_invalid_buf;
5155}
5156
af6bdddf 5157/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5158
5159static const reg_entry *
5160parse_register (reg_string, end_op)
5161 char *reg_string;
5162 char **end_op;
5163{
af6bdddf
AM		 5164 char *s = reg_string;
5165 char *p;
252b5132
RH		 5166 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5167 const reg_entry *r;
5168
5169 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5170 if (*s == REGISTER_PREFIX)
5171 ++s;
5172
5173 if (is_space_char (*s))
5174 ++s;
5175
5176 p = reg_name_given;
af6bdddf 5177 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5178 {
5179 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5180 return (const reg_entry *) NULL;
5181 s++;
252b5132
RH		 5182 }
5183
6588847e
DN		 5184 /* For naked regs, make sure that we are not dealing with an identifier.
5185 This prevents confusing an identifier like `eax_var' with register
5186 `eax'. */
5187 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5188 return (const reg_entry *) NULL;
5189
af6bdddf 5190 *end_op = s;
252b5132
RH		 5191
5192 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5193
5f47d35b 5194 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5195 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5196 {
5f47d35b
AM		 5197 if (is_space_char (*s))
5198 ++s;
5199 if (*s == '(')
5200 {
af6bdddf 5201 ++s;
5f47d35b
AM		 5202 if (is_space_char (*s))
5203 ++s;
5204 if (*s >= '0' && *s <= '7')
5205 {
5206 r = &i386_float_regtab[*s - '0'];
af6bdddf 5207 ++s;
5f47d35b
AM		 5208 if (is_space_char (*s))
5209 ++s;
5210 if (*s == ')')
5211 {
5212 *end_op = s + 1;
5213 return r;
5214 }
5f47d35b 5215 }
47926f60 5216 /* We have "%st(" then garbage. */
5f47d35b
AM		 5217 return (const reg_entry *) NULL;
5218 }
5219 }
5220
1ae00879 5221 if (r != NULL
20f0a1fc 5222 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5223 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5224 && flag_code != CODE_64BIT)
20f0a1fc 5225 return (const reg_entry *) NULL;
1ae00879 5226
252b5132
RH		 5227 return r;
5228}
5229\f
4cc782b5 5230#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5231const char *md_shortopts = "kVQ:sqn";
252b5132 5232#else
12b55ccc 5233const char *md_shortopts = "qn";
252b5132 5234#endif
6e0b89ee 5235
252b5132 5236struct option md_longopts[] = {
3e73aa7c
JH		 5237#define OPTION_32 (OPTION_MD_BASE + 0)
5238 {"32", no_argument, NULL, OPTION_32},
6e0b89ee 5239#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3e73aa7c
JH		 5240#define OPTION_64 (OPTION_MD_BASE + 1)
5241 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5242#endif
252b5132
RH		 5243 {NULL, no_argument, NULL, 0}
5244};
5245size_t md_longopts_size = sizeof (md_longopts);
5246
5247int
5248md_parse_option (c, arg)
5249 int c;
ab9da554 5250 char *arg ATTRIBUTE_UNUSED;
252b5132
RH		 5251{
5252 switch (c)
5253 {
12b55ccc
L		 5254 case 'n':
5255 optimize_align_code = 0;
5256 break;
5257
a38cf1db
AM		 5258 case 'q':
5259 quiet_warnings = 1;
252b5132
RH		 5260 break;
5261
5262#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5263 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5264 should be emitted or not. FIXME: Not implemented. */
5265 case 'Q':
252b5132
RH		 5266 break;
5267
5268 /* -V: SVR4 argument to print version ID. */
5269 case 'V':
5270 print_version_id ();
5271 break;
5272
a38cf1db
AM		 5273 /* -k: Ignore for FreeBSD compatibility. */
5274 case 'k':
252b5132 5275 break;
4cc782b5
ILT		 5276
5277 case 's':
5278 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5279 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5280 break;
6e0b89ee 5281
3e73aa7c
JH		 5282 case OPTION_64:
5283 {
5284 const char **list, **l;
5285
3e73aa7c
JH		 5286 list = bfd_target_list ();
5287 for (l = list; *l != NULL; l++)
6e0b89ee
AM		 5288 if (strcmp (*l, "elf64-x86-64") == 0)
5289 {
5290 default_arch = "x86_64";
5291 break;
5292 }
3e73aa7c 5293 if (*l == NULL)
6e0b89ee 5294 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5295 free (list);
5296 }
5297 break;
5298#endif
252b5132 5299
6e0b89ee
AM		 5300 case OPTION_32:
5301 default_arch = "i386";
5302 break;
5303
252b5132
RH		 5304 default:
5305 return 0;
5306 }
5307 return 1;
5308}
5309
5310void
5311md_show_usage (stream)
5312 FILE *stream;
5313{
4cc782b5
ILT		 5314#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5315 fprintf (stream, _("\
a38cf1db
AM		 5316 -Q ignored\n\
5317 -V print assembler version number\n\
5318 -k ignored\n\
12b55ccc 5319 -n Do not optimize code alignment\n\
a38cf1db
AM		 5320 -q quieten some warnings\n\
5321 -s ignored\n"));
5322#else
5323 fprintf (stream, _("\
12b55ccc 5324 -n Do not optimize code alignment\n\
a38cf1db 5325 -q quieten some warnings\n"));
4cc782b5 5326#endif
252b5132
RH		 5327}
5328
3e73aa7c
JH		 5329#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5330 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 5331
5332/* Pick the target format to use. */
5333
47926f60 5334const char *
252b5132
RH		 5335i386_target_format ()
5336{
3e73aa7c
JH		 5337 if (!strcmp (default_arch, "x86_64"))
5338 set_code_flag (CODE_64BIT);
5339 else if (!strcmp (default_arch, "i386"))
5340 set_code_flag (CODE_32BIT);
5341 else
5342 as_fatal (_("Unknown architecture"));
252b5132
RH		 5343 switch (OUTPUT_FLAVOR)
5344 {
4c63da97
AM		 5345#ifdef OBJ_MAYBE_AOUT
5346 case bfd_target_aout_flavour:
47926f60 5347 return AOUT_TARGET_FORMAT;
4c63da97
AM		 5348#endif
5349#ifdef OBJ_MAYBE_COFF
252b5132
RH		 5350 case bfd_target_coff_flavour:
5351 return "coff-i386";
4c63da97 5352#endif
3e73aa7c 5353#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 5354 case bfd_target_elf_flavour:
3e73aa7c 5355 {
e5cb08ac 5356 if (flag_code == CODE_64BIT)
4fa24527
JB		 5357 {
5358 object_64bit = 1;
5359 use_rela_relocations = 1;
5360 }
4ada7262 5361 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
3e73aa7c 5362 }
4c63da97 5363#endif
252b5132
RH		 5364 default:
5365 abort ();
5366 return NULL;
5367 }
5368}
5369
47926f60 5370#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 5371
5372#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5373void i386_elf_emit_arch_note ()
5374{
718ddfc0 5375 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 5376 {
5377 char *p;
5378 asection *seg = now_seg;
5379 subsegT subseg = now_subseg;
5380 Elf_Internal_Note i_note;
5381 Elf_External_Note e_note;
5382 asection *note_secp;
5383 int len;
5384
5385 /* Create the .note section. */
5386 note_secp = subseg_new (".note", 0);
5387 bfd_set_section_flags (stdoutput,
5388 note_secp,
5389 SEC_HAS_CONTENTS | SEC_READONLY);
5390
5391 /* Process the arch string. */
5392 len = strlen (cpu_arch_name);
5393
5394 i_note.namesz = len + 1;
5395 i_note.descsz = 0;
5396 i_note.type = NT_ARCH;
5397 p = frag_more (sizeof (e_note.namesz));
5398 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
5399 p = frag_more (sizeof (e_note.descsz));
5400 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
5401 p = frag_more (sizeof (e_note.type));
5402 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
5403 p = frag_more (len + 1);
5404 strcpy (p, cpu_arch_name);
5405
5406 frag_align (2, 0, 0);
5407
5408 subseg_set (seg, subseg);
5409 }
5410}
5411#endif
252b5132 5412\f
252b5132
RH		 5413symbolS *
5414md_undefined_symbol (name)
5415 char *name;
5416{
18dc2407
ILT		 5417 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
5418 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
5419 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
5420 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 5421 {
5422 if (!GOT_symbol)
5423 {
5424 if (symbol_find (name))
5425 as_bad (_("GOT already in symbol table"));
5426 GOT_symbol = symbol_new (name, undefined_section,
5427 (valueT) 0, &zero_address_frag);
5428 };
5429 return GOT_symbol;
5430 }
252b5132
RH		 5431 return 0;
5432}
5433
5434/* Round up a section size to the appropriate boundary. */
47926f60 5435
252b5132
RH		 5436valueT
5437md_section_align (segment, size)
ab9da554 5438 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 5439 valueT size;
5440{
4c63da97
AM		 5441#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5442 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
5443 {
5444 /* For a.out, force the section size to be aligned. If we don't do
5445 this, BFD will align it for us, but it will not write out the
5446 final bytes of the section. This may be a bug in BFD, but it is
5447 easier to fix it here since that is how the other a.out targets
5448 work. */
5449 int align;
5450
5451 align = bfd_get_section_alignment (stdoutput, segment);
5452 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
5453 }
252b5132
RH		 5454#endif
5455
5456 return size;
5457}
5458
5459/* On the i386, PC-relative offsets are relative to the start of the
5460 next instruction. That is, the address of the offset, plus its
5461 size, since the offset is always the last part of the insn. */
5462
5463long
5464md_pcrel_from (fixP)
5465 fixS *fixP;
5466{
5467 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5468}
5469
5470#ifndef I386COFF
5471
5472static void
5473s_bss (ignore)
ab9da554 5474 int ignore ATTRIBUTE_UNUSED;
252b5132 5475{
29b0f896 5476 int temp;
252b5132 5477
8a75718c
JB		 5478#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5479 if (IS_ELF)
5480 obj_elf_section_change_hook ();
5481#endif
252b5132
RH		 5482 temp = get_absolute_expression ();
5483 subseg_set (bss_section, (subsegT) temp);
5484 demand_empty_rest_of_line ();
5485}
5486
5487#endif
5488
252b5132
RH		 5489void
5490i386_validate_fix (fixp)
5491 fixS *fixp;
5492{
5493 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5494 {
23df1078
JH		 5495 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5496 {
4fa24527 5497 if (!object_64bit)
23df1078
JH		 5498 abort ();
5499 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5500 }
5501 else
5502 {
4fa24527 5503 if (!object_64bit)
d6ab8113
JB		 5504 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5505 else
5506 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 5507 }
252b5132
RH		 5508 fixp->fx_subsy = 0;
5509 }
5510}
5511
252b5132
RH		 5512arelent *
5513tc_gen_reloc (section, fixp)
ab9da554 5514 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 5515 fixS *fixp;
5516{
5517 arelent *rel;
5518 bfd_reloc_code_real_type code;
5519
5520 switch (fixp->fx_r_type)
5521 {
3e73aa7c
JH		 5522 case BFD_RELOC_X86_64_PLT32:
5523 case BFD_RELOC_X86_64_GOT32:
5524 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 5525 case BFD_RELOC_386_PLT32:
5526 case BFD_RELOC_386_GOT32:
5527 case BFD_RELOC_386_GOTOFF:
5528 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 5529 case BFD_RELOC_386_TLS_GD:
5530 case BFD_RELOC_386_TLS_LDM:
5531 case BFD_RELOC_386_TLS_LDO_32:
5532 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5533 case BFD_RELOC_386_TLS_IE:
5534 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 5535 case BFD_RELOC_386_TLS_LE_32:
5536 case BFD_RELOC_386_TLS_LE:
bffbf940
JJ		 5537 case BFD_RELOC_X86_64_TLSGD:
5538 case BFD_RELOC_X86_64_TLSLD:
5539 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5540 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 5541 case BFD_RELOC_X86_64_GOTTPOFF:
5542 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 5543 case BFD_RELOC_X86_64_TPOFF64:
5544 case BFD_RELOC_X86_64_GOTOFF64:
5545 case BFD_RELOC_X86_64_GOTPC32:
252b5132
RH		 5546 case BFD_RELOC_RVA:
5547 case BFD_RELOC_VTABLE_ENTRY:
5548 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 5549#ifdef TE_PE
5550 case BFD_RELOC_32_SECREL:
5551#endif
252b5132
RH		 5552 code = fixp->fx_r_type;
5553 break;
dbbaec26
L		 5554 case BFD_RELOC_X86_64_32S:
5555 if (!fixp->fx_pcrel)
5556 {
5557 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
5558 code = fixp->fx_r_type;
5559 break;
5560 }
252b5132 5561 default:
93382f6d 5562 if (fixp->fx_pcrel)
252b5132 5563 {
93382f6d
AM		 5564 switch (fixp->fx_size)
5565 {
5566 default:
b091f402
AM		 5567 as_bad_where (fixp->fx_file, fixp->fx_line,
5568 _("can not do %d byte pc-relative relocation"),
5569 fixp->fx_size);
93382f6d
AM		 5570 code = BFD_RELOC_32_PCREL;
5571 break;
5572 case 1: code = BFD_RELOC_8_PCREL; break;
5573 case 2: code = BFD_RELOC_16_PCREL; break;
5574 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 5575#ifdef BFD64
5576 case 8: code = BFD_RELOC_64_PCREL; break;
5577#endif
93382f6d
AM		 5578 }
5579 }
5580 else
5581 {
5582 switch (fixp->fx_size)
5583 {
5584 default:
b091f402
AM		 5585 as_bad_where (fixp->fx_file, fixp->fx_line,
5586 _("can not do %d byte relocation"),
5587 fixp->fx_size);
93382f6d
AM		 5588 code = BFD_RELOC_32;
5589 break;
5590 case 1: code = BFD_RELOC_8; break;
5591 case 2: code = BFD_RELOC_16; break;
5592 case 4: code = BFD_RELOC_32; break;
937149dd 5593#ifdef BFD64
3e73aa7c 5594 case 8: code = BFD_RELOC_64; break;
937149dd 5595#endif
93382f6d 5596 }
252b5132
RH		 5597 }
5598 break;
5599 }
252b5132 5600
d182319b
JB		 5601 if ((code == BFD_RELOC_32
5602 || code == BFD_RELOC_32_PCREL
5603 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 5604 && GOT_symbol
5605 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 5606 {
4fa24527 5607 if (!object_64bit)
d6ab8113
JB		 5608 code = BFD_RELOC_386_GOTPC;
5609 else
5610 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 5611 }
252b5132
RH		 5612
5613 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 5614 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5615 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 5616
5617 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 5618
3e73aa7c
JH		 5619 if (!use_rela_relocations)
5620 {
5621 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5622 vtable entry to be used in the relocation's section offset. */
5623 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5624 rel->address = fixp->fx_offset;
252b5132 5625
c6682705 5626 rel->addend = 0;
3e73aa7c
JH		 5627 }
5628 /* Use the rela in 64bit mode. */
252b5132 5629 else
3e73aa7c 5630 {
062cd5e7
AS		 5631 if (!fixp->fx_pcrel)
5632 rel->addend = fixp->fx_offset;
5633 else
5634 switch (code)
5635 {
5636 case BFD_RELOC_X86_64_PLT32:
5637 case BFD_RELOC_X86_64_GOT32:
5638 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 5639 case BFD_RELOC_X86_64_TLSGD:
5640 case BFD_RELOC_X86_64_TLSLD:
5641 case BFD_RELOC_X86_64_GOTTPOFF:
062cd5e7
AS		 5642 rel->addend = fixp->fx_offset - fixp->fx_size;
5643 break;
5644 default:
5645 rel->addend = (section->vma
5646 - fixp->fx_size
5647 + fixp->fx_addnumber
5648 + md_pcrel_from (fixp));
5649 break;
5650 }
3e73aa7c
JH		 5651 }
5652
252b5132
RH		 5653 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5654 if (rel->howto == NULL)
5655 {
5656 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 5657 _("cannot represent relocation type %s"),
252b5132
RH		 5658 bfd_get_reloc_code_name (code));
5659 /* Set howto to a garbage value so that we can keep going. */
5660 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5661 assert (rel->howto != NULL);
5662 }
5663
5664 return rel;
5665}
5666
64a0c779
DN		 5667\f
5668/* Parse operands using Intel syntax. This implements a recursive descent
5669 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5670 Programmer's Guide.
5671
5672 FIXME: We do not recognize the full operand grammar defined in the MASM
5673 documentation. In particular, all the structure/union and
5674 high-level macro operands are missing.
5675
5676 Uppercase words are terminals, lower case words are non-terminals.
5677 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5678 bars '|' denote choices. Most grammar productions are implemented in
5679 functions called 'intel_<production>'.
5680
5681 Initial production is 'expr'.
5682
9306ca4a 5683 addOp + | -
64a0c779
DN		 5684
5685 alpha [a-zA-Z]
5686
9306ca4a
JB		 5687 binOp & | AND | \| | OR | ^ | XOR
5688
64a0c779
DN		 5689 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5690
5691 constant digits [[ radixOverride ]]
5692
9306ca4a 5693 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 5694
5695 digits decdigit
b77a7acd
AJ		 5696 | digits decdigit
5697 | digits hexdigit
64a0c779
DN		 5698
5699 decdigit [0-9]
5700
9306ca4a
JB		 5701 e04 e04 addOp e05
5702 | e05
5703
5704 e05 e05 binOp e06
b77a7acd 5705 | e06
64a0c779
DN		 5706
5707 e06 e06 mulOp e09
b77a7acd 5708 | e09
64a0c779
DN		 5709
5710 e09 OFFSET e10
a724f0f4
JB		 5711 | SHORT e10
5712 | + e10
5713 | - e10
9306ca4a
JB		 5714 | ~ e10
5715 | NOT e10
64a0c779
DN		 5716 | e09 PTR e10
5717 | e09 : e10
5718 | e10
5719
5720 e10 e10 [ expr ]
b77a7acd 5721 | e11
64a0c779
DN		 5722
5723 e11 ( expr )
b77a7acd 5724 | [ expr ]
64a0c779
DN		 5725 | constant
5726 | dataType
5727 | id
5728 | $
5729 | register
5730
a724f0f4 5731 => expr expr cmpOp e04
9306ca4a 5732 | e04
64a0c779
DN		 5733
5734 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 5735 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 5736
5737 hexdigit a | b | c | d | e | f
b77a7acd 5738 | A | B | C | D | E | F
64a0c779
DN		 5739
5740 id alpha
b77a7acd 5741 | id alpha
64a0c779
DN		 5742 | id decdigit
5743
9306ca4a 5744 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 5745
5746 quote " | '
5747
5748 register specialRegister
b77a7acd 5749 | gpRegister
64a0c779
DN		 5750 | byteRegister
5751
5752 segmentRegister CS | DS | ES | FS | GS | SS
5753
9306ca4a 5754 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 5755 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 5756 | TR3 | TR4 | TR5 | TR6 | TR7
5757
64a0c779
DN		 5758 We simplify the grammar in obvious places (e.g., register parsing is
5759 done by calling parse_register) and eliminate immediate left recursion
5760 to implement a recursive-descent parser.
5761
a724f0f4
JB		 5762 expr e04 expr'
5763
5764 expr' cmpOp e04 expr'
5765 | Empty
9306ca4a
JB		 5766
5767 e04 e05 e04'
5768
5769 e04' addOp e05 e04'
5770 | Empty
64a0c779
DN		 5771
5772 e05 e06 e05'
5773
9306ca4a 5774 e05' binOp e06 e05'
b77a7acd 5775 | Empty
64a0c779
DN		 5776
5777 e06 e09 e06'
5778
5779 e06' mulOp e09 e06'
b77a7acd 5780 | Empty
64a0c779
DN		 5781
5782 e09 OFFSET e10 e09'
a724f0f4
JB		 5783 | SHORT e10'
5784 | + e10'
5785 | - e10'
5786 | ~ e10'
5787 | NOT e10'
b77a7acd 5788 | e10 e09'
64a0c779
DN		 5789
5790 e09' PTR e10 e09'
b77a7acd 5791 | : e10 e09'
64a0c779
DN		 5792 | Empty
5793
5794 e10 e11 e10'
5795
5796 e10' [ expr ] e10'
b77a7acd 5797 | Empty
64a0c779
DN		 5798
5799 e11 ( expr )
b77a7acd 5800 | [ expr ]
64a0c779
DN		 5801 | BYTE
5802 | WORD
5803 | DWORD
9306ca4a 5804 | FWORD
64a0c779 5805 | QWORD
9306ca4a
JB		 5806 | TBYTE
5807 | OWORD
5808 | XMMWORD
64a0c779
DN		 5809 | .
5810 | $
5811 | register
5812 | id
5813 | constant */
5814
5815/* Parsing structure for the intel syntax parser. Used to implement the
5816 semantic actions for the operand grammar. */
5817struct intel_parser_s
5818 {
5819 char *op_string; /* The string being parsed. */
5820 int got_a_float; /* Whether the operand is a float. */
4a1805b1 5821 int op_modifier; /* Operand modifier. */
64a0c779 5822 int is_mem; /* 1 if operand is memory reference. */
a724f0f4
JB		 5823 int in_offset; /* >=1 if parsing operand of offset. */
5824 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 5825 const reg_entry *reg; /* Last register reference found. */
5826 char *disp; /* Displacement string being built. */
a724f0f4 5827 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 5828 };
5829
5830static struct intel_parser_s intel_parser;
5831
5832/* Token structure for parsing intel syntax. */
5833struct intel_token
5834 {
5835 int code; /* Token code. */
5836 const reg_entry *reg; /* Register entry for register tokens. */
5837 char *str; /* String representation. */
5838 };
5839
5840static struct intel_token cur_token, prev_token;
5841
50705ef4
AM		 5842/* Token codes for the intel parser. Since T_SHORT is already used
5843 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 5844#define T_NIL -1
5845#define T_CONST 1
5846#define T_REG 2
5847#define T_BYTE 3
5848#define T_WORD 4
9306ca4a
JB		 5849#define T_DWORD 5
5850#define T_FWORD 6
5851#define T_QWORD 7
5852#define T_TBYTE 8
5853#define T_XMMWORD 9
50705ef4 5854#undef T_SHORT
9306ca4a
JB		 5855#define T_SHORT 10
5856#define T_OFFSET 11
5857#define T_PTR 12
5858#define T_ID 13
5859#define T_SHL 14
5860#define T_SHR 15
64a0c779
DN		 5861
5862/* Prototypes for intel parser functions. */
5863static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 5864static void intel_get_token PARAMS ((void));
5865static void intel_putback_token PARAMS ((void));
5866static int intel_expr PARAMS ((void));
9306ca4a 5867static int intel_e04 PARAMS ((void));
cce0cbdc 5868static int intel_e05 PARAMS ((void));
cce0cbdc 5869static int intel_e06 PARAMS ((void));
cce0cbdc 5870static int intel_e09 PARAMS ((void));
a724f0f4 5871static int intel_bracket_expr PARAMS ((void));
cce0cbdc 5872static int intel_e10 PARAMS ((void));
cce0cbdc 5873static int intel_e11 PARAMS ((void));
64a0c779 5874
64a0c779
DN		 5875static int
5876i386_intel_operand (operand_string, got_a_float)
5877 char *operand_string;
5878 int got_a_float;
5879{
5880 int ret;
5881 char *p;
5882
a724f0f4
JB		 5883 p = intel_parser.op_string = xstrdup (operand_string);
5884 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
5885
5886 for (;;)
64a0c779 5887 {
a724f0f4
JB		 5888 /* Initialize token holders. */
5889 cur_token.code = prev_token.code = T_NIL;
5890 cur_token.reg = prev_token.reg = NULL;
5891 cur_token.str = prev_token.str = NULL;
5892
5893 /* Initialize parser structure. */
5894 intel_parser.got_a_float = got_a_float;
5895 intel_parser.op_modifier = 0;
5896 intel_parser.is_mem = 0;
5897 intel_parser.in_offset = 0;
5898 intel_parser.in_bracket = 0;
5899 intel_parser.reg = NULL;
5900 intel_parser.disp[0] = '\0';
5901 intel_parser.next_operand = NULL;
5902
5903 /* Read the first token and start the parser. */
5904 intel_get_token ();
5905 ret = intel_expr ();
5906
5907 if (!ret)
5908 break;
5909
9306ca4a
JB		 5910 if (cur_token.code != T_NIL)
5911 {
5912 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
5913 current_templates->start->name, cur_token.str);
5914 ret = 0;
5915 }
64a0c779
DN		 5916 /* If we found a memory reference, hand it over to i386_displacement
5917 to fill in the rest of the operand fields. */
9306ca4a 5918 else if (intel_parser.is_mem)
64a0c779
DN		 5919 {
5920 if ((i.mem_operands == 1
5921 && (current_templates->start->opcode_modifier & IsString) == 0)
5922 || i.mem_operands == 2)
5923 {
5924 as_bad (_("too many memory references for '%s'"),
5925 current_templates->start->name);
5926 ret = 0;
5927 }
5928 else
5929 {
5930 char *s = intel_parser.disp;
5931 i.mem_operands++;
5932
a724f0f4
JB		 5933 if (!quiet_warnings && intel_parser.is_mem < 0)
5934 /* See the comments in intel_bracket_expr. */
5935 as_warn (_("Treating `%s' as memory reference"), operand_string);
5936
64a0c779
DN		 5937 /* Add the displacement expression. */
5938 if (*s != '\0')
a4622f40
AM		 5939 ret = i386_displacement (s, s + strlen (s));
5940 if (ret)
a724f0f4
JB		 5941 {
5942 /* Swap base and index in 16-bit memory operands like
5943 [si+bx]. Since i386_index_check is also used in AT&T
5944 mode we have to do that here. */
5945 if (i.base_reg
5946 && i.index_reg
5947 && (i.base_reg->reg_type & Reg16)
5948 && (i.index_reg->reg_type & Reg16)
5949 && i.base_reg->reg_num >= 6
5950 && i.index_reg->reg_num < 6)
5951 {
5952 const reg_entry *base = i.index_reg;
5953
5954 i.index_reg = i.base_reg;
5955 i.base_reg = base;
5956 }
5957 ret = i386_index_check (operand_string);
5958 }
64a0c779
DN		 5959 }
5960 }
5961
5962 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 5963 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 5964 || intel_parser.reg == NULL)
5965 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 5966
5967 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
5968 ret = 0;
5969 if (!ret || !intel_parser.next_operand)
5970 break;
5971 intel_parser.op_string = intel_parser.next_operand;
5972 this_operand = i.operands++;
64a0c779
DN		 5973 }
5974
5975 free (p);
5976 free (intel_parser.disp);
5977
5978 return ret;
5979}
5980
a724f0f4
JB		 5981#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
5982
5983/* expr e04 expr'
5984
5985 expr' cmpOp e04 expr'
5986 | Empty */
64a0c779
DN		 5987static int
5988intel_expr ()
5989{
a724f0f4
JB		 5990 /* XXX Implement the comparison operators. */
5991 return intel_e04 ();
9306ca4a
JB		 5992}
5993
a724f0f4 5994/* e04 e05 e04'
9306ca4a 5995
a724f0f4 5996 e04' addOp e05 e04'
9306ca4a
JB		 5997 | Empty */
5998static int
5999intel_e04 ()
6000{
a724f0f4 6001 int nregs = -1;
9306ca4a 6002
a724f0f4 6003 for (;;)
9306ca4a 6004 {
a724f0f4
JB		 6005 if (!intel_e05())
6006 return 0;
9306ca4a 6007
a724f0f4
JB		 6008 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6009 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 6010
a724f0f4
JB		 6011 if (cur_token.code == '+')
6012 nregs = -1;
6013 else if (cur_token.code == '-')
6014 nregs = NUM_ADDRESS_REGS;
6015 else
6016 return 1;
64a0c779 6017
a724f0f4
JB		 6018 strcat (intel_parser.disp, cur_token.str);
6019 intel_match_token (cur_token.code);
6020 }
64a0c779
DN		 6021}
6022
64a0c779
DN		 6023/* e05 e06 e05'
6024
9306ca4a 6025 e05' binOp e06 e05'
64a0c779
DN		 6026 | Empty */
6027static int
6028intel_e05 ()
6029{
a724f0f4 6030 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6031
a724f0f4 6032 for (;;)
64a0c779 6033 {
a724f0f4
JB		 6034 if (!intel_e06())
6035 return 0;
6036
6037 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6038 {
6039 char str[2];
6040
6041 str[0] = cur_token.code;
6042 str[1] = 0;
6043 strcat (intel_parser.disp, str);
6044 }
6045 else
6046 break;
9306ca4a 6047
64a0c779
DN		 6048 intel_match_token (cur_token.code);
6049
a724f0f4
JB		 6050 if (nregs < 0)
6051 nregs = ~nregs;
64a0c779 6052 }
a724f0f4
JB		 6053 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6054 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6055 return 1;
4a1805b1 6056}
64a0c779
DN		 6057
6058/* e06 e09 e06'
6059
6060 e06' mulOp e09 e06'
b77a7acd 6061 | Empty */
64a0c779
DN		 6062static int
6063intel_e06 ()
6064{
a724f0f4 6065 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6066
a724f0f4 6067 for (;;)
64a0c779 6068 {
a724f0f4
JB		 6069 if (!intel_e09())
6070 return 0;
9306ca4a 6071
a724f0f4
JB		 6072 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6073 {
6074 char str[2];
9306ca4a 6075
a724f0f4
JB		 6076 str[0] = cur_token.code;
6077 str[1] = 0;
6078 strcat (intel_parser.disp, str);
6079 }
6080 else if (cur_token.code == T_SHL)
6081 strcat (intel_parser.disp, "<<");
6082 else if (cur_token.code == T_SHR)
6083 strcat (intel_parser.disp, ">>");
6084 else
6085 break;
9306ca4a 6086
a724f0f4 6087 intel_match_token (cur_token.code);
64a0c779 6088
a724f0f4
JB		 6089 if (nregs < 0)
6090 nregs = ~nregs;
64a0c779 6091 }
a724f0f4
JB		 6092 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6093 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6094 return 1;
64a0c779
DN		 6095}
6096
a724f0f4
JB		 6097/* e09 OFFSET e09
6098 | SHORT e09
6099 | + e09
6100 | - e09
6101 | ~ e09
6102 | NOT e09
9306ca4a
JB		 6103 | e10 e09'
6104
64a0c779 6105 e09' PTR e10 e09'
b77a7acd 6106 | : e10 e09'
64a0c779
DN		 6107 | Empty */
6108static int
6109intel_e09 ()
6110{
a724f0f4
JB		 6111 int nregs = ~NUM_ADDRESS_REGS;
6112 int in_offset = 0;
6113
6114 for (;;)
64a0c779 6115 {
a724f0f4
JB		 6116 /* Don't consume constants here. */
6117 if (cur_token.code == '+' || cur_token.code == '-')
6118 {
6119 /* Need to look one token ahead - if the next token
6120 is a constant, the current token is its sign. */
6121 int next_code;
6122
6123 intel_match_token (cur_token.code);
6124 next_code = cur_token.code;
6125 intel_putback_token ();
6126 if (next_code == T_CONST)
6127 break;
6128 }
6129
6130 /* e09 OFFSET e09 */
6131 if (cur_token.code == T_OFFSET)
6132 {
6133 if (!in_offset++)
6134 ++intel_parser.in_offset;
6135 }
6136
6137 /* e09 SHORT e09 */
6138 else if (cur_token.code == T_SHORT)
6139 intel_parser.op_modifier |= 1 << T_SHORT;
6140
6141 /* e09 + e09 */
6142 else if (cur_token.code == '+')
6143 strcat (intel_parser.disp, "+");
6144
6145 /* e09 - e09
6146 | ~ e09
6147 | NOT e09 */
6148 else if (cur_token.code == '-' || cur_token.code == '~')
6149 {
6150 char str[2];
64a0c779 6151
a724f0f4
JB		 6152 if (nregs < 0)
6153 nregs = ~nregs;
6154 str[0] = cur_token.code;
6155 str[1] = 0;
6156 strcat (intel_parser.disp, str);
6157 }
6158
6159 /* e09 e10 e09' */
6160 else
6161 break;
6162
6163 intel_match_token (cur_token.code);
64a0c779
DN		 6164 }
6165
a724f0f4 6166 for (;;)
9306ca4a 6167 {
a724f0f4
JB		 6168 if (!intel_e10 ())
6169 return 0;
9306ca4a 6170
a724f0f4
JB		 6171 /* e09' PTR e10 e09' */
6172 if (cur_token.code == T_PTR)
6173 {
6174 char suffix;
9306ca4a 6175
a724f0f4
JB		 6176 if (prev_token.code == T_BYTE)
6177 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 6178
a724f0f4
JB		 6179 else if (prev_token.code == T_WORD)
6180 {
6181 if (current_templates->start->name[0] == 'l'
6182 && current_templates->start->name[2] == 's'
6183 && current_templates->start->name[3] == 0)
6184 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6185 else if (intel_parser.got_a_float == 2) /* "fi..." */
6186 suffix = SHORT_MNEM_SUFFIX;
6187 else
6188 suffix = WORD_MNEM_SUFFIX;
6189 }
64a0c779 6190
a724f0f4
JB		 6191 else if (prev_token.code == T_DWORD)
6192 {
6193 if (current_templates->start->name[0] == 'l'
6194 && current_templates->start->name[2] == 's'
6195 && current_templates->start->name[3] == 0)
6196 suffix = WORD_MNEM_SUFFIX;
6197 else if (flag_code == CODE_16BIT
6198 && (current_templates->start->opcode_modifier
435acd52 6199 & (Jump | JumpDword)))
a724f0f4
JB		 6200 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6201 else if (intel_parser.got_a_float == 1) /* "f..." */
6202 suffix = SHORT_MNEM_SUFFIX;
6203 else
6204 suffix = LONG_MNEM_SUFFIX;
6205 }
9306ca4a 6206
a724f0f4
JB		 6207 else if (prev_token.code == T_FWORD)
6208 {
6209 if (current_templates->start->name[0] == 'l'
6210 && current_templates->start->name[2] == 's'
6211 && current_templates->start->name[3] == 0)
6212 suffix = LONG_MNEM_SUFFIX;
6213 else if (!intel_parser.got_a_float)
6214 {
6215 if (flag_code == CODE_16BIT)
6216 add_prefix (DATA_PREFIX_OPCODE);
6217 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6218 }
6219 else
6220 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6221 }
64a0c779 6222
a724f0f4
JB		 6223 else if (prev_token.code == T_QWORD)
6224 {
6225 if (intel_parser.got_a_float == 1) /* "f..." */
6226 suffix = LONG_MNEM_SUFFIX;
6227 else
6228 suffix = QWORD_MNEM_SUFFIX;
6229 }
64a0c779 6230
a724f0f4
JB		 6231 else if (prev_token.code == T_TBYTE)
6232 {
6233 if (intel_parser.got_a_float == 1)
6234 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6235 else
6236 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6237 }
9306ca4a 6238
a724f0f4 6239 else if (prev_token.code == T_XMMWORD)
9306ca4a 6240 {
a724f0f4
JB		 6241 /* XXX ignored for now, but accepted since gcc uses it */
6242 suffix = 0;
9306ca4a 6243 }
64a0c779 6244
f16b83df 6245 else
a724f0f4
JB		 6246 {
6247 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6248 return 0;
6249 }
6250
435acd52
JB		 6251 /* Operands for jump/call using 'ptr' notation denote absolute
6252 addresses. */
6253 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6254 i.types[this_operand] |= JumpAbsolute;
6255
a724f0f4
JB		 6256 if (current_templates->start->base_opcode == 0x8d /* lea */)
6257 ;
6258 else if (!i.suffix)
6259 i.suffix = suffix;
6260 else if (i.suffix != suffix)
6261 {
6262 as_bad (_("Conflicting operand modifiers"));
6263 return 0;
6264 }
64a0c779 6265
9306ca4a
JB		 6266 }
6267
a724f0f4
JB		 6268 /* e09' : e10 e09' */
6269 else if (cur_token.code == ':')
9306ca4a 6270 {
a724f0f4
JB		 6271 if (prev_token.code != T_REG)
6272 {
6273 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6274 segment/group identifier (which we don't have), using comma
6275 as the operand separator there is even less consistent, since
6276 there all branches only have a single operand. */
6277 if (this_operand != 0
6278 || intel_parser.in_offset
6279 || intel_parser.in_bracket
6280 || (!(current_templates->start->opcode_modifier
6281 & (Jump|JumpDword|JumpInterSegment))
6282 && !(current_templates->start->operand_types[0]
6283 & JumpAbsolute)))
6284 return intel_match_token (T_NIL);
6285 /* Remember the start of the 2nd operand and terminate 1st
6286 operand here.
6287 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6288 another expression), but it gets at least the simplest case
6289 (a plain number or symbol on the left side) right. */
6290 intel_parser.next_operand = intel_parser.op_string;
6291 *--intel_parser.op_string = '\0';
6292 return intel_match_token (':');
6293 }
9306ca4a 6294 }
64a0c779 6295
a724f0f4 6296 /* e09' Empty */
64a0c779 6297 else
a724f0f4 6298 break;
64a0c779 6299
a724f0f4
JB		 6300 intel_match_token (cur_token.code);
6301
6302 }
6303
6304 if (in_offset)
6305 {
6306 --intel_parser.in_offset;
6307 if (nregs < 0)
6308 nregs = ~nregs;
6309 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 6310 {
a724f0f4 6311 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 6312 return 0;
6313 }
a724f0f4
JB		 6314 intel_parser.op_modifier |= 1 << T_OFFSET;
6315 }
9306ca4a 6316
a724f0f4
JB		 6317 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6318 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
6319 return 1;
6320}
64a0c779 6321
a724f0f4
JB		 6322static int
6323intel_bracket_expr ()
6324{
6325 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
6326 const char *start = intel_parser.op_string;
6327 int len;
6328
6329 if (i.op[this_operand].regs)
6330 return intel_match_token (T_NIL);
6331
6332 intel_match_token ('[');
6333
6334 /* Mark as a memory operand only if it's not already known to be an
6335 offset expression. If it's an offset expression, we need to keep
6336 the brace in. */
6337 if (!intel_parser.in_offset)
6338 {
6339 ++intel_parser.in_bracket;
435acd52
JB		 6340
6341 /* Operands for jump/call inside brackets denote absolute addresses. */
6342 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6343 i.types[this_operand] |= JumpAbsolute;
6344
a724f0f4
JB		 6345 /* Unfortunately gas always diverged from MASM in a respect that can't
6346 be easily fixed without risking to break code sequences likely to be
6347 encountered (the testsuite even check for this): MASM doesn't consider
6348 an expression inside brackets unconditionally as a memory reference.
6349 When that is e.g. a constant, an offset expression, or the sum of the
6350 two, this is still taken as a constant load. gas, however, always
6351 treated these as memory references. As a compromise, we'll try to make
6352 offset expressions inside brackets work the MASM way (since that's
6353 less likely to be found in real world code), but make constants alone
6354 continue to work the traditional gas way. In either case, issue a
6355 warning. */
6356 intel_parser.op_modifier &= ~was_offset;
64a0c779 6357 }
a724f0f4
JB		 6358 else
6359 strcat (intel_parser.disp, "[");
6360
6361 /* Add a '+' to the displacement string if necessary. */
6362 if (*intel_parser.disp != '\0'
6363 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
6364 strcat (intel_parser.disp, "+");
64a0c779 6365
a724f0f4
JB		 6366 if (intel_expr ()
6367 && (len = intel_parser.op_string - start - 1,
6368 intel_match_token (']')))
64a0c779 6369 {
a724f0f4
JB		 6370 /* Preserve brackets when the operand is an offset expression. */
6371 if (intel_parser.in_offset)
6372 strcat (intel_parser.disp, "]");
6373 else
6374 {
6375 --intel_parser.in_bracket;
6376 if (i.base_reg || i.index_reg)
6377 intel_parser.is_mem = 1;
6378 if (!intel_parser.is_mem)
6379 {
6380 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
6381 /* Defer the warning until all of the operand was parsed. */
6382 intel_parser.is_mem = -1;
6383 else if (!quiet_warnings)
6384 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
6385 }
6386 }
6387 intel_parser.op_modifier |= was_offset;
64a0c779 6388
a724f0f4 6389 return 1;
64a0c779 6390 }
a724f0f4 6391 return 0;
64a0c779
DN		 6392}
6393
6394/* e10 e11 e10'
6395
6396 e10' [ expr ] e10'
b77a7acd 6397 | Empty */
64a0c779
DN		 6398static int
6399intel_e10 ()
6400{
a724f0f4
JB		 6401 if (!intel_e11 ())
6402 return 0;
64a0c779 6403
a724f0f4 6404 while (cur_token.code == '[')
64a0c779 6405 {
a724f0f4 6406 if (!intel_bracket_expr ())
21d6c4af 6407 return 0;
64a0c779
DN		 6408 }
6409
a724f0f4 6410 return 1;
64a0c779
DN		 6411}
6412
64a0c779 6413/* e11 ( expr )
b77a7acd 6414 | [ expr ]
64a0c779
DN		 6415 | BYTE
6416 | WORD
6417 | DWORD
9306ca4a 6418 | FWORD
64a0c779 6419 | QWORD
9306ca4a
JB		 6420 | TBYTE
6421 | OWORD
6422 | XMMWORD
4a1805b1 6423 | $
64a0c779
DN		 6424 | .
6425 | register
6426 | id
6427 | constant */
6428static int
6429intel_e11 ()
6430{
a724f0f4 6431 switch (cur_token.code)
64a0c779 6432 {
a724f0f4
JB		 6433 /* e11 ( expr ) */
6434 case '(':
64a0c779
DN		 6435 intel_match_token ('(');
6436 strcat (intel_parser.disp, "(");
6437
6438 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 6439 {
6440 strcat (intel_parser.disp, ")");
6441 return 1;
6442 }
a724f0f4 6443 return 0;
4a1805b1 6444
a724f0f4
JB		 6445 /* e11 [ expr ] */
6446 case '[':
a724f0f4 6447 return intel_bracket_expr ();
64a0c779 6448
a724f0f4
JB		 6449 /* e11 $
6450 | . */
6451 case '.':
64a0c779
DN		 6452 strcat (intel_parser.disp, cur_token.str);
6453 intel_match_token (cur_token.code);
21d6c4af
DN		 6454
6455 /* Mark as a memory operand only if it's not already known to be an
6456 offset expression. */
a724f0f4 6457 if (!intel_parser.in_offset)
21d6c4af 6458 intel_parser.is_mem = 1;
64a0c779
DN		 6459
6460 return 1;
64a0c779 6461
a724f0f4
JB		 6462 /* e11 register */
6463 case T_REG:
6464 {
6465 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 6466
a724f0f4 6467 intel_match_token (T_REG);
64a0c779 6468
a724f0f4
JB		 6469 /* Check for segment change. */
6470 if (cur_token.code == ':')
6471 {
6472 if (!(reg->reg_type & (SReg2 | SReg3)))
6473 {
6474 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
6475 return 0;
6476 }
6477 else if (i.seg[i.mem_operands])
6478 as_warn (_("Extra segment override ignored"));
6479 else
6480 {
6481 if (!intel_parser.in_offset)
6482 intel_parser.is_mem = 1;
6483 switch (reg->reg_num)
6484 {
6485 case 0:
6486 i.seg[i.mem_operands] = &es;
6487 break;
6488 case 1:
6489 i.seg[i.mem_operands] = &cs;
6490 break;
6491 case 2:
6492 i.seg[i.mem_operands] = &ss;
6493 break;
6494 case 3:
6495 i.seg[i.mem_operands] = &ds;
6496 break;
6497 case 4:
6498 i.seg[i.mem_operands] = &fs;
6499 break;
6500 case 5:
6501 i.seg[i.mem_operands] = &gs;
6502 break;
6503 }
6504 }
6505 }
64a0c779 6506
a724f0f4
JB		 6507 /* Not a segment register. Check for register scaling. */
6508 else if (cur_token.code == '*')
6509 {
6510 if (!intel_parser.in_bracket)
6511 {
6512 as_bad (_("Register scaling only allowed in memory operands"));
6513 return 0;
6514 }
64a0c779 6515
a724f0f4
JB		 6516 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
6517 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6518 else if (i.index_reg)
6519 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 6520
a724f0f4
JB		 6521 /* What follows must be a valid scale. */
6522 intel_match_token ('*');
6523 i.index_reg = reg;
6524 i.types[this_operand] |= BaseIndex;
64a0c779 6525
a724f0f4
JB		 6526 /* Set the scale after setting the register (otherwise,
6527 i386_scale will complain) */
6528 if (cur_token.code == '+' || cur_token.code == '-')
6529 {
6530 char *str, sign = cur_token.code;
6531 intel_match_token (cur_token.code);
6532 if (cur_token.code != T_CONST)
6533 {
6534 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6535 cur_token.str);
6536 return 0;
6537 }
6538 str = (char *) xmalloc (strlen (cur_token.str) + 2);
6539 strcpy (str + 1, cur_token.str);
6540 *str = sign;
6541 if (!i386_scale (str))
6542 return 0;
6543 free (str);
6544 }
6545 else if (!i386_scale (cur_token.str))
64a0c779 6546 return 0;
a724f0f4
JB		 6547 intel_match_token (cur_token.code);
6548 }
64a0c779 6549
a724f0f4
JB		 6550 /* No scaling. If this is a memory operand, the register is either a
6551 base register (first occurrence) or an index register (second
6552 occurrence). */
6553 else if (intel_parser.in_bracket && !(reg->reg_type & (SReg2 | SReg3)))
6554 {
64a0c779 6555
a724f0f4
JB		 6556 if (!i.base_reg)
6557 i.base_reg = reg;
6558 else if (!i.index_reg)
6559 i.index_reg = reg;
6560 else
6561 {
6562 as_bad (_("Too many register references in memory operand"));
6563 return 0;
6564 }
64a0c779 6565
a724f0f4
JB		 6566 i.types[this_operand] |= BaseIndex;
6567 }
4a1805b1 6568
a724f0f4
JB		 6569 /* Offset modifier. Add the register to the displacement string to be
6570 parsed as an immediate expression after we're done. */
6571 else if (intel_parser.in_offset)
6572 {
6573 as_warn (_("Using register names in OFFSET expressions is deprecated"));
6574 strcat (intel_parser.disp, reg->reg_name);
6575 }
64a0c779 6576
a724f0f4
JB		 6577 /* It's neither base nor index nor offset. */
6578 else if (!intel_parser.is_mem)
6579 {
6580 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
6581 i.op[this_operand].regs = reg;
6582 i.reg_operands++;
6583 }
6584 else
6585 {
6586 as_bad (_("Invalid use of register"));
6587 return 0;
6588 }
64a0c779 6589
a724f0f4
JB		 6590 /* Since registers are not part of the displacement string (except
6591 when we're parsing offset operands), we may need to remove any
6592 preceding '+' from the displacement string. */
6593 if (*intel_parser.disp != '\0'
6594 && !intel_parser.in_offset)
6595 {
6596 char *s = intel_parser.disp;
6597 s += strlen (s) - 1;
6598 if (*s == '+')
6599 *s = '\0';
6600 }
4a1805b1 6601
a724f0f4
JB		 6602 return 1;
6603 }
6604
6605 /* e11 BYTE
6606 | WORD
6607 | DWORD
6608 | FWORD
6609 | QWORD
6610 | TBYTE
6611 | OWORD
6612 | XMMWORD */
6613 case T_BYTE:
6614 case T_WORD:
6615 case T_DWORD:
6616 case T_FWORD:
6617 case T_QWORD:
6618 case T_TBYTE:
6619 case T_XMMWORD:
6620 intel_match_token (cur_token.code);
64a0c779 6621
a724f0f4
JB		 6622 if (cur_token.code == T_PTR)
6623 return 1;
6624
6625 /* It must have been an identifier. */
6626 intel_putback_token ();
6627 cur_token.code = T_ID;
6628 /* FALLTHRU */
6629
6630 /* e11 id
6631 | constant */
6632 case T_ID:
6633 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 6634 {
6635 symbolS *symbolP;
6636
a724f0f4
JB		 6637 /* The identifier represents a memory reference only if it's not
6638 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 6639 symbolP = symbol_find(cur_token.str);
6640 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
6641 intel_parser.is_mem = 1;
6642 }
a724f0f4 6643 /* FALLTHRU */
64a0c779 6644
a724f0f4
JB		 6645 case T_CONST:
6646 case '-':
6647 case '+':
6648 {
6649 char *save_str, sign = 0;
64a0c779 6650
a724f0f4
JB		 6651 /* Allow constants that start with `+' or `-'. */
6652 if (cur_token.code == '-' || cur_token.code == '+')
6653 {
6654 sign = cur_token.code;
6655 intel_match_token (cur_token.code);
6656 if (cur_token.code != T_CONST)
6657 {
6658 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6659 cur_token.str);
6660 return 0;
6661 }
6662 }
64a0c779 6663
a724f0f4
JB		 6664 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
6665 strcpy (save_str + !!sign, cur_token.str);
6666 if (sign)
6667 *save_str = sign;
64a0c779 6668
a724f0f4
JB		 6669 /* Get the next token to check for register scaling. */
6670 intel_match_token (cur_token.code);
64a0c779 6671
a724f0f4
JB		 6672 /* Check if this constant is a scaling factor for an index register. */
6673 if (cur_token.code == '*')
6674 {
6675 if (intel_match_token ('*') && cur_token.code == T_REG)
6676 {
6677 const reg_entry *reg = cur_token.reg;
6678
6679 if (!intel_parser.in_bracket)
6680 {
6681 as_bad (_("Register scaling only allowed in memory operands"));
6682 return 0;
6683 }
6684
6685 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
6686 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6687 else if (i.index_reg)
6688 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
6689
6690 /* The constant is followed by `* reg', so it must be
6691 a valid scale. */
6692 i.index_reg = reg;
6693 i.types[this_operand] |= BaseIndex;
6694
6695 /* Set the scale after setting the register (otherwise,
6696 i386_scale will complain) */
6697 if (!i386_scale (save_str))
64a0c779 6698 return 0;
a724f0f4
JB		 6699 intel_match_token (T_REG);
6700
6701 /* Since registers are not part of the displacement
6702 string, we may need to remove any preceding '+' from
6703 the displacement string. */
6704 if (*intel_parser.disp != '\0')
6705 {
6706 char *s = intel_parser.disp;
6707 s += strlen (s) - 1;
6708 if (*s == '+')
6709 *s = '\0';
6710 }
6711
6712 free (save_str);
6713
6714 return 1;
6715 }
64a0c779 6716
a724f0f4
JB		 6717 /* The constant was not used for register scaling. Since we have
6718 already consumed the token following `*' we now need to put it
6719 back in the stream. */
64a0c779 6720 intel_putback_token ();
a724f0f4 6721 }
64a0c779 6722
a724f0f4
JB		 6723 /* Add the constant to the displacement string. */
6724 strcat (intel_parser.disp, save_str);
6725 free (save_str);
64a0c779 6726
a724f0f4
JB		 6727 return 1;
6728 }
64a0c779
DN		 6729 }
6730
64a0c779
DN		 6731 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6732 return 0;
6733}
6734
64a0c779
DN		 6735/* Match the given token against cur_token. If they match, read the next
6736 token from the operand string. */
6737static int
6738intel_match_token (code)
e5cb08ac 6739 int code;
64a0c779
DN		 6740{
6741 if (cur_token.code == code)
6742 {
6743 intel_get_token ();
6744 return 1;
6745 }
6746 else
6747 {
0477af35 6748 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 6749 return 0;
6750 }
6751}
6752
64a0c779
DN		 6753/* Read a new token from intel_parser.op_string and store it in cur_token. */
6754static void
6755intel_get_token ()
6756{
6757 char *end_op;
6758 const reg_entry *reg;
6759 struct intel_token new_token;
6760
6761 new_token.code = T_NIL;
6762 new_token.reg = NULL;
6763 new_token.str = NULL;
6764
4a1805b1 6765 /* Free the memory allocated to the previous token and move
64a0c779
DN		 6766 cur_token to prev_token. */
6767 if (prev_token.str)
6768 free (prev_token.str);
6769
6770 prev_token = cur_token;
6771
6772 /* Skip whitespace. */
6773 while (is_space_char (*intel_parser.op_string))
6774 intel_parser.op_string++;
6775
6776 /* Return an empty token if we find nothing else on the line. */
6777 if (*intel_parser.op_string == '\0')
6778 {
6779 cur_token = new_token;
6780 return;
6781 }
6782
6783 /* The new token cannot be larger than the remainder of the operand
6784 string. */
a724f0f4 6785 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 6786 new_token.str[0] = '\0';
6787
6788 if (strchr ("0123456789", *intel_parser.op_string))
6789 {
6790 char *p = new_token.str;
6791 char *q = intel_parser.op_string;
6792 new_token.code = T_CONST;
6793
6794 /* Allow any kind of identifier char to encompass floating point and
6795 hexadecimal numbers. */
6796 while (is_identifier_char (*q))
6797 *p++ = *q++;
6798 *p = '\0';
6799
6800 /* Recognize special symbol names [0-9][bf]. */
6801 if (strlen (intel_parser.op_string) == 2
4a1805b1 6802 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 6803 || intel_parser.op_string[1] == 'f'))
6804 new_token.code = T_ID;
6805 }
6806
64a0c779
DN		 6807 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
6808 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
6809 {
6810 new_token.code = T_REG;
6811 new_token.reg = reg;
6812
6813 if (*intel_parser.op_string == REGISTER_PREFIX)
6814 {
6815 new_token.str[0] = REGISTER_PREFIX;
6816 new_token.str[1] = '\0';
6817 }
6818
6819 strcat (new_token.str, reg->reg_name);
6820 }
6821
6822 else if (is_identifier_char (*intel_parser.op_string))
6823 {
6824 char *p = new_token.str;
6825 char *q = intel_parser.op_string;
6826
6827 /* A '.' or '$' followed by an identifier char is an identifier.
6828 Otherwise, it's operator '.' followed by an expression. */
6829 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6830 {
9306ca4a
JB		 6831 new_token.code = '.';
6832 new_token.str[0] = '.';
64a0c779
DN		 6833 new_token.str[1] = '\0';
6834 }
6835 else
6836 {
6837 while (is_identifier_char (*q) || *q == '@')
6838 *p++ = *q++;
6839 *p = '\0';
6840
9306ca4a
JB		 6841 if (strcasecmp (new_token.str, "NOT") == 0)
6842 new_token.code = '~';
6843
6844 else if (strcasecmp (new_token.str, "MOD") == 0)
6845 new_token.code = '%';
6846
6847 else if (strcasecmp (new_token.str, "AND") == 0)
6848 new_token.code = '&';
6849
6850 else if (strcasecmp (new_token.str, "OR") == 0)
6851 new_token.code = '|';
6852
6853 else if (strcasecmp (new_token.str, "XOR") == 0)
6854 new_token.code = '^';
6855
6856 else if (strcasecmp (new_token.str, "SHL") == 0)
6857 new_token.code = T_SHL;
6858
6859 else if (strcasecmp (new_token.str, "SHR") == 0)
6860 new_token.code = T_SHR;
6861
6862 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 6863 new_token.code = T_BYTE;
6864
6865 else if (strcasecmp (new_token.str, "WORD") == 0)
6866 new_token.code = T_WORD;
6867
6868 else if (strcasecmp (new_token.str, "DWORD") == 0)
6869 new_token.code = T_DWORD;
6870
9306ca4a
JB		 6871 else if (strcasecmp (new_token.str, "FWORD") == 0)
6872 new_token.code = T_FWORD;
6873
64a0c779
DN		 6874 else if (strcasecmp (new_token.str, "QWORD") == 0)
6875 new_token.code = T_QWORD;
6876
9306ca4a
JB		 6877 else if (strcasecmp (new_token.str, "TBYTE") == 0
6878 /* XXX remove (gcc still uses it) */
6879 || strcasecmp (new_token.str, "XWORD") == 0)
6880 new_token.code = T_TBYTE;
6881
6882 else if (strcasecmp (new_token.str, "XMMWORD") == 0
6883 || strcasecmp (new_token.str, "OWORD") == 0)
6884 new_token.code = T_XMMWORD;
64a0c779
DN		 6885
6886 else if (strcasecmp (new_token.str, "PTR") == 0)
6887 new_token.code = T_PTR;
6888
6889 else if (strcasecmp (new_token.str, "SHORT") == 0)
6890 new_token.code = T_SHORT;
6891
6892 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6893 {
6894 new_token.code = T_OFFSET;
6895
6896 /* ??? This is not mentioned in the MASM grammar but gcc
6897 makes use of it with -mintel-syntax. OFFSET may be
6898 followed by FLAT: */
6899 if (strncasecmp (q, " FLAT:", 6) == 0)
6900 strcat (new_token.str, " FLAT:");
6901 }
6902
6903 /* ??? This is not mentioned in the MASM grammar. */
6904 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 6905 {
6906 new_token.code = T_OFFSET;
6907 if (*q == ':')
6908 strcat (new_token.str, ":");
6909 else
6910 as_bad (_("`:' expected"));
6911 }
64a0c779
DN		 6912
6913 else
6914 new_token.code = T_ID;
6915 }
6916 }
6917
9306ca4a
JB		 6918 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
6919 {
6920 new_token.code = *intel_parser.op_string;
6921 new_token.str[0] = *intel_parser.op_string;
6922 new_token.str[1] = '\0';
6923 }
6924
6925 else if (strchr ("<>", *intel_parser.op_string)
6926 && *intel_parser.op_string == *(intel_parser.op_string + 1))
6927 {
6928 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
6929 new_token.str[0] = *intel_parser.op_string;
6930 new_token.str[1] = *intel_parser.op_string;
6931 new_token.str[2] = '\0';
6932 }
6933
64a0c779 6934 else
0477af35 6935 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 6936
6937 intel_parser.op_string += strlen (new_token.str);
6938 cur_token = new_token;
6939}
6940
64a0c779
DN		 6941/* Put cur_token back into the token stream and make cur_token point to
6942 prev_token. */
6943static void
6944intel_putback_token ()
6945{
a724f0f4
JB		 6946 if (cur_token.code != T_NIL)
6947 {
6948 intel_parser.op_string -= strlen (cur_token.str);
6949 free (cur_token.str);
6950 }
64a0c779 6951 cur_token = prev_token;
4a1805b1 6952
64a0c779
DN		 6953 /* Forget prev_token. */
6954 prev_token.code = T_NIL;
6955 prev_token.reg = NULL;
6956 prev_token.str = NULL;
6957}
54cfded0 6958
a4447b93 6959int
54cfded0
AM		 6960tc_x86_regname_to_dw2regnum (const char *regname)
6961{
6962 unsigned int regnum;
6963 unsigned int regnames_count;
089dfecd 6964 static const char *const regnames_32[] =
54cfded0 6965 {
a4447b93
RH		 6966 "eax", "ecx", "edx", "ebx",
6967 "esp", "ebp", "esi", "edi",
089dfecd
JB		 6968 "eip", "eflags", NULL,
6969 "st0", "st1", "st2", "st3",
6970 "st4", "st5", "st6", "st7",
6971 NULL, NULL,
6972 "xmm0", "xmm1", "xmm2", "xmm3",
6973 "xmm4", "xmm5", "xmm6", "xmm7",
6974 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 6975 "mm4", "mm5", "mm6", "mm7",
6976 "fcw", "fsw", "mxcsr",
6977 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
6978 "tr", "ldtr"
54cfded0 6979 };
089dfecd 6980 static const char *const regnames_64[] =
54cfded0 6981 {
089dfecd
JB		 6982 "rax", "rdx", "rcx", "rbx",
6983 "rsi", "rdi", "rbp", "rsp",
6984 "r8", "r9", "r10", "r11",
54cfded0 6985 "r12", "r13", "r14", "r15",
089dfecd
JB		 6986 "rip",
6987 "xmm0", "xmm1", "xmm2", "xmm3",
6988 "xmm4", "xmm5", "xmm6", "xmm7",
6989 "xmm8", "xmm9", "xmm10", "xmm11",
6990 "xmm12", "xmm13", "xmm14", "xmm15",
6991 "st0", "st1", "st2", "st3",
6992 "st4", "st5", "st6", "st7",
6993 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 6994 "mm4", "mm5", "mm6", "mm7",
6995 "rflags",
6996 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
6997 "fs.base", "gs.base", NULL, NULL,
6998 "tr", "ldtr",
6999 "mxcsr", "fcw", "fsw"
54cfded0 7000 };
089dfecd 7001 const char *const *regnames;
54cfded0
AM		 7002
7003 if (flag_code == CODE_64BIT)
7004 {
7005 regnames = regnames_64;
0cea6190 7006 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 7007 }
7008 else
7009 {
7010 regnames = regnames_32;
0cea6190 7011 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 7012 }
7013
7014 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 7015 if (regnames[regnum] != NULL
7016 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 7017 return regnum;
7018
54cfded0
AM		 7019 return -1;
7020}
7021
7022void
7023tc_x86_frame_initial_instructions (void)
7024{
a4447b93
RH		 7025 static unsigned int sp_regno;
7026
7027 if (!sp_regno)
7028 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7029 ? "rsp" : "esp");
7030
7031 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7032 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 7033}
d2b2c203
DJ		 7034
7035int
7036i386_elf_section_type (const char *str, size_t len)
7037{
7038 if (flag_code == CODE_64BIT
7039 && len == sizeof ("unwind") - 1
7040 && strncmp (str, "unwind", 6) == 0)
7041 return SHT_X86_64_UNWIND;
7042
7043 return -1;
7044}
bb41ade5
AM		 7045
7046#ifdef TE_PE
7047void
7048tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7049{
7050 expressionS expr;
7051
7052 expr.X_op = O_secrel;
7053 expr.X_add_symbol = symbol;
7054 expr.X_add_number = 0;
7055 emit_expr (&expr, size);
7056}
7057#endif
3b22753a
L		 7058
7059#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7060/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7061
7062int
7063x86_64_section_letter (int letter, char **ptr_msg)
7064{
7065 if (flag_code == CODE_64BIT)
7066 {
7067 if (letter == 'l')
7068 return SHF_X86_64_LARGE;
7069
7070 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7071 }
7072 else
7073 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
7074 return -1;
7075}
7076
7077int
7078x86_64_section_word (char *str, size_t len)
7079{
7080 if (len == 5 && flag_code == CODE_64BIT && strncmp (str, "large", 5) == 0)
7081 return SHF_X86_64_LARGE;
7082
7083 return -1;
7084}
7085
7086static void
7087handle_large_common (int small ATTRIBUTE_UNUSED)
7088{
7089 if (flag_code != CODE_64BIT)
7090 {
7091 s_comm_internal (0, elf_common_parse);
7092 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7093 }
7094 else
7095 {
7096 static segT lbss_section;
7097 asection *saved_com_section_ptr = elf_com_section_ptr;
7098 asection *saved_bss_section = bss_section;
7099
7100 if (lbss_section == NULL)
7101 {
7102 flagword applicable;
7103 segT seg = now_seg;
7104 subsegT subseg = now_subseg;
7105
7106 /* The .lbss section is for local .largecomm symbols. */
7107 lbss_section = subseg_new (".lbss", 0);
7108 applicable = bfd_applicable_section_flags (stdoutput);
7109 bfd_set_section_flags (stdoutput, lbss_section,
7110 applicable & SEC_ALLOC);
7111 seg_info (lbss_section)->bss = 1;
7112
7113 subseg_set (seg, subseg);
7114 }
7115
7116 elf_com_section_ptr = &_bfd_elf_large_com_section;
7117 bss_section = lbss_section;
7118
7119 s_comm_internal (0, elf_common_parse);
7120
7121 elf_com_section_ptr = saved_com_section_ptr;
7122 bss_section = saved_bss_section;
7123 }
7124}
7125#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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