Commit | Line | Data |
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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
f7e42eb4 | 2 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
5dd15031 | 3 | 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 |
47926f60 | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | |
6 | This file is part of GAS, the GNU Assembler. | |
7 | ||
8 | GAS is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
11 | any later version. |
12 | ||
13 | GAS is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
20 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
21 | 02110-1301, USA. */ | |
252b5132 | 22 | |
47926f60 KH |
23 | /* Intel 80386 machine specific gas. |
24 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 25 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
27 | Bugs & suggestions are completely welcome. This is free software. |
28 | Please help us make it better. */ | |
252b5132 | 29 | |
252b5132 | 30 | #include "as.h" |
3882b010 | 31 | #include "safe-ctype.h" |
252b5132 | 32 | #include "subsegs.h" |
316e2c05 | 33 | #include "dwarf2dbg.h" |
54cfded0 | 34 | #include "dw2gencfi.h" |
d2b2c203 | 35 | #include "elf/x86-64.h" |
40fb9820 | 36 | #include "opcodes/i386-init.h" |
252b5132 | 37 | |
252b5132 RH |
38 | #ifndef REGISTER_WARNINGS |
39 | #define REGISTER_WARNINGS 1 | |
40 | #endif | |
41 | ||
c3332e24 | 42 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 43 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
44 | #endif |
45 | ||
29b0f896 AM |
46 | #ifndef DEFAULT_ARCH |
47 | #define DEFAULT_ARCH "i386" | |
246fcdee | 48 | #endif |
252b5132 | 49 | |
edde18a5 AM |
50 | #ifndef INLINE |
51 | #if __GNUC__ >= 2 | |
52 | #define INLINE __inline__ | |
53 | #else | |
54 | #define INLINE | |
55 | #endif | |
56 | #endif | |
57 | ||
6305a203 L |
58 | /* Prefixes will be emitted in the order defined below. |
59 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
60 | instruction, and so must come before any prefixes. | |
61 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
62 | LOCKREP_PREFIX. */ | |
63 | #define WAIT_PREFIX 0 | |
64 | #define SEG_PREFIX 1 | |
65 | #define ADDR_PREFIX 2 | |
66 | #define DATA_PREFIX 3 | |
67 | #define LOCKREP_PREFIX 4 | |
68 | #define REX_PREFIX 5 /* must come last. */ | |
69 | #define MAX_PREFIXES 6 /* max prefixes per opcode */ | |
70 | ||
71 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
72 | #define REGISTER_PREFIX '%' | |
73 | #define IMMEDIATE_PREFIX '$' | |
74 | #define ABSOLUTE_PREFIX '*' | |
75 | ||
76 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
77 | memory operand size in Intel syntax. */ | |
78 | #define WORD_MNEM_SUFFIX 'w' | |
79 | #define BYTE_MNEM_SUFFIX 'b' | |
80 | #define SHORT_MNEM_SUFFIX 's' | |
81 | #define LONG_MNEM_SUFFIX 'l' | |
82 | #define QWORD_MNEM_SUFFIX 'q' | |
83 | #define XMMWORD_MNEM_SUFFIX 'x' | |
84 | /* Intel Syntax. Use a non-ascii letter since since it never appears | |
85 | in instructions. */ | |
86 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' | |
87 | ||
88 | #define END_OF_INSN '\0' | |
89 | ||
90 | /* | |
91 | 'templates' is for grouping together 'template' structures for opcodes | |
92 | of the same name. This is only used for storing the insns in the grand | |
93 | ole hash table of insns. | |
94 | The templates themselves start at START and range up to (but not including) | |
95 | END. | |
96 | */ | |
97 | typedef struct | |
98 | { | |
99 | const template *start; | |
100 | const template *end; | |
101 | } | |
102 | templates; | |
103 | ||
104 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
105 | typedef struct | |
106 | { | |
107 | unsigned int regmem; /* codes register or memory operand */ | |
108 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
109 | unsigned int mode; /* how to interpret regmem & reg */ | |
110 | } | |
111 | modrm_byte; | |
112 | ||
113 | /* x86-64 extension prefix. */ | |
114 | typedef int rex_byte; | |
115 | ||
116 | /* The SSE5 instructions have a two bit instruction modifier (OC) that | |
117 | is stored in two separate bytes in the instruction. Pick apart OC | |
118 | into the 2 separate bits for instruction. */ | |
119 | #define DREX_OC0(x) (((x) & 1) != 0) | |
120 | #define DREX_OC1(x) (((x) & 2) != 0) | |
121 | ||
122 | #define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */ | |
123 | #define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */ | |
124 | ||
125 | /* OC mappings */ | |
126 | #define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */ | |
127 | #define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */ | |
128 | #define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */ | |
129 | #define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */ | |
130 | ||
131 | #define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */ | |
132 | #define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */ | |
133 | ||
134 | /* Information needed to create the DREX byte in SSE5 instructions. */ | |
135 | typedef struct | |
136 | { | |
137 | unsigned int reg; /* register */ | |
138 | unsigned int rex; /* REX flags */ | |
139 | unsigned int modrm_reg; /* which arg goes in the modrm.reg field */ | |
140 | unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */ | |
141 | } drex_byte; | |
142 | ||
143 | /* 386 opcode byte to code indirect addressing. */ | |
144 | typedef struct | |
145 | { | |
146 | unsigned base; | |
147 | unsigned index; | |
148 | unsigned scale; | |
149 | } | |
150 | sib_byte; | |
151 | ||
152 | enum processor_type | |
153 | { | |
154 | PROCESSOR_UNKNOWN, | |
155 | PROCESSOR_I386, | |
156 | PROCESSOR_I486, | |
157 | PROCESSOR_PENTIUM, | |
158 | PROCESSOR_PENTIUMPRO, | |
159 | PROCESSOR_PENTIUM4, | |
160 | PROCESSOR_NOCONA, | |
161 | PROCESSOR_CORE, | |
162 | PROCESSOR_CORE2, | |
163 | PROCESSOR_K6, | |
164 | PROCESSOR_ATHLON, | |
165 | PROCESSOR_K8, | |
166 | PROCESSOR_GENERIC32, | |
167 | PROCESSOR_GENERIC64, | |
168 | PROCESSOR_AMDFAM10 | |
169 | }; | |
170 | ||
171 | /* x86 arch names, types and features */ | |
172 | typedef struct | |
173 | { | |
174 | const char *name; /* arch name */ | |
175 | enum processor_type type; /* arch type */ | |
176 | i386_cpu_flags flags; /* cpu feature flags */ | |
177 | } | |
178 | arch_entry; | |
179 | ||
e3bb37b5 L |
180 | static void set_code_flag (int); |
181 | static void set_16bit_gcc_code_flag (int); | |
182 | static void set_intel_syntax (int); | |
1efbbeb4 | 183 | static void set_intel_mnemonic (int); |
db51cc60 | 184 | static void set_allow_index_reg (int); |
e3bb37b5 | 185 | static void set_cpu_arch (int); |
6482c264 | 186 | #ifdef TE_PE |
e3bb37b5 | 187 | static void pe_directive_secrel (int); |
6482c264 | 188 | #endif |
e3bb37b5 L |
189 | static void signed_cons (int); |
190 | static char *output_invalid (int c); | |
a7619375 | 191 | static int i386_att_operand (char *); |
e3bb37b5 L |
192 | static int i386_intel_operand (char *, int); |
193 | static const reg_entry *parse_register (char *, char **); | |
194 | static char *parse_insn (char *, char *); | |
195 | static char *parse_operands (char *, const char *); | |
196 | static void swap_operands (void); | |
4d456e3d | 197 | static void swap_2_operands (int, int); |
e3bb37b5 L |
198 | static void optimize_imm (void); |
199 | static void optimize_disp (void); | |
200 | static int match_template (void); | |
201 | static int check_string (void); | |
202 | static int process_suffix (void); | |
203 | static int check_byte_reg (void); | |
204 | static int check_long_reg (void); | |
205 | static int check_qword_reg (void); | |
206 | static int check_word_reg (void); | |
207 | static int finalize_imm (void); | |
85f10a01 | 208 | static void process_drex (void); |
e3bb37b5 L |
209 | static int process_operands (void); |
210 | static const seg_entry *build_modrm_byte (void); | |
211 | static void output_insn (void); | |
212 | static void output_imm (fragS *, offsetT); | |
213 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 214 | #ifndef I386COFF |
e3bb37b5 | 215 | static void s_bss (int); |
252b5132 | 216 | #endif |
17d4e2a2 L |
217 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
218 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
219 | #endif | |
252b5132 | 220 | |
a847613f | 221 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 222 | |
252b5132 | 223 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 224 | i386_insn. */ |
252b5132 | 225 | |
520dc8e8 AM |
226 | union i386_op |
227 | { | |
228 | expressionS *disps; | |
229 | expressionS *imms; | |
230 | const reg_entry *regs; | |
231 | }; | |
232 | ||
252b5132 RH |
233 | struct _i386_insn |
234 | { | |
47926f60 | 235 | /* TM holds the template for the insn were currently assembling. */ |
252b5132 RH |
236 | template tm; |
237 | ||
7d5e4556 L |
238 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
239 | or qword, if given. */ | |
252b5132 RH |
240 | char suffix; |
241 | ||
47926f60 | 242 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
243 | unsigned int operands; |
244 | ||
245 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
246 | of given register, displacement, memory operands and immediate | |
47926f60 | 247 | operands. */ |
252b5132 RH |
248 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
249 | ||
250 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 251 | use OP[i] for the corresponding operand. */ |
40fb9820 | 252 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 253 | |
520dc8e8 AM |
254 | /* Displacement expression, immediate expression, or register for each |
255 | operand. */ | |
256 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 257 | |
3e73aa7c JH |
258 | /* Flags for operands. */ |
259 | unsigned int flags[MAX_OPERANDS]; | |
260 | #define Operand_PCrel 1 | |
261 | ||
252b5132 | 262 | /* Relocation type for operand */ |
f86103b7 | 263 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 264 | |
252b5132 RH |
265 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
266 | the base index byte below. */ | |
267 | const reg_entry *base_reg; | |
268 | const reg_entry *index_reg; | |
269 | unsigned int log2_scale_factor; | |
270 | ||
271 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 272 | explicit segment overrides are given. */ |
ce8a8b2f | 273 | const seg_entry *seg[2]; |
252b5132 RH |
274 | |
275 | /* PREFIX holds all the given prefix opcodes (usually null). | |
276 | PREFIXES is the number of prefix opcodes. */ | |
277 | unsigned int prefixes; | |
278 | unsigned char prefix[MAX_PREFIXES]; | |
279 | ||
280 | /* RM and SIB are the modrm byte and the sib byte where the | |
85f10a01 MM |
281 | addressing modes of this insn are encoded. DREX is the byte |
282 | added by the SSE5 instructions. */ | |
252b5132 RH |
283 | |
284 | modrm_byte rm; | |
3e73aa7c | 285 | rex_byte rex; |
252b5132 | 286 | sib_byte sib; |
85f10a01 | 287 | drex_byte drex; |
252b5132 RH |
288 | }; |
289 | ||
290 | typedef struct _i386_insn i386_insn; | |
291 | ||
292 | /* List of chars besides those in app.c:symbol_chars that can start an | |
293 | operand. Used to prevent the scrubber eating vital white-space. */ | |
32137342 | 294 | const char extra_symbol_chars[] = "*%-([" |
252b5132 | 295 | #ifdef LEX_AT |
32137342 NC |
296 | "@" |
297 | #endif | |
298 | #ifdef LEX_QM | |
299 | "?" | |
252b5132 | 300 | #endif |
32137342 | 301 | ; |
252b5132 | 302 | |
29b0f896 AM |
303 | #if (defined (TE_I386AIX) \ |
304 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
3896cfd5 | 305 | && !defined (TE_GNU) \ |
29b0f896 | 306 | && !defined (TE_LINUX) \ |
32137342 | 307 | && !defined (TE_NETWARE) \ |
29b0f896 AM |
308 | && !defined (TE_FreeBSD) \ |
309 | && !defined (TE_NetBSD))) | |
252b5132 | 310 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
311 | pre-processor is disabled, these aren't very useful. The option |
312 | --divide will remove '/' from this list. */ | |
313 | const char *i386_comment_chars = "#/"; | |
314 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 315 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 316 | |
b3b91714 AM |
317 | #else |
318 | const char *i386_comment_chars = "#"; | |
319 | #define PREFIX_SEPARATOR '/' | |
320 | #endif | |
321 | ||
252b5132 RH |
322 | /* This array holds the chars that only start a comment at the beginning of |
323 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
324 | .line and .file directives will appear in the pre-processed output. |
325 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 326 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
327 | #NO_APP at the beginning of its output. |
328 | Also note that comments started like this one will always work if | |
252b5132 | 329 | '/' isn't otherwise defined. */ |
b3b91714 | 330 | const char line_comment_chars[] = "#/"; |
252b5132 | 331 | |
63a0b638 | 332 | const char line_separator_chars[] = ";"; |
252b5132 | 333 | |
ce8a8b2f AM |
334 | /* Chars that can be used to separate mant from exp in floating point |
335 | nums. */ | |
252b5132 RH |
336 | const char EXP_CHARS[] = "eE"; |
337 | ||
ce8a8b2f AM |
338 | /* Chars that mean this number is a floating point constant |
339 | As in 0f12.456 | |
340 | or 0d1.2345e12. */ | |
252b5132 RH |
341 | const char FLT_CHARS[] = "fFdDxX"; |
342 | ||
ce8a8b2f | 343 | /* Tables for lexical analysis. */ |
252b5132 RH |
344 | static char mnemonic_chars[256]; |
345 | static char register_chars[256]; | |
346 | static char operand_chars[256]; | |
347 | static char identifier_chars[256]; | |
348 | static char digit_chars[256]; | |
349 | ||
ce8a8b2f | 350 | /* Lexical macros. */ |
252b5132 RH |
351 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
352 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
353 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
354 | #define is_space_char(x) ((x) == ' ') | |
355 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
356 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
357 | ||
0234cb7c | 358 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
359 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
360 | ||
361 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
362 | effect this we maintain a stack of saved characters that we've smashed | |
363 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 364 | assembler instruction). */ |
252b5132 | 365 | static char save_stack[32]; |
ce8a8b2f | 366 | static char *save_stack_p; |
252b5132 RH |
367 | #define END_STRING_AND_SAVE(s) \ |
368 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
369 | #define RESTORE_END_STRING(s) \ | |
370 | do { *(s) = *--save_stack_p; } while (0) | |
371 | ||
47926f60 | 372 | /* The instruction we're assembling. */ |
252b5132 RH |
373 | static i386_insn i; |
374 | ||
375 | /* Possible templates for current insn. */ | |
376 | static const templates *current_templates; | |
377 | ||
31b2323c L |
378 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
379 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
380 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 381 | |
47926f60 KH |
382 | /* Current operand we are working on. */ |
383 | static int this_operand; | |
252b5132 | 384 | |
3e73aa7c JH |
385 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
386 | these. */ | |
387 | ||
388 | enum flag_code { | |
389 | CODE_32BIT, | |
390 | CODE_16BIT, | |
391 | CODE_64BIT }; | |
392 | ||
393 | static enum flag_code flag_code; | |
4fa24527 | 394 | static unsigned int object_64bit; |
3e73aa7c JH |
395 | static int use_rela_relocations = 0; |
396 | ||
397 | /* The names used to print error messages. */ | |
b77a7acd | 398 | static const char *flag_code_names[] = |
3e73aa7c JH |
399 | { |
400 | "32", | |
401 | "16", | |
402 | "64" | |
403 | }; | |
252b5132 | 404 | |
47926f60 KH |
405 | /* 1 for intel syntax, |
406 | 0 if att syntax. */ | |
407 | static int intel_syntax = 0; | |
252b5132 | 408 | |
1efbbeb4 L |
409 | /* 1 for intel mnemonic, |
410 | 0 if att mnemonic. */ | |
411 | static int intel_mnemonic = !SYSV386_COMPAT; | |
412 | ||
5209009a | 413 | /* 1 if support old (<= 2.8.1) versions of gcc. */ |
1efbbeb4 L |
414 | static int old_gcc = OLDGCC_COMPAT; |
415 | ||
47926f60 KH |
416 | /* 1 if register prefix % not required. */ |
417 | static int allow_naked_reg = 0; | |
252b5132 | 418 | |
ba104c83 | 419 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
420 | static int allow_index_reg = 0; |
421 | ||
2ca3ace5 L |
422 | /* Register prefix used for error message. */ |
423 | static const char *register_prefix = "%"; | |
424 | ||
47926f60 KH |
425 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
426 | leave, push, and pop instructions so that gcc has the same stack | |
427 | frame as in 32 bit mode. */ | |
428 | static char stackop_size = '\0'; | |
eecb386c | 429 | |
12b55ccc L |
430 | /* Non-zero to optimize code alignment. */ |
431 | int optimize_align_code = 1; | |
432 | ||
47926f60 KH |
433 | /* Non-zero to quieten some warnings. */ |
434 | static int quiet_warnings = 0; | |
a38cf1db | 435 | |
47926f60 KH |
436 | /* CPU name. */ |
437 | static const char *cpu_arch_name = NULL; | |
6305a203 | 438 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 439 | |
47926f60 | 440 | /* CPU feature flags. */ |
40fb9820 L |
441 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
442 | ||
ccc9c027 L |
443 | /* If we have selected a cpu we are generating instructions for. */ |
444 | static int cpu_arch_tune_set = 0; | |
445 | ||
9103f4f4 L |
446 | /* Cpu we are generating instructions for. */ |
447 | static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; | |
448 | ||
449 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 450 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 451 | |
ccc9c027 L |
452 | /* CPU instruction set architecture used. */ |
453 | static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; | |
454 | ||
9103f4f4 | 455 | /* CPU feature flags of instruction set architecture used. */ |
40fb9820 | 456 | static i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 457 | |
fddf5b5b AM |
458 | /* If set, conditional jumps are not automatically promoted to handle |
459 | larger than a byte offset. */ | |
460 | static unsigned int no_cond_jump_promotion = 0; | |
461 | ||
29b0f896 | 462 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 463 | static symbolS *GOT_symbol; |
29b0f896 | 464 | |
a4447b93 RH |
465 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
466 | unsigned int x86_dwarf2_return_column; | |
467 | ||
468 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
469 | int x86_cie_data_alignment; | |
470 | ||
252b5132 | 471 | /* Interface to relax_segment. |
fddf5b5b AM |
472 | There are 3 major relax states for 386 jump insns because the |
473 | different types of jumps add different sizes to frags when we're | |
474 | figuring out what sort of jump to choose to reach a given label. */ | |
252b5132 | 475 | |
47926f60 | 476 | /* Types. */ |
93c2a809 AM |
477 | #define UNCOND_JUMP 0 |
478 | #define COND_JUMP 1 | |
479 | #define COND_JUMP86 2 | |
fddf5b5b | 480 | |
47926f60 | 481 | /* Sizes. */ |
252b5132 RH |
482 | #define CODE16 1 |
483 | #define SMALL 0 | |
29b0f896 | 484 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 485 | #define BIG 2 |
29b0f896 | 486 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
487 | |
488 | #ifndef INLINE | |
489 | #ifdef __GNUC__ | |
490 | #define INLINE __inline__ | |
491 | #else | |
492 | #define INLINE | |
493 | #endif | |
494 | #endif | |
495 | ||
fddf5b5b AM |
496 | #define ENCODE_RELAX_STATE(type, size) \ |
497 | ((relax_substateT) (((type) << 2) | (size))) | |
498 | #define TYPE_FROM_RELAX_STATE(s) \ | |
499 | ((s) >> 2) | |
500 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
501 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
502 | |
503 | /* This table is used by relax_frag to promote short jumps to long | |
504 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
505 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
506 | don't allow a short jump in a 32 bit code segment to be promoted to | |
507 | a 16 bit offset jump because it's slower (requires data size | |
508 | prefix), and doesn't work, unless the destination is in the bottom | |
509 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
510 | ||
511 | const relax_typeS md_relax_table[] = | |
512 | { | |
24eab124 AM |
513 | /* The fields are: |
514 | 1) most positive reach of this state, | |
515 | 2) most negative reach of this state, | |
93c2a809 | 516 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 517 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 518 | |
fddf5b5b | 519 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
520 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
521 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
522 | /* dword jmp adds 4 bytes to frag: | |
523 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 524 | {0, 0, 4, 0}, |
93c2a809 AM |
525 | /* word jmp adds 2 byte2 to frag: |
526 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
527 | {0, 0, 2, 0}, |
528 | ||
93c2a809 AM |
529 | /* COND_JUMP states. */ |
530 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
531 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
532 | /* dword conditionals adds 5 bytes to frag: | |
533 | 1 extra opcode byte, 4 displacement bytes. */ | |
534 | {0, 0, 5, 0}, | |
fddf5b5b | 535 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
536 | 1 extra opcode byte, 2 displacement bytes. */ |
537 | {0, 0, 3, 0}, | |
538 | ||
539 | /* COND_JUMP86 states. */ | |
540 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
541 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
542 | /* dword conditionals adds 5 bytes to frag: | |
543 | 1 extra opcode byte, 4 displacement bytes. */ | |
544 | {0, 0, 5, 0}, | |
545 | /* word conditionals add 4 bytes to frag: | |
546 | 1 displacement byte and a 3 byte long branch insn. */ | |
547 | {0, 0, 4, 0} | |
252b5132 RH |
548 | }; |
549 | ||
9103f4f4 L |
550 | static const arch_entry cpu_arch[] = |
551 | { | |
6305a203 L |
552 | { "generic32", PROCESSOR_GENERIC32, |
553 | CPU_GENERIC32_FLAGS }, | |
554 | { "generic64", PROCESSOR_GENERIC64, | |
555 | CPU_GENERIC64_FLAGS }, | |
556 | { "i8086", PROCESSOR_UNKNOWN, | |
557 | CPU_NONE_FLAGS }, | |
558 | { "i186", PROCESSOR_UNKNOWN, | |
559 | CPU_I186_FLAGS }, | |
560 | { "i286", PROCESSOR_UNKNOWN, | |
561 | CPU_I286_FLAGS }, | |
562 | { "i386", PROCESSOR_I386, | |
563 | CPU_I386_FLAGS }, | |
564 | { "i486", PROCESSOR_I486, | |
565 | CPU_I486_FLAGS }, | |
566 | { "i586", PROCESSOR_PENTIUM, | |
567 | CPU_I586_FLAGS }, | |
568 | { "i686", PROCESSOR_PENTIUMPRO, | |
569 | CPU_I686_FLAGS }, | |
570 | { "pentium", PROCESSOR_PENTIUM, | |
571 | CPU_I586_FLAGS }, | |
572 | { "pentiumpro", PROCESSOR_PENTIUMPRO, | |
573 | CPU_I686_FLAGS }, | |
574 | { "pentiumii", PROCESSOR_PENTIUMPRO, | |
575 | CPU_P2_FLAGS }, | |
576 | { "pentiumiii",PROCESSOR_PENTIUMPRO, | |
577 | CPU_P3_FLAGS }, | |
578 | { "pentium4", PROCESSOR_PENTIUM4, | |
579 | CPU_P4_FLAGS }, | |
580 | { "prescott", PROCESSOR_NOCONA, | |
581 | CPU_CORE_FLAGS }, | |
582 | { "nocona", PROCESSOR_NOCONA, | |
583 | CPU_NOCONA_FLAGS }, | |
584 | { "yonah", PROCESSOR_CORE, | |
585 | CPU_CORE_FLAGS }, | |
586 | { "core", PROCESSOR_CORE, | |
587 | CPU_CORE_FLAGS }, | |
588 | { "merom", PROCESSOR_CORE2, | |
589 | CPU_CORE2_FLAGS }, | |
590 | { "core2", PROCESSOR_CORE2, | |
591 | CPU_CORE2_FLAGS }, | |
592 | { "k6", PROCESSOR_K6, | |
593 | CPU_K6_FLAGS }, | |
594 | { "k6_2", PROCESSOR_K6, | |
595 | CPU_K6_2_FLAGS }, | |
596 | { "athlon", PROCESSOR_ATHLON, | |
597 | CPU_ATHLON_FLAGS }, | |
598 | { "sledgehammer", PROCESSOR_K8, | |
599 | CPU_K8_FLAGS }, | |
600 | { "opteron", PROCESSOR_K8, | |
601 | CPU_K8_FLAGS }, | |
602 | { "k8", PROCESSOR_K8, | |
603 | CPU_K8_FLAGS }, | |
604 | { "amdfam10", PROCESSOR_AMDFAM10, | |
605 | CPU_AMDFAM10_FLAGS }, | |
606 | { ".mmx", PROCESSOR_UNKNOWN, | |
607 | CPU_MMX_FLAGS }, | |
608 | { ".sse", PROCESSOR_UNKNOWN, | |
609 | CPU_SSE_FLAGS }, | |
610 | { ".sse2", PROCESSOR_UNKNOWN, | |
611 | CPU_SSE2_FLAGS }, | |
612 | { ".sse3", PROCESSOR_UNKNOWN, | |
613 | CPU_SSE3_FLAGS }, | |
614 | { ".ssse3", PROCESSOR_UNKNOWN, | |
615 | CPU_SSSE3_FLAGS }, | |
616 | { ".sse4.1", PROCESSOR_UNKNOWN, | |
617 | CPU_SSE4_1_FLAGS }, | |
618 | { ".sse4.2", PROCESSOR_UNKNOWN, | |
619 | CPU_SSE4_2_FLAGS }, | |
620 | { ".sse4", PROCESSOR_UNKNOWN, | |
621 | CPU_SSE4_2_FLAGS }, | |
622 | { ".vmx", PROCESSOR_UNKNOWN, | |
623 | CPU_VMX_FLAGS }, | |
624 | { ".smx", PROCESSOR_UNKNOWN, | |
625 | CPU_SMX_FLAGS }, | |
626 | { ".3dnow", PROCESSOR_UNKNOWN, | |
627 | CPU_3DNOW_FLAGS }, | |
628 | { ".3dnowa", PROCESSOR_UNKNOWN, | |
629 | CPU_3DNOWA_FLAGS }, | |
630 | { ".padlock", PROCESSOR_UNKNOWN, | |
631 | CPU_PADLOCK_FLAGS }, | |
632 | { ".pacifica", PROCESSOR_UNKNOWN, | |
633 | CPU_SVME_FLAGS }, | |
634 | { ".svme", PROCESSOR_UNKNOWN, | |
635 | CPU_SVME_FLAGS }, | |
636 | { ".sse4a", PROCESSOR_UNKNOWN, | |
637 | CPU_SSE4A_FLAGS }, | |
638 | { ".abm", PROCESSOR_UNKNOWN, | |
639 | CPU_ABM_FLAGS }, | |
640 | { ".sse5", PROCESSOR_UNKNOWN, | |
641 | CPU_SSE5_FLAGS }, | |
e413e4e9 AM |
642 | }; |
643 | ||
29b0f896 AM |
644 | const pseudo_typeS md_pseudo_table[] = |
645 | { | |
646 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
647 | {"align", s_align_bytes, 0}, | |
648 | #else | |
649 | {"align", s_align_ptwo, 0}, | |
650 | #endif | |
651 | {"arch", set_cpu_arch, 0}, | |
652 | #ifndef I386COFF | |
653 | {"bss", s_bss, 0}, | |
654 | #endif | |
655 | {"ffloat", float_cons, 'f'}, | |
656 | {"dfloat", float_cons, 'd'}, | |
657 | {"tfloat", float_cons, 'x'}, | |
658 | {"value", cons, 2}, | |
d182319b | 659 | {"slong", signed_cons, 4}, |
29b0f896 AM |
660 | {"noopt", s_ignore, 0}, |
661 | {"optim", s_ignore, 0}, | |
662 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
663 | {"code16", set_code_flag, CODE_16BIT}, | |
664 | {"code32", set_code_flag, CODE_32BIT}, | |
665 | {"code64", set_code_flag, CODE_64BIT}, | |
666 | {"intel_syntax", set_intel_syntax, 1}, | |
667 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
668 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
669 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
670 | {"allow_index_reg", set_allow_index_reg, 1}, |
671 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
3b22753a L |
672 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
673 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 674 | #else |
e3bb37b5 | 675 | {"file", (void (*) (int)) dwarf2_directive_file, 0}, |
07a53e5c RH |
676 | {"loc", dwarf2_directive_loc, 0}, |
677 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 678 | #endif |
6482c264 NC |
679 | #ifdef TE_PE |
680 | {"secrel32", pe_directive_secrel, 0}, | |
681 | #endif | |
29b0f896 AM |
682 | {0, 0, 0} |
683 | }; | |
684 | ||
685 | /* For interface with expression (). */ | |
686 | extern char *input_line_pointer; | |
687 | ||
688 | /* Hash table for instruction mnemonic lookup. */ | |
689 | static struct hash_control *op_hash; | |
690 | ||
691 | /* Hash table for register lookup. */ | |
692 | static struct hash_control *reg_hash; | |
693 | \f | |
252b5132 | 694 | void |
e3bb37b5 | 695 | i386_align_code (fragS *fragP, int count) |
252b5132 | 696 | { |
ce8a8b2f AM |
697 | /* Various efficient no-op patterns for aligning code labels. |
698 | Note: Don't try to assemble the instructions in the comments. | |
699 | 0L and 0w are not legal. */ | |
252b5132 RH |
700 | static const char f32_1[] = |
701 | {0x90}; /* nop */ | |
702 | static const char f32_2[] = | |
ccc9c027 | 703 | {0x66,0x90}; /* xchg %ax,%ax */ |
252b5132 RH |
704 | static const char f32_3[] = |
705 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
706 | static const char f32_4[] = | |
707 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
708 | static const char f32_5[] = | |
709 | {0x90, /* nop */ | |
710 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
711 | static const char f32_6[] = | |
712 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
713 | static const char f32_7[] = | |
714 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
715 | static const char f32_8[] = | |
716 | {0x90, /* nop */ | |
717 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
718 | static const char f32_9[] = | |
719 | {0x89,0xf6, /* movl %esi,%esi */ | |
720 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
721 | static const char f32_10[] = | |
722 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ | |
723 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
724 | static const char f32_11[] = | |
725 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ | |
726 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
727 | static const char f32_12[] = | |
728 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
729 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
730 | static const char f32_13[] = | |
731 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
732 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
733 | static const char f32_14[] = | |
734 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ | |
735 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
c3332e24 AM |
736 | static const char f16_3[] = |
737 | {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ | |
252b5132 RH |
738 | static const char f16_4[] = |
739 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
740 | static const char f16_5[] = | |
741 | {0x90, /* nop */ | |
742 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
743 | static const char f16_6[] = | |
744 | {0x89,0xf6, /* mov %si,%si */ | |
745 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
746 | static const char f16_7[] = | |
747 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ | |
748 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
749 | static const char f16_8[] = | |
750 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ | |
751 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
76bc74dc L |
752 | static const char jump_31[] = |
753 | {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */ | |
754 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, | |
755 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, | |
756 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
252b5132 RH |
757 | static const char *const f32_patt[] = { |
758 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, | |
76bc74dc | 759 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14 |
252b5132 RH |
760 | }; |
761 | static const char *const f16_patt[] = { | |
76bc74dc | 762 | f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8 |
252b5132 | 763 | }; |
ccc9c027 L |
764 | /* nopl (%[re]ax) */ |
765 | static const char alt_3[] = | |
766 | {0x0f,0x1f,0x00}; | |
767 | /* nopl 0(%[re]ax) */ | |
768 | static const char alt_4[] = | |
769 | {0x0f,0x1f,0x40,0x00}; | |
770 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
771 | static const char alt_5[] = | |
772 | {0x0f,0x1f,0x44,0x00,0x00}; | |
773 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
774 | static const char alt_6[] = | |
775 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
776 | /* nopl 0L(%[re]ax) */ | |
777 | static const char alt_7[] = | |
778 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
779 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
780 | static const char alt_8[] = | |
781 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
782 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
783 | static const char alt_9[] = | |
784 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
785 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
786 | static const char alt_10[] = | |
787 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
788 | /* data16 | |
789 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
790 | static const char alt_long_11[] = | |
791 | {0x66, | |
792 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
793 | /* data16 | |
794 | data16 | |
795 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
796 | static const char alt_long_12[] = | |
797 | {0x66, | |
798 | 0x66, | |
799 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
800 | /* data16 | |
801 | data16 | |
802 | data16 | |
803 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
804 | static const char alt_long_13[] = | |
805 | {0x66, | |
806 | 0x66, | |
807 | 0x66, | |
808 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
809 | /* data16 | |
810 | data16 | |
811 | data16 | |
812 | data16 | |
813 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
814 | static const char alt_long_14[] = | |
815 | {0x66, | |
816 | 0x66, | |
817 | 0x66, | |
818 | 0x66, | |
819 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
820 | /* data16 | |
821 | data16 | |
822 | data16 | |
823 | data16 | |
824 | data16 | |
825 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
826 | static const char alt_long_15[] = | |
827 | {0x66, | |
828 | 0x66, | |
829 | 0x66, | |
830 | 0x66, | |
831 | 0x66, | |
832 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
833 | /* nopl 0(%[re]ax,%[re]ax,1) | |
834 | nopw 0(%[re]ax,%[re]ax,1) */ | |
835 | static const char alt_short_11[] = | |
836 | {0x0f,0x1f,0x44,0x00,0x00, | |
837 | 0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
838 | /* nopw 0(%[re]ax,%[re]ax,1) | |
839 | nopw 0(%[re]ax,%[re]ax,1) */ | |
840 | static const char alt_short_12[] = | |
841 | {0x66,0x0f,0x1f,0x44,0x00,0x00, | |
842 | 0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
843 | /* nopw 0(%[re]ax,%[re]ax,1) | |
844 | nopl 0L(%[re]ax) */ | |
845 | static const char alt_short_13[] = | |
846 | {0x66,0x0f,0x1f,0x44,0x00,0x00, | |
847 | 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
848 | /* nopl 0L(%[re]ax) | |
849 | nopl 0L(%[re]ax) */ | |
850 | static const char alt_short_14[] = | |
851 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00, | |
852 | 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
853 | /* nopl 0L(%[re]ax) | |
854 | nopl 0L(%[re]ax,%[re]ax,1) */ | |
855 | static const char alt_short_15[] = | |
856 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00, | |
857 | 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
858 | static const char *const alt_short_patt[] = { | |
859 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
860 | alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13, | |
861 | alt_short_14, alt_short_15 | |
862 | }; | |
863 | static const char *const alt_long_patt[] = { | |
864 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
865 | alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13, | |
866 | alt_long_14, alt_long_15 | |
867 | }; | |
252b5132 | 868 | |
76bc74dc L |
869 | /* Only align for at least a positive non-zero boundary. */ |
870 | if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE) | |
33fef721 | 871 | return; |
3e73aa7c | 872 | |
ccc9c027 L |
873 | /* We need to decide which NOP sequence to use for 32bit and |
874 | 64bit. When -mtune= is used: | |
4eed87de | 875 | |
76bc74dc L |
876 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
877 | PROCESSOR_GENERIC32, f32_patt will be used. | |
878 | 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA, | |
879 | PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64, | |
880 | alt_long_patt will be used. | |
881 | 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and | |
882 | PROCESSOR_AMDFAM10, alt_short_patt will be used. | |
ccc9c027 | 883 | |
76bc74dc L |
884 | When -mtune= isn't used, alt_long_patt will be used if |
885 | cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will | |
886 | be used. | |
ccc9c027 L |
887 | |
888 | When -march= or .arch is used, we can't use anything beyond | |
889 | cpu_arch_isa_flags. */ | |
890 | ||
891 | if (flag_code == CODE_16BIT) | |
892 | { | |
ccc9c027 | 893 | if (count > 8) |
33fef721 | 894 | { |
76bc74dc L |
895 | memcpy (fragP->fr_literal + fragP->fr_fix, |
896 | jump_31, count); | |
897 | /* Adjust jump offset. */ | |
898 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
252b5132 | 899 | } |
76bc74dc L |
900 | else |
901 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
902 | f16_patt[count - 1], count); | |
252b5132 | 903 | } |
33fef721 | 904 | else |
ccc9c027 L |
905 | { |
906 | const char *const *patt = NULL; | |
907 | ||
908 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
909 | { | |
910 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
911 | switch (cpu_arch_tune) | |
912 | { | |
913 | case PROCESSOR_UNKNOWN: | |
914 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
915 | optimize for Cpu686. */ | |
40fb9820 | 916 | if (cpu_arch_isa_flags.bitfield.cpui686) |
76bc74dc | 917 | patt = alt_long_patt; |
ccc9c027 L |
918 | else |
919 | patt = f32_patt; | |
920 | break; | |
ccc9c027 L |
921 | case PROCESSOR_PENTIUMPRO: |
922 | case PROCESSOR_PENTIUM4: | |
923 | case PROCESSOR_NOCONA: | |
ef05d495 | 924 | case PROCESSOR_CORE: |
76bc74dc L |
925 | case PROCESSOR_CORE2: |
926 | case PROCESSOR_GENERIC64: | |
927 | patt = alt_long_patt; | |
928 | break; | |
ccc9c027 L |
929 | case PROCESSOR_K6: |
930 | case PROCESSOR_ATHLON: | |
931 | case PROCESSOR_K8: | |
4eed87de | 932 | case PROCESSOR_AMDFAM10: |
ccc9c027 L |
933 | patt = alt_short_patt; |
934 | break; | |
76bc74dc | 935 | case PROCESSOR_I386: |
ccc9c027 L |
936 | case PROCESSOR_I486: |
937 | case PROCESSOR_PENTIUM: | |
938 | case PROCESSOR_GENERIC32: | |
939 | patt = f32_patt; | |
940 | break; | |
4eed87de | 941 | } |
ccc9c027 L |
942 | } |
943 | else | |
944 | { | |
945 | switch (cpu_arch_tune) | |
946 | { | |
947 | case PROCESSOR_UNKNOWN: | |
948 | /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be | |
949 | PROCESSOR_UNKNOWN. */ | |
950 | abort (); | |
951 | break; | |
952 | ||
76bc74dc | 953 | case PROCESSOR_I386: |
ccc9c027 L |
954 | case PROCESSOR_I486: |
955 | case PROCESSOR_PENTIUM: | |
ccc9c027 L |
956 | case PROCESSOR_K6: |
957 | case PROCESSOR_ATHLON: | |
958 | case PROCESSOR_K8: | |
4eed87de | 959 | case PROCESSOR_AMDFAM10: |
ccc9c027 L |
960 | case PROCESSOR_GENERIC32: |
961 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
962 | for Cpu686. */ | |
40fb9820 | 963 | if (cpu_arch_isa_flags.bitfield.cpui686) |
ccc9c027 L |
964 | patt = alt_short_patt; |
965 | else | |
966 | patt = f32_patt; | |
967 | break; | |
76bc74dc L |
968 | case PROCESSOR_PENTIUMPRO: |
969 | case PROCESSOR_PENTIUM4: | |
970 | case PROCESSOR_NOCONA: | |
971 | case PROCESSOR_CORE: | |
ef05d495 | 972 | case PROCESSOR_CORE2: |
40fb9820 | 973 | if (cpu_arch_isa_flags.bitfield.cpui686) |
ccc9c027 L |
974 | patt = alt_long_patt; |
975 | else | |
976 | patt = f32_patt; | |
977 | break; | |
978 | case PROCESSOR_GENERIC64: | |
76bc74dc | 979 | patt = alt_long_patt; |
ccc9c027 | 980 | break; |
4eed87de | 981 | } |
ccc9c027 L |
982 | } |
983 | ||
76bc74dc L |
984 | if (patt == f32_patt) |
985 | { | |
986 | /* If the padding is less than 15 bytes, we use the normal | |
987 | ones. Otherwise, we use a jump instruction and adjust | |
988 | its offset. */ | |
989 | if (count < 15) | |
990 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
991 | patt[count - 1], count); | |
992 | else | |
993 | { | |
994 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
995 | jump_31, count); | |
996 | /* Adjust jump offset. */ | |
997 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
998 | } | |
999 | } | |
1000 | else | |
1001 | { | |
1002 | /* Maximum length of an instruction is 15 byte. If the | |
1003 | padding is greater than 15 bytes and we don't use jump, | |
1004 | we have to break it into smaller pieces. */ | |
1005 | int padding = count; | |
1006 | while (padding > 15) | |
1007 | { | |
1008 | padding -= 15; | |
1009 | memcpy (fragP->fr_literal + fragP->fr_fix + padding, | |
1010 | patt [14], 15); | |
1011 | } | |
1012 | ||
1013 | if (padding) | |
1014 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1015 | patt [padding - 1], padding); | |
1016 | } | |
ccc9c027 | 1017 | } |
33fef721 | 1018 | fragP->fr_var = count; |
252b5132 RH |
1019 | } |
1020 | ||
c6fb90c8 L |
1021 | static INLINE int |
1022 | uints_all_zero (const unsigned int *x, unsigned int size) | |
40fb9820 | 1023 | { |
c6fb90c8 L |
1024 | switch (size) |
1025 | { | |
1026 | case 3: | |
1027 | if (x[2]) | |
1028 | return 0; | |
1029 | case 2: | |
1030 | if (x[1]) | |
1031 | return 0; | |
1032 | case 1: | |
1033 | return !x[0]; | |
1034 | default: | |
1035 | abort (); | |
1036 | } | |
40fb9820 L |
1037 | } |
1038 | ||
c6fb90c8 L |
1039 | static INLINE void |
1040 | uints_set (unsigned int *x, unsigned int v, unsigned int size) | |
40fb9820 | 1041 | { |
c6fb90c8 L |
1042 | switch (size) |
1043 | { | |
1044 | case 3: | |
1045 | x[2] = v; | |
1046 | case 2: | |
1047 | x[1] = v; | |
1048 | case 1: | |
1049 | x[0] = v; | |
1050 | break; | |
1051 | default: | |
1052 | abort (); | |
1053 | } | |
1054 | } | |
40fb9820 | 1055 | |
c6fb90c8 L |
1056 | static INLINE int |
1057 | uints_equal (const unsigned int *x, const unsigned int *y, | |
1058 | unsigned int size) | |
1059 | { | |
1060 | switch (size) | |
1061 | { | |
1062 | case 3: | |
1063 | if (x[2] != y [2]) | |
1064 | return 0; | |
1065 | case 2: | |
1066 | if (x[1] != y [1]) | |
1067 | return 0; | |
1068 | case 1: | |
1069 | return x[0] == y [0]; | |
1070 | break; | |
1071 | default: | |
1072 | abort (); | |
1073 | } | |
1074 | } | |
40fb9820 | 1075 | |
c6fb90c8 L |
1076 | #define UINTS_ALL_ZERO(x) \ |
1077 | uints_all_zero ((x).array, ARRAY_SIZE ((x).array)) | |
1078 | #define UINTS_SET(x, v) \ | |
1079 | uints_set ((x).array, v, ARRAY_SIZE ((x).array)) | |
1080 | #define UINTS_CLEAR(x) \ | |
1081 | uints_set ((x).array, 0, ARRAY_SIZE ((x).array)) | |
1082 | #define UINTS_EQUAL(x, y) \ | |
1083 | uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array)) | |
1084 | ||
1085 | static INLINE int | |
1086 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1087 | { | |
1088 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1089 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1090 | } |
1091 | ||
c6fb90c8 L |
1092 | static INLINE i386_cpu_flags |
1093 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1094 | { |
c6fb90c8 L |
1095 | switch (ARRAY_SIZE (x.array)) |
1096 | { | |
1097 | case 3: | |
1098 | x.array [2] &= y.array [2]; | |
1099 | case 2: | |
1100 | x.array [1] &= y.array [1]; | |
1101 | case 1: | |
1102 | x.array [0] &= y.array [0]; | |
1103 | break; | |
1104 | default: | |
1105 | abort (); | |
1106 | } | |
1107 | return x; | |
1108 | } | |
40fb9820 | 1109 | |
c6fb90c8 L |
1110 | static INLINE i386_cpu_flags |
1111 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1112 | { |
c6fb90c8 | 1113 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1114 | { |
c6fb90c8 L |
1115 | case 3: |
1116 | x.array [2] |= y.array [2]; | |
1117 | case 2: | |
1118 | x.array [1] |= y.array [1]; | |
1119 | case 1: | |
1120 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1121 | break; |
1122 | default: | |
1123 | abort (); | |
1124 | } | |
40fb9820 L |
1125 | return x; |
1126 | } | |
1127 | ||
3629bb00 L |
1128 | /* Return 3 if there is a perfect match, 2 if compatible with 64bit, |
1129 | 1 if compatible with arch, 0 if there is no match. */ | |
1130 | ||
40fb9820 L |
1131 | static int |
1132 | cpu_flags_match (i386_cpu_flags x) | |
1133 | { | |
3629bb00 | 1134 | int overlap = cpu_flags_check_cpu64 (x) ? 2 : 0; |
40fb9820 L |
1135 | |
1136 | x.bitfield.cpu64 = 0; | |
1137 | x.bitfield.cpuno64 = 0; | |
1138 | ||
3629bb00 L |
1139 | if (UINTS_ALL_ZERO (x)) |
1140 | overlap |= 1; | |
1141 | else | |
1142 | { | |
1143 | i386_cpu_flags cpu = cpu_arch_flags; | |
1144 | ||
1145 | cpu.bitfield.cpu64 = 0; | |
1146 | cpu.bitfield.cpuno64 = 0; | |
1147 | cpu = cpu_flags_and (x, cpu); | |
1148 | overlap |= UINTS_ALL_ZERO (cpu) ? 0 : 1; | |
1149 | } | |
1150 | return overlap; | |
40fb9820 L |
1151 | } |
1152 | ||
c6fb90c8 L |
1153 | static INLINE i386_operand_type |
1154 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1155 | { |
c6fb90c8 L |
1156 | switch (ARRAY_SIZE (x.array)) |
1157 | { | |
1158 | case 3: | |
1159 | x.array [2] &= y.array [2]; | |
1160 | case 2: | |
1161 | x.array [1] &= y.array [1]; | |
1162 | case 1: | |
1163 | x.array [0] &= y.array [0]; | |
1164 | break; | |
1165 | default: | |
1166 | abort (); | |
1167 | } | |
1168 | return x; | |
40fb9820 L |
1169 | } |
1170 | ||
c6fb90c8 L |
1171 | static INLINE i386_operand_type |
1172 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1173 | { |
c6fb90c8 | 1174 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1175 | { |
c6fb90c8 L |
1176 | case 3: |
1177 | x.array [2] |= y.array [2]; | |
1178 | case 2: | |
1179 | x.array [1] |= y.array [1]; | |
1180 | case 1: | |
1181 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1182 | break; |
1183 | default: | |
1184 | abort (); | |
1185 | } | |
c6fb90c8 L |
1186 | return x; |
1187 | } | |
40fb9820 | 1188 | |
c6fb90c8 L |
1189 | static INLINE i386_operand_type |
1190 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
1191 | { | |
1192 | switch (ARRAY_SIZE (x.array)) | |
1193 | { | |
1194 | case 3: | |
1195 | x.array [2] ^= y.array [2]; | |
1196 | case 2: | |
1197 | x.array [1] ^= y.array [1]; | |
1198 | case 1: | |
1199 | x.array [0] ^= y.array [0]; | |
1200 | break; | |
1201 | default: | |
1202 | abort (); | |
1203 | } | |
40fb9820 L |
1204 | return x; |
1205 | } | |
1206 | ||
1207 | static const i386_operand_type acc32 = OPERAND_TYPE_ACC32; | |
1208 | static const i386_operand_type acc64 = OPERAND_TYPE_ACC64; | |
1209 | static const i386_operand_type control = OPERAND_TYPE_CONTROL; | |
1210 | static const i386_operand_type reg16_inoutportreg | |
1211 | = OPERAND_TYPE_REG16_INOUTPORTREG; | |
1212 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; | |
1213 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; | |
1214 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; | |
1215 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; | |
1216 | static const i386_operand_type anydisp | |
1217 | = OPERAND_TYPE_ANYDISP; | |
40fb9820 L |
1218 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
1219 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; | |
1220 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; | |
1221 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; | |
1222 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
1223 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
1224 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; | |
1225 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; | |
1226 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
1227 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
1228 | ||
1229 | enum operand_type | |
1230 | { | |
1231 | reg, | |
40fb9820 L |
1232 | imm, |
1233 | disp, | |
1234 | anymem | |
1235 | }; | |
1236 | ||
c6fb90c8 | 1237 | static INLINE int |
40fb9820 L |
1238 | operand_type_check (i386_operand_type t, enum operand_type c) |
1239 | { | |
1240 | switch (c) | |
1241 | { | |
1242 | case reg: | |
1243 | return (t.bitfield.reg8 | |
1244 | || t.bitfield.reg16 | |
1245 | || t.bitfield.reg32 | |
1246 | || t.bitfield.reg64); | |
1247 | ||
40fb9820 L |
1248 | case imm: |
1249 | return (t.bitfield.imm8 | |
1250 | || t.bitfield.imm8s | |
1251 | || t.bitfield.imm16 | |
1252 | || t.bitfield.imm32 | |
1253 | || t.bitfield.imm32s | |
1254 | || t.bitfield.imm64); | |
1255 | ||
1256 | case disp: | |
1257 | return (t.bitfield.disp8 | |
1258 | || t.bitfield.disp16 | |
1259 | || t.bitfield.disp32 | |
1260 | || t.bitfield.disp32s | |
1261 | || t.bitfield.disp64); | |
1262 | ||
1263 | case anymem: | |
1264 | return (t.bitfield.disp8 | |
1265 | || t.bitfield.disp16 | |
1266 | || t.bitfield.disp32 | |
1267 | || t.bitfield.disp32s | |
1268 | || t.bitfield.disp64 | |
1269 | || t.bitfield.baseindex); | |
1270 | ||
1271 | default: | |
1272 | abort (); | |
1273 | } | |
1274 | } | |
1275 | ||
5c07affc L |
1276 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on |
1277 | operand J for instruction template T. */ | |
1278 | ||
1279 | static INLINE int | |
1280 | match_reg_size (const template *t, unsigned int j) | |
1281 | { | |
1282 | return !((i.types[j].bitfield.byte | |
1283 | && !t->operand_types[j].bitfield.byte) | |
1284 | || (i.types[j].bitfield.word | |
1285 | && !t->operand_types[j].bitfield.word) | |
1286 | || (i.types[j].bitfield.dword | |
1287 | && !t->operand_types[j].bitfield.dword) | |
1288 | || (i.types[j].bitfield.qword | |
1289 | && !t->operand_types[j].bitfield.qword)); | |
1290 | } | |
1291 | ||
1292 | /* Return 1 if there is no conflict in any size on operand J for | |
1293 | instruction template T. */ | |
1294 | ||
1295 | static INLINE int | |
1296 | match_mem_size (const template *t, unsigned int j) | |
1297 | { | |
1298 | return (match_reg_size (t, j) | |
1299 | && !((i.types[j].bitfield.unspecified | |
1300 | && !t->operand_types[j].bitfield.unspecified) | |
1301 | || (i.types[j].bitfield.fword | |
1302 | && !t->operand_types[j].bitfield.fword) | |
1303 | || (i.types[j].bitfield.tbyte | |
1304 | && !t->operand_types[j].bitfield.tbyte) | |
1305 | || (i.types[j].bitfield.xmmword | |
1306 | && !t->operand_types[j].bitfield.xmmword))); | |
1307 | } | |
1308 | ||
1309 | /* Return 1 if there is no size conflict on any operands for | |
1310 | instruction template T. */ | |
1311 | ||
1312 | static INLINE int | |
1313 | operand_size_match (const template *t) | |
1314 | { | |
1315 | unsigned int j; | |
1316 | int match = 1; | |
1317 | ||
1318 | /* Don't check jump instructions. */ | |
1319 | if (t->opcode_modifier.jump | |
1320 | || t->opcode_modifier.jumpbyte | |
1321 | || t->opcode_modifier.jumpdword | |
1322 | || t->opcode_modifier.jumpintersegment) | |
1323 | return match; | |
1324 | ||
1325 | /* Check memory and accumulator operand size. */ | |
1326 | for (j = 0; j < i.operands; j++) | |
1327 | { | |
1328 | if (t->operand_types[j].bitfield.anysize) | |
1329 | continue; | |
1330 | ||
1331 | if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j)) | |
1332 | { | |
1333 | match = 0; | |
1334 | break; | |
1335 | } | |
1336 | ||
1337 | if (i.types[j].bitfield.mem && !match_mem_size (t, j)) | |
1338 | { | |
1339 | match = 0; | |
1340 | break; | |
1341 | } | |
1342 | } | |
1343 | ||
1344 | if (match | |
1345 | || (!t->opcode_modifier.d && !t->opcode_modifier.floatd)) | |
1346 | return match; | |
1347 | ||
1348 | /* Check reverse. */ | |
1349 | assert (i.operands == 2); | |
1350 | ||
1351 | match = 1; | |
1352 | for (j = 0; j < 2; j++) | |
1353 | { | |
1354 | if (t->operand_types[j].bitfield.acc | |
1355 | && !match_reg_size (t, j ? 0 : 1)) | |
1356 | { | |
1357 | match = 0; | |
1358 | break; | |
1359 | } | |
1360 | ||
1361 | if (i.types[j].bitfield.mem | |
1362 | && !match_mem_size (t, j ? 0 : 1)) | |
1363 | { | |
1364 | match = 0; | |
1365 | break; | |
1366 | } | |
1367 | } | |
1368 | ||
1369 | return match; | |
1370 | } | |
1371 | ||
c6fb90c8 | 1372 | static INLINE int |
40fb9820 L |
1373 | operand_type_match (i386_operand_type overlap, |
1374 | i386_operand_type given) | |
1375 | { | |
1376 | i386_operand_type temp = overlap; | |
1377 | ||
1378 | temp.bitfield.jumpabsolute = 0; | |
7d5e4556 | 1379 | temp.bitfield.unspecified = 0; |
5c07affc L |
1380 | temp.bitfield.byte = 0; |
1381 | temp.bitfield.word = 0; | |
1382 | temp.bitfield.dword = 0; | |
1383 | temp.bitfield.fword = 0; | |
1384 | temp.bitfield.qword = 0; | |
1385 | temp.bitfield.tbyte = 0; | |
1386 | temp.bitfield.xmmword = 0; | |
c6fb90c8 | 1387 | if (UINTS_ALL_ZERO (temp)) |
40fb9820 L |
1388 | return 0; |
1389 | ||
1390 | return (given.bitfield.baseindex == overlap.bitfield.baseindex | |
1391 | && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute); | |
1392 | } | |
1393 | ||
7d5e4556 | 1394 | /* If given types g0 and g1 are registers they must be of the same type |
40fb9820 L |
1395 | unless the expected operand type register overlap is null. |
1396 | Note that Acc in a template matches every size of reg. */ | |
1397 | ||
c6fb90c8 | 1398 | static INLINE int |
40fb9820 L |
1399 | operand_type_register_match (i386_operand_type m0, |
1400 | i386_operand_type g0, | |
1401 | i386_operand_type t0, | |
1402 | i386_operand_type m1, | |
1403 | i386_operand_type g1, | |
1404 | i386_operand_type t1) | |
1405 | { | |
1406 | if (!operand_type_check (g0, reg)) | |
1407 | return 1; | |
1408 | ||
1409 | if (!operand_type_check (g1, reg)) | |
1410 | return 1; | |
1411 | ||
1412 | if (g0.bitfield.reg8 == g1.bitfield.reg8 | |
1413 | && g0.bitfield.reg16 == g1.bitfield.reg16 | |
1414 | && g0.bitfield.reg32 == g1.bitfield.reg32 | |
1415 | && g0.bitfield.reg64 == g1.bitfield.reg64) | |
1416 | return 1; | |
1417 | ||
1418 | if (m0.bitfield.acc) | |
1419 | { | |
1420 | t0.bitfield.reg8 = 1; | |
1421 | t0.bitfield.reg16 = 1; | |
1422 | t0.bitfield.reg32 = 1; | |
1423 | t0.bitfield.reg64 = 1; | |
1424 | } | |
1425 | ||
1426 | if (m1.bitfield.acc) | |
1427 | { | |
1428 | t1.bitfield.reg8 = 1; | |
1429 | t1.bitfield.reg16 = 1; | |
1430 | t1.bitfield.reg32 = 1; | |
1431 | t1.bitfield.reg64 = 1; | |
1432 | } | |
1433 | ||
1434 | return (!(t0.bitfield.reg8 & t1.bitfield.reg8) | |
1435 | && !(t0.bitfield.reg16 & t1.bitfield.reg16) | |
1436 | && !(t0.bitfield.reg32 & t1.bitfield.reg32) | |
1437 | && !(t0.bitfield.reg64 & t1.bitfield.reg64)); | |
1438 | } | |
1439 | ||
252b5132 | 1440 | static INLINE unsigned int |
40fb9820 | 1441 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 1442 | { |
40fb9820 L |
1443 | if (t.bitfield.disp8) |
1444 | return 1; | |
1445 | else if (t.bitfield.disp16 | |
1446 | || t.bitfield.disp32 | |
1447 | || t.bitfield.disp32s) | |
1448 | return 2; | |
1449 | else | |
1450 | return 0; | |
252b5132 RH |
1451 | } |
1452 | ||
1453 | static INLINE int | |
e3bb37b5 | 1454 | fits_in_signed_byte (offsetT num) |
252b5132 RH |
1455 | { |
1456 | return (num >= -128) && (num <= 127); | |
47926f60 | 1457 | } |
252b5132 RH |
1458 | |
1459 | static INLINE int | |
e3bb37b5 | 1460 | fits_in_unsigned_byte (offsetT num) |
252b5132 RH |
1461 | { |
1462 | return (num & 0xff) == num; | |
47926f60 | 1463 | } |
252b5132 RH |
1464 | |
1465 | static INLINE int | |
e3bb37b5 | 1466 | fits_in_unsigned_word (offsetT num) |
252b5132 RH |
1467 | { |
1468 | return (num & 0xffff) == num; | |
47926f60 | 1469 | } |
252b5132 RH |
1470 | |
1471 | static INLINE int | |
e3bb37b5 | 1472 | fits_in_signed_word (offsetT num) |
252b5132 RH |
1473 | { |
1474 | return (-32768 <= num) && (num <= 32767); | |
47926f60 | 1475 | } |
2a962e6d | 1476 | |
3e73aa7c | 1477 | static INLINE int |
e3bb37b5 | 1478 | fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
1479 | { |
1480 | #ifndef BFD64 | |
1481 | return 1; | |
1482 | #else | |
1483 | return (!(((offsetT) -1 << 31) & num) | |
1484 | || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31)); | |
1485 | #endif | |
1486 | } /* fits_in_signed_long() */ | |
2a962e6d | 1487 | |
3e73aa7c | 1488 | static INLINE int |
e3bb37b5 | 1489 | fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
1490 | { |
1491 | #ifndef BFD64 | |
1492 | return 1; | |
1493 | #else | |
1494 | return (num & (((offsetT) 2 << 31) - 1)) == num; | |
1495 | #endif | |
1496 | } /* fits_in_unsigned_long() */ | |
252b5132 | 1497 | |
40fb9820 | 1498 | static i386_operand_type |
e3bb37b5 | 1499 | smallest_imm_type (offsetT num) |
252b5132 | 1500 | { |
40fb9820 L |
1501 | i386_operand_type t; |
1502 | ||
c6fb90c8 | 1503 | UINTS_CLEAR (t); |
40fb9820 L |
1504 | t.bitfield.imm64 = 1; |
1505 | ||
1506 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
1507 | { |
1508 | /* This code is disabled on the 486 because all the Imm1 forms | |
1509 | in the opcode table are slower on the i486. They're the | |
1510 | versions with the implicitly specified single-position | |
1511 | displacement, which has another syntax if you really want to | |
1512 | use that form. */ | |
40fb9820 L |
1513 | t.bitfield.imm1 = 1; |
1514 | t.bitfield.imm8 = 1; | |
1515 | t.bitfield.imm8s = 1; | |
1516 | t.bitfield.imm16 = 1; | |
1517 | t.bitfield.imm32 = 1; | |
1518 | t.bitfield.imm32s = 1; | |
1519 | } | |
1520 | else if (fits_in_signed_byte (num)) | |
1521 | { | |
1522 | t.bitfield.imm8 = 1; | |
1523 | t.bitfield.imm8s = 1; | |
1524 | t.bitfield.imm16 = 1; | |
1525 | t.bitfield.imm32 = 1; | |
1526 | t.bitfield.imm32s = 1; | |
1527 | } | |
1528 | else if (fits_in_unsigned_byte (num)) | |
1529 | { | |
1530 | t.bitfield.imm8 = 1; | |
1531 | t.bitfield.imm16 = 1; | |
1532 | t.bitfield.imm32 = 1; | |
1533 | t.bitfield.imm32s = 1; | |
1534 | } | |
1535 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
1536 | { | |
1537 | t.bitfield.imm16 = 1; | |
1538 | t.bitfield.imm32 = 1; | |
1539 | t.bitfield.imm32s = 1; | |
1540 | } | |
1541 | else if (fits_in_signed_long (num)) | |
1542 | { | |
1543 | t.bitfield.imm32 = 1; | |
1544 | t.bitfield.imm32s = 1; | |
1545 | } | |
1546 | else if (fits_in_unsigned_long (num)) | |
1547 | t.bitfield.imm32 = 1; | |
1548 | ||
1549 | return t; | |
47926f60 | 1550 | } |
252b5132 | 1551 | |
847f7ad4 | 1552 | static offsetT |
e3bb37b5 | 1553 | offset_in_range (offsetT val, int size) |
847f7ad4 | 1554 | { |
508866be | 1555 | addressT mask; |
ba2adb93 | 1556 | |
847f7ad4 AM |
1557 | switch (size) |
1558 | { | |
508866be L |
1559 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
1560 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 1561 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
1562 | #ifdef BFD64 |
1563 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
1564 | #endif | |
47926f60 | 1565 | default: abort (); |
847f7ad4 AM |
1566 | } |
1567 | ||
ba2adb93 | 1568 | /* If BFD64, sign extend val. */ |
3e73aa7c JH |
1569 | if (!use_rela_relocations) |
1570 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) | |
1571 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
ba2adb93 | 1572 | |
47926f60 | 1573 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
1574 | { |
1575 | char buf1[40], buf2[40]; | |
1576 | ||
1577 | sprint_value (buf1, val); | |
1578 | sprint_value (buf2, val & mask); | |
1579 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
1580 | } | |
1581 | return val & mask; | |
1582 | } | |
1583 | ||
252b5132 RH |
1584 | /* Returns 0 if attempting to add a prefix where one from the same |
1585 | class already exists, 1 if non rep/repne added, 2 if rep/repne | |
1586 | added. */ | |
1587 | static int | |
e3bb37b5 | 1588 | add_prefix (unsigned int prefix) |
252b5132 RH |
1589 | { |
1590 | int ret = 1; | |
b1905489 | 1591 | unsigned int q; |
252b5132 | 1592 | |
29b0f896 AM |
1593 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
1594 | && flag_code == CODE_64BIT) | |
b1905489 | 1595 | { |
161a04f6 L |
1596 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
1597 | || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B)) | |
1598 | && (prefix & (REX_R | REX_X | REX_B)))) | |
b1905489 JB |
1599 | ret = 0; |
1600 | q = REX_PREFIX; | |
1601 | } | |
3e73aa7c | 1602 | else |
b1905489 JB |
1603 | { |
1604 | switch (prefix) | |
1605 | { | |
1606 | default: | |
1607 | abort (); | |
1608 | ||
1609 | case CS_PREFIX_OPCODE: | |
1610 | case DS_PREFIX_OPCODE: | |
1611 | case ES_PREFIX_OPCODE: | |
1612 | case FS_PREFIX_OPCODE: | |
1613 | case GS_PREFIX_OPCODE: | |
1614 | case SS_PREFIX_OPCODE: | |
1615 | q = SEG_PREFIX; | |
1616 | break; | |
1617 | ||
1618 | case REPNE_PREFIX_OPCODE: | |
1619 | case REPE_PREFIX_OPCODE: | |
1620 | ret = 2; | |
1621 | /* fall thru */ | |
1622 | case LOCK_PREFIX_OPCODE: | |
1623 | q = LOCKREP_PREFIX; | |
1624 | break; | |
1625 | ||
1626 | case FWAIT_OPCODE: | |
1627 | q = WAIT_PREFIX; | |
1628 | break; | |
1629 | ||
1630 | case ADDR_PREFIX_OPCODE: | |
1631 | q = ADDR_PREFIX; | |
1632 | break; | |
1633 | ||
1634 | case DATA_PREFIX_OPCODE: | |
1635 | q = DATA_PREFIX; | |
1636 | break; | |
1637 | } | |
1638 | if (i.prefix[q] != 0) | |
1639 | ret = 0; | |
1640 | } | |
252b5132 | 1641 | |
b1905489 | 1642 | if (ret) |
252b5132 | 1643 | { |
b1905489 JB |
1644 | if (!i.prefix[q]) |
1645 | ++i.prefixes; | |
1646 | i.prefix[q] |= prefix; | |
252b5132 | 1647 | } |
b1905489 JB |
1648 | else |
1649 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 1650 | |
252b5132 RH |
1651 | return ret; |
1652 | } | |
1653 | ||
1654 | static void | |
e3bb37b5 | 1655 | set_code_flag (int value) |
eecb386c | 1656 | { |
3e73aa7c | 1657 | flag_code = value; |
40fb9820 L |
1658 | if (flag_code == CODE_64BIT) |
1659 | { | |
1660 | cpu_arch_flags.bitfield.cpu64 = 1; | |
1661 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
1662 | } |
1663 | else | |
1664 | { | |
1665 | cpu_arch_flags.bitfield.cpu64 = 0; | |
1666 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
1667 | } |
1668 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c JH |
1669 | { |
1670 | as_bad (_("64bit mode not supported on this CPU.")); | |
1671 | } | |
40fb9820 | 1672 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c JH |
1673 | { |
1674 | as_bad (_("32bit mode not supported on this CPU.")); | |
1675 | } | |
eecb386c AM |
1676 | stackop_size = '\0'; |
1677 | } | |
1678 | ||
1679 | static void | |
e3bb37b5 | 1680 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 1681 | { |
3e73aa7c | 1682 | flag_code = new_code_flag; |
40fb9820 L |
1683 | if (flag_code != CODE_16BIT) |
1684 | abort (); | |
1685 | cpu_arch_flags.bitfield.cpu64 = 0; | |
1686 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 1687 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
1688 | } |
1689 | ||
1690 | static void | |
e3bb37b5 | 1691 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
1692 | { |
1693 | /* Find out if register prefixing is specified. */ | |
1694 | int ask_naked_reg = 0; | |
1695 | ||
1696 | SKIP_WHITESPACE (); | |
29b0f896 | 1697 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 RH |
1698 | { |
1699 | char *string = input_line_pointer; | |
1700 | int e = get_symbol_end (); | |
1701 | ||
47926f60 | 1702 | if (strcmp (string, "prefix") == 0) |
252b5132 | 1703 | ask_naked_reg = 1; |
47926f60 | 1704 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
1705 | ask_naked_reg = -1; |
1706 | else | |
d0b47220 | 1707 | as_bad (_("bad argument to syntax directive.")); |
252b5132 RH |
1708 | *input_line_pointer = e; |
1709 | } | |
1710 | demand_empty_rest_of_line (); | |
c3332e24 | 1711 | |
252b5132 RH |
1712 | intel_syntax = syntax_flag; |
1713 | ||
1714 | if (ask_naked_reg == 0) | |
f86103b7 AM |
1715 | allow_naked_reg = (intel_syntax |
1716 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
1717 | else |
1718 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 1719 | |
e4a3b5a4 | 1720 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 1721 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 1722 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
1723 | } |
1724 | ||
1efbbeb4 L |
1725 | static void |
1726 | set_intel_mnemonic (int mnemonic_flag) | |
1727 | { | |
e1d4d893 | 1728 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
1729 | } |
1730 | ||
db51cc60 L |
1731 | static void |
1732 | set_allow_index_reg (int flag) | |
1733 | { | |
1734 | allow_index_reg = flag; | |
1735 | } | |
1736 | ||
e413e4e9 | 1737 | static void |
e3bb37b5 | 1738 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 1739 | { |
47926f60 | 1740 | SKIP_WHITESPACE (); |
e413e4e9 | 1741 | |
29b0f896 | 1742 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 AM |
1743 | { |
1744 | char *string = input_line_pointer; | |
1745 | int e = get_symbol_end (); | |
9103f4f4 | 1746 | unsigned int i; |
40fb9820 | 1747 | i386_cpu_flags flags; |
e413e4e9 | 1748 | |
9103f4f4 | 1749 | for (i = 0; i < ARRAY_SIZE (cpu_arch); i++) |
e413e4e9 AM |
1750 | { |
1751 | if (strcmp (string, cpu_arch[i].name) == 0) | |
1752 | { | |
5c6af06e JB |
1753 | if (*string != '.') |
1754 | { | |
1755 | cpu_arch_name = cpu_arch[i].name; | |
1756 | cpu_sub_arch_name = NULL; | |
40fb9820 L |
1757 | cpu_arch_flags = cpu_arch[i].flags; |
1758 | if (flag_code == CODE_64BIT) | |
1759 | { | |
1760 | cpu_arch_flags.bitfield.cpu64 = 1; | |
1761 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
1762 | } | |
1763 | else | |
1764 | { | |
1765 | cpu_arch_flags.bitfield.cpu64 = 0; | |
1766 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
1767 | } | |
ccc9c027 | 1768 | cpu_arch_isa = cpu_arch[i].type; |
9103f4f4 | 1769 | cpu_arch_isa_flags = cpu_arch[i].flags; |
ccc9c027 L |
1770 | if (!cpu_arch_tune_set) |
1771 | { | |
1772 | cpu_arch_tune = cpu_arch_isa; | |
1773 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
1774 | } | |
5c6af06e JB |
1775 | break; |
1776 | } | |
40fb9820 | 1777 | |
c6fb90c8 L |
1778 | flags = cpu_flags_or (cpu_arch_flags, |
1779 | cpu_arch[i].flags); | |
1780 | if (!UINTS_EQUAL (flags, cpu_arch_flags)) | |
5c6af06e | 1781 | { |
6305a203 L |
1782 | if (cpu_sub_arch_name) |
1783 | { | |
1784 | char *name = cpu_sub_arch_name; | |
1785 | cpu_sub_arch_name = concat (name, | |
1786 | cpu_arch[i].name, | |
1787 | NULL); | |
1788 | free (name); | |
1789 | } | |
1790 | else | |
1791 | cpu_sub_arch_name = xstrdup (cpu_arch[i].name); | |
40fb9820 | 1792 | cpu_arch_flags = flags; |
5c6af06e JB |
1793 | } |
1794 | *input_line_pointer = e; | |
1795 | demand_empty_rest_of_line (); | |
1796 | return; | |
e413e4e9 AM |
1797 | } |
1798 | } | |
9103f4f4 | 1799 | if (i >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
1800 | as_bad (_("no such architecture: `%s'"), string); |
1801 | ||
1802 | *input_line_pointer = e; | |
1803 | } | |
1804 | else | |
1805 | as_bad (_("missing cpu architecture")); | |
1806 | ||
fddf5b5b AM |
1807 | no_cond_jump_promotion = 0; |
1808 | if (*input_line_pointer == ',' | |
29b0f896 | 1809 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b AM |
1810 | { |
1811 | char *string = ++input_line_pointer; | |
1812 | int e = get_symbol_end (); | |
1813 | ||
1814 | if (strcmp (string, "nojumps") == 0) | |
1815 | no_cond_jump_promotion = 1; | |
1816 | else if (strcmp (string, "jumps") == 0) | |
1817 | ; | |
1818 | else | |
1819 | as_bad (_("no such architecture modifier: `%s'"), string); | |
1820 | ||
1821 | *input_line_pointer = e; | |
1822 | } | |
1823 | ||
e413e4e9 AM |
1824 | demand_empty_rest_of_line (); |
1825 | } | |
1826 | ||
b9d79e03 JH |
1827 | unsigned long |
1828 | i386_mach () | |
1829 | { | |
1830 | if (!strcmp (default_arch, "x86_64")) | |
1831 | return bfd_mach_x86_64; | |
1832 | else if (!strcmp (default_arch, "i386")) | |
1833 | return bfd_mach_i386_i386; | |
1834 | else | |
1835 | as_fatal (_("Unknown architecture")); | |
1836 | } | |
b9d79e03 | 1837 | \f |
252b5132 RH |
1838 | void |
1839 | md_begin () | |
1840 | { | |
1841 | const char *hash_err; | |
1842 | ||
47926f60 | 1843 | /* Initialize op_hash hash table. */ |
252b5132 RH |
1844 | op_hash = hash_new (); |
1845 | ||
1846 | { | |
29b0f896 AM |
1847 | const template *optab; |
1848 | templates *core_optab; | |
252b5132 | 1849 | |
47926f60 KH |
1850 | /* Setup for loop. */ |
1851 | optab = i386_optab; | |
252b5132 RH |
1852 | core_optab = (templates *) xmalloc (sizeof (templates)); |
1853 | core_optab->start = optab; | |
1854 | ||
1855 | while (1) | |
1856 | { | |
1857 | ++optab; | |
1858 | if (optab->name == NULL | |
1859 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
1860 | { | |
1861 | /* different name --> ship out current template list; | |
47926f60 | 1862 | add to hash table; & begin anew. */ |
252b5132 RH |
1863 | core_optab->end = optab; |
1864 | hash_err = hash_insert (op_hash, | |
1865 | (optab - 1)->name, | |
1866 | (PTR) core_optab); | |
1867 | if (hash_err) | |
1868 | { | |
252b5132 RH |
1869 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
1870 | (optab - 1)->name, | |
1871 | hash_err); | |
1872 | } | |
1873 | if (optab->name == NULL) | |
1874 | break; | |
1875 | core_optab = (templates *) xmalloc (sizeof (templates)); | |
1876 | core_optab->start = optab; | |
1877 | } | |
1878 | } | |
1879 | } | |
1880 | ||
47926f60 | 1881 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
1882 | reg_hash = hash_new (); |
1883 | { | |
29b0f896 | 1884 | const reg_entry *regtab; |
c3fe08fa | 1885 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 1886 | |
c3fe08fa | 1887 | for (regtab = i386_regtab; regtab_size--; regtab++) |
252b5132 RH |
1888 | { |
1889 | hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab); | |
1890 | if (hash_err) | |
3e73aa7c JH |
1891 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
1892 | regtab->reg_name, | |
1893 | hash_err); | |
252b5132 RH |
1894 | } |
1895 | } | |
1896 | ||
47926f60 | 1897 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 1898 | { |
29b0f896 AM |
1899 | int c; |
1900 | char *p; | |
252b5132 RH |
1901 | |
1902 | for (c = 0; c < 256; c++) | |
1903 | { | |
3882b010 | 1904 | if (ISDIGIT (c)) |
252b5132 RH |
1905 | { |
1906 | digit_chars[c] = c; | |
1907 | mnemonic_chars[c] = c; | |
1908 | register_chars[c] = c; | |
1909 | operand_chars[c] = c; | |
1910 | } | |
3882b010 | 1911 | else if (ISLOWER (c)) |
252b5132 RH |
1912 | { |
1913 | mnemonic_chars[c] = c; | |
1914 | register_chars[c] = c; | |
1915 | operand_chars[c] = c; | |
1916 | } | |
3882b010 | 1917 | else if (ISUPPER (c)) |
252b5132 | 1918 | { |
3882b010 | 1919 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
1920 | register_chars[c] = mnemonic_chars[c]; |
1921 | operand_chars[c] = c; | |
1922 | } | |
1923 | ||
3882b010 | 1924 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
1925 | identifier_chars[c] = c; |
1926 | else if (c >= 128) | |
1927 | { | |
1928 | identifier_chars[c] = c; | |
1929 | operand_chars[c] = c; | |
1930 | } | |
1931 | } | |
1932 | ||
1933 | #ifdef LEX_AT | |
1934 | identifier_chars['@'] = '@'; | |
32137342 NC |
1935 | #endif |
1936 | #ifdef LEX_QM | |
1937 | identifier_chars['?'] = '?'; | |
1938 | operand_chars['?'] = '?'; | |
252b5132 | 1939 | #endif |
252b5132 | 1940 | digit_chars['-'] = '-'; |
791fe849 | 1941 | mnemonic_chars['-'] = '-'; |
0003779b | 1942 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
1943 | identifier_chars['_'] = '_'; |
1944 | identifier_chars['.'] = '.'; | |
1945 | ||
1946 | for (p = operand_special_chars; *p != '\0'; p++) | |
1947 | operand_chars[(unsigned char) *p] = *p; | |
1948 | } | |
1949 | ||
1950 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 1951 | if (IS_ELF) |
252b5132 RH |
1952 | { |
1953 | record_alignment (text_section, 2); | |
1954 | record_alignment (data_section, 2); | |
1955 | record_alignment (bss_section, 2); | |
1956 | } | |
1957 | #endif | |
a4447b93 RH |
1958 | |
1959 | if (flag_code == CODE_64BIT) | |
1960 | { | |
1961 | x86_dwarf2_return_column = 16; | |
1962 | x86_cie_data_alignment = -8; | |
1963 | } | |
1964 | else | |
1965 | { | |
1966 | x86_dwarf2_return_column = 8; | |
1967 | x86_cie_data_alignment = -4; | |
1968 | } | |
252b5132 RH |
1969 | } |
1970 | ||
1971 | void | |
e3bb37b5 | 1972 | i386_print_statistics (FILE *file) |
252b5132 RH |
1973 | { |
1974 | hash_print_statistics (file, "i386 opcode", op_hash); | |
1975 | hash_print_statistics (file, "i386 register", reg_hash); | |
1976 | } | |
1977 | \f | |
252b5132 RH |
1978 | #ifdef DEBUG386 |
1979 | ||
ce8a8b2f | 1980 | /* Debugging routines for md_assemble. */ |
e3bb37b5 | 1981 | static void pte (template *); |
40fb9820 | 1982 | static void pt (i386_operand_type); |
e3bb37b5 L |
1983 | static void pe (expressionS *); |
1984 | static void ps (symbolS *); | |
252b5132 RH |
1985 | |
1986 | static void | |
e3bb37b5 | 1987 | pi (char *line, i386_insn *x) |
252b5132 | 1988 | { |
09f131f2 | 1989 | unsigned int i; |
252b5132 RH |
1990 | |
1991 | fprintf (stdout, "%s: template ", line); | |
1992 | pte (&x->tm); | |
09f131f2 JH |
1993 | fprintf (stdout, " address: base %s index %s scale %x\n", |
1994 | x->base_reg ? x->base_reg->reg_name : "none", | |
1995 | x->index_reg ? x->index_reg->reg_name : "none", | |
1996 | x->log2_scale_factor); | |
1997 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 1998 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
1999 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
2000 | x->sib.base, x->sib.index, x->sib.scale); | |
2001 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
2002 | (x->rex & REX_W) != 0, |
2003 | (x->rex & REX_R) != 0, | |
2004 | (x->rex & REX_X) != 0, | |
2005 | (x->rex & REX_B) != 0); | |
85f10a01 MM |
2006 | fprintf (stdout, " drex: reg %d rex 0x%x\n", |
2007 | x->drex.reg, x->drex.rex); | |
252b5132 RH |
2008 | for (i = 0; i < x->operands; i++) |
2009 | { | |
2010 | fprintf (stdout, " #%d: ", i + 1); | |
2011 | pt (x->types[i]); | |
2012 | fprintf (stdout, "\n"); | |
40fb9820 L |
2013 | if (x->types[i].bitfield.reg8 |
2014 | || x->types[i].bitfield.reg16 | |
2015 | || x->types[i].bitfield.reg32 | |
2016 | || x->types[i].bitfield.reg64 | |
2017 | || x->types[i].bitfield.regmmx | |
2018 | || x->types[i].bitfield.regxmm | |
2019 | || x->types[i].bitfield.sreg2 | |
2020 | || x->types[i].bitfield.sreg3 | |
2021 | || x->types[i].bitfield.control | |
2022 | || x->types[i].bitfield.debug | |
2023 | || x->types[i].bitfield.test) | |
520dc8e8 | 2024 | fprintf (stdout, "%s\n", x->op[i].regs->reg_name); |
40fb9820 | 2025 | if (operand_type_check (x->types[i], imm)) |
520dc8e8 | 2026 | pe (x->op[i].imms); |
40fb9820 | 2027 | if (operand_type_check (x->types[i], disp)) |
520dc8e8 | 2028 | pe (x->op[i].disps); |
252b5132 RH |
2029 | } |
2030 | } | |
2031 | ||
2032 | static void | |
e3bb37b5 | 2033 | pte (template *t) |
252b5132 | 2034 | { |
09f131f2 | 2035 | unsigned int i; |
252b5132 | 2036 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 2037 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
2038 | if (t->extension_opcode != None) |
2039 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 2040 | if (t->opcode_modifier.d) |
252b5132 | 2041 | fprintf (stdout, "D"); |
40fb9820 | 2042 | if (t->opcode_modifier.w) |
252b5132 RH |
2043 | fprintf (stdout, "W"); |
2044 | fprintf (stdout, "\n"); | |
2045 | for (i = 0; i < t->operands; i++) | |
2046 | { | |
2047 | fprintf (stdout, " #%d type ", i + 1); | |
2048 | pt (t->operand_types[i]); | |
2049 | fprintf (stdout, "\n"); | |
2050 | } | |
2051 | } | |
2052 | ||
2053 | static void | |
e3bb37b5 | 2054 | pe (expressionS *e) |
252b5132 | 2055 | { |
24eab124 | 2056 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
2057 | fprintf (stdout, " add_number %ld (%lx)\n", |
2058 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
2059 | if (e->X_add_symbol) |
2060 | { | |
2061 | fprintf (stdout, " add_symbol "); | |
2062 | ps (e->X_add_symbol); | |
2063 | fprintf (stdout, "\n"); | |
2064 | } | |
2065 | if (e->X_op_symbol) | |
2066 | { | |
2067 | fprintf (stdout, " op_symbol "); | |
2068 | ps (e->X_op_symbol); | |
2069 | fprintf (stdout, "\n"); | |
2070 | } | |
2071 | } | |
2072 | ||
2073 | static void | |
e3bb37b5 | 2074 | ps (symbolS *s) |
252b5132 RH |
2075 | { |
2076 | fprintf (stdout, "%s type %s%s", | |
2077 | S_GET_NAME (s), | |
2078 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
2079 | segment_name (S_GET_SEGMENT (s))); | |
2080 | } | |
2081 | ||
7b81dfbb | 2082 | static struct type_name |
252b5132 | 2083 | { |
40fb9820 L |
2084 | i386_operand_type mask; |
2085 | const char *name; | |
252b5132 | 2086 | } |
7b81dfbb | 2087 | const type_names[] = |
252b5132 | 2088 | { |
40fb9820 L |
2089 | { OPERAND_TYPE_REG8, "r8" }, |
2090 | { OPERAND_TYPE_REG16, "r16" }, | |
2091 | { OPERAND_TYPE_REG32, "r32" }, | |
2092 | { OPERAND_TYPE_REG64, "r64" }, | |
2093 | { OPERAND_TYPE_IMM8, "i8" }, | |
2094 | { OPERAND_TYPE_IMM8, "i8s" }, | |
2095 | { OPERAND_TYPE_IMM16, "i16" }, | |
2096 | { OPERAND_TYPE_IMM32, "i32" }, | |
2097 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
2098 | { OPERAND_TYPE_IMM64, "i64" }, | |
2099 | { OPERAND_TYPE_IMM1, "i1" }, | |
2100 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
2101 | { OPERAND_TYPE_DISP8, "d8" }, | |
2102 | { OPERAND_TYPE_DISP16, "d16" }, | |
2103 | { OPERAND_TYPE_DISP32, "d32" }, | |
2104 | { OPERAND_TYPE_DISP32S, "d32s" }, | |
2105 | { OPERAND_TYPE_DISP64, "d64" }, | |
2106 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, | |
2107 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
2108 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
2109 | { OPERAND_TYPE_TEST, "test reg" }, | |
2110 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
2111 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
2112 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
2113 | { OPERAND_TYPE_SREG2, "SReg2" }, | |
2114 | { OPERAND_TYPE_SREG3, "SReg3" }, | |
2115 | { OPERAND_TYPE_ACC, "Acc" }, | |
2116 | { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" }, | |
2117 | { OPERAND_TYPE_REGMMX, "rMMX" }, | |
2118 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
2119 | { OPERAND_TYPE_ESSEG, "es" }, | |
252b5132 RH |
2120 | }; |
2121 | ||
2122 | static void | |
40fb9820 | 2123 | pt (i386_operand_type t) |
252b5132 | 2124 | { |
40fb9820 | 2125 | unsigned int j; |
c6fb90c8 | 2126 | i386_operand_type a; |
252b5132 | 2127 | |
40fb9820 | 2128 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
2129 | { |
2130 | a = operand_type_and (t, type_names[j].mask); | |
2131 | if (!UINTS_ALL_ZERO (a)) | |
2132 | fprintf (stdout, "%s, ", type_names[j].name); | |
2133 | } | |
252b5132 RH |
2134 | fflush (stdout); |
2135 | } | |
2136 | ||
2137 | #endif /* DEBUG386 */ | |
2138 | \f | |
252b5132 | 2139 | static bfd_reloc_code_real_type |
3956db08 | 2140 | reloc (unsigned int size, |
64e74474 AM |
2141 | int pcrel, |
2142 | int sign, | |
2143 | bfd_reloc_code_real_type other) | |
252b5132 | 2144 | { |
47926f60 | 2145 | if (other != NO_RELOC) |
3956db08 JB |
2146 | { |
2147 | reloc_howto_type *reloc; | |
2148 | ||
2149 | if (size == 8) | |
2150 | switch (other) | |
2151 | { | |
64e74474 AM |
2152 | case BFD_RELOC_X86_64_GOT32: |
2153 | return BFD_RELOC_X86_64_GOT64; | |
2154 | break; | |
2155 | case BFD_RELOC_X86_64_PLTOFF64: | |
2156 | return BFD_RELOC_X86_64_PLTOFF64; | |
2157 | break; | |
2158 | case BFD_RELOC_X86_64_GOTPC32: | |
2159 | other = BFD_RELOC_X86_64_GOTPC64; | |
2160 | break; | |
2161 | case BFD_RELOC_X86_64_GOTPCREL: | |
2162 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
2163 | break; | |
2164 | case BFD_RELOC_X86_64_TPOFF32: | |
2165 | other = BFD_RELOC_X86_64_TPOFF64; | |
2166 | break; | |
2167 | case BFD_RELOC_X86_64_DTPOFF32: | |
2168 | other = BFD_RELOC_X86_64_DTPOFF64; | |
2169 | break; | |
2170 | default: | |
2171 | break; | |
3956db08 | 2172 | } |
e05278af JB |
2173 | |
2174 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ | |
2175 | if (size == 4 && flag_code != CODE_64BIT) | |
2176 | sign = -1; | |
2177 | ||
3956db08 JB |
2178 | reloc = bfd_reloc_type_lookup (stdoutput, other); |
2179 | if (!reloc) | |
2180 | as_bad (_("unknown relocation (%u)"), other); | |
2181 | else if (size != bfd_get_reloc_size (reloc)) | |
2182 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), | |
2183 | bfd_get_reloc_size (reloc), | |
2184 | size); | |
2185 | else if (pcrel && !reloc->pc_relative) | |
2186 | as_bad (_("non-pc-relative relocation for pc-relative field")); | |
2187 | else if ((reloc->complain_on_overflow == complain_overflow_signed | |
2188 | && !sign) | |
2189 | || (reloc->complain_on_overflow == complain_overflow_unsigned | |
64e74474 | 2190 | && sign > 0)) |
3956db08 JB |
2191 | as_bad (_("relocated field and relocation type differ in signedness")); |
2192 | else | |
2193 | return other; | |
2194 | return NO_RELOC; | |
2195 | } | |
252b5132 RH |
2196 | |
2197 | if (pcrel) | |
2198 | { | |
3e73aa7c | 2199 | if (!sign) |
3956db08 | 2200 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
2201 | switch (size) |
2202 | { | |
2203 | case 1: return BFD_RELOC_8_PCREL; | |
2204 | case 2: return BFD_RELOC_16_PCREL; | |
2205 | case 4: return BFD_RELOC_32_PCREL; | |
d6ab8113 | 2206 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 2207 | } |
3956db08 | 2208 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
2209 | } |
2210 | else | |
2211 | { | |
3956db08 | 2212 | if (sign > 0) |
e5cb08ac | 2213 | switch (size) |
3e73aa7c JH |
2214 | { |
2215 | case 4: return BFD_RELOC_X86_64_32S; | |
2216 | } | |
2217 | else | |
2218 | switch (size) | |
2219 | { | |
2220 | case 1: return BFD_RELOC_8; | |
2221 | case 2: return BFD_RELOC_16; | |
2222 | case 4: return BFD_RELOC_32; | |
2223 | case 8: return BFD_RELOC_64; | |
2224 | } | |
3956db08 JB |
2225 | as_bad (_("cannot do %s %u byte relocation"), |
2226 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
2227 | } |
2228 | ||
bfb32b52 | 2229 | abort (); |
252b5132 RH |
2230 | return BFD_RELOC_NONE; |
2231 | } | |
2232 | ||
47926f60 KH |
2233 | /* Here we decide which fixups can be adjusted to make them relative to |
2234 | the beginning of the section instead of the symbol. Basically we need | |
2235 | to make sure that the dynamic relocations are done correctly, so in | |
2236 | some cases we force the original symbol to be used. */ | |
2237 | ||
252b5132 | 2238 | int |
e3bb37b5 | 2239 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 2240 | { |
6d249963 | 2241 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 2242 | if (!IS_ELF) |
31312f95 AM |
2243 | return 1; |
2244 | ||
a161fe53 AM |
2245 | /* Don't adjust pc-relative references to merge sections in 64-bit |
2246 | mode. */ | |
2247 | if (use_rela_relocations | |
2248 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
2249 | && fixP->fx_pcrel) | |
252b5132 | 2250 | return 0; |
31312f95 | 2251 | |
8d01d9a9 AJ |
2252 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
2253 | and changed later by validate_fix. */ | |
2254 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
2255 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
2256 | return 0; | |
2257 | ||
ce8a8b2f | 2258 | /* adjust_reloc_syms doesn't know about the GOT. */ |
252b5132 RH |
2259 | if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF |
2260 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 | |
2261 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
13ae64f3 JJ |
2262 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
2263 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
2264 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
2265 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
2266 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
2267 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
2268 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
2269 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
2270 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
2271 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c JH |
2272 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
2273 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
80b3ee89 | 2274 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
bffbf940 JJ |
2275 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
2276 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
2277 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 2278 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
2279 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
2280 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
2281 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
2282 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
2283 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
2284 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
2285 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
2286 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
2287 | return 0; | |
31312f95 | 2288 | #endif |
252b5132 RH |
2289 | return 1; |
2290 | } | |
252b5132 | 2291 | |
b4cac588 | 2292 | static int |
e3bb37b5 | 2293 | intel_float_operand (const char *mnemonic) |
252b5132 | 2294 | { |
9306ca4a JB |
2295 | /* Note that the value returned is meaningful only for opcodes with (memory) |
2296 | operands, hence the code here is free to improperly handle opcodes that | |
2297 | have no operands (for better performance and smaller code). */ | |
2298 | ||
2299 | if (mnemonic[0] != 'f') | |
2300 | return 0; /* non-math */ | |
2301 | ||
2302 | switch (mnemonic[1]) | |
2303 | { | |
2304 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
2305 | the fs segment override prefix not currently handled because no | |
2306 | call path can make opcodes without operands get here */ | |
2307 | case 'i': | |
2308 | return 2 /* integer op */; | |
2309 | case 'l': | |
2310 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
2311 | return 3; /* fldcw/fldenv */ | |
2312 | break; | |
2313 | case 'n': | |
2314 | if (mnemonic[2] != 'o' /* fnop */) | |
2315 | return 3; /* non-waiting control op */ | |
2316 | break; | |
2317 | case 'r': | |
2318 | if (mnemonic[2] == 's') | |
2319 | return 3; /* frstor/frstpm */ | |
2320 | break; | |
2321 | case 's': | |
2322 | if (mnemonic[2] == 'a') | |
2323 | return 3; /* fsave */ | |
2324 | if (mnemonic[2] == 't') | |
2325 | { | |
2326 | switch (mnemonic[3]) | |
2327 | { | |
2328 | case 'c': /* fstcw */ | |
2329 | case 'd': /* fstdw */ | |
2330 | case 'e': /* fstenv */ | |
2331 | case 's': /* fsts[gw] */ | |
2332 | return 3; | |
2333 | } | |
2334 | } | |
2335 | break; | |
2336 | case 'x': | |
2337 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
2338 | return 0; /* fxsave/fxrstor are not really math ops */ | |
2339 | break; | |
2340 | } | |
252b5132 | 2341 | |
9306ca4a | 2342 | return 1; |
252b5132 RH |
2343 | } |
2344 | ||
2345 | /* This is the guts of the machine-dependent assembler. LINE points to a | |
2346 | machine dependent instruction. This function is supposed to emit | |
2347 | the frags/bytes it assembles to. */ | |
2348 | ||
2349 | void | |
2350 | md_assemble (line) | |
2351 | char *line; | |
2352 | { | |
40fb9820 | 2353 | unsigned int j; |
252b5132 RH |
2354 | char mnemonic[MAX_MNEM_SIZE]; |
2355 | ||
47926f60 | 2356 | /* Initialize globals. */ |
252b5132 RH |
2357 | memset (&i, '\0', sizeof (i)); |
2358 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 2359 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
2360 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
2361 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 2362 | save_stack_p = save_stack; |
252b5132 RH |
2363 | |
2364 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
2365 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 2366 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 2367 | |
29b0f896 AM |
2368 | line = parse_insn (line, mnemonic); |
2369 | if (line == NULL) | |
2370 | return; | |
252b5132 | 2371 | |
29b0f896 AM |
2372 | line = parse_operands (line, mnemonic); |
2373 | if (line == NULL) | |
2374 | return; | |
252b5132 | 2375 | |
29b0f896 AM |
2376 | /* Now we've parsed the mnemonic into a set of templates, and have the |
2377 | operands at hand. */ | |
2378 | ||
2379 | /* All intel opcodes have reversed operands except for "bound" and | |
2380 | "enter". We also don't reverse intersegment "jmp" and "call" | |
2381 | instructions with 2 immediate operands so that the immediate segment | |
050dfa73 | 2382 | precedes the offset, as it does when in AT&T mode. */ |
4d456e3d L |
2383 | if (intel_syntax |
2384 | && i.operands > 1 | |
29b0f896 | 2385 | && (strcmp (mnemonic, "bound") != 0) |
30123838 | 2386 | && (strcmp (mnemonic, "invlpga") != 0) |
40fb9820 L |
2387 | && !(operand_type_check (i.types[0], imm) |
2388 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
2389 | swap_operands (); |
2390 | ||
ec56d5c0 JB |
2391 | /* The order of the immediates should be reversed |
2392 | for 2 immediates extrq and insertq instructions */ | |
2393 | if (i.imm_operands == 2 | |
2394 | && (strcmp (mnemonic, "extrq") == 0 | |
2395 | || strcmp (mnemonic, "insertq") == 0)) | |
2396 | swap_2_operands (0, 1); | |
2397 | ||
29b0f896 AM |
2398 | if (i.imm_operands) |
2399 | optimize_imm (); | |
2400 | ||
b300c311 L |
2401 | /* Don't optimize displacement for movabs since it only takes 64bit |
2402 | displacement. */ | |
2403 | if (i.disp_operands | |
2404 | && (flag_code != CODE_64BIT | |
2405 | || strcmp (mnemonic, "movabs") != 0)) | |
29b0f896 AM |
2406 | optimize_disp (); |
2407 | ||
2408 | /* Next, we find a template that matches the given insn, | |
2409 | making sure the overlap of the given operands types is consistent | |
2410 | with the template operand types. */ | |
252b5132 | 2411 | |
29b0f896 AM |
2412 | if (!match_template ()) |
2413 | return; | |
252b5132 | 2414 | |
321fd21e L |
2415 | /* Zap movzx and movsx suffix. The suffix has been set from |
2416 | "word ptr" or "byte ptr" on the source operand in Intel syntax | |
2417 | or extracted from mnemonic in AT&T syntax. But we'll use | |
2418 | the destination register to choose the suffix for encoding. */ | |
2419 | if ((i.tm.base_opcode & ~9) == 0x0fb6) | |
cd61ebfe | 2420 | { |
321fd21e L |
2421 | /* In Intel syntax, there must be a suffix. In AT&T syntax, if |
2422 | there is no suffix, the default will be byte extension. */ | |
2423 | if (i.reg_operands != 2 | |
2424 | && !i.suffix | |
2425 | && intel_syntax) | |
2426 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); | |
2427 | ||
2428 | i.suffix = 0; | |
cd61ebfe | 2429 | } |
24eab124 | 2430 | |
40fb9820 | 2431 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
2432 | if (!add_prefix (FWAIT_OPCODE)) |
2433 | return; | |
252b5132 | 2434 | |
29b0f896 | 2435 | /* Check string instruction segment overrides. */ |
40fb9820 | 2436 | if (i.tm.opcode_modifier.isstring && i.mem_operands != 0) |
29b0f896 AM |
2437 | { |
2438 | if (!check_string ()) | |
5dd0794d | 2439 | return; |
29b0f896 | 2440 | } |
5dd0794d | 2441 | |
29b0f896 AM |
2442 | if (!process_suffix ()) |
2443 | return; | |
e413e4e9 | 2444 | |
29b0f896 AM |
2445 | /* Make still unresolved immediate matches conform to size of immediate |
2446 | given in i.suffix. */ | |
2447 | if (!finalize_imm ()) | |
2448 | return; | |
252b5132 | 2449 | |
40fb9820 | 2450 | if (i.types[0].bitfield.imm1) |
29b0f896 | 2451 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 2452 | |
40fb9820 | 2453 | for (j = 0; j < 3; j++) |
c6fb90c8 L |
2454 | if (i.types[j].bitfield.inoutportreg |
2455 | || i.types[j].bitfield.shiftcount | |
2456 | || i.types[j].bitfield.acc | |
2457 | || i.types[j].bitfield.floatacc) | |
40fb9820 L |
2458 | i.reg_operands--; |
2459 | ||
2460 | if (i.tm.opcode_modifier.immext) | |
29b0f896 | 2461 | { |
02fc3089 L |
2462 | expressionS *exp; |
2463 | ||
40fb9820 | 2464 | if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0) |
ca164297 | 2465 | { |
b7d9ef37 | 2466 | /* Streaming SIMD extensions 3 Instructions have the fixed |
ca164297 L |
2467 | operands with an opcode suffix which is coded in the same |
2468 | place as an 8-bit immediate field would be. Here we check | |
2469 | those operands and remove them afterwards. */ | |
2470 | unsigned int x; | |
2471 | ||
a4622f40 | 2472 | for (x = 0; x < i.operands; x++) |
ca164297 | 2473 | if (i.op[x].regs->reg_num != x) |
a540244d L |
2474 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), |
2475 | register_prefix, | |
2476 | i.op[x].regs->reg_name, | |
2477 | x + 1, | |
2478 | i.tm.name); | |
ca164297 L |
2479 | i.operands = 0; |
2480 | } | |
2481 | ||
29b0f896 AM |
2482 | /* These AMD 3DNow! and Intel Katmai New Instructions have an |
2483 | opcode suffix which is coded in the same place as an 8-bit | |
2484 | immediate field would be. Here we fake an 8-bit immediate | |
85f10a01 MM |
2485 | operand from the opcode suffix stored in tm.extension_opcode. |
2486 | SSE5 also uses this encoding, for some of its 3 argument | |
2487 | instructions. */ | |
252b5132 | 2488 | |
85f10a01 MM |
2489 | assert (i.imm_operands == 0 |
2490 | && (i.operands <= 2 | |
2491 | || (i.tm.cpu_flags.bitfield.cpusse5 | |
2492 | && i.operands <= 3))); | |
252b5132 | 2493 | |
29b0f896 AM |
2494 | exp = &im_expressions[i.imm_operands++]; |
2495 | i.op[i.operands].imms = exp; | |
c6fb90c8 | 2496 | UINTS_CLEAR (i.types[i.operands]); |
40fb9820 L |
2497 | i.types[i.operands].bitfield.imm8 = 1; |
2498 | i.operands++; | |
29b0f896 AM |
2499 | exp->X_op = O_constant; |
2500 | exp->X_add_number = i.tm.extension_opcode; | |
2501 | i.tm.extension_opcode = None; | |
2502 | } | |
252b5132 | 2503 | |
29b0f896 AM |
2504 | /* For insns with operands there are more diddles to do to the opcode. */ |
2505 | if (i.operands) | |
2506 | { | |
2507 | if (!process_operands ()) | |
2508 | return; | |
2509 | } | |
40fb9820 | 2510 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
2511 | { |
2512 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
2513 | as_warn (_("translating to `%sp'"), i.tm.name); | |
2514 | } | |
252b5132 | 2515 | |
29b0f896 AM |
2516 | /* Handle conversion of 'int $3' --> special int3 insn. */ |
2517 | if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3) | |
2518 | { | |
2519 | i.tm.base_opcode = INT3_OPCODE; | |
2520 | i.imm_operands = 0; | |
2521 | } | |
252b5132 | 2522 | |
40fb9820 L |
2523 | if ((i.tm.opcode_modifier.jump |
2524 | || i.tm.opcode_modifier.jumpbyte | |
2525 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 AM |
2526 | && i.op[0].disps->X_op == O_constant) |
2527 | { | |
2528 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
2529 | the absolute address given by the constant. Since ix86 jumps and | |
2530 | calls are pc relative, we need to generate a reloc. */ | |
2531 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
2532 | i.op[0].disps->X_op = O_symbol; | |
2533 | } | |
252b5132 | 2534 | |
40fb9820 | 2535 | if (i.tm.opcode_modifier.rex64) |
161a04f6 | 2536 | i.rex |= REX_W; |
252b5132 | 2537 | |
29b0f896 AM |
2538 | /* For 8 bit registers we need an empty rex prefix. Also if the |
2539 | instruction already has a prefix, we need to convert old | |
2540 | registers to new ones. */ | |
773f551c | 2541 | |
40fb9820 | 2542 | if ((i.types[0].bitfield.reg8 |
29b0f896 | 2543 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
40fb9820 | 2544 | || (i.types[1].bitfield.reg8 |
29b0f896 | 2545 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
40fb9820 L |
2546 | || ((i.types[0].bitfield.reg8 |
2547 | || i.types[1].bitfield.reg8) | |
29b0f896 AM |
2548 | && i.rex != 0)) |
2549 | { | |
2550 | int x; | |
726c5dcd | 2551 | |
29b0f896 AM |
2552 | i.rex |= REX_OPCODE; |
2553 | for (x = 0; x < 2; x++) | |
2554 | { | |
2555 | /* Look for 8 bit operand that uses old registers. */ | |
40fb9820 | 2556 | if (i.types[x].bitfield.reg8 |
29b0f896 | 2557 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 2558 | { |
29b0f896 AM |
2559 | /* In case it is "hi" register, give up. */ |
2560 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 2561 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 2562 | "instruction requiring REX prefix."), |
a540244d | 2563 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 2564 | |
29b0f896 AM |
2565 | /* Otherwise it is equivalent to the extended register. |
2566 | Since the encoding doesn't change this is merely | |
2567 | cosmetic cleanup for debug output. */ | |
2568 | ||
2569 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 2570 | } |
29b0f896 AM |
2571 | } |
2572 | } | |
773f551c | 2573 | |
85f10a01 MM |
2574 | /* If the instruction has the DREX attribute (aka SSE5), don't emit a |
2575 | REX prefix. */ | |
2576 | if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc) | |
2577 | { | |
2578 | i.drex.rex = i.rex; | |
2579 | i.rex = 0; | |
2580 | } | |
2581 | else if (i.rex != 0) | |
29b0f896 AM |
2582 | add_prefix (REX_OPCODE | i.rex); |
2583 | ||
2584 | /* We are ready to output the insn. */ | |
2585 | output_insn (); | |
2586 | } | |
2587 | ||
2588 | static char * | |
e3bb37b5 | 2589 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
2590 | { |
2591 | char *l = line; | |
2592 | char *token_start = l; | |
2593 | char *mnem_p; | |
5c6af06e JB |
2594 | int supported; |
2595 | const template *t; | |
29b0f896 AM |
2596 | |
2597 | /* Non-zero if we found a prefix only acceptable with string insns. */ | |
2598 | const char *expecting_string_instruction = NULL; | |
45288df1 | 2599 | |
29b0f896 AM |
2600 | while (1) |
2601 | { | |
2602 | mnem_p = mnemonic; | |
2603 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
2604 | { | |
2605 | mnem_p++; | |
2606 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 2607 | { |
29b0f896 AM |
2608 | as_bad (_("no such instruction: `%s'"), token_start); |
2609 | return NULL; | |
2610 | } | |
2611 | l++; | |
2612 | } | |
2613 | if (!is_space_char (*l) | |
2614 | && *l != END_OF_INSN | |
e44823cf JB |
2615 | && (intel_syntax |
2616 | || (*l != PREFIX_SEPARATOR | |
2617 | && *l != ','))) | |
29b0f896 AM |
2618 | { |
2619 | as_bad (_("invalid character %s in mnemonic"), | |
2620 | output_invalid (*l)); | |
2621 | return NULL; | |
2622 | } | |
2623 | if (token_start == l) | |
2624 | { | |
e44823cf | 2625 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
2626 | as_bad (_("expecting prefix; got nothing")); |
2627 | else | |
2628 | as_bad (_("expecting mnemonic; got nothing")); | |
2629 | return NULL; | |
2630 | } | |
45288df1 | 2631 | |
29b0f896 AM |
2632 | /* Look up instruction (or prefix) via hash table. */ |
2633 | current_templates = hash_find (op_hash, mnemonic); | |
47926f60 | 2634 | |
29b0f896 AM |
2635 | if (*l != END_OF_INSN |
2636 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
2637 | && current_templates | |
40fb9820 | 2638 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 2639 | { |
c6fb90c8 | 2640 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
2641 | { |
2642 | as_bad ((flag_code != CODE_64BIT | |
2643 | ? _("`%s' is only supported in 64-bit mode") | |
2644 | : _("`%s' is not supported in 64-bit mode")), | |
2645 | current_templates->start->name); | |
2646 | return NULL; | |
2647 | } | |
29b0f896 AM |
2648 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
2649 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
40fb9820 L |
2650 | if ((current_templates->start->opcode_modifier.size16 |
2651 | || current_templates->start->opcode_modifier.size32) | |
29b0f896 | 2652 | && flag_code != CODE_64BIT |
40fb9820 | 2653 | && (current_templates->start->opcode_modifier.size32 |
29b0f896 AM |
2654 | ^ (flag_code == CODE_16BIT))) |
2655 | { | |
2656 | as_bad (_("redundant %s prefix"), | |
2657 | current_templates->start->name); | |
2658 | return NULL; | |
45288df1 | 2659 | } |
29b0f896 AM |
2660 | /* Add prefix, checking for repeated prefixes. */ |
2661 | switch (add_prefix (current_templates->start->base_opcode)) | |
2662 | { | |
2663 | case 0: | |
2664 | return NULL; | |
2665 | case 2: | |
2666 | expecting_string_instruction = current_templates->start->name; | |
2667 | break; | |
2668 | } | |
2669 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
2670 | token_start = ++l; | |
2671 | } | |
2672 | else | |
2673 | break; | |
2674 | } | |
45288df1 | 2675 | |
29b0f896 AM |
2676 | if (!current_templates) |
2677 | { | |
2678 | /* See if we can get a match by trimming off a suffix. */ | |
2679 | switch (mnem_p[-1]) | |
2680 | { | |
2681 | case WORD_MNEM_SUFFIX: | |
9306ca4a JB |
2682 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) |
2683 | i.suffix = SHORT_MNEM_SUFFIX; | |
2684 | else | |
29b0f896 AM |
2685 | case BYTE_MNEM_SUFFIX: |
2686 | case QWORD_MNEM_SUFFIX: | |
2687 | i.suffix = mnem_p[-1]; | |
2688 | mnem_p[-1] = '\0'; | |
2689 | current_templates = hash_find (op_hash, mnemonic); | |
2690 | break; | |
2691 | case SHORT_MNEM_SUFFIX: | |
2692 | case LONG_MNEM_SUFFIX: | |
2693 | if (!intel_syntax) | |
2694 | { | |
2695 | i.suffix = mnem_p[-1]; | |
2696 | mnem_p[-1] = '\0'; | |
2697 | current_templates = hash_find (op_hash, mnemonic); | |
2698 | } | |
2699 | break; | |
252b5132 | 2700 | |
29b0f896 AM |
2701 | /* Intel Syntax. */ |
2702 | case 'd': | |
2703 | if (intel_syntax) | |
2704 | { | |
9306ca4a | 2705 | if (intel_float_operand (mnemonic) == 1) |
29b0f896 AM |
2706 | i.suffix = SHORT_MNEM_SUFFIX; |
2707 | else | |
2708 | i.suffix = LONG_MNEM_SUFFIX; | |
2709 | mnem_p[-1] = '\0'; | |
2710 | current_templates = hash_find (op_hash, mnemonic); | |
2711 | } | |
2712 | break; | |
2713 | } | |
2714 | if (!current_templates) | |
2715 | { | |
2716 | as_bad (_("no such instruction: `%s'"), token_start); | |
2717 | return NULL; | |
2718 | } | |
2719 | } | |
252b5132 | 2720 | |
40fb9820 L |
2721 | if (current_templates->start->opcode_modifier.jump |
2722 | || current_templates->start->opcode_modifier.jumpbyte) | |
29b0f896 AM |
2723 | { |
2724 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
2725 | predict taken and predict not taken respectively. | |
2726 | I'm not sure that branch hints actually do anything on loop | |
2727 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
2728 | may work in the future and it doesn't hurt to accept them | |
2729 | now. */ | |
2730 | if (l[0] == ',' && l[1] == 'p') | |
2731 | { | |
2732 | if (l[2] == 't') | |
2733 | { | |
2734 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
2735 | return NULL; | |
2736 | l += 3; | |
2737 | } | |
2738 | else if (l[2] == 'n') | |
2739 | { | |
2740 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
2741 | return NULL; | |
2742 | l += 3; | |
2743 | } | |
2744 | } | |
2745 | } | |
2746 | /* Any other comma loses. */ | |
2747 | if (*l == ',') | |
2748 | { | |
2749 | as_bad (_("invalid character %s in mnemonic"), | |
2750 | output_invalid (*l)); | |
2751 | return NULL; | |
2752 | } | |
252b5132 | 2753 | |
29b0f896 | 2754 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
2755 | supported = 0; |
2756 | for (t = current_templates->start; t < current_templates->end; ++t) | |
2757 | { | |
3629bb00 L |
2758 | supported |= cpu_flags_match (t->cpu_flags); |
2759 | if (supported == 3) | |
2760 | goto skip; | |
5c6af06e | 2761 | } |
3629bb00 | 2762 | |
5c6af06e JB |
2763 | if (!(supported & 2)) |
2764 | { | |
2765 | as_bad (flag_code == CODE_64BIT | |
2766 | ? _("`%s' is not supported in 64-bit mode") | |
2767 | : _("`%s' is only supported in 64-bit mode"), | |
2768 | current_templates->start->name); | |
2769 | return NULL; | |
2770 | } | |
2771 | if (!(supported & 1)) | |
29b0f896 | 2772 | { |
3629bb00 L |
2773 | as_bad (_("`%s' is not supported on `%s%s'"), |
2774 | current_templates->start->name, cpu_arch_name, | |
2775 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); | |
2776 | return NULL; | |
29b0f896 | 2777 | } |
3629bb00 L |
2778 | |
2779 | skip: | |
2780 | if (!cpu_arch_flags.bitfield.cpui386 | |
40fb9820 | 2781 | && (flag_code != CODE_16BIT)) |
29b0f896 AM |
2782 | { |
2783 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
2784 | } | |
252b5132 | 2785 | |
29b0f896 | 2786 | /* Check for rep/repne without a string instruction. */ |
f41bbced | 2787 | if (expecting_string_instruction) |
29b0f896 | 2788 | { |
f41bbced JB |
2789 | static templates override; |
2790 | ||
2791 | for (t = current_templates->start; t < current_templates->end; ++t) | |
40fb9820 | 2792 | if (t->opcode_modifier.isstring) |
f41bbced JB |
2793 | break; |
2794 | if (t >= current_templates->end) | |
2795 | { | |
2796 | as_bad (_("expecting string instruction after `%s'"), | |
64e74474 | 2797 | expecting_string_instruction); |
f41bbced JB |
2798 | return NULL; |
2799 | } | |
2800 | for (override.start = t; t < current_templates->end; ++t) | |
40fb9820 | 2801 | if (!t->opcode_modifier.isstring) |
f41bbced JB |
2802 | break; |
2803 | override.end = t; | |
2804 | current_templates = &override; | |
29b0f896 | 2805 | } |
252b5132 | 2806 | |
29b0f896 AM |
2807 | return l; |
2808 | } | |
252b5132 | 2809 | |
29b0f896 | 2810 | static char * |
e3bb37b5 | 2811 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
2812 | { |
2813 | char *token_start; | |
3138f287 | 2814 | |
29b0f896 AM |
2815 | /* 1 if operand is pending after ','. */ |
2816 | unsigned int expecting_operand = 0; | |
252b5132 | 2817 | |
29b0f896 AM |
2818 | /* Non-zero if operand parens not balanced. */ |
2819 | unsigned int paren_not_balanced; | |
2820 | ||
2821 | while (*l != END_OF_INSN) | |
2822 | { | |
2823 | /* Skip optional white space before operand. */ | |
2824 | if (is_space_char (*l)) | |
2825 | ++l; | |
2826 | if (!is_operand_char (*l) && *l != END_OF_INSN) | |
2827 | { | |
2828 | as_bad (_("invalid character %s before operand %d"), | |
2829 | output_invalid (*l), | |
2830 | i.operands + 1); | |
2831 | return NULL; | |
2832 | } | |
2833 | token_start = l; /* after white space */ | |
2834 | paren_not_balanced = 0; | |
2835 | while (paren_not_balanced || *l != ',') | |
2836 | { | |
2837 | if (*l == END_OF_INSN) | |
2838 | { | |
2839 | if (paren_not_balanced) | |
2840 | { | |
2841 | if (!intel_syntax) | |
2842 | as_bad (_("unbalanced parenthesis in operand %d."), | |
2843 | i.operands + 1); | |
2844 | else | |
2845 | as_bad (_("unbalanced brackets in operand %d."), | |
2846 | i.operands + 1); | |
2847 | return NULL; | |
2848 | } | |
2849 | else | |
2850 | break; /* we are done */ | |
2851 | } | |
2852 | else if (!is_operand_char (*l) && !is_space_char (*l)) | |
2853 | { | |
2854 | as_bad (_("invalid character %s in operand %d"), | |
2855 | output_invalid (*l), | |
2856 | i.operands + 1); | |
2857 | return NULL; | |
2858 | } | |
2859 | if (!intel_syntax) | |
2860 | { | |
2861 | if (*l == '(') | |
2862 | ++paren_not_balanced; | |
2863 | if (*l == ')') | |
2864 | --paren_not_balanced; | |
2865 | } | |
2866 | else | |
2867 | { | |
2868 | if (*l == '[') | |
2869 | ++paren_not_balanced; | |
2870 | if (*l == ']') | |
2871 | --paren_not_balanced; | |
2872 | } | |
2873 | l++; | |
2874 | } | |
2875 | if (l != token_start) | |
2876 | { /* Yes, we've read in another operand. */ | |
2877 | unsigned int operand_ok; | |
2878 | this_operand = i.operands++; | |
7d5e4556 | 2879 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
2880 | if (i.operands > MAX_OPERANDS) |
2881 | { | |
2882 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
2883 | MAX_OPERANDS); | |
2884 | return NULL; | |
2885 | } | |
2886 | /* Now parse operand adding info to 'i' as we go along. */ | |
2887 | END_STRING_AND_SAVE (l); | |
2888 | ||
2889 | if (intel_syntax) | |
2890 | operand_ok = | |
2891 | i386_intel_operand (token_start, | |
2892 | intel_float_operand (mnemonic)); | |
2893 | else | |
a7619375 | 2894 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
2895 | |
2896 | RESTORE_END_STRING (l); | |
2897 | if (!operand_ok) | |
2898 | return NULL; | |
2899 | } | |
2900 | else | |
2901 | { | |
2902 | if (expecting_operand) | |
2903 | { | |
2904 | expecting_operand_after_comma: | |
2905 | as_bad (_("expecting operand after ','; got nothing")); | |
2906 | return NULL; | |
2907 | } | |
2908 | if (*l == ',') | |
2909 | { | |
2910 | as_bad (_("expecting operand before ','; got nothing")); | |
2911 | return NULL; | |
2912 | } | |
2913 | } | |
7f3f1ea2 | 2914 | |
29b0f896 AM |
2915 | /* Now *l must be either ',' or END_OF_INSN. */ |
2916 | if (*l == ',') | |
2917 | { | |
2918 | if (*++l == END_OF_INSN) | |
2919 | { | |
2920 | /* Just skip it, if it's \n complain. */ | |
2921 | goto expecting_operand_after_comma; | |
2922 | } | |
2923 | expecting_operand = 1; | |
2924 | } | |
2925 | } | |
2926 | return l; | |
2927 | } | |
7f3f1ea2 | 2928 | |
050dfa73 | 2929 | static void |
4d456e3d | 2930 | swap_2_operands (int xchg1, int xchg2) |
050dfa73 MM |
2931 | { |
2932 | union i386_op temp_op; | |
40fb9820 | 2933 | i386_operand_type temp_type; |
050dfa73 | 2934 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 2935 | |
050dfa73 MM |
2936 | temp_type = i.types[xchg2]; |
2937 | i.types[xchg2] = i.types[xchg1]; | |
2938 | i.types[xchg1] = temp_type; | |
2939 | temp_op = i.op[xchg2]; | |
2940 | i.op[xchg2] = i.op[xchg1]; | |
2941 | i.op[xchg1] = temp_op; | |
2942 | temp_reloc = i.reloc[xchg2]; | |
2943 | i.reloc[xchg2] = i.reloc[xchg1]; | |
2944 | i.reloc[xchg1] = temp_reloc; | |
2945 | } | |
2946 | ||
29b0f896 | 2947 | static void |
e3bb37b5 | 2948 | swap_operands (void) |
29b0f896 | 2949 | { |
b7c61d9a | 2950 | switch (i.operands) |
050dfa73 | 2951 | { |
b7c61d9a | 2952 | case 4: |
4d456e3d | 2953 | swap_2_operands (1, i.operands - 2); |
b7c61d9a L |
2954 | case 3: |
2955 | case 2: | |
4d456e3d | 2956 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
2957 | break; |
2958 | default: | |
2959 | abort (); | |
29b0f896 | 2960 | } |
29b0f896 AM |
2961 | |
2962 | if (i.mem_operands == 2) | |
2963 | { | |
2964 | const seg_entry *temp_seg; | |
2965 | temp_seg = i.seg[0]; | |
2966 | i.seg[0] = i.seg[1]; | |
2967 | i.seg[1] = temp_seg; | |
2968 | } | |
2969 | } | |
252b5132 | 2970 | |
29b0f896 AM |
2971 | /* Try to ensure constant immediates are represented in the smallest |
2972 | opcode possible. */ | |
2973 | static void | |
e3bb37b5 | 2974 | optimize_imm (void) |
29b0f896 AM |
2975 | { |
2976 | char guess_suffix = 0; | |
2977 | int op; | |
252b5132 | 2978 | |
29b0f896 AM |
2979 | if (i.suffix) |
2980 | guess_suffix = i.suffix; | |
2981 | else if (i.reg_operands) | |
2982 | { | |
2983 | /* Figure out a suffix from the last register operand specified. | |
2984 | We can't do this properly yet, ie. excluding InOutPortReg, | |
2985 | but the following works for instructions with immediates. | |
2986 | In any case, we can't set i.suffix yet. */ | |
2987 | for (op = i.operands; --op >= 0;) | |
40fb9820 L |
2988 | if (i.types[op].bitfield.reg8) |
2989 | { | |
2990 | guess_suffix = BYTE_MNEM_SUFFIX; | |
2991 | break; | |
2992 | } | |
2993 | else if (i.types[op].bitfield.reg16) | |
252b5132 | 2994 | { |
40fb9820 L |
2995 | guess_suffix = WORD_MNEM_SUFFIX; |
2996 | break; | |
2997 | } | |
2998 | else if (i.types[op].bitfield.reg32) | |
2999 | { | |
3000 | guess_suffix = LONG_MNEM_SUFFIX; | |
3001 | break; | |
3002 | } | |
3003 | else if (i.types[op].bitfield.reg64) | |
3004 | { | |
3005 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 3006 | break; |
252b5132 | 3007 | } |
29b0f896 AM |
3008 | } |
3009 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
3010 | guess_suffix = WORD_MNEM_SUFFIX; | |
3011 | ||
3012 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 3013 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
3014 | { |
3015 | switch (i.op[op].imms->X_op) | |
252b5132 | 3016 | { |
29b0f896 AM |
3017 | case O_constant: |
3018 | /* If a suffix is given, this operand may be shortened. */ | |
3019 | switch (guess_suffix) | |
252b5132 | 3020 | { |
29b0f896 | 3021 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
3022 | i.types[op].bitfield.imm32 = 1; |
3023 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
3024 | break; |
3025 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
3026 | i.types[op].bitfield.imm16 = 1; |
3027 | i.types[op].bitfield.imm32 = 1; | |
3028 | i.types[op].bitfield.imm32s = 1; | |
3029 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
3030 | break; |
3031 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
3032 | i.types[op].bitfield.imm8 = 1; |
3033 | i.types[op].bitfield.imm8s = 1; | |
3034 | i.types[op].bitfield.imm16 = 1; | |
3035 | i.types[op].bitfield.imm32 = 1; | |
3036 | i.types[op].bitfield.imm32s = 1; | |
3037 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 3038 | break; |
252b5132 | 3039 | } |
252b5132 | 3040 | |
29b0f896 AM |
3041 | /* If this operand is at most 16 bits, convert it |
3042 | to a signed 16 bit number before trying to see | |
3043 | whether it will fit in an even smaller size. | |
3044 | This allows a 16-bit operand such as $0xffe0 to | |
3045 | be recognised as within Imm8S range. */ | |
40fb9820 | 3046 | if ((i.types[op].bitfield.imm16) |
29b0f896 | 3047 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
252b5132 | 3048 | { |
29b0f896 AM |
3049 | i.op[op].imms->X_add_number = |
3050 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
3051 | } | |
40fb9820 | 3052 | if ((i.types[op].bitfield.imm32) |
29b0f896 AM |
3053 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
3054 | == 0)) | |
3055 | { | |
3056 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
3057 | ^ ((offsetT) 1 << 31)) | |
3058 | - ((offsetT) 1 << 31)); | |
3059 | } | |
40fb9820 | 3060 | i.types[op] |
c6fb90c8 L |
3061 | = operand_type_or (i.types[op], |
3062 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 3063 | |
29b0f896 AM |
3064 | /* We must avoid matching of Imm32 templates when 64bit |
3065 | only immediate is available. */ | |
3066 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 3067 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 3068 | break; |
252b5132 | 3069 | |
29b0f896 AM |
3070 | case O_absent: |
3071 | case O_register: | |
3072 | abort (); | |
3073 | ||
3074 | /* Symbols and expressions. */ | |
3075 | default: | |
9cd96992 JB |
3076 | /* Convert symbolic operand to proper sizes for matching, but don't |
3077 | prevent matching a set of insns that only supports sizes other | |
3078 | than those matching the insn suffix. */ | |
3079 | { | |
40fb9820 | 3080 | i386_operand_type mask, allowed; |
9cd96992 JB |
3081 | const template *t; |
3082 | ||
c6fb90c8 L |
3083 | UINTS_CLEAR (mask); |
3084 | UINTS_CLEAR (allowed); | |
40fb9820 | 3085 | |
4eed87de AM |
3086 | for (t = current_templates->start; |
3087 | t < current_templates->end; | |
3088 | ++t) | |
c6fb90c8 L |
3089 | allowed = operand_type_or (allowed, |
3090 | t->operand_types[op]); | |
9cd96992 JB |
3091 | switch (guess_suffix) |
3092 | { | |
3093 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
3094 | mask.bitfield.imm64 = 1; |
3095 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
3096 | break; |
3097 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 3098 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
3099 | break; |
3100 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 3101 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
3102 | break; |
3103 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 3104 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
3105 | break; |
3106 | default: | |
9cd96992 JB |
3107 | break; |
3108 | } | |
c6fb90c8 L |
3109 | allowed = operand_type_and (mask, allowed); |
3110 | if (!UINTS_ALL_ZERO (allowed)) | |
3111 | i.types[op] = operand_type_and (i.types[op], mask); | |
9cd96992 | 3112 | } |
29b0f896 | 3113 | break; |
252b5132 | 3114 | } |
29b0f896 AM |
3115 | } |
3116 | } | |
47926f60 | 3117 | |
29b0f896 AM |
3118 | /* Try to use the smallest displacement type too. */ |
3119 | static void | |
e3bb37b5 | 3120 | optimize_disp (void) |
29b0f896 AM |
3121 | { |
3122 | int op; | |
3e73aa7c | 3123 | |
29b0f896 | 3124 | for (op = i.operands; --op >= 0;) |
40fb9820 | 3125 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 3126 | { |
b300c311 | 3127 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 3128 | { |
b300c311 | 3129 | offsetT disp = i.op[op].disps->X_add_number; |
29b0f896 | 3130 | |
40fb9820 | 3131 | if (i.types[op].bitfield.disp16 |
b300c311 L |
3132 | && (disp & ~(offsetT) 0xffff) == 0) |
3133 | { | |
3134 | /* If this operand is at most 16 bits, convert | |
3135 | to a signed 16 bit number and don't use 64bit | |
3136 | displacement. */ | |
3137 | disp = (((disp & 0xffff) ^ 0x8000) - 0x8000); | |
40fb9820 | 3138 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 3139 | } |
40fb9820 | 3140 | if (i.types[op].bitfield.disp32 |
b300c311 L |
3141 | && (disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
3142 | { | |
3143 | /* If this operand is at most 32 bits, convert | |
3144 | to a signed 32 bit number and don't use 64bit | |
3145 | displacement. */ | |
3146 | disp &= (((offsetT) 2 << 31) - 1); | |
3147 | disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
40fb9820 | 3148 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 3149 | } |
40fb9820 | 3150 | if (!disp && i.types[op].bitfield.baseindex) |
b300c311 | 3151 | { |
40fb9820 L |
3152 | i.types[op].bitfield.disp8 = 0; |
3153 | i.types[op].bitfield.disp16 = 0; | |
3154 | i.types[op].bitfield.disp32 = 0; | |
3155 | i.types[op].bitfield.disp32s = 0; | |
3156 | i.types[op].bitfield.disp64 = 0; | |
b300c311 L |
3157 | i.op[op].disps = 0; |
3158 | i.disp_operands--; | |
3159 | } | |
3160 | else if (flag_code == CODE_64BIT) | |
3161 | { | |
3162 | if (fits_in_signed_long (disp)) | |
28a9d8f5 | 3163 | { |
40fb9820 L |
3164 | i.types[op].bitfield.disp64 = 0; |
3165 | i.types[op].bitfield.disp32s = 1; | |
28a9d8f5 | 3166 | } |
b300c311 | 3167 | if (fits_in_unsigned_long (disp)) |
40fb9820 | 3168 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 3169 | } |
40fb9820 L |
3170 | if ((i.types[op].bitfield.disp32 |
3171 | || i.types[op].bitfield.disp32s | |
3172 | || i.types[op].bitfield.disp16) | |
b300c311 | 3173 | && fits_in_signed_byte (disp)) |
40fb9820 | 3174 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 3175 | } |
67a4f2b7 AO |
3176 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
3177 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
3178 | { | |
3179 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
3180 | i.op[op].disps, 0, i.reloc[op]); | |
40fb9820 L |
3181 | i.types[op].bitfield.disp8 = 0; |
3182 | i.types[op].bitfield.disp16 = 0; | |
3183 | i.types[op].bitfield.disp32 = 0; | |
3184 | i.types[op].bitfield.disp32s = 0; | |
3185 | i.types[op].bitfield.disp64 = 0; | |
67a4f2b7 AO |
3186 | } |
3187 | else | |
b300c311 | 3188 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 3189 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 3190 | } |
29b0f896 AM |
3191 | } |
3192 | ||
3193 | static int | |
e3bb37b5 | 3194 | match_template (void) |
29b0f896 AM |
3195 | { |
3196 | /* Points to template once we've found it. */ | |
3197 | const template *t; | |
40fb9820 | 3198 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
29b0f896 | 3199 | unsigned int found_reverse_match; |
40fb9820 L |
3200 | i386_opcode_modifier suffix_check; |
3201 | i386_operand_type operand_types [MAX_OPERANDS]; | |
539e75ad | 3202 | int addr_prefix_disp; |
a5c311ca | 3203 | unsigned int j; |
3629bb00 | 3204 | unsigned int found_cpu_match; |
45664ddb | 3205 | unsigned int check_register; |
29b0f896 | 3206 | |
f48ff2ae L |
3207 | #if MAX_OPERANDS != 4 |
3208 | # error "MAX_OPERANDS must be 4." | |
3209 | #endif | |
3210 | ||
29b0f896 | 3211 | found_reverse_match = 0; |
539e75ad | 3212 | addr_prefix_disp = -1; |
40fb9820 L |
3213 | |
3214 | memset (&suffix_check, 0, sizeof (suffix_check)); | |
3215 | if (i.suffix == BYTE_MNEM_SUFFIX) | |
3216 | suffix_check.no_bsuf = 1; | |
3217 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
3218 | suffix_check.no_wsuf = 1; | |
3219 | else if (i.suffix == SHORT_MNEM_SUFFIX) | |
3220 | suffix_check.no_ssuf = 1; | |
3221 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
3222 | suffix_check.no_lsuf = 1; | |
3223 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
3224 | suffix_check.no_qsuf = 1; | |
3225 | else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
7ce189b3 | 3226 | suffix_check.no_ldsuf = 1; |
29b0f896 | 3227 | |
45aa61fe | 3228 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 3229 | { |
539e75ad L |
3230 | addr_prefix_disp = -1; |
3231 | ||
29b0f896 AM |
3232 | /* Must have right number of operands. */ |
3233 | if (i.operands != t->operands) | |
3234 | continue; | |
3235 | ||
50aecf8c L |
3236 | /* Check processor support. */ |
3237 | found_cpu_match = cpu_flags_match (t->cpu_flags) == 3; | |
3238 | if (!found_cpu_match) | |
3239 | continue; | |
3240 | ||
e1d4d893 L |
3241 | /* Check old gcc support. */ |
3242 | if (!old_gcc && t->opcode_modifier.oldgcc) | |
3243 | continue; | |
3244 | ||
3245 | /* Check AT&T mnemonic. */ | |
3246 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) | |
1efbbeb4 L |
3247 | continue; |
3248 | ||
5c07affc L |
3249 | /* Check AT&T syntax Intel syntax. */ |
3250 | if ((intel_syntax && t->opcode_modifier.attsyntax) | |
3251 | || (!intel_syntax && t->opcode_modifier.intelsyntax)) | |
1efbbeb4 L |
3252 | continue; |
3253 | ||
20592a94 | 3254 | /* Check the suffix, except for some instructions in intel mode. */ |
567e4e96 L |
3255 | if ((!intel_syntax || !t->opcode_modifier.ignoresize) |
3256 | && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) | |
3257 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
3258 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
3259 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
3260 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
3261 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf))) | |
29b0f896 AM |
3262 | continue; |
3263 | ||
5c07affc | 3264 | if (!operand_size_match (t)) |
7d5e4556 | 3265 | continue; |
539e75ad | 3266 | |
5c07affc L |
3267 | for (j = 0; j < MAX_OPERANDS; j++) |
3268 | operand_types[j] = t->operand_types[j]; | |
3269 | ||
45aa61fe AM |
3270 | /* In general, don't allow 64-bit operands in 32-bit mode. */ |
3271 | if (i.suffix == QWORD_MNEM_SUFFIX | |
3272 | && flag_code != CODE_64BIT | |
3273 | && (intel_syntax | |
40fb9820 | 3274 | ? (!t->opcode_modifier.ignoresize |
45aa61fe AM |
3275 | && !intel_float_operand (t->name)) |
3276 | : intel_float_operand (t->name) != 2) | |
40fb9820 L |
3277 | && ((!operand_types[0].bitfield.regmmx |
3278 | && !operand_types[0].bitfield.regxmm) | |
3279 | || (!operand_types[t->operands > 1].bitfield.regmmx | |
3280 | && !!operand_types[t->operands > 1].bitfield.regxmm)) | |
45aa61fe AM |
3281 | && (t->base_opcode != 0x0fc7 |
3282 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
3283 | continue; | |
3284 | ||
29b0f896 | 3285 | /* Do not verify operands when there are none. */ |
50aecf8c | 3286 | else |
29b0f896 | 3287 | { |
c6fb90c8 | 3288 | if (!t->operands) |
2dbab7d5 L |
3289 | /* We've found a match; break out of loop. */ |
3290 | break; | |
29b0f896 | 3291 | } |
252b5132 | 3292 | |
539e75ad L |
3293 | /* Address size prefix will turn Disp64/Disp32/Disp16 operand |
3294 | into Disp32/Disp16/Disp32 operand. */ | |
3295 | if (i.prefix[ADDR_PREFIX] != 0) | |
3296 | { | |
40fb9820 | 3297 | /* There should be only one Disp operand. */ |
539e75ad L |
3298 | switch (flag_code) |
3299 | { | |
3300 | case CODE_16BIT: | |
40fb9820 L |
3301 | for (j = 0; j < MAX_OPERANDS; j++) |
3302 | { | |
3303 | if (operand_types[j].bitfield.disp16) | |
3304 | { | |
3305 | addr_prefix_disp = j; | |
3306 | operand_types[j].bitfield.disp32 = 1; | |
3307 | operand_types[j].bitfield.disp16 = 0; | |
3308 | break; | |
3309 | } | |
3310 | } | |
539e75ad L |
3311 | break; |
3312 | case CODE_32BIT: | |
40fb9820 L |
3313 | for (j = 0; j < MAX_OPERANDS; j++) |
3314 | { | |
3315 | if (operand_types[j].bitfield.disp32) | |
3316 | { | |
3317 | addr_prefix_disp = j; | |
3318 | operand_types[j].bitfield.disp32 = 0; | |
3319 | operand_types[j].bitfield.disp16 = 1; | |
3320 | break; | |
3321 | } | |
3322 | } | |
539e75ad L |
3323 | break; |
3324 | case CODE_64BIT: | |
40fb9820 L |
3325 | for (j = 0; j < MAX_OPERANDS; j++) |
3326 | { | |
3327 | if (operand_types[j].bitfield.disp64) | |
3328 | { | |
3329 | addr_prefix_disp = j; | |
3330 | operand_types[j].bitfield.disp64 = 0; | |
3331 | operand_types[j].bitfield.disp32 = 1; | |
3332 | break; | |
3333 | } | |
3334 | } | |
539e75ad L |
3335 | break; |
3336 | } | |
539e75ad L |
3337 | } |
3338 | ||
45664ddb L |
3339 | /* We check register size only if size of operands can be |
3340 | encoded the canonical way. */ | |
3341 | check_register = t->opcode_modifier.w; | |
c6fb90c8 | 3342 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
3343 | switch (t->operands) |
3344 | { | |
3345 | case 1: | |
40fb9820 | 3346 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
3347 | continue; |
3348 | break; | |
3349 | case 2: | |
8b38ad71 L |
3350 | /* xchg %eax, %eax is a special case. It is an aliase for nop |
3351 | only in 32bit mode and we can use opcode 0x90. In 64bit | |
3352 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
3353 | zero-extend %eax to %rax. */ | |
3354 | if (flag_code == CODE_64BIT | |
3355 | && t->base_opcode == 0x90 | |
c6fb90c8 L |
3356 | && UINTS_EQUAL (i.types [0], acc32) |
3357 | && UINTS_EQUAL (i.types [1], acc32)) | |
8b38ad71 | 3358 | continue; |
29b0f896 | 3359 | case 3: |
f48ff2ae | 3360 | case 4: |
c6fb90c8 | 3361 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
3362 | if (!operand_type_match (overlap0, i.types[0]) |
3363 | || !operand_type_match (overlap1, i.types[1]) | |
45664ddb L |
3364 | || (check_register |
3365 | && !operand_type_register_match (overlap0, i.types[0], | |
40fb9820 L |
3366 | operand_types[0], |
3367 | overlap1, i.types[1], | |
3368 | operand_types[1]))) | |
29b0f896 AM |
3369 | { |
3370 | /* Check if other direction is valid ... */ | |
40fb9820 | 3371 | if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) |
29b0f896 AM |
3372 | continue; |
3373 | ||
3374 | /* Try reversing direction of operands. */ | |
c6fb90c8 L |
3375 | overlap0 = operand_type_and (i.types[0], operand_types[1]); |
3376 | overlap1 = operand_type_and (i.types[1], operand_types[0]); | |
40fb9820 L |
3377 | if (!operand_type_match (overlap0, i.types[0]) |
3378 | || !operand_type_match (overlap1, i.types[1]) | |
45664ddb L |
3379 | || (check_register |
3380 | && !operand_type_register_match (overlap0, | |
3381 | i.types[0], | |
3382 | operand_types[1], | |
3383 | overlap1, | |
3384 | i.types[1], | |
3385 | operand_types[0]))) | |
29b0f896 AM |
3386 | { |
3387 | /* Does not match either direction. */ | |
3388 | continue; | |
3389 | } | |
3390 | /* found_reverse_match holds which of D or FloatDR | |
3391 | we've found. */ | |
40fb9820 | 3392 | if (t->opcode_modifier.d) |
8a2ed489 | 3393 | found_reverse_match = Opcode_D; |
40fb9820 | 3394 | else if (t->opcode_modifier.floatd) |
8a2ed489 L |
3395 | found_reverse_match = Opcode_FloatD; |
3396 | else | |
3397 | found_reverse_match = 0; | |
40fb9820 | 3398 | if (t->opcode_modifier.floatr) |
8a2ed489 | 3399 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 3400 | } |
f48ff2ae | 3401 | else |
29b0f896 | 3402 | { |
f48ff2ae | 3403 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
3404 | switch (t->operands) |
3405 | { | |
3406 | case 4: | |
c6fb90c8 L |
3407 | overlap3 = operand_type_and (i.types[3], |
3408 | operand_types[3]); | |
d1cbb4db | 3409 | case 3: |
c6fb90c8 L |
3410 | overlap2 = operand_type_and (i.types[2], |
3411 | operand_types[2]); | |
d1cbb4db L |
3412 | break; |
3413 | } | |
29b0f896 | 3414 | |
f48ff2ae L |
3415 | switch (t->operands) |
3416 | { | |
3417 | case 4: | |
40fb9820 | 3418 | if (!operand_type_match (overlap3, i.types[3]) |
45664ddb L |
3419 | || (check_register |
3420 | && !operand_type_register_match (overlap2, | |
3421 | i.types[2], | |
3422 | operand_types[2], | |
3423 | overlap3, | |
3424 | i.types[3], | |
3425 | operand_types[3]))) | |
f48ff2ae L |
3426 | continue; |
3427 | case 3: | |
3428 | /* Here we make use of the fact that there are no | |
3429 | reverse match 3 operand instructions, and all 3 | |
3430 | operand instructions only need to be checked for | |
3431 | register consistency between operands 2 and 3. */ | |
40fb9820 | 3432 | if (!operand_type_match (overlap2, i.types[2]) |
45664ddb L |
3433 | || (check_register |
3434 | && !operand_type_register_match (overlap1, | |
3435 | i.types[1], | |
3436 | operand_types[1], | |
3437 | overlap2, | |
3438 | i.types[2], | |
3439 | operand_types[2]))) | |
f48ff2ae L |
3440 | continue; |
3441 | break; | |
3442 | } | |
29b0f896 | 3443 | } |
f48ff2ae | 3444 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
3445 | slip through to break. */ |
3446 | } | |
3629bb00 | 3447 | if (!found_cpu_match) |
29b0f896 AM |
3448 | { |
3449 | found_reverse_match = 0; | |
3450 | continue; | |
3451 | } | |
3452 | /* We've found a match; break out of loop. */ | |
3453 | break; | |
3454 | } | |
3455 | ||
3456 | if (t == current_templates->end) | |
3457 | { | |
3458 | /* We found no match. */ | |
3459 | as_bad (_("suffix or operands invalid for `%s'"), | |
3460 | current_templates->start->name); | |
3461 | return 0; | |
3462 | } | |
252b5132 | 3463 | |
29b0f896 AM |
3464 | if (!quiet_warnings) |
3465 | { | |
3466 | if (!intel_syntax | |
40fb9820 L |
3467 | && (i.types[0].bitfield.jumpabsolute |
3468 | != operand_types[0].bitfield.jumpabsolute)) | |
29b0f896 AM |
3469 | { |
3470 | as_warn (_("indirect %s without `*'"), t->name); | |
3471 | } | |
3472 | ||
40fb9820 L |
3473 | if (t->opcode_modifier.isprefix |
3474 | && t->opcode_modifier.ignoresize) | |
29b0f896 AM |
3475 | { |
3476 | /* Warn them that a data or address size prefix doesn't | |
3477 | affect assembly of the next line of code. */ | |
3478 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
3479 | } | |
3480 | } | |
3481 | ||
3482 | /* Copy the template we found. */ | |
3483 | i.tm = *t; | |
539e75ad L |
3484 | |
3485 | if (addr_prefix_disp != -1) | |
3486 | i.tm.operand_types[addr_prefix_disp] | |
3487 | = operand_types[addr_prefix_disp]; | |
3488 | ||
29b0f896 AM |
3489 | if (found_reverse_match) |
3490 | { | |
3491 | /* If we found a reverse match we must alter the opcode | |
3492 | direction bit. found_reverse_match holds bits to change | |
3493 | (different for int & float insns). */ | |
3494 | ||
3495 | i.tm.base_opcode ^= found_reverse_match; | |
3496 | ||
539e75ad L |
3497 | i.tm.operand_types[0] = operand_types[1]; |
3498 | i.tm.operand_types[1] = operand_types[0]; | |
29b0f896 AM |
3499 | } |
3500 | ||
3501 | return 1; | |
3502 | } | |
3503 | ||
3504 | static int | |
e3bb37b5 | 3505 | check_string (void) |
29b0f896 | 3506 | { |
40fb9820 L |
3507 | int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1; |
3508 | if (i.tm.operand_types[mem_op].bitfield.esseg) | |
29b0f896 AM |
3509 | { |
3510 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
3511 | { | |
3512 | as_bad (_("`%s' operand %d must use `%%es' segment"), | |
3513 | i.tm.name, | |
3514 | mem_op + 1); | |
3515 | return 0; | |
3516 | } | |
3517 | /* There's only ever one segment override allowed per instruction. | |
3518 | This instruction possibly has a legal segment override on the | |
3519 | second operand, so copy the segment to where non-string | |
3520 | instructions store it, allowing common code. */ | |
3521 | i.seg[0] = i.seg[1]; | |
3522 | } | |
40fb9820 | 3523 | else if (i.tm.operand_types[mem_op + 1].bitfield.esseg) |
29b0f896 AM |
3524 | { |
3525 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
3526 | { | |
3527 | as_bad (_("`%s' operand %d must use `%%es' segment"), | |
3528 | i.tm.name, | |
3529 | mem_op + 2); | |
3530 | return 0; | |
3531 | } | |
3532 | } | |
3533 | return 1; | |
3534 | } | |
3535 | ||
3536 | static int | |
543613e9 | 3537 | process_suffix (void) |
29b0f896 AM |
3538 | { |
3539 | /* If matched instruction specifies an explicit instruction mnemonic | |
3540 | suffix, use it. */ | |
40fb9820 L |
3541 | if (i.tm.opcode_modifier.size16) |
3542 | i.suffix = WORD_MNEM_SUFFIX; | |
3543 | else if (i.tm.opcode_modifier.size32) | |
3544 | i.suffix = LONG_MNEM_SUFFIX; | |
3545 | else if (i.tm.opcode_modifier.size64) | |
3546 | i.suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 AM |
3547 | else if (i.reg_operands) |
3548 | { | |
3549 | /* If there's no instruction mnemonic suffix we try to invent one | |
3550 | based on register operands. */ | |
3551 | if (!i.suffix) | |
3552 | { | |
3553 | /* We take i.suffix from the last register operand specified, | |
3554 | Destination register type is more significant than source | |
381d071f L |
3555 | register type. crc32 in SSE4.2 prefers source register |
3556 | type. */ | |
3557 | if (i.tm.base_opcode == 0xf20f38f1) | |
3558 | { | |
40fb9820 L |
3559 | if (i.types[0].bitfield.reg16) |
3560 | i.suffix = WORD_MNEM_SUFFIX; | |
3561 | else if (i.types[0].bitfield.reg32) | |
3562 | i.suffix = LONG_MNEM_SUFFIX; | |
3563 | else if (i.types[0].bitfield.reg64) | |
3564 | i.suffix = QWORD_MNEM_SUFFIX; | |
381d071f | 3565 | } |
9344ff29 | 3566 | else if (i.tm.base_opcode == 0xf20f38f0) |
20592a94 | 3567 | { |
40fb9820 | 3568 | if (i.types[0].bitfield.reg8) |
20592a94 L |
3569 | i.suffix = BYTE_MNEM_SUFFIX; |
3570 | } | |
381d071f L |
3571 | |
3572 | if (!i.suffix) | |
3573 | { | |
3574 | int op; | |
3575 | ||
20592a94 L |
3576 | if (i.tm.base_opcode == 0xf20f38f1 |
3577 | || i.tm.base_opcode == 0xf20f38f0) | |
3578 | { | |
3579 | /* We have to know the operand size for crc32. */ | |
3580 | as_bad (_("ambiguous memory operand size for `%s`"), | |
3581 | i.tm.name); | |
3582 | return 0; | |
3583 | } | |
3584 | ||
381d071f | 3585 | for (op = i.operands; --op >= 0;) |
40fb9820 | 3586 | if (!i.tm.operand_types[op].bitfield.inoutportreg) |
381d071f | 3587 | { |
40fb9820 L |
3588 | if (i.types[op].bitfield.reg8) |
3589 | { | |
3590 | i.suffix = BYTE_MNEM_SUFFIX; | |
3591 | break; | |
3592 | } | |
3593 | else if (i.types[op].bitfield.reg16) | |
3594 | { | |
3595 | i.suffix = WORD_MNEM_SUFFIX; | |
3596 | break; | |
3597 | } | |
3598 | else if (i.types[op].bitfield.reg32) | |
3599 | { | |
3600 | i.suffix = LONG_MNEM_SUFFIX; | |
3601 | break; | |
3602 | } | |
3603 | else if (i.types[op].bitfield.reg64) | |
3604 | { | |
3605 | i.suffix = QWORD_MNEM_SUFFIX; | |
3606 | break; | |
3607 | } | |
381d071f L |
3608 | } |
3609 | } | |
29b0f896 AM |
3610 | } |
3611 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
3612 | { | |
3613 | if (!check_byte_reg ()) | |
3614 | return 0; | |
3615 | } | |
3616 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
3617 | { | |
3618 | if (!check_long_reg ()) | |
3619 | return 0; | |
3620 | } | |
3621 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
3622 | { | |
955e1e6a L |
3623 | if (intel_syntax |
3624 | && i.tm.opcode_modifier.ignoresize | |
3625 | && i.tm.opcode_modifier.no_qsuf) | |
3626 | i.suffix = 0; | |
3627 | else if (!check_qword_reg ()) | |
29b0f896 AM |
3628 | return 0; |
3629 | } | |
3630 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
3631 | { | |
3632 | if (!check_word_reg ()) | |
3633 | return 0; | |
3634 | } | |
582d5edd L |
3635 | else if (i.suffix == XMMWORD_MNEM_SUFFIX) |
3636 | { | |
3637 | /* Skip if the instruction has x suffix. match_template | |
3638 | should check if it is a valid suffix. */ | |
3639 | } | |
40fb9820 | 3640 | else if (intel_syntax && i.tm.opcode_modifier.ignoresize) |
29b0f896 AM |
3641 | /* Do nothing if the instruction is going to ignore the prefix. */ |
3642 | ; | |
3643 | else | |
3644 | abort (); | |
3645 | } | |
40fb9820 | 3646 | else if (i.tm.opcode_modifier.defaultsize |
9306ca4a JB |
3647 | && !i.suffix |
3648 | /* exclude fldenv/frstor/fsave/fstenv */ | |
40fb9820 | 3649 | && i.tm.opcode_modifier.no_ssuf) |
29b0f896 AM |
3650 | { |
3651 | i.suffix = stackop_size; | |
3652 | } | |
9306ca4a JB |
3653 | else if (intel_syntax |
3654 | && !i.suffix | |
40fb9820 L |
3655 | && (i.tm.operand_types[0].bitfield.jumpabsolute |
3656 | || i.tm.opcode_modifier.jumpbyte | |
3657 | || i.tm.opcode_modifier.jumpintersegment | |
64e74474 AM |
3658 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
3659 | && i.tm.extension_opcode <= 3))) | |
9306ca4a JB |
3660 | { |
3661 | switch (flag_code) | |
3662 | { | |
3663 | case CODE_64BIT: | |
40fb9820 | 3664 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a JB |
3665 | { |
3666 | i.suffix = QWORD_MNEM_SUFFIX; | |
3667 | break; | |
3668 | } | |
3669 | case CODE_32BIT: | |
40fb9820 | 3670 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
3671 | i.suffix = LONG_MNEM_SUFFIX; |
3672 | break; | |
3673 | case CODE_16BIT: | |
40fb9820 | 3674 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
3675 | i.suffix = WORD_MNEM_SUFFIX; |
3676 | break; | |
3677 | } | |
3678 | } | |
252b5132 | 3679 | |
9306ca4a | 3680 | if (!i.suffix) |
29b0f896 | 3681 | { |
9306ca4a JB |
3682 | if (!intel_syntax) |
3683 | { | |
40fb9820 | 3684 | if (i.tm.opcode_modifier.w) |
9306ca4a | 3685 | { |
4eed87de AM |
3686 | as_bad (_("no instruction mnemonic suffix given and " |
3687 | "no register operands; can't size instruction")); | |
9306ca4a JB |
3688 | return 0; |
3689 | } | |
3690 | } | |
3691 | else | |
3692 | { | |
40fb9820 L |
3693 | unsigned int suffixes; |
3694 | ||
3695 | suffixes = !i.tm.opcode_modifier.no_bsuf; | |
3696 | if (!i.tm.opcode_modifier.no_wsuf) | |
3697 | suffixes |= 1 << 1; | |
3698 | if (!i.tm.opcode_modifier.no_lsuf) | |
3699 | suffixes |= 1 << 2; | |
fc4adea1 | 3700 | if (!i.tm.opcode_modifier.no_ldsuf) |
40fb9820 L |
3701 | suffixes |= 1 << 3; |
3702 | if (!i.tm.opcode_modifier.no_ssuf) | |
3703 | suffixes |= 1 << 4; | |
3704 | if (!i.tm.opcode_modifier.no_qsuf) | |
3705 | suffixes |= 1 << 5; | |
3706 | ||
3707 | /* There are more than suffix matches. */ | |
3708 | if (i.tm.opcode_modifier.w | |
9306ca4a | 3709 | || ((suffixes & (suffixes - 1)) |
40fb9820 L |
3710 | && !i.tm.opcode_modifier.defaultsize |
3711 | && !i.tm.opcode_modifier.ignoresize)) | |
9306ca4a JB |
3712 | { |
3713 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); | |
3714 | return 0; | |
3715 | } | |
3716 | } | |
29b0f896 | 3717 | } |
252b5132 | 3718 | |
9306ca4a JB |
3719 | /* Change the opcode based on the operand size given by i.suffix; |
3720 | We don't need to change things for byte insns. */ | |
3721 | ||
582d5edd L |
3722 | if (i.suffix |
3723 | && i.suffix != BYTE_MNEM_SUFFIX | |
3724 | && i.suffix != XMMWORD_MNEM_SUFFIX) | |
29b0f896 AM |
3725 | { |
3726 | /* It's not a byte, select word/dword operation. */ | |
40fb9820 | 3727 | if (i.tm.opcode_modifier.w) |
29b0f896 | 3728 | { |
40fb9820 | 3729 | if (i.tm.opcode_modifier.shortform) |
29b0f896 AM |
3730 | i.tm.base_opcode |= 8; |
3731 | else | |
3732 | i.tm.base_opcode |= 1; | |
3733 | } | |
0f3f3d8b | 3734 | |
29b0f896 AM |
3735 | /* Now select between word & dword operations via the operand |
3736 | size prefix, except for instructions that will ignore this | |
3737 | prefix anyway. */ | |
ca61edf2 | 3738 | if (i.tm.opcode_modifier.addrprefixop0) |
cb712a9e | 3739 | { |
ca61edf2 L |
3740 | /* The address size override prefix changes the size of the |
3741 | first operand. */ | |
40fb9820 L |
3742 | if ((flag_code == CODE_32BIT |
3743 | && i.op->regs[0].reg_type.bitfield.reg16) | |
3744 | || (flag_code != CODE_32BIT | |
3745 | && i.op->regs[0].reg_type.bitfield.reg32)) | |
cb712a9e L |
3746 | if (!add_prefix (ADDR_PREFIX_OPCODE)) |
3747 | return 0; | |
3748 | } | |
3749 | else if (i.suffix != QWORD_MNEM_SUFFIX | |
3750 | && i.suffix != LONG_DOUBLE_MNEM_SUFFIX | |
40fb9820 L |
3751 | && !i.tm.opcode_modifier.ignoresize |
3752 | && !i.tm.opcode_modifier.floatmf | |
cb712a9e L |
3753 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) |
3754 | || (flag_code == CODE_64BIT | |
40fb9820 | 3755 | && i.tm.opcode_modifier.jumpbyte))) |
24eab124 AM |
3756 | { |
3757 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 3758 | |
40fb9820 | 3759 | if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */ |
29b0f896 | 3760 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 3761 | |
29b0f896 AM |
3762 | if (!add_prefix (prefix)) |
3763 | return 0; | |
24eab124 | 3764 | } |
252b5132 | 3765 | |
29b0f896 AM |
3766 | /* Set mode64 for an operand. */ |
3767 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 3768 | && flag_code == CODE_64BIT |
40fb9820 | 3769 | && !i.tm.opcode_modifier.norex64) |
46e883c5 L |
3770 | { |
3771 | /* Special case for xchg %rax,%rax. It is NOP and doesn't | |
d9a5e5e5 L |
3772 | need rex64. cmpxchg8b is also a special case. */ |
3773 | if (! (i.operands == 2 | |
3774 | && i.tm.base_opcode == 0x90 | |
3775 | && i.tm.extension_opcode == None | |
c6fb90c8 L |
3776 | && UINTS_EQUAL (i.types [0], acc64) |
3777 | && UINTS_EQUAL (i.types [1], acc64)) | |
d9a5e5e5 L |
3778 | && ! (i.operands == 1 |
3779 | && i.tm.base_opcode == 0xfc7 | |
3780 | && i.tm.extension_opcode == 1 | |
40fb9820 L |
3781 | && !operand_type_check (i.types [0], reg) |
3782 | && operand_type_check (i.types [0], anymem))) | |
f6bee062 | 3783 | i.rex |= REX_W; |
46e883c5 | 3784 | } |
3e73aa7c | 3785 | |
29b0f896 AM |
3786 | /* Size floating point instruction. */ |
3787 | if (i.suffix == LONG_MNEM_SUFFIX) | |
40fb9820 | 3788 | if (i.tm.opcode_modifier.floatmf) |
543613e9 | 3789 | i.tm.base_opcode ^= 4; |
29b0f896 | 3790 | } |
7ecd2f8b | 3791 | |
29b0f896 AM |
3792 | return 1; |
3793 | } | |
3e73aa7c | 3794 | |
29b0f896 | 3795 | static int |
543613e9 | 3796 | check_byte_reg (void) |
29b0f896 AM |
3797 | { |
3798 | int op; | |
543613e9 | 3799 | |
29b0f896 AM |
3800 | for (op = i.operands; --op >= 0;) |
3801 | { | |
3802 | /* If this is an eight bit register, it's OK. If it's the 16 or | |
3803 | 32 bit version of an eight bit register, we will just use the | |
3804 | low portion, and that's OK too. */ | |
40fb9820 | 3805 | if (i.types[op].bitfield.reg8) |
29b0f896 AM |
3806 | continue; |
3807 | ||
ca61edf2 L |
3808 | /* Don't generate this warning if not needed. */ |
3809 | if (intel_syntax && i.tm.opcode_modifier.byteokintel) | |
29b0f896 AM |
3810 | continue; |
3811 | ||
9344ff29 L |
3812 | /* crc32 doesn't generate this warning. */ |
3813 | if (i.tm.base_opcode == 0xf20f38f0) | |
3814 | continue; | |
3815 | ||
40fb9820 L |
3816 | if ((i.types[op].bitfield.reg16 |
3817 | || i.types[op].bitfield.reg32 | |
3818 | || i.types[op].bitfield.reg64) | |
3819 | && i.op[op].regs->reg_num < 4) | |
29b0f896 AM |
3820 | { |
3821 | /* Prohibit these changes in the 64bit mode, since the | |
3822 | lowering is more complicated. */ | |
3823 | if (flag_code == CODE_64BIT | |
40fb9820 | 3824 | && !i.tm.operand_types[op].bitfield.inoutportreg) |
29b0f896 | 3825 | { |
2ca3ace5 L |
3826 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), |
3827 | register_prefix, i.op[op].regs->reg_name, | |
29b0f896 AM |
3828 | i.suffix); |
3829 | return 0; | |
3830 | } | |
3831 | #if REGISTER_WARNINGS | |
3832 | if (!quiet_warnings | |
40fb9820 | 3833 | && !i.tm.operand_types[op].bitfield.inoutportreg) |
a540244d L |
3834 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
3835 | register_prefix, | |
40fb9820 | 3836 | (i.op[op].regs + (i.types[op].bitfield.reg16 |
29b0f896 AM |
3837 | ? REGNAM_AL - REGNAM_AX |
3838 | : REGNAM_AL - REGNAM_EAX))->reg_name, | |
a540244d | 3839 | register_prefix, |
29b0f896 AM |
3840 | i.op[op].regs->reg_name, |
3841 | i.suffix); | |
3842 | #endif | |
3843 | continue; | |
3844 | } | |
3845 | /* Any other register is bad. */ | |
40fb9820 L |
3846 | if (i.types[op].bitfield.reg16 |
3847 | || i.types[op].bitfield.reg32 | |
3848 | || i.types[op].bitfield.reg64 | |
3849 | || i.types[op].bitfield.regmmx | |
3850 | || i.types[op].bitfield.regxmm | |
3851 | || i.types[op].bitfield.sreg2 | |
3852 | || i.types[op].bitfield.sreg3 | |
3853 | || i.types[op].bitfield.control | |
3854 | || i.types[op].bitfield.debug | |
3855 | || i.types[op].bitfield.test | |
3856 | || i.types[op].bitfield.floatreg | |
3857 | || i.types[op].bitfield.floatacc) | |
29b0f896 | 3858 | { |
a540244d L |
3859 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
3860 | register_prefix, | |
29b0f896 AM |
3861 | i.op[op].regs->reg_name, |
3862 | i.tm.name, | |
3863 | i.suffix); | |
3864 | return 0; | |
3865 | } | |
3866 | } | |
3867 | return 1; | |
3868 | } | |
3869 | ||
3870 | static int | |
e3bb37b5 | 3871 | check_long_reg (void) |
29b0f896 AM |
3872 | { |
3873 | int op; | |
3874 | ||
3875 | for (op = i.operands; --op >= 0;) | |
3876 | /* Reject eight bit registers, except where the template requires | |
3877 | them. (eg. movzb) */ | |
40fb9820 L |
3878 | if (i.types[op].bitfield.reg8 |
3879 | && (i.tm.operand_types[op].bitfield.reg16 | |
3880 | || i.tm.operand_types[op].bitfield.reg32 | |
3881 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 3882 | { |
a540244d L |
3883 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
3884 | register_prefix, | |
29b0f896 AM |
3885 | i.op[op].regs->reg_name, |
3886 | i.tm.name, | |
3887 | i.suffix); | |
3888 | return 0; | |
3889 | } | |
3890 | /* Warn if the e prefix on a general reg is missing. */ | |
3891 | else if ((!quiet_warnings || flag_code == CODE_64BIT) | |
40fb9820 L |
3892 | && i.types[op].bitfield.reg16 |
3893 | && (i.tm.operand_types[op].bitfield.reg32 | |
3894 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 AM |
3895 | { |
3896 | /* Prohibit these changes in the 64bit mode, since the | |
3897 | lowering is more complicated. */ | |
3898 | if (flag_code == CODE_64BIT) | |
252b5132 | 3899 | { |
2ca3ace5 L |
3900 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), |
3901 | register_prefix, i.op[op].regs->reg_name, | |
29b0f896 AM |
3902 | i.suffix); |
3903 | return 0; | |
252b5132 | 3904 | } |
29b0f896 AM |
3905 | #if REGISTER_WARNINGS |
3906 | else | |
a540244d L |
3907 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
3908 | register_prefix, | |
29b0f896 | 3909 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, |
a540244d | 3910 | register_prefix, |
29b0f896 AM |
3911 | i.op[op].regs->reg_name, |
3912 | i.suffix); | |
3913 | #endif | |
252b5132 | 3914 | } |
29b0f896 | 3915 | /* Warn if the r prefix on a general reg is missing. */ |
40fb9820 L |
3916 | else if (i.types[op].bitfield.reg64 |
3917 | && (i.tm.operand_types[op].bitfield.reg32 | |
3918 | || i.tm.operand_types[op].bitfield.acc)) | |
252b5132 | 3919 | { |
34828aad | 3920 | if (intel_syntax |
ca61edf2 | 3921 | && i.tm.opcode_modifier.toqword |
40fb9820 | 3922 | && !i.types[0].bitfield.regxmm) |
34828aad | 3923 | { |
ca61edf2 | 3924 | /* Convert to QWORD. We want REX byte. */ |
34828aad L |
3925 | i.suffix = QWORD_MNEM_SUFFIX; |
3926 | } | |
3927 | else | |
3928 | { | |
3929 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), | |
3930 | register_prefix, i.op[op].regs->reg_name, | |
3931 | i.suffix); | |
3932 | return 0; | |
3933 | } | |
29b0f896 AM |
3934 | } |
3935 | return 1; | |
3936 | } | |
252b5132 | 3937 | |
29b0f896 | 3938 | static int |
e3bb37b5 | 3939 | check_qword_reg (void) |
29b0f896 AM |
3940 | { |
3941 | int op; | |
252b5132 | 3942 | |
29b0f896 AM |
3943 | for (op = i.operands; --op >= 0; ) |
3944 | /* Reject eight bit registers, except where the template requires | |
3945 | them. (eg. movzb) */ | |
40fb9820 L |
3946 | if (i.types[op].bitfield.reg8 |
3947 | && (i.tm.operand_types[op].bitfield.reg16 | |
3948 | || i.tm.operand_types[op].bitfield.reg32 | |
3949 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 3950 | { |
a540244d L |
3951 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
3952 | register_prefix, | |
29b0f896 AM |
3953 | i.op[op].regs->reg_name, |
3954 | i.tm.name, | |
3955 | i.suffix); | |
3956 | return 0; | |
3957 | } | |
3958 | /* Warn if the e prefix on a general reg is missing. */ | |
40fb9820 L |
3959 | else if ((i.types[op].bitfield.reg16 |
3960 | || i.types[op].bitfield.reg32) | |
3961 | && (i.tm.operand_types[op].bitfield.reg32 | |
3962 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 AM |
3963 | { |
3964 | /* Prohibit these changes in the 64bit mode, since the | |
3965 | lowering is more complicated. */ | |
34828aad | 3966 | if (intel_syntax |
ca61edf2 | 3967 | && i.tm.opcode_modifier.todword |
40fb9820 | 3968 | && !i.types[0].bitfield.regxmm) |
34828aad | 3969 | { |
ca61edf2 | 3970 | /* Convert to DWORD. We don't want REX byte. */ |
34828aad L |
3971 | i.suffix = LONG_MNEM_SUFFIX; |
3972 | } | |
3973 | else | |
3974 | { | |
3975 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), | |
3976 | register_prefix, i.op[op].regs->reg_name, | |
3977 | i.suffix); | |
3978 | return 0; | |
3979 | } | |
252b5132 | 3980 | } |
29b0f896 AM |
3981 | return 1; |
3982 | } | |
252b5132 | 3983 | |
29b0f896 | 3984 | static int |
e3bb37b5 | 3985 | check_word_reg (void) |
29b0f896 AM |
3986 | { |
3987 | int op; | |
3988 | for (op = i.operands; --op >= 0;) | |
3989 | /* Reject eight bit registers, except where the template requires | |
3990 | them. (eg. movzb) */ | |
40fb9820 L |
3991 | if (i.types[op].bitfield.reg8 |
3992 | && (i.tm.operand_types[op].bitfield.reg16 | |
3993 | || i.tm.operand_types[op].bitfield.reg32 | |
3994 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 3995 | { |
a540244d L |
3996 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
3997 | register_prefix, | |
29b0f896 AM |
3998 | i.op[op].regs->reg_name, |
3999 | i.tm.name, | |
4000 | i.suffix); | |
4001 | return 0; | |
4002 | } | |
4003 | /* Warn if the e prefix on a general reg is present. */ | |
4004 | else if ((!quiet_warnings || flag_code == CODE_64BIT) | |
40fb9820 L |
4005 | && i.types[op].bitfield.reg32 |
4006 | && (i.tm.operand_types[op].bitfield.reg16 | |
4007 | || i.tm.operand_types[op].bitfield.acc)) | |
252b5132 | 4008 | { |
29b0f896 AM |
4009 | /* Prohibit these changes in the 64bit mode, since the |
4010 | lowering is more complicated. */ | |
4011 | if (flag_code == CODE_64BIT) | |
252b5132 | 4012 | { |
2ca3ace5 L |
4013 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), |
4014 | register_prefix, i.op[op].regs->reg_name, | |
29b0f896 AM |
4015 | i.suffix); |
4016 | return 0; | |
252b5132 | 4017 | } |
29b0f896 AM |
4018 | else |
4019 | #if REGISTER_WARNINGS | |
a540244d L |
4020 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
4021 | register_prefix, | |
29b0f896 | 4022 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, |
a540244d | 4023 | register_prefix, |
29b0f896 AM |
4024 | i.op[op].regs->reg_name, |
4025 | i.suffix); | |
4026 | #endif | |
4027 | } | |
4028 | return 1; | |
4029 | } | |
252b5132 | 4030 | |
29b0f896 | 4031 | static int |
40fb9820 | 4032 | update_imm (unsigned int j) |
29b0f896 | 4033 | { |
40fb9820 L |
4034 | i386_operand_type overlap; |
4035 | ||
c6fb90c8 | 4036 | overlap = operand_type_and (i.types[j], i.tm.operand_types[j]); |
40fb9820 L |
4037 | if ((overlap.bitfield.imm8 |
4038 | || overlap.bitfield.imm8s | |
4039 | || overlap.bitfield.imm16 | |
4040 | || overlap.bitfield.imm32 | |
4041 | || overlap.bitfield.imm32s | |
4042 | || overlap.bitfield.imm64) | |
c6fb90c8 L |
4043 | && !UINTS_EQUAL (overlap, imm8) |
4044 | && !UINTS_EQUAL (overlap, imm8s) | |
4045 | && !UINTS_EQUAL (overlap, imm16) | |
4046 | && !UINTS_EQUAL (overlap, imm32) | |
4047 | && !UINTS_EQUAL (overlap, imm32s) | |
4048 | && !UINTS_EQUAL (overlap, imm64)) | |
29b0f896 AM |
4049 | { |
4050 | if (i.suffix) | |
4051 | { | |
40fb9820 L |
4052 | i386_operand_type temp; |
4053 | ||
c6fb90c8 | 4054 | UINTS_CLEAR (temp); |
40fb9820 L |
4055 | if (i.suffix == BYTE_MNEM_SUFFIX) |
4056 | { | |
4057 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
4058 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
4059 | } | |
4060 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
4061 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
4062 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
4063 | { | |
4064 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
4065 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
4066 | } | |
4067 | else | |
4068 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
4069 | overlap = temp; | |
29b0f896 | 4070 | } |
c6fb90c8 L |
4071 | else if (UINTS_EQUAL (overlap, imm16_32_32s) |
4072 | || UINTS_EQUAL (overlap, imm16_32) | |
4073 | || UINTS_EQUAL (overlap, imm16_32s)) | |
29b0f896 | 4074 | { |
c6fb90c8 | 4075 | UINTS_CLEAR (overlap); |
40fb9820 L |
4076 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
4077 | overlap.bitfield.imm16 = 1; | |
4078 | else | |
4079 | overlap.bitfield.imm32s = 1; | |
29b0f896 | 4080 | } |
c6fb90c8 L |
4081 | if (!UINTS_EQUAL (overlap, imm8) |
4082 | && !UINTS_EQUAL (overlap, imm8s) | |
4083 | && !UINTS_EQUAL (overlap, imm16) | |
4084 | && !UINTS_EQUAL (overlap, imm32) | |
4085 | && !UINTS_EQUAL (overlap, imm32s) | |
4086 | && !UINTS_EQUAL (overlap, imm64)) | |
29b0f896 | 4087 | { |
4eed87de AM |
4088 | as_bad (_("no instruction mnemonic suffix given; " |
4089 | "can't determine immediate size")); | |
29b0f896 AM |
4090 | return 0; |
4091 | } | |
4092 | } | |
40fb9820 | 4093 | i.types[j] = overlap; |
29b0f896 | 4094 | |
40fb9820 L |
4095 | return 1; |
4096 | } | |
4097 | ||
4098 | static int | |
4099 | finalize_imm (void) | |
4100 | { | |
4101 | unsigned int j; | |
29b0f896 | 4102 | |
40fb9820 L |
4103 | for (j = 0; j < 2; j++) |
4104 | if (update_imm (j) == 0) | |
4105 | return 0; | |
4106 | ||
c6fb90c8 | 4107 | i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]); |
40fb9820 | 4108 | assert (operand_type_check (i.types[2], imm) == 0); |
29b0f896 AM |
4109 | |
4110 | return 1; | |
4111 | } | |
4112 | ||
85f10a01 MM |
4113 | static void |
4114 | process_drex (void) | |
4115 | { | |
5dd15031 JJ |
4116 | i.drex.modrm_reg = 0; |
4117 | i.drex.modrm_regmem = 0; | |
85f10a01 MM |
4118 | |
4119 | /* SSE5 4 operand instructions must have the destination the same as | |
4120 | one of the inputs. Figure out the destination register and cache | |
4121 | it away in the drex field, and remember which fields to use for | |
4122 | the modrm byte. */ | |
4123 | if (i.tm.opcode_modifier.drex | |
4124 | && i.tm.opcode_modifier.drexv | |
4125 | && i.operands == 4) | |
4126 | { | |
4127 | i.tm.extension_opcode = None; | |
4128 | ||
4129 | /* Case 1: 4 operand insn, dest = src1, src3 = register. */ | |
4130 | if (i.types[0].bitfield.regxmm != 0 | |
4131 | && i.types[1].bitfield.regxmm != 0 | |
4132 | && i.types[2].bitfield.regxmm != 0 | |
4133 | && i.types[3].bitfield.regxmm != 0 | |
4134 | && i.op[0].regs->reg_num == i.op[3].regs->reg_num | |
4135 | && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags) | |
4136 | { | |
4137 | /* Clear the arguments that are stored in drex. */ | |
4138 | UINTS_CLEAR (i.types[0]); | |
4139 | UINTS_CLEAR (i.types[3]); | |
4140 | i.reg_operands -= 2; | |
4141 | ||
4142 | /* There are two different ways to encode a 4 operand | |
4143 | instruction with all registers that uses OC1 set to | |
4144 | 0 or 1. Favor setting OC1 to 0 since this mimics the | |
4145 | actions of other SSE5 assemblers. Use modrm encoding 2 | |
4146 | for register/register. Include the high order bit that | |
4147 | is normally stored in the REX byte in the register | |
4148 | field. */ | |
4149 | i.tm.extension_opcode = DREX_X1_XMEM_X2_X1; | |
4150 | i.drex.modrm_reg = 2; | |
4151 | i.drex.modrm_regmem = 1; | |
4152 | i.drex.reg = (i.op[3].regs->reg_num | |
4153 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4154 | } | |
4155 | ||
4156 | /* Case 2: 4 operand insn, dest = src1, src3 = memory. */ | |
4157 | else if (i.types[0].bitfield.regxmm != 0 | |
4158 | && i.types[1].bitfield.regxmm != 0 | |
4159 | && (i.types[2].bitfield.regxmm | |
4160 | || operand_type_check (i.types[2], anymem)) | |
4161 | && i.types[3].bitfield.regxmm != 0 | |
4162 | && i.op[0].regs->reg_num == i.op[3].regs->reg_num | |
4163 | && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags) | |
4164 | { | |
4165 | /* clear the arguments that are stored in drex */ | |
4166 | UINTS_CLEAR (i.types[0]); | |
4167 | UINTS_CLEAR (i.types[3]); | |
4168 | i.reg_operands -= 2; | |
4169 | ||
4170 | /* Specify the modrm encoding for memory addressing. Include | |
4171 | the high order bit that is normally stored in the REX byte | |
4172 | in the register field. */ | |
4173 | i.tm.extension_opcode = DREX_X1_X2_XMEM_X1; | |
4174 | i.drex.modrm_reg = 1; | |
4175 | i.drex.modrm_regmem = 2; | |
4176 | i.drex.reg = (i.op[3].regs->reg_num | |
4177 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4178 | } | |
4179 | ||
4180 | /* Case 3: 4 operand insn, dest = src1, src2 = memory. */ | |
4181 | else if (i.types[0].bitfield.regxmm != 0 | |
4182 | && operand_type_check (i.types[1], anymem) != 0 | |
4183 | && i.types[2].bitfield.regxmm != 0 | |
4184 | && i.types[3].bitfield.regxmm != 0 | |
4185 | && i.op[0].regs->reg_num == i.op[3].regs->reg_num | |
4186 | && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags) | |
4187 | { | |
4188 | /* Clear the arguments that are stored in drex. */ | |
4189 | UINTS_CLEAR (i.types[0]); | |
4190 | UINTS_CLEAR (i.types[3]); | |
4191 | i.reg_operands -= 2; | |
4192 | ||
4193 | /* Specify the modrm encoding for memory addressing. Include | |
4194 | the high order bit that is normally stored in the REX byte | |
4195 | in the register field. */ | |
4196 | i.tm.extension_opcode = DREX_X1_XMEM_X2_X1; | |
4197 | i.drex.modrm_reg = 2; | |
4198 | i.drex.modrm_regmem = 1; | |
4199 | i.drex.reg = (i.op[3].regs->reg_num | |
4200 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4201 | } | |
4202 | ||
4203 | /* Case 4: 4 operand insn, dest = src3, src2 = register. */ | |
4204 | else if (i.types[0].bitfield.regxmm != 0 | |
4205 | && i.types[1].bitfield.regxmm != 0 | |
4206 | && i.types[2].bitfield.regxmm != 0 | |
4207 | && i.types[3].bitfield.regxmm != 0 | |
4208 | && i.op[2].regs->reg_num == i.op[3].regs->reg_num | |
4209 | && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags) | |
4210 | { | |
4211 | /* clear the arguments that are stored in drex */ | |
4212 | UINTS_CLEAR (i.types[2]); | |
4213 | UINTS_CLEAR (i.types[3]); | |
4214 | i.reg_operands -= 2; | |
4215 | ||
4216 | /* There are two different ways to encode a 4 operand | |
4217 | instruction with all registers that uses OC1 set to | |
4218 | 0 or 1. Favor setting OC1 to 0 since this mimics the | |
4219 | actions of other SSE5 assemblers. Use modrm encoding | |
4220 | 2 for register/register. Include the high order bit that | |
4221 | is normally stored in the REX byte in the register | |
4222 | field. */ | |
4223 | i.tm.extension_opcode = DREX_XMEM_X1_X2_X2; | |
4224 | i.drex.modrm_reg = 1; | |
4225 | i.drex.modrm_regmem = 0; | |
4226 | ||
4227 | /* Remember the register, including the upper bits */ | |
4228 | i.drex.reg = (i.op[3].regs->reg_num | |
4229 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4230 | } | |
4231 | ||
4232 | /* Case 5: 4 operand insn, dest = src3, src2 = memory. */ | |
4233 | else if (i.types[0].bitfield.regxmm != 0 | |
4234 | && (i.types[1].bitfield.regxmm | |
4235 | || operand_type_check (i.types[1], anymem)) | |
4236 | && i.types[2].bitfield.regxmm != 0 | |
4237 | && i.types[3].bitfield.regxmm != 0 | |
4238 | && i.op[2].regs->reg_num == i.op[3].regs->reg_num | |
4239 | && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags) | |
4240 | { | |
4241 | /* Clear the arguments that are stored in drex. */ | |
4242 | UINTS_CLEAR (i.types[2]); | |
4243 | UINTS_CLEAR (i.types[3]); | |
4244 | i.reg_operands -= 2; | |
4245 | ||
4246 | /* Specify the modrm encoding and remember the register | |
4247 | including the bits normally stored in the REX byte. */ | |
4248 | i.tm.extension_opcode = DREX_X1_XMEM_X2_X2; | |
4249 | i.drex.modrm_reg = 0; | |
4250 | i.drex.modrm_regmem = 1; | |
4251 | i.drex.reg = (i.op[3].regs->reg_num | |
4252 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4253 | } | |
4254 | ||
4255 | /* Case 6: 4 operand insn, dest = src3, src1 = memory. */ | |
4256 | else if (operand_type_check (i.types[0], anymem) != 0 | |
4257 | && i.types[1].bitfield.regxmm != 0 | |
4258 | && i.types[2].bitfield.regxmm != 0 | |
4259 | && i.types[3].bitfield.regxmm != 0 | |
4260 | && i.op[2].regs->reg_num == i.op[3].regs->reg_num | |
4261 | && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags) | |
4262 | { | |
4263 | /* clear the arguments that are stored in drex */ | |
4264 | UINTS_CLEAR (i.types[2]); | |
4265 | UINTS_CLEAR (i.types[3]); | |
4266 | i.reg_operands -= 2; | |
4267 | ||
4268 | /* Specify the modrm encoding and remember the register | |
4269 | including the bits normally stored in the REX byte. */ | |
4270 | i.tm.extension_opcode = DREX_XMEM_X1_X2_X2; | |
4271 | i.drex.modrm_reg = 1; | |
4272 | i.drex.modrm_regmem = 0; | |
4273 | i.drex.reg = (i.op[3].regs->reg_num | |
4274 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4275 | } | |
4276 | ||
4277 | else | |
4278 | as_bad (_("Incorrect operands for the '%s' instruction"), | |
4279 | i.tm.name); | |
4280 | } | |
4281 | ||
4282 | /* SSE5 instructions with the DREX byte where the only memory operand | |
4283 | is in the 2nd argument, and the first and last xmm register must | |
4284 | match, and is encoded in the DREX byte. */ | |
4285 | else if (i.tm.opcode_modifier.drex | |
4286 | && !i.tm.opcode_modifier.drexv | |
4287 | && i.operands == 4) | |
4288 | { | |
4289 | /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */ | |
4290 | if (i.types[0].bitfield.regxmm != 0 | |
4291 | && (i.types[1].bitfield.regxmm | |
4292 | || operand_type_check(i.types[1], anymem)) | |
4293 | && i.types[2].bitfield.regxmm != 0 | |
4294 | && i.types[3].bitfield.regxmm != 0 | |
4295 | && i.op[0].regs->reg_num == i.op[3].regs->reg_num | |
4296 | && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags) | |
4297 | { | |
4298 | /* clear the arguments that are stored in drex */ | |
4299 | UINTS_CLEAR (i.types[0]); | |
4300 | UINTS_CLEAR (i.types[3]); | |
4301 | i.reg_operands -= 2; | |
4302 | ||
4303 | /* Specify the modrm encoding and remember the register | |
4304 | including the high bit normally stored in the REX | |
4305 | byte. */ | |
4306 | i.drex.modrm_reg = 2; | |
4307 | i.drex.modrm_regmem = 1; | |
4308 | i.drex.reg = (i.op[3].regs->reg_num | |
4309 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4310 | } | |
4311 | ||
4312 | else | |
4313 | as_bad (_("Incorrect operands for the '%s' instruction"), | |
4314 | i.tm.name); | |
4315 | } | |
4316 | ||
4317 | /* SSE5 3 operand instructions that the result is a register, being | |
4318 | either operand can be a memory operand, using OC0 to note which | |
4319 | one is the memory. */ | |
4320 | else if (i.tm.opcode_modifier.drex | |
4321 | && i.tm.opcode_modifier.drexv | |
4322 | && i.operands == 3) | |
4323 | { | |
4324 | i.tm.extension_opcode = None; | |
4325 | ||
4326 | /* Case 1: 3 operand insn, src1 = register. */ | |
4327 | if (i.types[0].bitfield.regxmm != 0 | |
4328 | && i.types[1].bitfield.regxmm != 0 | |
4329 | && i.types[2].bitfield.regxmm != 0) | |
4330 | { | |
4331 | /* Clear the arguments that are stored in drex. */ | |
4332 | UINTS_CLEAR (i.types[2]); | |
4333 | i.reg_operands--; | |
4334 | ||
4335 | /* Specify the modrm encoding and remember the register | |
4336 | including the high bit normally stored in the REX byte. */ | |
4337 | i.tm.extension_opcode = DREX_XMEM_X1_X2; | |
4338 | i.drex.modrm_reg = 1; | |
4339 | i.drex.modrm_regmem = 0; | |
4340 | i.drex.reg = (i.op[2].regs->reg_num | |
4341 | + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0)); | |
4342 | } | |
4343 | ||
4344 | /* Case 2: 3 operand insn, src1 = memory. */ | |
4345 | else if (operand_type_check (i.types[0], anymem) != 0 | |
4346 | && i.types[1].bitfield.regxmm != 0 | |
4347 | && i.types[2].bitfield.regxmm != 0) | |
4348 | { | |
4349 | /* Clear the arguments that are stored in drex. */ | |
4350 | UINTS_CLEAR (i.types[2]); | |
4351 | i.reg_operands--; | |
4352 | ||
4353 | /* Specify the modrm encoding and remember the register | |
4354 | including the high bit normally stored in the REX | |
4355 | byte. */ | |
4356 | i.tm.extension_opcode = DREX_XMEM_X1_X2; | |
4357 | i.drex.modrm_reg = 1; | |
4358 | i.drex.modrm_regmem = 0; | |
4359 | i.drex.reg = (i.op[2].regs->reg_num | |
4360 | + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0)); | |
4361 | } | |
4362 | ||
4363 | /* Case 3: 3 operand insn, src2 = memory. */ | |
4364 | else if (i.types[0].bitfield.regxmm != 0 | |
4365 | && operand_type_check (i.types[1], anymem) != 0 | |
4366 | && i.types[2].bitfield.regxmm != 0) | |
4367 | { | |
4368 | /* Clear the arguments that are stored in drex. */ | |
4369 | UINTS_CLEAR (i.types[2]); | |
4370 | i.reg_operands--; | |
4371 | ||
4372 | /* Specify the modrm encoding and remember the register | |
4373 | including the high bit normally stored in the REX byte. */ | |
4374 | i.tm.extension_opcode = DREX_X1_XMEM_X2; | |
4375 | i.drex.modrm_reg = 0; | |
4376 | i.drex.modrm_regmem = 1; | |
4377 | i.drex.reg = (i.op[2].regs->reg_num | |
4378 | + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0)); | |
4379 | } | |
4380 | ||
4381 | else | |
4382 | as_bad (_("Incorrect operands for the '%s' instruction"), | |
4383 | i.tm.name); | |
4384 | } | |
4385 | ||
4386 | /* SSE5 4 operand instructions that are the comparison instructions | |
4387 | where the first operand is the immediate value of the comparison | |
4388 | to be done. */ | |
4389 | else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4) | |
4390 | { | |
4391 | /* Case 1: 4 operand insn, src1 = reg/memory. */ | |
4392 | if (operand_type_check (i.types[0], imm) != 0 | |
4393 | && (i.types[1].bitfield.regxmm | |
4394 | || operand_type_check (i.types[1], anymem)) | |
4395 | && i.types[2].bitfield.regxmm != 0 | |
4396 | && i.types[3].bitfield.regxmm != 0) | |
4397 | { | |
4398 | /* clear the arguments that are stored in drex */ | |
4399 | UINTS_CLEAR (i.types[3]); | |
4400 | i.reg_operands--; | |
4401 | ||
4402 | /* Specify the modrm encoding and remember the register | |
4403 | including the high bit normally stored in the REX byte. */ | |
4404 | i.drex.modrm_reg = 2; | |
4405 | i.drex.modrm_regmem = 1; | |
4406 | i.drex.reg = (i.op[3].regs->reg_num | |
4407 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4408 | } | |
4409 | ||
4410 | /* Case 2: 3 operand insn with ImmExt that places the | |
4411 | opcode_extension as an immediate argument. This is used for | |
4412 | all of the varients of comparison that supplies the appropriate | |
4413 | value as part of the instruction. */ | |
4414 | else if ((i.types[0].bitfield.regxmm | |
4415 | || operand_type_check (i.types[0], anymem)) | |
4416 | && i.types[1].bitfield.regxmm != 0 | |
4417 | && i.types[2].bitfield.regxmm != 0 | |
4418 | && operand_type_check (i.types[3], imm) != 0) | |
4419 | { | |
4420 | /* clear the arguments that are stored in drex */ | |
4421 | UINTS_CLEAR (i.types[2]); | |
4422 | i.reg_operands--; | |
4423 | ||
4424 | /* Specify the modrm encoding and remember the register | |
4425 | including the high bit normally stored in the REX byte. */ | |
4426 | i.drex.modrm_reg = 1; | |
4427 | i.drex.modrm_regmem = 0; | |
4428 | i.drex.reg = (i.op[2].regs->reg_num | |
4429 | + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0)); | |
4430 | } | |
4431 | ||
4432 | else | |
4433 | as_bad (_("Incorrect operands for the '%s' instruction"), | |
4434 | i.tm.name); | |
4435 | } | |
4436 | ||
4437 | else if (i.tm.opcode_modifier.drex | |
4438 | || i.tm.opcode_modifier.drexv | |
4439 | || i.tm.opcode_modifier.drexc) | |
4440 | as_bad (_("Internal error for the '%s' instruction"), i.tm.name); | |
4441 | } | |
4442 | ||
29b0f896 | 4443 | static int |
e3bb37b5 | 4444 | process_operands (void) |
29b0f896 AM |
4445 | { |
4446 | /* Default segment register this instruction will use for memory | |
4447 | accesses. 0 means unknown. This is only for optimizing out | |
4448 | unnecessary segment overrides. */ | |
4449 | const seg_entry *default_seg = 0; | |
4450 | ||
85f10a01 MM |
4451 | /* Handle all of the DREX munging that SSE5 needs. */ |
4452 | if (i.tm.opcode_modifier.drex | |
4453 | || i.tm.opcode_modifier.drexv | |
4454 | || i.tm.opcode_modifier.drexc) | |
4455 | process_drex (); | |
4456 | ||
e2ec9d29 | 4457 | if (i.tm.opcode_modifier.firstxmm0) |
29b0f896 | 4458 | { |
9fcfb3d7 L |
4459 | unsigned int j; |
4460 | ||
e2ec9d29 L |
4461 | /* The first operand is implicit and must be xmm0. */ |
4462 | assert (i.reg_operands && UINTS_EQUAL (i.types[0], regxmm)); | |
4463 | if (i.op[0].regs->reg_num != 0) | |
4464 | { | |
4465 | if (intel_syntax) | |
4466 | as_bad (_("the last operand of `%s' must be `%sxmm0'"), | |
4467 | i.tm.name, register_prefix); | |
4468 | else | |
4469 | as_bad (_("the first operand of `%s' must be `%sxmm0'"), | |
4470 | i.tm.name, register_prefix); | |
4471 | return 0; | |
4472 | } | |
9fcfb3d7 L |
4473 | |
4474 | for (j = 1; j < i.operands; j++) | |
4475 | { | |
4476 | i.op[j - 1] = i.op[j]; | |
4477 | i.types[j - 1] = i.types[j]; | |
4478 | ||
4479 | /* We need to adjust fields in i.tm since they are used by | |
4480 | build_modrm_byte. */ | |
4481 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
4482 | } | |
4483 | ||
e2ec9d29 L |
4484 | i.operands--; |
4485 | i.reg_operands--; | |
e2ec9d29 L |
4486 | i.tm.operands--; |
4487 | } | |
4488 | else if (i.tm.opcode_modifier.regkludge) | |
4489 | { | |
4490 | /* The imul $imm, %reg instruction is converted into | |
4491 | imul $imm, %reg, %reg, and the clr %reg instruction | |
4492 | is converted into xor %reg, %reg. */ | |
4493 | ||
4494 | unsigned int first_reg_op; | |
4495 | ||
4496 | if (operand_type_check (i.types[0], reg)) | |
4497 | first_reg_op = 0; | |
4498 | else | |
4499 | first_reg_op = 1; | |
4500 | /* Pretend we saw the extra register operand. */ | |
4501 | assert (i.reg_operands == 1 | |
4502 | && i.op[first_reg_op + 1].regs == 0); | |
4503 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; | |
4504 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
4505 | i.operands++; | |
4506 | i.reg_operands++; | |
29b0f896 AM |
4507 | } |
4508 | ||
40fb9820 | 4509 | if (i.tm.opcode_modifier.shortform) |
29b0f896 | 4510 | { |
40fb9820 L |
4511 | if (i.types[0].bitfield.sreg2 |
4512 | || i.types[0].bitfield.sreg3) | |
29b0f896 | 4513 | { |
4eed87de AM |
4514 | if (i.tm.base_opcode == POP_SEG_SHORT |
4515 | && i.op[0].regs->reg_num == 1) | |
29b0f896 | 4516 | { |
4eed87de AM |
4517 | as_bad (_("you can't `pop %%cs'")); |
4518 | return 0; | |
29b0f896 | 4519 | } |
4eed87de AM |
4520 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
4521 | if ((i.op[0].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 4522 | i.rex |= REX_B; |
4eed87de AM |
4523 | } |
4524 | else | |
4525 | { | |
85f10a01 MM |
4526 | /* The register or float register operand is in operand |
4527 | 0 or 1. */ | |
40fb9820 L |
4528 | unsigned int op; |
4529 | ||
4530 | if (i.types[0].bitfield.floatreg | |
4531 | || operand_type_check (i.types[0], reg)) | |
4532 | op = 0; | |
4533 | else | |
4534 | op = 1; | |
4eed87de AM |
4535 | /* Register goes in low 3 bits of opcode. */ |
4536 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
4537 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 4538 | i.rex |= REX_B; |
40fb9820 | 4539 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 | 4540 | { |
4eed87de AM |
4541 | /* Warn about some common errors, but press on regardless. |
4542 | The first case can be generated by gcc (<= 2.8.1). */ | |
4543 | if (i.operands == 2) | |
4544 | { | |
4545 | /* Reversed arguments on faddp, fsubp, etc. */ | |
a540244d L |
4546 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, |
4547 | register_prefix, i.op[1].regs->reg_name, | |
4548 | register_prefix, i.op[0].regs->reg_name); | |
4eed87de AM |
4549 | } |
4550 | else | |
4551 | { | |
4552 | /* Extraneous `l' suffix on fp insn. */ | |
a540244d L |
4553 | as_warn (_("translating to `%s %s%s'"), i.tm.name, |
4554 | register_prefix, i.op[0].regs->reg_name); | |
4eed87de | 4555 | } |
29b0f896 AM |
4556 | } |
4557 | } | |
4558 | } | |
40fb9820 | 4559 | else if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
4560 | { |
4561 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
4562 | must be put into the modrm byte). Now, we make the modrm and |
4563 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
4564 | |
4565 | default_seg = build_modrm_byte (); | |
4566 | } | |
8a2ed489 | 4567 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
29b0f896 AM |
4568 | { |
4569 | default_seg = &ds; | |
4570 | } | |
40fb9820 | 4571 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
4572 | { |
4573 | /* For the string instructions that allow a segment override | |
4574 | on one of their operands, the default segment is ds. */ | |
4575 | default_seg = &ds; | |
4576 | } | |
4577 | ||
75178d9d L |
4578 | if (i.tm.base_opcode == 0x8d /* lea */ |
4579 | && i.seg[0] | |
4580 | && !quiet_warnings) | |
30123838 | 4581 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); |
52271982 AM |
4582 | |
4583 | /* If a segment was explicitly specified, and the specified segment | |
4584 | is not the default, use an opcode prefix to select it. If we | |
4585 | never figured out what the default segment is, then default_seg | |
4586 | will be zero at this point, and the specified segment prefix will | |
4587 | always be used. */ | |
29b0f896 AM |
4588 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
4589 | { | |
4590 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
4591 | return 0; | |
4592 | } | |
4593 | return 1; | |
4594 | } | |
4595 | ||
4596 | static const seg_entry * | |
e3bb37b5 | 4597 | build_modrm_byte (void) |
29b0f896 AM |
4598 | { |
4599 | const seg_entry *default_seg = 0; | |
4600 | ||
85f10a01 MM |
4601 | /* SSE5 4 operand instructions are encoded in such a way that one of |
4602 | the inputs must match the destination register. Process_drex hides | |
4603 | the 3rd argument in the drex field, so that by the time we get | |
4604 | here, it looks to GAS as if this is a 2 operand instruction. */ | |
4605 | if ((i.tm.opcode_modifier.drex | |
4606 | || i.tm.opcode_modifier.drexv | |
b5016f89 | 4607 | || i.tm.opcode_modifier.drexc) |
85f10a01 MM |
4608 | && i.reg_operands == 2) |
4609 | { | |
4610 | const reg_entry *reg = i.op[i.drex.modrm_reg].regs; | |
4611 | const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs; | |
4612 | ||
4613 | i.rm.reg = reg->reg_num; | |
4614 | i.rm.regmem = regmem->reg_num; | |
4615 | i.rm.mode = 3; | |
4616 | if ((reg->reg_flags & RegRex) != 0) | |
4617 | i.rex |= REX_R; | |
4618 | if ((regmem->reg_flags & RegRex) != 0) | |
4619 | i.rex |= REX_B; | |
4620 | } | |
4621 | ||
29b0f896 AM |
4622 | /* i.reg_operands MUST be the number of real register operands; |
4623 | implicit registers do not count. */ | |
85f10a01 | 4624 | else if (i.reg_operands == 2) |
29b0f896 AM |
4625 | { |
4626 | unsigned int source, dest; | |
cab737b9 L |
4627 | |
4628 | switch (i.operands) | |
4629 | { | |
4630 | case 2: | |
4631 | source = 0; | |
4632 | break; | |
4633 | case 3: | |
c81128dc L |
4634 | /* When there are 3 operands, one of them may be immediate, |
4635 | which may be the first or the last operand. Otherwise, | |
4636 | the first operand must be shift count register (cl). */ | |
4637 | assert (i.imm_operands == 1 | |
4638 | || (i.imm_operands == 0 | |
40fb9820 L |
4639 | && i.types[0].bitfield.shiftcount)); |
4640 | if (operand_type_check (i.types[0], imm) | |
4641 | || i.types[0].bitfield.shiftcount) | |
4642 | source = 1; | |
4643 | else | |
4644 | source = 0; | |
cab737b9 L |
4645 | break; |
4646 | case 4: | |
368d64cc L |
4647 | /* When there are 4 operands, the first two must be 8bit |
4648 | immediate operands. The source operand will be the 3rd | |
4649 | one. */ | |
cab737b9 | 4650 | assert (i.imm_operands == 2 |
368d64cc L |
4651 | && i.types[0].bitfield.imm8 |
4652 | && i.types[1].bitfield.imm8); | |
cab737b9 L |
4653 | source = 2; |
4654 | break; | |
4655 | default: | |
4656 | abort (); | |
4657 | } | |
4658 | ||
29b0f896 AM |
4659 | dest = source + 1; |
4660 | ||
4661 | i.rm.mode = 3; | |
4662 | /* One of the register operands will be encoded in the i.tm.reg | |
4663 | field, the other in the combined i.tm.mode and i.tm.regmem | |
4664 | fields. If no form of this instruction supports a memory | |
4665 | destination operand, then we assume the source operand may | |
4666 | sometimes be a memory operand and so we need to store the | |
4667 | destination in the i.rm.reg field. */ | |
40fb9820 L |
4668 | if (!i.tm.operand_types[dest].bitfield.regmem |
4669 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) | |
29b0f896 AM |
4670 | { |
4671 | i.rm.reg = i.op[dest].regs->reg_num; | |
4672 | i.rm.regmem = i.op[source].regs->reg_num; | |
4673 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 4674 | i.rex |= REX_R; |
29b0f896 | 4675 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 4676 | i.rex |= REX_B; |
29b0f896 AM |
4677 | } |
4678 | else | |
4679 | { | |
4680 | i.rm.reg = i.op[source].regs->reg_num; | |
4681 | i.rm.regmem = i.op[dest].regs->reg_num; | |
4682 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 4683 | i.rex |= REX_B; |
29b0f896 | 4684 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 4685 | i.rex |= REX_R; |
29b0f896 | 4686 | } |
161a04f6 | 4687 | if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B))) |
c4a530c5 | 4688 | { |
40fb9820 L |
4689 | if (!i.types[0].bitfield.control |
4690 | && !i.types[1].bitfield.control) | |
c4a530c5 | 4691 | abort (); |
161a04f6 | 4692 | i.rex &= ~(REX_R | REX_B); |
c4a530c5 JB |
4693 | add_prefix (LOCK_PREFIX_OPCODE); |
4694 | } | |
29b0f896 AM |
4695 | } |
4696 | else | |
4697 | { /* If it's not 2 reg operands... */ | |
4698 | if (i.mem_operands) | |
4699 | { | |
4700 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 4701 | unsigned int op; |
4eed87de | 4702 | |
85f10a01 MM |
4703 | /* This has been precalculated for SSE5 instructions |
4704 | that have a DREX field earlier in process_drex. */ | |
b5016f89 L |
4705 | if (i.tm.opcode_modifier.drex |
4706 | || i.tm.opcode_modifier.drexv | |
4707 | || i.tm.opcode_modifier.drexc) | |
85f10a01 MM |
4708 | op = i.drex.modrm_regmem; |
4709 | else | |
4710 | { | |
c0209578 L |
4711 | for (op = 0; op < i.operands; op++) |
4712 | if (operand_type_check (i.types[op], anymem)) | |
4713 | break; | |
4714 | assert (op < i.operands); | |
85f10a01 | 4715 | } |
29b0f896 AM |
4716 | |
4717 | default_seg = &ds; | |
4718 | ||
4719 | if (i.base_reg == 0) | |
4720 | { | |
4721 | i.rm.mode = 0; | |
4722 | if (!i.disp_operands) | |
4723 | fake_zero_displacement = 1; | |
4724 | if (i.index_reg == 0) | |
4725 | { | |
4726 | /* Operand is just <disp> */ | |
20f0a1fc | 4727 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
4728 | { |
4729 | /* 64bit mode overwrites the 32bit absolute | |
4730 | addressing by RIP relative addressing and | |
4731 | absolute addressing is encoded by one of the | |
4732 | redundant SIB forms. */ | |
4733 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
4734 | i.sib.base = NO_BASE_REGISTER; | |
4735 | i.sib.index = NO_INDEX_REGISTER; | |
fc225355 | 4736 | i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) |
40fb9820 | 4737 | ? disp32s : disp32); |
20f0a1fc | 4738 | } |
fc225355 L |
4739 | else if ((flag_code == CODE_16BIT) |
4740 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
4741 | { |
4742 | i.rm.regmem = NO_BASE_REGISTER_16; | |
40fb9820 | 4743 | i.types[op] = disp16; |
20f0a1fc NC |
4744 | } |
4745 | else | |
4746 | { | |
4747 | i.rm.regmem = NO_BASE_REGISTER; | |
40fb9820 | 4748 | i.types[op] = disp32; |
29b0f896 AM |
4749 | } |
4750 | } | |
4751 | else /* !i.base_reg && i.index_reg */ | |
4752 | { | |
db51cc60 L |
4753 | if (i.index_reg->reg_num == RegEiz |
4754 | || i.index_reg->reg_num == RegRiz) | |
4755 | i.sib.index = NO_INDEX_REGISTER; | |
4756 | else | |
4757 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
4758 | i.sib.base = NO_BASE_REGISTER; |
4759 | i.sib.scale = i.log2_scale_factor; | |
4760 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
40fb9820 L |
4761 | i.types[op].bitfield.disp8 = 0; |
4762 | i.types[op].bitfield.disp16 = 0; | |
4763 | i.types[op].bitfield.disp64 = 0; | |
29b0f896 | 4764 | if (flag_code != CODE_64BIT) |
40fb9820 L |
4765 | { |
4766 | /* Must be 32 bit */ | |
4767 | i.types[op].bitfield.disp32 = 1; | |
4768 | i.types[op].bitfield.disp32s = 0; | |
4769 | } | |
29b0f896 | 4770 | else |
40fb9820 L |
4771 | { |
4772 | i.types[op].bitfield.disp32 = 0; | |
4773 | i.types[op].bitfield.disp32s = 1; | |
4774 | } | |
29b0f896 | 4775 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 4776 | i.rex |= REX_X; |
29b0f896 AM |
4777 | } |
4778 | } | |
4779 | /* RIP addressing for 64bit mode. */ | |
9a04903e JB |
4780 | else if (i.base_reg->reg_num == RegRip || |
4781 | i.base_reg->reg_num == RegEip) | |
29b0f896 AM |
4782 | { |
4783 | i.rm.regmem = NO_BASE_REGISTER; | |
40fb9820 L |
4784 | i.types[op].bitfield.disp8 = 0; |
4785 | i.types[op].bitfield.disp16 = 0; | |
4786 | i.types[op].bitfield.disp32 = 0; | |
4787 | i.types[op].bitfield.disp32s = 1; | |
4788 | i.types[op].bitfield.disp64 = 0; | |
71903a11 | 4789 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
4790 | if (! i.disp_operands) |
4791 | fake_zero_displacement = 1; | |
29b0f896 | 4792 | } |
40fb9820 | 4793 | else if (i.base_reg->reg_type.bitfield.reg16) |
29b0f896 AM |
4794 | { |
4795 | switch (i.base_reg->reg_num) | |
4796 | { | |
4797 | case 3: /* (%bx) */ | |
4798 | if (i.index_reg == 0) | |
4799 | i.rm.regmem = 7; | |
4800 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
4801 | i.rm.regmem = i.index_reg->reg_num - 6; | |
4802 | break; | |
4803 | case 5: /* (%bp) */ | |
4804 | default_seg = &ss; | |
4805 | if (i.index_reg == 0) | |
4806 | { | |
4807 | i.rm.regmem = 6; | |
40fb9820 | 4808 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
4809 | { |
4810 | /* fake (%bp) into 0(%bp) */ | |
40fb9820 | 4811 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 4812 | fake_zero_displacement = 1; |
29b0f896 AM |
4813 | } |
4814 | } | |
4815 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
4816 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
4817 | break; | |
4818 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
4819 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
4820 | } | |
4821 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
4822 | } | |
4823 | else /* i.base_reg and 32/64 bit mode */ | |
4824 | { | |
4825 | if (flag_code == CODE_64BIT | |
40fb9820 L |
4826 | && operand_type_check (i.types[op], disp)) |
4827 | { | |
4828 | i386_operand_type temp; | |
c6fb90c8 | 4829 | UINTS_CLEAR (temp); |
40fb9820 L |
4830 | temp.bitfield.disp8 = i.types[op].bitfield.disp8; |
4831 | i.types[op] = temp; | |
4832 | if (i.prefix[ADDR_PREFIX] == 0) | |
4833 | i.types[op].bitfield.disp32s = 1; | |
4834 | else | |
4835 | i.types[op].bitfield.disp32 = 1; | |
4836 | } | |
20f0a1fc | 4837 | |
29b0f896 AM |
4838 | i.rm.regmem = i.base_reg->reg_num; |
4839 | if ((i.base_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 4840 | i.rex |= REX_B; |
29b0f896 AM |
4841 | i.sib.base = i.base_reg->reg_num; |
4842 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
4843 | complications. */ | |
4844 | if ((i.base_reg->reg_num & 7) == EBP_REG_NUM) | |
4845 | { | |
4846 | default_seg = &ss; | |
4847 | if (i.disp_operands == 0) | |
4848 | { | |
4849 | fake_zero_displacement = 1; | |
40fb9820 | 4850 | i.types[op].bitfield.disp8 = 1; |
29b0f896 AM |
4851 | } |
4852 | } | |
4853 | else if (i.base_reg->reg_num == ESP_REG_NUM) | |
4854 | { | |
4855 | default_seg = &ss; | |
4856 | } | |
4857 | i.sib.scale = i.log2_scale_factor; | |
4858 | if (i.index_reg == 0) | |
4859 | { | |
4860 | /* <disp>(%esp) becomes two byte modrm with no index | |
4861 | register. We've already stored the code for esp | |
4862 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
4863 | Any base register besides %esp will not use the | |
4864 | extra modrm byte. */ | |
4865 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 AM |
4866 | } |
4867 | else | |
4868 | { | |
db51cc60 L |
4869 | if (i.index_reg->reg_num == RegEiz |
4870 | || i.index_reg->reg_num == RegRiz) | |
4871 | i.sib.index = NO_INDEX_REGISTER; | |
4872 | else | |
4873 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
4874 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
4875 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 4876 | i.rex |= REX_X; |
29b0f896 | 4877 | } |
67a4f2b7 AO |
4878 | |
4879 | if (i.disp_operands | |
4880 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
4881 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
4882 | i.rm.mode = 0; | |
4883 | else | |
4884 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
29b0f896 | 4885 | } |
252b5132 | 4886 | |
29b0f896 AM |
4887 | if (fake_zero_displacement) |
4888 | { | |
4889 | /* Fakes a zero displacement assuming that i.types[op] | |
4890 | holds the correct displacement size. */ | |
4891 | expressionS *exp; | |
4892 | ||
4893 | assert (i.op[op].disps == 0); | |
4894 | exp = &disp_expressions[i.disp_operands++]; | |
4895 | i.op[op].disps = exp; | |
4896 | exp->X_op = O_constant; | |
4897 | exp->X_add_number = 0; | |
4898 | exp->X_add_symbol = (symbolS *) 0; | |
4899 | exp->X_op_symbol = (symbolS *) 0; | |
4900 | } | |
4901 | } | |
252b5132 | 4902 | |
29b0f896 AM |
4903 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
4904 | (if any) based on i.tm.extension_opcode. Again, we must be | |
4905 | careful to make sure that segment/control/debug/test/MMX | |
4906 | registers are coded into the i.rm.reg field. */ | |
4907 | if (i.reg_operands) | |
4908 | { | |
99018f42 L |
4909 | unsigned int op; |
4910 | ||
85f10a01 MM |
4911 | /* This has been precalculated for SSE5 instructions |
4912 | that have a DREX field earlier in process_drex. */ | |
b5016f89 L |
4913 | if (i.tm.opcode_modifier.drex |
4914 | || i.tm.opcode_modifier.drexv | |
4915 | || i.tm.opcode_modifier.drexc) | |
85f10a01 MM |
4916 | { |
4917 | op = i.drex.modrm_reg; | |
4918 | i.rm.reg = i.op[op].regs->reg_num; | |
4919 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
4920 | i.rex |= REX_R; | |
4921 | } | |
4922 | else | |
4923 | { | |
c0209578 L |
4924 | for (op = 0; op < i.operands; op++) |
4925 | if (i.types[op].bitfield.reg8 | |
4926 | || i.types[op].bitfield.reg16 | |
4927 | || i.types[op].bitfield.reg32 | |
4928 | || i.types[op].bitfield.reg64 | |
4929 | || i.types[op].bitfield.regmmx | |
4930 | || i.types[op].bitfield.regxmm | |
4931 | || i.types[op].bitfield.sreg2 | |
4932 | || i.types[op].bitfield.sreg3 | |
4933 | || i.types[op].bitfield.control | |
4934 | || i.types[op].bitfield.debug | |
4935 | || i.types[op].bitfield.test) | |
4936 | break; | |
4937 | ||
4938 | assert (op < i.operands); | |
99018f42 | 4939 | |
85f10a01 MM |
4940 | /* If there is an extension opcode to put here, the |
4941 | register number must be put into the regmem field. */ | |
c0209578 L |
4942 | if (i.tm.extension_opcode != None) |
4943 | { | |
4944 | i.rm.regmem = i.op[op].regs->reg_num; | |
4945 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
4946 | i.rex |= REX_B; | |
4947 | } | |
4948 | else | |
4949 | { | |
4950 | i.rm.reg = i.op[op].regs->reg_num; | |
4951 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
4952 | i.rex |= REX_R; | |
4953 | } | |
85f10a01 | 4954 | } |
252b5132 | 4955 | |
29b0f896 AM |
4956 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
4957 | must set it to 3 to indicate this is a register operand | |
4958 | in the regmem field. */ | |
4959 | if (!i.mem_operands) | |
4960 | i.rm.mode = 3; | |
4961 | } | |
252b5132 | 4962 | |
29b0f896 | 4963 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
85f10a01 MM |
4964 | if (i.tm.extension_opcode != None |
4965 | && !(i.tm.opcode_modifier.drex | |
4966 | || i.tm.opcode_modifier.drexv | |
4967 | || i.tm.opcode_modifier.drexc)) | |
29b0f896 AM |
4968 | i.rm.reg = i.tm.extension_opcode; |
4969 | } | |
4970 | return default_seg; | |
4971 | } | |
252b5132 | 4972 | |
29b0f896 | 4973 | static void |
e3bb37b5 | 4974 | output_branch (void) |
29b0f896 AM |
4975 | { |
4976 | char *p; | |
4977 | int code16; | |
4978 | int prefix; | |
4979 | relax_substateT subtype; | |
4980 | symbolS *sym; | |
4981 | offsetT off; | |
4982 | ||
4983 | code16 = 0; | |
4984 | if (flag_code == CODE_16BIT) | |
4985 | code16 = CODE16; | |
4986 | ||
4987 | prefix = 0; | |
4988 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 4989 | { |
29b0f896 AM |
4990 | prefix = 1; |
4991 | i.prefixes -= 1; | |
4992 | code16 ^= CODE16; | |
252b5132 | 4993 | } |
29b0f896 AM |
4994 | /* Pentium4 branch hints. */ |
4995 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
4996 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 4997 | { |
29b0f896 AM |
4998 | prefix++; |
4999 | i.prefixes--; | |
5000 | } | |
5001 | if (i.prefix[REX_PREFIX] != 0) | |
5002 | { | |
5003 | prefix++; | |
5004 | i.prefixes--; | |
2f66722d AM |
5005 | } |
5006 | ||
29b0f896 AM |
5007 | if (i.prefixes != 0 && !intel_syntax) |
5008 | as_warn (_("skipping prefixes on this instruction")); | |
5009 | ||
5010 | /* It's always a symbol; End frag & setup for relax. | |
5011 | Make sure there is enough room in this frag for the largest | |
5012 | instruction we may generate in md_convert_frag. This is 2 | |
5013 | bytes for the opcode and room for the prefix and largest | |
5014 | displacement. */ | |
5015 | frag_grow (prefix + 2 + 4); | |
5016 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
5017 | p = frag_more (prefix + 1); | |
5018 | if (i.prefix[DATA_PREFIX] != 0) | |
5019 | *p++ = DATA_PREFIX_OPCODE; | |
5020 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
5021 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
5022 | *p++ = i.prefix[SEG_PREFIX]; | |
5023 | if (i.prefix[REX_PREFIX] != 0) | |
5024 | *p++ = i.prefix[REX_PREFIX]; | |
5025 | *p = i.tm.base_opcode; | |
5026 | ||
5027 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
5028 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL); | |
40fb9820 | 5029 | else if (cpu_arch_flags.bitfield.cpui386) |
29b0f896 AM |
5030 | subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL); |
5031 | else | |
5032 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL); | |
5033 | subtype |= code16; | |
3e73aa7c | 5034 | |
29b0f896 AM |
5035 | sym = i.op[0].disps->X_add_symbol; |
5036 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 5037 | |
29b0f896 AM |
5038 | if (i.op[0].disps->X_op != O_constant |
5039 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 5040 | { |
29b0f896 AM |
5041 | /* Handle complex expressions. */ |
5042 | sym = make_expr_symbol (i.op[0].disps); | |
5043 | off = 0; | |
5044 | } | |
3e73aa7c | 5045 | |
29b0f896 AM |
5046 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
5047 | Pass reloc in fr_var. */ | |
5048 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); | |
5049 | } | |
3e73aa7c | 5050 | |
29b0f896 | 5051 | static void |
e3bb37b5 | 5052 | output_jump (void) |
29b0f896 AM |
5053 | { |
5054 | char *p; | |
5055 | int size; | |
3e02c1cc | 5056 | fixS *fixP; |
29b0f896 | 5057 | |
40fb9820 | 5058 | if (i.tm.opcode_modifier.jumpbyte) |
29b0f896 AM |
5059 | { |
5060 | /* This is a loop or jecxz type instruction. */ | |
5061 | size = 1; | |
5062 | if (i.prefix[ADDR_PREFIX] != 0) | |
5063 | { | |
5064 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
5065 | i.prefixes -= 1; | |
5066 | } | |
5067 | /* Pentium4 branch hints. */ | |
5068 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
5069 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
5070 | { | |
5071 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
5072 | i.prefixes--; | |
3e73aa7c JH |
5073 | } |
5074 | } | |
29b0f896 AM |
5075 | else |
5076 | { | |
5077 | int code16; | |
3e73aa7c | 5078 | |
29b0f896 AM |
5079 | code16 = 0; |
5080 | if (flag_code == CODE_16BIT) | |
5081 | code16 = CODE16; | |
3e73aa7c | 5082 | |
29b0f896 AM |
5083 | if (i.prefix[DATA_PREFIX] != 0) |
5084 | { | |
5085 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
5086 | i.prefixes -= 1; | |
5087 | code16 ^= CODE16; | |
5088 | } | |
252b5132 | 5089 | |
29b0f896 AM |
5090 | size = 4; |
5091 | if (code16) | |
5092 | size = 2; | |
5093 | } | |
9fcc94b6 | 5094 | |
29b0f896 AM |
5095 | if (i.prefix[REX_PREFIX] != 0) |
5096 | { | |
5097 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); | |
5098 | i.prefixes -= 1; | |
5099 | } | |
252b5132 | 5100 | |
29b0f896 AM |
5101 | if (i.prefixes != 0 && !intel_syntax) |
5102 | as_warn (_("skipping prefixes on this instruction")); | |
e0890092 | 5103 | |
29b0f896 AM |
5104 | p = frag_more (1 + size); |
5105 | *p++ = i.tm.base_opcode; | |
e0890092 | 5106 | |
3e02c1cc AM |
5107 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
5108 | i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0])); | |
5109 | ||
5110 | /* All jumps handled here are signed, but don't use a signed limit | |
5111 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
5112 | 4G and 64k respectively. */ | |
5113 | if (size == 1) | |
5114 | fixP->fx_signed = 1; | |
29b0f896 | 5115 | } |
e0890092 | 5116 | |
29b0f896 | 5117 | static void |
e3bb37b5 | 5118 | output_interseg_jump (void) |
29b0f896 AM |
5119 | { |
5120 | char *p; | |
5121 | int size; | |
5122 | int prefix; | |
5123 | int code16; | |
252b5132 | 5124 | |
29b0f896 AM |
5125 | code16 = 0; |
5126 | if (flag_code == CODE_16BIT) | |
5127 | code16 = CODE16; | |
a217f122 | 5128 | |
29b0f896 AM |
5129 | prefix = 0; |
5130 | if (i.prefix[DATA_PREFIX] != 0) | |
5131 | { | |
5132 | prefix = 1; | |
5133 | i.prefixes -= 1; | |
5134 | code16 ^= CODE16; | |
5135 | } | |
5136 | if (i.prefix[REX_PREFIX] != 0) | |
5137 | { | |
5138 | prefix++; | |
5139 | i.prefixes -= 1; | |
5140 | } | |
252b5132 | 5141 | |
29b0f896 AM |
5142 | size = 4; |
5143 | if (code16) | |
5144 | size = 2; | |
252b5132 | 5145 | |
29b0f896 AM |
5146 | if (i.prefixes != 0 && !intel_syntax) |
5147 | as_warn (_("skipping prefixes on this instruction")); | |
252b5132 | 5148 | |
29b0f896 AM |
5149 | /* 1 opcode; 2 segment; offset */ |
5150 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 5151 | |
29b0f896 AM |
5152 | if (i.prefix[DATA_PREFIX] != 0) |
5153 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 5154 | |
29b0f896 AM |
5155 | if (i.prefix[REX_PREFIX] != 0) |
5156 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 5157 | |
29b0f896 AM |
5158 | *p++ = i.tm.base_opcode; |
5159 | if (i.op[1].imms->X_op == O_constant) | |
5160 | { | |
5161 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 5162 | |
29b0f896 AM |
5163 | if (size == 2 |
5164 | && !fits_in_unsigned_word (n) | |
5165 | && !fits_in_signed_word (n)) | |
5166 | { | |
5167 | as_bad (_("16-bit jump out of range")); | |
5168 | return; | |
5169 | } | |
5170 | md_number_to_chars (p, n, size); | |
5171 | } | |
5172 | else | |
5173 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
5174 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); | |
5175 | if (i.op[0].imms->X_op != O_constant) | |
5176 | as_bad (_("can't handle non absolute segment in `%s'"), | |
5177 | i.tm.name); | |
5178 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
5179 | } | |
a217f122 | 5180 | |
29b0f896 | 5181 | static void |
e3bb37b5 | 5182 | output_insn (void) |
29b0f896 | 5183 | { |
2bbd9c25 JJ |
5184 | fragS *insn_start_frag; |
5185 | offsetT insn_start_off; | |
5186 | ||
29b0f896 AM |
5187 | /* Tie dwarf2 debug info to the address at the start of the insn. |
5188 | We can't do this after the insn has been output as the current | |
5189 | frag may have been closed off. eg. by frag_var. */ | |
5190 | dwarf2_emit_insn (0); | |
5191 | ||
2bbd9c25 JJ |
5192 | insn_start_frag = frag_now; |
5193 | insn_start_off = frag_now_fix (); | |
5194 | ||
29b0f896 | 5195 | /* Output jumps. */ |
40fb9820 | 5196 | if (i.tm.opcode_modifier.jump) |
29b0f896 | 5197 | output_branch (); |
40fb9820 L |
5198 | else if (i.tm.opcode_modifier.jumpbyte |
5199 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 | 5200 | output_jump (); |
40fb9820 | 5201 | else if (i.tm.opcode_modifier.jumpintersegment) |
29b0f896 AM |
5202 | output_interseg_jump (); |
5203 | else | |
5204 | { | |
5205 | /* Output normal instructions here. */ | |
5206 | char *p; | |
5207 | unsigned char *q; | |
47465058 | 5208 | unsigned int j; |
331d2d0d | 5209 | unsigned int prefix; |
4dffcebc L |
5210 | |
5211 | switch (i.tm.opcode_length) | |
bc4bd9ab | 5212 | { |
4dffcebc | 5213 | case 3: |
331d2d0d L |
5214 | if (i.tm.base_opcode & 0xff000000) |
5215 | { | |
5216 | prefix = (i.tm.base_opcode >> 24) & 0xff; | |
5217 | goto check_prefix; | |
5218 | } | |
4dffcebc L |
5219 | break; |
5220 | case 2: | |
5221 | if ((i.tm.base_opcode & 0xff0000) != 0) | |
bc4bd9ab | 5222 | { |
4dffcebc L |
5223 | prefix = (i.tm.base_opcode >> 16) & 0xff; |
5224 | if (i.tm.cpu_flags.bitfield.cpupadlock) | |
5225 | { | |
5226 | check_prefix: | |
5227 | if (prefix != REPE_PREFIX_OPCODE | |
5228 | || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE) | |
5229 | add_prefix (prefix); | |
5230 | } | |
5231 | else | |
bc4bd9ab MK |
5232 | add_prefix (prefix); |
5233 | } | |
4dffcebc L |
5234 | break; |
5235 | case 1: | |
5236 | break; | |
5237 | default: | |
5238 | abort (); | |
0f10071e | 5239 | } |
252b5132 | 5240 | |
29b0f896 | 5241 | /* The prefix bytes. */ |
47465058 L |
5242 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) |
5243 | if (*q) | |
5244 | FRAG_APPEND_1_CHAR (*q); | |
252b5132 | 5245 | |
29b0f896 | 5246 | /* Now the opcode; be careful about word order here! */ |
4dffcebc | 5247 | if (i.tm.opcode_length == 1) |
29b0f896 AM |
5248 | { |
5249 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
5250 | } | |
5251 | else | |
5252 | { | |
4dffcebc | 5253 | switch (i.tm.opcode_length) |
331d2d0d | 5254 | { |
4dffcebc | 5255 | case 3: |
331d2d0d L |
5256 | p = frag_more (3); |
5257 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
4dffcebc L |
5258 | break; |
5259 | case 2: | |
5260 | p = frag_more (2); | |
5261 | break; | |
5262 | default: | |
5263 | abort (); | |
5264 | break; | |
331d2d0d | 5265 | } |
0f10071e | 5266 | |
29b0f896 AM |
5267 | /* Put out high byte first: can't use md_number_to_chars! */ |
5268 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
5269 | *p = i.tm.base_opcode & 0xff; | |
85f10a01 MM |
5270 | |
5271 | /* On SSE5, encode the OC1 bit in the DREX field if this | |
5272 | encoding has multiple formats. */ | |
5273 | if (i.tm.opcode_modifier.drex | |
5274 | && i.tm.opcode_modifier.drexv | |
5275 | && DREX_OC1 (i.tm.extension_opcode)) | |
5276 | *p |= DREX_OC1_MASK; | |
29b0f896 | 5277 | } |
3e73aa7c | 5278 | |
29b0f896 | 5279 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 5280 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 5281 | { |
4a3523fa L |
5282 | FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 |
5283 | | i.rm.reg << 3 | |
5284 | | i.rm.mode << 6)); | |
29b0f896 AM |
5285 | /* If i.rm.regmem == ESP (4) |
5286 | && i.rm.mode != (Register mode) | |
5287 | && not 16 bit | |
5288 | ==> need second modrm byte. */ | |
5289 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
5290 | && i.rm.mode != 3 | |
40fb9820 | 5291 | && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16)) |
4a3523fa L |
5292 | FRAG_APPEND_1_CHAR ((i.sib.base << 0 |
5293 | | i.sib.index << 3 | |
5294 | | i.sib.scale << 6)); | |
29b0f896 | 5295 | } |
3e73aa7c | 5296 | |
85f10a01 MM |
5297 | /* Write the DREX byte if needed. */ |
5298 | if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc) | |
5299 | { | |
5300 | p = frag_more (1); | |
5301 | *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7)); | |
5302 | ||
5303 | /* Encode the OC0 bit if this encoding has multiple | |
5304 | formats. */ | |
5305 | if ((i.tm.opcode_modifier.drex | |
5306 | || i.tm.opcode_modifier.drexv) | |
5307 | && DREX_OC0 (i.tm.extension_opcode)) | |
5308 | *p |= DREX_OC0_MASK; | |
5309 | } | |
5310 | ||
29b0f896 | 5311 | if (i.disp_operands) |
2bbd9c25 | 5312 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 5313 | |
29b0f896 | 5314 | if (i.imm_operands) |
2bbd9c25 | 5315 | output_imm (insn_start_frag, insn_start_off); |
29b0f896 | 5316 | } |
252b5132 | 5317 | |
29b0f896 AM |
5318 | #ifdef DEBUG386 |
5319 | if (flag_debug) | |
5320 | { | |
7b81dfbb | 5321 | pi ("" /*line*/, &i); |
29b0f896 AM |
5322 | } |
5323 | #endif /* DEBUG386 */ | |
5324 | } | |
252b5132 | 5325 | |
e205caa7 L |
5326 | /* Return the size of the displacement operand N. */ |
5327 | ||
5328 | static int | |
5329 | disp_size (unsigned int n) | |
5330 | { | |
5331 | int size = 4; | |
40fb9820 L |
5332 | if (i.types[n].bitfield.disp64) |
5333 | size = 8; | |
5334 | else if (i.types[n].bitfield.disp8) | |
5335 | size = 1; | |
5336 | else if (i.types[n].bitfield.disp16) | |
5337 | size = 2; | |
e205caa7 L |
5338 | return size; |
5339 | } | |
5340 | ||
5341 | /* Return the size of the immediate operand N. */ | |
5342 | ||
5343 | static int | |
5344 | imm_size (unsigned int n) | |
5345 | { | |
5346 | int size = 4; | |
40fb9820 L |
5347 | if (i.types[n].bitfield.imm64) |
5348 | size = 8; | |
5349 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
5350 | size = 1; | |
5351 | else if (i.types[n].bitfield.imm16) | |
5352 | size = 2; | |
e205caa7 L |
5353 | return size; |
5354 | } | |
5355 | ||
29b0f896 | 5356 | static void |
64e74474 | 5357 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
5358 | { |
5359 | char *p; | |
5360 | unsigned int n; | |
252b5132 | 5361 | |
29b0f896 AM |
5362 | for (n = 0; n < i.operands; n++) |
5363 | { | |
40fb9820 | 5364 | if (operand_type_check (i.types[n], disp)) |
29b0f896 AM |
5365 | { |
5366 | if (i.op[n].disps->X_op == O_constant) | |
5367 | { | |
e205caa7 | 5368 | int size = disp_size (n); |
29b0f896 | 5369 | offsetT val; |
252b5132 | 5370 | |
29b0f896 AM |
5371 | val = offset_in_range (i.op[n].disps->X_add_number, |
5372 | size); | |
5373 | p = frag_more (size); | |
5374 | md_number_to_chars (p, val, size); | |
5375 | } | |
5376 | else | |
5377 | { | |
f86103b7 | 5378 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 5379 | int size = disp_size (n); |
40fb9820 | 5380 | int sign = i.types[n].bitfield.disp32s; |
29b0f896 AM |
5381 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
5382 | ||
e205caa7 | 5383 | /* We can't have 8 bit displacement here. */ |
40fb9820 | 5384 | assert (!i.types[n].bitfield.disp8); |
e205caa7 | 5385 | |
29b0f896 AM |
5386 | /* The PC relative address is computed relative |
5387 | to the instruction boundary, so in case immediate | |
5388 | fields follows, we need to adjust the value. */ | |
5389 | if (pcrel && i.imm_operands) | |
5390 | { | |
29b0f896 | 5391 | unsigned int n1; |
e205caa7 | 5392 | int sz = 0; |
252b5132 | 5393 | |
29b0f896 | 5394 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 5395 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 5396 | { |
e205caa7 L |
5397 | /* Only one immediate is allowed for PC |
5398 | relative address. */ | |
5399 | assert (sz == 0); | |
5400 | sz = imm_size (n1); | |
5401 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 5402 | } |
29b0f896 | 5403 | /* We should find the immediate. */ |
e205caa7 | 5404 | assert (sz != 0); |
29b0f896 | 5405 | } |
520dc8e8 | 5406 | |
29b0f896 | 5407 | p = frag_more (size); |
2bbd9c25 | 5408 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 5409 | if (GOT_symbol |
2bbd9c25 | 5410 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 5411 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
5412 | || reloc_type == BFD_RELOC_X86_64_32S |
5413 | || (reloc_type == BFD_RELOC_64 | |
5414 | && object_64bit)) | |
d6ab8113 JB |
5415 | && (i.op[n].disps->X_op == O_symbol |
5416 | || (i.op[n].disps->X_op == O_add | |
5417 | && ((symbol_get_value_expression | |
5418 | (i.op[n].disps->X_op_symbol)->X_op) | |
5419 | == O_subtract)))) | |
5420 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 JJ |
5421 | { |
5422 | offsetT add; | |
5423 | ||
5424 | if (insn_start_frag == frag_now) | |
5425 | add = (p - frag_now->fr_literal) - insn_start_off; | |
5426 | else | |
5427 | { | |
5428 | fragS *fr; | |
5429 | ||
5430 | add = insn_start_frag->fr_fix - insn_start_off; | |
5431 | for (fr = insn_start_frag->fr_next; | |
5432 | fr && fr != frag_now; fr = fr->fr_next) | |
5433 | add += fr->fr_fix; | |
5434 | add += p - frag_now->fr_literal; | |
5435 | } | |
5436 | ||
4fa24527 | 5437 | if (!object_64bit) |
7b81dfbb AJ |
5438 | { |
5439 | reloc_type = BFD_RELOC_386_GOTPC; | |
5440 | i.op[n].imms->X_add_number += add; | |
5441 | } | |
5442 | else if (reloc_type == BFD_RELOC_64) | |
5443 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 5444 | else |
7b81dfbb AJ |
5445 | /* Don't do the adjustment for x86-64, as there |
5446 | the pcrel addressing is relative to the _next_ | |
5447 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 5448 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 5449 | } |
062cd5e7 | 5450 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
2bbd9c25 | 5451 | i.op[n].disps, pcrel, reloc_type); |
29b0f896 AM |
5452 | } |
5453 | } | |
5454 | } | |
5455 | } | |
252b5132 | 5456 | |
29b0f896 | 5457 | static void |
64e74474 | 5458 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
5459 | { |
5460 | char *p; | |
5461 | unsigned int n; | |
252b5132 | 5462 | |
29b0f896 AM |
5463 | for (n = 0; n < i.operands; n++) |
5464 | { | |
40fb9820 | 5465 | if (operand_type_check (i.types[n], imm)) |
29b0f896 AM |
5466 | { |
5467 | if (i.op[n].imms->X_op == O_constant) | |
5468 | { | |
e205caa7 | 5469 | int size = imm_size (n); |
29b0f896 | 5470 | offsetT val; |
b4cac588 | 5471 | |
29b0f896 AM |
5472 | val = offset_in_range (i.op[n].imms->X_add_number, |
5473 | size); | |
5474 | p = frag_more (size); | |
5475 | md_number_to_chars (p, val, size); | |
5476 | } | |
5477 | else | |
5478 | { | |
5479 | /* Not absolute_section. | |
5480 | Need a 32-bit fixup (don't support 8bit | |
5481 | non-absolute imms). Try to support other | |
5482 | sizes ... */ | |
f86103b7 | 5483 | enum bfd_reloc_code_real reloc_type; |
e205caa7 L |
5484 | int size = imm_size (n); |
5485 | int sign; | |
29b0f896 | 5486 | |
40fb9820 | 5487 | if (i.types[n].bitfield.imm32s |
a7d61044 | 5488 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 5489 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 5490 | sign = 1; |
e205caa7 L |
5491 | else |
5492 | sign = 0; | |
520dc8e8 | 5493 | |
29b0f896 AM |
5494 | p = frag_more (size); |
5495 | reloc_type = reloc (size, 0, sign, i.reloc[n]); | |
f86103b7 | 5496 | |
2bbd9c25 JJ |
5497 | /* This is tough to explain. We end up with this one if we |
5498 | * have operands that look like | |
5499 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
5500 | * obtain the absolute address of the GOT, and it is strongly | |
5501 | * preferable from a performance point of view to avoid using | |
5502 | * a runtime relocation for this. The actual sequence of | |
5503 | * instructions often look something like: | |
5504 | * | |
5505 | * call .L66 | |
5506 | * .L66: | |
5507 | * popl %ebx | |
5508 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
5509 | * | |
5510 | * The call and pop essentially return the absolute address | |
5511 | * of the label .L66 and store it in %ebx. The linker itself | |
5512 | * will ultimately change the first operand of the addl so | |
5513 | * that %ebx points to the GOT, but to keep things simple, the | |
5514 | * .o file must have this operand set so that it generates not | |
5515 | * the absolute address of .L66, but the absolute address of | |
5516 | * itself. This allows the linker itself simply treat a GOTPC | |
5517 | * relocation as asking for a pcrel offset to the GOT to be | |
5518 | * added in, and the addend of the relocation is stored in the | |
5519 | * operand field for the instruction itself. | |
5520 | * | |
5521 | * Our job here is to fix the operand so that it would add | |
5522 | * the correct offset so that %ebx would point to itself. The | |
5523 | * thing that is tricky is that .-.L66 will point to the | |
5524 | * beginning of the instruction, so we need to further modify | |
5525 | * the operand so that it will point to itself. There are | |
5526 | * other cases where you have something like: | |
5527 | * | |
5528 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
5529 | * | |
5530 | * and here no correction would be required. Internally in | |
5531 | * the assembler we treat operands of this form as not being | |
5532 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
5533 | * whether it would simplify matters to do it this way. Who | |
5534 | * knows. In earlier versions of the PIC patches, the | |
5535 | * pcrel_adjust field was used to store the correction, but | |
5536 | * since the expression is not pcrel, I felt it would be | |
5537 | * confusing to do it this way. */ | |
5538 | ||
d6ab8113 | 5539 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
5540 | || reloc_type == BFD_RELOC_X86_64_32S |
5541 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
5542 | && GOT_symbol |
5543 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
5544 | && (i.op[n].imms->X_op == O_symbol | |
5545 | || (i.op[n].imms->X_op == O_add | |
5546 | && ((symbol_get_value_expression | |
5547 | (i.op[n].imms->X_op_symbol)->X_op) | |
5548 | == O_subtract)))) | |
5549 | { | |
2bbd9c25 JJ |
5550 | offsetT add; |
5551 | ||
5552 | if (insn_start_frag == frag_now) | |
5553 | add = (p - frag_now->fr_literal) - insn_start_off; | |
5554 | else | |
5555 | { | |
5556 | fragS *fr; | |
5557 | ||
5558 | add = insn_start_frag->fr_fix - insn_start_off; | |
5559 | for (fr = insn_start_frag->fr_next; | |
5560 | fr && fr != frag_now; fr = fr->fr_next) | |
5561 | add += fr->fr_fix; | |
5562 | add += p - frag_now->fr_literal; | |
5563 | } | |
5564 | ||
4fa24527 | 5565 | if (!object_64bit) |
d6ab8113 | 5566 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 5567 | else if (size == 4) |
d6ab8113 | 5568 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
5569 | else if (size == 8) |
5570 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
2bbd9c25 | 5571 | i.op[n].imms->X_add_number += add; |
29b0f896 | 5572 | } |
29b0f896 AM |
5573 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
5574 | i.op[n].imms, 0, reloc_type); | |
5575 | } | |
5576 | } | |
5577 | } | |
252b5132 RH |
5578 | } |
5579 | \f | |
d182319b JB |
5580 | /* x86_cons_fix_new is called via the expression parsing code when a |
5581 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
5582 | static enum bfd_reloc_code_real got_reloc = NO_RELOC; | |
5583 | static int cons_sign = -1; | |
5584 | ||
5585 | void | |
e3bb37b5 | 5586 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
64e74474 | 5587 | expressionS *exp) |
d182319b JB |
5588 | { |
5589 | enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc); | |
5590 | ||
5591 | got_reloc = NO_RELOC; | |
5592 | ||
5593 | #ifdef TE_PE | |
5594 | if (exp->X_op == O_secrel) | |
5595 | { | |
5596 | exp->X_op = O_symbol; | |
5597 | r = BFD_RELOC_32_SECREL; | |
5598 | } | |
5599 | #endif | |
5600 | ||
5601 | fix_new_exp (frag, off, len, exp, 0, r); | |
5602 | } | |
5603 | ||
718ddfc0 JB |
5604 | #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT) |
5605 | # define lex_got(reloc, adjust, types) NULL | |
5606 | #else | |
f3c180ae AM |
5607 | /* Parse operands of the form |
5608 | <symbol>@GOTOFF+<nnn> | |
5609 | and similar .plt or .got references. | |
5610 | ||
5611 | If we find one, set up the correct relocation in RELOC and copy the | |
5612 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
5613 | parsing by the calling routine. Return this buffer, and if ADJUST | |
5614 | is non-null set it to the length of the string we removed from the | |
5615 | input line. Otherwise return NULL. */ | |
5616 | static char * | |
3956db08 | 5617 | lex_got (enum bfd_reloc_code_real *reloc, |
64e74474 | 5618 | int *adjust, |
40fb9820 | 5619 | i386_operand_type *types) |
f3c180ae | 5620 | { |
7b81dfbb AJ |
5621 | /* Some of the relocations depend on the size of what field is to |
5622 | be relocated. But in our callers i386_immediate and i386_displacement | |
5623 | we don't yet know the operand size (this will be set by insn | |
5624 | matching). Hence we record the word32 relocation here, | |
5625 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
5626 | static const struct { |
5627 | const char *str; | |
4fa24527 | 5628 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 5629 | const i386_operand_type types64; |
f3c180ae | 5630 | } gotrel[] = { |
4eed87de AM |
5631 | { "PLTOFF", { 0, |
5632 | BFD_RELOC_X86_64_PLTOFF64 }, | |
40fb9820 | 5633 | OPERAND_TYPE_IMM64 }, |
4eed87de AM |
5634 | { "PLT", { BFD_RELOC_386_PLT32, |
5635 | BFD_RELOC_X86_64_PLT32 }, | |
40fb9820 | 5636 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
5637 | { "GOTPLT", { 0, |
5638 | BFD_RELOC_X86_64_GOTPLT64 }, | |
40fb9820 | 5639 | OPERAND_TYPE_IMM64_DISP64 }, |
4eed87de AM |
5640 | { "GOTOFF", { BFD_RELOC_386_GOTOFF, |
5641 | BFD_RELOC_X86_64_GOTOFF64 }, | |
40fb9820 | 5642 | OPERAND_TYPE_IMM64_DISP64 }, |
4eed87de AM |
5643 | { "GOTPCREL", { 0, |
5644 | BFD_RELOC_X86_64_GOTPCREL }, | |
40fb9820 | 5645 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
5646 | { "TLSGD", { BFD_RELOC_386_TLS_GD, |
5647 | BFD_RELOC_X86_64_TLSGD }, | |
40fb9820 | 5648 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
5649 | { "TLSLDM", { BFD_RELOC_386_TLS_LDM, |
5650 | 0 }, | |
40fb9820 | 5651 | OPERAND_TYPE_NONE }, |
4eed87de AM |
5652 | { "TLSLD", { 0, |
5653 | BFD_RELOC_X86_64_TLSLD }, | |
40fb9820 | 5654 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
5655 | { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, |
5656 | BFD_RELOC_X86_64_GOTTPOFF }, | |
40fb9820 | 5657 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
5658 | { "TPOFF", { BFD_RELOC_386_TLS_LE_32, |
5659 | BFD_RELOC_X86_64_TPOFF32 }, | |
40fb9820 | 5660 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
4eed87de AM |
5661 | { "NTPOFF", { BFD_RELOC_386_TLS_LE, |
5662 | 0 }, | |
40fb9820 | 5663 | OPERAND_TYPE_NONE }, |
4eed87de AM |
5664 | { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, |
5665 | BFD_RELOC_X86_64_DTPOFF32 }, | |
40fb9820 L |
5666 | |
5667 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, | |
4eed87de AM |
5668 | { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, |
5669 | 0 }, | |
40fb9820 | 5670 | OPERAND_TYPE_NONE }, |
4eed87de AM |
5671 | { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, |
5672 | 0 }, | |
40fb9820 | 5673 | OPERAND_TYPE_NONE }, |
4eed87de AM |
5674 | { "GOT", { BFD_RELOC_386_GOT32, |
5675 | BFD_RELOC_X86_64_GOT32 }, | |
40fb9820 | 5676 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
4eed87de AM |
5677 | { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, |
5678 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
40fb9820 | 5679 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
5680 | { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, |
5681 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
40fb9820 | 5682 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
f3c180ae AM |
5683 | }; |
5684 | char *cp; | |
5685 | unsigned int j; | |
5686 | ||
718ddfc0 JB |
5687 | if (!IS_ELF) |
5688 | return NULL; | |
5689 | ||
f3c180ae | 5690 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 5691 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
5692 | return NULL; |
5693 | ||
47465058 | 5694 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae AM |
5695 | { |
5696 | int len; | |
5697 | ||
5698 | len = strlen (gotrel[j].str); | |
28f81592 | 5699 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 5700 | { |
4fa24527 | 5701 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 5702 | { |
28f81592 AM |
5703 | int first, second; |
5704 | char *tmpbuf, *past_reloc; | |
f3c180ae | 5705 | |
4fa24527 | 5706 | *reloc = gotrel[j].rel[object_64bit]; |
28f81592 AM |
5707 | if (adjust) |
5708 | *adjust = len; | |
f3c180ae | 5709 | |
3956db08 JB |
5710 | if (types) |
5711 | { | |
5712 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
5713 | { |
5714 | types->bitfield.imm32 = 1; | |
5715 | types->bitfield.disp32 = 1; | |
5716 | } | |
3956db08 JB |
5717 | else |
5718 | *types = gotrel[j].types64; | |
5719 | } | |
5720 | ||
f3c180ae AM |
5721 | if (GOT_symbol == NULL) |
5722 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
5723 | ||
28f81592 | 5724 | /* The length of the first part of our input line. */ |
f3c180ae | 5725 | first = cp - input_line_pointer; |
28f81592 AM |
5726 | |
5727 | /* The second part goes from after the reloc token until | |
67c11a9b | 5728 | (and including) an end_of_line char or comma. */ |
28f81592 | 5729 | past_reloc = cp + 1 + len; |
67c11a9b AM |
5730 | cp = past_reloc; |
5731 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
5732 | ++cp; | |
5733 | second = cp + 1 - past_reloc; | |
28f81592 AM |
5734 | |
5735 | /* Allocate and copy string. The trailing NUL shouldn't | |
5736 | be necessary, but be safe. */ | |
5737 | tmpbuf = xmalloc (first + second + 2); | |
f3c180ae | 5738 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
5739 | if (second != 0 && *past_reloc != ' ') |
5740 | /* Replace the relocation token with ' ', so that | |
5741 | errors like foo@GOTOFF1 will be detected. */ | |
5742 | tmpbuf[first++] = ' '; | |
5743 | memcpy (tmpbuf + first, past_reloc, second); | |
5744 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
5745 | return tmpbuf; |
5746 | } | |
5747 | ||
4fa24527 JB |
5748 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
5749 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
5750 | return NULL; |
5751 | } | |
5752 | } | |
5753 | ||
5754 | /* Might be a symbol version string. Don't as_bad here. */ | |
5755 | return NULL; | |
5756 | } | |
5757 | ||
f3c180ae | 5758 | void |
e3bb37b5 | 5759 | x86_cons (expressionS *exp, int size) |
f3c180ae | 5760 | { |
4fa24527 | 5761 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
5762 | { |
5763 | /* Handle @GOTOFF and the like in an expression. */ | |
5764 | char *save; | |
5765 | char *gotfree_input_line; | |
5766 | int adjust; | |
5767 | ||
5768 | save = input_line_pointer; | |
3956db08 | 5769 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
5770 | if (gotfree_input_line) |
5771 | input_line_pointer = gotfree_input_line; | |
5772 | ||
5773 | expression (exp); | |
5774 | ||
5775 | if (gotfree_input_line) | |
5776 | { | |
5777 | /* expression () has merrily parsed up to the end of line, | |
5778 | or a comma - in the wrong buffer. Transfer how far | |
5779 | input_line_pointer has moved to the right buffer. */ | |
5780 | input_line_pointer = (save | |
5781 | + (input_line_pointer - gotfree_input_line) | |
5782 | + adjust); | |
5783 | free (gotfree_input_line); | |
3992d3b7 AM |
5784 | if (exp->X_op == O_constant |
5785 | || exp->X_op == O_absent | |
5786 | || exp->X_op == O_illegal | |
5787 | || exp->X_op == O_register | |
5788 | || exp->X_op == O_big) | |
5789 | { | |
5790 | char c = *input_line_pointer; | |
5791 | *input_line_pointer = 0; | |
5792 | as_bad (_("missing or invalid expression `%s'"), save); | |
5793 | *input_line_pointer = c; | |
5794 | } | |
f3c180ae AM |
5795 | } |
5796 | } | |
5797 | else | |
5798 | expression (exp); | |
5799 | } | |
5800 | #endif | |
5801 | ||
d182319b | 5802 | static void signed_cons (int size) |
6482c264 | 5803 | { |
d182319b JB |
5804 | if (flag_code == CODE_64BIT) |
5805 | cons_sign = 1; | |
5806 | cons (size); | |
5807 | cons_sign = -1; | |
6482c264 NC |
5808 | } |
5809 | ||
d182319b | 5810 | #ifdef TE_PE |
6482c264 NC |
5811 | static void |
5812 | pe_directive_secrel (dummy) | |
5813 | int dummy ATTRIBUTE_UNUSED; | |
5814 | { | |
5815 | expressionS exp; | |
5816 | ||
5817 | do | |
5818 | { | |
5819 | expression (&exp); | |
5820 | if (exp.X_op == O_symbol) | |
5821 | exp.X_op = O_secrel; | |
5822 | ||
5823 | emit_expr (&exp, 4); | |
5824 | } | |
5825 | while (*input_line_pointer++ == ','); | |
5826 | ||
5827 | input_line_pointer--; | |
5828 | demand_empty_rest_of_line (); | |
5829 | } | |
6482c264 NC |
5830 | #endif |
5831 | ||
252b5132 | 5832 | static int |
70e41ade | 5833 | i386_immediate (char *imm_start) |
252b5132 RH |
5834 | { |
5835 | char *save_input_line_pointer; | |
f3c180ae | 5836 | char *gotfree_input_line; |
252b5132 | 5837 | segT exp_seg = 0; |
47926f60 | 5838 | expressionS *exp; |
40fb9820 L |
5839 | i386_operand_type types; |
5840 | ||
c6fb90c8 | 5841 | UINTS_SET (types, ~0); |
252b5132 RH |
5842 | |
5843 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
5844 | { | |
31b2323c L |
5845 | as_bad (_("at most %d immediate operands are allowed"), |
5846 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
5847 | return 0; |
5848 | } | |
5849 | ||
5850 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 5851 | i.op[this_operand].imms = exp; |
252b5132 RH |
5852 | |
5853 | if (is_space_char (*imm_start)) | |
5854 | ++imm_start; | |
5855 | ||
5856 | save_input_line_pointer = input_line_pointer; | |
5857 | input_line_pointer = imm_start; | |
5858 | ||
3956db08 | 5859 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
5860 | if (gotfree_input_line) |
5861 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
5862 | |
5863 | exp_seg = expression (exp); | |
5864 | ||
83183c0c | 5865 | SKIP_WHITESPACE (); |
252b5132 | 5866 | if (*input_line_pointer) |
f3c180ae | 5867 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
5868 | |
5869 | input_line_pointer = save_input_line_pointer; | |
f3c180ae AM |
5870 | if (gotfree_input_line) |
5871 | free (gotfree_input_line); | |
252b5132 | 5872 | |
3992d3b7 AM |
5873 | if (exp->X_op == O_absent |
5874 | || exp->X_op == O_illegal | |
5875 | || exp->X_op == O_big | |
5876 | || (gotfree_input_line | |
5877 | && (exp->X_op == O_constant | |
5878 | || exp->X_op == O_register))) | |
252b5132 | 5879 | { |
3992d3b7 | 5880 | as_bad (_("missing or invalid immediate expression `%s'"), |
24eab124 | 5881 | imm_start); |
3992d3b7 | 5882 | return 0; |
252b5132 | 5883 | } |
3e73aa7c | 5884 | else if (exp->X_op == O_constant) |
252b5132 | 5885 | { |
47926f60 | 5886 | /* Size it properly later. */ |
40fb9820 | 5887 | i.types[this_operand].bitfield.imm64 = 1; |
3e73aa7c | 5888 | /* If BFD64, sign extend val. */ |
4eed87de AM |
5889 | if (!use_rela_relocations |
5890 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) | |
5891 | exp->X_add_number | |
5892 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 5893 | } |
4c63da97 | 5894 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 5895 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 5896 | && exp_seg != absolute_section |
47926f60 | 5897 | && exp_seg != text_section |
24eab124 AM |
5898 | && exp_seg != data_section |
5899 | && exp_seg != bss_section | |
5900 | && exp_seg != undefined_section | |
f86103b7 | 5901 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 5902 | { |
d0b47220 | 5903 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
5904 | return 0; |
5905 | } | |
5906 | #endif | |
bb8f5920 L |
5907 | else if (!intel_syntax && exp->X_op == O_register) |
5908 | { | |
5909 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
5910 | return 0; | |
5911 | } | |
252b5132 RH |
5912 | else |
5913 | { | |
5914 | /* This is an address. The size of the address will be | |
24eab124 | 5915 | determined later, depending on destination register, |
3e73aa7c | 5916 | suffix, or the default for the section. */ |
40fb9820 L |
5917 | i.types[this_operand].bitfield.imm8 = 1; |
5918 | i.types[this_operand].bitfield.imm16 = 1; | |
5919 | i.types[this_operand].bitfield.imm32 = 1; | |
5920 | i.types[this_operand].bitfield.imm32s = 1; | |
5921 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
5922 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
5923 | types); | |
252b5132 RH |
5924 | } |
5925 | ||
5926 | return 1; | |
5927 | } | |
5928 | ||
551c1ca1 | 5929 | static char * |
e3bb37b5 | 5930 | i386_scale (char *scale) |
252b5132 | 5931 | { |
551c1ca1 AM |
5932 | offsetT val; |
5933 | char *save = input_line_pointer; | |
252b5132 | 5934 | |
551c1ca1 AM |
5935 | input_line_pointer = scale; |
5936 | val = get_absolute_expression (); | |
5937 | ||
5938 | switch (val) | |
252b5132 | 5939 | { |
551c1ca1 | 5940 | case 1: |
252b5132 RH |
5941 | i.log2_scale_factor = 0; |
5942 | break; | |
551c1ca1 | 5943 | case 2: |
252b5132 RH |
5944 | i.log2_scale_factor = 1; |
5945 | break; | |
551c1ca1 | 5946 | case 4: |
252b5132 RH |
5947 | i.log2_scale_factor = 2; |
5948 | break; | |
551c1ca1 | 5949 | case 8: |
252b5132 RH |
5950 | i.log2_scale_factor = 3; |
5951 | break; | |
5952 | default: | |
a724f0f4 JB |
5953 | { |
5954 | char sep = *input_line_pointer; | |
5955 | ||
5956 | *input_line_pointer = '\0'; | |
5957 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
5958 | scale); | |
5959 | *input_line_pointer = sep; | |
5960 | input_line_pointer = save; | |
5961 | return NULL; | |
5962 | } | |
252b5132 | 5963 | } |
29b0f896 | 5964 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
5965 | { |
5966 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 5967 | 1 << i.log2_scale_factor); |
252b5132 | 5968 | i.log2_scale_factor = 0; |
252b5132 | 5969 | } |
551c1ca1 AM |
5970 | scale = input_line_pointer; |
5971 | input_line_pointer = save; | |
5972 | return scale; | |
252b5132 RH |
5973 | } |
5974 | ||
252b5132 | 5975 | static int |
e3bb37b5 | 5976 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 5977 | { |
29b0f896 | 5978 | expressionS *exp; |
252b5132 RH |
5979 | segT exp_seg = 0; |
5980 | char *save_input_line_pointer; | |
f3c180ae | 5981 | char *gotfree_input_line; |
40fb9820 L |
5982 | int override; |
5983 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 5984 | int ret; |
252b5132 | 5985 | |
31b2323c L |
5986 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
5987 | { | |
5988 | as_bad (_("at most %d displacement operands are allowed"), | |
5989 | MAX_MEMORY_OPERANDS); | |
5990 | return 0; | |
5991 | } | |
5992 | ||
c6fb90c8 | 5993 | UINTS_CLEAR (bigdisp); |
40fb9820 L |
5994 | if ((i.types[this_operand].bitfield.jumpabsolute) |
5995 | || (!current_templates->start->opcode_modifier.jump | |
5996 | && !current_templates->start->opcode_modifier.jumpdword)) | |
e05278af | 5997 | { |
40fb9820 | 5998 | bigdisp.bitfield.disp32 = 1; |
e05278af | 5999 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
6000 | if (flag_code == CODE_64BIT) |
6001 | { | |
6002 | if (!override) | |
6003 | { | |
6004 | bigdisp.bitfield.disp32s = 1; | |
6005 | bigdisp.bitfield.disp64 = 1; | |
6006 | } | |
6007 | } | |
6008 | else if ((flag_code == CODE_16BIT) ^ override) | |
6009 | { | |
6010 | bigdisp.bitfield.disp32 = 0; | |
6011 | bigdisp.bitfield.disp16 = 1; | |
6012 | } | |
e05278af JB |
6013 | } |
6014 | else | |
6015 | { | |
6016 | /* For PC-relative branches, the width of the displacement | |
6017 | is dependent upon data size, not address size. */ | |
e05278af | 6018 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
6019 | if (flag_code == CODE_64BIT) |
6020 | { | |
6021 | if (override || i.suffix == WORD_MNEM_SUFFIX) | |
6022 | bigdisp.bitfield.disp16 = 1; | |
6023 | else | |
6024 | { | |
6025 | bigdisp.bitfield.disp32 = 1; | |
6026 | bigdisp.bitfield.disp32s = 1; | |
6027 | } | |
6028 | } | |
6029 | else | |
e05278af JB |
6030 | { |
6031 | if (!override) | |
6032 | override = (i.suffix == (flag_code != CODE_16BIT | |
6033 | ? WORD_MNEM_SUFFIX | |
6034 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
6035 | bigdisp.bitfield.disp32 = 1; |
6036 | if ((flag_code == CODE_16BIT) ^ override) | |
6037 | { | |
6038 | bigdisp.bitfield.disp32 = 0; | |
6039 | bigdisp.bitfield.disp16 = 1; | |
6040 | } | |
e05278af | 6041 | } |
e05278af | 6042 | } |
c6fb90c8 L |
6043 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
6044 | bigdisp); | |
252b5132 RH |
6045 | |
6046 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 6047 | i.op[this_operand].disps = exp; |
252b5132 RH |
6048 | i.disp_operands++; |
6049 | save_input_line_pointer = input_line_pointer; | |
6050 | input_line_pointer = disp_start; | |
6051 | END_STRING_AND_SAVE (disp_end); | |
6052 | ||
6053 | #ifndef GCC_ASM_O_HACK | |
6054 | #define GCC_ASM_O_HACK 0 | |
6055 | #endif | |
6056 | #if GCC_ASM_O_HACK | |
6057 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 6058 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 6059 | && displacement_string_end[-1] == '+') |
252b5132 RH |
6060 | { |
6061 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
6062 | constraint within gcc asm statements. |
6063 | For instance: | |
6064 | ||
6065 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
6066 | __asm__ __volatile__ ( \ | |
6067 | "movw %w2,%0\n\t" \ | |
6068 | "movw %w1,2+%0\n\t" \ | |
6069 | "rorl $16,%1\n\t" \ | |
6070 | "movb %b1,4+%0\n\t" \ | |
6071 | "movb %4,5+%0\n\t" \ | |
6072 | "movb $0,6+%0\n\t" \ | |
6073 | "movb %h1,7+%0\n\t" \ | |
6074 | "rorl $16,%1" \ | |
6075 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
6076 | ||
6077 | This works great except that the output assembler ends | |
6078 | up looking a bit weird if it turns out that there is | |
6079 | no offset. You end up producing code that looks like: | |
6080 | ||
6081 | #APP | |
6082 | movw $235,(%eax) | |
6083 | movw %dx,2+(%eax) | |
6084 | rorl $16,%edx | |
6085 | movb %dl,4+(%eax) | |
6086 | movb $137,5+(%eax) | |
6087 | movb $0,6+(%eax) | |
6088 | movb %dh,7+(%eax) | |
6089 | rorl $16,%edx | |
6090 | #NO_APP | |
6091 | ||
47926f60 | 6092 | So here we provide the missing zero. */ |
24eab124 AM |
6093 | |
6094 | *displacement_string_end = '0'; | |
252b5132 RH |
6095 | } |
6096 | #endif | |
3956db08 | 6097 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
6098 | if (gotfree_input_line) |
6099 | input_line_pointer = gotfree_input_line; | |
252b5132 | 6100 | |
24eab124 | 6101 | exp_seg = expression (exp); |
252b5132 | 6102 | |
636c26b0 AM |
6103 | SKIP_WHITESPACE (); |
6104 | if (*input_line_pointer) | |
6105 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
6106 | #if GCC_ASM_O_HACK | |
6107 | RESTORE_END_STRING (disp_end + 1); | |
6108 | #endif | |
636c26b0 | 6109 | input_line_pointer = save_input_line_pointer; |
636c26b0 AM |
6110 | if (gotfree_input_line) |
6111 | free (gotfree_input_line); | |
3992d3b7 | 6112 | ret = 1; |
636c26b0 | 6113 | |
24eab124 AM |
6114 | /* We do this to make sure that the section symbol is in |
6115 | the symbol table. We will ultimately change the relocation | |
47926f60 | 6116 | to be relative to the beginning of the section. */ |
1ae12ab7 | 6117 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
6118 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
6119 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 6120 | { |
636c26b0 | 6121 | if (exp->X_op != O_symbol) |
3992d3b7 | 6122 | goto inv_disp; |
636c26b0 | 6123 | |
e5cb08ac | 6124 | if (S_IS_LOCAL (exp->X_add_symbol) |
24eab124 AM |
6125 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section) |
6126 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); | |
24eab124 AM |
6127 | exp->X_op = O_subtract; |
6128 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 6129 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 6130 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
6131 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
6132 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 6133 | else |
29b0f896 | 6134 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 6135 | } |
252b5132 | 6136 | |
3992d3b7 AM |
6137 | else if (exp->X_op == O_absent |
6138 | || exp->X_op == O_illegal | |
6139 | || exp->X_op == O_big | |
6140 | || (gotfree_input_line | |
6141 | && (exp->X_op == O_constant | |
6142 | || exp->X_op == O_register))) | |
2daf4fd8 | 6143 | { |
3992d3b7 AM |
6144 | inv_disp: |
6145 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 6146 | disp_start); |
3992d3b7 | 6147 | ret = 0; |
2daf4fd8 AM |
6148 | } |
6149 | ||
4c63da97 | 6150 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3992d3b7 AM |
6151 | else if (exp->X_op != O_constant |
6152 | && OUTPUT_FLAVOR == bfd_target_aout_flavour | |
6153 | && exp_seg != absolute_section | |
6154 | && exp_seg != text_section | |
6155 | && exp_seg != data_section | |
6156 | && exp_seg != bss_section | |
6157 | && exp_seg != undefined_section | |
6158 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 6159 | { |
d0b47220 | 6160 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 6161 | ret = 0; |
24eab124 | 6162 | } |
252b5132 | 6163 | #endif |
3956db08 | 6164 | |
3992d3b7 AM |
6165 | RESTORE_END_STRING (disp_end); |
6166 | ||
40fb9820 L |
6167 | /* Check if this is a displacement only operand. */ |
6168 | bigdisp = i.types[this_operand]; | |
6169 | bigdisp.bitfield.disp8 = 0; | |
6170 | bigdisp.bitfield.disp16 = 0; | |
6171 | bigdisp.bitfield.disp32 = 0; | |
6172 | bigdisp.bitfield.disp32s = 0; | |
6173 | bigdisp.bitfield.disp64 = 0; | |
c6fb90c8 L |
6174 | if (UINTS_ALL_ZERO (bigdisp)) |
6175 | i.types[this_operand] = operand_type_and (i.types[this_operand], | |
6176 | types); | |
3956db08 | 6177 | |
3992d3b7 | 6178 | return ret; |
252b5132 RH |
6179 | } |
6180 | ||
eecb386c | 6181 | /* Make sure the memory operand we've been dealt is valid. |
47926f60 KH |
6182 | Return 1 on success, 0 on a failure. */ |
6183 | ||
252b5132 | 6184 | static int |
e3bb37b5 | 6185 | i386_index_check (const char *operand_string) |
252b5132 | 6186 | { |
3e73aa7c | 6187 | int ok; |
24eab124 | 6188 | #if INFER_ADDR_PREFIX |
eecb386c AM |
6189 | int fudged = 0; |
6190 | ||
24eab124 AM |
6191 | tryprefix: |
6192 | #endif | |
3e73aa7c | 6193 | ok = 1; |
75178d9d | 6194 | if (flag_code == CODE_64BIT) |
64e74474 | 6195 | { |
64e74474 | 6196 | if ((i.base_reg |
40fb9820 L |
6197 | && ((i.prefix[ADDR_PREFIX] == 0 |
6198 | && !i.base_reg->reg_type.bitfield.reg64) | |
6199 | || (i.prefix[ADDR_PREFIX] | |
6200 | && !i.base_reg->reg_type.bitfield.reg32)) | |
6201 | && (i.index_reg | |
9a04903e JB |
6202 | || i.base_reg->reg_num != |
6203 | (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip))) | |
64e74474 | 6204 | || (i.index_reg |
40fb9820 L |
6205 | && (!i.index_reg->reg_type.bitfield.baseindex |
6206 | || (i.prefix[ADDR_PREFIX] == 0 | |
db51cc60 L |
6207 | && i.index_reg->reg_num != RegRiz |
6208 | && !i.index_reg->reg_type.bitfield.reg64 | |
6209 | ) | |
40fb9820 | 6210 | || (i.prefix[ADDR_PREFIX] |
db51cc60 | 6211 | && i.index_reg->reg_num != RegEiz |
40fb9820 | 6212 | && !i.index_reg->reg_type.bitfield.reg32)))) |
64e74474 | 6213 | ok = 0; |
3e73aa7c JH |
6214 | } |
6215 | else | |
6216 | { | |
6217 | if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) | |
6218 | { | |
6219 | /* 16bit checks. */ | |
6220 | if ((i.base_reg | |
40fb9820 L |
6221 | && (!i.base_reg->reg_type.bitfield.reg16 |
6222 | || !i.base_reg->reg_type.bitfield.baseindex)) | |
3e73aa7c | 6223 | || (i.index_reg |
40fb9820 L |
6224 | && (!i.index_reg->reg_type.bitfield.reg16 |
6225 | || !i.index_reg->reg_type.bitfield.baseindex | |
29b0f896 AM |
6226 | || !(i.base_reg |
6227 | && i.base_reg->reg_num < 6 | |
6228 | && i.index_reg->reg_num >= 6 | |
6229 | && i.log2_scale_factor == 0)))) | |
3e73aa7c JH |
6230 | ok = 0; |
6231 | } | |
6232 | else | |
e5cb08ac | 6233 | { |
3e73aa7c JH |
6234 | /* 32bit checks. */ |
6235 | if ((i.base_reg | |
40fb9820 | 6236 | && !i.base_reg->reg_type.bitfield.reg32) |
3e73aa7c | 6237 | || (i.index_reg |
db51cc60 L |
6238 | && ((!i.index_reg->reg_type.bitfield.reg32 |
6239 | && i.index_reg->reg_num != RegEiz) | |
40fb9820 | 6240 | || !i.index_reg->reg_type.bitfield.baseindex))) |
e5cb08ac | 6241 | ok = 0; |
3e73aa7c JH |
6242 | } |
6243 | } | |
6244 | if (!ok) | |
24eab124 AM |
6245 | { |
6246 | #if INFER_ADDR_PREFIX | |
20f0a1fc | 6247 | if (i.prefix[ADDR_PREFIX] == 0) |
24eab124 AM |
6248 | { |
6249 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
6250 | i.prefixes += 1; | |
b23bac36 AM |
6251 | /* Change the size of any displacement too. At most one of |
6252 | Disp16 or Disp32 is set. | |
6253 | FIXME. There doesn't seem to be any real need for separate | |
6254 | Disp16 and Disp32 flags. The same goes for Imm16 and Imm32. | |
47926f60 | 6255 | Removing them would probably clean up the code quite a lot. */ |
4eed87de | 6256 | if (flag_code != CODE_64BIT |
40fb9820 L |
6257 | && (i.types[this_operand].bitfield.disp16 |
6258 | || i.types[this_operand].bitfield.disp32)) | |
6259 | i.types[this_operand] | |
c6fb90c8 | 6260 | = operand_type_xor (i.types[this_operand], disp16_32); |
eecb386c | 6261 | fudged = 1; |
24eab124 AM |
6262 | goto tryprefix; |
6263 | } | |
eecb386c AM |
6264 | if (fudged) |
6265 | as_bad (_("`%s' is not a valid base/index expression"), | |
6266 | operand_string); | |
6267 | else | |
c388dee8 | 6268 | #endif |
eecb386c AM |
6269 | as_bad (_("`%s' is not a valid %s bit base/index expression"), |
6270 | operand_string, | |
3e73aa7c | 6271 | flag_code_names[flag_code]); |
24eab124 | 6272 | } |
20f0a1fc | 6273 | return ok; |
24eab124 | 6274 | } |
252b5132 | 6275 | |
252b5132 | 6276 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero |
47926f60 | 6277 | on error. */ |
252b5132 | 6278 | |
252b5132 | 6279 | static int |
a7619375 | 6280 | i386_att_operand (char *operand_string) |
252b5132 | 6281 | { |
af6bdddf AM |
6282 | const reg_entry *r; |
6283 | char *end_op; | |
24eab124 | 6284 | char *op_string = operand_string; |
252b5132 | 6285 | |
24eab124 | 6286 | if (is_space_char (*op_string)) |
252b5132 RH |
6287 | ++op_string; |
6288 | ||
24eab124 | 6289 | /* We check for an absolute prefix (differentiating, |
47926f60 | 6290 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
6291 | if (*op_string == ABSOLUTE_PREFIX) |
6292 | { | |
6293 | ++op_string; | |
6294 | if (is_space_char (*op_string)) | |
6295 | ++op_string; | |
40fb9820 | 6296 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 | 6297 | } |
252b5132 | 6298 | |
47926f60 | 6299 | /* Check if operand is a register. */ |
4d1bb795 | 6300 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 6301 | { |
40fb9820 L |
6302 | i386_operand_type temp; |
6303 | ||
24eab124 AM |
6304 | /* Check for a segment override by searching for ':' after a |
6305 | segment register. */ | |
6306 | op_string = end_op; | |
6307 | if (is_space_char (*op_string)) | |
6308 | ++op_string; | |
40fb9820 L |
6309 | if (*op_string == ':' |
6310 | && (r->reg_type.bitfield.sreg2 | |
6311 | || r->reg_type.bitfield.sreg3)) | |
24eab124 AM |
6312 | { |
6313 | switch (r->reg_num) | |
6314 | { | |
6315 | case 0: | |
6316 | i.seg[i.mem_operands] = &es; | |
6317 | break; | |
6318 | case 1: | |
6319 | i.seg[i.mem_operands] = &cs; | |
6320 | break; | |
6321 | case 2: | |
6322 | i.seg[i.mem_operands] = &ss; | |
6323 | break; | |
6324 | case 3: | |
6325 | i.seg[i.mem_operands] = &ds; | |
6326 | break; | |
6327 | case 4: | |
6328 | i.seg[i.mem_operands] = &fs; | |
6329 | break; | |
6330 | case 5: | |
6331 | i.seg[i.mem_operands] = &gs; | |
6332 | break; | |
6333 | } | |
252b5132 | 6334 | |
24eab124 | 6335 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
6336 | ++op_string; |
6337 | if (is_space_char (*op_string)) | |
24eab124 | 6338 | ++op_string; |
252b5132 | 6339 | |
24eab124 AM |
6340 | if (!is_digit_char (*op_string) |
6341 | && !is_identifier_char (*op_string) | |
6342 | && *op_string != '(' | |
6343 | && *op_string != ABSOLUTE_PREFIX) | |
6344 | { | |
6345 | as_bad (_("bad memory operand `%s'"), op_string); | |
6346 | return 0; | |
6347 | } | |
47926f60 | 6348 | /* Handle case of %es:*foo. */ |
24eab124 AM |
6349 | if (*op_string == ABSOLUTE_PREFIX) |
6350 | { | |
6351 | ++op_string; | |
6352 | if (is_space_char (*op_string)) | |
6353 | ++op_string; | |
40fb9820 | 6354 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 AM |
6355 | } |
6356 | goto do_memory_reference; | |
6357 | } | |
6358 | if (*op_string) | |
6359 | { | |
d0b47220 | 6360 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
6361 | return 0; |
6362 | } | |
40fb9820 L |
6363 | temp = r->reg_type; |
6364 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
6365 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
6366 | temp); | |
7d5e4556 | 6367 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 6368 | i.op[this_operand].regs = r; |
24eab124 AM |
6369 | i.reg_operands++; |
6370 | } | |
af6bdddf AM |
6371 | else if (*op_string == REGISTER_PREFIX) |
6372 | { | |
6373 | as_bad (_("bad register name `%s'"), op_string); | |
6374 | return 0; | |
6375 | } | |
24eab124 | 6376 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 6377 | { |
24eab124 | 6378 | ++op_string; |
40fb9820 | 6379 | if (i.types[this_operand].bitfield.jumpabsolute) |
24eab124 | 6380 | { |
d0b47220 | 6381 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
6382 | return 0; |
6383 | } | |
6384 | if (!i386_immediate (op_string)) | |
6385 | return 0; | |
6386 | } | |
6387 | else if (is_digit_char (*op_string) | |
6388 | || is_identifier_char (*op_string) | |
e5cb08ac | 6389 | || *op_string == '(') |
24eab124 | 6390 | { |
47926f60 | 6391 | /* This is a memory reference of some sort. */ |
af6bdddf | 6392 | char *base_string; |
252b5132 | 6393 | |
47926f60 | 6394 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
6395 | char *displacement_string_start; |
6396 | char *displacement_string_end; | |
252b5132 | 6397 | |
24eab124 | 6398 | do_memory_reference: |
24eab124 | 6399 | if ((i.mem_operands == 1 |
40fb9820 | 6400 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
6401 | || i.mem_operands == 2) |
6402 | { | |
6403 | as_bad (_("too many memory references for `%s'"), | |
6404 | current_templates->start->name); | |
6405 | return 0; | |
6406 | } | |
252b5132 | 6407 | |
24eab124 AM |
6408 | /* Check for base index form. We detect the base index form by |
6409 | looking for an ')' at the end of the operand, searching | |
6410 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
6411 | after the '('. */ | |
af6bdddf | 6412 | base_string = op_string + strlen (op_string); |
c3332e24 | 6413 | |
af6bdddf AM |
6414 | --base_string; |
6415 | if (is_space_char (*base_string)) | |
6416 | --base_string; | |
252b5132 | 6417 | |
47926f60 | 6418 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
6419 | displacement_string_start = op_string; |
6420 | displacement_string_end = base_string + 1; | |
252b5132 | 6421 | |
24eab124 AM |
6422 | if (*base_string == ')') |
6423 | { | |
af6bdddf | 6424 | char *temp_string; |
24eab124 AM |
6425 | unsigned int parens_balanced = 1; |
6426 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 6427 | equal, so this loop will not be infinite. */ |
24eab124 AM |
6428 | do |
6429 | { | |
6430 | base_string--; | |
6431 | if (*base_string == ')') | |
6432 | parens_balanced++; | |
6433 | if (*base_string == '(') | |
6434 | parens_balanced--; | |
6435 | } | |
6436 | while (parens_balanced); | |
c3332e24 | 6437 | |
af6bdddf | 6438 | temp_string = base_string; |
c3332e24 | 6439 | |
24eab124 | 6440 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
6441 | ++base_string; |
6442 | if (is_space_char (*base_string)) | |
24eab124 | 6443 | ++base_string; |
252b5132 | 6444 | |
af6bdddf | 6445 | if (*base_string == ',' |
4eed87de AM |
6446 | || ((i.base_reg = parse_register (base_string, &end_op)) |
6447 | != NULL)) | |
252b5132 | 6448 | { |
af6bdddf | 6449 | displacement_string_end = temp_string; |
252b5132 | 6450 | |
40fb9820 | 6451 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 6452 | |
af6bdddf | 6453 | if (i.base_reg) |
24eab124 | 6454 | { |
24eab124 AM |
6455 | base_string = end_op; |
6456 | if (is_space_char (*base_string)) | |
6457 | ++base_string; | |
af6bdddf AM |
6458 | } |
6459 | ||
6460 | /* There may be an index reg or scale factor here. */ | |
6461 | if (*base_string == ',') | |
6462 | { | |
6463 | ++base_string; | |
6464 | if (is_space_char (*base_string)) | |
6465 | ++base_string; | |
6466 | ||
4eed87de AM |
6467 | if ((i.index_reg = parse_register (base_string, &end_op)) |
6468 | != NULL) | |
24eab124 | 6469 | { |
af6bdddf | 6470 | base_string = end_op; |
24eab124 AM |
6471 | if (is_space_char (*base_string)) |
6472 | ++base_string; | |
af6bdddf AM |
6473 | if (*base_string == ',') |
6474 | { | |
6475 | ++base_string; | |
6476 | if (is_space_char (*base_string)) | |
6477 | ++base_string; | |
6478 | } | |
e5cb08ac | 6479 | else if (*base_string != ')') |
af6bdddf | 6480 | { |
4eed87de AM |
6481 | as_bad (_("expecting `,' or `)' " |
6482 | "after index register in `%s'"), | |
af6bdddf AM |
6483 | operand_string); |
6484 | return 0; | |
6485 | } | |
24eab124 | 6486 | } |
af6bdddf | 6487 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 6488 | { |
af6bdddf | 6489 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
6490 | return 0; |
6491 | } | |
252b5132 | 6492 | |
47926f60 | 6493 | /* Check for scale factor. */ |
551c1ca1 | 6494 | if (*base_string != ')') |
af6bdddf | 6495 | { |
551c1ca1 AM |
6496 | char *end_scale = i386_scale (base_string); |
6497 | ||
6498 | if (!end_scale) | |
af6bdddf | 6499 | return 0; |
24eab124 | 6500 | |
551c1ca1 | 6501 | base_string = end_scale; |
af6bdddf AM |
6502 | if (is_space_char (*base_string)) |
6503 | ++base_string; | |
6504 | if (*base_string != ')') | |
6505 | { | |
4eed87de AM |
6506 | as_bad (_("expecting `)' " |
6507 | "after scale factor in `%s'"), | |
af6bdddf AM |
6508 | operand_string); |
6509 | return 0; | |
6510 | } | |
6511 | } | |
6512 | else if (!i.index_reg) | |
24eab124 | 6513 | { |
4eed87de AM |
6514 | as_bad (_("expecting index register or scale factor " |
6515 | "after `,'; got '%c'"), | |
af6bdddf | 6516 | *base_string); |
24eab124 AM |
6517 | return 0; |
6518 | } | |
6519 | } | |
af6bdddf | 6520 | else if (*base_string != ')') |
24eab124 | 6521 | { |
4eed87de AM |
6522 | as_bad (_("expecting `,' or `)' " |
6523 | "after base register in `%s'"), | |
af6bdddf | 6524 | operand_string); |
24eab124 AM |
6525 | return 0; |
6526 | } | |
c3332e24 | 6527 | } |
af6bdddf | 6528 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 6529 | { |
af6bdddf | 6530 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 6531 | return 0; |
c3332e24 | 6532 | } |
24eab124 AM |
6533 | } |
6534 | ||
6535 | /* If there's an expression beginning the operand, parse it, | |
6536 | assuming displacement_string_start and | |
6537 | displacement_string_end are meaningful. */ | |
6538 | if (displacement_string_start != displacement_string_end) | |
6539 | { | |
6540 | if (!i386_displacement (displacement_string_start, | |
6541 | displacement_string_end)) | |
6542 | return 0; | |
6543 | } | |
6544 | ||
6545 | /* Special case for (%dx) while doing input/output op. */ | |
6546 | if (i.base_reg | |
c6fb90c8 | 6547 | && UINTS_EQUAL (i.base_reg->reg_type, reg16_inoutportreg) |
24eab124 AM |
6548 | && i.index_reg == 0 |
6549 | && i.log2_scale_factor == 0 | |
6550 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 6551 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 6552 | { |
c6fb90c8 | 6553 | UINTS_CLEAR (i.types[this_operand]); |
40fb9820 | 6554 | i.types[this_operand].bitfield.inoutportreg = 1; |
24eab124 AM |
6555 | return 1; |
6556 | } | |
6557 | ||
eecb386c AM |
6558 | if (i386_index_check (operand_string) == 0) |
6559 | return 0; | |
5c07affc | 6560 | i.types[this_operand].bitfield.mem = 1; |
24eab124 AM |
6561 | i.mem_operands++; |
6562 | } | |
6563 | else | |
ce8a8b2f AM |
6564 | { |
6565 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
6566 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
6567 | output_invalid (*op_string), | |
6568 | this_operand + 1, | |
6569 | op_string); | |
6570 | return 0; | |
6571 | } | |
47926f60 | 6572 | return 1; /* Normal return. */ |
252b5132 RH |
6573 | } |
6574 | \f | |
ee7fcc42 AM |
6575 | /* md_estimate_size_before_relax() |
6576 | ||
6577 | Called just before relax() for rs_machine_dependent frags. The x86 | |
6578 | assembler uses these frags to handle variable size jump | |
6579 | instructions. | |
6580 | ||
6581 | Any symbol that is now undefined will not become defined. | |
6582 | Return the correct fr_subtype in the frag. | |
6583 | Return the initial "guess for variable size of frag" to caller. | |
6584 | The guess is actually the growth beyond the fixed part. Whatever | |
6585 | we do to grow the fixed or variable part contributes to our | |
6586 | returned value. */ | |
6587 | ||
252b5132 RH |
6588 | int |
6589 | md_estimate_size_before_relax (fragP, segment) | |
29b0f896 AM |
6590 | fragS *fragP; |
6591 | segT segment; | |
252b5132 | 6592 | { |
252b5132 | 6593 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
6594 | check for un-relaxable symbols. On an ELF system, we can't relax |
6595 | an externally visible symbol, because it may be overridden by a | |
6596 | shared library. */ | |
6597 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 6598 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 6599 | || (IS_ELF |
31312f95 AM |
6600 | && (S_IS_EXTERNAL (fragP->fr_symbol) |
6601 | || S_IS_WEAK (fragP->fr_symbol))) | |
b98ef147 AM |
6602 | #endif |
6603 | ) | |
252b5132 | 6604 | { |
b98ef147 AM |
6605 | /* Symbol is undefined in this segment, or we need to keep a |
6606 | reloc so that weak symbols can be overridden. */ | |
6607 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 6608 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
6609 | unsigned char *opcode; |
6610 | int old_fr_fix; | |
f6af82bd | 6611 | |
ee7fcc42 AM |
6612 | if (fragP->fr_var != NO_RELOC) |
6613 | reloc_type = fragP->fr_var; | |
b98ef147 | 6614 | else if (size == 2) |
f6af82bd AM |
6615 | reloc_type = BFD_RELOC_16_PCREL; |
6616 | else | |
6617 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 6618 | |
ee7fcc42 AM |
6619 | old_fr_fix = fragP->fr_fix; |
6620 | opcode = (unsigned char *) fragP->fr_opcode; | |
6621 | ||
fddf5b5b | 6622 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 6623 | { |
fddf5b5b AM |
6624 | case UNCOND_JUMP: |
6625 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 6626 | opcode[0] = 0xe9; |
252b5132 | 6627 | fragP->fr_fix += size; |
062cd5e7 AS |
6628 | fix_new (fragP, old_fr_fix, size, |
6629 | fragP->fr_symbol, | |
6630 | fragP->fr_offset, 1, | |
6631 | reloc_type); | |
252b5132 RH |
6632 | break; |
6633 | ||
fddf5b5b | 6634 | case COND_JUMP86: |
412167cb AM |
6635 | if (size == 2 |
6636 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
6637 | { |
6638 | /* Negate the condition, and branch past an | |
6639 | unconditional jump. */ | |
6640 | opcode[0] ^= 1; | |
6641 | opcode[1] = 3; | |
6642 | /* Insert an unconditional jump. */ | |
6643 | opcode[2] = 0xe9; | |
6644 | /* We added two extra opcode bytes, and have a two byte | |
6645 | offset. */ | |
6646 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
6647 | fix_new (fragP, old_fr_fix + 2, 2, |
6648 | fragP->fr_symbol, | |
6649 | fragP->fr_offset, 1, | |
6650 | reloc_type); | |
fddf5b5b AM |
6651 | break; |
6652 | } | |
6653 | /* Fall through. */ | |
6654 | ||
6655 | case COND_JUMP: | |
412167cb AM |
6656 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
6657 | { | |
3e02c1cc AM |
6658 | fixS *fixP; |
6659 | ||
412167cb | 6660 | fragP->fr_fix += 1; |
3e02c1cc AM |
6661 | fixP = fix_new (fragP, old_fr_fix, 1, |
6662 | fragP->fr_symbol, | |
6663 | fragP->fr_offset, 1, | |
6664 | BFD_RELOC_8_PCREL); | |
6665 | fixP->fx_signed = 1; | |
412167cb AM |
6666 | break; |
6667 | } | |
93c2a809 | 6668 | |
24eab124 | 6669 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 6670 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 6671 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 6672 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
6673 | /* We've added an opcode byte. */ |
6674 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
6675 | fix_new (fragP, old_fr_fix + 1, size, |
6676 | fragP->fr_symbol, | |
6677 | fragP->fr_offset, 1, | |
6678 | reloc_type); | |
252b5132 | 6679 | break; |
fddf5b5b AM |
6680 | |
6681 | default: | |
6682 | BAD_CASE (fragP->fr_subtype); | |
6683 | break; | |
252b5132 RH |
6684 | } |
6685 | frag_wane (fragP); | |
ee7fcc42 | 6686 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 6687 | } |
93c2a809 | 6688 | |
93c2a809 AM |
6689 | /* Guess size depending on current relax state. Initially the relax |
6690 | state will correspond to a short jump and we return 1, because | |
6691 | the variable part of the frag (the branch offset) is one byte | |
6692 | long. However, we can relax a section more than once and in that | |
6693 | case we must either set fr_subtype back to the unrelaxed state, | |
6694 | or return the value for the appropriate branch. */ | |
6695 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
6696 | } |
6697 | ||
47926f60 KH |
6698 | /* Called after relax() is finished. |
6699 | ||
6700 | In: Address of frag. | |
6701 | fr_type == rs_machine_dependent. | |
6702 | fr_subtype is what the address relaxed to. | |
6703 | ||
6704 | Out: Any fixSs and constants are set up. | |
6705 | Caller will turn frag into a ".space 0". */ | |
6706 | ||
252b5132 RH |
6707 | void |
6708 | md_convert_frag (abfd, sec, fragP) | |
ab9da554 ILT |
6709 | bfd *abfd ATTRIBUTE_UNUSED; |
6710 | segT sec ATTRIBUTE_UNUSED; | |
29b0f896 | 6711 | fragS *fragP; |
252b5132 | 6712 | { |
29b0f896 | 6713 | unsigned char *opcode; |
252b5132 | 6714 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
6715 | offsetT target_address; |
6716 | offsetT opcode_address; | |
252b5132 | 6717 | unsigned int extension = 0; |
847f7ad4 | 6718 | offsetT displacement_from_opcode_start; |
252b5132 RH |
6719 | |
6720 | opcode = (unsigned char *) fragP->fr_opcode; | |
6721 | ||
47926f60 | 6722 | /* Address we want to reach in file space. */ |
252b5132 | 6723 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 6724 | |
47926f60 | 6725 | /* Address opcode resides at in file space. */ |
252b5132 RH |
6726 | opcode_address = fragP->fr_address + fragP->fr_fix; |
6727 | ||
47926f60 | 6728 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
6729 | displacement_from_opcode_start = target_address - opcode_address; |
6730 | ||
fddf5b5b | 6731 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 6732 | { |
47926f60 KH |
6733 | /* Don't have to change opcode. */ |
6734 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 6735 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
6736 | } |
6737 | else | |
6738 | { | |
6739 | if (no_cond_jump_promotion | |
6740 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
6741 | as_warn_where (fragP->fr_file, fragP->fr_line, |
6742 | _("long jump required")); | |
252b5132 | 6743 | |
fddf5b5b AM |
6744 | switch (fragP->fr_subtype) |
6745 | { | |
6746 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
6747 | extension = 4; /* 1 opcode + 4 displacement */ | |
6748 | opcode[0] = 0xe9; | |
6749 | where_to_put_displacement = &opcode[1]; | |
6750 | break; | |
252b5132 | 6751 | |
fddf5b5b AM |
6752 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
6753 | extension = 2; /* 1 opcode + 2 displacement */ | |
6754 | opcode[0] = 0xe9; | |
6755 | where_to_put_displacement = &opcode[1]; | |
6756 | break; | |
252b5132 | 6757 | |
fddf5b5b AM |
6758 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
6759 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
6760 | extension = 5; /* 2 opcode + 4 displacement */ | |
6761 | opcode[1] = opcode[0] + 0x10; | |
6762 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
6763 | where_to_put_displacement = &opcode[2]; | |
6764 | break; | |
252b5132 | 6765 | |
fddf5b5b AM |
6766 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
6767 | extension = 3; /* 2 opcode + 2 displacement */ | |
6768 | opcode[1] = opcode[0] + 0x10; | |
6769 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
6770 | where_to_put_displacement = &opcode[2]; | |
6771 | break; | |
252b5132 | 6772 | |
fddf5b5b AM |
6773 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
6774 | extension = 4; | |
6775 | opcode[0] ^= 1; | |
6776 | opcode[1] = 3; | |
6777 | opcode[2] = 0xe9; | |
6778 | where_to_put_displacement = &opcode[3]; | |
6779 | break; | |
6780 | ||
6781 | default: | |
6782 | BAD_CASE (fragP->fr_subtype); | |
6783 | break; | |
6784 | } | |
252b5132 | 6785 | } |
fddf5b5b | 6786 | |
7b81dfbb AJ |
6787 | /* If size if less then four we are sure that the operand fits, |
6788 | but if it's 4, then it could be that the displacement is larger | |
6789 | then -/+ 2GB. */ | |
6790 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
6791 | && object_64bit | |
6792 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
6793 | + ((addressT) 1 << 31)) |
6794 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
6795 | { |
6796 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
6797 | _("jump target out of range")); | |
6798 | /* Make us emit 0. */ | |
6799 | displacement_from_opcode_start = extension; | |
6800 | } | |
47926f60 | 6801 | /* Now put displacement after opcode. */ |
252b5132 RH |
6802 | md_number_to_chars ((char *) where_to_put_displacement, |
6803 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 6804 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
6805 | fragP->fr_fix += extension; |
6806 | } | |
6807 | \f | |
252b5132 RH |
6808 | /* Apply a fixup (fixS) to segment data, once it has been determined |
6809 | by our caller that we have all the info we need to fix it up. | |
6810 | ||
6811 | On the 386, immediates, displacements, and data pointers are all in | |
6812 | the same (little-endian) format, so we don't need to care about which | |
6813 | we are handling. */ | |
6814 | ||
94f592af | 6815 | void |
55cf6793 | 6816 | md_apply_fix (fixP, valP, seg) |
47926f60 KH |
6817 | /* The fix we're to put in. */ |
6818 | fixS *fixP; | |
47926f60 | 6819 | /* Pointer to the value of the bits. */ |
c6682705 | 6820 | valueT *valP; |
47926f60 KH |
6821 | /* Segment fix is from. */ |
6822 | segT seg ATTRIBUTE_UNUSED; | |
252b5132 | 6823 | { |
94f592af | 6824 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 6825 | valueT value = *valP; |
252b5132 | 6826 | |
f86103b7 | 6827 | #if !defined (TE_Mach) |
93382f6d AM |
6828 | if (fixP->fx_pcrel) |
6829 | { | |
6830 | switch (fixP->fx_r_type) | |
6831 | { | |
5865bb77 ILT |
6832 | default: |
6833 | break; | |
6834 | ||
d6ab8113 JB |
6835 | case BFD_RELOC_64: |
6836 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
6837 | break; | |
93382f6d | 6838 | case BFD_RELOC_32: |
ae8887b5 | 6839 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
6840 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
6841 | break; | |
6842 | case BFD_RELOC_16: | |
6843 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
6844 | break; | |
6845 | case BFD_RELOC_8: | |
6846 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
6847 | break; | |
6848 | } | |
6849 | } | |
252b5132 | 6850 | |
a161fe53 | 6851 | if (fixP->fx_addsy != NULL |
31312f95 | 6852 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 6853 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 AM |
6854 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
6855 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) | |
6856 | && !use_rela_relocations) | |
252b5132 | 6857 | { |
31312f95 AM |
6858 | /* This is a hack. There should be a better way to handle this. |
6859 | This covers for the fact that bfd_install_relocation will | |
6860 | subtract the current location (for partial_inplace, PC relative | |
6861 | relocations); see more below. */ | |
252b5132 | 6862 | #ifndef OBJ_AOUT |
718ddfc0 | 6863 | if (IS_ELF |
252b5132 RH |
6864 | #ifdef TE_PE |
6865 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
6866 | #endif | |
6867 | ) | |
6868 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
6869 | #endif | |
6870 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 6871 | if (IS_ELF) |
252b5132 | 6872 | { |
6539b54b | 6873 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 6874 | |
6539b54b | 6875 | if ((sym_seg == seg |
2f66722d | 6876 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 6877 | && sym_seg != absolute_section)) |
ae6063d4 | 6878 | && !generic_force_reloc (fixP)) |
2f66722d AM |
6879 | { |
6880 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
6881 | bfd_install_relocation subtracts them out again. I think |
6882 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
6883 | it. FIXME. */ |
6884 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
6885 | } | |
252b5132 RH |
6886 | } |
6887 | #endif | |
6888 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
6889 | /* For some reason, the PE format does not store a |
6890 | section address offset for a PC relative symbol. */ | |
6891 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 6892 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
6893 | value += md_pcrel_from (fixP); |
6894 | #endif | |
6895 | } | |
6896 | ||
6897 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 6898 | and we must not disappoint it. */ |
252b5132 | 6899 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 6900 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
6901 | switch (fixP->fx_r_type) |
6902 | { | |
6903 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 6904 | case BFD_RELOC_X86_64_PLT32: |
47926f60 KH |
6905 | /* Make the jump instruction point to the address of the operand. At |
6906 | runtime we merely add the offset to the actual PLT entry. */ | |
6907 | value = -4; | |
6908 | break; | |
31312f95 | 6909 | |
13ae64f3 JJ |
6910 | case BFD_RELOC_386_TLS_GD: |
6911 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 6912 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
6913 | case BFD_RELOC_386_TLS_IE: |
6914 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 6915 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
6916 | case BFD_RELOC_X86_64_TLSGD: |
6917 | case BFD_RELOC_X86_64_TLSLD: | |
6918 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 6919 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
6920 | value = 0; /* Fully resolved at runtime. No addend. */ |
6921 | /* Fallthrough */ | |
6922 | case BFD_RELOC_386_TLS_LE: | |
6923 | case BFD_RELOC_386_TLS_LDO_32: | |
6924 | case BFD_RELOC_386_TLS_LE_32: | |
6925 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 6926 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 6927 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 6928 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
6929 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
6930 | break; | |
6931 | ||
67a4f2b7 AO |
6932 | case BFD_RELOC_386_TLS_DESC_CALL: |
6933 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
6934 | value = 0; /* Fully resolved at runtime. No addend. */ | |
6935 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
6936 | fixP->fx_done = 0; | |
6937 | return; | |
6938 | ||
00f7efb6 JJ |
6939 | case BFD_RELOC_386_GOT32: |
6940 | case BFD_RELOC_X86_64_GOT32: | |
47926f60 KH |
6941 | value = 0; /* Fully resolved at runtime. No addend. */ |
6942 | break; | |
47926f60 KH |
6943 | |
6944 | case BFD_RELOC_VTABLE_INHERIT: | |
6945 | case BFD_RELOC_VTABLE_ENTRY: | |
6946 | fixP->fx_done = 0; | |
94f592af | 6947 | return; |
47926f60 KH |
6948 | |
6949 | default: | |
6950 | break; | |
6951 | } | |
6952 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 6953 | *valP = value; |
f86103b7 | 6954 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 6955 | |
3e73aa7c | 6956 | /* Are we finished with this relocation now? */ |
c6682705 | 6957 | if (fixP->fx_addsy == NULL) |
3e73aa7c JH |
6958 | fixP->fx_done = 1; |
6959 | else if (use_rela_relocations) | |
6960 | { | |
6961 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
6962 | /* Remember value for tc_gen_reloc. */ |
6963 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
6964 | value = 0; |
6965 | } | |
f86103b7 | 6966 | |
94f592af | 6967 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 6968 | } |
252b5132 | 6969 | \f |
252b5132 | 6970 | char * |
499ac353 | 6971 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 6972 | { |
499ac353 NC |
6973 | /* This outputs the LITTLENUMs in REVERSE order; |
6974 | in accord with the bigendian 386. */ | |
6975 | return ieee_md_atof (type, litP, sizeP, FALSE); | |
252b5132 RH |
6976 | } |
6977 | \f | |
2d545b82 | 6978 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 6979 | |
252b5132 | 6980 | static char * |
e3bb37b5 | 6981 | output_invalid (int c) |
252b5132 | 6982 | { |
3882b010 | 6983 | if (ISPRINT (c)) |
f9f21a03 L |
6984 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
6985 | "'%c'", c); | |
252b5132 | 6986 | else |
f9f21a03 | 6987 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 6988 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
6989 | return output_invalid_buf; |
6990 | } | |
6991 | ||
af6bdddf | 6992 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
6993 | |
6994 | static const reg_entry * | |
4d1bb795 | 6995 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 6996 | { |
af6bdddf AM |
6997 | char *s = reg_string; |
6998 | char *p; | |
252b5132 RH |
6999 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
7000 | const reg_entry *r; | |
7001 | ||
7002 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
7003 | if (*s == REGISTER_PREFIX) | |
7004 | ++s; | |
7005 | ||
7006 | if (is_space_char (*s)) | |
7007 | ++s; | |
7008 | ||
7009 | p = reg_name_given; | |
af6bdddf | 7010 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
7011 | { |
7012 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
7013 | return (const reg_entry *) NULL; |
7014 | s++; | |
252b5132 RH |
7015 | } |
7016 | ||
6588847e DN |
7017 | /* For naked regs, make sure that we are not dealing with an identifier. |
7018 | This prevents confusing an identifier like `eax_var' with register | |
7019 | `eax'. */ | |
7020 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
7021 | return (const reg_entry *) NULL; | |
7022 | ||
af6bdddf | 7023 | *end_op = s; |
252b5132 RH |
7024 | |
7025 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
7026 | ||
5f47d35b | 7027 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 7028 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 7029 | { |
5f47d35b AM |
7030 | if (is_space_char (*s)) |
7031 | ++s; | |
7032 | if (*s == '(') | |
7033 | { | |
af6bdddf | 7034 | ++s; |
5f47d35b AM |
7035 | if (is_space_char (*s)) |
7036 | ++s; | |
7037 | if (*s >= '0' && *s <= '7') | |
7038 | { | |
db557034 | 7039 | int fpr = *s - '0'; |
af6bdddf | 7040 | ++s; |
5f47d35b AM |
7041 | if (is_space_char (*s)) |
7042 | ++s; | |
7043 | if (*s == ')') | |
7044 | { | |
7045 | *end_op = s + 1; | |
db557034 AM |
7046 | r = hash_find (reg_hash, "st(0)"); |
7047 | know (r); | |
7048 | return r + fpr; | |
5f47d35b | 7049 | } |
5f47d35b | 7050 | } |
47926f60 | 7051 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
7052 | return (const reg_entry *) NULL; |
7053 | } | |
7054 | } | |
7055 | ||
db51cc60 L |
7056 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ |
7057 | if (r != NULL | |
7058 | && !allow_index_reg | |
7059 | && (r->reg_num == RegEiz || r->reg_num == RegRiz)) | |
7060 | return (const reg_entry *) NULL; | |
7061 | ||
1ae00879 | 7062 | if (r != NULL |
d946b91f | 7063 | && ((r->reg_flags & (RegRex64 | RegRex)) |
40fb9820 L |
7064 | || r->reg_type.bitfield.reg64) |
7065 | && (!cpu_arch_flags.bitfield.cpulm | |
c6fb90c8 | 7066 | || !UINTS_EQUAL (r->reg_type, control)) |
1ae00879 | 7067 | && flag_code != CODE_64BIT) |
20f0a1fc | 7068 | return (const reg_entry *) NULL; |
1ae00879 | 7069 | |
252b5132 RH |
7070 | return r; |
7071 | } | |
4d1bb795 JB |
7072 | |
7073 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
7074 | ||
7075 | static const reg_entry * | |
7076 | parse_register (char *reg_string, char **end_op) | |
7077 | { | |
7078 | const reg_entry *r; | |
7079 | ||
7080 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
7081 | r = parse_real_register (reg_string, end_op); | |
7082 | else | |
7083 | r = NULL; | |
7084 | if (!r) | |
7085 | { | |
7086 | char *save = input_line_pointer; | |
7087 | char c; | |
7088 | symbolS *symbolP; | |
7089 | ||
7090 | input_line_pointer = reg_string; | |
7091 | c = get_symbol_end (); | |
7092 | symbolP = symbol_find (reg_string); | |
7093 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
7094 | { | |
7095 | const expressionS *e = symbol_get_value_expression (symbolP); | |
7096 | ||
7097 | know (e->X_op == O_register); | |
4eed87de | 7098 | know (e->X_add_number >= 0 |
c3fe08fa | 7099 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 JB |
7100 | r = i386_regtab + e->X_add_number; |
7101 | *end_op = input_line_pointer; | |
7102 | } | |
7103 | *input_line_pointer = c; | |
7104 | input_line_pointer = save; | |
7105 | } | |
7106 | return r; | |
7107 | } | |
7108 | ||
7109 | int | |
7110 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
7111 | { | |
7112 | const reg_entry *r; | |
7113 | char *end = input_line_pointer; | |
7114 | ||
7115 | *end = *nextcharP; | |
7116 | r = parse_register (name, &input_line_pointer); | |
7117 | if (r && end <= input_line_pointer) | |
7118 | { | |
7119 | *nextcharP = *input_line_pointer; | |
7120 | *input_line_pointer = 0; | |
7121 | e->X_op = O_register; | |
7122 | e->X_add_number = r - i386_regtab; | |
7123 | return 1; | |
7124 | } | |
7125 | input_line_pointer = end; | |
7126 | *end = 0; | |
7127 | return 0; | |
7128 | } | |
7129 | ||
7130 | void | |
7131 | md_operand (expressionS *e) | |
7132 | { | |
7133 | if (*input_line_pointer == REGISTER_PREFIX) | |
7134 | { | |
7135 | char *end; | |
7136 | const reg_entry *r = parse_real_register (input_line_pointer, &end); | |
7137 | ||
7138 | if (r) | |
7139 | { | |
7140 | e->X_op = O_register; | |
7141 | e->X_add_number = r - i386_regtab; | |
7142 | input_line_pointer = end; | |
7143 | } | |
7144 | } | |
7145 | } | |
7146 | ||
252b5132 | 7147 | \f |
4cc782b5 | 7148 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
12b55ccc | 7149 | const char *md_shortopts = "kVQ:sqn"; |
252b5132 | 7150 | #else |
12b55ccc | 7151 | const char *md_shortopts = "qn"; |
252b5132 | 7152 | #endif |
6e0b89ee | 7153 | |
3e73aa7c | 7154 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
7155 | #define OPTION_64 (OPTION_MD_BASE + 1) |
7156 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
7157 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
7158 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
7159 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
7160 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
7161 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
7162 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
7163 | #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9) | |
b3b91714 | 7164 | |
99ad8390 NC |
7165 | struct option md_longopts[] = |
7166 | { | |
3e73aa7c | 7167 | {"32", no_argument, NULL, OPTION_32}, |
99ad8390 | 7168 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP) |
3e73aa7c | 7169 | {"64", no_argument, NULL, OPTION_64}, |
6e0b89ee | 7170 | #endif |
b3b91714 | 7171 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
7172 | {"march", required_argument, NULL, OPTION_MARCH}, |
7173 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
7174 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
7175 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
7176 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
7177 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
7178 | {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC}, | |
252b5132 RH |
7179 | {NULL, no_argument, NULL, 0} |
7180 | }; | |
7181 | size_t md_longopts_size = sizeof (md_longopts); | |
7182 | ||
7183 | int | |
9103f4f4 | 7184 | md_parse_option (int c, char *arg) |
252b5132 | 7185 | { |
9103f4f4 | 7186 | unsigned int i; |
6305a203 | 7187 | char *arch, *next; |
9103f4f4 | 7188 | |
252b5132 RH |
7189 | switch (c) |
7190 | { | |
12b55ccc L |
7191 | case 'n': |
7192 | optimize_align_code = 0; | |
7193 | break; | |
7194 | ||
a38cf1db AM |
7195 | case 'q': |
7196 | quiet_warnings = 1; | |
252b5132 RH |
7197 | break; |
7198 | ||
7199 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
7200 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
7201 | should be emitted or not. FIXME: Not implemented. */ | |
7202 | case 'Q': | |
252b5132 RH |
7203 | break; |
7204 | ||
7205 | /* -V: SVR4 argument to print version ID. */ | |
7206 | case 'V': | |
7207 | print_version_id (); | |
7208 | break; | |
7209 | ||
a38cf1db AM |
7210 | /* -k: Ignore for FreeBSD compatibility. */ |
7211 | case 'k': | |
252b5132 | 7212 | break; |
4cc782b5 ILT |
7213 | |
7214 | case 's': | |
7215 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 7216 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 7217 | break; |
99ad8390 NC |
7218 | #endif |
7219 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP) | |
3e73aa7c JH |
7220 | case OPTION_64: |
7221 | { | |
7222 | const char **list, **l; | |
7223 | ||
3e73aa7c JH |
7224 | list = bfd_target_list (); |
7225 | for (l = list; *l != NULL; l++) | |
8620418b | 7226 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
99ad8390 NC |
7227 | || strcmp (*l, "coff-x86-64") == 0 |
7228 | || strcmp (*l, "pe-x86-64") == 0 | |
7229 | || strcmp (*l, "pei-x86-64") == 0) | |
6e0b89ee AM |
7230 | { |
7231 | default_arch = "x86_64"; | |
7232 | break; | |
7233 | } | |
3e73aa7c | 7234 | if (*l == NULL) |
6e0b89ee | 7235 | as_fatal (_("No compiled in support for x86_64")); |
3e73aa7c JH |
7236 | free (list); |
7237 | } | |
7238 | break; | |
7239 | #endif | |
252b5132 | 7240 | |
6e0b89ee AM |
7241 | case OPTION_32: |
7242 | default_arch = "i386"; | |
7243 | break; | |
7244 | ||
b3b91714 AM |
7245 | case OPTION_DIVIDE: |
7246 | #ifdef SVR4_COMMENT_CHARS | |
7247 | { | |
7248 | char *n, *t; | |
7249 | const char *s; | |
7250 | ||
7251 | n = (char *) xmalloc (strlen (i386_comment_chars) + 1); | |
7252 | t = n; | |
7253 | for (s = i386_comment_chars; *s != '\0'; s++) | |
7254 | if (*s != '/') | |
7255 | *t++ = *s; | |
7256 | *t = '\0'; | |
7257 | i386_comment_chars = n; | |
7258 | } | |
7259 | #endif | |
7260 | break; | |
7261 | ||
9103f4f4 | 7262 | case OPTION_MARCH: |
6305a203 L |
7263 | arch = xstrdup (arg); |
7264 | do | |
9103f4f4 | 7265 | { |
6305a203 L |
7266 | if (*arch == '.') |
7267 | as_fatal (_("Invalid -march= option: `%s'"), arg); | |
7268 | next = strchr (arch, '+'); | |
7269 | if (next) | |
7270 | *next++ = '\0'; | |
7271 | for (i = 0; i < ARRAY_SIZE (cpu_arch); i++) | |
9103f4f4 | 7272 | { |
6305a203 | 7273 | if (strcmp (arch, cpu_arch [i].name) == 0) |
ccc9c027 | 7274 | { |
6305a203 L |
7275 | /* Processor. */ |
7276 | cpu_arch_name = cpu_arch[i].name; | |
7277 | cpu_sub_arch_name = NULL; | |
7278 | cpu_arch_flags = cpu_arch[i].flags; | |
7279 | cpu_arch_isa = cpu_arch[i].type; | |
7280 | cpu_arch_isa_flags = cpu_arch[i].flags; | |
7281 | if (!cpu_arch_tune_set) | |
7282 | { | |
7283 | cpu_arch_tune = cpu_arch_isa; | |
7284 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
7285 | } | |
7286 | break; | |
7287 | } | |
7288 | else if (*cpu_arch [i].name == '.' | |
7289 | && strcmp (arch, cpu_arch [i].name + 1) == 0) | |
7290 | { | |
7291 | /* ISA entension. */ | |
7292 | i386_cpu_flags flags; | |
7293 | flags = cpu_flags_or (cpu_arch_flags, | |
7294 | cpu_arch[i].flags); | |
7295 | if (!UINTS_EQUAL (flags, cpu_arch_flags)) | |
7296 | { | |
7297 | if (cpu_sub_arch_name) | |
7298 | { | |
7299 | char *name = cpu_sub_arch_name; | |
7300 | cpu_sub_arch_name = concat (name, | |
7301 | cpu_arch[i].name, | |
7302 | NULL); | |
7303 | free (name); | |
7304 | } | |
7305 | else | |
7306 | cpu_sub_arch_name = xstrdup (cpu_arch[i].name); | |
7307 | cpu_arch_flags = flags; | |
7308 | } | |
7309 | break; | |
ccc9c027 | 7310 | } |
9103f4f4 | 7311 | } |
6305a203 L |
7312 | |
7313 | if (i >= ARRAY_SIZE (cpu_arch)) | |
7314 | as_fatal (_("Invalid -march= option: `%s'"), arg); | |
7315 | ||
7316 | arch = next; | |
9103f4f4 | 7317 | } |
6305a203 | 7318 | while (next != NULL ); |
9103f4f4 L |
7319 | break; |
7320 | ||
7321 | case OPTION_MTUNE: | |
7322 | if (*arg == '.') | |
7323 | as_fatal (_("Invalid -mtune= option: `%s'"), arg); | |
7324 | for (i = 0; i < ARRAY_SIZE (cpu_arch); i++) | |
7325 | { | |
7326 | if (strcmp (arg, cpu_arch [i].name) == 0) | |
7327 | { | |
ccc9c027 | 7328 | cpu_arch_tune_set = 1; |
9103f4f4 L |
7329 | cpu_arch_tune = cpu_arch [i].type; |
7330 | cpu_arch_tune_flags = cpu_arch[i].flags; | |
7331 | break; | |
7332 | } | |
7333 | } | |
7334 | if (i >= ARRAY_SIZE (cpu_arch)) | |
7335 | as_fatal (_("Invalid -mtune= option: `%s'"), arg); | |
7336 | break; | |
7337 | ||
1efbbeb4 L |
7338 | case OPTION_MMNEMONIC: |
7339 | if (strcasecmp (arg, "att") == 0) | |
7340 | intel_mnemonic = 0; | |
7341 | else if (strcasecmp (arg, "intel") == 0) | |
7342 | intel_mnemonic = 1; | |
7343 | else | |
7344 | as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg); | |
7345 | break; | |
7346 | ||
7347 | case OPTION_MSYNTAX: | |
7348 | if (strcasecmp (arg, "att") == 0) | |
7349 | intel_syntax = 0; | |
7350 | else if (strcasecmp (arg, "intel") == 0) | |
7351 | intel_syntax = 1; | |
7352 | else | |
7353 | as_fatal (_("Invalid -msyntax= option: `%s'"), arg); | |
7354 | break; | |
7355 | ||
7356 | case OPTION_MINDEX_REG: | |
7357 | allow_index_reg = 1; | |
7358 | break; | |
7359 | ||
7360 | case OPTION_MNAKED_REG: | |
7361 | allow_naked_reg = 1; | |
7362 | break; | |
7363 | ||
7364 | case OPTION_MOLD_GCC: | |
7365 | old_gcc = 1; | |
1efbbeb4 L |
7366 | break; |
7367 | ||
252b5132 RH |
7368 | default: |
7369 | return 0; | |
7370 | } | |
7371 | return 1; | |
7372 | } | |
7373 | ||
7374 | void | |
7375 | md_show_usage (stream) | |
7376 | FILE *stream; | |
7377 | { | |
4cc782b5 ILT |
7378 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
7379 | fprintf (stream, _("\ | |
a38cf1db AM |
7380 | -Q ignored\n\ |
7381 | -V print assembler version number\n\ | |
b3b91714 AM |
7382 | -k ignored\n")); |
7383 | #endif | |
7384 | fprintf (stream, _("\ | |
12b55ccc | 7385 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
7386 | -q quieten some warnings\n")); |
7387 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
7388 | fprintf (stream, _("\ | |
a38cf1db | 7389 | -s ignored\n")); |
b3b91714 | 7390 | #endif |
751d281c L |
7391 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP) |
7392 | fprintf (stream, _("\ | |
7393 | --32/--64 generate 32bit/64bit code\n")); | |
7394 | #endif | |
b3b91714 AM |
7395 | #ifdef SVR4_COMMENT_CHARS |
7396 | fprintf (stream, _("\ | |
7397 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
7398 | #else |
7399 | fprintf (stream, _("\ | |
b3b91714 | 7400 | --divide ignored\n")); |
4cc782b5 | 7401 | #endif |
9103f4f4 | 7402 | fprintf (stream, _("\ |
6305a203 L |
7403 | -march=CPU[,+EXTENSION...]\n\ |
7404 | generate code for CPU and EXTENSION, CPU is one of:\n\ | |
2cb4f3d5 L |
7405 | i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\ |
7406 | pentiumii, pentiumiii, pentium4, prescott, nocona,\n\ | |
7407 | core, core2, k6, k6_2, athlon, k8, amdfam10,\n\ | |
7408 | generic32, generic64\n\ | |
599121aa L |
7409 | EXTENSION is combination of:\n\ |
7410 | mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\ | |
7411 | vmx, smx, 3dnow, 3dnowa, sse4a, sse5, svme, abm,\n\ | |
7412 | padlock\n")); | |
6305a203 | 7413 | fprintf (stream, _("\ |
2cb4f3d5 L |
7414 | -mtune=CPU optimize for CPU, CPU is one of:\n\ |
7415 | i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\ | |
7416 | pentiumii, pentiumiii, pentium4, prescott, nocona,\n\ | |
7417 | core, core2, k6, k6_2, athlon, k8, amdfam10,\n\ | |
7418 | generic32, generic64\n")); | |
ba104c83 L |
7419 | fprintf (stream, _("\ |
7420 | -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n")); | |
7421 | fprintf (stream, _("\ | |
7422 | -msyntax=[att|intel] use AT&T/Intel syntax\n")); | |
7423 | fprintf (stream, _("\ | |
7424 | -mindex-reg support pseudo index registers\n")); | |
7425 | fprintf (stream, _("\ | |
7426 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
7427 | fprintf (stream, _("\ | |
7428 | -mold-gcc support old (<= 2.8.1) versions of gcc\n")); | |
252b5132 RH |
7429 | } |
7430 | ||
3e73aa7c | 7431 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
872ce6ff | 7432 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP)) |
252b5132 RH |
7433 | |
7434 | /* Pick the target format to use. */ | |
7435 | ||
47926f60 | 7436 | const char * |
e3bb37b5 | 7437 | i386_target_format (void) |
252b5132 | 7438 | { |
3e73aa7c | 7439 | if (!strcmp (default_arch, "x86_64")) |
9103f4f4 L |
7440 | { |
7441 | set_code_flag (CODE_64BIT); | |
c6fb90c8 | 7442 | if (UINTS_ALL_ZERO (cpu_arch_isa_flags)) |
40fb9820 L |
7443 | { |
7444 | cpu_arch_isa_flags.bitfield.cpui186 = 1; | |
7445 | cpu_arch_isa_flags.bitfield.cpui286 = 1; | |
7446 | cpu_arch_isa_flags.bitfield.cpui386 = 1; | |
7447 | cpu_arch_isa_flags.bitfield.cpui486 = 1; | |
7448 | cpu_arch_isa_flags.bitfield.cpui586 = 1; | |
7449 | cpu_arch_isa_flags.bitfield.cpui686 = 1; | |
7450 | cpu_arch_isa_flags.bitfield.cpup4 = 1; | |
7451 | cpu_arch_isa_flags.bitfield.cpummx= 1; | |
40fb9820 L |
7452 | cpu_arch_isa_flags.bitfield.cpusse = 1; |
7453 | cpu_arch_isa_flags.bitfield.cpusse2 = 1; | |
7454 | } | |
c6fb90c8 | 7455 | if (UINTS_ALL_ZERO (cpu_arch_tune_flags)) |
40fb9820 L |
7456 | { |
7457 | cpu_arch_tune_flags.bitfield.cpui186 = 1; | |
7458 | cpu_arch_tune_flags.bitfield.cpui286 = 1; | |
7459 | cpu_arch_tune_flags.bitfield.cpui386 = 1; | |
7460 | cpu_arch_tune_flags.bitfield.cpui486 = 1; | |
7461 | cpu_arch_tune_flags.bitfield.cpui586 = 1; | |
7462 | cpu_arch_tune_flags.bitfield.cpui686 = 1; | |
7463 | cpu_arch_tune_flags.bitfield.cpup4 = 1; | |
7464 | cpu_arch_tune_flags.bitfield.cpummx= 1; | |
40fb9820 L |
7465 | cpu_arch_tune_flags.bitfield.cpusse = 1; |
7466 | cpu_arch_tune_flags.bitfield.cpusse2 = 1; | |
7467 | } | |
9103f4f4 | 7468 | } |
3e73aa7c | 7469 | else if (!strcmp (default_arch, "i386")) |
9103f4f4 L |
7470 | { |
7471 | set_code_flag (CODE_32BIT); | |
c6fb90c8 | 7472 | if (UINTS_ALL_ZERO (cpu_arch_isa_flags)) |
40fb9820 L |
7473 | { |
7474 | cpu_arch_isa_flags.bitfield.cpui186 = 1; | |
7475 | cpu_arch_isa_flags.bitfield.cpui286 = 1; | |
7476 | cpu_arch_isa_flags.bitfield.cpui386 = 1; | |
7477 | } | |
c6fb90c8 | 7478 | if (UINTS_ALL_ZERO (cpu_arch_tune_flags)) |
40fb9820 L |
7479 | { |
7480 | cpu_arch_tune_flags.bitfield.cpui186 = 1; | |
7481 | cpu_arch_tune_flags.bitfield.cpui286 = 1; | |
7482 | cpu_arch_tune_flags.bitfield.cpui386 = 1; | |
7483 | } | |
9103f4f4 | 7484 | } |
3e73aa7c JH |
7485 | else |
7486 | as_fatal (_("Unknown architecture")); | |
252b5132 RH |
7487 | switch (OUTPUT_FLAVOR) |
7488 | { | |
872ce6ff L |
7489 | #ifdef TE_PEP |
7490 | case bfd_target_coff_flavour: | |
7491 | return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386"; | |
7492 | break; | |
7493 | #endif | |
4c63da97 AM |
7494 | #ifdef OBJ_MAYBE_AOUT |
7495 | case bfd_target_aout_flavour: | |
47926f60 | 7496 | return AOUT_TARGET_FORMAT; |
4c63da97 AM |
7497 | #endif |
7498 | #ifdef OBJ_MAYBE_COFF | |
252b5132 RH |
7499 | case bfd_target_coff_flavour: |
7500 | return "coff-i386"; | |
4c63da97 | 7501 | #endif |
3e73aa7c | 7502 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 7503 | case bfd_target_elf_flavour: |
3e73aa7c | 7504 | { |
e5cb08ac | 7505 | if (flag_code == CODE_64BIT) |
4fa24527 JB |
7506 | { |
7507 | object_64bit = 1; | |
7508 | use_rela_relocations = 1; | |
7509 | } | |
9d7cbccd | 7510 | return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT; |
3e73aa7c | 7511 | } |
4c63da97 | 7512 | #endif |
252b5132 RH |
7513 | default: |
7514 | abort (); | |
7515 | return NULL; | |
7516 | } | |
7517 | } | |
7518 | ||
47926f60 | 7519 | #endif /* OBJ_MAYBE_ more than one */ |
a847613f AM |
7520 | |
7521 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) | |
e3bb37b5 L |
7522 | void |
7523 | i386_elf_emit_arch_note (void) | |
a847613f | 7524 | { |
718ddfc0 | 7525 | if (IS_ELF && cpu_arch_name != NULL) |
a847613f AM |
7526 | { |
7527 | char *p; | |
7528 | asection *seg = now_seg; | |
7529 | subsegT subseg = now_subseg; | |
7530 | Elf_Internal_Note i_note; | |
7531 | Elf_External_Note e_note; | |
7532 | asection *note_secp; | |
7533 | int len; | |
7534 | ||
7535 | /* Create the .note section. */ | |
7536 | note_secp = subseg_new (".note", 0); | |
7537 | bfd_set_section_flags (stdoutput, | |
7538 | note_secp, | |
7539 | SEC_HAS_CONTENTS | SEC_READONLY); | |
7540 | ||
7541 | /* Process the arch string. */ | |
7542 | len = strlen (cpu_arch_name); | |
7543 | ||
7544 | i_note.namesz = len + 1; | |
7545 | i_note.descsz = 0; | |
7546 | i_note.type = NT_ARCH; | |
7547 | p = frag_more (sizeof (e_note.namesz)); | |
7548 | md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz)); | |
7549 | p = frag_more (sizeof (e_note.descsz)); | |
7550 | md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz)); | |
7551 | p = frag_more (sizeof (e_note.type)); | |
7552 | md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type)); | |
7553 | p = frag_more (len + 1); | |
7554 | strcpy (p, cpu_arch_name); | |
7555 | ||
7556 | frag_align (2, 0, 0); | |
7557 | ||
7558 | subseg_set (seg, subseg); | |
7559 | } | |
7560 | } | |
7561 | #endif | |
252b5132 | 7562 | \f |
252b5132 RH |
7563 | symbolS * |
7564 | md_undefined_symbol (name) | |
7565 | char *name; | |
7566 | { | |
18dc2407 ILT |
7567 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
7568 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
7569 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
7570 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
7571 | { |
7572 | if (!GOT_symbol) | |
7573 | { | |
7574 | if (symbol_find (name)) | |
7575 | as_bad (_("GOT already in symbol table")); | |
7576 | GOT_symbol = symbol_new (name, undefined_section, | |
7577 | (valueT) 0, &zero_address_frag); | |
7578 | }; | |
7579 | return GOT_symbol; | |
7580 | } | |
252b5132 RH |
7581 | return 0; |
7582 | } | |
7583 | ||
7584 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 7585 | |
252b5132 RH |
7586 | valueT |
7587 | md_section_align (segment, size) | |
ab9da554 | 7588 | segT segment ATTRIBUTE_UNUSED; |
252b5132 RH |
7589 | valueT size; |
7590 | { | |
4c63da97 AM |
7591 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
7592 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
7593 | { | |
7594 | /* For a.out, force the section size to be aligned. If we don't do | |
7595 | this, BFD will align it for us, but it will not write out the | |
7596 | final bytes of the section. This may be a bug in BFD, but it is | |
7597 | easier to fix it here since that is how the other a.out targets | |
7598 | work. */ | |
7599 | int align; | |
7600 | ||
7601 | align = bfd_get_section_alignment (stdoutput, segment); | |
7602 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
7603 | } | |
252b5132 RH |
7604 | #endif |
7605 | ||
7606 | return size; | |
7607 | } | |
7608 | ||
7609 | /* On the i386, PC-relative offsets are relative to the start of the | |
7610 | next instruction. That is, the address of the offset, plus its | |
7611 | size, since the offset is always the last part of the insn. */ | |
7612 | ||
7613 | long | |
e3bb37b5 | 7614 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
7615 | { |
7616 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
7617 | } | |
7618 | ||
7619 | #ifndef I386COFF | |
7620 | ||
7621 | static void | |
e3bb37b5 | 7622 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 7623 | { |
29b0f896 | 7624 | int temp; |
252b5132 | 7625 | |
8a75718c JB |
7626 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
7627 | if (IS_ELF) | |
7628 | obj_elf_section_change_hook (); | |
7629 | #endif | |
252b5132 RH |
7630 | temp = get_absolute_expression (); |
7631 | subseg_set (bss_section, (subsegT) temp); | |
7632 | demand_empty_rest_of_line (); | |
7633 | } | |
7634 | ||
7635 | #endif | |
7636 | ||
252b5132 | 7637 | void |
e3bb37b5 | 7638 | i386_validate_fix (fixS *fixp) |
252b5132 RH |
7639 | { |
7640 | if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) | |
7641 | { | |
23df1078 JH |
7642 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
7643 | { | |
4fa24527 | 7644 | if (!object_64bit) |
23df1078 JH |
7645 | abort (); |
7646 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
7647 | } | |
7648 | else | |
7649 | { | |
4fa24527 | 7650 | if (!object_64bit) |
d6ab8113 JB |
7651 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; |
7652 | else | |
7653 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
23df1078 | 7654 | } |
252b5132 RH |
7655 | fixp->fx_subsy = 0; |
7656 | } | |
7657 | } | |
7658 | ||
252b5132 RH |
7659 | arelent * |
7660 | tc_gen_reloc (section, fixp) | |
ab9da554 | 7661 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
7662 | fixS *fixp; |
7663 | { | |
7664 | arelent *rel; | |
7665 | bfd_reloc_code_real_type code; | |
7666 | ||
7667 | switch (fixp->fx_r_type) | |
7668 | { | |
3e73aa7c JH |
7669 | case BFD_RELOC_X86_64_PLT32: |
7670 | case BFD_RELOC_X86_64_GOT32: | |
7671 | case BFD_RELOC_X86_64_GOTPCREL: | |
252b5132 RH |
7672 | case BFD_RELOC_386_PLT32: |
7673 | case BFD_RELOC_386_GOT32: | |
7674 | case BFD_RELOC_386_GOTOFF: | |
7675 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
7676 | case BFD_RELOC_386_TLS_GD: |
7677 | case BFD_RELOC_386_TLS_LDM: | |
7678 | case BFD_RELOC_386_TLS_LDO_32: | |
7679 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
7680 | case BFD_RELOC_386_TLS_IE: |
7681 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
7682 | case BFD_RELOC_386_TLS_LE_32: |
7683 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
7684 | case BFD_RELOC_386_TLS_GOTDESC: |
7685 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
7686 | case BFD_RELOC_X86_64_TLSGD: |
7687 | case BFD_RELOC_X86_64_TLSLD: | |
7688 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 7689 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
7690 | case BFD_RELOC_X86_64_GOTTPOFF: |
7691 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
7692 | case BFD_RELOC_X86_64_TPOFF64: |
7693 | case BFD_RELOC_X86_64_GOTOFF64: | |
7694 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
7695 | case BFD_RELOC_X86_64_GOT64: |
7696 | case BFD_RELOC_X86_64_GOTPCREL64: | |
7697 | case BFD_RELOC_X86_64_GOTPC64: | |
7698 | case BFD_RELOC_X86_64_GOTPLT64: | |
7699 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
7700 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
7701 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
7702 | case BFD_RELOC_RVA: |
7703 | case BFD_RELOC_VTABLE_ENTRY: | |
7704 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
7705 | #ifdef TE_PE |
7706 | case BFD_RELOC_32_SECREL: | |
7707 | #endif | |
252b5132 RH |
7708 | code = fixp->fx_r_type; |
7709 | break; | |
dbbaec26 L |
7710 | case BFD_RELOC_X86_64_32S: |
7711 | if (!fixp->fx_pcrel) | |
7712 | { | |
7713 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
7714 | code = fixp->fx_r_type; | |
7715 | break; | |
7716 | } | |
252b5132 | 7717 | default: |
93382f6d | 7718 | if (fixp->fx_pcrel) |
252b5132 | 7719 | { |
93382f6d AM |
7720 | switch (fixp->fx_size) |
7721 | { | |
7722 | default: | |
b091f402 AM |
7723 | as_bad_where (fixp->fx_file, fixp->fx_line, |
7724 | _("can not do %d byte pc-relative relocation"), | |
7725 | fixp->fx_size); | |
93382f6d AM |
7726 | code = BFD_RELOC_32_PCREL; |
7727 | break; | |
7728 | case 1: code = BFD_RELOC_8_PCREL; break; | |
7729 | case 2: code = BFD_RELOC_16_PCREL; break; | |
7730 | case 4: code = BFD_RELOC_32_PCREL; break; | |
d6ab8113 JB |
7731 | #ifdef BFD64 |
7732 | case 8: code = BFD_RELOC_64_PCREL; break; | |
7733 | #endif | |
93382f6d AM |
7734 | } |
7735 | } | |
7736 | else | |
7737 | { | |
7738 | switch (fixp->fx_size) | |
7739 | { | |
7740 | default: | |
b091f402 AM |
7741 | as_bad_where (fixp->fx_file, fixp->fx_line, |
7742 | _("can not do %d byte relocation"), | |
7743 | fixp->fx_size); | |
93382f6d AM |
7744 | code = BFD_RELOC_32; |
7745 | break; | |
7746 | case 1: code = BFD_RELOC_8; break; | |
7747 | case 2: code = BFD_RELOC_16; break; | |
7748 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 7749 | #ifdef BFD64 |
3e73aa7c | 7750 | case 8: code = BFD_RELOC_64; break; |
937149dd | 7751 | #endif |
93382f6d | 7752 | } |
252b5132 RH |
7753 | } |
7754 | break; | |
7755 | } | |
252b5132 | 7756 | |
d182319b JB |
7757 | if ((code == BFD_RELOC_32 |
7758 | || code == BFD_RELOC_32_PCREL | |
7759 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
7760 | && GOT_symbol |
7761 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 7762 | { |
4fa24527 | 7763 | if (!object_64bit) |
d6ab8113 JB |
7764 | code = BFD_RELOC_386_GOTPC; |
7765 | else | |
7766 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 7767 | } |
7b81dfbb AJ |
7768 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
7769 | && GOT_symbol | |
7770 | && fixp->fx_addsy == GOT_symbol) | |
7771 | { | |
7772 | code = BFD_RELOC_X86_64_GOTPC64; | |
7773 | } | |
252b5132 RH |
7774 | |
7775 | rel = (arelent *) xmalloc (sizeof (arelent)); | |
49309057 ILT |
7776 | rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
7777 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
7778 | |
7779 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 7780 | |
3e73aa7c JH |
7781 | if (!use_rela_relocations) |
7782 | { | |
7783 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
7784 | vtable entry to be used in the relocation's section offset. */ | |
7785 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
7786 | rel->address = fixp->fx_offset; | |
252b5132 | 7787 | |
c6682705 | 7788 | rel->addend = 0; |
3e73aa7c JH |
7789 | } |
7790 | /* Use the rela in 64bit mode. */ | |
252b5132 | 7791 | else |
3e73aa7c | 7792 | { |
062cd5e7 AS |
7793 | if (!fixp->fx_pcrel) |
7794 | rel->addend = fixp->fx_offset; | |
7795 | else | |
7796 | switch (code) | |
7797 | { | |
7798 | case BFD_RELOC_X86_64_PLT32: | |
7799 | case BFD_RELOC_X86_64_GOT32: | |
7800 | case BFD_RELOC_X86_64_GOTPCREL: | |
bffbf940 JJ |
7801 | case BFD_RELOC_X86_64_TLSGD: |
7802 | case BFD_RELOC_X86_64_TLSLD: | |
7803 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
7804 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
7805 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
7806 | rel->addend = fixp->fx_offset - fixp->fx_size; |
7807 | break; | |
7808 | default: | |
7809 | rel->addend = (section->vma | |
7810 | - fixp->fx_size | |
7811 | + fixp->fx_addnumber | |
7812 | + md_pcrel_from (fixp)); | |
7813 | break; | |
7814 | } | |
3e73aa7c JH |
7815 | } |
7816 | ||
252b5132 RH |
7817 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
7818 | if (rel->howto == NULL) | |
7819 | { | |
7820 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 7821 | _("cannot represent relocation type %s"), |
252b5132 RH |
7822 | bfd_get_reloc_code_name (code)); |
7823 | /* Set howto to a garbage value so that we can keep going. */ | |
7824 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
7825 | assert (rel->howto != NULL); | |
7826 | } | |
7827 | ||
7828 | return rel; | |
7829 | } | |
7830 | ||
64a0c779 DN |
7831 | \f |
7832 | /* Parse operands using Intel syntax. This implements a recursive descent | |
7833 | parser based on the BNF grammar published in Appendix B of the MASM 6.1 | |
7834 | Programmer's Guide. | |
7835 | ||
7836 | FIXME: We do not recognize the full operand grammar defined in the MASM | |
7837 | documentation. In particular, all the structure/union and | |
7838 | high-level macro operands are missing. | |
7839 | ||
7840 | Uppercase words are terminals, lower case words are non-terminals. | |
7841 | Objects surrounded by double brackets '[[' ']]' are optional. Vertical | |
7842 | bars '|' denote choices. Most grammar productions are implemented in | |
7843 | functions called 'intel_<production>'. | |
7844 | ||
7845 | Initial production is 'expr'. | |
7846 | ||
9306ca4a | 7847 | addOp + | - |
64a0c779 DN |
7848 | |
7849 | alpha [a-zA-Z] | |
7850 | ||
9306ca4a JB |
7851 | binOp & | AND | \| | OR | ^ | XOR |
7852 | ||
64a0c779 DN |
7853 | byteRegister AL | AH | BL | BH | CL | CH | DL | DH |
7854 | ||
7855 | constant digits [[ radixOverride ]] | |
7856 | ||
9306ca4a | 7857 | dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD |
64a0c779 DN |
7858 | |
7859 | digits decdigit | |
b77a7acd AJ |
7860 | | digits decdigit |
7861 | | digits hexdigit | |
64a0c779 DN |
7862 | |
7863 | decdigit [0-9] | |
7864 | ||
9306ca4a JB |
7865 | e04 e04 addOp e05 |
7866 | | e05 | |
7867 | ||
7868 | e05 e05 binOp e06 | |
b77a7acd | 7869 | | e06 |
64a0c779 DN |
7870 | |
7871 | e06 e06 mulOp e09 | |
b77a7acd | 7872 | | e09 |
64a0c779 DN |
7873 | |
7874 | e09 OFFSET e10 | |
a724f0f4 JB |
7875 | | SHORT e10 |
7876 | | + e10 | |
7877 | | - e10 | |
9306ca4a JB |
7878 | | ~ e10 |
7879 | | NOT e10 | |
64a0c779 DN |
7880 | | e09 PTR e10 |
7881 | | e09 : e10 | |
7882 | | e10 | |
7883 | ||
7884 | e10 e10 [ expr ] | |
b77a7acd | 7885 | | e11 |
64a0c779 DN |
7886 | |
7887 | e11 ( expr ) | |
b77a7acd | 7888 | | [ expr ] |
64a0c779 DN |
7889 | | constant |
7890 | | dataType | |
7891 | | id | |
7892 | | $ | |
7893 | | register | |
7894 | ||
a724f0f4 | 7895 | => expr expr cmpOp e04 |
9306ca4a | 7896 | | e04 |
64a0c779 DN |
7897 | |
7898 | gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX | |
b77a7acd | 7899 | | BP | EBP | SP | ESP | DI | EDI | SI | ESI |
64a0c779 DN |
7900 | |
7901 | hexdigit a | b | c | d | e | f | |
b77a7acd | 7902 | | A | B | C | D | E | F |
64a0c779 DN |
7903 | |
7904 | id alpha | |
b77a7acd | 7905 | | id alpha |
64a0c779 DN |
7906 | | id decdigit |
7907 | ||
9306ca4a | 7908 | mulOp * | / | % | MOD | << | SHL | >> | SHR |
64a0c779 DN |
7909 | |
7910 | quote " | ' | |
7911 | ||
7912 | register specialRegister | |
b77a7acd | 7913 | | gpRegister |
64a0c779 DN |
7914 | | byteRegister |
7915 | ||
7916 | segmentRegister CS | DS | ES | FS | GS | SS | |
7917 | ||
9306ca4a | 7918 | specialRegister CR0 | CR2 | CR3 | CR4 |
b77a7acd | 7919 | | DR0 | DR1 | DR2 | DR3 | DR6 | DR7 |
64a0c779 DN |
7920 | | TR3 | TR4 | TR5 | TR6 | TR7 |
7921 | ||
64a0c779 DN |
7922 | We simplify the grammar in obvious places (e.g., register parsing is |
7923 | done by calling parse_register) and eliminate immediate left recursion | |
7924 | to implement a recursive-descent parser. | |
7925 | ||
a724f0f4 JB |
7926 | expr e04 expr' |
7927 | ||
7928 | expr' cmpOp e04 expr' | |
7929 | | Empty | |
9306ca4a JB |
7930 | |
7931 | e04 e05 e04' | |
7932 | ||
7933 | e04' addOp e05 e04' | |
7934 | | Empty | |
64a0c779 DN |
7935 | |
7936 | e05 e06 e05' | |
7937 | ||
9306ca4a | 7938 | e05' binOp e06 e05' |
b77a7acd | 7939 | | Empty |
64a0c779 DN |
7940 | |
7941 | e06 e09 e06' | |
7942 | ||
7943 | e06' mulOp e09 e06' | |
b77a7acd | 7944 | | Empty |
64a0c779 DN |
7945 | |
7946 | e09 OFFSET e10 e09' | |
a724f0f4 JB |
7947 | | SHORT e10' |
7948 | | + e10' | |
7949 | | - e10' | |
7950 | | ~ e10' | |
7951 | | NOT e10' | |
b77a7acd | 7952 | | e10 e09' |
64a0c779 DN |
7953 | |
7954 | e09' PTR e10 e09' | |
b77a7acd | 7955 | | : e10 e09' |
64a0c779 DN |
7956 | | Empty |
7957 | ||
7958 | e10 e11 e10' | |
7959 | ||
7960 | e10' [ expr ] e10' | |
b77a7acd | 7961 | | Empty |
64a0c779 DN |
7962 | |
7963 | e11 ( expr ) | |
b77a7acd | 7964 | | [ expr ] |
64a0c779 DN |
7965 | | BYTE |
7966 | | WORD | |
7967 | | DWORD | |
9306ca4a | 7968 | | FWORD |
64a0c779 | 7969 | | QWORD |
9306ca4a JB |
7970 | | TBYTE |
7971 | | OWORD | |
7972 | | XMMWORD | |
64a0c779 DN |
7973 | | . |
7974 | | $ | |
7975 | | register | |
7976 | | id | |
7977 | | constant */ | |
7978 | ||
7979 | /* Parsing structure for the intel syntax parser. Used to implement the | |
7980 | semantic actions for the operand grammar. */ | |
7981 | struct intel_parser_s | |
7982 | { | |
7983 | char *op_string; /* The string being parsed. */ | |
7984 | int got_a_float; /* Whether the operand is a float. */ | |
4a1805b1 | 7985 | int op_modifier; /* Operand modifier. */ |
64a0c779 | 7986 | int is_mem; /* 1 if operand is memory reference. */ |
4eed87de AM |
7987 | int in_offset; /* >=1 if parsing operand of offset. */ |
7988 | int in_bracket; /* >=1 if parsing operand in brackets. */ | |
64a0c779 DN |
7989 | const reg_entry *reg; /* Last register reference found. */ |
7990 | char *disp; /* Displacement string being built. */ | |
a724f0f4 | 7991 | char *next_operand; /* Resume point when splitting operands. */ |
64a0c779 DN |
7992 | }; |
7993 | ||
7994 | static struct intel_parser_s intel_parser; | |
7995 | ||
7996 | /* Token structure for parsing intel syntax. */ | |
7997 | struct intel_token | |
7998 | { | |
7999 | int code; /* Token code. */ | |
8000 | const reg_entry *reg; /* Register entry for register tokens. */ | |
8001 | char *str; /* String representation. */ | |
8002 | }; | |
8003 | ||
8004 | static struct intel_token cur_token, prev_token; | |
8005 | ||
50705ef4 AM |
8006 | /* Token codes for the intel parser. Since T_SHORT is already used |
8007 | by COFF, undefine it first to prevent a warning. */ | |
64a0c779 DN |
8008 | #define T_NIL -1 |
8009 | #define T_CONST 1 | |
8010 | #define T_REG 2 | |
8011 | #define T_BYTE 3 | |
8012 | #define T_WORD 4 | |
9306ca4a JB |
8013 | #define T_DWORD 5 |
8014 | #define T_FWORD 6 | |
8015 | #define T_QWORD 7 | |
8016 | #define T_TBYTE 8 | |
8017 | #define T_XMMWORD 9 | |
50705ef4 | 8018 | #undef T_SHORT |
9306ca4a JB |
8019 | #define T_SHORT 10 |
8020 | #define T_OFFSET 11 | |
8021 | #define T_PTR 12 | |
8022 | #define T_ID 13 | |
8023 | #define T_SHL 14 | |
8024 | #define T_SHR 15 | |
64a0c779 DN |
8025 | |
8026 | /* Prototypes for intel parser functions. */ | |
e3bb37b5 L |
8027 | static int intel_match_token (int); |
8028 | static void intel_putback_token (void); | |
8029 | static void intel_get_token (void); | |
8030 | static int intel_expr (void); | |
8031 | static int intel_e04 (void); | |
8032 | static int intel_e05 (void); | |
8033 | static int intel_e06 (void); | |
8034 | static int intel_e09 (void); | |
8035 | static int intel_e10 (void); | |
8036 | static int intel_e11 (void); | |
64a0c779 | 8037 | |
64a0c779 | 8038 | static int |
e3bb37b5 | 8039 | i386_intel_operand (char *operand_string, int got_a_float) |
64a0c779 DN |
8040 | { |
8041 | int ret; | |
8042 | char *p; | |
8043 | ||
a724f0f4 JB |
8044 | p = intel_parser.op_string = xstrdup (operand_string); |
8045 | intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1); | |
8046 | ||
8047 | for (;;) | |
64a0c779 | 8048 | { |
a724f0f4 JB |
8049 | /* Initialize token holders. */ |
8050 | cur_token.code = prev_token.code = T_NIL; | |
8051 | cur_token.reg = prev_token.reg = NULL; | |
8052 | cur_token.str = prev_token.str = NULL; | |
8053 | ||
8054 | /* Initialize parser structure. */ | |
8055 | intel_parser.got_a_float = got_a_float; | |
8056 | intel_parser.op_modifier = 0; | |
8057 | intel_parser.is_mem = 0; | |
8058 | intel_parser.in_offset = 0; | |
8059 | intel_parser.in_bracket = 0; | |
8060 | intel_parser.reg = NULL; | |
8061 | intel_parser.disp[0] = '\0'; | |
8062 | intel_parser.next_operand = NULL; | |
8063 | ||
8064 | /* Read the first token and start the parser. */ | |
8065 | intel_get_token (); | |
8066 | ret = intel_expr (); | |
8067 | ||
8068 | if (!ret) | |
8069 | break; | |
8070 | ||
9306ca4a JB |
8071 | if (cur_token.code != T_NIL) |
8072 | { | |
8073 | as_bad (_("invalid operand for '%s' ('%s' unexpected)"), | |
8074 | current_templates->start->name, cur_token.str); | |
8075 | ret = 0; | |
8076 | } | |
64a0c779 DN |
8077 | /* If we found a memory reference, hand it over to i386_displacement |
8078 | to fill in the rest of the operand fields. */ | |
9306ca4a | 8079 | else if (intel_parser.is_mem) |
64a0c779 DN |
8080 | { |
8081 | if ((i.mem_operands == 1 | |
40fb9820 | 8082 | && !current_templates->start->opcode_modifier.isstring) |
64a0c779 DN |
8083 | || i.mem_operands == 2) |
8084 | { | |
8085 | as_bad (_("too many memory references for '%s'"), | |
8086 | current_templates->start->name); | |
8087 | ret = 0; | |
8088 | } | |
8089 | else | |
8090 | { | |
8091 | char *s = intel_parser.disp; | |
5c07affc | 8092 | i.types[this_operand].bitfield.mem = 1; |
64a0c779 DN |
8093 | i.mem_operands++; |
8094 | ||
a724f0f4 JB |
8095 | if (!quiet_warnings && intel_parser.is_mem < 0) |
8096 | /* See the comments in intel_bracket_expr. */ | |
8097 | as_warn (_("Treating `%s' as memory reference"), operand_string); | |
8098 | ||
64a0c779 DN |
8099 | /* Add the displacement expression. */ |
8100 | if (*s != '\0') | |
a4622f40 AM |
8101 | ret = i386_displacement (s, s + strlen (s)); |
8102 | if (ret) | |
a724f0f4 JB |
8103 | { |
8104 | /* Swap base and index in 16-bit memory operands like | |
8105 | [si+bx]. Since i386_index_check is also used in AT&T | |
8106 | mode we have to do that here. */ | |
8107 | if (i.base_reg | |
8108 | && i.index_reg | |
40fb9820 L |
8109 | && i.base_reg->reg_type.bitfield.reg16 |
8110 | && i.index_reg->reg_type.bitfield.reg16 | |
a724f0f4 JB |
8111 | && i.base_reg->reg_num >= 6 |
8112 | && i.index_reg->reg_num < 6) | |
8113 | { | |
8114 | const reg_entry *base = i.index_reg; | |
8115 | ||
8116 | i.index_reg = i.base_reg; | |
8117 | i.base_reg = base; | |
8118 | } | |
8119 | ret = i386_index_check (operand_string); | |
8120 | } | |
64a0c779 DN |
8121 | } |
8122 | } | |
8123 | ||
8124 | /* Constant and OFFSET expressions are handled by i386_immediate. */ | |
a724f0f4 | 8125 | else if ((intel_parser.op_modifier & (1 << T_OFFSET)) |
64a0c779 DN |
8126 | || intel_parser.reg == NULL) |
8127 | ret = i386_immediate (intel_parser.disp); | |
a724f0f4 JB |
8128 | |
8129 | if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1) | |
4eed87de | 8130 | ret = 0; |
a724f0f4 JB |
8131 | if (!ret || !intel_parser.next_operand) |
8132 | break; | |
8133 | intel_parser.op_string = intel_parser.next_operand; | |
8134 | this_operand = i.operands++; | |
7d5e4556 | 8135 | i.types[this_operand].bitfield.unspecified = 1; |
64a0c779 DN |
8136 | } |
8137 | ||
8138 | free (p); | |
8139 | free (intel_parser.disp); | |
8140 | ||
8141 | return ret; | |
8142 | } | |
8143 | ||
a724f0f4 JB |
8144 | #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg) |
8145 | ||
8146 | /* expr e04 expr' | |
8147 | ||
8148 | expr' cmpOp e04 expr' | |
8149 | | Empty */ | |
64a0c779 | 8150 | static int |
e3bb37b5 | 8151 | intel_expr (void) |
64a0c779 | 8152 | { |
a724f0f4 JB |
8153 | /* XXX Implement the comparison operators. */ |
8154 | return intel_e04 (); | |
9306ca4a JB |
8155 | } |
8156 | ||
a724f0f4 | 8157 | /* e04 e05 e04' |
9306ca4a | 8158 | |
a724f0f4 | 8159 | e04' addOp e05 e04' |
9306ca4a JB |
8160 | | Empty */ |
8161 | static int | |
e3bb37b5 | 8162 | intel_e04 (void) |
9306ca4a | 8163 | { |
a724f0f4 | 8164 | int nregs = -1; |
9306ca4a | 8165 | |
a724f0f4 | 8166 | for (;;) |
9306ca4a | 8167 | { |
a724f0f4 JB |
8168 | if (!intel_e05()) |
8169 | return 0; | |
9306ca4a | 8170 | |
a724f0f4 JB |
8171 | if (nregs >= 0 && NUM_ADDRESS_REGS > nregs) |
8172 | i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */ | |
9306ca4a | 8173 | |
a724f0f4 JB |
8174 | if (cur_token.code == '+') |
8175 | nregs = -1; | |
8176 | else if (cur_token.code == '-') | |
8177 | nregs = NUM_ADDRESS_REGS; | |
8178 | else | |
8179 | return 1; | |
64a0c779 | 8180 | |
a724f0f4 JB |
8181 | strcat (intel_parser.disp, cur_token.str); |
8182 | intel_match_token (cur_token.code); | |
8183 | } | |
64a0c779 DN |
8184 | } |
8185 | ||
64a0c779 DN |
8186 | /* e05 e06 e05' |
8187 | ||
9306ca4a | 8188 | e05' binOp e06 e05' |
64a0c779 DN |
8189 | | Empty */ |
8190 | static int | |
e3bb37b5 | 8191 | intel_e05 (void) |
64a0c779 | 8192 | { |
a724f0f4 | 8193 | int nregs = ~NUM_ADDRESS_REGS; |
64a0c779 | 8194 | |
a724f0f4 | 8195 | for (;;) |
64a0c779 | 8196 | { |
a724f0f4 JB |
8197 | if (!intel_e06()) |
8198 | return 0; | |
8199 | ||
4eed87de AM |
8200 | if (cur_token.code == '&' |
8201 | || cur_token.code == '|' | |
8202 | || cur_token.code == '^') | |
a724f0f4 JB |
8203 | { |
8204 | char str[2]; | |
8205 | ||
8206 | str[0] = cur_token.code; | |
8207 | str[1] = 0; | |
8208 | strcat (intel_parser.disp, str); | |
8209 | } | |
8210 | else | |
8211 | break; | |
9306ca4a | 8212 | |
64a0c779 DN |
8213 | intel_match_token (cur_token.code); |
8214 | ||
a724f0f4 JB |
8215 | if (nregs < 0) |
8216 | nregs = ~nregs; | |
64a0c779 | 8217 | } |
a724f0f4 JB |
8218 | if (nregs >= 0 && NUM_ADDRESS_REGS > nregs) |
8219 | i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */ | |
8220 | return 1; | |
4a1805b1 | 8221 | } |
64a0c779 DN |
8222 | |
8223 | /* e06 e09 e06' | |
8224 | ||
8225 | e06' mulOp e09 e06' | |
b77a7acd | 8226 | | Empty */ |
64a0c779 | 8227 | static int |
e3bb37b5 | 8228 | intel_e06 (void) |
64a0c779 | 8229 | { |
a724f0f4 | 8230 | int nregs = ~NUM_ADDRESS_REGS; |
64a0c779 | 8231 | |
a724f0f4 | 8232 | for (;;) |
64a0c779 | 8233 | { |
a724f0f4 JB |
8234 | if (!intel_e09()) |
8235 | return 0; | |
9306ca4a | 8236 | |
4eed87de AM |
8237 | if (cur_token.code == '*' |
8238 | || cur_token.code == '/' | |
8239 | || cur_token.code == '%') | |
a724f0f4 JB |
8240 | { |
8241 | char str[2]; | |
9306ca4a | 8242 | |
a724f0f4 JB |
8243 | str[0] = cur_token.code; |
8244 | str[1] = 0; | |
8245 | strcat (intel_parser.disp, str); | |
8246 | } | |
8247 | else if (cur_token.code == T_SHL) | |
8248 | strcat (intel_parser.disp, "<<"); | |
8249 | else if (cur_token.code == T_SHR) | |
8250 | strcat (intel_parser.disp, ">>"); | |
8251 | else | |
8252 | break; | |
9306ca4a | 8253 | |
64e74474 | 8254 | intel_match_token (cur_token.code); |
64a0c779 | 8255 | |
a724f0f4 JB |
8256 | if (nregs < 0) |
8257 | nregs = ~nregs; | |
64a0c779 | 8258 | } |
a724f0f4 JB |
8259 | if (nregs >= 0 && NUM_ADDRESS_REGS > nregs) |
8260 | i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */ | |
8261 | return 1; | |
64a0c779 DN |
8262 | } |
8263 | ||
a724f0f4 JB |
8264 | /* e09 OFFSET e09 |
8265 | | SHORT e09 | |
8266 | | + e09 | |
8267 | | - e09 | |
8268 | | ~ e09 | |
8269 | | NOT e09 | |
9306ca4a JB |
8270 | | e10 e09' |
8271 | ||
64a0c779 | 8272 | e09' PTR e10 e09' |
b77a7acd | 8273 | | : e10 e09' |
64a0c779 DN |
8274 | | Empty */ |
8275 | static int | |
e3bb37b5 | 8276 | intel_e09 (void) |
64a0c779 | 8277 | { |
a724f0f4 JB |
8278 | int nregs = ~NUM_ADDRESS_REGS; |
8279 | int in_offset = 0; | |
8280 | ||
8281 | for (;;) | |
64a0c779 | 8282 | { |
a724f0f4 JB |
8283 | /* Don't consume constants here. */ |
8284 | if (cur_token.code == '+' || cur_token.code == '-') | |
8285 | { | |
8286 | /* Need to look one token ahead - if the next token | |
8287 | is a constant, the current token is its sign. */ | |
8288 | int next_code; | |
8289 | ||
8290 | intel_match_token (cur_token.code); | |
8291 | next_code = cur_token.code; | |
8292 | intel_putback_token (); | |
8293 | if (next_code == T_CONST) | |
8294 | break; | |
8295 | } | |
8296 | ||
8297 | /* e09 OFFSET e09 */ | |
8298 | if (cur_token.code == T_OFFSET) | |
8299 | { | |
8300 | if (!in_offset++) | |
8301 | ++intel_parser.in_offset; | |
8302 | } | |
8303 | ||
8304 | /* e09 SHORT e09 */ | |
8305 | else if (cur_token.code == T_SHORT) | |
8306 | intel_parser.op_modifier |= 1 << T_SHORT; | |
8307 | ||
8308 | /* e09 + e09 */ | |
8309 | else if (cur_token.code == '+') | |
8310 | strcat (intel_parser.disp, "+"); | |
8311 | ||
8312 | /* e09 - e09 | |
8313 | | ~ e09 | |
8314 | | NOT e09 */ | |
8315 | else if (cur_token.code == '-' || cur_token.code == '~') | |
8316 | { | |
8317 | char str[2]; | |
64a0c779 | 8318 | |
a724f0f4 JB |
8319 | if (nregs < 0) |
8320 | nregs = ~nregs; | |
8321 | str[0] = cur_token.code; | |
8322 | str[1] = 0; | |
8323 | strcat (intel_parser.disp, str); | |
8324 | } | |
8325 | ||
8326 | /* e09 e10 e09' */ | |
8327 | else | |
8328 | break; | |
8329 | ||
8330 | intel_match_token (cur_token.code); | |
64a0c779 DN |
8331 | } |
8332 | ||
a724f0f4 | 8333 | for (;;) |
9306ca4a | 8334 | { |
a724f0f4 JB |
8335 | if (!intel_e10 ()) |
8336 | return 0; | |
9306ca4a | 8337 | |
a724f0f4 JB |
8338 | /* e09' PTR e10 e09' */ |
8339 | if (cur_token.code == T_PTR) | |
8340 | { | |
8341 | char suffix; | |
9306ca4a | 8342 | |
a724f0f4 | 8343 | if (prev_token.code == T_BYTE) |
7d5e4556 L |
8344 | { |
8345 | suffix = BYTE_MNEM_SUFFIX; | |
8346 | i.types[this_operand].bitfield.byte = 1; | |
8347 | } | |
9306ca4a | 8348 | |
a724f0f4 JB |
8349 | else if (prev_token.code == T_WORD) |
8350 | { | |
8351 | if (current_templates->start->name[0] == 'l' | |
8352 | && current_templates->start->name[2] == 's' | |
8353 | && current_templates->start->name[3] == 0) | |
8354 | suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */ | |
8355 | else if (intel_parser.got_a_float == 2) /* "fi..." */ | |
8356 | suffix = SHORT_MNEM_SUFFIX; | |
8357 | else | |
8358 | suffix = WORD_MNEM_SUFFIX; | |
7d5e4556 | 8359 | i.types[this_operand].bitfield.word = 1; |
a724f0f4 | 8360 | } |
64a0c779 | 8361 | |
a724f0f4 JB |
8362 | else if (prev_token.code == T_DWORD) |
8363 | { | |
8364 | if (current_templates->start->name[0] == 'l' | |
8365 | && current_templates->start->name[2] == 's' | |
8366 | && current_templates->start->name[3] == 0) | |
8367 | suffix = WORD_MNEM_SUFFIX; | |
8368 | else if (flag_code == CODE_16BIT | |
40fb9820 L |
8369 | && (current_templates->start->opcode_modifier.jump |
8370 | || current_templates->start->opcode_modifier.jumpdword)) | |
a724f0f4 JB |
8371 | suffix = LONG_DOUBLE_MNEM_SUFFIX; |
8372 | else if (intel_parser.got_a_float == 1) /* "f..." */ | |
8373 | suffix = SHORT_MNEM_SUFFIX; | |
8374 | else | |
8375 | suffix = LONG_MNEM_SUFFIX; | |
7d5e4556 | 8376 | i.types[this_operand].bitfield.dword = 1; |
a724f0f4 | 8377 | } |
9306ca4a | 8378 | |
a724f0f4 JB |
8379 | else if (prev_token.code == T_FWORD) |
8380 | { | |
8381 | if (current_templates->start->name[0] == 'l' | |
8382 | && current_templates->start->name[2] == 's' | |
8383 | && current_templates->start->name[3] == 0) | |
8384 | suffix = LONG_MNEM_SUFFIX; | |
8385 | else if (!intel_parser.got_a_float) | |
8386 | { | |
8387 | if (flag_code == CODE_16BIT) | |
8388 | add_prefix (DATA_PREFIX_OPCODE); | |
8389 | suffix = LONG_DOUBLE_MNEM_SUFFIX; | |
8390 | } | |
8391 | else | |
8392 | suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */ | |
7d5e4556 | 8393 | i.types[this_operand].bitfield.fword = 1; |
a724f0f4 | 8394 | } |
64a0c779 | 8395 | |
a724f0f4 JB |
8396 | else if (prev_token.code == T_QWORD) |
8397 | { | |
8398 | if (intel_parser.got_a_float == 1) /* "f..." */ | |
8399 | suffix = LONG_MNEM_SUFFIX; | |
8400 | else | |
7d5e4556 L |
8401 | suffix = QWORD_MNEM_SUFFIX; |
8402 | i.types[this_operand].bitfield.qword = 1; | |
a724f0f4 | 8403 | } |
64a0c779 | 8404 | |
a724f0f4 JB |
8405 | else if (prev_token.code == T_TBYTE) |
8406 | { | |
8407 | if (intel_parser.got_a_float == 1) | |
8408 | suffix = LONG_DOUBLE_MNEM_SUFFIX; | |
8409 | else | |
8410 | suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */ | |
8411 | } | |
9306ca4a | 8412 | |
a724f0f4 | 8413 | else if (prev_token.code == T_XMMWORD) |
9306ca4a | 8414 | { |
582d5edd | 8415 | suffix = XMMWORD_MNEM_SUFFIX; |
7d5e4556 | 8416 | i.types[this_operand].bitfield.xmmword = 1; |
9306ca4a | 8417 | } |
64a0c779 | 8418 | |
f16b83df | 8419 | else |
a724f0f4 JB |
8420 | { |
8421 | as_bad (_("Unknown operand modifier `%s'"), prev_token.str); | |
8422 | return 0; | |
8423 | } | |
8424 | ||
7d5e4556 L |
8425 | i.types[this_operand].bitfield.unspecified = 0; |
8426 | ||
435acd52 JB |
8427 | /* Operands for jump/call using 'ptr' notation denote absolute |
8428 | addresses. */ | |
40fb9820 L |
8429 | if (current_templates->start->opcode_modifier.jump |
8430 | || current_templates->start->opcode_modifier.jumpdword) | |
8431 | i.types[this_operand].bitfield.jumpabsolute = 1; | |
435acd52 | 8432 | |
a724f0f4 JB |
8433 | if (current_templates->start->base_opcode == 0x8d /* lea */) |
8434 | ; | |
8435 | else if (!i.suffix) | |
8436 | i.suffix = suffix; | |
8437 | else if (i.suffix != suffix) | |
8438 | { | |
8439 | as_bad (_("Conflicting operand modifiers")); | |
8440 | return 0; | |
8441 | } | |
64a0c779 | 8442 | |
9306ca4a JB |
8443 | } |
8444 | ||
a724f0f4 JB |
8445 | /* e09' : e10 e09' */ |
8446 | else if (cur_token.code == ':') | |
9306ca4a | 8447 | { |
a724f0f4 JB |
8448 | if (prev_token.code != T_REG) |
8449 | { | |
8450 | /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a | |
8451 | segment/group identifier (which we don't have), using comma | |
8452 | as the operand separator there is even less consistent, since | |
8453 | there all branches only have a single operand. */ | |
8454 | if (this_operand != 0 | |
8455 | || intel_parser.in_offset | |
8456 | || intel_parser.in_bracket | |
40fb9820 L |
8457 | || (!current_templates->start->opcode_modifier.jump |
8458 | && !current_templates->start->opcode_modifier.jumpdword | |
8459 | && !current_templates->start->opcode_modifier.jumpintersegment | |
8460 | && !current_templates->start->operand_types[0].bitfield.jumpabsolute)) | |
a724f0f4 JB |
8461 | return intel_match_token (T_NIL); |
8462 | /* Remember the start of the 2nd operand and terminate 1st | |
8463 | operand here. | |
8464 | XXX This isn't right, yet (when SSSS:OOOO is right operand of | |
8465 | another expression), but it gets at least the simplest case | |
8466 | (a plain number or symbol on the left side) right. */ | |
8467 | intel_parser.next_operand = intel_parser.op_string; | |
8468 | *--intel_parser.op_string = '\0'; | |
8469 | return intel_match_token (':'); | |
8470 | } | |
9306ca4a | 8471 | } |
64a0c779 | 8472 | |
a724f0f4 | 8473 | /* e09' Empty */ |
64a0c779 | 8474 | else |
a724f0f4 | 8475 | break; |
64a0c779 | 8476 | |
a724f0f4 JB |
8477 | intel_match_token (cur_token.code); |
8478 | ||
8479 | } | |
8480 | ||
8481 | if (in_offset) | |
8482 | { | |
8483 | --intel_parser.in_offset; | |
8484 | if (nregs < 0) | |
8485 | nregs = ~nregs; | |
8486 | if (NUM_ADDRESS_REGS > nregs) | |
9306ca4a | 8487 | { |
a724f0f4 | 8488 | as_bad (_("Invalid operand to `OFFSET'")); |
9306ca4a JB |
8489 | return 0; |
8490 | } | |
a724f0f4 JB |
8491 | intel_parser.op_modifier |= 1 << T_OFFSET; |
8492 | } | |
9306ca4a | 8493 | |
a724f0f4 JB |
8494 | if (nregs >= 0 && NUM_ADDRESS_REGS > nregs) |
8495 | i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */ | |
8496 | return 1; | |
8497 | } | |
64a0c779 | 8498 | |
a724f0f4 | 8499 | static int |
e3bb37b5 | 8500 | intel_bracket_expr (void) |
a724f0f4 JB |
8501 | { |
8502 | int was_offset = intel_parser.op_modifier & (1 << T_OFFSET); | |
8503 | const char *start = intel_parser.op_string; | |
8504 | int len; | |
8505 | ||
8506 | if (i.op[this_operand].regs) | |
8507 | return intel_match_token (T_NIL); | |
8508 | ||
8509 | intel_match_token ('['); | |
8510 | ||
8511 | /* Mark as a memory operand only if it's not already known to be an | |
8512 | offset expression. If it's an offset expression, we need to keep | |
8513 | the brace in. */ | |
8514 | if (!intel_parser.in_offset) | |
8515 | { | |
8516 | ++intel_parser.in_bracket; | |
435acd52 JB |
8517 | |
8518 | /* Operands for jump/call inside brackets denote absolute addresses. */ | |
40fb9820 L |
8519 | if (current_templates->start->opcode_modifier.jump |
8520 | || current_templates->start->opcode_modifier.jumpdword) | |
8521 | i.types[this_operand].bitfield.jumpabsolute = 1; | |
435acd52 | 8522 | |
a724f0f4 JB |
8523 | /* Unfortunately gas always diverged from MASM in a respect that can't |
8524 | be easily fixed without risking to break code sequences likely to be | |
8525 | encountered (the testsuite even check for this): MASM doesn't consider | |
8526 | an expression inside brackets unconditionally as a memory reference. | |
8527 | When that is e.g. a constant, an offset expression, or the sum of the | |
8528 | two, this is still taken as a constant load. gas, however, always | |
8529 | treated these as memory references. As a compromise, we'll try to make | |
8530 | offset expressions inside brackets work the MASM way (since that's | |
8531 | less likely to be found in real world code), but make constants alone | |
8532 | continue to work the traditional gas way. In either case, issue a | |
8533 | warning. */ | |
8534 | intel_parser.op_modifier &= ~was_offset; | |
64a0c779 | 8535 | } |
a724f0f4 | 8536 | else |
64e74474 | 8537 | strcat (intel_parser.disp, "["); |
a724f0f4 JB |
8538 | |
8539 | /* Add a '+' to the displacement string if necessary. */ | |
8540 | if (*intel_parser.disp != '\0' | |
8541 | && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+') | |
8542 | strcat (intel_parser.disp, "+"); | |
64a0c779 | 8543 | |
a724f0f4 JB |
8544 | if (intel_expr () |
8545 | && (len = intel_parser.op_string - start - 1, | |
8546 | intel_match_token (']'))) | |
64a0c779 | 8547 | { |
a724f0f4 JB |
8548 | /* Preserve brackets when the operand is an offset expression. */ |
8549 | if (intel_parser.in_offset) | |
8550 | strcat (intel_parser.disp, "]"); | |
8551 | else | |
8552 | { | |
8553 | --intel_parser.in_bracket; | |
8554 | if (i.base_reg || i.index_reg) | |
8555 | intel_parser.is_mem = 1; | |
8556 | if (!intel_parser.is_mem) | |
8557 | { | |
8558 | if (!(intel_parser.op_modifier & (1 << T_OFFSET))) | |
8559 | /* Defer the warning until all of the operand was parsed. */ | |
8560 | intel_parser.is_mem = -1; | |
8561 | else if (!quiet_warnings) | |
4eed87de AM |
8562 | as_warn (_("`[%.*s]' taken to mean just `%.*s'"), |
8563 | len, start, len, start); | |
a724f0f4 JB |
8564 | } |
8565 | } | |
8566 | intel_parser.op_modifier |= was_offset; | |
64a0c779 | 8567 | |
a724f0f4 | 8568 | return 1; |
64a0c779 | 8569 | } |
a724f0f4 | 8570 | return 0; |
64a0c779 DN |
8571 | } |
8572 | ||
8573 | /* e10 e11 e10' | |
8574 | ||
8575 | e10' [ expr ] e10' | |
b77a7acd | 8576 | | Empty */ |
64a0c779 | 8577 | static int |
e3bb37b5 | 8578 | intel_e10 (void) |
64a0c779 | 8579 | { |
a724f0f4 JB |
8580 | if (!intel_e11 ()) |
8581 | return 0; | |
64a0c779 | 8582 | |
a724f0f4 | 8583 | while (cur_token.code == '[') |
64a0c779 | 8584 | { |
a724f0f4 | 8585 | if (!intel_bracket_expr ()) |
21d6c4af | 8586 | return 0; |
64a0c779 DN |
8587 | } |
8588 | ||
a724f0f4 | 8589 | return 1; |
64a0c779 DN |
8590 | } |
8591 | ||
64a0c779 | 8592 | /* e11 ( expr ) |
b77a7acd | 8593 | | [ expr ] |
64a0c779 DN |
8594 | | BYTE |
8595 | | WORD | |
8596 | | DWORD | |
9306ca4a | 8597 | | FWORD |
64a0c779 | 8598 | | QWORD |
9306ca4a JB |
8599 | | TBYTE |
8600 | | OWORD | |
8601 | | XMMWORD | |
4a1805b1 | 8602 | | $ |
64a0c779 DN |
8603 | | . |
8604 | | register | |
8605 | | id | |
8606 | | constant */ | |
8607 | static int | |
e3bb37b5 | 8608 | intel_e11 (void) |
64a0c779 | 8609 | { |
a724f0f4 | 8610 | switch (cur_token.code) |
64a0c779 | 8611 | { |
a724f0f4 JB |
8612 | /* e11 ( expr ) */ |
8613 | case '(': | |
64a0c779 DN |
8614 | intel_match_token ('('); |
8615 | strcat (intel_parser.disp, "("); | |
8616 | ||
8617 | if (intel_expr () && intel_match_token (')')) | |
e5cb08ac KH |
8618 | { |
8619 | strcat (intel_parser.disp, ")"); | |
8620 | return 1; | |
8621 | } | |
a724f0f4 | 8622 | return 0; |
4a1805b1 | 8623 | |
a724f0f4 JB |
8624 | /* e11 [ expr ] */ |
8625 | case '[': | |
a724f0f4 | 8626 | return intel_bracket_expr (); |
64a0c779 | 8627 | |
a724f0f4 JB |
8628 | /* e11 $ |
8629 | | . */ | |
8630 | case '.': | |
64a0c779 DN |
8631 | strcat (intel_parser.disp, cur_token.str); |
8632 | intel_match_token (cur_token.code); | |
21d6c4af DN |
8633 | |
8634 | /* Mark as a memory operand only if it's not already known to be an | |
8635 | offset expression. */ | |
a724f0f4 | 8636 | if (!intel_parser.in_offset) |
21d6c4af | 8637 | intel_parser.is_mem = 1; |
64a0c779 DN |
8638 | |
8639 | return 1; | |
64a0c779 | 8640 | |
a724f0f4 JB |
8641 | /* e11 register */ |
8642 | case T_REG: | |
8643 | { | |
8644 | const reg_entry *reg = intel_parser.reg = cur_token.reg; | |
64a0c779 | 8645 | |
a724f0f4 | 8646 | intel_match_token (T_REG); |
64a0c779 | 8647 | |
a724f0f4 JB |
8648 | /* Check for segment change. */ |
8649 | if (cur_token.code == ':') | |
8650 | { | |
40fb9820 L |
8651 | if (!reg->reg_type.bitfield.sreg2 |
8652 | && !reg->reg_type.bitfield.sreg3) | |
a724f0f4 | 8653 | { |
4eed87de AM |
8654 | as_bad (_("`%s' is not a valid segment register"), |
8655 | reg->reg_name); | |
a724f0f4 JB |
8656 | return 0; |
8657 | } | |
8658 | else if (i.seg[i.mem_operands]) | |
8659 | as_warn (_("Extra segment override ignored")); | |
8660 | else | |
8661 | { | |
8662 | if (!intel_parser.in_offset) | |
8663 | intel_parser.is_mem = 1; | |
8664 | switch (reg->reg_num) | |
8665 | { | |
8666 | case 0: | |
8667 | i.seg[i.mem_operands] = &es; | |
8668 | break; | |
8669 | case 1: | |
8670 | i.seg[i.mem_operands] = &cs; | |
8671 | break; | |
8672 | case 2: | |
8673 | i.seg[i.mem_operands] = &ss; | |
8674 | break; | |
8675 | case 3: | |
8676 | i.seg[i.mem_operands] = &ds; | |
8677 | break; | |
8678 | case 4: | |
8679 | i.seg[i.mem_operands] = &fs; | |
8680 | break; | |
8681 | case 5: | |
8682 | i.seg[i.mem_operands] = &gs; | |
8683 | break; | |
8684 | } | |
8685 | } | |
8686 | } | |
64a0c779 | 8687 | |
a724f0f4 JB |
8688 | /* Not a segment register. Check for register scaling. */ |
8689 | else if (cur_token.code == '*') | |
8690 | { | |
8691 | if (!intel_parser.in_bracket) | |
8692 | { | |
8693 | as_bad (_("Register scaling only allowed in memory operands")); | |
8694 | return 0; | |
8695 | } | |
64a0c779 | 8696 | |
40fb9820 | 8697 | if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */ |
a724f0f4 JB |
8698 | reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */ |
8699 | else if (i.index_reg) | |
8700 | reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */ | |
64a0c779 | 8701 | |
a724f0f4 JB |
8702 | /* What follows must be a valid scale. */ |
8703 | intel_match_token ('*'); | |
8704 | i.index_reg = reg; | |
40fb9820 | 8705 | i.types[this_operand].bitfield.baseindex = 1; |
64a0c779 | 8706 | |
a724f0f4 JB |
8707 | /* Set the scale after setting the register (otherwise, |
8708 | i386_scale will complain) */ | |
8709 | if (cur_token.code == '+' || cur_token.code == '-') | |
8710 | { | |
8711 | char *str, sign = cur_token.code; | |
8712 | intel_match_token (cur_token.code); | |
8713 | if (cur_token.code != T_CONST) | |
8714 | { | |
8715 | as_bad (_("Syntax error: Expecting a constant, got `%s'"), | |
8716 | cur_token.str); | |
8717 | return 0; | |
8718 | } | |
8719 | str = (char *) xmalloc (strlen (cur_token.str) + 2); | |
8720 | strcpy (str + 1, cur_token.str); | |
8721 | *str = sign; | |
8722 | if (!i386_scale (str)) | |
8723 | return 0; | |
8724 | free (str); | |
8725 | } | |
8726 | else if (!i386_scale (cur_token.str)) | |
64a0c779 | 8727 | return 0; |
a724f0f4 JB |
8728 | intel_match_token (cur_token.code); |
8729 | } | |
64a0c779 | 8730 | |
a724f0f4 JB |
8731 | /* No scaling. If this is a memory operand, the register is either a |
8732 | base register (first occurrence) or an index register (second | |
8733 | occurrence). */ | |
7b0441f6 | 8734 | else if (intel_parser.in_bracket) |
a724f0f4 | 8735 | { |
64a0c779 | 8736 | |
a724f0f4 JB |
8737 | if (!i.base_reg) |
8738 | i.base_reg = reg; | |
8739 | else if (!i.index_reg) | |
8740 | i.index_reg = reg; | |
8741 | else | |
8742 | { | |
8743 | as_bad (_("Too many register references in memory operand")); | |
8744 | return 0; | |
8745 | } | |
64a0c779 | 8746 | |
40fb9820 | 8747 | i.types[this_operand].bitfield.baseindex = 1; |
a724f0f4 | 8748 | } |
4a1805b1 | 8749 | |
4d1bb795 JB |
8750 | /* It's neither base nor index. */ |
8751 | else if (!intel_parser.in_offset && !intel_parser.is_mem) | |
a724f0f4 | 8752 | { |
40fb9820 L |
8753 | i386_operand_type temp = reg->reg_type; |
8754 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
8755 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
8756 | temp); | |
7d5e4556 | 8757 | i.types[this_operand].bitfield.unspecified = 0; |
a724f0f4 JB |
8758 | i.op[this_operand].regs = reg; |
8759 | i.reg_operands++; | |
8760 | } | |
8761 | else | |
8762 | { | |
8763 | as_bad (_("Invalid use of register")); | |
8764 | return 0; | |
8765 | } | |
64a0c779 | 8766 | |
a724f0f4 JB |
8767 | /* Since registers are not part of the displacement string (except |
8768 | when we're parsing offset operands), we may need to remove any | |
8769 | preceding '+' from the displacement string. */ | |
8770 | if (*intel_parser.disp != '\0' | |
8771 | && !intel_parser.in_offset) | |
8772 | { | |
8773 | char *s = intel_parser.disp; | |
8774 | s += strlen (s) - 1; | |
8775 | if (*s == '+') | |
8776 | *s = '\0'; | |
8777 | } | |
4a1805b1 | 8778 | |
a724f0f4 JB |
8779 | return 1; |
8780 | } | |
8781 | ||
8782 | /* e11 BYTE | |
8783 | | WORD | |
8784 | | DWORD | |
8785 | | FWORD | |
8786 | | QWORD | |
8787 | | TBYTE | |
8788 | | OWORD | |
8789 | | XMMWORD */ | |
8790 | case T_BYTE: | |
8791 | case T_WORD: | |
8792 | case T_DWORD: | |
8793 | case T_FWORD: | |
8794 | case T_QWORD: | |
8795 | case T_TBYTE: | |
8796 | case T_XMMWORD: | |
8797 | intel_match_token (cur_token.code); | |
64a0c779 | 8798 | |
a724f0f4 JB |
8799 | if (cur_token.code == T_PTR) |
8800 | return 1; | |
8801 | ||
8802 | /* It must have been an identifier. */ | |
8803 | intel_putback_token (); | |
8804 | cur_token.code = T_ID; | |
8805 | /* FALLTHRU */ | |
8806 | ||
8807 | /* e11 id | |
8808 | | constant */ | |
8809 | case T_ID: | |
8810 | if (!intel_parser.in_offset && intel_parser.is_mem <= 0) | |
9306ca4a JB |
8811 | { |
8812 | symbolS *symbolP; | |
8813 | ||
a724f0f4 JB |
8814 | /* The identifier represents a memory reference only if it's not |
8815 | preceded by an offset modifier and if it's not an equate. */ | |
9306ca4a JB |
8816 | symbolP = symbol_find(cur_token.str); |
8817 | if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section) | |
8818 | intel_parser.is_mem = 1; | |
8819 | } | |
a724f0f4 | 8820 | /* FALLTHRU */ |
64a0c779 | 8821 | |
a724f0f4 JB |
8822 | case T_CONST: |
8823 | case '-': | |
8824 | case '+': | |
8825 | { | |
8826 | char *save_str, sign = 0; | |
64a0c779 | 8827 | |
a724f0f4 JB |
8828 | /* Allow constants that start with `+' or `-'. */ |
8829 | if (cur_token.code == '-' || cur_token.code == '+') | |
8830 | { | |
8831 | sign = cur_token.code; | |
8832 | intel_match_token (cur_token.code); | |
8833 | if (cur_token.code != T_CONST) | |
8834 | { | |
8835 | as_bad (_("Syntax error: Expecting a constant, got `%s'"), | |
8836 | cur_token.str); | |
8837 | return 0; | |
8838 | } | |
8839 | } | |
64a0c779 | 8840 | |
a724f0f4 JB |
8841 | save_str = (char *) xmalloc (strlen (cur_token.str) + 2); |
8842 | strcpy (save_str + !!sign, cur_token.str); | |
8843 | if (sign) | |
8844 | *save_str = sign; | |
64a0c779 | 8845 | |
a724f0f4 JB |
8846 | /* Get the next token to check for register scaling. */ |
8847 | intel_match_token (cur_token.code); | |
64a0c779 | 8848 | |
4eed87de AM |
8849 | /* Check if this constant is a scaling factor for an |
8850 | index register. */ | |
a724f0f4 JB |
8851 | if (cur_token.code == '*') |
8852 | { | |
8853 | if (intel_match_token ('*') && cur_token.code == T_REG) | |
8854 | { | |
8855 | const reg_entry *reg = cur_token.reg; | |
8856 | ||
8857 | if (!intel_parser.in_bracket) | |
8858 | { | |
4eed87de AM |
8859 | as_bad (_("Register scaling only allowed " |
8860 | "in memory operands")); | |
a724f0f4 JB |
8861 | return 0; |
8862 | } | |
8863 | ||
4eed87de AM |
8864 | /* Disallow things like [1*si]. |
8865 | sp and esp are invalid as index. */ | |
40fb9820 | 8866 | if (reg->reg_type.bitfield.reg16) |
4eed87de | 8867 | reg = i386_regtab + REGNAM_AX + 4; |
a724f0f4 | 8868 | else if (i.index_reg) |
4eed87de | 8869 | reg = i386_regtab + REGNAM_EAX + 4; |
a724f0f4 JB |
8870 | |
8871 | /* The constant is followed by `* reg', so it must be | |
8872 | a valid scale. */ | |
8873 | i.index_reg = reg; | |
40fb9820 | 8874 | i.types[this_operand].bitfield.baseindex = 1; |
a724f0f4 JB |
8875 | |
8876 | /* Set the scale after setting the register (otherwise, | |
8877 | i386_scale will complain) */ | |
8878 | if (!i386_scale (save_str)) | |
64a0c779 | 8879 | return 0; |
a724f0f4 JB |
8880 | intel_match_token (T_REG); |
8881 | ||
8882 | /* Since registers are not part of the displacement | |
8883 | string, we may need to remove any preceding '+' from | |
8884 | the displacement string. */ | |
8885 | if (*intel_parser.disp != '\0') | |
8886 | { | |
8887 | char *s = intel_parser.disp; | |
8888 | s += strlen (s) - 1; | |
8889 | if (*s == '+') | |
8890 | *s = '\0'; | |
8891 | } | |
8892 | ||
8893 | free (save_str); | |
8894 | ||
8895 | return 1; | |
8896 | } | |
64a0c779 | 8897 | |
a724f0f4 JB |
8898 | /* The constant was not used for register scaling. Since we have |
8899 | already consumed the token following `*' we now need to put it | |
8900 | back in the stream. */ | |
64a0c779 | 8901 | intel_putback_token (); |
a724f0f4 | 8902 | } |
64a0c779 | 8903 | |
a724f0f4 JB |
8904 | /* Add the constant to the displacement string. */ |
8905 | strcat (intel_parser.disp, save_str); | |
8906 | free (save_str); | |
64a0c779 | 8907 | |
a724f0f4 JB |
8908 | return 1; |
8909 | } | |
64a0c779 DN |
8910 | } |
8911 | ||
64a0c779 DN |
8912 | as_bad (_("Unrecognized token '%s'"), cur_token.str); |
8913 | return 0; | |
8914 | } | |
8915 | ||
64a0c779 DN |
8916 | /* Match the given token against cur_token. If they match, read the next |
8917 | token from the operand string. */ | |
8918 | static int | |
e3bb37b5 | 8919 | intel_match_token (int code) |
64a0c779 DN |
8920 | { |
8921 | if (cur_token.code == code) | |
8922 | { | |
8923 | intel_get_token (); | |
8924 | return 1; | |
8925 | } | |
8926 | else | |
8927 | { | |
0477af35 | 8928 | as_bad (_("Unexpected token `%s'"), cur_token.str); |
64a0c779 DN |
8929 | return 0; |
8930 | } | |
8931 | } | |
8932 | ||
64a0c779 DN |
8933 | /* Read a new token from intel_parser.op_string and store it in cur_token. */ |
8934 | static void | |
e3bb37b5 | 8935 | intel_get_token (void) |
64a0c779 DN |
8936 | { |
8937 | char *end_op; | |
8938 | const reg_entry *reg; | |
8939 | struct intel_token new_token; | |
8940 | ||
8941 | new_token.code = T_NIL; | |
8942 | new_token.reg = NULL; | |
8943 | new_token.str = NULL; | |
8944 | ||
4a1805b1 | 8945 | /* Free the memory allocated to the previous token and move |
64a0c779 DN |
8946 | cur_token to prev_token. */ |
8947 | if (prev_token.str) | |
8948 | free (prev_token.str); | |
8949 | ||
8950 | prev_token = cur_token; | |
8951 | ||
8952 | /* Skip whitespace. */ | |
8953 | while (is_space_char (*intel_parser.op_string)) | |
8954 | intel_parser.op_string++; | |
8955 | ||
8956 | /* Return an empty token if we find nothing else on the line. */ | |
8957 | if (*intel_parser.op_string == '\0') | |
8958 | { | |
8959 | cur_token = new_token; | |
8960 | return; | |
8961 | } | |
8962 | ||
8963 | /* The new token cannot be larger than the remainder of the operand | |
8964 | string. */ | |
a724f0f4 | 8965 | new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1); |
64a0c779 DN |
8966 | new_token.str[0] = '\0'; |
8967 | ||
8968 | if (strchr ("0123456789", *intel_parser.op_string)) | |
8969 | { | |
8970 | char *p = new_token.str; | |
8971 | char *q = intel_parser.op_string; | |
8972 | new_token.code = T_CONST; | |
8973 | ||
8974 | /* Allow any kind of identifier char to encompass floating point and | |
8975 | hexadecimal numbers. */ | |
8976 | while (is_identifier_char (*q)) | |
8977 | *p++ = *q++; | |
8978 | *p = '\0'; | |
8979 | ||
8980 | /* Recognize special symbol names [0-9][bf]. */ | |
8981 | if (strlen (intel_parser.op_string) == 2 | |
4a1805b1 | 8982 | && (intel_parser.op_string[1] == 'b' |
64a0c779 DN |
8983 | || intel_parser.op_string[1] == 'f')) |
8984 | new_token.code = T_ID; | |
8985 | } | |
8986 | ||
4d1bb795 | 8987 | else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL) |
64a0c779 | 8988 | { |
4d1bb795 JB |
8989 | size_t len = end_op - intel_parser.op_string; |
8990 | ||
64a0c779 DN |
8991 | new_token.code = T_REG; |
8992 | new_token.reg = reg; | |
8993 | ||
4d1bb795 JB |
8994 | memcpy (new_token.str, intel_parser.op_string, len); |
8995 | new_token.str[len] = '\0'; | |
64a0c779 DN |
8996 | } |
8997 | ||
8998 | else if (is_identifier_char (*intel_parser.op_string)) | |
8999 | { | |
9000 | char *p = new_token.str; | |
9001 | char *q = intel_parser.op_string; | |
9002 | ||
9003 | /* A '.' or '$' followed by an identifier char is an identifier. | |
9004 | Otherwise, it's operator '.' followed by an expression. */ | |
9005 | if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1))) | |
9006 | { | |
9306ca4a JB |
9007 | new_token.code = '.'; |
9008 | new_token.str[0] = '.'; | |
64a0c779 DN |
9009 | new_token.str[1] = '\0'; |
9010 | } | |
9011 | else | |
9012 | { | |
9013 | while (is_identifier_char (*q) || *q == '@') | |
9014 | *p++ = *q++; | |
9015 | *p = '\0'; | |
9016 | ||
9306ca4a JB |
9017 | if (strcasecmp (new_token.str, "NOT") == 0) |
9018 | new_token.code = '~'; | |
9019 | ||
9020 | else if (strcasecmp (new_token.str, "MOD") == 0) | |
9021 | new_token.code = '%'; | |
9022 | ||
9023 | else if (strcasecmp (new_token.str, "AND") == 0) | |
9024 | new_token.code = '&'; | |
9025 | ||
9026 | else if (strcasecmp (new_token.str, "OR") == 0) | |
9027 | new_token.code = '|'; | |
9028 | ||
9029 | else if (strcasecmp (new_token.str, "XOR") == 0) | |
9030 | new_token.code = '^'; | |
9031 | ||
9032 | else if (strcasecmp (new_token.str, "SHL") == 0) | |
9033 | new_token.code = T_SHL; | |
9034 | ||
9035 | else if (strcasecmp (new_token.str, "SHR") == 0) | |
9036 | new_token.code = T_SHR; | |
9037 | ||
9038 | else if (strcasecmp (new_token.str, "BYTE") == 0) | |
64a0c779 DN |
9039 | new_token.code = T_BYTE; |
9040 | ||
9041 | else if (strcasecmp (new_token.str, "WORD") == 0) | |
9042 | new_token.code = T_WORD; | |
9043 | ||
9044 | else if (strcasecmp (new_token.str, "DWORD") == 0) | |
9045 | new_token.code = T_DWORD; | |
9046 | ||
9306ca4a JB |
9047 | else if (strcasecmp (new_token.str, "FWORD") == 0) |
9048 | new_token.code = T_FWORD; | |
9049 | ||
64a0c779 DN |
9050 | else if (strcasecmp (new_token.str, "QWORD") == 0) |
9051 | new_token.code = T_QWORD; | |
9052 | ||
9306ca4a JB |
9053 | else if (strcasecmp (new_token.str, "TBYTE") == 0 |
9054 | /* XXX remove (gcc still uses it) */ | |
9055 | || strcasecmp (new_token.str, "XWORD") == 0) | |
9056 | new_token.code = T_TBYTE; | |
9057 | ||
9058 | else if (strcasecmp (new_token.str, "XMMWORD") == 0 | |
9059 | || strcasecmp (new_token.str, "OWORD") == 0) | |
9060 | new_token.code = T_XMMWORD; | |
64a0c779 DN |
9061 | |
9062 | else if (strcasecmp (new_token.str, "PTR") == 0) | |
9063 | new_token.code = T_PTR; | |
9064 | ||
9065 | else if (strcasecmp (new_token.str, "SHORT") == 0) | |
9066 | new_token.code = T_SHORT; | |
9067 | ||
9068 | else if (strcasecmp (new_token.str, "OFFSET") == 0) | |
9069 | { | |
9070 | new_token.code = T_OFFSET; | |
9071 | ||
9072 | /* ??? This is not mentioned in the MASM grammar but gcc | |
9073 | makes use of it with -mintel-syntax. OFFSET may be | |
9074 | followed by FLAT: */ | |
9075 | if (strncasecmp (q, " FLAT:", 6) == 0) | |
9076 | strcat (new_token.str, " FLAT:"); | |
9077 | } | |
9078 | ||
9079 | /* ??? This is not mentioned in the MASM grammar. */ | |
9080 | else if (strcasecmp (new_token.str, "FLAT") == 0) | |
a724f0f4 JB |
9081 | { |
9082 | new_token.code = T_OFFSET; | |
9083 | if (*q == ':') | |
9084 | strcat (new_token.str, ":"); | |
9085 | else | |
9086 | as_bad (_("`:' expected")); | |
9087 | } | |
64a0c779 DN |
9088 | |
9089 | else | |
9090 | new_token.code = T_ID; | |
9091 | } | |
9092 | } | |
9093 | ||
9306ca4a JB |
9094 | else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string)) |
9095 | { | |
9096 | new_token.code = *intel_parser.op_string; | |
9097 | new_token.str[0] = *intel_parser.op_string; | |
9098 | new_token.str[1] = '\0'; | |
9099 | } | |
9100 | ||
9101 | else if (strchr ("<>", *intel_parser.op_string) | |
9102 | && *intel_parser.op_string == *(intel_parser.op_string + 1)) | |
9103 | { | |
9104 | new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR; | |
9105 | new_token.str[0] = *intel_parser.op_string; | |
9106 | new_token.str[1] = *intel_parser.op_string; | |
9107 | new_token.str[2] = '\0'; | |
9108 | } | |
9109 | ||
64a0c779 | 9110 | else |
0477af35 | 9111 | as_bad (_("Unrecognized token `%s'"), intel_parser.op_string); |
64a0c779 DN |
9112 | |
9113 | intel_parser.op_string += strlen (new_token.str); | |
9114 | cur_token = new_token; | |
9115 | } | |
9116 | ||
64a0c779 DN |
9117 | /* Put cur_token back into the token stream and make cur_token point to |
9118 | prev_token. */ | |
9119 | static void | |
e3bb37b5 | 9120 | intel_putback_token (void) |
64a0c779 | 9121 | { |
a724f0f4 JB |
9122 | if (cur_token.code != T_NIL) |
9123 | { | |
9124 | intel_parser.op_string -= strlen (cur_token.str); | |
9125 | free (cur_token.str); | |
9126 | } | |
64a0c779 | 9127 | cur_token = prev_token; |
4a1805b1 | 9128 | |
64a0c779 DN |
9129 | /* Forget prev_token. */ |
9130 | prev_token.code = T_NIL; | |
9131 | prev_token.reg = NULL; | |
9132 | prev_token.str = NULL; | |
9133 | } | |
54cfded0 | 9134 | |
a4447b93 | 9135 | int |
1df69f4f | 9136 | tc_x86_regname_to_dw2regnum (char *regname) |
54cfded0 AM |
9137 | { |
9138 | unsigned int regnum; | |
9139 | unsigned int regnames_count; | |
089dfecd | 9140 | static const char *const regnames_32[] = |
54cfded0 | 9141 | { |
a4447b93 RH |
9142 | "eax", "ecx", "edx", "ebx", |
9143 | "esp", "ebp", "esi", "edi", | |
089dfecd JB |
9144 | "eip", "eflags", NULL, |
9145 | "st0", "st1", "st2", "st3", | |
9146 | "st4", "st5", "st6", "st7", | |
9147 | NULL, NULL, | |
9148 | "xmm0", "xmm1", "xmm2", "xmm3", | |
9149 | "xmm4", "xmm5", "xmm6", "xmm7", | |
9150 | "mm0", "mm1", "mm2", "mm3", | |
43fd16e4 JB |
9151 | "mm4", "mm5", "mm6", "mm7", |
9152 | "fcw", "fsw", "mxcsr", | |
9153 | "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL, | |
9154 | "tr", "ldtr" | |
54cfded0 | 9155 | }; |
089dfecd | 9156 | static const char *const regnames_64[] = |
54cfded0 | 9157 | { |
089dfecd JB |
9158 | "rax", "rdx", "rcx", "rbx", |
9159 | "rsi", "rdi", "rbp", "rsp", | |
9160 | "r8", "r9", "r10", "r11", | |
54cfded0 | 9161 | "r12", "r13", "r14", "r15", |
089dfecd JB |
9162 | "rip", |
9163 | "xmm0", "xmm1", "xmm2", "xmm3", | |
9164 | "xmm4", "xmm5", "xmm6", "xmm7", | |
9165 | "xmm8", "xmm9", "xmm10", "xmm11", | |
9166 | "xmm12", "xmm13", "xmm14", "xmm15", | |
9167 | "st0", "st1", "st2", "st3", | |
9168 | "st4", "st5", "st6", "st7", | |
9169 | "mm0", "mm1", "mm2", "mm3", | |
43fd16e4 JB |
9170 | "mm4", "mm5", "mm6", "mm7", |
9171 | "rflags", | |
9172 | "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL, | |
9173 | "fs.base", "gs.base", NULL, NULL, | |
9174 | "tr", "ldtr", | |
9175 | "mxcsr", "fcw", "fsw" | |
54cfded0 | 9176 | }; |
089dfecd | 9177 | const char *const *regnames; |
54cfded0 AM |
9178 | |
9179 | if (flag_code == CODE_64BIT) | |
9180 | { | |
9181 | regnames = regnames_64; | |
0cea6190 | 9182 | regnames_count = ARRAY_SIZE (regnames_64); |
54cfded0 AM |
9183 | } |
9184 | else | |
9185 | { | |
9186 | regnames = regnames_32; | |
0cea6190 | 9187 | regnames_count = ARRAY_SIZE (regnames_32); |
54cfded0 AM |
9188 | } |
9189 | ||
9190 | for (regnum = 0; regnum < regnames_count; regnum++) | |
089dfecd JB |
9191 | if (regnames[regnum] != NULL |
9192 | && strcmp (regname, regnames[regnum]) == 0) | |
54cfded0 AM |
9193 | return regnum; |
9194 | ||
54cfded0 AM |
9195 | return -1; |
9196 | } | |
9197 | ||
9198 | void | |
9199 | tc_x86_frame_initial_instructions (void) | |
9200 | { | |
a4447b93 RH |
9201 | static unsigned int sp_regno; |
9202 | ||
9203 | if (!sp_regno) | |
9204 | sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT | |
9205 | ? "rsp" : "esp"); | |
9206 | ||
9207 | cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment); | |
9208 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 9209 | } |
d2b2c203 DJ |
9210 | |
9211 | int | |
9212 | i386_elf_section_type (const char *str, size_t len) | |
9213 | { | |
9214 | if (flag_code == CODE_64BIT | |
9215 | && len == sizeof ("unwind") - 1 | |
9216 | && strncmp (str, "unwind", 6) == 0) | |
9217 | return SHT_X86_64_UNWIND; | |
9218 | ||
9219 | return -1; | |
9220 | } | |
bb41ade5 AM |
9221 | |
9222 | #ifdef TE_PE | |
9223 | void | |
9224 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
9225 | { | |
9226 | expressionS expr; | |
9227 | ||
9228 | expr.X_op = O_secrel; | |
9229 | expr.X_add_symbol = symbol; | |
9230 | expr.X_add_number = 0; | |
9231 | emit_expr (&expr, size); | |
9232 | } | |
9233 | #endif | |
3b22753a L |
9234 | |
9235 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
9236 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
9237 | ||
9238 | int | |
9239 | x86_64_section_letter (int letter, char **ptr_msg) | |
9240 | { | |
9241 | if (flag_code == CODE_64BIT) | |
9242 | { | |
9243 | if (letter == 'l') | |
9244 | return SHF_X86_64_LARGE; | |
9245 | ||
9246 | *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string"); | |
64e74474 | 9247 | } |
3b22753a | 9248 | else |
64e74474 | 9249 | *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
9250 | return -1; |
9251 | } | |
9252 | ||
9253 | int | |
9254 | x86_64_section_word (char *str, size_t len) | |
9255 | { | |
8620418b | 9256 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
3b22753a L |
9257 | return SHF_X86_64_LARGE; |
9258 | ||
9259 | return -1; | |
9260 | } | |
9261 | ||
9262 | static void | |
9263 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
9264 | { | |
9265 | if (flag_code != CODE_64BIT) | |
9266 | { | |
9267 | s_comm_internal (0, elf_common_parse); | |
9268 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
9269 | } | |
9270 | else | |
9271 | { | |
9272 | static segT lbss_section; | |
9273 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
9274 | asection *saved_bss_section = bss_section; | |
9275 | ||
9276 | if (lbss_section == NULL) | |
9277 | { | |
9278 | flagword applicable; | |
9279 | segT seg = now_seg; | |
9280 | subsegT subseg = now_subseg; | |
9281 | ||
9282 | /* The .lbss section is for local .largecomm symbols. */ | |
9283 | lbss_section = subseg_new (".lbss", 0); | |
9284 | applicable = bfd_applicable_section_flags (stdoutput); | |
9285 | bfd_set_section_flags (stdoutput, lbss_section, | |
9286 | applicable & SEC_ALLOC); | |
9287 | seg_info (lbss_section)->bss = 1; | |
9288 | ||
9289 | subseg_set (seg, subseg); | |
9290 | } | |
9291 | ||
9292 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
9293 | bss_section = lbss_section; | |
9294 | ||
9295 | s_comm_internal (0, elf_common_parse); | |
9296 | ||
9297 | elf_com_section_ptr = saved_com_section_ptr; | |
9298 | bss_section = saved_bss_section; | |
9299 | } | |
9300 | } | |
9301 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |