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[ARC] Add SYNTAX_NOP and SYNTAX_1OP for extension instructions
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
6f2750fe 2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d
L		 68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
22109423 136 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 137}
138arch_entry;
139
78f12dd3 140static void update_code_flag (int, int);
e3bb37b5
L		 141static void set_code_flag (int);
142static void set_16bit_gcc_code_flag (int);
143static void set_intel_syntax (int);
1efbbeb4 144static void set_intel_mnemonic (int);
db51cc60 145static void set_allow_index_reg (int);
7bab8ab5 146static void set_check (int);
e3bb37b5 147static void set_cpu_arch (int);
6482c264 148#ifdef TE_PE
e3bb37b5 149static void pe_directive_secrel (int);
6482c264 150#endif
e3bb37b5
L		 151static void signed_cons (int);
152static char *output_invalid (int c);
ee86248c
JB		 153static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
154 const char *);
155static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
156 const char *);
a7619375 157static int i386_att_operand (char *);
e3bb37b5 158static int i386_intel_operand (char *, int);
ee86248c
JB		 159static int i386_intel_simplify (expressionS *);
160static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 161static const reg_entry *parse_register (char *, char **);
162static char *parse_insn (char *, char *);
163static char *parse_operands (char *, const char *);
164static void swap_operands (void);
4d456e3d 165static void swap_2_operands (int, int);
e3bb37b5
L		 166static void optimize_imm (void);
167static void optimize_disp (void);
d3ce72d0 168static const insn_template *match_template (void);
e3bb37b5
L		 169static int check_string (void);
170static int process_suffix (void);
171static int check_byte_reg (void);
172static int check_long_reg (void);
173static int check_qword_reg (void);
174static int check_word_reg (void);
175static int finalize_imm (void);
176static int process_operands (void);
177static const seg_entry *build_modrm_byte (void);
178static void output_insn (void);
179static void output_imm (fragS *, offsetT);
180static void output_disp (fragS *, offsetT);
29b0f896 181#ifndef I386COFF
e3bb37b5 182static void s_bss (int);
252b5132 183#endif
17d4e2a2
L		 184#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185static void handle_large_common (int small ATTRIBUTE_UNUSED);
186#endif
252b5132 187
a847613f 188static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 189
43234a1e
L		 190/* This struct describes rounding control and SAE in the instruction. */
191struct RC_Operation
192{
193 enum rc_type
194 {
195 rne = 0,
196 rd,
197 ru,
198 rz,
199 saeonly
200 } type;
201 int operand;
202};
203
204static struct RC_Operation rc_op;
205
206/* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209struct Mask_Operation
210{
211 const reg_entry *mask;
212 unsigned int zeroing;
213 /* The operand where this operation is associated. */
214 int operand;
215};
216
217static struct Mask_Operation mask_op;
218
219/* The struct describes broadcasting, applied to OPERAND. FACTOR is
220 broadcast factor. */
221struct Broadcast_Operation
222{
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
224 int type;
225
226 /* Index of broadcasted operand. */
227 int operand;
228};
229
230static struct Broadcast_Operation broadcast_op;
231
c0f3af97
L		 232/* VEX prefix. */
233typedef struct
234{
43234a1e
L		 235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes[4];
c0f3af97
L		 237 unsigned int length;
238 /* Destination or source register specifier. */
239 const reg_entry *register_specifier;
240} vex_prefix;
241
252b5132 242/* 'md_assemble ()' gathers together information and puts it into a
47926f60 243 i386_insn. */
252b5132 244
520dc8e8
AM		 245union i386_op
246 {
247 expressionS *disps;
248 expressionS *imms;
249 const reg_entry *regs;
250 };
251
a65babc9
L		 252enum i386_error
253 {
86e026a4 254 operand_size_mismatch,
a65babc9
L		 255 operand_type_mismatch,
256 register_type_mismatch,
257 number_of_operands_mismatch,
258 invalid_instruction_suffix,
259 bad_imm4,
260 old_gcc_only,
261 unsupported_with_intel_mnemonic,
262 unsupported_syntax,
6c30d220
L		 263 unsupported,
264 invalid_vsib_address,
7bab8ab5 265 invalid_vector_register_set,
43234a1e
L		 266 unsupported_vector_index_register,
267 unsupported_broadcast,
268 broadcast_not_on_src_operand,
269 broadcast_needed,
270 unsupported_masking,
271 mask_not_on_destination,
272 no_default_mask,
273 unsupported_rc_sae,
274 rc_sae_operand_not_last_imm,
275 invalid_register_operand,
276 try_vector_disp8
a65babc9
L		 277 };
278
252b5132
RH		 279struct _i386_insn
280 {
47926f60 281 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 282 insn_template tm;
252b5132 283
7d5e4556
L		 284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
252b5132
RH		 286 char suffix;
287
47926f60 288 /* OPERANDS gives the number of given operands. */
252b5132
RH		 289 unsigned int operands;
290
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
47926f60 293 operands. */
252b5132
RH		 294 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
295
296 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 297 use OP[i] for the corresponding operand. */
40fb9820 298 i386_operand_type types[MAX_OPERANDS];
252b5132 299
520dc8e8
AM		 300 /* Displacement expression, immediate expression, or register for each
301 operand. */
302 union i386_op op[MAX_OPERANDS];
252b5132 303
3e73aa7c
JH		 304 /* Flags for operands. */
305 unsigned int flags[MAX_OPERANDS];
306#define Operand_PCrel 1
307
252b5132 308 /* Relocation type for operand */
f86103b7 309 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 310
252b5132
RH		 311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry *base_reg;
314 const reg_entry *index_reg;
315 unsigned int log2_scale_factor;
316
317 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 318 explicit segment overrides are given. */
ce8a8b2f 319 const seg_entry *seg[2];
252b5132
RH		 320
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes;
324 unsigned char prefix[MAX_PREFIXES];
325
326 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 327 addressing modes of this insn are encoded. */
252b5132 328 modrm_byte rm;
3e73aa7c 329 rex_byte rex;
43234a1e 330 rex_byte vrex;
252b5132 331 sib_byte sib;
c0f3af97 332 vex_prefix vex;
b6169b20 333
43234a1e
L		 334 /* Masking attributes. */
335 struct Mask_Operation *mask;
336
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation *rounding;
339
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation *broadcast;
342
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift;
345
b6169b20 346 /* Swap operand in encoding. */
4473e004 347 unsigned int swap_operand;
891edac4 348
a501d77e
L		 349 /* Prefer 8bit or 32bit displacement in encoding. */
350 enum
351 {
352 disp_encoding_default = 0,
353 disp_encoding_8bit,
354 disp_encoding_32bit
355 } disp_encoding;
f8a5c266 356
d5de92cf
L		 357 /* REP prefix. */
358 const char *rep_prefix;
359
165de32a
L		 360 /* HLE prefix. */
361 const char *hle_prefix;
42164a71 362
7e8b059b
L		 363 /* Have BND prefix. */
364 const char *bnd_prefix;
365
43234a1e
L		 366 /* Need VREX to support upper 16 registers. */
367 int need_vrex;
368
891edac4 369 /* Error message. */
a65babc9 370 enum i386_error error;
252b5132
RH		 371 };
372
373typedef struct _i386_insn i386_insn;
374
43234a1e
L		 375/* Link RC type with corresponding string, that'll be looked for in
376 asm. */
377struct RC_name
378{
379 enum rc_type type;
380 const char *name;
381 unsigned int len;
382};
383
384static const struct RC_name RC_NamesTable[] =
385{
386 { rne, STRING_COMMA_LEN ("rn-sae") },
387 { rd, STRING_COMMA_LEN ("rd-sae") },
388 { ru, STRING_COMMA_LEN ("ru-sae") },
389 { rz, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly, STRING_COMMA_LEN ("sae") },
391};
392
252b5132
RH		 393/* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 395const char extra_symbol_chars[] = "*%-([{"
252b5132 396#ifdef LEX_AT
32137342
NC		 397 "@"
398#endif
399#ifdef LEX_QM
400 "?"
252b5132 401#endif
32137342 402 ;
252b5132 403
29b0f896
AM		 404#if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 406 && !defined (TE_GNU) \
29b0f896 407 && !defined (TE_LINUX) \
8d63c93e
RM		 408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
29b0f896 410 && !defined (TE_FreeBSD) \
5b806d27 411 && !defined (TE_DragonFly) \
29b0f896 412 && !defined (TE_NetBSD)))
252b5132 413/* This array holds the chars that always start a comment. If the
b3b91714
AM		 414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416const char *i386_comment_chars = "#/";
417#define SVR4_COMMENT_CHARS 1
252b5132 418#define PREFIX_SEPARATOR '\\'
252b5132 419
b3b91714
AM		 420#else
421const char *i386_comment_chars = "#";
422#define PREFIX_SEPARATOR '/'
423#endif
424
252b5132
RH		 425/* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 429 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
252b5132 432 '/' isn't otherwise defined. */
b3b91714 433const char line_comment_chars[] = "#/";
252b5132 434
63a0b638 435const char line_separator_chars[] = ";";
252b5132 436
ce8a8b2f
AM		 437/* Chars that can be used to separate mant from exp in floating point
438 nums. */
252b5132
RH		 439const char EXP_CHARS[] = "eE";
440
ce8a8b2f
AM		 441/* Chars that mean this number is a floating point constant
442 As in 0f12.456
443 or 0d1.2345e12. */
252b5132
RH		 444const char FLT_CHARS[] = "fFdDxX";
445
ce8a8b2f 446/* Tables for lexical analysis. */
252b5132
RH		 447static char mnemonic_chars[256];
448static char register_chars[256];
449static char operand_chars[256];
450static char identifier_chars[256];
451static char digit_chars[256];
452
ce8a8b2f 453/* Lexical macros. */
252b5132
RH		 454#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455#define is_operand_char(x) (operand_chars[(unsigned char) x])
456#define is_register_char(x) (register_chars[(unsigned char) x])
457#define is_space_char(x) ((x) == ' ')
458#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459#define is_digit_char(x) (digit_chars[(unsigned char) x])
460
0234cb7c 461/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 462static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
463
464/* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
47926f60 467 assembler instruction). */
252b5132 468static char save_stack[32];
ce8a8b2f 469static char *save_stack_p;
252b5132
RH		 470#define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472#define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
474
47926f60 475/* The instruction we're assembling. */
252b5132
RH		 476static i386_insn i;
477
478/* Possible templates for current insn. */
479static const templates *current_templates;
480
31b2323c
L		 481/* Per instruction expressionS buffers: max displacements & immediates. */
482static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
483static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 484
47926f60 485/* Current operand we are working on. */
ee86248c 486static int this_operand = -1;
252b5132 487
3e73aa7c
JH		 488/* We support four different modes. FLAG_CODE variable is used to distinguish
489 these. */
490
491enum flag_code {
492 CODE_32BIT,
493 CODE_16BIT,
494 CODE_64BIT };
495
496static enum flag_code flag_code;
4fa24527 497static unsigned int object_64bit;
862be3fb 498static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 499static int use_rela_relocations = 0;
500
7af8ed2d
NC		 501#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
504
351f65ca
L		 505/* The ELF ABI to use. */
506enum x86_elf_abi
507{
508 I386_ABI,
7f56bc95
L		 509 X86_64_ABI,
510 X86_64_X32_ABI
351f65ca
L		 511};
512
513static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 514#endif
351f65ca 515
167ad85b
TG		 516#if defined (TE_PE) || defined (TE_PEP)
517/* Use big object file format. */
518static int use_big_obj = 0;
519#endif
520
8dcea932
L		 521#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
522/* 1 if generating code for a shared library. */
523static int shared = 0;
524#endif
525
47926f60
KH		 526/* 1 for intel syntax,
527 0 if att syntax. */
528static int intel_syntax = 0;
252b5132 529
1efbbeb4
L		 530/* 1 for intel mnemonic,
531 0 if att mnemonic. */
532static int intel_mnemonic = !SYSV386_COMPAT;
533
5209009a 534/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 535static int old_gcc = OLDGCC_COMPAT;
536
a60de03c
JB		 537/* 1 if pseudo registers are permitted. */
538static int allow_pseudo_reg = 0;
539
47926f60
KH		 540/* 1 if register prefix % not required. */
541static int allow_naked_reg = 0;
252b5132 542
7e8b059b
L		 543/* 1 if the assembler should add BND prefix for all control-tranferring
544 instructions supporting it, even if this prefix wasn't specified
545 explicitly. */
546static int add_bnd_prefix = 0;
547
ba104c83 548/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 549static int allow_index_reg = 0;
550
d022bddd
IT		 551/* 1 if the assembler should ignore LOCK prefix, even if it was
552 specified explicitly. */
553static int omit_lock_prefix = 0;
554
e4e00185
AS		 555/* 1 if the assembler should encode lfence, mfence, and sfence as
556 "lock addl $0, (%{re}sp)". */
557static int avoid_fence = 0;
558
0cb4071e
L		 559/* 1 if the assembler should generate relax relocations. */
560
561static int generate_relax_relocations
562 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
563
7bab8ab5 564static enum check_kind
daf50ae7 565 {
7bab8ab5
JB		 566 check_none = 0,
567 check_warning,
568 check_error
daf50ae7 569 }
7bab8ab5 570sse_check, operand_check = check_warning;
daf50ae7 571
2ca3ace5
L		 572/* Register prefix used for error message. */
573static const char *register_prefix = "%";
574
47926f60
KH		 575/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
576 leave, push, and pop instructions so that gcc has the same stack
577 frame as in 32 bit mode. */
578static char stackop_size = '\0';
eecb386c 579
12b55ccc
L		 580/* Non-zero to optimize code alignment. */
581int optimize_align_code = 1;
582
47926f60
KH		 583/* Non-zero to quieten some warnings. */
584static int quiet_warnings = 0;
a38cf1db 585
47926f60
KH		 586/* CPU name. */
587static const char *cpu_arch_name = NULL;
6305a203 588static char *cpu_sub_arch_name = NULL;
a38cf1db 589
47926f60 590/* CPU feature flags. */
40fb9820
L		 591static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
592
ccc9c027
L		 593/* If we have selected a cpu we are generating instructions for. */
594static int cpu_arch_tune_set = 0;
595
9103f4f4 596/* Cpu we are generating instructions for. */
fbf3f584 597enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 598
599/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 600static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 601
ccc9c027 602/* CPU instruction set architecture used. */
fbf3f584 603enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 604
9103f4f4 605/* CPU feature flags of instruction set architecture used. */
fbf3f584 606i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 607
fddf5b5b
AM		 608/* If set, conditional jumps are not automatically promoted to handle
609 larger than a byte offset. */
610static unsigned int no_cond_jump_promotion = 0;
611
c0f3af97
L		 612/* Encode SSE instructions with VEX prefix. */
613static unsigned int sse2avx;
614
539f890d
L		 615/* Encode scalar AVX instructions with specific vector length. */
616static enum
617 {
618 vex128 = 0,
619 vex256
620 } avxscalar;
621
43234a1e
L		 622/* Encode scalar EVEX LIG instructions with specific vector length. */
623static enum
624 {
625 evexl128 = 0,
626 evexl256,
627 evexl512
628 } evexlig;
629
630/* Encode EVEX WIG instructions with specific evex.w. */
631static enum
632 {
633 evexw0 = 0,
634 evexw1
635 } evexwig;
636
d3d3c6db
IT		 637/* Value to encode in EVEX RC bits, for SAE-only instructions. */
638static enum rc_type evexrcig = rne;
639
29b0f896 640/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 641static symbolS *GOT_symbol;
29b0f896 642
a4447b93
RH		 643/* The dwarf2 return column, adjusted for 32 or 64 bit. */
644unsigned int x86_dwarf2_return_column;
645
646/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
647int x86_cie_data_alignment;
648
252b5132 649/* Interface to relax_segment.
fddf5b5b
AM		 650 There are 3 major relax states for 386 jump insns because the
651 different types of jumps add different sizes to frags when we're
652 figuring out what sort of jump to choose to reach a given label. */
252b5132 653
47926f60 654/* Types. */
93c2a809
AM		 655#define UNCOND_JUMP 0
656#define COND_JUMP 1
657#define COND_JUMP86 2
fddf5b5b 658
47926f60 659/* Sizes. */
252b5132
RH		 660#define CODE16 1
661#define SMALL 0
29b0f896 662#define SMALL16 (SMALL | CODE16)
252b5132 663#define BIG 2
29b0f896 664#define BIG16 (BIG | CODE16)
252b5132
RH		 665
666#ifndef INLINE
667#ifdef __GNUC__
668#define INLINE __inline__
669#else
670#define INLINE
671#endif
672#endif
673
fddf5b5b
AM		 674#define ENCODE_RELAX_STATE(type, size) \
675 ((relax_substateT) (((type) << 2) | (size)))
676#define TYPE_FROM_RELAX_STATE(s) \
677 ((s) >> 2)
678#define DISP_SIZE_FROM_RELAX_STATE(s) \
679 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 680
681/* This table is used by relax_frag to promote short jumps to long
682 ones where necessary. SMALL (short) jumps may be promoted to BIG
683 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
684 don't allow a short jump in a 32 bit code segment to be promoted to
685 a 16 bit offset jump because it's slower (requires data size
686 prefix), and doesn't work, unless the destination is in the bottom
687 64k of the code segment (The top 16 bits of eip are zeroed). */
688
689const relax_typeS md_relax_table[] =
690{
24eab124
AM		 691 /* The fields are:
692 1) most positive reach of this state,
693 2) most negative reach of this state,
93c2a809 694 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 695 4) which index into the table to try if we can't fit into this one. */
252b5132 696
fddf5b5b 697 /* UNCOND_JUMP states. */
93c2a809
AM		 698 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
699 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
700 /* dword jmp adds 4 bytes to frag:
701 0 extra opcode bytes, 4 displacement bytes. */
252b5132 702 {0, 0, 4, 0},
93c2a809
AM		 703 /* word jmp adds 2 byte2 to frag:
704 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 705 {0, 0, 2, 0},
706
93c2a809
AM		 707 /* COND_JUMP states. */
708 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
709 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
710 /* dword conditionals adds 5 bytes to frag:
711 1 extra opcode byte, 4 displacement bytes. */
712 {0, 0, 5, 0},
fddf5b5b 713 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 714 1 extra opcode byte, 2 displacement bytes. */
715 {0, 0, 3, 0},
716
717 /* COND_JUMP86 states. */
718 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
719 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
720 /* dword conditionals adds 5 bytes to frag:
721 1 extra opcode byte, 4 displacement bytes. */
722 {0, 0, 5, 0},
723 /* word conditionals add 4 bytes to frag:
724 1 displacement byte and a 3 byte long branch insn. */
725 {0, 0, 4, 0}
252b5132
RH		 726};
727
9103f4f4
L		 728static const arch_entry cpu_arch[] =
729{
89507696
JB		 730 /* Do not replace the first two entries - i386_target_format()
731 relies on them being there in this order. */
8a2c8fef 732 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 733 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 734 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 735 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 736 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 737 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 738 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 739 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 740 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 741 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 742 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 743 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 744 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 745 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 746 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 747 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 748 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 749 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 750 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 751 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 752 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 753 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 754 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 755 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 756 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 757 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 758 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 759 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 760 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 761 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 762 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 763 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 764 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 765 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 766 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 767 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 768 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 769 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 770 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 771 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 772 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 773 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 774 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 775 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 776 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
777 CPU_K1OM_FLAGS, 0, 0 },
81486035
L		 778 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
779 CPU_IAMCU_FLAGS, 0, 0 },
8a2c8fef 780 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 781 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 782 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 783 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 784 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 785 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 786 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 787 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 788 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 789 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 790 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 791 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 792 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 793 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 794 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 795 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 796 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 797 CPU_BDVER2_FLAGS, 0, 0 },
5e5c50d3
NE		 798 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
799 CPU_BDVER3_FLAGS, 0, 0 },
c7b0bd56
SE		 800 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
801 CPU_BDVER4_FLAGS, 0, 0 },
029f3522 802 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
3739860c 803 CPU_ZNVER1_FLAGS, 0, 0 },
7b458c12
L		 804 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
805 CPU_BTVER1_FLAGS, 0, 0 },
806 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
807 CPU_BTVER2_FLAGS, 0, 0 },
8a2c8fef 808 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 809 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 810 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 811 CPU_287_FLAGS, 0, 0 },
8a2c8fef 812 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 813 CPU_387_FLAGS, 0, 0 },
8a2c8fef 814 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 815 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 816 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 817 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 818 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 819 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 820 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 821 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 822 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 823 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 824 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 825 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 826 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 827 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 828 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 829 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 830 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 831 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 832 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 833 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 834 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 835 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 836 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 837 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 838 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
839 CPU_AVX2_FLAGS, 0, 0 },
43234a1e
L		 840 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
841 CPU_AVX512F_FLAGS, 0, 0 },
842 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
843 CPU_AVX512CD_FLAGS, 0, 0 },
844 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
845 CPU_AVX512ER_FLAGS, 0, 0 },
846 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
847 CPU_AVX512PF_FLAGS, 0, 0 },
1dfc6506
L		 848 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
849 CPU_AVX512DQ_FLAGS, 0, 0 },
850 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
851 CPU_AVX512BW_FLAGS, 0, 0 },
852 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
853 CPU_AVX512VL_FLAGS, 0, 0 },
8a2c8fef 854 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 855 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 856 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 857 CPU_VMX_FLAGS, 0, 0 },
8729a6f6
L		 858 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
859 CPU_VMFUNC_FLAGS, 0, 0 },
8a2c8fef 860 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 861 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 862 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 863 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 864 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 865 CPU_XSAVEOPT_FLAGS, 0, 0 },
1dfc6506
L		 866 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
867 CPU_XSAVEC_FLAGS, 0, 0 },
868 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
869 CPU_XSAVES_FLAGS, 0, 0 },
8a2c8fef 870 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 871 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 872 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 873 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 874 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 875 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 876 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 877 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 878 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 879 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 880 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 881 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 882 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
883 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 884 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 885 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 886 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 887 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 888 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 889 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 890 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 891 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 892 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 893 CPU_MOVBE_FLAGS, 0, 0 },
60aa667e
L		 894 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
895 CPU_CX16_FLAGS, 0, 0 },
8a2c8fef 896 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 897 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 898 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
899 CPU_LZCNT_FLAGS, 0, 0 },
42164a71
L		 900 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
901 CPU_HLE_FLAGS, 0, 0 },
902 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
903 CPU_RTM_FLAGS, 0, 0 },
6c30d220
L		 904 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
905 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 906 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 907 CPU_CLFLUSH_FLAGS, 0, 0 },
908 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
909 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 910 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 911 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 912 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 913 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 914 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 915 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 916 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 917 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 918 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 919 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 920 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 921 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 922 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 923 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 924 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 925 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 926 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 927 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 928 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
929 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 930 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
931 CPU_TBM_FLAGS, 0, 0 },
e2e1fcde
L		 932 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
933 CPU_ADX_FLAGS, 0, 0 },
934 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
935 CPU_RDSEED_FLAGS, 0, 0 },
936 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
937 CPU_PRFCHW_FLAGS, 0, 0 },
5c111e37
L		 938 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
939 CPU_SMAP_FLAGS, 0, 0 },
7e8b059b
L		 940 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
941 CPU_MPX_FLAGS, 0, 0 },
a0046408
L		 942 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
943 CPU_SHA_FLAGS, 0, 0 },
963f3586
IT		 944 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
945 CPU_CLFLUSHOPT_FLAGS, 0, 0 },
dcf893b5
IT		 946 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
947 CPU_PREFETCHWT1_FLAGS, 0, 0 },
2cf200a4
IT		 948 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
949 CPU_SE1_FLAGS, 0, 0 },
c5e7287a
IT		 950 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
951 CPU_CLWB_FLAGS, 0, 0 },
9d8596f0
IT		 952 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN,
953 CPU_PCOMMIT_FLAGS, 0, 0 },
2cc1b5aa
IT		 954 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
955 CPU_AVX512IFMA_FLAGS, 0, 0 },
14f195c9
IT		 956 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
957 CPU_AVX512VBMI_FLAGS, 0, 0 },
029f3522
GG		 958 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
959 CPU_CLZERO_FLAGS, 0, 0 },
9916071f
AP		 960 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
961 CPU_MWAITX_FLAGS, 0, 0 },
8eab4136
L		 962 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
963 CPU_OSPKE_FLAGS, 0, 0 },
e413e4e9
AM		 964};
965
704209c0 966#ifdef I386COFF
a6c24e68
NC		 967/* Like s_lcomm_internal in gas/read.c but the alignment string
968 is allowed to be optional. */
969
970static symbolS *
971pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
972{
973 addressT align = 0;
974
975 SKIP_WHITESPACE ();
976
7ab9ffdd 977 if (needs_align
a6c24e68
NC		 978 && *input_line_pointer == ',')
979 {
980 align = parse_align (needs_align - 1);
7ab9ffdd 981
a6c24e68
NC		 982 if (align == (addressT) -1)
983 return NULL;
984 }
985 else
986 {
987 if (size >= 8)
988 align = 3;
989 else if (size >= 4)
990 align = 2;
991 else if (size >= 2)
992 align = 1;
993 else
994 align = 0;
995 }
996
997 bss_alloc (symbolP, size, align);
998 return symbolP;
999}
1000
704209c0 1001static void
a6c24e68
NC		 1002pe_lcomm (int needs_align)
1003{
1004 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1005}
704209c0 1006#endif
a6c24e68 1007
29b0f896
AM		 1008const pseudo_typeS md_pseudo_table[] =
1009{
1010#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1011 {"align", s_align_bytes, 0},
1012#else
1013 {"align", s_align_ptwo, 0},
1014#endif
1015 {"arch", set_cpu_arch, 0},
1016#ifndef I386COFF
1017 {"bss", s_bss, 0},
a6c24e68
NC		 1018#else
1019 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1020#endif
1021 {"ffloat", float_cons, 'f'},
1022 {"dfloat", float_cons, 'd'},
1023 {"tfloat", float_cons, 'x'},
1024 {"value", cons, 2},
d182319b 1025 {"slong", signed_cons, 4},
29b0f896
AM		 1026 {"noopt", s_ignore, 0},
1027 {"optim", s_ignore, 0},
1028 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1029 {"code16", set_code_flag, CODE_16BIT},
1030 {"code32", set_code_flag, CODE_32BIT},
1031 {"code64", set_code_flag, CODE_64BIT},
1032 {"intel_syntax", set_intel_syntax, 1},
1033 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1034 {"intel_mnemonic", set_intel_mnemonic, 1},
1035 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1036 {"allow_index_reg", set_allow_index_reg, 1},
1037 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1038 {"sse_check", set_check, 0},
1039 {"operand_check", set_check, 1},
3b22753a
L		 1040#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1041 {"largecomm", handle_large_common, 0},
07a53e5c 1042#else
e3bb37b5 1043 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1044 {"loc", dwarf2_directive_loc, 0},
1045 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1046#endif
6482c264
NC		 1047#ifdef TE_PE
1048 {"secrel32", pe_directive_secrel, 0},
1049#endif
29b0f896
AM		 1050 {0, 0, 0}
1051};
1052
1053/* For interface with expression (). */
1054extern char *input_line_pointer;
1055
1056/* Hash table for instruction mnemonic lookup. */
1057static struct hash_control *op_hash;
1058
1059/* Hash table for register lookup. */
1060static struct hash_control *reg_hash;
1061\f
252b5132 1062void
e3bb37b5 1063i386_align_code (fragS *fragP, int count)
252b5132 1064{
ce8a8b2f
AM		 1065 /* Various efficient no-op patterns for aligning code labels.
1066 Note: Don't try to assemble the instructions in the comments.
1067 0L and 0w are not legal. */
bad6e36d 1068 static const unsigned char f32_1[] =
252b5132 1069 {0x90}; /* nop */
bad6e36d 1070 static const unsigned char f32_2[] =
ccc9c027 1071 {0x66,0x90}; /* xchg %ax,%ax */
bad6e36d 1072 static const unsigned char f32_3[] =
252b5132 1073 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
bad6e36d 1074 static const unsigned char f32_4[] =
252b5132 1075 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1076 static const unsigned char f32_5[] =
252b5132
RH		 1077 {0x90, /* nop */
1078 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1079 static const unsigned char f32_6[] =
252b5132 1080 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
bad6e36d 1081 static const unsigned char f32_7[] =
252b5132 1082 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1083 static const unsigned char f32_8[] =
252b5132
RH		 1084 {0x90, /* nop */
1085 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1086 static const unsigned char f32_9[] =
252b5132
RH		 1087 {0x89,0xf6, /* movl %esi,%esi */
1088 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1089 static const unsigned char f32_10[] =
252b5132
RH		 1090 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1091 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1092 static const unsigned char f32_11[] =
252b5132
RH		 1093 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1094 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1095 static const unsigned char f32_12[] =
252b5132
RH		 1096 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1097 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
bad6e36d 1098 static const unsigned char f32_13[] =
252b5132
RH		 1099 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1100 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1101 static const unsigned char f32_14[] =
252b5132
RH		 1102 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1103 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1104 static const unsigned char f16_3[] =
c3332e24 1105 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
bad6e36d 1106 static const unsigned char f16_4[] =
252b5132 1107 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1108 static const unsigned char f16_5[] =
252b5132
RH		 1109 {0x90, /* nop */
1110 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1111 static const unsigned char f16_6[] =
252b5132
RH		 1112 {0x89,0xf6, /* mov %si,%si */
1113 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1114 static const unsigned char f16_7[] =
252b5132
RH		 1115 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1116 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1117 static const unsigned char f16_8[] =
252b5132
RH		 1118 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1119 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1120 static const unsigned char jump_31[] =
76bc74dc
L		 1121 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1122 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1123 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1124 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
bad6e36d 1125 static const unsigned char *const f32_patt[] = {
252b5132 1126 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1127 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132 1128 };
bad6e36d 1129 static const unsigned char *const f16_patt[] = {
76bc74dc 1130 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1131 };
ccc9c027 1132 /* nopl (%[re]ax) */
bad6e36d 1133 static const unsigned char alt_3[] =
ccc9c027
L		 1134 {0x0f,0x1f,0x00};
1135 /* nopl 0(%[re]ax) */
bad6e36d 1136 static const unsigned char alt_4[] =
ccc9c027
L		 1137 {0x0f,0x1f,0x40,0x00};
1138 /* nopl 0(%[re]ax,%[re]ax,1) */
bad6e36d 1139 static const unsigned char alt_5[] =
ccc9c027
L		 1140 {0x0f,0x1f,0x44,0x00,0x00};
1141 /* nopw 0(%[re]ax,%[re]ax,1) */
bad6e36d 1142 static const unsigned char alt_6[] =
ccc9c027
L		 1143 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1144 /* nopl 0L(%[re]ax) */
bad6e36d 1145 static const unsigned char alt_7[] =
ccc9c027
L		 1146 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1147 /* nopl 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1148 static const unsigned char alt_8[] =
ccc9c027
L		 1149 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1150 /* nopw 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1151 static const unsigned char alt_9[] =
ccc9c027
L		 1152 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1153 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
bad6e36d 1154 static const unsigned char alt_10[] =
ccc9c027 1155 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
bad6e36d 1156 static const unsigned char *const alt_patt[] = {
ccc9c027 1157 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
80b8656c 1158 alt_9, alt_10
ccc9c027 1159 };
252b5132 1160
76bc74dc
L		 1161 /* Only align for at least a positive non-zero boundary. */
1162 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1163 return;
3e73aa7c 1164
ccc9c027
L		 1165 /* We need to decide which NOP sequence to use for 32bit and
1166 64bit. When -mtune= is used:
4eed87de 1167
76bc74dc
L		 1168 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1169 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1170 2. For the rest, alt_patt will be used.
1171
1172 When -mtune= isn't used, alt_patt will be used if
22109423 1173 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1174 be used.
ccc9c027
L		 1175
1176 When -march= or .arch is used, we can't use anything beyond
1177 cpu_arch_isa_flags. */
1178
1179 if (flag_code == CODE_16BIT)
1180 {
ccc9c027 1181 if (count > 8)
33fef721 1182 {
76bc74dc
L		 1183 memcpy (fragP->fr_literal + fragP->fr_fix,
1184 jump_31, count);
1185 /* Adjust jump offset. */
1186 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1187 }
76bc74dc
L		 1188 else
1189 memcpy (fragP->fr_literal + fragP->fr_fix,
1190 f16_patt[count - 1], count);
252b5132 1191 }
33fef721 1192 else
ccc9c027 1193 {
bad6e36d 1194 const unsigned char *const *patt = NULL;
ccc9c027 1195
fbf3f584 1196 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1197 {
1198 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1199 switch (cpu_arch_tune)
1200 {
1201 case PROCESSOR_UNKNOWN:
1202 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1203 optimize with nops. */
1204 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1205 patt = alt_patt;
ccc9c027
L		 1206 else
1207 patt = f32_patt;
1208 break;
ccc9c027
L		 1209 case PROCESSOR_PENTIUM4:
1210 case PROCESSOR_NOCONA:
ef05d495 1211 case PROCESSOR_CORE:
76bc74dc 1212 case PROCESSOR_CORE2:
bd5295b2 1213 case PROCESSOR_COREI7:
3632d14b 1214 case PROCESSOR_L1OM:
7a9068fe 1215 case PROCESSOR_K1OM:
76bc74dc 1216 case PROCESSOR_GENERIC64:
ccc9c027
L		 1217 case PROCESSOR_K6:
1218 case PROCESSOR_ATHLON:
1219 case PROCESSOR_K8:
4eed87de 1220 case PROCESSOR_AMDFAM10:
8aedb9fe 1221 case PROCESSOR_BD:
029f3522 1222 case PROCESSOR_ZNVER:
7b458c12 1223 case PROCESSOR_BT:
80b8656c 1224 patt = alt_patt;
ccc9c027 1225 break;
76bc74dc 1226 case PROCESSOR_I386:
ccc9c027
L		 1227 case PROCESSOR_I486:
1228 case PROCESSOR_PENTIUM:
2dde1948 1229 case PROCESSOR_PENTIUMPRO:
81486035 1230 case PROCESSOR_IAMCU:
ccc9c027
L		 1231 case PROCESSOR_GENERIC32:
1232 patt = f32_patt;
1233 break;
4eed87de 1234 }
ccc9c027
L		 1235 }
1236 else
1237 {
fbf3f584 1238 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1239 {
1240 case PROCESSOR_UNKNOWN:
e6a14101 1241 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1242 PROCESSOR_UNKNOWN. */
1243 abort ();
1244 break;
1245
76bc74dc 1246 case PROCESSOR_I386:
ccc9c027
L		 1247 case PROCESSOR_I486:
1248 case PROCESSOR_PENTIUM:
81486035 1249 case PROCESSOR_IAMCU:
ccc9c027
L		 1250 case PROCESSOR_K6:
1251 case PROCESSOR_ATHLON:
1252 case PROCESSOR_K8:
4eed87de 1253 case PROCESSOR_AMDFAM10:
8aedb9fe 1254 case PROCESSOR_BD:
029f3522 1255 case PROCESSOR_ZNVER:
7b458c12 1256 case PROCESSOR_BT:
ccc9c027
L		 1257 case PROCESSOR_GENERIC32:
1258 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1259 with nops. */
1260 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1261 patt = alt_patt;
ccc9c027
L		 1262 else
1263 patt = f32_patt;
1264 break;
76bc74dc
L		 1265 case PROCESSOR_PENTIUMPRO:
1266 case PROCESSOR_PENTIUM4:
1267 case PROCESSOR_NOCONA:
1268 case PROCESSOR_CORE:
ef05d495 1269 case PROCESSOR_CORE2:
bd5295b2 1270 case PROCESSOR_COREI7:
3632d14b 1271 case PROCESSOR_L1OM:
7a9068fe 1272 case PROCESSOR_K1OM:
22109423 1273 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1274 patt = alt_patt;
ccc9c027
L		 1275 else
1276 patt = f32_patt;
1277 break;
1278 case PROCESSOR_GENERIC64:
80b8656c 1279 patt = alt_patt;
ccc9c027 1280 break;
4eed87de 1281 }
ccc9c027
L		 1282 }
1283
76bc74dc
L		 1284 if (patt == f32_patt)
1285 {
1286 /* If the padding is less than 15 bytes, we use the normal
1287 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1288 its offset. */
1289 int limit;
76ba9986 1290
711eedef
L		 1291 /* For 64bit, the limit is 3 bytes. */
1292 if (flag_code == CODE_64BIT
1293 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1294 limit = 3;
1295 else
1296 limit = 15;
1297 if (count < limit)
76bc74dc
L		 1298 memcpy (fragP->fr_literal + fragP->fr_fix,
1299 patt[count - 1], count);
1300 else
1301 {
1302 memcpy (fragP->fr_literal + fragP->fr_fix,
1303 jump_31, count);
1304 /* Adjust jump offset. */
1305 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1306 }
1307 }
1308 else
1309 {
80b8656c
L		 1310 /* Maximum length of an instruction is 10 byte. If the
1311 padding is greater than 10 bytes and we don't use jump,
76bc74dc
L		 1312 we have to break it into smaller pieces. */
1313 int padding = count;
80b8656c 1314 while (padding > 10)
76bc74dc 1315 {
80b8656c 1316 padding -= 10;
76bc74dc 1317 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
80b8656c 1318 patt [9], 10);
76bc74dc
L		 1319 }
1320
1321 if (padding)
1322 memcpy (fragP->fr_literal + fragP->fr_fix,
1323 patt [padding - 1], padding);
1324 }
ccc9c027 1325 }
33fef721 1326 fragP->fr_var = count;
252b5132
RH		 1327}
1328
c6fb90c8 1329static INLINE int
0dfbf9d7 1330operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1331{
0dfbf9d7 1332 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1333 {
1334 case 3:
0dfbf9d7 1335 if (x->array[2])
c6fb90c8
L		 1336 return 0;
1337 case 2:
0dfbf9d7 1338 if (x->array[1])
c6fb90c8
L		 1339 return 0;
1340 case 1:
0dfbf9d7 1341 return !x->array[0];
c6fb90c8
L		 1342 default:
1343 abort ();
1344 }
40fb9820
L		 1345}
1346
c6fb90c8 1347static INLINE void
0dfbf9d7 1348operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1349{
0dfbf9d7 1350 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1351 {
1352 case 3:
0dfbf9d7 1353 x->array[2] = v;
c6fb90c8 1354 case 2:
0dfbf9d7 1355 x->array[1] = v;
c6fb90c8 1356 case 1:
0dfbf9d7 1357 x->array[0] = v;
c6fb90c8
L		 1358 break;
1359 default:
1360 abort ();
1361 }
1362}
40fb9820 1363
c6fb90c8 1364static INLINE int
0dfbf9d7
L		 1365operand_type_equal (const union i386_operand_type *x,
1366 const union i386_operand_type *y)
c6fb90c8 1367{
0dfbf9d7 1368 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1369 {
1370 case 3:
0dfbf9d7 1371 if (x->array[2] != y->array[2])
c6fb90c8
L		 1372 return 0;
1373 case 2:
0dfbf9d7 1374 if (x->array[1] != y->array[1])
c6fb90c8
L		 1375 return 0;
1376 case 1:
0dfbf9d7 1377 return x->array[0] == y->array[0];
c6fb90c8
L		 1378 break;
1379 default:
1380 abort ();
1381 }
1382}
40fb9820 1383
0dfbf9d7
L		 1384static INLINE int
1385cpu_flags_all_zero (const union i386_cpu_flags *x)
1386{
1387 switch (ARRAY_SIZE(x->array))
1388 {
1389 case 3:
1390 if (x->array[2])
1391 return 0;
1392 case 2:
1393 if (x->array[1])
1394 return 0;
1395 case 1:
1396 return !x->array[0];
1397 default:
1398 abort ();
1399 }
1400}
1401
0dfbf9d7
L		 1402static INLINE int
1403cpu_flags_equal (const union i386_cpu_flags *x,
1404 const union i386_cpu_flags *y)
1405{
1406 switch (ARRAY_SIZE(x->array))
1407 {
1408 case 3:
1409 if (x->array[2] != y->array[2])
1410 return 0;
1411 case 2:
1412 if (x->array[1] != y->array[1])
1413 return 0;
1414 case 1:
1415 return x->array[0] == y->array[0];
1416 break;
1417 default:
1418 abort ();
1419 }
1420}
c6fb90c8
L		 1421
1422static INLINE int
1423cpu_flags_check_cpu64 (i386_cpu_flags f)
1424{
1425 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1426 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1427}
1428
c6fb90c8
L		 1429static INLINE i386_cpu_flags
1430cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1431{
c6fb90c8
L		 1432 switch (ARRAY_SIZE (x.array))
1433 {
1434 case 3:
1435 x.array [2] &= y.array [2];
1436 case 2:
1437 x.array [1] &= y.array [1];
1438 case 1:
1439 x.array [0] &= y.array [0];
1440 break;
1441 default:
1442 abort ();
1443 }
1444 return x;
1445}
40fb9820 1446
c6fb90c8
L		 1447static INLINE i386_cpu_flags
1448cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1449{
c6fb90c8 1450 switch (ARRAY_SIZE (x.array))
40fb9820 1451 {
c6fb90c8
L		 1452 case 3:
1453 x.array [2] |= y.array [2];
1454 case 2:
1455 x.array [1] |= y.array [1];
1456 case 1:
1457 x.array [0] |= y.array [0];
40fb9820
L		 1458 break;
1459 default:
1460 abort ();
1461 }
40fb9820
L		 1462 return x;
1463}
1464
309d3373
JB		 1465static INLINE i386_cpu_flags
1466cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1467{
1468 switch (ARRAY_SIZE (x.array))
1469 {
1470 case 3:
1471 x.array [2] &= ~y.array [2];
1472 case 2:
1473 x.array [1] &= ~y.array [1];
1474 case 1:
1475 x.array [0] &= ~y.array [0];
1476 break;
1477 default:
1478 abort ();
1479 }
1480 return x;
1481}
1482
81486035
L		 1483static int
1484valid_iamcu_cpu_flags (const i386_cpu_flags *flags)
1485{
1486 if (cpu_arch_isa == PROCESSOR_IAMCU)
1487 {
1488 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_COMPAT_FLAGS;
1489 i386_cpu_flags compat_flags;
1490 compat_flags = cpu_flags_and_not (*flags, iamcu_flags);
1491 return cpu_flags_all_zero (&compat_flags);
1492 }
1493 else
1494 return 1;
1495}
1496
c0f3af97
L		 1497#define CPU_FLAGS_ARCH_MATCH 0x1
1498#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1499#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1500#define CPU_FLAGS_PCLMUL_MATCH 0x8
1501#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1502
a5ff0eb2 1503#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1504 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1505 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1506#define CPU_FLAGS_PERFECT_MATCH \
1507 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1508
1509/* Return CPU flags match bits. */
3629bb00 1510
40fb9820 1511static int
d3ce72d0 1512cpu_flags_match (const insn_template *t)
40fb9820 1513{
c0f3af97
L		 1514 i386_cpu_flags x = t->cpu_flags;
1515 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1516
1517 x.bitfield.cpu64 = 0;
1518 x.bitfield.cpuno64 = 0;
1519
0dfbf9d7 1520 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1521 {
1522 /* This instruction is available on all archs. */
1523 match |= CPU_FLAGS_32BIT_MATCH;
1524 }
3629bb00
L		 1525 else
1526 {
c0f3af97 1527 /* This instruction is available only on some archs. */
3629bb00
L		 1528 i386_cpu_flags cpu = cpu_arch_flags;
1529
1530 cpu.bitfield.cpu64 = 0;
1531 cpu.bitfield.cpuno64 = 0;
1532 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1533 if (!cpu_flags_all_zero (&cpu))
1534 {
a5ff0eb2
L		 1535 if (x.bitfield.cpuavx)
1536 {
ce2f5b3c 1537 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1538 if (cpu.bitfield.cpuavx)
1539 {
1540 /* Check SSE2AVX. */
1541 if (!t->opcode_modifier.sse2avx|| sse2avx)
1542 {
1543 match |= (CPU_FLAGS_ARCH_MATCH
1544 | CPU_FLAGS_AVX_MATCH);
1545 /* Check AES. */
1546 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1547 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1548 /* Check PCLMUL. */
1549 if (!x.bitfield.cpupclmul
1550 || cpu.bitfield.cpupclmul)
1551 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1552 }
1553 }
1554 else
1555 match |= CPU_FLAGS_ARCH_MATCH;
1556 }
1557 else
c0f3af97
L		 1558 match |= CPU_FLAGS_32BIT_MATCH;
1559 }
3629bb00 1560 }
c0f3af97 1561 return match;
40fb9820
L		 1562}
1563
c6fb90c8
L		 1564static INLINE i386_operand_type
1565operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1566{
c6fb90c8
L		 1567 switch (ARRAY_SIZE (x.array))
1568 {
1569 case 3:
1570 x.array [2] &= y.array [2];
1571 case 2:
1572 x.array [1] &= y.array [1];
1573 case 1:
1574 x.array [0] &= y.array [0];
1575 break;
1576 default:
1577 abort ();
1578 }
1579 return x;
40fb9820
L		 1580}
1581
c6fb90c8
L		 1582static INLINE i386_operand_type
1583operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1584{
c6fb90c8 1585 switch (ARRAY_SIZE (x.array))
40fb9820 1586 {
c6fb90c8
L		 1587 case 3:
1588 x.array [2] |= y.array [2];
1589 case 2:
1590 x.array [1] |= y.array [1];
1591 case 1:
1592 x.array [0] |= y.array [0];
40fb9820
L		 1593 break;
1594 default:
1595 abort ();
1596 }
c6fb90c8
L		 1597 return x;
1598}
40fb9820 1599
c6fb90c8
L		 1600static INLINE i386_operand_type
1601operand_type_xor (i386_operand_type x, i386_operand_type y)
1602{
1603 switch (ARRAY_SIZE (x.array))
1604 {
1605 case 3:
1606 x.array [2] ^= y.array [2];
1607 case 2:
1608 x.array [1] ^= y.array [1];
1609 case 1:
1610 x.array [0] ^= y.array [0];
1611 break;
1612 default:
1613 abort ();
1614 }
40fb9820
L		 1615 return x;
1616}
1617
1618static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1619static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1620static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1621static const i386_operand_type inoutportreg
1622 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1623static const i386_operand_type reg16_inoutportreg
1624 = OPERAND_TYPE_REG16_INOUTPORTREG;
1625static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1626static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1627static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1628static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1629static const i386_operand_type anydisp
1630 = OPERAND_TYPE_ANYDISP;
40fb9820 1631static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1632static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1633static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1634static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1635static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1636static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1637static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1638static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1639static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1640static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1641static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1642static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1643static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1644static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1645
1646enum operand_type
1647{
1648 reg,
40fb9820
L		 1649 imm,
1650 disp,
1651 anymem
1652};
1653
c6fb90c8 1654static INLINE int
40fb9820
L		 1655operand_type_check (i386_operand_type t, enum operand_type c)
1656{
1657 switch (c)
1658 {
1659 case reg:
1660 return (t.bitfield.reg8
1661 || t.bitfield.reg16
1662 || t.bitfield.reg32
1663 || t.bitfield.reg64);
1664
40fb9820
L		 1665 case imm:
1666 return (t.bitfield.imm8
1667 || t.bitfield.imm8s
1668 || t.bitfield.imm16
1669 || t.bitfield.imm32
1670 || t.bitfield.imm32s
1671 || t.bitfield.imm64);
1672
1673 case disp:
1674 return (t.bitfield.disp8
1675 || t.bitfield.disp16
1676 || t.bitfield.disp32
1677 || t.bitfield.disp32s
1678 || t.bitfield.disp64);
1679
1680 case anymem:
1681 return (t.bitfield.disp8
1682 || t.bitfield.disp16
1683 || t.bitfield.disp32
1684 || t.bitfield.disp32s
1685 || t.bitfield.disp64
1686 || t.bitfield.baseindex);
1687
1688 default:
1689 abort ();
1690 }
2cfe26b6
AM		 1691
1692 return 0;
40fb9820
L		 1693}
1694
5c07affc
L		 1695/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1696 operand J for instruction template T. */
1697
1698static INLINE int
d3ce72d0 1699match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1700{
1701 return !((i.types[j].bitfield.byte
1702 && !t->operand_types[j].bitfield.byte)
1703 || (i.types[j].bitfield.word
1704 && !t->operand_types[j].bitfield.word)
1705 || (i.types[j].bitfield.dword
1706 && !t->operand_types[j].bitfield.dword)
1707 || (i.types[j].bitfield.qword
1708 && !t->operand_types[j].bitfield.qword));
1709}
1710
1711/* Return 1 if there is no conflict in any size on operand J for
1712 instruction template T. */
1713
1714static INLINE int
d3ce72d0 1715match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1716{
1717 return (match_reg_size (t, j)
1718 && !((i.types[j].bitfield.unspecified
af508cb9 1719 && !i.broadcast
5c07affc
L		 1720 && !t->operand_types[j].bitfield.unspecified)
1721 || (i.types[j].bitfield.fword
1722 && !t->operand_types[j].bitfield.fword)
1723 || (i.types[j].bitfield.tbyte
1724 && !t->operand_types[j].bitfield.tbyte)
1725 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1726 && !t->operand_types[j].bitfield.xmmword)
1727 || (i.types[j].bitfield.ymmword
43234a1e
L		 1728 && !t->operand_types[j].bitfield.ymmword)
1729 || (i.types[j].bitfield.zmmword
1730 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1731}
1732
1733/* Return 1 if there is no size conflict on any operands for
1734 instruction template T. */
1735
1736static INLINE int
d3ce72d0 1737operand_size_match (const insn_template *t)
5c07affc
L		 1738{
1739 unsigned int j;
1740 int match = 1;
1741
1742 /* Don't check jump instructions. */
1743 if (t->opcode_modifier.jump
1744 || t->opcode_modifier.jumpbyte
1745 || t->opcode_modifier.jumpdword
1746 || t->opcode_modifier.jumpintersegment)
1747 return match;
1748
1749 /* Check memory and accumulator operand size. */
1750 for (j = 0; j < i.operands; j++)
1751 {
1752 if (t->operand_types[j].bitfield.anysize)
1753 continue;
1754
1755 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1756 {
1757 match = 0;
1758 break;
1759 }
1760
1761 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1762 {
1763 match = 0;
1764 break;
1765 }
1766 }
1767
891edac4 1768 if (match)
5c07affc 1769 return match;
891edac4
L		 1770 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1771 {
1772mismatch:
86e026a4 1773 i.error = operand_size_mismatch;
891edac4
L		 1774 return 0;
1775 }
5c07affc
L		 1776
1777 /* Check reverse. */
9c2799c2 1778 gas_assert (i.operands == 2);
5c07affc
L		 1779
1780 match = 1;
1781 for (j = 0; j < 2; j++)
1782 {
1783 if (t->operand_types[j].bitfield.acc
1784 && !match_reg_size (t, j ? 0 : 1))
891edac4 1785 goto mismatch;
5c07affc
L		 1786
1787 if (i.types[j].bitfield.mem
1788 && !match_mem_size (t, j ? 0 : 1))
891edac4 1789 goto mismatch;
5c07affc
L		 1790 }
1791
1792 return match;
1793}
1794
c6fb90c8 1795static INLINE int
40fb9820
L		 1796operand_type_match (i386_operand_type overlap,
1797 i386_operand_type given)
1798{
1799 i386_operand_type temp = overlap;
1800
1801 temp.bitfield.jumpabsolute = 0;
7d5e4556 1802 temp.bitfield.unspecified = 0;
5c07affc
L		 1803 temp.bitfield.byte = 0;
1804 temp.bitfield.word = 0;
1805 temp.bitfield.dword = 0;
1806 temp.bitfield.fword = 0;
1807 temp.bitfield.qword = 0;
1808 temp.bitfield.tbyte = 0;
1809 temp.bitfield.xmmword = 0;
c0f3af97 1810 temp.bitfield.ymmword = 0;
43234a1e 1811 temp.bitfield.zmmword = 0;
0dfbf9d7 1812 if (operand_type_all_zero (&temp))
891edac4 1813 goto mismatch;
40fb9820 1814
891edac4
L		 1815 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1816 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1817 return 1;
1818
1819mismatch:
a65babc9 1820 i.error = operand_type_mismatch;
891edac4 1821 return 0;
40fb9820
L		 1822}
1823
7d5e4556 1824/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1825 unless the expected operand type register overlap is null.
1826 Note that Acc in a template matches every size of reg. */
1827
c6fb90c8 1828static INLINE int
40fb9820
L		 1829operand_type_register_match (i386_operand_type m0,
1830 i386_operand_type g0,
1831 i386_operand_type t0,
1832 i386_operand_type m1,
1833 i386_operand_type g1,
1834 i386_operand_type t1)
1835{
1836 if (!operand_type_check (g0, reg))
1837 return 1;
1838
1839 if (!operand_type_check (g1, reg))
1840 return 1;
1841
1842 if (g0.bitfield.reg8 == g1.bitfield.reg8
1843 && g0.bitfield.reg16 == g1.bitfield.reg16
1844 && g0.bitfield.reg32 == g1.bitfield.reg32
1845 && g0.bitfield.reg64 == g1.bitfield.reg64)
1846 return 1;
1847
1848 if (m0.bitfield.acc)
1849 {
1850 t0.bitfield.reg8 = 1;
1851 t0.bitfield.reg16 = 1;
1852 t0.bitfield.reg32 = 1;
1853 t0.bitfield.reg64 = 1;
1854 }
1855
1856 if (m1.bitfield.acc)
1857 {
1858 t1.bitfield.reg8 = 1;
1859 t1.bitfield.reg16 = 1;
1860 t1.bitfield.reg32 = 1;
1861 t1.bitfield.reg64 = 1;
1862 }
1863
891edac4
L		 1864 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1865 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1866 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1867 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1868 return 1;
1869
a65babc9 1870 i.error = register_type_mismatch;
891edac4
L		 1871
1872 return 0;
40fb9820
L		 1873}
1874
4c692bc7
JB		 1875static INLINE unsigned int
1876register_number (const reg_entry *r)
1877{
1878 unsigned int nr = r->reg_num;
1879
1880 if (r->reg_flags & RegRex)
1881 nr += 8;
1882
200cbe0f
L		 1883 if (r->reg_flags & RegVRex)
1884 nr += 16;
1885
4c692bc7
JB		 1886 return nr;
1887}
1888
252b5132 1889static INLINE unsigned int
40fb9820 1890mode_from_disp_size (i386_operand_type t)
252b5132 1891{
43234a1e 1892 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1893 return 1;
1894 else if (t.bitfield.disp16
1895 || t.bitfield.disp32
1896 || t.bitfield.disp32s)
1897 return 2;
1898 else
1899 return 0;
252b5132
RH		 1900}
1901
1902static INLINE int
65879393 1903fits_in_signed_byte (addressT num)
252b5132 1904{
65879393 1905 return num + 0x80 <= 0xff;
47926f60 1906}
252b5132
RH		 1907
1908static INLINE int
65879393 1909fits_in_unsigned_byte (addressT num)
252b5132 1910{
65879393 1911 return num <= 0xff;
47926f60 1912}
252b5132
RH		 1913
1914static INLINE int
65879393 1915fits_in_unsigned_word (addressT num)
252b5132 1916{
65879393 1917 return num <= 0xffff;
47926f60 1918}
252b5132
RH		 1919
1920static INLINE int
65879393 1921fits_in_signed_word (addressT num)
252b5132 1922{
65879393 1923 return num + 0x8000 <= 0xffff;
47926f60 1924}
2a962e6d 1925
3e73aa7c 1926static INLINE int
65879393 1927fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1928{
1929#ifndef BFD64
1930 return 1;
1931#else
65879393 1932 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 1933#endif
1934} /* fits_in_signed_long() */
2a962e6d 1935
3e73aa7c 1936static INLINE int
65879393 1937fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1938{
1939#ifndef BFD64
1940 return 1;
1941#else
65879393 1942 return num <= 0xffffffff;
3e73aa7c
JH		 1943#endif
1944} /* fits_in_unsigned_long() */
252b5132 1945
43234a1e
L		 1946static INLINE int
1947fits_in_vec_disp8 (offsetT num)
1948{
1949 int shift = i.memshift;
1950 unsigned int mask;
1951
1952 if (shift == -1)
1953 abort ();
1954
1955 mask = (1 << shift) - 1;
1956
1957 /* Return 0 if NUM isn't properly aligned. */
1958 if ((num & mask))
1959 return 0;
1960
1961 /* Check if NUM will fit in 8bit after shift. */
1962 return fits_in_signed_byte (num >> shift);
1963}
1964
a683cc34
SP		 1965static INLINE int
1966fits_in_imm4 (offsetT num)
1967{
1968 return (num & 0xf) == num;
1969}
1970
40fb9820 1971static i386_operand_type
e3bb37b5 1972smallest_imm_type (offsetT num)
252b5132 1973{
40fb9820 1974 i386_operand_type t;
7ab9ffdd 1975
0dfbf9d7 1976 operand_type_set (&t, 0);
40fb9820
L		 1977 t.bitfield.imm64 = 1;
1978
1979 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1980 {
1981 /* This code is disabled on the 486 because all the Imm1 forms
1982 in the opcode table are slower on the i486. They're the
1983 versions with the implicitly specified single-position
1984 displacement, which has another syntax if you really want to
1985 use that form. */
40fb9820
L		 1986 t.bitfield.imm1 = 1;
1987 t.bitfield.imm8 = 1;
1988 t.bitfield.imm8s = 1;
1989 t.bitfield.imm16 = 1;
1990 t.bitfield.imm32 = 1;
1991 t.bitfield.imm32s = 1;
1992 }
1993 else if (fits_in_signed_byte (num))
1994 {
1995 t.bitfield.imm8 = 1;
1996 t.bitfield.imm8s = 1;
1997 t.bitfield.imm16 = 1;
1998 t.bitfield.imm32 = 1;
1999 t.bitfield.imm32s = 1;
2000 }
2001 else if (fits_in_unsigned_byte (num))
2002 {
2003 t.bitfield.imm8 = 1;
2004 t.bitfield.imm16 = 1;
2005 t.bitfield.imm32 = 1;
2006 t.bitfield.imm32s = 1;
2007 }
2008 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2009 {
2010 t.bitfield.imm16 = 1;
2011 t.bitfield.imm32 = 1;
2012 t.bitfield.imm32s = 1;
2013 }
2014 else if (fits_in_signed_long (num))
2015 {
2016 t.bitfield.imm32 = 1;
2017 t.bitfield.imm32s = 1;
2018 }
2019 else if (fits_in_unsigned_long (num))
2020 t.bitfield.imm32 = 1;
2021
2022 return t;
47926f60 2023}
252b5132 2024
847f7ad4 2025static offsetT
e3bb37b5 2026offset_in_range (offsetT val, int size)
847f7ad4 2027{
508866be 2028 addressT mask;
ba2adb93 2029
847f7ad4
AM		 2030 switch (size)
2031 {
508866be
L		 2032 case 1: mask = ((addressT) 1 << 8) - 1; break;
2033 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2034 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2035#ifdef BFD64
2036 case 8: mask = ((addressT) 2 << 63) - 1; break;
2037#endif
47926f60 2038 default: abort ();
847f7ad4
AM		 2039 }
2040
9de868bf
L		 2041#ifdef BFD64
2042 /* If BFD64, sign extend val for 32bit address mode. */
2043 if (flag_code != CODE_64BIT
2044 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2045 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2046 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2047#endif
ba2adb93 2048
47926f60 2049 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2050 {
2051 char buf1[40], buf2[40];
2052
2053 sprint_value (buf1, val);
2054 sprint_value (buf2, val & mask);
2055 as_warn (_("%s shortened to %s"), buf1, buf2);
2056 }
2057 return val & mask;
2058}
2059
c32fa91d
L		 2060enum PREFIX_GROUP
2061{
2062 PREFIX_EXIST = 0,
2063 PREFIX_LOCK,
2064 PREFIX_REP,
2065 PREFIX_OTHER
2066};
2067
2068/* Returns
2069 a. PREFIX_EXIST if attempting to add a prefix where one from the
2070 same class already exists.
2071 b. PREFIX_LOCK if lock prefix is added.
2072 c. PREFIX_REP if rep/repne prefix is added.
2073 d. PREFIX_OTHER if other prefix is added.
2074 */
2075
2076static enum PREFIX_GROUP
e3bb37b5 2077add_prefix (unsigned int prefix)
252b5132 2078{
c32fa91d 2079 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2080 unsigned int q;
252b5132 2081
29b0f896
AM		 2082 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2083 && flag_code == CODE_64BIT)
b1905489 2084 {
161a04f6
L		 2085 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2086 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2087 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2088 ret = PREFIX_EXIST;
b1905489
JB		 2089 q = REX_PREFIX;
2090 }
3e73aa7c 2091 else
b1905489
JB		 2092 {
2093 switch (prefix)
2094 {
2095 default:
2096 abort ();
2097
2098 case CS_PREFIX_OPCODE:
2099 case DS_PREFIX_OPCODE:
2100 case ES_PREFIX_OPCODE:
2101 case FS_PREFIX_OPCODE:
2102 case GS_PREFIX_OPCODE:
2103 case SS_PREFIX_OPCODE:
2104 q = SEG_PREFIX;
2105 break;
2106
2107 case REPNE_PREFIX_OPCODE:
2108 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2109 q = REP_PREFIX;
2110 ret = PREFIX_REP;
2111 break;
2112
b1905489 2113 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2114 q = LOCK_PREFIX;
2115 ret = PREFIX_LOCK;
b1905489
JB		 2116 break;
2117
2118 case FWAIT_OPCODE:
2119 q = WAIT_PREFIX;
2120 break;
2121
2122 case ADDR_PREFIX_OPCODE:
2123 q = ADDR_PREFIX;
2124 break;
2125
2126 case DATA_PREFIX_OPCODE:
2127 q = DATA_PREFIX;
2128 break;
2129 }
2130 if (i.prefix[q] != 0)
c32fa91d 2131 ret = PREFIX_EXIST;
b1905489 2132 }
252b5132 2133
b1905489 2134 if (ret)
252b5132 2135 {
b1905489
JB		 2136 if (!i.prefix[q])
2137 ++i.prefixes;
2138 i.prefix[q] |= prefix;
252b5132 2139 }
b1905489
JB		 2140 else
2141 as_bad (_("same type of prefix used twice"));
252b5132 2142
252b5132
RH		 2143 return ret;
2144}
2145
2146static void
78f12dd3 2147update_code_flag (int value, int check)
eecb386c 2148{
78f12dd3
L		 2149 PRINTF_LIKE ((*as_error));
2150
1e9cc1c2 2151 flag_code = (enum flag_code) value;
40fb9820
L		 2152 if (flag_code == CODE_64BIT)
2153 {
2154 cpu_arch_flags.bitfield.cpu64 = 1;
2155 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2156 }
2157 else
2158 {
2159 cpu_arch_flags.bitfield.cpu64 = 0;
2160 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2161 }
2162 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2163 {
78f12dd3
L		 2164 if (check)
2165 as_error = as_fatal;
2166 else
2167 as_error = as_bad;
2168 (*as_error) (_("64bit mode not supported on `%s'."),
2169 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2170 }
40fb9820 2171 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2172 {
78f12dd3
L		 2173 if (check)
2174 as_error = as_fatal;
2175 else
2176 as_error = as_bad;
2177 (*as_error) (_("32bit mode not supported on `%s'."),
2178 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2179 }
eecb386c
AM		 2180 stackop_size = '\0';
2181}
2182
78f12dd3
L		 2183static void
2184set_code_flag (int value)
2185{
2186 update_code_flag (value, 0);
2187}
2188
eecb386c 2189static void
e3bb37b5 2190set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2191{
1e9cc1c2 2192 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2193 if (flag_code != CODE_16BIT)
2194 abort ();
2195 cpu_arch_flags.bitfield.cpu64 = 0;
2196 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2197 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2198}
2199
2200static void
e3bb37b5 2201set_intel_syntax (int syntax_flag)
252b5132
RH		 2202{
2203 /* Find out if register prefixing is specified. */
2204 int ask_naked_reg = 0;
2205
2206 SKIP_WHITESPACE ();
29b0f896 2207 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2208 {
d02603dc
NC		 2209 char *string;
2210 int e = get_symbol_name (&string);
252b5132 2211
47926f60 2212 if (strcmp (string, "prefix") == 0)
252b5132 2213 ask_naked_reg = 1;
47926f60 2214 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2215 ask_naked_reg = -1;
2216 else
d0b47220 2217 as_bad (_("bad argument to syntax directive."));
d02603dc 2218 (void) restore_line_pointer (e);
252b5132
RH		 2219 }
2220 demand_empty_rest_of_line ();
c3332e24 2221
252b5132
RH		 2222 intel_syntax = syntax_flag;
2223
2224 if (ask_naked_reg == 0)
f86103b7
AM		 2225 allow_naked_reg = (intel_syntax
2226 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2227 else
2228 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2229
ee86248c 2230 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2231
e4a3b5a4 2232 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2233 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2234 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2235}
2236
1efbbeb4
L		 2237static void
2238set_intel_mnemonic (int mnemonic_flag)
2239{
e1d4d893 2240 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2241}
2242
db51cc60
L		 2243static void
2244set_allow_index_reg (int flag)
2245{
2246 allow_index_reg = flag;
2247}
2248
cb19c032 2249static void
7bab8ab5 2250set_check (int what)
cb19c032 2251{
7bab8ab5
JB		 2252 enum check_kind *kind;
2253 const char *str;
2254
2255 if (what)
2256 {
2257 kind = &operand_check;
2258 str = "operand";
2259 }
2260 else
2261 {
2262 kind = &sse_check;
2263 str = "sse";
2264 }
2265
cb19c032
L		 2266 SKIP_WHITESPACE ();
2267
2268 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2269 {
d02603dc
NC		 2270 char *string;
2271 int e = get_symbol_name (&string);
cb19c032
L		 2272
2273 if (strcmp (string, "none") == 0)
7bab8ab5 2274 *kind = check_none;
cb19c032 2275 else if (strcmp (string, "warning") == 0)
7bab8ab5 2276 *kind = check_warning;
cb19c032 2277 else if (strcmp (string, "error") == 0)
7bab8ab5 2278 *kind = check_error;
cb19c032 2279 else
7bab8ab5 2280 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2281 (void) restore_line_pointer (e);
cb19c032
L		 2282 }
2283 else
7bab8ab5 2284 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2285
2286 demand_empty_rest_of_line ();
2287}
2288
8a9036a4
L		 2289static void
2290check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2291 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2292{
2293#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2294 static const char *arch;
2295
2296 /* Intel LIOM is only supported on ELF. */
2297 if (!IS_ELF)
2298 return;
2299
2300 if (!arch)
2301 {
2302 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2303 use default_arch. */
2304 arch = cpu_arch_name;
2305 if (!arch)
2306 arch = default_arch;
2307 }
2308
81486035
L		 2309 /* If we are targeting Intel MCU, we must enable it. */
2310 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2311 || new_flag.bitfield.cpuiamcu)
2312 return;
2313
3632d14b 2314 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2315 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2316 || new_flag.bitfield.cpul1om)
8a9036a4 2317 return;
76ba9986 2318
7a9068fe
L		 2319 /* If we are targeting Intel K1OM, we must enable it. */
2320 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2321 || new_flag.bitfield.cpuk1om)
2322 return;
2323
8a9036a4
L		 2324 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2325#endif
2326}
2327
e413e4e9 2328static void
e3bb37b5 2329set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2330{
47926f60 2331 SKIP_WHITESPACE ();
e413e4e9 2332
29b0f896 2333 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2334 {
d02603dc
NC		 2335 char *string;
2336 int e = get_symbol_name (&string);
91d6fa6a 2337 unsigned int j;
40fb9820 2338 i386_cpu_flags flags;
e413e4e9 2339
91d6fa6a 2340 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2341 {
91d6fa6a 2342 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2343 {
91d6fa6a 2344 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2345
5c6af06e
JB		 2346 if (*string != '.')
2347 {
91d6fa6a 2348 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2349 cpu_sub_arch_name = NULL;
91d6fa6a 2350 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2351 if (flag_code == CODE_64BIT)
2352 {
2353 cpu_arch_flags.bitfield.cpu64 = 1;
2354 cpu_arch_flags.bitfield.cpuno64 = 0;
2355 }
2356 else
2357 {
2358 cpu_arch_flags.bitfield.cpu64 = 0;
2359 cpu_arch_flags.bitfield.cpuno64 = 1;
2360 }
91d6fa6a
NC		 2361 cpu_arch_isa = cpu_arch[j].type;
2362 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2363 if (!cpu_arch_tune_set)
2364 {
2365 cpu_arch_tune = cpu_arch_isa;
2366 cpu_arch_tune_flags = cpu_arch_isa_flags;
2367 }
5c6af06e
JB		 2368 break;
2369 }
40fb9820 2370
22109423 2371 if (!cpu_arch[j].negated)
309d3373 2372 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2373 cpu_arch[j].flags);
309d3373
JB		 2374 else
2375 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2376 cpu_arch[j].flags);
81486035
L		 2377
2378 if (!valid_iamcu_cpu_flags (&flags))
2379 as_fatal (_("`%s' isn't valid for Intel MCU"),
2380 cpu_arch[j].name);
2381 else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2382 {
6305a203
L		 2383 if (cpu_sub_arch_name)
2384 {
2385 char *name = cpu_sub_arch_name;
2386 cpu_sub_arch_name = concat (name,
91d6fa6a 2387 cpu_arch[j].name,
1bf57e9f 2388 (const char *) NULL);
6305a203
L		 2389 free (name);
2390 }
2391 else
91d6fa6a 2392 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2393 cpu_arch_flags = flags;
a586129e 2394 cpu_arch_isa_flags = flags;
5c6af06e 2395 }
d02603dc 2396 (void) restore_line_pointer (e);
5c6af06e
JB		 2397 demand_empty_rest_of_line ();
2398 return;
e413e4e9
AM		 2399 }
2400 }
91d6fa6a 2401 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2402 as_bad (_("no such architecture: `%s'"), string);
2403
2404 *input_line_pointer = e;
2405 }
2406 else
2407 as_bad (_("missing cpu architecture"));
2408
fddf5b5b
AM		 2409 no_cond_jump_promotion = 0;
2410 if (*input_line_pointer == ','
29b0f896 2411 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2412 {
d02603dc
NC		 2413 char *string;
2414 char e;
2415
2416 ++input_line_pointer;
2417 e = get_symbol_name (&string);
fddf5b5b
AM		 2418
2419 if (strcmp (string, "nojumps") == 0)
2420 no_cond_jump_promotion = 1;
2421 else if (strcmp (string, "jumps") == 0)
2422 ;
2423 else
2424 as_bad (_("no such architecture modifier: `%s'"), string);
2425
d02603dc 2426 (void) restore_line_pointer (e);
fddf5b5b
AM		 2427 }
2428
e413e4e9
AM		 2429 demand_empty_rest_of_line ();
2430}
2431
8a9036a4
L		 2432enum bfd_architecture
2433i386_arch (void)
2434{
3632d14b 2435 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2436 {
2437 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2438 || flag_code != CODE_64BIT)
2439 as_fatal (_("Intel L1OM is 64bit ELF only"));
2440 return bfd_arch_l1om;
2441 }
7a9068fe
L		 2442 else if (cpu_arch_isa == PROCESSOR_K1OM)
2443 {
2444 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2445 || flag_code != CODE_64BIT)
2446 as_fatal (_("Intel K1OM is 64bit ELF only"));
2447 return bfd_arch_k1om;
2448 }
81486035
L		 2449 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2450 {
2451 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2452 || flag_code == CODE_64BIT)
2453 as_fatal (_("Intel MCU is 32bit ELF only"));
2454 return bfd_arch_iamcu;
2455 }
8a9036a4
L		 2456 else
2457 return bfd_arch_i386;
2458}
2459
b9d79e03 2460unsigned long
7016a5d5 2461i386_mach (void)
b9d79e03 2462{
351f65ca 2463 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2464 {
3632d14b 2465 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2466 {
351f65ca
L		 2467 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2468 || default_arch[6] != '\0')
8a9036a4
L		 2469 as_fatal (_("Intel L1OM is 64bit ELF only"));
2470 return bfd_mach_l1om;
2471 }
7a9068fe
L		 2472 else if (cpu_arch_isa == PROCESSOR_K1OM)
2473 {
2474 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2475 || default_arch[6] != '\0')
2476 as_fatal (_("Intel K1OM is 64bit ELF only"));
2477 return bfd_mach_k1om;
2478 }
351f65ca 2479 else if (default_arch[6] == '\0')
8a9036a4 2480 return bfd_mach_x86_64;
351f65ca
L		 2481 else
2482 return bfd_mach_x64_32;
8a9036a4 2483 }
5197d474
L		 2484 else if (!strcmp (default_arch, "i386")
2485 || !strcmp (default_arch, "iamcu"))
81486035
L		 2486 {
2487 if (cpu_arch_isa == PROCESSOR_IAMCU)
2488 {
2489 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2490 as_fatal (_("Intel MCU is 32bit ELF only"));
2491 return bfd_mach_i386_iamcu;
2492 }
2493 else
2494 return bfd_mach_i386_i386;
2495 }
b9d79e03 2496 else
2b5d6a91 2497 as_fatal (_("unknown architecture"));
b9d79e03 2498}
b9d79e03 2499\f
252b5132 2500void
7016a5d5 2501md_begin (void)
252b5132
RH		 2502{
2503 const char *hash_err;
2504
47926f60 2505 /* Initialize op_hash hash table. */
252b5132
RH		 2506 op_hash = hash_new ();
2507
2508 {
d3ce72d0 2509 const insn_template *optab;
29b0f896 2510 templates *core_optab;
252b5132 2511
47926f60
KH		 2512 /* Setup for loop. */
2513 optab = i386_optab;
252b5132
RH		 2514 core_optab = (templates *) xmalloc (sizeof (templates));
2515 core_optab->start = optab;
2516
2517 while (1)
2518 {
2519 ++optab;
2520 if (optab->name == NULL
2521 || strcmp (optab->name, (optab - 1)->name) != 0)
2522 {
2523 /* different name --> ship out current template list;
47926f60 2524 add to hash table; & begin anew. */
252b5132
RH		 2525 core_optab->end = optab;
2526 hash_err = hash_insert (op_hash,
2527 (optab - 1)->name,
5a49b8ac 2528 (void *) core_optab);
252b5132
RH		 2529 if (hash_err)
2530 {
b37df7c4 2531 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2532 (optab - 1)->name,
2533 hash_err);
2534 }
2535 if (optab->name == NULL)
2536 break;
2537 core_optab = (templates *) xmalloc (sizeof (templates));
2538 core_optab->start = optab;
2539 }
2540 }
2541 }
2542
47926f60 2543 /* Initialize reg_hash hash table. */
252b5132
RH		 2544 reg_hash = hash_new ();
2545 {
29b0f896 2546 const reg_entry *regtab;
c3fe08fa 2547 unsigned int regtab_size = i386_regtab_size;
252b5132 2548
c3fe08fa 2549 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2550 {
5a49b8ac 2551 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2552 if (hash_err)
b37df7c4 2553 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2554 regtab->reg_name,
2555 hash_err);
252b5132
RH		 2556 }
2557 }
2558
47926f60 2559 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2560 {
29b0f896
AM		 2561 int c;
2562 char *p;
252b5132
RH		 2563
2564 for (c = 0; c < 256; c++)
2565 {
3882b010 2566 if (ISDIGIT (c))
252b5132
RH		 2567 {
2568 digit_chars[c] = c;
2569 mnemonic_chars[c] = c;
2570 register_chars[c] = c;
2571 operand_chars[c] = c;
2572 }
3882b010 2573 else if (ISLOWER (c))
252b5132
RH		 2574 {
2575 mnemonic_chars[c] = c;
2576 register_chars[c] = c;
2577 operand_chars[c] = c;
2578 }
3882b010 2579 else if (ISUPPER (c))
252b5132 2580 {
3882b010 2581 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2582 register_chars[c] = mnemonic_chars[c];
2583 operand_chars[c] = c;
2584 }
43234a1e
L		 2585 else if (c == '{' || c == '}')
2586 operand_chars[c] = c;
252b5132 2587
3882b010 2588 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2589 identifier_chars[c] = c;
2590 else if (c >= 128)
2591 {
2592 identifier_chars[c] = c;
2593 operand_chars[c] = c;
2594 }
2595 }
2596
2597#ifdef LEX_AT
2598 identifier_chars['@'] = '@';
32137342
NC		 2599#endif
2600#ifdef LEX_QM
2601 identifier_chars['?'] = '?';
2602 operand_chars['?'] = '?';
252b5132 2603#endif
252b5132 2604 digit_chars['-'] = '-';
c0f3af97 2605 mnemonic_chars['_'] = '_';
791fe849 2606 mnemonic_chars['-'] = '-';
0003779b 2607 mnemonic_chars['.'] = '.';
252b5132
RH		 2608 identifier_chars['_'] = '_';
2609 identifier_chars['.'] = '.';
2610
2611 for (p = operand_special_chars; *p != '\0'; p++)
2612 operand_chars[(unsigned char) *p] = *p;
2613 }
2614
a4447b93
RH		 2615 if (flag_code == CODE_64BIT)
2616 {
ca19b261
KT		 2617#if defined (OBJ_COFF) && defined (TE_PE)
2618 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2619 ? 32 : 16);
2620#else
a4447b93 2621 x86_dwarf2_return_column = 16;
ca19b261 2622#endif
61ff971f 2623 x86_cie_data_alignment = -8;
a4447b93
RH		 2624 }
2625 else
2626 {
2627 x86_dwarf2_return_column = 8;
2628 x86_cie_data_alignment = -4;
2629 }
252b5132
RH		 2630}
2631
2632void
e3bb37b5 2633i386_print_statistics (FILE *file)
252b5132
RH		 2634{
2635 hash_print_statistics (file, "i386 opcode", op_hash);
2636 hash_print_statistics (file, "i386 register", reg_hash);
2637}
2638\f
252b5132
RH		 2639#ifdef DEBUG386
2640
ce8a8b2f 2641/* Debugging routines for md_assemble. */
d3ce72d0 2642static void pte (insn_template *);
40fb9820 2643static void pt (i386_operand_type);
e3bb37b5
L		 2644static void pe (expressionS *);
2645static void ps (symbolS *);
252b5132
RH		 2646
2647static void
e3bb37b5 2648pi (char *line, i386_insn *x)
252b5132 2649{
09137c09 2650 unsigned int j;
252b5132
RH		 2651
2652 fprintf (stdout, "%s: template ", line);
2653 pte (&x->tm);
09f131f2
JH		 2654 fprintf (stdout, " address: base %s index %s scale %x\n",
2655 x->base_reg ? x->base_reg->reg_name : "none",
2656 x->index_reg ? x->index_reg->reg_name : "none",
2657 x->log2_scale_factor);
2658 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2659 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2660 fprintf (stdout, " sib: base %x index %x scale %x\n",
2661 x->sib.base, x->sib.index, x->sib.scale);
2662 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2663 (x->rex & REX_W) != 0,
2664 (x->rex & REX_R) != 0,
2665 (x->rex & REX_X) != 0,
2666 (x->rex & REX_B) != 0);
09137c09 2667 for (j = 0; j < x->operands; j++)
252b5132 2668 {
09137c09
SP		 2669 fprintf (stdout, " #%d: ", j + 1);
2670 pt (x->types[j]);
252b5132 2671 fprintf (stdout, "\n");
09137c09
SP		 2672 if (x->types[j].bitfield.reg8
2673 || x->types[j].bitfield.reg16
2674 || x->types[j].bitfield.reg32
2675 || x->types[j].bitfield.reg64
2676 || x->types[j].bitfield.regmmx
2677 || x->types[j].bitfield.regxmm
2678 || x->types[j].bitfield.regymm
43234a1e 2679 || x->types[j].bitfield.regzmm
09137c09
SP		 2680 || x->types[j].bitfield.sreg2
2681 || x->types[j].bitfield.sreg3
2682 || x->types[j].bitfield.control
2683 || x->types[j].bitfield.debug
2684 || x->types[j].bitfield.test)
2685 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2686 if (operand_type_check (x->types[j], imm))
2687 pe (x->op[j].imms);
2688 if (operand_type_check (x->types[j], disp))
2689 pe (x->op[j].disps);
252b5132
RH		 2690 }
2691}
2692
2693static void
d3ce72d0 2694pte (insn_template *t)
252b5132 2695{
09137c09 2696 unsigned int j;
252b5132 2697 fprintf (stdout, " %d operands ", t->operands);
47926f60 2698 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2699 if (t->extension_opcode != None)
2700 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2701 if (t->opcode_modifier.d)
252b5132 2702 fprintf (stdout, "D");
40fb9820 2703 if (t->opcode_modifier.w)
252b5132
RH		 2704 fprintf (stdout, "W");
2705 fprintf (stdout, "\n");
09137c09 2706 for (j = 0; j < t->operands; j++)
252b5132 2707 {
09137c09
SP		 2708 fprintf (stdout, " #%d type ", j + 1);
2709 pt (t->operand_types[j]);
252b5132
RH		 2710 fprintf (stdout, "\n");
2711 }
2712}
2713
2714static void
e3bb37b5 2715pe (expressionS *e)
252b5132 2716{
24eab124 2717 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2718 fprintf (stdout, " add_number %ld (%lx)\n",
2719 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2720 if (e->X_add_symbol)
2721 {
2722 fprintf (stdout, " add_symbol ");
2723 ps (e->X_add_symbol);
2724 fprintf (stdout, "\n");
2725 }
2726 if (e->X_op_symbol)
2727 {
2728 fprintf (stdout, " op_symbol ");
2729 ps (e->X_op_symbol);
2730 fprintf (stdout, "\n");
2731 }
2732}
2733
2734static void
e3bb37b5 2735ps (symbolS *s)
252b5132
RH		 2736{
2737 fprintf (stdout, "%s type %s%s",
2738 S_GET_NAME (s),
2739 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2740 segment_name (S_GET_SEGMENT (s)));
2741}
2742
7b81dfbb 2743static struct type_name
252b5132 2744 {
40fb9820
L		 2745 i386_operand_type mask;
2746 const char *name;
252b5132 2747 }
7b81dfbb 2748const type_names[] =
252b5132 2749{
40fb9820
L		 2750 { OPERAND_TYPE_REG8, "r8" },
2751 { OPERAND_TYPE_REG16, "r16" },
2752 { OPERAND_TYPE_REG32, "r32" },
2753 { OPERAND_TYPE_REG64, "r64" },
2754 { OPERAND_TYPE_IMM8, "i8" },
2755 { OPERAND_TYPE_IMM8, "i8s" },
2756 { OPERAND_TYPE_IMM16, "i16" },
2757 { OPERAND_TYPE_IMM32, "i32" },
2758 { OPERAND_TYPE_IMM32S, "i32s" },
2759 { OPERAND_TYPE_IMM64, "i64" },
2760 { OPERAND_TYPE_IMM1, "i1" },
2761 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2762 { OPERAND_TYPE_DISP8, "d8" },
2763 { OPERAND_TYPE_DISP16, "d16" },
2764 { OPERAND_TYPE_DISP32, "d32" },
2765 { OPERAND_TYPE_DISP32S, "d32s" },
2766 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2767 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2768 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2769 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2770 { OPERAND_TYPE_CONTROL, "control reg" },
2771 { OPERAND_TYPE_TEST, "test reg" },
2772 { OPERAND_TYPE_DEBUG, "debug reg" },
2773 { OPERAND_TYPE_FLOATREG, "FReg" },
2774 { OPERAND_TYPE_FLOATACC, "FAcc" },
2775 { OPERAND_TYPE_SREG2, "SReg2" },
2776 { OPERAND_TYPE_SREG3, "SReg3" },
2777 { OPERAND_TYPE_ACC, "Acc" },
2778 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2779 { OPERAND_TYPE_REGMMX, "rMMX" },
2780 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2781 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2782 { OPERAND_TYPE_REGZMM, "rZMM" },
2783 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2784 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2785};
2786
2787static void
40fb9820 2788pt (i386_operand_type t)
252b5132 2789{
40fb9820 2790 unsigned int j;
c6fb90c8 2791 i386_operand_type a;
252b5132 2792
40fb9820 2793 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2794 {
2795 a = operand_type_and (t, type_names[j].mask);
0349dc08 2796 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2797 fprintf (stdout, "%s, ", type_names[j].name);
2798 }
252b5132
RH		 2799 fflush (stdout);
2800}
2801
2802#endif /* DEBUG386 */
2803\f
252b5132 2804static bfd_reloc_code_real_type
3956db08 2805reloc (unsigned int size,
64e74474
AM		 2806 int pcrel,
2807 int sign,
2808 bfd_reloc_code_real_type other)
252b5132 2809{
47926f60 2810 if (other != NO_RELOC)
3956db08 2811 {
91d6fa6a 2812 reloc_howto_type *rel;
3956db08
JB		 2813
2814 if (size == 8)
2815 switch (other)
2816 {
64e74474
AM		 2817 case BFD_RELOC_X86_64_GOT32:
2818 return BFD_RELOC_X86_64_GOT64;
2819 break;
553d1284
L		 2820 case BFD_RELOC_X86_64_GOTPLT64:
2821 return BFD_RELOC_X86_64_GOTPLT64;
2822 break;
64e74474
AM		 2823 case BFD_RELOC_X86_64_PLTOFF64:
2824 return BFD_RELOC_X86_64_PLTOFF64;
2825 break;
2826 case BFD_RELOC_X86_64_GOTPC32:
2827 other = BFD_RELOC_X86_64_GOTPC64;
2828 break;
2829 case BFD_RELOC_X86_64_GOTPCREL:
2830 other = BFD_RELOC_X86_64_GOTPCREL64;
2831 break;
2832 case BFD_RELOC_X86_64_TPOFF32:
2833 other = BFD_RELOC_X86_64_TPOFF64;
2834 break;
2835 case BFD_RELOC_X86_64_DTPOFF32:
2836 other = BFD_RELOC_X86_64_DTPOFF64;
2837 break;
2838 default:
2839 break;
3956db08 2840 }
e05278af 2841
8ce3d284 2842#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2843 if (other == BFD_RELOC_SIZE32)
2844 {
2845 if (size == 8)
1ab668bf 2846 other = BFD_RELOC_SIZE64;
8fd4256d 2847 if (pcrel)
1ab668bf
AM		 2848 {
2849 as_bad (_("there are no pc-relative size relocations"));
2850 return NO_RELOC;
2851 }
8fd4256d 2852 }
8ce3d284 2853#endif
8fd4256d 2854
e05278af 2855 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2856 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2857 sign = -1;
2858
91d6fa6a
NC		 2859 rel = bfd_reloc_type_lookup (stdoutput, other);
2860 if (!rel)
3956db08 2861 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2862 else if (size != bfd_get_reloc_size (rel))
3956db08 2863 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2864 bfd_get_reloc_size (rel),
3956db08 2865 size);
91d6fa6a 2866 else if (pcrel && !rel->pc_relative)
3956db08 2867 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2868 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2869 && !sign)
91d6fa6a 2870 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2871 && sign > 0))
3956db08
JB		 2872 as_bad (_("relocated field and relocation type differ in signedness"));
2873 else
2874 return other;
2875 return NO_RELOC;
2876 }
252b5132
RH		 2877
2878 if (pcrel)
2879 {
3e73aa7c 2880 if (!sign)
3956db08 2881 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2882 switch (size)
2883 {
2884 case 1: return BFD_RELOC_8_PCREL;
2885 case 2: return BFD_RELOC_16_PCREL;
d258b828 2886 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2887 case 8: return BFD_RELOC_64_PCREL;
252b5132 2888 }
3956db08 2889 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2890 }
2891 else
2892 {
3956db08 2893 if (sign > 0)
e5cb08ac 2894 switch (size)
3e73aa7c
JH		 2895 {
2896 case 4: return BFD_RELOC_X86_64_32S;
2897 }
2898 else
2899 switch (size)
2900 {
2901 case 1: return BFD_RELOC_8;
2902 case 2: return BFD_RELOC_16;
2903 case 4: return BFD_RELOC_32;
2904 case 8: return BFD_RELOC_64;
2905 }
3956db08
JB		 2906 as_bad (_("cannot do %s %u byte relocation"),
2907 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2908 }
2909
0cc9e1d3 2910 return NO_RELOC;
252b5132
RH		 2911}
2912
47926f60
KH		 2913/* Here we decide which fixups can be adjusted to make them relative to
2914 the beginning of the section instead of the symbol. Basically we need
2915 to make sure that the dynamic relocations are done correctly, so in
2916 some cases we force the original symbol to be used. */
2917
252b5132 2918int
e3bb37b5 2919tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2920{
6d249963 2921#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2922 if (!IS_ELF)
31312f95
AM		 2923 return 1;
2924
a161fe53
AM		 2925 /* Don't adjust pc-relative references to merge sections in 64-bit
2926 mode. */
2927 if (use_rela_relocations
2928 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2929 && fixP->fx_pcrel)
252b5132 2930 return 0;
31312f95 2931
8d01d9a9
AJ		 2932 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2933 and changed later by validate_fix. */
2934 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2935 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2936 return 0;
2937
8fd4256d
L		 2938 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2939 for size relocations. */
2940 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2941 || fixP->fx_r_type == BFD_RELOC_SIZE64
2942 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2943 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2944 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 2945 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 2946 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2947 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2948 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2949 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2950 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2951 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2952 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2953 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2954 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2955 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2956 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2957 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2958 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 2959 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
2960 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 2961 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2962 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2963 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2964 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2965 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2966 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2967 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2968 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2969 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2970 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2971 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2972 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2973 return 0;
31312f95 2974#endif
252b5132
RH		 2975 return 1;
2976}
252b5132 2977
b4cac588 2978static int
e3bb37b5 2979intel_float_operand (const char *mnemonic)
252b5132 2980{
9306ca4a
JB		 2981 /* Note that the value returned is meaningful only for opcodes with (memory)
2982 operands, hence the code here is free to improperly handle opcodes that
2983 have no operands (for better performance and smaller code). */
2984
2985 if (mnemonic[0] != 'f')
2986 return 0; /* non-math */
2987
2988 switch (mnemonic[1])
2989 {
2990 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2991 the fs segment override prefix not currently handled because no
2992 call path can make opcodes without operands get here */
2993 case 'i':
2994 return 2 /* integer op */;
2995 case 'l':
2996 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2997 return 3; /* fldcw/fldenv */
2998 break;
2999 case 'n':
3000 if (mnemonic[2] != 'o' /* fnop */)
3001 return 3; /* non-waiting control op */
3002 break;
3003 case 'r':
3004 if (mnemonic[2] == 's')
3005 return 3; /* frstor/frstpm */
3006 break;
3007 case 's':
3008 if (mnemonic[2] == 'a')
3009 return 3; /* fsave */
3010 if (mnemonic[2] == 't')
3011 {
3012 switch (mnemonic[3])
3013 {
3014 case 'c': /* fstcw */
3015 case 'd': /* fstdw */
3016 case 'e': /* fstenv */
3017 case 's': /* fsts[gw] */
3018 return 3;
3019 }
3020 }
3021 break;
3022 case 'x':
3023 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3024 return 0; /* fxsave/fxrstor are not really math ops */
3025 break;
3026 }
252b5132 3027
9306ca4a 3028 return 1;
252b5132
RH		 3029}
3030
c0f3af97
L		 3031/* Build the VEX prefix. */
3032
3033static void
d3ce72d0 3034build_vex_prefix (const insn_template *t)
c0f3af97
L		 3035{
3036 unsigned int register_specifier;
3037 unsigned int implied_prefix;
3038 unsigned int vector_length;
3039
3040 /* Check register specifier. */
3041 if (i.vex.register_specifier)
43234a1e
L		 3042 {
3043 register_specifier =
3044 ~register_number (i.vex.register_specifier) & 0xf;
3045 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3046 }
c0f3af97
L		 3047 else
3048 register_specifier = 0xf;
3049
fa99fab2
L		 3050 /* Use 2-byte VEX prefix by swappping destination and source
3051 operand. */
3052 if (!i.swap_operand
3053 && i.operands == i.reg_operands
7f399153 3054 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3055 && i.tm.opcode_modifier.s
3056 && i.rex == REX_B)
3057 {
3058 unsigned int xchg = i.operands - 1;
3059 union i386_op temp_op;
3060 i386_operand_type temp_type;
3061
3062 temp_type = i.types[xchg];
3063 i.types[xchg] = i.types[0];
3064 i.types[0] = temp_type;
3065 temp_op = i.op[xchg];
3066 i.op[xchg] = i.op[0];
3067 i.op[0] = temp_op;
3068
9c2799c2 3069 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3070
3071 i.rex = REX_R;
3072 xchg = i.rm.regmem;
3073 i.rm.regmem = i.rm.reg;
3074 i.rm.reg = xchg;
3075
3076 /* Use the next insn. */
3077 i.tm = t[1];
3078 }
3079
539f890d
L		 3080 if (i.tm.opcode_modifier.vex == VEXScalar)
3081 vector_length = avxscalar;
3082 else
3083 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3084
3085 switch ((i.tm.base_opcode >> 8) & 0xff)
3086 {
3087 case 0:
3088 implied_prefix = 0;
3089 break;
3090 case DATA_PREFIX_OPCODE:
3091 implied_prefix = 1;
3092 break;
3093 case REPE_PREFIX_OPCODE:
3094 implied_prefix = 2;
3095 break;
3096 case REPNE_PREFIX_OPCODE:
3097 implied_prefix = 3;
3098 break;
3099 default:
3100 abort ();
3101 }
3102
3103 /* Use 2-byte VEX prefix if possible. */
7f399153 3104 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3105 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3106 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3107 {
3108 /* 2-byte VEX prefix. */
3109 unsigned int r;
3110
3111 i.vex.length = 2;
3112 i.vex.bytes[0] = 0xc5;
3113
3114 /* Check the REX.R bit. */
3115 r = (i.rex & REX_R) ? 0 : 1;
3116 i.vex.bytes[1] = (r << 7
3117 | register_specifier << 3
3118 | vector_length << 2
3119 | implied_prefix);
3120 }
3121 else
3122 {
3123 /* 3-byte VEX prefix. */
3124 unsigned int m, w;
3125
f88c9eb0 3126 i.vex.length = 3;
f88c9eb0 3127
7f399153 3128 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3129 {
7f399153
L		 3130 case VEX0F:
3131 m = 0x1;
80de6e00 3132 i.vex.bytes[0] = 0xc4;
7f399153
L		 3133 break;
3134 case VEX0F38:
3135 m = 0x2;
80de6e00 3136 i.vex.bytes[0] = 0xc4;
7f399153
L		 3137 break;
3138 case VEX0F3A:
3139 m = 0x3;
80de6e00 3140 i.vex.bytes[0] = 0xc4;
7f399153
L		 3141 break;
3142 case XOP08:
5dd85c99
SP		 3143 m = 0x8;
3144 i.vex.bytes[0] = 0x8f;
7f399153
L		 3145 break;
3146 case XOP09:
f88c9eb0
SP		 3147 m = 0x9;
3148 i.vex.bytes[0] = 0x8f;
7f399153
L		 3149 break;
3150 case XOP0A:
f88c9eb0
SP		 3151 m = 0xa;
3152 i.vex.bytes[0] = 0x8f;
7f399153
L		 3153 break;
3154 default:
3155 abort ();
f88c9eb0 3156 }
c0f3af97 3157
c0f3af97
L		 3158 /* The high 3 bits of the second VEX byte are 1's compliment
3159 of RXB bits from REX. */
3160 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3161
3162 /* Check the REX.W bit. */
3163 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3164 if (i.tm.opcode_modifier.vexw == VEXW1)
3165 w = 1;
c0f3af97
L		 3166
3167 i.vex.bytes[2] = (w << 7
3168 | register_specifier << 3
3169 | vector_length << 2
3170 | implied_prefix);
3171 }
3172}
3173
43234a1e
L		 3174/* Build the EVEX prefix. */
3175
3176static void
3177build_evex_prefix (void)
3178{
3179 unsigned int register_specifier;
3180 unsigned int implied_prefix;
3181 unsigned int m, w;
3182 rex_byte vrex_used = 0;
3183
3184 /* Check register specifier. */
3185 if (i.vex.register_specifier)
3186 {
3187 gas_assert ((i.vrex & REX_X) == 0);
3188
3189 register_specifier = i.vex.register_specifier->reg_num;
3190 if ((i.vex.register_specifier->reg_flags & RegRex))
3191 register_specifier += 8;
3192 /* The upper 16 registers are encoded in the fourth byte of the
3193 EVEX prefix. */
3194 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3195 i.vex.bytes[3] = 0x8;
3196 register_specifier = ~register_specifier & 0xf;
3197 }
3198 else
3199 {
3200 register_specifier = 0xf;
3201
3202 /* Encode upper 16 vector index register in the fourth byte of
3203 the EVEX prefix. */
3204 if (!(i.vrex & REX_X))
3205 i.vex.bytes[3] = 0x8;
3206 else
3207 vrex_used |= REX_X;
3208 }
3209
3210 switch ((i.tm.base_opcode >> 8) & 0xff)
3211 {
3212 case 0:
3213 implied_prefix = 0;
3214 break;
3215 case DATA_PREFIX_OPCODE:
3216 implied_prefix = 1;
3217 break;
3218 case REPE_PREFIX_OPCODE:
3219 implied_prefix = 2;
3220 break;
3221 case REPNE_PREFIX_OPCODE:
3222 implied_prefix = 3;
3223 break;
3224 default:
3225 abort ();
3226 }
3227
3228 /* 4 byte EVEX prefix. */
3229 i.vex.length = 4;
3230 i.vex.bytes[0] = 0x62;
3231
3232 /* mmmm bits. */
3233 switch (i.tm.opcode_modifier.vexopcode)
3234 {
3235 case VEX0F:
3236 m = 1;
3237 break;
3238 case VEX0F38:
3239 m = 2;
3240 break;
3241 case VEX0F3A:
3242 m = 3;
3243 break;
3244 default:
3245 abort ();
3246 break;
3247 }
3248
3249 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3250 bits from REX. */
3251 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3252
3253 /* The fifth bit of the second EVEX byte is 1's compliment of the
3254 REX_R bit in VREX. */
3255 if (!(i.vrex & REX_R))
3256 i.vex.bytes[1] |= 0x10;
3257 else
3258 vrex_used |= REX_R;
3259
3260 if ((i.reg_operands + i.imm_operands) == i.operands)
3261 {
3262 /* When all operands are registers, the REX_X bit in REX is not
3263 used. We reuse it to encode the upper 16 registers, which is
3264 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3265 as 1's compliment. */
3266 if ((i.vrex & REX_B))
3267 {
3268 vrex_used |= REX_B;
3269 i.vex.bytes[1] &= ~0x40;
3270 }
3271 }
3272
3273 /* EVEX instructions shouldn't need the REX prefix. */
3274 i.vrex &= ~vrex_used;
3275 gas_assert (i.vrex == 0);
3276
3277 /* Check the REX.W bit. */
3278 w = (i.rex & REX_W) ? 1 : 0;
3279 if (i.tm.opcode_modifier.vexw)
3280 {
3281 if (i.tm.opcode_modifier.vexw == VEXW1)
3282 w = 1;
3283 }
3284 /* If w is not set it means we are dealing with WIG instruction. */
3285 else if (!w)
3286 {
3287 if (evexwig == evexw1)
3288 w = 1;
3289 }
3290
3291 /* Encode the U bit. */
3292 implied_prefix |= 0x4;
3293
3294 /* The third byte of the EVEX prefix. */
3295 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3296
3297 /* The fourth byte of the EVEX prefix. */
3298 /* The zeroing-masking bit. */
3299 if (i.mask && i.mask->zeroing)
3300 i.vex.bytes[3] |= 0x80;
3301
3302 /* Don't always set the broadcast bit if there is no RC. */
3303 if (!i.rounding)
3304 {
3305 /* Encode the vector length. */
3306 unsigned int vec_length;
3307
3308 switch (i.tm.opcode_modifier.evex)
3309 {
3310 case EVEXLIG: /* LL' is ignored */
3311 vec_length = evexlig << 5;
3312 break;
3313 case EVEX128:
3314 vec_length = 0 << 5;
3315 break;
3316 case EVEX256:
3317 vec_length = 1 << 5;
3318 break;
3319 case EVEX512:
3320 vec_length = 2 << 5;
3321 break;
3322 default:
3323 abort ();
3324 break;
3325 }
3326 i.vex.bytes[3] |= vec_length;
3327 /* Encode the broadcast bit. */
3328 if (i.broadcast)
3329 i.vex.bytes[3] |= 0x10;
3330 }
3331 else
3332 {
3333 if (i.rounding->type != saeonly)
3334 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3335 else
d3d3c6db 3336 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3337 }
3338
3339 if (i.mask && i.mask->mask)
3340 i.vex.bytes[3] |= i.mask->mask->reg_num;
3341}
3342
65da13b5
L		 3343static void
3344process_immext (void)
3345{
3346 expressionS *exp;
3347
4c692bc7
JB		 3348 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3349 && i.operands > 0)
65da13b5 3350 {
4c692bc7
JB		 3351 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3352 with an opcode suffix which is coded in the same place as an
3353 8-bit immediate field would be.
3354 Here we check those operands and remove them afterwards. */
65da13b5
L		 3355 unsigned int x;
3356
3357 for (x = 0; x < i.operands; x++)
4c692bc7 3358 if (register_number (i.op[x].regs) != x)
65da13b5 3359 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3360 register_prefix, i.op[x].regs->reg_name, x + 1,
3361 i.tm.name);
3362
3363 i.operands = 0;
65da13b5
L		 3364 }
3365
9916071f
AP		 3366 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3367 {
3368 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3369 suffix which is coded in the same place as an 8-bit immediate
3370 field would be.
3371 Here we check those operands and remove them afterwards. */
3372 unsigned int x;
3373
3374 if (i.operands != 3)
3375 abort();
3376
3377 for (x = 0; x < 2; x++)
3378 if (register_number (i.op[x].regs) != x)
3379 goto bad_register_operand;
3380
3381 /* Check for third operand for mwaitx/monitorx insn. */
3382 if (register_number (i.op[x].regs)
3383 != (x + (i.tm.extension_opcode == 0xfb)))
3384 {
3385bad_register_operand:
3386 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3387 register_prefix, i.op[x].regs->reg_name, x+1,
3388 i.tm.name);
3389 }
3390
3391 i.operands = 0;
3392 }
3393
c0f3af97 3394 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3395 which is coded in the same place as an 8-bit immediate field
3396 would be. Here we fake an 8-bit immediate operand from the
3397 opcode suffix stored in tm.extension_opcode.
3398
c1e679ec 3399 AVX instructions also use this encoding, for some of
c0f3af97 3400 3 argument instructions. */
65da13b5 3401
43234a1e 3402 gas_assert (i.imm_operands <= 1
7ab9ffdd 3403 && (i.operands <= 2
43234a1e
L		 3404 || ((i.tm.opcode_modifier.vex
3405 || i.tm.opcode_modifier.evex)
7ab9ffdd 3406 && i.operands <= 4)));
65da13b5
L		 3407
3408 exp = &im_expressions[i.imm_operands++];
3409 i.op[i.operands].imms = exp;
3410 i.types[i.operands] = imm8;
3411 i.operands++;
3412 exp->X_op = O_constant;
3413 exp->X_add_number = i.tm.extension_opcode;
3414 i.tm.extension_opcode = None;
3415}
3416
42164a71
L		 3417
3418static int
3419check_hle (void)
3420{
3421 switch (i.tm.opcode_modifier.hleprefixok)
3422 {
3423 default:
3424 abort ();
82c2def5 3425 case HLEPrefixNone:
165de32a
L		 3426 as_bad (_("invalid instruction `%s' after `%s'"),
3427 i.tm.name, i.hle_prefix);
42164a71 3428 return 0;
82c2def5 3429 case HLEPrefixLock:
42164a71
L		 3430 if (i.prefix[LOCK_PREFIX])
3431 return 1;
165de32a 3432 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3433 return 0;
82c2def5 3434 case HLEPrefixAny:
42164a71 3435 return 1;
82c2def5 3436 case HLEPrefixRelease:
42164a71
L		 3437 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3438 {
3439 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3440 i.tm.name);
3441 return 0;
3442 }
3443 if (i.mem_operands == 0
3444 || !operand_type_check (i.types[i.operands - 1], anymem))
3445 {
3446 as_bad (_("memory destination needed for instruction `%s'"
3447 " after `xrelease'"), i.tm.name);
3448 return 0;
3449 }
3450 return 1;
3451 }
3452}
3453
252b5132
RH		 3454/* This is the guts of the machine-dependent assembler. LINE points to a
3455 machine dependent instruction. This function is supposed to emit
3456 the frags/bytes it assembles to. */
3457
3458void
65da13b5 3459md_assemble (char *line)
252b5132 3460{
40fb9820 3461 unsigned int j;
252b5132 3462 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3463 const insn_template *t;
252b5132 3464
47926f60 3465 /* Initialize globals. */
252b5132
RH		 3466 memset (&i, '\0', sizeof (i));
3467 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3468 i.reloc[j] = NO_RELOC;
252b5132
RH		 3469 memset (disp_expressions, '\0', sizeof (disp_expressions));
3470 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3471 save_stack_p = save_stack;
252b5132
RH		 3472
3473 /* First parse an instruction mnemonic & call i386_operand for the operands.
3474 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3475 start of a (possibly prefixed) mnemonic. */
252b5132 3476
29b0f896
AM		 3477 line = parse_insn (line, mnemonic);
3478 if (line == NULL)
3479 return;
252b5132 3480
29b0f896 3481 line = parse_operands (line, mnemonic);
ee86248c 3482 this_operand = -1;
29b0f896
AM		 3483 if (line == NULL)
3484 return;
252b5132 3485
29b0f896
AM		 3486 /* Now we've parsed the mnemonic into a set of templates, and have the
3487 operands at hand. */
3488
3489 /* All intel opcodes have reversed operands except for "bound" and
3490 "enter". We also don't reverse intersegment "jmp" and "call"
3491 instructions with 2 immediate operands so that the immediate segment
050dfa73 3492 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3493 if (intel_syntax
3494 && i.operands > 1
29b0f896 3495 && (strcmp (mnemonic, "bound") != 0)
30123838 3496 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3497 && !(operand_type_check (i.types[0], imm)
3498 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3499 swap_operands ();
3500
ec56d5c0
JB		 3501 /* The order of the immediates should be reversed
3502 for 2 immediates extrq and insertq instructions */
3503 if (i.imm_operands == 2
3504 && (strcmp (mnemonic, "extrq") == 0
3505 || strcmp (mnemonic, "insertq") == 0))
3506 swap_2_operands (0, 1);
3507
29b0f896
AM		 3508 if (i.imm_operands)
3509 optimize_imm ();
3510
b300c311
L		 3511 /* Don't optimize displacement for movabs since it only takes 64bit
3512 displacement. */
3513 if (i.disp_operands
a501d77e 3514 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3515 && (flag_code != CODE_64BIT
3516 || strcmp (mnemonic, "movabs") != 0))
3517 optimize_disp ();
29b0f896
AM		 3518
3519 /* Next, we find a template that matches the given insn,
3520 making sure the overlap of the given operands types is consistent
3521 with the template operand types. */
252b5132 3522
fa99fab2 3523 if (!(t = match_template ()))
29b0f896 3524 return;
252b5132 3525
7bab8ab5 3526 if (sse_check != check_none
81f8a913 3527 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3528 && (i.tm.cpu_flags.bitfield.cpusse
3529 || i.tm.cpu_flags.bitfield.cpusse2
3530 || i.tm.cpu_flags.bitfield.cpusse3
3531 || i.tm.cpu_flags.bitfield.cpussse3
3532 || i.tm.cpu_flags.bitfield.cpusse4_1
3533 || i.tm.cpu_flags.bitfield.cpusse4_2))
3534 {
7bab8ab5 3535 (sse_check == check_warning
daf50ae7
L		 3536 ? as_warn
3537 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3538 }
3539
321fd21e
L		 3540 /* Zap movzx and movsx suffix. The suffix has been set from
3541 "word ptr" or "byte ptr" on the source operand in Intel syntax
3542 or extracted from mnemonic in AT&T syntax. But we'll use
3543 the destination register to choose the suffix for encoding. */
3544 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3545 {
321fd21e
L		 3546 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3547 there is no suffix, the default will be byte extension. */
3548 if (i.reg_operands != 2
3549 && !i.suffix
7ab9ffdd 3550 && intel_syntax)
321fd21e
L		 3551 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3552
3553 i.suffix = 0;
cd61ebfe 3554 }
24eab124 3555
40fb9820 3556 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3557 if (!add_prefix (FWAIT_OPCODE))
3558 return;
252b5132 3559
d5de92cf
L		 3560 /* Check if REP prefix is OK. */
3561 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3562 {
3563 as_bad (_("invalid instruction `%s' after `%s'"),
3564 i.tm.name, i.rep_prefix);
3565 return;
3566 }
3567
c1ba0266
L		 3568 /* Check for lock without a lockable instruction. Destination operand
3569 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3570 if (i.prefix[LOCK_PREFIX]
3571 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3572 || i.mem_operands == 0
3573 || (i.tm.base_opcode != 0x86
3574 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3575 {
3576 as_bad (_("expecting lockable instruction after `lock'"));
3577 return;
3578 }
3579
42164a71 3580 /* Check if HLE prefix is OK. */
165de32a 3581 if (i.hle_prefix && !check_hle ())
42164a71
L		 3582 return;
3583
7e8b059b
L		 3584 /* Check BND prefix. */
3585 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3586 as_bad (_("expecting valid branch instruction after `bnd'"));
3587
3588 if (i.tm.cpu_flags.bitfield.cpumpx
3589 && flag_code == CODE_64BIT
3590 && i.prefix[ADDR_PREFIX])
3591 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3592
3593 /* Insert BND prefix. */
3594 if (add_bnd_prefix
3595 && i.tm.opcode_modifier.bndprefixok
3596 && !i.prefix[BND_PREFIX])
3597 add_prefix (BND_PREFIX_OPCODE);
3598
29b0f896 3599 /* Check string instruction segment overrides. */
40fb9820 3600 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3601 {
3602 if (!check_string ())
5dd0794d 3603 return;
fc0763e6 3604 i.disp_operands = 0;
29b0f896 3605 }
5dd0794d 3606
29b0f896
AM		 3607 if (!process_suffix ())
3608 return;
e413e4e9 3609
bc0844ae
L		 3610 /* Update operand types. */
3611 for (j = 0; j < i.operands; j++)
3612 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3613
29b0f896
AM		 3614 /* Make still unresolved immediate matches conform to size of immediate
3615 given in i.suffix. */
3616 if (!finalize_imm ())
3617 return;
252b5132 3618
40fb9820 3619 if (i.types[0].bitfield.imm1)
29b0f896 3620 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3621
9afe6eb8
L		 3622 /* We only need to check those implicit registers for instructions
3623 with 3 operands or less. */
3624 if (i.operands <= 3)
3625 for (j = 0; j < i.operands; j++)
3626 if (i.types[j].bitfield.inoutportreg
3627 || i.types[j].bitfield.shiftcount
3628 || i.types[j].bitfield.acc
3629 || i.types[j].bitfield.floatacc)
3630 i.reg_operands--;
40fb9820 3631
c0f3af97
L		 3632 /* ImmExt should be processed after SSE2AVX. */
3633 if (!i.tm.opcode_modifier.sse2avx
3634 && i.tm.opcode_modifier.immext)
65da13b5 3635 process_immext ();
252b5132 3636
29b0f896
AM		 3637 /* For insns with operands there are more diddles to do to the opcode. */
3638 if (i.operands)
3639 {
3640 if (!process_operands ())
3641 return;
3642 }
40fb9820 3643 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3644 {
3645 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3646 as_warn (_("translating to `%sp'"), i.tm.name);
3647 }
252b5132 3648
9e5e5283
L		 3649 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3650 {
3651 if (flag_code == CODE_16BIT)
3652 {
3653 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3654 i.tm.name);
3655 return;
3656 }
c0f3af97 3657
9e5e5283
L		 3658 if (i.tm.opcode_modifier.vex)
3659 build_vex_prefix (t);
3660 else
3661 build_evex_prefix ();
3662 }
43234a1e 3663
5dd85c99
SP		 3664 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3665 instructions may define INT_OPCODE as well, so avoid this corner
3666 case for those instructions that use MODRM. */
3667 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3668 && !i.tm.opcode_modifier.modrm
3669 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3670 {
3671 i.tm.base_opcode = INT3_OPCODE;
3672 i.imm_operands = 0;
3673 }
252b5132 3674
40fb9820
L		 3675 if ((i.tm.opcode_modifier.jump
3676 || i.tm.opcode_modifier.jumpbyte
3677 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3678 && i.op[0].disps->X_op == O_constant)
3679 {
3680 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3681 the absolute address given by the constant. Since ix86 jumps and
3682 calls are pc relative, we need to generate a reloc. */
3683 i.op[0].disps->X_add_symbol = &abs_symbol;
3684 i.op[0].disps->X_op = O_symbol;
3685 }
252b5132 3686
40fb9820 3687 if (i.tm.opcode_modifier.rex64)
161a04f6 3688 i.rex |= REX_W;
252b5132 3689
29b0f896
AM		 3690 /* For 8 bit registers we need an empty rex prefix. Also if the
3691 instruction already has a prefix, we need to convert old
3692 registers to new ones. */
773f551c 3693
40fb9820 3694 if ((i.types[0].bitfield.reg8
29b0f896 3695 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3696 || (i.types[1].bitfield.reg8
29b0f896 3697 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3698 || ((i.types[0].bitfield.reg8
3699 || i.types[1].bitfield.reg8)
29b0f896
AM		 3700 && i.rex != 0))
3701 {
3702 int x;
726c5dcd 3703
29b0f896
AM		 3704 i.rex |= REX_OPCODE;
3705 for (x = 0; x < 2; x++)
3706 {
3707 /* Look for 8 bit operand that uses old registers. */
40fb9820 3708 if (i.types[x].bitfield.reg8
29b0f896 3709 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3710 {
29b0f896
AM		 3711 /* In case it is "hi" register, give up. */
3712 if (i.op[x].regs->reg_num > 3)
a540244d 3713 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3714 "instruction requiring REX prefix."),
a540244d 3715 register_prefix, i.op[x].regs->reg_name);
773f551c 3716
29b0f896
AM		 3717 /* Otherwise it is equivalent to the extended register.
3718 Since the encoding doesn't change this is merely
3719 cosmetic cleanup for debug output. */
3720
3721 i.op[x].regs = i.op[x].regs + 8;
773f551c 3722 }
29b0f896
AM		 3723 }
3724 }
773f551c 3725
7ab9ffdd 3726 if (i.rex != 0)
29b0f896
AM		 3727 add_prefix (REX_OPCODE | i.rex);
3728
3729 /* We are ready to output the insn. */
3730 output_insn ();
3731}
3732
3733static char *
e3bb37b5 3734parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3735{
3736 char *l = line;
3737 char *token_start = l;
3738 char *mnem_p;
5c6af06e 3739 int supported;
d3ce72d0 3740 const insn_template *t;
b6169b20 3741 char *dot_p = NULL;
29b0f896 3742
29b0f896
AM		 3743 while (1)
3744 {
3745 mnem_p = mnemonic;
3746 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3747 {
b6169b20
L		 3748 if (*mnem_p == '.')
3749 dot_p = mnem_p;
29b0f896
AM		 3750 mnem_p++;
3751 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3752 {
29b0f896
AM		 3753 as_bad (_("no such instruction: `%s'"), token_start);
3754 return NULL;
3755 }
3756 l++;
3757 }
3758 if (!is_space_char (*l)
3759 && *l != END_OF_INSN
e44823cf
JB		 3760 && (intel_syntax
3761 || (*l != PREFIX_SEPARATOR
3762 && *l != ',')))
29b0f896
AM		 3763 {
3764 as_bad (_("invalid character %s in mnemonic"),
3765 output_invalid (*l));
3766 return NULL;
3767 }
3768 if (token_start == l)
3769 {
e44823cf 3770 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3771 as_bad (_("expecting prefix; got nothing"));
3772 else
3773 as_bad (_("expecting mnemonic; got nothing"));
3774 return NULL;
3775 }
45288df1 3776
29b0f896 3777 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3778 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3779
29b0f896
AM		 3780 if (*l != END_OF_INSN
3781 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3782 && current_templates
40fb9820 3783 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3784 {
c6fb90c8 3785 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3786 {
3787 as_bad ((flag_code != CODE_64BIT
3788 ? _("`%s' is only supported in 64-bit mode")
3789 : _("`%s' is not supported in 64-bit mode")),
3790 current_templates->start->name);
3791 return NULL;
3792 }
29b0f896
AM		 3793 /* If we are in 16-bit mode, do not allow addr16 or data16.
3794 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3795 if ((current_templates->start->opcode_modifier.size16
3796 || current_templates->start->opcode_modifier.size32)
29b0f896 3797 && flag_code != CODE_64BIT
40fb9820 3798 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3799 ^ (flag_code == CODE_16BIT)))
3800 {
3801 as_bad (_("redundant %s prefix"),
3802 current_templates->start->name);
3803 return NULL;
45288df1 3804 }
29b0f896
AM		 3805 /* Add prefix, checking for repeated prefixes. */
3806 switch (add_prefix (current_templates->start->base_opcode))
3807 {
c32fa91d 3808 case PREFIX_EXIST:
29b0f896 3809 return NULL;
c32fa91d 3810 case PREFIX_REP:
42164a71 3811 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3812 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3813 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3814 i.bnd_prefix = current_templates->start->name;
42164a71 3815 else
d5de92cf 3816 i.rep_prefix = current_templates->start->name;
29b0f896 3817 break;
c32fa91d
L		 3818 default:
3819 break;
29b0f896
AM		 3820 }
3821 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3822 token_start = ++l;
3823 }
3824 else
3825 break;
3826 }
45288df1 3827
30a55f88 3828 if (!current_templates)
b6169b20 3829 {
f8a5c266
L		 3830 /* Check if we should swap operand or force 32bit displacement in
3831 encoding. */
30a55f88
L		 3832 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3833 i.swap_operand = 1;
8d63c93e 3834 else if (mnem_p - 3 == dot_p
a501d77e
L		 3835 && dot_p[1] == 'd'
3836 && dot_p[2] == '8')
3837 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3838 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3839 && dot_p[1] == 'd'
3840 && dot_p[2] == '3'
3841 && dot_p[3] == '2')
a501d77e 3842 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3843 else
3844 goto check_suffix;
3845 mnem_p = dot_p;
3846 *dot_p = '\0';
d3ce72d0 3847 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3848 }
3849
29b0f896
AM		 3850 if (!current_templates)
3851 {
b6169b20 3852check_suffix:
29b0f896
AM		 3853 /* See if we can get a match by trimming off a suffix. */
3854 switch (mnem_p[-1])
3855 {
3856 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3857 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3858 i.suffix = SHORT_MNEM_SUFFIX;
3859 else
29b0f896
AM		 3860 case BYTE_MNEM_SUFFIX:
3861 case QWORD_MNEM_SUFFIX:
3862 i.suffix = mnem_p[-1];
3863 mnem_p[-1] = '\0';
d3ce72d0
NC		 3864 current_templates = (const templates *) hash_find (op_hash,
3865 mnemonic);
29b0f896
AM		 3866 break;
3867 case SHORT_MNEM_SUFFIX:
3868 case LONG_MNEM_SUFFIX:
3869 if (!intel_syntax)
3870 {
3871 i.suffix = mnem_p[-1];
3872 mnem_p[-1] = '\0';
d3ce72d0
NC		 3873 current_templates = (const templates *) hash_find (op_hash,
3874 mnemonic);
29b0f896
AM		 3875 }
3876 break;
252b5132 3877
29b0f896
AM		 3878 /* Intel Syntax. */
3879 case 'd':
3880 if (intel_syntax)
3881 {
9306ca4a 3882 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3883 i.suffix = SHORT_MNEM_SUFFIX;
3884 else
3885 i.suffix = LONG_MNEM_SUFFIX;
3886 mnem_p[-1] = '\0';
d3ce72d0
NC		 3887 current_templates = (const templates *) hash_find (op_hash,
3888 mnemonic);
29b0f896
AM		 3889 }
3890 break;
3891 }
3892 if (!current_templates)
3893 {
3894 as_bad (_("no such instruction: `%s'"), token_start);
3895 return NULL;
3896 }
3897 }
252b5132 3898
40fb9820
L		 3899 if (current_templates->start->opcode_modifier.jump
3900 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3901 {
3902 /* Check for a branch hint. We allow ",pt" and ",pn" for
3903 predict taken and predict not taken respectively.
3904 I'm not sure that branch hints actually do anything on loop
3905 and jcxz insns (JumpByte) for current Pentium4 chips. They
3906 may work in the future and it doesn't hurt to accept them
3907 now. */
3908 if (l[0] == ',' && l[1] == 'p')
3909 {
3910 if (l[2] == 't')
3911 {
3912 if (!add_prefix (DS_PREFIX_OPCODE))
3913 return NULL;
3914 l += 3;
3915 }
3916 else if (l[2] == 'n')
3917 {
3918 if (!add_prefix (CS_PREFIX_OPCODE))
3919 return NULL;
3920 l += 3;
3921 }
3922 }
3923 }
3924 /* Any other comma loses. */
3925 if (*l == ',')
3926 {
3927 as_bad (_("invalid character %s in mnemonic"),
3928 output_invalid (*l));
3929 return NULL;
3930 }
252b5132 3931
29b0f896 3932 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3933 supported = 0;
3934 for (t = current_templates->start; t < current_templates->end; ++t)
3935 {
c0f3af97
L		 3936 supported |= cpu_flags_match (t);
3937 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3938 goto skip;
5c6af06e 3939 }
3629bb00 3940
c0f3af97 3941 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3942 {
3943 as_bad (flag_code == CODE_64BIT
3944 ? _("`%s' is not supported in 64-bit mode")
3945 : _("`%s' is only supported in 64-bit mode"),
3946 current_templates->start->name);
3947 return NULL;
3948 }
c0f3af97 3949 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3950 {
3629bb00 3951 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3952 current_templates->start->name,
41aacd83 3953 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3954 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3955 return NULL;
29b0f896 3956 }
3629bb00
L		 3957
3958skip:
3959 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3960 && (flag_code != CODE_16BIT))
29b0f896
AM		 3961 {
3962 as_warn (_("use .code16 to ensure correct addressing mode"));
3963 }
252b5132 3964
29b0f896
AM		 3965 return l;
3966}
252b5132 3967
29b0f896 3968static char *
e3bb37b5 3969parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3970{
3971 char *token_start;
3138f287 3972
29b0f896
AM		 3973 /* 1 if operand is pending after ','. */
3974 unsigned int expecting_operand = 0;
252b5132 3975
29b0f896
AM		 3976 /* Non-zero if operand parens not balanced. */
3977 unsigned int paren_not_balanced;
3978
3979 while (*l != END_OF_INSN)
3980 {
3981 /* Skip optional white space before operand. */
3982 if (is_space_char (*l))
3983 ++l;
d02603dc 3984 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 3985 {
3986 as_bad (_("invalid character %s before operand %d"),
3987 output_invalid (*l),
3988 i.operands + 1);
3989 return NULL;
3990 }
d02603dc 3991 token_start = l; /* After white space. */
29b0f896
AM		 3992 paren_not_balanced = 0;
3993 while (paren_not_balanced || *l != ',')
3994 {
3995 if (*l == END_OF_INSN)
3996 {
3997 if (paren_not_balanced)
3998 {
3999 if (!intel_syntax)
4000 as_bad (_("unbalanced parenthesis in operand %d."),
4001 i.operands + 1);
4002 else
4003 as_bad (_("unbalanced brackets in operand %d."),
4004 i.operands + 1);
4005 return NULL;
4006 }
4007 else
4008 break; /* we are done */
4009 }
d02603dc 4010 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4011 {
4012 as_bad (_("invalid character %s in operand %d"),
4013 output_invalid (*l),
4014 i.operands + 1);
4015 return NULL;
4016 }
4017 if (!intel_syntax)
4018 {
4019 if (*l == '(')
4020 ++paren_not_balanced;
4021 if (*l == ')')
4022 --paren_not_balanced;
4023 }
4024 else
4025 {
4026 if (*l == '[')
4027 ++paren_not_balanced;
4028 if (*l == ']')
4029 --paren_not_balanced;
4030 }
4031 l++;
4032 }
4033 if (l != token_start)
4034 { /* Yes, we've read in another operand. */
4035 unsigned int operand_ok;
4036 this_operand = i.operands++;
7d5e4556 4037 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4038 if (i.operands > MAX_OPERANDS)
4039 {
4040 as_bad (_("spurious operands; (%d operands/instruction max)"),
4041 MAX_OPERANDS);
4042 return NULL;
4043 }
4044 /* Now parse operand adding info to 'i' as we go along. */
4045 END_STRING_AND_SAVE (l);
4046
4047 if (intel_syntax)
4048 operand_ok =
4049 i386_intel_operand (token_start,
4050 intel_float_operand (mnemonic));
4051 else
a7619375 4052 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4053
4054 RESTORE_END_STRING (l);
4055 if (!operand_ok)
4056 return NULL;
4057 }
4058 else
4059 {
4060 if (expecting_operand)
4061 {
4062 expecting_operand_after_comma:
4063 as_bad (_("expecting operand after ','; got nothing"));
4064 return NULL;
4065 }
4066 if (*l == ',')
4067 {
4068 as_bad (_("expecting operand before ','; got nothing"));
4069 return NULL;
4070 }
4071 }
7f3f1ea2 4072
29b0f896
AM		 4073 /* Now *l must be either ',' or END_OF_INSN. */
4074 if (*l == ',')
4075 {
4076 if (*++l == END_OF_INSN)
4077 {
4078 /* Just skip it, if it's \n complain. */
4079 goto expecting_operand_after_comma;
4080 }
4081 expecting_operand = 1;
4082 }
4083 }
4084 return l;
4085}
7f3f1ea2 4086
050dfa73 4087static void
4d456e3d 4088swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4089{
4090 union i386_op temp_op;
40fb9820 4091 i386_operand_type temp_type;
050dfa73 4092 enum bfd_reloc_code_real temp_reloc;
4eed87de 4093
050dfa73
MM		 4094 temp_type = i.types[xchg2];
4095 i.types[xchg2] = i.types[xchg1];
4096 i.types[xchg1] = temp_type;
4097 temp_op = i.op[xchg2];
4098 i.op[xchg2] = i.op[xchg1];
4099 i.op[xchg1] = temp_op;
4100 temp_reloc = i.reloc[xchg2];
4101 i.reloc[xchg2] = i.reloc[xchg1];
4102 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4103
4104 if (i.mask)
4105 {
4106 if (i.mask->operand == xchg1)
4107 i.mask->operand = xchg2;
4108 else if (i.mask->operand == xchg2)
4109 i.mask->operand = xchg1;
4110 }
4111 if (i.broadcast)
4112 {
4113 if (i.broadcast->operand == xchg1)
4114 i.broadcast->operand = xchg2;
4115 else if (i.broadcast->operand == xchg2)
4116 i.broadcast->operand = xchg1;
4117 }
4118 if (i.rounding)
4119 {
4120 if (i.rounding->operand == xchg1)
4121 i.rounding->operand = xchg2;
4122 else if (i.rounding->operand == xchg2)
4123 i.rounding->operand = xchg1;
4124 }
050dfa73
MM		 4125}
4126
29b0f896 4127static void
e3bb37b5 4128swap_operands (void)
29b0f896 4129{
b7c61d9a 4130 switch (i.operands)
050dfa73 4131 {
c0f3af97 4132 case 5:
b7c61d9a 4133 case 4:
4d456e3d 4134 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4135 case 3:
4136 case 2:
4d456e3d 4137 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4138 break;
4139 default:
4140 abort ();
29b0f896 4141 }
29b0f896
AM		 4142
4143 if (i.mem_operands == 2)
4144 {
4145 const seg_entry *temp_seg;
4146 temp_seg = i.seg[0];
4147 i.seg[0] = i.seg[1];
4148 i.seg[1] = temp_seg;
4149 }
4150}
252b5132 4151
29b0f896
AM		 4152/* Try to ensure constant immediates are represented in the smallest
4153 opcode possible. */
4154static void
e3bb37b5 4155optimize_imm (void)
29b0f896
AM		 4156{
4157 char guess_suffix = 0;
4158 int op;
252b5132 4159
29b0f896
AM		 4160 if (i.suffix)
4161 guess_suffix = i.suffix;
4162 else if (i.reg_operands)
4163 {
4164 /* Figure out a suffix from the last register operand specified.
4165 We can't do this properly yet, ie. excluding InOutPortReg,
4166 but the following works for instructions with immediates.
4167 In any case, we can't set i.suffix yet. */
4168 for (op = i.operands; --op >= 0;)
40fb9820 4169 if (i.types[op].bitfield.reg8)
7ab9ffdd 4170 {
40fb9820
L		 4171 guess_suffix = BYTE_MNEM_SUFFIX;
4172 break;
4173 }
4174 else if (i.types[op].bitfield.reg16)
252b5132 4175 {
40fb9820
L		 4176 guess_suffix = WORD_MNEM_SUFFIX;
4177 break;
4178 }
4179 else if (i.types[op].bitfield.reg32)
4180 {
4181 guess_suffix = LONG_MNEM_SUFFIX;
4182 break;
4183 }
4184 else if (i.types[op].bitfield.reg64)
4185 {
4186 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4187 break;
252b5132 4188 }
29b0f896
AM		 4189 }
4190 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4191 guess_suffix = WORD_MNEM_SUFFIX;
4192
4193 for (op = i.operands; --op >= 0;)
40fb9820 4194 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4195 {
4196 switch (i.op[op].imms->X_op)
252b5132 4197 {
29b0f896
AM		 4198 case O_constant:
4199 /* If a suffix is given, this operand may be shortened. */
4200 switch (guess_suffix)
252b5132 4201 {
29b0f896 4202 case LONG_MNEM_SUFFIX:
40fb9820
L		 4203 i.types[op].bitfield.imm32 = 1;
4204 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4205 break;
4206 case WORD_MNEM_SUFFIX:
40fb9820
L		 4207 i.types[op].bitfield.imm16 = 1;
4208 i.types[op].bitfield.imm32 = 1;
4209 i.types[op].bitfield.imm32s = 1;
4210 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4211 break;
4212 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4213 i.types[op].bitfield.imm8 = 1;
4214 i.types[op].bitfield.imm8s = 1;
4215 i.types[op].bitfield.imm16 = 1;
4216 i.types[op].bitfield.imm32 = 1;
4217 i.types[op].bitfield.imm32s = 1;
4218 i.types[op].bitfield.imm64 = 1;
29b0f896 4219 break;
252b5132 4220 }
252b5132 4221
29b0f896
AM		 4222 /* If this operand is at most 16 bits, convert it
4223 to a signed 16 bit number before trying to see
4224 whether it will fit in an even smaller size.
4225 This allows a 16-bit operand such as $0xffe0 to
4226 be recognised as within Imm8S range. */
40fb9820 4227 if ((i.types[op].bitfield.imm16)
29b0f896 4228 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4229 {
29b0f896
AM		 4230 i.op[op].imms->X_add_number =
4231 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4232 }
a28def75
L		 4233#ifdef BFD64
4234 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4235 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4236 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4237 == 0))
4238 {
4239 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4240 ^ ((offsetT) 1 << 31))
4241 - ((offsetT) 1 << 31));
4242 }
a28def75 4243#endif
40fb9820 4244 i.types[op]
c6fb90c8
L		 4245 = operand_type_or (i.types[op],
4246 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4247
29b0f896
AM		 4248 /* We must avoid matching of Imm32 templates when 64bit
4249 only immediate is available. */
4250 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4251 i.types[op].bitfield.imm32 = 0;
29b0f896 4252 break;
252b5132 4253
29b0f896
AM		 4254 case O_absent:
4255 case O_register:
4256 abort ();
4257
4258 /* Symbols and expressions. */
4259 default:
9cd96992
JB		 4260 /* Convert symbolic operand to proper sizes for matching, but don't
4261 prevent matching a set of insns that only supports sizes other
4262 than those matching the insn suffix. */
4263 {
40fb9820 4264 i386_operand_type mask, allowed;
d3ce72d0 4265 const insn_template *t;
9cd96992 4266
0dfbf9d7
L		 4267 operand_type_set (&mask, 0);
4268 operand_type_set (&allowed, 0);
40fb9820 4269
4eed87de
AM		 4270 for (t = current_templates->start;
4271 t < current_templates->end;
4272 ++t)
c6fb90c8
L		 4273 allowed = operand_type_or (allowed,
4274 t->operand_types[op]);
9cd96992
JB		 4275 switch (guess_suffix)
4276 {
4277 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4278 mask.bitfield.imm64 = 1;
4279 mask.bitfield.imm32s = 1;
9cd96992
JB		 4280 break;
4281 case LONG_MNEM_SUFFIX:
40fb9820 4282 mask.bitfield.imm32 = 1;
9cd96992
JB		 4283 break;
4284 case WORD_MNEM_SUFFIX:
40fb9820 4285 mask.bitfield.imm16 = 1;
9cd96992
JB		 4286 break;
4287 case BYTE_MNEM_SUFFIX:
40fb9820 4288 mask.bitfield.imm8 = 1;
9cd96992
JB		 4289 break;
4290 default:
9cd96992
JB		 4291 break;
4292 }
c6fb90c8 4293 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4294 if (!operand_type_all_zero (&allowed))
c6fb90c8 4295 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4296 }
29b0f896 4297 break;
252b5132 4298 }
29b0f896
AM		 4299 }
4300}
47926f60 4301
29b0f896
AM		 4302/* Try to use the smallest displacement type too. */
4303static void
e3bb37b5 4304optimize_disp (void)
29b0f896
AM		 4305{
4306 int op;
3e73aa7c 4307
29b0f896 4308 for (op = i.operands; --op >= 0;)
40fb9820 4309 if (operand_type_check (i.types[op], disp))
252b5132 4310 {
b300c311 4311 if (i.op[op].disps->X_op == O_constant)
252b5132 4312 {
91d6fa6a 4313 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4314
40fb9820 4315 if (i.types[op].bitfield.disp16
91d6fa6a 4316 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4317 {
4318 /* If this operand is at most 16 bits, convert
4319 to a signed 16 bit number and don't use 64bit
4320 displacement. */
91d6fa6a 4321 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4322 i.types[op].bitfield.disp64 = 0;
b300c311 4323 }
a28def75
L		 4324#ifdef BFD64
4325 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4326 if (i.types[op].bitfield.disp32
91d6fa6a 4327 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4328 {
4329 /* If this operand is at most 32 bits, convert
4330 to a signed 32 bit number and don't use 64bit
4331 displacement. */
91d6fa6a
NC		 4332 op_disp &= (((offsetT) 2 << 31) - 1);
4333 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4334 i.types[op].bitfield.disp64 = 0;
b300c311 4335 }
a28def75 4336#endif
91d6fa6a 4337 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4338 {
40fb9820
L		 4339 i.types[op].bitfield.disp8 = 0;
4340 i.types[op].bitfield.disp16 = 0;
4341 i.types[op].bitfield.disp32 = 0;
4342 i.types[op].bitfield.disp32s = 0;
4343 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4344 i.op[op].disps = 0;
4345 i.disp_operands--;
4346 }
4347 else if (flag_code == CODE_64BIT)
4348 {
91d6fa6a 4349 if (fits_in_signed_long (op_disp))
28a9d8f5 4350 {
40fb9820
L		 4351 i.types[op].bitfield.disp64 = 0;
4352 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4353 }
0e1147d9 4354 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4355 && fits_in_unsigned_long (op_disp))
40fb9820 4356 i.types[op].bitfield.disp32 = 1;
b300c311 4357 }
40fb9820
L		 4358 if ((i.types[op].bitfield.disp32
4359 || i.types[op].bitfield.disp32s
4360 || i.types[op].bitfield.disp16)
91d6fa6a 4361 && fits_in_signed_byte (op_disp))
40fb9820 4362 i.types[op].bitfield.disp8 = 1;
252b5132 4363 }
67a4f2b7
AO		 4364 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4365 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4366 {
4367 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4368 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4369 i.types[op].bitfield.disp8 = 0;
4370 i.types[op].bitfield.disp16 = 0;
4371 i.types[op].bitfield.disp32 = 0;
4372 i.types[op].bitfield.disp32s = 0;
4373 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4374 }
4375 else
b300c311 4376 /* We only support 64bit displacement on constants. */
40fb9820 4377 i.types[op].bitfield.disp64 = 0;
252b5132 4378 }
29b0f896
AM		 4379}
4380
6c30d220
L		 4381/* Check if operands are valid for the instruction. */
4382
4383static int
4384check_VecOperands (const insn_template *t)
4385{
43234a1e
L		 4386 unsigned int op;
4387
6c30d220
L		 4388 /* Without VSIB byte, we can't have a vector register for index. */
4389 if (!t->opcode_modifier.vecsib
4390 && i.index_reg
4391 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4392 || i.index_reg->reg_type.bitfield.regymm
4393 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4394 {
4395 i.error = unsupported_vector_index_register;
4396 return 1;
4397 }
4398
ad8ecc81
MZ		 4399 /* Check if default mask is allowed. */
4400 if (t->opcode_modifier.nodefmask
4401 && (!i.mask || i.mask->mask->reg_num == 0))
4402 {
4403 i.error = no_default_mask;
4404 return 1;
4405 }
4406
7bab8ab5
JB		 4407 /* For VSIB byte, we need a vector register for index, and all vector
4408 registers must be distinct. */
4409 if (t->opcode_modifier.vecsib)
4410 {
4411 if (!i.index_reg
6c30d220
L		 4412 || !((t->opcode_modifier.vecsib == VecSIB128
4413 && i.index_reg->reg_type.bitfield.regxmm)
4414 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4415 && i.index_reg->reg_type.bitfield.regymm)
4416 || (t->opcode_modifier.vecsib == VecSIB512
4417 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4418 {
4419 i.error = invalid_vsib_address;
4420 return 1;
4421 }
4422
43234a1e
L		 4423 gas_assert (i.reg_operands == 2 || i.mask);
4424 if (i.reg_operands == 2 && !i.mask)
4425 {
4426 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4427 || i.types[0].bitfield.regymm);
43234a1e 4428 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4429 || i.types[2].bitfield.regymm);
43234a1e
L		 4430 if (operand_check == check_none)
4431 return 0;
4432 if (register_number (i.op[0].regs)
4433 != register_number (i.index_reg)
4434 && register_number (i.op[2].regs)
4435 != register_number (i.index_reg)
4436 && register_number (i.op[0].regs)
4437 != register_number (i.op[2].regs))
4438 return 0;
4439 if (operand_check == check_error)
4440 {
4441 i.error = invalid_vector_register_set;
4442 return 1;
4443 }
4444 as_warn (_("mask, index, and destination registers should be distinct"));
4445 }
8444f82a
MZ		 4446 else if (i.reg_operands == 1 && i.mask)
4447 {
4448 if ((i.types[1].bitfield.regymm
4449 || i.types[1].bitfield.regzmm)
4450 && (register_number (i.op[1].regs)
4451 == register_number (i.index_reg)))
4452 {
4453 if (operand_check == check_error)
4454 {
4455 i.error = invalid_vector_register_set;
4456 return 1;
4457 }
4458 if (operand_check != check_none)
4459 as_warn (_("index and destination registers should be distinct"));
4460 }
4461 }
43234a1e 4462 }
7bab8ab5 4463
43234a1e
L		 4464 /* Check if broadcast is supported by the instruction and is applied
4465 to the memory operand. */
4466 if (i.broadcast)
4467 {
4468 int broadcasted_opnd_size;
4469
4470 /* Check if specified broadcast is supported in this instruction,
4471 and it's applied to memory operand of DWORD or QWORD type,
4472 depending on VecESize. */
4473 if (i.broadcast->type != t->opcode_modifier.broadcast
4474 || !i.types[i.broadcast->operand].bitfield.mem
4475 || (t->opcode_modifier.vecesize == 0
4476 && !i.types[i.broadcast->operand].bitfield.dword
4477 && !i.types[i.broadcast->operand].bitfield.unspecified)
4478 || (t->opcode_modifier.vecesize == 1
4479 && !i.types[i.broadcast->operand].bitfield.qword
4480 && !i.types[i.broadcast->operand].bitfield.unspecified))
4481 goto bad_broadcast;
4482
4483 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4484 if (i.broadcast->type == BROADCAST_1TO16)
4485 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4486 else if (i.broadcast->type == BROADCAST_1TO8)
4487 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4488 else if (i.broadcast->type == BROADCAST_1TO4)
4489 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4490 else if (i.broadcast->type == BROADCAST_1TO2)
4491 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4492 else
4493 goto bad_broadcast;
4494
4495 if ((broadcasted_opnd_size == 256
4496 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4497 || (broadcasted_opnd_size == 512
4498 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4499 {
4500 bad_broadcast:
4501 i.error = unsupported_broadcast;
4502 return 1;
4503 }
4504 }
4505 /* If broadcast is supported in this instruction, we need to check if
4506 operand of one-element size isn't specified without broadcast. */
4507 else if (t->opcode_modifier.broadcast && i.mem_operands)
4508 {
4509 /* Find memory operand. */
4510 for (op = 0; op < i.operands; op++)
4511 if (operand_type_check (i.types[op], anymem))
4512 break;
4513 gas_assert (op < i.operands);
4514 /* Check size of the memory operand. */
4515 if ((t->opcode_modifier.vecesize == 0
4516 && i.types[op].bitfield.dword)
4517 || (t->opcode_modifier.vecesize == 1
4518 && i.types[op].bitfield.qword))
4519 {
4520 i.error = broadcast_needed;
4521 return 1;
4522 }
4523 }
4524
4525 /* Check if requested masking is supported. */
4526 if (i.mask
4527 && (!t->opcode_modifier.masking
4528 || (i.mask->zeroing
4529 && t->opcode_modifier.masking == MERGING_MASKING)))
4530 {
4531 i.error = unsupported_masking;
4532 return 1;
4533 }
4534
4535 /* Check if masking is applied to dest operand. */
4536 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4537 {
4538 i.error = mask_not_on_destination;
4539 return 1;
4540 }
4541
43234a1e
L		 4542 /* Check RC/SAE. */
4543 if (i.rounding)
4544 {
4545 if ((i.rounding->type != saeonly
4546 && !t->opcode_modifier.staticrounding)
4547 || (i.rounding->type == saeonly
4548 && (t->opcode_modifier.staticrounding
4549 || !t->opcode_modifier.sae)))
4550 {
4551 i.error = unsupported_rc_sae;
4552 return 1;
4553 }
4554 /* If the instruction has several immediate operands and one of
4555 them is rounding, the rounding operand should be the last
4556 immediate operand. */
4557 if (i.imm_operands > 1
4558 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4559 {
43234a1e 4560 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4561 return 1;
4562 }
6c30d220
L		 4563 }
4564
43234a1e
L		 4565 /* Check vector Disp8 operand. */
4566 if (t->opcode_modifier.disp8memshift)
4567 {
4568 if (i.broadcast)
4569 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4570 else
4571 i.memshift = t->opcode_modifier.disp8memshift;
4572
4573 for (op = 0; op < i.operands; op++)
4574 if (operand_type_check (i.types[op], disp)
4575 && i.op[op].disps->X_op == O_constant)
4576 {
4577 offsetT value = i.op[op].disps->X_add_number;
5be33403
L		 4578 int vec_disp8_ok
4579 = (i.disp_encoding != disp_encoding_32bit
4580 && fits_in_vec_disp8 (value));
43234a1e
L		 4581 if (t->operand_types [op].bitfield.vec_disp8)
4582 {
4583 if (vec_disp8_ok)
4584 i.types[op].bitfield.vec_disp8 = 1;
4585 else
4586 {
4587 /* Vector insn can only have Vec_Disp8/Disp32 in
4588 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4589 mode. */
4590 i.types[op].bitfield.disp8 = 0;
4591 if (flag_code != CODE_16BIT)
4592 i.types[op].bitfield.disp16 = 0;
4593 }
4594 }
4595 else if (flag_code != CODE_16BIT)
4596 {
4597 /* One form of this instruction supports vector Disp8.
4598 Try vector Disp8 if we need to use Disp32. */
4599 if (vec_disp8_ok && !fits_in_signed_byte (value))
4600 {
4601 i.error = try_vector_disp8;
4602 return 1;
4603 }
4604 }
4605 }
4606 }
4607 else
4608 i.memshift = -1;
4609
6c30d220
L		 4610 return 0;
4611}
4612
43f3e2ee 4613/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4614 operand types. */
4615
4616static int
4617VEX_check_operands (const insn_template *t)
4618{
43234a1e
L		 4619 /* VREX is only valid with EVEX prefix. */
4620 if (i.need_vrex && !t->opcode_modifier.evex)
4621 {
4622 i.error = invalid_register_operand;
4623 return 1;
4624 }
4625
a683cc34
SP		 4626 if (!t->opcode_modifier.vex)
4627 return 0;
4628
4629 /* Only check VEX_Imm4, which must be the first operand. */
4630 if (t->operand_types[0].bitfield.vec_imm4)
4631 {
4632 if (i.op[0].imms->X_op != O_constant
4633 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4634 {
a65babc9 4635 i.error = bad_imm4;
891edac4
L		 4636 return 1;
4637 }
a683cc34
SP		 4638
4639 /* Turn off Imm8 so that update_imm won't complain. */
4640 i.types[0] = vec_imm4;
4641 }
4642
4643 return 0;
4644}
4645
d3ce72d0 4646static const insn_template *
e3bb37b5 4647match_template (void)
29b0f896
AM		 4648{
4649 /* Points to template once we've found it. */
d3ce72d0 4650 const insn_template *t;
40fb9820 4651 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4652 i386_operand_type overlap4;
29b0f896 4653 unsigned int found_reverse_match;
40fb9820
L		 4654 i386_opcode_modifier suffix_check;
4655 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4656 int addr_prefix_disp;
a5c311ca 4657 unsigned int j;
3629bb00 4658 unsigned int found_cpu_match;
45664ddb 4659 unsigned int check_register;
5614d22c 4660 enum i386_error specific_error = 0;
29b0f896 4661
c0f3af97
L		 4662#if MAX_OPERANDS != 5
4663# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4664#endif
4665
29b0f896 4666 found_reverse_match = 0;
539e75ad 4667 addr_prefix_disp = -1;
40fb9820
L		 4668
4669 memset (&suffix_check, 0, sizeof (suffix_check));
4670 if (i.suffix == BYTE_MNEM_SUFFIX)
4671 suffix_check.no_bsuf = 1;
4672 else if (i.suffix == WORD_MNEM_SUFFIX)
4673 suffix_check.no_wsuf = 1;
4674 else if (i.suffix == SHORT_MNEM_SUFFIX)
4675 suffix_check.no_ssuf = 1;
4676 else if (i.suffix == LONG_MNEM_SUFFIX)
4677 suffix_check.no_lsuf = 1;
4678 else if (i.suffix == QWORD_MNEM_SUFFIX)
4679 suffix_check.no_qsuf = 1;
4680 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4681 suffix_check.no_ldsuf = 1;
29b0f896 4682
01559ecc
L		 4683 /* Must have right number of operands. */
4684 i.error = number_of_operands_mismatch;
4685
45aa61fe 4686 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4687 {
539e75ad
L		 4688 addr_prefix_disp = -1;
4689
29b0f896
AM		 4690 if (i.operands != t->operands)
4691 continue;
4692
50aecf8c 4693 /* Check processor support. */
a65babc9 4694 i.error = unsupported;
c0f3af97
L		 4695 found_cpu_match = (cpu_flags_match (t)
4696 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4697 if (!found_cpu_match)
4698 continue;
4699
e1d4d893 4700 /* Check old gcc support. */
a65babc9 4701 i.error = old_gcc_only;
e1d4d893
L		 4702 if (!old_gcc && t->opcode_modifier.oldgcc)
4703 continue;
4704
4705 /* Check AT&T mnemonic. */
a65babc9 4706 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4707 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4708 continue;
4709
891edac4 4710 /* Check AT&T/Intel syntax. */
a65babc9 4711 i.error = unsupported_syntax;
5c07affc
L		 4712 if ((intel_syntax && t->opcode_modifier.attsyntax)
4713 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4714 continue;
4715
20592a94 4716 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4717 i.error = invalid_instruction_suffix;
567e4e96
L		 4718 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4719 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4720 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4721 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4722 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4723 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4724 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4725 continue;
4726
5c07affc 4727 if (!operand_size_match (t))
7d5e4556 4728 continue;
539e75ad 4729
5c07affc
L		 4730 for (j = 0; j < MAX_OPERANDS; j++)
4731 operand_types[j] = t->operand_types[j];
4732
45aa61fe
AM		 4733 /* In general, don't allow 64-bit operands in 32-bit mode. */
4734 if (i.suffix == QWORD_MNEM_SUFFIX
4735 && flag_code != CODE_64BIT
4736 && (intel_syntax
40fb9820 4737 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4738 && !intel_float_operand (t->name))
4739 : intel_float_operand (t->name) != 2)
40fb9820 4740 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4741 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4742 && !operand_types[0].bitfield.regymm
4743 && !operand_types[0].bitfield.regzmm)
40fb9820 4744 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4745 && operand_types[t->operands > 1].bitfield.regxmm
4746 && operand_types[t->operands > 1].bitfield.regymm
4747 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4748 && (t->base_opcode != 0x0fc7
4749 || t->extension_opcode != 1 /* cmpxchg8b */))
4750 continue;
4751
192dc9c6
JB		 4752 /* In general, don't allow 32-bit operands on pre-386. */
4753 else if (i.suffix == LONG_MNEM_SUFFIX
4754 && !cpu_arch_flags.bitfield.cpui386
4755 && (intel_syntax
4756 ? (!t->opcode_modifier.ignoresize
4757 && !intel_float_operand (t->name))
4758 : intel_float_operand (t->name) != 2)
4759 && ((!operand_types[0].bitfield.regmmx
4760 && !operand_types[0].bitfield.regxmm)
4761 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 4762 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 4763 continue;
4764
29b0f896 4765 /* Do not verify operands when there are none. */
50aecf8c 4766 else
29b0f896 4767 {
c6fb90c8 4768 if (!t->operands)
2dbab7d5
L		 4769 /* We've found a match; break out of loop. */
4770 break;
29b0f896 4771 }
252b5132 4772
539e75ad
L		 4773 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4774 into Disp32/Disp16/Disp32 operand. */
4775 if (i.prefix[ADDR_PREFIX] != 0)
4776 {
40fb9820 4777 /* There should be only one Disp operand. */
539e75ad
L		 4778 switch (flag_code)
4779 {
4780 case CODE_16BIT:
40fb9820
L		 4781 for (j = 0; j < MAX_OPERANDS; j++)
4782 {
4783 if (operand_types[j].bitfield.disp16)
4784 {
4785 addr_prefix_disp = j;
4786 operand_types[j].bitfield.disp32 = 1;
4787 operand_types[j].bitfield.disp16 = 0;
4788 break;
4789 }
4790 }
539e75ad
L		 4791 break;
4792 case CODE_32BIT:
40fb9820
L		 4793 for (j = 0; j < MAX_OPERANDS; j++)
4794 {
4795 if (operand_types[j].bitfield.disp32)
4796 {
4797 addr_prefix_disp = j;
4798 operand_types[j].bitfield.disp32 = 0;
4799 operand_types[j].bitfield.disp16 = 1;
4800 break;
4801 }
4802 }
539e75ad
L		 4803 break;
4804 case CODE_64BIT:
40fb9820
L		 4805 for (j = 0; j < MAX_OPERANDS; j++)
4806 {
4807 if (operand_types[j].bitfield.disp64)
4808 {
4809 addr_prefix_disp = j;
4810 operand_types[j].bitfield.disp64 = 0;
4811 operand_types[j].bitfield.disp32 = 1;
4812 break;
4813 }
4814 }
539e75ad
L		 4815 break;
4816 }
539e75ad
L		 4817 }
4818
02a86693
L		 4819 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4820 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
4821 continue;
4822
56ffb741
L		 4823 /* We check register size if needed. */
4824 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4825 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4826 switch (t->operands)
4827 {
4828 case 1:
40fb9820 4829 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4830 continue;
4831 break;
4832 case 2:
8b38ad71
L		 4833 /* xchg %eax, %eax is a special case. It is an aliase for nop
4834 only in 32bit mode and we can use opcode 0x90. In 64bit
4835 mode, we can't use 0x90 for xchg %eax, %eax since it should
4836 zero-extend %eax to %rax. */
4837 if (flag_code == CODE_64BIT
4838 && t->base_opcode == 0x90
0dfbf9d7
L		 4839 && operand_type_equal (&i.types [0], &acc32)
4840 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4841 continue;
b6169b20
L		 4842 if (i.swap_operand)
4843 {
4844 /* If we swap operand in encoding, we either match
4845 the next one or reverse direction of operands. */
4846 if (t->opcode_modifier.s)
4847 continue;
4848 else if (t->opcode_modifier.d)
4849 goto check_reverse;
4850 }
4851
29b0f896 4852 case 3:
fa99fab2
L		 4853 /* If we swap operand in encoding, we match the next one. */
4854 if (i.swap_operand && t->opcode_modifier.s)
4855 continue;
f48ff2ae 4856 case 4:
c0f3af97 4857 case 5:
c6fb90c8 4858 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4859 if (!operand_type_match (overlap0, i.types[0])
4860 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4861 || (check_register
4862 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4863 operand_types[0],
4864 overlap1, i.types[1],
4865 operand_types[1])))
29b0f896
AM		 4866 {
4867 /* Check if other direction is valid ... */
40fb9820 4868 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4869 continue;
4870
b6169b20 4871check_reverse:
29b0f896 4872 /* Try reversing direction of operands. */
c6fb90c8
L		 4873 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4874 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4875 if (!operand_type_match (overlap0, i.types[0])
4876 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4877 || (check_register
4878 && !operand_type_register_match (overlap0,
4879 i.types[0],
4880 operand_types[1],
4881 overlap1,
4882 i.types[1],
4883 operand_types[0])))
29b0f896
AM		 4884 {
4885 /* Does not match either direction. */
4886 continue;
4887 }
4888 /* found_reverse_match holds which of D or FloatDR
4889 we've found. */
40fb9820 4890 if (t->opcode_modifier.d)
8a2ed489 4891 found_reverse_match = Opcode_D;
40fb9820 4892 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4893 found_reverse_match = Opcode_FloatD;
4894 else
4895 found_reverse_match = 0;
40fb9820 4896 if (t->opcode_modifier.floatr)
8a2ed489 4897 found_reverse_match |= Opcode_FloatR;
29b0f896 4898 }
f48ff2ae 4899 else
29b0f896 4900 {
f48ff2ae 4901 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4902 switch (t->operands)
4903 {
c0f3af97
L		 4904 case 5:
4905 overlap4 = operand_type_and (i.types[4],
4906 operand_types[4]);
d1cbb4db 4907 case 4:
c6fb90c8
L		 4908 overlap3 = operand_type_and (i.types[3],
4909 operand_types[3]);
d1cbb4db 4910 case 3:
c6fb90c8
L		 4911 overlap2 = operand_type_and (i.types[2],
4912 operand_types[2]);
d1cbb4db
L		 4913 break;
4914 }
29b0f896 4915
f48ff2ae
L		 4916 switch (t->operands)
4917 {
c0f3af97
L		 4918 case 5:
4919 if (!operand_type_match (overlap4, i.types[4])
4920 || !operand_type_register_match (overlap3,
4921 i.types[3],
4922 operand_types[3],
4923 overlap4,
4924 i.types[4],
4925 operand_types[4]))
4926 continue;
f48ff2ae 4927 case 4:
40fb9820 4928 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4929 || (check_register
4930 && !operand_type_register_match (overlap2,
4931 i.types[2],
4932 operand_types[2],
4933 overlap3,
4934 i.types[3],
4935 operand_types[3])))
f48ff2ae
L		 4936 continue;
4937 case 3:
4938 /* Here we make use of the fact that there are no
4939 reverse match 3 operand instructions, and all 3
4940 operand instructions only need to be checked for
4941 register consistency between operands 2 and 3. */
40fb9820 4942 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4943 || (check_register
4944 && !operand_type_register_match (overlap1,
4945 i.types[1],
4946 operand_types[1],
4947 overlap2,
4948 i.types[2],
4949 operand_types[2])))
f48ff2ae
L		 4950 continue;
4951 break;
4952 }
29b0f896 4953 }
f48ff2ae 4954 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4955 slip through to break. */
4956 }
3629bb00 4957 if (!found_cpu_match)
29b0f896
AM		 4958 {
4959 found_reverse_match = 0;
4960 continue;
4961 }
c0f3af97 4962
5614d22c
JB		 4963 /* Check if vector and VEX operands are valid. */
4964 if (check_VecOperands (t) || VEX_check_operands (t))
4965 {
4966 specific_error = i.error;
4967 continue;
4968 }
a683cc34 4969
29b0f896
AM		 4970 /* We've found a match; break out of loop. */
4971 break;
4972 }
4973
4974 if (t == current_templates->end)
4975 {
4976 /* We found no match. */
a65babc9 4977 const char *err_msg;
5614d22c 4978 switch (specific_error ? specific_error : i.error)
a65babc9
L		 4979 {
4980 default:
4981 abort ();
86e026a4 4982 case operand_size_mismatch:
a65babc9
L		 4983 err_msg = _("operand size mismatch");
4984 break;
4985 case operand_type_mismatch:
4986 err_msg = _("operand type mismatch");
4987 break;
4988 case register_type_mismatch:
4989 err_msg = _("register type mismatch");
4990 break;
4991 case number_of_operands_mismatch:
4992 err_msg = _("number of operands mismatch");
4993 break;
4994 case invalid_instruction_suffix:
4995 err_msg = _("invalid instruction suffix");
4996 break;
4997 case bad_imm4:
4a2608e3 4998 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 4999 break;
5000 case old_gcc_only:
5001 err_msg = _("only supported with old gcc");
5002 break;
5003 case unsupported_with_intel_mnemonic:
5004 err_msg = _("unsupported with Intel mnemonic");
5005 break;
5006 case unsupported_syntax:
5007 err_msg = _("unsupported syntax");
5008 break;
5009 case unsupported:
35262a23 5010 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5011 current_templates->start->name);
5012 return NULL;
6c30d220
L		 5013 case invalid_vsib_address:
5014 err_msg = _("invalid VSIB address");
5015 break;
7bab8ab5
JB		 5016 case invalid_vector_register_set:
5017 err_msg = _("mask, index, and destination registers must be distinct");
5018 break;
6c30d220
L		 5019 case unsupported_vector_index_register:
5020 err_msg = _("unsupported vector index register");
5021 break;
43234a1e
L		 5022 case unsupported_broadcast:
5023 err_msg = _("unsupported broadcast");
5024 break;
5025 case broadcast_not_on_src_operand:
5026 err_msg = _("broadcast not on source memory operand");
5027 break;
5028 case broadcast_needed:
5029 err_msg = _("broadcast is needed for operand of such type");
5030 break;
5031 case unsupported_masking:
5032 err_msg = _("unsupported masking");
5033 break;
5034 case mask_not_on_destination:
5035 err_msg = _("mask not on destination operand");
5036 break;
5037 case no_default_mask:
5038 err_msg = _("default mask isn't allowed");
5039 break;
5040 case unsupported_rc_sae:
5041 err_msg = _("unsupported static rounding/sae");
5042 break;
5043 case rc_sae_operand_not_last_imm:
5044 if (intel_syntax)
5045 err_msg = _("RC/SAE operand must precede immediate operands");
5046 else
5047 err_msg = _("RC/SAE operand must follow immediate operands");
5048 break;
5049 case invalid_register_operand:
5050 err_msg = _("invalid register operand");
5051 break;
a65babc9
L		 5052 }
5053 as_bad (_("%s for `%s'"), err_msg,
891edac4 5054 current_templates->start->name);
fa99fab2 5055 return NULL;
29b0f896 5056 }
252b5132 5057
29b0f896
AM		 5058 if (!quiet_warnings)
5059 {
5060 if (!intel_syntax
40fb9820
L		 5061 && (i.types[0].bitfield.jumpabsolute
5062 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5063 {
5064 as_warn (_("indirect %s without `*'"), t->name);
5065 }
5066
40fb9820
L		 5067 if (t->opcode_modifier.isprefix
5068 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5069 {
5070 /* Warn them that a data or address size prefix doesn't
5071 affect assembly of the next line of code. */
5072 as_warn (_("stand-alone `%s' prefix"), t->name);
5073 }
5074 }
5075
5076 /* Copy the template we found. */
5077 i.tm = *t;
539e75ad
L		 5078
5079 if (addr_prefix_disp != -1)
5080 i.tm.operand_types[addr_prefix_disp]
5081 = operand_types[addr_prefix_disp];
5082
29b0f896
AM		 5083 if (found_reverse_match)
5084 {
5085 /* If we found a reverse match we must alter the opcode
5086 direction bit. found_reverse_match holds bits to change
5087 (different for int & float insns). */
5088
5089 i.tm.base_opcode ^= found_reverse_match;
5090
539e75ad
L		 5091 i.tm.operand_types[0] = operand_types[1];
5092 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5093 }
5094
fa99fab2 5095 return t;
29b0f896
AM		 5096}
5097
5098static int
e3bb37b5 5099check_string (void)
29b0f896 5100{
40fb9820
L		 5101 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5102 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5103 {
5104 if (i.seg[0] != NULL && i.seg[0] != &es)
5105 {
a87af027 5106 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5107 i.tm.name,
a87af027
JB		 5108 mem_op + 1,
5109 register_prefix);
29b0f896
AM		 5110 return 0;
5111 }
5112 /* There's only ever one segment override allowed per instruction.
5113 This instruction possibly has a legal segment override on the
5114 second operand, so copy the segment to where non-string
5115 instructions store it, allowing common code. */
5116 i.seg[0] = i.seg[1];
5117 }
40fb9820 5118 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5119 {
5120 if (i.seg[1] != NULL && i.seg[1] != &es)
5121 {
a87af027 5122 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5123 i.tm.name,
a87af027
JB		 5124 mem_op + 2,
5125 register_prefix);
29b0f896
AM		 5126 return 0;
5127 }
5128 }
5129 return 1;
5130}
5131
5132static int
543613e9 5133process_suffix (void)
29b0f896
AM		 5134{
5135 /* If matched instruction specifies an explicit instruction mnemonic
5136 suffix, use it. */
40fb9820
L		 5137 if (i.tm.opcode_modifier.size16)
5138 i.suffix = WORD_MNEM_SUFFIX;
5139 else if (i.tm.opcode_modifier.size32)
5140 i.suffix = LONG_MNEM_SUFFIX;
5141 else if (i.tm.opcode_modifier.size64)
5142 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5143 else if (i.reg_operands)
5144 {
5145 /* If there's no instruction mnemonic suffix we try to invent one
5146 based on register operands. */
5147 if (!i.suffix)
5148 {
5149 /* We take i.suffix from the last register operand specified,
5150 Destination register type is more significant than source
381d071f
L		 5151 register type. crc32 in SSE4.2 prefers source register
5152 type. */
5153 if (i.tm.base_opcode == 0xf20f38f1)
5154 {
40fb9820
L		 5155 if (i.types[0].bitfield.reg16)
5156 i.suffix = WORD_MNEM_SUFFIX;
5157 else if (i.types[0].bitfield.reg32)
5158 i.suffix = LONG_MNEM_SUFFIX;
5159 else if (i.types[0].bitfield.reg64)
5160 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5161 }
9344ff29 5162 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5163 {
40fb9820 5164 if (i.types[0].bitfield.reg8)
20592a94
L		 5165 i.suffix = BYTE_MNEM_SUFFIX;
5166 }
381d071f
L		 5167
5168 if (!i.suffix)
5169 {
5170 int op;
5171
20592a94
L		 5172 if (i.tm.base_opcode == 0xf20f38f1
5173 || i.tm.base_opcode == 0xf20f38f0)
5174 {
5175 /* We have to know the operand size for crc32. */
5176 as_bad (_("ambiguous memory operand size for `%s`"),
5177 i.tm.name);
5178 return 0;
5179 }
5180
381d071f 5181 for (op = i.operands; --op >= 0;)
40fb9820 5182 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5183 {
40fb9820
L		 5184 if (i.types[op].bitfield.reg8)
5185 {
5186 i.suffix = BYTE_MNEM_SUFFIX;
5187 break;
5188 }
5189 else if (i.types[op].bitfield.reg16)
5190 {
5191 i.suffix = WORD_MNEM_SUFFIX;
5192 break;
5193 }
5194 else if (i.types[op].bitfield.reg32)
5195 {
5196 i.suffix = LONG_MNEM_SUFFIX;
5197 break;
5198 }
5199 else if (i.types[op].bitfield.reg64)
5200 {
5201 i.suffix = QWORD_MNEM_SUFFIX;
5202 break;
5203 }
381d071f
L		 5204 }
5205 }
29b0f896
AM		 5206 }
5207 else if (i.suffix == BYTE_MNEM_SUFFIX)
5208 {
2eb952a4
L		 5209 if (intel_syntax
5210 && i.tm.opcode_modifier.ignoresize
5211 && i.tm.opcode_modifier.no_bsuf)
5212 i.suffix = 0;
5213 else if (!check_byte_reg ())
29b0f896
AM		 5214 return 0;
5215 }
5216 else if (i.suffix == LONG_MNEM_SUFFIX)
5217 {
2eb952a4
L		 5218 if (intel_syntax
5219 && i.tm.opcode_modifier.ignoresize
5220 && i.tm.opcode_modifier.no_lsuf)
5221 i.suffix = 0;
5222 else if (!check_long_reg ())
29b0f896
AM		 5223 return 0;
5224 }
5225 else if (i.suffix == QWORD_MNEM_SUFFIX)
5226 {
955e1e6a
L		 5227 if (intel_syntax
5228 && i.tm.opcode_modifier.ignoresize
5229 && i.tm.opcode_modifier.no_qsuf)
5230 i.suffix = 0;
5231 else if (!check_qword_reg ())
29b0f896
AM		 5232 return 0;
5233 }
5234 else if (i.suffix == WORD_MNEM_SUFFIX)
5235 {
2eb952a4
L		 5236 if (intel_syntax
5237 && i.tm.opcode_modifier.ignoresize
5238 && i.tm.opcode_modifier.no_wsuf)
5239 i.suffix = 0;
5240 else if (!check_word_reg ())
29b0f896
AM		 5241 return 0;
5242 }
c0f3af97 5243 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5244 || i.suffix == YMMWORD_MNEM_SUFFIX
5245 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5246 {
43234a1e 5247 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5248 should check if it is a valid suffix. */
5249 }
40fb9820 5250 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5251 /* Do nothing if the instruction is going to ignore the prefix. */
5252 ;
5253 else
5254 abort ();
5255 }
40fb9820 5256 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5257 && !i.suffix
5258 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5259 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5260 {
5261 i.suffix = stackop_size;
5262 }
9306ca4a
JB		 5263 else if (intel_syntax
5264 && !i.suffix
40fb9820
L		 5265 && (i.tm.operand_types[0].bitfield.jumpabsolute
5266 || i.tm.opcode_modifier.jumpbyte
5267 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5268 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5269 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5270 {
5271 switch (flag_code)
5272 {
5273 case CODE_64BIT:
40fb9820 5274 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5275 {
5276 i.suffix = QWORD_MNEM_SUFFIX;
5277 break;
5278 }
5279 case CODE_32BIT:
40fb9820 5280 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5281 i.suffix = LONG_MNEM_SUFFIX;
5282 break;
5283 case CODE_16BIT:
40fb9820 5284 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5285 i.suffix = WORD_MNEM_SUFFIX;
5286 break;
5287 }
5288 }
252b5132 5289
9306ca4a 5290 if (!i.suffix)
29b0f896 5291 {
9306ca4a
JB		 5292 if (!intel_syntax)
5293 {
40fb9820 5294 if (i.tm.opcode_modifier.w)
9306ca4a 5295 {
4eed87de
AM		 5296 as_bad (_("no instruction mnemonic suffix given and "
5297 "no register operands; can't size instruction"));
9306ca4a
JB		 5298 return 0;
5299 }
5300 }
5301 else
5302 {
40fb9820 5303 unsigned int suffixes;
7ab9ffdd 5304
40fb9820
L		 5305 suffixes = !i.tm.opcode_modifier.no_bsuf;
5306 if (!i.tm.opcode_modifier.no_wsuf)
5307 suffixes |= 1 << 1;
5308 if (!i.tm.opcode_modifier.no_lsuf)
5309 suffixes |= 1 << 2;
fc4adea1 5310 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5311 suffixes |= 1 << 3;
5312 if (!i.tm.opcode_modifier.no_ssuf)
5313 suffixes |= 1 << 4;
5314 if (!i.tm.opcode_modifier.no_qsuf)
5315 suffixes |= 1 << 5;
5316
5317 /* There are more than suffix matches. */
5318 if (i.tm.opcode_modifier.w
9306ca4a 5319 || ((suffixes & (suffixes - 1))
40fb9820
L		 5320 && !i.tm.opcode_modifier.defaultsize
5321 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5322 {
5323 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5324 return 0;
5325 }
5326 }
29b0f896 5327 }
252b5132 5328
9306ca4a
JB		 5329 /* Change the opcode based on the operand size given by i.suffix;
5330 We don't need to change things for byte insns. */
5331
582d5edd
L		 5332 if (i.suffix
5333 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5334 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5335 && i.suffix != YMMWORD_MNEM_SUFFIX
5336 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5337 {
5338 /* It's not a byte, select word/dword operation. */
40fb9820 5339 if (i.tm.opcode_modifier.w)
29b0f896 5340 {
40fb9820 5341 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5342 i.tm.base_opcode |= 8;
5343 else
5344 i.tm.base_opcode |= 1;
5345 }
0f3f3d8b 5346
29b0f896
AM		 5347 /* Now select between word & dword operations via the operand
5348 size prefix, except for instructions that will ignore this
5349 prefix anyway. */
ca61edf2 5350 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5351 {
ca61edf2
L		 5352 /* The address size override prefix changes the size of the
5353 first operand. */
40fb9820
L		 5354 if ((flag_code == CODE_32BIT
5355 && i.op->regs[0].reg_type.bitfield.reg16)
5356 || (flag_code != CODE_32BIT
5357 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5358 if (!add_prefix (ADDR_PREFIX_OPCODE))
5359 return 0;
5360 }
5361 else if (i.suffix != QWORD_MNEM_SUFFIX
5362 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5363 && !i.tm.opcode_modifier.ignoresize
5364 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5365 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5366 || (flag_code == CODE_64BIT
40fb9820 5367 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5368 {
5369 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5370
40fb9820 5371 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5372 prefix = ADDR_PREFIX_OPCODE;
252b5132 5373
29b0f896
AM		 5374 if (!add_prefix (prefix))
5375 return 0;
24eab124 5376 }
252b5132 5377
29b0f896
AM		 5378 /* Set mode64 for an operand. */
5379 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5380 && flag_code == CODE_64BIT
40fb9820 5381 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5382 {
5383 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5384 need rex64. cmpxchg8b is also a special case. */
5385 if (! (i.operands == 2
5386 && i.tm.base_opcode == 0x90
5387 && i.tm.extension_opcode == None
0dfbf9d7
L		 5388 && operand_type_equal (&i.types [0], &acc64)
5389 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5390 && ! (i.operands == 1
5391 && i.tm.base_opcode == 0xfc7
5392 && i.tm.extension_opcode == 1
40fb9820
L		 5393 && !operand_type_check (i.types [0], reg)
5394 && operand_type_check (i.types [0], anymem)))
f6bee062 5395 i.rex |= REX_W;
46e883c5 5396 }
3e73aa7c 5397
29b0f896
AM		 5398 /* Size floating point instruction. */
5399 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5400 if (i.tm.opcode_modifier.floatmf)
543613e9 5401 i.tm.base_opcode ^= 4;
29b0f896 5402 }
7ecd2f8b 5403
29b0f896
AM		 5404 return 1;
5405}
3e73aa7c 5406
29b0f896 5407static int
543613e9 5408check_byte_reg (void)
29b0f896
AM		 5409{
5410 int op;
543613e9 5411
29b0f896
AM		 5412 for (op = i.operands; --op >= 0;)
5413 {
5414 /* If this is an eight bit register, it's OK. If it's the 16 or
5415 32 bit version of an eight bit register, we will just use the
5416 low portion, and that's OK too. */
40fb9820 5417 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5418 continue;
5419
5a819eb9
JB		 5420 /* I/O port address operands are OK too. */
5421 if (i.tm.operand_types[op].bitfield.inoutportreg)
5422 continue;
5423
9344ff29
L		 5424 /* crc32 doesn't generate this warning. */
5425 if (i.tm.base_opcode == 0xf20f38f0)
5426 continue;
5427
40fb9820
L		 5428 if ((i.types[op].bitfield.reg16
5429 || i.types[op].bitfield.reg32
5430 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5431 && i.op[op].regs->reg_num < 4
5432 /* Prohibit these changes in 64bit mode, since the lowering
5433 would be more complicated. */
5434 && flag_code != CODE_64BIT)
29b0f896 5435 {
29b0f896 5436#if REGISTER_WARNINGS
5a819eb9 5437 if (!quiet_warnings)
a540244d
L		 5438 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5439 register_prefix,
40fb9820 5440 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5441 ? REGNAM_AL - REGNAM_AX
5442 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5443 register_prefix,
29b0f896
AM		 5444 i.op[op].regs->reg_name,
5445 i.suffix);
5446#endif
5447 continue;
5448 }
5449 /* Any other register is bad. */
40fb9820
L		 5450 if (i.types[op].bitfield.reg16
5451 || i.types[op].bitfield.reg32
5452 || i.types[op].bitfield.reg64
5453 || i.types[op].bitfield.regmmx
5454 || i.types[op].bitfield.regxmm
c0f3af97 5455 || i.types[op].bitfield.regymm
43234a1e 5456 || i.types[op].bitfield.regzmm
40fb9820
L		 5457 || i.types[op].bitfield.sreg2
5458 || i.types[op].bitfield.sreg3
5459 || i.types[op].bitfield.control
5460 || i.types[op].bitfield.debug
5461 || i.types[op].bitfield.test
5462 || i.types[op].bitfield.floatreg
5463 || i.types[op].bitfield.floatacc)
29b0f896 5464 {
a540244d
L		 5465 as_bad (_("`%s%s' not allowed with `%s%c'"),
5466 register_prefix,
29b0f896
AM		 5467 i.op[op].regs->reg_name,
5468 i.tm.name,
5469 i.suffix);
5470 return 0;
5471 }
5472 }
5473 return 1;
5474}
5475
5476static int
e3bb37b5 5477check_long_reg (void)
29b0f896
AM		 5478{
5479 int op;
5480
5481 for (op = i.operands; --op >= 0;)
5482 /* Reject eight bit registers, except where the template requires
5483 them. (eg. movzb) */
40fb9820
L		 5484 if (i.types[op].bitfield.reg8
5485 && (i.tm.operand_types[op].bitfield.reg16
5486 || i.tm.operand_types[op].bitfield.reg32
5487 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5488 {
a540244d
L		 5489 as_bad (_("`%s%s' not allowed with `%s%c'"),
5490 register_prefix,
29b0f896
AM		 5491 i.op[op].regs->reg_name,
5492 i.tm.name,
5493 i.suffix);
5494 return 0;
5495 }
e4630f71 5496 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5497 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5498 && i.types[op].bitfield.reg16
5499 && (i.tm.operand_types[op].bitfield.reg32
5500 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5501 {
5502 /* Prohibit these changes in the 64bit mode, since the
5503 lowering is more complicated. */
5504 if (flag_code == CODE_64BIT)
252b5132 5505 {
2b5d6a91 5506 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5507 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5508 i.suffix);
5509 return 0;
252b5132 5510 }
29b0f896 5511#if REGISTER_WARNINGS
cecf1424
JB		 5512 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5513 register_prefix,
5514 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5515 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5516#endif
252b5132 5517 }
e4630f71 5518 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5519 else if (i.types[op].bitfield.reg64
5520 && (i.tm.operand_types[op].bitfield.reg32
5521 || i.tm.operand_types[op].bitfield.acc))
252b5132 5522 {
34828aad 5523 if (intel_syntax
ca61edf2 5524 && i.tm.opcode_modifier.toqword
40fb9820 5525 && !i.types[0].bitfield.regxmm)
34828aad 5526 {
ca61edf2 5527 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5528 i.suffix = QWORD_MNEM_SUFFIX;
5529 }
5530 else
5531 {
2b5d6a91 5532 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5533 register_prefix, i.op[op].regs->reg_name,
5534 i.suffix);
5535 return 0;
5536 }
29b0f896
AM		 5537 }
5538 return 1;
5539}
252b5132 5540
29b0f896 5541static int
e3bb37b5 5542check_qword_reg (void)
29b0f896
AM		 5543{
5544 int op;
252b5132 5545
29b0f896
AM		 5546 for (op = i.operands; --op >= 0; )
5547 /* Reject eight bit registers, except where the template requires
5548 them. (eg. movzb) */
40fb9820
L		 5549 if (i.types[op].bitfield.reg8
5550 && (i.tm.operand_types[op].bitfield.reg16
5551 || i.tm.operand_types[op].bitfield.reg32
5552 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5553 {
a540244d
L		 5554 as_bad (_("`%s%s' not allowed with `%s%c'"),
5555 register_prefix,
29b0f896
AM		 5556 i.op[op].regs->reg_name,
5557 i.tm.name,
5558 i.suffix);
5559 return 0;
5560 }
e4630f71 5561 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5562 else if ((i.types[op].bitfield.reg16
5563 || i.types[op].bitfield.reg32)
5564 && (i.tm.operand_types[op].bitfield.reg32
5565 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5566 {
5567 /* Prohibit these changes in the 64bit mode, since the
5568 lowering is more complicated. */
34828aad 5569 if (intel_syntax
ca61edf2 5570 && i.tm.opcode_modifier.todword
40fb9820 5571 && !i.types[0].bitfield.regxmm)
34828aad 5572 {
ca61edf2 5573 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5574 i.suffix = LONG_MNEM_SUFFIX;
5575 }
5576 else
5577 {
2b5d6a91 5578 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5579 register_prefix, i.op[op].regs->reg_name,
5580 i.suffix);
5581 return 0;
5582 }
252b5132 5583 }
29b0f896
AM		 5584 return 1;
5585}
252b5132 5586
29b0f896 5587static int
e3bb37b5 5588check_word_reg (void)
29b0f896
AM		 5589{
5590 int op;
5591 for (op = i.operands; --op >= 0;)
5592 /* Reject eight bit registers, except where the template requires
5593 them. (eg. movzb) */
40fb9820
L		 5594 if (i.types[op].bitfield.reg8
5595 && (i.tm.operand_types[op].bitfield.reg16
5596 || i.tm.operand_types[op].bitfield.reg32
5597 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5598 {
a540244d
L		 5599 as_bad (_("`%s%s' not allowed with `%s%c'"),
5600 register_prefix,
29b0f896
AM		 5601 i.op[op].regs->reg_name,
5602 i.tm.name,
5603 i.suffix);
5604 return 0;
5605 }
e4630f71 5606 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5607 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5608 && (i.types[op].bitfield.reg32
5609 || i.types[op].bitfield.reg64)
40fb9820
L		 5610 && (i.tm.operand_types[op].bitfield.reg16
5611 || i.tm.operand_types[op].bitfield.acc))
252b5132 5612 {
29b0f896
AM		 5613 /* Prohibit these changes in the 64bit mode, since the
5614 lowering is more complicated. */
5615 if (flag_code == CODE_64BIT)
252b5132 5616 {
2b5d6a91 5617 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5618 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5619 i.suffix);
5620 return 0;
252b5132 5621 }
29b0f896 5622#if REGISTER_WARNINGS
cecf1424
JB		 5623 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5624 register_prefix,
5625 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5626 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5627#endif
5628 }
5629 return 1;
5630}
252b5132 5631
29b0f896 5632static int
40fb9820 5633update_imm (unsigned int j)
29b0f896 5634{
bc0844ae 5635 i386_operand_type overlap = i.types[j];
40fb9820
L		 5636 if ((overlap.bitfield.imm8
5637 || overlap.bitfield.imm8s
5638 || overlap.bitfield.imm16
5639 || overlap.bitfield.imm32
5640 || overlap.bitfield.imm32s
5641 || overlap.bitfield.imm64)
0dfbf9d7
L		 5642 && !operand_type_equal (&overlap, &imm8)
5643 && !operand_type_equal (&overlap, &imm8s)
5644 && !operand_type_equal (&overlap, &imm16)
5645 && !operand_type_equal (&overlap, &imm32)
5646 && !operand_type_equal (&overlap, &imm32s)
5647 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5648 {
5649 if (i.suffix)
5650 {
40fb9820
L		 5651 i386_operand_type temp;
5652
0dfbf9d7 5653 operand_type_set (&temp, 0);
7ab9ffdd 5654 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5655 {
5656 temp.bitfield.imm8 = overlap.bitfield.imm8;
5657 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5658 }
5659 else if (i.suffix == WORD_MNEM_SUFFIX)
5660 temp.bitfield.imm16 = overlap.bitfield.imm16;
5661 else if (i.suffix == QWORD_MNEM_SUFFIX)
5662 {
5663 temp.bitfield.imm64 = overlap.bitfield.imm64;
5664 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5665 }
5666 else
5667 temp.bitfield.imm32 = overlap.bitfield.imm32;
5668 overlap = temp;
29b0f896 5669 }
0dfbf9d7
L		 5670 else if (operand_type_equal (&overlap, &imm16_32_32s)
5671 || operand_type_equal (&overlap, &imm16_32)
5672 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5673 {
40fb9820 5674 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5675 overlap = imm16;
40fb9820 5676 else
65da13b5 5677 overlap = imm32s;
29b0f896 5678 }
0dfbf9d7
L		 5679 if (!operand_type_equal (&overlap, &imm8)
5680 && !operand_type_equal (&overlap, &imm8s)
5681 && !operand_type_equal (&overlap, &imm16)
5682 && !operand_type_equal (&overlap, &imm32)
5683 && !operand_type_equal (&overlap, &imm32s)
5684 && !operand_type_equal (&overlap, &imm64))
29b0f896 5685 {
4eed87de
AM		 5686 as_bad (_("no instruction mnemonic suffix given; "
5687 "can't determine immediate size"));
29b0f896
AM		 5688 return 0;
5689 }
5690 }
40fb9820 5691 i.types[j] = overlap;
29b0f896 5692
40fb9820
L		 5693 return 1;
5694}
5695
5696static int
5697finalize_imm (void)
5698{
bc0844ae 5699 unsigned int j, n;
29b0f896 5700
bc0844ae
L		 5701 /* Update the first 2 immediate operands. */
5702 n = i.operands > 2 ? 2 : i.operands;
5703 if (n)
5704 {
5705 for (j = 0; j < n; j++)
5706 if (update_imm (j) == 0)
5707 return 0;
40fb9820 5708
bc0844ae
L		 5709 /* The 3rd operand can't be immediate operand. */
5710 gas_assert (operand_type_check (i.types[2], imm) == 0);
5711 }
29b0f896
AM		 5712
5713 return 1;
5714}
5715
c0f3af97
L		 5716static int
5717bad_implicit_operand (int xmm)
5718{
91d6fa6a
NC		 5719 const char *ireg = xmm ? "xmm0" : "ymm0";
5720
c0f3af97
L		 5721 if (intel_syntax)
5722 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5723 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5724 else
5725 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5726 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5727 return 0;
5728}
5729
29b0f896 5730static int
e3bb37b5 5731process_operands (void)
29b0f896
AM		 5732{
5733 /* Default segment register this instruction will use for memory
5734 accesses. 0 means unknown. This is only for optimizing out
5735 unnecessary segment overrides. */
5736 const seg_entry *default_seg = 0;
5737
2426c15f 5738 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5739 {
91d6fa6a
NC		 5740 unsigned int dupl = i.operands;
5741 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5742 unsigned int j;
5743
c0f3af97 5744 /* The destination must be an xmm register. */
9c2799c2 5745 gas_assert (i.reg_operands
91d6fa6a 5746 && MAX_OPERANDS > dupl
7ab9ffdd 5747 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5748
5749 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5750 {
c0f3af97 5751 /* The first operand is implicit and must be xmm0. */
9c2799c2 5752 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5753 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5754 return bad_implicit_operand (1);
5755
8cd7925b 5756 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5757 {
5758 /* Keep xmm0 for instructions with VEX prefix and 3
5759 sources. */
5760 goto duplicate;
5761 }
e2ec9d29 5762 else
c0f3af97
L		 5763 {
5764 /* We remove the first xmm0 and keep the number of
5765 operands unchanged, which in fact duplicates the
5766 destination. */
5767 for (j = 1; j < i.operands; j++)
5768 {
5769 i.op[j - 1] = i.op[j];
5770 i.types[j - 1] = i.types[j];
5771 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5772 }
5773 }
5774 }
5775 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5776 {
91d6fa6a 5777 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5778 && (i.tm.opcode_modifier.vexsources
5779 == VEX3SOURCES));
c0f3af97
L		 5780
5781 /* Add the implicit xmm0 for instructions with VEX prefix
5782 and 3 sources. */
5783 for (j = i.operands; j > 0; j--)
5784 {
5785 i.op[j] = i.op[j - 1];
5786 i.types[j] = i.types[j - 1];
5787 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5788 }
5789 i.op[0].regs
5790 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5791 i.types[0] = regxmm;
c0f3af97
L		 5792 i.tm.operand_types[0] = regxmm;
5793
5794 i.operands += 2;
5795 i.reg_operands += 2;
5796 i.tm.operands += 2;
5797
91d6fa6a 5798 dupl++;
c0f3af97 5799 dest++;
91d6fa6a
NC		 5800 i.op[dupl] = i.op[dest];
5801 i.types[dupl] = i.types[dest];
5802 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5803 }
c0f3af97
L		 5804 else
5805 {
5806duplicate:
5807 i.operands++;
5808 i.reg_operands++;
5809 i.tm.operands++;
5810
91d6fa6a
NC		 5811 i.op[dupl] = i.op[dest];
5812 i.types[dupl] = i.types[dest];
5813 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5814 }
5815
5816 if (i.tm.opcode_modifier.immext)
5817 process_immext ();
5818 }
5819 else if (i.tm.opcode_modifier.firstxmm0)
5820 {
5821 unsigned int j;
5822
43234a1e 5823 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5824 gas_assert (i.reg_operands
7ab9ffdd 5825 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5826 || operand_type_equal (&i.types[0], &regymm)
5827 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5828 if (register_number (i.op[0].regs) != 0)
c0f3af97 5829 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5830
5831 for (j = 1; j < i.operands; j++)
5832 {
5833 i.op[j - 1] = i.op[j];
5834 i.types[j - 1] = i.types[j];
5835
5836 /* We need to adjust fields in i.tm since they are used by
5837 build_modrm_byte. */
5838 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5839 }
5840
e2ec9d29
L		 5841 i.operands--;
5842 i.reg_operands--;
e2ec9d29
L		 5843 i.tm.operands--;
5844 }
5845 else if (i.tm.opcode_modifier.regkludge)
5846 {
5847 /* The imul $imm, %reg instruction is converted into
5848 imul $imm, %reg, %reg, and the clr %reg instruction
5849 is converted into xor %reg, %reg. */
5850
5851 unsigned int first_reg_op;
5852
5853 if (operand_type_check (i.types[0], reg))
5854 first_reg_op = 0;
5855 else
5856 first_reg_op = 1;
5857 /* Pretend we saw the extra register operand. */
9c2799c2 5858 gas_assert (i.reg_operands == 1
7ab9ffdd 5859 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5860 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5861 i.types[first_reg_op + 1] = i.types[first_reg_op];
5862 i.operands++;
5863 i.reg_operands++;
29b0f896
AM		 5864 }
5865
40fb9820 5866 if (i.tm.opcode_modifier.shortform)
29b0f896 5867 {
40fb9820
L		 5868 if (i.types[0].bitfield.sreg2
5869 || i.types[0].bitfield.sreg3)
29b0f896 5870 {
4eed87de
AM		 5871 if (i.tm.base_opcode == POP_SEG_SHORT
5872 && i.op[0].regs->reg_num == 1)
29b0f896 5873 {
a87af027 5874 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5875 return 0;
29b0f896 5876 }
4eed87de
AM		 5877 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5878 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5879 i.rex |= REX_B;
4eed87de
AM		 5880 }
5881 else
5882 {
7ab9ffdd 5883 /* The register or float register operand is in operand
85f10a01 5884 0 or 1. */
40fb9820 5885 unsigned int op;
7ab9ffdd
L		 5886
5887 if (i.types[0].bitfield.floatreg
5888 || operand_type_check (i.types[0], reg))
5889 op = 0;
5890 else
5891 op = 1;
4eed87de
AM		 5892 /* Register goes in low 3 bits of opcode. */
5893 i.tm.base_opcode |= i.op[op].regs->reg_num;
5894 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5895 i.rex |= REX_B;
40fb9820 5896 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5897 {
4eed87de
AM		 5898 /* Warn about some common errors, but press on regardless.
5899 The first case can be generated by gcc (<= 2.8.1). */
5900 if (i.operands == 2)
5901 {
5902 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5903 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5904 register_prefix, i.op[!intel_syntax].regs->reg_name,
5905 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5906 }
5907 else
5908 {
5909 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5910 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5911 register_prefix, i.op[0].regs->reg_name);
4eed87de 5912 }
29b0f896
AM		 5913 }
5914 }
5915 }
40fb9820 5916 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5917 {
5918 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5919 must be put into the modrm byte). Now, we make the modrm and
5920 index base bytes based on all the info we've collected. */
29b0f896
AM		 5921
5922 default_seg = build_modrm_byte ();
5923 }
8a2ed489 5924 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5925 {
5926 default_seg = &ds;
5927 }
40fb9820 5928 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5929 {
5930 /* For the string instructions that allow a segment override
5931 on one of their operands, the default segment is ds. */
5932 default_seg = &ds;
5933 }
5934
75178d9d
L		 5935 if (i.tm.base_opcode == 0x8d /* lea */
5936 && i.seg[0]
5937 && !quiet_warnings)
30123838 5938 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5939
5940 /* If a segment was explicitly specified, and the specified segment
5941 is not the default, use an opcode prefix to select it. If we
5942 never figured out what the default segment is, then default_seg
5943 will be zero at this point, and the specified segment prefix will
5944 always be used. */
29b0f896
AM		 5945 if ((i.seg[0]) && (i.seg[0] != default_seg))
5946 {
5947 if (!add_prefix (i.seg[0]->seg_prefix))
5948 return 0;
5949 }
5950 return 1;
5951}
5952
5953static const seg_entry *
e3bb37b5 5954build_modrm_byte (void)
29b0f896
AM		 5955{
5956 const seg_entry *default_seg = 0;
c0f3af97 5957 unsigned int source, dest;
8cd7925b 5958 int vex_3_sources;
c0f3af97
L		 5959
5960 /* The first operand of instructions with VEX prefix and 3 sources
5961 must be VEX_Imm4. */
8cd7925b 5962 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5963 if (vex_3_sources)
5964 {
91d6fa6a 5965 unsigned int nds, reg_slot;
4c2c6516 5966 expressionS *exp;
c0f3af97 5967
922d8de8 5968 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5969 && i.tm.opcode_modifier.immext)
5970 {
5971 dest = i.operands - 2;
5972 gas_assert (dest == 3);
5973 }
922d8de8 5974 else
a683cc34 5975 dest = i.operands - 1;
c0f3af97 5976 nds = dest - 1;
922d8de8 5977
a683cc34
SP		 5978 /* There are 2 kinds of instructions:
5979 1. 5 operands: 4 register operands or 3 register operands
5980 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 5981 VexW0 or VexW1. The destination must be either XMM, YMM or
5982 ZMM register.
a683cc34
SP		 5983 2. 4 operands: 4 register operands or 3 register operands
5984 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5985 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5986 || (i.reg_operands == 3 && i.mem_operands == 1))
5987 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5988 && (i.tm.opcode_modifier.veximmext
5989 || (i.imm_operands == 1
5990 && i.types[0].bitfield.vec_imm4
5991 && (i.tm.opcode_modifier.vexw == VEXW0
5992 || i.tm.opcode_modifier.vexw == VEXW1)
5993 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 5994 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
5995 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 5996
5997 if (i.imm_operands == 0)
5998 {
5999 /* When there is no immediate operand, generate an 8bit
6000 immediate operand to encode the first operand. */
6001 exp = &im_expressions[i.imm_operands++];
6002 i.op[i.operands].imms = exp;
6003 i.types[i.operands] = imm8;
6004 i.operands++;
6005 /* If VexW1 is set, the first operand is the source and
6006 the second operand is encoded in the immediate operand. */
6007 if (i.tm.opcode_modifier.vexw == VEXW1)
6008 {
6009 source = 0;
6010 reg_slot = 1;
6011 }
6012 else
6013 {
6014 source = 1;
6015 reg_slot = 0;
6016 }
6017
6018 /* FMA swaps REG and NDS. */
6019 if (i.tm.cpu_flags.bitfield.cpufma)
6020 {
6021 unsigned int tmp;
6022 tmp = reg_slot;
6023 reg_slot = nds;
6024 nds = tmp;
6025 }
6026
24981e7b
L		 6027 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6028 &regxmm)
a683cc34 6029 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6030 &regymm)
6031 || operand_type_equal (&i.tm.operand_types[reg_slot],
6032 &regzmm));
a683cc34 6033 exp->X_op = O_constant;
4c692bc7 6034 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6035 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6036 }
922d8de8 6037 else
a683cc34
SP		 6038 {
6039 unsigned int imm_slot;
6040
6041 if (i.tm.opcode_modifier.vexw == VEXW0)
6042 {
6043 /* If VexW0 is set, the third operand is the source and
6044 the second operand is encoded in the immediate
6045 operand. */
6046 source = 2;
6047 reg_slot = 1;
6048 }
6049 else
6050 {
6051 /* VexW1 is set, the second operand is the source and
6052 the third operand is encoded in the immediate
6053 operand. */
6054 source = 1;
6055 reg_slot = 2;
6056 }
6057
6058 if (i.tm.opcode_modifier.immext)
6059 {
6060 /* When ImmExt is set, the immdiate byte is the last
6061 operand. */
6062 imm_slot = i.operands - 1;
6063 source--;
6064 reg_slot--;
6065 }
6066 else
6067 {
6068 imm_slot = 0;
6069
6070 /* Turn on Imm8 so that output_imm will generate it. */
6071 i.types[imm_slot].bitfield.imm8 = 1;
6072 }
6073
24981e7b
L		 6074 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6075 &regxmm)
6076 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6077 &regymm)
6078 || operand_type_equal (&i.tm.operand_types[reg_slot],
6079 &regzmm));
a683cc34 6080 i.op[imm_slot].imms->X_add_number
4c692bc7 6081 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6082 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6083 }
6084
6085 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6086 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6087 &regymm)
6088 || operand_type_equal (&i.tm.operand_types[nds],
6089 &regzmm));
dae39acc 6090 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6091 }
6092 else
6093 source = dest = 0;
29b0f896
AM		 6094
6095 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6096 implicit registers do not count. If there are 3 register
6097 operands, it must be a instruction with VexNDS. For a
6098 instruction with VexNDD, the destination register is encoded
6099 in VEX prefix. If there are 4 register operands, it must be
6100 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6101 if (i.mem_operands == 0
6102 && ((i.reg_operands == 2
2426c15f 6103 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6104 || (i.reg_operands == 3
2426c15f 6105 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6106 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6107 {
cab737b9
L		 6108 switch (i.operands)
6109 {
6110 case 2:
6111 source = 0;
6112 break;
6113 case 3:
c81128dc
L		 6114 /* When there are 3 operands, one of them may be immediate,
6115 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6116 the first operand must be shift count register (cl) or it
6117 is an instruction with VexNDS. */
9c2799c2 6118 gas_assert (i.imm_operands == 1
7ab9ffdd 6119 || (i.imm_operands == 0
2426c15f 6120 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6121 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6122 if (operand_type_check (i.types[0], imm)
6123 || i.types[0].bitfield.shiftcount)
6124 source = 1;
6125 else
6126 source = 0;
cab737b9
L		 6127 break;
6128 case 4:
368d64cc
L		 6129 /* When there are 4 operands, the first two must be 8bit
6130 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6131 one.
6132
6133 For instructions with VexNDS, if the first operand
6134 an imm8, the source operand is the 2nd one. If the last
6135 operand is imm8, the source operand is the first one. */
9c2799c2 6136 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6137 && i.types[0].bitfield.imm8
6138 && i.types[1].bitfield.imm8)
2426c15f 6139 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6140 && i.imm_operands == 1
6141 && (i.types[0].bitfield.imm8
43234a1e
L		 6142 || i.types[i.operands - 1].bitfield.imm8
6143 || i.rounding)));
9f2670f2
L		 6144 if (i.imm_operands == 2)
6145 source = 2;
6146 else
c0f3af97
L		 6147 {
6148 if (i.types[0].bitfield.imm8)
6149 source = 1;
6150 else
6151 source = 0;
6152 }
c0f3af97
L		 6153 break;
6154 case 5:
43234a1e
L		 6155 if (i.tm.opcode_modifier.evex)
6156 {
6157 /* For EVEX instructions, when there are 5 operands, the
6158 first one must be immediate operand. If the second one
6159 is immediate operand, the source operand is the 3th
6160 one. If the last one is immediate operand, the source
6161 operand is the 2nd one. */
6162 gas_assert (i.imm_operands == 2
6163 && i.tm.opcode_modifier.sae
6164 && operand_type_check (i.types[0], imm));
6165 if (operand_type_check (i.types[1], imm))
6166 source = 2;
6167 else if (operand_type_check (i.types[4], imm))
6168 source = 1;
6169 else
6170 abort ();
6171 }
cab737b9
L		 6172 break;
6173 default:
6174 abort ();
6175 }
6176
c0f3af97
L		 6177 if (!vex_3_sources)
6178 {
6179 dest = source + 1;
6180
43234a1e
L		 6181 /* RC/SAE operand could be between DEST and SRC. That happens
6182 when one operand is GPR and the other one is XMM/YMM/ZMM
6183 register. */
6184 if (i.rounding && i.rounding->operand == (int) dest)
6185 dest++;
6186
2426c15f 6187 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6188 {
43234a1e
L		 6189 /* For instructions with VexNDS, the register-only source
6190 operand must be 32/64bit integer, XMM, YMM or ZMM
6191 register. It is encoded in VEX prefix. We need to
6192 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6193
6194 i386_operand_type op;
6195 unsigned int vvvv;
6196
6197 /* Check register-only source operand when two source
6198 operands are swapped. */
6199 if (!i.tm.operand_types[source].bitfield.baseindex
6200 && i.tm.operand_types[dest].bitfield.baseindex)
6201 {
6202 vvvv = source;
6203 source = dest;
6204 }
6205 else
6206 vvvv = dest;
6207
6208 op = i.tm.operand_types[vvvv];
fa99fab2 6209 op.bitfield.regmem = 0;
c0f3af97 6210 if ((dest + 1) >= i.operands
ac4eb736
AM		 6211 || (!op.bitfield.reg32
6212 && op.bitfield.reg64
f12dc422 6213 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6214 && !operand_type_equal (&op, &regymm)
6215 && !operand_type_equal (&op, &regzmm)
6216 && !operand_type_equal (&op, &regmask)))
c0f3af97 6217 abort ();
f12dc422 6218 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6219 dest++;
6220 }
6221 }
29b0f896
AM		 6222
6223 i.rm.mode = 3;
6224 /* One of the register operands will be encoded in the i.tm.reg
6225 field, the other in the combined i.tm.mode and i.tm.regmem
6226 fields. If no form of this instruction supports a memory
6227 destination operand, then we assume the source operand may
6228 sometimes be a memory operand and so we need to store the
6229 destination in the i.rm.reg field. */
40fb9820
L		 6230 if (!i.tm.operand_types[dest].bitfield.regmem
6231 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6232 {
6233 i.rm.reg = i.op[dest].regs->reg_num;
6234 i.rm.regmem = i.op[source].regs->reg_num;
6235 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6236 i.rex |= REX_R;
43234a1e
L		 6237 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6238 i.vrex |= REX_R;
29b0f896 6239 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6240 i.rex |= REX_B;
43234a1e
L		 6241 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6242 i.vrex |= REX_B;
29b0f896
AM		 6243 }
6244 else
6245 {
6246 i.rm.reg = i.op[source].regs->reg_num;
6247 i.rm.regmem = i.op[dest].regs->reg_num;
6248 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6249 i.rex |= REX_B;
43234a1e
L		 6250 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6251 i.vrex |= REX_B;
29b0f896 6252 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6253 i.rex |= REX_R;
43234a1e
L		 6254 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6255 i.vrex |= REX_R;
29b0f896 6256 }
161a04f6 6257 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6258 {
40fb9820
L		 6259 if (!i.types[0].bitfield.control
6260 && !i.types[1].bitfield.control)
c4a530c5 6261 abort ();
161a04f6 6262 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6263 add_prefix (LOCK_PREFIX_OPCODE);
6264 }
29b0f896
AM		 6265 }
6266 else
6267 { /* If it's not 2 reg operands... */
c0f3af97
L		 6268 unsigned int mem;
6269
29b0f896
AM		 6270 if (i.mem_operands)
6271 {
6272 unsigned int fake_zero_displacement = 0;
99018f42 6273 unsigned int op;
4eed87de 6274
7ab9ffdd
L		 6275 for (op = 0; op < i.operands; op++)
6276 if (operand_type_check (i.types[op], anymem))
6277 break;
7ab9ffdd 6278 gas_assert (op < i.operands);
29b0f896 6279
6c30d220
L		 6280 if (i.tm.opcode_modifier.vecsib)
6281 {
6282 if (i.index_reg->reg_num == RegEiz
6283 || i.index_reg->reg_num == RegRiz)
6284 abort ();
6285
6286 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6287 if (!i.base_reg)
6288 {
6289 i.sib.base = NO_BASE_REGISTER;
6290 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6291 /* No Vec_Disp8 if there is no base. */
6292 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6293 i.types[op].bitfield.disp8 = 0;
6294 i.types[op].bitfield.disp16 = 0;
6295 i.types[op].bitfield.disp64 = 0;
6296 if (flag_code != CODE_64BIT)
6297 {
6298 /* Must be 32 bit */
6299 i.types[op].bitfield.disp32 = 1;
6300 i.types[op].bitfield.disp32s = 0;
6301 }
6302 else
6303 {
6304 i.types[op].bitfield.disp32 = 0;
6305 i.types[op].bitfield.disp32s = 1;
6306 }
6307 }
6308 i.sib.index = i.index_reg->reg_num;
6309 if ((i.index_reg->reg_flags & RegRex) != 0)
6310 i.rex |= REX_X;
43234a1e
L		 6311 if ((i.index_reg->reg_flags & RegVRex) != 0)
6312 i.vrex |= REX_X;
6c30d220
L		 6313 }
6314
29b0f896
AM		 6315 default_seg = &ds;
6316
6317 if (i.base_reg == 0)
6318 {
6319 i.rm.mode = 0;
6320 if (!i.disp_operands)
6c30d220
L		 6321 {
6322 fake_zero_displacement = 1;
6323 /* Instructions with VSIB byte need 32bit displacement
6324 if there is no base register. */
6325 if (i.tm.opcode_modifier.vecsib)
6326 i.types[op].bitfield.disp32 = 1;
6327 }
29b0f896
AM		 6328 if (i.index_reg == 0)
6329 {
6c30d220 6330 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6331 /* Operand is just <disp> */
20f0a1fc 6332 if (flag_code == CODE_64BIT)
29b0f896
AM		 6333 {
6334 /* 64bit mode overwrites the 32bit absolute
6335 addressing by RIP relative addressing and
6336 absolute addressing is encoded by one of the
6337 redundant SIB forms. */
6338 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6339 i.sib.base = NO_BASE_REGISTER;
6340 i.sib.index = NO_INDEX_REGISTER;
fc225355 6341 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6342 ? disp32s : disp32);
20f0a1fc 6343 }
fc225355
L		 6344 else if ((flag_code == CODE_16BIT)
6345 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6346 {
6347 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6348 i.types[op] = disp16;
20f0a1fc
NC		 6349 }
6350 else
6351 {
6352 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6353 i.types[op] = disp32;
29b0f896
AM		 6354 }
6355 }
6c30d220 6356 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6357 {
6c30d220 6358 /* !i.base_reg && i.index_reg */
db51cc60
L		 6359 if (i.index_reg->reg_num == RegEiz
6360 || i.index_reg->reg_num == RegRiz)
6361 i.sib.index = NO_INDEX_REGISTER;
6362 else
6363 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6364 i.sib.base = NO_BASE_REGISTER;
6365 i.sib.scale = i.log2_scale_factor;
6366 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6367 /* No Vec_Disp8 if there is no base. */
6368 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6369 i.types[op].bitfield.disp8 = 0;
6370 i.types[op].bitfield.disp16 = 0;
6371 i.types[op].bitfield.disp64 = 0;
29b0f896 6372 if (flag_code != CODE_64BIT)
40fb9820
L		 6373 {
6374 /* Must be 32 bit */
6375 i.types[op].bitfield.disp32 = 1;
6376 i.types[op].bitfield.disp32s = 0;
6377 }
29b0f896 6378 else
40fb9820
L		 6379 {
6380 i.types[op].bitfield.disp32 = 0;
6381 i.types[op].bitfield.disp32s = 1;
6382 }
29b0f896 6383 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6384 i.rex |= REX_X;
29b0f896
AM		 6385 }
6386 }
6387 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6388 else if (i.base_reg->reg_num == RegRip ||
6389 i.base_reg->reg_num == RegEip)
29b0f896 6390 {
6c30d220 6391 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6392 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6393 i.types[op].bitfield.disp8 = 0;
6394 i.types[op].bitfield.disp16 = 0;
6395 i.types[op].bitfield.disp32 = 0;
6396 i.types[op].bitfield.disp32s = 1;
6397 i.types[op].bitfield.disp64 = 0;
43234a1e 6398 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6399 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6400 if (! i.disp_operands)
6401 fake_zero_displacement = 1;
29b0f896 6402 }
40fb9820 6403 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6404 {
6c30d220 6405 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6406 switch (i.base_reg->reg_num)
6407 {
6408 case 3: /* (%bx) */
6409 if (i.index_reg == 0)
6410 i.rm.regmem = 7;
6411 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6412 i.rm.regmem = i.index_reg->reg_num - 6;
6413 break;
6414 case 5: /* (%bp) */
6415 default_seg = &ss;
6416 if (i.index_reg == 0)
6417 {
6418 i.rm.regmem = 6;
40fb9820 6419 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6420 {
6421 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6422 if (i.tm.operand_types[op].bitfield.vec_disp8)
6423 i.types[op].bitfield.vec_disp8 = 1;
6424 else
6425 i.types[op].bitfield.disp8 = 1;
252b5132 6426 fake_zero_displacement = 1;
29b0f896
AM		 6427 }
6428 }
6429 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6430 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6431 break;
6432 default: /* (%si) -> 4 or (%di) -> 5 */
6433 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6434 }
6435 i.rm.mode = mode_from_disp_size (i.types[op]);
6436 }
6437 else /* i.base_reg and 32/64 bit mode */
6438 {
6439 if (flag_code == CODE_64BIT
40fb9820
L		 6440 && operand_type_check (i.types[op], disp))
6441 {
6442 i386_operand_type temp;
0dfbf9d7 6443 operand_type_set (&temp, 0);
40fb9820 6444 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6445 temp.bitfield.vec_disp8
6446 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6447 i.types[op] = temp;
6448 if (i.prefix[ADDR_PREFIX] == 0)
6449 i.types[op].bitfield.disp32s = 1;
6450 else
6451 i.types[op].bitfield.disp32 = 1;
6452 }
20f0a1fc 6453
6c30d220
L		 6454 if (!i.tm.opcode_modifier.vecsib)
6455 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6456 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6457 i.rex |= REX_B;
29b0f896
AM		 6458 i.sib.base = i.base_reg->reg_num;
6459 /* x86-64 ignores REX prefix bit here to avoid decoder
6460 complications. */
848930b2
JB		 6461 if (!(i.base_reg->reg_flags & RegRex)
6462 && (i.base_reg->reg_num == EBP_REG_NUM
6463 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6464 default_seg = &ss;
848930b2 6465 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6466 {
848930b2 6467 fake_zero_displacement = 1;
43234a1e
L		 6468 if (i.tm.operand_types [op].bitfield.vec_disp8)
6469 i.types[op].bitfield.vec_disp8 = 1;
6470 else
6471 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6472 }
6473 i.sib.scale = i.log2_scale_factor;
6474 if (i.index_reg == 0)
6475 {
6c30d220 6476 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6477 /* <disp>(%esp) becomes two byte modrm with no index
6478 register. We've already stored the code for esp
6479 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6480 Any base register besides %esp will not use the
6481 extra modrm byte. */
6482 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6483 }
6c30d220 6484 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6485 {
db51cc60
L		 6486 if (i.index_reg->reg_num == RegEiz
6487 || i.index_reg->reg_num == RegRiz)
6488 i.sib.index = NO_INDEX_REGISTER;
6489 else
6490 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6491 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6492 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6493 i.rex |= REX_X;
29b0f896 6494 }
67a4f2b7
AO		 6495
6496 if (i.disp_operands
6497 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6498 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6499 i.rm.mode = 0;
6500 else
a501d77e
L		 6501 {
6502 if (!fake_zero_displacement
6503 && !i.disp_operands
6504 && i.disp_encoding)
6505 {
6506 fake_zero_displacement = 1;
6507 if (i.disp_encoding == disp_encoding_8bit)
6508 i.types[op].bitfield.disp8 = 1;
6509 else
6510 i.types[op].bitfield.disp32 = 1;
6511 }
6512 i.rm.mode = mode_from_disp_size (i.types[op]);
6513 }
29b0f896 6514 }
252b5132 6515
29b0f896
AM		 6516 if (fake_zero_displacement)
6517 {
6518 /* Fakes a zero displacement assuming that i.types[op]
6519 holds the correct displacement size. */
6520 expressionS *exp;
6521
9c2799c2 6522 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6523 exp = &disp_expressions[i.disp_operands++];
6524 i.op[op].disps = exp;
6525 exp->X_op = O_constant;
6526 exp->X_add_number = 0;
6527 exp->X_add_symbol = (symbolS *) 0;
6528 exp->X_op_symbol = (symbolS *) 0;
6529 }
c0f3af97
L		 6530
6531 mem = op;
29b0f896 6532 }
c0f3af97
L		 6533 else
6534 mem = ~0;
252b5132 6535
8c43a48b 6536 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6537 {
6538 if (operand_type_check (i.types[0], imm))
6539 i.vex.register_specifier = NULL;
6540 else
6541 {
6542 /* VEX.vvvv encodes one of the sources when the first
6543 operand is not an immediate. */
1ef99a7b 6544 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6545 i.vex.register_specifier = i.op[0].regs;
6546 else
6547 i.vex.register_specifier = i.op[1].regs;
6548 }
6549
6550 /* Destination is a XMM register encoded in the ModRM.reg
6551 and VEX.R bit. */
6552 i.rm.reg = i.op[2].regs->reg_num;
6553 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6554 i.rex |= REX_R;
6555
6556 /* ModRM.rm and VEX.B encodes the other source. */
6557 if (!i.mem_operands)
6558 {
6559 i.rm.mode = 3;
6560
1ef99a7b 6561 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6562 i.rm.regmem = i.op[1].regs->reg_num;
6563 else
6564 i.rm.regmem = i.op[0].regs->reg_num;
6565
6566 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6567 i.rex |= REX_B;
6568 }
6569 }
2426c15f 6570 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6571 {
6572 i.vex.register_specifier = i.op[2].regs;
6573 if (!i.mem_operands)
6574 {
6575 i.rm.mode = 3;
6576 i.rm.regmem = i.op[1].regs->reg_num;
6577 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6578 i.rex |= REX_B;
6579 }
6580 }
29b0f896
AM		 6581 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6582 (if any) based on i.tm.extension_opcode. Again, we must be
6583 careful to make sure that segment/control/debug/test/MMX
6584 registers are coded into the i.rm.reg field. */
f88c9eb0 6585 else if (i.reg_operands)
29b0f896 6586 {
99018f42 6587 unsigned int op;
7ab9ffdd
L		 6588 unsigned int vex_reg = ~0;
6589
6590 for (op = 0; op < i.operands; op++)
6591 if (i.types[op].bitfield.reg8
6592 || i.types[op].bitfield.reg16
6593 || i.types[op].bitfield.reg32
6594 || i.types[op].bitfield.reg64
6595 || i.types[op].bitfield.regmmx
6596 || i.types[op].bitfield.regxmm
6597 || i.types[op].bitfield.regymm
7e8b059b 6598 || i.types[op].bitfield.regbnd
43234a1e
L		 6599 || i.types[op].bitfield.regzmm
6600 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6601 || i.types[op].bitfield.sreg2
6602 || i.types[op].bitfield.sreg3
6603 || i.types[op].bitfield.control
6604 || i.types[op].bitfield.debug
6605 || i.types[op].bitfield.test)
6606 break;
c0209578 6607
7ab9ffdd
L		 6608 if (vex_3_sources)
6609 op = dest;
2426c15f 6610 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6611 {
6612 /* For instructions with VexNDS, the register-only
6613 source operand is encoded in VEX prefix. */
6614 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6615
7ab9ffdd 6616 if (op > mem)
c0f3af97 6617 {
7ab9ffdd
L		 6618 vex_reg = op++;
6619 gas_assert (op < i.operands);
c0f3af97
L		 6620 }
6621 else
c0f3af97 6622 {
f12dc422
L		 6623 /* Check register-only source operand when two source
6624 operands are swapped. */
6625 if (!i.tm.operand_types[op].bitfield.baseindex
6626 && i.tm.operand_types[op + 1].bitfield.baseindex)
6627 {
6628 vex_reg = op;
6629 op += 2;
6630 gas_assert (mem == (vex_reg + 1)
6631 && op < i.operands);
6632 }
6633 else
6634 {
6635 vex_reg = op + 1;
6636 gas_assert (vex_reg < i.operands);
6637 }
c0f3af97 6638 }
7ab9ffdd 6639 }
2426c15f 6640 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6641 {
f12dc422 6642 /* For instructions with VexNDD, the register destination
7ab9ffdd 6643 is encoded in VEX prefix. */
f12dc422
L		 6644 if (i.mem_operands == 0)
6645 {
6646 /* There is no memory operand. */
6647 gas_assert ((op + 2) == i.operands);
6648 vex_reg = op + 1;
6649 }
6650 else
8d63c93e 6651 {
f12dc422
L		 6652 /* There are only 2 operands. */
6653 gas_assert (op < 2 && i.operands == 2);
6654 vex_reg = 1;
6655 }
7ab9ffdd
L		 6656 }
6657 else
6658 gas_assert (op < i.operands);
99018f42 6659
7ab9ffdd
L		 6660 if (vex_reg != (unsigned int) ~0)
6661 {
f12dc422 6662 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6663
f12dc422
L		 6664 if (type->bitfield.reg32 != 1
6665 && type->bitfield.reg64 != 1
6666 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6667 && !operand_type_equal (type, &regymm)
6668 && !operand_type_equal (type, &regzmm)
6669 && !operand_type_equal (type, &regmask))
7ab9ffdd 6670 abort ();
f88c9eb0 6671
7ab9ffdd
L		 6672 i.vex.register_specifier = i.op[vex_reg].regs;
6673 }
6674
1b9f0c97
L		 6675 /* Don't set OP operand twice. */
6676 if (vex_reg != op)
7ab9ffdd 6677 {
1b9f0c97
L		 6678 /* If there is an extension opcode to put here, the
6679 register number must be put into the regmem field. */
6680 if (i.tm.extension_opcode != None)
6681 {
6682 i.rm.regmem = i.op[op].regs->reg_num;
6683 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6684 i.rex |= REX_B;
43234a1e
L		 6685 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6686 i.vrex |= REX_B;
1b9f0c97
L		 6687 }
6688 else
6689 {
6690 i.rm.reg = i.op[op].regs->reg_num;
6691 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6692 i.rex |= REX_R;
43234a1e
L		 6693 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6694 i.vrex |= REX_R;
1b9f0c97 6695 }
7ab9ffdd 6696 }
252b5132 6697
29b0f896
AM		 6698 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6699 must set it to 3 to indicate this is a register operand
6700 in the regmem field. */
6701 if (!i.mem_operands)
6702 i.rm.mode = 3;
6703 }
252b5132 6704
29b0f896 6705 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6706 if (i.tm.extension_opcode != None)
29b0f896
AM		 6707 i.rm.reg = i.tm.extension_opcode;
6708 }
6709 return default_seg;
6710}
252b5132 6711
29b0f896 6712static void
e3bb37b5 6713output_branch (void)
29b0f896
AM		 6714{
6715 char *p;
f8a5c266 6716 int size;
29b0f896
AM		 6717 int code16;
6718 int prefix;
6719 relax_substateT subtype;
6720 symbolS *sym;
6721 offsetT off;
6722
f8a5c266 6723 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6724 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6725
6726 prefix = 0;
6727 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6728 {
29b0f896
AM		 6729 prefix = 1;
6730 i.prefixes -= 1;
6731 code16 ^= CODE16;
252b5132 6732 }
29b0f896
AM		 6733 /* Pentium4 branch hints. */
6734 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6735 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6736 {
29b0f896
AM		 6737 prefix++;
6738 i.prefixes--;
6739 }
6740 if (i.prefix[REX_PREFIX] != 0)
6741 {
6742 prefix++;
6743 i.prefixes--;
2f66722d
AM		 6744 }
6745
7e8b059b
L		 6746 /* BND prefixed jump. */
6747 if (i.prefix[BND_PREFIX] != 0)
6748 {
6749 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6750 i.prefixes -= 1;
6751 }
6752
29b0f896
AM		 6753 if (i.prefixes != 0 && !intel_syntax)
6754 as_warn (_("skipping prefixes on this instruction"));
6755
6756 /* It's always a symbol; End frag & setup for relax.
6757 Make sure there is enough room in this frag for the largest
6758 instruction we may generate in md_convert_frag. This is 2
6759 bytes for the opcode and room for the prefix and largest
6760 displacement. */
6761 frag_grow (prefix + 2 + 4);
6762 /* Prefix and 1 opcode byte go in fr_fix. */
6763 p = frag_more (prefix + 1);
6764 if (i.prefix[DATA_PREFIX] != 0)
6765 *p++ = DATA_PREFIX_OPCODE;
6766 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6767 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6768 *p++ = i.prefix[SEG_PREFIX];
6769 if (i.prefix[REX_PREFIX] != 0)
6770 *p++ = i.prefix[REX_PREFIX];
6771 *p = i.tm.base_opcode;
6772
6773 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6774 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6775 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6776 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6777 else
f8a5c266 6778 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6779 subtype |= code16;
3e73aa7c 6780
29b0f896
AM		 6781 sym = i.op[0].disps->X_add_symbol;
6782 off = i.op[0].disps->X_add_number;
3e73aa7c 6783
29b0f896
AM		 6784 if (i.op[0].disps->X_op != O_constant
6785 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6786 {
29b0f896
AM		 6787 /* Handle complex expressions. */
6788 sym = make_expr_symbol (i.op[0].disps);
6789 off = 0;
6790 }
3e73aa7c 6791
29b0f896
AM		 6792 /* 1 possible extra opcode + 4 byte displacement go in var part.
6793 Pass reloc in fr_var. */
d258b828 6794 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 6795}
3e73aa7c 6796
29b0f896 6797static void
e3bb37b5 6798output_jump (void)
29b0f896
AM		 6799{
6800 char *p;
6801 int size;
3e02c1cc 6802 fixS *fixP;
29b0f896 6803
40fb9820 6804 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6805 {
6806 /* This is a loop or jecxz type instruction. */
6807 size = 1;
6808 if (i.prefix[ADDR_PREFIX] != 0)
6809 {
6810 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6811 i.prefixes -= 1;
6812 }
6813 /* Pentium4 branch hints. */
6814 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6815 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6816 {
6817 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6818 i.prefixes--;
3e73aa7c
JH		 6819 }
6820 }
29b0f896
AM		 6821 else
6822 {
6823 int code16;
3e73aa7c 6824
29b0f896
AM		 6825 code16 = 0;
6826 if (flag_code == CODE_16BIT)
6827 code16 = CODE16;
3e73aa7c 6828
29b0f896
AM		 6829 if (i.prefix[DATA_PREFIX] != 0)
6830 {
6831 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6832 i.prefixes -= 1;
6833 code16 ^= CODE16;
6834 }
252b5132 6835
29b0f896
AM		 6836 size = 4;
6837 if (code16)
6838 size = 2;
6839 }
9fcc94b6 6840
29b0f896
AM		 6841 if (i.prefix[REX_PREFIX] != 0)
6842 {
6843 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6844 i.prefixes -= 1;
6845 }
252b5132 6846
7e8b059b
L		 6847 /* BND prefixed jump. */
6848 if (i.prefix[BND_PREFIX] != 0)
6849 {
6850 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6851 i.prefixes -= 1;
6852 }
6853
29b0f896
AM		 6854 if (i.prefixes != 0 && !intel_syntax)
6855 as_warn (_("skipping prefixes on this instruction"));
e0890092 6856
42164a71
L		 6857 p = frag_more (i.tm.opcode_length + size);
6858 switch (i.tm.opcode_length)
6859 {
6860 case 2:
6861 *p++ = i.tm.base_opcode >> 8;
6862 case 1:
6863 *p++ = i.tm.base_opcode;
6864 break;
6865 default:
6866 abort ();
6867 }
e0890092 6868
3e02c1cc 6869 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6870 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 6871
6872 /* All jumps handled here are signed, but don't use a signed limit
6873 check for 32 and 16 bit jumps as we want to allow wrap around at
6874 4G and 64k respectively. */
6875 if (size == 1)
6876 fixP->fx_signed = 1;
29b0f896 6877}
e0890092 6878
29b0f896 6879static void
e3bb37b5 6880output_interseg_jump (void)
29b0f896
AM		 6881{
6882 char *p;
6883 int size;
6884 int prefix;
6885 int code16;
252b5132 6886
29b0f896
AM		 6887 code16 = 0;
6888 if (flag_code == CODE_16BIT)
6889 code16 = CODE16;
a217f122 6890
29b0f896
AM		 6891 prefix = 0;
6892 if (i.prefix[DATA_PREFIX] != 0)
6893 {
6894 prefix = 1;
6895 i.prefixes -= 1;
6896 code16 ^= CODE16;
6897 }
6898 if (i.prefix[REX_PREFIX] != 0)
6899 {
6900 prefix++;
6901 i.prefixes -= 1;
6902 }
252b5132 6903
29b0f896
AM		 6904 size = 4;
6905 if (code16)
6906 size = 2;
252b5132 6907
29b0f896
AM		 6908 if (i.prefixes != 0 && !intel_syntax)
6909 as_warn (_("skipping prefixes on this instruction"));
252b5132 6910
29b0f896
AM		 6911 /* 1 opcode; 2 segment; offset */
6912 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6913
29b0f896
AM		 6914 if (i.prefix[DATA_PREFIX] != 0)
6915 *p++ = DATA_PREFIX_OPCODE;
252b5132 6916
29b0f896
AM		 6917 if (i.prefix[REX_PREFIX] != 0)
6918 *p++ = i.prefix[REX_PREFIX];
252b5132 6919
29b0f896
AM		 6920 *p++ = i.tm.base_opcode;
6921 if (i.op[1].imms->X_op == O_constant)
6922 {
6923 offsetT n = i.op[1].imms->X_add_number;
252b5132 6924
29b0f896
AM		 6925 if (size == 2
6926 && !fits_in_unsigned_word (n)
6927 && !fits_in_signed_word (n))
6928 {
6929 as_bad (_("16-bit jump out of range"));
6930 return;
6931 }
6932 md_number_to_chars (p, n, size);
6933 }
6934 else
6935 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6936 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 6937 if (i.op[0].imms->X_op != O_constant)
6938 as_bad (_("can't handle non absolute segment in `%s'"),
6939 i.tm.name);
6940 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6941}
a217f122 6942
29b0f896 6943static void
e3bb37b5 6944output_insn (void)
29b0f896 6945{
2bbd9c25
JJ		 6946 fragS *insn_start_frag;
6947 offsetT insn_start_off;
6948
29b0f896
AM		 6949 /* Tie dwarf2 debug info to the address at the start of the insn.
6950 We can't do this after the insn has been output as the current
6951 frag may have been closed off. eg. by frag_var. */
6952 dwarf2_emit_insn (0);
6953
2bbd9c25
JJ		 6954 insn_start_frag = frag_now;
6955 insn_start_off = frag_now_fix ();
6956
29b0f896 6957 /* Output jumps. */
40fb9820 6958 if (i.tm.opcode_modifier.jump)
29b0f896 6959 output_branch ();
40fb9820
L		 6960 else if (i.tm.opcode_modifier.jumpbyte
6961 || i.tm.opcode_modifier.jumpdword)
29b0f896 6962 output_jump ();
40fb9820 6963 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6964 output_interseg_jump ();
6965 else
6966 {
6967 /* Output normal instructions here. */
6968 char *p;
6969 unsigned char *q;
47465058 6970 unsigned int j;
331d2d0d 6971 unsigned int prefix;
4dffcebc 6972
e4e00185
AS		 6973 if (avoid_fence
6974 && i.tm.base_opcode == 0xfae
6975 && i.operands == 1
6976 && i.imm_operands == 1
6977 && (i.op[0].imms->X_add_number == 0xe8
6978 || i.op[0].imms->X_add_number == 0xf0
6979 || i.op[0].imms->X_add_number == 0xf8))
6980 {
6981 /* Encode lfence, mfence, and sfence as
6982 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
6983 offsetT val = 0x240483f0ULL;
6984 p = frag_more (5);
6985 md_number_to_chars (p, val, 5);
6986 return;
6987 }
6988
d022bddd
IT		 6989 /* Some processors fail on LOCK prefix. This options makes
6990 assembler ignore LOCK prefix and serves as a workaround. */
6991 if (omit_lock_prefix)
6992 {
6993 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
6994 return;
6995 i.prefix[LOCK_PREFIX] = 0;
6996 }
6997
43234a1e
L		 6998 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6999 don't need the explicit prefix. */
7000 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7001 {
c0f3af97 7002 switch (i.tm.opcode_length)
bc4bd9ab 7003 {
c0f3af97
L		 7004 case 3:
7005 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7006 {
c0f3af97
L		 7007 prefix = (i.tm.base_opcode >> 24) & 0xff;
7008 goto check_prefix;
7009 }
7010 break;
7011 case 2:
7012 if ((i.tm.base_opcode & 0xff0000) != 0)
7013 {
7014 prefix = (i.tm.base_opcode >> 16) & 0xff;
7015 if (i.tm.cpu_flags.bitfield.cpupadlock)
7016 {
4dffcebc 7017check_prefix:
c0f3af97 7018 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 7019 || (i.prefix[REP_PREFIX]
c0f3af97
L		 7020 != REPE_PREFIX_OPCODE))
7021 add_prefix (prefix);
7022 }
7023 else
4dffcebc
L		 7024 add_prefix (prefix);
7025 }
c0f3af97
L		 7026 break;
7027 case 1:
7028 break;
7029 default:
7030 abort ();
bc4bd9ab 7031 }
c0f3af97 7032
6d19a37a 7033#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7034 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7035 R_X86_64_GOTTPOFF relocation so that linker can safely
7036 perform IE->LE optimization. */
7037 if (x86_elf_abi == X86_64_X32_ABI
7038 && i.operands == 2
7039 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7040 && i.prefix[REX_PREFIX] == 0)
7041 add_prefix (REX_OPCODE);
6d19a37a 7042#endif
cf61b747 7043
c0f3af97
L		 7044 /* The prefix bytes. */
7045 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7046 if (*q)
7047 FRAG_APPEND_1_CHAR (*q);
0f10071e 7048 }
ae5c1c7b 7049 else
c0f3af97
L		 7050 {
7051 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7052 if (*q)
7053 switch (j)
7054 {
7055 case REX_PREFIX:
7056 /* REX byte is encoded in VEX prefix. */
7057 break;
7058 case SEG_PREFIX:
7059 case ADDR_PREFIX:
7060 FRAG_APPEND_1_CHAR (*q);
7061 break;
7062 default:
7063 /* There should be no other prefixes for instructions
7064 with VEX prefix. */
7065 abort ();
7066 }
7067
43234a1e
L		 7068 /* For EVEX instructions i.vrex should become 0 after
7069 build_evex_prefix. For VEX instructions upper 16 registers
7070 aren't available, so VREX should be 0. */
7071 if (i.vrex)
7072 abort ();
c0f3af97
L		 7073 /* Now the VEX prefix. */
7074 p = frag_more (i.vex.length);
7075 for (j = 0; j < i.vex.length; j++)
7076 p[j] = i.vex.bytes[j];
7077 }
252b5132 7078
29b0f896 7079 /* Now the opcode; be careful about word order here! */
4dffcebc 7080 if (i.tm.opcode_length == 1)
29b0f896
AM		 7081 {
7082 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7083 }
7084 else
7085 {
4dffcebc 7086 switch (i.tm.opcode_length)
331d2d0d 7087 {
43234a1e
L		 7088 case 4:
7089 p = frag_more (4);
7090 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7091 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7092 break;
4dffcebc 7093 case 3:
331d2d0d
L		 7094 p = frag_more (3);
7095 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7096 break;
7097 case 2:
7098 p = frag_more (2);
7099 break;
7100 default:
7101 abort ();
7102 break;
331d2d0d 7103 }
0f10071e 7104
29b0f896
AM		 7105 /* Put out high byte first: can't use md_number_to_chars! */
7106 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7107 *p = i.tm.base_opcode & 0xff;
7108 }
3e73aa7c 7109
29b0f896 7110 /* Now the modrm byte and sib byte (if present). */
40fb9820 7111 if (i.tm.opcode_modifier.modrm)
29b0f896 7112 {
4a3523fa
L		 7113 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7114 | i.rm.reg << 3
7115 | i.rm.mode << 6));
29b0f896
AM		 7116 /* If i.rm.regmem == ESP (4)
7117 && i.rm.mode != (Register mode)
7118 && not 16 bit
7119 ==> need second modrm byte. */
7120 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7121 && i.rm.mode != 3
40fb9820 7122 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7123 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7124 | i.sib.index << 3
7125 | i.sib.scale << 6));
29b0f896 7126 }
3e73aa7c 7127
29b0f896 7128 if (i.disp_operands)
2bbd9c25 7129 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7130
29b0f896 7131 if (i.imm_operands)
2bbd9c25 7132 output_imm (insn_start_frag, insn_start_off);
29b0f896 7133 }
252b5132 7134
29b0f896
AM		 7135#ifdef DEBUG386
7136 if (flag_debug)
7137 {
7b81dfbb 7138 pi ("" /*line*/, &i);
29b0f896
AM		 7139 }
7140#endif /* DEBUG386 */
7141}
252b5132 7142
e205caa7
L		 7143/* Return the size of the displacement operand N. */
7144
7145static int
7146disp_size (unsigned int n)
7147{
7148 int size = 4;
43234a1e
L		 7149
7150 /* Vec_Disp8 has to be 8bit. */
7151 if (i.types[n].bitfield.vec_disp8)
7152 size = 1;
7153 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7154 size = 8;
7155 else if (i.types[n].bitfield.disp8)
7156 size = 1;
7157 else if (i.types[n].bitfield.disp16)
7158 size = 2;
e205caa7
L		 7159 return size;
7160}
7161
7162/* Return the size of the immediate operand N. */
7163
7164static int
7165imm_size (unsigned int n)
7166{
7167 int size = 4;
40fb9820
L		 7168 if (i.types[n].bitfield.imm64)
7169 size = 8;
7170 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7171 size = 1;
7172 else if (i.types[n].bitfield.imm16)
7173 size = 2;
e205caa7
L		 7174 return size;
7175}
7176
29b0f896 7177static void
64e74474 7178output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7179{
7180 char *p;
7181 unsigned int n;
252b5132 7182
29b0f896
AM		 7183 for (n = 0; n < i.operands; n++)
7184 {
43234a1e
L		 7185 if (i.types[n].bitfield.vec_disp8
7186 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7187 {
7188 if (i.op[n].disps->X_op == O_constant)
7189 {
e205caa7 7190 int size = disp_size (n);
43234a1e 7191 offsetT val = i.op[n].disps->X_add_number;
252b5132 7192
43234a1e
L		 7193 if (i.types[n].bitfield.vec_disp8)
7194 val >>= i.memshift;
7195 val = offset_in_range (val, size);
29b0f896
AM		 7196 p = frag_more (size);
7197 md_number_to_chars (p, val, size);
7198 }
7199 else
7200 {
f86103b7 7201 enum bfd_reloc_code_real reloc_type;
e205caa7 7202 int size = disp_size (n);
40fb9820 7203 int sign = i.types[n].bitfield.disp32s;
29b0f896 7204 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7205 fixS *fixP;
29b0f896 7206
e205caa7 7207 /* We can't have 8 bit displacement here. */
9c2799c2 7208 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7209
29b0f896
AM		 7210 /* The PC relative address is computed relative
7211 to the instruction boundary, so in case immediate
7212 fields follows, we need to adjust the value. */
7213 if (pcrel && i.imm_operands)
7214 {
29b0f896 7215 unsigned int n1;
e205caa7 7216 int sz = 0;
252b5132 7217
29b0f896 7218 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7219 if (operand_type_check (i.types[n1], imm))
252b5132 7220 {
e205caa7
L		 7221 /* Only one immediate is allowed for PC
7222 relative address. */
9c2799c2 7223 gas_assert (sz == 0);
e205caa7
L		 7224 sz = imm_size (n1);
7225 i.op[n].disps->X_add_number -= sz;
252b5132 7226 }
29b0f896 7227 /* We should find the immediate. */
9c2799c2 7228 gas_assert (sz != 0);
29b0f896 7229 }
520dc8e8 7230
29b0f896 7231 p = frag_more (size);
d258b828 7232 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7233 if (GOT_symbol
2bbd9c25 7234 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7235 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7236 || reloc_type == BFD_RELOC_X86_64_32S
7237 || (reloc_type == BFD_RELOC_64
7238 && object_64bit))
d6ab8113
JB		 7239 && (i.op[n].disps->X_op == O_symbol
7240 || (i.op[n].disps->X_op == O_add
7241 && ((symbol_get_value_expression
7242 (i.op[n].disps->X_op_symbol)->X_op)
7243 == O_subtract))))
7244 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7245 {
7246 offsetT add;
7247
7248 if (insn_start_frag == frag_now)
7249 add = (p - frag_now->fr_literal) - insn_start_off;
7250 else
7251 {
7252 fragS *fr;
7253
7254 add = insn_start_frag->fr_fix - insn_start_off;
7255 for (fr = insn_start_frag->fr_next;
7256 fr && fr != frag_now; fr = fr->fr_next)
7257 add += fr->fr_fix;
7258 add += p - frag_now->fr_literal;
7259 }
7260
4fa24527 7261 if (!object_64bit)
7b81dfbb
AJ		 7262 {
7263 reloc_type = BFD_RELOC_386_GOTPC;
7264 i.op[n].imms->X_add_number += add;
7265 }
7266 else if (reloc_type == BFD_RELOC_64)
7267 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7268 else
7b81dfbb
AJ		 7269 /* Don't do the adjustment for x86-64, as there
7270 the pcrel addressing is relative to the _next_
7271 insn, and that is taken care of in other code. */
d6ab8113 7272 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7273 }
02a86693
L		 7274 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7275 size, i.op[n].disps, pcrel,
7276 reloc_type);
7277 /* Check for "call/jmp *mem", "mov mem, %reg",
7278 "test %reg, mem" and "binop mem, %reg" where binop
7279 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 7280 instructions. Always generate R_386_GOT32X for
7281 "sym*GOT" operand in 32-bit mode. */
7282 if ((generate_relax_relocations
7283 || (!object_64bit
7284 && i.rm.mode == 0
7285 && i.rm.regmem == 5))
7286 && (i.rm.mode == 2
7287 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 7288 && ((i.operands == 1
7289 && i.tm.base_opcode == 0xff
7290 && (i.rm.reg == 2 || i.rm.reg == 4))
7291 || (i.operands == 2
7292 && (i.tm.base_opcode == 0x8b
7293 || i.tm.base_opcode == 0x85
7294 || (i.tm.base_opcode & 0xc7) == 0x03))))
7295 {
7296 if (object_64bit)
7297 {
7298 fixP->fx_tcbit = i.rex != 0;
7299 if (i.base_reg
7300 && (i.base_reg->reg_num == RegRip
7301 || i.base_reg->reg_num == RegEip))
7302 fixP->fx_tcbit2 = 1;
7303 }
7304 else
7305 fixP->fx_tcbit2 = 1;
7306 }
29b0f896
AM		 7307 }
7308 }
7309 }
7310}
252b5132 7311
29b0f896 7312static void
64e74474 7313output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7314{
7315 char *p;
7316 unsigned int n;
252b5132 7317
29b0f896
AM		 7318 for (n = 0; n < i.operands; n++)
7319 {
43234a1e
L		 7320 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7321 if (i.rounding && (int) n == i.rounding->operand)
7322 continue;
7323
40fb9820 7324 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7325 {
7326 if (i.op[n].imms->X_op == O_constant)
7327 {
e205caa7 7328 int size = imm_size (n);
29b0f896 7329 offsetT val;
b4cac588 7330
29b0f896
AM		 7331 val = offset_in_range (i.op[n].imms->X_add_number,
7332 size);
7333 p = frag_more (size);
7334 md_number_to_chars (p, val, size);
7335 }
7336 else
7337 {
7338 /* Not absolute_section.
7339 Need a 32-bit fixup (don't support 8bit
7340 non-absolute imms). Try to support other
7341 sizes ... */
f86103b7 7342 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7343 int size = imm_size (n);
7344 int sign;
29b0f896 7345
40fb9820 7346 if (i.types[n].bitfield.imm32s
a7d61044 7347 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7348 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7349 sign = 1;
e205caa7
L		 7350 else
7351 sign = 0;
520dc8e8 7352
29b0f896 7353 p = frag_more (size);
d258b828 7354 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7355
2bbd9c25
JJ		 7356 /* This is tough to explain. We end up with this one if we
7357 * have operands that look like
7358 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7359 * obtain the absolute address of the GOT, and it is strongly
7360 * preferable from a performance point of view to avoid using
7361 * a runtime relocation for this. The actual sequence of
7362 * instructions often look something like:
7363 *
7364 * call .L66
7365 * .L66:
7366 * popl %ebx
7367 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7368 *
7369 * The call and pop essentially return the absolute address
7370 * of the label .L66 and store it in %ebx. The linker itself
7371 * will ultimately change the first operand of the addl so
7372 * that %ebx points to the GOT, but to keep things simple, the
7373 * .o file must have this operand set so that it generates not
7374 * the absolute address of .L66, but the absolute address of
7375 * itself. This allows the linker itself simply treat a GOTPC
7376 * relocation as asking for a pcrel offset to the GOT to be
7377 * added in, and the addend of the relocation is stored in the
7378 * operand field for the instruction itself.
7379 *
7380 * Our job here is to fix the operand so that it would add
7381 * the correct offset so that %ebx would point to itself. The
7382 * thing that is tricky is that .-.L66 will point to the
7383 * beginning of the instruction, so we need to further modify
7384 * the operand so that it will point to itself. There are
7385 * other cases where you have something like:
7386 *
7387 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7388 *
7389 * and here no correction would be required. Internally in
7390 * the assembler we treat operands of this form as not being
7391 * pcrel since the '.' is explicitly mentioned, and I wonder
7392 * whether it would simplify matters to do it this way. Who
7393 * knows. In earlier versions of the PIC patches, the
7394 * pcrel_adjust field was used to store the correction, but
7395 * since the expression is not pcrel, I felt it would be
7396 * confusing to do it this way. */
7397
d6ab8113 7398 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7399 || reloc_type == BFD_RELOC_X86_64_32S
7400 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7401 && GOT_symbol
7402 && GOT_symbol == i.op[n].imms->X_add_symbol
7403 && (i.op[n].imms->X_op == O_symbol
7404 || (i.op[n].imms->X_op == O_add
7405 && ((symbol_get_value_expression
7406 (i.op[n].imms->X_op_symbol)->X_op)
7407 == O_subtract))))
7408 {
2bbd9c25
JJ		 7409 offsetT add;
7410
7411 if (insn_start_frag == frag_now)
7412 add = (p - frag_now->fr_literal) - insn_start_off;
7413 else
7414 {
7415 fragS *fr;
7416
7417 add = insn_start_frag->fr_fix - insn_start_off;
7418 for (fr = insn_start_frag->fr_next;
7419 fr && fr != frag_now; fr = fr->fr_next)
7420 add += fr->fr_fix;
7421 add += p - frag_now->fr_literal;
7422 }
7423
4fa24527 7424 if (!object_64bit)
d6ab8113 7425 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7426 else if (size == 4)
d6ab8113 7427 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7428 else if (size == 8)
7429 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7430 i.op[n].imms->X_add_number += add;
29b0f896 7431 }
29b0f896
AM		 7432 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7433 i.op[n].imms, 0, reloc_type);
7434 }
7435 }
7436 }
252b5132
RH		 7437}
7438\f
d182319b
JB		 7439/* x86_cons_fix_new is called via the expression parsing code when a
7440 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7441static int cons_sign = -1;
7442
7443void
e3bb37b5 7444x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7445 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7446{
d258b828 7447 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7448
7449#ifdef TE_PE
7450 if (exp->X_op == O_secrel)
7451 {
7452 exp->X_op = O_symbol;
7453 r = BFD_RELOC_32_SECREL;
7454 }
7455#endif
7456
7457 fix_new_exp (frag, off, len, exp, 0, r);
7458}
7459
357d1bd8
L		 7460/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7461 purpose of the `.dc.a' internal pseudo-op. */
7462
7463int
7464x86_address_bytes (void)
7465{
7466 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7467 return 4;
7468 return stdoutput->arch_info->bits_per_address / 8;
7469}
7470
d382c579
TG		 7471#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7472 || defined (LEX_AT)
d258b828 7473# define lex_got(reloc, adjust, types) NULL
718ddfc0 7474#else
f3c180ae
AM		 7475/* Parse operands of the form
7476 <symbol>@GOTOFF+<nnn>
7477 and similar .plt or .got references.
7478
7479 If we find one, set up the correct relocation in RELOC and copy the
7480 input string, minus the `@GOTOFF' into a malloc'd buffer for
7481 parsing by the calling routine. Return this buffer, and if ADJUST
7482 is non-null set it to the length of the string we removed from the
7483 input line. Otherwise return NULL. */
7484static char *
91d6fa6a 7485lex_got (enum bfd_reloc_code_real *rel,
64e74474 7486 int *adjust,
d258b828 7487 i386_operand_type *types)
f3c180ae 7488{
7b81dfbb
AJ		 7489 /* Some of the relocations depend on the size of what field is to
7490 be relocated. But in our callers i386_immediate and i386_displacement
7491 we don't yet know the operand size (this will be set by insn
7492 matching). Hence we record the word32 relocation here,
7493 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7494 static const struct {
7495 const char *str;
cff8d58a 7496 int len;
4fa24527 7497 const enum bfd_reloc_code_real rel[2];
40fb9820 7498 const i386_operand_type types64;
f3c180ae 7499 } gotrel[] = {
8ce3d284 7500#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7501 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7502 BFD_RELOC_SIZE32 },
7503 OPERAND_TYPE_IMM32_64 },
8ce3d284 7504#endif
cff8d58a
L		 7505 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7506 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7507 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7508 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7509 BFD_RELOC_X86_64_PLT32 },
40fb9820 7510 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7511 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7512 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7513 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7514 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7515 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7516 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7517 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7518 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7519 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7520 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7521 BFD_RELOC_X86_64_TLSGD },
40fb9820 7522 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7523 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7524 _dummy_first_bfd_reloc_code_real },
40fb9820 7525 OPERAND_TYPE_NONE },
cff8d58a
L		 7526 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7527 BFD_RELOC_X86_64_TLSLD },
40fb9820 7528 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7529 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7530 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7531 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7532 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7533 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7534 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7535 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7536 _dummy_first_bfd_reloc_code_real },
40fb9820 7537 OPERAND_TYPE_NONE },
cff8d58a
L		 7538 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7539 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7540 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7541 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7542 _dummy_first_bfd_reloc_code_real },
40fb9820 7543 OPERAND_TYPE_NONE },
cff8d58a
L		 7544 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7545 _dummy_first_bfd_reloc_code_real },
40fb9820 7546 OPERAND_TYPE_NONE },
cff8d58a
L		 7547 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7548 BFD_RELOC_X86_64_GOT32 },
40fb9820 7549 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7550 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7551 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7552 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7553 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7554 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7555 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7556 };
7557 char *cp;
7558 unsigned int j;
7559
d382c579 7560#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7561 if (!IS_ELF)
7562 return NULL;
d382c579 7563#endif
718ddfc0 7564
f3c180ae 7565 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7566 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7567 return NULL;
7568
47465058 7569 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7570 {
cff8d58a 7571 int len = gotrel[j].len;
28f81592 7572 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7573 {
4fa24527 7574 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7575 {
28f81592
AM		 7576 int first, second;
7577 char *tmpbuf, *past_reloc;
f3c180ae 7578
91d6fa6a 7579 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7580
3956db08
JB		 7581 if (types)
7582 {
7583 if (flag_code != CODE_64BIT)
40fb9820
L		 7584 {
7585 types->bitfield.imm32 = 1;
7586 types->bitfield.disp32 = 1;
7587 }
3956db08
JB		 7588 else
7589 *types = gotrel[j].types64;
7590 }
7591
8fd4256d 7592 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7593 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7594
28f81592 7595 /* The length of the first part of our input line. */
f3c180ae 7596 first = cp - input_line_pointer;
28f81592
AM		 7597
7598 /* The second part goes from after the reloc token until
67c11a9b 7599 (and including) an end_of_line char or comma. */
28f81592 7600 past_reloc = cp + 1 + len;
67c11a9b
AM		 7601 cp = past_reloc;
7602 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7603 ++cp;
7604 second = cp + 1 - past_reloc;
28f81592
AM		 7605
7606 /* Allocate and copy string. The trailing NUL shouldn't
7607 be necessary, but be safe. */
1e9cc1c2 7608 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 7609 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7610 if (second != 0 && *past_reloc != ' ')
7611 /* Replace the relocation token with ' ', so that
7612 errors like foo@GOTOFF1 will be detected. */
7613 tmpbuf[first++] = ' ';
af89796a
L		 7614 else
7615 /* Increment length by 1 if the relocation token is
7616 removed. */
7617 len++;
7618 if (adjust)
7619 *adjust = len;
0787a12d
AM		 7620 memcpy (tmpbuf + first, past_reloc, second);
7621 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7622 return tmpbuf;
7623 }
7624
4fa24527
JB		 7625 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7626 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7627 return NULL;
7628 }
7629 }
7630
7631 /* Might be a symbol version string. Don't as_bad here. */
7632 return NULL;
7633}
4e4f7c87 7634#endif
f3c180ae 7635
a988325c
NC		 7636#ifdef TE_PE
7637#ifdef lex_got
7638#undef lex_got
7639#endif
7640/* Parse operands of the form
7641 <symbol>@SECREL32+<nnn>
7642
7643 If we find one, set up the correct relocation in RELOC and copy the
7644 input string, minus the `@SECREL32' into a malloc'd buffer for
7645 parsing by the calling routine. Return this buffer, and if ADJUST
7646 is non-null set it to the length of the string we removed from the
34bca508
L		 7647 input line. Otherwise return NULL.
7648
a988325c
NC		 7649 This function is copied from the ELF version above adjusted for PE targets. */
7650
7651static char *
7652lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7653 int *adjust ATTRIBUTE_UNUSED,
d258b828 7654 i386_operand_type *types)
a988325c
NC		 7655{
7656 static const struct
7657 {
7658 const char *str;
7659 int len;
7660 const enum bfd_reloc_code_real rel[2];
7661 const i386_operand_type types64;
7662 }
7663 gotrel[] =
7664 {
7665 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7666 BFD_RELOC_32_SECREL },
7667 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7668 };
7669
7670 char *cp;
7671 unsigned j;
7672
7673 for (cp = input_line_pointer; *cp != '@'; cp++)
7674 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7675 return NULL;
7676
7677 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7678 {
7679 int len = gotrel[j].len;
7680
7681 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7682 {
7683 if (gotrel[j].rel[object_64bit] != 0)
7684 {
7685 int first, second;
7686 char *tmpbuf, *past_reloc;
7687
7688 *rel = gotrel[j].rel[object_64bit];
7689 if (adjust)
7690 *adjust = len;
7691
7692 if (types)
7693 {
7694 if (flag_code != CODE_64BIT)
7695 {
7696 types->bitfield.imm32 = 1;
7697 types->bitfield.disp32 = 1;
7698 }
7699 else
7700 *types = gotrel[j].types64;
7701 }
7702
7703 /* The length of the first part of our input line. */
7704 first = cp - input_line_pointer;
7705
7706 /* The second part goes from after the reloc token until
7707 (and including) an end_of_line char or comma. */
7708 past_reloc = cp + 1 + len;
7709 cp = past_reloc;
7710 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7711 ++cp;
7712 second = cp + 1 - past_reloc;
7713
7714 /* Allocate and copy string. The trailing NUL shouldn't
7715 be necessary, but be safe. */
7716 tmpbuf = (char *) xmalloc (first + second + 2);
7717 memcpy (tmpbuf, input_line_pointer, first);
7718 if (second != 0 && *past_reloc != ' ')
7719 /* Replace the relocation token with ' ', so that
7720 errors like foo@SECLREL321 will be detected. */
7721 tmpbuf[first++] = ' ';
7722 memcpy (tmpbuf + first, past_reloc, second);
7723 tmpbuf[first + second] = '\0';
7724 return tmpbuf;
7725 }
7726
7727 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7728 gotrel[j].str, 1 << (5 + object_64bit));
7729 return NULL;
7730 }
7731 }
7732
7733 /* Might be a symbol version string. Don't as_bad here. */
7734 return NULL;
7735}
7736
7737#endif /* TE_PE */
7738
62ebcb5c 7739bfd_reloc_code_real_type
e3bb37b5 7740x86_cons (expressionS *exp, int size)
f3c180ae 7741{
62ebcb5c
AM		 7742 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7743
ee86248c
JB		 7744 intel_syntax = -intel_syntax;
7745
3c7b9c2c 7746 exp->X_md = 0;
4fa24527 7747 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7748 {
7749 /* Handle @GOTOFF and the like in an expression. */
7750 char *save;
7751 char *gotfree_input_line;
4a57f2cf 7752 int adjust = 0;
f3c180ae
AM		 7753
7754 save = input_line_pointer;
d258b828 7755 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 7756 if (gotfree_input_line)
7757 input_line_pointer = gotfree_input_line;
7758
7759 expression (exp);
7760
7761 if (gotfree_input_line)
7762 {
7763 /* expression () has merrily parsed up to the end of line,
7764 or a comma - in the wrong buffer. Transfer how far
7765 input_line_pointer has moved to the right buffer. */
7766 input_line_pointer = (save
7767 + (input_line_pointer - gotfree_input_line)
7768 + adjust);
7769 free (gotfree_input_line);
3992d3b7
AM		 7770 if (exp->X_op == O_constant
7771 || exp->X_op == O_absent
7772 || exp->X_op == O_illegal
0398aac5 7773 || exp->X_op == O_register
3992d3b7
AM		 7774 || exp->X_op == O_big)
7775 {
7776 char c = *input_line_pointer;
7777 *input_line_pointer = 0;
7778 as_bad (_("missing or invalid expression `%s'"), save);
7779 *input_line_pointer = c;
7780 }
f3c180ae
AM		 7781 }
7782 }
7783 else
7784 expression (exp);
ee86248c
JB		 7785
7786 intel_syntax = -intel_syntax;
7787
7788 if (intel_syntax)
7789 i386_intel_simplify (exp);
62ebcb5c
AM		 7790
7791 return got_reloc;
f3c180ae 7792}
f3c180ae 7793
9f32dd5b
L		 7794static void
7795signed_cons (int size)
6482c264 7796{
d182319b
JB		 7797 if (flag_code == CODE_64BIT)
7798 cons_sign = 1;
7799 cons (size);
7800 cons_sign = -1;
6482c264
NC		 7801}
7802
d182319b 7803#ifdef TE_PE
6482c264 7804static void
7016a5d5 7805pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7806{
7807 expressionS exp;
7808
7809 do
7810 {
7811 expression (&exp);
7812 if (exp.X_op == O_symbol)
7813 exp.X_op = O_secrel;
7814
7815 emit_expr (&exp, 4);
7816 }
7817 while (*input_line_pointer++ == ',');
7818
7819 input_line_pointer--;
7820 demand_empty_rest_of_line ();
7821}
6482c264
NC		 7822#endif
7823
43234a1e
L		 7824/* Handle Vector operations. */
7825
7826static char *
7827check_VecOperations (char *op_string, char *op_end)
7828{
7829 const reg_entry *mask;
7830 const char *saved;
7831 char *end_op;
7832
7833 while (*op_string
7834 && (op_end == NULL || op_string < op_end))
7835 {
7836 saved = op_string;
7837 if (*op_string == '{')
7838 {
7839 op_string++;
7840
7841 /* Check broadcasts. */
7842 if (strncmp (op_string, "1to", 3) == 0)
7843 {
7844 int bcst_type;
7845
7846 if (i.broadcast)
7847 goto duplicated_vec_op;
7848
7849 op_string += 3;
7850 if (*op_string == '8')
7851 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 7852 else if (*op_string == '4')
7853 bcst_type = BROADCAST_1TO4;
7854 else if (*op_string == '2')
7855 bcst_type = BROADCAST_1TO2;
43234a1e
L		 7856 else if (*op_string == '1'
7857 && *(op_string+1) == '6')
7858 {
7859 bcst_type = BROADCAST_1TO16;
7860 op_string++;
7861 }
7862 else
7863 {
7864 as_bad (_("Unsupported broadcast: `%s'"), saved);
7865 return NULL;
7866 }
7867 op_string++;
7868
7869 broadcast_op.type = bcst_type;
7870 broadcast_op.operand = this_operand;
7871 i.broadcast = &broadcast_op;
7872 }
7873 /* Check masking operation. */
7874 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7875 {
7876 /* k0 can't be used for write mask. */
7877 if (mask->reg_num == 0)
7878 {
7879 as_bad (_("`%s' can't be used for write mask"),
7880 op_string);
7881 return NULL;
7882 }
7883
7884 if (!i.mask)
7885 {
7886 mask_op.mask = mask;
7887 mask_op.zeroing = 0;
7888 mask_op.operand = this_operand;
7889 i.mask = &mask_op;
7890 }
7891 else
7892 {
7893 if (i.mask->mask)
7894 goto duplicated_vec_op;
7895
7896 i.mask->mask = mask;
7897
7898 /* Only "{z}" is allowed here. No need to check
7899 zeroing mask explicitly. */
7900 if (i.mask->operand != this_operand)
7901 {
7902 as_bad (_("invalid write mask `%s'"), saved);
7903 return NULL;
7904 }
7905 }
7906
7907 op_string = end_op;
7908 }
7909 /* Check zeroing-flag for masking operation. */
7910 else if (*op_string == 'z')
7911 {
7912 if (!i.mask)
7913 {
7914 mask_op.mask = NULL;
7915 mask_op.zeroing = 1;
7916 mask_op.operand = this_operand;
7917 i.mask = &mask_op;
7918 }
7919 else
7920 {
7921 if (i.mask->zeroing)
7922 {
7923 duplicated_vec_op:
7924 as_bad (_("duplicated `%s'"), saved);
7925 return NULL;
7926 }
7927
7928 i.mask->zeroing = 1;
7929
7930 /* Only "{%k}" is allowed here. No need to check mask
7931 register explicitly. */
7932 if (i.mask->operand != this_operand)
7933 {
7934 as_bad (_("invalid zeroing-masking `%s'"),
7935 saved);
7936 return NULL;
7937 }
7938 }
7939
7940 op_string++;
7941 }
7942 else
7943 goto unknown_vec_op;
7944
7945 if (*op_string != '}')
7946 {
7947 as_bad (_("missing `}' in `%s'"), saved);
7948 return NULL;
7949 }
7950 op_string++;
7951 continue;
7952 }
7953 unknown_vec_op:
7954 /* We don't know this one. */
7955 as_bad (_("unknown vector operation: `%s'"), saved);
7956 return NULL;
7957 }
7958
7959 return op_string;
7960}
7961
252b5132 7962static int
70e41ade 7963i386_immediate (char *imm_start)
252b5132
RH		 7964{
7965 char *save_input_line_pointer;
f3c180ae 7966 char *gotfree_input_line;
252b5132 7967 segT exp_seg = 0;
47926f60 7968 expressionS *exp;
40fb9820
L		 7969 i386_operand_type types;
7970
0dfbf9d7 7971 operand_type_set (&types, ~0);
252b5132
RH		 7972
7973 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7974 {
31b2323c
L		 7975 as_bad (_("at most %d immediate operands are allowed"),
7976 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 7977 return 0;
7978 }
7979
7980 exp = &im_expressions[i.imm_operands++];
520dc8e8 7981 i.op[this_operand].imms = exp;
252b5132
RH		 7982
7983 if (is_space_char (*imm_start))
7984 ++imm_start;
7985
7986 save_input_line_pointer = input_line_pointer;
7987 input_line_pointer = imm_start;
7988
d258b828 7989 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 7990 if (gotfree_input_line)
7991 input_line_pointer = gotfree_input_line;
252b5132
RH		 7992
7993 exp_seg = expression (exp);
7994
83183c0c 7995 SKIP_WHITESPACE ();
43234a1e
L		 7996
7997 /* Handle vector operations. */
7998 if (*input_line_pointer == '{')
7999 {
8000 input_line_pointer = check_VecOperations (input_line_pointer,
8001 NULL);
8002 if (input_line_pointer == NULL)
8003 return 0;
8004 }
8005
252b5132 8006 if (*input_line_pointer)
f3c180ae 8007 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8008
8009 input_line_pointer = save_input_line_pointer;
f3c180ae 8010 if (gotfree_input_line)
ee86248c
JB		 8011 {
8012 free (gotfree_input_line);
8013
8014 if (exp->X_op == O_constant || exp->X_op == O_register)
8015 exp->X_op = O_illegal;
8016 }
8017
8018 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8019}
252b5132 8020
ee86248c
JB		 8021static int
8022i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8023 i386_operand_type types, const char *imm_start)
8024{
8025 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8026 {
313c53d1
L		 8027 if (imm_start)
8028 as_bad (_("missing or invalid immediate expression `%s'"),
8029 imm_start);
3992d3b7 8030 return 0;
252b5132 8031 }
3e73aa7c 8032 else if (exp->X_op == O_constant)
252b5132 8033 {
47926f60 8034 /* Size it properly later. */
40fb9820 8035 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8036 /* If not 64bit, sign extend val. */
8037 if (flag_code != CODE_64BIT
4eed87de
AM		 8038 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8039 exp->X_add_number
8040 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8041 }
4c63da97 8042#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8043 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8044 && exp_seg != absolute_section
47926f60 8045 && exp_seg != text_section
24eab124
AM		 8046 && exp_seg != data_section
8047 && exp_seg != bss_section
8048 && exp_seg != undefined_section
f86103b7 8049 && !bfd_is_com_section (exp_seg))
252b5132 8050 {
d0b47220 8051 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8052 return 0;
8053 }
8054#endif
a841bdf5 8055 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8056 {
313c53d1
L		 8057 if (imm_start)
8058 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8059 return 0;
8060 }
252b5132
RH		 8061 else
8062 {
8063 /* This is an address. The size of the address will be
24eab124 8064 determined later, depending on destination register,
3e73aa7c 8065 suffix, or the default for the section. */
40fb9820
L		 8066 i.types[this_operand].bitfield.imm8 = 1;
8067 i.types[this_operand].bitfield.imm16 = 1;
8068 i.types[this_operand].bitfield.imm32 = 1;
8069 i.types[this_operand].bitfield.imm32s = 1;
8070 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8071 i.types[this_operand] = operand_type_and (i.types[this_operand],
8072 types);
252b5132
RH		 8073 }
8074
8075 return 1;
8076}
8077
551c1ca1 8078static char *
e3bb37b5 8079i386_scale (char *scale)
252b5132 8080{
551c1ca1
AM		 8081 offsetT val;
8082 char *save = input_line_pointer;
252b5132 8083
551c1ca1
AM		 8084 input_line_pointer = scale;
8085 val = get_absolute_expression ();
8086
8087 switch (val)
252b5132 8088 {
551c1ca1 8089 case 1:
252b5132
RH		 8090 i.log2_scale_factor = 0;
8091 break;
551c1ca1 8092 case 2:
252b5132
RH		 8093 i.log2_scale_factor = 1;
8094 break;
551c1ca1 8095 case 4:
252b5132
RH		 8096 i.log2_scale_factor = 2;
8097 break;
551c1ca1 8098 case 8:
252b5132
RH		 8099 i.log2_scale_factor = 3;
8100 break;
8101 default:
a724f0f4
JB		 8102 {
8103 char sep = *input_line_pointer;
8104
8105 *input_line_pointer = '\0';
8106 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8107 scale);
8108 *input_line_pointer = sep;
8109 input_line_pointer = save;
8110 return NULL;
8111 }
252b5132 8112 }
29b0f896 8113 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8114 {
8115 as_warn (_("scale factor of %d without an index register"),
24eab124 8116 1 << i.log2_scale_factor);
252b5132 8117 i.log2_scale_factor = 0;
252b5132 8118 }
551c1ca1
AM		 8119 scale = input_line_pointer;
8120 input_line_pointer = save;
8121 return scale;
252b5132
RH		 8122}
8123
252b5132 8124static int
e3bb37b5 8125i386_displacement (char *disp_start, char *disp_end)
252b5132 8126{
29b0f896 8127 expressionS *exp;
252b5132
RH		 8128 segT exp_seg = 0;
8129 char *save_input_line_pointer;
f3c180ae 8130 char *gotfree_input_line;
40fb9820
L		 8131 int override;
8132 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8133 int ret;
252b5132 8134
31b2323c
L		 8135 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8136 {
8137 as_bad (_("at most %d displacement operands are allowed"),
8138 MAX_MEMORY_OPERANDS);
8139 return 0;
8140 }
8141
0dfbf9d7 8142 operand_type_set (&bigdisp, 0);
40fb9820
L		 8143 if ((i.types[this_operand].bitfield.jumpabsolute)
8144 || (!current_templates->start->opcode_modifier.jump
8145 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8146 {
40fb9820 8147 bigdisp.bitfield.disp32 = 1;
e05278af 8148 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8149 if (flag_code == CODE_64BIT)
8150 {
8151 if (!override)
8152 {
8153 bigdisp.bitfield.disp32s = 1;
8154 bigdisp.bitfield.disp64 = 1;
8155 }
8156 }
8157 else if ((flag_code == CODE_16BIT) ^ override)
8158 {
8159 bigdisp.bitfield.disp32 = 0;
8160 bigdisp.bitfield.disp16 = 1;
8161 }
e05278af
JB		 8162 }
8163 else
8164 {
8165 /* For PC-relative branches, the width of the displacement
8166 is dependent upon data size, not address size. */
e05278af 8167 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8168 if (flag_code == CODE_64BIT)
8169 {
8170 if (override || i.suffix == WORD_MNEM_SUFFIX)
8171 bigdisp.bitfield.disp16 = 1;
8172 else
8173 {
8174 bigdisp.bitfield.disp32 = 1;
8175 bigdisp.bitfield.disp32s = 1;
8176 }
8177 }
8178 else
e05278af
JB		 8179 {
8180 if (!override)
8181 override = (i.suffix == (flag_code != CODE_16BIT
8182 ? WORD_MNEM_SUFFIX
8183 : LONG_MNEM_SUFFIX));
40fb9820
L		 8184 bigdisp.bitfield.disp32 = 1;
8185 if ((flag_code == CODE_16BIT) ^ override)
8186 {
8187 bigdisp.bitfield.disp32 = 0;
8188 bigdisp.bitfield.disp16 = 1;
8189 }
e05278af 8190 }
e05278af 8191 }
c6fb90c8
L		 8192 i.types[this_operand] = operand_type_or (i.types[this_operand],
8193 bigdisp);
252b5132
RH		 8194
8195 exp = &disp_expressions[i.disp_operands];
520dc8e8 8196 i.op[this_operand].disps = exp;
252b5132
RH		 8197 i.disp_operands++;
8198 save_input_line_pointer = input_line_pointer;
8199 input_line_pointer = disp_start;
8200 END_STRING_AND_SAVE (disp_end);
8201
8202#ifndef GCC_ASM_O_HACK
8203#define GCC_ASM_O_HACK 0
8204#endif
8205#if GCC_ASM_O_HACK
8206 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8207 if (i.types[this_operand].bitfield.baseIndex
24eab124 8208 && displacement_string_end[-1] == '+')
252b5132
RH		 8209 {
8210 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8211 constraint within gcc asm statements.
8212 For instance:
8213
8214 #define _set_tssldt_desc(n,addr,limit,type) \
8215 __asm__ __volatile__ ( \
8216 "movw %w2,%0\n\t" \
8217 "movw %w1,2+%0\n\t" \
8218 "rorl $16,%1\n\t" \
8219 "movb %b1,4+%0\n\t" \
8220 "movb %4,5+%0\n\t" \
8221 "movb $0,6+%0\n\t" \
8222 "movb %h1,7+%0\n\t" \
8223 "rorl $16,%1" \
8224 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8225
8226 This works great except that the output assembler ends
8227 up looking a bit weird if it turns out that there is
8228 no offset. You end up producing code that looks like:
8229
8230 #APP
8231 movw $235,(%eax)
8232 movw %dx,2+(%eax)
8233 rorl $16,%edx
8234 movb %dl,4+(%eax)
8235 movb $137,5+(%eax)
8236 movb $0,6+(%eax)
8237 movb %dh,7+(%eax)
8238 rorl $16,%edx
8239 #NO_APP
8240
47926f60 8241 So here we provide the missing zero. */
24eab124
AM		 8242
8243 *displacement_string_end = '0';
252b5132
RH		 8244 }
8245#endif
d258b828 8246 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8247 if (gotfree_input_line)
8248 input_line_pointer = gotfree_input_line;
252b5132 8249
24eab124 8250 exp_seg = expression (exp);
252b5132 8251
636c26b0
AM		 8252 SKIP_WHITESPACE ();
8253 if (*input_line_pointer)
8254 as_bad (_("junk `%s' after expression"), input_line_pointer);
8255#if GCC_ASM_O_HACK
8256 RESTORE_END_STRING (disp_end + 1);
8257#endif
636c26b0 8258 input_line_pointer = save_input_line_pointer;
636c26b0 8259 if (gotfree_input_line)
ee86248c
JB		 8260 {
8261 free (gotfree_input_line);
8262
8263 if (exp->X_op == O_constant || exp->X_op == O_register)
8264 exp->X_op = O_illegal;
8265 }
8266
8267 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8268
8269 RESTORE_END_STRING (disp_end);
8270
8271 return ret;
8272}
8273
8274static int
8275i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8276 i386_operand_type types, const char *disp_start)
8277{
8278 i386_operand_type bigdisp;
8279 int ret = 1;
636c26b0 8280
24eab124
AM		 8281 /* We do this to make sure that the section symbol is in
8282 the symbol table. We will ultimately change the relocation
47926f60 8283 to be relative to the beginning of the section. */
1ae12ab7 8284 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8285 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8286 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8287 {
636c26b0 8288 if (exp->X_op != O_symbol)
3992d3b7 8289 goto inv_disp;
636c26b0 8290
e5cb08ac 8291 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8292 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8293 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8294 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8295 exp->X_op = O_subtract;
8296 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8297 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8298 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8299 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8300 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8301 else
29b0f896 8302 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8303 }
252b5132 8304
3992d3b7
AM		 8305 else if (exp->X_op == O_absent
8306 || exp->X_op == O_illegal
ee86248c 8307 || exp->X_op == O_big)
2daf4fd8 8308 {
3992d3b7
AM		 8309 inv_disp:
8310 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8311 disp_start);
3992d3b7 8312 ret = 0;
2daf4fd8
AM		 8313 }
8314
0e1147d9
L		 8315 else if (flag_code == CODE_64BIT
8316 && !i.prefix[ADDR_PREFIX]
8317 && exp->X_op == O_constant)
8318 {
8319 /* Since displacement is signed extended to 64bit, don't allow
8320 disp32 and turn off disp32s if they are out of range. */
8321 i.types[this_operand].bitfield.disp32 = 0;
8322 if (!fits_in_signed_long (exp->X_add_number))
8323 {
8324 i.types[this_operand].bitfield.disp32s = 0;
8325 if (i.types[this_operand].bitfield.baseindex)
8326 {
8327 as_bad (_("0x%lx out range of signed 32bit displacement"),
8328 (long) exp->X_add_number);
8329 ret = 0;
8330 }
8331 }
8332 }
8333
4c63da97 8334#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8335 else if (exp->X_op != O_constant
8336 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8337 && exp_seg != absolute_section
8338 && exp_seg != text_section
8339 && exp_seg != data_section
8340 && exp_seg != bss_section
8341 && exp_seg != undefined_section
8342 && !bfd_is_com_section (exp_seg))
24eab124 8343 {
d0b47220 8344 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8345 ret = 0;
24eab124 8346 }
252b5132 8347#endif
3956db08 8348
40fb9820
L		 8349 /* Check if this is a displacement only operand. */
8350 bigdisp = i.types[this_operand];
8351 bigdisp.bitfield.disp8 = 0;
8352 bigdisp.bitfield.disp16 = 0;
8353 bigdisp.bitfield.disp32 = 0;
8354 bigdisp.bitfield.disp32s = 0;
8355 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8356 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8357 i.types[this_operand] = operand_type_and (i.types[this_operand],
8358 types);
3956db08 8359
3992d3b7 8360 return ret;
252b5132
RH		 8361}
8362
eecb386c 8363/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8364 Return 1 on success, 0 on a failure. */
8365
252b5132 8366static int
e3bb37b5 8367i386_index_check (const char *operand_string)
252b5132 8368{
fc0763e6 8369 const char *kind = "base/index";
be05d201
L		 8370 enum flag_code addr_mode;
8371
8372 if (i.prefix[ADDR_PREFIX])
8373 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8374 else
8375 {
8376 addr_mode = flag_code;
8377
24eab124 8378#if INFER_ADDR_PREFIX
be05d201
L		 8379 if (i.mem_operands == 0)
8380 {
8381 /* Infer address prefix from the first memory operand. */
8382 const reg_entry *addr_reg = i.base_reg;
8383
8384 if (addr_reg == NULL)
8385 addr_reg = i.index_reg;
eecb386c 8386
be05d201
L		 8387 if (addr_reg)
8388 {
8389 if (addr_reg->reg_num == RegEip
8390 || addr_reg->reg_num == RegEiz
8391 || addr_reg->reg_type.bitfield.reg32)
8392 addr_mode = CODE_32BIT;
8393 else if (flag_code != CODE_64BIT
8394 && addr_reg->reg_type.bitfield.reg16)
8395 addr_mode = CODE_16BIT;
8396
8397 if (addr_mode != flag_code)
8398 {
8399 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8400 i.prefixes += 1;
8401 /* Change the size of any displacement too. At most one
8402 of Disp16 or Disp32 is set.
8403 FIXME. There doesn't seem to be any real need for
8404 separate Disp16 and Disp32 flags. The same goes for
8405 Imm16 and Imm32. Removing them would probably clean
8406 up the code quite a lot. */
8407 if (flag_code != CODE_64BIT
8408 && (i.types[this_operand].bitfield.disp16
8409 || i.types[this_operand].bitfield.disp32))
8410 i.types[this_operand]
8411 = operand_type_xor (i.types[this_operand], disp16_32);
8412 }
8413 }
8414 }
24eab124 8415#endif
be05d201
L		 8416 }
8417
fc0763e6
JB		 8418 if (current_templates->start->opcode_modifier.isstring
8419 && !current_templates->start->opcode_modifier.immext
8420 && (current_templates->end[-1].opcode_modifier.isstring
8421 || i.mem_operands))
8422 {
8423 /* Memory operands of string insns are special in that they only allow
8424 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8425 const reg_entry *expected_reg;
8426 static const char *di_si[][2] =
8427 {
8428 { "esi", "edi" },
8429 { "si", "di" },
8430 { "rsi", "rdi" }
8431 };
8432 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8433
8434 kind = "string address";
8435
8436 if (current_templates->start->opcode_modifier.w)
8437 {
8438 i386_operand_type type = current_templates->end[-1].operand_types[0];
8439
8440 if (!type.bitfield.baseindex
8441 || ((!i.mem_operands != !intel_syntax)
8442 && current_templates->end[-1].operand_types[1]
8443 .bitfield.baseindex))
8444 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8445 expected_reg = hash_find (reg_hash,
8446 di_si[addr_mode][type.bitfield.esseg]);
8447
fc0763e6
JB		 8448 }
8449 else
be05d201 8450 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8451
be05d201
L		 8452 if (i.base_reg != expected_reg
8453 || i.index_reg
fc0763e6 8454 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8455 {
be05d201
L		 8456 /* The second memory operand must have the same size as
8457 the first one. */
8458 if (i.mem_operands
8459 && i.base_reg
8460 && !((addr_mode == CODE_64BIT
8461 && i.base_reg->reg_type.bitfield.reg64)
8462 || (addr_mode == CODE_32BIT
8463 ? i.base_reg->reg_type.bitfield.reg32
8464 : i.base_reg->reg_type.bitfield.reg16)))
8465 goto bad_address;
8466
fc0763e6
JB		 8467 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8468 operand_string,
8469 intel_syntax ? '[' : '(',
8470 register_prefix,
be05d201 8471 expected_reg->reg_name,
fc0763e6 8472 intel_syntax ? ']' : ')');
be05d201 8473 return 1;
fc0763e6 8474 }
be05d201
L		 8475 else
8476 return 1;
8477
8478bad_address:
8479 as_bad (_("`%s' is not a valid %s expression"),
8480 operand_string, kind);
8481 return 0;
3e73aa7c
JH		 8482 }
8483 else
8484 {
be05d201
L		 8485 if (addr_mode != CODE_16BIT)
8486 {
8487 /* 32-bit/64-bit checks. */
8488 if ((i.base_reg
8489 && (addr_mode == CODE_64BIT
8490 ? !i.base_reg->reg_type.bitfield.reg64
8491 : !i.base_reg->reg_type.bitfield.reg32)
8492 && (i.index_reg
8493 || (i.base_reg->reg_num
8494 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8495 || (i.index_reg
8496 && !i.index_reg->reg_type.bitfield.regxmm
8497 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8498 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8499 && ((addr_mode == CODE_64BIT
8500 ? !(i.index_reg->reg_type.bitfield.reg64
8501 || i.index_reg->reg_num == RegRiz)
8502 : !(i.index_reg->reg_type.bitfield.reg32
8503 || i.index_reg->reg_num == RegEiz))
8504 || !i.index_reg->reg_type.bitfield.baseindex)))
8505 goto bad_address;
8506 }
8507 else
3e73aa7c 8508 {
be05d201 8509 /* 16-bit checks. */
3e73aa7c 8510 if ((i.base_reg
40fb9820
L		 8511 && (!i.base_reg->reg_type.bitfield.reg16
8512 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8513 || (i.index_reg
40fb9820
L		 8514 && (!i.index_reg->reg_type.bitfield.reg16
8515 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8516 || !(i.base_reg
8517 && i.base_reg->reg_num < 6
8518 && i.index_reg->reg_num >= 6
8519 && i.log2_scale_factor == 0))))
be05d201 8520 goto bad_address;
3e73aa7c
JH		 8521 }
8522 }
be05d201 8523 return 1;
24eab124 8524}
252b5132 8525
43234a1e
L		 8526/* Handle vector immediates. */
8527
8528static int
8529RC_SAE_immediate (const char *imm_start)
8530{
8531 unsigned int match_found, j;
8532 const char *pstr = imm_start;
8533 expressionS *exp;
8534
8535 if (*pstr != '{')
8536 return 0;
8537
8538 pstr++;
8539 match_found = 0;
8540 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8541 {
8542 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8543 {
8544 if (!i.rounding)
8545 {
8546 rc_op.type = RC_NamesTable[j].type;
8547 rc_op.operand = this_operand;
8548 i.rounding = &rc_op;
8549 }
8550 else
8551 {
8552 as_bad (_("duplicated `%s'"), imm_start);
8553 return 0;
8554 }
8555 pstr += RC_NamesTable[j].len;
8556 match_found = 1;
8557 break;
8558 }
8559 }
8560 if (!match_found)
8561 return 0;
8562
8563 if (*pstr++ != '}')
8564 {
8565 as_bad (_("Missing '}': '%s'"), imm_start);
8566 return 0;
8567 }
8568 /* RC/SAE immediate string should contain nothing more. */;
8569 if (*pstr != 0)
8570 {
8571 as_bad (_("Junk after '}': '%s'"), imm_start);
8572 return 0;
8573 }
8574
8575 exp = &im_expressions[i.imm_operands++];
8576 i.op[this_operand].imms = exp;
8577
8578 exp->X_op = O_constant;
8579 exp->X_add_number = 0;
8580 exp->X_add_symbol = (symbolS *) 0;
8581 exp->X_op_symbol = (symbolS *) 0;
8582
8583 i.types[this_operand].bitfield.imm8 = 1;
8584 return 1;
8585}
8586
fc0763e6 8587/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8588 on error. */
252b5132 8589
252b5132 8590static int
a7619375 8591i386_att_operand (char *operand_string)
252b5132 8592{
af6bdddf
AM		 8593 const reg_entry *r;
8594 char *end_op;
24eab124 8595 char *op_string = operand_string;
252b5132 8596
24eab124 8597 if (is_space_char (*op_string))
252b5132
RH		 8598 ++op_string;
8599
24eab124 8600 /* We check for an absolute prefix (differentiating,
47926f60 8601 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8602 if (*op_string == ABSOLUTE_PREFIX)
8603 {
8604 ++op_string;
8605 if (is_space_char (*op_string))
8606 ++op_string;
40fb9820 8607 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8608 }
252b5132 8609
47926f60 8610 /* Check if operand is a register. */
4d1bb795 8611 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8612 {
40fb9820
L		 8613 i386_operand_type temp;
8614
24eab124
AM		 8615 /* Check for a segment override by searching for ':' after a
8616 segment register. */
8617 op_string = end_op;
8618 if (is_space_char (*op_string))
8619 ++op_string;
40fb9820
L		 8620 if (*op_string == ':'
8621 && (r->reg_type.bitfield.sreg2
8622 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8623 {
8624 switch (r->reg_num)
8625 {
8626 case 0:
8627 i.seg[i.mem_operands] = &es;
8628 break;
8629 case 1:
8630 i.seg[i.mem_operands] = &cs;
8631 break;
8632 case 2:
8633 i.seg[i.mem_operands] = &ss;
8634 break;
8635 case 3:
8636 i.seg[i.mem_operands] = &ds;
8637 break;
8638 case 4:
8639 i.seg[i.mem_operands] = &fs;
8640 break;
8641 case 5:
8642 i.seg[i.mem_operands] = &gs;
8643 break;
8644 }
252b5132 8645
24eab124 8646 /* Skip the ':' and whitespace. */
252b5132
RH		 8647 ++op_string;
8648 if (is_space_char (*op_string))
24eab124 8649 ++op_string;
252b5132 8650
24eab124
AM		 8651 if (!is_digit_char (*op_string)
8652 && !is_identifier_char (*op_string)
8653 && *op_string != '('
8654 && *op_string != ABSOLUTE_PREFIX)
8655 {
8656 as_bad (_("bad memory operand `%s'"), op_string);
8657 return 0;
8658 }
47926f60 8659 /* Handle case of %es:*foo. */
24eab124
AM		 8660 if (*op_string == ABSOLUTE_PREFIX)
8661 {
8662 ++op_string;
8663 if (is_space_char (*op_string))
8664 ++op_string;
40fb9820 8665 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8666 }
8667 goto do_memory_reference;
8668 }
43234a1e
L		 8669
8670 /* Handle vector operations. */
8671 if (*op_string == '{')
8672 {
8673 op_string = check_VecOperations (op_string, NULL);
8674 if (op_string == NULL)
8675 return 0;
8676 }
8677
24eab124
AM		 8678 if (*op_string)
8679 {
d0b47220 8680 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8681 return 0;
8682 }
40fb9820
L		 8683 temp = r->reg_type;
8684 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8685 i.types[this_operand] = operand_type_or (i.types[this_operand],
8686 temp);
7d5e4556 8687 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8688 i.op[this_operand].regs = r;
24eab124
AM		 8689 i.reg_operands++;
8690 }
af6bdddf
AM		 8691 else if (*op_string == REGISTER_PREFIX)
8692 {
8693 as_bad (_("bad register name `%s'"), op_string);
8694 return 0;
8695 }
24eab124 8696 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8697 {
24eab124 8698 ++op_string;
40fb9820 8699 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8700 {
d0b47220 8701 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8702 return 0;
8703 }
8704 if (!i386_immediate (op_string))
8705 return 0;
8706 }
43234a1e
L		 8707 else if (RC_SAE_immediate (operand_string))
8708 {
8709 /* If it is a RC or SAE immediate, do nothing. */
8710 ;
8711 }
24eab124
AM		 8712 else if (is_digit_char (*op_string)
8713 || is_identifier_char (*op_string)
d02603dc 8714 || *op_string == '"'
e5cb08ac 8715 || *op_string == '(')
24eab124 8716 {
47926f60 8717 /* This is a memory reference of some sort. */
af6bdddf 8718 char *base_string;
252b5132 8719
47926f60 8720 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8721 char *displacement_string_start;
8722 char *displacement_string_end;
43234a1e 8723 char *vop_start;
252b5132 8724
24eab124 8725 do_memory_reference:
24eab124 8726 if ((i.mem_operands == 1
40fb9820 8727 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8728 || i.mem_operands == 2)
8729 {
8730 as_bad (_("too many memory references for `%s'"),
8731 current_templates->start->name);
8732 return 0;
8733 }
252b5132 8734
24eab124
AM		 8735 /* Check for base index form. We detect the base index form by
8736 looking for an ')' at the end of the operand, searching
8737 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8738 after the '('. */
af6bdddf 8739 base_string = op_string + strlen (op_string);
c3332e24 8740
43234a1e
L		 8741 /* Handle vector operations. */
8742 vop_start = strchr (op_string, '{');
8743 if (vop_start && vop_start < base_string)
8744 {
8745 if (check_VecOperations (vop_start, base_string) == NULL)
8746 return 0;
8747 base_string = vop_start;
8748 }
8749
af6bdddf
AM		 8750 --base_string;
8751 if (is_space_char (*base_string))
8752 --base_string;
252b5132 8753
47926f60 8754 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8755 displacement_string_start = op_string;
8756 displacement_string_end = base_string + 1;
252b5132 8757
24eab124
AM		 8758 if (*base_string == ')')
8759 {
af6bdddf 8760 char *temp_string;
24eab124
AM		 8761 unsigned int parens_balanced = 1;
8762 /* We've already checked that the number of left & right ()'s are
47926f60 8763 equal, so this loop will not be infinite. */
24eab124
AM		 8764 do
8765 {
8766 base_string--;
8767 if (*base_string == ')')
8768 parens_balanced++;
8769 if (*base_string == '(')
8770 parens_balanced--;
8771 }
8772 while (parens_balanced);
c3332e24 8773
af6bdddf 8774 temp_string = base_string;
c3332e24 8775
24eab124 8776 /* Skip past '(' and whitespace. */
252b5132
RH		 8777 ++base_string;
8778 if (is_space_char (*base_string))
24eab124 8779 ++base_string;
252b5132 8780
af6bdddf 8781 if (*base_string == ','
4eed87de
AM		 8782 || ((i.base_reg = parse_register (base_string, &end_op))
8783 != NULL))
252b5132 8784 {
af6bdddf 8785 displacement_string_end = temp_string;
252b5132 8786
40fb9820 8787 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8788
af6bdddf 8789 if (i.base_reg)
24eab124 8790 {
24eab124
AM		 8791 base_string = end_op;
8792 if (is_space_char (*base_string))
8793 ++base_string;
af6bdddf
AM		 8794 }
8795
8796 /* There may be an index reg or scale factor here. */
8797 if (*base_string == ',')
8798 {
8799 ++base_string;
8800 if (is_space_char (*base_string))
8801 ++base_string;
8802
4eed87de
AM		 8803 if ((i.index_reg = parse_register (base_string, &end_op))
8804 != NULL)
24eab124 8805 {
af6bdddf 8806 base_string = end_op;
24eab124
AM		 8807 if (is_space_char (*base_string))
8808 ++base_string;
af6bdddf
AM		 8809 if (*base_string == ',')
8810 {
8811 ++base_string;
8812 if (is_space_char (*base_string))
8813 ++base_string;
8814 }
e5cb08ac 8815 else if (*base_string != ')')
af6bdddf 8816 {
4eed87de
AM		 8817 as_bad (_("expecting `,' or `)' "
8818 "after index register in `%s'"),
af6bdddf
AM		 8819 operand_string);
8820 return 0;
8821 }
24eab124 8822 }
af6bdddf 8823 else if (*base_string == REGISTER_PREFIX)
24eab124 8824 {
f76bf5e0
L		 8825 end_op = strchr (base_string, ',');
8826 if (end_op)
8827 *end_op = '\0';
af6bdddf 8828 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8829 return 0;
8830 }
252b5132 8831
47926f60 8832 /* Check for scale factor. */
551c1ca1 8833 if (*base_string != ')')
af6bdddf 8834 {
551c1ca1
AM		 8835 char *end_scale = i386_scale (base_string);
8836
8837 if (!end_scale)
af6bdddf 8838 return 0;
24eab124 8839
551c1ca1 8840 base_string = end_scale;
af6bdddf
AM		 8841 if (is_space_char (*base_string))
8842 ++base_string;
8843 if (*base_string != ')')
8844 {
4eed87de
AM		 8845 as_bad (_("expecting `)' "
8846 "after scale factor in `%s'"),
af6bdddf
AM		 8847 operand_string);
8848 return 0;
8849 }
8850 }
8851 else if (!i.index_reg)
24eab124 8852 {
4eed87de
AM		 8853 as_bad (_("expecting index register or scale factor "
8854 "after `,'; got '%c'"),
af6bdddf 8855 *base_string);
24eab124
AM		 8856 return 0;
8857 }
8858 }
af6bdddf 8859 else if (*base_string != ')')
24eab124 8860 {
4eed87de
AM		 8861 as_bad (_("expecting `,' or `)' "
8862 "after base register in `%s'"),
af6bdddf 8863 operand_string);
24eab124
AM		 8864 return 0;
8865 }
c3332e24 8866 }
af6bdddf 8867 else if (*base_string == REGISTER_PREFIX)
c3332e24 8868 {
f76bf5e0
L		 8869 end_op = strchr (base_string, ',');
8870 if (end_op)
8871 *end_op = '\0';
af6bdddf 8872 as_bad (_("bad register name `%s'"), base_string);
24eab124 8873 return 0;
c3332e24 8874 }
24eab124
AM		 8875 }
8876
8877 /* If there's an expression beginning the operand, parse it,
8878 assuming displacement_string_start and
8879 displacement_string_end are meaningful. */
8880 if (displacement_string_start != displacement_string_end)
8881 {
8882 if (!i386_displacement (displacement_string_start,
8883 displacement_string_end))
8884 return 0;
8885 }
8886
8887 /* Special case for (%dx) while doing input/output op. */
8888 if (i.base_reg
0dfbf9d7
L		 8889 && operand_type_equal (&i.base_reg->reg_type,
8890 &reg16_inoutportreg)
24eab124
AM		 8891 && i.index_reg == 0
8892 && i.log2_scale_factor == 0
8893 && i.seg[i.mem_operands] == 0
40fb9820 8894 && !operand_type_check (i.types[this_operand], disp))
24eab124 8895 {
65da13b5 8896 i.types[this_operand] = inoutportreg;
24eab124
AM		 8897 return 1;
8898 }
8899
eecb386c
AM		 8900 if (i386_index_check (operand_string) == 0)
8901 return 0;
5c07affc 8902 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 8903 i.mem_operands++;
8904 }
8905 else
ce8a8b2f
AM		 8906 {
8907 /* It's not a memory operand; argh! */
24eab124
AM		 8908 as_bad (_("invalid char %s beginning operand %d `%s'"),
8909 output_invalid (*op_string),
8910 this_operand + 1,
8911 op_string);
8912 return 0;
8913 }
47926f60 8914 return 1; /* Normal return. */
252b5132
RH		 8915}
8916\f
fa94de6b
RM		 8917/* Calculate the maximum variable size (i.e., excluding fr_fix)
8918 that an rs_machine_dependent frag may reach. */
8919
8920unsigned int
8921i386_frag_max_var (fragS *frag)
8922{
8923 /* The only relaxable frags are for jumps.
8924 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8925 gas_assert (frag->fr_type == rs_machine_dependent);
8926 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8927}
8928
b084df0b
L		 8929#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8930static int
8dcea932 8931elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 8932{
8933 /* STT_GNU_IFUNC symbol must go through PLT. */
8934 if ((symbol_get_bfdsym (fr_symbol)->flags
8935 & BSF_GNU_INDIRECT_FUNCTION) != 0)
8936 return 0;
8937
8938 if (!S_IS_EXTERNAL (fr_symbol))
8939 /* Symbol may be weak or local. */
8940 return !S_IS_WEAK (fr_symbol);
8941
8dcea932
L		 8942 /* Global symbols with non-default visibility can't be preempted. */
8943 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
8944 return 1;
8945
8946 if (fr_var != NO_RELOC)
8947 switch ((enum bfd_reloc_code_real) fr_var)
8948 {
8949 case BFD_RELOC_386_PLT32:
8950 case BFD_RELOC_X86_64_PLT32:
8951 /* Symbol with PLT relocatin may be preempted. */
8952 return 0;
8953 default:
8954 abort ();
8955 }
8956
b084df0b
L		 8957 /* Global symbols with default visibility in a shared library may be
8958 preempted by another definition. */
8dcea932 8959 return !shared;
b084df0b
L		 8960}
8961#endif
8962
ee7fcc42
AM		 8963/* md_estimate_size_before_relax()
8964
8965 Called just before relax() for rs_machine_dependent frags. The x86
8966 assembler uses these frags to handle variable size jump
8967 instructions.
8968
8969 Any symbol that is now undefined will not become defined.
8970 Return the correct fr_subtype in the frag.
8971 Return the initial "guess for variable size of frag" to caller.
8972 The guess is actually the growth beyond the fixed part. Whatever
8973 we do to grow the fixed or variable part contributes to our
8974 returned value. */
8975
252b5132 8976int
7016a5d5 8977md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 8978{
252b5132 8979 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 8980 check for un-relaxable symbols. On an ELF system, we can't relax
8981 an externally visible symbol, because it may be overridden by a
8982 shared library. */
8983 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 8984#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8985 || (IS_ELF
8dcea932
L		 8986 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
8987 fragP->fr_var))
fbeb56a4
DK		 8988#endif
8989#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 8990 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 8991 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 8992#endif
8993 )
252b5132 8994 {
b98ef147
AM		 8995 /* Symbol is undefined in this segment, or we need to keep a
8996 reloc so that weak symbols can be overridden. */
8997 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 8998 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 8999 unsigned char *opcode;
9000 int old_fr_fix;
f6af82bd 9001
ee7fcc42 9002 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9003 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9004 else if (size == 2)
f6af82bd
AM		 9005 reloc_type = BFD_RELOC_16_PCREL;
9006 else
9007 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9008
ee7fcc42
AM		 9009 old_fr_fix = fragP->fr_fix;
9010 opcode = (unsigned char *) fragP->fr_opcode;
9011
fddf5b5b 9012 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9013 {
fddf5b5b
AM		 9014 case UNCOND_JUMP:
9015 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9016 opcode[0] = 0xe9;
252b5132 9017 fragP->fr_fix += size;
062cd5e7
AS		 9018 fix_new (fragP, old_fr_fix, size,
9019 fragP->fr_symbol,
9020 fragP->fr_offset, 1,
9021 reloc_type);
252b5132
RH		 9022 break;
9023
fddf5b5b 9024 case COND_JUMP86:
412167cb
AM		 9025 if (size == 2
9026 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9027 {
9028 /* Negate the condition, and branch past an
9029 unconditional jump. */
9030 opcode[0] ^= 1;
9031 opcode[1] = 3;
9032 /* Insert an unconditional jump. */
9033 opcode[2] = 0xe9;
9034 /* We added two extra opcode bytes, and have a two byte
9035 offset. */
9036 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9037 fix_new (fragP, old_fr_fix + 2, 2,
9038 fragP->fr_symbol,
9039 fragP->fr_offset, 1,
9040 reloc_type);
fddf5b5b
AM		 9041 break;
9042 }
9043 /* Fall through. */
9044
9045 case COND_JUMP:
412167cb
AM		 9046 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9047 {
3e02c1cc
AM		 9048 fixS *fixP;
9049
412167cb 9050 fragP->fr_fix += 1;
3e02c1cc
AM		 9051 fixP = fix_new (fragP, old_fr_fix, 1,
9052 fragP->fr_symbol,
9053 fragP->fr_offset, 1,
9054 BFD_RELOC_8_PCREL);
9055 fixP->fx_signed = 1;
412167cb
AM		 9056 break;
9057 }
93c2a809 9058
24eab124 9059 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9060 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9061 opcode[1] = opcode[0] + 0x10;
f6af82bd 9062 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9063 /* We've added an opcode byte. */
9064 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9065 fix_new (fragP, old_fr_fix + 1, size,
9066 fragP->fr_symbol,
9067 fragP->fr_offset, 1,
9068 reloc_type);
252b5132 9069 break;
fddf5b5b
AM		 9070
9071 default:
9072 BAD_CASE (fragP->fr_subtype);
9073 break;
252b5132
RH		 9074 }
9075 frag_wane (fragP);
ee7fcc42 9076 return fragP->fr_fix - old_fr_fix;
252b5132 9077 }
93c2a809 9078
93c2a809
AM		 9079 /* Guess size depending on current relax state. Initially the relax
9080 state will correspond to a short jump and we return 1, because
9081 the variable part of the frag (the branch offset) is one byte
9082 long. However, we can relax a section more than once and in that
9083 case we must either set fr_subtype back to the unrelaxed state,
9084 or return the value for the appropriate branch. */
9085 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9086}
9087
47926f60
KH		 9088/* Called after relax() is finished.
9089
9090 In: Address of frag.
9091 fr_type == rs_machine_dependent.
9092 fr_subtype is what the address relaxed to.
9093
9094 Out: Any fixSs and constants are set up.
9095 Caller will turn frag into a ".space 0". */
9096
252b5132 9097void
7016a5d5
TG		 9098md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9099 fragS *fragP)
252b5132 9100{
29b0f896 9101 unsigned char *opcode;
252b5132 9102 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9103 offsetT target_address;
9104 offsetT opcode_address;
252b5132 9105 unsigned int extension = 0;
847f7ad4 9106 offsetT displacement_from_opcode_start;
252b5132
RH		 9107
9108 opcode = (unsigned char *) fragP->fr_opcode;
9109
47926f60 9110 /* Address we want to reach in file space. */
252b5132 9111 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9112
47926f60 9113 /* Address opcode resides at in file space. */
252b5132
RH		 9114 opcode_address = fragP->fr_address + fragP->fr_fix;
9115
47926f60 9116 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9117 displacement_from_opcode_start = target_address - opcode_address;
9118
fddf5b5b 9119 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9120 {
47926f60
KH		 9121 /* Don't have to change opcode. */
9122 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9123 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9124 }
9125 else
9126 {
9127 if (no_cond_jump_promotion
9128 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9129 as_warn_where (fragP->fr_file, fragP->fr_line,
9130 _("long jump required"));
252b5132 9131
fddf5b5b
AM		 9132 switch (fragP->fr_subtype)
9133 {
9134 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9135 extension = 4; /* 1 opcode + 4 displacement */
9136 opcode[0] = 0xe9;
9137 where_to_put_displacement = &opcode[1];
9138 break;
252b5132 9139
fddf5b5b
AM		 9140 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9141 extension = 2; /* 1 opcode + 2 displacement */
9142 opcode[0] = 0xe9;
9143 where_to_put_displacement = &opcode[1];
9144 break;
252b5132 9145
fddf5b5b
AM		 9146 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9147 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9148 extension = 5; /* 2 opcode + 4 displacement */
9149 opcode[1] = opcode[0] + 0x10;
9150 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9151 where_to_put_displacement = &opcode[2];
9152 break;
252b5132 9153
fddf5b5b
AM		 9154 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9155 extension = 3; /* 2 opcode + 2 displacement */
9156 opcode[1] = opcode[0] + 0x10;
9157 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9158 where_to_put_displacement = &opcode[2];
9159 break;
252b5132 9160
fddf5b5b
AM		 9161 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9162 extension = 4;
9163 opcode[0] ^= 1;
9164 opcode[1] = 3;
9165 opcode[2] = 0xe9;
9166 where_to_put_displacement = &opcode[3];
9167 break;
9168
9169 default:
9170 BAD_CASE (fragP->fr_subtype);
9171 break;
9172 }
252b5132 9173 }
fddf5b5b 9174
7b81dfbb
AJ		 9175 /* If size if less then four we are sure that the operand fits,
9176 but if it's 4, then it could be that the displacement is larger
9177 then -/+ 2GB. */
9178 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9179 && object_64bit
9180 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9181 + ((addressT) 1 << 31))
9182 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9183 {
9184 as_bad_where (fragP->fr_file, fragP->fr_line,
9185 _("jump target out of range"));
9186 /* Make us emit 0. */
9187 displacement_from_opcode_start = extension;
9188 }
47926f60 9189 /* Now put displacement after opcode. */
252b5132
RH		 9190 md_number_to_chars ((char *) where_to_put_displacement,
9191 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9192 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9193 fragP->fr_fix += extension;
9194}
9195\f
7016a5d5 9196/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9197 by our caller that we have all the info we need to fix it up.
9198
7016a5d5
TG		 9199 Parameter valP is the pointer to the value of the bits.
9200
252b5132
RH		 9201 On the 386, immediates, displacements, and data pointers are all in
9202 the same (little-endian) format, so we don't need to care about which
9203 we are handling. */
9204
94f592af 9205void
7016a5d5 9206md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9207{
94f592af 9208 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9209 valueT value = *valP;
252b5132 9210
f86103b7 9211#if !defined (TE_Mach)
93382f6d
AM		 9212 if (fixP->fx_pcrel)
9213 {
9214 switch (fixP->fx_r_type)
9215 {
5865bb77
ILT		 9216 default:
9217 break;
9218
d6ab8113
JB		 9219 case BFD_RELOC_64:
9220 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9221 break;
93382f6d 9222 case BFD_RELOC_32:
ae8887b5 9223 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9224 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9225 break;
9226 case BFD_RELOC_16:
9227 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9228 break;
9229 case BFD_RELOC_8:
9230 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9231 break;
9232 }
9233 }
252b5132 9234
a161fe53 9235 if (fixP->fx_addsy != NULL
31312f95 9236 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9237 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9238 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9239 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9240 && !use_rela_relocations)
252b5132 9241 {
31312f95
AM		 9242 /* This is a hack. There should be a better way to handle this.
9243 This covers for the fact that bfd_install_relocation will
9244 subtract the current location (for partial_inplace, PC relative
9245 relocations); see more below. */
252b5132 9246#ifndef OBJ_AOUT
718ddfc0 9247 if (IS_ELF
252b5132
RH		 9248#ifdef TE_PE
9249 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9250#endif
9251 )
9252 value += fixP->fx_where + fixP->fx_frag->fr_address;
9253#endif
9254#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9255 if (IS_ELF)
252b5132 9256 {
6539b54b 9257 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9258
6539b54b 9259 if ((sym_seg == seg
2f66722d 9260 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9261 && sym_seg != absolute_section))
af65af87 9262 && !generic_force_reloc (fixP))
2f66722d
AM		 9263 {
9264 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9265 bfd_install_relocation subtracts them out again. I think
9266 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9267 it. FIXME. */
9268 value += fixP->fx_where + fixP->fx_frag->fr_address;
9269 }
252b5132
RH		 9270 }
9271#endif
9272#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9273 /* For some reason, the PE format does not store a
9274 section address offset for a PC relative symbol. */
9275 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9276 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9277 value += md_pcrel_from (fixP);
9278#endif
9279 }
fbeb56a4 9280#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9281 if (fixP->fx_addsy != NULL
9282 && S_IS_WEAK (fixP->fx_addsy)
9283 /* PR 16858: Do not modify weak function references. */
9284 && ! fixP->fx_pcrel)
fbeb56a4 9285 {
296a8689
NC		 9286#if !defined (TE_PEP)
9287 /* For x86 PE weak function symbols are neither PC-relative
9288 nor do they set S_IS_FUNCTION. So the only reliable way
9289 to detect them is to check the flags of their containing
9290 section. */
9291 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9292 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9293 ;
9294 else
9295#endif
fbeb56a4
DK		 9296 value -= S_GET_VALUE (fixP->fx_addsy);
9297 }
9298#endif
252b5132
RH		 9299
9300 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9301 and we must not disappoint it. */
252b5132 9302#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9303 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9304 switch (fixP->fx_r_type)
9305 {
9306 case BFD_RELOC_386_PLT32:
3e73aa7c 9307 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9308 /* Make the jump instruction point to the address of the operand. At
9309 runtime we merely add the offset to the actual PLT entry. */
9310 value = -4;
9311 break;
31312f95 9312
13ae64f3
JJ		 9313 case BFD_RELOC_386_TLS_GD:
9314 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9315 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9316 case BFD_RELOC_386_TLS_IE:
9317 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9318 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9319 case BFD_RELOC_X86_64_TLSGD:
9320 case BFD_RELOC_X86_64_TLSLD:
9321 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9322 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9323 value = 0; /* Fully resolved at runtime. No addend. */
9324 /* Fallthrough */
9325 case BFD_RELOC_386_TLS_LE:
9326 case BFD_RELOC_386_TLS_LDO_32:
9327 case BFD_RELOC_386_TLS_LE_32:
9328 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9329 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9330 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9331 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9332 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9333 break;
9334
67a4f2b7
AO		 9335 case BFD_RELOC_386_TLS_DESC_CALL:
9336 case BFD_RELOC_X86_64_TLSDESC_CALL:
9337 value = 0; /* Fully resolved at runtime. No addend. */
9338 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9339 fixP->fx_done = 0;
9340 return;
9341
00f7efb6
JJ		 9342 case BFD_RELOC_386_GOT32:
9343 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 9344 value = 0; /* Fully resolved at runtime. No addend. */
9345 break;
47926f60
KH		 9346
9347 case BFD_RELOC_VTABLE_INHERIT:
9348 case BFD_RELOC_VTABLE_ENTRY:
9349 fixP->fx_done = 0;
94f592af 9350 return;
47926f60
KH		 9351
9352 default:
9353 break;
9354 }
9355#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9356 *valP = value;
f86103b7 9357#endif /* !defined (TE_Mach) */
3e73aa7c 9358
3e73aa7c 9359 /* Are we finished with this relocation now? */
c6682705 9360 if (fixP->fx_addsy == NULL)
3e73aa7c 9361 fixP->fx_done = 1;
fbeb56a4
DK		 9362#if defined (OBJ_COFF) && defined (TE_PE)
9363 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9364 {
9365 fixP->fx_done = 0;
9366 /* Remember value for tc_gen_reloc. */
9367 fixP->fx_addnumber = value;
9368 /* Clear out the frag for now. */
9369 value = 0;
9370 }
9371#endif
3e73aa7c
JH		 9372 else if (use_rela_relocations)
9373 {
9374 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9375 /* Remember value for tc_gen_reloc. */
9376 fixP->fx_addnumber = value;
3e73aa7c
JH		 9377 value = 0;
9378 }
f86103b7 9379
94f592af 9380 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9381}
252b5132 9382\f
6d4af3c2 9383const char *
499ac353 9384md_atof (int type, char *litP, int *sizeP)
252b5132 9385{
499ac353
NC		 9386 /* This outputs the LITTLENUMs in REVERSE order;
9387 in accord with the bigendian 386. */
9388 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9389}
9390\f
2d545b82 9391static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9392
252b5132 9393static char *
e3bb37b5 9394output_invalid (int c)
252b5132 9395{
3882b010 9396 if (ISPRINT (c))
f9f21a03
L		 9397 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9398 "'%c'", c);
252b5132 9399 else
f9f21a03 9400 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9401 "(0x%x)", (unsigned char) c);
252b5132
RH		 9402 return output_invalid_buf;
9403}
9404
af6bdddf 9405/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9406
9407static const reg_entry *
4d1bb795 9408parse_real_register (char *reg_string, char **end_op)
252b5132 9409{
af6bdddf
AM		 9410 char *s = reg_string;
9411 char *p;
252b5132
RH		 9412 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9413 const reg_entry *r;
9414
9415 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9416 if (*s == REGISTER_PREFIX)
9417 ++s;
9418
9419 if (is_space_char (*s))
9420 ++s;
9421
9422 p = reg_name_given;
af6bdddf 9423 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9424 {
9425 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9426 return (const reg_entry *) NULL;
9427 s++;
252b5132
RH		 9428 }
9429
6588847e
DN		 9430 /* For naked regs, make sure that we are not dealing with an identifier.
9431 This prevents confusing an identifier like `eax_var' with register
9432 `eax'. */
9433 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9434 return (const reg_entry *) NULL;
9435
af6bdddf 9436 *end_op = s;
252b5132
RH		 9437
9438 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9439
5f47d35b 9440 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9441 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9442 {
5f47d35b
AM		 9443 if (is_space_char (*s))
9444 ++s;
9445 if (*s == '(')
9446 {
af6bdddf 9447 ++s;
5f47d35b
AM		 9448 if (is_space_char (*s))
9449 ++s;
9450 if (*s >= '0' && *s <= '7')
9451 {
db557034 9452 int fpr = *s - '0';
af6bdddf 9453 ++s;
5f47d35b
AM		 9454 if (is_space_char (*s))
9455 ++s;
9456 if (*s == ')')
9457 {
9458 *end_op = s + 1;
1e9cc1c2 9459 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9460 know (r);
9461 return r + fpr;
5f47d35b 9462 }
5f47d35b 9463 }
47926f60 9464 /* We have "%st(" then garbage. */
5f47d35b
AM		 9465 return (const reg_entry *) NULL;
9466 }
9467 }
9468
a60de03c
JB		 9469 if (r == NULL || allow_pseudo_reg)
9470 return r;
9471
0dfbf9d7 9472 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9473 return (const reg_entry *) NULL;
9474
192dc9c6
JB		 9475 if ((r->reg_type.bitfield.reg32
9476 || r->reg_type.bitfield.sreg3
9477 || r->reg_type.bitfield.control
9478 || r->reg_type.bitfield.debug
9479 || r->reg_type.bitfield.test)
9480 && !cpu_arch_flags.bitfield.cpui386)
9481 return (const reg_entry *) NULL;
9482
309d3373
JB		 9483 if (r->reg_type.bitfield.floatreg
9484 && !cpu_arch_flags.bitfield.cpu8087
9485 && !cpu_arch_flags.bitfield.cpu287
9486 && !cpu_arch_flags.bitfield.cpu387)
9487 return (const reg_entry *) NULL;
9488
192dc9c6
JB		 9489 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9490 return (const reg_entry *) NULL;
9491
9492 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9493 return (const reg_entry *) NULL;
9494
40f12533
L		 9495 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9496 return (const reg_entry *) NULL;
9497
43234a1e
L		 9498 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9499 && !cpu_arch_flags.bitfield.cpuavx512f)
9500 return (const reg_entry *) NULL;
9501
db51cc60 9502 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9503 if (!allow_index_reg
db51cc60
L		 9504 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9505 return (const reg_entry *) NULL;
9506
43234a1e
L		 9507 /* Upper 16 vector register is only available with VREX in 64bit
9508 mode. */
9509 if ((r->reg_flags & RegVRex))
9510 {
9511 if (!cpu_arch_flags.bitfield.cpuvrex
9512 || flag_code != CODE_64BIT)
9513 return (const reg_entry *) NULL;
9514
9515 i.need_vrex = 1;
9516 }
9517
a60de03c
JB		 9518 if (((r->reg_flags & (RegRex64 | RegRex))
9519 || r->reg_type.bitfield.reg64)
40fb9820 9520 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9521 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9522 && flag_code != CODE_64BIT)
20f0a1fc 9523 return (const reg_entry *) NULL;
1ae00879 9524
b7240065
JB		 9525 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9526 return (const reg_entry *) NULL;
9527
252b5132
RH		 9528 return r;
9529}
4d1bb795
JB		 9530
9531/* REG_STRING starts *before* REGISTER_PREFIX. */
9532
9533static const reg_entry *
9534parse_register (char *reg_string, char **end_op)
9535{
9536 const reg_entry *r;
9537
9538 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9539 r = parse_real_register (reg_string, end_op);
9540 else
9541 r = NULL;
9542 if (!r)
9543 {
9544 char *save = input_line_pointer;
9545 char c;
9546 symbolS *symbolP;
9547
9548 input_line_pointer = reg_string;
d02603dc 9549 c = get_symbol_name (&reg_string);
4d1bb795
JB		 9550 symbolP = symbol_find (reg_string);
9551 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9552 {
9553 const expressionS *e = symbol_get_value_expression (symbolP);
9554
0398aac5 9555 know (e->X_op == O_register);
4eed87de 9556 know (e->X_add_number >= 0
c3fe08fa 9557 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9558 r = i386_regtab + e->X_add_number;
d3bb6b49
IT		 9559 if ((r->reg_flags & RegVRex))
9560 i.need_vrex = 1;
4d1bb795
JB		 9561 *end_op = input_line_pointer;
9562 }
9563 *input_line_pointer = c;
9564 input_line_pointer = save;
9565 }
9566 return r;
9567}
9568
9569int
9570i386_parse_name (char *name, expressionS *e, char *nextcharP)
9571{
9572 const reg_entry *r;
9573 char *end = input_line_pointer;
9574
9575 *end = *nextcharP;
9576 r = parse_register (name, &input_line_pointer);
9577 if (r && end <= input_line_pointer)
9578 {
9579 *nextcharP = *input_line_pointer;
9580 *input_line_pointer = 0;
9581 e->X_op = O_register;
9582 e->X_add_number = r - i386_regtab;
9583 return 1;
9584 }
9585 input_line_pointer = end;
9586 *end = 0;
ee86248c 9587 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9588}
9589
9590void
9591md_operand (expressionS *e)
9592{
ee86248c
JB		 9593 char *end;
9594 const reg_entry *r;
4d1bb795 9595
ee86248c
JB		 9596 switch (*input_line_pointer)
9597 {
9598 case REGISTER_PREFIX:
9599 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9600 if (r)
9601 {
9602 e->X_op = O_register;
9603 e->X_add_number = r - i386_regtab;
9604 input_line_pointer = end;
9605 }
ee86248c
JB		 9606 break;
9607
9608 case '[':
9c2799c2 9609 gas_assert (intel_syntax);
ee86248c
JB		 9610 end = input_line_pointer++;
9611 expression (e);
9612 if (*input_line_pointer == ']')
9613 {
9614 ++input_line_pointer;
9615 e->X_op_symbol = make_expr_symbol (e);
9616 e->X_add_symbol = NULL;
9617 e->X_add_number = 0;
9618 e->X_op = O_index;
9619 }
9620 else
9621 {
9622 e->X_op = O_absent;
9623 input_line_pointer = end;
9624 }
9625 break;
4d1bb795
JB		 9626 }
9627}
9628
252b5132 9629\f
4cc782b5 9630#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9631const char *md_shortopts = "kVQ:sqn";
252b5132 9632#else
12b55ccc 9633const char *md_shortopts = "qn";
252b5132 9634#endif
6e0b89ee 9635
3e73aa7c 9636#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9637#define OPTION_64 (OPTION_MD_BASE + 1)
9638#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9639#define OPTION_MARCH (OPTION_MD_BASE + 3)
9640#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9641#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9642#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9643#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9644#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9645#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9646#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9647#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9648#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9649#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9650#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9651#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9652#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9653#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9654#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 9655#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9656#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 9657#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 9658#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9659#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 9660#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
0cb4071e 9661#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
b3b91714 9662
99ad8390
NC		 9663struct option md_longopts[] =
9664{
3e73aa7c 9665 {"32", no_argument, NULL, OPTION_32},
321098a5 9666#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9667 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9668 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9669#endif
9670#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9671 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 9672 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 9673#endif
b3b91714 9674 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9675 {"march", required_argument, NULL, OPTION_MARCH},
9676 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9677 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9678 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9679 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9680 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9681 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9682 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9683 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9684 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9685 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9686 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9687 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9688 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9689# if defined (TE_PE) || defined (TE_PEP)
9690 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9691#endif
d1982f93 9692 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 9693 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 9694 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 9695 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 9696 {"mamd64", no_argument, NULL, OPTION_MAMD64},
9697 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 9698 {NULL, no_argument, NULL, 0}
9699};
9700size_t md_longopts_size = sizeof (md_longopts);
9701
9702int
17b9d67d 9703md_parse_option (int c, const char *arg)
252b5132 9704{
91d6fa6a 9705 unsigned int j;
6305a203 9706 char *arch, *next;
9103f4f4 9707
252b5132
RH		 9708 switch (c)
9709 {
12b55ccc
L		 9710 case 'n':
9711 optimize_align_code = 0;
9712 break;
9713
a38cf1db
AM		 9714 case 'q':
9715 quiet_warnings = 1;
252b5132
RH		 9716 break;
9717
9718#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9719 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9720 should be emitted or not. FIXME: Not implemented. */
9721 case 'Q':
252b5132
RH		 9722 break;
9723
9724 /* -V: SVR4 argument to print version ID. */
9725 case 'V':
9726 print_version_id ();
9727 break;
9728
a38cf1db
AM		 9729 /* -k: Ignore for FreeBSD compatibility. */
9730 case 'k':
252b5132 9731 break;
4cc782b5
ILT		 9732
9733 case 's':
9734 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9735 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9736 break;
8dcea932
L		 9737
9738 case OPTION_MSHARED:
9739 shared = 1;
9740 break;
99ad8390 9741#endif
321098a5 9742#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9743 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9744 case OPTION_64:
9745 {
9746 const char **list, **l;
9747
3e73aa7c
JH		 9748 list = bfd_target_list ();
9749 for (l = list; *l != NULL; l++)
8620418b 9750 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9751 || strcmp (*l, "coff-x86-64") == 0
9752 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9753 || strcmp (*l, "pei-x86-64") == 0
9754 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9755 {
9756 default_arch = "x86_64";
9757 break;
9758 }
3e73aa7c 9759 if (*l == NULL)
2b5d6a91 9760 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9761 free (list);
9762 }
9763 break;
9764#endif
252b5132 9765
351f65ca 9766#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9767 case OPTION_X32:
351f65ca
L		 9768 if (IS_ELF)
9769 {
9770 const char **list, **l;
9771
9772 list = bfd_target_list ();
9773 for (l = list; *l != NULL; l++)
9774 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9775 {
9776 default_arch = "x86_64:32";
9777 break;
9778 }
9779 if (*l == NULL)
2b5d6a91 9780 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9781 free (list);
9782 }
9783 else
9784 as_fatal (_("32bit x86_64 is only supported for ELF"));
9785 break;
9786#endif
9787
6e0b89ee
AM		 9788 case OPTION_32:
9789 default_arch = "i386";
9790 break;
9791
b3b91714
AM		 9792 case OPTION_DIVIDE:
9793#ifdef SVR4_COMMENT_CHARS
9794 {
9795 char *n, *t;
9796 const char *s;
9797
9798 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
9799 t = n;
9800 for (s = i386_comment_chars; *s != '\0'; s++)
9801 if (*s != '/')
9802 *t++ = *s;
9803 *t = '\0';
9804 i386_comment_chars = n;
9805 }
9806#endif
9807 break;
9808
9103f4f4 9809 case OPTION_MARCH:
6305a203
L		 9810 arch = xstrdup (arg);
9811 do
9103f4f4 9812 {
6305a203 9813 if (*arch == '.')
2b5d6a91 9814 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9815 next = strchr (arch, '+');
9816 if (next)
9817 *next++ = '\0';
91d6fa6a 9818 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9819 {
91d6fa6a 9820 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9821 {
6305a203 9822 /* Processor. */
1ded5609
JB		 9823 if (! cpu_arch[j].flags.bitfield.cpui386)
9824 continue;
9825
91d6fa6a 9826 cpu_arch_name = cpu_arch[j].name;
6305a203 9827 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9828 cpu_arch_flags = cpu_arch[j].flags;
9829 cpu_arch_isa = cpu_arch[j].type;
9830 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9831 if (!cpu_arch_tune_set)
9832 {
9833 cpu_arch_tune = cpu_arch_isa;
9834 cpu_arch_tune_flags = cpu_arch_isa_flags;
9835 }
9836 break;
9837 }
91d6fa6a
NC		 9838 else if (*cpu_arch [j].name == '.'
9839 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9840 {
9841 /* ISA entension. */
9842 i386_cpu_flags flags;
309d3373 9843
49021df2 9844 if (!cpu_arch[j].negated)
309d3373 9845 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 9846 cpu_arch[j].flags);
309d3373
JB		 9847 else
9848 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 9849 cpu_arch[j].flags);
81486035
L		 9850
9851 if (!valid_iamcu_cpu_flags (&flags))
9852 as_fatal (_("`%s' isn't valid for Intel MCU"), arch);
9853 else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 9854 {
9855 if (cpu_sub_arch_name)
9856 {
9857 char *name = cpu_sub_arch_name;
9858 cpu_sub_arch_name = concat (name,
91d6fa6a 9859 cpu_arch[j].name,
1bf57e9f 9860 (const char *) NULL);
6305a203
L		 9861 free (name);
9862 }
9863 else
91d6fa6a 9864 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 9865 cpu_arch_flags = flags;
a586129e 9866 cpu_arch_isa_flags = flags;
6305a203
L		 9867 }
9868 break;
ccc9c027 9869 }
9103f4f4 9870 }
6305a203 9871
91d6fa6a 9872 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9873 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9874
9875 arch = next;
9103f4f4 9876 }
6305a203 9877 while (next != NULL );
9103f4f4
L		 9878 break;
9879
9880 case OPTION_MTUNE:
9881 if (*arg == '.')
2b5d6a91 9882 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 9883 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9884 {
91d6fa6a 9885 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 9886 {
ccc9c027 9887 cpu_arch_tune_set = 1;
91d6fa6a
NC		 9888 cpu_arch_tune = cpu_arch [j].type;
9889 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 9890 break;
9891 }
9892 }
91d6fa6a 9893 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9894 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 9895 break;
9896
1efbbeb4
L		 9897 case OPTION_MMNEMONIC:
9898 if (strcasecmp (arg, "att") == 0)
9899 intel_mnemonic = 0;
9900 else if (strcasecmp (arg, "intel") == 0)
9901 intel_mnemonic = 1;
9902 else
2b5d6a91 9903 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 9904 break;
9905
9906 case OPTION_MSYNTAX:
9907 if (strcasecmp (arg, "att") == 0)
9908 intel_syntax = 0;
9909 else if (strcasecmp (arg, "intel") == 0)
9910 intel_syntax = 1;
9911 else
2b5d6a91 9912 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 9913 break;
9914
9915 case OPTION_MINDEX_REG:
9916 allow_index_reg = 1;
9917 break;
9918
9919 case OPTION_MNAKED_REG:
9920 allow_naked_reg = 1;
9921 break;
9922
9923 case OPTION_MOLD_GCC:
9924 old_gcc = 1;
1efbbeb4
L		 9925 break;
9926
c0f3af97
L		 9927 case OPTION_MSSE2AVX:
9928 sse2avx = 1;
9929 break;
9930
daf50ae7
L		 9931 case OPTION_MSSE_CHECK:
9932 if (strcasecmp (arg, "error") == 0)
7bab8ab5 9933 sse_check = check_error;
daf50ae7 9934 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 9935 sse_check = check_warning;
daf50ae7 9936 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 9937 sse_check = check_none;
daf50ae7 9938 else
2b5d6a91 9939 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 9940 break;
9941
7bab8ab5
JB		 9942 case OPTION_MOPERAND_CHECK:
9943 if (strcasecmp (arg, "error") == 0)
9944 operand_check = check_error;
9945 else if (strcasecmp (arg, "warning") == 0)
9946 operand_check = check_warning;
9947 else if (strcasecmp (arg, "none") == 0)
9948 operand_check = check_none;
9949 else
9950 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
9951 break;
9952
539f890d
L		 9953 case OPTION_MAVXSCALAR:
9954 if (strcasecmp (arg, "128") == 0)
9955 avxscalar = vex128;
9956 else if (strcasecmp (arg, "256") == 0)
9957 avxscalar = vex256;
9958 else
2b5d6a91 9959 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 9960 break;
9961
7e8b059b
L		 9962 case OPTION_MADD_BND_PREFIX:
9963 add_bnd_prefix = 1;
9964 break;
9965
43234a1e
L		 9966 case OPTION_MEVEXLIG:
9967 if (strcmp (arg, "128") == 0)
9968 evexlig = evexl128;
9969 else if (strcmp (arg, "256") == 0)
9970 evexlig = evexl256;
9971 else if (strcmp (arg, "512") == 0)
9972 evexlig = evexl512;
9973 else
9974 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
9975 break;
9976
d3d3c6db
IT		 9977 case OPTION_MEVEXRCIG:
9978 if (strcmp (arg, "rne") == 0)
9979 evexrcig = rne;
9980 else if (strcmp (arg, "rd") == 0)
9981 evexrcig = rd;
9982 else if (strcmp (arg, "ru") == 0)
9983 evexrcig = ru;
9984 else if (strcmp (arg, "rz") == 0)
9985 evexrcig = rz;
9986 else
9987 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
9988 break;
9989
43234a1e
L		 9990 case OPTION_MEVEXWIG:
9991 if (strcmp (arg, "0") == 0)
9992 evexwig = evexw0;
9993 else if (strcmp (arg, "1") == 0)
9994 evexwig = evexw1;
9995 else
9996 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
9997 break;
9998
167ad85b
TG		 9999# if defined (TE_PE) || defined (TE_PEP)
10000 case OPTION_MBIG_OBJ:
10001 use_big_obj = 1;
10002 break;
10003#endif
10004
d1982f93 10005 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10006 if (strcasecmp (arg, "yes") == 0)
10007 omit_lock_prefix = 1;
10008 else if (strcasecmp (arg, "no") == 0)
10009 omit_lock_prefix = 0;
10010 else
10011 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10012 break;
10013
e4e00185
AS		 10014 case OPTION_MFENCE_AS_LOCK_ADD:
10015 if (strcasecmp (arg, "yes") == 0)
10016 avoid_fence = 1;
10017 else if (strcasecmp (arg, "no") == 0)
10018 avoid_fence = 0;
10019 else
10020 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10021 break;
10022
0cb4071e
L		 10023 case OPTION_MRELAX_RELOCATIONS:
10024 if (strcasecmp (arg, "yes") == 0)
10025 generate_relax_relocations = 1;
10026 else if (strcasecmp (arg, "no") == 0)
10027 generate_relax_relocations = 0;
10028 else
10029 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10030 break;
10031
5db04b09
L		 10032 case OPTION_MAMD64:
10033 cpu_arch_flags.bitfield.cpuamd64 = 1;
10034 cpu_arch_flags.bitfield.cpuintel64 = 0;
10035 cpu_arch_isa_flags.bitfield.cpuamd64 = 1;
10036 cpu_arch_isa_flags.bitfield.cpuintel64 = 0;
10037 break;
10038
10039 case OPTION_MINTEL64:
10040 cpu_arch_flags.bitfield.cpuamd64 = 0;
10041 cpu_arch_flags.bitfield.cpuintel64 = 1;
10042 cpu_arch_isa_flags.bitfield.cpuamd64 = 0;
10043 cpu_arch_isa_flags.bitfield.cpuintel64 = 1;
10044 break;
10045
252b5132
RH		 10046 default:
10047 return 0;
10048 }
10049 return 1;
10050}
10051
8a2c8fef
L		 10052#define MESSAGE_TEMPLATE \
10053" "
10054
10055static void
1ded5609 10056show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10057{
10058 static char message[] = MESSAGE_TEMPLATE;
10059 char *start = message + 27;
10060 char *p;
10061 int size = sizeof (MESSAGE_TEMPLATE);
10062 int left;
10063 const char *name;
10064 int len;
10065 unsigned int j;
10066
10067 p = start;
10068 left = size - (start - message);
10069 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10070 {
10071 /* Should it be skipped? */
10072 if (cpu_arch [j].skip)
10073 continue;
10074
10075 name = cpu_arch [j].name;
10076 len = cpu_arch [j].len;
10077 if (*name == '.')
10078 {
10079 /* It is an extension. Skip if we aren't asked to show it. */
10080 if (ext)
10081 {
10082 name++;
10083 len--;
10084 }
10085 else
10086 continue;
10087 }
10088 else if (ext)
10089 {
10090 /* It is an processor. Skip if we show only extension. */
10091 continue;
10092 }
1ded5609
JB		 10093 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10094 {
10095 /* It is an impossible processor - skip. */
10096 continue;
10097 }
8a2c8fef
L		 10098
10099 /* Reserve 2 spaces for ", " or ",\0" */
10100 left -= len + 2;
10101
10102 /* Check if there is any room. */
10103 if (left >= 0)
10104 {
10105 if (p != start)
10106 {
10107 *p++ = ',';
10108 *p++ = ' ';
10109 }
10110 p = mempcpy (p, name, len);
10111 }
10112 else
10113 {
10114 /* Output the current message now and start a new one. */
10115 *p++ = ',';
10116 *p = '\0';
10117 fprintf (stream, "%s\n", message);
10118 p = start;
10119 left = size - (start - message) - len - 2;
8d63c93e 10120
8a2c8fef
L		 10121 gas_assert (left >= 0);
10122
10123 p = mempcpy (p, name, len);
10124 }
10125 }
10126
10127 *p = '\0';
10128 fprintf (stream, "%s\n", message);
10129}
10130
252b5132 10131void
8a2c8fef 10132md_show_usage (FILE *stream)
252b5132 10133{
4cc782b5
ILT		 10134#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10135 fprintf (stream, _("\
a38cf1db
AM		 10136 -Q ignored\n\
10137 -V print assembler version number\n\
b3b91714
AM		 10138 -k ignored\n"));
10139#endif
10140 fprintf (stream, _("\
12b55ccc 10141 -n Do not optimize code alignment\n\
b3b91714
AM		 10142 -q quieten some warnings\n"));
10143#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10144 fprintf (stream, _("\
a38cf1db 10145 -s ignored\n"));
b3b91714 10146#endif
321098a5
L		 10147#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10148 || defined (TE_PE) || defined (TE_PEP))
751d281c 10149 fprintf (stream, _("\
570561f7 10150 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10151#endif
b3b91714
AM		 10152#ifdef SVR4_COMMENT_CHARS
10153 fprintf (stream, _("\
10154 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10155#else
10156 fprintf (stream, _("\
b3b91714 10157 --divide ignored\n"));
4cc782b5 10158#endif
9103f4f4 10159 fprintf (stream, _("\
6305a203 10160 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10161 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10162 show_arch (stream, 0, 1);
8a2c8fef
L		 10163 fprintf (stream, _("\
10164 EXTENSION is combination of:\n"));
1ded5609 10165 show_arch (stream, 1, 0);
6305a203 10166 fprintf (stream, _("\
8a2c8fef 10167 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10168 show_arch (stream, 0, 0);
ba104c83 10169 fprintf (stream, _("\
c0f3af97
L		 10170 -msse2avx encode SSE instructions with VEX prefix\n"));
10171 fprintf (stream, _("\
daf50ae7
L		 10172 -msse-check=[none|error|warning]\n\
10173 check SSE instructions\n"));
10174 fprintf (stream, _("\
7bab8ab5
JB		 10175 -moperand-check=[none|error|warning]\n\
10176 check operand combinations for validity\n"));
10177 fprintf (stream, _("\
539f890d
L		 10178 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10179 length\n"));
10180 fprintf (stream, _("\
43234a1e
L		 10181 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10182 length\n"));
10183 fprintf (stream, _("\
10184 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10185 for EVEX.W bit ignored instructions\n"));
10186 fprintf (stream, _("\
d3d3c6db
IT		 10187 -mevexrcig=[rne|rd|ru|rz]\n\
10188 encode EVEX instructions with specific EVEX.RC value\n\
10189 for SAE-only ignored instructions\n"));
10190 fprintf (stream, _("\
ba104c83
L		 10191 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10192 fprintf (stream, _("\
10193 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10194 fprintf (stream, _("\
10195 -mindex-reg support pseudo index registers\n"));
10196 fprintf (stream, _("\
10197 -mnaked-reg don't require `%%' prefix for registers\n"));
10198 fprintf (stream, _("\
10199 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10200 fprintf (stream, _("\
10201 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10202 fprintf (stream, _("\
10203 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10204# if defined (TE_PE) || defined (TE_PEP)
10205 fprintf (stream, _("\
10206 -mbig-obj generate big object files\n"));
10207#endif
d022bddd
IT		 10208 fprintf (stream, _("\
10209 -momit-lock-prefix=[no|yes]\n\
10210 strip all lock prefixes\n"));
5db04b09 10211 fprintf (stream, _("\
e4e00185
AS		 10212 -mfence-as-lock-add=[no|yes]\n\
10213 encode lfence, mfence and sfence as\n\
10214 lock addl $0x0, (%%{re}sp)\n"));
10215 fprintf (stream, _("\
0cb4071e
L		 10216 -mrelax-relocations=[no|yes]\n\
10217 generate relax relocations\n"));
10218 fprintf (stream, _("\
5db04b09
L		 10219 -mamd64 accept only AMD64 ISA\n"));
10220 fprintf (stream, _("\
10221 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10222}
10223
3e73aa7c 10224#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10225 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10226 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10227
10228/* Pick the target format to use. */
10229
47926f60 10230const char *
e3bb37b5 10231i386_target_format (void)
252b5132 10232{
351f65ca
L		 10233 if (!strncmp (default_arch, "x86_64", 6))
10234 {
10235 update_code_flag (CODE_64BIT, 1);
10236 if (default_arch[6] == '\0')
7f56bc95 10237 x86_elf_abi = X86_64_ABI;
351f65ca 10238 else
7f56bc95 10239 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10240 }
3e73aa7c 10241 else if (!strcmp (default_arch, "i386"))
78f12dd3 10242 update_code_flag (CODE_32BIT, 1);
5197d474
L		 10243 else if (!strcmp (default_arch, "iamcu"))
10244 {
10245 update_code_flag (CODE_32BIT, 1);
10246 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10247 {
10248 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10249 cpu_arch_name = "iamcu";
10250 cpu_sub_arch_name = NULL;
10251 cpu_arch_flags = iamcu_flags;
10252 cpu_arch_isa = PROCESSOR_IAMCU;
10253 cpu_arch_isa_flags = iamcu_flags;
10254 if (!cpu_arch_tune_set)
10255 {
10256 cpu_arch_tune = cpu_arch_isa;
10257 cpu_arch_tune_flags = cpu_arch_isa_flags;
10258 }
10259 }
10260 else
10261 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10262 cpu_arch_name);
10263 }
3e73aa7c 10264 else
2b5d6a91 10265 as_fatal (_("unknown architecture"));
89507696
JB		 10266
10267 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10268 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10269 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10270 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10271
252b5132
RH		 10272 switch (OUTPUT_FLAVOR)
10273 {
9384f2ff 10274#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10275 case bfd_target_aout_flavour:
47926f60 10276 return AOUT_TARGET_FORMAT;
4c63da97 10277#endif
9384f2ff
AM		 10278#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10279# if defined (TE_PE) || defined (TE_PEP)
10280 case bfd_target_coff_flavour:
167ad85b
TG		 10281 if (flag_code == CODE_64BIT)
10282 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10283 else
10284 return "pe-i386";
9384f2ff 10285# elif defined (TE_GO32)
0561d57c
JK		 10286 case bfd_target_coff_flavour:
10287 return "coff-go32";
9384f2ff 10288# else
252b5132
RH		 10289 case bfd_target_coff_flavour:
10290 return "coff-i386";
9384f2ff 10291# endif
4c63da97 10292#endif
3e73aa7c 10293#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10294 case bfd_target_elf_flavour:
3e73aa7c 10295 {
351f65ca
L		 10296 const char *format;
10297
10298 switch (x86_elf_abi)
4fa24527 10299 {
351f65ca
L		 10300 default:
10301 format = ELF_TARGET_FORMAT;
10302 break;
7f56bc95 10303 case X86_64_ABI:
351f65ca 10304 use_rela_relocations = 1;
4fa24527 10305 object_64bit = 1;
351f65ca
L		 10306 format = ELF_TARGET_FORMAT64;
10307 break;
7f56bc95 10308 case X86_64_X32_ABI:
4fa24527 10309 use_rela_relocations = 1;
351f65ca 10310 object_64bit = 1;
862be3fb 10311 disallow_64bit_reloc = 1;
351f65ca
L		 10312 format = ELF_TARGET_FORMAT32;
10313 break;
4fa24527 10314 }
3632d14b 10315 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10316 {
7f56bc95 10317 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10318 as_fatal (_("Intel L1OM is 64bit only"));
10319 return ELF_TARGET_L1OM_FORMAT;
10320 }
b49f93f6 10321 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 10322 {
10323 if (x86_elf_abi != X86_64_ABI)
10324 as_fatal (_("Intel K1OM is 64bit only"));
10325 return ELF_TARGET_K1OM_FORMAT;
10326 }
81486035
L		 10327 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10328 {
10329 if (x86_elf_abi != I386_ABI)
10330 as_fatal (_("Intel MCU is 32bit only"));
10331 return ELF_TARGET_IAMCU_FORMAT;
10332 }
8a9036a4 10333 else
351f65ca 10334 return format;
3e73aa7c 10335 }
e57f8c65
TG		 10336#endif
10337#if defined (OBJ_MACH_O)
10338 case bfd_target_mach_o_flavour:
d382c579
TG		 10339 if (flag_code == CODE_64BIT)
10340 {
10341 use_rela_relocations = 1;
10342 object_64bit = 1;
10343 return "mach-o-x86-64";
10344 }
10345 else
10346 return "mach-o-i386";
4c63da97 10347#endif
252b5132
RH		 10348 default:
10349 abort ();
10350 return NULL;
10351 }
10352}
10353
47926f60 10354#endif /* OBJ_MAYBE_ more than one */
252b5132 10355\f
252b5132 10356symbolS *
7016a5d5 10357md_undefined_symbol (char *name)
252b5132 10358{
18dc2407
ILT		 10359 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10360 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10361 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10362 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10363 {
10364 if (!GOT_symbol)
10365 {
10366 if (symbol_find (name))
10367 as_bad (_("GOT already in symbol table"));
10368 GOT_symbol = symbol_new (name, undefined_section,
10369 (valueT) 0, &zero_address_frag);
10370 };
10371 return GOT_symbol;
10372 }
252b5132
RH		 10373 return 0;
10374}
10375
10376/* Round up a section size to the appropriate boundary. */
47926f60 10377
252b5132 10378valueT
7016a5d5 10379md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10380{
4c63da97
AM		 10381#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10382 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10383 {
10384 /* For a.out, force the section size to be aligned. If we don't do
10385 this, BFD will align it for us, but it will not write out the
10386 final bytes of the section. This may be a bug in BFD, but it is
10387 easier to fix it here since that is how the other a.out targets
10388 work. */
10389 int align;
10390
10391 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 10392 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 10393 }
252b5132
RH		 10394#endif
10395
10396 return size;
10397}
10398
10399/* On the i386, PC-relative offsets are relative to the start of the
10400 next instruction. That is, the address of the offset, plus its
10401 size, since the offset is always the last part of the insn. */
10402
10403long
e3bb37b5 10404md_pcrel_from (fixS *fixP)
252b5132
RH		 10405{
10406 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10407}
10408
10409#ifndef I386COFF
10410
10411static void
e3bb37b5 10412s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10413{
29b0f896 10414 int temp;
252b5132 10415
8a75718c
JB		 10416#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10417 if (IS_ELF)
10418 obj_elf_section_change_hook ();
10419#endif
252b5132
RH		 10420 temp = get_absolute_expression ();
10421 subseg_set (bss_section, (subsegT) temp);
10422 demand_empty_rest_of_line ();
10423}
10424
10425#endif
10426
252b5132 10427void
e3bb37b5 10428i386_validate_fix (fixS *fixp)
252b5132 10429{
02a86693 10430 if (fixp->fx_subsy)
252b5132 10431 {
02a86693 10432 if (fixp->fx_subsy == GOT_symbol)
23df1078 10433 {
02a86693
L		 10434 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10435 {
10436 if (!object_64bit)
10437 abort ();
10438#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10439 if (fixp->fx_tcbit2)
56ceb5b5
L		 10440 fixp->fx_r_type = (fixp->fx_tcbit
10441 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10442 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 10443 else
10444#endif
10445 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10446 }
d6ab8113 10447 else
02a86693
L		 10448 {
10449 if (!object_64bit)
10450 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10451 else
10452 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10453 }
10454 fixp->fx_subsy = 0;
23df1078 10455 }
252b5132 10456 }
02a86693
L		 10457#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10458 else if (!object_64bit)
10459 {
10460 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
10461 && fixp->fx_tcbit2)
10462 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
10463 }
10464#endif
252b5132
RH		 10465}
10466
252b5132 10467arelent *
7016a5d5 10468tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10469{
10470 arelent *rel;
10471 bfd_reloc_code_real_type code;
10472
10473 switch (fixp->fx_r_type)
10474 {
8ce3d284 10475#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10476 case BFD_RELOC_SIZE32:
10477 case BFD_RELOC_SIZE64:
10478 if (S_IS_DEFINED (fixp->fx_addsy)
10479 && !S_IS_EXTERNAL (fixp->fx_addsy))
10480 {
10481 /* Resolve size relocation against local symbol to size of
10482 the symbol plus addend. */
10483 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10484 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10485 && !fits_in_unsigned_long (value))
10486 as_bad_where (fixp->fx_file, fixp->fx_line,
10487 _("symbol size computation overflow"));
10488 fixp->fx_addsy = NULL;
10489 fixp->fx_subsy = NULL;
10490 md_apply_fix (fixp, (valueT *) &value, NULL);
10491 return NULL;
10492 }
8ce3d284 10493#endif
8fd4256d 10494
3e73aa7c
JH		 10495 case BFD_RELOC_X86_64_PLT32:
10496 case BFD_RELOC_X86_64_GOT32:
10497 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10498 case BFD_RELOC_X86_64_GOTPCRELX:
10499 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 10500 case BFD_RELOC_386_PLT32:
10501 case BFD_RELOC_386_GOT32:
02a86693 10502 case BFD_RELOC_386_GOT32X:
252b5132
RH		 10503 case BFD_RELOC_386_GOTOFF:
10504 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10505 case BFD_RELOC_386_TLS_GD:
10506 case BFD_RELOC_386_TLS_LDM:
10507 case BFD_RELOC_386_TLS_LDO_32:
10508 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10509 case BFD_RELOC_386_TLS_IE:
10510 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10511 case BFD_RELOC_386_TLS_LE_32:
10512 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10513 case BFD_RELOC_386_TLS_GOTDESC:
10514 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10515 case BFD_RELOC_X86_64_TLSGD:
10516 case BFD_RELOC_X86_64_TLSLD:
10517 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10518 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10519 case BFD_RELOC_X86_64_GOTTPOFF:
10520 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10521 case BFD_RELOC_X86_64_TPOFF64:
10522 case BFD_RELOC_X86_64_GOTOFF64:
10523 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10524 case BFD_RELOC_X86_64_GOT64:
10525 case BFD_RELOC_X86_64_GOTPCREL64:
10526 case BFD_RELOC_X86_64_GOTPC64:
10527 case BFD_RELOC_X86_64_GOTPLT64:
10528 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10529 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10530 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10531 case BFD_RELOC_RVA:
10532 case BFD_RELOC_VTABLE_ENTRY:
10533 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10534#ifdef TE_PE
10535 case BFD_RELOC_32_SECREL:
10536#endif
252b5132
RH		 10537 code = fixp->fx_r_type;
10538 break;
dbbaec26
L		 10539 case BFD_RELOC_X86_64_32S:
10540 if (!fixp->fx_pcrel)
10541 {
10542 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10543 code = fixp->fx_r_type;
10544 break;
10545 }
252b5132 10546 default:
93382f6d 10547 if (fixp->fx_pcrel)
252b5132 10548 {
93382f6d
AM		 10549 switch (fixp->fx_size)
10550 {
10551 default:
b091f402
AM		 10552 as_bad_where (fixp->fx_file, fixp->fx_line,
10553 _("can not do %d byte pc-relative relocation"),
10554 fixp->fx_size);
93382f6d
AM		 10555 code = BFD_RELOC_32_PCREL;
10556 break;
10557 case 1: code = BFD_RELOC_8_PCREL; break;
10558 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10559 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10560#ifdef BFD64
10561 case 8: code = BFD_RELOC_64_PCREL; break;
10562#endif
93382f6d
AM		 10563 }
10564 }
10565 else
10566 {
10567 switch (fixp->fx_size)
10568 {
10569 default:
b091f402
AM		 10570 as_bad_where (fixp->fx_file, fixp->fx_line,
10571 _("can not do %d byte relocation"),
10572 fixp->fx_size);
93382f6d
AM		 10573 code = BFD_RELOC_32;
10574 break;
10575 case 1: code = BFD_RELOC_8; break;
10576 case 2: code = BFD_RELOC_16; break;
10577 case 4: code = BFD_RELOC_32; break;
937149dd 10578#ifdef BFD64
3e73aa7c 10579 case 8: code = BFD_RELOC_64; break;
937149dd 10580#endif
93382f6d 10581 }
252b5132
RH		 10582 }
10583 break;
10584 }
252b5132 10585
d182319b
JB		 10586 if ((code == BFD_RELOC_32
10587 || code == BFD_RELOC_32_PCREL
10588 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10589 && GOT_symbol
10590 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10591 {
4fa24527 10592 if (!object_64bit)
d6ab8113
JB		 10593 code = BFD_RELOC_386_GOTPC;
10594 else
10595 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10596 }
7b81dfbb
AJ		 10597 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10598 && GOT_symbol
10599 && fixp->fx_addsy == GOT_symbol)
10600 {
10601 code = BFD_RELOC_X86_64_GOTPC64;
10602 }
252b5132
RH		 10603
10604 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 10605 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10606 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10607
10608 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10609
3e73aa7c
JH		 10610 if (!use_rela_relocations)
10611 {
10612 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10613 vtable entry to be used in the relocation's section offset. */
10614 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10615 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10616#if defined (OBJ_COFF) && defined (TE_PE)
10617 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10618 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10619 else
10620#endif
c6682705 10621 rel->addend = 0;
3e73aa7c
JH		 10622 }
10623 /* Use the rela in 64bit mode. */
252b5132 10624 else
3e73aa7c 10625 {
862be3fb
L		 10626 if (disallow_64bit_reloc)
10627 switch (code)
10628 {
862be3fb
L		 10629 case BFD_RELOC_X86_64_DTPOFF64:
10630 case BFD_RELOC_X86_64_TPOFF64:
10631 case BFD_RELOC_64_PCREL:
10632 case BFD_RELOC_X86_64_GOTOFF64:
10633 case BFD_RELOC_X86_64_GOT64:
10634 case BFD_RELOC_X86_64_GOTPCREL64:
10635 case BFD_RELOC_X86_64_GOTPC64:
10636 case BFD_RELOC_X86_64_GOTPLT64:
10637 case BFD_RELOC_X86_64_PLTOFF64:
10638 as_bad_where (fixp->fx_file, fixp->fx_line,
10639 _("cannot represent relocation type %s in x32 mode"),
10640 bfd_get_reloc_code_name (code));
10641 break;
10642 default:
10643 break;
10644 }
10645
062cd5e7
AS		 10646 if (!fixp->fx_pcrel)
10647 rel->addend = fixp->fx_offset;
10648 else
10649 switch (code)
10650 {
10651 case BFD_RELOC_X86_64_PLT32:
10652 case BFD_RELOC_X86_64_GOT32:
10653 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10654 case BFD_RELOC_X86_64_GOTPCRELX:
10655 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 10656 case BFD_RELOC_X86_64_TLSGD:
10657 case BFD_RELOC_X86_64_TLSLD:
10658 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10659 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10660 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10661 rel->addend = fixp->fx_offset - fixp->fx_size;
10662 break;
10663 default:
10664 rel->addend = (section->vma
10665 - fixp->fx_size
10666 + fixp->fx_addnumber
10667 + md_pcrel_from (fixp));
10668 break;
10669 }
3e73aa7c
JH		 10670 }
10671
252b5132
RH		 10672 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10673 if (rel->howto == NULL)
10674 {
10675 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10676 _("cannot represent relocation type %s"),
252b5132
RH		 10677 bfd_get_reloc_code_name (code));
10678 /* Set howto to a garbage value so that we can keep going. */
10679 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10680 gas_assert (rel->howto != NULL);
252b5132
RH		 10681 }
10682
10683 return rel;
10684}
10685
ee86248c 10686#include "tc-i386-intel.c"
54cfded0 10687
a60de03c
JB		 10688void
10689tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10690{
a60de03c
JB		 10691 int saved_naked_reg;
10692 char saved_register_dot;
54cfded0 10693
a60de03c
JB		 10694 saved_naked_reg = allow_naked_reg;
10695 allow_naked_reg = 1;
10696 saved_register_dot = register_chars['.'];
10697 register_chars['.'] = '.';
10698 allow_pseudo_reg = 1;
10699 expression_and_evaluate (exp);
10700 allow_pseudo_reg = 0;
10701 register_chars['.'] = saved_register_dot;
10702 allow_naked_reg = saved_naked_reg;
10703
e96d56a1 10704 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10705 {
a60de03c
JB		 10706 if ((addressT) exp->X_add_number < i386_regtab_size)
10707 {
10708 exp->X_op = O_constant;
10709 exp->X_add_number = i386_regtab[exp->X_add_number]
10710 .dw2_regnum[flag_code >> 1];
10711 }
10712 else
10713 exp->X_op = O_illegal;
54cfded0 10714 }
54cfded0
AM		 10715}
10716
10717void
10718tc_x86_frame_initial_instructions (void)
10719{
a60de03c
JB		 10720 static unsigned int sp_regno[2];
10721
10722 if (!sp_regno[flag_code >> 1])
10723 {
10724 char *saved_input = input_line_pointer;
10725 char sp[][4] = {"esp", "rsp"};
10726 expressionS exp;
a4447b93 10727
a60de03c
JB		 10728 input_line_pointer = sp[flag_code >> 1];
10729 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10730 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10731 sp_regno[flag_code >> 1] = exp.X_add_number;
10732 input_line_pointer = saved_input;
10733 }
a4447b93 10734
61ff971f
L		 10735 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10736 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10737}
d2b2c203 10738
d7921315
L		 10739int
10740x86_dwarf2_addr_size (void)
10741{
10742#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10743 if (x86_elf_abi == X86_64_X32_ABI)
10744 return 4;
10745#endif
10746 return bfd_arch_bits_per_address (stdoutput) / 8;
10747}
10748
d2b2c203
DJ		 10749int
10750i386_elf_section_type (const char *str, size_t len)
10751{
10752 if (flag_code == CODE_64BIT
10753 && len == sizeof ("unwind") - 1
10754 && strncmp (str, "unwind", 6) == 0)
10755 return SHT_X86_64_UNWIND;
10756
10757 return -1;
10758}
bb41ade5 10759
ad5fec3b
EB		 10760#ifdef TE_SOLARIS
10761void
10762i386_solaris_fix_up_eh_frame (segT sec)
10763{
10764 if (flag_code == CODE_64BIT)
10765 elf_section_type (sec) = SHT_X86_64_UNWIND;
10766}
10767#endif
10768
bb41ade5
AM		 10769#ifdef TE_PE
10770void
10771tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10772{
91d6fa6a 10773 expressionS exp;
bb41ade5 10774
91d6fa6a
NC		 10775 exp.X_op = O_secrel;
10776 exp.X_add_symbol = symbol;
10777 exp.X_add_number = 0;
10778 emit_expr (&exp, size);
bb41ade5
AM		 10779}
10780#endif
3b22753a
L		 10781
10782#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10783/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10784
01e1a5bc 10785bfd_vma
6d4af3c2 10786x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 10787{
10788 if (flag_code == CODE_64BIT)
10789 {
10790 if (letter == 'l')
10791 return SHF_X86_64_LARGE;
10792
8f3bae45 10793 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10794 }
3b22753a 10795 else
8f3bae45 10796 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10797 return -1;
10798}
10799
01e1a5bc 10800bfd_vma
3b22753a
L		 10801x86_64_section_word (char *str, size_t len)
10802{
8620418b 10803 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10804 return SHF_X86_64_LARGE;
10805
10806 return -1;
10807}
10808
10809static void
10810handle_large_common (int small ATTRIBUTE_UNUSED)
10811{
10812 if (flag_code != CODE_64BIT)
10813 {
10814 s_comm_internal (0, elf_common_parse);
10815 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10816 }
10817 else
10818 {
10819 static segT lbss_section;
10820 asection *saved_com_section_ptr = elf_com_section_ptr;
10821 asection *saved_bss_section = bss_section;
10822
10823 if (lbss_section == NULL)
10824 {
10825 flagword applicable;
10826 segT seg = now_seg;
10827 subsegT subseg = now_subseg;
10828
10829 /* The .lbss section is for local .largecomm symbols. */
10830 lbss_section = subseg_new (".lbss", 0);
10831 applicable = bfd_applicable_section_flags (stdoutput);
10832 bfd_set_section_flags (stdoutput, lbss_section,
10833 applicable & SEC_ALLOC);
10834 seg_info (lbss_section)->bss = 1;
10835
10836 subseg_set (seg, subseg);
10837 }
10838
10839 elf_com_section_ptr = &_bfd_elf_large_com_section;
10840 bss_section = lbss_section;
10841
10842 s_comm_internal (0, elf_common_parse);
10843
10844 elf_com_section_ptr = saved_com_section_ptr;
10845 bss_section = saved_bss_section;
10846 }
10847}
10848#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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