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* gas/tc-avr.c: Add new devices
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
4b95cf5c 2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d
L		 68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
22109423 136 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 137}
138arch_entry;
139
78f12dd3 140static void update_code_flag (int, int);
e3bb37b5
L		 141static void set_code_flag (int);
142static void set_16bit_gcc_code_flag (int);
143static void set_intel_syntax (int);
1efbbeb4 144static void set_intel_mnemonic (int);
db51cc60 145static void set_allow_index_reg (int);
7bab8ab5 146static void set_check (int);
e3bb37b5 147static void set_cpu_arch (int);
6482c264 148#ifdef TE_PE
e3bb37b5 149static void pe_directive_secrel (int);
6482c264 150#endif
e3bb37b5
L		 151static void signed_cons (int);
152static char *output_invalid (int c);
ee86248c
JB		 153static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
154 const char *);
155static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
156 const char *);
a7619375 157static int i386_att_operand (char *);
e3bb37b5 158static int i386_intel_operand (char *, int);
ee86248c
JB		 159static int i386_intel_simplify (expressionS *);
160static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 161static const reg_entry *parse_register (char *, char **);
162static char *parse_insn (char *, char *);
163static char *parse_operands (char *, const char *);
164static void swap_operands (void);
4d456e3d 165static void swap_2_operands (int, int);
e3bb37b5
L		 166static void optimize_imm (void);
167static void optimize_disp (void);
d3ce72d0 168static const insn_template *match_template (void);
e3bb37b5
L		 169static int check_string (void);
170static int process_suffix (void);
171static int check_byte_reg (void);
172static int check_long_reg (void);
173static int check_qword_reg (void);
174static int check_word_reg (void);
175static int finalize_imm (void);
176static int process_operands (void);
177static const seg_entry *build_modrm_byte (void);
178static void output_insn (void);
179static void output_imm (fragS *, offsetT);
180static void output_disp (fragS *, offsetT);
29b0f896 181#ifndef I386COFF
e3bb37b5 182static void s_bss (int);
252b5132 183#endif
17d4e2a2
L		 184#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185static void handle_large_common (int small ATTRIBUTE_UNUSED);
186#endif
252b5132 187
a847613f 188static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 189
43234a1e
L		 190/* This struct describes rounding control and SAE in the instruction. */
191struct RC_Operation
192{
193 enum rc_type
194 {
195 rne = 0,
196 rd,
197 ru,
198 rz,
199 saeonly
200 } type;
201 int operand;
202};
203
204static struct RC_Operation rc_op;
205
206/* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209struct Mask_Operation
210{
211 const reg_entry *mask;
212 unsigned int zeroing;
213 /* The operand where this operation is associated. */
214 int operand;
215};
216
217static struct Mask_Operation mask_op;
218
219/* The struct describes broadcasting, applied to OPERAND. FACTOR is
220 broadcast factor. */
221struct Broadcast_Operation
222{
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
224 int type;
225
226 /* Index of broadcasted operand. */
227 int operand;
228};
229
230static struct Broadcast_Operation broadcast_op;
231
c0f3af97
L		 232/* VEX prefix. */
233typedef struct
234{
43234a1e
L		 235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes[4];
c0f3af97
L		 237 unsigned int length;
238 /* Destination or source register specifier. */
239 const reg_entry *register_specifier;
240} vex_prefix;
241
252b5132 242/* 'md_assemble ()' gathers together information and puts it into a
47926f60 243 i386_insn. */
252b5132 244
520dc8e8
AM		 245union i386_op
246 {
247 expressionS *disps;
248 expressionS *imms;
249 const reg_entry *regs;
250 };
251
a65babc9
L		 252enum i386_error
253 {
86e026a4 254 operand_size_mismatch,
a65babc9
L		 255 operand_type_mismatch,
256 register_type_mismatch,
257 number_of_operands_mismatch,
258 invalid_instruction_suffix,
259 bad_imm4,
260 old_gcc_only,
261 unsupported_with_intel_mnemonic,
262 unsupported_syntax,
6c30d220
L		 263 unsupported,
264 invalid_vsib_address,
7bab8ab5 265 invalid_vector_register_set,
43234a1e
L		 266 unsupported_vector_index_register,
267 unsupported_broadcast,
268 broadcast_not_on_src_operand,
269 broadcast_needed,
270 unsupported_masking,
271 mask_not_on_destination,
272 no_default_mask,
273 unsupported_rc_sae,
274 rc_sae_operand_not_last_imm,
275 invalid_register_operand,
276 try_vector_disp8
a65babc9
L		 277 };
278
252b5132
RH		 279struct _i386_insn
280 {
47926f60 281 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 282 insn_template tm;
252b5132 283
7d5e4556
L		 284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
252b5132
RH		 286 char suffix;
287
47926f60 288 /* OPERANDS gives the number of given operands. */
252b5132
RH		 289 unsigned int operands;
290
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
47926f60 293 operands. */
252b5132
RH		 294 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
295
296 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 297 use OP[i] for the corresponding operand. */
40fb9820 298 i386_operand_type types[MAX_OPERANDS];
252b5132 299
520dc8e8
AM		 300 /* Displacement expression, immediate expression, or register for each
301 operand. */
302 union i386_op op[MAX_OPERANDS];
252b5132 303
3e73aa7c
JH		 304 /* Flags for operands. */
305 unsigned int flags[MAX_OPERANDS];
306#define Operand_PCrel 1
307
252b5132 308 /* Relocation type for operand */
f86103b7 309 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 310
252b5132
RH		 311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry *base_reg;
314 const reg_entry *index_reg;
315 unsigned int log2_scale_factor;
316
317 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 318 explicit segment overrides are given. */
ce8a8b2f 319 const seg_entry *seg[2];
252b5132
RH		 320
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes;
324 unsigned char prefix[MAX_PREFIXES];
325
326 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 327 addressing modes of this insn are encoded. */
252b5132 328 modrm_byte rm;
3e73aa7c 329 rex_byte rex;
43234a1e 330 rex_byte vrex;
252b5132 331 sib_byte sib;
c0f3af97 332 vex_prefix vex;
b6169b20 333
43234a1e
L		 334 /* Masking attributes. */
335 struct Mask_Operation *mask;
336
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation *rounding;
339
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation *broadcast;
342
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift;
345
b6169b20 346 /* Swap operand in encoding. */
4473e004 347 unsigned int swap_operand;
891edac4 348
a501d77e
L		 349 /* Prefer 8bit or 32bit displacement in encoding. */
350 enum
351 {
352 disp_encoding_default = 0,
353 disp_encoding_8bit,
354 disp_encoding_32bit
355 } disp_encoding;
f8a5c266 356
d5de92cf
L		 357 /* REP prefix. */
358 const char *rep_prefix;
359
165de32a
L		 360 /* HLE prefix. */
361 const char *hle_prefix;
42164a71 362
7e8b059b
L		 363 /* Have BND prefix. */
364 const char *bnd_prefix;
365
43234a1e
L		 366 /* Need VREX to support upper 16 registers. */
367 int need_vrex;
368
891edac4 369 /* Error message. */
a65babc9 370 enum i386_error error;
252b5132
RH		 371 };
372
373typedef struct _i386_insn i386_insn;
374
43234a1e
L		 375/* Link RC type with corresponding string, that'll be looked for in
376 asm. */
377struct RC_name
378{
379 enum rc_type type;
380 const char *name;
381 unsigned int len;
382};
383
384static const struct RC_name RC_NamesTable[] =
385{
386 { rne, STRING_COMMA_LEN ("rn-sae") },
387 { rd, STRING_COMMA_LEN ("rd-sae") },
388 { ru, STRING_COMMA_LEN ("ru-sae") },
389 { rz, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly, STRING_COMMA_LEN ("sae") },
391};
392
252b5132
RH		 393/* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 395const char extra_symbol_chars[] = "*%-([{"
252b5132 396#ifdef LEX_AT
32137342
NC		 397 "@"
398#endif
399#ifdef LEX_QM
400 "?"
252b5132 401#endif
32137342 402 ;
252b5132 403
29b0f896
AM		 404#if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 406 && !defined (TE_GNU) \
29b0f896 407 && !defined (TE_LINUX) \
8d63c93e
RM		 408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
29b0f896 410 && !defined (TE_FreeBSD) \
5b806d27 411 && !defined (TE_DragonFly) \
29b0f896 412 && !defined (TE_NetBSD)))
252b5132 413/* This array holds the chars that always start a comment. If the
b3b91714
AM		 414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416const char *i386_comment_chars = "#/";
417#define SVR4_COMMENT_CHARS 1
252b5132 418#define PREFIX_SEPARATOR '\\'
252b5132 419
b3b91714
AM		 420#else
421const char *i386_comment_chars = "#";
422#define PREFIX_SEPARATOR '/'
423#endif
424
252b5132
RH		 425/* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 429 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
252b5132 432 '/' isn't otherwise defined. */
b3b91714 433const char line_comment_chars[] = "#/";
252b5132 434
63a0b638 435const char line_separator_chars[] = ";";
252b5132 436
ce8a8b2f
AM		 437/* Chars that can be used to separate mant from exp in floating point
438 nums. */
252b5132
RH		 439const char EXP_CHARS[] = "eE";
440
ce8a8b2f
AM		 441/* Chars that mean this number is a floating point constant
442 As in 0f12.456
443 or 0d1.2345e12. */
252b5132
RH		 444const char FLT_CHARS[] = "fFdDxX";
445
ce8a8b2f 446/* Tables for lexical analysis. */
252b5132
RH		 447static char mnemonic_chars[256];
448static char register_chars[256];
449static char operand_chars[256];
450static char identifier_chars[256];
451static char digit_chars[256];
452
ce8a8b2f 453/* Lexical macros. */
252b5132
RH		 454#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455#define is_operand_char(x) (operand_chars[(unsigned char) x])
456#define is_register_char(x) (register_chars[(unsigned char) x])
457#define is_space_char(x) ((x) == ' ')
458#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459#define is_digit_char(x) (digit_chars[(unsigned char) x])
460
0234cb7c 461/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 462static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
463
464/* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
47926f60 467 assembler instruction). */
252b5132 468static char save_stack[32];
ce8a8b2f 469static char *save_stack_p;
252b5132
RH		 470#define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472#define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
474
47926f60 475/* The instruction we're assembling. */
252b5132
RH		 476static i386_insn i;
477
478/* Possible templates for current insn. */
479static const templates *current_templates;
480
31b2323c
L		 481/* Per instruction expressionS buffers: max displacements & immediates. */
482static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
483static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 484
47926f60 485/* Current operand we are working on. */
ee86248c 486static int this_operand = -1;
252b5132 487
3e73aa7c
JH		 488/* We support four different modes. FLAG_CODE variable is used to distinguish
489 these. */
490
491enum flag_code {
492 CODE_32BIT,
493 CODE_16BIT,
494 CODE_64BIT };
495
496static enum flag_code flag_code;
4fa24527 497static unsigned int object_64bit;
862be3fb 498static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 499static int use_rela_relocations = 0;
500
7af8ed2d
NC		 501#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
504
351f65ca
L		 505/* The ELF ABI to use. */
506enum x86_elf_abi
507{
508 I386_ABI,
7f56bc95
L		 509 X86_64_ABI,
510 X86_64_X32_ABI
351f65ca
L		 511};
512
513static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 514#endif
351f65ca 515
47926f60
KH		 516/* 1 for intel syntax,
517 0 if att syntax. */
518static int intel_syntax = 0;
252b5132 519
1efbbeb4
L		 520/* 1 for intel mnemonic,
521 0 if att mnemonic. */
522static int intel_mnemonic = !SYSV386_COMPAT;
523
5209009a 524/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 525static int old_gcc = OLDGCC_COMPAT;
526
a60de03c
JB		 527/* 1 if pseudo registers are permitted. */
528static int allow_pseudo_reg = 0;
529
47926f60
KH		 530/* 1 if register prefix % not required. */
531static int allow_naked_reg = 0;
252b5132 532
7e8b059b
L		 533/* 1 if the assembler should add BND prefix for all control-tranferring
534 instructions supporting it, even if this prefix wasn't specified
535 explicitly. */
536static int add_bnd_prefix = 0;
537
ba104c83 538/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 539static int allow_index_reg = 0;
540
7bab8ab5 541static enum check_kind
daf50ae7 542 {
7bab8ab5
JB		 543 check_none = 0,
544 check_warning,
545 check_error
daf50ae7 546 }
7bab8ab5 547sse_check, operand_check = check_warning;
daf50ae7 548
2ca3ace5
L		 549/* Register prefix used for error message. */
550static const char *register_prefix = "%";
551
47926f60
KH		 552/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
553 leave, push, and pop instructions so that gcc has the same stack
554 frame as in 32 bit mode. */
555static char stackop_size = '\0';
eecb386c 556
12b55ccc
L		 557/* Non-zero to optimize code alignment. */
558int optimize_align_code = 1;
559
47926f60
KH		 560/* Non-zero to quieten some warnings. */
561static int quiet_warnings = 0;
a38cf1db 562
47926f60
KH		 563/* CPU name. */
564static const char *cpu_arch_name = NULL;
6305a203 565static char *cpu_sub_arch_name = NULL;
a38cf1db 566
47926f60 567/* CPU feature flags. */
40fb9820
L		 568static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
569
ccc9c027
L		 570/* If we have selected a cpu we are generating instructions for. */
571static int cpu_arch_tune_set = 0;
572
9103f4f4 573/* Cpu we are generating instructions for. */
fbf3f584 574enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 575
576/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 577static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 578
ccc9c027 579/* CPU instruction set architecture used. */
fbf3f584 580enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 581
9103f4f4 582/* CPU feature flags of instruction set architecture used. */
fbf3f584 583i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 584
fddf5b5b
AM		 585/* If set, conditional jumps are not automatically promoted to handle
586 larger than a byte offset. */
587static unsigned int no_cond_jump_promotion = 0;
588
c0f3af97
L		 589/* Encode SSE instructions with VEX prefix. */
590static unsigned int sse2avx;
591
539f890d
L		 592/* Encode scalar AVX instructions with specific vector length. */
593static enum
594 {
595 vex128 = 0,
596 vex256
597 } avxscalar;
598
43234a1e
L		 599/* Encode scalar EVEX LIG instructions with specific vector length. */
600static enum
601 {
602 evexl128 = 0,
603 evexl256,
604 evexl512
605 } evexlig;
606
607/* Encode EVEX WIG instructions with specific evex.w. */
608static enum
609 {
610 evexw0 = 0,
611 evexw1
612 } evexwig;
613
29b0f896 614/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 615static symbolS *GOT_symbol;
29b0f896 616
a4447b93
RH		 617/* The dwarf2 return column, adjusted for 32 or 64 bit. */
618unsigned int x86_dwarf2_return_column;
619
620/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
621int x86_cie_data_alignment;
622
252b5132 623/* Interface to relax_segment.
fddf5b5b
AM		 624 There are 3 major relax states for 386 jump insns because the
625 different types of jumps add different sizes to frags when we're
626 figuring out what sort of jump to choose to reach a given label. */
252b5132 627
47926f60 628/* Types. */
93c2a809
AM		 629#define UNCOND_JUMP 0
630#define COND_JUMP 1
631#define COND_JUMP86 2
fddf5b5b 632
47926f60 633/* Sizes. */
252b5132
RH		 634#define CODE16 1
635#define SMALL 0
29b0f896 636#define SMALL16 (SMALL | CODE16)
252b5132 637#define BIG 2
29b0f896 638#define BIG16 (BIG | CODE16)
252b5132
RH		 639
640#ifndef INLINE
641#ifdef __GNUC__
642#define INLINE __inline__
643#else
644#define INLINE
645#endif
646#endif
647
fddf5b5b
AM		 648#define ENCODE_RELAX_STATE(type, size) \
649 ((relax_substateT) (((type) << 2) | (size)))
650#define TYPE_FROM_RELAX_STATE(s) \
651 ((s) >> 2)
652#define DISP_SIZE_FROM_RELAX_STATE(s) \
653 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 654
655/* This table is used by relax_frag to promote short jumps to long
656 ones where necessary. SMALL (short) jumps may be promoted to BIG
657 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
658 don't allow a short jump in a 32 bit code segment to be promoted to
659 a 16 bit offset jump because it's slower (requires data size
660 prefix), and doesn't work, unless the destination is in the bottom
661 64k of the code segment (The top 16 bits of eip are zeroed). */
662
663const relax_typeS md_relax_table[] =
664{
24eab124
AM		 665 /* The fields are:
666 1) most positive reach of this state,
667 2) most negative reach of this state,
93c2a809 668 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 669 4) which index into the table to try if we can't fit into this one. */
252b5132 670
fddf5b5b 671 /* UNCOND_JUMP states. */
93c2a809
AM		 672 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
673 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
674 /* dword jmp adds 4 bytes to frag:
675 0 extra opcode bytes, 4 displacement bytes. */
252b5132 676 {0, 0, 4, 0},
93c2a809
AM		 677 /* word jmp adds 2 byte2 to frag:
678 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 679 {0, 0, 2, 0},
680
93c2a809
AM		 681 /* COND_JUMP states. */
682 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
683 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
684 /* dword conditionals adds 5 bytes to frag:
685 1 extra opcode byte, 4 displacement bytes. */
686 {0, 0, 5, 0},
fddf5b5b 687 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 688 1 extra opcode byte, 2 displacement bytes. */
689 {0, 0, 3, 0},
690
691 /* COND_JUMP86 states. */
692 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
693 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
694 /* dword conditionals adds 5 bytes to frag:
695 1 extra opcode byte, 4 displacement bytes. */
696 {0, 0, 5, 0},
697 /* word conditionals add 4 bytes to frag:
698 1 displacement byte and a 3 byte long branch insn. */
699 {0, 0, 4, 0}
252b5132
RH		 700};
701
9103f4f4
L		 702static const arch_entry cpu_arch[] =
703{
89507696
JB		 704 /* Do not replace the first two entries - i386_target_format()
705 relies on them being there in this order. */
8a2c8fef 706 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 707 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 708 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 709 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 710 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 711 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 712 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 713 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 714 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 715 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 716 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 717 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 718 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 719 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 720 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 721 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 722 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 723 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 724 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 725 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 726 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 727 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 728 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 729 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 730 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 731 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 732 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 733 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 734 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 735 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 736 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 737 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 738 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 739 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 740 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 741 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 742 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 743 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 744 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 745 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 746 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 747 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 748 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 749 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 750 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
751 CPU_K1OM_FLAGS, 0, 0 },
8a2c8fef 752 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 753 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 754 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 755 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 756 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 757 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 758 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 759 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 760 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 761 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 762 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 763 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 764 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 765 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 766 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 767 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 768 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 769 CPU_BDVER2_FLAGS, 0, 0 },
5e5c50d3
NE		 770 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
771 CPU_BDVER3_FLAGS, 0, 0 },
c7b0bd56
SE		 772 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
773 CPU_BDVER4_FLAGS, 0, 0 },
7b458c12
L		 774 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
775 CPU_BTVER1_FLAGS, 0, 0 },
776 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
777 CPU_BTVER2_FLAGS, 0, 0 },
8a2c8fef 778 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 779 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 780 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 781 CPU_287_FLAGS, 0, 0 },
8a2c8fef 782 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 783 CPU_387_FLAGS, 0, 0 },
8a2c8fef 784 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 785 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 786 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 787 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 788 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 789 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 790 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 791 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 792 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 793 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 794 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 795 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 796 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 797 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 798 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 799 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 800 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 801 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 802 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 803 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 804 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 805 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 806 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 807 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 808 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
809 CPU_AVX2_FLAGS, 0, 0 },
43234a1e
L		 810 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
811 CPU_AVX512F_FLAGS, 0, 0 },
812 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
813 CPU_AVX512CD_FLAGS, 0, 0 },
814 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
815 CPU_AVX512ER_FLAGS, 0, 0 },
816 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
817 CPU_AVX512PF_FLAGS, 0, 0 },
8a2c8fef 818 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 819 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 820 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 821 CPU_VMX_FLAGS, 0, 0 },
8729a6f6
L		 822 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
823 CPU_VMFUNC_FLAGS, 0, 0 },
8a2c8fef 824 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 825 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 826 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 827 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 828 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 829 CPU_XSAVEOPT_FLAGS, 0, 0 },
8a2c8fef 830 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 831 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 832 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 833 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 834 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 835 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 836 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 837 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 838 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 839 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 840 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 841 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 842 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
843 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 844 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 845 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 846 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 847 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 848 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 849 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 850 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 851 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 852 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 853 CPU_MOVBE_FLAGS, 0, 0 },
60aa667e
L		 854 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
855 CPU_CX16_FLAGS, 0, 0 },
8a2c8fef 856 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 857 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 858 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
859 CPU_LZCNT_FLAGS, 0, 0 },
42164a71
L		 860 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
861 CPU_HLE_FLAGS, 0, 0 },
862 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
863 CPU_RTM_FLAGS, 0, 0 },
6c30d220
L		 864 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
865 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 866 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 867 CPU_CLFLUSH_FLAGS, 0, 0 },
868 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
869 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 870 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 871 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 872 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 873 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 874 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 875 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 876 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 877 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 878 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 879 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 880 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 881 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 882 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 883 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 884 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 885 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 886 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 887 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 888 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
889 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 890 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
891 CPU_TBM_FLAGS, 0, 0 },
e2e1fcde
L		 892 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
893 CPU_ADX_FLAGS, 0, 0 },
894 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
895 CPU_RDSEED_FLAGS, 0, 0 },
896 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
897 CPU_PRFCHW_FLAGS, 0, 0 },
5c111e37
L		 898 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
899 CPU_SMAP_FLAGS, 0, 0 },
7e8b059b
L		 900 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
901 CPU_MPX_FLAGS, 0, 0 },
a0046408
L		 902 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
903 CPU_SHA_FLAGS, 0, 0 },
963f3586
IT		 904 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
905 CPU_CLFLUSHOPT_FLAGS, 0, 0 },
906 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
907 CPU_XSAVEC_FLAGS, 0, 0 },
908 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
909 CPU_XSAVES_FLAGS, 0, 0 },
dcf893b5
IT		 910 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
911 CPU_PREFETCHWT1_FLAGS, 0, 0 },
e413e4e9
AM		 912};
913
704209c0 914#ifdef I386COFF
a6c24e68
NC		 915/* Like s_lcomm_internal in gas/read.c but the alignment string
916 is allowed to be optional. */
917
918static symbolS *
919pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
920{
921 addressT align = 0;
922
923 SKIP_WHITESPACE ();
924
7ab9ffdd 925 if (needs_align
a6c24e68
NC		 926 && *input_line_pointer == ',')
927 {
928 align = parse_align (needs_align - 1);
7ab9ffdd 929
a6c24e68
NC		 930 if (align == (addressT) -1)
931 return NULL;
932 }
933 else
934 {
935 if (size >= 8)
936 align = 3;
937 else if (size >= 4)
938 align = 2;
939 else if (size >= 2)
940 align = 1;
941 else
942 align = 0;
943 }
944
945 bss_alloc (symbolP, size, align);
946 return symbolP;
947}
948
704209c0 949static void
a6c24e68
NC		 950pe_lcomm (int needs_align)
951{
952 s_comm_internal (needs_align * 2, pe_lcomm_internal);
953}
704209c0 954#endif
a6c24e68 955
29b0f896
AM		 956const pseudo_typeS md_pseudo_table[] =
957{
958#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
959 {"align", s_align_bytes, 0},
960#else
961 {"align", s_align_ptwo, 0},
962#endif
963 {"arch", set_cpu_arch, 0},
964#ifndef I386COFF
965 {"bss", s_bss, 0},
a6c24e68
NC		 966#else
967 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 968#endif
969 {"ffloat", float_cons, 'f'},
970 {"dfloat", float_cons, 'd'},
971 {"tfloat", float_cons, 'x'},
972 {"value", cons, 2},
d182319b 973 {"slong", signed_cons, 4},
29b0f896
AM		 974 {"noopt", s_ignore, 0},
975 {"optim", s_ignore, 0},
976 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
977 {"code16", set_code_flag, CODE_16BIT},
978 {"code32", set_code_flag, CODE_32BIT},
979 {"code64", set_code_flag, CODE_64BIT},
980 {"intel_syntax", set_intel_syntax, 1},
981 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 982 {"intel_mnemonic", set_intel_mnemonic, 1},
983 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 984 {"allow_index_reg", set_allow_index_reg, 1},
985 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 986 {"sse_check", set_check, 0},
987 {"operand_check", set_check, 1},
3b22753a
L		 988#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
989 {"largecomm", handle_large_common, 0},
07a53e5c 990#else
e3bb37b5 991 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 992 {"loc", dwarf2_directive_loc, 0},
993 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 994#endif
6482c264
NC		 995#ifdef TE_PE
996 {"secrel32", pe_directive_secrel, 0},
997#endif
29b0f896
AM		 998 {0, 0, 0}
999};
1000
1001/* For interface with expression (). */
1002extern char *input_line_pointer;
1003
1004/* Hash table for instruction mnemonic lookup. */
1005static struct hash_control *op_hash;
1006
1007/* Hash table for register lookup. */
1008static struct hash_control *reg_hash;
1009\f
252b5132 1010void
e3bb37b5 1011i386_align_code (fragS *fragP, int count)
252b5132 1012{
ce8a8b2f
AM		 1013 /* Various efficient no-op patterns for aligning code labels.
1014 Note: Don't try to assemble the instructions in the comments.
1015 0L and 0w are not legal. */
252b5132
RH		 1016 static const char f32_1[] =
1017 {0x90}; /* nop */
1018 static const char f32_2[] =
ccc9c027 1019 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 1020 static const char f32_3[] =
1021 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1022 static const char f32_4[] =
1023 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1024 static const char f32_5[] =
1025 {0x90, /* nop */
1026 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1027 static const char f32_6[] =
1028 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1029 static const char f32_7[] =
1030 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1031 static const char f32_8[] =
1032 {0x90, /* nop */
1033 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1034 static const char f32_9[] =
1035 {0x89,0xf6, /* movl %esi,%esi */
1036 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1037 static const char f32_10[] =
1038 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1039 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1040 static const char f32_11[] =
1041 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1042 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1043 static const char f32_12[] =
1044 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1045 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1046 static const char f32_13[] =
1047 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1048 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1049 static const char f32_14[] =
1050 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1051 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 1052 static const char f16_3[] =
1053 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 1054 static const char f16_4[] =
1055 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1056 static const char f16_5[] =
1057 {0x90, /* nop */
1058 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1059 static const char f16_6[] =
1060 {0x89,0xf6, /* mov %si,%si */
1061 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1062 static const char f16_7[] =
1063 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1064 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1065 static const char f16_8[] =
1066 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1067 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 1068 static const char jump_31[] =
1069 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1070 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1071 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1072 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 1073 static const char *const f32_patt[] = {
1074 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1075 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 1076 };
1077 static const char *const f16_patt[] = {
76bc74dc 1078 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1079 };
ccc9c027
L		 1080 /* nopl (%[re]ax) */
1081 static const char alt_3[] =
1082 {0x0f,0x1f,0x00};
1083 /* nopl 0(%[re]ax) */
1084 static const char alt_4[] =
1085 {0x0f,0x1f,0x40,0x00};
1086 /* nopl 0(%[re]ax,%[re]ax,1) */
1087 static const char alt_5[] =
1088 {0x0f,0x1f,0x44,0x00,0x00};
1089 /* nopw 0(%[re]ax,%[re]ax,1) */
1090 static const char alt_6[] =
1091 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1092 /* nopl 0L(%[re]ax) */
1093 static const char alt_7[] =
1094 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1095 /* nopl 0L(%[re]ax,%[re]ax,1) */
1096 static const char alt_8[] =
1097 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1098 /* nopw 0L(%[re]ax,%[re]ax,1) */
1099 static const char alt_9[] =
1100 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1101 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1102 static const char alt_10[] =
1103 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1104 /* data16
1105 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1106 static const char alt_long_11[] =
1107 {0x66,
1108 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1109 /* data16
1110 data16
1111 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1112 static const char alt_long_12[] =
1113 {0x66,
1114 0x66,
1115 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1116 /* data16
1117 data16
1118 data16
1119 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1120 static const char alt_long_13[] =
1121 {0x66,
1122 0x66,
1123 0x66,
1124 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1125 /* data16
1126 data16
1127 data16
1128 data16
1129 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1130 static const char alt_long_14[] =
1131 {0x66,
1132 0x66,
1133 0x66,
1134 0x66,
1135 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1136 /* data16
1137 data16
1138 data16
1139 data16
1140 data16
1141 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1142 static const char alt_long_15[] =
1143 {0x66,
1144 0x66,
1145 0x66,
1146 0x66,
1147 0x66,
1148 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1149 /* nopl 0(%[re]ax,%[re]ax,1)
1150 nopw 0(%[re]ax,%[re]ax,1) */
1151 static const char alt_short_11[] =
1152 {0x0f,0x1f,0x44,0x00,0x00,
1153 0x66,0x0f,0x1f,0x44,0x00,0x00};
1154 /* nopw 0(%[re]ax,%[re]ax,1)
1155 nopw 0(%[re]ax,%[re]ax,1) */
1156 static const char alt_short_12[] =
1157 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1158 0x66,0x0f,0x1f,0x44,0x00,0x00};
1159 /* nopw 0(%[re]ax,%[re]ax,1)
1160 nopl 0L(%[re]ax) */
1161 static const char alt_short_13[] =
1162 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1163 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1164 /* nopl 0L(%[re]ax)
1165 nopl 0L(%[re]ax) */
1166 static const char alt_short_14[] =
1167 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1168 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1169 /* nopl 0L(%[re]ax)
1170 nopl 0L(%[re]ax,%[re]ax,1) */
1171 static const char alt_short_15[] =
1172 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1173 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1174 static const char *const alt_short_patt[] = {
1175 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1176 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
1177 alt_short_14, alt_short_15
1178 };
1179 static const char *const alt_long_patt[] = {
1180 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1181 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1182 alt_long_14, alt_long_15
1183 };
252b5132 1184
76bc74dc
L		 1185 /* Only align for at least a positive non-zero boundary. */
1186 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1187 return;
3e73aa7c 1188
ccc9c027
L		 1189 /* We need to decide which NOP sequence to use for 32bit and
1190 64bit. When -mtune= is used:
4eed87de 1191
76bc74dc
L		 1192 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1193 PROCESSOR_GENERIC32, f32_patt will be used.
1194 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 1195 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1196 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 1197 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
7b458c12 1198 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
69dd9865 1199 will be used.
ccc9c027 1200
76bc74dc 1201 When -mtune= isn't used, alt_long_patt will be used if
22109423 1202 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1203 be used.
ccc9c027
L		 1204
1205 When -march= or .arch is used, we can't use anything beyond
1206 cpu_arch_isa_flags. */
1207
1208 if (flag_code == CODE_16BIT)
1209 {
ccc9c027 1210 if (count > 8)
33fef721 1211 {
76bc74dc
L		 1212 memcpy (fragP->fr_literal + fragP->fr_fix,
1213 jump_31, count);
1214 /* Adjust jump offset. */
1215 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1216 }
76bc74dc
L		 1217 else
1218 memcpy (fragP->fr_literal + fragP->fr_fix,
1219 f16_patt[count - 1], count);
252b5132 1220 }
33fef721 1221 else
ccc9c027
L		 1222 {
1223 const char *const *patt = NULL;
1224
fbf3f584 1225 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1226 {
1227 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1228 switch (cpu_arch_tune)
1229 {
1230 case PROCESSOR_UNKNOWN:
1231 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1232 optimize with nops. */
1233 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1234 patt = alt_long_patt;
ccc9c027
L		 1235 else
1236 patt = f32_patt;
1237 break;
ccc9c027
L		 1238 case PROCESSOR_PENTIUM4:
1239 case PROCESSOR_NOCONA:
ef05d495 1240 case PROCESSOR_CORE:
76bc74dc 1241 case PROCESSOR_CORE2:
bd5295b2 1242 case PROCESSOR_COREI7:
3632d14b 1243 case PROCESSOR_L1OM:
7a9068fe 1244 case PROCESSOR_K1OM:
76bc74dc
L		 1245 case PROCESSOR_GENERIC64:
1246 patt = alt_long_patt;
1247 break;
ccc9c027
L		 1248 case PROCESSOR_K6:
1249 case PROCESSOR_ATHLON:
1250 case PROCESSOR_K8:
4eed87de 1251 case PROCESSOR_AMDFAM10:
8aedb9fe 1252 case PROCESSOR_BD:
7b458c12 1253 case PROCESSOR_BT:
ccc9c027
L		 1254 patt = alt_short_patt;
1255 break;
76bc74dc 1256 case PROCESSOR_I386:
ccc9c027
L		 1257 case PROCESSOR_I486:
1258 case PROCESSOR_PENTIUM:
2dde1948 1259 case PROCESSOR_PENTIUMPRO:
ccc9c027
L		 1260 case PROCESSOR_GENERIC32:
1261 patt = f32_patt;
1262 break;
4eed87de 1263 }
ccc9c027
L		 1264 }
1265 else
1266 {
fbf3f584 1267 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1268 {
1269 case PROCESSOR_UNKNOWN:
e6a14101 1270 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1271 PROCESSOR_UNKNOWN. */
1272 abort ();
1273 break;
1274
76bc74dc 1275 case PROCESSOR_I386:
ccc9c027
L		 1276 case PROCESSOR_I486:
1277 case PROCESSOR_PENTIUM:
ccc9c027
L		 1278 case PROCESSOR_K6:
1279 case PROCESSOR_ATHLON:
1280 case PROCESSOR_K8:
4eed87de 1281 case PROCESSOR_AMDFAM10:
8aedb9fe 1282 case PROCESSOR_BD:
7b458c12 1283 case PROCESSOR_BT:
ccc9c027
L		 1284 case PROCESSOR_GENERIC32:
1285 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1286 with nops. */
1287 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1288 patt = alt_short_patt;
1289 else
1290 patt = f32_patt;
1291 break;
76bc74dc
L		 1292 case PROCESSOR_PENTIUMPRO:
1293 case PROCESSOR_PENTIUM4:
1294 case PROCESSOR_NOCONA:
1295 case PROCESSOR_CORE:
ef05d495 1296 case PROCESSOR_CORE2:
bd5295b2 1297 case PROCESSOR_COREI7:
3632d14b 1298 case PROCESSOR_L1OM:
7a9068fe 1299 case PROCESSOR_K1OM:
22109423 1300 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1301 patt = alt_long_patt;
1302 else
1303 patt = f32_patt;
1304 break;
1305 case PROCESSOR_GENERIC64:
76bc74dc 1306 patt = alt_long_patt;
ccc9c027 1307 break;
4eed87de 1308 }
ccc9c027
L		 1309 }
1310
76bc74dc
L		 1311 if (patt == f32_patt)
1312 {
1313 /* If the padding is less than 15 bytes, we use the normal
1314 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1315 its offset. */
1316 int limit;
76ba9986 1317
711eedef
L		 1318 /* For 64bit, the limit is 3 bytes. */
1319 if (flag_code == CODE_64BIT
1320 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1321 limit = 3;
1322 else
1323 limit = 15;
1324 if (count < limit)
76bc74dc
L		 1325 memcpy (fragP->fr_literal + fragP->fr_fix,
1326 patt[count - 1], count);
1327 else
1328 {
1329 memcpy (fragP->fr_literal + fragP->fr_fix,
1330 jump_31, count);
1331 /* Adjust jump offset. */
1332 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1333 }
1334 }
1335 else
1336 {
1337 /* Maximum length of an instruction is 15 byte. If the
1338 padding is greater than 15 bytes and we don't use jump,
1339 we have to break it into smaller pieces. */
1340 int padding = count;
1341 while (padding > 15)
1342 {
1343 padding -= 15;
1344 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1345 patt [14], 15);
1346 }
1347
1348 if (padding)
1349 memcpy (fragP->fr_literal + fragP->fr_fix,
1350 patt [padding - 1], padding);
1351 }
ccc9c027 1352 }
33fef721 1353 fragP->fr_var = count;
252b5132
RH		 1354}
1355
c6fb90c8 1356static INLINE int
0dfbf9d7 1357operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1358{
0dfbf9d7 1359 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1360 {
1361 case 3:
0dfbf9d7 1362 if (x->array[2])
c6fb90c8
L		 1363 return 0;
1364 case 2:
0dfbf9d7 1365 if (x->array[1])
c6fb90c8
L		 1366 return 0;
1367 case 1:
0dfbf9d7 1368 return !x->array[0];
c6fb90c8
L		 1369 default:
1370 abort ();
1371 }
40fb9820
L		 1372}
1373
c6fb90c8 1374static INLINE void
0dfbf9d7 1375operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1376{
0dfbf9d7 1377 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1378 {
1379 case 3:
0dfbf9d7 1380 x->array[2] = v;
c6fb90c8 1381 case 2:
0dfbf9d7 1382 x->array[1] = v;
c6fb90c8 1383 case 1:
0dfbf9d7 1384 x->array[0] = v;
c6fb90c8
L		 1385 break;
1386 default:
1387 abort ();
1388 }
1389}
40fb9820 1390
c6fb90c8 1391static INLINE int
0dfbf9d7
L		 1392operand_type_equal (const union i386_operand_type *x,
1393 const union i386_operand_type *y)
c6fb90c8 1394{
0dfbf9d7 1395 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1396 {
1397 case 3:
0dfbf9d7 1398 if (x->array[2] != y->array[2])
c6fb90c8
L		 1399 return 0;
1400 case 2:
0dfbf9d7 1401 if (x->array[1] != y->array[1])
c6fb90c8
L		 1402 return 0;
1403 case 1:
0dfbf9d7 1404 return x->array[0] == y->array[0];
c6fb90c8
L		 1405 break;
1406 default:
1407 abort ();
1408 }
1409}
40fb9820 1410
0dfbf9d7
L		 1411static INLINE int
1412cpu_flags_all_zero (const union i386_cpu_flags *x)
1413{
1414 switch (ARRAY_SIZE(x->array))
1415 {
1416 case 3:
1417 if (x->array[2])
1418 return 0;
1419 case 2:
1420 if (x->array[1])
1421 return 0;
1422 case 1:
1423 return !x->array[0];
1424 default:
1425 abort ();
1426 }
1427}
1428
1429static INLINE void
1430cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1431{
1432 switch (ARRAY_SIZE(x->array))
1433 {
1434 case 3:
1435 x->array[2] = v;
1436 case 2:
1437 x->array[1] = v;
1438 case 1:
1439 x->array[0] = v;
1440 break;
1441 default:
1442 abort ();
1443 }
1444}
1445
1446static INLINE int
1447cpu_flags_equal (const union i386_cpu_flags *x,
1448 const union i386_cpu_flags *y)
1449{
1450 switch (ARRAY_SIZE(x->array))
1451 {
1452 case 3:
1453 if (x->array[2] != y->array[2])
1454 return 0;
1455 case 2:
1456 if (x->array[1] != y->array[1])
1457 return 0;
1458 case 1:
1459 return x->array[0] == y->array[0];
1460 break;
1461 default:
1462 abort ();
1463 }
1464}
c6fb90c8
L		 1465
1466static INLINE int
1467cpu_flags_check_cpu64 (i386_cpu_flags f)
1468{
1469 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1470 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1471}
1472
c6fb90c8
L		 1473static INLINE i386_cpu_flags
1474cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1475{
c6fb90c8
L		 1476 switch (ARRAY_SIZE (x.array))
1477 {
1478 case 3:
1479 x.array [2] &= y.array [2];
1480 case 2:
1481 x.array [1] &= y.array [1];
1482 case 1:
1483 x.array [0] &= y.array [0];
1484 break;
1485 default:
1486 abort ();
1487 }
1488 return x;
1489}
40fb9820 1490
c6fb90c8
L		 1491static INLINE i386_cpu_flags
1492cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1493{
c6fb90c8 1494 switch (ARRAY_SIZE (x.array))
40fb9820 1495 {
c6fb90c8
L		 1496 case 3:
1497 x.array [2] |= y.array [2];
1498 case 2:
1499 x.array [1] |= y.array [1];
1500 case 1:
1501 x.array [0] |= y.array [0];
40fb9820
L		 1502 break;
1503 default:
1504 abort ();
1505 }
40fb9820
L		 1506 return x;
1507}
1508
309d3373
JB		 1509static INLINE i386_cpu_flags
1510cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1511{
1512 switch (ARRAY_SIZE (x.array))
1513 {
1514 case 3:
1515 x.array [2] &= ~y.array [2];
1516 case 2:
1517 x.array [1] &= ~y.array [1];
1518 case 1:
1519 x.array [0] &= ~y.array [0];
1520 break;
1521 default:
1522 abort ();
1523 }
1524 return x;
1525}
1526
c0f3af97
L		 1527#define CPU_FLAGS_ARCH_MATCH 0x1
1528#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1529#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1530#define CPU_FLAGS_PCLMUL_MATCH 0x8
1531#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1532
a5ff0eb2 1533#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1534 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1535 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1536#define CPU_FLAGS_PERFECT_MATCH \
1537 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1538
1539/* Return CPU flags match bits. */
3629bb00 1540
40fb9820 1541static int
d3ce72d0 1542cpu_flags_match (const insn_template *t)
40fb9820 1543{
c0f3af97
L		 1544 i386_cpu_flags x = t->cpu_flags;
1545 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1546
1547 x.bitfield.cpu64 = 0;
1548 x.bitfield.cpuno64 = 0;
1549
0dfbf9d7 1550 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1551 {
1552 /* This instruction is available on all archs. */
1553 match |= CPU_FLAGS_32BIT_MATCH;
1554 }
3629bb00
L		 1555 else
1556 {
c0f3af97 1557 /* This instruction is available only on some archs. */
3629bb00
L		 1558 i386_cpu_flags cpu = cpu_arch_flags;
1559
1560 cpu.bitfield.cpu64 = 0;
1561 cpu.bitfield.cpuno64 = 0;
1562 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1563 if (!cpu_flags_all_zero (&cpu))
1564 {
a5ff0eb2
L		 1565 if (x.bitfield.cpuavx)
1566 {
ce2f5b3c 1567 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1568 if (cpu.bitfield.cpuavx)
1569 {
1570 /* Check SSE2AVX. */
1571 if (!t->opcode_modifier.sse2avx|| sse2avx)
1572 {
1573 match |= (CPU_FLAGS_ARCH_MATCH
1574 | CPU_FLAGS_AVX_MATCH);
1575 /* Check AES. */
1576 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1577 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1578 /* Check PCLMUL. */
1579 if (!x.bitfield.cpupclmul
1580 || cpu.bitfield.cpupclmul)
1581 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1582 }
1583 }
1584 else
1585 match |= CPU_FLAGS_ARCH_MATCH;
1586 }
1587 else
c0f3af97
L		 1588 match |= CPU_FLAGS_32BIT_MATCH;
1589 }
3629bb00 1590 }
c0f3af97 1591 return match;
40fb9820
L		 1592}
1593
c6fb90c8
L		 1594static INLINE i386_operand_type
1595operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1596{
c6fb90c8
L		 1597 switch (ARRAY_SIZE (x.array))
1598 {
1599 case 3:
1600 x.array [2] &= y.array [2];
1601 case 2:
1602 x.array [1] &= y.array [1];
1603 case 1:
1604 x.array [0] &= y.array [0];
1605 break;
1606 default:
1607 abort ();
1608 }
1609 return x;
40fb9820
L		 1610}
1611
c6fb90c8
L		 1612static INLINE i386_operand_type
1613operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1614{
c6fb90c8 1615 switch (ARRAY_SIZE (x.array))
40fb9820 1616 {
c6fb90c8
L		 1617 case 3:
1618 x.array [2] |= y.array [2];
1619 case 2:
1620 x.array [1] |= y.array [1];
1621 case 1:
1622 x.array [0] |= y.array [0];
40fb9820
L		 1623 break;
1624 default:
1625 abort ();
1626 }
c6fb90c8
L		 1627 return x;
1628}
40fb9820 1629
c6fb90c8
L		 1630static INLINE i386_operand_type
1631operand_type_xor (i386_operand_type x, i386_operand_type y)
1632{
1633 switch (ARRAY_SIZE (x.array))
1634 {
1635 case 3:
1636 x.array [2] ^= y.array [2];
1637 case 2:
1638 x.array [1] ^= y.array [1];
1639 case 1:
1640 x.array [0] ^= y.array [0];
1641 break;
1642 default:
1643 abort ();
1644 }
40fb9820
L		 1645 return x;
1646}
1647
1648static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1649static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1650static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1651static const i386_operand_type inoutportreg
1652 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1653static const i386_operand_type reg16_inoutportreg
1654 = OPERAND_TYPE_REG16_INOUTPORTREG;
1655static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1656static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1657static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1658static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1659static const i386_operand_type anydisp
1660 = OPERAND_TYPE_ANYDISP;
40fb9820 1661static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1662static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1663static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1664static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1665static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1666static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1667static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1668static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1669static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1670static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1671static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1672static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1673static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1674static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1675
1676enum operand_type
1677{
1678 reg,
40fb9820
L		 1679 imm,
1680 disp,
1681 anymem
1682};
1683
c6fb90c8 1684static INLINE int
40fb9820
L		 1685operand_type_check (i386_operand_type t, enum operand_type c)
1686{
1687 switch (c)
1688 {
1689 case reg:
1690 return (t.bitfield.reg8
1691 || t.bitfield.reg16
1692 || t.bitfield.reg32
1693 || t.bitfield.reg64);
1694
40fb9820
L		 1695 case imm:
1696 return (t.bitfield.imm8
1697 || t.bitfield.imm8s
1698 || t.bitfield.imm16
1699 || t.bitfield.imm32
1700 || t.bitfield.imm32s
1701 || t.bitfield.imm64);
1702
1703 case disp:
1704 return (t.bitfield.disp8
1705 || t.bitfield.disp16
1706 || t.bitfield.disp32
1707 || t.bitfield.disp32s
1708 || t.bitfield.disp64);
1709
1710 case anymem:
1711 return (t.bitfield.disp8
1712 || t.bitfield.disp16
1713 || t.bitfield.disp32
1714 || t.bitfield.disp32s
1715 || t.bitfield.disp64
1716 || t.bitfield.baseindex);
1717
1718 default:
1719 abort ();
1720 }
2cfe26b6
AM		 1721
1722 return 0;
40fb9820
L		 1723}
1724
5c07affc
L		 1725/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1726 operand J for instruction template T. */
1727
1728static INLINE int
d3ce72d0 1729match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1730{
1731 return !((i.types[j].bitfield.byte
1732 && !t->operand_types[j].bitfield.byte)
1733 || (i.types[j].bitfield.word
1734 && !t->operand_types[j].bitfield.word)
1735 || (i.types[j].bitfield.dword
1736 && !t->operand_types[j].bitfield.dword)
1737 || (i.types[j].bitfield.qword
1738 && !t->operand_types[j].bitfield.qword));
1739}
1740
1741/* Return 1 if there is no conflict in any size on operand J for
1742 instruction template T. */
1743
1744static INLINE int
d3ce72d0 1745match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1746{
1747 return (match_reg_size (t, j)
1748 && !((i.types[j].bitfield.unspecified
1749 && !t->operand_types[j].bitfield.unspecified)
1750 || (i.types[j].bitfield.fword
1751 && !t->operand_types[j].bitfield.fword)
1752 || (i.types[j].bitfield.tbyte
1753 && !t->operand_types[j].bitfield.tbyte)
1754 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1755 && !t->operand_types[j].bitfield.xmmword)
1756 || (i.types[j].bitfield.ymmword
43234a1e
L		 1757 && !t->operand_types[j].bitfield.ymmword)
1758 || (i.types[j].bitfield.zmmword
1759 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1760}
1761
1762/* Return 1 if there is no size conflict on any operands for
1763 instruction template T. */
1764
1765static INLINE int
d3ce72d0 1766operand_size_match (const insn_template *t)
5c07affc
L		 1767{
1768 unsigned int j;
1769 int match = 1;
1770
1771 /* Don't check jump instructions. */
1772 if (t->opcode_modifier.jump
1773 || t->opcode_modifier.jumpbyte
1774 || t->opcode_modifier.jumpdword
1775 || t->opcode_modifier.jumpintersegment)
1776 return match;
1777
1778 /* Check memory and accumulator operand size. */
1779 for (j = 0; j < i.operands; j++)
1780 {
1781 if (t->operand_types[j].bitfield.anysize)
1782 continue;
1783
1784 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1785 {
1786 match = 0;
1787 break;
1788 }
1789
1790 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1791 {
1792 match = 0;
1793 break;
1794 }
1795 }
1796
891edac4 1797 if (match)
5c07affc 1798 return match;
891edac4
L		 1799 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1800 {
1801mismatch:
86e026a4 1802 i.error = operand_size_mismatch;
891edac4
L		 1803 return 0;
1804 }
5c07affc
L		 1805
1806 /* Check reverse. */
9c2799c2 1807 gas_assert (i.operands == 2);
5c07affc
L		 1808
1809 match = 1;
1810 for (j = 0; j < 2; j++)
1811 {
1812 if (t->operand_types[j].bitfield.acc
1813 && !match_reg_size (t, j ? 0 : 1))
891edac4 1814 goto mismatch;
5c07affc
L		 1815
1816 if (i.types[j].bitfield.mem
1817 && !match_mem_size (t, j ? 0 : 1))
891edac4 1818 goto mismatch;
5c07affc
L		 1819 }
1820
1821 return match;
1822}
1823
c6fb90c8 1824static INLINE int
40fb9820
L		 1825operand_type_match (i386_operand_type overlap,
1826 i386_operand_type given)
1827{
1828 i386_operand_type temp = overlap;
1829
1830 temp.bitfield.jumpabsolute = 0;
7d5e4556 1831 temp.bitfield.unspecified = 0;
5c07affc
L		 1832 temp.bitfield.byte = 0;
1833 temp.bitfield.word = 0;
1834 temp.bitfield.dword = 0;
1835 temp.bitfield.fword = 0;
1836 temp.bitfield.qword = 0;
1837 temp.bitfield.tbyte = 0;
1838 temp.bitfield.xmmword = 0;
c0f3af97 1839 temp.bitfield.ymmword = 0;
43234a1e 1840 temp.bitfield.zmmword = 0;
0dfbf9d7 1841 if (operand_type_all_zero (&temp))
891edac4 1842 goto mismatch;
40fb9820 1843
891edac4
L		 1844 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1845 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1846 return 1;
1847
1848mismatch:
a65babc9 1849 i.error = operand_type_mismatch;
891edac4 1850 return 0;
40fb9820
L		 1851}
1852
7d5e4556 1853/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1854 unless the expected operand type register overlap is null.
1855 Note that Acc in a template matches every size of reg. */
1856
c6fb90c8 1857static INLINE int
40fb9820
L		 1858operand_type_register_match (i386_operand_type m0,
1859 i386_operand_type g0,
1860 i386_operand_type t0,
1861 i386_operand_type m1,
1862 i386_operand_type g1,
1863 i386_operand_type t1)
1864{
1865 if (!operand_type_check (g0, reg))
1866 return 1;
1867
1868 if (!operand_type_check (g1, reg))
1869 return 1;
1870
1871 if (g0.bitfield.reg8 == g1.bitfield.reg8
1872 && g0.bitfield.reg16 == g1.bitfield.reg16
1873 && g0.bitfield.reg32 == g1.bitfield.reg32
1874 && g0.bitfield.reg64 == g1.bitfield.reg64)
1875 return 1;
1876
1877 if (m0.bitfield.acc)
1878 {
1879 t0.bitfield.reg8 = 1;
1880 t0.bitfield.reg16 = 1;
1881 t0.bitfield.reg32 = 1;
1882 t0.bitfield.reg64 = 1;
1883 }
1884
1885 if (m1.bitfield.acc)
1886 {
1887 t1.bitfield.reg8 = 1;
1888 t1.bitfield.reg16 = 1;
1889 t1.bitfield.reg32 = 1;
1890 t1.bitfield.reg64 = 1;
1891 }
1892
891edac4
L		 1893 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1894 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1895 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1896 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1897 return 1;
1898
a65babc9 1899 i.error = register_type_mismatch;
891edac4
L		 1900
1901 return 0;
40fb9820
L		 1902}
1903
4c692bc7
JB		 1904static INLINE unsigned int
1905register_number (const reg_entry *r)
1906{
1907 unsigned int nr = r->reg_num;
1908
1909 if (r->reg_flags & RegRex)
1910 nr += 8;
1911
1912 return nr;
1913}
1914
252b5132 1915static INLINE unsigned int
40fb9820 1916mode_from_disp_size (i386_operand_type t)
252b5132 1917{
43234a1e 1918 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1919 return 1;
1920 else if (t.bitfield.disp16
1921 || t.bitfield.disp32
1922 || t.bitfield.disp32s)
1923 return 2;
1924 else
1925 return 0;
252b5132
RH		 1926}
1927
1928static INLINE int
e3bb37b5 1929fits_in_signed_byte (offsetT num)
252b5132
RH		 1930{
1931 return (num >= -128) && (num <= 127);
47926f60 1932}
252b5132
RH		 1933
1934static INLINE int
e3bb37b5 1935fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1936{
1937 return (num & 0xff) == num;
47926f60 1938}
252b5132
RH		 1939
1940static INLINE int
e3bb37b5 1941fits_in_unsigned_word (offsetT num)
252b5132
RH		 1942{
1943 return (num & 0xffff) == num;
47926f60 1944}
252b5132
RH		 1945
1946static INLINE int
e3bb37b5 1947fits_in_signed_word (offsetT num)
252b5132
RH		 1948{
1949 return (-32768 <= num) && (num <= 32767);
47926f60 1950}
2a962e6d 1951
3e73aa7c 1952static INLINE int
e3bb37b5 1953fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1954{
1955#ifndef BFD64
1956 return 1;
1957#else
1958 return (!(((offsetT) -1 << 31) & num)
1959 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1960#endif
1961} /* fits_in_signed_long() */
2a962e6d 1962
3e73aa7c 1963static INLINE int
e3bb37b5 1964fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1965{
1966#ifndef BFD64
1967 return 1;
1968#else
1969 return (num & (((offsetT) 2 << 31) - 1)) == num;
1970#endif
1971} /* fits_in_unsigned_long() */
252b5132 1972
43234a1e
L		 1973static INLINE int
1974fits_in_vec_disp8 (offsetT num)
1975{
1976 int shift = i.memshift;
1977 unsigned int mask;
1978
1979 if (shift == -1)
1980 abort ();
1981
1982 mask = (1 << shift) - 1;
1983
1984 /* Return 0 if NUM isn't properly aligned. */
1985 if ((num & mask))
1986 return 0;
1987
1988 /* Check if NUM will fit in 8bit after shift. */
1989 return fits_in_signed_byte (num >> shift);
1990}
1991
a683cc34
SP		 1992static INLINE int
1993fits_in_imm4 (offsetT num)
1994{
1995 return (num & 0xf) == num;
1996}
1997
40fb9820 1998static i386_operand_type
e3bb37b5 1999smallest_imm_type (offsetT num)
252b5132 2000{
40fb9820 2001 i386_operand_type t;
7ab9ffdd 2002
0dfbf9d7 2003 operand_type_set (&t, 0);
40fb9820
L		 2004 t.bitfield.imm64 = 1;
2005
2006 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2007 {
2008 /* This code is disabled on the 486 because all the Imm1 forms
2009 in the opcode table are slower on the i486. They're the
2010 versions with the implicitly specified single-position
2011 displacement, which has another syntax if you really want to
2012 use that form. */
40fb9820
L		 2013 t.bitfield.imm1 = 1;
2014 t.bitfield.imm8 = 1;
2015 t.bitfield.imm8s = 1;
2016 t.bitfield.imm16 = 1;
2017 t.bitfield.imm32 = 1;
2018 t.bitfield.imm32s = 1;
2019 }
2020 else if (fits_in_signed_byte (num))
2021 {
2022 t.bitfield.imm8 = 1;
2023 t.bitfield.imm8s = 1;
2024 t.bitfield.imm16 = 1;
2025 t.bitfield.imm32 = 1;
2026 t.bitfield.imm32s = 1;
2027 }
2028 else if (fits_in_unsigned_byte (num))
2029 {
2030 t.bitfield.imm8 = 1;
2031 t.bitfield.imm16 = 1;
2032 t.bitfield.imm32 = 1;
2033 t.bitfield.imm32s = 1;
2034 }
2035 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2036 {
2037 t.bitfield.imm16 = 1;
2038 t.bitfield.imm32 = 1;
2039 t.bitfield.imm32s = 1;
2040 }
2041 else if (fits_in_signed_long (num))
2042 {
2043 t.bitfield.imm32 = 1;
2044 t.bitfield.imm32s = 1;
2045 }
2046 else if (fits_in_unsigned_long (num))
2047 t.bitfield.imm32 = 1;
2048
2049 return t;
47926f60 2050}
252b5132 2051
847f7ad4 2052static offsetT
e3bb37b5 2053offset_in_range (offsetT val, int size)
847f7ad4 2054{
508866be 2055 addressT mask;
ba2adb93 2056
847f7ad4
AM		 2057 switch (size)
2058 {
508866be
L		 2059 case 1: mask = ((addressT) 1 << 8) - 1; break;
2060 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2061 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2062#ifdef BFD64
2063 case 8: mask = ((addressT) 2 << 63) - 1; break;
2064#endif
47926f60 2065 default: abort ();
847f7ad4
AM		 2066 }
2067
9de868bf
L		 2068#ifdef BFD64
2069 /* If BFD64, sign extend val for 32bit address mode. */
2070 if (flag_code != CODE_64BIT
2071 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2072 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2073 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2074#endif
ba2adb93 2075
47926f60 2076 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2077 {
2078 char buf1[40], buf2[40];
2079
2080 sprint_value (buf1, val);
2081 sprint_value (buf2, val & mask);
2082 as_warn (_("%s shortened to %s"), buf1, buf2);
2083 }
2084 return val & mask;
2085}
2086
c32fa91d
L		 2087enum PREFIX_GROUP
2088{
2089 PREFIX_EXIST = 0,
2090 PREFIX_LOCK,
2091 PREFIX_REP,
2092 PREFIX_OTHER
2093};
2094
2095/* Returns
2096 a. PREFIX_EXIST if attempting to add a prefix where one from the
2097 same class already exists.
2098 b. PREFIX_LOCK if lock prefix is added.
2099 c. PREFIX_REP if rep/repne prefix is added.
2100 d. PREFIX_OTHER if other prefix is added.
2101 */
2102
2103static enum PREFIX_GROUP
e3bb37b5 2104add_prefix (unsigned int prefix)
252b5132 2105{
c32fa91d 2106 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2107 unsigned int q;
252b5132 2108
29b0f896
AM		 2109 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2110 && flag_code == CODE_64BIT)
b1905489 2111 {
161a04f6
L		 2112 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2113 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2114 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2115 ret = PREFIX_EXIST;
b1905489
JB		 2116 q = REX_PREFIX;
2117 }
3e73aa7c 2118 else
b1905489
JB		 2119 {
2120 switch (prefix)
2121 {
2122 default:
2123 abort ();
2124
2125 case CS_PREFIX_OPCODE:
2126 case DS_PREFIX_OPCODE:
2127 case ES_PREFIX_OPCODE:
2128 case FS_PREFIX_OPCODE:
2129 case GS_PREFIX_OPCODE:
2130 case SS_PREFIX_OPCODE:
2131 q = SEG_PREFIX;
2132 break;
2133
2134 case REPNE_PREFIX_OPCODE:
2135 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2136 q = REP_PREFIX;
2137 ret = PREFIX_REP;
2138 break;
2139
b1905489 2140 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2141 q = LOCK_PREFIX;
2142 ret = PREFIX_LOCK;
b1905489
JB		 2143 break;
2144
2145 case FWAIT_OPCODE:
2146 q = WAIT_PREFIX;
2147 break;
2148
2149 case ADDR_PREFIX_OPCODE:
2150 q = ADDR_PREFIX;
2151 break;
2152
2153 case DATA_PREFIX_OPCODE:
2154 q = DATA_PREFIX;
2155 break;
2156 }
2157 if (i.prefix[q] != 0)
c32fa91d 2158 ret = PREFIX_EXIST;
b1905489 2159 }
252b5132 2160
b1905489 2161 if (ret)
252b5132 2162 {
b1905489
JB		 2163 if (!i.prefix[q])
2164 ++i.prefixes;
2165 i.prefix[q] |= prefix;
252b5132 2166 }
b1905489
JB		 2167 else
2168 as_bad (_("same type of prefix used twice"));
252b5132 2169
252b5132
RH		 2170 return ret;
2171}
2172
2173static void
78f12dd3 2174update_code_flag (int value, int check)
eecb386c 2175{
78f12dd3
L		 2176 PRINTF_LIKE ((*as_error));
2177
1e9cc1c2 2178 flag_code = (enum flag_code) value;
40fb9820
L		 2179 if (flag_code == CODE_64BIT)
2180 {
2181 cpu_arch_flags.bitfield.cpu64 = 1;
2182 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2183 }
2184 else
2185 {
2186 cpu_arch_flags.bitfield.cpu64 = 0;
2187 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2188 }
2189 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2190 {
78f12dd3
L		 2191 if (check)
2192 as_error = as_fatal;
2193 else
2194 as_error = as_bad;
2195 (*as_error) (_("64bit mode not supported on `%s'."),
2196 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2197 }
40fb9820 2198 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2199 {
78f12dd3
L		 2200 if (check)
2201 as_error = as_fatal;
2202 else
2203 as_error = as_bad;
2204 (*as_error) (_("32bit mode not supported on `%s'."),
2205 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2206 }
eecb386c
AM		 2207 stackop_size = '\0';
2208}
2209
78f12dd3
L		 2210static void
2211set_code_flag (int value)
2212{
2213 update_code_flag (value, 0);
2214}
2215
eecb386c 2216static void
e3bb37b5 2217set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2218{
1e9cc1c2 2219 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2220 if (flag_code != CODE_16BIT)
2221 abort ();
2222 cpu_arch_flags.bitfield.cpu64 = 0;
2223 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2224 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2225}
2226
2227static void
e3bb37b5 2228set_intel_syntax (int syntax_flag)
252b5132
RH		 2229{
2230 /* Find out if register prefixing is specified. */
2231 int ask_naked_reg = 0;
2232
2233 SKIP_WHITESPACE ();
29b0f896 2234 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2235 {
2236 char *string = input_line_pointer;
2237 int e = get_symbol_end ();
2238
47926f60 2239 if (strcmp (string, "prefix") == 0)
252b5132 2240 ask_naked_reg = 1;
47926f60 2241 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2242 ask_naked_reg = -1;
2243 else
d0b47220 2244 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2245 *input_line_pointer = e;
2246 }
2247 demand_empty_rest_of_line ();
c3332e24 2248
252b5132
RH		 2249 intel_syntax = syntax_flag;
2250
2251 if (ask_naked_reg == 0)
f86103b7
AM		 2252 allow_naked_reg = (intel_syntax
2253 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2254 else
2255 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2256
ee86248c 2257 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2258
e4a3b5a4 2259 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2260 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2261 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2262}
2263
1efbbeb4
L		 2264static void
2265set_intel_mnemonic (int mnemonic_flag)
2266{
e1d4d893 2267 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2268}
2269
db51cc60
L		 2270static void
2271set_allow_index_reg (int flag)
2272{
2273 allow_index_reg = flag;
2274}
2275
cb19c032 2276static void
7bab8ab5 2277set_check (int what)
cb19c032 2278{
7bab8ab5
JB		 2279 enum check_kind *kind;
2280 const char *str;
2281
2282 if (what)
2283 {
2284 kind = &operand_check;
2285 str = "operand";
2286 }
2287 else
2288 {
2289 kind = &sse_check;
2290 str = "sse";
2291 }
2292
cb19c032
L		 2293 SKIP_WHITESPACE ();
2294
2295 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2296 {
2297 char *string = input_line_pointer;
2298 int e = get_symbol_end ();
2299
2300 if (strcmp (string, "none") == 0)
7bab8ab5 2301 *kind = check_none;
cb19c032 2302 else if (strcmp (string, "warning") == 0)
7bab8ab5 2303 *kind = check_warning;
cb19c032 2304 else if (strcmp (string, "error") == 0)
7bab8ab5 2305 *kind = check_error;
cb19c032 2306 else
7bab8ab5 2307 as_bad (_("bad argument to %s_check directive."), str);
cb19c032
L		 2308 *input_line_pointer = e;
2309 }
2310 else
7bab8ab5 2311 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2312
2313 demand_empty_rest_of_line ();
2314}
2315
8a9036a4
L		 2316static void
2317check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2318 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2319{
2320#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2321 static const char *arch;
2322
2323 /* Intel LIOM is only supported on ELF. */
2324 if (!IS_ELF)
2325 return;
2326
2327 if (!arch)
2328 {
2329 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2330 use default_arch. */
2331 arch = cpu_arch_name;
2332 if (!arch)
2333 arch = default_arch;
2334 }
2335
3632d14b 2336 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2337 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2338 || new_flag.bitfield.cpul1om)
8a9036a4 2339 return;
76ba9986 2340
7a9068fe
L		 2341 /* If we are targeting Intel K1OM, we must enable it. */
2342 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2343 || new_flag.bitfield.cpuk1om)
2344 return;
2345
8a9036a4
L		 2346 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2347#endif
2348}
2349
e413e4e9 2350static void
e3bb37b5 2351set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2352{
47926f60 2353 SKIP_WHITESPACE ();
e413e4e9 2354
29b0f896 2355 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2356 {
2357 char *string = input_line_pointer;
2358 int e = get_symbol_end ();
91d6fa6a 2359 unsigned int j;
40fb9820 2360 i386_cpu_flags flags;
e413e4e9 2361
91d6fa6a 2362 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2363 {
91d6fa6a 2364 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2365 {
91d6fa6a 2366 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2367
5c6af06e
JB		 2368 if (*string != '.')
2369 {
91d6fa6a 2370 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2371 cpu_sub_arch_name = NULL;
91d6fa6a 2372 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2373 if (flag_code == CODE_64BIT)
2374 {
2375 cpu_arch_flags.bitfield.cpu64 = 1;
2376 cpu_arch_flags.bitfield.cpuno64 = 0;
2377 }
2378 else
2379 {
2380 cpu_arch_flags.bitfield.cpu64 = 0;
2381 cpu_arch_flags.bitfield.cpuno64 = 1;
2382 }
91d6fa6a
NC		 2383 cpu_arch_isa = cpu_arch[j].type;
2384 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2385 if (!cpu_arch_tune_set)
2386 {
2387 cpu_arch_tune = cpu_arch_isa;
2388 cpu_arch_tune_flags = cpu_arch_isa_flags;
2389 }
5c6af06e
JB		 2390 break;
2391 }
40fb9820 2392
22109423 2393 if (!cpu_arch[j].negated)
309d3373 2394 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2395 cpu_arch[j].flags);
309d3373
JB		 2396 else
2397 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2398 cpu_arch[j].flags);
0dfbf9d7 2399 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2400 {
6305a203
L		 2401 if (cpu_sub_arch_name)
2402 {
2403 char *name = cpu_sub_arch_name;
2404 cpu_sub_arch_name = concat (name,
91d6fa6a 2405 cpu_arch[j].name,
1bf57e9f 2406 (const char *) NULL);
6305a203
L		 2407 free (name);
2408 }
2409 else
91d6fa6a 2410 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2411 cpu_arch_flags = flags;
a586129e 2412 cpu_arch_isa_flags = flags;
5c6af06e
JB		 2413 }
2414 *input_line_pointer = e;
2415 demand_empty_rest_of_line ();
2416 return;
e413e4e9
AM		 2417 }
2418 }
91d6fa6a 2419 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2420 as_bad (_("no such architecture: `%s'"), string);
2421
2422 *input_line_pointer = e;
2423 }
2424 else
2425 as_bad (_("missing cpu architecture"));
2426
fddf5b5b
AM		 2427 no_cond_jump_promotion = 0;
2428 if (*input_line_pointer == ','
29b0f896 2429 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2430 {
2431 char *string = ++input_line_pointer;
2432 int e = get_symbol_end ();
2433
2434 if (strcmp (string, "nojumps") == 0)
2435 no_cond_jump_promotion = 1;
2436 else if (strcmp (string, "jumps") == 0)
2437 ;
2438 else
2439 as_bad (_("no such architecture modifier: `%s'"), string);
2440
2441 *input_line_pointer = e;
2442 }
2443
e413e4e9
AM		 2444 demand_empty_rest_of_line ();
2445}
2446
8a9036a4
L		 2447enum bfd_architecture
2448i386_arch (void)
2449{
3632d14b 2450 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2451 {
2452 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2453 || flag_code != CODE_64BIT)
2454 as_fatal (_("Intel L1OM is 64bit ELF only"));
2455 return bfd_arch_l1om;
2456 }
7a9068fe
L		 2457 else if (cpu_arch_isa == PROCESSOR_K1OM)
2458 {
2459 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2460 || flag_code != CODE_64BIT)
2461 as_fatal (_("Intel K1OM is 64bit ELF only"));
2462 return bfd_arch_k1om;
2463 }
8a9036a4
L		 2464 else
2465 return bfd_arch_i386;
2466}
2467
b9d79e03 2468unsigned long
7016a5d5 2469i386_mach (void)
b9d79e03 2470{
351f65ca 2471 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2472 {
3632d14b 2473 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2474 {
351f65ca
L		 2475 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2476 || default_arch[6] != '\0')
8a9036a4
L		 2477 as_fatal (_("Intel L1OM is 64bit ELF only"));
2478 return bfd_mach_l1om;
2479 }
7a9068fe
L		 2480 else if (cpu_arch_isa == PROCESSOR_K1OM)
2481 {
2482 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2483 || default_arch[6] != '\0')
2484 as_fatal (_("Intel K1OM is 64bit ELF only"));
2485 return bfd_mach_k1om;
2486 }
351f65ca 2487 else if (default_arch[6] == '\0')
8a9036a4 2488 return bfd_mach_x86_64;
351f65ca
L		 2489 else
2490 return bfd_mach_x64_32;
8a9036a4 2491 }
b9d79e03
JH		 2492 else if (!strcmp (default_arch, "i386"))
2493 return bfd_mach_i386_i386;
2494 else
2b5d6a91 2495 as_fatal (_("unknown architecture"));
b9d79e03 2496}
b9d79e03 2497\f
252b5132 2498void
7016a5d5 2499md_begin (void)
252b5132
RH		 2500{
2501 const char *hash_err;
2502
47926f60 2503 /* Initialize op_hash hash table. */
252b5132
RH		 2504 op_hash = hash_new ();
2505
2506 {
d3ce72d0 2507 const insn_template *optab;
29b0f896 2508 templates *core_optab;
252b5132 2509
47926f60
KH		 2510 /* Setup for loop. */
2511 optab = i386_optab;
252b5132
RH		 2512 core_optab = (templates *) xmalloc (sizeof (templates));
2513 core_optab->start = optab;
2514
2515 while (1)
2516 {
2517 ++optab;
2518 if (optab->name == NULL
2519 || strcmp (optab->name, (optab - 1)->name) != 0)
2520 {
2521 /* different name --> ship out current template list;
47926f60 2522 add to hash table; & begin anew. */
252b5132
RH		 2523 core_optab->end = optab;
2524 hash_err = hash_insert (op_hash,
2525 (optab - 1)->name,
5a49b8ac 2526 (void *) core_optab);
252b5132
RH		 2527 if (hash_err)
2528 {
b37df7c4 2529 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2530 (optab - 1)->name,
2531 hash_err);
2532 }
2533 if (optab->name == NULL)
2534 break;
2535 core_optab = (templates *) xmalloc (sizeof (templates));
2536 core_optab->start = optab;
2537 }
2538 }
2539 }
2540
47926f60 2541 /* Initialize reg_hash hash table. */
252b5132
RH		 2542 reg_hash = hash_new ();
2543 {
29b0f896 2544 const reg_entry *regtab;
c3fe08fa 2545 unsigned int regtab_size = i386_regtab_size;
252b5132 2546
c3fe08fa 2547 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2548 {
5a49b8ac 2549 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2550 if (hash_err)
b37df7c4 2551 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2552 regtab->reg_name,
2553 hash_err);
252b5132
RH		 2554 }
2555 }
2556
47926f60 2557 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2558 {
29b0f896
AM		 2559 int c;
2560 char *p;
252b5132
RH		 2561
2562 for (c = 0; c < 256; c++)
2563 {
3882b010 2564 if (ISDIGIT (c))
252b5132
RH		 2565 {
2566 digit_chars[c] = c;
2567 mnemonic_chars[c] = c;
2568 register_chars[c] = c;
2569 operand_chars[c] = c;
2570 }
3882b010 2571 else if (ISLOWER (c))
252b5132
RH		 2572 {
2573 mnemonic_chars[c] = c;
2574 register_chars[c] = c;
2575 operand_chars[c] = c;
2576 }
3882b010 2577 else if (ISUPPER (c))
252b5132 2578 {
3882b010 2579 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2580 register_chars[c] = mnemonic_chars[c];
2581 operand_chars[c] = c;
2582 }
43234a1e
L		 2583 else if (c == '{' || c == '}')
2584 operand_chars[c] = c;
252b5132 2585
3882b010 2586 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2587 identifier_chars[c] = c;
2588 else if (c >= 128)
2589 {
2590 identifier_chars[c] = c;
2591 operand_chars[c] = c;
2592 }
2593 }
2594
2595#ifdef LEX_AT
2596 identifier_chars['@'] = '@';
32137342
NC		 2597#endif
2598#ifdef LEX_QM
2599 identifier_chars['?'] = '?';
2600 operand_chars['?'] = '?';
252b5132 2601#endif
252b5132 2602 digit_chars['-'] = '-';
c0f3af97 2603 mnemonic_chars['_'] = '_';
791fe849 2604 mnemonic_chars['-'] = '-';
0003779b 2605 mnemonic_chars['.'] = '.';
252b5132
RH		 2606 identifier_chars['_'] = '_';
2607 identifier_chars['.'] = '.';
2608
2609 for (p = operand_special_chars; *p != '\0'; p++)
2610 operand_chars[(unsigned char) *p] = *p;
2611 }
2612
a4447b93
RH		 2613 if (flag_code == CODE_64BIT)
2614 {
ca19b261
KT		 2615#if defined (OBJ_COFF) && defined (TE_PE)
2616 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2617 ? 32 : 16);
2618#else
a4447b93 2619 x86_dwarf2_return_column = 16;
ca19b261 2620#endif
61ff971f 2621 x86_cie_data_alignment = -8;
a4447b93
RH		 2622 }
2623 else
2624 {
2625 x86_dwarf2_return_column = 8;
2626 x86_cie_data_alignment = -4;
2627 }
252b5132
RH		 2628}
2629
2630void
e3bb37b5 2631i386_print_statistics (FILE *file)
252b5132
RH		 2632{
2633 hash_print_statistics (file, "i386 opcode", op_hash);
2634 hash_print_statistics (file, "i386 register", reg_hash);
2635}
2636\f
252b5132
RH		 2637#ifdef DEBUG386
2638
ce8a8b2f 2639/* Debugging routines for md_assemble. */
d3ce72d0 2640static void pte (insn_template *);
40fb9820 2641static void pt (i386_operand_type);
e3bb37b5
L		 2642static void pe (expressionS *);
2643static void ps (symbolS *);
252b5132
RH		 2644
2645static void
e3bb37b5 2646pi (char *line, i386_insn *x)
252b5132 2647{
09137c09 2648 unsigned int j;
252b5132
RH		 2649
2650 fprintf (stdout, "%s: template ", line);
2651 pte (&x->tm);
09f131f2
JH		 2652 fprintf (stdout, " address: base %s index %s scale %x\n",
2653 x->base_reg ? x->base_reg->reg_name : "none",
2654 x->index_reg ? x->index_reg->reg_name : "none",
2655 x->log2_scale_factor);
2656 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2657 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2658 fprintf (stdout, " sib: base %x index %x scale %x\n",
2659 x->sib.base, x->sib.index, x->sib.scale);
2660 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2661 (x->rex & REX_W) != 0,
2662 (x->rex & REX_R) != 0,
2663 (x->rex & REX_X) != 0,
2664 (x->rex & REX_B) != 0);
09137c09 2665 for (j = 0; j < x->operands; j++)
252b5132 2666 {
09137c09
SP		 2667 fprintf (stdout, " #%d: ", j + 1);
2668 pt (x->types[j]);
252b5132 2669 fprintf (stdout, "\n");
09137c09
SP		 2670 if (x->types[j].bitfield.reg8
2671 || x->types[j].bitfield.reg16
2672 || x->types[j].bitfield.reg32
2673 || x->types[j].bitfield.reg64
2674 || x->types[j].bitfield.regmmx
2675 || x->types[j].bitfield.regxmm
2676 || x->types[j].bitfield.regymm
43234a1e 2677 || x->types[j].bitfield.regzmm
09137c09
SP		 2678 || x->types[j].bitfield.sreg2
2679 || x->types[j].bitfield.sreg3
2680 || x->types[j].bitfield.control
2681 || x->types[j].bitfield.debug
2682 || x->types[j].bitfield.test)
2683 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2684 if (operand_type_check (x->types[j], imm))
2685 pe (x->op[j].imms);
2686 if (operand_type_check (x->types[j], disp))
2687 pe (x->op[j].disps);
252b5132
RH		 2688 }
2689}
2690
2691static void
d3ce72d0 2692pte (insn_template *t)
252b5132 2693{
09137c09 2694 unsigned int j;
252b5132 2695 fprintf (stdout, " %d operands ", t->operands);
47926f60 2696 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2697 if (t->extension_opcode != None)
2698 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2699 if (t->opcode_modifier.d)
252b5132 2700 fprintf (stdout, "D");
40fb9820 2701 if (t->opcode_modifier.w)
252b5132
RH		 2702 fprintf (stdout, "W");
2703 fprintf (stdout, "\n");
09137c09 2704 for (j = 0; j < t->operands; j++)
252b5132 2705 {
09137c09
SP		 2706 fprintf (stdout, " #%d type ", j + 1);
2707 pt (t->operand_types[j]);
252b5132
RH		 2708 fprintf (stdout, "\n");
2709 }
2710}
2711
2712static void
e3bb37b5 2713pe (expressionS *e)
252b5132 2714{
24eab124 2715 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2716 fprintf (stdout, " add_number %ld (%lx)\n",
2717 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2718 if (e->X_add_symbol)
2719 {
2720 fprintf (stdout, " add_symbol ");
2721 ps (e->X_add_symbol);
2722 fprintf (stdout, "\n");
2723 }
2724 if (e->X_op_symbol)
2725 {
2726 fprintf (stdout, " op_symbol ");
2727 ps (e->X_op_symbol);
2728 fprintf (stdout, "\n");
2729 }
2730}
2731
2732static void
e3bb37b5 2733ps (symbolS *s)
252b5132
RH		 2734{
2735 fprintf (stdout, "%s type %s%s",
2736 S_GET_NAME (s),
2737 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2738 segment_name (S_GET_SEGMENT (s)));
2739}
2740
7b81dfbb 2741static struct type_name
252b5132 2742 {
40fb9820
L		 2743 i386_operand_type mask;
2744 const char *name;
252b5132 2745 }
7b81dfbb 2746const type_names[] =
252b5132 2747{
40fb9820
L		 2748 { OPERAND_TYPE_REG8, "r8" },
2749 { OPERAND_TYPE_REG16, "r16" },
2750 { OPERAND_TYPE_REG32, "r32" },
2751 { OPERAND_TYPE_REG64, "r64" },
2752 { OPERAND_TYPE_IMM8, "i8" },
2753 { OPERAND_TYPE_IMM8, "i8s" },
2754 { OPERAND_TYPE_IMM16, "i16" },
2755 { OPERAND_TYPE_IMM32, "i32" },
2756 { OPERAND_TYPE_IMM32S, "i32s" },
2757 { OPERAND_TYPE_IMM64, "i64" },
2758 { OPERAND_TYPE_IMM1, "i1" },
2759 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2760 { OPERAND_TYPE_DISP8, "d8" },
2761 { OPERAND_TYPE_DISP16, "d16" },
2762 { OPERAND_TYPE_DISP32, "d32" },
2763 { OPERAND_TYPE_DISP32S, "d32s" },
2764 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2765 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2766 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2767 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2768 { OPERAND_TYPE_CONTROL, "control reg" },
2769 { OPERAND_TYPE_TEST, "test reg" },
2770 { OPERAND_TYPE_DEBUG, "debug reg" },
2771 { OPERAND_TYPE_FLOATREG, "FReg" },
2772 { OPERAND_TYPE_FLOATACC, "FAcc" },
2773 { OPERAND_TYPE_SREG2, "SReg2" },
2774 { OPERAND_TYPE_SREG3, "SReg3" },
2775 { OPERAND_TYPE_ACC, "Acc" },
2776 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2777 { OPERAND_TYPE_REGMMX, "rMMX" },
2778 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2779 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2780 { OPERAND_TYPE_REGZMM, "rZMM" },
2781 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2782 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2783};
2784
2785static void
40fb9820 2786pt (i386_operand_type t)
252b5132 2787{
40fb9820 2788 unsigned int j;
c6fb90c8 2789 i386_operand_type a;
252b5132 2790
40fb9820 2791 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2792 {
2793 a = operand_type_and (t, type_names[j].mask);
0349dc08 2794 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2795 fprintf (stdout, "%s, ", type_names[j].name);
2796 }
252b5132
RH		 2797 fflush (stdout);
2798}
2799
2800#endif /* DEBUG386 */
2801\f
252b5132 2802static bfd_reloc_code_real_type
3956db08 2803reloc (unsigned int size,
64e74474
AM		 2804 int pcrel,
2805 int sign,
c3320543 2806 int bnd_prefix,
64e74474 2807 bfd_reloc_code_real_type other)
252b5132 2808{
47926f60 2809 if (other != NO_RELOC)
3956db08 2810 {
91d6fa6a 2811 reloc_howto_type *rel;
3956db08
JB		 2812
2813 if (size == 8)
2814 switch (other)
2815 {
64e74474
AM		 2816 case BFD_RELOC_X86_64_GOT32:
2817 return BFD_RELOC_X86_64_GOT64;
2818 break;
2819 case BFD_RELOC_X86_64_PLTOFF64:
2820 return BFD_RELOC_X86_64_PLTOFF64;
2821 break;
2822 case BFD_RELOC_X86_64_GOTPC32:
2823 other = BFD_RELOC_X86_64_GOTPC64;
2824 break;
2825 case BFD_RELOC_X86_64_GOTPCREL:
2826 other = BFD_RELOC_X86_64_GOTPCREL64;
2827 break;
2828 case BFD_RELOC_X86_64_TPOFF32:
2829 other = BFD_RELOC_X86_64_TPOFF64;
2830 break;
2831 case BFD_RELOC_X86_64_DTPOFF32:
2832 other = BFD_RELOC_X86_64_DTPOFF64;
2833 break;
2834 default:
2835 break;
3956db08 2836 }
e05278af 2837
8ce3d284 2838#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2839 if (other == BFD_RELOC_SIZE32)
2840 {
2841 if (size == 8)
2842 return BFD_RELOC_SIZE64;
2843 if (pcrel)
2844 as_bad (_("there are no pc-relative size relocations"));
2845 }
8ce3d284 2846#endif
8fd4256d 2847
e05278af 2848 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2849 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2850 sign = -1;
2851
91d6fa6a
NC		 2852 rel = bfd_reloc_type_lookup (stdoutput, other);
2853 if (!rel)
3956db08 2854 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2855 else if (size != bfd_get_reloc_size (rel))
3956db08 2856 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2857 bfd_get_reloc_size (rel),
3956db08 2858 size);
91d6fa6a 2859 else if (pcrel && !rel->pc_relative)
3956db08 2860 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2861 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2862 && !sign)
91d6fa6a 2863 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2864 && sign > 0))
3956db08
JB		 2865 as_bad (_("relocated field and relocation type differ in signedness"));
2866 else
2867 return other;
2868 return NO_RELOC;
2869 }
252b5132
RH		 2870
2871 if (pcrel)
2872 {
3e73aa7c 2873 if (!sign)
3956db08 2874 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2875 switch (size)
2876 {
2877 case 1: return BFD_RELOC_8_PCREL;
2878 case 2: return BFD_RELOC_16_PCREL;
c3320543
L		 2879 case 4: return (bnd_prefix && object_64bit
2880 ? BFD_RELOC_X86_64_PC32_BND
2881 : BFD_RELOC_32_PCREL);
d6ab8113 2882 case 8: return BFD_RELOC_64_PCREL;
252b5132 2883 }
3956db08 2884 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2885 }
2886 else
2887 {
3956db08 2888 if (sign > 0)
e5cb08ac 2889 switch (size)
3e73aa7c
JH		 2890 {
2891 case 4: return BFD_RELOC_X86_64_32S;
2892 }
2893 else
2894 switch (size)
2895 {
2896 case 1: return BFD_RELOC_8;
2897 case 2: return BFD_RELOC_16;
2898 case 4: return BFD_RELOC_32;
2899 case 8: return BFD_RELOC_64;
2900 }
3956db08
JB		 2901 as_bad (_("cannot do %s %u byte relocation"),
2902 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2903 }
2904
0cc9e1d3 2905 return NO_RELOC;
252b5132
RH		 2906}
2907
47926f60
KH		 2908/* Here we decide which fixups can be adjusted to make them relative to
2909 the beginning of the section instead of the symbol. Basically we need
2910 to make sure that the dynamic relocations are done correctly, so in
2911 some cases we force the original symbol to be used. */
2912
252b5132 2913int
e3bb37b5 2914tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2915{
6d249963 2916#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2917 if (!IS_ELF)
31312f95
AM		 2918 return 1;
2919
a161fe53
AM		 2920 /* Don't adjust pc-relative references to merge sections in 64-bit
2921 mode. */
2922 if (use_rela_relocations
2923 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2924 && fixP->fx_pcrel)
252b5132 2925 return 0;
31312f95 2926
8d01d9a9
AJ		 2927 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2928 and changed later by validate_fix. */
2929 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2930 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2931 return 0;
2932
8fd4256d
L		 2933 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2934 for size relocations. */
2935 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2936 || fixP->fx_r_type == BFD_RELOC_SIZE64
2937 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2938 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2939 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2940 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2941 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2942 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2943 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2944 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2945 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2946 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2947 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2948 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2949 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2950 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2951 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2952 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2953 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2954 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2955 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2956 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2957 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2958 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2959 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2960 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2961 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2962 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2963 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2964 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2965 return 0;
31312f95 2966#endif
252b5132
RH		 2967 return 1;
2968}
252b5132 2969
b4cac588 2970static int
e3bb37b5 2971intel_float_operand (const char *mnemonic)
252b5132 2972{
9306ca4a
JB		 2973 /* Note that the value returned is meaningful only for opcodes with (memory)
2974 operands, hence the code here is free to improperly handle opcodes that
2975 have no operands (for better performance and smaller code). */
2976
2977 if (mnemonic[0] != 'f')
2978 return 0; /* non-math */
2979
2980 switch (mnemonic[1])
2981 {
2982 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2983 the fs segment override prefix not currently handled because no
2984 call path can make opcodes without operands get here */
2985 case 'i':
2986 return 2 /* integer op */;
2987 case 'l':
2988 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2989 return 3; /* fldcw/fldenv */
2990 break;
2991 case 'n':
2992 if (mnemonic[2] != 'o' /* fnop */)
2993 return 3; /* non-waiting control op */
2994 break;
2995 case 'r':
2996 if (mnemonic[2] == 's')
2997 return 3; /* frstor/frstpm */
2998 break;
2999 case 's':
3000 if (mnemonic[2] == 'a')
3001 return 3; /* fsave */
3002 if (mnemonic[2] == 't')
3003 {
3004 switch (mnemonic[3])
3005 {
3006 case 'c': /* fstcw */
3007 case 'd': /* fstdw */
3008 case 'e': /* fstenv */
3009 case 's': /* fsts[gw] */
3010 return 3;
3011 }
3012 }
3013 break;
3014 case 'x':
3015 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3016 return 0; /* fxsave/fxrstor are not really math ops */
3017 break;
3018 }
252b5132 3019
9306ca4a 3020 return 1;
252b5132
RH		 3021}
3022
c0f3af97
L		 3023/* Build the VEX prefix. */
3024
3025static void
d3ce72d0 3026build_vex_prefix (const insn_template *t)
c0f3af97
L		 3027{
3028 unsigned int register_specifier;
3029 unsigned int implied_prefix;
3030 unsigned int vector_length;
3031
3032 /* Check register specifier. */
3033 if (i.vex.register_specifier)
43234a1e
L		 3034 {
3035 register_specifier =
3036 ~register_number (i.vex.register_specifier) & 0xf;
3037 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3038 }
c0f3af97
L		 3039 else
3040 register_specifier = 0xf;
3041
fa99fab2
L		 3042 /* Use 2-byte VEX prefix by swappping destination and source
3043 operand. */
3044 if (!i.swap_operand
3045 && i.operands == i.reg_operands
7f399153 3046 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3047 && i.tm.opcode_modifier.s
3048 && i.rex == REX_B)
3049 {
3050 unsigned int xchg = i.operands - 1;
3051 union i386_op temp_op;
3052 i386_operand_type temp_type;
3053
3054 temp_type = i.types[xchg];
3055 i.types[xchg] = i.types[0];
3056 i.types[0] = temp_type;
3057 temp_op = i.op[xchg];
3058 i.op[xchg] = i.op[0];
3059 i.op[0] = temp_op;
3060
9c2799c2 3061 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3062
3063 i.rex = REX_R;
3064 xchg = i.rm.regmem;
3065 i.rm.regmem = i.rm.reg;
3066 i.rm.reg = xchg;
3067
3068 /* Use the next insn. */
3069 i.tm = t[1];
3070 }
3071
539f890d
L		 3072 if (i.tm.opcode_modifier.vex == VEXScalar)
3073 vector_length = avxscalar;
3074 else
3075 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3076
3077 switch ((i.tm.base_opcode >> 8) & 0xff)
3078 {
3079 case 0:
3080 implied_prefix = 0;
3081 break;
3082 case DATA_PREFIX_OPCODE:
3083 implied_prefix = 1;
3084 break;
3085 case REPE_PREFIX_OPCODE:
3086 implied_prefix = 2;
3087 break;
3088 case REPNE_PREFIX_OPCODE:
3089 implied_prefix = 3;
3090 break;
3091 default:
3092 abort ();
3093 }
3094
3095 /* Use 2-byte VEX prefix if possible. */
7f399153 3096 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3097 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3098 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3099 {
3100 /* 2-byte VEX prefix. */
3101 unsigned int r;
3102
3103 i.vex.length = 2;
3104 i.vex.bytes[0] = 0xc5;
3105
3106 /* Check the REX.R bit. */
3107 r = (i.rex & REX_R) ? 0 : 1;
3108 i.vex.bytes[1] = (r << 7
3109 | register_specifier << 3
3110 | vector_length << 2
3111 | implied_prefix);
3112 }
3113 else
3114 {
3115 /* 3-byte VEX prefix. */
3116 unsigned int m, w;
3117
f88c9eb0 3118 i.vex.length = 3;
f88c9eb0 3119
7f399153 3120 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3121 {
7f399153
L		 3122 case VEX0F:
3123 m = 0x1;
80de6e00 3124 i.vex.bytes[0] = 0xc4;
7f399153
L		 3125 break;
3126 case VEX0F38:
3127 m = 0x2;
80de6e00 3128 i.vex.bytes[0] = 0xc4;
7f399153
L		 3129 break;
3130 case VEX0F3A:
3131 m = 0x3;
80de6e00 3132 i.vex.bytes[0] = 0xc4;
7f399153
L		 3133 break;
3134 case XOP08:
5dd85c99
SP		 3135 m = 0x8;
3136 i.vex.bytes[0] = 0x8f;
7f399153
L		 3137 break;
3138 case XOP09:
f88c9eb0
SP		 3139 m = 0x9;
3140 i.vex.bytes[0] = 0x8f;
7f399153
L		 3141 break;
3142 case XOP0A:
f88c9eb0
SP		 3143 m = 0xa;
3144 i.vex.bytes[0] = 0x8f;
7f399153
L		 3145 break;
3146 default:
3147 abort ();
f88c9eb0 3148 }
c0f3af97 3149
c0f3af97
L		 3150 /* The high 3 bits of the second VEX byte are 1's compliment
3151 of RXB bits from REX. */
3152 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3153
3154 /* Check the REX.W bit. */
3155 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 3156 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 3157 {
3158 if (w)
3159 abort ();
3160
1ef99a7b 3161 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 3162 w = 1;
3163 }
3164
3165 i.vex.bytes[2] = (w << 7
3166 | register_specifier << 3
3167 | vector_length << 2
3168 | implied_prefix);
3169 }
3170}
3171
43234a1e
L		 3172/* Build the EVEX prefix. */
3173
3174static void
3175build_evex_prefix (void)
3176{
3177 unsigned int register_specifier;
3178 unsigned int implied_prefix;
3179 unsigned int m, w;
3180 rex_byte vrex_used = 0;
3181
3182 /* Check register specifier. */
3183 if (i.vex.register_specifier)
3184 {
3185 gas_assert ((i.vrex & REX_X) == 0);
3186
3187 register_specifier = i.vex.register_specifier->reg_num;
3188 if ((i.vex.register_specifier->reg_flags & RegRex))
3189 register_specifier += 8;
3190 /* The upper 16 registers are encoded in the fourth byte of the
3191 EVEX prefix. */
3192 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3193 i.vex.bytes[3] = 0x8;
3194 register_specifier = ~register_specifier & 0xf;
3195 }
3196 else
3197 {
3198 register_specifier = 0xf;
3199
3200 /* Encode upper 16 vector index register in the fourth byte of
3201 the EVEX prefix. */
3202 if (!(i.vrex & REX_X))
3203 i.vex.bytes[3] = 0x8;
3204 else
3205 vrex_used |= REX_X;
3206 }
3207
3208 switch ((i.tm.base_opcode >> 8) & 0xff)
3209 {
3210 case 0:
3211 implied_prefix = 0;
3212 break;
3213 case DATA_PREFIX_OPCODE:
3214 implied_prefix = 1;
3215 break;
3216 case REPE_PREFIX_OPCODE:
3217 implied_prefix = 2;
3218 break;
3219 case REPNE_PREFIX_OPCODE:
3220 implied_prefix = 3;
3221 break;
3222 default:
3223 abort ();
3224 }
3225
3226 /* 4 byte EVEX prefix. */
3227 i.vex.length = 4;
3228 i.vex.bytes[0] = 0x62;
3229
3230 /* mmmm bits. */
3231 switch (i.tm.opcode_modifier.vexopcode)
3232 {
3233 case VEX0F:
3234 m = 1;
3235 break;
3236 case VEX0F38:
3237 m = 2;
3238 break;
3239 case VEX0F3A:
3240 m = 3;
3241 break;
3242 default:
3243 abort ();
3244 break;
3245 }
3246
3247 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3248 bits from REX. */
3249 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3250
3251 /* The fifth bit of the second EVEX byte is 1's compliment of the
3252 REX_R bit in VREX. */
3253 if (!(i.vrex & REX_R))
3254 i.vex.bytes[1] |= 0x10;
3255 else
3256 vrex_used |= REX_R;
3257
3258 if ((i.reg_operands + i.imm_operands) == i.operands)
3259 {
3260 /* When all operands are registers, the REX_X bit in REX is not
3261 used. We reuse it to encode the upper 16 registers, which is
3262 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3263 as 1's compliment. */
3264 if ((i.vrex & REX_B))
3265 {
3266 vrex_used |= REX_B;
3267 i.vex.bytes[1] &= ~0x40;
3268 }
3269 }
3270
3271 /* EVEX instructions shouldn't need the REX prefix. */
3272 i.vrex &= ~vrex_used;
3273 gas_assert (i.vrex == 0);
3274
3275 /* Check the REX.W bit. */
3276 w = (i.rex & REX_W) ? 1 : 0;
3277 if (i.tm.opcode_modifier.vexw)
3278 {
3279 if (i.tm.opcode_modifier.vexw == VEXW1)
3280 w = 1;
3281 }
3282 /* If w is not set it means we are dealing with WIG instruction. */
3283 else if (!w)
3284 {
3285 if (evexwig == evexw1)
3286 w = 1;
3287 }
3288
3289 /* Encode the U bit. */
3290 implied_prefix |= 0x4;
3291
3292 /* The third byte of the EVEX prefix. */
3293 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3294
3295 /* The fourth byte of the EVEX prefix. */
3296 /* The zeroing-masking bit. */
3297 if (i.mask && i.mask->zeroing)
3298 i.vex.bytes[3] |= 0x80;
3299
3300 /* Don't always set the broadcast bit if there is no RC. */
3301 if (!i.rounding)
3302 {
3303 /* Encode the vector length. */
3304 unsigned int vec_length;
3305
3306 switch (i.tm.opcode_modifier.evex)
3307 {
3308 case EVEXLIG: /* LL' is ignored */
3309 vec_length = evexlig << 5;
3310 break;
3311 case EVEX128:
3312 vec_length = 0 << 5;
3313 break;
3314 case EVEX256:
3315 vec_length = 1 << 5;
3316 break;
3317 case EVEX512:
3318 vec_length = 2 << 5;
3319 break;
3320 default:
3321 abort ();
3322 break;
3323 }
3324 i.vex.bytes[3] |= vec_length;
3325 /* Encode the broadcast bit. */
3326 if (i.broadcast)
3327 i.vex.bytes[3] |= 0x10;
3328 }
3329 else
3330 {
3331 if (i.rounding->type != saeonly)
3332 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3333 else
3334 i.vex.bytes[3] |= 0x10;
3335 }
3336
3337 if (i.mask && i.mask->mask)
3338 i.vex.bytes[3] |= i.mask->mask->reg_num;
3339}
3340
65da13b5
L		 3341static void
3342process_immext (void)
3343{
3344 expressionS *exp;
3345
4c692bc7
JB		 3346 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3347 && i.operands > 0)
65da13b5 3348 {
4c692bc7
JB		 3349 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3350 with an opcode suffix which is coded in the same place as an
3351 8-bit immediate field would be.
3352 Here we check those operands and remove them afterwards. */
65da13b5
L		 3353 unsigned int x;
3354
3355 for (x = 0; x < i.operands; x++)
4c692bc7 3356 if (register_number (i.op[x].regs) != x)
65da13b5 3357 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3358 register_prefix, i.op[x].regs->reg_name, x + 1,
3359 i.tm.name);
3360
3361 i.operands = 0;
65da13b5
L		 3362 }
3363
c0f3af97 3364 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3365 which is coded in the same place as an 8-bit immediate field
3366 would be. Here we fake an 8-bit immediate operand from the
3367 opcode suffix stored in tm.extension_opcode.
3368
c1e679ec 3369 AVX instructions also use this encoding, for some of
c0f3af97 3370 3 argument instructions. */
65da13b5 3371
43234a1e 3372 gas_assert (i.imm_operands <= 1
7ab9ffdd 3373 && (i.operands <= 2
43234a1e
L		 3374 || ((i.tm.opcode_modifier.vex
3375 || i.tm.opcode_modifier.evex)
7ab9ffdd 3376 && i.operands <= 4)));
65da13b5
L		 3377
3378 exp = &im_expressions[i.imm_operands++];
3379 i.op[i.operands].imms = exp;
3380 i.types[i.operands] = imm8;
3381 i.operands++;
3382 exp->X_op = O_constant;
3383 exp->X_add_number = i.tm.extension_opcode;
3384 i.tm.extension_opcode = None;
3385}
3386
42164a71
L		 3387
3388static int
3389check_hle (void)
3390{
3391 switch (i.tm.opcode_modifier.hleprefixok)
3392 {
3393 default:
3394 abort ();
82c2def5 3395 case HLEPrefixNone:
165de32a
L		 3396 as_bad (_("invalid instruction `%s' after `%s'"),
3397 i.tm.name, i.hle_prefix);
42164a71 3398 return 0;
82c2def5 3399 case HLEPrefixLock:
42164a71
L		 3400 if (i.prefix[LOCK_PREFIX])
3401 return 1;
165de32a 3402 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3403 return 0;
82c2def5 3404 case HLEPrefixAny:
42164a71 3405 return 1;
82c2def5 3406 case HLEPrefixRelease:
42164a71
L		 3407 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3408 {
3409 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3410 i.tm.name);
3411 return 0;
3412 }
3413 if (i.mem_operands == 0
3414 || !operand_type_check (i.types[i.operands - 1], anymem))
3415 {
3416 as_bad (_("memory destination needed for instruction `%s'"
3417 " after `xrelease'"), i.tm.name);
3418 return 0;
3419 }
3420 return 1;
3421 }
3422}
3423
252b5132
RH		 3424/* This is the guts of the machine-dependent assembler. LINE points to a
3425 machine dependent instruction. This function is supposed to emit
3426 the frags/bytes it assembles to. */
3427
3428void
65da13b5 3429md_assemble (char *line)
252b5132 3430{
40fb9820 3431 unsigned int j;
252b5132 3432 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3433 const insn_template *t;
252b5132 3434
47926f60 3435 /* Initialize globals. */
252b5132
RH		 3436 memset (&i, '\0', sizeof (i));
3437 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3438 i.reloc[j] = NO_RELOC;
252b5132
RH		 3439 memset (disp_expressions, '\0', sizeof (disp_expressions));
3440 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3441 save_stack_p = save_stack;
252b5132
RH		 3442
3443 /* First parse an instruction mnemonic & call i386_operand for the operands.
3444 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3445 start of a (possibly prefixed) mnemonic. */
252b5132 3446
29b0f896
AM		 3447 line = parse_insn (line, mnemonic);
3448 if (line == NULL)
3449 return;
252b5132 3450
29b0f896 3451 line = parse_operands (line, mnemonic);
ee86248c 3452 this_operand = -1;
29b0f896
AM		 3453 if (line == NULL)
3454 return;
252b5132 3455
29b0f896
AM		 3456 /* Now we've parsed the mnemonic into a set of templates, and have the
3457 operands at hand. */
3458
3459 /* All intel opcodes have reversed operands except for "bound" and
3460 "enter". We also don't reverse intersegment "jmp" and "call"
3461 instructions with 2 immediate operands so that the immediate segment
050dfa73 3462 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3463 if (intel_syntax
3464 && i.operands > 1
29b0f896 3465 && (strcmp (mnemonic, "bound") != 0)
30123838 3466 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3467 && !(operand_type_check (i.types[0], imm)
3468 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3469 swap_operands ();
3470
ec56d5c0
JB		 3471 /* The order of the immediates should be reversed
3472 for 2 immediates extrq and insertq instructions */
3473 if (i.imm_operands == 2
3474 && (strcmp (mnemonic, "extrq") == 0
3475 || strcmp (mnemonic, "insertq") == 0))
3476 swap_2_operands (0, 1);
3477
29b0f896
AM		 3478 if (i.imm_operands)
3479 optimize_imm ();
3480
b300c311
L		 3481 /* Don't optimize displacement for movabs since it only takes 64bit
3482 displacement. */
3483 if (i.disp_operands
a501d77e 3484 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3485 && (flag_code != CODE_64BIT
3486 || strcmp (mnemonic, "movabs") != 0))
3487 optimize_disp ();
29b0f896
AM		 3488
3489 /* Next, we find a template that matches the given insn,
3490 making sure the overlap of the given operands types is consistent
3491 with the template operand types. */
252b5132 3492
fa99fab2 3493 if (!(t = match_template ()))
29b0f896 3494 return;
252b5132 3495
7bab8ab5 3496 if (sse_check != check_none
81f8a913 3497 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3498 && (i.tm.cpu_flags.bitfield.cpusse
3499 || i.tm.cpu_flags.bitfield.cpusse2
3500 || i.tm.cpu_flags.bitfield.cpusse3
3501 || i.tm.cpu_flags.bitfield.cpussse3
3502 || i.tm.cpu_flags.bitfield.cpusse4_1
3503 || i.tm.cpu_flags.bitfield.cpusse4_2))
3504 {
7bab8ab5 3505 (sse_check == check_warning
daf50ae7
L		 3506 ? as_warn
3507 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3508 }
3509
321fd21e
L		 3510 /* Zap movzx and movsx suffix. The suffix has been set from
3511 "word ptr" or "byte ptr" on the source operand in Intel syntax
3512 or extracted from mnemonic in AT&T syntax. But we'll use
3513 the destination register to choose the suffix for encoding. */
3514 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3515 {
321fd21e
L		 3516 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3517 there is no suffix, the default will be byte extension. */
3518 if (i.reg_operands != 2
3519 && !i.suffix
7ab9ffdd 3520 && intel_syntax)
321fd21e
L		 3521 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3522
3523 i.suffix = 0;
cd61ebfe 3524 }
24eab124 3525
40fb9820 3526 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3527 if (!add_prefix (FWAIT_OPCODE))
3528 return;
252b5132 3529
d5de92cf
L		 3530 /* Check if REP prefix is OK. */
3531 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3532 {
3533 as_bad (_("invalid instruction `%s' after `%s'"),
3534 i.tm.name, i.rep_prefix);
3535 return;
3536 }
3537
c1ba0266
L		 3538 /* Check for lock without a lockable instruction. Destination operand
3539 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3540 if (i.prefix[LOCK_PREFIX]
3541 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3542 || i.mem_operands == 0
3543 || (i.tm.base_opcode != 0x86
3544 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3545 {
3546 as_bad (_("expecting lockable instruction after `lock'"));
3547 return;
3548 }
3549
42164a71 3550 /* Check if HLE prefix is OK. */
165de32a 3551 if (i.hle_prefix && !check_hle ())
42164a71
L		 3552 return;
3553
7e8b059b
L		 3554 /* Check BND prefix. */
3555 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3556 as_bad (_("expecting valid branch instruction after `bnd'"));
3557
3558 if (i.tm.cpu_flags.bitfield.cpumpx
3559 && flag_code == CODE_64BIT
3560 && i.prefix[ADDR_PREFIX])
3561 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3562
3563 /* Insert BND prefix. */
3564 if (add_bnd_prefix
3565 && i.tm.opcode_modifier.bndprefixok
3566 && !i.prefix[BND_PREFIX])
3567 add_prefix (BND_PREFIX_OPCODE);
3568
29b0f896 3569 /* Check string instruction segment overrides. */
40fb9820 3570 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3571 {
3572 if (!check_string ())
5dd0794d 3573 return;
fc0763e6 3574 i.disp_operands = 0;
29b0f896 3575 }
5dd0794d 3576
29b0f896
AM		 3577 if (!process_suffix ())
3578 return;
e413e4e9 3579
bc0844ae
L		 3580 /* Update operand types. */
3581 for (j = 0; j < i.operands; j++)
3582 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3583
29b0f896
AM		 3584 /* Make still unresolved immediate matches conform to size of immediate
3585 given in i.suffix. */
3586 if (!finalize_imm ())
3587 return;
252b5132 3588
40fb9820 3589 if (i.types[0].bitfield.imm1)
29b0f896 3590 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3591
9afe6eb8
L		 3592 /* We only need to check those implicit registers for instructions
3593 with 3 operands or less. */
3594 if (i.operands <= 3)
3595 for (j = 0; j < i.operands; j++)
3596 if (i.types[j].bitfield.inoutportreg
3597 || i.types[j].bitfield.shiftcount
3598 || i.types[j].bitfield.acc
3599 || i.types[j].bitfield.floatacc)
3600 i.reg_operands--;
40fb9820 3601
c0f3af97
L		 3602 /* ImmExt should be processed after SSE2AVX. */
3603 if (!i.tm.opcode_modifier.sse2avx
3604 && i.tm.opcode_modifier.immext)
65da13b5 3605 process_immext ();
252b5132 3606
29b0f896
AM		 3607 /* For insns with operands there are more diddles to do to the opcode. */
3608 if (i.operands)
3609 {
3610 if (!process_operands ())
3611 return;
3612 }
40fb9820 3613 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3614 {
3615 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3616 as_warn (_("translating to `%sp'"), i.tm.name);
3617 }
252b5132 3618
c0f3af97 3619 if (i.tm.opcode_modifier.vex)
fa99fab2 3620 build_vex_prefix (t);
c0f3af97 3621
43234a1e
L		 3622 if (i.tm.opcode_modifier.evex)
3623 build_evex_prefix ();
3624
5dd85c99
SP		 3625 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3626 instructions may define INT_OPCODE as well, so avoid this corner
3627 case for those instructions that use MODRM. */
3628 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3629 && !i.tm.opcode_modifier.modrm
3630 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3631 {
3632 i.tm.base_opcode = INT3_OPCODE;
3633 i.imm_operands = 0;
3634 }
252b5132 3635
40fb9820
L		 3636 if ((i.tm.opcode_modifier.jump
3637 || i.tm.opcode_modifier.jumpbyte
3638 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3639 && i.op[0].disps->X_op == O_constant)
3640 {
3641 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3642 the absolute address given by the constant. Since ix86 jumps and
3643 calls are pc relative, we need to generate a reloc. */
3644 i.op[0].disps->X_add_symbol = &abs_symbol;
3645 i.op[0].disps->X_op = O_symbol;
3646 }
252b5132 3647
40fb9820 3648 if (i.tm.opcode_modifier.rex64)
161a04f6 3649 i.rex |= REX_W;
252b5132 3650
29b0f896
AM		 3651 /* For 8 bit registers we need an empty rex prefix. Also if the
3652 instruction already has a prefix, we need to convert old
3653 registers to new ones. */
773f551c 3654
40fb9820 3655 if ((i.types[0].bitfield.reg8
29b0f896 3656 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3657 || (i.types[1].bitfield.reg8
29b0f896 3658 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3659 || ((i.types[0].bitfield.reg8
3660 || i.types[1].bitfield.reg8)
29b0f896
AM		 3661 && i.rex != 0))
3662 {
3663 int x;
726c5dcd 3664
29b0f896
AM		 3665 i.rex |= REX_OPCODE;
3666 for (x = 0; x < 2; x++)
3667 {
3668 /* Look for 8 bit operand that uses old registers. */
40fb9820 3669 if (i.types[x].bitfield.reg8
29b0f896 3670 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3671 {
29b0f896
AM		 3672 /* In case it is "hi" register, give up. */
3673 if (i.op[x].regs->reg_num > 3)
a540244d 3674 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3675 "instruction requiring REX prefix."),
a540244d 3676 register_prefix, i.op[x].regs->reg_name);
773f551c 3677
29b0f896
AM		 3678 /* Otherwise it is equivalent to the extended register.
3679 Since the encoding doesn't change this is merely
3680 cosmetic cleanup for debug output. */
3681
3682 i.op[x].regs = i.op[x].regs + 8;
773f551c 3683 }
29b0f896
AM		 3684 }
3685 }
773f551c 3686
7ab9ffdd 3687 if (i.rex != 0)
29b0f896
AM		 3688 add_prefix (REX_OPCODE | i.rex);
3689
3690 /* We are ready to output the insn. */
3691 output_insn ();
3692}
3693
3694static char *
e3bb37b5 3695parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3696{
3697 char *l = line;
3698 char *token_start = l;
3699 char *mnem_p;
5c6af06e 3700 int supported;
d3ce72d0 3701 const insn_template *t;
b6169b20 3702 char *dot_p = NULL;
29b0f896 3703
29b0f896
AM		 3704 while (1)
3705 {
3706 mnem_p = mnemonic;
3707 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3708 {
b6169b20
L		 3709 if (*mnem_p == '.')
3710 dot_p = mnem_p;
29b0f896
AM		 3711 mnem_p++;
3712 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3713 {
29b0f896
AM		 3714 as_bad (_("no such instruction: `%s'"), token_start);
3715 return NULL;
3716 }
3717 l++;
3718 }
3719 if (!is_space_char (*l)
3720 && *l != END_OF_INSN
e44823cf
JB		 3721 && (intel_syntax
3722 || (*l != PREFIX_SEPARATOR
3723 && *l != ',')))
29b0f896
AM		 3724 {
3725 as_bad (_("invalid character %s in mnemonic"),
3726 output_invalid (*l));
3727 return NULL;
3728 }
3729 if (token_start == l)
3730 {
e44823cf 3731 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3732 as_bad (_("expecting prefix; got nothing"));
3733 else
3734 as_bad (_("expecting mnemonic; got nothing"));
3735 return NULL;
3736 }
45288df1 3737
29b0f896 3738 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3739 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3740
29b0f896
AM		 3741 if (*l != END_OF_INSN
3742 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3743 && current_templates
40fb9820 3744 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3745 {
c6fb90c8 3746 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3747 {
3748 as_bad ((flag_code != CODE_64BIT
3749 ? _("`%s' is only supported in 64-bit mode")
3750 : _("`%s' is not supported in 64-bit mode")),
3751 current_templates->start->name);
3752 return NULL;
3753 }
29b0f896
AM		 3754 /* If we are in 16-bit mode, do not allow addr16 or data16.
3755 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3756 if ((current_templates->start->opcode_modifier.size16
3757 || current_templates->start->opcode_modifier.size32)
29b0f896 3758 && flag_code != CODE_64BIT
40fb9820 3759 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3760 ^ (flag_code == CODE_16BIT)))
3761 {
3762 as_bad (_("redundant %s prefix"),
3763 current_templates->start->name);
3764 return NULL;
45288df1 3765 }
29b0f896
AM		 3766 /* Add prefix, checking for repeated prefixes. */
3767 switch (add_prefix (current_templates->start->base_opcode))
3768 {
c32fa91d 3769 case PREFIX_EXIST:
29b0f896 3770 return NULL;
c32fa91d 3771 case PREFIX_REP:
42164a71 3772 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3773 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3774 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3775 i.bnd_prefix = current_templates->start->name;
42164a71 3776 else
d5de92cf 3777 i.rep_prefix = current_templates->start->name;
29b0f896 3778 break;
c32fa91d
L		 3779 default:
3780 break;
29b0f896
AM		 3781 }
3782 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3783 token_start = ++l;
3784 }
3785 else
3786 break;
3787 }
45288df1 3788
30a55f88 3789 if (!current_templates)
b6169b20 3790 {
f8a5c266
L		 3791 /* Check if we should swap operand or force 32bit displacement in
3792 encoding. */
30a55f88
L		 3793 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3794 i.swap_operand = 1;
8d63c93e 3795 else if (mnem_p - 3 == dot_p
a501d77e
L		 3796 && dot_p[1] == 'd'
3797 && dot_p[2] == '8')
3798 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3799 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3800 && dot_p[1] == 'd'
3801 && dot_p[2] == '3'
3802 && dot_p[3] == '2')
a501d77e 3803 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3804 else
3805 goto check_suffix;
3806 mnem_p = dot_p;
3807 *dot_p = '\0';
d3ce72d0 3808 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3809 }
3810
29b0f896
AM		 3811 if (!current_templates)
3812 {
b6169b20 3813check_suffix:
29b0f896
AM		 3814 /* See if we can get a match by trimming off a suffix. */
3815 switch (mnem_p[-1])
3816 {
3817 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3818 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3819 i.suffix = SHORT_MNEM_SUFFIX;
3820 else
29b0f896
AM		 3821 case BYTE_MNEM_SUFFIX:
3822 case QWORD_MNEM_SUFFIX:
3823 i.suffix = mnem_p[-1];
3824 mnem_p[-1] = '\0';
d3ce72d0
NC		 3825 current_templates = (const templates *) hash_find (op_hash,
3826 mnemonic);
29b0f896
AM		 3827 break;
3828 case SHORT_MNEM_SUFFIX:
3829 case LONG_MNEM_SUFFIX:
3830 if (!intel_syntax)
3831 {
3832 i.suffix = mnem_p[-1];
3833 mnem_p[-1] = '\0';
d3ce72d0
NC		 3834 current_templates = (const templates *) hash_find (op_hash,
3835 mnemonic);
29b0f896
AM		 3836 }
3837 break;
252b5132 3838
29b0f896
AM		 3839 /* Intel Syntax. */
3840 case 'd':
3841 if (intel_syntax)
3842 {
9306ca4a 3843 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3844 i.suffix = SHORT_MNEM_SUFFIX;
3845 else
3846 i.suffix = LONG_MNEM_SUFFIX;
3847 mnem_p[-1] = '\0';
d3ce72d0
NC		 3848 current_templates = (const templates *) hash_find (op_hash,
3849 mnemonic);
29b0f896
AM		 3850 }
3851 break;
3852 }
3853 if (!current_templates)
3854 {
3855 as_bad (_("no such instruction: `%s'"), token_start);
3856 return NULL;
3857 }
3858 }
252b5132 3859
40fb9820
L		 3860 if (current_templates->start->opcode_modifier.jump
3861 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3862 {
3863 /* Check for a branch hint. We allow ",pt" and ",pn" for
3864 predict taken and predict not taken respectively.
3865 I'm not sure that branch hints actually do anything on loop
3866 and jcxz insns (JumpByte) for current Pentium4 chips. They
3867 may work in the future and it doesn't hurt to accept them
3868 now. */
3869 if (l[0] == ',' && l[1] == 'p')
3870 {
3871 if (l[2] == 't')
3872 {
3873 if (!add_prefix (DS_PREFIX_OPCODE))
3874 return NULL;
3875 l += 3;
3876 }
3877 else if (l[2] == 'n')
3878 {
3879 if (!add_prefix (CS_PREFIX_OPCODE))
3880 return NULL;
3881 l += 3;
3882 }
3883 }
3884 }
3885 /* Any other comma loses. */
3886 if (*l == ',')
3887 {
3888 as_bad (_("invalid character %s in mnemonic"),
3889 output_invalid (*l));
3890 return NULL;
3891 }
252b5132 3892
29b0f896 3893 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3894 supported = 0;
3895 for (t = current_templates->start; t < current_templates->end; ++t)
3896 {
c0f3af97
L		 3897 supported |= cpu_flags_match (t);
3898 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3899 goto skip;
5c6af06e 3900 }
3629bb00 3901
c0f3af97 3902 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3903 {
3904 as_bad (flag_code == CODE_64BIT
3905 ? _("`%s' is not supported in 64-bit mode")
3906 : _("`%s' is only supported in 64-bit mode"),
3907 current_templates->start->name);
3908 return NULL;
3909 }
c0f3af97 3910 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3911 {
3629bb00 3912 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3913 current_templates->start->name,
41aacd83 3914 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3915 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3916 return NULL;
29b0f896 3917 }
3629bb00
L		 3918
3919skip:
3920 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3921 && (flag_code != CODE_16BIT))
29b0f896
AM		 3922 {
3923 as_warn (_("use .code16 to ensure correct addressing mode"));
3924 }
252b5132 3925
29b0f896
AM		 3926 return l;
3927}
252b5132 3928
29b0f896 3929static char *
e3bb37b5 3930parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3931{
3932 char *token_start;
3138f287 3933
29b0f896
AM		 3934 /* 1 if operand is pending after ','. */
3935 unsigned int expecting_operand = 0;
252b5132 3936
29b0f896
AM		 3937 /* Non-zero if operand parens not balanced. */
3938 unsigned int paren_not_balanced;
3939
3940 while (*l != END_OF_INSN)
3941 {
3942 /* Skip optional white space before operand. */
3943 if (is_space_char (*l))
3944 ++l;
3945 if (!is_operand_char (*l) && *l != END_OF_INSN)
3946 {
3947 as_bad (_("invalid character %s before operand %d"),
3948 output_invalid (*l),
3949 i.operands + 1);
3950 return NULL;
3951 }
3952 token_start = l; /* after white space */
3953 paren_not_balanced = 0;
3954 while (paren_not_balanced || *l != ',')
3955 {
3956 if (*l == END_OF_INSN)
3957 {
3958 if (paren_not_balanced)
3959 {
3960 if (!intel_syntax)
3961 as_bad (_("unbalanced parenthesis in operand %d."),
3962 i.operands + 1);
3963 else
3964 as_bad (_("unbalanced brackets in operand %d."),
3965 i.operands + 1);
3966 return NULL;
3967 }
3968 else
3969 break; /* we are done */
3970 }
3971 else if (!is_operand_char (*l) && !is_space_char (*l))
3972 {
3973 as_bad (_("invalid character %s in operand %d"),
3974 output_invalid (*l),
3975 i.operands + 1);
3976 return NULL;
3977 }
3978 if (!intel_syntax)
3979 {
3980 if (*l == '(')
3981 ++paren_not_balanced;
3982 if (*l == ')')
3983 --paren_not_balanced;
3984 }
3985 else
3986 {
3987 if (*l == '[')
3988 ++paren_not_balanced;
3989 if (*l == ']')
3990 --paren_not_balanced;
3991 }
3992 l++;
3993 }
3994 if (l != token_start)
3995 { /* Yes, we've read in another operand. */
3996 unsigned int operand_ok;
3997 this_operand = i.operands++;
7d5e4556 3998 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3999 if (i.operands > MAX_OPERANDS)
4000 {
4001 as_bad (_("spurious operands; (%d operands/instruction max)"),
4002 MAX_OPERANDS);
4003 return NULL;
4004 }
4005 /* Now parse operand adding info to 'i' as we go along. */
4006 END_STRING_AND_SAVE (l);
4007
4008 if (intel_syntax)
4009 operand_ok =
4010 i386_intel_operand (token_start,
4011 intel_float_operand (mnemonic));
4012 else
a7619375 4013 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4014
4015 RESTORE_END_STRING (l);
4016 if (!operand_ok)
4017 return NULL;
4018 }
4019 else
4020 {
4021 if (expecting_operand)
4022 {
4023 expecting_operand_after_comma:
4024 as_bad (_("expecting operand after ','; got nothing"));
4025 return NULL;
4026 }
4027 if (*l == ',')
4028 {
4029 as_bad (_("expecting operand before ','; got nothing"));
4030 return NULL;
4031 }
4032 }
7f3f1ea2 4033
29b0f896
AM		 4034 /* Now *l must be either ',' or END_OF_INSN. */
4035 if (*l == ',')
4036 {
4037 if (*++l == END_OF_INSN)
4038 {
4039 /* Just skip it, if it's \n complain. */
4040 goto expecting_operand_after_comma;
4041 }
4042 expecting_operand = 1;
4043 }
4044 }
4045 return l;
4046}
7f3f1ea2 4047
050dfa73 4048static void
4d456e3d 4049swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4050{
4051 union i386_op temp_op;
40fb9820 4052 i386_operand_type temp_type;
050dfa73 4053 enum bfd_reloc_code_real temp_reloc;
4eed87de 4054
050dfa73
MM		 4055 temp_type = i.types[xchg2];
4056 i.types[xchg2] = i.types[xchg1];
4057 i.types[xchg1] = temp_type;
4058 temp_op = i.op[xchg2];
4059 i.op[xchg2] = i.op[xchg1];
4060 i.op[xchg1] = temp_op;
4061 temp_reloc = i.reloc[xchg2];
4062 i.reloc[xchg2] = i.reloc[xchg1];
4063 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4064
4065 if (i.mask)
4066 {
4067 if (i.mask->operand == xchg1)
4068 i.mask->operand = xchg2;
4069 else if (i.mask->operand == xchg2)
4070 i.mask->operand = xchg1;
4071 }
4072 if (i.broadcast)
4073 {
4074 if (i.broadcast->operand == xchg1)
4075 i.broadcast->operand = xchg2;
4076 else if (i.broadcast->operand == xchg2)
4077 i.broadcast->operand = xchg1;
4078 }
4079 if (i.rounding)
4080 {
4081 if (i.rounding->operand == xchg1)
4082 i.rounding->operand = xchg2;
4083 else if (i.rounding->operand == xchg2)
4084 i.rounding->operand = xchg1;
4085 }
050dfa73
MM		 4086}
4087
29b0f896 4088static void
e3bb37b5 4089swap_operands (void)
29b0f896 4090{
b7c61d9a 4091 switch (i.operands)
050dfa73 4092 {
c0f3af97 4093 case 5:
b7c61d9a 4094 case 4:
4d456e3d 4095 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4096 case 3:
4097 case 2:
4d456e3d 4098 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4099 break;
4100 default:
4101 abort ();
29b0f896 4102 }
29b0f896
AM		 4103
4104 if (i.mem_operands == 2)
4105 {
4106 const seg_entry *temp_seg;
4107 temp_seg = i.seg[0];
4108 i.seg[0] = i.seg[1];
4109 i.seg[1] = temp_seg;
4110 }
4111}
252b5132 4112
29b0f896
AM		 4113/* Try to ensure constant immediates are represented in the smallest
4114 opcode possible. */
4115static void
e3bb37b5 4116optimize_imm (void)
29b0f896
AM		 4117{
4118 char guess_suffix = 0;
4119 int op;
252b5132 4120
29b0f896
AM		 4121 if (i.suffix)
4122 guess_suffix = i.suffix;
4123 else if (i.reg_operands)
4124 {
4125 /* Figure out a suffix from the last register operand specified.
4126 We can't do this properly yet, ie. excluding InOutPortReg,
4127 but the following works for instructions with immediates.
4128 In any case, we can't set i.suffix yet. */
4129 for (op = i.operands; --op >= 0;)
40fb9820 4130 if (i.types[op].bitfield.reg8)
7ab9ffdd 4131 {
40fb9820
L		 4132 guess_suffix = BYTE_MNEM_SUFFIX;
4133 break;
4134 }
4135 else if (i.types[op].bitfield.reg16)
252b5132 4136 {
40fb9820
L		 4137 guess_suffix = WORD_MNEM_SUFFIX;
4138 break;
4139 }
4140 else if (i.types[op].bitfield.reg32)
4141 {
4142 guess_suffix = LONG_MNEM_SUFFIX;
4143 break;
4144 }
4145 else if (i.types[op].bitfield.reg64)
4146 {
4147 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4148 break;
252b5132 4149 }
29b0f896
AM		 4150 }
4151 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4152 guess_suffix = WORD_MNEM_SUFFIX;
4153
4154 for (op = i.operands; --op >= 0;)
40fb9820 4155 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4156 {
4157 switch (i.op[op].imms->X_op)
252b5132 4158 {
29b0f896
AM		 4159 case O_constant:
4160 /* If a suffix is given, this operand may be shortened. */
4161 switch (guess_suffix)
252b5132 4162 {
29b0f896 4163 case LONG_MNEM_SUFFIX:
40fb9820
L		 4164 i.types[op].bitfield.imm32 = 1;
4165 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4166 break;
4167 case WORD_MNEM_SUFFIX:
40fb9820
L		 4168 i.types[op].bitfield.imm16 = 1;
4169 i.types[op].bitfield.imm32 = 1;
4170 i.types[op].bitfield.imm32s = 1;
4171 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4172 break;
4173 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4174 i.types[op].bitfield.imm8 = 1;
4175 i.types[op].bitfield.imm8s = 1;
4176 i.types[op].bitfield.imm16 = 1;
4177 i.types[op].bitfield.imm32 = 1;
4178 i.types[op].bitfield.imm32s = 1;
4179 i.types[op].bitfield.imm64 = 1;
29b0f896 4180 break;
252b5132 4181 }
252b5132 4182
29b0f896
AM		 4183 /* If this operand is at most 16 bits, convert it
4184 to a signed 16 bit number before trying to see
4185 whether it will fit in an even smaller size.
4186 This allows a 16-bit operand such as $0xffe0 to
4187 be recognised as within Imm8S range. */
40fb9820 4188 if ((i.types[op].bitfield.imm16)
29b0f896 4189 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4190 {
29b0f896
AM		 4191 i.op[op].imms->X_add_number =
4192 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4193 }
40fb9820 4194 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4195 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4196 == 0))
4197 {
4198 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4199 ^ ((offsetT) 1 << 31))
4200 - ((offsetT) 1 << 31));
4201 }
40fb9820 4202 i.types[op]
c6fb90c8
L		 4203 = operand_type_or (i.types[op],
4204 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4205
29b0f896
AM		 4206 /* We must avoid matching of Imm32 templates when 64bit
4207 only immediate is available. */
4208 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4209 i.types[op].bitfield.imm32 = 0;
29b0f896 4210 break;
252b5132 4211
29b0f896
AM		 4212 case O_absent:
4213 case O_register:
4214 abort ();
4215
4216 /* Symbols and expressions. */
4217 default:
9cd96992
JB		 4218 /* Convert symbolic operand to proper sizes for matching, but don't
4219 prevent matching a set of insns that only supports sizes other
4220 than those matching the insn suffix. */
4221 {
40fb9820 4222 i386_operand_type mask, allowed;
d3ce72d0 4223 const insn_template *t;
9cd96992 4224
0dfbf9d7
L		 4225 operand_type_set (&mask, 0);
4226 operand_type_set (&allowed, 0);
40fb9820 4227
4eed87de
AM		 4228 for (t = current_templates->start;
4229 t < current_templates->end;
4230 ++t)
c6fb90c8
L		 4231 allowed = operand_type_or (allowed,
4232 t->operand_types[op]);
9cd96992
JB		 4233 switch (guess_suffix)
4234 {
4235 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4236 mask.bitfield.imm64 = 1;
4237 mask.bitfield.imm32s = 1;
9cd96992
JB		 4238 break;
4239 case LONG_MNEM_SUFFIX:
40fb9820 4240 mask.bitfield.imm32 = 1;
9cd96992
JB		 4241 break;
4242 case WORD_MNEM_SUFFIX:
40fb9820 4243 mask.bitfield.imm16 = 1;
9cd96992
JB		 4244 break;
4245 case BYTE_MNEM_SUFFIX:
40fb9820 4246 mask.bitfield.imm8 = 1;
9cd96992
JB		 4247 break;
4248 default:
9cd96992
JB		 4249 break;
4250 }
c6fb90c8 4251 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4252 if (!operand_type_all_zero (&allowed))
c6fb90c8 4253 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4254 }
29b0f896 4255 break;
252b5132 4256 }
29b0f896
AM		 4257 }
4258}
47926f60 4259
29b0f896
AM		 4260/* Try to use the smallest displacement type too. */
4261static void
e3bb37b5 4262optimize_disp (void)
29b0f896
AM		 4263{
4264 int op;
3e73aa7c 4265
29b0f896 4266 for (op = i.operands; --op >= 0;)
40fb9820 4267 if (operand_type_check (i.types[op], disp))
252b5132 4268 {
b300c311 4269 if (i.op[op].disps->X_op == O_constant)
252b5132 4270 {
91d6fa6a 4271 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4272
40fb9820 4273 if (i.types[op].bitfield.disp16
91d6fa6a 4274 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4275 {
4276 /* If this operand is at most 16 bits, convert
4277 to a signed 16 bit number and don't use 64bit
4278 displacement. */
91d6fa6a 4279 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4280 i.types[op].bitfield.disp64 = 0;
b300c311 4281 }
40fb9820 4282 if (i.types[op].bitfield.disp32
91d6fa6a 4283 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4284 {
4285 /* If this operand is at most 32 bits, convert
4286 to a signed 32 bit number and don't use 64bit
4287 displacement. */
91d6fa6a
NC		 4288 op_disp &= (((offsetT) 2 << 31) - 1);
4289 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4290 i.types[op].bitfield.disp64 = 0;
b300c311 4291 }
91d6fa6a 4292 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4293 {
40fb9820
L		 4294 i.types[op].bitfield.disp8 = 0;
4295 i.types[op].bitfield.disp16 = 0;
4296 i.types[op].bitfield.disp32 = 0;
4297 i.types[op].bitfield.disp32s = 0;
4298 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4299 i.op[op].disps = 0;
4300 i.disp_operands--;
4301 }
4302 else if (flag_code == CODE_64BIT)
4303 {
91d6fa6a 4304 if (fits_in_signed_long (op_disp))
28a9d8f5 4305 {
40fb9820
L		 4306 i.types[op].bitfield.disp64 = 0;
4307 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4308 }
0e1147d9 4309 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4310 && fits_in_unsigned_long (op_disp))
40fb9820 4311 i.types[op].bitfield.disp32 = 1;
b300c311 4312 }
40fb9820
L		 4313 if ((i.types[op].bitfield.disp32
4314 || i.types[op].bitfield.disp32s
4315 || i.types[op].bitfield.disp16)
91d6fa6a 4316 && fits_in_signed_byte (op_disp))
40fb9820 4317 i.types[op].bitfield.disp8 = 1;
252b5132 4318 }
67a4f2b7
AO		 4319 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4320 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4321 {
4322 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4323 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4324 i.types[op].bitfield.disp8 = 0;
4325 i.types[op].bitfield.disp16 = 0;
4326 i.types[op].bitfield.disp32 = 0;
4327 i.types[op].bitfield.disp32s = 0;
4328 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4329 }
4330 else
b300c311 4331 /* We only support 64bit displacement on constants. */
40fb9820 4332 i.types[op].bitfield.disp64 = 0;
252b5132 4333 }
29b0f896
AM		 4334}
4335
6c30d220
L		 4336/* Check if operands are valid for the instruction. */
4337
4338static int
4339check_VecOperands (const insn_template *t)
4340{
43234a1e
L		 4341 unsigned int op;
4342
6c30d220
L		 4343 /* Without VSIB byte, we can't have a vector register for index. */
4344 if (!t->opcode_modifier.vecsib
4345 && i.index_reg
4346 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4347 || i.index_reg->reg_type.bitfield.regymm
4348 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4349 {
4350 i.error = unsupported_vector_index_register;
4351 return 1;
4352 }
4353
ad8ecc81
MZ		 4354 /* Check if default mask is allowed. */
4355 if (t->opcode_modifier.nodefmask
4356 && (!i.mask || i.mask->mask->reg_num == 0))
4357 {
4358 i.error = no_default_mask;
4359 return 1;
4360 }
4361
7bab8ab5
JB		 4362 /* For VSIB byte, we need a vector register for index, and all vector
4363 registers must be distinct. */
4364 if (t->opcode_modifier.vecsib)
4365 {
4366 if (!i.index_reg
6c30d220
L		 4367 || !((t->opcode_modifier.vecsib == VecSIB128
4368 && i.index_reg->reg_type.bitfield.regxmm)
4369 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4370 && i.index_reg->reg_type.bitfield.regymm)
4371 || (t->opcode_modifier.vecsib == VecSIB512
4372 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4373 {
4374 i.error = invalid_vsib_address;
4375 return 1;
4376 }
4377
43234a1e
L		 4378 gas_assert (i.reg_operands == 2 || i.mask);
4379 if (i.reg_operands == 2 && !i.mask)
4380 {
4381 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4382 || i.types[0].bitfield.regymm);
43234a1e 4383 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4384 || i.types[2].bitfield.regymm);
43234a1e
L		 4385 if (operand_check == check_none)
4386 return 0;
4387 if (register_number (i.op[0].regs)
4388 != register_number (i.index_reg)
4389 && register_number (i.op[2].regs)
4390 != register_number (i.index_reg)
4391 && register_number (i.op[0].regs)
4392 != register_number (i.op[2].regs))
4393 return 0;
4394 if (operand_check == check_error)
4395 {
4396 i.error = invalid_vector_register_set;
4397 return 1;
4398 }
4399 as_warn (_("mask, index, and destination registers should be distinct"));
4400 }
8444f82a
MZ		 4401 else if (i.reg_operands == 1 && i.mask)
4402 {
4403 if ((i.types[1].bitfield.regymm
4404 || i.types[1].bitfield.regzmm)
4405 && (register_number (i.op[1].regs)
4406 == register_number (i.index_reg)))
4407 {
4408 if (operand_check == check_error)
4409 {
4410 i.error = invalid_vector_register_set;
4411 return 1;
4412 }
4413 if (operand_check != check_none)
4414 as_warn (_("index and destination registers should be distinct"));
4415 }
4416 }
43234a1e 4417 }
7bab8ab5 4418
43234a1e
L		 4419 /* Check if broadcast is supported by the instruction and is applied
4420 to the memory operand. */
4421 if (i.broadcast)
4422 {
4423 int broadcasted_opnd_size;
4424
4425 /* Check if specified broadcast is supported in this instruction,
4426 and it's applied to memory operand of DWORD or QWORD type,
4427 depending on VecESize. */
4428 if (i.broadcast->type != t->opcode_modifier.broadcast
4429 || !i.types[i.broadcast->operand].bitfield.mem
4430 || (t->opcode_modifier.vecesize == 0
4431 && !i.types[i.broadcast->operand].bitfield.dword
4432 && !i.types[i.broadcast->operand].bitfield.unspecified)
4433 || (t->opcode_modifier.vecesize == 1
4434 && !i.types[i.broadcast->operand].bitfield.qword
4435 && !i.types[i.broadcast->operand].bitfield.unspecified))
4436 goto bad_broadcast;
4437
4438 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4439 if (i.broadcast->type == BROADCAST_1TO16)
4440 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4441 else if (i.broadcast->type == BROADCAST_1TO8)
4442 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
4443 else
4444 goto bad_broadcast;
4445
4446 if ((broadcasted_opnd_size == 256
4447 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4448 || (broadcasted_opnd_size == 512
4449 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4450 {
4451 bad_broadcast:
4452 i.error = unsupported_broadcast;
4453 return 1;
4454 }
4455 }
4456 /* If broadcast is supported in this instruction, we need to check if
4457 operand of one-element size isn't specified without broadcast. */
4458 else if (t->opcode_modifier.broadcast && i.mem_operands)
4459 {
4460 /* Find memory operand. */
4461 for (op = 0; op < i.operands; op++)
4462 if (operand_type_check (i.types[op], anymem))
4463 break;
4464 gas_assert (op < i.operands);
4465 /* Check size of the memory operand. */
4466 if ((t->opcode_modifier.vecesize == 0
4467 && i.types[op].bitfield.dword)
4468 || (t->opcode_modifier.vecesize == 1
4469 && i.types[op].bitfield.qword))
4470 {
4471 i.error = broadcast_needed;
4472 return 1;
4473 }
4474 }
4475
4476 /* Check if requested masking is supported. */
4477 if (i.mask
4478 && (!t->opcode_modifier.masking
4479 || (i.mask->zeroing
4480 && t->opcode_modifier.masking == MERGING_MASKING)))
4481 {
4482 i.error = unsupported_masking;
4483 return 1;
4484 }
4485
4486 /* Check if masking is applied to dest operand. */
4487 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4488 {
4489 i.error = mask_not_on_destination;
4490 return 1;
4491 }
4492
43234a1e
L		 4493 /* Check RC/SAE. */
4494 if (i.rounding)
4495 {
4496 if ((i.rounding->type != saeonly
4497 && !t->opcode_modifier.staticrounding)
4498 || (i.rounding->type == saeonly
4499 && (t->opcode_modifier.staticrounding
4500 || !t->opcode_modifier.sae)))
4501 {
4502 i.error = unsupported_rc_sae;
4503 return 1;
4504 }
4505 /* If the instruction has several immediate operands and one of
4506 them is rounding, the rounding operand should be the last
4507 immediate operand. */
4508 if (i.imm_operands > 1
4509 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4510 {
43234a1e 4511 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4512 return 1;
4513 }
6c30d220
L		 4514 }
4515
43234a1e
L		 4516 /* Check vector Disp8 operand. */
4517 if (t->opcode_modifier.disp8memshift)
4518 {
4519 if (i.broadcast)
4520 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4521 else
4522 i.memshift = t->opcode_modifier.disp8memshift;
4523
4524 for (op = 0; op < i.operands; op++)
4525 if (operand_type_check (i.types[op], disp)
4526 && i.op[op].disps->X_op == O_constant)
4527 {
4528 offsetT value = i.op[op].disps->X_add_number;
4529 int vec_disp8_ok = fits_in_vec_disp8 (value);
4530 if (t->operand_types [op].bitfield.vec_disp8)
4531 {
4532 if (vec_disp8_ok)
4533 i.types[op].bitfield.vec_disp8 = 1;
4534 else
4535 {
4536 /* Vector insn can only have Vec_Disp8/Disp32 in
4537 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4538 mode. */
4539 i.types[op].bitfield.disp8 = 0;
4540 if (flag_code != CODE_16BIT)
4541 i.types[op].bitfield.disp16 = 0;
4542 }
4543 }
4544 else if (flag_code != CODE_16BIT)
4545 {
4546 /* One form of this instruction supports vector Disp8.
4547 Try vector Disp8 if we need to use Disp32. */
4548 if (vec_disp8_ok && !fits_in_signed_byte (value))
4549 {
4550 i.error = try_vector_disp8;
4551 return 1;
4552 }
4553 }
4554 }
4555 }
4556 else
4557 i.memshift = -1;
4558
6c30d220
L		 4559 return 0;
4560}
4561
43f3e2ee 4562/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4563 operand types. */
4564
4565static int
4566VEX_check_operands (const insn_template *t)
4567{
43234a1e
L		 4568 /* VREX is only valid with EVEX prefix. */
4569 if (i.need_vrex && !t->opcode_modifier.evex)
4570 {
4571 i.error = invalid_register_operand;
4572 return 1;
4573 }
4574
a683cc34
SP		 4575 if (!t->opcode_modifier.vex)
4576 return 0;
4577
4578 /* Only check VEX_Imm4, which must be the first operand. */
4579 if (t->operand_types[0].bitfield.vec_imm4)
4580 {
4581 if (i.op[0].imms->X_op != O_constant
4582 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4583 {
a65babc9 4584 i.error = bad_imm4;
891edac4
L		 4585 return 1;
4586 }
a683cc34
SP		 4587
4588 /* Turn off Imm8 so that update_imm won't complain. */
4589 i.types[0] = vec_imm4;
4590 }
4591
4592 return 0;
4593}
4594
d3ce72d0 4595static const insn_template *
e3bb37b5 4596match_template (void)
29b0f896
AM		 4597{
4598 /* Points to template once we've found it. */
d3ce72d0 4599 const insn_template *t;
40fb9820 4600 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4601 i386_operand_type overlap4;
29b0f896 4602 unsigned int found_reverse_match;
40fb9820
L		 4603 i386_opcode_modifier suffix_check;
4604 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4605 int addr_prefix_disp;
a5c311ca 4606 unsigned int j;
3629bb00 4607 unsigned int found_cpu_match;
45664ddb 4608 unsigned int check_register;
5614d22c 4609 enum i386_error specific_error = 0;
29b0f896 4610
c0f3af97
L		 4611#if MAX_OPERANDS != 5
4612# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4613#endif
4614
29b0f896 4615 found_reverse_match = 0;
539e75ad 4616 addr_prefix_disp = -1;
40fb9820
L		 4617
4618 memset (&suffix_check, 0, sizeof (suffix_check));
4619 if (i.suffix == BYTE_MNEM_SUFFIX)
4620 suffix_check.no_bsuf = 1;
4621 else if (i.suffix == WORD_MNEM_SUFFIX)
4622 suffix_check.no_wsuf = 1;
4623 else if (i.suffix == SHORT_MNEM_SUFFIX)
4624 suffix_check.no_ssuf = 1;
4625 else if (i.suffix == LONG_MNEM_SUFFIX)
4626 suffix_check.no_lsuf = 1;
4627 else if (i.suffix == QWORD_MNEM_SUFFIX)
4628 suffix_check.no_qsuf = 1;
4629 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4630 suffix_check.no_ldsuf = 1;
29b0f896 4631
01559ecc
L		 4632 /* Must have right number of operands. */
4633 i.error = number_of_operands_mismatch;
4634
45aa61fe 4635 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4636 {
539e75ad
L		 4637 addr_prefix_disp = -1;
4638
29b0f896
AM		 4639 if (i.operands != t->operands)
4640 continue;
4641
50aecf8c 4642 /* Check processor support. */
a65babc9 4643 i.error = unsupported;
c0f3af97
L		 4644 found_cpu_match = (cpu_flags_match (t)
4645 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4646 if (!found_cpu_match)
4647 continue;
4648
e1d4d893 4649 /* Check old gcc support. */
a65babc9 4650 i.error = old_gcc_only;
e1d4d893
L		 4651 if (!old_gcc && t->opcode_modifier.oldgcc)
4652 continue;
4653
4654 /* Check AT&T mnemonic. */
a65babc9 4655 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4656 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4657 continue;
4658
891edac4 4659 /* Check AT&T/Intel syntax. */
a65babc9 4660 i.error = unsupported_syntax;
5c07affc
L		 4661 if ((intel_syntax && t->opcode_modifier.attsyntax)
4662 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4663 continue;
4664
20592a94 4665 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4666 i.error = invalid_instruction_suffix;
567e4e96
L		 4667 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4668 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4669 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4670 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4671 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4672 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4673 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4674 continue;
4675
5c07affc 4676 if (!operand_size_match (t))
7d5e4556 4677 continue;
539e75ad 4678
5c07affc
L		 4679 for (j = 0; j < MAX_OPERANDS; j++)
4680 operand_types[j] = t->operand_types[j];
4681
45aa61fe
AM		 4682 /* In general, don't allow 64-bit operands in 32-bit mode. */
4683 if (i.suffix == QWORD_MNEM_SUFFIX
4684 && flag_code != CODE_64BIT
4685 && (intel_syntax
40fb9820 4686 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4687 && !intel_float_operand (t->name))
4688 : intel_float_operand (t->name) != 2)
40fb9820 4689 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4690 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4691 && !operand_types[0].bitfield.regymm
4692 && !operand_types[0].bitfield.regzmm)
40fb9820 4693 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97 4694 && !!operand_types[t->operands > 1].bitfield.regxmm
43234a1e
L		 4695 && !!operand_types[t->operands > 1].bitfield.regymm
4696 && !!operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4697 && (t->base_opcode != 0x0fc7
4698 || t->extension_opcode != 1 /* cmpxchg8b */))
4699 continue;
4700
192dc9c6
JB		 4701 /* In general, don't allow 32-bit operands on pre-386. */
4702 else if (i.suffix == LONG_MNEM_SUFFIX
4703 && !cpu_arch_flags.bitfield.cpui386
4704 && (intel_syntax
4705 ? (!t->opcode_modifier.ignoresize
4706 && !intel_float_operand (t->name))
4707 : intel_float_operand (t->name) != 2)
4708 && ((!operand_types[0].bitfield.regmmx
4709 && !operand_types[0].bitfield.regxmm)
4710 || (!operand_types[t->operands > 1].bitfield.regmmx
4711 && !!operand_types[t->operands > 1].bitfield.regxmm)))
4712 continue;
4713
29b0f896 4714 /* Do not verify operands when there are none. */
50aecf8c 4715 else
29b0f896 4716 {
c6fb90c8 4717 if (!t->operands)
2dbab7d5
L		 4718 /* We've found a match; break out of loop. */
4719 break;
29b0f896 4720 }
252b5132 4721
539e75ad
L		 4722 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4723 into Disp32/Disp16/Disp32 operand. */
4724 if (i.prefix[ADDR_PREFIX] != 0)
4725 {
40fb9820 4726 /* There should be only one Disp operand. */
539e75ad
L		 4727 switch (flag_code)
4728 {
4729 case CODE_16BIT:
40fb9820
L		 4730 for (j = 0; j < MAX_OPERANDS; j++)
4731 {
4732 if (operand_types[j].bitfield.disp16)
4733 {
4734 addr_prefix_disp = j;
4735 operand_types[j].bitfield.disp32 = 1;
4736 operand_types[j].bitfield.disp16 = 0;
4737 break;
4738 }
4739 }
539e75ad
L		 4740 break;
4741 case CODE_32BIT:
40fb9820
L		 4742 for (j = 0; j < MAX_OPERANDS; j++)
4743 {
4744 if (operand_types[j].bitfield.disp32)
4745 {
4746 addr_prefix_disp = j;
4747 operand_types[j].bitfield.disp32 = 0;
4748 operand_types[j].bitfield.disp16 = 1;
4749 break;
4750 }
4751 }
539e75ad
L		 4752 break;
4753 case CODE_64BIT:
40fb9820
L		 4754 for (j = 0; j < MAX_OPERANDS; j++)
4755 {
4756 if (operand_types[j].bitfield.disp64)
4757 {
4758 addr_prefix_disp = j;
4759 operand_types[j].bitfield.disp64 = 0;
4760 operand_types[j].bitfield.disp32 = 1;
4761 break;
4762 }
4763 }
539e75ad
L		 4764 break;
4765 }
539e75ad
L		 4766 }
4767
56ffb741
L		 4768 /* We check register size if needed. */
4769 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4770 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4771 switch (t->operands)
4772 {
4773 case 1:
40fb9820 4774 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4775 continue;
4776 break;
4777 case 2:
8b38ad71
L		 4778 /* xchg %eax, %eax is a special case. It is an aliase for nop
4779 only in 32bit mode and we can use opcode 0x90. In 64bit
4780 mode, we can't use 0x90 for xchg %eax, %eax since it should
4781 zero-extend %eax to %rax. */
4782 if (flag_code == CODE_64BIT
4783 && t->base_opcode == 0x90
0dfbf9d7
L		 4784 && operand_type_equal (&i.types [0], &acc32)
4785 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4786 continue;
b6169b20
L		 4787 if (i.swap_operand)
4788 {
4789 /* If we swap operand in encoding, we either match
4790 the next one or reverse direction of operands. */
4791 if (t->opcode_modifier.s)
4792 continue;
4793 else if (t->opcode_modifier.d)
4794 goto check_reverse;
4795 }
4796
29b0f896 4797 case 3:
fa99fab2
L		 4798 /* If we swap operand in encoding, we match the next one. */
4799 if (i.swap_operand && t->opcode_modifier.s)
4800 continue;
f48ff2ae 4801 case 4:
c0f3af97 4802 case 5:
c6fb90c8 4803 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4804 if (!operand_type_match (overlap0, i.types[0])
4805 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4806 || (check_register
4807 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4808 operand_types[0],
4809 overlap1, i.types[1],
4810 operand_types[1])))
29b0f896
AM		 4811 {
4812 /* Check if other direction is valid ... */
40fb9820 4813 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4814 continue;
4815
b6169b20 4816check_reverse:
29b0f896 4817 /* Try reversing direction of operands. */
c6fb90c8
L		 4818 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4819 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4820 if (!operand_type_match (overlap0, i.types[0])
4821 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4822 || (check_register
4823 && !operand_type_register_match (overlap0,
4824 i.types[0],
4825 operand_types[1],
4826 overlap1,
4827 i.types[1],
4828 operand_types[0])))
29b0f896
AM		 4829 {
4830 /* Does not match either direction. */
4831 continue;
4832 }
4833 /* found_reverse_match holds which of D or FloatDR
4834 we've found. */
40fb9820 4835 if (t->opcode_modifier.d)
8a2ed489 4836 found_reverse_match = Opcode_D;
40fb9820 4837 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4838 found_reverse_match = Opcode_FloatD;
4839 else
4840 found_reverse_match = 0;
40fb9820 4841 if (t->opcode_modifier.floatr)
8a2ed489 4842 found_reverse_match |= Opcode_FloatR;
29b0f896 4843 }
f48ff2ae 4844 else
29b0f896 4845 {
f48ff2ae 4846 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4847 switch (t->operands)
4848 {
c0f3af97
L		 4849 case 5:
4850 overlap4 = operand_type_and (i.types[4],
4851 operand_types[4]);
d1cbb4db 4852 case 4:
c6fb90c8
L		 4853 overlap3 = operand_type_and (i.types[3],
4854 operand_types[3]);
d1cbb4db 4855 case 3:
c6fb90c8
L		 4856 overlap2 = operand_type_and (i.types[2],
4857 operand_types[2]);
d1cbb4db
L		 4858 break;
4859 }
29b0f896 4860
f48ff2ae
L		 4861 switch (t->operands)
4862 {
c0f3af97
L		 4863 case 5:
4864 if (!operand_type_match (overlap4, i.types[4])
4865 || !operand_type_register_match (overlap3,
4866 i.types[3],
4867 operand_types[3],
4868 overlap4,
4869 i.types[4],
4870 operand_types[4]))
4871 continue;
f48ff2ae 4872 case 4:
40fb9820 4873 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4874 || (check_register
4875 && !operand_type_register_match (overlap2,
4876 i.types[2],
4877 operand_types[2],
4878 overlap3,
4879 i.types[3],
4880 operand_types[3])))
f48ff2ae
L		 4881 continue;
4882 case 3:
4883 /* Here we make use of the fact that there are no
4884 reverse match 3 operand instructions, and all 3
4885 operand instructions only need to be checked for
4886 register consistency between operands 2 and 3. */
40fb9820 4887 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4888 || (check_register
4889 && !operand_type_register_match (overlap1,
4890 i.types[1],
4891 operand_types[1],
4892 overlap2,
4893 i.types[2],
4894 operand_types[2])))
f48ff2ae
L		 4895 continue;
4896 break;
4897 }
29b0f896 4898 }
f48ff2ae 4899 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4900 slip through to break. */
4901 }
3629bb00 4902 if (!found_cpu_match)
29b0f896
AM		 4903 {
4904 found_reverse_match = 0;
4905 continue;
4906 }
c0f3af97 4907
5614d22c
JB		 4908 /* Check if vector and VEX operands are valid. */
4909 if (check_VecOperands (t) || VEX_check_operands (t))
4910 {
4911 specific_error = i.error;
4912 continue;
4913 }
a683cc34 4914
29b0f896
AM		 4915 /* We've found a match; break out of loop. */
4916 break;
4917 }
4918
4919 if (t == current_templates->end)
4920 {
4921 /* We found no match. */
a65babc9 4922 const char *err_msg;
5614d22c 4923 switch (specific_error ? specific_error : i.error)
a65babc9
L		 4924 {
4925 default:
4926 abort ();
86e026a4 4927 case operand_size_mismatch:
a65babc9
L		 4928 err_msg = _("operand size mismatch");
4929 break;
4930 case operand_type_mismatch:
4931 err_msg = _("operand type mismatch");
4932 break;
4933 case register_type_mismatch:
4934 err_msg = _("register type mismatch");
4935 break;
4936 case number_of_operands_mismatch:
4937 err_msg = _("number of operands mismatch");
4938 break;
4939 case invalid_instruction_suffix:
4940 err_msg = _("invalid instruction suffix");
4941 break;
4942 case bad_imm4:
4a2608e3 4943 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 4944 break;
4945 case old_gcc_only:
4946 err_msg = _("only supported with old gcc");
4947 break;
4948 case unsupported_with_intel_mnemonic:
4949 err_msg = _("unsupported with Intel mnemonic");
4950 break;
4951 case unsupported_syntax:
4952 err_msg = _("unsupported syntax");
4953 break;
4954 case unsupported:
35262a23 4955 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 4956 current_templates->start->name);
4957 return NULL;
6c30d220
L		 4958 case invalid_vsib_address:
4959 err_msg = _("invalid VSIB address");
4960 break;
7bab8ab5
JB		 4961 case invalid_vector_register_set:
4962 err_msg = _("mask, index, and destination registers must be distinct");
4963 break;
6c30d220
L		 4964 case unsupported_vector_index_register:
4965 err_msg = _("unsupported vector index register");
4966 break;
43234a1e
L		 4967 case unsupported_broadcast:
4968 err_msg = _("unsupported broadcast");
4969 break;
4970 case broadcast_not_on_src_operand:
4971 err_msg = _("broadcast not on source memory operand");
4972 break;
4973 case broadcast_needed:
4974 err_msg = _("broadcast is needed for operand of such type");
4975 break;
4976 case unsupported_masking:
4977 err_msg = _("unsupported masking");
4978 break;
4979 case mask_not_on_destination:
4980 err_msg = _("mask not on destination operand");
4981 break;
4982 case no_default_mask:
4983 err_msg = _("default mask isn't allowed");
4984 break;
4985 case unsupported_rc_sae:
4986 err_msg = _("unsupported static rounding/sae");
4987 break;
4988 case rc_sae_operand_not_last_imm:
4989 if (intel_syntax)
4990 err_msg = _("RC/SAE operand must precede immediate operands");
4991 else
4992 err_msg = _("RC/SAE operand must follow immediate operands");
4993 break;
4994 case invalid_register_operand:
4995 err_msg = _("invalid register operand");
4996 break;
a65babc9
L		 4997 }
4998 as_bad (_("%s for `%s'"), err_msg,
891edac4 4999 current_templates->start->name);
fa99fab2 5000 return NULL;
29b0f896 5001 }
252b5132 5002
29b0f896
AM		 5003 if (!quiet_warnings)
5004 {
5005 if (!intel_syntax
40fb9820
L		 5006 && (i.types[0].bitfield.jumpabsolute
5007 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5008 {
5009 as_warn (_("indirect %s without `*'"), t->name);
5010 }
5011
40fb9820
L		 5012 if (t->opcode_modifier.isprefix
5013 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5014 {
5015 /* Warn them that a data or address size prefix doesn't
5016 affect assembly of the next line of code. */
5017 as_warn (_("stand-alone `%s' prefix"), t->name);
5018 }
5019 }
5020
5021 /* Copy the template we found. */
5022 i.tm = *t;
539e75ad
L		 5023
5024 if (addr_prefix_disp != -1)
5025 i.tm.operand_types[addr_prefix_disp]
5026 = operand_types[addr_prefix_disp];
5027
29b0f896
AM		 5028 if (found_reverse_match)
5029 {
5030 /* If we found a reverse match we must alter the opcode
5031 direction bit. found_reverse_match holds bits to change
5032 (different for int & float insns). */
5033
5034 i.tm.base_opcode ^= found_reverse_match;
5035
539e75ad
L		 5036 i.tm.operand_types[0] = operand_types[1];
5037 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5038 }
5039
fa99fab2 5040 return t;
29b0f896
AM		 5041}
5042
5043static int
e3bb37b5 5044check_string (void)
29b0f896 5045{
40fb9820
L		 5046 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5047 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5048 {
5049 if (i.seg[0] != NULL && i.seg[0] != &es)
5050 {
a87af027 5051 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5052 i.tm.name,
a87af027
JB		 5053 mem_op + 1,
5054 register_prefix);
29b0f896
AM		 5055 return 0;
5056 }
5057 /* There's only ever one segment override allowed per instruction.
5058 This instruction possibly has a legal segment override on the
5059 second operand, so copy the segment to where non-string
5060 instructions store it, allowing common code. */
5061 i.seg[0] = i.seg[1];
5062 }
40fb9820 5063 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5064 {
5065 if (i.seg[1] != NULL && i.seg[1] != &es)
5066 {
a87af027 5067 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5068 i.tm.name,
a87af027
JB		 5069 mem_op + 2,
5070 register_prefix);
29b0f896
AM		 5071 return 0;
5072 }
5073 }
5074 return 1;
5075}
5076
5077static int
543613e9 5078process_suffix (void)
29b0f896
AM		 5079{
5080 /* If matched instruction specifies an explicit instruction mnemonic
5081 suffix, use it. */
40fb9820
L		 5082 if (i.tm.opcode_modifier.size16)
5083 i.suffix = WORD_MNEM_SUFFIX;
5084 else if (i.tm.opcode_modifier.size32)
5085 i.suffix = LONG_MNEM_SUFFIX;
5086 else if (i.tm.opcode_modifier.size64)
5087 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5088 else if (i.reg_operands)
5089 {
5090 /* If there's no instruction mnemonic suffix we try to invent one
5091 based on register operands. */
5092 if (!i.suffix)
5093 {
5094 /* We take i.suffix from the last register operand specified,
5095 Destination register type is more significant than source
381d071f
L		 5096 register type. crc32 in SSE4.2 prefers source register
5097 type. */
5098 if (i.tm.base_opcode == 0xf20f38f1)
5099 {
40fb9820
L		 5100 if (i.types[0].bitfield.reg16)
5101 i.suffix = WORD_MNEM_SUFFIX;
5102 else if (i.types[0].bitfield.reg32)
5103 i.suffix = LONG_MNEM_SUFFIX;
5104 else if (i.types[0].bitfield.reg64)
5105 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5106 }
9344ff29 5107 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5108 {
40fb9820 5109 if (i.types[0].bitfield.reg8)
20592a94
L		 5110 i.suffix = BYTE_MNEM_SUFFIX;
5111 }
381d071f
L		 5112
5113 if (!i.suffix)
5114 {
5115 int op;
5116
20592a94
L		 5117 if (i.tm.base_opcode == 0xf20f38f1
5118 || i.tm.base_opcode == 0xf20f38f0)
5119 {
5120 /* We have to know the operand size for crc32. */
5121 as_bad (_("ambiguous memory operand size for `%s`"),
5122 i.tm.name);
5123 return 0;
5124 }
5125
381d071f 5126 for (op = i.operands; --op >= 0;)
40fb9820 5127 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5128 {
40fb9820
L		 5129 if (i.types[op].bitfield.reg8)
5130 {
5131 i.suffix = BYTE_MNEM_SUFFIX;
5132 break;
5133 }
5134 else if (i.types[op].bitfield.reg16)
5135 {
5136 i.suffix = WORD_MNEM_SUFFIX;
5137 break;
5138 }
5139 else if (i.types[op].bitfield.reg32)
5140 {
5141 i.suffix = LONG_MNEM_SUFFIX;
5142 break;
5143 }
5144 else if (i.types[op].bitfield.reg64)
5145 {
5146 i.suffix = QWORD_MNEM_SUFFIX;
5147 break;
5148 }
381d071f
L		 5149 }
5150 }
29b0f896
AM		 5151 }
5152 else if (i.suffix == BYTE_MNEM_SUFFIX)
5153 {
2eb952a4
L		 5154 if (intel_syntax
5155 && i.tm.opcode_modifier.ignoresize
5156 && i.tm.opcode_modifier.no_bsuf)
5157 i.suffix = 0;
5158 else if (!check_byte_reg ())
29b0f896
AM		 5159 return 0;
5160 }
5161 else if (i.suffix == LONG_MNEM_SUFFIX)
5162 {
2eb952a4
L		 5163 if (intel_syntax
5164 && i.tm.opcode_modifier.ignoresize
5165 && i.tm.opcode_modifier.no_lsuf)
5166 i.suffix = 0;
5167 else if (!check_long_reg ())
29b0f896
AM		 5168 return 0;
5169 }
5170 else if (i.suffix == QWORD_MNEM_SUFFIX)
5171 {
955e1e6a
L		 5172 if (intel_syntax
5173 && i.tm.opcode_modifier.ignoresize
5174 && i.tm.opcode_modifier.no_qsuf)
5175 i.suffix = 0;
5176 else if (!check_qword_reg ())
29b0f896
AM		 5177 return 0;
5178 }
5179 else if (i.suffix == WORD_MNEM_SUFFIX)
5180 {
2eb952a4
L		 5181 if (intel_syntax
5182 && i.tm.opcode_modifier.ignoresize
5183 && i.tm.opcode_modifier.no_wsuf)
5184 i.suffix = 0;
5185 else if (!check_word_reg ())
29b0f896
AM		 5186 return 0;
5187 }
c0f3af97 5188 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5189 || i.suffix == YMMWORD_MNEM_SUFFIX
5190 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5191 {
43234a1e 5192 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5193 should check if it is a valid suffix. */
5194 }
40fb9820 5195 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5196 /* Do nothing if the instruction is going to ignore the prefix. */
5197 ;
5198 else
5199 abort ();
5200 }
40fb9820 5201 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5202 && !i.suffix
5203 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5204 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5205 {
5206 i.suffix = stackop_size;
5207 }
9306ca4a
JB		 5208 else if (intel_syntax
5209 && !i.suffix
40fb9820
L		 5210 && (i.tm.operand_types[0].bitfield.jumpabsolute
5211 || i.tm.opcode_modifier.jumpbyte
5212 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5213 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5214 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5215 {
5216 switch (flag_code)
5217 {
5218 case CODE_64BIT:
40fb9820 5219 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5220 {
5221 i.suffix = QWORD_MNEM_SUFFIX;
5222 break;
5223 }
5224 case CODE_32BIT:
40fb9820 5225 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5226 i.suffix = LONG_MNEM_SUFFIX;
5227 break;
5228 case CODE_16BIT:
40fb9820 5229 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5230 i.suffix = WORD_MNEM_SUFFIX;
5231 break;
5232 }
5233 }
252b5132 5234
9306ca4a 5235 if (!i.suffix)
29b0f896 5236 {
9306ca4a
JB		 5237 if (!intel_syntax)
5238 {
40fb9820 5239 if (i.tm.opcode_modifier.w)
9306ca4a 5240 {
4eed87de
AM		 5241 as_bad (_("no instruction mnemonic suffix given and "
5242 "no register operands; can't size instruction"));
9306ca4a
JB		 5243 return 0;
5244 }
5245 }
5246 else
5247 {
40fb9820 5248 unsigned int suffixes;
7ab9ffdd 5249
40fb9820
L		 5250 suffixes = !i.tm.opcode_modifier.no_bsuf;
5251 if (!i.tm.opcode_modifier.no_wsuf)
5252 suffixes |= 1 << 1;
5253 if (!i.tm.opcode_modifier.no_lsuf)
5254 suffixes |= 1 << 2;
fc4adea1 5255 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5256 suffixes |= 1 << 3;
5257 if (!i.tm.opcode_modifier.no_ssuf)
5258 suffixes |= 1 << 4;
5259 if (!i.tm.opcode_modifier.no_qsuf)
5260 suffixes |= 1 << 5;
5261
5262 /* There are more than suffix matches. */
5263 if (i.tm.opcode_modifier.w
9306ca4a 5264 || ((suffixes & (suffixes - 1))
40fb9820
L		 5265 && !i.tm.opcode_modifier.defaultsize
5266 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5267 {
5268 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5269 return 0;
5270 }
5271 }
29b0f896 5272 }
252b5132 5273
9306ca4a
JB		 5274 /* Change the opcode based on the operand size given by i.suffix;
5275 We don't need to change things for byte insns. */
5276
582d5edd
L		 5277 if (i.suffix
5278 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5279 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5280 && i.suffix != YMMWORD_MNEM_SUFFIX
5281 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5282 {
5283 /* It's not a byte, select word/dword operation. */
40fb9820 5284 if (i.tm.opcode_modifier.w)
29b0f896 5285 {
40fb9820 5286 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5287 i.tm.base_opcode |= 8;
5288 else
5289 i.tm.base_opcode |= 1;
5290 }
0f3f3d8b 5291
29b0f896
AM		 5292 /* Now select between word & dword operations via the operand
5293 size prefix, except for instructions that will ignore this
5294 prefix anyway. */
ca61edf2 5295 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5296 {
ca61edf2
L		 5297 /* The address size override prefix changes the size of the
5298 first operand. */
40fb9820
L		 5299 if ((flag_code == CODE_32BIT
5300 && i.op->regs[0].reg_type.bitfield.reg16)
5301 || (flag_code != CODE_32BIT
5302 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5303 if (!add_prefix (ADDR_PREFIX_OPCODE))
5304 return 0;
5305 }
5306 else if (i.suffix != QWORD_MNEM_SUFFIX
5307 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5308 && !i.tm.opcode_modifier.ignoresize
5309 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5310 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5311 || (flag_code == CODE_64BIT
40fb9820 5312 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5313 {
5314 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5315
40fb9820 5316 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5317 prefix = ADDR_PREFIX_OPCODE;
252b5132 5318
29b0f896
AM		 5319 if (!add_prefix (prefix))
5320 return 0;
24eab124 5321 }
252b5132 5322
29b0f896
AM		 5323 /* Set mode64 for an operand. */
5324 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5325 && flag_code == CODE_64BIT
40fb9820 5326 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5327 {
5328 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5329 need rex64. cmpxchg8b is also a special case. */
5330 if (! (i.operands == 2
5331 && i.tm.base_opcode == 0x90
5332 && i.tm.extension_opcode == None
0dfbf9d7
L		 5333 && operand_type_equal (&i.types [0], &acc64)
5334 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5335 && ! (i.operands == 1
5336 && i.tm.base_opcode == 0xfc7
5337 && i.tm.extension_opcode == 1
40fb9820
L		 5338 && !operand_type_check (i.types [0], reg)
5339 && operand_type_check (i.types [0], anymem)))
f6bee062 5340 i.rex |= REX_W;
46e883c5 5341 }
3e73aa7c 5342
29b0f896
AM		 5343 /* Size floating point instruction. */
5344 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5345 if (i.tm.opcode_modifier.floatmf)
543613e9 5346 i.tm.base_opcode ^= 4;
29b0f896 5347 }
7ecd2f8b 5348
29b0f896
AM		 5349 return 1;
5350}
3e73aa7c 5351
29b0f896 5352static int
543613e9 5353check_byte_reg (void)
29b0f896
AM		 5354{
5355 int op;
543613e9 5356
29b0f896
AM		 5357 for (op = i.operands; --op >= 0;)
5358 {
5359 /* If this is an eight bit register, it's OK. If it's the 16 or
5360 32 bit version of an eight bit register, we will just use the
5361 low portion, and that's OK too. */
40fb9820 5362 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5363 continue;
5364
5a819eb9
JB		 5365 /* I/O port address operands are OK too. */
5366 if (i.tm.operand_types[op].bitfield.inoutportreg)
5367 continue;
5368
9344ff29
L		 5369 /* crc32 doesn't generate this warning. */
5370 if (i.tm.base_opcode == 0xf20f38f0)
5371 continue;
5372
40fb9820
L		 5373 if ((i.types[op].bitfield.reg16
5374 || i.types[op].bitfield.reg32
5375 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5376 && i.op[op].regs->reg_num < 4
5377 /* Prohibit these changes in 64bit mode, since the lowering
5378 would be more complicated. */
5379 && flag_code != CODE_64BIT)
29b0f896 5380 {
29b0f896 5381#if REGISTER_WARNINGS
5a819eb9 5382 if (!quiet_warnings)
a540244d
L		 5383 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5384 register_prefix,
40fb9820 5385 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5386 ? REGNAM_AL - REGNAM_AX
5387 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5388 register_prefix,
29b0f896
AM		 5389 i.op[op].regs->reg_name,
5390 i.suffix);
5391#endif
5392 continue;
5393 }
5394 /* Any other register is bad. */
40fb9820
L		 5395 if (i.types[op].bitfield.reg16
5396 || i.types[op].bitfield.reg32
5397 || i.types[op].bitfield.reg64
5398 || i.types[op].bitfield.regmmx
5399 || i.types[op].bitfield.regxmm
c0f3af97 5400 || i.types[op].bitfield.regymm
43234a1e 5401 || i.types[op].bitfield.regzmm
40fb9820
L		 5402 || i.types[op].bitfield.sreg2
5403 || i.types[op].bitfield.sreg3
5404 || i.types[op].bitfield.control
5405 || i.types[op].bitfield.debug
5406 || i.types[op].bitfield.test
5407 || i.types[op].bitfield.floatreg
5408 || i.types[op].bitfield.floatacc)
29b0f896 5409 {
a540244d
L		 5410 as_bad (_("`%s%s' not allowed with `%s%c'"),
5411 register_prefix,
29b0f896
AM		 5412 i.op[op].regs->reg_name,
5413 i.tm.name,
5414 i.suffix);
5415 return 0;
5416 }
5417 }
5418 return 1;
5419}
5420
5421static int
e3bb37b5 5422check_long_reg (void)
29b0f896
AM		 5423{
5424 int op;
5425
5426 for (op = i.operands; --op >= 0;)
5427 /* Reject eight bit registers, except where the template requires
5428 them. (eg. movzb) */
40fb9820
L		 5429 if (i.types[op].bitfield.reg8
5430 && (i.tm.operand_types[op].bitfield.reg16
5431 || i.tm.operand_types[op].bitfield.reg32
5432 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5433 {
a540244d
L		 5434 as_bad (_("`%s%s' not allowed with `%s%c'"),
5435 register_prefix,
29b0f896
AM		 5436 i.op[op].regs->reg_name,
5437 i.tm.name,
5438 i.suffix);
5439 return 0;
5440 }
e4630f71 5441 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5442 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5443 && i.types[op].bitfield.reg16
5444 && (i.tm.operand_types[op].bitfield.reg32
5445 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5446 {
5447 /* Prohibit these changes in the 64bit mode, since the
5448 lowering is more complicated. */
5449 if (flag_code == CODE_64BIT)
252b5132 5450 {
2b5d6a91 5451 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5452 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5453 i.suffix);
5454 return 0;
252b5132 5455 }
29b0f896 5456#if REGISTER_WARNINGS
cecf1424
JB		 5457 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5458 register_prefix,
5459 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5460 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5461#endif
252b5132 5462 }
e4630f71 5463 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5464 else if (i.types[op].bitfield.reg64
5465 && (i.tm.operand_types[op].bitfield.reg32
5466 || i.tm.operand_types[op].bitfield.acc))
252b5132 5467 {
34828aad 5468 if (intel_syntax
ca61edf2 5469 && i.tm.opcode_modifier.toqword
40fb9820 5470 && !i.types[0].bitfield.regxmm)
34828aad 5471 {
ca61edf2 5472 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5473 i.suffix = QWORD_MNEM_SUFFIX;
5474 }
5475 else
5476 {
2b5d6a91 5477 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5478 register_prefix, i.op[op].regs->reg_name,
5479 i.suffix);
5480 return 0;
5481 }
29b0f896
AM		 5482 }
5483 return 1;
5484}
252b5132 5485
29b0f896 5486static int
e3bb37b5 5487check_qword_reg (void)
29b0f896
AM		 5488{
5489 int op;
252b5132 5490
29b0f896
AM		 5491 for (op = i.operands; --op >= 0; )
5492 /* Reject eight bit registers, except where the template requires
5493 them. (eg. movzb) */
40fb9820
L		 5494 if (i.types[op].bitfield.reg8
5495 && (i.tm.operand_types[op].bitfield.reg16
5496 || i.tm.operand_types[op].bitfield.reg32
5497 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5498 {
a540244d
L		 5499 as_bad (_("`%s%s' not allowed with `%s%c'"),
5500 register_prefix,
29b0f896
AM		 5501 i.op[op].regs->reg_name,
5502 i.tm.name,
5503 i.suffix);
5504 return 0;
5505 }
e4630f71 5506 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5507 else if ((i.types[op].bitfield.reg16
5508 || i.types[op].bitfield.reg32)
5509 && (i.tm.operand_types[op].bitfield.reg32
5510 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5511 {
5512 /* Prohibit these changes in the 64bit mode, since the
5513 lowering is more complicated. */
34828aad 5514 if (intel_syntax
ca61edf2 5515 && i.tm.opcode_modifier.todword
40fb9820 5516 && !i.types[0].bitfield.regxmm)
34828aad 5517 {
ca61edf2 5518 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5519 i.suffix = LONG_MNEM_SUFFIX;
5520 }
5521 else
5522 {
2b5d6a91 5523 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5524 register_prefix, i.op[op].regs->reg_name,
5525 i.suffix);
5526 return 0;
5527 }
252b5132 5528 }
29b0f896
AM		 5529 return 1;
5530}
252b5132 5531
29b0f896 5532static int
e3bb37b5 5533check_word_reg (void)
29b0f896
AM		 5534{
5535 int op;
5536 for (op = i.operands; --op >= 0;)
5537 /* Reject eight bit registers, except where the template requires
5538 them. (eg. movzb) */
40fb9820
L		 5539 if (i.types[op].bitfield.reg8
5540 && (i.tm.operand_types[op].bitfield.reg16
5541 || i.tm.operand_types[op].bitfield.reg32
5542 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5543 {
a540244d
L		 5544 as_bad (_("`%s%s' not allowed with `%s%c'"),
5545 register_prefix,
29b0f896
AM		 5546 i.op[op].regs->reg_name,
5547 i.tm.name,
5548 i.suffix);
5549 return 0;
5550 }
e4630f71 5551 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5552 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5553 && (i.types[op].bitfield.reg32
5554 || i.types[op].bitfield.reg64)
40fb9820
L		 5555 && (i.tm.operand_types[op].bitfield.reg16
5556 || i.tm.operand_types[op].bitfield.acc))
252b5132 5557 {
29b0f896
AM		 5558 /* Prohibit these changes in the 64bit mode, since the
5559 lowering is more complicated. */
5560 if (flag_code == CODE_64BIT)
252b5132 5561 {
2b5d6a91 5562 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5563 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5564 i.suffix);
5565 return 0;
252b5132 5566 }
29b0f896 5567#if REGISTER_WARNINGS
cecf1424
JB		 5568 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5569 register_prefix,
5570 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5571 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5572#endif
5573 }
5574 return 1;
5575}
252b5132 5576
29b0f896 5577static int
40fb9820 5578update_imm (unsigned int j)
29b0f896 5579{
bc0844ae 5580 i386_operand_type overlap = i.types[j];
40fb9820
L		 5581 if ((overlap.bitfield.imm8
5582 || overlap.bitfield.imm8s
5583 || overlap.bitfield.imm16
5584 || overlap.bitfield.imm32
5585 || overlap.bitfield.imm32s
5586 || overlap.bitfield.imm64)
0dfbf9d7
L		 5587 && !operand_type_equal (&overlap, &imm8)
5588 && !operand_type_equal (&overlap, &imm8s)
5589 && !operand_type_equal (&overlap, &imm16)
5590 && !operand_type_equal (&overlap, &imm32)
5591 && !operand_type_equal (&overlap, &imm32s)
5592 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5593 {
5594 if (i.suffix)
5595 {
40fb9820
L		 5596 i386_operand_type temp;
5597
0dfbf9d7 5598 operand_type_set (&temp, 0);
7ab9ffdd 5599 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5600 {
5601 temp.bitfield.imm8 = overlap.bitfield.imm8;
5602 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5603 }
5604 else if (i.suffix == WORD_MNEM_SUFFIX)
5605 temp.bitfield.imm16 = overlap.bitfield.imm16;
5606 else if (i.suffix == QWORD_MNEM_SUFFIX)
5607 {
5608 temp.bitfield.imm64 = overlap.bitfield.imm64;
5609 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5610 }
5611 else
5612 temp.bitfield.imm32 = overlap.bitfield.imm32;
5613 overlap = temp;
29b0f896 5614 }
0dfbf9d7
L		 5615 else if (operand_type_equal (&overlap, &imm16_32_32s)
5616 || operand_type_equal (&overlap, &imm16_32)
5617 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5618 {
40fb9820 5619 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5620 overlap = imm16;
40fb9820 5621 else
65da13b5 5622 overlap = imm32s;
29b0f896 5623 }
0dfbf9d7
L		 5624 if (!operand_type_equal (&overlap, &imm8)
5625 && !operand_type_equal (&overlap, &imm8s)
5626 && !operand_type_equal (&overlap, &imm16)
5627 && !operand_type_equal (&overlap, &imm32)
5628 && !operand_type_equal (&overlap, &imm32s)
5629 && !operand_type_equal (&overlap, &imm64))
29b0f896 5630 {
4eed87de
AM		 5631 as_bad (_("no instruction mnemonic suffix given; "
5632 "can't determine immediate size"));
29b0f896
AM		 5633 return 0;
5634 }
5635 }
40fb9820 5636 i.types[j] = overlap;
29b0f896 5637
40fb9820
L		 5638 return 1;
5639}
5640
5641static int
5642finalize_imm (void)
5643{
bc0844ae 5644 unsigned int j, n;
29b0f896 5645
bc0844ae
L		 5646 /* Update the first 2 immediate operands. */
5647 n = i.operands > 2 ? 2 : i.operands;
5648 if (n)
5649 {
5650 for (j = 0; j < n; j++)
5651 if (update_imm (j) == 0)
5652 return 0;
40fb9820 5653
bc0844ae
L		 5654 /* The 3rd operand can't be immediate operand. */
5655 gas_assert (operand_type_check (i.types[2], imm) == 0);
5656 }
29b0f896
AM		 5657
5658 return 1;
5659}
5660
c0f3af97
L		 5661static int
5662bad_implicit_operand (int xmm)
5663{
91d6fa6a
NC		 5664 const char *ireg = xmm ? "xmm0" : "ymm0";
5665
c0f3af97
L		 5666 if (intel_syntax)
5667 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5668 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5669 else
5670 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5671 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5672 return 0;
5673}
5674
29b0f896 5675static int
e3bb37b5 5676process_operands (void)
29b0f896
AM		 5677{
5678 /* Default segment register this instruction will use for memory
5679 accesses. 0 means unknown. This is only for optimizing out
5680 unnecessary segment overrides. */
5681 const seg_entry *default_seg = 0;
5682
2426c15f 5683 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5684 {
91d6fa6a
NC		 5685 unsigned int dupl = i.operands;
5686 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5687 unsigned int j;
5688
c0f3af97 5689 /* The destination must be an xmm register. */
9c2799c2 5690 gas_assert (i.reg_operands
91d6fa6a 5691 && MAX_OPERANDS > dupl
7ab9ffdd 5692 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5693
5694 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5695 {
c0f3af97 5696 /* The first operand is implicit and must be xmm0. */
9c2799c2 5697 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5698 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5699 return bad_implicit_operand (1);
5700
8cd7925b 5701 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5702 {
5703 /* Keep xmm0 for instructions with VEX prefix and 3
5704 sources. */
5705 goto duplicate;
5706 }
e2ec9d29 5707 else
c0f3af97
L		 5708 {
5709 /* We remove the first xmm0 and keep the number of
5710 operands unchanged, which in fact duplicates the
5711 destination. */
5712 for (j = 1; j < i.operands; j++)
5713 {
5714 i.op[j - 1] = i.op[j];
5715 i.types[j - 1] = i.types[j];
5716 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5717 }
5718 }
5719 }
5720 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5721 {
91d6fa6a 5722 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5723 && (i.tm.opcode_modifier.vexsources
5724 == VEX3SOURCES));
c0f3af97
L		 5725
5726 /* Add the implicit xmm0 for instructions with VEX prefix
5727 and 3 sources. */
5728 for (j = i.operands; j > 0; j--)
5729 {
5730 i.op[j] = i.op[j - 1];
5731 i.types[j] = i.types[j - 1];
5732 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5733 }
5734 i.op[0].regs
5735 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5736 i.types[0] = regxmm;
c0f3af97
L		 5737 i.tm.operand_types[0] = regxmm;
5738
5739 i.operands += 2;
5740 i.reg_operands += 2;
5741 i.tm.operands += 2;
5742
91d6fa6a 5743 dupl++;
c0f3af97 5744 dest++;
91d6fa6a
NC		 5745 i.op[dupl] = i.op[dest];
5746 i.types[dupl] = i.types[dest];
5747 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5748 }
c0f3af97
L		 5749 else
5750 {
5751duplicate:
5752 i.operands++;
5753 i.reg_operands++;
5754 i.tm.operands++;
5755
91d6fa6a
NC		 5756 i.op[dupl] = i.op[dest];
5757 i.types[dupl] = i.types[dest];
5758 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5759 }
5760
5761 if (i.tm.opcode_modifier.immext)
5762 process_immext ();
5763 }
5764 else if (i.tm.opcode_modifier.firstxmm0)
5765 {
5766 unsigned int j;
5767
43234a1e 5768 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5769 gas_assert (i.reg_operands
7ab9ffdd 5770 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5771 || operand_type_equal (&i.types[0], &regymm)
5772 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5773 if (register_number (i.op[0].regs) != 0)
c0f3af97 5774 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5775
5776 for (j = 1; j < i.operands; j++)
5777 {
5778 i.op[j - 1] = i.op[j];
5779 i.types[j - 1] = i.types[j];
5780
5781 /* We need to adjust fields in i.tm since they are used by
5782 build_modrm_byte. */
5783 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5784 }
5785
e2ec9d29
L		 5786 i.operands--;
5787 i.reg_operands--;
e2ec9d29
L		 5788 i.tm.operands--;
5789 }
5790 else if (i.tm.opcode_modifier.regkludge)
5791 {
5792 /* The imul $imm, %reg instruction is converted into
5793 imul $imm, %reg, %reg, and the clr %reg instruction
5794 is converted into xor %reg, %reg. */
5795
5796 unsigned int first_reg_op;
5797
5798 if (operand_type_check (i.types[0], reg))
5799 first_reg_op = 0;
5800 else
5801 first_reg_op = 1;
5802 /* Pretend we saw the extra register operand. */
9c2799c2 5803 gas_assert (i.reg_operands == 1
7ab9ffdd 5804 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5805 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5806 i.types[first_reg_op + 1] = i.types[first_reg_op];
5807 i.operands++;
5808 i.reg_operands++;
29b0f896
AM		 5809 }
5810
40fb9820 5811 if (i.tm.opcode_modifier.shortform)
29b0f896 5812 {
40fb9820
L		 5813 if (i.types[0].bitfield.sreg2
5814 || i.types[0].bitfield.sreg3)
29b0f896 5815 {
4eed87de
AM		 5816 if (i.tm.base_opcode == POP_SEG_SHORT
5817 && i.op[0].regs->reg_num == 1)
29b0f896 5818 {
a87af027 5819 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5820 return 0;
29b0f896 5821 }
4eed87de
AM		 5822 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5823 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5824 i.rex |= REX_B;
4eed87de
AM		 5825 }
5826 else
5827 {
7ab9ffdd 5828 /* The register or float register operand is in operand
85f10a01 5829 0 or 1. */
40fb9820 5830 unsigned int op;
7ab9ffdd
L		 5831
5832 if (i.types[0].bitfield.floatreg
5833 || operand_type_check (i.types[0], reg))
5834 op = 0;
5835 else
5836 op = 1;
4eed87de
AM		 5837 /* Register goes in low 3 bits of opcode. */
5838 i.tm.base_opcode |= i.op[op].regs->reg_num;
5839 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5840 i.rex |= REX_B;
40fb9820 5841 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5842 {
4eed87de
AM		 5843 /* Warn about some common errors, but press on regardless.
5844 The first case can be generated by gcc (<= 2.8.1). */
5845 if (i.operands == 2)
5846 {
5847 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5848 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5849 register_prefix, i.op[!intel_syntax].regs->reg_name,
5850 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5851 }
5852 else
5853 {
5854 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5855 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5856 register_prefix, i.op[0].regs->reg_name);
4eed87de 5857 }
29b0f896
AM		 5858 }
5859 }
5860 }
40fb9820 5861 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5862 {
5863 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5864 must be put into the modrm byte). Now, we make the modrm and
5865 index base bytes based on all the info we've collected. */
29b0f896
AM		 5866
5867 default_seg = build_modrm_byte ();
5868 }
8a2ed489 5869 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5870 {
5871 default_seg = &ds;
5872 }
40fb9820 5873 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5874 {
5875 /* For the string instructions that allow a segment override
5876 on one of their operands, the default segment is ds. */
5877 default_seg = &ds;
5878 }
5879
75178d9d
L		 5880 if (i.tm.base_opcode == 0x8d /* lea */
5881 && i.seg[0]
5882 && !quiet_warnings)
30123838 5883 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5884
5885 /* If a segment was explicitly specified, and the specified segment
5886 is not the default, use an opcode prefix to select it. If we
5887 never figured out what the default segment is, then default_seg
5888 will be zero at this point, and the specified segment prefix will
5889 always be used. */
29b0f896
AM		 5890 if ((i.seg[0]) && (i.seg[0] != default_seg))
5891 {
5892 if (!add_prefix (i.seg[0]->seg_prefix))
5893 return 0;
5894 }
5895 return 1;
5896}
5897
5898static const seg_entry *
e3bb37b5 5899build_modrm_byte (void)
29b0f896
AM		 5900{
5901 const seg_entry *default_seg = 0;
c0f3af97 5902 unsigned int source, dest;
8cd7925b 5903 int vex_3_sources;
c0f3af97
L		 5904
5905 /* The first operand of instructions with VEX prefix and 3 sources
5906 must be VEX_Imm4. */
8cd7925b 5907 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5908 if (vex_3_sources)
5909 {
91d6fa6a 5910 unsigned int nds, reg_slot;
4c2c6516 5911 expressionS *exp;
c0f3af97 5912
922d8de8 5913 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5914 && i.tm.opcode_modifier.immext)
5915 {
5916 dest = i.operands - 2;
5917 gas_assert (dest == 3);
5918 }
922d8de8 5919 else
a683cc34 5920 dest = i.operands - 1;
c0f3af97 5921 nds = dest - 1;
922d8de8 5922
a683cc34
SP		 5923 /* There are 2 kinds of instructions:
5924 1. 5 operands: 4 register operands or 3 register operands
5925 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 5926 VexW0 or VexW1. The destination must be either XMM, YMM or
5927 ZMM register.
a683cc34
SP		 5928 2. 4 operands: 4 register operands or 3 register operands
5929 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5930 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5931 || (i.reg_operands == 3 && i.mem_operands == 1))
5932 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5933 && (i.tm.opcode_modifier.veximmext
5934 || (i.imm_operands == 1
5935 && i.types[0].bitfield.vec_imm4
5936 && (i.tm.opcode_modifier.vexw == VEXW0
5937 || i.tm.opcode_modifier.vexw == VEXW1)
5938 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 5939 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
5940 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 5941
5942 if (i.imm_operands == 0)
5943 {
5944 /* When there is no immediate operand, generate an 8bit
5945 immediate operand to encode the first operand. */
5946 exp = &im_expressions[i.imm_operands++];
5947 i.op[i.operands].imms = exp;
5948 i.types[i.operands] = imm8;
5949 i.operands++;
5950 /* If VexW1 is set, the first operand is the source and
5951 the second operand is encoded in the immediate operand. */
5952 if (i.tm.opcode_modifier.vexw == VEXW1)
5953 {
5954 source = 0;
5955 reg_slot = 1;
5956 }
5957 else
5958 {
5959 source = 1;
5960 reg_slot = 0;
5961 }
5962
5963 /* FMA swaps REG and NDS. */
5964 if (i.tm.cpu_flags.bitfield.cpufma)
5965 {
5966 unsigned int tmp;
5967 tmp = reg_slot;
5968 reg_slot = nds;
5969 nds = tmp;
5970 }
5971
24981e7b
L		 5972 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5973 &regxmm)
a683cc34 5974 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 5975 &regymm)
5976 || operand_type_equal (&i.tm.operand_types[reg_slot],
5977 &regzmm));
a683cc34 5978 exp->X_op = O_constant;
4c692bc7 5979 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 5980 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
5981 }
922d8de8 5982 else
a683cc34
SP		 5983 {
5984 unsigned int imm_slot;
5985
5986 if (i.tm.opcode_modifier.vexw == VEXW0)
5987 {
5988 /* If VexW0 is set, the third operand is the source and
5989 the second operand is encoded in the immediate
5990 operand. */
5991 source = 2;
5992 reg_slot = 1;
5993 }
5994 else
5995 {
5996 /* VexW1 is set, the second operand is the source and
5997 the third operand is encoded in the immediate
5998 operand. */
5999 source = 1;
6000 reg_slot = 2;
6001 }
6002
6003 if (i.tm.opcode_modifier.immext)
6004 {
6005 /* When ImmExt is set, the immdiate byte is the last
6006 operand. */
6007 imm_slot = i.operands - 1;
6008 source--;
6009 reg_slot--;
6010 }
6011 else
6012 {
6013 imm_slot = 0;
6014
6015 /* Turn on Imm8 so that output_imm will generate it. */
6016 i.types[imm_slot].bitfield.imm8 = 1;
6017 }
6018
24981e7b
L		 6019 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6020 &regxmm)
6021 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6022 &regymm)
6023 || operand_type_equal (&i.tm.operand_types[reg_slot],
6024 &regzmm));
a683cc34 6025 i.op[imm_slot].imms->X_add_number
4c692bc7 6026 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6027 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6028 }
6029
6030 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6031 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6032 &regymm)
6033 || operand_type_equal (&i.tm.operand_types[nds],
6034 &regzmm));
dae39acc 6035 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6036 }
6037 else
6038 source = dest = 0;
29b0f896
AM		 6039
6040 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6041 implicit registers do not count. If there are 3 register
6042 operands, it must be a instruction with VexNDS. For a
6043 instruction with VexNDD, the destination register is encoded
6044 in VEX prefix. If there are 4 register operands, it must be
6045 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6046 if (i.mem_operands == 0
6047 && ((i.reg_operands == 2
2426c15f 6048 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6049 || (i.reg_operands == 3
2426c15f 6050 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6051 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6052 {
cab737b9
L		 6053 switch (i.operands)
6054 {
6055 case 2:
6056 source = 0;
6057 break;
6058 case 3:
c81128dc
L		 6059 /* When there are 3 operands, one of them may be immediate,
6060 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6061 the first operand must be shift count register (cl) or it
6062 is an instruction with VexNDS. */
9c2799c2 6063 gas_assert (i.imm_operands == 1
7ab9ffdd 6064 || (i.imm_operands == 0
2426c15f 6065 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6066 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6067 if (operand_type_check (i.types[0], imm)
6068 || i.types[0].bitfield.shiftcount)
6069 source = 1;
6070 else
6071 source = 0;
cab737b9
L		 6072 break;
6073 case 4:
368d64cc
L		 6074 /* When there are 4 operands, the first two must be 8bit
6075 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6076 one.
6077
6078 For instructions with VexNDS, if the first operand
6079 an imm8, the source operand is the 2nd one. If the last
6080 operand is imm8, the source operand is the first one. */
9c2799c2 6081 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6082 && i.types[0].bitfield.imm8
6083 && i.types[1].bitfield.imm8)
2426c15f 6084 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6085 && i.imm_operands == 1
6086 && (i.types[0].bitfield.imm8
43234a1e
L		 6087 || i.types[i.operands - 1].bitfield.imm8
6088 || i.rounding)));
9f2670f2
L		 6089 if (i.imm_operands == 2)
6090 source = 2;
6091 else
c0f3af97
L		 6092 {
6093 if (i.types[0].bitfield.imm8)
6094 source = 1;
6095 else
6096 source = 0;
6097 }
c0f3af97
L		 6098 break;
6099 case 5:
43234a1e
L		 6100 if (i.tm.opcode_modifier.evex)
6101 {
6102 /* For EVEX instructions, when there are 5 operands, the
6103 first one must be immediate operand. If the second one
6104 is immediate operand, the source operand is the 3th
6105 one. If the last one is immediate operand, the source
6106 operand is the 2nd one. */
6107 gas_assert (i.imm_operands == 2
6108 && i.tm.opcode_modifier.sae
6109 && operand_type_check (i.types[0], imm));
6110 if (operand_type_check (i.types[1], imm))
6111 source = 2;
6112 else if (operand_type_check (i.types[4], imm))
6113 source = 1;
6114 else
6115 abort ();
6116 }
cab737b9
L		 6117 break;
6118 default:
6119 abort ();
6120 }
6121
c0f3af97
L		 6122 if (!vex_3_sources)
6123 {
6124 dest = source + 1;
6125
43234a1e
L		 6126 /* RC/SAE operand could be between DEST and SRC. That happens
6127 when one operand is GPR and the other one is XMM/YMM/ZMM
6128 register. */
6129 if (i.rounding && i.rounding->operand == (int) dest)
6130 dest++;
6131
2426c15f 6132 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6133 {
43234a1e
L		 6134 /* For instructions with VexNDS, the register-only source
6135 operand must be 32/64bit integer, XMM, YMM or ZMM
6136 register. It is encoded in VEX prefix. We need to
6137 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6138
6139 i386_operand_type op;
6140 unsigned int vvvv;
6141
6142 /* Check register-only source operand when two source
6143 operands are swapped. */
6144 if (!i.tm.operand_types[source].bitfield.baseindex
6145 && i.tm.operand_types[dest].bitfield.baseindex)
6146 {
6147 vvvv = source;
6148 source = dest;
6149 }
6150 else
6151 vvvv = dest;
6152
6153 op = i.tm.operand_types[vvvv];
fa99fab2 6154 op.bitfield.regmem = 0;
c0f3af97 6155 if ((dest + 1) >= i.operands
f12dc422
L		 6156 || (op.bitfield.reg32 != 1
6157 && !op.bitfield.reg64 != 1
6158 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6159 && !operand_type_equal (&op, &regymm)
6160 && !operand_type_equal (&op, &regzmm)
6161 && !operand_type_equal (&op, &regmask)))
c0f3af97 6162 abort ();
f12dc422 6163 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6164 dest++;
6165 }
6166 }
29b0f896
AM		 6167
6168 i.rm.mode = 3;
6169 /* One of the register operands will be encoded in the i.tm.reg
6170 field, the other in the combined i.tm.mode and i.tm.regmem
6171 fields. If no form of this instruction supports a memory
6172 destination operand, then we assume the source operand may
6173 sometimes be a memory operand and so we need to store the
6174 destination in the i.rm.reg field. */
40fb9820
L		 6175 if (!i.tm.operand_types[dest].bitfield.regmem
6176 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6177 {
6178 i.rm.reg = i.op[dest].regs->reg_num;
6179 i.rm.regmem = i.op[source].regs->reg_num;
6180 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6181 i.rex |= REX_R;
43234a1e
L		 6182 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6183 i.vrex |= REX_R;
29b0f896 6184 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6185 i.rex |= REX_B;
43234a1e
L		 6186 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6187 i.vrex |= REX_B;
29b0f896
AM		 6188 }
6189 else
6190 {
6191 i.rm.reg = i.op[source].regs->reg_num;
6192 i.rm.regmem = i.op[dest].regs->reg_num;
6193 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6194 i.rex |= REX_B;
43234a1e
L		 6195 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6196 i.vrex |= REX_B;
29b0f896 6197 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6198 i.rex |= REX_R;
43234a1e
L		 6199 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6200 i.vrex |= REX_R;
29b0f896 6201 }
161a04f6 6202 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6203 {
40fb9820
L		 6204 if (!i.types[0].bitfield.control
6205 && !i.types[1].bitfield.control)
c4a530c5 6206 abort ();
161a04f6 6207 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6208 add_prefix (LOCK_PREFIX_OPCODE);
6209 }
29b0f896
AM		 6210 }
6211 else
6212 { /* If it's not 2 reg operands... */
c0f3af97
L		 6213 unsigned int mem;
6214
29b0f896
AM		 6215 if (i.mem_operands)
6216 {
6217 unsigned int fake_zero_displacement = 0;
99018f42 6218 unsigned int op;
4eed87de 6219
7ab9ffdd
L		 6220 for (op = 0; op < i.operands; op++)
6221 if (operand_type_check (i.types[op], anymem))
6222 break;
7ab9ffdd 6223 gas_assert (op < i.operands);
29b0f896 6224
6c30d220
L		 6225 if (i.tm.opcode_modifier.vecsib)
6226 {
6227 if (i.index_reg->reg_num == RegEiz
6228 || i.index_reg->reg_num == RegRiz)
6229 abort ();
6230
6231 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6232 if (!i.base_reg)
6233 {
6234 i.sib.base = NO_BASE_REGISTER;
6235 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6236 /* No Vec_Disp8 if there is no base. */
6237 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6238 i.types[op].bitfield.disp8 = 0;
6239 i.types[op].bitfield.disp16 = 0;
6240 i.types[op].bitfield.disp64 = 0;
6241 if (flag_code != CODE_64BIT)
6242 {
6243 /* Must be 32 bit */
6244 i.types[op].bitfield.disp32 = 1;
6245 i.types[op].bitfield.disp32s = 0;
6246 }
6247 else
6248 {
6249 i.types[op].bitfield.disp32 = 0;
6250 i.types[op].bitfield.disp32s = 1;
6251 }
6252 }
6253 i.sib.index = i.index_reg->reg_num;
6254 if ((i.index_reg->reg_flags & RegRex) != 0)
6255 i.rex |= REX_X;
43234a1e
L		 6256 if ((i.index_reg->reg_flags & RegVRex) != 0)
6257 i.vrex |= REX_X;
6c30d220
L		 6258 }
6259
29b0f896
AM		 6260 default_seg = &ds;
6261
6262 if (i.base_reg == 0)
6263 {
6264 i.rm.mode = 0;
6265 if (!i.disp_operands)
6c30d220
L		 6266 {
6267 fake_zero_displacement = 1;
6268 /* Instructions with VSIB byte need 32bit displacement
6269 if there is no base register. */
6270 if (i.tm.opcode_modifier.vecsib)
6271 i.types[op].bitfield.disp32 = 1;
6272 }
29b0f896
AM		 6273 if (i.index_reg == 0)
6274 {
6c30d220 6275 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6276 /* Operand is just <disp> */
20f0a1fc 6277 if (flag_code == CODE_64BIT)
29b0f896
AM		 6278 {
6279 /* 64bit mode overwrites the 32bit absolute
6280 addressing by RIP relative addressing and
6281 absolute addressing is encoded by one of the
6282 redundant SIB forms. */
6283 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6284 i.sib.base = NO_BASE_REGISTER;
6285 i.sib.index = NO_INDEX_REGISTER;
fc225355 6286 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6287 ? disp32s : disp32);
20f0a1fc 6288 }
fc225355
L		 6289 else if ((flag_code == CODE_16BIT)
6290 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6291 {
6292 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6293 i.types[op] = disp16;
20f0a1fc
NC		 6294 }
6295 else
6296 {
6297 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6298 i.types[op] = disp32;
29b0f896
AM		 6299 }
6300 }
6c30d220 6301 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6302 {
6c30d220 6303 /* !i.base_reg && i.index_reg */
db51cc60
L		 6304 if (i.index_reg->reg_num == RegEiz
6305 || i.index_reg->reg_num == RegRiz)
6306 i.sib.index = NO_INDEX_REGISTER;
6307 else
6308 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6309 i.sib.base = NO_BASE_REGISTER;
6310 i.sib.scale = i.log2_scale_factor;
6311 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6312 /* No Vec_Disp8 if there is no base. */
6313 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6314 i.types[op].bitfield.disp8 = 0;
6315 i.types[op].bitfield.disp16 = 0;
6316 i.types[op].bitfield.disp64 = 0;
29b0f896 6317 if (flag_code != CODE_64BIT)
40fb9820
L		 6318 {
6319 /* Must be 32 bit */
6320 i.types[op].bitfield.disp32 = 1;
6321 i.types[op].bitfield.disp32s = 0;
6322 }
29b0f896 6323 else
40fb9820
L		 6324 {
6325 i.types[op].bitfield.disp32 = 0;
6326 i.types[op].bitfield.disp32s = 1;
6327 }
29b0f896 6328 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6329 i.rex |= REX_X;
29b0f896
AM		 6330 }
6331 }
6332 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6333 else if (i.base_reg->reg_num == RegRip ||
6334 i.base_reg->reg_num == RegEip)
29b0f896 6335 {
6c30d220 6336 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6337 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6338 i.types[op].bitfield.disp8 = 0;
6339 i.types[op].bitfield.disp16 = 0;
6340 i.types[op].bitfield.disp32 = 0;
6341 i.types[op].bitfield.disp32s = 1;
6342 i.types[op].bitfield.disp64 = 0;
43234a1e 6343 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6344 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6345 if (! i.disp_operands)
6346 fake_zero_displacement = 1;
29b0f896 6347 }
40fb9820 6348 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6349 {
6c30d220 6350 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6351 switch (i.base_reg->reg_num)
6352 {
6353 case 3: /* (%bx) */
6354 if (i.index_reg == 0)
6355 i.rm.regmem = 7;
6356 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6357 i.rm.regmem = i.index_reg->reg_num - 6;
6358 break;
6359 case 5: /* (%bp) */
6360 default_seg = &ss;
6361 if (i.index_reg == 0)
6362 {
6363 i.rm.regmem = 6;
40fb9820 6364 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6365 {
6366 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6367 if (i.tm.operand_types[op].bitfield.vec_disp8)
6368 i.types[op].bitfield.vec_disp8 = 1;
6369 else
6370 i.types[op].bitfield.disp8 = 1;
252b5132 6371 fake_zero_displacement = 1;
29b0f896
AM		 6372 }
6373 }
6374 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6375 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6376 break;
6377 default: /* (%si) -> 4 or (%di) -> 5 */
6378 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6379 }
6380 i.rm.mode = mode_from_disp_size (i.types[op]);
6381 }
6382 else /* i.base_reg and 32/64 bit mode */
6383 {
6384 if (flag_code == CODE_64BIT
40fb9820
L		 6385 && operand_type_check (i.types[op], disp))
6386 {
6387 i386_operand_type temp;
0dfbf9d7 6388 operand_type_set (&temp, 0);
40fb9820 6389 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6390 temp.bitfield.vec_disp8
6391 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6392 i.types[op] = temp;
6393 if (i.prefix[ADDR_PREFIX] == 0)
6394 i.types[op].bitfield.disp32s = 1;
6395 else
6396 i.types[op].bitfield.disp32 = 1;
6397 }
20f0a1fc 6398
6c30d220
L		 6399 if (!i.tm.opcode_modifier.vecsib)
6400 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6401 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6402 i.rex |= REX_B;
29b0f896
AM		 6403 i.sib.base = i.base_reg->reg_num;
6404 /* x86-64 ignores REX prefix bit here to avoid decoder
6405 complications. */
848930b2
JB		 6406 if (!(i.base_reg->reg_flags & RegRex)
6407 && (i.base_reg->reg_num == EBP_REG_NUM
6408 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6409 default_seg = &ss;
848930b2 6410 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6411 {
848930b2 6412 fake_zero_displacement = 1;
43234a1e
L		 6413 if (i.tm.operand_types [op].bitfield.vec_disp8)
6414 i.types[op].bitfield.vec_disp8 = 1;
6415 else
6416 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6417 }
6418 i.sib.scale = i.log2_scale_factor;
6419 if (i.index_reg == 0)
6420 {
6c30d220 6421 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6422 /* <disp>(%esp) becomes two byte modrm with no index
6423 register. We've already stored the code for esp
6424 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6425 Any base register besides %esp will not use the
6426 extra modrm byte. */
6427 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6428 }
6c30d220 6429 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6430 {
db51cc60
L		 6431 if (i.index_reg->reg_num == RegEiz
6432 || i.index_reg->reg_num == RegRiz)
6433 i.sib.index = NO_INDEX_REGISTER;
6434 else
6435 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6436 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6437 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6438 i.rex |= REX_X;
29b0f896 6439 }
67a4f2b7
AO		 6440
6441 if (i.disp_operands
6442 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6443 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6444 i.rm.mode = 0;
6445 else
a501d77e
L		 6446 {
6447 if (!fake_zero_displacement
6448 && !i.disp_operands
6449 && i.disp_encoding)
6450 {
6451 fake_zero_displacement = 1;
6452 if (i.disp_encoding == disp_encoding_8bit)
6453 i.types[op].bitfield.disp8 = 1;
6454 else
6455 i.types[op].bitfield.disp32 = 1;
6456 }
6457 i.rm.mode = mode_from_disp_size (i.types[op]);
6458 }
29b0f896 6459 }
252b5132 6460
29b0f896
AM		 6461 if (fake_zero_displacement)
6462 {
6463 /* Fakes a zero displacement assuming that i.types[op]
6464 holds the correct displacement size. */
6465 expressionS *exp;
6466
9c2799c2 6467 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6468 exp = &disp_expressions[i.disp_operands++];
6469 i.op[op].disps = exp;
6470 exp->X_op = O_constant;
6471 exp->X_add_number = 0;
6472 exp->X_add_symbol = (symbolS *) 0;
6473 exp->X_op_symbol = (symbolS *) 0;
6474 }
c0f3af97
L		 6475
6476 mem = op;
29b0f896 6477 }
c0f3af97
L		 6478 else
6479 mem = ~0;
252b5132 6480
8c43a48b 6481 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6482 {
6483 if (operand_type_check (i.types[0], imm))
6484 i.vex.register_specifier = NULL;
6485 else
6486 {
6487 /* VEX.vvvv encodes one of the sources when the first
6488 operand is not an immediate. */
1ef99a7b 6489 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6490 i.vex.register_specifier = i.op[0].regs;
6491 else
6492 i.vex.register_specifier = i.op[1].regs;
6493 }
6494
6495 /* Destination is a XMM register encoded in the ModRM.reg
6496 and VEX.R bit. */
6497 i.rm.reg = i.op[2].regs->reg_num;
6498 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6499 i.rex |= REX_R;
6500
6501 /* ModRM.rm and VEX.B encodes the other source. */
6502 if (!i.mem_operands)
6503 {
6504 i.rm.mode = 3;
6505
1ef99a7b 6506 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6507 i.rm.regmem = i.op[1].regs->reg_num;
6508 else
6509 i.rm.regmem = i.op[0].regs->reg_num;
6510
6511 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6512 i.rex |= REX_B;
6513 }
6514 }
2426c15f 6515 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6516 {
6517 i.vex.register_specifier = i.op[2].regs;
6518 if (!i.mem_operands)
6519 {
6520 i.rm.mode = 3;
6521 i.rm.regmem = i.op[1].regs->reg_num;
6522 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6523 i.rex |= REX_B;
6524 }
6525 }
29b0f896
AM		 6526 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6527 (if any) based on i.tm.extension_opcode. Again, we must be
6528 careful to make sure that segment/control/debug/test/MMX
6529 registers are coded into the i.rm.reg field. */
f88c9eb0 6530 else if (i.reg_operands)
29b0f896 6531 {
99018f42 6532 unsigned int op;
7ab9ffdd
L		 6533 unsigned int vex_reg = ~0;
6534
6535 for (op = 0; op < i.operands; op++)
6536 if (i.types[op].bitfield.reg8
6537 || i.types[op].bitfield.reg16
6538 || i.types[op].bitfield.reg32
6539 || i.types[op].bitfield.reg64
6540 || i.types[op].bitfield.regmmx
6541 || i.types[op].bitfield.regxmm
6542 || i.types[op].bitfield.regymm
7e8b059b 6543 || i.types[op].bitfield.regbnd
43234a1e
L		 6544 || i.types[op].bitfield.regzmm
6545 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6546 || i.types[op].bitfield.sreg2
6547 || i.types[op].bitfield.sreg3
6548 || i.types[op].bitfield.control
6549 || i.types[op].bitfield.debug
6550 || i.types[op].bitfield.test)
6551 break;
c0209578 6552
7ab9ffdd
L		 6553 if (vex_3_sources)
6554 op = dest;
2426c15f 6555 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6556 {
6557 /* For instructions with VexNDS, the register-only
6558 source operand is encoded in VEX prefix. */
6559 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6560
7ab9ffdd 6561 if (op > mem)
c0f3af97 6562 {
7ab9ffdd
L		 6563 vex_reg = op++;
6564 gas_assert (op < i.operands);
c0f3af97
L		 6565 }
6566 else
c0f3af97 6567 {
f12dc422
L		 6568 /* Check register-only source operand when two source
6569 operands are swapped. */
6570 if (!i.tm.operand_types[op].bitfield.baseindex
6571 && i.tm.operand_types[op + 1].bitfield.baseindex)
6572 {
6573 vex_reg = op;
6574 op += 2;
6575 gas_assert (mem == (vex_reg + 1)
6576 && op < i.operands);
6577 }
6578 else
6579 {
6580 vex_reg = op + 1;
6581 gas_assert (vex_reg < i.operands);
6582 }
c0f3af97 6583 }
7ab9ffdd 6584 }
2426c15f 6585 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6586 {
f12dc422 6587 /* For instructions with VexNDD, the register destination
7ab9ffdd 6588 is encoded in VEX prefix. */
f12dc422
L		 6589 if (i.mem_operands == 0)
6590 {
6591 /* There is no memory operand. */
6592 gas_assert ((op + 2) == i.operands);
6593 vex_reg = op + 1;
6594 }
6595 else
8d63c93e 6596 {
f12dc422
L		 6597 /* There are only 2 operands. */
6598 gas_assert (op < 2 && i.operands == 2);
6599 vex_reg = 1;
6600 }
7ab9ffdd
L		 6601 }
6602 else
6603 gas_assert (op < i.operands);
99018f42 6604
7ab9ffdd
L		 6605 if (vex_reg != (unsigned int) ~0)
6606 {
f12dc422 6607 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6608
f12dc422
L		 6609 if (type->bitfield.reg32 != 1
6610 && type->bitfield.reg64 != 1
6611 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6612 && !operand_type_equal (type, &regymm)
6613 && !operand_type_equal (type, &regzmm)
6614 && !operand_type_equal (type, &regmask))
7ab9ffdd 6615 abort ();
f88c9eb0 6616
7ab9ffdd
L		 6617 i.vex.register_specifier = i.op[vex_reg].regs;
6618 }
6619
1b9f0c97
L		 6620 /* Don't set OP operand twice. */
6621 if (vex_reg != op)
7ab9ffdd 6622 {
1b9f0c97
L		 6623 /* If there is an extension opcode to put here, the
6624 register number must be put into the regmem field. */
6625 if (i.tm.extension_opcode != None)
6626 {
6627 i.rm.regmem = i.op[op].regs->reg_num;
6628 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6629 i.rex |= REX_B;
43234a1e
L		 6630 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6631 i.vrex |= REX_B;
1b9f0c97
L		 6632 }
6633 else
6634 {
6635 i.rm.reg = i.op[op].regs->reg_num;
6636 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6637 i.rex |= REX_R;
43234a1e
L		 6638 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6639 i.vrex |= REX_R;
1b9f0c97 6640 }
7ab9ffdd 6641 }
252b5132 6642
29b0f896
AM		 6643 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6644 must set it to 3 to indicate this is a register operand
6645 in the regmem field. */
6646 if (!i.mem_operands)
6647 i.rm.mode = 3;
6648 }
252b5132 6649
29b0f896 6650 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6651 if (i.tm.extension_opcode != None)
29b0f896
AM		 6652 i.rm.reg = i.tm.extension_opcode;
6653 }
6654 return default_seg;
6655}
252b5132 6656
29b0f896 6657static void
e3bb37b5 6658output_branch (void)
29b0f896
AM		 6659{
6660 char *p;
f8a5c266 6661 int size;
29b0f896
AM		 6662 int code16;
6663 int prefix;
6664 relax_substateT subtype;
6665 symbolS *sym;
6666 offsetT off;
6667
f8a5c266 6668 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6669 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6670
6671 prefix = 0;
6672 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6673 {
29b0f896
AM		 6674 prefix = 1;
6675 i.prefixes -= 1;
6676 code16 ^= CODE16;
252b5132 6677 }
29b0f896
AM		 6678 /* Pentium4 branch hints. */
6679 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6680 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6681 {
29b0f896
AM		 6682 prefix++;
6683 i.prefixes--;
6684 }
6685 if (i.prefix[REX_PREFIX] != 0)
6686 {
6687 prefix++;
6688 i.prefixes--;
2f66722d
AM		 6689 }
6690
7e8b059b
L		 6691 /* BND prefixed jump. */
6692 if (i.prefix[BND_PREFIX] != 0)
6693 {
6694 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6695 i.prefixes -= 1;
6696 }
6697
29b0f896
AM		 6698 if (i.prefixes != 0 && !intel_syntax)
6699 as_warn (_("skipping prefixes on this instruction"));
6700
6701 /* It's always a symbol; End frag & setup for relax.
6702 Make sure there is enough room in this frag for the largest
6703 instruction we may generate in md_convert_frag. This is 2
6704 bytes for the opcode and room for the prefix and largest
6705 displacement. */
6706 frag_grow (prefix + 2 + 4);
6707 /* Prefix and 1 opcode byte go in fr_fix. */
6708 p = frag_more (prefix + 1);
6709 if (i.prefix[DATA_PREFIX] != 0)
6710 *p++ = DATA_PREFIX_OPCODE;
6711 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6712 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6713 *p++ = i.prefix[SEG_PREFIX];
6714 if (i.prefix[REX_PREFIX] != 0)
6715 *p++ = i.prefix[REX_PREFIX];
6716 *p = i.tm.base_opcode;
6717
6718 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6719 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6720 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6721 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6722 else
f8a5c266 6723 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6724 subtype |= code16;
3e73aa7c 6725
29b0f896
AM		 6726 sym = i.op[0].disps->X_add_symbol;
6727 off = i.op[0].disps->X_add_number;
3e73aa7c 6728
29b0f896
AM		 6729 if (i.op[0].disps->X_op != O_constant
6730 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6731 {
29b0f896
AM		 6732 /* Handle complex expressions. */
6733 sym = make_expr_symbol (i.op[0].disps);
6734 off = 0;
6735 }
3e73aa7c 6736
29b0f896
AM		 6737 /* 1 possible extra opcode + 4 byte displacement go in var part.
6738 Pass reloc in fr_var. */
c3320543
L		 6739 frag_var (rs_machine_dependent, 5,
6740 ((!object_64bit
6741 || i.reloc[0] != NO_RELOC
6742 || (i.bnd_prefix == NULL && !add_bnd_prefix))
6743 ? i.reloc[0]
6744 : BFD_RELOC_X86_64_PC32_BND),
6745 subtype, sym, off, p);
29b0f896 6746}
3e73aa7c 6747
29b0f896 6748static void
e3bb37b5 6749output_jump (void)
29b0f896
AM		 6750{
6751 char *p;
6752 int size;
3e02c1cc 6753 fixS *fixP;
29b0f896 6754
40fb9820 6755 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6756 {
6757 /* This is a loop or jecxz type instruction. */
6758 size = 1;
6759 if (i.prefix[ADDR_PREFIX] != 0)
6760 {
6761 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6762 i.prefixes -= 1;
6763 }
6764 /* Pentium4 branch hints. */
6765 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6766 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6767 {
6768 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6769 i.prefixes--;
3e73aa7c
JH		 6770 }
6771 }
29b0f896
AM		 6772 else
6773 {
6774 int code16;
3e73aa7c 6775
29b0f896
AM		 6776 code16 = 0;
6777 if (flag_code == CODE_16BIT)
6778 code16 = CODE16;
3e73aa7c 6779
29b0f896
AM		 6780 if (i.prefix[DATA_PREFIX] != 0)
6781 {
6782 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6783 i.prefixes -= 1;
6784 code16 ^= CODE16;
6785 }
252b5132 6786
29b0f896
AM		 6787 size = 4;
6788 if (code16)
6789 size = 2;
6790 }
9fcc94b6 6791
29b0f896
AM		 6792 if (i.prefix[REX_PREFIX] != 0)
6793 {
6794 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6795 i.prefixes -= 1;
6796 }
252b5132 6797
7e8b059b
L		 6798 /* BND prefixed jump. */
6799 if (i.prefix[BND_PREFIX] != 0)
6800 {
6801 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6802 i.prefixes -= 1;
6803 }
6804
29b0f896
AM		 6805 if (i.prefixes != 0 && !intel_syntax)
6806 as_warn (_("skipping prefixes on this instruction"));
e0890092 6807
42164a71
L		 6808 p = frag_more (i.tm.opcode_length + size);
6809 switch (i.tm.opcode_length)
6810 {
6811 case 2:
6812 *p++ = i.tm.base_opcode >> 8;
6813 case 1:
6814 *p++ = i.tm.base_opcode;
6815 break;
6816 default:
6817 abort ();
6818 }
e0890092 6819
3e02c1cc 6820 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
c3320543
L		 6821 i.op[0].disps, 1, reloc (size, 1, 1,
6822 (i.bnd_prefix != NULL
6823 || add_bnd_prefix),
6824 i.reloc[0]));
3e02c1cc
AM		 6825
6826 /* All jumps handled here are signed, but don't use a signed limit
6827 check for 32 and 16 bit jumps as we want to allow wrap around at
6828 4G and 64k respectively. */
6829 if (size == 1)
6830 fixP->fx_signed = 1;
29b0f896 6831}
e0890092 6832
29b0f896 6833static void
e3bb37b5 6834output_interseg_jump (void)
29b0f896
AM		 6835{
6836 char *p;
6837 int size;
6838 int prefix;
6839 int code16;
252b5132 6840
29b0f896
AM		 6841 code16 = 0;
6842 if (flag_code == CODE_16BIT)
6843 code16 = CODE16;
a217f122 6844
29b0f896
AM		 6845 prefix = 0;
6846 if (i.prefix[DATA_PREFIX] != 0)
6847 {
6848 prefix = 1;
6849 i.prefixes -= 1;
6850 code16 ^= CODE16;
6851 }
6852 if (i.prefix[REX_PREFIX] != 0)
6853 {
6854 prefix++;
6855 i.prefixes -= 1;
6856 }
252b5132 6857
29b0f896
AM		 6858 size = 4;
6859 if (code16)
6860 size = 2;
252b5132 6861
29b0f896
AM		 6862 if (i.prefixes != 0 && !intel_syntax)
6863 as_warn (_("skipping prefixes on this instruction"));
252b5132 6864
29b0f896
AM		 6865 /* 1 opcode; 2 segment; offset */
6866 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6867
29b0f896
AM		 6868 if (i.prefix[DATA_PREFIX] != 0)
6869 *p++ = DATA_PREFIX_OPCODE;
252b5132 6870
29b0f896
AM		 6871 if (i.prefix[REX_PREFIX] != 0)
6872 *p++ = i.prefix[REX_PREFIX];
252b5132 6873
29b0f896
AM		 6874 *p++ = i.tm.base_opcode;
6875 if (i.op[1].imms->X_op == O_constant)
6876 {
6877 offsetT n = i.op[1].imms->X_add_number;
252b5132 6878
29b0f896
AM		 6879 if (size == 2
6880 && !fits_in_unsigned_word (n)
6881 && !fits_in_signed_word (n))
6882 {
6883 as_bad (_("16-bit jump out of range"));
6884 return;
6885 }
6886 md_number_to_chars (p, n, size);
6887 }
6888 else
6889 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
c3320543 6890 i.op[1].imms, 0, reloc (size, 0, 0, 0, i.reloc[1]));
29b0f896
AM		 6891 if (i.op[0].imms->X_op != O_constant)
6892 as_bad (_("can't handle non absolute segment in `%s'"),
6893 i.tm.name);
6894 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6895}
a217f122 6896
29b0f896 6897static void
e3bb37b5 6898output_insn (void)
29b0f896 6899{
2bbd9c25
JJ		 6900 fragS *insn_start_frag;
6901 offsetT insn_start_off;
6902
29b0f896
AM		 6903 /* Tie dwarf2 debug info to the address at the start of the insn.
6904 We can't do this after the insn has been output as the current
6905 frag may have been closed off. eg. by frag_var. */
6906 dwarf2_emit_insn (0);
6907
2bbd9c25
JJ		 6908 insn_start_frag = frag_now;
6909 insn_start_off = frag_now_fix ();
6910
29b0f896 6911 /* Output jumps. */
40fb9820 6912 if (i.tm.opcode_modifier.jump)
29b0f896 6913 output_branch ();
40fb9820
L		 6914 else if (i.tm.opcode_modifier.jumpbyte
6915 || i.tm.opcode_modifier.jumpdword)
29b0f896 6916 output_jump ();
40fb9820 6917 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6918 output_interseg_jump ();
6919 else
6920 {
6921 /* Output normal instructions here. */
6922 char *p;
6923 unsigned char *q;
47465058 6924 unsigned int j;
331d2d0d 6925 unsigned int prefix;
4dffcebc 6926
43234a1e
L		 6927 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6928 don't need the explicit prefix. */
6929 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 6930 {
c0f3af97 6931 switch (i.tm.opcode_length)
bc4bd9ab 6932 {
c0f3af97
L		 6933 case 3:
6934 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6935 {
c0f3af97
L		 6936 prefix = (i.tm.base_opcode >> 24) & 0xff;
6937 goto check_prefix;
6938 }
6939 break;
6940 case 2:
6941 if ((i.tm.base_opcode & 0xff0000) != 0)
6942 {
6943 prefix = (i.tm.base_opcode >> 16) & 0xff;
6944 if (i.tm.cpu_flags.bitfield.cpupadlock)
6945 {
4dffcebc 6946check_prefix:
c0f3af97 6947 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6948 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6949 != REPE_PREFIX_OPCODE))
6950 add_prefix (prefix);
6951 }
6952 else
4dffcebc
L		 6953 add_prefix (prefix);
6954 }
c0f3af97
L		 6955 break;
6956 case 1:
6957 break;
6958 default:
6959 abort ();
bc4bd9ab 6960 }
c0f3af97
L		 6961
6962 /* The prefix bytes. */
6963 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
6964 if (*q)
6965 FRAG_APPEND_1_CHAR (*q);
0f10071e 6966 }
ae5c1c7b 6967 else
c0f3af97
L		 6968 {
6969 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
6970 if (*q)
6971 switch (j)
6972 {
6973 case REX_PREFIX:
6974 /* REX byte is encoded in VEX prefix. */
6975 break;
6976 case SEG_PREFIX:
6977 case ADDR_PREFIX:
6978 FRAG_APPEND_1_CHAR (*q);
6979 break;
6980 default:
6981 /* There should be no other prefixes for instructions
6982 with VEX prefix. */
6983 abort ();
6984 }
6985
43234a1e
L		 6986 /* For EVEX instructions i.vrex should become 0 after
6987 build_evex_prefix. For VEX instructions upper 16 registers
6988 aren't available, so VREX should be 0. */
6989 if (i.vrex)
6990 abort ();
c0f3af97
L		 6991 /* Now the VEX prefix. */
6992 p = frag_more (i.vex.length);
6993 for (j = 0; j < i.vex.length; j++)
6994 p[j] = i.vex.bytes[j];
6995 }
252b5132 6996
29b0f896 6997 /* Now the opcode; be careful about word order here! */
4dffcebc 6998 if (i.tm.opcode_length == 1)
29b0f896
AM		 6999 {
7000 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7001 }
7002 else
7003 {
4dffcebc 7004 switch (i.tm.opcode_length)
331d2d0d 7005 {
43234a1e
L		 7006 case 4:
7007 p = frag_more (4);
7008 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7009 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7010 break;
4dffcebc 7011 case 3:
331d2d0d
L		 7012 p = frag_more (3);
7013 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7014 break;
7015 case 2:
7016 p = frag_more (2);
7017 break;
7018 default:
7019 abort ();
7020 break;
331d2d0d 7021 }
0f10071e 7022
29b0f896
AM		 7023 /* Put out high byte first: can't use md_number_to_chars! */
7024 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7025 *p = i.tm.base_opcode & 0xff;
7026 }
3e73aa7c 7027
29b0f896 7028 /* Now the modrm byte and sib byte (if present). */
40fb9820 7029 if (i.tm.opcode_modifier.modrm)
29b0f896 7030 {
4a3523fa
L		 7031 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7032 | i.rm.reg << 3
7033 | i.rm.mode << 6));
29b0f896
AM		 7034 /* If i.rm.regmem == ESP (4)
7035 && i.rm.mode != (Register mode)
7036 && not 16 bit
7037 ==> need second modrm byte. */
7038 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7039 && i.rm.mode != 3
40fb9820 7040 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7041 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7042 | i.sib.index << 3
7043 | i.sib.scale << 6));
29b0f896 7044 }
3e73aa7c 7045
29b0f896 7046 if (i.disp_operands)
2bbd9c25 7047 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7048
29b0f896 7049 if (i.imm_operands)
2bbd9c25 7050 output_imm (insn_start_frag, insn_start_off);
29b0f896 7051 }
252b5132 7052
29b0f896
AM		 7053#ifdef DEBUG386
7054 if (flag_debug)
7055 {
7b81dfbb 7056 pi ("" /*line*/, &i);
29b0f896
AM		 7057 }
7058#endif /* DEBUG386 */
7059}
252b5132 7060
e205caa7
L		 7061/* Return the size of the displacement operand N. */
7062
7063static int
7064disp_size (unsigned int n)
7065{
7066 int size = 4;
43234a1e
L		 7067
7068 /* Vec_Disp8 has to be 8bit. */
7069 if (i.types[n].bitfield.vec_disp8)
7070 size = 1;
7071 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7072 size = 8;
7073 else if (i.types[n].bitfield.disp8)
7074 size = 1;
7075 else if (i.types[n].bitfield.disp16)
7076 size = 2;
e205caa7
L		 7077 return size;
7078}
7079
7080/* Return the size of the immediate operand N. */
7081
7082static int
7083imm_size (unsigned int n)
7084{
7085 int size = 4;
40fb9820
L		 7086 if (i.types[n].bitfield.imm64)
7087 size = 8;
7088 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7089 size = 1;
7090 else if (i.types[n].bitfield.imm16)
7091 size = 2;
e205caa7
L		 7092 return size;
7093}
7094
29b0f896 7095static void
64e74474 7096output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7097{
7098 char *p;
7099 unsigned int n;
252b5132 7100
29b0f896
AM		 7101 for (n = 0; n < i.operands; n++)
7102 {
43234a1e
L		 7103 if (i.types[n].bitfield.vec_disp8
7104 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7105 {
7106 if (i.op[n].disps->X_op == O_constant)
7107 {
e205caa7 7108 int size = disp_size (n);
43234a1e 7109 offsetT val = i.op[n].disps->X_add_number;
252b5132 7110
43234a1e
L		 7111 if (i.types[n].bitfield.vec_disp8)
7112 val >>= i.memshift;
7113 val = offset_in_range (val, size);
29b0f896
AM		 7114 p = frag_more (size);
7115 md_number_to_chars (p, val, size);
7116 }
7117 else
7118 {
f86103b7 7119 enum bfd_reloc_code_real reloc_type;
e205caa7 7120 int size = disp_size (n);
40fb9820 7121 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 7122 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7123
e205caa7 7124 /* We can't have 8 bit displacement here. */
9c2799c2 7125 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7126
29b0f896
AM		 7127 /* The PC relative address is computed relative
7128 to the instruction boundary, so in case immediate
7129 fields follows, we need to adjust the value. */
7130 if (pcrel && i.imm_operands)
7131 {
29b0f896 7132 unsigned int n1;
e205caa7 7133 int sz = 0;
252b5132 7134
29b0f896 7135 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7136 if (operand_type_check (i.types[n1], imm))
252b5132 7137 {
e205caa7
L		 7138 /* Only one immediate is allowed for PC
7139 relative address. */
9c2799c2 7140 gas_assert (sz == 0);
e205caa7
L		 7141 sz = imm_size (n1);
7142 i.op[n].disps->X_add_number -= sz;
252b5132 7143 }
29b0f896 7144 /* We should find the immediate. */
9c2799c2 7145 gas_assert (sz != 0);
29b0f896 7146 }
520dc8e8 7147
29b0f896 7148 p = frag_more (size);
c3320543
L		 7149 reloc_type = reloc (size, pcrel, sign,
7150 (i.bnd_prefix != NULL
7151 || add_bnd_prefix),
7152 i.reloc[n]);
d6ab8113 7153 if (GOT_symbol
2bbd9c25 7154 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7155 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7156 || reloc_type == BFD_RELOC_X86_64_32S
7157 || (reloc_type == BFD_RELOC_64
7158 && object_64bit))
d6ab8113
JB		 7159 && (i.op[n].disps->X_op == O_symbol
7160 || (i.op[n].disps->X_op == O_add
7161 && ((symbol_get_value_expression
7162 (i.op[n].disps->X_op_symbol)->X_op)
7163 == O_subtract))))
7164 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7165 {
7166 offsetT add;
7167
7168 if (insn_start_frag == frag_now)
7169 add = (p - frag_now->fr_literal) - insn_start_off;
7170 else
7171 {
7172 fragS *fr;
7173
7174 add = insn_start_frag->fr_fix - insn_start_off;
7175 for (fr = insn_start_frag->fr_next;
7176 fr && fr != frag_now; fr = fr->fr_next)
7177 add += fr->fr_fix;
7178 add += p - frag_now->fr_literal;
7179 }
7180
4fa24527 7181 if (!object_64bit)
7b81dfbb
AJ		 7182 {
7183 reloc_type = BFD_RELOC_386_GOTPC;
7184 i.op[n].imms->X_add_number += add;
7185 }
7186 else if (reloc_type == BFD_RELOC_64)
7187 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7188 else
7b81dfbb
AJ		 7189 /* Don't do the adjustment for x86-64, as there
7190 the pcrel addressing is relative to the _next_
7191 insn, and that is taken care of in other code. */
d6ab8113 7192 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7193 }
062cd5e7 7194 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 7195 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 7196 }
7197 }
7198 }
7199}
252b5132 7200
29b0f896 7201static void
64e74474 7202output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7203{
7204 char *p;
7205 unsigned int n;
252b5132 7206
29b0f896
AM		 7207 for (n = 0; n < i.operands; n++)
7208 {
43234a1e
L		 7209 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7210 if (i.rounding && (int) n == i.rounding->operand)
7211 continue;
7212
40fb9820 7213 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7214 {
7215 if (i.op[n].imms->X_op == O_constant)
7216 {
e205caa7 7217 int size = imm_size (n);
29b0f896 7218 offsetT val;
b4cac588 7219
29b0f896
AM		 7220 val = offset_in_range (i.op[n].imms->X_add_number,
7221 size);
7222 p = frag_more (size);
7223 md_number_to_chars (p, val, size);
7224 }
7225 else
7226 {
7227 /* Not absolute_section.
7228 Need a 32-bit fixup (don't support 8bit
7229 non-absolute imms). Try to support other
7230 sizes ... */
f86103b7 7231 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7232 int size = imm_size (n);
7233 int sign;
29b0f896 7234
40fb9820 7235 if (i.types[n].bitfield.imm32s
a7d61044 7236 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7237 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7238 sign = 1;
e205caa7
L		 7239 else
7240 sign = 0;
520dc8e8 7241
29b0f896 7242 p = frag_more (size);
c3320543 7243 reloc_type = reloc (size, 0, sign, 0, i.reloc[n]);
f86103b7 7244
2bbd9c25
JJ		 7245 /* This is tough to explain. We end up with this one if we
7246 * have operands that look like
7247 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7248 * obtain the absolute address of the GOT, and it is strongly
7249 * preferable from a performance point of view to avoid using
7250 * a runtime relocation for this. The actual sequence of
7251 * instructions often look something like:
7252 *
7253 * call .L66
7254 * .L66:
7255 * popl %ebx
7256 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7257 *
7258 * The call and pop essentially return the absolute address
7259 * of the label .L66 and store it in %ebx. The linker itself
7260 * will ultimately change the first operand of the addl so
7261 * that %ebx points to the GOT, but to keep things simple, the
7262 * .o file must have this operand set so that it generates not
7263 * the absolute address of .L66, but the absolute address of
7264 * itself. This allows the linker itself simply treat a GOTPC
7265 * relocation as asking for a pcrel offset to the GOT to be
7266 * added in, and the addend of the relocation is stored in the
7267 * operand field for the instruction itself.
7268 *
7269 * Our job here is to fix the operand so that it would add
7270 * the correct offset so that %ebx would point to itself. The
7271 * thing that is tricky is that .-.L66 will point to the
7272 * beginning of the instruction, so we need to further modify
7273 * the operand so that it will point to itself. There are
7274 * other cases where you have something like:
7275 *
7276 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7277 *
7278 * and here no correction would be required. Internally in
7279 * the assembler we treat operands of this form as not being
7280 * pcrel since the '.' is explicitly mentioned, and I wonder
7281 * whether it would simplify matters to do it this way. Who
7282 * knows. In earlier versions of the PIC patches, the
7283 * pcrel_adjust field was used to store the correction, but
7284 * since the expression is not pcrel, I felt it would be
7285 * confusing to do it this way. */
7286
d6ab8113 7287 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7288 || reloc_type == BFD_RELOC_X86_64_32S
7289 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7290 && GOT_symbol
7291 && GOT_symbol == i.op[n].imms->X_add_symbol
7292 && (i.op[n].imms->X_op == O_symbol
7293 || (i.op[n].imms->X_op == O_add
7294 && ((symbol_get_value_expression
7295 (i.op[n].imms->X_op_symbol)->X_op)
7296 == O_subtract))))
7297 {
2bbd9c25
JJ		 7298 offsetT add;
7299
7300 if (insn_start_frag == frag_now)
7301 add = (p - frag_now->fr_literal) - insn_start_off;
7302 else
7303 {
7304 fragS *fr;
7305
7306 add = insn_start_frag->fr_fix - insn_start_off;
7307 for (fr = insn_start_frag->fr_next;
7308 fr && fr != frag_now; fr = fr->fr_next)
7309 add += fr->fr_fix;
7310 add += p - frag_now->fr_literal;
7311 }
7312
4fa24527 7313 if (!object_64bit)
d6ab8113 7314 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7315 else if (size == 4)
d6ab8113 7316 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7317 else if (size == 8)
7318 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7319 i.op[n].imms->X_add_number += add;
29b0f896 7320 }
29b0f896
AM		 7321 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7322 i.op[n].imms, 0, reloc_type);
7323 }
7324 }
7325 }
252b5132
RH		 7326}
7327\f
d182319b
JB		 7328/* x86_cons_fix_new is called via the expression parsing code when a
7329 reloc is needed. We use this hook to get the correct .got reloc. */
7330static enum bfd_reloc_code_real got_reloc = NO_RELOC;
7331static int cons_sign = -1;
7332
7333void
e3bb37b5 7334x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 7335 expressionS *exp)
d182319b 7336{
c3320543 7337 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, 0, got_reloc);
d182319b
JB		 7338
7339 got_reloc = NO_RELOC;
7340
7341#ifdef TE_PE
7342 if (exp->X_op == O_secrel)
7343 {
7344 exp->X_op = O_symbol;
7345 r = BFD_RELOC_32_SECREL;
7346 }
7347#endif
7348
7349 fix_new_exp (frag, off, len, exp, 0, r);
7350}
7351
357d1bd8
L		 7352/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7353 purpose of the `.dc.a' internal pseudo-op. */
7354
7355int
7356x86_address_bytes (void)
7357{
7358 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7359 return 4;
7360 return stdoutput->arch_info->bits_per_address / 8;
7361}
7362
d382c579
TG		 7363#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7364 || defined (LEX_AT)
c06ec724 7365# define lex_got(reloc, adjust, types, bnd_prefix) NULL
718ddfc0 7366#else
f3c180ae
AM		 7367/* Parse operands of the form
7368 <symbol>@GOTOFF+<nnn>
7369 and similar .plt or .got references.
7370
7371 If we find one, set up the correct relocation in RELOC and copy the
7372 input string, minus the `@GOTOFF' into a malloc'd buffer for
7373 parsing by the calling routine. Return this buffer, and if ADJUST
7374 is non-null set it to the length of the string we removed from the
7375 input line. Otherwise return NULL. */
7376static char *
91d6fa6a 7377lex_got (enum bfd_reloc_code_real *rel,
64e74474 7378 int *adjust,
c3320543
L		 7379 i386_operand_type *types,
7380 int bnd_prefix)
f3c180ae 7381{
7b81dfbb
AJ		 7382 /* Some of the relocations depend on the size of what field is to
7383 be relocated. But in our callers i386_immediate and i386_displacement
7384 we don't yet know the operand size (this will be set by insn
7385 matching). Hence we record the word32 relocation here,
7386 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7387 static const struct {
7388 const char *str;
cff8d58a 7389 int len;
4fa24527 7390 const enum bfd_reloc_code_real rel[2];
40fb9820 7391 const i386_operand_type types64;
f3c180ae 7392 } gotrel[] = {
8ce3d284 7393#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7394 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7395 BFD_RELOC_SIZE32 },
7396 OPERAND_TYPE_IMM32_64 },
8ce3d284 7397#endif
cff8d58a
L		 7398 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7399 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7400 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7401 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7402 BFD_RELOC_X86_64_PLT32 },
40fb9820 7403 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7404 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7405 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7406 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7407 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7408 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7409 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7410 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7411 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7412 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7413 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7414 BFD_RELOC_X86_64_TLSGD },
40fb9820 7415 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7416 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7417 _dummy_first_bfd_reloc_code_real },
40fb9820 7418 OPERAND_TYPE_NONE },
cff8d58a
L		 7419 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7420 BFD_RELOC_X86_64_TLSLD },
40fb9820 7421 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7422 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7423 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7424 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7425 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7426 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7427 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7428 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7429 _dummy_first_bfd_reloc_code_real },
40fb9820 7430 OPERAND_TYPE_NONE },
cff8d58a
L		 7431 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7432 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7433 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7434 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7435 _dummy_first_bfd_reloc_code_real },
40fb9820 7436 OPERAND_TYPE_NONE },
cff8d58a
L		 7437 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7438 _dummy_first_bfd_reloc_code_real },
40fb9820 7439 OPERAND_TYPE_NONE },
cff8d58a
L		 7440 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7441 BFD_RELOC_X86_64_GOT32 },
40fb9820 7442 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7443 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7444 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7445 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7446 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7447 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7448 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7449 };
7450 char *cp;
7451 unsigned int j;
7452
d382c579 7453#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7454 if (!IS_ELF)
7455 return NULL;
d382c579 7456#endif
718ddfc0 7457
f3c180ae 7458 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7459 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7460 return NULL;
7461
47465058 7462 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7463 {
cff8d58a 7464 int len = gotrel[j].len;
28f81592 7465 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7466 {
4fa24527 7467 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7468 {
28f81592
AM		 7469 int first, second;
7470 char *tmpbuf, *past_reloc;
f3c180ae 7471
91d6fa6a 7472 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7473
3956db08
JB		 7474 if (types)
7475 {
7476 if (flag_code != CODE_64BIT)
40fb9820
L		 7477 {
7478 types->bitfield.imm32 = 1;
7479 types->bitfield.disp32 = 1;
7480 }
3956db08
JB		 7481 else
7482 *types = gotrel[j].types64;
7483 }
7484
8fd4256d 7485 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7486 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7487
28f81592 7488 /* The length of the first part of our input line. */
f3c180ae 7489 first = cp - input_line_pointer;
28f81592
AM		 7490
7491 /* The second part goes from after the reloc token until
67c11a9b 7492 (and including) an end_of_line char or comma. */
28f81592 7493 past_reloc = cp + 1 + len;
67c11a9b
AM		 7494 cp = past_reloc;
7495 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7496 ++cp;
7497 second = cp + 1 - past_reloc;
28f81592
AM		 7498
7499 /* Allocate and copy string. The trailing NUL shouldn't
7500 be necessary, but be safe. */
1e9cc1c2 7501 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 7502 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7503 if (second != 0 && *past_reloc != ' ')
7504 /* Replace the relocation token with ' ', so that
7505 errors like foo@GOTOFF1 will be detected. */
7506 tmpbuf[first++] = ' ';
af89796a
L		 7507 else
7508 /* Increment length by 1 if the relocation token is
7509 removed. */
7510 len++;
7511 if (adjust)
7512 *adjust = len;
0787a12d
AM		 7513 memcpy (tmpbuf + first, past_reloc, second);
7514 tmpbuf[first + second] = '\0';
c3320543
L		 7515 if (bnd_prefix && *rel == BFD_RELOC_X86_64_PLT32)
7516 *rel = BFD_RELOC_X86_64_PLT32_BND;
f3c180ae
AM		 7517 return tmpbuf;
7518 }
7519
4fa24527
JB		 7520 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7521 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7522 return NULL;
7523 }
7524 }
7525
7526 /* Might be a symbol version string. Don't as_bad here. */
7527 return NULL;
7528}
4e4f7c87 7529#endif
f3c180ae 7530
a988325c
NC		 7531#ifdef TE_PE
7532#ifdef lex_got
7533#undef lex_got
7534#endif
7535/* Parse operands of the form
7536 <symbol>@SECREL32+<nnn>
7537
7538 If we find one, set up the correct relocation in RELOC and copy the
7539 input string, minus the `@SECREL32' into a malloc'd buffer for
7540 parsing by the calling routine. Return this buffer, and if ADJUST
7541 is non-null set it to the length of the string we removed from the
34bca508
L		 7542 input line. Otherwise return NULL.
7543
a988325c
NC		 7544 This function is copied from the ELF version above adjusted for PE targets. */
7545
7546static char *
7547lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7548 int *adjust ATTRIBUTE_UNUSED,
c06ec724
L		 7549 i386_operand_type *types,
7550 int bnd_prefix ATTRIBUTE_UNUSED)
a988325c
NC		 7551{
7552 static const struct
7553 {
7554 const char *str;
7555 int len;
7556 const enum bfd_reloc_code_real rel[2];
7557 const i386_operand_type types64;
7558 }
7559 gotrel[] =
7560 {
7561 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7562 BFD_RELOC_32_SECREL },
7563 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7564 };
7565
7566 char *cp;
7567 unsigned j;
7568
7569 for (cp = input_line_pointer; *cp != '@'; cp++)
7570 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7571 return NULL;
7572
7573 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7574 {
7575 int len = gotrel[j].len;
7576
7577 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7578 {
7579 if (gotrel[j].rel[object_64bit] != 0)
7580 {
7581 int first, second;
7582 char *tmpbuf, *past_reloc;
7583
7584 *rel = gotrel[j].rel[object_64bit];
7585 if (adjust)
7586 *adjust = len;
7587
7588 if (types)
7589 {
7590 if (flag_code != CODE_64BIT)
7591 {
7592 types->bitfield.imm32 = 1;
7593 types->bitfield.disp32 = 1;
7594 }
7595 else
7596 *types = gotrel[j].types64;
7597 }
7598
7599 /* The length of the first part of our input line. */
7600 first = cp - input_line_pointer;
7601
7602 /* The second part goes from after the reloc token until
7603 (and including) an end_of_line char or comma. */
7604 past_reloc = cp + 1 + len;
7605 cp = past_reloc;
7606 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7607 ++cp;
7608 second = cp + 1 - past_reloc;
7609
7610 /* Allocate and copy string. The trailing NUL shouldn't
7611 be necessary, but be safe. */
7612 tmpbuf = (char *) xmalloc (first + second + 2);
7613 memcpy (tmpbuf, input_line_pointer, first);
7614 if (second != 0 && *past_reloc != ' ')
7615 /* Replace the relocation token with ' ', so that
7616 errors like foo@SECLREL321 will be detected. */
7617 tmpbuf[first++] = ' ';
7618 memcpy (tmpbuf + first, past_reloc, second);
7619 tmpbuf[first + second] = '\0';
7620 return tmpbuf;
7621 }
7622
7623 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7624 gotrel[j].str, 1 << (5 + object_64bit));
7625 return NULL;
7626 }
7627 }
7628
7629 /* Might be a symbol version string. Don't as_bad here. */
7630 return NULL;
7631}
7632
7633#endif /* TE_PE */
7634
f3c180ae 7635void
e3bb37b5 7636x86_cons (expressionS *exp, int size)
f3c180ae 7637{
ee86248c
JB		 7638 intel_syntax = -intel_syntax;
7639
3c7b9c2c 7640 exp->X_md = 0;
4fa24527 7641 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7642 {
7643 /* Handle @GOTOFF and the like in an expression. */
7644 char *save;
7645 char *gotfree_input_line;
4a57f2cf 7646 int adjust = 0;
f3c180ae
AM		 7647
7648 save = input_line_pointer;
c3320543 7649 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL, 0);
f3c180ae
AM		 7650 if (gotfree_input_line)
7651 input_line_pointer = gotfree_input_line;
7652
7653 expression (exp);
7654
7655 if (gotfree_input_line)
7656 {
7657 /* expression () has merrily parsed up to the end of line,
7658 or a comma - in the wrong buffer. Transfer how far
7659 input_line_pointer has moved to the right buffer. */
7660 input_line_pointer = (save
7661 + (input_line_pointer - gotfree_input_line)
7662 + adjust);
7663 free (gotfree_input_line);
3992d3b7
AM		 7664 if (exp->X_op == O_constant
7665 || exp->X_op == O_absent
7666 || exp->X_op == O_illegal
0398aac5 7667 || exp->X_op == O_register
3992d3b7
AM		 7668 || exp->X_op == O_big)
7669 {
7670 char c = *input_line_pointer;
7671 *input_line_pointer = 0;
7672 as_bad (_("missing or invalid expression `%s'"), save);
7673 *input_line_pointer = c;
7674 }
f3c180ae
AM		 7675 }
7676 }
7677 else
7678 expression (exp);
ee86248c
JB		 7679
7680 intel_syntax = -intel_syntax;
7681
7682 if (intel_syntax)
7683 i386_intel_simplify (exp);
f3c180ae 7684}
f3c180ae 7685
9f32dd5b
L		 7686static void
7687signed_cons (int size)
6482c264 7688{
d182319b
JB		 7689 if (flag_code == CODE_64BIT)
7690 cons_sign = 1;
7691 cons (size);
7692 cons_sign = -1;
6482c264
NC		 7693}
7694
d182319b 7695#ifdef TE_PE
6482c264 7696static void
7016a5d5 7697pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7698{
7699 expressionS exp;
7700
7701 do
7702 {
7703 expression (&exp);
7704 if (exp.X_op == O_symbol)
7705 exp.X_op = O_secrel;
7706
7707 emit_expr (&exp, 4);
7708 }
7709 while (*input_line_pointer++ == ',');
7710
7711 input_line_pointer--;
7712 demand_empty_rest_of_line ();
7713}
6482c264
NC		 7714#endif
7715
43234a1e
L		 7716/* Handle Vector operations. */
7717
7718static char *
7719check_VecOperations (char *op_string, char *op_end)
7720{
7721 const reg_entry *mask;
7722 const char *saved;
7723 char *end_op;
7724
7725 while (*op_string
7726 && (op_end == NULL || op_string < op_end))
7727 {
7728 saved = op_string;
7729 if (*op_string == '{')
7730 {
7731 op_string++;
7732
7733 /* Check broadcasts. */
7734 if (strncmp (op_string, "1to", 3) == 0)
7735 {
7736 int bcst_type;
7737
7738 if (i.broadcast)
7739 goto duplicated_vec_op;
7740
7741 op_string += 3;
7742 if (*op_string == '8')
7743 bcst_type = BROADCAST_1TO8;
7744 else if (*op_string == '1'
7745 && *(op_string+1) == '6')
7746 {
7747 bcst_type = BROADCAST_1TO16;
7748 op_string++;
7749 }
7750 else
7751 {
7752 as_bad (_("Unsupported broadcast: `%s'"), saved);
7753 return NULL;
7754 }
7755 op_string++;
7756
7757 broadcast_op.type = bcst_type;
7758 broadcast_op.operand = this_operand;
7759 i.broadcast = &broadcast_op;
7760 }
7761 /* Check masking operation. */
7762 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7763 {
7764 /* k0 can't be used for write mask. */
7765 if (mask->reg_num == 0)
7766 {
7767 as_bad (_("`%s' can't be used for write mask"),
7768 op_string);
7769 return NULL;
7770 }
7771
7772 if (!i.mask)
7773 {
7774 mask_op.mask = mask;
7775 mask_op.zeroing = 0;
7776 mask_op.operand = this_operand;
7777 i.mask = &mask_op;
7778 }
7779 else
7780 {
7781 if (i.mask->mask)
7782 goto duplicated_vec_op;
7783
7784 i.mask->mask = mask;
7785
7786 /* Only "{z}" is allowed here. No need to check
7787 zeroing mask explicitly. */
7788 if (i.mask->operand != this_operand)
7789 {
7790 as_bad (_("invalid write mask `%s'"), saved);
7791 return NULL;
7792 }
7793 }
7794
7795 op_string = end_op;
7796 }
7797 /* Check zeroing-flag for masking operation. */
7798 else if (*op_string == 'z')
7799 {
7800 if (!i.mask)
7801 {
7802 mask_op.mask = NULL;
7803 mask_op.zeroing = 1;
7804 mask_op.operand = this_operand;
7805 i.mask = &mask_op;
7806 }
7807 else
7808 {
7809 if (i.mask->zeroing)
7810 {
7811 duplicated_vec_op:
7812 as_bad (_("duplicated `%s'"), saved);
7813 return NULL;
7814 }
7815
7816 i.mask->zeroing = 1;
7817
7818 /* Only "{%k}" is allowed here. No need to check mask
7819 register explicitly. */
7820 if (i.mask->operand != this_operand)
7821 {
7822 as_bad (_("invalid zeroing-masking `%s'"),
7823 saved);
7824 return NULL;
7825 }
7826 }
7827
7828 op_string++;
7829 }
7830 else
7831 goto unknown_vec_op;
7832
7833 if (*op_string != '}')
7834 {
7835 as_bad (_("missing `}' in `%s'"), saved);
7836 return NULL;
7837 }
7838 op_string++;
7839 continue;
7840 }
7841 unknown_vec_op:
7842 /* We don't know this one. */
7843 as_bad (_("unknown vector operation: `%s'"), saved);
7844 return NULL;
7845 }
7846
7847 return op_string;
7848}
7849
252b5132 7850static int
70e41ade 7851i386_immediate (char *imm_start)
252b5132
RH		 7852{
7853 char *save_input_line_pointer;
f3c180ae 7854 char *gotfree_input_line;
252b5132 7855 segT exp_seg = 0;
47926f60 7856 expressionS *exp;
40fb9820
L		 7857 i386_operand_type types;
7858
0dfbf9d7 7859 operand_type_set (&types, ~0);
252b5132
RH		 7860
7861 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7862 {
31b2323c
L		 7863 as_bad (_("at most %d immediate operands are allowed"),
7864 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 7865 return 0;
7866 }
7867
7868 exp = &im_expressions[i.imm_operands++];
520dc8e8 7869 i.op[this_operand].imms = exp;
252b5132
RH		 7870
7871 if (is_space_char (*imm_start))
7872 ++imm_start;
7873
7874 save_input_line_pointer = input_line_pointer;
7875 input_line_pointer = imm_start;
7876
c3320543
L		 7877 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types,
7878 (i.bnd_prefix != NULL
7879 || add_bnd_prefix));
f3c180ae
AM		 7880 if (gotfree_input_line)
7881 input_line_pointer = gotfree_input_line;
252b5132
RH		 7882
7883 exp_seg = expression (exp);
7884
83183c0c 7885 SKIP_WHITESPACE ();
43234a1e
L		 7886
7887 /* Handle vector operations. */
7888 if (*input_line_pointer == '{')
7889 {
7890 input_line_pointer = check_VecOperations (input_line_pointer,
7891 NULL);
7892 if (input_line_pointer == NULL)
7893 return 0;
7894 }
7895
252b5132 7896 if (*input_line_pointer)
f3c180ae 7897 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 7898
7899 input_line_pointer = save_input_line_pointer;
f3c180ae 7900 if (gotfree_input_line)
ee86248c
JB		 7901 {
7902 free (gotfree_input_line);
7903
7904 if (exp->X_op == O_constant || exp->X_op == O_register)
7905 exp->X_op = O_illegal;
7906 }
7907
7908 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7909}
252b5132 7910
ee86248c
JB		 7911static int
7912i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7913 i386_operand_type types, const char *imm_start)
7914{
7915 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 7916 {
313c53d1
L		 7917 if (imm_start)
7918 as_bad (_("missing or invalid immediate expression `%s'"),
7919 imm_start);
3992d3b7 7920 return 0;
252b5132 7921 }
3e73aa7c 7922 else if (exp->X_op == O_constant)
252b5132 7923 {
47926f60 7924 /* Size it properly later. */
40fb9820 7925 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 7926 /* If not 64bit, sign extend val. */
7927 if (flag_code != CODE_64BIT
4eed87de
AM		 7928 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7929 exp->X_add_number
7930 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 7931 }
4c63da97 7932#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 7933 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 7934 && exp_seg != absolute_section
47926f60 7935 && exp_seg != text_section
24eab124
AM		 7936 && exp_seg != data_section
7937 && exp_seg != bss_section
7938 && exp_seg != undefined_section
f86103b7 7939 && !bfd_is_com_section (exp_seg))
252b5132 7940 {
d0b47220 7941 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 7942 return 0;
7943 }
7944#endif
bb8f5920
L		 7945 else if (!intel_syntax && exp->X_op == O_register)
7946 {
313c53d1
L		 7947 if (imm_start)
7948 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 7949 return 0;
7950 }
252b5132
RH		 7951 else
7952 {
7953 /* This is an address. The size of the address will be
24eab124 7954 determined later, depending on destination register,
3e73aa7c 7955 suffix, or the default for the section. */
40fb9820
L		 7956 i.types[this_operand].bitfield.imm8 = 1;
7957 i.types[this_operand].bitfield.imm16 = 1;
7958 i.types[this_operand].bitfield.imm32 = 1;
7959 i.types[this_operand].bitfield.imm32s = 1;
7960 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 7961 i.types[this_operand] = operand_type_and (i.types[this_operand],
7962 types);
252b5132
RH		 7963 }
7964
7965 return 1;
7966}
7967
551c1ca1 7968static char *
e3bb37b5 7969i386_scale (char *scale)
252b5132 7970{
551c1ca1
AM		 7971 offsetT val;
7972 char *save = input_line_pointer;
252b5132 7973
551c1ca1
AM		 7974 input_line_pointer = scale;
7975 val = get_absolute_expression ();
7976
7977 switch (val)
252b5132 7978 {
551c1ca1 7979 case 1:
252b5132
RH		 7980 i.log2_scale_factor = 0;
7981 break;
551c1ca1 7982 case 2:
252b5132
RH		 7983 i.log2_scale_factor = 1;
7984 break;
551c1ca1 7985 case 4:
252b5132
RH		 7986 i.log2_scale_factor = 2;
7987 break;
551c1ca1 7988 case 8:
252b5132
RH		 7989 i.log2_scale_factor = 3;
7990 break;
7991 default:
a724f0f4
JB		 7992 {
7993 char sep = *input_line_pointer;
7994
7995 *input_line_pointer = '\0';
7996 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
7997 scale);
7998 *input_line_pointer = sep;
7999 input_line_pointer = save;
8000 return NULL;
8001 }
252b5132 8002 }
29b0f896 8003 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8004 {
8005 as_warn (_("scale factor of %d without an index register"),
24eab124 8006 1 << i.log2_scale_factor);
252b5132 8007 i.log2_scale_factor = 0;
252b5132 8008 }
551c1ca1
AM		 8009 scale = input_line_pointer;
8010 input_line_pointer = save;
8011 return scale;
252b5132
RH		 8012}
8013
252b5132 8014static int
e3bb37b5 8015i386_displacement (char *disp_start, char *disp_end)
252b5132 8016{
29b0f896 8017 expressionS *exp;
252b5132
RH		 8018 segT exp_seg = 0;
8019 char *save_input_line_pointer;
f3c180ae 8020 char *gotfree_input_line;
40fb9820
L		 8021 int override;
8022 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8023 int ret;
252b5132 8024
31b2323c
L		 8025 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8026 {
8027 as_bad (_("at most %d displacement operands are allowed"),
8028 MAX_MEMORY_OPERANDS);
8029 return 0;
8030 }
8031
0dfbf9d7 8032 operand_type_set (&bigdisp, 0);
40fb9820
L		 8033 if ((i.types[this_operand].bitfield.jumpabsolute)
8034 || (!current_templates->start->opcode_modifier.jump
8035 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8036 {
40fb9820 8037 bigdisp.bitfield.disp32 = 1;
e05278af 8038 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8039 if (flag_code == CODE_64BIT)
8040 {
8041 if (!override)
8042 {
8043 bigdisp.bitfield.disp32s = 1;
8044 bigdisp.bitfield.disp64 = 1;
8045 }
8046 }
8047 else if ((flag_code == CODE_16BIT) ^ override)
8048 {
8049 bigdisp.bitfield.disp32 = 0;
8050 bigdisp.bitfield.disp16 = 1;
8051 }
e05278af
JB		 8052 }
8053 else
8054 {
8055 /* For PC-relative branches, the width of the displacement
8056 is dependent upon data size, not address size. */
e05278af 8057 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8058 if (flag_code == CODE_64BIT)
8059 {
8060 if (override || i.suffix == WORD_MNEM_SUFFIX)
8061 bigdisp.bitfield.disp16 = 1;
8062 else
8063 {
8064 bigdisp.bitfield.disp32 = 1;
8065 bigdisp.bitfield.disp32s = 1;
8066 }
8067 }
8068 else
e05278af
JB		 8069 {
8070 if (!override)
8071 override = (i.suffix == (flag_code != CODE_16BIT
8072 ? WORD_MNEM_SUFFIX
8073 : LONG_MNEM_SUFFIX));
40fb9820
L		 8074 bigdisp.bitfield.disp32 = 1;
8075 if ((flag_code == CODE_16BIT) ^ override)
8076 {
8077 bigdisp.bitfield.disp32 = 0;
8078 bigdisp.bitfield.disp16 = 1;
8079 }
e05278af 8080 }
e05278af 8081 }
c6fb90c8
L		 8082 i.types[this_operand] = operand_type_or (i.types[this_operand],
8083 bigdisp);
252b5132
RH		 8084
8085 exp = &disp_expressions[i.disp_operands];
520dc8e8 8086 i.op[this_operand].disps = exp;
252b5132
RH		 8087 i.disp_operands++;
8088 save_input_line_pointer = input_line_pointer;
8089 input_line_pointer = disp_start;
8090 END_STRING_AND_SAVE (disp_end);
8091
8092#ifndef GCC_ASM_O_HACK
8093#define GCC_ASM_O_HACK 0
8094#endif
8095#if GCC_ASM_O_HACK
8096 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8097 if (i.types[this_operand].bitfield.baseIndex
24eab124 8098 && displacement_string_end[-1] == '+')
252b5132
RH		 8099 {
8100 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8101 constraint within gcc asm statements.
8102 For instance:
8103
8104 #define _set_tssldt_desc(n,addr,limit,type) \
8105 __asm__ __volatile__ ( \
8106 "movw %w2,%0\n\t" \
8107 "movw %w1,2+%0\n\t" \
8108 "rorl $16,%1\n\t" \
8109 "movb %b1,4+%0\n\t" \
8110 "movb %4,5+%0\n\t" \
8111 "movb $0,6+%0\n\t" \
8112 "movb %h1,7+%0\n\t" \
8113 "rorl $16,%1" \
8114 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8115
8116 This works great except that the output assembler ends
8117 up looking a bit weird if it turns out that there is
8118 no offset. You end up producing code that looks like:
8119
8120 #APP
8121 movw $235,(%eax)
8122 movw %dx,2+(%eax)
8123 rorl $16,%edx
8124 movb %dl,4+(%eax)
8125 movb $137,5+(%eax)
8126 movb $0,6+(%eax)
8127 movb %dh,7+(%eax)
8128 rorl $16,%edx
8129 #NO_APP
8130
47926f60 8131 So here we provide the missing zero. */
24eab124
AM		 8132
8133 *displacement_string_end = '0';
252b5132
RH		 8134 }
8135#endif
c3320543
L		 8136 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types,
8137 (i.bnd_prefix != NULL
8138 || add_bnd_prefix));
f3c180ae
AM		 8139 if (gotfree_input_line)
8140 input_line_pointer = gotfree_input_line;
252b5132 8141
24eab124 8142 exp_seg = expression (exp);
252b5132 8143
636c26b0
AM		 8144 SKIP_WHITESPACE ();
8145 if (*input_line_pointer)
8146 as_bad (_("junk `%s' after expression"), input_line_pointer);
8147#if GCC_ASM_O_HACK
8148 RESTORE_END_STRING (disp_end + 1);
8149#endif
636c26b0 8150 input_line_pointer = save_input_line_pointer;
636c26b0 8151 if (gotfree_input_line)
ee86248c
JB		 8152 {
8153 free (gotfree_input_line);
8154
8155 if (exp->X_op == O_constant || exp->X_op == O_register)
8156 exp->X_op = O_illegal;
8157 }
8158
8159 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8160
8161 RESTORE_END_STRING (disp_end);
8162
8163 return ret;
8164}
8165
8166static int
8167i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8168 i386_operand_type types, const char *disp_start)
8169{
8170 i386_operand_type bigdisp;
8171 int ret = 1;
636c26b0 8172
24eab124
AM		 8173 /* We do this to make sure that the section symbol is in
8174 the symbol table. We will ultimately change the relocation
47926f60 8175 to be relative to the beginning of the section. */
1ae12ab7 8176 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8177 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8178 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8179 {
636c26b0 8180 if (exp->X_op != O_symbol)
3992d3b7 8181 goto inv_disp;
636c26b0 8182
e5cb08ac 8183 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8184 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8185 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8186 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8187 exp->X_op = O_subtract;
8188 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8189 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8190 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8191 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8192 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8193 else
29b0f896 8194 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8195 }
252b5132 8196
3992d3b7
AM		 8197 else if (exp->X_op == O_absent
8198 || exp->X_op == O_illegal
ee86248c 8199 || exp->X_op == O_big)
2daf4fd8 8200 {
3992d3b7
AM		 8201 inv_disp:
8202 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8203 disp_start);
3992d3b7 8204 ret = 0;
2daf4fd8
AM		 8205 }
8206
0e1147d9
L		 8207 else if (flag_code == CODE_64BIT
8208 && !i.prefix[ADDR_PREFIX]
8209 && exp->X_op == O_constant)
8210 {
8211 /* Since displacement is signed extended to 64bit, don't allow
8212 disp32 and turn off disp32s if they are out of range. */
8213 i.types[this_operand].bitfield.disp32 = 0;
8214 if (!fits_in_signed_long (exp->X_add_number))
8215 {
8216 i.types[this_operand].bitfield.disp32s = 0;
8217 if (i.types[this_operand].bitfield.baseindex)
8218 {
8219 as_bad (_("0x%lx out range of signed 32bit displacement"),
8220 (long) exp->X_add_number);
8221 ret = 0;
8222 }
8223 }
8224 }
8225
4c63da97 8226#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8227 else if (exp->X_op != O_constant
8228 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8229 && exp_seg != absolute_section
8230 && exp_seg != text_section
8231 && exp_seg != data_section
8232 && exp_seg != bss_section
8233 && exp_seg != undefined_section
8234 && !bfd_is_com_section (exp_seg))
24eab124 8235 {
d0b47220 8236 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8237 ret = 0;
24eab124 8238 }
252b5132 8239#endif
3956db08 8240
40fb9820
L		 8241 /* Check if this is a displacement only operand. */
8242 bigdisp = i.types[this_operand];
8243 bigdisp.bitfield.disp8 = 0;
8244 bigdisp.bitfield.disp16 = 0;
8245 bigdisp.bitfield.disp32 = 0;
8246 bigdisp.bitfield.disp32s = 0;
8247 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8248 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8249 i.types[this_operand] = operand_type_and (i.types[this_operand],
8250 types);
3956db08 8251
3992d3b7 8252 return ret;
252b5132
RH		 8253}
8254
eecb386c 8255/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8256 Return 1 on success, 0 on a failure. */
8257
252b5132 8258static int
e3bb37b5 8259i386_index_check (const char *operand_string)
252b5132 8260{
fc0763e6 8261 const char *kind = "base/index";
be05d201
L		 8262 enum flag_code addr_mode;
8263
8264 if (i.prefix[ADDR_PREFIX])
8265 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8266 else
8267 {
8268 addr_mode = flag_code;
8269
24eab124 8270#if INFER_ADDR_PREFIX
be05d201
L		 8271 if (i.mem_operands == 0)
8272 {
8273 /* Infer address prefix from the first memory operand. */
8274 const reg_entry *addr_reg = i.base_reg;
8275
8276 if (addr_reg == NULL)
8277 addr_reg = i.index_reg;
eecb386c 8278
be05d201
L		 8279 if (addr_reg)
8280 {
8281 if (addr_reg->reg_num == RegEip
8282 || addr_reg->reg_num == RegEiz
8283 || addr_reg->reg_type.bitfield.reg32)
8284 addr_mode = CODE_32BIT;
8285 else if (flag_code != CODE_64BIT
8286 && addr_reg->reg_type.bitfield.reg16)
8287 addr_mode = CODE_16BIT;
8288
8289 if (addr_mode != flag_code)
8290 {
8291 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8292 i.prefixes += 1;
8293 /* Change the size of any displacement too. At most one
8294 of Disp16 or Disp32 is set.
8295 FIXME. There doesn't seem to be any real need for
8296 separate Disp16 and Disp32 flags. The same goes for
8297 Imm16 and Imm32. Removing them would probably clean
8298 up the code quite a lot. */
8299 if (flag_code != CODE_64BIT
8300 && (i.types[this_operand].bitfield.disp16
8301 || i.types[this_operand].bitfield.disp32))
8302 i.types[this_operand]
8303 = operand_type_xor (i.types[this_operand], disp16_32);
8304 }
8305 }
8306 }
24eab124 8307#endif
be05d201
L		 8308 }
8309
fc0763e6
JB		 8310 if (current_templates->start->opcode_modifier.isstring
8311 && !current_templates->start->opcode_modifier.immext
8312 && (current_templates->end[-1].opcode_modifier.isstring
8313 || i.mem_operands))
8314 {
8315 /* Memory operands of string insns are special in that they only allow
8316 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8317 const reg_entry *expected_reg;
8318 static const char *di_si[][2] =
8319 {
8320 { "esi", "edi" },
8321 { "si", "di" },
8322 { "rsi", "rdi" }
8323 };
8324 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8325
8326 kind = "string address";
8327
8328 if (current_templates->start->opcode_modifier.w)
8329 {
8330 i386_operand_type type = current_templates->end[-1].operand_types[0];
8331
8332 if (!type.bitfield.baseindex
8333 || ((!i.mem_operands != !intel_syntax)
8334 && current_templates->end[-1].operand_types[1]
8335 .bitfield.baseindex))
8336 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8337 expected_reg = hash_find (reg_hash,
8338 di_si[addr_mode][type.bitfield.esseg]);
8339
fc0763e6
JB		 8340 }
8341 else
be05d201 8342 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8343
be05d201
L		 8344 if (i.base_reg != expected_reg
8345 || i.index_reg
fc0763e6 8346 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8347 {
be05d201
L		 8348 /* The second memory operand must have the same size as
8349 the first one. */
8350 if (i.mem_operands
8351 && i.base_reg
8352 && !((addr_mode == CODE_64BIT
8353 && i.base_reg->reg_type.bitfield.reg64)
8354 || (addr_mode == CODE_32BIT
8355 ? i.base_reg->reg_type.bitfield.reg32
8356 : i.base_reg->reg_type.bitfield.reg16)))
8357 goto bad_address;
8358
fc0763e6
JB		 8359 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8360 operand_string,
8361 intel_syntax ? '[' : '(',
8362 register_prefix,
be05d201 8363 expected_reg->reg_name,
fc0763e6 8364 intel_syntax ? ']' : ')');
be05d201 8365 return 1;
fc0763e6 8366 }
be05d201
L		 8367 else
8368 return 1;
8369
8370bad_address:
8371 as_bad (_("`%s' is not a valid %s expression"),
8372 operand_string, kind);
8373 return 0;
3e73aa7c
JH		 8374 }
8375 else
8376 {
be05d201
L		 8377 if (addr_mode != CODE_16BIT)
8378 {
8379 /* 32-bit/64-bit checks. */
8380 if ((i.base_reg
8381 && (addr_mode == CODE_64BIT
8382 ? !i.base_reg->reg_type.bitfield.reg64
8383 : !i.base_reg->reg_type.bitfield.reg32)
8384 && (i.index_reg
8385 || (i.base_reg->reg_num
8386 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8387 || (i.index_reg
8388 && !i.index_reg->reg_type.bitfield.regxmm
8389 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8390 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8391 && ((addr_mode == CODE_64BIT
8392 ? !(i.index_reg->reg_type.bitfield.reg64
8393 || i.index_reg->reg_num == RegRiz)
8394 : !(i.index_reg->reg_type.bitfield.reg32
8395 || i.index_reg->reg_num == RegEiz))
8396 || !i.index_reg->reg_type.bitfield.baseindex)))
8397 goto bad_address;
8398 }
8399 else
3e73aa7c 8400 {
be05d201 8401 /* 16-bit checks. */
3e73aa7c 8402 if ((i.base_reg
40fb9820
L		 8403 && (!i.base_reg->reg_type.bitfield.reg16
8404 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8405 || (i.index_reg
40fb9820
L		 8406 && (!i.index_reg->reg_type.bitfield.reg16
8407 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8408 || !(i.base_reg
8409 && i.base_reg->reg_num < 6
8410 && i.index_reg->reg_num >= 6
8411 && i.log2_scale_factor == 0))))
be05d201 8412 goto bad_address;
3e73aa7c
JH		 8413 }
8414 }
be05d201 8415 return 1;
24eab124 8416}
252b5132 8417
43234a1e
L		 8418/* Handle vector immediates. */
8419
8420static int
8421RC_SAE_immediate (const char *imm_start)
8422{
8423 unsigned int match_found, j;
8424 const char *pstr = imm_start;
8425 expressionS *exp;
8426
8427 if (*pstr != '{')
8428 return 0;
8429
8430 pstr++;
8431 match_found = 0;
8432 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8433 {
8434 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8435 {
8436 if (!i.rounding)
8437 {
8438 rc_op.type = RC_NamesTable[j].type;
8439 rc_op.operand = this_operand;
8440 i.rounding = &rc_op;
8441 }
8442 else
8443 {
8444 as_bad (_("duplicated `%s'"), imm_start);
8445 return 0;
8446 }
8447 pstr += RC_NamesTable[j].len;
8448 match_found = 1;
8449 break;
8450 }
8451 }
8452 if (!match_found)
8453 return 0;
8454
8455 if (*pstr++ != '}')
8456 {
8457 as_bad (_("Missing '}': '%s'"), imm_start);
8458 return 0;
8459 }
8460 /* RC/SAE immediate string should contain nothing more. */;
8461 if (*pstr != 0)
8462 {
8463 as_bad (_("Junk after '}': '%s'"), imm_start);
8464 return 0;
8465 }
8466
8467 exp = &im_expressions[i.imm_operands++];
8468 i.op[this_operand].imms = exp;
8469
8470 exp->X_op = O_constant;
8471 exp->X_add_number = 0;
8472 exp->X_add_symbol = (symbolS *) 0;
8473 exp->X_op_symbol = (symbolS *) 0;
8474
8475 i.types[this_operand].bitfield.imm8 = 1;
8476 return 1;
8477}
8478
fc0763e6 8479/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8480 on error. */
252b5132 8481
252b5132 8482static int
a7619375 8483i386_att_operand (char *operand_string)
252b5132 8484{
af6bdddf
AM		 8485 const reg_entry *r;
8486 char *end_op;
24eab124 8487 char *op_string = operand_string;
252b5132 8488
24eab124 8489 if (is_space_char (*op_string))
252b5132
RH		 8490 ++op_string;
8491
24eab124 8492 /* We check for an absolute prefix (differentiating,
47926f60 8493 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8494 if (*op_string == ABSOLUTE_PREFIX)
8495 {
8496 ++op_string;
8497 if (is_space_char (*op_string))
8498 ++op_string;
40fb9820 8499 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8500 }
252b5132 8501
47926f60 8502 /* Check if operand is a register. */
4d1bb795 8503 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8504 {
40fb9820
L		 8505 i386_operand_type temp;
8506
24eab124
AM		 8507 /* Check for a segment override by searching for ':' after a
8508 segment register. */
8509 op_string = end_op;
8510 if (is_space_char (*op_string))
8511 ++op_string;
40fb9820
L		 8512 if (*op_string == ':'
8513 && (r->reg_type.bitfield.sreg2
8514 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8515 {
8516 switch (r->reg_num)
8517 {
8518 case 0:
8519 i.seg[i.mem_operands] = &es;
8520 break;
8521 case 1:
8522 i.seg[i.mem_operands] = &cs;
8523 break;
8524 case 2:
8525 i.seg[i.mem_operands] = &ss;
8526 break;
8527 case 3:
8528 i.seg[i.mem_operands] = &ds;
8529 break;
8530 case 4:
8531 i.seg[i.mem_operands] = &fs;
8532 break;
8533 case 5:
8534 i.seg[i.mem_operands] = &gs;
8535 break;
8536 }
252b5132 8537
24eab124 8538 /* Skip the ':' and whitespace. */
252b5132
RH		 8539 ++op_string;
8540 if (is_space_char (*op_string))
24eab124 8541 ++op_string;
252b5132 8542
24eab124
AM		 8543 if (!is_digit_char (*op_string)
8544 && !is_identifier_char (*op_string)
8545 && *op_string != '('
8546 && *op_string != ABSOLUTE_PREFIX)
8547 {
8548 as_bad (_("bad memory operand `%s'"), op_string);
8549 return 0;
8550 }
47926f60 8551 /* Handle case of %es:*foo. */
24eab124
AM		 8552 if (*op_string == ABSOLUTE_PREFIX)
8553 {
8554 ++op_string;
8555 if (is_space_char (*op_string))
8556 ++op_string;
40fb9820 8557 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8558 }
8559 goto do_memory_reference;
8560 }
43234a1e
L		 8561
8562 /* Handle vector operations. */
8563 if (*op_string == '{')
8564 {
8565 op_string = check_VecOperations (op_string, NULL);
8566 if (op_string == NULL)
8567 return 0;
8568 }
8569
24eab124
AM		 8570 if (*op_string)
8571 {
d0b47220 8572 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8573 return 0;
8574 }
40fb9820
L		 8575 temp = r->reg_type;
8576 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8577 i.types[this_operand] = operand_type_or (i.types[this_operand],
8578 temp);
7d5e4556 8579 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8580 i.op[this_operand].regs = r;
24eab124
AM		 8581 i.reg_operands++;
8582 }
af6bdddf
AM		 8583 else if (*op_string == REGISTER_PREFIX)
8584 {
8585 as_bad (_("bad register name `%s'"), op_string);
8586 return 0;
8587 }
24eab124 8588 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8589 {
24eab124 8590 ++op_string;
40fb9820 8591 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8592 {
d0b47220 8593 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8594 return 0;
8595 }
8596 if (!i386_immediate (op_string))
8597 return 0;
8598 }
43234a1e
L		 8599 else if (RC_SAE_immediate (operand_string))
8600 {
8601 /* If it is a RC or SAE immediate, do nothing. */
8602 ;
8603 }
24eab124
AM		 8604 else if (is_digit_char (*op_string)
8605 || is_identifier_char (*op_string)
e5cb08ac 8606 || *op_string == '(')
24eab124 8607 {
47926f60 8608 /* This is a memory reference of some sort. */
af6bdddf 8609 char *base_string;
252b5132 8610
47926f60 8611 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8612 char *displacement_string_start;
8613 char *displacement_string_end;
43234a1e 8614 char *vop_start;
252b5132 8615
24eab124 8616 do_memory_reference:
24eab124 8617 if ((i.mem_operands == 1
40fb9820 8618 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8619 || i.mem_operands == 2)
8620 {
8621 as_bad (_("too many memory references for `%s'"),
8622 current_templates->start->name);
8623 return 0;
8624 }
252b5132 8625
24eab124
AM		 8626 /* Check for base index form. We detect the base index form by
8627 looking for an ')' at the end of the operand, searching
8628 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8629 after the '('. */
af6bdddf 8630 base_string = op_string + strlen (op_string);
c3332e24 8631
43234a1e
L		 8632 /* Handle vector operations. */
8633 vop_start = strchr (op_string, '{');
8634 if (vop_start && vop_start < base_string)
8635 {
8636 if (check_VecOperations (vop_start, base_string) == NULL)
8637 return 0;
8638 base_string = vop_start;
8639 }
8640
af6bdddf
AM		 8641 --base_string;
8642 if (is_space_char (*base_string))
8643 --base_string;
252b5132 8644
47926f60 8645 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8646 displacement_string_start = op_string;
8647 displacement_string_end = base_string + 1;
252b5132 8648
24eab124
AM		 8649 if (*base_string == ')')
8650 {
af6bdddf 8651 char *temp_string;
24eab124
AM		 8652 unsigned int parens_balanced = 1;
8653 /* We've already checked that the number of left & right ()'s are
47926f60 8654 equal, so this loop will not be infinite. */
24eab124
AM		 8655 do
8656 {
8657 base_string--;
8658 if (*base_string == ')')
8659 parens_balanced++;
8660 if (*base_string == '(')
8661 parens_balanced--;
8662 }
8663 while (parens_balanced);
c3332e24 8664
af6bdddf 8665 temp_string = base_string;
c3332e24 8666
24eab124 8667 /* Skip past '(' and whitespace. */
252b5132
RH		 8668 ++base_string;
8669 if (is_space_char (*base_string))
24eab124 8670 ++base_string;
252b5132 8671
af6bdddf 8672 if (*base_string == ','
4eed87de
AM		 8673 || ((i.base_reg = parse_register (base_string, &end_op))
8674 != NULL))
252b5132 8675 {
af6bdddf 8676 displacement_string_end = temp_string;
252b5132 8677
40fb9820 8678 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8679
af6bdddf 8680 if (i.base_reg)
24eab124 8681 {
24eab124
AM		 8682 base_string = end_op;
8683 if (is_space_char (*base_string))
8684 ++base_string;
af6bdddf
AM		 8685 }
8686
8687 /* There may be an index reg or scale factor here. */
8688 if (*base_string == ',')
8689 {
8690 ++base_string;
8691 if (is_space_char (*base_string))
8692 ++base_string;
8693
4eed87de
AM		 8694 if ((i.index_reg = parse_register (base_string, &end_op))
8695 != NULL)
24eab124 8696 {
af6bdddf 8697 base_string = end_op;
24eab124
AM		 8698 if (is_space_char (*base_string))
8699 ++base_string;
af6bdddf
AM		 8700 if (*base_string == ',')
8701 {
8702 ++base_string;
8703 if (is_space_char (*base_string))
8704 ++base_string;
8705 }
e5cb08ac 8706 else if (*base_string != ')')
af6bdddf 8707 {
4eed87de
AM		 8708 as_bad (_("expecting `,' or `)' "
8709 "after index register in `%s'"),
af6bdddf
AM		 8710 operand_string);
8711 return 0;
8712 }
24eab124 8713 }
af6bdddf 8714 else if (*base_string == REGISTER_PREFIX)
24eab124 8715 {
f76bf5e0
L		 8716 end_op = strchr (base_string, ',');
8717 if (end_op)
8718 *end_op = '\0';
af6bdddf 8719 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8720 return 0;
8721 }
252b5132 8722
47926f60 8723 /* Check for scale factor. */
551c1ca1 8724 if (*base_string != ')')
af6bdddf 8725 {
551c1ca1
AM		 8726 char *end_scale = i386_scale (base_string);
8727
8728 if (!end_scale)
af6bdddf 8729 return 0;
24eab124 8730
551c1ca1 8731 base_string = end_scale;
af6bdddf
AM		 8732 if (is_space_char (*base_string))
8733 ++base_string;
8734 if (*base_string != ')')
8735 {
4eed87de
AM		 8736 as_bad (_("expecting `)' "
8737 "after scale factor in `%s'"),
af6bdddf
AM		 8738 operand_string);
8739 return 0;
8740 }
8741 }
8742 else if (!i.index_reg)
24eab124 8743 {
4eed87de
AM		 8744 as_bad (_("expecting index register or scale factor "
8745 "after `,'; got '%c'"),
af6bdddf 8746 *base_string);
24eab124
AM		 8747 return 0;
8748 }
8749 }
af6bdddf 8750 else if (*base_string != ')')
24eab124 8751 {
4eed87de
AM		 8752 as_bad (_("expecting `,' or `)' "
8753 "after base register in `%s'"),
af6bdddf 8754 operand_string);
24eab124
AM		 8755 return 0;
8756 }
c3332e24 8757 }
af6bdddf 8758 else if (*base_string == REGISTER_PREFIX)
c3332e24 8759 {
f76bf5e0
L		 8760 end_op = strchr (base_string, ',');
8761 if (end_op)
8762 *end_op = '\0';
af6bdddf 8763 as_bad (_("bad register name `%s'"), base_string);
24eab124 8764 return 0;
c3332e24 8765 }
24eab124
AM		 8766 }
8767
8768 /* If there's an expression beginning the operand, parse it,
8769 assuming displacement_string_start and
8770 displacement_string_end are meaningful. */
8771 if (displacement_string_start != displacement_string_end)
8772 {
8773 if (!i386_displacement (displacement_string_start,
8774 displacement_string_end))
8775 return 0;
8776 }
8777
8778 /* Special case for (%dx) while doing input/output op. */
8779 if (i.base_reg
0dfbf9d7
L		 8780 && operand_type_equal (&i.base_reg->reg_type,
8781 &reg16_inoutportreg)
24eab124
AM		 8782 && i.index_reg == 0
8783 && i.log2_scale_factor == 0
8784 && i.seg[i.mem_operands] == 0
40fb9820 8785 && !operand_type_check (i.types[this_operand], disp))
24eab124 8786 {
65da13b5 8787 i.types[this_operand] = inoutportreg;
24eab124
AM		 8788 return 1;
8789 }
8790
eecb386c
AM		 8791 if (i386_index_check (operand_string) == 0)
8792 return 0;
5c07affc 8793 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 8794 i.mem_operands++;
8795 }
8796 else
ce8a8b2f
AM		 8797 {
8798 /* It's not a memory operand; argh! */
24eab124
AM		 8799 as_bad (_("invalid char %s beginning operand %d `%s'"),
8800 output_invalid (*op_string),
8801 this_operand + 1,
8802 op_string);
8803 return 0;
8804 }
47926f60 8805 return 1; /* Normal return. */
252b5132
RH		 8806}
8807\f
fa94de6b
RM		 8808/* Calculate the maximum variable size (i.e., excluding fr_fix)
8809 that an rs_machine_dependent frag may reach. */
8810
8811unsigned int
8812i386_frag_max_var (fragS *frag)
8813{
8814 /* The only relaxable frags are for jumps.
8815 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8816 gas_assert (frag->fr_type == rs_machine_dependent);
8817 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8818}
8819
ee7fcc42
AM		 8820/* md_estimate_size_before_relax()
8821
8822 Called just before relax() for rs_machine_dependent frags. The x86
8823 assembler uses these frags to handle variable size jump
8824 instructions.
8825
8826 Any symbol that is now undefined will not become defined.
8827 Return the correct fr_subtype in the frag.
8828 Return the initial "guess for variable size of frag" to caller.
8829 The guess is actually the growth beyond the fixed part. Whatever
8830 we do to grow the fixed or variable part contributes to our
8831 returned value. */
8832
252b5132 8833int
7016a5d5 8834md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 8835{
252b5132 8836 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 8837 check for un-relaxable symbols. On an ELF system, we can't relax
8838 an externally visible symbol, because it may be overridden by a
8839 shared library. */
8840 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 8841#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8842 || (IS_ELF
31312f95 8843 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 8844 || S_IS_WEAK (fragP->fr_symbol)
8845 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
8846 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 8847#endif
8848#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 8849 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 8850 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 8851#endif
8852 )
252b5132 8853 {
b98ef147
AM		 8854 /* Symbol is undefined in this segment, or we need to keep a
8855 reloc so that weak symbols can be overridden. */
8856 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 8857 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 8858 unsigned char *opcode;
8859 int old_fr_fix;
f6af82bd 8860
ee7fcc42 8861 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 8862 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 8863 else if (size == 2)
f6af82bd
AM		 8864 reloc_type = BFD_RELOC_16_PCREL;
8865 else
8866 reloc_type = BFD_RELOC_32_PCREL;
252b5132 8867
ee7fcc42
AM		 8868 old_fr_fix = fragP->fr_fix;
8869 opcode = (unsigned char *) fragP->fr_opcode;
8870
fddf5b5b 8871 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 8872 {
fddf5b5b
AM		 8873 case UNCOND_JUMP:
8874 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 8875 opcode[0] = 0xe9;
252b5132 8876 fragP->fr_fix += size;
062cd5e7
AS		 8877 fix_new (fragP, old_fr_fix, size,
8878 fragP->fr_symbol,
8879 fragP->fr_offset, 1,
8880 reloc_type);
252b5132
RH		 8881 break;
8882
fddf5b5b 8883 case COND_JUMP86:
412167cb
AM		 8884 if (size == 2
8885 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 8886 {
8887 /* Negate the condition, and branch past an
8888 unconditional jump. */
8889 opcode[0] ^= 1;
8890 opcode[1] = 3;
8891 /* Insert an unconditional jump. */
8892 opcode[2] = 0xe9;
8893 /* We added two extra opcode bytes, and have a two byte
8894 offset. */
8895 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 8896 fix_new (fragP, old_fr_fix + 2, 2,
8897 fragP->fr_symbol,
8898 fragP->fr_offset, 1,
8899 reloc_type);
fddf5b5b
AM		 8900 break;
8901 }
8902 /* Fall through. */
8903
8904 case COND_JUMP:
412167cb
AM		 8905 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
8906 {
3e02c1cc
AM		 8907 fixS *fixP;
8908
412167cb 8909 fragP->fr_fix += 1;
3e02c1cc
AM		 8910 fixP = fix_new (fragP, old_fr_fix, 1,
8911 fragP->fr_symbol,
8912 fragP->fr_offset, 1,
8913 BFD_RELOC_8_PCREL);
8914 fixP->fx_signed = 1;
412167cb
AM		 8915 break;
8916 }
93c2a809 8917
24eab124 8918 /* This changes the byte-displacement jump 0x7N
fddf5b5b 8919 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 8920 opcode[1] = opcode[0] + 0x10;
f6af82bd 8921 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 8922 /* We've added an opcode byte. */
8923 fragP->fr_fix += 1 + size;
062cd5e7
AS		 8924 fix_new (fragP, old_fr_fix + 1, size,
8925 fragP->fr_symbol,
8926 fragP->fr_offset, 1,
8927 reloc_type);
252b5132 8928 break;
fddf5b5b
AM		 8929
8930 default:
8931 BAD_CASE (fragP->fr_subtype);
8932 break;
252b5132
RH		 8933 }
8934 frag_wane (fragP);
ee7fcc42 8935 return fragP->fr_fix - old_fr_fix;
252b5132 8936 }
93c2a809 8937
93c2a809
AM		 8938 /* Guess size depending on current relax state. Initially the relax
8939 state will correspond to a short jump and we return 1, because
8940 the variable part of the frag (the branch offset) is one byte
8941 long. However, we can relax a section more than once and in that
8942 case we must either set fr_subtype back to the unrelaxed state,
8943 or return the value for the appropriate branch. */
8944 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 8945}
8946
47926f60
KH		 8947/* Called after relax() is finished.
8948
8949 In: Address of frag.
8950 fr_type == rs_machine_dependent.
8951 fr_subtype is what the address relaxed to.
8952
8953 Out: Any fixSs and constants are set up.
8954 Caller will turn frag into a ".space 0". */
8955
252b5132 8956void
7016a5d5
TG		 8957md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
8958 fragS *fragP)
252b5132 8959{
29b0f896 8960 unsigned char *opcode;
252b5132 8961 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 8962 offsetT target_address;
8963 offsetT opcode_address;
252b5132 8964 unsigned int extension = 0;
847f7ad4 8965 offsetT displacement_from_opcode_start;
252b5132
RH		 8966
8967 opcode = (unsigned char *) fragP->fr_opcode;
8968
47926f60 8969 /* Address we want to reach in file space. */
252b5132 8970 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 8971
47926f60 8972 /* Address opcode resides at in file space. */
252b5132
RH		 8973 opcode_address = fragP->fr_address + fragP->fr_fix;
8974
47926f60 8975 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 8976 displacement_from_opcode_start = target_address - opcode_address;
8977
fddf5b5b 8978 if ((fragP->fr_subtype & BIG) == 0)
252b5132 8979 {
47926f60
KH		 8980 /* Don't have to change opcode. */
8981 extension = 1; /* 1 opcode + 1 displacement */
252b5132 8982 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 8983 }
8984 else
8985 {
8986 if (no_cond_jump_promotion
8987 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 8988 as_warn_where (fragP->fr_file, fragP->fr_line,
8989 _("long jump required"));
252b5132 8990
fddf5b5b
AM		 8991 switch (fragP->fr_subtype)
8992 {
8993 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
8994 extension = 4; /* 1 opcode + 4 displacement */
8995 opcode[0] = 0xe9;
8996 where_to_put_displacement = &opcode[1];
8997 break;
252b5132 8998
fddf5b5b
AM		 8999 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9000 extension = 2; /* 1 opcode + 2 displacement */
9001 opcode[0] = 0xe9;
9002 where_to_put_displacement = &opcode[1];
9003 break;
252b5132 9004
fddf5b5b
AM		 9005 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9006 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9007 extension = 5; /* 2 opcode + 4 displacement */
9008 opcode[1] = opcode[0] + 0x10;
9009 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9010 where_to_put_displacement = &opcode[2];
9011 break;
252b5132 9012
fddf5b5b
AM		 9013 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9014 extension = 3; /* 2 opcode + 2 displacement */
9015 opcode[1] = opcode[0] + 0x10;
9016 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9017 where_to_put_displacement = &opcode[2];
9018 break;
252b5132 9019
fddf5b5b
AM		 9020 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9021 extension = 4;
9022 opcode[0] ^= 1;
9023 opcode[1] = 3;
9024 opcode[2] = 0xe9;
9025 where_to_put_displacement = &opcode[3];
9026 break;
9027
9028 default:
9029 BAD_CASE (fragP->fr_subtype);
9030 break;
9031 }
252b5132 9032 }
fddf5b5b 9033
7b81dfbb
AJ		 9034 /* If size if less then four we are sure that the operand fits,
9035 but if it's 4, then it could be that the displacement is larger
9036 then -/+ 2GB. */
9037 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9038 && object_64bit
9039 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9040 + ((addressT) 1 << 31))
9041 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9042 {
9043 as_bad_where (fragP->fr_file, fragP->fr_line,
9044 _("jump target out of range"));
9045 /* Make us emit 0. */
9046 displacement_from_opcode_start = extension;
9047 }
47926f60 9048 /* Now put displacement after opcode. */
252b5132
RH		 9049 md_number_to_chars ((char *) where_to_put_displacement,
9050 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9051 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9052 fragP->fr_fix += extension;
9053}
9054\f
7016a5d5 9055/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9056 by our caller that we have all the info we need to fix it up.
9057
7016a5d5
TG		 9058 Parameter valP is the pointer to the value of the bits.
9059
252b5132
RH		 9060 On the 386, immediates, displacements, and data pointers are all in
9061 the same (little-endian) format, so we don't need to care about which
9062 we are handling. */
9063
94f592af 9064void
7016a5d5 9065md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9066{
94f592af 9067 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9068 valueT value = *valP;
252b5132 9069
f86103b7 9070#if !defined (TE_Mach)
93382f6d
AM		 9071 if (fixP->fx_pcrel)
9072 {
9073 switch (fixP->fx_r_type)
9074 {
5865bb77
ILT		 9075 default:
9076 break;
9077
d6ab8113
JB		 9078 case BFD_RELOC_64:
9079 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9080 break;
93382f6d 9081 case BFD_RELOC_32:
ae8887b5 9082 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9083 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9084 break;
9085 case BFD_RELOC_16:
9086 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9087 break;
9088 case BFD_RELOC_8:
9089 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9090 break;
9091 }
9092 }
252b5132 9093
a161fe53 9094 if (fixP->fx_addsy != NULL
31312f95 9095 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9096 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9097 || fixP->fx_r_type == BFD_RELOC_16_PCREL
c3320543
L		 9098 || fixP->fx_r_type == BFD_RELOC_8_PCREL
9099 || fixP->fx_r_type == BFD_RELOC_X86_64_PC32_BND)
31312f95 9100 && !use_rela_relocations)
252b5132 9101 {
31312f95
AM		 9102 /* This is a hack. There should be a better way to handle this.
9103 This covers for the fact that bfd_install_relocation will
9104 subtract the current location (for partial_inplace, PC relative
9105 relocations); see more below. */
252b5132 9106#ifndef OBJ_AOUT
718ddfc0 9107 if (IS_ELF
252b5132
RH		 9108#ifdef TE_PE
9109 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9110#endif
9111 )
9112 value += fixP->fx_where + fixP->fx_frag->fr_address;
9113#endif
9114#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9115 if (IS_ELF)
252b5132 9116 {
6539b54b 9117 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9118
6539b54b 9119 if ((sym_seg == seg
2f66722d 9120 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9121 && sym_seg != absolute_section))
af65af87 9122 && !generic_force_reloc (fixP))
2f66722d
AM		 9123 {
9124 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9125 bfd_install_relocation subtracts them out again. I think
9126 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9127 it. FIXME. */
9128 value += fixP->fx_where + fixP->fx_frag->fr_address;
9129 }
252b5132
RH		 9130 }
9131#endif
9132#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9133 /* For some reason, the PE format does not store a
9134 section address offset for a PC relative symbol. */
9135 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9136 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9137 value += md_pcrel_from (fixP);
9138#endif
9139 }
fbeb56a4
DK		 9140#if defined (OBJ_COFF) && defined (TE_PE)
9141 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9142 {
9143 value -= S_GET_VALUE (fixP->fx_addsy);
9144 }
9145#endif
252b5132
RH		 9146
9147 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9148 and we must not disappoint it. */
252b5132 9149#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9150 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9151 switch (fixP->fx_r_type)
9152 {
9153 case BFD_RELOC_386_PLT32:
3e73aa7c 9154 case BFD_RELOC_X86_64_PLT32:
c3320543 9155 case BFD_RELOC_X86_64_PLT32_BND:
47926f60
KH		 9156 /* Make the jump instruction point to the address of the operand. At
9157 runtime we merely add the offset to the actual PLT entry. */
9158 value = -4;
9159 break;
31312f95 9160
13ae64f3
JJ		 9161 case BFD_RELOC_386_TLS_GD:
9162 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9163 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9164 case BFD_RELOC_386_TLS_IE:
9165 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9166 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9167 case BFD_RELOC_X86_64_TLSGD:
9168 case BFD_RELOC_X86_64_TLSLD:
9169 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9170 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9171 value = 0; /* Fully resolved at runtime. No addend. */
9172 /* Fallthrough */
9173 case BFD_RELOC_386_TLS_LE:
9174 case BFD_RELOC_386_TLS_LDO_32:
9175 case BFD_RELOC_386_TLS_LE_32:
9176 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9177 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9178 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9179 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9180 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9181 break;
9182
67a4f2b7
AO		 9183 case BFD_RELOC_386_TLS_DESC_CALL:
9184 case BFD_RELOC_X86_64_TLSDESC_CALL:
9185 value = 0; /* Fully resolved at runtime. No addend. */
9186 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9187 fixP->fx_done = 0;
9188 return;
9189
00f7efb6
JJ		 9190 case BFD_RELOC_386_GOT32:
9191 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 9192 value = 0; /* Fully resolved at runtime. No addend. */
9193 break;
47926f60
KH		 9194
9195 case BFD_RELOC_VTABLE_INHERIT:
9196 case BFD_RELOC_VTABLE_ENTRY:
9197 fixP->fx_done = 0;
94f592af 9198 return;
47926f60
KH		 9199
9200 default:
9201 break;
9202 }
9203#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9204 *valP = value;
f86103b7 9205#endif /* !defined (TE_Mach) */
3e73aa7c 9206
3e73aa7c 9207 /* Are we finished with this relocation now? */
c6682705 9208 if (fixP->fx_addsy == NULL)
3e73aa7c 9209 fixP->fx_done = 1;
fbeb56a4
DK		 9210#if defined (OBJ_COFF) && defined (TE_PE)
9211 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9212 {
9213 fixP->fx_done = 0;
9214 /* Remember value for tc_gen_reloc. */
9215 fixP->fx_addnumber = value;
9216 /* Clear out the frag for now. */
9217 value = 0;
9218 }
9219#endif
3e73aa7c
JH		 9220 else if (use_rela_relocations)
9221 {
9222 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9223 /* Remember value for tc_gen_reloc. */
9224 fixP->fx_addnumber = value;
3e73aa7c
JH		 9225 value = 0;
9226 }
f86103b7 9227
94f592af 9228 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9229}
252b5132 9230\f
252b5132 9231char *
499ac353 9232md_atof (int type, char *litP, int *sizeP)
252b5132 9233{
499ac353
NC		 9234 /* This outputs the LITTLENUMs in REVERSE order;
9235 in accord with the bigendian 386. */
9236 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9237}
9238\f
2d545b82 9239static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9240
252b5132 9241static char *
e3bb37b5 9242output_invalid (int c)
252b5132 9243{
3882b010 9244 if (ISPRINT (c))
f9f21a03
L		 9245 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9246 "'%c'", c);
252b5132 9247 else
f9f21a03 9248 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9249 "(0x%x)", (unsigned char) c);
252b5132
RH		 9250 return output_invalid_buf;
9251}
9252
af6bdddf 9253/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9254
9255static const reg_entry *
4d1bb795 9256parse_real_register (char *reg_string, char **end_op)
252b5132 9257{
af6bdddf
AM		 9258 char *s = reg_string;
9259 char *p;
252b5132
RH		 9260 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9261 const reg_entry *r;
9262
9263 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9264 if (*s == REGISTER_PREFIX)
9265 ++s;
9266
9267 if (is_space_char (*s))
9268 ++s;
9269
9270 p = reg_name_given;
af6bdddf 9271 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9272 {
9273 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9274 return (const reg_entry *) NULL;
9275 s++;
252b5132
RH		 9276 }
9277
6588847e
DN		 9278 /* For naked regs, make sure that we are not dealing with an identifier.
9279 This prevents confusing an identifier like `eax_var' with register
9280 `eax'. */
9281 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9282 return (const reg_entry *) NULL;
9283
af6bdddf 9284 *end_op = s;
252b5132
RH		 9285
9286 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9287
5f47d35b 9288 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9289 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9290 {
5f47d35b
AM		 9291 if (is_space_char (*s))
9292 ++s;
9293 if (*s == '(')
9294 {
af6bdddf 9295 ++s;
5f47d35b
AM		 9296 if (is_space_char (*s))
9297 ++s;
9298 if (*s >= '0' && *s <= '7')
9299 {
db557034 9300 int fpr = *s - '0';
af6bdddf 9301 ++s;
5f47d35b
AM		 9302 if (is_space_char (*s))
9303 ++s;
9304 if (*s == ')')
9305 {
9306 *end_op = s + 1;
1e9cc1c2 9307 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9308 know (r);
9309 return r + fpr;
5f47d35b 9310 }
5f47d35b 9311 }
47926f60 9312 /* We have "%st(" then garbage. */
5f47d35b
AM		 9313 return (const reg_entry *) NULL;
9314 }
9315 }
9316
a60de03c
JB		 9317 if (r == NULL || allow_pseudo_reg)
9318 return r;
9319
0dfbf9d7 9320 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9321 return (const reg_entry *) NULL;
9322
192dc9c6
JB		 9323 if ((r->reg_type.bitfield.reg32
9324 || r->reg_type.bitfield.sreg3
9325 || r->reg_type.bitfield.control
9326 || r->reg_type.bitfield.debug
9327 || r->reg_type.bitfield.test)
9328 && !cpu_arch_flags.bitfield.cpui386)
9329 return (const reg_entry *) NULL;
9330
309d3373
JB		 9331 if (r->reg_type.bitfield.floatreg
9332 && !cpu_arch_flags.bitfield.cpu8087
9333 && !cpu_arch_flags.bitfield.cpu287
9334 && !cpu_arch_flags.bitfield.cpu387)
9335 return (const reg_entry *) NULL;
9336
192dc9c6
JB		 9337 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9338 return (const reg_entry *) NULL;
9339
9340 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9341 return (const reg_entry *) NULL;
9342
40f12533
L		 9343 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9344 return (const reg_entry *) NULL;
9345
43234a1e
L		 9346 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9347 && !cpu_arch_flags.bitfield.cpuavx512f)
9348 return (const reg_entry *) NULL;
9349
db51cc60 9350 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9351 if (!allow_index_reg
db51cc60
L		 9352 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9353 return (const reg_entry *) NULL;
9354
43234a1e
L		 9355 /* Upper 16 vector register is only available with VREX in 64bit
9356 mode. */
9357 if ((r->reg_flags & RegVRex))
9358 {
9359 if (!cpu_arch_flags.bitfield.cpuvrex
9360 || flag_code != CODE_64BIT)
9361 return (const reg_entry *) NULL;
9362
9363 i.need_vrex = 1;
9364 }
9365
a60de03c
JB		 9366 if (((r->reg_flags & (RegRex64 | RegRex))
9367 || r->reg_type.bitfield.reg64)
40fb9820 9368 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9369 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9370 && flag_code != CODE_64BIT)
20f0a1fc 9371 return (const reg_entry *) NULL;
1ae00879 9372
b7240065
JB		 9373 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9374 return (const reg_entry *) NULL;
9375
252b5132
RH		 9376 return r;
9377}
4d1bb795
JB		 9378
9379/* REG_STRING starts *before* REGISTER_PREFIX. */
9380
9381static const reg_entry *
9382parse_register (char *reg_string, char **end_op)
9383{
9384 const reg_entry *r;
9385
9386 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9387 r = parse_real_register (reg_string, end_op);
9388 else
9389 r = NULL;
9390 if (!r)
9391 {
9392 char *save = input_line_pointer;
9393 char c;
9394 symbolS *symbolP;
9395
9396 input_line_pointer = reg_string;
9397 c = get_symbol_end ();
9398 symbolP = symbol_find (reg_string);
9399 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9400 {
9401 const expressionS *e = symbol_get_value_expression (symbolP);
9402
0398aac5 9403 know (e->X_op == O_register);
4eed87de 9404 know (e->X_add_number >= 0
c3fe08fa 9405 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 9406 r = i386_regtab + e->X_add_number;
9407 *end_op = input_line_pointer;
9408 }
9409 *input_line_pointer = c;
9410 input_line_pointer = save;
9411 }
9412 return r;
9413}
9414
9415int
9416i386_parse_name (char *name, expressionS *e, char *nextcharP)
9417{
9418 const reg_entry *r;
9419 char *end = input_line_pointer;
9420
9421 *end = *nextcharP;
9422 r = parse_register (name, &input_line_pointer);
9423 if (r && end <= input_line_pointer)
9424 {
9425 *nextcharP = *input_line_pointer;
9426 *input_line_pointer = 0;
9427 e->X_op = O_register;
9428 e->X_add_number = r - i386_regtab;
9429 return 1;
9430 }
9431 input_line_pointer = end;
9432 *end = 0;
ee86248c 9433 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9434}
9435
9436void
9437md_operand (expressionS *e)
9438{
ee86248c
JB		 9439 char *end;
9440 const reg_entry *r;
4d1bb795 9441
ee86248c
JB		 9442 switch (*input_line_pointer)
9443 {
9444 case REGISTER_PREFIX:
9445 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9446 if (r)
9447 {
9448 e->X_op = O_register;
9449 e->X_add_number = r - i386_regtab;
9450 input_line_pointer = end;
9451 }
ee86248c
JB		 9452 break;
9453
9454 case '[':
9c2799c2 9455 gas_assert (intel_syntax);
ee86248c
JB		 9456 end = input_line_pointer++;
9457 expression (e);
9458 if (*input_line_pointer == ']')
9459 {
9460 ++input_line_pointer;
9461 e->X_op_symbol = make_expr_symbol (e);
9462 e->X_add_symbol = NULL;
9463 e->X_add_number = 0;
9464 e->X_op = O_index;
9465 }
9466 else
9467 {
9468 e->X_op = O_absent;
9469 input_line_pointer = end;
9470 }
9471 break;
4d1bb795
JB		 9472 }
9473}
9474
252b5132 9475\f
4cc782b5 9476#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9477const char *md_shortopts = "kVQ:sqn";
252b5132 9478#else
12b55ccc 9479const char *md_shortopts = "qn";
252b5132 9480#endif
6e0b89ee 9481
3e73aa7c 9482#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9483#define OPTION_64 (OPTION_MD_BASE + 1)
9484#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9485#define OPTION_MARCH (OPTION_MD_BASE + 3)
9486#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9487#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9488#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9489#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9490#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9491#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9492#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9493#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9494#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9495#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9496#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9497#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9498#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9499#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
b3b91714 9500
99ad8390
NC		 9501struct option md_longopts[] =
9502{
3e73aa7c 9503 {"32", no_argument, NULL, OPTION_32},
321098a5 9504#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9505 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9506 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9507#endif
9508#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9509 {"x32", no_argument, NULL, OPTION_X32},
6e0b89ee 9510#endif
b3b91714 9511 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9512 {"march", required_argument, NULL, OPTION_MARCH},
9513 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9514 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9515 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9516 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9517 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9518 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9519 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9520 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9521 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9522 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9523 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9524 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9525 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
252b5132
RH		 9526 {NULL, no_argument, NULL, 0}
9527};
9528size_t md_longopts_size = sizeof (md_longopts);
9529
9530int
9103f4f4 9531md_parse_option (int c, char *arg)
252b5132 9532{
91d6fa6a 9533 unsigned int j;
6305a203 9534 char *arch, *next;
9103f4f4 9535
252b5132
RH		 9536 switch (c)
9537 {
12b55ccc
L		 9538 case 'n':
9539 optimize_align_code = 0;
9540 break;
9541
a38cf1db
AM		 9542 case 'q':
9543 quiet_warnings = 1;
252b5132
RH		 9544 break;
9545
9546#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9547 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9548 should be emitted or not. FIXME: Not implemented. */
9549 case 'Q':
252b5132
RH		 9550 break;
9551
9552 /* -V: SVR4 argument to print version ID. */
9553 case 'V':
9554 print_version_id ();
9555 break;
9556
a38cf1db
AM		 9557 /* -k: Ignore for FreeBSD compatibility. */
9558 case 'k':
252b5132 9559 break;
4cc782b5
ILT		 9560
9561 case 's':
9562 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9563 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9564 break;
99ad8390 9565#endif
321098a5 9566#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9567 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9568 case OPTION_64:
9569 {
9570 const char **list, **l;
9571
3e73aa7c
JH		 9572 list = bfd_target_list ();
9573 for (l = list; *l != NULL; l++)
8620418b 9574 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9575 || strcmp (*l, "coff-x86-64") == 0
9576 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9577 || strcmp (*l, "pei-x86-64") == 0
9578 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9579 {
9580 default_arch = "x86_64";
9581 break;
9582 }
3e73aa7c 9583 if (*l == NULL)
2b5d6a91 9584 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9585 free (list);
9586 }
9587 break;
9588#endif
252b5132 9589
351f65ca 9590#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9591 case OPTION_X32:
351f65ca
L		 9592 if (IS_ELF)
9593 {
9594 const char **list, **l;
9595
9596 list = bfd_target_list ();
9597 for (l = list; *l != NULL; l++)
9598 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9599 {
9600 default_arch = "x86_64:32";
9601 break;
9602 }
9603 if (*l == NULL)
2b5d6a91 9604 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9605 free (list);
9606 }
9607 else
9608 as_fatal (_("32bit x86_64 is only supported for ELF"));
9609 break;
9610#endif
9611
6e0b89ee
AM		 9612 case OPTION_32:
9613 default_arch = "i386";
9614 break;
9615
b3b91714
AM		 9616 case OPTION_DIVIDE:
9617#ifdef SVR4_COMMENT_CHARS
9618 {
9619 char *n, *t;
9620 const char *s;
9621
9622 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
9623 t = n;
9624 for (s = i386_comment_chars; *s != '\0'; s++)
9625 if (*s != '/')
9626 *t++ = *s;
9627 *t = '\0';
9628 i386_comment_chars = n;
9629 }
9630#endif
9631 break;
9632
9103f4f4 9633 case OPTION_MARCH:
6305a203
L		 9634 arch = xstrdup (arg);
9635 do
9103f4f4 9636 {
6305a203 9637 if (*arch == '.')
2b5d6a91 9638 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9639 next = strchr (arch, '+');
9640 if (next)
9641 *next++ = '\0';
91d6fa6a 9642 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9643 {
91d6fa6a 9644 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9645 {
6305a203 9646 /* Processor. */
1ded5609
JB		 9647 if (! cpu_arch[j].flags.bitfield.cpui386)
9648 continue;
9649
91d6fa6a 9650 cpu_arch_name = cpu_arch[j].name;
6305a203 9651 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9652 cpu_arch_flags = cpu_arch[j].flags;
9653 cpu_arch_isa = cpu_arch[j].type;
9654 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9655 if (!cpu_arch_tune_set)
9656 {
9657 cpu_arch_tune = cpu_arch_isa;
9658 cpu_arch_tune_flags = cpu_arch_isa_flags;
9659 }
9660 break;
9661 }
91d6fa6a
NC		 9662 else if (*cpu_arch [j].name == '.'
9663 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9664 {
9665 /* ISA entension. */
9666 i386_cpu_flags flags;
309d3373 9667
49021df2 9668 if (!cpu_arch[j].negated)
309d3373 9669 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 9670 cpu_arch[j].flags);
309d3373
JB		 9671 else
9672 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 9673 cpu_arch[j].flags);
0dfbf9d7 9674 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 9675 {
9676 if (cpu_sub_arch_name)
9677 {
9678 char *name = cpu_sub_arch_name;
9679 cpu_sub_arch_name = concat (name,
91d6fa6a 9680 cpu_arch[j].name,
1bf57e9f 9681 (const char *) NULL);
6305a203
L		 9682 free (name);
9683 }
9684 else
91d6fa6a 9685 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 9686 cpu_arch_flags = flags;
a586129e 9687 cpu_arch_isa_flags = flags;
6305a203
L		 9688 }
9689 break;
ccc9c027 9690 }
9103f4f4 9691 }
6305a203 9692
91d6fa6a 9693 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9694 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9695
9696 arch = next;
9103f4f4 9697 }
6305a203 9698 while (next != NULL );
9103f4f4
L		 9699 break;
9700
9701 case OPTION_MTUNE:
9702 if (*arg == '.')
2b5d6a91 9703 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 9704 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9705 {
91d6fa6a 9706 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 9707 {
ccc9c027 9708 cpu_arch_tune_set = 1;
91d6fa6a
NC		 9709 cpu_arch_tune = cpu_arch [j].type;
9710 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 9711 break;
9712 }
9713 }
91d6fa6a 9714 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9715 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 9716 break;
9717
1efbbeb4
L		 9718 case OPTION_MMNEMONIC:
9719 if (strcasecmp (arg, "att") == 0)
9720 intel_mnemonic = 0;
9721 else if (strcasecmp (arg, "intel") == 0)
9722 intel_mnemonic = 1;
9723 else
2b5d6a91 9724 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 9725 break;
9726
9727 case OPTION_MSYNTAX:
9728 if (strcasecmp (arg, "att") == 0)
9729 intel_syntax = 0;
9730 else if (strcasecmp (arg, "intel") == 0)
9731 intel_syntax = 1;
9732 else
2b5d6a91 9733 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 9734 break;
9735
9736 case OPTION_MINDEX_REG:
9737 allow_index_reg = 1;
9738 break;
9739
9740 case OPTION_MNAKED_REG:
9741 allow_naked_reg = 1;
9742 break;
9743
9744 case OPTION_MOLD_GCC:
9745 old_gcc = 1;
1efbbeb4
L		 9746 break;
9747
c0f3af97
L		 9748 case OPTION_MSSE2AVX:
9749 sse2avx = 1;
9750 break;
9751
daf50ae7
L		 9752 case OPTION_MSSE_CHECK:
9753 if (strcasecmp (arg, "error") == 0)
7bab8ab5 9754 sse_check = check_error;
daf50ae7 9755 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 9756 sse_check = check_warning;
daf50ae7 9757 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 9758 sse_check = check_none;
daf50ae7 9759 else
2b5d6a91 9760 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 9761 break;
9762
7bab8ab5
JB		 9763 case OPTION_MOPERAND_CHECK:
9764 if (strcasecmp (arg, "error") == 0)
9765 operand_check = check_error;
9766 else if (strcasecmp (arg, "warning") == 0)
9767 operand_check = check_warning;
9768 else if (strcasecmp (arg, "none") == 0)
9769 operand_check = check_none;
9770 else
9771 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
9772 break;
9773
539f890d
L		 9774 case OPTION_MAVXSCALAR:
9775 if (strcasecmp (arg, "128") == 0)
9776 avxscalar = vex128;
9777 else if (strcasecmp (arg, "256") == 0)
9778 avxscalar = vex256;
9779 else
2b5d6a91 9780 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 9781 break;
9782
7e8b059b
L		 9783 case OPTION_MADD_BND_PREFIX:
9784 add_bnd_prefix = 1;
9785 break;
9786
43234a1e
L		 9787 case OPTION_MEVEXLIG:
9788 if (strcmp (arg, "128") == 0)
9789 evexlig = evexl128;
9790 else if (strcmp (arg, "256") == 0)
9791 evexlig = evexl256;
9792 else if (strcmp (arg, "512") == 0)
9793 evexlig = evexl512;
9794 else
9795 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
9796 break;
9797
9798 case OPTION_MEVEXWIG:
9799 if (strcmp (arg, "0") == 0)
9800 evexwig = evexw0;
9801 else if (strcmp (arg, "1") == 0)
9802 evexwig = evexw1;
9803 else
9804 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
9805 break;
9806
252b5132
RH		 9807 default:
9808 return 0;
9809 }
9810 return 1;
9811}
9812
8a2c8fef
L		 9813#define MESSAGE_TEMPLATE \
9814" "
9815
9816static void
1ded5609 9817show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 9818{
9819 static char message[] = MESSAGE_TEMPLATE;
9820 char *start = message + 27;
9821 char *p;
9822 int size = sizeof (MESSAGE_TEMPLATE);
9823 int left;
9824 const char *name;
9825 int len;
9826 unsigned int j;
9827
9828 p = start;
9829 left = size - (start - message);
9830 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9831 {
9832 /* Should it be skipped? */
9833 if (cpu_arch [j].skip)
9834 continue;
9835
9836 name = cpu_arch [j].name;
9837 len = cpu_arch [j].len;
9838 if (*name == '.')
9839 {
9840 /* It is an extension. Skip if we aren't asked to show it. */
9841 if (ext)
9842 {
9843 name++;
9844 len--;
9845 }
9846 else
9847 continue;
9848 }
9849 else if (ext)
9850 {
9851 /* It is an processor. Skip if we show only extension. */
9852 continue;
9853 }
1ded5609
JB		 9854 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
9855 {
9856 /* It is an impossible processor - skip. */
9857 continue;
9858 }
8a2c8fef
L		 9859
9860 /* Reserve 2 spaces for ", " or ",\0" */
9861 left -= len + 2;
9862
9863 /* Check if there is any room. */
9864 if (left >= 0)
9865 {
9866 if (p != start)
9867 {
9868 *p++ = ',';
9869 *p++ = ' ';
9870 }
9871 p = mempcpy (p, name, len);
9872 }
9873 else
9874 {
9875 /* Output the current message now and start a new one. */
9876 *p++ = ',';
9877 *p = '\0';
9878 fprintf (stream, "%s\n", message);
9879 p = start;
9880 left = size - (start - message) - len - 2;
8d63c93e 9881
8a2c8fef
L		 9882 gas_assert (left >= 0);
9883
9884 p = mempcpy (p, name, len);
9885 }
9886 }
9887
9888 *p = '\0';
9889 fprintf (stream, "%s\n", message);
9890}
9891
252b5132 9892void
8a2c8fef 9893md_show_usage (FILE *stream)
252b5132 9894{
4cc782b5
ILT		 9895#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9896 fprintf (stream, _("\
a38cf1db
AM		 9897 -Q ignored\n\
9898 -V print assembler version number\n\
b3b91714
AM		 9899 -k ignored\n"));
9900#endif
9901 fprintf (stream, _("\
12b55ccc 9902 -n Do not optimize code alignment\n\
b3b91714
AM		 9903 -q quieten some warnings\n"));
9904#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9905 fprintf (stream, _("\
a38cf1db 9906 -s ignored\n"));
b3b91714 9907#endif
321098a5
L		 9908#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9909 || defined (TE_PE) || defined (TE_PEP))
751d281c 9910 fprintf (stream, _("\
570561f7 9911 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 9912#endif
b3b91714
AM		 9913#ifdef SVR4_COMMENT_CHARS
9914 fprintf (stream, _("\
9915 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 9916#else
9917 fprintf (stream, _("\
b3b91714 9918 --divide ignored\n"));
4cc782b5 9919#endif
9103f4f4 9920 fprintf (stream, _("\
6305a203 9921 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 9922 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 9923 show_arch (stream, 0, 1);
8a2c8fef
L		 9924 fprintf (stream, _("\
9925 EXTENSION is combination of:\n"));
1ded5609 9926 show_arch (stream, 1, 0);
6305a203 9927 fprintf (stream, _("\
8a2c8fef 9928 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 9929 show_arch (stream, 0, 0);
ba104c83 9930 fprintf (stream, _("\
c0f3af97
L		 9931 -msse2avx encode SSE instructions with VEX prefix\n"));
9932 fprintf (stream, _("\
daf50ae7
L		 9933 -msse-check=[none|error|warning]\n\
9934 check SSE instructions\n"));
9935 fprintf (stream, _("\
7bab8ab5
JB		 9936 -moperand-check=[none|error|warning]\n\
9937 check operand combinations for validity\n"));
9938 fprintf (stream, _("\
539f890d
L		 9939 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
9940 length\n"));
9941 fprintf (stream, _("\
43234a1e
L		 9942 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
9943 length\n"));
9944 fprintf (stream, _("\
9945 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
9946 for EVEX.W bit ignored instructions\n"));
9947 fprintf (stream, _("\
ba104c83
L		 9948 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
9949 fprintf (stream, _("\
9950 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
9951 fprintf (stream, _("\
9952 -mindex-reg support pseudo index registers\n"));
9953 fprintf (stream, _("\
9954 -mnaked-reg don't require `%%' prefix for registers\n"));
9955 fprintf (stream, _("\
9956 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 9957 fprintf (stream, _("\
9958 -madd-bnd-prefix add BND prefix for all valid branches\n"));
252b5132
RH		 9959}
9960
3e73aa7c 9961#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 9962 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 9963 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 9964
9965/* Pick the target format to use. */
9966
47926f60 9967const char *
e3bb37b5 9968i386_target_format (void)
252b5132 9969{
351f65ca
L		 9970 if (!strncmp (default_arch, "x86_64", 6))
9971 {
9972 update_code_flag (CODE_64BIT, 1);
9973 if (default_arch[6] == '\0')
7f56bc95 9974 x86_elf_abi = X86_64_ABI;
351f65ca 9975 else
7f56bc95 9976 x86_elf_abi = X86_64_X32_ABI;
351f65ca 9977 }
3e73aa7c 9978 else if (!strcmp (default_arch, "i386"))
78f12dd3 9979 update_code_flag (CODE_32BIT, 1);
3e73aa7c 9980 else
2b5d6a91 9981 as_fatal (_("unknown architecture"));
89507696
JB		 9982
9983 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
9984 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
9985 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
9986 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
9987
252b5132
RH		 9988 switch (OUTPUT_FLAVOR)
9989 {
9384f2ff 9990#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 9991 case bfd_target_aout_flavour:
47926f60 9992 return AOUT_TARGET_FORMAT;
4c63da97 9993#endif
9384f2ff
AM		 9994#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
9995# if defined (TE_PE) || defined (TE_PEP)
9996 case bfd_target_coff_flavour:
9997 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
9998# elif defined (TE_GO32)
0561d57c
JK		 9999 case bfd_target_coff_flavour:
10000 return "coff-go32";
9384f2ff 10001# else
252b5132
RH		 10002 case bfd_target_coff_flavour:
10003 return "coff-i386";
9384f2ff 10004# endif
4c63da97 10005#endif
3e73aa7c 10006#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10007 case bfd_target_elf_flavour:
3e73aa7c 10008 {
351f65ca
L		 10009 const char *format;
10010
10011 switch (x86_elf_abi)
4fa24527 10012 {
351f65ca
L		 10013 default:
10014 format = ELF_TARGET_FORMAT;
10015 break;
7f56bc95 10016 case X86_64_ABI:
351f65ca 10017 use_rela_relocations = 1;
4fa24527 10018 object_64bit = 1;
351f65ca
L		 10019 format = ELF_TARGET_FORMAT64;
10020 break;
7f56bc95 10021 case X86_64_X32_ABI:
4fa24527 10022 use_rela_relocations = 1;
351f65ca 10023 object_64bit = 1;
862be3fb 10024 disallow_64bit_reloc = 1;
351f65ca
L		 10025 format = ELF_TARGET_FORMAT32;
10026 break;
4fa24527 10027 }
3632d14b 10028 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10029 {
7f56bc95 10030 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10031 as_fatal (_("Intel L1OM is 64bit only"));
10032 return ELF_TARGET_L1OM_FORMAT;
10033 }
7a9068fe
L		 10034 if (cpu_arch_isa == PROCESSOR_K1OM)
10035 {
10036 if (x86_elf_abi != X86_64_ABI)
10037 as_fatal (_("Intel K1OM is 64bit only"));
10038 return ELF_TARGET_K1OM_FORMAT;
10039 }
8a9036a4 10040 else
351f65ca 10041 return format;
3e73aa7c 10042 }
e57f8c65
TG		 10043#endif
10044#if defined (OBJ_MACH_O)
10045 case bfd_target_mach_o_flavour:
d382c579
TG		 10046 if (flag_code == CODE_64BIT)
10047 {
10048 use_rela_relocations = 1;
10049 object_64bit = 1;
10050 return "mach-o-x86-64";
10051 }
10052 else
10053 return "mach-o-i386";
4c63da97 10054#endif
252b5132
RH		 10055 default:
10056 abort ();
10057 return NULL;
10058 }
10059}
10060
47926f60 10061#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 10062
10063#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 10064void
10065i386_elf_emit_arch_note (void)
a847613f 10066{
718ddfc0 10067 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 10068 {
10069 char *p;
10070 asection *seg = now_seg;
10071 subsegT subseg = now_subseg;
10072 Elf_Internal_Note i_note;
10073 Elf_External_Note e_note;
10074 asection *note_secp;
10075 int len;
10076
10077 /* Create the .note section. */
10078 note_secp = subseg_new (".note", 0);
10079 bfd_set_section_flags (stdoutput,
10080 note_secp,
10081 SEC_HAS_CONTENTS | SEC_READONLY);
10082
10083 /* Process the arch string. */
10084 len = strlen (cpu_arch_name);
10085
10086 i_note.namesz = len + 1;
10087 i_note.descsz = 0;
10088 i_note.type = NT_ARCH;
10089 p = frag_more (sizeof (e_note.namesz));
10090 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
10091 p = frag_more (sizeof (e_note.descsz));
10092 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
10093 p = frag_more (sizeof (e_note.type));
10094 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
10095 p = frag_more (len + 1);
10096 strcpy (p, cpu_arch_name);
10097
10098 frag_align (2, 0, 0);
10099
10100 subseg_set (seg, subseg);
10101 }
10102}
10103#endif
252b5132 10104\f
252b5132 10105symbolS *
7016a5d5 10106md_undefined_symbol (char *name)
252b5132 10107{
18dc2407
ILT		 10108 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10109 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10110 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10111 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10112 {
10113 if (!GOT_symbol)
10114 {
10115 if (symbol_find (name))
10116 as_bad (_("GOT already in symbol table"));
10117 GOT_symbol = symbol_new (name, undefined_section,
10118 (valueT) 0, &zero_address_frag);
10119 };
10120 return GOT_symbol;
10121 }
252b5132
RH		 10122 return 0;
10123}
10124
10125/* Round up a section size to the appropriate boundary. */
47926f60 10126
252b5132 10127valueT
7016a5d5 10128md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10129{
4c63da97
AM		 10130#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10131 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10132 {
10133 /* For a.out, force the section size to be aligned. If we don't do
10134 this, BFD will align it for us, but it will not write out the
10135 final bytes of the section. This may be a bug in BFD, but it is
10136 easier to fix it here since that is how the other a.out targets
10137 work. */
10138 int align;
10139
10140 align = bfd_get_section_alignment (stdoutput, segment);
10141 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
10142 }
252b5132
RH		 10143#endif
10144
10145 return size;
10146}
10147
10148/* On the i386, PC-relative offsets are relative to the start of the
10149 next instruction. That is, the address of the offset, plus its
10150 size, since the offset is always the last part of the insn. */
10151
10152long
e3bb37b5 10153md_pcrel_from (fixS *fixP)
252b5132
RH		 10154{
10155 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10156}
10157
10158#ifndef I386COFF
10159
10160static void
e3bb37b5 10161s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10162{
29b0f896 10163 int temp;
252b5132 10164
8a75718c
JB		 10165#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10166 if (IS_ELF)
10167 obj_elf_section_change_hook ();
10168#endif
252b5132
RH		 10169 temp = get_absolute_expression ();
10170 subseg_set (bss_section, (subsegT) temp);
10171 demand_empty_rest_of_line ();
10172}
10173
10174#endif
10175
252b5132 10176void
e3bb37b5 10177i386_validate_fix (fixS *fixp)
252b5132
RH		 10178{
10179 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
10180 {
23df1078
JH		 10181 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10182 {
4fa24527 10183 if (!object_64bit)
23df1078
JH		 10184 abort ();
10185 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10186 }
10187 else
10188 {
4fa24527 10189 if (!object_64bit)
d6ab8113
JB		 10190 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10191 else
10192 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 10193 }
252b5132
RH		 10194 fixp->fx_subsy = 0;
10195 }
10196}
10197
252b5132 10198arelent *
7016a5d5 10199tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10200{
10201 arelent *rel;
10202 bfd_reloc_code_real_type code;
10203
10204 switch (fixp->fx_r_type)
10205 {
8ce3d284 10206#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10207 case BFD_RELOC_SIZE32:
10208 case BFD_RELOC_SIZE64:
10209 if (S_IS_DEFINED (fixp->fx_addsy)
10210 && !S_IS_EXTERNAL (fixp->fx_addsy))
10211 {
10212 /* Resolve size relocation against local symbol to size of
10213 the symbol plus addend. */
10214 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10215 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10216 && !fits_in_unsigned_long (value))
10217 as_bad_where (fixp->fx_file, fixp->fx_line,
10218 _("symbol size computation overflow"));
10219 fixp->fx_addsy = NULL;
10220 fixp->fx_subsy = NULL;
10221 md_apply_fix (fixp, (valueT *) &value, NULL);
10222 return NULL;
10223 }
8ce3d284 10224#endif
8fd4256d 10225
3e73aa7c 10226 case BFD_RELOC_X86_64_PLT32:
c3320543 10227 case BFD_RELOC_X86_64_PLT32_BND:
3e73aa7c
JH		 10228 case BFD_RELOC_X86_64_GOT32:
10229 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 10230 case BFD_RELOC_386_PLT32:
10231 case BFD_RELOC_386_GOT32:
10232 case BFD_RELOC_386_GOTOFF:
10233 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10234 case BFD_RELOC_386_TLS_GD:
10235 case BFD_RELOC_386_TLS_LDM:
10236 case BFD_RELOC_386_TLS_LDO_32:
10237 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10238 case BFD_RELOC_386_TLS_IE:
10239 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10240 case BFD_RELOC_386_TLS_LE_32:
10241 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10242 case BFD_RELOC_386_TLS_GOTDESC:
10243 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10244 case BFD_RELOC_X86_64_TLSGD:
10245 case BFD_RELOC_X86_64_TLSLD:
10246 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10247 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10248 case BFD_RELOC_X86_64_GOTTPOFF:
10249 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10250 case BFD_RELOC_X86_64_TPOFF64:
10251 case BFD_RELOC_X86_64_GOTOFF64:
10252 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10253 case BFD_RELOC_X86_64_GOT64:
10254 case BFD_RELOC_X86_64_GOTPCREL64:
10255 case BFD_RELOC_X86_64_GOTPC64:
10256 case BFD_RELOC_X86_64_GOTPLT64:
10257 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10258 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10259 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10260 case BFD_RELOC_RVA:
10261 case BFD_RELOC_VTABLE_ENTRY:
10262 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10263#ifdef TE_PE
10264 case BFD_RELOC_32_SECREL:
10265#endif
252b5132
RH		 10266 code = fixp->fx_r_type;
10267 break;
dbbaec26
L		 10268 case BFD_RELOC_X86_64_32S:
10269 if (!fixp->fx_pcrel)
10270 {
10271 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10272 code = fixp->fx_r_type;
10273 break;
10274 }
252b5132 10275 default:
93382f6d 10276 if (fixp->fx_pcrel)
252b5132 10277 {
93382f6d
AM		 10278 switch (fixp->fx_size)
10279 {
10280 default:
b091f402
AM		 10281 as_bad_where (fixp->fx_file, fixp->fx_line,
10282 _("can not do %d byte pc-relative relocation"),
10283 fixp->fx_size);
93382f6d
AM		 10284 code = BFD_RELOC_32_PCREL;
10285 break;
10286 case 1: code = BFD_RELOC_8_PCREL; break;
10287 case 2: code = BFD_RELOC_16_PCREL; break;
c3320543
L		 10288 case 4:
10289 code = (fixp->fx_r_type == BFD_RELOC_X86_64_PC32_BND
10290 ? fixp-> fx_r_type : BFD_RELOC_32_PCREL);
10291 break;
d6ab8113
JB		 10292#ifdef BFD64
10293 case 8: code = BFD_RELOC_64_PCREL; break;
10294#endif
93382f6d
AM		 10295 }
10296 }
10297 else
10298 {
10299 switch (fixp->fx_size)
10300 {
10301 default:
b091f402
AM		 10302 as_bad_where (fixp->fx_file, fixp->fx_line,
10303 _("can not do %d byte relocation"),
10304 fixp->fx_size);
93382f6d
AM		 10305 code = BFD_RELOC_32;
10306 break;
10307 case 1: code = BFD_RELOC_8; break;
10308 case 2: code = BFD_RELOC_16; break;
10309 case 4: code = BFD_RELOC_32; break;
937149dd 10310#ifdef BFD64
3e73aa7c 10311 case 8: code = BFD_RELOC_64; break;
937149dd 10312#endif
93382f6d 10313 }
252b5132
RH		 10314 }
10315 break;
10316 }
252b5132 10317
d182319b
JB		 10318 if ((code == BFD_RELOC_32
10319 || code == BFD_RELOC_32_PCREL
10320 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10321 && GOT_symbol
10322 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10323 {
4fa24527 10324 if (!object_64bit)
d6ab8113
JB		 10325 code = BFD_RELOC_386_GOTPC;
10326 else
10327 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10328 }
7b81dfbb
AJ		 10329 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10330 && GOT_symbol
10331 && fixp->fx_addsy == GOT_symbol)
10332 {
10333 code = BFD_RELOC_X86_64_GOTPC64;
10334 }
252b5132
RH		 10335
10336 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 10337 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10338 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10339
10340 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10341
3e73aa7c
JH		 10342 if (!use_rela_relocations)
10343 {
10344 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10345 vtable entry to be used in the relocation's section offset. */
10346 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10347 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10348#if defined (OBJ_COFF) && defined (TE_PE)
10349 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10350 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10351 else
10352#endif
c6682705 10353 rel->addend = 0;
3e73aa7c
JH		 10354 }
10355 /* Use the rela in 64bit mode. */
252b5132 10356 else
3e73aa7c 10357 {
862be3fb
L		 10358 if (disallow_64bit_reloc)
10359 switch (code)
10360 {
862be3fb
L		 10361 case BFD_RELOC_X86_64_DTPOFF64:
10362 case BFD_RELOC_X86_64_TPOFF64:
10363 case BFD_RELOC_64_PCREL:
10364 case BFD_RELOC_X86_64_GOTOFF64:
10365 case BFD_RELOC_X86_64_GOT64:
10366 case BFD_RELOC_X86_64_GOTPCREL64:
10367 case BFD_RELOC_X86_64_GOTPC64:
10368 case BFD_RELOC_X86_64_GOTPLT64:
10369 case BFD_RELOC_X86_64_PLTOFF64:
10370 as_bad_where (fixp->fx_file, fixp->fx_line,
10371 _("cannot represent relocation type %s in x32 mode"),
10372 bfd_get_reloc_code_name (code));
10373 break;
10374 default:
10375 break;
10376 }
10377
062cd5e7
AS		 10378 if (!fixp->fx_pcrel)
10379 rel->addend = fixp->fx_offset;
10380 else
10381 switch (code)
10382 {
10383 case BFD_RELOC_X86_64_PLT32:
c3320543 10384 case BFD_RELOC_X86_64_PLT32_BND:
062cd5e7
AS		 10385 case BFD_RELOC_X86_64_GOT32:
10386 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 10387 case BFD_RELOC_X86_64_TLSGD:
10388 case BFD_RELOC_X86_64_TLSLD:
10389 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10390 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10391 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10392 rel->addend = fixp->fx_offset - fixp->fx_size;
10393 break;
10394 default:
10395 rel->addend = (section->vma
10396 - fixp->fx_size
10397 + fixp->fx_addnumber
10398 + md_pcrel_from (fixp));
10399 break;
10400 }
3e73aa7c
JH		 10401 }
10402
252b5132
RH		 10403 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10404 if (rel->howto == NULL)
10405 {
10406 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10407 _("cannot represent relocation type %s"),
252b5132
RH		 10408 bfd_get_reloc_code_name (code));
10409 /* Set howto to a garbage value so that we can keep going. */
10410 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10411 gas_assert (rel->howto != NULL);
252b5132
RH		 10412 }
10413
10414 return rel;
10415}
10416
ee86248c 10417#include "tc-i386-intel.c"
54cfded0 10418
a60de03c
JB		 10419void
10420tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10421{
a60de03c
JB		 10422 int saved_naked_reg;
10423 char saved_register_dot;
54cfded0 10424
a60de03c
JB		 10425 saved_naked_reg = allow_naked_reg;
10426 allow_naked_reg = 1;
10427 saved_register_dot = register_chars['.'];
10428 register_chars['.'] = '.';
10429 allow_pseudo_reg = 1;
10430 expression_and_evaluate (exp);
10431 allow_pseudo_reg = 0;
10432 register_chars['.'] = saved_register_dot;
10433 allow_naked_reg = saved_naked_reg;
10434
e96d56a1 10435 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10436 {
a60de03c
JB		 10437 if ((addressT) exp->X_add_number < i386_regtab_size)
10438 {
10439 exp->X_op = O_constant;
10440 exp->X_add_number = i386_regtab[exp->X_add_number]
10441 .dw2_regnum[flag_code >> 1];
10442 }
10443 else
10444 exp->X_op = O_illegal;
54cfded0 10445 }
54cfded0
AM		 10446}
10447
10448void
10449tc_x86_frame_initial_instructions (void)
10450{
a60de03c
JB		 10451 static unsigned int sp_regno[2];
10452
10453 if (!sp_regno[flag_code >> 1])
10454 {
10455 char *saved_input = input_line_pointer;
10456 char sp[][4] = {"esp", "rsp"};
10457 expressionS exp;
a4447b93 10458
a60de03c
JB		 10459 input_line_pointer = sp[flag_code >> 1];
10460 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10461 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10462 sp_regno[flag_code >> 1] = exp.X_add_number;
10463 input_line_pointer = saved_input;
10464 }
a4447b93 10465
61ff971f
L		 10466 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10467 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10468}
d2b2c203 10469
d7921315
L		 10470int
10471x86_dwarf2_addr_size (void)
10472{
10473#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10474 if (x86_elf_abi == X86_64_X32_ABI)
10475 return 4;
10476#endif
10477 return bfd_arch_bits_per_address (stdoutput) / 8;
10478}
10479
d2b2c203
DJ		 10480int
10481i386_elf_section_type (const char *str, size_t len)
10482{
10483 if (flag_code == CODE_64BIT
10484 && len == sizeof ("unwind") - 1
10485 && strncmp (str, "unwind", 6) == 0)
10486 return SHT_X86_64_UNWIND;
10487
10488 return -1;
10489}
bb41ade5 10490
ad5fec3b
EB		 10491#ifdef TE_SOLARIS
10492void
10493i386_solaris_fix_up_eh_frame (segT sec)
10494{
10495 if (flag_code == CODE_64BIT)
10496 elf_section_type (sec) = SHT_X86_64_UNWIND;
10497}
10498#endif
10499
bb41ade5
AM		 10500#ifdef TE_PE
10501void
10502tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10503{
91d6fa6a 10504 expressionS exp;
bb41ade5 10505
91d6fa6a
NC		 10506 exp.X_op = O_secrel;
10507 exp.X_add_symbol = symbol;
10508 exp.X_add_number = 0;
10509 emit_expr (&exp, size);
bb41ade5
AM		 10510}
10511#endif
3b22753a
L		 10512
10513#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10514/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10515
01e1a5bc 10516bfd_vma
3b22753a
L		 10517x86_64_section_letter (int letter, char **ptr_msg)
10518{
10519 if (flag_code == CODE_64BIT)
10520 {
10521 if (letter == 'l')
10522 return SHF_X86_64_LARGE;
10523
8f3bae45 10524 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10525 }
3b22753a 10526 else
8f3bae45 10527 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10528 return -1;
10529}
10530
01e1a5bc 10531bfd_vma
3b22753a
L		 10532x86_64_section_word (char *str, size_t len)
10533{
8620418b 10534 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10535 return SHF_X86_64_LARGE;
10536
10537 return -1;
10538}
10539
10540static void
10541handle_large_common (int small ATTRIBUTE_UNUSED)
10542{
10543 if (flag_code != CODE_64BIT)
10544 {
10545 s_comm_internal (0, elf_common_parse);
10546 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10547 }
10548 else
10549 {
10550 static segT lbss_section;
10551 asection *saved_com_section_ptr = elf_com_section_ptr;
10552 asection *saved_bss_section = bss_section;
10553
10554 if (lbss_section == NULL)
10555 {
10556 flagword applicable;
10557 segT seg = now_seg;
10558 subsegT subseg = now_subseg;
10559
10560 /* The .lbss section is for local .largecomm symbols. */
10561 lbss_section = subseg_new (".lbss", 0);
10562 applicable = bfd_applicable_section_flags (stdoutput);
10563 bfd_set_section_flags (stdoutput, lbss_section,
10564 applicable & SEC_ALLOC);
10565 seg_info (lbss_section)->bss = 1;
10566
10567 subseg_set (seg, subseg);
10568 }
10569
10570 elf_com_section_ptr = &_bfd_elf_large_com_section;
10571 bss_section = lbss_section;
10572
10573 s_comm_internal (0, elf_common_parse);
10574
10575 elf_com_section_ptr = saved_com_section_ptr;
10576 bss_section = saved_bss_section;
10577 }
10578}
10579#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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