projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Minor comment reformatting in generic_elf_osabi_sniffer
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
c75ef631 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
c32fa91d 62 REP_PREFIX, LOCK_PREFIX. */
6305a203
L		 63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
c32fa91d
L		 67#define REP_PREFIX 4
68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 86/* Intel Syntax. Use a non-ascii letter since since it never appears
87 in instructions. */
88#define LONG_DOUBLE_MNEM_SUFFIX '\1'
89
90#define END_OF_INSN '\0'
91
92/*
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
97 END.
98 */
99typedef struct
100{
d3ce72d0
NC		 101 const insn_template *start;
102 const insn_template *end;
6305a203
L		 103}
104templates;
105
106/* 386 operand encoding bytes: see 386 book for details of this. */
107typedef struct
108{
109 unsigned int regmem; /* codes register or memory operand */
110 unsigned int reg; /* codes register operand (or extended opcode) */
111 unsigned int mode; /* how to interpret regmem & reg */
112}
113modrm_byte;
114
115/* x86-64 extension prefix. */
116typedef int rex_byte;
117
6305a203
L		 118/* 386 opcode byte to code indirect addressing. */
119typedef struct
120{
121 unsigned base;
122 unsigned index;
123 unsigned scale;
124}
125sib_byte;
126
6305a203
L		 127/* x86 arch names, types and features */
128typedef struct
129{
130 const char *name; /* arch name */
8a2c8fef 131 unsigned int len; /* arch string length */
6305a203
L		 132 enum processor_type type; /* arch type */
133 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 134 unsigned int skip; /* show_arch should skip this. */
22109423 135 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 136}
137arch_entry;
138
78f12dd3 139static void update_code_flag (int, int);
e3bb37b5
L		 140static void set_code_flag (int);
141static void set_16bit_gcc_code_flag (int);
142static void set_intel_syntax (int);
1efbbeb4 143static void set_intel_mnemonic (int);
db51cc60 144static void set_allow_index_reg (int);
cb19c032 145static void set_sse_check (int);
e3bb37b5 146static void set_cpu_arch (int);
6482c264 147#ifdef TE_PE
e3bb37b5 148static void pe_directive_secrel (int);
6482c264 149#endif
e3bb37b5
L		 150static void signed_cons (int);
151static char *output_invalid (int c);
ee86248c
JB		 152static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
153 const char *);
154static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
155 const char *);
a7619375 156static int i386_att_operand (char *);
e3bb37b5 157static int i386_intel_operand (char *, int);
ee86248c
JB		 158static int i386_intel_simplify (expressionS *);
159static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 160static const reg_entry *parse_register (char *, char **);
161static char *parse_insn (char *, char *);
162static char *parse_operands (char *, const char *);
163static void swap_operands (void);
4d456e3d 164static void swap_2_operands (int, int);
e3bb37b5
L		 165static void optimize_imm (void);
166static void optimize_disp (void);
d3ce72d0 167static const insn_template *match_template (void);
e3bb37b5
L		 168static int check_string (void);
169static int process_suffix (void);
170static int check_byte_reg (void);
171static int check_long_reg (void);
172static int check_qword_reg (void);
173static int check_word_reg (void);
174static int finalize_imm (void);
175static int process_operands (void);
176static const seg_entry *build_modrm_byte (void);
177static void output_insn (void);
178static void output_imm (fragS *, offsetT);
179static void output_disp (fragS *, offsetT);
29b0f896 180#ifndef I386COFF
e3bb37b5 181static void s_bss (int);
252b5132 182#endif
17d4e2a2
L		 183#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
184static void handle_large_common (int small ATTRIBUTE_UNUSED);
314a59d5 185static void handle_quad (int);
17d4e2a2 186#endif
252b5132 187
a847613f 188static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 189
c0f3af97
L		 190/* VEX prefix. */
191typedef struct
192{
193 /* VEX prefix is either 2 byte or 3 byte. */
194 unsigned char bytes[3];
195 unsigned int length;
196 /* Destination or source register specifier. */
197 const reg_entry *register_specifier;
198} vex_prefix;
199
252b5132 200/* 'md_assemble ()' gathers together information and puts it into a
47926f60 201 i386_insn. */
252b5132 202
520dc8e8
AM		 203union i386_op
204 {
205 expressionS *disps;
206 expressionS *imms;
207 const reg_entry *regs;
208 };
209
a65babc9
L		 210enum i386_error
211 {
86e026a4 212 operand_size_mismatch,
a65babc9
L		 213 operand_type_mismatch,
214 register_type_mismatch,
215 number_of_operands_mismatch,
216 invalid_instruction_suffix,
217 bad_imm4,
218 old_gcc_only,
219 unsupported_with_intel_mnemonic,
220 unsupported_syntax,
6c30d220
L		 221 unsupported,
222 invalid_vsib_address,
223 unsupported_vector_index_register
a65babc9
L		 224 };
225
252b5132
RH		 226struct _i386_insn
227 {
47926f60 228 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 229 insn_template tm;
252b5132 230
7d5e4556
L		 231 /* SUFFIX holds the instruction size suffix for byte, word, dword
232 or qword, if given. */
252b5132
RH		 233 char suffix;
234
47926f60 235 /* OPERANDS gives the number of given operands. */
252b5132
RH		 236 unsigned int operands;
237
238 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
239 of given register, displacement, memory operands and immediate
47926f60 240 operands. */
252b5132
RH		 241 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
242
243 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 244 use OP[i] for the corresponding operand. */
40fb9820 245 i386_operand_type types[MAX_OPERANDS];
252b5132 246
520dc8e8
AM		 247 /* Displacement expression, immediate expression, or register for each
248 operand. */
249 union i386_op op[MAX_OPERANDS];
252b5132 250
3e73aa7c
JH		 251 /* Flags for operands. */
252 unsigned int flags[MAX_OPERANDS];
253#define Operand_PCrel 1
254
252b5132 255 /* Relocation type for operand */
f86103b7 256 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 257
252b5132
RH		 258 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
259 the base index byte below. */
260 const reg_entry *base_reg;
261 const reg_entry *index_reg;
262 unsigned int log2_scale_factor;
263
264 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 265 explicit segment overrides are given. */
ce8a8b2f 266 const seg_entry *seg[2];
252b5132
RH		 267
268 /* PREFIX holds all the given prefix opcodes (usually null).
269 PREFIXES is the number of prefix opcodes. */
270 unsigned int prefixes;
271 unsigned char prefix[MAX_PREFIXES];
272
273 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 274 addressing modes of this insn are encoded. */
252b5132 275 modrm_byte rm;
3e73aa7c 276 rex_byte rex;
252b5132 277 sib_byte sib;
c0f3af97 278 vex_prefix vex;
b6169b20
L		 279
280 /* Swap operand in encoding. */
4473e004 281 unsigned int swap_operand;
891edac4 282
f8a5c266
L		 283 /* Force 32bit displacement in encoding. */
284 unsigned int disp32_encoding;
285
891edac4 286 /* Error message. */
a65babc9 287 enum i386_error error;
252b5132
RH		 288 };
289
290typedef struct _i386_insn i386_insn;
291
292/* List of chars besides those in app.c:symbol_chars that can start an
293 operand. Used to prevent the scrubber eating vital white-space. */
32137342 294const char extra_symbol_chars[] = "*%-(["
252b5132 295#ifdef LEX_AT
32137342
NC		 296 "@"
297#endif
298#ifdef LEX_QM
299 "?"
252b5132 300#endif
32137342 301 ;
252b5132 302
29b0f896
AM		 303#if (defined (TE_I386AIX) \
304 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 305 && !defined (TE_GNU) \
29b0f896 306 && !defined (TE_LINUX) \
32137342 307 && !defined (TE_NETWARE) \
29b0f896 308 && !defined (TE_FreeBSD) \
5b806d27 309 && !defined (TE_DragonFly) \
29b0f896 310 && !defined (TE_NetBSD)))
252b5132 311/* This array holds the chars that always start a comment. If the
b3b91714
AM		 312 pre-processor is disabled, these aren't very useful. The option
313 --divide will remove '/' from this list. */
314const char *i386_comment_chars = "#/";
315#define SVR4_COMMENT_CHARS 1
252b5132 316#define PREFIX_SEPARATOR '\\'
252b5132 317
b3b91714
AM		 318#else
319const char *i386_comment_chars = "#";
320#define PREFIX_SEPARATOR '/'
321#endif
322
252b5132
RH		 323/* This array holds the chars that only start a comment at the beginning of
324 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 325 .line and .file directives will appear in the pre-processed output.
326 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 327 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 328 #NO_APP at the beginning of its output.
329 Also note that comments started like this one will always work if
252b5132 330 '/' isn't otherwise defined. */
b3b91714 331const char line_comment_chars[] = "#/";
252b5132 332
63a0b638 333const char line_separator_chars[] = ";";
252b5132 334
ce8a8b2f
AM		 335/* Chars that can be used to separate mant from exp in floating point
336 nums. */
252b5132
RH		 337const char EXP_CHARS[] = "eE";
338
ce8a8b2f
AM		 339/* Chars that mean this number is a floating point constant
340 As in 0f12.456
341 or 0d1.2345e12. */
252b5132
RH		 342const char FLT_CHARS[] = "fFdDxX";
343
ce8a8b2f 344/* Tables for lexical analysis. */
252b5132
RH		 345static char mnemonic_chars[256];
346static char register_chars[256];
347static char operand_chars[256];
348static char identifier_chars[256];
349static char digit_chars[256];
350
ce8a8b2f 351/* Lexical macros. */
252b5132
RH		 352#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
353#define is_operand_char(x) (operand_chars[(unsigned char) x])
354#define is_register_char(x) (register_chars[(unsigned char) x])
355#define is_space_char(x) ((x) == ' ')
356#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
357#define is_digit_char(x) (digit_chars[(unsigned char) x])
358
0234cb7c 359/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 360static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
361
362/* md_assemble() always leaves the strings it's passed unaltered. To
363 effect this we maintain a stack of saved characters that we've smashed
364 with '\0's (indicating end of strings for various sub-fields of the
47926f60 365 assembler instruction). */
252b5132 366static char save_stack[32];
ce8a8b2f 367static char *save_stack_p;
252b5132
RH		 368#define END_STRING_AND_SAVE(s) \
369 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
370#define RESTORE_END_STRING(s) \
371 do { *(s) = *--save_stack_p; } while (0)
372
47926f60 373/* The instruction we're assembling. */
252b5132
RH		 374static i386_insn i;
375
376/* Possible templates for current insn. */
377static const templates *current_templates;
378
31b2323c
L		 379/* Per instruction expressionS buffers: max displacements & immediates. */
380static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
381static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 382
47926f60 383/* Current operand we are working on. */
ee86248c 384static int this_operand = -1;
252b5132 385
3e73aa7c
JH		 386/* We support four different modes. FLAG_CODE variable is used to distinguish
387 these. */
388
389enum flag_code {
390 CODE_32BIT,
391 CODE_16BIT,
392 CODE_64BIT };
393
394static enum flag_code flag_code;
4fa24527 395static unsigned int object_64bit;
862be3fb 396static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 397static int use_rela_relocations = 0;
398
7af8ed2d
NC		 399#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
400 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
401 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
402
351f65ca
L		 403/* The ELF ABI to use. */
404enum x86_elf_abi
405{
406 I386_ABI,
7f56bc95
L		 407 X86_64_ABI,
408 X86_64_X32_ABI
351f65ca
L		 409};
410
411static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 412#endif
351f65ca 413
3e73aa7c 414/* The names used to print error messages. */
b77a7acd 415static const char *flag_code_names[] =
3e73aa7c
JH		 416 {
417 "32",
418 "16",
419 "64"
420 };
252b5132 421
47926f60
KH		 422/* 1 for intel syntax,
423 0 if att syntax. */
424static int intel_syntax = 0;
252b5132 425
1efbbeb4
L		 426/* 1 for intel mnemonic,
427 0 if att mnemonic. */
428static int intel_mnemonic = !SYSV386_COMPAT;
429
5209009a 430/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 431static int old_gcc = OLDGCC_COMPAT;
432
a60de03c
JB		 433/* 1 if pseudo registers are permitted. */
434static int allow_pseudo_reg = 0;
435
47926f60
KH		 436/* 1 if register prefix % not required. */
437static int allow_naked_reg = 0;
252b5132 438
ba104c83 439/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 440static int allow_index_reg = 0;
441
daf50ae7
L		 442static enum
443 {
444 sse_check_none = 0,
445 sse_check_warning,
446 sse_check_error
447 }
448sse_check;
449
2ca3ace5
L		 450/* Register prefix used for error message. */
451static const char *register_prefix = "%";
452
47926f60
KH		 453/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
454 leave, push, and pop instructions so that gcc has the same stack
455 frame as in 32 bit mode. */
456static char stackop_size = '\0';
eecb386c 457
12b55ccc
L		 458/* Non-zero to optimize code alignment. */
459int optimize_align_code = 1;
460
47926f60
KH		 461/* Non-zero to quieten some warnings. */
462static int quiet_warnings = 0;
a38cf1db 463
47926f60
KH		 464/* CPU name. */
465static const char *cpu_arch_name = NULL;
6305a203 466static char *cpu_sub_arch_name = NULL;
a38cf1db 467
47926f60 468/* CPU feature flags. */
40fb9820
L		 469static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
470
ccc9c027
L		 471/* If we have selected a cpu we are generating instructions for. */
472static int cpu_arch_tune_set = 0;
473
9103f4f4 474/* Cpu we are generating instructions for. */
fbf3f584 475enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 476
477/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 478static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 479
ccc9c027 480/* CPU instruction set architecture used. */
fbf3f584 481enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 482
9103f4f4 483/* CPU feature flags of instruction set architecture used. */
fbf3f584 484i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 485
fddf5b5b
AM		 486/* If set, conditional jumps are not automatically promoted to handle
487 larger than a byte offset. */
488static unsigned int no_cond_jump_promotion = 0;
489
c0f3af97
L		 490/* Encode SSE instructions with VEX prefix. */
491static unsigned int sse2avx;
492
539f890d
L		 493/* Encode scalar AVX instructions with specific vector length. */
494static enum
495 {
496 vex128 = 0,
497 vex256
498 } avxscalar;
499
29b0f896 500/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 501static symbolS *GOT_symbol;
29b0f896 502
a4447b93
RH		 503/* The dwarf2 return column, adjusted for 32 or 64 bit. */
504unsigned int x86_dwarf2_return_column;
505
506/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
507int x86_cie_data_alignment;
508
252b5132 509/* Interface to relax_segment.
fddf5b5b
AM		 510 There are 3 major relax states for 386 jump insns because the
511 different types of jumps add different sizes to frags when we're
512 figuring out what sort of jump to choose to reach a given label. */
252b5132 513
47926f60 514/* Types. */
93c2a809
AM		 515#define UNCOND_JUMP 0
516#define COND_JUMP 1
517#define COND_JUMP86 2
fddf5b5b 518
47926f60 519/* Sizes. */
252b5132
RH		 520#define CODE16 1
521#define SMALL 0
29b0f896 522#define SMALL16 (SMALL | CODE16)
252b5132 523#define BIG 2
29b0f896 524#define BIG16 (BIG | CODE16)
252b5132
RH		 525
526#ifndef INLINE
527#ifdef __GNUC__
528#define INLINE __inline__
529#else
530#define INLINE
531#endif
532#endif
533
fddf5b5b
AM		 534#define ENCODE_RELAX_STATE(type, size) \
535 ((relax_substateT) (((type) << 2) | (size)))
536#define TYPE_FROM_RELAX_STATE(s) \
537 ((s) >> 2)
538#define DISP_SIZE_FROM_RELAX_STATE(s) \
539 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 540
541/* This table is used by relax_frag to promote short jumps to long
542 ones where necessary. SMALL (short) jumps may be promoted to BIG
543 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
544 don't allow a short jump in a 32 bit code segment to be promoted to
545 a 16 bit offset jump because it's slower (requires data size
546 prefix), and doesn't work, unless the destination is in the bottom
547 64k of the code segment (The top 16 bits of eip are zeroed). */
548
549const relax_typeS md_relax_table[] =
550{
24eab124
AM		 551 /* The fields are:
552 1) most positive reach of this state,
553 2) most negative reach of this state,
93c2a809 554 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 555 4) which index into the table to try if we can't fit into this one. */
252b5132 556
fddf5b5b 557 /* UNCOND_JUMP states. */
93c2a809
AM		 558 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
559 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
560 /* dword jmp adds 4 bytes to frag:
561 0 extra opcode bytes, 4 displacement bytes. */
252b5132 562 {0, 0, 4, 0},
93c2a809
AM		 563 /* word jmp adds 2 byte2 to frag:
564 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 565 {0, 0, 2, 0},
566
93c2a809
AM		 567 /* COND_JUMP states. */
568 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
569 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
570 /* dword conditionals adds 5 bytes to frag:
571 1 extra opcode byte, 4 displacement bytes. */
572 {0, 0, 5, 0},
fddf5b5b 573 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 574 1 extra opcode byte, 2 displacement bytes. */
575 {0, 0, 3, 0},
576
577 /* COND_JUMP86 states. */
578 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
579 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
580 /* dword conditionals adds 5 bytes to frag:
581 1 extra opcode byte, 4 displacement bytes. */
582 {0, 0, 5, 0},
583 /* word conditionals add 4 bytes to frag:
584 1 displacement byte and a 3 byte long branch insn. */
585 {0, 0, 4, 0}
252b5132
RH		 586};
587
9103f4f4
L		 588static const arch_entry cpu_arch[] =
589{
89507696
JB		 590 /* Do not replace the first two entries - i386_target_format()
591 relies on them being there in this order. */
8a2c8fef 592 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 593 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 594 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 595 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 596 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 597 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 598 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 599 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 600 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 601 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 602 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 603 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 604 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 605 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 606 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 607 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 608 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 609 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 610 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 611 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 612 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 613 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 614 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 615 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 616 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 617 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 618 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 619 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 620 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 621 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 622 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 623 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 624 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 625 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 626 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 627 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 628 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 629 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 630 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 631 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 632 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 633 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 634 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 635 CPU_L1OM_FLAGS, 0, 0 },
8a2c8fef 636 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 637 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 638 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 639 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 640 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 641 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 642 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 643 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 644 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 645 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 646 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 647 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 648 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 649 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 650 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 651 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 652 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 653 CPU_BDVER2_FLAGS, 0, 0 },
8a2c8fef 654 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 655 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 656 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 657 CPU_287_FLAGS, 0, 0 },
8a2c8fef 658 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 659 CPU_387_FLAGS, 0, 0 },
8a2c8fef 660 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 661 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 662 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 663 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 664 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 665 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 666 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 667 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 668 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 669 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 670 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 671 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 672 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 673 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 674 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 675 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 676 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 677 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 678 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 679 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 680 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 681 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 682 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 683 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 684 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
685 CPU_AVX2_FLAGS, 0, 0 },
8a2c8fef 686 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 687 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 688 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 689 CPU_VMX_FLAGS, 0, 0 },
8a2c8fef 690 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 691 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 692 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 693 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 694 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 695 CPU_XSAVEOPT_FLAGS, 0, 0 },
8a2c8fef 696 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 697 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 698 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 699 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 700 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 701 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 702 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 703 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 704 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 705 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 706 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 707 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 708 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
709 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 710 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 711 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 712 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 713 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 714 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 715 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 716 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 717 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 718 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 719 CPU_MOVBE_FLAGS, 0, 0 },
8a2c8fef 720 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 721 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 722 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
723 CPU_LZCNT_FLAGS, 0, 0 },
724 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
725 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 726 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 727 CPU_CLFLUSH_FLAGS, 0, 0 },
728 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
729 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 730 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 731 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 732 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 733 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 734 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 735 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 736 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 737 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 738 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 739 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 740 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 741 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 742 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 743 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 744 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 745 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 746 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 747 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 748 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
749 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 750 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
751 CPU_TBM_FLAGS, 0, 0 },
e413e4e9
AM		 752};
753
704209c0 754#ifdef I386COFF
a6c24e68
NC		 755/* Like s_lcomm_internal in gas/read.c but the alignment string
756 is allowed to be optional. */
757
758static symbolS *
759pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
760{
761 addressT align = 0;
762
763 SKIP_WHITESPACE ();
764
7ab9ffdd 765 if (needs_align
a6c24e68
NC		 766 && *input_line_pointer == ',')
767 {
768 align = parse_align (needs_align - 1);
7ab9ffdd 769
a6c24e68
NC		 770 if (align == (addressT) -1)
771 return NULL;
772 }
773 else
774 {
775 if (size >= 8)
776 align = 3;
777 else if (size >= 4)
778 align = 2;
779 else if (size >= 2)
780 align = 1;
781 else
782 align = 0;
783 }
784
785 bss_alloc (symbolP, size, align);
786 return symbolP;
787}
788
704209c0 789static void
a6c24e68
NC		 790pe_lcomm (int needs_align)
791{
792 s_comm_internal (needs_align * 2, pe_lcomm_internal);
793}
704209c0 794#endif
a6c24e68 795
29b0f896
AM		 796const pseudo_typeS md_pseudo_table[] =
797{
798#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
799 {"align", s_align_bytes, 0},
800#else
801 {"align", s_align_ptwo, 0},
802#endif
803 {"arch", set_cpu_arch, 0},
804#ifndef I386COFF
805 {"bss", s_bss, 0},
a6c24e68
NC		 806#else
807 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 808#endif
809 {"ffloat", float_cons, 'f'},
810 {"dfloat", float_cons, 'd'},
811 {"tfloat", float_cons, 'x'},
812 {"value", cons, 2},
d182319b 813 {"slong", signed_cons, 4},
29b0f896
AM		 814 {"noopt", s_ignore, 0},
815 {"optim", s_ignore, 0},
816 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
817 {"code16", set_code_flag, CODE_16BIT},
818 {"code32", set_code_flag, CODE_32BIT},
819 {"code64", set_code_flag, CODE_64BIT},
820 {"intel_syntax", set_intel_syntax, 1},
821 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 822 {"intel_mnemonic", set_intel_mnemonic, 1},
823 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 824 {"allow_index_reg", set_allow_index_reg, 1},
825 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 826 {"sse_check", set_sse_check, 0},
3b22753a
L		 827#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
828 {"largecomm", handle_large_common, 0},
314a59d5 829 {"quad", handle_quad, 8},
07a53e5c 830#else
e3bb37b5 831 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 832 {"loc", dwarf2_directive_loc, 0},
833 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 834#endif
6482c264
NC		 835#ifdef TE_PE
836 {"secrel32", pe_directive_secrel, 0},
837#endif
29b0f896
AM		 838 {0, 0, 0}
839};
840
841/* For interface with expression (). */
842extern char *input_line_pointer;
843
844/* Hash table for instruction mnemonic lookup. */
845static struct hash_control *op_hash;
846
847/* Hash table for register lookup. */
848static struct hash_control *reg_hash;
849\f
252b5132 850void
e3bb37b5 851i386_align_code (fragS *fragP, int count)
252b5132 852{
ce8a8b2f
AM		 853 /* Various efficient no-op patterns for aligning code labels.
854 Note: Don't try to assemble the instructions in the comments.
855 0L and 0w are not legal. */
252b5132
RH		 856 static const char f32_1[] =
857 {0x90}; /* nop */
858 static const char f32_2[] =
ccc9c027 859 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 860 static const char f32_3[] =
861 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
862 static const char f32_4[] =
863 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
864 static const char f32_5[] =
865 {0x90, /* nop */
866 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
867 static const char f32_6[] =
868 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
869 static const char f32_7[] =
870 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
871 static const char f32_8[] =
872 {0x90, /* nop */
873 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
874 static const char f32_9[] =
875 {0x89,0xf6, /* movl %esi,%esi */
876 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
877 static const char f32_10[] =
878 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
879 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
880 static const char f32_11[] =
881 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
882 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
883 static const char f32_12[] =
884 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
885 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
886 static const char f32_13[] =
887 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
888 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
889 static const char f32_14[] =
890 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
891 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 892 static const char f16_3[] =
893 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 894 static const char f16_4[] =
895 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
896 static const char f16_5[] =
897 {0x90, /* nop */
898 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
899 static const char f16_6[] =
900 {0x89,0xf6, /* mov %si,%si */
901 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
902 static const char f16_7[] =
903 {0x8d,0x74,0x00, /* lea 0(%si),%si */
904 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
905 static const char f16_8[] =
906 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
907 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 908 static const char jump_31[] =
909 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
910 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
911 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
912 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 913 static const char *const f32_patt[] = {
914 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 915 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 916 };
917 static const char *const f16_patt[] = {
76bc74dc 918 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 919 };
ccc9c027
L		 920 /* nopl (%[re]ax) */
921 static const char alt_3[] =
922 {0x0f,0x1f,0x00};
923 /* nopl 0(%[re]ax) */
924 static const char alt_4[] =
925 {0x0f,0x1f,0x40,0x00};
926 /* nopl 0(%[re]ax,%[re]ax,1) */
927 static const char alt_5[] =
928 {0x0f,0x1f,0x44,0x00,0x00};
929 /* nopw 0(%[re]ax,%[re]ax,1) */
930 static const char alt_6[] =
931 {0x66,0x0f,0x1f,0x44,0x00,0x00};
932 /* nopl 0L(%[re]ax) */
933 static const char alt_7[] =
934 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
935 /* nopl 0L(%[re]ax,%[re]ax,1) */
936 static const char alt_8[] =
937 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
938 /* nopw 0L(%[re]ax,%[re]ax,1) */
939 static const char alt_9[] =
940 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
941 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
942 static const char alt_10[] =
943 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
944 /* data16
945 nopw %cs:0L(%[re]ax,%[re]ax,1) */
946 static const char alt_long_11[] =
947 {0x66,
948 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
949 /* data16
950 data16
951 nopw %cs:0L(%[re]ax,%[re]ax,1) */
952 static const char alt_long_12[] =
953 {0x66,
954 0x66,
955 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
956 /* data16
957 data16
958 data16
959 nopw %cs:0L(%[re]ax,%[re]ax,1) */
960 static const char alt_long_13[] =
961 {0x66,
962 0x66,
963 0x66,
964 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
965 /* data16
966 data16
967 data16
968 data16
969 nopw %cs:0L(%[re]ax,%[re]ax,1) */
970 static const char alt_long_14[] =
971 {0x66,
972 0x66,
973 0x66,
974 0x66,
975 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
976 /* data16
977 data16
978 data16
979 data16
980 data16
981 nopw %cs:0L(%[re]ax,%[re]ax,1) */
982 static const char alt_long_15[] =
983 {0x66,
984 0x66,
985 0x66,
986 0x66,
987 0x66,
988 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
989 /* nopl 0(%[re]ax,%[re]ax,1)
990 nopw 0(%[re]ax,%[re]ax,1) */
991 static const char alt_short_11[] =
992 {0x0f,0x1f,0x44,0x00,0x00,
993 0x66,0x0f,0x1f,0x44,0x00,0x00};
994 /* nopw 0(%[re]ax,%[re]ax,1)
995 nopw 0(%[re]ax,%[re]ax,1) */
996 static const char alt_short_12[] =
997 {0x66,0x0f,0x1f,0x44,0x00,0x00,
998 0x66,0x0f,0x1f,0x44,0x00,0x00};
999 /* nopw 0(%[re]ax,%[re]ax,1)
1000 nopl 0L(%[re]ax) */
1001 static const char alt_short_13[] =
1002 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1003 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1004 /* nopl 0L(%[re]ax)
1005 nopl 0L(%[re]ax) */
1006 static const char alt_short_14[] =
1007 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1008 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1009 /* nopl 0L(%[re]ax)
1010 nopl 0L(%[re]ax,%[re]ax,1) */
1011 static const char alt_short_15[] =
1012 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1013 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1014 static const char *const alt_short_patt[] = {
1015 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1016 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
1017 alt_short_14, alt_short_15
1018 };
1019 static const char *const alt_long_patt[] = {
1020 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1021 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1022 alt_long_14, alt_long_15
1023 };
252b5132 1024
76bc74dc
L		 1025 /* Only align for at least a positive non-zero boundary. */
1026 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1027 return;
3e73aa7c 1028
ccc9c027
L		 1029 /* We need to decide which NOP sequence to use for 32bit and
1030 64bit. When -mtune= is used:
4eed87de 1031
76bc74dc
L		 1032 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1033 PROCESSOR_GENERIC32, f32_patt will be used.
1034 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 1035 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1036 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 1037 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
8aedb9fe 1038 PROCESSOR_AMDFAM10, and PROCESSOR_BD, alt_short_patt
69dd9865 1039 will be used.
ccc9c027 1040
76bc74dc 1041 When -mtune= isn't used, alt_long_patt will be used if
22109423 1042 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1043 be used.
ccc9c027
L		 1044
1045 When -march= or .arch is used, we can't use anything beyond
1046 cpu_arch_isa_flags. */
1047
1048 if (flag_code == CODE_16BIT)
1049 {
ccc9c027 1050 if (count > 8)
33fef721 1051 {
76bc74dc
L		 1052 memcpy (fragP->fr_literal + fragP->fr_fix,
1053 jump_31, count);
1054 /* Adjust jump offset. */
1055 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1056 }
76bc74dc
L		 1057 else
1058 memcpy (fragP->fr_literal + fragP->fr_fix,
1059 f16_patt[count - 1], count);
252b5132 1060 }
33fef721 1061 else
ccc9c027
L		 1062 {
1063 const char *const *patt = NULL;
1064
fbf3f584 1065 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1066 {
1067 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1068 switch (cpu_arch_tune)
1069 {
1070 case PROCESSOR_UNKNOWN:
1071 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1072 optimize with nops. */
1073 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1074 patt = alt_long_patt;
ccc9c027
L		 1075 else
1076 patt = f32_patt;
1077 break;
ccc9c027
L		 1078 case PROCESSOR_PENTIUM4:
1079 case PROCESSOR_NOCONA:
ef05d495 1080 case PROCESSOR_CORE:
76bc74dc 1081 case PROCESSOR_CORE2:
bd5295b2 1082 case PROCESSOR_COREI7:
3632d14b 1083 case PROCESSOR_L1OM:
76bc74dc
L		 1084 case PROCESSOR_GENERIC64:
1085 patt = alt_long_patt;
1086 break;
ccc9c027
L		 1087 case PROCESSOR_K6:
1088 case PROCESSOR_ATHLON:
1089 case PROCESSOR_K8:
4eed87de 1090 case PROCESSOR_AMDFAM10:
8aedb9fe 1091 case PROCESSOR_BD:
ccc9c027
L		 1092 patt = alt_short_patt;
1093 break;
76bc74dc 1094 case PROCESSOR_I386:
ccc9c027
L		 1095 case PROCESSOR_I486:
1096 case PROCESSOR_PENTIUM:
2dde1948 1097 case PROCESSOR_PENTIUMPRO:
ccc9c027
L		 1098 case PROCESSOR_GENERIC32:
1099 patt = f32_patt;
1100 break;
4eed87de 1101 }
ccc9c027
L		 1102 }
1103 else
1104 {
fbf3f584 1105 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1106 {
1107 case PROCESSOR_UNKNOWN:
e6a14101 1108 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1109 PROCESSOR_UNKNOWN. */
1110 abort ();
1111 break;
1112
76bc74dc 1113 case PROCESSOR_I386:
ccc9c027
L		 1114 case PROCESSOR_I486:
1115 case PROCESSOR_PENTIUM:
ccc9c027
L		 1116 case PROCESSOR_K6:
1117 case PROCESSOR_ATHLON:
1118 case PROCESSOR_K8:
4eed87de 1119 case PROCESSOR_AMDFAM10:
8aedb9fe 1120 case PROCESSOR_BD:
ccc9c027
L		 1121 case PROCESSOR_GENERIC32:
1122 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1123 with nops. */
1124 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1125 patt = alt_short_patt;
1126 else
1127 patt = f32_patt;
1128 break;
76bc74dc
L		 1129 case PROCESSOR_PENTIUMPRO:
1130 case PROCESSOR_PENTIUM4:
1131 case PROCESSOR_NOCONA:
1132 case PROCESSOR_CORE:
ef05d495 1133 case PROCESSOR_CORE2:
bd5295b2 1134 case PROCESSOR_COREI7:
3632d14b 1135 case PROCESSOR_L1OM:
22109423 1136 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1137 patt = alt_long_patt;
1138 else
1139 patt = f32_patt;
1140 break;
1141 case PROCESSOR_GENERIC64:
76bc74dc 1142 patt = alt_long_patt;
ccc9c027 1143 break;
4eed87de 1144 }
ccc9c027
L		 1145 }
1146
76bc74dc
L		 1147 if (patt == f32_patt)
1148 {
1149 /* If the padding is less than 15 bytes, we use the normal
1150 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1151 its offset. */
1152 int limit;
76ba9986 1153
711eedef
L		 1154 /* For 64bit, the limit is 3 bytes. */
1155 if (flag_code == CODE_64BIT
1156 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1157 limit = 3;
1158 else
1159 limit = 15;
1160 if (count < limit)
76bc74dc
L		 1161 memcpy (fragP->fr_literal + fragP->fr_fix,
1162 patt[count - 1], count);
1163 else
1164 {
1165 memcpy (fragP->fr_literal + fragP->fr_fix,
1166 jump_31, count);
1167 /* Adjust jump offset. */
1168 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1169 }
1170 }
1171 else
1172 {
1173 /* Maximum length of an instruction is 15 byte. If the
1174 padding is greater than 15 bytes and we don't use jump,
1175 we have to break it into smaller pieces. */
1176 int padding = count;
1177 while (padding > 15)
1178 {
1179 padding -= 15;
1180 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1181 patt [14], 15);
1182 }
1183
1184 if (padding)
1185 memcpy (fragP->fr_literal + fragP->fr_fix,
1186 patt [padding - 1], padding);
1187 }
ccc9c027 1188 }
33fef721 1189 fragP->fr_var = count;
252b5132
RH		 1190}
1191
c6fb90c8 1192static INLINE int
0dfbf9d7 1193operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1194{
0dfbf9d7 1195 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1196 {
1197 case 3:
0dfbf9d7 1198 if (x->array[2])
c6fb90c8
L		 1199 return 0;
1200 case 2:
0dfbf9d7 1201 if (x->array[1])
c6fb90c8
L		 1202 return 0;
1203 case 1:
0dfbf9d7 1204 return !x->array[0];
c6fb90c8
L		 1205 default:
1206 abort ();
1207 }
40fb9820
L		 1208}
1209
c6fb90c8 1210static INLINE void
0dfbf9d7 1211operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1212{
0dfbf9d7 1213 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1214 {
1215 case 3:
0dfbf9d7 1216 x->array[2] = v;
c6fb90c8 1217 case 2:
0dfbf9d7 1218 x->array[1] = v;
c6fb90c8 1219 case 1:
0dfbf9d7 1220 x->array[0] = v;
c6fb90c8
L		 1221 break;
1222 default:
1223 abort ();
1224 }
1225}
40fb9820 1226
c6fb90c8 1227static INLINE int
0dfbf9d7
L		 1228operand_type_equal (const union i386_operand_type *x,
1229 const union i386_operand_type *y)
c6fb90c8 1230{
0dfbf9d7 1231 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1232 {
1233 case 3:
0dfbf9d7 1234 if (x->array[2] != y->array[2])
c6fb90c8
L		 1235 return 0;
1236 case 2:
0dfbf9d7 1237 if (x->array[1] != y->array[1])
c6fb90c8
L		 1238 return 0;
1239 case 1:
0dfbf9d7 1240 return x->array[0] == y->array[0];
c6fb90c8
L		 1241 break;
1242 default:
1243 abort ();
1244 }
1245}
40fb9820 1246
0dfbf9d7
L		 1247static INLINE int
1248cpu_flags_all_zero (const union i386_cpu_flags *x)
1249{
1250 switch (ARRAY_SIZE(x->array))
1251 {
1252 case 3:
1253 if (x->array[2])
1254 return 0;
1255 case 2:
1256 if (x->array[1])
1257 return 0;
1258 case 1:
1259 return !x->array[0];
1260 default:
1261 abort ();
1262 }
1263}
1264
1265static INLINE void
1266cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1267{
1268 switch (ARRAY_SIZE(x->array))
1269 {
1270 case 3:
1271 x->array[2] = v;
1272 case 2:
1273 x->array[1] = v;
1274 case 1:
1275 x->array[0] = v;
1276 break;
1277 default:
1278 abort ();
1279 }
1280}
1281
1282static INLINE int
1283cpu_flags_equal (const union i386_cpu_flags *x,
1284 const union i386_cpu_flags *y)
1285{
1286 switch (ARRAY_SIZE(x->array))
1287 {
1288 case 3:
1289 if (x->array[2] != y->array[2])
1290 return 0;
1291 case 2:
1292 if (x->array[1] != y->array[1])
1293 return 0;
1294 case 1:
1295 return x->array[0] == y->array[0];
1296 break;
1297 default:
1298 abort ();
1299 }
1300}
c6fb90c8
L		 1301
1302static INLINE int
1303cpu_flags_check_cpu64 (i386_cpu_flags f)
1304{
1305 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1306 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1307}
1308
c6fb90c8
L		 1309static INLINE i386_cpu_flags
1310cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1311{
c6fb90c8
L		 1312 switch (ARRAY_SIZE (x.array))
1313 {
1314 case 3:
1315 x.array [2] &= y.array [2];
1316 case 2:
1317 x.array [1] &= y.array [1];
1318 case 1:
1319 x.array [0] &= y.array [0];
1320 break;
1321 default:
1322 abort ();
1323 }
1324 return x;
1325}
40fb9820 1326
c6fb90c8
L		 1327static INLINE i386_cpu_flags
1328cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1329{
c6fb90c8 1330 switch (ARRAY_SIZE (x.array))
40fb9820 1331 {
c6fb90c8
L		 1332 case 3:
1333 x.array [2] |= y.array [2];
1334 case 2:
1335 x.array [1] |= y.array [1];
1336 case 1:
1337 x.array [0] |= y.array [0];
40fb9820
L		 1338 break;
1339 default:
1340 abort ();
1341 }
40fb9820
L		 1342 return x;
1343}
1344
309d3373
JB		 1345static INLINE i386_cpu_flags
1346cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1347{
1348 switch (ARRAY_SIZE (x.array))
1349 {
1350 case 3:
1351 x.array [2] &= ~y.array [2];
1352 case 2:
1353 x.array [1] &= ~y.array [1];
1354 case 1:
1355 x.array [0] &= ~y.array [0];
1356 break;
1357 default:
1358 abort ();
1359 }
1360 return x;
1361}
1362
c0f3af97
L		 1363#define CPU_FLAGS_ARCH_MATCH 0x1
1364#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1365#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1366#define CPU_FLAGS_PCLMUL_MATCH 0x8
1367#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1368
a5ff0eb2 1369#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1370 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1371 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1372#define CPU_FLAGS_PERFECT_MATCH \
1373 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1374
1375/* Return CPU flags match bits. */
3629bb00 1376
40fb9820 1377static int
d3ce72d0 1378cpu_flags_match (const insn_template *t)
40fb9820 1379{
c0f3af97
L		 1380 i386_cpu_flags x = t->cpu_flags;
1381 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1382
1383 x.bitfield.cpu64 = 0;
1384 x.bitfield.cpuno64 = 0;
1385
0dfbf9d7 1386 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1387 {
1388 /* This instruction is available on all archs. */
1389 match |= CPU_FLAGS_32BIT_MATCH;
1390 }
3629bb00
L		 1391 else
1392 {
c0f3af97 1393 /* This instruction is available only on some archs. */
3629bb00
L		 1394 i386_cpu_flags cpu = cpu_arch_flags;
1395
1396 cpu.bitfield.cpu64 = 0;
1397 cpu.bitfield.cpuno64 = 0;
1398 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1399 if (!cpu_flags_all_zero (&cpu))
1400 {
a5ff0eb2
L		 1401 if (x.bitfield.cpuavx)
1402 {
ce2f5b3c 1403 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1404 if (cpu.bitfield.cpuavx)
1405 {
1406 /* Check SSE2AVX. */
1407 if (!t->opcode_modifier.sse2avx|| sse2avx)
1408 {
1409 match |= (CPU_FLAGS_ARCH_MATCH
1410 | CPU_FLAGS_AVX_MATCH);
1411 /* Check AES. */
1412 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1413 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1414 /* Check PCLMUL. */
1415 if (!x.bitfield.cpupclmul
1416 || cpu.bitfield.cpupclmul)
1417 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1418 }
1419 }
1420 else
1421 match |= CPU_FLAGS_ARCH_MATCH;
1422 }
1423 else
c0f3af97
L		 1424 match |= CPU_FLAGS_32BIT_MATCH;
1425 }
3629bb00 1426 }
c0f3af97 1427 return match;
40fb9820
L		 1428}
1429
c6fb90c8
L		 1430static INLINE i386_operand_type
1431operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1432{
c6fb90c8
L		 1433 switch (ARRAY_SIZE (x.array))
1434 {
1435 case 3:
1436 x.array [2] &= y.array [2];
1437 case 2:
1438 x.array [1] &= y.array [1];
1439 case 1:
1440 x.array [0] &= y.array [0];
1441 break;
1442 default:
1443 abort ();
1444 }
1445 return x;
40fb9820
L		 1446}
1447
c6fb90c8
L		 1448static INLINE i386_operand_type
1449operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1450{
c6fb90c8 1451 switch (ARRAY_SIZE (x.array))
40fb9820 1452 {
c6fb90c8
L		 1453 case 3:
1454 x.array [2] |= y.array [2];
1455 case 2:
1456 x.array [1] |= y.array [1];
1457 case 1:
1458 x.array [0] |= y.array [0];
40fb9820
L		 1459 break;
1460 default:
1461 abort ();
1462 }
c6fb90c8
L		 1463 return x;
1464}
40fb9820 1465
c6fb90c8
L		 1466static INLINE i386_operand_type
1467operand_type_xor (i386_operand_type x, i386_operand_type y)
1468{
1469 switch (ARRAY_SIZE (x.array))
1470 {
1471 case 3:
1472 x.array [2] ^= y.array [2];
1473 case 2:
1474 x.array [1] ^= y.array [1];
1475 case 1:
1476 x.array [0] ^= y.array [0];
1477 break;
1478 default:
1479 abort ();
1480 }
40fb9820
L		 1481 return x;
1482}
1483
1484static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1485static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1486static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1487static const i386_operand_type inoutportreg
1488 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1489static const i386_operand_type reg16_inoutportreg
1490 = OPERAND_TYPE_REG16_INOUTPORTREG;
1491static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1492static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1493static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1494static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1495static const i386_operand_type anydisp
1496 = OPERAND_TYPE_ANYDISP;
40fb9820 1497static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1498static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1499static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1500static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1501static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1502static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1503static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1504static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1505static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1506static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1507static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1508static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1509
1510enum operand_type
1511{
1512 reg,
40fb9820
L		 1513 imm,
1514 disp,
1515 anymem
1516};
1517
c6fb90c8 1518static INLINE int
40fb9820
L		 1519operand_type_check (i386_operand_type t, enum operand_type c)
1520{
1521 switch (c)
1522 {
1523 case reg:
1524 return (t.bitfield.reg8
1525 || t.bitfield.reg16
1526 || t.bitfield.reg32
1527 || t.bitfield.reg64);
1528
40fb9820
L		 1529 case imm:
1530 return (t.bitfield.imm8
1531 || t.bitfield.imm8s
1532 || t.bitfield.imm16
1533 || t.bitfield.imm32
1534 || t.bitfield.imm32s
1535 || t.bitfield.imm64);
1536
1537 case disp:
1538 return (t.bitfield.disp8
1539 || t.bitfield.disp16
1540 || t.bitfield.disp32
1541 || t.bitfield.disp32s
1542 || t.bitfield.disp64);
1543
1544 case anymem:
1545 return (t.bitfield.disp8
1546 || t.bitfield.disp16
1547 || t.bitfield.disp32
1548 || t.bitfield.disp32s
1549 || t.bitfield.disp64
1550 || t.bitfield.baseindex);
1551
1552 default:
1553 abort ();
1554 }
2cfe26b6
AM		 1555
1556 return 0;
40fb9820
L		 1557}
1558
5c07affc
L		 1559/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1560 operand J for instruction template T. */
1561
1562static INLINE int
d3ce72d0 1563match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1564{
1565 return !((i.types[j].bitfield.byte
1566 && !t->operand_types[j].bitfield.byte)
1567 || (i.types[j].bitfield.word
1568 && !t->operand_types[j].bitfield.word)
1569 || (i.types[j].bitfield.dword
1570 && !t->operand_types[j].bitfield.dword)
1571 || (i.types[j].bitfield.qword
1572 && !t->operand_types[j].bitfield.qword));
1573}
1574
1575/* Return 1 if there is no conflict in any size on operand J for
1576 instruction template T. */
1577
1578static INLINE int
d3ce72d0 1579match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1580{
1581 return (match_reg_size (t, j)
1582 && !((i.types[j].bitfield.unspecified
1583 && !t->operand_types[j].bitfield.unspecified)
1584 || (i.types[j].bitfield.fword
1585 && !t->operand_types[j].bitfield.fword)
1586 || (i.types[j].bitfield.tbyte
1587 && !t->operand_types[j].bitfield.tbyte)
1588 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1589 && !t->operand_types[j].bitfield.xmmword)
1590 || (i.types[j].bitfield.ymmword
1591 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1592}
1593
1594/* Return 1 if there is no size conflict on any operands for
1595 instruction template T. */
1596
1597static INLINE int
d3ce72d0 1598operand_size_match (const insn_template *t)
5c07affc
L		 1599{
1600 unsigned int j;
1601 int match = 1;
1602
1603 /* Don't check jump instructions. */
1604 if (t->opcode_modifier.jump
1605 || t->opcode_modifier.jumpbyte
1606 || t->opcode_modifier.jumpdword
1607 || t->opcode_modifier.jumpintersegment)
1608 return match;
1609
1610 /* Check memory and accumulator operand size. */
1611 for (j = 0; j < i.operands; j++)
1612 {
1613 if (t->operand_types[j].bitfield.anysize)
1614 continue;
1615
1616 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1617 {
1618 match = 0;
1619 break;
1620 }
1621
1622 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1623 {
1624 match = 0;
1625 break;
1626 }
1627 }
1628
891edac4 1629 if (match)
5c07affc 1630 return match;
891edac4
L		 1631 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1632 {
1633mismatch:
86e026a4 1634 i.error = operand_size_mismatch;
891edac4
L		 1635 return 0;
1636 }
5c07affc
L		 1637
1638 /* Check reverse. */
9c2799c2 1639 gas_assert (i.operands == 2);
5c07affc
L		 1640
1641 match = 1;
1642 for (j = 0; j < 2; j++)
1643 {
1644 if (t->operand_types[j].bitfield.acc
1645 && !match_reg_size (t, j ? 0 : 1))
891edac4 1646 goto mismatch;
5c07affc
L		 1647
1648 if (i.types[j].bitfield.mem
1649 && !match_mem_size (t, j ? 0 : 1))
891edac4 1650 goto mismatch;
5c07affc
L		 1651 }
1652
1653 return match;
1654}
1655
c6fb90c8 1656static INLINE int
40fb9820
L		 1657operand_type_match (i386_operand_type overlap,
1658 i386_operand_type given)
1659{
1660 i386_operand_type temp = overlap;
1661
1662 temp.bitfield.jumpabsolute = 0;
7d5e4556 1663 temp.bitfield.unspecified = 0;
5c07affc
L		 1664 temp.bitfield.byte = 0;
1665 temp.bitfield.word = 0;
1666 temp.bitfield.dword = 0;
1667 temp.bitfield.fword = 0;
1668 temp.bitfield.qword = 0;
1669 temp.bitfield.tbyte = 0;
1670 temp.bitfield.xmmword = 0;
c0f3af97 1671 temp.bitfield.ymmword = 0;
0dfbf9d7 1672 if (operand_type_all_zero (&temp))
891edac4 1673 goto mismatch;
40fb9820 1674
891edac4
L		 1675 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1676 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1677 return 1;
1678
1679mismatch:
a65babc9 1680 i.error = operand_type_mismatch;
891edac4 1681 return 0;
40fb9820
L		 1682}
1683
7d5e4556 1684/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1685 unless the expected operand type register overlap is null.
1686 Note that Acc in a template matches every size of reg. */
1687
c6fb90c8 1688static INLINE int
40fb9820
L		 1689operand_type_register_match (i386_operand_type m0,
1690 i386_operand_type g0,
1691 i386_operand_type t0,
1692 i386_operand_type m1,
1693 i386_operand_type g1,
1694 i386_operand_type t1)
1695{
1696 if (!operand_type_check (g0, reg))
1697 return 1;
1698
1699 if (!operand_type_check (g1, reg))
1700 return 1;
1701
1702 if (g0.bitfield.reg8 == g1.bitfield.reg8
1703 && g0.bitfield.reg16 == g1.bitfield.reg16
1704 && g0.bitfield.reg32 == g1.bitfield.reg32
1705 && g0.bitfield.reg64 == g1.bitfield.reg64)
1706 return 1;
1707
1708 if (m0.bitfield.acc)
1709 {
1710 t0.bitfield.reg8 = 1;
1711 t0.bitfield.reg16 = 1;
1712 t0.bitfield.reg32 = 1;
1713 t0.bitfield.reg64 = 1;
1714 }
1715
1716 if (m1.bitfield.acc)
1717 {
1718 t1.bitfield.reg8 = 1;
1719 t1.bitfield.reg16 = 1;
1720 t1.bitfield.reg32 = 1;
1721 t1.bitfield.reg64 = 1;
1722 }
1723
891edac4
L		 1724 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1725 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1726 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1727 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1728 return 1;
1729
a65babc9 1730 i.error = register_type_mismatch;
891edac4
L		 1731
1732 return 0;
40fb9820
L		 1733}
1734
252b5132 1735static INLINE unsigned int
40fb9820 1736mode_from_disp_size (i386_operand_type t)
252b5132 1737{
40fb9820
L		 1738 if (t.bitfield.disp8)
1739 return 1;
1740 else if (t.bitfield.disp16
1741 || t.bitfield.disp32
1742 || t.bitfield.disp32s)
1743 return 2;
1744 else
1745 return 0;
252b5132
RH		 1746}
1747
1748static INLINE int
e3bb37b5 1749fits_in_signed_byte (offsetT num)
252b5132
RH		 1750{
1751 return (num >= -128) && (num <= 127);
47926f60 1752}
252b5132
RH		 1753
1754static INLINE int
e3bb37b5 1755fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1756{
1757 return (num & 0xff) == num;
47926f60 1758}
252b5132
RH		 1759
1760static INLINE int
e3bb37b5 1761fits_in_unsigned_word (offsetT num)
252b5132
RH		 1762{
1763 return (num & 0xffff) == num;
47926f60 1764}
252b5132
RH		 1765
1766static INLINE int
e3bb37b5 1767fits_in_signed_word (offsetT num)
252b5132
RH		 1768{
1769 return (-32768 <= num) && (num <= 32767);
47926f60 1770}
2a962e6d 1771
3e73aa7c 1772static INLINE int
e3bb37b5 1773fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1774{
1775#ifndef BFD64
1776 return 1;
1777#else
1778 return (!(((offsetT) -1 << 31) & num)
1779 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1780#endif
1781} /* fits_in_signed_long() */
2a962e6d 1782
3e73aa7c 1783static INLINE int
e3bb37b5 1784fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1785{
1786#ifndef BFD64
1787 return 1;
1788#else
1789 return (num & (((offsetT) 2 << 31) - 1)) == num;
1790#endif
1791} /* fits_in_unsigned_long() */
252b5132 1792
a683cc34
SP		 1793static INLINE int
1794fits_in_imm4 (offsetT num)
1795{
1796 return (num & 0xf) == num;
1797}
1798
40fb9820 1799static i386_operand_type
e3bb37b5 1800smallest_imm_type (offsetT num)
252b5132 1801{
40fb9820 1802 i386_operand_type t;
7ab9ffdd 1803
0dfbf9d7 1804 operand_type_set (&t, 0);
40fb9820
L		 1805 t.bitfield.imm64 = 1;
1806
1807 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1808 {
1809 /* This code is disabled on the 486 because all the Imm1 forms
1810 in the opcode table are slower on the i486. They're the
1811 versions with the implicitly specified single-position
1812 displacement, which has another syntax if you really want to
1813 use that form. */
40fb9820
L		 1814 t.bitfield.imm1 = 1;
1815 t.bitfield.imm8 = 1;
1816 t.bitfield.imm8s = 1;
1817 t.bitfield.imm16 = 1;
1818 t.bitfield.imm32 = 1;
1819 t.bitfield.imm32s = 1;
1820 }
1821 else if (fits_in_signed_byte (num))
1822 {
1823 t.bitfield.imm8 = 1;
1824 t.bitfield.imm8s = 1;
1825 t.bitfield.imm16 = 1;
1826 t.bitfield.imm32 = 1;
1827 t.bitfield.imm32s = 1;
1828 }
1829 else if (fits_in_unsigned_byte (num))
1830 {
1831 t.bitfield.imm8 = 1;
1832 t.bitfield.imm16 = 1;
1833 t.bitfield.imm32 = 1;
1834 t.bitfield.imm32s = 1;
1835 }
1836 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1837 {
1838 t.bitfield.imm16 = 1;
1839 t.bitfield.imm32 = 1;
1840 t.bitfield.imm32s = 1;
1841 }
1842 else if (fits_in_signed_long (num))
1843 {
1844 t.bitfield.imm32 = 1;
1845 t.bitfield.imm32s = 1;
1846 }
1847 else if (fits_in_unsigned_long (num))
1848 t.bitfield.imm32 = 1;
1849
1850 return t;
47926f60 1851}
252b5132 1852
847f7ad4 1853static offsetT
e3bb37b5 1854offset_in_range (offsetT val, int size)
847f7ad4 1855{
508866be 1856 addressT mask;
ba2adb93 1857
847f7ad4
AM		 1858 switch (size)
1859 {
508866be
L		 1860 case 1: mask = ((addressT) 1 << 8) - 1; break;
1861 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1862 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1863#ifdef BFD64
1864 case 8: mask = ((addressT) 2 << 63) - 1; break;
1865#endif
47926f60 1866 default: abort ();
847f7ad4
AM		 1867 }
1868
9de868bf
L		 1869#ifdef BFD64
1870 /* If BFD64, sign extend val for 32bit address mode. */
1871 if (flag_code != CODE_64BIT
1872 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 1873 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1874 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 1875#endif
ba2adb93 1876
47926f60 1877 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1878 {
1879 char buf1[40], buf2[40];
1880
1881 sprint_value (buf1, val);
1882 sprint_value (buf2, val & mask);
1883 as_warn (_("%s shortened to %s"), buf1, buf2);
1884 }
1885 return val & mask;
1886}
1887
c32fa91d
L		 1888enum PREFIX_GROUP
1889{
1890 PREFIX_EXIST = 0,
1891 PREFIX_LOCK,
1892 PREFIX_REP,
1893 PREFIX_OTHER
1894};
1895
1896/* Returns
1897 a. PREFIX_EXIST if attempting to add a prefix where one from the
1898 same class already exists.
1899 b. PREFIX_LOCK if lock prefix is added.
1900 c. PREFIX_REP if rep/repne prefix is added.
1901 d. PREFIX_OTHER if other prefix is added.
1902 */
1903
1904static enum PREFIX_GROUP
e3bb37b5 1905add_prefix (unsigned int prefix)
252b5132 1906{
c32fa91d 1907 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 1908 unsigned int q;
252b5132 1909
29b0f896
AM		 1910 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1911 && flag_code == CODE_64BIT)
b1905489 1912 {
161a04f6
L		 1913 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1914 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1915 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 1916 ret = PREFIX_EXIST;
b1905489
JB		 1917 q = REX_PREFIX;
1918 }
3e73aa7c 1919 else
b1905489
JB		 1920 {
1921 switch (prefix)
1922 {
1923 default:
1924 abort ();
1925
1926 case CS_PREFIX_OPCODE:
1927 case DS_PREFIX_OPCODE:
1928 case ES_PREFIX_OPCODE:
1929 case FS_PREFIX_OPCODE:
1930 case GS_PREFIX_OPCODE:
1931 case SS_PREFIX_OPCODE:
1932 q = SEG_PREFIX;
1933 break;
1934
1935 case REPNE_PREFIX_OPCODE:
1936 case REPE_PREFIX_OPCODE:
c32fa91d
L		 1937 q = REP_PREFIX;
1938 ret = PREFIX_REP;
1939 break;
1940
b1905489 1941 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 1942 q = LOCK_PREFIX;
1943 ret = PREFIX_LOCK;
b1905489
JB		 1944 break;
1945
1946 case FWAIT_OPCODE:
1947 q = WAIT_PREFIX;
1948 break;
1949
1950 case ADDR_PREFIX_OPCODE:
1951 q = ADDR_PREFIX;
1952 break;
1953
1954 case DATA_PREFIX_OPCODE:
1955 q = DATA_PREFIX;
1956 break;
1957 }
1958 if (i.prefix[q] != 0)
c32fa91d 1959 ret = PREFIX_EXIST;
b1905489 1960 }
252b5132 1961
b1905489 1962 if (ret)
252b5132 1963 {
b1905489
JB		 1964 if (!i.prefix[q])
1965 ++i.prefixes;
1966 i.prefix[q] |= prefix;
252b5132 1967 }
b1905489
JB		 1968 else
1969 as_bad (_("same type of prefix used twice"));
252b5132 1970
252b5132
RH		 1971 return ret;
1972}
1973
1974static void
78f12dd3 1975update_code_flag (int value, int check)
eecb386c 1976{
78f12dd3
L		 1977 PRINTF_LIKE ((*as_error));
1978
1e9cc1c2 1979 flag_code = (enum flag_code) value;
40fb9820
L		 1980 if (flag_code == CODE_64BIT)
1981 {
1982 cpu_arch_flags.bitfield.cpu64 = 1;
1983 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1984 }
1985 else
1986 {
1987 cpu_arch_flags.bitfield.cpu64 = 0;
1988 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1989 }
1990 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 1991 {
78f12dd3
L		 1992 if (check)
1993 as_error = as_fatal;
1994 else
1995 as_error = as_bad;
1996 (*as_error) (_("64bit mode not supported on `%s'."),
1997 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 1998 }
40fb9820 1999 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2000 {
78f12dd3
L		 2001 if (check)
2002 as_error = as_fatal;
2003 else
2004 as_error = as_bad;
2005 (*as_error) (_("32bit mode not supported on `%s'."),
2006 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2007 }
eecb386c
AM		 2008 stackop_size = '\0';
2009}
2010
78f12dd3
L		 2011static void
2012set_code_flag (int value)
2013{
2014 update_code_flag (value, 0);
2015}
2016
eecb386c 2017static void
e3bb37b5 2018set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2019{
1e9cc1c2 2020 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2021 if (flag_code != CODE_16BIT)
2022 abort ();
2023 cpu_arch_flags.bitfield.cpu64 = 0;
2024 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2025 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2026}
2027
2028static void
e3bb37b5 2029set_intel_syntax (int syntax_flag)
252b5132
RH		 2030{
2031 /* Find out if register prefixing is specified. */
2032 int ask_naked_reg = 0;
2033
2034 SKIP_WHITESPACE ();
29b0f896 2035 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2036 {
2037 char *string = input_line_pointer;
2038 int e = get_symbol_end ();
2039
47926f60 2040 if (strcmp (string, "prefix") == 0)
252b5132 2041 ask_naked_reg = 1;
47926f60 2042 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2043 ask_naked_reg = -1;
2044 else
d0b47220 2045 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2046 *input_line_pointer = e;
2047 }
2048 demand_empty_rest_of_line ();
c3332e24 2049
252b5132
RH		 2050 intel_syntax = syntax_flag;
2051
2052 if (ask_naked_reg == 0)
f86103b7
AM		 2053 allow_naked_reg = (intel_syntax
2054 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2055 else
2056 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2057
ee86248c 2058 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2059
e4a3b5a4 2060 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2061 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2062 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2063}
2064
1efbbeb4
L		 2065static void
2066set_intel_mnemonic (int mnemonic_flag)
2067{
e1d4d893 2068 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2069}
2070
db51cc60
L		 2071static void
2072set_allow_index_reg (int flag)
2073{
2074 allow_index_reg = flag;
2075}
2076
cb19c032
L		 2077static void
2078set_sse_check (int dummy ATTRIBUTE_UNUSED)
2079{
2080 SKIP_WHITESPACE ();
2081
2082 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2083 {
2084 char *string = input_line_pointer;
2085 int e = get_symbol_end ();
2086
2087 if (strcmp (string, "none") == 0)
2088 sse_check = sse_check_none;
2089 else if (strcmp (string, "warning") == 0)
2090 sse_check = sse_check_warning;
2091 else if (strcmp (string, "error") == 0)
2092 sse_check = sse_check_error;
2093 else
2094 as_bad (_("bad argument to sse_check directive."));
2095 *input_line_pointer = e;
2096 }
2097 else
2098 as_bad (_("missing argument for sse_check directive"));
2099
2100 demand_empty_rest_of_line ();
2101}
2102
8a9036a4
L		 2103static void
2104check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2105 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2106{
2107#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2108 static const char *arch;
2109
2110 /* Intel LIOM is only supported on ELF. */
2111 if (!IS_ELF)
2112 return;
2113
2114 if (!arch)
2115 {
2116 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2117 use default_arch. */
2118 arch = cpu_arch_name;
2119 if (!arch)
2120 arch = default_arch;
2121 }
2122
3632d14b 2123 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2124 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2125 || new_flag.bitfield.cpul1om)
8a9036a4 2126 return;
76ba9986 2127
8a9036a4
L		 2128 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2129#endif
2130}
2131
e413e4e9 2132static void
e3bb37b5 2133set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2134{
47926f60 2135 SKIP_WHITESPACE ();
e413e4e9 2136
29b0f896 2137 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2138 {
2139 char *string = input_line_pointer;
2140 int e = get_symbol_end ();
91d6fa6a 2141 unsigned int j;
40fb9820 2142 i386_cpu_flags flags;
e413e4e9 2143
91d6fa6a 2144 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2145 {
91d6fa6a 2146 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2147 {
91d6fa6a 2148 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2149
5c6af06e
JB		 2150 if (*string != '.')
2151 {
91d6fa6a 2152 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2153 cpu_sub_arch_name = NULL;
91d6fa6a 2154 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2155 if (flag_code == CODE_64BIT)
2156 {
2157 cpu_arch_flags.bitfield.cpu64 = 1;
2158 cpu_arch_flags.bitfield.cpuno64 = 0;
2159 }
2160 else
2161 {
2162 cpu_arch_flags.bitfield.cpu64 = 0;
2163 cpu_arch_flags.bitfield.cpuno64 = 1;
2164 }
91d6fa6a
NC		 2165 cpu_arch_isa = cpu_arch[j].type;
2166 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2167 if (!cpu_arch_tune_set)
2168 {
2169 cpu_arch_tune = cpu_arch_isa;
2170 cpu_arch_tune_flags = cpu_arch_isa_flags;
2171 }
5c6af06e
JB		 2172 break;
2173 }
40fb9820 2174
22109423 2175 if (!cpu_arch[j].negated)
309d3373 2176 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2177 cpu_arch[j].flags);
309d3373
JB		 2178 else
2179 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2180 cpu_arch[j].flags);
0dfbf9d7 2181 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2182 {
6305a203
L		 2183 if (cpu_sub_arch_name)
2184 {
2185 char *name = cpu_sub_arch_name;
2186 cpu_sub_arch_name = concat (name,
91d6fa6a 2187 cpu_arch[j].name,
1bf57e9f 2188 (const char *) NULL);
6305a203
L		 2189 free (name);
2190 }
2191 else
91d6fa6a 2192 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2193 cpu_arch_flags = flags;
a586129e 2194 cpu_arch_isa_flags = flags;
5c6af06e
JB		 2195 }
2196 *input_line_pointer = e;
2197 demand_empty_rest_of_line ();
2198 return;
e413e4e9
AM		 2199 }
2200 }
91d6fa6a 2201 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2202 as_bad (_("no such architecture: `%s'"), string);
2203
2204 *input_line_pointer = e;
2205 }
2206 else
2207 as_bad (_("missing cpu architecture"));
2208
fddf5b5b
AM		 2209 no_cond_jump_promotion = 0;
2210 if (*input_line_pointer == ','
29b0f896 2211 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2212 {
2213 char *string = ++input_line_pointer;
2214 int e = get_symbol_end ();
2215
2216 if (strcmp (string, "nojumps") == 0)
2217 no_cond_jump_promotion = 1;
2218 else if (strcmp (string, "jumps") == 0)
2219 ;
2220 else
2221 as_bad (_("no such architecture modifier: `%s'"), string);
2222
2223 *input_line_pointer = e;
2224 }
2225
e413e4e9
AM		 2226 demand_empty_rest_of_line ();
2227}
2228
8a9036a4
L		 2229enum bfd_architecture
2230i386_arch (void)
2231{
3632d14b 2232 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2233 {
2234 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2235 || flag_code != CODE_64BIT)
2236 as_fatal (_("Intel L1OM is 64bit ELF only"));
2237 return bfd_arch_l1om;
2238 }
2239 else
2240 return bfd_arch_i386;
2241}
2242
b9d79e03 2243unsigned long
7016a5d5 2244i386_mach (void)
b9d79e03 2245{
351f65ca 2246 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2247 {
3632d14b 2248 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2249 {
351f65ca
L		 2250 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2251 || default_arch[6] != '\0')
8a9036a4
L		 2252 as_fatal (_("Intel L1OM is 64bit ELF only"));
2253 return bfd_mach_l1om;
2254 }
351f65ca 2255 else if (default_arch[6] == '\0')
8a9036a4 2256 return bfd_mach_x86_64;
351f65ca
L		 2257 else
2258 return bfd_mach_x64_32;
8a9036a4 2259 }
b9d79e03
JH		 2260 else if (!strcmp (default_arch, "i386"))
2261 return bfd_mach_i386_i386;
2262 else
2b5d6a91 2263 as_fatal (_("unknown architecture"));
b9d79e03 2264}
b9d79e03 2265\f
252b5132 2266void
7016a5d5 2267md_begin (void)
252b5132
RH		 2268{
2269 const char *hash_err;
2270
47926f60 2271 /* Initialize op_hash hash table. */
252b5132
RH		 2272 op_hash = hash_new ();
2273
2274 {
d3ce72d0 2275 const insn_template *optab;
29b0f896 2276 templates *core_optab;
252b5132 2277
47926f60
KH		 2278 /* Setup for loop. */
2279 optab = i386_optab;
252b5132
RH		 2280 core_optab = (templates *) xmalloc (sizeof (templates));
2281 core_optab->start = optab;
2282
2283 while (1)
2284 {
2285 ++optab;
2286 if (optab->name == NULL
2287 || strcmp (optab->name, (optab - 1)->name) != 0)
2288 {
2289 /* different name --> ship out current template list;
47926f60 2290 add to hash table; & begin anew. */
252b5132
RH		 2291 core_optab->end = optab;
2292 hash_err = hash_insert (op_hash,
2293 (optab - 1)->name,
5a49b8ac 2294 (void *) core_optab);
252b5132
RH		 2295 if (hash_err)
2296 {
2b5d6a91 2297 as_fatal (_("internal Error: Can't hash %s: %s"),
252b5132
RH		 2298 (optab - 1)->name,
2299 hash_err);
2300 }
2301 if (optab->name == NULL)
2302 break;
2303 core_optab = (templates *) xmalloc (sizeof (templates));
2304 core_optab->start = optab;
2305 }
2306 }
2307 }
2308
47926f60 2309 /* Initialize reg_hash hash table. */
252b5132
RH		 2310 reg_hash = hash_new ();
2311 {
29b0f896 2312 const reg_entry *regtab;
c3fe08fa 2313 unsigned int regtab_size = i386_regtab_size;
252b5132 2314
c3fe08fa 2315 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2316 {
5a49b8ac 2317 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2318 if (hash_err)
2b5d6a91 2319 as_fatal (_("internal Error: Can't hash %s: %s"),
3e73aa7c
JH		 2320 regtab->reg_name,
2321 hash_err);
252b5132
RH		 2322 }
2323 }
2324
47926f60 2325 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2326 {
29b0f896
AM		 2327 int c;
2328 char *p;
252b5132
RH		 2329
2330 for (c = 0; c < 256; c++)
2331 {
3882b010 2332 if (ISDIGIT (c))
252b5132
RH		 2333 {
2334 digit_chars[c] = c;
2335 mnemonic_chars[c] = c;
2336 register_chars[c] = c;
2337 operand_chars[c] = c;
2338 }
3882b010 2339 else if (ISLOWER (c))
252b5132
RH		 2340 {
2341 mnemonic_chars[c] = c;
2342 register_chars[c] = c;
2343 operand_chars[c] = c;
2344 }
3882b010 2345 else if (ISUPPER (c))
252b5132 2346 {
3882b010 2347 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2348 register_chars[c] = mnemonic_chars[c];
2349 operand_chars[c] = c;
2350 }
2351
3882b010 2352 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2353 identifier_chars[c] = c;
2354 else if (c >= 128)
2355 {
2356 identifier_chars[c] = c;
2357 operand_chars[c] = c;
2358 }
2359 }
2360
2361#ifdef LEX_AT
2362 identifier_chars['@'] = '@';
32137342
NC		 2363#endif
2364#ifdef LEX_QM
2365 identifier_chars['?'] = '?';
2366 operand_chars['?'] = '?';
252b5132 2367#endif
252b5132 2368 digit_chars['-'] = '-';
c0f3af97 2369 mnemonic_chars['_'] = '_';
791fe849 2370 mnemonic_chars['-'] = '-';
0003779b 2371 mnemonic_chars['.'] = '.';
252b5132
RH		 2372 identifier_chars['_'] = '_';
2373 identifier_chars['.'] = '.';
2374
2375 for (p = operand_special_chars; *p != '\0'; p++)
2376 operand_chars[(unsigned char) *p] = *p;
2377 }
2378
2379#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2380 if (IS_ELF)
252b5132
RH		 2381 {
2382 record_alignment (text_section, 2);
2383 record_alignment (data_section, 2);
2384 record_alignment (bss_section, 2);
2385 }
2386#endif
a4447b93
RH		 2387
2388 if (flag_code == CODE_64BIT)
2389 {
ca19b261
KT		 2390#if defined (OBJ_COFF) && defined (TE_PE)
2391 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2392 ? 32 : 16);
2393#else
a4447b93 2394 x86_dwarf2_return_column = 16;
ca19b261 2395#endif
61ff971f 2396 x86_cie_data_alignment = -8;
a4447b93
RH		 2397 }
2398 else
2399 {
2400 x86_dwarf2_return_column = 8;
2401 x86_cie_data_alignment = -4;
2402 }
252b5132
RH		 2403}
2404
2405void
e3bb37b5 2406i386_print_statistics (FILE *file)
252b5132
RH		 2407{
2408 hash_print_statistics (file, "i386 opcode", op_hash);
2409 hash_print_statistics (file, "i386 register", reg_hash);
2410}
2411\f
252b5132
RH		 2412#ifdef DEBUG386
2413
ce8a8b2f 2414/* Debugging routines for md_assemble. */
d3ce72d0 2415static void pte (insn_template *);
40fb9820 2416static void pt (i386_operand_type);
e3bb37b5
L		 2417static void pe (expressionS *);
2418static void ps (symbolS *);
252b5132
RH		 2419
2420static void
e3bb37b5 2421pi (char *line, i386_insn *x)
252b5132 2422{
09137c09 2423 unsigned int j;
252b5132
RH		 2424
2425 fprintf (stdout, "%s: template ", line);
2426 pte (&x->tm);
09f131f2
JH		 2427 fprintf (stdout, " address: base %s index %s scale %x\n",
2428 x->base_reg ? x->base_reg->reg_name : "none",
2429 x->index_reg ? x->index_reg->reg_name : "none",
2430 x->log2_scale_factor);
2431 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2432 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2433 fprintf (stdout, " sib: base %x index %x scale %x\n",
2434 x->sib.base, x->sib.index, x->sib.scale);
2435 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2436 (x->rex & REX_W) != 0,
2437 (x->rex & REX_R) != 0,
2438 (x->rex & REX_X) != 0,
2439 (x->rex & REX_B) != 0);
09137c09 2440 for (j = 0; j < x->operands; j++)
252b5132 2441 {
09137c09
SP		 2442 fprintf (stdout, " #%d: ", j + 1);
2443 pt (x->types[j]);
252b5132 2444 fprintf (stdout, "\n");
09137c09
SP		 2445 if (x->types[j].bitfield.reg8
2446 || x->types[j].bitfield.reg16
2447 || x->types[j].bitfield.reg32
2448 || x->types[j].bitfield.reg64
2449 || x->types[j].bitfield.regmmx
2450 || x->types[j].bitfield.regxmm
2451 || x->types[j].bitfield.regymm
2452 || x->types[j].bitfield.sreg2
2453 || x->types[j].bitfield.sreg3
2454 || x->types[j].bitfield.control
2455 || x->types[j].bitfield.debug
2456 || x->types[j].bitfield.test)
2457 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2458 if (operand_type_check (x->types[j], imm))
2459 pe (x->op[j].imms);
2460 if (operand_type_check (x->types[j], disp))
2461 pe (x->op[j].disps);
252b5132
RH		 2462 }
2463}
2464
2465static void
d3ce72d0 2466pte (insn_template *t)
252b5132 2467{
09137c09 2468 unsigned int j;
252b5132 2469 fprintf (stdout, " %d operands ", t->operands);
47926f60 2470 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2471 if (t->extension_opcode != None)
2472 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2473 if (t->opcode_modifier.d)
252b5132 2474 fprintf (stdout, "D");
40fb9820 2475 if (t->opcode_modifier.w)
252b5132
RH		 2476 fprintf (stdout, "W");
2477 fprintf (stdout, "\n");
09137c09 2478 for (j = 0; j < t->operands; j++)
252b5132 2479 {
09137c09
SP		 2480 fprintf (stdout, " #%d type ", j + 1);
2481 pt (t->operand_types[j]);
252b5132
RH		 2482 fprintf (stdout, "\n");
2483 }
2484}
2485
2486static void
e3bb37b5 2487pe (expressionS *e)
252b5132 2488{
24eab124 2489 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2490 fprintf (stdout, " add_number %ld (%lx)\n",
2491 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2492 if (e->X_add_symbol)
2493 {
2494 fprintf (stdout, " add_symbol ");
2495 ps (e->X_add_symbol);
2496 fprintf (stdout, "\n");
2497 }
2498 if (e->X_op_symbol)
2499 {
2500 fprintf (stdout, " op_symbol ");
2501 ps (e->X_op_symbol);
2502 fprintf (stdout, "\n");
2503 }
2504}
2505
2506static void
e3bb37b5 2507ps (symbolS *s)
252b5132
RH		 2508{
2509 fprintf (stdout, "%s type %s%s",
2510 S_GET_NAME (s),
2511 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2512 segment_name (S_GET_SEGMENT (s)));
2513}
2514
7b81dfbb 2515static struct type_name
252b5132 2516 {
40fb9820
L		 2517 i386_operand_type mask;
2518 const char *name;
252b5132 2519 }
7b81dfbb 2520const type_names[] =
252b5132 2521{
40fb9820
L		 2522 { OPERAND_TYPE_REG8, "r8" },
2523 { OPERAND_TYPE_REG16, "r16" },
2524 { OPERAND_TYPE_REG32, "r32" },
2525 { OPERAND_TYPE_REG64, "r64" },
2526 { OPERAND_TYPE_IMM8, "i8" },
2527 { OPERAND_TYPE_IMM8, "i8s" },
2528 { OPERAND_TYPE_IMM16, "i16" },
2529 { OPERAND_TYPE_IMM32, "i32" },
2530 { OPERAND_TYPE_IMM32S, "i32s" },
2531 { OPERAND_TYPE_IMM64, "i64" },
2532 { OPERAND_TYPE_IMM1, "i1" },
2533 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2534 { OPERAND_TYPE_DISP8, "d8" },
2535 { OPERAND_TYPE_DISP16, "d16" },
2536 { OPERAND_TYPE_DISP32, "d32" },
2537 { OPERAND_TYPE_DISP32S, "d32s" },
2538 { OPERAND_TYPE_DISP64, "d64" },
2539 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2540 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2541 { OPERAND_TYPE_CONTROL, "control reg" },
2542 { OPERAND_TYPE_TEST, "test reg" },
2543 { OPERAND_TYPE_DEBUG, "debug reg" },
2544 { OPERAND_TYPE_FLOATREG, "FReg" },
2545 { OPERAND_TYPE_FLOATACC, "FAcc" },
2546 { OPERAND_TYPE_SREG2, "SReg2" },
2547 { OPERAND_TYPE_SREG3, "SReg3" },
2548 { OPERAND_TYPE_ACC, "Acc" },
2549 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2550 { OPERAND_TYPE_REGMMX, "rMMX" },
2551 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2552 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2553 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2554};
2555
2556static void
40fb9820 2557pt (i386_operand_type t)
252b5132 2558{
40fb9820 2559 unsigned int j;
c6fb90c8 2560 i386_operand_type a;
252b5132 2561
40fb9820 2562 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2563 {
2564 a = operand_type_and (t, type_names[j].mask);
0349dc08 2565 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2566 fprintf (stdout, "%s, ", type_names[j].name);
2567 }
252b5132
RH		 2568 fflush (stdout);
2569}
2570
2571#endif /* DEBUG386 */
2572\f
252b5132 2573static bfd_reloc_code_real_type
3956db08 2574reloc (unsigned int size,
64e74474
AM		 2575 int pcrel,
2576 int sign,
2577 bfd_reloc_code_real_type other)
252b5132 2578{
47926f60 2579 if (other != NO_RELOC)
3956db08 2580 {
91d6fa6a 2581 reloc_howto_type *rel;
3956db08
JB		 2582
2583 if (size == 8)
2584 switch (other)
2585 {
64e74474
AM		 2586 case BFD_RELOC_X86_64_GOT32:
2587 return BFD_RELOC_X86_64_GOT64;
2588 break;
2589 case BFD_RELOC_X86_64_PLTOFF64:
2590 return BFD_RELOC_X86_64_PLTOFF64;
2591 break;
2592 case BFD_RELOC_X86_64_GOTPC32:
2593 other = BFD_RELOC_X86_64_GOTPC64;
2594 break;
2595 case BFD_RELOC_X86_64_GOTPCREL:
2596 other = BFD_RELOC_X86_64_GOTPCREL64;
2597 break;
2598 case BFD_RELOC_X86_64_TPOFF32:
2599 other = BFD_RELOC_X86_64_TPOFF64;
2600 break;
2601 case BFD_RELOC_X86_64_DTPOFF32:
2602 other = BFD_RELOC_X86_64_DTPOFF64;
2603 break;
2604 default:
2605 break;
3956db08 2606 }
e05278af
JB		 2607
2608 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2609 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2610 sign = -1;
2611
91d6fa6a
NC		 2612 rel = bfd_reloc_type_lookup (stdoutput, other);
2613 if (!rel)
3956db08 2614 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2615 else if (size != bfd_get_reloc_size (rel))
3956db08 2616 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2617 bfd_get_reloc_size (rel),
3956db08 2618 size);
91d6fa6a 2619 else if (pcrel && !rel->pc_relative)
3956db08 2620 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2621 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2622 && !sign)
91d6fa6a 2623 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2624 && sign > 0))
3956db08
JB		 2625 as_bad (_("relocated field and relocation type differ in signedness"));
2626 else
2627 return other;
2628 return NO_RELOC;
2629 }
252b5132
RH		 2630
2631 if (pcrel)
2632 {
3e73aa7c 2633 if (!sign)
3956db08 2634 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2635 switch (size)
2636 {
2637 case 1: return BFD_RELOC_8_PCREL;
2638 case 2: return BFD_RELOC_16_PCREL;
2639 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2640 case 8: return BFD_RELOC_64_PCREL;
252b5132 2641 }
3956db08 2642 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2643 }
2644 else
2645 {
3956db08 2646 if (sign > 0)
e5cb08ac 2647 switch (size)
3e73aa7c
JH		 2648 {
2649 case 4: return BFD_RELOC_X86_64_32S;
2650 }
2651 else
2652 switch (size)
2653 {
2654 case 1: return BFD_RELOC_8;
2655 case 2: return BFD_RELOC_16;
2656 case 4: return BFD_RELOC_32;
2657 case 8: return BFD_RELOC_64;
2658 }
3956db08
JB		 2659 as_bad (_("cannot do %s %u byte relocation"),
2660 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2661 }
2662
0cc9e1d3 2663 return NO_RELOC;
252b5132
RH		 2664}
2665
47926f60
KH		 2666/* Here we decide which fixups can be adjusted to make them relative to
2667 the beginning of the section instead of the symbol. Basically we need
2668 to make sure that the dynamic relocations are done correctly, so in
2669 some cases we force the original symbol to be used. */
2670
252b5132 2671int
e3bb37b5 2672tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2673{
6d249963 2674#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2675 if (!IS_ELF)
31312f95
AM		 2676 return 1;
2677
a161fe53
AM		 2678 /* Don't adjust pc-relative references to merge sections in 64-bit
2679 mode. */
2680 if (use_rela_relocations
2681 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2682 && fixP->fx_pcrel)
252b5132 2683 return 0;
31312f95 2684
8d01d9a9
AJ		 2685 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2686 and changed later by validate_fix. */
2687 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2688 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2689 return 0;
2690
ce8a8b2f 2691 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2692 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2693 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2694 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2695 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2696 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2697 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2698 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2699 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2700 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2701 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2702 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2703 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2704 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2705 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2706 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2707 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2708 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2709 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2710 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2711 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2712 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2713 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2714 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2715 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2716 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2717 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2718 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2719 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2720 return 0;
31312f95 2721#endif
252b5132
RH		 2722 return 1;
2723}
252b5132 2724
b4cac588 2725static int
e3bb37b5 2726intel_float_operand (const char *mnemonic)
252b5132 2727{
9306ca4a
JB		 2728 /* Note that the value returned is meaningful only for opcodes with (memory)
2729 operands, hence the code here is free to improperly handle opcodes that
2730 have no operands (for better performance and smaller code). */
2731
2732 if (mnemonic[0] != 'f')
2733 return 0; /* non-math */
2734
2735 switch (mnemonic[1])
2736 {
2737 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2738 the fs segment override prefix not currently handled because no
2739 call path can make opcodes without operands get here */
2740 case 'i':
2741 return 2 /* integer op */;
2742 case 'l':
2743 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2744 return 3; /* fldcw/fldenv */
2745 break;
2746 case 'n':
2747 if (mnemonic[2] != 'o' /* fnop */)
2748 return 3; /* non-waiting control op */
2749 break;
2750 case 'r':
2751 if (mnemonic[2] == 's')
2752 return 3; /* frstor/frstpm */
2753 break;
2754 case 's':
2755 if (mnemonic[2] == 'a')
2756 return 3; /* fsave */
2757 if (mnemonic[2] == 't')
2758 {
2759 switch (mnemonic[3])
2760 {
2761 case 'c': /* fstcw */
2762 case 'd': /* fstdw */
2763 case 'e': /* fstenv */
2764 case 's': /* fsts[gw] */
2765 return 3;
2766 }
2767 }
2768 break;
2769 case 'x':
2770 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2771 return 0; /* fxsave/fxrstor are not really math ops */
2772 break;
2773 }
252b5132 2774
9306ca4a 2775 return 1;
252b5132
RH		 2776}
2777
c0f3af97
L		 2778/* Build the VEX prefix. */
2779
2780static void
d3ce72d0 2781build_vex_prefix (const insn_template *t)
c0f3af97
L		 2782{
2783 unsigned int register_specifier;
2784 unsigned int implied_prefix;
2785 unsigned int vector_length;
2786
2787 /* Check register specifier. */
2788 if (i.vex.register_specifier)
2789 {
2790 register_specifier = i.vex.register_specifier->reg_num;
2791 if ((i.vex.register_specifier->reg_flags & RegRex))
2792 register_specifier += 8;
2793 register_specifier = ~register_specifier & 0xf;
2794 }
2795 else
2796 register_specifier = 0xf;
2797
fa99fab2
L		 2798 /* Use 2-byte VEX prefix by swappping destination and source
2799 operand. */
2800 if (!i.swap_operand
2801 && i.operands == i.reg_operands
7f399153 2802 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 2803 && i.tm.opcode_modifier.s
2804 && i.rex == REX_B)
2805 {
2806 unsigned int xchg = i.operands - 1;
2807 union i386_op temp_op;
2808 i386_operand_type temp_type;
2809
2810 temp_type = i.types[xchg];
2811 i.types[xchg] = i.types[0];
2812 i.types[0] = temp_type;
2813 temp_op = i.op[xchg];
2814 i.op[xchg] = i.op[0];
2815 i.op[0] = temp_op;
2816
9c2799c2 2817 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2818
2819 i.rex = REX_R;
2820 xchg = i.rm.regmem;
2821 i.rm.regmem = i.rm.reg;
2822 i.rm.reg = xchg;
2823
2824 /* Use the next insn. */
2825 i.tm = t[1];
2826 }
2827
539f890d
L		 2828 if (i.tm.opcode_modifier.vex == VEXScalar)
2829 vector_length = avxscalar;
2830 else
2831 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 2832
2833 switch ((i.tm.base_opcode >> 8) & 0xff)
2834 {
2835 case 0:
2836 implied_prefix = 0;
2837 break;
2838 case DATA_PREFIX_OPCODE:
2839 implied_prefix = 1;
2840 break;
2841 case REPE_PREFIX_OPCODE:
2842 implied_prefix = 2;
2843 break;
2844 case REPNE_PREFIX_OPCODE:
2845 implied_prefix = 3;
2846 break;
2847 default:
2848 abort ();
2849 }
2850
2851 /* Use 2-byte VEX prefix if possible. */
7f399153 2852 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 2853 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 2854 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2855 {
2856 /* 2-byte VEX prefix. */
2857 unsigned int r;
2858
2859 i.vex.length = 2;
2860 i.vex.bytes[0] = 0xc5;
2861
2862 /* Check the REX.R bit. */
2863 r = (i.rex & REX_R) ? 0 : 1;
2864 i.vex.bytes[1] = (r << 7
2865 | register_specifier << 3
2866 | vector_length << 2
2867 | implied_prefix);
2868 }
2869 else
2870 {
2871 /* 3-byte VEX prefix. */
2872 unsigned int m, w;
2873
f88c9eb0 2874 i.vex.length = 3;
f88c9eb0 2875
7f399153 2876 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 2877 {
7f399153
L		 2878 case VEX0F:
2879 m = 0x1;
80de6e00 2880 i.vex.bytes[0] = 0xc4;
7f399153
L		 2881 break;
2882 case VEX0F38:
2883 m = 0x2;
80de6e00 2884 i.vex.bytes[0] = 0xc4;
7f399153
L		 2885 break;
2886 case VEX0F3A:
2887 m = 0x3;
80de6e00 2888 i.vex.bytes[0] = 0xc4;
7f399153
L		 2889 break;
2890 case XOP08:
5dd85c99
SP		 2891 m = 0x8;
2892 i.vex.bytes[0] = 0x8f;
7f399153
L		 2893 break;
2894 case XOP09:
f88c9eb0
SP		 2895 m = 0x9;
2896 i.vex.bytes[0] = 0x8f;
7f399153
L		 2897 break;
2898 case XOP0A:
f88c9eb0
SP		 2899 m = 0xa;
2900 i.vex.bytes[0] = 0x8f;
7f399153
L		 2901 break;
2902 default:
2903 abort ();
f88c9eb0 2904 }
c0f3af97 2905
c0f3af97
L		 2906 /* The high 3 bits of the second VEX byte are 1's compliment
2907 of RXB bits from REX. */
2908 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2909
2910 /* Check the REX.W bit. */
2911 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 2912 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 2913 {
2914 if (w)
2915 abort ();
2916
1ef99a7b 2917 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 2918 w = 1;
2919 }
2920
2921 i.vex.bytes[2] = (w << 7
2922 | register_specifier << 3
2923 | vector_length << 2
2924 | implied_prefix);
2925 }
2926}
2927
65da13b5
L		 2928static void
2929process_immext (void)
2930{
2931 expressionS *exp;
2932
2933 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2934 {
1fed0ba1
L		 2935 /* SSE3 Instructions have the fixed operands with an opcode
2936 suffix which is coded in the same place as an 8-bit immediate
2937 field would be. Here we check those operands and remove them
2938 afterwards. */
65da13b5
L		 2939 unsigned int x;
2940
2941 for (x = 0; x < i.operands; x++)
2942 if (i.op[x].regs->reg_num != x)
2943 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2944 register_prefix, i.op[x].regs->reg_name, x + 1,
2945 i.tm.name);
2946
2947 i.operands = 0;
65da13b5
L		 2948 }
2949
c0f3af97 2950 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2951 which is coded in the same place as an 8-bit immediate field
2952 would be. Here we fake an 8-bit immediate operand from the
2953 opcode suffix stored in tm.extension_opcode.
2954
c1e679ec 2955 AVX instructions also use this encoding, for some of
c0f3af97 2956 3 argument instructions. */
65da13b5 2957
9c2799c2 2958 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 2959 && (i.operands <= 2
2960 || (i.tm.opcode_modifier.vex
2961 && i.operands <= 4)));
65da13b5
L		 2962
2963 exp = &im_expressions[i.imm_operands++];
2964 i.op[i.operands].imms = exp;
2965 i.types[i.operands] = imm8;
2966 i.operands++;
2967 exp->X_op = O_constant;
2968 exp->X_add_number = i.tm.extension_opcode;
2969 i.tm.extension_opcode = None;
2970}
2971
252b5132
RH		 2972/* This is the guts of the machine-dependent assembler. LINE points to a
2973 machine dependent instruction. This function is supposed to emit
2974 the frags/bytes it assembles to. */
2975
2976void
65da13b5 2977md_assemble (char *line)
252b5132 2978{
40fb9820 2979 unsigned int j;
252b5132 2980 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 2981 const insn_template *t;
252b5132 2982
47926f60 2983 /* Initialize globals. */
252b5132
RH		 2984 memset (&i, '\0', sizeof (i));
2985 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2986 i.reloc[j] = NO_RELOC;
252b5132
RH		 2987 memset (disp_expressions, '\0', sizeof (disp_expressions));
2988 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2989 save_stack_p = save_stack;
252b5132
RH		 2990
2991 /* First parse an instruction mnemonic & call i386_operand for the operands.
2992 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2993 start of a (possibly prefixed) mnemonic. */
252b5132 2994
29b0f896
AM		 2995 line = parse_insn (line, mnemonic);
2996 if (line == NULL)
2997 return;
252b5132 2998
29b0f896 2999 line = parse_operands (line, mnemonic);
ee86248c 3000 this_operand = -1;
29b0f896
AM		 3001 if (line == NULL)
3002 return;
252b5132 3003
29b0f896
AM		 3004 /* Now we've parsed the mnemonic into a set of templates, and have the
3005 operands at hand. */
3006
3007 /* All intel opcodes have reversed operands except for "bound" and
3008 "enter". We also don't reverse intersegment "jmp" and "call"
3009 instructions with 2 immediate operands so that the immediate segment
050dfa73 3010 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3011 if (intel_syntax
3012 && i.operands > 1
29b0f896 3013 && (strcmp (mnemonic, "bound") != 0)
30123838 3014 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3015 && !(operand_type_check (i.types[0], imm)
3016 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3017 swap_operands ();
3018
ec56d5c0
JB		 3019 /* The order of the immediates should be reversed
3020 for 2 immediates extrq and insertq instructions */
3021 if (i.imm_operands == 2
3022 && (strcmp (mnemonic, "extrq") == 0
3023 || strcmp (mnemonic, "insertq") == 0))
3024 swap_2_operands (0, 1);
3025
29b0f896
AM		 3026 if (i.imm_operands)
3027 optimize_imm ();
3028
b300c311
L		 3029 /* Don't optimize displacement for movabs since it only takes 64bit
3030 displacement. */
3031 if (i.disp_operands
862be3fb
L		 3032 && !i.disp32_encoding
3033 && (flag_code != CODE_64BIT
3034 || strcmp (mnemonic, "movabs") != 0))
3035 optimize_disp ();
29b0f896
AM		 3036
3037 /* Next, we find a template that matches the given insn,
3038 making sure the overlap of the given operands types is consistent
3039 with the template operand types. */
252b5132 3040
fa99fab2 3041 if (!(t = match_template ()))
29b0f896 3042 return;
252b5132 3043
daf50ae7 3044 if (sse_check != sse_check_none
81f8a913 3045 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3046 && (i.tm.cpu_flags.bitfield.cpusse
3047 || i.tm.cpu_flags.bitfield.cpusse2
3048 || i.tm.cpu_flags.bitfield.cpusse3
3049 || i.tm.cpu_flags.bitfield.cpussse3
3050 || i.tm.cpu_flags.bitfield.cpusse4_1
3051 || i.tm.cpu_flags.bitfield.cpusse4_2))
3052 {
3053 (sse_check == sse_check_warning
3054 ? as_warn
3055 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3056 }
3057
321fd21e
L		 3058 /* Zap movzx and movsx suffix. The suffix has been set from
3059 "word ptr" or "byte ptr" on the source operand in Intel syntax
3060 or extracted from mnemonic in AT&T syntax. But we'll use
3061 the destination register to choose the suffix for encoding. */
3062 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3063 {
321fd21e
L		 3064 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3065 there is no suffix, the default will be byte extension. */
3066 if (i.reg_operands != 2
3067 && !i.suffix
7ab9ffdd 3068 && intel_syntax)
321fd21e
L		 3069 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3070
3071 i.suffix = 0;
cd61ebfe 3072 }
24eab124 3073
40fb9820 3074 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3075 if (!add_prefix (FWAIT_OPCODE))
3076 return;
252b5132 3077
c1ba0266
L		 3078 /* Check for lock without a lockable instruction. Destination operand
3079 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3080 if (i.prefix[LOCK_PREFIX]
3081 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3082 || i.mem_operands == 0
3083 || (i.tm.base_opcode != 0x86
3084 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3085 {
3086 as_bad (_("expecting lockable instruction after `lock'"));
3087 return;
3088 }
3089
29b0f896 3090 /* Check string instruction segment overrides. */
40fb9820 3091 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3092 {
3093 if (!check_string ())
5dd0794d 3094 return;
fc0763e6 3095 i.disp_operands = 0;
29b0f896 3096 }
5dd0794d 3097
29b0f896
AM		 3098 if (!process_suffix ())
3099 return;
e413e4e9 3100
bc0844ae
L		 3101 /* Update operand types. */
3102 for (j = 0; j < i.operands; j++)
3103 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3104
29b0f896
AM		 3105 /* Make still unresolved immediate matches conform to size of immediate
3106 given in i.suffix. */
3107 if (!finalize_imm ())
3108 return;
252b5132 3109
40fb9820 3110 if (i.types[0].bitfield.imm1)
29b0f896 3111 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3112
9afe6eb8
L		 3113 /* We only need to check those implicit registers for instructions
3114 with 3 operands or less. */
3115 if (i.operands <= 3)
3116 for (j = 0; j < i.operands; j++)
3117 if (i.types[j].bitfield.inoutportreg
3118 || i.types[j].bitfield.shiftcount
3119 || i.types[j].bitfield.acc
3120 || i.types[j].bitfield.floatacc)
3121 i.reg_operands--;
40fb9820 3122
c0f3af97
L		 3123 /* ImmExt should be processed after SSE2AVX. */
3124 if (!i.tm.opcode_modifier.sse2avx
3125 && i.tm.opcode_modifier.immext)
65da13b5 3126 process_immext ();
252b5132 3127
29b0f896
AM		 3128 /* For insns with operands there are more diddles to do to the opcode. */
3129 if (i.operands)
3130 {
3131 if (!process_operands ())
3132 return;
3133 }
40fb9820 3134 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3135 {
3136 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3137 as_warn (_("translating to `%sp'"), i.tm.name);
3138 }
252b5132 3139
c0f3af97 3140 if (i.tm.opcode_modifier.vex)
fa99fab2 3141 build_vex_prefix (t);
c0f3af97 3142
5dd85c99
SP		 3143 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3144 instructions may define INT_OPCODE as well, so avoid this corner
3145 case for those instructions that use MODRM. */
3146 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3147 && !i.tm.opcode_modifier.modrm
3148 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3149 {
3150 i.tm.base_opcode = INT3_OPCODE;
3151 i.imm_operands = 0;
3152 }
252b5132 3153
40fb9820
L		 3154 if ((i.tm.opcode_modifier.jump
3155 || i.tm.opcode_modifier.jumpbyte
3156 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3157 && i.op[0].disps->X_op == O_constant)
3158 {
3159 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3160 the absolute address given by the constant. Since ix86 jumps and
3161 calls are pc relative, we need to generate a reloc. */
3162 i.op[0].disps->X_add_symbol = &abs_symbol;
3163 i.op[0].disps->X_op = O_symbol;
3164 }
252b5132 3165
40fb9820 3166 if (i.tm.opcode_modifier.rex64)
161a04f6 3167 i.rex |= REX_W;
252b5132 3168
29b0f896
AM		 3169 /* For 8 bit registers we need an empty rex prefix. Also if the
3170 instruction already has a prefix, we need to convert old
3171 registers to new ones. */
773f551c 3172
40fb9820 3173 if ((i.types[0].bitfield.reg8
29b0f896 3174 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3175 || (i.types[1].bitfield.reg8
29b0f896 3176 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3177 || ((i.types[0].bitfield.reg8
3178 || i.types[1].bitfield.reg8)
29b0f896
AM		 3179 && i.rex != 0))
3180 {
3181 int x;
726c5dcd 3182
29b0f896
AM		 3183 i.rex |= REX_OPCODE;
3184 for (x = 0; x < 2; x++)
3185 {
3186 /* Look for 8 bit operand that uses old registers. */
40fb9820 3187 if (i.types[x].bitfield.reg8
29b0f896 3188 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3189 {
29b0f896
AM		 3190 /* In case it is "hi" register, give up. */
3191 if (i.op[x].regs->reg_num > 3)
a540244d 3192 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3193 "instruction requiring REX prefix."),
a540244d 3194 register_prefix, i.op[x].regs->reg_name);
773f551c 3195
29b0f896
AM		 3196 /* Otherwise it is equivalent to the extended register.
3197 Since the encoding doesn't change this is merely
3198 cosmetic cleanup for debug output. */
3199
3200 i.op[x].regs = i.op[x].regs + 8;
773f551c 3201 }
29b0f896
AM		 3202 }
3203 }
773f551c 3204
7ab9ffdd 3205 if (i.rex != 0)
29b0f896
AM		 3206 add_prefix (REX_OPCODE | i.rex);
3207
3208 /* We are ready to output the insn. */
3209 output_insn ();
3210}
3211
3212static char *
e3bb37b5 3213parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3214{
3215 char *l = line;
3216 char *token_start = l;
3217 char *mnem_p;
5c6af06e 3218 int supported;
d3ce72d0 3219 const insn_template *t;
b6169b20 3220 char *dot_p = NULL;
29b0f896
AM		 3221
3222 /* Non-zero if we found a prefix only acceptable with string insns. */
3223 const char *expecting_string_instruction = NULL;
45288df1 3224
29b0f896
AM		 3225 while (1)
3226 {
3227 mnem_p = mnemonic;
3228 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3229 {
b6169b20
L		 3230 if (*mnem_p == '.')
3231 dot_p = mnem_p;
29b0f896
AM		 3232 mnem_p++;
3233 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3234 {
29b0f896
AM		 3235 as_bad (_("no such instruction: `%s'"), token_start);
3236 return NULL;
3237 }
3238 l++;
3239 }
3240 if (!is_space_char (*l)
3241 && *l != END_OF_INSN
e44823cf
JB		 3242 && (intel_syntax
3243 || (*l != PREFIX_SEPARATOR
3244 && *l != ',')))
29b0f896
AM		 3245 {
3246 as_bad (_("invalid character %s in mnemonic"),
3247 output_invalid (*l));
3248 return NULL;
3249 }
3250 if (token_start == l)
3251 {
e44823cf 3252 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3253 as_bad (_("expecting prefix; got nothing"));
3254 else
3255 as_bad (_("expecting mnemonic; got nothing"));
3256 return NULL;
3257 }
45288df1 3258
29b0f896 3259 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3260 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3261
29b0f896
AM		 3262 if (*l != END_OF_INSN
3263 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3264 && current_templates
40fb9820 3265 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3266 {
c6fb90c8 3267 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3268 {
3269 as_bad ((flag_code != CODE_64BIT
3270 ? _("`%s' is only supported in 64-bit mode")
3271 : _("`%s' is not supported in 64-bit mode")),
3272 current_templates->start->name);
3273 return NULL;
3274 }
29b0f896
AM		 3275 /* If we are in 16-bit mode, do not allow addr16 or data16.
3276 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3277 if ((current_templates->start->opcode_modifier.size16
3278 || current_templates->start->opcode_modifier.size32)
29b0f896 3279 && flag_code != CODE_64BIT
40fb9820 3280 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3281 ^ (flag_code == CODE_16BIT)))
3282 {
3283 as_bad (_("redundant %s prefix"),
3284 current_templates->start->name);
3285 return NULL;
45288df1 3286 }
29b0f896
AM		 3287 /* Add prefix, checking for repeated prefixes. */
3288 switch (add_prefix (current_templates->start->base_opcode))
3289 {
c32fa91d 3290 case PREFIX_EXIST:
29b0f896 3291 return NULL;
c32fa91d 3292 case PREFIX_REP:
29b0f896
AM		 3293 expecting_string_instruction = current_templates->start->name;
3294 break;
c32fa91d
L		 3295 default:
3296 break;
29b0f896
AM		 3297 }
3298 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3299 token_start = ++l;
3300 }
3301 else
3302 break;
3303 }
45288df1 3304
30a55f88 3305 if (!current_templates)
b6169b20 3306 {
f8a5c266
L		 3307 /* Check if we should swap operand or force 32bit displacement in
3308 encoding. */
30a55f88
L		 3309 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3310 i.swap_operand = 1;
f8a5c266
L		 3311 else if (mnem_p - 4 == dot_p
3312 && dot_p[1] == 'd'
3313 && dot_p[2] == '3'
3314 && dot_p[3] == '2')
3315 i.disp32_encoding = 1;
30a55f88
L		 3316 else
3317 goto check_suffix;
3318 mnem_p = dot_p;
3319 *dot_p = '\0';
d3ce72d0 3320 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3321 }
3322
29b0f896
AM		 3323 if (!current_templates)
3324 {
b6169b20 3325check_suffix:
29b0f896
AM		 3326 /* See if we can get a match by trimming off a suffix. */
3327 switch (mnem_p[-1])
3328 {
3329 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3330 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3331 i.suffix = SHORT_MNEM_SUFFIX;
3332 else
29b0f896
AM		 3333 case BYTE_MNEM_SUFFIX:
3334 case QWORD_MNEM_SUFFIX:
3335 i.suffix = mnem_p[-1];
3336 mnem_p[-1] = '\0';
d3ce72d0
NC		 3337 current_templates = (const templates *) hash_find (op_hash,
3338 mnemonic);
29b0f896
AM		 3339 break;
3340 case SHORT_MNEM_SUFFIX:
3341 case LONG_MNEM_SUFFIX:
3342 if (!intel_syntax)
3343 {
3344 i.suffix = mnem_p[-1];
3345 mnem_p[-1] = '\0';
d3ce72d0
NC		 3346 current_templates = (const templates *) hash_find (op_hash,
3347 mnemonic);
29b0f896
AM		 3348 }
3349 break;
252b5132 3350
29b0f896
AM		 3351 /* Intel Syntax. */
3352 case 'd':
3353 if (intel_syntax)
3354 {
9306ca4a 3355 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3356 i.suffix = SHORT_MNEM_SUFFIX;
3357 else
3358 i.suffix = LONG_MNEM_SUFFIX;
3359 mnem_p[-1] = '\0';
d3ce72d0
NC		 3360 current_templates = (const templates *) hash_find (op_hash,
3361 mnemonic);
29b0f896
AM		 3362 }
3363 break;
3364 }
3365 if (!current_templates)
3366 {
3367 as_bad (_("no such instruction: `%s'"), token_start);
3368 return NULL;
3369 }
3370 }
252b5132 3371
40fb9820
L		 3372 if (current_templates->start->opcode_modifier.jump
3373 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3374 {
3375 /* Check for a branch hint. We allow ",pt" and ",pn" for
3376 predict taken and predict not taken respectively.
3377 I'm not sure that branch hints actually do anything on loop
3378 and jcxz insns (JumpByte) for current Pentium4 chips. They
3379 may work in the future and it doesn't hurt to accept them
3380 now. */
3381 if (l[0] == ',' && l[1] == 'p')
3382 {
3383 if (l[2] == 't')
3384 {
3385 if (!add_prefix (DS_PREFIX_OPCODE))
3386 return NULL;
3387 l += 3;
3388 }
3389 else if (l[2] == 'n')
3390 {
3391 if (!add_prefix (CS_PREFIX_OPCODE))
3392 return NULL;
3393 l += 3;
3394 }
3395 }
3396 }
3397 /* Any other comma loses. */
3398 if (*l == ',')
3399 {
3400 as_bad (_("invalid character %s in mnemonic"),
3401 output_invalid (*l));
3402 return NULL;
3403 }
252b5132 3404
29b0f896 3405 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3406 supported = 0;
3407 for (t = current_templates->start; t < current_templates->end; ++t)
3408 {
c0f3af97
L		 3409 supported |= cpu_flags_match (t);
3410 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3411 goto skip;
5c6af06e 3412 }
3629bb00 3413
c0f3af97 3414 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3415 {
3416 as_bad (flag_code == CODE_64BIT
3417 ? _("`%s' is not supported in 64-bit mode")
3418 : _("`%s' is only supported in 64-bit mode"),
3419 current_templates->start->name);
3420 return NULL;
3421 }
c0f3af97 3422 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3423 {
3629bb00 3424 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3425 current_templates->start->name,
41aacd83 3426 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3427 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3428 return NULL;
29b0f896 3429 }
3629bb00
L		 3430
3431skip:
3432 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3433 && (flag_code != CODE_16BIT))
29b0f896
AM		 3434 {
3435 as_warn (_("use .code16 to ensure correct addressing mode"));
3436 }
252b5132 3437
29b0f896 3438 /* Check for rep/repne without a string instruction. */
f41bbced 3439 if (expecting_string_instruction)
29b0f896 3440 {
f41bbced
JB		 3441 static templates override;
3442
3443 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3444 if (t->opcode_modifier.isstring)
f41bbced
JB		 3445 break;
3446 if (t >= current_templates->end)
3447 {
3448 as_bad (_("expecting string instruction after `%s'"),
64e74474 3449 expecting_string_instruction);
f41bbced
JB		 3450 return NULL;
3451 }
3452 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3453 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3454 break;
3455 override.end = t;
3456 current_templates = &override;
29b0f896 3457 }
252b5132 3458
29b0f896
AM		 3459 return l;
3460}
252b5132 3461
29b0f896 3462static char *
e3bb37b5 3463parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3464{
3465 char *token_start;
3138f287 3466
29b0f896
AM		 3467 /* 1 if operand is pending after ','. */
3468 unsigned int expecting_operand = 0;
252b5132 3469
29b0f896
AM		 3470 /* Non-zero if operand parens not balanced. */
3471 unsigned int paren_not_balanced;
3472
3473 while (*l != END_OF_INSN)
3474 {
3475 /* Skip optional white space before operand. */
3476 if (is_space_char (*l))
3477 ++l;
3478 if (!is_operand_char (*l) && *l != END_OF_INSN)
3479 {
3480 as_bad (_("invalid character %s before operand %d"),
3481 output_invalid (*l),
3482 i.operands + 1);
3483 return NULL;
3484 }
3485 token_start = l; /* after white space */
3486 paren_not_balanced = 0;
3487 while (paren_not_balanced || *l != ',')
3488 {
3489 if (*l == END_OF_INSN)
3490 {
3491 if (paren_not_balanced)
3492 {
3493 if (!intel_syntax)
3494 as_bad (_("unbalanced parenthesis in operand %d."),
3495 i.operands + 1);
3496 else
3497 as_bad (_("unbalanced brackets in operand %d."),
3498 i.operands + 1);
3499 return NULL;
3500 }
3501 else
3502 break; /* we are done */
3503 }
3504 else if (!is_operand_char (*l) && !is_space_char (*l))
3505 {
3506 as_bad (_("invalid character %s in operand %d"),
3507 output_invalid (*l),
3508 i.operands + 1);
3509 return NULL;
3510 }
3511 if (!intel_syntax)
3512 {
3513 if (*l == '(')
3514 ++paren_not_balanced;
3515 if (*l == ')')
3516 --paren_not_balanced;
3517 }
3518 else
3519 {
3520 if (*l == '[')
3521 ++paren_not_balanced;
3522 if (*l == ']')
3523 --paren_not_balanced;
3524 }
3525 l++;
3526 }
3527 if (l != token_start)
3528 { /* Yes, we've read in another operand. */
3529 unsigned int operand_ok;
3530 this_operand = i.operands++;
7d5e4556 3531 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3532 if (i.operands > MAX_OPERANDS)
3533 {
3534 as_bad (_("spurious operands; (%d operands/instruction max)"),
3535 MAX_OPERANDS);
3536 return NULL;
3537 }
3538 /* Now parse operand adding info to 'i' as we go along. */
3539 END_STRING_AND_SAVE (l);
3540
3541 if (intel_syntax)
3542 operand_ok =
3543 i386_intel_operand (token_start,
3544 intel_float_operand (mnemonic));
3545 else
a7619375 3546 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3547
3548 RESTORE_END_STRING (l);
3549 if (!operand_ok)
3550 return NULL;
3551 }
3552 else
3553 {
3554 if (expecting_operand)
3555 {
3556 expecting_operand_after_comma:
3557 as_bad (_("expecting operand after ','; got nothing"));
3558 return NULL;
3559 }
3560 if (*l == ',')
3561 {
3562 as_bad (_("expecting operand before ','; got nothing"));
3563 return NULL;
3564 }
3565 }
7f3f1ea2 3566
29b0f896
AM		 3567 /* Now *l must be either ',' or END_OF_INSN. */
3568 if (*l == ',')
3569 {
3570 if (*++l == END_OF_INSN)
3571 {
3572 /* Just skip it, if it's \n complain. */
3573 goto expecting_operand_after_comma;
3574 }
3575 expecting_operand = 1;
3576 }
3577 }
3578 return l;
3579}
7f3f1ea2 3580
050dfa73 3581static void
4d456e3d 3582swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3583{
3584 union i386_op temp_op;
40fb9820 3585 i386_operand_type temp_type;
050dfa73 3586 enum bfd_reloc_code_real temp_reloc;
4eed87de 3587
050dfa73
MM		 3588 temp_type = i.types[xchg2];
3589 i.types[xchg2] = i.types[xchg1];
3590 i.types[xchg1] = temp_type;
3591 temp_op = i.op[xchg2];
3592 i.op[xchg2] = i.op[xchg1];
3593 i.op[xchg1] = temp_op;
3594 temp_reloc = i.reloc[xchg2];
3595 i.reloc[xchg2] = i.reloc[xchg1];
3596 i.reloc[xchg1] = temp_reloc;
3597}
3598
29b0f896 3599static void
e3bb37b5 3600swap_operands (void)
29b0f896 3601{
b7c61d9a 3602 switch (i.operands)
050dfa73 3603 {
c0f3af97 3604 case 5:
b7c61d9a 3605 case 4:
4d456e3d 3606 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3607 case 3:
3608 case 2:
4d456e3d 3609 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3610 break;
3611 default:
3612 abort ();
29b0f896 3613 }
29b0f896
AM		 3614
3615 if (i.mem_operands == 2)
3616 {
3617 const seg_entry *temp_seg;
3618 temp_seg = i.seg[0];
3619 i.seg[0] = i.seg[1];
3620 i.seg[1] = temp_seg;
3621 }
3622}
252b5132 3623
29b0f896
AM		 3624/* Try to ensure constant immediates are represented in the smallest
3625 opcode possible. */
3626static void
e3bb37b5 3627optimize_imm (void)
29b0f896
AM		 3628{
3629 char guess_suffix = 0;
3630 int op;
252b5132 3631
29b0f896
AM		 3632 if (i.suffix)
3633 guess_suffix = i.suffix;
3634 else if (i.reg_operands)
3635 {
3636 /* Figure out a suffix from the last register operand specified.
3637 We can't do this properly yet, ie. excluding InOutPortReg,
3638 but the following works for instructions with immediates.
3639 In any case, we can't set i.suffix yet. */
3640 for (op = i.operands; --op >= 0;)
40fb9820 3641 if (i.types[op].bitfield.reg8)
7ab9ffdd 3642 {
40fb9820
L		 3643 guess_suffix = BYTE_MNEM_SUFFIX;
3644 break;
3645 }
3646 else if (i.types[op].bitfield.reg16)
252b5132 3647 {
40fb9820
L		 3648 guess_suffix = WORD_MNEM_SUFFIX;
3649 break;
3650 }
3651 else if (i.types[op].bitfield.reg32)
3652 {
3653 guess_suffix = LONG_MNEM_SUFFIX;
3654 break;
3655 }
3656 else if (i.types[op].bitfield.reg64)
3657 {
3658 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3659 break;
252b5132 3660 }
29b0f896
AM		 3661 }
3662 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3663 guess_suffix = WORD_MNEM_SUFFIX;
3664
3665 for (op = i.operands; --op >= 0;)
40fb9820 3666 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3667 {
3668 switch (i.op[op].imms->X_op)
252b5132 3669 {
29b0f896
AM		 3670 case O_constant:
3671 /* If a suffix is given, this operand may be shortened. */
3672 switch (guess_suffix)
252b5132 3673 {
29b0f896 3674 case LONG_MNEM_SUFFIX:
40fb9820
L		 3675 i.types[op].bitfield.imm32 = 1;
3676 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3677 break;
3678 case WORD_MNEM_SUFFIX:
40fb9820
L		 3679 i.types[op].bitfield.imm16 = 1;
3680 i.types[op].bitfield.imm32 = 1;
3681 i.types[op].bitfield.imm32s = 1;
3682 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3683 break;
3684 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3685 i.types[op].bitfield.imm8 = 1;
3686 i.types[op].bitfield.imm8s = 1;
3687 i.types[op].bitfield.imm16 = 1;
3688 i.types[op].bitfield.imm32 = 1;
3689 i.types[op].bitfield.imm32s = 1;
3690 i.types[op].bitfield.imm64 = 1;
29b0f896 3691 break;
252b5132 3692 }
252b5132 3693
29b0f896
AM		 3694 /* If this operand is at most 16 bits, convert it
3695 to a signed 16 bit number before trying to see
3696 whether it will fit in an even smaller size.
3697 This allows a 16-bit operand such as $0xffe0 to
3698 be recognised as within Imm8S range. */
40fb9820 3699 if ((i.types[op].bitfield.imm16)
29b0f896 3700 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3701 {
29b0f896
AM		 3702 i.op[op].imms->X_add_number =
3703 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3704 }
40fb9820 3705 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3706 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3707 == 0))
3708 {
3709 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3710 ^ ((offsetT) 1 << 31))
3711 - ((offsetT) 1 << 31));
3712 }
40fb9820 3713 i.types[op]
c6fb90c8
L		 3714 = operand_type_or (i.types[op],
3715 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3716
29b0f896
AM		 3717 /* We must avoid matching of Imm32 templates when 64bit
3718 only immediate is available. */
3719 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3720 i.types[op].bitfield.imm32 = 0;
29b0f896 3721 break;
252b5132 3722
29b0f896
AM		 3723 case O_absent:
3724 case O_register:
3725 abort ();
3726
3727 /* Symbols and expressions. */
3728 default:
9cd96992
JB		 3729 /* Convert symbolic operand to proper sizes for matching, but don't
3730 prevent matching a set of insns that only supports sizes other
3731 than those matching the insn suffix. */
3732 {
40fb9820 3733 i386_operand_type mask, allowed;
d3ce72d0 3734 const insn_template *t;
9cd96992 3735
0dfbf9d7
L		 3736 operand_type_set (&mask, 0);
3737 operand_type_set (&allowed, 0);
40fb9820 3738
4eed87de
AM		 3739 for (t = current_templates->start;
3740 t < current_templates->end;
3741 ++t)
c6fb90c8
L		 3742 allowed = operand_type_or (allowed,
3743 t->operand_types[op]);
9cd96992
JB		 3744 switch (guess_suffix)
3745 {
3746 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3747 mask.bitfield.imm64 = 1;
3748 mask.bitfield.imm32s = 1;
9cd96992
JB		 3749 break;
3750 case LONG_MNEM_SUFFIX:
40fb9820 3751 mask.bitfield.imm32 = 1;
9cd96992
JB		 3752 break;
3753 case WORD_MNEM_SUFFIX:
40fb9820 3754 mask.bitfield.imm16 = 1;
9cd96992
JB		 3755 break;
3756 case BYTE_MNEM_SUFFIX:
40fb9820 3757 mask.bitfield.imm8 = 1;
9cd96992
JB		 3758 break;
3759 default:
9cd96992
JB		 3760 break;
3761 }
c6fb90c8 3762 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3763 if (!operand_type_all_zero (&allowed))
c6fb90c8 3764 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3765 }
29b0f896 3766 break;
252b5132 3767 }
29b0f896
AM		 3768 }
3769}
47926f60 3770
29b0f896
AM		 3771/* Try to use the smallest displacement type too. */
3772static void
e3bb37b5 3773optimize_disp (void)
29b0f896
AM		 3774{
3775 int op;
3e73aa7c 3776
29b0f896 3777 for (op = i.operands; --op >= 0;)
40fb9820 3778 if (operand_type_check (i.types[op], disp))
252b5132 3779 {
b300c311 3780 if (i.op[op].disps->X_op == O_constant)
252b5132 3781 {
91d6fa6a 3782 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 3783
40fb9820 3784 if (i.types[op].bitfield.disp16
91d6fa6a 3785 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 3786 {
3787 /* If this operand is at most 16 bits, convert
3788 to a signed 16 bit number and don't use 64bit
3789 displacement. */
91d6fa6a 3790 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3791 i.types[op].bitfield.disp64 = 0;
b300c311 3792 }
40fb9820 3793 if (i.types[op].bitfield.disp32
91d6fa6a 3794 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 3795 {
3796 /* If this operand is at most 32 bits, convert
3797 to a signed 32 bit number and don't use 64bit
3798 displacement. */
91d6fa6a
NC		 3799 op_disp &= (((offsetT) 2 << 31) - 1);
3800 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3801 i.types[op].bitfield.disp64 = 0;
b300c311 3802 }
91d6fa6a 3803 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 3804 {
40fb9820
L		 3805 i.types[op].bitfield.disp8 = 0;
3806 i.types[op].bitfield.disp16 = 0;
3807 i.types[op].bitfield.disp32 = 0;
3808 i.types[op].bitfield.disp32s = 0;
3809 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3810 i.op[op].disps = 0;
3811 i.disp_operands--;
3812 }
3813 else if (flag_code == CODE_64BIT)
3814 {
91d6fa6a 3815 if (fits_in_signed_long (op_disp))
28a9d8f5 3816 {
40fb9820
L		 3817 i.types[op].bitfield.disp64 = 0;
3818 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3819 }
0e1147d9 3820 if (i.prefix[ADDR_PREFIX]
91d6fa6a 3821 && fits_in_unsigned_long (op_disp))
40fb9820 3822 i.types[op].bitfield.disp32 = 1;
b300c311 3823 }
40fb9820
L		 3824 if ((i.types[op].bitfield.disp32
3825 || i.types[op].bitfield.disp32s
3826 || i.types[op].bitfield.disp16)
91d6fa6a 3827 && fits_in_signed_byte (op_disp))
40fb9820 3828 i.types[op].bitfield.disp8 = 1;
252b5132 3829 }
67a4f2b7
AO		 3830 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3831 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3832 {
3833 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3834 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3835 i.types[op].bitfield.disp8 = 0;
3836 i.types[op].bitfield.disp16 = 0;
3837 i.types[op].bitfield.disp32 = 0;
3838 i.types[op].bitfield.disp32s = 0;
3839 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3840 }
3841 else
b300c311 3842 /* We only support 64bit displacement on constants. */
40fb9820 3843 i.types[op].bitfield.disp64 = 0;
252b5132 3844 }
29b0f896
AM		 3845}
3846
6c30d220
L		 3847/* Check if operands are valid for the instruction. */
3848
3849static int
3850check_VecOperands (const insn_template *t)
3851{
3852 /* Without VSIB byte, we can't have a vector register for index. */
3853 if (!t->opcode_modifier.vecsib
3854 && i.index_reg
3855 && (i.index_reg->reg_type.bitfield.regxmm
3856 || i.index_reg->reg_type.bitfield.regymm))
3857 {
3858 i.error = unsupported_vector_index_register;
3859 return 1;
3860 }
3861
3862 /* For VSIB byte, we need a vector register for index and no PC
3863 relative addressing is allowed. */
3864 if (t->opcode_modifier.vecsib
3865 && (!i.index_reg
3866 || !((t->opcode_modifier.vecsib == VecSIB128
3867 && i.index_reg->reg_type.bitfield.regxmm)
3868 || (t->opcode_modifier.vecsib == VecSIB256
3869 && i.index_reg->reg_type.bitfield.regymm))
3870 || (i.base_reg && i.base_reg->reg_num == RegRip)))
3871 {
3872 i.error = invalid_vsib_address;
3873 return 1;
3874 }
3875
3876 return 0;
3877}
3878
43f3e2ee 3879/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 3880 operand types. */
3881
3882static int
3883VEX_check_operands (const insn_template *t)
3884{
3885 if (!t->opcode_modifier.vex)
3886 return 0;
3887
3888 /* Only check VEX_Imm4, which must be the first operand. */
3889 if (t->operand_types[0].bitfield.vec_imm4)
3890 {
3891 if (i.op[0].imms->X_op != O_constant
3892 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 3893 {
a65babc9 3894 i.error = bad_imm4;
891edac4
L		 3895 return 1;
3896 }
a683cc34
SP		 3897
3898 /* Turn off Imm8 so that update_imm won't complain. */
3899 i.types[0] = vec_imm4;
3900 }
3901
3902 return 0;
3903}
3904
d3ce72d0 3905static const insn_template *
e3bb37b5 3906match_template (void)
29b0f896
AM		 3907{
3908 /* Points to template once we've found it. */
d3ce72d0 3909 const insn_template *t;
40fb9820 3910 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3911 i386_operand_type overlap4;
29b0f896 3912 unsigned int found_reverse_match;
40fb9820
L		 3913 i386_opcode_modifier suffix_check;
3914 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3915 int addr_prefix_disp;
a5c311ca 3916 unsigned int j;
3629bb00 3917 unsigned int found_cpu_match;
45664ddb 3918 unsigned int check_register;
29b0f896 3919
c0f3af97
L		 3920#if MAX_OPERANDS != 5
3921# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3922#endif
3923
29b0f896 3924 found_reverse_match = 0;
539e75ad 3925 addr_prefix_disp = -1;
40fb9820
L		 3926
3927 memset (&suffix_check, 0, sizeof (suffix_check));
3928 if (i.suffix == BYTE_MNEM_SUFFIX)
3929 suffix_check.no_bsuf = 1;
3930 else if (i.suffix == WORD_MNEM_SUFFIX)
3931 suffix_check.no_wsuf = 1;
3932 else if (i.suffix == SHORT_MNEM_SUFFIX)
3933 suffix_check.no_ssuf = 1;
3934 else if (i.suffix == LONG_MNEM_SUFFIX)
3935 suffix_check.no_lsuf = 1;
3936 else if (i.suffix == QWORD_MNEM_SUFFIX)
3937 suffix_check.no_qsuf = 1;
3938 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3939 suffix_check.no_ldsuf = 1;
29b0f896 3940
01559ecc
L		 3941 /* Must have right number of operands. */
3942 i.error = number_of_operands_mismatch;
3943
45aa61fe 3944 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3945 {
539e75ad
L		 3946 addr_prefix_disp = -1;
3947
29b0f896
AM		 3948 if (i.operands != t->operands)
3949 continue;
3950
50aecf8c 3951 /* Check processor support. */
a65babc9 3952 i.error = unsupported;
c0f3af97
L		 3953 found_cpu_match = (cpu_flags_match (t)
3954 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3955 if (!found_cpu_match)
3956 continue;
3957
e1d4d893 3958 /* Check old gcc support. */
a65babc9 3959 i.error = old_gcc_only;
e1d4d893
L		 3960 if (!old_gcc && t->opcode_modifier.oldgcc)
3961 continue;
3962
3963 /* Check AT&T mnemonic. */
a65babc9 3964 i.error = unsupported_with_intel_mnemonic;
e1d4d893 3965 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3966 continue;
3967
891edac4 3968 /* Check AT&T/Intel syntax. */
a65babc9 3969 i.error = unsupported_syntax;
5c07affc
L		 3970 if ((intel_syntax && t->opcode_modifier.attsyntax)
3971 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3972 continue;
3973
20592a94 3974 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 3975 i.error = invalid_instruction_suffix;
567e4e96
L		 3976 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3977 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3978 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3979 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3980 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3981 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3982 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3983 continue;
3984
5c07affc 3985 if (!operand_size_match (t))
7d5e4556 3986 continue;
539e75ad 3987
5c07affc
L		 3988 for (j = 0; j < MAX_OPERANDS; j++)
3989 operand_types[j] = t->operand_types[j];
3990
45aa61fe
AM		 3991 /* In general, don't allow 64-bit operands in 32-bit mode. */
3992 if (i.suffix == QWORD_MNEM_SUFFIX
3993 && flag_code != CODE_64BIT
3994 && (intel_syntax
40fb9820 3995 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3996 && !intel_float_operand (t->name))
3997 : intel_float_operand (t->name) != 2)
40fb9820 3998 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3999 && !operand_types[0].bitfield.regxmm
4000 && !operand_types[0].bitfield.regymm)
40fb9820 4001 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 4002 && !!operand_types[t->operands > 1].bitfield.regxmm
4003 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 4004 && (t->base_opcode != 0x0fc7
4005 || t->extension_opcode != 1 /* cmpxchg8b */))
4006 continue;
4007
192dc9c6
JB		 4008 /* In general, don't allow 32-bit operands on pre-386. */
4009 else if (i.suffix == LONG_MNEM_SUFFIX
4010 && !cpu_arch_flags.bitfield.cpui386
4011 && (intel_syntax
4012 ? (!t->opcode_modifier.ignoresize
4013 && !intel_float_operand (t->name))
4014 : intel_float_operand (t->name) != 2)
4015 && ((!operand_types[0].bitfield.regmmx
4016 && !operand_types[0].bitfield.regxmm)
4017 || (!operand_types[t->operands > 1].bitfield.regmmx
4018 && !!operand_types[t->operands > 1].bitfield.regxmm)))
4019 continue;
4020
29b0f896 4021 /* Do not verify operands when there are none. */
50aecf8c 4022 else
29b0f896 4023 {
c6fb90c8 4024 if (!t->operands)
2dbab7d5
L		 4025 /* We've found a match; break out of loop. */
4026 break;
29b0f896 4027 }
252b5132 4028
539e75ad
L		 4029 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4030 into Disp32/Disp16/Disp32 operand. */
4031 if (i.prefix[ADDR_PREFIX] != 0)
4032 {
40fb9820 4033 /* There should be only one Disp operand. */
539e75ad
L		 4034 switch (flag_code)
4035 {
4036 case CODE_16BIT:
40fb9820
L		 4037 for (j = 0; j < MAX_OPERANDS; j++)
4038 {
4039 if (operand_types[j].bitfield.disp16)
4040 {
4041 addr_prefix_disp = j;
4042 operand_types[j].bitfield.disp32 = 1;
4043 operand_types[j].bitfield.disp16 = 0;
4044 break;
4045 }
4046 }
539e75ad
L		 4047 break;
4048 case CODE_32BIT:
40fb9820
L		 4049 for (j = 0; j < MAX_OPERANDS; j++)
4050 {
4051 if (operand_types[j].bitfield.disp32)
4052 {
4053 addr_prefix_disp = j;
4054 operand_types[j].bitfield.disp32 = 0;
4055 operand_types[j].bitfield.disp16 = 1;
4056 break;
4057 }
4058 }
539e75ad
L		 4059 break;
4060 case CODE_64BIT:
40fb9820
L		 4061 for (j = 0; j < MAX_OPERANDS; j++)
4062 {
4063 if (operand_types[j].bitfield.disp64)
4064 {
4065 addr_prefix_disp = j;
4066 operand_types[j].bitfield.disp64 = 0;
4067 operand_types[j].bitfield.disp32 = 1;
4068 break;
4069 }
4070 }
539e75ad
L		 4071 break;
4072 }
539e75ad
L		 4073 }
4074
56ffb741
L		 4075 /* We check register size if needed. */
4076 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4077 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4078 switch (t->operands)
4079 {
4080 case 1:
40fb9820 4081 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4082 continue;
4083 break;
4084 case 2:
8b38ad71
L		 4085 /* xchg %eax, %eax is a special case. It is an aliase for nop
4086 only in 32bit mode and we can use opcode 0x90. In 64bit
4087 mode, we can't use 0x90 for xchg %eax, %eax since it should
4088 zero-extend %eax to %rax. */
4089 if (flag_code == CODE_64BIT
4090 && t->base_opcode == 0x90
0dfbf9d7
L		 4091 && operand_type_equal (&i.types [0], &acc32)
4092 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4093 continue;
b6169b20
L		 4094 if (i.swap_operand)
4095 {
4096 /* If we swap operand in encoding, we either match
4097 the next one or reverse direction of operands. */
4098 if (t->opcode_modifier.s)
4099 continue;
4100 else if (t->opcode_modifier.d)
4101 goto check_reverse;
4102 }
4103
29b0f896 4104 case 3:
fa99fab2
L		 4105 /* If we swap operand in encoding, we match the next one. */
4106 if (i.swap_operand && t->opcode_modifier.s)
4107 continue;
f48ff2ae 4108 case 4:
c0f3af97 4109 case 5:
c6fb90c8 4110 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4111 if (!operand_type_match (overlap0, i.types[0])
4112 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4113 || (check_register
4114 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4115 operand_types[0],
4116 overlap1, i.types[1],
4117 operand_types[1])))
29b0f896
AM		 4118 {
4119 /* Check if other direction is valid ... */
40fb9820 4120 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4121 continue;
4122
b6169b20 4123check_reverse:
29b0f896 4124 /* Try reversing direction of operands. */
c6fb90c8
L		 4125 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4126 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4127 if (!operand_type_match (overlap0, i.types[0])
4128 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4129 || (check_register
4130 && !operand_type_register_match (overlap0,
4131 i.types[0],
4132 operand_types[1],
4133 overlap1,
4134 i.types[1],
4135 operand_types[0])))
29b0f896
AM		 4136 {
4137 /* Does not match either direction. */
4138 continue;
4139 }
4140 /* found_reverse_match holds which of D or FloatDR
4141 we've found. */
40fb9820 4142 if (t->opcode_modifier.d)
8a2ed489 4143 found_reverse_match = Opcode_D;
40fb9820 4144 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4145 found_reverse_match = Opcode_FloatD;
4146 else
4147 found_reverse_match = 0;
40fb9820 4148 if (t->opcode_modifier.floatr)
8a2ed489 4149 found_reverse_match |= Opcode_FloatR;
29b0f896 4150 }
f48ff2ae 4151 else
29b0f896 4152 {
f48ff2ae 4153 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4154 switch (t->operands)
4155 {
c0f3af97
L		 4156 case 5:
4157 overlap4 = operand_type_and (i.types[4],
4158 operand_types[4]);
d1cbb4db 4159 case 4:
c6fb90c8
L		 4160 overlap3 = operand_type_and (i.types[3],
4161 operand_types[3]);
d1cbb4db 4162 case 3:
c6fb90c8
L		 4163 overlap2 = operand_type_and (i.types[2],
4164 operand_types[2]);
d1cbb4db
L		 4165 break;
4166 }
29b0f896 4167
f48ff2ae
L		 4168 switch (t->operands)
4169 {
c0f3af97
L		 4170 case 5:
4171 if (!operand_type_match (overlap4, i.types[4])
4172 || !operand_type_register_match (overlap3,
4173 i.types[3],
4174 operand_types[3],
4175 overlap4,
4176 i.types[4],
4177 operand_types[4]))
4178 continue;
f48ff2ae 4179 case 4:
40fb9820 4180 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4181 || (check_register
4182 && !operand_type_register_match (overlap2,
4183 i.types[2],
4184 operand_types[2],
4185 overlap3,
4186 i.types[3],
4187 operand_types[3])))
f48ff2ae
L		 4188 continue;
4189 case 3:
4190 /* Here we make use of the fact that there are no
4191 reverse match 3 operand instructions, and all 3
4192 operand instructions only need to be checked for
4193 register consistency between operands 2 and 3. */
40fb9820 4194 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4195 || (check_register
4196 && !operand_type_register_match (overlap1,
4197 i.types[1],
4198 operand_types[1],
4199 overlap2,
4200 i.types[2],
4201 operand_types[2])))
f48ff2ae
L		 4202 continue;
4203 break;
4204 }
29b0f896 4205 }
f48ff2ae 4206 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4207 slip through to break. */
4208 }
3629bb00 4209 if (!found_cpu_match)
29b0f896
AM		 4210 {
4211 found_reverse_match = 0;
4212 continue;
4213 }
c0f3af97 4214
6c30d220
L		 4215 /* Check if vector operands are valid. */
4216 if (check_VecOperands (t))
4217 continue;
4218
a683cc34
SP		 4219 /* Check if VEX operands are valid. */
4220 if (VEX_check_operands (t))
4221 continue;
4222
29b0f896
AM		 4223 /* We've found a match; break out of loop. */
4224 break;
4225 }
4226
4227 if (t == current_templates->end)
4228 {
4229 /* We found no match. */
a65babc9
L		 4230 const char *err_msg;
4231 switch (i.error)
4232 {
4233 default:
4234 abort ();
86e026a4 4235 case operand_size_mismatch:
a65babc9
L		 4236 err_msg = _("operand size mismatch");
4237 break;
4238 case operand_type_mismatch:
4239 err_msg = _("operand type mismatch");
4240 break;
4241 case register_type_mismatch:
4242 err_msg = _("register type mismatch");
4243 break;
4244 case number_of_operands_mismatch:
4245 err_msg = _("number of operands mismatch");
4246 break;
4247 case invalid_instruction_suffix:
4248 err_msg = _("invalid instruction suffix");
4249 break;
4250 case bad_imm4:
4251 err_msg = _("Imm4 isn't the first operand");
4252 break;
4253 case old_gcc_only:
4254 err_msg = _("only supported with old gcc");
4255 break;
4256 case unsupported_with_intel_mnemonic:
4257 err_msg = _("unsupported with Intel mnemonic");
4258 break;
4259 case unsupported_syntax:
4260 err_msg = _("unsupported syntax");
4261 break;
4262 case unsupported:
4263 err_msg = _("unsupported");
4264 break;
6c30d220
L		 4265 case invalid_vsib_address:
4266 err_msg = _("invalid VSIB address");
4267 break;
4268 case unsupported_vector_index_register:
4269 err_msg = _("unsupported vector index register");
4270 break;
a65babc9
L		 4271 }
4272 as_bad (_("%s for `%s'"), err_msg,
891edac4 4273 current_templates->start->name);
fa99fab2 4274 return NULL;
29b0f896 4275 }
252b5132 4276
29b0f896
AM		 4277 if (!quiet_warnings)
4278 {
4279 if (!intel_syntax
40fb9820
L		 4280 && (i.types[0].bitfield.jumpabsolute
4281 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 4282 {
4283 as_warn (_("indirect %s without `*'"), t->name);
4284 }
4285
40fb9820
L		 4286 if (t->opcode_modifier.isprefix
4287 && t->opcode_modifier.ignoresize)
29b0f896
AM		 4288 {
4289 /* Warn them that a data or address size prefix doesn't
4290 affect assembly of the next line of code. */
4291 as_warn (_("stand-alone `%s' prefix"), t->name);
4292 }
4293 }
4294
4295 /* Copy the template we found. */
4296 i.tm = *t;
539e75ad
L		 4297
4298 if (addr_prefix_disp != -1)
4299 i.tm.operand_types[addr_prefix_disp]
4300 = operand_types[addr_prefix_disp];
4301
29b0f896
AM		 4302 if (found_reverse_match)
4303 {
4304 /* If we found a reverse match we must alter the opcode
4305 direction bit. found_reverse_match holds bits to change
4306 (different for int & float insns). */
4307
4308 i.tm.base_opcode ^= found_reverse_match;
4309
539e75ad
L		 4310 i.tm.operand_types[0] = operand_types[1];
4311 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 4312 }
4313
fa99fab2 4314 return t;
29b0f896
AM		 4315}
4316
4317static int
e3bb37b5 4318check_string (void)
29b0f896 4319{
40fb9820
L		 4320 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4321 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 4322 {
4323 if (i.seg[0] != NULL && i.seg[0] != &es)
4324 {
a87af027 4325 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4326 i.tm.name,
a87af027
JB		 4327 mem_op + 1,
4328 register_prefix);
29b0f896
AM		 4329 return 0;
4330 }
4331 /* There's only ever one segment override allowed per instruction.
4332 This instruction possibly has a legal segment override on the
4333 second operand, so copy the segment to where non-string
4334 instructions store it, allowing common code. */
4335 i.seg[0] = i.seg[1];
4336 }
40fb9820 4337 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 4338 {
4339 if (i.seg[1] != NULL && i.seg[1] != &es)
4340 {
a87af027 4341 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4342 i.tm.name,
a87af027
JB		 4343 mem_op + 2,
4344 register_prefix);
29b0f896
AM		 4345 return 0;
4346 }
4347 }
4348 return 1;
4349}
4350
4351static int
543613e9 4352process_suffix (void)
29b0f896
AM		 4353{
4354 /* If matched instruction specifies an explicit instruction mnemonic
4355 suffix, use it. */
40fb9820
L		 4356 if (i.tm.opcode_modifier.size16)
4357 i.suffix = WORD_MNEM_SUFFIX;
4358 else if (i.tm.opcode_modifier.size32)
4359 i.suffix = LONG_MNEM_SUFFIX;
4360 else if (i.tm.opcode_modifier.size64)
4361 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 4362 else if (i.reg_operands)
4363 {
4364 /* If there's no instruction mnemonic suffix we try to invent one
4365 based on register operands. */
4366 if (!i.suffix)
4367 {
4368 /* We take i.suffix from the last register operand specified,
4369 Destination register type is more significant than source
381d071f
L		 4370 register type. crc32 in SSE4.2 prefers source register
4371 type. */
4372 if (i.tm.base_opcode == 0xf20f38f1)
4373 {
40fb9820
L		 4374 if (i.types[0].bitfield.reg16)
4375 i.suffix = WORD_MNEM_SUFFIX;
4376 else if (i.types[0].bitfield.reg32)
4377 i.suffix = LONG_MNEM_SUFFIX;
4378 else if (i.types[0].bitfield.reg64)
4379 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4380 }
9344ff29 4381 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4382 {
40fb9820 4383 if (i.types[0].bitfield.reg8)
20592a94
L		 4384 i.suffix = BYTE_MNEM_SUFFIX;
4385 }
381d071f
L		 4386
4387 if (!i.suffix)
4388 {
4389 int op;
4390
20592a94
L		 4391 if (i.tm.base_opcode == 0xf20f38f1
4392 || i.tm.base_opcode == 0xf20f38f0)
4393 {
4394 /* We have to know the operand size for crc32. */
4395 as_bad (_("ambiguous memory operand size for `%s`"),
4396 i.tm.name);
4397 return 0;
4398 }
4399
381d071f 4400 for (op = i.operands; --op >= 0;)
40fb9820 4401 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4402 {
40fb9820
L		 4403 if (i.types[op].bitfield.reg8)
4404 {
4405 i.suffix = BYTE_MNEM_SUFFIX;
4406 break;
4407 }
4408 else if (i.types[op].bitfield.reg16)
4409 {
4410 i.suffix = WORD_MNEM_SUFFIX;
4411 break;
4412 }
4413 else if (i.types[op].bitfield.reg32)
4414 {
4415 i.suffix = LONG_MNEM_SUFFIX;
4416 break;
4417 }
4418 else if (i.types[op].bitfield.reg64)
4419 {
4420 i.suffix = QWORD_MNEM_SUFFIX;
4421 break;
4422 }
381d071f
L		 4423 }
4424 }
29b0f896
AM		 4425 }
4426 else if (i.suffix == BYTE_MNEM_SUFFIX)
4427 {
2eb952a4
L		 4428 if (intel_syntax
4429 && i.tm.opcode_modifier.ignoresize
4430 && i.tm.opcode_modifier.no_bsuf)
4431 i.suffix = 0;
4432 else if (!check_byte_reg ())
29b0f896
AM		 4433 return 0;
4434 }
4435 else if (i.suffix == LONG_MNEM_SUFFIX)
4436 {
2eb952a4
L		 4437 if (intel_syntax
4438 && i.tm.opcode_modifier.ignoresize
4439 && i.tm.opcode_modifier.no_lsuf)
4440 i.suffix = 0;
4441 else if (!check_long_reg ())
29b0f896
AM		 4442 return 0;
4443 }
4444 else if (i.suffix == QWORD_MNEM_SUFFIX)
4445 {
955e1e6a
L		 4446 if (intel_syntax
4447 && i.tm.opcode_modifier.ignoresize
4448 && i.tm.opcode_modifier.no_qsuf)
4449 i.suffix = 0;
4450 else if (!check_qword_reg ())
29b0f896
AM		 4451 return 0;
4452 }
4453 else if (i.suffix == WORD_MNEM_SUFFIX)
4454 {
2eb952a4
L		 4455 if (intel_syntax
4456 && i.tm.opcode_modifier.ignoresize
4457 && i.tm.opcode_modifier.no_wsuf)
4458 i.suffix = 0;
4459 else if (!check_word_reg ())
29b0f896
AM		 4460 return 0;
4461 }
c0f3af97
L		 4462 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4463 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4464 {
c0f3af97 4465 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4466 should check if it is a valid suffix. */
4467 }
40fb9820 4468 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4469 /* Do nothing if the instruction is going to ignore the prefix. */
4470 ;
4471 else
4472 abort ();
4473 }
40fb9820 4474 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4475 && !i.suffix
4476 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4477 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4478 {
4479 i.suffix = stackop_size;
4480 }
9306ca4a
JB		 4481 else if (intel_syntax
4482 && !i.suffix
40fb9820
L		 4483 && (i.tm.operand_types[0].bitfield.jumpabsolute
4484 || i.tm.opcode_modifier.jumpbyte
4485 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4486 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4487 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4488 {
4489 switch (flag_code)
4490 {
4491 case CODE_64BIT:
40fb9820 4492 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4493 {
4494 i.suffix = QWORD_MNEM_SUFFIX;
4495 break;
4496 }
4497 case CODE_32BIT:
40fb9820 4498 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4499 i.suffix = LONG_MNEM_SUFFIX;
4500 break;
4501 case CODE_16BIT:
40fb9820 4502 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4503 i.suffix = WORD_MNEM_SUFFIX;
4504 break;
4505 }
4506 }
252b5132 4507
9306ca4a 4508 if (!i.suffix)
29b0f896 4509 {
9306ca4a
JB		 4510 if (!intel_syntax)
4511 {
40fb9820 4512 if (i.tm.opcode_modifier.w)
9306ca4a 4513 {
4eed87de
AM		 4514 as_bad (_("no instruction mnemonic suffix given and "
4515 "no register operands; can't size instruction"));
9306ca4a
JB		 4516 return 0;
4517 }
4518 }
4519 else
4520 {
40fb9820 4521 unsigned int suffixes;
7ab9ffdd 4522
40fb9820
L		 4523 suffixes = !i.tm.opcode_modifier.no_bsuf;
4524 if (!i.tm.opcode_modifier.no_wsuf)
4525 suffixes |= 1 << 1;
4526 if (!i.tm.opcode_modifier.no_lsuf)
4527 suffixes |= 1 << 2;
fc4adea1 4528 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4529 suffixes |= 1 << 3;
4530 if (!i.tm.opcode_modifier.no_ssuf)
4531 suffixes |= 1 << 4;
4532 if (!i.tm.opcode_modifier.no_qsuf)
4533 suffixes |= 1 << 5;
4534
4535 /* There are more than suffix matches. */
4536 if (i.tm.opcode_modifier.w
9306ca4a 4537 || ((suffixes & (suffixes - 1))
40fb9820
L		 4538 && !i.tm.opcode_modifier.defaultsize
4539 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4540 {
4541 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4542 return 0;
4543 }
4544 }
29b0f896 4545 }
252b5132 4546
9306ca4a
JB		 4547 /* Change the opcode based on the operand size given by i.suffix;
4548 We don't need to change things for byte insns. */
4549
582d5edd
L		 4550 if (i.suffix
4551 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4552 && i.suffix != XMMWORD_MNEM_SUFFIX
4553 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4554 {
4555 /* It's not a byte, select word/dword operation. */
40fb9820 4556 if (i.tm.opcode_modifier.w)
29b0f896 4557 {
40fb9820 4558 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4559 i.tm.base_opcode |= 8;
4560 else
4561 i.tm.base_opcode |= 1;
4562 }
0f3f3d8b 4563
29b0f896
AM		 4564 /* Now select between word & dword operations via the operand
4565 size prefix, except for instructions that will ignore this
4566 prefix anyway. */
ca61edf2 4567 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4568 {
ca61edf2
L		 4569 /* The address size override prefix changes the size of the
4570 first operand. */
40fb9820
L		 4571 if ((flag_code == CODE_32BIT
4572 && i.op->regs[0].reg_type.bitfield.reg16)
4573 || (flag_code != CODE_32BIT
4574 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4575 if (!add_prefix (ADDR_PREFIX_OPCODE))
4576 return 0;
4577 }
4578 else if (i.suffix != QWORD_MNEM_SUFFIX
4579 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4580 && !i.tm.opcode_modifier.ignoresize
4581 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4582 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4583 || (flag_code == CODE_64BIT
40fb9820 4584 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4585 {
4586 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4587
40fb9820 4588 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4589 prefix = ADDR_PREFIX_OPCODE;
252b5132 4590
29b0f896
AM		 4591 if (!add_prefix (prefix))
4592 return 0;
24eab124 4593 }
252b5132 4594
29b0f896
AM		 4595 /* Set mode64 for an operand. */
4596 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4597 && flag_code == CODE_64BIT
40fb9820 4598 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4599 {
4600 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4601 need rex64. cmpxchg8b is also a special case. */
4602 if (! (i.operands == 2
4603 && i.tm.base_opcode == 0x90
4604 && i.tm.extension_opcode == None
0dfbf9d7
L		 4605 && operand_type_equal (&i.types [0], &acc64)
4606 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4607 && ! (i.operands == 1
4608 && i.tm.base_opcode == 0xfc7
4609 && i.tm.extension_opcode == 1
40fb9820
L		 4610 && !operand_type_check (i.types [0], reg)
4611 && operand_type_check (i.types [0], anymem)))
f6bee062 4612 i.rex |= REX_W;
46e883c5 4613 }
3e73aa7c 4614
29b0f896
AM		 4615 /* Size floating point instruction. */
4616 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4617 if (i.tm.opcode_modifier.floatmf)
543613e9 4618 i.tm.base_opcode ^= 4;
29b0f896 4619 }
7ecd2f8b 4620
29b0f896
AM		 4621 return 1;
4622}
3e73aa7c 4623
29b0f896 4624static int
543613e9 4625check_byte_reg (void)
29b0f896
AM		 4626{
4627 int op;
543613e9 4628
29b0f896
AM		 4629 for (op = i.operands; --op >= 0;)
4630 {
4631 /* If this is an eight bit register, it's OK. If it's the 16 or
4632 32 bit version of an eight bit register, we will just use the
4633 low portion, and that's OK too. */
40fb9820 4634 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4635 continue;
4636
9344ff29
L		 4637 /* crc32 doesn't generate this warning. */
4638 if (i.tm.base_opcode == 0xf20f38f0)
4639 continue;
4640
40fb9820
L		 4641 if ((i.types[op].bitfield.reg16
4642 || i.types[op].bitfield.reg32
4643 || i.types[op].bitfield.reg64)
4644 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4645 {
4646 /* Prohibit these changes in the 64bit mode, since the
4647 lowering is more complicated. */
4648 if (flag_code == CODE_64BIT
40fb9820 4649 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4650 {
2b5d6a91 4651 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 4652 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4653 i.suffix);
4654 return 0;
4655 }
4656#if REGISTER_WARNINGS
4657 if (!quiet_warnings
40fb9820 4658 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4659 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4660 register_prefix,
40fb9820 4661 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4662 ? REGNAM_AL - REGNAM_AX
4663 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4664 register_prefix,
29b0f896
AM		 4665 i.op[op].regs->reg_name,
4666 i.suffix);
4667#endif
4668 continue;
4669 }
4670 /* Any other register is bad. */
40fb9820
L		 4671 if (i.types[op].bitfield.reg16
4672 || i.types[op].bitfield.reg32
4673 || i.types[op].bitfield.reg64
4674 || i.types[op].bitfield.regmmx
4675 || i.types[op].bitfield.regxmm
c0f3af97 4676 || i.types[op].bitfield.regymm
40fb9820
L		 4677 || i.types[op].bitfield.sreg2
4678 || i.types[op].bitfield.sreg3
4679 || i.types[op].bitfield.control
4680 || i.types[op].bitfield.debug
4681 || i.types[op].bitfield.test
4682 || i.types[op].bitfield.floatreg
4683 || i.types[op].bitfield.floatacc)
29b0f896 4684 {
a540244d
L		 4685 as_bad (_("`%s%s' not allowed with `%s%c'"),
4686 register_prefix,
29b0f896
AM		 4687 i.op[op].regs->reg_name,
4688 i.tm.name,
4689 i.suffix);
4690 return 0;
4691 }
4692 }
4693 return 1;
4694}
4695
4696static int
e3bb37b5 4697check_long_reg (void)
29b0f896
AM		 4698{
4699 int op;
4700
4701 for (op = i.operands; --op >= 0;)
4702 /* Reject eight bit registers, except where the template requires
4703 them. (eg. movzb) */
40fb9820
L		 4704 if (i.types[op].bitfield.reg8
4705 && (i.tm.operand_types[op].bitfield.reg16
4706 || i.tm.operand_types[op].bitfield.reg32
4707 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4708 {
a540244d
L		 4709 as_bad (_("`%s%s' not allowed with `%s%c'"),
4710 register_prefix,
29b0f896
AM		 4711 i.op[op].regs->reg_name,
4712 i.tm.name,
4713 i.suffix);
4714 return 0;
4715 }
4716 /* Warn if the e prefix on a general reg is missing. */
4717 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4718 && i.types[op].bitfield.reg16
4719 && (i.tm.operand_types[op].bitfield.reg32
4720 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4721 {
4722 /* Prohibit these changes in the 64bit mode, since the
4723 lowering is more complicated. */
4724 if (flag_code == CODE_64BIT)
252b5132 4725 {
2b5d6a91 4726 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 4727 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4728 i.suffix);
4729 return 0;
252b5132 4730 }
29b0f896
AM		 4731#if REGISTER_WARNINGS
4732 else
a540244d
L		 4733 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4734 register_prefix,
29b0f896 4735 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4736 register_prefix,
29b0f896
AM		 4737 i.op[op].regs->reg_name,
4738 i.suffix);
4739#endif
252b5132 4740 }
29b0f896 4741 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4742 else if (i.types[op].bitfield.reg64
4743 && (i.tm.operand_types[op].bitfield.reg32
4744 || i.tm.operand_types[op].bitfield.acc))
252b5132 4745 {
34828aad 4746 if (intel_syntax
ca61edf2 4747 && i.tm.opcode_modifier.toqword
40fb9820 4748 && !i.types[0].bitfield.regxmm)
34828aad 4749 {
ca61edf2 4750 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4751 i.suffix = QWORD_MNEM_SUFFIX;
4752 }
4753 else
4754 {
2b5d6a91 4755 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 4756 register_prefix, i.op[op].regs->reg_name,
4757 i.suffix);
4758 return 0;
4759 }
29b0f896
AM		 4760 }
4761 return 1;
4762}
252b5132 4763
29b0f896 4764static int
e3bb37b5 4765check_qword_reg (void)
29b0f896
AM		 4766{
4767 int op;
252b5132 4768
29b0f896
AM		 4769 for (op = i.operands; --op >= 0; )
4770 /* Reject eight bit registers, except where the template requires
4771 them. (eg. movzb) */
40fb9820
L		 4772 if (i.types[op].bitfield.reg8
4773 && (i.tm.operand_types[op].bitfield.reg16
4774 || i.tm.operand_types[op].bitfield.reg32
4775 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4776 {
a540244d
L		 4777 as_bad (_("`%s%s' not allowed with `%s%c'"),
4778 register_prefix,
29b0f896
AM		 4779 i.op[op].regs->reg_name,
4780 i.tm.name,
4781 i.suffix);
4782 return 0;
4783 }
4784 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4785 else if ((i.types[op].bitfield.reg16
4786 || i.types[op].bitfield.reg32)
4787 && (i.tm.operand_types[op].bitfield.reg32
4788 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4789 {
4790 /* Prohibit these changes in the 64bit mode, since the
4791 lowering is more complicated. */
34828aad 4792 if (intel_syntax
ca61edf2 4793 && i.tm.opcode_modifier.todword
40fb9820 4794 && !i.types[0].bitfield.regxmm)
34828aad 4795 {
ca61edf2 4796 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4797 i.suffix = LONG_MNEM_SUFFIX;
4798 }
4799 else
4800 {
2b5d6a91 4801 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 4802 register_prefix, i.op[op].regs->reg_name,
4803 i.suffix);
4804 return 0;
4805 }
252b5132 4806 }
29b0f896
AM		 4807 return 1;
4808}
252b5132 4809
29b0f896 4810static int
e3bb37b5 4811check_word_reg (void)
29b0f896
AM		 4812{
4813 int op;
4814 for (op = i.operands; --op >= 0;)
4815 /* Reject eight bit registers, except where the template requires
4816 them. (eg. movzb) */
40fb9820
L		 4817 if (i.types[op].bitfield.reg8
4818 && (i.tm.operand_types[op].bitfield.reg16
4819 || i.tm.operand_types[op].bitfield.reg32
4820 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4821 {
a540244d
L		 4822 as_bad (_("`%s%s' not allowed with `%s%c'"),
4823 register_prefix,
29b0f896
AM		 4824 i.op[op].regs->reg_name,
4825 i.tm.name,
4826 i.suffix);
4827 return 0;
4828 }
4829 /* Warn if the e prefix on a general reg is present. */
4830 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4831 && i.types[op].bitfield.reg32
4832 && (i.tm.operand_types[op].bitfield.reg16
4833 || i.tm.operand_types[op].bitfield.acc))
252b5132 4834 {
29b0f896
AM		 4835 /* Prohibit these changes in the 64bit mode, since the
4836 lowering is more complicated. */
4837 if (flag_code == CODE_64BIT)
252b5132 4838 {
2b5d6a91 4839 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 4840 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4841 i.suffix);
4842 return 0;
252b5132 4843 }
29b0f896
AM		 4844 else
4845#if REGISTER_WARNINGS
a540244d
L		 4846 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4847 register_prefix,
29b0f896 4848 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4849 register_prefix,
29b0f896
AM		 4850 i.op[op].regs->reg_name,
4851 i.suffix);
4852#endif
4853 }
4854 return 1;
4855}
252b5132 4856
29b0f896 4857static int
40fb9820 4858update_imm (unsigned int j)
29b0f896 4859{
bc0844ae 4860 i386_operand_type overlap = i.types[j];
40fb9820
L		 4861 if ((overlap.bitfield.imm8
4862 || overlap.bitfield.imm8s
4863 || overlap.bitfield.imm16
4864 || overlap.bitfield.imm32
4865 || overlap.bitfield.imm32s
4866 || overlap.bitfield.imm64)
0dfbf9d7
L		 4867 && !operand_type_equal (&overlap, &imm8)
4868 && !operand_type_equal (&overlap, &imm8s)
4869 && !operand_type_equal (&overlap, &imm16)
4870 && !operand_type_equal (&overlap, &imm32)
4871 && !operand_type_equal (&overlap, &imm32s)
4872 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4873 {
4874 if (i.suffix)
4875 {
40fb9820
L		 4876 i386_operand_type temp;
4877
0dfbf9d7 4878 operand_type_set (&temp, 0);
7ab9ffdd 4879 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 4880 {
4881 temp.bitfield.imm8 = overlap.bitfield.imm8;
4882 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4883 }
4884 else if (i.suffix == WORD_MNEM_SUFFIX)
4885 temp.bitfield.imm16 = overlap.bitfield.imm16;
4886 else if (i.suffix == QWORD_MNEM_SUFFIX)
4887 {
4888 temp.bitfield.imm64 = overlap.bitfield.imm64;
4889 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4890 }
4891 else
4892 temp.bitfield.imm32 = overlap.bitfield.imm32;
4893 overlap = temp;
29b0f896 4894 }
0dfbf9d7
L		 4895 else if (operand_type_equal (&overlap, &imm16_32_32s)
4896 || operand_type_equal (&overlap, &imm16_32)
4897 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4898 {
40fb9820 4899 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4900 overlap = imm16;
40fb9820 4901 else
65da13b5 4902 overlap = imm32s;
29b0f896 4903 }
0dfbf9d7
L		 4904 if (!operand_type_equal (&overlap, &imm8)
4905 && !operand_type_equal (&overlap, &imm8s)
4906 && !operand_type_equal (&overlap, &imm16)
4907 && !operand_type_equal (&overlap, &imm32)
4908 && !operand_type_equal (&overlap, &imm32s)
4909 && !operand_type_equal (&overlap, &imm64))
29b0f896 4910 {
4eed87de
AM		 4911 as_bad (_("no instruction mnemonic suffix given; "
4912 "can't determine immediate size"));
29b0f896
AM		 4913 return 0;
4914 }
4915 }
40fb9820 4916 i.types[j] = overlap;
29b0f896 4917
40fb9820
L		 4918 return 1;
4919}
4920
4921static int
4922finalize_imm (void)
4923{
bc0844ae 4924 unsigned int j, n;
29b0f896 4925
bc0844ae
L		 4926 /* Update the first 2 immediate operands. */
4927 n = i.operands > 2 ? 2 : i.operands;
4928 if (n)
4929 {
4930 for (j = 0; j < n; j++)
4931 if (update_imm (j) == 0)
4932 return 0;
40fb9820 4933
bc0844ae
L		 4934 /* The 3rd operand can't be immediate operand. */
4935 gas_assert (operand_type_check (i.types[2], imm) == 0);
4936 }
29b0f896
AM		 4937
4938 return 1;
4939}
4940
c0f3af97
L		 4941static int
4942bad_implicit_operand (int xmm)
4943{
91d6fa6a
NC		 4944 const char *ireg = xmm ? "xmm0" : "ymm0";
4945
c0f3af97
L		 4946 if (intel_syntax)
4947 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 4948 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4949 else
4950 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 4951 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4952 return 0;
4953}
4954
29b0f896 4955static int
e3bb37b5 4956process_operands (void)
29b0f896
AM		 4957{
4958 /* Default segment register this instruction will use for memory
4959 accesses. 0 means unknown. This is only for optimizing out
4960 unnecessary segment overrides. */
4961 const seg_entry *default_seg = 0;
4962
2426c15f 4963 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 4964 {
91d6fa6a
NC		 4965 unsigned int dupl = i.operands;
4966 unsigned int dest = dupl - 1;
9fcfb3d7
L		 4967 unsigned int j;
4968
c0f3af97 4969 /* The destination must be an xmm register. */
9c2799c2 4970 gas_assert (i.reg_operands
91d6fa6a 4971 && MAX_OPERANDS > dupl
7ab9ffdd 4972 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 4973
4974 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4975 {
c0f3af97 4976 /* The first operand is implicit and must be xmm0. */
9c2799c2 4977 gas_assert (operand_type_equal (&i.types[0], &regxmm));
c0f3af97
L		 4978 if (i.op[0].regs->reg_num != 0)
4979 return bad_implicit_operand (1);
4980
8cd7925b 4981 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 4982 {
4983 /* Keep xmm0 for instructions with VEX prefix and 3
4984 sources. */
4985 goto duplicate;
4986 }
e2ec9d29 4987 else
c0f3af97
L		 4988 {
4989 /* We remove the first xmm0 and keep the number of
4990 operands unchanged, which in fact duplicates the
4991 destination. */
4992 for (j = 1; j < i.operands; j++)
4993 {
4994 i.op[j - 1] = i.op[j];
4995 i.types[j - 1] = i.types[j];
4996 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4997 }
4998 }
4999 }
5000 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5001 {
91d6fa6a 5002 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5003 && (i.tm.opcode_modifier.vexsources
5004 == VEX3SOURCES));
c0f3af97
L		 5005
5006 /* Add the implicit xmm0 for instructions with VEX prefix
5007 and 3 sources. */
5008 for (j = i.operands; j > 0; j--)
5009 {
5010 i.op[j] = i.op[j - 1];
5011 i.types[j] = i.types[j - 1];
5012 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5013 }
5014 i.op[0].regs
5015 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5016 i.types[0] = regxmm;
c0f3af97
L		 5017 i.tm.operand_types[0] = regxmm;
5018
5019 i.operands += 2;
5020 i.reg_operands += 2;
5021 i.tm.operands += 2;
5022
91d6fa6a 5023 dupl++;
c0f3af97 5024 dest++;
91d6fa6a
NC		 5025 i.op[dupl] = i.op[dest];
5026 i.types[dupl] = i.types[dest];
5027 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5028 }
c0f3af97
L		 5029 else
5030 {
5031duplicate:
5032 i.operands++;
5033 i.reg_operands++;
5034 i.tm.operands++;
5035
91d6fa6a
NC		 5036 i.op[dupl] = i.op[dest];
5037 i.types[dupl] = i.types[dest];
5038 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5039 }
5040
5041 if (i.tm.opcode_modifier.immext)
5042 process_immext ();
5043 }
5044 else if (i.tm.opcode_modifier.firstxmm0)
5045 {
5046 unsigned int j;
5047
5048 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 5049 gas_assert (i.reg_operands
7ab9ffdd
L		 5050 && (operand_type_equal (&i.types[0], &regxmm)
5051 || operand_type_equal (&i.types[0], &regymm)));
c0f3af97
L		 5052 if (i.op[0].regs->reg_num != 0)
5053 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5054
5055 for (j = 1; j < i.operands; j++)
5056 {
5057 i.op[j - 1] = i.op[j];
5058 i.types[j - 1] = i.types[j];
5059
5060 /* We need to adjust fields in i.tm since they are used by
5061 build_modrm_byte. */
5062 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5063 }
5064
e2ec9d29
L		 5065 i.operands--;
5066 i.reg_operands--;
e2ec9d29
L		 5067 i.tm.operands--;
5068 }
5069 else if (i.tm.opcode_modifier.regkludge)
5070 {
5071 /* The imul $imm, %reg instruction is converted into
5072 imul $imm, %reg, %reg, and the clr %reg instruction
5073 is converted into xor %reg, %reg. */
5074
5075 unsigned int first_reg_op;
5076
5077 if (operand_type_check (i.types[0], reg))
5078 first_reg_op = 0;
5079 else
5080 first_reg_op = 1;
5081 /* Pretend we saw the extra register operand. */
9c2799c2 5082 gas_assert (i.reg_operands == 1
7ab9ffdd 5083 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5084 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5085 i.types[first_reg_op + 1] = i.types[first_reg_op];
5086 i.operands++;
5087 i.reg_operands++;
29b0f896
AM		 5088 }
5089
40fb9820 5090 if (i.tm.opcode_modifier.shortform)
29b0f896 5091 {
40fb9820
L		 5092 if (i.types[0].bitfield.sreg2
5093 || i.types[0].bitfield.sreg3)
29b0f896 5094 {
4eed87de
AM		 5095 if (i.tm.base_opcode == POP_SEG_SHORT
5096 && i.op[0].regs->reg_num == 1)
29b0f896 5097 {
a87af027 5098 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5099 return 0;
29b0f896 5100 }
4eed87de
AM		 5101 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5102 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5103 i.rex |= REX_B;
4eed87de
AM		 5104 }
5105 else
5106 {
7ab9ffdd 5107 /* The register or float register operand is in operand
85f10a01 5108 0 or 1. */
40fb9820 5109 unsigned int op;
7ab9ffdd
L		 5110
5111 if (i.types[0].bitfield.floatreg
5112 || operand_type_check (i.types[0], reg))
5113 op = 0;
5114 else
5115 op = 1;
4eed87de
AM		 5116 /* Register goes in low 3 bits of opcode. */
5117 i.tm.base_opcode |= i.op[op].regs->reg_num;
5118 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5119 i.rex |= REX_B;
40fb9820 5120 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5121 {
4eed87de
AM		 5122 /* Warn about some common errors, but press on regardless.
5123 The first case can be generated by gcc (<= 2.8.1). */
5124 if (i.operands == 2)
5125 {
5126 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5127 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5128 register_prefix, i.op[!intel_syntax].regs->reg_name,
5129 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5130 }
5131 else
5132 {
5133 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5134 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5135 register_prefix, i.op[0].regs->reg_name);
4eed87de 5136 }
29b0f896
AM		 5137 }
5138 }
5139 }
40fb9820 5140 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5141 {
5142 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5143 must be put into the modrm byte). Now, we make the modrm and
5144 index base bytes based on all the info we've collected. */
29b0f896
AM		 5145
5146 default_seg = build_modrm_byte ();
5147 }
8a2ed489 5148 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5149 {
5150 default_seg = &ds;
5151 }
40fb9820 5152 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5153 {
5154 /* For the string instructions that allow a segment override
5155 on one of their operands, the default segment is ds. */
5156 default_seg = &ds;
5157 }
5158
75178d9d
L		 5159 if (i.tm.base_opcode == 0x8d /* lea */
5160 && i.seg[0]
5161 && !quiet_warnings)
30123838 5162 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5163
5164 /* If a segment was explicitly specified, and the specified segment
5165 is not the default, use an opcode prefix to select it. If we
5166 never figured out what the default segment is, then default_seg
5167 will be zero at this point, and the specified segment prefix will
5168 always be used. */
29b0f896
AM		 5169 if ((i.seg[0]) && (i.seg[0] != default_seg))
5170 {
5171 if (!add_prefix (i.seg[0]->seg_prefix))
5172 return 0;
5173 }
5174 return 1;
5175}
5176
5177static const seg_entry *
e3bb37b5 5178build_modrm_byte (void)
29b0f896
AM		 5179{
5180 const seg_entry *default_seg = 0;
c0f3af97 5181 unsigned int source, dest;
8cd7925b 5182 int vex_3_sources;
c0f3af97
L		 5183
5184 /* The first operand of instructions with VEX prefix and 3 sources
5185 must be VEX_Imm4. */
8cd7925b 5186 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5187 if (vex_3_sources)
5188 {
91d6fa6a 5189 unsigned int nds, reg_slot;
4c2c6516 5190 expressionS *exp;
c0f3af97 5191
922d8de8 5192 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5193 && i.tm.opcode_modifier.immext)
5194 {
5195 dest = i.operands - 2;
5196 gas_assert (dest == 3);
5197 }
922d8de8 5198 else
a683cc34 5199 dest = i.operands - 1;
c0f3af97 5200 nds = dest - 1;
922d8de8 5201
a683cc34
SP		 5202 /* There are 2 kinds of instructions:
5203 1. 5 operands: 4 register operands or 3 register operands
5204 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5205 VexW0 or VexW1. The destination must be either XMM or YMM
5206 register.
5207 2. 4 operands: 4 register operands or 3 register operands
5208 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5209 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5210 || (i.reg_operands == 3 && i.mem_operands == 1))
5211 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5212 && (i.tm.opcode_modifier.veximmext
5213 || (i.imm_operands == 1
5214 && i.types[0].bitfield.vec_imm4
5215 && (i.tm.opcode_modifier.vexw == VEXW0
5216 || i.tm.opcode_modifier.vexw == VEXW1)
5217 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
5218 || operand_type_equal (&i.tm.operand_types[dest], &regymm)))));
5219
5220 if (i.imm_operands == 0)
5221 {
5222 /* When there is no immediate operand, generate an 8bit
5223 immediate operand to encode the first operand. */
5224 exp = &im_expressions[i.imm_operands++];
5225 i.op[i.operands].imms = exp;
5226 i.types[i.operands] = imm8;
5227 i.operands++;
5228 /* If VexW1 is set, the first operand is the source and
5229 the second operand is encoded in the immediate operand. */
5230 if (i.tm.opcode_modifier.vexw == VEXW1)
5231 {
5232 source = 0;
5233 reg_slot = 1;
5234 }
5235 else
5236 {
5237 source = 1;
5238 reg_slot = 0;
5239 }
5240
5241 /* FMA swaps REG and NDS. */
5242 if (i.tm.cpu_flags.bitfield.cpufma)
5243 {
5244 unsigned int tmp;
5245 tmp = reg_slot;
5246 reg_slot = nds;
5247 nds = tmp;
5248 }
5249
24981e7b
L		 5250 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5251 &regxmm)
a683cc34
SP		 5252 || operand_type_equal (&i.tm.operand_types[reg_slot],
5253 &regymm));
5254 exp->X_op = O_constant;
5255 exp->X_add_number
5256 = ((i.op[reg_slot].regs->reg_num
24981e7b
L		 5257 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
5258 << 4);
a683cc34 5259 }
922d8de8 5260 else
a683cc34
SP		 5261 {
5262 unsigned int imm_slot;
5263
5264 if (i.tm.opcode_modifier.vexw == VEXW0)
5265 {
5266 /* If VexW0 is set, the third operand is the source and
5267 the second operand is encoded in the immediate
5268 operand. */
5269 source = 2;
5270 reg_slot = 1;
5271 }
5272 else
5273 {
5274 /* VexW1 is set, the second operand is the source and
5275 the third operand is encoded in the immediate
5276 operand. */
5277 source = 1;
5278 reg_slot = 2;
5279 }
5280
5281 if (i.tm.opcode_modifier.immext)
5282 {
5283 /* When ImmExt is set, the immdiate byte is the last
5284 operand. */
5285 imm_slot = i.operands - 1;
5286 source--;
5287 reg_slot--;
5288 }
5289 else
5290 {
5291 imm_slot = 0;
5292
5293 /* Turn on Imm8 so that output_imm will generate it. */
5294 i.types[imm_slot].bitfield.imm8 = 1;
5295 }
5296
24981e7b
L		 5297 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5298 &regxmm)
5299 || operand_type_equal (&i.tm.operand_types[reg_slot],
5300 &regymm));
a683cc34
SP		 5301 i.op[imm_slot].imms->X_add_number
5302 |= ((i.op[reg_slot].regs->reg_num
24981e7b
L		 5303 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
5304 << 4);
a683cc34
SP		 5305 }
5306
5307 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
5308 || operand_type_equal (&i.tm.operand_types[nds],
5309 &regymm));
dae39acc 5310 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 5311 }
5312 else
5313 source = dest = 0;
29b0f896
AM		 5314
5315 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5316 implicit registers do not count. If there are 3 register
5317 operands, it must be a instruction with VexNDS. For a
5318 instruction with VexNDD, the destination register is encoded
5319 in VEX prefix. If there are 4 register operands, it must be
5320 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 5321 if (i.mem_operands == 0
5322 && ((i.reg_operands == 2
2426c15f 5323 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 5324 || (i.reg_operands == 3
2426c15f 5325 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 5326 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5327 {
cab737b9
L		 5328 switch (i.operands)
5329 {
5330 case 2:
5331 source = 0;
5332 break;
5333 case 3:
c81128dc
L		 5334 /* When there are 3 operands, one of them may be immediate,
5335 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5336 the first operand must be shift count register (cl) or it
5337 is an instruction with VexNDS. */
9c2799c2 5338 gas_assert (i.imm_operands == 1
7ab9ffdd 5339 || (i.imm_operands == 0
2426c15f 5340 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 5341 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5342 if (operand_type_check (i.types[0], imm)
5343 || i.types[0].bitfield.shiftcount)
5344 source = 1;
5345 else
5346 source = 0;
cab737b9
L		 5347 break;
5348 case 4:
368d64cc
L		 5349 /* When there are 4 operands, the first two must be 8bit
5350 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5351 one.
5352
5353 For instructions with VexNDS, if the first operand
5354 an imm8, the source operand is the 2nd one. If the last
5355 operand is imm8, the source operand is the first one. */
9c2799c2 5356 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 5357 && i.types[0].bitfield.imm8
5358 && i.types[1].bitfield.imm8)
2426c15f 5359 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 5360 && i.imm_operands == 1
5361 && (i.types[0].bitfield.imm8
5362 || i.types[i.operands - 1].bitfield.imm8)));
9f2670f2
L		 5363 if (i.imm_operands == 2)
5364 source = 2;
5365 else
c0f3af97
L		 5366 {
5367 if (i.types[0].bitfield.imm8)
5368 source = 1;
5369 else
5370 source = 0;
5371 }
c0f3af97
L		 5372 break;
5373 case 5:
cab737b9
L		 5374 break;
5375 default:
5376 abort ();
5377 }
5378
c0f3af97
L		 5379 if (!vex_3_sources)
5380 {
5381 dest = source + 1;
5382
2426c15f 5383 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97
L		 5384 {
5385 /* For instructions with VexNDS, the register-only
f12dc422
L		 5386 source operand must be 32/64bit integer, XMM or
5387 YMM register. It is encoded in VEX prefix. We
5388 need to clear RegMem bit before calling
5389 operand_type_equal. */
5390
5391 i386_operand_type op;
5392 unsigned int vvvv;
5393
5394 /* Check register-only source operand when two source
5395 operands are swapped. */
5396 if (!i.tm.operand_types[source].bitfield.baseindex
5397 && i.tm.operand_types[dest].bitfield.baseindex)
5398 {
5399 vvvv = source;
5400 source = dest;
5401 }
5402 else
5403 vvvv = dest;
5404
5405 op = i.tm.operand_types[vvvv];
fa99fab2 5406 op.bitfield.regmem = 0;
c0f3af97 5407 if ((dest + 1) >= i.operands
f12dc422
L		 5408 || (op.bitfield.reg32 != 1
5409 && !op.bitfield.reg64 != 1
5410 && !operand_type_equal (&op, &regxmm)
fa99fab2 5411 && !operand_type_equal (&op, &regymm)))
c0f3af97 5412 abort ();
f12dc422 5413 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 5414 dest++;
5415 }
5416 }
29b0f896
AM		 5417
5418 i.rm.mode = 3;
5419 /* One of the register operands will be encoded in the i.tm.reg
5420 field, the other in the combined i.tm.mode and i.tm.regmem
5421 fields. If no form of this instruction supports a memory
5422 destination operand, then we assume the source operand may
5423 sometimes be a memory operand and so we need to store the
5424 destination in the i.rm.reg field. */
40fb9820
L		 5425 if (!i.tm.operand_types[dest].bitfield.regmem
5426 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5427 {
5428 i.rm.reg = i.op[dest].regs->reg_num;
5429 i.rm.regmem = i.op[source].regs->reg_num;
5430 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5431 i.rex |= REX_R;
29b0f896 5432 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5433 i.rex |= REX_B;
29b0f896
AM		 5434 }
5435 else
5436 {
5437 i.rm.reg = i.op[source].regs->reg_num;
5438 i.rm.regmem = i.op[dest].regs->reg_num;
5439 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5440 i.rex |= REX_B;
29b0f896 5441 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5442 i.rex |= REX_R;
29b0f896 5443 }
161a04f6 5444 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5445 {
40fb9820
L		 5446 if (!i.types[0].bitfield.control
5447 && !i.types[1].bitfield.control)
c4a530c5 5448 abort ();
161a04f6 5449 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5450 add_prefix (LOCK_PREFIX_OPCODE);
5451 }
29b0f896
AM		 5452 }
5453 else
5454 { /* If it's not 2 reg operands... */
c0f3af97
L		 5455 unsigned int mem;
5456
29b0f896
AM		 5457 if (i.mem_operands)
5458 {
5459 unsigned int fake_zero_displacement = 0;
99018f42 5460 unsigned int op;
4eed87de 5461
7ab9ffdd
L		 5462 for (op = 0; op < i.operands; op++)
5463 if (operand_type_check (i.types[op], anymem))
5464 break;
7ab9ffdd 5465 gas_assert (op < i.operands);
29b0f896 5466
6c30d220
L		 5467 if (i.tm.opcode_modifier.vecsib)
5468 {
5469 if (i.index_reg->reg_num == RegEiz
5470 || i.index_reg->reg_num == RegRiz)
5471 abort ();
5472
5473 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5474 if (!i.base_reg)
5475 {
5476 i.sib.base = NO_BASE_REGISTER;
5477 i.sib.scale = i.log2_scale_factor;
5478 i.types[op].bitfield.disp8 = 0;
5479 i.types[op].bitfield.disp16 = 0;
5480 i.types[op].bitfield.disp64 = 0;
5481 if (flag_code != CODE_64BIT)
5482 {
5483 /* Must be 32 bit */
5484 i.types[op].bitfield.disp32 = 1;
5485 i.types[op].bitfield.disp32s = 0;
5486 }
5487 else
5488 {
5489 i.types[op].bitfield.disp32 = 0;
5490 i.types[op].bitfield.disp32s = 1;
5491 }
5492 }
5493 i.sib.index = i.index_reg->reg_num;
5494 if ((i.index_reg->reg_flags & RegRex) != 0)
5495 i.rex |= REX_X;
5496 }
5497
29b0f896
AM		 5498 default_seg = &ds;
5499
5500 if (i.base_reg == 0)
5501 {
5502 i.rm.mode = 0;
5503 if (!i.disp_operands)
6c30d220
L		 5504 {
5505 fake_zero_displacement = 1;
5506 /* Instructions with VSIB byte need 32bit displacement
5507 if there is no base register. */
5508 if (i.tm.opcode_modifier.vecsib)
5509 i.types[op].bitfield.disp32 = 1;
5510 }
29b0f896
AM		 5511 if (i.index_reg == 0)
5512 {
6c30d220 5513 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 5514 /* Operand is just <disp> */
20f0a1fc 5515 if (flag_code == CODE_64BIT)
29b0f896
AM		 5516 {
5517 /* 64bit mode overwrites the 32bit absolute
5518 addressing by RIP relative addressing and
5519 absolute addressing is encoded by one of the
5520 redundant SIB forms. */
5521 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5522 i.sib.base = NO_BASE_REGISTER;
5523 i.sib.index = NO_INDEX_REGISTER;
fc225355 5524 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5525 ? disp32s : disp32);
20f0a1fc 5526 }
fc225355
L		 5527 else if ((flag_code == CODE_16BIT)
5528 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5529 {
5530 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5531 i.types[op] = disp16;
20f0a1fc
NC		 5532 }
5533 else
5534 {
5535 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5536 i.types[op] = disp32;
29b0f896
AM		 5537 }
5538 }
6c30d220 5539 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 5540 {
6c30d220 5541 /* !i.base_reg && i.index_reg */
db51cc60
L		 5542 if (i.index_reg->reg_num == RegEiz
5543 || i.index_reg->reg_num == RegRiz)
5544 i.sib.index = NO_INDEX_REGISTER;
5545 else
5546 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5547 i.sib.base = NO_BASE_REGISTER;
5548 i.sib.scale = i.log2_scale_factor;
5549 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5550 i.types[op].bitfield.disp8 = 0;
5551 i.types[op].bitfield.disp16 = 0;
5552 i.types[op].bitfield.disp64 = 0;
29b0f896 5553 if (flag_code != CODE_64BIT)
40fb9820
L		 5554 {
5555 /* Must be 32 bit */
5556 i.types[op].bitfield.disp32 = 1;
5557 i.types[op].bitfield.disp32s = 0;
5558 }
29b0f896 5559 else
40fb9820
L		 5560 {
5561 i.types[op].bitfield.disp32 = 0;
5562 i.types[op].bitfield.disp32s = 1;
5563 }
29b0f896 5564 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5565 i.rex |= REX_X;
29b0f896
AM		 5566 }
5567 }
5568 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5569 else if (i.base_reg->reg_num == RegRip ||
5570 i.base_reg->reg_num == RegEip)
29b0f896 5571 {
6c30d220 5572 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 5573 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5574 i.types[op].bitfield.disp8 = 0;
5575 i.types[op].bitfield.disp16 = 0;
5576 i.types[op].bitfield.disp32 = 0;
5577 i.types[op].bitfield.disp32s = 1;
5578 i.types[op].bitfield.disp64 = 0;
71903a11 5579 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5580 if (! i.disp_operands)
5581 fake_zero_displacement = 1;
29b0f896 5582 }
40fb9820 5583 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 5584 {
6c30d220 5585 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 5586 switch (i.base_reg->reg_num)
5587 {
5588 case 3: /* (%bx) */
5589 if (i.index_reg == 0)
5590 i.rm.regmem = 7;
5591 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5592 i.rm.regmem = i.index_reg->reg_num - 6;
5593 break;
5594 case 5: /* (%bp) */
5595 default_seg = &ss;
5596 if (i.index_reg == 0)
5597 {
5598 i.rm.regmem = 6;
40fb9820 5599 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5600 {
5601 /* fake (%bp) into 0(%bp) */
40fb9820 5602 i.types[op].bitfield.disp8 = 1;
252b5132 5603 fake_zero_displacement = 1;
29b0f896
AM		 5604 }
5605 }
5606 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5607 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5608 break;
5609 default: /* (%si) -> 4 or (%di) -> 5 */
5610 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5611 }
5612 i.rm.mode = mode_from_disp_size (i.types[op]);
5613 }
5614 else /* i.base_reg and 32/64 bit mode */
5615 {
5616 if (flag_code == CODE_64BIT
40fb9820
L		 5617 && operand_type_check (i.types[op], disp))
5618 {
5619 i386_operand_type temp;
0dfbf9d7 5620 operand_type_set (&temp, 0);
40fb9820
L		 5621 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5622 i.types[op] = temp;
5623 if (i.prefix[ADDR_PREFIX] == 0)
5624 i.types[op].bitfield.disp32s = 1;
5625 else
5626 i.types[op].bitfield.disp32 = 1;
5627 }
20f0a1fc 5628
6c30d220
L		 5629 if (!i.tm.opcode_modifier.vecsib)
5630 i.rm.regmem = i.base_reg->reg_num;
29b0f896 5631 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5632 i.rex |= REX_B;
29b0f896
AM		 5633 i.sib.base = i.base_reg->reg_num;
5634 /* x86-64 ignores REX prefix bit here to avoid decoder
5635 complications. */
5636 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5637 {
5638 default_seg = &ss;
5639 if (i.disp_operands == 0)
5640 {
5641 fake_zero_displacement = 1;
40fb9820 5642 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5643 }
5644 }
5645 else if (i.base_reg->reg_num == ESP_REG_NUM)
5646 {
5647 default_seg = &ss;
5648 }
5649 i.sib.scale = i.log2_scale_factor;
5650 if (i.index_reg == 0)
5651 {
6c30d220 5652 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 5653 /* <disp>(%esp) becomes two byte modrm with no index
5654 register. We've already stored the code for esp
5655 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5656 Any base register besides %esp will not use the
5657 extra modrm byte. */
5658 i.sib.index = NO_INDEX_REGISTER;
29b0f896 5659 }
6c30d220 5660 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 5661 {
db51cc60
L		 5662 if (i.index_reg->reg_num == RegEiz
5663 || i.index_reg->reg_num == RegRiz)
5664 i.sib.index = NO_INDEX_REGISTER;
5665 else
5666 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5667 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5668 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5669 i.rex |= REX_X;
29b0f896 5670 }
67a4f2b7
AO		 5671
5672 if (i.disp_operands
5673 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5674 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5675 i.rm.mode = 0;
5676 else
5677 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5678 }
252b5132 5679
29b0f896
AM		 5680 if (fake_zero_displacement)
5681 {
5682 /* Fakes a zero displacement assuming that i.types[op]
5683 holds the correct displacement size. */
5684 expressionS *exp;
5685
9c2799c2 5686 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5687 exp = &disp_expressions[i.disp_operands++];
5688 i.op[op].disps = exp;
5689 exp->X_op = O_constant;
5690 exp->X_add_number = 0;
5691 exp->X_add_symbol = (symbolS *) 0;
5692 exp->X_op_symbol = (symbolS *) 0;
5693 }
c0f3af97
L		 5694
5695 mem = op;
29b0f896 5696 }
c0f3af97
L		 5697 else
5698 mem = ~0;
252b5132 5699
8c43a48b 5700 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 5701 {
5702 if (operand_type_check (i.types[0], imm))
5703 i.vex.register_specifier = NULL;
5704 else
5705 {
5706 /* VEX.vvvv encodes one of the sources when the first
5707 operand is not an immediate. */
1ef99a7b 5708 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5709 i.vex.register_specifier = i.op[0].regs;
5710 else
5711 i.vex.register_specifier = i.op[1].regs;
5712 }
5713
5714 /* Destination is a XMM register encoded in the ModRM.reg
5715 and VEX.R bit. */
5716 i.rm.reg = i.op[2].regs->reg_num;
5717 if ((i.op[2].regs->reg_flags & RegRex) != 0)
5718 i.rex |= REX_R;
5719
5720 /* ModRM.rm and VEX.B encodes the other source. */
5721 if (!i.mem_operands)
5722 {
5723 i.rm.mode = 3;
5724
1ef99a7b 5725 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5726 i.rm.regmem = i.op[1].regs->reg_num;
5727 else
5728 i.rm.regmem = i.op[0].regs->reg_num;
5729
5730 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5731 i.rex |= REX_B;
5732 }
5733 }
2426c15f 5734 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 5735 {
5736 i.vex.register_specifier = i.op[2].regs;
5737 if (!i.mem_operands)
5738 {
5739 i.rm.mode = 3;
5740 i.rm.regmem = i.op[1].regs->reg_num;
5741 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5742 i.rex |= REX_B;
5743 }
5744 }
29b0f896
AM		 5745 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5746 (if any) based on i.tm.extension_opcode. Again, we must be
5747 careful to make sure that segment/control/debug/test/MMX
5748 registers are coded into the i.rm.reg field. */
f88c9eb0 5749 else if (i.reg_operands)
29b0f896 5750 {
99018f42 5751 unsigned int op;
7ab9ffdd
L		 5752 unsigned int vex_reg = ~0;
5753
5754 for (op = 0; op < i.operands; op++)
5755 if (i.types[op].bitfield.reg8
5756 || i.types[op].bitfield.reg16
5757 || i.types[op].bitfield.reg32
5758 || i.types[op].bitfield.reg64
5759 || i.types[op].bitfield.regmmx
5760 || i.types[op].bitfield.regxmm
5761 || i.types[op].bitfield.regymm
5762 || i.types[op].bitfield.sreg2
5763 || i.types[op].bitfield.sreg3
5764 || i.types[op].bitfield.control
5765 || i.types[op].bitfield.debug
5766 || i.types[op].bitfield.test)
5767 break;
c0209578 5768
7ab9ffdd
L		 5769 if (vex_3_sources)
5770 op = dest;
2426c15f 5771 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 5772 {
5773 /* For instructions with VexNDS, the register-only
5774 source operand is encoded in VEX prefix. */
5775 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5776
7ab9ffdd 5777 if (op > mem)
c0f3af97 5778 {
7ab9ffdd
L		 5779 vex_reg = op++;
5780 gas_assert (op < i.operands);
c0f3af97
L		 5781 }
5782 else
c0f3af97 5783 {
f12dc422
L		 5784 /* Check register-only source operand when two source
5785 operands are swapped. */
5786 if (!i.tm.operand_types[op].bitfield.baseindex
5787 && i.tm.operand_types[op + 1].bitfield.baseindex)
5788 {
5789 vex_reg = op;
5790 op += 2;
5791 gas_assert (mem == (vex_reg + 1)
5792 && op < i.operands);
5793 }
5794 else
5795 {
5796 vex_reg = op + 1;
5797 gas_assert (vex_reg < i.operands);
5798 }
c0f3af97 5799 }
7ab9ffdd 5800 }
2426c15f 5801 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 5802 {
f12dc422 5803 /* For instructions with VexNDD, the register destination
7ab9ffdd 5804 is encoded in VEX prefix. */
f12dc422
L		 5805 if (i.mem_operands == 0)
5806 {
5807 /* There is no memory operand. */
5808 gas_assert ((op + 2) == i.operands);
5809 vex_reg = op + 1;
5810 }
5811 else
5812 {
5813 /* There are only 2 operands. */
5814 gas_assert (op < 2 && i.operands == 2);
5815 vex_reg = 1;
5816 }
7ab9ffdd
L		 5817 }
5818 else
5819 gas_assert (op < i.operands);
99018f42 5820
7ab9ffdd
L		 5821 if (vex_reg != (unsigned int) ~0)
5822 {
f12dc422 5823 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 5824
f12dc422
L		 5825 if (type->bitfield.reg32 != 1
5826 && type->bitfield.reg64 != 1
5827 && !operand_type_equal (type, &regxmm)
5828 && !operand_type_equal (type, &regymm))
7ab9ffdd 5829 abort ();
f88c9eb0 5830
7ab9ffdd
L		 5831 i.vex.register_specifier = i.op[vex_reg].regs;
5832 }
5833
1b9f0c97
L		 5834 /* Don't set OP operand twice. */
5835 if (vex_reg != op)
7ab9ffdd 5836 {
1b9f0c97
L		 5837 /* If there is an extension opcode to put here, the
5838 register number must be put into the regmem field. */
5839 if (i.tm.extension_opcode != None)
5840 {
5841 i.rm.regmem = i.op[op].regs->reg_num;
5842 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5843 i.rex |= REX_B;
5844 }
5845 else
5846 {
5847 i.rm.reg = i.op[op].regs->reg_num;
5848 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5849 i.rex |= REX_R;
5850 }
7ab9ffdd 5851 }
252b5132 5852
29b0f896
AM		 5853 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5854 must set it to 3 to indicate this is a register operand
5855 in the regmem field. */
5856 if (!i.mem_operands)
5857 i.rm.mode = 3;
5858 }
252b5132 5859
29b0f896 5860 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 5861 if (i.tm.extension_opcode != None)
29b0f896
AM		 5862 i.rm.reg = i.tm.extension_opcode;
5863 }
5864 return default_seg;
5865}
252b5132 5866
29b0f896 5867static void
e3bb37b5 5868output_branch (void)
29b0f896
AM		 5869{
5870 char *p;
f8a5c266 5871 int size;
29b0f896
AM		 5872 int code16;
5873 int prefix;
5874 relax_substateT subtype;
5875 symbolS *sym;
5876 offsetT off;
5877
f8a5c266
L		 5878 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
5879 size = i.disp32_encoding ? BIG : SMALL;
29b0f896
AM		 5880
5881 prefix = 0;
5882 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5883 {
29b0f896
AM		 5884 prefix = 1;
5885 i.prefixes -= 1;
5886 code16 ^= CODE16;
252b5132 5887 }
29b0f896
AM		 5888 /* Pentium4 branch hints. */
5889 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5890 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5891 {
29b0f896
AM		 5892 prefix++;
5893 i.prefixes--;
5894 }
5895 if (i.prefix[REX_PREFIX] != 0)
5896 {
5897 prefix++;
5898 i.prefixes--;
2f66722d
AM		 5899 }
5900
29b0f896
AM		 5901 if (i.prefixes != 0 && !intel_syntax)
5902 as_warn (_("skipping prefixes on this instruction"));
5903
5904 /* It's always a symbol; End frag & setup for relax.
5905 Make sure there is enough room in this frag for the largest
5906 instruction we may generate in md_convert_frag. This is 2
5907 bytes for the opcode and room for the prefix and largest
5908 displacement. */
5909 frag_grow (prefix + 2 + 4);
5910 /* Prefix and 1 opcode byte go in fr_fix. */
5911 p = frag_more (prefix + 1);
5912 if (i.prefix[DATA_PREFIX] != 0)
5913 *p++ = DATA_PREFIX_OPCODE;
5914 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5915 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5916 *p++ = i.prefix[SEG_PREFIX];
5917 if (i.prefix[REX_PREFIX] != 0)
5918 *p++ = i.prefix[REX_PREFIX];
5919 *p = i.tm.base_opcode;
5920
5921 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 5922 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 5923 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 5924 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 5925 else
f8a5c266 5926 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 5927 subtype |= code16;
3e73aa7c 5928
29b0f896
AM		 5929 sym = i.op[0].disps->X_add_symbol;
5930 off = i.op[0].disps->X_add_number;
3e73aa7c 5931
29b0f896
AM		 5932 if (i.op[0].disps->X_op != O_constant
5933 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5934 {
29b0f896
AM		 5935 /* Handle complex expressions. */
5936 sym = make_expr_symbol (i.op[0].disps);
5937 off = 0;
5938 }
3e73aa7c 5939
29b0f896
AM		 5940 /* 1 possible extra opcode + 4 byte displacement go in var part.
5941 Pass reloc in fr_var. */
5942 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5943}
3e73aa7c 5944
29b0f896 5945static void
e3bb37b5 5946output_jump (void)
29b0f896
AM		 5947{
5948 char *p;
5949 int size;
3e02c1cc 5950 fixS *fixP;
29b0f896 5951
40fb9820 5952 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5953 {
5954 /* This is a loop or jecxz type instruction. */
5955 size = 1;
5956 if (i.prefix[ADDR_PREFIX] != 0)
5957 {
5958 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5959 i.prefixes -= 1;
5960 }
5961 /* Pentium4 branch hints. */
5962 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5963 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5964 {
5965 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5966 i.prefixes--;
3e73aa7c
JH		 5967 }
5968 }
29b0f896
AM		 5969 else
5970 {
5971 int code16;
3e73aa7c 5972
29b0f896
AM		 5973 code16 = 0;
5974 if (flag_code == CODE_16BIT)
5975 code16 = CODE16;
3e73aa7c 5976
29b0f896
AM		 5977 if (i.prefix[DATA_PREFIX] != 0)
5978 {
5979 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5980 i.prefixes -= 1;
5981 code16 ^= CODE16;
5982 }
252b5132 5983
29b0f896
AM		 5984 size = 4;
5985 if (code16)
5986 size = 2;
5987 }
9fcc94b6 5988
29b0f896
AM		 5989 if (i.prefix[REX_PREFIX] != 0)
5990 {
5991 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5992 i.prefixes -= 1;
5993 }
252b5132 5994
29b0f896
AM		 5995 if (i.prefixes != 0 && !intel_syntax)
5996 as_warn (_("skipping prefixes on this instruction"));
e0890092 5997
29b0f896
AM		 5998 p = frag_more (1 + size);
5999 *p++ = i.tm.base_opcode;
e0890092 6000
3e02c1cc
AM		 6001 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6002 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
6003
6004 /* All jumps handled here are signed, but don't use a signed limit
6005 check for 32 and 16 bit jumps as we want to allow wrap around at
6006 4G and 64k respectively. */
6007 if (size == 1)
6008 fixP->fx_signed = 1;
29b0f896 6009}
e0890092 6010
29b0f896 6011static void
e3bb37b5 6012output_interseg_jump (void)
29b0f896
AM		 6013{
6014 char *p;
6015 int size;
6016 int prefix;
6017 int code16;
252b5132 6018
29b0f896
AM		 6019 code16 = 0;
6020 if (flag_code == CODE_16BIT)
6021 code16 = CODE16;
a217f122 6022
29b0f896
AM		 6023 prefix = 0;
6024 if (i.prefix[DATA_PREFIX] != 0)
6025 {
6026 prefix = 1;
6027 i.prefixes -= 1;
6028 code16 ^= CODE16;
6029 }
6030 if (i.prefix[REX_PREFIX] != 0)
6031 {
6032 prefix++;
6033 i.prefixes -= 1;
6034 }
252b5132 6035
29b0f896
AM		 6036 size = 4;
6037 if (code16)
6038 size = 2;
252b5132 6039
29b0f896
AM		 6040 if (i.prefixes != 0 && !intel_syntax)
6041 as_warn (_("skipping prefixes on this instruction"));
252b5132 6042
29b0f896
AM		 6043 /* 1 opcode; 2 segment; offset */
6044 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6045
29b0f896
AM		 6046 if (i.prefix[DATA_PREFIX] != 0)
6047 *p++ = DATA_PREFIX_OPCODE;
252b5132 6048
29b0f896
AM		 6049 if (i.prefix[REX_PREFIX] != 0)
6050 *p++ = i.prefix[REX_PREFIX];
252b5132 6051
29b0f896
AM		 6052 *p++ = i.tm.base_opcode;
6053 if (i.op[1].imms->X_op == O_constant)
6054 {
6055 offsetT n = i.op[1].imms->X_add_number;
252b5132 6056
29b0f896
AM		 6057 if (size == 2
6058 && !fits_in_unsigned_word (n)
6059 && !fits_in_signed_word (n))
6060 {
6061 as_bad (_("16-bit jump out of range"));
6062 return;
6063 }
6064 md_number_to_chars (p, n, size);
6065 }
6066 else
6067 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6068 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
6069 if (i.op[0].imms->X_op != O_constant)
6070 as_bad (_("can't handle non absolute segment in `%s'"),
6071 i.tm.name);
6072 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6073}
a217f122 6074
29b0f896 6075static void
e3bb37b5 6076output_insn (void)
29b0f896 6077{
2bbd9c25
JJ		 6078 fragS *insn_start_frag;
6079 offsetT insn_start_off;
6080
29b0f896
AM		 6081 /* Tie dwarf2 debug info to the address at the start of the insn.
6082 We can't do this after the insn has been output as the current
6083 frag may have been closed off. eg. by frag_var. */
6084 dwarf2_emit_insn (0);
6085
2bbd9c25
JJ		 6086 insn_start_frag = frag_now;
6087 insn_start_off = frag_now_fix ();
6088
29b0f896 6089 /* Output jumps. */
40fb9820 6090 if (i.tm.opcode_modifier.jump)
29b0f896 6091 output_branch ();
40fb9820
L		 6092 else if (i.tm.opcode_modifier.jumpbyte
6093 || i.tm.opcode_modifier.jumpdword)
29b0f896 6094 output_jump ();
40fb9820 6095 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6096 output_interseg_jump ();
6097 else
6098 {
6099 /* Output normal instructions here. */
6100 char *p;
6101 unsigned char *q;
47465058 6102 unsigned int j;
331d2d0d 6103 unsigned int prefix;
4dffcebc 6104
c0f3af97
L		 6105 /* Since the VEX prefix contains the implicit prefix, we don't
6106 need the explicit prefix. */
6107 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 6108 {
c0f3af97 6109 switch (i.tm.opcode_length)
bc4bd9ab 6110 {
c0f3af97
L		 6111 case 3:
6112 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6113 {
c0f3af97
L		 6114 prefix = (i.tm.base_opcode >> 24) & 0xff;
6115 goto check_prefix;
6116 }
6117 break;
6118 case 2:
6119 if ((i.tm.base_opcode & 0xff0000) != 0)
6120 {
6121 prefix = (i.tm.base_opcode >> 16) & 0xff;
6122 if (i.tm.cpu_flags.bitfield.cpupadlock)
6123 {
4dffcebc 6124check_prefix:
c0f3af97 6125 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6126 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6127 != REPE_PREFIX_OPCODE))
6128 add_prefix (prefix);
6129 }
6130 else
4dffcebc
L		 6131 add_prefix (prefix);
6132 }
c0f3af97
L		 6133 break;
6134 case 1:
6135 break;
6136 default:
6137 abort ();
bc4bd9ab 6138 }
c0f3af97
L		 6139
6140 /* The prefix bytes. */
6141 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
6142 if (*q)
6143 FRAG_APPEND_1_CHAR (*q);
0f10071e 6144 }
252b5132 6145
c0f3af97
L		 6146 if (i.tm.opcode_modifier.vex)
6147 {
6148 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
6149 if (*q)
6150 switch (j)
6151 {
6152 case REX_PREFIX:
6153 /* REX byte is encoded in VEX prefix. */
6154 break;
6155 case SEG_PREFIX:
6156 case ADDR_PREFIX:
6157 FRAG_APPEND_1_CHAR (*q);
6158 break;
6159 default:
6160 /* There should be no other prefixes for instructions
6161 with VEX prefix. */
6162 abort ();
6163 }
6164
6165 /* Now the VEX prefix. */
6166 p = frag_more (i.vex.length);
6167 for (j = 0; j < i.vex.length; j++)
6168 p[j] = i.vex.bytes[j];
6169 }
252b5132 6170
29b0f896 6171 /* Now the opcode; be careful about word order here! */
4dffcebc 6172 if (i.tm.opcode_length == 1)
29b0f896
AM		 6173 {
6174 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
6175 }
6176 else
6177 {
4dffcebc 6178 switch (i.tm.opcode_length)
331d2d0d 6179 {
4dffcebc 6180 case 3:
331d2d0d
L		 6181 p = frag_more (3);
6182 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 6183 break;
6184 case 2:
6185 p = frag_more (2);
6186 break;
6187 default:
6188 abort ();
6189 break;
331d2d0d 6190 }
0f10071e 6191
29b0f896
AM		 6192 /* Put out high byte first: can't use md_number_to_chars! */
6193 *p++ = (i.tm.base_opcode >> 8) & 0xff;
6194 *p = i.tm.base_opcode & 0xff;
6195 }
3e73aa7c 6196
29b0f896 6197 /* Now the modrm byte and sib byte (if present). */
40fb9820 6198 if (i.tm.opcode_modifier.modrm)
29b0f896 6199 {
4a3523fa
L		 6200 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
6201 | i.rm.reg << 3
6202 | i.rm.mode << 6));
29b0f896
AM		 6203 /* If i.rm.regmem == ESP (4)
6204 && i.rm.mode != (Register mode)
6205 && not 16 bit
6206 ==> need second modrm byte. */
6207 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
6208 && i.rm.mode != 3
40fb9820 6209 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 6210 FRAG_APPEND_1_CHAR ((i.sib.base << 0
6211 | i.sib.index << 3
6212 | i.sib.scale << 6));
29b0f896 6213 }
3e73aa7c 6214
29b0f896 6215 if (i.disp_operands)
2bbd9c25 6216 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 6217
29b0f896 6218 if (i.imm_operands)
2bbd9c25 6219 output_imm (insn_start_frag, insn_start_off);
29b0f896 6220 }
252b5132 6221
29b0f896
AM		 6222#ifdef DEBUG386
6223 if (flag_debug)
6224 {
7b81dfbb 6225 pi ("" /*line*/, &i);
29b0f896
AM		 6226 }
6227#endif /* DEBUG386 */
6228}
252b5132 6229
e205caa7
L		 6230/* Return the size of the displacement operand N. */
6231
6232static int
6233disp_size (unsigned int n)
6234{
6235 int size = 4;
40fb9820
L		 6236 if (i.types[n].bitfield.disp64)
6237 size = 8;
6238 else if (i.types[n].bitfield.disp8)
6239 size = 1;
6240 else if (i.types[n].bitfield.disp16)
6241 size = 2;
e205caa7
L		 6242 return size;
6243}
6244
6245/* Return the size of the immediate operand N. */
6246
6247static int
6248imm_size (unsigned int n)
6249{
6250 int size = 4;
40fb9820
L		 6251 if (i.types[n].bitfield.imm64)
6252 size = 8;
6253 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
6254 size = 1;
6255 else if (i.types[n].bitfield.imm16)
6256 size = 2;
e205caa7
L		 6257 return size;
6258}
6259
29b0f896 6260static void
64e74474 6261output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6262{
6263 char *p;
6264 unsigned int n;
252b5132 6265
29b0f896
AM		 6266 for (n = 0; n < i.operands; n++)
6267 {
40fb9820 6268 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 6269 {
6270 if (i.op[n].disps->X_op == O_constant)
6271 {
e205caa7 6272 int size = disp_size (n);
29b0f896 6273 offsetT val;
252b5132 6274
29b0f896
AM		 6275 val = offset_in_range (i.op[n].disps->X_add_number,
6276 size);
6277 p = frag_more (size);
6278 md_number_to_chars (p, val, size);
6279 }
6280 else
6281 {
f86103b7 6282 enum bfd_reloc_code_real reloc_type;
e205caa7 6283 int size = disp_size (n);
40fb9820 6284 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 6285 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6286
e205caa7 6287 /* We can't have 8 bit displacement here. */
9c2799c2 6288 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 6289
29b0f896
AM		 6290 /* The PC relative address is computed relative
6291 to the instruction boundary, so in case immediate
6292 fields follows, we need to adjust the value. */
6293 if (pcrel && i.imm_operands)
6294 {
29b0f896 6295 unsigned int n1;
e205caa7 6296 int sz = 0;
252b5132 6297
29b0f896 6298 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 6299 if (operand_type_check (i.types[n1], imm))
252b5132 6300 {
e205caa7
L		 6301 /* Only one immediate is allowed for PC
6302 relative address. */
9c2799c2 6303 gas_assert (sz == 0);
e205caa7
L		 6304 sz = imm_size (n1);
6305 i.op[n].disps->X_add_number -= sz;
252b5132 6306 }
29b0f896 6307 /* We should find the immediate. */
9c2799c2 6308 gas_assert (sz != 0);
29b0f896 6309 }
520dc8e8 6310
29b0f896 6311 p = frag_more (size);
2bbd9c25 6312 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 6313 if (GOT_symbol
2bbd9c25 6314 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 6315 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6316 || reloc_type == BFD_RELOC_X86_64_32S
6317 || (reloc_type == BFD_RELOC_64
6318 && object_64bit))
d6ab8113
JB		 6319 && (i.op[n].disps->X_op == O_symbol
6320 || (i.op[n].disps->X_op == O_add
6321 && ((symbol_get_value_expression
6322 (i.op[n].disps->X_op_symbol)->X_op)
6323 == O_subtract))))
6324 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 6325 {
6326 offsetT add;
6327
6328 if (insn_start_frag == frag_now)
6329 add = (p - frag_now->fr_literal) - insn_start_off;
6330 else
6331 {
6332 fragS *fr;
6333
6334 add = insn_start_frag->fr_fix - insn_start_off;
6335 for (fr = insn_start_frag->fr_next;
6336 fr && fr != frag_now; fr = fr->fr_next)
6337 add += fr->fr_fix;
6338 add += p - frag_now->fr_literal;
6339 }
6340
4fa24527 6341 if (!object_64bit)
7b81dfbb
AJ		 6342 {
6343 reloc_type = BFD_RELOC_386_GOTPC;
6344 i.op[n].imms->X_add_number += add;
6345 }
6346 else if (reloc_type == BFD_RELOC_64)
6347 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 6348 else
7b81dfbb
AJ		 6349 /* Don't do the adjustment for x86-64, as there
6350 the pcrel addressing is relative to the _next_
6351 insn, and that is taken care of in other code. */
d6ab8113 6352 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 6353 }
062cd5e7 6354 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 6355 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 6356 }
6357 }
6358 }
6359}
252b5132 6360
29b0f896 6361static void
64e74474 6362output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6363{
6364 char *p;
6365 unsigned int n;
252b5132 6366
29b0f896
AM		 6367 for (n = 0; n < i.operands; n++)
6368 {
40fb9820 6369 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 6370 {
6371 if (i.op[n].imms->X_op == O_constant)
6372 {
e205caa7 6373 int size = imm_size (n);
29b0f896 6374 offsetT val;
b4cac588 6375
29b0f896
AM		 6376 val = offset_in_range (i.op[n].imms->X_add_number,
6377 size);
6378 p = frag_more (size);
6379 md_number_to_chars (p, val, size);
6380 }
6381 else
6382 {
6383 /* Not absolute_section.
6384 Need a 32-bit fixup (don't support 8bit
6385 non-absolute imms). Try to support other
6386 sizes ... */
f86103b7 6387 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 6388 int size = imm_size (n);
6389 int sign;
29b0f896 6390
40fb9820 6391 if (i.types[n].bitfield.imm32s
a7d61044 6392 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6393 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6394 sign = 1;
e205caa7
L		 6395 else
6396 sign = 0;
520dc8e8 6397
29b0f896
AM		 6398 p = frag_more (size);
6399 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6400
2bbd9c25
JJ		 6401 /* This is tough to explain. We end up with this one if we
6402 * have operands that look like
6403 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6404 * obtain the absolute address of the GOT, and it is strongly
6405 * preferable from a performance point of view to avoid using
6406 * a runtime relocation for this. The actual sequence of
6407 * instructions often look something like:
6408 *
6409 * call .L66
6410 * .L66:
6411 * popl %ebx
6412 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6413 *
6414 * The call and pop essentially return the absolute address
6415 * of the label .L66 and store it in %ebx. The linker itself
6416 * will ultimately change the first operand of the addl so
6417 * that %ebx points to the GOT, but to keep things simple, the
6418 * .o file must have this operand set so that it generates not
6419 * the absolute address of .L66, but the absolute address of
6420 * itself. This allows the linker itself simply treat a GOTPC
6421 * relocation as asking for a pcrel offset to the GOT to be
6422 * added in, and the addend of the relocation is stored in the
6423 * operand field for the instruction itself.
6424 *
6425 * Our job here is to fix the operand so that it would add
6426 * the correct offset so that %ebx would point to itself. The
6427 * thing that is tricky is that .-.L66 will point to the
6428 * beginning of the instruction, so we need to further modify
6429 * the operand so that it will point to itself. There are
6430 * other cases where you have something like:
6431 *
6432 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6433 *
6434 * and here no correction would be required. Internally in
6435 * the assembler we treat operands of this form as not being
6436 * pcrel since the '.' is explicitly mentioned, and I wonder
6437 * whether it would simplify matters to do it this way. Who
6438 * knows. In earlier versions of the PIC patches, the
6439 * pcrel_adjust field was used to store the correction, but
6440 * since the expression is not pcrel, I felt it would be
6441 * confusing to do it this way. */
6442
d6ab8113 6443 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6444 || reloc_type == BFD_RELOC_X86_64_32S
6445 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6446 && GOT_symbol
6447 && GOT_symbol == i.op[n].imms->X_add_symbol
6448 && (i.op[n].imms->X_op == O_symbol
6449 || (i.op[n].imms->X_op == O_add
6450 && ((symbol_get_value_expression
6451 (i.op[n].imms->X_op_symbol)->X_op)
6452 == O_subtract))))
6453 {
2bbd9c25
JJ		 6454 offsetT add;
6455
6456 if (insn_start_frag == frag_now)
6457 add = (p - frag_now->fr_literal) - insn_start_off;
6458 else
6459 {
6460 fragS *fr;
6461
6462 add = insn_start_frag->fr_fix - insn_start_off;
6463 for (fr = insn_start_frag->fr_next;
6464 fr && fr != frag_now; fr = fr->fr_next)
6465 add += fr->fr_fix;
6466 add += p - frag_now->fr_literal;
6467 }
6468
4fa24527 6469 if (!object_64bit)
d6ab8113 6470 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6471 else if (size == 4)
d6ab8113 6472 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6473 else if (size == 8)
6474 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6475 i.op[n].imms->X_add_number += add;
29b0f896 6476 }
29b0f896
AM		 6477 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6478 i.op[n].imms, 0, reloc_type);
6479 }
6480 }
6481 }
252b5132
RH		 6482}
6483\f
d182319b
JB		 6484/* x86_cons_fix_new is called via the expression parsing code when a
6485 reloc is needed. We use this hook to get the correct .got reloc. */
6486static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6487static int cons_sign = -1;
6488
6489void
e3bb37b5 6490x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6491 expressionS *exp)
d182319b
JB		 6492{
6493 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6494
6495 got_reloc = NO_RELOC;
6496
6497#ifdef TE_PE
6498 if (exp->X_op == O_secrel)
6499 {
6500 exp->X_op = O_symbol;
6501 r = BFD_RELOC_32_SECREL;
6502 }
6503#endif
6504
6505 fix_new_exp (frag, off, len, exp, 0, r);
6506}
6507
718ddfc0
JB		 6508#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6509# define lex_got(reloc, adjust, types) NULL
6510#else
f3c180ae
AM		 6511/* Parse operands of the form
6512 <symbol>@GOTOFF+<nnn>
6513 and similar .plt or .got references.
6514
6515 If we find one, set up the correct relocation in RELOC and copy the
6516 input string, minus the `@GOTOFF' into a malloc'd buffer for
6517 parsing by the calling routine. Return this buffer, and if ADJUST
6518 is non-null set it to the length of the string we removed from the
6519 input line. Otherwise return NULL. */
6520static char *
91d6fa6a 6521lex_got (enum bfd_reloc_code_real *rel,
64e74474 6522 int *adjust,
40fb9820 6523 i386_operand_type *types)
f3c180ae 6524{
7b81dfbb
AJ		 6525 /* Some of the relocations depend on the size of what field is to
6526 be relocated. But in our callers i386_immediate and i386_displacement
6527 we don't yet know the operand size (this will be set by insn
6528 matching). Hence we record the word32 relocation here,
6529 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6530 static const struct {
6531 const char *str;
cff8d58a 6532 int len;
4fa24527 6533 const enum bfd_reloc_code_real rel[2];
40fb9820 6534 const i386_operand_type types64;
f3c180ae 6535 } gotrel[] = {
cff8d58a
L		 6536 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
6537 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6538 OPERAND_TYPE_IMM64 },
cff8d58a
L		 6539 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
6540 BFD_RELOC_X86_64_PLT32 },
40fb9820 6541 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6542 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
6543 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6544 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6545 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
6546 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6547 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6548 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
6549 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6550 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6551 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
6552 BFD_RELOC_X86_64_TLSGD },
40fb9820 6553 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6554 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
6555 _dummy_first_bfd_reloc_code_real },
40fb9820 6556 OPERAND_TYPE_NONE },
cff8d58a
L		 6557 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
6558 BFD_RELOC_X86_64_TLSLD },
40fb9820 6559 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6560 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
6561 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6562 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6563 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
6564 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6565 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6566 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
6567 _dummy_first_bfd_reloc_code_real },
40fb9820 6568 OPERAND_TYPE_NONE },
cff8d58a
L		 6569 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
6570 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 6571 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6572 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
6573 _dummy_first_bfd_reloc_code_real },
40fb9820 6574 OPERAND_TYPE_NONE },
cff8d58a
L		 6575 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
6576 _dummy_first_bfd_reloc_code_real },
40fb9820 6577 OPERAND_TYPE_NONE },
cff8d58a
L		 6578 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
6579 BFD_RELOC_X86_64_GOT32 },
40fb9820 6580 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 6581 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
6582 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6583 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6584 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
6585 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6586 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6587 };
6588 char *cp;
6589 unsigned int j;
6590
718ddfc0
JB		 6591 if (!IS_ELF)
6592 return NULL;
6593
f3c180ae 6594 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6595 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6596 return NULL;
6597
47465058 6598 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 6599 {
cff8d58a 6600 int len = gotrel[j].len;
28f81592 6601 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6602 {
4fa24527 6603 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6604 {
28f81592
AM		 6605 int first, second;
6606 char *tmpbuf, *past_reloc;
f3c180ae 6607
91d6fa6a 6608 *rel = gotrel[j].rel[object_64bit];
28f81592
AM		 6609 if (adjust)
6610 *adjust = len;
f3c180ae 6611
3956db08
JB		 6612 if (types)
6613 {
6614 if (flag_code != CODE_64BIT)
40fb9820
L		 6615 {
6616 types->bitfield.imm32 = 1;
6617 types->bitfield.disp32 = 1;
6618 }
3956db08
JB		 6619 else
6620 *types = gotrel[j].types64;
6621 }
6622
f3c180ae
AM		 6623 if (GOT_symbol == NULL)
6624 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6625
28f81592 6626 /* The length of the first part of our input line. */
f3c180ae 6627 first = cp - input_line_pointer;
28f81592
AM		 6628
6629 /* The second part goes from after the reloc token until
67c11a9b 6630 (and including) an end_of_line char or comma. */
28f81592 6631 past_reloc = cp + 1 + len;
67c11a9b
AM		 6632 cp = past_reloc;
6633 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6634 ++cp;
6635 second = cp + 1 - past_reloc;
28f81592
AM		 6636
6637 /* Allocate and copy string. The trailing NUL shouldn't
6638 be necessary, but be safe. */
1e9cc1c2 6639 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 6640 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6641 if (second != 0 && *past_reloc != ' ')
6642 /* Replace the relocation token with ' ', so that
6643 errors like foo@GOTOFF1 will be detected. */
6644 tmpbuf[first++] = ' ';
6645 memcpy (tmpbuf + first, past_reloc, second);
6646 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6647 return tmpbuf;
6648 }
6649
4fa24527
JB		 6650 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6651 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6652 return NULL;
6653 }
6654 }
6655
6656 /* Might be a symbol version string. Don't as_bad here. */
6657 return NULL;
6658}
4e4f7c87 6659#endif
f3c180ae 6660
f3c180ae 6661void
e3bb37b5 6662x86_cons (expressionS *exp, int size)
f3c180ae 6663{
ee86248c
JB		 6664 intel_syntax = -intel_syntax;
6665
3c7b9c2c 6666 exp->X_md = 0;
4fa24527 6667 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6668 {
6669 /* Handle @GOTOFF and the like in an expression. */
6670 char *save;
6671 char *gotfree_input_line;
4a57f2cf 6672 int adjust = 0;
f3c180ae
AM		 6673
6674 save = input_line_pointer;
3956db08 6675 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6676 if (gotfree_input_line)
6677 input_line_pointer = gotfree_input_line;
6678
6679 expression (exp);
6680
6681 if (gotfree_input_line)
6682 {
6683 /* expression () has merrily parsed up to the end of line,
6684 or a comma - in the wrong buffer. Transfer how far
6685 input_line_pointer has moved to the right buffer. */
6686 input_line_pointer = (save
6687 + (input_line_pointer - gotfree_input_line)
6688 + adjust);
6689 free (gotfree_input_line);
3992d3b7
AM		 6690 if (exp->X_op == O_constant
6691 || exp->X_op == O_absent
6692 || exp->X_op == O_illegal
0398aac5 6693 || exp->X_op == O_register
3992d3b7
AM		 6694 || exp->X_op == O_big)
6695 {
6696 char c = *input_line_pointer;
6697 *input_line_pointer = 0;
6698 as_bad (_("missing or invalid expression `%s'"), save);
6699 *input_line_pointer = c;
6700 }
f3c180ae
AM		 6701 }
6702 }
6703 else
6704 expression (exp);
ee86248c
JB		 6705
6706 intel_syntax = -intel_syntax;
6707
6708 if (intel_syntax)
6709 i386_intel_simplify (exp);
f3c180ae 6710}
f3c180ae 6711
9f32dd5b
L		 6712static void
6713signed_cons (int size)
6482c264 6714{
d182319b
JB		 6715 if (flag_code == CODE_64BIT)
6716 cons_sign = 1;
6717 cons (size);
6718 cons_sign = -1;
6482c264
NC		 6719}
6720
d182319b 6721#ifdef TE_PE
6482c264 6722static void
7016a5d5 6723pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 6724{
6725 expressionS exp;
6726
6727 do
6728 {
6729 expression (&exp);
6730 if (exp.X_op == O_symbol)
6731 exp.X_op = O_secrel;
6732
6733 emit_expr (&exp, 4);
6734 }
6735 while (*input_line_pointer++ == ',');
6736
6737 input_line_pointer--;
6738 demand_empty_rest_of_line ();
6739}
6482c264
NC		 6740#endif
6741
252b5132 6742static int
70e41ade 6743i386_immediate (char *imm_start)
252b5132
RH		 6744{
6745 char *save_input_line_pointer;
f3c180ae 6746 char *gotfree_input_line;
252b5132 6747 segT exp_seg = 0;
47926f60 6748 expressionS *exp;
40fb9820
L		 6749 i386_operand_type types;
6750
0dfbf9d7 6751 operand_type_set (&types, ~0);
252b5132
RH		 6752
6753 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6754 {
31b2323c
L		 6755 as_bad (_("at most %d immediate operands are allowed"),
6756 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6757 return 0;
6758 }
6759
6760 exp = &im_expressions[i.imm_operands++];
520dc8e8 6761 i.op[this_operand].imms = exp;
252b5132
RH		 6762
6763 if (is_space_char (*imm_start))
6764 ++imm_start;
6765
6766 save_input_line_pointer = input_line_pointer;
6767 input_line_pointer = imm_start;
6768
3956db08 6769 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6770 if (gotfree_input_line)
6771 input_line_pointer = gotfree_input_line;
252b5132
RH		 6772
6773 exp_seg = expression (exp);
6774
83183c0c 6775 SKIP_WHITESPACE ();
252b5132 6776 if (*input_line_pointer)
f3c180ae 6777 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6778
6779 input_line_pointer = save_input_line_pointer;
f3c180ae 6780 if (gotfree_input_line)
ee86248c
JB		 6781 {
6782 free (gotfree_input_line);
6783
6784 if (exp->X_op == O_constant || exp->X_op == O_register)
6785 exp->X_op = O_illegal;
6786 }
6787
6788 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6789}
252b5132 6790
ee86248c
JB		 6791static int
6792i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6793 i386_operand_type types, const char *imm_start)
6794{
6795 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 6796 {
313c53d1
L		 6797 if (imm_start)
6798 as_bad (_("missing or invalid immediate expression `%s'"),
6799 imm_start);
3992d3b7 6800 return 0;
252b5132 6801 }
3e73aa7c 6802 else if (exp->X_op == O_constant)
252b5132 6803 {
47926f60 6804 /* Size it properly later. */
40fb9820 6805 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 6806 /* If not 64bit, sign extend val. */
6807 if (flag_code != CODE_64BIT
4eed87de
AM		 6808 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6809 exp->X_add_number
6810 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6811 }
4c63da97 6812#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6813 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6814 && exp_seg != absolute_section
47926f60 6815 && exp_seg != text_section
24eab124
AM		 6816 && exp_seg != data_section
6817 && exp_seg != bss_section
6818 && exp_seg != undefined_section
f86103b7 6819 && !bfd_is_com_section (exp_seg))
252b5132 6820 {
d0b47220 6821 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6822 return 0;
6823 }
6824#endif
bb8f5920
L		 6825 else if (!intel_syntax && exp->X_op == O_register)
6826 {
313c53d1
L		 6827 if (imm_start)
6828 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 6829 return 0;
6830 }
252b5132
RH		 6831 else
6832 {
6833 /* This is an address. The size of the address will be
24eab124 6834 determined later, depending on destination register,
3e73aa7c 6835 suffix, or the default for the section. */
40fb9820
L		 6836 i.types[this_operand].bitfield.imm8 = 1;
6837 i.types[this_operand].bitfield.imm16 = 1;
6838 i.types[this_operand].bitfield.imm32 = 1;
6839 i.types[this_operand].bitfield.imm32s = 1;
6840 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6841 i.types[this_operand] = operand_type_and (i.types[this_operand],
6842 types);
252b5132
RH		 6843 }
6844
6845 return 1;
6846}
6847
551c1ca1 6848static char *
e3bb37b5 6849i386_scale (char *scale)
252b5132 6850{
551c1ca1
AM		 6851 offsetT val;
6852 char *save = input_line_pointer;
252b5132 6853
551c1ca1
AM		 6854 input_line_pointer = scale;
6855 val = get_absolute_expression ();
6856
6857 switch (val)
252b5132 6858 {
551c1ca1 6859 case 1:
252b5132
RH		 6860 i.log2_scale_factor = 0;
6861 break;
551c1ca1 6862 case 2:
252b5132
RH		 6863 i.log2_scale_factor = 1;
6864 break;
551c1ca1 6865 case 4:
252b5132
RH		 6866 i.log2_scale_factor = 2;
6867 break;
551c1ca1 6868 case 8:
252b5132
RH		 6869 i.log2_scale_factor = 3;
6870 break;
6871 default:
a724f0f4
JB		 6872 {
6873 char sep = *input_line_pointer;
6874
6875 *input_line_pointer = '\0';
6876 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6877 scale);
6878 *input_line_pointer = sep;
6879 input_line_pointer = save;
6880 return NULL;
6881 }
252b5132 6882 }
29b0f896 6883 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6884 {
6885 as_warn (_("scale factor of %d without an index register"),
24eab124 6886 1 << i.log2_scale_factor);
252b5132 6887 i.log2_scale_factor = 0;
252b5132 6888 }
551c1ca1
AM		 6889 scale = input_line_pointer;
6890 input_line_pointer = save;
6891 return scale;
252b5132
RH		 6892}
6893
252b5132 6894static int
e3bb37b5 6895i386_displacement (char *disp_start, char *disp_end)
252b5132 6896{
29b0f896 6897 expressionS *exp;
252b5132
RH		 6898 segT exp_seg = 0;
6899 char *save_input_line_pointer;
f3c180ae 6900 char *gotfree_input_line;
40fb9820
L		 6901 int override;
6902 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6903 int ret;
252b5132 6904
31b2323c
L		 6905 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6906 {
6907 as_bad (_("at most %d displacement operands are allowed"),
6908 MAX_MEMORY_OPERANDS);
6909 return 0;
6910 }
6911
0dfbf9d7 6912 operand_type_set (&bigdisp, 0);
40fb9820
L		 6913 if ((i.types[this_operand].bitfield.jumpabsolute)
6914 || (!current_templates->start->opcode_modifier.jump
6915 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6916 {
40fb9820 6917 bigdisp.bitfield.disp32 = 1;
e05278af 6918 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6919 if (flag_code == CODE_64BIT)
6920 {
6921 if (!override)
6922 {
6923 bigdisp.bitfield.disp32s = 1;
6924 bigdisp.bitfield.disp64 = 1;
6925 }
6926 }
6927 else if ((flag_code == CODE_16BIT) ^ override)
6928 {
6929 bigdisp.bitfield.disp32 = 0;
6930 bigdisp.bitfield.disp16 = 1;
6931 }
e05278af
JB		 6932 }
6933 else
6934 {
6935 /* For PC-relative branches, the width of the displacement
6936 is dependent upon data size, not address size. */
e05278af 6937 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6938 if (flag_code == CODE_64BIT)
6939 {
6940 if (override || i.suffix == WORD_MNEM_SUFFIX)
6941 bigdisp.bitfield.disp16 = 1;
6942 else
6943 {
6944 bigdisp.bitfield.disp32 = 1;
6945 bigdisp.bitfield.disp32s = 1;
6946 }
6947 }
6948 else
e05278af
JB		 6949 {
6950 if (!override)
6951 override = (i.suffix == (flag_code != CODE_16BIT
6952 ? WORD_MNEM_SUFFIX
6953 : LONG_MNEM_SUFFIX));
40fb9820
L		 6954 bigdisp.bitfield.disp32 = 1;
6955 if ((flag_code == CODE_16BIT) ^ override)
6956 {
6957 bigdisp.bitfield.disp32 = 0;
6958 bigdisp.bitfield.disp16 = 1;
6959 }
e05278af 6960 }
e05278af 6961 }
c6fb90c8
L		 6962 i.types[this_operand] = operand_type_or (i.types[this_operand],
6963 bigdisp);
252b5132
RH		 6964
6965 exp = &disp_expressions[i.disp_operands];
520dc8e8 6966 i.op[this_operand].disps = exp;
252b5132
RH		 6967 i.disp_operands++;
6968 save_input_line_pointer = input_line_pointer;
6969 input_line_pointer = disp_start;
6970 END_STRING_AND_SAVE (disp_end);
6971
6972#ifndef GCC_ASM_O_HACK
6973#define GCC_ASM_O_HACK 0
6974#endif
6975#if GCC_ASM_O_HACK
6976 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6977 if (i.types[this_operand].bitfield.baseIndex
24eab124 6978 && displacement_string_end[-1] == '+')
252b5132
RH		 6979 {
6980 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6981 constraint within gcc asm statements.
6982 For instance:
6983
6984 #define _set_tssldt_desc(n,addr,limit,type) \
6985 __asm__ __volatile__ ( \
6986 "movw %w2,%0\n\t" \
6987 "movw %w1,2+%0\n\t" \
6988 "rorl $16,%1\n\t" \
6989 "movb %b1,4+%0\n\t" \
6990 "movb %4,5+%0\n\t" \
6991 "movb $0,6+%0\n\t" \
6992 "movb %h1,7+%0\n\t" \
6993 "rorl $16,%1" \
6994 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6995
6996 This works great except that the output assembler ends
6997 up looking a bit weird if it turns out that there is
6998 no offset. You end up producing code that looks like:
6999
7000 #APP
7001 movw $235,(%eax)
7002 movw %dx,2+(%eax)
7003 rorl $16,%edx
7004 movb %dl,4+(%eax)
7005 movb $137,5+(%eax)
7006 movb $0,6+(%eax)
7007 movb %dh,7+(%eax)
7008 rorl $16,%edx
7009 #NO_APP
7010
47926f60 7011 So here we provide the missing zero. */
24eab124
AM		 7012
7013 *displacement_string_end = '0';
252b5132
RH		 7014 }
7015#endif
3956db08 7016 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 7017 if (gotfree_input_line)
7018 input_line_pointer = gotfree_input_line;
252b5132 7019
24eab124 7020 exp_seg = expression (exp);
252b5132 7021
636c26b0
AM		 7022 SKIP_WHITESPACE ();
7023 if (*input_line_pointer)
7024 as_bad (_("junk `%s' after expression"), input_line_pointer);
7025#if GCC_ASM_O_HACK
7026 RESTORE_END_STRING (disp_end + 1);
7027#endif
636c26b0 7028 input_line_pointer = save_input_line_pointer;
636c26b0 7029 if (gotfree_input_line)
ee86248c
JB		 7030 {
7031 free (gotfree_input_line);
7032
7033 if (exp->X_op == O_constant || exp->X_op == O_register)
7034 exp->X_op = O_illegal;
7035 }
7036
7037 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
7038
7039 RESTORE_END_STRING (disp_end);
7040
7041 return ret;
7042}
7043
7044static int
7045i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7046 i386_operand_type types, const char *disp_start)
7047{
7048 i386_operand_type bigdisp;
7049 int ret = 1;
636c26b0 7050
24eab124
AM		 7051 /* We do this to make sure that the section symbol is in
7052 the symbol table. We will ultimately change the relocation
47926f60 7053 to be relative to the beginning of the section. */
1ae12ab7 7054 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 7055 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
7056 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 7057 {
636c26b0 7058 if (exp->X_op != O_symbol)
3992d3b7 7059 goto inv_disp;
636c26b0 7060
e5cb08ac 7061 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 7062 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
7063 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 7064 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 7065 exp->X_op = O_subtract;
7066 exp->X_op_symbol = GOT_symbol;
1ae12ab7 7067 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 7068 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 7069 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
7070 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 7071 else
29b0f896 7072 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 7073 }
252b5132 7074
3992d3b7
AM		 7075 else if (exp->X_op == O_absent
7076 || exp->X_op == O_illegal
ee86248c 7077 || exp->X_op == O_big)
2daf4fd8 7078 {
3992d3b7
AM		 7079 inv_disp:
7080 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 7081 disp_start);
3992d3b7 7082 ret = 0;
2daf4fd8
AM		 7083 }
7084
0e1147d9
L		 7085 else if (flag_code == CODE_64BIT
7086 && !i.prefix[ADDR_PREFIX]
7087 && exp->X_op == O_constant)
7088 {
7089 /* Since displacement is signed extended to 64bit, don't allow
7090 disp32 and turn off disp32s if they are out of range. */
7091 i.types[this_operand].bitfield.disp32 = 0;
7092 if (!fits_in_signed_long (exp->X_add_number))
7093 {
7094 i.types[this_operand].bitfield.disp32s = 0;
7095 if (i.types[this_operand].bitfield.baseindex)
7096 {
7097 as_bad (_("0x%lx out range of signed 32bit displacement"),
7098 (long) exp->X_add_number);
7099 ret = 0;
7100 }
7101 }
7102 }
7103
4c63da97 7104#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 7105 else if (exp->X_op != O_constant
7106 && OUTPUT_FLAVOR == bfd_target_aout_flavour
7107 && exp_seg != absolute_section
7108 && exp_seg != text_section
7109 && exp_seg != data_section
7110 && exp_seg != bss_section
7111 && exp_seg != undefined_section
7112 && !bfd_is_com_section (exp_seg))
24eab124 7113 {
d0b47220 7114 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 7115 ret = 0;
24eab124 7116 }
252b5132 7117#endif
3956db08 7118
40fb9820
L		 7119 /* Check if this is a displacement only operand. */
7120 bigdisp = i.types[this_operand];
7121 bigdisp.bitfield.disp8 = 0;
7122 bigdisp.bitfield.disp16 = 0;
7123 bigdisp.bitfield.disp32 = 0;
7124 bigdisp.bitfield.disp32s = 0;
7125 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 7126 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 7127 i.types[this_operand] = operand_type_and (i.types[this_operand],
7128 types);
3956db08 7129
3992d3b7 7130 return ret;
252b5132
RH		 7131}
7132
eecb386c 7133/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 7134 Return 1 on success, 0 on a failure. */
7135
252b5132 7136static int
e3bb37b5 7137i386_index_check (const char *operand_string)
252b5132 7138{
3e73aa7c 7139 int ok;
fc0763e6 7140 const char *kind = "base/index";
24eab124 7141#if INFER_ADDR_PREFIX
eecb386c
AM		 7142 int fudged = 0;
7143
24eab124
AM		 7144 tryprefix:
7145#endif
3e73aa7c 7146 ok = 1;
fc0763e6
JB		 7147 if (current_templates->start->opcode_modifier.isstring
7148 && !current_templates->start->opcode_modifier.immext
7149 && (current_templates->end[-1].opcode_modifier.isstring
7150 || i.mem_operands))
7151 {
7152 /* Memory operands of string insns are special in that they only allow
7153 a single register (rDI, rSI, or rBX) as their memory address. */
7154 unsigned int expected;
7155
7156 kind = "string address";
7157
7158 if (current_templates->start->opcode_modifier.w)
7159 {
7160 i386_operand_type type = current_templates->end[-1].operand_types[0];
7161
7162 if (!type.bitfield.baseindex
7163 || ((!i.mem_operands != !intel_syntax)
7164 && current_templates->end[-1].operand_types[1]
7165 .bitfield.baseindex))
7166 type = current_templates->end[-1].operand_types[1];
7167 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
7168 }
7169 else
7170 expected = 3 /* rBX */;
7171
7172 if (!i.base_reg || i.index_reg
7173 || operand_type_check (i.types[this_operand], disp))
7174 ok = -1;
7175 else if (!(flag_code == CODE_64BIT
7176 ? i.prefix[ADDR_PREFIX]
7177 ? i.base_reg->reg_type.bitfield.reg32
7178 : i.base_reg->reg_type.bitfield.reg64
7179 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7180 ? i.base_reg->reg_type.bitfield.reg32
7181 : i.base_reg->reg_type.bitfield.reg16))
7182 ok = 0;
7183 else if (i.base_reg->reg_num != expected)
7184 ok = -1;
7185
7186 if (ok < 0)
7187 {
7188 unsigned int j;
7189
7190 for (j = 0; j < i386_regtab_size; ++j)
7191 if ((flag_code == CODE_64BIT
7192 ? i.prefix[ADDR_PREFIX]
7193 ? i386_regtab[j].reg_type.bitfield.reg32
7194 : i386_regtab[j].reg_type.bitfield.reg64
7195 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7196 ? i386_regtab[j].reg_type.bitfield.reg32
7197 : i386_regtab[j].reg_type.bitfield.reg16)
7198 && i386_regtab[j].reg_num == expected)
7199 break;
9c2799c2 7200 gas_assert (j < i386_regtab_size);
fc0763e6
JB		 7201 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7202 operand_string,
7203 intel_syntax ? '[' : '(',
7204 register_prefix,
7205 i386_regtab[j].reg_name,
7206 intel_syntax ? ']' : ')');
7207 ok = 1;
7208 }
7209 }
7210 else if (flag_code == CODE_64BIT)
64e74474 7211 {
64e74474 7212 if ((i.base_reg
40fb9820
L		 7213 && ((i.prefix[ADDR_PREFIX] == 0
7214 && !i.base_reg->reg_type.bitfield.reg64)
7215 || (i.prefix[ADDR_PREFIX]
7216 && !i.base_reg->reg_type.bitfield.reg32))
7217 && (i.index_reg
9a04903e
JB		 7218 || i.base_reg->reg_num !=
7219 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 7220 || (i.index_reg
6c30d220
L		 7221 && !(i.index_reg->reg_type.bitfield.regxmm
7222 || i.index_reg->reg_type.bitfield.regymm)
40fb9820
L		 7223 && (!i.index_reg->reg_type.bitfield.baseindex
7224 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 7225 && i.index_reg->reg_num != RegRiz
7226 && !i.index_reg->reg_type.bitfield.reg64
7227 )
40fb9820 7228 || (i.prefix[ADDR_PREFIX]
db51cc60 7229 && i.index_reg->reg_num != RegEiz
40fb9820 7230 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 7231 ok = 0;
3e73aa7c
JH		 7232 }
7233 else
7234 {
7235 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
7236 {
7237 /* 16bit checks. */
7238 if ((i.base_reg
40fb9820
L		 7239 && (!i.base_reg->reg_type.bitfield.reg16
7240 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 7241 || (i.index_reg
40fb9820
L		 7242 && (!i.index_reg->reg_type.bitfield.reg16
7243 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 7244 || !(i.base_reg
7245 && i.base_reg->reg_num < 6
7246 && i.index_reg->reg_num >= 6
7247 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 7248 ok = 0;
7249 }
7250 else
e5cb08ac 7251 {
3e73aa7c
JH		 7252 /* 32bit checks. */
7253 if ((i.base_reg
40fb9820 7254 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 7255 || (i.index_reg
6c30d220
L		 7256 && !i.index_reg->reg_type.bitfield.regxmm
7257 && !i.index_reg->reg_type.bitfield.regymm
db51cc60
L		 7258 && ((!i.index_reg->reg_type.bitfield.reg32
7259 && i.index_reg->reg_num != RegEiz)
40fb9820 7260 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 7261 ok = 0;
3e73aa7c
JH		 7262 }
7263 }
7264 if (!ok)
24eab124
AM		 7265 {
7266#if INFER_ADDR_PREFIX
fc0763e6 7267 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 7268 {
7269 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
7270 i.prefixes += 1;
b23bac36
AM		 7271 /* Change the size of any displacement too. At most one of
7272 Disp16 or Disp32 is set.
7273 FIXME. There doesn't seem to be any real need for separate
7274 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 7275 Removing them would probably clean up the code quite a lot. */
4eed87de 7276 if (flag_code != CODE_64BIT
40fb9820
L		 7277 && (i.types[this_operand].bitfield.disp16
7278 || i.types[this_operand].bitfield.disp32))
7279 i.types[this_operand]
c6fb90c8 7280 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 7281 fudged = 1;
24eab124
AM		 7282 goto tryprefix;
7283 }
eecb386c 7284 if (fudged)
fc0763e6
JB		 7285 as_bad (_("`%s' is not a valid %s expression"),
7286 operand_string,
7287 kind);
eecb386c 7288 else
c388dee8 7289#endif
fc0763e6 7290 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 7291 operand_string,
fc0763e6
JB		 7292 flag_code_names[i.prefix[ADDR_PREFIX]
7293 ? flag_code == CODE_32BIT
7294 ? CODE_16BIT
7295 : CODE_32BIT
7296 : flag_code],
7297 kind);
24eab124 7298 }
20f0a1fc 7299 return ok;
24eab124 7300}
252b5132 7301
fc0763e6 7302/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 7303 on error. */
252b5132 7304
252b5132 7305static int
a7619375 7306i386_att_operand (char *operand_string)
252b5132 7307{
af6bdddf
AM		 7308 const reg_entry *r;
7309 char *end_op;
24eab124 7310 char *op_string = operand_string;
252b5132 7311
24eab124 7312 if (is_space_char (*op_string))
252b5132
RH		 7313 ++op_string;
7314
24eab124 7315 /* We check for an absolute prefix (differentiating,
47926f60 7316 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 7317 if (*op_string == ABSOLUTE_PREFIX)
7318 {
7319 ++op_string;
7320 if (is_space_char (*op_string))
7321 ++op_string;
40fb9820 7322 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 7323 }
252b5132 7324
47926f60 7325 /* Check if operand is a register. */
4d1bb795 7326 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 7327 {
40fb9820
L		 7328 i386_operand_type temp;
7329
24eab124
AM		 7330 /* Check for a segment override by searching for ':' after a
7331 segment register. */
7332 op_string = end_op;
7333 if (is_space_char (*op_string))
7334 ++op_string;
40fb9820
L		 7335 if (*op_string == ':'
7336 && (r->reg_type.bitfield.sreg2
7337 || r->reg_type.bitfield.sreg3))
24eab124
AM		 7338 {
7339 switch (r->reg_num)
7340 {
7341 case 0:
7342 i.seg[i.mem_operands] = &es;
7343 break;
7344 case 1:
7345 i.seg[i.mem_operands] = &cs;
7346 break;
7347 case 2:
7348 i.seg[i.mem_operands] = &ss;
7349 break;
7350 case 3:
7351 i.seg[i.mem_operands] = &ds;
7352 break;
7353 case 4:
7354 i.seg[i.mem_operands] = &fs;
7355 break;
7356 case 5:
7357 i.seg[i.mem_operands] = &gs;
7358 break;
7359 }
252b5132 7360
24eab124 7361 /* Skip the ':' and whitespace. */
252b5132
RH		 7362 ++op_string;
7363 if (is_space_char (*op_string))
24eab124 7364 ++op_string;
252b5132 7365
24eab124
AM		 7366 if (!is_digit_char (*op_string)
7367 && !is_identifier_char (*op_string)
7368 && *op_string != '('
7369 && *op_string != ABSOLUTE_PREFIX)
7370 {
7371 as_bad (_("bad memory operand `%s'"), op_string);
7372 return 0;
7373 }
47926f60 7374 /* Handle case of %es:*foo. */
24eab124
AM		 7375 if (*op_string == ABSOLUTE_PREFIX)
7376 {
7377 ++op_string;
7378 if (is_space_char (*op_string))
7379 ++op_string;
40fb9820 7380 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 7381 }
7382 goto do_memory_reference;
7383 }
7384 if (*op_string)
7385 {
d0b47220 7386 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 7387 return 0;
7388 }
40fb9820
L		 7389 temp = r->reg_type;
7390 temp.bitfield.baseindex = 0;
c6fb90c8
L		 7391 i.types[this_operand] = operand_type_or (i.types[this_operand],
7392 temp);
7d5e4556 7393 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 7394 i.op[this_operand].regs = r;
24eab124
AM		 7395 i.reg_operands++;
7396 }
af6bdddf
AM		 7397 else if (*op_string == REGISTER_PREFIX)
7398 {
7399 as_bad (_("bad register name `%s'"), op_string);
7400 return 0;
7401 }
24eab124 7402 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7403 {
24eab124 7404 ++op_string;
40fb9820 7405 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7406 {
d0b47220 7407 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7408 return 0;
7409 }
7410 if (!i386_immediate (op_string))
7411 return 0;
7412 }
7413 else if (is_digit_char (*op_string)
7414 || is_identifier_char (*op_string)
e5cb08ac 7415 || *op_string == '(')
24eab124 7416 {
47926f60 7417 /* This is a memory reference of some sort. */
af6bdddf 7418 char *base_string;
252b5132 7419
47926f60 7420 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7421 char *displacement_string_start;
7422 char *displacement_string_end;
252b5132 7423
24eab124 7424 do_memory_reference:
24eab124 7425 if ((i.mem_operands == 1
40fb9820 7426 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7427 || i.mem_operands == 2)
7428 {
7429 as_bad (_("too many memory references for `%s'"),
7430 current_templates->start->name);
7431 return 0;
7432 }
252b5132 7433
24eab124
AM		 7434 /* Check for base index form. We detect the base index form by
7435 looking for an ')' at the end of the operand, searching
7436 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7437 after the '('. */
af6bdddf 7438 base_string = op_string + strlen (op_string);
c3332e24 7439
af6bdddf
AM		 7440 --base_string;
7441 if (is_space_char (*base_string))
7442 --base_string;
252b5132 7443
47926f60 7444 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7445 displacement_string_start = op_string;
7446 displacement_string_end = base_string + 1;
252b5132 7447
24eab124
AM		 7448 if (*base_string == ')')
7449 {
af6bdddf 7450 char *temp_string;
24eab124
AM		 7451 unsigned int parens_balanced = 1;
7452 /* We've already checked that the number of left & right ()'s are
47926f60 7453 equal, so this loop will not be infinite. */
24eab124
AM		 7454 do
7455 {
7456 base_string--;
7457 if (*base_string == ')')
7458 parens_balanced++;
7459 if (*base_string == '(')
7460 parens_balanced--;
7461 }
7462 while (parens_balanced);
c3332e24 7463
af6bdddf 7464 temp_string = base_string;
c3332e24 7465
24eab124 7466 /* Skip past '(' and whitespace. */
252b5132
RH		 7467 ++base_string;
7468 if (is_space_char (*base_string))
24eab124 7469 ++base_string;
252b5132 7470
af6bdddf 7471 if (*base_string == ','
4eed87de
AM		 7472 || ((i.base_reg = parse_register (base_string, &end_op))
7473 != NULL))
252b5132 7474 {
af6bdddf 7475 displacement_string_end = temp_string;
252b5132 7476
40fb9820 7477 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7478
af6bdddf 7479 if (i.base_reg)
24eab124 7480 {
24eab124
AM		 7481 base_string = end_op;
7482 if (is_space_char (*base_string))
7483 ++base_string;
af6bdddf
AM		 7484 }
7485
7486 /* There may be an index reg or scale factor here. */
7487 if (*base_string == ',')
7488 {
7489 ++base_string;
7490 if (is_space_char (*base_string))
7491 ++base_string;
7492
4eed87de
AM		 7493 if ((i.index_reg = parse_register (base_string, &end_op))
7494 != NULL)
24eab124 7495 {
af6bdddf 7496 base_string = end_op;
24eab124
AM		 7497 if (is_space_char (*base_string))
7498 ++base_string;
af6bdddf
AM		 7499 if (*base_string == ',')
7500 {
7501 ++base_string;
7502 if (is_space_char (*base_string))
7503 ++base_string;
7504 }
e5cb08ac 7505 else if (*base_string != ')')
af6bdddf 7506 {
4eed87de
AM		 7507 as_bad (_("expecting `,' or `)' "
7508 "after index register in `%s'"),
af6bdddf
AM		 7509 operand_string);
7510 return 0;
7511 }
24eab124 7512 }
af6bdddf 7513 else if (*base_string == REGISTER_PREFIX)
24eab124 7514 {
af6bdddf 7515 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7516 return 0;
7517 }
252b5132 7518
47926f60 7519 /* Check for scale factor. */
551c1ca1 7520 if (*base_string != ')')
af6bdddf 7521 {
551c1ca1
AM		 7522 char *end_scale = i386_scale (base_string);
7523
7524 if (!end_scale)
af6bdddf 7525 return 0;
24eab124 7526
551c1ca1 7527 base_string = end_scale;
af6bdddf
AM		 7528 if (is_space_char (*base_string))
7529 ++base_string;
7530 if (*base_string != ')')
7531 {
4eed87de
AM		 7532 as_bad (_("expecting `)' "
7533 "after scale factor in `%s'"),
af6bdddf
AM		 7534 operand_string);
7535 return 0;
7536 }
7537 }
7538 else if (!i.index_reg)
24eab124 7539 {
4eed87de
AM		 7540 as_bad (_("expecting index register or scale factor "
7541 "after `,'; got '%c'"),
af6bdddf 7542 *base_string);
24eab124
AM		 7543 return 0;
7544 }
7545 }
af6bdddf 7546 else if (*base_string != ')')
24eab124 7547 {
4eed87de
AM		 7548 as_bad (_("expecting `,' or `)' "
7549 "after base register in `%s'"),
af6bdddf 7550 operand_string);
24eab124
AM		 7551 return 0;
7552 }
c3332e24 7553 }
af6bdddf 7554 else if (*base_string == REGISTER_PREFIX)
c3332e24 7555 {
af6bdddf 7556 as_bad (_("bad register name `%s'"), base_string);
24eab124 7557 return 0;
c3332e24 7558 }
24eab124
AM		 7559 }
7560
7561 /* If there's an expression beginning the operand, parse it,
7562 assuming displacement_string_start and
7563 displacement_string_end are meaningful. */
7564 if (displacement_string_start != displacement_string_end)
7565 {
7566 if (!i386_displacement (displacement_string_start,
7567 displacement_string_end))
7568 return 0;
7569 }
7570
7571 /* Special case for (%dx) while doing input/output op. */
7572 if (i.base_reg
0dfbf9d7
L		 7573 && operand_type_equal (&i.base_reg->reg_type,
7574 &reg16_inoutportreg)
24eab124
AM		 7575 && i.index_reg == 0
7576 && i.log2_scale_factor == 0
7577 && i.seg[i.mem_operands] == 0
40fb9820 7578 && !operand_type_check (i.types[this_operand], disp))
24eab124 7579 {
65da13b5 7580 i.types[this_operand] = inoutportreg;
24eab124
AM		 7581 return 1;
7582 }
7583
eecb386c
AM		 7584 if (i386_index_check (operand_string) == 0)
7585 return 0;
5c07affc 7586 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7587 i.mem_operands++;
7588 }
7589 else
ce8a8b2f
AM		 7590 {
7591 /* It's not a memory operand; argh! */
24eab124
AM		 7592 as_bad (_("invalid char %s beginning operand %d `%s'"),
7593 output_invalid (*op_string),
7594 this_operand + 1,
7595 op_string);
7596 return 0;
7597 }
47926f60 7598 return 1; /* Normal return. */
252b5132
RH		 7599}
7600\f
ee7fcc42
AM		 7601/* md_estimate_size_before_relax()
7602
7603 Called just before relax() for rs_machine_dependent frags. The x86
7604 assembler uses these frags to handle variable size jump
7605 instructions.
7606
7607 Any symbol that is now undefined will not become defined.
7608 Return the correct fr_subtype in the frag.
7609 Return the initial "guess for variable size of frag" to caller.
7610 The guess is actually the growth beyond the fixed part. Whatever
7611 we do to grow the fixed or variable part contributes to our
7612 returned value. */
7613
252b5132 7614int
7016a5d5 7615md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 7616{
252b5132 7617 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7618 check for un-relaxable symbols. On an ELF system, we can't relax
7619 an externally visible symbol, because it may be overridden by a
7620 shared library. */
7621 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7622#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7623 || (IS_ELF
31312f95 7624 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 7625 || S_IS_WEAK (fragP->fr_symbol)
7626 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7627 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 7628#endif
7629#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 7630 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 7631 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 7632#endif
7633 )
252b5132 7634 {
b98ef147
AM		 7635 /* Symbol is undefined in this segment, or we need to keep a
7636 reloc so that weak symbols can be overridden. */
7637 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7638 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7639 unsigned char *opcode;
7640 int old_fr_fix;
f6af82bd 7641
ee7fcc42 7642 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 7643 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 7644 else if (size == 2)
f6af82bd
AM		 7645 reloc_type = BFD_RELOC_16_PCREL;
7646 else
7647 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7648
ee7fcc42
AM		 7649 old_fr_fix = fragP->fr_fix;
7650 opcode = (unsigned char *) fragP->fr_opcode;
7651
fddf5b5b 7652 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7653 {
fddf5b5b
AM		 7654 case UNCOND_JUMP:
7655 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7656 opcode[0] = 0xe9;
252b5132 7657 fragP->fr_fix += size;
062cd5e7
AS		 7658 fix_new (fragP, old_fr_fix, size,
7659 fragP->fr_symbol,
7660 fragP->fr_offset, 1,
7661 reloc_type);
252b5132
RH		 7662 break;
7663
fddf5b5b 7664 case COND_JUMP86:
412167cb
AM		 7665 if (size == 2
7666 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7667 {
7668 /* Negate the condition, and branch past an
7669 unconditional jump. */
7670 opcode[0] ^= 1;
7671 opcode[1] = 3;
7672 /* Insert an unconditional jump. */
7673 opcode[2] = 0xe9;
7674 /* We added two extra opcode bytes, and have a two byte
7675 offset. */
7676 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7677 fix_new (fragP, old_fr_fix + 2, 2,
7678 fragP->fr_symbol,
7679 fragP->fr_offset, 1,
7680 reloc_type);
fddf5b5b
AM		 7681 break;
7682 }
7683 /* Fall through. */
7684
7685 case COND_JUMP:
412167cb
AM		 7686 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7687 {
3e02c1cc
AM		 7688 fixS *fixP;
7689
412167cb 7690 fragP->fr_fix += 1;
3e02c1cc
AM		 7691 fixP = fix_new (fragP, old_fr_fix, 1,
7692 fragP->fr_symbol,
7693 fragP->fr_offset, 1,
7694 BFD_RELOC_8_PCREL);
7695 fixP->fx_signed = 1;
412167cb
AM		 7696 break;
7697 }
93c2a809 7698
24eab124 7699 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7700 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7701 opcode[1] = opcode[0] + 0x10;
f6af82bd 7702 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7703 /* We've added an opcode byte. */
7704 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7705 fix_new (fragP, old_fr_fix + 1, size,
7706 fragP->fr_symbol,
7707 fragP->fr_offset, 1,
7708 reloc_type);
252b5132 7709 break;
fddf5b5b
AM		 7710
7711 default:
7712 BAD_CASE (fragP->fr_subtype);
7713 break;
252b5132
RH		 7714 }
7715 frag_wane (fragP);
ee7fcc42 7716 return fragP->fr_fix - old_fr_fix;
252b5132 7717 }
93c2a809 7718
93c2a809
AM		 7719 /* Guess size depending on current relax state. Initially the relax
7720 state will correspond to a short jump and we return 1, because
7721 the variable part of the frag (the branch offset) is one byte
7722 long. However, we can relax a section more than once and in that
7723 case we must either set fr_subtype back to the unrelaxed state,
7724 or return the value for the appropriate branch. */
7725 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7726}
7727
47926f60
KH		 7728/* Called after relax() is finished.
7729
7730 In: Address of frag.
7731 fr_type == rs_machine_dependent.
7732 fr_subtype is what the address relaxed to.
7733
7734 Out: Any fixSs and constants are set up.
7735 Caller will turn frag into a ".space 0". */
7736
252b5132 7737void
7016a5d5
TG		 7738md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
7739 fragS *fragP)
252b5132 7740{
29b0f896 7741 unsigned char *opcode;
252b5132 7742 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7743 offsetT target_address;
7744 offsetT opcode_address;
252b5132 7745 unsigned int extension = 0;
847f7ad4 7746 offsetT displacement_from_opcode_start;
252b5132
RH		 7747
7748 opcode = (unsigned char *) fragP->fr_opcode;
7749
47926f60 7750 /* Address we want to reach in file space. */
252b5132 7751 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7752
47926f60 7753 /* Address opcode resides at in file space. */
252b5132
RH		 7754 opcode_address = fragP->fr_address + fragP->fr_fix;
7755
47926f60 7756 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7757 displacement_from_opcode_start = target_address - opcode_address;
7758
fddf5b5b 7759 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7760 {
47926f60
KH		 7761 /* Don't have to change opcode. */
7762 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7763 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7764 }
7765 else
7766 {
7767 if (no_cond_jump_promotion
7768 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7769 as_warn_where (fragP->fr_file, fragP->fr_line,
7770 _("long jump required"));
252b5132 7771
fddf5b5b
AM		 7772 switch (fragP->fr_subtype)
7773 {
7774 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7775 extension = 4; /* 1 opcode + 4 displacement */
7776 opcode[0] = 0xe9;
7777 where_to_put_displacement = &opcode[1];
7778 break;
252b5132 7779
fddf5b5b
AM		 7780 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7781 extension = 2; /* 1 opcode + 2 displacement */
7782 opcode[0] = 0xe9;
7783 where_to_put_displacement = &opcode[1];
7784 break;
252b5132 7785
fddf5b5b
AM		 7786 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7787 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7788 extension = 5; /* 2 opcode + 4 displacement */
7789 opcode[1] = opcode[0] + 0x10;
7790 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7791 where_to_put_displacement = &opcode[2];
7792 break;
252b5132 7793
fddf5b5b
AM		 7794 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7795 extension = 3; /* 2 opcode + 2 displacement */
7796 opcode[1] = opcode[0] + 0x10;
7797 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7798 where_to_put_displacement = &opcode[2];
7799 break;
252b5132 7800
fddf5b5b
AM		 7801 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7802 extension = 4;
7803 opcode[0] ^= 1;
7804 opcode[1] = 3;
7805 opcode[2] = 0xe9;
7806 where_to_put_displacement = &opcode[3];
7807 break;
7808
7809 default:
7810 BAD_CASE (fragP->fr_subtype);
7811 break;
7812 }
252b5132 7813 }
fddf5b5b 7814
7b81dfbb
AJ		 7815 /* If size if less then four we are sure that the operand fits,
7816 but if it's 4, then it could be that the displacement is larger
7817 then -/+ 2GB. */
7818 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7819 && object_64bit
7820 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7821 + ((addressT) 1 << 31))
7822 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7823 {
7824 as_bad_where (fragP->fr_file, fragP->fr_line,
7825 _("jump target out of range"));
7826 /* Make us emit 0. */
7827 displacement_from_opcode_start = extension;
7828 }
47926f60 7829 /* Now put displacement after opcode. */
252b5132
RH		 7830 md_number_to_chars ((char *) where_to_put_displacement,
7831 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7832 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7833 fragP->fr_fix += extension;
7834}
7835\f
7016a5d5 7836/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 7837 by our caller that we have all the info we need to fix it up.
7838
7016a5d5
TG		 7839 Parameter valP is the pointer to the value of the bits.
7840
252b5132
RH		 7841 On the 386, immediates, displacements, and data pointers are all in
7842 the same (little-endian) format, so we don't need to care about which
7843 we are handling. */
7844
94f592af 7845void
7016a5d5 7846md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 7847{
94f592af 7848 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7849 valueT value = *valP;
252b5132 7850
f86103b7 7851#if !defined (TE_Mach)
93382f6d
AM		 7852 if (fixP->fx_pcrel)
7853 {
7854 switch (fixP->fx_r_type)
7855 {
5865bb77
ILT		 7856 default:
7857 break;
7858
d6ab8113
JB		 7859 case BFD_RELOC_64:
7860 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7861 break;
93382f6d 7862 case BFD_RELOC_32:
ae8887b5 7863 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7864 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7865 break;
7866 case BFD_RELOC_16:
7867 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7868 break;
7869 case BFD_RELOC_8:
7870 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7871 break;
7872 }
7873 }
252b5132 7874
a161fe53 7875 if (fixP->fx_addsy != NULL
31312f95 7876 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7877 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7878 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7879 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7880 && !use_rela_relocations)
252b5132 7881 {
31312f95
AM		 7882 /* This is a hack. There should be a better way to handle this.
7883 This covers for the fact that bfd_install_relocation will
7884 subtract the current location (for partial_inplace, PC relative
7885 relocations); see more below. */
252b5132 7886#ifndef OBJ_AOUT
718ddfc0 7887 if (IS_ELF
252b5132
RH		 7888#ifdef TE_PE
7889 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7890#endif
7891 )
7892 value += fixP->fx_where + fixP->fx_frag->fr_address;
7893#endif
7894#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7895 if (IS_ELF)
252b5132 7896 {
6539b54b 7897 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7898
6539b54b 7899 if ((sym_seg == seg
2f66722d 7900 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7901 && sym_seg != absolute_section))
af65af87 7902 && !generic_force_reloc (fixP))
2f66722d
AM		 7903 {
7904 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7905 bfd_install_relocation subtracts them out again. I think
7906 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7907 it. FIXME. */
7908 value += fixP->fx_where + fixP->fx_frag->fr_address;
7909 }
252b5132
RH		 7910 }
7911#endif
7912#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7913 /* For some reason, the PE format does not store a
7914 section address offset for a PC relative symbol. */
7915 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7916 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7917 value += md_pcrel_from (fixP);
7918#endif
7919 }
fbeb56a4
DK		 7920#if defined (OBJ_COFF) && defined (TE_PE)
7921 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7922 {
7923 value -= S_GET_VALUE (fixP->fx_addsy);
7924 }
7925#endif
252b5132
RH		 7926
7927 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7928 and we must not disappoint it. */
252b5132 7929#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7930 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7931 switch (fixP->fx_r_type)
7932 {
7933 case BFD_RELOC_386_PLT32:
3e73aa7c 7934 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7935 /* Make the jump instruction point to the address of the operand. At
7936 runtime we merely add the offset to the actual PLT entry. */
7937 value = -4;
7938 break;
31312f95 7939
13ae64f3
JJ		 7940 case BFD_RELOC_386_TLS_GD:
7941 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7942 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7943 case BFD_RELOC_386_TLS_IE:
7944 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7945 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7946 case BFD_RELOC_X86_64_TLSGD:
7947 case BFD_RELOC_X86_64_TLSLD:
7948 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7949 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7950 value = 0; /* Fully resolved at runtime. No addend. */
7951 /* Fallthrough */
7952 case BFD_RELOC_386_TLS_LE:
7953 case BFD_RELOC_386_TLS_LDO_32:
7954 case BFD_RELOC_386_TLS_LE_32:
7955 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7956 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7957 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7958 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7959 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7960 break;
7961
67a4f2b7
AO		 7962 case BFD_RELOC_386_TLS_DESC_CALL:
7963 case BFD_RELOC_X86_64_TLSDESC_CALL:
7964 value = 0; /* Fully resolved at runtime. No addend. */
7965 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7966 fixP->fx_done = 0;
7967 return;
7968
00f7efb6
JJ		 7969 case BFD_RELOC_386_GOT32:
7970 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7971 value = 0; /* Fully resolved at runtime. No addend. */
7972 break;
47926f60
KH		 7973
7974 case BFD_RELOC_VTABLE_INHERIT:
7975 case BFD_RELOC_VTABLE_ENTRY:
7976 fixP->fx_done = 0;
94f592af 7977 return;
47926f60
KH		 7978
7979 default:
7980 break;
7981 }
7982#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7983 *valP = value;
f86103b7 7984#endif /* !defined (TE_Mach) */
3e73aa7c 7985
3e73aa7c 7986 /* Are we finished with this relocation now? */
c6682705 7987 if (fixP->fx_addsy == NULL)
3e73aa7c 7988 fixP->fx_done = 1;
fbeb56a4
DK		 7989#if defined (OBJ_COFF) && defined (TE_PE)
7990 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7991 {
7992 fixP->fx_done = 0;
7993 /* Remember value for tc_gen_reloc. */
7994 fixP->fx_addnumber = value;
7995 /* Clear out the frag for now. */
7996 value = 0;
7997 }
7998#endif
3e73aa7c
JH		 7999 else if (use_rela_relocations)
8000 {
8001 fixP->fx_no_overflow = 1;
062cd5e7
AS		 8002 /* Remember value for tc_gen_reloc. */
8003 fixP->fx_addnumber = value;
3e73aa7c
JH		 8004 value = 0;
8005 }
f86103b7 8006
94f592af 8007 md_number_to_chars (p, value, fixP->fx_size);
252b5132 8008}
252b5132 8009\f
252b5132 8010char *
499ac353 8011md_atof (int type, char *litP, int *sizeP)
252b5132 8012{
499ac353
NC		 8013 /* This outputs the LITTLENUMs in REVERSE order;
8014 in accord with the bigendian 386. */
8015 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 8016}
8017\f
2d545b82 8018static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 8019
252b5132 8020static char *
e3bb37b5 8021output_invalid (int c)
252b5132 8022{
3882b010 8023 if (ISPRINT (c))
f9f21a03
L		 8024 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
8025 "'%c'", c);
252b5132 8026 else
f9f21a03 8027 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 8028 "(0x%x)", (unsigned char) c);
252b5132
RH		 8029 return output_invalid_buf;
8030}
8031
af6bdddf 8032/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 8033
8034static const reg_entry *
4d1bb795 8035parse_real_register (char *reg_string, char **end_op)
252b5132 8036{
af6bdddf
AM		 8037 char *s = reg_string;
8038 char *p;
252b5132
RH		 8039 char reg_name_given[MAX_REG_NAME_SIZE + 1];
8040 const reg_entry *r;
8041
8042 /* Skip possible REGISTER_PREFIX and possible whitespace. */
8043 if (*s == REGISTER_PREFIX)
8044 ++s;
8045
8046 if (is_space_char (*s))
8047 ++s;
8048
8049 p = reg_name_given;
af6bdddf 8050 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 8051 {
8052 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 8053 return (const reg_entry *) NULL;
8054 s++;
252b5132
RH		 8055 }
8056
6588847e
DN		 8057 /* For naked regs, make sure that we are not dealing with an identifier.
8058 This prevents confusing an identifier like `eax_var' with register
8059 `eax'. */
8060 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
8061 return (const reg_entry *) NULL;
8062
af6bdddf 8063 *end_op = s;
252b5132
RH		 8064
8065 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
8066
5f47d35b 8067 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 8068 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 8069 {
5f47d35b
AM		 8070 if (is_space_char (*s))
8071 ++s;
8072 if (*s == '(')
8073 {
af6bdddf 8074 ++s;
5f47d35b
AM		 8075 if (is_space_char (*s))
8076 ++s;
8077 if (*s >= '0' && *s <= '7')
8078 {
db557034 8079 int fpr = *s - '0';
af6bdddf 8080 ++s;
5f47d35b
AM		 8081 if (is_space_char (*s))
8082 ++s;
8083 if (*s == ')')
8084 {
8085 *end_op = s + 1;
1e9cc1c2 8086 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 8087 know (r);
8088 return r + fpr;
5f47d35b 8089 }
5f47d35b 8090 }
47926f60 8091 /* We have "%st(" then garbage. */
5f47d35b
AM		 8092 return (const reg_entry *) NULL;
8093 }
8094 }
8095
a60de03c
JB		 8096 if (r == NULL || allow_pseudo_reg)
8097 return r;
8098
0dfbf9d7 8099 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 8100 return (const reg_entry *) NULL;
8101
192dc9c6
JB		 8102 if ((r->reg_type.bitfield.reg32
8103 || r->reg_type.bitfield.sreg3
8104 || r->reg_type.bitfield.control
8105 || r->reg_type.bitfield.debug
8106 || r->reg_type.bitfield.test)
8107 && !cpu_arch_flags.bitfield.cpui386)
8108 return (const reg_entry *) NULL;
8109
309d3373
JB		 8110 if (r->reg_type.bitfield.floatreg
8111 && !cpu_arch_flags.bitfield.cpu8087
8112 && !cpu_arch_flags.bitfield.cpu287
8113 && !cpu_arch_flags.bitfield.cpu387)
8114 return (const reg_entry *) NULL;
8115
192dc9c6
JB		 8116 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
8117 return (const reg_entry *) NULL;
8118
8119 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
8120 return (const reg_entry *) NULL;
8121
40f12533
L		 8122 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
8123 return (const reg_entry *) NULL;
8124
db51cc60 8125 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 8126 if (!allow_index_reg
db51cc60
L		 8127 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
8128 return (const reg_entry *) NULL;
8129
a60de03c
JB		 8130 if (((r->reg_flags & (RegRex64 | RegRex))
8131 || r->reg_type.bitfield.reg64)
40fb9820 8132 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 8133 || !operand_type_equal (&r->reg_type, &control))
1ae00879 8134 && flag_code != CODE_64BIT)
20f0a1fc 8135 return (const reg_entry *) NULL;
1ae00879 8136
b7240065
JB		 8137 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
8138 return (const reg_entry *) NULL;
8139
252b5132
RH		 8140 return r;
8141}
4d1bb795
JB		 8142
8143/* REG_STRING starts *before* REGISTER_PREFIX. */
8144
8145static const reg_entry *
8146parse_register (char *reg_string, char **end_op)
8147{
8148 const reg_entry *r;
8149
8150 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
8151 r = parse_real_register (reg_string, end_op);
8152 else
8153 r = NULL;
8154 if (!r)
8155 {
8156 char *save = input_line_pointer;
8157 char c;
8158 symbolS *symbolP;
8159
8160 input_line_pointer = reg_string;
8161 c = get_symbol_end ();
8162 symbolP = symbol_find (reg_string);
8163 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
8164 {
8165 const expressionS *e = symbol_get_value_expression (symbolP);
8166
0398aac5 8167 know (e->X_op == O_register);
4eed87de 8168 know (e->X_add_number >= 0
c3fe08fa 8169 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 8170 r = i386_regtab + e->X_add_number;
8171 *end_op = input_line_pointer;
8172 }
8173 *input_line_pointer = c;
8174 input_line_pointer = save;
8175 }
8176 return r;
8177}
8178
8179int
8180i386_parse_name (char *name, expressionS *e, char *nextcharP)
8181{
8182 const reg_entry *r;
8183 char *end = input_line_pointer;
8184
8185 *end = *nextcharP;
8186 r = parse_register (name, &input_line_pointer);
8187 if (r && end <= input_line_pointer)
8188 {
8189 *nextcharP = *input_line_pointer;
8190 *input_line_pointer = 0;
8191 e->X_op = O_register;
8192 e->X_add_number = r - i386_regtab;
8193 return 1;
8194 }
8195 input_line_pointer = end;
8196 *end = 0;
ee86248c 8197 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 8198}
8199
8200void
8201md_operand (expressionS *e)
8202{
ee86248c
JB		 8203 char *end;
8204 const reg_entry *r;
4d1bb795 8205
ee86248c
JB		 8206 switch (*input_line_pointer)
8207 {
8208 case REGISTER_PREFIX:
8209 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 8210 if (r)
8211 {
8212 e->X_op = O_register;
8213 e->X_add_number = r - i386_regtab;
8214 input_line_pointer = end;
8215 }
ee86248c
JB		 8216 break;
8217
8218 case '[':
9c2799c2 8219 gas_assert (intel_syntax);
ee86248c
JB		 8220 end = input_line_pointer++;
8221 expression (e);
8222 if (*input_line_pointer == ']')
8223 {
8224 ++input_line_pointer;
8225 e->X_op_symbol = make_expr_symbol (e);
8226 e->X_add_symbol = NULL;
8227 e->X_add_number = 0;
8228 e->X_op = O_index;
8229 }
8230 else
8231 {
8232 e->X_op = O_absent;
8233 input_line_pointer = end;
8234 }
8235 break;
4d1bb795
JB		 8236 }
8237}
8238
252b5132 8239\f
4cc782b5 8240#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 8241const char *md_shortopts = "kVQ:sqn";
252b5132 8242#else
12b55ccc 8243const char *md_shortopts = "qn";
252b5132 8244#endif
6e0b89ee 8245
3e73aa7c 8246#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 8247#define OPTION_64 (OPTION_MD_BASE + 1)
8248#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 8249#define OPTION_MARCH (OPTION_MD_BASE + 3)
8250#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 8251#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8252#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8253#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8254#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8255#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 8256#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 8257#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
40a9833c 8258#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 12)
570561f7 8259#define OPTION_X32 (OPTION_MD_BASE + 13)
b3b91714 8260
99ad8390
NC		 8261struct option md_longopts[] =
8262{
3e73aa7c 8263 {"32", no_argument, NULL, OPTION_32},
321098a5
L		 8264#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8265 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c 8266 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 8267#endif
8268#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 8269 {"x32", no_argument, NULL, OPTION_X32},
6e0b89ee 8270#endif
b3b91714 8271 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 8272 {"march", required_argument, NULL, OPTION_MARCH},
8273 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 8274 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
8275 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
8276 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
8277 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
8278 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 8279 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 8280 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
539f890d 8281 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
252b5132
RH		 8282 {NULL, no_argument, NULL, 0}
8283};
8284size_t md_longopts_size = sizeof (md_longopts);
8285
8286int
9103f4f4 8287md_parse_option (int c, char *arg)
252b5132 8288{
91d6fa6a 8289 unsigned int j;
6305a203 8290 char *arch, *next;
9103f4f4 8291
252b5132
RH		 8292 switch (c)
8293 {
12b55ccc
L		 8294 case 'n':
8295 optimize_align_code = 0;
8296 break;
8297
a38cf1db
AM		 8298 case 'q':
8299 quiet_warnings = 1;
252b5132
RH		 8300 break;
8301
8302#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 8303 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8304 should be emitted or not. FIXME: Not implemented. */
8305 case 'Q':
252b5132
RH		 8306 break;
8307
8308 /* -V: SVR4 argument to print version ID. */
8309 case 'V':
8310 print_version_id ();
8311 break;
8312
a38cf1db
AM		 8313 /* -k: Ignore for FreeBSD compatibility. */
8314 case 'k':
252b5132 8315 break;
4cc782b5
ILT		 8316
8317 case 's':
8318 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 8319 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 8320 break;
99ad8390 8321#endif
321098a5
L		 8322#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8323 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c
JH		 8324 case OPTION_64:
8325 {
8326 const char **list, **l;
8327
3e73aa7c
JH		 8328 list = bfd_target_list ();
8329 for (l = list; *l != NULL; l++)
8620418b 8330 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 8331 || strcmp (*l, "coff-x86-64") == 0
8332 || strcmp (*l, "pe-x86-64") == 0
8333 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 8334 {
8335 default_arch = "x86_64";
8336 break;
8337 }
3e73aa7c 8338 if (*l == NULL)
2b5d6a91 8339 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 8340 free (list);
8341 }
8342 break;
8343#endif
252b5132 8344
351f65ca 8345#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 8346 case OPTION_X32:
351f65ca
L		 8347 if (IS_ELF)
8348 {
8349 const char **list, **l;
8350
8351 list = bfd_target_list ();
8352 for (l = list; *l != NULL; l++)
8353 if (CONST_STRNEQ (*l, "elf32-x86-64"))
8354 {
8355 default_arch = "x86_64:32";
8356 break;
8357 }
8358 if (*l == NULL)
2b5d6a91 8359 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 8360 free (list);
8361 }
8362 else
8363 as_fatal (_("32bit x86_64 is only supported for ELF"));
8364 break;
8365#endif
8366
6e0b89ee
AM		 8367 case OPTION_32:
8368 default_arch = "i386";
8369 break;
8370
b3b91714
AM		 8371 case OPTION_DIVIDE:
8372#ifdef SVR4_COMMENT_CHARS
8373 {
8374 char *n, *t;
8375 const char *s;
8376
8377 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
8378 t = n;
8379 for (s = i386_comment_chars; *s != '\0'; s++)
8380 if (*s != '/')
8381 *t++ = *s;
8382 *t = '\0';
8383 i386_comment_chars = n;
8384 }
8385#endif
8386 break;
8387
9103f4f4 8388 case OPTION_MARCH:
6305a203
L		 8389 arch = xstrdup (arg);
8390 do
9103f4f4 8391 {
6305a203 8392 if (*arch == '.')
2b5d6a91 8393 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 8394 next = strchr (arch, '+');
8395 if (next)
8396 *next++ = '\0';
91d6fa6a 8397 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8398 {
91d6fa6a 8399 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 8400 {
6305a203 8401 /* Processor. */
1ded5609
JB		 8402 if (! cpu_arch[j].flags.bitfield.cpui386)
8403 continue;
8404
91d6fa6a 8405 cpu_arch_name = cpu_arch[j].name;
6305a203 8406 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 8407 cpu_arch_flags = cpu_arch[j].flags;
8408 cpu_arch_isa = cpu_arch[j].type;
8409 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 8410 if (!cpu_arch_tune_set)
8411 {
8412 cpu_arch_tune = cpu_arch_isa;
8413 cpu_arch_tune_flags = cpu_arch_isa_flags;
8414 }
8415 break;
8416 }
91d6fa6a
NC		 8417 else if (*cpu_arch [j].name == '.'
8418 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 8419 {
8420 /* ISA entension. */
8421 i386_cpu_flags flags;
309d3373 8422
49021df2 8423 if (!cpu_arch[j].negated)
309d3373 8424 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 8425 cpu_arch[j].flags);
309d3373
JB		 8426 else
8427 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 8428 cpu_arch[j].flags);
0dfbf9d7 8429 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8430 {
8431 if (cpu_sub_arch_name)
8432 {
8433 char *name = cpu_sub_arch_name;
8434 cpu_sub_arch_name = concat (name,
91d6fa6a 8435 cpu_arch[j].name,
1bf57e9f 8436 (const char *) NULL);
6305a203
L		 8437 free (name);
8438 }
8439 else
91d6fa6a 8440 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 8441 cpu_arch_flags = flags;
a586129e 8442 cpu_arch_isa_flags = flags;
6305a203
L		 8443 }
8444 break;
ccc9c027 8445 }
9103f4f4 8446 }
6305a203 8447
91d6fa6a 8448 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 8449 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 8450
8451 arch = next;
9103f4f4 8452 }
6305a203 8453 while (next != NULL );
9103f4f4
L		 8454 break;
8455
8456 case OPTION_MTUNE:
8457 if (*arg == '.')
2b5d6a91 8458 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 8459 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8460 {
91d6fa6a 8461 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 8462 {
ccc9c027 8463 cpu_arch_tune_set = 1;
91d6fa6a
NC		 8464 cpu_arch_tune = cpu_arch [j].type;
8465 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 8466 break;
8467 }
8468 }
91d6fa6a 8469 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 8470 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 8471 break;
8472
1efbbeb4
L		 8473 case OPTION_MMNEMONIC:
8474 if (strcasecmp (arg, "att") == 0)
8475 intel_mnemonic = 0;
8476 else if (strcasecmp (arg, "intel") == 0)
8477 intel_mnemonic = 1;
8478 else
2b5d6a91 8479 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 8480 break;
8481
8482 case OPTION_MSYNTAX:
8483 if (strcasecmp (arg, "att") == 0)
8484 intel_syntax = 0;
8485 else if (strcasecmp (arg, "intel") == 0)
8486 intel_syntax = 1;
8487 else
2b5d6a91 8488 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 8489 break;
8490
8491 case OPTION_MINDEX_REG:
8492 allow_index_reg = 1;
8493 break;
8494
8495 case OPTION_MNAKED_REG:
8496 allow_naked_reg = 1;
8497 break;
8498
8499 case OPTION_MOLD_GCC:
8500 old_gcc = 1;
1efbbeb4
L		 8501 break;
8502
c0f3af97
L		 8503 case OPTION_MSSE2AVX:
8504 sse2avx = 1;
8505 break;
8506
daf50ae7
L		 8507 case OPTION_MSSE_CHECK:
8508 if (strcasecmp (arg, "error") == 0)
8509 sse_check = sse_check_error;
8510 else if (strcasecmp (arg, "warning") == 0)
8511 sse_check = sse_check_warning;
8512 else if (strcasecmp (arg, "none") == 0)
8513 sse_check = sse_check_none;
8514 else
2b5d6a91 8515 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 8516 break;
8517
539f890d
L		 8518 case OPTION_MAVXSCALAR:
8519 if (strcasecmp (arg, "128") == 0)
8520 avxscalar = vex128;
8521 else if (strcasecmp (arg, "256") == 0)
8522 avxscalar = vex256;
8523 else
2b5d6a91 8524 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 8525 break;
8526
252b5132
RH		 8527 default:
8528 return 0;
8529 }
8530 return 1;
8531}
8532
8a2c8fef
L		 8533#define MESSAGE_TEMPLATE \
8534" "
8535
8536static void
1ded5609 8537show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 8538{
8539 static char message[] = MESSAGE_TEMPLATE;
8540 char *start = message + 27;
8541 char *p;
8542 int size = sizeof (MESSAGE_TEMPLATE);
8543 int left;
8544 const char *name;
8545 int len;
8546 unsigned int j;
8547
8548 p = start;
8549 left = size - (start - message);
8550 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
8551 {
8552 /* Should it be skipped? */
8553 if (cpu_arch [j].skip)
8554 continue;
8555
8556 name = cpu_arch [j].name;
8557 len = cpu_arch [j].len;
8558 if (*name == '.')
8559 {
8560 /* It is an extension. Skip if we aren't asked to show it. */
8561 if (ext)
8562 {
8563 name++;
8564 len--;
8565 }
8566 else
8567 continue;
8568 }
8569 else if (ext)
8570 {
8571 /* It is an processor. Skip if we show only extension. */
8572 continue;
8573 }
1ded5609
JB		 8574 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
8575 {
8576 /* It is an impossible processor - skip. */
8577 continue;
8578 }
8a2c8fef
L		 8579
8580 /* Reserve 2 spaces for ", " or ",\0" */
8581 left -= len + 2;
8582
8583 /* Check if there is any room. */
8584 if (left >= 0)
8585 {
8586 if (p != start)
8587 {
8588 *p++ = ',';
8589 *p++ = ' ';
8590 }
8591 p = mempcpy (p, name, len);
8592 }
8593 else
8594 {
8595 /* Output the current message now and start a new one. */
8596 *p++ = ',';
8597 *p = '\0';
8598 fprintf (stream, "%s\n", message);
8599 p = start;
8600 left = size - (start - message) - len - 2;
8601
8602 gas_assert (left >= 0);
8603
8604 p = mempcpy (p, name, len);
8605 }
8606 }
8607
8608 *p = '\0';
8609 fprintf (stream, "%s\n", message);
8610}
8611
252b5132 8612void
8a2c8fef 8613md_show_usage (FILE *stream)
252b5132 8614{
4cc782b5
ILT		 8615#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8616 fprintf (stream, _("\
a38cf1db
AM		 8617 -Q ignored\n\
8618 -V print assembler version number\n\
b3b91714
AM		 8619 -k ignored\n"));
8620#endif
8621 fprintf (stream, _("\
12b55ccc 8622 -n Do not optimize code alignment\n\
b3b91714
AM		 8623 -q quieten some warnings\n"));
8624#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8625 fprintf (stream, _("\
a38cf1db 8626 -s ignored\n"));
b3b91714 8627#endif
321098a5
L		 8628#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8629 || defined (TE_PE) || defined (TE_PEP))
751d281c 8630 fprintf (stream, _("\
570561f7 8631 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 8632#endif
b3b91714
AM		 8633#ifdef SVR4_COMMENT_CHARS
8634 fprintf (stream, _("\
8635 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8636#else
8637 fprintf (stream, _("\
b3b91714 8638 --divide ignored\n"));
4cc782b5 8639#endif
9103f4f4 8640 fprintf (stream, _("\
6305a203 8641 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 8642 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 8643 show_arch (stream, 0, 1);
8a2c8fef
L		 8644 fprintf (stream, _("\
8645 EXTENSION is combination of:\n"));
1ded5609 8646 show_arch (stream, 1, 0);
6305a203 8647 fprintf (stream, _("\
8a2c8fef 8648 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 8649 show_arch (stream, 0, 0);
ba104c83 8650 fprintf (stream, _("\
c0f3af97
L		 8651 -msse2avx encode SSE instructions with VEX prefix\n"));
8652 fprintf (stream, _("\
daf50ae7
L		 8653 -msse-check=[none|error|warning]\n\
8654 check SSE instructions\n"));
8655 fprintf (stream, _("\
539f890d
L		 8656 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8657 length\n"));
8658 fprintf (stream, _("\
ba104c83
L		 8659 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8660 fprintf (stream, _("\
8661 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8662 fprintf (stream, _("\
8663 -mindex-reg support pseudo index registers\n"));
8664 fprintf (stream, _("\
8665 -mnaked-reg don't require `%%' prefix for registers\n"));
8666 fprintf (stream, _("\
8667 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8668}
8669
3e73aa7c 8670#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 8671 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 8672 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 8673
8674/* Pick the target format to use. */
8675
47926f60 8676const char *
e3bb37b5 8677i386_target_format (void)
252b5132 8678{
351f65ca
L		 8679 if (!strncmp (default_arch, "x86_64", 6))
8680 {
8681 update_code_flag (CODE_64BIT, 1);
8682 if (default_arch[6] == '\0')
7f56bc95 8683 x86_elf_abi = X86_64_ABI;
351f65ca 8684 else
7f56bc95 8685 x86_elf_abi = X86_64_X32_ABI;
351f65ca 8686 }
3e73aa7c 8687 else if (!strcmp (default_arch, "i386"))
78f12dd3 8688 update_code_flag (CODE_32BIT, 1);
3e73aa7c 8689 else
2b5d6a91 8690 as_fatal (_("unknown architecture"));
89507696
JB		 8691
8692 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
8693 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
8694 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
8695 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
8696
252b5132
RH		 8697 switch (OUTPUT_FLAVOR)
8698 {
9384f2ff 8699#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 8700 case bfd_target_aout_flavour:
47926f60 8701 return AOUT_TARGET_FORMAT;
4c63da97 8702#endif
9384f2ff
AM		 8703#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8704# if defined (TE_PE) || defined (TE_PEP)
8705 case bfd_target_coff_flavour:
8706 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
8707# elif defined (TE_GO32)
0561d57c
JK		 8708 case bfd_target_coff_flavour:
8709 return "coff-go32";
9384f2ff 8710# else
252b5132
RH		 8711 case bfd_target_coff_flavour:
8712 return "coff-i386";
9384f2ff 8713# endif
4c63da97 8714#endif
3e73aa7c 8715#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8716 case bfd_target_elf_flavour:
3e73aa7c 8717 {
351f65ca
L		 8718 const char *format;
8719
8720 switch (x86_elf_abi)
4fa24527 8721 {
351f65ca
L		 8722 default:
8723 format = ELF_TARGET_FORMAT;
8724 break;
7f56bc95 8725 case X86_64_ABI:
351f65ca 8726 use_rela_relocations = 1;
4fa24527 8727 object_64bit = 1;
351f65ca
L		 8728 format = ELF_TARGET_FORMAT64;
8729 break;
7f56bc95 8730 case X86_64_X32_ABI:
4fa24527 8731 use_rela_relocations = 1;
351f65ca 8732 object_64bit = 1;
862be3fb 8733 disallow_64bit_reloc = 1;
351f65ca
L		 8734 format = ELF_TARGET_FORMAT32;
8735 break;
4fa24527 8736 }
3632d14b 8737 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 8738 {
7f56bc95 8739 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 8740 as_fatal (_("Intel L1OM is 64bit only"));
8741 return ELF_TARGET_L1OM_FORMAT;
8742 }
8743 else
351f65ca 8744 return format;
3e73aa7c 8745 }
e57f8c65
TG		 8746#endif
8747#if defined (OBJ_MACH_O)
8748 case bfd_target_mach_o_flavour:
8749 return flag_code == CODE_64BIT ? "mach-o-x86-64" : "mach-o-i386";
4c63da97 8750#endif
252b5132
RH		 8751 default:
8752 abort ();
8753 return NULL;
8754 }
8755}
8756
47926f60 8757#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8758
8759#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8760void
8761i386_elf_emit_arch_note (void)
a847613f 8762{
718ddfc0 8763 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8764 {
8765 char *p;
8766 asection *seg = now_seg;
8767 subsegT subseg = now_subseg;
8768 Elf_Internal_Note i_note;
8769 Elf_External_Note e_note;
8770 asection *note_secp;
8771 int len;
8772
8773 /* Create the .note section. */
8774 note_secp = subseg_new (".note", 0);
8775 bfd_set_section_flags (stdoutput,
8776 note_secp,
8777 SEC_HAS_CONTENTS | SEC_READONLY);
8778
8779 /* Process the arch string. */
8780 len = strlen (cpu_arch_name);
8781
8782 i_note.namesz = len + 1;
8783 i_note.descsz = 0;
8784 i_note.type = NT_ARCH;
8785 p = frag_more (sizeof (e_note.namesz));
8786 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8787 p = frag_more (sizeof (e_note.descsz));
8788 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8789 p = frag_more (sizeof (e_note.type));
8790 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8791 p = frag_more (len + 1);
8792 strcpy (p, cpu_arch_name);
8793
8794 frag_align (2, 0, 0);
8795
8796 subseg_set (seg, subseg);
8797 }
8798}
8799#endif
252b5132 8800\f
252b5132 8801symbolS *
7016a5d5 8802md_undefined_symbol (char *name)
252b5132 8803{
18dc2407
ILT		 8804 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8805 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8806 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8807 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8808 {
8809 if (!GOT_symbol)
8810 {
8811 if (symbol_find (name))
8812 as_bad (_("GOT already in symbol table"));
8813 GOT_symbol = symbol_new (name, undefined_section,
8814 (valueT) 0, &zero_address_frag);
8815 };
8816 return GOT_symbol;
8817 }
252b5132
RH		 8818 return 0;
8819}
8820
8821/* Round up a section size to the appropriate boundary. */
47926f60 8822
252b5132 8823valueT
7016a5d5 8824md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 8825{
4c63da97
AM		 8826#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8827 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8828 {
8829 /* For a.out, force the section size to be aligned. If we don't do
8830 this, BFD will align it for us, but it will not write out the
8831 final bytes of the section. This may be a bug in BFD, but it is
8832 easier to fix it here since that is how the other a.out targets
8833 work. */
8834 int align;
8835
8836 align = bfd_get_section_alignment (stdoutput, segment);
8837 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8838 }
252b5132
RH		 8839#endif
8840
8841 return size;
8842}
8843
8844/* On the i386, PC-relative offsets are relative to the start of the
8845 next instruction. That is, the address of the offset, plus its
8846 size, since the offset is always the last part of the insn. */
8847
8848long
e3bb37b5 8849md_pcrel_from (fixS *fixP)
252b5132
RH		 8850{
8851 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8852}
8853
8854#ifndef I386COFF
8855
8856static void
e3bb37b5 8857s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8858{
29b0f896 8859 int temp;
252b5132 8860
8a75718c
JB		 8861#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8862 if (IS_ELF)
8863 obj_elf_section_change_hook ();
8864#endif
252b5132
RH		 8865 temp = get_absolute_expression ();
8866 subseg_set (bss_section, (subsegT) temp);
8867 demand_empty_rest_of_line ();
8868}
8869
8870#endif
8871
252b5132 8872void
e3bb37b5 8873i386_validate_fix (fixS *fixp)
252b5132
RH		 8874{
8875 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8876 {
23df1078
JH		 8877 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8878 {
4fa24527 8879 if (!object_64bit)
23df1078
JH		 8880 abort ();
8881 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8882 }
8883 else
8884 {
4fa24527 8885 if (!object_64bit)
d6ab8113
JB		 8886 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8887 else
8888 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8889 }
252b5132
RH		 8890 fixp->fx_subsy = 0;
8891 }
8892}
8893
252b5132 8894arelent *
7016a5d5 8895tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 8896{
8897 arelent *rel;
8898 bfd_reloc_code_real_type code;
8899
8900 switch (fixp->fx_r_type)
8901 {
3e73aa7c
JH		 8902 case BFD_RELOC_X86_64_PLT32:
8903 case BFD_RELOC_X86_64_GOT32:
8904 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8905 case BFD_RELOC_386_PLT32:
8906 case BFD_RELOC_386_GOT32:
8907 case BFD_RELOC_386_GOTOFF:
8908 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8909 case BFD_RELOC_386_TLS_GD:
8910 case BFD_RELOC_386_TLS_LDM:
8911 case BFD_RELOC_386_TLS_LDO_32:
8912 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8913 case BFD_RELOC_386_TLS_IE:
8914 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8915 case BFD_RELOC_386_TLS_LE_32:
8916 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8917 case BFD_RELOC_386_TLS_GOTDESC:
8918 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8919 case BFD_RELOC_X86_64_TLSGD:
8920 case BFD_RELOC_X86_64_TLSLD:
8921 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8922 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8923 case BFD_RELOC_X86_64_GOTTPOFF:
8924 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8925 case BFD_RELOC_X86_64_TPOFF64:
8926 case BFD_RELOC_X86_64_GOTOFF64:
8927 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8928 case BFD_RELOC_X86_64_GOT64:
8929 case BFD_RELOC_X86_64_GOTPCREL64:
8930 case BFD_RELOC_X86_64_GOTPC64:
8931 case BFD_RELOC_X86_64_GOTPLT64:
8932 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8933 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8934 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8935 case BFD_RELOC_RVA:
8936 case BFD_RELOC_VTABLE_ENTRY:
8937 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8938#ifdef TE_PE
8939 case BFD_RELOC_32_SECREL:
8940#endif
252b5132
RH		 8941 code = fixp->fx_r_type;
8942 break;
dbbaec26
L		 8943 case BFD_RELOC_X86_64_32S:
8944 if (!fixp->fx_pcrel)
8945 {
8946 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8947 code = fixp->fx_r_type;
8948 break;
8949 }
252b5132 8950 default:
93382f6d 8951 if (fixp->fx_pcrel)
252b5132 8952 {
93382f6d
AM		 8953 switch (fixp->fx_size)
8954 {
8955 default:
b091f402
AM		 8956 as_bad_where (fixp->fx_file, fixp->fx_line,
8957 _("can not do %d byte pc-relative relocation"),
8958 fixp->fx_size);
93382f6d
AM		 8959 code = BFD_RELOC_32_PCREL;
8960 break;
8961 case 1: code = BFD_RELOC_8_PCREL; break;
8962 case 2: code = BFD_RELOC_16_PCREL; break;
8963 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8964#ifdef BFD64
8965 case 8: code = BFD_RELOC_64_PCREL; break;
8966#endif
93382f6d
AM		 8967 }
8968 }
8969 else
8970 {
8971 switch (fixp->fx_size)
8972 {
8973 default:
b091f402
AM		 8974 as_bad_where (fixp->fx_file, fixp->fx_line,
8975 _("can not do %d byte relocation"),
8976 fixp->fx_size);
93382f6d
AM		 8977 code = BFD_RELOC_32;
8978 break;
8979 case 1: code = BFD_RELOC_8; break;
8980 case 2: code = BFD_RELOC_16; break;
8981 case 4: code = BFD_RELOC_32; break;
937149dd 8982#ifdef BFD64
3e73aa7c 8983 case 8: code = BFD_RELOC_64; break;
937149dd 8984#endif
93382f6d 8985 }
252b5132
RH		 8986 }
8987 break;
8988 }
252b5132 8989
d182319b
JB		 8990 if ((code == BFD_RELOC_32
8991 || code == BFD_RELOC_32_PCREL
8992 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8993 && GOT_symbol
8994 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8995 {
4fa24527 8996 if (!object_64bit)
d6ab8113
JB		 8997 code = BFD_RELOC_386_GOTPC;
8998 else
8999 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 9000 }
7b81dfbb
AJ		 9001 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
9002 && GOT_symbol
9003 && fixp->fx_addsy == GOT_symbol)
9004 {
9005 code = BFD_RELOC_X86_64_GOTPC64;
9006 }
252b5132
RH		 9007
9008 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 9009 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
9010 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 9011
9012 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 9013
3e73aa7c
JH		 9014 if (!use_rela_relocations)
9015 {
9016 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
9017 vtable entry to be used in the relocation's section offset. */
9018 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
9019 rel->address = fixp->fx_offset;
fbeb56a4
DK		 9020#if defined (OBJ_COFF) && defined (TE_PE)
9021 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
9022 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
9023 else
9024#endif
c6682705 9025 rel->addend = 0;
3e73aa7c
JH		 9026 }
9027 /* Use the rela in 64bit mode. */
252b5132 9028 else
3e73aa7c 9029 {
862be3fb
L		 9030 if (disallow_64bit_reloc)
9031 switch (code)
9032 {
9033 case BFD_RELOC_64:
9034 case BFD_RELOC_X86_64_DTPOFF64:
9035 case BFD_RELOC_X86_64_TPOFF64:
9036 case BFD_RELOC_64_PCREL:
9037 case BFD_RELOC_X86_64_GOTOFF64:
9038 case BFD_RELOC_X86_64_GOT64:
9039 case BFD_RELOC_X86_64_GOTPCREL64:
9040 case BFD_RELOC_X86_64_GOTPC64:
9041 case BFD_RELOC_X86_64_GOTPLT64:
9042 case BFD_RELOC_X86_64_PLTOFF64:
9043 as_bad_where (fixp->fx_file, fixp->fx_line,
9044 _("cannot represent relocation type %s in x32 mode"),
9045 bfd_get_reloc_code_name (code));
9046 break;
9047 default:
9048 break;
9049 }
9050
062cd5e7
AS		 9051 if (!fixp->fx_pcrel)
9052 rel->addend = fixp->fx_offset;
9053 else
9054 switch (code)
9055 {
9056 case BFD_RELOC_X86_64_PLT32:
9057 case BFD_RELOC_X86_64_GOT32:
9058 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 9059 case BFD_RELOC_X86_64_TLSGD:
9060 case BFD_RELOC_X86_64_TLSLD:
9061 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 9062 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9063 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 9064 rel->addend = fixp->fx_offset - fixp->fx_size;
9065 break;
9066 default:
9067 rel->addend = (section->vma
9068 - fixp->fx_size
9069 + fixp->fx_addnumber
9070 + md_pcrel_from (fixp));
9071 break;
9072 }
3e73aa7c
JH		 9073 }
9074
252b5132
RH		 9075 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
9076 if (rel->howto == NULL)
9077 {
9078 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 9079 _("cannot represent relocation type %s"),
252b5132
RH		 9080 bfd_get_reloc_code_name (code));
9081 /* Set howto to a garbage value so that we can keep going. */
9082 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 9083 gas_assert (rel->howto != NULL);
252b5132
RH		 9084 }
9085
9086 return rel;
9087}
9088
ee86248c 9089#include "tc-i386-intel.c"
54cfded0 9090
a60de03c
JB		 9091void
9092tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 9093{
a60de03c
JB		 9094 int saved_naked_reg;
9095 char saved_register_dot;
54cfded0 9096
a60de03c
JB		 9097 saved_naked_reg = allow_naked_reg;
9098 allow_naked_reg = 1;
9099 saved_register_dot = register_chars['.'];
9100 register_chars['.'] = '.';
9101 allow_pseudo_reg = 1;
9102 expression_and_evaluate (exp);
9103 allow_pseudo_reg = 0;
9104 register_chars['.'] = saved_register_dot;
9105 allow_naked_reg = saved_naked_reg;
9106
e96d56a1 9107 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 9108 {
a60de03c
JB		 9109 if ((addressT) exp->X_add_number < i386_regtab_size)
9110 {
9111 exp->X_op = O_constant;
9112 exp->X_add_number = i386_regtab[exp->X_add_number]
9113 .dw2_regnum[flag_code >> 1];
9114 }
9115 else
9116 exp->X_op = O_illegal;
54cfded0 9117 }
54cfded0
AM		 9118}
9119
9120void
9121tc_x86_frame_initial_instructions (void)
9122{
a60de03c
JB		 9123 static unsigned int sp_regno[2];
9124
9125 if (!sp_regno[flag_code >> 1])
9126 {
9127 char *saved_input = input_line_pointer;
9128 char sp[][4] = {"esp", "rsp"};
9129 expressionS exp;
a4447b93 9130
a60de03c
JB		 9131 input_line_pointer = sp[flag_code >> 1];
9132 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 9133 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 9134 sp_regno[flag_code >> 1] = exp.X_add_number;
9135 input_line_pointer = saved_input;
9136 }
a4447b93 9137
61ff971f
L		 9138 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
9139 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 9140}
d2b2c203
DJ		 9141
9142int
9143i386_elf_section_type (const char *str, size_t len)
9144{
9145 if (flag_code == CODE_64BIT
9146 && len == sizeof ("unwind") - 1
9147 && strncmp (str, "unwind", 6) == 0)
9148 return SHT_X86_64_UNWIND;
9149
9150 return -1;
9151}
bb41ade5 9152
ad5fec3b
EB		 9153#ifdef TE_SOLARIS
9154void
9155i386_solaris_fix_up_eh_frame (segT sec)
9156{
9157 if (flag_code == CODE_64BIT)
9158 elf_section_type (sec) = SHT_X86_64_UNWIND;
9159}
9160#endif
9161
bb41ade5
AM		 9162#ifdef TE_PE
9163void
9164tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
9165{
91d6fa6a 9166 expressionS exp;
bb41ade5 9167
91d6fa6a
NC		 9168 exp.X_op = O_secrel;
9169 exp.X_add_symbol = symbol;
9170 exp.X_add_number = 0;
9171 emit_expr (&exp, size);
bb41ade5
AM		 9172}
9173#endif
3b22753a
L		 9174
9175#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9176/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9177
01e1a5bc 9178bfd_vma
3b22753a
L		 9179x86_64_section_letter (int letter, char **ptr_msg)
9180{
9181 if (flag_code == CODE_64BIT)
9182 {
9183 if (letter == 'l')
9184 return SHF_X86_64_LARGE;
9185
8f3bae45 9186 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 9187 }
3b22753a 9188 else
8f3bae45 9189 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 9190 return -1;
9191}
9192
01e1a5bc 9193bfd_vma
3b22753a
L		 9194x86_64_section_word (char *str, size_t len)
9195{
8620418b 9196 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 9197 return SHF_X86_64_LARGE;
9198
9199 return -1;
9200}
9201
9202static void
9203handle_large_common (int small ATTRIBUTE_UNUSED)
9204{
9205 if (flag_code != CODE_64BIT)
9206 {
9207 s_comm_internal (0, elf_common_parse);
9208 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9209 }
9210 else
9211 {
9212 static segT lbss_section;
9213 asection *saved_com_section_ptr = elf_com_section_ptr;
9214 asection *saved_bss_section = bss_section;
9215
9216 if (lbss_section == NULL)
9217 {
9218 flagword applicable;
9219 segT seg = now_seg;
9220 subsegT subseg = now_subseg;
9221
9222 /* The .lbss section is for local .largecomm symbols. */
9223 lbss_section = subseg_new (".lbss", 0);
9224 applicable = bfd_applicable_section_flags (stdoutput);
9225 bfd_set_section_flags (stdoutput, lbss_section,
9226 applicable & SEC_ALLOC);
9227 seg_info (lbss_section)->bss = 1;
9228
9229 subseg_set (seg, subseg);
9230 }
9231
9232 elf_com_section_ptr = &_bfd_elf_large_com_section;
9233 bss_section = lbss_section;
9234
9235 s_comm_internal (0, elf_common_parse);
9236
9237 elf_com_section_ptr = saved_com_section_ptr;
9238 bss_section = saved_bss_section;
9239 }
9240}
314a59d5
L		 9241
9242static void
9243handle_quad (int nbytes)
9244{
9245 expressionS exp;
9246
9247 if (x86_elf_abi != X86_64_X32_ABI)
9248 {
9249 cons (nbytes);
9250 return;
9251 }
9252
9253 if (is_it_end_of_statement ())
9254 {
9255 demand_empty_rest_of_line ();
9256 return;
9257 }
9258
9259 do
9260 {
9261 if (*input_line_pointer == '"')
9262 {
9263 as_bad (_("unexpected `\"' in expression"));
9264 ignore_rest_of_line ();
9265 return;
9266 }
9267 x86_cons (&exp, nbytes);
9268 /* Output 4 bytes if not constant. */
9269 if (exp.X_op != O_constant)
9270 nbytes = 4;
9271 emit_expr (&exp, (unsigned int) nbytes);
75c1c785
L		 9272 /* Zero-extends to 8 bytes if not constant. */
9273 if (nbytes == 4)
9274 {
9275 memset (&exp, '\0', sizeof (exp));
9276 exp.X_op = O_constant;
9277 emit_expr (&exp, nbytes);
9278 }
9279 nbytes = 8;
314a59d5
L		 9280 }
9281 while (*input_line_pointer++ == ',');
9282
9283 input_line_pointer--; /* Put terminator back into stream. */
9284
9285 demand_empty_rest_of_line ();
314a59d5 9286}
3b22753a 9287#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
This page took 1.389687 seconds and 4 git commands to generate.