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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
5db1645b 3 2000, 2001, 2002
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
47926f60
KH		 26 Bugs & suggestions are completely welcome. This is free software.
27 Please help us make it better. */
252b5132 28
252b5132 29#include "as.h"
3882b010 30#include "safe-ctype.h"
252b5132 31#include "subsegs.h"
316e2c05 32#include "dwarf2dbg.h"
252b5132
RH		 33#include "opcode/i386.h"
34
252b5132
RH		 35#ifndef REGISTER_WARNINGS
36#define REGISTER_WARNINGS 1
37#endif
38
c3332e24 39#ifndef INFER_ADDR_PREFIX
eecb386c 40#define INFER_ADDR_PREFIX 1
c3332e24
AM		 41#endif
42
252b5132
RH		 43#ifndef SCALE1_WHEN_NO_INDEX
44/* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48#define SCALE1_WHEN_NO_INDEX 1
49#endif
50
29b0f896
AM		 51#ifdef BFD_ASSEMBLER
52#define RELOC_ENUM enum bfd_reloc_code_real
53#else
54#define RELOC_ENUM int
246fcdee 55#endif
29b0f896
AM		 56
57#ifndef DEFAULT_ARCH
58#define DEFAULT_ARCH "i386"
246fcdee 59#endif
252b5132 60
edde18a5
AM		 61#ifndef INLINE
62#if __GNUC__ >= 2
63#define INLINE __inline__
64#else
65#define INLINE
66#endif
67#endif
68
29b0f896
AM		 69static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
70static INLINE int fits_in_signed_byte PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
72static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
73static INLINE int fits_in_signed_word PARAMS ((offsetT));
74static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
75static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 76static int smallest_imm_type PARAMS ((offsetT));
77static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 78static int add_prefix PARAMS ((unsigned int));
3e73aa7c 79static void set_code_flag PARAMS ((int));
47926f60 80static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 81static void set_intel_syntax PARAMS ((int));
e413e4e9 82static void set_cpu_arch PARAMS ((int));
29b0f896
AM		 83static char *output_invalid PARAMS ((int c));
84static int i386_operand PARAMS ((char *operand_string));
85static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
86static const reg_entry *parse_register PARAMS ((char *reg_string,
87 char **end_op));
88static char *parse_insn PARAMS ((char *, char *));
89static char *parse_operands PARAMS ((char *, const char *));
90static void swap_operands PARAMS ((void));
91static void optimize_imm PARAMS ((void));
92static void optimize_disp PARAMS ((void));
93static int match_template PARAMS ((void));
94static int check_string PARAMS ((void));
95static int process_suffix PARAMS ((void));
96static int check_byte_reg PARAMS ((void));
97static int check_long_reg PARAMS ((void));
98static int check_qword_reg PARAMS ((void));
99static int check_word_reg PARAMS ((void));
100static int finalize_imm PARAMS ((void));
101static int process_operands PARAMS ((void));
102static const seg_entry *build_modrm_byte PARAMS ((void));
103static void output_insn PARAMS ((void));
104static void output_branch PARAMS ((void));
105static void output_jump PARAMS ((void));
106static void output_interseg_jump PARAMS ((void));
2bbd9c25
JJ		 107static void output_imm PARAMS ((fragS *insn_start_frag,
108 offsetT insn_start_off));
109static void output_disp PARAMS ((fragS *insn_start_frag,
110 offsetT insn_start_off));
29b0f896
AM		 111#ifndef I386COFF
112static void s_bss PARAMS ((int));
252b5132
RH		 113#endif
114
a847613f 115static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 116
252b5132 117/* 'md_assemble ()' gathers together information and puts it into a
47926f60 118 i386_insn. */
252b5132 119
520dc8e8
AM		 120union i386_op
121 {
122 expressionS *disps;
123 expressionS *imms;
124 const reg_entry *regs;
125 };
126
252b5132
RH		 127struct _i386_insn
128 {
47926f60 129 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 130 template tm;
131
132 /* SUFFIX holds the instruction mnemonic suffix if given.
133 (e.g. 'l' for 'movl') */
134 char suffix;
135
47926f60 136 /* OPERANDS gives the number of given operands. */
252b5132
RH		 137 unsigned int operands;
138
139 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
140 of given register, displacement, memory operands and immediate
47926f60 141 operands. */
252b5132
RH		 142 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
143
144 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 145 use OP[i] for the corresponding operand. */
252b5132
RH		 146 unsigned int types[MAX_OPERANDS];
147
520dc8e8
AM		 148 /* Displacement expression, immediate expression, or register for each
149 operand. */
150 union i386_op op[MAX_OPERANDS];
252b5132 151
3e73aa7c
JH		 152 /* Flags for operands. */
153 unsigned int flags[MAX_OPERANDS];
154#define Operand_PCrel 1
155
252b5132 156 /* Relocation type for operand */
f3c180ae 157 RELOC_ENUM reloc[MAX_OPERANDS];
252b5132 158
252b5132
RH		 159 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
160 the base index byte below. */
161 const reg_entry *base_reg;
162 const reg_entry *index_reg;
163 unsigned int log2_scale_factor;
164
165 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 166 explicit segment overrides are given. */
ce8a8b2f 167 const seg_entry *seg[2];
252b5132
RH		 168
169 /* PREFIX holds all the given prefix opcodes (usually null).
170 PREFIXES is the number of prefix opcodes. */
171 unsigned int prefixes;
172 unsigned char prefix[MAX_PREFIXES];
173
174 /* RM and SIB are the modrm byte and the sib byte where the
175 addressing modes of this insn are encoded. */
176
177 modrm_byte rm;
3e73aa7c 178 rex_byte rex;
252b5132
RH		 179 sib_byte sib;
180 };
181
182typedef struct _i386_insn i386_insn;
183
184/* List of chars besides those in app.c:symbol_chars that can start an
185 operand. Used to prevent the scrubber eating vital white-space. */
186#ifdef LEX_AT
200dbde8 187const char extra_symbol_chars[] = "*%-(@[";
252b5132 188#else
200dbde8 189const char extra_symbol_chars[] = "*%-([";
252b5132
RH		 190#endif
191
29b0f896
AM		 192#if (defined (TE_I386AIX) \
193 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
194 && !defined (TE_LINUX) \
195 && !defined (TE_FreeBSD) \
196 && !defined (TE_NetBSD)))
252b5132 197/* This array holds the chars that always start a comment. If the
ce8a8b2f 198 pre-processor is disabled, these aren't very useful. */
252b5132
RH		 199const char comment_chars[] = "#/";
200#define PREFIX_SEPARATOR '\\'
252b5132
RH		 201
202/* This array holds the chars that only start a comment at the beginning of
203 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 204 .line and .file directives will appear in the pre-processed output.
205 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 206 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 207 #NO_APP at the beginning of its output.
208 Also note that comments started like this one will always work if
252b5132 209 '/' isn't otherwise defined. */
252b5132 210const char line_comment_chars[] = "";
29b0f896 211
252b5132 212#else
29b0f896
AM		 213/* Putting '/' here makes it impossible to use the divide operator.
214 However, we need it for compatibility with SVR4 systems. */
215const char comment_chars[] = "#";
216#define PREFIX_SEPARATOR '/'
217
252b5132
RH		 218const char line_comment_chars[] = "/";
219#endif
220
63a0b638 221const char line_separator_chars[] = ";";
252b5132 222
ce8a8b2f
AM		 223/* Chars that can be used to separate mant from exp in floating point
224 nums. */
252b5132
RH		 225const char EXP_CHARS[] = "eE";
226
ce8a8b2f
AM		 227/* Chars that mean this number is a floating point constant
228 As in 0f12.456
229 or 0d1.2345e12. */
252b5132
RH		 230const char FLT_CHARS[] = "fFdDxX";
231
ce8a8b2f 232/* Tables for lexical analysis. */
252b5132
RH		 233static char mnemonic_chars[256];
234static char register_chars[256];
235static char operand_chars[256];
236static char identifier_chars[256];
237static char digit_chars[256];
238
ce8a8b2f 239/* Lexical macros. */
252b5132
RH		 240#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
241#define is_operand_char(x) (operand_chars[(unsigned char) x])
242#define is_register_char(x) (register_chars[(unsigned char) x])
243#define is_space_char(x) ((x) == ' ')
244#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
245#define is_digit_char(x) (digit_chars[(unsigned char) x])
246
ce8a8b2f 247/* All non-digit non-letter charcters that may occur in an operand. */
252b5132
RH		 248static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
249
250/* md_assemble() always leaves the strings it's passed unaltered. To
251 effect this we maintain a stack of saved characters that we've smashed
252 with '\0's (indicating end of strings for various sub-fields of the
47926f60 253 assembler instruction). */
252b5132 254static char save_stack[32];
ce8a8b2f 255static char *save_stack_p;
252b5132
RH		 256#define END_STRING_AND_SAVE(s) \
257 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
258#define RESTORE_END_STRING(s) \
259 do { *(s) = *--save_stack_p; } while (0)
260
47926f60 261/* The instruction we're assembling. */
252b5132
RH		 262static i386_insn i;
263
264/* Possible templates for current insn. */
265static const templates *current_templates;
266
47926f60 267/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 268static expressionS disp_expressions[2], im_expressions[2];
269
47926f60
KH		 270/* Current operand we are working on. */
271static int this_operand;
252b5132 272
3e73aa7c
JH		 273/* We support four different modes. FLAG_CODE variable is used to distinguish
274 these. */
275
276enum flag_code {
277 CODE_32BIT,
278 CODE_16BIT,
279 CODE_64BIT };
f3c180ae 280#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 281
282static enum flag_code flag_code;
283static int use_rela_relocations = 0;
284
285/* The names used to print error messages. */
b77a7acd 286static const char *flag_code_names[] =
3e73aa7c
JH		 287 {
288 "32",
289 "16",
290 "64"
291 };
252b5132 292
47926f60
KH		 293/* 1 for intel syntax,
294 0 if att syntax. */
295static int intel_syntax = 0;
252b5132 296
47926f60
KH		 297/* 1 if register prefix % not required. */
298static int allow_naked_reg = 0;
252b5132 299
47926f60
KH		 300/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
301 leave, push, and pop instructions so that gcc has the same stack
302 frame as in 32 bit mode. */
303static char stackop_size = '\0';
eecb386c 304
47926f60
KH		 305/* Non-zero to quieten some warnings. */
306static int quiet_warnings = 0;
a38cf1db 307
47926f60
KH		 308/* CPU name. */
309static const char *cpu_arch_name = NULL;
a38cf1db 310
47926f60 311/* CPU feature flags. */
29b0f896 312static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 313
fddf5b5b
AM		 314/* If set, conditional jumps are not automatically promoted to handle
315 larger than a byte offset. */
316static unsigned int no_cond_jump_promotion = 0;
317
29b0f896
AM		 318/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
319symbolS *GOT_symbol;
320
252b5132 321/* Interface to relax_segment.
fddf5b5b
AM		 322 There are 3 major relax states for 386 jump insns because the
323 different types of jumps add different sizes to frags when we're
324 figuring out what sort of jump to choose to reach a given label. */
252b5132 325
47926f60 326/* Types. */
93c2a809
AM		 327#define UNCOND_JUMP 0
328#define COND_JUMP 1
329#define COND_JUMP86 2
fddf5b5b 330
47926f60 331/* Sizes. */
252b5132
RH		 332#define CODE16 1
333#define SMALL 0
29b0f896 334#define SMALL16 (SMALL | CODE16)
252b5132 335#define BIG 2
29b0f896 336#define BIG16 (BIG | CODE16)
252b5132
RH		 337
338#ifndef INLINE
339#ifdef __GNUC__
340#define INLINE __inline__
341#else
342#define INLINE
343#endif
344#endif
345
fddf5b5b
AM		 346#define ENCODE_RELAX_STATE(type, size) \
347 ((relax_substateT) (((type) << 2) | (size)))
348#define TYPE_FROM_RELAX_STATE(s) \
349 ((s) >> 2)
350#define DISP_SIZE_FROM_RELAX_STATE(s) \
351 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 352
353/* This table is used by relax_frag to promote short jumps to long
354 ones where necessary. SMALL (short) jumps may be promoted to BIG
355 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
356 don't allow a short jump in a 32 bit code segment to be promoted to
357 a 16 bit offset jump because it's slower (requires data size
358 prefix), and doesn't work, unless the destination is in the bottom
359 64k of the code segment (The top 16 bits of eip are zeroed). */
360
361const relax_typeS md_relax_table[] =
362{
24eab124
AM		 363 /* The fields are:
364 1) most positive reach of this state,
365 2) most negative reach of this state,
93c2a809 366 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 367 4) which index into the table to try if we can't fit into this one. */
252b5132 368
fddf5b5b 369 /* UNCOND_JUMP states. */
93c2a809
AM		 370 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
371 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
372 /* dword jmp adds 4 bytes to frag:
373 0 extra opcode bytes, 4 displacement bytes. */
252b5132 374 {0, 0, 4, 0},
93c2a809
AM		 375 /* word jmp adds 2 byte2 to frag:
376 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 377 {0, 0, 2, 0},
378
93c2a809
AM		 379 /* COND_JUMP states. */
380 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
381 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
382 /* dword conditionals adds 5 bytes to frag:
383 1 extra opcode byte, 4 displacement bytes. */
384 {0, 0, 5, 0},
fddf5b5b 385 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 386 1 extra opcode byte, 2 displacement bytes. */
387 {0, 0, 3, 0},
388
389 /* COND_JUMP86 states. */
390 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
391 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
392 /* dword conditionals adds 5 bytes to frag:
393 1 extra opcode byte, 4 displacement bytes. */
394 {0, 0, 5, 0},
395 /* word conditionals add 4 bytes to frag:
396 1 displacement byte and a 3 byte long branch insn. */
397 {0, 0, 4, 0}
252b5132
RH		 398};
399
e413e4e9
AM		 400static const arch_entry cpu_arch[] = {
401 {"i8086", Cpu086 },
402 {"i186", Cpu086|Cpu186 },
403 {"i286", Cpu086|Cpu186|Cpu286 },
404 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
405 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
406 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
407 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
408 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
409 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
a167610d 410 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 },
3e73aa7c
JH		 411 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
412 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow },
a167610d 413 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 },
e413e4e9
AM		 414 {NULL, 0 }
415};
416
29b0f896
AM		 417const pseudo_typeS md_pseudo_table[] =
418{
419#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
420 {"align", s_align_bytes, 0},
421#else
422 {"align", s_align_ptwo, 0},
423#endif
424 {"arch", set_cpu_arch, 0},
425#ifndef I386COFF
426 {"bss", s_bss, 0},
427#endif
428 {"ffloat", float_cons, 'f'},
429 {"dfloat", float_cons, 'd'},
430 {"tfloat", float_cons, 'x'},
431 {"value", cons, 2},
432 {"noopt", s_ignore, 0},
433 {"optim", s_ignore, 0},
434 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
435 {"code16", set_code_flag, CODE_16BIT},
436 {"code32", set_code_flag, CODE_32BIT},
437 {"code64", set_code_flag, CODE_64BIT},
438 {"intel_syntax", set_intel_syntax, 1},
439 {"att_syntax", set_intel_syntax, 0},
c6682705 440 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
29b0f896
AM		 441 {"loc", dwarf2_directive_loc, 0},
442 {0, 0, 0}
443};
444
445/* For interface with expression (). */
446extern char *input_line_pointer;
447
448/* Hash table for instruction mnemonic lookup. */
449static struct hash_control *op_hash;
450
451/* Hash table for register lookup. */
452static struct hash_control *reg_hash;
453\f
252b5132
RH		 454void
455i386_align_code (fragP, count)
456 fragS *fragP;
457 int count;
458{
ce8a8b2f
AM		 459 /* Various efficient no-op patterns for aligning code labels.
460 Note: Don't try to assemble the instructions in the comments.
461 0L and 0w are not legal. */
252b5132
RH		 462 static const char f32_1[] =
463 {0x90}; /* nop */
464 static const char f32_2[] =
465 {0x89,0xf6}; /* movl %esi,%esi */
466 static const char f32_3[] =
467 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
468 static const char f32_4[] =
469 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
470 static const char f32_5[] =
471 {0x90, /* nop */
472 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
473 static const char f32_6[] =
474 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
475 static const char f32_7[] =
476 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
477 static const char f32_8[] =
478 {0x90, /* nop */
479 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
480 static const char f32_9[] =
481 {0x89,0xf6, /* movl %esi,%esi */
482 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
483 static const char f32_10[] =
484 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
485 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
486 static const char f32_11[] =
487 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
488 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
489 static const char f32_12[] =
490 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
491 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
492 static const char f32_13[] =
493 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
494 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
495 static const char f32_14[] =
496 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
497 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
498 static const char f32_15[] =
499 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
500 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 501 static const char f16_3[] =
502 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 503 static const char f16_4[] =
504 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
505 static const char f16_5[] =
506 {0x90, /* nop */
507 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
508 static const char f16_6[] =
509 {0x89,0xf6, /* mov %si,%si */
510 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
511 static const char f16_7[] =
512 {0x8d,0x74,0x00, /* lea 0(%si),%si */
513 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
514 static const char f16_8[] =
515 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
516 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
517 static const char *const f32_patt[] = {
518 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
519 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
520 };
521 static const char *const f16_patt[] = {
c3332e24 522 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 523 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
524 };
525
33fef721
JH		 526 if (count <= 0 || count > 15)
527 return;
3e73aa7c 528
33fef721
JH		 529 /* The recommended way to pad 64bit code is to use NOPs preceded by
530 maximally four 0x66 prefixes. Balance the size of nops. */
531 if (flag_code == CODE_64BIT)
252b5132 532 {
33fef721
JH		 533 int i;
534 int nnops = (count + 3) / 4;
535 int len = count / nnops;
536 int remains = count - nnops * len;
537 int pos = 0;
538
539 for (i = 0; i < remains; i++)
252b5132 540 {
33fef721
JH		 541 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
542 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
543 pos += len + 1;
544 }
545 for (; i < nnops; i++)
546 {
547 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
548 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
549 pos += len;
252b5132 550 }
252b5132 551 }
33fef721
JH		 552 else
553 if (flag_code == CODE_16BIT)
554 {
555 memcpy (fragP->fr_literal + fragP->fr_fix,
556 f16_patt[count - 1], count);
557 if (count > 8)
558 /* Adjust jump offset. */
559 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
560 }
561 else
562 memcpy (fragP->fr_literal + fragP->fr_fix,
563 f32_patt[count - 1], count);
564 fragP->fr_var = count;
252b5132
RH		 565}
566
252b5132
RH		 567static INLINE unsigned int
568mode_from_disp_size (t)
569 unsigned int t;
570{
3e73aa7c 571 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 572}
573
574static INLINE int
575fits_in_signed_byte (num)
847f7ad4 576 offsetT num;
252b5132
RH		 577{
578 return (num >= -128) && (num <= 127);
47926f60 579}
252b5132
RH		 580
581static INLINE int
582fits_in_unsigned_byte (num)
847f7ad4 583 offsetT num;
252b5132
RH		 584{
585 return (num & 0xff) == num;
47926f60 586}
252b5132
RH		 587
588static INLINE int
589fits_in_unsigned_word (num)
847f7ad4 590 offsetT num;
252b5132
RH		 591{
592 return (num & 0xffff) == num;
47926f60 593}
252b5132
RH		 594
595static INLINE int
596fits_in_signed_word (num)
847f7ad4 597 offsetT num;
252b5132
RH		 598{
599 return (-32768 <= num) && (num <= 32767);
47926f60 600}
3e73aa7c
JH		 601static INLINE int
602fits_in_signed_long (num)
603 offsetT num ATTRIBUTE_UNUSED;
604{
605#ifndef BFD64
606 return 1;
607#else
608 return (!(((offsetT) -1 << 31) & num)
609 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
610#endif
611} /* fits_in_signed_long() */
612static INLINE int
613fits_in_unsigned_long (num)
614 offsetT num ATTRIBUTE_UNUSED;
615{
616#ifndef BFD64
617 return 1;
618#else
619 return (num & (((offsetT) 2 << 31) - 1)) == num;
620#endif
621} /* fits_in_unsigned_long() */
252b5132
RH		 622
623static int
624smallest_imm_type (num)
847f7ad4 625 offsetT num;
252b5132 626{
a847613f 627 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 628 {
629 /* This code is disabled on the 486 because all the Imm1 forms
630 in the opcode table are slower on the i486. They're the
631 versions with the implicitly specified single-position
632 displacement, which has another syntax if you really want to
633 use that form. */
634 if (num == 1)
3e73aa7c 635 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 636 }
252b5132 637 return (fits_in_signed_byte (num)
3e73aa7c 638 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 639 : fits_in_unsigned_byte (num)
3e73aa7c 640 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 641 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 642 ? (Imm16 | Imm32 | Imm32S | Imm64)
643 : fits_in_signed_long (num)
644 ? (Imm32 | Imm32S | Imm64)
645 : fits_in_unsigned_long (num)
646 ? (Imm32 | Imm64)
647 : Imm64);
47926f60 648}
252b5132 649
847f7ad4
AM		 650static offsetT
651offset_in_range (val, size)
652 offsetT val;
653 int size;
654{
508866be 655 addressT mask;
ba2adb93 656
847f7ad4
AM		 657 switch (size)
658 {
508866be
L		 659 case 1: mask = ((addressT) 1 << 8) - 1; break;
660 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 661 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 662#ifdef BFD64
663 case 8: mask = ((addressT) 2 << 63) - 1; break;
664#endif
47926f60 665 default: abort ();
847f7ad4
AM		 666 }
667
ba2adb93 668 /* If BFD64, sign extend val. */
3e73aa7c
JH		 669 if (!use_rela_relocations)
670 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
671 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 672
47926f60 673 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 674 {
675 char buf1[40], buf2[40];
676
677 sprint_value (buf1, val);
678 sprint_value (buf2, val & mask);
679 as_warn (_("%s shortened to %s"), buf1, buf2);
680 }
681 return val & mask;
682}
683
252b5132
RH		 684/* Returns 0 if attempting to add a prefix where one from the same
685 class already exists, 1 if non rep/repne added, 2 if rep/repne
686 added. */
687static int
688add_prefix (prefix)
689 unsigned int prefix;
690{
691 int ret = 1;
692 int q;
693
29b0f896
AM		 694 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
695 && flag_code == CODE_64BIT)
3e73aa7c
JH		 696 q = REX_PREFIX;
697 else
698 switch (prefix)
699 {
700 default:
701 abort ();
702
703 case CS_PREFIX_OPCODE:
704 case DS_PREFIX_OPCODE:
705 case ES_PREFIX_OPCODE:
706 case FS_PREFIX_OPCODE:
707 case GS_PREFIX_OPCODE:
708 case SS_PREFIX_OPCODE:
709 q = SEG_PREFIX;
710 break;
252b5132 711
3e73aa7c
JH		 712 case REPNE_PREFIX_OPCODE:
713 case REPE_PREFIX_OPCODE:
714 ret = 2;
715 /* fall thru */
716 case LOCK_PREFIX_OPCODE:
717 q = LOCKREP_PREFIX;
718 break;
252b5132 719
3e73aa7c
JH		 720 case FWAIT_OPCODE:
721 q = WAIT_PREFIX;
722 break;
252b5132 723
3e73aa7c
JH		 724 case ADDR_PREFIX_OPCODE:
725 q = ADDR_PREFIX;
726 break;
252b5132 727
3e73aa7c
JH		 728 case DATA_PREFIX_OPCODE:
729 q = DATA_PREFIX;
730 break;
731 }
252b5132 732
29b0f896 733 if (i.prefix[q] != 0)
252b5132
RH		 734 {
735 as_bad (_("same type of prefix used twice"));
736 return 0;
737 }
738
739 i.prefixes += 1;
740 i.prefix[q] = prefix;
741 return ret;
742}
743
744static void
3e73aa7c 745set_code_flag (value)
e5cb08ac 746 int value;
eecb386c 747{
3e73aa7c
JH		 748 flag_code = value;
749 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
750 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
751 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
752 {
753 as_bad (_("64bit mode not supported on this CPU."));
754 }
755 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
756 {
757 as_bad (_("32bit mode not supported on this CPU."));
758 }
eecb386c
AM		 759 stackop_size = '\0';
760}
761
762static void
3e73aa7c
JH		 763set_16bit_gcc_code_flag (new_code_flag)
764 int new_code_flag;
252b5132 765{
3e73aa7c
JH		 766 flag_code = new_code_flag;
767 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
768 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
769 stackop_size = 'l';
252b5132
RH		 770}
771
772static void
773set_intel_syntax (syntax_flag)
eecb386c 774 int syntax_flag;
252b5132
RH		 775{
776 /* Find out if register prefixing is specified. */
777 int ask_naked_reg = 0;
778
779 SKIP_WHITESPACE ();
29b0f896 780 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 781 {
782 char *string = input_line_pointer;
783 int e = get_symbol_end ();
784
47926f60 785 if (strcmp (string, "prefix") == 0)
252b5132 786 ask_naked_reg = 1;
47926f60 787 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 788 ask_naked_reg = -1;
789 else
d0b47220 790 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 791 *input_line_pointer = e;
792 }
793 demand_empty_rest_of_line ();
c3332e24 794
252b5132
RH		 795 intel_syntax = syntax_flag;
796
797 if (ask_naked_reg == 0)
798 {
799#ifdef BFD_ASSEMBLER
800 allow_naked_reg = (intel_syntax
24eab124 801 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132 802#else
47926f60
KH		 803 /* Conservative default. */
804 allow_naked_reg = 0;
252b5132
RH		 805#endif
806 }
807 else
808 allow_naked_reg = (ask_naked_reg < 0);
809}
810
e413e4e9
AM		 811static void
812set_cpu_arch (dummy)
47926f60 813 int dummy ATTRIBUTE_UNUSED;
e413e4e9 814{
47926f60 815 SKIP_WHITESPACE ();
e413e4e9 816
29b0f896 817 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 818 {
819 char *string = input_line_pointer;
820 int e = get_symbol_end ();
821 int i;
822
823 for (i = 0; cpu_arch[i].name; i++)
824 {
825 if (strcmp (string, cpu_arch[i].name) == 0)
826 {
827 cpu_arch_name = cpu_arch[i].name;
fddf5b5b
AM		 828 cpu_arch_flags = (cpu_arch[i].flags
829 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
e413e4e9
AM		 830 break;
831 }
832 }
833 if (!cpu_arch[i].name)
834 as_bad (_("no such architecture: `%s'"), string);
835
836 *input_line_pointer = e;
837 }
838 else
839 as_bad (_("missing cpu architecture"));
840
fddf5b5b
AM		 841 no_cond_jump_promotion = 0;
842 if (*input_line_pointer == ','
29b0f896 843 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 844 {
845 char *string = ++input_line_pointer;
846 int e = get_symbol_end ();
847
848 if (strcmp (string, "nojumps") == 0)
849 no_cond_jump_promotion = 1;
850 else if (strcmp (string, "jumps") == 0)
851 ;
852 else
853 as_bad (_("no such architecture modifier: `%s'"), string);
854
855 *input_line_pointer = e;
856 }
857
e413e4e9
AM		 858 demand_empty_rest_of_line ();
859}
860
b9d79e03
JH		 861#ifdef BFD_ASSEMBLER
862unsigned long
863i386_mach ()
864{
865 if (!strcmp (default_arch, "x86_64"))
866 return bfd_mach_x86_64;
867 else if (!strcmp (default_arch, "i386"))
868 return bfd_mach_i386_i386;
869 else
870 as_fatal (_("Unknown architecture"));
871}
872#endif
873\f
252b5132
RH		 874void
875md_begin ()
876{
877 const char *hash_err;
878
47926f60 879 /* Initialize op_hash hash table. */
252b5132
RH		 880 op_hash = hash_new ();
881
882 {
29b0f896
AM		 883 const template *optab;
884 templates *core_optab;
252b5132 885
47926f60
KH		 886 /* Setup for loop. */
887 optab = i386_optab;
252b5132
RH		 888 core_optab = (templates *) xmalloc (sizeof (templates));
889 core_optab->start = optab;
890
891 while (1)
892 {
893 ++optab;
894 if (optab->name == NULL
895 || strcmp (optab->name, (optab - 1)->name) != 0)
896 {
897 /* different name --> ship out current template list;
47926f60 898 add to hash table; & begin anew. */
252b5132
RH		 899 core_optab->end = optab;
900 hash_err = hash_insert (op_hash,
901 (optab - 1)->name,
902 (PTR) core_optab);
903 if (hash_err)
904 {
252b5132
RH		 905 as_fatal (_("Internal Error: Can't hash %s: %s"),
906 (optab - 1)->name,
907 hash_err);
908 }
909 if (optab->name == NULL)
910 break;
911 core_optab = (templates *) xmalloc (sizeof (templates));
912 core_optab->start = optab;
913 }
914 }
915 }
916
47926f60 917 /* Initialize reg_hash hash table. */
252b5132
RH		 918 reg_hash = hash_new ();
919 {
29b0f896 920 const reg_entry *regtab;
252b5132
RH		 921
922 for (regtab = i386_regtab;
923 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
924 regtab++)
925 {
926 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
927 if (hash_err)
3e73aa7c
JH		 928 as_fatal (_("Internal Error: Can't hash %s: %s"),
929 regtab->reg_name,
930 hash_err);
252b5132
RH		 931 }
932 }
933
47926f60 934 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 935 {
29b0f896
AM		 936 int c;
937 char *p;
252b5132
RH		 938
939 for (c = 0; c < 256; c++)
940 {
3882b010 941 if (ISDIGIT (c))
252b5132
RH		 942 {
943 digit_chars[c] = c;
944 mnemonic_chars[c] = c;
945 register_chars[c] = c;
946 operand_chars[c] = c;
947 }
3882b010 948 else if (ISLOWER (c))
252b5132
RH		 949 {
950 mnemonic_chars[c] = c;
951 register_chars[c] = c;
952 operand_chars[c] = c;
953 }
3882b010 954 else if (ISUPPER (c))
252b5132 955 {
3882b010 956 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 957 register_chars[c] = mnemonic_chars[c];
958 operand_chars[c] = c;
959 }
960
3882b010 961 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 962 identifier_chars[c] = c;
963 else if (c >= 128)
964 {
965 identifier_chars[c] = c;
966 operand_chars[c] = c;
967 }
968 }
969
970#ifdef LEX_AT
971 identifier_chars['@'] = '@';
972#endif
252b5132
RH		 973 digit_chars['-'] = '-';
974 identifier_chars['_'] = '_';
975 identifier_chars['.'] = '.';
976
977 for (p = operand_special_chars; *p != '\0'; p++)
978 operand_chars[(unsigned char) *p] = *p;
979 }
980
981#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
982 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
983 {
984 record_alignment (text_section, 2);
985 record_alignment (data_section, 2);
986 record_alignment (bss_section, 2);
987 }
988#endif
989}
990
991void
992i386_print_statistics (file)
993 FILE *file;
994{
995 hash_print_statistics (file, "i386 opcode", op_hash);
996 hash_print_statistics (file, "i386 register", reg_hash);
997}
998\f
252b5132
RH		 999#ifdef DEBUG386
1000
ce8a8b2f 1001/* Debugging routines for md_assemble. */
252b5132
RH		 1002static void pi PARAMS ((char *, i386_insn *));
1003static void pte PARAMS ((template *));
1004static void pt PARAMS ((unsigned int));
1005static void pe PARAMS ((expressionS *));
1006static void ps PARAMS ((symbolS *));
1007
1008static void
1009pi (line, x)
1010 char *line;
1011 i386_insn *x;
1012{
09f131f2 1013 unsigned int i;
252b5132
RH		 1014
1015 fprintf (stdout, "%s: template ", line);
1016 pte (&x->tm);
09f131f2
JH		 1017 fprintf (stdout, " address: base %s index %s scale %x\n",
1018 x->base_reg ? x->base_reg->reg_name : "none",
1019 x->index_reg ? x->index_reg->reg_name : "none",
1020 x->log2_scale_factor);
1021 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1022 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1023 fprintf (stdout, " sib: base %x index %x scale %x\n",
1024 x->sib.base, x->sib.index, x->sib.scale);
1025 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1026 (x->rex & REX_MODE64) != 0,
1027 (x->rex & REX_EXTX) != 0,
1028 (x->rex & REX_EXTY) != 0,
1029 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1030 for (i = 0; i < x->operands; i++)
1031 {
1032 fprintf (stdout, " #%d: ", i + 1);
1033 pt (x->types[i]);
1034 fprintf (stdout, "\n");
1035 if (x->types[i]
3f4438ab 1036 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1037 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1038 if (x->types[i] & Imm)
520dc8e8 1039 pe (x->op[i].imms);
252b5132 1040 if (x->types[i] & Disp)
520dc8e8 1041 pe (x->op[i].disps);
252b5132
RH		 1042 }
1043}
1044
1045static void
1046pte (t)
1047 template *t;
1048{
09f131f2 1049 unsigned int i;
252b5132 1050 fprintf (stdout, " %d operands ", t->operands);
47926f60 1051 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1052 if (t->extension_opcode != None)
1053 fprintf (stdout, "ext %x ", t->extension_opcode);
1054 if (t->opcode_modifier & D)
1055 fprintf (stdout, "D");
1056 if (t->opcode_modifier & W)
1057 fprintf (stdout, "W");
1058 fprintf (stdout, "\n");
1059 for (i = 0; i < t->operands; i++)
1060 {
1061 fprintf (stdout, " #%d type ", i + 1);
1062 pt (t->operand_types[i]);
1063 fprintf (stdout, "\n");
1064 }
1065}
1066
1067static void
1068pe (e)
1069 expressionS *e;
1070{
24eab124 1071 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1072 fprintf (stdout, " add_number %ld (%lx)\n",
1073 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1074 if (e->X_add_symbol)
1075 {
1076 fprintf (stdout, " add_symbol ");
1077 ps (e->X_add_symbol);
1078 fprintf (stdout, "\n");
1079 }
1080 if (e->X_op_symbol)
1081 {
1082 fprintf (stdout, " op_symbol ");
1083 ps (e->X_op_symbol);
1084 fprintf (stdout, "\n");
1085 }
1086}
1087
1088static void
1089ps (s)
1090 symbolS *s;
1091{
1092 fprintf (stdout, "%s type %s%s",
1093 S_GET_NAME (s),
1094 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1095 segment_name (S_GET_SEGMENT (s)));
1096}
1097
1098struct type_name
1099 {
1100 unsigned int mask;
1101 char *tname;
1102 }
1103
29b0f896 1104static const type_names[] =
252b5132
RH		 1105{
1106 { Reg8, "r8" },
1107 { Reg16, "r16" },
1108 { Reg32, "r32" },
09f131f2 1109 { Reg64, "r64" },
252b5132
RH		 1110 { Imm8, "i8" },
1111 { Imm8S, "i8s" },
1112 { Imm16, "i16" },
1113 { Imm32, "i32" },
09f131f2
JH		 1114 { Imm32S, "i32s" },
1115 { Imm64, "i64" },
252b5132
RH		 1116 { Imm1, "i1" },
1117 { BaseIndex, "BaseIndex" },
1118 { Disp8, "d8" },
1119 { Disp16, "d16" },
1120 { Disp32, "d32" },
09f131f2
JH		 1121 { Disp32S, "d32s" },
1122 { Disp64, "d64" },
252b5132
RH		 1123 { InOutPortReg, "InOutPortReg" },
1124 { ShiftCount, "ShiftCount" },
1125 { Control, "control reg" },
1126 { Test, "test reg" },
1127 { Debug, "debug reg" },
1128 { FloatReg, "FReg" },
1129 { FloatAcc, "FAcc" },
1130 { SReg2, "SReg2" },
1131 { SReg3, "SReg3" },
1132 { Acc, "Acc" },
1133 { JumpAbsolute, "Jump Absolute" },
1134 { RegMMX, "rMMX" },
3f4438ab 1135 { RegXMM, "rXMM" },
252b5132
RH		 1136 { EsSeg, "es" },
1137 { 0, "" }
1138};
1139
1140static void
1141pt (t)
1142 unsigned int t;
1143{
29b0f896 1144 const struct type_name *ty;
252b5132 1145
09f131f2
JH		 1146 for (ty = type_names; ty->mask; ty++)
1147 if (t & ty->mask)
1148 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1149 fflush (stdout);
1150}
1151
1152#endif /* DEBUG386 */
1153\f
252b5132 1154#ifdef BFD_ASSEMBLER
29b0f896
AM		 1155static bfd_reloc_code_real_type reloc
1156 PARAMS ((int, int, int, bfd_reloc_code_real_type));
252b5132
RH		 1157
1158static bfd_reloc_code_real_type
3e73aa7c 1159reloc (size, pcrel, sign, other)
252b5132
RH		 1160 int size;
1161 int pcrel;
3e73aa7c 1162 int sign;
252b5132
RH		 1163 bfd_reloc_code_real_type other;
1164{
47926f60
KH		 1165 if (other != NO_RELOC)
1166 return other;
252b5132
RH		 1167
1168 if (pcrel)
1169 {
3e73aa7c 1170 if (!sign)
e5cb08ac 1171 as_bad (_("There are no unsigned pc-relative relocations"));
252b5132
RH		 1172 switch (size)
1173 {
1174 case 1: return BFD_RELOC_8_PCREL;
1175 case 2: return BFD_RELOC_16_PCREL;
1176 case 4: return BFD_RELOC_32_PCREL;
1177 }
d0b47220 1178 as_bad (_("can not do %d byte pc-relative relocation"), size);
252b5132
RH		 1179 }
1180 else
1181 {
3e73aa7c 1182 if (sign)
e5cb08ac 1183 switch (size)
3e73aa7c
JH		 1184 {
1185 case 4: return BFD_RELOC_X86_64_32S;
1186 }
1187 else
1188 switch (size)
1189 {
1190 case 1: return BFD_RELOC_8;
1191 case 2: return BFD_RELOC_16;
1192 case 4: return BFD_RELOC_32;
1193 case 8: return BFD_RELOC_64;
1194 }
1195 as_bad (_("can not do %s %d byte relocation"),
1196 sign ? "signed" : "unsigned", size);
252b5132
RH		 1197 }
1198
bfb32b52 1199 abort ();
252b5132
RH		 1200 return BFD_RELOC_NONE;
1201}
1202
47926f60
KH		 1203/* Here we decide which fixups can be adjusted to make them relative to
1204 the beginning of the section instead of the symbol. Basically we need
1205 to make sure that the dynamic relocations are done correctly, so in
1206 some cases we force the original symbol to be used. */
1207
252b5132 1208int
c0c949c7 1209tc_i386_fix_adjustable (fixP)
31312f95 1210 fixS *fixP ATTRIBUTE_UNUSED;
252b5132 1211{
6d249963 1212#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
31312f95
AM		 1213 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
1214 return 1;
1215
a161fe53
AM		 1216 /* Don't adjust pc-relative references to merge sections in 64-bit
1217 mode. */
1218 if (use_rela_relocations
1219 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1220 && fixP->fx_pcrel)
252b5132 1221 return 0;
31312f95 1222
ce8a8b2f 1223 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1224 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1225 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1226 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1227 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1228 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1229 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1230 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1231 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1232 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1233 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1234 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3e73aa7c
JH		 1235 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1236 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1237 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1238 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1239 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1240 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
1241 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1242 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
252b5132
RH		 1243 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1244 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1245 return 0;
31312f95 1246#endif
252b5132
RH		 1247 return 1;
1248}
1249#else
ec56dfb4 1250#define reloc(SIZE,PCREL,SIGN,OTHER) 0
c6682705 1251#define BFD_RELOC_8 0
ec56dfb4
L		 1252#define BFD_RELOC_16 0
1253#define BFD_RELOC_32 0
c6682705 1254#define BFD_RELOC_8_PCREL 0
ec56dfb4
L		 1255#define BFD_RELOC_16_PCREL 0
1256#define BFD_RELOC_32_PCREL 0
1257#define BFD_RELOC_386_PLT32 0
1258#define BFD_RELOC_386_GOT32 0
1259#define BFD_RELOC_386_GOTOFF 0
13ae64f3
JJ		 1260#define BFD_RELOC_386_TLS_GD 0
1261#define BFD_RELOC_386_TLS_LDM 0
1262#define BFD_RELOC_386_TLS_LDO_32 0
1263#define BFD_RELOC_386_TLS_IE_32 0
37e55690
JJ		 1264#define BFD_RELOC_386_TLS_IE 0
1265#define BFD_RELOC_386_TLS_GOTIE 0
13ae64f3
JJ		 1266#define BFD_RELOC_386_TLS_LE_32 0
1267#define BFD_RELOC_386_TLS_LE 0
ec56dfb4
L		 1268#define BFD_RELOC_X86_64_PLT32 0
1269#define BFD_RELOC_X86_64_GOT32 0
1270#define BFD_RELOC_X86_64_GOTPCREL 0
bffbf940
JJ		 1271#define BFD_RELOC_X86_64_TLSGD 0
1272#define BFD_RELOC_X86_64_TLSLD 0
1273#define BFD_RELOC_X86_64_DTPOFF32 0
1274#define BFD_RELOC_X86_64_GOTTPOFF 0
1275#define BFD_RELOC_X86_64_TPOFF32 0
252b5132
RH		 1276#endif
1277
29b0f896 1278static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1279
1280static int
252b5132 1281intel_float_operand (mnemonic)
29b0f896 1282 const char *mnemonic;
252b5132 1283{
47926f60 1284 if (mnemonic[0] == 'f' && mnemonic[1] == 'i')
cc5ca5ce 1285 return 2;
252b5132
RH		 1286
1287 if (mnemonic[0] == 'f')
1288 return 1;
1289
1290 return 0;
1291}
1292
1293/* This is the guts of the machine-dependent assembler. LINE points to a
1294 machine dependent instruction. This function is supposed to emit
1295 the frags/bytes it assembles to. */
1296
1297void
1298md_assemble (line)
1299 char *line;
1300{
252b5132 1301 int j;
252b5132
RH		 1302 char mnemonic[MAX_MNEM_SIZE];
1303
47926f60 1304 /* Initialize globals. */
252b5132
RH		 1305 memset (&i, '\0', sizeof (i));
1306 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1307 i.reloc[j] = NO_RELOC;
252b5132
RH		 1308 memset (disp_expressions, '\0', sizeof (disp_expressions));
1309 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1310 save_stack_p = save_stack;
252b5132
RH		 1311
1312 /* First parse an instruction mnemonic & call i386_operand for the operands.
1313 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1314 start of a (possibly prefixed) mnemonic. */
252b5132 1315
29b0f896
AM		 1316 line = parse_insn (line, mnemonic);
1317 if (line == NULL)
1318 return;
252b5132 1319
29b0f896
AM		 1320 line = parse_operands (line, mnemonic);
1321 if (line == NULL)
1322 return;
252b5132 1323
29b0f896
AM		 1324 /* Now we've parsed the mnemonic into a set of templates, and have the
1325 operands at hand. */
1326
1327 /* All intel opcodes have reversed operands except for "bound" and
1328 "enter". We also don't reverse intersegment "jmp" and "call"
1329 instructions with 2 immediate operands so that the immediate segment
1330 precedes the offset, as it does when in AT&T mode. "enter" and the
1331 intersegment "jmp" and "call" instructions are the only ones that
1332 have two immediate operands. */
1333 if (intel_syntax && i.operands > 1
1334 && (strcmp (mnemonic, "bound") != 0)
1335 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1336 swap_operands ();
1337
1338 if (i.imm_operands)
1339 optimize_imm ();
1340
1341 if (i.disp_operands)
1342 optimize_disp ();
1343
1344 /* Next, we find a template that matches the given insn,
1345 making sure the overlap of the given operands types is consistent
1346 with the template operand types. */
252b5132 1347
29b0f896
AM		 1348 if (!match_template ())
1349 return;
252b5132 1350
cd61ebfe
AM		 1351 if (intel_syntax)
1352 {
1353 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1354 if (SYSV386_COMPAT
1355 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1356 i.tm.base_opcode ^= FloatR;
1357
1358 /* Zap movzx and movsx suffix. The suffix may have been set from
1359 "word ptr" or "byte ptr" on the source operand, but we'll use
1360 the suffix later to choose the destination register. */
1361 if ((i.tm.base_opcode & ~9) == 0x0fb6)
1362 i.suffix = 0;
1363 }
24eab124 1364
29b0f896
AM		 1365 if (i.tm.opcode_modifier & FWait)
1366 if (!add_prefix (FWAIT_OPCODE))
1367 return;
252b5132 1368
29b0f896
AM		 1369 /* Check string instruction segment overrides. */
1370 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1371 {
1372 if (!check_string ())
5dd0794d 1373 return;
29b0f896 1374 }
5dd0794d 1375
29b0f896
AM		 1376 if (!process_suffix ())
1377 return;
e413e4e9 1378
29b0f896
AM		 1379 /* Make still unresolved immediate matches conform to size of immediate
1380 given in i.suffix. */
1381 if (!finalize_imm ())
1382 return;
252b5132 1383
29b0f896
AM		 1384 if (i.types[0] & Imm1)
1385 i.imm_operands = 0; /* kludge for shift insns. */
1386 if (i.types[0] & ImplicitRegister)
1387 i.reg_operands--;
1388 if (i.types[1] & ImplicitRegister)
1389 i.reg_operands--;
1390 if (i.types[2] & ImplicitRegister)
1391 i.reg_operands--;
252b5132 1392
29b0f896
AM		 1393 if (i.tm.opcode_modifier & ImmExt)
1394 {
1395 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1396 opcode suffix which is coded in the same place as an 8-bit
1397 immediate field would be. Here we fake an 8-bit immediate
1398 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1399
29b0f896 1400 expressionS *exp;
252b5132 1401
29b0f896 1402 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1403
29b0f896
AM		 1404 exp = &im_expressions[i.imm_operands++];
1405 i.op[i.operands].imms = exp;
1406 i.types[i.operands++] = Imm8;
1407 exp->X_op = O_constant;
1408 exp->X_add_number = i.tm.extension_opcode;
1409 i.tm.extension_opcode = None;
1410 }
252b5132 1411
29b0f896
AM		 1412 /* For insns with operands there are more diddles to do to the opcode. */
1413 if (i.operands)
1414 {
1415 if (!process_operands ())
1416 return;
1417 }
1418 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1419 {
1420 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1421 as_warn (_("translating to `%sp'"), i.tm.name);
1422 }
252b5132 1423
29b0f896
AM		 1424 /* Handle conversion of 'int $3' --> special int3 insn. */
1425 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1426 {
1427 i.tm.base_opcode = INT3_OPCODE;
1428 i.imm_operands = 0;
1429 }
252b5132 1430
29b0f896
AM		 1431 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1432 && i.op[0].disps->X_op == O_constant)
1433 {
1434 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1435 the absolute address given by the constant. Since ix86 jumps and
1436 calls are pc relative, we need to generate a reloc. */
1437 i.op[0].disps->X_add_symbol = &abs_symbol;
1438 i.op[0].disps->X_op = O_symbol;
1439 }
252b5132 1440
29b0f896
AM		 1441 if ((i.tm.opcode_modifier & Rex64) != 0)
1442 i.rex |= REX_MODE64;
252b5132 1443
29b0f896
AM		 1444 /* For 8 bit registers we need an empty rex prefix. Also if the
1445 instruction already has a prefix, we need to convert old
1446 registers to new ones. */
773f551c 1447
29b0f896
AM		 1448 if (((i.types[0] & Reg8) != 0
1449 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1450 || ((i.types[1] & Reg8) != 0
1451 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1452 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1453 && i.rex != 0))
1454 {
1455 int x;
726c5dcd 1456
29b0f896
AM		 1457 i.rex |= REX_OPCODE;
1458 for (x = 0; x < 2; x++)
1459 {
1460 /* Look for 8 bit operand that uses old registers. */
1461 if ((i.types[x] & Reg8) != 0
1462 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1463 {
29b0f896
AM		 1464 /* In case it is "hi" register, give up. */
1465 if (i.op[x].regs->reg_num > 3)
1466 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix.\n"),
1467 i.op[x].regs->reg_name);
773f551c 1468
29b0f896
AM		 1469 /* Otherwise it is equivalent to the extended register.
1470 Since the encoding doesn't change this is merely
1471 cosmetic cleanup for debug output. */
1472
1473 i.op[x].regs = i.op[x].regs + 8;
773f551c 1474 }
29b0f896
AM		 1475 }
1476 }
773f551c 1477
29b0f896
AM		 1478 if (i.rex != 0)
1479 add_prefix (REX_OPCODE | i.rex);
1480
1481 /* We are ready to output the insn. */
1482 output_insn ();
1483}
1484
1485static char *
1486parse_insn (line, mnemonic)
1487 char *line;
1488 char *mnemonic;
1489{
1490 char *l = line;
1491 char *token_start = l;
1492 char *mnem_p;
1493
1494 /* Non-zero if we found a prefix only acceptable with string insns. */
1495 const char *expecting_string_instruction = NULL;
45288df1 1496
29b0f896
AM		 1497 while (1)
1498 {
1499 mnem_p = mnemonic;
1500 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1501 {
1502 mnem_p++;
1503 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1504 {
29b0f896
AM		 1505 as_bad (_("no such instruction: `%s'"), token_start);
1506 return NULL;
1507 }
1508 l++;
1509 }
1510 if (!is_space_char (*l)
1511 && *l != END_OF_INSN
1512 && *l != PREFIX_SEPARATOR
1513 && *l != ',')
1514 {
1515 as_bad (_("invalid character %s in mnemonic"),
1516 output_invalid (*l));
1517 return NULL;
1518 }
1519 if (token_start == l)
1520 {
1521 if (*l == PREFIX_SEPARATOR)
1522 as_bad (_("expecting prefix; got nothing"));
1523 else
1524 as_bad (_("expecting mnemonic; got nothing"));
1525 return NULL;
1526 }
45288df1 1527
29b0f896
AM		 1528 /* Look up instruction (or prefix) via hash table. */
1529 current_templates = hash_find (op_hash, mnemonic);
47926f60 1530
29b0f896
AM		 1531 if (*l != END_OF_INSN
1532 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1533 && current_templates
1534 && (current_templates->start->opcode_modifier & IsPrefix))
1535 {
1536 /* If we are in 16-bit mode, do not allow addr16 or data16.
1537 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1538 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1539 && flag_code != CODE_64BIT
1540 && (((current_templates->start->opcode_modifier & Size32) != 0)
1541 ^ (flag_code == CODE_16BIT)))
1542 {
1543 as_bad (_("redundant %s prefix"),
1544 current_templates->start->name);
1545 return NULL;
45288df1 1546 }
29b0f896
AM		 1547 /* Add prefix, checking for repeated prefixes. */
1548 switch (add_prefix (current_templates->start->base_opcode))
1549 {
1550 case 0:
1551 return NULL;
1552 case 2:
1553 expecting_string_instruction = current_templates->start->name;
1554 break;
1555 }
1556 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1557 token_start = ++l;
1558 }
1559 else
1560 break;
1561 }
45288df1 1562
29b0f896
AM		 1563 if (!current_templates)
1564 {
1565 /* See if we can get a match by trimming off a suffix. */
1566 switch (mnem_p[-1])
1567 {
1568 case WORD_MNEM_SUFFIX:
1569 case BYTE_MNEM_SUFFIX:
1570 case QWORD_MNEM_SUFFIX:
1571 i.suffix = mnem_p[-1];
1572 mnem_p[-1] = '\0';
1573 current_templates = hash_find (op_hash, mnemonic);
1574 break;
1575 case SHORT_MNEM_SUFFIX:
1576 case LONG_MNEM_SUFFIX:
1577 if (!intel_syntax)
1578 {
1579 i.suffix = mnem_p[-1];
1580 mnem_p[-1] = '\0';
1581 current_templates = hash_find (op_hash, mnemonic);
1582 }
1583 break;
252b5132 1584
29b0f896
AM		 1585 /* Intel Syntax. */
1586 case 'd':
1587 if (intel_syntax)
1588 {
1589 if (intel_float_operand (mnemonic))
1590 i.suffix = SHORT_MNEM_SUFFIX;
1591 else
1592 i.suffix = LONG_MNEM_SUFFIX;
1593 mnem_p[-1] = '\0';
1594 current_templates = hash_find (op_hash, mnemonic);
1595 }
1596 break;
1597 }
1598 if (!current_templates)
1599 {
1600 as_bad (_("no such instruction: `%s'"), token_start);
1601 return NULL;
1602 }
1603 }
252b5132 1604
29b0f896
AM		 1605 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1606 {
1607 /* Check for a branch hint. We allow ",pt" and ",pn" for
1608 predict taken and predict not taken respectively.
1609 I'm not sure that branch hints actually do anything on loop
1610 and jcxz insns (JumpByte) for current Pentium4 chips. They
1611 may work in the future and it doesn't hurt to accept them
1612 now. */
1613 if (l[0] == ',' && l[1] == 'p')
1614 {
1615 if (l[2] == 't')
1616 {
1617 if (!add_prefix (DS_PREFIX_OPCODE))
1618 return NULL;
1619 l += 3;
1620 }
1621 else if (l[2] == 'n')
1622 {
1623 if (!add_prefix (CS_PREFIX_OPCODE))
1624 return NULL;
1625 l += 3;
1626 }
1627 }
1628 }
1629 /* Any other comma loses. */
1630 if (*l == ',')
1631 {
1632 as_bad (_("invalid character %s in mnemonic"),
1633 output_invalid (*l));
1634 return NULL;
1635 }
252b5132 1636
29b0f896
AM		 1637 /* Check if instruction is supported on specified architecture. */
1638 if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64))
1639 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64)))
1640 {
1641 as_warn (_("`%s' is not supported on `%s'"),
1642 current_templates->start->name, cpu_arch_name);
1643 }
1644 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1645 {
1646 as_warn (_("use .code16 to ensure correct addressing mode"));
1647 }
252b5132 1648
29b0f896
AM		 1649 /* Check for rep/repne without a string instruction. */
1650 if (expecting_string_instruction
1651 && !(current_templates->start->opcode_modifier & IsString))
1652 {
1653 as_bad (_("expecting string instruction after `%s'"),
1654 expecting_string_instruction);
1655 return NULL;
1656 }
252b5132 1657
29b0f896
AM		 1658 return l;
1659}
252b5132 1660
29b0f896
AM		 1661static char *
1662parse_operands (l, mnemonic)
1663 char *l;
1664 const char *mnemonic;
1665{
1666 char *token_start;
3138f287 1667
29b0f896
AM		 1668 /* 1 if operand is pending after ','. */
1669 unsigned int expecting_operand = 0;
252b5132 1670
29b0f896
AM		 1671 /* Non-zero if operand parens not balanced. */
1672 unsigned int paren_not_balanced;
1673
1674 while (*l != END_OF_INSN)
1675 {
1676 /* Skip optional white space before operand. */
1677 if (is_space_char (*l))
1678 ++l;
1679 if (!is_operand_char (*l) && *l != END_OF_INSN)
1680 {
1681 as_bad (_("invalid character %s before operand %d"),
1682 output_invalid (*l),
1683 i.operands + 1);
1684 return NULL;
1685 }
1686 token_start = l; /* after white space */
1687 paren_not_balanced = 0;
1688 while (paren_not_balanced || *l != ',')
1689 {
1690 if (*l == END_OF_INSN)
1691 {
1692 if (paren_not_balanced)
1693 {
1694 if (!intel_syntax)
1695 as_bad (_("unbalanced parenthesis in operand %d."),
1696 i.operands + 1);
1697 else
1698 as_bad (_("unbalanced brackets in operand %d."),
1699 i.operands + 1);
1700 return NULL;
1701 }
1702 else
1703 break; /* we are done */
1704 }
1705 else if (!is_operand_char (*l) && !is_space_char (*l))
1706 {
1707 as_bad (_("invalid character %s in operand %d"),
1708 output_invalid (*l),
1709 i.operands + 1);
1710 return NULL;
1711 }
1712 if (!intel_syntax)
1713 {
1714 if (*l == '(')
1715 ++paren_not_balanced;
1716 if (*l == ')')
1717 --paren_not_balanced;
1718 }
1719 else
1720 {
1721 if (*l == '[')
1722 ++paren_not_balanced;
1723 if (*l == ']')
1724 --paren_not_balanced;
1725 }
1726 l++;
1727 }
1728 if (l != token_start)
1729 { /* Yes, we've read in another operand. */
1730 unsigned int operand_ok;
1731 this_operand = i.operands++;
1732 if (i.operands > MAX_OPERANDS)
1733 {
1734 as_bad (_("spurious operands; (%d operands/instruction max)"),
1735 MAX_OPERANDS);
1736 return NULL;
1737 }
1738 /* Now parse operand adding info to 'i' as we go along. */
1739 END_STRING_AND_SAVE (l);
1740
1741 if (intel_syntax)
1742 operand_ok =
1743 i386_intel_operand (token_start,
1744 intel_float_operand (mnemonic));
1745 else
1746 operand_ok = i386_operand (token_start);
1747
1748 RESTORE_END_STRING (l);
1749 if (!operand_ok)
1750 return NULL;
1751 }
1752 else
1753 {
1754 if (expecting_operand)
1755 {
1756 expecting_operand_after_comma:
1757 as_bad (_("expecting operand after ','; got nothing"));
1758 return NULL;
1759 }
1760 if (*l == ',')
1761 {
1762 as_bad (_("expecting operand before ','; got nothing"));
1763 return NULL;
1764 }
1765 }
7f3f1ea2 1766
29b0f896
AM		 1767 /* Now *l must be either ',' or END_OF_INSN. */
1768 if (*l == ',')
1769 {
1770 if (*++l == END_OF_INSN)
1771 {
1772 /* Just skip it, if it's \n complain. */
1773 goto expecting_operand_after_comma;
1774 }
1775 expecting_operand = 1;
1776 }
1777 }
1778 return l;
1779}
7f3f1ea2 1780
29b0f896
AM		 1781static void
1782swap_operands ()
1783{
1784 union i386_op temp_op;
1785 unsigned int temp_type;
1786 RELOC_ENUM temp_reloc;
1787 int xchg1 = 0;
1788 int xchg2 = 0;
252b5132 1789
29b0f896
AM		 1790 if (i.operands == 2)
1791 {
1792 xchg1 = 0;
1793 xchg2 = 1;
1794 }
1795 else if (i.operands == 3)
1796 {
1797 xchg1 = 0;
1798 xchg2 = 2;
1799 }
1800 temp_type = i.types[xchg2];
1801 i.types[xchg2] = i.types[xchg1];
1802 i.types[xchg1] = temp_type;
1803 temp_op = i.op[xchg2];
1804 i.op[xchg2] = i.op[xchg1];
1805 i.op[xchg1] = temp_op;
1806 temp_reloc = i.reloc[xchg2];
1807 i.reloc[xchg2] = i.reloc[xchg1];
1808 i.reloc[xchg1] = temp_reloc;
1809
1810 if (i.mem_operands == 2)
1811 {
1812 const seg_entry *temp_seg;
1813 temp_seg = i.seg[0];
1814 i.seg[0] = i.seg[1];
1815 i.seg[1] = temp_seg;
1816 }
1817}
252b5132 1818
29b0f896
AM		 1819/* Try to ensure constant immediates are represented in the smallest
1820 opcode possible. */
1821static void
1822optimize_imm ()
1823{
1824 char guess_suffix = 0;
1825 int op;
252b5132 1826
29b0f896
AM		 1827 if (i.suffix)
1828 guess_suffix = i.suffix;
1829 else if (i.reg_operands)
1830 {
1831 /* Figure out a suffix from the last register operand specified.
1832 We can't do this properly yet, ie. excluding InOutPortReg,
1833 but the following works for instructions with immediates.
1834 In any case, we can't set i.suffix yet. */
1835 for (op = i.operands; --op >= 0;)
1836 if (i.types[op] & Reg)
252b5132 1837 {
29b0f896
AM		 1838 if (i.types[op] & Reg8)
1839 guess_suffix = BYTE_MNEM_SUFFIX;
1840 else if (i.types[op] & Reg16)
1841 guess_suffix = WORD_MNEM_SUFFIX;
1842 else if (i.types[op] & Reg32)
1843 guess_suffix = LONG_MNEM_SUFFIX;
1844 else if (i.types[op] & Reg64)
1845 guess_suffix = QWORD_MNEM_SUFFIX;
1846 break;
252b5132 1847 }
29b0f896
AM		 1848 }
1849 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
1850 guess_suffix = WORD_MNEM_SUFFIX;
1851
1852 for (op = i.operands; --op >= 0;)
1853 if (i.types[op] & Imm)
1854 {
1855 switch (i.op[op].imms->X_op)
252b5132 1856 {
29b0f896
AM		 1857 case O_constant:
1858 /* If a suffix is given, this operand may be shortened. */
1859 switch (guess_suffix)
252b5132 1860 {
29b0f896
AM		 1861 case LONG_MNEM_SUFFIX:
1862 i.types[op] |= Imm32 | Imm64;
1863 break;
1864 case WORD_MNEM_SUFFIX:
1865 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
1866 break;
1867 case BYTE_MNEM_SUFFIX:
1868 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
1869 break;
252b5132 1870 }
252b5132 1871
29b0f896
AM		 1872 /* If this operand is at most 16 bits, convert it
1873 to a signed 16 bit number before trying to see
1874 whether it will fit in an even smaller size.
1875 This allows a 16-bit operand such as $0xffe0 to
1876 be recognised as within Imm8S range. */
1877 if ((i.types[op] & Imm16)
1878 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 1879 {
29b0f896
AM		 1880 i.op[op].imms->X_add_number =
1881 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
1882 }
1883 if ((i.types[op] & Imm32)
1884 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
1885 == 0))
1886 {
1887 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
1888 ^ ((offsetT) 1 << 31))
1889 - ((offsetT) 1 << 31));
1890 }
1891 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 1892
29b0f896
AM		 1893 /* We must avoid matching of Imm32 templates when 64bit
1894 only immediate is available. */
1895 if (guess_suffix == QWORD_MNEM_SUFFIX)
1896 i.types[op] &= ~Imm32;
1897 break;
252b5132 1898
29b0f896
AM		 1899 case O_absent:
1900 case O_register:
1901 abort ();
1902
1903 /* Symbols and expressions. */
1904 default:
1905 /* Convert symbolic operand to proper sizes for matching. */
1906 switch (guess_suffix)
1907 {
1908 case QWORD_MNEM_SUFFIX:
1909 i.types[op] = Imm64 | Imm32S;
1910 break;
1911 case LONG_MNEM_SUFFIX:
1912 i.types[op] = Imm32 | Imm64;
1913 break;
1914 case WORD_MNEM_SUFFIX:
1915 i.types[op] = Imm16 | Imm32 | Imm64;
1916 break;
1917 break;
1918 case BYTE_MNEM_SUFFIX:
1919 i.types[op] = Imm8 | Imm8S | Imm16 | Imm32S | Imm32;
1920 break;
1921 break;
252b5132 1922 }
29b0f896 1923 break;
252b5132 1924 }
29b0f896
AM		 1925 }
1926}
47926f60 1927
29b0f896
AM		 1928/* Try to use the smallest displacement type too. */
1929static void
1930optimize_disp ()
1931{
1932 int op;
3e73aa7c 1933
29b0f896
AM		 1934 for (op = i.operands; --op >= 0;)
1935 if ((i.types[op] & Disp) && i.op[op].disps->X_op == O_constant)
252b5132 1936 {
29b0f896
AM		 1937 offsetT disp = i.op[op].disps->X_add_number;
1938
1939 if (i.types[op] & Disp16)
252b5132 1940 {
29b0f896
AM		 1941 /* We know this operand is at most 16 bits, so
1942 convert to a signed 16 bit number before trying
1943 to see whether it will fit in an even smaller
1944 size. */
1945
1946 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
252b5132 1947 }
29b0f896 1948 else if (i.types[op] & Disp32)
252b5132 1949 {
29b0f896
AM		 1950 /* We know this operand is at most 32 bits, so convert to a
1951 signed 32 bit number before trying to see whether it will
1952 fit in an even smaller size. */
1953 disp &= (((offsetT) 2 << 31) - 1);
1954 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 1955 }
29b0f896 1956 if (flag_code == CODE_64BIT)
252b5132 1957 {
29b0f896
AM		 1958 if (fits_in_signed_long (disp))
1959 i.types[op] |= Disp32S;
1960 if (fits_in_unsigned_long (disp))
1961 i.types[op] |= Disp32;
252b5132 1962 }
29b0f896
AM		 1963 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
1964 && fits_in_signed_byte (disp))
1965 i.types[op] |= Disp8;
252b5132 1966 }
29b0f896
AM		 1967}
1968
1969static int
1970match_template ()
1971{
1972 /* Points to template once we've found it. */
1973 const template *t;
1974 unsigned int overlap0, overlap1, overlap2;
1975 unsigned int found_reverse_match;
1976 int suffix_check;
1977
1978#define MATCH(overlap, given, template) \
1979 ((overlap & ~JumpAbsolute) \
1980 && (((given) & (BaseIndex | JumpAbsolute)) \
1981 == ((overlap) & (BaseIndex | JumpAbsolute))))
1982
1983 /* If given types r0 and r1 are registers they must be of the same type
1984 unless the expected operand type register overlap is null.
1985 Note that Acc in a template matches every size of reg. */
1986#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1987 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
1988 || ((g0) & Reg) == ((g1) & Reg) \
1989 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1990
1991 overlap0 = 0;
1992 overlap1 = 0;
1993 overlap2 = 0;
1994 found_reverse_match = 0;
1995 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
1996 ? No_bSuf
1997 : (i.suffix == WORD_MNEM_SUFFIX
1998 ? No_wSuf
1999 : (i.suffix == SHORT_MNEM_SUFFIX
2000 ? No_sSuf
2001 : (i.suffix == LONG_MNEM_SUFFIX
2002 ? No_lSuf
2003 : (i.suffix == QWORD_MNEM_SUFFIX
2004 ? No_qSuf
2005 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2006 ? No_xSuf : 0))))));
2007
2008 for (t = current_templates->start;
2009 t < current_templates->end;
2010 t++)
2011 {
2012 /* Must have right number of operands. */
2013 if (i.operands != t->operands)
2014 continue;
2015
2016 /* Check the suffix, except for some instructions in intel mode. */
2017 if ((t->opcode_modifier & suffix_check)
2018 && !(intel_syntax
2019 && (t->opcode_modifier & IgnoreSize))
2020 && !(intel_syntax
2021 && t->base_opcode == 0xd9
2022 && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */
2023 || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */
2024 continue;
2025
2026 /* Do not verify operands when there are none. */
2027 else if (!t->operands)
2028 {
2029 if (t->cpu_flags & ~cpu_arch_flags)
2030 continue;
2031 /* We've found a match; break out of loop. */
2032 break;
2033 }
252b5132 2034
29b0f896
AM		 2035 overlap0 = i.types[0] & t->operand_types[0];
2036 switch (t->operands)
2037 {
2038 case 1:
2039 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2040 continue;
2041 break;
2042 case 2:
2043 case 3:
2044 overlap1 = i.types[1] & t->operand_types[1];
2045 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2046 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2047 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2048 t->operand_types[0],
2049 overlap1, i.types[1],
2050 t->operand_types[1]))
2051 {
2052 /* Check if other direction is valid ... */
2053 if ((t->opcode_modifier & (D | FloatD)) == 0)
2054 continue;
2055
2056 /* Try reversing direction of operands. */
2057 overlap0 = i.types[0] & t->operand_types[1];
2058 overlap1 = i.types[1] & t->operand_types[0];
2059 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2060 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2061 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2062 t->operand_types[1],
2063 overlap1, i.types[1],
2064 t->operand_types[0]))
2065 {
2066 /* Does not match either direction. */
2067 continue;
2068 }
2069 /* found_reverse_match holds which of D or FloatDR
2070 we've found. */
2071 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2072 }
2073 /* Found a forward 2 operand match here. */
2074 else if (t->operands == 3)
2075 {
2076 /* Here we make use of the fact that there are no
2077 reverse match 3 operand instructions, and all 3
2078 operand instructions only need to be checked for
2079 register consistency between operands 2 and 3. */
2080 overlap2 = i.types[2] & t->operand_types[2];
2081 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2082 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2083 t->operand_types[1],
2084 overlap2, i.types[2],
2085 t->operand_types[2]))
2086
2087 continue;
2088 }
2089 /* Found either forward/reverse 2 or 3 operand match here:
2090 slip through to break. */
2091 }
2092 if (t->cpu_flags & ~cpu_arch_flags)
2093 {
2094 found_reverse_match = 0;
2095 continue;
2096 }
2097 /* We've found a match; break out of loop. */
2098 break;
2099 }
2100
2101 if (t == current_templates->end)
2102 {
2103 /* We found no match. */
2104 as_bad (_("suffix or operands invalid for `%s'"),
2105 current_templates->start->name);
2106 return 0;
2107 }
252b5132 2108
29b0f896
AM		 2109 if (!quiet_warnings)
2110 {
2111 if (!intel_syntax
2112 && ((i.types[0] & JumpAbsolute)
2113 != (t->operand_types[0] & JumpAbsolute)))
2114 {
2115 as_warn (_("indirect %s without `*'"), t->name);
2116 }
2117
2118 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2119 == (IsPrefix | IgnoreSize))
2120 {
2121 /* Warn them that a data or address size prefix doesn't
2122 affect assembly of the next line of code. */
2123 as_warn (_("stand-alone `%s' prefix"), t->name);
2124 }
2125 }
2126
2127 /* Copy the template we found. */
2128 i.tm = *t;
2129 if (found_reverse_match)
2130 {
2131 /* If we found a reverse match we must alter the opcode
2132 direction bit. found_reverse_match holds bits to change
2133 (different for int & float insns). */
2134
2135 i.tm.base_opcode ^= found_reverse_match;
2136
2137 i.tm.operand_types[0] = t->operand_types[1];
2138 i.tm.operand_types[1] = t->operand_types[0];
2139 }
2140
2141 return 1;
2142}
2143
2144static int
2145check_string ()
2146{
2147 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2148 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2149 {
2150 if (i.seg[0] != NULL && i.seg[0] != &es)
2151 {
2152 as_bad (_("`%s' operand %d must use `%%es' segment"),
2153 i.tm.name,
2154 mem_op + 1);
2155 return 0;
2156 }
2157 /* There's only ever one segment override allowed per instruction.
2158 This instruction possibly has a legal segment override on the
2159 second operand, so copy the segment to where non-string
2160 instructions store it, allowing common code. */
2161 i.seg[0] = i.seg[1];
2162 }
2163 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2164 {
2165 if (i.seg[1] != NULL && i.seg[1] != &es)
2166 {
2167 as_bad (_("`%s' operand %d must use `%%es' segment"),
2168 i.tm.name,
2169 mem_op + 2);
2170 return 0;
2171 }
2172 }
2173 return 1;
2174}
2175
2176static int
2177process_suffix ()
2178{
2179 /* If matched instruction specifies an explicit instruction mnemonic
2180 suffix, use it. */
2181 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2182 {
2183 if (i.tm.opcode_modifier & Size16)
2184 i.suffix = WORD_MNEM_SUFFIX;
2185 else if (i.tm.opcode_modifier & Size64)
2186 i.suffix = QWORD_MNEM_SUFFIX;
2187 else
2188 i.suffix = LONG_MNEM_SUFFIX;
2189 }
2190 else if (i.reg_operands)
2191 {
2192 /* If there's no instruction mnemonic suffix we try to invent one
2193 based on register operands. */
2194 if (!i.suffix)
2195 {
2196 /* We take i.suffix from the last register operand specified,
2197 Destination register type is more significant than source
2198 register type. */
2199 int op;
2200 for (op = i.operands; --op >= 0;)
2201 if ((i.types[op] & Reg)
2202 && !(i.tm.operand_types[op] & InOutPortReg))
2203 {
2204 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2205 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2206 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2207 LONG_MNEM_SUFFIX);
2208 break;
2209 }
2210 }
2211 else if (i.suffix == BYTE_MNEM_SUFFIX)
2212 {
2213 if (!check_byte_reg ())
2214 return 0;
2215 }
2216 else if (i.suffix == LONG_MNEM_SUFFIX)
2217 {
2218 if (!check_long_reg ())
2219 return 0;
2220 }
2221 else if (i.suffix == QWORD_MNEM_SUFFIX)
2222 {
2223 if (!check_qword_reg ())
2224 return 0;
2225 }
2226 else if (i.suffix == WORD_MNEM_SUFFIX)
2227 {
2228 if (!check_word_reg ())
2229 return 0;
2230 }
2231 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2232 /* Do nothing if the instruction is going to ignore the prefix. */
2233 ;
2234 else
2235 abort ();
2236 }
2237 else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix)
2238 {
2239 i.suffix = stackop_size;
2240 }
252b5132 2241
29b0f896
AM		 2242 /* Change the opcode based on the operand size given by i.suffix;
2243 We need not change things for byte insns. */
252b5132 2244
29b0f896
AM		 2245 if (!i.suffix && (i.tm.opcode_modifier & W))
2246 {
2247 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2248 return 0;
2249 }
252b5132 2250
29b0f896
AM		 2251 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2252 {
2253 /* It's not a byte, select word/dword operation. */
2254 if (i.tm.opcode_modifier & W)
2255 {
2256 if (i.tm.opcode_modifier & ShortForm)
2257 i.tm.base_opcode |= 8;
2258 else
2259 i.tm.base_opcode |= 1;
2260 }
0f3f3d8b 2261
29b0f896
AM		 2262 /* Now select between word & dword operations via the operand
2263 size prefix, except for instructions that will ignore this
2264 prefix anyway. */
2265 if (i.suffix != QWORD_MNEM_SUFFIX
9146926a
AM		 2266 && !(i.tm.opcode_modifier & IgnoreSize)
2267 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2268 || (flag_code == CODE_64BIT
2269 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2270 {
2271 unsigned int prefix = DATA_PREFIX_OPCODE;
29b0f896
AM		 2272 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2273 prefix = ADDR_PREFIX_OPCODE;
252b5132 2274
29b0f896
AM		 2275 if (!add_prefix (prefix))
2276 return 0;
24eab124 2277 }
252b5132 2278
29b0f896
AM		 2279 /* Set mode64 for an operand. */
2280 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2281 && flag_code == CODE_64BIT
29b0f896 2282 && (i.tm.opcode_modifier & NoRex64) == 0)
9146926a 2283 i.rex |= REX_MODE64;
3e73aa7c 2284
29b0f896
AM		 2285 /* Size floating point instruction. */
2286 if (i.suffix == LONG_MNEM_SUFFIX)
2287 {
2288 if (i.tm.opcode_modifier & FloatMF)
2289 i.tm.base_opcode ^= 4;
2290 }
2291 }
7ecd2f8b 2292
29b0f896
AM		 2293 return 1;
2294}
3e73aa7c 2295
29b0f896
AM		 2296static int
2297check_byte_reg ()
2298{
2299 int op;
2300 for (op = i.operands; --op >= 0;)
2301 {
2302 /* If this is an eight bit register, it's OK. If it's the 16 or
2303 32 bit version of an eight bit register, we will just use the
2304 low portion, and that's OK too. */
2305 if (i.types[op] & Reg8)
2306 continue;
2307
2308 /* movzx and movsx should not generate this warning. */
2309 if (intel_syntax
2310 && (i.tm.base_opcode == 0xfb7
2311 || i.tm.base_opcode == 0xfb6
2312 || i.tm.base_opcode == 0x63
2313 || i.tm.base_opcode == 0xfbe
2314 || i.tm.base_opcode == 0xfbf))
2315 continue;
2316
2317 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4
2318#if 0
2319 /* Check that the template allows eight bit regs. This
2320 kills insns such as `orb $1,%edx', which maybe should be
2321 allowed. */
2322 && (i.tm.operand_types[op] & (Reg8 | InOutPortReg))
2323#endif
2324 )
2325 {
2326 /* Prohibit these changes in the 64bit mode, since the
2327 lowering is more complicated. */
2328 if (flag_code == CODE_64BIT
2329 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2330 {
0f3f3d8b 2331 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2332 i.op[op].regs->reg_name,
2333 i.suffix);
2334 return 0;
2335 }
2336#if REGISTER_WARNINGS
2337 if (!quiet_warnings
2338 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2339 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2340 (i.op[op].regs + (i.types[op] & Reg16
2341 ? REGNAM_AL - REGNAM_AX
2342 : REGNAM_AL - REGNAM_EAX))->reg_name,
2343 i.op[op].regs->reg_name,
2344 i.suffix);
2345#endif
2346 continue;
2347 }
2348 /* Any other register is bad. */
2349 if (i.types[op] & (Reg | RegMMX | RegXMM
2350 | SReg2 | SReg3
2351 | Control | Debug | Test
2352 | FloatReg | FloatAcc))
2353 {
2354 as_bad (_("`%%%s' not allowed with `%s%c'"),
2355 i.op[op].regs->reg_name,
2356 i.tm.name,
2357 i.suffix);
2358 return 0;
2359 }
2360 }
2361 return 1;
2362}
2363
2364static int
2365check_long_reg ()
2366{
2367 int op;
2368
2369 for (op = i.operands; --op >= 0;)
2370 /* Reject eight bit registers, except where the template requires
2371 them. (eg. movzb) */
2372 if ((i.types[op] & Reg8) != 0
2373 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2374 {
2375 as_bad (_("`%%%s' not allowed with `%s%c'"),
2376 i.op[op].regs->reg_name,
2377 i.tm.name,
2378 i.suffix);
2379 return 0;
2380 }
2381 /* Warn if the e prefix on a general reg is missing. */
2382 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2383 && (i.types[op] & Reg16) != 0
2384 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2385 {
2386 /* Prohibit these changes in the 64bit mode, since the
2387 lowering is more complicated. */
2388 if (flag_code == CODE_64BIT)
252b5132 2389 {
0f3f3d8b 2390 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2391 i.op[op].regs->reg_name,
2392 i.suffix);
2393 return 0;
252b5132 2394 }
29b0f896
AM		 2395#if REGISTER_WARNINGS
2396 else
2397 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2398 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2399 i.op[op].regs->reg_name,
2400 i.suffix);
2401#endif
252b5132 2402 }
29b0f896
AM		 2403 /* Warn if the r prefix on a general reg is missing. */
2404 else if ((i.types[op] & Reg64) != 0
2405 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 2406 {
0f3f3d8b 2407 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2408 i.op[op].regs->reg_name,
2409 i.suffix);
2410 return 0;
2411 }
2412 return 1;
2413}
252b5132 2414
29b0f896
AM		 2415static int
2416check_qword_reg ()
2417{
2418 int op;
252b5132 2419
29b0f896
AM		 2420 for (op = i.operands; --op >= 0; )
2421 /* Reject eight bit registers, except where the template requires
2422 them. (eg. movzb) */
2423 if ((i.types[op] & Reg8) != 0
2424 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2425 {
2426 as_bad (_("`%%%s' not allowed with `%s%c'"),
2427 i.op[op].regs->reg_name,
2428 i.tm.name,
2429 i.suffix);
2430 return 0;
2431 }
2432 /* Warn if the e prefix on a general reg is missing. */
2433 else if (((i.types[op] & Reg16) != 0
2434 || (i.types[op] & Reg32) != 0)
2435 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2436 {
2437 /* Prohibit these changes in the 64bit mode, since the
2438 lowering is more complicated. */
0f3f3d8b 2439 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2440 i.op[op].regs->reg_name,
2441 i.suffix);
2442 return 0;
252b5132 2443 }
29b0f896
AM		 2444 return 1;
2445}
252b5132 2446
29b0f896
AM		 2447static int
2448check_word_reg ()
2449{
2450 int op;
2451 for (op = i.operands; --op >= 0;)
2452 /* Reject eight bit registers, except where the template requires
2453 them. (eg. movzb) */
2454 if ((i.types[op] & Reg8) != 0
2455 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2456 {
2457 as_bad (_("`%%%s' not allowed with `%s%c'"),
2458 i.op[op].regs->reg_name,
2459 i.tm.name,
2460 i.suffix);
2461 return 0;
2462 }
2463 /* Warn if the e prefix on a general reg is present. */
2464 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2465 && (i.types[op] & Reg32) != 0
2466 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 2467 {
29b0f896
AM		 2468 /* Prohibit these changes in the 64bit mode, since the
2469 lowering is more complicated. */
2470 if (flag_code == CODE_64BIT)
252b5132 2471 {
0f3f3d8b 2472 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2473 i.op[op].regs->reg_name,
2474 i.suffix);
2475 return 0;
252b5132 2476 }
29b0f896
AM		 2477 else
2478#if REGISTER_WARNINGS
2479 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2480 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2481 i.op[op].regs->reg_name,
2482 i.suffix);
2483#endif
2484 }
2485 return 1;
2486}
252b5132 2487
29b0f896
AM		 2488static int
2489finalize_imm ()
2490{
2491 unsigned int overlap0, overlap1, overlap2;
2492
2493 overlap0 = i.types[0] & i.tm.operand_types[0];
2494 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S))
2495 && overlap0 != Imm8 && overlap0 != Imm8S
2496 && overlap0 != Imm16 && overlap0 != Imm32S
2497 && overlap0 != Imm32 && overlap0 != Imm64)
2498 {
2499 if (i.suffix)
2500 {
2501 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2502 ? Imm8 | Imm8S
2503 : (i.suffix == WORD_MNEM_SUFFIX
2504 ? Imm16
2505 : (i.suffix == QWORD_MNEM_SUFFIX
2506 ? Imm64 | Imm32S
2507 : Imm32)));
2508 }
2509 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2510 || overlap0 == (Imm16 | Imm32)
2511 || overlap0 == (Imm16 | Imm32S))
2512 {
2513 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2514 ? Imm16 : Imm32S);
2515 }
2516 if (overlap0 != Imm8 && overlap0 != Imm8S
2517 && overlap0 != Imm16 && overlap0 != Imm32S
2518 && overlap0 != Imm32 && overlap0 != Imm64)
2519 {
2520 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2521 return 0;
2522 }
2523 }
2524 i.types[0] = overlap0;
2525
2526 overlap1 = i.types[1] & i.tm.operand_types[1];
2527 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32))
2528 && overlap1 != Imm8 && overlap1 != Imm8S
2529 && overlap1 != Imm16 && overlap1 != Imm32S
2530 && overlap1 != Imm32 && overlap1 != Imm64)
2531 {
2532 if (i.suffix)
2533 {
2534 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2535 ? Imm8 | Imm8S
2536 : (i.suffix == WORD_MNEM_SUFFIX
2537 ? Imm16
2538 : (i.suffix == QWORD_MNEM_SUFFIX
2539 ? Imm64 | Imm32S
2540 : Imm32)));
2541 }
2542 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2543 || overlap1 == (Imm16 | Imm32)
2544 || overlap1 == (Imm16 | Imm32S))
2545 {
2546 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2547 ? Imm16 : Imm32S);
2548 }
2549 if (overlap1 != Imm8 && overlap1 != Imm8S
2550 && overlap1 != Imm16 && overlap1 != Imm32S
2551 && overlap1 != Imm32 && overlap1 != Imm64)
2552 {
2553 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2554 return 0;
2555 }
2556 }
2557 i.types[1] = overlap1;
2558
2559 overlap2 = i.types[2] & i.tm.operand_types[2];
2560 assert ((overlap2 & Imm) == 0);
2561 i.types[2] = overlap2;
2562
2563 return 1;
2564}
2565
2566static int
2567process_operands ()
2568{
2569 /* Default segment register this instruction will use for memory
2570 accesses. 0 means unknown. This is only for optimizing out
2571 unnecessary segment overrides. */
2572 const seg_entry *default_seg = 0;
2573
2574 /* The imul $imm, %reg instruction is converted into
2575 imul $imm, %reg, %reg, and the clr %reg instruction
2576 is converted into xor %reg, %reg. */
2577 if (i.tm.opcode_modifier & regKludge)
2578 {
2579 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2580 /* Pretend we saw the extra register operand. */
2581 assert (i.op[first_reg_op + 1].regs == 0);
2582 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2583 i.types[first_reg_op + 1] = i.types[first_reg_op];
2584 i.reg_operands = 2;
2585 }
2586
2587 if (i.tm.opcode_modifier & ShortForm)
2588 {
2589 /* The register or float register operand is in operand 0 or 1. */
2590 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2591 /* Register goes in low 3 bits of opcode. */
2592 i.tm.base_opcode |= i.op[op].regs->reg_num;
2593 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2594 i.rex |= REX_EXTZ;
2595 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2596 {
2597 /* Warn about some common errors, but press on regardless.
2598 The first case can be generated by gcc (<= 2.8.1). */
2599 if (i.operands == 2)
2600 {
2601 /* Reversed arguments on faddp, fsubp, etc. */
2602 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2603 i.op[1].regs->reg_name,
2604 i.op[0].regs->reg_name);
2605 }
2606 else
2607 {
2608 /* Extraneous `l' suffix on fp insn. */
2609 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2610 i.op[0].regs->reg_name);
2611 }
2612 }
2613 }
2614 else if (i.tm.opcode_modifier & Modrm)
2615 {
2616 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 2617 must be put into the modrm byte). Now, we make the modrm and
2618 index base bytes based on all the info we've collected. */
29b0f896
AM		 2619
2620 default_seg = build_modrm_byte ();
2621 }
2622 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2623 {
2624 if (i.tm.base_opcode == POP_SEG_SHORT
2625 && i.op[0].regs->reg_num == 1)
2626 {
2627 as_bad (_("you can't `pop %%cs'"));
2628 return 0;
2629 }
2630 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2631 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2632 i.rex |= REX_EXTZ;
2633 }
2634 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2635 {
2636 default_seg = &ds;
2637 }
2638 else if ((i.tm.opcode_modifier & IsString) != 0)
2639 {
2640 /* For the string instructions that allow a segment override
2641 on one of their operands, the default segment is ds. */
2642 default_seg = &ds;
2643 }
2644
52271982
AM		 2645 if (i.tm.base_opcode == 0x8d /* lea */ && i.seg[0] && !quiet_warnings)
2646 as_warn (_("segment override on `lea' is ineffectual"));
2647
2648 /* If a segment was explicitly specified, and the specified segment
2649 is not the default, use an opcode prefix to select it. If we
2650 never figured out what the default segment is, then default_seg
2651 will be zero at this point, and the specified segment prefix will
2652 always be used. */
29b0f896
AM		 2653 if ((i.seg[0]) && (i.seg[0] != default_seg))
2654 {
2655 if (!add_prefix (i.seg[0]->seg_prefix))
2656 return 0;
2657 }
2658 return 1;
2659}
2660
2661static const seg_entry *
2662build_modrm_byte ()
2663{
2664 const seg_entry *default_seg = 0;
2665
2666 /* i.reg_operands MUST be the number of real register operands;
2667 implicit registers do not count. */
2668 if (i.reg_operands == 2)
2669 {
2670 unsigned int source, dest;
2671 source = ((i.types[0]
2672 & (Reg | RegMMX | RegXMM
2673 | SReg2 | SReg3
2674 | Control | Debug | Test))
2675 ? 0 : 1);
2676 dest = source + 1;
2677
2678 i.rm.mode = 3;
2679 /* One of the register operands will be encoded in the i.tm.reg
2680 field, the other in the combined i.tm.mode and i.tm.regmem
2681 fields. If no form of this instruction supports a memory
2682 destination operand, then we assume the source operand may
2683 sometimes be a memory operand and so we need to store the
2684 destination in the i.rm.reg field. */
2685 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2686 {
2687 i.rm.reg = i.op[dest].regs->reg_num;
2688 i.rm.regmem = i.op[source].regs->reg_num;
2689 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2690 i.rex |= REX_EXTX;
2691 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2692 i.rex |= REX_EXTZ;
2693 }
2694 else
2695 {
2696 i.rm.reg = i.op[source].regs->reg_num;
2697 i.rm.regmem = i.op[dest].regs->reg_num;
2698 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2699 i.rex |= REX_EXTZ;
2700 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2701 i.rex |= REX_EXTX;
2702 }
2703 }
2704 else
2705 { /* If it's not 2 reg operands... */
2706 if (i.mem_operands)
2707 {
2708 unsigned int fake_zero_displacement = 0;
2709 unsigned int op = ((i.types[0] & AnyMem)
2710 ? 0
2711 : (i.types[1] & AnyMem) ? 1 : 2);
2712
2713 default_seg = &ds;
2714
2715 if (i.base_reg == 0)
2716 {
2717 i.rm.mode = 0;
2718 if (!i.disp_operands)
2719 fake_zero_displacement = 1;
2720 if (i.index_reg == 0)
2721 {
2722 /* Operand is just <disp> */
2723 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
2724 && (flag_code != CODE_64BIT))
2725 {
2726 i.rm.regmem = NO_BASE_REGISTER_16;
2727 i.types[op] &= ~Disp;
2728 i.types[op] |= Disp16;
2729 }
2730 else if (flag_code != CODE_64BIT
2731 || (i.prefix[ADDR_PREFIX] != 0))
2732 {
2733 i.rm.regmem = NO_BASE_REGISTER;
2734 i.types[op] &= ~Disp;
2735 i.types[op] |= Disp32;
2736 }
2737 else
2738 {
2739 /* 64bit mode overwrites the 32bit absolute
2740 addressing by RIP relative addressing and
2741 absolute addressing is encoded by one of the
2742 redundant SIB forms. */
2743 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2744 i.sib.base = NO_BASE_REGISTER;
2745 i.sib.index = NO_INDEX_REGISTER;
2746 i.types[op] &= ~Disp;
2747 i.types[op] |= Disp32S;
2748 }
2749 }
2750 else /* !i.base_reg && i.index_reg */
2751 {
2752 i.sib.index = i.index_reg->reg_num;
2753 i.sib.base = NO_BASE_REGISTER;
2754 i.sib.scale = i.log2_scale_factor;
2755 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2756 i.types[op] &= ~Disp;
2757 if (flag_code != CODE_64BIT)
2758 i.types[op] |= Disp32; /* Must be 32 bit */
2759 else
2760 i.types[op] |= Disp32S;
2761 if ((i.index_reg->reg_flags & RegRex) != 0)
2762 i.rex |= REX_EXTY;
2763 }
2764 }
2765 /* RIP addressing for 64bit mode. */
2766 else if (i.base_reg->reg_type == BaseIndex)
2767 {
2768 i.rm.regmem = NO_BASE_REGISTER;
2769 i.types[op] &= ~Disp;
2770 i.types[op] |= Disp32S;
2771 i.flags[op] = Operand_PCrel;
2772 }
2773 else if (i.base_reg->reg_type & Reg16)
2774 {
2775 switch (i.base_reg->reg_num)
2776 {
2777 case 3: /* (%bx) */
2778 if (i.index_reg == 0)
2779 i.rm.regmem = 7;
2780 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2781 i.rm.regmem = i.index_reg->reg_num - 6;
2782 break;
2783 case 5: /* (%bp) */
2784 default_seg = &ss;
2785 if (i.index_reg == 0)
2786 {
2787 i.rm.regmem = 6;
2788 if ((i.types[op] & Disp) == 0)
2789 {
2790 /* fake (%bp) into 0(%bp) */
2791 i.types[op] |= Disp8;
252b5132 2792 fake_zero_displacement = 1;
29b0f896
AM		 2793 }
2794 }
2795 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2796 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
2797 break;
2798 default: /* (%si) -> 4 or (%di) -> 5 */
2799 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
2800 }
2801 i.rm.mode = mode_from_disp_size (i.types[op]);
2802 }
2803 else /* i.base_reg and 32/64 bit mode */
2804 {
2805 if (flag_code == CODE_64BIT
2806 && (i.types[op] & Disp))
2807 {
2808 if (i.types[op] & Disp8)
2809 i.types[op] = Disp8 | Disp32S;
2810 else
2811 i.types[op] = Disp32S;
2812 }
2813 i.rm.regmem = i.base_reg->reg_num;
2814 if ((i.base_reg->reg_flags & RegRex) != 0)
2815 i.rex |= REX_EXTZ;
2816 i.sib.base = i.base_reg->reg_num;
2817 /* x86-64 ignores REX prefix bit here to avoid decoder
2818 complications. */
2819 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
2820 {
2821 default_seg = &ss;
2822 if (i.disp_operands == 0)
2823 {
2824 fake_zero_displacement = 1;
2825 i.types[op] |= Disp8;
2826 }
2827 }
2828 else if (i.base_reg->reg_num == ESP_REG_NUM)
2829 {
2830 default_seg = &ss;
2831 }
2832 i.sib.scale = i.log2_scale_factor;
2833 if (i.index_reg == 0)
2834 {
2835 /* <disp>(%esp) becomes two byte modrm with no index
2836 register. We've already stored the code for esp
2837 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
2838 Any base register besides %esp will not use the
2839 extra modrm byte. */
2840 i.sib.index = NO_INDEX_REGISTER;
2841#if !SCALE1_WHEN_NO_INDEX
2842 /* Another case where we force the second modrm byte. */
2843 if (i.log2_scale_factor)
2844 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 2845#endif
29b0f896
AM		 2846 }
2847 else
2848 {
2849 i.sib.index = i.index_reg->reg_num;
2850 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2851 if ((i.index_reg->reg_flags & RegRex) != 0)
2852 i.rex |= REX_EXTY;
2853 }
2854 i.rm.mode = mode_from_disp_size (i.types[op]);
2855 }
252b5132 2856
29b0f896
AM		 2857 if (fake_zero_displacement)
2858 {
2859 /* Fakes a zero displacement assuming that i.types[op]
2860 holds the correct displacement size. */
2861 expressionS *exp;
2862
2863 assert (i.op[op].disps == 0);
2864 exp = &disp_expressions[i.disp_operands++];
2865 i.op[op].disps = exp;
2866 exp->X_op = O_constant;
2867 exp->X_add_number = 0;
2868 exp->X_add_symbol = (symbolS *) 0;
2869 exp->X_op_symbol = (symbolS *) 0;
2870 }
2871 }
252b5132 2872
29b0f896
AM		 2873 /* Fill in i.rm.reg or i.rm.regmem field with register operand
2874 (if any) based on i.tm.extension_opcode. Again, we must be
2875 careful to make sure that segment/control/debug/test/MMX
2876 registers are coded into the i.rm.reg field. */
2877 if (i.reg_operands)
2878 {
2879 unsigned int op =
2880 ((i.types[0]
2881 & (Reg | RegMMX | RegXMM
2882 | SReg2 | SReg3
2883 | Control | Debug | Test))
2884 ? 0
2885 : ((i.types[1]
2886 & (Reg | RegMMX | RegXMM
2887 | SReg2 | SReg3
2888 | Control | Debug | Test))
2889 ? 1
2890 : 2));
2891 /* If there is an extension opcode to put here, the register
2892 number must be put into the regmem field. */
2893 if (i.tm.extension_opcode != None)
2894 {
2895 i.rm.regmem = i.op[op].regs->reg_num;
2896 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2897 i.rex |= REX_EXTZ;
2898 }
2899 else
2900 {
2901 i.rm.reg = i.op[op].regs->reg_num;
2902 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2903 i.rex |= REX_EXTX;
2904 }
252b5132 2905
29b0f896
AM		 2906 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
2907 must set it to 3 to indicate this is a register operand
2908 in the regmem field. */
2909 if (!i.mem_operands)
2910 i.rm.mode = 3;
2911 }
252b5132 2912
29b0f896
AM		 2913 /* Fill in i.rm.reg field with extension opcode (if any). */
2914 if (i.tm.extension_opcode != None)
2915 i.rm.reg = i.tm.extension_opcode;
2916 }
2917 return default_seg;
2918}
252b5132 2919
29b0f896
AM		 2920static void
2921output_branch ()
2922{
2923 char *p;
2924 int code16;
2925 int prefix;
2926 relax_substateT subtype;
2927 symbolS *sym;
2928 offsetT off;
2929
2930 code16 = 0;
2931 if (flag_code == CODE_16BIT)
2932 code16 = CODE16;
2933
2934 prefix = 0;
2935 if (i.prefix[DATA_PREFIX] != 0)
252b5132 2936 {
29b0f896
AM		 2937 prefix = 1;
2938 i.prefixes -= 1;
2939 code16 ^= CODE16;
252b5132 2940 }
29b0f896
AM		 2941 /* Pentium4 branch hints. */
2942 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
2943 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 2944 {
29b0f896
AM		 2945 prefix++;
2946 i.prefixes--;
2947 }
2948 if (i.prefix[REX_PREFIX] != 0)
2949 {
2950 prefix++;
2951 i.prefixes--;
2f66722d
AM		 2952 }
2953
29b0f896
AM		 2954 if (i.prefixes != 0 && !intel_syntax)
2955 as_warn (_("skipping prefixes on this instruction"));
2956
2957 /* It's always a symbol; End frag & setup for relax.
2958 Make sure there is enough room in this frag for the largest
2959 instruction we may generate in md_convert_frag. This is 2
2960 bytes for the opcode and room for the prefix and largest
2961 displacement. */
2962 frag_grow (prefix + 2 + 4);
2963 /* Prefix and 1 opcode byte go in fr_fix. */
2964 p = frag_more (prefix + 1);
2965 if (i.prefix[DATA_PREFIX] != 0)
2966 *p++ = DATA_PREFIX_OPCODE;
2967 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
2968 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
2969 *p++ = i.prefix[SEG_PREFIX];
2970 if (i.prefix[REX_PREFIX] != 0)
2971 *p++ = i.prefix[REX_PREFIX];
2972 *p = i.tm.base_opcode;
2973
2974 if ((unsigned char) *p == JUMP_PC_RELATIVE)
2975 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
2976 else if ((cpu_arch_flags & Cpu386) != 0)
2977 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
2978 else
2979 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
2980 subtype |= code16;
3e73aa7c 2981
29b0f896
AM		 2982 sym = i.op[0].disps->X_add_symbol;
2983 off = i.op[0].disps->X_add_number;
3e73aa7c 2984
29b0f896
AM		 2985 if (i.op[0].disps->X_op != O_constant
2986 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 2987 {
29b0f896
AM		 2988 /* Handle complex expressions. */
2989 sym = make_expr_symbol (i.op[0].disps);
2990 off = 0;
2991 }
3e73aa7c 2992
29b0f896
AM		 2993 /* 1 possible extra opcode + 4 byte displacement go in var part.
2994 Pass reloc in fr_var. */
2995 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
2996}
3e73aa7c 2997
29b0f896
AM		 2998static void
2999output_jump ()
3000{
3001 char *p;
3002 int size;
3e02c1cc 3003 fixS *fixP;
29b0f896
AM		 3004
3005 if (i.tm.opcode_modifier & JumpByte)
3006 {
3007 /* This is a loop or jecxz type instruction. */
3008 size = 1;
3009 if (i.prefix[ADDR_PREFIX] != 0)
3010 {
3011 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3012 i.prefixes -= 1;
3013 }
3014 /* Pentium4 branch hints. */
3015 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3016 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3017 {
3018 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3019 i.prefixes--;
3e73aa7c
JH		 3020 }
3021 }
29b0f896
AM		 3022 else
3023 {
3024 int code16;
3e73aa7c 3025
29b0f896
AM		 3026 code16 = 0;
3027 if (flag_code == CODE_16BIT)
3028 code16 = CODE16;
3e73aa7c 3029
29b0f896
AM		 3030 if (i.prefix[DATA_PREFIX] != 0)
3031 {
3032 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3033 i.prefixes -= 1;
3034 code16 ^= CODE16;
3035 }
252b5132 3036
29b0f896
AM		 3037 size = 4;
3038 if (code16)
3039 size = 2;
3040 }
9fcc94b6 3041
29b0f896
AM		 3042 if (i.prefix[REX_PREFIX] != 0)
3043 {
3044 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3045 i.prefixes -= 1;
3046 }
252b5132 3047
29b0f896
AM		 3048 if (i.prefixes != 0 && !intel_syntax)
3049 as_warn (_("skipping prefixes on this instruction"));
e0890092 3050
29b0f896
AM		 3051 p = frag_more (1 + size);
3052 *p++ = i.tm.base_opcode;
e0890092 3053
3e02c1cc
AM		 3054 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3055 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3056
3057 /* All jumps handled here are signed, but don't use a signed limit
3058 check for 32 and 16 bit jumps as we want to allow wrap around at
3059 4G and 64k respectively. */
3060 if (size == 1)
3061 fixP->fx_signed = 1;
29b0f896 3062}
e0890092 3063
29b0f896
AM		 3064static void
3065output_interseg_jump ()
3066{
3067 char *p;
3068 int size;
3069 int prefix;
3070 int code16;
252b5132 3071
29b0f896
AM		 3072 code16 = 0;
3073 if (flag_code == CODE_16BIT)
3074 code16 = CODE16;
a217f122 3075
29b0f896
AM		 3076 prefix = 0;
3077 if (i.prefix[DATA_PREFIX] != 0)
3078 {
3079 prefix = 1;
3080 i.prefixes -= 1;
3081 code16 ^= CODE16;
3082 }
3083 if (i.prefix[REX_PREFIX] != 0)
3084 {
3085 prefix++;
3086 i.prefixes -= 1;
3087 }
252b5132 3088
29b0f896
AM		 3089 size = 4;
3090 if (code16)
3091 size = 2;
252b5132 3092
29b0f896
AM		 3093 if (i.prefixes != 0 && !intel_syntax)
3094 as_warn (_("skipping prefixes on this instruction"));
252b5132 3095
29b0f896
AM		 3096 /* 1 opcode; 2 segment; offset */
3097 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3098
29b0f896
AM		 3099 if (i.prefix[DATA_PREFIX] != 0)
3100 *p++ = DATA_PREFIX_OPCODE;
252b5132 3101
29b0f896
AM		 3102 if (i.prefix[REX_PREFIX] != 0)
3103 *p++ = i.prefix[REX_PREFIX];
252b5132 3104
29b0f896
AM		 3105 *p++ = i.tm.base_opcode;
3106 if (i.op[1].imms->X_op == O_constant)
3107 {
3108 offsetT n = i.op[1].imms->X_add_number;
252b5132 3109
29b0f896
AM		 3110 if (size == 2
3111 && !fits_in_unsigned_word (n)
3112 && !fits_in_signed_word (n))
3113 {
3114 as_bad (_("16-bit jump out of range"));
3115 return;
3116 }
3117 md_number_to_chars (p, n, size);
3118 }
3119 else
3120 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3121 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3122 if (i.op[0].imms->X_op != O_constant)
3123 as_bad (_("can't handle non absolute segment in `%s'"),
3124 i.tm.name);
3125 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3126}
a217f122 3127
2bbd9c25 3128
29b0f896
AM		 3129static void
3130output_insn ()
3131{
2bbd9c25
JJ		 3132 fragS *insn_start_frag;
3133 offsetT insn_start_off;
3134
29b0f896
AM		 3135 /* Tie dwarf2 debug info to the address at the start of the insn.
3136 We can't do this after the insn has been output as the current
3137 frag may have been closed off. eg. by frag_var. */
3138 dwarf2_emit_insn (0);
3139
2bbd9c25
JJ		 3140 insn_start_frag = frag_now;
3141 insn_start_off = frag_now_fix ();
3142
29b0f896
AM		 3143 /* Output jumps. */
3144 if (i.tm.opcode_modifier & Jump)
3145 output_branch ();
3146 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3147 output_jump ();
3148 else if (i.tm.opcode_modifier & JumpInterSegment)
3149 output_interseg_jump ();
3150 else
3151 {
3152 /* Output normal instructions here. */
3153 char *p;
3154 unsigned char *q;
252b5132 3155
29b0f896
AM		 3156 /* All opcodes on i386 have either 1 or 2 bytes. We may use third
3157 byte for the SSE instructions to specify a prefix they require. */
3158 if (i.tm.base_opcode & 0xff0000)
3159 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
252b5132 3160
29b0f896
AM		 3161 /* The prefix bytes. */
3162 for (q = i.prefix;
3163 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3164 q++)
3165 {
3166 if (*q)
3167 {
3168 p = frag_more (1);
3169 md_number_to_chars (p, (valueT) *q, 1);
3170 }
3171 }
252b5132 3172
29b0f896
AM		 3173 /* Now the opcode; be careful about word order here! */
3174 if (fits_in_unsigned_byte (i.tm.base_opcode))
3175 {
3176 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3177 }
3178 else
3179 {
3180 p = frag_more (2);
3181 /* Put out high byte first: can't use md_number_to_chars! */
3182 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3183 *p = i.tm.base_opcode & 0xff;
3184 }
3e73aa7c 3185
29b0f896
AM		 3186 /* Now the modrm byte and sib byte (if present). */
3187 if (i.tm.opcode_modifier & Modrm)
3188 {
3189 p = frag_more (1);
3190 md_number_to_chars (p,
3191 (valueT) (i.rm.regmem << 0
3192 | i.rm.reg << 3
3193 | i.rm.mode << 6),
3194 1);
3195 /* If i.rm.regmem == ESP (4)
3196 && i.rm.mode != (Register mode)
3197 && not 16 bit
3198 ==> need second modrm byte. */
3199 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3200 && i.rm.mode != 3
3201 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3202 {
3203 p = frag_more (1);
3204 md_number_to_chars (p,
3205 (valueT) (i.sib.base << 0
3206 | i.sib.index << 3
3207 | i.sib.scale << 6),
3208 1);
3209 }
3210 }
3e73aa7c 3211
29b0f896 3212 if (i.disp_operands)
2bbd9c25 3213 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3214
29b0f896 3215 if (i.imm_operands)
2bbd9c25 3216 output_imm (insn_start_frag, insn_start_off);
29b0f896 3217 }
252b5132 3218
29b0f896
AM		 3219#ifdef DEBUG386
3220 if (flag_debug)
3221 {
3222 pi (line, &i);
3223 }
3224#endif /* DEBUG386 */
3225}
252b5132 3226
29b0f896 3227static void
2bbd9c25
JJ		 3228output_disp (insn_start_frag, insn_start_off)
3229 fragS *insn_start_frag;
3230 offsetT insn_start_off;
29b0f896
AM		 3231{
3232 char *p;
3233 unsigned int n;
252b5132 3234
29b0f896
AM		 3235 for (n = 0; n < i.operands; n++)
3236 {
3237 if (i.types[n] & Disp)
3238 {
3239 if (i.op[n].disps->X_op == O_constant)
3240 {
3241 int size;
3242 offsetT val;
252b5132 3243
29b0f896
AM		 3244 size = 4;
3245 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3246 {
3247 size = 2;
3248 if (i.types[n] & Disp8)
3249 size = 1;
3250 if (i.types[n] & Disp64)
3251 size = 8;
3252 }
3253 val = offset_in_range (i.op[n].disps->X_add_number,
3254 size);
3255 p = frag_more (size);
3256 md_number_to_chars (p, val, size);
3257 }
3258 else
3259 {
2bbd9c25 3260 RELOC_ENUM reloc_type;
29b0f896
AM		 3261 int size = 4;
3262 int sign = 0;
3263 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3264
3265 /* The PC relative address is computed relative
3266 to the instruction boundary, so in case immediate
3267 fields follows, we need to adjust the value. */
3268 if (pcrel && i.imm_operands)
3269 {
3270 int imm_size = 4;
3271 unsigned int n1;
252b5132 3272
29b0f896
AM		 3273 for (n1 = 0; n1 < i.operands; n1++)
3274 if (i.types[n1] & Imm)
252b5132 3275 {
29b0f896 3276 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 3277 {
29b0f896
AM		 3278 imm_size = 2;
3279 if (i.types[n1] & (Imm8 | Imm8S))
3280 imm_size = 1;
3281 if (i.types[n1] & Imm64)
3282 imm_size = 8;
252b5132 3283 }
29b0f896 3284 break;
252b5132 3285 }
29b0f896
AM		 3286 /* We should find the immediate. */
3287 if (n1 == i.operands)
3288 abort ();
3289 i.op[n].disps->X_add_number -= imm_size;
3290 }
520dc8e8 3291
29b0f896
AM		 3292 if (i.types[n] & Disp32S)
3293 sign = 1;
3e73aa7c 3294
29b0f896
AM		 3295 if (i.types[n] & (Disp16 | Disp64))
3296 {
3297 size = 2;
3298 if (i.types[n] & Disp64)
3299 size = 8;
3300 }
520dc8e8 3301
29b0f896 3302 p = frag_more (size);
2bbd9c25
JJ		 3303 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
3304#ifdef BFD_ASSEMBLER
3305 if (reloc_type == BFD_RELOC_32
3306 && GOT_symbol
3307 && GOT_symbol == i.op[n].disps->X_add_symbol
3308 && (i.op[n].disps->X_op == O_symbol
3309 || (i.op[n].disps->X_op == O_add
3310 && ((symbol_get_value_expression
3311 (i.op[n].disps->X_op_symbol)->X_op)
3312 == O_subtract))))
3313 {
3314 offsetT add;
3315
3316 if (insn_start_frag == frag_now)
3317 add = (p - frag_now->fr_literal) - insn_start_off;
3318 else
3319 {
3320 fragS *fr;
3321
3322 add = insn_start_frag->fr_fix - insn_start_off;
3323 for (fr = insn_start_frag->fr_next;
3324 fr && fr != frag_now; fr = fr->fr_next)
3325 add += fr->fr_fix;
3326 add += p - frag_now->fr_literal;
3327 }
3328
3329 /* We don't support dynamic linking on x86-64 yet. */
3330 if (flag_code == CODE_64BIT)
3331 abort ();
3332 reloc_type = BFD_RELOC_386_GOTPC;
3333 i.op[n].disps->X_add_number += add;
3334 }
3335#endif
062cd5e7 3336 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 3337 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 3338 }
3339 }
3340 }
3341}
252b5132 3342
29b0f896 3343static void
2bbd9c25
JJ		 3344output_imm (insn_start_frag, insn_start_off)
3345 fragS *insn_start_frag;
3346 offsetT insn_start_off;
29b0f896
AM		 3347{
3348 char *p;
3349 unsigned int n;
252b5132 3350
29b0f896
AM		 3351 for (n = 0; n < i.operands; n++)
3352 {
3353 if (i.types[n] & Imm)
3354 {
3355 if (i.op[n].imms->X_op == O_constant)
3356 {
3357 int size;
3358 offsetT val;
b4cac588 3359
29b0f896
AM		 3360 size = 4;
3361 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3362 {
3363 size = 2;
3364 if (i.types[n] & (Imm8 | Imm8S))
3365 size = 1;
3366 else if (i.types[n] & Imm64)
3367 size = 8;
3368 }
3369 val = offset_in_range (i.op[n].imms->X_add_number,
3370 size);
3371 p = frag_more (size);
3372 md_number_to_chars (p, val, size);
3373 }
3374 else
3375 {
3376 /* Not absolute_section.
3377 Need a 32-bit fixup (don't support 8bit
3378 non-absolute imms). Try to support other
3379 sizes ... */
3380 RELOC_ENUM reloc_type;
3381 int size = 4;
3382 int sign = 0;
3383
3384 if ((i.types[n] & (Imm32S))
3385 && i.suffix == QWORD_MNEM_SUFFIX)
3386 sign = 1;
3387 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3388 {
3389 size = 2;
3390 if (i.types[n] & (Imm8 | Imm8S))
3391 size = 1;
3392 if (i.types[n] & Imm64)
3393 size = 8;
3394 }
520dc8e8 3395
29b0f896
AM		 3396 p = frag_more (size);
3397 reloc_type = reloc (size, 0, sign, i.reloc[n]);
252b5132 3398#ifdef BFD_ASSEMBLER
2bbd9c25
JJ		 3399 /* This is tough to explain. We end up with this one if we
3400 * have operands that look like
3401 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3402 * obtain the absolute address of the GOT, and it is strongly
3403 * preferable from a performance point of view to avoid using
3404 * a runtime relocation for this. The actual sequence of
3405 * instructions often look something like:
3406 *
3407 * call .L66
3408 * .L66:
3409 * popl %ebx
3410 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3411 *
3412 * The call and pop essentially return the absolute address
3413 * of the label .L66 and store it in %ebx. The linker itself
3414 * will ultimately change the first operand of the addl so
3415 * that %ebx points to the GOT, but to keep things simple, the
3416 * .o file must have this operand set so that it generates not
3417 * the absolute address of .L66, but the absolute address of
3418 * itself. This allows the linker itself simply treat a GOTPC
3419 * relocation as asking for a pcrel offset to the GOT to be
3420 * added in, and the addend of the relocation is stored in the
3421 * operand field for the instruction itself.
3422 *
3423 * Our job here is to fix the operand so that it would add
3424 * the correct offset so that %ebx would point to itself. The
3425 * thing that is tricky is that .-.L66 will point to the
3426 * beginning of the instruction, so we need to further modify
3427 * the operand so that it will point to itself. There are
3428 * other cases where you have something like:
3429 *
3430 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3431 *
3432 * and here no correction would be required. Internally in
3433 * the assembler we treat operands of this form as not being
3434 * pcrel since the '.' is explicitly mentioned, and I wonder
3435 * whether it would simplify matters to do it this way. Who
3436 * knows. In earlier versions of the PIC patches, the
3437 * pcrel_adjust field was used to store the correction, but
3438 * since the expression is not pcrel, I felt it would be
3439 * confusing to do it this way. */
3440
29b0f896
AM		 3441 if (reloc_type == BFD_RELOC_32
3442 && GOT_symbol
3443 && GOT_symbol == i.op[n].imms->X_add_symbol
3444 && (i.op[n].imms->X_op == O_symbol
3445 || (i.op[n].imms->X_op == O_add
3446 && ((symbol_get_value_expression
3447 (i.op[n].imms->X_op_symbol)->X_op)
3448 == O_subtract))))
3449 {
2bbd9c25
JJ		 3450 offsetT add;
3451
3452 if (insn_start_frag == frag_now)
3453 add = (p - frag_now->fr_literal) - insn_start_off;
3454 else
3455 {
3456 fragS *fr;
3457
3458 add = insn_start_frag->fr_fix - insn_start_off;
3459 for (fr = insn_start_frag->fr_next;
3460 fr && fr != frag_now; fr = fr->fr_next)
3461 add += fr->fr_fix;
3462 add += p - frag_now->fr_literal;
3463 }
3464
29b0f896
AM		 3465 /* We don't support dynamic linking on x86-64 yet. */
3466 if (flag_code == CODE_64BIT)
3467 abort ();
3468 reloc_type = BFD_RELOC_386_GOTPC;
2bbd9c25 3469 i.op[n].imms->X_add_number += add;
29b0f896 3470 }
252b5132 3471#endif
29b0f896
AM		 3472 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3473 i.op[n].imms, 0, reloc_type);
3474 }
3475 }
3476 }
252b5132
RH		 3477}
3478\f
f3c180ae
AM		 3479#ifndef LEX_AT
3480static char *lex_got PARAMS ((RELOC_ENUM *, int *));
3481
3482/* Parse operands of the form
3483 <symbol>@GOTOFF+<nnn>
3484 and similar .plt or .got references.
3485
3486 If we find one, set up the correct relocation in RELOC and copy the
3487 input string, minus the `@GOTOFF' into a malloc'd buffer for
3488 parsing by the calling routine. Return this buffer, and if ADJUST
3489 is non-null set it to the length of the string we removed from the
3490 input line. Otherwise return NULL. */
3491static char *
3492lex_got (reloc, adjust)
3493 RELOC_ENUM *reloc;
3494 int *adjust;
3495{
3496 static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
3497 static const struct {
3498 const char *str;
3499 const RELOC_ENUM rel[NUM_FLAG_CODE];
3500 } gotrel[] = {
13ae64f3
JJ		 3501 { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } },
3502 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } },
3503 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } },
bffbf940 3504 { "TLSGD", { BFD_RELOC_386_TLS_GD, 0, BFD_RELOC_X86_64_TLSGD } },
13ae64f3 3505 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0, 0 } },
bffbf940
JJ		 3506 { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD } },
3507 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 0, BFD_RELOC_X86_64_GOTTPOFF } },
3508 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 0, BFD_RELOC_X86_64_TPOFF32 } },
13ae64f3 3509 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0, 0 } },
bffbf940 3510 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 0, BFD_RELOC_X86_64_DTPOFF32 } },
37e55690
JJ		 3511 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0, 0 } },
3512 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0, 0 } },
13ae64f3 3513 { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } }
f3c180ae
AM		 3514 };
3515 char *cp;
3516 unsigned int j;
3517
3518 for (cp = input_line_pointer; *cp != '@'; cp++)
3519 if (is_end_of_line[(unsigned char) *cp])
3520 return NULL;
3521
3522 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3523 {
3524 int len;
3525
3526 len = strlen (gotrel[j].str);
28f81592 3527 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae
AM		 3528 {
3529 if (gotrel[j].rel[(unsigned int) flag_code] != 0)
3530 {
28f81592
AM		 3531 int first, second;
3532 char *tmpbuf, *past_reloc;
f3c180ae
AM		 3533
3534 *reloc = gotrel[j].rel[(unsigned int) flag_code];
28f81592
AM		 3535 if (adjust)
3536 *adjust = len;
f3c180ae
AM		 3537
3538 if (GOT_symbol == NULL)
3539 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3540
3541 /* Replace the relocation token with ' ', so that
3542 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 3543
3544 /* The length of the first part of our input line. */
f3c180ae 3545 first = cp - input_line_pointer;
28f81592
AM		 3546
3547 /* The second part goes from after the reloc token until
3548 (and including) an end_of_line char. Don't use strlen
3549 here as the end_of_line char may not be a NUL. */
3550 past_reloc = cp + 1 + len;
3551 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3552 ;
3553 second = cp - past_reloc;
3554
3555 /* Allocate and copy string. The trailing NUL shouldn't
3556 be necessary, but be safe. */
3557 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 3558 memcpy (tmpbuf, input_line_pointer, first);
3559 tmpbuf[first] = ' ';
28f81592
AM		 3560 memcpy (tmpbuf + first + 1, past_reloc, second);
3561 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 3562 return tmpbuf;
3563 }
3564
3565 as_bad (_("@%s reloc is not supported in %s bit mode"),
3566 gotrel[j].str, mode_name[(unsigned int) flag_code]);
3567 return NULL;
3568 }
3569 }
3570
3571 /* Might be a symbol version string. Don't as_bad here. */
3572 return NULL;
3573}
3574
3575/* x86_cons_fix_new is called via the expression parsing code when a
3576 reloc is needed. We use this hook to get the correct .got reloc. */
3577static RELOC_ENUM got_reloc = NO_RELOC;
3578
3579void
3580x86_cons_fix_new (frag, off, len, exp)
3581 fragS *frag;
3582 unsigned int off;
3583 unsigned int len;
3584 expressionS *exp;
3585{
3586 RELOC_ENUM r = reloc (len, 0, 0, got_reloc);
3587 got_reloc = NO_RELOC;
3588 fix_new_exp (frag, off, len, exp, 0, r);
3589}
3590
3591void
3592x86_cons (exp, size)
3593 expressionS *exp;
3594 int size;
3595{
3596 if (size == 4)
3597 {
3598 /* Handle @GOTOFF and the like in an expression. */
3599 char *save;
3600 char *gotfree_input_line;
3601 int adjust;
3602
3603 save = input_line_pointer;
3604 gotfree_input_line = lex_got (&got_reloc, &adjust);
3605 if (gotfree_input_line)
3606 input_line_pointer = gotfree_input_line;
3607
3608 expression (exp);
3609
3610 if (gotfree_input_line)
3611 {
3612 /* expression () has merrily parsed up to the end of line,
3613 or a comma - in the wrong buffer. Transfer how far
3614 input_line_pointer has moved to the right buffer. */
3615 input_line_pointer = (save
3616 + (input_line_pointer - gotfree_input_line)
3617 + adjust);
3618 free (gotfree_input_line);
3619 }
3620 }
3621 else
3622 expression (exp);
3623}
3624#endif
3625
252b5132
RH		 3626static int i386_immediate PARAMS ((char *));
3627
3628static int
3629i386_immediate (imm_start)
3630 char *imm_start;
3631{
3632 char *save_input_line_pointer;
f3c180ae
AM		 3633#ifndef LEX_AT
3634 char *gotfree_input_line;
3635#endif
252b5132 3636 segT exp_seg = 0;
47926f60 3637 expressionS *exp;
252b5132
RH		 3638
3639 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3640 {
d0b47220 3641 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 3642 return 0;
3643 }
3644
3645 exp = &im_expressions[i.imm_operands++];
520dc8e8 3646 i.op[this_operand].imms = exp;
252b5132
RH		 3647
3648 if (is_space_char (*imm_start))
3649 ++imm_start;
3650
3651 save_input_line_pointer = input_line_pointer;
3652 input_line_pointer = imm_start;
3653
3654#ifndef LEX_AT
f3c180ae
AM		 3655 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3656 if (gotfree_input_line)
3657 input_line_pointer = gotfree_input_line;
252b5132
RH		 3658#endif
3659
3660 exp_seg = expression (exp);
3661
83183c0c 3662 SKIP_WHITESPACE ();
252b5132 3663 if (*input_line_pointer)
f3c180ae 3664 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 3665
3666 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 3667#ifndef LEX_AT
3668 if (gotfree_input_line)
3669 free (gotfree_input_line);
3670#endif
252b5132 3671
2daf4fd8 3672 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 3673 {
47926f60 3674 /* Missing or bad expr becomes absolute 0. */
d0b47220 3675 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 3676 imm_start);
252b5132
RH		 3677 exp->X_op = O_constant;
3678 exp->X_add_number = 0;
3679 exp->X_add_symbol = (symbolS *) 0;
3680 exp->X_op_symbol = (symbolS *) 0;
252b5132 3681 }
3e73aa7c 3682 else if (exp->X_op == O_constant)
252b5132 3683 {
47926f60 3684 /* Size it properly later. */
3e73aa7c
JH		 3685 i.types[this_operand] |= Imm64;
3686 /* If BFD64, sign extend val. */
3687 if (!use_rela_relocations)
3688 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
3689 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 3690 }
4c63da97 3691#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
47926f60 3692 else if (1
4c63da97 3693#ifdef BFD_ASSEMBLER
47926f60 3694 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4c63da97 3695#endif
31312f95 3696 && exp_seg != absolute_section
47926f60 3697 && exp_seg != text_section
24eab124
AM		 3698 && exp_seg != data_section
3699 && exp_seg != bss_section
3700 && exp_seg != undefined_section
252b5132 3701#ifdef BFD_ASSEMBLER
24eab124 3702 && !bfd_is_com_section (exp_seg)
252b5132 3703#endif
24eab124 3704 )
252b5132 3705 {
4c63da97 3706#ifdef BFD_ASSEMBLER
d0b47220 3707 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4c63da97 3708#else
d0b47220 3709 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
4c63da97 3710#endif
252b5132
RH		 3711 return 0;
3712 }
3713#endif
3714 else
3715 {
3716 /* This is an address. The size of the address will be
24eab124 3717 determined later, depending on destination register,
3e73aa7c
JH		 3718 suffix, or the default for the section. */
3719 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
252b5132
RH		 3720 }
3721
3722 return 1;
3723}
3724
551c1ca1 3725static char *i386_scale PARAMS ((char *));
252b5132 3726
551c1ca1 3727static char *
252b5132
RH		 3728i386_scale (scale)
3729 char *scale;
3730{
551c1ca1
AM		 3731 offsetT val;
3732 char *save = input_line_pointer;
252b5132 3733
551c1ca1
AM		 3734 input_line_pointer = scale;
3735 val = get_absolute_expression ();
3736
3737 switch (val)
252b5132 3738 {
551c1ca1
AM		 3739 case 0:
3740 case 1:
252b5132
RH		 3741 i.log2_scale_factor = 0;
3742 break;
551c1ca1 3743 case 2:
252b5132
RH		 3744 i.log2_scale_factor = 1;
3745 break;
551c1ca1 3746 case 4:
252b5132
RH		 3747 i.log2_scale_factor = 2;
3748 break;
551c1ca1 3749 case 8:
252b5132
RH		 3750 i.log2_scale_factor = 3;
3751 break;
3752 default:
252b5132 3753 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
24eab124 3754 scale);
551c1ca1
AM		 3755 input_line_pointer = save;
3756 return NULL;
252b5132 3757 }
29b0f896 3758 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 3759 {
3760 as_warn (_("scale factor of %d without an index register"),
24eab124 3761 1 << i.log2_scale_factor);
252b5132
RH		 3762#if SCALE1_WHEN_NO_INDEX
3763 i.log2_scale_factor = 0;
3764#endif
3765 }
551c1ca1
AM		 3766 scale = input_line_pointer;
3767 input_line_pointer = save;
3768 return scale;
252b5132
RH		 3769}
3770
3771static int i386_displacement PARAMS ((char *, char *));
3772
3773static int
3774i386_displacement (disp_start, disp_end)
3775 char *disp_start;
3776 char *disp_end;
3777{
29b0f896 3778 expressionS *exp;
252b5132
RH		 3779 segT exp_seg = 0;
3780 char *save_input_line_pointer;
f3c180ae
AM		 3781#ifndef LEX_AT
3782 char *gotfree_input_line;
3783#endif
252b5132
RH		 3784 int bigdisp = Disp32;
3785
3e73aa7c 3786 if (flag_code == CODE_64BIT)
7ecd2f8b 3787 {
29b0f896
AM		 3788 if (i.prefix[ADDR_PREFIX] == 0)
3789 bigdisp = Disp64;
7ecd2f8b
JH		 3790 }
3791 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3792 bigdisp = Disp16;
252b5132
RH		 3793 i.types[this_operand] |= bigdisp;
3794
3795 exp = &disp_expressions[i.disp_operands];
520dc8e8 3796 i.op[this_operand].disps = exp;
252b5132
RH		 3797 i.disp_operands++;
3798 save_input_line_pointer = input_line_pointer;
3799 input_line_pointer = disp_start;
3800 END_STRING_AND_SAVE (disp_end);
3801
3802#ifndef GCC_ASM_O_HACK
3803#define GCC_ASM_O_HACK 0
3804#endif
3805#if GCC_ASM_O_HACK
3806 END_STRING_AND_SAVE (disp_end + 1);
3807 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 3808 && displacement_string_end[-1] == '+')
252b5132
RH		 3809 {
3810 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 3811 constraint within gcc asm statements.
3812 For instance:
3813
3814 #define _set_tssldt_desc(n,addr,limit,type) \
3815 __asm__ __volatile__ ( \
3816 "movw %w2,%0\n\t" \
3817 "movw %w1,2+%0\n\t" \
3818 "rorl $16,%1\n\t" \
3819 "movb %b1,4+%0\n\t" \
3820 "movb %4,5+%0\n\t" \
3821 "movb $0,6+%0\n\t" \
3822 "movb %h1,7+%0\n\t" \
3823 "rorl $16,%1" \
3824 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3825
3826 This works great except that the output assembler ends
3827 up looking a bit weird if it turns out that there is
3828 no offset. You end up producing code that looks like:
3829
3830 #APP
3831 movw $235,(%eax)
3832 movw %dx,2+(%eax)
3833 rorl $16,%edx
3834 movb %dl,4+(%eax)
3835 movb $137,5+(%eax)
3836 movb $0,6+(%eax)
3837 movb %dh,7+(%eax)
3838 rorl $16,%edx
3839 #NO_APP
3840
47926f60 3841 So here we provide the missing zero. */
24eab124
AM		 3842
3843 *displacement_string_end = '0';
252b5132
RH		 3844 }
3845#endif
3846#ifndef LEX_AT
f3c180ae
AM		 3847 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3848 if (gotfree_input_line)
3849 input_line_pointer = gotfree_input_line;
252b5132
RH		 3850#endif
3851
24eab124 3852 exp_seg = expression (exp);
252b5132 3853
636c26b0
AM		 3854 SKIP_WHITESPACE ();
3855 if (*input_line_pointer)
3856 as_bad (_("junk `%s' after expression"), input_line_pointer);
3857#if GCC_ASM_O_HACK
3858 RESTORE_END_STRING (disp_end + 1);
3859#endif
3860 RESTORE_END_STRING (disp_end);
3861 input_line_pointer = save_input_line_pointer;
3862#ifndef LEX_AT
3863 if (gotfree_input_line)
3864 free (gotfree_input_line);
3865#endif
3866
252b5132 3867#ifdef BFD_ASSEMBLER
24eab124
AM		 3868 /* We do this to make sure that the section symbol is in
3869 the symbol table. We will ultimately change the relocation
47926f60 3870 to be relative to the beginning of the section. */
1ae12ab7
AM		 3871 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
3872 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
24eab124 3873 {
636c26b0
AM		 3874 if (exp->X_op != O_symbol)
3875 {
3876 as_bad (_("bad expression used with @%s"),
3877 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
3878 ? "GOTPCREL"
3879 : "GOTOFF"));
3880 return 0;
3881 }
3882
e5cb08ac 3883 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 3884 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
3885 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 3886 exp->X_op = O_subtract;
3887 exp->X_op_symbol = GOT_symbol;
1ae12ab7 3888 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 3889 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
23df1078 3890 else
29b0f896 3891 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 3892 }
252b5132
RH		 3893#endif
3894
2daf4fd8
AM		 3895 if (exp->X_op == O_absent || exp->X_op == O_big)
3896 {
47926f60 3897 /* Missing or bad expr becomes absolute 0. */
d0b47220 3898 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 3899 disp_start);
3900 exp->X_op = O_constant;
3901 exp->X_add_number = 0;
3902 exp->X_add_symbol = (symbolS *) 0;
3903 exp->X_op_symbol = (symbolS *) 0;
3904 }
3905
4c63da97 3906#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 3907 if (exp->X_op != O_constant
4c63da97 3908#ifdef BFD_ASSEMBLER
45288df1 3909 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4c63da97 3910#endif
31312f95 3911 && exp_seg != absolute_section
45288df1
AM		 3912 && exp_seg != text_section
3913 && exp_seg != data_section
3914 && exp_seg != bss_section
31312f95
AM		 3915 && exp_seg != undefined_section
3916#ifdef BFD_ASSEMBLER
3917 && !bfd_is_com_section (exp_seg)
3918#endif
3919 )
24eab124 3920 {
4c63da97 3921#ifdef BFD_ASSEMBLER
d0b47220 3922 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4c63da97 3923#else
d0b47220 3924 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
4c63da97 3925#endif
24eab124
AM		 3926 return 0;
3927 }
252b5132 3928#endif
3e73aa7c
JH		 3929 else if (flag_code == CODE_64BIT)
3930 i.types[this_operand] |= Disp32S | Disp32;
252b5132
RH		 3931 return 1;
3932}
3933
e5cb08ac 3934static int i386_index_check PARAMS ((const char *));
252b5132 3935
eecb386c 3936/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 3937 Return 1 on success, 0 on a failure. */
3938
252b5132 3939static int
eecb386c
AM		 3940i386_index_check (operand_string)
3941 const char *operand_string;
252b5132 3942{
3e73aa7c 3943 int ok;
24eab124 3944#if INFER_ADDR_PREFIX
eecb386c
AM		 3945 int fudged = 0;
3946
24eab124
AM		 3947 tryprefix:
3948#endif
3e73aa7c
JH		 3949 ok = 1;
3950 if (flag_code == CODE_64BIT)
3951 {
7ecd2f8b
JH		 3952 if (i.prefix[ADDR_PREFIX] == 0)
3953 {
3954 /* 64bit checks. */
3955 if ((i.base_reg
3956 && ((i.base_reg->reg_type & Reg64) == 0)
3957 && (i.base_reg->reg_type != BaseIndex
3958 || i.index_reg))
3959 || (i.index_reg
29b0f896
AM		 3960 && ((i.index_reg->reg_type & (Reg64 | BaseIndex))
3961 != (Reg64 | BaseIndex))))
7ecd2f8b
JH		 3962 ok = 0;
3963 }
3964 else
3965 {
3966 /* 32bit checks. */
3967 if ((i.base_reg
3968 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3969 || (i.index_reg
29b0f896
AM		 3970 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
3971 != (Reg32 | BaseIndex))))
7ecd2f8b
JH		 3972 ok = 0;
3973 }
3e73aa7c
JH		 3974 }
3975 else
3976 {
3977 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3978 {
3979 /* 16bit checks. */
3980 if ((i.base_reg
29b0f896
AM		 3981 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
3982 != (Reg16 | BaseIndex)))
3e73aa7c 3983 || (i.index_reg
29b0f896
AM		 3984 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
3985 != (Reg16 | BaseIndex))
3986 || !(i.base_reg
3987 && i.base_reg->reg_num < 6
3988 && i.index_reg->reg_num >= 6
3989 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 3990 ok = 0;
3991 }
3992 else
e5cb08ac 3993 {
3e73aa7c
JH		 3994 /* 32bit checks. */
3995 if ((i.base_reg
3996 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3997 || (i.index_reg
29b0f896
AM		 3998 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
3999 != (Reg32 | BaseIndex))))
e5cb08ac 4000 ok = 0;
3e73aa7c
JH		 4001 }
4002 }
4003 if (!ok)
24eab124
AM		 4004 {
4005#if INFER_ADDR_PREFIX
3e73aa7c
JH		 4006 if (flag_code != CODE_64BIT
4007 && i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0')
24eab124
AM		 4008 {
4009 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4010 i.prefixes += 1;
b23bac36
AM		 4011 /* Change the size of any displacement too. At most one of
4012 Disp16 or Disp32 is set.
4013 FIXME. There doesn't seem to be any real need for separate
4014 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4015 Removing them would probably clean up the code quite a lot. */
29b0f896
AM		 4016 if (i.types[this_operand] & (Disp16 | Disp32))
4017 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4018 fudged = 1;
24eab124
AM		 4019 goto tryprefix;
4020 }
eecb386c
AM		 4021 if (fudged)
4022 as_bad (_("`%s' is not a valid base/index expression"),
4023 operand_string);
4024 else
c388dee8 4025#endif
eecb386c
AM		 4026 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4027 operand_string,
3e73aa7c 4028 flag_code_names[flag_code]);
eecb386c 4029 return 0;
24eab124
AM		 4030 }
4031 return 1;
4032}
252b5132 4033
252b5132 4034/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4035 on error. */
252b5132 4036
252b5132
RH		 4037static int
4038i386_operand (operand_string)
4039 char *operand_string;
4040{
af6bdddf
AM		 4041 const reg_entry *r;
4042 char *end_op;
24eab124 4043 char *op_string = operand_string;
252b5132 4044
24eab124 4045 if (is_space_char (*op_string))
252b5132
RH		 4046 ++op_string;
4047
24eab124 4048 /* We check for an absolute prefix (differentiating,
47926f60 4049 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4050 if (*op_string == ABSOLUTE_PREFIX)
4051 {
4052 ++op_string;
4053 if (is_space_char (*op_string))
4054 ++op_string;
4055 i.types[this_operand] |= JumpAbsolute;
4056 }
252b5132 4057
47926f60 4058 /* Check if operand is a register. */
af6bdddf
AM		 4059 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
4060 && (r = parse_register (op_string, &end_op)) != NULL)
24eab124 4061 {
24eab124
AM		 4062 /* Check for a segment override by searching for ':' after a
4063 segment register. */
4064 op_string = end_op;
4065 if (is_space_char (*op_string))
4066 ++op_string;
4067 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4068 {
4069 switch (r->reg_num)
4070 {
4071 case 0:
4072 i.seg[i.mem_operands] = &es;
4073 break;
4074 case 1:
4075 i.seg[i.mem_operands] = &cs;
4076 break;
4077 case 2:
4078 i.seg[i.mem_operands] = &ss;
4079 break;
4080 case 3:
4081 i.seg[i.mem_operands] = &ds;
4082 break;
4083 case 4:
4084 i.seg[i.mem_operands] = &fs;
4085 break;
4086 case 5:
4087 i.seg[i.mem_operands] = &gs;
4088 break;
4089 }
252b5132 4090
24eab124 4091 /* Skip the ':' and whitespace. */
252b5132
RH		 4092 ++op_string;
4093 if (is_space_char (*op_string))
24eab124 4094 ++op_string;
252b5132 4095
24eab124
AM		 4096 if (!is_digit_char (*op_string)
4097 && !is_identifier_char (*op_string)
4098 && *op_string != '('
4099 && *op_string != ABSOLUTE_PREFIX)
4100 {
4101 as_bad (_("bad memory operand `%s'"), op_string);
4102 return 0;
4103 }
47926f60 4104 /* Handle case of %es:*foo. */
24eab124
AM		 4105 if (*op_string == ABSOLUTE_PREFIX)
4106 {
4107 ++op_string;
4108 if (is_space_char (*op_string))
4109 ++op_string;
4110 i.types[this_operand] |= JumpAbsolute;
4111 }
4112 goto do_memory_reference;
4113 }
4114 if (*op_string)
4115 {
d0b47220 4116 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4117 return 0;
4118 }
4119 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 4120 i.op[this_operand].regs = r;
24eab124
AM		 4121 i.reg_operands++;
4122 }
af6bdddf
AM		 4123 else if (*op_string == REGISTER_PREFIX)
4124 {
4125 as_bad (_("bad register name `%s'"), op_string);
4126 return 0;
4127 }
24eab124 4128 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 4129 {
24eab124
AM		 4130 ++op_string;
4131 if (i.types[this_operand] & JumpAbsolute)
4132 {
d0b47220 4133 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4134 return 0;
4135 }
4136 if (!i386_immediate (op_string))
4137 return 0;
4138 }
4139 else if (is_digit_char (*op_string)
4140 || is_identifier_char (*op_string)
e5cb08ac 4141 || *op_string == '(')
24eab124 4142 {
47926f60 4143 /* This is a memory reference of some sort. */
af6bdddf 4144 char *base_string;
252b5132 4145
47926f60 4146 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 4147 char *displacement_string_start;
4148 char *displacement_string_end;
252b5132 4149
24eab124 4150 do_memory_reference:
24eab124
AM		 4151 if ((i.mem_operands == 1
4152 && (current_templates->start->opcode_modifier & IsString) == 0)
4153 || i.mem_operands == 2)
4154 {
4155 as_bad (_("too many memory references for `%s'"),
4156 current_templates->start->name);
4157 return 0;
4158 }
252b5132 4159
24eab124
AM		 4160 /* Check for base index form. We detect the base index form by
4161 looking for an ')' at the end of the operand, searching
4162 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4163 after the '('. */
af6bdddf 4164 base_string = op_string + strlen (op_string);
c3332e24 4165
af6bdddf
AM		 4166 --base_string;
4167 if (is_space_char (*base_string))
4168 --base_string;
252b5132 4169
47926f60 4170 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 4171 displacement_string_start = op_string;
4172 displacement_string_end = base_string + 1;
252b5132 4173
24eab124
AM		 4174 if (*base_string == ')')
4175 {
af6bdddf 4176 char *temp_string;
24eab124
AM		 4177 unsigned int parens_balanced = 1;
4178 /* We've already checked that the number of left & right ()'s are
47926f60 4179 equal, so this loop will not be infinite. */
24eab124
AM		 4180 do
4181 {
4182 base_string--;
4183 if (*base_string == ')')
4184 parens_balanced++;
4185 if (*base_string == '(')
4186 parens_balanced--;
4187 }
4188 while (parens_balanced);
c3332e24 4189
af6bdddf 4190 temp_string = base_string;
c3332e24 4191
24eab124 4192 /* Skip past '(' and whitespace. */
252b5132
RH		 4193 ++base_string;
4194 if (is_space_char (*base_string))
24eab124 4195 ++base_string;
252b5132 4196
af6bdddf
AM		 4197 if (*base_string == ','
4198 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4199 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 4200 {
af6bdddf 4201 displacement_string_end = temp_string;
252b5132 4202
af6bdddf 4203 i.types[this_operand] |= BaseIndex;
252b5132 4204
af6bdddf 4205 if (i.base_reg)
24eab124 4206 {
24eab124
AM		 4207 base_string = end_op;
4208 if (is_space_char (*base_string))
4209 ++base_string;
af6bdddf
AM		 4210 }
4211
4212 /* There may be an index reg or scale factor here. */
4213 if (*base_string == ',')
4214 {
4215 ++base_string;
4216 if (is_space_char (*base_string))
4217 ++base_string;
4218
4219 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4220 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 4221 {
af6bdddf 4222 base_string = end_op;
24eab124
AM		 4223 if (is_space_char (*base_string))
4224 ++base_string;
af6bdddf
AM		 4225 if (*base_string == ',')
4226 {
4227 ++base_string;
4228 if (is_space_char (*base_string))
4229 ++base_string;
4230 }
e5cb08ac 4231 else if (*base_string != ')')
af6bdddf
AM		 4232 {
4233 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4234 operand_string);
4235 return 0;
4236 }
24eab124 4237 }
af6bdddf 4238 else if (*base_string == REGISTER_PREFIX)
24eab124 4239 {
af6bdddf 4240 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 4241 return 0;
4242 }
252b5132 4243
47926f60 4244 /* Check for scale factor. */
551c1ca1 4245 if (*base_string != ')')
af6bdddf 4246 {
551c1ca1
AM		 4247 char *end_scale = i386_scale (base_string);
4248
4249 if (!end_scale)
af6bdddf 4250 return 0;
24eab124 4251
551c1ca1 4252 base_string = end_scale;
af6bdddf
AM		 4253 if (is_space_char (*base_string))
4254 ++base_string;
4255 if (*base_string != ')')
4256 {
4257 as_bad (_("expecting `)' after scale factor in `%s'"),
4258 operand_string);
4259 return 0;
4260 }
4261 }
4262 else if (!i.index_reg)
24eab124 4263 {
af6bdddf
AM		 4264 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4265 *base_string);
24eab124
AM		 4266 return 0;
4267 }
4268 }
af6bdddf 4269 else if (*base_string != ')')
24eab124 4270 {
af6bdddf
AM		 4271 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4272 operand_string);
24eab124
AM		 4273 return 0;
4274 }
c3332e24 4275 }
af6bdddf 4276 else if (*base_string == REGISTER_PREFIX)
c3332e24 4277 {
af6bdddf 4278 as_bad (_("bad register name `%s'"), base_string);
24eab124 4279 return 0;
c3332e24 4280 }
24eab124
AM		 4281 }
4282
4283 /* If there's an expression beginning the operand, parse it,
4284 assuming displacement_string_start and
4285 displacement_string_end are meaningful. */
4286 if (displacement_string_start != displacement_string_end)
4287 {
4288 if (!i386_displacement (displacement_string_start,
4289 displacement_string_end))
4290 return 0;
4291 }
4292
4293 /* Special case for (%dx) while doing input/output op. */
4294 if (i.base_reg
4295 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4296 && i.index_reg == 0
4297 && i.log2_scale_factor == 0
4298 && i.seg[i.mem_operands] == 0
4299 && (i.types[this_operand] & Disp) == 0)
4300 {
4301 i.types[this_operand] = InOutPortReg;
4302 return 1;
4303 }
4304
eecb386c
AM		 4305 if (i386_index_check (operand_string) == 0)
4306 return 0;
24eab124
AM		 4307 i.mem_operands++;
4308 }
4309 else
ce8a8b2f
AM		 4310 {
4311 /* It's not a memory operand; argh! */
24eab124
AM		 4312 as_bad (_("invalid char %s beginning operand %d `%s'"),
4313 output_invalid (*op_string),
4314 this_operand + 1,
4315 op_string);
4316 return 0;
4317 }
47926f60 4318 return 1; /* Normal return. */
252b5132
RH		 4319}
4320\f
ee7fcc42
AM		 4321/* md_estimate_size_before_relax()
4322
4323 Called just before relax() for rs_machine_dependent frags. The x86
4324 assembler uses these frags to handle variable size jump
4325 instructions.
4326
4327 Any symbol that is now undefined will not become defined.
4328 Return the correct fr_subtype in the frag.
4329 Return the initial "guess for variable size of frag" to caller.
4330 The guess is actually the growth beyond the fixed part. Whatever
4331 we do to grow the fixed or variable part contributes to our
4332 returned value. */
4333
252b5132
RH		 4334int
4335md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 4336 fragS *fragP;
4337 segT segment;
252b5132 4338{
252b5132 4339 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 4340 check for un-relaxable symbols. On an ELF system, we can't relax
4341 an externally visible symbol, because it may be overridden by a
4342 shared library. */
4343 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 4344#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
31312f95
AM		 4345 || (OUTPUT_FLAVOR == bfd_target_elf_flavour
4346 && (S_IS_EXTERNAL (fragP->fr_symbol)
4347 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 4348#endif
4349 )
252b5132 4350 {
b98ef147
AM		 4351 /* Symbol is undefined in this segment, or we need to keep a
4352 reloc so that weak symbols can be overridden. */
4353 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f3c180ae 4354 RELOC_ENUM reloc_type;
ee7fcc42
AM		 4355 unsigned char *opcode;
4356 int old_fr_fix;
f6af82bd 4357
ee7fcc42
AM		 4358 if (fragP->fr_var != NO_RELOC)
4359 reloc_type = fragP->fr_var;
b98ef147 4360 else if (size == 2)
f6af82bd
AM		 4361 reloc_type = BFD_RELOC_16_PCREL;
4362 else
4363 reloc_type = BFD_RELOC_32_PCREL;
252b5132 4364
ee7fcc42
AM		 4365 old_fr_fix = fragP->fr_fix;
4366 opcode = (unsigned char *) fragP->fr_opcode;
4367
fddf5b5b 4368 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 4369 {
fddf5b5b
AM		 4370 case UNCOND_JUMP:
4371 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 4372 opcode[0] = 0xe9;
252b5132 4373 fragP->fr_fix += size;
062cd5e7
AS		 4374 fix_new (fragP, old_fr_fix, size,
4375 fragP->fr_symbol,
4376 fragP->fr_offset, 1,
4377 reloc_type);
252b5132
RH		 4378 break;
4379
fddf5b5b 4380 case COND_JUMP86:
412167cb
AM		 4381 if (size == 2
4382 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 4383 {
4384 /* Negate the condition, and branch past an
4385 unconditional jump. */
4386 opcode[0] ^= 1;
4387 opcode[1] = 3;
4388 /* Insert an unconditional jump. */
4389 opcode[2] = 0xe9;
4390 /* We added two extra opcode bytes, and have a two byte
4391 offset. */
4392 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 4393 fix_new (fragP, old_fr_fix + 2, 2,
4394 fragP->fr_symbol,
4395 fragP->fr_offset, 1,
4396 reloc_type);
fddf5b5b
AM		 4397 break;
4398 }
4399 /* Fall through. */
4400
4401 case COND_JUMP:
412167cb
AM		 4402 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4403 {
3e02c1cc
AM		 4404 fixS *fixP;
4405
412167cb 4406 fragP->fr_fix += 1;
3e02c1cc
AM		 4407 fixP = fix_new (fragP, old_fr_fix, 1,
4408 fragP->fr_symbol,
4409 fragP->fr_offset, 1,
4410 BFD_RELOC_8_PCREL);
4411 fixP->fx_signed = 1;
412167cb
AM		 4412 break;
4413 }
93c2a809 4414
24eab124 4415 /* This changes the byte-displacement jump 0x7N
fddf5b5b 4416 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 4417 opcode[1] = opcode[0] + 0x10;
f6af82bd 4418 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 4419 /* We've added an opcode byte. */
4420 fragP->fr_fix += 1 + size;
062cd5e7
AS		 4421 fix_new (fragP, old_fr_fix + 1, size,
4422 fragP->fr_symbol,
4423 fragP->fr_offset, 1,
4424 reloc_type);
252b5132 4425 break;
fddf5b5b
AM		 4426
4427 default:
4428 BAD_CASE (fragP->fr_subtype);
4429 break;
252b5132
RH		 4430 }
4431 frag_wane (fragP);
ee7fcc42 4432 return fragP->fr_fix - old_fr_fix;
252b5132 4433 }
93c2a809 4434
93c2a809
AM		 4435 /* Guess size depending on current relax state. Initially the relax
4436 state will correspond to a short jump and we return 1, because
4437 the variable part of the frag (the branch offset) is one byte
4438 long. However, we can relax a section more than once and in that
4439 case we must either set fr_subtype back to the unrelaxed state,
4440 or return the value for the appropriate branch. */
4441 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 4442}
4443
47926f60
KH		 4444/* Called after relax() is finished.
4445
4446 In: Address of frag.
4447 fr_type == rs_machine_dependent.
4448 fr_subtype is what the address relaxed to.
4449
4450 Out: Any fixSs and constants are set up.
4451 Caller will turn frag into a ".space 0". */
4452
252b5132
RH		 4453#ifndef BFD_ASSEMBLER
4454void
4455md_convert_frag (headers, sec, fragP)
a04b544b
ILT		 4456 object_headers *headers ATTRIBUTE_UNUSED;
4457 segT sec ATTRIBUTE_UNUSED;
29b0f896 4458 fragS *fragP;
252b5132
RH		 4459#else
4460void
4461md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 4462 bfd *abfd ATTRIBUTE_UNUSED;
4463 segT sec ATTRIBUTE_UNUSED;
29b0f896 4464 fragS *fragP;
252b5132
RH		 4465#endif
4466{
29b0f896 4467 unsigned char *opcode;
252b5132 4468 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 4469 offsetT target_address;
4470 offsetT opcode_address;
252b5132 4471 unsigned int extension = 0;
847f7ad4 4472 offsetT displacement_from_opcode_start;
252b5132
RH		 4473
4474 opcode = (unsigned char *) fragP->fr_opcode;
4475
47926f60 4476 /* Address we want to reach in file space. */
252b5132 4477 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 4478
47926f60 4479 /* Address opcode resides at in file space. */
252b5132
RH		 4480 opcode_address = fragP->fr_address + fragP->fr_fix;
4481
47926f60 4482 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 4483 displacement_from_opcode_start = target_address - opcode_address;
4484
fddf5b5b 4485 if ((fragP->fr_subtype & BIG) == 0)
252b5132 4486 {
47926f60
KH		 4487 /* Don't have to change opcode. */
4488 extension = 1; /* 1 opcode + 1 displacement */
252b5132 4489 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 4490 }
4491 else
4492 {
4493 if (no_cond_jump_promotion
4494 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4495 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 4496
fddf5b5b
AM		 4497 switch (fragP->fr_subtype)
4498 {
4499 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4500 extension = 4; /* 1 opcode + 4 displacement */
4501 opcode[0] = 0xe9;
4502 where_to_put_displacement = &opcode[1];
4503 break;
252b5132 4504
fddf5b5b
AM		 4505 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4506 extension = 2; /* 1 opcode + 2 displacement */
4507 opcode[0] = 0xe9;
4508 where_to_put_displacement = &opcode[1];
4509 break;
252b5132 4510
fddf5b5b
AM		 4511 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4512 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4513 extension = 5; /* 2 opcode + 4 displacement */
4514 opcode[1] = opcode[0] + 0x10;
4515 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4516 where_to_put_displacement = &opcode[2];
4517 break;
252b5132 4518
fddf5b5b
AM		 4519 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4520 extension = 3; /* 2 opcode + 2 displacement */
4521 opcode[1] = opcode[0] + 0x10;
4522 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4523 where_to_put_displacement = &opcode[2];
4524 break;
252b5132 4525
fddf5b5b
AM		 4526 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4527 extension = 4;
4528 opcode[0] ^= 1;
4529 opcode[1] = 3;
4530 opcode[2] = 0xe9;
4531 where_to_put_displacement = &opcode[3];
4532 break;
4533
4534 default:
4535 BAD_CASE (fragP->fr_subtype);
4536 break;
4537 }
252b5132 4538 }
fddf5b5b 4539
47926f60 4540 /* Now put displacement after opcode. */
252b5132
RH		 4541 md_number_to_chars ((char *) where_to_put_displacement,
4542 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 4543 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 4544 fragP->fr_fix += extension;
4545}
4546\f
47926f60
KH		 4547/* Size of byte displacement jmp. */
4548int md_short_jump_size = 2;
4549
4550/* Size of dword displacement jmp. */
4551int md_long_jump_size = 5;
252b5132 4552
47926f60
KH		 4553/* Size of relocation record. */
4554const int md_reloc_size = 8;
252b5132
RH		 4555
4556void
4557md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4558 char *ptr;
4559 addressT from_addr, to_addr;
ab9da554
ILT		 4560 fragS *frag ATTRIBUTE_UNUSED;
4561 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4562{
847f7ad4 4563 offsetT offset;
252b5132
RH		 4564
4565 offset = to_addr - (from_addr + 2);
47926f60
KH		 4566 /* Opcode for byte-disp jump. */
4567 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 4568 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4569}
4570
4571void
4572md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4573 char *ptr;
4574 addressT from_addr, to_addr;
a38cf1db
AM		 4575 fragS *frag ATTRIBUTE_UNUSED;
4576 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4577{
847f7ad4 4578 offsetT offset;
252b5132 4579
a38cf1db
AM		 4580 offset = to_addr - (from_addr + 5);
4581 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4582 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 4583}
4584\f
4585/* Apply a fixup (fixS) to segment data, once it has been determined
4586 by our caller that we have all the info we need to fix it up.
4587
4588 On the 386, immediates, displacements, and data pointers are all in
4589 the same (little-endian) format, so we don't need to care about which
4590 we are handling. */
4591
94f592af
NC		 4592void
4593md_apply_fix3 (fixP, valP, seg)
47926f60
KH		 4594 /* The fix we're to put in. */
4595 fixS *fixP;
47926f60 4596 /* Pointer to the value of the bits. */
c6682705 4597 valueT *valP;
47926f60
KH		 4598 /* Segment fix is from. */
4599 segT seg ATTRIBUTE_UNUSED;
252b5132 4600{
94f592af 4601 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 4602 valueT value = *valP;
252b5132 4603
e1b283bb 4604#if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
93382f6d
AM		 4605 if (fixP->fx_pcrel)
4606 {
4607 switch (fixP->fx_r_type)
4608 {
5865bb77
ILT		 4609 default:
4610 break;
4611
93382f6d
AM		 4612 case BFD_RELOC_32:
4613 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4614 break;
4615 case BFD_RELOC_16:
4616 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4617 break;
4618 case BFD_RELOC_8:
4619 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4620 break;
4621 }
4622 }
252b5132 4623
a161fe53 4624 if (fixP->fx_addsy != NULL
31312f95
AM		 4625 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
4626 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4627 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4628 && !use_rela_relocations)
252b5132 4629 {
31312f95
AM		 4630 /* This is a hack. There should be a better way to handle this.
4631 This covers for the fact that bfd_install_relocation will
4632 subtract the current location (for partial_inplace, PC relative
4633 relocations); see more below. */
252b5132
RH		 4634#ifndef OBJ_AOUT
4635 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4636#ifdef TE_PE
4637 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4638#endif
4639 )
4640 value += fixP->fx_where + fixP->fx_frag->fr_address;
4641#endif
4642#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2f66722d 4643 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
252b5132 4644 {
6539b54b 4645 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 4646
6539b54b 4647 if ((sym_seg == seg
2f66722d 4648 || (symbol_section_p (fixP->fx_addsy)
6539b54b
AM		 4649 && sym_seg != absolute_section))
4650 && !S_FORCE_RELOC (fixP->fx_addsy))
2f66722d
AM		 4651 {
4652 /* Yes, we add the values in twice. This is because
6539b54b
AM		 4653 bfd_install_relocation subtracts them out again. I think
4654 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 4655 it. FIXME. */
4656 value += fixP->fx_where + fixP->fx_frag->fr_address;
4657 }
252b5132
RH		 4658 }
4659#endif
4660#if defined (OBJ_COFF) && defined (TE_PE)
4661 /* For some reason, the PE format does not store a section
24eab124 4662 address offset for a PC relative symbol. */
252b5132
RH		 4663 if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
4664 value += md_pcrel_from (fixP);
4665#endif
4666 }
4667
4668 /* Fix a few things - the dynamic linker expects certain values here,
47926f60 4669 and we must not dissappoint it. */
252b5132
RH		 4670#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4671 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4672 && fixP->fx_addsy)
47926f60
KH		 4673 switch (fixP->fx_r_type)
4674 {
4675 case BFD_RELOC_386_PLT32:
3e73aa7c 4676 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 4677 /* Make the jump instruction point to the address of the operand. At
4678 runtime we merely add the offset to the actual PLT entry. */
4679 value = -4;
4680 break;
31312f95 4681
13ae64f3
JJ		 4682 case BFD_RELOC_386_TLS_GD:
4683 case BFD_RELOC_386_TLS_LDM:
13ae64f3 4684 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 4685 case BFD_RELOC_386_TLS_IE:
4686 case BFD_RELOC_386_TLS_GOTIE:
bffbf940
JJ		 4687 case BFD_RELOC_X86_64_TLSGD:
4688 case BFD_RELOC_X86_64_TLSLD:
4689 case BFD_RELOC_X86_64_GOTTPOFF:
00f7efb6
JJ		 4690 value = 0; /* Fully resolved at runtime. No addend. */
4691 /* Fallthrough */
4692 case BFD_RELOC_386_TLS_LE:
4693 case BFD_RELOC_386_TLS_LDO_32:
4694 case BFD_RELOC_386_TLS_LE_32:
4695 case BFD_RELOC_X86_64_DTPOFF32:
4696 case BFD_RELOC_X86_64_TPOFF32:
4697 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4698 break;
4699
4700 case BFD_RELOC_386_GOT32:
4701 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 4702 value = 0; /* Fully resolved at runtime. No addend. */
4703 break;
47926f60
KH		 4704
4705 case BFD_RELOC_VTABLE_INHERIT:
4706 case BFD_RELOC_VTABLE_ENTRY:
4707 fixP->fx_done = 0;
94f592af 4708 return;
47926f60
KH		 4709
4710 default:
4711 break;
4712 }
4713#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 4714 *valP = value;
47926f60 4715#endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
3e73aa7c 4716
3e73aa7c 4717 /* Are we finished with this relocation now? */
c6682705 4718 if (fixP->fx_addsy == NULL)
3e73aa7c 4719 fixP->fx_done = 1;
94f592af 4720#ifdef BFD_ASSEMBLER
3e73aa7c
JH		 4721 else if (use_rela_relocations)
4722 {
4723 fixP->fx_no_overflow = 1;
062cd5e7
AS		 4724 /* Remember value for tc_gen_reloc. */
4725 fixP->fx_addnumber = value;
3e73aa7c
JH		 4726 value = 0;
4727 }
3e73aa7c 4728#endif
94f592af 4729 md_number_to_chars (p, value, fixP->fx_size);
252b5132 4730}
252b5132 4731\f
252b5132
RH		 4732#define MAX_LITTLENUMS 6
4733
47926f60
KH		 4734/* Turn the string pointed to by litP into a floating point constant
4735 of type TYPE, and emit the appropriate bytes. The number of
4736 LITTLENUMS emitted is stored in *SIZEP. An error message is
4737 returned, or NULL on OK. */
4738
252b5132
RH		 4739char *
4740md_atof (type, litP, sizeP)
2ab9b79e 4741 int type;
252b5132
RH		 4742 char *litP;
4743 int *sizeP;
4744{
4745 int prec;
4746 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4747 LITTLENUM_TYPE *wordP;
4748 char *t;
4749
4750 switch (type)
4751 {
4752 case 'f':
4753 case 'F':
4754 prec = 2;
4755 break;
4756
4757 case 'd':
4758 case 'D':
4759 prec = 4;
4760 break;
4761
4762 case 'x':
4763 case 'X':
4764 prec = 5;
4765 break;
4766
4767 default:
4768 *sizeP = 0;
4769 return _("Bad call to md_atof ()");
4770 }
4771 t = atof_ieee (input_line_pointer, type, words);
4772 if (t)
4773 input_line_pointer = t;
4774
4775 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4776 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4777 the bigendian 386. */
4778 for (wordP = words + prec - 1; prec--;)
4779 {
4780 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
4781 litP += sizeof (LITTLENUM_TYPE);
4782 }
4783 return 0;
4784}
4785\f
4786char output_invalid_buf[8];
4787
252b5132
RH		 4788static char *
4789output_invalid (c)
4790 int c;
4791{
3882b010 4792 if (ISPRINT (c))
252b5132
RH		 4793 sprintf (output_invalid_buf, "'%c'", c);
4794 else
4795 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
4796 return output_invalid_buf;
4797}
4798
af6bdddf 4799/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 4800
4801static const reg_entry *
4802parse_register (reg_string, end_op)
4803 char *reg_string;
4804 char **end_op;
4805{
af6bdddf
AM		 4806 char *s = reg_string;
4807 char *p;
252b5132
RH		 4808 char reg_name_given[MAX_REG_NAME_SIZE + 1];
4809 const reg_entry *r;
4810
4811 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4812 if (*s == REGISTER_PREFIX)
4813 ++s;
4814
4815 if (is_space_char (*s))
4816 ++s;
4817
4818 p = reg_name_given;
af6bdddf 4819 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 4820 {
4821 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 4822 return (const reg_entry *) NULL;
4823 s++;
252b5132
RH		 4824 }
4825
6588847e
DN		 4826 /* For naked regs, make sure that we are not dealing with an identifier.
4827 This prevents confusing an identifier like `eax_var' with register
4828 `eax'. */
4829 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
4830 return (const reg_entry *) NULL;
4831
af6bdddf 4832 *end_op = s;
252b5132
RH		 4833
4834 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
4835
5f47d35b 4836 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 4837 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 4838 {
5f47d35b
AM		 4839 if (is_space_char (*s))
4840 ++s;
4841 if (*s == '(')
4842 {
af6bdddf 4843 ++s;
5f47d35b
AM		 4844 if (is_space_char (*s))
4845 ++s;
4846 if (*s >= '0' && *s <= '7')
4847 {
4848 r = &i386_float_regtab[*s - '0'];
af6bdddf 4849 ++s;
5f47d35b
AM		 4850 if (is_space_char (*s))
4851 ++s;
4852 if (*s == ')')
4853 {
4854 *end_op = s + 1;
4855 return r;
4856 }
5f47d35b 4857 }
47926f60 4858 /* We have "%st(" then garbage. */
5f47d35b
AM		 4859 return (const reg_entry *) NULL;
4860 }
4861 }
4862
1ae00879 4863 if (r != NULL
29b0f896 4864 && (r->reg_flags & (RegRex64 | RegRex)) != 0
1ae00879
AM		 4865 && flag_code != CODE_64BIT)
4866 {
4867 return (const reg_entry *) NULL;
4868 }
4869
252b5132
RH		 4870 return r;
4871}
4872\f
4cc782b5 4873#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
65172ab8 4874const char *md_shortopts = "kVQ:sq";
252b5132 4875#else
65172ab8 4876const char *md_shortopts = "q";
252b5132 4877#endif
6e0b89ee 4878
252b5132 4879struct option md_longopts[] = {
3e73aa7c
JH		 4880#define OPTION_32 (OPTION_MD_BASE + 0)
4881 {"32", no_argument, NULL, OPTION_32},
6e0b89ee 4882#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3e73aa7c
JH		 4883#define OPTION_64 (OPTION_MD_BASE + 1)
4884 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 4885#endif
252b5132
RH		 4886 {NULL, no_argument, NULL, 0}
4887};
4888size_t md_longopts_size = sizeof (md_longopts);
4889
4890int
4891md_parse_option (c, arg)
4892 int c;
ab9da554 4893 char *arg ATTRIBUTE_UNUSED;
252b5132
RH		 4894{
4895 switch (c)
4896 {
a38cf1db
AM		 4897 case 'q':
4898 quiet_warnings = 1;
252b5132
RH		 4899 break;
4900
4901#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 4902 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4903 should be emitted or not. FIXME: Not implemented. */
4904 case 'Q':
252b5132
RH		 4905 break;
4906
4907 /* -V: SVR4 argument to print version ID. */
4908 case 'V':
4909 print_version_id ();
4910 break;
4911
a38cf1db
AM		 4912 /* -k: Ignore for FreeBSD compatibility. */
4913 case 'k':
252b5132 4914 break;
4cc782b5
ILT		 4915
4916 case 's':
4917 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 4918 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 4919 break;
6e0b89ee 4920
3e73aa7c
JH		 4921 case OPTION_64:
4922 {
4923 const char **list, **l;
4924
3e73aa7c
JH		 4925 list = bfd_target_list ();
4926 for (l = list; *l != NULL; l++)
6e0b89ee
AM		 4927 if (strcmp (*l, "elf64-x86-64") == 0)
4928 {
4929 default_arch = "x86_64";
4930 break;
4931 }
3e73aa7c 4932 if (*l == NULL)
6e0b89ee 4933 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 4934 free (list);
4935 }
4936 break;
4937#endif
252b5132 4938
6e0b89ee
AM		 4939 case OPTION_32:
4940 default_arch = "i386";
4941 break;
4942
252b5132
RH		 4943 default:
4944 return 0;
4945 }
4946 return 1;
4947}
4948
4949void
4950md_show_usage (stream)
4951 FILE *stream;
4952{
4cc782b5
ILT		 4953#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4954 fprintf (stream, _("\
a38cf1db
AM		 4955 -Q ignored\n\
4956 -V print assembler version number\n\
4957 -k ignored\n\
4958 -q quieten some warnings\n\
4959 -s ignored\n"));
4960#else
4961 fprintf (stream, _("\
4962 -q quieten some warnings\n"));
4cc782b5 4963#endif
252b5132
RH		 4964}
4965
4966#ifdef BFD_ASSEMBLER
3e73aa7c
JH		 4967#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4968 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 4969
4970/* Pick the target format to use. */
4971
47926f60 4972const char *
252b5132
RH		 4973i386_target_format ()
4974{
3e73aa7c
JH		 4975 if (!strcmp (default_arch, "x86_64"))
4976 set_code_flag (CODE_64BIT);
4977 else if (!strcmp (default_arch, "i386"))
4978 set_code_flag (CODE_32BIT);
4979 else
4980 as_fatal (_("Unknown architecture"));
252b5132
RH		 4981 switch (OUTPUT_FLAVOR)
4982 {
4c63da97
AM		 4983#ifdef OBJ_MAYBE_AOUT
4984 case bfd_target_aout_flavour:
47926f60 4985 return AOUT_TARGET_FORMAT;
4c63da97
AM		 4986#endif
4987#ifdef OBJ_MAYBE_COFF
252b5132
RH		 4988 case bfd_target_coff_flavour:
4989 return "coff-i386";
4c63da97 4990#endif
3e73aa7c 4991#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 4992 case bfd_target_elf_flavour:
3e73aa7c 4993 {
e5cb08ac
KH		 4994 if (flag_code == CODE_64BIT)
4995 use_rela_relocations = 1;
4ada7262 4996 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
3e73aa7c 4997 }
4c63da97 4998#endif
252b5132
RH		 4999 default:
5000 abort ();
5001 return NULL;
5002 }
5003}
5004
47926f60 5005#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 5006
5007#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5008void i386_elf_emit_arch_note ()
5009{
5010 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
5011 && cpu_arch_name != NULL)
5012 {
5013 char *p;
5014 asection *seg = now_seg;
5015 subsegT subseg = now_subseg;
5016 Elf_Internal_Note i_note;
5017 Elf_External_Note e_note;
5018 asection *note_secp;
5019 int len;
5020
5021 /* Create the .note section. */
5022 note_secp = subseg_new (".note", 0);
5023 bfd_set_section_flags (stdoutput,
5024 note_secp,
5025 SEC_HAS_CONTENTS | SEC_READONLY);
5026
5027 /* Process the arch string. */
5028 len = strlen (cpu_arch_name);
5029
5030 i_note.namesz = len + 1;
5031 i_note.descsz = 0;
5032 i_note.type = NT_ARCH;
5033 p = frag_more (sizeof (e_note.namesz));
5034 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
5035 p = frag_more (sizeof (e_note.descsz));
5036 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
5037 p = frag_more (sizeof (e_note.type));
5038 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
5039 p = frag_more (len + 1);
5040 strcpy (p, cpu_arch_name);
5041
5042 frag_align (2, 0, 0);
5043
5044 subseg_set (seg, subseg);
5045 }
5046}
5047#endif
47926f60 5048#endif /* BFD_ASSEMBLER */
252b5132 5049\f
252b5132
RH		 5050symbolS *
5051md_undefined_symbol (name)
5052 char *name;
5053{
18dc2407
ILT		 5054 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
5055 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
5056 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
5057 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 5058 {
5059 if (!GOT_symbol)
5060 {
5061 if (symbol_find (name))
5062 as_bad (_("GOT already in symbol table"));
5063 GOT_symbol = symbol_new (name, undefined_section,
5064 (valueT) 0, &zero_address_frag);
5065 };
5066 return GOT_symbol;
5067 }
252b5132
RH		 5068 return 0;
5069}
5070
5071/* Round up a section size to the appropriate boundary. */
47926f60 5072
252b5132
RH		 5073valueT
5074md_section_align (segment, size)
ab9da554 5075 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 5076 valueT size;
5077{
252b5132 5078#ifdef BFD_ASSEMBLER
4c63da97
AM		 5079#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5080 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
5081 {
5082 /* For a.out, force the section size to be aligned. If we don't do
5083 this, BFD will align it for us, but it will not write out the
5084 final bytes of the section. This may be a bug in BFD, but it is
5085 easier to fix it here since that is how the other a.out targets
5086 work. */
5087 int align;
5088
5089 align = bfd_get_section_alignment (stdoutput, segment);
5090 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
5091 }
252b5132
RH		 5092#endif
5093#endif
5094
5095 return size;
5096}
5097
5098/* On the i386, PC-relative offsets are relative to the start of the
5099 next instruction. That is, the address of the offset, plus its
5100 size, since the offset is always the last part of the insn. */
5101
5102long
5103md_pcrel_from (fixP)
5104 fixS *fixP;
5105{
5106 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5107}
5108
5109#ifndef I386COFF
5110
5111static void
5112s_bss (ignore)
ab9da554 5113 int ignore ATTRIBUTE_UNUSED;
252b5132 5114{
29b0f896 5115 int temp;
252b5132
RH		 5116
5117 temp = get_absolute_expression ();
5118 subseg_set (bss_section, (subsegT) temp);
5119 demand_empty_rest_of_line ();
5120}
5121
5122#endif
5123
252b5132
RH		 5124#ifdef BFD_ASSEMBLER
5125
5126void
5127i386_validate_fix (fixp)
5128 fixS *fixp;
5129{
5130 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5131 {
3e73aa7c 5132 /* GOTOFF relocation are nonsense in 64bit mode. */
23df1078
JH		 5133 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5134 {
5135 if (flag_code != CODE_64BIT)
5136 abort ();
5137 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5138 }
5139 else
5140 {
5141 if (flag_code == CODE_64BIT)
5142 abort ();
5143 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5144 }
252b5132
RH		 5145 fixp->fx_subsy = 0;
5146 }
5147}
5148
b34976b6 5149bfd_boolean
a161fe53
AM		 5150i386_force_relocation (fixp)
5151 fixS *fixp;
5152{
5153 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
5154 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5155 return 1;
5156
5157 return S_FORCE_RELOC (fixp->fx_addsy);
5158}
5159
252b5132
RH		 5160arelent *
5161tc_gen_reloc (section, fixp)
ab9da554 5162 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 5163 fixS *fixp;
5164{
5165 arelent *rel;
5166 bfd_reloc_code_real_type code;
5167
5168 switch (fixp->fx_r_type)
5169 {
3e73aa7c
JH		 5170 case BFD_RELOC_X86_64_PLT32:
5171 case BFD_RELOC_X86_64_GOT32:
5172 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 5173 case BFD_RELOC_386_PLT32:
5174 case BFD_RELOC_386_GOT32:
5175 case BFD_RELOC_386_GOTOFF:
5176 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 5177 case BFD_RELOC_386_TLS_GD:
5178 case BFD_RELOC_386_TLS_LDM:
5179 case BFD_RELOC_386_TLS_LDO_32:
5180 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5181 case BFD_RELOC_386_TLS_IE:
5182 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 5183 case BFD_RELOC_386_TLS_LE_32:
5184 case BFD_RELOC_386_TLS_LE:
3e73aa7c 5185 case BFD_RELOC_X86_64_32S:
bffbf940
JJ		 5186 case BFD_RELOC_X86_64_TLSGD:
5187 case BFD_RELOC_X86_64_TLSLD:
5188 case BFD_RELOC_X86_64_DTPOFF32:
5189 case BFD_RELOC_X86_64_GOTTPOFF:
5190 case BFD_RELOC_X86_64_TPOFF32:
252b5132
RH		 5191 case BFD_RELOC_RVA:
5192 case BFD_RELOC_VTABLE_ENTRY:
5193 case BFD_RELOC_VTABLE_INHERIT:
5194 code = fixp->fx_r_type;
5195 break;
5196 default:
93382f6d 5197 if (fixp->fx_pcrel)
252b5132 5198 {
93382f6d
AM		 5199 switch (fixp->fx_size)
5200 {
5201 default:
b091f402
AM		 5202 as_bad_where (fixp->fx_file, fixp->fx_line,
5203 _("can not do %d byte pc-relative relocation"),
5204 fixp->fx_size);
93382f6d
AM		 5205 code = BFD_RELOC_32_PCREL;
5206 break;
5207 case 1: code = BFD_RELOC_8_PCREL; break;
5208 case 2: code = BFD_RELOC_16_PCREL; break;
5209 case 4: code = BFD_RELOC_32_PCREL; break;
5210 }
5211 }
5212 else
5213 {
5214 switch (fixp->fx_size)
5215 {
5216 default:
b091f402
AM		 5217 as_bad_where (fixp->fx_file, fixp->fx_line,
5218 _("can not do %d byte relocation"),
5219 fixp->fx_size);
93382f6d
AM		 5220 code = BFD_RELOC_32;
5221 break;
5222 case 1: code = BFD_RELOC_8; break;
5223 case 2: code = BFD_RELOC_16; break;
5224 case 4: code = BFD_RELOC_32; break;
937149dd 5225#ifdef BFD64
3e73aa7c 5226 case 8: code = BFD_RELOC_64; break;
937149dd 5227#endif
93382f6d 5228 }
252b5132
RH		 5229 }
5230 break;
5231 }
252b5132
RH		 5232
5233 if (code == BFD_RELOC_32
5234 && GOT_symbol
5235 && fixp->fx_addsy == GOT_symbol)
3e73aa7c
JH		 5236 {
5237 /* We don't support GOTPC on 64bit targets. */
5238 if (flag_code == CODE_64BIT)
bfb32b52 5239 abort ();
3e73aa7c
JH		 5240 code = BFD_RELOC_386_GOTPC;
5241 }
252b5132
RH		 5242
5243 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 5244 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5245 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 5246
5247 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
3e73aa7c
JH		 5248 if (!use_rela_relocations)
5249 {
5250 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5251 vtable entry to be used in the relocation's section offset. */
5252 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5253 rel->address = fixp->fx_offset;
252b5132 5254
c6682705 5255 rel->addend = 0;
3e73aa7c
JH		 5256 }
5257 /* Use the rela in 64bit mode. */
252b5132 5258 else
3e73aa7c 5259 {
062cd5e7
AS		 5260 if (!fixp->fx_pcrel)
5261 rel->addend = fixp->fx_offset;
5262 else
5263 switch (code)
5264 {
5265 case BFD_RELOC_X86_64_PLT32:
5266 case BFD_RELOC_X86_64_GOT32:
5267 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 5268 case BFD_RELOC_X86_64_TLSGD:
5269 case BFD_RELOC_X86_64_TLSLD:
5270 case BFD_RELOC_X86_64_GOTTPOFF:
062cd5e7
AS		 5271 rel->addend = fixp->fx_offset - fixp->fx_size;
5272 break;
5273 default:
5274 rel->addend = (section->vma
5275 - fixp->fx_size
5276 + fixp->fx_addnumber
5277 + md_pcrel_from (fixp));
5278 break;
5279 }
3e73aa7c
JH		 5280 }
5281
252b5132
RH		 5282 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5283 if (rel->howto == NULL)
5284 {
5285 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 5286 _("cannot represent relocation type %s"),
252b5132
RH		 5287 bfd_get_reloc_code_name (code));
5288 /* Set howto to a garbage value so that we can keep going. */
5289 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5290 assert (rel->howto != NULL);
5291 }
5292
5293 return rel;
5294}
5295
29b0f896 5296#else /* !BFD_ASSEMBLER */
252b5132
RH		 5297
5298#if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
5299void
5300tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
5301 char *where;
5302 fixS *fixP;
5303 relax_addressT segment_address_in_file;
5304{
47926f60
KH		 5305 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
5306 Out: GNU LD relocation length code: 0, 1, or 2. */
252b5132 5307
47926f60 5308 static const unsigned char nbytes_r_length[] = { 42, 0, 1, 42, 2 };
252b5132
RH		 5309 long r_symbolnum;
5310
5311 know (fixP->fx_addsy != NULL);
5312
5313 md_number_to_chars (where,
5314 (valueT) (fixP->fx_frag->fr_address
5315 + fixP->fx_where - segment_address_in_file),
5316 4);
5317
5318 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
5319 ? S_GET_TYPE (fixP->fx_addsy)
5320 : fixP->fx_addsy->sy_number);
5321
5322 where[6] = (r_symbolnum >> 16) & 0x0ff;
5323 where[5] = (r_symbolnum >> 8) & 0x0ff;
5324 where[4] = r_symbolnum & 0x0ff;
5325 where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08)
5326 | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06)
5327 | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f));
5328}
5329
47926f60 5330#endif /* OBJ_AOUT or OBJ_BOUT. */
252b5132
RH		 5331
5332#if defined (I386COFF)
5333
5334short
5335tc_coff_fix2rtype (fixP)
5336 fixS *fixP;
5337{
5338 if (fixP->fx_r_type == R_IMAGEBASE)
5339 return R_IMAGEBASE;
5340
5341 return (fixP->fx_pcrel ?
5342 (fixP->fx_size == 1 ? R_PCRBYTE :
5343 fixP->fx_size == 2 ? R_PCRWORD :
5344 R_PCRLONG) :
5345 (fixP->fx_size == 1 ? R_RELBYTE :
5346 fixP->fx_size == 2 ? R_RELWORD :
5347 R_DIR32));
5348}
5349
5350int
5351tc_coff_sizemachdep (frag)
5352 fragS *frag;
5353{
5354 if (frag->fr_next)
5355 return (frag->fr_next->fr_address - frag->fr_address);
5356 else
5357 return 0;
5358}
5359
47926f60 5360#endif /* I386COFF */
252b5132 5361
29b0f896 5362#endif /* !BFD_ASSEMBLER */
64a0c779
DN		 5363\f
5364/* Parse operands using Intel syntax. This implements a recursive descent
5365 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5366 Programmer's Guide.
5367
5368 FIXME: We do not recognize the full operand grammar defined in the MASM
5369 documentation. In particular, all the structure/union and
5370 high-level macro operands are missing.
5371
5372 Uppercase words are terminals, lower case words are non-terminals.
5373 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5374 bars '|' denote choices. Most grammar productions are implemented in
5375 functions called 'intel_<production>'.
5376
5377 Initial production is 'expr'.
5378
64a0c779
DN		 5379 addOp + | -
5380
5381 alpha [a-zA-Z]
5382
5383 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5384
5385 constant digits [[ radixOverride ]]
5386
5387 dataType BYTE | WORD | DWORD | QWORD | XWORD
5388
5389 digits decdigit
b77a7acd
AJ		 5390 | digits decdigit
5391 | digits hexdigit
64a0c779
DN		 5392
5393 decdigit [0-9]
5394
5395 e05 e05 addOp e06
b77a7acd 5396 | e06
64a0c779
DN		 5397
5398 e06 e06 mulOp e09
b77a7acd 5399 | e09
64a0c779
DN		 5400
5401 e09 OFFSET e10
5402 | e09 PTR e10
5403 | e09 : e10
5404 | e10
5405
5406 e10 e10 [ expr ]
b77a7acd 5407 | e11
64a0c779
DN		 5408
5409 e11 ( expr )
b77a7acd 5410 | [ expr ]
64a0c779
DN		 5411 | constant
5412 | dataType
5413 | id
5414 | $
5415 | register
5416
5417 => expr SHORT e05
b77a7acd 5418 | e05
64a0c779
DN		 5419
5420 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 5421 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 5422
5423 hexdigit a | b | c | d | e | f
b77a7acd 5424 | A | B | C | D | E | F
64a0c779
DN		 5425
5426 id alpha
b77a7acd 5427 | id alpha
64a0c779
DN		 5428 | id decdigit
5429
5430 mulOp * | / | MOD
5431
5432 quote " | '
5433
5434 register specialRegister
b77a7acd 5435 | gpRegister
64a0c779
DN		 5436 | byteRegister
5437
5438 segmentRegister CS | DS | ES | FS | GS | SS
5439
5440 specialRegister CR0 | CR2 | CR3
b77a7acd 5441 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 5442 | TR3 | TR4 | TR5 | TR6 | TR7
5443
64a0c779
DN		 5444 We simplify the grammar in obvious places (e.g., register parsing is
5445 done by calling parse_register) and eliminate immediate left recursion
5446 to implement a recursive-descent parser.
5447
5448 expr SHORT e05
b77a7acd 5449 | e05
64a0c779
DN		 5450
5451 e05 e06 e05'
5452
5453 e05' addOp e06 e05'
b77a7acd 5454 | Empty
64a0c779
DN		 5455
5456 e06 e09 e06'
5457
5458 e06' mulOp e09 e06'
b77a7acd 5459 | Empty
64a0c779
DN		 5460
5461 e09 OFFSET e10 e09'
b77a7acd 5462 | e10 e09'
64a0c779
DN		 5463
5464 e09' PTR e10 e09'
b77a7acd 5465 | : e10 e09'
64a0c779
DN		 5466 | Empty
5467
5468 e10 e11 e10'
5469
5470 e10' [ expr ] e10'
b77a7acd 5471 | Empty
64a0c779
DN		 5472
5473 e11 ( expr )
b77a7acd 5474 | [ expr ]
64a0c779
DN		 5475 | BYTE
5476 | WORD
5477 | DWORD
5478 | QWORD
5479 | XWORD
5480 | .
5481 | $
5482 | register
5483 | id
5484 | constant */
5485
5486/* Parsing structure for the intel syntax parser. Used to implement the
5487 semantic actions for the operand grammar. */
5488struct intel_parser_s
5489 {
5490 char *op_string; /* The string being parsed. */
5491 int got_a_float; /* Whether the operand is a float. */
4a1805b1 5492 int op_modifier; /* Operand modifier. */
64a0c779
DN		 5493 int is_mem; /* 1 if operand is memory reference. */
5494 const reg_entry *reg; /* Last register reference found. */
5495 char *disp; /* Displacement string being built. */
5496 };
5497
5498static struct intel_parser_s intel_parser;
5499
5500/* Token structure for parsing intel syntax. */
5501struct intel_token
5502 {
5503 int code; /* Token code. */
5504 const reg_entry *reg; /* Register entry for register tokens. */
5505 char *str; /* String representation. */
5506 };
5507
5508static struct intel_token cur_token, prev_token;
5509
50705ef4
AM		 5510/* Token codes for the intel parser. Since T_SHORT is already used
5511 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 5512#define T_NIL -1
5513#define T_CONST 1
5514#define T_REG 2
5515#define T_BYTE 3
5516#define T_WORD 4
5517#define T_DWORD 5
5518#define T_QWORD 6
5519#define T_XWORD 7
50705ef4 5520#undef T_SHORT
64a0c779
DN		 5521#define T_SHORT 8
5522#define T_OFFSET 9
5523#define T_PTR 10
5524#define T_ID 11
5525
5526/* Prototypes for intel parser functions. */
5527static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 5528static void intel_get_token PARAMS ((void));
5529static void intel_putback_token PARAMS ((void));
5530static int intel_expr PARAMS ((void));
5531static int intel_e05 PARAMS ((void));
5532static int intel_e05_1 PARAMS ((void));
5533static int intel_e06 PARAMS ((void));
5534static int intel_e06_1 PARAMS ((void));
5535static int intel_e09 PARAMS ((void));
5536static int intel_e09_1 PARAMS ((void));
5537static int intel_e10 PARAMS ((void));
5538static int intel_e10_1 PARAMS ((void));
5539static int intel_e11 PARAMS ((void));
64a0c779 5540
64a0c779
DN		 5541static int
5542i386_intel_operand (operand_string, got_a_float)
5543 char *operand_string;
5544 int got_a_float;
5545{
5546 int ret;
5547 char *p;
5548
5549 /* Initialize token holders. */
5550 cur_token.code = prev_token.code = T_NIL;
5551 cur_token.reg = prev_token.reg = NULL;
5552 cur_token.str = prev_token.str = NULL;
5553
5554 /* Initialize parser structure. */
e5cb08ac 5555 p = intel_parser.op_string = (char *) malloc (strlen (operand_string) + 1);
64a0c779
DN		 5556 if (p == NULL)
5557 abort ();
5558 strcpy (intel_parser.op_string, operand_string);
5559 intel_parser.got_a_float = got_a_float;
5560 intel_parser.op_modifier = -1;
5561 intel_parser.is_mem = 0;
5562 intel_parser.reg = NULL;
e5cb08ac 5563 intel_parser.disp = (char *) malloc (strlen (operand_string) + 1);
64a0c779
DN		 5564 if (intel_parser.disp == NULL)
5565 abort ();
5566 intel_parser.disp[0] = '\0';
5567
5568 /* Read the first token and start the parser. */
5569 intel_get_token ();
5570 ret = intel_expr ();
5571
5572 if (ret)
5573 {
5574 /* If we found a memory reference, hand it over to i386_displacement
5575 to fill in the rest of the operand fields. */
5576 if (intel_parser.is_mem)
5577 {
5578 if ((i.mem_operands == 1
5579 && (current_templates->start->opcode_modifier & IsString) == 0)
5580 || i.mem_operands == 2)
5581 {
5582 as_bad (_("too many memory references for '%s'"),
5583 current_templates->start->name);
5584 ret = 0;
5585 }
5586 else
5587 {
5588 char *s = intel_parser.disp;
5589 i.mem_operands++;
5590
5591 /* Add the displacement expression. */
5592 if (*s != '\0')
5593 ret = i386_displacement (s, s + strlen (s))
5594 && i386_index_check (s);
5595 }
5596 }
5597
5598 /* Constant and OFFSET expressions are handled by i386_immediate. */
5599 else if (intel_parser.op_modifier == OFFSET_FLAT
5600 || intel_parser.reg == NULL)
5601 ret = i386_immediate (intel_parser.disp);
5602 }
5603
5604 free (p);
5605 free (intel_parser.disp);
5606
5607 return ret;
5608}
5609
64a0c779 5610/* expr SHORT e05
b77a7acd 5611 | e05 */
64a0c779
DN		 5612static int
5613intel_expr ()
5614{
5615 /* expr SHORT e05 */
5616 if (cur_token.code == T_SHORT)
5617 {
5618 intel_parser.op_modifier = SHORT;
5619 intel_match_token (T_SHORT);
5620
5621 return (intel_e05 ());
5622 }
5623
5624 /* expr e05 */
5625 else
5626 return intel_e05 ();
5627}
5628
64a0c779
DN		 5629/* e05 e06 e05'
5630
4a1805b1 5631 e05' addOp e06 e05'
64a0c779
DN		 5632 | Empty */
5633static int
5634intel_e05 ()
5635{
5636 return (intel_e06 () && intel_e05_1 ());
5637}
5638
5639static int
5640intel_e05_1 ()
5641{
5642 /* e05' addOp e06 e05' */
5643 if (cur_token.code == '+' || cur_token.code == '-')
5644 {
5645 strcat (intel_parser.disp, cur_token.str);
5646 intel_match_token (cur_token.code);
5647
5648 return (intel_e06 () && intel_e05_1 ());
5649 }
5650
5651 /* e05' Empty */
5652 else
5653 return 1;
4a1805b1 5654}
64a0c779
DN		 5655
5656/* e06 e09 e06'
5657
5658 e06' mulOp e09 e06'
b77a7acd 5659 | Empty */
64a0c779
DN		 5660static int
5661intel_e06 ()
5662{
5663 return (intel_e09 () && intel_e06_1 ());
5664}
5665
5666static int
5667intel_e06_1 ()
5668{
5669 /* e06' mulOp e09 e06' */
5670 if (cur_token.code == '*' || cur_token.code == '/')
5671 {
5672 strcat (intel_parser.disp, cur_token.str);
5673 intel_match_token (cur_token.code);
5674
5675 return (intel_e09 () && intel_e06_1 ());
5676 }
4a1805b1 5677
64a0c779 5678 /* e06' Empty */
4a1805b1 5679 else
64a0c779
DN		 5680 return 1;
5681}
5682
64a0c779 5683/* e09 OFFSET e10 e09'
b77a7acd 5684 | e10 e09'
64a0c779
DN		 5685
5686 e09' PTR e10 e09'
b77a7acd 5687 | : e10 e09'
64a0c779
DN		 5688 | Empty */
5689static int
5690intel_e09 ()
5691{
5692 /* e09 OFFSET e10 e09' */
5693 if (cur_token.code == T_OFFSET)
5694 {
5695 intel_parser.is_mem = 0;
5696 intel_parser.op_modifier = OFFSET_FLAT;
5697 intel_match_token (T_OFFSET);
5698
5699 return (intel_e10 () && intel_e09_1 ());
5700 }
5701
5702 /* e09 e10 e09' */
5703 else
5704 return (intel_e10 () && intel_e09_1 ());
5705}
5706
5707static int
5708intel_e09_1 ()
5709{
5710 /* e09' PTR e10 e09' */
5711 if (cur_token.code == T_PTR)
5712 {
5713 if (prev_token.code == T_BYTE)
5714 i.suffix = BYTE_MNEM_SUFFIX;
5715
5716 else if (prev_token.code == T_WORD)
5717 {
5718 if (intel_parser.got_a_float == 2) /* "fi..." */
5719 i.suffix = SHORT_MNEM_SUFFIX;
5720 else
5721 i.suffix = WORD_MNEM_SUFFIX;
5722 }
5723
5724 else if (prev_token.code == T_DWORD)
5725 {
5726 if (intel_parser.got_a_float == 1) /* "f..." */
5727 i.suffix = SHORT_MNEM_SUFFIX;
5728 else
5729 i.suffix = LONG_MNEM_SUFFIX;
5730 }
5731
5732 else if (prev_token.code == T_QWORD)
f16b83df
JH		 5733 {
5734 if (intel_parser.got_a_float == 1) /* "f..." */
5735 i.suffix = LONG_MNEM_SUFFIX;
5736 else
3e73aa7c 5737 i.suffix = QWORD_MNEM_SUFFIX;
f16b83df 5738 }
64a0c779
DN		 5739
5740 else if (prev_token.code == T_XWORD)
5741 i.suffix = LONG_DOUBLE_MNEM_SUFFIX;
5742
5743 else
5744 {
5745 as_bad (_("Unknown operand modifier `%s'\n"), prev_token.str);
5746 return 0;
5747 }
5748
5749 intel_match_token (T_PTR);
5750
5751 return (intel_e10 () && intel_e09_1 ());
5752 }
5753
5754 /* e09 : e10 e09' */
5755 else if (cur_token.code == ':')
5756 {
21d6c4af
DN		 5757 /* Mark as a memory operand only if it's not already known to be an
5758 offset expression. */
5759 if (intel_parser.op_modifier != OFFSET_FLAT)
5760 intel_parser.is_mem = 1;
64a0c779
DN		 5761
5762 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5763 }
5764
5765 /* e09' Empty */
5766 else
5767 return 1;
5768}
5769
5770/* e10 e11 e10'
5771
5772 e10' [ expr ] e10'
b77a7acd 5773 | Empty */
64a0c779
DN		 5774static int
5775intel_e10 ()
5776{
5777 return (intel_e11 () && intel_e10_1 ());
5778}
5779
5780static int
5781intel_e10_1 ()
5782{
5783 /* e10' [ expr ] e10' */
5784 if (cur_token.code == '[')
5785 {
5786 intel_match_token ('[');
21d6c4af
DN		 5787
5788 /* Mark as a memory operand only if it's not already known to be an
5789 offset expression. If it's an offset expression, we need to keep
5790 the brace in. */
5791 if (intel_parser.op_modifier != OFFSET_FLAT)
5792 intel_parser.is_mem = 1;
5793 else
5794 strcat (intel_parser.disp, "[");
4a1805b1 5795
64a0c779 5796 /* Add a '+' to the displacement string if necessary. */
21d6c4af
DN		 5797 if (*intel_parser.disp != '\0'
5798 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
64a0c779
DN		 5799 strcat (intel_parser.disp, "+");
5800
21d6c4af
DN		 5801 if (intel_expr () && intel_match_token (']'))
5802 {
5803 /* Preserve brackets when the operand is an offset expression. */
5804 if (intel_parser.op_modifier == OFFSET_FLAT)
5805 strcat (intel_parser.disp, "]");
5806
5807 return intel_e10_1 ();
5808 }
5809 else
5810 return 0;
64a0c779
DN		 5811 }
5812
5813 /* e10' Empty */
5814 else
5815 return 1;
5816}
5817
64a0c779 5818/* e11 ( expr )
b77a7acd 5819 | [ expr ]
64a0c779
DN		 5820 | BYTE
5821 | WORD
5822 | DWORD
5823 | QWORD
5824 | XWORD
4a1805b1 5825 | $
64a0c779
DN		 5826 | .
5827 | register
5828 | id
5829 | constant */
5830static int
5831intel_e11 ()
5832{
5833 /* e11 ( expr ) */
5834 if (cur_token.code == '(')
5835 {
5836 intel_match_token ('(');
5837 strcat (intel_parser.disp, "(");
5838
5839 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 5840 {
5841 strcat (intel_parser.disp, ")");
5842 return 1;
5843 }
64a0c779
DN		 5844 else
5845 return 0;
5846 }
5847
5848 /* e11 [ expr ] */
5849 else if (cur_token.code == '[')
5850 {
5851 intel_match_token ('[');
21d6c4af
DN		 5852
5853 /* Mark as a memory operand only if it's not already known to be an
5854 offset expression. If it's an offset expression, we need to keep
5855 the brace in. */
5856 if (intel_parser.op_modifier != OFFSET_FLAT)
5857 intel_parser.is_mem = 1;
5858 else
5859 strcat (intel_parser.disp, "[");
4a1805b1 5860
64a0c779
DN		 5861 /* Operands for jump/call inside brackets denote absolute addresses. */
5862 if (current_templates->start->opcode_modifier & Jump
5863 || current_templates->start->opcode_modifier & JumpDword
5864 || current_templates->start->opcode_modifier & JumpByte
5865 || current_templates->start->opcode_modifier & JumpInterSegment)
5866 i.types[this_operand] |= JumpAbsolute;
5867
5868 /* Add a '+' to the displacement string if necessary. */
21d6c4af
DN		 5869 if (*intel_parser.disp != '\0'
5870 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
64a0c779
DN		 5871 strcat (intel_parser.disp, "+");
5872
21d6c4af
DN		 5873 if (intel_expr () && intel_match_token (']'))
5874 {
5875 /* Preserve brackets when the operand is an offset expression. */
5876 if (intel_parser.op_modifier == OFFSET_FLAT)
5877 strcat (intel_parser.disp, "]");
5878
5879 return 1;
5880 }
5881 else
5882 return 0;
64a0c779
DN		 5883 }
5884
4a1805b1 5885 /* e11 BYTE
64a0c779
DN		 5886 | WORD
5887 | DWORD
5888 | QWORD
5889 | XWORD */
5890 else if (cur_token.code == T_BYTE
5891 || cur_token.code == T_WORD
5892 || cur_token.code == T_DWORD
5893 || cur_token.code == T_QWORD
5894 || cur_token.code == T_XWORD)
5895 {
5896 intel_match_token (cur_token.code);
5897
5898 return 1;
5899 }
5900
5901 /* e11 $
5902 | . */
5903 else if (cur_token.code == '$' || cur_token.code == '.')
5904 {
5905 strcat (intel_parser.disp, cur_token.str);
5906 intel_match_token (cur_token.code);
21d6c4af
DN		 5907
5908 /* Mark as a memory operand only if it's not already known to be an
5909 offset expression. */
5910 if (intel_parser.op_modifier != OFFSET_FLAT)
5911 intel_parser.is_mem = 1;
64a0c779
DN		 5912
5913 return 1;
5914 }
5915
5916 /* e11 register */
5917 else if (cur_token.code == T_REG)
5918 {
5919 const reg_entry *reg = intel_parser.reg = cur_token.reg;
5920
5921 intel_match_token (T_REG);
5922
5923 /* Check for segment change. */
5924 if (cur_token.code == ':')
5925 {
5926 if (reg->reg_type & (SReg2 | SReg3))
5927 {
5928 switch (reg->reg_num)
5929 {
5930 case 0:
5931 i.seg[i.mem_operands] = &es;
5932 break;
5933 case 1:
5934 i.seg[i.mem_operands] = &cs;
5935 break;
5936 case 2:
5937 i.seg[i.mem_operands] = &ss;
5938 break;
5939 case 3:
5940 i.seg[i.mem_operands] = &ds;
5941 break;
5942 case 4:
5943 i.seg[i.mem_operands] = &fs;
5944 break;
5945 case 5:
5946 i.seg[i.mem_operands] = &gs;
5947 break;
5948 }
5949 }
5950 else
5951 {
5952 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
5953 return 0;
5954 }
5955 }
5956
5957 /* Not a segment register. Check for register scaling. */
5958 else if (cur_token.code == '*')
5959 {
5960 if (!intel_parser.is_mem)
5961 {
5962 as_bad (_("Register scaling only allowed in memory operands."));
5963 return 0;
5964 }
5965
4a1805b1 5966 /* What follows must be a valid scale. */
64a0c779
DN		 5967 if (intel_match_token ('*')
5968 && strchr ("01248", *cur_token.str))
5969 {
5970 i.index_reg = reg;
5971 i.types[this_operand] |= BaseIndex;
5972
5973 /* Set the scale after setting the register (otherwise,
5974 i386_scale will complain) */
5975 i386_scale (cur_token.str);
5976 intel_match_token (T_CONST);
5977 }
5978 else
5979 {
5980 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5981 cur_token.str);
5982 return 0;
5983 }
5984 }
5985
5986 /* No scaling. If this is a memory operand, the register is either a
5987 base register (first occurrence) or an index register (second
5988 occurrence). */
5989 else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3)))
5990 {
5991 if (i.base_reg && i.index_reg)
5992 {
5993 as_bad (_("Too many register references in memory operand.\n"));
5994 return 0;
5995 }
5996
5997 if (i.base_reg == NULL)
5998 i.base_reg = reg;
5999 else
6000 i.index_reg = reg;
6001
6002 i.types[this_operand] |= BaseIndex;
6003 }
6004
6005 /* Offset modifier. Add the register to the displacement string to be
6006 parsed as an immediate expression after we're done. */
6007 else if (intel_parser.op_modifier == OFFSET_FLAT)
6008 strcat (intel_parser.disp, reg->reg_name);
4a1805b1 6009
64a0c779
DN		 6010 /* It's neither base nor index nor offset. */
6011 else
6012 {
6013 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
6014 i.op[this_operand].regs = reg;
6015 i.reg_operands++;
6016 }
6017
6018 /* Since registers are not part of the displacement string (except
6019 when we're parsing offset operands), we may need to remove any
6020 preceding '+' from the displacement string. */
6021 if (*intel_parser.disp != '\0'
6022 && intel_parser.op_modifier != OFFSET_FLAT)
6023 {
6024 char *s = intel_parser.disp;
6025 s += strlen (s) - 1;
6026 if (*s == '+')
6027 *s = '\0';
6028 }
6029
6030 return 1;
6031 }
4a1805b1 6032
64a0c779
DN		 6033 /* e11 id */
6034 else if (cur_token.code == T_ID)
6035 {
6036 /* Add the identifier to the displacement string. */
6037 strcat (intel_parser.disp, cur_token.str);
6038 intel_match_token (T_ID);
6039
6040 /* The identifier represents a memory reference only if it's not
6041 preceded by an offset modifier. */
21d6c4af 6042 if (intel_parser.op_modifier != OFFSET_FLAT)
64a0c779
DN		 6043 intel_parser.is_mem = 1;
6044
6045 return 1;
6046 }
6047
6048 /* e11 constant */
6049 else if (cur_token.code == T_CONST
e5cb08ac 6050 || cur_token.code == '-'
64a0c779
DN		 6051 || cur_token.code == '+')
6052 {
6053 char *save_str;
6054
6055 /* Allow constants that start with `+' or `-'. */
6056 if (cur_token.code == '-' || cur_token.code == '+')
6057 {
6058 strcat (intel_parser.disp, cur_token.str);
6059 intel_match_token (cur_token.code);
6060 if (cur_token.code != T_CONST)
6061 {
6062 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
6063 cur_token.str);
6064 return 0;
6065 }
6066 }
6067
e5cb08ac 6068 save_str = (char *) malloc (strlen (cur_token.str) + 1);
64a0c779 6069 if (save_str == NULL)
bc805888 6070 abort ();
64a0c779
DN		 6071 strcpy (save_str, cur_token.str);
6072
6073 /* Get the next token to check for register scaling. */
6074 intel_match_token (cur_token.code);
6075
6076 /* Check if this constant is a scaling factor for an index register. */
6077 if (cur_token.code == '*')
6078 {
6079 if (intel_match_token ('*') && cur_token.code == T_REG)
6080 {
6081 if (!intel_parser.is_mem)
6082 {
6083 as_bad (_("Register scaling only allowed in memory operands."));
6084 return 0;
6085 }
6086
4a1805b1 6087 /* The constant is followed by `* reg', so it must be
64a0c779
DN		 6088 a valid scale. */
6089 if (strchr ("01248", *save_str))
6090 {
6091 i.index_reg = cur_token.reg;
6092 i.types[this_operand] |= BaseIndex;
6093
6094 /* Set the scale after setting the register (otherwise,
6095 i386_scale will complain) */
6096 i386_scale (save_str);
6097 intel_match_token (T_REG);
6098
6099 /* Since registers are not part of the displacement
6100 string, we may need to remove any preceding '+' from
6101 the displacement string. */
6102 if (*intel_parser.disp != '\0')
6103 {
6104 char *s = intel_parser.disp;
6105 s += strlen (s) - 1;
6106 if (*s == '+')
6107 *s = '\0';
6108 }
6109
6110 free (save_str);
6111
6112 return 1;
6113 }
6114 else
6115 return 0;
6116 }
6117
6118 /* The constant was not used for register scaling. Since we have
6119 already consumed the token following `*' we now need to put it
6120 back in the stream. */
6121 else
6122 intel_putback_token ();
6123 }
6124
6125 /* Add the constant to the displacement string. */
6126 strcat (intel_parser.disp, save_str);
6127 free (save_str);
6128
6129 return 1;
6130 }
6131
64a0c779
DN		 6132 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6133 return 0;
6134}
6135
64a0c779
DN		 6136/* Match the given token against cur_token. If they match, read the next
6137 token from the operand string. */
6138static int
6139intel_match_token (code)
e5cb08ac 6140 int code;
64a0c779
DN		 6141{
6142 if (cur_token.code == code)
6143 {
6144 intel_get_token ();
6145 return 1;
6146 }
6147 else
6148 {
6149 as_bad (_("Unexpected token `%s'\n"), cur_token.str);
6150 return 0;
6151 }
6152}
6153
64a0c779
DN		 6154/* Read a new token from intel_parser.op_string and store it in cur_token. */
6155static void
6156intel_get_token ()
6157{
6158 char *end_op;
6159 const reg_entry *reg;
6160 struct intel_token new_token;
6161
6162 new_token.code = T_NIL;
6163 new_token.reg = NULL;
6164 new_token.str = NULL;
6165
4a1805b1 6166 /* Free the memory allocated to the previous token and move
64a0c779
DN		 6167 cur_token to prev_token. */
6168 if (prev_token.str)
6169 free (prev_token.str);
6170
6171 prev_token = cur_token;
6172
6173 /* Skip whitespace. */
6174 while (is_space_char (*intel_parser.op_string))
6175 intel_parser.op_string++;
6176
6177 /* Return an empty token if we find nothing else on the line. */
6178 if (*intel_parser.op_string == '\0')
6179 {
6180 cur_token = new_token;
6181 return;
6182 }
6183
6184 /* The new token cannot be larger than the remainder of the operand
6185 string. */
e5cb08ac 6186 new_token.str = (char *) malloc (strlen (intel_parser.op_string) + 1);
64a0c779 6187 if (new_token.str == NULL)
bc805888 6188 abort ();
64a0c779
DN		 6189 new_token.str[0] = '\0';
6190
6191 if (strchr ("0123456789", *intel_parser.op_string))
6192 {
6193 char *p = new_token.str;
6194 char *q = intel_parser.op_string;
6195 new_token.code = T_CONST;
6196
6197 /* Allow any kind of identifier char to encompass floating point and
6198 hexadecimal numbers. */
6199 while (is_identifier_char (*q))
6200 *p++ = *q++;
6201 *p = '\0';
6202
6203 /* Recognize special symbol names [0-9][bf]. */
6204 if (strlen (intel_parser.op_string) == 2
4a1805b1 6205 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 6206 || intel_parser.op_string[1] == 'f'))
6207 new_token.code = T_ID;
6208 }
6209
6210 else if (strchr ("+-/*:[]()", *intel_parser.op_string))
6211 {
6212 new_token.code = *intel_parser.op_string;
6213 new_token.str[0] = *intel_parser.op_string;
6214 new_token.str[1] = '\0';
6215 }
6216
6217 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
6218 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
6219 {
6220 new_token.code = T_REG;
6221 new_token.reg = reg;
6222
6223 if (*intel_parser.op_string == REGISTER_PREFIX)
6224 {
6225 new_token.str[0] = REGISTER_PREFIX;
6226 new_token.str[1] = '\0';
6227 }
6228
6229 strcat (new_token.str, reg->reg_name);
6230 }
6231
6232 else if (is_identifier_char (*intel_parser.op_string))
6233 {
6234 char *p = new_token.str;
6235 char *q = intel_parser.op_string;
6236
6237 /* A '.' or '$' followed by an identifier char is an identifier.
6238 Otherwise, it's operator '.' followed by an expression. */
6239 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6240 {
6241 new_token.code = *q;
6242 new_token.str[0] = *q;
6243 new_token.str[1] = '\0';
6244 }
6245 else
6246 {
6247 while (is_identifier_char (*q) || *q == '@')
6248 *p++ = *q++;
6249 *p = '\0';
6250
6251 if (strcasecmp (new_token.str, "BYTE") == 0)
6252 new_token.code = T_BYTE;
6253
6254 else if (strcasecmp (new_token.str, "WORD") == 0)
6255 new_token.code = T_WORD;
6256
6257 else if (strcasecmp (new_token.str, "DWORD") == 0)
6258 new_token.code = T_DWORD;
6259
6260 else if (strcasecmp (new_token.str, "QWORD") == 0)
6261 new_token.code = T_QWORD;
6262
6263 else if (strcasecmp (new_token.str, "XWORD") == 0)
6264 new_token.code = T_XWORD;
6265
6266 else if (strcasecmp (new_token.str, "PTR") == 0)
6267 new_token.code = T_PTR;
6268
6269 else if (strcasecmp (new_token.str, "SHORT") == 0)
6270 new_token.code = T_SHORT;
6271
6272 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6273 {
6274 new_token.code = T_OFFSET;
6275
6276 /* ??? This is not mentioned in the MASM grammar but gcc
6277 makes use of it with -mintel-syntax. OFFSET may be
6278 followed by FLAT: */
6279 if (strncasecmp (q, " FLAT:", 6) == 0)
6280 strcat (new_token.str, " FLAT:");
6281 }
6282
6283 /* ??? This is not mentioned in the MASM grammar. */
6284 else if (strcasecmp (new_token.str, "FLAT") == 0)
6285 new_token.code = T_OFFSET;
6286
6287 else
6288 new_token.code = T_ID;
6289 }
6290 }
6291
6292 else
6293 as_bad (_("Unrecognized token `%s'\n"), intel_parser.op_string);
6294
6295 intel_parser.op_string += strlen (new_token.str);
6296 cur_token = new_token;
6297}
6298
64a0c779
DN		 6299/* Put cur_token back into the token stream and make cur_token point to
6300 prev_token. */
6301static void
6302intel_putback_token ()
6303{
6304 intel_parser.op_string -= strlen (cur_token.str);
6305 free (cur_token.str);
6306 cur_token = prev_token;
4a1805b1 6307
64a0c779
DN		 6308 /* Forget prev_token. */
6309 prev_token.code = T_NIL;
6310 prev_token.reg = NULL;
6311 prev_token.str = NULL;
6312}
GDB Binutils - Deliverables
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