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Add znver1 processor
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
b90efa5b 2 Copyright (C) 1989-2015 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
89e7505f
L		 36#ifdef TE_LINUX
37/* Default to compress debug sections for Linux. */
38int flag_compress_debug = 1;
39#endif
40
252b5132
RH		 41#ifndef REGISTER_WARNINGS
42#define REGISTER_WARNINGS 1
43#endif
44
c3332e24 45#ifndef INFER_ADDR_PREFIX
eecb386c 46#define INFER_ADDR_PREFIX 1
c3332e24
AM		 47#endif
48
29b0f896
AM		 49#ifndef DEFAULT_ARCH
50#define DEFAULT_ARCH "i386"
246fcdee 51#endif
252b5132 52
edde18a5
AM		 53#ifndef INLINE
54#if __GNUC__ >= 2
55#define INLINE __inline__
56#else
57#define INLINE
58#endif
59#endif
60
6305a203
L		 61/* Prefixes will be emitted in the order defined below.
62 WAIT_PREFIX must be the first prefix since FWAIT is really is an
63 instruction, and so must come before any prefixes.
64 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 65 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 66#define WAIT_PREFIX 0
67#define SEG_PREFIX 1
68#define ADDR_PREFIX 2
69#define DATA_PREFIX 3
c32fa91d 70#define REP_PREFIX 4
42164a71 71#define HLE_PREFIX REP_PREFIX
7e8b059b 72#define BND_PREFIX REP_PREFIX
c32fa91d
L		 73#define LOCK_PREFIX 5
74#define REX_PREFIX 6 /* must come last. */
75#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 76
77/* we define the syntax here (modulo base,index,scale syntax) */
78#define REGISTER_PREFIX '%'
79#define IMMEDIATE_PREFIX '$'
80#define ABSOLUTE_PREFIX '*'
81
82/* these are the instruction mnemonic suffixes in AT&T syntax or
83 memory operand size in Intel syntax. */
84#define WORD_MNEM_SUFFIX 'w'
85#define BYTE_MNEM_SUFFIX 'b'
86#define SHORT_MNEM_SUFFIX 's'
87#define LONG_MNEM_SUFFIX 'l'
88#define QWORD_MNEM_SUFFIX 'q'
89#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 90#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 91#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 92/* Intel Syntax. Use a non-ascii letter since since it never appears
93 in instructions. */
94#define LONG_DOUBLE_MNEM_SUFFIX '\1'
95
96#define END_OF_INSN '\0'
97
98/*
99 'templates' is for grouping together 'template' structures for opcodes
100 of the same name. This is only used for storing the insns in the grand
101 ole hash table of insns.
102 The templates themselves start at START and range up to (but not including)
103 END.
104 */
105typedef struct
106{
d3ce72d0
NC		 107 const insn_template *start;
108 const insn_template *end;
6305a203
L		 109}
110templates;
111
112/* 386 operand encoding bytes: see 386 book for details of this. */
113typedef struct
114{
115 unsigned int regmem; /* codes register or memory operand */
116 unsigned int reg; /* codes register operand (or extended opcode) */
117 unsigned int mode; /* how to interpret regmem & reg */
118}
119modrm_byte;
120
121/* x86-64 extension prefix. */
122typedef int rex_byte;
123
6305a203
L		 124/* 386 opcode byte to code indirect addressing. */
125typedef struct
126{
127 unsigned base;
128 unsigned index;
129 unsigned scale;
130}
131sib_byte;
132
6305a203
L		 133/* x86 arch names, types and features */
134typedef struct
135{
136 const char *name; /* arch name */
8a2c8fef 137 unsigned int len; /* arch string length */
6305a203
L		 138 enum processor_type type; /* arch type */
139 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 140 unsigned int skip; /* show_arch should skip this. */
22109423 141 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 142}
143arch_entry;
144
78f12dd3 145static void update_code_flag (int, int);
e3bb37b5
L		 146static void set_code_flag (int);
147static void set_16bit_gcc_code_flag (int);
148static void set_intel_syntax (int);
1efbbeb4 149static void set_intel_mnemonic (int);
db51cc60 150static void set_allow_index_reg (int);
7bab8ab5 151static void set_check (int);
e3bb37b5 152static void set_cpu_arch (int);
6482c264 153#ifdef TE_PE
e3bb37b5 154static void pe_directive_secrel (int);
6482c264 155#endif
e3bb37b5
L		 156static void signed_cons (int);
157static char *output_invalid (int c);
ee86248c
JB		 158static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
159 const char *);
160static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
161 const char *);
a7619375 162static int i386_att_operand (char *);
e3bb37b5 163static int i386_intel_operand (char *, int);
ee86248c
JB		 164static int i386_intel_simplify (expressionS *);
165static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 166static const reg_entry *parse_register (char *, char **);
167static char *parse_insn (char *, char *);
168static char *parse_operands (char *, const char *);
169static void swap_operands (void);
4d456e3d 170static void swap_2_operands (int, int);
e3bb37b5
L		 171static void optimize_imm (void);
172static void optimize_disp (void);
d3ce72d0 173static const insn_template *match_template (void);
e3bb37b5
L		 174static int check_string (void);
175static int process_suffix (void);
176static int check_byte_reg (void);
177static int check_long_reg (void);
178static int check_qword_reg (void);
179static int check_word_reg (void);
180static int finalize_imm (void);
181static int process_operands (void);
182static const seg_entry *build_modrm_byte (void);
183static void output_insn (void);
184static void output_imm (fragS *, offsetT);
185static void output_disp (fragS *, offsetT);
29b0f896 186#ifndef I386COFF
e3bb37b5 187static void s_bss (int);
252b5132 188#endif
17d4e2a2
L		 189#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190static void handle_large_common (int small ATTRIBUTE_UNUSED);
191#endif
252b5132 192
a847613f 193static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 194
43234a1e
L		 195/* This struct describes rounding control and SAE in the instruction. */
196struct RC_Operation
197{
198 enum rc_type
199 {
200 rne = 0,
201 rd,
202 ru,
203 rz,
204 saeonly
205 } type;
206 int operand;
207};
208
209static struct RC_Operation rc_op;
210
211/* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214struct Mask_Operation
215{
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
219 int operand;
220};
221
222static struct Mask_Operation mask_op;
223
224/* The struct describes broadcasting, applied to OPERAND. FACTOR is
225 broadcast factor. */
226struct Broadcast_Operation
227{
228 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
229 int type;
230
231 /* Index of broadcasted operand. */
232 int operand;
233};
234
235static struct Broadcast_Operation broadcast_op;
236
c0f3af97
L		 237/* VEX prefix. */
238typedef struct
239{
43234a1e
L		 240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes[4];
c0f3af97
L		 242 unsigned int length;
243 /* Destination or source register specifier. */
244 const reg_entry *register_specifier;
245} vex_prefix;
246
252b5132 247/* 'md_assemble ()' gathers together information and puts it into a
47926f60 248 i386_insn. */
252b5132 249
520dc8e8
AM		 250union i386_op
251 {
252 expressionS *disps;
253 expressionS *imms;
254 const reg_entry *regs;
255 };
256
a65babc9
L		 257enum i386_error
258 {
86e026a4 259 operand_size_mismatch,
a65babc9
L		 260 operand_type_mismatch,
261 register_type_mismatch,
262 number_of_operands_mismatch,
263 invalid_instruction_suffix,
264 bad_imm4,
265 old_gcc_only,
266 unsupported_with_intel_mnemonic,
267 unsupported_syntax,
6c30d220
L		 268 unsupported,
269 invalid_vsib_address,
7bab8ab5 270 invalid_vector_register_set,
43234a1e
L		 271 unsupported_vector_index_register,
272 unsupported_broadcast,
273 broadcast_not_on_src_operand,
274 broadcast_needed,
275 unsupported_masking,
276 mask_not_on_destination,
277 no_default_mask,
278 unsupported_rc_sae,
279 rc_sae_operand_not_last_imm,
280 invalid_register_operand,
281 try_vector_disp8
a65babc9
L		 282 };
283
252b5132
RH		 284struct _i386_insn
285 {
47926f60 286 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 287 insn_template tm;
252b5132 288
7d5e4556
L		 289 /* SUFFIX holds the instruction size suffix for byte, word, dword
290 or qword, if given. */
252b5132
RH		 291 char suffix;
292
47926f60 293 /* OPERANDS gives the number of given operands. */
252b5132
RH		 294 unsigned int operands;
295
296 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
297 of given register, displacement, memory operands and immediate
47926f60 298 operands. */
252b5132
RH		 299 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
300
301 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 302 use OP[i] for the corresponding operand. */
40fb9820 303 i386_operand_type types[MAX_OPERANDS];
252b5132 304
520dc8e8
AM		 305 /* Displacement expression, immediate expression, or register for each
306 operand. */
307 union i386_op op[MAX_OPERANDS];
252b5132 308
3e73aa7c
JH		 309 /* Flags for operands. */
310 unsigned int flags[MAX_OPERANDS];
311#define Operand_PCrel 1
312
252b5132 313 /* Relocation type for operand */
f86103b7 314 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 315
252b5132
RH		 316 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
317 the base index byte below. */
318 const reg_entry *base_reg;
319 const reg_entry *index_reg;
320 unsigned int log2_scale_factor;
321
322 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 323 explicit segment overrides are given. */
ce8a8b2f 324 const seg_entry *seg[2];
252b5132
RH		 325
326 /* PREFIX holds all the given prefix opcodes (usually null).
327 PREFIXES is the number of prefix opcodes. */
328 unsigned int prefixes;
329 unsigned char prefix[MAX_PREFIXES];
330
331 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 332 addressing modes of this insn are encoded. */
252b5132 333 modrm_byte rm;
3e73aa7c 334 rex_byte rex;
43234a1e 335 rex_byte vrex;
252b5132 336 sib_byte sib;
c0f3af97 337 vex_prefix vex;
b6169b20 338
43234a1e
L		 339 /* Masking attributes. */
340 struct Mask_Operation *mask;
341
342 /* Rounding control and SAE attributes. */
343 struct RC_Operation *rounding;
344
345 /* Broadcasting attributes. */
346 struct Broadcast_Operation *broadcast;
347
348 /* Compressed disp8*N attribute. */
349 unsigned int memshift;
350
b6169b20 351 /* Swap operand in encoding. */
4473e004 352 unsigned int swap_operand;
891edac4 353
a501d77e
L		 354 /* Prefer 8bit or 32bit displacement in encoding. */
355 enum
356 {
357 disp_encoding_default = 0,
358 disp_encoding_8bit,
359 disp_encoding_32bit
360 } disp_encoding;
f8a5c266 361
d5de92cf
L		 362 /* REP prefix. */
363 const char *rep_prefix;
364
165de32a
L		 365 /* HLE prefix. */
366 const char *hle_prefix;
42164a71 367
7e8b059b
L		 368 /* Have BND prefix. */
369 const char *bnd_prefix;
370
43234a1e
L		 371 /* Need VREX to support upper 16 registers. */
372 int need_vrex;
373
891edac4 374 /* Error message. */
a65babc9 375 enum i386_error error;
252b5132
RH		 376 };
377
378typedef struct _i386_insn i386_insn;
379
43234a1e
L		 380/* Link RC type with corresponding string, that'll be looked for in
381 asm. */
382struct RC_name
383{
384 enum rc_type type;
385 const char *name;
386 unsigned int len;
387};
388
389static const struct RC_name RC_NamesTable[] =
390{
391 { rne, STRING_COMMA_LEN ("rn-sae") },
392 { rd, STRING_COMMA_LEN ("rd-sae") },
393 { ru, STRING_COMMA_LEN ("ru-sae") },
394 { rz, STRING_COMMA_LEN ("rz-sae") },
395 { saeonly, STRING_COMMA_LEN ("sae") },
396};
397
252b5132
RH		 398/* List of chars besides those in app.c:symbol_chars that can start an
399 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 400const char extra_symbol_chars[] = "*%-([{"
252b5132 401#ifdef LEX_AT
32137342
NC		 402 "@"
403#endif
404#ifdef LEX_QM
405 "?"
252b5132 406#endif
32137342 407 ;
252b5132 408
29b0f896
AM		 409#if (defined (TE_I386AIX) \
410 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 411 && !defined (TE_GNU) \
29b0f896 412 && !defined (TE_LINUX) \
8d63c93e
RM		 413 && !defined (TE_NACL) \
414 && !defined (TE_NETWARE) \
29b0f896 415 && !defined (TE_FreeBSD) \
5b806d27 416 && !defined (TE_DragonFly) \
29b0f896 417 && !defined (TE_NetBSD)))
252b5132 418/* This array holds the chars that always start a comment. If the
b3b91714
AM		 419 pre-processor is disabled, these aren't very useful. The option
420 --divide will remove '/' from this list. */
421const char *i386_comment_chars = "#/";
422#define SVR4_COMMENT_CHARS 1
252b5132 423#define PREFIX_SEPARATOR '\\'
252b5132 424
b3b91714
AM		 425#else
426const char *i386_comment_chars = "#";
427#define PREFIX_SEPARATOR '/'
428#endif
429
252b5132
RH		 430/* This array holds the chars that only start a comment at the beginning of
431 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 432 .line and .file directives will appear in the pre-processed output.
433 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 434 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 435 #NO_APP at the beginning of its output.
436 Also note that comments started like this one will always work if
252b5132 437 '/' isn't otherwise defined. */
b3b91714 438const char line_comment_chars[] = "#/";
252b5132 439
63a0b638 440const char line_separator_chars[] = ";";
252b5132 441
ce8a8b2f
AM		 442/* Chars that can be used to separate mant from exp in floating point
443 nums. */
252b5132
RH		 444const char EXP_CHARS[] = "eE";
445
ce8a8b2f
AM		 446/* Chars that mean this number is a floating point constant
447 As in 0f12.456
448 or 0d1.2345e12. */
252b5132
RH		 449const char FLT_CHARS[] = "fFdDxX";
450
ce8a8b2f 451/* Tables for lexical analysis. */
252b5132
RH		 452static char mnemonic_chars[256];
453static char register_chars[256];
454static char operand_chars[256];
455static char identifier_chars[256];
456static char digit_chars[256];
457
ce8a8b2f 458/* Lexical macros. */
252b5132
RH		 459#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
460#define is_operand_char(x) (operand_chars[(unsigned char) x])
461#define is_register_char(x) (register_chars[(unsigned char) x])
462#define is_space_char(x) ((x) == ' ')
463#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
464#define is_digit_char(x) (digit_chars[(unsigned char) x])
465
0234cb7c 466/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 467static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
468
469/* md_assemble() always leaves the strings it's passed unaltered. To
470 effect this we maintain a stack of saved characters that we've smashed
471 with '\0's (indicating end of strings for various sub-fields of the
47926f60 472 assembler instruction). */
252b5132 473static char save_stack[32];
ce8a8b2f 474static char *save_stack_p;
252b5132
RH		 475#define END_STRING_AND_SAVE(s) \
476 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
477#define RESTORE_END_STRING(s) \
478 do { *(s) = *--save_stack_p; } while (0)
479
47926f60 480/* The instruction we're assembling. */
252b5132
RH		 481static i386_insn i;
482
483/* Possible templates for current insn. */
484static const templates *current_templates;
485
31b2323c
L		 486/* Per instruction expressionS buffers: max displacements & immediates. */
487static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
488static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 489
47926f60 490/* Current operand we are working on. */
ee86248c 491static int this_operand = -1;
252b5132 492
3e73aa7c
JH		 493/* We support four different modes. FLAG_CODE variable is used to distinguish
494 these. */
495
496enum flag_code {
497 CODE_32BIT,
498 CODE_16BIT,
499 CODE_64BIT };
500
501static enum flag_code flag_code;
4fa24527 502static unsigned int object_64bit;
862be3fb 503static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 504static int use_rela_relocations = 0;
505
7af8ed2d
NC		 506#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
507 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
508 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
509
351f65ca
L		 510/* The ELF ABI to use. */
511enum x86_elf_abi
512{
513 I386_ABI,
7f56bc95
L		 514 X86_64_ABI,
515 X86_64_X32_ABI
351f65ca
L		 516};
517
518static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 519#endif
351f65ca 520
167ad85b
TG		 521#if defined (TE_PE) || defined (TE_PEP)
522/* Use big object file format. */
523static int use_big_obj = 0;
524#endif
525
47926f60
KH		 526/* 1 for intel syntax,
527 0 if att syntax. */
528static int intel_syntax = 0;
252b5132 529
1efbbeb4
L		 530/* 1 for intel mnemonic,
531 0 if att mnemonic. */
532static int intel_mnemonic = !SYSV386_COMPAT;
533
5209009a 534/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 535static int old_gcc = OLDGCC_COMPAT;
536
a60de03c
JB		 537/* 1 if pseudo registers are permitted. */
538static int allow_pseudo_reg = 0;
539
47926f60
KH		 540/* 1 if register prefix % not required. */
541static int allow_naked_reg = 0;
252b5132 542
7e8b059b
L		 543/* 1 if the assembler should add BND prefix for all control-tranferring
544 instructions supporting it, even if this prefix wasn't specified
545 explicitly. */
546static int add_bnd_prefix = 0;
547
ba104c83 548/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 549static int allow_index_reg = 0;
550
d022bddd
IT		 551/* 1 if the assembler should ignore LOCK prefix, even if it was
552 specified explicitly. */
553static int omit_lock_prefix = 0;
554
7bab8ab5 555static enum check_kind
daf50ae7 556 {
7bab8ab5
JB		 557 check_none = 0,
558 check_warning,
559 check_error
daf50ae7 560 }
7bab8ab5 561sse_check, operand_check = check_warning;
daf50ae7 562
2ca3ace5
L		 563/* Register prefix used for error message. */
564static const char *register_prefix = "%";
565
47926f60
KH		 566/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
567 leave, push, and pop instructions so that gcc has the same stack
568 frame as in 32 bit mode. */
569static char stackop_size = '\0';
eecb386c 570
12b55ccc
L		 571/* Non-zero to optimize code alignment. */
572int optimize_align_code = 1;
573
47926f60
KH		 574/* Non-zero to quieten some warnings. */
575static int quiet_warnings = 0;
a38cf1db 576
47926f60
KH		 577/* CPU name. */
578static const char *cpu_arch_name = NULL;
6305a203 579static char *cpu_sub_arch_name = NULL;
a38cf1db 580
47926f60 581/* CPU feature flags. */
40fb9820
L		 582static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
583
ccc9c027
L		 584/* If we have selected a cpu we are generating instructions for. */
585static int cpu_arch_tune_set = 0;
586
9103f4f4 587/* Cpu we are generating instructions for. */
fbf3f584 588enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 589
590/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 591static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 592
ccc9c027 593/* CPU instruction set architecture used. */
fbf3f584 594enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 595
9103f4f4 596/* CPU feature flags of instruction set architecture used. */
fbf3f584 597i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 598
fddf5b5b
AM		 599/* If set, conditional jumps are not automatically promoted to handle
600 larger than a byte offset. */
601static unsigned int no_cond_jump_promotion = 0;
602
c0f3af97
L		 603/* Encode SSE instructions with VEX prefix. */
604static unsigned int sse2avx;
605
539f890d
L		 606/* Encode scalar AVX instructions with specific vector length. */
607static enum
608 {
609 vex128 = 0,
610 vex256
611 } avxscalar;
612
43234a1e
L		 613/* Encode scalar EVEX LIG instructions with specific vector length. */
614static enum
615 {
616 evexl128 = 0,
617 evexl256,
618 evexl512
619 } evexlig;
620
621/* Encode EVEX WIG instructions with specific evex.w. */
622static enum
623 {
624 evexw0 = 0,
625 evexw1
626 } evexwig;
627
d3d3c6db
IT		 628/* Value to encode in EVEX RC bits, for SAE-only instructions. */
629static enum rc_type evexrcig = rne;
630
29b0f896 631/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 632static symbolS *GOT_symbol;
29b0f896 633
a4447b93
RH		 634/* The dwarf2 return column, adjusted for 32 or 64 bit. */
635unsigned int x86_dwarf2_return_column;
636
637/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
638int x86_cie_data_alignment;
639
252b5132 640/* Interface to relax_segment.
fddf5b5b
AM		 641 There are 3 major relax states for 386 jump insns because the
642 different types of jumps add different sizes to frags when we're
643 figuring out what sort of jump to choose to reach a given label. */
252b5132 644
47926f60 645/* Types. */
93c2a809
AM		 646#define UNCOND_JUMP 0
647#define COND_JUMP 1
648#define COND_JUMP86 2
fddf5b5b 649
47926f60 650/* Sizes. */
252b5132
RH		 651#define CODE16 1
652#define SMALL 0
29b0f896 653#define SMALL16 (SMALL | CODE16)
252b5132 654#define BIG 2
29b0f896 655#define BIG16 (BIG | CODE16)
252b5132
RH		 656
657#ifndef INLINE
658#ifdef __GNUC__
659#define INLINE __inline__
660#else
661#define INLINE
662#endif
663#endif
664
fddf5b5b
AM		 665#define ENCODE_RELAX_STATE(type, size) \
666 ((relax_substateT) (((type) << 2) | (size)))
667#define TYPE_FROM_RELAX_STATE(s) \
668 ((s) >> 2)
669#define DISP_SIZE_FROM_RELAX_STATE(s) \
670 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 671
672/* This table is used by relax_frag to promote short jumps to long
673 ones where necessary. SMALL (short) jumps may be promoted to BIG
674 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
675 don't allow a short jump in a 32 bit code segment to be promoted to
676 a 16 bit offset jump because it's slower (requires data size
677 prefix), and doesn't work, unless the destination is in the bottom
678 64k of the code segment (The top 16 bits of eip are zeroed). */
679
680const relax_typeS md_relax_table[] =
681{
24eab124
AM		 682 /* The fields are:
683 1) most positive reach of this state,
684 2) most negative reach of this state,
93c2a809 685 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 686 4) which index into the table to try if we can't fit into this one. */
252b5132 687
fddf5b5b 688 /* UNCOND_JUMP states. */
93c2a809
AM		 689 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
690 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
691 /* dword jmp adds 4 bytes to frag:
692 0 extra opcode bytes, 4 displacement bytes. */
252b5132 693 {0, 0, 4, 0},
93c2a809
AM		 694 /* word jmp adds 2 byte2 to frag:
695 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 696 {0, 0, 2, 0},
697
93c2a809
AM		 698 /* COND_JUMP states. */
699 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
700 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
701 /* dword conditionals adds 5 bytes to frag:
702 1 extra opcode byte, 4 displacement bytes. */
703 {0, 0, 5, 0},
fddf5b5b 704 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 705 1 extra opcode byte, 2 displacement bytes. */
706 {0, 0, 3, 0},
707
708 /* COND_JUMP86 states. */
709 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
710 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
711 /* dword conditionals adds 5 bytes to frag:
712 1 extra opcode byte, 4 displacement bytes. */
713 {0, 0, 5, 0},
714 /* word conditionals add 4 bytes to frag:
715 1 displacement byte and a 3 byte long branch insn. */
716 {0, 0, 4, 0}
252b5132
RH		 717};
718
9103f4f4
L		 719static const arch_entry cpu_arch[] =
720{
89507696
JB		 721 /* Do not replace the first two entries - i386_target_format()
722 relies on them being there in this order. */
8a2c8fef 723 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 724 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 725 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 726 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 727 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 728 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 729 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 730 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 731 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 732 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 733 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 734 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 735 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 736 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 737 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 738 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 739 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 740 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 741 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 742 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 743 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 744 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 745 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 746 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 747 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 748 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 749 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 750 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 751 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 752 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 753 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 754 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 755 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 756 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 757 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 758 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 759 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 760 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 761 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 762 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 763 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 764 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 765 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 766 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 767 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
768 CPU_K1OM_FLAGS, 0, 0 },
8a2c8fef 769 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 770 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 771 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 772 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 773 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 774 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 775 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 776 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 777 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 778 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 779 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 780 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 781 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 782 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 783 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 784 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 785 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 786 CPU_BDVER2_FLAGS, 0, 0 },
5e5c50d3
NE		 787 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
788 CPU_BDVER3_FLAGS, 0, 0 },
c7b0bd56
SE		 789 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
790 CPU_BDVER4_FLAGS, 0, 0 },
029f3522
GG		 791 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
792 CPU_ZNVER1_FLAGS, 0, 0 },
7b458c12
L		 793 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
794 CPU_BTVER1_FLAGS, 0, 0 },
795 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
796 CPU_BTVER2_FLAGS, 0, 0 },
8a2c8fef 797 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 798 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 799 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 800 CPU_287_FLAGS, 0, 0 },
8a2c8fef 801 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 802 CPU_387_FLAGS, 0, 0 },
8a2c8fef 803 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 804 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 805 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 806 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 807 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 808 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 809 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 810 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 811 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 812 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 813 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 814 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 815 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 816 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 817 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 818 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 819 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 820 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 821 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 822 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 823 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 824 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 825 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 826 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 827 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
828 CPU_AVX2_FLAGS, 0, 0 },
43234a1e
L		 829 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
830 CPU_AVX512F_FLAGS, 0, 0 },
831 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
832 CPU_AVX512CD_FLAGS, 0, 0 },
833 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
834 CPU_AVX512ER_FLAGS, 0, 0 },
835 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
836 CPU_AVX512PF_FLAGS, 0, 0 },
1dfc6506
L		 837 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
838 CPU_AVX512DQ_FLAGS, 0, 0 },
839 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
840 CPU_AVX512BW_FLAGS, 0, 0 },
841 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
842 CPU_AVX512VL_FLAGS, 0, 0 },
8a2c8fef 843 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 844 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 845 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 846 CPU_VMX_FLAGS, 0, 0 },
8729a6f6
L		 847 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
848 CPU_VMFUNC_FLAGS, 0, 0 },
8a2c8fef 849 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 850 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 851 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 852 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 853 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 854 CPU_XSAVEOPT_FLAGS, 0, 0 },
1dfc6506
L		 855 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
856 CPU_XSAVEC_FLAGS, 0, 0 },
857 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
858 CPU_XSAVES_FLAGS, 0, 0 },
8a2c8fef 859 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 860 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 861 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 862 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 863 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 864 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 865 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 866 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 867 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 868 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 869 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 870 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 871 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
872 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 873 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 874 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 875 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 876 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 877 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 878 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 879 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 880 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 881 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 882 CPU_MOVBE_FLAGS, 0, 0 },
60aa667e
L		 883 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
884 CPU_CX16_FLAGS, 0, 0 },
8a2c8fef 885 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 886 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 887 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
888 CPU_LZCNT_FLAGS, 0, 0 },
42164a71
L		 889 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
890 CPU_HLE_FLAGS, 0, 0 },
891 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
892 CPU_RTM_FLAGS, 0, 0 },
6c30d220
L		 893 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
894 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 895 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 896 CPU_CLFLUSH_FLAGS, 0, 0 },
897 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
898 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 899 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 900 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 901 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 902 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 903 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 904 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 905 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 906 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 907 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 908 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 909 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 910 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 911 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 912 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 913 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 914 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 915 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 916 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 917 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
918 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 919 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
920 CPU_TBM_FLAGS, 0, 0 },
e2e1fcde
L		 921 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
922 CPU_ADX_FLAGS, 0, 0 },
923 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
924 CPU_RDSEED_FLAGS, 0, 0 },
925 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
926 CPU_PRFCHW_FLAGS, 0, 0 },
5c111e37
L		 927 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
928 CPU_SMAP_FLAGS, 0, 0 },
7e8b059b
L		 929 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
930 CPU_MPX_FLAGS, 0, 0 },
a0046408
L		 931 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
932 CPU_SHA_FLAGS, 0, 0 },
963f3586
IT		 933 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
934 CPU_CLFLUSHOPT_FLAGS, 0, 0 },
dcf893b5
IT		 935 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
936 CPU_PREFETCHWT1_FLAGS, 0, 0 },
2cf200a4
IT		 937 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
938 CPU_SE1_FLAGS, 0, 0 },
c5e7287a
IT		 939 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
940 CPU_CLWB_FLAGS, 0, 0 },
9d8596f0
IT		 941 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN,
942 CPU_PCOMMIT_FLAGS, 0, 0 },
2cc1b5aa
IT		 943 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
944 CPU_AVX512IFMA_FLAGS, 0, 0 },
14f195c9
IT		 945 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
946 CPU_AVX512VBMI_FLAGS, 0, 0 },
029f3522
GG		 947 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
948 CPU_CLZERO_FLAGS, 0, 0 },
e413e4e9
AM		 949};
950
704209c0 951#ifdef I386COFF
a6c24e68
NC		 952/* Like s_lcomm_internal in gas/read.c but the alignment string
953 is allowed to be optional. */
954
955static symbolS *
956pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
957{
958 addressT align = 0;
959
960 SKIP_WHITESPACE ();
961
7ab9ffdd 962 if (needs_align
a6c24e68
NC		 963 && *input_line_pointer == ',')
964 {
965 align = parse_align (needs_align - 1);
7ab9ffdd 966
a6c24e68
NC		 967 if (align == (addressT) -1)
968 return NULL;
969 }
970 else
971 {
972 if (size >= 8)
973 align = 3;
974 else if (size >= 4)
975 align = 2;
976 else if (size >= 2)
977 align = 1;
978 else
979 align = 0;
980 }
981
982 bss_alloc (symbolP, size, align);
983 return symbolP;
984}
985
704209c0 986static void
a6c24e68
NC		 987pe_lcomm (int needs_align)
988{
989 s_comm_internal (needs_align * 2, pe_lcomm_internal);
990}
704209c0 991#endif
a6c24e68 992
29b0f896
AM		 993const pseudo_typeS md_pseudo_table[] =
994{
995#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
996 {"align", s_align_bytes, 0},
997#else
998 {"align", s_align_ptwo, 0},
999#endif
1000 {"arch", set_cpu_arch, 0},
1001#ifndef I386COFF
1002 {"bss", s_bss, 0},
a6c24e68
NC		 1003#else
1004 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1005#endif
1006 {"ffloat", float_cons, 'f'},
1007 {"dfloat", float_cons, 'd'},
1008 {"tfloat", float_cons, 'x'},
1009 {"value", cons, 2},
d182319b 1010 {"slong", signed_cons, 4},
29b0f896
AM		 1011 {"noopt", s_ignore, 0},
1012 {"optim", s_ignore, 0},
1013 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1014 {"code16", set_code_flag, CODE_16BIT},
1015 {"code32", set_code_flag, CODE_32BIT},
1016 {"code64", set_code_flag, CODE_64BIT},
1017 {"intel_syntax", set_intel_syntax, 1},
1018 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1019 {"intel_mnemonic", set_intel_mnemonic, 1},
1020 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1021 {"allow_index_reg", set_allow_index_reg, 1},
1022 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1023 {"sse_check", set_check, 0},
1024 {"operand_check", set_check, 1},
3b22753a
L		 1025#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1026 {"largecomm", handle_large_common, 0},
07a53e5c 1027#else
e3bb37b5 1028 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1029 {"loc", dwarf2_directive_loc, 0},
1030 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1031#endif
6482c264
NC		 1032#ifdef TE_PE
1033 {"secrel32", pe_directive_secrel, 0},
1034#endif
29b0f896
AM		 1035 {0, 0, 0}
1036};
1037
1038/* For interface with expression (). */
1039extern char *input_line_pointer;
1040
1041/* Hash table for instruction mnemonic lookup. */
1042static struct hash_control *op_hash;
1043
1044/* Hash table for register lookup. */
1045static struct hash_control *reg_hash;
1046\f
252b5132 1047void
e3bb37b5 1048i386_align_code (fragS *fragP, int count)
252b5132 1049{
ce8a8b2f
AM		 1050 /* Various efficient no-op patterns for aligning code labels.
1051 Note: Don't try to assemble the instructions in the comments.
1052 0L and 0w are not legal. */
252b5132
RH		 1053 static const char f32_1[] =
1054 {0x90}; /* nop */
1055 static const char f32_2[] =
ccc9c027 1056 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 1057 static const char f32_3[] =
1058 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1059 static const char f32_4[] =
1060 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1061 static const char f32_5[] =
1062 {0x90, /* nop */
1063 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1064 static const char f32_6[] =
1065 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1066 static const char f32_7[] =
1067 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1068 static const char f32_8[] =
1069 {0x90, /* nop */
1070 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1071 static const char f32_9[] =
1072 {0x89,0xf6, /* movl %esi,%esi */
1073 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1074 static const char f32_10[] =
1075 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1076 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1077 static const char f32_11[] =
1078 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1079 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1080 static const char f32_12[] =
1081 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1082 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1083 static const char f32_13[] =
1084 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1085 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1086 static const char f32_14[] =
1087 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1088 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 1089 static const char f16_3[] =
1090 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 1091 static const char f16_4[] =
1092 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1093 static const char f16_5[] =
1094 {0x90, /* nop */
1095 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1096 static const char f16_6[] =
1097 {0x89,0xf6, /* mov %si,%si */
1098 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1099 static const char f16_7[] =
1100 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1101 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1102 static const char f16_8[] =
1103 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1104 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 1105 static const char jump_31[] =
1106 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1107 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1108 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1109 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 1110 static const char *const f32_patt[] = {
1111 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1112 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 1113 };
1114 static const char *const f16_patt[] = {
76bc74dc 1115 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1116 };
ccc9c027
L		 1117 /* nopl (%[re]ax) */
1118 static const char alt_3[] =
1119 {0x0f,0x1f,0x00};
1120 /* nopl 0(%[re]ax) */
1121 static const char alt_4[] =
1122 {0x0f,0x1f,0x40,0x00};
1123 /* nopl 0(%[re]ax,%[re]ax,1) */
1124 static const char alt_5[] =
1125 {0x0f,0x1f,0x44,0x00,0x00};
1126 /* nopw 0(%[re]ax,%[re]ax,1) */
1127 static const char alt_6[] =
1128 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1129 /* nopl 0L(%[re]ax) */
1130 static const char alt_7[] =
1131 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1132 /* nopl 0L(%[re]ax,%[re]ax,1) */
1133 static const char alt_8[] =
1134 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1135 /* nopw 0L(%[re]ax,%[re]ax,1) */
1136 static const char alt_9[] =
1137 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1138 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1139 static const char alt_10[] =
1140 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1141 /* data16
1142 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1143 static const char alt_long_11[] =
1144 {0x66,
1145 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1146 /* data16
1147 data16
1148 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1149 static const char alt_long_12[] =
1150 {0x66,
1151 0x66,
1152 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1153 /* data16
1154 data16
1155 data16
1156 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1157 static const char alt_long_13[] =
1158 {0x66,
1159 0x66,
1160 0x66,
1161 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1162 /* data16
1163 data16
1164 data16
1165 data16
1166 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1167 static const char alt_long_14[] =
1168 {0x66,
1169 0x66,
1170 0x66,
1171 0x66,
1172 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1173 /* data16
1174 data16
1175 data16
1176 data16
1177 data16
1178 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1179 static const char alt_long_15[] =
1180 {0x66,
1181 0x66,
1182 0x66,
1183 0x66,
1184 0x66,
1185 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1186 /* nopl 0(%[re]ax,%[re]ax,1)
1187 nopw 0(%[re]ax,%[re]ax,1) */
1188 static const char alt_short_11[] =
1189 {0x0f,0x1f,0x44,0x00,0x00,
1190 0x66,0x0f,0x1f,0x44,0x00,0x00};
1191 /* nopw 0(%[re]ax,%[re]ax,1)
1192 nopw 0(%[re]ax,%[re]ax,1) */
1193 static const char alt_short_12[] =
1194 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1195 0x66,0x0f,0x1f,0x44,0x00,0x00};
1196 /* nopw 0(%[re]ax,%[re]ax,1)
1197 nopl 0L(%[re]ax) */
1198 static const char alt_short_13[] =
1199 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1200 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1201 /* nopl 0L(%[re]ax)
1202 nopl 0L(%[re]ax) */
1203 static const char alt_short_14[] =
1204 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1205 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1206 /* nopl 0L(%[re]ax)
1207 nopl 0L(%[re]ax,%[re]ax,1) */
1208 static const char alt_short_15[] =
1209 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1210 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1211 static const char *const alt_short_patt[] = {
1212 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1213 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
1214 alt_short_14, alt_short_15
1215 };
1216 static const char *const alt_long_patt[] = {
1217 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1218 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1219 alt_long_14, alt_long_15
1220 };
252b5132 1221
76bc74dc
L		 1222 /* Only align for at least a positive non-zero boundary. */
1223 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1224 return;
3e73aa7c 1225
ccc9c027
L		 1226 /* We need to decide which NOP sequence to use for 32bit and
1227 64bit. When -mtune= is used:
4eed87de 1228
76bc74dc
L		 1229 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1230 PROCESSOR_GENERIC32, f32_patt will be used.
1231 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 1232 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1233 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 1234 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
7b458c12 1235 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
69dd9865 1236 will be used.
ccc9c027 1237
76bc74dc 1238 When -mtune= isn't used, alt_long_patt will be used if
22109423 1239 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1240 be used.
ccc9c027
L		 1241
1242 When -march= or .arch is used, we can't use anything beyond
1243 cpu_arch_isa_flags. */
1244
1245 if (flag_code == CODE_16BIT)
1246 {
ccc9c027 1247 if (count > 8)
33fef721 1248 {
76bc74dc
L		 1249 memcpy (fragP->fr_literal + fragP->fr_fix,
1250 jump_31, count);
1251 /* Adjust jump offset. */
1252 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1253 }
76bc74dc
L		 1254 else
1255 memcpy (fragP->fr_literal + fragP->fr_fix,
1256 f16_patt[count - 1], count);
252b5132 1257 }
33fef721 1258 else
ccc9c027
L		 1259 {
1260 const char *const *patt = NULL;
1261
fbf3f584 1262 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1263 {
1264 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1265 switch (cpu_arch_tune)
1266 {
1267 case PROCESSOR_UNKNOWN:
1268 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1269 optimize with nops. */
1270 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1271 patt = alt_long_patt;
ccc9c027
L		 1272 else
1273 patt = f32_patt;
1274 break;
ccc9c027
L		 1275 case PROCESSOR_PENTIUM4:
1276 case PROCESSOR_NOCONA:
ef05d495 1277 case PROCESSOR_CORE:
76bc74dc 1278 case PROCESSOR_CORE2:
bd5295b2 1279 case PROCESSOR_COREI7:
3632d14b 1280 case PROCESSOR_L1OM:
7a9068fe 1281 case PROCESSOR_K1OM:
76bc74dc
L		 1282 case PROCESSOR_GENERIC64:
1283 patt = alt_long_patt;
1284 break;
ccc9c027
L		 1285 case PROCESSOR_K6:
1286 case PROCESSOR_ATHLON:
1287 case PROCESSOR_K8:
4eed87de 1288 case PROCESSOR_AMDFAM10:
8aedb9fe 1289 case PROCESSOR_BD:
029f3522 1290 case PROCESSOR_ZNVER:
7b458c12 1291 case PROCESSOR_BT:
ccc9c027
L		 1292 patt = alt_short_patt;
1293 break;
76bc74dc 1294 case PROCESSOR_I386:
ccc9c027
L		 1295 case PROCESSOR_I486:
1296 case PROCESSOR_PENTIUM:
2dde1948 1297 case PROCESSOR_PENTIUMPRO:
ccc9c027
L		 1298 case PROCESSOR_GENERIC32:
1299 patt = f32_patt;
1300 break;
4eed87de 1301 }
ccc9c027
L		 1302 }
1303 else
1304 {
fbf3f584 1305 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1306 {
1307 case PROCESSOR_UNKNOWN:
e6a14101 1308 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1309 PROCESSOR_UNKNOWN. */
1310 abort ();
1311 break;
1312
76bc74dc 1313 case PROCESSOR_I386:
ccc9c027
L		 1314 case PROCESSOR_I486:
1315 case PROCESSOR_PENTIUM:
ccc9c027
L		 1316 case PROCESSOR_K6:
1317 case PROCESSOR_ATHLON:
1318 case PROCESSOR_K8:
4eed87de 1319 case PROCESSOR_AMDFAM10:
8aedb9fe 1320 case PROCESSOR_BD:
029f3522 1321 case PROCESSOR_ZNVER:
7b458c12 1322 case PROCESSOR_BT:
ccc9c027
L		 1323 case PROCESSOR_GENERIC32:
1324 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1325 with nops. */
1326 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1327 patt = alt_short_patt;
1328 else
1329 patt = f32_patt;
1330 break;
76bc74dc
L		 1331 case PROCESSOR_PENTIUMPRO:
1332 case PROCESSOR_PENTIUM4:
1333 case PROCESSOR_NOCONA:
1334 case PROCESSOR_CORE:
ef05d495 1335 case PROCESSOR_CORE2:
bd5295b2 1336 case PROCESSOR_COREI7:
3632d14b 1337 case PROCESSOR_L1OM:
7a9068fe 1338 case PROCESSOR_K1OM:
22109423 1339 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1340 patt = alt_long_patt;
1341 else
1342 patt = f32_patt;
1343 break;
1344 case PROCESSOR_GENERIC64:
76bc74dc 1345 patt = alt_long_patt;
ccc9c027 1346 break;
4eed87de 1347 }
ccc9c027
L		 1348 }
1349
76bc74dc
L		 1350 if (patt == f32_patt)
1351 {
1352 /* If the padding is less than 15 bytes, we use the normal
1353 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1354 its offset. */
1355 int limit;
76ba9986 1356
711eedef
L		 1357 /* For 64bit, the limit is 3 bytes. */
1358 if (flag_code == CODE_64BIT
1359 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1360 limit = 3;
1361 else
1362 limit = 15;
1363 if (count < limit)
76bc74dc
L		 1364 memcpy (fragP->fr_literal + fragP->fr_fix,
1365 patt[count - 1], count);
1366 else
1367 {
1368 memcpy (fragP->fr_literal + fragP->fr_fix,
1369 jump_31, count);
1370 /* Adjust jump offset. */
1371 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1372 }
1373 }
1374 else
1375 {
1376 /* Maximum length of an instruction is 15 byte. If the
1377 padding is greater than 15 bytes and we don't use jump,
1378 we have to break it into smaller pieces. */
1379 int padding = count;
1380 while (padding > 15)
1381 {
1382 padding -= 15;
1383 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1384 patt [14], 15);
1385 }
1386
1387 if (padding)
1388 memcpy (fragP->fr_literal + fragP->fr_fix,
1389 patt [padding - 1], padding);
1390 }
ccc9c027 1391 }
33fef721 1392 fragP->fr_var = count;
252b5132
RH		 1393}
1394
c6fb90c8 1395static INLINE int
0dfbf9d7 1396operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1397{
0dfbf9d7 1398 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1399 {
1400 case 3:
0dfbf9d7 1401 if (x->array[2])
c6fb90c8
L		 1402 return 0;
1403 case 2:
0dfbf9d7 1404 if (x->array[1])
c6fb90c8
L		 1405 return 0;
1406 case 1:
0dfbf9d7 1407 return !x->array[0];
c6fb90c8
L		 1408 default:
1409 abort ();
1410 }
40fb9820
L		 1411}
1412
c6fb90c8 1413static INLINE void
0dfbf9d7 1414operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1415{
0dfbf9d7 1416 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1417 {
1418 case 3:
0dfbf9d7 1419 x->array[2] = v;
c6fb90c8 1420 case 2:
0dfbf9d7 1421 x->array[1] = v;
c6fb90c8 1422 case 1:
0dfbf9d7 1423 x->array[0] = v;
c6fb90c8
L		 1424 break;
1425 default:
1426 abort ();
1427 }
1428}
40fb9820 1429
c6fb90c8 1430static INLINE int
0dfbf9d7
L		 1431operand_type_equal (const union i386_operand_type *x,
1432 const union i386_operand_type *y)
c6fb90c8 1433{
0dfbf9d7 1434 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1435 {
1436 case 3:
0dfbf9d7 1437 if (x->array[2] != y->array[2])
c6fb90c8
L		 1438 return 0;
1439 case 2:
0dfbf9d7 1440 if (x->array[1] != y->array[1])
c6fb90c8
L		 1441 return 0;
1442 case 1:
0dfbf9d7 1443 return x->array[0] == y->array[0];
c6fb90c8
L		 1444 break;
1445 default:
1446 abort ();
1447 }
1448}
40fb9820 1449
0dfbf9d7
L		 1450static INLINE int
1451cpu_flags_all_zero (const union i386_cpu_flags *x)
1452{
1453 switch (ARRAY_SIZE(x->array))
1454 {
1455 case 3:
1456 if (x->array[2])
1457 return 0;
1458 case 2:
1459 if (x->array[1])
1460 return 0;
1461 case 1:
1462 return !x->array[0];
1463 default:
1464 abort ();
1465 }
1466}
1467
1468static INLINE void
1469cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1470{
1471 switch (ARRAY_SIZE(x->array))
1472 {
1473 case 3:
1474 x->array[2] = v;
1475 case 2:
1476 x->array[1] = v;
1477 case 1:
1478 x->array[0] = v;
1479 break;
1480 default:
1481 abort ();
1482 }
1483}
1484
1485static INLINE int
1486cpu_flags_equal (const union i386_cpu_flags *x,
1487 const union i386_cpu_flags *y)
1488{
1489 switch (ARRAY_SIZE(x->array))
1490 {
1491 case 3:
1492 if (x->array[2] != y->array[2])
1493 return 0;
1494 case 2:
1495 if (x->array[1] != y->array[1])
1496 return 0;
1497 case 1:
1498 return x->array[0] == y->array[0];
1499 break;
1500 default:
1501 abort ();
1502 }
1503}
c6fb90c8
L		 1504
1505static INLINE int
1506cpu_flags_check_cpu64 (i386_cpu_flags f)
1507{
1508 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1509 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1510}
1511
c6fb90c8
L		 1512static INLINE i386_cpu_flags
1513cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1514{
c6fb90c8
L		 1515 switch (ARRAY_SIZE (x.array))
1516 {
1517 case 3:
1518 x.array [2] &= y.array [2];
1519 case 2:
1520 x.array [1] &= y.array [1];
1521 case 1:
1522 x.array [0] &= y.array [0];
1523 break;
1524 default:
1525 abort ();
1526 }
1527 return x;
1528}
40fb9820 1529
c6fb90c8
L		 1530static INLINE i386_cpu_flags
1531cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1532{
c6fb90c8 1533 switch (ARRAY_SIZE (x.array))
40fb9820 1534 {
c6fb90c8
L		 1535 case 3:
1536 x.array [2] |= y.array [2];
1537 case 2:
1538 x.array [1] |= y.array [1];
1539 case 1:
1540 x.array [0] |= y.array [0];
40fb9820
L		 1541 break;
1542 default:
1543 abort ();
1544 }
40fb9820
L		 1545 return x;
1546}
1547
309d3373
JB		 1548static INLINE i386_cpu_flags
1549cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1550{
1551 switch (ARRAY_SIZE (x.array))
1552 {
1553 case 3:
1554 x.array [2] &= ~y.array [2];
1555 case 2:
1556 x.array [1] &= ~y.array [1];
1557 case 1:
1558 x.array [0] &= ~y.array [0];
1559 break;
1560 default:
1561 abort ();
1562 }
1563 return x;
1564}
1565
c0f3af97
L		 1566#define CPU_FLAGS_ARCH_MATCH 0x1
1567#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1568#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1569#define CPU_FLAGS_PCLMUL_MATCH 0x8
1570#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1571
a5ff0eb2 1572#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1573 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1574 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1575#define CPU_FLAGS_PERFECT_MATCH \
1576 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1577
1578/* Return CPU flags match bits. */
3629bb00 1579
40fb9820 1580static int
d3ce72d0 1581cpu_flags_match (const insn_template *t)
40fb9820 1582{
c0f3af97
L		 1583 i386_cpu_flags x = t->cpu_flags;
1584 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1585
1586 x.bitfield.cpu64 = 0;
1587 x.bitfield.cpuno64 = 0;
1588
0dfbf9d7 1589 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1590 {
1591 /* This instruction is available on all archs. */
1592 match |= CPU_FLAGS_32BIT_MATCH;
1593 }
3629bb00
L		 1594 else
1595 {
c0f3af97 1596 /* This instruction is available only on some archs. */
3629bb00
L		 1597 i386_cpu_flags cpu = cpu_arch_flags;
1598
1599 cpu.bitfield.cpu64 = 0;
1600 cpu.bitfield.cpuno64 = 0;
1601 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1602 if (!cpu_flags_all_zero (&cpu))
1603 {
a5ff0eb2
L		 1604 if (x.bitfield.cpuavx)
1605 {
ce2f5b3c 1606 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1607 if (cpu.bitfield.cpuavx)
1608 {
1609 /* Check SSE2AVX. */
1610 if (!t->opcode_modifier.sse2avx|| sse2avx)
1611 {
1612 match |= (CPU_FLAGS_ARCH_MATCH
1613 | CPU_FLAGS_AVX_MATCH);
1614 /* Check AES. */
1615 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1616 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1617 /* Check PCLMUL. */
1618 if (!x.bitfield.cpupclmul
1619 || cpu.bitfield.cpupclmul)
1620 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1621 }
1622 }
1623 else
1624 match |= CPU_FLAGS_ARCH_MATCH;
1625 }
1626 else
c0f3af97
L		 1627 match |= CPU_FLAGS_32BIT_MATCH;
1628 }
3629bb00 1629 }
c0f3af97 1630 return match;
40fb9820
L		 1631}
1632
c6fb90c8
L		 1633static INLINE i386_operand_type
1634operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1635{
c6fb90c8
L		 1636 switch (ARRAY_SIZE (x.array))
1637 {
1638 case 3:
1639 x.array [2] &= y.array [2];
1640 case 2:
1641 x.array [1] &= y.array [1];
1642 case 1:
1643 x.array [0] &= y.array [0];
1644 break;
1645 default:
1646 abort ();
1647 }
1648 return x;
40fb9820
L		 1649}
1650
c6fb90c8
L		 1651static INLINE i386_operand_type
1652operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1653{
c6fb90c8 1654 switch (ARRAY_SIZE (x.array))
40fb9820 1655 {
c6fb90c8
L		 1656 case 3:
1657 x.array [2] |= y.array [2];
1658 case 2:
1659 x.array [1] |= y.array [1];
1660 case 1:
1661 x.array [0] |= y.array [0];
40fb9820
L		 1662 break;
1663 default:
1664 abort ();
1665 }
c6fb90c8
L		 1666 return x;
1667}
40fb9820 1668
c6fb90c8
L		 1669static INLINE i386_operand_type
1670operand_type_xor (i386_operand_type x, i386_operand_type y)
1671{
1672 switch (ARRAY_SIZE (x.array))
1673 {
1674 case 3:
1675 x.array [2] ^= y.array [2];
1676 case 2:
1677 x.array [1] ^= y.array [1];
1678 case 1:
1679 x.array [0] ^= y.array [0];
1680 break;
1681 default:
1682 abort ();
1683 }
40fb9820
L		 1684 return x;
1685}
1686
1687static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1688static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1689static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1690static const i386_operand_type inoutportreg
1691 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1692static const i386_operand_type reg16_inoutportreg
1693 = OPERAND_TYPE_REG16_INOUTPORTREG;
1694static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1695static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1696static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1697static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1698static const i386_operand_type anydisp
1699 = OPERAND_TYPE_ANYDISP;
40fb9820 1700static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1701static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1702static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1703static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1704static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1705static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1706static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1707static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1708static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1709static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1710static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1711static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1712static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1713static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1714
1715enum operand_type
1716{
1717 reg,
40fb9820
L		 1718 imm,
1719 disp,
1720 anymem
1721};
1722
c6fb90c8 1723static INLINE int
40fb9820
L		 1724operand_type_check (i386_operand_type t, enum operand_type c)
1725{
1726 switch (c)
1727 {
1728 case reg:
1729 return (t.bitfield.reg8
1730 || t.bitfield.reg16
1731 || t.bitfield.reg32
1732 || t.bitfield.reg64);
1733
40fb9820
L		 1734 case imm:
1735 return (t.bitfield.imm8
1736 || t.bitfield.imm8s
1737 || t.bitfield.imm16
1738 || t.bitfield.imm32
1739 || t.bitfield.imm32s
1740 || t.bitfield.imm64);
1741
1742 case disp:
1743 return (t.bitfield.disp8
1744 || t.bitfield.disp16
1745 || t.bitfield.disp32
1746 || t.bitfield.disp32s
1747 || t.bitfield.disp64);
1748
1749 case anymem:
1750 return (t.bitfield.disp8
1751 || t.bitfield.disp16
1752 || t.bitfield.disp32
1753 || t.bitfield.disp32s
1754 || t.bitfield.disp64
1755 || t.bitfield.baseindex);
1756
1757 default:
1758 abort ();
1759 }
2cfe26b6
AM		 1760
1761 return 0;
40fb9820
L		 1762}
1763
5c07affc
L		 1764/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1765 operand J for instruction template T. */
1766
1767static INLINE int
d3ce72d0 1768match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1769{
1770 return !((i.types[j].bitfield.byte
1771 && !t->operand_types[j].bitfield.byte)
1772 || (i.types[j].bitfield.word
1773 && !t->operand_types[j].bitfield.word)
1774 || (i.types[j].bitfield.dword
1775 && !t->operand_types[j].bitfield.dword)
1776 || (i.types[j].bitfield.qword
1777 && !t->operand_types[j].bitfield.qword));
1778}
1779
1780/* Return 1 if there is no conflict in any size on operand J for
1781 instruction template T. */
1782
1783static INLINE int
d3ce72d0 1784match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1785{
1786 return (match_reg_size (t, j)
1787 && !((i.types[j].bitfield.unspecified
1788 && !t->operand_types[j].bitfield.unspecified)
1789 || (i.types[j].bitfield.fword
1790 && !t->operand_types[j].bitfield.fword)
1791 || (i.types[j].bitfield.tbyte
1792 && !t->operand_types[j].bitfield.tbyte)
1793 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1794 && !t->operand_types[j].bitfield.xmmword)
1795 || (i.types[j].bitfield.ymmword
43234a1e
L		 1796 && !t->operand_types[j].bitfield.ymmword)
1797 || (i.types[j].bitfield.zmmword
1798 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1799}
1800
1801/* Return 1 if there is no size conflict on any operands for
1802 instruction template T. */
1803
1804static INLINE int
d3ce72d0 1805operand_size_match (const insn_template *t)
5c07affc
L		 1806{
1807 unsigned int j;
1808 int match = 1;
1809
1810 /* Don't check jump instructions. */
1811 if (t->opcode_modifier.jump
1812 || t->opcode_modifier.jumpbyte
1813 || t->opcode_modifier.jumpdword
1814 || t->opcode_modifier.jumpintersegment)
1815 return match;
1816
1817 /* Check memory and accumulator operand size. */
1818 for (j = 0; j < i.operands; j++)
1819 {
1820 if (t->operand_types[j].bitfield.anysize)
1821 continue;
1822
1823 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1824 {
1825 match = 0;
1826 break;
1827 }
1828
1829 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1830 {
1831 match = 0;
1832 break;
1833 }
1834 }
1835
891edac4 1836 if (match)
5c07affc 1837 return match;
891edac4
L		 1838 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1839 {
1840mismatch:
86e026a4 1841 i.error = operand_size_mismatch;
891edac4
L		 1842 return 0;
1843 }
5c07affc
L		 1844
1845 /* Check reverse. */
9c2799c2 1846 gas_assert (i.operands == 2);
5c07affc
L		 1847
1848 match = 1;
1849 for (j = 0; j < 2; j++)
1850 {
1851 if (t->operand_types[j].bitfield.acc
1852 && !match_reg_size (t, j ? 0 : 1))
891edac4 1853 goto mismatch;
5c07affc
L		 1854
1855 if (i.types[j].bitfield.mem
1856 && !match_mem_size (t, j ? 0 : 1))
891edac4 1857 goto mismatch;
5c07affc
L		 1858 }
1859
1860 return match;
1861}
1862
c6fb90c8 1863static INLINE int
40fb9820
L		 1864operand_type_match (i386_operand_type overlap,
1865 i386_operand_type given)
1866{
1867 i386_operand_type temp = overlap;
1868
1869 temp.bitfield.jumpabsolute = 0;
7d5e4556 1870 temp.bitfield.unspecified = 0;
5c07affc
L		 1871 temp.bitfield.byte = 0;
1872 temp.bitfield.word = 0;
1873 temp.bitfield.dword = 0;
1874 temp.bitfield.fword = 0;
1875 temp.bitfield.qword = 0;
1876 temp.bitfield.tbyte = 0;
1877 temp.bitfield.xmmword = 0;
c0f3af97 1878 temp.bitfield.ymmword = 0;
43234a1e 1879 temp.bitfield.zmmword = 0;
0dfbf9d7 1880 if (operand_type_all_zero (&temp))
891edac4 1881 goto mismatch;
40fb9820 1882
891edac4
L		 1883 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1884 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1885 return 1;
1886
1887mismatch:
a65babc9 1888 i.error = operand_type_mismatch;
891edac4 1889 return 0;
40fb9820
L		 1890}
1891
7d5e4556 1892/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1893 unless the expected operand type register overlap is null.
1894 Note that Acc in a template matches every size of reg. */
1895
c6fb90c8 1896static INLINE int
40fb9820
L		 1897operand_type_register_match (i386_operand_type m0,
1898 i386_operand_type g0,
1899 i386_operand_type t0,
1900 i386_operand_type m1,
1901 i386_operand_type g1,
1902 i386_operand_type t1)
1903{
1904 if (!operand_type_check (g0, reg))
1905 return 1;
1906
1907 if (!operand_type_check (g1, reg))
1908 return 1;
1909
1910 if (g0.bitfield.reg8 == g1.bitfield.reg8
1911 && g0.bitfield.reg16 == g1.bitfield.reg16
1912 && g0.bitfield.reg32 == g1.bitfield.reg32
1913 && g0.bitfield.reg64 == g1.bitfield.reg64)
1914 return 1;
1915
1916 if (m0.bitfield.acc)
1917 {
1918 t0.bitfield.reg8 = 1;
1919 t0.bitfield.reg16 = 1;
1920 t0.bitfield.reg32 = 1;
1921 t0.bitfield.reg64 = 1;
1922 }
1923
1924 if (m1.bitfield.acc)
1925 {
1926 t1.bitfield.reg8 = 1;
1927 t1.bitfield.reg16 = 1;
1928 t1.bitfield.reg32 = 1;
1929 t1.bitfield.reg64 = 1;
1930 }
1931
891edac4
L		 1932 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1933 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1934 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1935 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1936 return 1;
1937
a65babc9 1938 i.error = register_type_mismatch;
891edac4
L		 1939
1940 return 0;
40fb9820
L		 1941}
1942
4c692bc7
JB		 1943static INLINE unsigned int
1944register_number (const reg_entry *r)
1945{
1946 unsigned int nr = r->reg_num;
1947
1948 if (r->reg_flags & RegRex)
1949 nr += 8;
1950
1951 return nr;
1952}
1953
252b5132 1954static INLINE unsigned int
40fb9820 1955mode_from_disp_size (i386_operand_type t)
252b5132 1956{
43234a1e 1957 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1958 return 1;
1959 else if (t.bitfield.disp16
1960 || t.bitfield.disp32
1961 || t.bitfield.disp32s)
1962 return 2;
1963 else
1964 return 0;
252b5132
RH		 1965}
1966
1967static INLINE int
65879393 1968fits_in_signed_byte (addressT num)
252b5132 1969{
65879393 1970 return num + 0x80 <= 0xff;
47926f60 1971}
252b5132
RH		 1972
1973static INLINE int
65879393 1974fits_in_unsigned_byte (addressT num)
252b5132 1975{
65879393 1976 return num <= 0xff;
47926f60 1977}
252b5132
RH		 1978
1979static INLINE int
65879393 1980fits_in_unsigned_word (addressT num)
252b5132 1981{
65879393 1982 return num <= 0xffff;
47926f60 1983}
252b5132
RH		 1984
1985static INLINE int
65879393 1986fits_in_signed_word (addressT num)
252b5132 1987{
65879393 1988 return num + 0x8000 <= 0xffff;
47926f60 1989}
2a962e6d 1990
3e73aa7c 1991static INLINE int
65879393 1992fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1993{
1994#ifndef BFD64
1995 return 1;
1996#else
65879393 1997 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 1998#endif
1999} /* fits_in_signed_long() */
2a962e6d 2000
3e73aa7c 2001static INLINE int
65879393 2002fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2003{
2004#ifndef BFD64
2005 return 1;
2006#else
65879393 2007 return num <= 0xffffffff;
3e73aa7c
JH		 2008#endif
2009} /* fits_in_unsigned_long() */
252b5132 2010
43234a1e
L		 2011static INLINE int
2012fits_in_vec_disp8 (offsetT num)
2013{
2014 int shift = i.memshift;
2015 unsigned int mask;
2016
2017 if (shift == -1)
2018 abort ();
2019
2020 mask = (1 << shift) - 1;
2021
2022 /* Return 0 if NUM isn't properly aligned. */
2023 if ((num & mask))
2024 return 0;
2025
2026 /* Check if NUM will fit in 8bit after shift. */
2027 return fits_in_signed_byte (num >> shift);
2028}
2029
a683cc34
SP		 2030static INLINE int
2031fits_in_imm4 (offsetT num)
2032{
2033 return (num & 0xf) == num;
2034}
2035
40fb9820 2036static i386_operand_type
e3bb37b5 2037smallest_imm_type (offsetT num)
252b5132 2038{
40fb9820 2039 i386_operand_type t;
7ab9ffdd 2040
0dfbf9d7 2041 operand_type_set (&t, 0);
40fb9820
L		 2042 t.bitfield.imm64 = 1;
2043
2044 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2045 {
2046 /* This code is disabled on the 486 because all the Imm1 forms
2047 in the opcode table are slower on the i486. They're the
2048 versions with the implicitly specified single-position
2049 displacement, which has another syntax if you really want to
2050 use that form. */
40fb9820
L		 2051 t.bitfield.imm1 = 1;
2052 t.bitfield.imm8 = 1;
2053 t.bitfield.imm8s = 1;
2054 t.bitfield.imm16 = 1;
2055 t.bitfield.imm32 = 1;
2056 t.bitfield.imm32s = 1;
2057 }
2058 else if (fits_in_signed_byte (num))
2059 {
2060 t.bitfield.imm8 = 1;
2061 t.bitfield.imm8s = 1;
2062 t.bitfield.imm16 = 1;
2063 t.bitfield.imm32 = 1;
2064 t.bitfield.imm32s = 1;
2065 }
2066 else if (fits_in_unsigned_byte (num))
2067 {
2068 t.bitfield.imm8 = 1;
2069 t.bitfield.imm16 = 1;
2070 t.bitfield.imm32 = 1;
2071 t.bitfield.imm32s = 1;
2072 }
2073 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2074 {
2075 t.bitfield.imm16 = 1;
2076 t.bitfield.imm32 = 1;
2077 t.bitfield.imm32s = 1;
2078 }
2079 else if (fits_in_signed_long (num))
2080 {
2081 t.bitfield.imm32 = 1;
2082 t.bitfield.imm32s = 1;
2083 }
2084 else if (fits_in_unsigned_long (num))
2085 t.bitfield.imm32 = 1;
2086
2087 return t;
47926f60 2088}
252b5132 2089
847f7ad4 2090static offsetT
e3bb37b5 2091offset_in_range (offsetT val, int size)
847f7ad4 2092{
508866be 2093 addressT mask;
ba2adb93 2094
847f7ad4
AM		 2095 switch (size)
2096 {
508866be
L		 2097 case 1: mask = ((addressT) 1 << 8) - 1; break;
2098 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2099 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2100#ifdef BFD64
2101 case 8: mask = ((addressT) 2 << 63) - 1; break;
2102#endif
47926f60 2103 default: abort ();
847f7ad4
AM		 2104 }
2105
9de868bf
L		 2106#ifdef BFD64
2107 /* If BFD64, sign extend val for 32bit address mode. */
2108 if (flag_code != CODE_64BIT
2109 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2110 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2111 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2112#endif
ba2adb93 2113
47926f60 2114 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2115 {
2116 char buf1[40], buf2[40];
2117
2118 sprint_value (buf1, val);
2119 sprint_value (buf2, val & mask);
2120 as_warn (_("%s shortened to %s"), buf1, buf2);
2121 }
2122 return val & mask;
2123}
2124
c32fa91d
L		 2125enum PREFIX_GROUP
2126{
2127 PREFIX_EXIST = 0,
2128 PREFIX_LOCK,
2129 PREFIX_REP,
2130 PREFIX_OTHER
2131};
2132
2133/* Returns
2134 a. PREFIX_EXIST if attempting to add a prefix where one from the
2135 same class already exists.
2136 b. PREFIX_LOCK if lock prefix is added.
2137 c. PREFIX_REP if rep/repne prefix is added.
2138 d. PREFIX_OTHER if other prefix is added.
2139 */
2140
2141static enum PREFIX_GROUP
e3bb37b5 2142add_prefix (unsigned int prefix)
252b5132 2143{
c32fa91d 2144 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2145 unsigned int q;
252b5132 2146
29b0f896
AM		 2147 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2148 && flag_code == CODE_64BIT)
b1905489 2149 {
161a04f6
L		 2150 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2151 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2152 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2153 ret = PREFIX_EXIST;
b1905489
JB		 2154 q = REX_PREFIX;
2155 }
3e73aa7c 2156 else
b1905489
JB		 2157 {
2158 switch (prefix)
2159 {
2160 default:
2161 abort ();
2162
2163 case CS_PREFIX_OPCODE:
2164 case DS_PREFIX_OPCODE:
2165 case ES_PREFIX_OPCODE:
2166 case FS_PREFIX_OPCODE:
2167 case GS_PREFIX_OPCODE:
2168 case SS_PREFIX_OPCODE:
2169 q = SEG_PREFIX;
2170 break;
2171
2172 case REPNE_PREFIX_OPCODE:
2173 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2174 q = REP_PREFIX;
2175 ret = PREFIX_REP;
2176 break;
2177
b1905489 2178 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2179 q = LOCK_PREFIX;
2180 ret = PREFIX_LOCK;
b1905489
JB		 2181 break;
2182
2183 case FWAIT_OPCODE:
2184 q = WAIT_PREFIX;
2185 break;
2186
2187 case ADDR_PREFIX_OPCODE:
2188 q = ADDR_PREFIX;
2189 break;
2190
2191 case DATA_PREFIX_OPCODE:
2192 q = DATA_PREFIX;
2193 break;
2194 }
2195 if (i.prefix[q] != 0)
c32fa91d 2196 ret = PREFIX_EXIST;
b1905489 2197 }
252b5132 2198
b1905489 2199 if (ret)
252b5132 2200 {
b1905489
JB		 2201 if (!i.prefix[q])
2202 ++i.prefixes;
2203 i.prefix[q] |= prefix;
252b5132 2204 }
b1905489
JB		 2205 else
2206 as_bad (_("same type of prefix used twice"));
252b5132 2207
252b5132
RH		 2208 return ret;
2209}
2210
2211static void
78f12dd3 2212update_code_flag (int value, int check)
eecb386c 2213{
78f12dd3
L		 2214 PRINTF_LIKE ((*as_error));
2215
1e9cc1c2 2216 flag_code = (enum flag_code) value;
40fb9820
L		 2217 if (flag_code == CODE_64BIT)
2218 {
2219 cpu_arch_flags.bitfield.cpu64 = 1;
2220 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2221 }
2222 else
2223 {
2224 cpu_arch_flags.bitfield.cpu64 = 0;
2225 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2226 }
2227 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2228 {
78f12dd3
L		 2229 if (check)
2230 as_error = as_fatal;
2231 else
2232 as_error = as_bad;
2233 (*as_error) (_("64bit mode not supported on `%s'."),
2234 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2235 }
40fb9820 2236 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2237 {
78f12dd3
L		 2238 if (check)
2239 as_error = as_fatal;
2240 else
2241 as_error = as_bad;
2242 (*as_error) (_("32bit mode not supported on `%s'."),
2243 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2244 }
eecb386c
AM		 2245 stackop_size = '\0';
2246}
2247
78f12dd3
L		 2248static void
2249set_code_flag (int value)
2250{
2251 update_code_flag (value, 0);
2252}
2253
eecb386c 2254static void
e3bb37b5 2255set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2256{
1e9cc1c2 2257 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2258 if (flag_code != CODE_16BIT)
2259 abort ();
2260 cpu_arch_flags.bitfield.cpu64 = 0;
2261 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2262 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2263}
2264
2265static void
e3bb37b5 2266set_intel_syntax (int syntax_flag)
252b5132
RH		 2267{
2268 /* Find out if register prefixing is specified. */
2269 int ask_naked_reg = 0;
2270
2271 SKIP_WHITESPACE ();
29b0f896 2272 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2273 {
2274 char *string = input_line_pointer;
2275 int e = get_symbol_end ();
2276
47926f60 2277 if (strcmp (string, "prefix") == 0)
252b5132 2278 ask_naked_reg = 1;
47926f60 2279 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2280 ask_naked_reg = -1;
2281 else
d0b47220 2282 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2283 *input_line_pointer = e;
2284 }
2285 demand_empty_rest_of_line ();
c3332e24 2286
252b5132
RH		 2287 intel_syntax = syntax_flag;
2288
2289 if (ask_naked_reg == 0)
f86103b7
AM		 2290 allow_naked_reg = (intel_syntax
2291 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2292 else
2293 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2294
ee86248c 2295 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2296
e4a3b5a4 2297 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2298 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2299 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2300}
2301
1efbbeb4
L		 2302static void
2303set_intel_mnemonic (int mnemonic_flag)
2304{
e1d4d893 2305 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2306}
2307
db51cc60
L		 2308static void
2309set_allow_index_reg (int flag)
2310{
2311 allow_index_reg = flag;
2312}
2313
cb19c032 2314static void
7bab8ab5 2315set_check (int what)
cb19c032 2316{
7bab8ab5
JB		 2317 enum check_kind *kind;
2318 const char *str;
2319
2320 if (what)
2321 {
2322 kind = &operand_check;
2323 str = "operand";
2324 }
2325 else
2326 {
2327 kind = &sse_check;
2328 str = "sse";
2329 }
2330
cb19c032
L		 2331 SKIP_WHITESPACE ();
2332
2333 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2334 {
2335 char *string = input_line_pointer;
2336 int e = get_symbol_end ();
2337
2338 if (strcmp (string, "none") == 0)
7bab8ab5 2339 *kind = check_none;
cb19c032 2340 else if (strcmp (string, "warning") == 0)
7bab8ab5 2341 *kind = check_warning;
cb19c032 2342 else if (strcmp (string, "error") == 0)
7bab8ab5 2343 *kind = check_error;
cb19c032 2344 else
7bab8ab5 2345 as_bad (_("bad argument to %s_check directive."), str);
cb19c032
L		 2346 *input_line_pointer = e;
2347 }
2348 else
7bab8ab5 2349 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2350
2351 demand_empty_rest_of_line ();
2352}
2353
8a9036a4
L		 2354static void
2355check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2356 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2357{
2358#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2359 static const char *arch;
2360
2361 /* Intel LIOM is only supported on ELF. */
2362 if (!IS_ELF)
2363 return;
2364
2365 if (!arch)
2366 {
2367 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2368 use default_arch. */
2369 arch = cpu_arch_name;
2370 if (!arch)
2371 arch = default_arch;
2372 }
2373
3632d14b 2374 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2375 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2376 || new_flag.bitfield.cpul1om)
8a9036a4 2377 return;
76ba9986 2378
7a9068fe
L		 2379 /* If we are targeting Intel K1OM, we must enable it. */
2380 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2381 || new_flag.bitfield.cpuk1om)
2382 return;
2383
8a9036a4
L		 2384 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2385#endif
2386}
2387
e413e4e9 2388static void
e3bb37b5 2389set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2390{
47926f60 2391 SKIP_WHITESPACE ();
e413e4e9 2392
29b0f896 2393 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2394 {
2395 char *string = input_line_pointer;
2396 int e = get_symbol_end ();
91d6fa6a 2397 unsigned int j;
40fb9820 2398 i386_cpu_flags flags;
e413e4e9 2399
91d6fa6a 2400 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2401 {
91d6fa6a 2402 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2403 {
91d6fa6a 2404 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2405
5c6af06e
JB		 2406 if (*string != '.')
2407 {
91d6fa6a 2408 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2409 cpu_sub_arch_name = NULL;
91d6fa6a 2410 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2411 if (flag_code == CODE_64BIT)
2412 {
2413 cpu_arch_flags.bitfield.cpu64 = 1;
2414 cpu_arch_flags.bitfield.cpuno64 = 0;
2415 }
2416 else
2417 {
2418 cpu_arch_flags.bitfield.cpu64 = 0;
2419 cpu_arch_flags.bitfield.cpuno64 = 1;
2420 }
91d6fa6a
NC		 2421 cpu_arch_isa = cpu_arch[j].type;
2422 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2423 if (!cpu_arch_tune_set)
2424 {
2425 cpu_arch_tune = cpu_arch_isa;
2426 cpu_arch_tune_flags = cpu_arch_isa_flags;
2427 }
5c6af06e
JB		 2428 break;
2429 }
40fb9820 2430
22109423 2431 if (!cpu_arch[j].negated)
309d3373 2432 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2433 cpu_arch[j].flags);
309d3373
JB		 2434 else
2435 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2436 cpu_arch[j].flags);
0dfbf9d7 2437 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2438 {
6305a203
L		 2439 if (cpu_sub_arch_name)
2440 {
2441 char *name = cpu_sub_arch_name;
2442 cpu_sub_arch_name = concat (name,
91d6fa6a 2443 cpu_arch[j].name,
1bf57e9f 2444 (const char *) NULL);
6305a203
L		 2445 free (name);
2446 }
2447 else
91d6fa6a 2448 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2449 cpu_arch_flags = flags;
a586129e 2450 cpu_arch_isa_flags = flags;
5c6af06e
JB		 2451 }
2452 *input_line_pointer = e;
2453 demand_empty_rest_of_line ();
2454 return;
e413e4e9
AM		 2455 }
2456 }
91d6fa6a 2457 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2458 as_bad (_("no such architecture: `%s'"), string);
2459
2460 *input_line_pointer = e;
2461 }
2462 else
2463 as_bad (_("missing cpu architecture"));
2464
fddf5b5b
AM		 2465 no_cond_jump_promotion = 0;
2466 if (*input_line_pointer == ','
29b0f896 2467 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2468 {
2469 char *string = ++input_line_pointer;
2470 int e = get_symbol_end ();
2471
2472 if (strcmp (string, "nojumps") == 0)
2473 no_cond_jump_promotion = 1;
2474 else if (strcmp (string, "jumps") == 0)
2475 ;
2476 else
2477 as_bad (_("no such architecture modifier: `%s'"), string);
2478
2479 *input_line_pointer = e;
2480 }
2481
e413e4e9
AM		 2482 demand_empty_rest_of_line ();
2483}
2484
8a9036a4
L		 2485enum bfd_architecture
2486i386_arch (void)
2487{
3632d14b 2488 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2489 {
2490 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2491 || flag_code != CODE_64BIT)
2492 as_fatal (_("Intel L1OM is 64bit ELF only"));
2493 return bfd_arch_l1om;
2494 }
7a9068fe
L		 2495 else if (cpu_arch_isa == PROCESSOR_K1OM)
2496 {
2497 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2498 || flag_code != CODE_64BIT)
2499 as_fatal (_("Intel K1OM is 64bit ELF only"));
2500 return bfd_arch_k1om;
2501 }
8a9036a4
L		 2502 else
2503 return bfd_arch_i386;
2504}
2505
b9d79e03 2506unsigned long
7016a5d5 2507i386_mach (void)
b9d79e03 2508{
351f65ca 2509 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2510 {
3632d14b 2511 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2512 {
351f65ca
L		 2513 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2514 || default_arch[6] != '\0')
8a9036a4
L		 2515 as_fatal (_("Intel L1OM is 64bit ELF only"));
2516 return bfd_mach_l1om;
2517 }
7a9068fe
L		 2518 else if (cpu_arch_isa == PROCESSOR_K1OM)
2519 {
2520 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2521 || default_arch[6] != '\0')
2522 as_fatal (_("Intel K1OM is 64bit ELF only"));
2523 return bfd_mach_k1om;
2524 }
351f65ca 2525 else if (default_arch[6] == '\0')
8a9036a4 2526 return bfd_mach_x86_64;
351f65ca
L		 2527 else
2528 return bfd_mach_x64_32;
8a9036a4 2529 }
b9d79e03
JH		 2530 else if (!strcmp (default_arch, "i386"))
2531 return bfd_mach_i386_i386;
2532 else
2b5d6a91 2533 as_fatal (_("unknown architecture"));
b9d79e03 2534}
b9d79e03 2535\f
252b5132 2536void
7016a5d5 2537md_begin (void)
252b5132
RH		 2538{
2539 const char *hash_err;
2540
47926f60 2541 /* Initialize op_hash hash table. */
252b5132
RH		 2542 op_hash = hash_new ();
2543
2544 {
d3ce72d0 2545 const insn_template *optab;
29b0f896 2546 templates *core_optab;
252b5132 2547
47926f60
KH		 2548 /* Setup for loop. */
2549 optab = i386_optab;
252b5132
RH		 2550 core_optab = (templates *) xmalloc (sizeof (templates));
2551 core_optab->start = optab;
2552
2553 while (1)
2554 {
2555 ++optab;
2556 if (optab->name == NULL
2557 || strcmp (optab->name, (optab - 1)->name) != 0)
2558 {
2559 /* different name --> ship out current template list;
47926f60 2560 add to hash table; & begin anew. */
252b5132
RH		 2561 core_optab->end = optab;
2562 hash_err = hash_insert (op_hash,
2563 (optab - 1)->name,
5a49b8ac 2564 (void *) core_optab);
252b5132
RH		 2565 if (hash_err)
2566 {
b37df7c4 2567 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2568 (optab - 1)->name,
2569 hash_err);
2570 }
2571 if (optab->name == NULL)
2572 break;
2573 core_optab = (templates *) xmalloc (sizeof (templates));
2574 core_optab->start = optab;
2575 }
2576 }
2577 }
2578
47926f60 2579 /* Initialize reg_hash hash table. */
252b5132
RH		 2580 reg_hash = hash_new ();
2581 {
29b0f896 2582 const reg_entry *regtab;
c3fe08fa 2583 unsigned int regtab_size = i386_regtab_size;
252b5132 2584
c3fe08fa 2585 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2586 {
5a49b8ac 2587 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2588 if (hash_err)
b37df7c4 2589 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2590 regtab->reg_name,
2591 hash_err);
252b5132
RH		 2592 }
2593 }
2594
47926f60 2595 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2596 {
29b0f896
AM		 2597 int c;
2598 char *p;
252b5132
RH		 2599
2600 for (c = 0; c < 256; c++)
2601 {
3882b010 2602 if (ISDIGIT (c))
252b5132
RH		 2603 {
2604 digit_chars[c] = c;
2605 mnemonic_chars[c] = c;
2606 register_chars[c] = c;
2607 operand_chars[c] = c;
2608 }
3882b010 2609 else if (ISLOWER (c))
252b5132
RH		 2610 {
2611 mnemonic_chars[c] = c;
2612 register_chars[c] = c;
2613 operand_chars[c] = c;
2614 }
3882b010 2615 else if (ISUPPER (c))
252b5132 2616 {
3882b010 2617 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2618 register_chars[c] = mnemonic_chars[c];
2619 operand_chars[c] = c;
2620 }
43234a1e
L		 2621 else if (c == '{' || c == '}')
2622 operand_chars[c] = c;
252b5132 2623
3882b010 2624 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2625 identifier_chars[c] = c;
2626 else if (c >= 128)
2627 {
2628 identifier_chars[c] = c;
2629 operand_chars[c] = c;
2630 }
2631 }
2632
2633#ifdef LEX_AT
2634 identifier_chars['@'] = '@';
32137342
NC		 2635#endif
2636#ifdef LEX_QM
2637 identifier_chars['?'] = '?';
2638 operand_chars['?'] = '?';
252b5132 2639#endif
252b5132 2640 digit_chars['-'] = '-';
c0f3af97 2641 mnemonic_chars['_'] = '_';
791fe849 2642 mnemonic_chars['-'] = '-';
0003779b 2643 mnemonic_chars['.'] = '.';
252b5132
RH		 2644 identifier_chars['_'] = '_';
2645 identifier_chars['.'] = '.';
2646
2647 for (p = operand_special_chars; *p != '\0'; p++)
2648 operand_chars[(unsigned char) *p] = *p;
2649 }
2650
a4447b93
RH		 2651 if (flag_code == CODE_64BIT)
2652 {
ca19b261
KT		 2653#if defined (OBJ_COFF) && defined (TE_PE)
2654 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2655 ? 32 : 16);
2656#else
a4447b93 2657 x86_dwarf2_return_column = 16;
ca19b261 2658#endif
61ff971f 2659 x86_cie_data_alignment = -8;
a4447b93
RH		 2660 }
2661 else
2662 {
2663 x86_dwarf2_return_column = 8;
2664 x86_cie_data_alignment = -4;
2665 }
252b5132
RH		 2666}
2667
2668void
e3bb37b5 2669i386_print_statistics (FILE *file)
252b5132
RH		 2670{
2671 hash_print_statistics (file, "i386 opcode", op_hash);
2672 hash_print_statistics (file, "i386 register", reg_hash);
2673}
2674\f
252b5132
RH		 2675#ifdef DEBUG386
2676
ce8a8b2f 2677/* Debugging routines for md_assemble. */
d3ce72d0 2678static void pte (insn_template *);
40fb9820 2679static void pt (i386_operand_type);
e3bb37b5
L		 2680static void pe (expressionS *);
2681static void ps (symbolS *);
252b5132
RH		 2682
2683static void
e3bb37b5 2684pi (char *line, i386_insn *x)
252b5132 2685{
09137c09 2686 unsigned int j;
252b5132
RH		 2687
2688 fprintf (stdout, "%s: template ", line);
2689 pte (&x->tm);
09f131f2
JH		 2690 fprintf (stdout, " address: base %s index %s scale %x\n",
2691 x->base_reg ? x->base_reg->reg_name : "none",
2692 x->index_reg ? x->index_reg->reg_name : "none",
2693 x->log2_scale_factor);
2694 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2695 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2696 fprintf (stdout, " sib: base %x index %x scale %x\n",
2697 x->sib.base, x->sib.index, x->sib.scale);
2698 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2699 (x->rex & REX_W) != 0,
2700 (x->rex & REX_R) != 0,
2701 (x->rex & REX_X) != 0,
2702 (x->rex & REX_B) != 0);
09137c09 2703 for (j = 0; j < x->operands; j++)
252b5132 2704 {
09137c09
SP		 2705 fprintf (stdout, " #%d: ", j + 1);
2706 pt (x->types[j]);
252b5132 2707 fprintf (stdout, "\n");
09137c09
SP		 2708 if (x->types[j].bitfield.reg8
2709 || x->types[j].bitfield.reg16
2710 || x->types[j].bitfield.reg32
2711 || x->types[j].bitfield.reg64
2712 || x->types[j].bitfield.regmmx
2713 || x->types[j].bitfield.regxmm
2714 || x->types[j].bitfield.regymm
43234a1e 2715 || x->types[j].bitfield.regzmm
09137c09
SP		 2716 || x->types[j].bitfield.sreg2
2717 || x->types[j].bitfield.sreg3
2718 || x->types[j].bitfield.control
2719 || x->types[j].bitfield.debug
2720 || x->types[j].bitfield.test)
2721 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2722 if (operand_type_check (x->types[j], imm))
2723 pe (x->op[j].imms);
2724 if (operand_type_check (x->types[j], disp))
2725 pe (x->op[j].disps);
252b5132
RH		 2726 }
2727}
2728
2729static void
d3ce72d0 2730pte (insn_template *t)
252b5132 2731{
09137c09 2732 unsigned int j;
252b5132 2733 fprintf (stdout, " %d operands ", t->operands);
47926f60 2734 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2735 if (t->extension_opcode != None)
2736 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2737 if (t->opcode_modifier.d)
252b5132 2738 fprintf (stdout, "D");
40fb9820 2739 if (t->opcode_modifier.w)
252b5132
RH		 2740 fprintf (stdout, "W");
2741 fprintf (stdout, "\n");
09137c09 2742 for (j = 0; j < t->operands; j++)
252b5132 2743 {
09137c09
SP		 2744 fprintf (stdout, " #%d type ", j + 1);
2745 pt (t->operand_types[j]);
252b5132
RH		 2746 fprintf (stdout, "\n");
2747 }
2748}
2749
2750static void
e3bb37b5 2751pe (expressionS *e)
252b5132 2752{
24eab124 2753 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2754 fprintf (stdout, " add_number %ld (%lx)\n",
2755 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2756 if (e->X_add_symbol)
2757 {
2758 fprintf (stdout, " add_symbol ");
2759 ps (e->X_add_symbol);
2760 fprintf (stdout, "\n");
2761 }
2762 if (e->X_op_symbol)
2763 {
2764 fprintf (stdout, " op_symbol ");
2765 ps (e->X_op_symbol);
2766 fprintf (stdout, "\n");
2767 }
2768}
2769
2770static void
e3bb37b5 2771ps (symbolS *s)
252b5132
RH		 2772{
2773 fprintf (stdout, "%s type %s%s",
2774 S_GET_NAME (s),
2775 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2776 segment_name (S_GET_SEGMENT (s)));
2777}
2778
7b81dfbb 2779static struct type_name
252b5132 2780 {
40fb9820
L		 2781 i386_operand_type mask;
2782 const char *name;
252b5132 2783 }
7b81dfbb 2784const type_names[] =
252b5132 2785{
40fb9820
L		 2786 { OPERAND_TYPE_REG8, "r8" },
2787 { OPERAND_TYPE_REG16, "r16" },
2788 { OPERAND_TYPE_REG32, "r32" },
2789 { OPERAND_TYPE_REG64, "r64" },
2790 { OPERAND_TYPE_IMM8, "i8" },
2791 { OPERAND_TYPE_IMM8, "i8s" },
2792 { OPERAND_TYPE_IMM16, "i16" },
2793 { OPERAND_TYPE_IMM32, "i32" },
2794 { OPERAND_TYPE_IMM32S, "i32s" },
2795 { OPERAND_TYPE_IMM64, "i64" },
2796 { OPERAND_TYPE_IMM1, "i1" },
2797 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2798 { OPERAND_TYPE_DISP8, "d8" },
2799 { OPERAND_TYPE_DISP16, "d16" },
2800 { OPERAND_TYPE_DISP32, "d32" },
2801 { OPERAND_TYPE_DISP32S, "d32s" },
2802 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2803 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2804 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2805 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2806 { OPERAND_TYPE_CONTROL, "control reg" },
2807 { OPERAND_TYPE_TEST, "test reg" },
2808 { OPERAND_TYPE_DEBUG, "debug reg" },
2809 { OPERAND_TYPE_FLOATREG, "FReg" },
2810 { OPERAND_TYPE_FLOATACC, "FAcc" },
2811 { OPERAND_TYPE_SREG2, "SReg2" },
2812 { OPERAND_TYPE_SREG3, "SReg3" },
2813 { OPERAND_TYPE_ACC, "Acc" },
2814 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2815 { OPERAND_TYPE_REGMMX, "rMMX" },
2816 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2817 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2818 { OPERAND_TYPE_REGZMM, "rZMM" },
2819 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2820 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2821};
2822
2823static void
40fb9820 2824pt (i386_operand_type t)
252b5132 2825{
40fb9820 2826 unsigned int j;
c6fb90c8 2827 i386_operand_type a;
252b5132 2828
40fb9820 2829 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2830 {
2831 a = operand_type_and (t, type_names[j].mask);
0349dc08 2832 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2833 fprintf (stdout, "%s, ", type_names[j].name);
2834 }
252b5132
RH		 2835 fflush (stdout);
2836}
2837
2838#endif /* DEBUG386 */
2839\f
252b5132 2840static bfd_reloc_code_real_type
3956db08 2841reloc (unsigned int size,
64e74474
AM		 2842 int pcrel,
2843 int sign,
2844 bfd_reloc_code_real_type other)
252b5132 2845{
47926f60 2846 if (other != NO_RELOC)
3956db08 2847 {
91d6fa6a 2848 reloc_howto_type *rel;
3956db08
JB		 2849
2850 if (size == 8)
2851 switch (other)
2852 {
64e74474
AM		 2853 case BFD_RELOC_X86_64_GOT32:
2854 return BFD_RELOC_X86_64_GOT64;
2855 break;
553d1284
L		 2856 case BFD_RELOC_X86_64_GOTPLT64:
2857 return BFD_RELOC_X86_64_GOTPLT64;
2858 break;
64e74474
AM		 2859 case BFD_RELOC_X86_64_PLTOFF64:
2860 return BFD_RELOC_X86_64_PLTOFF64;
2861 break;
2862 case BFD_RELOC_X86_64_GOTPC32:
2863 other = BFD_RELOC_X86_64_GOTPC64;
2864 break;
2865 case BFD_RELOC_X86_64_GOTPCREL:
2866 other = BFD_RELOC_X86_64_GOTPCREL64;
2867 break;
2868 case BFD_RELOC_X86_64_TPOFF32:
2869 other = BFD_RELOC_X86_64_TPOFF64;
2870 break;
2871 case BFD_RELOC_X86_64_DTPOFF32:
2872 other = BFD_RELOC_X86_64_DTPOFF64;
2873 break;
2874 default:
2875 break;
3956db08 2876 }
e05278af 2877
8ce3d284 2878#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2879 if (other == BFD_RELOC_SIZE32)
2880 {
2881 if (size == 8)
1ab668bf 2882 other = BFD_RELOC_SIZE64;
8fd4256d 2883 if (pcrel)
1ab668bf
AM		 2884 {
2885 as_bad (_("there are no pc-relative size relocations"));
2886 return NO_RELOC;
2887 }
8fd4256d 2888 }
8ce3d284 2889#endif
8fd4256d 2890
e05278af 2891 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2892 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2893 sign = -1;
2894
91d6fa6a
NC		 2895 rel = bfd_reloc_type_lookup (stdoutput, other);
2896 if (!rel)
3956db08 2897 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2898 else if (size != bfd_get_reloc_size (rel))
3956db08 2899 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2900 bfd_get_reloc_size (rel),
3956db08 2901 size);
91d6fa6a 2902 else if (pcrel && !rel->pc_relative)
3956db08 2903 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2904 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2905 && !sign)
91d6fa6a 2906 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2907 && sign > 0))
3956db08
JB		 2908 as_bad (_("relocated field and relocation type differ in signedness"));
2909 else
2910 return other;
2911 return NO_RELOC;
2912 }
252b5132
RH		 2913
2914 if (pcrel)
2915 {
3e73aa7c 2916 if (!sign)
3956db08 2917 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2918 switch (size)
2919 {
2920 case 1: return BFD_RELOC_8_PCREL;
2921 case 2: return BFD_RELOC_16_PCREL;
d258b828 2922 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2923 case 8: return BFD_RELOC_64_PCREL;
252b5132 2924 }
3956db08 2925 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2926 }
2927 else
2928 {
3956db08 2929 if (sign > 0)
e5cb08ac 2930 switch (size)
3e73aa7c
JH		 2931 {
2932 case 4: return BFD_RELOC_X86_64_32S;
2933 }
2934 else
2935 switch (size)
2936 {
2937 case 1: return BFD_RELOC_8;
2938 case 2: return BFD_RELOC_16;
2939 case 4: return BFD_RELOC_32;
2940 case 8: return BFD_RELOC_64;
2941 }
3956db08
JB		 2942 as_bad (_("cannot do %s %u byte relocation"),
2943 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2944 }
2945
0cc9e1d3 2946 return NO_RELOC;
252b5132
RH		 2947}
2948
47926f60
KH		 2949/* Here we decide which fixups can be adjusted to make them relative to
2950 the beginning of the section instead of the symbol. Basically we need
2951 to make sure that the dynamic relocations are done correctly, so in
2952 some cases we force the original symbol to be used. */
2953
252b5132 2954int
e3bb37b5 2955tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2956{
6d249963 2957#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2958 if (!IS_ELF)
31312f95
AM		 2959 return 1;
2960
a161fe53
AM		 2961 /* Don't adjust pc-relative references to merge sections in 64-bit
2962 mode. */
2963 if (use_rela_relocations
2964 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2965 && fixP->fx_pcrel)
252b5132 2966 return 0;
31312f95 2967
8d01d9a9
AJ		 2968 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2969 and changed later by validate_fix. */
2970 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2971 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2972 return 0;
2973
8fd4256d
L		 2974 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2975 for size relocations. */
2976 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2977 || fixP->fx_r_type == BFD_RELOC_SIZE64
2978 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2979 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2980 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2981 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2982 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2983 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2984 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2985 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2986 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2987 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2988 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2989 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2990 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2991 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2992 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2993 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2994 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2995 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2996 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2997 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2998 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2999 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3000 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3001 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3002 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3003 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3004 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3005 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3006 return 0;
31312f95 3007#endif
252b5132
RH		 3008 return 1;
3009}
252b5132 3010
b4cac588 3011static int
e3bb37b5 3012intel_float_operand (const char *mnemonic)
252b5132 3013{
9306ca4a
JB		 3014 /* Note that the value returned is meaningful only for opcodes with (memory)
3015 operands, hence the code here is free to improperly handle opcodes that
3016 have no operands (for better performance and smaller code). */
3017
3018 if (mnemonic[0] != 'f')
3019 return 0; /* non-math */
3020
3021 switch (mnemonic[1])
3022 {
3023 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3024 the fs segment override prefix not currently handled because no
3025 call path can make opcodes without operands get here */
3026 case 'i':
3027 return 2 /* integer op */;
3028 case 'l':
3029 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3030 return 3; /* fldcw/fldenv */
3031 break;
3032 case 'n':
3033 if (mnemonic[2] != 'o' /* fnop */)
3034 return 3; /* non-waiting control op */
3035 break;
3036 case 'r':
3037 if (mnemonic[2] == 's')
3038 return 3; /* frstor/frstpm */
3039 break;
3040 case 's':
3041 if (mnemonic[2] == 'a')
3042 return 3; /* fsave */
3043 if (mnemonic[2] == 't')
3044 {
3045 switch (mnemonic[3])
3046 {
3047 case 'c': /* fstcw */
3048 case 'd': /* fstdw */
3049 case 'e': /* fstenv */
3050 case 's': /* fsts[gw] */
3051 return 3;
3052 }
3053 }
3054 break;
3055 case 'x':
3056 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3057 return 0; /* fxsave/fxrstor are not really math ops */
3058 break;
3059 }
252b5132 3060
9306ca4a 3061 return 1;
252b5132
RH		 3062}
3063
c0f3af97
L		 3064/* Build the VEX prefix. */
3065
3066static void
d3ce72d0 3067build_vex_prefix (const insn_template *t)
c0f3af97
L		 3068{
3069 unsigned int register_specifier;
3070 unsigned int implied_prefix;
3071 unsigned int vector_length;
3072
3073 /* Check register specifier. */
3074 if (i.vex.register_specifier)
43234a1e
L		 3075 {
3076 register_specifier =
3077 ~register_number (i.vex.register_specifier) & 0xf;
3078 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3079 }
c0f3af97
L		 3080 else
3081 register_specifier = 0xf;
3082
fa99fab2
L		 3083 /* Use 2-byte VEX prefix by swappping destination and source
3084 operand. */
3085 if (!i.swap_operand
3086 && i.operands == i.reg_operands
7f399153 3087 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3088 && i.tm.opcode_modifier.s
3089 && i.rex == REX_B)
3090 {
3091 unsigned int xchg = i.operands - 1;
3092 union i386_op temp_op;
3093 i386_operand_type temp_type;
3094
3095 temp_type = i.types[xchg];
3096 i.types[xchg] = i.types[0];
3097 i.types[0] = temp_type;
3098 temp_op = i.op[xchg];
3099 i.op[xchg] = i.op[0];
3100 i.op[0] = temp_op;
3101
9c2799c2 3102 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3103
3104 i.rex = REX_R;
3105 xchg = i.rm.regmem;
3106 i.rm.regmem = i.rm.reg;
3107 i.rm.reg = xchg;
3108
3109 /* Use the next insn. */
3110 i.tm = t[1];
3111 }
3112
539f890d
L		 3113 if (i.tm.opcode_modifier.vex == VEXScalar)
3114 vector_length = avxscalar;
3115 else
3116 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3117
3118 switch ((i.tm.base_opcode >> 8) & 0xff)
3119 {
3120 case 0:
3121 implied_prefix = 0;
3122 break;
3123 case DATA_PREFIX_OPCODE:
3124 implied_prefix = 1;
3125 break;
3126 case REPE_PREFIX_OPCODE:
3127 implied_prefix = 2;
3128 break;
3129 case REPNE_PREFIX_OPCODE:
3130 implied_prefix = 3;
3131 break;
3132 default:
3133 abort ();
3134 }
3135
3136 /* Use 2-byte VEX prefix if possible. */
7f399153 3137 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3138 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3139 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3140 {
3141 /* 2-byte VEX prefix. */
3142 unsigned int r;
3143
3144 i.vex.length = 2;
3145 i.vex.bytes[0] = 0xc5;
3146
3147 /* Check the REX.R bit. */
3148 r = (i.rex & REX_R) ? 0 : 1;
3149 i.vex.bytes[1] = (r << 7
3150 | register_specifier << 3
3151 | vector_length << 2
3152 | implied_prefix);
3153 }
3154 else
3155 {
3156 /* 3-byte VEX prefix. */
3157 unsigned int m, w;
3158
f88c9eb0 3159 i.vex.length = 3;
f88c9eb0 3160
7f399153 3161 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3162 {
7f399153
L		 3163 case VEX0F:
3164 m = 0x1;
80de6e00 3165 i.vex.bytes[0] = 0xc4;
7f399153
L		 3166 break;
3167 case VEX0F38:
3168 m = 0x2;
80de6e00 3169 i.vex.bytes[0] = 0xc4;
7f399153
L		 3170 break;
3171 case VEX0F3A:
3172 m = 0x3;
80de6e00 3173 i.vex.bytes[0] = 0xc4;
7f399153
L		 3174 break;
3175 case XOP08:
5dd85c99
SP		 3176 m = 0x8;
3177 i.vex.bytes[0] = 0x8f;
7f399153
L		 3178 break;
3179 case XOP09:
f88c9eb0
SP		 3180 m = 0x9;
3181 i.vex.bytes[0] = 0x8f;
7f399153
L		 3182 break;
3183 case XOP0A:
f88c9eb0
SP		 3184 m = 0xa;
3185 i.vex.bytes[0] = 0x8f;
7f399153
L		 3186 break;
3187 default:
3188 abort ();
f88c9eb0 3189 }
c0f3af97 3190
c0f3af97
L		 3191 /* The high 3 bits of the second VEX byte are 1's compliment
3192 of RXB bits from REX. */
3193 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3194
3195 /* Check the REX.W bit. */
3196 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3197 if (i.tm.opcode_modifier.vexw == VEXW1)
3198 w = 1;
c0f3af97
L		 3199
3200 i.vex.bytes[2] = (w << 7
3201 | register_specifier << 3
3202 | vector_length << 2
3203 | implied_prefix);
3204 }
3205}
3206
43234a1e
L		 3207/* Build the EVEX prefix. */
3208
3209static void
3210build_evex_prefix (void)
3211{
3212 unsigned int register_specifier;
3213 unsigned int implied_prefix;
3214 unsigned int m, w;
3215 rex_byte vrex_used = 0;
3216
3217 /* Check register specifier. */
3218 if (i.vex.register_specifier)
3219 {
3220 gas_assert ((i.vrex & REX_X) == 0);
3221
3222 register_specifier = i.vex.register_specifier->reg_num;
3223 if ((i.vex.register_specifier->reg_flags & RegRex))
3224 register_specifier += 8;
3225 /* The upper 16 registers are encoded in the fourth byte of the
3226 EVEX prefix. */
3227 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3228 i.vex.bytes[3] = 0x8;
3229 register_specifier = ~register_specifier & 0xf;
3230 }
3231 else
3232 {
3233 register_specifier = 0xf;
3234
3235 /* Encode upper 16 vector index register in the fourth byte of
3236 the EVEX prefix. */
3237 if (!(i.vrex & REX_X))
3238 i.vex.bytes[3] = 0x8;
3239 else
3240 vrex_used |= REX_X;
3241 }
3242
3243 switch ((i.tm.base_opcode >> 8) & 0xff)
3244 {
3245 case 0:
3246 implied_prefix = 0;
3247 break;
3248 case DATA_PREFIX_OPCODE:
3249 implied_prefix = 1;
3250 break;
3251 case REPE_PREFIX_OPCODE:
3252 implied_prefix = 2;
3253 break;
3254 case REPNE_PREFIX_OPCODE:
3255 implied_prefix = 3;
3256 break;
3257 default:
3258 abort ();
3259 }
3260
3261 /* 4 byte EVEX prefix. */
3262 i.vex.length = 4;
3263 i.vex.bytes[0] = 0x62;
3264
3265 /* mmmm bits. */
3266 switch (i.tm.opcode_modifier.vexopcode)
3267 {
3268 case VEX0F:
3269 m = 1;
3270 break;
3271 case VEX0F38:
3272 m = 2;
3273 break;
3274 case VEX0F3A:
3275 m = 3;
3276 break;
3277 default:
3278 abort ();
3279 break;
3280 }
3281
3282 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3283 bits from REX. */
3284 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3285
3286 /* The fifth bit of the second EVEX byte is 1's compliment of the
3287 REX_R bit in VREX. */
3288 if (!(i.vrex & REX_R))
3289 i.vex.bytes[1] |= 0x10;
3290 else
3291 vrex_used |= REX_R;
3292
3293 if ((i.reg_operands + i.imm_operands) == i.operands)
3294 {
3295 /* When all operands are registers, the REX_X bit in REX is not
3296 used. We reuse it to encode the upper 16 registers, which is
3297 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3298 as 1's compliment. */
3299 if ((i.vrex & REX_B))
3300 {
3301 vrex_used |= REX_B;
3302 i.vex.bytes[1] &= ~0x40;
3303 }
3304 }
3305
3306 /* EVEX instructions shouldn't need the REX prefix. */
3307 i.vrex &= ~vrex_used;
3308 gas_assert (i.vrex == 0);
3309
3310 /* Check the REX.W bit. */
3311 w = (i.rex & REX_W) ? 1 : 0;
3312 if (i.tm.opcode_modifier.vexw)
3313 {
3314 if (i.tm.opcode_modifier.vexw == VEXW1)
3315 w = 1;
3316 }
3317 /* If w is not set it means we are dealing with WIG instruction. */
3318 else if (!w)
3319 {
3320 if (evexwig == evexw1)
3321 w = 1;
3322 }
3323
3324 /* Encode the U bit. */
3325 implied_prefix |= 0x4;
3326
3327 /* The third byte of the EVEX prefix. */
3328 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3329
3330 /* The fourth byte of the EVEX prefix. */
3331 /* The zeroing-masking bit. */
3332 if (i.mask && i.mask->zeroing)
3333 i.vex.bytes[3] |= 0x80;
3334
3335 /* Don't always set the broadcast bit if there is no RC. */
3336 if (!i.rounding)
3337 {
3338 /* Encode the vector length. */
3339 unsigned int vec_length;
3340
3341 switch (i.tm.opcode_modifier.evex)
3342 {
3343 case EVEXLIG: /* LL' is ignored */
3344 vec_length = evexlig << 5;
3345 break;
3346 case EVEX128:
3347 vec_length = 0 << 5;
3348 break;
3349 case EVEX256:
3350 vec_length = 1 << 5;
3351 break;
3352 case EVEX512:
3353 vec_length = 2 << 5;
3354 break;
3355 default:
3356 abort ();
3357 break;
3358 }
3359 i.vex.bytes[3] |= vec_length;
3360 /* Encode the broadcast bit. */
3361 if (i.broadcast)
3362 i.vex.bytes[3] |= 0x10;
3363 }
3364 else
3365 {
3366 if (i.rounding->type != saeonly)
3367 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3368 else
d3d3c6db 3369 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3370 }
3371
3372 if (i.mask && i.mask->mask)
3373 i.vex.bytes[3] |= i.mask->mask->reg_num;
3374}
3375
65da13b5
L		 3376static void
3377process_immext (void)
3378{
3379 expressionS *exp;
3380
4c692bc7
JB		 3381 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3382 && i.operands > 0)
65da13b5 3383 {
4c692bc7
JB		 3384 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3385 with an opcode suffix which is coded in the same place as an
3386 8-bit immediate field would be.
3387 Here we check those operands and remove them afterwards. */
65da13b5
L		 3388 unsigned int x;
3389
3390 for (x = 0; x < i.operands; x++)
4c692bc7 3391 if (register_number (i.op[x].regs) != x)
65da13b5 3392 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3393 register_prefix, i.op[x].regs->reg_name, x + 1,
3394 i.tm.name);
3395
3396 i.operands = 0;
65da13b5
L		 3397 }
3398
c0f3af97 3399 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3400 which is coded in the same place as an 8-bit immediate field
3401 would be. Here we fake an 8-bit immediate operand from the
3402 opcode suffix stored in tm.extension_opcode.
3403
c1e679ec 3404 AVX instructions also use this encoding, for some of
c0f3af97 3405 3 argument instructions. */
65da13b5 3406
43234a1e 3407 gas_assert (i.imm_operands <= 1
7ab9ffdd 3408 && (i.operands <= 2
43234a1e
L		 3409 || ((i.tm.opcode_modifier.vex
3410 || i.tm.opcode_modifier.evex)
7ab9ffdd 3411 && i.operands <= 4)));
65da13b5
L		 3412
3413 exp = &im_expressions[i.imm_operands++];
3414 i.op[i.operands].imms = exp;
3415 i.types[i.operands] = imm8;
3416 i.operands++;
3417 exp->X_op = O_constant;
3418 exp->X_add_number = i.tm.extension_opcode;
3419 i.tm.extension_opcode = None;
3420}
3421
42164a71
L		 3422
3423static int
3424check_hle (void)
3425{
3426 switch (i.tm.opcode_modifier.hleprefixok)
3427 {
3428 default:
3429 abort ();
82c2def5 3430 case HLEPrefixNone:
165de32a
L		 3431 as_bad (_("invalid instruction `%s' after `%s'"),
3432 i.tm.name, i.hle_prefix);
42164a71 3433 return 0;
82c2def5 3434 case HLEPrefixLock:
42164a71
L		 3435 if (i.prefix[LOCK_PREFIX])
3436 return 1;
165de32a 3437 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3438 return 0;
82c2def5 3439 case HLEPrefixAny:
42164a71 3440 return 1;
82c2def5 3441 case HLEPrefixRelease:
42164a71
L		 3442 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3443 {
3444 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3445 i.tm.name);
3446 return 0;
3447 }
3448 if (i.mem_operands == 0
3449 || !operand_type_check (i.types[i.operands - 1], anymem))
3450 {
3451 as_bad (_("memory destination needed for instruction `%s'"
3452 " after `xrelease'"), i.tm.name);
3453 return 0;
3454 }
3455 return 1;
3456 }
3457}
3458
252b5132
RH		 3459/* This is the guts of the machine-dependent assembler. LINE points to a
3460 machine dependent instruction. This function is supposed to emit
3461 the frags/bytes it assembles to. */
3462
3463void
65da13b5 3464md_assemble (char *line)
252b5132 3465{
40fb9820 3466 unsigned int j;
252b5132 3467 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3468 const insn_template *t;
252b5132 3469
47926f60 3470 /* Initialize globals. */
252b5132
RH		 3471 memset (&i, '\0', sizeof (i));
3472 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3473 i.reloc[j] = NO_RELOC;
252b5132
RH		 3474 memset (disp_expressions, '\0', sizeof (disp_expressions));
3475 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3476 save_stack_p = save_stack;
252b5132
RH		 3477
3478 /* First parse an instruction mnemonic & call i386_operand for the operands.
3479 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3480 start of a (possibly prefixed) mnemonic. */
252b5132 3481
29b0f896
AM		 3482 line = parse_insn (line, mnemonic);
3483 if (line == NULL)
3484 return;
252b5132 3485
29b0f896 3486 line = parse_operands (line, mnemonic);
ee86248c 3487 this_operand = -1;
29b0f896
AM		 3488 if (line == NULL)
3489 return;
252b5132 3490
29b0f896
AM		 3491 /* Now we've parsed the mnemonic into a set of templates, and have the
3492 operands at hand. */
3493
3494 /* All intel opcodes have reversed operands except for "bound" and
3495 "enter". We also don't reverse intersegment "jmp" and "call"
3496 instructions with 2 immediate operands so that the immediate segment
050dfa73 3497 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3498 if (intel_syntax
3499 && i.operands > 1
29b0f896 3500 && (strcmp (mnemonic, "bound") != 0)
30123838 3501 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3502 && !(operand_type_check (i.types[0], imm)
3503 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3504 swap_operands ();
3505
ec56d5c0
JB		 3506 /* The order of the immediates should be reversed
3507 for 2 immediates extrq and insertq instructions */
3508 if (i.imm_operands == 2
3509 && (strcmp (mnemonic, "extrq") == 0
3510 || strcmp (mnemonic, "insertq") == 0))
3511 swap_2_operands (0, 1);
3512
29b0f896
AM		 3513 if (i.imm_operands)
3514 optimize_imm ();
3515
b300c311
L		 3516 /* Don't optimize displacement for movabs since it only takes 64bit
3517 displacement. */
3518 if (i.disp_operands
a501d77e 3519 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3520 && (flag_code != CODE_64BIT
3521 || strcmp (mnemonic, "movabs") != 0))
3522 optimize_disp ();
29b0f896
AM		 3523
3524 /* Next, we find a template that matches the given insn,
3525 making sure the overlap of the given operands types is consistent
3526 with the template operand types. */
252b5132 3527
fa99fab2 3528 if (!(t = match_template ()))
29b0f896 3529 return;
252b5132 3530
7bab8ab5 3531 if (sse_check != check_none
81f8a913 3532 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3533 && (i.tm.cpu_flags.bitfield.cpusse
3534 || i.tm.cpu_flags.bitfield.cpusse2
3535 || i.tm.cpu_flags.bitfield.cpusse3
3536 || i.tm.cpu_flags.bitfield.cpussse3
3537 || i.tm.cpu_flags.bitfield.cpusse4_1
3538 || i.tm.cpu_flags.bitfield.cpusse4_2))
3539 {
7bab8ab5 3540 (sse_check == check_warning
daf50ae7
L		 3541 ? as_warn
3542 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3543 }
3544
321fd21e
L		 3545 /* Zap movzx and movsx suffix. The suffix has been set from
3546 "word ptr" or "byte ptr" on the source operand in Intel syntax
3547 or extracted from mnemonic in AT&T syntax. But we'll use
3548 the destination register to choose the suffix for encoding. */
3549 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3550 {
321fd21e
L		 3551 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3552 there is no suffix, the default will be byte extension. */
3553 if (i.reg_operands != 2
3554 && !i.suffix
7ab9ffdd 3555 && intel_syntax)
321fd21e
L		 3556 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3557
3558 i.suffix = 0;
cd61ebfe 3559 }
24eab124 3560
40fb9820 3561 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3562 if (!add_prefix (FWAIT_OPCODE))
3563 return;
252b5132 3564
d5de92cf
L		 3565 /* Check if REP prefix is OK. */
3566 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3567 {
3568 as_bad (_("invalid instruction `%s' after `%s'"),
3569 i.tm.name, i.rep_prefix);
3570 return;
3571 }
3572
c1ba0266
L		 3573 /* Check for lock without a lockable instruction. Destination operand
3574 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3575 if (i.prefix[LOCK_PREFIX]
3576 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3577 || i.mem_operands == 0
3578 || (i.tm.base_opcode != 0x86
3579 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3580 {
3581 as_bad (_("expecting lockable instruction after `lock'"));
3582 return;
3583 }
3584
42164a71 3585 /* Check if HLE prefix is OK. */
165de32a 3586 if (i.hle_prefix && !check_hle ())
42164a71
L		 3587 return;
3588
7e8b059b
L		 3589 /* Check BND prefix. */
3590 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3591 as_bad (_("expecting valid branch instruction after `bnd'"));
3592
3593 if (i.tm.cpu_flags.bitfield.cpumpx
3594 && flag_code == CODE_64BIT
3595 && i.prefix[ADDR_PREFIX])
3596 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3597
3598 /* Insert BND prefix. */
3599 if (add_bnd_prefix
3600 && i.tm.opcode_modifier.bndprefixok
3601 && !i.prefix[BND_PREFIX])
3602 add_prefix (BND_PREFIX_OPCODE);
3603
29b0f896 3604 /* Check string instruction segment overrides. */
40fb9820 3605 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3606 {
3607 if (!check_string ())
5dd0794d 3608 return;
fc0763e6 3609 i.disp_operands = 0;
29b0f896 3610 }
5dd0794d 3611
29b0f896
AM		 3612 if (!process_suffix ())
3613 return;
e413e4e9 3614
bc0844ae
L		 3615 /* Update operand types. */
3616 for (j = 0; j < i.operands; j++)
3617 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3618
29b0f896
AM		 3619 /* Make still unresolved immediate matches conform to size of immediate
3620 given in i.suffix. */
3621 if (!finalize_imm ())
3622 return;
252b5132 3623
40fb9820 3624 if (i.types[0].bitfield.imm1)
29b0f896 3625 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3626
9afe6eb8
L		 3627 /* We only need to check those implicit registers for instructions
3628 with 3 operands or less. */
3629 if (i.operands <= 3)
3630 for (j = 0; j < i.operands; j++)
3631 if (i.types[j].bitfield.inoutportreg
3632 || i.types[j].bitfield.shiftcount
3633 || i.types[j].bitfield.acc
3634 || i.types[j].bitfield.floatacc)
3635 i.reg_operands--;
40fb9820 3636
c0f3af97
L		 3637 /* ImmExt should be processed after SSE2AVX. */
3638 if (!i.tm.opcode_modifier.sse2avx
3639 && i.tm.opcode_modifier.immext)
65da13b5 3640 process_immext ();
252b5132 3641
29b0f896
AM		 3642 /* For insns with operands there are more diddles to do to the opcode. */
3643 if (i.operands)
3644 {
3645 if (!process_operands ())
3646 return;
3647 }
40fb9820 3648 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3649 {
3650 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3651 as_warn (_("translating to `%sp'"), i.tm.name);
3652 }
252b5132 3653
9e5e5283
L		 3654 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3655 {
3656 if (flag_code == CODE_16BIT)
3657 {
3658 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3659 i.tm.name);
3660 return;
3661 }
c0f3af97 3662
9e5e5283
L		 3663 if (i.tm.opcode_modifier.vex)
3664 build_vex_prefix (t);
3665 else
3666 build_evex_prefix ();
3667 }
43234a1e 3668
5dd85c99
SP		 3669 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3670 instructions may define INT_OPCODE as well, so avoid this corner
3671 case for those instructions that use MODRM. */
3672 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3673 && !i.tm.opcode_modifier.modrm
3674 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3675 {
3676 i.tm.base_opcode = INT3_OPCODE;
3677 i.imm_operands = 0;
3678 }
252b5132 3679
40fb9820
L		 3680 if ((i.tm.opcode_modifier.jump
3681 || i.tm.opcode_modifier.jumpbyte
3682 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3683 && i.op[0].disps->X_op == O_constant)
3684 {
3685 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3686 the absolute address given by the constant. Since ix86 jumps and
3687 calls are pc relative, we need to generate a reloc. */
3688 i.op[0].disps->X_add_symbol = &abs_symbol;
3689 i.op[0].disps->X_op = O_symbol;
3690 }
252b5132 3691
40fb9820 3692 if (i.tm.opcode_modifier.rex64)
161a04f6 3693 i.rex |= REX_W;
252b5132 3694
29b0f896
AM		 3695 /* For 8 bit registers we need an empty rex prefix. Also if the
3696 instruction already has a prefix, we need to convert old
3697 registers to new ones. */
773f551c 3698
40fb9820 3699 if ((i.types[0].bitfield.reg8
29b0f896 3700 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3701 || (i.types[1].bitfield.reg8
29b0f896 3702 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3703 || ((i.types[0].bitfield.reg8
3704 || i.types[1].bitfield.reg8)
29b0f896
AM		 3705 && i.rex != 0))
3706 {
3707 int x;
726c5dcd 3708
29b0f896
AM		 3709 i.rex |= REX_OPCODE;
3710 for (x = 0; x < 2; x++)
3711 {
3712 /* Look for 8 bit operand that uses old registers. */
40fb9820 3713 if (i.types[x].bitfield.reg8
29b0f896 3714 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3715 {
29b0f896
AM		 3716 /* In case it is "hi" register, give up. */
3717 if (i.op[x].regs->reg_num > 3)
a540244d 3718 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3719 "instruction requiring REX prefix."),
a540244d 3720 register_prefix, i.op[x].regs->reg_name);
773f551c 3721
29b0f896
AM		 3722 /* Otherwise it is equivalent to the extended register.
3723 Since the encoding doesn't change this is merely
3724 cosmetic cleanup for debug output. */
3725
3726 i.op[x].regs = i.op[x].regs + 8;
773f551c 3727 }
29b0f896
AM		 3728 }
3729 }
773f551c 3730
7ab9ffdd 3731 if (i.rex != 0)
29b0f896
AM		 3732 add_prefix (REX_OPCODE | i.rex);
3733
3734 /* We are ready to output the insn. */
3735 output_insn ();
3736}
3737
3738static char *
e3bb37b5 3739parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3740{
3741 char *l = line;
3742 char *token_start = l;
3743 char *mnem_p;
5c6af06e 3744 int supported;
d3ce72d0 3745 const insn_template *t;
b6169b20 3746 char *dot_p = NULL;
29b0f896 3747
29b0f896
AM		 3748 while (1)
3749 {
3750 mnem_p = mnemonic;
3751 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3752 {
b6169b20
L		 3753 if (*mnem_p == '.')
3754 dot_p = mnem_p;
29b0f896
AM		 3755 mnem_p++;
3756 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3757 {
29b0f896
AM		 3758 as_bad (_("no such instruction: `%s'"), token_start);
3759 return NULL;
3760 }
3761 l++;
3762 }
3763 if (!is_space_char (*l)
3764 && *l != END_OF_INSN
e44823cf
JB		 3765 && (intel_syntax
3766 || (*l != PREFIX_SEPARATOR
3767 && *l != ',')))
29b0f896
AM		 3768 {
3769 as_bad (_("invalid character %s in mnemonic"),
3770 output_invalid (*l));
3771 return NULL;
3772 }
3773 if (token_start == l)
3774 {
e44823cf 3775 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3776 as_bad (_("expecting prefix; got nothing"));
3777 else
3778 as_bad (_("expecting mnemonic; got nothing"));
3779 return NULL;
3780 }
45288df1 3781
29b0f896 3782 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3783 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3784
29b0f896
AM		 3785 if (*l != END_OF_INSN
3786 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3787 && current_templates
40fb9820 3788 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3789 {
c6fb90c8 3790 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3791 {
3792 as_bad ((flag_code != CODE_64BIT
3793 ? _("`%s' is only supported in 64-bit mode")
3794 : _("`%s' is not supported in 64-bit mode")),
3795 current_templates->start->name);
3796 return NULL;
3797 }
29b0f896
AM		 3798 /* If we are in 16-bit mode, do not allow addr16 or data16.
3799 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3800 if ((current_templates->start->opcode_modifier.size16
3801 || current_templates->start->opcode_modifier.size32)
29b0f896 3802 && flag_code != CODE_64BIT
40fb9820 3803 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3804 ^ (flag_code == CODE_16BIT)))
3805 {
3806 as_bad (_("redundant %s prefix"),
3807 current_templates->start->name);
3808 return NULL;
45288df1 3809 }
29b0f896
AM		 3810 /* Add prefix, checking for repeated prefixes. */
3811 switch (add_prefix (current_templates->start->base_opcode))
3812 {
c32fa91d 3813 case PREFIX_EXIST:
29b0f896 3814 return NULL;
c32fa91d 3815 case PREFIX_REP:
42164a71 3816 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3817 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3818 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3819 i.bnd_prefix = current_templates->start->name;
42164a71 3820 else
d5de92cf 3821 i.rep_prefix = current_templates->start->name;
29b0f896 3822 break;
c32fa91d
L		 3823 default:
3824 break;
29b0f896
AM		 3825 }
3826 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3827 token_start = ++l;
3828 }
3829 else
3830 break;
3831 }
45288df1 3832
30a55f88 3833 if (!current_templates)
b6169b20 3834 {
f8a5c266
L		 3835 /* Check if we should swap operand or force 32bit displacement in
3836 encoding. */
30a55f88
L		 3837 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3838 i.swap_operand = 1;
8d63c93e 3839 else if (mnem_p - 3 == dot_p
a501d77e
L		 3840 && dot_p[1] == 'd'
3841 && dot_p[2] == '8')
3842 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3843 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3844 && dot_p[1] == 'd'
3845 && dot_p[2] == '3'
3846 && dot_p[3] == '2')
a501d77e 3847 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3848 else
3849 goto check_suffix;
3850 mnem_p = dot_p;
3851 *dot_p = '\0';
d3ce72d0 3852 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3853 }
3854
29b0f896
AM		 3855 if (!current_templates)
3856 {
b6169b20 3857check_suffix:
29b0f896
AM		 3858 /* See if we can get a match by trimming off a suffix. */
3859 switch (mnem_p[-1])
3860 {
3861 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3862 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3863 i.suffix = SHORT_MNEM_SUFFIX;
3864 else
29b0f896
AM		 3865 case BYTE_MNEM_SUFFIX:
3866 case QWORD_MNEM_SUFFIX:
3867 i.suffix = mnem_p[-1];
3868 mnem_p[-1] = '\0';
d3ce72d0
NC		 3869 current_templates = (const templates *) hash_find (op_hash,
3870 mnemonic);
29b0f896
AM		 3871 break;
3872 case SHORT_MNEM_SUFFIX:
3873 case LONG_MNEM_SUFFIX:
3874 if (!intel_syntax)
3875 {
3876 i.suffix = mnem_p[-1];
3877 mnem_p[-1] = '\0';
d3ce72d0
NC		 3878 current_templates = (const templates *) hash_find (op_hash,
3879 mnemonic);
29b0f896
AM		 3880 }
3881 break;
252b5132 3882
29b0f896
AM		 3883 /* Intel Syntax. */
3884 case 'd':
3885 if (intel_syntax)
3886 {
9306ca4a 3887 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3888 i.suffix = SHORT_MNEM_SUFFIX;
3889 else
3890 i.suffix = LONG_MNEM_SUFFIX;
3891 mnem_p[-1] = '\0';
d3ce72d0
NC		 3892 current_templates = (const templates *) hash_find (op_hash,
3893 mnemonic);
29b0f896
AM		 3894 }
3895 break;
3896 }
3897 if (!current_templates)
3898 {
3899 as_bad (_("no such instruction: `%s'"), token_start);
3900 return NULL;
3901 }
3902 }
252b5132 3903
40fb9820
L		 3904 if (current_templates->start->opcode_modifier.jump
3905 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3906 {
3907 /* Check for a branch hint. We allow ",pt" and ",pn" for
3908 predict taken and predict not taken respectively.
3909 I'm not sure that branch hints actually do anything on loop
3910 and jcxz insns (JumpByte) for current Pentium4 chips. They
3911 may work in the future and it doesn't hurt to accept them
3912 now. */
3913 if (l[0] == ',' && l[1] == 'p')
3914 {
3915 if (l[2] == 't')
3916 {
3917 if (!add_prefix (DS_PREFIX_OPCODE))
3918 return NULL;
3919 l += 3;
3920 }
3921 else if (l[2] == 'n')
3922 {
3923 if (!add_prefix (CS_PREFIX_OPCODE))
3924 return NULL;
3925 l += 3;
3926 }
3927 }
3928 }
3929 /* Any other comma loses. */
3930 if (*l == ',')
3931 {
3932 as_bad (_("invalid character %s in mnemonic"),
3933 output_invalid (*l));
3934 return NULL;
3935 }
252b5132 3936
29b0f896 3937 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3938 supported = 0;
3939 for (t = current_templates->start; t < current_templates->end; ++t)
3940 {
c0f3af97
L		 3941 supported |= cpu_flags_match (t);
3942 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3943 goto skip;
5c6af06e 3944 }
3629bb00 3945
c0f3af97 3946 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3947 {
3948 as_bad (flag_code == CODE_64BIT
3949 ? _("`%s' is not supported in 64-bit mode")
3950 : _("`%s' is only supported in 64-bit mode"),
3951 current_templates->start->name);
3952 return NULL;
3953 }
c0f3af97 3954 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3955 {
3629bb00 3956 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3957 current_templates->start->name,
41aacd83 3958 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3959 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3960 return NULL;
29b0f896 3961 }
3629bb00
L		 3962
3963skip:
3964 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3965 && (flag_code != CODE_16BIT))
29b0f896
AM		 3966 {
3967 as_warn (_("use .code16 to ensure correct addressing mode"));
3968 }
252b5132 3969
29b0f896
AM		 3970 return l;
3971}
252b5132 3972
29b0f896 3973static char *
e3bb37b5 3974parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3975{
3976 char *token_start;
3138f287 3977
29b0f896
AM		 3978 /* 1 if operand is pending after ','. */
3979 unsigned int expecting_operand = 0;
252b5132 3980
29b0f896
AM		 3981 /* Non-zero if operand parens not balanced. */
3982 unsigned int paren_not_balanced;
3983
3984 while (*l != END_OF_INSN)
3985 {
3986 /* Skip optional white space before operand. */
3987 if (is_space_char (*l))
3988 ++l;
3989 if (!is_operand_char (*l) && *l != END_OF_INSN)
3990 {
3991 as_bad (_("invalid character %s before operand %d"),
3992 output_invalid (*l),
3993 i.operands + 1);
3994 return NULL;
3995 }
3996 token_start = l; /* after white space */
3997 paren_not_balanced = 0;
3998 while (paren_not_balanced || *l != ',')
3999 {
4000 if (*l == END_OF_INSN)
4001 {
4002 if (paren_not_balanced)
4003 {
4004 if (!intel_syntax)
4005 as_bad (_("unbalanced parenthesis in operand %d."),
4006 i.operands + 1);
4007 else
4008 as_bad (_("unbalanced brackets in operand %d."),
4009 i.operands + 1);
4010 return NULL;
4011 }
4012 else
4013 break; /* we are done */
4014 }
4015 else if (!is_operand_char (*l) && !is_space_char (*l))
4016 {
4017 as_bad (_("invalid character %s in operand %d"),
4018 output_invalid (*l),
4019 i.operands + 1);
4020 return NULL;
4021 }
4022 if (!intel_syntax)
4023 {
4024 if (*l == '(')
4025 ++paren_not_balanced;
4026 if (*l == ')')
4027 --paren_not_balanced;
4028 }
4029 else
4030 {
4031 if (*l == '[')
4032 ++paren_not_balanced;
4033 if (*l == ']')
4034 --paren_not_balanced;
4035 }
4036 l++;
4037 }
4038 if (l != token_start)
4039 { /* Yes, we've read in another operand. */
4040 unsigned int operand_ok;
4041 this_operand = i.operands++;
7d5e4556 4042 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4043 if (i.operands > MAX_OPERANDS)
4044 {
4045 as_bad (_("spurious operands; (%d operands/instruction max)"),
4046 MAX_OPERANDS);
4047 return NULL;
4048 }
4049 /* Now parse operand adding info to 'i' as we go along. */
4050 END_STRING_AND_SAVE (l);
4051
4052 if (intel_syntax)
4053 operand_ok =
4054 i386_intel_operand (token_start,
4055 intel_float_operand (mnemonic));
4056 else
a7619375 4057 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4058
4059 RESTORE_END_STRING (l);
4060 if (!operand_ok)
4061 return NULL;
4062 }
4063 else
4064 {
4065 if (expecting_operand)
4066 {
4067 expecting_operand_after_comma:
4068 as_bad (_("expecting operand after ','; got nothing"));
4069 return NULL;
4070 }
4071 if (*l == ',')
4072 {
4073 as_bad (_("expecting operand before ','; got nothing"));
4074 return NULL;
4075 }
4076 }
7f3f1ea2 4077
29b0f896
AM		 4078 /* Now *l must be either ',' or END_OF_INSN. */
4079 if (*l == ',')
4080 {
4081 if (*++l == END_OF_INSN)
4082 {
4083 /* Just skip it, if it's \n complain. */
4084 goto expecting_operand_after_comma;
4085 }
4086 expecting_operand = 1;
4087 }
4088 }
4089 return l;
4090}
7f3f1ea2 4091
050dfa73 4092static void
4d456e3d 4093swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4094{
4095 union i386_op temp_op;
40fb9820 4096 i386_operand_type temp_type;
050dfa73 4097 enum bfd_reloc_code_real temp_reloc;
4eed87de 4098
050dfa73
MM		 4099 temp_type = i.types[xchg2];
4100 i.types[xchg2] = i.types[xchg1];
4101 i.types[xchg1] = temp_type;
4102 temp_op = i.op[xchg2];
4103 i.op[xchg2] = i.op[xchg1];
4104 i.op[xchg1] = temp_op;
4105 temp_reloc = i.reloc[xchg2];
4106 i.reloc[xchg2] = i.reloc[xchg1];
4107 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4108
4109 if (i.mask)
4110 {
4111 if (i.mask->operand == xchg1)
4112 i.mask->operand = xchg2;
4113 else if (i.mask->operand == xchg2)
4114 i.mask->operand = xchg1;
4115 }
4116 if (i.broadcast)
4117 {
4118 if (i.broadcast->operand == xchg1)
4119 i.broadcast->operand = xchg2;
4120 else if (i.broadcast->operand == xchg2)
4121 i.broadcast->operand = xchg1;
4122 }
4123 if (i.rounding)
4124 {
4125 if (i.rounding->operand == xchg1)
4126 i.rounding->operand = xchg2;
4127 else if (i.rounding->operand == xchg2)
4128 i.rounding->operand = xchg1;
4129 }
050dfa73
MM		 4130}
4131
29b0f896 4132static void
e3bb37b5 4133swap_operands (void)
29b0f896 4134{
b7c61d9a 4135 switch (i.operands)
050dfa73 4136 {
c0f3af97 4137 case 5:
b7c61d9a 4138 case 4:
4d456e3d 4139 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4140 case 3:
4141 case 2:
4d456e3d 4142 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4143 break;
4144 default:
4145 abort ();
29b0f896 4146 }
29b0f896
AM		 4147
4148 if (i.mem_operands == 2)
4149 {
4150 const seg_entry *temp_seg;
4151 temp_seg = i.seg[0];
4152 i.seg[0] = i.seg[1];
4153 i.seg[1] = temp_seg;
4154 }
4155}
252b5132 4156
29b0f896
AM		 4157/* Try to ensure constant immediates are represented in the smallest
4158 opcode possible. */
4159static void
e3bb37b5 4160optimize_imm (void)
29b0f896
AM		 4161{
4162 char guess_suffix = 0;
4163 int op;
252b5132 4164
29b0f896
AM		 4165 if (i.suffix)
4166 guess_suffix = i.suffix;
4167 else if (i.reg_operands)
4168 {
4169 /* Figure out a suffix from the last register operand specified.
4170 We can't do this properly yet, ie. excluding InOutPortReg,
4171 but the following works for instructions with immediates.
4172 In any case, we can't set i.suffix yet. */
4173 for (op = i.operands; --op >= 0;)
40fb9820 4174 if (i.types[op].bitfield.reg8)
7ab9ffdd 4175 {
40fb9820
L		 4176 guess_suffix = BYTE_MNEM_SUFFIX;
4177 break;
4178 }
4179 else if (i.types[op].bitfield.reg16)
252b5132 4180 {
40fb9820
L		 4181 guess_suffix = WORD_MNEM_SUFFIX;
4182 break;
4183 }
4184 else if (i.types[op].bitfield.reg32)
4185 {
4186 guess_suffix = LONG_MNEM_SUFFIX;
4187 break;
4188 }
4189 else if (i.types[op].bitfield.reg64)
4190 {
4191 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4192 break;
252b5132 4193 }
29b0f896
AM		 4194 }
4195 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4196 guess_suffix = WORD_MNEM_SUFFIX;
4197
4198 for (op = i.operands; --op >= 0;)
40fb9820 4199 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4200 {
4201 switch (i.op[op].imms->X_op)
252b5132 4202 {
29b0f896
AM		 4203 case O_constant:
4204 /* If a suffix is given, this operand may be shortened. */
4205 switch (guess_suffix)
252b5132 4206 {
29b0f896 4207 case LONG_MNEM_SUFFIX:
40fb9820
L		 4208 i.types[op].bitfield.imm32 = 1;
4209 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4210 break;
4211 case WORD_MNEM_SUFFIX:
40fb9820
L		 4212 i.types[op].bitfield.imm16 = 1;
4213 i.types[op].bitfield.imm32 = 1;
4214 i.types[op].bitfield.imm32s = 1;
4215 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4216 break;
4217 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4218 i.types[op].bitfield.imm8 = 1;
4219 i.types[op].bitfield.imm8s = 1;
4220 i.types[op].bitfield.imm16 = 1;
4221 i.types[op].bitfield.imm32 = 1;
4222 i.types[op].bitfield.imm32s = 1;
4223 i.types[op].bitfield.imm64 = 1;
29b0f896 4224 break;
252b5132 4225 }
252b5132 4226
29b0f896
AM		 4227 /* If this operand is at most 16 bits, convert it
4228 to a signed 16 bit number before trying to see
4229 whether it will fit in an even smaller size.
4230 This allows a 16-bit operand such as $0xffe0 to
4231 be recognised as within Imm8S range. */
40fb9820 4232 if ((i.types[op].bitfield.imm16)
29b0f896 4233 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4234 {
29b0f896
AM		 4235 i.op[op].imms->X_add_number =
4236 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4237 }
40fb9820 4238 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4239 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4240 == 0))
4241 {
4242 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4243 ^ ((offsetT) 1 << 31))
4244 - ((offsetT) 1 << 31));
4245 }
40fb9820 4246 i.types[op]
c6fb90c8
L		 4247 = operand_type_or (i.types[op],
4248 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4249
29b0f896
AM		 4250 /* We must avoid matching of Imm32 templates when 64bit
4251 only immediate is available. */
4252 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4253 i.types[op].bitfield.imm32 = 0;
29b0f896 4254 break;
252b5132 4255
29b0f896
AM		 4256 case O_absent:
4257 case O_register:
4258 abort ();
4259
4260 /* Symbols and expressions. */
4261 default:
9cd96992
JB		 4262 /* Convert symbolic operand to proper sizes for matching, but don't
4263 prevent matching a set of insns that only supports sizes other
4264 than those matching the insn suffix. */
4265 {
40fb9820 4266 i386_operand_type mask, allowed;
d3ce72d0 4267 const insn_template *t;
9cd96992 4268
0dfbf9d7
L		 4269 operand_type_set (&mask, 0);
4270 operand_type_set (&allowed, 0);
40fb9820 4271
4eed87de
AM		 4272 for (t = current_templates->start;
4273 t < current_templates->end;
4274 ++t)
c6fb90c8
L		 4275 allowed = operand_type_or (allowed,
4276 t->operand_types[op]);
9cd96992
JB		 4277 switch (guess_suffix)
4278 {
4279 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4280 mask.bitfield.imm64 = 1;
4281 mask.bitfield.imm32s = 1;
9cd96992
JB		 4282 break;
4283 case LONG_MNEM_SUFFIX:
40fb9820 4284 mask.bitfield.imm32 = 1;
9cd96992
JB		 4285 break;
4286 case WORD_MNEM_SUFFIX:
40fb9820 4287 mask.bitfield.imm16 = 1;
9cd96992
JB		 4288 break;
4289 case BYTE_MNEM_SUFFIX:
40fb9820 4290 mask.bitfield.imm8 = 1;
9cd96992
JB		 4291 break;
4292 default:
9cd96992
JB		 4293 break;
4294 }
c6fb90c8 4295 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4296 if (!operand_type_all_zero (&allowed))
c6fb90c8 4297 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4298 }
29b0f896 4299 break;
252b5132 4300 }
29b0f896
AM		 4301 }
4302}
47926f60 4303
29b0f896
AM		 4304/* Try to use the smallest displacement type too. */
4305static void
e3bb37b5 4306optimize_disp (void)
29b0f896
AM		 4307{
4308 int op;
3e73aa7c 4309
29b0f896 4310 for (op = i.operands; --op >= 0;)
40fb9820 4311 if (operand_type_check (i.types[op], disp))
252b5132 4312 {
b300c311 4313 if (i.op[op].disps->X_op == O_constant)
252b5132 4314 {
91d6fa6a 4315 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4316
40fb9820 4317 if (i.types[op].bitfield.disp16
91d6fa6a 4318 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4319 {
4320 /* If this operand is at most 16 bits, convert
4321 to a signed 16 bit number and don't use 64bit
4322 displacement. */
91d6fa6a 4323 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4324 i.types[op].bitfield.disp64 = 0;
b300c311 4325 }
40fb9820 4326 if (i.types[op].bitfield.disp32
91d6fa6a 4327 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4328 {
4329 /* If this operand is at most 32 bits, convert
4330 to a signed 32 bit number and don't use 64bit
4331 displacement. */
91d6fa6a
NC		 4332 op_disp &= (((offsetT) 2 << 31) - 1);
4333 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4334 i.types[op].bitfield.disp64 = 0;
b300c311 4335 }
91d6fa6a 4336 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4337 {
40fb9820
L		 4338 i.types[op].bitfield.disp8 = 0;
4339 i.types[op].bitfield.disp16 = 0;
4340 i.types[op].bitfield.disp32 = 0;
4341 i.types[op].bitfield.disp32s = 0;
4342 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4343 i.op[op].disps = 0;
4344 i.disp_operands--;
4345 }
4346 else if (flag_code == CODE_64BIT)
4347 {
91d6fa6a 4348 if (fits_in_signed_long (op_disp))
28a9d8f5 4349 {
40fb9820
L		 4350 i.types[op].bitfield.disp64 = 0;
4351 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4352 }
0e1147d9 4353 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4354 && fits_in_unsigned_long (op_disp))
40fb9820 4355 i.types[op].bitfield.disp32 = 1;
b300c311 4356 }
40fb9820
L		 4357 if ((i.types[op].bitfield.disp32
4358 || i.types[op].bitfield.disp32s
4359 || i.types[op].bitfield.disp16)
91d6fa6a 4360 && fits_in_signed_byte (op_disp))
40fb9820 4361 i.types[op].bitfield.disp8 = 1;
252b5132 4362 }
67a4f2b7
AO		 4363 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4364 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4365 {
4366 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4367 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4368 i.types[op].bitfield.disp8 = 0;
4369 i.types[op].bitfield.disp16 = 0;
4370 i.types[op].bitfield.disp32 = 0;
4371 i.types[op].bitfield.disp32s = 0;
4372 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4373 }
4374 else
b300c311 4375 /* We only support 64bit displacement on constants. */
40fb9820 4376 i.types[op].bitfield.disp64 = 0;
252b5132 4377 }
29b0f896
AM		 4378}
4379
6c30d220
L		 4380/* Check if operands are valid for the instruction. */
4381
4382static int
4383check_VecOperands (const insn_template *t)
4384{
43234a1e
L		 4385 unsigned int op;
4386
6c30d220
L		 4387 /* Without VSIB byte, we can't have a vector register for index. */
4388 if (!t->opcode_modifier.vecsib
4389 && i.index_reg
4390 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4391 || i.index_reg->reg_type.bitfield.regymm
4392 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4393 {
4394 i.error = unsupported_vector_index_register;
4395 return 1;
4396 }
4397
ad8ecc81
MZ		 4398 /* Check if default mask is allowed. */
4399 if (t->opcode_modifier.nodefmask
4400 && (!i.mask || i.mask->mask->reg_num == 0))
4401 {
4402 i.error = no_default_mask;
4403 return 1;
4404 }
4405
7bab8ab5
JB		 4406 /* For VSIB byte, we need a vector register for index, and all vector
4407 registers must be distinct. */
4408 if (t->opcode_modifier.vecsib)
4409 {
4410 if (!i.index_reg
6c30d220
L		 4411 || !((t->opcode_modifier.vecsib == VecSIB128
4412 && i.index_reg->reg_type.bitfield.regxmm)
4413 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4414 && i.index_reg->reg_type.bitfield.regymm)
4415 || (t->opcode_modifier.vecsib == VecSIB512
4416 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4417 {
4418 i.error = invalid_vsib_address;
4419 return 1;
4420 }
4421
43234a1e
L		 4422 gas_assert (i.reg_operands == 2 || i.mask);
4423 if (i.reg_operands == 2 && !i.mask)
4424 {
4425 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4426 || i.types[0].bitfield.regymm);
43234a1e 4427 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4428 || i.types[2].bitfield.regymm);
43234a1e
L		 4429 if (operand_check == check_none)
4430 return 0;
4431 if (register_number (i.op[0].regs)
4432 != register_number (i.index_reg)
4433 && register_number (i.op[2].regs)
4434 != register_number (i.index_reg)
4435 && register_number (i.op[0].regs)
4436 != register_number (i.op[2].regs))
4437 return 0;
4438 if (operand_check == check_error)
4439 {
4440 i.error = invalid_vector_register_set;
4441 return 1;
4442 }
4443 as_warn (_("mask, index, and destination registers should be distinct"));
4444 }
8444f82a
MZ		 4445 else if (i.reg_operands == 1 && i.mask)
4446 {
4447 if ((i.types[1].bitfield.regymm
4448 || i.types[1].bitfield.regzmm)
4449 && (register_number (i.op[1].regs)
4450 == register_number (i.index_reg)))
4451 {
4452 if (operand_check == check_error)
4453 {
4454 i.error = invalid_vector_register_set;
4455 return 1;
4456 }
4457 if (operand_check != check_none)
4458 as_warn (_("index and destination registers should be distinct"));
4459 }
4460 }
43234a1e 4461 }
7bab8ab5 4462
43234a1e
L		 4463 /* Check if broadcast is supported by the instruction and is applied
4464 to the memory operand. */
4465 if (i.broadcast)
4466 {
4467 int broadcasted_opnd_size;
4468
4469 /* Check if specified broadcast is supported in this instruction,
4470 and it's applied to memory operand of DWORD or QWORD type,
4471 depending on VecESize. */
4472 if (i.broadcast->type != t->opcode_modifier.broadcast
4473 || !i.types[i.broadcast->operand].bitfield.mem
4474 || (t->opcode_modifier.vecesize == 0
4475 && !i.types[i.broadcast->operand].bitfield.dword
4476 && !i.types[i.broadcast->operand].bitfield.unspecified)
4477 || (t->opcode_modifier.vecesize == 1
4478 && !i.types[i.broadcast->operand].bitfield.qword
4479 && !i.types[i.broadcast->operand].bitfield.unspecified))
4480 goto bad_broadcast;
4481
4482 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4483 if (i.broadcast->type == BROADCAST_1TO16)
4484 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4485 else if (i.broadcast->type == BROADCAST_1TO8)
4486 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4487 else if (i.broadcast->type == BROADCAST_1TO4)
4488 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4489 else if (i.broadcast->type == BROADCAST_1TO2)
4490 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4491 else
4492 goto bad_broadcast;
4493
4494 if ((broadcasted_opnd_size == 256
4495 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4496 || (broadcasted_opnd_size == 512
4497 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4498 {
4499 bad_broadcast:
4500 i.error = unsupported_broadcast;
4501 return 1;
4502 }
4503 }
4504 /* If broadcast is supported in this instruction, we need to check if
4505 operand of one-element size isn't specified without broadcast. */
4506 else if (t->opcode_modifier.broadcast && i.mem_operands)
4507 {
4508 /* Find memory operand. */
4509 for (op = 0; op < i.operands; op++)
4510 if (operand_type_check (i.types[op], anymem))
4511 break;
4512 gas_assert (op < i.operands);
4513 /* Check size of the memory operand. */
4514 if ((t->opcode_modifier.vecesize == 0
4515 && i.types[op].bitfield.dword)
4516 || (t->opcode_modifier.vecesize == 1
4517 && i.types[op].bitfield.qword))
4518 {
4519 i.error = broadcast_needed;
4520 return 1;
4521 }
4522 }
4523
4524 /* Check if requested masking is supported. */
4525 if (i.mask
4526 && (!t->opcode_modifier.masking
4527 || (i.mask->zeroing
4528 && t->opcode_modifier.masking == MERGING_MASKING)))
4529 {
4530 i.error = unsupported_masking;
4531 return 1;
4532 }
4533
4534 /* Check if masking is applied to dest operand. */
4535 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4536 {
4537 i.error = mask_not_on_destination;
4538 return 1;
4539 }
4540
43234a1e
L		 4541 /* Check RC/SAE. */
4542 if (i.rounding)
4543 {
4544 if ((i.rounding->type != saeonly
4545 && !t->opcode_modifier.staticrounding)
4546 || (i.rounding->type == saeonly
4547 && (t->opcode_modifier.staticrounding
4548 || !t->opcode_modifier.sae)))
4549 {
4550 i.error = unsupported_rc_sae;
4551 return 1;
4552 }
4553 /* If the instruction has several immediate operands and one of
4554 them is rounding, the rounding operand should be the last
4555 immediate operand. */
4556 if (i.imm_operands > 1
4557 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4558 {
43234a1e 4559 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4560 return 1;
4561 }
6c30d220
L		 4562 }
4563
43234a1e
L		 4564 /* Check vector Disp8 operand. */
4565 if (t->opcode_modifier.disp8memshift)
4566 {
4567 if (i.broadcast)
4568 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4569 else
4570 i.memshift = t->opcode_modifier.disp8memshift;
4571
4572 for (op = 0; op < i.operands; op++)
4573 if (operand_type_check (i.types[op], disp)
4574 && i.op[op].disps->X_op == O_constant)
4575 {
4576 offsetT value = i.op[op].disps->X_add_number;
4577 int vec_disp8_ok = fits_in_vec_disp8 (value);
4578 if (t->operand_types [op].bitfield.vec_disp8)
4579 {
4580 if (vec_disp8_ok)
4581 i.types[op].bitfield.vec_disp8 = 1;
4582 else
4583 {
4584 /* Vector insn can only have Vec_Disp8/Disp32 in
4585 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4586 mode. */
4587 i.types[op].bitfield.disp8 = 0;
4588 if (flag_code != CODE_16BIT)
4589 i.types[op].bitfield.disp16 = 0;
4590 }
4591 }
4592 else if (flag_code != CODE_16BIT)
4593 {
4594 /* One form of this instruction supports vector Disp8.
4595 Try vector Disp8 if we need to use Disp32. */
4596 if (vec_disp8_ok && !fits_in_signed_byte (value))
4597 {
4598 i.error = try_vector_disp8;
4599 return 1;
4600 }
4601 }
4602 }
4603 }
4604 else
4605 i.memshift = -1;
4606
6c30d220
L		 4607 return 0;
4608}
4609
43f3e2ee 4610/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4611 operand types. */
4612
4613static int
4614VEX_check_operands (const insn_template *t)
4615{
43234a1e
L		 4616 /* VREX is only valid with EVEX prefix. */
4617 if (i.need_vrex && !t->opcode_modifier.evex)
4618 {
4619 i.error = invalid_register_operand;
4620 return 1;
4621 }
4622
a683cc34
SP		 4623 if (!t->opcode_modifier.vex)
4624 return 0;
4625
4626 /* Only check VEX_Imm4, which must be the first operand. */
4627 if (t->operand_types[0].bitfield.vec_imm4)
4628 {
4629 if (i.op[0].imms->X_op != O_constant
4630 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4631 {
a65babc9 4632 i.error = bad_imm4;
891edac4
L		 4633 return 1;
4634 }
a683cc34
SP		 4635
4636 /* Turn off Imm8 so that update_imm won't complain. */
4637 i.types[0] = vec_imm4;
4638 }
4639
4640 return 0;
4641}
4642
d3ce72d0 4643static const insn_template *
e3bb37b5 4644match_template (void)
29b0f896
AM		 4645{
4646 /* Points to template once we've found it. */
d3ce72d0 4647 const insn_template *t;
40fb9820 4648 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4649 i386_operand_type overlap4;
29b0f896 4650 unsigned int found_reverse_match;
40fb9820
L		 4651 i386_opcode_modifier suffix_check;
4652 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4653 int addr_prefix_disp;
a5c311ca 4654 unsigned int j;
3629bb00 4655 unsigned int found_cpu_match;
45664ddb 4656 unsigned int check_register;
5614d22c 4657 enum i386_error specific_error = 0;
29b0f896 4658
c0f3af97
L		 4659#if MAX_OPERANDS != 5
4660# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4661#endif
4662
29b0f896 4663 found_reverse_match = 0;
539e75ad 4664 addr_prefix_disp = -1;
40fb9820
L		 4665
4666 memset (&suffix_check, 0, sizeof (suffix_check));
4667 if (i.suffix == BYTE_MNEM_SUFFIX)
4668 suffix_check.no_bsuf = 1;
4669 else if (i.suffix == WORD_MNEM_SUFFIX)
4670 suffix_check.no_wsuf = 1;
4671 else if (i.suffix == SHORT_MNEM_SUFFIX)
4672 suffix_check.no_ssuf = 1;
4673 else if (i.suffix == LONG_MNEM_SUFFIX)
4674 suffix_check.no_lsuf = 1;
4675 else if (i.suffix == QWORD_MNEM_SUFFIX)
4676 suffix_check.no_qsuf = 1;
4677 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4678 suffix_check.no_ldsuf = 1;
29b0f896 4679
01559ecc
L		 4680 /* Must have right number of operands. */
4681 i.error = number_of_operands_mismatch;
4682
45aa61fe 4683 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4684 {
539e75ad
L		 4685 addr_prefix_disp = -1;
4686
29b0f896
AM		 4687 if (i.operands != t->operands)
4688 continue;
4689
50aecf8c 4690 /* Check processor support. */
a65babc9 4691 i.error = unsupported;
c0f3af97
L		 4692 found_cpu_match = (cpu_flags_match (t)
4693 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4694 if (!found_cpu_match)
4695 continue;
4696
e1d4d893 4697 /* Check old gcc support. */
a65babc9 4698 i.error = old_gcc_only;
e1d4d893
L		 4699 if (!old_gcc && t->opcode_modifier.oldgcc)
4700 continue;
4701
4702 /* Check AT&T mnemonic. */
a65babc9 4703 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4704 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4705 continue;
4706
891edac4 4707 /* Check AT&T/Intel syntax. */
a65babc9 4708 i.error = unsupported_syntax;
5c07affc
L		 4709 if ((intel_syntax && t->opcode_modifier.attsyntax)
4710 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4711 continue;
4712
20592a94 4713 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4714 i.error = invalid_instruction_suffix;
567e4e96
L		 4715 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4716 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4717 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4718 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4719 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4720 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4721 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4722 continue;
4723
5c07affc 4724 if (!operand_size_match (t))
7d5e4556 4725 continue;
539e75ad 4726
5c07affc
L		 4727 for (j = 0; j < MAX_OPERANDS; j++)
4728 operand_types[j] = t->operand_types[j];
4729
45aa61fe
AM		 4730 /* In general, don't allow 64-bit operands in 32-bit mode. */
4731 if (i.suffix == QWORD_MNEM_SUFFIX
4732 && flag_code != CODE_64BIT
4733 && (intel_syntax
40fb9820 4734 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4735 && !intel_float_operand (t->name))
4736 : intel_float_operand (t->name) != 2)
40fb9820 4737 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4738 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4739 && !operand_types[0].bitfield.regymm
4740 && !operand_types[0].bitfield.regzmm)
40fb9820 4741 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4742 && operand_types[t->operands > 1].bitfield.regxmm
4743 && operand_types[t->operands > 1].bitfield.regymm
4744 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4745 && (t->base_opcode != 0x0fc7
4746 || t->extension_opcode != 1 /* cmpxchg8b */))
4747 continue;
4748
192dc9c6
JB		 4749 /* In general, don't allow 32-bit operands on pre-386. */
4750 else if (i.suffix == LONG_MNEM_SUFFIX
4751 && !cpu_arch_flags.bitfield.cpui386
4752 && (intel_syntax
4753 ? (!t->opcode_modifier.ignoresize
4754 && !intel_float_operand (t->name))
4755 : intel_float_operand (t->name) != 2)
4756 && ((!operand_types[0].bitfield.regmmx
4757 && !operand_types[0].bitfield.regxmm)
4758 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 4759 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 4760 continue;
4761
29b0f896 4762 /* Do not verify operands when there are none. */
50aecf8c 4763 else
29b0f896 4764 {
c6fb90c8 4765 if (!t->operands)
2dbab7d5
L		 4766 /* We've found a match; break out of loop. */
4767 break;
29b0f896 4768 }
252b5132 4769
539e75ad
L		 4770 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4771 into Disp32/Disp16/Disp32 operand. */
4772 if (i.prefix[ADDR_PREFIX] != 0)
4773 {
40fb9820 4774 /* There should be only one Disp operand. */
539e75ad
L		 4775 switch (flag_code)
4776 {
4777 case CODE_16BIT:
40fb9820
L		 4778 for (j = 0; j < MAX_OPERANDS; j++)
4779 {
4780 if (operand_types[j].bitfield.disp16)
4781 {
4782 addr_prefix_disp = j;
4783 operand_types[j].bitfield.disp32 = 1;
4784 operand_types[j].bitfield.disp16 = 0;
4785 break;
4786 }
4787 }
539e75ad
L		 4788 break;
4789 case CODE_32BIT:
40fb9820
L		 4790 for (j = 0; j < MAX_OPERANDS; j++)
4791 {
4792 if (operand_types[j].bitfield.disp32)
4793 {
4794 addr_prefix_disp = j;
4795 operand_types[j].bitfield.disp32 = 0;
4796 operand_types[j].bitfield.disp16 = 1;
4797 break;
4798 }
4799 }
539e75ad
L		 4800 break;
4801 case CODE_64BIT:
40fb9820
L		 4802 for (j = 0; j < MAX_OPERANDS; j++)
4803 {
4804 if (operand_types[j].bitfield.disp64)
4805 {
4806 addr_prefix_disp = j;
4807 operand_types[j].bitfield.disp64 = 0;
4808 operand_types[j].bitfield.disp32 = 1;
4809 break;
4810 }
4811 }
539e75ad
L		 4812 break;
4813 }
539e75ad
L		 4814 }
4815
56ffb741
L		 4816 /* We check register size if needed. */
4817 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4818 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4819 switch (t->operands)
4820 {
4821 case 1:
40fb9820 4822 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4823 continue;
4824 break;
4825 case 2:
8b38ad71
L		 4826 /* xchg %eax, %eax is a special case. It is an aliase for nop
4827 only in 32bit mode and we can use opcode 0x90. In 64bit
4828 mode, we can't use 0x90 for xchg %eax, %eax since it should
4829 zero-extend %eax to %rax. */
4830 if (flag_code == CODE_64BIT
4831 && t->base_opcode == 0x90
0dfbf9d7
L		 4832 && operand_type_equal (&i.types [0], &acc32)
4833 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4834 continue;
b6169b20
L		 4835 if (i.swap_operand)
4836 {
4837 /* If we swap operand in encoding, we either match
4838 the next one or reverse direction of operands. */
4839 if (t->opcode_modifier.s)
4840 continue;
4841 else if (t->opcode_modifier.d)
4842 goto check_reverse;
4843 }
4844
29b0f896 4845 case 3:
fa99fab2
L		 4846 /* If we swap operand in encoding, we match the next one. */
4847 if (i.swap_operand && t->opcode_modifier.s)
4848 continue;
f48ff2ae 4849 case 4:
c0f3af97 4850 case 5:
c6fb90c8 4851 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4852 if (!operand_type_match (overlap0, i.types[0])
4853 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4854 || (check_register
4855 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4856 operand_types[0],
4857 overlap1, i.types[1],
4858 operand_types[1])))
29b0f896
AM		 4859 {
4860 /* Check if other direction is valid ... */
40fb9820 4861 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4862 continue;
4863
b6169b20 4864check_reverse:
29b0f896 4865 /* Try reversing direction of operands. */
c6fb90c8
L		 4866 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4867 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4868 if (!operand_type_match (overlap0, i.types[0])
4869 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4870 || (check_register
4871 && !operand_type_register_match (overlap0,
4872 i.types[0],
4873 operand_types[1],
4874 overlap1,
4875 i.types[1],
4876 operand_types[0])))
29b0f896
AM		 4877 {
4878 /* Does not match either direction. */
4879 continue;
4880 }
4881 /* found_reverse_match holds which of D or FloatDR
4882 we've found. */
40fb9820 4883 if (t->opcode_modifier.d)
8a2ed489 4884 found_reverse_match = Opcode_D;
40fb9820 4885 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4886 found_reverse_match = Opcode_FloatD;
4887 else
4888 found_reverse_match = 0;
40fb9820 4889 if (t->opcode_modifier.floatr)
8a2ed489 4890 found_reverse_match |= Opcode_FloatR;
29b0f896 4891 }
f48ff2ae 4892 else
29b0f896 4893 {
f48ff2ae 4894 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4895 switch (t->operands)
4896 {
c0f3af97
L		 4897 case 5:
4898 overlap4 = operand_type_and (i.types[4],
4899 operand_types[4]);
d1cbb4db 4900 case 4:
c6fb90c8
L		 4901 overlap3 = operand_type_and (i.types[3],
4902 operand_types[3]);
d1cbb4db 4903 case 3:
c6fb90c8
L		 4904 overlap2 = operand_type_and (i.types[2],
4905 operand_types[2]);
d1cbb4db
L		 4906 break;
4907 }
29b0f896 4908
f48ff2ae
L		 4909 switch (t->operands)
4910 {
c0f3af97
L		 4911 case 5:
4912 if (!operand_type_match (overlap4, i.types[4])
4913 || !operand_type_register_match (overlap3,
4914 i.types[3],
4915 operand_types[3],
4916 overlap4,
4917 i.types[4],
4918 operand_types[4]))
4919 continue;
f48ff2ae 4920 case 4:
40fb9820 4921 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4922 || (check_register
4923 && !operand_type_register_match (overlap2,
4924 i.types[2],
4925 operand_types[2],
4926 overlap3,
4927 i.types[3],
4928 operand_types[3])))
f48ff2ae
L		 4929 continue;
4930 case 3:
4931 /* Here we make use of the fact that there are no
4932 reverse match 3 operand instructions, and all 3
4933 operand instructions only need to be checked for
4934 register consistency between operands 2 and 3. */
40fb9820 4935 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4936 || (check_register
4937 && !operand_type_register_match (overlap1,
4938 i.types[1],
4939 operand_types[1],
4940 overlap2,
4941 i.types[2],
4942 operand_types[2])))
f48ff2ae
L		 4943 continue;
4944 break;
4945 }
29b0f896 4946 }
f48ff2ae 4947 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4948 slip through to break. */
4949 }
3629bb00 4950 if (!found_cpu_match)
29b0f896
AM		 4951 {
4952 found_reverse_match = 0;
4953 continue;
4954 }
c0f3af97 4955
5614d22c
JB		 4956 /* Check if vector and VEX operands are valid. */
4957 if (check_VecOperands (t) || VEX_check_operands (t))
4958 {
4959 specific_error = i.error;
4960 continue;
4961 }
a683cc34 4962
29b0f896
AM		 4963 /* We've found a match; break out of loop. */
4964 break;
4965 }
4966
4967 if (t == current_templates->end)
4968 {
4969 /* We found no match. */
a65babc9 4970 const char *err_msg;
5614d22c 4971 switch (specific_error ? specific_error : i.error)
a65babc9
L		 4972 {
4973 default:
4974 abort ();
86e026a4 4975 case operand_size_mismatch:
a65babc9
L		 4976 err_msg = _("operand size mismatch");
4977 break;
4978 case operand_type_mismatch:
4979 err_msg = _("operand type mismatch");
4980 break;
4981 case register_type_mismatch:
4982 err_msg = _("register type mismatch");
4983 break;
4984 case number_of_operands_mismatch:
4985 err_msg = _("number of operands mismatch");
4986 break;
4987 case invalid_instruction_suffix:
4988 err_msg = _("invalid instruction suffix");
4989 break;
4990 case bad_imm4:
4a2608e3 4991 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 4992 break;
4993 case old_gcc_only:
4994 err_msg = _("only supported with old gcc");
4995 break;
4996 case unsupported_with_intel_mnemonic:
4997 err_msg = _("unsupported with Intel mnemonic");
4998 break;
4999 case unsupported_syntax:
5000 err_msg = _("unsupported syntax");
5001 break;
5002 case unsupported:
35262a23 5003 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5004 current_templates->start->name);
5005 return NULL;
6c30d220
L		 5006 case invalid_vsib_address:
5007 err_msg = _("invalid VSIB address");
5008 break;
7bab8ab5
JB		 5009 case invalid_vector_register_set:
5010 err_msg = _("mask, index, and destination registers must be distinct");
5011 break;
6c30d220
L		 5012 case unsupported_vector_index_register:
5013 err_msg = _("unsupported vector index register");
5014 break;
43234a1e
L		 5015 case unsupported_broadcast:
5016 err_msg = _("unsupported broadcast");
5017 break;
5018 case broadcast_not_on_src_operand:
5019 err_msg = _("broadcast not on source memory operand");
5020 break;
5021 case broadcast_needed:
5022 err_msg = _("broadcast is needed for operand of such type");
5023 break;
5024 case unsupported_masking:
5025 err_msg = _("unsupported masking");
5026 break;
5027 case mask_not_on_destination:
5028 err_msg = _("mask not on destination operand");
5029 break;
5030 case no_default_mask:
5031 err_msg = _("default mask isn't allowed");
5032 break;
5033 case unsupported_rc_sae:
5034 err_msg = _("unsupported static rounding/sae");
5035 break;
5036 case rc_sae_operand_not_last_imm:
5037 if (intel_syntax)
5038 err_msg = _("RC/SAE operand must precede immediate operands");
5039 else
5040 err_msg = _("RC/SAE operand must follow immediate operands");
5041 break;
5042 case invalid_register_operand:
5043 err_msg = _("invalid register operand");
5044 break;
a65babc9
L		 5045 }
5046 as_bad (_("%s for `%s'"), err_msg,
891edac4 5047 current_templates->start->name);
fa99fab2 5048 return NULL;
29b0f896 5049 }
252b5132 5050
29b0f896
AM		 5051 if (!quiet_warnings)
5052 {
5053 if (!intel_syntax
40fb9820
L		 5054 && (i.types[0].bitfield.jumpabsolute
5055 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5056 {
5057 as_warn (_("indirect %s without `*'"), t->name);
5058 }
5059
40fb9820
L		 5060 if (t->opcode_modifier.isprefix
5061 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5062 {
5063 /* Warn them that a data or address size prefix doesn't
5064 affect assembly of the next line of code. */
5065 as_warn (_("stand-alone `%s' prefix"), t->name);
5066 }
5067 }
5068
5069 /* Copy the template we found. */
5070 i.tm = *t;
539e75ad
L		 5071
5072 if (addr_prefix_disp != -1)
5073 i.tm.operand_types[addr_prefix_disp]
5074 = operand_types[addr_prefix_disp];
5075
29b0f896
AM		 5076 if (found_reverse_match)
5077 {
5078 /* If we found a reverse match we must alter the opcode
5079 direction bit. found_reverse_match holds bits to change
5080 (different for int & float insns). */
5081
5082 i.tm.base_opcode ^= found_reverse_match;
5083
539e75ad
L		 5084 i.tm.operand_types[0] = operand_types[1];
5085 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5086 }
5087
fa99fab2 5088 return t;
29b0f896
AM		 5089}
5090
5091static int
e3bb37b5 5092check_string (void)
29b0f896 5093{
40fb9820
L		 5094 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5095 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5096 {
5097 if (i.seg[0] != NULL && i.seg[0] != &es)
5098 {
a87af027 5099 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5100 i.tm.name,
a87af027
JB		 5101 mem_op + 1,
5102 register_prefix);
29b0f896
AM		 5103 return 0;
5104 }
5105 /* There's only ever one segment override allowed per instruction.
5106 This instruction possibly has a legal segment override on the
5107 second operand, so copy the segment to where non-string
5108 instructions store it, allowing common code. */
5109 i.seg[0] = i.seg[1];
5110 }
40fb9820 5111 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5112 {
5113 if (i.seg[1] != NULL && i.seg[1] != &es)
5114 {
a87af027 5115 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5116 i.tm.name,
a87af027
JB		 5117 mem_op + 2,
5118 register_prefix);
29b0f896
AM		 5119 return 0;
5120 }
5121 }
5122 return 1;
5123}
5124
5125static int
543613e9 5126process_suffix (void)
29b0f896
AM		 5127{
5128 /* If matched instruction specifies an explicit instruction mnemonic
5129 suffix, use it. */
40fb9820
L		 5130 if (i.tm.opcode_modifier.size16)
5131 i.suffix = WORD_MNEM_SUFFIX;
5132 else if (i.tm.opcode_modifier.size32)
5133 i.suffix = LONG_MNEM_SUFFIX;
5134 else if (i.tm.opcode_modifier.size64)
5135 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5136 else if (i.reg_operands)
5137 {
5138 /* If there's no instruction mnemonic suffix we try to invent one
5139 based on register operands. */
5140 if (!i.suffix)
5141 {
5142 /* We take i.suffix from the last register operand specified,
5143 Destination register type is more significant than source
381d071f
L		 5144 register type. crc32 in SSE4.2 prefers source register
5145 type. */
5146 if (i.tm.base_opcode == 0xf20f38f1)
5147 {
40fb9820
L		 5148 if (i.types[0].bitfield.reg16)
5149 i.suffix = WORD_MNEM_SUFFIX;
5150 else if (i.types[0].bitfield.reg32)
5151 i.suffix = LONG_MNEM_SUFFIX;
5152 else if (i.types[0].bitfield.reg64)
5153 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5154 }
9344ff29 5155 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5156 {
40fb9820 5157 if (i.types[0].bitfield.reg8)
20592a94
L		 5158 i.suffix = BYTE_MNEM_SUFFIX;
5159 }
381d071f
L		 5160
5161 if (!i.suffix)
5162 {
5163 int op;
5164
20592a94
L		 5165 if (i.tm.base_opcode == 0xf20f38f1
5166 || i.tm.base_opcode == 0xf20f38f0)
5167 {
5168 /* We have to know the operand size for crc32. */
5169 as_bad (_("ambiguous memory operand size for `%s`"),
5170 i.tm.name);
5171 return 0;
5172 }
5173
381d071f 5174 for (op = i.operands; --op >= 0;)
40fb9820 5175 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5176 {
40fb9820
L		 5177 if (i.types[op].bitfield.reg8)
5178 {
5179 i.suffix = BYTE_MNEM_SUFFIX;
5180 break;
5181 }
5182 else if (i.types[op].bitfield.reg16)
5183 {
5184 i.suffix = WORD_MNEM_SUFFIX;
5185 break;
5186 }
5187 else if (i.types[op].bitfield.reg32)
5188 {
5189 i.suffix = LONG_MNEM_SUFFIX;
5190 break;
5191 }
5192 else if (i.types[op].bitfield.reg64)
5193 {
5194 i.suffix = QWORD_MNEM_SUFFIX;
5195 break;
5196 }
381d071f
L		 5197 }
5198 }
29b0f896
AM		 5199 }
5200 else if (i.suffix == BYTE_MNEM_SUFFIX)
5201 {
2eb952a4
L		 5202 if (intel_syntax
5203 && i.tm.opcode_modifier.ignoresize
5204 && i.tm.opcode_modifier.no_bsuf)
5205 i.suffix = 0;
5206 else if (!check_byte_reg ())
29b0f896
AM		 5207 return 0;
5208 }
5209 else if (i.suffix == LONG_MNEM_SUFFIX)
5210 {
2eb952a4
L		 5211 if (intel_syntax
5212 && i.tm.opcode_modifier.ignoresize
5213 && i.tm.opcode_modifier.no_lsuf)
5214 i.suffix = 0;
5215 else if (!check_long_reg ())
29b0f896
AM		 5216 return 0;
5217 }
5218 else if (i.suffix == QWORD_MNEM_SUFFIX)
5219 {
955e1e6a
L		 5220 if (intel_syntax
5221 && i.tm.opcode_modifier.ignoresize
5222 && i.tm.opcode_modifier.no_qsuf)
5223 i.suffix = 0;
5224 else if (!check_qword_reg ())
29b0f896
AM		 5225 return 0;
5226 }
5227 else if (i.suffix == WORD_MNEM_SUFFIX)
5228 {
2eb952a4
L		 5229 if (intel_syntax
5230 && i.tm.opcode_modifier.ignoresize
5231 && i.tm.opcode_modifier.no_wsuf)
5232 i.suffix = 0;
5233 else if (!check_word_reg ())
29b0f896
AM		 5234 return 0;
5235 }
c0f3af97 5236 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5237 || i.suffix == YMMWORD_MNEM_SUFFIX
5238 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5239 {
43234a1e 5240 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5241 should check if it is a valid suffix. */
5242 }
40fb9820 5243 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5244 /* Do nothing if the instruction is going to ignore the prefix. */
5245 ;
5246 else
5247 abort ();
5248 }
40fb9820 5249 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5250 && !i.suffix
5251 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5252 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5253 {
5254 i.suffix = stackop_size;
5255 }
9306ca4a
JB		 5256 else if (intel_syntax
5257 && !i.suffix
40fb9820
L		 5258 && (i.tm.operand_types[0].bitfield.jumpabsolute
5259 || i.tm.opcode_modifier.jumpbyte
5260 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5261 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5262 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5263 {
5264 switch (flag_code)
5265 {
5266 case CODE_64BIT:
40fb9820 5267 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5268 {
5269 i.suffix = QWORD_MNEM_SUFFIX;
5270 break;
5271 }
5272 case CODE_32BIT:
40fb9820 5273 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5274 i.suffix = LONG_MNEM_SUFFIX;
5275 break;
5276 case CODE_16BIT:
40fb9820 5277 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5278 i.suffix = WORD_MNEM_SUFFIX;
5279 break;
5280 }
5281 }
252b5132 5282
9306ca4a 5283 if (!i.suffix)
29b0f896 5284 {
9306ca4a
JB		 5285 if (!intel_syntax)
5286 {
40fb9820 5287 if (i.tm.opcode_modifier.w)
9306ca4a 5288 {
4eed87de
AM		 5289 as_bad (_("no instruction mnemonic suffix given and "
5290 "no register operands; can't size instruction"));
9306ca4a
JB		 5291 return 0;
5292 }
5293 }
5294 else
5295 {
40fb9820 5296 unsigned int suffixes;
7ab9ffdd 5297
40fb9820
L		 5298 suffixes = !i.tm.opcode_modifier.no_bsuf;
5299 if (!i.tm.opcode_modifier.no_wsuf)
5300 suffixes |= 1 << 1;
5301 if (!i.tm.opcode_modifier.no_lsuf)
5302 suffixes |= 1 << 2;
fc4adea1 5303 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5304 suffixes |= 1 << 3;
5305 if (!i.tm.opcode_modifier.no_ssuf)
5306 suffixes |= 1 << 4;
5307 if (!i.tm.opcode_modifier.no_qsuf)
5308 suffixes |= 1 << 5;
5309
5310 /* There are more than suffix matches. */
5311 if (i.tm.opcode_modifier.w
9306ca4a 5312 || ((suffixes & (suffixes - 1))
40fb9820
L		 5313 && !i.tm.opcode_modifier.defaultsize
5314 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5315 {
5316 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5317 return 0;
5318 }
5319 }
29b0f896 5320 }
252b5132 5321
9306ca4a
JB		 5322 /* Change the opcode based on the operand size given by i.suffix;
5323 We don't need to change things for byte insns. */
5324
582d5edd
L		 5325 if (i.suffix
5326 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5327 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5328 && i.suffix != YMMWORD_MNEM_SUFFIX
5329 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5330 {
5331 /* It's not a byte, select word/dword operation. */
40fb9820 5332 if (i.tm.opcode_modifier.w)
29b0f896 5333 {
40fb9820 5334 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5335 i.tm.base_opcode |= 8;
5336 else
5337 i.tm.base_opcode |= 1;
5338 }
0f3f3d8b 5339
29b0f896
AM		 5340 /* Now select between word & dword operations via the operand
5341 size prefix, except for instructions that will ignore this
5342 prefix anyway. */
ca61edf2 5343 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5344 {
ca61edf2
L		 5345 /* The address size override prefix changes the size of the
5346 first operand. */
40fb9820
L		 5347 if ((flag_code == CODE_32BIT
5348 && i.op->regs[0].reg_type.bitfield.reg16)
5349 || (flag_code != CODE_32BIT
5350 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5351 if (!add_prefix (ADDR_PREFIX_OPCODE))
5352 return 0;
5353 }
5354 else if (i.suffix != QWORD_MNEM_SUFFIX
5355 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5356 && !i.tm.opcode_modifier.ignoresize
5357 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5358 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5359 || (flag_code == CODE_64BIT
40fb9820 5360 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5361 {
5362 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5363
40fb9820 5364 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5365 prefix = ADDR_PREFIX_OPCODE;
252b5132 5366
29b0f896
AM		 5367 if (!add_prefix (prefix))
5368 return 0;
24eab124 5369 }
252b5132 5370
29b0f896
AM		 5371 /* Set mode64 for an operand. */
5372 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5373 && flag_code == CODE_64BIT
40fb9820 5374 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5375 {
5376 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5377 need rex64. cmpxchg8b is also a special case. */
5378 if (! (i.operands == 2
5379 && i.tm.base_opcode == 0x90
5380 && i.tm.extension_opcode == None
0dfbf9d7
L		 5381 && operand_type_equal (&i.types [0], &acc64)
5382 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5383 && ! (i.operands == 1
5384 && i.tm.base_opcode == 0xfc7
5385 && i.tm.extension_opcode == 1
40fb9820
L		 5386 && !operand_type_check (i.types [0], reg)
5387 && operand_type_check (i.types [0], anymem)))
f6bee062 5388 i.rex |= REX_W;
46e883c5 5389 }
3e73aa7c 5390
29b0f896
AM		 5391 /* Size floating point instruction. */
5392 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5393 if (i.tm.opcode_modifier.floatmf)
543613e9 5394 i.tm.base_opcode ^= 4;
29b0f896 5395 }
7ecd2f8b 5396
29b0f896
AM		 5397 return 1;
5398}
3e73aa7c 5399
29b0f896 5400static int
543613e9 5401check_byte_reg (void)
29b0f896
AM		 5402{
5403 int op;
543613e9 5404
29b0f896
AM		 5405 for (op = i.operands; --op >= 0;)
5406 {
5407 /* If this is an eight bit register, it's OK. If it's the 16 or
5408 32 bit version of an eight bit register, we will just use the
5409 low portion, and that's OK too. */
40fb9820 5410 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5411 continue;
5412
5a819eb9
JB		 5413 /* I/O port address operands are OK too. */
5414 if (i.tm.operand_types[op].bitfield.inoutportreg)
5415 continue;
5416
9344ff29
L		 5417 /* crc32 doesn't generate this warning. */
5418 if (i.tm.base_opcode == 0xf20f38f0)
5419 continue;
5420
40fb9820
L		 5421 if ((i.types[op].bitfield.reg16
5422 || i.types[op].bitfield.reg32
5423 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5424 && i.op[op].regs->reg_num < 4
5425 /* Prohibit these changes in 64bit mode, since the lowering
5426 would be more complicated. */
5427 && flag_code != CODE_64BIT)
29b0f896 5428 {
29b0f896 5429#if REGISTER_WARNINGS
5a819eb9 5430 if (!quiet_warnings)
a540244d
L		 5431 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5432 register_prefix,
40fb9820 5433 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5434 ? REGNAM_AL - REGNAM_AX
5435 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5436 register_prefix,
29b0f896
AM		 5437 i.op[op].regs->reg_name,
5438 i.suffix);
5439#endif
5440 continue;
5441 }
5442 /* Any other register is bad. */
40fb9820
L		 5443 if (i.types[op].bitfield.reg16
5444 || i.types[op].bitfield.reg32
5445 || i.types[op].bitfield.reg64
5446 || i.types[op].bitfield.regmmx
5447 || i.types[op].bitfield.regxmm
c0f3af97 5448 || i.types[op].bitfield.regymm
43234a1e 5449 || i.types[op].bitfield.regzmm
40fb9820
L		 5450 || i.types[op].bitfield.sreg2
5451 || i.types[op].bitfield.sreg3
5452 || i.types[op].bitfield.control
5453 || i.types[op].bitfield.debug
5454 || i.types[op].bitfield.test
5455 || i.types[op].bitfield.floatreg
5456 || i.types[op].bitfield.floatacc)
29b0f896 5457 {
a540244d
L		 5458 as_bad (_("`%s%s' not allowed with `%s%c'"),
5459 register_prefix,
29b0f896
AM		 5460 i.op[op].regs->reg_name,
5461 i.tm.name,
5462 i.suffix);
5463 return 0;
5464 }
5465 }
5466 return 1;
5467}
5468
5469static int
e3bb37b5 5470check_long_reg (void)
29b0f896
AM		 5471{
5472 int op;
5473
5474 for (op = i.operands; --op >= 0;)
5475 /* Reject eight bit registers, except where the template requires
5476 them. (eg. movzb) */
40fb9820
L		 5477 if (i.types[op].bitfield.reg8
5478 && (i.tm.operand_types[op].bitfield.reg16
5479 || i.tm.operand_types[op].bitfield.reg32
5480 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5481 {
a540244d
L		 5482 as_bad (_("`%s%s' not allowed with `%s%c'"),
5483 register_prefix,
29b0f896
AM		 5484 i.op[op].regs->reg_name,
5485 i.tm.name,
5486 i.suffix);
5487 return 0;
5488 }
e4630f71 5489 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5490 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5491 && i.types[op].bitfield.reg16
5492 && (i.tm.operand_types[op].bitfield.reg32
5493 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5494 {
5495 /* Prohibit these changes in the 64bit mode, since the
5496 lowering is more complicated. */
5497 if (flag_code == CODE_64BIT)
252b5132 5498 {
2b5d6a91 5499 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5500 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5501 i.suffix);
5502 return 0;
252b5132 5503 }
29b0f896 5504#if REGISTER_WARNINGS
cecf1424
JB		 5505 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5506 register_prefix,
5507 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5508 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5509#endif
252b5132 5510 }
e4630f71 5511 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5512 else if (i.types[op].bitfield.reg64
5513 && (i.tm.operand_types[op].bitfield.reg32
5514 || i.tm.operand_types[op].bitfield.acc))
252b5132 5515 {
34828aad 5516 if (intel_syntax
ca61edf2 5517 && i.tm.opcode_modifier.toqword
40fb9820 5518 && !i.types[0].bitfield.regxmm)
34828aad 5519 {
ca61edf2 5520 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5521 i.suffix = QWORD_MNEM_SUFFIX;
5522 }
5523 else
5524 {
2b5d6a91 5525 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5526 register_prefix, i.op[op].regs->reg_name,
5527 i.suffix);
5528 return 0;
5529 }
29b0f896
AM		 5530 }
5531 return 1;
5532}
252b5132 5533
29b0f896 5534static int
e3bb37b5 5535check_qword_reg (void)
29b0f896
AM		 5536{
5537 int op;
252b5132 5538
29b0f896
AM		 5539 for (op = i.operands; --op >= 0; )
5540 /* Reject eight bit registers, except where the template requires
5541 them. (eg. movzb) */
40fb9820
L		 5542 if (i.types[op].bitfield.reg8
5543 && (i.tm.operand_types[op].bitfield.reg16
5544 || i.tm.operand_types[op].bitfield.reg32
5545 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5546 {
a540244d
L		 5547 as_bad (_("`%s%s' not allowed with `%s%c'"),
5548 register_prefix,
29b0f896
AM		 5549 i.op[op].regs->reg_name,
5550 i.tm.name,
5551 i.suffix);
5552 return 0;
5553 }
e4630f71 5554 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5555 else if ((i.types[op].bitfield.reg16
5556 || i.types[op].bitfield.reg32)
5557 && (i.tm.operand_types[op].bitfield.reg32
5558 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5559 {
5560 /* Prohibit these changes in the 64bit mode, since the
5561 lowering is more complicated. */
34828aad 5562 if (intel_syntax
ca61edf2 5563 && i.tm.opcode_modifier.todword
40fb9820 5564 && !i.types[0].bitfield.regxmm)
34828aad 5565 {
ca61edf2 5566 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5567 i.suffix = LONG_MNEM_SUFFIX;
5568 }
5569 else
5570 {
2b5d6a91 5571 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5572 register_prefix, i.op[op].regs->reg_name,
5573 i.suffix);
5574 return 0;
5575 }
252b5132 5576 }
29b0f896
AM		 5577 return 1;
5578}
252b5132 5579
29b0f896 5580static int
e3bb37b5 5581check_word_reg (void)
29b0f896
AM		 5582{
5583 int op;
5584 for (op = i.operands; --op >= 0;)
5585 /* Reject eight bit registers, except where the template requires
5586 them. (eg. movzb) */
40fb9820
L		 5587 if (i.types[op].bitfield.reg8
5588 && (i.tm.operand_types[op].bitfield.reg16
5589 || i.tm.operand_types[op].bitfield.reg32
5590 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5591 {
a540244d
L		 5592 as_bad (_("`%s%s' not allowed with `%s%c'"),
5593 register_prefix,
29b0f896
AM		 5594 i.op[op].regs->reg_name,
5595 i.tm.name,
5596 i.suffix);
5597 return 0;
5598 }
e4630f71 5599 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5600 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5601 && (i.types[op].bitfield.reg32
5602 || i.types[op].bitfield.reg64)
40fb9820
L		 5603 && (i.tm.operand_types[op].bitfield.reg16
5604 || i.tm.operand_types[op].bitfield.acc))
252b5132 5605 {
29b0f896
AM		 5606 /* Prohibit these changes in the 64bit mode, since the
5607 lowering is more complicated. */
5608 if (flag_code == CODE_64BIT)
252b5132 5609 {
2b5d6a91 5610 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5611 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5612 i.suffix);
5613 return 0;
252b5132 5614 }
29b0f896 5615#if REGISTER_WARNINGS
cecf1424
JB		 5616 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5617 register_prefix,
5618 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5619 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5620#endif
5621 }
5622 return 1;
5623}
252b5132 5624
29b0f896 5625static int
40fb9820 5626update_imm (unsigned int j)
29b0f896 5627{
bc0844ae 5628 i386_operand_type overlap = i.types[j];
40fb9820
L		 5629 if ((overlap.bitfield.imm8
5630 || overlap.bitfield.imm8s
5631 || overlap.bitfield.imm16
5632 || overlap.bitfield.imm32
5633 || overlap.bitfield.imm32s
5634 || overlap.bitfield.imm64)
0dfbf9d7
L		 5635 && !operand_type_equal (&overlap, &imm8)
5636 && !operand_type_equal (&overlap, &imm8s)
5637 && !operand_type_equal (&overlap, &imm16)
5638 && !operand_type_equal (&overlap, &imm32)
5639 && !operand_type_equal (&overlap, &imm32s)
5640 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5641 {
5642 if (i.suffix)
5643 {
40fb9820
L		 5644 i386_operand_type temp;
5645
0dfbf9d7 5646 operand_type_set (&temp, 0);
7ab9ffdd 5647 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5648 {
5649 temp.bitfield.imm8 = overlap.bitfield.imm8;
5650 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5651 }
5652 else if (i.suffix == WORD_MNEM_SUFFIX)
5653 temp.bitfield.imm16 = overlap.bitfield.imm16;
5654 else if (i.suffix == QWORD_MNEM_SUFFIX)
5655 {
5656 temp.bitfield.imm64 = overlap.bitfield.imm64;
5657 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5658 }
5659 else
5660 temp.bitfield.imm32 = overlap.bitfield.imm32;
5661 overlap = temp;
29b0f896 5662 }
0dfbf9d7
L		 5663 else if (operand_type_equal (&overlap, &imm16_32_32s)
5664 || operand_type_equal (&overlap, &imm16_32)
5665 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5666 {
40fb9820 5667 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5668 overlap = imm16;
40fb9820 5669 else
65da13b5 5670 overlap = imm32s;
29b0f896 5671 }
0dfbf9d7
L		 5672 if (!operand_type_equal (&overlap, &imm8)
5673 && !operand_type_equal (&overlap, &imm8s)
5674 && !operand_type_equal (&overlap, &imm16)
5675 && !operand_type_equal (&overlap, &imm32)
5676 && !operand_type_equal (&overlap, &imm32s)
5677 && !operand_type_equal (&overlap, &imm64))
29b0f896 5678 {
4eed87de
AM		 5679 as_bad (_("no instruction mnemonic suffix given; "
5680 "can't determine immediate size"));
29b0f896
AM		 5681 return 0;
5682 }
5683 }
40fb9820 5684 i.types[j] = overlap;
29b0f896 5685
40fb9820
L		 5686 return 1;
5687}
5688
5689static int
5690finalize_imm (void)
5691{
bc0844ae 5692 unsigned int j, n;
29b0f896 5693
bc0844ae
L		 5694 /* Update the first 2 immediate operands. */
5695 n = i.operands > 2 ? 2 : i.operands;
5696 if (n)
5697 {
5698 for (j = 0; j < n; j++)
5699 if (update_imm (j) == 0)
5700 return 0;
40fb9820 5701
bc0844ae
L		 5702 /* The 3rd operand can't be immediate operand. */
5703 gas_assert (operand_type_check (i.types[2], imm) == 0);
5704 }
29b0f896
AM		 5705
5706 return 1;
5707}
5708
c0f3af97
L		 5709static int
5710bad_implicit_operand (int xmm)
5711{
91d6fa6a
NC		 5712 const char *ireg = xmm ? "xmm0" : "ymm0";
5713
c0f3af97
L		 5714 if (intel_syntax)
5715 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5716 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5717 else
5718 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5719 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5720 return 0;
5721}
5722
29b0f896 5723static int
e3bb37b5 5724process_operands (void)
29b0f896
AM		 5725{
5726 /* Default segment register this instruction will use for memory
5727 accesses. 0 means unknown. This is only for optimizing out
5728 unnecessary segment overrides. */
5729 const seg_entry *default_seg = 0;
5730
2426c15f 5731 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5732 {
91d6fa6a
NC		 5733 unsigned int dupl = i.operands;
5734 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5735 unsigned int j;
5736
c0f3af97 5737 /* The destination must be an xmm register. */
9c2799c2 5738 gas_assert (i.reg_operands
91d6fa6a 5739 && MAX_OPERANDS > dupl
7ab9ffdd 5740 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5741
5742 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5743 {
c0f3af97 5744 /* The first operand is implicit and must be xmm0. */
9c2799c2 5745 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5746 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5747 return bad_implicit_operand (1);
5748
8cd7925b 5749 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5750 {
5751 /* Keep xmm0 for instructions with VEX prefix and 3
5752 sources. */
5753 goto duplicate;
5754 }
e2ec9d29 5755 else
c0f3af97
L		 5756 {
5757 /* We remove the first xmm0 and keep the number of
5758 operands unchanged, which in fact duplicates the
5759 destination. */
5760 for (j = 1; j < i.operands; j++)
5761 {
5762 i.op[j - 1] = i.op[j];
5763 i.types[j - 1] = i.types[j];
5764 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5765 }
5766 }
5767 }
5768 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5769 {
91d6fa6a 5770 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5771 && (i.tm.opcode_modifier.vexsources
5772 == VEX3SOURCES));
c0f3af97
L		 5773
5774 /* Add the implicit xmm0 for instructions with VEX prefix
5775 and 3 sources. */
5776 for (j = i.operands; j > 0; j--)
5777 {
5778 i.op[j] = i.op[j - 1];
5779 i.types[j] = i.types[j - 1];
5780 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5781 }
5782 i.op[0].regs
5783 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5784 i.types[0] = regxmm;
c0f3af97
L		 5785 i.tm.operand_types[0] = regxmm;
5786
5787 i.operands += 2;
5788 i.reg_operands += 2;
5789 i.tm.operands += 2;
5790
91d6fa6a 5791 dupl++;
c0f3af97 5792 dest++;
91d6fa6a
NC		 5793 i.op[dupl] = i.op[dest];
5794 i.types[dupl] = i.types[dest];
5795 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5796 }
c0f3af97
L		 5797 else
5798 {
5799duplicate:
5800 i.operands++;
5801 i.reg_operands++;
5802 i.tm.operands++;
5803
91d6fa6a
NC		 5804 i.op[dupl] = i.op[dest];
5805 i.types[dupl] = i.types[dest];
5806 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5807 }
5808
5809 if (i.tm.opcode_modifier.immext)
5810 process_immext ();
5811 }
5812 else if (i.tm.opcode_modifier.firstxmm0)
5813 {
5814 unsigned int j;
5815
43234a1e 5816 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5817 gas_assert (i.reg_operands
7ab9ffdd 5818 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5819 || operand_type_equal (&i.types[0], &regymm)
5820 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5821 if (register_number (i.op[0].regs) != 0)
c0f3af97 5822 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5823
5824 for (j = 1; j < i.operands; j++)
5825 {
5826 i.op[j - 1] = i.op[j];
5827 i.types[j - 1] = i.types[j];
5828
5829 /* We need to adjust fields in i.tm since they are used by
5830 build_modrm_byte. */
5831 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5832 }
5833
e2ec9d29
L		 5834 i.operands--;
5835 i.reg_operands--;
e2ec9d29
L		 5836 i.tm.operands--;
5837 }
5838 else if (i.tm.opcode_modifier.regkludge)
5839 {
5840 /* The imul $imm, %reg instruction is converted into
5841 imul $imm, %reg, %reg, and the clr %reg instruction
5842 is converted into xor %reg, %reg. */
5843
5844 unsigned int first_reg_op;
5845
5846 if (operand_type_check (i.types[0], reg))
5847 first_reg_op = 0;
5848 else
5849 first_reg_op = 1;
5850 /* Pretend we saw the extra register operand. */
9c2799c2 5851 gas_assert (i.reg_operands == 1
7ab9ffdd 5852 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5853 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5854 i.types[first_reg_op + 1] = i.types[first_reg_op];
5855 i.operands++;
5856 i.reg_operands++;
29b0f896
AM		 5857 }
5858
40fb9820 5859 if (i.tm.opcode_modifier.shortform)
29b0f896 5860 {
40fb9820
L		 5861 if (i.types[0].bitfield.sreg2
5862 || i.types[0].bitfield.sreg3)
29b0f896 5863 {
4eed87de
AM		 5864 if (i.tm.base_opcode == POP_SEG_SHORT
5865 && i.op[0].regs->reg_num == 1)
29b0f896 5866 {
a87af027 5867 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5868 return 0;
29b0f896 5869 }
4eed87de
AM		 5870 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5871 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5872 i.rex |= REX_B;
4eed87de
AM		 5873 }
5874 else
5875 {
7ab9ffdd 5876 /* The register or float register operand is in operand
85f10a01 5877 0 or 1. */
40fb9820 5878 unsigned int op;
7ab9ffdd
L		 5879
5880 if (i.types[0].bitfield.floatreg
5881 || operand_type_check (i.types[0], reg))
5882 op = 0;
5883 else
5884 op = 1;
4eed87de
AM		 5885 /* Register goes in low 3 bits of opcode. */
5886 i.tm.base_opcode |= i.op[op].regs->reg_num;
5887 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5888 i.rex |= REX_B;
40fb9820 5889 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5890 {
4eed87de
AM		 5891 /* Warn about some common errors, but press on regardless.
5892 The first case can be generated by gcc (<= 2.8.1). */
5893 if (i.operands == 2)
5894 {
5895 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5896 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5897 register_prefix, i.op[!intel_syntax].regs->reg_name,
5898 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5899 }
5900 else
5901 {
5902 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5903 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5904 register_prefix, i.op[0].regs->reg_name);
4eed87de 5905 }
29b0f896
AM		 5906 }
5907 }
5908 }
40fb9820 5909 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5910 {
5911 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5912 must be put into the modrm byte). Now, we make the modrm and
5913 index base bytes based on all the info we've collected. */
29b0f896
AM		 5914
5915 default_seg = build_modrm_byte ();
5916 }
8a2ed489 5917 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5918 {
5919 default_seg = &ds;
5920 }
40fb9820 5921 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5922 {
5923 /* For the string instructions that allow a segment override
5924 on one of their operands, the default segment is ds. */
5925 default_seg = &ds;
5926 }
5927
75178d9d
L		 5928 if (i.tm.base_opcode == 0x8d /* lea */
5929 && i.seg[0]
5930 && !quiet_warnings)
30123838 5931 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5932
5933 /* If a segment was explicitly specified, and the specified segment
5934 is not the default, use an opcode prefix to select it. If we
5935 never figured out what the default segment is, then default_seg
5936 will be zero at this point, and the specified segment prefix will
5937 always be used. */
29b0f896
AM		 5938 if ((i.seg[0]) && (i.seg[0] != default_seg))
5939 {
5940 if (!add_prefix (i.seg[0]->seg_prefix))
5941 return 0;
5942 }
5943 return 1;
5944}
5945
5946static const seg_entry *
e3bb37b5 5947build_modrm_byte (void)
29b0f896
AM		 5948{
5949 const seg_entry *default_seg = 0;
c0f3af97 5950 unsigned int source, dest;
8cd7925b 5951 int vex_3_sources;
c0f3af97
L		 5952
5953 /* The first operand of instructions with VEX prefix and 3 sources
5954 must be VEX_Imm4. */
8cd7925b 5955 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5956 if (vex_3_sources)
5957 {
91d6fa6a 5958 unsigned int nds, reg_slot;
4c2c6516 5959 expressionS *exp;
c0f3af97 5960
922d8de8 5961 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5962 && i.tm.opcode_modifier.immext)
5963 {
5964 dest = i.operands - 2;
5965 gas_assert (dest == 3);
5966 }
922d8de8 5967 else
a683cc34 5968 dest = i.operands - 1;
c0f3af97 5969 nds = dest - 1;
922d8de8 5970
a683cc34
SP		 5971 /* There are 2 kinds of instructions:
5972 1. 5 operands: 4 register operands or 3 register operands
5973 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 5974 VexW0 or VexW1. The destination must be either XMM, YMM or
5975 ZMM register.
a683cc34
SP		 5976 2. 4 operands: 4 register operands or 3 register operands
5977 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5978 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5979 || (i.reg_operands == 3 && i.mem_operands == 1))
5980 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5981 && (i.tm.opcode_modifier.veximmext
5982 || (i.imm_operands == 1
5983 && i.types[0].bitfield.vec_imm4
5984 && (i.tm.opcode_modifier.vexw == VEXW0
5985 || i.tm.opcode_modifier.vexw == VEXW1)
5986 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 5987 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
5988 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 5989
5990 if (i.imm_operands == 0)
5991 {
5992 /* When there is no immediate operand, generate an 8bit
5993 immediate operand to encode the first operand. */
5994 exp = &im_expressions[i.imm_operands++];
5995 i.op[i.operands].imms = exp;
5996 i.types[i.operands] = imm8;
5997 i.operands++;
5998 /* If VexW1 is set, the first operand is the source and
5999 the second operand is encoded in the immediate operand. */
6000 if (i.tm.opcode_modifier.vexw == VEXW1)
6001 {
6002 source = 0;
6003 reg_slot = 1;
6004 }
6005 else
6006 {
6007 source = 1;
6008 reg_slot = 0;
6009 }
6010
6011 /* FMA swaps REG and NDS. */
6012 if (i.tm.cpu_flags.bitfield.cpufma)
6013 {
6014 unsigned int tmp;
6015 tmp = reg_slot;
6016 reg_slot = nds;
6017 nds = tmp;
6018 }
6019
24981e7b
L		 6020 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6021 &regxmm)
a683cc34 6022 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6023 &regymm)
6024 || operand_type_equal (&i.tm.operand_types[reg_slot],
6025 &regzmm));
a683cc34 6026 exp->X_op = O_constant;
4c692bc7 6027 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6028 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6029 }
922d8de8 6030 else
a683cc34
SP		 6031 {
6032 unsigned int imm_slot;
6033
6034 if (i.tm.opcode_modifier.vexw == VEXW0)
6035 {
6036 /* If VexW0 is set, the third operand is the source and
6037 the second operand is encoded in the immediate
6038 operand. */
6039 source = 2;
6040 reg_slot = 1;
6041 }
6042 else
6043 {
6044 /* VexW1 is set, the second operand is the source and
6045 the third operand is encoded in the immediate
6046 operand. */
6047 source = 1;
6048 reg_slot = 2;
6049 }
6050
6051 if (i.tm.opcode_modifier.immext)
6052 {
6053 /* When ImmExt is set, the immdiate byte is the last
6054 operand. */
6055 imm_slot = i.operands - 1;
6056 source--;
6057 reg_slot--;
6058 }
6059 else
6060 {
6061 imm_slot = 0;
6062
6063 /* Turn on Imm8 so that output_imm will generate it. */
6064 i.types[imm_slot].bitfield.imm8 = 1;
6065 }
6066
24981e7b
L		 6067 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6068 &regxmm)
6069 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6070 &regymm)
6071 || operand_type_equal (&i.tm.operand_types[reg_slot],
6072 &regzmm));
a683cc34 6073 i.op[imm_slot].imms->X_add_number
4c692bc7 6074 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6075 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6076 }
6077
6078 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6079 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6080 &regymm)
6081 || operand_type_equal (&i.tm.operand_types[nds],
6082 &regzmm));
dae39acc 6083 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6084 }
6085 else
6086 source = dest = 0;
29b0f896
AM		 6087
6088 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6089 implicit registers do not count. If there are 3 register
6090 operands, it must be a instruction with VexNDS. For a
6091 instruction with VexNDD, the destination register is encoded
6092 in VEX prefix. If there are 4 register operands, it must be
6093 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6094 if (i.mem_operands == 0
6095 && ((i.reg_operands == 2
2426c15f 6096 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6097 || (i.reg_operands == 3
2426c15f 6098 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6099 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6100 {
cab737b9
L		 6101 switch (i.operands)
6102 {
6103 case 2:
6104 source = 0;
6105 break;
6106 case 3:
c81128dc
L		 6107 /* When there are 3 operands, one of them may be immediate,
6108 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6109 the first operand must be shift count register (cl) or it
6110 is an instruction with VexNDS. */
9c2799c2 6111 gas_assert (i.imm_operands == 1
7ab9ffdd 6112 || (i.imm_operands == 0
2426c15f 6113 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6114 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6115 if (operand_type_check (i.types[0], imm)
6116 || i.types[0].bitfield.shiftcount)
6117 source = 1;
6118 else
6119 source = 0;
cab737b9
L		 6120 break;
6121 case 4:
368d64cc
L		 6122 /* When there are 4 operands, the first two must be 8bit
6123 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6124 one.
6125
6126 For instructions with VexNDS, if the first operand
6127 an imm8, the source operand is the 2nd one. If the last
6128 operand is imm8, the source operand is the first one. */
9c2799c2 6129 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6130 && i.types[0].bitfield.imm8
6131 && i.types[1].bitfield.imm8)
2426c15f 6132 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6133 && i.imm_operands == 1
6134 && (i.types[0].bitfield.imm8
43234a1e
L		 6135 || i.types[i.operands - 1].bitfield.imm8
6136 || i.rounding)));
9f2670f2
L		 6137 if (i.imm_operands == 2)
6138 source = 2;
6139 else
c0f3af97
L		 6140 {
6141 if (i.types[0].bitfield.imm8)
6142 source = 1;
6143 else
6144 source = 0;
6145 }
c0f3af97
L		 6146 break;
6147 case 5:
43234a1e
L		 6148 if (i.tm.opcode_modifier.evex)
6149 {
6150 /* For EVEX instructions, when there are 5 operands, the
6151 first one must be immediate operand. If the second one
6152 is immediate operand, the source operand is the 3th
6153 one. If the last one is immediate operand, the source
6154 operand is the 2nd one. */
6155 gas_assert (i.imm_operands == 2
6156 && i.tm.opcode_modifier.sae
6157 && operand_type_check (i.types[0], imm));
6158 if (operand_type_check (i.types[1], imm))
6159 source = 2;
6160 else if (operand_type_check (i.types[4], imm))
6161 source = 1;
6162 else
6163 abort ();
6164 }
cab737b9
L		 6165 break;
6166 default:
6167 abort ();
6168 }
6169
c0f3af97
L		 6170 if (!vex_3_sources)
6171 {
6172 dest = source + 1;
6173
43234a1e
L		 6174 /* RC/SAE operand could be between DEST and SRC. That happens
6175 when one operand is GPR and the other one is XMM/YMM/ZMM
6176 register. */
6177 if (i.rounding && i.rounding->operand == (int) dest)
6178 dest++;
6179
2426c15f 6180 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6181 {
43234a1e
L		 6182 /* For instructions with VexNDS, the register-only source
6183 operand must be 32/64bit integer, XMM, YMM or ZMM
6184 register. It is encoded in VEX prefix. We need to
6185 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6186
6187 i386_operand_type op;
6188 unsigned int vvvv;
6189
6190 /* Check register-only source operand when two source
6191 operands are swapped. */
6192 if (!i.tm.operand_types[source].bitfield.baseindex
6193 && i.tm.operand_types[dest].bitfield.baseindex)
6194 {
6195 vvvv = source;
6196 source = dest;
6197 }
6198 else
6199 vvvv = dest;
6200
6201 op = i.tm.operand_types[vvvv];
fa99fab2 6202 op.bitfield.regmem = 0;
c0f3af97 6203 if ((dest + 1) >= i.operands
ac4eb736
AM		 6204 || (!op.bitfield.reg32
6205 && op.bitfield.reg64
f12dc422 6206 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6207 && !operand_type_equal (&op, &regymm)
6208 && !operand_type_equal (&op, &regzmm)
6209 && !operand_type_equal (&op, &regmask)))
c0f3af97 6210 abort ();
f12dc422 6211 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6212 dest++;
6213 }
6214 }
29b0f896
AM		 6215
6216 i.rm.mode = 3;
6217 /* One of the register operands will be encoded in the i.tm.reg
6218 field, the other in the combined i.tm.mode and i.tm.regmem
6219 fields. If no form of this instruction supports a memory
6220 destination operand, then we assume the source operand may
6221 sometimes be a memory operand and so we need to store the
6222 destination in the i.rm.reg field. */
40fb9820
L		 6223 if (!i.tm.operand_types[dest].bitfield.regmem
6224 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6225 {
6226 i.rm.reg = i.op[dest].regs->reg_num;
6227 i.rm.regmem = i.op[source].regs->reg_num;
6228 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6229 i.rex |= REX_R;
43234a1e
L		 6230 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6231 i.vrex |= REX_R;
29b0f896 6232 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6233 i.rex |= REX_B;
43234a1e
L		 6234 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6235 i.vrex |= REX_B;
29b0f896
AM		 6236 }
6237 else
6238 {
6239 i.rm.reg = i.op[source].regs->reg_num;
6240 i.rm.regmem = i.op[dest].regs->reg_num;
6241 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6242 i.rex |= REX_B;
43234a1e
L		 6243 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6244 i.vrex |= REX_B;
29b0f896 6245 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6246 i.rex |= REX_R;
43234a1e
L		 6247 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6248 i.vrex |= REX_R;
29b0f896 6249 }
161a04f6 6250 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6251 {
40fb9820
L		 6252 if (!i.types[0].bitfield.control
6253 && !i.types[1].bitfield.control)
c4a530c5 6254 abort ();
161a04f6 6255 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6256 add_prefix (LOCK_PREFIX_OPCODE);
6257 }
29b0f896
AM		 6258 }
6259 else
6260 { /* If it's not 2 reg operands... */
c0f3af97
L		 6261 unsigned int mem;
6262
29b0f896
AM		 6263 if (i.mem_operands)
6264 {
6265 unsigned int fake_zero_displacement = 0;
99018f42 6266 unsigned int op;
4eed87de 6267
7ab9ffdd
L		 6268 for (op = 0; op < i.operands; op++)
6269 if (operand_type_check (i.types[op], anymem))
6270 break;
7ab9ffdd 6271 gas_assert (op < i.operands);
29b0f896 6272
6c30d220
L		 6273 if (i.tm.opcode_modifier.vecsib)
6274 {
6275 if (i.index_reg->reg_num == RegEiz
6276 || i.index_reg->reg_num == RegRiz)
6277 abort ();
6278
6279 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6280 if (!i.base_reg)
6281 {
6282 i.sib.base = NO_BASE_REGISTER;
6283 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6284 /* No Vec_Disp8 if there is no base. */
6285 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6286 i.types[op].bitfield.disp8 = 0;
6287 i.types[op].bitfield.disp16 = 0;
6288 i.types[op].bitfield.disp64 = 0;
6289 if (flag_code != CODE_64BIT)
6290 {
6291 /* Must be 32 bit */
6292 i.types[op].bitfield.disp32 = 1;
6293 i.types[op].bitfield.disp32s = 0;
6294 }
6295 else
6296 {
6297 i.types[op].bitfield.disp32 = 0;
6298 i.types[op].bitfield.disp32s = 1;
6299 }
6300 }
6301 i.sib.index = i.index_reg->reg_num;
6302 if ((i.index_reg->reg_flags & RegRex) != 0)
6303 i.rex |= REX_X;
43234a1e
L		 6304 if ((i.index_reg->reg_flags & RegVRex) != 0)
6305 i.vrex |= REX_X;
6c30d220
L		 6306 }
6307
29b0f896
AM		 6308 default_seg = &ds;
6309
6310 if (i.base_reg == 0)
6311 {
6312 i.rm.mode = 0;
6313 if (!i.disp_operands)
6c30d220
L		 6314 {
6315 fake_zero_displacement = 1;
6316 /* Instructions with VSIB byte need 32bit displacement
6317 if there is no base register. */
6318 if (i.tm.opcode_modifier.vecsib)
6319 i.types[op].bitfield.disp32 = 1;
6320 }
29b0f896
AM		 6321 if (i.index_reg == 0)
6322 {
6c30d220 6323 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6324 /* Operand is just <disp> */
20f0a1fc 6325 if (flag_code == CODE_64BIT)
29b0f896
AM		 6326 {
6327 /* 64bit mode overwrites the 32bit absolute
6328 addressing by RIP relative addressing and
6329 absolute addressing is encoded by one of the
6330 redundant SIB forms. */
6331 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6332 i.sib.base = NO_BASE_REGISTER;
6333 i.sib.index = NO_INDEX_REGISTER;
fc225355 6334 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6335 ? disp32s : disp32);
20f0a1fc 6336 }
fc225355
L		 6337 else if ((flag_code == CODE_16BIT)
6338 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6339 {
6340 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6341 i.types[op] = disp16;
20f0a1fc
NC		 6342 }
6343 else
6344 {
6345 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6346 i.types[op] = disp32;
29b0f896
AM		 6347 }
6348 }
6c30d220 6349 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6350 {
6c30d220 6351 /* !i.base_reg && i.index_reg */
db51cc60
L		 6352 if (i.index_reg->reg_num == RegEiz
6353 || i.index_reg->reg_num == RegRiz)
6354 i.sib.index = NO_INDEX_REGISTER;
6355 else
6356 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6357 i.sib.base = NO_BASE_REGISTER;
6358 i.sib.scale = i.log2_scale_factor;
6359 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6360 /* No Vec_Disp8 if there is no base. */
6361 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6362 i.types[op].bitfield.disp8 = 0;
6363 i.types[op].bitfield.disp16 = 0;
6364 i.types[op].bitfield.disp64 = 0;
29b0f896 6365 if (flag_code != CODE_64BIT)
40fb9820
L		 6366 {
6367 /* Must be 32 bit */
6368 i.types[op].bitfield.disp32 = 1;
6369 i.types[op].bitfield.disp32s = 0;
6370 }
29b0f896 6371 else
40fb9820
L		 6372 {
6373 i.types[op].bitfield.disp32 = 0;
6374 i.types[op].bitfield.disp32s = 1;
6375 }
29b0f896 6376 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6377 i.rex |= REX_X;
29b0f896
AM		 6378 }
6379 }
6380 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6381 else if (i.base_reg->reg_num == RegRip ||
6382 i.base_reg->reg_num == RegEip)
29b0f896 6383 {
6c30d220 6384 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6385 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6386 i.types[op].bitfield.disp8 = 0;
6387 i.types[op].bitfield.disp16 = 0;
6388 i.types[op].bitfield.disp32 = 0;
6389 i.types[op].bitfield.disp32s = 1;
6390 i.types[op].bitfield.disp64 = 0;
43234a1e 6391 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6392 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6393 if (! i.disp_operands)
6394 fake_zero_displacement = 1;
29b0f896 6395 }
40fb9820 6396 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6397 {
6c30d220 6398 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6399 switch (i.base_reg->reg_num)
6400 {
6401 case 3: /* (%bx) */
6402 if (i.index_reg == 0)
6403 i.rm.regmem = 7;
6404 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6405 i.rm.regmem = i.index_reg->reg_num - 6;
6406 break;
6407 case 5: /* (%bp) */
6408 default_seg = &ss;
6409 if (i.index_reg == 0)
6410 {
6411 i.rm.regmem = 6;
40fb9820 6412 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6413 {
6414 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6415 if (i.tm.operand_types[op].bitfield.vec_disp8)
6416 i.types[op].bitfield.vec_disp8 = 1;
6417 else
6418 i.types[op].bitfield.disp8 = 1;
252b5132 6419 fake_zero_displacement = 1;
29b0f896
AM		 6420 }
6421 }
6422 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6423 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6424 break;
6425 default: /* (%si) -> 4 or (%di) -> 5 */
6426 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6427 }
6428 i.rm.mode = mode_from_disp_size (i.types[op]);
6429 }
6430 else /* i.base_reg and 32/64 bit mode */
6431 {
6432 if (flag_code == CODE_64BIT
40fb9820
L		 6433 && operand_type_check (i.types[op], disp))
6434 {
6435 i386_operand_type temp;
0dfbf9d7 6436 operand_type_set (&temp, 0);
40fb9820 6437 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6438 temp.bitfield.vec_disp8
6439 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6440 i.types[op] = temp;
6441 if (i.prefix[ADDR_PREFIX] == 0)
6442 i.types[op].bitfield.disp32s = 1;
6443 else
6444 i.types[op].bitfield.disp32 = 1;
6445 }
20f0a1fc 6446
6c30d220
L		 6447 if (!i.tm.opcode_modifier.vecsib)
6448 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6449 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6450 i.rex |= REX_B;
29b0f896
AM		 6451 i.sib.base = i.base_reg->reg_num;
6452 /* x86-64 ignores REX prefix bit here to avoid decoder
6453 complications. */
848930b2
JB		 6454 if (!(i.base_reg->reg_flags & RegRex)
6455 && (i.base_reg->reg_num == EBP_REG_NUM
6456 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6457 default_seg = &ss;
848930b2 6458 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6459 {
848930b2 6460 fake_zero_displacement = 1;
43234a1e
L		 6461 if (i.tm.operand_types [op].bitfield.vec_disp8)
6462 i.types[op].bitfield.vec_disp8 = 1;
6463 else
6464 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6465 }
6466 i.sib.scale = i.log2_scale_factor;
6467 if (i.index_reg == 0)
6468 {
6c30d220 6469 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6470 /* <disp>(%esp) becomes two byte modrm with no index
6471 register. We've already stored the code for esp
6472 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6473 Any base register besides %esp will not use the
6474 extra modrm byte. */
6475 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6476 }
6c30d220 6477 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6478 {
db51cc60
L		 6479 if (i.index_reg->reg_num == RegEiz
6480 || i.index_reg->reg_num == RegRiz)
6481 i.sib.index = NO_INDEX_REGISTER;
6482 else
6483 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6484 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6485 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6486 i.rex |= REX_X;
29b0f896 6487 }
67a4f2b7
AO		 6488
6489 if (i.disp_operands
6490 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6491 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6492 i.rm.mode = 0;
6493 else
a501d77e
L		 6494 {
6495 if (!fake_zero_displacement
6496 && !i.disp_operands
6497 && i.disp_encoding)
6498 {
6499 fake_zero_displacement = 1;
6500 if (i.disp_encoding == disp_encoding_8bit)
6501 i.types[op].bitfield.disp8 = 1;
6502 else
6503 i.types[op].bitfield.disp32 = 1;
6504 }
6505 i.rm.mode = mode_from_disp_size (i.types[op]);
6506 }
29b0f896 6507 }
252b5132 6508
29b0f896
AM		 6509 if (fake_zero_displacement)
6510 {
6511 /* Fakes a zero displacement assuming that i.types[op]
6512 holds the correct displacement size. */
6513 expressionS *exp;
6514
9c2799c2 6515 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6516 exp = &disp_expressions[i.disp_operands++];
6517 i.op[op].disps = exp;
6518 exp->X_op = O_constant;
6519 exp->X_add_number = 0;
6520 exp->X_add_symbol = (symbolS *) 0;
6521 exp->X_op_symbol = (symbolS *) 0;
6522 }
c0f3af97
L		 6523
6524 mem = op;
29b0f896 6525 }
c0f3af97
L		 6526 else
6527 mem = ~0;
252b5132 6528
8c43a48b 6529 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6530 {
6531 if (operand_type_check (i.types[0], imm))
6532 i.vex.register_specifier = NULL;
6533 else
6534 {
6535 /* VEX.vvvv encodes one of the sources when the first
6536 operand is not an immediate. */
1ef99a7b 6537 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6538 i.vex.register_specifier = i.op[0].regs;
6539 else
6540 i.vex.register_specifier = i.op[1].regs;
6541 }
6542
6543 /* Destination is a XMM register encoded in the ModRM.reg
6544 and VEX.R bit. */
6545 i.rm.reg = i.op[2].regs->reg_num;
6546 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6547 i.rex |= REX_R;
6548
6549 /* ModRM.rm and VEX.B encodes the other source. */
6550 if (!i.mem_operands)
6551 {
6552 i.rm.mode = 3;
6553
1ef99a7b 6554 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6555 i.rm.regmem = i.op[1].regs->reg_num;
6556 else
6557 i.rm.regmem = i.op[0].regs->reg_num;
6558
6559 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6560 i.rex |= REX_B;
6561 }
6562 }
2426c15f 6563 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6564 {
6565 i.vex.register_specifier = i.op[2].regs;
6566 if (!i.mem_operands)
6567 {
6568 i.rm.mode = 3;
6569 i.rm.regmem = i.op[1].regs->reg_num;
6570 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6571 i.rex |= REX_B;
6572 }
6573 }
29b0f896
AM		 6574 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6575 (if any) based on i.tm.extension_opcode. Again, we must be
6576 careful to make sure that segment/control/debug/test/MMX
6577 registers are coded into the i.rm.reg field. */
f88c9eb0 6578 else if (i.reg_operands)
29b0f896 6579 {
99018f42 6580 unsigned int op;
7ab9ffdd
L		 6581 unsigned int vex_reg = ~0;
6582
6583 for (op = 0; op < i.operands; op++)
6584 if (i.types[op].bitfield.reg8
6585 || i.types[op].bitfield.reg16
6586 || i.types[op].bitfield.reg32
6587 || i.types[op].bitfield.reg64
6588 || i.types[op].bitfield.regmmx
6589 || i.types[op].bitfield.regxmm
6590 || i.types[op].bitfield.regymm
7e8b059b 6591 || i.types[op].bitfield.regbnd
43234a1e
L		 6592 || i.types[op].bitfield.regzmm
6593 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6594 || i.types[op].bitfield.sreg2
6595 || i.types[op].bitfield.sreg3
6596 || i.types[op].bitfield.control
6597 || i.types[op].bitfield.debug
6598 || i.types[op].bitfield.test)
6599 break;
c0209578 6600
7ab9ffdd
L		 6601 if (vex_3_sources)
6602 op = dest;
2426c15f 6603 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6604 {
6605 /* For instructions with VexNDS, the register-only
6606 source operand is encoded in VEX prefix. */
6607 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6608
7ab9ffdd 6609 if (op > mem)
c0f3af97 6610 {
7ab9ffdd
L		 6611 vex_reg = op++;
6612 gas_assert (op < i.operands);
c0f3af97
L		 6613 }
6614 else
c0f3af97 6615 {
f12dc422
L		 6616 /* Check register-only source operand when two source
6617 operands are swapped. */
6618 if (!i.tm.operand_types[op].bitfield.baseindex
6619 && i.tm.operand_types[op + 1].bitfield.baseindex)
6620 {
6621 vex_reg = op;
6622 op += 2;
6623 gas_assert (mem == (vex_reg + 1)
6624 && op < i.operands);
6625 }
6626 else
6627 {
6628 vex_reg = op + 1;
6629 gas_assert (vex_reg < i.operands);
6630 }
c0f3af97 6631 }
7ab9ffdd 6632 }
2426c15f 6633 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6634 {
f12dc422 6635 /* For instructions with VexNDD, the register destination
7ab9ffdd 6636 is encoded in VEX prefix. */
f12dc422
L		 6637 if (i.mem_operands == 0)
6638 {
6639 /* There is no memory operand. */
6640 gas_assert ((op + 2) == i.operands);
6641 vex_reg = op + 1;
6642 }
6643 else
8d63c93e 6644 {
f12dc422
L		 6645 /* There are only 2 operands. */
6646 gas_assert (op < 2 && i.operands == 2);
6647 vex_reg = 1;
6648 }
7ab9ffdd
L		 6649 }
6650 else
6651 gas_assert (op < i.operands);
99018f42 6652
7ab9ffdd
L		 6653 if (vex_reg != (unsigned int) ~0)
6654 {
f12dc422 6655 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6656
f12dc422
L		 6657 if (type->bitfield.reg32 != 1
6658 && type->bitfield.reg64 != 1
6659 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6660 && !operand_type_equal (type, &regymm)
6661 && !operand_type_equal (type, &regzmm)
6662 && !operand_type_equal (type, &regmask))
7ab9ffdd 6663 abort ();
f88c9eb0 6664
7ab9ffdd
L		 6665 i.vex.register_specifier = i.op[vex_reg].regs;
6666 }
6667
1b9f0c97
L		 6668 /* Don't set OP operand twice. */
6669 if (vex_reg != op)
7ab9ffdd 6670 {
1b9f0c97
L		 6671 /* If there is an extension opcode to put here, the
6672 register number must be put into the regmem field. */
6673 if (i.tm.extension_opcode != None)
6674 {
6675 i.rm.regmem = i.op[op].regs->reg_num;
6676 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6677 i.rex |= REX_B;
43234a1e
L		 6678 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6679 i.vrex |= REX_B;
1b9f0c97
L		 6680 }
6681 else
6682 {
6683 i.rm.reg = i.op[op].regs->reg_num;
6684 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6685 i.rex |= REX_R;
43234a1e
L		 6686 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6687 i.vrex |= REX_R;
1b9f0c97 6688 }
7ab9ffdd 6689 }
252b5132 6690
29b0f896
AM		 6691 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6692 must set it to 3 to indicate this is a register operand
6693 in the regmem field. */
6694 if (!i.mem_operands)
6695 i.rm.mode = 3;
6696 }
252b5132 6697
29b0f896 6698 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6699 if (i.tm.extension_opcode != None)
29b0f896
AM		 6700 i.rm.reg = i.tm.extension_opcode;
6701 }
6702 return default_seg;
6703}
252b5132 6704
29b0f896 6705static void
e3bb37b5 6706output_branch (void)
29b0f896
AM		 6707{
6708 char *p;
f8a5c266 6709 int size;
29b0f896
AM		 6710 int code16;
6711 int prefix;
6712 relax_substateT subtype;
6713 symbolS *sym;
6714 offsetT off;
6715
f8a5c266 6716 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6717 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6718
6719 prefix = 0;
6720 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6721 {
29b0f896
AM		 6722 prefix = 1;
6723 i.prefixes -= 1;
6724 code16 ^= CODE16;
252b5132 6725 }
29b0f896
AM		 6726 /* Pentium4 branch hints. */
6727 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6728 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6729 {
29b0f896
AM		 6730 prefix++;
6731 i.prefixes--;
6732 }
6733 if (i.prefix[REX_PREFIX] != 0)
6734 {
6735 prefix++;
6736 i.prefixes--;
2f66722d
AM		 6737 }
6738
7e8b059b
L		 6739 /* BND prefixed jump. */
6740 if (i.prefix[BND_PREFIX] != 0)
6741 {
6742 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6743 i.prefixes -= 1;
6744 }
6745
29b0f896
AM		 6746 if (i.prefixes != 0 && !intel_syntax)
6747 as_warn (_("skipping prefixes on this instruction"));
6748
6749 /* It's always a symbol; End frag & setup for relax.
6750 Make sure there is enough room in this frag for the largest
6751 instruction we may generate in md_convert_frag. This is 2
6752 bytes for the opcode and room for the prefix and largest
6753 displacement. */
6754 frag_grow (prefix + 2 + 4);
6755 /* Prefix and 1 opcode byte go in fr_fix. */
6756 p = frag_more (prefix + 1);
6757 if (i.prefix[DATA_PREFIX] != 0)
6758 *p++ = DATA_PREFIX_OPCODE;
6759 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6760 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6761 *p++ = i.prefix[SEG_PREFIX];
6762 if (i.prefix[REX_PREFIX] != 0)
6763 *p++ = i.prefix[REX_PREFIX];
6764 *p = i.tm.base_opcode;
6765
6766 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6767 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6768 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6769 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6770 else
f8a5c266 6771 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6772 subtype |= code16;
3e73aa7c 6773
29b0f896
AM		 6774 sym = i.op[0].disps->X_add_symbol;
6775 off = i.op[0].disps->X_add_number;
3e73aa7c 6776
29b0f896
AM		 6777 if (i.op[0].disps->X_op != O_constant
6778 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6779 {
29b0f896
AM		 6780 /* Handle complex expressions. */
6781 sym = make_expr_symbol (i.op[0].disps);
6782 off = 0;
6783 }
3e73aa7c 6784
29b0f896
AM		 6785 /* 1 possible extra opcode + 4 byte displacement go in var part.
6786 Pass reloc in fr_var. */
d258b828 6787 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 6788}
3e73aa7c 6789
29b0f896 6790static void
e3bb37b5 6791output_jump (void)
29b0f896
AM		 6792{
6793 char *p;
6794 int size;
3e02c1cc 6795 fixS *fixP;
29b0f896 6796
40fb9820 6797 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6798 {
6799 /* This is a loop or jecxz type instruction. */
6800 size = 1;
6801 if (i.prefix[ADDR_PREFIX] != 0)
6802 {
6803 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6804 i.prefixes -= 1;
6805 }
6806 /* Pentium4 branch hints. */
6807 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6808 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6809 {
6810 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6811 i.prefixes--;
3e73aa7c
JH		 6812 }
6813 }
29b0f896
AM		 6814 else
6815 {
6816 int code16;
3e73aa7c 6817
29b0f896
AM		 6818 code16 = 0;
6819 if (flag_code == CODE_16BIT)
6820 code16 = CODE16;
3e73aa7c 6821
29b0f896
AM		 6822 if (i.prefix[DATA_PREFIX] != 0)
6823 {
6824 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6825 i.prefixes -= 1;
6826 code16 ^= CODE16;
6827 }
252b5132 6828
29b0f896
AM		 6829 size = 4;
6830 if (code16)
6831 size = 2;
6832 }
9fcc94b6 6833
29b0f896
AM		 6834 if (i.prefix[REX_PREFIX] != 0)
6835 {
6836 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6837 i.prefixes -= 1;
6838 }
252b5132 6839
7e8b059b
L		 6840 /* BND prefixed jump. */
6841 if (i.prefix[BND_PREFIX] != 0)
6842 {
6843 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6844 i.prefixes -= 1;
6845 }
6846
29b0f896
AM		 6847 if (i.prefixes != 0 && !intel_syntax)
6848 as_warn (_("skipping prefixes on this instruction"));
e0890092 6849
42164a71
L		 6850 p = frag_more (i.tm.opcode_length + size);
6851 switch (i.tm.opcode_length)
6852 {
6853 case 2:
6854 *p++ = i.tm.base_opcode >> 8;
6855 case 1:
6856 *p++ = i.tm.base_opcode;
6857 break;
6858 default:
6859 abort ();
6860 }
e0890092 6861
3e02c1cc 6862 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6863 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 6864
6865 /* All jumps handled here are signed, but don't use a signed limit
6866 check for 32 and 16 bit jumps as we want to allow wrap around at
6867 4G and 64k respectively. */
6868 if (size == 1)
6869 fixP->fx_signed = 1;
29b0f896 6870}
e0890092 6871
29b0f896 6872static void
e3bb37b5 6873output_interseg_jump (void)
29b0f896
AM		 6874{
6875 char *p;
6876 int size;
6877 int prefix;
6878 int code16;
252b5132 6879
29b0f896
AM		 6880 code16 = 0;
6881 if (flag_code == CODE_16BIT)
6882 code16 = CODE16;
a217f122 6883
29b0f896
AM		 6884 prefix = 0;
6885 if (i.prefix[DATA_PREFIX] != 0)
6886 {
6887 prefix = 1;
6888 i.prefixes -= 1;
6889 code16 ^= CODE16;
6890 }
6891 if (i.prefix[REX_PREFIX] != 0)
6892 {
6893 prefix++;
6894 i.prefixes -= 1;
6895 }
252b5132 6896
29b0f896
AM		 6897 size = 4;
6898 if (code16)
6899 size = 2;
252b5132 6900
29b0f896
AM		 6901 if (i.prefixes != 0 && !intel_syntax)
6902 as_warn (_("skipping prefixes on this instruction"));
252b5132 6903
29b0f896
AM		 6904 /* 1 opcode; 2 segment; offset */
6905 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6906
29b0f896
AM		 6907 if (i.prefix[DATA_PREFIX] != 0)
6908 *p++ = DATA_PREFIX_OPCODE;
252b5132 6909
29b0f896
AM		 6910 if (i.prefix[REX_PREFIX] != 0)
6911 *p++ = i.prefix[REX_PREFIX];
252b5132 6912
29b0f896
AM		 6913 *p++ = i.tm.base_opcode;
6914 if (i.op[1].imms->X_op == O_constant)
6915 {
6916 offsetT n = i.op[1].imms->X_add_number;
252b5132 6917
29b0f896
AM		 6918 if (size == 2
6919 && !fits_in_unsigned_word (n)
6920 && !fits_in_signed_word (n))
6921 {
6922 as_bad (_("16-bit jump out of range"));
6923 return;
6924 }
6925 md_number_to_chars (p, n, size);
6926 }
6927 else
6928 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6929 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 6930 if (i.op[0].imms->X_op != O_constant)
6931 as_bad (_("can't handle non absolute segment in `%s'"),
6932 i.tm.name);
6933 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6934}
a217f122 6935
29b0f896 6936static void
e3bb37b5 6937output_insn (void)
29b0f896 6938{
2bbd9c25
JJ		 6939 fragS *insn_start_frag;
6940 offsetT insn_start_off;
6941
29b0f896
AM		 6942 /* Tie dwarf2 debug info to the address at the start of the insn.
6943 We can't do this after the insn has been output as the current
6944 frag may have been closed off. eg. by frag_var. */
6945 dwarf2_emit_insn (0);
6946
2bbd9c25
JJ		 6947 insn_start_frag = frag_now;
6948 insn_start_off = frag_now_fix ();
6949
29b0f896 6950 /* Output jumps. */
40fb9820 6951 if (i.tm.opcode_modifier.jump)
29b0f896 6952 output_branch ();
40fb9820
L		 6953 else if (i.tm.opcode_modifier.jumpbyte
6954 || i.tm.opcode_modifier.jumpdword)
29b0f896 6955 output_jump ();
40fb9820 6956 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6957 output_interseg_jump ();
6958 else
6959 {
6960 /* Output normal instructions here. */
6961 char *p;
6962 unsigned char *q;
47465058 6963 unsigned int j;
331d2d0d 6964 unsigned int prefix;
4dffcebc 6965
d022bddd
IT		 6966 /* Some processors fail on LOCK prefix. This options makes
6967 assembler ignore LOCK prefix and serves as a workaround. */
6968 if (omit_lock_prefix)
6969 {
6970 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
6971 return;
6972 i.prefix[LOCK_PREFIX] = 0;
6973 }
6974
43234a1e
L		 6975 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6976 don't need the explicit prefix. */
6977 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 6978 {
c0f3af97 6979 switch (i.tm.opcode_length)
bc4bd9ab 6980 {
c0f3af97
L		 6981 case 3:
6982 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6983 {
c0f3af97
L		 6984 prefix = (i.tm.base_opcode >> 24) & 0xff;
6985 goto check_prefix;
6986 }
6987 break;
6988 case 2:
6989 if ((i.tm.base_opcode & 0xff0000) != 0)
6990 {
6991 prefix = (i.tm.base_opcode >> 16) & 0xff;
6992 if (i.tm.cpu_flags.bitfield.cpupadlock)
6993 {
4dffcebc 6994check_prefix:
c0f3af97 6995 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6996 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6997 != REPE_PREFIX_OPCODE))
6998 add_prefix (prefix);
6999 }
7000 else
4dffcebc
L		 7001 add_prefix (prefix);
7002 }
c0f3af97
L		 7003 break;
7004 case 1:
7005 break;
7006 default:
7007 abort ();
bc4bd9ab 7008 }
c0f3af97 7009
6d19a37a 7010#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7011 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7012 R_X86_64_GOTTPOFF relocation so that linker can safely
7013 perform IE->LE optimization. */
7014 if (x86_elf_abi == X86_64_X32_ABI
7015 && i.operands == 2
7016 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7017 && i.prefix[REX_PREFIX] == 0)
7018 add_prefix (REX_OPCODE);
6d19a37a 7019#endif
cf61b747 7020
c0f3af97
L		 7021 /* The prefix bytes. */
7022 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7023 if (*q)
7024 FRAG_APPEND_1_CHAR (*q);
0f10071e 7025 }
ae5c1c7b 7026 else
c0f3af97
L		 7027 {
7028 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7029 if (*q)
7030 switch (j)
7031 {
7032 case REX_PREFIX:
7033 /* REX byte is encoded in VEX prefix. */
7034 break;
7035 case SEG_PREFIX:
7036 case ADDR_PREFIX:
7037 FRAG_APPEND_1_CHAR (*q);
7038 break;
7039 default:
7040 /* There should be no other prefixes for instructions
7041 with VEX prefix. */
7042 abort ();
7043 }
7044
43234a1e
L		 7045 /* For EVEX instructions i.vrex should become 0 after
7046 build_evex_prefix. For VEX instructions upper 16 registers
7047 aren't available, so VREX should be 0. */
7048 if (i.vrex)
7049 abort ();
c0f3af97
L		 7050 /* Now the VEX prefix. */
7051 p = frag_more (i.vex.length);
7052 for (j = 0; j < i.vex.length; j++)
7053 p[j] = i.vex.bytes[j];
7054 }
252b5132 7055
29b0f896 7056 /* Now the opcode; be careful about word order here! */
4dffcebc 7057 if (i.tm.opcode_length == 1)
29b0f896
AM		 7058 {
7059 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7060 }
7061 else
7062 {
4dffcebc 7063 switch (i.tm.opcode_length)
331d2d0d 7064 {
43234a1e
L		 7065 case 4:
7066 p = frag_more (4);
7067 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7068 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7069 break;
4dffcebc 7070 case 3:
331d2d0d
L		 7071 p = frag_more (3);
7072 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7073 break;
7074 case 2:
7075 p = frag_more (2);
7076 break;
7077 default:
7078 abort ();
7079 break;
331d2d0d 7080 }
0f10071e 7081
29b0f896
AM		 7082 /* Put out high byte first: can't use md_number_to_chars! */
7083 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7084 *p = i.tm.base_opcode & 0xff;
7085 }
3e73aa7c 7086
29b0f896 7087 /* Now the modrm byte and sib byte (if present). */
40fb9820 7088 if (i.tm.opcode_modifier.modrm)
29b0f896 7089 {
4a3523fa
L		 7090 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7091 | i.rm.reg << 3
7092 | i.rm.mode << 6));
29b0f896
AM		 7093 /* If i.rm.regmem == ESP (4)
7094 && i.rm.mode != (Register mode)
7095 && not 16 bit
7096 ==> need second modrm byte. */
7097 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7098 && i.rm.mode != 3
40fb9820 7099 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7100 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7101 | i.sib.index << 3
7102 | i.sib.scale << 6));
29b0f896 7103 }
3e73aa7c 7104
29b0f896 7105 if (i.disp_operands)
2bbd9c25 7106 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7107
29b0f896 7108 if (i.imm_operands)
2bbd9c25 7109 output_imm (insn_start_frag, insn_start_off);
29b0f896 7110 }
252b5132 7111
29b0f896
AM		 7112#ifdef DEBUG386
7113 if (flag_debug)
7114 {
7b81dfbb 7115 pi ("" /*line*/, &i);
29b0f896
AM		 7116 }
7117#endif /* DEBUG386 */
7118}
252b5132 7119
e205caa7
L		 7120/* Return the size of the displacement operand N. */
7121
7122static int
7123disp_size (unsigned int n)
7124{
7125 int size = 4;
43234a1e
L		 7126
7127 /* Vec_Disp8 has to be 8bit. */
7128 if (i.types[n].bitfield.vec_disp8)
7129 size = 1;
7130 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7131 size = 8;
7132 else if (i.types[n].bitfield.disp8)
7133 size = 1;
7134 else if (i.types[n].bitfield.disp16)
7135 size = 2;
e205caa7
L		 7136 return size;
7137}
7138
7139/* Return the size of the immediate operand N. */
7140
7141static int
7142imm_size (unsigned int n)
7143{
7144 int size = 4;
40fb9820
L		 7145 if (i.types[n].bitfield.imm64)
7146 size = 8;
7147 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7148 size = 1;
7149 else if (i.types[n].bitfield.imm16)
7150 size = 2;
e205caa7
L		 7151 return size;
7152}
7153
29b0f896 7154static void
64e74474 7155output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7156{
7157 char *p;
7158 unsigned int n;
252b5132 7159
29b0f896
AM		 7160 for (n = 0; n < i.operands; n++)
7161 {
43234a1e
L		 7162 if (i.types[n].bitfield.vec_disp8
7163 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7164 {
7165 if (i.op[n].disps->X_op == O_constant)
7166 {
e205caa7 7167 int size = disp_size (n);
43234a1e 7168 offsetT val = i.op[n].disps->X_add_number;
252b5132 7169
43234a1e
L		 7170 if (i.types[n].bitfield.vec_disp8)
7171 val >>= i.memshift;
7172 val = offset_in_range (val, size);
29b0f896
AM		 7173 p = frag_more (size);
7174 md_number_to_chars (p, val, size);
7175 }
7176 else
7177 {
f86103b7 7178 enum bfd_reloc_code_real reloc_type;
e205caa7 7179 int size = disp_size (n);
40fb9820 7180 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 7181 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7182
e205caa7 7183 /* We can't have 8 bit displacement here. */
9c2799c2 7184 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7185
29b0f896
AM		 7186 /* The PC relative address is computed relative
7187 to the instruction boundary, so in case immediate
7188 fields follows, we need to adjust the value. */
7189 if (pcrel && i.imm_operands)
7190 {
29b0f896 7191 unsigned int n1;
e205caa7 7192 int sz = 0;
252b5132 7193
29b0f896 7194 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7195 if (operand_type_check (i.types[n1], imm))
252b5132 7196 {
e205caa7
L		 7197 /* Only one immediate is allowed for PC
7198 relative address. */
9c2799c2 7199 gas_assert (sz == 0);
e205caa7
L		 7200 sz = imm_size (n1);
7201 i.op[n].disps->X_add_number -= sz;
252b5132 7202 }
29b0f896 7203 /* We should find the immediate. */
9c2799c2 7204 gas_assert (sz != 0);
29b0f896 7205 }
520dc8e8 7206
29b0f896 7207 p = frag_more (size);
d258b828 7208 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7209 if (GOT_symbol
2bbd9c25 7210 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7211 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7212 || reloc_type == BFD_RELOC_X86_64_32S
7213 || (reloc_type == BFD_RELOC_64
7214 && object_64bit))
d6ab8113
JB		 7215 && (i.op[n].disps->X_op == O_symbol
7216 || (i.op[n].disps->X_op == O_add
7217 && ((symbol_get_value_expression
7218 (i.op[n].disps->X_op_symbol)->X_op)
7219 == O_subtract))))
7220 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7221 {
7222 offsetT add;
7223
7224 if (insn_start_frag == frag_now)
7225 add = (p - frag_now->fr_literal) - insn_start_off;
7226 else
7227 {
7228 fragS *fr;
7229
7230 add = insn_start_frag->fr_fix - insn_start_off;
7231 for (fr = insn_start_frag->fr_next;
7232 fr && fr != frag_now; fr = fr->fr_next)
7233 add += fr->fr_fix;
7234 add += p - frag_now->fr_literal;
7235 }
7236
4fa24527 7237 if (!object_64bit)
7b81dfbb
AJ		 7238 {
7239 reloc_type = BFD_RELOC_386_GOTPC;
7240 i.op[n].imms->X_add_number += add;
7241 }
7242 else if (reloc_type == BFD_RELOC_64)
7243 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7244 else
7b81dfbb
AJ		 7245 /* Don't do the adjustment for x86-64, as there
7246 the pcrel addressing is relative to the _next_
7247 insn, and that is taken care of in other code. */
d6ab8113 7248 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7249 }
062cd5e7 7250 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 7251 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 7252 }
7253 }
7254 }
7255}
252b5132 7256
29b0f896 7257static void
64e74474 7258output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7259{
7260 char *p;
7261 unsigned int n;
252b5132 7262
29b0f896
AM		 7263 for (n = 0; n < i.operands; n++)
7264 {
43234a1e
L		 7265 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7266 if (i.rounding && (int) n == i.rounding->operand)
7267 continue;
7268
40fb9820 7269 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7270 {
7271 if (i.op[n].imms->X_op == O_constant)
7272 {
e205caa7 7273 int size = imm_size (n);
29b0f896 7274 offsetT val;
b4cac588 7275
29b0f896
AM		 7276 val = offset_in_range (i.op[n].imms->X_add_number,
7277 size);
7278 p = frag_more (size);
7279 md_number_to_chars (p, val, size);
7280 }
7281 else
7282 {
7283 /* Not absolute_section.
7284 Need a 32-bit fixup (don't support 8bit
7285 non-absolute imms). Try to support other
7286 sizes ... */
f86103b7 7287 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7288 int size = imm_size (n);
7289 int sign;
29b0f896 7290
40fb9820 7291 if (i.types[n].bitfield.imm32s
a7d61044 7292 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7293 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7294 sign = 1;
e205caa7
L		 7295 else
7296 sign = 0;
520dc8e8 7297
29b0f896 7298 p = frag_more (size);
d258b828 7299 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7300
2bbd9c25
JJ		 7301 /* This is tough to explain. We end up with this one if we
7302 * have operands that look like
7303 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7304 * obtain the absolute address of the GOT, and it is strongly
7305 * preferable from a performance point of view to avoid using
7306 * a runtime relocation for this. The actual sequence of
7307 * instructions often look something like:
7308 *
7309 * call .L66
7310 * .L66:
7311 * popl %ebx
7312 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7313 *
7314 * The call and pop essentially return the absolute address
7315 * of the label .L66 and store it in %ebx. The linker itself
7316 * will ultimately change the first operand of the addl so
7317 * that %ebx points to the GOT, but to keep things simple, the
7318 * .o file must have this operand set so that it generates not
7319 * the absolute address of .L66, but the absolute address of
7320 * itself. This allows the linker itself simply treat a GOTPC
7321 * relocation as asking for a pcrel offset to the GOT to be
7322 * added in, and the addend of the relocation is stored in the
7323 * operand field for the instruction itself.
7324 *
7325 * Our job here is to fix the operand so that it would add
7326 * the correct offset so that %ebx would point to itself. The
7327 * thing that is tricky is that .-.L66 will point to the
7328 * beginning of the instruction, so we need to further modify
7329 * the operand so that it will point to itself. There are
7330 * other cases where you have something like:
7331 *
7332 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7333 *
7334 * and here no correction would be required. Internally in
7335 * the assembler we treat operands of this form as not being
7336 * pcrel since the '.' is explicitly mentioned, and I wonder
7337 * whether it would simplify matters to do it this way. Who
7338 * knows. In earlier versions of the PIC patches, the
7339 * pcrel_adjust field was used to store the correction, but
7340 * since the expression is not pcrel, I felt it would be
7341 * confusing to do it this way. */
7342
d6ab8113 7343 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7344 || reloc_type == BFD_RELOC_X86_64_32S
7345 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7346 && GOT_symbol
7347 && GOT_symbol == i.op[n].imms->X_add_symbol
7348 && (i.op[n].imms->X_op == O_symbol
7349 || (i.op[n].imms->X_op == O_add
7350 && ((symbol_get_value_expression
7351 (i.op[n].imms->X_op_symbol)->X_op)
7352 == O_subtract))))
7353 {
2bbd9c25
JJ		 7354 offsetT add;
7355
7356 if (insn_start_frag == frag_now)
7357 add = (p - frag_now->fr_literal) - insn_start_off;
7358 else
7359 {
7360 fragS *fr;
7361
7362 add = insn_start_frag->fr_fix - insn_start_off;
7363 for (fr = insn_start_frag->fr_next;
7364 fr && fr != frag_now; fr = fr->fr_next)
7365 add += fr->fr_fix;
7366 add += p - frag_now->fr_literal;
7367 }
7368
4fa24527 7369 if (!object_64bit)
d6ab8113 7370 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7371 else if (size == 4)
d6ab8113 7372 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7373 else if (size == 8)
7374 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7375 i.op[n].imms->X_add_number += add;
29b0f896 7376 }
29b0f896
AM		 7377 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7378 i.op[n].imms, 0, reloc_type);
7379 }
7380 }
7381 }
252b5132
RH		 7382}
7383\f
d182319b
JB		 7384/* x86_cons_fix_new is called via the expression parsing code when a
7385 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7386static int cons_sign = -1;
7387
7388void
e3bb37b5 7389x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7390 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7391{
d258b828 7392 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7393
7394#ifdef TE_PE
7395 if (exp->X_op == O_secrel)
7396 {
7397 exp->X_op = O_symbol;
7398 r = BFD_RELOC_32_SECREL;
7399 }
7400#endif
7401
7402 fix_new_exp (frag, off, len, exp, 0, r);
7403}
7404
357d1bd8
L		 7405/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7406 purpose of the `.dc.a' internal pseudo-op. */
7407
7408int
7409x86_address_bytes (void)
7410{
7411 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7412 return 4;
7413 return stdoutput->arch_info->bits_per_address / 8;
7414}
7415
d382c579
TG		 7416#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7417 || defined (LEX_AT)
d258b828 7418# define lex_got(reloc, adjust, types) NULL
718ddfc0 7419#else
f3c180ae
AM		 7420/* Parse operands of the form
7421 <symbol>@GOTOFF+<nnn>
7422 and similar .plt or .got references.
7423
7424 If we find one, set up the correct relocation in RELOC and copy the
7425 input string, minus the `@GOTOFF' into a malloc'd buffer for
7426 parsing by the calling routine. Return this buffer, and if ADJUST
7427 is non-null set it to the length of the string we removed from the
7428 input line. Otherwise return NULL. */
7429static char *
91d6fa6a 7430lex_got (enum bfd_reloc_code_real *rel,
64e74474 7431 int *adjust,
d258b828 7432 i386_operand_type *types)
f3c180ae 7433{
7b81dfbb
AJ		 7434 /* Some of the relocations depend on the size of what field is to
7435 be relocated. But in our callers i386_immediate and i386_displacement
7436 we don't yet know the operand size (this will be set by insn
7437 matching). Hence we record the word32 relocation here,
7438 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7439 static const struct {
7440 const char *str;
cff8d58a 7441 int len;
4fa24527 7442 const enum bfd_reloc_code_real rel[2];
40fb9820 7443 const i386_operand_type types64;
f3c180ae 7444 } gotrel[] = {
8ce3d284 7445#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7446 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7447 BFD_RELOC_SIZE32 },
7448 OPERAND_TYPE_IMM32_64 },
8ce3d284 7449#endif
cff8d58a
L		 7450 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7451 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7452 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7453 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7454 BFD_RELOC_X86_64_PLT32 },
40fb9820 7455 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7456 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7457 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7458 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7459 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7460 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7461 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7462 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7463 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7464 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7465 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7466 BFD_RELOC_X86_64_TLSGD },
40fb9820 7467 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7468 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7469 _dummy_first_bfd_reloc_code_real },
40fb9820 7470 OPERAND_TYPE_NONE },
cff8d58a
L		 7471 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7472 BFD_RELOC_X86_64_TLSLD },
40fb9820 7473 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7474 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7475 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7476 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7477 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7478 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7479 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7480 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7481 _dummy_first_bfd_reloc_code_real },
40fb9820 7482 OPERAND_TYPE_NONE },
cff8d58a
L		 7483 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7484 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7485 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7486 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7487 _dummy_first_bfd_reloc_code_real },
40fb9820 7488 OPERAND_TYPE_NONE },
cff8d58a
L		 7489 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7490 _dummy_first_bfd_reloc_code_real },
40fb9820 7491 OPERAND_TYPE_NONE },
cff8d58a
L		 7492 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7493 BFD_RELOC_X86_64_GOT32 },
40fb9820 7494 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7495 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7496 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7497 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7498 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7499 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7500 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7501 };
7502 char *cp;
7503 unsigned int j;
7504
d382c579 7505#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7506 if (!IS_ELF)
7507 return NULL;
d382c579 7508#endif
718ddfc0 7509
f3c180ae 7510 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7511 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7512 return NULL;
7513
47465058 7514 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7515 {
cff8d58a 7516 int len = gotrel[j].len;
28f81592 7517 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7518 {
4fa24527 7519 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7520 {
28f81592
AM		 7521 int first, second;
7522 char *tmpbuf, *past_reloc;
f3c180ae 7523
91d6fa6a 7524 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7525
3956db08
JB		 7526 if (types)
7527 {
7528 if (flag_code != CODE_64BIT)
40fb9820
L		 7529 {
7530 types->bitfield.imm32 = 1;
7531 types->bitfield.disp32 = 1;
7532 }
3956db08
JB		 7533 else
7534 *types = gotrel[j].types64;
7535 }
7536
8fd4256d 7537 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7538 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7539
28f81592 7540 /* The length of the first part of our input line. */
f3c180ae 7541 first = cp - input_line_pointer;
28f81592
AM		 7542
7543 /* The second part goes from after the reloc token until
67c11a9b 7544 (and including) an end_of_line char or comma. */
28f81592 7545 past_reloc = cp + 1 + len;
67c11a9b
AM		 7546 cp = past_reloc;
7547 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7548 ++cp;
7549 second = cp + 1 - past_reloc;
28f81592
AM		 7550
7551 /* Allocate and copy string. The trailing NUL shouldn't
7552 be necessary, but be safe. */
1e9cc1c2 7553 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 7554 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7555 if (second != 0 && *past_reloc != ' ')
7556 /* Replace the relocation token with ' ', so that
7557 errors like foo@GOTOFF1 will be detected. */
7558 tmpbuf[first++] = ' ';
af89796a
L		 7559 else
7560 /* Increment length by 1 if the relocation token is
7561 removed. */
7562 len++;
7563 if (adjust)
7564 *adjust = len;
0787a12d
AM		 7565 memcpy (tmpbuf + first, past_reloc, second);
7566 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7567 return tmpbuf;
7568 }
7569
4fa24527
JB		 7570 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7571 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7572 return NULL;
7573 }
7574 }
7575
7576 /* Might be a symbol version string. Don't as_bad here. */
7577 return NULL;
7578}
4e4f7c87 7579#endif
f3c180ae 7580
a988325c
NC		 7581#ifdef TE_PE
7582#ifdef lex_got
7583#undef lex_got
7584#endif
7585/* Parse operands of the form
7586 <symbol>@SECREL32+<nnn>
7587
7588 If we find one, set up the correct relocation in RELOC and copy the
7589 input string, minus the `@SECREL32' into a malloc'd buffer for
7590 parsing by the calling routine. Return this buffer, and if ADJUST
7591 is non-null set it to the length of the string we removed from the
34bca508
L		 7592 input line. Otherwise return NULL.
7593
a988325c
NC		 7594 This function is copied from the ELF version above adjusted for PE targets. */
7595
7596static char *
7597lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7598 int *adjust ATTRIBUTE_UNUSED,
d258b828 7599 i386_operand_type *types)
a988325c
NC		 7600{
7601 static const struct
7602 {
7603 const char *str;
7604 int len;
7605 const enum bfd_reloc_code_real rel[2];
7606 const i386_operand_type types64;
7607 }
7608 gotrel[] =
7609 {
7610 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7611 BFD_RELOC_32_SECREL },
7612 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7613 };
7614
7615 char *cp;
7616 unsigned j;
7617
7618 for (cp = input_line_pointer; *cp != '@'; cp++)
7619 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7620 return NULL;
7621
7622 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7623 {
7624 int len = gotrel[j].len;
7625
7626 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7627 {
7628 if (gotrel[j].rel[object_64bit] != 0)
7629 {
7630 int first, second;
7631 char *tmpbuf, *past_reloc;
7632
7633 *rel = gotrel[j].rel[object_64bit];
7634 if (adjust)
7635 *adjust = len;
7636
7637 if (types)
7638 {
7639 if (flag_code != CODE_64BIT)
7640 {
7641 types->bitfield.imm32 = 1;
7642 types->bitfield.disp32 = 1;
7643 }
7644 else
7645 *types = gotrel[j].types64;
7646 }
7647
7648 /* The length of the first part of our input line. */
7649 first = cp - input_line_pointer;
7650
7651 /* The second part goes from after the reloc token until
7652 (and including) an end_of_line char or comma. */
7653 past_reloc = cp + 1 + len;
7654 cp = past_reloc;
7655 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7656 ++cp;
7657 second = cp + 1 - past_reloc;
7658
7659 /* Allocate and copy string. The trailing NUL shouldn't
7660 be necessary, but be safe. */
7661 tmpbuf = (char *) xmalloc (first + second + 2);
7662 memcpy (tmpbuf, input_line_pointer, first);
7663 if (second != 0 && *past_reloc != ' ')
7664 /* Replace the relocation token with ' ', so that
7665 errors like foo@SECLREL321 will be detected. */
7666 tmpbuf[first++] = ' ';
7667 memcpy (tmpbuf + first, past_reloc, second);
7668 tmpbuf[first + second] = '\0';
7669 return tmpbuf;
7670 }
7671
7672 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7673 gotrel[j].str, 1 << (5 + object_64bit));
7674 return NULL;
7675 }
7676 }
7677
7678 /* Might be a symbol version string. Don't as_bad here. */
7679 return NULL;
7680}
7681
7682#endif /* TE_PE */
7683
62ebcb5c 7684bfd_reloc_code_real_type
e3bb37b5 7685x86_cons (expressionS *exp, int size)
f3c180ae 7686{
62ebcb5c
AM		 7687 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7688
ee86248c
JB		 7689 intel_syntax = -intel_syntax;
7690
3c7b9c2c 7691 exp->X_md = 0;
4fa24527 7692 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7693 {
7694 /* Handle @GOTOFF and the like in an expression. */
7695 char *save;
7696 char *gotfree_input_line;
4a57f2cf 7697 int adjust = 0;
f3c180ae
AM		 7698
7699 save = input_line_pointer;
d258b828 7700 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 7701 if (gotfree_input_line)
7702 input_line_pointer = gotfree_input_line;
7703
7704 expression (exp);
7705
7706 if (gotfree_input_line)
7707 {
7708 /* expression () has merrily parsed up to the end of line,
7709 or a comma - in the wrong buffer. Transfer how far
7710 input_line_pointer has moved to the right buffer. */
7711 input_line_pointer = (save
7712 + (input_line_pointer - gotfree_input_line)
7713 + adjust);
7714 free (gotfree_input_line);
3992d3b7
AM		 7715 if (exp->X_op == O_constant
7716 || exp->X_op == O_absent
7717 || exp->X_op == O_illegal
0398aac5 7718 || exp->X_op == O_register
3992d3b7
AM		 7719 || exp->X_op == O_big)
7720 {
7721 char c = *input_line_pointer;
7722 *input_line_pointer = 0;
7723 as_bad (_("missing or invalid expression `%s'"), save);
7724 *input_line_pointer = c;
7725 }
f3c180ae
AM		 7726 }
7727 }
7728 else
7729 expression (exp);
ee86248c
JB		 7730
7731 intel_syntax = -intel_syntax;
7732
7733 if (intel_syntax)
7734 i386_intel_simplify (exp);
62ebcb5c
AM		 7735
7736 return got_reloc;
f3c180ae 7737}
f3c180ae 7738
9f32dd5b
L		 7739static void
7740signed_cons (int size)
6482c264 7741{
d182319b
JB		 7742 if (flag_code == CODE_64BIT)
7743 cons_sign = 1;
7744 cons (size);
7745 cons_sign = -1;
6482c264
NC		 7746}
7747
d182319b 7748#ifdef TE_PE
6482c264 7749static void
7016a5d5 7750pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7751{
7752 expressionS exp;
7753
7754 do
7755 {
7756 expression (&exp);
7757 if (exp.X_op == O_symbol)
7758 exp.X_op = O_secrel;
7759
7760 emit_expr (&exp, 4);
7761 }
7762 while (*input_line_pointer++ == ',');
7763
7764 input_line_pointer--;
7765 demand_empty_rest_of_line ();
7766}
6482c264
NC		 7767#endif
7768
43234a1e
L		 7769/* Handle Vector operations. */
7770
7771static char *
7772check_VecOperations (char *op_string, char *op_end)
7773{
7774 const reg_entry *mask;
7775 const char *saved;
7776 char *end_op;
7777
7778 while (*op_string
7779 && (op_end == NULL || op_string < op_end))
7780 {
7781 saved = op_string;
7782 if (*op_string == '{')
7783 {
7784 op_string++;
7785
7786 /* Check broadcasts. */
7787 if (strncmp (op_string, "1to", 3) == 0)
7788 {
7789 int bcst_type;
7790
7791 if (i.broadcast)
7792 goto duplicated_vec_op;
7793
7794 op_string += 3;
7795 if (*op_string == '8')
7796 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 7797 else if (*op_string == '4')
7798 bcst_type = BROADCAST_1TO4;
7799 else if (*op_string == '2')
7800 bcst_type = BROADCAST_1TO2;
43234a1e
L		 7801 else if (*op_string == '1'
7802 && *(op_string+1) == '6')
7803 {
7804 bcst_type = BROADCAST_1TO16;
7805 op_string++;
7806 }
7807 else
7808 {
7809 as_bad (_("Unsupported broadcast: `%s'"), saved);
7810 return NULL;
7811 }
7812 op_string++;
7813
7814 broadcast_op.type = bcst_type;
7815 broadcast_op.operand = this_operand;
7816 i.broadcast = &broadcast_op;
7817 }
7818 /* Check masking operation. */
7819 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7820 {
7821 /* k0 can't be used for write mask. */
7822 if (mask->reg_num == 0)
7823 {
7824 as_bad (_("`%s' can't be used for write mask"),
7825 op_string);
7826 return NULL;
7827 }
7828
7829 if (!i.mask)
7830 {
7831 mask_op.mask = mask;
7832 mask_op.zeroing = 0;
7833 mask_op.operand = this_operand;
7834 i.mask = &mask_op;
7835 }
7836 else
7837 {
7838 if (i.mask->mask)
7839 goto duplicated_vec_op;
7840
7841 i.mask->mask = mask;
7842
7843 /* Only "{z}" is allowed here. No need to check
7844 zeroing mask explicitly. */
7845 if (i.mask->operand != this_operand)
7846 {
7847 as_bad (_("invalid write mask `%s'"), saved);
7848 return NULL;
7849 }
7850 }
7851
7852 op_string = end_op;
7853 }
7854 /* Check zeroing-flag for masking operation. */
7855 else if (*op_string == 'z')
7856 {
7857 if (!i.mask)
7858 {
7859 mask_op.mask = NULL;
7860 mask_op.zeroing = 1;
7861 mask_op.operand = this_operand;
7862 i.mask = &mask_op;
7863 }
7864 else
7865 {
7866 if (i.mask->zeroing)
7867 {
7868 duplicated_vec_op:
7869 as_bad (_("duplicated `%s'"), saved);
7870 return NULL;
7871 }
7872
7873 i.mask->zeroing = 1;
7874
7875 /* Only "{%k}" is allowed here. No need to check mask
7876 register explicitly. */
7877 if (i.mask->operand != this_operand)
7878 {
7879 as_bad (_("invalid zeroing-masking `%s'"),
7880 saved);
7881 return NULL;
7882 }
7883 }
7884
7885 op_string++;
7886 }
7887 else
7888 goto unknown_vec_op;
7889
7890 if (*op_string != '}')
7891 {
7892 as_bad (_("missing `}' in `%s'"), saved);
7893 return NULL;
7894 }
7895 op_string++;
7896 continue;
7897 }
7898 unknown_vec_op:
7899 /* We don't know this one. */
7900 as_bad (_("unknown vector operation: `%s'"), saved);
7901 return NULL;
7902 }
7903
7904 return op_string;
7905}
7906
252b5132 7907static int
70e41ade 7908i386_immediate (char *imm_start)
252b5132
RH		 7909{
7910 char *save_input_line_pointer;
f3c180ae 7911 char *gotfree_input_line;
252b5132 7912 segT exp_seg = 0;
47926f60 7913 expressionS *exp;
40fb9820
L		 7914 i386_operand_type types;
7915
0dfbf9d7 7916 operand_type_set (&types, ~0);
252b5132
RH		 7917
7918 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7919 {
31b2323c
L		 7920 as_bad (_("at most %d immediate operands are allowed"),
7921 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 7922 return 0;
7923 }
7924
7925 exp = &im_expressions[i.imm_operands++];
520dc8e8 7926 i.op[this_operand].imms = exp;
252b5132
RH		 7927
7928 if (is_space_char (*imm_start))
7929 ++imm_start;
7930
7931 save_input_line_pointer = input_line_pointer;
7932 input_line_pointer = imm_start;
7933
d258b828 7934 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 7935 if (gotfree_input_line)
7936 input_line_pointer = gotfree_input_line;
252b5132
RH		 7937
7938 exp_seg = expression (exp);
7939
83183c0c 7940 SKIP_WHITESPACE ();
43234a1e
L		 7941
7942 /* Handle vector operations. */
7943 if (*input_line_pointer == '{')
7944 {
7945 input_line_pointer = check_VecOperations (input_line_pointer,
7946 NULL);
7947 if (input_line_pointer == NULL)
7948 return 0;
7949 }
7950
252b5132 7951 if (*input_line_pointer)
f3c180ae 7952 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 7953
7954 input_line_pointer = save_input_line_pointer;
f3c180ae 7955 if (gotfree_input_line)
ee86248c
JB		 7956 {
7957 free (gotfree_input_line);
7958
7959 if (exp->X_op == O_constant || exp->X_op == O_register)
7960 exp->X_op = O_illegal;
7961 }
7962
7963 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7964}
252b5132 7965
ee86248c
JB		 7966static int
7967i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7968 i386_operand_type types, const char *imm_start)
7969{
7970 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 7971 {
313c53d1
L		 7972 if (imm_start)
7973 as_bad (_("missing or invalid immediate expression `%s'"),
7974 imm_start);
3992d3b7 7975 return 0;
252b5132 7976 }
3e73aa7c 7977 else if (exp->X_op == O_constant)
252b5132 7978 {
47926f60 7979 /* Size it properly later. */
40fb9820 7980 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 7981 /* If not 64bit, sign extend val. */
7982 if (flag_code != CODE_64BIT
4eed87de
AM		 7983 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7984 exp->X_add_number
7985 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 7986 }
4c63da97 7987#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 7988 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 7989 && exp_seg != absolute_section
47926f60 7990 && exp_seg != text_section
24eab124
AM		 7991 && exp_seg != data_section
7992 && exp_seg != bss_section
7993 && exp_seg != undefined_section
f86103b7 7994 && !bfd_is_com_section (exp_seg))
252b5132 7995 {
d0b47220 7996 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 7997 return 0;
7998 }
7999#endif
a841bdf5 8000 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8001 {
313c53d1
L		 8002 if (imm_start)
8003 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8004 return 0;
8005 }
252b5132
RH		 8006 else
8007 {
8008 /* This is an address. The size of the address will be
24eab124 8009 determined later, depending on destination register,
3e73aa7c 8010 suffix, or the default for the section. */
40fb9820
L		 8011 i.types[this_operand].bitfield.imm8 = 1;
8012 i.types[this_operand].bitfield.imm16 = 1;
8013 i.types[this_operand].bitfield.imm32 = 1;
8014 i.types[this_operand].bitfield.imm32s = 1;
8015 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8016 i.types[this_operand] = operand_type_and (i.types[this_operand],
8017 types);
252b5132
RH		 8018 }
8019
8020 return 1;
8021}
8022
551c1ca1 8023static char *
e3bb37b5 8024i386_scale (char *scale)
252b5132 8025{
551c1ca1
AM		 8026 offsetT val;
8027 char *save = input_line_pointer;
252b5132 8028
551c1ca1
AM		 8029 input_line_pointer = scale;
8030 val = get_absolute_expression ();
8031
8032 switch (val)
252b5132 8033 {
551c1ca1 8034 case 1:
252b5132
RH		 8035 i.log2_scale_factor = 0;
8036 break;
551c1ca1 8037 case 2:
252b5132
RH		 8038 i.log2_scale_factor = 1;
8039 break;
551c1ca1 8040 case 4:
252b5132
RH		 8041 i.log2_scale_factor = 2;
8042 break;
551c1ca1 8043 case 8:
252b5132
RH		 8044 i.log2_scale_factor = 3;
8045 break;
8046 default:
a724f0f4
JB		 8047 {
8048 char sep = *input_line_pointer;
8049
8050 *input_line_pointer = '\0';
8051 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8052 scale);
8053 *input_line_pointer = sep;
8054 input_line_pointer = save;
8055 return NULL;
8056 }
252b5132 8057 }
29b0f896 8058 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8059 {
8060 as_warn (_("scale factor of %d without an index register"),
24eab124 8061 1 << i.log2_scale_factor);
252b5132 8062 i.log2_scale_factor = 0;
252b5132 8063 }
551c1ca1
AM		 8064 scale = input_line_pointer;
8065 input_line_pointer = save;
8066 return scale;
252b5132
RH		 8067}
8068
252b5132 8069static int
e3bb37b5 8070i386_displacement (char *disp_start, char *disp_end)
252b5132 8071{
29b0f896 8072 expressionS *exp;
252b5132
RH		 8073 segT exp_seg = 0;
8074 char *save_input_line_pointer;
f3c180ae 8075 char *gotfree_input_line;
40fb9820
L		 8076 int override;
8077 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8078 int ret;
252b5132 8079
31b2323c
L		 8080 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8081 {
8082 as_bad (_("at most %d displacement operands are allowed"),
8083 MAX_MEMORY_OPERANDS);
8084 return 0;
8085 }
8086
0dfbf9d7 8087 operand_type_set (&bigdisp, 0);
40fb9820
L		 8088 if ((i.types[this_operand].bitfield.jumpabsolute)
8089 || (!current_templates->start->opcode_modifier.jump
8090 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8091 {
40fb9820 8092 bigdisp.bitfield.disp32 = 1;
e05278af 8093 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8094 if (flag_code == CODE_64BIT)
8095 {
8096 if (!override)
8097 {
8098 bigdisp.bitfield.disp32s = 1;
8099 bigdisp.bitfield.disp64 = 1;
8100 }
8101 }
8102 else if ((flag_code == CODE_16BIT) ^ override)
8103 {
8104 bigdisp.bitfield.disp32 = 0;
8105 bigdisp.bitfield.disp16 = 1;
8106 }
e05278af
JB		 8107 }
8108 else
8109 {
8110 /* For PC-relative branches, the width of the displacement
8111 is dependent upon data size, not address size. */
e05278af 8112 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8113 if (flag_code == CODE_64BIT)
8114 {
8115 if (override || i.suffix == WORD_MNEM_SUFFIX)
8116 bigdisp.bitfield.disp16 = 1;
8117 else
8118 {
8119 bigdisp.bitfield.disp32 = 1;
8120 bigdisp.bitfield.disp32s = 1;
8121 }
8122 }
8123 else
e05278af
JB		 8124 {
8125 if (!override)
8126 override = (i.suffix == (flag_code != CODE_16BIT
8127 ? WORD_MNEM_SUFFIX
8128 : LONG_MNEM_SUFFIX));
40fb9820
L		 8129 bigdisp.bitfield.disp32 = 1;
8130 if ((flag_code == CODE_16BIT) ^ override)
8131 {
8132 bigdisp.bitfield.disp32 = 0;
8133 bigdisp.bitfield.disp16 = 1;
8134 }
e05278af 8135 }
e05278af 8136 }
c6fb90c8
L		 8137 i.types[this_operand] = operand_type_or (i.types[this_operand],
8138 bigdisp);
252b5132
RH		 8139
8140 exp = &disp_expressions[i.disp_operands];
520dc8e8 8141 i.op[this_operand].disps = exp;
252b5132
RH		 8142 i.disp_operands++;
8143 save_input_line_pointer = input_line_pointer;
8144 input_line_pointer = disp_start;
8145 END_STRING_AND_SAVE (disp_end);
8146
8147#ifndef GCC_ASM_O_HACK
8148#define GCC_ASM_O_HACK 0
8149#endif
8150#if GCC_ASM_O_HACK
8151 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8152 if (i.types[this_operand].bitfield.baseIndex
24eab124 8153 && displacement_string_end[-1] == '+')
252b5132
RH		 8154 {
8155 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8156 constraint within gcc asm statements.
8157 For instance:
8158
8159 #define _set_tssldt_desc(n,addr,limit,type) \
8160 __asm__ __volatile__ ( \
8161 "movw %w2,%0\n\t" \
8162 "movw %w1,2+%0\n\t" \
8163 "rorl $16,%1\n\t" \
8164 "movb %b1,4+%0\n\t" \
8165 "movb %4,5+%0\n\t" \
8166 "movb $0,6+%0\n\t" \
8167 "movb %h1,7+%0\n\t" \
8168 "rorl $16,%1" \
8169 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8170
8171 This works great except that the output assembler ends
8172 up looking a bit weird if it turns out that there is
8173 no offset. You end up producing code that looks like:
8174
8175 #APP
8176 movw $235,(%eax)
8177 movw %dx,2+(%eax)
8178 rorl $16,%edx
8179 movb %dl,4+(%eax)
8180 movb $137,5+(%eax)
8181 movb $0,6+(%eax)
8182 movb %dh,7+(%eax)
8183 rorl $16,%edx
8184 #NO_APP
8185
47926f60 8186 So here we provide the missing zero. */
24eab124
AM		 8187
8188 *displacement_string_end = '0';
252b5132
RH		 8189 }
8190#endif
d258b828 8191 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8192 if (gotfree_input_line)
8193 input_line_pointer = gotfree_input_line;
252b5132 8194
24eab124 8195 exp_seg = expression (exp);
252b5132 8196
636c26b0
AM		 8197 SKIP_WHITESPACE ();
8198 if (*input_line_pointer)
8199 as_bad (_("junk `%s' after expression"), input_line_pointer);
8200#if GCC_ASM_O_HACK
8201 RESTORE_END_STRING (disp_end + 1);
8202#endif
636c26b0 8203 input_line_pointer = save_input_line_pointer;
636c26b0 8204 if (gotfree_input_line)
ee86248c
JB		 8205 {
8206 free (gotfree_input_line);
8207
8208 if (exp->X_op == O_constant || exp->X_op == O_register)
8209 exp->X_op = O_illegal;
8210 }
8211
8212 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8213
8214 RESTORE_END_STRING (disp_end);
8215
8216 return ret;
8217}
8218
8219static int
8220i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8221 i386_operand_type types, const char *disp_start)
8222{
8223 i386_operand_type bigdisp;
8224 int ret = 1;
636c26b0 8225
24eab124
AM		 8226 /* We do this to make sure that the section symbol is in
8227 the symbol table. We will ultimately change the relocation
47926f60 8228 to be relative to the beginning of the section. */
1ae12ab7 8229 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8230 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8231 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8232 {
636c26b0 8233 if (exp->X_op != O_symbol)
3992d3b7 8234 goto inv_disp;
636c26b0 8235
e5cb08ac 8236 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8237 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8238 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8239 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8240 exp->X_op = O_subtract;
8241 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8242 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8243 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8244 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8245 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8246 else
29b0f896 8247 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8248 }
252b5132 8249
3992d3b7
AM		 8250 else if (exp->X_op == O_absent
8251 || exp->X_op == O_illegal
ee86248c 8252 || exp->X_op == O_big)
2daf4fd8 8253 {
3992d3b7
AM		 8254 inv_disp:
8255 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8256 disp_start);
3992d3b7 8257 ret = 0;
2daf4fd8
AM		 8258 }
8259
0e1147d9
L		 8260 else if (flag_code == CODE_64BIT
8261 && !i.prefix[ADDR_PREFIX]
8262 && exp->X_op == O_constant)
8263 {
8264 /* Since displacement is signed extended to 64bit, don't allow
8265 disp32 and turn off disp32s if they are out of range. */
8266 i.types[this_operand].bitfield.disp32 = 0;
8267 if (!fits_in_signed_long (exp->X_add_number))
8268 {
8269 i.types[this_operand].bitfield.disp32s = 0;
8270 if (i.types[this_operand].bitfield.baseindex)
8271 {
8272 as_bad (_("0x%lx out range of signed 32bit displacement"),
8273 (long) exp->X_add_number);
8274 ret = 0;
8275 }
8276 }
8277 }
8278
4c63da97 8279#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8280 else if (exp->X_op != O_constant
8281 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8282 && exp_seg != absolute_section
8283 && exp_seg != text_section
8284 && exp_seg != data_section
8285 && exp_seg != bss_section
8286 && exp_seg != undefined_section
8287 && !bfd_is_com_section (exp_seg))
24eab124 8288 {
d0b47220 8289 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8290 ret = 0;
24eab124 8291 }
252b5132 8292#endif
3956db08 8293
40fb9820
L		 8294 /* Check if this is a displacement only operand. */
8295 bigdisp = i.types[this_operand];
8296 bigdisp.bitfield.disp8 = 0;
8297 bigdisp.bitfield.disp16 = 0;
8298 bigdisp.bitfield.disp32 = 0;
8299 bigdisp.bitfield.disp32s = 0;
8300 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8301 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8302 i.types[this_operand] = operand_type_and (i.types[this_operand],
8303 types);
3956db08 8304
3992d3b7 8305 return ret;
252b5132
RH		 8306}
8307
eecb386c 8308/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8309 Return 1 on success, 0 on a failure. */
8310
252b5132 8311static int
e3bb37b5 8312i386_index_check (const char *operand_string)
252b5132 8313{
fc0763e6 8314 const char *kind = "base/index";
be05d201
L		 8315 enum flag_code addr_mode;
8316
8317 if (i.prefix[ADDR_PREFIX])
8318 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8319 else
8320 {
8321 addr_mode = flag_code;
8322
24eab124 8323#if INFER_ADDR_PREFIX
be05d201
L		 8324 if (i.mem_operands == 0)
8325 {
8326 /* Infer address prefix from the first memory operand. */
8327 const reg_entry *addr_reg = i.base_reg;
8328
8329 if (addr_reg == NULL)
8330 addr_reg = i.index_reg;
eecb386c 8331
be05d201
L		 8332 if (addr_reg)
8333 {
8334 if (addr_reg->reg_num == RegEip
8335 || addr_reg->reg_num == RegEiz
8336 || addr_reg->reg_type.bitfield.reg32)
8337 addr_mode = CODE_32BIT;
8338 else if (flag_code != CODE_64BIT
8339 && addr_reg->reg_type.bitfield.reg16)
8340 addr_mode = CODE_16BIT;
8341
8342 if (addr_mode != flag_code)
8343 {
8344 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8345 i.prefixes += 1;
8346 /* Change the size of any displacement too. At most one
8347 of Disp16 or Disp32 is set.
8348 FIXME. There doesn't seem to be any real need for
8349 separate Disp16 and Disp32 flags. The same goes for
8350 Imm16 and Imm32. Removing them would probably clean
8351 up the code quite a lot. */
8352 if (flag_code != CODE_64BIT
8353 && (i.types[this_operand].bitfield.disp16
8354 || i.types[this_operand].bitfield.disp32))
8355 i.types[this_operand]
8356 = operand_type_xor (i.types[this_operand], disp16_32);
8357 }
8358 }
8359 }
24eab124 8360#endif
be05d201
L		 8361 }
8362
fc0763e6
JB		 8363 if (current_templates->start->opcode_modifier.isstring
8364 && !current_templates->start->opcode_modifier.immext
8365 && (current_templates->end[-1].opcode_modifier.isstring
8366 || i.mem_operands))
8367 {
8368 /* Memory operands of string insns are special in that they only allow
8369 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8370 const reg_entry *expected_reg;
8371 static const char *di_si[][2] =
8372 {
8373 { "esi", "edi" },
8374 { "si", "di" },
8375 { "rsi", "rdi" }
8376 };
8377 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8378
8379 kind = "string address";
8380
8381 if (current_templates->start->opcode_modifier.w)
8382 {
8383 i386_operand_type type = current_templates->end[-1].operand_types[0];
8384
8385 if (!type.bitfield.baseindex
8386 || ((!i.mem_operands != !intel_syntax)
8387 && current_templates->end[-1].operand_types[1]
8388 .bitfield.baseindex))
8389 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8390 expected_reg = hash_find (reg_hash,
8391 di_si[addr_mode][type.bitfield.esseg]);
8392
fc0763e6
JB		 8393 }
8394 else
be05d201 8395 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8396
be05d201
L		 8397 if (i.base_reg != expected_reg
8398 || i.index_reg
fc0763e6 8399 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8400 {
be05d201
L		 8401 /* The second memory operand must have the same size as
8402 the first one. */
8403 if (i.mem_operands
8404 && i.base_reg
8405 && !((addr_mode == CODE_64BIT
8406 && i.base_reg->reg_type.bitfield.reg64)
8407 || (addr_mode == CODE_32BIT
8408 ? i.base_reg->reg_type.bitfield.reg32
8409 : i.base_reg->reg_type.bitfield.reg16)))
8410 goto bad_address;
8411
fc0763e6
JB		 8412 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8413 operand_string,
8414 intel_syntax ? '[' : '(',
8415 register_prefix,
be05d201 8416 expected_reg->reg_name,
fc0763e6 8417 intel_syntax ? ']' : ')');
be05d201 8418 return 1;
fc0763e6 8419 }
be05d201
L		 8420 else
8421 return 1;
8422
8423bad_address:
8424 as_bad (_("`%s' is not a valid %s expression"),
8425 operand_string, kind);
8426 return 0;
3e73aa7c
JH		 8427 }
8428 else
8429 {
be05d201
L		 8430 if (addr_mode != CODE_16BIT)
8431 {
8432 /* 32-bit/64-bit checks. */
8433 if ((i.base_reg
8434 && (addr_mode == CODE_64BIT
8435 ? !i.base_reg->reg_type.bitfield.reg64
8436 : !i.base_reg->reg_type.bitfield.reg32)
8437 && (i.index_reg
8438 || (i.base_reg->reg_num
8439 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8440 || (i.index_reg
8441 && !i.index_reg->reg_type.bitfield.regxmm
8442 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8443 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8444 && ((addr_mode == CODE_64BIT
8445 ? !(i.index_reg->reg_type.bitfield.reg64
8446 || i.index_reg->reg_num == RegRiz)
8447 : !(i.index_reg->reg_type.bitfield.reg32
8448 || i.index_reg->reg_num == RegEiz))
8449 || !i.index_reg->reg_type.bitfield.baseindex)))
8450 goto bad_address;
8451 }
8452 else
3e73aa7c 8453 {
be05d201 8454 /* 16-bit checks. */
3e73aa7c 8455 if ((i.base_reg
40fb9820
L		 8456 && (!i.base_reg->reg_type.bitfield.reg16
8457 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8458 || (i.index_reg
40fb9820
L		 8459 && (!i.index_reg->reg_type.bitfield.reg16
8460 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8461 || !(i.base_reg
8462 && i.base_reg->reg_num < 6
8463 && i.index_reg->reg_num >= 6
8464 && i.log2_scale_factor == 0))))
be05d201 8465 goto bad_address;
3e73aa7c
JH		 8466 }
8467 }
be05d201 8468 return 1;
24eab124 8469}
252b5132 8470
43234a1e
L		 8471/* Handle vector immediates. */
8472
8473static int
8474RC_SAE_immediate (const char *imm_start)
8475{
8476 unsigned int match_found, j;
8477 const char *pstr = imm_start;
8478 expressionS *exp;
8479
8480 if (*pstr != '{')
8481 return 0;
8482
8483 pstr++;
8484 match_found = 0;
8485 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8486 {
8487 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8488 {
8489 if (!i.rounding)
8490 {
8491 rc_op.type = RC_NamesTable[j].type;
8492 rc_op.operand = this_operand;
8493 i.rounding = &rc_op;
8494 }
8495 else
8496 {
8497 as_bad (_("duplicated `%s'"), imm_start);
8498 return 0;
8499 }
8500 pstr += RC_NamesTable[j].len;
8501 match_found = 1;
8502 break;
8503 }
8504 }
8505 if (!match_found)
8506 return 0;
8507
8508 if (*pstr++ != '}')
8509 {
8510 as_bad (_("Missing '}': '%s'"), imm_start);
8511 return 0;
8512 }
8513 /* RC/SAE immediate string should contain nothing more. */;
8514 if (*pstr != 0)
8515 {
8516 as_bad (_("Junk after '}': '%s'"), imm_start);
8517 return 0;
8518 }
8519
8520 exp = &im_expressions[i.imm_operands++];
8521 i.op[this_operand].imms = exp;
8522
8523 exp->X_op = O_constant;
8524 exp->X_add_number = 0;
8525 exp->X_add_symbol = (symbolS *) 0;
8526 exp->X_op_symbol = (symbolS *) 0;
8527
8528 i.types[this_operand].bitfield.imm8 = 1;
8529 return 1;
8530}
8531
fc0763e6 8532/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8533 on error. */
252b5132 8534
252b5132 8535static int
a7619375 8536i386_att_operand (char *operand_string)
252b5132 8537{
af6bdddf
AM		 8538 const reg_entry *r;
8539 char *end_op;
24eab124 8540 char *op_string = operand_string;
252b5132 8541
24eab124 8542 if (is_space_char (*op_string))
252b5132
RH		 8543 ++op_string;
8544
24eab124 8545 /* We check for an absolute prefix (differentiating,
47926f60 8546 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8547 if (*op_string == ABSOLUTE_PREFIX)
8548 {
8549 ++op_string;
8550 if (is_space_char (*op_string))
8551 ++op_string;
40fb9820 8552 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8553 }
252b5132 8554
47926f60 8555 /* Check if operand is a register. */
4d1bb795 8556 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8557 {
40fb9820
L		 8558 i386_operand_type temp;
8559
24eab124
AM		 8560 /* Check for a segment override by searching for ':' after a
8561 segment register. */
8562 op_string = end_op;
8563 if (is_space_char (*op_string))
8564 ++op_string;
40fb9820
L		 8565 if (*op_string == ':'
8566 && (r->reg_type.bitfield.sreg2
8567 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8568 {
8569 switch (r->reg_num)
8570 {
8571 case 0:
8572 i.seg[i.mem_operands] = &es;
8573 break;
8574 case 1:
8575 i.seg[i.mem_operands] = &cs;
8576 break;
8577 case 2:
8578 i.seg[i.mem_operands] = &ss;
8579 break;
8580 case 3:
8581 i.seg[i.mem_operands] = &ds;
8582 break;
8583 case 4:
8584 i.seg[i.mem_operands] = &fs;
8585 break;
8586 case 5:
8587 i.seg[i.mem_operands] = &gs;
8588 break;
8589 }
252b5132 8590
24eab124 8591 /* Skip the ':' and whitespace. */
252b5132
RH		 8592 ++op_string;
8593 if (is_space_char (*op_string))
24eab124 8594 ++op_string;
252b5132 8595
24eab124
AM		 8596 if (!is_digit_char (*op_string)
8597 && !is_identifier_char (*op_string)
8598 && *op_string != '('
8599 && *op_string != ABSOLUTE_PREFIX)
8600 {
8601 as_bad (_("bad memory operand `%s'"), op_string);
8602 return 0;
8603 }
47926f60 8604 /* Handle case of %es:*foo. */
24eab124
AM		 8605 if (*op_string == ABSOLUTE_PREFIX)
8606 {
8607 ++op_string;
8608 if (is_space_char (*op_string))
8609 ++op_string;
40fb9820 8610 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8611 }
8612 goto do_memory_reference;
8613 }
43234a1e
L		 8614
8615 /* Handle vector operations. */
8616 if (*op_string == '{')
8617 {
8618 op_string = check_VecOperations (op_string, NULL);
8619 if (op_string == NULL)
8620 return 0;
8621 }
8622
24eab124
AM		 8623 if (*op_string)
8624 {
d0b47220 8625 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8626 return 0;
8627 }
40fb9820
L		 8628 temp = r->reg_type;
8629 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8630 i.types[this_operand] = operand_type_or (i.types[this_operand],
8631 temp);
7d5e4556 8632 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8633 i.op[this_operand].regs = r;
24eab124
AM		 8634 i.reg_operands++;
8635 }
af6bdddf
AM		 8636 else if (*op_string == REGISTER_PREFIX)
8637 {
8638 as_bad (_("bad register name `%s'"), op_string);
8639 return 0;
8640 }
24eab124 8641 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8642 {
24eab124 8643 ++op_string;
40fb9820 8644 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8645 {
d0b47220 8646 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8647 return 0;
8648 }
8649 if (!i386_immediate (op_string))
8650 return 0;
8651 }
43234a1e
L		 8652 else if (RC_SAE_immediate (operand_string))
8653 {
8654 /* If it is a RC or SAE immediate, do nothing. */
8655 ;
8656 }
24eab124
AM		 8657 else if (is_digit_char (*op_string)
8658 || is_identifier_char (*op_string)
e5cb08ac 8659 || *op_string == '(')
24eab124 8660 {
47926f60 8661 /* This is a memory reference of some sort. */
af6bdddf 8662 char *base_string;
252b5132 8663
47926f60 8664 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8665 char *displacement_string_start;
8666 char *displacement_string_end;
43234a1e 8667 char *vop_start;
252b5132 8668
24eab124 8669 do_memory_reference:
24eab124 8670 if ((i.mem_operands == 1
40fb9820 8671 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8672 || i.mem_operands == 2)
8673 {
8674 as_bad (_("too many memory references for `%s'"),
8675 current_templates->start->name);
8676 return 0;
8677 }
252b5132 8678
24eab124
AM		 8679 /* Check for base index form. We detect the base index form by
8680 looking for an ')' at the end of the operand, searching
8681 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8682 after the '('. */
af6bdddf 8683 base_string = op_string + strlen (op_string);
c3332e24 8684
43234a1e
L		 8685 /* Handle vector operations. */
8686 vop_start = strchr (op_string, '{');
8687 if (vop_start && vop_start < base_string)
8688 {
8689 if (check_VecOperations (vop_start, base_string) == NULL)
8690 return 0;
8691 base_string = vop_start;
8692 }
8693
af6bdddf
AM		 8694 --base_string;
8695 if (is_space_char (*base_string))
8696 --base_string;
252b5132 8697
47926f60 8698 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8699 displacement_string_start = op_string;
8700 displacement_string_end = base_string + 1;
252b5132 8701
24eab124
AM		 8702 if (*base_string == ')')
8703 {
af6bdddf 8704 char *temp_string;
24eab124
AM		 8705 unsigned int parens_balanced = 1;
8706 /* We've already checked that the number of left & right ()'s are
47926f60 8707 equal, so this loop will not be infinite. */
24eab124
AM		 8708 do
8709 {
8710 base_string--;
8711 if (*base_string == ')')
8712 parens_balanced++;
8713 if (*base_string == '(')
8714 parens_balanced--;
8715 }
8716 while (parens_balanced);
c3332e24 8717
af6bdddf 8718 temp_string = base_string;
c3332e24 8719
24eab124 8720 /* Skip past '(' and whitespace. */
252b5132
RH		 8721 ++base_string;
8722 if (is_space_char (*base_string))
24eab124 8723 ++base_string;
252b5132 8724
af6bdddf 8725 if (*base_string == ','
4eed87de
AM		 8726 || ((i.base_reg = parse_register (base_string, &end_op))
8727 != NULL))
252b5132 8728 {
af6bdddf 8729 displacement_string_end = temp_string;
252b5132 8730
40fb9820 8731 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8732
af6bdddf 8733 if (i.base_reg)
24eab124 8734 {
24eab124
AM		 8735 base_string = end_op;
8736 if (is_space_char (*base_string))
8737 ++base_string;
af6bdddf
AM		 8738 }
8739
8740 /* There may be an index reg or scale factor here. */
8741 if (*base_string == ',')
8742 {
8743 ++base_string;
8744 if (is_space_char (*base_string))
8745 ++base_string;
8746
4eed87de
AM		 8747 if ((i.index_reg = parse_register (base_string, &end_op))
8748 != NULL)
24eab124 8749 {
af6bdddf 8750 base_string = end_op;
24eab124
AM		 8751 if (is_space_char (*base_string))
8752 ++base_string;
af6bdddf
AM		 8753 if (*base_string == ',')
8754 {
8755 ++base_string;
8756 if (is_space_char (*base_string))
8757 ++base_string;
8758 }
e5cb08ac 8759 else if (*base_string != ')')
af6bdddf 8760 {
4eed87de
AM		 8761 as_bad (_("expecting `,' or `)' "
8762 "after index register in `%s'"),
af6bdddf
AM		 8763 operand_string);
8764 return 0;
8765 }
24eab124 8766 }
af6bdddf 8767 else if (*base_string == REGISTER_PREFIX)
24eab124 8768 {
f76bf5e0
L		 8769 end_op = strchr (base_string, ',');
8770 if (end_op)
8771 *end_op = '\0';
af6bdddf 8772 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8773 return 0;
8774 }
252b5132 8775
47926f60 8776 /* Check for scale factor. */
551c1ca1 8777 if (*base_string != ')')
af6bdddf 8778 {
551c1ca1
AM		 8779 char *end_scale = i386_scale (base_string);
8780
8781 if (!end_scale)
af6bdddf 8782 return 0;
24eab124 8783
551c1ca1 8784 base_string = end_scale;
af6bdddf
AM		 8785 if (is_space_char (*base_string))
8786 ++base_string;
8787 if (*base_string != ')')
8788 {
4eed87de
AM		 8789 as_bad (_("expecting `)' "
8790 "after scale factor in `%s'"),
af6bdddf
AM		 8791 operand_string);
8792 return 0;
8793 }
8794 }
8795 else if (!i.index_reg)
24eab124 8796 {
4eed87de
AM		 8797 as_bad (_("expecting index register or scale factor "
8798 "after `,'; got '%c'"),
af6bdddf 8799 *base_string);
24eab124
AM		 8800 return 0;
8801 }
8802 }
af6bdddf 8803 else if (*base_string != ')')
24eab124 8804 {
4eed87de
AM		 8805 as_bad (_("expecting `,' or `)' "
8806 "after base register in `%s'"),
af6bdddf 8807 operand_string);
24eab124
AM		 8808 return 0;
8809 }
c3332e24 8810 }
af6bdddf 8811 else if (*base_string == REGISTER_PREFIX)
c3332e24 8812 {
f76bf5e0
L		 8813 end_op = strchr (base_string, ',');
8814 if (end_op)
8815 *end_op = '\0';
af6bdddf 8816 as_bad (_("bad register name `%s'"), base_string);
24eab124 8817 return 0;
c3332e24 8818 }
24eab124
AM		 8819 }
8820
8821 /* If there's an expression beginning the operand, parse it,
8822 assuming displacement_string_start and
8823 displacement_string_end are meaningful. */
8824 if (displacement_string_start != displacement_string_end)
8825 {
8826 if (!i386_displacement (displacement_string_start,
8827 displacement_string_end))
8828 return 0;
8829 }
8830
8831 /* Special case for (%dx) while doing input/output op. */
8832 if (i.base_reg
0dfbf9d7
L		 8833 && operand_type_equal (&i.base_reg->reg_type,
8834 &reg16_inoutportreg)
24eab124
AM		 8835 && i.index_reg == 0
8836 && i.log2_scale_factor == 0
8837 && i.seg[i.mem_operands] == 0
40fb9820 8838 && !operand_type_check (i.types[this_operand], disp))
24eab124 8839 {
65da13b5 8840 i.types[this_operand] = inoutportreg;
24eab124
AM		 8841 return 1;
8842 }
8843
eecb386c
AM		 8844 if (i386_index_check (operand_string) == 0)
8845 return 0;
5c07affc 8846 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 8847 i.mem_operands++;
8848 }
8849 else
ce8a8b2f
AM		 8850 {
8851 /* It's not a memory operand; argh! */
24eab124
AM		 8852 as_bad (_("invalid char %s beginning operand %d `%s'"),
8853 output_invalid (*op_string),
8854 this_operand + 1,
8855 op_string);
8856 return 0;
8857 }
47926f60 8858 return 1; /* Normal return. */
252b5132
RH		 8859}
8860\f
fa94de6b
RM		 8861/* Calculate the maximum variable size (i.e., excluding fr_fix)
8862 that an rs_machine_dependent frag may reach. */
8863
8864unsigned int
8865i386_frag_max_var (fragS *frag)
8866{
8867 /* The only relaxable frags are for jumps.
8868 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8869 gas_assert (frag->fr_type == rs_machine_dependent);
8870 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8871}
8872
ee7fcc42
AM		 8873/* md_estimate_size_before_relax()
8874
8875 Called just before relax() for rs_machine_dependent frags. The x86
8876 assembler uses these frags to handle variable size jump
8877 instructions.
8878
8879 Any symbol that is now undefined will not become defined.
8880 Return the correct fr_subtype in the frag.
8881 Return the initial "guess for variable size of frag" to caller.
8882 The guess is actually the growth beyond the fixed part. Whatever
8883 we do to grow the fixed or variable part contributes to our
8884 returned value. */
8885
252b5132 8886int
7016a5d5 8887md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 8888{
252b5132 8889 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 8890 check for un-relaxable symbols. On an ELF system, we can't relax
8891 an externally visible symbol, because it may be overridden by a
8892 shared library. */
8893 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 8894#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8895 || (IS_ELF
31312f95 8896 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 8897 || S_IS_WEAK (fragP->fr_symbol)
8898 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
8899 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 8900#endif
8901#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 8902 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 8903 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 8904#endif
8905 )
252b5132 8906 {
b98ef147
AM		 8907 /* Symbol is undefined in this segment, or we need to keep a
8908 reloc so that weak symbols can be overridden. */
8909 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 8910 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 8911 unsigned char *opcode;
8912 int old_fr_fix;
f6af82bd 8913
ee7fcc42 8914 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 8915 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 8916 else if (size == 2)
f6af82bd
AM		 8917 reloc_type = BFD_RELOC_16_PCREL;
8918 else
8919 reloc_type = BFD_RELOC_32_PCREL;
252b5132 8920
ee7fcc42
AM		 8921 old_fr_fix = fragP->fr_fix;
8922 opcode = (unsigned char *) fragP->fr_opcode;
8923
fddf5b5b 8924 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 8925 {
fddf5b5b
AM		 8926 case UNCOND_JUMP:
8927 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 8928 opcode[0] = 0xe9;
252b5132 8929 fragP->fr_fix += size;
062cd5e7
AS		 8930 fix_new (fragP, old_fr_fix, size,
8931 fragP->fr_symbol,
8932 fragP->fr_offset, 1,
8933 reloc_type);
252b5132
RH		 8934 break;
8935
fddf5b5b 8936 case COND_JUMP86:
412167cb
AM		 8937 if (size == 2
8938 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 8939 {
8940 /* Negate the condition, and branch past an
8941 unconditional jump. */
8942 opcode[0] ^= 1;
8943 opcode[1] = 3;
8944 /* Insert an unconditional jump. */
8945 opcode[2] = 0xe9;
8946 /* We added two extra opcode bytes, and have a two byte
8947 offset. */
8948 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 8949 fix_new (fragP, old_fr_fix + 2, 2,
8950 fragP->fr_symbol,
8951 fragP->fr_offset, 1,
8952 reloc_type);
fddf5b5b
AM		 8953 break;
8954 }
8955 /* Fall through. */
8956
8957 case COND_JUMP:
412167cb
AM		 8958 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
8959 {
3e02c1cc
AM		 8960 fixS *fixP;
8961
412167cb 8962 fragP->fr_fix += 1;
3e02c1cc
AM		 8963 fixP = fix_new (fragP, old_fr_fix, 1,
8964 fragP->fr_symbol,
8965 fragP->fr_offset, 1,
8966 BFD_RELOC_8_PCREL);
8967 fixP->fx_signed = 1;
412167cb
AM		 8968 break;
8969 }
93c2a809 8970
24eab124 8971 /* This changes the byte-displacement jump 0x7N
fddf5b5b 8972 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 8973 opcode[1] = opcode[0] + 0x10;
f6af82bd 8974 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 8975 /* We've added an opcode byte. */
8976 fragP->fr_fix += 1 + size;
062cd5e7
AS		 8977 fix_new (fragP, old_fr_fix + 1, size,
8978 fragP->fr_symbol,
8979 fragP->fr_offset, 1,
8980 reloc_type);
252b5132 8981 break;
fddf5b5b
AM		 8982
8983 default:
8984 BAD_CASE (fragP->fr_subtype);
8985 break;
252b5132
RH		 8986 }
8987 frag_wane (fragP);
ee7fcc42 8988 return fragP->fr_fix - old_fr_fix;
252b5132 8989 }
93c2a809 8990
93c2a809
AM		 8991 /* Guess size depending on current relax state. Initially the relax
8992 state will correspond to a short jump and we return 1, because
8993 the variable part of the frag (the branch offset) is one byte
8994 long. However, we can relax a section more than once and in that
8995 case we must either set fr_subtype back to the unrelaxed state,
8996 or return the value for the appropriate branch. */
8997 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 8998}
8999
47926f60
KH		 9000/* Called after relax() is finished.
9001
9002 In: Address of frag.
9003 fr_type == rs_machine_dependent.
9004 fr_subtype is what the address relaxed to.
9005
9006 Out: Any fixSs and constants are set up.
9007 Caller will turn frag into a ".space 0". */
9008
252b5132 9009void
7016a5d5
TG		 9010md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9011 fragS *fragP)
252b5132 9012{
29b0f896 9013 unsigned char *opcode;
252b5132 9014 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9015 offsetT target_address;
9016 offsetT opcode_address;
252b5132 9017 unsigned int extension = 0;
847f7ad4 9018 offsetT displacement_from_opcode_start;
252b5132
RH		 9019
9020 opcode = (unsigned char *) fragP->fr_opcode;
9021
47926f60 9022 /* Address we want to reach in file space. */
252b5132 9023 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9024
47926f60 9025 /* Address opcode resides at in file space. */
252b5132
RH		 9026 opcode_address = fragP->fr_address + fragP->fr_fix;
9027
47926f60 9028 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9029 displacement_from_opcode_start = target_address - opcode_address;
9030
fddf5b5b 9031 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9032 {
47926f60
KH		 9033 /* Don't have to change opcode. */
9034 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9035 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9036 }
9037 else
9038 {
9039 if (no_cond_jump_promotion
9040 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9041 as_warn_where (fragP->fr_file, fragP->fr_line,
9042 _("long jump required"));
252b5132 9043
fddf5b5b
AM		 9044 switch (fragP->fr_subtype)
9045 {
9046 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9047 extension = 4; /* 1 opcode + 4 displacement */
9048 opcode[0] = 0xe9;
9049 where_to_put_displacement = &opcode[1];
9050 break;
252b5132 9051
fddf5b5b
AM		 9052 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9053 extension = 2; /* 1 opcode + 2 displacement */
9054 opcode[0] = 0xe9;
9055 where_to_put_displacement = &opcode[1];
9056 break;
252b5132 9057
fddf5b5b
AM		 9058 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9059 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9060 extension = 5; /* 2 opcode + 4 displacement */
9061 opcode[1] = opcode[0] + 0x10;
9062 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9063 where_to_put_displacement = &opcode[2];
9064 break;
252b5132 9065
fddf5b5b
AM		 9066 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9067 extension = 3; /* 2 opcode + 2 displacement */
9068 opcode[1] = opcode[0] + 0x10;
9069 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9070 where_to_put_displacement = &opcode[2];
9071 break;
252b5132 9072
fddf5b5b
AM		 9073 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9074 extension = 4;
9075 opcode[0] ^= 1;
9076 opcode[1] = 3;
9077 opcode[2] = 0xe9;
9078 where_to_put_displacement = &opcode[3];
9079 break;
9080
9081 default:
9082 BAD_CASE (fragP->fr_subtype);
9083 break;
9084 }
252b5132 9085 }
fddf5b5b 9086
7b81dfbb
AJ		 9087 /* If size if less then four we are sure that the operand fits,
9088 but if it's 4, then it could be that the displacement is larger
9089 then -/+ 2GB. */
9090 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9091 && object_64bit
9092 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9093 + ((addressT) 1 << 31))
9094 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9095 {
9096 as_bad_where (fragP->fr_file, fragP->fr_line,
9097 _("jump target out of range"));
9098 /* Make us emit 0. */
9099 displacement_from_opcode_start = extension;
9100 }
47926f60 9101 /* Now put displacement after opcode. */
252b5132
RH		 9102 md_number_to_chars ((char *) where_to_put_displacement,
9103 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9104 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9105 fragP->fr_fix += extension;
9106}
9107\f
7016a5d5 9108/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9109 by our caller that we have all the info we need to fix it up.
9110
7016a5d5
TG		 9111 Parameter valP is the pointer to the value of the bits.
9112
252b5132
RH		 9113 On the 386, immediates, displacements, and data pointers are all in
9114 the same (little-endian) format, so we don't need to care about which
9115 we are handling. */
9116
94f592af 9117void
7016a5d5 9118md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9119{
94f592af 9120 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9121 valueT value = *valP;
252b5132 9122
f86103b7 9123#if !defined (TE_Mach)
93382f6d
AM		 9124 if (fixP->fx_pcrel)
9125 {
9126 switch (fixP->fx_r_type)
9127 {
5865bb77
ILT		 9128 default:
9129 break;
9130
d6ab8113
JB		 9131 case BFD_RELOC_64:
9132 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9133 break;
93382f6d 9134 case BFD_RELOC_32:
ae8887b5 9135 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9136 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9137 break;
9138 case BFD_RELOC_16:
9139 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9140 break;
9141 case BFD_RELOC_8:
9142 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9143 break;
9144 }
9145 }
252b5132 9146
a161fe53 9147 if (fixP->fx_addsy != NULL
31312f95 9148 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9149 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9150 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9151 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9152 && !use_rela_relocations)
252b5132 9153 {
31312f95
AM		 9154 /* This is a hack. There should be a better way to handle this.
9155 This covers for the fact that bfd_install_relocation will
9156 subtract the current location (for partial_inplace, PC relative
9157 relocations); see more below. */
252b5132 9158#ifndef OBJ_AOUT
718ddfc0 9159 if (IS_ELF
252b5132
RH		 9160#ifdef TE_PE
9161 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9162#endif
9163 )
9164 value += fixP->fx_where + fixP->fx_frag->fr_address;
9165#endif
9166#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9167 if (IS_ELF)
252b5132 9168 {
6539b54b 9169 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9170
6539b54b 9171 if ((sym_seg == seg
2f66722d 9172 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9173 && sym_seg != absolute_section))
af65af87 9174 && !generic_force_reloc (fixP))
2f66722d
AM		 9175 {
9176 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9177 bfd_install_relocation subtracts them out again. I think
9178 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9179 it. FIXME. */
9180 value += fixP->fx_where + fixP->fx_frag->fr_address;
9181 }
252b5132
RH		 9182 }
9183#endif
9184#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9185 /* For some reason, the PE format does not store a
9186 section address offset for a PC relative symbol. */
9187 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9188 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9189 value += md_pcrel_from (fixP);
9190#endif
9191 }
fbeb56a4 9192#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9193 if (fixP->fx_addsy != NULL
9194 && S_IS_WEAK (fixP->fx_addsy)
9195 /* PR 16858: Do not modify weak function references. */
9196 && ! fixP->fx_pcrel)
fbeb56a4 9197 {
296a8689
NC		 9198#if !defined (TE_PEP)
9199 /* For x86 PE weak function symbols are neither PC-relative
9200 nor do they set S_IS_FUNCTION. So the only reliable way
9201 to detect them is to check the flags of their containing
9202 section. */
9203 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9204 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9205 ;
9206 else
9207#endif
fbeb56a4
DK		 9208 value -= S_GET_VALUE (fixP->fx_addsy);
9209 }
9210#endif
252b5132
RH		 9211
9212 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9213 and we must not disappoint it. */
252b5132 9214#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9215 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9216 switch (fixP->fx_r_type)
9217 {
9218 case BFD_RELOC_386_PLT32:
3e73aa7c 9219 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9220 /* Make the jump instruction point to the address of the operand. At
9221 runtime we merely add the offset to the actual PLT entry. */
9222 value = -4;
9223 break;
31312f95 9224
13ae64f3
JJ		 9225 case BFD_RELOC_386_TLS_GD:
9226 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9227 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9228 case BFD_RELOC_386_TLS_IE:
9229 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9230 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9231 case BFD_RELOC_X86_64_TLSGD:
9232 case BFD_RELOC_X86_64_TLSLD:
9233 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9234 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9235 value = 0; /* Fully resolved at runtime. No addend. */
9236 /* Fallthrough */
9237 case BFD_RELOC_386_TLS_LE:
9238 case BFD_RELOC_386_TLS_LDO_32:
9239 case BFD_RELOC_386_TLS_LE_32:
9240 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9241 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9242 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9243 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9244 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9245 break;
9246
67a4f2b7
AO		 9247 case BFD_RELOC_386_TLS_DESC_CALL:
9248 case BFD_RELOC_X86_64_TLSDESC_CALL:
9249 value = 0; /* Fully resolved at runtime. No addend. */
9250 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9251 fixP->fx_done = 0;
9252 return;
9253
00f7efb6
JJ		 9254 case BFD_RELOC_386_GOT32:
9255 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 9256 value = 0; /* Fully resolved at runtime. No addend. */
9257 break;
47926f60
KH		 9258
9259 case BFD_RELOC_VTABLE_INHERIT:
9260 case BFD_RELOC_VTABLE_ENTRY:
9261 fixP->fx_done = 0;
94f592af 9262 return;
47926f60
KH		 9263
9264 default:
9265 break;
9266 }
9267#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9268 *valP = value;
f86103b7 9269#endif /* !defined (TE_Mach) */
3e73aa7c 9270
3e73aa7c 9271 /* Are we finished with this relocation now? */
c6682705 9272 if (fixP->fx_addsy == NULL)
3e73aa7c 9273 fixP->fx_done = 1;
fbeb56a4
DK		 9274#if defined (OBJ_COFF) && defined (TE_PE)
9275 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9276 {
9277 fixP->fx_done = 0;
9278 /* Remember value for tc_gen_reloc. */
9279 fixP->fx_addnumber = value;
9280 /* Clear out the frag for now. */
9281 value = 0;
9282 }
9283#endif
3e73aa7c
JH		 9284 else if (use_rela_relocations)
9285 {
9286 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9287 /* Remember value for tc_gen_reloc. */
9288 fixP->fx_addnumber = value;
3e73aa7c
JH		 9289 value = 0;
9290 }
f86103b7 9291
94f592af 9292 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9293}
252b5132 9294\f
252b5132 9295char *
499ac353 9296md_atof (int type, char *litP, int *sizeP)
252b5132 9297{
499ac353
NC		 9298 /* This outputs the LITTLENUMs in REVERSE order;
9299 in accord with the bigendian 386. */
9300 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9301}
9302\f
2d545b82 9303static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9304
252b5132 9305static char *
e3bb37b5 9306output_invalid (int c)
252b5132 9307{
3882b010 9308 if (ISPRINT (c))
f9f21a03
L		 9309 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9310 "'%c'", c);
252b5132 9311 else
f9f21a03 9312 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9313 "(0x%x)", (unsigned char) c);
252b5132
RH		 9314 return output_invalid_buf;
9315}
9316
af6bdddf 9317/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9318
9319static const reg_entry *
4d1bb795 9320parse_real_register (char *reg_string, char **end_op)
252b5132 9321{
af6bdddf
AM		 9322 char *s = reg_string;
9323 char *p;
252b5132
RH		 9324 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9325 const reg_entry *r;
9326
9327 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9328 if (*s == REGISTER_PREFIX)
9329 ++s;
9330
9331 if (is_space_char (*s))
9332 ++s;
9333
9334 p = reg_name_given;
af6bdddf 9335 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9336 {
9337 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9338 return (const reg_entry *) NULL;
9339 s++;
252b5132
RH		 9340 }
9341
6588847e
DN		 9342 /* For naked regs, make sure that we are not dealing with an identifier.
9343 This prevents confusing an identifier like `eax_var' with register
9344 `eax'. */
9345 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9346 return (const reg_entry *) NULL;
9347
af6bdddf 9348 *end_op = s;
252b5132
RH		 9349
9350 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9351
5f47d35b 9352 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9353 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9354 {
5f47d35b
AM		 9355 if (is_space_char (*s))
9356 ++s;
9357 if (*s == '(')
9358 {
af6bdddf 9359 ++s;
5f47d35b
AM		 9360 if (is_space_char (*s))
9361 ++s;
9362 if (*s >= '0' && *s <= '7')
9363 {
db557034 9364 int fpr = *s - '0';
af6bdddf 9365 ++s;
5f47d35b
AM		 9366 if (is_space_char (*s))
9367 ++s;
9368 if (*s == ')')
9369 {
9370 *end_op = s + 1;
1e9cc1c2 9371 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9372 know (r);
9373 return r + fpr;
5f47d35b 9374 }
5f47d35b 9375 }
47926f60 9376 /* We have "%st(" then garbage. */
5f47d35b
AM		 9377 return (const reg_entry *) NULL;
9378 }
9379 }
9380
a60de03c
JB		 9381 if (r == NULL || allow_pseudo_reg)
9382 return r;
9383
0dfbf9d7 9384 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9385 return (const reg_entry *) NULL;
9386
192dc9c6
JB		 9387 if ((r->reg_type.bitfield.reg32
9388 || r->reg_type.bitfield.sreg3
9389 || r->reg_type.bitfield.control
9390 || r->reg_type.bitfield.debug
9391 || r->reg_type.bitfield.test)
9392 && !cpu_arch_flags.bitfield.cpui386)
9393 return (const reg_entry *) NULL;
9394
309d3373
JB		 9395 if (r->reg_type.bitfield.floatreg
9396 && !cpu_arch_flags.bitfield.cpu8087
9397 && !cpu_arch_flags.bitfield.cpu287
9398 && !cpu_arch_flags.bitfield.cpu387)
9399 return (const reg_entry *) NULL;
9400
192dc9c6
JB		 9401 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9402 return (const reg_entry *) NULL;
9403
9404 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9405 return (const reg_entry *) NULL;
9406
40f12533
L		 9407 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9408 return (const reg_entry *) NULL;
9409
43234a1e
L		 9410 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9411 && !cpu_arch_flags.bitfield.cpuavx512f)
9412 return (const reg_entry *) NULL;
9413
db51cc60 9414 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9415 if (!allow_index_reg
db51cc60
L		 9416 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9417 return (const reg_entry *) NULL;
9418
43234a1e
L		 9419 /* Upper 16 vector register is only available with VREX in 64bit
9420 mode. */
9421 if ((r->reg_flags & RegVRex))
9422 {
9423 if (!cpu_arch_flags.bitfield.cpuvrex
9424 || flag_code != CODE_64BIT)
9425 return (const reg_entry *) NULL;
9426
9427 i.need_vrex = 1;
9428 }
9429
a60de03c
JB		 9430 if (((r->reg_flags & (RegRex64 | RegRex))
9431 || r->reg_type.bitfield.reg64)
40fb9820 9432 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9433 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9434 && flag_code != CODE_64BIT)
20f0a1fc 9435 return (const reg_entry *) NULL;
1ae00879 9436
b7240065
JB		 9437 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9438 return (const reg_entry *) NULL;
9439
252b5132
RH		 9440 return r;
9441}
4d1bb795
JB		 9442
9443/* REG_STRING starts *before* REGISTER_PREFIX. */
9444
9445static const reg_entry *
9446parse_register (char *reg_string, char **end_op)
9447{
9448 const reg_entry *r;
9449
9450 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9451 r = parse_real_register (reg_string, end_op);
9452 else
9453 r = NULL;
9454 if (!r)
9455 {
9456 char *save = input_line_pointer;
9457 char c;
9458 symbolS *symbolP;
9459
9460 input_line_pointer = reg_string;
9461 c = get_symbol_end ();
9462 symbolP = symbol_find (reg_string);
9463 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9464 {
9465 const expressionS *e = symbol_get_value_expression (symbolP);
9466
0398aac5 9467 know (e->X_op == O_register);
4eed87de 9468 know (e->X_add_number >= 0
c3fe08fa 9469 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9470 r = i386_regtab + e->X_add_number;
d3bb6b49
IT		 9471 if ((r->reg_flags & RegVRex))
9472 i.need_vrex = 1;
4d1bb795
JB		 9473 *end_op = input_line_pointer;
9474 }
9475 *input_line_pointer = c;
9476 input_line_pointer = save;
9477 }
9478 return r;
9479}
9480
9481int
9482i386_parse_name (char *name, expressionS *e, char *nextcharP)
9483{
9484 const reg_entry *r;
9485 char *end = input_line_pointer;
9486
9487 *end = *nextcharP;
9488 r = parse_register (name, &input_line_pointer);
9489 if (r && end <= input_line_pointer)
9490 {
9491 *nextcharP = *input_line_pointer;
9492 *input_line_pointer = 0;
9493 e->X_op = O_register;
9494 e->X_add_number = r - i386_regtab;
9495 return 1;
9496 }
9497 input_line_pointer = end;
9498 *end = 0;
ee86248c 9499 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9500}
9501
9502void
9503md_operand (expressionS *e)
9504{
ee86248c
JB		 9505 char *end;
9506 const reg_entry *r;
4d1bb795 9507
ee86248c
JB		 9508 switch (*input_line_pointer)
9509 {
9510 case REGISTER_PREFIX:
9511 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9512 if (r)
9513 {
9514 e->X_op = O_register;
9515 e->X_add_number = r - i386_regtab;
9516 input_line_pointer = end;
9517 }
ee86248c
JB		 9518 break;
9519
9520 case '[':
9c2799c2 9521 gas_assert (intel_syntax);
ee86248c
JB		 9522 end = input_line_pointer++;
9523 expression (e);
9524 if (*input_line_pointer == ']')
9525 {
9526 ++input_line_pointer;
9527 e->X_op_symbol = make_expr_symbol (e);
9528 e->X_add_symbol = NULL;
9529 e->X_add_number = 0;
9530 e->X_op = O_index;
9531 }
9532 else
9533 {
9534 e->X_op = O_absent;
9535 input_line_pointer = end;
9536 }
9537 break;
4d1bb795
JB		 9538 }
9539}
9540
252b5132 9541\f
4cc782b5 9542#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9543const char *md_shortopts = "kVQ:sqn";
252b5132 9544#else
12b55ccc 9545const char *md_shortopts = "qn";
252b5132 9546#endif
6e0b89ee 9547
3e73aa7c 9548#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9549#define OPTION_64 (OPTION_MD_BASE + 1)
9550#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9551#define OPTION_MARCH (OPTION_MD_BASE + 3)
9552#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9553#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9554#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9555#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9556#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9557#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9558#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9559#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9560#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9561#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9562#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9563#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9564#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9565#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9566#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
a5094208 9567#define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9568#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
b3b91714 9569
99ad8390
NC		 9570struct option md_longopts[] =
9571{
3e73aa7c 9572 {"32", no_argument, NULL, OPTION_32},
321098a5 9573#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9574 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9575 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9576#endif
9577#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9578 {"x32", no_argument, NULL, OPTION_X32},
6e0b89ee 9579#endif
b3b91714 9580 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9581 {"march", required_argument, NULL, OPTION_MARCH},
9582 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9583 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9584 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9585 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9586 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9587 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9588 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9589 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9590 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9591 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9592 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9593 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9594 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9595# if defined (TE_PE) || defined (TE_PEP)
9596 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9597#endif
a5094208 9598 {"momit-lock-prefix", required_argument, NULL, OPTION_OMIT_LOCK_PREFIX},
d3d3c6db 9599 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
252b5132
RH		 9600 {NULL, no_argument, NULL, 0}
9601};
9602size_t md_longopts_size = sizeof (md_longopts);
9603
9604int
9103f4f4 9605md_parse_option (int c, char *arg)
252b5132 9606{
91d6fa6a 9607 unsigned int j;
6305a203 9608 char *arch, *next;
9103f4f4 9609
252b5132
RH		 9610 switch (c)
9611 {
12b55ccc
L		 9612 case 'n':
9613 optimize_align_code = 0;
9614 break;
9615
a38cf1db
AM		 9616 case 'q':
9617 quiet_warnings = 1;
252b5132
RH		 9618 break;
9619
9620#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9621 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9622 should be emitted or not. FIXME: Not implemented. */
9623 case 'Q':
252b5132
RH		 9624 break;
9625
9626 /* -V: SVR4 argument to print version ID. */
9627 case 'V':
9628 print_version_id ();
9629 break;
9630
a38cf1db
AM		 9631 /* -k: Ignore for FreeBSD compatibility. */
9632 case 'k':
252b5132 9633 break;
4cc782b5
ILT		 9634
9635 case 's':
9636 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9637 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9638 break;
99ad8390 9639#endif
321098a5 9640#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9641 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9642 case OPTION_64:
9643 {
9644 const char **list, **l;
9645
3e73aa7c
JH		 9646 list = bfd_target_list ();
9647 for (l = list; *l != NULL; l++)
8620418b 9648 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9649 || strcmp (*l, "coff-x86-64") == 0
9650 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9651 || strcmp (*l, "pei-x86-64") == 0
9652 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9653 {
9654 default_arch = "x86_64";
9655 break;
9656 }
3e73aa7c 9657 if (*l == NULL)
2b5d6a91 9658 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9659 free (list);
9660 }
9661 break;
9662#endif
252b5132 9663
351f65ca 9664#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9665 case OPTION_X32:
351f65ca
L		 9666 if (IS_ELF)
9667 {
9668 const char **list, **l;
9669
9670 list = bfd_target_list ();
9671 for (l = list; *l != NULL; l++)
9672 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9673 {
9674 default_arch = "x86_64:32";
9675 break;
9676 }
9677 if (*l == NULL)
2b5d6a91 9678 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9679 free (list);
9680 }
9681 else
9682 as_fatal (_("32bit x86_64 is only supported for ELF"));
9683 break;
9684#endif
9685
6e0b89ee
AM		 9686 case OPTION_32:
9687 default_arch = "i386";
9688 break;
9689
b3b91714
AM		 9690 case OPTION_DIVIDE:
9691#ifdef SVR4_COMMENT_CHARS
9692 {
9693 char *n, *t;
9694 const char *s;
9695
9696 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
9697 t = n;
9698 for (s = i386_comment_chars; *s != '\0'; s++)
9699 if (*s != '/')
9700 *t++ = *s;
9701 *t = '\0';
9702 i386_comment_chars = n;
9703 }
9704#endif
9705 break;
9706
9103f4f4 9707 case OPTION_MARCH:
6305a203
L		 9708 arch = xstrdup (arg);
9709 do
9103f4f4 9710 {
6305a203 9711 if (*arch == '.')
2b5d6a91 9712 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9713 next = strchr (arch, '+');
9714 if (next)
9715 *next++ = '\0';
91d6fa6a 9716 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9717 {
91d6fa6a 9718 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9719 {
6305a203 9720 /* Processor. */
1ded5609
JB		 9721 if (! cpu_arch[j].flags.bitfield.cpui386)
9722 continue;
9723
91d6fa6a 9724 cpu_arch_name = cpu_arch[j].name;
6305a203 9725 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9726 cpu_arch_flags = cpu_arch[j].flags;
9727 cpu_arch_isa = cpu_arch[j].type;
9728 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9729 if (!cpu_arch_tune_set)
9730 {
9731 cpu_arch_tune = cpu_arch_isa;
9732 cpu_arch_tune_flags = cpu_arch_isa_flags;
9733 }
9734 break;
9735 }
91d6fa6a
NC		 9736 else if (*cpu_arch [j].name == '.'
9737 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9738 {
9739 /* ISA entension. */
9740 i386_cpu_flags flags;
309d3373 9741
49021df2 9742 if (!cpu_arch[j].negated)
309d3373 9743 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 9744 cpu_arch[j].flags);
309d3373
JB		 9745 else
9746 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 9747 cpu_arch[j].flags);
0dfbf9d7 9748 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 9749 {
9750 if (cpu_sub_arch_name)
9751 {
9752 char *name = cpu_sub_arch_name;
9753 cpu_sub_arch_name = concat (name,
91d6fa6a 9754 cpu_arch[j].name,
1bf57e9f 9755 (const char *) NULL);
6305a203
L		 9756 free (name);
9757 }
9758 else
91d6fa6a 9759 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 9760 cpu_arch_flags = flags;
a586129e 9761 cpu_arch_isa_flags = flags;
6305a203
L		 9762 }
9763 break;
ccc9c027 9764 }
9103f4f4 9765 }
6305a203 9766
91d6fa6a 9767 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9768 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9769
9770 arch = next;
9103f4f4 9771 }
6305a203 9772 while (next != NULL );
9103f4f4
L		 9773 break;
9774
9775 case OPTION_MTUNE:
9776 if (*arg == '.')
2b5d6a91 9777 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 9778 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9779 {
91d6fa6a 9780 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 9781 {
ccc9c027 9782 cpu_arch_tune_set = 1;
91d6fa6a
NC		 9783 cpu_arch_tune = cpu_arch [j].type;
9784 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 9785 break;
9786 }
9787 }
91d6fa6a 9788 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9789 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 9790 break;
9791
1efbbeb4
L		 9792 case OPTION_MMNEMONIC:
9793 if (strcasecmp (arg, "att") == 0)
9794 intel_mnemonic = 0;
9795 else if (strcasecmp (arg, "intel") == 0)
9796 intel_mnemonic = 1;
9797 else
2b5d6a91 9798 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 9799 break;
9800
9801 case OPTION_MSYNTAX:
9802 if (strcasecmp (arg, "att") == 0)
9803 intel_syntax = 0;
9804 else if (strcasecmp (arg, "intel") == 0)
9805 intel_syntax = 1;
9806 else
2b5d6a91 9807 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 9808 break;
9809
9810 case OPTION_MINDEX_REG:
9811 allow_index_reg = 1;
9812 break;
9813
9814 case OPTION_MNAKED_REG:
9815 allow_naked_reg = 1;
9816 break;
9817
9818 case OPTION_MOLD_GCC:
9819 old_gcc = 1;
1efbbeb4
L		 9820 break;
9821
c0f3af97
L		 9822 case OPTION_MSSE2AVX:
9823 sse2avx = 1;
9824 break;
9825
daf50ae7
L		 9826 case OPTION_MSSE_CHECK:
9827 if (strcasecmp (arg, "error") == 0)
7bab8ab5 9828 sse_check = check_error;
daf50ae7 9829 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 9830 sse_check = check_warning;
daf50ae7 9831 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 9832 sse_check = check_none;
daf50ae7 9833 else
2b5d6a91 9834 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 9835 break;
9836
7bab8ab5
JB		 9837 case OPTION_MOPERAND_CHECK:
9838 if (strcasecmp (arg, "error") == 0)
9839 operand_check = check_error;
9840 else if (strcasecmp (arg, "warning") == 0)
9841 operand_check = check_warning;
9842 else if (strcasecmp (arg, "none") == 0)
9843 operand_check = check_none;
9844 else
9845 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
9846 break;
9847
539f890d
L		 9848 case OPTION_MAVXSCALAR:
9849 if (strcasecmp (arg, "128") == 0)
9850 avxscalar = vex128;
9851 else if (strcasecmp (arg, "256") == 0)
9852 avxscalar = vex256;
9853 else
2b5d6a91 9854 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 9855 break;
9856
7e8b059b
L		 9857 case OPTION_MADD_BND_PREFIX:
9858 add_bnd_prefix = 1;
9859 break;
9860
43234a1e
L		 9861 case OPTION_MEVEXLIG:
9862 if (strcmp (arg, "128") == 0)
9863 evexlig = evexl128;
9864 else if (strcmp (arg, "256") == 0)
9865 evexlig = evexl256;
9866 else if (strcmp (arg, "512") == 0)
9867 evexlig = evexl512;
9868 else
9869 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
9870 break;
9871
d3d3c6db
IT		 9872 case OPTION_MEVEXRCIG:
9873 if (strcmp (arg, "rne") == 0)
9874 evexrcig = rne;
9875 else if (strcmp (arg, "rd") == 0)
9876 evexrcig = rd;
9877 else if (strcmp (arg, "ru") == 0)
9878 evexrcig = ru;
9879 else if (strcmp (arg, "rz") == 0)
9880 evexrcig = rz;
9881 else
9882 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
9883 break;
9884
43234a1e
L		 9885 case OPTION_MEVEXWIG:
9886 if (strcmp (arg, "0") == 0)
9887 evexwig = evexw0;
9888 else if (strcmp (arg, "1") == 0)
9889 evexwig = evexw1;
9890 else
9891 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
9892 break;
9893
167ad85b
TG		 9894# if defined (TE_PE) || defined (TE_PEP)
9895 case OPTION_MBIG_OBJ:
9896 use_big_obj = 1;
9897 break;
9898#endif
9899
a5094208 9900 case OPTION_OMIT_LOCK_PREFIX:
d022bddd
IT		 9901 if (strcasecmp (arg, "yes") == 0)
9902 omit_lock_prefix = 1;
9903 else if (strcasecmp (arg, "no") == 0)
9904 omit_lock_prefix = 0;
9905 else
9906 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
9907 break;
9908
252b5132
RH		 9909 default:
9910 return 0;
9911 }
9912 return 1;
9913}
9914
8a2c8fef
L		 9915#define MESSAGE_TEMPLATE \
9916" "
9917
9918static void
1ded5609 9919show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 9920{
9921 static char message[] = MESSAGE_TEMPLATE;
9922 char *start = message + 27;
9923 char *p;
9924 int size = sizeof (MESSAGE_TEMPLATE);
9925 int left;
9926 const char *name;
9927 int len;
9928 unsigned int j;
9929
9930 p = start;
9931 left = size - (start - message);
9932 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9933 {
9934 /* Should it be skipped? */
9935 if (cpu_arch [j].skip)
9936 continue;
9937
9938 name = cpu_arch [j].name;
9939 len = cpu_arch [j].len;
9940 if (*name == '.')
9941 {
9942 /* It is an extension. Skip if we aren't asked to show it. */
9943 if (ext)
9944 {
9945 name++;
9946 len--;
9947 }
9948 else
9949 continue;
9950 }
9951 else if (ext)
9952 {
9953 /* It is an processor. Skip if we show only extension. */
9954 continue;
9955 }
1ded5609
JB		 9956 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
9957 {
9958 /* It is an impossible processor - skip. */
9959 continue;
9960 }
8a2c8fef
L		 9961
9962 /* Reserve 2 spaces for ", " or ",\0" */
9963 left -= len + 2;
9964
9965 /* Check if there is any room. */
9966 if (left >= 0)
9967 {
9968 if (p != start)
9969 {
9970 *p++ = ',';
9971 *p++ = ' ';
9972 }
9973 p = mempcpy (p, name, len);
9974 }
9975 else
9976 {
9977 /* Output the current message now and start a new one. */
9978 *p++ = ',';
9979 *p = '\0';
9980 fprintf (stream, "%s\n", message);
9981 p = start;
9982 left = size - (start - message) - len - 2;
8d63c93e 9983
8a2c8fef
L		 9984 gas_assert (left >= 0);
9985
9986 p = mempcpy (p, name, len);
9987 }
9988 }
9989
9990 *p = '\0';
9991 fprintf (stream, "%s\n", message);
9992}
9993
252b5132 9994void
8a2c8fef 9995md_show_usage (FILE *stream)
252b5132 9996{
4cc782b5
ILT		 9997#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9998 fprintf (stream, _("\
a38cf1db
AM		 9999 -Q ignored\n\
10000 -V print assembler version number\n\
b3b91714
AM		 10001 -k ignored\n"));
10002#endif
10003 fprintf (stream, _("\
12b55ccc 10004 -n Do not optimize code alignment\n\
b3b91714
AM		 10005 -q quieten some warnings\n"));
10006#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10007 fprintf (stream, _("\
a38cf1db 10008 -s ignored\n"));
b3b91714 10009#endif
321098a5
L		 10010#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10011 || defined (TE_PE) || defined (TE_PEP))
751d281c 10012 fprintf (stream, _("\
570561f7 10013 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10014#endif
b3b91714
AM		 10015#ifdef SVR4_COMMENT_CHARS
10016 fprintf (stream, _("\
10017 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10018#else
10019 fprintf (stream, _("\
b3b91714 10020 --divide ignored\n"));
4cc782b5 10021#endif
9103f4f4 10022 fprintf (stream, _("\
6305a203 10023 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10024 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10025 show_arch (stream, 0, 1);
8a2c8fef
L		 10026 fprintf (stream, _("\
10027 EXTENSION is combination of:\n"));
1ded5609 10028 show_arch (stream, 1, 0);
6305a203 10029 fprintf (stream, _("\
8a2c8fef 10030 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10031 show_arch (stream, 0, 0);
ba104c83 10032 fprintf (stream, _("\
c0f3af97
L		 10033 -msse2avx encode SSE instructions with VEX prefix\n"));
10034 fprintf (stream, _("\
daf50ae7
L		 10035 -msse-check=[none|error|warning]\n\
10036 check SSE instructions\n"));
10037 fprintf (stream, _("\
7bab8ab5
JB		 10038 -moperand-check=[none|error|warning]\n\
10039 check operand combinations for validity\n"));
10040 fprintf (stream, _("\
539f890d
L		 10041 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10042 length\n"));
10043 fprintf (stream, _("\
43234a1e
L		 10044 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10045 length\n"));
10046 fprintf (stream, _("\
10047 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10048 for EVEX.W bit ignored instructions\n"));
10049 fprintf (stream, _("\
d3d3c6db
IT		 10050 -mevexrcig=[rne|rd|ru|rz]\n\
10051 encode EVEX instructions with specific EVEX.RC value\n\
10052 for SAE-only ignored instructions\n"));
10053 fprintf (stream, _("\
ba104c83
L		 10054 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10055 fprintf (stream, _("\
10056 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10057 fprintf (stream, _("\
10058 -mindex-reg support pseudo index registers\n"));
10059 fprintf (stream, _("\
10060 -mnaked-reg don't require `%%' prefix for registers\n"));
10061 fprintf (stream, _("\
10062 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10063 fprintf (stream, _("\
10064 -madd-bnd-prefix add BND prefix for all valid branches\n"));
167ad85b
TG		 10065# if defined (TE_PE) || defined (TE_PEP)
10066 fprintf (stream, _("\
10067 -mbig-obj generate big object files\n"));
10068#endif
d022bddd
IT		 10069 fprintf (stream, _("\
10070 -momit-lock-prefix=[no|yes]\n\
10071 strip all lock prefixes\n"));
252b5132
RH		 10072}
10073
3e73aa7c 10074#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10075 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10076 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10077
10078/* Pick the target format to use. */
10079
47926f60 10080const char *
e3bb37b5 10081i386_target_format (void)
252b5132 10082{
351f65ca
L		 10083 if (!strncmp (default_arch, "x86_64", 6))
10084 {
10085 update_code_flag (CODE_64BIT, 1);
10086 if (default_arch[6] == '\0')
7f56bc95 10087 x86_elf_abi = X86_64_ABI;
351f65ca 10088 else
7f56bc95 10089 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10090 }
3e73aa7c 10091 else if (!strcmp (default_arch, "i386"))
78f12dd3 10092 update_code_flag (CODE_32BIT, 1);
3e73aa7c 10093 else
2b5d6a91 10094 as_fatal (_("unknown architecture"));
89507696
JB		 10095
10096 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10097 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10098 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10099 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10100
252b5132
RH		 10101 switch (OUTPUT_FLAVOR)
10102 {
9384f2ff 10103#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10104 case bfd_target_aout_flavour:
47926f60 10105 return AOUT_TARGET_FORMAT;
4c63da97 10106#endif
9384f2ff
AM		 10107#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10108# if defined (TE_PE) || defined (TE_PEP)
10109 case bfd_target_coff_flavour:
167ad85b
TG		 10110 if (flag_code == CODE_64BIT)
10111 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10112 else
10113 return "pe-i386";
9384f2ff 10114# elif defined (TE_GO32)
0561d57c
JK		 10115 case bfd_target_coff_flavour:
10116 return "coff-go32";
9384f2ff 10117# else
252b5132
RH		 10118 case bfd_target_coff_flavour:
10119 return "coff-i386";
9384f2ff 10120# endif
4c63da97 10121#endif
3e73aa7c 10122#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10123 case bfd_target_elf_flavour:
3e73aa7c 10124 {
351f65ca
L		 10125 const char *format;
10126
10127 switch (x86_elf_abi)
4fa24527 10128 {
351f65ca
L		 10129 default:
10130 format = ELF_TARGET_FORMAT;
10131 break;
7f56bc95 10132 case X86_64_ABI:
351f65ca 10133 use_rela_relocations = 1;
4fa24527 10134 object_64bit = 1;
351f65ca
L		 10135 format = ELF_TARGET_FORMAT64;
10136 break;
7f56bc95 10137 case X86_64_X32_ABI:
4fa24527 10138 use_rela_relocations = 1;
351f65ca 10139 object_64bit = 1;
862be3fb 10140 disallow_64bit_reloc = 1;
351f65ca
L		 10141 format = ELF_TARGET_FORMAT32;
10142 break;
4fa24527 10143 }
3632d14b 10144 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10145 {
7f56bc95 10146 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10147 as_fatal (_("Intel L1OM is 64bit only"));
10148 return ELF_TARGET_L1OM_FORMAT;
10149 }
7a9068fe
L		 10150 if (cpu_arch_isa == PROCESSOR_K1OM)
10151 {
10152 if (x86_elf_abi != X86_64_ABI)
10153 as_fatal (_("Intel K1OM is 64bit only"));
10154 return ELF_TARGET_K1OM_FORMAT;
10155 }
8a9036a4 10156 else
351f65ca 10157 return format;
3e73aa7c 10158 }
e57f8c65
TG		 10159#endif
10160#if defined (OBJ_MACH_O)
10161 case bfd_target_mach_o_flavour:
d382c579
TG		 10162 if (flag_code == CODE_64BIT)
10163 {
10164 use_rela_relocations = 1;
10165 object_64bit = 1;
10166 return "mach-o-x86-64";
10167 }
10168 else
10169 return "mach-o-i386";
4c63da97 10170#endif
252b5132
RH		 10171 default:
10172 abort ();
10173 return NULL;
10174 }
10175}
10176
47926f60 10177#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 10178
10179#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 10180void
10181i386_elf_emit_arch_note (void)
a847613f 10182{
718ddfc0 10183 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 10184 {
10185 char *p;
10186 asection *seg = now_seg;
10187 subsegT subseg = now_subseg;
10188 Elf_Internal_Note i_note;
10189 Elf_External_Note e_note;
10190 asection *note_secp;
10191 int len;
10192
10193 /* Create the .note section. */
10194 note_secp = subseg_new (".note", 0);
10195 bfd_set_section_flags (stdoutput,
10196 note_secp,
10197 SEC_HAS_CONTENTS | SEC_READONLY);
10198
10199 /* Process the arch string. */
10200 len = strlen (cpu_arch_name);
10201
10202 i_note.namesz = len + 1;
10203 i_note.descsz = 0;
10204 i_note.type = NT_ARCH;
10205 p = frag_more (sizeof (e_note.namesz));
10206 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
10207 p = frag_more (sizeof (e_note.descsz));
10208 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
10209 p = frag_more (sizeof (e_note.type));
10210 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
10211 p = frag_more (len + 1);
10212 strcpy (p, cpu_arch_name);
10213
10214 frag_align (2, 0, 0);
10215
10216 subseg_set (seg, subseg);
10217 }
10218}
10219#endif
252b5132 10220\f
252b5132 10221symbolS *
7016a5d5 10222md_undefined_symbol (char *name)
252b5132 10223{
18dc2407
ILT		 10224 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10225 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10226 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10227 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10228 {
10229 if (!GOT_symbol)
10230 {
10231 if (symbol_find (name))
10232 as_bad (_("GOT already in symbol table"));
10233 GOT_symbol = symbol_new (name, undefined_section,
10234 (valueT) 0, &zero_address_frag);
10235 };
10236 return GOT_symbol;
10237 }
252b5132
RH		 10238 return 0;
10239}
10240
10241/* Round up a section size to the appropriate boundary. */
47926f60 10242
252b5132 10243valueT
7016a5d5 10244md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10245{
4c63da97
AM		 10246#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10247 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10248 {
10249 /* For a.out, force the section size to be aligned. If we don't do
10250 this, BFD will align it for us, but it will not write out the
10251 final bytes of the section. This may be a bug in BFD, but it is
10252 easier to fix it here since that is how the other a.out targets
10253 work. */
10254 int align;
10255
10256 align = bfd_get_section_alignment (stdoutput, segment);
10257 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
10258 }
252b5132
RH		 10259#endif
10260
10261 return size;
10262}
10263
10264/* On the i386, PC-relative offsets are relative to the start of the
10265 next instruction. That is, the address of the offset, plus its
10266 size, since the offset is always the last part of the insn. */
10267
10268long
e3bb37b5 10269md_pcrel_from (fixS *fixP)
252b5132
RH		 10270{
10271 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10272}
10273
10274#ifndef I386COFF
10275
10276static void
e3bb37b5 10277s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10278{
29b0f896 10279 int temp;
252b5132 10280
8a75718c
JB		 10281#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10282 if (IS_ELF)
10283 obj_elf_section_change_hook ();
10284#endif
252b5132
RH		 10285 temp = get_absolute_expression ();
10286 subseg_set (bss_section, (subsegT) temp);
10287 demand_empty_rest_of_line ();
10288}
10289
10290#endif
10291
252b5132 10292void
e3bb37b5 10293i386_validate_fix (fixS *fixp)
252b5132
RH		 10294{
10295 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
10296 {
23df1078
JH		 10297 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10298 {
4fa24527 10299 if (!object_64bit)
23df1078
JH		 10300 abort ();
10301 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10302 }
10303 else
10304 {
4fa24527 10305 if (!object_64bit)
d6ab8113
JB		 10306 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10307 else
10308 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 10309 }
252b5132
RH		 10310 fixp->fx_subsy = 0;
10311 }
10312}
10313
252b5132 10314arelent *
7016a5d5 10315tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10316{
10317 arelent *rel;
10318 bfd_reloc_code_real_type code;
10319
10320 switch (fixp->fx_r_type)
10321 {
8ce3d284 10322#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10323 case BFD_RELOC_SIZE32:
10324 case BFD_RELOC_SIZE64:
10325 if (S_IS_DEFINED (fixp->fx_addsy)
10326 && !S_IS_EXTERNAL (fixp->fx_addsy))
10327 {
10328 /* Resolve size relocation against local symbol to size of
10329 the symbol plus addend. */
10330 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10331 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10332 && !fits_in_unsigned_long (value))
10333 as_bad_where (fixp->fx_file, fixp->fx_line,
10334 _("symbol size computation overflow"));
10335 fixp->fx_addsy = NULL;
10336 fixp->fx_subsy = NULL;
10337 md_apply_fix (fixp, (valueT *) &value, NULL);
10338 return NULL;
10339 }
8ce3d284 10340#endif
8fd4256d 10341
3e73aa7c
JH		 10342 case BFD_RELOC_X86_64_PLT32:
10343 case BFD_RELOC_X86_64_GOT32:
10344 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 10345 case BFD_RELOC_386_PLT32:
10346 case BFD_RELOC_386_GOT32:
10347 case BFD_RELOC_386_GOTOFF:
10348 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10349 case BFD_RELOC_386_TLS_GD:
10350 case BFD_RELOC_386_TLS_LDM:
10351 case BFD_RELOC_386_TLS_LDO_32:
10352 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10353 case BFD_RELOC_386_TLS_IE:
10354 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10355 case BFD_RELOC_386_TLS_LE_32:
10356 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10357 case BFD_RELOC_386_TLS_GOTDESC:
10358 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10359 case BFD_RELOC_X86_64_TLSGD:
10360 case BFD_RELOC_X86_64_TLSLD:
10361 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10362 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10363 case BFD_RELOC_X86_64_GOTTPOFF:
10364 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10365 case BFD_RELOC_X86_64_TPOFF64:
10366 case BFD_RELOC_X86_64_GOTOFF64:
10367 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10368 case BFD_RELOC_X86_64_GOT64:
10369 case BFD_RELOC_X86_64_GOTPCREL64:
10370 case BFD_RELOC_X86_64_GOTPC64:
10371 case BFD_RELOC_X86_64_GOTPLT64:
10372 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10373 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10374 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10375 case BFD_RELOC_RVA:
10376 case BFD_RELOC_VTABLE_ENTRY:
10377 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10378#ifdef TE_PE
10379 case BFD_RELOC_32_SECREL:
10380#endif
252b5132
RH		 10381 code = fixp->fx_r_type;
10382 break;
dbbaec26
L		 10383 case BFD_RELOC_X86_64_32S:
10384 if (!fixp->fx_pcrel)
10385 {
10386 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10387 code = fixp->fx_r_type;
10388 break;
10389 }
252b5132 10390 default:
93382f6d 10391 if (fixp->fx_pcrel)
252b5132 10392 {
93382f6d
AM		 10393 switch (fixp->fx_size)
10394 {
10395 default:
b091f402
AM		 10396 as_bad_where (fixp->fx_file, fixp->fx_line,
10397 _("can not do %d byte pc-relative relocation"),
10398 fixp->fx_size);
93382f6d
AM		 10399 code = BFD_RELOC_32_PCREL;
10400 break;
10401 case 1: code = BFD_RELOC_8_PCREL; break;
10402 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10403 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10404#ifdef BFD64
10405 case 8: code = BFD_RELOC_64_PCREL; break;
10406#endif
93382f6d
AM		 10407 }
10408 }
10409 else
10410 {
10411 switch (fixp->fx_size)
10412 {
10413 default:
b091f402
AM		 10414 as_bad_where (fixp->fx_file, fixp->fx_line,
10415 _("can not do %d byte relocation"),
10416 fixp->fx_size);
93382f6d
AM		 10417 code = BFD_RELOC_32;
10418 break;
10419 case 1: code = BFD_RELOC_8; break;
10420 case 2: code = BFD_RELOC_16; break;
10421 case 4: code = BFD_RELOC_32; break;
937149dd 10422#ifdef BFD64
3e73aa7c 10423 case 8: code = BFD_RELOC_64; break;
937149dd 10424#endif
93382f6d 10425 }
252b5132
RH		 10426 }
10427 break;
10428 }
252b5132 10429
d182319b
JB		 10430 if ((code == BFD_RELOC_32
10431 || code == BFD_RELOC_32_PCREL
10432 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10433 && GOT_symbol
10434 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10435 {
4fa24527 10436 if (!object_64bit)
d6ab8113
JB		 10437 code = BFD_RELOC_386_GOTPC;
10438 else
10439 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10440 }
7b81dfbb
AJ		 10441 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10442 && GOT_symbol
10443 && fixp->fx_addsy == GOT_symbol)
10444 {
10445 code = BFD_RELOC_X86_64_GOTPC64;
10446 }
252b5132
RH		 10447
10448 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 10449 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10450 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10451
10452 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10453
3e73aa7c
JH		 10454 if (!use_rela_relocations)
10455 {
10456 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10457 vtable entry to be used in the relocation's section offset. */
10458 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10459 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10460#if defined (OBJ_COFF) && defined (TE_PE)
10461 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10462 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10463 else
10464#endif
c6682705 10465 rel->addend = 0;
3e73aa7c
JH		 10466 }
10467 /* Use the rela in 64bit mode. */
252b5132 10468 else
3e73aa7c 10469 {
862be3fb
L		 10470 if (disallow_64bit_reloc)
10471 switch (code)
10472 {
862be3fb
L		 10473 case BFD_RELOC_X86_64_DTPOFF64:
10474 case BFD_RELOC_X86_64_TPOFF64:
10475 case BFD_RELOC_64_PCREL:
10476 case BFD_RELOC_X86_64_GOTOFF64:
10477 case BFD_RELOC_X86_64_GOT64:
10478 case BFD_RELOC_X86_64_GOTPCREL64:
10479 case BFD_RELOC_X86_64_GOTPC64:
10480 case BFD_RELOC_X86_64_GOTPLT64:
10481 case BFD_RELOC_X86_64_PLTOFF64:
10482 as_bad_where (fixp->fx_file, fixp->fx_line,
10483 _("cannot represent relocation type %s in x32 mode"),
10484 bfd_get_reloc_code_name (code));
10485 break;
10486 default:
10487 break;
10488 }
10489
062cd5e7
AS		 10490 if (!fixp->fx_pcrel)
10491 rel->addend = fixp->fx_offset;
10492 else
10493 switch (code)
10494 {
10495 case BFD_RELOC_X86_64_PLT32:
10496 case BFD_RELOC_X86_64_GOT32:
10497 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 10498 case BFD_RELOC_X86_64_TLSGD:
10499 case BFD_RELOC_X86_64_TLSLD:
10500 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10501 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10502 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10503 rel->addend = fixp->fx_offset - fixp->fx_size;
10504 break;
10505 default:
10506 rel->addend = (section->vma
10507 - fixp->fx_size
10508 + fixp->fx_addnumber
10509 + md_pcrel_from (fixp));
10510 break;
10511 }
3e73aa7c
JH		 10512 }
10513
252b5132
RH		 10514 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10515 if (rel->howto == NULL)
10516 {
10517 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10518 _("cannot represent relocation type %s"),
252b5132
RH		 10519 bfd_get_reloc_code_name (code));
10520 /* Set howto to a garbage value so that we can keep going. */
10521 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10522 gas_assert (rel->howto != NULL);
252b5132
RH		 10523 }
10524
10525 return rel;
10526}
10527
ee86248c 10528#include "tc-i386-intel.c"
54cfded0 10529
a60de03c
JB		 10530void
10531tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10532{
a60de03c
JB		 10533 int saved_naked_reg;
10534 char saved_register_dot;
54cfded0 10535
a60de03c
JB		 10536 saved_naked_reg = allow_naked_reg;
10537 allow_naked_reg = 1;
10538 saved_register_dot = register_chars['.'];
10539 register_chars['.'] = '.';
10540 allow_pseudo_reg = 1;
10541 expression_and_evaluate (exp);
10542 allow_pseudo_reg = 0;
10543 register_chars['.'] = saved_register_dot;
10544 allow_naked_reg = saved_naked_reg;
10545
e96d56a1 10546 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10547 {
a60de03c
JB		 10548 if ((addressT) exp->X_add_number < i386_regtab_size)
10549 {
10550 exp->X_op = O_constant;
10551 exp->X_add_number = i386_regtab[exp->X_add_number]
10552 .dw2_regnum[flag_code >> 1];
10553 }
10554 else
10555 exp->X_op = O_illegal;
54cfded0 10556 }
54cfded0
AM		 10557}
10558
10559void
10560tc_x86_frame_initial_instructions (void)
10561{
a60de03c
JB		 10562 static unsigned int sp_regno[2];
10563
10564 if (!sp_regno[flag_code >> 1])
10565 {
10566 char *saved_input = input_line_pointer;
10567 char sp[][4] = {"esp", "rsp"};
10568 expressionS exp;
a4447b93 10569
a60de03c
JB		 10570 input_line_pointer = sp[flag_code >> 1];
10571 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10572 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10573 sp_regno[flag_code >> 1] = exp.X_add_number;
10574 input_line_pointer = saved_input;
10575 }
a4447b93 10576
61ff971f
L		 10577 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10578 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10579}
d2b2c203 10580
d7921315
L		 10581int
10582x86_dwarf2_addr_size (void)
10583{
10584#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10585 if (x86_elf_abi == X86_64_X32_ABI)
10586 return 4;
10587#endif
10588 return bfd_arch_bits_per_address (stdoutput) / 8;
10589}
10590
d2b2c203
DJ		 10591int
10592i386_elf_section_type (const char *str, size_t len)
10593{
10594 if (flag_code == CODE_64BIT
10595 && len == sizeof ("unwind") - 1
10596 && strncmp (str, "unwind", 6) == 0)
10597 return SHT_X86_64_UNWIND;
10598
10599 return -1;
10600}
bb41ade5 10601
ad5fec3b
EB		 10602#ifdef TE_SOLARIS
10603void
10604i386_solaris_fix_up_eh_frame (segT sec)
10605{
10606 if (flag_code == CODE_64BIT)
10607 elf_section_type (sec) = SHT_X86_64_UNWIND;
10608}
10609#endif
10610
bb41ade5
AM		 10611#ifdef TE_PE
10612void
10613tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10614{
91d6fa6a 10615 expressionS exp;
bb41ade5 10616
91d6fa6a
NC		 10617 exp.X_op = O_secrel;
10618 exp.X_add_symbol = symbol;
10619 exp.X_add_number = 0;
10620 emit_expr (&exp, size);
bb41ade5
AM		 10621}
10622#endif
3b22753a
L		 10623
10624#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10625/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10626
01e1a5bc 10627bfd_vma
3b22753a
L		 10628x86_64_section_letter (int letter, char **ptr_msg)
10629{
10630 if (flag_code == CODE_64BIT)
10631 {
10632 if (letter == 'l')
10633 return SHF_X86_64_LARGE;
10634
8f3bae45 10635 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10636 }
3b22753a 10637 else
8f3bae45 10638 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10639 return -1;
10640}
10641
01e1a5bc 10642bfd_vma
3b22753a
L		 10643x86_64_section_word (char *str, size_t len)
10644{
8620418b 10645 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10646 return SHF_X86_64_LARGE;
10647
10648 return -1;
10649}
10650
10651static void
10652handle_large_common (int small ATTRIBUTE_UNUSED)
10653{
10654 if (flag_code != CODE_64BIT)
10655 {
10656 s_comm_internal (0, elf_common_parse);
10657 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10658 }
10659 else
10660 {
10661 static segT lbss_section;
10662 asection *saved_com_section_ptr = elf_com_section_ptr;
10663 asection *saved_bss_section = bss_section;
10664
10665 if (lbss_section == NULL)
10666 {
10667 flagword applicable;
10668 segT seg = now_seg;
10669 subsegT subseg = now_subseg;
10670
10671 /* The .lbss section is for local .largecomm symbols. */
10672 lbss_section = subseg_new (".lbss", 0);
10673 applicable = bfd_applicable_section_flags (stdoutput);
10674 bfd_set_section_flags (stdoutput, lbss_section,
10675 applicable & SEC_ALLOC);
10676 seg_info (lbss_section)->bss = 1;
10677
10678 subseg_set (seg, subseg);
10679 }
10680
10681 elf_com_section_ptr = &_bfd_elf_large_com_section;
10682 bss_section = lbss_section;
10683
10684 s_comm_internal (0, elf_common_parse);
10685
10686 elf_com_section_ptr = saved_com_section_ptr;
10687 bss_section = saved_bss_section;
10688 }
10689}
10690#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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