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Add R_386_GOT32X support to gas and ld
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
b90efa5b 2 Copyright (C) 1989-2015 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d
L		 68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
22109423 136 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 137}
138arch_entry;
139
78f12dd3 140static void update_code_flag (int, int);
e3bb37b5
L		 141static void set_code_flag (int);
142static void set_16bit_gcc_code_flag (int);
143static void set_intel_syntax (int);
1efbbeb4 144static void set_intel_mnemonic (int);
db51cc60 145static void set_allow_index_reg (int);
7bab8ab5 146static void set_check (int);
e3bb37b5 147static void set_cpu_arch (int);
6482c264 148#ifdef TE_PE
e3bb37b5 149static void pe_directive_secrel (int);
6482c264 150#endif
e3bb37b5
L		 151static void signed_cons (int);
152static char *output_invalid (int c);
ee86248c
JB		 153static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
154 const char *);
155static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
156 const char *);
a7619375 157static int i386_att_operand (char *);
e3bb37b5 158static int i386_intel_operand (char *, int);
ee86248c
JB		 159static int i386_intel_simplify (expressionS *);
160static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 161static const reg_entry *parse_register (char *, char **);
162static char *parse_insn (char *, char *);
163static char *parse_operands (char *, const char *);
164static void swap_operands (void);
4d456e3d 165static void swap_2_operands (int, int);
e3bb37b5
L		 166static void optimize_imm (void);
167static void optimize_disp (void);
d3ce72d0 168static const insn_template *match_template (void);
e3bb37b5
L		 169static int check_string (void);
170static int process_suffix (void);
171static int check_byte_reg (void);
172static int check_long_reg (void);
173static int check_qword_reg (void);
174static int check_word_reg (void);
175static int finalize_imm (void);
176static int process_operands (void);
177static const seg_entry *build_modrm_byte (void);
178static void output_insn (void);
179static void output_imm (fragS *, offsetT);
180static void output_disp (fragS *, offsetT);
29b0f896 181#ifndef I386COFF
e3bb37b5 182static void s_bss (int);
252b5132 183#endif
17d4e2a2
L		 184#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185static void handle_large_common (int small ATTRIBUTE_UNUSED);
186#endif
252b5132 187
a847613f 188static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 189
43234a1e
L		 190/* This struct describes rounding control and SAE in the instruction. */
191struct RC_Operation
192{
193 enum rc_type
194 {
195 rne = 0,
196 rd,
197 ru,
198 rz,
199 saeonly
200 } type;
201 int operand;
202};
203
204static struct RC_Operation rc_op;
205
206/* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209struct Mask_Operation
210{
211 const reg_entry *mask;
212 unsigned int zeroing;
213 /* The operand where this operation is associated. */
214 int operand;
215};
216
217static struct Mask_Operation mask_op;
218
219/* The struct describes broadcasting, applied to OPERAND. FACTOR is
220 broadcast factor. */
221struct Broadcast_Operation
222{
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
224 int type;
225
226 /* Index of broadcasted operand. */
227 int operand;
228};
229
230static struct Broadcast_Operation broadcast_op;
231
c0f3af97
L		 232/* VEX prefix. */
233typedef struct
234{
43234a1e
L		 235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes[4];
c0f3af97
L		 237 unsigned int length;
238 /* Destination or source register specifier. */
239 const reg_entry *register_specifier;
240} vex_prefix;
241
252b5132 242/* 'md_assemble ()' gathers together information and puts it into a
47926f60 243 i386_insn. */
252b5132 244
520dc8e8
AM		 245union i386_op
246 {
247 expressionS *disps;
248 expressionS *imms;
249 const reg_entry *regs;
250 };
251
a65babc9
L		 252enum i386_error
253 {
86e026a4 254 operand_size_mismatch,
a65babc9
L		 255 operand_type_mismatch,
256 register_type_mismatch,
257 number_of_operands_mismatch,
258 invalid_instruction_suffix,
259 bad_imm4,
260 old_gcc_only,
261 unsupported_with_intel_mnemonic,
262 unsupported_syntax,
6c30d220
L		 263 unsupported,
264 invalid_vsib_address,
7bab8ab5 265 invalid_vector_register_set,
43234a1e
L		 266 unsupported_vector_index_register,
267 unsupported_broadcast,
268 broadcast_not_on_src_operand,
269 broadcast_needed,
270 unsupported_masking,
271 mask_not_on_destination,
272 no_default_mask,
273 unsupported_rc_sae,
274 rc_sae_operand_not_last_imm,
275 invalid_register_operand,
276 try_vector_disp8
a65babc9
L		 277 };
278
252b5132
RH		 279struct _i386_insn
280 {
47926f60 281 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 282 insn_template tm;
252b5132 283
7d5e4556
L		 284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
252b5132
RH		 286 char suffix;
287
47926f60 288 /* OPERANDS gives the number of given operands. */
252b5132
RH		 289 unsigned int operands;
290
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
47926f60 293 operands. */
252b5132
RH		 294 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
295
296 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 297 use OP[i] for the corresponding operand. */
40fb9820 298 i386_operand_type types[MAX_OPERANDS];
252b5132 299
520dc8e8
AM		 300 /* Displacement expression, immediate expression, or register for each
301 operand. */
302 union i386_op op[MAX_OPERANDS];
252b5132 303
3e73aa7c
JH		 304 /* Flags for operands. */
305 unsigned int flags[MAX_OPERANDS];
306#define Operand_PCrel 1
307
252b5132 308 /* Relocation type for operand */
f86103b7 309 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 310
252b5132
RH		 311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry *base_reg;
314 const reg_entry *index_reg;
315 unsigned int log2_scale_factor;
316
317 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 318 explicit segment overrides are given. */
ce8a8b2f 319 const seg_entry *seg[2];
252b5132
RH		 320
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes;
324 unsigned char prefix[MAX_PREFIXES];
325
326 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 327 addressing modes of this insn are encoded. */
252b5132 328 modrm_byte rm;
3e73aa7c 329 rex_byte rex;
43234a1e 330 rex_byte vrex;
252b5132 331 sib_byte sib;
c0f3af97 332 vex_prefix vex;
b6169b20 333
43234a1e
L		 334 /* Masking attributes. */
335 struct Mask_Operation *mask;
336
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation *rounding;
339
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation *broadcast;
342
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift;
345
b6169b20 346 /* Swap operand in encoding. */
4473e004 347 unsigned int swap_operand;
891edac4 348
a501d77e
L		 349 /* Prefer 8bit or 32bit displacement in encoding. */
350 enum
351 {
352 disp_encoding_default = 0,
353 disp_encoding_8bit,
354 disp_encoding_32bit
355 } disp_encoding;
f8a5c266 356
d5de92cf
L		 357 /* REP prefix. */
358 const char *rep_prefix;
359
165de32a
L		 360 /* HLE prefix. */
361 const char *hle_prefix;
42164a71 362
7e8b059b
L		 363 /* Have BND prefix. */
364 const char *bnd_prefix;
365
43234a1e
L		 366 /* Need VREX to support upper 16 registers. */
367 int need_vrex;
368
891edac4 369 /* Error message. */
a65babc9 370 enum i386_error error;
252b5132
RH		 371 };
372
373typedef struct _i386_insn i386_insn;
374
43234a1e
L		 375/* Link RC type with corresponding string, that'll be looked for in
376 asm. */
377struct RC_name
378{
379 enum rc_type type;
380 const char *name;
381 unsigned int len;
382};
383
384static const struct RC_name RC_NamesTable[] =
385{
386 { rne, STRING_COMMA_LEN ("rn-sae") },
387 { rd, STRING_COMMA_LEN ("rd-sae") },
388 { ru, STRING_COMMA_LEN ("ru-sae") },
389 { rz, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly, STRING_COMMA_LEN ("sae") },
391};
392
252b5132
RH		 393/* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 395const char extra_symbol_chars[] = "*%-([{"
252b5132 396#ifdef LEX_AT
32137342
NC		 397 "@"
398#endif
399#ifdef LEX_QM
400 "?"
252b5132 401#endif
32137342 402 ;
252b5132 403
29b0f896
AM		 404#if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 406 && !defined (TE_GNU) \
29b0f896 407 && !defined (TE_LINUX) \
8d63c93e
RM		 408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
29b0f896 410 && !defined (TE_FreeBSD) \
5b806d27 411 && !defined (TE_DragonFly) \
29b0f896 412 && !defined (TE_NetBSD)))
252b5132 413/* This array holds the chars that always start a comment. If the
b3b91714
AM		 414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416const char *i386_comment_chars = "#/";
417#define SVR4_COMMENT_CHARS 1
252b5132 418#define PREFIX_SEPARATOR '\\'
252b5132 419
b3b91714
AM		 420#else
421const char *i386_comment_chars = "#";
422#define PREFIX_SEPARATOR '/'
423#endif
424
252b5132
RH		 425/* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 429 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
252b5132 432 '/' isn't otherwise defined. */
b3b91714 433const char line_comment_chars[] = "#/";
252b5132 434
63a0b638 435const char line_separator_chars[] = ";";
252b5132 436
ce8a8b2f
AM		 437/* Chars that can be used to separate mant from exp in floating point
438 nums. */
252b5132
RH		 439const char EXP_CHARS[] = "eE";
440
ce8a8b2f
AM		 441/* Chars that mean this number is a floating point constant
442 As in 0f12.456
443 or 0d1.2345e12. */
252b5132
RH		 444const char FLT_CHARS[] = "fFdDxX";
445
ce8a8b2f 446/* Tables for lexical analysis. */
252b5132
RH		 447static char mnemonic_chars[256];
448static char register_chars[256];
449static char operand_chars[256];
450static char identifier_chars[256];
451static char digit_chars[256];
452
ce8a8b2f 453/* Lexical macros. */
252b5132
RH		 454#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455#define is_operand_char(x) (operand_chars[(unsigned char) x])
456#define is_register_char(x) (register_chars[(unsigned char) x])
457#define is_space_char(x) ((x) == ' ')
458#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459#define is_digit_char(x) (digit_chars[(unsigned char) x])
460
0234cb7c 461/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 462static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
463
464/* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
47926f60 467 assembler instruction). */
252b5132 468static char save_stack[32];
ce8a8b2f 469static char *save_stack_p;
252b5132
RH		 470#define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472#define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
474
47926f60 475/* The instruction we're assembling. */
252b5132
RH		 476static i386_insn i;
477
478/* Possible templates for current insn. */
479static const templates *current_templates;
480
31b2323c
L		 481/* Per instruction expressionS buffers: max displacements & immediates. */
482static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
483static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 484
47926f60 485/* Current operand we are working on. */
ee86248c 486static int this_operand = -1;
252b5132 487
3e73aa7c
JH		 488/* We support four different modes. FLAG_CODE variable is used to distinguish
489 these. */
490
491enum flag_code {
492 CODE_32BIT,
493 CODE_16BIT,
494 CODE_64BIT };
495
496static enum flag_code flag_code;
4fa24527 497static unsigned int object_64bit;
862be3fb 498static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 499static int use_rela_relocations = 0;
500
7af8ed2d
NC		 501#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
504
351f65ca
L		 505/* The ELF ABI to use. */
506enum x86_elf_abi
507{
508 I386_ABI,
7f56bc95
L		 509 X86_64_ABI,
510 X86_64_X32_ABI
351f65ca
L		 511};
512
513static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 514#endif
351f65ca 515
167ad85b
TG		 516#if defined (TE_PE) || defined (TE_PEP)
517/* Use big object file format. */
518static int use_big_obj = 0;
519#endif
520
8dcea932
L		 521#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
522/* 1 if generating code for a shared library. */
523static int shared = 0;
524#endif
525
47926f60
KH		 526/* 1 for intel syntax,
527 0 if att syntax. */
528static int intel_syntax = 0;
252b5132 529
1efbbeb4
L		 530/* 1 for intel mnemonic,
531 0 if att mnemonic. */
532static int intel_mnemonic = !SYSV386_COMPAT;
533
5209009a 534/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 535static int old_gcc = OLDGCC_COMPAT;
536
a60de03c
JB		 537/* 1 if pseudo registers are permitted. */
538static int allow_pseudo_reg = 0;
539
47926f60
KH		 540/* 1 if register prefix % not required. */
541static int allow_naked_reg = 0;
252b5132 542
7e8b059b
L		 543/* 1 if the assembler should add BND prefix for all control-tranferring
544 instructions supporting it, even if this prefix wasn't specified
545 explicitly. */
546static int add_bnd_prefix = 0;
547
ba104c83 548/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 549static int allow_index_reg = 0;
550
d022bddd
IT		 551/* 1 if the assembler should ignore LOCK prefix, even if it was
552 specified explicitly. */
553static int omit_lock_prefix = 0;
554
7bab8ab5 555static enum check_kind
daf50ae7 556 {
7bab8ab5
JB		 557 check_none = 0,
558 check_warning,
559 check_error
daf50ae7 560 }
7bab8ab5 561sse_check, operand_check = check_warning;
daf50ae7 562
2ca3ace5
L		 563/* Register prefix used for error message. */
564static const char *register_prefix = "%";
565
47926f60
KH		 566/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
567 leave, push, and pop instructions so that gcc has the same stack
568 frame as in 32 bit mode. */
569static char stackop_size = '\0';
eecb386c 570
12b55ccc
L		 571/* Non-zero to optimize code alignment. */
572int optimize_align_code = 1;
573
47926f60
KH		 574/* Non-zero to quieten some warnings. */
575static int quiet_warnings = 0;
a38cf1db 576
47926f60
KH		 577/* CPU name. */
578static const char *cpu_arch_name = NULL;
6305a203 579static char *cpu_sub_arch_name = NULL;
a38cf1db 580
47926f60 581/* CPU feature flags. */
40fb9820
L		 582static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
583
ccc9c027
L		 584/* If we have selected a cpu we are generating instructions for. */
585static int cpu_arch_tune_set = 0;
586
9103f4f4 587/* Cpu we are generating instructions for. */
fbf3f584 588enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 589
590/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 591static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 592
ccc9c027 593/* CPU instruction set architecture used. */
fbf3f584 594enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 595
9103f4f4 596/* CPU feature flags of instruction set architecture used. */
fbf3f584 597i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 598
fddf5b5b
AM		 599/* If set, conditional jumps are not automatically promoted to handle
600 larger than a byte offset. */
601static unsigned int no_cond_jump_promotion = 0;
602
c0f3af97
L		 603/* Encode SSE instructions with VEX prefix. */
604static unsigned int sse2avx;
605
539f890d
L		 606/* Encode scalar AVX instructions with specific vector length. */
607static enum
608 {
609 vex128 = 0,
610 vex256
611 } avxscalar;
612
43234a1e
L		 613/* Encode scalar EVEX LIG instructions with specific vector length. */
614static enum
615 {
616 evexl128 = 0,
617 evexl256,
618 evexl512
619 } evexlig;
620
621/* Encode EVEX WIG instructions with specific evex.w. */
622static enum
623 {
624 evexw0 = 0,
625 evexw1
626 } evexwig;
627
d3d3c6db
IT		 628/* Value to encode in EVEX RC bits, for SAE-only instructions. */
629static enum rc_type evexrcig = rne;
630
29b0f896 631/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 632static symbolS *GOT_symbol;
29b0f896 633
a4447b93
RH		 634/* The dwarf2 return column, adjusted for 32 or 64 bit. */
635unsigned int x86_dwarf2_return_column;
636
637/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
638int x86_cie_data_alignment;
639
252b5132 640/* Interface to relax_segment.
fddf5b5b
AM		 641 There are 3 major relax states for 386 jump insns because the
642 different types of jumps add different sizes to frags when we're
643 figuring out what sort of jump to choose to reach a given label. */
252b5132 644
47926f60 645/* Types. */
93c2a809
AM		 646#define UNCOND_JUMP 0
647#define COND_JUMP 1
648#define COND_JUMP86 2
fddf5b5b 649
47926f60 650/* Sizes. */
252b5132
RH		 651#define CODE16 1
652#define SMALL 0
29b0f896 653#define SMALL16 (SMALL | CODE16)
252b5132 654#define BIG 2
29b0f896 655#define BIG16 (BIG | CODE16)
252b5132
RH		 656
657#ifndef INLINE
658#ifdef __GNUC__
659#define INLINE __inline__
660#else
661#define INLINE
662#endif
663#endif
664
fddf5b5b
AM		 665#define ENCODE_RELAX_STATE(type, size) \
666 ((relax_substateT) (((type) << 2) | (size)))
667#define TYPE_FROM_RELAX_STATE(s) \
668 ((s) >> 2)
669#define DISP_SIZE_FROM_RELAX_STATE(s) \
670 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 671
672/* This table is used by relax_frag to promote short jumps to long
673 ones where necessary. SMALL (short) jumps may be promoted to BIG
674 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
675 don't allow a short jump in a 32 bit code segment to be promoted to
676 a 16 bit offset jump because it's slower (requires data size
677 prefix), and doesn't work, unless the destination is in the bottom
678 64k of the code segment (The top 16 bits of eip are zeroed). */
679
680const relax_typeS md_relax_table[] =
681{
24eab124
AM		 682 /* The fields are:
683 1) most positive reach of this state,
684 2) most negative reach of this state,
93c2a809 685 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 686 4) which index into the table to try if we can't fit into this one. */
252b5132 687
fddf5b5b 688 /* UNCOND_JUMP states. */
93c2a809
AM		 689 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
690 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
691 /* dword jmp adds 4 bytes to frag:
692 0 extra opcode bytes, 4 displacement bytes. */
252b5132 693 {0, 0, 4, 0},
93c2a809
AM		 694 /* word jmp adds 2 byte2 to frag:
695 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 696 {0, 0, 2, 0},
697
93c2a809
AM		 698 /* COND_JUMP states. */
699 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
700 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
701 /* dword conditionals adds 5 bytes to frag:
702 1 extra opcode byte, 4 displacement bytes. */
703 {0, 0, 5, 0},
fddf5b5b 704 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 705 1 extra opcode byte, 2 displacement bytes. */
706 {0, 0, 3, 0},
707
708 /* COND_JUMP86 states. */
709 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
710 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
711 /* dword conditionals adds 5 bytes to frag:
712 1 extra opcode byte, 4 displacement bytes. */
713 {0, 0, 5, 0},
714 /* word conditionals add 4 bytes to frag:
715 1 displacement byte and a 3 byte long branch insn. */
716 {0, 0, 4, 0}
252b5132
RH		 717};
718
9103f4f4
L		 719static const arch_entry cpu_arch[] =
720{
89507696
JB		 721 /* Do not replace the first two entries - i386_target_format()
722 relies on them being there in this order. */
8a2c8fef 723 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 724 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 725 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 726 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 727 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 728 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 729 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 730 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 731 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 732 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 733 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 734 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 735 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 736 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 737 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 738 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 739 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 740 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 741 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 742 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 743 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 744 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 745 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 746 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 747 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 748 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 749 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 750 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 751 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 752 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 753 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 754 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 755 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 756 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 757 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 758 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 759 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 760 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 761 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 762 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 763 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 764 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 765 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 766 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 767 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
768 CPU_K1OM_FLAGS, 0, 0 },
81486035
L		 769 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
770 CPU_IAMCU_FLAGS, 0, 0 },
8a2c8fef 771 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 772 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 773 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 774 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 775 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 776 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 777 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 778 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 779 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 780 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 781 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 782 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 783 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 784 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 785 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 786 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 787 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 788 CPU_BDVER2_FLAGS, 0, 0 },
5e5c50d3
NE		 789 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
790 CPU_BDVER3_FLAGS, 0, 0 },
c7b0bd56
SE		 791 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
792 CPU_BDVER4_FLAGS, 0, 0 },
029f3522 793 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
3739860c 794 CPU_ZNVER1_FLAGS, 0, 0 },
7b458c12
L		 795 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
796 CPU_BTVER1_FLAGS, 0, 0 },
797 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
798 CPU_BTVER2_FLAGS, 0, 0 },
8a2c8fef 799 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 800 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 801 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 802 CPU_287_FLAGS, 0, 0 },
8a2c8fef 803 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 804 CPU_387_FLAGS, 0, 0 },
8a2c8fef 805 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 806 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 807 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 808 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 809 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 810 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 811 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 812 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 813 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 814 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 815 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 816 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 817 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 818 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 819 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 820 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 821 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 822 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 823 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 824 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 825 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 826 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 827 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 828 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 829 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
830 CPU_AVX2_FLAGS, 0, 0 },
43234a1e
L		 831 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
832 CPU_AVX512F_FLAGS, 0, 0 },
833 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
834 CPU_AVX512CD_FLAGS, 0, 0 },
835 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
836 CPU_AVX512ER_FLAGS, 0, 0 },
837 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
838 CPU_AVX512PF_FLAGS, 0, 0 },
1dfc6506
L		 839 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
840 CPU_AVX512DQ_FLAGS, 0, 0 },
841 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
842 CPU_AVX512BW_FLAGS, 0, 0 },
843 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
844 CPU_AVX512VL_FLAGS, 0, 0 },
8a2c8fef 845 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 846 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 847 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 848 CPU_VMX_FLAGS, 0, 0 },
8729a6f6
L		 849 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
850 CPU_VMFUNC_FLAGS, 0, 0 },
8a2c8fef 851 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 852 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 853 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 854 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 855 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 856 CPU_XSAVEOPT_FLAGS, 0, 0 },
1dfc6506
L		 857 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
858 CPU_XSAVEC_FLAGS, 0, 0 },
859 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
860 CPU_XSAVES_FLAGS, 0, 0 },
8a2c8fef 861 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 862 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 863 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 864 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 865 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 866 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 867 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 868 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 869 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 870 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 871 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 872 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 873 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
874 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 875 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 876 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 877 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 878 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 879 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 880 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 881 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 882 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 883 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 884 CPU_MOVBE_FLAGS, 0, 0 },
60aa667e
L		 885 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
886 CPU_CX16_FLAGS, 0, 0 },
8a2c8fef 887 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 888 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 889 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
890 CPU_LZCNT_FLAGS, 0, 0 },
42164a71
L		 891 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
892 CPU_HLE_FLAGS, 0, 0 },
893 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
894 CPU_RTM_FLAGS, 0, 0 },
6c30d220
L		 895 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
896 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 897 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 898 CPU_CLFLUSH_FLAGS, 0, 0 },
899 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
900 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 901 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 902 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 903 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 904 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 905 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 906 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 907 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 908 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 909 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 910 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 911 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 912 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 913 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 914 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 915 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 916 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 917 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 918 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 919 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
920 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 921 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
922 CPU_TBM_FLAGS, 0, 0 },
e2e1fcde
L		 923 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
924 CPU_ADX_FLAGS, 0, 0 },
925 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
926 CPU_RDSEED_FLAGS, 0, 0 },
927 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
928 CPU_PRFCHW_FLAGS, 0, 0 },
5c111e37
L		 929 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
930 CPU_SMAP_FLAGS, 0, 0 },
7e8b059b
L		 931 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
932 CPU_MPX_FLAGS, 0, 0 },
a0046408
L		 933 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
934 CPU_SHA_FLAGS, 0, 0 },
963f3586
IT		 935 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
936 CPU_CLFLUSHOPT_FLAGS, 0, 0 },
dcf893b5
IT		 937 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
938 CPU_PREFETCHWT1_FLAGS, 0, 0 },
2cf200a4
IT		 939 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
940 CPU_SE1_FLAGS, 0, 0 },
c5e7287a
IT		 941 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
942 CPU_CLWB_FLAGS, 0, 0 },
9d8596f0
IT		 943 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN,
944 CPU_PCOMMIT_FLAGS, 0, 0 },
2cc1b5aa
IT		 945 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
946 CPU_AVX512IFMA_FLAGS, 0, 0 },
14f195c9
IT		 947 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
948 CPU_AVX512VBMI_FLAGS, 0, 0 },
029f3522
GG		 949 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
950 CPU_CLZERO_FLAGS, 0, 0 },
9916071f
AP		 951 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
952 CPU_MWAITX_FLAGS, 0, 0 },
e413e4e9
AM		 953};
954
704209c0 955#ifdef I386COFF
a6c24e68
NC		 956/* Like s_lcomm_internal in gas/read.c but the alignment string
957 is allowed to be optional. */
958
959static symbolS *
960pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
961{
962 addressT align = 0;
963
964 SKIP_WHITESPACE ();
965
7ab9ffdd 966 if (needs_align
a6c24e68
NC		 967 && *input_line_pointer == ',')
968 {
969 align = parse_align (needs_align - 1);
7ab9ffdd 970
a6c24e68
NC		 971 if (align == (addressT) -1)
972 return NULL;
973 }
974 else
975 {
976 if (size >= 8)
977 align = 3;
978 else if (size >= 4)
979 align = 2;
980 else if (size >= 2)
981 align = 1;
982 else
983 align = 0;
984 }
985
986 bss_alloc (symbolP, size, align);
987 return symbolP;
988}
989
704209c0 990static void
a6c24e68
NC		 991pe_lcomm (int needs_align)
992{
993 s_comm_internal (needs_align * 2, pe_lcomm_internal);
994}
704209c0 995#endif
a6c24e68 996
29b0f896
AM		 997const pseudo_typeS md_pseudo_table[] =
998{
999#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1000 {"align", s_align_bytes, 0},
1001#else
1002 {"align", s_align_ptwo, 0},
1003#endif
1004 {"arch", set_cpu_arch, 0},
1005#ifndef I386COFF
1006 {"bss", s_bss, 0},
a6c24e68
NC		 1007#else
1008 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1009#endif
1010 {"ffloat", float_cons, 'f'},
1011 {"dfloat", float_cons, 'd'},
1012 {"tfloat", float_cons, 'x'},
1013 {"value", cons, 2},
d182319b 1014 {"slong", signed_cons, 4},
29b0f896
AM		 1015 {"noopt", s_ignore, 0},
1016 {"optim", s_ignore, 0},
1017 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1018 {"code16", set_code_flag, CODE_16BIT},
1019 {"code32", set_code_flag, CODE_32BIT},
1020 {"code64", set_code_flag, CODE_64BIT},
1021 {"intel_syntax", set_intel_syntax, 1},
1022 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1023 {"intel_mnemonic", set_intel_mnemonic, 1},
1024 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1025 {"allow_index_reg", set_allow_index_reg, 1},
1026 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1027 {"sse_check", set_check, 0},
1028 {"operand_check", set_check, 1},
3b22753a
L		 1029#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1030 {"largecomm", handle_large_common, 0},
07a53e5c 1031#else
e3bb37b5 1032 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1033 {"loc", dwarf2_directive_loc, 0},
1034 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1035#endif
6482c264
NC		 1036#ifdef TE_PE
1037 {"secrel32", pe_directive_secrel, 0},
1038#endif
29b0f896
AM		 1039 {0, 0, 0}
1040};
1041
1042/* For interface with expression (). */
1043extern char *input_line_pointer;
1044
1045/* Hash table for instruction mnemonic lookup. */
1046static struct hash_control *op_hash;
1047
1048/* Hash table for register lookup. */
1049static struct hash_control *reg_hash;
1050\f
252b5132 1051void
e3bb37b5 1052i386_align_code (fragS *fragP, int count)
252b5132 1053{
ce8a8b2f
AM		 1054 /* Various efficient no-op patterns for aligning code labels.
1055 Note: Don't try to assemble the instructions in the comments.
1056 0L and 0w are not legal. */
252b5132
RH		 1057 static const char f32_1[] =
1058 {0x90}; /* nop */
1059 static const char f32_2[] =
ccc9c027 1060 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 1061 static const char f32_3[] =
1062 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1063 static const char f32_4[] =
1064 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1065 static const char f32_5[] =
1066 {0x90, /* nop */
1067 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1068 static const char f32_6[] =
1069 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1070 static const char f32_7[] =
1071 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1072 static const char f32_8[] =
1073 {0x90, /* nop */
1074 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1075 static const char f32_9[] =
1076 {0x89,0xf6, /* movl %esi,%esi */
1077 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1078 static const char f32_10[] =
1079 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1080 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1081 static const char f32_11[] =
1082 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1083 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1084 static const char f32_12[] =
1085 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1086 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1087 static const char f32_13[] =
1088 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1089 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1090 static const char f32_14[] =
1091 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1092 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 1093 static const char f16_3[] =
1094 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 1095 static const char f16_4[] =
1096 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1097 static const char f16_5[] =
1098 {0x90, /* nop */
1099 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1100 static const char f16_6[] =
1101 {0x89,0xf6, /* mov %si,%si */
1102 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1103 static const char f16_7[] =
1104 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1105 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1106 static const char f16_8[] =
1107 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1108 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 1109 static const char jump_31[] =
1110 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1111 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1112 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1113 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 1114 static const char *const f32_patt[] = {
1115 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1116 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 1117 };
1118 static const char *const f16_patt[] = {
76bc74dc 1119 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1120 };
ccc9c027
L		 1121 /* nopl (%[re]ax) */
1122 static const char alt_3[] =
1123 {0x0f,0x1f,0x00};
1124 /* nopl 0(%[re]ax) */
1125 static const char alt_4[] =
1126 {0x0f,0x1f,0x40,0x00};
1127 /* nopl 0(%[re]ax,%[re]ax,1) */
1128 static const char alt_5[] =
1129 {0x0f,0x1f,0x44,0x00,0x00};
1130 /* nopw 0(%[re]ax,%[re]ax,1) */
1131 static const char alt_6[] =
1132 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1133 /* nopl 0L(%[re]ax) */
1134 static const char alt_7[] =
1135 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1136 /* nopl 0L(%[re]ax,%[re]ax,1) */
1137 static const char alt_8[] =
1138 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1139 /* nopw 0L(%[re]ax,%[re]ax,1) */
1140 static const char alt_9[] =
1141 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1142 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1143 static const char alt_10[] =
1144 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
80b8656c 1145 static const char *const alt_patt[] = {
ccc9c027 1146 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
80b8656c 1147 alt_9, alt_10
ccc9c027 1148 };
252b5132 1149
76bc74dc
L		 1150 /* Only align for at least a positive non-zero boundary. */
1151 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1152 return;
3e73aa7c 1153
ccc9c027
L		 1154 /* We need to decide which NOP sequence to use for 32bit and
1155 64bit. When -mtune= is used:
4eed87de 1156
76bc74dc
L		 1157 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1158 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1159 2. For the rest, alt_patt will be used.
1160
1161 When -mtune= isn't used, alt_patt will be used if
22109423 1162 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1163 be used.
ccc9c027
L		 1164
1165 When -march= or .arch is used, we can't use anything beyond
1166 cpu_arch_isa_flags. */
1167
1168 if (flag_code == CODE_16BIT)
1169 {
ccc9c027 1170 if (count > 8)
33fef721 1171 {
76bc74dc
L		 1172 memcpy (fragP->fr_literal + fragP->fr_fix,
1173 jump_31, count);
1174 /* Adjust jump offset. */
1175 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1176 }
76bc74dc
L		 1177 else
1178 memcpy (fragP->fr_literal + fragP->fr_fix,
1179 f16_patt[count - 1], count);
252b5132 1180 }
33fef721 1181 else
ccc9c027
L		 1182 {
1183 const char *const *patt = NULL;
1184
fbf3f584 1185 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1186 {
1187 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1188 switch (cpu_arch_tune)
1189 {
1190 case PROCESSOR_UNKNOWN:
1191 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1192 optimize with nops. */
1193 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1194 patt = alt_patt;
ccc9c027
L		 1195 else
1196 patt = f32_patt;
1197 break;
ccc9c027
L		 1198 case PROCESSOR_PENTIUM4:
1199 case PROCESSOR_NOCONA:
ef05d495 1200 case PROCESSOR_CORE:
76bc74dc 1201 case PROCESSOR_CORE2:
bd5295b2 1202 case PROCESSOR_COREI7:
3632d14b 1203 case PROCESSOR_L1OM:
7a9068fe 1204 case PROCESSOR_K1OM:
76bc74dc 1205 case PROCESSOR_GENERIC64:
ccc9c027
L		 1206 case PROCESSOR_K6:
1207 case PROCESSOR_ATHLON:
1208 case PROCESSOR_K8:
4eed87de 1209 case PROCESSOR_AMDFAM10:
8aedb9fe 1210 case PROCESSOR_BD:
029f3522 1211 case PROCESSOR_ZNVER:
7b458c12 1212 case PROCESSOR_BT:
80b8656c 1213 patt = alt_patt;
ccc9c027 1214 break;
76bc74dc 1215 case PROCESSOR_I386:
ccc9c027
L		 1216 case PROCESSOR_I486:
1217 case PROCESSOR_PENTIUM:
2dde1948 1218 case PROCESSOR_PENTIUMPRO:
81486035 1219 case PROCESSOR_IAMCU:
ccc9c027
L		 1220 case PROCESSOR_GENERIC32:
1221 patt = f32_patt;
1222 break;
4eed87de 1223 }
ccc9c027
L		 1224 }
1225 else
1226 {
fbf3f584 1227 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1228 {
1229 case PROCESSOR_UNKNOWN:
e6a14101 1230 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1231 PROCESSOR_UNKNOWN. */
1232 abort ();
1233 break;
1234
76bc74dc 1235 case PROCESSOR_I386:
ccc9c027
L		 1236 case PROCESSOR_I486:
1237 case PROCESSOR_PENTIUM:
81486035 1238 case PROCESSOR_IAMCU:
ccc9c027
L		 1239 case PROCESSOR_K6:
1240 case PROCESSOR_ATHLON:
1241 case PROCESSOR_K8:
4eed87de 1242 case PROCESSOR_AMDFAM10:
8aedb9fe 1243 case PROCESSOR_BD:
029f3522 1244 case PROCESSOR_ZNVER:
7b458c12 1245 case PROCESSOR_BT:
ccc9c027
L		 1246 case PROCESSOR_GENERIC32:
1247 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1248 with nops. */
1249 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1250 patt = alt_patt;
ccc9c027
L		 1251 else
1252 patt = f32_patt;
1253 break;
76bc74dc
L		 1254 case PROCESSOR_PENTIUMPRO:
1255 case PROCESSOR_PENTIUM4:
1256 case PROCESSOR_NOCONA:
1257 case PROCESSOR_CORE:
ef05d495 1258 case PROCESSOR_CORE2:
bd5295b2 1259 case PROCESSOR_COREI7:
3632d14b 1260 case PROCESSOR_L1OM:
7a9068fe 1261 case PROCESSOR_K1OM:
22109423 1262 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1263 patt = alt_patt;
ccc9c027
L		 1264 else
1265 patt = f32_patt;
1266 break;
1267 case PROCESSOR_GENERIC64:
80b8656c 1268 patt = alt_patt;
ccc9c027 1269 break;
4eed87de 1270 }
ccc9c027
L		 1271 }
1272
76bc74dc
L		 1273 if (patt == f32_patt)
1274 {
1275 /* If the padding is less than 15 bytes, we use the normal
1276 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1277 its offset. */
1278 int limit;
76ba9986 1279
711eedef
L		 1280 /* For 64bit, the limit is 3 bytes. */
1281 if (flag_code == CODE_64BIT
1282 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1283 limit = 3;
1284 else
1285 limit = 15;
1286 if (count < limit)
76bc74dc
L		 1287 memcpy (fragP->fr_literal + fragP->fr_fix,
1288 patt[count - 1], count);
1289 else
1290 {
1291 memcpy (fragP->fr_literal + fragP->fr_fix,
1292 jump_31, count);
1293 /* Adjust jump offset. */
1294 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1295 }
1296 }
1297 else
1298 {
80b8656c
L		 1299 /* Maximum length of an instruction is 10 byte. If the
1300 padding is greater than 10 bytes and we don't use jump,
76bc74dc
L		 1301 we have to break it into smaller pieces. */
1302 int padding = count;
80b8656c 1303 while (padding > 10)
76bc74dc 1304 {
80b8656c 1305 padding -= 10;
76bc74dc 1306 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
80b8656c 1307 patt [9], 10);
76bc74dc
L		 1308 }
1309
1310 if (padding)
1311 memcpy (fragP->fr_literal + fragP->fr_fix,
1312 patt [padding - 1], padding);
1313 }
ccc9c027 1314 }
33fef721 1315 fragP->fr_var = count;
252b5132
RH		 1316}
1317
c6fb90c8 1318static INLINE int
0dfbf9d7 1319operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1320{
0dfbf9d7 1321 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1322 {
1323 case 3:
0dfbf9d7 1324 if (x->array[2])
c6fb90c8
L		 1325 return 0;
1326 case 2:
0dfbf9d7 1327 if (x->array[1])
c6fb90c8
L		 1328 return 0;
1329 case 1:
0dfbf9d7 1330 return !x->array[0];
c6fb90c8
L		 1331 default:
1332 abort ();
1333 }
40fb9820
L		 1334}
1335
c6fb90c8 1336static INLINE void
0dfbf9d7 1337operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1338{
0dfbf9d7 1339 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1340 {
1341 case 3:
0dfbf9d7 1342 x->array[2] = v;
c6fb90c8 1343 case 2:
0dfbf9d7 1344 x->array[1] = v;
c6fb90c8 1345 case 1:
0dfbf9d7 1346 x->array[0] = v;
c6fb90c8
L		 1347 break;
1348 default:
1349 abort ();
1350 }
1351}
40fb9820 1352
c6fb90c8 1353static INLINE int
0dfbf9d7
L		 1354operand_type_equal (const union i386_operand_type *x,
1355 const union i386_operand_type *y)
c6fb90c8 1356{
0dfbf9d7 1357 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1358 {
1359 case 3:
0dfbf9d7 1360 if (x->array[2] != y->array[2])
c6fb90c8
L		 1361 return 0;
1362 case 2:
0dfbf9d7 1363 if (x->array[1] != y->array[1])
c6fb90c8
L		 1364 return 0;
1365 case 1:
0dfbf9d7 1366 return x->array[0] == y->array[0];
c6fb90c8
L		 1367 break;
1368 default:
1369 abort ();
1370 }
1371}
40fb9820 1372
0dfbf9d7
L		 1373static INLINE int
1374cpu_flags_all_zero (const union i386_cpu_flags *x)
1375{
1376 switch (ARRAY_SIZE(x->array))
1377 {
1378 case 3:
1379 if (x->array[2])
1380 return 0;
1381 case 2:
1382 if (x->array[1])
1383 return 0;
1384 case 1:
1385 return !x->array[0];
1386 default:
1387 abort ();
1388 }
1389}
1390
0dfbf9d7
L		 1391static INLINE int
1392cpu_flags_equal (const union i386_cpu_flags *x,
1393 const union i386_cpu_flags *y)
1394{
1395 switch (ARRAY_SIZE(x->array))
1396 {
1397 case 3:
1398 if (x->array[2] != y->array[2])
1399 return 0;
1400 case 2:
1401 if (x->array[1] != y->array[1])
1402 return 0;
1403 case 1:
1404 return x->array[0] == y->array[0];
1405 break;
1406 default:
1407 abort ();
1408 }
1409}
c6fb90c8
L		 1410
1411static INLINE int
1412cpu_flags_check_cpu64 (i386_cpu_flags f)
1413{
1414 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1415 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1416}
1417
c6fb90c8
L		 1418static INLINE i386_cpu_flags
1419cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1420{
c6fb90c8
L		 1421 switch (ARRAY_SIZE (x.array))
1422 {
1423 case 3:
1424 x.array [2] &= y.array [2];
1425 case 2:
1426 x.array [1] &= y.array [1];
1427 case 1:
1428 x.array [0] &= y.array [0];
1429 break;
1430 default:
1431 abort ();
1432 }
1433 return x;
1434}
40fb9820 1435
c6fb90c8
L		 1436static INLINE i386_cpu_flags
1437cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1438{
c6fb90c8 1439 switch (ARRAY_SIZE (x.array))
40fb9820 1440 {
c6fb90c8
L		 1441 case 3:
1442 x.array [2] |= y.array [2];
1443 case 2:
1444 x.array [1] |= y.array [1];
1445 case 1:
1446 x.array [0] |= y.array [0];
40fb9820
L		 1447 break;
1448 default:
1449 abort ();
1450 }
40fb9820
L		 1451 return x;
1452}
1453
309d3373
JB		 1454static INLINE i386_cpu_flags
1455cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1456{
1457 switch (ARRAY_SIZE (x.array))
1458 {
1459 case 3:
1460 x.array [2] &= ~y.array [2];
1461 case 2:
1462 x.array [1] &= ~y.array [1];
1463 case 1:
1464 x.array [0] &= ~y.array [0];
1465 break;
1466 default:
1467 abort ();
1468 }
1469 return x;
1470}
1471
81486035
L		 1472static int
1473valid_iamcu_cpu_flags (const i386_cpu_flags *flags)
1474{
1475 if (cpu_arch_isa == PROCESSOR_IAMCU)
1476 {
1477 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_COMPAT_FLAGS;
1478 i386_cpu_flags compat_flags;
1479 compat_flags = cpu_flags_and_not (*flags, iamcu_flags);
1480 return cpu_flags_all_zero (&compat_flags);
1481 }
1482 else
1483 return 1;
1484}
1485
c0f3af97
L		 1486#define CPU_FLAGS_ARCH_MATCH 0x1
1487#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1488#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1489#define CPU_FLAGS_PCLMUL_MATCH 0x8
1490#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1491
a5ff0eb2 1492#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1493 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1494 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1495#define CPU_FLAGS_PERFECT_MATCH \
1496 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1497
1498/* Return CPU flags match bits. */
3629bb00 1499
40fb9820 1500static int
d3ce72d0 1501cpu_flags_match (const insn_template *t)
40fb9820 1502{
c0f3af97
L		 1503 i386_cpu_flags x = t->cpu_flags;
1504 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1505
1506 x.bitfield.cpu64 = 0;
1507 x.bitfield.cpuno64 = 0;
1508
0dfbf9d7 1509 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1510 {
1511 /* This instruction is available on all archs. */
1512 match |= CPU_FLAGS_32BIT_MATCH;
1513 }
3629bb00
L		 1514 else
1515 {
c0f3af97 1516 /* This instruction is available only on some archs. */
3629bb00
L		 1517 i386_cpu_flags cpu = cpu_arch_flags;
1518
1519 cpu.bitfield.cpu64 = 0;
1520 cpu.bitfield.cpuno64 = 0;
1521 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1522 if (!cpu_flags_all_zero (&cpu))
1523 {
a5ff0eb2
L		 1524 if (x.bitfield.cpuavx)
1525 {
ce2f5b3c 1526 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1527 if (cpu.bitfield.cpuavx)
1528 {
1529 /* Check SSE2AVX. */
1530 if (!t->opcode_modifier.sse2avx|| sse2avx)
1531 {
1532 match |= (CPU_FLAGS_ARCH_MATCH
1533 | CPU_FLAGS_AVX_MATCH);
1534 /* Check AES. */
1535 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1536 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1537 /* Check PCLMUL. */
1538 if (!x.bitfield.cpupclmul
1539 || cpu.bitfield.cpupclmul)
1540 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1541 }
1542 }
1543 else
1544 match |= CPU_FLAGS_ARCH_MATCH;
1545 }
1546 else
c0f3af97
L		 1547 match |= CPU_FLAGS_32BIT_MATCH;
1548 }
3629bb00 1549 }
c0f3af97 1550 return match;
40fb9820
L		 1551}
1552
c6fb90c8
L		 1553static INLINE i386_operand_type
1554operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1555{
c6fb90c8
L		 1556 switch (ARRAY_SIZE (x.array))
1557 {
1558 case 3:
1559 x.array [2] &= y.array [2];
1560 case 2:
1561 x.array [1] &= y.array [1];
1562 case 1:
1563 x.array [0] &= y.array [0];
1564 break;
1565 default:
1566 abort ();
1567 }
1568 return x;
40fb9820
L		 1569}
1570
c6fb90c8
L		 1571static INLINE i386_operand_type
1572operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1573{
c6fb90c8 1574 switch (ARRAY_SIZE (x.array))
40fb9820 1575 {
c6fb90c8
L		 1576 case 3:
1577 x.array [2] |= y.array [2];
1578 case 2:
1579 x.array [1] |= y.array [1];
1580 case 1:
1581 x.array [0] |= y.array [0];
40fb9820
L		 1582 break;
1583 default:
1584 abort ();
1585 }
c6fb90c8
L		 1586 return x;
1587}
40fb9820 1588
c6fb90c8
L		 1589static INLINE i386_operand_type
1590operand_type_xor (i386_operand_type x, i386_operand_type y)
1591{
1592 switch (ARRAY_SIZE (x.array))
1593 {
1594 case 3:
1595 x.array [2] ^= y.array [2];
1596 case 2:
1597 x.array [1] ^= y.array [1];
1598 case 1:
1599 x.array [0] ^= y.array [0];
1600 break;
1601 default:
1602 abort ();
1603 }
40fb9820
L		 1604 return x;
1605}
1606
1607static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1608static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1609static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1610static const i386_operand_type inoutportreg
1611 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1612static const i386_operand_type reg16_inoutportreg
1613 = OPERAND_TYPE_REG16_INOUTPORTREG;
1614static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1615static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1616static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1617static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1618static const i386_operand_type anydisp
1619 = OPERAND_TYPE_ANYDISP;
40fb9820 1620static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1621static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1622static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1623static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1624static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1625static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1626static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1627static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1628static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1629static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1630static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1631static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1632static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1633static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1634
1635enum operand_type
1636{
1637 reg,
40fb9820
L		 1638 imm,
1639 disp,
1640 anymem
1641};
1642
c6fb90c8 1643static INLINE int
40fb9820
L		 1644operand_type_check (i386_operand_type t, enum operand_type c)
1645{
1646 switch (c)
1647 {
1648 case reg:
1649 return (t.bitfield.reg8
1650 || t.bitfield.reg16
1651 || t.bitfield.reg32
1652 || t.bitfield.reg64);
1653
40fb9820
L		 1654 case imm:
1655 return (t.bitfield.imm8
1656 || t.bitfield.imm8s
1657 || t.bitfield.imm16
1658 || t.bitfield.imm32
1659 || t.bitfield.imm32s
1660 || t.bitfield.imm64);
1661
1662 case disp:
1663 return (t.bitfield.disp8
1664 || t.bitfield.disp16
1665 || t.bitfield.disp32
1666 || t.bitfield.disp32s
1667 || t.bitfield.disp64);
1668
1669 case anymem:
1670 return (t.bitfield.disp8
1671 || t.bitfield.disp16
1672 || t.bitfield.disp32
1673 || t.bitfield.disp32s
1674 || t.bitfield.disp64
1675 || t.bitfield.baseindex);
1676
1677 default:
1678 abort ();
1679 }
2cfe26b6
AM		 1680
1681 return 0;
40fb9820
L		 1682}
1683
5c07affc
L		 1684/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1685 operand J for instruction template T. */
1686
1687static INLINE int
d3ce72d0 1688match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1689{
1690 return !((i.types[j].bitfield.byte
1691 && !t->operand_types[j].bitfield.byte)
1692 || (i.types[j].bitfield.word
1693 && !t->operand_types[j].bitfield.word)
1694 || (i.types[j].bitfield.dword
1695 && !t->operand_types[j].bitfield.dword)
1696 || (i.types[j].bitfield.qword
1697 && !t->operand_types[j].bitfield.qword));
1698}
1699
1700/* Return 1 if there is no conflict in any size on operand J for
1701 instruction template T. */
1702
1703static INLINE int
d3ce72d0 1704match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1705{
1706 return (match_reg_size (t, j)
1707 && !((i.types[j].bitfield.unspecified
af508cb9 1708 && !i.broadcast
5c07affc
L		 1709 && !t->operand_types[j].bitfield.unspecified)
1710 || (i.types[j].bitfield.fword
1711 && !t->operand_types[j].bitfield.fword)
1712 || (i.types[j].bitfield.tbyte
1713 && !t->operand_types[j].bitfield.tbyte)
1714 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1715 && !t->operand_types[j].bitfield.xmmword)
1716 || (i.types[j].bitfield.ymmword
43234a1e
L		 1717 && !t->operand_types[j].bitfield.ymmword)
1718 || (i.types[j].bitfield.zmmword
1719 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1720}
1721
1722/* Return 1 if there is no size conflict on any operands for
1723 instruction template T. */
1724
1725static INLINE int
d3ce72d0 1726operand_size_match (const insn_template *t)
5c07affc
L		 1727{
1728 unsigned int j;
1729 int match = 1;
1730
1731 /* Don't check jump instructions. */
1732 if (t->opcode_modifier.jump
1733 || t->opcode_modifier.jumpbyte
1734 || t->opcode_modifier.jumpdword
1735 || t->opcode_modifier.jumpintersegment)
1736 return match;
1737
1738 /* Check memory and accumulator operand size. */
1739 for (j = 0; j < i.operands; j++)
1740 {
1741 if (t->operand_types[j].bitfield.anysize)
1742 continue;
1743
1744 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1745 {
1746 match = 0;
1747 break;
1748 }
1749
1750 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1751 {
1752 match = 0;
1753 break;
1754 }
1755 }
1756
891edac4 1757 if (match)
5c07affc 1758 return match;
891edac4
L		 1759 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1760 {
1761mismatch:
86e026a4 1762 i.error = operand_size_mismatch;
891edac4
L		 1763 return 0;
1764 }
5c07affc
L		 1765
1766 /* Check reverse. */
9c2799c2 1767 gas_assert (i.operands == 2);
5c07affc
L		 1768
1769 match = 1;
1770 for (j = 0; j < 2; j++)
1771 {
1772 if (t->operand_types[j].bitfield.acc
1773 && !match_reg_size (t, j ? 0 : 1))
891edac4 1774 goto mismatch;
5c07affc
L		 1775
1776 if (i.types[j].bitfield.mem
1777 && !match_mem_size (t, j ? 0 : 1))
891edac4 1778 goto mismatch;
5c07affc
L		 1779 }
1780
1781 return match;
1782}
1783
c6fb90c8 1784static INLINE int
40fb9820
L		 1785operand_type_match (i386_operand_type overlap,
1786 i386_operand_type given)
1787{
1788 i386_operand_type temp = overlap;
1789
1790 temp.bitfield.jumpabsolute = 0;
7d5e4556 1791 temp.bitfield.unspecified = 0;
5c07affc
L		 1792 temp.bitfield.byte = 0;
1793 temp.bitfield.word = 0;
1794 temp.bitfield.dword = 0;
1795 temp.bitfield.fword = 0;
1796 temp.bitfield.qword = 0;
1797 temp.bitfield.tbyte = 0;
1798 temp.bitfield.xmmword = 0;
c0f3af97 1799 temp.bitfield.ymmword = 0;
43234a1e 1800 temp.bitfield.zmmword = 0;
0dfbf9d7 1801 if (operand_type_all_zero (&temp))
891edac4 1802 goto mismatch;
40fb9820 1803
891edac4
L		 1804 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1805 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1806 return 1;
1807
1808mismatch:
a65babc9 1809 i.error = operand_type_mismatch;
891edac4 1810 return 0;
40fb9820
L		 1811}
1812
7d5e4556 1813/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1814 unless the expected operand type register overlap is null.
1815 Note that Acc in a template matches every size of reg. */
1816
c6fb90c8 1817static INLINE int
40fb9820
L		 1818operand_type_register_match (i386_operand_type m0,
1819 i386_operand_type g0,
1820 i386_operand_type t0,
1821 i386_operand_type m1,
1822 i386_operand_type g1,
1823 i386_operand_type t1)
1824{
1825 if (!operand_type_check (g0, reg))
1826 return 1;
1827
1828 if (!operand_type_check (g1, reg))
1829 return 1;
1830
1831 if (g0.bitfield.reg8 == g1.bitfield.reg8
1832 && g0.bitfield.reg16 == g1.bitfield.reg16
1833 && g0.bitfield.reg32 == g1.bitfield.reg32
1834 && g0.bitfield.reg64 == g1.bitfield.reg64)
1835 return 1;
1836
1837 if (m0.bitfield.acc)
1838 {
1839 t0.bitfield.reg8 = 1;
1840 t0.bitfield.reg16 = 1;
1841 t0.bitfield.reg32 = 1;
1842 t0.bitfield.reg64 = 1;
1843 }
1844
1845 if (m1.bitfield.acc)
1846 {
1847 t1.bitfield.reg8 = 1;
1848 t1.bitfield.reg16 = 1;
1849 t1.bitfield.reg32 = 1;
1850 t1.bitfield.reg64 = 1;
1851 }
1852
891edac4
L		 1853 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1854 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1855 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1856 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1857 return 1;
1858
a65babc9 1859 i.error = register_type_mismatch;
891edac4
L		 1860
1861 return 0;
40fb9820
L		 1862}
1863
4c692bc7
JB		 1864static INLINE unsigned int
1865register_number (const reg_entry *r)
1866{
1867 unsigned int nr = r->reg_num;
1868
1869 if (r->reg_flags & RegRex)
1870 nr += 8;
1871
1872 return nr;
1873}
1874
252b5132 1875static INLINE unsigned int
40fb9820 1876mode_from_disp_size (i386_operand_type t)
252b5132 1877{
43234a1e 1878 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1879 return 1;
1880 else if (t.bitfield.disp16
1881 || t.bitfield.disp32
1882 || t.bitfield.disp32s)
1883 return 2;
1884 else
1885 return 0;
252b5132
RH		 1886}
1887
1888static INLINE int
65879393 1889fits_in_signed_byte (addressT num)
252b5132 1890{
65879393 1891 return num + 0x80 <= 0xff;
47926f60 1892}
252b5132
RH		 1893
1894static INLINE int
65879393 1895fits_in_unsigned_byte (addressT num)
252b5132 1896{
65879393 1897 return num <= 0xff;
47926f60 1898}
252b5132
RH		 1899
1900static INLINE int
65879393 1901fits_in_unsigned_word (addressT num)
252b5132 1902{
65879393 1903 return num <= 0xffff;
47926f60 1904}
252b5132
RH		 1905
1906static INLINE int
65879393 1907fits_in_signed_word (addressT num)
252b5132 1908{
65879393 1909 return num + 0x8000 <= 0xffff;
47926f60 1910}
2a962e6d 1911
3e73aa7c 1912static INLINE int
65879393 1913fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1914{
1915#ifndef BFD64
1916 return 1;
1917#else
65879393 1918 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 1919#endif
1920} /* fits_in_signed_long() */
2a962e6d 1921
3e73aa7c 1922static INLINE int
65879393 1923fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1924{
1925#ifndef BFD64
1926 return 1;
1927#else
65879393 1928 return num <= 0xffffffff;
3e73aa7c
JH		 1929#endif
1930} /* fits_in_unsigned_long() */
252b5132 1931
43234a1e
L		 1932static INLINE int
1933fits_in_vec_disp8 (offsetT num)
1934{
1935 int shift = i.memshift;
1936 unsigned int mask;
1937
1938 if (shift == -1)
1939 abort ();
1940
1941 mask = (1 << shift) - 1;
1942
1943 /* Return 0 if NUM isn't properly aligned. */
1944 if ((num & mask))
1945 return 0;
1946
1947 /* Check if NUM will fit in 8bit after shift. */
1948 return fits_in_signed_byte (num >> shift);
1949}
1950
a683cc34
SP		 1951static INLINE int
1952fits_in_imm4 (offsetT num)
1953{
1954 return (num & 0xf) == num;
1955}
1956
40fb9820 1957static i386_operand_type
e3bb37b5 1958smallest_imm_type (offsetT num)
252b5132 1959{
40fb9820 1960 i386_operand_type t;
7ab9ffdd 1961
0dfbf9d7 1962 operand_type_set (&t, 0);
40fb9820
L		 1963 t.bitfield.imm64 = 1;
1964
1965 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1966 {
1967 /* This code is disabled on the 486 because all the Imm1 forms
1968 in the opcode table are slower on the i486. They're the
1969 versions with the implicitly specified single-position
1970 displacement, which has another syntax if you really want to
1971 use that form. */
40fb9820
L		 1972 t.bitfield.imm1 = 1;
1973 t.bitfield.imm8 = 1;
1974 t.bitfield.imm8s = 1;
1975 t.bitfield.imm16 = 1;
1976 t.bitfield.imm32 = 1;
1977 t.bitfield.imm32s = 1;
1978 }
1979 else if (fits_in_signed_byte (num))
1980 {
1981 t.bitfield.imm8 = 1;
1982 t.bitfield.imm8s = 1;
1983 t.bitfield.imm16 = 1;
1984 t.bitfield.imm32 = 1;
1985 t.bitfield.imm32s = 1;
1986 }
1987 else if (fits_in_unsigned_byte (num))
1988 {
1989 t.bitfield.imm8 = 1;
1990 t.bitfield.imm16 = 1;
1991 t.bitfield.imm32 = 1;
1992 t.bitfield.imm32s = 1;
1993 }
1994 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1995 {
1996 t.bitfield.imm16 = 1;
1997 t.bitfield.imm32 = 1;
1998 t.bitfield.imm32s = 1;
1999 }
2000 else if (fits_in_signed_long (num))
2001 {
2002 t.bitfield.imm32 = 1;
2003 t.bitfield.imm32s = 1;
2004 }
2005 else if (fits_in_unsigned_long (num))
2006 t.bitfield.imm32 = 1;
2007
2008 return t;
47926f60 2009}
252b5132 2010
847f7ad4 2011static offsetT
e3bb37b5 2012offset_in_range (offsetT val, int size)
847f7ad4 2013{
508866be 2014 addressT mask;
ba2adb93 2015
847f7ad4
AM		 2016 switch (size)
2017 {
508866be
L		 2018 case 1: mask = ((addressT) 1 << 8) - 1; break;
2019 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2020 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2021#ifdef BFD64
2022 case 8: mask = ((addressT) 2 << 63) - 1; break;
2023#endif
47926f60 2024 default: abort ();
847f7ad4
AM		 2025 }
2026
9de868bf
L		 2027#ifdef BFD64
2028 /* If BFD64, sign extend val for 32bit address mode. */
2029 if (flag_code != CODE_64BIT
2030 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2031 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2032 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2033#endif
ba2adb93 2034
47926f60 2035 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2036 {
2037 char buf1[40], buf2[40];
2038
2039 sprint_value (buf1, val);
2040 sprint_value (buf2, val & mask);
2041 as_warn (_("%s shortened to %s"), buf1, buf2);
2042 }
2043 return val & mask;
2044}
2045
c32fa91d
L		 2046enum PREFIX_GROUP
2047{
2048 PREFIX_EXIST = 0,
2049 PREFIX_LOCK,
2050 PREFIX_REP,
2051 PREFIX_OTHER
2052};
2053
2054/* Returns
2055 a. PREFIX_EXIST if attempting to add a prefix where one from the
2056 same class already exists.
2057 b. PREFIX_LOCK if lock prefix is added.
2058 c. PREFIX_REP if rep/repne prefix is added.
2059 d. PREFIX_OTHER if other prefix is added.
2060 */
2061
2062static enum PREFIX_GROUP
e3bb37b5 2063add_prefix (unsigned int prefix)
252b5132 2064{
c32fa91d 2065 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2066 unsigned int q;
252b5132 2067
29b0f896
AM		 2068 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2069 && flag_code == CODE_64BIT)
b1905489 2070 {
161a04f6
L		 2071 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2072 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2073 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2074 ret = PREFIX_EXIST;
b1905489
JB		 2075 q = REX_PREFIX;
2076 }
3e73aa7c 2077 else
b1905489
JB		 2078 {
2079 switch (prefix)
2080 {
2081 default:
2082 abort ();
2083
2084 case CS_PREFIX_OPCODE:
2085 case DS_PREFIX_OPCODE:
2086 case ES_PREFIX_OPCODE:
2087 case FS_PREFIX_OPCODE:
2088 case GS_PREFIX_OPCODE:
2089 case SS_PREFIX_OPCODE:
2090 q = SEG_PREFIX;
2091 break;
2092
2093 case REPNE_PREFIX_OPCODE:
2094 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2095 q = REP_PREFIX;
2096 ret = PREFIX_REP;
2097 break;
2098
b1905489 2099 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2100 q = LOCK_PREFIX;
2101 ret = PREFIX_LOCK;
b1905489
JB		 2102 break;
2103
2104 case FWAIT_OPCODE:
2105 q = WAIT_PREFIX;
2106 break;
2107
2108 case ADDR_PREFIX_OPCODE:
2109 q = ADDR_PREFIX;
2110 break;
2111
2112 case DATA_PREFIX_OPCODE:
2113 q = DATA_PREFIX;
2114 break;
2115 }
2116 if (i.prefix[q] != 0)
c32fa91d 2117 ret = PREFIX_EXIST;
b1905489 2118 }
252b5132 2119
b1905489 2120 if (ret)
252b5132 2121 {
b1905489
JB		 2122 if (!i.prefix[q])
2123 ++i.prefixes;
2124 i.prefix[q] |= prefix;
252b5132 2125 }
b1905489
JB		 2126 else
2127 as_bad (_("same type of prefix used twice"));
252b5132 2128
252b5132
RH		 2129 return ret;
2130}
2131
2132static void
78f12dd3 2133update_code_flag (int value, int check)
eecb386c 2134{
78f12dd3
L		 2135 PRINTF_LIKE ((*as_error));
2136
1e9cc1c2 2137 flag_code = (enum flag_code) value;
40fb9820
L		 2138 if (flag_code == CODE_64BIT)
2139 {
2140 cpu_arch_flags.bitfield.cpu64 = 1;
2141 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2142 }
2143 else
2144 {
2145 cpu_arch_flags.bitfield.cpu64 = 0;
2146 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2147 }
2148 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2149 {
78f12dd3
L		 2150 if (check)
2151 as_error = as_fatal;
2152 else
2153 as_error = as_bad;
2154 (*as_error) (_("64bit mode not supported on `%s'."),
2155 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2156 }
40fb9820 2157 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2158 {
78f12dd3
L		 2159 if (check)
2160 as_error = as_fatal;
2161 else
2162 as_error = as_bad;
2163 (*as_error) (_("32bit mode not supported on `%s'."),
2164 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2165 }
eecb386c
AM		 2166 stackop_size = '\0';
2167}
2168
78f12dd3
L		 2169static void
2170set_code_flag (int value)
2171{
2172 update_code_flag (value, 0);
2173}
2174
eecb386c 2175static void
e3bb37b5 2176set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2177{
1e9cc1c2 2178 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2179 if (flag_code != CODE_16BIT)
2180 abort ();
2181 cpu_arch_flags.bitfield.cpu64 = 0;
2182 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2183 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2184}
2185
2186static void
e3bb37b5 2187set_intel_syntax (int syntax_flag)
252b5132
RH		 2188{
2189 /* Find out if register prefixing is specified. */
2190 int ask_naked_reg = 0;
2191
2192 SKIP_WHITESPACE ();
29b0f896 2193 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2194 {
d02603dc
NC		 2195 char *string;
2196 int e = get_symbol_name (&string);
252b5132 2197
47926f60 2198 if (strcmp (string, "prefix") == 0)
252b5132 2199 ask_naked_reg = 1;
47926f60 2200 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2201 ask_naked_reg = -1;
2202 else
d0b47220 2203 as_bad (_("bad argument to syntax directive."));
d02603dc 2204 (void) restore_line_pointer (e);
252b5132
RH		 2205 }
2206 demand_empty_rest_of_line ();
c3332e24 2207
252b5132
RH		 2208 intel_syntax = syntax_flag;
2209
2210 if (ask_naked_reg == 0)
f86103b7
AM		 2211 allow_naked_reg = (intel_syntax
2212 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2213 else
2214 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2215
ee86248c 2216 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2217
e4a3b5a4 2218 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2219 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2220 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2221}
2222
1efbbeb4
L		 2223static void
2224set_intel_mnemonic (int mnemonic_flag)
2225{
e1d4d893 2226 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2227}
2228
db51cc60
L		 2229static void
2230set_allow_index_reg (int flag)
2231{
2232 allow_index_reg = flag;
2233}
2234
cb19c032 2235static void
7bab8ab5 2236set_check (int what)
cb19c032 2237{
7bab8ab5
JB		 2238 enum check_kind *kind;
2239 const char *str;
2240
2241 if (what)
2242 {
2243 kind = &operand_check;
2244 str = "operand";
2245 }
2246 else
2247 {
2248 kind = &sse_check;
2249 str = "sse";
2250 }
2251
cb19c032
L		 2252 SKIP_WHITESPACE ();
2253
2254 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2255 {
d02603dc
NC		 2256 char *string;
2257 int e = get_symbol_name (&string);
cb19c032
L		 2258
2259 if (strcmp (string, "none") == 0)
7bab8ab5 2260 *kind = check_none;
cb19c032 2261 else if (strcmp (string, "warning") == 0)
7bab8ab5 2262 *kind = check_warning;
cb19c032 2263 else if (strcmp (string, "error") == 0)
7bab8ab5 2264 *kind = check_error;
cb19c032 2265 else
7bab8ab5 2266 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2267 (void) restore_line_pointer (e);
cb19c032
L		 2268 }
2269 else
7bab8ab5 2270 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2271
2272 demand_empty_rest_of_line ();
2273}
2274
8a9036a4
L		 2275static void
2276check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2277 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2278{
2279#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2280 static const char *arch;
2281
2282 /* Intel LIOM is only supported on ELF. */
2283 if (!IS_ELF)
2284 return;
2285
2286 if (!arch)
2287 {
2288 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2289 use default_arch. */
2290 arch = cpu_arch_name;
2291 if (!arch)
2292 arch = default_arch;
2293 }
2294
81486035
L		 2295 /* If we are targeting Intel MCU, we must enable it. */
2296 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2297 || new_flag.bitfield.cpuiamcu)
2298 return;
2299
3632d14b 2300 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2301 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2302 || new_flag.bitfield.cpul1om)
8a9036a4 2303 return;
76ba9986 2304
7a9068fe
L		 2305 /* If we are targeting Intel K1OM, we must enable it. */
2306 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2307 || new_flag.bitfield.cpuk1om)
2308 return;
2309
8a9036a4
L		 2310 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2311#endif
2312}
2313
e413e4e9 2314static void
e3bb37b5 2315set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2316{
47926f60 2317 SKIP_WHITESPACE ();
e413e4e9 2318
29b0f896 2319 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2320 {
d02603dc
NC		 2321 char *string;
2322 int e = get_symbol_name (&string);
91d6fa6a 2323 unsigned int j;
40fb9820 2324 i386_cpu_flags flags;
e413e4e9 2325
91d6fa6a 2326 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2327 {
91d6fa6a 2328 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2329 {
91d6fa6a 2330 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2331
5c6af06e
JB		 2332 if (*string != '.')
2333 {
91d6fa6a 2334 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2335 cpu_sub_arch_name = NULL;
91d6fa6a 2336 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2337 if (flag_code == CODE_64BIT)
2338 {
2339 cpu_arch_flags.bitfield.cpu64 = 1;
2340 cpu_arch_flags.bitfield.cpuno64 = 0;
2341 }
2342 else
2343 {
2344 cpu_arch_flags.bitfield.cpu64 = 0;
2345 cpu_arch_flags.bitfield.cpuno64 = 1;
2346 }
91d6fa6a
NC		 2347 cpu_arch_isa = cpu_arch[j].type;
2348 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2349 if (!cpu_arch_tune_set)
2350 {
2351 cpu_arch_tune = cpu_arch_isa;
2352 cpu_arch_tune_flags = cpu_arch_isa_flags;
2353 }
5c6af06e
JB		 2354 break;
2355 }
40fb9820 2356
22109423 2357 if (!cpu_arch[j].negated)
309d3373 2358 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2359 cpu_arch[j].flags);
309d3373
JB		 2360 else
2361 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2362 cpu_arch[j].flags);
81486035
L		 2363
2364 if (!valid_iamcu_cpu_flags (&flags))
2365 as_fatal (_("`%s' isn't valid for Intel MCU"),
2366 cpu_arch[j].name);
2367 else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2368 {
6305a203
L		 2369 if (cpu_sub_arch_name)
2370 {
2371 char *name = cpu_sub_arch_name;
2372 cpu_sub_arch_name = concat (name,
91d6fa6a 2373 cpu_arch[j].name,
1bf57e9f 2374 (const char *) NULL);
6305a203
L		 2375 free (name);
2376 }
2377 else
91d6fa6a 2378 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2379 cpu_arch_flags = flags;
a586129e 2380 cpu_arch_isa_flags = flags;
5c6af06e 2381 }
d02603dc 2382 (void) restore_line_pointer (e);
5c6af06e
JB		 2383 demand_empty_rest_of_line ();
2384 return;
e413e4e9
AM		 2385 }
2386 }
91d6fa6a 2387 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2388 as_bad (_("no such architecture: `%s'"), string);
2389
2390 *input_line_pointer = e;
2391 }
2392 else
2393 as_bad (_("missing cpu architecture"));
2394
fddf5b5b
AM		 2395 no_cond_jump_promotion = 0;
2396 if (*input_line_pointer == ','
29b0f896 2397 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2398 {
d02603dc
NC		 2399 char *string;
2400 char e;
2401
2402 ++input_line_pointer;
2403 e = get_symbol_name (&string);
fddf5b5b
AM		 2404
2405 if (strcmp (string, "nojumps") == 0)
2406 no_cond_jump_promotion = 1;
2407 else if (strcmp (string, "jumps") == 0)
2408 ;
2409 else
2410 as_bad (_("no such architecture modifier: `%s'"), string);
2411
d02603dc 2412 (void) restore_line_pointer (e);
fddf5b5b
AM		 2413 }
2414
e413e4e9
AM		 2415 demand_empty_rest_of_line ();
2416}
2417
8a9036a4
L		 2418enum bfd_architecture
2419i386_arch (void)
2420{
3632d14b 2421 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2422 {
2423 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2424 || flag_code != CODE_64BIT)
2425 as_fatal (_("Intel L1OM is 64bit ELF only"));
2426 return bfd_arch_l1om;
2427 }
7a9068fe
L		 2428 else if (cpu_arch_isa == PROCESSOR_K1OM)
2429 {
2430 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2431 || flag_code != CODE_64BIT)
2432 as_fatal (_("Intel K1OM is 64bit ELF only"));
2433 return bfd_arch_k1om;
2434 }
81486035
L		 2435 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2436 {
2437 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2438 || flag_code == CODE_64BIT)
2439 as_fatal (_("Intel MCU is 32bit ELF only"));
2440 return bfd_arch_iamcu;
2441 }
8a9036a4
L		 2442 else
2443 return bfd_arch_i386;
2444}
2445
b9d79e03 2446unsigned long
7016a5d5 2447i386_mach (void)
b9d79e03 2448{
351f65ca 2449 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2450 {
3632d14b 2451 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2452 {
351f65ca
L		 2453 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2454 || default_arch[6] != '\0')
8a9036a4
L		 2455 as_fatal (_("Intel L1OM is 64bit ELF only"));
2456 return bfd_mach_l1om;
2457 }
7a9068fe
L		 2458 else if (cpu_arch_isa == PROCESSOR_K1OM)
2459 {
2460 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2461 || default_arch[6] != '\0')
2462 as_fatal (_("Intel K1OM is 64bit ELF only"));
2463 return bfd_mach_k1om;
2464 }
351f65ca 2465 else if (default_arch[6] == '\0')
8a9036a4 2466 return bfd_mach_x86_64;
351f65ca
L		 2467 else
2468 return bfd_mach_x64_32;
8a9036a4 2469 }
5197d474
L		 2470 else if (!strcmp (default_arch, "i386")
2471 || !strcmp (default_arch, "iamcu"))
81486035
L		 2472 {
2473 if (cpu_arch_isa == PROCESSOR_IAMCU)
2474 {
2475 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2476 as_fatal (_("Intel MCU is 32bit ELF only"));
2477 return bfd_mach_i386_iamcu;
2478 }
2479 else
2480 return bfd_mach_i386_i386;
2481 }
b9d79e03 2482 else
2b5d6a91 2483 as_fatal (_("unknown architecture"));
b9d79e03 2484}
b9d79e03 2485\f
252b5132 2486void
7016a5d5 2487md_begin (void)
252b5132
RH		 2488{
2489 const char *hash_err;
2490
47926f60 2491 /* Initialize op_hash hash table. */
252b5132
RH		 2492 op_hash = hash_new ();
2493
2494 {
d3ce72d0 2495 const insn_template *optab;
29b0f896 2496 templates *core_optab;
252b5132 2497
47926f60
KH		 2498 /* Setup for loop. */
2499 optab = i386_optab;
252b5132
RH		 2500 core_optab = (templates *) xmalloc (sizeof (templates));
2501 core_optab->start = optab;
2502
2503 while (1)
2504 {
2505 ++optab;
2506 if (optab->name == NULL
2507 || strcmp (optab->name, (optab - 1)->name) != 0)
2508 {
2509 /* different name --> ship out current template list;
47926f60 2510 add to hash table; & begin anew. */
252b5132
RH		 2511 core_optab->end = optab;
2512 hash_err = hash_insert (op_hash,
2513 (optab - 1)->name,
5a49b8ac 2514 (void *) core_optab);
252b5132
RH		 2515 if (hash_err)
2516 {
b37df7c4 2517 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2518 (optab - 1)->name,
2519 hash_err);
2520 }
2521 if (optab->name == NULL)
2522 break;
2523 core_optab = (templates *) xmalloc (sizeof (templates));
2524 core_optab->start = optab;
2525 }
2526 }
2527 }
2528
47926f60 2529 /* Initialize reg_hash hash table. */
252b5132
RH		 2530 reg_hash = hash_new ();
2531 {
29b0f896 2532 const reg_entry *regtab;
c3fe08fa 2533 unsigned int regtab_size = i386_regtab_size;
252b5132 2534
c3fe08fa 2535 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2536 {
5a49b8ac 2537 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2538 if (hash_err)
b37df7c4 2539 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2540 regtab->reg_name,
2541 hash_err);
252b5132
RH		 2542 }
2543 }
2544
47926f60 2545 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2546 {
29b0f896
AM		 2547 int c;
2548 char *p;
252b5132
RH		 2549
2550 for (c = 0; c < 256; c++)
2551 {
3882b010 2552 if (ISDIGIT (c))
252b5132
RH		 2553 {
2554 digit_chars[c] = c;
2555 mnemonic_chars[c] = c;
2556 register_chars[c] = c;
2557 operand_chars[c] = c;
2558 }
3882b010 2559 else if (ISLOWER (c))
252b5132
RH		 2560 {
2561 mnemonic_chars[c] = c;
2562 register_chars[c] = c;
2563 operand_chars[c] = c;
2564 }
3882b010 2565 else if (ISUPPER (c))
252b5132 2566 {
3882b010 2567 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2568 register_chars[c] = mnemonic_chars[c];
2569 operand_chars[c] = c;
2570 }
43234a1e
L		 2571 else if (c == '{' || c == '}')
2572 operand_chars[c] = c;
252b5132 2573
3882b010 2574 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2575 identifier_chars[c] = c;
2576 else if (c >= 128)
2577 {
2578 identifier_chars[c] = c;
2579 operand_chars[c] = c;
2580 }
2581 }
2582
2583#ifdef LEX_AT
2584 identifier_chars['@'] = '@';
32137342
NC		 2585#endif
2586#ifdef LEX_QM
2587 identifier_chars['?'] = '?';
2588 operand_chars['?'] = '?';
252b5132 2589#endif
252b5132 2590 digit_chars['-'] = '-';
c0f3af97 2591 mnemonic_chars['_'] = '_';
791fe849 2592 mnemonic_chars['-'] = '-';
0003779b 2593 mnemonic_chars['.'] = '.';
252b5132
RH		 2594 identifier_chars['_'] = '_';
2595 identifier_chars['.'] = '.';
2596
2597 for (p = operand_special_chars; *p != '\0'; p++)
2598 operand_chars[(unsigned char) *p] = *p;
2599 }
2600
a4447b93
RH		 2601 if (flag_code == CODE_64BIT)
2602 {
ca19b261
KT		 2603#if defined (OBJ_COFF) && defined (TE_PE)
2604 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2605 ? 32 : 16);
2606#else
a4447b93 2607 x86_dwarf2_return_column = 16;
ca19b261 2608#endif
61ff971f 2609 x86_cie_data_alignment = -8;
a4447b93
RH		 2610 }
2611 else
2612 {
2613 x86_dwarf2_return_column = 8;
2614 x86_cie_data_alignment = -4;
2615 }
252b5132
RH		 2616}
2617
2618void
e3bb37b5 2619i386_print_statistics (FILE *file)
252b5132
RH		 2620{
2621 hash_print_statistics (file, "i386 opcode", op_hash);
2622 hash_print_statistics (file, "i386 register", reg_hash);
2623}
2624\f
252b5132
RH		 2625#ifdef DEBUG386
2626
ce8a8b2f 2627/* Debugging routines for md_assemble. */
d3ce72d0 2628static void pte (insn_template *);
40fb9820 2629static void pt (i386_operand_type);
e3bb37b5
L		 2630static void pe (expressionS *);
2631static void ps (symbolS *);
252b5132
RH		 2632
2633static void
e3bb37b5 2634pi (char *line, i386_insn *x)
252b5132 2635{
09137c09 2636 unsigned int j;
252b5132
RH		 2637
2638 fprintf (stdout, "%s: template ", line);
2639 pte (&x->tm);
09f131f2
JH		 2640 fprintf (stdout, " address: base %s index %s scale %x\n",
2641 x->base_reg ? x->base_reg->reg_name : "none",
2642 x->index_reg ? x->index_reg->reg_name : "none",
2643 x->log2_scale_factor);
2644 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2645 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2646 fprintf (stdout, " sib: base %x index %x scale %x\n",
2647 x->sib.base, x->sib.index, x->sib.scale);
2648 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2649 (x->rex & REX_W) != 0,
2650 (x->rex & REX_R) != 0,
2651 (x->rex & REX_X) != 0,
2652 (x->rex & REX_B) != 0);
09137c09 2653 for (j = 0; j < x->operands; j++)
252b5132 2654 {
09137c09
SP		 2655 fprintf (stdout, " #%d: ", j + 1);
2656 pt (x->types[j]);
252b5132 2657 fprintf (stdout, "\n");
09137c09
SP		 2658 if (x->types[j].bitfield.reg8
2659 || x->types[j].bitfield.reg16
2660 || x->types[j].bitfield.reg32
2661 || x->types[j].bitfield.reg64
2662 || x->types[j].bitfield.regmmx
2663 || x->types[j].bitfield.regxmm
2664 || x->types[j].bitfield.regymm
43234a1e 2665 || x->types[j].bitfield.regzmm
09137c09
SP		 2666 || x->types[j].bitfield.sreg2
2667 || x->types[j].bitfield.sreg3
2668 || x->types[j].bitfield.control
2669 || x->types[j].bitfield.debug
2670 || x->types[j].bitfield.test)
2671 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2672 if (operand_type_check (x->types[j], imm))
2673 pe (x->op[j].imms);
2674 if (operand_type_check (x->types[j], disp))
2675 pe (x->op[j].disps);
252b5132
RH		 2676 }
2677}
2678
2679static void
d3ce72d0 2680pte (insn_template *t)
252b5132 2681{
09137c09 2682 unsigned int j;
252b5132 2683 fprintf (stdout, " %d operands ", t->operands);
47926f60 2684 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2685 if (t->extension_opcode != None)
2686 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2687 if (t->opcode_modifier.d)
252b5132 2688 fprintf (stdout, "D");
40fb9820 2689 if (t->opcode_modifier.w)
252b5132
RH		 2690 fprintf (stdout, "W");
2691 fprintf (stdout, "\n");
09137c09 2692 for (j = 0; j < t->operands; j++)
252b5132 2693 {
09137c09
SP		 2694 fprintf (stdout, " #%d type ", j + 1);
2695 pt (t->operand_types[j]);
252b5132
RH		 2696 fprintf (stdout, "\n");
2697 }
2698}
2699
2700static void
e3bb37b5 2701pe (expressionS *e)
252b5132 2702{
24eab124 2703 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2704 fprintf (stdout, " add_number %ld (%lx)\n",
2705 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2706 if (e->X_add_symbol)
2707 {
2708 fprintf (stdout, " add_symbol ");
2709 ps (e->X_add_symbol);
2710 fprintf (stdout, "\n");
2711 }
2712 if (e->X_op_symbol)
2713 {
2714 fprintf (stdout, " op_symbol ");
2715 ps (e->X_op_symbol);
2716 fprintf (stdout, "\n");
2717 }
2718}
2719
2720static void
e3bb37b5 2721ps (symbolS *s)
252b5132
RH		 2722{
2723 fprintf (stdout, "%s type %s%s",
2724 S_GET_NAME (s),
2725 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2726 segment_name (S_GET_SEGMENT (s)));
2727}
2728
7b81dfbb 2729static struct type_name
252b5132 2730 {
40fb9820
L		 2731 i386_operand_type mask;
2732 const char *name;
252b5132 2733 }
7b81dfbb 2734const type_names[] =
252b5132 2735{
40fb9820
L		 2736 { OPERAND_TYPE_REG8, "r8" },
2737 { OPERAND_TYPE_REG16, "r16" },
2738 { OPERAND_TYPE_REG32, "r32" },
2739 { OPERAND_TYPE_REG64, "r64" },
2740 { OPERAND_TYPE_IMM8, "i8" },
2741 { OPERAND_TYPE_IMM8, "i8s" },
2742 { OPERAND_TYPE_IMM16, "i16" },
2743 { OPERAND_TYPE_IMM32, "i32" },
2744 { OPERAND_TYPE_IMM32S, "i32s" },
2745 { OPERAND_TYPE_IMM64, "i64" },
2746 { OPERAND_TYPE_IMM1, "i1" },
2747 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2748 { OPERAND_TYPE_DISP8, "d8" },
2749 { OPERAND_TYPE_DISP16, "d16" },
2750 { OPERAND_TYPE_DISP32, "d32" },
2751 { OPERAND_TYPE_DISP32S, "d32s" },
2752 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2753 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2754 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2755 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2756 { OPERAND_TYPE_CONTROL, "control reg" },
2757 { OPERAND_TYPE_TEST, "test reg" },
2758 { OPERAND_TYPE_DEBUG, "debug reg" },
2759 { OPERAND_TYPE_FLOATREG, "FReg" },
2760 { OPERAND_TYPE_FLOATACC, "FAcc" },
2761 { OPERAND_TYPE_SREG2, "SReg2" },
2762 { OPERAND_TYPE_SREG3, "SReg3" },
2763 { OPERAND_TYPE_ACC, "Acc" },
2764 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2765 { OPERAND_TYPE_REGMMX, "rMMX" },
2766 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2767 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2768 { OPERAND_TYPE_REGZMM, "rZMM" },
2769 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2770 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2771};
2772
2773static void
40fb9820 2774pt (i386_operand_type t)
252b5132 2775{
40fb9820 2776 unsigned int j;
c6fb90c8 2777 i386_operand_type a;
252b5132 2778
40fb9820 2779 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2780 {
2781 a = operand_type_and (t, type_names[j].mask);
0349dc08 2782 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2783 fprintf (stdout, "%s, ", type_names[j].name);
2784 }
252b5132
RH		 2785 fflush (stdout);
2786}
2787
2788#endif /* DEBUG386 */
2789\f
252b5132 2790static bfd_reloc_code_real_type
3956db08 2791reloc (unsigned int size,
64e74474
AM		 2792 int pcrel,
2793 int sign,
2794 bfd_reloc_code_real_type other)
252b5132 2795{
47926f60 2796 if (other != NO_RELOC)
3956db08 2797 {
91d6fa6a 2798 reloc_howto_type *rel;
3956db08
JB		 2799
2800 if (size == 8)
2801 switch (other)
2802 {
64e74474
AM		 2803 case BFD_RELOC_X86_64_GOT32:
2804 return BFD_RELOC_X86_64_GOT64;
2805 break;
553d1284
L		 2806 case BFD_RELOC_X86_64_GOTPLT64:
2807 return BFD_RELOC_X86_64_GOTPLT64;
2808 break;
64e74474
AM		 2809 case BFD_RELOC_X86_64_PLTOFF64:
2810 return BFD_RELOC_X86_64_PLTOFF64;
2811 break;
2812 case BFD_RELOC_X86_64_GOTPC32:
2813 other = BFD_RELOC_X86_64_GOTPC64;
2814 break;
2815 case BFD_RELOC_X86_64_GOTPCREL:
2816 other = BFD_RELOC_X86_64_GOTPCREL64;
2817 break;
2818 case BFD_RELOC_X86_64_TPOFF32:
2819 other = BFD_RELOC_X86_64_TPOFF64;
2820 break;
2821 case BFD_RELOC_X86_64_DTPOFF32:
2822 other = BFD_RELOC_X86_64_DTPOFF64;
2823 break;
2824 default:
2825 break;
3956db08 2826 }
e05278af 2827
8ce3d284 2828#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2829 if (other == BFD_RELOC_SIZE32)
2830 {
2831 if (size == 8)
1ab668bf 2832 other = BFD_RELOC_SIZE64;
8fd4256d 2833 if (pcrel)
1ab668bf
AM		 2834 {
2835 as_bad (_("there are no pc-relative size relocations"));
2836 return NO_RELOC;
2837 }
8fd4256d 2838 }
8ce3d284 2839#endif
8fd4256d 2840
e05278af 2841 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2842 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2843 sign = -1;
2844
91d6fa6a
NC		 2845 rel = bfd_reloc_type_lookup (stdoutput, other);
2846 if (!rel)
3956db08 2847 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2848 else if (size != bfd_get_reloc_size (rel))
3956db08 2849 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2850 bfd_get_reloc_size (rel),
3956db08 2851 size);
91d6fa6a 2852 else if (pcrel && !rel->pc_relative)
3956db08 2853 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2854 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2855 && !sign)
91d6fa6a 2856 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2857 && sign > 0))
3956db08
JB		 2858 as_bad (_("relocated field and relocation type differ in signedness"));
2859 else
2860 return other;
2861 return NO_RELOC;
2862 }
252b5132
RH		 2863
2864 if (pcrel)
2865 {
3e73aa7c 2866 if (!sign)
3956db08 2867 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2868 switch (size)
2869 {
2870 case 1: return BFD_RELOC_8_PCREL;
2871 case 2: return BFD_RELOC_16_PCREL;
d258b828 2872 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2873 case 8: return BFD_RELOC_64_PCREL;
252b5132 2874 }
3956db08 2875 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2876 }
2877 else
2878 {
3956db08 2879 if (sign > 0)
e5cb08ac 2880 switch (size)
3e73aa7c
JH		 2881 {
2882 case 4: return BFD_RELOC_X86_64_32S;
2883 }
2884 else
2885 switch (size)
2886 {
2887 case 1: return BFD_RELOC_8;
2888 case 2: return BFD_RELOC_16;
2889 case 4: return BFD_RELOC_32;
2890 case 8: return BFD_RELOC_64;
2891 }
3956db08
JB		 2892 as_bad (_("cannot do %s %u byte relocation"),
2893 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2894 }
2895
0cc9e1d3 2896 return NO_RELOC;
252b5132
RH		 2897}
2898
47926f60
KH		 2899/* Here we decide which fixups can be adjusted to make them relative to
2900 the beginning of the section instead of the symbol. Basically we need
2901 to make sure that the dynamic relocations are done correctly, so in
2902 some cases we force the original symbol to be used. */
2903
252b5132 2904int
e3bb37b5 2905tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2906{
6d249963 2907#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2908 if (!IS_ELF)
31312f95
AM		 2909 return 1;
2910
a161fe53
AM		 2911 /* Don't adjust pc-relative references to merge sections in 64-bit
2912 mode. */
2913 if (use_rela_relocations
2914 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2915 && fixP->fx_pcrel)
252b5132 2916 return 0;
31312f95 2917
8d01d9a9
AJ		 2918 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2919 and changed later by validate_fix. */
2920 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2921 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2922 return 0;
2923
8fd4256d
L		 2924 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2925 for size relocations. */
2926 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2927 || fixP->fx_r_type == BFD_RELOC_SIZE64
2928 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2929 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2930 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 2931 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 2932 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2933 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2934 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2935 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2936 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2937 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2938 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2939 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2940 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2941 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2942 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2943 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2944 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2945 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2946 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2947 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2948 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2949 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2950 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2951 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2952 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2953 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2954 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2955 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2956 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2957 return 0;
31312f95 2958#endif
252b5132
RH		 2959 return 1;
2960}
252b5132 2961
b4cac588 2962static int
e3bb37b5 2963intel_float_operand (const char *mnemonic)
252b5132 2964{
9306ca4a
JB		 2965 /* Note that the value returned is meaningful only for opcodes with (memory)
2966 operands, hence the code here is free to improperly handle opcodes that
2967 have no operands (for better performance and smaller code). */
2968
2969 if (mnemonic[0] != 'f')
2970 return 0; /* non-math */
2971
2972 switch (mnemonic[1])
2973 {
2974 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2975 the fs segment override prefix not currently handled because no
2976 call path can make opcodes without operands get here */
2977 case 'i':
2978 return 2 /* integer op */;
2979 case 'l':
2980 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2981 return 3; /* fldcw/fldenv */
2982 break;
2983 case 'n':
2984 if (mnemonic[2] != 'o' /* fnop */)
2985 return 3; /* non-waiting control op */
2986 break;
2987 case 'r':
2988 if (mnemonic[2] == 's')
2989 return 3; /* frstor/frstpm */
2990 break;
2991 case 's':
2992 if (mnemonic[2] == 'a')
2993 return 3; /* fsave */
2994 if (mnemonic[2] == 't')
2995 {
2996 switch (mnemonic[3])
2997 {
2998 case 'c': /* fstcw */
2999 case 'd': /* fstdw */
3000 case 'e': /* fstenv */
3001 case 's': /* fsts[gw] */
3002 return 3;
3003 }
3004 }
3005 break;
3006 case 'x':
3007 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3008 return 0; /* fxsave/fxrstor are not really math ops */
3009 break;
3010 }
252b5132 3011
9306ca4a 3012 return 1;
252b5132
RH		 3013}
3014
c0f3af97
L		 3015/* Build the VEX prefix. */
3016
3017static void
d3ce72d0 3018build_vex_prefix (const insn_template *t)
c0f3af97
L		 3019{
3020 unsigned int register_specifier;
3021 unsigned int implied_prefix;
3022 unsigned int vector_length;
3023
3024 /* Check register specifier. */
3025 if (i.vex.register_specifier)
43234a1e
L		 3026 {
3027 register_specifier =
3028 ~register_number (i.vex.register_specifier) & 0xf;
3029 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3030 }
c0f3af97
L		 3031 else
3032 register_specifier = 0xf;
3033
fa99fab2
L		 3034 /* Use 2-byte VEX prefix by swappping destination and source
3035 operand. */
3036 if (!i.swap_operand
3037 && i.operands == i.reg_operands
7f399153 3038 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3039 && i.tm.opcode_modifier.s
3040 && i.rex == REX_B)
3041 {
3042 unsigned int xchg = i.operands - 1;
3043 union i386_op temp_op;
3044 i386_operand_type temp_type;
3045
3046 temp_type = i.types[xchg];
3047 i.types[xchg] = i.types[0];
3048 i.types[0] = temp_type;
3049 temp_op = i.op[xchg];
3050 i.op[xchg] = i.op[0];
3051 i.op[0] = temp_op;
3052
9c2799c2 3053 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3054
3055 i.rex = REX_R;
3056 xchg = i.rm.regmem;
3057 i.rm.regmem = i.rm.reg;
3058 i.rm.reg = xchg;
3059
3060 /* Use the next insn. */
3061 i.tm = t[1];
3062 }
3063
539f890d
L		 3064 if (i.tm.opcode_modifier.vex == VEXScalar)
3065 vector_length = avxscalar;
3066 else
3067 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3068
3069 switch ((i.tm.base_opcode >> 8) & 0xff)
3070 {
3071 case 0:
3072 implied_prefix = 0;
3073 break;
3074 case DATA_PREFIX_OPCODE:
3075 implied_prefix = 1;
3076 break;
3077 case REPE_PREFIX_OPCODE:
3078 implied_prefix = 2;
3079 break;
3080 case REPNE_PREFIX_OPCODE:
3081 implied_prefix = 3;
3082 break;
3083 default:
3084 abort ();
3085 }
3086
3087 /* Use 2-byte VEX prefix if possible. */
7f399153 3088 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3089 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3090 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3091 {
3092 /* 2-byte VEX prefix. */
3093 unsigned int r;
3094
3095 i.vex.length = 2;
3096 i.vex.bytes[0] = 0xc5;
3097
3098 /* Check the REX.R bit. */
3099 r = (i.rex & REX_R) ? 0 : 1;
3100 i.vex.bytes[1] = (r << 7
3101 | register_specifier << 3
3102 | vector_length << 2
3103 | implied_prefix);
3104 }
3105 else
3106 {
3107 /* 3-byte VEX prefix. */
3108 unsigned int m, w;
3109
f88c9eb0 3110 i.vex.length = 3;
f88c9eb0 3111
7f399153 3112 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3113 {
7f399153
L		 3114 case VEX0F:
3115 m = 0x1;
80de6e00 3116 i.vex.bytes[0] = 0xc4;
7f399153
L		 3117 break;
3118 case VEX0F38:
3119 m = 0x2;
80de6e00 3120 i.vex.bytes[0] = 0xc4;
7f399153
L		 3121 break;
3122 case VEX0F3A:
3123 m = 0x3;
80de6e00 3124 i.vex.bytes[0] = 0xc4;
7f399153
L		 3125 break;
3126 case XOP08:
5dd85c99
SP		 3127 m = 0x8;
3128 i.vex.bytes[0] = 0x8f;
7f399153
L		 3129 break;
3130 case XOP09:
f88c9eb0
SP		 3131 m = 0x9;
3132 i.vex.bytes[0] = 0x8f;
7f399153
L		 3133 break;
3134 case XOP0A:
f88c9eb0
SP		 3135 m = 0xa;
3136 i.vex.bytes[0] = 0x8f;
7f399153
L		 3137 break;
3138 default:
3139 abort ();
f88c9eb0 3140 }
c0f3af97 3141
c0f3af97
L		 3142 /* The high 3 bits of the second VEX byte are 1's compliment
3143 of RXB bits from REX. */
3144 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3145
3146 /* Check the REX.W bit. */
3147 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3148 if (i.tm.opcode_modifier.vexw == VEXW1)
3149 w = 1;
c0f3af97
L		 3150
3151 i.vex.bytes[2] = (w << 7
3152 | register_specifier << 3
3153 | vector_length << 2
3154 | implied_prefix);
3155 }
3156}
3157
43234a1e
L		 3158/* Build the EVEX prefix. */
3159
3160static void
3161build_evex_prefix (void)
3162{
3163 unsigned int register_specifier;
3164 unsigned int implied_prefix;
3165 unsigned int m, w;
3166 rex_byte vrex_used = 0;
3167
3168 /* Check register specifier. */
3169 if (i.vex.register_specifier)
3170 {
3171 gas_assert ((i.vrex & REX_X) == 0);
3172
3173 register_specifier = i.vex.register_specifier->reg_num;
3174 if ((i.vex.register_specifier->reg_flags & RegRex))
3175 register_specifier += 8;
3176 /* The upper 16 registers are encoded in the fourth byte of the
3177 EVEX prefix. */
3178 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3179 i.vex.bytes[3] = 0x8;
3180 register_specifier = ~register_specifier & 0xf;
3181 }
3182 else
3183 {
3184 register_specifier = 0xf;
3185
3186 /* Encode upper 16 vector index register in the fourth byte of
3187 the EVEX prefix. */
3188 if (!(i.vrex & REX_X))
3189 i.vex.bytes[3] = 0x8;
3190 else
3191 vrex_used |= REX_X;
3192 }
3193
3194 switch ((i.tm.base_opcode >> 8) & 0xff)
3195 {
3196 case 0:
3197 implied_prefix = 0;
3198 break;
3199 case DATA_PREFIX_OPCODE:
3200 implied_prefix = 1;
3201 break;
3202 case REPE_PREFIX_OPCODE:
3203 implied_prefix = 2;
3204 break;
3205 case REPNE_PREFIX_OPCODE:
3206 implied_prefix = 3;
3207 break;
3208 default:
3209 abort ();
3210 }
3211
3212 /* 4 byte EVEX prefix. */
3213 i.vex.length = 4;
3214 i.vex.bytes[0] = 0x62;
3215
3216 /* mmmm bits. */
3217 switch (i.tm.opcode_modifier.vexopcode)
3218 {
3219 case VEX0F:
3220 m = 1;
3221 break;
3222 case VEX0F38:
3223 m = 2;
3224 break;
3225 case VEX0F3A:
3226 m = 3;
3227 break;
3228 default:
3229 abort ();
3230 break;
3231 }
3232
3233 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3234 bits from REX. */
3235 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3236
3237 /* The fifth bit of the second EVEX byte is 1's compliment of the
3238 REX_R bit in VREX. */
3239 if (!(i.vrex & REX_R))
3240 i.vex.bytes[1] |= 0x10;
3241 else
3242 vrex_used |= REX_R;
3243
3244 if ((i.reg_operands + i.imm_operands) == i.operands)
3245 {
3246 /* When all operands are registers, the REX_X bit in REX is not
3247 used. We reuse it to encode the upper 16 registers, which is
3248 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3249 as 1's compliment. */
3250 if ((i.vrex & REX_B))
3251 {
3252 vrex_used |= REX_B;
3253 i.vex.bytes[1] &= ~0x40;
3254 }
3255 }
3256
3257 /* EVEX instructions shouldn't need the REX prefix. */
3258 i.vrex &= ~vrex_used;
3259 gas_assert (i.vrex == 0);
3260
3261 /* Check the REX.W bit. */
3262 w = (i.rex & REX_W) ? 1 : 0;
3263 if (i.tm.opcode_modifier.vexw)
3264 {
3265 if (i.tm.opcode_modifier.vexw == VEXW1)
3266 w = 1;
3267 }
3268 /* If w is not set it means we are dealing with WIG instruction. */
3269 else if (!w)
3270 {
3271 if (evexwig == evexw1)
3272 w = 1;
3273 }
3274
3275 /* Encode the U bit. */
3276 implied_prefix |= 0x4;
3277
3278 /* The third byte of the EVEX prefix. */
3279 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3280
3281 /* The fourth byte of the EVEX prefix. */
3282 /* The zeroing-masking bit. */
3283 if (i.mask && i.mask->zeroing)
3284 i.vex.bytes[3] |= 0x80;
3285
3286 /* Don't always set the broadcast bit if there is no RC. */
3287 if (!i.rounding)
3288 {
3289 /* Encode the vector length. */
3290 unsigned int vec_length;
3291
3292 switch (i.tm.opcode_modifier.evex)
3293 {
3294 case EVEXLIG: /* LL' is ignored */
3295 vec_length = evexlig << 5;
3296 break;
3297 case EVEX128:
3298 vec_length = 0 << 5;
3299 break;
3300 case EVEX256:
3301 vec_length = 1 << 5;
3302 break;
3303 case EVEX512:
3304 vec_length = 2 << 5;
3305 break;
3306 default:
3307 abort ();
3308 break;
3309 }
3310 i.vex.bytes[3] |= vec_length;
3311 /* Encode the broadcast bit. */
3312 if (i.broadcast)
3313 i.vex.bytes[3] |= 0x10;
3314 }
3315 else
3316 {
3317 if (i.rounding->type != saeonly)
3318 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3319 else
d3d3c6db 3320 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3321 }
3322
3323 if (i.mask && i.mask->mask)
3324 i.vex.bytes[3] |= i.mask->mask->reg_num;
3325}
3326
65da13b5
L		 3327static void
3328process_immext (void)
3329{
3330 expressionS *exp;
3331
4c692bc7
JB		 3332 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3333 && i.operands > 0)
65da13b5 3334 {
4c692bc7
JB		 3335 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3336 with an opcode suffix which is coded in the same place as an
3337 8-bit immediate field would be.
3338 Here we check those operands and remove them afterwards. */
65da13b5
L		 3339 unsigned int x;
3340
3341 for (x = 0; x < i.operands; x++)
4c692bc7 3342 if (register_number (i.op[x].regs) != x)
65da13b5 3343 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3344 register_prefix, i.op[x].regs->reg_name, x + 1,
3345 i.tm.name);
3346
3347 i.operands = 0;
65da13b5
L		 3348 }
3349
9916071f
AP		 3350 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3351 {
3352 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3353 suffix which is coded in the same place as an 8-bit immediate
3354 field would be.
3355 Here we check those operands and remove them afterwards. */
3356 unsigned int x;
3357
3358 if (i.operands != 3)
3359 abort();
3360
3361 for (x = 0; x < 2; x++)
3362 if (register_number (i.op[x].regs) != x)
3363 goto bad_register_operand;
3364
3365 /* Check for third operand for mwaitx/monitorx insn. */
3366 if (register_number (i.op[x].regs)
3367 != (x + (i.tm.extension_opcode == 0xfb)))
3368 {
3369bad_register_operand:
3370 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3371 register_prefix, i.op[x].regs->reg_name, x+1,
3372 i.tm.name);
3373 }
3374
3375 i.operands = 0;
3376 }
3377
c0f3af97 3378 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3379 which is coded in the same place as an 8-bit immediate field
3380 would be. Here we fake an 8-bit immediate operand from the
3381 opcode suffix stored in tm.extension_opcode.
3382
c1e679ec 3383 AVX instructions also use this encoding, for some of
c0f3af97 3384 3 argument instructions. */
65da13b5 3385
43234a1e 3386 gas_assert (i.imm_operands <= 1
7ab9ffdd 3387 && (i.operands <= 2
43234a1e
L		 3388 || ((i.tm.opcode_modifier.vex
3389 || i.tm.opcode_modifier.evex)
7ab9ffdd 3390 && i.operands <= 4)));
65da13b5
L		 3391
3392 exp = &im_expressions[i.imm_operands++];
3393 i.op[i.operands].imms = exp;
3394 i.types[i.operands] = imm8;
3395 i.operands++;
3396 exp->X_op = O_constant;
3397 exp->X_add_number = i.tm.extension_opcode;
3398 i.tm.extension_opcode = None;
3399}
3400
42164a71
L		 3401
3402static int
3403check_hle (void)
3404{
3405 switch (i.tm.opcode_modifier.hleprefixok)
3406 {
3407 default:
3408 abort ();
82c2def5 3409 case HLEPrefixNone:
165de32a
L		 3410 as_bad (_("invalid instruction `%s' after `%s'"),
3411 i.tm.name, i.hle_prefix);
42164a71 3412 return 0;
82c2def5 3413 case HLEPrefixLock:
42164a71
L		 3414 if (i.prefix[LOCK_PREFIX])
3415 return 1;
165de32a 3416 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3417 return 0;
82c2def5 3418 case HLEPrefixAny:
42164a71 3419 return 1;
82c2def5 3420 case HLEPrefixRelease:
42164a71
L		 3421 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3422 {
3423 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3424 i.tm.name);
3425 return 0;
3426 }
3427 if (i.mem_operands == 0
3428 || !operand_type_check (i.types[i.operands - 1], anymem))
3429 {
3430 as_bad (_("memory destination needed for instruction `%s'"
3431 " after `xrelease'"), i.tm.name);
3432 return 0;
3433 }
3434 return 1;
3435 }
3436}
3437
252b5132
RH		 3438/* This is the guts of the machine-dependent assembler. LINE points to a
3439 machine dependent instruction. This function is supposed to emit
3440 the frags/bytes it assembles to. */
3441
3442void
65da13b5 3443md_assemble (char *line)
252b5132 3444{
40fb9820 3445 unsigned int j;
252b5132 3446 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3447 const insn_template *t;
252b5132 3448
47926f60 3449 /* Initialize globals. */
252b5132
RH		 3450 memset (&i, '\0', sizeof (i));
3451 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3452 i.reloc[j] = NO_RELOC;
252b5132
RH		 3453 memset (disp_expressions, '\0', sizeof (disp_expressions));
3454 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3455 save_stack_p = save_stack;
252b5132
RH		 3456
3457 /* First parse an instruction mnemonic & call i386_operand for the operands.
3458 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3459 start of a (possibly prefixed) mnemonic. */
252b5132 3460
29b0f896
AM		 3461 line = parse_insn (line, mnemonic);
3462 if (line == NULL)
3463 return;
252b5132 3464
29b0f896 3465 line = parse_operands (line, mnemonic);
ee86248c 3466 this_operand = -1;
29b0f896
AM		 3467 if (line == NULL)
3468 return;
252b5132 3469
29b0f896
AM		 3470 /* Now we've parsed the mnemonic into a set of templates, and have the
3471 operands at hand. */
3472
3473 /* All intel opcodes have reversed operands except for "bound" and
3474 "enter". We also don't reverse intersegment "jmp" and "call"
3475 instructions with 2 immediate operands so that the immediate segment
050dfa73 3476 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3477 if (intel_syntax
3478 && i.operands > 1
29b0f896 3479 && (strcmp (mnemonic, "bound") != 0)
30123838 3480 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3481 && !(operand_type_check (i.types[0], imm)
3482 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3483 swap_operands ();
3484
ec56d5c0
JB		 3485 /* The order of the immediates should be reversed
3486 for 2 immediates extrq and insertq instructions */
3487 if (i.imm_operands == 2
3488 && (strcmp (mnemonic, "extrq") == 0
3489 || strcmp (mnemonic, "insertq") == 0))
3490 swap_2_operands (0, 1);
3491
29b0f896
AM		 3492 if (i.imm_operands)
3493 optimize_imm ();
3494
b300c311
L		 3495 /* Don't optimize displacement for movabs since it only takes 64bit
3496 displacement. */
3497 if (i.disp_operands
a501d77e 3498 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3499 && (flag_code != CODE_64BIT
3500 || strcmp (mnemonic, "movabs") != 0))
3501 optimize_disp ();
29b0f896
AM		 3502
3503 /* Next, we find a template that matches the given insn,
3504 making sure the overlap of the given operands types is consistent
3505 with the template operand types. */
252b5132 3506
fa99fab2 3507 if (!(t = match_template ()))
29b0f896 3508 return;
252b5132 3509
7bab8ab5 3510 if (sse_check != check_none
81f8a913 3511 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3512 && (i.tm.cpu_flags.bitfield.cpusse
3513 || i.tm.cpu_flags.bitfield.cpusse2
3514 || i.tm.cpu_flags.bitfield.cpusse3
3515 || i.tm.cpu_flags.bitfield.cpussse3
3516 || i.tm.cpu_flags.bitfield.cpusse4_1
3517 || i.tm.cpu_flags.bitfield.cpusse4_2))
3518 {
7bab8ab5 3519 (sse_check == check_warning
daf50ae7
L		 3520 ? as_warn
3521 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3522 }
3523
321fd21e
L		 3524 /* Zap movzx and movsx suffix. The suffix has been set from
3525 "word ptr" or "byte ptr" on the source operand in Intel syntax
3526 or extracted from mnemonic in AT&T syntax. But we'll use
3527 the destination register to choose the suffix for encoding. */
3528 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3529 {
321fd21e
L		 3530 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3531 there is no suffix, the default will be byte extension. */
3532 if (i.reg_operands != 2
3533 && !i.suffix
7ab9ffdd 3534 && intel_syntax)
321fd21e
L		 3535 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3536
3537 i.suffix = 0;
cd61ebfe 3538 }
24eab124 3539
40fb9820 3540 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3541 if (!add_prefix (FWAIT_OPCODE))
3542 return;
252b5132 3543
d5de92cf
L		 3544 /* Check if REP prefix is OK. */
3545 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3546 {
3547 as_bad (_("invalid instruction `%s' after `%s'"),
3548 i.tm.name, i.rep_prefix);
3549 return;
3550 }
3551
c1ba0266
L		 3552 /* Check for lock without a lockable instruction. Destination operand
3553 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3554 if (i.prefix[LOCK_PREFIX]
3555 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3556 || i.mem_operands == 0
3557 || (i.tm.base_opcode != 0x86
3558 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3559 {
3560 as_bad (_("expecting lockable instruction after `lock'"));
3561 return;
3562 }
3563
42164a71 3564 /* Check if HLE prefix is OK. */
165de32a 3565 if (i.hle_prefix && !check_hle ())
42164a71
L		 3566 return;
3567
7e8b059b
L		 3568 /* Check BND prefix. */
3569 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3570 as_bad (_("expecting valid branch instruction after `bnd'"));
3571
3572 if (i.tm.cpu_flags.bitfield.cpumpx
3573 && flag_code == CODE_64BIT
3574 && i.prefix[ADDR_PREFIX])
3575 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3576
3577 /* Insert BND prefix. */
3578 if (add_bnd_prefix
3579 && i.tm.opcode_modifier.bndprefixok
3580 && !i.prefix[BND_PREFIX])
3581 add_prefix (BND_PREFIX_OPCODE);
3582
29b0f896 3583 /* Check string instruction segment overrides. */
40fb9820 3584 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3585 {
3586 if (!check_string ())
5dd0794d 3587 return;
fc0763e6 3588 i.disp_operands = 0;
29b0f896 3589 }
5dd0794d 3590
29b0f896
AM		 3591 if (!process_suffix ())
3592 return;
e413e4e9 3593
bc0844ae
L		 3594 /* Update operand types. */
3595 for (j = 0; j < i.operands; j++)
3596 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3597
29b0f896
AM		 3598 /* Make still unresolved immediate matches conform to size of immediate
3599 given in i.suffix. */
3600 if (!finalize_imm ())
3601 return;
252b5132 3602
40fb9820 3603 if (i.types[0].bitfield.imm1)
29b0f896 3604 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3605
9afe6eb8
L		 3606 /* We only need to check those implicit registers for instructions
3607 with 3 operands or less. */
3608 if (i.operands <= 3)
3609 for (j = 0; j < i.operands; j++)
3610 if (i.types[j].bitfield.inoutportreg
3611 || i.types[j].bitfield.shiftcount
3612 || i.types[j].bitfield.acc
3613 || i.types[j].bitfield.floatacc)
3614 i.reg_operands--;
40fb9820 3615
c0f3af97
L		 3616 /* ImmExt should be processed after SSE2AVX. */
3617 if (!i.tm.opcode_modifier.sse2avx
3618 && i.tm.opcode_modifier.immext)
65da13b5 3619 process_immext ();
252b5132 3620
29b0f896
AM		 3621 /* For insns with operands there are more diddles to do to the opcode. */
3622 if (i.operands)
3623 {
3624 if (!process_operands ())
3625 return;
3626 }
40fb9820 3627 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3628 {
3629 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3630 as_warn (_("translating to `%sp'"), i.tm.name);
3631 }
252b5132 3632
9e5e5283
L		 3633 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3634 {
3635 if (flag_code == CODE_16BIT)
3636 {
3637 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3638 i.tm.name);
3639 return;
3640 }
c0f3af97 3641
9e5e5283
L		 3642 if (i.tm.opcode_modifier.vex)
3643 build_vex_prefix (t);
3644 else
3645 build_evex_prefix ();
3646 }
43234a1e 3647
5dd85c99
SP		 3648 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3649 instructions may define INT_OPCODE as well, so avoid this corner
3650 case for those instructions that use MODRM. */
3651 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3652 && !i.tm.opcode_modifier.modrm
3653 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3654 {
3655 i.tm.base_opcode = INT3_OPCODE;
3656 i.imm_operands = 0;
3657 }
252b5132 3658
40fb9820
L		 3659 if ((i.tm.opcode_modifier.jump
3660 || i.tm.opcode_modifier.jumpbyte
3661 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3662 && i.op[0].disps->X_op == O_constant)
3663 {
3664 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3665 the absolute address given by the constant. Since ix86 jumps and
3666 calls are pc relative, we need to generate a reloc. */
3667 i.op[0].disps->X_add_symbol = &abs_symbol;
3668 i.op[0].disps->X_op = O_symbol;
3669 }
252b5132 3670
40fb9820 3671 if (i.tm.opcode_modifier.rex64)
161a04f6 3672 i.rex |= REX_W;
252b5132 3673
29b0f896
AM		 3674 /* For 8 bit registers we need an empty rex prefix. Also if the
3675 instruction already has a prefix, we need to convert old
3676 registers to new ones. */
773f551c 3677
40fb9820 3678 if ((i.types[0].bitfield.reg8
29b0f896 3679 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3680 || (i.types[1].bitfield.reg8
29b0f896 3681 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3682 || ((i.types[0].bitfield.reg8
3683 || i.types[1].bitfield.reg8)
29b0f896
AM		 3684 && i.rex != 0))
3685 {
3686 int x;
726c5dcd 3687
29b0f896
AM		 3688 i.rex |= REX_OPCODE;
3689 for (x = 0; x < 2; x++)
3690 {
3691 /* Look for 8 bit operand that uses old registers. */
40fb9820 3692 if (i.types[x].bitfield.reg8
29b0f896 3693 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3694 {
29b0f896
AM		 3695 /* In case it is "hi" register, give up. */
3696 if (i.op[x].regs->reg_num > 3)
a540244d 3697 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3698 "instruction requiring REX prefix."),
a540244d 3699 register_prefix, i.op[x].regs->reg_name);
773f551c 3700
29b0f896
AM		 3701 /* Otherwise it is equivalent to the extended register.
3702 Since the encoding doesn't change this is merely
3703 cosmetic cleanup for debug output. */
3704
3705 i.op[x].regs = i.op[x].regs + 8;
773f551c 3706 }
29b0f896
AM		 3707 }
3708 }
773f551c 3709
7ab9ffdd 3710 if (i.rex != 0)
29b0f896
AM		 3711 add_prefix (REX_OPCODE | i.rex);
3712
3713 /* We are ready to output the insn. */
3714 output_insn ();
3715}
3716
3717static char *
e3bb37b5 3718parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3719{
3720 char *l = line;
3721 char *token_start = l;
3722 char *mnem_p;
5c6af06e 3723 int supported;
d3ce72d0 3724 const insn_template *t;
b6169b20 3725 char *dot_p = NULL;
29b0f896 3726
29b0f896
AM		 3727 while (1)
3728 {
3729 mnem_p = mnemonic;
3730 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3731 {
b6169b20
L		 3732 if (*mnem_p == '.')
3733 dot_p = mnem_p;
29b0f896
AM		 3734 mnem_p++;
3735 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3736 {
29b0f896
AM		 3737 as_bad (_("no such instruction: `%s'"), token_start);
3738 return NULL;
3739 }
3740 l++;
3741 }
3742 if (!is_space_char (*l)
3743 && *l != END_OF_INSN
e44823cf
JB		 3744 && (intel_syntax
3745 || (*l != PREFIX_SEPARATOR
3746 && *l != ',')))
29b0f896
AM		 3747 {
3748 as_bad (_("invalid character %s in mnemonic"),
3749 output_invalid (*l));
3750 return NULL;
3751 }
3752 if (token_start == l)
3753 {
e44823cf 3754 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3755 as_bad (_("expecting prefix; got nothing"));
3756 else
3757 as_bad (_("expecting mnemonic; got nothing"));
3758 return NULL;
3759 }
45288df1 3760
29b0f896 3761 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3762 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3763
29b0f896
AM		 3764 if (*l != END_OF_INSN
3765 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3766 && current_templates
40fb9820 3767 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3768 {
c6fb90c8 3769 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3770 {
3771 as_bad ((flag_code != CODE_64BIT
3772 ? _("`%s' is only supported in 64-bit mode")
3773 : _("`%s' is not supported in 64-bit mode")),
3774 current_templates->start->name);
3775 return NULL;
3776 }
29b0f896
AM		 3777 /* If we are in 16-bit mode, do not allow addr16 or data16.
3778 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3779 if ((current_templates->start->opcode_modifier.size16
3780 || current_templates->start->opcode_modifier.size32)
29b0f896 3781 && flag_code != CODE_64BIT
40fb9820 3782 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3783 ^ (flag_code == CODE_16BIT)))
3784 {
3785 as_bad (_("redundant %s prefix"),
3786 current_templates->start->name);
3787 return NULL;
45288df1 3788 }
29b0f896
AM		 3789 /* Add prefix, checking for repeated prefixes. */
3790 switch (add_prefix (current_templates->start->base_opcode))
3791 {
c32fa91d 3792 case PREFIX_EXIST:
29b0f896 3793 return NULL;
c32fa91d 3794 case PREFIX_REP:
42164a71 3795 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3796 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3797 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3798 i.bnd_prefix = current_templates->start->name;
42164a71 3799 else
d5de92cf 3800 i.rep_prefix = current_templates->start->name;
29b0f896 3801 break;
c32fa91d
L		 3802 default:
3803 break;
29b0f896
AM		 3804 }
3805 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3806 token_start = ++l;
3807 }
3808 else
3809 break;
3810 }
45288df1 3811
30a55f88 3812 if (!current_templates)
b6169b20 3813 {
f8a5c266
L		 3814 /* Check if we should swap operand or force 32bit displacement in
3815 encoding. */
30a55f88
L		 3816 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3817 i.swap_operand = 1;
8d63c93e 3818 else if (mnem_p - 3 == dot_p
a501d77e
L		 3819 && dot_p[1] == 'd'
3820 && dot_p[2] == '8')
3821 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3822 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3823 && dot_p[1] == 'd'
3824 && dot_p[2] == '3'
3825 && dot_p[3] == '2')
a501d77e 3826 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3827 else
3828 goto check_suffix;
3829 mnem_p = dot_p;
3830 *dot_p = '\0';
d3ce72d0 3831 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3832 }
3833
29b0f896
AM		 3834 if (!current_templates)
3835 {
b6169b20 3836check_suffix:
29b0f896
AM		 3837 /* See if we can get a match by trimming off a suffix. */
3838 switch (mnem_p[-1])
3839 {
3840 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3841 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3842 i.suffix = SHORT_MNEM_SUFFIX;
3843 else
29b0f896
AM		 3844 case BYTE_MNEM_SUFFIX:
3845 case QWORD_MNEM_SUFFIX:
3846 i.suffix = mnem_p[-1];
3847 mnem_p[-1] = '\0';
d3ce72d0
NC		 3848 current_templates = (const templates *) hash_find (op_hash,
3849 mnemonic);
29b0f896
AM		 3850 break;
3851 case SHORT_MNEM_SUFFIX:
3852 case LONG_MNEM_SUFFIX:
3853 if (!intel_syntax)
3854 {
3855 i.suffix = mnem_p[-1];
3856 mnem_p[-1] = '\0';
d3ce72d0
NC		 3857 current_templates = (const templates *) hash_find (op_hash,
3858 mnemonic);
29b0f896
AM		 3859 }
3860 break;
252b5132 3861
29b0f896
AM		 3862 /* Intel Syntax. */
3863 case 'd':
3864 if (intel_syntax)
3865 {
9306ca4a 3866 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3867 i.suffix = SHORT_MNEM_SUFFIX;
3868 else
3869 i.suffix = LONG_MNEM_SUFFIX;
3870 mnem_p[-1] = '\0';
d3ce72d0
NC		 3871 current_templates = (const templates *) hash_find (op_hash,
3872 mnemonic);
29b0f896
AM		 3873 }
3874 break;
3875 }
3876 if (!current_templates)
3877 {
3878 as_bad (_("no such instruction: `%s'"), token_start);
3879 return NULL;
3880 }
3881 }
252b5132 3882
40fb9820
L		 3883 if (current_templates->start->opcode_modifier.jump
3884 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3885 {
3886 /* Check for a branch hint. We allow ",pt" and ",pn" for
3887 predict taken and predict not taken respectively.
3888 I'm not sure that branch hints actually do anything on loop
3889 and jcxz insns (JumpByte) for current Pentium4 chips. They
3890 may work in the future and it doesn't hurt to accept them
3891 now. */
3892 if (l[0] == ',' && l[1] == 'p')
3893 {
3894 if (l[2] == 't')
3895 {
3896 if (!add_prefix (DS_PREFIX_OPCODE))
3897 return NULL;
3898 l += 3;
3899 }
3900 else if (l[2] == 'n')
3901 {
3902 if (!add_prefix (CS_PREFIX_OPCODE))
3903 return NULL;
3904 l += 3;
3905 }
3906 }
3907 }
3908 /* Any other comma loses. */
3909 if (*l == ',')
3910 {
3911 as_bad (_("invalid character %s in mnemonic"),
3912 output_invalid (*l));
3913 return NULL;
3914 }
252b5132 3915
29b0f896 3916 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3917 supported = 0;
3918 for (t = current_templates->start; t < current_templates->end; ++t)
3919 {
c0f3af97
L		 3920 supported |= cpu_flags_match (t);
3921 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3922 goto skip;
5c6af06e 3923 }
3629bb00 3924
c0f3af97 3925 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3926 {
3927 as_bad (flag_code == CODE_64BIT
3928 ? _("`%s' is not supported in 64-bit mode")
3929 : _("`%s' is only supported in 64-bit mode"),
3930 current_templates->start->name);
3931 return NULL;
3932 }
c0f3af97 3933 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3934 {
3629bb00 3935 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3936 current_templates->start->name,
41aacd83 3937 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3938 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3939 return NULL;
29b0f896 3940 }
3629bb00
L		 3941
3942skip:
3943 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3944 && (flag_code != CODE_16BIT))
29b0f896
AM		 3945 {
3946 as_warn (_("use .code16 to ensure correct addressing mode"));
3947 }
252b5132 3948
29b0f896
AM		 3949 return l;
3950}
252b5132 3951
29b0f896 3952static char *
e3bb37b5 3953parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3954{
3955 char *token_start;
3138f287 3956
29b0f896
AM		 3957 /* 1 if operand is pending after ','. */
3958 unsigned int expecting_operand = 0;
252b5132 3959
29b0f896
AM		 3960 /* Non-zero if operand parens not balanced. */
3961 unsigned int paren_not_balanced;
3962
3963 while (*l != END_OF_INSN)
3964 {
3965 /* Skip optional white space before operand. */
3966 if (is_space_char (*l))
3967 ++l;
d02603dc 3968 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 3969 {
3970 as_bad (_("invalid character %s before operand %d"),
3971 output_invalid (*l),
3972 i.operands + 1);
3973 return NULL;
3974 }
d02603dc 3975 token_start = l; /* After white space. */
29b0f896
AM		 3976 paren_not_balanced = 0;
3977 while (paren_not_balanced || *l != ',')
3978 {
3979 if (*l == END_OF_INSN)
3980 {
3981 if (paren_not_balanced)
3982 {
3983 if (!intel_syntax)
3984 as_bad (_("unbalanced parenthesis in operand %d."),
3985 i.operands + 1);
3986 else
3987 as_bad (_("unbalanced brackets in operand %d."),
3988 i.operands + 1);
3989 return NULL;
3990 }
3991 else
3992 break; /* we are done */
3993 }
d02603dc 3994 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 3995 {
3996 as_bad (_("invalid character %s in operand %d"),
3997 output_invalid (*l),
3998 i.operands + 1);
3999 return NULL;
4000 }
4001 if (!intel_syntax)
4002 {
4003 if (*l == '(')
4004 ++paren_not_balanced;
4005 if (*l == ')')
4006 --paren_not_balanced;
4007 }
4008 else
4009 {
4010 if (*l == '[')
4011 ++paren_not_balanced;
4012 if (*l == ']')
4013 --paren_not_balanced;
4014 }
4015 l++;
4016 }
4017 if (l != token_start)
4018 { /* Yes, we've read in another operand. */
4019 unsigned int operand_ok;
4020 this_operand = i.operands++;
7d5e4556 4021 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4022 if (i.operands > MAX_OPERANDS)
4023 {
4024 as_bad (_("spurious operands; (%d operands/instruction max)"),
4025 MAX_OPERANDS);
4026 return NULL;
4027 }
4028 /* Now parse operand adding info to 'i' as we go along. */
4029 END_STRING_AND_SAVE (l);
4030
4031 if (intel_syntax)
4032 operand_ok =
4033 i386_intel_operand (token_start,
4034 intel_float_operand (mnemonic));
4035 else
a7619375 4036 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4037
4038 RESTORE_END_STRING (l);
4039 if (!operand_ok)
4040 return NULL;
4041 }
4042 else
4043 {
4044 if (expecting_operand)
4045 {
4046 expecting_operand_after_comma:
4047 as_bad (_("expecting operand after ','; got nothing"));
4048 return NULL;
4049 }
4050 if (*l == ',')
4051 {
4052 as_bad (_("expecting operand before ','; got nothing"));
4053 return NULL;
4054 }
4055 }
7f3f1ea2 4056
29b0f896
AM		 4057 /* Now *l must be either ',' or END_OF_INSN. */
4058 if (*l == ',')
4059 {
4060 if (*++l == END_OF_INSN)
4061 {
4062 /* Just skip it, if it's \n complain. */
4063 goto expecting_operand_after_comma;
4064 }
4065 expecting_operand = 1;
4066 }
4067 }
4068 return l;
4069}
7f3f1ea2 4070
050dfa73 4071static void
4d456e3d 4072swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4073{
4074 union i386_op temp_op;
40fb9820 4075 i386_operand_type temp_type;
050dfa73 4076 enum bfd_reloc_code_real temp_reloc;
4eed87de 4077
050dfa73
MM		 4078 temp_type = i.types[xchg2];
4079 i.types[xchg2] = i.types[xchg1];
4080 i.types[xchg1] = temp_type;
4081 temp_op = i.op[xchg2];
4082 i.op[xchg2] = i.op[xchg1];
4083 i.op[xchg1] = temp_op;
4084 temp_reloc = i.reloc[xchg2];
4085 i.reloc[xchg2] = i.reloc[xchg1];
4086 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4087
4088 if (i.mask)
4089 {
4090 if (i.mask->operand == xchg1)
4091 i.mask->operand = xchg2;
4092 else if (i.mask->operand == xchg2)
4093 i.mask->operand = xchg1;
4094 }
4095 if (i.broadcast)
4096 {
4097 if (i.broadcast->operand == xchg1)
4098 i.broadcast->operand = xchg2;
4099 else if (i.broadcast->operand == xchg2)
4100 i.broadcast->operand = xchg1;
4101 }
4102 if (i.rounding)
4103 {
4104 if (i.rounding->operand == xchg1)
4105 i.rounding->operand = xchg2;
4106 else if (i.rounding->operand == xchg2)
4107 i.rounding->operand = xchg1;
4108 }
050dfa73
MM		 4109}
4110
29b0f896 4111static void
e3bb37b5 4112swap_operands (void)
29b0f896 4113{
b7c61d9a 4114 switch (i.operands)
050dfa73 4115 {
c0f3af97 4116 case 5:
b7c61d9a 4117 case 4:
4d456e3d 4118 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4119 case 3:
4120 case 2:
4d456e3d 4121 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4122 break;
4123 default:
4124 abort ();
29b0f896 4125 }
29b0f896
AM		 4126
4127 if (i.mem_operands == 2)
4128 {
4129 const seg_entry *temp_seg;
4130 temp_seg = i.seg[0];
4131 i.seg[0] = i.seg[1];
4132 i.seg[1] = temp_seg;
4133 }
4134}
252b5132 4135
29b0f896
AM		 4136/* Try to ensure constant immediates are represented in the smallest
4137 opcode possible. */
4138static void
e3bb37b5 4139optimize_imm (void)
29b0f896
AM		 4140{
4141 char guess_suffix = 0;
4142 int op;
252b5132 4143
29b0f896
AM		 4144 if (i.suffix)
4145 guess_suffix = i.suffix;
4146 else if (i.reg_operands)
4147 {
4148 /* Figure out a suffix from the last register operand specified.
4149 We can't do this properly yet, ie. excluding InOutPortReg,
4150 but the following works for instructions with immediates.
4151 In any case, we can't set i.suffix yet. */
4152 for (op = i.operands; --op >= 0;)
40fb9820 4153 if (i.types[op].bitfield.reg8)
7ab9ffdd 4154 {
40fb9820
L		 4155 guess_suffix = BYTE_MNEM_SUFFIX;
4156 break;
4157 }
4158 else if (i.types[op].bitfield.reg16)
252b5132 4159 {
40fb9820
L		 4160 guess_suffix = WORD_MNEM_SUFFIX;
4161 break;
4162 }
4163 else if (i.types[op].bitfield.reg32)
4164 {
4165 guess_suffix = LONG_MNEM_SUFFIX;
4166 break;
4167 }
4168 else if (i.types[op].bitfield.reg64)
4169 {
4170 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4171 break;
252b5132 4172 }
29b0f896
AM		 4173 }
4174 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4175 guess_suffix = WORD_MNEM_SUFFIX;
4176
4177 for (op = i.operands; --op >= 0;)
40fb9820 4178 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4179 {
4180 switch (i.op[op].imms->X_op)
252b5132 4181 {
29b0f896
AM		 4182 case O_constant:
4183 /* If a suffix is given, this operand may be shortened. */
4184 switch (guess_suffix)
252b5132 4185 {
29b0f896 4186 case LONG_MNEM_SUFFIX:
40fb9820
L		 4187 i.types[op].bitfield.imm32 = 1;
4188 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4189 break;
4190 case WORD_MNEM_SUFFIX:
40fb9820
L		 4191 i.types[op].bitfield.imm16 = 1;
4192 i.types[op].bitfield.imm32 = 1;
4193 i.types[op].bitfield.imm32s = 1;
4194 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4195 break;
4196 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4197 i.types[op].bitfield.imm8 = 1;
4198 i.types[op].bitfield.imm8s = 1;
4199 i.types[op].bitfield.imm16 = 1;
4200 i.types[op].bitfield.imm32 = 1;
4201 i.types[op].bitfield.imm32s = 1;
4202 i.types[op].bitfield.imm64 = 1;
29b0f896 4203 break;
252b5132 4204 }
252b5132 4205
29b0f896
AM		 4206 /* If this operand is at most 16 bits, convert it
4207 to a signed 16 bit number before trying to see
4208 whether it will fit in an even smaller size.
4209 This allows a 16-bit operand such as $0xffe0 to
4210 be recognised as within Imm8S range. */
40fb9820 4211 if ((i.types[op].bitfield.imm16)
29b0f896 4212 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4213 {
29b0f896
AM		 4214 i.op[op].imms->X_add_number =
4215 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4216 }
40fb9820 4217 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4218 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4219 == 0))
4220 {
4221 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4222 ^ ((offsetT) 1 << 31))
4223 - ((offsetT) 1 << 31));
4224 }
40fb9820 4225 i.types[op]
c6fb90c8
L		 4226 = operand_type_or (i.types[op],
4227 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4228
29b0f896
AM		 4229 /* We must avoid matching of Imm32 templates when 64bit
4230 only immediate is available. */
4231 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4232 i.types[op].bitfield.imm32 = 0;
29b0f896 4233 break;
252b5132 4234
29b0f896
AM		 4235 case O_absent:
4236 case O_register:
4237 abort ();
4238
4239 /* Symbols and expressions. */
4240 default:
9cd96992
JB		 4241 /* Convert symbolic operand to proper sizes for matching, but don't
4242 prevent matching a set of insns that only supports sizes other
4243 than those matching the insn suffix. */
4244 {
40fb9820 4245 i386_operand_type mask, allowed;
d3ce72d0 4246 const insn_template *t;
9cd96992 4247
0dfbf9d7
L		 4248 operand_type_set (&mask, 0);
4249 operand_type_set (&allowed, 0);
40fb9820 4250
4eed87de
AM		 4251 for (t = current_templates->start;
4252 t < current_templates->end;
4253 ++t)
c6fb90c8
L		 4254 allowed = operand_type_or (allowed,
4255 t->operand_types[op]);
9cd96992
JB		 4256 switch (guess_suffix)
4257 {
4258 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4259 mask.bitfield.imm64 = 1;
4260 mask.bitfield.imm32s = 1;
9cd96992
JB		 4261 break;
4262 case LONG_MNEM_SUFFIX:
40fb9820 4263 mask.bitfield.imm32 = 1;
9cd96992
JB		 4264 break;
4265 case WORD_MNEM_SUFFIX:
40fb9820 4266 mask.bitfield.imm16 = 1;
9cd96992
JB		 4267 break;
4268 case BYTE_MNEM_SUFFIX:
40fb9820 4269 mask.bitfield.imm8 = 1;
9cd96992
JB		 4270 break;
4271 default:
9cd96992
JB		 4272 break;
4273 }
c6fb90c8 4274 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4275 if (!operand_type_all_zero (&allowed))
c6fb90c8 4276 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4277 }
29b0f896 4278 break;
252b5132 4279 }
29b0f896
AM		 4280 }
4281}
47926f60 4282
29b0f896
AM		 4283/* Try to use the smallest displacement type too. */
4284static void
e3bb37b5 4285optimize_disp (void)
29b0f896
AM		 4286{
4287 int op;
3e73aa7c 4288
29b0f896 4289 for (op = i.operands; --op >= 0;)
40fb9820 4290 if (operand_type_check (i.types[op], disp))
252b5132 4291 {
b300c311 4292 if (i.op[op].disps->X_op == O_constant)
252b5132 4293 {
91d6fa6a 4294 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4295
40fb9820 4296 if (i.types[op].bitfield.disp16
91d6fa6a 4297 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4298 {
4299 /* If this operand is at most 16 bits, convert
4300 to a signed 16 bit number and don't use 64bit
4301 displacement. */
91d6fa6a 4302 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4303 i.types[op].bitfield.disp64 = 0;
b300c311 4304 }
40fb9820 4305 if (i.types[op].bitfield.disp32
91d6fa6a 4306 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4307 {
4308 /* If this operand is at most 32 bits, convert
4309 to a signed 32 bit number and don't use 64bit
4310 displacement. */
91d6fa6a
NC		 4311 op_disp &= (((offsetT) 2 << 31) - 1);
4312 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4313 i.types[op].bitfield.disp64 = 0;
b300c311 4314 }
91d6fa6a 4315 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4316 {
40fb9820
L		 4317 i.types[op].bitfield.disp8 = 0;
4318 i.types[op].bitfield.disp16 = 0;
4319 i.types[op].bitfield.disp32 = 0;
4320 i.types[op].bitfield.disp32s = 0;
4321 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4322 i.op[op].disps = 0;
4323 i.disp_operands--;
4324 }
4325 else if (flag_code == CODE_64BIT)
4326 {
91d6fa6a 4327 if (fits_in_signed_long (op_disp))
28a9d8f5 4328 {
40fb9820
L		 4329 i.types[op].bitfield.disp64 = 0;
4330 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4331 }
0e1147d9 4332 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4333 && fits_in_unsigned_long (op_disp))
40fb9820 4334 i.types[op].bitfield.disp32 = 1;
b300c311 4335 }
40fb9820
L		 4336 if ((i.types[op].bitfield.disp32
4337 || i.types[op].bitfield.disp32s
4338 || i.types[op].bitfield.disp16)
91d6fa6a 4339 && fits_in_signed_byte (op_disp))
40fb9820 4340 i.types[op].bitfield.disp8 = 1;
252b5132 4341 }
67a4f2b7
AO		 4342 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4343 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4344 {
4345 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4346 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4347 i.types[op].bitfield.disp8 = 0;
4348 i.types[op].bitfield.disp16 = 0;
4349 i.types[op].bitfield.disp32 = 0;
4350 i.types[op].bitfield.disp32s = 0;
4351 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4352 }
4353 else
b300c311 4354 /* We only support 64bit displacement on constants. */
40fb9820 4355 i.types[op].bitfield.disp64 = 0;
252b5132 4356 }
29b0f896
AM		 4357}
4358
6c30d220
L		 4359/* Check if operands are valid for the instruction. */
4360
4361static int
4362check_VecOperands (const insn_template *t)
4363{
43234a1e
L		 4364 unsigned int op;
4365
6c30d220
L		 4366 /* Without VSIB byte, we can't have a vector register for index. */
4367 if (!t->opcode_modifier.vecsib
4368 && i.index_reg
4369 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4370 || i.index_reg->reg_type.bitfield.regymm
4371 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4372 {
4373 i.error = unsupported_vector_index_register;
4374 return 1;
4375 }
4376
ad8ecc81
MZ		 4377 /* Check if default mask is allowed. */
4378 if (t->opcode_modifier.nodefmask
4379 && (!i.mask || i.mask->mask->reg_num == 0))
4380 {
4381 i.error = no_default_mask;
4382 return 1;
4383 }
4384
7bab8ab5
JB		 4385 /* For VSIB byte, we need a vector register for index, and all vector
4386 registers must be distinct. */
4387 if (t->opcode_modifier.vecsib)
4388 {
4389 if (!i.index_reg
6c30d220
L		 4390 || !((t->opcode_modifier.vecsib == VecSIB128
4391 && i.index_reg->reg_type.bitfield.regxmm)
4392 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4393 && i.index_reg->reg_type.bitfield.regymm)
4394 || (t->opcode_modifier.vecsib == VecSIB512
4395 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4396 {
4397 i.error = invalid_vsib_address;
4398 return 1;
4399 }
4400
43234a1e
L		 4401 gas_assert (i.reg_operands == 2 || i.mask);
4402 if (i.reg_operands == 2 && !i.mask)
4403 {
4404 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4405 || i.types[0].bitfield.regymm);
43234a1e 4406 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4407 || i.types[2].bitfield.regymm);
43234a1e
L		 4408 if (operand_check == check_none)
4409 return 0;
4410 if (register_number (i.op[0].regs)
4411 != register_number (i.index_reg)
4412 && register_number (i.op[2].regs)
4413 != register_number (i.index_reg)
4414 && register_number (i.op[0].regs)
4415 != register_number (i.op[2].regs))
4416 return 0;
4417 if (operand_check == check_error)
4418 {
4419 i.error = invalid_vector_register_set;
4420 return 1;
4421 }
4422 as_warn (_("mask, index, and destination registers should be distinct"));
4423 }
8444f82a
MZ		 4424 else if (i.reg_operands == 1 && i.mask)
4425 {
4426 if ((i.types[1].bitfield.regymm
4427 || i.types[1].bitfield.regzmm)
4428 && (register_number (i.op[1].regs)
4429 == register_number (i.index_reg)))
4430 {
4431 if (operand_check == check_error)
4432 {
4433 i.error = invalid_vector_register_set;
4434 return 1;
4435 }
4436 if (operand_check != check_none)
4437 as_warn (_("index and destination registers should be distinct"));
4438 }
4439 }
43234a1e 4440 }
7bab8ab5 4441
43234a1e
L		 4442 /* Check if broadcast is supported by the instruction and is applied
4443 to the memory operand. */
4444 if (i.broadcast)
4445 {
4446 int broadcasted_opnd_size;
4447
4448 /* Check if specified broadcast is supported in this instruction,
4449 and it's applied to memory operand of DWORD or QWORD type,
4450 depending on VecESize. */
4451 if (i.broadcast->type != t->opcode_modifier.broadcast
4452 || !i.types[i.broadcast->operand].bitfield.mem
4453 || (t->opcode_modifier.vecesize == 0
4454 && !i.types[i.broadcast->operand].bitfield.dword
4455 && !i.types[i.broadcast->operand].bitfield.unspecified)
4456 || (t->opcode_modifier.vecesize == 1
4457 && !i.types[i.broadcast->operand].bitfield.qword
4458 && !i.types[i.broadcast->operand].bitfield.unspecified))
4459 goto bad_broadcast;
4460
4461 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4462 if (i.broadcast->type == BROADCAST_1TO16)
4463 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4464 else if (i.broadcast->type == BROADCAST_1TO8)
4465 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4466 else if (i.broadcast->type == BROADCAST_1TO4)
4467 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4468 else if (i.broadcast->type == BROADCAST_1TO2)
4469 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4470 else
4471 goto bad_broadcast;
4472
4473 if ((broadcasted_opnd_size == 256
4474 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4475 || (broadcasted_opnd_size == 512
4476 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4477 {
4478 bad_broadcast:
4479 i.error = unsupported_broadcast;
4480 return 1;
4481 }
4482 }
4483 /* If broadcast is supported in this instruction, we need to check if
4484 operand of one-element size isn't specified without broadcast. */
4485 else if (t->opcode_modifier.broadcast && i.mem_operands)
4486 {
4487 /* Find memory operand. */
4488 for (op = 0; op < i.operands; op++)
4489 if (operand_type_check (i.types[op], anymem))
4490 break;
4491 gas_assert (op < i.operands);
4492 /* Check size of the memory operand. */
4493 if ((t->opcode_modifier.vecesize == 0
4494 && i.types[op].bitfield.dword)
4495 || (t->opcode_modifier.vecesize == 1
4496 && i.types[op].bitfield.qword))
4497 {
4498 i.error = broadcast_needed;
4499 return 1;
4500 }
4501 }
4502
4503 /* Check if requested masking is supported. */
4504 if (i.mask
4505 && (!t->opcode_modifier.masking
4506 || (i.mask->zeroing
4507 && t->opcode_modifier.masking == MERGING_MASKING)))
4508 {
4509 i.error = unsupported_masking;
4510 return 1;
4511 }
4512
4513 /* Check if masking is applied to dest operand. */
4514 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4515 {
4516 i.error = mask_not_on_destination;
4517 return 1;
4518 }
4519
43234a1e
L		 4520 /* Check RC/SAE. */
4521 if (i.rounding)
4522 {
4523 if ((i.rounding->type != saeonly
4524 && !t->opcode_modifier.staticrounding)
4525 || (i.rounding->type == saeonly
4526 && (t->opcode_modifier.staticrounding
4527 || !t->opcode_modifier.sae)))
4528 {
4529 i.error = unsupported_rc_sae;
4530 return 1;
4531 }
4532 /* If the instruction has several immediate operands and one of
4533 them is rounding, the rounding operand should be the last
4534 immediate operand. */
4535 if (i.imm_operands > 1
4536 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4537 {
43234a1e 4538 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4539 return 1;
4540 }
6c30d220
L		 4541 }
4542
43234a1e
L		 4543 /* Check vector Disp8 operand. */
4544 if (t->opcode_modifier.disp8memshift)
4545 {
4546 if (i.broadcast)
4547 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4548 else
4549 i.memshift = t->opcode_modifier.disp8memshift;
4550
4551 for (op = 0; op < i.operands; op++)
4552 if (operand_type_check (i.types[op], disp)
4553 && i.op[op].disps->X_op == O_constant)
4554 {
4555 offsetT value = i.op[op].disps->X_add_number;
4556 int vec_disp8_ok = fits_in_vec_disp8 (value);
4557 if (t->operand_types [op].bitfield.vec_disp8)
4558 {
4559 if (vec_disp8_ok)
4560 i.types[op].bitfield.vec_disp8 = 1;
4561 else
4562 {
4563 /* Vector insn can only have Vec_Disp8/Disp32 in
4564 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4565 mode. */
4566 i.types[op].bitfield.disp8 = 0;
4567 if (flag_code != CODE_16BIT)
4568 i.types[op].bitfield.disp16 = 0;
4569 }
4570 }
4571 else if (flag_code != CODE_16BIT)
4572 {
4573 /* One form of this instruction supports vector Disp8.
4574 Try vector Disp8 if we need to use Disp32. */
4575 if (vec_disp8_ok && !fits_in_signed_byte (value))
4576 {
4577 i.error = try_vector_disp8;
4578 return 1;
4579 }
4580 }
4581 }
4582 }
4583 else
4584 i.memshift = -1;
4585
6c30d220
L		 4586 return 0;
4587}
4588
43f3e2ee 4589/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4590 operand types. */
4591
4592static int
4593VEX_check_operands (const insn_template *t)
4594{
43234a1e
L		 4595 /* VREX is only valid with EVEX prefix. */
4596 if (i.need_vrex && !t->opcode_modifier.evex)
4597 {
4598 i.error = invalid_register_operand;
4599 return 1;
4600 }
4601
a683cc34
SP		 4602 if (!t->opcode_modifier.vex)
4603 return 0;
4604
4605 /* Only check VEX_Imm4, which must be the first operand. */
4606 if (t->operand_types[0].bitfield.vec_imm4)
4607 {
4608 if (i.op[0].imms->X_op != O_constant
4609 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4610 {
a65babc9 4611 i.error = bad_imm4;
891edac4
L		 4612 return 1;
4613 }
a683cc34
SP		 4614
4615 /* Turn off Imm8 so that update_imm won't complain. */
4616 i.types[0] = vec_imm4;
4617 }
4618
4619 return 0;
4620}
4621
d3ce72d0 4622static const insn_template *
e3bb37b5 4623match_template (void)
29b0f896
AM		 4624{
4625 /* Points to template once we've found it. */
d3ce72d0 4626 const insn_template *t;
40fb9820 4627 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4628 i386_operand_type overlap4;
29b0f896 4629 unsigned int found_reverse_match;
40fb9820
L		 4630 i386_opcode_modifier suffix_check;
4631 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4632 int addr_prefix_disp;
a5c311ca 4633 unsigned int j;
3629bb00 4634 unsigned int found_cpu_match;
45664ddb 4635 unsigned int check_register;
5614d22c 4636 enum i386_error specific_error = 0;
29b0f896 4637
c0f3af97
L		 4638#if MAX_OPERANDS != 5
4639# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4640#endif
4641
29b0f896 4642 found_reverse_match = 0;
539e75ad 4643 addr_prefix_disp = -1;
40fb9820
L		 4644
4645 memset (&suffix_check, 0, sizeof (suffix_check));
4646 if (i.suffix == BYTE_MNEM_SUFFIX)
4647 suffix_check.no_bsuf = 1;
4648 else if (i.suffix == WORD_MNEM_SUFFIX)
4649 suffix_check.no_wsuf = 1;
4650 else if (i.suffix == SHORT_MNEM_SUFFIX)
4651 suffix_check.no_ssuf = 1;
4652 else if (i.suffix == LONG_MNEM_SUFFIX)
4653 suffix_check.no_lsuf = 1;
4654 else if (i.suffix == QWORD_MNEM_SUFFIX)
4655 suffix_check.no_qsuf = 1;
4656 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4657 suffix_check.no_ldsuf = 1;
29b0f896 4658
01559ecc
L		 4659 /* Must have right number of operands. */
4660 i.error = number_of_operands_mismatch;
4661
45aa61fe 4662 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4663 {
539e75ad
L		 4664 addr_prefix_disp = -1;
4665
29b0f896
AM		 4666 if (i.operands != t->operands)
4667 continue;
4668
50aecf8c 4669 /* Check processor support. */
a65babc9 4670 i.error = unsupported;
c0f3af97
L		 4671 found_cpu_match = (cpu_flags_match (t)
4672 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4673 if (!found_cpu_match)
4674 continue;
4675
e1d4d893 4676 /* Check old gcc support. */
a65babc9 4677 i.error = old_gcc_only;
e1d4d893
L		 4678 if (!old_gcc && t->opcode_modifier.oldgcc)
4679 continue;
4680
4681 /* Check AT&T mnemonic. */
a65babc9 4682 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4683 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4684 continue;
4685
891edac4 4686 /* Check AT&T/Intel syntax. */
a65babc9 4687 i.error = unsupported_syntax;
5c07affc
L		 4688 if ((intel_syntax && t->opcode_modifier.attsyntax)
4689 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4690 continue;
4691
20592a94 4692 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4693 i.error = invalid_instruction_suffix;
567e4e96
L		 4694 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4695 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4696 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4697 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4698 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4699 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4700 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4701 continue;
4702
5c07affc 4703 if (!operand_size_match (t))
7d5e4556 4704 continue;
539e75ad 4705
5c07affc
L		 4706 for (j = 0; j < MAX_OPERANDS; j++)
4707 operand_types[j] = t->operand_types[j];
4708
45aa61fe
AM		 4709 /* In general, don't allow 64-bit operands in 32-bit mode. */
4710 if (i.suffix == QWORD_MNEM_SUFFIX
4711 && flag_code != CODE_64BIT
4712 && (intel_syntax
40fb9820 4713 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4714 && !intel_float_operand (t->name))
4715 : intel_float_operand (t->name) != 2)
40fb9820 4716 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4717 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4718 && !operand_types[0].bitfield.regymm
4719 && !operand_types[0].bitfield.regzmm)
40fb9820 4720 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4721 && operand_types[t->operands > 1].bitfield.regxmm
4722 && operand_types[t->operands > 1].bitfield.regymm
4723 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4724 && (t->base_opcode != 0x0fc7
4725 || t->extension_opcode != 1 /* cmpxchg8b */))
4726 continue;
4727
192dc9c6
JB		 4728 /* In general, don't allow 32-bit operands on pre-386. */
4729 else if (i.suffix == LONG_MNEM_SUFFIX
4730 && !cpu_arch_flags.bitfield.cpui386
4731 && (intel_syntax
4732 ? (!t->opcode_modifier.ignoresize
4733 && !intel_float_operand (t->name))
4734 : intel_float_operand (t->name) != 2)
4735 && ((!operand_types[0].bitfield.regmmx
4736 && !operand_types[0].bitfield.regxmm)
4737 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 4738 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 4739 continue;
4740
29b0f896 4741 /* Do not verify operands when there are none. */
50aecf8c 4742 else
29b0f896 4743 {
c6fb90c8 4744 if (!t->operands)
2dbab7d5
L		 4745 /* We've found a match; break out of loop. */
4746 break;
29b0f896 4747 }
252b5132 4748
539e75ad
L		 4749 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4750 into Disp32/Disp16/Disp32 operand. */
4751 if (i.prefix[ADDR_PREFIX] != 0)
4752 {
40fb9820 4753 /* There should be only one Disp operand. */
539e75ad
L		 4754 switch (flag_code)
4755 {
4756 case CODE_16BIT:
40fb9820
L		 4757 for (j = 0; j < MAX_OPERANDS; j++)
4758 {
4759 if (operand_types[j].bitfield.disp16)
4760 {
4761 addr_prefix_disp = j;
4762 operand_types[j].bitfield.disp32 = 1;
4763 operand_types[j].bitfield.disp16 = 0;
4764 break;
4765 }
4766 }
539e75ad
L		 4767 break;
4768 case CODE_32BIT:
40fb9820
L		 4769 for (j = 0; j < MAX_OPERANDS; j++)
4770 {
4771 if (operand_types[j].bitfield.disp32)
4772 {
4773 addr_prefix_disp = j;
4774 operand_types[j].bitfield.disp32 = 0;
4775 operand_types[j].bitfield.disp16 = 1;
4776 break;
4777 }
4778 }
539e75ad
L		 4779 break;
4780 case CODE_64BIT:
40fb9820
L		 4781 for (j = 0; j < MAX_OPERANDS; j++)
4782 {
4783 if (operand_types[j].bitfield.disp64)
4784 {
4785 addr_prefix_disp = j;
4786 operand_types[j].bitfield.disp64 = 0;
4787 operand_types[j].bitfield.disp32 = 1;
4788 break;
4789 }
4790 }
539e75ad
L		 4791 break;
4792 }
539e75ad
L		 4793 }
4794
02a86693
L		 4795 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4796 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
4797 continue;
4798
56ffb741
L		 4799 /* We check register size if needed. */
4800 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4801 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4802 switch (t->operands)
4803 {
4804 case 1:
40fb9820 4805 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4806 continue;
4807 break;
4808 case 2:
8b38ad71
L		 4809 /* xchg %eax, %eax is a special case. It is an aliase for nop
4810 only in 32bit mode and we can use opcode 0x90. In 64bit
4811 mode, we can't use 0x90 for xchg %eax, %eax since it should
4812 zero-extend %eax to %rax. */
4813 if (flag_code == CODE_64BIT
4814 && t->base_opcode == 0x90
0dfbf9d7
L		 4815 && operand_type_equal (&i.types [0], &acc32)
4816 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4817 continue;
b6169b20
L		 4818 if (i.swap_operand)
4819 {
4820 /* If we swap operand in encoding, we either match
4821 the next one or reverse direction of operands. */
4822 if (t->opcode_modifier.s)
4823 continue;
4824 else if (t->opcode_modifier.d)
4825 goto check_reverse;
4826 }
4827
29b0f896 4828 case 3:
fa99fab2
L		 4829 /* If we swap operand in encoding, we match the next one. */
4830 if (i.swap_operand && t->opcode_modifier.s)
4831 continue;
f48ff2ae 4832 case 4:
c0f3af97 4833 case 5:
c6fb90c8 4834 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4835 if (!operand_type_match (overlap0, i.types[0])
4836 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4837 || (check_register
4838 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4839 operand_types[0],
4840 overlap1, i.types[1],
4841 operand_types[1])))
29b0f896
AM		 4842 {
4843 /* Check if other direction is valid ... */
40fb9820 4844 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4845 continue;
4846
b6169b20 4847check_reverse:
29b0f896 4848 /* Try reversing direction of operands. */
c6fb90c8
L		 4849 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4850 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4851 if (!operand_type_match (overlap0, i.types[0])
4852 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4853 || (check_register
4854 && !operand_type_register_match (overlap0,
4855 i.types[0],
4856 operand_types[1],
4857 overlap1,
4858 i.types[1],
4859 operand_types[0])))
29b0f896
AM		 4860 {
4861 /* Does not match either direction. */
4862 continue;
4863 }
4864 /* found_reverse_match holds which of D or FloatDR
4865 we've found. */
40fb9820 4866 if (t->opcode_modifier.d)
8a2ed489 4867 found_reverse_match = Opcode_D;
40fb9820 4868 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4869 found_reverse_match = Opcode_FloatD;
4870 else
4871 found_reverse_match = 0;
40fb9820 4872 if (t->opcode_modifier.floatr)
8a2ed489 4873 found_reverse_match |= Opcode_FloatR;
29b0f896 4874 }
f48ff2ae 4875 else
29b0f896 4876 {
f48ff2ae 4877 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4878 switch (t->operands)
4879 {
c0f3af97
L		 4880 case 5:
4881 overlap4 = operand_type_and (i.types[4],
4882 operand_types[4]);
d1cbb4db 4883 case 4:
c6fb90c8
L		 4884 overlap3 = operand_type_and (i.types[3],
4885 operand_types[3]);
d1cbb4db 4886 case 3:
c6fb90c8
L		 4887 overlap2 = operand_type_and (i.types[2],
4888 operand_types[2]);
d1cbb4db
L		 4889 break;
4890 }
29b0f896 4891
f48ff2ae
L		 4892 switch (t->operands)
4893 {
c0f3af97
L		 4894 case 5:
4895 if (!operand_type_match (overlap4, i.types[4])
4896 || !operand_type_register_match (overlap3,
4897 i.types[3],
4898 operand_types[3],
4899 overlap4,
4900 i.types[4],
4901 operand_types[4]))
4902 continue;
f48ff2ae 4903 case 4:
40fb9820 4904 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4905 || (check_register
4906 && !operand_type_register_match (overlap2,
4907 i.types[2],
4908 operand_types[2],
4909 overlap3,
4910 i.types[3],
4911 operand_types[3])))
f48ff2ae
L		 4912 continue;
4913 case 3:
4914 /* Here we make use of the fact that there are no
4915 reverse match 3 operand instructions, and all 3
4916 operand instructions only need to be checked for
4917 register consistency between operands 2 and 3. */
40fb9820 4918 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4919 || (check_register
4920 && !operand_type_register_match (overlap1,
4921 i.types[1],
4922 operand_types[1],
4923 overlap2,
4924 i.types[2],
4925 operand_types[2])))
f48ff2ae
L		 4926 continue;
4927 break;
4928 }
29b0f896 4929 }
f48ff2ae 4930 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4931 slip through to break. */
4932 }
3629bb00 4933 if (!found_cpu_match)
29b0f896
AM		 4934 {
4935 found_reverse_match = 0;
4936 continue;
4937 }
c0f3af97 4938
5614d22c
JB		 4939 /* Check if vector and VEX operands are valid. */
4940 if (check_VecOperands (t) || VEX_check_operands (t))
4941 {
4942 specific_error = i.error;
4943 continue;
4944 }
a683cc34 4945
29b0f896
AM		 4946 /* We've found a match; break out of loop. */
4947 break;
4948 }
4949
4950 if (t == current_templates->end)
4951 {
4952 /* We found no match. */
a65babc9 4953 const char *err_msg;
5614d22c 4954 switch (specific_error ? specific_error : i.error)
a65babc9
L		 4955 {
4956 default:
4957 abort ();
86e026a4 4958 case operand_size_mismatch:
a65babc9
L		 4959 err_msg = _("operand size mismatch");
4960 break;
4961 case operand_type_mismatch:
4962 err_msg = _("operand type mismatch");
4963 break;
4964 case register_type_mismatch:
4965 err_msg = _("register type mismatch");
4966 break;
4967 case number_of_operands_mismatch:
4968 err_msg = _("number of operands mismatch");
4969 break;
4970 case invalid_instruction_suffix:
4971 err_msg = _("invalid instruction suffix");
4972 break;
4973 case bad_imm4:
4a2608e3 4974 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 4975 break;
4976 case old_gcc_only:
4977 err_msg = _("only supported with old gcc");
4978 break;
4979 case unsupported_with_intel_mnemonic:
4980 err_msg = _("unsupported with Intel mnemonic");
4981 break;
4982 case unsupported_syntax:
4983 err_msg = _("unsupported syntax");
4984 break;
4985 case unsupported:
35262a23 4986 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 4987 current_templates->start->name);
4988 return NULL;
6c30d220
L		 4989 case invalid_vsib_address:
4990 err_msg = _("invalid VSIB address");
4991 break;
7bab8ab5
JB		 4992 case invalid_vector_register_set:
4993 err_msg = _("mask, index, and destination registers must be distinct");
4994 break;
6c30d220
L		 4995 case unsupported_vector_index_register:
4996 err_msg = _("unsupported vector index register");
4997 break;
43234a1e
L		 4998 case unsupported_broadcast:
4999 err_msg = _("unsupported broadcast");
5000 break;
5001 case broadcast_not_on_src_operand:
5002 err_msg = _("broadcast not on source memory operand");
5003 break;
5004 case broadcast_needed:
5005 err_msg = _("broadcast is needed for operand of such type");
5006 break;
5007 case unsupported_masking:
5008 err_msg = _("unsupported masking");
5009 break;
5010 case mask_not_on_destination:
5011 err_msg = _("mask not on destination operand");
5012 break;
5013 case no_default_mask:
5014 err_msg = _("default mask isn't allowed");
5015 break;
5016 case unsupported_rc_sae:
5017 err_msg = _("unsupported static rounding/sae");
5018 break;
5019 case rc_sae_operand_not_last_imm:
5020 if (intel_syntax)
5021 err_msg = _("RC/SAE operand must precede immediate operands");
5022 else
5023 err_msg = _("RC/SAE operand must follow immediate operands");
5024 break;
5025 case invalid_register_operand:
5026 err_msg = _("invalid register operand");
5027 break;
a65babc9
L		 5028 }
5029 as_bad (_("%s for `%s'"), err_msg,
891edac4 5030 current_templates->start->name);
fa99fab2 5031 return NULL;
29b0f896 5032 }
252b5132 5033
29b0f896
AM		 5034 if (!quiet_warnings)
5035 {
5036 if (!intel_syntax
40fb9820
L		 5037 && (i.types[0].bitfield.jumpabsolute
5038 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5039 {
5040 as_warn (_("indirect %s without `*'"), t->name);
5041 }
5042
40fb9820
L		 5043 if (t->opcode_modifier.isprefix
5044 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5045 {
5046 /* Warn them that a data or address size prefix doesn't
5047 affect assembly of the next line of code. */
5048 as_warn (_("stand-alone `%s' prefix"), t->name);
5049 }
5050 }
5051
5052 /* Copy the template we found. */
5053 i.tm = *t;
539e75ad
L		 5054
5055 if (addr_prefix_disp != -1)
5056 i.tm.operand_types[addr_prefix_disp]
5057 = operand_types[addr_prefix_disp];
5058
29b0f896
AM		 5059 if (found_reverse_match)
5060 {
5061 /* If we found a reverse match we must alter the opcode
5062 direction bit. found_reverse_match holds bits to change
5063 (different for int & float insns). */
5064
5065 i.tm.base_opcode ^= found_reverse_match;
5066
539e75ad
L		 5067 i.tm.operand_types[0] = operand_types[1];
5068 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5069 }
5070
fa99fab2 5071 return t;
29b0f896
AM		 5072}
5073
5074static int
e3bb37b5 5075check_string (void)
29b0f896 5076{
40fb9820
L		 5077 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5078 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5079 {
5080 if (i.seg[0] != NULL && i.seg[0] != &es)
5081 {
a87af027 5082 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5083 i.tm.name,
a87af027
JB		 5084 mem_op + 1,
5085 register_prefix);
29b0f896
AM		 5086 return 0;
5087 }
5088 /* There's only ever one segment override allowed per instruction.
5089 This instruction possibly has a legal segment override on the
5090 second operand, so copy the segment to where non-string
5091 instructions store it, allowing common code. */
5092 i.seg[0] = i.seg[1];
5093 }
40fb9820 5094 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5095 {
5096 if (i.seg[1] != NULL && i.seg[1] != &es)
5097 {
a87af027 5098 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5099 i.tm.name,
a87af027
JB		 5100 mem_op + 2,
5101 register_prefix);
29b0f896
AM		 5102 return 0;
5103 }
5104 }
5105 return 1;
5106}
5107
5108static int
543613e9 5109process_suffix (void)
29b0f896
AM		 5110{
5111 /* If matched instruction specifies an explicit instruction mnemonic
5112 suffix, use it. */
40fb9820
L		 5113 if (i.tm.opcode_modifier.size16)
5114 i.suffix = WORD_MNEM_SUFFIX;
5115 else if (i.tm.opcode_modifier.size32)
5116 i.suffix = LONG_MNEM_SUFFIX;
5117 else if (i.tm.opcode_modifier.size64)
5118 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5119 else if (i.reg_operands)
5120 {
5121 /* If there's no instruction mnemonic suffix we try to invent one
5122 based on register operands. */
5123 if (!i.suffix)
5124 {
5125 /* We take i.suffix from the last register operand specified,
5126 Destination register type is more significant than source
381d071f
L		 5127 register type. crc32 in SSE4.2 prefers source register
5128 type. */
5129 if (i.tm.base_opcode == 0xf20f38f1)
5130 {
40fb9820
L		 5131 if (i.types[0].bitfield.reg16)
5132 i.suffix = WORD_MNEM_SUFFIX;
5133 else if (i.types[0].bitfield.reg32)
5134 i.suffix = LONG_MNEM_SUFFIX;
5135 else if (i.types[0].bitfield.reg64)
5136 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5137 }
9344ff29 5138 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5139 {
40fb9820 5140 if (i.types[0].bitfield.reg8)
20592a94
L		 5141 i.suffix = BYTE_MNEM_SUFFIX;
5142 }
381d071f
L		 5143
5144 if (!i.suffix)
5145 {
5146 int op;
5147
20592a94
L		 5148 if (i.tm.base_opcode == 0xf20f38f1
5149 || i.tm.base_opcode == 0xf20f38f0)
5150 {
5151 /* We have to know the operand size for crc32. */
5152 as_bad (_("ambiguous memory operand size for `%s`"),
5153 i.tm.name);
5154 return 0;
5155 }
5156
381d071f 5157 for (op = i.operands; --op >= 0;)
40fb9820 5158 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5159 {
40fb9820
L		 5160 if (i.types[op].bitfield.reg8)
5161 {
5162 i.suffix = BYTE_MNEM_SUFFIX;
5163 break;
5164 }
5165 else if (i.types[op].bitfield.reg16)
5166 {
5167 i.suffix = WORD_MNEM_SUFFIX;
5168 break;
5169 }
5170 else if (i.types[op].bitfield.reg32)
5171 {
5172 i.suffix = LONG_MNEM_SUFFIX;
5173 break;
5174 }
5175 else if (i.types[op].bitfield.reg64)
5176 {
5177 i.suffix = QWORD_MNEM_SUFFIX;
5178 break;
5179 }
381d071f
L		 5180 }
5181 }
29b0f896
AM		 5182 }
5183 else if (i.suffix == BYTE_MNEM_SUFFIX)
5184 {
2eb952a4
L		 5185 if (intel_syntax
5186 && i.tm.opcode_modifier.ignoresize
5187 && i.tm.opcode_modifier.no_bsuf)
5188 i.suffix = 0;
5189 else if (!check_byte_reg ())
29b0f896
AM		 5190 return 0;
5191 }
5192 else if (i.suffix == LONG_MNEM_SUFFIX)
5193 {
2eb952a4
L		 5194 if (intel_syntax
5195 && i.tm.opcode_modifier.ignoresize
5196 && i.tm.opcode_modifier.no_lsuf)
5197 i.suffix = 0;
5198 else if (!check_long_reg ())
29b0f896
AM		 5199 return 0;
5200 }
5201 else if (i.suffix == QWORD_MNEM_SUFFIX)
5202 {
955e1e6a
L		 5203 if (intel_syntax
5204 && i.tm.opcode_modifier.ignoresize
5205 && i.tm.opcode_modifier.no_qsuf)
5206 i.suffix = 0;
5207 else if (!check_qword_reg ())
29b0f896
AM		 5208 return 0;
5209 }
5210 else if (i.suffix == WORD_MNEM_SUFFIX)
5211 {
2eb952a4
L		 5212 if (intel_syntax
5213 && i.tm.opcode_modifier.ignoresize
5214 && i.tm.opcode_modifier.no_wsuf)
5215 i.suffix = 0;
5216 else if (!check_word_reg ())
29b0f896
AM		 5217 return 0;
5218 }
c0f3af97 5219 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5220 || i.suffix == YMMWORD_MNEM_SUFFIX
5221 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5222 {
43234a1e 5223 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5224 should check if it is a valid suffix. */
5225 }
40fb9820 5226 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5227 /* Do nothing if the instruction is going to ignore the prefix. */
5228 ;
5229 else
5230 abort ();
5231 }
40fb9820 5232 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5233 && !i.suffix
5234 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5235 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5236 {
5237 i.suffix = stackop_size;
5238 }
9306ca4a
JB		 5239 else if (intel_syntax
5240 && !i.suffix
40fb9820
L		 5241 && (i.tm.operand_types[0].bitfield.jumpabsolute
5242 || i.tm.opcode_modifier.jumpbyte
5243 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5244 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5245 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5246 {
5247 switch (flag_code)
5248 {
5249 case CODE_64BIT:
40fb9820 5250 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5251 {
5252 i.suffix = QWORD_MNEM_SUFFIX;
5253 break;
5254 }
5255 case CODE_32BIT:
40fb9820 5256 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5257 i.suffix = LONG_MNEM_SUFFIX;
5258 break;
5259 case CODE_16BIT:
40fb9820 5260 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5261 i.suffix = WORD_MNEM_SUFFIX;
5262 break;
5263 }
5264 }
252b5132 5265
9306ca4a 5266 if (!i.suffix)
29b0f896 5267 {
9306ca4a
JB		 5268 if (!intel_syntax)
5269 {
40fb9820 5270 if (i.tm.opcode_modifier.w)
9306ca4a 5271 {
4eed87de
AM		 5272 as_bad (_("no instruction mnemonic suffix given and "
5273 "no register operands; can't size instruction"));
9306ca4a
JB		 5274 return 0;
5275 }
5276 }
5277 else
5278 {
40fb9820 5279 unsigned int suffixes;
7ab9ffdd 5280
40fb9820
L		 5281 suffixes = !i.tm.opcode_modifier.no_bsuf;
5282 if (!i.tm.opcode_modifier.no_wsuf)
5283 suffixes |= 1 << 1;
5284 if (!i.tm.opcode_modifier.no_lsuf)
5285 suffixes |= 1 << 2;
fc4adea1 5286 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5287 suffixes |= 1 << 3;
5288 if (!i.tm.opcode_modifier.no_ssuf)
5289 suffixes |= 1 << 4;
5290 if (!i.tm.opcode_modifier.no_qsuf)
5291 suffixes |= 1 << 5;
5292
5293 /* There are more than suffix matches. */
5294 if (i.tm.opcode_modifier.w
9306ca4a 5295 || ((suffixes & (suffixes - 1))
40fb9820
L		 5296 && !i.tm.opcode_modifier.defaultsize
5297 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5298 {
5299 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5300 return 0;
5301 }
5302 }
29b0f896 5303 }
252b5132 5304
9306ca4a
JB		 5305 /* Change the opcode based on the operand size given by i.suffix;
5306 We don't need to change things for byte insns. */
5307
582d5edd
L		 5308 if (i.suffix
5309 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5310 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5311 && i.suffix != YMMWORD_MNEM_SUFFIX
5312 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5313 {
5314 /* It's not a byte, select word/dword operation. */
40fb9820 5315 if (i.tm.opcode_modifier.w)
29b0f896 5316 {
40fb9820 5317 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5318 i.tm.base_opcode |= 8;
5319 else
5320 i.tm.base_opcode |= 1;
5321 }
0f3f3d8b 5322
29b0f896
AM		 5323 /* Now select between word & dword operations via the operand
5324 size prefix, except for instructions that will ignore this
5325 prefix anyway. */
ca61edf2 5326 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5327 {
ca61edf2
L		 5328 /* The address size override prefix changes the size of the
5329 first operand. */
40fb9820
L		 5330 if ((flag_code == CODE_32BIT
5331 && i.op->regs[0].reg_type.bitfield.reg16)
5332 || (flag_code != CODE_32BIT
5333 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5334 if (!add_prefix (ADDR_PREFIX_OPCODE))
5335 return 0;
5336 }
5337 else if (i.suffix != QWORD_MNEM_SUFFIX
5338 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5339 && !i.tm.opcode_modifier.ignoresize
5340 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5341 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5342 || (flag_code == CODE_64BIT
40fb9820 5343 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5344 {
5345 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5346
40fb9820 5347 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5348 prefix = ADDR_PREFIX_OPCODE;
252b5132 5349
29b0f896
AM		 5350 if (!add_prefix (prefix))
5351 return 0;
24eab124 5352 }
252b5132 5353
29b0f896
AM		 5354 /* Set mode64 for an operand. */
5355 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5356 && flag_code == CODE_64BIT
40fb9820 5357 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5358 {
5359 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5360 need rex64. cmpxchg8b is also a special case. */
5361 if (! (i.operands == 2
5362 && i.tm.base_opcode == 0x90
5363 && i.tm.extension_opcode == None
0dfbf9d7
L		 5364 && operand_type_equal (&i.types [0], &acc64)
5365 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5366 && ! (i.operands == 1
5367 && i.tm.base_opcode == 0xfc7
5368 && i.tm.extension_opcode == 1
40fb9820
L		 5369 && !operand_type_check (i.types [0], reg)
5370 && operand_type_check (i.types [0], anymem)))
f6bee062 5371 i.rex |= REX_W;
46e883c5 5372 }
3e73aa7c 5373
29b0f896
AM		 5374 /* Size floating point instruction. */
5375 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5376 if (i.tm.opcode_modifier.floatmf)
543613e9 5377 i.tm.base_opcode ^= 4;
29b0f896 5378 }
7ecd2f8b 5379
29b0f896
AM		 5380 return 1;
5381}
3e73aa7c 5382
29b0f896 5383static int
543613e9 5384check_byte_reg (void)
29b0f896
AM		 5385{
5386 int op;
543613e9 5387
29b0f896
AM		 5388 for (op = i.operands; --op >= 0;)
5389 {
5390 /* If this is an eight bit register, it's OK. If it's the 16 or
5391 32 bit version of an eight bit register, we will just use the
5392 low portion, and that's OK too. */
40fb9820 5393 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5394 continue;
5395
5a819eb9
JB		 5396 /* I/O port address operands are OK too. */
5397 if (i.tm.operand_types[op].bitfield.inoutportreg)
5398 continue;
5399
9344ff29
L		 5400 /* crc32 doesn't generate this warning. */
5401 if (i.tm.base_opcode == 0xf20f38f0)
5402 continue;
5403
40fb9820
L		 5404 if ((i.types[op].bitfield.reg16
5405 || i.types[op].bitfield.reg32
5406 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5407 && i.op[op].regs->reg_num < 4
5408 /* Prohibit these changes in 64bit mode, since the lowering
5409 would be more complicated. */
5410 && flag_code != CODE_64BIT)
29b0f896 5411 {
29b0f896 5412#if REGISTER_WARNINGS
5a819eb9 5413 if (!quiet_warnings)
a540244d
L		 5414 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5415 register_prefix,
40fb9820 5416 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5417 ? REGNAM_AL - REGNAM_AX
5418 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5419 register_prefix,
29b0f896
AM		 5420 i.op[op].regs->reg_name,
5421 i.suffix);
5422#endif
5423 continue;
5424 }
5425 /* Any other register is bad. */
40fb9820
L		 5426 if (i.types[op].bitfield.reg16
5427 || i.types[op].bitfield.reg32
5428 || i.types[op].bitfield.reg64
5429 || i.types[op].bitfield.regmmx
5430 || i.types[op].bitfield.regxmm
c0f3af97 5431 || i.types[op].bitfield.regymm
43234a1e 5432 || i.types[op].bitfield.regzmm
40fb9820
L		 5433 || i.types[op].bitfield.sreg2
5434 || i.types[op].bitfield.sreg3
5435 || i.types[op].bitfield.control
5436 || i.types[op].bitfield.debug
5437 || i.types[op].bitfield.test
5438 || i.types[op].bitfield.floatreg
5439 || i.types[op].bitfield.floatacc)
29b0f896 5440 {
a540244d
L		 5441 as_bad (_("`%s%s' not allowed with `%s%c'"),
5442 register_prefix,
29b0f896
AM		 5443 i.op[op].regs->reg_name,
5444 i.tm.name,
5445 i.suffix);
5446 return 0;
5447 }
5448 }
5449 return 1;
5450}
5451
5452static int
e3bb37b5 5453check_long_reg (void)
29b0f896
AM		 5454{
5455 int op;
5456
5457 for (op = i.operands; --op >= 0;)
5458 /* Reject eight bit registers, except where the template requires
5459 them. (eg. movzb) */
40fb9820
L		 5460 if (i.types[op].bitfield.reg8
5461 && (i.tm.operand_types[op].bitfield.reg16
5462 || i.tm.operand_types[op].bitfield.reg32
5463 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5464 {
a540244d
L		 5465 as_bad (_("`%s%s' not allowed with `%s%c'"),
5466 register_prefix,
29b0f896
AM		 5467 i.op[op].regs->reg_name,
5468 i.tm.name,
5469 i.suffix);
5470 return 0;
5471 }
e4630f71 5472 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5473 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5474 && i.types[op].bitfield.reg16
5475 && (i.tm.operand_types[op].bitfield.reg32
5476 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5477 {
5478 /* Prohibit these changes in the 64bit mode, since the
5479 lowering is more complicated. */
5480 if (flag_code == CODE_64BIT)
252b5132 5481 {
2b5d6a91 5482 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5483 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5484 i.suffix);
5485 return 0;
252b5132 5486 }
29b0f896 5487#if REGISTER_WARNINGS
cecf1424
JB		 5488 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5489 register_prefix,
5490 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5491 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5492#endif
252b5132 5493 }
e4630f71 5494 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5495 else if (i.types[op].bitfield.reg64
5496 && (i.tm.operand_types[op].bitfield.reg32
5497 || i.tm.operand_types[op].bitfield.acc))
252b5132 5498 {
34828aad 5499 if (intel_syntax
ca61edf2 5500 && i.tm.opcode_modifier.toqword
40fb9820 5501 && !i.types[0].bitfield.regxmm)
34828aad 5502 {
ca61edf2 5503 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5504 i.suffix = QWORD_MNEM_SUFFIX;
5505 }
5506 else
5507 {
2b5d6a91 5508 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5509 register_prefix, i.op[op].regs->reg_name,
5510 i.suffix);
5511 return 0;
5512 }
29b0f896
AM		 5513 }
5514 return 1;
5515}
252b5132 5516
29b0f896 5517static int
e3bb37b5 5518check_qword_reg (void)
29b0f896
AM		 5519{
5520 int op;
252b5132 5521
29b0f896
AM		 5522 for (op = i.operands; --op >= 0; )
5523 /* Reject eight bit registers, except where the template requires
5524 them. (eg. movzb) */
40fb9820
L		 5525 if (i.types[op].bitfield.reg8
5526 && (i.tm.operand_types[op].bitfield.reg16
5527 || i.tm.operand_types[op].bitfield.reg32
5528 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5529 {
a540244d
L		 5530 as_bad (_("`%s%s' not allowed with `%s%c'"),
5531 register_prefix,
29b0f896
AM		 5532 i.op[op].regs->reg_name,
5533 i.tm.name,
5534 i.suffix);
5535 return 0;
5536 }
e4630f71 5537 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5538 else if ((i.types[op].bitfield.reg16
5539 || i.types[op].bitfield.reg32)
5540 && (i.tm.operand_types[op].bitfield.reg32
5541 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5542 {
5543 /* Prohibit these changes in the 64bit mode, since the
5544 lowering is more complicated. */
34828aad 5545 if (intel_syntax
ca61edf2 5546 && i.tm.opcode_modifier.todword
40fb9820 5547 && !i.types[0].bitfield.regxmm)
34828aad 5548 {
ca61edf2 5549 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5550 i.suffix = LONG_MNEM_SUFFIX;
5551 }
5552 else
5553 {
2b5d6a91 5554 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5555 register_prefix, i.op[op].regs->reg_name,
5556 i.suffix);
5557 return 0;
5558 }
252b5132 5559 }
29b0f896
AM		 5560 return 1;
5561}
252b5132 5562
29b0f896 5563static int
e3bb37b5 5564check_word_reg (void)
29b0f896
AM		 5565{
5566 int op;
5567 for (op = i.operands; --op >= 0;)
5568 /* Reject eight bit registers, except where the template requires
5569 them. (eg. movzb) */
40fb9820
L		 5570 if (i.types[op].bitfield.reg8
5571 && (i.tm.operand_types[op].bitfield.reg16
5572 || i.tm.operand_types[op].bitfield.reg32
5573 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5574 {
a540244d
L		 5575 as_bad (_("`%s%s' not allowed with `%s%c'"),
5576 register_prefix,
29b0f896
AM		 5577 i.op[op].regs->reg_name,
5578 i.tm.name,
5579 i.suffix);
5580 return 0;
5581 }
e4630f71 5582 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5583 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5584 && (i.types[op].bitfield.reg32
5585 || i.types[op].bitfield.reg64)
40fb9820
L		 5586 && (i.tm.operand_types[op].bitfield.reg16
5587 || i.tm.operand_types[op].bitfield.acc))
252b5132 5588 {
29b0f896
AM		 5589 /* Prohibit these changes in the 64bit mode, since the
5590 lowering is more complicated. */
5591 if (flag_code == CODE_64BIT)
252b5132 5592 {
2b5d6a91 5593 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5594 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5595 i.suffix);
5596 return 0;
252b5132 5597 }
29b0f896 5598#if REGISTER_WARNINGS
cecf1424
JB		 5599 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5600 register_prefix,
5601 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5602 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5603#endif
5604 }
5605 return 1;
5606}
252b5132 5607
29b0f896 5608static int
40fb9820 5609update_imm (unsigned int j)
29b0f896 5610{
bc0844ae 5611 i386_operand_type overlap = i.types[j];
40fb9820
L		 5612 if ((overlap.bitfield.imm8
5613 || overlap.bitfield.imm8s
5614 || overlap.bitfield.imm16
5615 || overlap.bitfield.imm32
5616 || overlap.bitfield.imm32s
5617 || overlap.bitfield.imm64)
0dfbf9d7
L		 5618 && !operand_type_equal (&overlap, &imm8)
5619 && !operand_type_equal (&overlap, &imm8s)
5620 && !operand_type_equal (&overlap, &imm16)
5621 && !operand_type_equal (&overlap, &imm32)
5622 && !operand_type_equal (&overlap, &imm32s)
5623 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5624 {
5625 if (i.suffix)
5626 {
40fb9820
L		 5627 i386_operand_type temp;
5628
0dfbf9d7 5629 operand_type_set (&temp, 0);
7ab9ffdd 5630 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5631 {
5632 temp.bitfield.imm8 = overlap.bitfield.imm8;
5633 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5634 }
5635 else if (i.suffix == WORD_MNEM_SUFFIX)
5636 temp.bitfield.imm16 = overlap.bitfield.imm16;
5637 else if (i.suffix == QWORD_MNEM_SUFFIX)
5638 {
5639 temp.bitfield.imm64 = overlap.bitfield.imm64;
5640 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5641 }
5642 else
5643 temp.bitfield.imm32 = overlap.bitfield.imm32;
5644 overlap = temp;
29b0f896 5645 }
0dfbf9d7
L		 5646 else if (operand_type_equal (&overlap, &imm16_32_32s)
5647 || operand_type_equal (&overlap, &imm16_32)
5648 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5649 {
40fb9820 5650 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5651 overlap = imm16;
40fb9820 5652 else
65da13b5 5653 overlap = imm32s;
29b0f896 5654 }
0dfbf9d7
L		 5655 if (!operand_type_equal (&overlap, &imm8)
5656 && !operand_type_equal (&overlap, &imm8s)
5657 && !operand_type_equal (&overlap, &imm16)
5658 && !operand_type_equal (&overlap, &imm32)
5659 && !operand_type_equal (&overlap, &imm32s)
5660 && !operand_type_equal (&overlap, &imm64))
29b0f896 5661 {
4eed87de
AM		 5662 as_bad (_("no instruction mnemonic suffix given; "
5663 "can't determine immediate size"));
29b0f896
AM		 5664 return 0;
5665 }
5666 }
40fb9820 5667 i.types[j] = overlap;
29b0f896 5668
40fb9820
L		 5669 return 1;
5670}
5671
5672static int
5673finalize_imm (void)
5674{
bc0844ae 5675 unsigned int j, n;
29b0f896 5676
bc0844ae
L		 5677 /* Update the first 2 immediate operands. */
5678 n = i.operands > 2 ? 2 : i.operands;
5679 if (n)
5680 {
5681 for (j = 0; j < n; j++)
5682 if (update_imm (j) == 0)
5683 return 0;
40fb9820 5684
bc0844ae
L		 5685 /* The 3rd operand can't be immediate operand. */
5686 gas_assert (operand_type_check (i.types[2], imm) == 0);
5687 }
29b0f896
AM		 5688
5689 return 1;
5690}
5691
c0f3af97
L		 5692static int
5693bad_implicit_operand (int xmm)
5694{
91d6fa6a
NC		 5695 const char *ireg = xmm ? "xmm0" : "ymm0";
5696
c0f3af97
L		 5697 if (intel_syntax)
5698 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5699 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5700 else
5701 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5702 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5703 return 0;
5704}
5705
29b0f896 5706static int
e3bb37b5 5707process_operands (void)
29b0f896
AM		 5708{
5709 /* Default segment register this instruction will use for memory
5710 accesses. 0 means unknown. This is only for optimizing out
5711 unnecessary segment overrides. */
5712 const seg_entry *default_seg = 0;
5713
2426c15f 5714 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5715 {
91d6fa6a
NC		 5716 unsigned int dupl = i.operands;
5717 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5718 unsigned int j;
5719
c0f3af97 5720 /* The destination must be an xmm register. */
9c2799c2 5721 gas_assert (i.reg_operands
91d6fa6a 5722 && MAX_OPERANDS > dupl
7ab9ffdd 5723 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5724
5725 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5726 {
c0f3af97 5727 /* The first operand is implicit and must be xmm0. */
9c2799c2 5728 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5729 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5730 return bad_implicit_operand (1);
5731
8cd7925b 5732 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5733 {
5734 /* Keep xmm0 for instructions with VEX prefix and 3
5735 sources. */
5736 goto duplicate;
5737 }
e2ec9d29 5738 else
c0f3af97
L		 5739 {
5740 /* We remove the first xmm0 and keep the number of
5741 operands unchanged, which in fact duplicates the
5742 destination. */
5743 for (j = 1; j < i.operands; j++)
5744 {
5745 i.op[j - 1] = i.op[j];
5746 i.types[j - 1] = i.types[j];
5747 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5748 }
5749 }
5750 }
5751 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5752 {
91d6fa6a 5753 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5754 && (i.tm.opcode_modifier.vexsources
5755 == VEX3SOURCES));
c0f3af97
L		 5756
5757 /* Add the implicit xmm0 for instructions with VEX prefix
5758 and 3 sources. */
5759 for (j = i.operands; j > 0; j--)
5760 {
5761 i.op[j] = i.op[j - 1];
5762 i.types[j] = i.types[j - 1];
5763 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5764 }
5765 i.op[0].regs
5766 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5767 i.types[0] = regxmm;
c0f3af97
L		 5768 i.tm.operand_types[0] = regxmm;
5769
5770 i.operands += 2;
5771 i.reg_operands += 2;
5772 i.tm.operands += 2;
5773
91d6fa6a 5774 dupl++;
c0f3af97 5775 dest++;
91d6fa6a
NC		 5776 i.op[dupl] = i.op[dest];
5777 i.types[dupl] = i.types[dest];
5778 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5779 }
c0f3af97
L		 5780 else
5781 {
5782duplicate:
5783 i.operands++;
5784 i.reg_operands++;
5785 i.tm.operands++;
5786
91d6fa6a
NC		 5787 i.op[dupl] = i.op[dest];
5788 i.types[dupl] = i.types[dest];
5789 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5790 }
5791
5792 if (i.tm.opcode_modifier.immext)
5793 process_immext ();
5794 }
5795 else if (i.tm.opcode_modifier.firstxmm0)
5796 {
5797 unsigned int j;
5798
43234a1e 5799 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5800 gas_assert (i.reg_operands
7ab9ffdd 5801 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5802 || operand_type_equal (&i.types[0], &regymm)
5803 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5804 if (register_number (i.op[0].regs) != 0)
c0f3af97 5805 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5806
5807 for (j = 1; j < i.operands; j++)
5808 {
5809 i.op[j - 1] = i.op[j];
5810 i.types[j - 1] = i.types[j];
5811
5812 /* We need to adjust fields in i.tm since they are used by
5813 build_modrm_byte. */
5814 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5815 }
5816
e2ec9d29
L		 5817 i.operands--;
5818 i.reg_operands--;
e2ec9d29
L		 5819 i.tm.operands--;
5820 }
5821 else if (i.tm.opcode_modifier.regkludge)
5822 {
5823 /* The imul $imm, %reg instruction is converted into
5824 imul $imm, %reg, %reg, and the clr %reg instruction
5825 is converted into xor %reg, %reg. */
5826
5827 unsigned int first_reg_op;
5828
5829 if (operand_type_check (i.types[0], reg))
5830 first_reg_op = 0;
5831 else
5832 first_reg_op = 1;
5833 /* Pretend we saw the extra register operand. */
9c2799c2 5834 gas_assert (i.reg_operands == 1
7ab9ffdd 5835 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5836 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5837 i.types[first_reg_op + 1] = i.types[first_reg_op];
5838 i.operands++;
5839 i.reg_operands++;
29b0f896
AM		 5840 }
5841
40fb9820 5842 if (i.tm.opcode_modifier.shortform)
29b0f896 5843 {
40fb9820
L		 5844 if (i.types[0].bitfield.sreg2
5845 || i.types[0].bitfield.sreg3)
29b0f896 5846 {
4eed87de
AM		 5847 if (i.tm.base_opcode == POP_SEG_SHORT
5848 && i.op[0].regs->reg_num == 1)
29b0f896 5849 {
a87af027 5850 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5851 return 0;
29b0f896 5852 }
4eed87de
AM		 5853 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5854 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5855 i.rex |= REX_B;
4eed87de
AM		 5856 }
5857 else
5858 {
7ab9ffdd 5859 /* The register or float register operand is in operand
85f10a01 5860 0 or 1. */
40fb9820 5861 unsigned int op;
7ab9ffdd
L		 5862
5863 if (i.types[0].bitfield.floatreg
5864 || operand_type_check (i.types[0], reg))
5865 op = 0;
5866 else
5867 op = 1;
4eed87de
AM		 5868 /* Register goes in low 3 bits of opcode. */
5869 i.tm.base_opcode |= i.op[op].regs->reg_num;
5870 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5871 i.rex |= REX_B;
40fb9820 5872 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5873 {
4eed87de
AM		 5874 /* Warn about some common errors, but press on regardless.
5875 The first case can be generated by gcc (<= 2.8.1). */
5876 if (i.operands == 2)
5877 {
5878 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5879 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5880 register_prefix, i.op[!intel_syntax].regs->reg_name,
5881 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5882 }
5883 else
5884 {
5885 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5886 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5887 register_prefix, i.op[0].regs->reg_name);
4eed87de 5888 }
29b0f896
AM		 5889 }
5890 }
5891 }
40fb9820 5892 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5893 {
5894 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5895 must be put into the modrm byte). Now, we make the modrm and
5896 index base bytes based on all the info we've collected. */
29b0f896
AM		 5897
5898 default_seg = build_modrm_byte ();
5899 }
8a2ed489 5900 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5901 {
5902 default_seg = &ds;
5903 }
40fb9820 5904 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5905 {
5906 /* For the string instructions that allow a segment override
5907 on one of their operands, the default segment is ds. */
5908 default_seg = &ds;
5909 }
5910
75178d9d
L		 5911 if (i.tm.base_opcode == 0x8d /* lea */
5912 && i.seg[0]
5913 && !quiet_warnings)
30123838 5914 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5915
5916 /* If a segment was explicitly specified, and the specified segment
5917 is not the default, use an opcode prefix to select it. If we
5918 never figured out what the default segment is, then default_seg
5919 will be zero at this point, and the specified segment prefix will
5920 always be used. */
29b0f896
AM		 5921 if ((i.seg[0]) && (i.seg[0] != default_seg))
5922 {
5923 if (!add_prefix (i.seg[0]->seg_prefix))
5924 return 0;
5925 }
5926 return 1;
5927}
5928
5929static const seg_entry *
e3bb37b5 5930build_modrm_byte (void)
29b0f896
AM		 5931{
5932 const seg_entry *default_seg = 0;
c0f3af97 5933 unsigned int source, dest;
8cd7925b 5934 int vex_3_sources;
c0f3af97
L		 5935
5936 /* The first operand of instructions with VEX prefix and 3 sources
5937 must be VEX_Imm4. */
8cd7925b 5938 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5939 if (vex_3_sources)
5940 {
91d6fa6a 5941 unsigned int nds, reg_slot;
4c2c6516 5942 expressionS *exp;
c0f3af97 5943
922d8de8 5944 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5945 && i.tm.opcode_modifier.immext)
5946 {
5947 dest = i.operands - 2;
5948 gas_assert (dest == 3);
5949 }
922d8de8 5950 else
a683cc34 5951 dest = i.operands - 1;
c0f3af97 5952 nds = dest - 1;
922d8de8 5953
a683cc34
SP		 5954 /* There are 2 kinds of instructions:
5955 1. 5 operands: 4 register operands or 3 register operands
5956 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 5957 VexW0 or VexW1. The destination must be either XMM, YMM or
5958 ZMM register.
a683cc34
SP		 5959 2. 4 operands: 4 register operands or 3 register operands
5960 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5961 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5962 || (i.reg_operands == 3 && i.mem_operands == 1))
5963 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5964 && (i.tm.opcode_modifier.veximmext
5965 || (i.imm_operands == 1
5966 && i.types[0].bitfield.vec_imm4
5967 && (i.tm.opcode_modifier.vexw == VEXW0
5968 || i.tm.opcode_modifier.vexw == VEXW1)
5969 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 5970 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
5971 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 5972
5973 if (i.imm_operands == 0)
5974 {
5975 /* When there is no immediate operand, generate an 8bit
5976 immediate operand to encode the first operand. */
5977 exp = &im_expressions[i.imm_operands++];
5978 i.op[i.operands].imms = exp;
5979 i.types[i.operands] = imm8;
5980 i.operands++;
5981 /* If VexW1 is set, the first operand is the source and
5982 the second operand is encoded in the immediate operand. */
5983 if (i.tm.opcode_modifier.vexw == VEXW1)
5984 {
5985 source = 0;
5986 reg_slot = 1;
5987 }
5988 else
5989 {
5990 source = 1;
5991 reg_slot = 0;
5992 }
5993
5994 /* FMA swaps REG and NDS. */
5995 if (i.tm.cpu_flags.bitfield.cpufma)
5996 {
5997 unsigned int tmp;
5998 tmp = reg_slot;
5999 reg_slot = nds;
6000 nds = tmp;
6001 }
6002
24981e7b
L		 6003 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6004 &regxmm)
a683cc34 6005 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6006 &regymm)
6007 || operand_type_equal (&i.tm.operand_types[reg_slot],
6008 &regzmm));
a683cc34 6009 exp->X_op = O_constant;
4c692bc7 6010 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6011 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6012 }
922d8de8 6013 else
a683cc34
SP		 6014 {
6015 unsigned int imm_slot;
6016
6017 if (i.tm.opcode_modifier.vexw == VEXW0)
6018 {
6019 /* If VexW0 is set, the third operand is the source and
6020 the second operand is encoded in the immediate
6021 operand. */
6022 source = 2;
6023 reg_slot = 1;
6024 }
6025 else
6026 {
6027 /* VexW1 is set, the second operand is the source and
6028 the third operand is encoded in the immediate
6029 operand. */
6030 source = 1;
6031 reg_slot = 2;
6032 }
6033
6034 if (i.tm.opcode_modifier.immext)
6035 {
6036 /* When ImmExt is set, the immdiate byte is the last
6037 operand. */
6038 imm_slot = i.operands - 1;
6039 source--;
6040 reg_slot--;
6041 }
6042 else
6043 {
6044 imm_slot = 0;
6045
6046 /* Turn on Imm8 so that output_imm will generate it. */
6047 i.types[imm_slot].bitfield.imm8 = 1;
6048 }
6049
24981e7b
L		 6050 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6051 &regxmm)
6052 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6053 &regymm)
6054 || operand_type_equal (&i.tm.operand_types[reg_slot],
6055 &regzmm));
a683cc34 6056 i.op[imm_slot].imms->X_add_number
4c692bc7 6057 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6058 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6059 }
6060
6061 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6062 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6063 &regymm)
6064 || operand_type_equal (&i.tm.operand_types[nds],
6065 &regzmm));
dae39acc 6066 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6067 }
6068 else
6069 source = dest = 0;
29b0f896
AM		 6070
6071 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6072 implicit registers do not count. If there are 3 register
6073 operands, it must be a instruction with VexNDS. For a
6074 instruction with VexNDD, the destination register is encoded
6075 in VEX prefix. If there are 4 register operands, it must be
6076 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6077 if (i.mem_operands == 0
6078 && ((i.reg_operands == 2
2426c15f 6079 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6080 || (i.reg_operands == 3
2426c15f 6081 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6082 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6083 {
cab737b9
L		 6084 switch (i.operands)
6085 {
6086 case 2:
6087 source = 0;
6088 break;
6089 case 3:
c81128dc
L		 6090 /* When there are 3 operands, one of them may be immediate,
6091 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6092 the first operand must be shift count register (cl) or it
6093 is an instruction with VexNDS. */
9c2799c2 6094 gas_assert (i.imm_operands == 1
7ab9ffdd 6095 || (i.imm_operands == 0
2426c15f 6096 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6097 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6098 if (operand_type_check (i.types[0], imm)
6099 || i.types[0].bitfield.shiftcount)
6100 source = 1;
6101 else
6102 source = 0;
cab737b9
L		 6103 break;
6104 case 4:
368d64cc
L		 6105 /* When there are 4 operands, the first two must be 8bit
6106 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6107 one.
6108
6109 For instructions with VexNDS, if the first operand
6110 an imm8, the source operand is the 2nd one. If the last
6111 operand is imm8, the source operand is the first one. */
9c2799c2 6112 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6113 && i.types[0].bitfield.imm8
6114 && i.types[1].bitfield.imm8)
2426c15f 6115 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6116 && i.imm_operands == 1
6117 && (i.types[0].bitfield.imm8
43234a1e
L		 6118 || i.types[i.operands - 1].bitfield.imm8
6119 || i.rounding)));
9f2670f2
L		 6120 if (i.imm_operands == 2)
6121 source = 2;
6122 else
c0f3af97
L		 6123 {
6124 if (i.types[0].bitfield.imm8)
6125 source = 1;
6126 else
6127 source = 0;
6128 }
c0f3af97
L		 6129 break;
6130 case 5:
43234a1e
L		 6131 if (i.tm.opcode_modifier.evex)
6132 {
6133 /* For EVEX instructions, when there are 5 operands, the
6134 first one must be immediate operand. If the second one
6135 is immediate operand, the source operand is the 3th
6136 one. If the last one is immediate operand, the source
6137 operand is the 2nd one. */
6138 gas_assert (i.imm_operands == 2
6139 && i.tm.opcode_modifier.sae
6140 && operand_type_check (i.types[0], imm));
6141 if (operand_type_check (i.types[1], imm))
6142 source = 2;
6143 else if (operand_type_check (i.types[4], imm))
6144 source = 1;
6145 else
6146 abort ();
6147 }
cab737b9
L		 6148 break;
6149 default:
6150 abort ();
6151 }
6152
c0f3af97
L		 6153 if (!vex_3_sources)
6154 {
6155 dest = source + 1;
6156
43234a1e
L		 6157 /* RC/SAE operand could be between DEST and SRC. That happens
6158 when one operand is GPR and the other one is XMM/YMM/ZMM
6159 register. */
6160 if (i.rounding && i.rounding->operand == (int) dest)
6161 dest++;
6162
2426c15f 6163 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6164 {
43234a1e
L		 6165 /* For instructions with VexNDS, the register-only source
6166 operand must be 32/64bit integer, XMM, YMM or ZMM
6167 register. It is encoded in VEX prefix. We need to
6168 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6169
6170 i386_operand_type op;
6171 unsigned int vvvv;
6172
6173 /* Check register-only source operand when two source
6174 operands are swapped. */
6175 if (!i.tm.operand_types[source].bitfield.baseindex
6176 && i.tm.operand_types[dest].bitfield.baseindex)
6177 {
6178 vvvv = source;
6179 source = dest;
6180 }
6181 else
6182 vvvv = dest;
6183
6184 op = i.tm.operand_types[vvvv];
fa99fab2 6185 op.bitfield.regmem = 0;
c0f3af97 6186 if ((dest + 1) >= i.operands
ac4eb736
AM		 6187 || (!op.bitfield.reg32
6188 && op.bitfield.reg64
f12dc422 6189 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6190 && !operand_type_equal (&op, &regymm)
6191 && !operand_type_equal (&op, &regzmm)
6192 && !operand_type_equal (&op, &regmask)))
c0f3af97 6193 abort ();
f12dc422 6194 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6195 dest++;
6196 }
6197 }
29b0f896
AM		 6198
6199 i.rm.mode = 3;
6200 /* One of the register operands will be encoded in the i.tm.reg
6201 field, the other in the combined i.tm.mode and i.tm.regmem
6202 fields. If no form of this instruction supports a memory
6203 destination operand, then we assume the source operand may
6204 sometimes be a memory operand and so we need to store the
6205 destination in the i.rm.reg field. */
40fb9820
L		 6206 if (!i.tm.operand_types[dest].bitfield.regmem
6207 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6208 {
6209 i.rm.reg = i.op[dest].regs->reg_num;
6210 i.rm.regmem = i.op[source].regs->reg_num;
6211 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6212 i.rex |= REX_R;
43234a1e
L		 6213 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6214 i.vrex |= REX_R;
29b0f896 6215 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6216 i.rex |= REX_B;
43234a1e
L		 6217 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6218 i.vrex |= REX_B;
29b0f896
AM		 6219 }
6220 else
6221 {
6222 i.rm.reg = i.op[source].regs->reg_num;
6223 i.rm.regmem = i.op[dest].regs->reg_num;
6224 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6225 i.rex |= REX_B;
43234a1e
L		 6226 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6227 i.vrex |= REX_B;
29b0f896 6228 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6229 i.rex |= REX_R;
43234a1e
L		 6230 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6231 i.vrex |= REX_R;
29b0f896 6232 }
161a04f6 6233 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6234 {
40fb9820
L		 6235 if (!i.types[0].bitfield.control
6236 && !i.types[1].bitfield.control)
c4a530c5 6237 abort ();
161a04f6 6238 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6239 add_prefix (LOCK_PREFIX_OPCODE);
6240 }
29b0f896
AM		 6241 }
6242 else
6243 { /* If it's not 2 reg operands... */
c0f3af97
L		 6244 unsigned int mem;
6245
29b0f896
AM		 6246 if (i.mem_operands)
6247 {
6248 unsigned int fake_zero_displacement = 0;
99018f42 6249 unsigned int op;
4eed87de 6250
7ab9ffdd
L		 6251 for (op = 0; op < i.operands; op++)
6252 if (operand_type_check (i.types[op], anymem))
6253 break;
7ab9ffdd 6254 gas_assert (op < i.operands);
29b0f896 6255
6c30d220
L		 6256 if (i.tm.opcode_modifier.vecsib)
6257 {
6258 if (i.index_reg->reg_num == RegEiz
6259 || i.index_reg->reg_num == RegRiz)
6260 abort ();
6261
6262 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6263 if (!i.base_reg)
6264 {
6265 i.sib.base = NO_BASE_REGISTER;
6266 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6267 /* No Vec_Disp8 if there is no base. */
6268 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6269 i.types[op].bitfield.disp8 = 0;
6270 i.types[op].bitfield.disp16 = 0;
6271 i.types[op].bitfield.disp64 = 0;
6272 if (flag_code != CODE_64BIT)
6273 {
6274 /* Must be 32 bit */
6275 i.types[op].bitfield.disp32 = 1;
6276 i.types[op].bitfield.disp32s = 0;
6277 }
6278 else
6279 {
6280 i.types[op].bitfield.disp32 = 0;
6281 i.types[op].bitfield.disp32s = 1;
6282 }
6283 }
6284 i.sib.index = i.index_reg->reg_num;
6285 if ((i.index_reg->reg_flags & RegRex) != 0)
6286 i.rex |= REX_X;
43234a1e
L		 6287 if ((i.index_reg->reg_flags & RegVRex) != 0)
6288 i.vrex |= REX_X;
6c30d220
L		 6289 }
6290
29b0f896
AM		 6291 default_seg = &ds;
6292
6293 if (i.base_reg == 0)
6294 {
6295 i.rm.mode = 0;
6296 if (!i.disp_operands)
6c30d220
L		 6297 {
6298 fake_zero_displacement = 1;
6299 /* Instructions with VSIB byte need 32bit displacement
6300 if there is no base register. */
6301 if (i.tm.opcode_modifier.vecsib)
6302 i.types[op].bitfield.disp32 = 1;
6303 }
29b0f896
AM		 6304 if (i.index_reg == 0)
6305 {
6c30d220 6306 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6307 /* Operand is just <disp> */
20f0a1fc 6308 if (flag_code == CODE_64BIT)
29b0f896
AM		 6309 {
6310 /* 64bit mode overwrites the 32bit absolute
6311 addressing by RIP relative addressing and
6312 absolute addressing is encoded by one of the
6313 redundant SIB forms. */
6314 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6315 i.sib.base = NO_BASE_REGISTER;
6316 i.sib.index = NO_INDEX_REGISTER;
fc225355 6317 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6318 ? disp32s : disp32);
20f0a1fc 6319 }
fc225355
L		 6320 else if ((flag_code == CODE_16BIT)
6321 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6322 {
6323 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6324 i.types[op] = disp16;
20f0a1fc
NC		 6325 }
6326 else
6327 {
6328 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6329 i.types[op] = disp32;
29b0f896
AM		 6330 }
6331 }
6c30d220 6332 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6333 {
6c30d220 6334 /* !i.base_reg && i.index_reg */
db51cc60
L		 6335 if (i.index_reg->reg_num == RegEiz
6336 || i.index_reg->reg_num == RegRiz)
6337 i.sib.index = NO_INDEX_REGISTER;
6338 else
6339 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6340 i.sib.base = NO_BASE_REGISTER;
6341 i.sib.scale = i.log2_scale_factor;
6342 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6343 /* No Vec_Disp8 if there is no base. */
6344 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6345 i.types[op].bitfield.disp8 = 0;
6346 i.types[op].bitfield.disp16 = 0;
6347 i.types[op].bitfield.disp64 = 0;
29b0f896 6348 if (flag_code != CODE_64BIT)
40fb9820
L		 6349 {
6350 /* Must be 32 bit */
6351 i.types[op].bitfield.disp32 = 1;
6352 i.types[op].bitfield.disp32s = 0;
6353 }
29b0f896 6354 else
40fb9820
L		 6355 {
6356 i.types[op].bitfield.disp32 = 0;
6357 i.types[op].bitfield.disp32s = 1;
6358 }
29b0f896 6359 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6360 i.rex |= REX_X;
29b0f896
AM		 6361 }
6362 }
6363 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6364 else if (i.base_reg->reg_num == RegRip ||
6365 i.base_reg->reg_num == RegEip)
29b0f896 6366 {
6c30d220 6367 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6368 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6369 i.types[op].bitfield.disp8 = 0;
6370 i.types[op].bitfield.disp16 = 0;
6371 i.types[op].bitfield.disp32 = 0;
6372 i.types[op].bitfield.disp32s = 1;
6373 i.types[op].bitfield.disp64 = 0;
43234a1e 6374 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6375 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6376 if (! i.disp_operands)
6377 fake_zero_displacement = 1;
29b0f896 6378 }
40fb9820 6379 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6380 {
6c30d220 6381 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6382 switch (i.base_reg->reg_num)
6383 {
6384 case 3: /* (%bx) */
6385 if (i.index_reg == 0)
6386 i.rm.regmem = 7;
6387 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6388 i.rm.regmem = i.index_reg->reg_num - 6;
6389 break;
6390 case 5: /* (%bp) */
6391 default_seg = &ss;
6392 if (i.index_reg == 0)
6393 {
6394 i.rm.regmem = 6;
40fb9820 6395 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6396 {
6397 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6398 if (i.tm.operand_types[op].bitfield.vec_disp8)
6399 i.types[op].bitfield.vec_disp8 = 1;
6400 else
6401 i.types[op].bitfield.disp8 = 1;
252b5132 6402 fake_zero_displacement = 1;
29b0f896
AM		 6403 }
6404 }
6405 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6406 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6407 break;
6408 default: /* (%si) -> 4 or (%di) -> 5 */
6409 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6410 }
6411 i.rm.mode = mode_from_disp_size (i.types[op]);
6412 }
6413 else /* i.base_reg and 32/64 bit mode */
6414 {
6415 if (flag_code == CODE_64BIT
40fb9820
L		 6416 && operand_type_check (i.types[op], disp))
6417 {
6418 i386_operand_type temp;
0dfbf9d7 6419 operand_type_set (&temp, 0);
40fb9820 6420 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6421 temp.bitfield.vec_disp8
6422 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6423 i.types[op] = temp;
6424 if (i.prefix[ADDR_PREFIX] == 0)
6425 i.types[op].bitfield.disp32s = 1;
6426 else
6427 i.types[op].bitfield.disp32 = 1;
6428 }
20f0a1fc 6429
6c30d220
L		 6430 if (!i.tm.opcode_modifier.vecsib)
6431 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6432 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6433 i.rex |= REX_B;
29b0f896
AM		 6434 i.sib.base = i.base_reg->reg_num;
6435 /* x86-64 ignores REX prefix bit here to avoid decoder
6436 complications. */
848930b2
JB		 6437 if (!(i.base_reg->reg_flags & RegRex)
6438 && (i.base_reg->reg_num == EBP_REG_NUM
6439 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6440 default_seg = &ss;
848930b2 6441 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6442 {
848930b2 6443 fake_zero_displacement = 1;
43234a1e
L		 6444 if (i.tm.operand_types [op].bitfield.vec_disp8)
6445 i.types[op].bitfield.vec_disp8 = 1;
6446 else
6447 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6448 }
6449 i.sib.scale = i.log2_scale_factor;
6450 if (i.index_reg == 0)
6451 {
6c30d220 6452 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6453 /* <disp>(%esp) becomes two byte modrm with no index
6454 register. We've already stored the code for esp
6455 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6456 Any base register besides %esp will not use the
6457 extra modrm byte. */
6458 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6459 }
6c30d220 6460 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6461 {
db51cc60
L		 6462 if (i.index_reg->reg_num == RegEiz
6463 || i.index_reg->reg_num == RegRiz)
6464 i.sib.index = NO_INDEX_REGISTER;
6465 else
6466 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6467 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6468 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6469 i.rex |= REX_X;
29b0f896 6470 }
67a4f2b7
AO		 6471
6472 if (i.disp_operands
6473 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6474 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6475 i.rm.mode = 0;
6476 else
a501d77e
L		 6477 {
6478 if (!fake_zero_displacement
6479 && !i.disp_operands
6480 && i.disp_encoding)
6481 {
6482 fake_zero_displacement = 1;
6483 if (i.disp_encoding == disp_encoding_8bit)
6484 i.types[op].bitfield.disp8 = 1;
6485 else
6486 i.types[op].bitfield.disp32 = 1;
6487 }
6488 i.rm.mode = mode_from_disp_size (i.types[op]);
6489 }
29b0f896 6490 }
252b5132 6491
29b0f896
AM		 6492 if (fake_zero_displacement)
6493 {
6494 /* Fakes a zero displacement assuming that i.types[op]
6495 holds the correct displacement size. */
6496 expressionS *exp;
6497
9c2799c2 6498 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6499 exp = &disp_expressions[i.disp_operands++];
6500 i.op[op].disps = exp;
6501 exp->X_op = O_constant;
6502 exp->X_add_number = 0;
6503 exp->X_add_symbol = (symbolS *) 0;
6504 exp->X_op_symbol = (symbolS *) 0;
6505 }
c0f3af97
L		 6506
6507 mem = op;
29b0f896 6508 }
c0f3af97
L		 6509 else
6510 mem = ~0;
252b5132 6511
8c43a48b 6512 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6513 {
6514 if (operand_type_check (i.types[0], imm))
6515 i.vex.register_specifier = NULL;
6516 else
6517 {
6518 /* VEX.vvvv encodes one of the sources when the first
6519 operand is not an immediate. */
1ef99a7b 6520 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6521 i.vex.register_specifier = i.op[0].regs;
6522 else
6523 i.vex.register_specifier = i.op[1].regs;
6524 }
6525
6526 /* Destination is a XMM register encoded in the ModRM.reg
6527 and VEX.R bit. */
6528 i.rm.reg = i.op[2].regs->reg_num;
6529 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6530 i.rex |= REX_R;
6531
6532 /* ModRM.rm and VEX.B encodes the other source. */
6533 if (!i.mem_operands)
6534 {
6535 i.rm.mode = 3;
6536
1ef99a7b 6537 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6538 i.rm.regmem = i.op[1].regs->reg_num;
6539 else
6540 i.rm.regmem = i.op[0].regs->reg_num;
6541
6542 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6543 i.rex |= REX_B;
6544 }
6545 }
2426c15f 6546 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6547 {
6548 i.vex.register_specifier = i.op[2].regs;
6549 if (!i.mem_operands)
6550 {
6551 i.rm.mode = 3;
6552 i.rm.regmem = i.op[1].regs->reg_num;
6553 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6554 i.rex |= REX_B;
6555 }
6556 }
29b0f896
AM		 6557 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6558 (if any) based on i.tm.extension_opcode. Again, we must be
6559 careful to make sure that segment/control/debug/test/MMX
6560 registers are coded into the i.rm.reg field. */
f88c9eb0 6561 else if (i.reg_operands)
29b0f896 6562 {
99018f42 6563 unsigned int op;
7ab9ffdd
L		 6564 unsigned int vex_reg = ~0;
6565
6566 for (op = 0; op < i.operands; op++)
6567 if (i.types[op].bitfield.reg8
6568 || i.types[op].bitfield.reg16
6569 || i.types[op].bitfield.reg32
6570 || i.types[op].bitfield.reg64
6571 || i.types[op].bitfield.regmmx
6572 || i.types[op].bitfield.regxmm
6573 || i.types[op].bitfield.regymm
7e8b059b 6574 || i.types[op].bitfield.regbnd
43234a1e
L		 6575 || i.types[op].bitfield.regzmm
6576 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6577 || i.types[op].bitfield.sreg2
6578 || i.types[op].bitfield.sreg3
6579 || i.types[op].bitfield.control
6580 || i.types[op].bitfield.debug
6581 || i.types[op].bitfield.test)
6582 break;
c0209578 6583
7ab9ffdd
L		 6584 if (vex_3_sources)
6585 op = dest;
2426c15f 6586 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6587 {
6588 /* For instructions with VexNDS, the register-only
6589 source operand is encoded in VEX prefix. */
6590 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6591
7ab9ffdd 6592 if (op > mem)
c0f3af97 6593 {
7ab9ffdd
L		 6594 vex_reg = op++;
6595 gas_assert (op < i.operands);
c0f3af97
L		 6596 }
6597 else
c0f3af97 6598 {
f12dc422
L		 6599 /* Check register-only source operand when two source
6600 operands are swapped. */
6601 if (!i.tm.operand_types[op].bitfield.baseindex
6602 && i.tm.operand_types[op + 1].bitfield.baseindex)
6603 {
6604 vex_reg = op;
6605 op += 2;
6606 gas_assert (mem == (vex_reg + 1)
6607 && op < i.operands);
6608 }
6609 else
6610 {
6611 vex_reg = op + 1;
6612 gas_assert (vex_reg < i.operands);
6613 }
c0f3af97 6614 }
7ab9ffdd 6615 }
2426c15f 6616 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6617 {
f12dc422 6618 /* For instructions with VexNDD, the register destination
7ab9ffdd 6619 is encoded in VEX prefix. */
f12dc422
L		 6620 if (i.mem_operands == 0)
6621 {
6622 /* There is no memory operand. */
6623 gas_assert ((op + 2) == i.operands);
6624 vex_reg = op + 1;
6625 }
6626 else
8d63c93e 6627 {
f12dc422
L		 6628 /* There are only 2 operands. */
6629 gas_assert (op < 2 && i.operands == 2);
6630 vex_reg = 1;
6631 }
7ab9ffdd
L		 6632 }
6633 else
6634 gas_assert (op < i.operands);
99018f42 6635
7ab9ffdd
L		 6636 if (vex_reg != (unsigned int) ~0)
6637 {
f12dc422 6638 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6639
f12dc422
L		 6640 if (type->bitfield.reg32 != 1
6641 && type->bitfield.reg64 != 1
6642 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6643 && !operand_type_equal (type, &regymm)
6644 && !operand_type_equal (type, &regzmm)
6645 && !operand_type_equal (type, &regmask))
7ab9ffdd 6646 abort ();
f88c9eb0 6647
7ab9ffdd
L		 6648 i.vex.register_specifier = i.op[vex_reg].regs;
6649 }
6650
1b9f0c97
L		 6651 /* Don't set OP operand twice. */
6652 if (vex_reg != op)
7ab9ffdd 6653 {
1b9f0c97
L		 6654 /* If there is an extension opcode to put here, the
6655 register number must be put into the regmem field. */
6656 if (i.tm.extension_opcode != None)
6657 {
6658 i.rm.regmem = i.op[op].regs->reg_num;
6659 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6660 i.rex |= REX_B;
43234a1e
L		 6661 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6662 i.vrex |= REX_B;
1b9f0c97
L		 6663 }
6664 else
6665 {
6666 i.rm.reg = i.op[op].regs->reg_num;
6667 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6668 i.rex |= REX_R;
43234a1e
L		 6669 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6670 i.vrex |= REX_R;
1b9f0c97 6671 }
7ab9ffdd 6672 }
252b5132 6673
29b0f896
AM		 6674 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6675 must set it to 3 to indicate this is a register operand
6676 in the regmem field. */
6677 if (!i.mem_operands)
6678 i.rm.mode = 3;
6679 }
252b5132 6680
29b0f896 6681 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6682 if (i.tm.extension_opcode != None)
29b0f896
AM		 6683 i.rm.reg = i.tm.extension_opcode;
6684 }
6685 return default_seg;
6686}
252b5132 6687
29b0f896 6688static void
e3bb37b5 6689output_branch (void)
29b0f896
AM		 6690{
6691 char *p;
f8a5c266 6692 int size;
29b0f896
AM		 6693 int code16;
6694 int prefix;
6695 relax_substateT subtype;
6696 symbolS *sym;
6697 offsetT off;
6698
f8a5c266 6699 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6700 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6701
6702 prefix = 0;
6703 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6704 {
29b0f896
AM		 6705 prefix = 1;
6706 i.prefixes -= 1;
6707 code16 ^= CODE16;
252b5132 6708 }
29b0f896
AM		 6709 /* Pentium4 branch hints. */
6710 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6711 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6712 {
29b0f896
AM		 6713 prefix++;
6714 i.prefixes--;
6715 }
6716 if (i.prefix[REX_PREFIX] != 0)
6717 {
6718 prefix++;
6719 i.prefixes--;
2f66722d
AM		 6720 }
6721
7e8b059b
L		 6722 /* BND prefixed jump. */
6723 if (i.prefix[BND_PREFIX] != 0)
6724 {
6725 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6726 i.prefixes -= 1;
6727 }
6728
29b0f896
AM		 6729 if (i.prefixes != 0 && !intel_syntax)
6730 as_warn (_("skipping prefixes on this instruction"));
6731
6732 /* It's always a symbol; End frag & setup for relax.
6733 Make sure there is enough room in this frag for the largest
6734 instruction we may generate in md_convert_frag. This is 2
6735 bytes for the opcode and room for the prefix and largest
6736 displacement. */
6737 frag_grow (prefix + 2 + 4);
6738 /* Prefix and 1 opcode byte go in fr_fix. */
6739 p = frag_more (prefix + 1);
6740 if (i.prefix[DATA_PREFIX] != 0)
6741 *p++ = DATA_PREFIX_OPCODE;
6742 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6743 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6744 *p++ = i.prefix[SEG_PREFIX];
6745 if (i.prefix[REX_PREFIX] != 0)
6746 *p++ = i.prefix[REX_PREFIX];
6747 *p = i.tm.base_opcode;
6748
6749 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6750 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6751 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6752 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6753 else
f8a5c266 6754 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6755 subtype |= code16;
3e73aa7c 6756
29b0f896
AM		 6757 sym = i.op[0].disps->X_add_symbol;
6758 off = i.op[0].disps->X_add_number;
3e73aa7c 6759
29b0f896
AM		 6760 if (i.op[0].disps->X_op != O_constant
6761 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6762 {
29b0f896
AM		 6763 /* Handle complex expressions. */
6764 sym = make_expr_symbol (i.op[0].disps);
6765 off = 0;
6766 }
3e73aa7c 6767
29b0f896
AM		 6768 /* 1 possible extra opcode + 4 byte displacement go in var part.
6769 Pass reloc in fr_var. */
d258b828 6770 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 6771}
3e73aa7c 6772
29b0f896 6773static void
e3bb37b5 6774output_jump (void)
29b0f896
AM		 6775{
6776 char *p;
6777 int size;
3e02c1cc 6778 fixS *fixP;
29b0f896 6779
40fb9820 6780 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6781 {
6782 /* This is a loop or jecxz type instruction. */
6783 size = 1;
6784 if (i.prefix[ADDR_PREFIX] != 0)
6785 {
6786 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6787 i.prefixes -= 1;
6788 }
6789 /* Pentium4 branch hints. */
6790 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6791 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6792 {
6793 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6794 i.prefixes--;
3e73aa7c
JH		 6795 }
6796 }
29b0f896
AM		 6797 else
6798 {
6799 int code16;
3e73aa7c 6800
29b0f896
AM		 6801 code16 = 0;
6802 if (flag_code == CODE_16BIT)
6803 code16 = CODE16;
3e73aa7c 6804
29b0f896
AM		 6805 if (i.prefix[DATA_PREFIX] != 0)
6806 {
6807 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6808 i.prefixes -= 1;
6809 code16 ^= CODE16;
6810 }
252b5132 6811
29b0f896
AM		 6812 size = 4;
6813 if (code16)
6814 size = 2;
6815 }
9fcc94b6 6816
29b0f896
AM		 6817 if (i.prefix[REX_PREFIX] != 0)
6818 {
6819 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6820 i.prefixes -= 1;
6821 }
252b5132 6822
7e8b059b
L		 6823 /* BND prefixed jump. */
6824 if (i.prefix[BND_PREFIX] != 0)
6825 {
6826 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6827 i.prefixes -= 1;
6828 }
6829
29b0f896
AM		 6830 if (i.prefixes != 0 && !intel_syntax)
6831 as_warn (_("skipping prefixes on this instruction"));
e0890092 6832
42164a71
L		 6833 p = frag_more (i.tm.opcode_length + size);
6834 switch (i.tm.opcode_length)
6835 {
6836 case 2:
6837 *p++ = i.tm.base_opcode >> 8;
6838 case 1:
6839 *p++ = i.tm.base_opcode;
6840 break;
6841 default:
6842 abort ();
6843 }
e0890092 6844
3e02c1cc 6845 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6846 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 6847
6848 /* All jumps handled here are signed, but don't use a signed limit
6849 check for 32 and 16 bit jumps as we want to allow wrap around at
6850 4G and 64k respectively. */
6851 if (size == 1)
6852 fixP->fx_signed = 1;
29b0f896 6853}
e0890092 6854
29b0f896 6855static void
e3bb37b5 6856output_interseg_jump (void)
29b0f896
AM		 6857{
6858 char *p;
6859 int size;
6860 int prefix;
6861 int code16;
252b5132 6862
29b0f896
AM		 6863 code16 = 0;
6864 if (flag_code == CODE_16BIT)
6865 code16 = CODE16;
a217f122 6866
29b0f896
AM		 6867 prefix = 0;
6868 if (i.prefix[DATA_PREFIX] != 0)
6869 {
6870 prefix = 1;
6871 i.prefixes -= 1;
6872 code16 ^= CODE16;
6873 }
6874 if (i.prefix[REX_PREFIX] != 0)
6875 {
6876 prefix++;
6877 i.prefixes -= 1;
6878 }
252b5132 6879
29b0f896
AM		 6880 size = 4;
6881 if (code16)
6882 size = 2;
252b5132 6883
29b0f896
AM		 6884 if (i.prefixes != 0 && !intel_syntax)
6885 as_warn (_("skipping prefixes on this instruction"));
252b5132 6886
29b0f896
AM		 6887 /* 1 opcode; 2 segment; offset */
6888 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6889
29b0f896
AM		 6890 if (i.prefix[DATA_PREFIX] != 0)
6891 *p++ = DATA_PREFIX_OPCODE;
252b5132 6892
29b0f896
AM		 6893 if (i.prefix[REX_PREFIX] != 0)
6894 *p++ = i.prefix[REX_PREFIX];
252b5132 6895
29b0f896
AM		 6896 *p++ = i.tm.base_opcode;
6897 if (i.op[1].imms->X_op == O_constant)
6898 {
6899 offsetT n = i.op[1].imms->X_add_number;
252b5132 6900
29b0f896
AM		 6901 if (size == 2
6902 && !fits_in_unsigned_word (n)
6903 && !fits_in_signed_word (n))
6904 {
6905 as_bad (_("16-bit jump out of range"));
6906 return;
6907 }
6908 md_number_to_chars (p, n, size);
6909 }
6910 else
6911 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6912 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 6913 if (i.op[0].imms->X_op != O_constant)
6914 as_bad (_("can't handle non absolute segment in `%s'"),
6915 i.tm.name);
6916 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6917}
a217f122 6918
29b0f896 6919static void
e3bb37b5 6920output_insn (void)
29b0f896 6921{
2bbd9c25
JJ		 6922 fragS *insn_start_frag;
6923 offsetT insn_start_off;
6924
29b0f896
AM		 6925 /* Tie dwarf2 debug info to the address at the start of the insn.
6926 We can't do this after the insn has been output as the current
6927 frag may have been closed off. eg. by frag_var. */
6928 dwarf2_emit_insn (0);
6929
2bbd9c25
JJ		 6930 insn_start_frag = frag_now;
6931 insn_start_off = frag_now_fix ();
6932
29b0f896 6933 /* Output jumps. */
40fb9820 6934 if (i.tm.opcode_modifier.jump)
29b0f896 6935 output_branch ();
40fb9820
L		 6936 else if (i.tm.opcode_modifier.jumpbyte
6937 || i.tm.opcode_modifier.jumpdword)
29b0f896 6938 output_jump ();
40fb9820 6939 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6940 output_interseg_jump ();
6941 else
6942 {
6943 /* Output normal instructions here. */
6944 char *p;
6945 unsigned char *q;
47465058 6946 unsigned int j;
331d2d0d 6947 unsigned int prefix;
4dffcebc 6948
d022bddd
IT		 6949 /* Some processors fail on LOCK prefix. This options makes
6950 assembler ignore LOCK prefix and serves as a workaround. */
6951 if (omit_lock_prefix)
6952 {
6953 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
6954 return;
6955 i.prefix[LOCK_PREFIX] = 0;
6956 }
6957
43234a1e
L		 6958 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6959 don't need the explicit prefix. */
6960 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 6961 {
c0f3af97 6962 switch (i.tm.opcode_length)
bc4bd9ab 6963 {
c0f3af97
L		 6964 case 3:
6965 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6966 {
c0f3af97
L		 6967 prefix = (i.tm.base_opcode >> 24) & 0xff;
6968 goto check_prefix;
6969 }
6970 break;
6971 case 2:
6972 if ((i.tm.base_opcode & 0xff0000) != 0)
6973 {
6974 prefix = (i.tm.base_opcode >> 16) & 0xff;
6975 if (i.tm.cpu_flags.bitfield.cpupadlock)
6976 {
4dffcebc 6977check_prefix:
c0f3af97 6978 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6979 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6980 != REPE_PREFIX_OPCODE))
6981 add_prefix (prefix);
6982 }
6983 else
4dffcebc
L		 6984 add_prefix (prefix);
6985 }
c0f3af97
L		 6986 break;
6987 case 1:
6988 break;
6989 default:
6990 abort ();
bc4bd9ab 6991 }
c0f3af97 6992
6d19a37a 6993#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 6994 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
6995 R_X86_64_GOTTPOFF relocation so that linker can safely
6996 perform IE->LE optimization. */
6997 if (x86_elf_abi == X86_64_X32_ABI
6998 && i.operands == 2
6999 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7000 && i.prefix[REX_PREFIX] == 0)
7001 add_prefix (REX_OPCODE);
6d19a37a 7002#endif
cf61b747 7003
c0f3af97
L		 7004 /* The prefix bytes. */
7005 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7006 if (*q)
7007 FRAG_APPEND_1_CHAR (*q);
0f10071e 7008 }
ae5c1c7b 7009 else
c0f3af97
L		 7010 {
7011 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7012 if (*q)
7013 switch (j)
7014 {
7015 case REX_PREFIX:
7016 /* REX byte is encoded in VEX prefix. */
7017 break;
7018 case SEG_PREFIX:
7019 case ADDR_PREFIX:
7020 FRAG_APPEND_1_CHAR (*q);
7021 break;
7022 default:
7023 /* There should be no other prefixes for instructions
7024 with VEX prefix. */
7025 abort ();
7026 }
7027
43234a1e
L		 7028 /* For EVEX instructions i.vrex should become 0 after
7029 build_evex_prefix. For VEX instructions upper 16 registers
7030 aren't available, so VREX should be 0. */
7031 if (i.vrex)
7032 abort ();
c0f3af97
L		 7033 /* Now the VEX prefix. */
7034 p = frag_more (i.vex.length);
7035 for (j = 0; j < i.vex.length; j++)
7036 p[j] = i.vex.bytes[j];
7037 }
252b5132 7038
29b0f896 7039 /* Now the opcode; be careful about word order here! */
4dffcebc 7040 if (i.tm.opcode_length == 1)
29b0f896
AM		 7041 {
7042 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7043 }
7044 else
7045 {
4dffcebc 7046 switch (i.tm.opcode_length)
331d2d0d 7047 {
43234a1e
L		 7048 case 4:
7049 p = frag_more (4);
7050 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7051 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7052 break;
4dffcebc 7053 case 3:
331d2d0d
L		 7054 p = frag_more (3);
7055 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7056 break;
7057 case 2:
7058 p = frag_more (2);
7059 break;
7060 default:
7061 abort ();
7062 break;
331d2d0d 7063 }
0f10071e 7064
29b0f896
AM		 7065 /* Put out high byte first: can't use md_number_to_chars! */
7066 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7067 *p = i.tm.base_opcode & 0xff;
7068 }
3e73aa7c 7069
29b0f896 7070 /* Now the modrm byte and sib byte (if present). */
40fb9820 7071 if (i.tm.opcode_modifier.modrm)
29b0f896 7072 {
4a3523fa
L		 7073 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7074 | i.rm.reg << 3
7075 | i.rm.mode << 6));
29b0f896
AM		 7076 /* If i.rm.regmem == ESP (4)
7077 && i.rm.mode != (Register mode)
7078 && not 16 bit
7079 ==> need second modrm byte. */
7080 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7081 && i.rm.mode != 3
40fb9820 7082 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7083 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7084 | i.sib.index << 3
7085 | i.sib.scale << 6));
29b0f896 7086 }
3e73aa7c 7087
29b0f896 7088 if (i.disp_operands)
2bbd9c25 7089 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7090
29b0f896 7091 if (i.imm_operands)
2bbd9c25 7092 output_imm (insn_start_frag, insn_start_off);
29b0f896 7093 }
252b5132 7094
29b0f896
AM		 7095#ifdef DEBUG386
7096 if (flag_debug)
7097 {
7b81dfbb 7098 pi ("" /*line*/, &i);
29b0f896
AM		 7099 }
7100#endif /* DEBUG386 */
7101}
252b5132 7102
e205caa7
L		 7103/* Return the size of the displacement operand N. */
7104
7105static int
7106disp_size (unsigned int n)
7107{
7108 int size = 4;
43234a1e
L		 7109
7110 /* Vec_Disp8 has to be 8bit. */
7111 if (i.types[n].bitfield.vec_disp8)
7112 size = 1;
7113 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7114 size = 8;
7115 else if (i.types[n].bitfield.disp8)
7116 size = 1;
7117 else if (i.types[n].bitfield.disp16)
7118 size = 2;
e205caa7
L		 7119 return size;
7120}
7121
7122/* Return the size of the immediate operand N. */
7123
7124static int
7125imm_size (unsigned int n)
7126{
7127 int size = 4;
40fb9820
L		 7128 if (i.types[n].bitfield.imm64)
7129 size = 8;
7130 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7131 size = 1;
7132 else if (i.types[n].bitfield.imm16)
7133 size = 2;
e205caa7
L		 7134 return size;
7135}
7136
29b0f896 7137static void
64e74474 7138output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7139{
7140 char *p;
7141 unsigned int n;
252b5132 7142
29b0f896
AM		 7143 for (n = 0; n < i.operands; n++)
7144 {
43234a1e
L		 7145 if (i.types[n].bitfield.vec_disp8
7146 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7147 {
7148 if (i.op[n].disps->X_op == O_constant)
7149 {
e205caa7 7150 int size = disp_size (n);
43234a1e 7151 offsetT val = i.op[n].disps->X_add_number;
252b5132 7152
43234a1e
L		 7153 if (i.types[n].bitfield.vec_disp8)
7154 val >>= i.memshift;
7155 val = offset_in_range (val, size);
29b0f896
AM		 7156 p = frag_more (size);
7157 md_number_to_chars (p, val, size);
7158 }
7159 else
7160 {
f86103b7 7161 enum bfd_reloc_code_real reloc_type;
e205caa7 7162 int size = disp_size (n);
40fb9820 7163 int sign = i.types[n].bitfield.disp32s;
29b0f896 7164 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7165 fixS *fixP;
29b0f896 7166
e205caa7 7167 /* We can't have 8 bit displacement here. */
9c2799c2 7168 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7169
29b0f896
AM		 7170 /* The PC relative address is computed relative
7171 to the instruction boundary, so in case immediate
7172 fields follows, we need to adjust the value. */
7173 if (pcrel && i.imm_operands)
7174 {
29b0f896 7175 unsigned int n1;
e205caa7 7176 int sz = 0;
252b5132 7177
29b0f896 7178 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7179 if (operand_type_check (i.types[n1], imm))
252b5132 7180 {
e205caa7
L		 7181 /* Only one immediate is allowed for PC
7182 relative address. */
9c2799c2 7183 gas_assert (sz == 0);
e205caa7
L		 7184 sz = imm_size (n1);
7185 i.op[n].disps->X_add_number -= sz;
252b5132 7186 }
29b0f896 7187 /* We should find the immediate. */
9c2799c2 7188 gas_assert (sz != 0);
29b0f896 7189 }
520dc8e8 7190
29b0f896 7191 p = frag_more (size);
d258b828 7192 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7193 if (GOT_symbol
2bbd9c25 7194 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7195 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7196 || reloc_type == BFD_RELOC_X86_64_32S
7197 || (reloc_type == BFD_RELOC_64
7198 && object_64bit))
d6ab8113
JB		 7199 && (i.op[n].disps->X_op == O_symbol
7200 || (i.op[n].disps->X_op == O_add
7201 && ((symbol_get_value_expression
7202 (i.op[n].disps->X_op_symbol)->X_op)
7203 == O_subtract))))
7204 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7205 {
7206 offsetT add;
7207
7208 if (insn_start_frag == frag_now)
7209 add = (p - frag_now->fr_literal) - insn_start_off;
7210 else
7211 {
7212 fragS *fr;
7213
7214 add = insn_start_frag->fr_fix - insn_start_off;
7215 for (fr = insn_start_frag->fr_next;
7216 fr && fr != frag_now; fr = fr->fr_next)
7217 add += fr->fr_fix;
7218 add += p - frag_now->fr_literal;
7219 }
7220
4fa24527 7221 if (!object_64bit)
7b81dfbb
AJ		 7222 {
7223 reloc_type = BFD_RELOC_386_GOTPC;
7224 i.op[n].imms->X_add_number += add;
7225 }
7226 else if (reloc_type == BFD_RELOC_64)
7227 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7228 else
7b81dfbb
AJ		 7229 /* Don't do the adjustment for x86-64, as there
7230 the pcrel addressing is relative to the _next_
7231 insn, and that is taken care of in other code. */
d6ab8113 7232 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7233 }
02a86693
L		 7234 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7235 size, i.op[n].disps, pcrel,
7236 reloc_type);
7237 /* Check for "call/jmp *mem", "mov mem, %reg",
7238 "test %reg, mem" and "binop mem, %reg" where binop
7239 is one of adc, add, and, cmp, or, sbb, sub, xor
7240 instructions. */
7241 if ((i.rm.mode == 2
7242 || (i.rm.mode == 0 && i.rm.regmem == 5))
7243 && ((i.operands == 1
7244 && i.tm.base_opcode == 0xff
7245 && (i.rm.reg == 2 || i.rm.reg == 4))
7246 || (i.operands == 2
7247 && (i.tm.base_opcode == 0x8b
7248 || i.tm.base_opcode == 0x85
7249 || (i.tm.base_opcode & 0xc7) == 0x03))))
7250 {
7251 if (object_64bit)
7252 {
7253 fixP->fx_tcbit = i.rex != 0;
7254 if (i.base_reg
7255 && (i.base_reg->reg_num == RegRip
7256 || i.base_reg->reg_num == RegEip))
7257 fixP->fx_tcbit2 = 1;
7258 }
7259 else
7260 fixP->fx_tcbit2 = 1;
7261 }
29b0f896
AM		 7262 }
7263 }
7264 }
7265}
252b5132 7266
29b0f896 7267static void
64e74474 7268output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7269{
7270 char *p;
7271 unsigned int n;
252b5132 7272
29b0f896
AM		 7273 for (n = 0; n < i.operands; n++)
7274 {
43234a1e
L		 7275 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7276 if (i.rounding && (int) n == i.rounding->operand)
7277 continue;
7278
40fb9820 7279 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7280 {
7281 if (i.op[n].imms->X_op == O_constant)
7282 {
e205caa7 7283 int size = imm_size (n);
29b0f896 7284 offsetT val;
b4cac588 7285
29b0f896
AM		 7286 val = offset_in_range (i.op[n].imms->X_add_number,
7287 size);
7288 p = frag_more (size);
7289 md_number_to_chars (p, val, size);
7290 }
7291 else
7292 {
7293 /* Not absolute_section.
7294 Need a 32-bit fixup (don't support 8bit
7295 non-absolute imms). Try to support other
7296 sizes ... */
f86103b7 7297 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7298 int size = imm_size (n);
7299 int sign;
29b0f896 7300
40fb9820 7301 if (i.types[n].bitfield.imm32s
a7d61044 7302 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7303 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7304 sign = 1;
e205caa7
L		 7305 else
7306 sign = 0;
520dc8e8 7307
29b0f896 7308 p = frag_more (size);
d258b828 7309 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7310
2bbd9c25
JJ		 7311 /* This is tough to explain. We end up with this one if we
7312 * have operands that look like
7313 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7314 * obtain the absolute address of the GOT, and it is strongly
7315 * preferable from a performance point of view to avoid using
7316 * a runtime relocation for this. The actual sequence of
7317 * instructions often look something like:
7318 *
7319 * call .L66
7320 * .L66:
7321 * popl %ebx
7322 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7323 *
7324 * The call and pop essentially return the absolute address
7325 * of the label .L66 and store it in %ebx. The linker itself
7326 * will ultimately change the first operand of the addl so
7327 * that %ebx points to the GOT, but to keep things simple, the
7328 * .o file must have this operand set so that it generates not
7329 * the absolute address of .L66, but the absolute address of
7330 * itself. This allows the linker itself simply treat a GOTPC
7331 * relocation as asking for a pcrel offset to the GOT to be
7332 * added in, and the addend of the relocation is stored in the
7333 * operand field for the instruction itself.
7334 *
7335 * Our job here is to fix the operand so that it would add
7336 * the correct offset so that %ebx would point to itself. The
7337 * thing that is tricky is that .-.L66 will point to the
7338 * beginning of the instruction, so we need to further modify
7339 * the operand so that it will point to itself. There are
7340 * other cases where you have something like:
7341 *
7342 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7343 *
7344 * and here no correction would be required. Internally in
7345 * the assembler we treat operands of this form as not being
7346 * pcrel since the '.' is explicitly mentioned, and I wonder
7347 * whether it would simplify matters to do it this way. Who
7348 * knows. In earlier versions of the PIC patches, the
7349 * pcrel_adjust field was used to store the correction, but
7350 * since the expression is not pcrel, I felt it would be
7351 * confusing to do it this way. */
7352
d6ab8113 7353 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7354 || reloc_type == BFD_RELOC_X86_64_32S
7355 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7356 && GOT_symbol
7357 && GOT_symbol == i.op[n].imms->X_add_symbol
7358 && (i.op[n].imms->X_op == O_symbol
7359 || (i.op[n].imms->X_op == O_add
7360 && ((symbol_get_value_expression
7361 (i.op[n].imms->X_op_symbol)->X_op)
7362 == O_subtract))))
7363 {
2bbd9c25
JJ		 7364 offsetT add;
7365
7366 if (insn_start_frag == frag_now)
7367 add = (p - frag_now->fr_literal) - insn_start_off;
7368 else
7369 {
7370 fragS *fr;
7371
7372 add = insn_start_frag->fr_fix - insn_start_off;
7373 for (fr = insn_start_frag->fr_next;
7374 fr && fr != frag_now; fr = fr->fr_next)
7375 add += fr->fr_fix;
7376 add += p - frag_now->fr_literal;
7377 }
7378
4fa24527 7379 if (!object_64bit)
d6ab8113 7380 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7381 else if (size == 4)
d6ab8113 7382 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7383 else if (size == 8)
7384 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7385 i.op[n].imms->X_add_number += add;
29b0f896 7386 }
29b0f896
AM		 7387 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7388 i.op[n].imms, 0, reloc_type);
7389 }
7390 }
7391 }
252b5132
RH		 7392}
7393\f
d182319b
JB		 7394/* x86_cons_fix_new is called via the expression parsing code when a
7395 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7396static int cons_sign = -1;
7397
7398void
e3bb37b5 7399x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7400 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7401{
d258b828 7402 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7403
7404#ifdef TE_PE
7405 if (exp->X_op == O_secrel)
7406 {
7407 exp->X_op = O_symbol;
7408 r = BFD_RELOC_32_SECREL;
7409 }
7410#endif
7411
7412 fix_new_exp (frag, off, len, exp, 0, r);
7413}
7414
357d1bd8
L		 7415/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7416 purpose of the `.dc.a' internal pseudo-op. */
7417
7418int
7419x86_address_bytes (void)
7420{
7421 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7422 return 4;
7423 return stdoutput->arch_info->bits_per_address / 8;
7424}
7425
d382c579
TG		 7426#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7427 || defined (LEX_AT)
d258b828 7428# define lex_got(reloc, adjust, types) NULL
718ddfc0 7429#else
f3c180ae
AM		 7430/* Parse operands of the form
7431 <symbol>@GOTOFF+<nnn>
7432 and similar .plt or .got references.
7433
7434 If we find one, set up the correct relocation in RELOC and copy the
7435 input string, minus the `@GOTOFF' into a malloc'd buffer for
7436 parsing by the calling routine. Return this buffer, and if ADJUST
7437 is non-null set it to the length of the string we removed from the
7438 input line. Otherwise return NULL. */
7439static char *
91d6fa6a 7440lex_got (enum bfd_reloc_code_real *rel,
64e74474 7441 int *adjust,
d258b828 7442 i386_operand_type *types)
f3c180ae 7443{
7b81dfbb
AJ		 7444 /* Some of the relocations depend on the size of what field is to
7445 be relocated. But in our callers i386_immediate and i386_displacement
7446 we don't yet know the operand size (this will be set by insn
7447 matching). Hence we record the word32 relocation here,
7448 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7449 static const struct {
7450 const char *str;
cff8d58a 7451 int len;
4fa24527 7452 const enum bfd_reloc_code_real rel[2];
40fb9820 7453 const i386_operand_type types64;
f3c180ae 7454 } gotrel[] = {
8ce3d284 7455#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7456 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7457 BFD_RELOC_SIZE32 },
7458 OPERAND_TYPE_IMM32_64 },
8ce3d284 7459#endif
cff8d58a
L		 7460 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7461 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7462 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7463 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7464 BFD_RELOC_X86_64_PLT32 },
40fb9820 7465 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7466 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7467 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7468 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7469 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7470 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7471 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7472 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7473 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7474 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7475 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7476 BFD_RELOC_X86_64_TLSGD },
40fb9820 7477 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7478 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7479 _dummy_first_bfd_reloc_code_real },
40fb9820 7480 OPERAND_TYPE_NONE },
cff8d58a
L		 7481 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7482 BFD_RELOC_X86_64_TLSLD },
40fb9820 7483 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7484 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7485 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7486 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7487 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7488 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7489 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7490 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7491 _dummy_first_bfd_reloc_code_real },
40fb9820 7492 OPERAND_TYPE_NONE },
cff8d58a
L		 7493 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7494 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7495 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7496 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7497 _dummy_first_bfd_reloc_code_real },
40fb9820 7498 OPERAND_TYPE_NONE },
cff8d58a
L		 7499 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7500 _dummy_first_bfd_reloc_code_real },
40fb9820 7501 OPERAND_TYPE_NONE },
cff8d58a
L		 7502 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7503 BFD_RELOC_X86_64_GOT32 },
40fb9820 7504 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7505 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7506 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7507 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7508 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7509 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7510 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7511 };
7512 char *cp;
7513 unsigned int j;
7514
d382c579 7515#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7516 if (!IS_ELF)
7517 return NULL;
d382c579 7518#endif
718ddfc0 7519
f3c180ae 7520 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7521 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7522 return NULL;
7523
47465058 7524 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7525 {
cff8d58a 7526 int len = gotrel[j].len;
28f81592 7527 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7528 {
4fa24527 7529 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7530 {
28f81592
AM		 7531 int first, second;
7532 char *tmpbuf, *past_reloc;
f3c180ae 7533
91d6fa6a 7534 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7535
3956db08
JB		 7536 if (types)
7537 {
7538 if (flag_code != CODE_64BIT)
40fb9820
L		 7539 {
7540 types->bitfield.imm32 = 1;
7541 types->bitfield.disp32 = 1;
7542 }
3956db08
JB		 7543 else
7544 *types = gotrel[j].types64;
7545 }
7546
8fd4256d 7547 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7548 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7549
28f81592 7550 /* The length of the first part of our input line. */
f3c180ae 7551 first = cp - input_line_pointer;
28f81592
AM		 7552
7553 /* The second part goes from after the reloc token until
67c11a9b 7554 (and including) an end_of_line char or comma. */
28f81592 7555 past_reloc = cp + 1 + len;
67c11a9b
AM		 7556 cp = past_reloc;
7557 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7558 ++cp;
7559 second = cp + 1 - past_reloc;
28f81592
AM		 7560
7561 /* Allocate and copy string. The trailing NUL shouldn't
7562 be necessary, but be safe. */
1e9cc1c2 7563 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 7564 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7565 if (second != 0 && *past_reloc != ' ')
7566 /* Replace the relocation token with ' ', so that
7567 errors like foo@GOTOFF1 will be detected. */
7568 tmpbuf[first++] = ' ';
af89796a
L		 7569 else
7570 /* Increment length by 1 if the relocation token is
7571 removed. */
7572 len++;
7573 if (adjust)
7574 *adjust = len;
0787a12d
AM		 7575 memcpy (tmpbuf + first, past_reloc, second);
7576 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7577 return tmpbuf;
7578 }
7579
4fa24527
JB		 7580 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7581 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7582 return NULL;
7583 }
7584 }
7585
7586 /* Might be a symbol version string. Don't as_bad here. */
7587 return NULL;
7588}
4e4f7c87 7589#endif
f3c180ae 7590
a988325c
NC		 7591#ifdef TE_PE
7592#ifdef lex_got
7593#undef lex_got
7594#endif
7595/* Parse operands of the form
7596 <symbol>@SECREL32+<nnn>
7597
7598 If we find one, set up the correct relocation in RELOC and copy the
7599 input string, minus the `@SECREL32' into a malloc'd buffer for
7600 parsing by the calling routine. Return this buffer, and if ADJUST
7601 is non-null set it to the length of the string we removed from the
34bca508
L		 7602 input line. Otherwise return NULL.
7603
a988325c
NC		 7604 This function is copied from the ELF version above adjusted for PE targets. */
7605
7606static char *
7607lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7608 int *adjust ATTRIBUTE_UNUSED,
d258b828 7609 i386_operand_type *types)
a988325c
NC		 7610{
7611 static const struct
7612 {
7613 const char *str;
7614 int len;
7615 const enum bfd_reloc_code_real rel[2];
7616 const i386_operand_type types64;
7617 }
7618 gotrel[] =
7619 {
7620 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7621 BFD_RELOC_32_SECREL },
7622 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7623 };
7624
7625 char *cp;
7626 unsigned j;
7627
7628 for (cp = input_line_pointer; *cp != '@'; cp++)
7629 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7630 return NULL;
7631
7632 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7633 {
7634 int len = gotrel[j].len;
7635
7636 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7637 {
7638 if (gotrel[j].rel[object_64bit] != 0)
7639 {
7640 int first, second;
7641 char *tmpbuf, *past_reloc;
7642
7643 *rel = gotrel[j].rel[object_64bit];
7644 if (adjust)
7645 *adjust = len;
7646
7647 if (types)
7648 {
7649 if (flag_code != CODE_64BIT)
7650 {
7651 types->bitfield.imm32 = 1;
7652 types->bitfield.disp32 = 1;
7653 }
7654 else
7655 *types = gotrel[j].types64;
7656 }
7657
7658 /* The length of the first part of our input line. */
7659 first = cp - input_line_pointer;
7660
7661 /* The second part goes from after the reloc token until
7662 (and including) an end_of_line char or comma. */
7663 past_reloc = cp + 1 + len;
7664 cp = past_reloc;
7665 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7666 ++cp;
7667 second = cp + 1 - past_reloc;
7668
7669 /* Allocate and copy string. The trailing NUL shouldn't
7670 be necessary, but be safe. */
7671 tmpbuf = (char *) xmalloc (first + second + 2);
7672 memcpy (tmpbuf, input_line_pointer, first);
7673 if (second != 0 && *past_reloc != ' ')
7674 /* Replace the relocation token with ' ', so that
7675 errors like foo@SECLREL321 will be detected. */
7676 tmpbuf[first++] = ' ';
7677 memcpy (tmpbuf + first, past_reloc, second);
7678 tmpbuf[first + second] = '\0';
7679 return tmpbuf;
7680 }
7681
7682 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7683 gotrel[j].str, 1 << (5 + object_64bit));
7684 return NULL;
7685 }
7686 }
7687
7688 /* Might be a symbol version string. Don't as_bad here. */
7689 return NULL;
7690}
7691
7692#endif /* TE_PE */
7693
62ebcb5c 7694bfd_reloc_code_real_type
e3bb37b5 7695x86_cons (expressionS *exp, int size)
f3c180ae 7696{
62ebcb5c
AM		 7697 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7698
ee86248c
JB		 7699 intel_syntax = -intel_syntax;
7700
3c7b9c2c 7701 exp->X_md = 0;
4fa24527 7702 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7703 {
7704 /* Handle @GOTOFF and the like in an expression. */
7705 char *save;
7706 char *gotfree_input_line;
4a57f2cf 7707 int adjust = 0;
f3c180ae
AM		 7708
7709 save = input_line_pointer;
d258b828 7710 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 7711 if (gotfree_input_line)
7712 input_line_pointer = gotfree_input_line;
7713
7714 expression (exp);
7715
7716 if (gotfree_input_line)
7717 {
7718 /* expression () has merrily parsed up to the end of line,
7719 or a comma - in the wrong buffer. Transfer how far
7720 input_line_pointer has moved to the right buffer. */
7721 input_line_pointer = (save
7722 + (input_line_pointer - gotfree_input_line)
7723 + adjust);
7724 free (gotfree_input_line);
3992d3b7
AM		 7725 if (exp->X_op == O_constant
7726 || exp->X_op == O_absent
7727 || exp->X_op == O_illegal
0398aac5 7728 || exp->X_op == O_register
3992d3b7
AM		 7729 || exp->X_op == O_big)
7730 {
7731 char c = *input_line_pointer;
7732 *input_line_pointer = 0;
7733 as_bad (_("missing or invalid expression `%s'"), save);
7734 *input_line_pointer = c;
7735 }
f3c180ae
AM		 7736 }
7737 }
7738 else
7739 expression (exp);
ee86248c
JB		 7740
7741 intel_syntax = -intel_syntax;
7742
7743 if (intel_syntax)
7744 i386_intel_simplify (exp);
62ebcb5c
AM		 7745
7746 return got_reloc;
f3c180ae 7747}
f3c180ae 7748
9f32dd5b
L		 7749static void
7750signed_cons (int size)
6482c264 7751{
d182319b
JB		 7752 if (flag_code == CODE_64BIT)
7753 cons_sign = 1;
7754 cons (size);
7755 cons_sign = -1;
6482c264
NC		 7756}
7757
d182319b 7758#ifdef TE_PE
6482c264 7759static void
7016a5d5 7760pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7761{
7762 expressionS exp;
7763
7764 do
7765 {
7766 expression (&exp);
7767 if (exp.X_op == O_symbol)
7768 exp.X_op = O_secrel;
7769
7770 emit_expr (&exp, 4);
7771 }
7772 while (*input_line_pointer++ == ',');
7773
7774 input_line_pointer--;
7775 demand_empty_rest_of_line ();
7776}
6482c264
NC		 7777#endif
7778
43234a1e
L		 7779/* Handle Vector operations. */
7780
7781static char *
7782check_VecOperations (char *op_string, char *op_end)
7783{
7784 const reg_entry *mask;
7785 const char *saved;
7786 char *end_op;
7787
7788 while (*op_string
7789 && (op_end == NULL || op_string < op_end))
7790 {
7791 saved = op_string;
7792 if (*op_string == '{')
7793 {
7794 op_string++;
7795
7796 /* Check broadcasts. */
7797 if (strncmp (op_string, "1to", 3) == 0)
7798 {
7799 int bcst_type;
7800
7801 if (i.broadcast)
7802 goto duplicated_vec_op;
7803
7804 op_string += 3;
7805 if (*op_string == '8')
7806 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 7807 else if (*op_string == '4')
7808 bcst_type = BROADCAST_1TO4;
7809 else if (*op_string == '2')
7810 bcst_type = BROADCAST_1TO2;
43234a1e
L		 7811 else if (*op_string == '1'
7812 && *(op_string+1) == '6')
7813 {
7814 bcst_type = BROADCAST_1TO16;
7815 op_string++;
7816 }
7817 else
7818 {
7819 as_bad (_("Unsupported broadcast: `%s'"), saved);
7820 return NULL;
7821 }
7822 op_string++;
7823
7824 broadcast_op.type = bcst_type;
7825 broadcast_op.operand = this_operand;
7826 i.broadcast = &broadcast_op;
7827 }
7828 /* Check masking operation. */
7829 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7830 {
7831 /* k0 can't be used for write mask. */
7832 if (mask->reg_num == 0)
7833 {
7834 as_bad (_("`%s' can't be used for write mask"),
7835 op_string);
7836 return NULL;
7837 }
7838
7839 if (!i.mask)
7840 {
7841 mask_op.mask = mask;
7842 mask_op.zeroing = 0;
7843 mask_op.operand = this_operand;
7844 i.mask = &mask_op;
7845 }
7846 else
7847 {
7848 if (i.mask->mask)
7849 goto duplicated_vec_op;
7850
7851 i.mask->mask = mask;
7852
7853 /* Only "{z}" is allowed here. No need to check
7854 zeroing mask explicitly. */
7855 if (i.mask->operand != this_operand)
7856 {
7857 as_bad (_("invalid write mask `%s'"), saved);
7858 return NULL;
7859 }
7860 }
7861
7862 op_string = end_op;
7863 }
7864 /* Check zeroing-flag for masking operation. */
7865 else if (*op_string == 'z')
7866 {
7867 if (!i.mask)
7868 {
7869 mask_op.mask = NULL;
7870 mask_op.zeroing = 1;
7871 mask_op.operand = this_operand;
7872 i.mask = &mask_op;
7873 }
7874 else
7875 {
7876 if (i.mask->zeroing)
7877 {
7878 duplicated_vec_op:
7879 as_bad (_("duplicated `%s'"), saved);
7880 return NULL;
7881 }
7882
7883 i.mask->zeroing = 1;
7884
7885 /* Only "{%k}" is allowed here. No need to check mask
7886 register explicitly. */
7887 if (i.mask->operand != this_operand)
7888 {
7889 as_bad (_("invalid zeroing-masking `%s'"),
7890 saved);
7891 return NULL;
7892 }
7893 }
7894
7895 op_string++;
7896 }
7897 else
7898 goto unknown_vec_op;
7899
7900 if (*op_string != '}')
7901 {
7902 as_bad (_("missing `}' in `%s'"), saved);
7903 return NULL;
7904 }
7905 op_string++;
7906 continue;
7907 }
7908 unknown_vec_op:
7909 /* We don't know this one. */
7910 as_bad (_("unknown vector operation: `%s'"), saved);
7911 return NULL;
7912 }
7913
7914 return op_string;
7915}
7916
252b5132 7917static int
70e41ade 7918i386_immediate (char *imm_start)
252b5132
RH		 7919{
7920 char *save_input_line_pointer;
f3c180ae 7921 char *gotfree_input_line;
252b5132 7922 segT exp_seg = 0;
47926f60 7923 expressionS *exp;
40fb9820
L		 7924 i386_operand_type types;
7925
0dfbf9d7 7926 operand_type_set (&types, ~0);
252b5132
RH		 7927
7928 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7929 {
31b2323c
L		 7930 as_bad (_("at most %d immediate operands are allowed"),
7931 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 7932 return 0;
7933 }
7934
7935 exp = &im_expressions[i.imm_operands++];
520dc8e8 7936 i.op[this_operand].imms = exp;
252b5132
RH		 7937
7938 if (is_space_char (*imm_start))
7939 ++imm_start;
7940
7941 save_input_line_pointer = input_line_pointer;
7942 input_line_pointer = imm_start;
7943
d258b828 7944 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 7945 if (gotfree_input_line)
7946 input_line_pointer = gotfree_input_line;
252b5132
RH		 7947
7948 exp_seg = expression (exp);
7949
83183c0c 7950 SKIP_WHITESPACE ();
43234a1e
L		 7951
7952 /* Handle vector operations. */
7953 if (*input_line_pointer == '{')
7954 {
7955 input_line_pointer = check_VecOperations (input_line_pointer,
7956 NULL);
7957 if (input_line_pointer == NULL)
7958 return 0;
7959 }
7960
252b5132 7961 if (*input_line_pointer)
f3c180ae 7962 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 7963
7964 input_line_pointer = save_input_line_pointer;
f3c180ae 7965 if (gotfree_input_line)
ee86248c
JB		 7966 {
7967 free (gotfree_input_line);
7968
7969 if (exp->X_op == O_constant || exp->X_op == O_register)
7970 exp->X_op = O_illegal;
7971 }
7972
7973 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7974}
252b5132 7975
ee86248c
JB		 7976static int
7977i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7978 i386_operand_type types, const char *imm_start)
7979{
7980 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 7981 {
313c53d1
L		 7982 if (imm_start)
7983 as_bad (_("missing or invalid immediate expression `%s'"),
7984 imm_start);
3992d3b7 7985 return 0;
252b5132 7986 }
3e73aa7c 7987 else if (exp->X_op == O_constant)
252b5132 7988 {
47926f60 7989 /* Size it properly later. */
40fb9820 7990 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 7991 /* If not 64bit, sign extend val. */
7992 if (flag_code != CODE_64BIT
4eed87de
AM		 7993 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7994 exp->X_add_number
7995 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 7996 }
4c63da97 7997#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 7998 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 7999 && exp_seg != absolute_section
47926f60 8000 && exp_seg != text_section
24eab124
AM		 8001 && exp_seg != data_section
8002 && exp_seg != bss_section
8003 && exp_seg != undefined_section
f86103b7 8004 && !bfd_is_com_section (exp_seg))
252b5132 8005 {
d0b47220 8006 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8007 return 0;
8008 }
8009#endif
a841bdf5 8010 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8011 {
313c53d1
L		 8012 if (imm_start)
8013 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8014 return 0;
8015 }
252b5132
RH		 8016 else
8017 {
8018 /* This is an address. The size of the address will be
24eab124 8019 determined later, depending on destination register,
3e73aa7c 8020 suffix, or the default for the section. */
40fb9820
L		 8021 i.types[this_operand].bitfield.imm8 = 1;
8022 i.types[this_operand].bitfield.imm16 = 1;
8023 i.types[this_operand].bitfield.imm32 = 1;
8024 i.types[this_operand].bitfield.imm32s = 1;
8025 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8026 i.types[this_operand] = operand_type_and (i.types[this_operand],
8027 types);
252b5132
RH		 8028 }
8029
8030 return 1;
8031}
8032
551c1ca1 8033static char *
e3bb37b5 8034i386_scale (char *scale)
252b5132 8035{
551c1ca1
AM		 8036 offsetT val;
8037 char *save = input_line_pointer;
252b5132 8038
551c1ca1
AM		 8039 input_line_pointer = scale;
8040 val = get_absolute_expression ();
8041
8042 switch (val)
252b5132 8043 {
551c1ca1 8044 case 1:
252b5132
RH		 8045 i.log2_scale_factor = 0;
8046 break;
551c1ca1 8047 case 2:
252b5132
RH		 8048 i.log2_scale_factor = 1;
8049 break;
551c1ca1 8050 case 4:
252b5132
RH		 8051 i.log2_scale_factor = 2;
8052 break;
551c1ca1 8053 case 8:
252b5132
RH		 8054 i.log2_scale_factor = 3;
8055 break;
8056 default:
a724f0f4
JB		 8057 {
8058 char sep = *input_line_pointer;
8059
8060 *input_line_pointer = '\0';
8061 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8062 scale);
8063 *input_line_pointer = sep;
8064 input_line_pointer = save;
8065 return NULL;
8066 }
252b5132 8067 }
29b0f896 8068 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8069 {
8070 as_warn (_("scale factor of %d without an index register"),
24eab124 8071 1 << i.log2_scale_factor);
252b5132 8072 i.log2_scale_factor = 0;
252b5132 8073 }
551c1ca1
AM		 8074 scale = input_line_pointer;
8075 input_line_pointer = save;
8076 return scale;
252b5132
RH		 8077}
8078
252b5132 8079static int
e3bb37b5 8080i386_displacement (char *disp_start, char *disp_end)
252b5132 8081{
29b0f896 8082 expressionS *exp;
252b5132
RH		 8083 segT exp_seg = 0;
8084 char *save_input_line_pointer;
f3c180ae 8085 char *gotfree_input_line;
40fb9820
L		 8086 int override;
8087 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8088 int ret;
252b5132 8089
31b2323c
L		 8090 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8091 {
8092 as_bad (_("at most %d displacement operands are allowed"),
8093 MAX_MEMORY_OPERANDS);
8094 return 0;
8095 }
8096
0dfbf9d7 8097 operand_type_set (&bigdisp, 0);
40fb9820
L		 8098 if ((i.types[this_operand].bitfield.jumpabsolute)
8099 || (!current_templates->start->opcode_modifier.jump
8100 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8101 {
40fb9820 8102 bigdisp.bitfield.disp32 = 1;
e05278af 8103 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8104 if (flag_code == CODE_64BIT)
8105 {
8106 if (!override)
8107 {
8108 bigdisp.bitfield.disp32s = 1;
8109 bigdisp.bitfield.disp64 = 1;
8110 }
8111 }
8112 else if ((flag_code == CODE_16BIT) ^ override)
8113 {
8114 bigdisp.bitfield.disp32 = 0;
8115 bigdisp.bitfield.disp16 = 1;
8116 }
e05278af
JB		 8117 }
8118 else
8119 {
8120 /* For PC-relative branches, the width of the displacement
8121 is dependent upon data size, not address size. */
e05278af 8122 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8123 if (flag_code == CODE_64BIT)
8124 {
8125 if (override || i.suffix == WORD_MNEM_SUFFIX)
8126 bigdisp.bitfield.disp16 = 1;
8127 else
8128 {
8129 bigdisp.bitfield.disp32 = 1;
8130 bigdisp.bitfield.disp32s = 1;
8131 }
8132 }
8133 else
e05278af
JB		 8134 {
8135 if (!override)
8136 override = (i.suffix == (flag_code != CODE_16BIT
8137 ? WORD_MNEM_SUFFIX
8138 : LONG_MNEM_SUFFIX));
40fb9820
L		 8139 bigdisp.bitfield.disp32 = 1;
8140 if ((flag_code == CODE_16BIT) ^ override)
8141 {
8142 bigdisp.bitfield.disp32 = 0;
8143 bigdisp.bitfield.disp16 = 1;
8144 }
e05278af 8145 }
e05278af 8146 }
c6fb90c8
L		 8147 i.types[this_operand] = operand_type_or (i.types[this_operand],
8148 bigdisp);
252b5132
RH		 8149
8150 exp = &disp_expressions[i.disp_operands];
520dc8e8 8151 i.op[this_operand].disps = exp;
252b5132
RH		 8152 i.disp_operands++;
8153 save_input_line_pointer = input_line_pointer;
8154 input_line_pointer = disp_start;
8155 END_STRING_AND_SAVE (disp_end);
8156
8157#ifndef GCC_ASM_O_HACK
8158#define GCC_ASM_O_HACK 0
8159#endif
8160#if GCC_ASM_O_HACK
8161 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8162 if (i.types[this_operand].bitfield.baseIndex
24eab124 8163 && displacement_string_end[-1] == '+')
252b5132
RH		 8164 {
8165 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8166 constraint within gcc asm statements.
8167 For instance:
8168
8169 #define _set_tssldt_desc(n,addr,limit,type) \
8170 __asm__ __volatile__ ( \
8171 "movw %w2,%0\n\t" \
8172 "movw %w1,2+%0\n\t" \
8173 "rorl $16,%1\n\t" \
8174 "movb %b1,4+%0\n\t" \
8175 "movb %4,5+%0\n\t" \
8176 "movb $0,6+%0\n\t" \
8177 "movb %h1,7+%0\n\t" \
8178 "rorl $16,%1" \
8179 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8180
8181 This works great except that the output assembler ends
8182 up looking a bit weird if it turns out that there is
8183 no offset. You end up producing code that looks like:
8184
8185 #APP
8186 movw $235,(%eax)
8187 movw %dx,2+(%eax)
8188 rorl $16,%edx
8189 movb %dl,4+(%eax)
8190 movb $137,5+(%eax)
8191 movb $0,6+(%eax)
8192 movb %dh,7+(%eax)
8193 rorl $16,%edx
8194 #NO_APP
8195
47926f60 8196 So here we provide the missing zero. */
24eab124
AM		 8197
8198 *displacement_string_end = '0';
252b5132
RH		 8199 }
8200#endif
d258b828 8201 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8202 if (gotfree_input_line)
8203 input_line_pointer = gotfree_input_line;
252b5132 8204
24eab124 8205 exp_seg = expression (exp);
252b5132 8206
636c26b0
AM		 8207 SKIP_WHITESPACE ();
8208 if (*input_line_pointer)
8209 as_bad (_("junk `%s' after expression"), input_line_pointer);
8210#if GCC_ASM_O_HACK
8211 RESTORE_END_STRING (disp_end + 1);
8212#endif
636c26b0 8213 input_line_pointer = save_input_line_pointer;
636c26b0 8214 if (gotfree_input_line)
ee86248c
JB		 8215 {
8216 free (gotfree_input_line);
8217
8218 if (exp->X_op == O_constant || exp->X_op == O_register)
8219 exp->X_op = O_illegal;
8220 }
8221
8222 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8223
8224 RESTORE_END_STRING (disp_end);
8225
8226 return ret;
8227}
8228
8229static int
8230i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8231 i386_operand_type types, const char *disp_start)
8232{
8233 i386_operand_type bigdisp;
8234 int ret = 1;
636c26b0 8235
24eab124
AM		 8236 /* We do this to make sure that the section symbol is in
8237 the symbol table. We will ultimately change the relocation
47926f60 8238 to be relative to the beginning of the section. */
1ae12ab7 8239 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8240 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8241 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8242 {
636c26b0 8243 if (exp->X_op != O_symbol)
3992d3b7 8244 goto inv_disp;
636c26b0 8245
e5cb08ac 8246 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8247 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8248 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8249 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8250 exp->X_op = O_subtract;
8251 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8252 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8253 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8254 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8255 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8256 else
29b0f896 8257 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8258 }
252b5132 8259
3992d3b7
AM		 8260 else if (exp->X_op == O_absent
8261 || exp->X_op == O_illegal
ee86248c 8262 || exp->X_op == O_big)
2daf4fd8 8263 {
3992d3b7
AM		 8264 inv_disp:
8265 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8266 disp_start);
3992d3b7 8267 ret = 0;
2daf4fd8
AM		 8268 }
8269
0e1147d9
L		 8270 else if (flag_code == CODE_64BIT
8271 && !i.prefix[ADDR_PREFIX]
8272 && exp->X_op == O_constant)
8273 {
8274 /* Since displacement is signed extended to 64bit, don't allow
8275 disp32 and turn off disp32s if they are out of range. */
8276 i.types[this_operand].bitfield.disp32 = 0;
8277 if (!fits_in_signed_long (exp->X_add_number))
8278 {
8279 i.types[this_operand].bitfield.disp32s = 0;
8280 if (i.types[this_operand].bitfield.baseindex)
8281 {
8282 as_bad (_("0x%lx out range of signed 32bit displacement"),
8283 (long) exp->X_add_number);
8284 ret = 0;
8285 }
8286 }
8287 }
8288
4c63da97 8289#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8290 else if (exp->X_op != O_constant
8291 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8292 && exp_seg != absolute_section
8293 && exp_seg != text_section
8294 && exp_seg != data_section
8295 && exp_seg != bss_section
8296 && exp_seg != undefined_section
8297 && !bfd_is_com_section (exp_seg))
24eab124 8298 {
d0b47220 8299 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8300 ret = 0;
24eab124 8301 }
252b5132 8302#endif
3956db08 8303
40fb9820
L		 8304 /* Check if this is a displacement only operand. */
8305 bigdisp = i.types[this_operand];
8306 bigdisp.bitfield.disp8 = 0;
8307 bigdisp.bitfield.disp16 = 0;
8308 bigdisp.bitfield.disp32 = 0;
8309 bigdisp.bitfield.disp32s = 0;
8310 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8311 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8312 i.types[this_operand] = operand_type_and (i.types[this_operand],
8313 types);
3956db08 8314
3992d3b7 8315 return ret;
252b5132
RH		 8316}
8317
eecb386c 8318/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8319 Return 1 on success, 0 on a failure. */
8320
252b5132 8321static int
e3bb37b5 8322i386_index_check (const char *operand_string)
252b5132 8323{
fc0763e6 8324 const char *kind = "base/index";
be05d201
L		 8325 enum flag_code addr_mode;
8326
8327 if (i.prefix[ADDR_PREFIX])
8328 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8329 else
8330 {
8331 addr_mode = flag_code;
8332
24eab124 8333#if INFER_ADDR_PREFIX
be05d201
L		 8334 if (i.mem_operands == 0)
8335 {
8336 /* Infer address prefix from the first memory operand. */
8337 const reg_entry *addr_reg = i.base_reg;
8338
8339 if (addr_reg == NULL)
8340 addr_reg = i.index_reg;
eecb386c 8341
be05d201
L		 8342 if (addr_reg)
8343 {
8344 if (addr_reg->reg_num == RegEip
8345 || addr_reg->reg_num == RegEiz
8346 || addr_reg->reg_type.bitfield.reg32)
8347 addr_mode = CODE_32BIT;
8348 else if (flag_code != CODE_64BIT
8349 && addr_reg->reg_type.bitfield.reg16)
8350 addr_mode = CODE_16BIT;
8351
8352 if (addr_mode != flag_code)
8353 {
8354 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8355 i.prefixes += 1;
8356 /* Change the size of any displacement too. At most one
8357 of Disp16 or Disp32 is set.
8358 FIXME. There doesn't seem to be any real need for
8359 separate Disp16 and Disp32 flags. The same goes for
8360 Imm16 and Imm32. Removing them would probably clean
8361 up the code quite a lot. */
8362 if (flag_code != CODE_64BIT
8363 && (i.types[this_operand].bitfield.disp16
8364 || i.types[this_operand].bitfield.disp32))
8365 i.types[this_operand]
8366 = operand_type_xor (i.types[this_operand], disp16_32);
8367 }
8368 }
8369 }
24eab124 8370#endif
be05d201
L		 8371 }
8372
fc0763e6
JB		 8373 if (current_templates->start->opcode_modifier.isstring
8374 && !current_templates->start->opcode_modifier.immext
8375 && (current_templates->end[-1].opcode_modifier.isstring
8376 || i.mem_operands))
8377 {
8378 /* Memory operands of string insns are special in that they only allow
8379 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8380 const reg_entry *expected_reg;
8381 static const char *di_si[][2] =
8382 {
8383 { "esi", "edi" },
8384 { "si", "di" },
8385 { "rsi", "rdi" }
8386 };
8387 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8388
8389 kind = "string address";
8390
8391 if (current_templates->start->opcode_modifier.w)
8392 {
8393 i386_operand_type type = current_templates->end[-1].operand_types[0];
8394
8395 if (!type.bitfield.baseindex
8396 || ((!i.mem_operands != !intel_syntax)
8397 && current_templates->end[-1].operand_types[1]
8398 .bitfield.baseindex))
8399 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8400 expected_reg = hash_find (reg_hash,
8401 di_si[addr_mode][type.bitfield.esseg]);
8402
fc0763e6
JB		 8403 }
8404 else
be05d201 8405 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8406
be05d201
L		 8407 if (i.base_reg != expected_reg
8408 || i.index_reg
fc0763e6 8409 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8410 {
be05d201
L		 8411 /* The second memory operand must have the same size as
8412 the first one. */
8413 if (i.mem_operands
8414 && i.base_reg
8415 && !((addr_mode == CODE_64BIT
8416 && i.base_reg->reg_type.bitfield.reg64)
8417 || (addr_mode == CODE_32BIT
8418 ? i.base_reg->reg_type.bitfield.reg32
8419 : i.base_reg->reg_type.bitfield.reg16)))
8420 goto bad_address;
8421
fc0763e6
JB		 8422 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8423 operand_string,
8424 intel_syntax ? '[' : '(',
8425 register_prefix,
be05d201 8426 expected_reg->reg_name,
fc0763e6 8427 intel_syntax ? ']' : ')');
be05d201 8428 return 1;
fc0763e6 8429 }
be05d201
L		 8430 else
8431 return 1;
8432
8433bad_address:
8434 as_bad (_("`%s' is not a valid %s expression"),
8435 operand_string, kind);
8436 return 0;
3e73aa7c
JH		 8437 }
8438 else
8439 {
be05d201
L		 8440 if (addr_mode != CODE_16BIT)
8441 {
8442 /* 32-bit/64-bit checks. */
8443 if ((i.base_reg
8444 && (addr_mode == CODE_64BIT
8445 ? !i.base_reg->reg_type.bitfield.reg64
8446 : !i.base_reg->reg_type.bitfield.reg32)
8447 && (i.index_reg
8448 || (i.base_reg->reg_num
8449 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8450 || (i.index_reg
8451 && !i.index_reg->reg_type.bitfield.regxmm
8452 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8453 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8454 && ((addr_mode == CODE_64BIT
8455 ? !(i.index_reg->reg_type.bitfield.reg64
8456 || i.index_reg->reg_num == RegRiz)
8457 : !(i.index_reg->reg_type.bitfield.reg32
8458 || i.index_reg->reg_num == RegEiz))
8459 || !i.index_reg->reg_type.bitfield.baseindex)))
8460 goto bad_address;
8461 }
8462 else
3e73aa7c 8463 {
be05d201 8464 /* 16-bit checks. */
3e73aa7c 8465 if ((i.base_reg
40fb9820
L		 8466 && (!i.base_reg->reg_type.bitfield.reg16
8467 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8468 || (i.index_reg
40fb9820
L		 8469 && (!i.index_reg->reg_type.bitfield.reg16
8470 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8471 || !(i.base_reg
8472 && i.base_reg->reg_num < 6
8473 && i.index_reg->reg_num >= 6
8474 && i.log2_scale_factor == 0))))
be05d201 8475 goto bad_address;
3e73aa7c
JH		 8476 }
8477 }
be05d201 8478 return 1;
24eab124 8479}
252b5132 8480
43234a1e
L		 8481/* Handle vector immediates. */
8482
8483static int
8484RC_SAE_immediate (const char *imm_start)
8485{
8486 unsigned int match_found, j;
8487 const char *pstr = imm_start;
8488 expressionS *exp;
8489
8490 if (*pstr != '{')
8491 return 0;
8492
8493 pstr++;
8494 match_found = 0;
8495 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8496 {
8497 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8498 {
8499 if (!i.rounding)
8500 {
8501 rc_op.type = RC_NamesTable[j].type;
8502 rc_op.operand = this_operand;
8503 i.rounding = &rc_op;
8504 }
8505 else
8506 {
8507 as_bad (_("duplicated `%s'"), imm_start);
8508 return 0;
8509 }
8510 pstr += RC_NamesTable[j].len;
8511 match_found = 1;
8512 break;
8513 }
8514 }
8515 if (!match_found)
8516 return 0;
8517
8518 if (*pstr++ != '}')
8519 {
8520 as_bad (_("Missing '}': '%s'"), imm_start);
8521 return 0;
8522 }
8523 /* RC/SAE immediate string should contain nothing more. */;
8524 if (*pstr != 0)
8525 {
8526 as_bad (_("Junk after '}': '%s'"), imm_start);
8527 return 0;
8528 }
8529
8530 exp = &im_expressions[i.imm_operands++];
8531 i.op[this_operand].imms = exp;
8532
8533 exp->X_op = O_constant;
8534 exp->X_add_number = 0;
8535 exp->X_add_symbol = (symbolS *) 0;
8536 exp->X_op_symbol = (symbolS *) 0;
8537
8538 i.types[this_operand].bitfield.imm8 = 1;
8539 return 1;
8540}
8541
fc0763e6 8542/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8543 on error. */
252b5132 8544
252b5132 8545static int
a7619375 8546i386_att_operand (char *operand_string)
252b5132 8547{
af6bdddf
AM		 8548 const reg_entry *r;
8549 char *end_op;
24eab124 8550 char *op_string = operand_string;
252b5132 8551
24eab124 8552 if (is_space_char (*op_string))
252b5132
RH		 8553 ++op_string;
8554
24eab124 8555 /* We check for an absolute prefix (differentiating,
47926f60 8556 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8557 if (*op_string == ABSOLUTE_PREFIX)
8558 {
8559 ++op_string;
8560 if (is_space_char (*op_string))
8561 ++op_string;
40fb9820 8562 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8563 }
252b5132 8564
47926f60 8565 /* Check if operand is a register. */
4d1bb795 8566 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8567 {
40fb9820
L		 8568 i386_operand_type temp;
8569
24eab124
AM		 8570 /* Check for a segment override by searching for ':' after a
8571 segment register. */
8572 op_string = end_op;
8573 if (is_space_char (*op_string))
8574 ++op_string;
40fb9820
L		 8575 if (*op_string == ':'
8576 && (r->reg_type.bitfield.sreg2
8577 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8578 {
8579 switch (r->reg_num)
8580 {
8581 case 0:
8582 i.seg[i.mem_operands] = &es;
8583 break;
8584 case 1:
8585 i.seg[i.mem_operands] = &cs;
8586 break;
8587 case 2:
8588 i.seg[i.mem_operands] = &ss;
8589 break;
8590 case 3:
8591 i.seg[i.mem_operands] = &ds;
8592 break;
8593 case 4:
8594 i.seg[i.mem_operands] = &fs;
8595 break;
8596 case 5:
8597 i.seg[i.mem_operands] = &gs;
8598 break;
8599 }
252b5132 8600
24eab124 8601 /* Skip the ':' and whitespace. */
252b5132
RH		 8602 ++op_string;
8603 if (is_space_char (*op_string))
24eab124 8604 ++op_string;
252b5132 8605
24eab124
AM		 8606 if (!is_digit_char (*op_string)
8607 && !is_identifier_char (*op_string)
8608 && *op_string != '('
8609 && *op_string != ABSOLUTE_PREFIX)
8610 {
8611 as_bad (_("bad memory operand `%s'"), op_string);
8612 return 0;
8613 }
47926f60 8614 /* Handle case of %es:*foo. */
24eab124
AM		 8615 if (*op_string == ABSOLUTE_PREFIX)
8616 {
8617 ++op_string;
8618 if (is_space_char (*op_string))
8619 ++op_string;
40fb9820 8620 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8621 }
8622 goto do_memory_reference;
8623 }
43234a1e
L		 8624
8625 /* Handle vector operations. */
8626 if (*op_string == '{')
8627 {
8628 op_string = check_VecOperations (op_string, NULL);
8629 if (op_string == NULL)
8630 return 0;
8631 }
8632
24eab124
AM		 8633 if (*op_string)
8634 {
d0b47220 8635 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8636 return 0;
8637 }
40fb9820
L		 8638 temp = r->reg_type;
8639 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8640 i.types[this_operand] = operand_type_or (i.types[this_operand],
8641 temp);
7d5e4556 8642 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8643 i.op[this_operand].regs = r;
24eab124
AM		 8644 i.reg_operands++;
8645 }
af6bdddf
AM		 8646 else if (*op_string == REGISTER_PREFIX)
8647 {
8648 as_bad (_("bad register name `%s'"), op_string);
8649 return 0;
8650 }
24eab124 8651 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8652 {
24eab124 8653 ++op_string;
40fb9820 8654 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8655 {
d0b47220 8656 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8657 return 0;
8658 }
8659 if (!i386_immediate (op_string))
8660 return 0;
8661 }
43234a1e
L		 8662 else if (RC_SAE_immediate (operand_string))
8663 {
8664 /* If it is a RC or SAE immediate, do nothing. */
8665 ;
8666 }
24eab124
AM		 8667 else if (is_digit_char (*op_string)
8668 || is_identifier_char (*op_string)
d02603dc 8669 || *op_string == '"'
e5cb08ac 8670 || *op_string == '(')
24eab124 8671 {
47926f60 8672 /* This is a memory reference of some sort. */
af6bdddf 8673 char *base_string;
252b5132 8674
47926f60 8675 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8676 char *displacement_string_start;
8677 char *displacement_string_end;
43234a1e 8678 char *vop_start;
252b5132 8679
24eab124 8680 do_memory_reference:
24eab124 8681 if ((i.mem_operands == 1
40fb9820 8682 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8683 || i.mem_operands == 2)
8684 {
8685 as_bad (_("too many memory references for `%s'"),
8686 current_templates->start->name);
8687 return 0;
8688 }
252b5132 8689
24eab124
AM		 8690 /* Check for base index form. We detect the base index form by
8691 looking for an ')' at the end of the operand, searching
8692 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8693 after the '('. */
af6bdddf 8694 base_string = op_string + strlen (op_string);
c3332e24 8695
43234a1e
L		 8696 /* Handle vector operations. */
8697 vop_start = strchr (op_string, '{');
8698 if (vop_start && vop_start < base_string)
8699 {
8700 if (check_VecOperations (vop_start, base_string) == NULL)
8701 return 0;
8702 base_string = vop_start;
8703 }
8704
af6bdddf
AM		 8705 --base_string;
8706 if (is_space_char (*base_string))
8707 --base_string;
252b5132 8708
47926f60 8709 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8710 displacement_string_start = op_string;
8711 displacement_string_end = base_string + 1;
252b5132 8712
24eab124
AM		 8713 if (*base_string == ')')
8714 {
af6bdddf 8715 char *temp_string;
24eab124
AM		 8716 unsigned int parens_balanced = 1;
8717 /* We've already checked that the number of left & right ()'s are
47926f60 8718 equal, so this loop will not be infinite. */
24eab124
AM		 8719 do
8720 {
8721 base_string--;
8722 if (*base_string == ')')
8723 parens_balanced++;
8724 if (*base_string == '(')
8725 parens_balanced--;
8726 }
8727 while (parens_balanced);
c3332e24 8728
af6bdddf 8729 temp_string = base_string;
c3332e24 8730
24eab124 8731 /* Skip past '(' and whitespace. */
252b5132
RH		 8732 ++base_string;
8733 if (is_space_char (*base_string))
24eab124 8734 ++base_string;
252b5132 8735
af6bdddf 8736 if (*base_string == ','
4eed87de
AM		 8737 || ((i.base_reg = parse_register (base_string, &end_op))
8738 != NULL))
252b5132 8739 {
af6bdddf 8740 displacement_string_end = temp_string;
252b5132 8741
40fb9820 8742 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8743
af6bdddf 8744 if (i.base_reg)
24eab124 8745 {
24eab124
AM		 8746 base_string = end_op;
8747 if (is_space_char (*base_string))
8748 ++base_string;
af6bdddf
AM		 8749 }
8750
8751 /* There may be an index reg or scale factor here. */
8752 if (*base_string == ',')
8753 {
8754 ++base_string;
8755 if (is_space_char (*base_string))
8756 ++base_string;
8757
4eed87de
AM		 8758 if ((i.index_reg = parse_register (base_string, &end_op))
8759 != NULL)
24eab124 8760 {
af6bdddf 8761 base_string = end_op;
24eab124
AM		 8762 if (is_space_char (*base_string))
8763 ++base_string;
af6bdddf
AM		 8764 if (*base_string == ',')
8765 {
8766 ++base_string;
8767 if (is_space_char (*base_string))
8768 ++base_string;
8769 }
e5cb08ac 8770 else if (*base_string != ')')
af6bdddf 8771 {
4eed87de
AM		 8772 as_bad (_("expecting `,' or `)' "
8773 "after index register in `%s'"),
af6bdddf
AM		 8774 operand_string);
8775 return 0;
8776 }
24eab124 8777 }
af6bdddf 8778 else if (*base_string == REGISTER_PREFIX)
24eab124 8779 {
f76bf5e0
L		 8780 end_op = strchr (base_string, ',');
8781 if (end_op)
8782 *end_op = '\0';
af6bdddf 8783 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8784 return 0;
8785 }
252b5132 8786
47926f60 8787 /* Check for scale factor. */
551c1ca1 8788 if (*base_string != ')')
af6bdddf 8789 {
551c1ca1
AM		 8790 char *end_scale = i386_scale (base_string);
8791
8792 if (!end_scale)
af6bdddf 8793 return 0;
24eab124 8794
551c1ca1 8795 base_string = end_scale;
af6bdddf
AM		 8796 if (is_space_char (*base_string))
8797 ++base_string;
8798 if (*base_string != ')')
8799 {
4eed87de
AM		 8800 as_bad (_("expecting `)' "
8801 "after scale factor in `%s'"),
af6bdddf
AM		 8802 operand_string);
8803 return 0;
8804 }
8805 }
8806 else if (!i.index_reg)
24eab124 8807 {
4eed87de
AM		 8808 as_bad (_("expecting index register or scale factor "
8809 "after `,'; got '%c'"),
af6bdddf 8810 *base_string);
24eab124
AM		 8811 return 0;
8812 }
8813 }
af6bdddf 8814 else if (*base_string != ')')
24eab124 8815 {
4eed87de
AM		 8816 as_bad (_("expecting `,' or `)' "
8817 "after base register in `%s'"),
af6bdddf 8818 operand_string);
24eab124
AM		 8819 return 0;
8820 }
c3332e24 8821 }
af6bdddf 8822 else if (*base_string == REGISTER_PREFIX)
c3332e24 8823 {
f76bf5e0
L		 8824 end_op = strchr (base_string, ',');
8825 if (end_op)
8826 *end_op = '\0';
af6bdddf 8827 as_bad (_("bad register name `%s'"), base_string);
24eab124 8828 return 0;
c3332e24 8829 }
24eab124
AM		 8830 }
8831
8832 /* If there's an expression beginning the operand, parse it,
8833 assuming displacement_string_start and
8834 displacement_string_end are meaningful. */
8835 if (displacement_string_start != displacement_string_end)
8836 {
8837 if (!i386_displacement (displacement_string_start,
8838 displacement_string_end))
8839 return 0;
8840 }
8841
8842 /* Special case for (%dx) while doing input/output op. */
8843 if (i.base_reg
0dfbf9d7
L		 8844 && operand_type_equal (&i.base_reg->reg_type,
8845 &reg16_inoutportreg)
24eab124
AM		 8846 && i.index_reg == 0
8847 && i.log2_scale_factor == 0
8848 && i.seg[i.mem_operands] == 0
40fb9820 8849 && !operand_type_check (i.types[this_operand], disp))
24eab124 8850 {
65da13b5 8851 i.types[this_operand] = inoutportreg;
24eab124
AM		 8852 return 1;
8853 }
8854
eecb386c
AM		 8855 if (i386_index_check (operand_string) == 0)
8856 return 0;
5c07affc 8857 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 8858 i.mem_operands++;
8859 }
8860 else
ce8a8b2f
AM		 8861 {
8862 /* It's not a memory operand; argh! */
24eab124
AM		 8863 as_bad (_("invalid char %s beginning operand %d `%s'"),
8864 output_invalid (*op_string),
8865 this_operand + 1,
8866 op_string);
8867 return 0;
8868 }
47926f60 8869 return 1; /* Normal return. */
252b5132
RH		 8870}
8871\f
fa94de6b
RM		 8872/* Calculate the maximum variable size (i.e., excluding fr_fix)
8873 that an rs_machine_dependent frag may reach. */
8874
8875unsigned int
8876i386_frag_max_var (fragS *frag)
8877{
8878 /* The only relaxable frags are for jumps.
8879 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8880 gas_assert (frag->fr_type == rs_machine_dependent);
8881 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8882}
8883
b084df0b
L		 8884#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8885static int
8dcea932 8886elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 8887{
8888 /* STT_GNU_IFUNC symbol must go through PLT. */
8889 if ((symbol_get_bfdsym (fr_symbol)->flags
8890 & BSF_GNU_INDIRECT_FUNCTION) != 0)
8891 return 0;
8892
8893 if (!S_IS_EXTERNAL (fr_symbol))
8894 /* Symbol may be weak or local. */
8895 return !S_IS_WEAK (fr_symbol);
8896
8dcea932
L		 8897 /* Global symbols with non-default visibility can't be preempted. */
8898 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
8899 return 1;
8900
8901 if (fr_var != NO_RELOC)
8902 switch ((enum bfd_reloc_code_real) fr_var)
8903 {
8904 case BFD_RELOC_386_PLT32:
8905 case BFD_RELOC_X86_64_PLT32:
8906 /* Symbol with PLT relocatin may be preempted. */
8907 return 0;
8908 default:
8909 abort ();
8910 }
8911
b084df0b
L		 8912 /* Global symbols with default visibility in a shared library may be
8913 preempted by another definition. */
8dcea932 8914 return !shared;
b084df0b
L		 8915}
8916#endif
8917
ee7fcc42
AM		 8918/* md_estimate_size_before_relax()
8919
8920 Called just before relax() for rs_machine_dependent frags. The x86
8921 assembler uses these frags to handle variable size jump
8922 instructions.
8923
8924 Any symbol that is now undefined will not become defined.
8925 Return the correct fr_subtype in the frag.
8926 Return the initial "guess for variable size of frag" to caller.
8927 The guess is actually the growth beyond the fixed part. Whatever
8928 we do to grow the fixed or variable part contributes to our
8929 returned value. */
8930
252b5132 8931int
7016a5d5 8932md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 8933{
252b5132 8934 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 8935 check for un-relaxable symbols. On an ELF system, we can't relax
8936 an externally visible symbol, because it may be overridden by a
8937 shared library. */
8938 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 8939#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8940 || (IS_ELF
8dcea932
L		 8941 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
8942 fragP->fr_var))
fbeb56a4
DK		 8943#endif
8944#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 8945 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 8946 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 8947#endif
8948 )
252b5132 8949 {
b98ef147
AM		 8950 /* Symbol is undefined in this segment, or we need to keep a
8951 reloc so that weak symbols can be overridden. */
8952 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 8953 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 8954 unsigned char *opcode;
8955 int old_fr_fix;
f6af82bd 8956
ee7fcc42 8957 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 8958 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 8959 else if (size == 2)
f6af82bd
AM		 8960 reloc_type = BFD_RELOC_16_PCREL;
8961 else
8962 reloc_type = BFD_RELOC_32_PCREL;
252b5132 8963
ee7fcc42
AM		 8964 old_fr_fix = fragP->fr_fix;
8965 opcode = (unsigned char *) fragP->fr_opcode;
8966
fddf5b5b 8967 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 8968 {
fddf5b5b
AM		 8969 case UNCOND_JUMP:
8970 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 8971 opcode[0] = 0xe9;
252b5132 8972 fragP->fr_fix += size;
062cd5e7
AS		 8973 fix_new (fragP, old_fr_fix, size,
8974 fragP->fr_symbol,
8975 fragP->fr_offset, 1,
8976 reloc_type);
252b5132
RH		 8977 break;
8978
fddf5b5b 8979 case COND_JUMP86:
412167cb
AM		 8980 if (size == 2
8981 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 8982 {
8983 /* Negate the condition, and branch past an
8984 unconditional jump. */
8985 opcode[0] ^= 1;
8986 opcode[1] = 3;
8987 /* Insert an unconditional jump. */
8988 opcode[2] = 0xe9;
8989 /* We added two extra opcode bytes, and have a two byte
8990 offset. */
8991 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 8992 fix_new (fragP, old_fr_fix + 2, 2,
8993 fragP->fr_symbol,
8994 fragP->fr_offset, 1,
8995 reloc_type);
fddf5b5b
AM		 8996 break;
8997 }
8998 /* Fall through. */
8999
9000 case COND_JUMP:
412167cb
AM		 9001 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9002 {
3e02c1cc
AM		 9003 fixS *fixP;
9004
412167cb 9005 fragP->fr_fix += 1;
3e02c1cc
AM		 9006 fixP = fix_new (fragP, old_fr_fix, 1,
9007 fragP->fr_symbol,
9008 fragP->fr_offset, 1,
9009 BFD_RELOC_8_PCREL);
9010 fixP->fx_signed = 1;
412167cb
AM		 9011 break;
9012 }
93c2a809 9013
24eab124 9014 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9015 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9016 opcode[1] = opcode[0] + 0x10;
f6af82bd 9017 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9018 /* We've added an opcode byte. */
9019 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9020 fix_new (fragP, old_fr_fix + 1, size,
9021 fragP->fr_symbol,
9022 fragP->fr_offset, 1,
9023 reloc_type);
252b5132 9024 break;
fddf5b5b
AM		 9025
9026 default:
9027 BAD_CASE (fragP->fr_subtype);
9028 break;
252b5132
RH		 9029 }
9030 frag_wane (fragP);
ee7fcc42 9031 return fragP->fr_fix - old_fr_fix;
252b5132 9032 }
93c2a809 9033
93c2a809
AM		 9034 /* Guess size depending on current relax state. Initially the relax
9035 state will correspond to a short jump and we return 1, because
9036 the variable part of the frag (the branch offset) is one byte
9037 long. However, we can relax a section more than once and in that
9038 case we must either set fr_subtype back to the unrelaxed state,
9039 or return the value for the appropriate branch. */
9040 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9041}
9042
47926f60
KH		 9043/* Called after relax() is finished.
9044
9045 In: Address of frag.
9046 fr_type == rs_machine_dependent.
9047 fr_subtype is what the address relaxed to.
9048
9049 Out: Any fixSs and constants are set up.
9050 Caller will turn frag into a ".space 0". */
9051
252b5132 9052void
7016a5d5
TG		 9053md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9054 fragS *fragP)
252b5132 9055{
29b0f896 9056 unsigned char *opcode;
252b5132 9057 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9058 offsetT target_address;
9059 offsetT opcode_address;
252b5132 9060 unsigned int extension = 0;
847f7ad4 9061 offsetT displacement_from_opcode_start;
252b5132
RH		 9062
9063 opcode = (unsigned char *) fragP->fr_opcode;
9064
47926f60 9065 /* Address we want to reach in file space. */
252b5132 9066 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9067
47926f60 9068 /* Address opcode resides at in file space. */
252b5132
RH		 9069 opcode_address = fragP->fr_address + fragP->fr_fix;
9070
47926f60 9071 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9072 displacement_from_opcode_start = target_address - opcode_address;
9073
fddf5b5b 9074 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9075 {
47926f60
KH		 9076 /* Don't have to change opcode. */
9077 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9078 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9079 }
9080 else
9081 {
9082 if (no_cond_jump_promotion
9083 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9084 as_warn_where (fragP->fr_file, fragP->fr_line,
9085 _("long jump required"));
252b5132 9086
fddf5b5b
AM		 9087 switch (fragP->fr_subtype)
9088 {
9089 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9090 extension = 4; /* 1 opcode + 4 displacement */
9091 opcode[0] = 0xe9;
9092 where_to_put_displacement = &opcode[1];
9093 break;
252b5132 9094
fddf5b5b
AM		 9095 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9096 extension = 2; /* 1 opcode + 2 displacement */
9097 opcode[0] = 0xe9;
9098 where_to_put_displacement = &opcode[1];
9099 break;
252b5132 9100
fddf5b5b
AM		 9101 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9102 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9103 extension = 5; /* 2 opcode + 4 displacement */
9104 opcode[1] = opcode[0] + 0x10;
9105 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9106 where_to_put_displacement = &opcode[2];
9107 break;
252b5132 9108
fddf5b5b
AM		 9109 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9110 extension = 3; /* 2 opcode + 2 displacement */
9111 opcode[1] = opcode[0] + 0x10;
9112 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9113 where_to_put_displacement = &opcode[2];
9114 break;
252b5132 9115
fddf5b5b
AM		 9116 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9117 extension = 4;
9118 opcode[0] ^= 1;
9119 opcode[1] = 3;
9120 opcode[2] = 0xe9;
9121 where_to_put_displacement = &opcode[3];
9122 break;
9123
9124 default:
9125 BAD_CASE (fragP->fr_subtype);
9126 break;
9127 }
252b5132 9128 }
fddf5b5b 9129
7b81dfbb
AJ		 9130 /* If size if less then four we are sure that the operand fits,
9131 but if it's 4, then it could be that the displacement is larger
9132 then -/+ 2GB. */
9133 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9134 && object_64bit
9135 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9136 + ((addressT) 1 << 31))
9137 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9138 {
9139 as_bad_where (fragP->fr_file, fragP->fr_line,
9140 _("jump target out of range"));
9141 /* Make us emit 0. */
9142 displacement_from_opcode_start = extension;
9143 }
47926f60 9144 /* Now put displacement after opcode. */
252b5132
RH		 9145 md_number_to_chars ((char *) where_to_put_displacement,
9146 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9147 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9148 fragP->fr_fix += extension;
9149}
9150\f
7016a5d5 9151/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9152 by our caller that we have all the info we need to fix it up.
9153
7016a5d5
TG		 9154 Parameter valP is the pointer to the value of the bits.
9155
252b5132
RH		 9156 On the 386, immediates, displacements, and data pointers are all in
9157 the same (little-endian) format, so we don't need to care about which
9158 we are handling. */
9159
94f592af 9160void
7016a5d5 9161md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9162{
94f592af 9163 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9164 valueT value = *valP;
252b5132 9165
f86103b7 9166#if !defined (TE_Mach)
93382f6d
AM		 9167 if (fixP->fx_pcrel)
9168 {
9169 switch (fixP->fx_r_type)
9170 {
5865bb77
ILT		 9171 default:
9172 break;
9173
d6ab8113
JB		 9174 case BFD_RELOC_64:
9175 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9176 break;
93382f6d 9177 case BFD_RELOC_32:
ae8887b5 9178 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9179 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9180 break;
9181 case BFD_RELOC_16:
9182 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9183 break;
9184 case BFD_RELOC_8:
9185 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9186 break;
9187 }
9188 }
252b5132 9189
a161fe53 9190 if (fixP->fx_addsy != NULL
31312f95 9191 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9192 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9193 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9194 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9195 && !use_rela_relocations)
252b5132 9196 {
31312f95
AM		 9197 /* This is a hack. There should be a better way to handle this.
9198 This covers for the fact that bfd_install_relocation will
9199 subtract the current location (for partial_inplace, PC relative
9200 relocations); see more below. */
252b5132 9201#ifndef OBJ_AOUT
718ddfc0 9202 if (IS_ELF
252b5132
RH		 9203#ifdef TE_PE
9204 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9205#endif
9206 )
9207 value += fixP->fx_where + fixP->fx_frag->fr_address;
9208#endif
9209#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9210 if (IS_ELF)
252b5132 9211 {
6539b54b 9212 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9213
6539b54b 9214 if ((sym_seg == seg
2f66722d 9215 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9216 && sym_seg != absolute_section))
af65af87 9217 && !generic_force_reloc (fixP))
2f66722d
AM		 9218 {
9219 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9220 bfd_install_relocation subtracts them out again. I think
9221 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9222 it. FIXME. */
9223 value += fixP->fx_where + fixP->fx_frag->fr_address;
9224 }
252b5132
RH		 9225 }
9226#endif
9227#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9228 /* For some reason, the PE format does not store a
9229 section address offset for a PC relative symbol. */
9230 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9231 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9232 value += md_pcrel_from (fixP);
9233#endif
9234 }
fbeb56a4 9235#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9236 if (fixP->fx_addsy != NULL
9237 && S_IS_WEAK (fixP->fx_addsy)
9238 /* PR 16858: Do not modify weak function references. */
9239 && ! fixP->fx_pcrel)
fbeb56a4 9240 {
296a8689
NC		 9241#if !defined (TE_PEP)
9242 /* For x86 PE weak function symbols are neither PC-relative
9243 nor do they set S_IS_FUNCTION. So the only reliable way
9244 to detect them is to check the flags of their containing
9245 section. */
9246 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9247 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9248 ;
9249 else
9250#endif
fbeb56a4
DK		 9251 value -= S_GET_VALUE (fixP->fx_addsy);
9252 }
9253#endif
252b5132
RH		 9254
9255 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9256 and we must not disappoint it. */
252b5132 9257#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9258 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9259 switch (fixP->fx_r_type)
9260 {
9261 case BFD_RELOC_386_PLT32:
3e73aa7c 9262 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9263 /* Make the jump instruction point to the address of the operand. At
9264 runtime we merely add the offset to the actual PLT entry. */
9265 value = -4;
9266 break;
31312f95 9267
13ae64f3
JJ		 9268 case BFD_RELOC_386_TLS_GD:
9269 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9270 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9271 case BFD_RELOC_386_TLS_IE:
9272 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9273 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9274 case BFD_RELOC_X86_64_TLSGD:
9275 case BFD_RELOC_X86_64_TLSLD:
9276 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9277 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9278 value = 0; /* Fully resolved at runtime. No addend. */
9279 /* Fallthrough */
9280 case BFD_RELOC_386_TLS_LE:
9281 case BFD_RELOC_386_TLS_LDO_32:
9282 case BFD_RELOC_386_TLS_LE_32:
9283 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9284 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9285 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9286 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9287 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9288 break;
9289
67a4f2b7
AO		 9290 case BFD_RELOC_386_TLS_DESC_CALL:
9291 case BFD_RELOC_X86_64_TLSDESC_CALL:
9292 value = 0; /* Fully resolved at runtime. No addend. */
9293 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9294 fixP->fx_done = 0;
9295 return;
9296
00f7efb6
JJ		 9297 case BFD_RELOC_386_GOT32:
9298 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 9299 value = 0; /* Fully resolved at runtime. No addend. */
9300 break;
47926f60
KH		 9301
9302 case BFD_RELOC_VTABLE_INHERIT:
9303 case BFD_RELOC_VTABLE_ENTRY:
9304 fixP->fx_done = 0;
94f592af 9305 return;
47926f60
KH		 9306
9307 default:
9308 break;
9309 }
9310#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9311 *valP = value;
f86103b7 9312#endif /* !defined (TE_Mach) */
3e73aa7c 9313
3e73aa7c 9314 /* Are we finished with this relocation now? */
c6682705 9315 if (fixP->fx_addsy == NULL)
3e73aa7c 9316 fixP->fx_done = 1;
fbeb56a4
DK		 9317#if defined (OBJ_COFF) && defined (TE_PE)
9318 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9319 {
9320 fixP->fx_done = 0;
9321 /* Remember value for tc_gen_reloc. */
9322 fixP->fx_addnumber = value;
9323 /* Clear out the frag for now. */
9324 value = 0;
9325 }
9326#endif
3e73aa7c
JH		 9327 else if (use_rela_relocations)
9328 {
9329 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9330 /* Remember value for tc_gen_reloc. */
9331 fixP->fx_addnumber = value;
3e73aa7c
JH		 9332 value = 0;
9333 }
f86103b7 9334
94f592af 9335 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9336}
252b5132 9337\f
252b5132 9338char *
499ac353 9339md_atof (int type, char *litP, int *sizeP)
252b5132 9340{
499ac353
NC		 9341 /* This outputs the LITTLENUMs in REVERSE order;
9342 in accord with the bigendian 386. */
9343 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9344}
9345\f
2d545b82 9346static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9347
252b5132 9348static char *
e3bb37b5 9349output_invalid (int c)
252b5132 9350{
3882b010 9351 if (ISPRINT (c))
f9f21a03
L		 9352 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9353 "'%c'", c);
252b5132 9354 else
f9f21a03 9355 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9356 "(0x%x)", (unsigned char) c);
252b5132
RH		 9357 return output_invalid_buf;
9358}
9359
af6bdddf 9360/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9361
9362static const reg_entry *
4d1bb795 9363parse_real_register (char *reg_string, char **end_op)
252b5132 9364{
af6bdddf
AM		 9365 char *s = reg_string;
9366 char *p;
252b5132
RH		 9367 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9368 const reg_entry *r;
9369
9370 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9371 if (*s == REGISTER_PREFIX)
9372 ++s;
9373
9374 if (is_space_char (*s))
9375 ++s;
9376
9377 p = reg_name_given;
af6bdddf 9378 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9379 {
9380 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9381 return (const reg_entry *) NULL;
9382 s++;
252b5132
RH		 9383 }
9384
6588847e
DN		 9385 /* For naked regs, make sure that we are not dealing with an identifier.
9386 This prevents confusing an identifier like `eax_var' with register
9387 `eax'. */
9388 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9389 return (const reg_entry *) NULL;
9390
af6bdddf 9391 *end_op = s;
252b5132
RH		 9392
9393 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9394
5f47d35b 9395 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9396 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9397 {
5f47d35b
AM		 9398 if (is_space_char (*s))
9399 ++s;
9400 if (*s == '(')
9401 {
af6bdddf 9402 ++s;
5f47d35b
AM		 9403 if (is_space_char (*s))
9404 ++s;
9405 if (*s >= '0' && *s <= '7')
9406 {
db557034 9407 int fpr = *s - '0';
af6bdddf 9408 ++s;
5f47d35b
AM		 9409 if (is_space_char (*s))
9410 ++s;
9411 if (*s == ')')
9412 {
9413 *end_op = s + 1;
1e9cc1c2 9414 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9415 know (r);
9416 return r + fpr;
5f47d35b 9417 }
5f47d35b 9418 }
47926f60 9419 /* We have "%st(" then garbage. */
5f47d35b
AM		 9420 return (const reg_entry *) NULL;
9421 }
9422 }
9423
a60de03c
JB		 9424 if (r == NULL || allow_pseudo_reg)
9425 return r;
9426
0dfbf9d7 9427 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9428 return (const reg_entry *) NULL;
9429
192dc9c6
JB		 9430 if ((r->reg_type.bitfield.reg32
9431 || r->reg_type.bitfield.sreg3
9432 || r->reg_type.bitfield.control
9433 || r->reg_type.bitfield.debug
9434 || r->reg_type.bitfield.test)
9435 && !cpu_arch_flags.bitfield.cpui386)
9436 return (const reg_entry *) NULL;
9437
309d3373
JB		 9438 if (r->reg_type.bitfield.floatreg
9439 && !cpu_arch_flags.bitfield.cpu8087
9440 && !cpu_arch_flags.bitfield.cpu287
9441 && !cpu_arch_flags.bitfield.cpu387)
9442 return (const reg_entry *) NULL;
9443
192dc9c6
JB		 9444 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9445 return (const reg_entry *) NULL;
9446
9447 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9448 return (const reg_entry *) NULL;
9449
40f12533
L		 9450 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9451 return (const reg_entry *) NULL;
9452
43234a1e
L		 9453 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9454 && !cpu_arch_flags.bitfield.cpuavx512f)
9455 return (const reg_entry *) NULL;
9456
db51cc60 9457 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9458 if (!allow_index_reg
db51cc60
L		 9459 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9460 return (const reg_entry *) NULL;
9461
43234a1e
L		 9462 /* Upper 16 vector register is only available with VREX in 64bit
9463 mode. */
9464 if ((r->reg_flags & RegVRex))
9465 {
9466 if (!cpu_arch_flags.bitfield.cpuvrex
9467 || flag_code != CODE_64BIT)
9468 return (const reg_entry *) NULL;
9469
9470 i.need_vrex = 1;
9471 }
9472
a60de03c
JB		 9473 if (((r->reg_flags & (RegRex64 | RegRex))
9474 || r->reg_type.bitfield.reg64)
40fb9820 9475 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9476 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9477 && flag_code != CODE_64BIT)
20f0a1fc 9478 return (const reg_entry *) NULL;
1ae00879 9479
b7240065
JB		 9480 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9481 return (const reg_entry *) NULL;
9482
252b5132
RH		 9483 return r;
9484}
4d1bb795
JB		 9485
9486/* REG_STRING starts *before* REGISTER_PREFIX. */
9487
9488static const reg_entry *
9489parse_register (char *reg_string, char **end_op)
9490{
9491 const reg_entry *r;
9492
9493 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9494 r = parse_real_register (reg_string, end_op);
9495 else
9496 r = NULL;
9497 if (!r)
9498 {
9499 char *save = input_line_pointer;
9500 char c;
9501 symbolS *symbolP;
9502
9503 input_line_pointer = reg_string;
d02603dc 9504 c = get_symbol_name (&reg_string);
4d1bb795
JB		 9505 symbolP = symbol_find (reg_string);
9506 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9507 {
9508 const expressionS *e = symbol_get_value_expression (symbolP);
9509
0398aac5 9510 know (e->X_op == O_register);
4eed87de 9511 know (e->X_add_number >= 0
c3fe08fa 9512 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9513 r = i386_regtab + e->X_add_number;
d3bb6b49
IT		 9514 if ((r->reg_flags & RegVRex))
9515 i.need_vrex = 1;
4d1bb795
JB		 9516 *end_op = input_line_pointer;
9517 }
9518 *input_line_pointer = c;
9519 input_line_pointer = save;
9520 }
9521 return r;
9522}
9523
9524int
9525i386_parse_name (char *name, expressionS *e, char *nextcharP)
9526{
9527 const reg_entry *r;
9528 char *end = input_line_pointer;
9529
9530 *end = *nextcharP;
9531 r = parse_register (name, &input_line_pointer);
9532 if (r && end <= input_line_pointer)
9533 {
9534 *nextcharP = *input_line_pointer;
9535 *input_line_pointer = 0;
9536 e->X_op = O_register;
9537 e->X_add_number = r - i386_regtab;
9538 return 1;
9539 }
9540 input_line_pointer = end;
9541 *end = 0;
ee86248c 9542 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9543}
9544
9545void
9546md_operand (expressionS *e)
9547{
ee86248c
JB		 9548 char *end;
9549 const reg_entry *r;
4d1bb795 9550
ee86248c
JB		 9551 switch (*input_line_pointer)
9552 {
9553 case REGISTER_PREFIX:
9554 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9555 if (r)
9556 {
9557 e->X_op = O_register;
9558 e->X_add_number = r - i386_regtab;
9559 input_line_pointer = end;
9560 }
ee86248c
JB		 9561 break;
9562
9563 case '[':
9c2799c2 9564 gas_assert (intel_syntax);
ee86248c
JB		 9565 end = input_line_pointer++;
9566 expression (e);
9567 if (*input_line_pointer == ']')
9568 {
9569 ++input_line_pointer;
9570 e->X_op_symbol = make_expr_symbol (e);
9571 e->X_add_symbol = NULL;
9572 e->X_add_number = 0;
9573 e->X_op = O_index;
9574 }
9575 else
9576 {
9577 e->X_op = O_absent;
9578 input_line_pointer = end;
9579 }
9580 break;
4d1bb795
JB		 9581 }
9582}
9583
252b5132 9584\f
4cc782b5 9585#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9586const char *md_shortopts = "kVQ:sqn";
252b5132 9587#else
12b55ccc 9588const char *md_shortopts = "qn";
252b5132 9589#endif
6e0b89ee 9590
3e73aa7c 9591#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9592#define OPTION_64 (OPTION_MD_BASE + 1)
9593#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9594#define OPTION_MARCH (OPTION_MD_BASE + 3)
9595#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9596#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9597#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9598#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9599#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9600#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9601#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9602#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9603#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9604#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9605#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9606#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9607#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9608#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9609#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
a5094208 9610#define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9611#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 9612#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 9613#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9614#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
b3b91714 9615
99ad8390
NC		 9616struct option md_longopts[] =
9617{
3e73aa7c 9618 {"32", no_argument, NULL, OPTION_32},
321098a5 9619#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9620 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9621 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9622#endif
9623#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9624 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 9625 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 9626#endif
b3b91714 9627 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9628 {"march", required_argument, NULL, OPTION_MARCH},
9629 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9630 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9631 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9632 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9633 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9634 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9635 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9636 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9637 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9638 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9639 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9640 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9641 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9642# if defined (TE_PE) || defined (TE_PEP)
9643 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9644#endif
a5094208 9645 {"momit-lock-prefix", required_argument, NULL, OPTION_OMIT_LOCK_PREFIX},
d3d3c6db 9646 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 9647 {"mamd64", no_argument, NULL, OPTION_MAMD64},
9648 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 9649 {NULL, no_argument, NULL, 0}
9650};
9651size_t md_longopts_size = sizeof (md_longopts);
9652
9653int
9103f4f4 9654md_parse_option (int c, char *arg)
252b5132 9655{
91d6fa6a 9656 unsigned int j;
6305a203 9657 char *arch, *next;
9103f4f4 9658
252b5132
RH		 9659 switch (c)
9660 {
12b55ccc
L		 9661 case 'n':
9662 optimize_align_code = 0;
9663 break;
9664
a38cf1db
AM		 9665 case 'q':
9666 quiet_warnings = 1;
252b5132
RH		 9667 break;
9668
9669#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9670 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9671 should be emitted or not. FIXME: Not implemented. */
9672 case 'Q':
252b5132
RH		 9673 break;
9674
9675 /* -V: SVR4 argument to print version ID. */
9676 case 'V':
9677 print_version_id ();
9678 break;
9679
a38cf1db
AM		 9680 /* -k: Ignore for FreeBSD compatibility. */
9681 case 'k':
252b5132 9682 break;
4cc782b5
ILT		 9683
9684 case 's':
9685 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9686 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9687 break;
8dcea932
L		 9688
9689 case OPTION_MSHARED:
9690 shared = 1;
9691 break;
99ad8390 9692#endif
321098a5 9693#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9694 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9695 case OPTION_64:
9696 {
9697 const char **list, **l;
9698
3e73aa7c
JH		 9699 list = bfd_target_list ();
9700 for (l = list; *l != NULL; l++)
8620418b 9701 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9702 || strcmp (*l, "coff-x86-64") == 0
9703 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9704 || strcmp (*l, "pei-x86-64") == 0
9705 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9706 {
9707 default_arch = "x86_64";
9708 break;
9709 }
3e73aa7c 9710 if (*l == NULL)
2b5d6a91 9711 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9712 free (list);
9713 }
9714 break;
9715#endif
252b5132 9716
351f65ca 9717#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9718 case OPTION_X32:
351f65ca
L		 9719 if (IS_ELF)
9720 {
9721 const char **list, **l;
9722
9723 list = bfd_target_list ();
9724 for (l = list; *l != NULL; l++)
9725 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9726 {
9727 default_arch = "x86_64:32";
9728 break;
9729 }
9730 if (*l == NULL)
2b5d6a91 9731 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9732 free (list);
9733 }
9734 else
9735 as_fatal (_("32bit x86_64 is only supported for ELF"));
9736 break;
9737#endif
9738
6e0b89ee
AM		 9739 case OPTION_32:
9740 default_arch = "i386";
9741 break;
9742
b3b91714
AM		 9743 case OPTION_DIVIDE:
9744#ifdef SVR4_COMMENT_CHARS
9745 {
9746 char *n, *t;
9747 const char *s;
9748
9749 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
9750 t = n;
9751 for (s = i386_comment_chars; *s != '\0'; s++)
9752 if (*s != '/')
9753 *t++ = *s;
9754 *t = '\0';
9755 i386_comment_chars = n;
9756 }
9757#endif
9758 break;
9759
9103f4f4 9760 case OPTION_MARCH:
6305a203
L		 9761 arch = xstrdup (arg);
9762 do
9103f4f4 9763 {
6305a203 9764 if (*arch == '.')
2b5d6a91 9765 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9766 next = strchr (arch, '+');
9767 if (next)
9768 *next++ = '\0';
91d6fa6a 9769 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9770 {
91d6fa6a 9771 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9772 {
6305a203 9773 /* Processor. */
1ded5609
JB		 9774 if (! cpu_arch[j].flags.bitfield.cpui386)
9775 continue;
9776
91d6fa6a 9777 cpu_arch_name = cpu_arch[j].name;
6305a203 9778 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9779 cpu_arch_flags = cpu_arch[j].flags;
9780 cpu_arch_isa = cpu_arch[j].type;
9781 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9782 if (!cpu_arch_tune_set)
9783 {
9784 cpu_arch_tune = cpu_arch_isa;
9785 cpu_arch_tune_flags = cpu_arch_isa_flags;
9786 }
9787 break;
9788 }
91d6fa6a
NC		 9789 else if (*cpu_arch [j].name == '.'
9790 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9791 {
9792 /* ISA entension. */
9793 i386_cpu_flags flags;
309d3373 9794
49021df2 9795 if (!cpu_arch[j].negated)
309d3373 9796 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 9797 cpu_arch[j].flags);
309d3373
JB		 9798 else
9799 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 9800 cpu_arch[j].flags);
81486035
L		 9801
9802 if (!valid_iamcu_cpu_flags (&flags))
9803 as_fatal (_("`%s' isn't valid for Intel MCU"), arch);
9804 else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 9805 {
9806 if (cpu_sub_arch_name)
9807 {
9808 char *name = cpu_sub_arch_name;
9809 cpu_sub_arch_name = concat (name,
91d6fa6a 9810 cpu_arch[j].name,
1bf57e9f 9811 (const char *) NULL);
6305a203
L		 9812 free (name);
9813 }
9814 else
91d6fa6a 9815 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 9816 cpu_arch_flags = flags;
a586129e 9817 cpu_arch_isa_flags = flags;
6305a203
L		 9818 }
9819 break;
ccc9c027 9820 }
9103f4f4 9821 }
6305a203 9822
91d6fa6a 9823 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9824 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9825
9826 arch = next;
9103f4f4 9827 }
6305a203 9828 while (next != NULL );
9103f4f4
L		 9829 break;
9830
9831 case OPTION_MTUNE:
9832 if (*arg == '.')
2b5d6a91 9833 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 9834 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9835 {
91d6fa6a 9836 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 9837 {
ccc9c027 9838 cpu_arch_tune_set = 1;
91d6fa6a
NC		 9839 cpu_arch_tune = cpu_arch [j].type;
9840 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 9841 break;
9842 }
9843 }
91d6fa6a 9844 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9845 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 9846 break;
9847
1efbbeb4
L		 9848 case OPTION_MMNEMONIC:
9849 if (strcasecmp (arg, "att") == 0)
9850 intel_mnemonic = 0;
9851 else if (strcasecmp (arg, "intel") == 0)
9852 intel_mnemonic = 1;
9853 else
2b5d6a91 9854 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 9855 break;
9856
9857 case OPTION_MSYNTAX:
9858 if (strcasecmp (arg, "att") == 0)
9859 intel_syntax = 0;
9860 else if (strcasecmp (arg, "intel") == 0)
9861 intel_syntax = 1;
9862 else
2b5d6a91 9863 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 9864 break;
9865
9866 case OPTION_MINDEX_REG:
9867 allow_index_reg = 1;
9868 break;
9869
9870 case OPTION_MNAKED_REG:
9871 allow_naked_reg = 1;
9872 break;
9873
9874 case OPTION_MOLD_GCC:
9875 old_gcc = 1;
1efbbeb4
L		 9876 break;
9877
c0f3af97
L		 9878 case OPTION_MSSE2AVX:
9879 sse2avx = 1;
9880 break;
9881
daf50ae7
L		 9882 case OPTION_MSSE_CHECK:
9883 if (strcasecmp (arg, "error") == 0)
7bab8ab5 9884 sse_check = check_error;
daf50ae7 9885 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 9886 sse_check = check_warning;
daf50ae7 9887 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 9888 sse_check = check_none;
daf50ae7 9889 else
2b5d6a91 9890 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 9891 break;
9892
7bab8ab5
JB		 9893 case OPTION_MOPERAND_CHECK:
9894 if (strcasecmp (arg, "error") == 0)
9895 operand_check = check_error;
9896 else if (strcasecmp (arg, "warning") == 0)
9897 operand_check = check_warning;
9898 else if (strcasecmp (arg, "none") == 0)
9899 operand_check = check_none;
9900 else
9901 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
9902 break;
9903
539f890d
L		 9904 case OPTION_MAVXSCALAR:
9905 if (strcasecmp (arg, "128") == 0)
9906 avxscalar = vex128;
9907 else if (strcasecmp (arg, "256") == 0)
9908 avxscalar = vex256;
9909 else
2b5d6a91 9910 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 9911 break;
9912
7e8b059b
L		 9913 case OPTION_MADD_BND_PREFIX:
9914 add_bnd_prefix = 1;
9915 break;
9916
43234a1e
L		 9917 case OPTION_MEVEXLIG:
9918 if (strcmp (arg, "128") == 0)
9919 evexlig = evexl128;
9920 else if (strcmp (arg, "256") == 0)
9921 evexlig = evexl256;
9922 else if (strcmp (arg, "512") == 0)
9923 evexlig = evexl512;
9924 else
9925 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
9926 break;
9927
d3d3c6db
IT		 9928 case OPTION_MEVEXRCIG:
9929 if (strcmp (arg, "rne") == 0)
9930 evexrcig = rne;
9931 else if (strcmp (arg, "rd") == 0)
9932 evexrcig = rd;
9933 else if (strcmp (arg, "ru") == 0)
9934 evexrcig = ru;
9935 else if (strcmp (arg, "rz") == 0)
9936 evexrcig = rz;
9937 else
9938 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
9939 break;
9940
43234a1e
L		 9941 case OPTION_MEVEXWIG:
9942 if (strcmp (arg, "0") == 0)
9943 evexwig = evexw0;
9944 else if (strcmp (arg, "1") == 0)
9945 evexwig = evexw1;
9946 else
9947 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
9948 break;
9949
167ad85b
TG		 9950# if defined (TE_PE) || defined (TE_PEP)
9951 case OPTION_MBIG_OBJ:
9952 use_big_obj = 1;
9953 break;
9954#endif
9955
a5094208 9956 case OPTION_OMIT_LOCK_PREFIX:
d022bddd
IT		 9957 if (strcasecmp (arg, "yes") == 0)
9958 omit_lock_prefix = 1;
9959 else if (strcasecmp (arg, "no") == 0)
9960 omit_lock_prefix = 0;
9961 else
9962 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
9963 break;
9964
5db04b09
L		 9965 case OPTION_MAMD64:
9966 cpu_arch_flags.bitfield.cpuamd64 = 1;
9967 cpu_arch_flags.bitfield.cpuintel64 = 0;
9968 cpu_arch_isa_flags.bitfield.cpuamd64 = 1;
9969 cpu_arch_isa_flags.bitfield.cpuintel64 = 0;
9970 break;
9971
9972 case OPTION_MINTEL64:
9973 cpu_arch_flags.bitfield.cpuamd64 = 0;
9974 cpu_arch_flags.bitfield.cpuintel64 = 1;
9975 cpu_arch_isa_flags.bitfield.cpuamd64 = 0;
9976 cpu_arch_isa_flags.bitfield.cpuintel64 = 1;
9977 break;
9978
252b5132
RH		 9979 default:
9980 return 0;
9981 }
9982 return 1;
9983}
9984
8a2c8fef
L		 9985#define MESSAGE_TEMPLATE \
9986" "
9987
9988static void
1ded5609 9989show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 9990{
9991 static char message[] = MESSAGE_TEMPLATE;
9992 char *start = message + 27;
9993 char *p;
9994 int size = sizeof (MESSAGE_TEMPLATE);
9995 int left;
9996 const char *name;
9997 int len;
9998 unsigned int j;
9999
10000 p = start;
10001 left = size - (start - message);
10002 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10003 {
10004 /* Should it be skipped? */
10005 if (cpu_arch [j].skip)
10006 continue;
10007
10008 name = cpu_arch [j].name;
10009 len = cpu_arch [j].len;
10010 if (*name == '.')
10011 {
10012 /* It is an extension. Skip if we aren't asked to show it. */
10013 if (ext)
10014 {
10015 name++;
10016 len--;
10017 }
10018 else
10019 continue;
10020 }
10021 else if (ext)
10022 {
10023 /* It is an processor. Skip if we show only extension. */
10024 continue;
10025 }
1ded5609
JB		 10026 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10027 {
10028 /* It is an impossible processor - skip. */
10029 continue;
10030 }
8a2c8fef
L		 10031
10032 /* Reserve 2 spaces for ", " or ",\0" */
10033 left -= len + 2;
10034
10035 /* Check if there is any room. */
10036 if (left >= 0)
10037 {
10038 if (p != start)
10039 {
10040 *p++ = ',';
10041 *p++ = ' ';
10042 }
10043 p = mempcpy (p, name, len);
10044 }
10045 else
10046 {
10047 /* Output the current message now and start a new one. */
10048 *p++ = ',';
10049 *p = '\0';
10050 fprintf (stream, "%s\n", message);
10051 p = start;
10052 left = size - (start - message) - len - 2;
8d63c93e 10053
8a2c8fef
L		 10054 gas_assert (left >= 0);
10055
10056 p = mempcpy (p, name, len);
10057 }
10058 }
10059
10060 *p = '\0';
10061 fprintf (stream, "%s\n", message);
10062}
10063
252b5132 10064void
8a2c8fef 10065md_show_usage (FILE *stream)
252b5132 10066{
4cc782b5
ILT		 10067#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10068 fprintf (stream, _("\
a38cf1db
AM		 10069 -Q ignored\n\
10070 -V print assembler version number\n\
b3b91714
AM		 10071 -k ignored\n"));
10072#endif
10073 fprintf (stream, _("\
12b55ccc 10074 -n Do not optimize code alignment\n\
b3b91714
AM		 10075 -q quieten some warnings\n"));
10076#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10077 fprintf (stream, _("\
a38cf1db 10078 -s ignored\n"));
b3b91714 10079#endif
321098a5
L		 10080#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10081 || defined (TE_PE) || defined (TE_PEP))
751d281c 10082 fprintf (stream, _("\
570561f7 10083 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10084#endif
b3b91714
AM		 10085#ifdef SVR4_COMMENT_CHARS
10086 fprintf (stream, _("\
10087 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10088#else
10089 fprintf (stream, _("\
b3b91714 10090 --divide ignored\n"));
4cc782b5 10091#endif
9103f4f4 10092 fprintf (stream, _("\
6305a203 10093 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10094 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10095 show_arch (stream, 0, 1);
8a2c8fef
L		 10096 fprintf (stream, _("\
10097 EXTENSION is combination of:\n"));
1ded5609 10098 show_arch (stream, 1, 0);
6305a203 10099 fprintf (stream, _("\
8a2c8fef 10100 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10101 show_arch (stream, 0, 0);
ba104c83 10102 fprintf (stream, _("\
c0f3af97
L		 10103 -msse2avx encode SSE instructions with VEX prefix\n"));
10104 fprintf (stream, _("\
daf50ae7
L		 10105 -msse-check=[none|error|warning]\n\
10106 check SSE instructions\n"));
10107 fprintf (stream, _("\
7bab8ab5
JB		 10108 -moperand-check=[none|error|warning]\n\
10109 check operand combinations for validity\n"));
10110 fprintf (stream, _("\
539f890d
L		 10111 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10112 length\n"));
10113 fprintf (stream, _("\
43234a1e
L		 10114 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10115 length\n"));
10116 fprintf (stream, _("\
10117 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10118 for EVEX.W bit ignored instructions\n"));
10119 fprintf (stream, _("\
d3d3c6db
IT		 10120 -mevexrcig=[rne|rd|ru|rz]\n\
10121 encode EVEX instructions with specific EVEX.RC value\n\
10122 for SAE-only ignored instructions\n"));
10123 fprintf (stream, _("\
ba104c83
L		 10124 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10125 fprintf (stream, _("\
10126 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10127 fprintf (stream, _("\
10128 -mindex-reg support pseudo index registers\n"));
10129 fprintf (stream, _("\
10130 -mnaked-reg don't require `%%' prefix for registers\n"));
10131 fprintf (stream, _("\
10132 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10133 fprintf (stream, _("\
10134 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10135 fprintf (stream, _("\
10136 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10137# if defined (TE_PE) || defined (TE_PEP)
10138 fprintf (stream, _("\
10139 -mbig-obj generate big object files\n"));
10140#endif
d022bddd
IT		 10141 fprintf (stream, _("\
10142 -momit-lock-prefix=[no|yes]\n\
10143 strip all lock prefixes\n"));
5db04b09
L		 10144 fprintf (stream, _("\
10145 -mamd64 accept only AMD64 ISA\n"));
10146 fprintf (stream, _("\
10147 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10148}
10149
3e73aa7c 10150#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10151 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10152 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10153
10154/* Pick the target format to use. */
10155
47926f60 10156const char *
e3bb37b5 10157i386_target_format (void)
252b5132 10158{
351f65ca
L		 10159 if (!strncmp (default_arch, "x86_64", 6))
10160 {
10161 update_code_flag (CODE_64BIT, 1);
10162 if (default_arch[6] == '\0')
7f56bc95 10163 x86_elf_abi = X86_64_ABI;
351f65ca 10164 else
7f56bc95 10165 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10166 }
3e73aa7c 10167 else if (!strcmp (default_arch, "i386"))
78f12dd3 10168 update_code_flag (CODE_32BIT, 1);
5197d474
L		 10169 else if (!strcmp (default_arch, "iamcu"))
10170 {
10171 update_code_flag (CODE_32BIT, 1);
10172 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10173 {
10174 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10175 cpu_arch_name = "iamcu";
10176 cpu_sub_arch_name = NULL;
10177 cpu_arch_flags = iamcu_flags;
10178 cpu_arch_isa = PROCESSOR_IAMCU;
10179 cpu_arch_isa_flags = iamcu_flags;
10180 if (!cpu_arch_tune_set)
10181 {
10182 cpu_arch_tune = cpu_arch_isa;
10183 cpu_arch_tune_flags = cpu_arch_isa_flags;
10184 }
10185 }
10186 else
10187 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10188 cpu_arch_name);
10189 }
3e73aa7c 10190 else
2b5d6a91 10191 as_fatal (_("unknown architecture"));
89507696
JB		 10192
10193 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10194 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10195 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10196 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10197
252b5132
RH		 10198 switch (OUTPUT_FLAVOR)
10199 {
9384f2ff 10200#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10201 case bfd_target_aout_flavour:
47926f60 10202 return AOUT_TARGET_FORMAT;
4c63da97 10203#endif
9384f2ff
AM		 10204#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10205# if defined (TE_PE) || defined (TE_PEP)
10206 case bfd_target_coff_flavour:
167ad85b
TG		 10207 if (flag_code == CODE_64BIT)
10208 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10209 else
10210 return "pe-i386";
9384f2ff 10211# elif defined (TE_GO32)
0561d57c
JK		 10212 case bfd_target_coff_flavour:
10213 return "coff-go32";
9384f2ff 10214# else
252b5132
RH		 10215 case bfd_target_coff_flavour:
10216 return "coff-i386";
9384f2ff 10217# endif
4c63da97 10218#endif
3e73aa7c 10219#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10220 case bfd_target_elf_flavour:
3e73aa7c 10221 {
351f65ca
L		 10222 const char *format;
10223
10224 switch (x86_elf_abi)
4fa24527 10225 {
351f65ca
L		 10226 default:
10227 format = ELF_TARGET_FORMAT;
10228 break;
7f56bc95 10229 case X86_64_ABI:
351f65ca 10230 use_rela_relocations = 1;
4fa24527 10231 object_64bit = 1;
351f65ca
L		 10232 format = ELF_TARGET_FORMAT64;
10233 break;
7f56bc95 10234 case X86_64_X32_ABI:
4fa24527 10235 use_rela_relocations = 1;
351f65ca 10236 object_64bit = 1;
862be3fb 10237 disallow_64bit_reloc = 1;
351f65ca
L		 10238 format = ELF_TARGET_FORMAT32;
10239 break;
4fa24527 10240 }
3632d14b 10241 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10242 {
7f56bc95 10243 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10244 as_fatal (_("Intel L1OM is 64bit only"));
10245 return ELF_TARGET_L1OM_FORMAT;
10246 }
b49f93f6 10247 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 10248 {
10249 if (x86_elf_abi != X86_64_ABI)
10250 as_fatal (_("Intel K1OM is 64bit only"));
10251 return ELF_TARGET_K1OM_FORMAT;
10252 }
81486035
L		 10253 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10254 {
10255 if (x86_elf_abi != I386_ABI)
10256 as_fatal (_("Intel MCU is 32bit only"));
10257 return ELF_TARGET_IAMCU_FORMAT;
10258 }
8a9036a4 10259 else
351f65ca 10260 return format;
3e73aa7c 10261 }
e57f8c65
TG		 10262#endif
10263#if defined (OBJ_MACH_O)
10264 case bfd_target_mach_o_flavour:
d382c579
TG		 10265 if (flag_code == CODE_64BIT)
10266 {
10267 use_rela_relocations = 1;
10268 object_64bit = 1;
10269 return "mach-o-x86-64";
10270 }
10271 else
10272 return "mach-o-i386";
4c63da97 10273#endif
252b5132
RH		 10274 default:
10275 abort ();
10276 return NULL;
10277 }
10278}
10279
47926f60 10280#endif /* OBJ_MAYBE_ more than one */
252b5132 10281\f
252b5132 10282symbolS *
7016a5d5 10283md_undefined_symbol (char *name)
252b5132 10284{
18dc2407
ILT		 10285 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10286 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10287 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10288 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10289 {
10290 if (!GOT_symbol)
10291 {
10292 if (symbol_find (name))
10293 as_bad (_("GOT already in symbol table"));
10294 GOT_symbol = symbol_new (name, undefined_section,
10295 (valueT) 0, &zero_address_frag);
10296 };
10297 return GOT_symbol;
10298 }
252b5132
RH		 10299 return 0;
10300}
10301
10302/* Round up a section size to the appropriate boundary. */
47926f60 10303
252b5132 10304valueT
7016a5d5 10305md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10306{
4c63da97
AM		 10307#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10308 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10309 {
10310 /* For a.out, force the section size to be aligned. If we don't do
10311 this, BFD will align it for us, but it will not write out the
10312 final bytes of the section. This may be a bug in BFD, but it is
10313 easier to fix it here since that is how the other a.out targets
10314 work. */
10315 int align;
10316
10317 align = bfd_get_section_alignment (stdoutput, segment);
10318 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
10319 }
252b5132
RH		 10320#endif
10321
10322 return size;
10323}
10324
10325/* On the i386, PC-relative offsets are relative to the start of the
10326 next instruction. That is, the address of the offset, plus its
10327 size, since the offset is always the last part of the insn. */
10328
10329long
e3bb37b5 10330md_pcrel_from (fixS *fixP)
252b5132
RH		 10331{
10332 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10333}
10334
10335#ifndef I386COFF
10336
10337static void
e3bb37b5 10338s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10339{
29b0f896 10340 int temp;
252b5132 10341
8a75718c
JB		 10342#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10343 if (IS_ELF)
10344 obj_elf_section_change_hook ();
10345#endif
252b5132
RH		 10346 temp = get_absolute_expression ();
10347 subseg_set (bss_section, (subsegT) temp);
10348 demand_empty_rest_of_line ();
10349}
10350
10351#endif
10352
252b5132 10353void
e3bb37b5 10354i386_validate_fix (fixS *fixp)
252b5132 10355{
02a86693 10356 if (fixp->fx_subsy)
252b5132 10357 {
02a86693 10358 if (fixp->fx_subsy == GOT_symbol)
23df1078 10359 {
02a86693
L		 10360 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10361 {
10362 if (!object_64bit)
10363 abort ();
10364#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10365 if (fixp->fx_tcbit2)
10366 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10367 else
10368#endif
10369 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10370 }
d6ab8113 10371 else
02a86693
L		 10372 {
10373 if (!object_64bit)
10374 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10375 else
10376 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10377 }
10378 fixp->fx_subsy = 0;
23df1078 10379 }
252b5132 10380 }
02a86693
L		 10381#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10382 else if (!object_64bit)
10383 {
10384 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
10385 && fixp->fx_tcbit2)
10386 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
10387 }
10388#endif
252b5132
RH		 10389}
10390
252b5132 10391arelent *
7016a5d5 10392tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10393{
10394 arelent *rel;
10395 bfd_reloc_code_real_type code;
10396
10397 switch (fixp->fx_r_type)
10398 {
8ce3d284 10399#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10400 case BFD_RELOC_SIZE32:
10401 case BFD_RELOC_SIZE64:
10402 if (S_IS_DEFINED (fixp->fx_addsy)
10403 && !S_IS_EXTERNAL (fixp->fx_addsy))
10404 {
10405 /* Resolve size relocation against local symbol to size of
10406 the symbol plus addend. */
10407 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10408 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10409 && !fits_in_unsigned_long (value))
10410 as_bad_where (fixp->fx_file, fixp->fx_line,
10411 _("symbol size computation overflow"));
10412 fixp->fx_addsy = NULL;
10413 fixp->fx_subsy = NULL;
10414 md_apply_fix (fixp, (valueT *) &value, NULL);
10415 return NULL;
10416 }
8ce3d284 10417#endif
8fd4256d 10418
3e73aa7c
JH		 10419 case BFD_RELOC_X86_64_PLT32:
10420 case BFD_RELOC_X86_64_GOT32:
10421 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 10422 case BFD_RELOC_386_PLT32:
10423 case BFD_RELOC_386_GOT32:
02a86693 10424 case BFD_RELOC_386_GOT32X:
252b5132
RH		 10425 case BFD_RELOC_386_GOTOFF:
10426 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10427 case BFD_RELOC_386_TLS_GD:
10428 case BFD_RELOC_386_TLS_LDM:
10429 case BFD_RELOC_386_TLS_LDO_32:
10430 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10431 case BFD_RELOC_386_TLS_IE:
10432 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10433 case BFD_RELOC_386_TLS_LE_32:
10434 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10435 case BFD_RELOC_386_TLS_GOTDESC:
10436 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10437 case BFD_RELOC_X86_64_TLSGD:
10438 case BFD_RELOC_X86_64_TLSLD:
10439 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10440 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10441 case BFD_RELOC_X86_64_GOTTPOFF:
10442 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10443 case BFD_RELOC_X86_64_TPOFF64:
10444 case BFD_RELOC_X86_64_GOTOFF64:
10445 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10446 case BFD_RELOC_X86_64_GOT64:
10447 case BFD_RELOC_X86_64_GOTPCREL64:
10448 case BFD_RELOC_X86_64_GOTPC64:
10449 case BFD_RELOC_X86_64_GOTPLT64:
10450 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10451 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10452 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10453 case BFD_RELOC_RVA:
10454 case BFD_RELOC_VTABLE_ENTRY:
10455 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10456#ifdef TE_PE
10457 case BFD_RELOC_32_SECREL:
10458#endif
252b5132
RH		 10459 code = fixp->fx_r_type;
10460 break;
dbbaec26
L		 10461 case BFD_RELOC_X86_64_32S:
10462 if (!fixp->fx_pcrel)
10463 {
10464 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10465 code = fixp->fx_r_type;
10466 break;
10467 }
252b5132 10468 default:
93382f6d 10469 if (fixp->fx_pcrel)
252b5132 10470 {
93382f6d
AM		 10471 switch (fixp->fx_size)
10472 {
10473 default:
b091f402
AM		 10474 as_bad_where (fixp->fx_file, fixp->fx_line,
10475 _("can not do %d byte pc-relative relocation"),
10476 fixp->fx_size);
93382f6d
AM		 10477 code = BFD_RELOC_32_PCREL;
10478 break;
10479 case 1: code = BFD_RELOC_8_PCREL; break;
10480 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10481 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10482#ifdef BFD64
10483 case 8: code = BFD_RELOC_64_PCREL; break;
10484#endif
93382f6d
AM		 10485 }
10486 }
10487 else
10488 {
10489 switch (fixp->fx_size)
10490 {
10491 default:
b091f402
AM		 10492 as_bad_where (fixp->fx_file, fixp->fx_line,
10493 _("can not do %d byte relocation"),
10494 fixp->fx_size);
93382f6d
AM		 10495 code = BFD_RELOC_32;
10496 break;
10497 case 1: code = BFD_RELOC_8; break;
10498 case 2: code = BFD_RELOC_16; break;
10499 case 4: code = BFD_RELOC_32; break;
937149dd 10500#ifdef BFD64
3e73aa7c 10501 case 8: code = BFD_RELOC_64; break;
937149dd 10502#endif
93382f6d 10503 }
252b5132
RH		 10504 }
10505 break;
10506 }
252b5132 10507
d182319b
JB		 10508 if ((code == BFD_RELOC_32
10509 || code == BFD_RELOC_32_PCREL
10510 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10511 && GOT_symbol
10512 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10513 {
4fa24527 10514 if (!object_64bit)
d6ab8113
JB		 10515 code = BFD_RELOC_386_GOTPC;
10516 else
10517 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10518 }
7b81dfbb
AJ		 10519 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10520 && GOT_symbol
10521 && fixp->fx_addsy == GOT_symbol)
10522 {
10523 code = BFD_RELOC_X86_64_GOTPC64;
10524 }
252b5132
RH		 10525
10526 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 10527 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10528 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10529
10530 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10531
3e73aa7c
JH		 10532 if (!use_rela_relocations)
10533 {
10534 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10535 vtable entry to be used in the relocation's section offset. */
10536 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10537 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10538#if defined (OBJ_COFF) && defined (TE_PE)
10539 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10540 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10541 else
10542#endif
c6682705 10543 rel->addend = 0;
3e73aa7c
JH		 10544 }
10545 /* Use the rela in 64bit mode. */
252b5132 10546 else
3e73aa7c 10547 {
862be3fb
L		 10548 if (disallow_64bit_reloc)
10549 switch (code)
10550 {
862be3fb
L		 10551 case BFD_RELOC_X86_64_DTPOFF64:
10552 case BFD_RELOC_X86_64_TPOFF64:
10553 case BFD_RELOC_64_PCREL:
10554 case BFD_RELOC_X86_64_GOTOFF64:
10555 case BFD_RELOC_X86_64_GOT64:
10556 case BFD_RELOC_X86_64_GOTPCREL64:
10557 case BFD_RELOC_X86_64_GOTPC64:
10558 case BFD_RELOC_X86_64_GOTPLT64:
10559 case BFD_RELOC_X86_64_PLTOFF64:
10560 as_bad_where (fixp->fx_file, fixp->fx_line,
10561 _("cannot represent relocation type %s in x32 mode"),
10562 bfd_get_reloc_code_name (code));
10563 break;
10564 default:
10565 break;
10566 }
10567
062cd5e7
AS		 10568 if (!fixp->fx_pcrel)
10569 rel->addend = fixp->fx_offset;
10570 else
10571 switch (code)
10572 {
10573 case BFD_RELOC_X86_64_PLT32:
10574 case BFD_RELOC_X86_64_GOT32:
10575 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 10576 case BFD_RELOC_X86_64_TLSGD:
10577 case BFD_RELOC_X86_64_TLSLD:
10578 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10579 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10580 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10581 rel->addend = fixp->fx_offset - fixp->fx_size;
10582 break;
10583 default:
10584 rel->addend = (section->vma
10585 - fixp->fx_size
10586 + fixp->fx_addnumber
10587 + md_pcrel_from (fixp));
10588 break;
10589 }
3e73aa7c
JH		 10590 }
10591
252b5132
RH		 10592 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10593 if (rel->howto == NULL)
10594 {
10595 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10596 _("cannot represent relocation type %s"),
252b5132
RH		 10597 bfd_get_reloc_code_name (code));
10598 /* Set howto to a garbage value so that we can keep going. */
10599 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10600 gas_assert (rel->howto != NULL);
252b5132
RH		 10601 }
10602
10603 return rel;
10604}
10605
ee86248c 10606#include "tc-i386-intel.c"
54cfded0 10607
a60de03c
JB		 10608void
10609tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10610{
a60de03c
JB		 10611 int saved_naked_reg;
10612 char saved_register_dot;
54cfded0 10613
a60de03c
JB		 10614 saved_naked_reg = allow_naked_reg;
10615 allow_naked_reg = 1;
10616 saved_register_dot = register_chars['.'];
10617 register_chars['.'] = '.';
10618 allow_pseudo_reg = 1;
10619 expression_and_evaluate (exp);
10620 allow_pseudo_reg = 0;
10621 register_chars['.'] = saved_register_dot;
10622 allow_naked_reg = saved_naked_reg;
10623
e96d56a1 10624 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10625 {
a60de03c
JB		 10626 if ((addressT) exp->X_add_number < i386_regtab_size)
10627 {
10628 exp->X_op = O_constant;
10629 exp->X_add_number = i386_regtab[exp->X_add_number]
10630 .dw2_regnum[flag_code >> 1];
10631 }
10632 else
10633 exp->X_op = O_illegal;
54cfded0 10634 }
54cfded0
AM		 10635}
10636
10637void
10638tc_x86_frame_initial_instructions (void)
10639{
a60de03c
JB		 10640 static unsigned int sp_regno[2];
10641
10642 if (!sp_regno[flag_code >> 1])
10643 {
10644 char *saved_input = input_line_pointer;
10645 char sp[][4] = {"esp", "rsp"};
10646 expressionS exp;
a4447b93 10647
a60de03c
JB		 10648 input_line_pointer = sp[flag_code >> 1];
10649 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10650 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10651 sp_regno[flag_code >> 1] = exp.X_add_number;
10652 input_line_pointer = saved_input;
10653 }
a4447b93 10654
61ff971f
L		 10655 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10656 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10657}
d2b2c203 10658
d7921315
L		 10659int
10660x86_dwarf2_addr_size (void)
10661{
10662#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10663 if (x86_elf_abi == X86_64_X32_ABI)
10664 return 4;
10665#endif
10666 return bfd_arch_bits_per_address (stdoutput) / 8;
10667}
10668
d2b2c203
DJ		 10669int
10670i386_elf_section_type (const char *str, size_t len)
10671{
10672 if (flag_code == CODE_64BIT
10673 && len == sizeof ("unwind") - 1
10674 && strncmp (str, "unwind", 6) == 0)
10675 return SHT_X86_64_UNWIND;
10676
10677 return -1;
10678}
bb41ade5 10679
ad5fec3b
EB		 10680#ifdef TE_SOLARIS
10681void
10682i386_solaris_fix_up_eh_frame (segT sec)
10683{
10684 if (flag_code == CODE_64BIT)
10685 elf_section_type (sec) = SHT_X86_64_UNWIND;
10686}
10687#endif
10688
bb41ade5
AM		 10689#ifdef TE_PE
10690void
10691tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10692{
91d6fa6a 10693 expressionS exp;
bb41ade5 10694
91d6fa6a
NC		 10695 exp.X_op = O_secrel;
10696 exp.X_add_symbol = symbol;
10697 exp.X_add_number = 0;
10698 emit_expr (&exp, size);
bb41ade5
AM		 10699}
10700#endif
3b22753a
L		 10701
10702#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10703/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10704
01e1a5bc 10705bfd_vma
3b22753a
L		 10706x86_64_section_letter (int letter, char **ptr_msg)
10707{
10708 if (flag_code == CODE_64BIT)
10709 {
10710 if (letter == 'l')
10711 return SHF_X86_64_LARGE;
10712
8f3bae45 10713 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10714 }
3b22753a 10715 else
8f3bae45 10716 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10717 return -1;
10718}
10719
01e1a5bc 10720bfd_vma
3b22753a
L		 10721x86_64_section_word (char *str, size_t len)
10722{
8620418b 10723 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10724 return SHF_X86_64_LARGE;
10725
10726 return -1;
10727}
10728
10729static void
10730handle_large_common (int small ATTRIBUTE_UNUSED)
10731{
10732 if (flag_code != CODE_64BIT)
10733 {
10734 s_comm_internal (0, elf_common_parse);
10735 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10736 }
10737 else
10738 {
10739 static segT lbss_section;
10740 asection *saved_com_section_ptr = elf_com_section_ptr;
10741 asection *saved_bss_section = bss_section;
10742
10743 if (lbss_section == NULL)
10744 {
10745 flagword applicable;
10746 segT seg = now_seg;
10747 subsegT subseg = now_subseg;
10748
10749 /* The .lbss section is for local .largecomm symbols. */
10750 lbss_section = subseg_new (".lbss", 0);
10751 applicable = bfd_applicable_section_flags (stdoutput);
10752 bfd_set_section_flags (stdoutput, lbss_section,
10753 applicable & SEC_ALLOC);
10754 seg_info (lbss_section)->bss = 1;
10755
10756 subseg_set (seg, subseg);
10757 }
10758
10759 elf_com_section_ptr = &_bfd_elf_large_com_section;
10760 bss_section = lbss_section;
10761
10762 s_comm_internal (0, elf_common_parse);
10763
10764 elf_com_section_ptr = saved_com_section_ptr;
10765 bss_section = saved_bss_section;
10766 }
10767}
10768#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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