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Remove regbnd and vec_disp8
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
d382c579 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
143e9f4a 4 2012, 2013, 2014
47926f60 5 Free Software Foundation, Inc.
252b5132
RH		 6
7 This file is part of GAS, the GNU Assembler.
8
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
ec2655a6 11 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 12 any later version.
13
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 21 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
22 02110-1301, USA. */
252b5132 23
47926f60
KH		 24/* Intel 80386 machine specific gas.
25 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 26 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 28 Bugs & suggestions are completely welcome. This is free software.
29 Please help us make it better. */
252b5132 30
252b5132 31#include "as.h"
3882b010 32#include "safe-ctype.h"
252b5132 33#include "subsegs.h"
316e2c05 34#include "dwarf2dbg.h"
54cfded0 35#include "dw2gencfi.h"
d2b2c203 36#include "elf/x86-64.h"
40fb9820 37#include "opcodes/i386-init.h"
252b5132 38
252b5132
RH		 39#ifndef REGISTER_WARNINGS
40#define REGISTER_WARNINGS 1
41#endif
42
c3332e24 43#ifndef INFER_ADDR_PREFIX
eecb386c 44#define INFER_ADDR_PREFIX 1
c3332e24
AM		 45#endif
46
29b0f896
AM		 47#ifndef DEFAULT_ARCH
48#define DEFAULT_ARCH "i386"
246fcdee 49#endif
252b5132 50
edde18a5
AM		 51#ifndef INLINE
52#if __GNUC__ >= 2
53#define INLINE __inline__
54#else
55#define INLINE
56#endif
57#endif
58
6305a203
L		 59/* Prefixes will be emitted in the order defined below.
60 WAIT_PREFIX must be the first prefix since FWAIT is really is an
61 instruction, and so must come before any prefixes.
62 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 63 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 64#define WAIT_PREFIX 0
65#define SEG_PREFIX 1
66#define ADDR_PREFIX 2
67#define DATA_PREFIX 3
c32fa91d 68#define REP_PREFIX 4
42164a71 69#define HLE_PREFIX REP_PREFIX
7e8b059b 70#define BND_PREFIX REP_PREFIX
c32fa91d
L		 71#define LOCK_PREFIX 5
72#define REX_PREFIX 6 /* must come last. */
73#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 74
75/* we define the syntax here (modulo base,index,scale syntax) */
76#define REGISTER_PREFIX '%'
77#define IMMEDIATE_PREFIX '$'
78#define ABSOLUTE_PREFIX '*'
79
80/* these are the instruction mnemonic suffixes in AT&T syntax or
81 memory operand size in Intel syntax. */
82#define WORD_MNEM_SUFFIX 'w'
83#define BYTE_MNEM_SUFFIX 'b'
84#define SHORT_MNEM_SUFFIX 's'
85#define LONG_MNEM_SUFFIX 'l'
86#define QWORD_MNEM_SUFFIX 'q'
87#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 88#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 89#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 90/* Intel Syntax. Use a non-ascii letter since since it never appears
91 in instructions. */
92#define LONG_DOUBLE_MNEM_SUFFIX '\1'
93
94#define END_OF_INSN '\0'
95
96/*
97 'templates' is for grouping together 'template' structures for opcodes
98 of the same name. This is only used for storing the insns in the grand
99 ole hash table of insns.
100 The templates themselves start at START and range up to (but not including)
101 END.
102 */
103typedef struct
104{
d3ce72d0
NC		 105 const insn_template *start;
106 const insn_template *end;
6305a203
L		 107}
108templates;
109
110/* 386 operand encoding bytes: see 386 book for details of this. */
111typedef struct
112{
113 unsigned int regmem; /* codes register or memory operand */
114 unsigned int reg; /* codes register operand (or extended opcode) */
115 unsigned int mode; /* how to interpret regmem & reg */
116}
117modrm_byte;
118
119/* x86-64 extension prefix. */
120typedef int rex_byte;
121
6305a203
L		 122/* 386 opcode byte to code indirect addressing. */
123typedef struct
124{
125 unsigned base;
126 unsigned index;
127 unsigned scale;
128}
129sib_byte;
130
6305a203
L		 131/* x86 arch names, types and features */
132typedef struct
133{
134 const char *name; /* arch name */
8a2c8fef 135 unsigned int len; /* arch string length */
6305a203
L		 136 enum processor_type type; /* arch type */
137 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 138 unsigned int skip; /* show_arch should skip this. */
22109423 139 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 140}
141arch_entry;
142
78f12dd3 143static void update_code_flag (int, int);
e3bb37b5
L		 144static void set_code_flag (int);
145static void set_16bit_gcc_code_flag (int);
146static void set_intel_syntax (int);
1efbbeb4 147static void set_intel_mnemonic (int);
db51cc60 148static void set_allow_index_reg (int);
7bab8ab5 149static void set_check (int);
e3bb37b5 150static void set_cpu_arch (int);
6482c264 151#ifdef TE_PE
e3bb37b5 152static void pe_directive_secrel (int);
6482c264 153#endif
e3bb37b5
L		 154static void signed_cons (int);
155static char *output_invalid (int c);
ee86248c
JB		 156static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
157 const char *);
158static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
159 const char *);
a7619375 160static int i386_att_operand (char *);
e3bb37b5 161static int i386_intel_operand (char *, int);
ee86248c
JB		 162static int i386_intel_simplify (expressionS *);
163static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 164static const reg_entry *parse_register (char *, char **);
165static char *parse_insn (char *, char *);
166static char *parse_operands (char *, const char *);
167static void swap_operands (void);
4d456e3d 168static void swap_2_operands (int, int);
e3bb37b5
L		 169static void optimize_imm (void);
170static void optimize_disp (void);
d3ce72d0 171static const insn_template *match_template (void);
e3bb37b5
L		 172static int check_string (void);
173static int process_suffix (void);
174static int check_byte_reg (void);
175static int check_long_reg (void);
176static int check_qword_reg (void);
177static int check_word_reg (void);
178static int finalize_imm (void);
179static int process_operands (void);
180static const seg_entry *build_modrm_byte (void);
181static void output_insn (void);
182static void output_imm (fragS *, offsetT);
183static void output_disp (fragS *, offsetT);
29b0f896 184#ifndef I386COFF
e3bb37b5 185static void s_bss (int);
252b5132 186#endif
17d4e2a2
L		 187#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
188static void handle_large_common (int small ATTRIBUTE_UNUSED);
189#endif
252b5132 190
a847613f 191static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 192
43234a1e
L		 193/* This struct describes rounding control and SAE in the instruction. */
194struct RC_Operation
195{
196 enum rc_type
197 {
198 rne = 0,
199 rd,
200 ru,
201 rz,
202 saeonly
203 } type;
204 int operand;
205};
206
207static struct RC_Operation rc_op;
208
209/* The struct describes masking, applied to OPERAND in the instruction.
210 MASK is a pointer to the corresponding mask register. ZEROING tells
211 whether merging or zeroing mask is used. */
212struct Mask_Operation
213{
214 const reg_entry *mask;
215 unsigned int zeroing;
216 /* The operand where this operation is associated. */
217 int operand;
218};
219
220static struct Mask_Operation mask_op;
221
222/* The struct describes broadcasting, applied to OPERAND. FACTOR is
223 broadcast factor. */
224struct Broadcast_Operation
225{
226 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
227 int type;
228
229 /* Index of broadcasted operand. */
230 int operand;
231};
232
233static struct Broadcast_Operation broadcast_op;
234
c0f3af97
L		 235/* VEX prefix. */
236typedef struct
237{
43234a1e
L		 238 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
239 unsigned char bytes[4];
c0f3af97
L		 240 unsigned int length;
241 /* Destination or source register specifier. */
242 const reg_entry *register_specifier;
243} vex_prefix;
244
252b5132 245/* 'md_assemble ()' gathers together information and puts it into a
47926f60 246 i386_insn. */
252b5132 247
520dc8e8
AM		 248union i386_op
249 {
250 expressionS *disps;
251 expressionS *imms;
252 const reg_entry *regs;
253 };
254
a65babc9
L		 255enum i386_error
256 {
86e026a4 257 operand_size_mismatch,
a65babc9
L		 258 operand_type_mismatch,
259 register_type_mismatch,
260 number_of_operands_mismatch,
261 invalid_instruction_suffix,
262 bad_imm4,
263 old_gcc_only,
264 unsupported_with_intel_mnemonic,
265 unsupported_syntax,
6c30d220
L		 266 unsupported,
267 invalid_vsib_address,
7bab8ab5 268 invalid_vector_register_set,
43234a1e
L		 269 unsupported_vector_index_register,
270 unsupported_broadcast,
271 broadcast_not_on_src_operand,
272 broadcast_needed,
273 unsupported_masking,
274 mask_not_on_destination,
275 no_default_mask,
276 unsupported_rc_sae,
277 rc_sae_operand_not_last_imm,
278 invalid_register_operand,
279 try_vector_disp8
a65babc9
L		 280 };
281
252b5132
RH		 282struct _i386_insn
283 {
47926f60 284 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 285 insn_template tm;
252b5132 286
7d5e4556
L		 287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
252b5132
RH		 289 char suffix;
290
47926f60 291 /* OPERANDS gives the number of given operands. */
252b5132
RH		 292 unsigned int operands;
293
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
47926f60 296 operands. */
252b5132
RH		 297 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
298
299 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 300 use OP[i] for the corresponding operand. */
40fb9820 301 i386_operand_type types[MAX_OPERANDS];
252b5132 302
520dc8e8
AM		 303 /* Displacement expression, immediate expression, or register for each
304 operand. */
305 union i386_op op[MAX_OPERANDS];
252b5132 306
3e73aa7c
JH		 307 /* Flags for operands. */
308 unsigned int flags[MAX_OPERANDS];
309#define Operand_PCrel 1
310
252b5132 311 /* Relocation type for operand */
f86103b7 312 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 313
252b5132
RH		 314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry *base_reg;
317 const reg_entry *index_reg;
318 unsigned int log2_scale_factor;
319
320 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 321 explicit segment overrides are given. */
ce8a8b2f 322 const seg_entry *seg[2];
252b5132
RH		 323
324 /* PREFIX holds all the given prefix opcodes (usually null).
325 PREFIXES is the number of prefix opcodes. */
326 unsigned int prefixes;
327 unsigned char prefix[MAX_PREFIXES];
328
329 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 330 addressing modes of this insn are encoded. */
252b5132 331 modrm_byte rm;
3e73aa7c 332 rex_byte rex;
43234a1e 333 rex_byte vrex;
252b5132 334 sib_byte sib;
c0f3af97 335 vex_prefix vex;
b6169b20 336
43234a1e
L		 337 /* Masking attributes. */
338 struct Mask_Operation *mask;
339
340 /* Rounding control and SAE attributes. */
341 struct RC_Operation *rounding;
342
343 /* Broadcasting attributes. */
344 struct Broadcast_Operation *broadcast;
345
346 /* Compressed disp8*N attribute. */
347 unsigned int memshift;
348
b6169b20 349 /* Swap operand in encoding. */
4473e004 350 unsigned int swap_operand;
891edac4 351
a501d77e
L		 352 /* Prefer 8bit or 32bit displacement in encoding. */
353 enum
354 {
355 disp_encoding_default = 0,
356 disp_encoding_8bit,
357 disp_encoding_32bit
358 } disp_encoding;
f8a5c266 359
d5de92cf
L		 360 /* REP prefix. */
361 const char *rep_prefix;
362
165de32a
L		 363 /* HLE prefix. */
364 const char *hle_prefix;
42164a71 365
7e8b059b
L		 366 /* Have BND prefix. */
367 const char *bnd_prefix;
368
43234a1e
L		 369 /* Need VREX to support upper 16 registers. */
370 int need_vrex;
371
891edac4 372 /* Error message. */
a65babc9 373 enum i386_error error;
252b5132
RH		 374 };
375
376typedef struct _i386_insn i386_insn;
377
43234a1e
L		 378/* Link RC type with corresponding string, that'll be looked for in
379 asm. */
380struct RC_name
381{
382 enum rc_type type;
383 const char *name;
384 unsigned int len;
385};
386
387static const struct RC_name RC_NamesTable[] =
388{
389 { rne, STRING_COMMA_LEN ("rn-sae") },
390 { rd, STRING_COMMA_LEN ("rd-sae") },
391 { ru, STRING_COMMA_LEN ("ru-sae") },
392 { rz, STRING_COMMA_LEN ("rz-sae") },
393 { saeonly, STRING_COMMA_LEN ("sae") },
394};
395
252b5132
RH		 396/* List of chars besides those in app.c:symbol_chars that can start an
397 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 398const char extra_symbol_chars[] = "*%-([{"
252b5132 399#ifdef LEX_AT
32137342
NC		 400 "@"
401#endif
402#ifdef LEX_QM
403 "?"
252b5132 404#endif
32137342 405 ;
252b5132 406
29b0f896
AM		 407#if (defined (TE_I386AIX) \
408 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 409 && !defined (TE_GNU) \
29b0f896 410 && !defined (TE_LINUX) \
8d63c93e
RM		 411 && !defined (TE_NACL) \
412 && !defined (TE_NETWARE) \
29b0f896 413 && !defined (TE_FreeBSD) \
5b806d27 414 && !defined (TE_DragonFly) \
29b0f896 415 && !defined (TE_NetBSD)))
252b5132 416/* This array holds the chars that always start a comment. If the
b3b91714
AM		 417 pre-processor is disabled, these aren't very useful. The option
418 --divide will remove '/' from this list. */
419const char *i386_comment_chars = "#/";
420#define SVR4_COMMENT_CHARS 1
252b5132 421#define PREFIX_SEPARATOR '\\'
252b5132 422
b3b91714
AM		 423#else
424const char *i386_comment_chars = "#";
425#define PREFIX_SEPARATOR '/'
426#endif
427
252b5132
RH		 428/* This array holds the chars that only start a comment at the beginning of
429 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 430 .line and .file directives will appear in the pre-processed output.
431 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 432 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 433 #NO_APP at the beginning of its output.
434 Also note that comments started like this one will always work if
252b5132 435 '/' isn't otherwise defined. */
b3b91714 436const char line_comment_chars[] = "#/";
252b5132 437
63a0b638 438const char line_separator_chars[] = ";";
252b5132 439
ce8a8b2f
AM		 440/* Chars that can be used to separate mant from exp in floating point
441 nums. */
252b5132
RH		 442const char EXP_CHARS[] = "eE";
443
ce8a8b2f
AM		 444/* Chars that mean this number is a floating point constant
445 As in 0f12.456
446 or 0d1.2345e12. */
252b5132
RH		 447const char FLT_CHARS[] = "fFdDxX";
448
ce8a8b2f 449/* Tables for lexical analysis. */
252b5132
RH		 450static char mnemonic_chars[256];
451static char register_chars[256];
452static char operand_chars[256];
453static char identifier_chars[256];
454static char digit_chars[256];
455
ce8a8b2f 456/* Lexical macros. */
252b5132
RH		 457#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
458#define is_operand_char(x) (operand_chars[(unsigned char) x])
459#define is_register_char(x) (register_chars[(unsigned char) x])
460#define is_space_char(x) ((x) == ' ')
461#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
462#define is_digit_char(x) (digit_chars[(unsigned char) x])
463
0234cb7c 464/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 465static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
466
467/* md_assemble() always leaves the strings it's passed unaltered. To
468 effect this we maintain a stack of saved characters that we've smashed
469 with '\0's (indicating end of strings for various sub-fields of the
47926f60 470 assembler instruction). */
252b5132 471static char save_stack[32];
ce8a8b2f 472static char *save_stack_p;
252b5132
RH		 473#define END_STRING_AND_SAVE(s) \
474 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
475#define RESTORE_END_STRING(s) \
476 do { *(s) = *--save_stack_p; } while (0)
477
47926f60 478/* The instruction we're assembling. */
252b5132
RH		 479static i386_insn i;
480
481/* Possible templates for current insn. */
482static const templates *current_templates;
483
31b2323c
L		 484/* Per instruction expressionS buffers: max displacements & immediates. */
485static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
486static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 487
47926f60 488/* Current operand we are working on. */
ee86248c 489static int this_operand = -1;
252b5132 490
3e73aa7c
JH		 491/* We support four different modes. FLAG_CODE variable is used to distinguish
492 these. */
493
494enum flag_code {
495 CODE_32BIT,
496 CODE_16BIT,
497 CODE_64BIT };
498
499static enum flag_code flag_code;
4fa24527 500static unsigned int object_64bit;
862be3fb 501static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 502static int use_rela_relocations = 0;
503
7af8ed2d
NC		 504#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
505 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
506 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
507
351f65ca
L		 508/* The ELF ABI to use. */
509enum x86_elf_abi
510{
511 I386_ABI,
7f56bc95
L		 512 X86_64_ABI,
513 X86_64_X32_ABI
351f65ca
L		 514};
515
516static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 517#endif
351f65ca 518
47926f60
KH		 519/* 1 for intel syntax,
520 0 if att syntax. */
521static int intel_syntax = 0;
252b5132 522
1efbbeb4
L		 523/* 1 for intel mnemonic,
524 0 if att mnemonic. */
525static int intel_mnemonic = !SYSV386_COMPAT;
526
5209009a 527/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 528static int old_gcc = OLDGCC_COMPAT;
529
a60de03c
JB		 530/* 1 if pseudo registers are permitted. */
531static int allow_pseudo_reg = 0;
532
47926f60
KH		 533/* 1 if register prefix % not required. */
534static int allow_naked_reg = 0;
252b5132 535
7e8b059b
L		 536/* 1 if the assembler should add BND prefix for all control-tranferring
537 instructions supporting it, even if this prefix wasn't specified
538 explicitly. */
539static int add_bnd_prefix = 0;
540
ba104c83 541/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 542static int allow_index_reg = 0;
543
7bab8ab5 544static enum check_kind
daf50ae7 545 {
7bab8ab5
JB		 546 check_none = 0,
547 check_warning,
548 check_error
daf50ae7 549 }
7bab8ab5 550sse_check, operand_check = check_warning;
daf50ae7 551
2ca3ace5
L		 552/* Register prefix used for error message. */
553static const char *register_prefix = "%";
554
47926f60
KH		 555/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
556 leave, push, and pop instructions so that gcc has the same stack
557 frame as in 32 bit mode. */
558static char stackop_size = '\0';
eecb386c 559
12b55ccc
L		 560/* Non-zero to optimize code alignment. */
561int optimize_align_code = 1;
562
47926f60
KH		 563/* Non-zero to quieten some warnings. */
564static int quiet_warnings = 0;
a38cf1db 565
47926f60
KH		 566/* CPU name. */
567static const char *cpu_arch_name = NULL;
6305a203 568static char *cpu_sub_arch_name = NULL;
a38cf1db 569
47926f60 570/* CPU feature flags. */
40fb9820
L		 571static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
572
ccc9c027
L		 573/* If we have selected a cpu we are generating instructions for. */
574static int cpu_arch_tune_set = 0;
575
9103f4f4 576/* Cpu we are generating instructions for. */
fbf3f584 577enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 578
579/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 580static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 581
ccc9c027 582/* CPU instruction set architecture used. */
fbf3f584 583enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 584
9103f4f4 585/* CPU feature flags of instruction set architecture used. */
fbf3f584 586i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 587
fddf5b5b
AM		 588/* If set, conditional jumps are not automatically promoted to handle
589 larger than a byte offset. */
590static unsigned int no_cond_jump_promotion = 0;
591
c0f3af97
L		 592/* Encode SSE instructions with VEX prefix. */
593static unsigned int sse2avx;
594
539f890d
L		 595/* Encode scalar AVX instructions with specific vector length. */
596static enum
597 {
598 vex128 = 0,
599 vex256
600 } avxscalar;
601
43234a1e
L		 602/* Encode scalar EVEX LIG instructions with specific vector length. */
603static enum
604 {
605 evexl128 = 0,
606 evexl256,
607 evexl512
608 } evexlig;
609
610/* Encode EVEX WIG instructions with specific evex.w. */
611static enum
612 {
613 evexw0 = 0,
614 evexw1
615 } evexwig;
616
29b0f896 617/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 618static symbolS *GOT_symbol;
29b0f896 619
a4447b93
RH		 620/* The dwarf2 return column, adjusted for 32 or 64 bit. */
621unsigned int x86_dwarf2_return_column;
622
623/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
624int x86_cie_data_alignment;
625
252b5132 626/* Interface to relax_segment.
fddf5b5b
AM		 627 There are 3 major relax states for 386 jump insns because the
628 different types of jumps add different sizes to frags when we're
629 figuring out what sort of jump to choose to reach a given label. */
252b5132 630
47926f60 631/* Types. */
93c2a809
AM		 632#define UNCOND_JUMP 0
633#define COND_JUMP 1
634#define COND_JUMP86 2
fddf5b5b 635
47926f60 636/* Sizes. */
252b5132
RH		 637#define CODE16 1
638#define SMALL 0
29b0f896 639#define SMALL16 (SMALL | CODE16)
252b5132 640#define BIG 2
29b0f896 641#define BIG16 (BIG | CODE16)
252b5132
RH		 642
643#ifndef INLINE
644#ifdef __GNUC__
645#define INLINE __inline__
646#else
647#define INLINE
648#endif
649#endif
650
fddf5b5b
AM		 651#define ENCODE_RELAX_STATE(type, size) \
652 ((relax_substateT) (((type) << 2) | (size)))
653#define TYPE_FROM_RELAX_STATE(s) \
654 ((s) >> 2)
655#define DISP_SIZE_FROM_RELAX_STATE(s) \
656 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 657
658/* This table is used by relax_frag to promote short jumps to long
659 ones where necessary. SMALL (short) jumps may be promoted to BIG
660 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
661 don't allow a short jump in a 32 bit code segment to be promoted to
662 a 16 bit offset jump because it's slower (requires data size
663 prefix), and doesn't work, unless the destination is in the bottom
664 64k of the code segment (The top 16 bits of eip are zeroed). */
665
666const relax_typeS md_relax_table[] =
667{
24eab124
AM		 668 /* The fields are:
669 1) most positive reach of this state,
670 2) most negative reach of this state,
93c2a809 671 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 672 4) which index into the table to try if we can't fit into this one. */
252b5132 673
fddf5b5b 674 /* UNCOND_JUMP states. */
93c2a809
AM		 675 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
676 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
677 /* dword jmp adds 4 bytes to frag:
678 0 extra opcode bytes, 4 displacement bytes. */
252b5132 679 {0, 0, 4, 0},
93c2a809
AM		 680 /* word jmp adds 2 byte2 to frag:
681 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 682 {0, 0, 2, 0},
683
93c2a809
AM		 684 /* COND_JUMP states. */
685 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
686 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
687 /* dword conditionals adds 5 bytes to frag:
688 1 extra opcode byte, 4 displacement bytes. */
689 {0, 0, 5, 0},
fddf5b5b 690 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 691 1 extra opcode byte, 2 displacement bytes. */
692 {0, 0, 3, 0},
693
694 /* COND_JUMP86 states. */
695 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
696 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
697 /* dword conditionals adds 5 bytes to frag:
698 1 extra opcode byte, 4 displacement bytes. */
699 {0, 0, 5, 0},
700 /* word conditionals add 4 bytes to frag:
701 1 displacement byte and a 3 byte long branch insn. */
702 {0, 0, 4, 0}
252b5132
RH		 703};
704
9103f4f4
L		 705static const arch_entry cpu_arch[] =
706{
89507696
JB		 707 /* Do not replace the first two entries - i386_target_format()
708 relies on them being there in this order. */
8a2c8fef 709 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 710 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 711 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 712 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 713 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 714 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 715 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 716 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 717 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 718 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 719 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 720 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 721 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 722 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 723 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 724 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 725 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 726 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 727 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 728 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 729 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 730 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 731 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 732 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 733 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 734 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 735 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 736 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 737 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 738 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 739 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 740 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 741 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 742 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 743 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 744 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 745 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 746 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 747 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 748 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 749 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 750 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 751 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 752 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 753 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
754 CPU_K1OM_FLAGS, 0, 0 },
8a2c8fef 755 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 756 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 757 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 758 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 759 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 760 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 761 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 762 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 763 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 764 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 765 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 766 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 767 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 768 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 769 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 770 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 771 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 772 CPU_BDVER2_FLAGS, 0, 0 },
5e5c50d3
NE		 773 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
774 CPU_BDVER3_FLAGS, 0, 0 },
c7b0bd56
SE		 775 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
776 CPU_BDVER4_FLAGS, 0, 0 },
7b458c12
L		 777 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
778 CPU_BTVER1_FLAGS, 0, 0 },
779 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
780 CPU_BTVER2_FLAGS, 0, 0 },
8a2c8fef 781 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 782 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 783 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 784 CPU_287_FLAGS, 0, 0 },
8a2c8fef 785 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 786 CPU_387_FLAGS, 0, 0 },
8a2c8fef 787 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 788 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 789 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 790 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 791 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 792 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 793 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 794 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 795 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 796 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 797 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 798 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 799 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 800 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 801 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 802 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 803 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 804 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 805 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 806 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 807 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 808 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 809 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 810 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 811 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
812 CPU_AVX2_FLAGS, 0, 0 },
43234a1e
L		 813 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
814 CPU_AVX512F_FLAGS, 0, 0 },
815 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
816 CPU_AVX512CD_FLAGS, 0, 0 },
817 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
818 CPU_AVX512ER_FLAGS, 0, 0 },
819 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
820 CPU_AVX512PF_FLAGS, 0, 0 },
8a2c8fef 821 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 822 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 823 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 824 CPU_VMX_FLAGS, 0, 0 },
8729a6f6
L		 825 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
826 CPU_VMFUNC_FLAGS, 0, 0 },
8a2c8fef 827 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 828 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 829 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 830 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 831 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 832 CPU_XSAVEOPT_FLAGS, 0, 0 },
8a2c8fef 833 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 834 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 835 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 836 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 837 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 838 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 839 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 840 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 841 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 842 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 843 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 844 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 845 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
846 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 847 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 848 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 849 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 850 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 851 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 852 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 853 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 854 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 855 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 856 CPU_MOVBE_FLAGS, 0, 0 },
60aa667e
L		 857 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
858 CPU_CX16_FLAGS, 0, 0 },
8a2c8fef 859 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 860 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 861 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
862 CPU_LZCNT_FLAGS, 0, 0 },
42164a71
L		 863 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
864 CPU_HLE_FLAGS, 0, 0 },
865 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
866 CPU_RTM_FLAGS, 0, 0 },
6c30d220
L		 867 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
868 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 869 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 870 CPU_CLFLUSH_FLAGS, 0, 0 },
871 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
872 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 873 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 874 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 875 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 876 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 877 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 878 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 879 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 880 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 881 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 882 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 883 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 884 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 885 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 886 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 887 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 888 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 889 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 890 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 891 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
892 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 893 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
894 CPU_TBM_FLAGS, 0, 0 },
e2e1fcde
L		 895 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
896 CPU_ADX_FLAGS, 0, 0 },
897 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
898 CPU_RDSEED_FLAGS, 0, 0 },
899 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
900 CPU_PRFCHW_FLAGS, 0, 0 },
5c111e37
L		 901 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
902 CPU_SMAP_FLAGS, 0, 0 },
7e8b059b
L		 903 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
904 CPU_MPX_FLAGS, 0, 0 },
a0046408
L		 905 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
906 CPU_SHA_FLAGS, 0, 0 },
e413e4e9
AM		 907};
908
704209c0 909#ifdef I386COFF
a6c24e68
NC		 910/* Like s_lcomm_internal in gas/read.c but the alignment string
911 is allowed to be optional. */
912
913static symbolS *
914pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
915{
916 addressT align = 0;
917
918 SKIP_WHITESPACE ();
919
7ab9ffdd 920 if (needs_align
a6c24e68
NC		 921 && *input_line_pointer == ',')
922 {
923 align = parse_align (needs_align - 1);
7ab9ffdd 924
a6c24e68
NC		 925 if (align == (addressT) -1)
926 return NULL;
927 }
928 else
929 {
930 if (size >= 8)
931 align = 3;
932 else if (size >= 4)
933 align = 2;
934 else if (size >= 2)
935 align = 1;
936 else
937 align = 0;
938 }
939
940 bss_alloc (symbolP, size, align);
941 return symbolP;
942}
943
704209c0 944static void
a6c24e68
NC		 945pe_lcomm (int needs_align)
946{
947 s_comm_internal (needs_align * 2, pe_lcomm_internal);
948}
704209c0 949#endif
a6c24e68 950
29b0f896
AM		 951const pseudo_typeS md_pseudo_table[] =
952{
953#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
954 {"align", s_align_bytes, 0},
955#else
956 {"align", s_align_ptwo, 0},
957#endif
958 {"arch", set_cpu_arch, 0},
959#ifndef I386COFF
960 {"bss", s_bss, 0},
a6c24e68
NC		 961#else
962 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 963#endif
964 {"ffloat", float_cons, 'f'},
965 {"dfloat", float_cons, 'd'},
966 {"tfloat", float_cons, 'x'},
967 {"value", cons, 2},
d182319b 968 {"slong", signed_cons, 4},
29b0f896
AM		 969 {"noopt", s_ignore, 0},
970 {"optim", s_ignore, 0},
971 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
972 {"code16", set_code_flag, CODE_16BIT},
973 {"code32", set_code_flag, CODE_32BIT},
974 {"code64", set_code_flag, CODE_64BIT},
975 {"intel_syntax", set_intel_syntax, 1},
976 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 977 {"intel_mnemonic", set_intel_mnemonic, 1},
978 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 979 {"allow_index_reg", set_allow_index_reg, 1},
980 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 981 {"sse_check", set_check, 0},
982 {"operand_check", set_check, 1},
3b22753a
L		 983#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
984 {"largecomm", handle_large_common, 0},
07a53e5c 985#else
e3bb37b5 986 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 987 {"loc", dwarf2_directive_loc, 0},
988 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 989#endif
6482c264
NC		 990#ifdef TE_PE
991 {"secrel32", pe_directive_secrel, 0},
992#endif
29b0f896
AM		 993 {0, 0, 0}
994};
995
996/* For interface with expression (). */
997extern char *input_line_pointer;
998
999/* Hash table for instruction mnemonic lookup. */
1000static struct hash_control *op_hash;
1001
1002/* Hash table for register lookup. */
1003static struct hash_control *reg_hash;
1004\f
252b5132 1005void
e3bb37b5 1006i386_align_code (fragS *fragP, int count)
252b5132 1007{
ce8a8b2f
AM		 1008 /* Various efficient no-op patterns for aligning code labels.
1009 Note: Don't try to assemble the instructions in the comments.
1010 0L and 0w are not legal. */
252b5132
RH		 1011 static const char f32_1[] =
1012 {0x90}; /* nop */
1013 static const char f32_2[] =
ccc9c027 1014 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 1015 static const char f32_3[] =
1016 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1017 static const char f32_4[] =
1018 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1019 static const char f32_5[] =
1020 {0x90, /* nop */
1021 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1022 static const char f32_6[] =
1023 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1024 static const char f32_7[] =
1025 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1026 static const char f32_8[] =
1027 {0x90, /* nop */
1028 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1029 static const char f32_9[] =
1030 {0x89,0xf6, /* movl %esi,%esi */
1031 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1032 static const char f32_10[] =
1033 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1034 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1035 static const char f32_11[] =
1036 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1037 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1038 static const char f32_12[] =
1039 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1040 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1041 static const char f32_13[] =
1042 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1043 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1044 static const char f32_14[] =
1045 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1046 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 1047 static const char f16_3[] =
1048 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 1049 static const char f16_4[] =
1050 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1051 static const char f16_5[] =
1052 {0x90, /* nop */
1053 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1054 static const char f16_6[] =
1055 {0x89,0xf6, /* mov %si,%si */
1056 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1057 static const char f16_7[] =
1058 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1059 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1060 static const char f16_8[] =
1061 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1062 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 1063 static const char jump_31[] =
1064 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1065 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1066 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1067 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 1068 static const char *const f32_patt[] = {
1069 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1070 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 1071 };
1072 static const char *const f16_patt[] = {
76bc74dc 1073 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1074 };
ccc9c027
L		 1075 /* nopl (%[re]ax) */
1076 static const char alt_3[] =
1077 {0x0f,0x1f,0x00};
1078 /* nopl 0(%[re]ax) */
1079 static const char alt_4[] =
1080 {0x0f,0x1f,0x40,0x00};
1081 /* nopl 0(%[re]ax,%[re]ax,1) */
1082 static const char alt_5[] =
1083 {0x0f,0x1f,0x44,0x00,0x00};
1084 /* nopw 0(%[re]ax,%[re]ax,1) */
1085 static const char alt_6[] =
1086 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1087 /* nopl 0L(%[re]ax) */
1088 static const char alt_7[] =
1089 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1090 /* nopl 0L(%[re]ax,%[re]ax,1) */
1091 static const char alt_8[] =
1092 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1093 /* nopw 0L(%[re]ax,%[re]ax,1) */
1094 static const char alt_9[] =
1095 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1096 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1097 static const char alt_10[] =
1098 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1099 /* data16
1100 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1101 static const char alt_long_11[] =
1102 {0x66,
1103 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1104 /* data16
1105 data16
1106 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1107 static const char alt_long_12[] =
1108 {0x66,
1109 0x66,
1110 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1111 /* data16
1112 data16
1113 data16
1114 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1115 static const char alt_long_13[] =
1116 {0x66,
1117 0x66,
1118 0x66,
1119 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1120 /* data16
1121 data16
1122 data16
1123 data16
1124 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1125 static const char alt_long_14[] =
1126 {0x66,
1127 0x66,
1128 0x66,
1129 0x66,
1130 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1131 /* data16
1132 data16
1133 data16
1134 data16
1135 data16
1136 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1137 static const char alt_long_15[] =
1138 {0x66,
1139 0x66,
1140 0x66,
1141 0x66,
1142 0x66,
1143 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1144 /* nopl 0(%[re]ax,%[re]ax,1)
1145 nopw 0(%[re]ax,%[re]ax,1) */
1146 static const char alt_short_11[] =
1147 {0x0f,0x1f,0x44,0x00,0x00,
1148 0x66,0x0f,0x1f,0x44,0x00,0x00};
1149 /* nopw 0(%[re]ax,%[re]ax,1)
1150 nopw 0(%[re]ax,%[re]ax,1) */
1151 static const char alt_short_12[] =
1152 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1153 0x66,0x0f,0x1f,0x44,0x00,0x00};
1154 /* nopw 0(%[re]ax,%[re]ax,1)
1155 nopl 0L(%[re]ax) */
1156 static const char alt_short_13[] =
1157 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1158 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1159 /* nopl 0L(%[re]ax)
1160 nopl 0L(%[re]ax) */
1161 static const char alt_short_14[] =
1162 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1163 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1164 /* nopl 0L(%[re]ax)
1165 nopl 0L(%[re]ax,%[re]ax,1) */
1166 static const char alt_short_15[] =
1167 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1168 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1169 static const char *const alt_short_patt[] = {
1170 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1171 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
1172 alt_short_14, alt_short_15
1173 };
1174 static const char *const alt_long_patt[] = {
1175 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1176 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1177 alt_long_14, alt_long_15
1178 };
252b5132 1179
76bc74dc
L		 1180 /* Only align for at least a positive non-zero boundary. */
1181 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1182 return;
3e73aa7c 1183
ccc9c027
L		 1184 /* We need to decide which NOP sequence to use for 32bit and
1185 64bit. When -mtune= is used:
4eed87de 1186
76bc74dc
L		 1187 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1188 PROCESSOR_GENERIC32, f32_patt will be used.
1189 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 1190 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1191 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 1192 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
7b458c12 1193 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
69dd9865 1194 will be used.
ccc9c027 1195
76bc74dc 1196 When -mtune= isn't used, alt_long_patt will be used if
22109423 1197 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1198 be used.
ccc9c027
L		 1199
1200 When -march= or .arch is used, we can't use anything beyond
1201 cpu_arch_isa_flags. */
1202
1203 if (flag_code == CODE_16BIT)
1204 {
ccc9c027 1205 if (count > 8)
33fef721 1206 {
76bc74dc
L		 1207 memcpy (fragP->fr_literal + fragP->fr_fix,
1208 jump_31, count);
1209 /* Adjust jump offset. */
1210 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1211 }
76bc74dc
L		 1212 else
1213 memcpy (fragP->fr_literal + fragP->fr_fix,
1214 f16_patt[count - 1], count);
252b5132 1215 }
33fef721 1216 else
ccc9c027
L		 1217 {
1218 const char *const *patt = NULL;
1219
fbf3f584 1220 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1221 {
1222 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1223 switch (cpu_arch_tune)
1224 {
1225 case PROCESSOR_UNKNOWN:
1226 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1227 optimize with nops. */
1228 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1229 patt = alt_long_patt;
ccc9c027
L		 1230 else
1231 patt = f32_patt;
1232 break;
ccc9c027
L		 1233 case PROCESSOR_PENTIUM4:
1234 case PROCESSOR_NOCONA:
ef05d495 1235 case PROCESSOR_CORE:
76bc74dc 1236 case PROCESSOR_CORE2:
bd5295b2 1237 case PROCESSOR_COREI7:
3632d14b 1238 case PROCESSOR_L1OM:
7a9068fe 1239 case PROCESSOR_K1OM:
76bc74dc
L		 1240 case PROCESSOR_GENERIC64:
1241 patt = alt_long_patt;
1242 break;
ccc9c027
L		 1243 case PROCESSOR_K6:
1244 case PROCESSOR_ATHLON:
1245 case PROCESSOR_K8:
4eed87de 1246 case PROCESSOR_AMDFAM10:
8aedb9fe 1247 case PROCESSOR_BD:
7b458c12 1248 case PROCESSOR_BT:
ccc9c027
L		 1249 patt = alt_short_patt;
1250 break;
76bc74dc 1251 case PROCESSOR_I386:
ccc9c027
L		 1252 case PROCESSOR_I486:
1253 case PROCESSOR_PENTIUM:
2dde1948 1254 case PROCESSOR_PENTIUMPRO:
ccc9c027
L		 1255 case PROCESSOR_GENERIC32:
1256 patt = f32_patt;
1257 break;
4eed87de 1258 }
ccc9c027
L		 1259 }
1260 else
1261 {
fbf3f584 1262 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1263 {
1264 case PROCESSOR_UNKNOWN:
e6a14101 1265 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1266 PROCESSOR_UNKNOWN. */
1267 abort ();
1268 break;
1269
76bc74dc 1270 case PROCESSOR_I386:
ccc9c027
L		 1271 case PROCESSOR_I486:
1272 case PROCESSOR_PENTIUM:
ccc9c027
L		 1273 case PROCESSOR_K6:
1274 case PROCESSOR_ATHLON:
1275 case PROCESSOR_K8:
4eed87de 1276 case PROCESSOR_AMDFAM10:
8aedb9fe 1277 case PROCESSOR_BD:
7b458c12 1278 case PROCESSOR_BT:
ccc9c027
L		 1279 case PROCESSOR_GENERIC32:
1280 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1281 with nops. */
1282 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1283 patt = alt_short_patt;
1284 else
1285 patt = f32_patt;
1286 break;
76bc74dc
L		 1287 case PROCESSOR_PENTIUMPRO:
1288 case PROCESSOR_PENTIUM4:
1289 case PROCESSOR_NOCONA:
1290 case PROCESSOR_CORE:
ef05d495 1291 case PROCESSOR_CORE2:
bd5295b2 1292 case PROCESSOR_COREI7:
3632d14b 1293 case PROCESSOR_L1OM:
7a9068fe 1294 case PROCESSOR_K1OM:
22109423 1295 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1296 patt = alt_long_patt;
1297 else
1298 patt = f32_patt;
1299 break;
1300 case PROCESSOR_GENERIC64:
76bc74dc 1301 patt = alt_long_patt;
ccc9c027 1302 break;
4eed87de 1303 }
ccc9c027
L		 1304 }
1305
76bc74dc
L		 1306 if (patt == f32_patt)
1307 {
1308 /* If the padding is less than 15 bytes, we use the normal
1309 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1310 its offset. */
1311 int limit;
76ba9986 1312
711eedef
L		 1313 /* For 64bit, the limit is 3 bytes. */
1314 if (flag_code == CODE_64BIT
1315 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1316 limit = 3;
1317 else
1318 limit = 15;
1319 if (count < limit)
76bc74dc
L		 1320 memcpy (fragP->fr_literal + fragP->fr_fix,
1321 patt[count - 1], count);
1322 else
1323 {
1324 memcpy (fragP->fr_literal + fragP->fr_fix,
1325 jump_31, count);
1326 /* Adjust jump offset. */
1327 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1328 }
1329 }
1330 else
1331 {
1332 /* Maximum length of an instruction is 15 byte. If the
1333 padding is greater than 15 bytes and we don't use jump,
1334 we have to break it into smaller pieces. */
1335 int padding = count;
1336 while (padding > 15)
1337 {
1338 padding -= 15;
1339 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1340 patt [14], 15);
1341 }
1342
1343 if (padding)
1344 memcpy (fragP->fr_literal + fragP->fr_fix,
1345 patt [padding - 1], padding);
1346 }
ccc9c027 1347 }
33fef721 1348 fragP->fr_var = count;
252b5132
RH		 1349}
1350
c6fb90c8 1351static INLINE int
0dfbf9d7 1352operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1353{
0dfbf9d7 1354 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1355 {
1356 case 3:
0dfbf9d7 1357 if (x->array[2])
c6fb90c8
L		 1358 return 0;
1359 case 2:
0dfbf9d7 1360 if (x->array[1])
c6fb90c8
L		 1361 return 0;
1362 case 1:
0dfbf9d7 1363 return !x->array[0];
c6fb90c8
L		 1364 default:
1365 abort ();
1366 }
40fb9820
L		 1367}
1368
c6fb90c8 1369static INLINE void
0dfbf9d7 1370operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1371{
0dfbf9d7 1372 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1373 {
1374 case 3:
0dfbf9d7 1375 x->array[2] = v;
c6fb90c8 1376 case 2:
0dfbf9d7 1377 x->array[1] = v;
c6fb90c8 1378 case 1:
0dfbf9d7 1379 x->array[0] = v;
c6fb90c8
L		 1380 break;
1381 default:
1382 abort ();
1383 }
1384}
40fb9820 1385
c6fb90c8 1386static INLINE int
0dfbf9d7
L		 1387operand_type_equal (const union i386_operand_type *x,
1388 const union i386_operand_type *y)
c6fb90c8 1389{
0dfbf9d7 1390 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1391 {
1392 case 3:
0dfbf9d7 1393 if (x->array[2] != y->array[2])
c6fb90c8
L		 1394 return 0;
1395 case 2:
0dfbf9d7 1396 if (x->array[1] != y->array[1])
c6fb90c8
L		 1397 return 0;
1398 case 1:
0dfbf9d7 1399 return x->array[0] == y->array[0];
c6fb90c8
L		 1400 break;
1401 default:
1402 abort ();
1403 }
1404}
40fb9820 1405
0dfbf9d7
L		 1406static INLINE int
1407cpu_flags_all_zero (const union i386_cpu_flags *x)
1408{
1409 switch (ARRAY_SIZE(x->array))
1410 {
1411 case 3:
1412 if (x->array[2])
1413 return 0;
1414 case 2:
1415 if (x->array[1])
1416 return 0;
1417 case 1:
1418 return !x->array[0];
1419 default:
1420 abort ();
1421 }
1422}
1423
1424static INLINE void
1425cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1426{
1427 switch (ARRAY_SIZE(x->array))
1428 {
1429 case 3:
1430 x->array[2] = v;
1431 case 2:
1432 x->array[1] = v;
1433 case 1:
1434 x->array[0] = v;
1435 break;
1436 default:
1437 abort ();
1438 }
1439}
1440
1441static INLINE int
1442cpu_flags_equal (const union i386_cpu_flags *x,
1443 const union i386_cpu_flags *y)
1444{
1445 switch (ARRAY_SIZE(x->array))
1446 {
1447 case 3:
1448 if (x->array[2] != y->array[2])
1449 return 0;
1450 case 2:
1451 if (x->array[1] != y->array[1])
1452 return 0;
1453 case 1:
1454 return x->array[0] == y->array[0];
1455 break;
1456 default:
1457 abort ();
1458 }
1459}
c6fb90c8
L		 1460
1461static INLINE int
1462cpu_flags_check_cpu64 (i386_cpu_flags f)
1463{
1464 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1465 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1466}
1467
c6fb90c8
L		 1468static INLINE i386_cpu_flags
1469cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1470{
c6fb90c8
L		 1471 switch (ARRAY_SIZE (x.array))
1472 {
1473 case 3:
1474 x.array [2] &= y.array [2];
1475 case 2:
1476 x.array [1] &= y.array [1];
1477 case 1:
1478 x.array [0] &= y.array [0];
1479 break;
1480 default:
1481 abort ();
1482 }
1483 return x;
1484}
40fb9820 1485
c6fb90c8
L		 1486static INLINE i386_cpu_flags
1487cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1488{
c6fb90c8 1489 switch (ARRAY_SIZE (x.array))
40fb9820 1490 {
c6fb90c8
L		 1491 case 3:
1492 x.array [2] |= y.array [2];
1493 case 2:
1494 x.array [1] |= y.array [1];
1495 case 1:
1496 x.array [0] |= y.array [0];
40fb9820
L		 1497 break;
1498 default:
1499 abort ();
1500 }
40fb9820
L		 1501 return x;
1502}
1503
309d3373
JB		 1504static INLINE i386_cpu_flags
1505cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1506{
1507 switch (ARRAY_SIZE (x.array))
1508 {
1509 case 3:
1510 x.array [2] &= ~y.array [2];
1511 case 2:
1512 x.array [1] &= ~y.array [1];
1513 case 1:
1514 x.array [0] &= ~y.array [0];
1515 break;
1516 default:
1517 abort ();
1518 }
1519 return x;
1520}
1521
c0f3af97
L		 1522#define CPU_FLAGS_ARCH_MATCH 0x1
1523#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1524#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1525#define CPU_FLAGS_PCLMUL_MATCH 0x8
1526#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1527
a5ff0eb2 1528#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1529 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1530 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1531#define CPU_FLAGS_PERFECT_MATCH \
1532 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1533
1534/* Return CPU flags match bits. */
3629bb00 1535
40fb9820 1536static int
d3ce72d0 1537cpu_flags_match (const insn_template *t)
40fb9820 1538{
c0f3af97
L		 1539 i386_cpu_flags x = t->cpu_flags;
1540 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1541
1542 x.bitfield.cpu64 = 0;
1543 x.bitfield.cpuno64 = 0;
1544
0dfbf9d7 1545 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1546 {
1547 /* This instruction is available on all archs. */
1548 match |= CPU_FLAGS_32BIT_MATCH;
1549 }
3629bb00
L		 1550 else
1551 {
c0f3af97 1552 /* This instruction is available only on some archs. */
3629bb00
L		 1553 i386_cpu_flags cpu = cpu_arch_flags;
1554
1555 cpu.bitfield.cpu64 = 0;
1556 cpu.bitfield.cpuno64 = 0;
1557 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1558 if (!cpu_flags_all_zero (&cpu))
1559 {
a5ff0eb2
L		 1560 if (x.bitfield.cpuavx)
1561 {
ce2f5b3c 1562 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1563 if (cpu.bitfield.cpuavx)
1564 {
1565 /* Check SSE2AVX. */
1566 if (!t->opcode_modifier.sse2avx|| sse2avx)
1567 {
1568 match |= (CPU_FLAGS_ARCH_MATCH
1569 | CPU_FLAGS_AVX_MATCH);
1570 /* Check AES. */
1571 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1572 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1573 /* Check PCLMUL. */
1574 if (!x.bitfield.cpupclmul
1575 || cpu.bitfield.cpupclmul)
1576 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1577 }
1578 }
1579 else
1580 match |= CPU_FLAGS_ARCH_MATCH;
1581 }
1582 else
c0f3af97
L		 1583 match |= CPU_FLAGS_32BIT_MATCH;
1584 }
3629bb00 1585 }
c0f3af97 1586 return match;
40fb9820
L		 1587}
1588
c6fb90c8
L		 1589static INLINE i386_operand_type
1590operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1591{
c6fb90c8
L		 1592 switch (ARRAY_SIZE (x.array))
1593 {
1594 case 3:
1595 x.array [2] &= y.array [2];
1596 case 2:
1597 x.array [1] &= y.array [1];
1598 case 1:
1599 x.array [0] &= y.array [0];
1600 break;
1601 default:
1602 abort ();
1603 }
1604 return x;
40fb9820
L		 1605}
1606
c6fb90c8
L		 1607static INLINE i386_operand_type
1608operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1609{
c6fb90c8 1610 switch (ARRAY_SIZE (x.array))
40fb9820 1611 {
c6fb90c8
L		 1612 case 3:
1613 x.array [2] |= y.array [2];
1614 case 2:
1615 x.array [1] |= y.array [1];
1616 case 1:
1617 x.array [0] |= y.array [0];
40fb9820
L		 1618 break;
1619 default:
1620 abort ();
1621 }
c6fb90c8
L		 1622 return x;
1623}
40fb9820 1624
c6fb90c8
L		 1625static INLINE i386_operand_type
1626operand_type_xor (i386_operand_type x, i386_operand_type y)
1627{
1628 switch (ARRAY_SIZE (x.array))
1629 {
1630 case 3:
1631 x.array [2] ^= y.array [2];
1632 case 2:
1633 x.array [1] ^= y.array [1];
1634 case 1:
1635 x.array [0] ^= y.array [0];
1636 break;
1637 default:
1638 abort ();
1639 }
40fb9820
L		 1640 return x;
1641}
1642
1643static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1644static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1645static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1646static const i386_operand_type inoutportreg
1647 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1648static const i386_operand_type reg16_inoutportreg
1649 = OPERAND_TYPE_REG16_INOUTPORTREG;
1650static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1651static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1652static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1653static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1654static const i386_operand_type anydisp
1655 = OPERAND_TYPE_ANYDISP;
40fb9820 1656static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1657static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1658static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1659static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1660static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1661static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1662static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1663static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1664static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1665static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1666static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1667static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1668static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1669static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1670
1671enum operand_type
1672{
1673 reg,
40fb9820
L		 1674 imm,
1675 disp,
1676 anymem
1677};
1678
c6fb90c8 1679static INLINE int
40fb9820
L		 1680operand_type_check (i386_operand_type t, enum operand_type c)
1681{
1682 switch (c)
1683 {
1684 case reg:
1685 return (t.bitfield.reg8
1686 || t.bitfield.reg16
1687 || t.bitfield.reg32
1688 || t.bitfield.reg64);
1689
40fb9820
L		 1690 case imm:
1691 return (t.bitfield.imm8
1692 || t.bitfield.imm8s
1693 || t.bitfield.imm16
1694 || t.bitfield.imm32
1695 || t.bitfield.imm32s
1696 || t.bitfield.imm64);
1697
1698 case disp:
1699 return (t.bitfield.disp8
1700 || t.bitfield.disp16
1701 || t.bitfield.disp32
1702 || t.bitfield.disp32s
1703 || t.bitfield.disp64);
1704
1705 case anymem:
1706 return (t.bitfield.disp8
1707 || t.bitfield.disp16
1708 || t.bitfield.disp32
1709 || t.bitfield.disp32s
1710 || t.bitfield.disp64
1711 || t.bitfield.baseindex);
1712
1713 default:
1714 abort ();
1715 }
2cfe26b6
AM		 1716
1717 return 0;
40fb9820
L		 1718}
1719
5c07affc
L		 1720/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1721 operand J for instruction template T. */
1722
1723static INLINE int
d3ce72d0 1724match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1725{
1726 return !((i.types[j].bitfield.byte
1727 && !t->operand_types[j].bitfield.byte)
1728 || (i.types[j].bitfield.word
1729 && !t->operand_types[j].bitfield.word)
1730 || (i.types[j].bitfield.dword
1731 && !t->operand_types[j].bitfield.dword)
1732 || (i.types[j].bitfield.qword
1733 && !t->operand_types[j].bitfield.qword));
1734}
1735
1736/* Return 1 if there is no conflict in any size on operand J for
1737 instruction template T. */
1738
1739static INLINE int
d3ce72d0 1740match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1741{
1742 return (match_reg_size (t, j)
1743 && !((i.types[j].bitfield.unspecified
1744 && !t->operand_types[j].bitfield.unspecified)
1745 || (i.types[j].bitfield.fword
1746 && !t->operand_types[j].bitfield.fword)
1747 || (i.types[j].bitfield.tbyte
1748 && !t->operand_types[j].bitfield.tbyte)
1749 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1750 && !t->operand_types[j].bitfield.xmmword)
1751 || (i.types[j].bitfield.ymmword
43234a1e
L		 1752 && !t->operand_types[j].bitfield.ymmword)
1753 || (i.types[j].bitfield.zmmword
1754 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1755}
1756
1757/* Return 1 if there is no size conflict on any operands for
1758 instruction template T. */
1759
1760static INLINE int
d3ce72d0 1761operand_size_match (const insn_template *t)
5c07affc
L		 1762{
1763 unsigned int j;
1764 int match = 1;
1765
1766 /* Don't check jump instructions. */
1767 if (t->opcode_modifier.jump
1768 || t->opcode_modifier.jumpbyte
1769 || t->opcode_modifier.jumpdword
1770 || t->opcode_modifier.jumpintersegment)
1771 return match;
1772
1773 /* Check memory and accumulator operand size. */
1774 for (j = 0; j < i.operands; j++)
1775 {
1776 if (t->operand_types[j].bitfield.anysize)
1777 continue;
1778
1779 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1780 {
1781 match = 0;
1782 break;
1783 }
1784
1785 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1786 {
1787 match = 0;
1788 break;
1789 }
1790 }
1791
891edac4 1792 if (match)
5c07affc 1793 return match;
891edac4
L		 1794 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1795 {
1796mismatch:
86e026a4 1797 i.error = operand_size_mismatch;
891edac4
L		 1798 return 0;
1799 }
5c07affc
L		 1800
1801 /* Check reverse. */
9c2799c2 1802 gas_assert (i.operands == 2);
5c07affc
L		 1803
1804 match = 1;
1805 for (j = 0; j < 2; j++)
1806 {
1807 if (t->operand_types[j].bitfield.acc
1808 && !match_reg_size (t, j ? 0 : 1))
891edac4 1809 goto mismatch;
5c07affc
L		 1810
1811 if (i.types[j].bitfield.mem
1812 && !match_mem_size (t, j ? 0 : 1))
891edac4 1813 goto mismatch;
5c07affc
L		 1814 }
1815
1816 return match;
1817}
1818
c6fb90c8 1819static INLINE int
40fb9820
L		 1820operand_type_match (i386_operand_type overlap,
1821 i386_operand_type given)
1822{
1823 i386_operand_type temp = overlap;
1824
1825 temp.bitfield.jumpabsolute = 0;
7d5e4556 1826 temp.bitfield.unspecified = 0;
5c07affc
L		 1827 temp.bitfield.byte = 0;
1828 temp.bitfield.word = 0;
1829 temp.bitfield.dword = 0;
1830 temp.bitfield.fword = 0;
1831 temp.bitfield.qword = 0;
1832 temp.bitfield.tbyte = 0;
1833 temp.bitfield.xmmword = 0;
c0f3af97 1834 temp.bitfield.ymmword = 0;
43234a1e 1835 temp.bitfield.zmmword = 0;
0dfbf9d7 1836 if (operand_type_all_zero (&temp))
891edac4 1837 goto mismatch;
40fb9820 1838
891edac4
L		 1839 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1840 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1841 return 1;
1842
1843mismatch:
a65babc9 1844 i.error = operand_type_mismatch;
891edac4 1845 return 0;
40fb9820
L		 1846}
1847
7d5e4556 1848/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1849 unless the expected operand type register overlap is null.
1850 Note that Acc in a template matches every size of reg. */
1851
c6fb90c8 1852static INLINE int
40fb9820
L		 1853operand_type_register_match (i386_operand_type m0,
1854 i386_operand_type g0,
1855 i386_operand_type t0,
1856 i386_operand_type m1,
1857 i386_operand_type g1,
1858 i386_operand_type t1)
1859{
1860 if (!operand_type_check (g0, reg))
1861 return 1;
1862
1863 if (!operand_type_check (g1, reg))
1864 return 1;
1865
1866 if (g0.bitfield.reg8 == g1.bitfield.reg8
1867 && g0.bitfield.reg16 == g1.bitfield.reg16
1868 && g0.bitfield.reg32 == g1.bitfield.reg32
1869 && g0.bitfield.reg64 == g1.bitfield.reg64)
1870 return 1;
1871
1872 if (m0.bitfield.acc)
1873 {
1874 t0.bitfield.reg8 = 1;
1875 t0.bitfield.reg16 = 1;
1876 t0.bitfield.reg32 = 1;
1877 t0.bitfield.reg64 = 1;
1878 }
1879
1880 if (m1.bitfield.acc)
1881 {
1882 t1.bitfield.reg8 = 1;
1883 t1.bitfield.reg16 = 1;
1884 t1.bitfield.reg32 = 1;
1885 t1.bitfield.reg64 = 1;
1886 }
1887
891edac4
L		 1888 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1889 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1890 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1891 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1892 return 1;
1893
a65babc9 1894 i.error = register_type_mismatch;
891edac4
L		 1895
1896 return 0;
40fb9820
L		 1897}
1898
4c692bc7
JB		 1899static INLINE unsigned int
1900register_number (const reg_entry *r)
1901{
1902 unsigned int nr = r->reg_num;
1903
1904 if (r->reg_flags & RegRex)
1905 nr += 8;
1906
1907 return nr;
1908}
1909
252b5132 1910static INLINE unsigned int
40fb9820 1911mode_from_disp_size (i386_operand_type t)
252b5132 1912{
43234a1e 1913 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1914 return 1;
1915 else if (t.bitfield.disp16
1916 || t.bitfield.disp32
1917 || t.bitfield.disp32s)
1918 return 2;
1919 else
1920 return 0;
252b5132
RH		 1921}
1922
1923static INLINE int
e3bb37b5 1924fits_in_signed_byte (offsetT num)
252b5132
RH		 1925{
1926 return (num >= -128) && (num <= 127);
47926f60 1927}
252b5132
RH		 1928
1929static INLINE int
e3bb37b5 1930fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1931{
1932 return (num & 0xff) == num;
47926f60 1933}
252b5132
RH		 1934
1935static INLINE int
e3bb37b5 1936fits_in_unsigned_word (offsetT num)
252b5132
RH		 1937{
1938 return (num & 0xffff) == num;
47926f60 1939}
252b5132
RH		 1940
1941static INLINE int
e3bb37b5 1942fits_in_signed_word (offsetT num)
252b5132
RH		 1943{
1944 return (-32768 <= num) && (num <= 32767);
47926f60 1945}
2a962e6d 1946
3e73aa7c 1947static INLINE int
e3bb37b5 1948fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1949{
1950#ifndef BFD64
1951 return 1;
1952#else
1953 return (!(((offsetT) -1 << 31) & num)
1954 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1955#endif
1956} /* fits_in_signed_long() */
2a962e6d 1957
3e73aa7c 1958static INLINE int
e3bb37b5 1959fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1960{
1961#ifndef BFD64
1962 return 1;
1963#else
1964 return (num & (((offsetT) 2 << 31) - 1)) == num;
1965#endif
1966} /* fits_in_unsigned_long() */
252b5132 1967
43234a1e
L		 1968static INLINE int
1969fits_in_vec_disp8 (offsetT num)
1970{
1971 int shift = i.memshift;
1972 unsigned int mask;
1973
1974 if (shift == -1)
1975 abort ();
1976
1977 mask = (1 << shift) - 1;
1978
1979 /* Return 0 if NUM isn't properly aligned. */
1980 if ((num & mask))
1981 return 0;
1982
1983 /* Check if NUM will fit in 8bit after shift. */
1984 return fits_in_signed_byte (num >> shift);
1985}
1986
a683cc34
SP		 1987static INLINE int
1988fits_in_imm4 (offsetT num)
1989{
1990 return (num & 0xf) == num;
1991}
1992
40fb9820 1993static i386_operand_type
e3bb37b5 1994smallest_imm_type (offsetT num)
252b5132 1995{
40fb9820 1996 i386_operand_type t;
7ab9ffdd 1997
0dfbf9d7 1998 operand_type_set (&t, 0);
40fb9820
L		 1999 t.bitfield.imm64 = 1;
2000
2001 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2002 {
2003 /* This code is disabled on the 486 because all the Imm1 forms
2004 in the opcode table are slower on the i486. They're the
2005 versions with the implicitly specified single-position
2006 displacement, which has another syntax if you really want to
2007 use that form. */
40fb9820
L		 2008 t.bitfield.imm1 = 1;
2009 t.bitfield.imm8 = 1;
2010 t.bitfield.imm8s = 1;
2011 t.bitfield.imm16 = 1;
2012 t.bitfield.imm32 = 1;
2013 t.bitfield.imm32s = 1;
2014 }
2015 else if (fits_in_signed_byte (num))
2016 {
2017 t.bitfield.imm8 = 1;
2018 t.bitfield.imm8s = 1;
2019 t.bitfield.imm16 = 1;
2020 t.bitfield.imm32 = 1;
2021 t.bitfield.imm32s = 1;
2022 }
2023 else if (fits_in_unsigned_byte (num))
2024 {
2025 t.bitfield.imm8 = 1;
2026 t.bitfield.imm16 = 1;
2027 t.bitfield.imm32 = 1;
2028 t.bitfield.imm32s = 1;
2029 }
2030 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2031 {
2032 t.bitfield.imm16 = 1;
2033 t.bitfield.imm32 = 1;
2034 t.bitfield.imm32s = 1;
2035 }
2036 else if (fits_in_signed_long (num))
2037 {
2038 t.bitfield.imm32 = 1;
2039 t.bitfield.imm32s = 1;
2040 }
2041 else if (fits_in_unsigned_long (num))
2042 t.bitfield.imm32 = 1;
2043
2044 return t;
47926f60 2045}
252b5132 2046
847f7ad4 2047static offsetT
e3bb37b5 2048offset_in_range (offsetT val, int size)
847f7ad4 2049{
508866be 2050 addressT mask;
ba2adb93 2051
847f7ad4
AM		 2052 switch (size)
2053 {
508866be
L		 2054 case 1: mask = ((addressT) 1 << 8) - 1; break;
2055 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2056 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2057#ifdef BFD64
2058 case 8: mask = ((addressT) 2 << 63) - 1; break;
2059#endif
47926f60 2060 default: abort ();
847f7ad4
AM		 2061 }
2062
9de868bf
L		 2063#ifdef BFD64
2064 /* If BFD64, sign extend val for 32bit address mode. */
2065 if (flag_code != CODE_64BIT
2066 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2067 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2068 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2069#endif
ba2adb93 2070
47926f60 2071 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2072 {
2073 char buf1[40], buf2[40];
2074
2075 sprint_value (buf1, val);
2076 sprint_value (buf2, val & mask);
2077 as_warn (_("%s shortened to %s"), buf1, buf2);
2078 }
2079 return val & mask;
2080}
2081
c32fa91d
L		 2082enum PREFIX_GROUP
2083{
2084 PREFIX_EXIST = 0,
2085 PREFIX_LOCK,
2086 PREFIX_REP,
2087 PREFIX_OTHER
2088};
2089
2090/* Returns
2091 a. PREFIX_EXIST if attempting to add a prefix where one from the
2092 same class already exists.
2093 b. PREFIX_LOCK if lock prefix is added.
2094 c. PREFIX_REP if rep/repne prefix is added.
2095 d. PREFIX_OTHER if other prefix is added.
2096 */
2097
2098static enum PREFIX_GROUP
e3bb37b5 2099add_prefix (unsigned int prefix)
252b5132 2100{
c32fa91d 2101 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2102 unsigned int q;
252b5132 2103
29b0f896
AM		 2104 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2105 && flag_code == CODE_64BIT)
b1905489 2106 {
161a04f6
L		 2107 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2108 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2109 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2110 ret = PREFIX_EXIST;
b1905489
JB		 2111 q = REX_PREFIX;
2112 }
3e73aa7c 2113 else
b1905489
JB		 2114 {
2115 switch (prefix)
2116 {
2117 default:
2118 abort ();
2119
2120 case CS_PREFIX_OPCODE:
2121 case DS_PREFIX_OPCODE:
2122 case ES_PREFIX_OPCODE:
2123 case FS_PREFIX_OPCODE:
2124 case GS_PREFIX_OPCODE:
2125 case SS_PREFIX_OPCODE:
2126 q = SEG_PREFIX;
2127 break;
2128
2129 case REPNE_PREFIX_OPCODE:
2130 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2131 q = REP_PREFIX;
2132 ret = PREFIX_REP;
2133 break;
2134
b1905489 2135 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2136 q = LOCK_PREFIX;
2137 ret = PREFIX_LOCK;
b1905489
JB		 2138 break;
2139
2140 case FWAIT_OPCODE:
2141 q = WAIT_PREFIX;
2142 break;
2143
2144 case ADDR_PREFIX_OPCODE:
2145 q = ADDR_PREFIX;
2146 break;
2147
2148 case DATA_PREFIX_OPCODE:
2149 q = DATA_PREFIX;
2150 break;
2151 }
2152 if (i.prefix[q] != 0)
c32fa91d 2153 ret = PREFIX_EXIST;
b1905489 2154 }
252b5132 2155
b1905489 2156 if (ret)
252b5132 2157 {
b1905489
JB		 2158 if (!i.prefix[q])
2159 ++i.prefixes;
2160 i.prefix[q] |= prefix;
252b5132 2161 }
b1905489
JB		 2162 else
2163 as_bad (_("same type of prefix used twice"));
252b5132 2164
252b5132
RH		 2165 return ret;
2166}
2167
2168static void
78f12dd3 2169update_code_flag (int value, int check)
eecb386c 2170{
78f12dd3
L		 2171 PRINTF_LIKE ((*as_error));
2172
1e9cc1c2 2173 flag_code = (enum flag_code) value;
40fb9820
L		 2174 if (flag_code == CODE_64BIT)
2175 {
2176 cpu_arch_flags.bitfield.cpu64 = 1;
2177 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2178 }
2179 else
2180 {
2181 cpu_arch_flags.bitfield.cpu64 = 0;
2182 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2183 }
2184 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2185 {
78f12dd3
L		 2186 if (check)
2187 as_error = as_fatal;
2188 else
2189 as_error = as_bad;
2190 (*as_error) (_("64bit mode not supported on `%s'."),
2191 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2192 }
40fb9820 2193 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2194 {
78f12dd3
L		 2195 if (check)
2196 as_error = as_fatal;
2197 else
2198 as_error = as_bad;
2199 (*as_error) (_("32bit mode not supported on `%s'."),
2200 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2201 }
eecb386c
AM		 2202 stackop_size = '\0';
2203}
2204
78f12dd3
L		 2205static void
2206set_code_flag (int value)
2207{
2208 update_code_flag (value, 0);
2209}
2210
eecb386c 2211static void
e3bb37b5 2212set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2213{
1e9cc1c2 2214 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2215 if (flag_code != CODE_16BIT)
2216 abort ();
2217 cpu_arch_flags.bitfield.cpu64 = 0;
2218 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2219 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2220}
2221
2222static void
e3bb37b5 2223set_intel_syntax (int syntax_flag)
252b5132
RH		 2224{
2225 /* Find out if register prefixing is specified. */
2226 int ask_naked_reg = 0;
2227
2228 SKIP_WHITESPACE ();
29b0f896 2229 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2230 {
2231 char *string = input_line_pointer;
2232 int e = get_symbol_end ();
2233
47926f60 2234 if (strcmp (string, "prefix") == 0)
252b5132 2235 ask_naked_reg = 1;
47926f60 2236 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2237 ask_naked_reg = -1;
2238 else
d0b47220 2239 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2240 *input_line_pointer = e;
2241 }
2242 demand_empty_rest_of_line ();
c3332e24 2243
252b5132
RH		 2244 intel_syntax = syntax_flag;
2245
2246 if (ask_naked_reg == 0)
f86103b7
AM		 2247 allow_naked_reg = (intel_syntax
2248 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2249 else
2250 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2251
ee86248c 2252 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2253
e4a3b5a4 2254 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2255 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2256 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2257}
2258
1efbbeb4
L		 2259static void
2260set_intel_mnemonic (int mnemonic_flag)
2261{
e1d4d893 2262 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2263}
2264
db51cc60
L		 2265static void
2266set_allow_index_reg (int flag)
2267{
2268 allow_index_reg = flag;
2269}
2270
cb19c032 2271static void
7bab8ab5 2272set_check (int what)
cb19c032 2273{
7bab8ab5
JB		 2274 enum check_kind *kind;
2275 const char *str;
2276
2277 if (what)
2278 {
2279 kind = &operand_check;
2280 str = "operand";
2281 }
2282 else
2283 {
2284 kind = &sse_check;
2285 str = "sse";
2286 }
2287
cb19c032
L		 2288 SKIP_WHITESPACE ();
2289
2290 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2291 {
2292 char *string = input_line_pointer;
2293 int e = get_symbol_end ();
2294
2295 if (strcmp (string, "none") == 0)
7bab8ab5 2296 *kind = check_none;
cb19c032 2297 else if (strcmp (string, "warning") == 0)
7bab8ab5 2298 *kind = check_warning;
cb19c032 2299 else if (strcmp (string, "error") == 0)
7bab8ab5 2300 *kind = check_error;
cb19c032 2301 else
7bab8ab5 2302 as_bad (_("bad argument to %s_check directive."), str);
cb19c032
L		 2303 *input_line_pointer = e;
2304 }
2305 else
7bab8ab5 2306 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2307
2308 demand_empty_rest_of_line ();
2309}
2310
8a9036a4
L		 2311static void
2312check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2313 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2314{
2315#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2316 static const char *arch;
2317
2318 /* Intel LIOM is only supported on ELF. */
2319 if (!IS_ELF)
2320 return;
2321
2322 if (!arch)
2323 {
2324 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2325 use default_arch. */
2326 arch = cpu_arch_name;
2327 if (!arch)
2328 arch = default_arch;
2329 }
2330
3632d14b 2331 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2332 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2333 || new_flag.bitfield.cpul1om)
8a9036a4 2334 return;
76ba9986 2335
7a9068fe
L		 2336 /* If we are targeting Intel K1OM, we must enable it. */
2337 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2338 || new_flag.bitfield.cpuk1om)
2339 return;
2340
8a9036a4
L		 2341 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2342#endif
2343}
2344
e413e4e9 2345static void
e3bb37b5 2346set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2347{
47926f60 2348 SKIP_WHITESPACE ();
e413e4e9 2349
29b0f896 2350 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2351 {
2352 char *string = input_line_pointer;
2353 int e = get_symbol_end ();
91d6fa6a 2354 unsigned int j;
40fb9820 2355 i386_cpu_flags flags;
e413e4e9 2356
91d6fa6a 2357 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2358 {
91d6fa6a 2359 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2360 {
91d6fa6a 2361 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2362
5c6af06e
JB		 2363 if (*string != '.')
2364 {
91d6fa6a 2365 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2366 cpu_sub_arch_name = NULL;
91d6fa6a 2367 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2368 if (flag_code == CODE_64BIT)
2369 {
2370 cpu_arch_flags.bitfield.cpu64 = 1;
2371 cpu_arch_flags.bitfield.cpuno64 = 0;
2372 }
2373 else
2374 {
2375 cpu_arch_flags.bitfield.cpu64 = 0;
2376 cpu_arch_flags.bitfield.cpuno64 = 1;
2377 }
91d6fa6a
NC		 2378 cpu_arch_isa = cpu_arch[j].type;
2379 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2380 if (!cpu_arch_tune_set)
2381 {
2382 cpu_arch_tune = cpu_arch_isa;
2383 cpu_arch_tune_flags = cpu_arch_isa_flags;
2384 }
5c6af06e
JB		 2385 break;
2386 }
40fb9820 2387
22109423 2388 if (!cpu_arch[j].negated)
309d3373 2389 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2390 cpu_arch[j].flags);
309d3373
JB		 2391 else
2392 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2393 cpu_arch[j].flags);
0dfbf9d7 2394 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2395 {
6305a203
L		 2396 if (cpu_sub_arch_name)
2397 {
2398 char *name = cpu_sub_arch_name;
2399 cpu_sub_arch_name = concat (name,
91d6fa6a 2400 cpu_arch[j].name,
1bf57e9f 2401 (const char *) NULL);
6305a203
L		 2402 free (name);
2403 }
2404 else
91d6fa6a 2405 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2406 cpu_arch_flags = flags;
a586129e 2407 cpu_arch_isa_flags = flags;
5c6af06e
JB		 2408 }
2409 *input_line_pointer = e;
2410 demand_empty_rest_of_line ();
2411 return;
e413e4e9
AM		 2412 }
2413 }
91d6fa6a 2414 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2415 as_bad (_("no such architecture: `%s'"), string);
2416
2417 *input_line_pointer = e;
2418 }
2419 else
2420 as_bad (_("missing cpu architecture"));
2421
fddf5b5b
AM		 2422 no_cond_jump_promotion = 0;
2423 if (*input_line_pointer == ','
29b0f896 2424 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2425 {
2426 char *string = ++input_line_pointer;
2427 int e = get_symbol_end ();
2428
2429 if (strcmp (string, "nojumps") == 0)
2430 no_cond_jump_promotion = 1;
2431 else if (strcmp (string, "jumps") == 0)
2432 ;
2433 else
2434 as_bad (_("no such architecture modifier: `%s'"), string);
2435
2436 *input_line_pointer = e;
2437 }
2438
e413e4e9
AM		 2439 demand_empty_rest_of_line ();
2440}
2441
8a9036a4
L		 2442enum bfd_architecture
2443i386_arch (void)
2444{
3632d14b 2445 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2446 {
2447 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2448 || flag_code != CODE_64BIT)
2449 as_fatal (_("Intel L1OM is 64bit ELF only"));
2450 return bfd_arch_l1om;
2451 }
7a9068fe
L		 2452 else if (cpu_arch_isa == PROCESSOR_K1OM)
2453 {
2454 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2455 || flag_code != CODE_64BIT)
2456 as_fatal (_("Intel K1OM is 64bit ELF only"));
2457 return bfd_arch_k1om;
2458 }
8a9036a4
L		 2459 else
2460 return bfd_arch_i386;
2461}
2462
b9d79e03 2463unsigned long
7016a5d5 2464i386_mach (void)
b9d79e03 2465{
351f65ca 2466 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2467 {
3632d14b 2468 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2469 {
351f65ca
L		 2470 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2471 || default_arch[6] != '\0')
8a9036a4
L		 2472 as_fatal (_("Intel L1OM is 64bit ELF only"));
2473 return bfd_mach_l1om;
2474 }
7a9068fe
L		 2475 else if (cpu_arch_isa == PROCESSOR_K1OM)
2476 {
2477 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2478 || default_arch[6] != '\0')
2479 as_fatal (_("Intel K1OM is 64bit ELF only"));
2480 return bfd_mach_k1om;
2481 }
351f65ca 2482 else if (default_arch[6] == '\0')
8a9036a4 2483 return bfd_mach_x86_64;
351f65ca
L		 2484 else
2485 return bfd_mach_x64_32;
8a9036a4 2486 }
b9d79e03
JH		 2487 else if (!strcmp (default_arch, "i386"))
2488 return bfd_mach_i386_i386;
2489 else
2b5d6a91 2490 as_fatal (_("unknown architecture"));
b9d79e03 2491}
b9d79e03 2492\f
252b5132 2493void
7016a5d5 2494md_begin (void)
252b5132
RH		 2495{
2496 const char *hash_err;
2497
47926f60 2498 /* Initialize op_hash hash table. */
252b5132
RH		 2499 op_hash = hash_new ();
2500
2501 {
d3ce72d0 2502 const insn_template *optab;
29b0f896 2503 templates *core_optab;
252b5132 2504
47926f60
KH		 2505 /* Setup for loop. */
2506 optab = i386_optab;
252b5132
RH		 2507 core_optab = (templates *) xmalloc (sizeof (templates));
2508 core_optab->start = optab;
2509
2510 while (1)
2511 {
2512 ++optab;
2513 if (optab->name == NULL
2514 || strcmp (optab->name, (optab - 1)->name) != 0)
2515 {
2516 /* different name --> ship out current template list;
47926f60 2517 add to hash table; & begin anew. */
252b5132
RH		 2518 core_optab->end = optab;
2519 hash_err = hash_insert (op_hash,
2520 (optab - 1)->name,
5a49b8ac 2521 (void *) core_optab);
252b5132
RH		 2522 if (hash_err)
2523 {
b37df7c4 2524 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2525 (optab - 1)->name,
2526 hash_err);
2527 }
2528 if (optab->name == NULL)
2529 break;
2530 core_optab = (templates *) xmalloc (sizeof (templates));
2531 core_optab->start = optab;
2532 }
2533 }
2534 }
2535
47926f60 2536 /* Initialize reg_hash hash table. */
252b5132
RH		 2537 reg_hash = hash_new ();
2538 {
29b0f896 2539 const reg_entry *regtab;
c3fe08fa 2540 unsigned int regtab_size = i386_regtab_size;
252b5132 2541
c3fe08fa 2542 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2543 {
5a49b8ac 2544 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2545 if (hash_err)
b37df7c4 2546 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2547 regtab->reg_name,
2548 hash_err);
252b5132
RH		 2549 }
2550 }
2551
47926f60 2552 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2553 {
29b0f896
AM		 2554 int c;
2555 char *p;
252b5132
RH		 2556
2557 for (c = 0; c < 256; c++)
2558 {
3882b010 2559 if (ISDIGIT (c))
252b5132
RH		 2560 {
2561 digit_chars[c] = c;
2562 mnemonic_chars[c] = c;
2563 register_chars[c] = c;
2564 operand_chars[c] = c;
2565 }
3882b010 2566 else if (ISLOWER (c))
252b5132
RH		 2567 {
2568 mnemonic_chars[c] = c;
2569 register_chars[c] = c;
2570 operand_chars[c] = c;
2571 }
3882b010 2572 else if (ISUPPER (c))
252b5132 2573 {
3882b010 2574 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2575 register_chars[c] = mnemonic_chars[c];
2576 operand_chars[c] = c;
2577 }
43234a1e
L		 2578 else if (c == '{' || c == '}')
2579 operand_chars[c] = c;
252b5132 2580
3882b010 2581 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2582 identifier_chars[c] = c;
2583 else if (c >= 128)
2584 {
2585 identifier_chars[c] = c;
2586 operand_chars[c] = c;
2587 }
2588 }
2589
2590#ifdef LEX_AT
2591 identifier_chars['@'] = '@';
32137342
NC		 2592#endif
2593#ifdef LEX_QM
2594 identifier_chars['?'] = '?';
2595 operand_chars['?'] = '?';
252b5132 2596#endif
252b5132 2597 digit_chars['-'] = '-';
c0f3af97 2598 mnemonic_chars['_'] = '_';
791fe849 2599 mnemonic_chars['-'] = '-';
0003779b 2600 mnemonic_chars['.'] = '.';
252b5132
RH		 2601 identifier_chars['_'] = '_';
2602 identifier_chars['.'] = '.';
2603
2604 for (p = operand_special_chars; *p != '\0'; p++)
2605 operand_chars[(unsigned char) *p] = *p;
2606 }
2607
a4447b93
RH		 2608 if (flag_code == CODE_64BIT)
2609 {
ca19b261
KT		 2610#if defined (OBJ_COFF) && defined (TE_PE)
2611 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2612 ? 32 : 16);
2613#else
a4447b93 2614 x86_dwarf2_return_column = 16;
ca19b261 2615#endif
61ff971f 2616 x86_cie_data_alignment = -8;
a4447b93
RH		 2617 }
2618 else
2619 {
2620 x86_dwarf2_return_column = 8;
2621 x86_cie_data_alignment = -4;
2622 }
252b5132
RH		 2623}
2624
2625void
e3bb37b5 2626i386_print_statistics (FILE *file)
252b5132
RH		 2627{
2628 hash_print_statistics (file, "i386 opcode", op_hash);
2629 hash_print_statistics (file, "i386 register", reg_hash);
2630}
2631\f
252b5132
RH		 2632#ifdef DEBUG386
2633
ce8a8b2f 2634/* Debugging routines for md_assemble. */
d3ce72d0 2635static void pte (insn_template *);
40fb9820 2636static void pt (i386_operand_type);
e3bb37b5
L		 2637static void pe (expressionS *);
2638static void ps (symbolS *);
252b5132
RH		 2639
2640static void
e3bb37b5 2641pi (char *line, i386_insn *x)
252b5132 2642{
09137c09 2643 unsigned int j;
252b5132
RH		 2644
2645 fprintf (stdout, "%s: template ", line);
2646 pte (&x->tm);
09f131f2
JH		 2647 fprintf (stdout, " address: base %s index %s scale %x\n",
2648 x->base_reg ? x->base_reg->reg_name : "none",
2649 x->index_reg ? x->index_reg->reg_name : "none",
2650 x->log2_scale_factor);
2651 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2652 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2653 fprintf (stdout, " sib: base %x index %x scale %x\n",
2654 x->sib.base, x->sib.index, x->sib.scale);
2655 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2656 (x->rex & REX_W) != 0,
2657 (x->rex & REX_R) != 0,
2658 (x->rex & REX_X) != 0,
2659 (x->rex & REX_B) != 0);
09137c09 2660 for (j = 0; j < x->operands; j++)
252b5132 2661 {
09137c09
SP		 2662 fprintf (stdout, " #%d: ", j + 1);
2663 pt (x->types[j]);
252b5132 2664 fprintf (stdout, "\n");
09137c09
SP		 2665 if (x->types[j].bitfield.reg8
2666 || x->types[j].bitfield.reg16
2667 || x->types[j].bitfield.reg32
2668 || x->types[j].bitfield.reg64
2669 || x->types[j].bitfield.regmmx
2670 || x->types[j].bitfield.regxmm
2671 || x->types[j].bitfield.regymm
43234a1e 2672 || x->types[j].bitfield.regzmm
09137c09
SP		 2673 || x->types[j].bitfield.sreg2
2674 || x->types[j].bitfield.sreg3
2675 || x->types[j].bitfield.control
2676 || x->types[j].bitfield.debug
2677 || x->types[j].bitfield.test)
2678 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2679 if (operand_type_check (x->types[j], imm))
2680 pe (x->op[j].imms);
2681 if (operand_type_check (x->types[j], disp))
2682 pe (x->op[j].disps);
252b5132
RH		 2683 }
2684}
2685
2686static void
d3ce72d0 2687pte (insn_template *t)
252b5132 2688{
09137c09 2689 unsigned int j;
252b5132 2690 fprintf (stdout, " %d operands ", t->operands);
47926f60 2691 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2692 if (t->extension_opcode != None)
2693 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2694 if (t->opcode_modifier.d)
252b5132 2695 fprintf (stdout, "D");
40fb9820 2696 if (t->opcode_modifier.w)
252b5132
RH		 2697 fprintf (stdout, "W");
2698 fprintf (stdout, "\n");
09137c09 2699 for (j = 0; j < t->operands; j++)
252b5132 2700 {
09137c09
SP		 2701 fprintf (stdout, " #%d type ", j + 1);
2702 pt (t->operand_types[j]);
252b5132
RH		 2703 fprintf (stdout, "\n");
2704 }
2705}
2706
2707static void
e3bb37b5 2708pe (expressionS *e)
252b5132 2709{
24eab124 2710 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2711 fprintf (stdout, " add_number %ld (%lx)\n",
2712 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2713 if (e->X_add_symbol)
2714 {
2715 fprintf (stdout, " add_symbol ");
2716 ps (e->X_add_symbol);
2717 fprintf (stdout, "\n");
2718 }
2719 if (e->X_op_symbol)
2720 {
2721 fprintf (stdout, " op_symbol ");
2722 ps (e->X_op_symbol);
2723 fprintf (stdout, "\n");
2724 }
2725}
2726
2727static void
e3bb37b5 2728ps (symbolS *s)
252b5132
RH		 2729{
2730 fprintf (stdout, "%s type %s%s",
2731 S_GET_NAME (s),
2732 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2733 segment_name (S_GET_SEGMENT (s)));
2734}
2735
7b81dfbb 2736static struct type_name
252b5132 2737 {
40fb9820
L		 2738 i386_operand_type mask;
2739 const char *name;
252b5132 2740 }
7b81dfbb 2741const type_names[] =
252b5132 2742{
40fb9820
L		 2743 { OPERAND_TYPE_REG8, "r8" },
2744 { OPERAND_TYPE_REG16, "r16" },
2745 { OPERAND_TYPE_REG32, "r32" },
2746 { OPERAND_TYPE_REG64, "r64" },
2747 { OPERAND_TYPE_IMM8, "i8" },
2748 { OPERAND_TYPE_IMM8, "i8s" },
2749 { OPERAND_TYPE_IMM16, "i16" },
2750 { OPERAND_TYPE_IMM32, "i32" },
2751 { OPERAND_TYPE_IMM32S, "i32s" },
2752 { OPERAND_TYPE_IMM64, "i64" },
2753 { OPERAND_TYPE_IMM1, "i1" },
2754 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2755 { OPERAND_TYPE_DISP8, "d8" },
2756 { OPERAND_TYPE_DISP16, "d16" },
2757 { OPERAND_TYPE_DISP32, "d32" },
2758 { OPERAND_TYPE_DISP32S, "d32s" },
2759 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2760 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2761 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2762 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2763 { OPERAND_TYPE_CONTROL, "control reg" },
2764 { OPERAND_TYPE_TEST, "test reg" },
2765 { OPERAND_TYPE_DEBUG, "debug reg" },
2766 { OPERAND_TYPE_FLOATREG, "FReg" },
2767 { OPERAND_TYPE_FLOATACC, "FAcc" },
2768 { OPERAND_TYPE_SREG2, "SReg2" },
2769 { OPERAND_TYPE_SREG3, "SReg3" },
2770 { OPERAND_TYPE_ACC, "Acc" },
2771 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2772 { OPERAND_TYPE_REGMMX, "rMMX" },
2773 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2774 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2775 { OPERAND_TYPE_REGZMM, "rZMM" },
2776 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2777 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2778};
2779
2780static void
40fb9820 2781pt (i386_operand_type t)
252b5132 2782{
40fb9820 2783 unsigned int j;
c6fb90c8 2784 i386_operand_type a;
252b5132 2785
40fb9820 2786 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2787 {
2788 a = operand_type_and (t, type_names[j].mask);
0349dc08 2789 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2790 fprintf (stdout, "%s, ", type_names[j].name);
2791 }
252b5132
RH		 2792 fflush (stdout);
2793}
2794
2795#endif /* DEBUG386 */
2796\f
252b5132 2797static bfd_reloc_code_real_type
3956db08 2798reloc (unsigned int size,
64e74474
AM		 2799 int pcrel,
2800 int sign,
c3320543 2801 int bnd_prefix,
64e74474 2802 bfd_reloc_code_real_type other)
252b5132 2803{
47926f60 2804 if (other != NO_RELOC)
3956db08 2805 {
91d6fa6a 2806 reloc_howto_type *rel;
3956db08
JB		 2807
2808 if (size == 8)
2809 switch (other)
2810 {
64e74474
AM		 2811 case BFD_RELOC_X86_64_GOT32:
2812 return BFD_RELOC_X86_64_GOT64;
2813 break;
2814 case BFD_RELOC_X86_64_PLTOFF64:
2815 return BFD_RELOC_X86_64_PLTOFF64;
2816 break;
2817 case BFD_RELOC_X86_64_GOTPC32:
2818 other = BFD_RELOC_X86_64_GOTPC64;
2819 break;
2820 case BFD_RELOC_X86_64_GOTPCREL:
2821 other = BFD_RELOC_X86_64_GOTPCREL64;
2822 break;
2823 case BFD_RELOC_X86_64_TPOFF32:
2824 other = BFD_RELOC_X86_64_TPOFF64;
2825 break;
2826 case BFD_RELOC_X86_64_DTPOFF32:
2827 other = BFD_RELOC_X86_64_DTPOFF64;
2828 break;
2829 default:
2830 break;
3956db08 2831 }
e05278af 2832
8ce3d284 2833#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2834 if (other == BFD_RELOC_SIZE32)
2835 {
2836 if (size == 8)
2837 return BFD_RELOC_SIZE64;
2838 if (pcrel)
2839 as_bad (_("there are no pc-relative size relocations"));
2840 }
8ce3d284 2841#endif
8fd4256d 2842
e05278af 2843 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2844 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2845 sign = -1;
2846
91d6fa6a
NC		 2847 rel = bfd_reloc_type_lookup (stdoutput, other);
2848 if (!rel)
3956db08 2849 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2850 else if (size != bfd_get_reloc_size (rel))
3956db08 2851 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2852 bfd_get_reloc_size (rel),
3956db08 2853 size);
91d6fa6a 2854 else if (pcrel && !rel->pc_relative)
3956db08 2855 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2856 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2857 && !sign)
91d6fa6a 2858 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2859 && sign > 0))
3956db08
JB		 2860 as_bad (_("relocated field and relocation type differ in signedness"));
2861 else
2862 return other;
2863 return NO_RELOC;
2864 }
252b5132
RH		 2865
2866 if (pcrel)
2867 {
3e73aa7c 2868 if (!sign)
3956db08 2869 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2870 switch (size)
2871 {
2872 case 1: return BFD_RELOC_8_PCREL;
2873 case 2: return BFD_RELOC_16_PCREL;
c3320543
L		 2874 case 4: return (bnd_prefix && object_64bit
2875 ? BFD_RELOC_X86_64_PC32_BND
2876 : BFD_RELOC_32_PCREL);
d6ab8113 2877 case 8: return BFD_RELOC_64_PCREL;
252b5132 2878 }
3956db08 2879 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2880 }
2881 else
2882 {
3956db08 2883 if (sign > 0)
e5cb08ac 2884 switch (size)
3e73aa7c
JH		 2885 {
2886 case 4: return BFD_RELOC_X86_64_32S;
2887 }
2888 else
2889 switch (size)
2890 {
2891 case 1: return BFD_RELOC_8;
2892 case 2: return BFD_RELOC_16;
2893 case 4: return BFD_RELOC_32;
2894 case 8: return BFD_RELOC_64;
2895 }
3956db08
JB		 2896 as_bad (_("cannot do %s %u byte relocation"),
2897 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2898 }
2899
0cc9e1d3 2900 return NO_RELOC;
252b5132
RH		 2901}
2902
47926f60
KH		 2903/* Here we decide which fixups can be adjusted to make them relative to
2904 the beginning of the section instead of the symbol. Basically we need
2905 to make sure that the dynamic relocations are done correctly, so in
2906 some cases we force the original symbol to be used. */
2907
252b5132 2908int
e3bb37b5 2909tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2910{
6d249963 2911#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2912 if (!IS_ELF)
31312f95
AM		 2913 return 1;
2914
a161fe53
AM		 2915 /* Don't adjust pc-relative references to merge sections in 64-bit
2916 mode. */
2917 if (use_rela_relocations
2918 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2919 && fixP->fx_pcrel)
252b5132 2920 return 0;
31312f95 2921
8d01d9a9
AJ		 2922 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2923 and changed later by validate_fix. */
2924 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2925 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2926 return 0;
2927
8fd4256d
L		 2928 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2929 for size relocations. */
2930 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2931 || fixP->fx_r_type == BFD_RELOC_SIZE64
2932 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2933 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2934 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2935 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2936 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2937 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2938 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2939 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2940 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2941 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2942 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2943 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2944 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2945 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2946 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2947 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2948 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2949 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2950 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2951 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2952 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2953 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2954 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2955 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2956 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2957 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2958 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2959 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2960 return 0;
31312f95 2961#endif
252b5132
RH		 2962 return 1;
2963}
252b5132 2964
b4cac588 2965static int
e3bb37b5 2966intel_float_operand (const char *mnemonic)
252b5132 2967{
9306ca4a
JB		 2968 /* Note that the value returned is meaningful only for opcodes with (memory)
2969 operands, hence the code here is free to improperly handle opcodes that
2970 have no operands (for better performance and smaller code). */
2971
2972 if (mnemonic[0] != 'f')
2973 return 0; /* non-math */
2974
2975 switch (mnemonic[1])
2976 {
2977 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2978 the fs segment override prefix not currently handled because no
2979 call path can make opcodes without operands get here */
2980 case 'i':
2981 return 2 /* integer op */;
2982 case 'l':
2983 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2984 return 3; /* fldcw/fldenv */
2985 break;
2986 case 'n':
2987 if (mnemonic[2] != 'o' /* fnop */)
2988 return 3; /* non-waiting control op */
2989 break;
2990 case 'r':
2991 if (mnemonic[2] == 's')
2992 return 3; /* frstor/frstpm */
2993 break;
2994 case 's':
2995 if (mnemonic[2] == 'a')
2996 return 3; /* fsave */
2997 if (mnemonic[2] == 't')
2998 {
2999 switch (mnemonic[3])
3000 {
3001 case 'c': /* fstcw */
3002 case 'd': /* fstdw */
3003 case 'e': /* fstenv */
3004 case 's': /* fsts[gw] */
3005 return 3;
3006 }
3007 }
3008 break;
3009 case 'x':
3010 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3011 return 0; /* fxsave/fxrstor are not really math ops */
3012 break;
3013 }
252b5132 3014
9306ca4a 3015 return 1;
252b5132
RH		 3016}
3017
c0f3af97
L		 3018/* Build the VEX prefix. */
3019
3020static void
d3ce72d0 3021build_vex_prefix (const insn_template *t)
c0f3af97
L		 3022{
3023 unsigned int register_specifier;
3024 unsigned int implied_prefix;
3025 unsigned int vector_length;
3026
3027 /* Check register specifier. */
3028 if (i.vex.register_specifier)
43234a1e
L		 3029 {
3030 register_specifier =
3031 ~register_number (i.vex.register_specifier) & 0xf;
3032 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3033 }
c0f3af97
L		 3034 else
3035 register_specifier = 0xf;
3036
fa99fab2
L		 3037 /* Use 2-byte VEX prefix by swappping destination and source
3038 operand. */
3039 if (!i.swap_operand
3040 && i.operands == i.reg_operands
7f399153 3041 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3042 && i.tm.opcode_modifier.s
3043 && i.rex == REX_B)
3044 {
3045 unsigned int xchg = i.operands - 1;
3046 union i386_op temp_op;
3047 i386_operand_type temp_type;
3048
3049 temp_type = i.types[xchg];
3050 i.types[xchg] = i.types[0];
3051 i.types[0] = temp_type;
3052 temp_op = i.op[xchg];
3053 i.op[xchg] = i.op[0];
3054 i.op[0] = temp_op;
3055
9c2799c2 3056 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3057
3058 i.rex = REX_R;
3059 xchg = i.rm.regmem;
3060 i.rm.regmem = i.rm.reg;
3061 i.rm.reg = xchg;
3062
3063 /* Use the next insn. */
3064 i.tm = t[1];
3065 }
3066
539f890d
L		 3067 if (i.tm.opcode_modifier.vex == VEXScalar)
3068 vector_length = avxscalar;
3069 else
3070 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3071
3072 switch ((i.tm.base_opcode >> 8) & 0xff)
3073 {
3074 case 0:
3075 implied_prefix = 0;
3076 break;
3077 case DATA_PREFIX_OPCODE:
3078 implied_prefix = 1;
3079 break;
3080 case REPE_PREFIX_OPCODE:
3081 implied_prefix = 2;
3082 break;
3083 case REPNE_PREFIX_OPCODE:
3084 implied_prefix = 3;
3085 break;
3086 default:
3087 abort ();
3088 }
3089
3090 /* Use 2-byte VEX prefix if possible. */
7f399153 3091 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3092 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3093 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3094 {
3095 /* 2-byte VEX prefix. */
3096 unsigned int r;
3097
3098 i.vex.length = 2;
3099 i.vex.bytes[0] = 0xc5;
3100
3101 /* Check the REX.R bit. */
3102 r = (i.rex & REX_R) ? 0 : 1;
3103 i.vex.bytes[1] = (r << 7
3104 | register_specifier << 3
3105 | vector_length << 2
3106 | implied_prefix);
3107 }
3108 else
3109 {
3110 /* 3-byte VEX prefix. */
3111 unsigned int m, w;
3112
f88c9eb0 3113 i.vex.length = 3;
f88c9eb0 3114
7f399153 3115 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3116 {
7f399153
L		 3117 case VEX0F:
3118 m = 0x1;
80de6e00 3119 i.vex.bytes[0] = 0xc4;
7f399153
L		 3120 break;
3121 case VEX0F38:
3122 m = 0x2;
80de6e00 3123 i.vex.bytes[0] = 0xc4;
7f399153
L		 3124 break;
3125 case VEX0F3A:
3126 m = 0x3;
80de6e00 3127 i.vex.bytes[0] = 0xc4;
7f399153
L		 3128 break;
3129 case XOP08:
5dd85c99
SP		 3130 m = 0x8;
3131 i.vex.bytes[0] = 0x8f;
7f399153
L		 3132 break;
3133 case XOP09:
f88c9eb0
SP		 3134 m = 0x9;
3135 i.vex.bytes[0] = 0x8f;
7f399153
L		 3136 break;
3137 case XOP0A:
f88c9eb0
SP		 3138 m = 0xa;
3139 i.vex.bytes[0] = 0x8f;
7f399153
L		 3140 break;
3141 default:
3142 abort ();
f88c9eb0 3143 }
c0f3af97 3144
c0f3af97
L		 3145 /* The high 3 bits of the second VEX byte are 1's compliment
3146 of RXB bits from REX. */
3147 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3148
3149 /* Check the REX.W bit. */
3150 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 3151 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 3152 {
3153 if (w)
3154 abort ();
3155
1ef99a7b 3156 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 3157 w = 1;
3158 }
3159
3160 i.vex.bytes[2] = (w << 7
3161 | register_specifier << 3
3162 | vector_length << 2
3163 | implied_prefix);
3164 }
3165}
3166
43234a1e
L		 3167/* Build the EVEX prefix. */
3168
3169static void
3170build_evex_prefix (void)
3171{
3172 unsigned int register_specifier;
3173 unsigned int implied_prefix;
3174 unsigned int m, w;
3175 rex_byte vrex_used = 0;
3176
3177 /* Check register specifier. */
3178 if (i.vex.register_specifier)
3179 {
3180 gas_assert ((i.vrex & REX_X) == 0);
3181
3182 register_specifier = i.vex.register_specifier->reg_num;
3183 if ((i.vex.register_specifier->reg_flags & RegRex))
3184 register_specifier += 8;
3185 /* The upper 16 registers are encoded in the fourth byte of the
3186 EVEX prefix. */
3187 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3188 i.vex.bytes[3] = 0x8;
3189 register_specifier = ~register_specifier & 0xf;
3190 }
3191 else
3192 {
3193 register_specifier = 0xf;
3194
3195 /* Encode upper 16 vector index register in the fourth byte of
3196 the EVEX prefix. */
3197 if (!(i.vrex & REX_X))
3198 i.vex.bytes[3] = 0x8;
3199 else
3200 vrex_used |= REX_X;
3201 }
3202
3203 switch ((i.tm.base_opcode >> 8) & 0xff)
3204 {
3205 case 0:
3206 implied_prefix = 0;
3207 break;
3208 case DATA_PREFIX_OPCODE:
3209 implied_prefix = 1;
3210 break;
3211 case REPE_PREFIX_OPCODE:
3212 implied_prefix = 2;
3213 break;
3214 case REPNE_PREFIX_OPCODE:
3215 implied_prefix = 3;
3216 break;
3217 default:
3218 abort ();
3219 }
3220
3221 /* 4 byte EVEX prefix. */
3222 i.vex.length = 4;
3223 i.vex.bytes[0] = 0x62;
3224
3225 /* mmmm bits. */
3226 switch (i.tm.opcode_modifier.vexopcode)
3227 {
3228 case VEX0F:
3229 m = 1;
3230 break;
3231 case VEX0F38:
3232 m = 2;
3233 break;
3234 case VEX0F3A:
3235 m = 3;
3236 break;
3237 default:
3238 abort ();
3239 break;
3240 }
3241
3242 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3243 bits from REX. */
3244 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3245
3246 /* The fifth bit of the second EVEX byte is 1's compliment of the
3247 REX_R bit in VREX. */
3248 if (!(i.vrex & REX_R))
3249 i.vex.bytes[1] |= 0x10;
3250 else
3251 vrex_used |= REX_R;
3252
3253 if ((i.reg_operands + i.imm_operands) == i.operands)
3254 {
3255 /* When all operands are registers, the REX_X bit in REX is not
3256 used. We reuse it to encode the upper 16 registers, which is
3257 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3258 as 1's compliment. */
3259 if ((i.vrex & REX_B))
3260 {
3261 vrex_used |= REX_B;
3262 i.vex.bytes[1] &= ~0x40;
3263 }
3264 }
3265
3266 /* EVEX instructions shouldn't need the REX prefix. */
3267 i.vrex &= ~vrex_used;
3268 gas_assert (i.vrex == 0);
3269
3270 /* Check the REX.W bit. */
3271 w = (i.rex & REX_W) ? 1 : 0;
3272 if (i.tm.opcode_modifier.vexw)
3273 {
3274 if (i.tm.opcode_modifier.vexw == VEXW1)
3275 w = 1;
3276 }
3277 /* If w is not set it means we are dealing with WIG instruction. */
3278 else if (!w)
3279 {
3280 if (evexwig == evexw1)
3281 w = 1;
3282 }
3283
3284 /* Encode the U bit. */
3285 implied_prefix |= 0x4;
3286
3287 /* The third byte of the EVEX prefix. */
3288 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3289
3290 /* The fourth byte of the EVEX prefix. */
3291 /* The zeroing-masking bit. */
3292 if (i.mask && i.mask->zeroing)
3293 i.vex.bytes[3] |= 0x80;
3294
3295 /* Don't always set the broadcast bit if there is no RC. */
3296 if (!i.rounding)
3297 {
3298 /* Encode the vector length. */
3299 unsigned int vec_length;
3300
3301 switch (i.tm.opcode_modifier.evex)
3302 {
3303 case EVEXLIG: /* LL' is ignored */
3304 vec_length = evexlig << 5;
3305 break;
3306 case EVEX128:
3307 vec_length = 0 << 5;
3308 break;
3309 case EVEX256:
3310 vec_length = 1 << 5;
3311 break;
3312 case EVEX512:
3313 vec_length = 2 << 5;
3314 break;
3315 default:
3316 abort ();
3317 break;
3318 }
3319 i.vex.bytes[3] |= vec_length;
3320 /* Encode the broadcast bit. */
3321 if (i.broadcast)
3322 i.vex.bytes[3] |= 0x10;
3323 }
3324 else
3325 {
3326 if (i.rounding->type != saeonly)
3327 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3328 else
3329 i.vex.bytes[3] |= 0x10;
3330 }
3331
3332 if (i.mask && i.mask->mask)
3333 i.vex.bytes[3] |= i.mask->mask->reg_num;
3334}
3335
65da13b5
L		 3336static void
3337process_immext (void)
3338{
3339 expressionS *exp;
3340
4c692bc7
JB		 3341 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3342 && i.operands > 0)
65da13b5 3343 {
4c692bc7
JB		 3344 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3345 with an opcode suffix which is coded in the same place as an
3346 8-bit immediate field would be.
3347 Here we check those operands and remove them afterwards. */
65da13b5
L		 3348 unsigned int x;
3349
3350 for (x = 0; x < i.operands; x++)
4c692bc7 3351 if (register_number (i.op[x].regs) != x)
65da13b5 3352 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3353 register_prefix, i.op[x].regs->reg_name, x + 1,
3354 i.tm.name);
3355
3356 i.operands = 0;
65da13b5
L		 3357 }
3358
c0f3af97 3359 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3360 which is coded in the same place as an 8-bit immediate field
3361 would be. Here we fake an 8-bit immediate operand from the
3362 opcode suffix stored in tm.extension_opcode.
3363
c1e679ec 3364 AVX instructions also use this encoding, for some of
c0f3af97 3365 3 argument instructions. */
65da13b5 3366
43234a1e 3367 gas_assert (i.imm_operands <= 1
7ab9ffdd 3368 && (i.operands <= 2
43234a1e
L		 3369 || ((i.tm.opcode_modifier.vex
3370 || i.tm.opcode_modifier.evex)
7ab9ffdd 3371 && i.operands <= 4)));
65da13b5
L		 3372
3373 exp = &im_expressions[i.imm_operands++];
3374 i.op[i.operands].imms = exp;
3375 i.types[i.operands] = imm8;
3376 i.operands++;
3377 exp->X_op = O_constant;
3378 exp->X_add_number = i.tm.extension_opcode;
3379 i.tm.extension_opcode = None;
3380}
3381
42164a71
L		 3382
3383static int
3384check_hle (void)
3385{
3386 switch (i.tm.opcode_modifier.hleprefixok)
3387 {
3388 default:
3389 abort ();
82c2def5 3390 case HLEPrefixNone:
165de32a
L		 3391 as_bad (_("invalid instruction `%s' after `%s'"),
3392 i.tm.name, i.hle_prefix);
42164a71 3393 return 0;
82c2def5 3394 case HLEPrefixLock:
42164a71
L		 3395 if (i.prefix[LOCK_PREFIX])
3396 return 1;
165de32a 3397 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3398 return 0;
82c2def5 3399 case HLEPrefixAny:
42164a71 3400 return 1;
82c2def5 3401 case HLEPrefixRelease:
42164a71
L		 3402 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3403 {
3404 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3405 i.tm.name);
3406 return 0;
3407 }
3408 if (i.mem_operands == 0
3409 || !operand_type_check (i.types[i.operands - 1], anymem))
3410 {
3411 as_bad (_("memory destination needed for instruction `%s'"
3412 " after `xrelease'"), i.tm.name);
3413 return 0;
3414 }
3415 return 1;
3416 }
3417}
3418
252b5132
RH		 3419/* This is the guts of the machine-dependent assembler. LINE points to a
3420 machine dependent instruction. This function is supposed to emit
3421 the frags/bytes it assembles to. */
3422
3423void
65da13b5 3424md_assemble (char *line)
252b5132 3425{
40fb9820 3426 unsigned int j;
252b5132 3427 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3428 const insn_template *t;
252b5132 3429
47926f60 3430 /* Initialize globals. */
252b5132
RH		 3431 memset (&i, '\0', sizeof (i));
3432 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3433 i.reloc[j] = NO_RELOC;
252b5132
RH		 3434 memset (disp_expressions, '\0', sizeof (disp_expressions));
3435 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3436 save_stack_p = save_stack;
252b5132
RH		 3437
3438 /* First parse an instruction mnemonic & call i386_operand for the operands.
3439 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3440 start of a (possibly prefixed) mnemonic. */
252b5132 3441
29b0f896
AM		 3442 line = parse_insn (line, mnemonic);
3443 if (line == NULL)
3444 return;
252b5132 3445
29b0f896 3446 line = parse_operands (line, mnemonic);
ee86248c 3447 this_operand = -1;
29b0f896
AM		 3448 if (line == NULL)
3449 return;
252b5132 3450
29b0f896
AM		 3451 /* Now we've parsed the mnemonic into a set of templates, and have the
3452 operands at hand. */
3453
3454 /* All intel opcodes have reversed operands except for "bound" and
3455 "enter". We also don't reverse intersegment "jmp" and "call"
3456 instructions with 2 immediate operands so that the immediate segment
050dfa73 3457 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3458 if (intel_syntax
3459 && i.operands > 1
29b0f896 3460 && (strcmp (mnemonic, "bound") != 0)
30123838 3461 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3462 && !(operand_type_check (i.types[0], imm)
3463 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3464 swap_operands ();
3465
ec56d5c0
JB		 3466 /* The order of the immediates should be reversed
3467 for 2 immediates extrq and insertq instructions */
3468 if (i.imm_operands == 2
3469 && (strcmp (mnemonic, "extrq") == 0
3470 || strcmp (mnemonic, "insertq") == 0))
3471 swap_2_operands (0, 1);
3472
29b0f896
AM		 3473 if (i.imm_operands)
3474 optimize_imm ();
3475
b300c311
L		 3476 /* Don't optimize displacement for movabs since it only takes 64bit
3477 displacement. */
3478 if (i.disp_operands
a501d77e 3479 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3480 && (flag_code != CODE_64BIT
3481 || strcmp (mnemonic, "movabs") != 0))
3482 optimize_disp ();
29b0f896
AM		 3483
3484 /* Next, we find a template that matches the given insn,
3485 making sure the overlap of the given operands types is consistent
3486 with the template operand types. */
252b5132 3487
fa99fab2 3488 if (!(t = match_template ()))
29b0f896 3489 return;
252b5132 3490
7bab8ab5 3491 if (sse_check != check_none
81f8a913 3492 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3493 && (i.tm.cpu_flags.bitfield.cpusse
3494 || i.tm.cpu_flags.bitfield.cpusse2
3495 || i.tm.cpu_flags.bitfield.cpusse3
3496 || i.tm.cpu_flags.bitfield.cpussse3
3497 || i.tm.cpu_flags.bitfield.cpusse4_1
3498 || i.tm.cpu_flags.bitfield.cpusse4_2))
3499 {
7bab8ab5 3500 (sse_check == check_warning
daf50ae7
L		 3501 ? as_warn
3502 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3503 }
3504
321fd21e
L		 3505 /* Zap movzx and movsx suffix. The suffix has been set from
3506 "word ptr" or "byte ptr" on the source operand in Intel syntax
3507 or extracted from mnemonic in AT&T syntax. But we'll use
3508 the destination register to choose the suffix for encoding. */
3509 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3510 {
321fd21e
L		 3511 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3512 there is no suffix, the default will be byte extension. */
3513 if (i.reg_operands != 2
3514 && !i.suffix
7ab9ffdd 3515 && intel_syntax)
321fd21e
L		 3516 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3517
3518 i.suffix = 0;
cd61ebfe 3519 }
24eab124 3520
40fb9820 3521 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3522 if (!add_prefix (FWAIT_OPCODE))
3523 return;
252b5132 3524
d5de92cf
L		 3525 /* Check if REP prefix is OK. */
3526 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3527 {
3528 as_bad (_("invalid instruction `%s' after `%s'"),
3529 i.tm.name, i.rep_prefix);
3530 return;
3531 }
3532
c1ba0266
L		 3533 /* Check for lock without a lockable instruction. Destination operand
3534 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3535 if (i.prefix[LOCK_PREFIX]
3536 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3537 || i.mem_operands == 0
3538 || (i.tm.base_opcode != 0x86
3539 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3540 {
3541 as_bad (_("expecting lockable instruction after `lock'"));
3542 return;
3543 }
3544
42164a71 3545 /* Check if HLE prefix is OK. */
165de32a 3546 if (i.hle_prefix && !check_hle ())
42164a71
L		 3547 return;
3548
7e8b059b
L		 3549 /* Check BND prefix. */
3550 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3551 as_bad (_("expecting valid branch instruction after `bnd'"));
3552
3553 if (i.tm.cpu_flags.bitfield.cpumpx
3554 && flag_code == CODE_64BIT
3555 && i.prefix[ADDR_PREFIX])
3556 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3557
3558 /* Insert BND prefix. */
3559 if (add_bnd_prefix
3560 && i.tm.opcode_modifier.bndprefixok
3561 && !i.prefix[BND_PREFIX])
3562 add_prefix (BND_PREFIX_OPCODE);
3563
29b0f896 3564 /* Check string instruction segment overrides. */
40fb9820 3565 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3566 {
3567 if (!check_string ())
5dd0794d 3568 return;
fc0763e6 3569 i.disp_operands = 0;
29b0f896 3570 }
5dd0794d 3571
29b0f896
AM		 3572 if (!process_suffix ())
3573 return;
e413e4e9 3574
bc0844ae
L		 3575 /* Update operand types. */
3576 for (j = 0; j < i.operands; j++)
3577 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3578
29b0f896
AM		 3579 /* Make still unresolved immediate matches conform to size of immediate
3580 given in i.suffix. */
3581 if (!finalize_imm ())
3582 return;
252b5132 3583
40fb9820 3584 if (i.types[0].bitfield.imm1)
29b0f896 3585 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3586
9afe6eb8
L		 3587 /* We only need to check those implicit registers for instructions
3588 with 3 operands or less. */
3589 if (i.operands <= 3)
3590 for (j = 0; j < i.operands; j++)
3591 if (i.types[j].bitfield.inoutportreg
3592 || i.types[j].bitfield.shiftcount
3593 || i.types[j].bitfield.acc
3594 || i.types[j].bitfield.floatacc)
3595 i.reg_operands--;
40fb9820 3596
c0f3af97
L		 3597 /* ImmExt should be processed after SSE2AVX. */
3598 if (!i.tm.opcode_modifier.sse2avx
3599 && i.tm.opcode_modifier.immext)
65da13b5 3600 process_immext ();
252b5132 3601
29b0f896
AM		 3602 /* For insns with operands there are more diddles to do to the opcode. */
3603 if (i.operands)
3604 {
3605 if (!process_operands ())
3606 return;
3607 }
40fb9820 3608 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3609 {
3610 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3611 as_warn (_("translating to `%sp'"), i.tm.name);
3612 }
252b5132 3613
c0f3af97 3614 if (i.tm.opcode_modifier.vex)
fa99fab2 3615 build_vex_prefix (t);
c0f3af97 3616
43234a1e
L		 3617 if (i.tm.opcode_modifier.evex)
3618 build_evex_prefix ();
3619
5dd85c99
SP		 3620 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3621 instructions may define INT_OPCODE as well, so avoid this corner
3622 case for those instructions that use MODRM. */
3623 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3624 && !i.tm.opcode_modifier.modrm
3625 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3626 {
3627 i.tm.base_opcode = INT3_OPCODE;
3628 i.imm_operands = 0;
3629 }
252b5132 3630
40fb9820
L		 3631 if ((i.tm.opcode_modifier.jump
3632 || i.tm.opcode_modifier.jumpbyte
3633 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3634 && i.op[0].disps->X_op == O_constant)
3635 {
3636 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3637 the absolute address given by the constant. Since ix86 jumps and
3638 calls are pc relative, we need to generate a reloc. */
3639 i.op[0].disps->X_add_symbol = &abs_symbol;
3640 i.op[0].disps->X_op = O_symbol;
3641 }
252b5132 3642
40fb9820 3643 if (i.tm.opcode_modifier.rex64)
161a04f6 3644 i.rex |= REX_W;
252b5132 3645
29b0f896
AM		 3646 /* For 8 bit registers we need an empty rex prefix. Also if the
3647 instruction already has a prefix, we need to convert old
3648 registers to new ones. */
773f551c 3649
40fb9820 3650 if ((i.types[0].bitfield.reg8
29b0f896 3651 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3652 || (i.types[1].bitfield.reg8
29b0f896 3653 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3654 || ((i.types[0].bitfield.reg8
3655 || i.types[1].bitfield.reg8)
29b0f896
AM		 3656 && i.rex != 0))
3657 {
3658 int x;
726c5dcd 3659
29b0f896
AM		 3660 i.rex |= REX_OPCODE;
3661 for (x = 0; x < 2; x++)
3662 {
3663 /* Look for 8 bit operand that uses old registers. */
40fb9820 3664 if (i.types[x].bitfield.reg8
29b0f896 3665 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3666 {
29b0f896
AM		 3667 /* In case it is "hi" register, give up. */
3668 if (i.op[x].regs->reg_num > 3)
a540244d 3669 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3670 "instruction requiring REX prefix."),
a540244d 3671 register_prefix, i.op[x].regs->reg_name);
773f551c 3672
29b0f896
AM		 3673 /* Otherwise it is equivalent to the extended register.
3674 Since the encoding doesn't change this is merely
3675 cosmetic cleanup for debug output. */
3676
3677 i.op[x].regs = i.op[x].regs + 8;
773f551c 3678 }
29b0f896
AM		 3679 }
3680 }
773f551c 3681
7ab9ffdd 3682 if (i.rex != 0)
29b0f896
AM		 3683 add_prefix (REX_OPCODE | i.rex);
3684
3685 /* We are ready to output the insn. */
3686 output_insn ();
3687}
3688
3689static char *
e3bb37b5 3690parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3691{
3692 char *l = line;
3693 char *token_start = l;
3694 char *mnem_p;
5c6af06e 3695 int supported;
d3ce72d0 3696 const insn_template *t;
b6169b20 3697 char *dot_p = NULL;
29b0f896 3698
29b0f896
AM		 3699 while (1)
3700 {
3701 mnem_p = mnemonic;
3702 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3703 {
b6169b20
L		 3704 if (*mnem_p == '.')
3705 dot_p = mnem_p;
29b0f896
AM		 3706 mnem_p++;
3707 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3708 {
29b0f896
AM		 3709 as_bad (_("no such instruction: `%s'"), token_start);
3710 return NULL;
3711 }
3712 l++;
3713 }
3714 if (!is_space_char (*l)
3715 && *l != END_OF_INSN
e44823cf
JB		 3716 && (intel_syntax
3717 || (*l != PREFIX_SEPARATOR
3718 && *l != ',')))
29b0f896
AM		 3719 {
3720 as_bad (_("invalid character %s in mnemonic"),
3721 output_invalid (*l));
3722 return NULL;
3723 }
3724 if (token_start == l)
3725 {
e44823cf 3726 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3727 as_bad (_("expecting prefix; got nothing"));
3728 else
3729 as_bad (_("expecting mnemonic; got nothing"));
3730 return NULL;
3731 }
45288df1 3732
29b0f896 3733 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3734 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3735
29b0f896
AM		 3736 if (*l != END_OF_INSN
3737 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3738 && current_templates
40fb9820 3739 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3740 {
c6fb90c8 3741 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3742 {
3743 as_bad ((flag_code != CODE_64BIT
3744 ? _("`%s' is only supported in 64-bit mode")
3745 : _("`%s' is not supported in 64-bit mode")),
3746 current_templates->start->name);
3747 return NULL;
3748 }
29b0f896
AM		 3749 /* If we are in 16-bit mode, do not allow addr16 or data16.
3750 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3751 if ((current_templates->start->opcode_modifier.size16
3752 || current_templates->start->opcode_modifier.size32)
29b0f896 3753 && flag_code != CODE_64BIT
40fb9820 3754 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3755 ^ (flag_code == CODE_16BIT)))
3756 {
3757 as_bad (_("redundant %s prefix"),
3758 current_templates->start->name);
3759 return NULL;
45288df1 3760 }
29b0f896
AM		 3761 /* Add prefix, checking for repeated prefixes. */
3762 switch (add_prefix (current_templates->start->base_opcode))
3763 {
c32fa91d 3764 case PREFIX_EXIST:
29b0f896 3765 return NULL;
c32fa91d 3766 case PREFIX_REP:
42164a71 3767 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3768 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3769 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3770 i.bnd_prefix = current_templates->start->name;
42164a71 3771 else
d5de92cf 3772 i.rep_prefix = current_templates->start->name;
29b0f896 3773 break;
c32fa91d
L		 3774 default:
3775 break;
29b0f896
AM		 3776 }
3777 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3778 token_start = ++l;
3779 }
3780 else
3781 break;
3782 }
45288df1 3783
30a55f88 3784 if (!current_templates)
b6169b20 3785 {
f8a5c266
L		 3786 /* Check if we should swap operand or force 32bit displacement in
3787 encoding. */
30a55f88
L		 3788 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3789 i.swap_operand = 1;
8d63c93e 3790 else if (mnem_p - 3 == dot_p
a501d77e
L		 3791 && dot_p[1] == 'd'
3792 && dot_p[2] == '8')
3793 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3794 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3795 && dot_p[1] == 'd'
3796 && dot_p[2] == '3'
3797 && dot_p[3] == '2')
a501d77e 3798 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3799 else
3800 goto check_suffix;
3801 mnem_p = dot_p;
3802 *dot_p = '\0';
d3ce72d0 3803 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3804 }
3805
29b0f896
AM		 3806 if (!current_templates)
3807 {
b6169b20 3808check_suffix:
29b0f896
AM		 3809 /* See if we can get a match by trimming off a suffix. */
3810 switch (mnem_p[-1])
3811 {
3812 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3813 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3814 i.suffix = SHORT_MNEM_SUFFIX;
3815 else
29b0f896
AM		 3816 case BYTE_MNEM_SUFFIX:
3817 case QWORD_MNEM_SUFFIX:
3818 i.suffix = mnem_p[-1];
3819 mnem_p[-1] = '\0';
d3ce72d0
NC		 3820 current_templates = (const templates *) hash_find (op_hash,
3821 mnemonic);
29b0f896
AM		 3822 break;
3823 case SHORT_MNEM_SUFFIX:
3824 case LONG_MNEM_SUFFIX:
3825 if (!intel_syntax)
3826 {
3827 i.suffix = mnem_p[-1];
3828 mnem_p[-1] = '\0';
d3ce72d0
NC		 3829 current_templates = (const templates *) hash_find (op_hash,
3830 mnemonic);
29b0f896
AM		 3831 }
3832 break;
252b5132 3833
29b0f896
AM		 3834 /* Intel Syntax. */
3835 case 'd':
3836 if (intel_syntax)
3837 {
9306ca4a 3838 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3839 i.suffix = SHORT_MNEM_SUFFIX;
3840 else
3841 i.suffix = LONG_MNEM_SUFFIX;
3842 mnem_p[-1] = '\0';
d3ce72d0
NC		 3843 current_templates = (const templates *) hash_find (op_hash,
3844 mnemonic);
29b0f896
AM		 3845 }
3846 break;
3847 }
3848 if (!current_templates)
3849 {
3850 as_bad (_("no such instruction: `%s'"), token_start);
3851 return NULL;
3852 }
3853 }
252b5132 3854
40fb9820
L		 3855 if (current_templates->start->opcode_modifier.jump
3856 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3857 {
3858 /* Check for a branch hint. We allow ",pt" and ",pn" for
3859 predict taken and predict not taken respectively.
3860 I'm not sure that branch hints actually do anything on loop
3861 and jcxz insns (JumpByte) for current Pentium4 chips. They
3862 may work in the future and it doesn't hurt to accept them
3863 now. */
3864 if (l[0] == ',' && l[1] == 'p')
3865 {
3866 if (l[2] == 't')
3867 {
3868 if (!add_prefix (DS_PREFIX_OPCODE))
3869 return NULL;
3870 l += 3;
3871 }
3872 else if (l[2] == 'n')
3873 {
3874 if (!add_prefix (CS_PREFIX_OPCODE))
3875 return NULL;
3876 l += 3;
3877 }
3878 }
3879 }
3880 /* Any other comma loses. */
3881 if (*l == ',')
3882 {
3883 as_bad (_("invalid character %s in mnemonic"),
3884 output_invalid (*l));
3885 return NULL;
3886 }
252b5132 3887
29b0f896 3888 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3889 supported = 0;
3890 for (t = current_templates->start; t < current_templates->end; ++t)
3891 {
c0f3af97
L		 3892 supported |= cpu_flags_match (t);
3893 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3894 goto skip;
5c6af06e 3895 }
3629bb00 3896
c0f3af97 3897 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3898 {
3899 as_bad (flag_code == CODE_64BIT
3900 ? _("`%s' is not supported in 64-bit mode")
3901 : _("`%s' is only supported in 64-bit mode"),
3902 current_templates->start->name);
3903 return NULL;
3904 }
c0f3af97 3905 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3906 {
3629bb00 3907 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3908 current_templates->start->name,
41aacd83 3909 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3910 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3911 return NULL;
29b0f896 3912 }
3629bb00
L		 3913
3914skip:
3915 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3916 && (flag_code != CODE_16BIT))
29b0f896
AM		 3917 {
3918 as_warn (_("use .code16 to ensure correct addressing mode"));
3919 }
252b5132 3920
29b0f896
AM		 3921 return l;
3922}
252b5132 3923
29b0f896 3924static char *
e3bb37b5 3925parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3926{
3927 char *token_start;
3138f287 3928
29b0f896
AM		 3929 /* 1 if operand is pending after ','. */
3930 unsigned int expecting_operand = 0;
252b5132 3931
29b0f896
AM		 3932 /* Non-zero if operand parens not balanced. */
3933 unsigned int paren_not_balanced;
3934
3935 while (*l != END_OF_INSN)
3936 {
3937 /* Skip optional white space before operand. */
3938 if (is_space_char (*l))
3939 ++l;
3940 if (!is_operand_char (*l) && *l != END_OF_INSN)
3941 {
3942 as_bad (_("invalid character %s before operand %d"),
3943 output_invalid (*l),
3944 i.operands + 1);
3945 return NULL;
3946 }
3947 token_start = l; /* after white space */
3948 paren_not_balanced = 0;
3949 while (paren_not_balanced || *l != ',')
3950 {
3951 if (*l == END_OF_INSN)
3952 {
3953 if (paren_not_balanced)
3954 {
3955 if (!intel_syntax)
3956 as_bad (_("unbalanced parenthesis in operand %d."),
3957 i.operands + 1);
3958 else
3959 as_bad (_("unbalanced brackets in operand %d."),
3960 i.operands + 1);
3961 return NULL;
3962 }
3963 else
3964 break; /* we are done */
3965 }
3966 else if (!is_operand_char (*l) && !is_space_char (*l))
3967 {
3968 as_bad (_("invalid character %s in operand %d"),
3969 output_invalid (*l),
3970 i.operands + 1);
3971 return NULL;
3972 }
3973 if (!intel_syntax)
3974 {
3975 if (*l == '(')
3976 ++paren_not_balanced;
3977 if (*l == ')')
3978 --paren_not_balanced;
3979 }
3980 else
3981 {
3982 if (*l == '[')
3983 ++paren_not_balanced;
3984 if (*l == ']')
3985 --paren_not_balanced;
3986 }
3987 l++;
3988 }
3989 if (l != token_start)
3990 { /* Yes, we've read in another operand. */
3991 unsigned int operand_ok;
3992 this_operand = i.operands++;
7d5e4556 3993 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3994 if (i.operands > MAX_OPERANDS)
3995 {
3996 as_bad (_("spurious operands; (%d operands/instruction max)"),
3997 MAX_OPERANDS);
3998 return NULL;
3999 }
4000 /* Now parse operand adding info to 'i' as we go along. */
4001 END_STRING_AND_SAVE (l);
4002
4003 if (intel_syntax)
4004 operand_ok =
4005 i386_intel_operand (token_start,
4006 intel_float_operand (mnemonic));
4007 else
a7619375 4008 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4009
4010 RESTORE_END_STRING (l);
4011 if (!operand_ok)
4012 return NULL;
4013 }
4014 else
4015 {
4016 if (expecting_operand)
4017 {
4018 expecting_operand_after_comma:
4019 as_bad (_("expecting operand after ','; got nothing"));
4020 return NULL;
4021 }
4022 if (*l == ',')
4023 {
4024 as_bad (_("expecting operand before ','; got nothing"));
4025 return NULL;
4026 }
4027 }
7f3f1ea2 4028
29b0f896
AM		 4029 /* Now *l must be either ',' or END_OF_INSN. */
4030 if (*l == ',')
4031 {
4032 if (*++l == END_OF_INSN)
4033 {
4034 /* Just skip it, if it's \n complain. */
4035 goto expecting_operand_after_comma;
4036 }
4037 expecting_operand = 1;
4038 }
4039 }
4040 return l;
4041}
7f3f1ea2 4042
050dfa73 4043static void
4d456e3d 4044swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4045{
4046 union i386_op temp_op;
40fb9820 4047 i386_operand_type temp_type;
050dfa73 4048 enum bfd_reloc_code_real temp_reloc;
4eed87de 4049
050dfa73
MM		 4050 temp_type = i.types[xchg2];
4051 i.types[xchg2] = i.types[xchg1];
4052 i.types[xchg1] = temp_type;
4053 temp_op = i.op[xchg2];
4054 i.op[xchg2] = i.op[xchg1];
4055 i.op[xchg1] = temp_op;
4056 temp_reloc = i.reloc[xchg2];
4057 i.reloc[xchg2] = i.reloc[xchg1];
4058 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4059
4060 if (i.mask)
4061 {
4062 if (i.mask->operand == xchg1)
4063 i.mask->operand = xchg2;
4064 else if (i.mask->operand == xchg2)
4065 i.mask->operand = xchg1;
4066 }
4067 if (i.broadcast)
4068 {
4069 if (i.broadcast->operand == xchg1)
4070 i.broadcast->operand = xchg2;
4071 else if (i.broadcast->operand == xchg2)
4072 i.broadcast->operand = xchg1;
4073 }
4074 if (i.rounding)
4075 {
4076 if (i.rounding->operand == xchg1)
4077 i.rounding->operand = xchg2;
4078 else if (i.rounding->operand == xchg2)
4079 i.rounding->operand = xchg1;
4080 }
050dfa73
MM		 4081}
4082
29b0f896 4083static void
e3bb37b5 4084swap_operands (void)
29b0f896 4085{
b7c61d9a 4086 switch (i.operands)
050dfa73 4087 {
c0f3af97 4088 case 5:
b7c61d9a 4089 case 4:
4d456e3d 4090 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4091 case 3:
4092 case 2:
4d456e3d 4093 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4094 break;
4095 default:
4096 abort ();
29b0f896 4097 }
29b0f896
AM		 4098
4099 if (i.mem_operands == 2)
4100 {
4101 const seg_entry *temp_seg;
4102 temp_seg = i.seg[0];
4103 i.seg[0] = i.seg[1];
4104 i.seg[1] = temp_seg;
4105 }
4106}
252b5132 4107
29b0f896
AM		 4108/* Try to ensure constant immediates are represented in the smallest
4109 opcode possible. */
4110static void
e3bb37b5 4111optimize_imm (void)
29b0f896
AM		 4112{
4113 char guess_suffix = 0;
4114 int op;
252b5132 4115
29b0f896
AM		 4116 if (i.suffix)
4117 guess_suffix = i.suffix;
4118 else if (i.reg_operands)
4119 {
4120 /* Figure out a suffix from the last register operand specified.
4121 We can't do this properly yet, ie. excluding InOutPortReg,
4122 but the following works for instructions with immediates.
4123 In any case, we can't set i.suffix yet. */
4124 for (op = i.operands; --op >= 0;)
40fb9820 4125 if (i.types[op].bitfield.reg8)
7ab9ffdd 4126 {
40fb9820
L		 4127 guess_suffix = BYTE_MNEM_SUFFIX;
4128 break;
4129 }
4130 else if (i.types[op].bitfield.reg16)
252b5132 4131 {
40fb9820
L		 4132 guess_suffix = WORD_MNEM_SUFFIX;
4133 break;
4134 }
4135 else if (i.types[op].bitfield.reg32)
4136 {
4137 guess_suffix = LONG_MNEM_SUFFIX;
4138 break;
4139 }
4140 else if (i.types[op].bitfield.reg64)
4141 {
4142 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4143 break;
252b5132 4144 }
29b0f896
AM		 4145 }
4146 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4147 guess_suffix = WORD_MNEM_SUFFIX;
4148
4149 for (op = i.operands; --op >= 0;)
40fb9820 4150 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4151 {
4152 switch (i.op[op].imms->X_op)
252b5132 4153 {
29b0f896
AM		 4154 case O_constant:
4155 /* If a suffix is given, this operand may be shortened. */
4156 switch (guess_suffix)
252b5132 4157 {
29b0f896 4158 case LONG_MNEM_SUFFIX:
40fb9820
L		 4159 i.types[op].bitfield.imm32 = 1;
4160 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4161 break;
4162 case WORD_MNEM_SUFFIX:
40fb9820
L		 4163 i.types[op].bitfield.imm16 = 1;
4164 i.types[op].bitfield.imm32 = 1;
4165 i.types[op].bitfield.imm32s = 1;
4166 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4167 break;
4168 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4169 i.types[op].bitfield.imm8 = 1;
4170 i.types[op].bitfield.imm8s = 1;
4171 i.types[op].bitfield.imm16 = 1;
4172 i.types[op].bitfield.imm32 = 1;
4173 i.types[op].bitfield.imm32s = 1;
4174 i.types[op].bitfield.imm64 = 1;
29b0f896 4175 break;
252b5132 4176 }
252b5132 4177
29b0f896
AM		 4178 /* If this operand is at most 16 bits, convert it
4179 to a signed 16 bit number before trying to see
4180 whether it will fit in an even smaller size.
4181 This allows a 16-bit operand such as $0xffe0 to
4182 be recognised as within Imm8S range. */
40fb9820 4183 if ((i.types[op].bitfield.imm16)
29b0f896 4184 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4185 {
29b0f896
AM		 4186 i.op[op].imms->X_add_number =
4187 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4188 }
40fb9820 4189 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4190 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4191 == 0))
4192 {
4193 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4194 ^ ((offsetT) 1 << 31))
4195 - ((offsetT) 1 << 31));
4196 }
40fb9820 4197 i.types[op]
c6fb90c8
L		 4198 = operand_type_or (i.types[op],
4199 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4200
29b0f896
AM		 4201 /* We must avoid matching of Imm32 templates when 64bit
4202 only immediate is available. */
4203 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4204 i.types[op].bitfield.imm32 = 0;
29b0f896 4205 break;
252b5132 4206
29b0f896
AM		 4207 case O_absent:
4208 case O_register:
4209 abort ();
4210
4211 /* Symbols and expressions. */
4212 default:
9cd96992
JB		 4213 /* Convert symbolic operand to proper sizes for matching, but don't
4214 prevent matching a set of insns that only supports sizes other
4215 than those matching the insn suffix. */
4216 {
40fb9820 4217 i386_operand_type mask, allowed;
d3ce72d0 4218 const insn_template *t;
9cd96992 4219
0dfbf9d7
L		 4220 operand_type_set (&mask, 0);
4221 operand_type_set (&allowed, 0);
40fb9820 4222
4eed87de
AM		 4223 for (t = current_templates->start;
4224 t < current_templates->end;
4225 ++t)
c6fb90c8
L		 4226 allowed = operand_type_or (allowed,
4227 t->operand_types[op]);
9cd96992
JB		 4228 switch (guess_suffix)
4229 {
4230 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4231 mask.bitfield.imm64 = 1;
4232 mask.bitfield.imm32s = 1;
9cd96992
JB		 4233 break;
4234 case LONG_MNEM_SUFFIX:
40fb9820 4235 mask.bitfield.imm32 = 1;
9cd96992
JB		 4236 break;
4237 case WORD_MNEM_SUFFIX:
40fb9820 4238 mask.bitfield.imm16 = 1;
9cd96992
JB		 4239 break;
4240 case BYTE_MNEM_SUFFIX:
40fb9820 4241 mask.bitfield.imm8 = 1;
9cd96992
JB		 4242 break;
4243 default:
9cd96992
JB		 4244 break;
4245 }
c6fb90c8 4246 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4247 if (!operand_type_all_zero (&allowed))
c6fb90c8 4248 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4249 }
29b0f896 4250 break;
252b5132 4251 }
29b0f896
AM		 4252 }
4253}
47926f60 4254
29b0f896
AM		 4255/* Try to use the smallest displacement type too. */
4256static void
e3bb37b5 4257optimize_disp (void)
29b0f896
AM		 4258{
4259 int op;
3e73aa7c 4260
29b0f896 4261 for (op = i.operands; --op >= 0;)
40fb9820 4262 if (operand_type_check (i.types[op], disp))
252b5132 4263 {
b300c311 4264 if (i.op[op].disps->X_op == O_constant)
252b5132 4265 {
91d6fa6a 4266 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4267
40fb9820 4268 if (i.types[op].bitfield.disp16
91d6fa6a 4269 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4270 {
4271 /* If this operand is at most 16 bits, convert
4272 to a signed 16 bit number and don't use 64bit
4273 displacement. */
91d6fa6a 4274 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4275 i.types[op].bitfield.disp64 = 0;
b300c311 4276 }
40fb9820 4277 if (i.types[op].bitfield.disp32
91d6fa6a 4278 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4279 {
4280 /* If this operand is at most 32 bits, convert
4281 to a signed 32 bit number and don't use 64bit
4282 displacement. */
91d6fa6a
NC		 4283 op_disp &= (((offsetT) 2 << 31) - 1);
4284 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4285 i.types[op].bitfield.disp64 = 0;
b300c311 4286 }
91d6fa6a 4287 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4288 {
40fb9820
L		 4289 i.types[op].bitfield.disp8 = 0;
4290 i.types[op].bitfield.disp16 = 0;
4291 i.types[op].bitfield.disp32 = 0;
4292 i.types[op].bitfield.disp32s = 0;
4293 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4294 i.op[op].disps = 0;
4295 i.disp_operands--;
4296 }
4297 else if (flag_code == CODE_64BIT)
4298 {
91d6fa6a 4299 if (fits_in_signed_long (op_disp))
28a9d8f5 4300 {
40fb9820
L		 4301 i.types[op].bitfield.disp64 = 0;
4302 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4303 }
0e1147d9 4304 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4305 && fits_in_unsigned_long (op_disp))
40fb9820 4306 i.types[op].bitfield.disp32 = 1;
b300c311 4307 }
40fb9820
L		 4308 if ((i.types[op].bitfield.disp32
4309 || i.types[op].bitfield.disp32s
4310 || i.types[op].bitfield.disp16)
91d6fa6a 4311 && fits_in_signed_byte (op_disp))
40fb9820 4312 i.types[op].bitfield.disp8 = 1;
252b5132 4313 }
67a4f2b7
AO		 4314 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4315 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4316 {
4317 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4318 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4319 i.types[op].bitfield.disp8 = 0;
4320 i.types[op].bitfield.disp16 = 0;
4321 i.types[op].bitfield.disp32 = 0;
4322 i.types[op].bitfield.disp32s = 0;
4323 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4324 }
4325 else
b300c311 4326 /* We only support 64bit displacement on constants. */
40fb9820 4327 i.types[op].bitfield.disp64 = 0;
252b5132 4328 }
29b0f896
AM		 4329}
4330
6c30d220
L		 4331/* Check if operands are valid for the instruction. */
4332
4333static int
4334check_VecOperands (const insn_template *t)
4335{
43234a1e
L		 4336 unsigned int op;
4337
6c30d220
L		 4338 /* Without VSIB byte, we can't have a vector register for index. */
4339 if (!t->opcode_modifier.vecsib
4340 && i.index_reg
4341 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4342 || i.index_reg->reg_type.bitfield.regymm
4343 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4344 {
4345 i.error = unsupported_vector_index_register;
4346 return 1;
4347 }
4348
ad8ecc81
MZ		 4349 /* Check if default mask is allowed. */
4350 if (t->opcode_modifier.nodefmask
4351 && (!i.mask || i.mask->mask->reg_num == 0))
4352 {
4353 i.error = no_default_mask;
4354 return 1;
4355 }
4356
7bab8ab5
JB		 4357 /* For VSIB byte, we need a vector register for index, and all vector
4358 registers must be distinct. */
4359 if (t->opcode_modifier.vecsib)
4360 {
4361 if (!i.index_reg
6c30d220
L		 4362 || !((t->opcode_modifier.vecsib == VecSIB128
4363 && i.index_reg->reg_type.bitfield.regxmm)
4364 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4365 && i.index_reg->reg_type.bitfield.regymm)
4366 || (t->opcode_modifier.vecsib == VecSIB512
4367 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4368 {
4369 i.error = invalid_vsib_address;
4370 return 1;
4371 }
4372
43234a1e
L		 4373 gas_assert (i.reg_operands == 2 || i.mask);
4374 if (i.reg_operands == 2 && !i.mask)
4375 {
4376 gas_assert (i.types[0].bitfield.regxmm
4377 || i.types[0].bitfield.regymm
4378 || i.types[0].bitfield.regzmm);
4379 gas_assert (i.types[2].bitfield.regxmm
4380 || i.types[2].bitfield.regymm
4381 || i.types[2].bitfield.regzmm);
4382 if (operand_check == check_none)
4383 return 0;
4384 if (register_number (i.op[0].regs)
4385 != register_number (i.index_reg)
4386 && register_number (i.op[2].regs)
4387 != register_number (i.index_reg)
4388 && register_number (i.op[0].regs)
4389 != register_number (i.op[2].regs))
4390 return 0;
4391 if (operand_check == check_error)
4392 {
4393 i.error = invalid_vector_register_set;
4394 return 1;
4395 }
4396 as_warn (_("mask, index, and destination registers should be distinct"));
4397 }
4398 }
7bab8ab5 4399
43234a1e
L		 4400 /* Check if broadcast is supported by the instruction and is applied
4401 to the memory operand. */
4402 if (i.broadcast)
4403 {
4404 int broadcasted_opnd_size;
4405
4406 /* Check if specified broadcast is supported in this instruction,
4407 and it's applied to memory operand of DWORD or QWORD type,
4408 depending on VecESize. */
4409 if (i.broadcast->type != t->opcode_modifier.broadcast
4410 || !i.types[i.broadcast->operand].bitfield.mem
4411 || (t->opcode_modifier.vecesize == 0
4412 && !i.types[i.broadcast->operand].bitfield.dword
4413 && !i.types[i.broadcast->operand].bitfield.unspecified)
4414 || (t->opcode_modifier.vecesize == 1
4415 && !i.types[i.broadcast->operand].bitfield.qword
4416 && !i.types[i.broadcast->operand].bitfield.unspecified))
4417 goto bad_broadcast;
4418
4419 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4420 if (i.broadcast->type == BROADCAST_1TO16)
4421 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4422 else if (i.broadcast->type == BROADCAST_1TO8)
4423 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
4424 else
4425 goto bad_broadcast;
4426
4427 if ((broadcasted_opnd_size == 256
4428 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4429 || (broadcasted_opnd_size == 512
4430 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4431 {
4432 bad_broadcast:
4433 i.error = unsupported_broadcast;
4434 return 1;
4435 }
4436 }
4437 /* If broadcast is supported in this instruction, we need to check if
4438 operand of one-element size isn't specified without broadcast. */
4439 else if (t->opcode_modifier.broadcast && i.mem_operands)
4440 {
4441 /* Find memory operand. */
4442 for (op = 0; op < i.operands; op++)
4443 if (operand_type_check (i.types[op], anymem))
4444 break;
4445 gas_assert (op < i.operands);
4446 /* Check size of the memory operand. */
4447 if ((t->opcode_modifier.vecesize == 0
4448 && i.types[op].bitfield.dword)
4449 || (t->opcode_modifier.vecesize == 1
4450 && i.types[op].bitfield.qword))
4451 {
4452 i.error = broadcast_needed;
4453 return 1;
4454 }
4455 }
4456
4457 /* Check if requested masking is supported. */
4458 if (i.mask
4459 && (!t->opcode_modifier.masking
4460 || (i.mask->zeroing
4461 && t->opcode_modifier.masking == MERGING_MASKING)))
4462 {
4463 i.error = unsupported_masking;
4464 return 1;
4465 }
4466
4467 /* Check if masking is applied to dest operand. */
4468 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4469 {
4470 i.error = mask_not_on_destination;
4471 return 1;
4472 }
4473
43234a1e
L		 4474 /* Check RC/SAE. */
4475 if (i.rounding)
4476 {
4477 if ((i.rounding->type != saeonly
4478 && !t->opcode_modifier.staticrounding)
4479 || (i.rounding->type == saeonly
4480 && (t->opcode_modifier.staticrounding
4481 || !t->opcode_modifier.sae)))
4482 {
4483 i.error = unsupported_rc_sae;
4484 return 1;
4485 }
4486 /* If the instruction has several immediate operands and one of
4487 them is rounding, the rounding operand should be the last
4488 immediate operand. */
4489 if (i.imm_operands > 1
4490 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4491 {
43234a1e 4492 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4493 return 1;
4494 }
6c30d220
L		 4495 }
4496
43234a1e
L		 4497 /* Check vector Disp8 operand. */
4498 if (t->opcode_modifier.disp8memshift)
4499 {
4500 if (i.broadcast)
4501 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4502 else
4503 i.memshift = t->opcode_modifier.disp8memshift;
4504
4505 for (op = 0; op < i.operands; op++)
4506 if (operand_type_check (i.types[op], disp)
4507 && i.op[op].disps->X_op == O_constant)
4508 {
4509 offsetT value = i.op[op].disps->X_add_number;
4510 int vec_disp8_ok = fits_in_vec_disp8 (value);
4511 if (t->operand_types [op].bitfield.vec_disp8)
4512 {
4513 if (vec_disp8_ok)
4514 i.types[op].bitfield.vec_disp8 = 1;
4515 else
4516 {
4517 /* Vector insn can only have Vec_Disp8/Disp32 in
4518 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4519 mode. */
4520 i.types[op].bitfield.disp8 = 0;
4521 if (flag_code != CODE_16BIT)
4522 i.types[op].bitfield.disp16 = 0;
4523 }
4524 }
4525 else if (flag_code != CODE_16BIT)
4526 {
4527 /* One form of this instruction supports vector Disp8.
4528 Try vector Disp8 if we need to use Disp32. */
4529 if (vec_disp8_ok && !fits_in_signed_byte (value))
4530 {
4531 i.error = try_vector_disp8;
4532 return 1;
4533 }
4534 }
4535 }
4536 }
4537 else
4538 i.memshift = -1;
4539
6c30d220
L		 4540 return 0;
4541}
4542
43f3e2ee 4543/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4544 operand types. */
4545
4546static int
4547VEX_check_operands (const insn_template *t)
4548{
43234a1e
L		 4549 /* VREX is only valid with EVEX prefix. */
4550 if (i.need_vrex && !t->opcode_modifier.evex)
4551 {
4552 i.error = invalid_register_operand;
4553 return 1;
4554 }
4555
a683cc34
SP		 4556 if (!t->opcode_modifier.vex)
4557 return 0;
4558
4559 /* Only check VEX_Imm4, which must be the first operand. */
4560 if (t->operand_types[0].bitfield.vec_imm4)
4561 {
4562 if (i.op[0].imms->X_op != O_constant
4563 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4564 {
a65babc9 4565 i.error = bad_imm4;
891edac4
L		 4566 return 1;
4567 }
a683cc34
SP		 4568
4569 /* Turn off Imm8 so that update_imm won't complain. */
4570 i.types[0] = vec_imm4;
4571 }
4572
4573 return 0;
4574}
4575
d3ce72d0 4576static const insn_template *
e3bb37b5 4577match_template (void)
29b0f896
AM		 4578{
4579 /* Points to template once we've found it. */
d3ce72d0 4580 const insn_template *t;
40fb9820 4581 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4582 i386_operand_type overlap4;
29b0f896 4583 unsigned int found_reverse_match;
40fb9820
L		 4584 i386_opcode_modifier suffix_check;
4585 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4586 int addr_prefix_disp;
a5c311ca 4587 unsigned int j;
3629bb00 4588 unsigned int found_cpu_match;
45664ddb 4589 unsigned int check_register;
5614d22c 4590 enum i386_error specific_error = 0;
29b0f896 4591
c0f3af97
L		 4592#if MAX_OPERANDS != 5
4593# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4594#endif
4595
29b0f896 4596 found_reverse_match = 0;
539e75ad 4597 addr_prefix_disp = -1;
40fb9820
L		 4598
4599 memset (&suffix_check, 0, sizeof (suffix_check));
4600 if (i.suffix == BYTE_MNEM_SUFFIX)
4601 suffix_check.no_bsuf = 1;
4602 else if (i.suffix == WORD_MNEM_SUFFIX)
4603 suffix_check.no_wsuf = 1;
4604 else if (i.suffix == SHORT_MNEM_SUFFIX)
4605 suffix_check.no_ssuf = 1;
4606 else if (i.suffix == LONG_MNEM_SUFFIX)
4607 suffix_check.no_lsuf = 1;
4608 else if (i.suffix == QWORD_MNEM_SUFFIX)
4609 suffix_check.no_qsuf = 1;
4610 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4611 suffix_check.no_ldsuf = 1;
29b0f896 4612
01559ecc
L		 4613 /* Must have right number of operands. */
4614 i.error = number_of_operands_mismatch;
4615
45aa61fe 4616 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4617 {
539e75ad
L		 4618 addr_prefix_disp = -1;
4619
29b0f896
AM		 4620 if (i.operands != t->operands)
4621 continue;
4622
50aecf8c 4623 /* Check processor support. */
a65babc9 4624 i.error = unsupported;
c0f3af97
L		 4625 found_cpu_match = (cpu_flags_match (t)
4626 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4627 if (!found_cpu_match)
4628 continue;
4629
e1d4d893 4630 /* Check old gcc support. */
a65babc9 4631 i.error = old_gcc_only;
e1d4d893
L		 4632 if (!old_gcc && t->opcode_modifier.oldgcc)
4633 continue;
4634
4635 /* Check AT&T mnemonic. */
a65babc9 4636 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4637 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4638 continue;
4639
891edac4 4640 /* Check AT&T/Intel syntax. */
a65babc9 4641 i.error = unsupported_syntax;
5c07affc
L		 4642 if ((intel_syntax && t->opcode_modifier.attsyntax)
4643 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4644 continue;
4645
20592a94 4646 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4647 i.error = invalid_instruction_suffix;
567e4e96
L		 4648 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4649 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4650 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4651 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4652 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4653 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4654 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4655 continue;
4656
5c07affc 4657 if (!operand_size_match (t))
7d5e4556 4658 continue;
539e75ad 4659
5c07affc
L		 4660 for (j = 0; j < MAX_OPERANDS; j++)
4661 operand_types[j] = t->operand_types[j];
4662
45aa61fe
AM		 4663 /* In general, don't allow 64-bit operands in 32-bit mode. */
4664 if (i.suffix == QWORD_MNEM_SUFFIX
4665 && flag_code != CODE_64BIT
4666 && (intel_syntax
40fb9820 4667 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4668 && !intel_float_operand (t->name))
4669 : intel_float_operand (t->name) != 2)
40fb9820 4670 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4671 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4672 && !operand_types[0].bitfield.regymm
4673 && !operand_types[0].bitfield.regzmm)
40fb9820 4674 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97 4675 && !!operand_types[t->operands > 1].bitfield.regxmm
43234a1e
L		 4676 && !!operand_types[t->operands > 1].bitfield.regymm
4677 && !!operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4678 && (t->base_opcode != 0x0fc7
4679 || t->extension_opcode != 1 /* cmpxchg8b */))
4680 continue;
4681
192dc9c6
JB		 4682 /* In general, don't allow 32-bit operands on pre-386. */
4683 else if (i.suffix == LONG_MNEM_SUFFIX
4684 && !cpu_arch_flags.bitfield.cpui386
4685 && (intel_syntax
4686 ? (!t->opcode_modifier.ignoresize
4687 && !intel_float_operand (t->name))
4688 : intel_float_operand (t->name) != 2)
4689 && ((!operand_types[0].bitfield.regmmx
4690 && !operand_types[0].bitfield.regxmm)
4691 || (!operand_types[t->operands > 1].bitfield.regmmx
4692 && !!operand_types[t->operands > 1].bitfield.regxmm)))
4693 continue;
4694
29b0f896 4695 /* Do not verify operands when there are none. */
50aecf8c 4696 else
29b0f896 4697 {
c6fb90c8 4698 if (!t->operands)
2dbab7d5
L		 4699 /* We've found a match; break out of loop. */
4700 break;
29b0f896 4701 }
252b5132 4702
539e75ad
L		 4703 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4704 into Disp32/Disp16/Disp32 operand. */
4705 if (i.prefix[ADDR_PREFIX] != 0)
4706 {
40fb9820 4707 /* There should be only one Disp operand. */
539e75ad
L		 4708 switch (flag_code)
4709 {
4710 case CODE_16BIT:
40fb9820
L		 4711 for (j = 0; j < MAX_OPERANDS; j++)
4712 {
4713 if (operand_types[j].bitfield.disp16)
4714 {
4715 addr_prefix_disp = j;
4716 operand_types[j].bitfield.disp32 = 1;
4717 operand_types[j].bitfield.disp16 = 0;
4718 break;
4719 }
4720 }
539e75ad
L		 4721 break;
4722 case CODE_32BIT:
40fb9820
L		 4723 for (j = 0; j < MAX_OPERANDS; j++)
4724 {
4725 if (operand_types[j].bitfield.disp32)
4726 {
4727 addr_prefix_disp = j;
4728 operand_types[j].bitfield.disp32 = 0;
4729 operand_types[j].bitfield.disp16 = 1;
4730 break;
4731 }
4732 }
539e75ad
L		 4733 break;
4734 case CODE_64BIT:
40fb9820
L		 4735 for (j = 0; j < MAX_OPERANDS; j++)
4736 {
4737 if (operand_types[j].bitfield.disp64)
4738 {
4739 addr_prefix_disp = j;
4740 operand_types[j].bitfield.disp64 = 0;
4741 operand_types[j].bitfield.disp32 = 1;
4742 break;
4743 }
4744 }
539e75ad
L		 4745 break;
4746 }
539e75ad
L		 4747 }
4748
56ffb741
L		 4749 /* We check register size if needed. */
4750 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4751 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4752 switch (t->operands)
4753 {
4754 case 1:
40fb9820 4755 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4756 continue;
4757 break;
4758 case 2:
8b38ad71
L		 4759 /* xchg %eax, %eax is a special case. It is an aliase for nop
4760 only in 32bit mode and we can use opcode 0x90. In 64bit
4761 mode, we can't use 0x90 for xchg %eax, %eax since it should
4762 zero-extend %eax to %rax. */
4763 if (flag_code == CODE_64BIT
4764 && t->base_opcode == 0x90
0dfbf9d7
L		 4765 && operand_type_equal (&i.types [0], &acc32)
4766 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4767 continue;
b6169b20
L		 4768 if (i.swap_operand)
4769 {
4770 /* If we swap operand in encoding, we either match
4771 the next one or reverse direction of operands. */
4772 if (t->opcode_modifier.s)
4773 continue;
4774 else if (t->opcode_modifier.d)
4775 goto check_reverse;
4776 }
4777
29b0f896 4778 case 3:
fa99fab2
L		 4779 /* If we swap operand in encoding, we match the next one. */
4780 if (i.swap_operand && t->opcode_modifier.s)
4781 continue;
f48ff2ae 4782 case 4:
c0f3af97 4783 case 5:
c6fb90c8 4784 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4785 if (!operand_type_match (overlap0, i.types[0])
4786 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4787 || (check_register
4788 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4789 operand_types[0],
4790 overlap1, i.types[1],
4791 operand_types[1])))
29b0f896
AM		 4792 {
4793 /* Check if other direction is valid ... */
40fb9820 4794 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4795 continue;
4796
b6169b20 4797check_reverse:
29b0f896 4798 /* Try reversing direction of operands. */
c6fb90c8
L		 4799 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4800 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4801 if (!operand_type_match (overlap0, i.types[0])
4802 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4803 || (check_register
4804 && !operand_type_register_match (overlap0,
4805 i.types[0],
4806 operand_types[1],
4807 overlap1,
4808 i.types[1],
4809 operand_types[0])))
29b0f896
AM		 4810 {
4811 /* Does not match either direction. */
4812 continue;
4813 }
4814 /* found_reverse_match holds which of D or FloatDR
4815 we've found. */
40fb9820 4816 if (t->opcode_modifier.d)
8a2ed489 4817 found_reverse_match = Opcode_D;
40fb9820 4818 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4819 found_reverse_match = Opcode_FloatD;
4820 else
4821 found_reverse_match = 0;
40fb9820 4822 if (t->opcode_modifier.floatr)
8a2ed489 4823 found_reverse_match |= Opcode_FloatR;
29b0f896 4824 }
f48ff2ae 4825 else
29b0f896 4826 {
f48ff2ae 4827 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4828 switch (t->operands)
4829 {
c0f3af97
L		 4830 case 5:
4831 overlap4 = operand_type_and (i.types[4],
4832 operand_types[4]);
d1cbb4db 4833 case 4:
c6fb90c8
L		 4834 overlap3 = operand_type_and (i.types[3],
4835 operand_types[3]);
d1cbb4db 4836 case 3:
c6fb90c8
L		 4837 overlap2 = operand_type_and (i.types[2],
4838 operand_types[2]);
d1cbb4db
L		 4839 break;
4840 }
29b0f896 4841
f48ff2ae
L		 4842 switch (t->operands)
4843 {
c0f3af97
L		 4844 case 5:
4845 if (!operand_type_match (overlap4, i.types[4])
4846 || !operand_type_register_match (overlap3,
4847 i.types[3],
4848 operand_types[3],
4849 overlap4,
4850 i.types[4],
4851 operand_types[4]))
4852 continue;
f48ff2ae 4853 case 4:
40fb9820 4854 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4855 || (check_register
4856 && !operand_type_register_match (overlap2,
4857 i.types[2],
4858 operand_types[2],
4859 overlap3,
4860 i.types[3],
4861 operand_types[3])))
f48ff2ae
L		 4862 continue;
4863 case 3:
4864 /* Here we make use of the fact that there are no
4865 reverse match 3 operand instructions, and all 3
4866 operand instructions only need to be checked for
4867 register consistency between operands 2 and 3. */
40fb9820 4868 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4869 || (check_register
4870 && !operand_type_register_match (overlap1,
4871 i.types[1],
4872 operand_types[1],
4873 overlap2,
4874 i.types[2],
4875 operand_types[2])))
f48ff2ae
L		 4876 continue;
4877 break;
4878 }
29b0f896 4879 }
f48ff2ae 4880 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4881 slip through to break. */
4882 }
3629bb00 4883 if (!found_cpu_match)
29b0f896
AM		 4884 {
4885 found_reverse_match = 0;
4886 continue;
4887 }
c0f3af97 4888
5614d22c
JB		 4889 /* Check if vector and VEX operands are valid. */
4890 if (check_VecOperands (t) || VEX_check_operands (t))
4891 {
4892 specific_error = i.error;
4893 continue;
4894 }
a683cc34 4895
29b0f896
AM		 4896 /* We've found a match; break out of loop. */
4897 break;
4898 }
4899
4900 if (t == current_templates->end)
4901 {
4902 /* We found no match. */
a65babc9 4903 const char *err_msg;
5614d22c 4904 switch (specific_error ? specific_error : i.error)
a65babc9
L		 4905 {
4906 default:
4907 abort ();
86e026a4 4908 case operand_size_mismatch:
a65babc9
L		 4909 err_msg = _("operand size mismatch");
4910 break;
4911 case operand_type_mismatch:
4912 err_msg = _("operand type mismatch");
4913 break;
4914 case register_type_mismatch:
4915 err_msg = _("register type mismatch");
4916 break;
4917 case number_of_operands_mismatch:
4918 err_msg = _("number of operands mismatch");
4919 break;
4920 case invalid_instruction_suffix:
4921 err_msg = _("invalid instruction suffix");
4922 break;
4923 case bad_imm4:
4a2608e3 4924 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 4925 break;
4926 case old_gcc_only:
4927 err_msg = _("only supported with old gcc");
4928 break;
4929 case unsupported_with_intel_mnemonic:
4930 err_msg = _("unsupported with Intel mnemonic");
4931 break;
4932 case unsupported_syntax:
4933 err_msg = _("unsupported syntax");
4934 break;
4935 case unsupported:
35262a23 4936 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 4937 current_templates->start->name);
4938 return NULL;
6c30d220
L		 4939 case invalid_vsib_address:
4940 err_msg = _("invalid VSIB address");
4941 break;
7bab8ab5
JB		 4942 case invalid_vector_register_set:
4943 err_msg = _("mask, index, and destination registers must be distinct");
4944 break;
6c30d220
L		 4945 case unsupported_vector_index_register:
4946 err_msg = _("unsupported vector index register");
4947 break;
43234a1e
L		 4948 case unsupported_broadcast:
4949 err_msg = _("unsupported broadcast");
4950 break;
4951 case broadcast_not_on_src_operand:
4952 err_msg = _("broadcast not on source memory operand");
4953 break;
4954 case broadcast_needed:
4955 err_msg = _("broadcast is needed for operand of such type");
4956 break;
4957 case unsupported_masking:
4958 err_msg = _("unsupported masking");
4959 break;
4960 case mask_not_on_destination:
4961 err_msg = _("mask not on destination operand");
4962 break;
4963 case no_default_mask:
4964 err_msg = _("default mask isn't allowed");
4965 break;
4966 case unsupported_rc_sae:
4967 err_msg = _("unsupported static rounding/sae");
4968 break;
4969 case rc_sae_operand_not_last_imm:
4970 if (intel_syntax)
4971 err_msg = _("RC/SAE operand must precede immediate operands");
4972 else
4973 err_msg = _("RC/SAE operand must follow immediate operands");
4974 break;
4975 case invalid_register_operand:
4976 err_msg = _("invalid register operand");
4977 break;
a65babc9
L		 4978 }
4979 as_bad (_("%s for `%s'"), err_msg,
891edac4 4980 current_templates->start->name);
fa99fab2 4981 return NULL;
29b0f896 4982 }
252b5132 4983
29b0f896
AM		 4984 if (!quiet_warnings)
4985 {
4986 if (!intel_syntax
40fb9820
L		 4987 && (i.types[0].bitfield.jumpabsolute
4988 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 4989 {
4990 as_warn (_("indirect %s without `*'"), t->name);
4991 }
4992
40fb9820
L		 4993 if (t->opcode_modifier.isprefix
4994 && t->opcode_modifier.ignoresize)
29b0f896
AM		 4995 {
4996 /* Warn them that a data or address size prefix doesn't
4997 affect assembly of the next line of code. */
4998 as_warn (_("stand-alone `%s' prefix"), t->name);
4999 }
5000 }
5001
5002 /* Copy the template we found. */
5003 i.tm = *t;
539e75ad
L		 5004
5005 if (addr_prefix_disp != -1)
5006 i.tm.operand_types[addr_prefix_disp]
5007 = operand_types[addr_prefix_disp];
5008
29b0f896
AM		 5009 if (found_reverse_match)
5010 {
5011 /* If we found a reverse match we must alter the opcode
5012 direction bit. found_reverse_match holds bits to change
5013 (different for int & float insns). */
5014
5015 i.tm.base_opcode ^= found_reverse_match;
5016
539e75ad
L		 5017 i.tm.operand_types[0] = operand_types[1];
5018 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5019 }
5020
fa99fab2 5021 return t;
29b0f896
AM		 5022}
5023
5024static int
e3bb37b5 5025check_string (void)
29b0f896 5026{
40fb9820
L		 5027 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5028 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5029 {
5030 if (i.seg[0] != NULL && i.seg[0] != &es)
5031 {
a87af027 5032 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5033 i.tm.name,
a87af027
JB		 5034 mem_op + 1,
5035 register_prefix);
29b0f896
AM		 5036 return 0;
5037 }
5038 /* There's only ever one segment override allowed per instruction.
5039 This instruction possibly has a legal segment override on the
5040 second operand, so copy the segment to where non-string
5041 instructions store it, allowing common code. */
5042 i.seg[0] = i.seg[1];
5043 }
40fb9820 5044 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5045 {
5046 if (i.seg[1] != NULL && i.seg[1] != &es)
5047 {
a87af027 5048 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5049 i.tm.name,
a87af027
JB		 5050 mem_op + 2,
5051 register_prefix);
29b0f896
AM		 5052 return 0;
5053 }
5054 }
5055 return 1;
5056}
5057
5058static int
543613e9 5059process_suffix (void)
29b0f896
AM		 5060{
5061 /* If matched instruction specifies an explicit instruction mnemonic
5062 suffix, use it. */
40fb9820
L		 5063 if (i.tm.opcode_modifier.size16)
5064 i.suffix = WORD_MNEM_SUFFIX;
5065 else if (i.tm.opcode_modifier.size32)
5066 i.suffix = LONG_MNEM_SUFFIX;
5067 else if (i.tm.opcode_modifier.size64)
5068 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5069 else if (i.reg_operands)
5070 {
5071 /* If there's no instruction mnemonic suffix we try to invent one
5072 based on register operands. */
5073 if (!i.suffix)
5074 {
5075 /* We take i.suffix from the last register operand specified,
5076 Destination register type is more significant than source
381d071f
L		 5077 register type. crc32 in SSE4.2 prefers source register
5078 type. */
5079 if (i.tm.base_opcode == 0xf20f38f1)
5080 {
40fb9820
L		 5081 if (i.types[0].bitfield.reg16)
5082 i.suffix = WORD_MNEM_SUFFIX;
5083 else if (i.types[0].bitfield.reg32)
5084 i.suffix = LONG_MNEM_SUFFIX;
5085 else if (i.types[0].bitfield.reg64)
5086 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5087 }
9344ff29 5088 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5089 {
40fb9820 5090 if (i.types[0].bitfield.reg8)
20592a94
L		 5091 i.suffix = BYTE_MNEM_SUFFIX;
5092 }
381d071f
L		 5093
5094 if (!i.suffix)
5095 {
5096 int op;
5097
20592a94
L		 5098 if (i.tm.base_opcode == 0xf20f38f1
5099 || i.tm.base_opcode == 0xf20f38f0)
5100 {
5101 /* We have to know the operand size for crc32. */
5102 as_bad (_("ambiguous memory operand size for `%s`"),
5103 i.tm.name);
5104 return 0;
5105 }
5106
381d071f 5107 for (op = i.operands; --op >= 0;)
40fb9820 5108 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5109 {
40fb9820
L		 5110 if (i.types[op].bitfield.reg8)
5111 {
5112 i.suffix = BYTE_MNEM_SUFFIX;
5113 break;
5114 }
5115 else if (i.types[op].bitfield.reg16)
5116 {
5117 i.suffix = WORD_MNEM_SUFFIX;
5118 break;
5119 }
5120 else if (i.types[op].bitfield.reg32)
5121 {
5122 i.suffix = LONG_MNEM_SUFFIX;
5123 break;
5124 }
5125 else if (i.types[op].bitfield.reg64)
5126 {
5127 i.suffix = QWORD_MNEM_SUFFIX;
5128 break;
5129 }
381d071f
L		 5130 }
5131 }
29b0f896
AM		 5132 }
5133 else if (i.suffix == BYTE_MNEM_SUFFIX)
5134 {
2eb952a4
L		 5135 if (intel_syntax
5136 && i.tm.opcode_modifier.ignoresize
5137 && i.tm.opcode_modifier.no_bsuf)
5138 i.suffix = 0;
5139 else if (!check_byte_reg ())
29b0f896
AM		 5140 return 0;
5141 }
5142 else if (i.suffix == LONG_MNEM_SUFFIX)
5143 {
2eb952a4
L		 5144 if (intel_syntax
5145 && i.tm.opcode_modifier.ignoresize
5146 && i.tm.opcode_modifier.no_lsuf)
5147 i.suffix = 0;
5148 else if (!check_long_reg ())
29b0f896
AM		 5149 return 0;
5150 }
5151 else if (i.suffix == QWORD_MNEM_SUFFIX)
5152 {
955e1e6a
L		 5153 if (intel_syntax
5154 && i.tm.opcode_modifier.ignoresize
5155 && i.tm.opcode_modifier.no_qsuf)
5156 i.suffix = 0;
5157 else if (!check_qword_reg ())
29b0f896
AM		 5158 return 0;
5159 }
5160 else if (i.suffix == WORD_MNEM_SUFFIX)
5161 {
2eb952a4
L		 5162 if (intel_syntax
5163 && i.tm.opcode_modifier.ignoresize
5164 && i.tm.opcode_modifier.no_wsuf)
5165 i.suffix = 0;
5166 else if (!check_word_reg ())
29b0f896
AM		 5167 return 0;
5168 }
c0f3af97 5169 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5170 || i.suffix == YMMWORD_MNEM_SUFFIX
5171 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5172 {
43234a1e 5173 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5174 should check if it is a valid suffix. */
5175 }
40fb9820 5176 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5177 /* Do nothing if the instruction is going to ignore the prefix. */
5178 ;
5179 else
5180 abort ();
5181 }
40fb9820 5182 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5183 && !i.suffix
5184 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5185 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5186 {
5187 i.suffix = stackop_size;
5188 }
9306ca4a
JB		 5189 else if (intel_syntax
5190 && !i.suffix
40fb9820
L		 5191 && (i.tm.operand_types[0].bitfield.jumpabsolute
5192 || i.tm.opcode_modifier.jumpbyte
5193 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5194 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5195 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5196 {
5197 switch (flag_code)
5198 {
5199 case CODE_64BIT:
40fb9820 5200 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5201 {
5202 i.suffix = QWORD_MNEM_SUFFIX;
5203 break;
5204 }
5205 case CODE_32BIT:
40fb9820 5206 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5207 i.suffix = LONG_MNEM_SUFFIX;
5208 break;
5209 case CODE_16BIT:
40fb9820 5210 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5211 i.suffix = WORD_MNEM_SUFFIX;
5212 break;
5213 }
5214 }
252b5132 5215
9306ca4a 5216 if (!i.suffix)
29b0f896 5217 {
9306ca4a
JB		 5218 if (!intel_syntax)
5219 {
40fb9820 5220 if (i.tm.opcode_modifier.w)
9306ca4a 5221 {
4eed87de
AM		 5222 as_bad (_("no instruction mnemonic suffix given and "
5223 "no register operands; can't size instruction"));
9306ca4a
JB		 5224 return 0;
5225 }
5226 }
5227 else
5228 {
40fb9820 5229 unsigned int suffixes;
7ab9ffdd 5230
40fb9820
L		 5231 suffixes = !i.tm.opcode_modifier.no_bsuf;
5232 if (!i.tm.opcode_modifier.no_wsuf)
5233 suffixes |= 1 << 1;
5234 if (!i.tm.opcode_modifier.no_lsuf)
5235 suffixes |= 1 << 2;
fc4adea1 5236 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5237 suffixes |= 1 << 3;
5238 if (!i.tm.opcode_modifier.no_ssuf)
5239 suffixes |= 1 << 4;
5240 if (!i.tm.opcode_modifier.no_qsuf)
5241 suffixes |= 1 << 5;
5242
5243 /* There are more than suffix matches. */
5244 if (i.tm.opcode_modifier.w
9306ca4a 5245 || ((suffixes & (suffixes - 1))
40fb9820
L		 5246 && !i.tm.opcode_modifier.defaultsize
5247 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5248 {
5249 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5250 return 0;
5251 }
5252 }
29b0f896 5253 }
252b5132 5254
9306ca4a
JB		 5255 /* Change the opcode based on the operand size given by i.suffix;
5256 We don't need to change things for byte insns. */
5257
582d5edd
L		 5258 if (i.suffix
5259 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5260 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5261 && i.suffix != YMMWORD_MNEM_SUFFIX
5262 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5263 {
5264 /* It's not a byte, select word/dword operation. */
40fb9820 5265 if (i.tm.opcode_modifier.w)
29b0f896 5266 {
40fb9820 5267 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5268 i.tm.base_opcode |= 8;
5269 else
5270 i.tm.base_opcode |= 1;
5271 }
0f3f3d8b 5272
29b0f896
AM		 5273 /* Now select between word & dword operations via the operand
5274 size prefix, except for instructions that will ignore this
5275 prefix anyway. */
ca61edf2 5276 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5277 {
ca61edf2
L		 5278 /* The address size override prefix changes the size of the
5279 first operand. */
40fb9820
L		 5280 if ((flag_code == CODE_32BIT
5281 && i.op->regs[0].reg_type.bitfield.reg16)
5282 || (flag_code != CODE_32BIT
5283 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5284 if (!add_prefix (ADDR_PREFIX_OPCODE))
5285 return 0;
5286 }
5287 else if (i.suffix != QWORD_MNEM_SUFFIX
5288 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5289 && !i.tm.opcode_modifier.ignoresize
5290 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5291 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5292 || (flag_code == CODE_64BIT
40fb9820 5293 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5294 {
5295 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5296
40fb9820 5297 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5298 prefix = ADDR_PREFIX_OPCODE;
252b5132 5299
29b0f896
AM		 5300 if (!add_prefix (prefix))
5301 return 0;
24eab124 5302 }
252b5132 5303
29b0f896
AM		 5304 /* Set mode64 for an operand. */
5305 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5306 && flag_code == CODE_64BIT
40fb9820 5307 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5308 {
5309 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5310 need rex64. cmpxchg8b is also a special case. */
5311 if (! (i.operands == 2
5312 && i.tm.base_opcode == 0x90
5313 && i.tm.extension_opcode == None
0dfbf9d7
L		 5314 && operand_type_equal (&i.types [0], &acc64)
5315 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5316 && ! (i.operands == 1
5317 && i.tm.base_opcode == 0xfc7
5318 && i.tm.extension_opcode == 1
40fb9820
L		 5319 && !operand_type_check (i.types [0], reg)
5320 && operand_type_check (i.types [0], anymem)))
f6bee062 5321 i.rex |= REX_W;
46e883c5 5322 }
3e73aa7c 5323
29b0f896
AM		 5324 /* Size floating point instruction. */
5325 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5326 if (i.tm.opcode_modifier.floatmf)
543613e9 5327 i.tm.base_opcode ^= 4;
29b0f896 5328 }
7ecd2f8b 5329
29b0f896
AM		 5330 return 1;
5331}
3e73aa7c 5332
29b0f896 5333static int
543613e9 5334check_byte_reg (void)
29b0f896
AM		 5335{
5336 int op;
543613e9 5337
29b0f896
AM		 5338 for (op = i.operands; --op >= 0;)
5339 {
5340 /* If this is an eight bit register, it's OK. If it's the 16 or
5341 32 bit version of an eight bit register, we will just use the
5342 low portion, and that's OK too. */
40fb9820 5343 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5344 continue;
5345
5a819eb9
JB		 5346 /* I/O port address operands are OK too. */
5347 if (i.tm.operand_types[op].bitfield.inoutportreg)
5348 continue;
5349
9344ff29
L		 5350 /* crc32 doesn't generate this warning. */
5351 if (i.tm.base_opcode == 0xf20f38f0)
5352 continue;
5353
40fb9820
L		 5354 if ((i.types[op].bitfield.reg16
5355 || i.types[op].bitfield.reg32
5356 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5357 && i.op[op].regs->reg_num < 4
5358 /* Prohibit these changes in 64bit mode, since the lowering
5359 would be more complicated. */
5360 && flag_code != CODE_64BIT)
29b0f896 5361 {
29b0f896 5362#if REGISTER_WARNINGS
5a819eb9 5363 if (!quiet_warnings)
a540244d
L		 5364 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5365 register_prefix,
40fb9820 5366 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5367 ? REGNAM_AL - REGNAM_AX
5368 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5369 register_prefix,
29b0f896
AM		 5370 i.op[op].regs->reg_name,
5371 i.suffix);
5372#endif
5373 continue;
5374 }
5375 /* Any other register is bad. */
40fb9820
L		 5376 if (i.types[op].bitfield.reg16
5377 || i.types[op].bitfield.reg32
5378 || i.types[op].bitfield.reg64
5379 || i.types[op].bitfield.regmmx
5380 || i.types[op].bitfield.regxmm
c0f3af97 5381 || i.types[op].bitfield.regymm
43234a1e 5382 || i.types[op].bitfield.regzmm
40fb9820
L		 5383 || i.types[op].bitfield.sreg2
5384 || i.types[op].bitfield.sreg3
5385 || i.types[op].bitfield.control
5386 || i.types[op].bitfield.debug
5387 || i.types[op].bitfield.test
5388 || i.types[op].bitfield.floatreg
5389 || i.types[op].bitfield.floatacc)
29b0f896 5390 {
a540244d
L		 5391 as_bad (_("`%s%s' not allowed with `%s%c'"),
5392 register_prefix,
29b0f896
AM		 5393 i.op[op].regs->reg_name,
5394 i.tm.name,
5395 i.suffix);
5396 return 0;
5397 }
5398 }
5399 return 1;
5400}
5401
5402static int
e3bb37b5 5403check_long_reg (void)
29b0f896
AM		 5404{
5405 int op;
5406
5407 for (op = i.operands; --op >= 0;)
5408 /* Reject eight bit registers, except where the template requires
5409 them. (eg. movzb) */
40fb9820
L		 5410 if (i.types[op].bitfield.reg8
5411 && (i.tm.operand_types[op].bitfield.reg16
5412 || i.tm.operand_types[op].bitfield.reg32
5413 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5414 {
a540244d
L		 5415 as_bad (_("`%s%s' not allowed with `%s%c'"),
5416 register_prefix,
29b0f896
AM		 5417 i.op[op].regs->reg_name,
5418 i.tm.name,
5419 i.suffix);
5420 return 0;
5421 }
e4630f71 5422 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5423 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5424 && i.types[op].bitfield.reg16
5425 && (i.tm.operand_types[op].bitfield.reg32
5426 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5427 {
5428 /* Prohibit these changes in the 64bit mode, since the
5429 lowering is more complicated. */
5430 if (flag_code == CODE_64BIT)
252b5132 5431 {
2b5d6a91 5432 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5433 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5434 i.suffix);
5435 return 0;
252b5132 5436 }
29b0f896 5437#if REGISTER_WARNINGS
cecf1424
JB		 5438 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5439 register_prefix,
5440 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5441 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5442#endif
252b5132 5443 }
e4630f71 5444 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5445 else if (i.types[op].bitfield.reg64
5446 && (i.tm.operand_types[op].bitfield.reg32
5447 || i.tm.operand_types[op].bitfield.acc))
252b5132 5448 {
34828aad 5449 if (intel_syntax
ca61edf2 5450 && i.tm.opcode_modifier.toqword
40fb9820 5451 && !i.types[0].bitfield.regxmm)
34828aad 5452 {
ca61edf2 5453 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5454 i.suffix = QWORD_MNEM_SUFFIX;
5455 }
5456 else
5457 {
2b5d6a91 5458 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5459 register_prefix, i.op[op].regs->reg_name,
5460 i.suffix);
5461 return 0;
5462 }
29b0f896
AM		 5463 }
5464 return 1;
5465}
252b5132 5466
29b0f896 5467static int
e3bb37b5 5468check_qword_reg (void)
29b0f896
AM		 5469{
5470 int op;
252b5132 5471
29b0f896
AM		 5472 for (op = i.operands; --op >= 0; )
5473 /* Reject eight bit registers, except where the template requires
5474 them. (eg. movzb) */
40fb9820
L		 5475 if (i.types[op].bitfield.reg8
5476 && (i.tm.operand_types[op].bitfield.reg16
5477 || i.tm.operand_types[op].bitfield.reg32
5478 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5479 {
a540244d
L		 5480 as_bad (_("`%s%s' not allowed with `%s%c'"),
5481 register_prefix,
29b0f896
AM		 5482 i.op[op].regs->reg_name,
5483 i.tm.name,
5484 i.suffix);
5485 return 0;
5486 }
e4630f71 5487 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5488 else if ((i.types[op].bitfield.reg16
5489 || i.types[op].bitfield.reg32)
5490 && (i.tm.operand_types[op].bitfield.reg32
5491 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5492 {
5493 /* Prohibit these changes in the 64bit mode, since the
5494 lowering is more complicated. */
34828aad 5495 if (intel_syntax
ca61edf2 5496 && i.tm.opcode_modifier.todword
40fb9820 5497 && !i.types[0].bitfield.regxmm)
34828aad 5498 {
ca61edf2 5499 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5500 i.suffix = LONG_MNEM_SUFFIX;
5501 }
5502 else
5503 {
2b5d6a91 5504 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5505 register_prefix, i.op[op].regs->reg_name,
5506 i.suffix);
5507 return 0;
5508 }
252b5132 5509 }
29b0f896
AM		 5510 return 1;
5511}
252b5132 5512
29b0f896 5513static int
e3bb37b5 5514check_word_reg (void)
29b0f896
AM		 5515{
5516 int op;
5517 for (op = i.operands; --op >= 0;)
5518 /* Reject eight bit registers, except where the template requires
5519 them. (eg. movzb) */
40fb9820
L		 5520 if (i.types[op].bitfield.reg8
5521 && (i.tm.operand_types[op].bitfield.reg16
5522 || i.tm.operand_types[op].bitfield.reg32
5523 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5524 {
a540244d
L		 5525 as_bad (_("`%s%s' not allowed with `%s%c'"),
5526 register_prefix,
29b0f896
AM		 5527 i.op[op].regs->reg_name,
5528 i.tm.name,
5529 i.suffix);
5530 return 0;
5531 }
e4630f71 5532 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5533 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5534 && (i.types[op].bitfield.reg32
5535 || i.types[op].bitfield.reg64)
40fb9820
L		 5536 && (i.tm.operand_types[op].bitfield.reg16
5537 || i.tm.operand_types[op].bitfield.acc))
252b5132 5538 {
29b0f896
AM		 5539 /* Prohibit these changes in the 64bit mode, since the
5540 lowering is more complicated. */
5541 if (flag_code == CODE_64BIT)
252b5132 5542 {
2b5d6a91 5543 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5544 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5545 i.suffix);
5546 return 0;
252b5132 5547 }
29b0f896 5548#if REGISTER_WARNINGS
cecf1424
JB		 5549 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5550 register_prefix,
5551 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5552 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5553#endif
5554 }
5555 return 1;
5556}
252b5132 5557
29b0f896 5558static int
40fb9820 5559update_imm (unsigned int j)
29b0f896 5560{
bc0844ae 5561 i386_operand_type overlap = i.types[j];
40fb9820
L		 5562 if ((overlap.bitfield.imm8
5563 || overlap.bitfield.imm8s
5564 || overlap.bitfield.imm16
5565 || overlap.bitfield.imm32
5566 || overlap.bitfield.imm32s
5567 || overlap.bitfield.imm64)
0dfbf9d7
L		 5568 && !operand_type_equal (&overlap, &imm8)
5569 && !operand_type_equal (&overlap, &imm8s)
5570 && !operand_type_equal (&overlap, &imm16)
5571 && !operand_type_equal (&overlap, &imm32)
5572 && !operand_type_equal (&overlap, &imm32s)
5573 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5574 {
5575 if (i.suffix)
5576 {
40fb9820
L		 5577 i386_operand_type temp;
5578
0dfbf9d7 5579 operand_type_set (&temp, 0);
7ab9ffdd 5580 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5581 {
5582 temp.bitfield.imm8 = overlap.bitfield.imm8;
5583 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5584 }
5585 else if (i.suffix == WORD_MNEM_SUFFIX)
5586 temp.bitfield.imm16 = overlap.bitfield.imm16;
5587 else if (i.suffix == QWORD_MNEM_SUFFIX)
5588 {
5589 temp.bitfield.imm64 = overlap.bitfield.imm64;
5590 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5591 }
5592 else
5593 temp.bitfield.imm32 = overlap.bitfield.imm32;
5594 overlap = temp;
29b0f896 5595 }
0dfbf9d7
L		 5596 else if (operand_type_equal (&overlap, &imm16_32_32s)
5597 || operand_type_equal (&overlap, &imm16_32)
5598 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5599 {
40fb9820 5600 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5601 overlap = imm16;
40fb9820 5602 else
65da13b5 5603 overlap = imm32s;
29b0f896 5604 }
0dfbf9d7
L		 5605 if (!operand_type_equal (&overlap, &imm8)
5606 && !operand_type_equal (&overlap, &imm8s)
5607 && !operand_type_equal (&overlap, &imm16)
5608 && !operand_type_equal (&overlap, &imm32)
5609 && !operand_type_equal (&overlap, &imm32s)
5610 && !operand_type_equal (&overlap, &imm64))
29b0f896 5611 {
4eed87de
AM		 5612 as_bad (_("no instruction mnemonic suffix given; "
5613 "can't determine immediate size"));
29b0f896
AM		 5614 return 0;
5615 }
5616 }
40fb9820 5617 i.types[j] = overlap;
29b0f896 5618
40fb9820
L		 5619 return 1;
5620}
5621
5622static int
5623finalize_imm (void)
5624{
bc0844ae 5625 unsigned int j, n;
29b0f896 5626
bc0844ae
L		 5627 /* Update the first 2 immediate operands. */
5628 n = i.operands > 2 ? 2 : i.operands;
5629 if (n)
5630 {
5631 for (j = 0; j < n; j++)
5632 if (update_imm (j) == 0)
5633 return 0;
40fb9820 5634
bc0844ae
L		 5635 /* The 3rd operand can't be immediate operand. */
5636 gas_assert (operand_type_check (i.types[2], imm) == 0);
5637 }
29b0f896
AM		 5638
5639 return 1;
5640}
5641
c0f3af97
L		 5642static int
5643bad_implicit_operand (int xmm)
5644{
91d6fa6a
NC		 5645 const char *ireg = xmm ? "xmm0" : "ymm0";
5646
c0f3af97
L		 5647 if (intel_syntax)
5648 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5649 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5650 else
5651 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5652 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5653 return 0;
5654}
5655
29b0f896 5656static int
e3bb37b5 5657process_operands (void)
29b0f896
AM		 5658{
5659 /* Default segment register this instruction will use for memory
5660 accesses. 0 means unknown. This is only for optimizing out
5661 unnecessary segment overrides. */
5662 const seg_entry *default_seg = 0;
5663
2426c15f 5664 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5665 {
91d6fa6a
NC		 5666 unsigned int dupl = i.operands;
5667 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5668 unsigned int j;
5669
c0f3af97 5670 /* The destination must be an xmm register. */
9c2799c2 5671 gas_assert (i.reg_operands
91d6fa6a 5672 && MAX_OPERANDS > dupl
7ab9ffdd 5673 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5674
5675 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5676 {
c0f3af97 5677 /* The first operand is implicit and must be xmm0. */
9c2799c2 5678 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5679 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5680 return bad_implicit_operand (1);
5681
8cd7925b 5682 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5683 {
5684 /* Keep xmm0 for instructions with VEX prefix and 3
5685 sources. */
5686 goto duplicate;
5687 }
e2ec9d29 5688 else
c0f3af97
L		 5689 {
5690 /* We remove the first xmm0 and keep the number of
5691 operands unchanged, which in fact duplicates the
5692 destination. */
5693 for (j = 1; j < i.operands; j++)
5694 {
5695 i.op[j - 1] = i.op[j];
5696 i.types[j - 1] = i.types[j];
5697 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5698 }
5699 }
5700 }
5701 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5702 {
91d6fa6a 5703 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5704 && (i.tm.opcode_modifier.vexsources
5705 == VEX3SOURCES));
c0f3af97
L		 5706
5707 /* Add the implicit xmm0 for instructions with VEX prefix
5708 and 3 sources. */
5709 for (j = i.operands; j > 0; j--)
5710 {
5711 i.op[j] = i.op[j - 1];
5712 i.types[j] = i.types[j - 1];
5713 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5714 }
5715 i.op[0].regs
5716 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5717 i.types[0] = regxmm;
c0f3af97
L		 5718 i.tm.operand_types[0] = regxmm;
5719
5720 i.operands += 2;
5721 i.reg_operands += 2;
5722 i.tm.operands += 2;
5723
91d6fa6a 5724 dupl++;
c0f3af97 5725 dest++;
91d6fa6a
NC		 5726 i.op[dupl] = i.op[dest];
5727 i.types[dupl] = i.types[dest];
5728 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5729 }
c0f3af97
L		 5730 else
5731 {
5732duplicate:
5733 i.operands++;
5734 i.reg_operands++;
5735 i.tm.operands++;
5736
91d6fa6a
NC		 5737 i.op[dupl] = i.op[dest];
5738 i.types[dupl] = i.types[dest];
5739 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5740 }
5741
5742 if (i.tm.opcode_modifier.immext)
5743 process_immext ();
5744 }
5745 else if (i.tm.opcode_modifier.firstxmm0)
5746 {
5747 unsigned int j;
5748
43234a1e 5749 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5750 gas_assert (i.reg_operands
7ab9ffdd 5751 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5752 || operand_type_equal (&i.types[0], &regymm)
5753 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5754 if (register_number (i.op[0].regs) != 0)
c0f3af97 5755 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5756
5757 for (j = 1; j < i.operands; j++)
5758 {
5759 i.op[j - 1] = i.op[j];
5760 i.types[j - 1] = i.types[j];
5761
5762 /* We need to adjust fields in i.tm since they are used by
5763 build_modrm_byte. */
5764 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5765 }
5766
e2ec9d29
L		 5767 i.operands--;
5768 i.reg_operands--;
e2ec9d29
L		 5769 i.tm.operands--;
5770 }
5771 else if (i.tm.opcode_modifier.regkludge)
5772 {
5773 /* The imul $imm, %reg instruction is converted into
5774 imul $imm, %reg, %reg, and the clr %reg instruction
5775 is converted into xor %reg, %reg. */
5776
5777 unsigned int first_reg_op;
5778
5779 if (operand_type_check (i.types[0], reg))
5780 first_reg_op = 0;
5781 else
5782 first_reg_op = 1;
5783 /* Pretend we saw the extra register operand. */
9c2799c2 5784 gas_assert (i.reg_operands == 1
7ab9ffdd 5785 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5786 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5787 i.types[first_reg_op + 1] = i.types[first_reg_op];
5788 i.operands++;
5789 i.reg_operands++;
29b0f896
AM		 5790 }
5791
40fb9820 5792 if (i.tm.opcode_modifier.shortform)
29b0f896 5793 {
40fb9820
L		 5794 if (i.types[0].bitfield.sreg2
5795 || i.types[0].bitfield.sreg3)
29b0f896 5796 {
4eed87de
AM		 5797 if (i.tm.base_opcode == POP_SEG_SHORT
5798 && i.op[0].regs->reg_num == 1)
29b0f896 5799 {
a87af027 5800 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5801 return 0;
29b0f896 5802 }
4eed87de
AM		 5803 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5804 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5805 i.rex |= REX_B;
4eed87de
AM		 5806 }
5807 else
5808 {
7ab9ffdd 5809 /* The register or float register operand is in operand
85f10a01 5810 0 or 1. */
40fb9820 5811 unsigned int op;
7ab9ffdd
L		 5812
5813 if (i.types[0].bitfield.floatreg
5814 || operand_type_check (i.types[0], reg))
5815 op = 0;
5816 else
5817 op = 1;
4eed87de
AM		 5818 /* Register goes in low 3 bits of opcode. */
5819 i.tm.base_opcode |= i.op[op].regs->reg_num;
5820 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5821 i.rex |= REX_B;
40fb9820 5822 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5823 {
4eed87de
AM		 5824 /* Warn about some common errors, but press on regardless.
5825 The first case can be generated by gcc (<= 2.8.1). */
5826 if (i.operands == 2)
5827 {
5828 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5829 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5830 register_prefix, i.op[!intel_syntax].regs->reg_name,
5831 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5832 }
5833 else
5834 {
5835 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5836 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5837 register_prefix, i.op[0].regs->reg_name);
4eed87de 5838 }
29b0f896
AM		 5839 }
5840 }
5841 }
40fb9820 5842 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5843 {
5844 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5845 must be put into the modrm byte). Now, we make the modrm and
5846 index base bytes based on all the info we've collected. */
29b0f896
AM		 5847
5848 default_seg = build_modrm_byte ();
5849 }
8a2ed489 5850 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5851 {
5852 default_seg = &ds;
5853 }
40fb9820 5854 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5855 {
5856 /* For the string instructions that allow a segment override
5857 on one of their operands, the default segment is ds. */
5858 default_seg = &ds;
5859 }
5860
75178d9d
L		 5861 if (i.tm.base_opcode == 0x8d /* lea */
5862 && i.seg[0]
5863 && !quiet_warnings)
30123838 5864 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5865
5866 /* If a segment was explicitly specified, and the specified segment
5867 is not the default, use an opcode prefix to select it. If we
5868 never figured out what the default segment is, then default_seg
5869 will be zero at this point, and the specified segment prefix will
5870 always be used. */
29b0f896
AM		 5871 if ((i.seg[0]) && (i.seg[0] != default_seg))
5872 {
5873 if (!add_prefix (i.seg[0]->seg_prefix))
5874 return 0;
5875 }
5876 return 1;
5877}
5878
5879static const seg_entry *
e3bb37b5 5880build_modrm_byte (void)
29b0f896
AM		 5881{
5882 const seg_entry *default_seg = 0;
c0f3af97 5883 unsigned int source, dest;
8cd7925b 5884 int vex_3_sources;
c0f3af97
L		 5885
5886 /* The first operand of instructions with VEX prefix and 3 sources
5887 must be VEX_Imm4. */
8cd7925b 5888 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5889 if (vex_3_sources)
5890 {
91d6fa6a 5891 unsigned int nds, reg_slot;
4c2c6516 5892 expressionS *exp;
c0f3af97 5893
922d8de8 5894 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5895 && i.tm.opcode_modifier.immext)
5896 {
5897 dest = i.operands - 2;
5898 gas_assert (dest == 3);
5899 }
922d8de8 5900 else
a683cc34 5901 dest = i.operands - 1;
c0f3af97 5902 nds = dest - 1;
922d8de8 5903
a683cc34
SP		 5904 /* There are 2 kinds of instructions:
5905 1. 5 operands: 4 register operands or 3 register operands
5906 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 5907 VexW0 or VexW1. The destination must be either XMM, YMM or
5908 ZMM register.
a683cc34
SP		 5909 2. 4 operands: 4 register operands or 3 register operands
5910 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5911 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5912 || (i.reg_operands == 3 && i.mem_operands == 1))
5913 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5914 && (i.tm.opcode_modifier.veximmext
5915 || (i.imm_operands == 1
5916 && i.types[0].bitfield.vec_imm4
5917 && (i.tm.opcode_modifier.vexw == VEXW0
5918 || i.tm.opcode_modifier.vexw == VEXW1)
5919 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 5920 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
5921 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 5922
5923 if (i.imm_operands == 0)
5924 {
5925 /* When there is no immediate operand, generate an 8bit
5926 immediate operand to encode the first operand. */
5927 exp = &im_expressions[i.imm_operands++];
5928 i.op[i.operands].imms = exp;
5929 i.types[i.operands] = imm8;
5930 i.operands++;
5931 /* If VexW1 is set, the first operand is the source and
5932 the second operand is encoded in the immediate operand. */
5933 if (i.tm.opcode_modifier.vexw == VEXW1)
5934 {
5935 source = 0;
5936 reg_slot = 1;
5937 }
5938 else
5939 {
5940 source = 1;
5941 reg_slot = 0;
5942 }
5943
5944 /* FMA swaps REG and NDS. */
5945 if (i.tm.cpu_flags.bitfield.cpufma)
5946 {
5947 unsigned int tmp;
5948 tmp = reg_slot;
5949 reg_slot = nds;
5950 nds = tmp;
5951 }
5952
24981e7b
L		 5953 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5954 &regxmm)
a683cc34 5955 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 5956 &regymm)
5957 || operand_type_equal (&i.tm.operand_types[reg_slot],
5958 &regzmm));
a683cc34 5959 exp->X_op = O_constant;
4c692bc7 5960 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 5961 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
5962 }
922d8de8 5963 else
a683cc34
SP		 5964 {
5965 unsigned int imm_slot;
5966
5967 if (i.tm.opcode_modifier.vexw == VEXW0)
5968 {
5969 /* If VexW0 is set, the third operand is the source and
5970 the second operand is encoded in the immediate
5971 operand. */
5972 source = 2;
5973 reg_slot = 1;
5974 }
5975 else
5976 {
5977 /* VexW1 is set, the second operand is the source and
5978 the third operand is encoded in the immediate
5979 operand. */
5980 source = 1;
5981 reg_slot = 2;
5982 }
5983
5984 if (i.tm.opcode_modifier.immext)
5985 {
5986 /* When ImmExt is set, the immdiate byte is the last
5987 operand. */
5988 imm_slot = i.operands - 1;
5989 source--;
5990 reg_slot--;
5991 }
5992 else
5993 {
5994 imm_slot = 0;
5995
5996 /* Turn on Imm8 so that output_imm will generate it. */
5997 i.types[imm_slot].bitfield.imm8 = 1;
5998 }
5999
24981e7b
L		 6000 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6001 &regxmm)
6002 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6003 &regymm)
6004 || operand_type_equal (&i.tm.operand_types[reg_slot],
6005 &regzmm));
a683cc34 6006 i.op[imm_slot].imms->X_add_number
4c692bc7 6007 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6008 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6009 }
6010
6011 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6012 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6013 &regymm)
6014 || operand_type_equal (&i.tm.operand_types[nds],
6015 &regzmm));
dae39acc 6016 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6017 }
6018 else
6019 source = dest = 0;
29b0f896
AM		 6020
6021 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6022 implicit registers do not count. If there are 3 register
6023 operands, it must be a instruction with VexNDS. For a
6024 instruction with VexNDD, the destination register is encoded
6025 in VEX prefix. If there are 4 register operands, it must be
6026 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6027 if (i.mem_operands == 0
6028 && ((i.reg_operands == 2
2426c15f 6029 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6030 || (i.reg_operands == 3
2426c15f 6031 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6032 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6033 {
cab737b9
L		 6034 switch (i.operands)
6035 {
6036 case 2:
6037 source = 0;
6038 break;
6039 case 3:
c81128dc
L		 6040 /* When there are 3 operands, one of them may be immediate,
6041 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6042 the first operand must be shift count register (cl) or it
6043 is an instruction with VexNDS. */
9c2799c2 6044 gas_assert (i.imm_operands == 1
7ab9ffdd 6045 || (i.imm_operands == 0
2426c15f 6046 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6047 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6048 if (operand_type_check (i.types[0], imm)
6049 || i.types[0].bitfield.shiftcount)
6050 source = 1;
6051 else
6052 source = 0;
cab737b9
L		 6053 break;
6054 case 4:
368d64cc
L		 6055 /* When there are 4 operands, the first two must be 8bit
6056 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6057 one.
6058
6059 For instructions with VexNDS, if the first operand
6060 an imm8, the source operand is the 2nd one. If the last
6061 operand is imm8, the source operand is the first one. */
9c2799c2 6062 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6063 && i.types[0].bitfield.imm8
6064 && i.types[1].bitfield.imm8)
2426c15f 6065 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6066 && i.imm_operands == 1
6067 && (i.types[0].bitfield.imm8
43234a1e
L		 6068 || i.types[i.operands - 1].bitfield.imm8
6069 || i.rounding)));
9f2670f2
L		 6070 if (i.imm_operands == 2)
6071 source = 2;
6072 else
c0f3af97
L		 6073 {
6074 if (i.types[0].bitfield.imm8)
6075 source = 1;
6076 else
6077 source = 0;
6078 }
c0f3af97
L		 6079 break;
6080 case 5:
43234a1e
L		 6081 if (i.tm.opcode_modifier.evex)
6082 {
6083 /* For EVEX instructions, when there are 5 operands, the
6084 first one must be immediate operand. If the second one
6085 is immediate operand, the source operand is the 3th
6086 one. If the last one is immediate operand, the source
6087 operand is the 2nd one. */
6088 gas_assert (i.imm_operands == 2
6089 && i.tm.opcode_modifier.sae
6090 && operand_type_check (i.types[0], imm));
6091 if (operand_type_check (i.types[1], imm))
6092 source = 2;
6093 else if (operand_type_check (i.types[4], imm))
6094 source = 1;
6095 else
6096 abort ();
6097 }
cab737b9
L		 6098 break;
6099 default:
6100 abort ();
6101 }
6102
c0f3af97
L		 6103 if (!vex_3_sources)
6104 {
6105 dest = source + 1;
6106
43234a1e
L		 6107 /* RC/SAE operand could be between DEST and SRC. That happens
6108 when one operand is GPR and the other one is XMM/YMM/ZMM
6109 register. */
6110 if (i.rounding && i.rounding->operand == (int) dest)
6111 dest++;
6112
2426c15f 6113 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6114 {
43234a1e
L		 6115 /* For instructions with VexNDS, the register-only source
6116 operand must be 32/64bit integer, XMM, YMM or ZMM
6117 register. It is encoded in VEX prefix. We need to
6118 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6119
6120 i386_operand_type op;
6121 unsigned int vvvv;
6122
6123 /* Check register-only source operand when two source
6124 operands are swapped. */
6125 if (!i.tm.operand_types[source].bitfield.baseindex
6126 && i.tm.operand_types[dest].bitfield.baseindex)
6127 {
6128 vvvv = source;
6129 source = dest;
6130 }
6131 else
6132 vvvv = dest;
6133
6134 op = i.tm.operand_types[vvvv];
fa99fab2 6135 op.bitfield.regmem = 0;
c0f3af97 6136 if ((dest + 1) >= i.operands
f12dc422
L		 6137 || (op.bitfield.reg32 != 1
6138 && !op.bitfield.reg64 != 1
6139 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6140 && !operand_type_equal (&op, &regymm)
6141 && !operand_type_equal (&op, &regzmm)
6142 && !operand_type_equal (&op, &regmask)))
c0f3af97 6143 abort ();
f12dc422 6144 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6145 dest++;
6146 }
6147 }
29b0f896
AM		 6148
6149 i.rm.mode = 3;
6150 /* One of the register operands will be encoded in the i.tm.reg
6151 field, the other in the combined i.tm.mode and i.tm.regmem
6152 fields. If no form of this instruction supports a memory
6153 destination operand, then we assume the source operand may
6154 sometimes be a memory operand and so we need to store the
6155 destination in the i.rm.reg field. */
40fb9820
L		 6156 if (!i.tm.operand_types[dest].bitfield.regmem
6157 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6158 {
6159 i.rm.reg = i.op[dest].regs->reg_num;
6160 i.rm.regmem = i.op[source].regs->reg_num;
6161 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6162 i.rex |= REX_R;
43234a1e
L		 6163 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6164 i.vrex |= REX_R;
29b0f896 6165 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6166 i.rex |= REX_B;
43234a1e
L		 6167 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6168 i.vrex |= REX_B;
29b0f896
AM		 6169 }
6170 else
6171 {
6172 i.rm.reg = i.op[source].regs->reg_num;
6173 i.rm.regmem = i.op[dest].regs->reg_num;
6174 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6175 i.rex |= REX_B;
43234a1e
L		 6176 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6177 i.vrex |= REX_B;
29b0f896 6178 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6179 i.rex |= REX_R;
43234a1e
L		 6180 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6181 i.vrex |= REX_R;
29b0f896 6182 }
161a04f6 6183 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6184 {
40fb9820
L		 6185 if (!i.types[0].bitfield.control
6186 && !i.types[1].bitfield.control)
c4a530c5 6187 abort ();
161a04f6 6188 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6189 add_prefix (LOCK_PREFIX_OPCODE);
6190 }
29b0f896
AM		 6191 }
6192 else
6193 { /* If it's not 2 reg operands... */
c0f3af97
L		 6194 unsigned int mem;
6195
29b0f896
AM		 6196 if (i.mem_operands)
6197 {
6198 unsigned int fake_zero_displacement = 0;
99018f42 6199 unsigned int op;
4eed87de 6200
7ab9ffdd
L		 6201 for (op = 0; op < i.operands; op++)
6202 if (operand_type_check (i.types[op], anymem))
6203 break;
7ab9ffdd 6204 gas_assert (op < i.operands);
29b0f896 6205
6c30d220
L		 6206 if (i.tm.opcode_modifier.vecsib)
6207 {
6208 if (i.index_reg->reg_num == RegEiz
6209 || i.index_reg->reg_num == RegRiz)
6210 abort ();
6211
6212 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6213 if (!i.base_reg)
6214 {
6215 i.sib.base = NO_BASE_REGISTER;
6216 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6217 /* No Vec_Disp8 if there is no base. */
6218 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6219 i.types[op].bitfield.disp8 = 0;
6220 i.types[op].bitfield.disp16 = 0;
6221 i.types[op].bitfield.disp64 = 0;
6222 if (flag_code != CODE_64BIT)
6223 {
6224 /* Must be 32 bit */
6225 i.types[op].bitfield.disp32 = 1;
6226 i.types[op].bitfield.disp32s = 0;
6227 }
6228 else
6229 {
6230 i.types[op].bitfield.disp32 = 0;
6231 i.types[op].bitfield.disp32s = 1;
6232 }
6233 }
6234 i.sib.index = i.index_reg->reg_num;
6235 if ((i.index_reg->reg_flags & RegRex) != 0)
6236 i.rex |= REX_X;
43234a1e
L		 6237 if ((i.index_reg->reg_flags & RegVRex) != 0)
6238 i.vrex |= REX_X;
6c30d220
L		 6239 }
6240
29b0f896
AM		 6241 default_seg = &ds;
6242
6243 if (i.base_reg == 0)
6244 {
6245 i.rm.mode = 0;
6246 if (!i.disp_operands)
6c30d220
L		 6247 {
6248 fake_zero_displacement = 1;
6249 /* Instructions with VSIB byte need 32bit displacement
6250 if there is no base register. */
6251 if (i.tm.opcode_modifier.vecsib)
6252 i.types[op].bitfield.disp32 = 1;
6253 }
29b0f896
AM		 6254 if (i.index_reg == 0)
6255 {
6c30d220 6256 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6257 /* Operand is just <disp> */
20f0a1fc 6258 if (flag_code == CODE_64BIT)
29b0f896
AM		 6259 {
6260 /* 64bit mode overwrites the 32bit absolute
6261 addressing by RIP relative addressing and
6262 absolute addressing is encoded by one of the
6263 redundant SIB forms. */
6264 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6265 i.sib.base = NO_BASE_REGISTER;
6266 i.sib.index = NO_INDEX_REGISTER;
fc225355 6267 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6268 ? disp32s : disp32);
20f0a1fc 6269 }
fc225355
L		 6270 else if ((flag_code == CODE_16BIT)
6271 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6272 {
6273 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6274 i.types[op] = disp16;
20f0a1fc
NC		 6275 }
6276 else
6277 {
6278 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6279 i.types[op] = disp32;
29b0f896
AM		 6280 }
6281 }
6c30d220 6282 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6283 {
6c30d220 6284 /* !i.base_reg && i.index_reg */
db51cc60
L		 6285 if (i.index_reg->reg_num == RegEiz
6286 || i.index_reg->reg_num == RegRiz)
6287 i.sib.index = NO_INDEX_REGISTER;
6288 else
6289 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6290 i.sib.base = NO_BASE_REGISTER;
6291 i.sib.scale = i.log2_scale_factor;
6292 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6293 /* No Vec_Disp8 if there is no base. */
6294 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6295 i.types[op].bitfield.disp8 = 0;
6296 i.types[op].bitfield.disp16 = 0;
6297 i.types[op].bitfield.disp64 = 0;
29b0f896 6298 if (flag_code != CODE_64BIT)
40fb9820
L		 6299 {
6300 /* Must be 32 bit */
6301 i.types[op].bitfield.disp32 = 1;
6302 i.types[op].bitfield.disp32s = 0;
6303 }
29b0f896 6304 else
40fb9820
L		 6305 {
6306 i.types[op].bitfield.disp32 = 0;
6307 i.types[op].bitfield.disp32s = 1;
6308 }
29b0f896 6309 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6310 i.rex |= REX_X;
29b0f896
AM		 6311 }
6312 }
6313 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6314 else if (i.base_reg->reg_num == RegRip ||
6315 i.base_reg->reg_num == RegEip)
29b0f896 6316 {
6c30d220 6317 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6318 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6319 i.types[op].bitfield.disp8 = 0;
6320 i.types[op].bitfield.disp16 = 0;
6321 i.types[op].bitfield.disp32 = 0;
6322 i.types[op].bitfield.disp32s = 1;
6323 i.types[op].bitfield.disp64 = 0;
43234a1e 6324 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6325 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6326 if (! i.disp_operands)
6327 fake_zero_displacement = 1;
29b0f896 6328 }
40fb9820 6329 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6330 {
6c30d220 6331 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6332 switch (i.base_reg->reg_num)
6333 {
6334 case 3: /* (%bx) */
6335 if (i.index_reg == 0)
6336 i.rm.regmem = 7;
6337 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6338 i.rm.regmem = i.index_reg->reg_num - 6;
6339 break;
6340 case 5: /* (%bp) */
6341 default_seg = &ss;
6342 if (i.index_reg == 0)
6343 {
6344 i.rm.regmem = 6;
40fb9820 6345 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6346 {
6347 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6348 if (i.tm.operand_types[op].bitfield.vec_disp8)
6349 i.types[op].bitfield.vec_disp8 = 1;
6350 else
6351 i.types[op].bitfield.disp8 = 1;
252b5132 6352 fake_zero_displacement = 1;
29b0f896
AM		 6353 }
6354 }
6355 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6356 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6357 break;
6358 default: /* (%si) -> 4 or (%di) -> 5 */
6359 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6360 }
6361 i.rm.mode = mode_from_disp_size (i.types[op]);
6362 }
6363 else /* i.base_reg and 32/64 bit mode */
6364 {
6365 if (flag_code == CODE_64BIT
40fb9820
L		 6366 && operand_type_check (i.types[op], disp))
6367 {
6368 i386_operand_type temp;
0dfbf9d7 6369 operand_type_set (&temp, 0);
40fb9820 6370 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6371 temp.bitfield.vec_disp8
6372 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6373 i.types[op] = temp;
6374 if (i.prefix[ADDR_PREFIX] == 0)
6375 i.types[op].bitfield.disp32s = 1;
6376 else
6377 i.types[op].bitfield.disp32 = 1;
6378 }
20f0a1fc 6379
6c30d220
L		 6380 if (!i.tm.opcode_modifier.vecsib)
6381 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6382 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6383 i.rex |= REX_B;
29b0f896
AM		 6384 i.sib.base = i.base_reg->reg_num;
6385 /* x86-64 ignores REX prefix bit here to avoid decoder
6386 complications. */
848930b2
JB		 6387 if (!(i.base_reg->reg_flags & RegRex)
6388 && (i.base_reg->reg_num == EBP_REG_NUM
6389 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6390 default_seg = &ss;
848930b2 6391 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6392 {
848930b2 6393 fake_zero_displacement = 1;
43234a1e
L		 6394 if (i.tm.operand_types [op].bitfield.vec_disp8)
6395 i.types[op].bitfield.vec_disp8 = 1;
6396 else
6397 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6398 }
6399 i.sib.scale = i.log2_scale_factor;
6400 if (i.index_reg == 0)
6401 {
6c30d220 6402 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6403 /* <disp>(%esp) becomes two byte modrm with no index
6404 register. We've already stored the code for esp
6405 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6406 Any base register besides %esp will not use the
6407 extra modrm byte. */
6408 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6409 }
6c30d220 6410 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6411 {
db51cc60
L		 6412 if (i.index_reg->reg_num == RegEiz
6413 || i.index_reg->reg_num == RegRiz)
6414 i.sib.index = NO_INDEX_REGISTER;
6415 else
6416 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6417 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6418 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6419 i.rex |= REX_X;
29b0f896 6420 }
67a4f2b7
AO		 6421
6422 if (i.disp_operands
6423 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6424 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6425 i.rm.mode = 0;
6426 else
a501d77e
L		 6427 {
6428 if (!fake_zero_displacement
6429 && !i.disp_operands
6430 && i.disp_encoding)
6431 {
6432 fake_zero_displacement = 1;
6433 if (i.disp_encoding == disp_encoding_8bit)
6434 i.types[op].bitfield.disp8 = 1;
6435 else
6436 i.types[op].bitfield.disp32 = 1;
6437 }
6438 i.rm.mode = mode_from_disp_size (i.types[op]);
6439 }
29b0f896 6440 }
252b5132 6441
29b0f896
AM		 6442 if (fake_zero_displacement)
6443 {
6444 /* Fakes a zero displacement assuming that i.types[op]
6445 holds the correct displacement size. */
6446 expressionS *exp;
6447
9c2799c2 6448 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6449 exp = &disp_expressions[i.disp_operands++];
6450 i.op[op].disps = exp;
6451 exp->X_op = O_constant;
6452 exp->X_add_number = 0;
6453 exp->X_add_symbol = (symbolS *) 0;
6454 exp->X_op_symbol = (symbolS *) 0;
6455 }
c0f3af97
L		 6456
6457 mem = op;
29b0f896 6458 }
c0f3af97
L		 6459 else
6460 mem = ~0;
252b5132 6461
8c43a48b 6462 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6463 {
6464 if (operand_type_check (i.types[0], imm))
6465 i.vex.register_specifier = NULL;
6466 else
6467 {
6468 /* VEX.vvvv encodes one of the sources when the first
6469 operand is not an immediate. */
1ef99a7b 6470 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6471 i.vex.register_specifier = i.op[0].regs;
6472 else
6473 i.vex.register_specifier = i.op[1].regs;
6474 }
6475
6476 /* Destination is a XMM register encoded in the ModRM.reg
6477 and VEX.R bit. */
6478 i.rm.reg = i.op[2].regs->reg_num;
6479 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6480 i.rex |= REX_R;
6481
6482 /* ModRM.rm and VEX.B encodes the other source. */
6483 if (!i.mem_operands)
6484 {
6485 i.rm.mode = 3;
6486
1ef99a7b 6487 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6488 i.rm.regmem = i.op[1].regs->reg_num;
6489 else
6490 i.rm.regmem = i.op[0].regs->reg_num;
6491
6492 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6493 i.rex |= REX_B;
6494 }
6495 }
2426c15f 6496 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6497 {
6498 i.vex.register_specifier = i.op[2].regs;
6499 if (!i.mem_operands)
6500 {
6501 i.rm.mode = 3;
6502 i.rm.regmem = i.op[1].regs->reg_num;
6503 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6504 i.rex |= REX_B;
6505 }
6506 }
29b0f896
AM		 6507 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6508 (if any) based on i.tm.extension_opcode. Again, we must be
6509 careful to make sure that segment/control/debug/test/MMX
6510 registers are coded into the i.rm.reg field. */
f88c9eb0 6511 else if (i.reg_operands)
29b0f896 6512 {
99018f42 6513 unsigned int op;
7ab9ffdd
L		 6514 unsigned int vex_reg = ~0;
6515
6516 for (op = 0; op < i.operands; op++)
6517 if (i.types[op].bitfield.reg8
6518 || i.types[op].bitfield.reg16
6519 || i.types[op].bitfield.reg32
6520 || i.types[op].bitfield.reg64
6521 || i.types[op].bitfield.regmmx
6522 || i.types[op].bitfield.regxmm
6523 || i.types[op].bitfield.regymm
7e8b059b 6524 || i.types[op].bitfield.regbnd
43234a1e
L		 6525 || i.types[op].bitfield.regzmm
6526 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6527 || i.types[op].bitfield.sreg2
6528 || i.types[op].bitfield.sreg3
6529 || i.types[op].bitfield.control
6530 || i.types[op].bitfield.debug
6531 || i.types[op].bitfield.test)
6532 break;
c0209578 6533
7ab9ffdd
L		 6534 if (vex_3_sources)
6535 op = dest;
2426c15f 6536 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6537 {
6538 /* For instructions with VexNDS, the register-only
6539 source operand is encoded in VEX prefix. */
6540 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6541
7ab9ffdd 6542 if (op > mem)
c0f3af97 6543 {
7ab9ffdd
L		 6544 vex_reg = op++;
6545 gas_assert (op < i.operands);
c0f3af97
L		 6546 }
6547 else
c0f3af97 6548 {
f12dc422
L		 6549 /* Check register-only source operand when two source
6550 operands are swapped. */
6551 if (!i.tm.operand_types[op].bitfield.baseindex
6552 && i.tm.operand_types[op + 1].bitfield.baseindex)
6553 {
6554 vex_reg = op;
6555 op += 2;
6556 gas_assert (mem == (vex_reg + 1)
6557 && op < i.operands);
6558 }
6559 else
6560 {
6561 vex_reg = op + 1;
6562 gas_assert (vex_reg < i.operands);
6563 }
c0f3af97 6564 }
7ab9ffdd 6565 }
2426c15f 6566 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6567 {
f12dc422 6568 /* For instructions with VexNDD, the register destination
7ab9ffdd 6569 is encoded in VEX prefix. */
f12dc422
L		 6570 if (i.mem_operands == 0)
6571 {
6572 /* There is no memory operand. */
6573 gas_assert ((op + 2) == i.operands);
6574 vex_reg = op + 1;
6575 }
6576 else
8d63c93e 6577 {
f12dc422
L		 6578 /* There are only 2 operands. */
6579 gas_assert (op < 2 && i.operands == 2);
6580 vex_reg = 1;
6581 }
7ab9ffdd
L		 6582 }
6583 else
6584 gas_assert (op < i.operands);
99018f42 6585
7ab9ffdd
L		 6586 if (vex_reg != (unsigned int) ~0)
6587 {
f12dc422 6588 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6589
f12dc422
L		 6590 if (type->bitfield.reg32 != 1
6591 && type->bitfield.reg64 != 1
6592 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6593 && !operand_type_equal (type, &regymm)
6594 && !operand_type_equal (type, &regzmm)
6595 && !operand_type_equal (type, &regmask))
7ab9ffdd 6596 abort ();
f88c9eb0 6597
7ab9ffdd
L		 6598 i.vex.register_specifier = i.op[vex_reg].regs;
6599 }
6600
1b9f0c97
L		 6601 /* Don't set OP operand twice. */
6602 if (vex_reg != op)
7ab9ffdd 6603 {
1b9f0c97
L		 6604 /* If there is an extension opcode to put here, the
6605 register number must be put into the regmem field. */
6606 if (i.tm.extension_opcode != None)
6607 {
6608 i.rm.regmem = i.op[op].regs->reg_num;
6609 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6610 i.rex |= REX_B;
43234a1e
L		 6611 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6612 i.vrex |= REX_B;
1b9f0c97
L		 6613 }
6614 else
6615 {
6616 i.rm.reg = i.op[op].regs->reg_num;
6617 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6618 i.rex |= REX_R;
43234a1e
L		 6619 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6620 i.vrex |= REX_R;
1b9f0c97 6621 }
7ab9ffdd 6622 }
252b5132 6623
29b0f896
AM		 6624 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6625 must set it to 3 to indicate this is a register operand
6626 in the regmem field. */
6627 if (!i.mem_operands)
6628 i.rm.mode = 3;
6629 }
252b5132 6630
29b0f896 6631 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6632 if (i.tm.extension_opcode != None)
29b0f896
AM		 6633 i.rm.reg = i.tm.extension_opcode;
6634 }
6635 return default_seg;
6636}
252b5132 6637
29b0f896 6638static void
e3bb37b5 6639output_branch (void)
29b0f896
AM		 6640{
6641 char *p;
f8a5c266 6642 int size;
29b0f896
AM		 6643 int code16;
6644 int prefix;
6645 relax_substateT subtype;
6646 symbolS *sym;
6647 offsetT off;
6648
f8a5c266 6649 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6650 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6651
6652 prefix = 0;
6653 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6654 {
29b0f896
AM		 6655 prefix = 1;
6656 i.prefixes -= 1;
6657 code16 ^= CODE16;
252b5132 6658 }
29b0f896
AM		 6659 /* Pentium4 branch hints. */
6660 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6661 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6662 {
29b0f896
AM		 6663 prefix++;
6664 i.prefixes--;
6665 }
6666 if (i.prefix[REX_PREFIX] != 0)
6667 {
6668 prefix++;
6669 i.prefixes--;
2f66722d
AM		 6670 }
6671
7e8b059b
L		 6672 /* BND prefixed jump. */
6673 if (i.prefix[BND_PREFIX] != 0)
6674 {
6675 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6676 i.prefixes -= 1;
6677 }
6678
29b0f896
AM		 6679 if (i.prefixes != 0 && !intel_syntax)
6680 as_warn (_("skipping prefixes on this instruction"));
6681
6682 /* It's always a symbol; End frag & setup for relax.
6683 Make sure there is enough room in this frag for the largest
6684 instruction we may generate in md_convert_frag. This is 2
6685 bytes for the opcode and room for the prefix and largest
6686 displacement. */
6687 frag_grow (prefix + 2 + 4);
6688 /* Prefix and 1 opcode byte go in fr_fix. */
6689 p = frag_more (prefix + 1);
6690 if (i.prefix[DATA_PREFIX] != 0)
6691 *p++ = DATA_PREFIX_OPCODE;
6692 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6693 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6694 *p++ = i.prefix[SEG_PREFIX];
6695 if (i.prefix[REX_PREFIX] != 0)
6696 *p++ = i.prefix[REX_PREFIX];
6697 *p = i.tm.base_opcode;
6698
6699 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6700 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6701 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6702 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6703 else
f8a5c266 6704 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6705 subtype |= code16;
3e73aa7c 6706
29b0f896
AM		 6707 sym = i.op[0].disps->X_add_symbol;
6708 off = i.op[0].disps->X_add_number;
3e73aa7c 6709
29b0f896
AM		 6710 if (i.op[0].disps->X_op != O_constant
6711 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6712 {
29b0f896
AM		 6713 /* Handle complex expressions. */
6714 sym = make_expr_symbol (i.op[0].disps);
6715 off = 0;
6716 }
3e73aa7c 6717
29b0f896
AM		 6718 /* 1 possible extra opcode + 4 byte displacement go in var part.
6719 Pass reloc in fr_var. */
c3320543
L		 6720 frag_var (rs_machine_dependent, 5,
6721 ((!object_64bit
6722 || i.reloc[0] != NO_RELOC
6723 || (i.bnd_prefix == NULL && !add_bnd_prefix))
6724 ? i.reloc[0]
6725 : BFD_RELOC_X86_64_PC32_BND),
6726 subtype, sym, off, p);
29b0f896 6727}
3e73aa7c 6728
29b0f896 6729static void
e3bb37b5 6730output_jump (void)
29b0f896
AM		 6731{
6732 char *p;
6733 int size;
3e02c1cc 6734 fixS *fixP;
29b0f896 6735
40fb9820 6736 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6737 {
6738 /* This is a loop or jecxz type instruction. */
6739 size = 1;
6740 if (i.prefix[ADDR_PREFIX] != 0)
6741 {
6742 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6743 i.prefixes -= 1;
6744 }
6745 /* Pentium4 branch hints. */
6746 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6747 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6748 {
6749 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6750 i.prefixes--;
3e73aa7c
JH		 6751 }
6752 }
29b0f896
AM		 6753 else
6754 {
6755 int code16;
3e73aa7c 6756
29b0f896
AM		 6757 code16 = 0;
6758 if (flag_code == CODE_16BIT)
6759 code16 = CODE16;
3e73aa7c 6760
29b0f896
AM		 6761 if (i.prefix[DATA_PREFIX] != 0)
6762 {
6763 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6764 i.prefixes -= 1;
6765 code16 ^= CODE16;
6766 }
252b5132 6767
29b0f896
AM		 6768 size = 4;
6769 if (code16)
6770 size = 2;
6771 }
9fcc94b6 6772
29b0f896
AM		 6773 if (i.prefix[REX_PREFIX] != 0)
6774 {
6775 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6776 i.prefixes -= 1;
6777 }
252b5132 6778
7e8b059b
L		 6779 /* BND prefixed jump. */
6780 if (i.prefix[BND_PREFIX] != 0)
6781 {
6782 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6783 i.prefixes -= 1;
6784 }
6785
29b0f896
AM		 6786 if (i.prefixes != 0 && !intel_syntax)
6787 as_warn (_("skipping prefixes on this instruction"));
e0890092 6788
42164a71
L		 6789 p = frag_more (i.tm.opcode_length + size);
6790 switch (i.tm.opcode_length)
6791 {
6792 case 2:
6793 *p++ = i.tm.base_opcode >> 8;
6794 case 1:
6795 *p++ = i.tm.base_opcode;
6796 break;
6797 default:
6798 abort ();
6799 }
e0890092 6800
3e02c1cc 6801 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
c3320543
L		 6802 i.op[0].disps, 1, reloc (size, 1, 1,
6803 (i.bnd_prefix != NULL
6804 || add_bnd_prefix),
6805 i.reloc[0]));
3e02c1cc
AM		 6806
6807 /* All jumps handled here are signed, but don't use a signed limit
6808 check for 32 and 16 bit jumps as we want to allow wrap around at
6809 4G and 64k respectively. */
6810 if (size == 1)
6811 fixP->fx_signed = 1;
29b0f896 6812}
e0890092 6813
29b0f896 6814static void
e3bb37b5 6815output_interseg_jump (void)
29b0f896
AM		 6816{
6817 char *p;
6818 int size;
6819 int prefix;
6820 int code16;
252b5132 6821
29b0f896
AM		 6822 code16 = 0;
6823 if (flag_code == CODE_16BIT)
6824 code16 = CODE16;
a217f122 6825
29b0f896
AM		 6826 prefix = 0;
6827 if (i.prefix[DATA_PREFIX] != 0)
6828 {
6829 prefix = 1;
6830 i.prefixes -= 1;
6831 code16 ^= CODE16;
6832 }
6833 if (i.prefix[REX_PREFIX] != 0)
6834 {
6835 prefix++;
6836 i.prefixes -= 1;
6837 }
252b5132 6838
29b0f896
AM		 6839 size = 4;
6840 if (code16)
6841 size = 2;
252b5132 6842
29b0f896
AM		 6843 if (i.prefixes != 0 && !intel_syntax)
6844 as_warn (_("skipping prefixes on this instruction"));
252b5132 6845
29b0f896
AM		 6846 /* 1 opcode; 2 segment; offset */
6847 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6848
29b0f896
AM		 6849 if (i.prefix[DATA_PREFIX] != 0)
6850 *p++ = DATA_PREFIX_OPCODE;
252b5132 6851
29b0f896
AM		 6852 if (i.prefix[REX_PREFIX] != 0)
6853 *p++ = i.prefix[REX_PREFIX];
252b5132 6854
29b0f896
AM		 6855 *p++ = i.tm.base_opcode;
6856 if (i.op[1].imms->X_op == O_constant)
6857 {
6858 offsetT n = i.op[1].imms->X_add_number;
252b5132 6859
29b0f896
AM		 6860 if (size == 2
6861 && !fits_in_unsigned_word (n)
6862 && !fits_in_signed_word (n))
6863 {
6864 as_bad (_("16-bit jump out of range"));
6865 return;
6866 }
6867 md_number_to_chars (p, n, size);
6868 }
6869 else
6870 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
c3320543 6871 i.op[1].imms, 0, reloc (size, 0, 0, 0, i.reloc[1]));
29b0f896
AM		 6872 if (i.op[0].imms->X_op != O_constant)
6873 as_bad (_("can't handle non absolute segment in `%s'"),
6874 i.tm.name);
6875 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6876}
a217f122 6877
29b0f896 6878static void
e3bb37b5 6879output_insn (void)
29b0f896 6880{
2bbd9c25
JJ		 6881 fragS *insn_start_frag;
6882 offsetT insn_start_off;
6883
29b0f896
AM		 6884 /* Tie dwarf2 debug info to the address at the start of the insn.
6885 We can't do this after the insn has been output as the current
6886 frag may have been closed off. eg. by frag_var. */
6887 dwarf2_emit_insn (0);
6888
2bbd9c25
JJ		 6889 insn_start_frag = frag_now;
6890 insn_start_off = frag_now_fix ();
6891
29b0f896 6892 /* Output jumps. */
40fb9820 6893 if (i.tm.opcode_modifier.jump)
29b0f896 6894 output_branch ();
40fb9820
L		 6895 else if (i.tm.opcode_modifier.jumpbyte
6896 || i.tm.opcode_modifier.jumpdword)
29b0f896 6897 output_jump ();
40fb9820 6898 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6899 output_interseg_jump ();
6900 else
6901 {
6902 /* Output normal instructions here. */
6903 char *p;
6904 unsigned char *q;
47465058 6905 unsigned int j;
331d2d0d 6906 unsigned int prefix;
4dffcebc 6907
43234a1e
L		 6908 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6909 don't need the explicit prefix. */
6910 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 6911 {
c0f3af97 6912 switch (i.tm.opcode_length)
bc4bd9ab 6913 {
c0f3af97
L		 6914 case 3:
6915 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6916 {
c0f3af97
L		 6917 prefix = (i.tm.base_opcode >> 24) & 0xff;
6918 goto check_prefix;
6919 }
6920 break;
6921 case 2:
6922 if ((i.tm.base_opcode & 0xff0000) != 0)
6923 {
6924 prefix = (i.tm.base_opcode >> 16) & 0xff;
6925 if (i.tm.cpu_flags.bitfield.cpupadlock)
6926 {
4dffcebc 6927check_prefix:
c0f3af97 6928 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6929 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6930 != REPE_PREFIX_OPCODE))
6931 add_prefix (prefix);
6932 }
6933 else
4dffcebc
L		 6934 add_prefix (prefix);
6935 }
c0f3af97
L		 6936 break;
6937 case 1:
6938 break;
6939 default:
6940 abort ();
bc4bd9ab 6941 }
c0f3af97
L		 6942
6943 /* The prefix bytes. */
6944 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
6945 if (*q)
6946 FRAG_APPEND_1_CHAR (*q);
0f10071e 6947 }
ae5c1c7b 6948 else
c0f3af97
L		 6949 {
6950 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
6951 if (*q)
6952 switch (j)
6953 {
6954 case REX_PREFIX:
6955 /* REX byte is encoded in VEX prefix. */
6956 break;
6957 case SEG_PREFIX:
6958 case ADDR_PREFIX:
6959 FRAG_APPEND_1_CHAR (*q);
6960 break;
6961 default:
6962 /* There should be no other prefixes for instructions
6963 with VEX prefix. */
6964 abort ();
6965 }
6966
43234a1e
L		 6967 /* For EVEX instructions i.vrex should become 0 after
6968 build_evex_prefix. For VEX instructions upper 16 registers
6969 aren't available, so VREX should be 0. */
6970 if (i.vrex)
6971 abort ();
c0f3af97
L		 6972 /* Now the VEX prefix. */
6973 p = frag_more (i.vex.length);
6974 for (j = 0; j < i.vex.length; j++)
6975 p[j] = i.vex.bytes[j];
6976 }
252b5132 6977
29b0f896 6978 /* Now the opcode; be careful about word order here! */
4dffcebc 6979 if (i.tm.opcode_length == 1)
29b0f896
AM		 6980 {
6981 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
6982 }
6983 else
6984 {
4dffcebc 6985 switch (i.tm.opcode_length)
331d2d0d 6986 {
43234a1e
L		 6987 case 4:
6988 p = frag_more (4);
6989 *p++ = (i.tm.base_opcode >> 24) & 0xff;
6990 *p++ = (i.tm.base_opcode >> 16) & 0xff;
6991 break;
4dffcebc 6992 case 3:
331d2d0d
L		 6993 p = frag_more (3);
6994 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 6995 break;
6996 case 2:
6997 p = frag_more (2);
6998 break;
6999 default:
7000 abort ();
7001 break;
331d2d0d 7002 }
0f10071e 7003
29b0f896
AM		 7004 /* Put out high byte first: can't use md_number_to_chars! */
7005 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7006 *p = i.tm.base_opcode & 0xff;
7007 }
3e73aa7c 7008
29b0f896 7009 /* Now the modrm byte and sib byte (if present). */
40fb9820 7010 if (i.tm.opcode_modifier.modrm)
29b0f896 7011 {
4a3523fa
L		 7012 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7013 | i.rm.reg << 3
7014 | i.rm.mode << 6));
29b0f896
AM		 7015 /* If i.rm.regmem == ESP (4)
7016 && i.rm.mode != (Register mode)
7017 && not 16 bit
7018 ==> need second modrm byte. */
7019 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7020 && i.rm.mode != 3
40fb9820 7021 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7022 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7023 | i.sib.index << 3
7024 | i.sib.scale << 6));
29b0f896 7025 }
3e73aa7c 7026
29b0f896 7027 if (i.disp_operands)
2bbd9c25 7028 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7029
29b0f896 7030 if (i.imm_operands)
2bbd9c25 7031 output_imm (insn_start_frag, insn_start_off);
29b0f896 7032 }
252b5132 7033
29b0f896
AM		 7034#ifdef DEBUG386
7035 if (flag_debug)
7036 {
7b81dfbb 7037 pi ("" /*line*/, &i);
29b0f896
AM		 7038 }
7039#endif /* DEBUG386 */
7040}
252b5132 7041
e205caa7
L		 7042/* Return the size of the displacement operand N. */
7043
7044static int
7045disp_size (unsigned int n)
7046{
7047 int size = 4;
43234a1e
L		 7048
7049 /* Vec_Disp8 has to be 8bit. */
7050 if (i.types[n].bitfield.vec_disp8)
7051 size = 1;
7052 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7053 size = 8;
7054 else if (i.types[n].bitfield.disp8)
7055 size = 1;
7056 else if (i.types[n].bitfield.disp16)
7057 size = 2;
e205caa7
L		 7058 return size;
7059}
7060
7061/* Return the size of the immediate operand N. */
7062
7063static int
7064imm_size (unsigned int n)
7065{
7066 int size = 4;
40fb9820
L		 7067 if (i.types[n].bitfield.imm64)
7068 size = 8;
7069 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7070 size = 1;
7071 else if (i.types[n].bitfield.imm16)
7072 size = 2;
e205caa7
L		 7073 return size;
7074}
7075
29b0f896 7076static void
64e74474 7077output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7078{
7079 char *p;
7080 unsigned int n;
252b5132 7081
29b0f896
AM		 7082 for (n = 0; n < i.operands; n++)
7083 {
43234a1e
L		 7084 if (i.types[n].bitfield.vec_disp8
7085 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7086 {
7087 if (i.op[n].disps->X_op == O_constant)
7088 {
e205caa7 7089 int size = disp_size (n);
43234a1e 7090 offsetT val = i.op[n].disps->X_add_number;
252b5132 7091
43234a1e
L		 7092 if (i.types[n].bitfield.vec_disp8)
7093 val >>= i.memshift;
7094 val = offset_in_range (val, size);
29b0f896
AM		 7095 p = frag_more (size);
7096 md_number_to_chars (p, val, size);
7097 }
7098 else
7099 {
f86103b7 7100 enum bfd_reloc_code_real reloc_type;
e205caa7 7101 int size = disp_size (n);
40fb9820 7102 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 7103 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7104
e205caa7 7105 /* We can't have 8 bit displacement here. */
9c2799c2 7106 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7107
29b0f896
AM		 7108 /* The PC relative address is computed relative
7109 to the instruction boundary, so in case immediate
7110 fields follows, we need to adjust the value. */
7111 if (pcrel && i.imm_operands)
7112 {
29b0f896 7113 unsigned int n1;
e205caa7 7114 int sz = 0;
252b5132 7115
29b0f896 7116 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7117 if (operand_type_check (i.types[n1], imm))
252b5132 7118 {
e205caa7
L		 7119 /* Only one immediate is allowed for PC
7120 relative address. */
9c2799c2 7121 gas_assert (sz == 0);
e205caa7
L		 7122 sz = imm_size (n1);
7123 i.op[n].disps->X_add_number -= sz;
252b5132 7124 }
29b0f896 7125 /* We should find the immediate. */
9c2799c2 7126 gas_assert (sz != 0);
29b0f896 7127 }
520dc8e8 7128
29b0f896 7129 p = frag_more (size);
c3320543
L		 7130 reloc_type = reloc (size, pcrel, sign,
7131 (i.bnd_prefix != NULL
7132 || add_bnd_prefix),
7133 i.reloc[n]);
d6ab8113 7134 if (GOT_symbol
2bbd9c25 7135 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7136 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7137 || reloc_type == BFD_RELOC_X86_64_32S
7138 || (reloc_type == BFD_RELOC_64
7139 && object_64bit))
d6ab8113
JB		 7140 && (i.op[n].disps->X_op == O_symbol
7141 || (i.op[n].disps->X_op == O_add
7142 && ((symbol_get_value_expression
7143 (i.op[n].disps->X_op_symbol)->X_op)
7144 == O_subtract))))
7145 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7146 {
7147 offsetT add;
7148
7149 if (insn_start_frag == frag_now)
7150 add = (p - frag_now->fr_literal) - insn_start_off;
7151 else
7152 {
7153 fragS *fr;
7154
7155 add = insn_start_frag->fr_fix - insn_start_off;
7156 for (fr = insn_start_frag->fr_next;
7157 fr && fr != frag_now; fr = fr->fr_next)
7158 add += fr->fr_fix;
7159 add += p - frag_now->fr_literal;
7160 }
7161
4fa24527 7162 if (!object_64bit)
7b81dfbb
AJ		 7163 {
7164 reloc_type = BFD_RELOC_386_GOTPC;
7165 i.op[n].imms->X_add_number += add;
7166 }
7167 else if (reloc_type == BFD_RELOC_64)
7168 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7169 else
7b81dfbb
AJ		 7170 /* Don't do the adjustment for x86-64, as there
7171 the pcrel addressing is relative to the _next_
7172 insn, and that is taken care of in other code. */
d6ab8113 7173 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7174 }
062cd5e7 7175 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 7176 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 7177 }
7178 }
7179 }
7180}
252b5132 7181
29b0f896 7182static void
64e74474 7183output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7184{
7185 char *p;
7186 unsigned int n;
252b5132 7187
29b0f896
AM		 7188 for (n = 0; n < i.operands; n++)
7189 {
43234a1e
L		 7190 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7191 if (i.rounding && (int) n == i.rounding->operand)
7192 continue;
7193
40fb9820 7194 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7195 {
7196 if (i.op[n].imms->X_op == O_constant)
7197 {
e205caa7 7198 int size = imm_size (n);
29b0f896 7199 offsetT val;
b4cac588 7200
29b0f896
AM		 7201 val = offset_in_range (i.op[n].imms->X_add_number,
7202 size);
7203 p = frag_more (size);
7204 md_number_to_chars (p, val, size);
7205 }
7206 else
7207 {
7208 /* Not absolute_section.
7209 Need a 32-bit fixup (don't support 8bit
7210 non-absolute imms). Try to support other
7211 sizes ... */
f86103b7 7212 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7213 int size = imm_size (n);
7214 int sign;
29b0f896 7215
40fb9820 7216 if (i.types[n].bitfield.imm32s
a7d61044 7217 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7218 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7219 sign = 1;
e205caa7
L		 7220 else
7221 sign = 0;
520dc8e8 7222
29b0f896 7223 p = frag_more (size);
c3320543 7224 reloc_type = reloc (size, 0, sign, 0, i.reloc[n]);
f86103b7 7225
2bbd9c25
JJ		 7226 /* This is tough to explain. We end up with this one if we
7227 * have operands that look like
7228 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7229 * obtain the absolute address of the GOT, and it is strongly
7230 * preferable from a performance point of view to avoid using
7231 * a runtime relocation for this. The actual sequence of
7232 * instructions often look something like:
7233 *
7234 * call .L66
7235 * .L66:
7236 * popl %ebx
7237 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7238 *
7239 * The call and pop essentially return the absolute address
7240 * of the label .L66 and store it in %ebx. The linker itself
7241 * will ultimately change the first operand of the addl so
7242 * that %ebx points to the GOT, but to keep things simple, the
7243 * .o file must have this operand set so that it generates not
7244 * the absolute address of .L66, but the absolute address of
7245 * itself. This allows the linker itself simply treat a GOTPC
7246 * relocation as asking for a pcrel offset to the GOT to be
7247 * added in, and the addend of the relocation is stored in the
7248 * operand field for the instruction itself.
7249 *
7250 * Our job here is to fix the operand so that it would add
7251 * the correct offset so that %ebx would point to itself. The
7252 * thing that is tricky is that .-.L66 will point to the
7253 * beginning of the instruction, so we need to further modify
7254 * the operand so that it will point to itself. There are
7255 * other cases where you have something like:
7256 *
7257 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7258 *
7259 * and here no correction would be required. Internally in
7260 * the assembler we treat operands of this form as not being
7261 * pcrel since the '.' is explicitly mentioned, and I wonder
7262 * whether it would simplify matters to do it this way. Who
7263 * knows. In earlier versions of the PIC patches, the
7264 * pcrel_adjust field was used to store the correction, but
7265 * since the expression is not pcrel, I felt it would be
7266 * confusing to do it this way. */
7267
d6ab8113 7268 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7269 || reloc_type == BFD_RELOC_X86_64_32S
7270 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7271 && GOT_symbol
7272 && GOT_symbol == i.op[n].imms->X_add_symbol
7273 && (i.op[n].imms->X_op == O_symbol
7274 || (i.op[n].imms->X_op == O_add
7275 && ((symbol_get_value_expression
7276 (i.op[n].imms->X_op_symbol)->X_op)
7277 == O_subtract))))
7278 {
2bbd9c25
JJ		 7279 offsetT add;
7280
7281 if (insn_start_frag == frag_now)
7282 add = (p - frag_now->fr_literal) - insn_start_off;
7283 else
7284 {
7285 fragS *fr;
7286
7287 add = insn_start_frag->fr_fix - insn_start_off;
7288 for (fr = insn_start_frag->fr_next;
7289 fr && fr != frag_now; fr = fr->fr_next)
7290 add += fr->fr_fix;
7291 add += p - frag_now->fr_literal;
7292 }
7293
4fa24527 7294 if (!object_64bit)
d6ab8113 7295 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7296 else if (size == 4)
d6ab8113 7297 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7298 else if (size == 8)
7299 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7300 i.op[n].imms->X_add_number += add;
29b0f896 7301 }
29b0f896
AM		 7302 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7303 i.op[n].imms, 0, reloc_type);
7304 }
7305 }
7306 }
252b5132
RH		 7307}
7308\f
d182319b
JB		 7309/* x86_cons_fix_new is called via the expression parsing code when a
7310 reloc is needed. We use this hook to get the correct .got reloc. */
7311static enum bfd_reloc_code_real got_reloc = NO_RELOC;
7312static int cons_sign = -1;
7313
7314void
e3bb37b5 7315x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 7316 expressionS *exp)
d182319b 7317{
c3320543 7318 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, 0, got_reloc);
d182319b
JB		 7319
7320 got_reloc = NO_RELOC;
7321
7322#ifdef TE_PE
7323 if (exp->X_op == O_secrel)
7324 {
7325 exp->X_op = O_symbol;
7326 r = BFD_RELOC_32_SECREL;
7327 }
7328#endif
7329
7330 fix_new_exp (frag, off, len, exp, 0, r);
7331}
7332
357d1bd8
L		 7333/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7334 purpose of the `.dc.a' internal pseudo-op. */
7335
7336int
7337x86_address_bytes (void)
7338{
7339 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7340 return 4;
7341 return stdoutput->arch_info->bits_per_address / 8;
7342}
7343
d382c579
TG		 7344#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7345 || defined (LEX_AT)
c06ec724 7346# define lex_got(reloc, adjust, types, bnd_prefix) NULL
718ddfc0 7347#else
f3c180ae
AM		 7348/* Parse operands of the form
7349 <symbol>@GOTOFF+<nnn>
7350 and similar .plt or .got references.
7351
7352 If we find one, set up the correct relocation in RELOC and copy the
7353 input string, minus the `@GOTOFF' into a malloc'd buffer for
7354 parsing by the calling routine. Return this buffer, and if ADJUST
7355 is non-null set it to the length of the string we removed from the
7356 input line. Otherwise return NULL. */
7357static char *
91d6fa6a 7358lex_got (enum bfd_reloc_code_real *rel,
64e74474 7359 int *adjust,
c3320543
L		 7360 i386_operand_type *types,
7361 int bnd_prefix)
f3c180ae 7362{
7b81dfbb
AJ		 7363 /* Some of the relocations depend on the size of what field is to
7364 be relocated. But in our callers i386_immediate and i386_displacement
7365 we don't yet know the operand size (this will be set by insn
7366 matching). Hence we record the word32 relocation here,
7367 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7368 static const struct {
7369 const char *str;
cff8d58a 7370 int len;
4fa24527 7371 const enum bfd_reloc_code_real rel[2];
40fb9820 7372 const i386_operand_type types64;
f3c180ae 7373 } gotrel[] = {
8ce3d284 7374#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7375 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7376 BFD_RELOC_SIZE32 },
7377 OPERAND_TYPE_IMM32_64 },
8ce3d284 7378#endif
cff8d58a
L		 7379 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7380 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7381 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7382 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7383 BFD_RELOC_X86_64_PLT32 },
40fb9820 7384 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7385 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7386 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7387 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7388 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7389 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7390 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7391 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7392 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7393 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7394 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7395 BFD_RELOC_X86_64_TLSGD },
40fb9820 7396 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7397 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7398 _dummy_first_bfd_reloc_code_real },
40fb9820 7399 OPERAND_TYPE_NONE },
cff8d58a
L		 7400 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7401 BFD_RELOC_X86_64_TLSLD },
40fb9820 7402 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7403 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7404 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7405 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7406 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7407 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7408 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7409 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7410 _dummy_first_bfd_reloc_code_real },
40fb9820 7411 OPERAND_TYPE_NONE },
cff8d58a
L		 7412 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7413 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7414 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7415 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7416 _dummy_first_bfd_reloc_code_real },
40fb9820 7417 OPERAND_TYPE_NONE },
cff8d58a
L		 7418 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7419 _dummy_first_bfd_reloc_code_real },
40fb9820 7420 OPERAND_TYPE_NONE },
cff8d58a
L		 7421 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7422 BFD_RELOC_X86_64_GOT32 },
40fb9820 7423 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7424 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7425 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7426 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7427 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7428 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7429 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7430 };
7431 char *cp;
7432 unsigned int j;
7433
d382c579 7434#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7435 if (!IS_ELF)
7436 return NULL;
d382c579 7437#endif
718ddfc0 7438
f3c180ae 7439 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7440 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7441 return NULL;
7442
47465058 7443 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7444 {
cff8d58a 7445 int len = gotrel[j].len;
28f81592 7446 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7447 {
4fa24527 7448 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7449 {
28f81592
AM		 7450 int first, second;
7451 char *tmpbuf, *past_reloc;
f3c180ae 7452
91d6fa6a 7453 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7454
3956db08
JB		 7455 if (types)
7456 {
7457 if (flag_code != CODE_64BIT)
40fb9820
L		 7458 {
7459 types->bitfield.imm32 = 1;
7460 types->bitfield.disp32 = 1;
7461 }
3956db08
JB		 7462 else
7463 *types = gotrel[j].types64;
7464 }
7465
8fd4256d 7466 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7467 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7468
28f81592 7469 /* The length of the first part of our input line. */
f3c180ae 7470 first = cp - input_line_pointer;
28f81592
AM		 7471
7472 /* The second part goes from after the reloc token until
67c11a9b 7473 (and including) an end_of_line char or comma. */
28f81592 7474 past_reloc = cp + 1 + len;
67c11a9b
AM		 7475 cp = past_reloc;
7476 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7477 ++cp;
7478 second = cp + 1 - past_reloc;
28f81592
AM		 7479
7480 /* Allocate and copy string. The trailing NUL shouldn't
7481 be necessary, but be safe. */
1e9cc1c2 7482 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 7483 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7484 if (second != 0 && *past_reloc != ' ')
7485 /* Replace the relocation token with ' ', so that
7486 errors like foo@GOTOFF1 will be detected. */
7487 tmpbuf[first++] = ' ';
af89796a
L		 7488 else
7489 /* Increment length by 1 if the relocation token is
7490 removed. */
7491 len++;
7492 if (adjust)
7493 *adjust = len;
0787a12d
AM		 7494 memcpy (tmpbuf + first, past_reloc, second);
7495 tmpbuf[first + second] = '\0';
c3320543
L		 7496 if (bnd_prefix && *rel == BFD_RELOC_X86_64_PLT32)
7497 *rel = BFD_RELOC_X86_64_PLT32_BND;
f3c180ae
AM		 7498 return tmpbuf;
7499 }
7500
4fa24527
JB		 7501 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7502 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7503 return NULL;
7504 }
7505 }
7506
7507 /* Might be a symbol version string. Don't as_bad here. */
7508 return NULL;
7509}
4e4f7c87 7510#endif
f3c180ae 7511
a988325c
NC		 7512#ifdef TE_PE
7513#ifdef lex_got
7514#undef lex_got
7515#endif
7516/* Parse operands of the form
7517 <symbol>@SECREL32+<nnn>
7518
7519 If we find one, set up the correct relocation in RELOC and copy the
7520 input string, minus the `@SECREL32' into a malloc'd buffer for
7521 parsing by the calling routine. Return this buffer, and if ADJUST
7522 is non-null set it to the length of the string we removed from the
34bca508
L		 7523 input line. Otherwise return NULL.
7524
a988325c
NC		 7525 This function is copied from the ELF version above adjusted for PE targets. */
7526
7527static char *
7528lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7529 int *adjust ATTRIBUTE_UNUSED,
c06ec724
L		 7530 i386_operand_type *types,
7531 int bnd_prefix ATTRIBUTE_UNUSED)
a988325c
NC		 7532{
7533 static const struct
7534 {
7535 const char *str;
7536 int len;
7537 const enum bfd_reloc_code_real rel[2];
7538 const i386_operand_type types64;
7539 }
7540 gotrel[] =
7541 {
7542 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7543 BFD_RELOC_32_SECREL },
7544 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7545 };
7546
7547 char *cp;
7548 unsigned j;
7549
7550 for (cp = input_line_pointer; *cp != '@'; cp++)
7551 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7552 return NULL;
7553
7554 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7555 {
7556 int len = gotrel[j].len;
7557
7558 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7559 {
7560 if (gotrel[j].rel[object_64bit] != 0)
7561 {
7562 int first, second;
7563 char *tmpbuf, *past_reloc;
7564
7565 *rel = gotrel[j].rel[object_64bit];
7566 if (adjust)
7567 *adjust = len;
7568
7569 if (types)
7570 {
7571 if (flag_code != CODE_64BIT)
7572 {
7573 types->bitfield.imm32 = 1;
7574 types->bitfield.disp32 = 1;
7575 }
7576 else
7577 *types = gotrel[j].types64;
7578 }
7579
7580 /* The length of the first part of our input line. */
7581 first = cp - input_line_pointer;
7582
7583 /* The second part goes from after the reloc token until
7584 (and including) an end_of_line char or comma. */
7585 past_reloc = cp + 1 + len;
7586 cp = past_reloc;
7587 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7588 ++cp;
7589 second = cp + 1 - past_reloc;
7590
7591 /* Allocate and copy string. The trailing NUL shouldn't
7592 be necessary, but be safe. */
7593 tmpbuf = (char *) xmalloc (first + second + 2);
7594 memcpy (tmpbuf, input_line_pointer, first);
7595 if (second != 0 && *past_reloc != ' ')
7596 /* Replace the relocation token with ' ', so that
7597 errors like foo@SECLREL321 will be detected. */
7598 tmpbuf[first++] = ' ';
7599 memcpy (tmpbuf + first, past_reloc, second);
7600 tmpbuf[first + second] = '\0';
7601 return tmpbuf;
7602 }
7603
7604 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7605 gotrel[j].str, 1 << (5 + object_64bit));
7606 return NULL;
7607 }
7608 }
7609
7610 /* Might be a symbol version string. Don't as_bad here. */
7611 return NULL;
7612}
7613
7614#endif /* TE_PE */
7615
f3c180ae 7616void
e3bb37b5 7617x86_cons (expressionS *exp, int size)
f3c180ae 7618{
ee86248c
JB		 7619 intel_syntax = -intel_syntax;
7620
3c7b9c2c 7621 exp->X_md = 0;
4fa24527 7622 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7623 {
7624 /* Handle @GOTOFF and the like in an expression. */
7625 char *save;
7626 char *gotfree_input_line;
4a57f2cf 7627 int adjust = 0;
f3c180ae
AM		 7628
7629 save = input_line_pointer;
c3320543 7630 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL, 0);
f3c180ae
AM		 7631 if (gotfree_input_line)
7632 input_line_pointer = gotfree_input_line;
7633
7634 expression (exp);
7635
7636 if (gotfree_input_line)
7637 {
7638 /* expression () has merrily parsed up to the end of line,
7639 or a comma - in the wrong buffer. Transfer how far
7640 input_line_pointer has moved to the right buffer. */
7641 input_line_pointer = (save
7642 + (input_line_pointer - gotfree_input_line)
7643 + adjust);
7644 free (gotfree_input_line);
3992d3b7
AM		 7645 if (exp->X_op == O_constant
7646 || exp->X_op == O_absent
7647 || exp->X_op == O_illegal
0398aac5 7648 || exp->X_op == O_register
3992d3b7
AM		 7649 || exp->X_op == O_big)
7650 {
7651 char c = *input_line_pointer;
7652 *input_line_pointer = 0;
7653 as_bad (_("missing or invalid expression `%s'"), save);
7654 *input_line_pointer = c;
7655 }
f3c180ae
AM		 7656 }
7657 }
7658 else
7659 expression (exp);
ee86248c
JB		 7660
7661 intel_syntax = -intel_syntax;
7662
7663 if (intel_syntax)
7664 i386_intel_simplify (exp);
f3c180ae 7665}
f3c180ae 7666
9f32dd5b
L		 7667static void
7668signed_cons (int size)
6482c264 7669{
d182319b
JB		 7670 if (flag_code == CODE_64BIT)
7671 cons_sign = 1;
7672 cons (size);
7673 cons_sign = -1;
6482c264
NC		 7674}
7675
d182319b 7676#ifdef TE_PE
6482c264 7677static void
7016a5d5 7678pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7679{
7680 expressionS exp;
7681
7682 do
7683 {
7684 expression (&exp);
7685 if (exp.X_op == O_symbol)
7686 exp.X_op = O_secrel;
7687
7688 emit_expr (&exp, 4);
7689 }
7690 while (*input_line_pointer++ == ',');
7691
7692 input_line_pointer--;
7693 demand_empty_rest_of_line ();
7694}
6482c264
NC		 7695#endif
7696
43234a1e
L		 7697/* Handle Vector operations. */
7698
7699static char *
7700check_VecOperations (char *op_string, char *op_end)
7701{
7702 const reg_entry *mask;
7703 const char *saved;
7704 char *end_op;
7705
7706 while (*op_string
7707 && (op_end == NULL || op_string < op_end))
7708 {
7709 saved = op_string;
7710 if (*op_string == '{')
7711 {
7712 op_string++;
7713
7714 /* Check broadcasts. */
7715 if (strncmp (op_string, "1to", 3) == 0)
7716 {
7717 int bcst_type;
7718
7719 if (i.broadcast)
7720 goto duplicated_vec_op;
7721
7722 op_string += 3;
7723 if (*op_string == '8')
7724 bcst_type = BROADCAST_1TO8;
7725 else if (*op_string == '1'
7726 && *(op_string+1) == '6')
7727 {
7728 bcst_type = BROADCAST_1TO16;
7729 op_string++;
7730 }
7731 else
7732 {
7733 as_bad (_("Unsupported broadcast: `%s'"), saved);
7734 return NULL;
7735 }
7736 op_string++;
7737
7738 broadcast_op.type = bcst_type;
7739 broadcast_op.operand = this_operand;
7740 i.broadcast = &broadcast_op;
7741 }
7742 /* Check masking operation. */
7743 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7744 {
7745 /* k0 can't be used for write mask. */
7746 if (mask->reg_num == 0)
7747 {
7748 as_bad (_("`%s' can't be used for write mask"),
7749 op_string);
7750 return NULL;
7751 }
7752
7753 if (!i.mask)
7754 {
7755 mask_op.mask = mask;
7756 mask_op.zeroing = 0;
7757 mask_op.operand = this_operand;
7758 i.mask = &mask_op;
7759 }
7760 else
7761 {
7762 if (i.mask->mask)
7763 goto duplicated_vec_op;
7764
7765 i.mask->mask = mask;
7766
7767 /* Only "{z}" is allowed here. No need to check
7768 zeroing mask explicitly. */
7769 if (i.mask->operand != this_operand)
7770 {
7771 as_bad (_("invalid write mask `%s'"), saved);
7772 return NULL;
7773 }
7774 }
7775
7776 op_string = end_op;
7777 }
7778 /* Check zeroing-flag for masking operation. */
7779 else if (*op_string == 'z')
7780 {
7781 if (!i.mask)
7782 {
7783 mask_op.mask = NULL;
7784 mask_op.zeroing = 1;
7785 mask_op.operand = this_operand;
7786 i.mask = &mask_op;
7787 }
7788 else
7789 {
7790 if (i.mask->zeroing)
7791 {
7792 duplicated_vec_op:
7793 as_bad (_("duplicated `%s'"), saved);
7794 return NULL;
7795 }
7796
7797 i.mask->zeroing = 1;
7798
7799 /* Only "{%k}" is allowed here. No need to check mask
7800 register explicitly. */
7801 if (i.mask->operand != this_operand)
7802 {
7803 as_bad (_("invalid zeroing-masking `%s'"),
7804 saved);
7805 return NULL;
7806 }
7807 }
7808
7809 op_string++;
7810 }
7811 else
7812 goto unknown_vec_op;
7813
7814 if (*op_string != '}')
7815 {
7816 as_bad (_("missing `}' in `%s'"), saved);
7817 return NULL;
7818 }
7819 op_string++;
7820 continue;
7821 }
7822 unknown_vec_op:
7823 /* We don't know this one. */
7824 as_bad (_("unknown vector operation: `%s'"), saved);
7825 return NULL;
7826 }
7827
7828 return op_string;
7829}
7830
252b5132 7831static int
70e41ade 7832i386_immediate (char *imm_start)
252b5132
RH		 7833{
7834 char *save_input_line_pointer;
f3c180ae 7835 char *gotfree_input_line;
252b5132 7836 segT exp_seg = 0;
47926f60 7837 expressionS *exp;
40fb9820
L		 7838 i386_operand_type types;
7839
0dfbf9d7 7840 operand_type_set (&types, ~0);
252b5132
RH		 7841
7842 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7843 {
31b2323c
L		 7844 as_bad (_("at most %d immediate operands are allowed"),
7845 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 7846 return 0;
7847 }
7848
7849 exp = &im_expressions[i.imm_operands++];
520dc8e8 7850 i.op[this_operand].imms = exp;
252b5132
RH		 7851
7852 if (is_space_char (*imm_start))
7853 ++imm_start;
7854
7855 save_input_line_pointer = input_line_pointer;
7856 input_line_pointer = imm_start;
7857
c3320543
L		 7858 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types,
7859 (i.bnd_prefix != NULL
7860 || add_bnd_prefix));
f3c180ae
AM		 7861 if (gotfree_input_line)
7862 input_line_pointer = gotfree_input_line;
252b5132
RH		 7863
7864 exp_seg = expression (exp);
7865
83183c0c 7866 SKIP_WHITESPACE ();
43234a1e
L		 7867
7868 /* Handle vector operations. */
7869 if (*input_line_pointer == '{')
7870 {
7871 input_line_pointer = check_VecOperations (input_line_pointer,
7872 NULL);
7873 if (input_line_pointer == NULL)
7874 return 0;
7875 }
7876
252b5132 7877 if (*input_line_pointer)
f3c180ae 7878 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 7879
7880 input_line_pointer = save_input_line_pointer;
f3c180ae 7881 if (gotfree_input_line)
ee86248c
JB		 7882 {
7883 free (gotfree_input_line);
7884
7885 if (exp->X_op == O_constant || exp->X_op == O_register)
7886 exp->X_op = O_illegal;
7887 }
7888
7889 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7890}
252b5132 7891
ee86248c
JB		 7892static int
7893i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7894 i386_operand_type types, const char *imm_start)
7895{
7896 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 7897 {
313c53d1
L		 7898 if (imm_start)
7899 as_bad (_("missing or invalid immediate expression `%s'"),
7900 imm_start);
3992d3b7 7901 return 0;
252b5132 7902 }
3e73aa7c 7903 else if (exp->X_op == O_constant)
252b5132 7904 {
47926f60 7905 /* Size it properly later. */
40fb9820 7906 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 7907 /* If not 64bit, sign extend val. */
7908 if (flag_code != CODE_64BIT
4eed87de
AM		 7909 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7910 exp->X_add_number
7911 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 7912 }
4c63da97 7913#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 7914 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 7915 && exp_seg != absolute_section
47926f60 7916 && exp_seg != text_section
24eab124
AM		 7917 && exp_seg != data_section
7918 && exp_seg != bss_section
7919 && exp_seg != undefined_section
f86103b7 7920 && !bfd_is_com_section (exp_seg))
252b5132 7921 {
d0b47220 7922 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 7923 return 0;
7924 }
7925#endif
bb8f5920
L		 7926 else if (!intel_syntax && exp->X_op == O_register)
7927 {
313c53d1
L		 7928 if (imm_start)
7929 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 7930 return 0;
7931 }
252b5132
RH		 7932 else
7933 {
7934 /* This is an address. The size of the address will be
24eab124 7935 determined later, depending on destination register,
3e73aa7c 7936 suffix, or the default for the section. */
40fb9820
L		 7937 i.types[this_operand].bitfield.imm8 = 1;
7938 i.types[this_operand].bitfield.imm16 = 1;
7939 i.types[this_operand].bitfield.imm32 = 1;
7940 i.types[this_operand].bitfield.imm32s = 1;
7941 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 7942 i.types[this_operand] = operand_type_and (i.types[this_operand],
7943 types);
252b5132
RH		 7944 }
7945
7946 return 1;
7947}
7948
551c1ca1 7949static char *
e3bb37b5 7950i386_scale (char *scale)
252b5132 7951{
551c1ca1
AM		 7952 offsetT val;
7953 char *save = input_line_pointer;
252b5132 7954
551c1ca1
AM		 7955 input_line_pointer = scale;
7956 val = get_absolute_expression ();
7957
7958 switch (val)
252b5132 7959 {
551c1ca1 7960 case 1:
252b5132
RH		 7961 i.log2_scale_factor = 0;
7962 break;
551c1ca1 7963 case 2:
252b5132
RH		 7964 i.log2_scale_factor = 1;
7965 break;
551c1ca1 7966 case 4:
252b5132
RH		 7967 i.log2_scale_factor = 2;
7968 break;
551c1ca1 7969 case 8:
252b5132
RH		 7970 i.log2_scale_factor = 3;
7971 break;
7972 default:
a724f0f4
JB		 7973 {
7974 char sep = *input_line_pointer;
7975
7976 *input_line_pointer = '\0';
7977 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
7978 scale);
7979 *input_line_pointer = sep;
7980 input_line_pointer = save;
7981 return NULL;
7982 }
252b5132 7983 }
29b0f896 7984 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 7985 {
7986 as_warn (_("scale factor of %d without an index register"),
24eab124 7987 1 << i.log2_scale_factor);
252b5132 7988 i.log2_scale_factor = 0;
252b5132 7989 }
551c1ca1
AM		 7990 scale = input_line_pointer;
7991 input_line_pointer = save;
7992 return scale;
252b5132
RH		 7993}
7994
252b5132 7995static int
e3bb37b5 7996i386_displacement (char *disp_start, char *disp_end)
252b5132 7997{
29b0f896 7998 expressionS *exp;
252b5132
RH		 7999 segT exp_seg = 0;
8000 char *save_input_line_pointer;
f3c180ae 8001 char *gotfree_input_line;
40fb9820
L		 8002 int override;
8003 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8004 int ret;
252b5132 8005
31b2323c
L		 8006 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8007 {
8008 as_bad (_("at most %d displacement operands are allowed"),
8009 MAX_MEMORY_OPERANDS);
8010 return 0;
8011 }
8012
0dfbf9d7 8013 operand_type_set (&bigdisp, 0);
40fb9820
L		 8014 if ((i.types[this_operand].bitfield.jumpabsolute)
8015 || (!current_templates->start->opcode_modifier.jump
8016 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8017 {
40fb9820 8018 bigdisp.bitfield.disp32 = 1;
e05278af 8019 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8020 if (flag_code == CODE_64BIT)
8021 {
8022 if (!override)
8023 {
8024 bigdisp.bitfield.disp32s = 1;
8025 bigdisp.bitfield.disp64 = 1;
8026 }
8027 }
8028 else if ((flag_code == CODE_16BIT) ^ override)
8029 {
8030 bigdisp.bitfield.disp32 = 0;
8031 bigdisp.bitfield.disp16 = 1;
8032 }
e05278af
JB		 8033 }
8034 else
8035 {
8036 /* For PC-relative branches, the width of the displacement
8037 is dependent upon data size, not address size. */
e05278af 8038 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8039 if (flag_code == CODE_64BIT)
8040 {
8041 if (override || i.suffix == WORD_MNEM_SUFFIX)
8042 bigdisp.bitfield.disp16 = 1;
8043 else
8044 {
8045 bigdisp.bitfield.disp32 = 1;
8046 bigdisp.bitfield.disp32s = 1;
8047 }
8048 }
8049 else
e05278af
JB		 8050 {
8051 if (!override)
8052 override = (i.suffix == (flag_code != CODE_16BIT
8053 ? WORD_MNEM_SUFFIX
8054 : LONG_MNEM_SUFFIX));
40fb9820
L		 8055 bigdisp.bitfield.disp32 = 1;
8056 if ((flag_code == CODE_16BIT) ^ override)
8057 {
8058 bigdisp.bitfield.disp32 = 0;
8059 bigdisp.bitfield.disp16 = 1;
8060 }
e05278af 8061 }
e05278af 8062 }
c6fb90c8
L		 8063 i.types[this_operand] = operand_type_or (i.types[this_operand],
8064 bigdisp);
252b5132
RH		 8065
8066 exp = &disp_expressions[i.disp_operands];
520dc8e8 8067 i.op[this_operand].disps = exp;
252b5132
RH		 8068 i.disp_operands++;
8069 save_input_line_pointer = input_line_pointer;
8070 input_line_pointer = disp_start;
8071 END_STRING_AND_SAVE (disp_end);
8072
8073#ifndef GCC_ASM_O_HACK
8074#define GCC_ASM_O_HACK 0
8075#endif
8076#if GCC_ASM_O_HACK
8077 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8078 if (i.types[this_operand].bitfield.baseIndex
24eab124 8079 && displacement_string_end[-1] == '+')
252b5132
RH		 8080 {
8081 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8082 constraint within gcc asm statements.
8083 For instance:
8084
8085 #define _set_tssldt_desc(n,addr,limit,type) \
8086 __asm__ __volatile__ ( \
8087 "movw %w2,%0\n\t" \
8088 "movw %w1,2+%0\n\t" \
8089 "rorl $16,%1\n\t" \
8090 "movb %b1,4+%0\n\t" \
8091 "movb %4,5+%0\n\t" \
8092 "movb $0,6+%0\n\t" \
8093 "movb %h1,7+%0\n\t" \
8094 "rorl $16,%1" \
8095 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8096
8097 This works great except that the output assembler ends
8098 up looking a bit weird if it turns out that there is
8099 no offset. You end up producing code that looks like:
8100
8101 #APP
8102 movw $235,(%eax)
8103 movw %dx,2+(%eax)
8104 rorl $16,%edx
8105 movb %dl,4+(%eax)
8106 movb $137,5+(%eax)
8107 movb $0,6+(%eax)
8108 movb %dh,7+(%eax)
8109 rorl $16,%edx
8110 #NO_APP
8111
47926f60 8112 So here we provide the missing zero. */
24eab124
AM		 8113
8114 *displacement_string_end = '0';
252b5132
RH		 8115 }
8116#endif
c3320543
L		 8117 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types,
8118 (i.bnd_prefix != NULL
8119 || add_bnd_prefix));
f3c180ae
AM		 8120 if (gotfree_input_line)
8121 input_line_pointer = gotfree_input_line;
252b5132 8122
24eab124 8123 exp_seg = expression (exp);
252b5132 8124
636c26b0
AM		 8125 SKIP_WHITESPACE ();
8126 if (*input_line_pointer)
8127 as_bad (_("junk `%s' after expression"), input_line_pointer);
8128#if GCC_ASM_O_HACK
8129 RESTORE_END_STRING (disp_end + 1);
8130#endif
636c26b0 8131 input_line_pointer = save_input_line_pointer;
636c26b0 8132 if (gotfree_input_line)
ee86248c
JB		 8133 {
8134 free (gotfree_input_line);
8135
8136 if (exp->X_op == O_constant || exp->X_op == O_register)
8137 exp->X_op = O_illegal;
8138 }
8139
8140 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8141
8142 RESTORE_END_STRING (disp_end);
8143
8144 return ret;
8145}
8146
8147static int
8148i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8149 i386_operand_type types, const char *disp_start)
8150{
8151 i386_operand_type bigdisp;
8152 int ret = 1;
636c26b0 8153
24eab124
AM		 8154 /* We do this to make sure that the section symbol is in
8155 the symbol table. We will ultimately change the relocation
47926f60 8156 to be relative to the beginning of the section. */
1ae12ab7 8157 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8158 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8159 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8160 {
636c26b0 8161 if (exp->X_op != O_symbol)
3992d3b7 8162 goto inv_disp;
636c26b0 8163
e5cb08ac 8164 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8165 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8166 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8167 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8168 exp->X_op = O_subtract;
8169 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8170 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8171 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8172 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8173 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8174 else
29b0f896 8175 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8176 }
252b5132 8177
3992d3b7
AM		 8178 else if (exp->X_op == O_absent
8179 || exp->X_op == O_illegal
ee86248c 8180 || exp->X_op == O_big)
2daf4fd8 8181 {
3992d3b7
AM		 8182 inv_disp:
8183 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8184 disp_start);
3992d3b7 8185 ret = 0;
2daf4fd8
AM		 8186 }
8187
0e1147d9
L		 8188 else if (flag_code == CODE_64BIT
8189 && !i.prefix[ADDR_PREFIX]
8190 && exp->X_op == O_constant)
8191 {
8192 /* Since displacement is signed extended to 64bit, don't allow
8193 disp32 and turn off disp32s if they are out of range. */
8194 i.types[this_operand].bitfield.disp32 = 0;
8195 if (!fits_in_signed_long (exp->X_add_number))
8196 {
8197 i.types[this_operand].bitfield.disp32s = 0;
8198 if (i.types[this_operand].bitfield.baseindex)
8199 {
8200 as_bad (_("0x%lx out range of signed 32bit displacement"),
8201 (long) exp->X_add_number);
8202 ret = 0;
8203 }
8204 }
8205 }
8206
4c63da97 8207#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8208 else if (exp->X_op != O_constant
8209 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8210 && exp_seg != absolute_section
8211 && exp_seg != text_section
8212 && exp_seg != data_section
8213 && exp_seg != bss_section
8214 && exp_seg != undefined_section
8215 && !bfd_is_com_section (exp_seg))
24eab124 8216 {
d0b47220 8217 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8218 ret = 0;
24eab124 8219 }
252b5132 8220#endif
3956db08 8221
40fb9820
L		 8222 /* Check if this is a displacement only operand. */
8223 bigdisp = i.types[this_operand];
8224 bigdisp.bitfield.disp8 = 0;
8225 bigdisp.bitfield.disp16 = 0;
8226 bigdisp.bitfield.disp32 = 0;
8227 bigdisp.bitfield.disp32s = 0;
8228 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8229 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8230 i.types[this_operand] = operand_type_and (i.types[this_operand],
8231 types);
3956db08 8232
3992d3b7 8233 return ret;
252b5132
RH		 8234}
8235
eecb386c 8236/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8237 Return 1 on success, 0 on a failure. */
8238
252b5132 8239static int
e3bb37b5 8240i386_index_check (const char *operand_string)
252b5132 8241{
fc0763e6 8242 const char *kind = "base/index";
be05d201
L		 8243 enum flag_code addr_mode;
8244
8245 if (i.prefix[ADDR_PREFIX])
8246 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8247 else
8248 {
8249 addr_mode = flag_code;
8250
24eab124 8251#if INFER_ADDR_PREFIX
be05d201
L		 8252 if (i.mem_operands == 0)
8253 {
8254 /* Infer address prefix from the first memory operand. */
8255 const reg_entry *addr_reg = i.base_reg;
8256
8257 if (addr_reg == NULL)
8258 addr_reg = i.index_reg;
eecb386c 8259
be05d201
L		 8260 if (addr_reg)
8261 {
8262 if (addr_reg->reg_num == RegEip
8263 || addr_reg->reg_num == RegEiz
8264 || addr_reg->reg_type.bitfield.reg32)
8265 addr_mode = CODE_32BIT;
8266 else if (flag_code != CODE_64BIT
8267 && addr_reg->reg_type.bitfield.reg16)
8268 addr_mode = CODE_16BIT;
8269
8270 if (addr_mode != flag_code)
8271 {
8272 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8273 i.prefixes += 1;
8274 /* Change the size of any displacement too. At most one
8275 of Disp16 or Disp32 is set.
8276 FIXME. There doesn't seem to be any real need for
8277 separate Disp16 and Disp32 flags. The same goes for
8278 Imm16 and Imm32. Removing them would probably clean
8279 up the code quite a lot. */
8280 if (flag_code != CODE_64BIT
8281 && (i.types[this_operand].bitfield.disp16
8282 || i.types[this_operand].bitfield.disp32))
8283 i.types[this_operand]
8284 = operand_type_xor (i.types[this_operand], disp16_32);
8285 }
8286 }
8287 }
24eab124 8288#endif
be05d201
L		 8289 }
8290
fc0763e6
JB		 8291 if (current_templates->start->opcode_modifier.isstring
8292 && !current_templates->start->opcode_modifier.immext
8293 && (current_templates->end[-1].opcode_modifier.isstring
8294 || i.mem_operands))
8295 {
8296 /* Memory operands of string insns are special in that they only allow
8297 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8298 const reg_entry *expected_reg;
8299 static const char *di_si[][2] =
8300 {
8301 { "esi", "edi" },
8302 { "si", "di" },
8303 { "rsi", "rdi" }
8304 };
8305 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8306
8307 kind = "string address";
8308
8309 if (current_templates->start->opcode_modifier.w)
8310 {
8311 i386_operand_type type = current_templates->end[-1].operand_types[0];
8312
8313 if (!type.bitfield.baseindex
8314 || ((!i.mem_operands != !intel_syntax)
8315 && current_templates->end[-1].operand_types[1]
8316 .bitfield.baseindex))
8317 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8318 expected_reg = hash_find (reg_hash,
8319 di_si[addr_mode][type.bitfield.esseg]);
8320
fc0763e6
JB		 8321 }
8322 else
be05d201 8323 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8324
be05d201
L		 8325 if (i.base_reg != expected_reg
8326 || i.index_reg
fc0763e6 8327 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8328 {
be05d201
L		 8329 /* The second memory operand must have the same size as
8330 the first one. */
8331 if (i.mem_operands
8332 && i.base_reg
8333 && !((addr_mode == CODE_64BIT
8334 && i.base_reg->reg_type.bitfield.reg64)
8335 || (addr_mode == CODE_32BIT
8336 ? i.base_reg->reg_type.bitfield.reg32
8337 : i.base_reg->reg_type.bitfield.reg16)))
8338 goto bad_address;
8339
fc0763e6
JB		 8340 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8341 operand_string,
8342 intel_syntax ? '[' : '(',
8343 register_prefix,
be05d201 8344 expected_reg->reg_name,
fc0763e6 8345 intel_syntax ? ']' : ')');
be05d201 8346 return 1;
fc0763e6 8347 }
be05d201
L		 8348 else
8349 return 1;
8350
8351bad_address:
8352 as_bad (_("`%s' is not a valid %s expression"),
8353 operand_string, kind);
8354 return 0;
3e73aa7c
JH		 8355 }
8356 else
8357 {
be05d201
L		 8358 if (addr_mode != CODE_16BIT)
8359 {
8360 /* 32-bit/64-bit checks. */
8361 if ((i.base_reg
8362 && (addr_mode == CODE_64BIT
8363 ? !i.base_reg->reg_type.bitfield.reg64
8364 : !i.base_reg->reg_type.bitfield.reg32)
8365 && (i.index_reg
8366 || (i.base_reg->reg_num
8367 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8368 || (i.index_reg
8369 && !i.index_reg->reg_type.bitfield.regxmm
8370 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8371 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8372 && ((addr_mode == CODE_64BIT
8373 ? !(i.index_reg->reg_type.bitfield.reg64
8374 || i.index_reg->reg_num == RegRiz)
8375 : !(i.index_reg->reg_type.bitfield.reg32
8376 || i.index_reg->reg_num == RegEiz))
8377 || !i.index_reg->reg_type.bitfield.baseindex)))
8378 goto bad_address;
8379 }
8380 else
3e73aa7c 8381 {
be05d201 8382 /* 16-bit checks. */
3e73aa7c 8383 if ((i.base_reg
40fb9820
L		 8384 && (!i.base_reg->reg_type.bitfield.reg16
8385 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8386 || (i.index_reg
40fb9820
L		 8387 && (!i.index_reg->reg_type.bitfield.reg16
8388 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8389 || !(i.base_reg
8390 && i.base_reg->reg_num < 6
8391 && i.index_reg->reg_num >= 6
8392 && i.log2_scale_factor == 0))))
be05d201 8393 goto bad_address;
3e73aa7c
JH		 8394 }
8395 }
be05d201 8396 return 1;
24eab124 8397}
252b5132 8398
43234a1e
L		 8399/* Handle vector immediates. */
8400
8401static int
8402RC_SAE_immediate (const char *imm_start)
8403{
8404 unsigned int match_found, j;
8405 const char *pstr = imm_start;
8406 expressionS *exp;
8407
8408 if (*pstr != '{')
8409 return 0;
8410
8411 pstr++;
8412 match_found = 0;
8413 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8414 {
8415 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8416 {
8417 if (!i.rounding)
8418 {
8419 rc_op.type = RC_NamesTable[j].type;
8420 rc_op.operand = this_operand;
8421 i.rounding = &rc_op;
8422 }
8423 else
8424 {
8425 as_bad (_("duplicated `%s'"), imm_start);
8426 return 0;
8427 }
8428 pstr += RC_NamesTable[j].len;
8429 match_found = 1;
8430 break;
8431 }
8432 }
8433 if (!match_found)
8434 return 0;
8435
8436 if (*pstr++ != '}')
8437 {
8438 as_bad (_("Missing '}': '%s'"), imm_start);
8439 return 0;
8440 }
8441 /* RC/SAE immediate string should contain nothing more. */;
8442 if (*pstr != 0)
8443 {
8444 as_bad (_("Junk after '}': '%s'"), imm_start);
8445 return 0;
8446 }
8447
8448 exp = &im_expressions[i.imm_operands++];
8449 i.op[this_operand].imms = exp;
8450
8451 exp->X_op = O_constant;
8452 exp->X_add_number = 0;
8453 exp->X_add_symbol = (symbolS *) 0;
8454 exp->X_op_symbol = (symbolS *) 0;
8455
8456 i.types[this_operand].bitfield.imm8 = 1;
8457 return 1;
8458}
8459
fc0763e6 8460/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8461 on error. */
252b5132 8462
252b5132 8463static int
a7619375 8464i386_att_operand (char *operand_string)
252b5132 8465{
af6bdddf
AM		 8466 const reg_entry *r;
8467 char *end_op;
24eab124 8468 char *op_string = operand_string;
252b5132 8469
24eab124 8470 if (is_space_char (*op_string))
252b5132
RH		 8471 ++op_string;
8472
24eab124 8473 /* We check for an absolute prefix (differentiating,
47926f60 8474 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8475 if (*op_string == ABSOLUTE_PREFIX)
8476 {
8477 ++op_string;
8478 if (is_space_char (*op_string))
8479 ++op_string;
40fb9820 8480 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8481 }
252b5132 8482
47926f60 8483 /* Check if operand is a register. */
4d1bb795 8484 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8485 {
40fb9820
L		 8486 i386_operand_type temp;
8487
24eab124
AM		 8488 /* Check for a segment override by searching for ':' after a
8489 segment register. */
8490 op_string = end_op;
8491 if (is_space_char (*op_string))
8492 ++op_string;
40fb9820
L		 8493 if (*op_string == ':'
8494 && (r->reg_type.bitfield.sreg2
8495 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8496 {
8497 switch (r->reg_num)
8498 {
8499 case 0:
8500 i.seg[i.mem_operands] = &es;
8501 break;
8502 case 1:
8503 i.seg[i.mem_operands] = &cs;
8504 break;
8505 case 2:
8506 i.seg[i.mem_operands] = &ss;
8507 break;
8508 case 3:
8509 i.seg[i.mem_operands] = &ds;
8510 break;
8511 case 4:
8512 i.seg[i.mem_operands] = &fs;
8513 break;
8514 case 5:
8515 i.seg[i.mem_operands] = &gs;
8516 break;
8517 }
252b5132 8518
24eab124 8519 /* Skip the ':' and whitespace. */
252b5132
RH		 8520 ++op_string;
8521 if (is_space_char (*op_string))
24eab124 8522 ++op_string;
252b5132 8523
24eab124
AM		 8524 if (!is_digit_char (*op_string)
8525 && !is_identifier_char (*op_string)
8526 && *op_string != '('
8527 && *op_string != ABSOLUTE_PREFIX)
8528 {
8529 as_bad (_("bad memory operand `%s'"), op_string);
8530 return 0;
8531 }
47926f60 8532 /* Handle case of %es:*foo. */
24eab124
AM		 8533 if (*op_string == ABSOLUTE_PREFIX)
8534 {
8535 ++op_string;
8536 if (is_space_char (*op_string))
8537 ++op_string;
40fb9820 8538 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8539 }
8540 goto do_memory_reference;
8541 }
43234a1e
L		 8542
8543 /* Handle vector operations. */
8544 if (*op_string == '{')
8545 {
8546 op_string = check_VecOperations (op_string, NULL);
8547 if (op_string == NULL)
8548 return 0;
8549 }
8550
24eab124
AM		 8551 if (*op_string)
8552 {
d0b47220 8553 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8554 return 0;
8555 }
40fb9820
L		 8556 temp = r->reg_type;
8557 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8558 i.types[this_operand] = operand_type_or (i.types[this_operand],
8559 temp);
7d5e4556 8560 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8561 i.op[this_operand].regs = r;
24eab124
AM		 8562 i.reg_operands++;
8563 }
af6bdddf
AM		 8564 else if (*op_string == REGISTER_PREFIX)
8565 {
8566 as_bad (_("bad register name `%s'"), op_string);
8567 return 0;
8568 }
24eab124 8569 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8570 {
24eab124 8571 ++op_string;
40fb9820 8572 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8573 {
d0b47220 8574 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8575 return 0;
8576 }
8577 if (!i386_immediate (op_string))
8578 return 0;
8579 }
43234a1e
L		 8580 else if (RC_SAE_immediate (operand_string))
8581 {
8582 /* If it is a RC or SAE immediate, do nothing. */
8583 ;
8584 }
24eab124
AM		 8585 else if (is_digit_char (*op_string)
8586 || is_identifier_char (*op_string)
e5cb08ac 8587 || *op_string == '(')
24eab124 8588 {
47926f60 8589 /* This is a memory reference of some sort. */
af6bdddf 8590 char *base_string;
252b5132 8591
47926f60 8592 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8593 char *displacement_string_start;
8594 char *displacement_string_end;
43234a1e 8595 char *vop_start;
252b5132 8596
24eab124 8597 do_memory_reference:
24eab124 8598 if ((i.mem_operands == 1
40fb9820 8599 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8600 || i.mem_operands == 2)
8601 {
8602 as_bad (_("too many memory references for `%s'"),
8603 current_templates->start->name);
8604 return 0;
8605 }
252b5132 8606
24eab124
AM		 8607 /* Check for base index form. We detect the base index form by
8608 looking for an ')' at the end of the operand, searching
8609 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8610 after the '('. */
af6bdddf 8611 base_string = op_string + strlen (op_string);
c3332e24 8612
43234a1e
L		 8613 /* Handle vector operations. */
8614 vop_start = strchr (op_string, '{');
8615 if (vop_start && vop_start < base_string)
8616 {
8617 if (check_VecOperations (vop_start, base_string) == NULL)
8618 return 0;
8619 base_string = vop_start;
8620 }
8621
af6bdddf
AM		 8622 --base_string;
8623 if (is_space_char (*base_string))
8624 --base_string;
252b5132 8625
47926f60 8626 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8627 displacement_string_start = op_string;
8628 displacement_string_end = base_string + 1;
252b5132 8629
24eab124
AM		 8630 if (*base_string == ')')
8631 {
af6bdddf 8632 char *temp_string;
24eab124
AM		 8633 unsigned int parens_balanced = 1;
8634 /* We've already checked that the number of left & right ()'s are
47926f60 8635 equal, so this loop will not be infinite. */
24eab124
AM		 8636 do
8637 {
8638 base_string--;
8639 if (*base_string == ')')
8640 parens_balanced++;
8641 if (*base_string == '(')
8642 parens_balanced--;
8643 }
8644 while (parens_balanced);
c3332e24 8645
af6bdddf 8646 temp_string = base_string;
c3332e24 8647
24eab124 8648 /* Skip past '(' and whitespace. */
252b5132
RH		 8649 ++base_string;
8650 if (is_space_char (*base_string))
24eab124 8651 ++base_string;
252b5132 8652
af6bdddf 8653 if (*base_string == ','
4eed87de
AM		 8654 || ((i.base_reg = parse_register (base_string, &end_op))
8655 != NULL))
252b5132 8656 {
af6bdddf 8657 displacement_string_end = temp_string;
252b5132 8658
40fb9820 8659 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8660
af6bdddf 8661 if (i.base_reg)
24eab124 8662 {
24eab124
AM		 8663 base_string = end_op;
8664 if (is_space_char (*base_string))
8665 ++base_string;
af6bdddf
AM		 8666 }
8667
8668 /* There may be an index reg or scale factor here. */
8669 if (*base_string == ',')
8670 {
8671 ++base_string;
8672 if (is_space_char (*base_string))
8673 ++base_string;
8674
4eed87de
AM		 8675 if ((i.index_reg = parse_register (base_string, &end_op))
8676 != NULL)
24eab124 8677 {
af6bdddf 8678 base_string = end_op;
24eab124
AM		 8679 if (is_space_char (*base_string))
8680 ++base_string;
af6bdddf
AM		 8681 if (*base_string == ',')
8682 {
8683 ++base_string;
8684 if (is_space_char (*base_string))
8685 ++base_string;
8686 }
e5cb08ac 8687 else if (*base_string != ')')
af6bdddf 8688 {
4eed87de
AM		 8689 as_bad (_("expecting `,' or `)' "
8690 "after index register in `%s'"),
af6bdddf
AM		 8691 operand_string);
8692 return 0;
8693 }
24eab124 8694 }
af6bdddf 8695 else if (*base_string == REGISTER_PREFIX)
24eab124 8696 {
f76bf5e0
L		 8697 end_op = strchr (base_string, ',');
8698 if (end_op)
8699 *end_op = '\0';
af6bdddf 8700 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8701 return 0;
8702 }
252b5132 8703
47926f60 8704 /* Check for scale factor. */
551c1ca1 8705 if (*base_string != ')')
af6bdddf 8706 {
551c1ca1
AM		 8707 char *end_scale = i386_scale (base_string);
8708
8709 if (!end_scale)
af6bdddf 8710 return 0;
24eab124 8711
551c1ca1 8712 base_string = end_scale;
af6bdddf
AM		 8713 if (is_space_char (*base_string))
8714 ++base_string;
8715 if (*base_string != ')')
8716 {
4eed87de
AM		 8717 as_bad (_("expecting `)' "
8718 "after scale factor in `%s'"),
af6bdddf
AM		 8719 operand_string);
8720 return 0;
8721 }
8722 }
8723 else if (!i.index_reg)
24eab124 8724 {
4eed87de
AM		 8725 as_bad (_("expecting index register or scale factor "
8726 "after `,'; got '%c'"),
af6bdddf 8727 *base_string);
24eab124
AM		 8728 return 0;
8729 }
8730 }
af6bdddf 8731 else if (*base_string != ')')
24eab124 8732 {
4eed87de
AM		 8733 as_bad (_("expecting `,' or `)' "
8734 "after base register in `%s'"),
af6bdddf 8735 operand_string);
24eab124
AM		 8736 return 0;
8737 }
c3332e24 8738 }
af6bdddf 8739 else if (*base_string == REGISTER_PREFIX)
c3332e24 8740 {
f76bf5e0
L		 8741 end_op = strchr (base_string, ',');
8742 if (end_op)
8743 *end_op = '\0';
af6bdddf 8744 as_bad (_("bad register name `%s'"), base_string);
24eab124 8745 return 0;
c3332e24 8746 }
24eab124
AM		 8747 }
8748
8749 /* If there's an expression beginning the operand, parse it,
8750 assuming displacement_string_start and
8751 displacement_string_end are meaningful. */
8752 if (displacement_string_start != displacement_string_end)
8753 {
8754 if (!i386_displacement (displacement_string_start,
8755 displacement_string_end))
8756 return 0;
8757 }
8758
8759 /* Special case for (%dx) while doing input/output op. */
8760 if (i.base_reg
0dfbf9d7
L		 8761 && operand_type_equal (&i.base_reg->reg_type,
8762 &reg16_inoutportreg)
24eab124
AM		 8763 && i.index_reg == 0
8764 && i.log2_scale_factor == 0
8765 && i.seg[i.mem_operands] == 0
40fb9820 8766 && !operand_type_check (i.types[this_operand], disp))
24eab124 8767 {
65da13b5 8768 i.types[this_operand] = inoutportreg;
24eab124
AM		 8769 return 1;
8770 }
8771
eecb386c
AM		 8772 if (i386_index_check (operand_string) == 0)
8773 return 0;
5c07affc 8774 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 8775 i.mem_operands++;
8776 }
8777 else
ce8a8b2f
AM		 8778 {
8779 /* It's not a memory operand; argh! */
24eab124
AM		 8780 as_bad (_("invalid char %s beginning operand %d `%s'"),
8781 output_invalid (*op_string),
8782 this_operand + 1,
8783 op_string);
8784 return 0;
8785 }
47926f60 8786 return 1; /* Normal return. */
252b5132
RH		 8787}
8788\f
fa94de6b
RM		 8789/* Calculate the maximum variable size (i.e., excluding fr_fix)
8790 that an rs_machine_dependent frag may reach. */
8791
8792unsigned int
8793i386_frag_max_var (fragS *frag)
8794{
8795 /* The only relaxable frags are for jumps.
8796 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8797 gas_assert (frag->fr_type == rs_machine_dependent);
8798 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8799}
8800
ee7fcc42
AM		 8801/* md_estimate_size_before_relax()
8802
8803 Called just before relax() for rs_machine_dependent frags. The x86
8804 assembler uses these frags to handle variable size jump
8805 instructions.
8806
8807 Any symbol that is now undefined will not become defined.
8808 Return the correct fr_subtype in the frag.
8809 Return the initial "guess for variable size of frag" to caller.
8810 The guess is actually the growth beyond the fixed part. Whatever
8811 we do to grow the fixed or variable part contributes to our
8812 returned value. */
8813
252b5132 8814int
7016a5d5 8815md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 8816{
252b5132 8817 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 8818 check for un-relaxable symbols. On an ELF system, we can't relax
8819 an externally visible symbol, because it may be overridden by a
8820 shared library. */
8821 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 8822#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8823 || (IS_ELF
31312f95 8824 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 8825 || S_IS_WEAK (fragP->fr_symbol)
8826 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
8827 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 8828#endif
8829#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 8830 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 8831 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 8832#endif
8833 )
252b5132 8834 {
b98ef147
AM		 8835 /* Symbol is undefined in this segment, or we need to keep a
8836 reloc so that weak symbols can be overridden. */
8837 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 8838 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 8839 unsigned char *opcode;
8840 int old_fr_fix;
f6af82bd 8841
ee7fcc42 8842 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 8843 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 8844 else if (size == 2)
f6af82bd
AM		 8845 reloc_type = BFD_RELOC_16_PCREL;
8846 else
8847 reloc_type = BFD_RELOC_32_PCREL;
252b5132 8848
ee7fcc42
AM		 8849 old_fr_fix = fragP->fr_fix;
8850 opcode = (unsigned char *) fragP->fr_opcode;
8851
fddf5b5b 8852 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 8853 {
fddf5b5b
AM		 8854 case UNCOND_JUMP:
8855 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 8856 opcode[0] = 0xe9;
252b5132 8857 fragP->fr_fix += size;
062cd5e7
AS		 8858 fix_new (fragP, old_fr_fix, size,
8859 fragP->fr_symbol,
8860 fragP->fr_offset, 1,
8861 reloc_type);
252b5132
RH		 8862 break;
8863
fddf5b5b 8864 case COND_JUMP86:
412167cb
AM		 8865 if (size == 2
8866 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 8867 {
8868 /* Negate the condition, and branch past an
8869 unconditional jump. */
8870 opcode[0] ^= 1;
8871 opcode[1] = 3;
8872 /* Insert an unconditional jump. */
8873 opcode[2] = 0xe9;
8874 /* We added two extra opcode bytes, and have a two byte
8875 offset. */
8876 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 8877 fix_new (fragP, old_fr_fix + 2, 2,
8878 fragP->fr_symbol,
8879 fragP->fr_offset, 1,
8880 reloc_type);
fddf5b5b
AM		 8881 break;
8882 }
8883 /* Fall through. */
8884
8885 case COND_JUMP:
412167cb
AM		 8886 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
8887 {
3e02c1cc
AM		 8888 fixS *fixP;
8889
412167cb 8890 fragP->fr_fix += 1;
3e02c1cc
AM		 8891 fixP = fix_new (fragP, old_fr_fix, 1,
8892 fragP->fr_symbol,
8893 fragP->fr_offset, 1,
8894 BFD_RELOC_8_PCREL);
8895 fixP->fx_signed = 1;
412167cb
AM		 8896 break;
8897 }
93c2a809 8898
24eab124 8899 /* This changes the byte-displacement jump 0x7N
fddf5b5b 8900 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 8901 opcode[1] = opcode[0] + 0x10;
f6af82bd 8902 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 8903 /* We've added an opcode byte. */
8904 fragP->fr_fix += 1 + size;
062cd5e7
AS		 8905 fix_new (fragP, old_fr_fix + 1, size,
8906 fragP->fr_symbol,
8907 fragP->fr_offset, 1,
8908 reloc_type);
252b5132 8909 break;
fddf5b5b
AM		 8910
8911 default:
8912 BAD_CASE (fragP->fr_subtype);
8913 break;
252b5132
RH		 8914 }
8915 frag_wane (fragP);
ee7fcc42 8916 return fragP->fr_fix - old_fr_fix;
252b5132 8917 }
93c2a809 8918
93c2a809
AM		 8919 /* Guess size depending on current relax state. Initially the relax
8920 state will correspond to a short jump and we return 1, because
8921 the variable part of the frag (the branch offset) is one byte
8922 long. However, we can relax a section more than once and in that
8923 case we must either set fr_subtype back to the unrelaxed state,
8924 or return the value for the appropriate branch. */
8925 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 8926}
8927
47926f60
KH		 8928/* Called after relax() is finished.
8929
8930 In: Address of frag.
8931 fr_type == rs_machine_dependent.
8932 fr_subtype is what the address relaxed to.
8933
8934 Out: Any fixSs and constants are set up.
8935 Caller will turn frag into a ".space 0". */
8936
252b5132 8937void
7016a5d5
TG		 8938md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
8939 fragS *fragP)
252b5132 8940{
29b0f896 8941 unsigned char *opcode;
252b5132 8942 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 8943 offsetT target_address;
8944 offsetT opcode_address;
252b5132 8945 unsigned int extension = 0;
847f7ad4 8946 offsetT displacement_from_opcode_start;
252b5132
RH		 8947
8948 opcode = (unsigned char *) fragP->fr_opcode;
8949
47926f60 8950 /* Address we want to reach in file space. */
252b5132 8951 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 8952
47926f60 8953 /* Address opcode resides at in file space. */
252b5132
RH		 8954 opcode_address = fragP->fr_address + fragP->fr_fix;
8955
47926f60 8956 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 8957 displacement_from_opcode_start = target_address - opcode_address;
8958
fddf5b5b 8959 if ((fragP->fr_subtype & BIG) == 0)
252b5132 8960 {
47926f60
KH		 8961 /* Don't have to change opcode. */
8962 extension = 1; /* 1 opcode + 1 displacement */
252b5132 8963 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 8964 }
8965 else
8966 {
8967 if (no_cond_jump_promotion
8968 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 8969 as_warn_where (fragP->fr_file, fragP->fr_line,
8970 _("long jump required"));
252b5132 8971
fddf5b5b
AM		 8972 switch (fragP->fr_subtype)
8973 {
8974 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
8975 extension = 4; /* 1 opcode + 4 displacement */
8976 opcode[0] = 0xe9;
8977 where_to_put_displacement = &opcode[1];
8978 break;
252b5132 8979
fddf5b5b
AM		 8980 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
8981 extension = 2; /* 1 opcode + 2 displacement */
8982 opcode[0] = 0xe9;
8983 where_to_put_displacement = &opcode[1];
8984 break;
252b5132 8985
fddf5b5b
AM		 8986 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
8987 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
8988 extension = 5; /* 2 opcode + 4 displacement */
8989 opcode[1] = opcode[0] + 0x10;
8990 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
8991 where_to_put_displacement = &opcode[2];
8992 break;
252b5132 8993
fddf5b5b
AM		 8994 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
8995 extension = 3; /* 2 opcode + 2 displacement */
8996 opcode[1] = opcode[0] + 0x10;
8997 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
8998 where_to_put_displacement = &opcode[2];
8999 break;
252b5132 9000
fddf5b5b
AM		 9001 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9002 extension = 4;
9003 opcode[0] ^= 1;
9004 opcode[1] = 3;
9005 opcode[2] = 0xe9;
9006 where_to_put_displacement = &opcode[3];
9007 break;
9008
9009 default:
9010 BAD_CASE (fragP->fr_subtype);
9011 break;
9012 }
252b5132 9013 }
fddf5b5b 9014
7b81dfbb
AJ		 9015 /* If size if less then four we are sure that the operand fits,
9016 but if it's 4, then it could be that the displacement is larger
9017 then -/+ 2GB. */
9018 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9019 && object_64bit
9020 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9021 + ((addressT) 1 << 31))
9022 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9023 {
9024 as_bad_where (fragP->fr_file, fragP->fr_line,
9025 _("jump target out of range"));
9026 /* Make us emit 0. */
9027 displacement_from_opcode_start = extension;
9028 }
47926f60 9029 /* Now put displacement after opcode. */
252b5132
RH		 9030 md_number_to_chars ((char *) where_to_put_displacement,
9031 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9032 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9033 fragP->fr_fix += extension;
9034}
9035\f
7016a5d5 9036/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9037 by our caller that we have all the info we need to fix it up.
9038
7016a5d5
TG		 9039 Parameter valP is the pointer to the value of the bits.
9040
252b5132
RH		 9041 On the 386, immediates, displacements, and data pointers are all in
9042 the same (little-endian) format, so we don't need to care about which
9043 we are handling. */
9044
94f592af 9045void
7016a5d5 9046md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9047{
94f592af 9048 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9049 valueT value = *valP;
252b5132 9050
f86103b7 9051#if !defined (TE_Mach)
93382f6d
AM		 9052 if (fixP->fx_pcrel)
9053 {
9054 switch (fixP->fx_r_type)
9055 {
5865bb77
ILT		 9056 default:
9057 break;
9058
d6ab8113
JB		 9059 case BFD_RELOC_64:
9060 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9061 break;
93382f6d 9062 case BFD_RELOC_32:
ae8887b5 9063 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9064 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9065 break;
9066 case BFD_RELOC_16:
9067 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9068 break;
9069 case BFD_RELOC_8:
9070 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9071 break;
9072 }
9073 }
252b5132 9074
a161fe53 9075 if (fixP->fx_addsy != NULL
31312f95 9076 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9077 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9078 || fixP->fx_r_type == BFD_RELOC_16_PCREL
c3320543
L		 9079 || fixP->fx_r_type == BFD_RELOC_8_PCREL
9080 || fixP->fx_r_type == BFD_RELOC_X86_64_PC32_BND)
31312f95 9081 && !use_rela_relocations)
252b5132 9082 {
31312f95
AM		 9083 /* This is a hack. There should be a better way to handle this.
9084 This covers for the fact that bfd_install_relocation will
9085 subtract the current location (for partial_inplace, PC relative
9086 relocations); see more below. */
252b5132 9087#ifndef OBJ_AOUT
718ddfc0 9088 if (IS_ELF
252b5132
RH		 9089#ifdef TE_PE
9090 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9091#endif
9092 )
9093 value += fixP->fx_where + fixP->fx_frag->fr_address;
9094#endif
9095#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9096 if (IS_ELF)
252b5132 9097 {
6539b54b 9098 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9099
6539b54b 9100 if ((sym_seg == seg
2f66722d 9101 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9102 && sym_seg != absolute_section))
af65af87 9103 && !generic_force_reloc (fixP))
2f66722d
AM		 9104 {
9105 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9106 bfd_install_relocation subtracts them out again. I think
9107 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9108 it. FIXME. */
9109 value += fixP->fx_where + fixP->fx_frag->fr_address;
9110 }
252b5132
RH		 9111 }
9112#endif
9113#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9114 /* For some reason, the PE format does not store a
9115 section address offset for a PC relative symbol. */
9116 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9117 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9118 value += md_pcrel_from (fixP);
9119#endif
9120 }
fbeb56a4
DK		 9121#if defined (OBJ_COFF) && defined (TE_PE)
9122 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9123 {
9124 value -= S_GET_VALUE (fixP->fx_addsy);
9125 }
9126#endif
252b5132
RH		 9127
9128 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9129 and we must not disappoint it. */
252b5132 9130#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9131 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9132 switch (fixP->fx_r_type)
9133 {
9134 case BFD_RELOC_386_PLT32:
3e73aa7c 9135 case BFD_RELOC_X86_64_PLT32:
c3320543 9136 case BFD_RELOC_X86_64_PLT32_BND:
47926f60
KH		 9137 /* Make the jump instruction point to the address of the operand. At
9138 runtime we merely add the offset to the actual PLT entry. */
9139 value = -4;
9140 break;
31312f95 9141
13ae64f3
JJ		 9142 case BFD_RELOC_386_TLS_GD:
9143 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9144 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9145 case BFD_RELOC_386_TLS_IE:
9146 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9147 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9148 case BFD_RELOC_X86_64_TLSGD:
9149 case BFD_RELOC_X86_64_TLSLD:
9150 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9151 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9152 value = 0; /* Fully resolved at runtime. No addend. */
9153 /* Fallthrough */
9154 case BFD_RELOC_386_TLS_LE:
9155 case BFD_RELOC_386_TLS_LDO_32:
9156 case BFD_RELOC_386_TLS_LE_32:
9157 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9158 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9159 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9160 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9161 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9162 break;
9163
67a4f2b7
AO		 9164 case BFD_RELOC_386_TLS_DESC_CALL:
9165 case BFD_RELOC_X86_64_TLSDESC_CALL:
9166 value = 0; /* Fully resolved at runtime. No addend. */
9167 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9168 fixP->fx_done = 0;
9169 return;
9170
00f7efb6
JJ		 9171 case BFD_RELOC_386_GOT32:
9172 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 9173 value = 0; /* Fully resolved at runtime. No addend. */
9174 break;
47926f60
KH		 9175
9176 case BFD_RELOC_VTABLE_INHERIT:
9177 case BFD_RELOC_VTABLE_ENTRY:
9178 fixP->fx_done = 0;
94f592af 9179 return;
47926f60
KH		 9180
9181 default:
9182 break;
9183 }
9184#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9185 *valP = value;
f86103b7 9186#endif /* !defined (TE_Mach) */
3e73aa7c 9187
3e73aa7c 9188 /* Are we finished with this relocation now? */
c6682705 9189 if (fixP->fx_addsy == NULL)
3e73aa7c 9190 fixP->fx_done = 1;
fbeb56a4
DK		 9191#if defined (OBJ_COFF) && defined (TE_PE)
9192 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9193 {
9194 fixP->fx_done = 0;
9195 /* Remember value for tc_gen_reloc. */
9196 fixP->fx_addnumber = value;
9197 /* Clear out the frag for now. */
9198 value = 0;
9199 }
9200#endif
3e73aa7c
JH		 9201 else if (use_rela_relocations)
9202 {
9203 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9204 /* Remember value for tc_gen_reloc. */
9205 fixP->fx_addnumber = value;
3e73aa7c
JH		 9206 value = 0;
9207 }
f86103b7 9208
94f592af 9209 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9210}
252b5132 9211\f
252b5132 9212char *
499ac353 9213md_atof (int type, char *litP, int *sizeP)
252b5132 9214{
499ac353
NC		 9215 /* This outputs the LITTLENUMs in REVERSE order;
9216 in accord with the bigendian 386. */
9217 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9218}
9219\f
2d545b82 9220static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9221
252b5132 9222static char *
e3bb37b5 9223output_invalid (int c)
252b5132 9224{
3882b010 9225 if (ISPRINT (c))
f9f21a03
L		 9226 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9227 "'%c'", c);
252b5132 9228 else
f9f21a03 9229 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9230 "(0x%x)", (unsigned char) c);
252b5132
RH		 9231 return output_invalid_buf;
9232}
9233
af6bdddf 9234/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9235
9236static const reg_entry *
4d1bb795 9237parse_real_register (char *reg_string, char **end_op)
252b5132 9238{
af6bdddf
AM		 9239 char *s = reg_string;
9240 char *p;
252b5132
RH		 9241 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9242 const reg_entry *r;
9243
9244 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9245 if (*s == REGISTER_PREFIX)
9246 ++s;
9247
9248 if (is_space_char (*s))
9249 ++s;
9250
9251 p = reg_name_given;
af6bdddf 9252 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9253 {
9254 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9255 return (const reg_entry *) NULL;
9256 s++;
252b5132
RH		 9257 }
9258
6588847e
DN		 9259 /* For naked regs, make sure that we are not dealing with an identifier.
9260 This prevents confusing an identifier like `eax_var' with register
9261 `eax'. */
9262 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9263 return (const reg_entry *) NULL;
9264
af6bdddf 9265 *end_op = s;
252b5132
RH		 9266
9267 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9268
5f47d35b 9269 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9270 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9271 {
5f47d35b
AM		 9272 if (is_space_char (*s))
9273 ++s;
9274 if (*s == '(')
9275 {
af6bdddf 9276 ++s;
5f47d35b
AM		 9277 if (is_space_char (*s))
9278 ++s;
9279 if (*s >= '0' && *s <= '7')
9280 {
db557034 9281 int fpr = *s - '0';
af6bdddf 9282 ++s;
5f47d35b
AM		 9283 if (is_space_char (*s))
9284 ++s;
9285 if (*s == ')')
9286 {
9287 *end_op = s + 1;
1e9cc1c2 9288 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9289 know (r);
9290 return r + fpr;
5f47d35b 9291 }
5f47d35b 9292 }
47926f60 9293 /* We have "%st(" then garbage. */
5f47d35b
AM		 9294 return (const reg_entry *) NULL;
9295 }
9296 }
9297
a60de03c
JB		 9298 if (r == NULL || allow_pseudo_reg)
9299 return r;
9300
0dfbf9d7 9301 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9302 return (const reg_entry *) NULL;
9303
192dc9c6
JB		 9304 if ((r->reg_type.bitfield.reg32
9305 || r->reg_type.bitfield.sreg3
9306 || r->reg_type.bitfield.control
9307 || r->reg_type.bitfield.debug
9308 || r->reg_type.bitfield.test)
9309 && !cpu_arch_flags.bitfield.cpui386)
9310 return (const reg_entry *) NULL;
9311
309d3373
JB		 9312 if (r->reg_type.bitfield.floatreg
9313 && !cpu_arch_flags.bitfield.cpu8087
9314 && !cpu_arch_flags.bitfield.cpu287
9315 && !cpu_arch_flags.bitfield.cpu387)
9316 return (const reg_entry *) NULL;
9317
192dc9c6
JB		 9318 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9319 return (const reg_entry *) NULL;
9320
9321 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9322 return (const reg_entry *) NULL;
9323
40f12533
L		 9324 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9325 return (const reg_entry *) NULL;
9326
43234a1e
L		 9327 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9328 && !cpu_arch_flags.bitfield.cpuavx512f)
9329 return (const reg_entry *) NULL;
9330
db51cc60 9331 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9332 if (!allow_index_reg
db51cc60
L		 9333 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9334 return (const reg_entry *) NULL;
9335
43234a1e
L		 9336 /* Upper 16 vector register is only available with VREX in 64bit
9337 mode. */
9338 if ((r->reg_flags & RegVRex))
9339 {
9340 if (!cpu_arch_flags.bitfield.cpuvrex
9341 || flag_code != CODE_64BIT)
9342 return (const reg_entry *) NULL;
9343
9344 i.need_vrex = 1;
9345 }
9346
a60de03c
JB		 9347 if (((r->reg_flags & (RegRex64 | RegRex))
9348 || r->reg_type.bitfield.reg64)
40fb9820 9349 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9350 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9351 && flag_code != CODE_64BIT)
20f0a1fc 9352 return (const reg_entry *) NULL;
1ae00879 9353
b7240065
JB		 9354 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9355 return (const reg_entry *) NULL;
9356
252b5132
RH		 9357 return r;
9358}
4d1bb795
JB		 9359
9360/* REG_STRING starts *before* REGISTER_PREFIX. */
9361
9362static const reg_entry *
9363parse_register (char *reg_string, char **end_op)
9364{
9365 const reg_entry *r;
9366
9367 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9368 r = parse_real_register (reg_string, end_op);
9369 else
9370 r = NULL;
9371 if (!r)
9372 {
9373 char *save = input_line_pointer;
9374 char c;
9375 symbolS *symbolP;
9376
9377 input_line_pointer = reg_string;
9378 c = get_symbol_end ();
9379 symbolP = symbol_find (reg_string);
9380 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9381 {
9382 const expressionS *e = symbol_get_value_expression (symbolP);
9383
0398aac5 9384 know (e->X_op == O_register);
4eed87de 9385 know (e->X_add_number >= 0
c3fe08fa 9386 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 9387 r = i386_regtab + e->X_add_number;
9388 *end_op = input_line_pointer;
9389 }
9390 *input_line_pointer = c;
9391 input_line_pointer = save;
9392 }
9393 return r;
9394}
9395
9396int
9397i386_parse_name (char *name, expressionS *e, char *nextcharP)
9398{
9399 const reg_entry *r;
9400 char *end = input_line_pointer;
9401
9402 *end = *nextcharP;
9403 r = parse_register (name, &input_line_pointer);
9404 if (r && end <= input_line_pointer)
9405 {
9406 *nextcharP = *input_line_pointer;
9407 *input_line_pointer = 0;
9408 e->X_op = O_register;
9409 e->X_add_number = r - i386_regtab;
9410 return 1;
9411 }
9412 input_line_pointer = end;
9413 *end = 0;
ee86248c 9414 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9415}
9416
9417void
9418md_operand (expressionS *e)
9419{
ee86248c
JB		 9420 char *end;
9421 const reg_entry *r;
4d1bb795 9422
ee86248c
JB		 9423 switch (*input_line_pointer)
9424 {
9425 case REGISTER_PREFIX:
9426 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9427 if (r)
9428 {
9429 e->X_op = O_register;
9430 e->X_add_number = r - i386_regtab;
9431 input_line_pointer = end;
9432 }
ee86248c
JB		 9433 break;
9434
9435 case '[':
9c2799c2 9436 gas_assert (intel_syntax);
ee86248c
JB		 9437 end = input_line_pointer++;
9438 expression (e);
9439 if (*input_line_pointer == ']')
9440 {
9441 ++input_line_pointer;
9442 e->X_op_symbol = make_expr_symbol (e);
9443 e->X_add_symbol = NULL;
9444 e->X_add_number = 0;
9445 e->X_op = O_index;
9446 }
9447 else
9448 {
9449 e->X_op = O_absent;
9450 input_line_pointer = end;
9451 }
9452 break;
4d1bb795
JB		 9453 }
9454}
9455
252b5132 9456\f
4cc782b5 9457#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9458const char *md_shortopts = "kVQ:sqn";
252b5132 9459#else
12b55ccc 9460const char *md_shortopts = "qn";
252b5132 9461#endif
6e0b89ee 9462
3e73aa7c 9463#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9464#define OPTION_64 (OPTION_MD_BASE + 1)
9465#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9466#define OPTION_MARCH (OPTION_MD_BASE + 3)
9467#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9468#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9469#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9470#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9471#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9472#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9473#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9474#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9475#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9476#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9477#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9478#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9479#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9480#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
b3b91714 9481
99ad8390
NC		 9482struct option md_longopts[] =
9483{
3e73aa7c 9484 {"32", no_argument, NULL, OPTION_32},
321098a5 9485#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9486 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9487 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9488#endif
9489#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9490 {"x32", no_argument, NULL, OPTION_X32},
6e0b89ee 9491#endif
b3b91714 9492 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9493 {"march", required_argument, NULL, OPTION_MARCH},
9494 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9495 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9496 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9497 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9498 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9499 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9500 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9501 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9502 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9503 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9504 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9505 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9506 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
252b5132
RH		 9507 {NULL, no_argument, NULL, 0}
9508};
9509size_t md_longopts_size = sizeof (md_longopts);
9510
9511int
9103f4f4 9512md_parse_option (int c, char *arg)
252b5132 9513{
91d6fa6a 9514 unsigned int j;
6305a203 9515 char *arch, *next;
9103f4f4 9516
252b5132
RH		 9517 switch (c)
9518 {
12b55ccc
L		 9519 case 'n':
9520 optimize_align_code = 0;
9521 break;
9522
a38cf1db
AM		 9523 case 'q':
9524 quiet_warnings = 1;
252b5132
RH		 9525 break;
9526
9527#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9528 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9529 should be emitted or not. FIXME: Not implemented. */
9530 case 'Q':
252b5132
RH		 9531 break;
9532
9533 /* -V: SVR4 argument to print version ID. */
9534 case 'V':
9535 print_version_id ();
9536 break;
9537
a38cf1db
AM		 9538 /* -k: Ignore for FreeBSD compatibility. */
9539 case 'k':
252b5132 9540 break;
4cc782b5
ILT		 9541
9542 case 's':
9543 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9544 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9545 break;
99ad8390 9546#endif
321098a5 9547#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9548 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9549 case OPTION_64:
9550 {
9551 const char **list, **l;
9552
3e73aa7c
JH		 9553 list = bfd_target_list ();
9554 for (l = list; *l != NULL; l++)
8620418b 9555 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9556 || strcmp (*l, "coff-x86-64") == 0
9557 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9558 || strcmp (*l, "pei-x86-64") == 0
9559 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9560 {
9561 default_arch = "x86_64";
9562 break;
9563 }
3e73aa7c 9564 if (*l == NULL)
2b5d6a91 9565 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9566 free (list);
9567 }
9568 break;
9569#endif
252b5132 9570
351f65ca 9571#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9572 case OPTION_X32:
351f65ca
L		 9573 if (IS_ELF)
9574 {
9575 const char **list, **l;
9576
9577 list = bfd_target_list ();
9578 for (l = list; *l != NULL; l++)
9579 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9580 {
9581 default_arch = "x86_64:32";
9582 break;
9583 }
9584 if (*l == NULL)
2b5d6a91 9585 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9586 free (list);
9587 }
9588 else
9589 as_fatal (_("32bit x86_64 is only supported for ELF"));
9590 break;
9591#endif
9592
6e0b89ee
AM		 9593 case OPTION_32:
9594 default_arch = "i386";
9595 break;
9596
b3b91714
AM		 9597 case OPTION_DIVIDE:
9598#ifdef SVR4_COMMENT_CHARS
9599 {
9600 char *n, *t;
9601 const char *s;
9602
9603 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
9604 t = n;
9605 for (s = i386_comment_chars; *s != '\0'; s++)
9606 if (*s != '/')
9607 *t++ = *s;
9608 *t = '\0';
9609 i386_comment_chars = n;
9610 }
9611#endif
9612 break;
9613
9103f4f4 9614 case OPTION_MARCH:
6305a203
L		 9615 arch = xstrdup (arg);
9616 do
9103f4f4 9617 {
6305a203 9618 if (*arch == '.')
2b5d6a91 9619 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9620 next = strchr (arch, '+');
9621 if (next)
9622 *next++ = '\0';
91d6fa6a 9623 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9624 {
91d6fa6a 9625 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9626 {
6305a203 9627 /* Processor. */
1ded5609
JB		 9628 if (! cpu_arch[j].flags.bitfield.cpui386)
9629 continue;
9630
91d6fa6a 9631 cpu_arch_name = cpu_arch[j].name;
6305a203 9632 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9633 cpu_arch_flags = cpu_arch[j].flags;
9634 cpu_arch_isa = cpu_arch[j].type;
9635 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9636 if (!cpu_arch_tune_set)
9637 {
9638 cpu_arch_tune = cpu_arch_isa;
9639 cpu_arch_tune_flags = cpu_arch_isa_flags;
9640 }
9641 break;
9642 }
91d6fa6a
NC		 9643 else if (*cpu_arch [j].name == '.'
9644 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9645 {
9646 /* ISA entension. */
9647 i386_cpu_flags flags;
309d3373 9648
49021df2 9649 if (!cpu_arch[j].negated)
309d3373 9650 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 9651 cpu_arch[j].flags);
309d3373
JB		 9652 else
9653 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 9654 cpu_arch[j].flags);
0dfbf9d7 9655 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 9656 {
9657 if (cpu_sub_arch_name)
9658 {
9659 char *name = cpu_sub_arch_name;
9660 cpu_sub_arch_name = concat (name,
91d6fa6a 9661 cpu_arch[j].name,
1bf57e9f 9662 (const char *) NULL);
6305a203
L		 9663 free (name);
9664 }
9665 else
91d6fa6a 9666 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 9667 cpu_arch_flags = flags;
a586129e 9668 cpu_arch_isa_flags = flags;
6305a203
L		 9669 }
9670 break;
ccc9c027 9671 }
9103f4f4 9672 }
6305a203 9673
91d6fa6a 9674 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9675 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9676
9677 arch = next;
9103f4f4 9678 }
6305a203 9679 while (next != NULL );
9103f4f4
L		 9680 break;
9681
9682 case OPTION_MTUNE:
9683 if (*arg == '.')
2b5d6a91 9684 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 9685 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9686 {
91d6fa6a 9687 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 9688 {
ccc9c027 9689 cpu_arch_tune_set = 1;
91d6fa6a
NC		 9690 cpu_arch_tune = cpu_arch [j].type;
9691 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 9692 break;
9693 }
9694 }
91d6fa6a 9695 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9696 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 9697 break;
9698
1efbbeb4
L		 9699 case OPTION_MMNEMONIC:
9700 if (strcasecmp (arg, "att") == 0)
9701 intel_mnemonic = 0;
9702 else if (strcasecmp (arg, "intel") == 0)
9703 intel_mnemonic = 1;
9704 else
2b5d6a91 9705 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 9706 break;
9707
9708 case OPTION_MSYNTAX:
9709 if (strcasecmp (arg, "att") == 0)
9710 intel_syntax = 0;
9711 else if (strcasecmp (arg, "intel") == 0)
9712 intel_syntax = 1;
9713 else
2b5d6a91 9714 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 9715 break;
9716
9717 case OPTION_MINDEX_REG:
9718 allow_index_reg = 1;
9719 break;
9720
9721 case OPTION_MNAKED_REG:
9722 allow_naked_reg = 1;
9723 break;
9724
9725 case OPTION_MOLD_GCC:
9726 old_gcc = 1;
1efbbeb4
L		 9727 break;
9728
c0f3af97
L		 9729 case OPTION_MSSE2AVX:
9730 sse2avx = 1;
9731 break;
9732
daf50ae7
L		 9733 case OPTION_MSSE_CHECK:
9734 if (strcasecmp (arg, "error") == 0)
7bab8ab5 9735 sse_check = check_error;
daf50ae7 9736 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 9737 sse_check = check_warning;
daf50ae7 9738 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 9739 sse_check = check_none;
daf50ae7 9740 else
2b5d6a91 9741 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 9742 break;
9743
7bab8ab5
JB		 9744 case OPTION_MOPERAND_CHECK:
9745 if (strcasecmp (arg, "error") == 0)
9746 operand_check = check_error;
9747 else if (strcasecmp (arg, "warning") == 0)
9748 operand_check = check_warning;
9749 else if (strcasecmp (arg, "none") == 0)
9750 operand_check = check_none;
9751 else
9752 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
9753 break;
9754
539f890d
L		 9755 case OPTION_MAVXSCALAR:
9756 if (strcasecmp (arg, "128") == 0)
9757 avxscalar = vex128;
9758 else if (strcasecmp (arg, "256") == 0)
9759 avxscalar = vex256;
9760 else
2b5d6a91 9761 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 9762 break;
9763
7e8b059b
L		 9764 case OPTION_MADD_BND_PREFIX:
9765 add_bnd_prefix = 1;
9766 break;
9767
43234a1e
L		 9768 case OPTION_MEVEXLIG:
9769 if (strcmp (arg, "128") == 0)
9770 evexlig = evexl128;
9771 else if (strcmp (arg, "256") == 0)
9772 evexlig = evexl256;
9773 else if (strcmp (arg, "512") == 0)
9774 evexlig = evexl512;
9775 else
9776 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
9777 break;
9778
9779 case OPTION_MEVEXWIG:
9780 if (strcmp (arg, "0") == 0)
9781 evexwig = evexw0;
9782 else if (strcmp (arg, "1") == 0)
9783 evexwig = evexw1;
9784 else
9785 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
9786 break;
9787
252b5132
RH		 9788 default:
9789 return 0;
9790 }
9791 return 1;
9792}
9793
8a2c8fef
L		 9794#define MESSAGE_TEMPLATE \
9795" "
9796
9797static void
1ded5609 9798show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 9799{
9800 static char message[] = MESSAGE_TEMPLATE;
9801 char *start = message + 27;
9802 char *p;
9803 int size = sizeof (MESSAGE_TEMPLATE);
9804 int left;
9805 const char *name;
9806 int len;
9807 unsigned int j;
9808
9809 p = start;
9810 left = size - (start - message);
9811 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9812 {
9813 /* Should it be skipped? */
9814 if (cpu_arch [j].skip)
9815 continue;
9816
9817 name = cpu_arch [j].name;
9818 len = cpu_arch [j].len;
9819 if (*name == '.')
9820 {
9821 /* It is an extension. Skip if we aren't asked to show it. */
9822 if (ext)
9823 {
9824 name++;
9825 len--;
9826 }
9827 else
9828 continue;
9829 }
9830 else if (ext)
9831 {
9832 /* It is an processor. Skip if we show only extension. */
9833 continue;
9834 }
1ded5609
JB		 9835 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
9836 {
9837 /* It is an impossible processor - skip. */
9838 continue;
9839 }
8a2c8fef
L		 9840
9841 /* Reserve 2 spaces for ", " or ",\0" */
9842 left -= len + 2;
9843
9844 /* Check if there is any room. */
9845 if (left >= 0)
9846 {
9847 if (p != start)
9848 {
9849 *p++ = ',';
9850 *p++ = ' ';
9851 }
9852 p = mempcpy (p, name, len);
9853 }
9854 else
9855 {
9856 /* Output the current message now and start a new one. */
9857 *p++ = ',';
9858 *p = '\0';
9859 fprintf (stream, "%s\n", message);
9860 p = start;
9861 left = size - (start - message) - len - 2;
8d63c93e 9862
8a2c8fef
L		 9863 gas_assert (left >= 0);
9864
9865 p = mempcpy (p, name, len);
9866 }
9867 }
9868
9869 *p = '\0';
9870 fprintf (stream, "%s\n", message);
9871}
9872
252b5132 9873void
8a2c8fef 9874md_show_usage (FILE *stream)
252b5132 9875{
4cc782b5
ILT		 9876#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9877 fprintf (stream, _("\
a38cf1db
AM		 9878 -Q ignored\n\
9879 -V print assembler version number\n\
b3b91714
AM		 9880 -k ignored\n"));
9881#endif
9882 fprintf (stream, _("\
12b55ccc 9883 -n Do not optimize code alignment\n\
b3b91714
AM		 9884 -q quieten some warnings\n"));
9885#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9886 fprintf (stream, _("\
a38cf1db 9887 -s ignored\n"));
b3b91714 9888#endif
321098a5
L		 9889#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9890 || defined (TE_PE) || defined (TE_PEP))
751d281c 9891 fprintf (stream, _("\
570561f7 9892 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 9893#endif
b3b91714
AM		 9894#ifdef SVR4_COMMENT_CHARS
9895 fprintf (stream, _("\
9896 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 9897#else
9898 fprintf (stream, _("\
b3b91714 9899 --divide ignored\n"));
4cc782b5 9900#endif
9103f4f4 9901 fprintf (stream, _("\
6305a203 9902 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 9903 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 9904 show_arch (stream, 0, 1);
8a2c8fef
L		 9905 fprintf (stream, _("\
9906 EXTENSION is combination of:\n"));
1ded5609 9907 show_arch (stream, 1, 0);
6305a203 9908 fprintf (stream, _("\
8a2c8fef 9909 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 9910 show_arch (stream, 0, 0);
ba104c83 9911 fprintf (stream, _("\
c0f3af97
L		 9912 -msse2avx encode SSE instructions with VEX prefix\n"));
9913 fprintf (stream, _("\
daf50ae7
L		 9914 -msse-check=[none|error|warning]\n\
9915 check SSE instructions\n"));
9916 fprintf (stream, _("\
7bab8ab5
JB		 9917 -moperand-check=[none|error|warning]\n\
9918 check operand combinations for validity\n"));
9919 fprintf (stream, _("\
539f890d
L		 9920 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
9921 length\n"));
9922 fprintf (stream, _("\
43234a1e
L		 9923 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
9924 length\n"));
9925 fprintf (stream, _("\
9926 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
9927 for EVEX.W bit ignored instructions\n"));
9928 fprintf (stream, _("\
ba104c83
L		 9929 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
9930 fprintf (stream, _("\
9931 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
9932 fprintf (stream, _("\
9933 -mindex-reg support pseudo index registers\n"));
9934 fprintf (stream, _("\
9935 -mnaked-reg don't require `%%' prefix for registers\n"));
9936 fprintf (stream, _("\
9937 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 9938 fprintf (stream, _("\
9939 -madd-bnd-prefix add BND prefix for all valid branches\n"));
252b5132
RH		 9940}
9941
3e73aa7c 9942#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 9943 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 9944 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 9945
9946/* Pick the target format to use. */
9947
47926f60 9948const char *
e3bb37b5 9949i386_target_format (void)
252b5132 9950{
351f65ca
L		 9951 if (!strncmp (default_arch, "x86_64", 6))
9952 {
9953 update_code_flag (CODE_64BIT, 1);
9954 if (default_arch[6] == '\0')
7f56bc95 9955 x86_elf_abi = X86_64_ABI;
351f65ca 9956 else
7f56bc95 9957 x86_elf_abi = X86_64_X32_ABI;
351f65ca 9958 }
3e73aa7c 9959 else if (!strcmp (default_arch, "i386"))
78f12dd3 9960 update_code_flag (CODE_32BIT, 1);
3e73aa7c 9961 else
2b5d6a91 9962 as_fatal (_("unknown architecture"));
89507696
JB		 9963
9964 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
9965 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
9966 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
9967 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
9968
252b5132
RH		 9969 switch (OUTPUT_FLAVOR)
9970 {
9384f2ff 9971#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 9972 case bfd_target_aout_flavour:
47926f60 9973 return AOUT_TARGET_FORMAT;
4c63da97 9974#endif
9384f2ff
AM		 9975#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
9976# if defined (TE_PE) || defined (TE_PEP)
9977 case bfd_target_coff_flavour:
9978 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
9979# elif defined (TE_GO32)
0561d57c
JK		 9980 case bfd_target_coff_flavour:
9981 return "coff-go32";
9384f2ff 9982# else
252b5132
RH		 9983 case bfd_target_coff_flavour:
9984 return "coff-i386";
9384f2ff 9985# endif
4c63da97 9986#endif
3e73aa7c 9987#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 9988 case bfd_target_elf_flavour:
3e73aa7c 9989 {
351f65ca
L		 9990 const char *format;
9991
9992 switch (x86_elf_abi)
4fa24527 9993 {
351f65ca
L		 9994 default:
9995 format = ELF_TARGET_FORMAT;
9996 break;
7f56bc95 9997 case X86_64_ABI:
351f65ca 9998 use_rela_relocations = 1;
4fa24527 9999 object_64bit = 1;
351f65ca
L		 10000 format = ELF_TARGET_FORMAT64;
10001 break;
7f56bc95 10002 case X86_64_X32_ABI:
4fa24527 10003 use_rela_relocations = 1;
351f65ca 10004 object_64bit = 1;
862be3fb 10005 disallow_64bit_reloc = 1;
351f65ca
L		 10006 format = ELF_TARGET_FORMAT32;
10007 break;
4fa24527 10008 }
3632d14b 10009 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10010 {
7f56bc95 10011 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10012 as_fatal (_("Intel L1OM is 64bit only"));
10013 return ELF_TARGET_L1OM_FORMAT;
10014 }
7a9068fe
L		 10015 if (cpu_arch_isa == PROCESSOR_K1OM)
10016 {
10017 if (x86_elf_abi != X86_64_ABI)
10018 as_fatal (_("Intel K1OM is 64bit only"));
10019 return ELF_TARGET_K1OM_FORMAT;
10020 }
8a9036a4 10021 else
351f65ca 10022 return format;
3e73aa7c 10023 }
e57f8c65
TG		 10024#endif
10025#if defined (OBJ_MACH_O)
10026 case bfd_target_mach_o_flavour:
d382c579
TG		 10027 if (flag_code == CODE_64BIT)
10028 {
10029 use_rela_relocations = 1;
10030 object_64bit = 1;
10031 return "mach-o-x86-64";
10032 }
10033 else
10034 return "mach-o-i386";
4c63da97 10035#endif
252b5132
RH		 10036 default:
10037 abort ();
10038 return NULL;
10039 }
10040}
10041
47926f60 10042#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 10043
10044#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 10045void
10046i386_elf_emit_arch_note (void)
a847613f 10047{
718ddfc0 10048 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 10049 {
10050 char *p;
10051 asection *seg = now_seg;
10052 subsegT subseg = now_subseg;
10053 Elf_Internal_Note i_note;
10054 Elf_External_Note e_note;
10055 asection *note_secp;
10056 int len;
10057
10058 /* Create the .note section. */
10059 note_secp = subseg_new (".note", 0);
10060 bfd_set_section_flags (stdoutput,
10061 note_secp,
10062 SEC_HAS_CONTENTS | SEC_READONLY);
10063
10064 /* Process the arch string. */
10065 len = strlen (cpu_arch_name);
10066
10067 i_note.namesz = len + 1;
10068 i_note.descsz = 0;
10069 i_note.type = NT_ARCH;
10070 p = frag_more (sizeof (e_note.namesz));
10071 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
10072 p = frag_more (sizeof (e_note.descsz));
10073 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
10074 p = frag_more (sizeof (e_note.type));
10075 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
10076 p = frag_more (len + 1);
10077 strcpy (p, cpu_arch_name);
10078
10079 frag_align (2, 0, 0);
10080
10081 subseg_set (seg, subseg);
10082 }
10083}
10084#endif
252b5132 10085\f
252b5132 10086symbolS *
7016a5d5 10087md_undefined_symbol (char *name)
252b5132 10088{
18dc2407
ILT		 10089 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10090 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10091 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10092 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10093 {
10094 if (!GOT_symbol)
10095 {
10096 if (symbol_find (name))
10097 as_bad (_("GOT already in symbol table"));
10098 GOT_symbol = symbol_new (name, undefined_section,
10099 (valueT) 0, &zero_address_frag);
10100 };
10101 return GOT_symbol;
10102 }
252b5132
RH		 10103 return 0;
10104}
10105
10106/* Round up a section size to the appropriate boundary. */
47926f60 10107
252b5132 10108valueT
7016a5d5 10109md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10110{
4c63da97
AM		 10111#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10112 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10113 {
10114 /* For a.out, force the section size to be aligned. If we don't do
10115 this, BFD will align it for us, but it will not write out the
10116 final bytes of the section. This may be a bug in BFD, but it is
10117 easier to fix it here since that is how the other a.out targets
10118 work. */
10119 int align;
10120
10121 align = bfd_get_section_alignment (stdoutput, segment);
10122 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
10123 }
252b5132
RH		 10124#endif
10125
10126 return size;
10127}
10128
10129/* On the i386, PC-relative offsets are relative to the start of the
10130 next instruction. That is, the address of the offset, plus its
10131 size, since the offset is always the last part of the insn. */
10132
10133long
e3bb37b5 10134md_pcrel_from (fixS *fixP)
252b5132
RH		 10135{
10136 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10137}
10138
10139#ifndef I386COFF
10140
10141static void
e3bb37b5 10142s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10143{
29b0f896 10144 int temp;
252b5132 10145
8a75718c
JB		 10146#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10147 if (IS_ELF)
10148 obj_elf_section_change_hook ();
10149#endif
252b5132
RH		 10150 temp = get_absolute_expression ();
10151 subseg_set (bss_section, (subsegT) temp);
10152 demand_empty_rest_of_line ();
10153}
10154
10155#endif
10156
252b5132 10157void
e3bb37b5 10158i386_validate_fix (fixS *fixp)
252b5132
RH		 10159{
10160 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
10161 {
23df1078
JH		 10162 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10163 {
4fa24527 10164 if (!object_64bit)
23df1078
JH		 10165 abort ();
10166 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10167 }
10168 else
10169 {
4fa24527 10170 if (!object_64bit)
d6ab8113
JB		 10171 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10172 else
10173 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 10174 }
252b5132
RH		 10175 fixp->fx_subsy = 0;
10176 }
10177}
10178
252b5132 10179arelent *
7016a5d5 10180tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10181{
10182 arelent *rel;
10183 bfd_reloc_code_real_type code;
10184
10185 switch (fixp->fx_r_type)
10186 {
8ce3d284 10187#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10188 case BFD_RELOC_SIZE32:
10189 case BFD_RELOC_SIZE64:
10190 if (S_IS_DEFINED (fixp->fx_addsy)
10191 && !S_IS_EXTERNAL (fixp->fx_addsy))
10192 {
10193 /* Resolve size relocation against local symbol to size of
10194 the symbol plus addend. */
10195 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10196 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10197 && !fits_in_unsigned_long (value))
10198 as_bad_where (fixp->fx_file, fixp->fx_line,
10199 _("symbol size computation overflow"));
10200 fixp->fx_addsy = NULL;
10201 fixp->fx_subsy = NULL;
10202 md_apply_fix (fixp, (valueT *) &value, NULL);
10203 return NULL;
10204 }
8ce3d284 10205#endif
8fd4256d 10206
3e73aa7c 10207 case BFD_RELOC_X86_64_PLT32:
c3320543 10208 case BFD_RELOC_X86_64_PLT32_BND:
3e73aa7c
JH		 10209 case BFD_RELOC_X86_64_GOT32:
10210 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 10211 case BFD_RELOC_386_PLT32:
10212 case BFD_RELOC_386_GOT32:
10213 case BFD_RELOC_386_GOTOFF:
10214 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10215 case BFD_RELOC_386_TLS_GD:
10216 case BFD_RELOC_386_TLS_LDM:
10217 case BFD_RELOC_386_TLS_LDO_32:
10218 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10219 case BFD_RELOC_386_TLS_IE:
10220 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10221 case BFD_RELOC_386_TLS_LE_32:
10222 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10223 case BFD_RELOC_386_TLS_GOTDESC:
10224 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10225 case BFD_RELOC_X86_64_TLSGD:
10226 case BFD_RELOC_X86_64_TLSLD:
10227 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10228 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10229 case BFD_RELOC_X86_64_GOTTPOFF:
10230 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10231 case BFD_RELOC_X86_64_TPOFF64:
10232 case BFD_RELOC_X86_64_GOTOFF64:
10233 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10234 case BFD_RELOC_X86_64_GOT64:
10235 case BFD_RELOC_X86_64_GOTPCREL64:
10236 case BFD_RELOC_X86_64_GOTPC64:
10237 case BFD_RELOC_X86_64_GOTPLT64:
10238 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10239 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10240 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10241 case BFD_RELOC_RVA:
10242 case BFD_RELOC_VTABLE_ENTRY:
10243 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10244#ifdef TE_PE
10245 case BFD_RELOC_32_SECREL:
10246#endif
252b5132
RH		 10247 code = fixp->fx_r_type;
10248 break;
dbbaec26
L		 10249 case BFD_RELOC_X86_64_32S:
10250 if (!fixp->fx_pcrel)
10251 {
10252 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10253 code = fixp->fx_r_type;
10254 break;
10255 }
252b5132 10256 default:
93382f6d 10257 if (fixp->fx_pcrel)
252b5132 10258 {
93382f6d
AM		 10259 switch (fixp->fx_size)
10260 {
10261 default:
b091f402
AM		 10262 as_bad_where (fixp->fx_file, fixp->fx_line,
10263 _("can not do %d byte pc-relative relocation"),
10264 fixp->fx_size);
93382f6d
AM		 10265 code = BFD_RELOC_32_PCREL;
10266 break;
10267 case 1: code = BFD_RELOC_8_PCREL; break;
10268 case 2: code = BFD_RELOC_16_PCREL; break;
c3320543
L		 10269 case 4:
10270 code = (fixp->fx_r_type == BFD_RELOC_X86_64_PC32_BND
10271 ? fixp-> fx_r_type : BFD_RELOC_32_PCREL);
10272 break;
d6ab8113
JB		 10273#ifdef BFD64
10274 case 8: code = BFD_RELOC_64_PCREL; break;
10275#endif
93382f6d
AM		 10276 }
10277 }
10278 else
10279 {
10280 switch (fixp->fx_size)
10281 {
10282 default:
b091f402
AM		 10283 as_bad_where (fixp->fx_file, fixp->fx_line,
10284 _("can not do %d byte relocation"),
10285 fixp->fx_size);
93382f6d
AM		 10286 code = BFD_RELOC_32;
10287 break;
10288 case 1: code = BFD_RELOC_8; break;
10289 case 2: code = BFD_RELOC_16; break;
10290 case 4: code = BFD_RELOC_32; break;
937149dd 10291#ifdef BFD64
3e73aa7c 10292 case 8: code = BFD_RELOC_64; break;
937149dd 10293#endif
93382f6d 10294 }
252b5132
RH		 10295 }
10296 break;
10297 }
252b5132 10298
d182319b
JB		 10299 if ((code == BFD_RELOC_32
10300 || code == BFD_RELOC_32_PCREL
10301 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10302 && GOT_symbol
10303 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10304 {
4fa24527 10305 if (!object_64bit)
d6ab8113
JB		 10306 code = BFD_RELOC_386_GOTPC;
10307 else
10308 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10309 }
7b81dfbb
AJ		 10310 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10311 && GOT_symbol
10312 && fixp->fx_addsy == GOT_symbol)
10313 {
10314 code = BFD_RELOC_X86_64_GOTPC64;
10315 }
252b5132
RH		 10316
10317 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 10318 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10319 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10320
10321 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10322
3e73aa7c
JH		 10323 if (!use_rela_relocations)
10324 {
10325 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10326 vtable entry to be used in the relocation's section offset. */
10327 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10328 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10329#if defined (OBJ_COFF) && defined (TE_PE)
10330 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10331 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10332 else
10333#endif
c6682705 10334 rel->addend = 0;
3e73aa7c
JH		 10335 }
10336 /* Use the rela in 64bit mode. */
252b5132 10337 else
3e73aa7c 10338 {
862be3fb
L		 10339 if (disallow_64bit_reloc)
10340 switch (code)
10341 {
862be3fb
L		 10342 case BFD_RELOC_X86_64_DTPOFF64:
10343 case BFD_RELOC_X86_64_TPOFF64:
10344 case BFD_RELOC_64_PCREL:
10345 case BFD_RELOC_X86_64_GOTOFF64:
10346 case BFD_RELOC_X86_64_GOT64:
10347 case BFD_RELOC_X86_64_GOTPCREL64:
10348 case BFD_RELOC_X86_64_GOTPC64:
10349 case BFD_RELOC_X86_64_GOTPLT64:
10350 case BFD_RELOC_X86_64_PLTOFF64:
10351 as_bad_where (fixp->fx_file, fixp->fx_line,
10352 _("cannot represent relocation type %s in x32 mode"),
10353 bfd_get_reloc_code_name (code));
10354 break;
10355 default:
10356 break;
10357 }
10358
062cd5e7
AS		 10359 if (!fixp->fx_pcrel)
10360 rel->addend = fixp->fx_offset;
10361 else
10362 switch (code)
10363 {
10364 case BFD_RELOC_X86_64_PLT32:
c3320543 10365 case BFD_RELOC_X86_64_PLT32_BND:
062cd5e7
AS		 10366 case BFD_RELOC_X86_64_GOT32:
10367 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 10368 case BFD_RELOC_X86_64_TLSGD:
10369 case BFD_RELOC_X86_64_TLSLD:
10370 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10371 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10372 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10373 rel->addend = fixp->fx_offset - fixp->fx_size;
10374 break;
10375 default:
10376 rel->addend = (section->vma
10377 - fixp->fx_size
10378 + fixp->fx_addnumber
10379 + md_pcrel_from (fixp));
10380 break;
10381 }
3e73aa7c
JH		 10382 }
10383
252b5132
RH		 10384 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10385 if (rel->howto == NULL)
10386 {
10387 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10388 _("cannot represent relocation type %s"),
252b5132
RH		 10389 bfd_get_reloc_code_name (code));
10390 /* Set howto to a garbage value so that we can keep going. */
10391 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10392 gas_assert (rel->howto != NULL);
252b5132
RH		 10393 }
10394
10395 return rel;
10396}
10397
ee86248c 10398#include "tc-i386-intel.c"
54cfded0 10399
a60de03c
JB		 10400void
10401tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10402{
a60de03c
JB		 10403 int saved_naked_reg;
10404 char saved_register_dot;
54cfded0 10405
a60de03c
JB		 10406 saved_naked_reg = allow_naked_reg;
10407 allow_naked_reg = 1;
10408 saved_register_dot = register_chars['.'];
10409 register_chars['.'] = '.';
10410 allow_pseudo_reg = 1;
10411 expression_and_evaluate (exp);
10412 allow_pseudo_reg = 0;
10413 register_chars['.'] = saved_register_dot;
10414 allow_naked_reg = saved_naked_reg;
10415
e96d56a1 10416 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10417 {
a60de03c
JB		 10418 if ((addressT) exp->X_add_number < i386_regtab_size)
10419 {
10420 exp->X_op = O_constant;
10421 exp->X_add_number = i386_regtab[exp->X_add_number]
10422 .dw2_regnum[flag_code >> 1];
10423 }
10424 else
10425 exp->X_op = O_illegal;
54cfded0 10426 }
54cfded0
AM		 10427}
10428
10429void
10430tc_x86_frame_initial_instructions (void)
10431{
a60de03c
JB		 10432 static unsigned int sp_regno[2];
10433
10434 if (!sp_regno[flag_code >> 1])
10435 {
10436 char *saved_input = input_line_pointer;
10437 char sp[][4] = {"esp", "rsp"};
10438 expressionS exp;
a4447b93 10439
a60de03c
JB		 10440 input_line_pointer = sp[flag_code >> 1];
10441 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10442 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10443 sp_regno[flag_code >> 1] = exp.X_add_number;
10444 input_line_pointer = saved_input;
10445 }
a4447b93 10446
61ff971f
L		 10447 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10448 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10449}
d2b2c203 10450
d7921315
L		 10451int
10452x86_dwarf2_addr_size (void)
10453{
10454#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10455 if (x86_elf_abi == X86_64_X32_ABI)
10456 return 4;
10457#endif
10458 return bfd_arch_bits_per_address (stdoutput) / 8;
10459}
10460
d2b2c203
DJ		 10461int
10462i386_elf_section_type (const char *str, size_t len)
10463{
10464 if (flag_code == CODE_64BIT
10465 && len == sizeof ("unwind") - 1
10466 && strncmp (str, "unwind", 6) == 0)
10467 return SHT_X86_64_UNWIND;
10468
10469 return -1;
10470}
bb41ade5 10471
ad5fec3b
EB		 10472#ifdef TE_SOLARIS
10473void
10474i386_solaris_fix_up_eh_frame (segT sec)
10475{
10476 if (flag_code == CODE_64BIT)
10477 elf_section_type (sec) = SHT_X86_64_UNWIND;
10478}
10479#endif
10480
bb41ade5
AM		 10481#ifdef TE_PE
10482void
10483tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10484{
91d6fa6a 10485 expressionS exp;
bb41ade5 10486
91d6fa6a
NC		 10487 exp.X_op = O_secrel;
10488 exp.X_add_symbol = symbol;
10489 exp.X_add_number = 0;
10490 emit_expr (&exp, size);
bb41ade5
AM		 10491}
10492#endif
3b22753a
L		 10493
10494#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10495/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10496
01e1a5bc 10497bfd_vma
3b22753a
L		 10498x86_64_section_letter (int letter, char **ptr_msg)
10499{
10500 if (flag_code == CODE_64BIT)
10501 {
10502 if (letter == 'l')
10503 return SHF_X86_64_LARGE;
10504
8f3bae45 10505 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10506 }
3b22753a 10507 else
8f3bae45 10508 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10509 return -1;
10510}
10511
01e1a5bc 10512bfd_vma
3b22753a
L		 10513x86_64_section_word (char *str, size_t len)
10514{
8620418b 10515 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10516 return SHF_X86_64_LARGE;
10517
10518 return -1;
10519}
10520
10521static void
10522handle_large_common (int small ATTRIBUTE_UNUSED)
10523{
10524 if (flag_code != CODE_64BIT)
10525 {
10526 s_comm_internal (0, elf_common_parse);
10527 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10528 }
10529 else
10530 {
10531 static segT lbss_section;
10532 asection *saved_com_section_ptr = elf_com_section_ptr;
10533 asection *saved_bss_section = bss_section;
10534
10535 if (lbss_section == NULL)
10536 {
10537 flagword applicable;
10538 segT seg = now_seg;
10539 subsegT subseg = now_subseg;
10540
10541 /* The .lbss section is for local .largecomm symbols. */
10542 lbss_section = subseg_new (".lbss", 0);
10543 applicable = bfd_applicable_section_flags (stdoutput);
10544 bfd_set_section_flags (stdoutput, lbss_section,
10545 applicable & SEC_ALLOC);
10546 seg_info (lbss_section)->bss = 1;
10547
10548 subseg_set (seg, subseg);
10549 }
10550
10551 elf_com_section_ptr = &_bfd_elf_large_com_section;
10552 bss_section = lbss_section;
10553
10554 s_comm_internal (0, elf_common_parse);
10555
10556 elf_com_section_ptr = saved_com_section_ptr;
10557 bss_section = saved_bss_section;
10558 }
10559}
10560#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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