projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Add AVX512VBMI instructions
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
4b95cf5c 2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d
L		 68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
22109423 136 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 137}
138arch_entry;
139
78f12dd3 140static void update_code_flag (int, int);
e3bb37b5
L		 141static void set_code_flag (int);
142static void set_16bit_gcc_code_flag (int);
143static void set_intel_syntax (int);
1efbbeb4 144static void set_intel_mnemonic (int);
db51cc60 145static void set_allow_index_reg (int);
7bab8ab5 146static void set_check (int);
e3bb37b5 147static void set_cpu_arch (int);
6482c264 148#ifdef TE_PE
e3bb37b5 149static void pe_directive_secrel (int);
6482c264 150#endif
e3bb37b5
L		 151static void signed_cons (int);
152static char *output_invalid (int c);
ee86248c
JB		 153static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
154 const char *);
155static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
156 const char *);
a7619375 157static int i386_att_operand (char *);
e3bb37b5 158static int i386_intel_operand (char *, int);
ee86248c
JB		 159static int i386_intel_simplify (expressionS *);
160static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 161static const reg_entry *parse_register (char *, char **);
162static char *parse_insn (char *, char *);
163static char *parse_operands (char *, const char *);
164static void swap_operands (void);
4d456e3d 165static void swap_2_operands (int, int);
e3bb37b5
L		 166static void optimize_imm (void);
167static void optimize_disp (void);
d3ce72d0 168static const insn_template *match_template (void);
e3bb37b5
L		 169static int check_string (void);
170static int process_suffix (void);
171static int check_byte_reg (void);
172static int check_long_reg (void);
173static int check_qword_reg (void);
174static int check_word_reg (void);
175static int finalize_imm (void);
176static int process_operands (void);
177static const seg_entry *build_modrm_byte (void);
178static void output_insn (void);
179static void output_imm (fragS *, offsetT);
180static void output_disp (fragS *, offsetT);
29b0f896 181#ifndef I386COFF
e3bb37b5 182static void s_bss (int);
252b5132 183#endif
17d4e2a2
L		 184#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185static void handle_large_common (int small ATTRIBUTE_UNUSED);
186#endif
252b5132 187
a847613f 188static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 189
43234a1e
L		 190/* This struct describes rounding control and SAE in the instruction. */
191struct RC_Operation
192{
193 enum rc_type
194 {
195 rne = 0,
196 rd,
197 ru,
198 rz,
199 saeonly
200 } type;
201 int operand;
202};
203
204static struct RC_Operation rc_op;
205
206/* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209struct Mask_Operation
210{
211 const reg_entry *mask;
212 unsigned int zeroing;
213 /* The operand where this operation is associated. */
214 int operand;
215};
216
217static struct Mask_Operation mask_op;
218
219/* The struct describes broadcasting, applied to OPERAND. FACTOR is
220 broadcast factor. */
221struct Broadcast_Operation
222{
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
224 int type;
225
226 /* Index of broadcasted operand. */
227 int operand;
228};
229
230static struct Broadcast_Operation broadcast_op;
231
c0f3af97
L		 232/* VEX prefix. */
233typedef struct
234{
43234a1e
L		 235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes[4];
c0f3af97
L		 237 unsigned int length;
238 /* Destination or source register specifier. */
239 const reg_entry *register_specifier;
240} vex_prefix;
241
252b5132 242/* 'md_assemble ()' gathers together information and puts it into a
47926f60 243 i386_insn. */
252b5132 244
520dc8e8
AM		 245union i386_op
246 {
247 expressionS *disps;
248 expressionS *imms;
249 const reg_entry *regs;
250 };
251
a65babc9
L		 252enum i386_error
253 {
86e026a4 254 operand_size_mismatch,
a65babc9
L		 255 operand_type_mismatch,
256 register_type_mismatch,
257 number_of_operands_mismatch,
258 invalid_instruction_suffix,
259 bad_imm4,
260 old_gcc_only,
261 unsupported_with_intel_mnemonic,
262 unsupported_syntax,
6c30d220
L		 263 unsupported,
264 invalid_vsib_address,
7bab8ab5 265 invalid_vector_register_set,
43234a1e
L		 266 unsupported_vector_index_register,
267 unsupported_broadcast,
268 broadcast_not_on_src_operand,
269 broadcast_needed,
270 unsupported_masking,
271 mask_not_on_destination,
272 no_default_mask,
273 unsupported_rc_sae,
274 rc_sae_operand_not_last_imm,
275 invalid_register_operand,
276 try_vector_disp8
a65babc9
L		 277 };
278
252b5132
RH		 279struct _i386_insn
280 {
47926f60 281 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 282 insn_template tm;
252b5132 283
7d5e4556
L		 284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
252b5132
RH		 286 char suffix;
287
47926f60 288 /* OPERANDS gives the number of given operands. */
252b5132
RH		 289 unsigned int operands;
290
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
47926f60 293 operands. */
252b5132
RH		 294 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
295
296 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 297 use OP[i] for the corresponding operand. */
40fb9820 298 i386_operand_type types[MAX_OPERANDS];
252b5132 299
520dc8e8
AM		 300 /* Displacement expression, immediate expression, or register for each
301 operand. */
302 union i386_op op[MAX_OPERANDS];
252b5132 303
3e73aa7c
JH		 304 /* Flags for operands. */
305 unsigned int flags[MAX_OPERANDS];
306#define Operand_PCrel 1
307
252b5132 308 /* Relocation type for operand */
f86103b7 309 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 310
252b5132
RH		 311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry *base_reg;
314 const reg_entry *index_reg;
315 unsigned int log2_scale_factor;
316
317 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 318 explicit segment overrides are given. */
ce8a8b2f 319 const seg_entry *seg[2];
252b5132
RH		 320
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes;
324 unsigned char prefix[MAX_PREFIXES];
325
326 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 327 addressing modes of this insn are encoded. */
252b5132 328 modrm_byte rm;
3e73aa7c 329 rex_byte rex;
43234a1e 330 rex_byte vrex;
252b5132 331 sib_byte sib;
c0f3af97 332 vex_prefix vex;
b6169b20 333
43234a1e
L		 334 /* Masking attributes. */
335 struct Mask_Operation *mask;
336
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation *rounding;
339
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation *broadcast;
342
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift;
345
b6169b20 346 /* Swap operand in encoding. */
4473e004 347 unsigned int swap_operand;
891edac4 348
a501d77e
L		 349 /* Prefer 8bit or 32bit displacement in encoding. */
350 enum
351 {
352 disp_encoding_default = 0,
353 disp_encoding_8bit,
354 disp_encoding_32bit
355 } disp_encoding;
f8a5c266 356
d5de92cf
L		 357 /* REP prefix. */
358 const char *rep_prefix;
359
165de32a
L		 360 /* HLE prefix. */
361 const char *hle_prefix;
42164a71 362
7e8b059b
L		 363 /* Have BND prefix. */
364 const char *bnd_prefix;
365
43234a1e
L		 366 /* Need VREX to support upper 16 registers. */
367 int need_vrex;
368
891edac4 369 /* Error message. */
a65babc9 370 enum i386_error error;
252b5132
RH		 371 };
372
373typedef struct _i386_insn i386_insn;
374
43234a1e
L		 375/* Link RC type with corresponding string, that'll be looked for in
376 asm. */
377struct RC_name
378{
379 enum rc_type type;
380 const char *name;
381 unsigned int len;
382};
383
384static const struct RC_name RC_NamesTable[] =
385{
386 { rne, STRING_COMMA_LEN ("rn-sae") },
387 { rd, STRING_COMMA_LEN ("rd-sae") },
388 { ru, STRING_COMMA_LEN ("ru-sae") },
389 { rz, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly, STRING_COMMA_LEN ("sae") },
391};
392
252b5132
RH		 393/* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 395const char extra_symbol_chars[] = "*%-([{"
252b5132 396#ifdef LEX_AT
32137342
NC		 397 "@"
398#endif
399#ifdef LEX_QM
400 "?"
252b5132 401#endif
32137342 402 ;
252b5132 403
29b0f896
AM		 404#if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 406 && !defined (TE_GNU) \
29b0f896 407 && !defined (TE_LINUX) \
8d63c93e
RM		 408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
29b0f896 410 && !defined (TE_FreeBSD) \
5b806d27 411 && !defined (TE_DragonFly) \
29b0f896 412 && !defined (TE_NetBSD)))
252b5132 413/* This array holds the chars that always start a comment. If the
b3b91714
AM		 414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416const char *i386_comment_chars = "#/";
417#define SVR4_COMMENT_CHARS 1
252b5132 418#define PREFIX_SEPARATOR '\\'
252b5132 419
b3b91714
AM		 420#else
421const char *i386_comment_chars = "#";
422#define PREFIX_SEPARATOR '/'
423#endif
424
252b5132
RH		 425/* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 429 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
252b5132 432 '/' isn't otherwise defined. */
b3b91714 433const char line_comment_chars[] = "#/";
252b5132 434
63a0b638 435const char line_separator_chars[] = ";";
252b5132 436
ce8a8b2f
AM		 437/* Chars that can be used to separate mant from exp in floating point
438 nums. */
252b5132
RH		 439const char EXP_CHARS[] = "eE";
440
ce8a8b2f
AM		 441/* Chars that mean this number is a floating point constant
442 As in 0f12.456
443 or 0d1.2345e12. */
252b5132
RH		 444const char FLT_CHARS[] = "fFdDxX";
445
ce8a8b2f 446/* Tables for lexical analysis. */
252b5132
RH		 447static char mnemonic_chars[256];
448static char register_chars[256];
449static char operand_chars[256];
450static char identifier_chars[256];
451static char digit_chars[256];
452
ce8a8b2f 453/* Lexical macros. */
252b5132
RH		 454#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455#define is_operand_char(x) (operand_chars[(unsigned char) x])
456#define is_register_char(x) (register_chars[(unsigned char) x])
457#define is_space_char(x) ((x) == ' ')
458#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459#define is_digit_char(x) (digit_chars[(unsigned char) x])
460
0234cb7c 461/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 462static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
463
464/* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
47926f60 467 assembler instruction). */
252b5132 468static char save_stack[32];
ce8a8b2f 469static char *save_stack_p;
252b5132
RH		 470#define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472#define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
474
47926f60 475/* The instruction we're assembling. */
252b5132
RH		 476static i386_insn i;
477
478/* Possible templates for current insn. */
479static const templates *current_templates;
480
31b2323c
L		 481/* Per instruction expressionS buffers: max displacements & immediates. */
482static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
483static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 484
47926f60 485/* Current operand we are working on. */
ee86248c 486static int this_operand = -1;
252b5132 487
3e73aa7c
JH		 488/* We support four different modes. FLAG_CODE variable is used to distinguish
489 these. */
490
491enum flag_code {
492 CODE_32BIT,
493 CODE_16BIT,
494 CODE_64BIT };
495
496static enum flag_code flag_code;
4fa24527 497static unsigned int object_64bit;
862be3fb 498static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 499static int use_rela_relocations = 0;
500
7af8ed2d
NC		 501#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
504
351f65ca
L		 505/* The ELF ABI to use. */
506enum x86_elf_abi
507{
508 I386_ABI,
7f56bc95
L		 509 X86_64_ABI,
510 X86_64_X32_ABI
351f65ca
L		 511};
512
513static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 514#endif
351f65ca 515
167ad85b
TG		 516#if defined (TE_PE) || defined (TE_PEP)
517/* Use big object file format. */
518static int use_big_obj = 0;
519#endif
520
47926f60
KH		 521/* 1 for intel syntax,
522 0 if att syntax. */
523static int intel_syntax = 0;
252b5132 524
1efbbeb4
L		 525/* 1 for intel mnemonic,
526 0 if att mnemonic. */
527static int intel_mnemonic = !SYSV386_COMPAT;
528
5209009a 529/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 530static int old_gcc = OLDGCC_COMPAT;
531
a60de03c
JB		 532/* 1 if pseudo registers are permitted. */
533static int allow_pseudo_reg = 0;
534
47926f60
KH		 535/* 1 if register prefix % not required. */
536static int allow_naked_reg = 0;
252b5132 537
7e8b059b
L		 538/* 1 if the assembler should add BND prefix for all control-tranferring
539 instructions supporting it, even if this prefix wasn't specified
540 explicitly. */
541static int add_bnd_prefix = 0;
542
ba104c83 543/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 544static int allow_index_reg = 0;
545
d022bddd
IT		 546/* 1 if the assembler should ignore LOCK prefix, even if it was
547 specified explicitly. */
548static int omit_lock_prefix = 0;
549
7bab8ab5 550static enum check_kind
daf50ae7 551 {
7bab8ab5
JB		 552 check_none = 0,
553 check_warning,
554 check_error
daf50ae7 555 }
7bab8ab5 556sse_check, operand_check = check_warning;
daf50ae7 557
2ca3ace5
L		 558/* Register prefix used for error message. */
559static const char *register_prefix = "%";
560
47926f60
KH		 561/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
562 leave, push, and pop instructions so that gcc has the same stack
563 frame as in 32 bit mode. */
564static char stackop_size = '\0';
eecb386c 565
12b55ccc
L		 566/* Non-zero to optimize code alignment. */
567int optimize_align_code = 1;
568
47926f60
KH		 569/* Non-zero to quieten some warnings. */
570static int quiet_warnings = 0;
a38cf1db 571
47926f60
KH		 572/* CPU name. */
573static const char *cpu_arch_name = NULL;
6305a203 574static char *cpu_sub_arch_name = NULL;
a38cf1db 575
47926f60 576/* CPU feature flags. */
40fb9820
L		 577static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
578
ccc9c027
L		 579/* If we have selected a cpu we are generating instructions for. */
580static int cpu_arch_tune_set = 0;
581
9103f4f4 582/* Cpu we are generating instructions for. */
fbf3f584 583enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 584
585/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 586static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 587
ccc9c027 588/* CPU instruction set architecture used. */
fbf3f584 589enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 590
9103f4f4 591/* CPU feature flags of instruction set architecture used. */
fbf3f584 592i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 593
fddf5b5b
AM		 594/* If set, conditional jumps are not automatically promoted to handle
595 larger than a byte offset. */
596static unsigned int no_cond_jump_promotion = 0;
597
c0f3af97
L		 598/* Encode SSE instructions with VEX prefix. */
599static unsigned int sse2avx;
600
539f890d
L		 601/* Encode scalar AVX instructions with specific vector length. */
602static enum
603 {
604 vex128 = 0,
605 vex256
606 } avxscalar;
607
43234a1e
L		 608/* Encode scalar EVEX LIG instructions with specific vector length. */
609static enum
610 {
611 evexl128 = 0,
612 evexl256,
613 evexl512
614 } evexlig;
615
616/* Encode EVEX WIG instructions with specific evex.w. */
617static enum
618 {
619 evexw0 = 0,
620 evexw1
621 } evexwig;
622
d3d3c6db
IT		 623/* Value to encode in EVEX RC bits, for SAE-only instructions. */
624static enum rc_type evexrcig = rne;
625
29b0f896 626/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 627static symbolS *GOT_symbol;
29b0f896 628
a4447b93
RH		 629/* The dwarf2 return column, adjusted for 32 or 64 bit. */
630unsigned int x86_dwarf2_return_column;
631
632/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
633int x86_cie_data_alignment;
634
252b5132 635/* Interface to relax_segment.
fddf5b5b
AM		 636 There are 3 major relax states for 386 jump insns because the
637 different types of jumps add different sizes to frags when we're
638 figuring out what sort of jump to choose to reach a given label. */
252b5132 639
47926f60 640/* Types. */
93c2a809
AM		 641#define UNCOND_JUMP 0
642#define COND_JUMP 1
643#define COND_JUMP86 2
fddf5b5b 644
47926f60 645/* Sizes. */
252b5132
RH		 646#define CODE16 1
647#define SMALL 0
29b0f896 648#define SMALL16 (SMALL | CODE16)
252b5132 649#define BIG 2
29b0f896 650#define BIG16 (BIG | CODE16)
252b5132
RH		 651
652#ifndef INLINE
653#ifdef __GNUC__
654#define INLINE __inline__
655#else
656#define INLINE
657#endif
658#endif
659
fddf5b5b
AM		 660#define ENCODE_RELAX_STATE(type, size) \
661 ((relax_substateT) (((type) << 2) | (size)))
662#define TYPE_FROM_RELAX_STATE(s) \
663 ((s) >> 2)
664#define DISP_SIZE_FROM_RELAX_STATE(s) \
665 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 666
667/* This table is used by relax_frag to promote short jumps to long
668 ones where necessary. SMALL (short) jumps may be promoted to BIG
669 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
670 don't allow a short jump in a 32 bit code segment to be promoted to
671 a 16 bit offset jump because it's slower (requires data size
672 prefix), and doesn't work, unless the destination is in the bottom
673 64k of the code segment (The top 16 bits of eip are zeroed). */
674
675const relax_typeS md_relax_table[] =
676{
24eab124
AM		 677 /* The fields are:
678 1) most positive reach of this state,
679 2) most negative reach of this state,
93c2a809 680 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 681 4) which index into the table to try if we can't fit into this one. */
252b5132 682
fddf5b5b 683 /* UNCOND_JUMP states. */
93c2a809
AM		 684 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
685 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
686 /* dword jmp adds 4 bytes to frag:
687 0 extra opcode bytes, 4 displacement bytes. */
252b5132 688 {0, 0, 4, 0},
93c2a809
AM		 689 /* word jmp adds 2 byte2 to frag:
690 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 691 {0, 0, 2, 0},
692
93c2a809
AM		 693 /* COND_JUMP states. */
694 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
695 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
696 /* dword conditionals adds 5 bytes to frag:
697 1 extra opcode byte, 4 displacement bytes. */
698 {0, 0, 5, 0},
fddf5b5b 699 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 700 1 extra opcode byte, 2 displacement bytes. */
701 {0, 0, 3, 0},
702
703 /* COND_JUMP86 states. */
704 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
705 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
706 /* dword conditionals adds 5 bytes to frag:
707 1 extra opcode byte, 4 displacement bytes. */
708 {0, 0, 5, 0},
709 /* word conditionals add 4 bytes to frag:
710 1 displacement byte and a 3 byte long branch insn. */
711 {0, 0, 4, 0}
252b5132
RH		 712};
713
9103f4f4
L		 714static const arch_entry cpu_arch[] =
715{
89507696
JB		 716 /* Do not replace the first two entries - i386_target_format()
717 relies on them being there in this order. */
8a2c8fef 718 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 719 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 720 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 721 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 722 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 723 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 724 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 725 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 726 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 727 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 728 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 729 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 730 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 731 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 732 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 733 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 734 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 735 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 736 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 737 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 738 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 739 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 740 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 741 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 742 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 743 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 744 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 745 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 746 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 747 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 748 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 749 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 750 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 751 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 752 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 753 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 754 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 755 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 756 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 757 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 758 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 759 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 760 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 761 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 762 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
763 CPU_K1OM_FLAGS, 0, 0 },
8a2c8fef 764 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 765 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 766 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 767 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 768 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 769 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 770 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 771 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 772 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 773 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 774 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 775 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 776 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 777 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 778 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 779 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 780 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 781 CPU_BDVER2_FLAGS, 0, 0 },
5e5c50d3
NE		 782 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
783 CPU_BDVER3_FLAGS, 0, 0 },
c7b0bd56
SE		 784 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
785 CPU_BDVER4_FLAGS, 0, 0 },
7b458c12
L		 786 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
787 CPU_BTVER1_FLAGS, 0, 0 },
788 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
789 CPU_BTVER2_FLAGS, 0, 0 },
8a2c8fef 790 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 791 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 792 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 793 CPU_287_FLAGS, 0, 0 },
8a2c8fef 794 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 795 CPU_387_FLAGS, 0, 0 },
8a2c8fef 796 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 797 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 798 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 799 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 800 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 801 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 802 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 803 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 804 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 805 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 806 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 807 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 808 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 809 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 810 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 811 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 812 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 813 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 814 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 815 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 816 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 817 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 818 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 819 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 820 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
821 CPU_AVX2_FLAGS, 0, 0 },
43234a1e
L		 822 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
823 CPU_AVX512F_FLAGS, 0, 0 },
824 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
825 CPU_AVX512CD_FLAGS, 0, 0 },
826 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
827 CPU_AVX512ER_FLAGS, 0, 0 },
828 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
829 CPU_AVX512PF_FLAGS, 0, 0 },
1dfc6506
L		 830 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
831 CPU_AVX512DQ_FLAGS, 0, 0 },
832 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
833 CPU_AVX512BW_FLAGS, 0, 0 },
834 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
835 CPU_AVX512VL_FLAGS, 0, 0 },
8a2c8fef 836 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 837 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 838 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 839 CPU_VMX_FLAGS, 0, 0 },
8729a6f6
L		 840 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
841 CPU_VMFUNC_FLAGS, 0, 0 },
8a2c8fef 842 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 843 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 844 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 845 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 846 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 847 CPU_XSAVEOPT_FLAGS, 0, 0 },
1dfc6506
L		 848 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
849 CPU_XSAVEC_FLAGS, 0, 0 },
850 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
851 CPU_XSAVES_FLAGS, 0, 0 },
8a2c8fef 852 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 853 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 854 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 855 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 856 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 857 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 858 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 859 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 860 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 861 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 862 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 863 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 864 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
865 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 866 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 867 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 868 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 869 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 870 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 871 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 872 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 873 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 874 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 875 CPU_MOVBE_FLAGS, 0, 0 },
60aa667e
L		 876 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
877 CPU_CX16_FLAGS, 0, 0 },
8a2c8fef 878 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 879 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 880 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
881 CPU_LZCNT_FLAGS, 0, 0 },
42164a71
L		 882 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
883 CPU_HLE_FLAGS, 0, 0 },
884 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
885 CPU_RTM_FLAGS, 0, 0 },
6c30d220
L		 886 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
887 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 888 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 889 CPU_CLFLUSH_FLAGS, 0, 0 },
890 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
891 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 892 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 893 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 894 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 895 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 896 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 897 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 898 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 899 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 900 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 901 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 902 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 903 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 904 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 905 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 906 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 907 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 908 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 909 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 910 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
911 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 912 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
913 CPU_TBM_FLAGS, 0, 0 },
e2e1fcde
L		 914 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
915 CPU_ADX_FLAGS, 0, 0 },
916 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
917 CPU_RDSEED_FLAGS, 0, 0 },
918 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
919 CPU_PRFCHW_FLAGS, 0, 0 },
5c111e37
L		 920 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
921 CPU_SMAP_FLAGS, 0, 0 },
7e8b059b
L		 922 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
923 CPU_MPX_FLAGS, 0, 0 },
a0046408
L		 924 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
925 CPU_SHA_FLAGS, 0, 0 },
963f3586
IT		 926 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
927 CPU_CLFLUSHOPT_FLAGS, 0, 0 },
dcf893b5
IT		 928 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
929 CPU_PREFETCHWT1_FLAGS, 0, 0 },
2cf200a4
IT		 930 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
931 CPU_SE1_FLAGS, 0, 0 },
c5e7287a
IT		 932 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
933 CPU_CLWB_FLAGS, 0, 0 },
9d8596f0
IT		 934 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN,
935 CPU_PCOMMIT_FLAGS, 0, 0 },
2cc1b5aa
IT		 936 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
937 CPU_AVX512IFMA_FLAGS, 0, 0 },
14f195c9
IT		 938 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
939 CPU_AVX512VBMI_FLAGS, 0, 0 },
e413e4e9
AM		 940};
941
704209c0 942#ifdef I386COFF
a6c24e68
NC		 943/* Like s_lcomm_internal in gas/read.c but the alignment string
944 is allowed to be optional. */
945
946static symbolS *
947pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
948{
949 addressT align = 0;
950
951 SKIP_WHITESPACE ();
952
7ab9ffdd 953 if (needs_align
a6c24e68
NC		 954 && *input_line_pointer == ',')
955 {
956 align = parse_align (needs_align - 1);
7ab9ffdd 957
a6c24e68
NC		 958 if (align == (addressT) -1)
959 return NULL;
960 }
961 else
962 {
963 if (size >= 8)
964 align = 3;
965 else if (size >= 4)
966 align = 2;
967 else if (size >= 2)
968 align = 1;
969 else
970 align = 0;
971 }
972
973 bss_alloc (symbolP, size, align);
974 return symbolP;
975}
976
704209c0 977static void
a6c24e68
NC		 978pe_lcomm (int needs_align)
979{
980 s_comm_internal (needs_align * 2, pe_lcomm_internal);
981}
704209c0 982#endif
a6c24e68 983
29b0f896
AM		 984const pseudo_typeS md_pseudo_table[] =
985{
986#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
987 {"align", s_align_bytes, 0},
988#else
989 {"align", s_align_ptwo, 0},
990#endif
991 {"arch", set_cpu_arch, 0},
992#ifndef I386COFF
993 {"bss", s_bss, 0},
a6c24e68
NC		 994#else
995 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 996#endif
997 {"ffloat", float_cons, 'f'},
998 {"dfloat", float_cons, 'd'},
999 {"tfloat", float_cons, 'x'},
1000 {"value", cons, 2},
d182319b 1001 {"slong", signed_cons, 4},
29b0f896
AM		 1002 {"noopt", s_ignore, 0},
1003 {"optim", s_ignore, 0},
1004 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1005 {"code16", set_code_flag, CODE_16BIT},
1006 {"code32", set_code_flag, CODE_32BIT},
1007 {"code64", set_code_flag, CODE_64BIT},
1008 {"intel_syntax", set_intel_syntax, 1},
1009 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1010 {"intel_mnemonic", set_intel_mnemonic, 1},
1011 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1012 {"allow_index_reg", set_allow_index_reg, 1},
1013 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1014 {"sse_check", set_check, 0},
1015 {"operand_check", set_check, 1},
3b22753a
L		 1016#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1017 {"largecomm", handle_large_common, 0},
07a53e5c 1018#else
e3bb37b5 1019 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1020 {"loc", dwarf2_directive_loc, 0},
1021 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1022#endif
6482c264
NC		 1023#ifdef TE_PE
1024 {"secrel32", pe_directive_secrel, 0},
1025#endif
29b0f896
AM		 1026 {0, 0, 0}
1027};
1028
1029/* For interface with expression (). */
1030extern char *input_line_pointer;
1031
1032/* Hash table for instruction mnemonic lookup. */
1033static struct hash_control *op_hash;
1034
1035/* Hash table for register lookup. */
1036static struct hash_control *reg_hash;
1037\f
252b5132 1038void
e3bb37b5 1039i386_align_code (fragS *fragP, int count)
252b5132 1040{
ce8a8b2f
AM		 1041 /* Various efficient no-op patterns for aligning code labels.
1042 Note: Don't try to assemble the instructions in the comments.
1043 0L and 0w are not legal. */
252b5132
RH		 1044 static const char f32_1[] =
1045 {0x90}; /* nop */
1046 static const char f32_2[] =
ccc9c027 1047 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 1048 static const char f32_3[] =
1049 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1050 static const char f32_4[] =
1051 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1052 static const char f32_5[] =
1053 {0x90, /* nop */
1054 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1055 static const char f32_6[] =
1056 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1057 static const char f32_7[] =
1058 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1059 static const char f32_8[] =
1060 {0x90, /* nop */
1061 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1062 static const char f32_9[] =
1063 {0x89,0xf6, /* movl %esi,%esi */
1064 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1065 static const char f32_10[] =
1066 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1067 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1068 static const char f32_11[] =
1069 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1070 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1071 static const char f32_12[] =
1072 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1073 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1074 static const char f32_13[] =
1075 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1076 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1077 static const char f32_14[] =
1078 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1079 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 1080 static const char f16_3[] =
1081 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 1082 static const char f16_4[] =
1083 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1084 static const char f16_5[] =
1085 {0x90, /* nop */
1086 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1087 static const char f16_6[] =
1088 {0x89,0xf6, /* mov %si,%si */
1089 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1090 static const char f16_7[] =
1091 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1092 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1093 static const char f16_8[] =
1094 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1095 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 1096 static const char jump_31[] =
1097 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1098 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1099 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1100 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 1101 static const char *const f32_patt[] = {
1102 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1103 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 1104 };
1105 static const char *const f16_patt[] = {
76bc74dc 1106 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1107 };
ccc9c027
L		 1108 /* nopl (%[re]ax) */
1109 static const char alt_3[] =
1110 {0x0f,0x1f,0x00};
1111 /* nopl 0(%[re]ax) */
1112 static const char alt_4[] =
1113 {0x0f,0x1f,0x40,0x00};
1114 /* nopl 0(%[re]ax,%[re]ax,1) */
1115 static const char alt_5[] =
1116 {0x0f,0x1f,0x44,0x00,0x00};
1117 /* nopw 0(%[re]ax,%[re]ax,1) */
1118 static const char alt_6[] =
1119 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1120 /* nopl 0L(%[re]ax) */
1121 static const char alt_7[] =
1122 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1123 /* nopl 0L(%[re]ax,%[re]ax,1) */
1124 static const char alt_8[] =
1125 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1126 /* nopw 0L(%[re]ax,%[re]ax,1) */
1127 static const char alt_9[] =
1128 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1129 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1130 static const char alt_10[] =
1131 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1132 /* data16
1133 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1134 static const char alt_long_11[] =
1135 {0x66,
1136 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1137 /* data16
1138 data16
1139 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1140 static const char alt_long_12[] =
1141 {0x66,
1142 0x66,
1143 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1144 /* data16
1145 data16
1146 data16
1147 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1148 static const char alt_long_13[] =
1149 {0x66,
1150 0x66,
1151 0x66,
1152 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1153 /* data16
1154 data16
1155 data16
1156 data16
1157 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1158 static const char alt_long_14[] =
1159 {0x66,
1160 0x66,
1161 0x66,
1162 0x66,
1163 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1164 /* data16
1165 data16
1166 data16
1167 data16
1168 data16
1169 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1170 static const char alt_long_15[] =
1171 {0x66,
1172 0x66,
1173 0x66,
1174 0x66,
1175 0x66,
1176 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1177 /* nopl 0(%[re]ax,%[re]ax,1)
1178 nopw 0(%[re]ax,%[re]ax,1) */
1179 static const char alt_short_11[] =
1180 {0x0f,0x1f,0x44,0x00,0x00,
1181 0x66,0x0f,0x1f,0x44,0x00,0x00};
1182 /* nopw 0(%[re]ax,%[re]ax,1)
1183 nopw 0(%[re]ax,%[re]ax,1) */
1184 static const char alt_short_12[] =
1185 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1186 0x66,0x0f,0x1f,0x44,0x00,0x00};
1187 /* nopw 0(%[re]ax,%[re]ax,1)
1188 nopl 0L(%[re]ax) */
1189 static const char alt_short_13[] =
1190 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1191 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1192 /* nopl 0L(%[re]ax)
1193 nopl 0L(%[re]ax) */
1194 static const char alt_short_14[] =
1195 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1196 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1197 /* nopl 0L(%[re]ax)
1198 nopl 0L(%[re]ax,%[re]ax,1) */
1199 static const char alt_short_15[] =
1200 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1201 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1202 static const char *const alt_short_patt[] = {
1203 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1204 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
1205 alt_short_14, alt_short_15
1206 };
1207 static const char *const alt_long_patt[] = {
1208 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1209 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1210 alt_long_14, alt_long_15
1211 };
252b5132 1212
76bc74dc
L		 1213 /* Only align for at least a positive non-zero boundary. */
1214 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1215 return;
3e73aa7c 1216
ccc9c027
L		 1217 /* We need to decide which NOP sequence to use for 32bit and
1218 64bit. When -mtune= is used:
4eed87de 1219
76bc74dc
L		 1220 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1221 PROCESSOR_GENERIC32, f32_patt will be used.
1222 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 1223 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1224 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 1225 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
7b458c12 1226 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
69dd9865 1227 will be used.
ccc9c027 1228
76bc74dc 1229 When -mtune= isn't used, alt_long_patt will be used if
22109423 1230 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1231 be used.
ccc9c027
L		 1232
1233 When -march= or .arch is used, we can't use anything beyond
1234 cpu_arch_isa_flags. */
1235
1236 if (flag_code == CODE_16BIT)
1237 {
ccc9c027 1238 if (count > 8)
33fef721 1239 {
76bc74dc
L		 1240 memcpy (fragP->fr_literal + fragP->fr_fix,
1241 jump_31, count);
1242 /* Adjust jump offset. */
1243 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1244 }
76bc74dc
L		 1245 else
1246 memcpy (fragP->fr_literal + fragP->fr_fix,
1247 f16_patt[count - 1], count);
252b5132 1248 }
33fef721 1249 else
ccc9c027
L		 1250 {
1251 const char *const *patt = NULL;
1252
fbf3f584 1253 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1254 {
1255 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1256 switch (cpu_arch_tune)
1257 {
1258 case PROCESSOR_UNKNOWN:
1259 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1260 optimize with nops. */
1261 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1262 patt = alt_long_patt;
ccc9c027
L		 1263 else
1264 patt = f32_patt;
1265 break;
ccc9c027
L		 1266 case PROCESSOR_PENTIUM4:
1267 case PROCESSOR_NOCONA:
ef05d495 1268 case PROCESSOR_CORE:
76bc74dc 1269 case PROCESSOR_CORE2:
bd5295b2 1270 case PROCESSOR_COREI7:
3632d14b 1271 case PROCESSOR_L1OM:
7a9068fe 1272 case PROCESSOR_K1OM:
76bc74dc
L		 1273 case PROCESSOR_GENERIC64:
1274 patt = alt_long_patt;
1275 break;
ccc9c027
L		 1276 case PROCESSOR_K6:
1277 case PROCESSOR_ATHLON:
1278 case PROCESSOR_K8:
4eed87de 1279 case PROCESSOR_AMDFAM10:
8aedb9fe 1280 case PROCESSOR_BD:
7b458c12 1281 case PROCESSOR_BT:
ccc9c027
L		 1282 patt = alt_short_patt;
1283 break;
76bc74dc 1284 case PROCESSOR_I386:
ccc9c027
L		 1285 case PROCESSOR_I486:
1286 case PROCESSOR_PENTIUM:
2dde1948 1287 case PROCESSOR_PENTIUMPRO:
ccc9c027
L		 1288 case PROCESSOR_GENERIC32:
1289 patt = f32_patt;
1290 break;
4eed87de 1291 }
ccc9c027
L		 1292 }
1293 else
1294 {
fbf3f584 1295 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1296 {
1297 case PROCESSOR_UNKNOWN:
e6a14101 1298 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1299 PROCESSOR_UNKNOWN. */
1300 abort ();
1301 break;
1302
76bc74dc 1303 case PROCESSOR_I386:
ccc9c027
L		 1304 case PROCESSOR_I486:
1305 case PROCESSOR_PENTIUM:
ccc9c027
L		 1306 case PROCESSOR_K6:
1307 case PROCESSOR_ATHLON:
1308 case PROCESSOR_K8:
4eed87de 1309 case PROCESSOR_AMDFAM10:
8aedb9fe 1310 case PROCESSOR_BD:
7b458c12 1311 case PROCESSOR_BT:
ccc9c027
L		 1312 case PROCESSOR_GENERIC32:
1313 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1314 with nops. */
1315 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1316 patt = alt_short_patt;
1317 else
1318 patt = f32_patt;
1319 break;
76bc74dc
L		 1320 case PROCESSOR_PENTIUMPRO:
1321 case PROCESSOR_PENTIUM4:
1322 case PROCESSOR_NOCONA:
1323 case PROCESSOR_CORE:
ef05d495 1324 case PROCESSOR_CORE2:
bd5295b2 1325 case PROCESSOR_COREI7:
3632d14b 1326 case PROCESSOR_L1OM:
7a9068fe 1327 case PROCESSOR_K1OM:
22109423 1328 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1329 patt = alt_long_patt;
1330 else
1331 patt = f32_patt;
1332 break;
1333 case PROCESSOR_GENERIC64:
76bc74dc 1334 patt = alt_long_patt;
ccc9c027 1335 break;
4eed87de 1336 }
ccc9c027
L		 1337 }
1338
76bc74dc
L		 1339 if (patt == f32_patt)
1340 {
1341 /* If the padding is less than 15 bytes, we use the normal
1342 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1343 its offset. */
1344 int limit;
76ba9986 1345
711eedef
L		 1346 /* For 64bit, the limit is 3 bytes. */
1347 if (flag_code == CODE_64BIT
1348 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1349 limit = 3;
1350 else
1351 limit = 15;
1352 if (count < limit)
76bc74dc
L		 1353 memcpy (fragP->fr_literal + fragP->fr_fix,
1354 patt[count - 1], count);
1355 else
1356 {
1357 memcpy (fragP->fr_literal + fragP->fr_fix,
1358 jump_31, count);
1359 /* Adjust jump offset. */
1360 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1361 }
1362 }
1363 else
1364 {
1365 /* Maximum length of an instruction is 15 byte. If the
1366 padding is greater than 15 bytes and we don't use jump,
1367 we have to break it into smaller pieces. */
1368 int padding = count;
1369 while (padding > 15)
1370 {
1371 padding -= 15;
1372 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1373 patt [14], 15);
1374 }
1375
1376 if (padding)
1377 memcpy (fragP->fr_literal + fragP->fr_fix,
1378 patt [padding - 1], padding);
1379 }
ccc9c027 1380 }
33fef721 1381 fragP->fr_var = count;
252b5132
RH		 1382}
1383
c6fb90c8 1384static INLINE int
0dfbf9d7 1385operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1386{
0dfbf9d7 1387 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1388 {
1389 case 3:
0dfbf9d7 1390 if (x->array[2])
c6fb90c8
L		 1391 return 0;
1392 case 2:
0dfbf9d7 1393 if (x->array[1])
c6fb90c8
L		 1394 return 0;
1395 case 1:
0dfbf9d7 1396 return !x->array[0];
c6fb90c8
L		 1397 default:
1398 abort ();
1399 }
40fb9820
L		 1400}
1401
c6fb90c8 1402static INLINE void
0dfbf9d7 1403operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1404{
0dfbf9d7 1405 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1406 {
1407 case 3:
0dfbf9d7 1408 x->array[2] = v;
c6fb90c8 1409 case 2:
0dfbf9d7 1410 x->array[1] = v;
c6fb90c8 1411 case 1:
0dfbf9d7 1412 x->array[0] = v;
c6fb90c8
L		 1413 break;
1414 default:
1415 abort ();
1416 }
1417}
40fb9820 1418
c6fb90c8 1419static INLINE int
0dfbf9d7
L		 1420operand_type_equal (const union i386_operand_type *x,
1421 const union i386_operand_type *y)
c6fb90c8 1422{
0dfbf9d7 1423 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1424 {
1425 case 3:
0dfbf9d7 1426 if (x->array[2] != y->array[2])
c6fb90c8
L		 1427 return 0;
1428 case 2:
0dfbf9d7 1429 if (x->array[1] != y->array[1])
c6fb90c8
L		 1430 return 0;
1431 case 1:
0dfbf9d7 1432 return x->array[0] == y->array[0];
c6fb90c8
L		 1433 break;
1434 default:
1435 abort ();
1436 }
1437}
40fb9820 1438
0dfbf9d7
L		 1439static INLINE int
1440cpu_flags_all_zero (const union i386_cpu_flags *x)
1441{
1442 switch (ARRAY_SIZE(x->array))
1443 {
1444 case 3:
1445 if (x->array[2])
1446 return 0;
1447 case 2:
1448 if (x->array[1])
1449 return 0;
1450 case 1:
1451 return !x->array[0];
1452 default:
1453 abort ();
1454 }
1455}
1456
1457static INLINE void
1458cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1459{
1460 switch (ARRAY_SIZE(x->array))
1461 {
1462 case 3:
1463 x->array[2] = v;
1464 case 2:
1465 x->array[1] = v;
1466 case 1:
1467 x->array[0] = v;
1468 break;
1469 default:
1470 abort ();
1471 }
1472}
1473
1474static INLINE int
1475cpu_flags_equal (const union i386_cpu_flags *x,
1476 const union i386_cpu_flags *y)
1477{
1478 switch (ARRAY_SIZE(x->array))
1479 {
1480 case 3:
1481 if (x->array[2] != y->array[2])
1482 return 0;
1483 case 2:
1484 if (x->array[1] != y->array[1])
1485 return 0;
1486 case 1:
1487 return x->array[0] == y->array[0];
1488 break;
1489 default:
1490 abort ();
1491 }
1492}
c6fb90c8
L		 1493
1494static INLINE int
1495cpu_flags_check_cpu64 (i386_cpu_flags f)
1496{
1497 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1498 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1499}
1500
c6fb90c8
L		 1501static INLINE i386_cpu_flags
1502cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1503{
c6fb90c8
L		 1504 switch (ARRAY_SIZE (x.array))
1505 {
1506 case 3:
1507 x.array [2] &= y.array [2];
1508 case 2:
1509 x.array [1] &= y.array [1];
1510 case 1:
1511 x.array [0] &= y.array [0];
1512 break;
1513 default:
1514 abort ();
1515 }
1516 return x;
1517}
40fb9820 1518
c6fb90c8
L		 1519static INLINE i386_cpu_flags
1520cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1521{
c6fb90c8 1522 switch (ARRAY_SIZE (x.array))
40fb9820 1523 {
c6fb90c8
L		 1524 case 3:
1525 x.array [2] |= y.array [2];
1526 case 2:
1527 x.array [1] |= y.array [1];
1528 case 1:
1529 x.array [0] |= y.array [0];
40fb9820
L		 1530 break;
1531 default:
1532 abort ();
1533 }
40fb9820
L		 1534 return x;
1535}
1536
309d3373
JB		 1537static INLINE i386_cpu_flags
1538cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1539{
1540 switch (ARRAY_SIZE (x.array))
1541 {
1542 case 3:
1543 x.array [2] &= ~y.array [2];
1544 case 2:
1545 x.array [1] &= ~y.array [1];
1546 case 1:
1547 x.array [0] &= ~y.array [0];
1548 break;
1549 default:
1550 abort ();
1551 }
1552 return x;
1553}
1554
c0f3af97
L		 1555#define CPU_FLAGS_ARCH_MATCH 0x1
1556#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1557#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1558#define CPU_FLAGS_PCLMUL_MATCH 0x8
1559#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1560
a5ff0eb2 1561#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1562 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1563 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1564#define CPU_FLAGS_PERFECT_MATCH \
1565 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1566
1567/* Return CPU flags match bits. */
3629bb00 1568
40fb9820 1569static int
d3ce72d0 1570cpu_flags_match (const insn_template *t)
40fb9820 1571{
c0f3af97
L		 1572 i386_cpu_flags x = t->cpu_flags;
1573 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1574
1575 x.bitfield.cpu64 = 0;
1576 x.bitfield.cpuno64 = 0;
1577
0dfbf9d7 1578 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1579 {
1580 /* This instruction is available on all archs. */
1581 match |= CPU_FLAGS_32BIT_MATCH;
1582 }
3629bb00
L		 1583 else
1584 {
c0f3af97 1585 /* This instruction is available only on some archs. */
3629bb00
L		 1586 i386_cpu_flags cpu = cpu_arch_flags;
1587
1588 cpu.bitfield.cpu64 = 0;
1589 cpu.bitfield.cpuno64 = 0;
1590 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1591 if (!cpu_flags_all_zero (&cpu))
1592 {
a5ff0eb2
L		 1593 if (x.bitfield.cpuavx)
1594 {
ce2f5b3c 1595 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1596 if (cpu.bitfield.cpuavx)
1597 {
1598 /* Check SSE2AVX. */
1599 if (!t->opcode_modifier.sse2avx|| sse2avx)
1600 {
1601 match |= (CPU_FLAGS_ARCH_MATCH
1602 | CPU_FLAGS_AVX_MATCH);
1603 /* Check AES. */
1604 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1605 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1606 /* Check PCLMUL. */
1607 if (!x.bitfield.cpupclmul
1608 || cpu.bitfield.cpupclmul)
1609 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1610 }
1611 }
1612 else
1613 match |= CPU_FLAGS_ARCH_MATCH;
1614 }
1615 else
c0f3af97
L		 1616 match |= CPU_FLAGS_32BIT_MATCH;
1617 }
3629bb00 1618 }
c0f3af97 1619 return match;
40fb9820
L		 1620}
1621
c6fb90c8
L		 1622static INLINE i386_operand_type
1623operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1624{
c6fb90c8
L		 1625 switch (ARRAY_SIZE (x.array))
1626 {
1627 case 3:
1628 x.array [2] &= y.array [2];
1629 case 2:
1630 x.array [1] &= y.array [1];
1631 case 1:
1632 x.array [0] &= y.array [0];
1633 break;
1634 default:
1635 abort ();
1636 }
1637 return x;
40fb9820
L		 1638}
1639
c6fb90c8
L		 1640static INLINE i386_operand_type
1641operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1642{
c6fb90c8 1643 switch (ARRAY_SIZE (x.array))
40fb9820 1644 {
c6fb90c8
L		 1645 case 3:
1646 x.array [2] |= y.array [2];
1647 case 2:
1648 x.array [1] |= y.array [1];
1649 case 1:
1650 x.array [0] |= y.array [0];
40fb9820
L		 1651 break;
1652 default:
1653 abort ();
1654 }
c6fb90c8
L		 1655 return x;
1656}
40fb9820 1657
c6fb90c8
L		 1658static INLINE i386_operand_type
1659operand_type_xor (i386_operand_type x, i386_operand_type y)
1660{
1661 switch (ARRAY_SIZE (x.array))
1662 {
1663 case 3:
1664 x.array [2] ^= y.array [2];
1665 case 2:
1666 x.array [1] ^= y.array [1];
1667 case 1:
1668 x.array [0] ^= y.array [0];
1669 break;
1670 default:
1671 abort ();
1672 }
40fb9820
L		 1673 return x;
1674}
1675
1676static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1677static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1678static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1679static const i386_operand_type inoutportreg
1680 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1681static const i386_operand_type reg16_inoutportreg
1682 = OPERAND_TYPE_REG16_INOUTPORTREG;
1683static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1684static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1685static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1686static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1687static const i386_operand_type anydisp
1688 = OPERAND_TYPE_ANYDISP;
40fb9820 1689static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1690static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1691static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1692static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1693static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1694static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1695static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1696static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1697static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1698static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1699static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1700static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1701static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1702static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1703
1704enum operand_type
1705{
1706 reg,
40fb9820
L		 1707 imm,
1708 disp,
1709 anymem
1710};
1711
c6fb90c8 1712static INLINE int
40fb9820
L		 1713operand_type_check (i386_operand_type t, enum operand_type c)
1714{
1715 switch (c)
1716 {
1717 case reg:
1718 return (t.bitfield.reg8
1719 || t.bitfield.reg16
1720 || t.bitfield.reg32
1721 || t.bitfield.reg64);
1722
40fb9820
L		 1723 case imm:
1724 return (t.bitfield.imm8
1725 || t.bitfield.imm8s
1726 || t.bitfield.imm16
1727 || t.bitfield.imm32
1728 || t.bitfield.imm32s
1729 || t.bitfield.imm64);
1730
1731 case disp:
1732 return (t.bitfield.disp8
1733 || t.bitfield.disp16
1734 || t.bitfield.disp32
1735 || t.bitfield.disp32s
1736 || t.bitfield.disp64);
1737
1738 case anymem:
1739 return (t.bitfield.disp8
1740 || t.bitfield.disp16
1741 || t.bitfield.disp32
1742 || t.bitfield.disp32s
1743 || t.bitfield.disp64
1744 || t.bitfield.baseindex);
1745
1746 default:
1747 abort ();
1748 }
2cfe26b6
AM		 1749
1750 return 0;
40fb9820
L		 1751}
1752
5c07affc
L		 1753/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1754 operand J for instruction template T. */
1755
1756static INLINE int
d3ce72d0 1757match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1758{
1759 return !((i.types[j].bitfield.byte
1760 && !t->operand_types[j].bitfield.byte)
1761 || (i.types[j].bitfield.word
1762 && !t->operand_types[j].bitfield.word)
1763 || (i.types[j].bitfield.dword
1764 && !t->operand_types[j].bitfield.dword)
1765 || (i.types[j].bitfield.qword
1766 && !t->operand_types[j].bitfield.qword));
1767}
1768
1769/* Return 1 if there is no conflict in any size on operand J for
1770 instruction template T. */
1771
1772static INLINE int
d3ce72d0 1773match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1774{
1775 return (match_reg_size (t, j)
1776 && !((i.types[j].bitfield.unspecified
1777 && !t->operand_types[j].bitfield.unspecified)
1778 || (i.types[j].bitfield.fword
1779 && !t->operand_types[j].bitfield.fword)
1780 || (i.types[j].bitfield.tbyte
1781 && !t->operand_types[j].bitfield.tbyte)
1782 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1783 && !t->operand_types[j].bitfield.xmmword)
1784 || (i.types[j].bitfield.ymmword
43234a1e
L		 1785 && !t->operand_types[j].bitfield.ymmword)
1786 || (i.types[j].bitfield.zmmword
1787 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1788}
1789
1790/* Return 1 if there is no size conflict on any operands for
1791 instruction template T. */
1792
1793static INLINE int
d3ce72d0 1794operand_size_match (const insn_template *t)
5c07affc
L		 1795{
1796 unsigned int j;
1797 int match = 1;
1798
1799 /* Don't check jump instructions. */
1800 if (t->opcode_modifier.jump
1801 || t->opcode_modifier.jumpbyte
1802 || t->opcode_modifier.jumpdword
1803 || t->opcode_modifier.jumpintersegment)
1804 return match;
1805
1806 /* Check memory and accumulator operand size. */
1807 for (j = 0; j < i.operands; j++)
1808 {
1809 if (t->operand_types[j].bitfield.anysize)
1810 continue;
1811
1812 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1813 {
1814 match = 0;
1815 break;
1816 }
1817
1818 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1819 {
1820 match = 0;
1821 break;
1822 }
1823 }
1824
891edac4 1825 if (match)
5c07affc 1826 return match;
891edac4
L		 1827 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1828 {
1829mismatch:
86e026a4 1830 i.error = operand_size_mismatch;
891edac4
L		 1831 return 0;
1832 }
5c07affc
L		 1833
1834 /* Check reverse. */
9c2799c2 1835 gas_assert (i.operands == 2);
5c07affc
L		 1836
1837 match = 1;
1838 for (j = 0; j < 2; j++)
1839 {
1840 if (t->operand_types[j].bitfield.acc
1841 && !match_reg_size (t, j ? 0 : 1))
891edac4 1842 goto mismatch;
5c07affc
L		 1843
1844 if (i.types[j].bitfield.mem
1845 && !match_mem_size (t, j ? 0 : 1))
891edac4 1846 goto mismatch;
5c07affc
L		 1847 }
1848
1849 return match;
1850}
1851
c6fb90c8 1852static INLINE int
40fb9820
L		 1853operand_type_match (i386_operand_type overlap,
1854 i386_operand_type given)
1855{
1856 i386_operand_type temp = overlap;
1857
1858 temp.bitfield.jumpabsolute = 0;
7d5e4556 1859 temp.bitfield.unspecified = 0;
5c07affc
L		 1860 temp.bitfield.byte = 0;
1861 temp.bitfield.word = 0;
1862 temp.bitfield.dword = 0;
1863 temp.bitfield.fword = 0;
1864 temp.bitfield.qword = 0;
1865 temp.bitfield.tbyte = 0;
1866 temp.bitfield.xmmword = 0;
c0f3af97 1867 temp.bitfield.ymmword = 0;
43234a1e 1868 temp.bitfield.zmmword = 0;
0dfbf9d7 1869 if (operand_type_all_zero (&temp))
891edac4 1870 goto mismatch;
40fb9820 1871
891edac4
L		 1872 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1873 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1874 return 1;
1875
1876mismatch:
a65babc9 1877 i.error = operand_type_mismatch;
891edac4 1878 return 0;
40fb9820
L		 1879}
1880
7d5e4556 1881/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1882 unless the expected operand type register overlap is null.
1883 Note that Acc in a template matches every size of reg. */
1884
c6fb90c8 1885static INLINE int
40fb9820
L		 1886operand_type_register_match (i386_operand_type m0,
1887 i386_operand_type g0,
1888 i386_operand_type t0,
1889 i386_operand_type m1,
1890 i386_operand_type g1,
1891 i386_operand_type t1)
1892{
1893 if (!operand_type_check (g0, reg))
1894 return 1;
1895
1896 if (!operand_type_check (g1, reg))
1897 return 1;
1898
1899 if (g0.bitfield.reg8 == g1.bitfield.reg8
1900 && g0.bitfield.reg16 == g1.bitfield.reg16
1901 && g0.bitfield.reg32 == g1.bitfield.reg32
1902 && g0.bitfield.reg64 == g1.bitfield.reg64)
1903 return 1;
1904
1905 if (m0.bitfield.acc)
1906 {
1907 t0.bitfield.reg8 = 1;
1908 t0.bitfield.reg16 = 1;
1909 t0.bitfield.reg32 = 1;
1910 t0.bitfield.reg64 = 1;
1911 }
1912
1913 if (m1.bitfield.acc)
1914 {
1915 t1.bitfield.reg8 = 1;
1916 t1.bitfield.reg16 = 1;
1917 t1.bitfield.reg32 = 1;
1918 t1.bitfield.reg64 = 1;
1919 }
1920
891edac4
L		 1921 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1922 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1923 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1924 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1925 return 1;
1926
a65babc9 1927 i.error = register_type_mismatch;
891edac4
L		 1928
1929 return 0;
40fb9820
L		 1930}
1931
4c692bc7
JB		 1932static INLINE unsigned int
1933register_number (const reg_entry *r)
1934{
1935 unsigned int nr = r->reg_num;
1936
1937 if (r->reg_flags & RegRex)
1938 nr += 8;
1939
1940 return nr;
1941}
1942
252b5132 1943static INLINE unsigned int
40fb9820 1944mode_from_disp_size (i386_operand_type t)
252b5132 1945{
43234a1e 1946 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1947 return 1;
1948 else if (t.bitfield.disp16
1949 || t.bitfield.disp32
1950 || t.bitfield.disp32s)
1951 return 2;
1952 else
1953 return 0;
252b5132
RH		 1954}
1955
1956static INLINE int
65879393 1957fits_in_signed_byte (addressT num)
252b5132 1958{
65879393 1959 return num + 0x80 <= 0xff;
47926f60 1960}
252b5132
RH		 1961
1962static INLINE int
65879393 1963fits_in_unsigned_byte (addressT num)
252b5132 1964{
65879393 1965 return num <= 0xff;
47926f60 1966}
252b5132
RH		 1967
1968static INLINE int
65879393 1969fits_in_unsigned_word (addressT num)
252b5132 1970{
65879393 1971 return num <= 0xffff;
47926f60 1972}
252b5132
RH		 1973
1974static INLINE int
65879393 1975fits_in_signed_word (addressT num)
252b5132 1976{
65879393 1977 return num + 0x8000 <= 0xffff;
47926f60 1978}
2a962e6d 1979
3e73aa7c 1980static INLINE int
65879393 1981fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1982{
1983#ifndef BFD64
1984 return 1;
1985#else
65879393 1986 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 1987#endif
1988} /* fits_in_signed_long() */
2a962e6d 1989
3e73aa7c 1990static INLINE int
65879393 1991fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1992{
1993#ifndef BFD64
1994 return 1;
1995#else
65879393 1996 return num <= 0xffffffff;
3e73aa7c
JH		 1997#endif
1998} /* fits_in_unsigned_long() */
252b5132 1999
43234a1e
L		 2000static INLINE int
2001fits_in_vec_disp8 (offsetT num)
2002{
2003 int shift = i.memshift;
2004 unsigned int mask;
2005
2006 if (shift == -1)
2007 abort ();
2008
2009 mask = (1 << shift) - 1;
2010
2011 /* Return 0 if NUM isn't properly aligned. */
2012 if ((num & mask))
2013 return 0;
2014
2015 /* Check if NUM will fit in 8bit after shift. */
2016 return fits_in_signed_byte (num >> shift);
2017}
2018
a683cc34
SP		 2019static INLINE int
2020fits_in_imm4 (offsetT num)
2021{
2022 return (num & 0xf) == num;
2023}
2024
40fb9820 2025static i386_operand_type
e3bb37b5 2026smallest_imm_type (offsetT num)
252b5132 2027{
40fb9820 2028 i386_operand_type t;
7ab9ffdd 2029
0dfbf9d7 2030 operand_type_set (&t, 0);
40fb9820
L		 2031 t.bitfield.imm64 = 1;
2032
2033 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2034 {
2035 /* This code is disabled on the 486 because all the Imm1 forms
2036 in the opcode table are slower on the i486. They're the
2037 versions with the implicitly specified single-position
2038 displacement, which has another syntax if you really want to
2039 use that form. */
40fb9820
L		 2040 t.bitfield.imm1 = 1;
2041 t.bitfield.imm8 = 1;
2042 t.bitfield.imm8s = 1;
2043 t.bitfield.imm16 = 1;
2044 t.bitfield.imm32 = 1;
2045 t.bitfield.imm32s = 1;
2046 }
2047 else if (fits_in_signed_byte (num))
2048 {
2049 t.bitfield.imm8 = 1;
2050 t.bitfield.imm8s = 1;
2051 t.bitfield.imm16 = 1;
2052 t.bitfield.imm32 = 1;
2053 t.bitfield.imm32s = 1;
2054 }
2055 else if (fits_in_unsigned_byte (num))
2056 {
2057 t.bitfield.imm8 = 1;
2058 t.bitfield.imm16 = 1;
2059 t.bitfield.imm32 = 1;
2060 t.bitfield.imm32s = 1;
2061 }
2062 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2063 {
2064 t.bitfield.imm16 = 1;
2065 t.bitfield.imm32 = 1;
2066 t.bitfield.imm32s = 1;
2067 }
2068 else if (fits_in_signed_long (num))
2069 {
2070 t.bitfield.imm32 = 1;
2071 t.bitfield.imm32s = 1;
2072 }
2073 else if (fits_in_unsigned_long (num))
2074 t.bitfield.imm32 = 1;
2075
2076 return t;
47926f60 2077}
252b5132 2078
847f7ad4 2079static offsetT
e3bb37b5 2080offset_in_range (offsetT val, int size)
847f7ad4 2081{
508866be 2082 addressT mask;
ba2adb93 2083
847f7ad4
AM		 2084 switch (size)
2085 {
508866be
L		 2086 case 1: mask = ((addressT) 1 << 8) - 1; break;
2087 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2088 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2089#ifdef BFD64
2090 case 8: mask = ((addressT) 2 << 63) - 1; break;
2091#endif
47926f60 2092 default: abort ();
847f7ad4
AM		 2093 }
2094
9de868bf
L		 2095#ifdef BFD64
2096 /* If BFD64, sign extend val for 32bit address mode. */
2097 if (flag_code != CODE_64BIT
2098 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2099 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2100 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2101#endif
ba2adb93 2102
47926f60 2103 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2104 {
2105 char buf1[40], buf2[40];
2106
2107 sprint_value (buf1, val);
2108 sprint_value (buf2, val & mask);
2109 as_warn (_("%s shortened to %s"), buf1, buf2);
2110 }
2111 return val & mask;
2112}
2113
c32fa91d
L		 2114enum PREFIX_GROUP
2115{
2116 PREFIX_EXIST = 0,
2117 PREFIX_LOCK,
2118 PREFIX_REP,
2119 PREFIX_OTHER
2120};
2121
2122/* Returns
2123 a. PREFIX_EXIST if attempting to add a prefix where one from the
2124 same class already exists.
2125 b. PREFIX_LOCK if lock prefix is added.
2126 c. PREFIX_REP if rep/repne prefix is added.
2127 d. PREFIX_OTHER if other prefix is added.
2128 */
2129
2130static enum PREFIX_GROUP
e3bb37b5 2131add_prefix (unsigned int prefix)
252b5132 2132{
c32fa91d 2133 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2134 unsigned int q;
252b5132 2135
29b0f896
AM		 2136 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2137 && flag_code == CODE_64BIT)
b1905489 2138 {
161a04f6
L		 2139 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2140 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2141 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2142 ret = PREFIX_EXIST;
b1905489
JB		 2143 q = REX_PREFIX;
2144 }
3e73aa7c 2145 else
b1905489
JB		 2146 {
2147 switch (prefix)
2148 {
2149 default:
2150 abort ();
2151
2152 case CS_PREFIX_OPCODE:
2153 case DS_PREFIX_OPCODE:
2154 case ES_PREFIX_OPCODE:
2155 case FS_PREFIX_OPCODE:
2156 case GS_PREFIX_OPCODE:
2157 case SS_PREFIX_OPCODE:
2158 q = SEG_PREFIX;
2159 break;
2160
2161 case REPNE_PREFIX_OPCODE:
2162 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2163 q = REP_PREFIX;
2164 ret = PREFIX_REP;
2165 break;
2166
b1905489 2167 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2168 q = LOCK_PREFIX;
2169 ret = PREFIX_LOCK;
b1905489
JB		 2170 break;
2171
2172 case FWAIT_OPCODE:
2173 q = WAIT_PREFIX;
2174 break;
2175
2176 case ADDR_PREFIX_OPCODE:
2177 q = ADDR_PREFIX;
2178 break;
2179
2180 case DATA_PREFIX_OPCODE:
2181 q = DATA_PREFIX;
2182 break;
2183 }
2184 if (i.prefix[q] != 0)
c32fa91d 2185 ret = PREFIX_EXIST;
b1905489 2186 }
252b5132 2187
b1905489 2188 if (ret)
252b5132 2189 {
b1905489
JB		 2190 if (!i.prefix[q])
2191 ++i.prefixes;
2192 i.prefix[q] |= prefix;
252b5132 2193 }
b1905489
JB		 2194 else
2195 as_bad (_("same type of prefix used twice"));
252b5132 2196
252b5132
RH		 2197 return ret;
2198}
2199
2200static void
78f12dd3 2201update_code_flag (int value, int check)
eecb386c 2202{
78f12dd3
L		 2203 PRINTF_LIKE ((*as_error));
2204
1e9cc1c2 2205 flag_code = (enum flag_code) value;
40fb9820
L		 2206 if (flag_code == CODE_64BIT)
2207 {
2208 cpu_arch_flags.bitfield.cpu64 = 1;
2209 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2210 }
2211 else
2212 {
2213 cpu_arch_flags.bitfield.cpu64 = 0;
2214 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2215 }
2216 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2217 {
78f12dd3
L		 2218 if (check)
2219 as_error = as_fatal;
2220 else
2221 as_error = as_bad;
2222 (*as_error) (_("64bit mode not supported on `%s'."),
2223 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2224 }
40fb9820 2225 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2226 {
78f12dd3
L		 2227 if (check)
2228 as_error = as_fatal;
2229 else
2230 as_error = as_bad;
2231 (*as_error) (_("32bit mode not supported on `%s'."),
2232 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2233 }
eecb386c
AM		 2234 stackop_size = '\0';
2235}
2236
78f12dd3
L		 2237static void
2238set_code_flag (int value)
2239{
2240 update_code_flag (value, 0);
2241}
2242
eecb386c 2243static void
e3bb37b5 2244set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2245{
1e9cc1c2 2246 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2247 if (flag_code != CODE_16BIT)
2248 abort ();
2249 cpu_arch_flags.bitfield.cpu64 = 0;
2250 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2251 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2252}
2253
2254static void
e3bb37b5 2255set_intel_syntax (int syntax_flag)
252b5132
RH		 2256{
2257 /* Find out if register prefixing is specified. */
2258 int ask_naked_reg = 0;
2259
2260 SKIP_WHITESPACE ();
29b0f896 2261 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2262 {
2263 char *string = input_line_pointer;
2264 int e = get_symbol_end ();
2265
47926f60 2266 if (strcmp (string, "prefix") == 0)
252b5132 2267 ask_naked_reg = 1;
47926f60 2268 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2269 ask_naked_reg = -1;
2270 else
d0b47220 2271 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2272 *input_line_pointer = e;
2273 }
2274 demand_empty_rest_of_line ();
c3332e24 2275
252b5132
RH		 2276 intel_syntax = syntax_flag;
2277
2278 if (ask_naked_reg == 0)
f86103b7
AM		 2279 allow_naked_reg = (intel_syntax
2280 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2281 else
2282 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2283
ee86248c 2284 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2285
e4a3b5a4 2286 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2287 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2288 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2289}
2290
1efbbeb4
L		 2291static void
2292set_intel_mnemonic (int mnemonic_flag)
2293{
e1d4d893 2294 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2295}
2296
db51cc60
L		 2297static void
2298set_allow_index_reg (int flag)
2299{
2300 allow_index_reg = flag;
2301}
2302
cb19c032 2303static void
7bab8ab5 2304set_check (int what)
cb19c032 2305{
7bab8ab5
JB		 2306 enum check_kind *kind;
2307 const char *str;
2308
2309 if (what)
2310 {
2311 kind = &operand_check;
2312 str = "operand";
2313 }
2314 else
2315 {
2316 kind = &sse_check;
2317 str = "sse";
2318 }
2319
cb19c032
L		 2320 SKIP_WHITESPACE ();
2321
2322 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2323 {
2324 char *string = input_line_pointer;
2325 int e = get_symbol_end ();
2326
2327 if (strcmp (string, "none") == 0)
7bab8ab5 2328 *kind = check_none;
cb19c032 2329 else if (strcmp (string, "warning") == 0)
7bab8ab5 2330 *kind = check_warning;
cb19c032 2331 else if (strcmp (string, "error") == 0)
7bab8ab5 2332 *kind = check_error;
cb19c032 2333 else
7bab8ab5 2334 as_bad (_("bad argument to %s_check directive."), str);
cb19c032
L		 2335 *input_line_pointer = e;
2336 }
2337 else
7bab8ab5 2338 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2339
2340 demand_empty_rest_of_line ();
2341}
2342
8a9036a4
L		 2343static void
2344check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2345 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2346{
2347#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2348 static const char *arch;
2349
2350 /* Intel LIOM is only supported on ELF. */
2351 if (!IS_ELF)
2352 return;
2353
2354 if (!arch)
2355 {
2356 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2357 use default_arch. */
2358 arch = cpu_arch_name;
2359 if (!arch)
2360 arch = default_arch;
2361 }
2362
3632d14b 2363 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2364 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2365 || new_flag.bitfield.cpul1om)
8a9036a4 2366 return;
76ba9986 2367
7a9068fe
L		 2368 /* If we are targeting Intel K1OM, we must enable it. */
2369 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2370 || new_flag.bitfield.cpuk1om)
2371 return;
2372
8a9036a4
L		 2373 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2374#endif
2375}
2376
e413e4e9 2377static void
e3bb37b5 2378set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2379{
47926f60 2380 SKIP_WHITESPACE ();
e413e4e9 2381
29b0f896 2382 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2383 {
2384 char *string = input_line_pointer;
2385 int e = get_symbol_end ();
91d6fa6a 2386 unsigned int j;
40fb9820 2387 i386_cpu_flags flags;
e413e4e9 2388
91d6fa6a 2389 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2390 {
91d6fa6a 2391 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2392 {
91d6fa6a 2393 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2394
5c6af06e
JB		 2395 if (*string != '.')
2396 {
91d6fa6a 2397 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2398 cpu_sub_arch_name = NULL;
91d6fa6a 2399 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2400 if (flag_code == CODE_64BIT)
2401 {
2402 cpu_arch_flags.bitfield.cpu64 = 1;
2403 cpu_arch_flags.bitfield.cpuno64 = 0;
2404 }
2405 else
2406 {
2407 cpu_arch_flags.bitfield.cpu64 = 0;
2408 cpu_arch_flags.bitfield.cpuno64 = 1;
2409 }
91d6fa6a
NC		 2410 cpu_arch_isa = cpu_arch[j].type;
2411 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2412 if (!cpu_arch_tune_set)
2413 {
2414 cpu_arch_tune = cpu_arch_isa;
2415 cpu_arch_tune_flags = cpu_arch_isa_flags;
2416 }
5c6af06e
JB		 2417 break;
2418 }
40fb9820 2419
22109423 2420 if (!cpu_arch[j].negated)
309d3373 2421 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2422 cpu_arch[j].flags);
309d3373
JB		 2423 else
2424 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2425 cpu_arch[j].flags);
0dfbf9d7 2426 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2427 {
6305a203
L		 2428 if (cpu_sub_arch_name)
2429 {
2430 char *name = cpu_sub_arch_name;
2431 cpu_sub_arch_name = concat (name,
91d6fa6a 2432 cpu_arch[j].name,
1bf57e9f 2433 (const char *) NULL);
6305a203
L		 2434 free (name);
2435 }
2436 else
91d6fa6a 2437 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2438 cpu_arch_flags = flags;
a586129e 2439 cpu_arch_isa_flags = flags;
5c6af06e
JB		 2440 }
2441 *input_line_pointer = e;
2442 demand_empty_rest_of_line ();
2443 return;
e413e4e9
AM		 2444 }
2445 }
91d6fa6a 2446 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2447 as_bad (_("no such architecture: `%s'"), string);
2448
2449 *input_line_pointer = e;
2450 }
2451 else
2452 as_bad (_("missing cpu architecture"));
2453
fddf5b5b
AM		 2454 no_cond_jump_promotion = 0;
2455 if (*input_line_pointer == ','
29b0f896 2456 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2457 {
2458 char *string = ++input_line_pointer;
2459 int e = get_symbol_end ();
2460
2461 if (strcmp (string, "nojumps") == 0)
2462 no_cond_jump_promotion = 1;
2463 else if (strcmp (string, "jumps") == 0)
2464 ;
2465 else
2466 as_bad (_("no such architecture modifier: `%s'"), string);
2467
2468 *input_line_pointer = e;
2469 }
2470
e413e4e9
AM		 2471 demand_empty_rest_of_line ();
2472}
2473
8a9036a4
L		 2474enum bfd_architecture
2475i386_arch (void)
2476{
3632d14b 2477 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2478 {
2479 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2480 || flag_code != CODE_64BIT)
2481 as_fatal (_("Intel L1OM is 64bit ELF only"));
2482 return bfd_arch_l1om;
2483 }
7a9068fe
L		 2484 else if (cpu_arch_isa == PROCESSOR_K1OM)
2485 {
2486 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2487 || flag_code != CODE_64BIT)
2488 as_fatal (_("Intel K1OM is 64bit ELF only"));
2489 return bfd_arch_k1om;
2490 }
8a9036a4
L		 2491 else
2492 return bfd_arch_i386;
2493}
2494
b9d79e03 2495unsigned long
7016a5d5 2496i386_mach (void)
b9d79e03 2497{
351f65ca 2498 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2499 {
3632d14b 2500 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2501 {
351f65ca
L		 2502 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2503 || default_arch[6] != '\0')
8a9036a4
L		 2504 as_fatal (_("Intel L1OM is 64bit ELF only"));
2505 return bfd_mach_l1om;
2506 }
7a9068fe
L		 2507 else if (cpu_arch_isa == PROCESSOR_K1OM)
2508 {
2509 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2510 || default_arch[6] != '\0')
2511 as_fatal (_("Intel K1OM is 64bit ELF only"));
2512 return bfd_mach_k1om;
2513 }
351f65ca 2514 else if (default_arch[6] == '\0')
8a9036a4 2515 return bfd_mach_x86_64;
351f65ca
L		 2516 else
2517 return bfd_mach_x64_32;
8a9036a4 2518 }
b9d79e03
JH		 2519 else if (!strcmp (default_arch, "i386"))
2520 return bfd_mach_i386_i386;
2521 else
2b5d6a91 2522 as_fatal (_("unknown architecture"));
b9d79e03 2523}
b9d79e03 2524\f
252b5132 2525void
7016a5d5 2526md_begin (void)
252b5132
RH		 2527{
2528 const char *hash_err;
2529
47926f60 2530 /* Initialize op_hash hash table. */
252b5132
RH		 2531 op_hash = hash_new ();
2532
2533 {
d3ce72d0 2534 const insn_template *optab;
29b0f896 2535 templates *core_optab;
252b5132 2536
47926f60
KH		 2537 /* Setup for loop. */
2538 optab = i386_optab;
252b5132
RH		 2539 core_optab = (templates *) xmalloc (sizeof (templates));
2540 core_optab->start = optab;
2541
2542 while (1)
2543 {
2544 ++optab;
2545 if (optab->name == NULL
2546 || strcmp (optab->name, (optab - 1)->name) != 0)
2547 {
2548 /* different name --> ship out current template list;
47926f60 2549 add to hash table; & begin anew. */
252b5132
RH		 2550 core_optab->end = optab;
2551 hash_err = hash_insert (op_hash,
2552 (optab - 1)->name,
5a49b8ac 2553 (void *) core_optab);
252b5132
RH		 2554 if (hash_err)
2555 {
b37df7c4 2556 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2557 (optab - 1)->name,
2558 hash_err);
2559 }
2560 if (optab->name == NULL)
2561 break;
2562 core_optab = (templates *) xmalloc (sizeof (templates));
2563 core_optab->start = optab;
2564 }
2565 }
2566 }
2567
47926f60 2568 /* Initialize reg_hash hash table. */
252b5132
RH		 2569 reg_hash = hash_new ();
2570 {
29b0f896 2571 const reg_entry *regtab;
c3fe08fa 2572 unsigned int regtab_size = i386_regtab_size;
252b5132 2573
c3fe08fa 2574 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2575 {
5a49b8ac 2576 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2577 if (hash_err)
b37df7c4 2578 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2579 regtab->reg_name,
2580 hash_err);
252b5132
RH		 2581 }
2582 }
2583
47926f60 2584 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2585 {
29b0f896
AM		 2586 int c;
2587 char *p;
252b5132
RH		 2588
2589 for (c = 0; c < 256; c++)
2590 {
3882b010 2591 if (ISDIGIT (c))
252b5132
RH		 2592 {
2593 digit_chars[c] = c;
2594 mnemonic_chars[c] = c;
2595 register_chars[c] = c;
2596 operand_chars[c] = c;
2597 }
3882b010 2598 else if (ISLOWER (c))
252b5132
RH		 2599 {
2600 mnemonic_chars[c] = c;
2601 register_chars[c] = c;
2602 operand_chars[c] = c;
2603 }
3882b010 2604 else if (ISUPPER (c))
252b5132 2605 {
3882b010 2606 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2607 register_chars[c] = mnemonic_chars[c];
2608 operand_chars[c] = c;
2609 }
43234a1e
L		 2610 else if (c == '{' || c == '}')
2611 operand_chars[c] = c;
252b5132 2612
3882b010 2613 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2614 identifier_chars[c] = c;
2615 else if (c >= 128)
2616 {
2617 identifier_chars[c] = c;
2618 operand_chars[c] = c;
2619 }
2620 }
2621
2622#ifdef LEX_AT
2623 identifier_chars['@'] = '@';
32137342
NC		 2624#endif
2625#ifdef LEX_QM
2626 identifier_chars['?'] = '?';
2627 operand_chars['?'] = '?';
252b5132 2628#endif
252b5132 2629 digit_chars['-'] = '-';
c0f3af97 2630 mnemonic_chars['_'] = '_';
791fe849 2631 mnemonic_chars['-'] = '-';
0003779b 2632 mnemonic_chars['.'] = '.';
252b5132
RH		 2633 identifier_chars['_'] = '_';
2634 identifier_chars['.'] = '.';
2635
2636 for (p = operand_special_chars; *p != '\0'; p++)
2637 operand_chars[(unsigned char) *p] = *p;
2638 }
2639
a4447b93
RH		 2640 if (flag_code == CODE_64BIT)
2641 {
ca19b261
KT		 2642#if defined (OBJ_COFF) && defined (TE_PE)
2643 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2644 ? 32 : 16);
2645#else
a4447b93 2646 x86_dwarf2_return_column = 16;
ca19b261 2647#endif
61ff971f 2648 x86_cie_data_alignment = -8;
a4447b93
RH		 2649 }
2650 else
2651 {
2652 x86_dwarf2_return_column = 8;
2653 x86_cie_data_alignment = -4;
2654 }
252b5132
RH		 2655}
2656
2657void
e3bb37b5 2658i386_print_statistics (FILE *file)
252b5132
RH		 2659{
2660 hash_print_statistics (file, "i386 opcode", op_hash);
2661 hash_print_statistics (file, "i386 register", reg_hash);
2662}
2663\f
252b5132
RH		 2664#ifdef DEBUG386
2665
ce8a8b2f 2666/* Debugging routines for md_assemble. */
d3ce72d0 2667static void pte (insn_template *);
40fb9820 2668static void pt (i386_operand_type);
e3bb37b5
L		 2669static void pe (expressionS *);
2670static void ps (symbolS *);
252b5132
RH		 2671
2672static void
e3bb37b5 2673pi (char *line, i386_insn *x)
252b5132 2674{
09137c09 2675 unsigned int j;
252b5132
RH		 2676
2677 fprintf (stdout, "%s: template ", line);
2678 pte (&x->tm);
09f131f2
JH		 2679 fprintf (stdout, " address: base %s index %s scale %x\n",
2680 x->base_reg ? x->base_reg->reg_name : "none",
2681 x->index_reg ? x->index_reg->reg_name : "none",
2682 x->log2_scale_factor);
2683 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2684 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2685 fprintf (stdout, " sib: base %x index %x scale %x\n",
2686 x->sib.base, x->sib.index, x->sib.scale);
2687 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2688 (x->rex & REX_W) != 0,
2689 (x->rex & REX_R) != 0,
2690 (x->rex & REX_X) != 0,
2691 (x->rex & REX_B) != 0);
09137c09 2692 for (j = 0; j < x->operands; j++)
252b5132 2693 {
09137c09
SP		 2694 fprintf (stdout, " #%d: ", j + 1);
2695 pt (x->types[j]);
252b5132 2696 fprintf (stdout, "\n");
09137c09
SP		 2697 if (x->types[j].bitfield.reg8
2698 || x->types[j].bitfield.reg16
2699 || x->types[j].bitfield.reg32
2700 || x->types[j].bitfield.reg64
2701 || x->types[j].bitfield.regmmx
2702 || x->types[j].bitfield.regxmm
2703 || x->types[j].bitfield.regymm
43234a1e 2704 || x->types[j].bitfield.regzmm
09137c09
SP		 2705 || x->types[j].bitfield.sreg2
2706 || x->types[j].bitfield.sreg3
2707 || x->types[j].bitfield.control
2708 || x->types[j].bitfield.debug
2709 || x->types[j].bitfield.test)
2710 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2711 if (operand_type_check (x->types[j], imm))
2712 pe (x->op[j].imms);
2713 if (operand_type_check (x->types[j], disp))
2714 pe (x->op[j].disps);
252b5132
RH		 2715 }
2716}
2717
2718static void
d3ce72d0 2719pte (insn_template *t)
252b5132 2720{
09137c09 2721 unsigned int j;
252b5132 2722 fprintf (stdout, " %d operands ", t->operands);
47926f60 2723 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2724 if (t->extension_opcode != None)
2725 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2726 if (t->opcode_modifier.d)
252b5132 2727 fprintf (stdout, "D");
40fb9820 2728 if (t->opcode_modifier.w)
252b5132
RH		 2729 fprintf (stdout, "W");
2730 fprintf (stdout, "\n");
09137c09 2731 for (j = 0; j < t->operands; j++)
252b5132 2732 {
09137c09
SP		 2733 fprintf (stdout, " #%d type ", j + 1);
2734 pt (t->operand_types[j]);
252b5132
RH		 2735 fprintf (stdout, "\n");
2736 }
2737}
2738
2739static void
e3bb37b5 2740pe (expressionS *e)
252b5132 2741{
24eab124 2742 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2743 fprintf (stdout, " add_number %ld (%lx)\n",
2744 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2745 if (e->X_add_symbol)
2746 {
2747 fprintf (stdout, " add_symbol ");
2748 ps (e->X_add_symbol);
2749 fprintf (stdout, "\n");
2750 }
2751 if (e->X_op_symbol)
2752 {
2753 fprintf (stdout, " op_symbol ");
2754 ps (e->X_op_symbol);
2755 fprintf (stdout, "\n");
2756 }
2757}
2758
2759static void
e3bb37b5 2760ps (symbolS *s)
252b5132
RH		 2761{
2762 fprintf (stdout, "%s type %s%s",
2763 S_GET_NAME (s),
2764 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2765 segment_name (S_GET_SEGMENT (s)));
2766}
2767
7b81dfbb 2768static struct type_name
252b5132 2769 {
40fb9820
L		 2770 i386_operand_type mask;
2771 const char *name;
252b5132 2772 }
7b81dfbb 2773const type_names[] =
252b5132 2774{
40fb9820
L		 2775 { OPERAND_TYPE_REG8, "r8" },
2776 { OPERAND_TYPE_REG16, "r16" },
2777 { OPERAND_TYPE_REG32, "r32" },
2778 { OPERAND_TYPE_REG64, "r64" },
2779 { OPERAND_TYPE_IMM8, "i8" },
2780 { OPERAND_TYPE_IMM8, "i8s" },
2781 { OPERAND_TYPE_IMM16, "i16" },
2782 { OPERAND_TYPE_IMM32, "i32" },
2783 { OPERAND_TYPE_IMM32S, "i32s" },
2784 { OPERAND_TYPE_IMM64, "i64" },
2785 { OPERAND_TYPE_IMM1, "i1" },
2786 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2787 { OPERAND_TYPE_DISP8, "d8" },
2788 { OPERAND_TYPE_DISP16, "d16" },
2789 { OPERAND_TYPE_DISP32, "d32" },
2790 { OPERAND_TYPE_DISP32S, "d32s" },
2791 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2792 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2793 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2794 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2795 { OPERAND_TYPE_CONTROL, "control reg" },
2796 { OPERAND_TYPE_TEST, "test reg" },
2797 { OPERAND_TYPE_DEBUG, "debug reg" },
2798 { OPERAND_TYPE_FLOATREG, "FReg" },
2799 { OPERAND_TYPE_FLOATACC, "FAcc" },
2800 { OPERAND_TYPE_SREG2, "SReg2" },
2801 { OPERAND_TYPE_SREG3, "SReg3" },
2802 { OPERAND_TYPE_ACC, "Acc" },
2803 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2804 { OPERAND_TYPE_REGMMX, "rMMX" },
2805 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2806 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2807 { OPERAND_TYPE_REGZMM, "rZMM" },
2808 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2809 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2810};
2811
2812static void
40fb9820 2813pt (i386_operand_type t)
252b5132 2814{
40fb9820 2815 unsigned int j;
c6fb90c8 2816 i386_operand_type a;
252b5132 2817
40fb9820 2818 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2819 {
2820 a = operand_type_and (t, type_names[j].mask);
0349dc08 2821 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2822 fprintf (stdout, "%s, ", type_names[j].name);
2823 }
252b5132
RH		 2824 fflush (stdout);
2825}
2826
2827#endif /* DEBUG386 */
2828\f
252b5132 2829static bfd_reloc_code_real_type
3956db08 2830reloc (unsigned int size,
64e74474
AM		 2831 int pcrel,
2832 int sign,
c3320543 2833 int bnd_prefix,
64e74474 2834 bfd_reloc_code_real_type other)
252b5132 2835{
47926f60 2836 if (other != NO_RELOC)
3956db08 2837 {
91d6fa6a 2838 reloc_howto_type *rel;
3956db08
JB		 2839
2840 if (size == 8)
2841 switch (other)
2842 {
64e74474
AM		 2843 case BFD_RELOC_X86_64_GOT32:
2844 return BFD_RELOC_X86_64_GOT64;
2845 break;
553d1284
L		 2846 case BFD_RELOC_X86_64_GOTPLT64:
2847 return BFD_RELOC_X86_64_GOTPLT64;
2848 break;
64e74474
AM		 2849 case BFD_RELOC_X86_64_PLTOFF64:
2850 return BFD_RELOC_X86_64_PLTOFF64;
2851 break;
2852 case BFD_RELOC_X86_64_GOTPC32:
2853 other = BFD_RELOC_X86_64_GOTPC64;
2854 break;
2855 case BFD_RELOC_X86_64_GOTPCREL:
2856 other = BFD_RELOC_X86_64_GOTPCREL64;
2857 break;
2858 case BFD_RELOC_X86_64_TPOFF32:
2859 other = BFD_RELOC_X86_64_TPOFF64;
2860 break;
2861 case BFD_RELOC_X86_64_DTPOFF32:
2862 other = BFD_RELOC_X86_64_DTPOFF64;
2863 break;
2864 default:
2865 break;
3956db08 2866 }
e05278af 2867
8ce3d284 2868#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2869 if (other == BFD_RELOC_SIZE32)
2870 {
2871 if (size == 8)
1ab668bf 2872 other = BFD_RELOC_SIZE64;
8fd4256d 2873 if (pcrel)
1ab668bf
AM		 2874 {
2875 as_bad (_("there are no pc-relative size relocations"));
2876 return NO_RELOC;
2877 }
8fd4256d 2878 }
8ce3d284 2879#endif
8fd4256d 2880
e05278af 2881 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2882 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2883 sign = -1;
2884
91d6fa6a
NC		 2885 rel = bfd_reloc_type_lookup (stdoutput, other);
2886 if (!rel)
3956db08 2887 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2888 else if (size != bfd_get_reloc_size (rel))
3956db08 2889 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2890 bfd_get_reloc_size (rel),
3956db08 2891 size);
91d6fa6a 2892 else if (pcrel && !rel->pc_relative)
3956db08 2893 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2894 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2895 && !sign)
91d6fa6a 2896 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2897 && sign > 0))
3956db08
JB		 2898 as_bad (_("relocated field and relocation type differ in signedness"));
2899 else
2900 return other;
2901 return NO_RELOC;
2902 }
252b5132
RH		 2903
2904 if (pcrel)
2905 {
3e73aa7c 2906 if (!sign)
3956db08 2907 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2908 switch (size)
2909 {
2910 case 1: return BFD_RELOC_8_PCREL;
2911 case 2: return BFD_RELOC_16_PCREL;
c3320543
L		 2912 case 4: return (bnd_prefix && object_64bit
2913 ? BFD_RELOC_X86_64_PC32_BND
2914 : BFD_RELOC_32_PCREL);
d6ab8113 2915 case 8: return BFD_RELOC_64_PCREL;
252b5132 2916 }
3956db08 2917 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2918 }
2919 else
2920 {
3956db08 2921 if (sign > 0)
e5cb08ac 2922 switch (size)
3e73aa7c
JH		 2923 {
2924 case 4: return BFD_RELOC_X86_64_32S;
2925 }
2926 else
2927 switch (size)
2928 {
2929 case 1: return BFD_RELOC_8;
2930 case 2: return BFD_RELOC_16;
2931 case 4: return BFD_RELOC_32;
2932 case 8: return BFD_RELOC_64;
2933 }
3956db08
JB		 2934 as_bad (_("cannot do %s %u byte relocation"),
2935 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2936 }
2937
0cc9e1d3 2938 return NO_RELOC;
252b5132
RH		 2939}
2940
47926f60
KH		 2941/* Here we decide which fixups can be adjusted to make them relative to
2942 the beginning of the section instead of the symbol. Basically we need
2943 to make sure that the dynamic relocations are done correctly, so in
2944 some cases we force the original symbol to be used. */
2945
252b5132 2946int
e3bb37b5 2947tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2948{
6d249963 2949#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2950 if (!IS_ELF)
31312f95
AM		 2951 return 1;
2952
a161fe53
AM		 2953 /* Don't adjust pc-relative references to merge sections in 64-bit
2954 mode. */
2955 if (use_rela_relocations
2956 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2957 && fixP->fx_pcrel)
252b5132 2958 return 0;
31312f95 2959
8d01d9a9
AJ		 2960 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2961 and changed later by validate_fix. */
2962 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2963 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2964 return 0;
2965
8fd4256d
L		 2966 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2967 for size relocations. */
2968 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2969 || fixP->fx_r_type == BFD_RELOC_SIZE64
2970 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2971 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2972 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2973 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2974 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2975 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2976 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2977 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2978 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2979 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2980 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2981 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2982 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2983 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2984 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2985 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2986 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2987 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2988 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2989 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2990 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2991 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2992 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2993 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2994 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2995 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2996 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2997 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2998 return 0;
31312f95 2999#endif
252b5132
RH		 3000 return 1;
3001}
252b5132 3002
b4cac588 3003static int
e3bb37b5 3004intel_float_operand (const char *mnemonic)
252b5132 3005{
9306ca4a
JB		 3006 /* Note that the value returned is meaningful only for opcodes with (memory)
3007 operands, hence the code here is free to improperly handle opcodes that
3008 have no operands (for better performance and smaller code). */
3009
3010 if (mnemonic[0] != 'f')
3011 return 0; /* non-math */
3012
3013 switch (mnemonic[1])
3014 {
3015 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3016 the fs segment override prefix not currently handled because no
3017 call path can make opcodes without operands get here */
3018 case 'i':
3019 return 2 /* integer op */;
3020 case 'l':
3021 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3022 return 3; /* fldcw/fldenv */
3023 break;
3024 case 'n':
3025 if (mnemonic[2] != 'o' /* fnop */)
3026 return 3; /* non-waiting control op */
3027 break;
3028 case 'r':
3029 if (mnemonic[2] == 's')
3030 return 3; /* frstor/frstpm */
3031 break;
3032 case 's':
3033 if (mnemonic[2] == 'a')
3034 return 3; /* fsave */
3035 if (mnemonic[2] == 't')
3036 {
3037 switch (mnemonic[3])
3038 {
3039 case 'c': /* fstcw */
3040 case 'd': /* fstdw */
3041 case 'e': /* fstenv */
3042 case 's': /* fsts[gw] */
3043 return 3;
3044 }
3045 }
3046 break;
3047 case 'x':
3048 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3049 return 0; /* fxsave/fxrstor are not really math ops */
3050 break;
3051 }
252b5132 3052
9306ca4a 3053 return 1;
252b5132
RH		 3054}
3055
c0f3af97
L		 3056/* Build the VEX prefix. */
3057
3058static void
d3ce72d0 3059build_vex_prefix (const insn_template *t)
c0f3af97
L		 3060{
3061 unsigned int register_specifier;
3062 unsigned int implied_prefix;
3063 unsigned int vector_length;
3064
3065 /* Check register specifier. */
3066 if (i.vex.register_specifier)
43234a1e
L		 3067 {
3068 register_specifier =
3069 ~register_number (i.vex.register_specifier) & 0xf;
3070 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3071 }
c0f3af97
L		 3072 else
3073 register_specifier = 0xf;
3074
fa99fab2
L		 3075 /* Use 2-byte VEX prefix by swappping destination and source
3076 operand. */
3077 if (!i.swap_operand
3078 && i.operands == i.reg_operands
7f399153 3079 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3080 && i.tm.opcode_modifier.s
3081 && i.rex == REX_B)
3082 {
3083 unsigned int xchg = i.operands - 1;
3084 union i386_op temp_op;
3085 i386_operand_type temp_type;
3086
3087 temp_type = i.types[xchg];
3088 i.types[xchg] = i.types[0];
3089 i.types[0] = temp_type;
3090 temp_op = i.op[xchg];
3091 i.op[xchg] = i.op[0];
3092 i.op[0] = temp_op;
3093
9c2799c2 3094 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3095
3096 i.rex = REX_R;
3097 xchg = i.rm.regmem;
3098 i.rm.regmem = i.rm.reg;
3099 i.rm.reg = xchg;
3100
3101 /* Use the next insn. */
3102 i.tm = t[1];
3103 }
3104
539f890d
L		 3105 if (i.tm.opcode_modifier.vex == VEXScalar)
3106 vector_length = avxscalar;
3107 else
3108 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3109
3110 switch ((i.tm.base_opcode >> 8) & 0xff)
3111 {
3112 case 0:
3113 implied_prefix = 0;
3114 break;
3115 case DATA_PREFIX_OPCODE:
3116 implied_prefix = 1;
3117 break;
3118 case REPE_PREFIX_OPCODE:
3119 implied_prefix = 2;
3120 break;
3121 case REPNE_PREFIX_OPCODE:
3122 implied_prefix = 3;
3123 break;
3124 default:
3125 abort ();
3126 }
3127
3128 /* Use 2-byte VEX prefix if possible. */
7f399153 3129 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3130 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3131 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3132 {
3133 /* 2-byte VEX prefix. */
3134 unsigned int r;
3135
3136 i.vex.length = 2;
3137 i.vex.bytes[0] = 0xc5;
3138
3139 /* Check the REX.R bit. */
3140 r = (i.rex & REX_R) ? 0 : 1;
3141 i.vex.bytes[1] = (r << 7
3142 | register_specifier << 3
3143 | vector_length << 2
3144 | implied_prefix);
3145 }
3146 else
3147 {
3148 /* 3-byte VEX prefix. */
3149 unsigned int m, w;
3150
f88c9eb0 3151 i.vex.length = 3;
f88c9eb0 3152
7f399153 3153 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3154 {
7f399153
L		 3155 case VEX0F:
3156 m = 0x1;
80de6e00 3157 i.vex.bytes[0] = 0xc4;
7f399153
L		 3158 break;
3159 case VEX0F38:
3160 m = 0x2;
80de6e00 3161 i.vex.bytes[0] = 0xc4;
7f399153
L		 3162 break;
3163 case VEX0F3A:
3164 m = 0x3;
80de6e00 3165 i.vex.bytes[0] = 0xc4;
7f399153
L		 3166 break;
3167 case XOP08:
5dd85c99
SP		 3168 m = 0x8;
3169 i.vex.bytes[0] = 0x8f;
7f399153
L		 3170 break;
3171 case XOP09:
f88c9eb0
SP		 3172 m = 0x9;
3173 i.vex.bytes[0] = 0x8f;
7f399153
L		 3174 break;
3175 case XOP0A:
f88c9eb0
SP		 3176 m = 0xa;
3177 i.vex.bytes[0] = 0x8f;
7f399153
L		 3178 break;
3179 default:
3180 abort ();
f88c9eb0 3181 }
c0f3af97 3182
c0f3af97
L		 3183 /* The high 3 bits of the second VEX byte are 1's compliment
3184 of RXB bits from REX. */
3185 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3186
3187 /* Check the REX.W bit. */
3188 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3189 if (i.tm.opcode_modifier.vexw == VEXW1)
3190 w = 1;
c0f3af97
L		 3191
3192 i.vex.bytes[2] = (w << 7
3193 | register_specifier << 3
3194 | vector_length << 2
3195 | implied_prefix);
3196 }
3197}
3198
43234a1e
L		 3199/* Build the EVEX prefix. */
3200
3201static void
3202build_evex_prefix (void)
3203{
3204 unsigned int register_specifier;
3205 unsigned int implied_prefix;
3206 unsigned int m, w;
3207 rex_byte vrex_used = 0;
3208
3209 /* Check register specifier. */
3210 if (i.vex.register_specifier)
3211 {
3212 gas_assert ((i.vrex & REX_X) == 0);
3213
3214 register_specifier = i.vex.register_specifier->reg_num;
3215 if ((i.vex.register_specifier->reg_flags & RegRex))
3216 register_specifier += 8;
3217 /* The upper 16 registers are encoded in the fourth byte of the
3218 EVEX prefix. */
3219 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3220 i.vex.bytes[3] = 0x8;
3221 register_specifier = ~register_specifier & 0xf;
3222 }
3223 else
3224 {
3225 register_specifier = 0xf;
3226
3227 /* Encode upper 16 vector index register in the fourth byte of
3228 the EVEX prefix. */
3229 if (!(i.vrex & REX_X))
3230 i.vex.bytes[3] = 0x8;
3231 else
3232 vrex_used |= REX_X;
3233 }
3234
3235 switch ((i.tm.base_opcode >> 8) & 0xff)
3236 {
3237 case 0:
3238 implied_prefix = 0;
3239 break;
3240 case DATA_PREFIX_OPCODE:
3241 implied_prefix = 1;
3242 break;
3243 case REPE_PREFIX_OPCODE:
3244 implied_prefix = 2;
3245 break;
3246 case REPNE_PREFIX_OPCODE:
3247 implied_prefix = 3;
3248 break;
3249 default:
3250 abort ();
3251 }
3252
3253 /* 4 byte EVEX prefix. */
3254 i.vex.length = 4;
3255 i.vex.bytes[0] = 0x62;
3256
3257 /* mmmm bits. */
3258 switch (i.tm.opcode_modifier.vexopcode)
3259 {
3260 case VEX0F:
3261 m = 1;
3262 break;
3263 case VEX0F38:
3264 m = 2;
3265 break;
3266 case VEX0F3A:
3267 m = 3;
3268 break;
3269 default:
3270 abort ();
3271 break;
3272 }
3273
3274 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3275 bits from REX. */
3276 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3277
3278 /* The fifth bit of the second EVEX byte is 1's compliment of the
3279 REX_R bit in VREX. */
3280 if (!(i.vrex & REX_R))
3281 i.vex.bytes[1] |= 0x10;
3282 else
3283 vrex_used |= REX_R;
3284
3285 if ((i.reg_operands + i.imm_operands) == i.operands)
3286 {
3287 /* When all operands are registers, the REX_X bit in REX is not
3288 used. We reuse it to encode the upper 16 registers, which is
3289 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3290 as 1's compliment. */
3291 if ((i.vrex & REX_B))
3292 {
3293 vrex_used |= REX_B;
3294 i.vex.bytes[1] &= ~0x40;
3295 }
3296 }
3297
3298 /* EVEX instructions shouldn't need the REX prefix. */
3299 i.vrex &= ~vrex_used;
3300 gas_assert (i.vrex == 0);
3301
3302 /* Check the REX.W bit. */
3303 w = (i.rex & REX_W) ? 1 : 0;
3304 if (i.tm.opcode_modifier.vexw)
3305 {
3306 if (i.tm.opcode_modifier.vexw == VEXW1)
3307 w = 1;
3308 }
3309 /* If w is not set it means we are dealing with WIG instruction. */
3310 else if (!w)
3311 {
3312 if (evexwig == evexw1)
3313 w = 1;
3314 }
3315
3316 /* Encode the U bit. */
3317 implied_prefix |= 0x4;
3318
3319 /* The third byte of the EVEX prefix. */
3320 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3321
3322 /* The fourth byte of the EVEX prefix. */
3323 /* The zeroing-masking bit. */
3324 if (i.mask && i.mask->zeroing)
3325 i.vex.bytes[3] |= 0x80;
3326
3327 /* Don't always set the broadcast bit if there is no RC. */
3328 if (!i.rounding)
3329 {
3330 /* Encode the vector length. */
3331 unsigned int vec_length;
3332
3333 switch (i.tm.opcode_modifier.evex)
3334 {
3335 case EVEXLIG: /* LL' is ignored */
3336 vec_length = evexlig << 5;
3337 break;
3338 case EVEX128:
3339 vec_length = 0 << 5;
3340 break;
3341 case EVEX256:
3342 vec_length = 1 << 5;
3343 break;
3344 case EVEX512:
3345 vec_length = 2 << 5;
3346 break;
3347 default:
3348 abort ();
3349 break;
3350 }
3351 i.vex.bytes[3] |= vec_length;
3352 /* Encode the broadcast bit. */
3353 if (i.broadcast)
3354 i.vex.bytes[3] |= 0x10;
3355 }
3356 else
3357 {
3358 if (i.rounding->type != saeonly)
3359 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3360 else
d3d3c6db 3361 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3362 }
3363
3364 if (i.mask && i.mask->mask)
3365 i.vex.bytes[3] |= i.mask->mask->reg_num;
3366}
3367
65da13b5
L		 3368static void
3369process_immext (void)
3370{
3371 expressionS *exp;
3372
4c692bc7
JB		 3373 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3374 && i.operands > 0)
65da13b5 3375 {
4c692bc7
JB		 3376 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3377 with an opcode suffix which is coded in the same place as an
3378 8-bit immediate field would be.
3379 Here we check those operands and remove them afterwards. */
65da13b5
L		 3380 unsigned int x;
3381
3382 for (x = 0; x < i.operands; x++)
4c692bc7 3383 if (register_number (i.op[x].regs) != x)
65da13b5 3384 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3385 register_prefix, i.op[x].regs->reg_name, x + 1,
3386 i.tm.name);
3387
3388 i.operands = 0;
65da13b5
L		 3389 }
3390
c0f3af97 3391 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3392 which is coded in the same place as an 8-bit immediate field
3393 would be. Here we fake an 8-bit immediate operand from the
3394 opcode suffix stored in tm.extension_opcode.
3395
c1e679ec 3396 AVX instructions also use this encoding, for some of
c0f3af97 3397 3 argument instructions. */
65da13b5 3398
43234a1e 3399 gas_assert (i.imm_operands <= 1
7ab9ffdd 3400 && (i.operands <= 2
43234a1e
L		 3401 || ((i.tm.opcode_modifier.vex
3402 || i.tm.opcode_modifier.evex)
7ab9ffdd 3403 && i.operands <= 4)));
65da13b5
L		 3404
3405 exp = &im_expressions[i.imm_operands++];
3406 i.op[i.operands].imms = exp;
3407 i.types[i.operands] = imm8;
3408 i.operands++;
3409 exp->X_op = O_constant;
3410 exp->X_add_number = i.tm.extension_opcode;
3411 i.tm.extension_opcode = None;
3412}
3413
42164a71
L		 3414
3415static int
3416check_hle (void)
3417{
3418 switch (i.tm.opcode_modifier.hleprefixok)
3419 {
3420 default:
3421 abort ();
82c2def5 3422 case HLEPrefixNone:
165de32a
L		 3423 as_bad (_("invalid instruction `%s' after `%s'"),
3424 i.tm.name, i.hle_prefix);
42164a71 3425 return 0;
82c2def5 3426 case HLEPrefixLock:
42164a71
L		 3427 if (i.prefix[LOCK_PREFIX])
3428 return 1;
165de32a 3429 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3430 return 0;
82c2def5 3431 case HLEPrefixAny:
42164a71 3432 return 1;
82c2def5 3433 case HLEPrefixRelease:
42164a71
L		 3434 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3435 {
3436 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3437 i.tm.name);
3438 return 0;
3439 }
3440 if (i.mem_operands == 0
3441 || !operand_type_check (i.types[i.operands - 1], anymem))
3442 {
3443 as_bad (_("memory destination needed for instruction `%s'"
3444 " after `xrelease'"), i.tm.name);
3445 return 0;
3446 }
3447 return 1;
3448 }
3449}
3450
252b5132
RH		 3451/* This is the guts of the machine-dependent assembler. LINE points to a
3452 machine dependent instruction. This function is supposed to emit
3453 the frags/bytes it assembles to. */
3454
3455void
65da13b5 3456md_assemble (char *line)
252b5132 3457{
40fb9820 3458 unsigned int j;
252b5132 3459 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3460 const insn_template *t;
252b5132 3461
47926f60 3462 /* Initialize globals. */
252b5132
RH		 3463 memset (&i, '\0', sizeof (i));
3464 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3465 i.reloc[j] = NO_RELOC;
252b5132
RH		 3466 memset (disp_expressions, '\0', sizeof (disp_expressions));
3467 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3468 save_stack_p = save_stack;
252b5132
RH		 3469
3470 /* First parse an instruction mnemonic & call i386_operand for the operands.
3471 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3472 start of a (possibly prefixed) mnemonic. */
252b5132 3473
29b0f896
AM		 3474 line = parse_insn (line, mnemonic);
3475 if (line == NULL)
3476 return;
252b5132 3477
29b0f896 3478 line = parse_operands (line, mnemonic);
ee86248c 3479 this_operand = -1;
29b0f896
AM		 3480 if (line == NULL)
3481 return;
252b5132 3482
29b0f896
AM		 3483 /* Now we've parsed the mnemonic into a set of templates, and have the
3484 operands at hand. */
3485
3486 /* All intel opcodes have reversed operands except for "bound" and
3487 "enter". We also don't reverse intersegment "jmp" and "call"
3488 instructions with 2 immediate operands so that the immediate segment
050dfa73 3489 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3490 if (intel_syntax
3491 && i.operands > 1
29b0f896 3492 && (strcmp (mnemonic, "bound") != 0)
30123838 3493 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3494 && !(operand_type_check (i.types[0], imm)
3495 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3496 swap_operands ();
3497
ec56d5c0
JB		 3498 /* The order of the immediates should be reversed
3499 for 2 immediates extrq and insertq instructions */
3500 if (i.imm_operands == 2
3501 && (strcmp (mnemonic, "extrq") == 0
3502 || strcmp (mnemonic, "insertq") == 0))
3503 swap_2_operands (0, 1);
3504
29b0f896
AM		 3505 if (i.imm_operands)
3506 optimize_imm ();
3507
b300c311
L		 3508 /* Don't optimize displacement for movabs since it only takes 64bit
3509 displacement. */
3510 if (i.disp_operands
a501d77e 3511 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3512 && (flag_code != CODE_64BIT
3513 || strcmp (mnemonic, "movabs") != 0))
3514 optimize_disp ();
29b0f896
AM		 3515
3516 /* Next, we find a template that matches the given insn,
3517 making sure the overlap of the given operands types is consistent
3518 with the template operand types. */
252b5132 3519
fa99fab2 3520 if (!(t = match_template ()))
29b0f896 3521 return;
252b5132 3522
7bab8ab5 3523 if (sse_check != check_none
81f8a913 3524 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3525 && (i.tm.cpu_flags.bitfield.cpusse
3526 || i.tm.cpu_flags.bitfield.cpusse2
3527 || i.tm.cpu_flags.bitfield.cpusse3
3528 || i.tm.cpu_flags.bitfield.cpussse3
3529 || i.tm.cpu_flags.bitfield.cpusse4_1
3530 || i.tm.cpu_flags.bitfield.cpusse4_2))
3531 {
7bab8ab5 3532 (sse_check == check_warning
daf50ae7
L		 3533 ? as_warn
3534 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3535 }
3536
321fd21e
L		 3537 /* Zap movzx and movsx suffix. The suffix has been set from
3538 "word ptr" or "byte ptr" on the source operand in Intel syntax
3539 or extracted from mnemonic in AT&T syntax. But we'll use
3540 the destination register to choose the suffix for encoding. */
3541 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3542 {
321fd21e
L		 3543 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3544 there is no suffix, the default will be byte extension. */
3545 if (i.reg_operands != 2
3546 && !i.suffix
7ab9ffdd 3547 && intel_syntax)
321fd21e
L		 3548 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3549
3550 i.suffix = 0;
cd61ebfe 3551 }
24eab124 3552
40fb9820 3553 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3554 if (!add_prefix (FWAIT_OPCODE))
3555 return;
252b5132 3556
d5de92cf
L		 3557 /* Check if REP prefix is OK. */
3558 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3559 {
3560 as_bad (_("invalid instruction `%s' after `%s'"),
3561 i.tm.name, i.rep_prefix);
3562 return;
3563 }
3564
c1ba0266
L		 3565 /* Check for lock without a lockable instruction. Destination operand
3566 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3567 if (i.prefix[LOCK_PREFIX]
3568 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3569 || i.mem_operands == 0
3570 || (i.tm.base_opcode != 0x86
3571 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3572 {
3573 as_bad (_("expecting lockable instruction after `lock'"));
3574 return;
3575 }
3576
42164a71 3577 /* Check if HLE prefix is OK. */
165de32a 3578 if (i.hle_prefix && !check_hle ())
42164a71
L		 3579 return;
3580
7e8b059b
L		 3581 /* Check BND prefix. */
3582 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3583 as_bad (_("expecting valid branch instruction after `bnd'"));
3584
3585 if (i.tm.cpu_flags.bitfield.cpumpx
3586 && flag_code == CODE_64BIT
3587 && i.prefix[ADDR_PREFIX])
3588 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3589
3590 /* Insert BND prefix. */
3591 if (add_bnd_prefix
3592 && i.tm.opcode_modifier.bndprefixok
3593 && !i.prefix[BND_PREFIX])
3594 add_prefix (BND_PREFIX_OPCODE);
3595
29b0f896 3596 /* Check string instruction segment overrides. */
40fb9820 3597 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3598 {
3599 if (!check_string ())
5dd0794d 3600 return;
fc0763e6 3601 i.disp_operands = 0;
29b0f896 3602 }
5dd0794d 3603
29b0f896
AM		 3604 if (!process_suffix ())
3605 return;
e413e4e9 3606
bc0844ae
L		 3607 /* Update operand types. */
3608 for (j = 0; j < i.operands; j++)
3609 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3610
29b0f896
AM		 3611 /* Make still unresolved immediate matches conform to size of immediate
3612 given in i.suffix. */
3613 if (!finalize_imm ())
3614 return;
252b5132 3615
40fb9820 3616 if (i.types[0].bitfield.imm1)
29b0f896 3617 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3618
9afe6eb8
L		 3619 /* We only need to check those implicit registers for instructions
3620 with 3 operands or less. */
3621 if (i.operands <= 3)
3622 for (j = 0; j < i.operands; j++)
3623 if (i.types[j].bitfield.inoutportreg
3624 || i.types[j].bitfield.shiftcount
3625 || i.types[j].bitfield.acc
3626 || i.types[j].bitfield.floatacc)
3627 i.reg_operands--;
40fb9820 3628
c0f3af97
L		 3629 /* ImmExt should be processed after SSE2AVX. */
3630 if (!i.tm.opcode_modifier.sse2avx
3631 && i.tm.opcode_modifier.immext)
65da13b5 3632 process_immext ();
252b5132 3633
29b0f896
AM		 3634 /* For insns with operands there are more diddles to do to the opcode. */
3635 if (i.operands)
3636 {
3637 if (!process_operands ())
3638 return;
3639 }
40fb9820 3640 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3641 {
3642 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3643 as_warn (_("translating to `%sp'"), i.tm.name);
3644 }
252b5132 3645
9e5e5283
L		 3646 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3647 {
3648 if (flag_code == CODE_16BIT)
3649 {
3650 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3651 i.tm.name);
3652 return;
3653 }
c0f3af97 3654
9e5e5283
L		 3655 if (i.tm.opcode_modifier.vex)
3656 build_vex_prefix (t);
3657 else
3658 build_evex_prefix ();
3659 }
43234a1e 3660
5dd85c99
SP		 3661 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3662 instructions may define INT_OPCODE as well, so avoid this corner
3663 case for those instructions that use MODRM. */
3664 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3665 && !i.tm.opcode_modifier.modrm
3666 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3667 {
3668 i.tm.base_opcode = INT3_OPCODE;
3669 i.imm_operands = 0;
3670 }
252b5132 3671
40fb9820
L		 3672 if ((i.tm.opcode_modifier.jump
3673 || i.tm.opcode_modifier.jumpbyte
3674 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3675 && i.op[0].disps->X_op == O_constant)
3676 {
3677 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3678 the absolute address given by the constant. Since ix86 jumps and
3679 calls are pc relative, we need to generate a reloc. */
3680 i.op[0].disps->X_add_symbol = &abs_symbol;
3681 i.op[0].disps->X_op = O_symbol;
3682 }
252b5132 3683
40fb9820 3684 if (i.tm.opcode_modifier.rex64)
161a04f6 3685 i.rex |= REX_W;
252b5132 3686
29b0f896
AM		 3687 /* For 8 bit registers we need an empty rex prefix. Also if the
3688 instruction already has a prefix, we need to convert old
3689 registers to new ones. */
773f551c 3690
40fb9820 3691 if ((i.types[0].bitfield.reg8
29b0f896 3692 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3693 || (i.types[1].bitfield.reg8
29b0f896 3694 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3695 || ((i.types[0].bitfield.reg8
3696 || i.types[1].bitfield.reg8)
29b0f896
AM		 3697 && i.rex != 0))
3698 {
3699 int x;
726c5dcd 3700
29b0f896
AM		 3701 i.rex |= REX_OPCODE;
3702 for (x = 0; x < 2; x++)
3703 {
3704 /* Look for 8 bit operand that uses old registers. */
40fb9820 3705 if (i.types[x].bitfield.reg8
29b0f896 3706 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3707 {
29b0f896
AM		 3708 /* In case it is "hi" register, give up. */
3709 if (i.op[x].regs->reg_num > 3)
a540244d 3710 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3711 "instruction requiring REX prefix."),
a540244d 3712 register_prefix, i.op[x].regs->reg_name);
773f551c 3713
29b0f896
AM		 3714 /* Otherwise it is equivalent to the extended register.
3715 Since the encoding doesn't change this is merely
3716 cosmetic cleanup for debug output. */
3717
3718 i.op[x].regs = i.op[x].regs + 8;
773f551c 3719 }
29b0f896
AM		 3720 }
3721 }
773f551c 3722
7ab9ffdd 3723 if (i.rex != 0)
29b0f896
AM		 3724 add_prefix (REX_OPCODE | i.rex);
3725
3726 /* We are ready to output the insn. */
3727 output_insn ();
3728}
3729
3730static char *
e3bb37b5 3731parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3732{
3733 char *l = line;
3734 char *token_start = l;
3735 char *mnem_p;
5c6af06e 3736 int supported;
d3ce72d0 3737 const insn_template *t;
b6169b20 3738 char *dot_p = NULL;
29b0f896 3739
29b0f896
AM		 3740 while (1)
3741 {
3742 mnem_p = mnemonic;
3743 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3744 {
b6169b20
L		 3745 if (*mnem_p == '.')
3746 dot_p = mnem_p;
29b0f896
AM		 3747 mnem_p++;
3748 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3749 {
29b0f896
AM		 3750 as_bad (_("no such instruction: `%s'"), token_start);
3751 return NULL;
3752 }
3753 l++;
3754 }
3755 if (!is_space_char (*l)
3756 && *l != END_OF_INSN
e44823cf
JB		 3757 && (intel_syntax
3758 || (*l != PREFIX_SEPARATOR
3759 && *l != ',')))
29b0f896
AM		 3760 {
3761 as_bad (_("invalid character %s in mnemonic"),
3762 output_invalid (*l));
3763 return NULL;
3764 }
3765 if (token_start == l)
3766 {
e44823cf 3767 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3768 as_bad (_("expecting prefix; got nothing"));
3769 else
3770 as_bad (_("expecting mnemonic; got nothing"));
3771 return NULL;
3772 }
45288df1 3773
29b0f896 3774 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3775 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3776
29b0f896
AM		 3777 if (*l != END_OF_INSN
3778 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3779 && current_templates
40fb9820 3780 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3781 {
c6fb90c8 3782 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3783 {
3784 as_bad ((flag_code != CODE_64BIT
3785 ? _("`%s' is only supported in 64-bit mode")
3786 : _("`%s' is not supported in 64-bit mode")),
3787 current_templates->start->name);
3788 return NULL;
3789 }
29b0f896
AM		 3790 /* If we are in 16-bit mode, do not allow addr16 or data16.
3791 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3792 if ((current_templates->start->opcode_modifier.size16
3793 || current_templates->start->opcode_modifier.size32)
29b0f896 3794 && flag_code != CODE_64BIT
40fb9820 3795 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3796 ^ (flag_code == CODE_16BIT)))
3797 {
3798 as_bad (_("redundant %s prefix"),
3799 current_templates->start->name);
3800 return NULL;
45288df1 3801 }
29b0f896
AM		 3802 /* Add prefix, checking for repeated prefixes. */
3803 switch (add_prefix (current_templates->start->base_opcode))
3804 {
c32fa91d 3805 case PREFIX_EXIST:
29b0f896 3806 return NULL;
c32fa91d 3807 case PREFIX_REP:
42164a71 3808 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3809 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3810 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3811 i.bnd_prefix = current_templates->start->name;
42164a71 3812 else
d5de92cf 3813 i.rep_prefix = current_templates->start->name;
29b0f896 3814 break;
c32fa91d
L		 3815 default:
3816 break;
29b0f896
AM		 3817 }
3818 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3819 token_start = ++l;
3820 }
3821 else
3822 break;
3823 }
45288df1 3824
30a55f88 3825 if (!current_templates)
b6169b20 3826 {
f8a5c266
L		 3827 /* Check if we should swap operand or force 32bit displacement in
3828 encoding. */
30a55f88
L		 3829 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3830 i.swap_operand = 1;
8d63c93e 3831 else if (mnem_p - 3 == dot_p
a501d77e
L		 3832 && dot_p[1] == 'd'
3833 && dot_p[2] == '8')
3834 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3835 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3836 && dot_p[1] == 'd'
3837 && dot_p[2] == '3'
3838 && dot_p[3] == '2')
a501d77e 3839 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3840 else
3841 goto check_suffix;
3842 mnem_p = dot_p;
3843 *dot_p = '\0';
d3ce72d0 3844 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3845 }
3846
29b0f896
AM		 3847 if (!current_templates)
3848 {
b6169b20 3849check_suffix:
29b0f896
AM		 3850 /* See if we can get a match by trimming off a suffix. */
3851 switch (mnem_p[-1])
3852 {
3853 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3854 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3855 i.suffix = SHORT_MNEM_SUFFIX;
3856 else
29b0f896
AM		 3857 case BYTE_MNEM_SUFFIX:
3858 case QWORD_MNEM_SUFFIX:
3859 i.suffix = mnem_p[-1];
3860 mnem_p[-1] = '\0';
d3ce72d0
NC		 3861 current_templates = (const templates *) hash_find (op_hash,
3862 mnemonic);
29b0f896
AM		 3863 break;
3864 case SHORT_MNEM_SUFFIX:
3865 case LONG_MNEM_SUFFIX:
3866 if (!intel_syntax)
3867 {
3868 i.suffix = mnem_p[-1];
3869 mnem_p[-1] = '\0';
d3ce72d0
NC		 3870 current_templates = (const templates *) hash_find (op_hash,
3871 mnemonic);
29b0f896
AM		 3872 }
3873 break;
252b5132 3874
29b0f896
AM		 3875 /* Intel Syntax. */
3876 case 'd':
3877 if (intel_syntax)
3878 {
9306ca4a 3879 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3880 i.suffix = SHORT_MNEM_SUFFIX;
3881 else
3882 i.suffix = LONG_MNEM_SUFFIX;
3883 mnem_p[-1] = '\0';
d3ce72d0
NC		 3884 current_templates = (const templates *) hash_find (op_hash,
3885 mnemonic);
29b0f896
AM		 3886 }
3887 break;
3888 }
3889 if (!current_templates)
3890 {
3891 as_bad (_("no such instruction: `%s'"), token_start);
3892 return NULL;
3893 }
3894 }
252b5132 3895
40fb9820
L		 3896 if (current_templates->start->opcode_modifier.jump
3897 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3898 {
3899 /* Check for a branch hint. We allow ",pt" and ",pn" for
3900 predict taken and predict not taken respectively.
3901 I'm not sure that branch hints actually do anything on loop
3902 and jcxz insns (JumpByte) for current Pentium4 chips. They
3903 may work in the future and it doesn't hurt to accept them
3904 now. */
3905 if (l[0] == ',' && l[1] == 'p')
3906 {
3907 if (l[2] == 't')
3908 {
3909 if (!add_prefix (DS_PREFIX_OPCODE))
3910 return NULL;
3911 l += 3;
3912 }
3913 else if (l[2] == 'n')
3914 {
3915 if (!add_prefix (CS_PREFIX_OPCODE))
3916 return NULL;
3917 l += 3;
3918 }
3919 }
3920 }
3921 /* Any other comma loses. */
3922 if (*l == ',')
3923 {
3924 as_bad (_("invalid character %s in mnemonic"),
3925 output_invalid (*l));
3926 return NULL;
3927 }
252b5132 3928
29b0f896 3929 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3930 supported = 0;
3931 for (t = current_templates->start; t < current_templates->end; ++t)
3932 {
c0f3af97
L		 3933 supported |= cpu_flags_match (t);
3934 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3935 goto skip;
5c6af06e 3936 }
3629bb00 3937
c0f3af97 3938 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3939 {
3940 as_bad (flag_code == CODE_64BIT
3941 ? _("`%s' is not supported in 64-bit mode")
3942 : _("`%s' is only supported in 64-bit mode"),
3943 current_templates->start->name);
3944 return NULL;
3945 }
c0f3af97 3946 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3947 {
3629bb00 3948 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3949 current_templates->start->name,
41aacd83 3950 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3951 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3952 return NULL;
29b0f896 3953 }
3629bb00
L		 3954
3955skip:
3956 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3957 && (flag_code != CODE_16BIT))
29b0f896
AM		 3958 {
3959 as_warn (_("use .code16 to ensure correct addressing mode"));
3960 }
252b5132 3961
29b0f896
AM		 3962 return l;
3963}
252b5132 3964
29b0f896 3965static char *
e3bb37b5 3966parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3967{
3968 char *token_start;
3138f287 3969
29b0f896
AM		 3970 /* 1 if operand is pending after ','. */
3971 unsigned int expecting_operand = 0;
252b5132 3972
29b0f896
AM		 3973 /* Non-zero if operand parens not balanced. */
3974 unsigned int paren_not_balanced;
3975
3976 while (*l != END_OF_INSN)
3977 {
3978 /* Skip optional white space before operand. */
3979 if (is_space_char (*l))
3980 ++l;
3981 if (!is_operand_char (*l) && *l != END_OF_INSN)
3982 {
3983 as_bad (_("invalid character %s before operand %d"),
3984 output_invalid (*l),
3985 i.operands + 1);
3986 return NULL;
3987 }
3988 token_start = l; /* after white space */
3989 paren_not_balanced = 0;
3990 while (paren_not_balanced || *l != ',')
3991 {
3992 if (*l == END_OF_INSN)
3993 {
3994 if (paren_not_balanced)
3995 {
3996 if (!intel_syntax)
3997 as_bad (_("unbalanced parenthesis in operand %d."),
3998 i.operands + 1);
3999 else
4000 as_bad (_("unbalanced brackets in operand %d."),
4001 i.operands + 1);
4002 return NULL;
4003 }
4004 else
4005 break; /* we are done */
4006 }
4007 else if (!is_operand_char (*l) && !is_space_char (*l))
4008 {
4009 as_bad (_("invalid character %s in operand %d"),
4010 output_invalid (*l),
4011 i.operands + 1);
4012 return NULL;
4013 }
4014 if (!intel_syntax)
4015 {
4016 if (*l == '(')
4017 ++paren_not_balanced;
4018 if (*l == ')')
4019 --paren_not_balanced;
4020 }
4021 else
4022 {
4023 if (*l == '[')
4024 ++paren_not_balanced;
4025 if (*l == ']')
4026 --paren_not_balanced;
4027 }
4028 l++;
4029 }
4030 if (l != token_start)
4031 { /* Yes, we've read in another operand. */
4032 unsigned int operand_ok;
4033 this_operand = i.operands++;
7d5e4556 4034 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4035 if (i.operands > MAX_OPERANDS)
4036 {
4037 as_bad (_("spurious operands; (%d operands/instruction max)"),
4038 MAX_OPERANDS);
4039 return NULL;
4040 }
4041 /* Now parse operand adding info to 'i' as we go along. */
4042 END_STRING_AND_SAVE (l);
4043
4044 if (intel_syntax)
4045 operand_ok =
4046 i386_intel_operand (token_start,
4047 intel_float_operand (mnemonic));
4048 else
a7619375 4049 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4050
4051 RESTORE_END_STRING (l);
4052 if (!operand_ok)
4053 return NULL;
4054 }
4055 else
4056 {
4057 if (expecting_operand)
4058 {
4059 expecting_operand_after_comma:
4060 as_bad (_("expecting operand after ','; got nothing"));
4061 return NULL;
4062 }
4063 if (*l == ',')
4064 {
4065 as_bad (_("expecting operand before ','; got nothing"));
4066 return NULL;
4067 }
4068 }
7f3f1ea2 4069
29b0f896
AM		 4070 /* Now *l must be either ',' or END_OF_INSN. */
4071 if (*l == ',')
4072 {
4073 if (*++l == END_OF_INSN)
4074 {
4075 /* Just skip it, if it's \n complain. */
4076 goto expecting_operand_after_comma;
4077 }
4078 expecting_operand = 1;
4079 }
4080 }
4081 return l;
4082}
7f3f1ea2 4083
050dfa73 4084static void
4d456e3d 4085swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4086{
4087 union i386_op temp_op;
40fb9820 4088 i386_operand_type temp_type;
050dfa73 4089 enum bfd_reloc_code_real temp_reloc;
4eed87de 4090
050dfa73
MM		 4091 temp_type = i.types[xchg2];
4092 i.types[xchg2] = i.types[xchg1];
4093 i.types[xchg1] = temp_type;
4094 temp_op = i.op[xchg2];
4095 i.op[xchg2] = i.op[xchg1];
4096 i.op[xchg1] = temp_op;
4097 temp_reloc = i.reloc[xchg2];
4098 i.reloc[xchg2] = i.reloc[xchg1];
4099 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4100
4101 if (i.mask)
4102 {
4103 if (i.mask->operand == xchg1)
4104 i.mask->operand = xchg2;
4105 else if (i.mask->operand == xchg2)
4106 i.mask->operand = xchg1;
4107 }
4108 if (i.broadcast)
4109 {
4110 if (i.broadcast->operand == xchg1)
4111 i.broadcast->operand = xchg2;
4112 else if (i.broadcast->operand == xchg2)
4113 i.broadcast->operand = xchg1;
4114 }
4115 if (i.rounding)
4116 {
4117 if (i.rounding->operand == xchg1)
4118 i.rounding->operand = xchg2;
4119 else if (i.rounding->operand == xchg2)
4120 i.rounding->operand = xchg1;
4121 }
050dfa73
MM		 4122}
4123
29b0f896 4124static void
e3bb37b5 4125swap_operands (void)
29b0f896 4126{
b7c61d9a 4127 switch (i.operands)
050dfa73 4128 {
c0f3af97 4129 case 5:
b7c61d9a 4130 case 4:
4d456e3d 4131 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4132 case 3:
4133 case 2:
4d456e3d 4134 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4135 break;
4136 default:
4137 abort ();
29b0f896 4138 }
29b0f896
AM		 4139
4140 if (i.mem_operands == 2)
4141 {
4142 const seg_entry *temp_seg;
4143 temp_seg = i.seg[0];
4144 i.seg[0] = i.seg[1];
4145 i.seg[1] = temp_seg;
4146 }
4147}
252b5132 4148
29b0f896
AM		 4149/* Try to ensure constant immediates are represented in the smallest
4150 opcode possible. */
4151static void
e3bb37b5 4152optimize_imm (void)
29b0f896
AM		 4153{
4154 char guess_suffix = 0;
4155 int op;
252b5132 4156
29b0f896
AM		 4157 if (i.suffix)
4158 guess_suffix = i.suffix;
4159 else if (i.reg_operands)
4160 {
4161 /* Figure out a suffix from the last register operand specified.
4162 We can't do this properly yet, ie. excluding InOutPortReg,
4163 but the following works for instructions with immediates.
4164 In any case, we can't set i.suffix yet. */
4165 for (op = i.operands; --op >= 0;)
40fb9820 4166 if (i.types[op].bitfield.reg8)
7ab9ffdd 4167 {
40fb9820
L		 4168 guess_suffix = BYTE_MNEM_SUFFIX;
4169 break;
4170 }
4171 else if (i.types[op].bitfield.reg16)
252b5132 4172 {
40fb9820
L		 4173 guess_suffix = WORD_MNEM_SUFFIX;
4174 break;
4175 }
4176 else if (i.types[op].bitfield.reg32)
4177 {
4178 guess_suffix = LONG_MNEM_SUFFIX;
4179 break;
4180 }
4181 else if (i.types[op].bitfield.reg64)
4182 {
4183 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4184 break;
252b5132 4185 }
29b0f896
AM		 4186 }
4187 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4188 guess_suffix = WORD_MNEM_SUFFIX;
4189
4190 for (op = i.operands; --op >= 0;)
40fb9820 4191 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4192 {
4193 switch (i.op[op].imms->X_op)
252b5132 4194 {
29b0f896
AM		 4195 case O_constant:
4196 /* If a suffix is given, this operand may be shortened. */
4197 switch (guess_suffix)
252b5132 4198 {
29b0f896 4199 case LONG_MNEM_SUFFIX:
40fb9820
L		 4200 i.types[op].bitfield.imm32 = 1;
4201 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4202 break;
4203 case WORD_MNEM_SUFFIX:
40fb9820
L		 4204 i.types[op].bitfield.imm16 = 1;
4205 i.types[op].bitfield.imm32 = 1;
4206 i.types[op].bitfield.imm32s = 1;
4207 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4208 break;
4209 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4210 i.types[op].bitfield.imm8 = 1;
4211 i.types[op].bitfield.imm8s = 1;
4212 i.types[op].bitfield.imm16 = 1;
4213 i.types[op].bitfield.imm32 = 1;
4214 i.types[op].bitfield.imm32s = 1;
4215 i.types[op].bitfield.imm64 = 1;
29b0f896 4216 break;
252b5132 4217 }
252b5132 4218
29b0f896
AM		 4219 /* If this operand is at most 16 bits, convert it
4220 to a signed 16 bit number before trying to see
4221 whether it will fit in an even smaller size.
4222 This allows a 16-bit operand such as $0xffe0 to
4223 be recognised as within Imm8S range. */
40fb9820 4224 if ((i.types[op].bitfield.imm16)
29b0f896 4225 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4226 {
29b0f896
AM		 4227 i.op[op].imms->X_add_number =
4228 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4229 }
40fb9820 4230 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4231 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4232 == 0))
4233 {
4234 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4235 ^ ((offsetT) 1 << 31))
4236 - ((offsetT) 1 << 31));
4237 }
40fb9820 4238 i.types[op]
c6fb90c8
L		 4239 = operand_type_or (i.types[op],
4240 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4241
29b0f896
AM		 4242 /* We must avoid matching of Imm32 templates when 64bit
4243 only immediate is available. */
4244 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4245 i.types[op].bitfield.imm32 = 0;
29b0f896 4246 break;
252b5132 4247
29b0f896
AM		 4248 case O_absent:
4249 case O_register:
4250 abort ();
4251
4252 /* Symbols and expressions. */
4253 default:
9cd96992
JB		 4254 /* Convert symbolic operand to proper sizes for matching, but don't
4255 prevent matching a set of insns that only supports sizes other
4256 than those matching the insn suffix. */
4257 {
40fb9820 4258 i386_operand_type mask, allowed;
d3ce72d0 4259 const insn_template *t;
9cd96992 4260
0dfbf9d7
L		 4261 operand_type_set (&mask, 0);
4262 operand_type_set (&allowed, 0);
40fb9820 4263
4eed87de
AM		 4264 for (t = current_templates->start;
4265 t < current_templates->end;
4266 ++t)
c6fb90c8
L		 4267 allowed = operand_type_or (allowed,
4268 t->operand_types[op]);
9cd96992
JB		 4269 switch (guess_suffix)
4270 {
4271 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4272 mask.bitfield.imm64 = 1;
4273 mask.bitfield.imm32s = 1;
9cd96992
JB		 4274 break;
4275 case LONG_MNEM_SUFFIX:
40fb9820 4276 mask.bitfield.imm32 = 1;
9cd96992
JB		 4277 break;
4278 case WORD_MNEM_SUFFIX:
40fb9820 4279 mask.bitfield.imm16 = 1;
9cd96992
JB		 4280 break;
4281 case BYTE_MNEM_SUFFIX:
40fb9820 4282 mask.bitfield.imm8 = 1;
9cd96992
JB		 4283 break;
4284 default:
9cd96992
JB		 4285 break;
4286 }
c6fb90c8 4287 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4288 if (!operand_type_all_zero (&allowed))
c6fb90c8 4289 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4290 }
29b0f896 4291 break;
252b5132 4292 }
29b0f896
AM		 4293 }
4294}
47926f60 4295
29b0f896
AM		 4296/* Try to use the smallest displacement type too. */
4297static void
e3bb37b5 4298optimize_disp (void)
29b0f896
AM		 4299{
4300 int op;
3e73aa7c 4301
29b0f896 4302 for (op = i.operands; --op >= 0;)
40fb9820 4303 if (operand_type_check (i.types[op], disp))
252b5132 4304 {
b300c311 4305 if (i.op[op].disps->X_op == O_constant)
252b5132 4306 {
91d6fa6a 4307 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4308
40fb9820 4309 if (i.types[op].bitfield.disp16
91d6fa6a 4310 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4311 {
4312 /* If this operand is at most 16 bits, convert
4313 to a signed 16 bit number and don't use 64bit
4314 displacement. */
91d6fa6a 4315 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4316 i.types[op].bitfield.disp64 = 0;
b300c311 4317 }
40fb9820 4318 if (i.types[op].bitfield.disp32
91d6fa6a 4319 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4320 {
4321 /* If this operand is at most 32 bits, convert
4322 to a signed 32 bit number and don't use 64bit
4323 displacement. */
91d6fa6a
NC		 4324 op_disp &= (((offsetT) 2 << 31) - 1);
4325 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4326 i.types[op].bitfield.disp64 = 0;
b300c311 4327 }
91d6fa6a 4328 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4329 {
40fb9820
L		 4330 i.types[op].bitfield.disp8 = 0;
4331 i.types[op].bitfield.disp16 = 0;
4332 i.types[op].bitfield.disp32 = 0;
4333 i.types[op].bitfield.disp32s = 0;
4334 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4335 i.op[op].disps = 0;
4336 i.disp_operands--;
4337 }
4338 else if (flag_code == CODE_64BIT)
4339 {
91d6fa6a 4340 if (fits_in_signed_long (op_disp))
28a9d8f5 4341 {
40fb9820
L		 4342 i.types[op].bitfield.disp64 = 0;
4343 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4344 }
0e1147d9 4345 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4346 && fits_in_unsigned_long (op_disp))
40fb9820 4347 i.types[op].bitfield.disp32 = 1;
b300c311 4348 }
40fb9820
L		 4349 if ((i.types[op].bitfield.disp32
4350 || i.types[op].bitfield.disp32s
4351 || i.types[op].bitfield.disp16)
91d6fa6a 4352 && fits_in_signed_byte (op_disp))
40fb9820 4353 i.types[op].bitfield.disp8 = 1;
252b5132 4354 }
67a4f2b7
AO		 4355 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4356 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4357 {
4358 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4359 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4360 i.types[op].bitfield.disp8 = 0;
4361 i.types[op].bitfield.disp16 = 0;
4362 i.types[op].bitfield.disp32 = 0;
4363 i.types[op].bitfield.disp32s = 0;
4364 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4365 }
4366 else
b300c311 4367 /* We only support 64bit displacement on constants. */
40fb9820 4368 i.types[op].bitfield.disp64 = 0;
252b5132 4369 }
29b0f896
AM		 4370}
4371
6c30d220
L		 4372/* Check if operands are valid for the instruction. */
4373
4374static int
4375check_VecOperands (const insn_template *t)
4376{
43234a1e
L		 4377 unsigned int op;
4378
6c30d220
L		 4379 /* Without VSIB byte, we can't have a vector register for index. */
4380 if (!t->opcode_modifier.vecsib
4381 && i.index_reg
4382 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4383 || i.index_reg->reg_type.bitfield.regymm
4384 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4385 {
4386 i.error = unsupported_vector_index_register;
4387 return 1;
4388 }
4389
ad8ecc81
MZ		 4390 /* Check if default mask is allowed. */
4391 if (t->opcode_modifier.nodefmask
4392 && (!i.mask || i.mask->mask->reg_num == 0))
4393 {
4394 i.error = no_default_mask;
4395 return 1;
4396 }
4397
7bab8ab5
JB		 4398 /* For VSIB byte, we need a vector register for index, and all vector
4399 registers must be distinct. */
4400 if (t->opcode_modifier.vecsib)
4401 {
4402 if (!i.index_reg
6c30d220
L		 4403 || !((t->opcode_modifier.vecsib == VecSIB128
4404 && i.index_reg->reg_type.bitfield.regxmm)
4405 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4406 && i.index_reg->reg_type.bitfield.regymm)
4407 || (t->opcode_modifier.vecsib == VecSIB512
4408 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4409 {
4410 i.error = invalid_vsib_address;
4411 return 1;
4412 }
4413
43234a1e
L		 4414 gas_assert (i.reg_operands == 2 || i.mask);
4415 if (i.reg_operands == 2 && !i.mask)
4416 {
4417 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4418 || i.types[0].bitfield.regymm);
43234a1e 4419 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4420 || i.types[2].bitfield.regymm);
43234a1e
L		 4421 if (operand_check == check_none)
4422 return 0;
4423 if (register_number (i.op[0].regs)
4424 != register_number (i.index_reg)
4425 && register_number (i.op[2].regs)
4426 != register_number (i.index_reg)
4427 && register_number (i.op[0].regs)
4428 != register_number (i.op[2].regs))
4429 return 0;
4430 if (operand_check == check_error)
4431 {
4432 i.error = invalid_vector_register_set;
4433 return 1;
4434 }
4435 as_warn (_("mask, index, and destination registers should be distinct"));
4436 }
8444f82a
MZ		 4437 else if (i.reg_operands == 1 && i.mask)
4438 {
4439 if ((i.types[1].bitfield.regymm
4440 || i.types[1].bitfield.regzmm)
4441 && (register_number (i.op[1].regs)
4442 == register_number (i.index_reg)))
4443 {
4444 if (operand_check == check_error)
4445 {
4446 i.error = invalid_vector_register_set;
4447 return 1;
4448 }
4449 if (operand_check != check_none)
4450 as_warn (_("index and destination registers should be distinct"));
4451 }
4452 }
43234a1e 4453 }
7bab8ab5 4454
43234a1e
L		 4455 /* Check if broadcast is supported by the instruction and is applied
4456 to the memory operand. */
4457 if (i.broadcast)
4458 {
4459 int broadcasted_opnd_size;
4460
4461 /* Check if specified broadcast is supported in this instruction,
4462 and it's applied to memory operand of DWORD or QWORD type,
4463 depending on VecESize. */
4464 if (i.broadcast->type != t->opcode_modifier.broadcast
4465 || !i.types[i.broadcast->operand].bitfield.mem
4466 || (t->opcode_modifier.vecesize == 0
4467 && !i.types[i.broadcast->operand].bitfield.dword
4468 && !i.types[i.broadcast->operand].bitfield.unspecified)
4469 || (t->opcode_modifier.vecesize == 1
4470 && !i.types[i.broadcast->operand].bitfield.qword
4471 && !i.types[i.broadcast->operand].bitfield.unspecified))
4472 goto bad_broadcast;
4473
4474 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4475 if (i.broadcast->type == BROADCAST_1TO16)
4476 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4477 else if (i.broadcast->type == BROADCAST_1TO8)
4478 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4479 else if (i.broadcast->type == BROADCAST_1TO4)
4480 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4481 else if (i.broadcast->type == BROADCAST_1TO2)
4482 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4483 else
4484 goto bad_broadcast;
4485
4486 if ((broadcasted_opnd_size == 256
4487 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4488 || (broadcasted_opnd_size == 512
4489 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4490 {
4491 bad_broadcast:
4492 i.error = unsupported_broadcast;
4493 return 1;
4494 }
4495 }
4496 /* If broadcast is supported in this instruction, we need to check if
4497 operand of one-element size isn't specified without broadcast. */
4498 else if (t->opcode_modifier.broadcast && i.mem_operands)
4499 {
4500 /* Find memory operand. */
4501 for (op = 0; op < i.operands; op++)
4502 if (operand_type_check (i.types[op], anymem))
4503 break;
4504 gas_assert (op < i.operands);
4505 /* Check size of the memory operand. */
4506 if ((t->opcode_modifier.vecesize == 0
4507 && i.types[op].bitfield.dword)
4508 || (t->opcode_modifier.vecesize == 1
4509 && i.types[op].bitfield.qword))
4510 {
4511 i.error = broadcast_needed;
4512 return 1;
4513 }
4514 }
4515
4516 /* Check if requested masking is supported. */
4517 if (i.mask
4518 && (!t->opcode_modifier.masking
4519 || (i.mask->zeroing
4520 && t->opcode_modifier.masking == MERGING_MASKING)))
4521 {
4522 i.error = unsupported_masking;
4523 return 1;
4524 }
4525
4526 /* Check if masking is applied to dest operand. */
4527 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4528 {
4529 i.error = mask_not_on_destination;
4530 return 1;
4531 }
4532
43234a1e
L		 4533 /* Check RC/SAE. */
4534 if (i.rounding)
4535 {
4536 if ((i.rounding->type != saeonly
4537 && !t->opcode_modifier.staticrounding)
4538 || (i.rounding->type == saeonly
4539 && (t->opcode_modifier.staticrounding
4540 || !t->opcode_modifier.sae)))
4541 {
4542 i.error = unsupported_rc_sae;
4543 return 1;
4544 }
4545 /* If the instruction has several immediate operands and one of
4546 them is rounding, the rounding operand should be the last
4547 immediate operand. */
4548 if (i.imm_operands > 1
4549 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4550 {
43234a1e 4551 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4552 return 1;
4553 }
6c30d220
L		 4554 }
4555
43234a1e
L		 4556 /* Check vector Disp8 operand. */
4557 if (t->opcode_modifier.disp8memshift)
4558 {
4559 if (i.broadcast)
4560 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4561 else
4562 i.memshift = t->opcode_modifier.disp8memshift;
4563
4564 for (op = 0; op < i.operands; op++)
4565 if (operand_type_check (i.types[op], disp)
4566 && i.op[op].disps->X_op == O_constant)
4567 {
4568 offsetT value = i.op[op].disps->X_add_number;
4569 int vec_disp8_ok = fits_in_vec_disp8 (value);
4570 if (t->operand_types [op].bitfield.vec_disp8)
4571 {
4572 if (vec_disp8_ok)
4573 i.types[op].bitfield.vec_disp8 = 1;
4574 else
4575 {
4576 /* Vector insn can only have Vec_Disp8/Disp32 in
4577 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4578 mode. */
4579 i.types[op].bitfield.disp8 = 0;
4580 if (flag_code != CODE_16BIT)
4581 i.types[op].bitfield.disp16 = 0;
4582 }
4583 }
4584 else if (flag_code != CODE_16BIT)
4585 {
4586 /* One form of this instruction supports vector Disp8.
4587 Try vector Disp8 if we need to use Disp32. */
4588 if (vec_disp8_ok && !fits_in_signed_byte (value))
4589 {
4590 i.error = try_vector_disp8;
4591 return 1;
4592 }
4593 }
4594 }
4595 }
4596 else
4597 i.memshift = -1;
4598
6c30d220
L		 4599 return 0;
4600}
4601
43f3e2ee 4602/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4603 operand types. */
4604
4605static int
4606VEX_check_operands (const insn_template *t)
4607{
43234a1e
L		 4608 /* VREX is only valid with EVEX prefix. */
4609 if (i.need_vrex && !t->opcode_modifier.evex)
4610 {
4611 i.error = invalid_register_operand;
4612 return 1;
4613 }
4614
a683cc34
SP		 4615 if (!t->opcode_modifier.vex)
4616 return 0;
4617
4618 /* Only check VEX_Imm4, which must be the first operand. */
4619 if (t->operand_types[0].bitfield.vec_imm4)
4620 {
4621 if (i.op[0].imms->X_op != O_constant
4622 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4623 {
a65babc9 4624 i.error = bad_imm4;
891edac4
L		 4625 return 1;
4626 }
a683cc34
SP		 4627
4628 /* Turn off Imm8 so that update_imm won't complain. */
4629 i.types[0] = vec_imm4;
4630 }
4631
4632 return 0;
4633}
4634
d3ce72d0 4635static const insn_template *
e3bb37b5 4636match_template (void)
29b0f896
AM		 4637{
4638 /* Points to template once we've found it. */
d3ce72d0 4639 const insn_template *t;
40fb9820 4640 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4641 i386_operand_type overlap4;
29b0f896 4642 unsigned int found_reverse_match;
40fb9820
L		 4643 i386_opcode_modifier suffix_check;
4644 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4645 int addr_prefix_disp;
a5c311ca 4646 unsigned int j;
3629bb00 4647 unsigned int found_cpu_match;
45664ddb 4648 unsigned int check_register;
5614d22c 4649 enum i386_error specific_error = 0;
29b0f896 4650
c0f3af97
L		 4651#if MAX_OPERANDS != 5
4652# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4653#endif
4654
29b0f896 4655 found_reverse_match = 0;
539e75ad 4656 addr_prefix_disp = -1;
40fb9820
L		 4657
4658 memset (&suffix_check, 0, sizeof (suffix_check));
4659 if (i.suffix == BYTE_MNEM_SUFFIX)
4660 suffix_check.no_bsuf = 1;
4661 else if (i.suffix == WORD_MNEM_SUFFIX)
4662 suffix_check.no_wsuf = 1;
4663 else if (i.suffix == SHORT_MNEM_SUFFIX)
4664 suffix_check.no_ssuf = 1;
4665 else if (i.suffix == LONG_MNEM_SUFFIX)
4666 suffix_check.no_lsuf = 1;
4667 else if (i.suffix == QWORD_MNEM_SUFFIX)
4668 suffix_check.no_qsuf = 1;
4669 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4670 suffix_check.no_ldsuf = 1;
29b0f896 4671
01559ecc
L		 4672 /* Must have right number of operands. */
4673 i.error = number_of_operands_mismatch;
4674
45aa61fe 4675 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4676 {
539e75ad
L		 4677 addr_prefix_disp = -1;
4678
29b0f896
AM		 4679 if (i.operands != t->operands)
4680 continue;
4681
50aecf8c 4682 /* Check processor support. */
a65babc9 4683 i.error = unsupported;
c0f3af97
L		 4684 found_cpu_match = (cpu_flags_match (t)
4685 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4686 if (!found_cpu_match)
4687 continue;
4688
e1d4d893 4689 /* Check old gcc support. */
a65babc9 4690 i.error = old_gcc_only;
e1d4d893
L		 4691 if (!old_gcc && t->opcode_modifier.oldgcc)
4692 continue;
4693
4694 /* Check AT&T mnemonic. */
a65babc9 4695 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4696 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4697 continue;
4698
891edac4 4699 /* Check AT&T/Intel syntax. */
a65babc9 4700 i.error = unsupported_syntax;
5c07affc
L		 4701 if ((intel_syntax && t->opcode_modifier.attsyntax)
4702 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4703 continue;
4704
20592a94 4705 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4706 i.error = invalid_instruction_suffix;
567e4e96
L		 4707 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4708 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4709 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4710 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4711 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4712 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4713 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4714 continue;
4715
5c07affc 4716 if (!operand_size_match (t))
7d5e4556 4717 continue;
539e75ad 4718
5c07affc
L		 4719 for (j = 0; j < MAX_OPERANDS; j++)
4720 operand_types[j] = t->operand_types[j];
4721
45aa61fe
AM		 4722 /* In general, don't allow 64-bit operands in 32-bit mode. */
4723 if (i.suffix == QWORD_MNEM_SUFFIX
4724 && flag_code != CODE_64BIT
4725 && (intel_syntax
40fb9820 4726 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4727 && !intel_float_operand (t->name))
4728 : intel_float_operand (t->name) != 2)
40fb9820 4729 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4730 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4731 && !operand_types[0].bitfield.regymm
4732 && !operand_types[0].bitfield.regzmm)
40fb9820 4733 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4734 && operand_types[t->operands > 1].bitfield.regxmm
4735 && operand_types[t->operands > 1].bitfield.regymm
4736 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4737 && (t->base_opcode != 0x0fc7
4738 || t->extension_opcode != 1 /* cmpxchg8b */))
4739 continue;
4740
192dc9c6
JB		 4741 /* In general, don't allow 32-bit operands on pre-386. */
4742 else if (i.suffix == LONG_MNEM_SUFFIX
4743 && !cpu_arch_flags.bitfield.cpui386
4744 && (intel_syntax
4745 ? (!t->opcode_modifier.ignoresize
4746 && !intel_float_operand (t->name))
4747 : intel_float_operand (t->name) != 2)
4748 && ((!operand_types[0].bitfield.regmmx
4749 && !operand_types[0].bitfield.regxmm)
4750 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 4751 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 4752 continue;
4753
29b0f896 4754 /* Do not verify operands when there are none. */
50aecf8c 4755 else
29b0f896 4756 {
c6fb90c8 4757 if (!t->operands)
2dbab7d5
L		 4758 /* We've found a match; break out of loop. */
4759 break;
29b0f896 4760 }
252b5132 4761
539e75ad
L		 4762 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4763 into Disp32/Disp16/Disp32 operand. */
4764 if (i.prefix[ADDR_PREFIX] != 0)
4765 {
40fb9820 4766 /* There should be only one Disp operand. */
539e75ad
L		 4767 switch (flag_code)
4768 {
4769 case CODE_16BIT:
40fb9820
L		 4770 for (j = 0; j < MAX_OPERANDS; j++)
4771 {
4772 if (operand_types[j].bitfield.disp16)
4773 {
4774 addr_prefix_disp = j;
4775 operand_types[j].bitfield.disp32 = 1;
4776 operand_types[j].bitfield.disp16 = 0;
4777 break;
4778 }
4779 }
539e75ad
L		 4780 break;
4781 case CODE_32BIT:
40fb9820
L		 4782 for (j = 0; j < MAX_OPERANDS; j++)
4783 {
4784 if (operand_types[j].bitfield.disp32)
4785 {
4786 addr_prefix_disp = j;
4787 operand_types[j].bitfield.disp32 = 0;
4788 operand_types[j].bitfield.disp16 = 1;
4789 break;
4790 }
4791 }
539e75ad
L		 4792 break;
4793 case CODE_64BIT:
40fb9820
L		 4794 for (j = 0; j < MAX_OPERANDS; j++)
4795 {
4796 if (operand_types[j].bitfield.disp64)
4797 {
4798 addr_prefix_disp = j;
4799 operand_types[j].bitfield.disp64 = 0;
4800 operand_types[j].bitfield.disp32 = 1;
4801 break;
4802 }
4803 }
539e75ad
L		 4804 break;
4805 }
539e75ad
L		 4806 }
4807
56ffb741
L		 4808 /* We check register size if needed. */
4809 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4810 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4811 switch (t->operands)
4812 {
4813 case 1:
40fb9820 4814 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4815 continue;
4816 break;
4817 case 2:
8b38ad71
L		 4818 /* xchg %eax, %eax is a special case. It is an aliase for nop
4819 only in 32bit mode and we can use opcode 0x90. In 64bit
4820 mode, we can't use 0x90 for xchg %eax, %eax since it should
4821 zero-extend %eax to %rax. */
4822 if (flag_code == CODE_64BIT
4823 && t->base_opcode == 0x90
0dfbf9d7
L		 4824 && operand_type_equal (&i.types [0], &acc32)
4825 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4826 continue;
b6169b20
L		 4827 if (i.swap_operand)
4828 {
4829 /* If we swap operand in encoding, we either match
4830 the next one or reverse direction of operands. */
4831 if (t->opcode_modifier.s)
4832 continue;
4833 else if (t->opcode_modifier.d)
4834 goto check_reverse;
4835 }
4836
29b0f896 4837 case 3:
fa99fab2
L		 4838 /* If we swap operand in encoding, we match the next one. */
4839 if (i.swap_operand && t->opcode_modifier.s)
4840 continue;
f48ff2ae 4841 case 4:
c0f3af97 4842 case 5:
c6fb90c8 4843 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4844 if (!operand_type_match (overlap0, i.types[0])
4845 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4846 || (check_register
4847 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4848 operand_types[0],
4849 overlap1, i.types[1],
4850 operand_types[1])))
29b0f896
AM		 4851 {
4852 /* Check if other direction is valid ... */
40fb9820 4853 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4854 continue;
4855
b6169b20 4856check_reverse:
29b0f896 4857 /* Try reversing direction of operands. */
c6fb90c8
L		 4858 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4859 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4860 if (!operand_type_match (overlap0, i.types[0])
4861 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4862 || (check_register
4863 && !operand_type_register_match (overlap0,
4864 i.types[0],
4865 operand_types[1],
4866 overlap1,
4867 i.types[1],
4868 operand_types[0])))
29b0f896
AM		 4869 {
4870 /* Does not match either direction. */
4871 continue;
4872 }
4873 /* found_reverse_match holds which of D or FloatDR
4874 we've found. */
40fb9820 4875 if (t->opcode_modifier.d)
8a2ed489 4876 found_reverse_match = Opcode_D;
40fb9820 4877 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4878 found_reverse_match = Opcode_FloatD;
4879 else
4880 found_reverse_match = 0;
40fb9820 4881 if (t->opcode_modifier.floatr)
8a2ed489 4882 found_reverse_match |= Opcode_FloatR;
29b0f896 4883 }
f48ff2ae 4884 else
29b0f896 4885 {
f48ff2ae 4886 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4887 switch (t->operands)
4888 {
c0f3af97
L		 4889 case 5:
4890 overlap4 = operand_type_and (i.types[4],
4891 operand_types[4]);
d1cbb4db 4892 case 4:
c6fb90c8
L		 4893 overlap3 = operand_type_and (i.types[3],
4894 operand_types[3]);
d1cbb4db 4895 case 3:
c6fb90c8
L		 4896 overlap2 = operand_type_and (i.types[2],
4897 operand_types[2]);
d1cbb4db
L		 4898 break;
4899 }
29b0f896 4900
f48ff2ae
L		 4901 switch (t->operands)
4902 {
c0f3af97
L		 4903 case 5:
4904 if (!operand_type_match (overlap4, i.types[4])
4905 || !operand_type_register_match (overlap3,
4906 i.types[3],
4907 operand_types[3],
4908 overlap4,
4909 i.types[4],
4910 operand_types[4]))
4911 continue;
f48ff2ae 4912 case 4:
40fb9820 4913 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4914 || (check_register
4915 && !operand_type_register_match (overlap2,
4916 i.types[2],
4917 operand_types[2],
4918 overlap3,
4919 i.types[3],
4920 operand_types[3])))
f48ff2ae
L		 4921 continue;
4922 case 3:
4923 /* Here we make use of the fact that there are no
4924 reverse match 3 operand instructions, and all 3
4925 operand instructions only need to be checked for
4926 register consistency between operands 2 and 3. */
40fb9820 4927 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4928 || (check_register
4929 && !operand_type_register_match (overlap1,
4930 i.types[1],
4931 operand_types[1],
4932 overlap2,
4933 i.types[2],
4934 operand_types[2])))
f48ff2ae
L		 4935 continue;
4936 break;
4937 }
29b0f896 4938 }
f48ff2ae 4939 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4940 slip through to break. */
4941 }
3629bb00 4942 if (!found_cpu_match)
29b0f896
AM		 4943 {
4944 found_reverse_match = 0;
4945 continue;
4946 }
c0f3af97 4947
5614d22c
JB		 4948 /* Check if vector and VEX operands are valid. */
4949 if (check_VecOperands (t) || VEX_check_operands (t))
4950 {
4951 specific_error = i.error;
4952 continue;
4953 }
a683cc34 4954
29b0f896
AM		 4955 /* We've found a match; break out of loop. */
4956 break;
4957 }
4958
4959 if (t == current_templates->end)
4960 {
4961 /* We found no match. */
a65babc9 4962 const char *err_msg;
5614d22c 4963 switch (specific_error ? specific_error : i.error)
a65babc9
L		 4964 {
4965 default:
4966 abort ();
86e026a4 4967 case operand_size_mismatch:
a65babc9
L		 4968 err_msg = _("operand size mismatch");
4969 break;
4970 case operand_type_mismatch:
4971 err_msg = _("operand type mismatch");
4972 break;
4973 case register_type_mismatch:
4974 err_msg = _("register type mismatch");
4975 break;
4976 case number_of_operands_mismatch:
4977 err_msg = _("number of operands mismatch");
4978 break;
4979 case invalid_instruction_suffix:
4980 err_msg = _("invalid instruction suffix");
4981 break;
4982 case bad_imm4:
4a2608e3 4983 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 4984 break;
4985 case old_gcc_only:
4986 err_msg = _("only supported with old gcc");
4987 break;
4988 case unsupported_with_intel_mnemonic:
4989 err_msg = _("unsupported with Intel mnemonic");
4990 break;
4991 case unsupported_syntax:
4992 err_msg = _("unsupported syntax");
4993 break;
4994 case unsupported:
35262a23 4995 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 4996 current_templates->start->name);
4997 return NULL;
6c30d220
L		 4998 case invalid_vsib_address:
4999 err_msg = _("invalid VSIB address");
5000 break;
7bab8ab5
JB		 5001 case invalid_vector_register_set:
5002 err_msg = _("mask, index, and destination registers must be distinct");
5003 break;
6c30d220
L		 5004 case unsupported_vector_index_register:
5005 err_msg = _("unsupported vector index register");
5006 break;
43234a1e
L		 5007 case unsupported_broadcast:
5008 err_msg = _("unsupported broadcast");
5009 break;
5010 case broadcast_not_on_src_operand:
5011 err_msg = _("broadcast not on source memory operand");
5012 break;
5013 case broadcast_needed:
5014 err_msg = _("broadcast is needed for operand of such type");
5015 break;
5016 case unsupported_masking:
5017 err_msg = _("unsupported masking");
5018 break;
5019 case mask_not_on_destination:
5020 err_msg = _("mask not on destination operand");
5021 break;
5022 case no_default_mask:
5023 err_msg = _("default mask isn't allowed");
5024 break;
5025 case unsupported_rc_sae:
5026 err_msg = _("unsupported static rounding/sae");
5027 break;
5028 case rc_sae_operand_not_last_imm:
5029 if (intel_syntax)
5030 err_msg = _("RC/SAE operand must precede immediate operands");
5031 else
5032 err_msg = _("RC/SAE operand must follow immediate operands");
5033 break;
5034 case invalid_register_operand:
5035 err_msg = _("invalid register operand");
5036 break;
a65babc9
L		 5037 }
5038 as_bad (_("%s for `%s'"), err_msg,
891edac4 5039 current_templates->start->name);
fa99fab2 5040 return NULL;
29b0f896 5041 }
252b5132 5042
29b0f896
AM		 5043 if (!quiet_warnings)
5044 {
5045 if (!intel_syntax
40fb9820
L		 5046 && (i.types[0].bitfield.jumpabsolute
5047 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5048 {
5049 as_warn (_("indirect %s without `*'"), t->name);
5050 }
5051
40fb9820
L		 5052 if (t->opcode_modifier.isprefix
5053 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5054 {
5055 /* Warn them that a data or address size prefix doesn't
5056 affect assembly of the next line of code. */
5057 as_warn (_("stand-alone `%s' prefix"), t->name);
5058 }
5059 }
5060
5061 /* Copy the template we found. */
5062 i.tm = *t;
539e75ad
L		 5063
5064 if (addr_prefix_disp != -1)
5065 i.tm.operand_types[addr_prefix_disp]
5066 = operand_types[addr_prefix_disp];
5067
29b0f896
AM		 5068 if (found_reverse_match)
5069 {
5070 /* If we found a reverse match we must alter the opcode
5071 direction bit. found_reverse_match holds bits to change
5072 (different for int & float insns). */
5073
5074 i.tm.base_opcode ^= found_reverse_match;
5075
539e75ad
L		 5076 i.tm.operand_types[0] = operand_types[1];
5077 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5078 }
5079
fa99fab2 5080 return t;
29b0f896
AM		 5081}
5082
5083static int
e3bb37b5 5084check_string (void)
29b0f896 5085{
40fb9820
L		 5086 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5087 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5088 {
5089 if (i.seg[0] != NULL && i.seg[0] != &es)
5090 {
a87af027 5091 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5092 i.tm.name,
a87af027
JB		 5093 mem_op + 1,
5094 register_prefix);
29b0f896
AM		 5095 return 0;
5096 }
5097 /* There's only ever one segment override allowed per instruction.
5098 This instruction possibly has a legal segment override on the
5099 second operand, so copy the segment to where non-string
5100 instructions store it, allowing common code. */
5101 i.seg[0] = i.seg[1];
5102 }
40fb9820 5103 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5104 {
5105 if (i.seg[1] != NULL && i.seg[1] != &es)
5106 {
a87af027 5107 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5108 i.tm.name,
a87af027
JB		 5109 mem_op + 2,
5110 register_prefix);
29b0f896
AM		 5111 return 0;
5112 }
5113 }
5114 return 1;
5115}
5116
5117static int
543613e9 5118process_suffix (void)
29b0f896
AM		 5119{
5120 /* If matched instruction specifies an explicit instruction mnemonic
5121 suffix, use it. */
40fb9820
L		 5122 if (i.tm.opcode_modifier.size16)
5123 i.suffix = WORD_MNEM_SUFFIX;
5124 else if (i.tm.opcode_modifier.size32)
5125 i.suffix = LONG_MNEM_SUFFIX;
5126 else if (i.tm.opcode_modifier.size64)
5127 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5128 else if (i.reg_operands)
5129 {
5130 /* If there's no instruction mnemonic suffix we try to invent one
5131 based on register operands. */
5132 if (!i.suffix)
5133 {
5134 /* We take i.suffix from the last register operand specified,
5135 Destination register type is more significant than source
381d071f
L		 5136 register type. crc32 in SSE4.2 prefers source register
5137 type. */
5138 if (i.tm.base_opcode == 0xf20f38f1)
5139 {
40fb9820
L		 5140 if (i.types[0].bitfield.reg16)
5141 i.suffix = WORD_MNEM_SUFFIX;
5142 else if (i.types[0].bitfield.reg32)
5143 i.suffix = LONG_MNEM_SUFFIX;
5144 else if (i.types[0].bitfield.reg64)
5145 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5146 }
9344ff29 5147 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5148 {
40fb9820 5149 if (i.types[0].bitfield.reg8)
20592a94
L		 5150 i.suffix = BYTE_MNEM_SUFFIX;
5151 }
381d071f
L		 5152
5153 if (!i.suffix)
5154 {
5155 int op;
5156
20592a94
L		 5157 if (i.tm.base_opcode == 0xf20f38f1
5158 || i.tm.base_opcode == 0xf20f38f0)
5159 {
5160 /* We have to know the operand size for crc32. */
5161 as_bad (_("ambiguous memory operand size for `%s`"),
5162 i.tm.name);
5163 return 0;
5164 }
5165
381d071f 5166 for (op = i.operands; --op >= 0;)
40fb9820 5167 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5168 {
40fb9820
L		 5169 if (i.types[op].bitfield.reg8)
5170 {
5171 i.suffix = BYTE_MNEM_SUFFIX;
5172 break;
5173 }
5174 else if (i.types[op].bitfield.reg16)
5175 {
5176 i.suffix = WORD_MNEM_SUFFIX;
5177 break;
5178 }
5179 else if (i.types[op].bitfield.reg32)
5180 {
5181 i.suffix = LONG_MNEM_SUFFIX;
5182 break;
5183 }
5184 else if (i.types[op].bitfield.reg64)
5185 {
5186 i.suffix = QWORD_MNEM_SUFFIX;
5187 break;
5188 }
381d071f
L		 5189 }
5190 }
29b0f896
AM		 5191 }
5192 else if (i.suffix == BYTE_MNEM_SUFFIX)
5193 {
2eb952a4
L		 5194 if (intel_syntax
5195 && i.tm.opcode_modifier.ignoresize
5196 && i.tm.opcode_modifier.no_bsuf)
5197 i.suffix = 0;
5198 else if (!check_byte_reg ())
29b0f896
AM		 5199 return 0;
5200 }
5201 else if (i.suffix == LONG_MNEM_SUFFIX)
5202 {
2eb952a4
L		 5203 if (intel_syntax
5204 && i.tm.opcode_modifier.ignoresize
5205 && i.tm.opcode_modifier.no_lsuf)
5206 i.suffix = 0;
5207 else if (!check_long_reg ())
29b0f896
AM		 5208 return 0;
5209 }
5210 else if (i.suffix == QWORD_MNEM_SUFFIX)
5211 {
955e1e6a
L		 5212 if (intel_syntax
5213 && i.tm.opcode_modifier.ignoresize
5214 && i.tm.opcode_modifier.no_qsuf)
5215 i.suffix = 0;
5216 else if (!check_qword_reg ())
29b0f896
AM		 5217 return 0;
5218 }
5219 else if (i.suffix == WORD_MNEM_SUFFIX)
5220 {
2eb952a4
L		 5221 if (intel_syntax
5222 && i.tm.opcode_modifier.ignoresize
5223 && i.tm.opcode_modifier.no_wsuf)
5224 i.suffix = 0;
5225 else if (!check_word_reg ())
29b0f896
AM		 5226 return 0;
5227 }
c0f3af97 5228 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5229 || i.suffix == YMMWORD_MNEM_SUFFIX
5230 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5231 {
43234a1e 5232 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5233 should check if it is a valid suffix. */
5234 }
40fb9820 5235 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5236 /* Do nothing if the instruction is going to ignore the prefix. */
5237 ;
5238 else
5239 abort ();
5240 }
40fb9820 5241 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5242 && !i.suffix
5243 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5244 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5245 {
5246 i.suffix = stackop_size;
5247 }
9306ca4a
JB		 5248 else if (intel_syntax
5249 && !i.suffix
40fb9820
L		 5250 && (i.tm.operand_types[0].bitfield.jumpabsolute
5251 || i.tm.opcode_modifier.jumpbyte
5252 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5253 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5254 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5255 {
5256 switch (flag_code)
5257 {
5258 case CODE_64BIT:
40fb9820 5259 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5260 {
5261 i.suffix = QWORD_MNEM_SUFFIX;
5262 break;
5263 }
5264 case CODE_32BIT:
40fb9820 5265 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5266 i.suffix = LONG_MNEM_SUFFIX;
5267 break;
5268 case CODE_16BIT:
40fb9820 5269 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5270 i.suffix = WORD_MNEM_SUFFIX;
5271 break;
5272 }
5273 }
252b5132 5274
9306ca4a 5275 if (!i.suffix)
29b0f896 5276 {
9306ca4a
JB		 5277 if (!intel_syntax)
5278 {
40fb9820 5279 if (i.tm.opcode_modifier.w)
9306ca4a 5280 {
4eed87de
AM		 5281 as_bad (_("no instruction mnemonic suffix given and "
5282 "no register operands; can't size instruction"));
9306ca4a
JB		 5283 return 0;
5284 }
5285 }
5286 else
5287 {
40fb9820 5288 unsigned int suffixes;
7ab9ffdd 5289
40fb9820
L		 5290 suffixes = !i.tm.opcode_modifier.no_bsuf;
5291 if (!i.tm.opcode_modifier.no_wsuf)
5292 suffixes |= 1 << 1;
5293 if (!i.tm.opcode_modifier.no_lsuf)
5294 suffixes |= 1 << 2;
fc4adea1 5295 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5296 suffixes |= 1 << 3;
5297 if (!i.tm.opcode_modifier.no_ssuf)
5298 suffixes |= 1 << 4;
5299 if (!i.tm.opcode_modifier.no_qsuf)
5300 suffixes |= 1 << 5;
5301
5302 /* There are more than suffix matches. */
5303 if (i.tm.opcode_modifier.w
9306ca4a 5304 || ((suffixes & (suffixes - 1))
40fb9820
L		 5305 && !i.tm.opcode_modifier.defaultsize
5306 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5307 {
5308 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5309 return 0;
5310 }
5311 }
29b0f896 5312 }
252b5132 5313
9306ca4a
JB		 5314 /* Change the opcode based on the operand size given by i.suffix;
5315 We don't need to change things for byte insns. */
5316
582d5edd
L		 5317 if (i.suffix
5318 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5319 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5320 && i.suffix != YMMWORD_MNEM_SUFFIX
5321 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5322 {
5323 /* It's not a byte, select word/dword operation. */
40fb9820 5324 if (i.tm.opcode_modifier.w)
29b0f896 5325 {
40fb9820 5326 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5327 i.tm.base_opcode |= 8;
5328 else
5329 i.tm.base_opcode |= 1;
5330 }
0f3f3d8b 5331
29b0f896
AM		 5332 /* Now select between word & dword operations via the operand
5333 size prefix, except for instructions that will ignore this
5334 prefix anyway. */
ca61edf2 5335 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5336 {
ca61edf2
L		 5337 /* The address size override prefix changes the size of the
5338 first operand. */
40fb9820
L		 5339 if ((flag_code == CODE_32BIT
5340 && i.op->regs[0].reg_type.bitfield.reg16)
5341 || (flag_code != CODE_32BIT
5342 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5343 if (!add_prefix (ADDR_PREFIX_OPCODE))
5344 return 0;
5345 }
5346 else if (i.suffix != QWORD_MNEM_SUFFIX
5347 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5348 && !i.tm.opcode_modifier.ignoresize
5349 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5350 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5351 || (flag_code == CODE_64BIT
40fb9820 5352 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5353 {
5354 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5355
40fb9820 5356 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5357 prefix = ADDR_PREFIX_OPCODE;
252b5132 5358
29b0f896
AM		 5359 if (!add_prefix (prefix))
5360 return 0;
24eab124 5361 }
252b5132 5362
29b0f896
AM		 5363 /* Set mode64 for an operand. */
5364 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5365 && flag_code == CODE_64BIT
40fb9820 5366 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5367 {
5368 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5369 need rex64. cmpxchg8b is also a special case. */
5370 if (! (i.operands == 2
5371 && i.tm.base_opcode == 0x90
5372 && i.tm.extension_opcode == None
0dfbf9d7
L		 5373 && operand_type_equal (&i.types [0], &acc64)
5374 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5375 && ! (i.operands == 1
5376 && i.tm.base_opcode == 0xfc7
5377 && i.tm.extension_opcode == 1
40fb9820
L		 5378 && !operand_type_check (i.types [0], reg)
5379 && operand_type_check (i.types [0], anymem)))
f6bee062 5380 i.rex |= REX_W;
46e883c5 5381 }
3e73aa7c 5382
29b0f896
AM		 5383 /* Size floating point instruction. */
5384 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5385 if (i.tm.opcode_modifier.floatmf)
543613e9 5386 i.tm.base_opcode ^= 4;
29b0f896 5387 }
7ecd2f8b 5388
29b0f896
AM		 5389 return 1;
5390}
3e73aa7c 5391
29b0f896 5392static int
543613e9 5393check_byte_reg (void)
29b0f896
AM		 5394{
5395 int op;
543613e9 5396
29b0f896
AM		 5397 for (op = i.operands; --op >= 0;)
5398 {
5399 /* If this is an eight bit register, it's OK. If it's the 16 or
5400 32 bit version of an eight bit register, we will just use the
5401 low portion, and that's OK too. */
40fb9820 5402 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5403 continue;
5404
5a819eb9
JB		 5405 /* I/O port address operands are OK too. */
5406 if (i.tm.operand_types[op].bitfield.inoutportreg)
5407 continue;
5408
9344ff29
L		 5409 /* crc32 doesn't generate this warning. */
5410 if (i.tm.base_opcode == 0xf20f38f0)
5411 continue;
5412
40fb9820
L		 5413 if ((i.types[op].bitfield.reg16
5414 || i.types[op].bitfield.reg32
5415 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5416 && i.op[op].regs->reg_num < 4
5417 /* Prohibit these changes in 64bit mode, since the lowering
5418 would be more complicated. */
5419 && flag_code != CODE_64BIT)
29b0f896 5420 {
29b0f896 5421#if REGISTER_WARNINGS
5a819eb9 5422 if (!quiet_warnings)
a540244d
L		 5423 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5424 register_prefix,
40fb9820 5425 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5426 ? REGNAM_AL - REGNAM_AX
5427 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5428 register_prefix,
29b0f896
AM		 5429 i.op[op].regs->reg_name,
5430 i.suffix);
5431#endif
5432 continue;
5433 }
5434 /* Any other register is bad. */
40fb9820
L		 5435 if (i.types[op].bitfield.reg16
5436 || i.types[op].bitfield.reg32
5437 || i.types[op].bitfield.reg64
5438 || i.types[op].bitfield.regmmx
5439 || i.types[op].bitfield.regxmm
c0f3af97 5440 || i.types[op].bitfield.regymm
43234a1e 5441 || i.types[op].bitfield.regzmm
40fb9820
L		 5442 || i.types[op].bitfield.sreg2
5443 || i.types[op].bitfield.sreg3
5444 || i.types[op].bitfield.control
5445 || i.types[op].bitfield.debug
5446 || i.types[op].bitfield.test
5447 || i.types[op].bitfield.floatreg
5448 || i.types[op].bitfield.floatacc)
29b0f896 5449 {
a540244d
L		 5450 as_bad (_("`%s%s' not allowed with `%s%c'"),
5451 register_prefix,
29b0f896
AM		 5452 i.op[op].regs->reg_name,
5453 i.tm.name,
5454 i.suffix);
5455 return 0;
5456 }
5457 }
5458 return 1;
5459}
5460
5461static int
e3bb37b5 5462check_long_reg (void)
29b0f896
AM		 5463{
5464 int op;
5465
5466 for (op = i.operands; --op >= 0;)
5467 /* Reject eight bit registers, except where the template requires
5468 them. (eg. movzb) */
40fb9820
L		 5469 if (i.types[op].bitfield.reg8
5470 && (i.tm.operand_types[op].bitfield.reg16
5471 || i.tm.operand_types[op].bitfield.reg32
5472 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5473 {
a540244d
L		 5474 as_bad (_("`%s%s' not allowed with `%s%c'"),
5475 register_prefix,
29b0f896
AM		 5476 i.op[op].regs->reg_name,
5477 i.tm.name,
5478 i.suffix);
5479 return 0;
5480 }
e4630f71 5481 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5482 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5483 && i.types[op].bitfield.reg16
5484 && (i.tm.operand_types[op].bitfield.reg32
5485 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5486 {
5487 /* Prohibit these changes in the 64bit mode, since the
5488 lowering is more complicated. */
5489 if (flag_code == CODE_64BIT)
252b5132 5490 {
2b5d6a91 5491 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5492 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5493 i.suffix);
5494 return 0;
252b5132 5495 }
29b0f896 5496#if REGISTER_WARNINGS
cecf1424
JB		 5497 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5498 register_prefix,
5499 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5500 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5501#endif
252b5132 5502 }
e4630f71 5503 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5504 else if (i.types[op].bitfield.reg64
5505 && (i.tm.operand_types[op].bitfield.reg32
5506 || i.tm.operand_types[op].bitfield.acc))
252b5132 5507 {
34828aad 5508 if (intel_syntax
ca61edf2 5509 && i.tm.opcode_modifier.toqword
40fb9820 5510 && !i.types[0].bitfield.regxmm)
34828aad 5511 {
ca61edf2 5512 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5513 i.suffix = QWORD_MNEM_SUFFIX;
5514 }
5515 else
5516 {
2b5d6a91 5517 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5518 register_prefix, i.op[op].regs->reg_name,
5519 i.suffix);
5520 return 0;
5521 }
29b0f896
AM		 5522 }
5523 return 1;
5524}
252b5132 5525
29b0f896 5526static int
e3bb37b5 5527check_qword_reg (void)
29b0f896
AM		 5528{
5529 int op;
252b5132 5530
29b0f896
AM		 5531 for (op = i.operands; --op >= 0; )
5532 /* Reject eight bit registers, except where the template requires
5533 them. (eg. movzb) */
40fb9820
L		 5534 if (i.types[op].bitfield.reg8
5535 && (i.tm.operand_types[op].bitfield.reg16
5536 || i.tm.operand_types[op].bitfield.reg32
5537 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5538 {
a540244d
L		 5539 as_bad (_("`%s%s' not allowed with `%s%c'"),
5540 register_prefix,
29b0f896
AM		 5541 i.op[op].regs->reg_name,
5542 i.tm.name,
5543 i.suffix);
5544 return 0;
5545 }
e4630f71 5546 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5547 else if ((i.types[op].bitfield.reg16
5548 || i.types[op].bitfield.reg32)
5549 && (i.tm.operand_types[op].bitfield.reg32
5550 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5551 {
5552 /* Prohibit these changes in the 64bit mode, since the
5553 lowering is more complicated. */
34828aad 5554 if (intel_syntax
ca61edf2 5555 && i.tm.opcode_modifier.todword
40fb9820 5556 && !i.types[0].bitfield.regxmm)
34828aad 5557 {
ca61edf2 5558 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5559 i.suffix = LONG_MNEM_SUFFIX;
5560 }
5561 else
5562 {
2b5d6a91 5563 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5564 register_prefix, i.op[op].regs->reg_name,
5565 i.suffix);
5566 return 0;
5567 }
252b5132 5568 }
29b0f896
AM		 5569 return 1;
5570}
252b5132 5571
29b0f896 5572static int
e3bb37b5 5573check_word_reg (void)
29b0f896
AM		 5574{
5575 int op;
5576 for (op = i.operands; --op >= 0;)
5577 /* Reject eight bit registers, except where the template requires
5578 them. (eg. movzb) */
40fb9820
L		 5579 if (i.types[op].bitfield.reg8
5580 && (i.tm.operand_types[op].bitfield.reg16
5581 || i.tm.operand_types[op].bitfield.reg32
5582 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5583 {
a540244d
L		 5584 as_bad (_("`%s%s' not allowed with `%s%c'"),
5585 register_prefix,
29b0f896
AM		 5586 i.op[op].regs->reg_name,
5587 i.tm.name,
5588 i.suffix);
5589 return 0;
5590 }
e4630f71 5591 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5592 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5593 && (i.types[op].bitfield.reg32
5594 || i.types[op].bitfield.reg64)
40fb9820
L		 5595 && (i.tm.operand_types[op].bitfield.reg16
5596 || i.tm.operand_types[op].bitfield.acc))
252b5132 5597 {
29b0f896
AM		 5598 /* Prohibit these changes in the 64bit mode, since the
5599 lowering is more complicated. */
5600 if (flag_code == CODE_64BIT)
252b5132 5601 {
2b5d6a91 5602 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5603 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5604 i.suffix);
5605 return 0;
252b5132 5606 }
29b0f896 5607#if REGISTER_WARNINGS
cecf1424
JB		 5608 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5609 register_prefix,
5610 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5611 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5612#endif
5613 }
5614 return 1;
5615}
252b5132 5616
29b0f896 5617static int
40fb9820 5618update_imm (unsigned int j)
29b0f896 5619{
bc0844ae 5620 i386_operand_type overlap = i.types[j];
40fb9820
L		 5621 if ((overlap.bitfield.imm8
5622 || overlap.bitfield.imm8s
5623 || overlap.bitfield.imm16
5624 || overlap.bitfield.imm32
5625 || overlap.bitfield.imm32s
5626 || overlap.bitfield.imm64)
0dfbf9d7
L		 5627 && !operand_type_equal (&overlap, &imm8)
5628 && !operand_type_equal (&overlap, &imm8s)
5629 && !operand_type_equal (&overlap, &imm16)
5630 && !operand_type_equal (&overlap, &imm32)
5631 && !operand_type_equal (&overlap, &imm32s)
5632 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5633 {
5634 if (i.suffix)
5635 {
40fb9820
L		 5636 i386_operand_type temp;
5637
0dfbf9d7 5638 operand_type_set (&temp, 0);
7ab9ffdd 5639 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5640 {
5641 temp.bitfield.imm8 = overlap.bitfield.imm8;
5642 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5643 }
5644 else if (i.suffix == WORD_MNEM_SUFFIX)
5645 temp.bitfield.imm16 = overlap.bitfield.imm16;
5646 else if (i.suffix == QWORD_MNEM_SUFFIX)
5647 {
5648 temp.bitfield.imm64 = overlap.bitfield.imm64;
5649 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5650 }
5651 else
5652 temp.bitfield.imm32 = overlap.bitfield.imm32;
5653 overlap = temp;
29b0f896 5654 }
0dfbf9d7
L		 5655 else if (operand_type_equal (&overlap, &imm16_32_32s)
5656 || operand_type_equal (&overlap, &imm16_32)
5657 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5658 {
40fb9820 5659 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5660 overlap = imm16;
40fb9820 5661 else
65da13b5 5662 overlap = imm32s;
29b0f896 5663 }
0dfbf9d7
L		 5664 if (!operand_type_equal (&overlap, &imm8)
5665 && !operand_type_equal (&overlap, &imm8s)
5666 && !operand_type_equal (&overlap, &imm16)
5667 && !operand_type_equal (&overlap, &imm32)
5668 && !operand_type_equal (&overlap, &imm32s)
5669 && !operand_type_equal (&overlap, &imm64))
29b0f896 5670 {
4eed87de
AM		 5671 as_bad (_("no instruction mnemonic suffix given; "
5672 "can't determine immediate size"));
29b0f896
AM		 5673 return 0;
5674 }
5675 }
40fb9820 5676 i.types[j] = overlap;
29b0f896 5677
40fb9820
L		 5678 return 1;
5679}
5680
5681static int
5682finalize_imm (void)
5683{
bc0844ae 5684 unsigned int j, n;
29b0f896 5685
bc0844ae
L		 5686 /* Update the first 2 immediate operands. */
5687 n = i.operands > 2 ? 2 : i.operands;
5688 if (n)
5689 {
5690 for (j = 0; j < n; j++)
5691 if (update_imm (j) == 0)
5692 return 0;
40fb9820 5693
bc0844ae
L		 5694 /* The 3rd operand can't be immediate operand. */
5695 gas_assert (operand_type_check (i.types[2], imm) == 0);
5696 }
29b0f896
AM		 5697
5698 return 1;
5699}
5700
c0f3af97
L		 5701static int
5702bad_implicit_operand (int xmm)
5703{
91d6fa6a
NC		 5704 const char *ireg = xmm ? "xmm0" : "ymm0";
5705
c0f3af97
L		 5706 if (intel_syntax)
5707 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5708 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5709 else
5710 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5711 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5712 return 0;
5713}
5714
29b0f896 5715static int
e3bb37b5 5716process_operands (void)
29b0f896
AM		 5717{
5718 /* Default segment register this instruction will use for memory
5719 accesses. 0 means unknown. This is only for optimizing out
5720 unnecessary segment overrides. */
5721 const seg_entry *default_seg = 0;
5722
2426c15f 5723 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5724 {
91d6fa6a
NC		 5725 unsigned int dupl = i.operands;
5726 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5727 unsigned int j;
5728
c0f3af97 5729 /* The destination must be an xmm register. */
9c2799c2 5730 gas_assert (i.reg_operands
91d6fa6a 5731 && MAX_OPERANDS > dupl
7ab9ffdd 5732 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5733
5734 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5735 {
c0f3af97 5736 /* The first operand is implicit and must be xmm0. */
9c2799c2 5737 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5738 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5739 return bad_implicit_operand (1);
5740
8cd7925b 5741 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5742 {
5743 /* Keep xmm0 for instructions with VEX prefix and 3
5744 sources. */
5745 goto duplicate;
5746 }
e2ec9d29 5747 else
c0f3af97
L		 5748 {
5749 /* We remove the first xmm0 and keep the number of
5750 operands unchanged, which in fact duplicates the
5751 destination. */
5752 for (j = 1; j < i.operands; j++)
5753 {
5754 i.op[j - 1] = i.op[j];
5755 i.types[j - 1] = i.types[j];
5756 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5757 }
5758 }
5759 }
5760 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5761 {
91d6fa6a 5762 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5763 && (i.tm.opcode_modifier.vexsources
5764 == VEX3SOURCES));
c0f3af97
L		 5765
5766 /* Add the implicit xmm0 for instructions with VEX prefix
5767 and 3 sources. */
5768 for (j = i.operands; j > 0; j--)
5769 {
5770 i.op[j] = i.op[j - 1];
5771 i.types[j] = i.types[j - 1];
5772 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5773 }
5774 i.op[0].regs
5775 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5776 i.types[0] = regxmm;
c0f3af97
L		 5777 i.tm.operand_types[0] = regxmm;
5778
5779 i.operands += 2;
5780 i.reg_operands += 2;
5781 i.tm.operands += 2;
5782
91d6fa6a 5783 dupl++;
c0f3af97 5784 dest++;
91d6fa6a
NC		 5785 i.op[dupl] = i.op[dest];
5786 i.types[dupl] = i.types[dest];
5787 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5788 }
c0f3af97
L		 5789 else
5790 {
5791duplicate:
5792 i.operands++;
5793 i.reg_operands++;
5794 i.tm.operands++;
5795
91d6fa6a
NC		 5796 i.op[dupl] = i.op[dest];
5797 i.types[dupl] = i.types[dest];
5798 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5799 }
5800
5801 if (i.tm.opcode_modifier.immext)
5802 process_immext ();
5803 }
5804 else if (i.tm.opcode_modifier.firstxmm0)
5805 {
5806 unsigned int j;
5807
43234a1e 5808 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5809 gas_assert (i.reg_operands
7ab9ffdd 5810 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5811 || operand_type_equal (&i.types[0], &regymm)
5812 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5813 if (register_number (i.op[0].regs) != 0)
c0f3af97 5814 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5815
5816 for (j = 1; j < i.operands; j++)
5817 {
5818 i.op[j - 1] = i.op[j];
5819 i.types[j - 1] = i.types[j];
5820
5821 /* We need to adjust fields in i.tm since they are used by
5822 build_modrm_byte. */
5823 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5824 }
5825
e2ec9d29
L		 5826 i.operands--;
5827 i.reg_operands--;
e2ec9d29
L		 5828 i.tm.operands--;
5829 }
5830 else if (i.tm.opcode_modifier.regkludge)
5831 {
5832 /* The imul $imm, %reg instruction is converted into
5833 imul $imm, %reg, %reg, and the clr %reg instruction
5834 is converted into xor %reg, %reg. */
5835
5836 unsigned int first_reg_op;
5837
5838 if (operand_type_check (i.types[0], reg))
5839 first_reg_op = 0;
5840 else
5841 first_reg_op = 1;
5842 /* Pretend we saw the extra register operand. */
9c2799c2 5843 gas_assert (i.reg_operands == 1
7ab9ffdd 5844 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5845 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5846 i.types[first_reg_op + 1] = i.types[first_reg_op];
5847 i.operands++;
5848 i.reg_operands++;
29b0f896
AM		 5849 }
5850
40fb9820 5851 if (i.tm.opcode_modifier.shortform)
29b0f896 5852 {
40fb9820
L		 5853 if (i.types[0].bitfield.sreg2
5854 || i.types[0].bitfield.sreg3)
29b0f896 5855 {
4eed87de
AM		 5856 if (i.tm.base_opcode == POP_SEG_SHORT
5857 && i.op[0].regs->reg_num == 1)
29b0f896 5858 {
a87af027 5859 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5860 return 0;
29b0f896 5861 }
4eed87de
AM		 5862 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5863 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5864 i.rex |= REX_B;
4eed87de
AM		 5865 }
5866 else
5867 {
7ab9ffdd 5868 /* The register or float register operand is in operand
85f10a01 5869 0 or 1. */
40fb9820 5870 unsigned int op;
7ab9ffdd
L		 5871
5872 if (i.types[0].bitfield.floatreg
5873 || operand_type_check (i.types[0], reg))
5874 op = 0;
5875 else
5876 op = 1;
4eed87de
AM		 5877 /* Register goes in low 3 bits of opcode. */
5878 i.tm.base_opcode |= i.op[op].regs->reg_num;
5879 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5880 i.rex |= REX_B;
40fb9820 5881 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5882 {
4eed87de
AM		 5883 /* Warn about some common errors, but press on regardless.
5884 The first case can be generated by gcc (<= 2.8.1). */
5885 if (i.operands == 2)
5886 {
5887 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5888 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5889 register_prefix, i.op[!intel_syntax].regs->reg_name,
5890 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5891 }
5892 else
5893 {
5894 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5895 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5896 register_prefix, i.op[0].regs->reg_name);
4eed87de 5897 }
29b0f896
AM		 5898 }
5899 }
5900 }
40fb9820 5901 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5902 {
5903 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5904 must be put into the modrm byte). Now, we make the modrm and
5905 index base bytes based on all the info we've collected. */
29b0f896
AM		 5906
5907 default_seg = build_modrm_byte ();
5908 }
8a2ed489 5909 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5910 {
5911 default_seg = &ds;
5912 }
40fb9820 5913 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5914 {
5915 /* For the string instructions that allow a segment override
5916 on one of their operands, the default segment is ds. */
5917 default_seg = &ds;
5918 }
5919
75178d9d
L		 5920 if (i.tm.base_opcode == 0x8d /* lea */
5921 && i.seg[0]
5922 && !quiet_warnings)
30123838 5923 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5924
5925 /* If a segment was explicitly specified, and the specified segment
5926 is not the default, use an opcode prefix to select it. If we
5927 never figured out what the default segment is, then default_seg
5928 will be zero at this point, and the specified segment prefix will
5929 always be used. */
29b0f896
AM		 5930 if ((i.seg[0]) && (i.seg[0] != default_seg))
5931 {
5932 if (!add_prefix (i.seg[0]->seg_prefix))
5933 return 0;
5934 }
5935 return 1;
5936}
5937
5938static const seg_entry *
e3bb37b5 5939build_modrm_byte (void)
29b0f896
AM		 5940{
5941 const seg_entry *default_seg = 0;
c0f3af97 5942 unsigned int source, dest;
8cd7925b 5943 int vex_3_sources;
c0f3af97
L		 5944
5945 /* The first operand of instructions with VEX prefix and 3 sources
5946 must be VEX_Imm4. */
8cd7925b 5947 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5948 if (vex_3_sources)
5949 {
91d6fa6a 5950 unsigned int nds, reg_slot;
4c2c6516 5951 expressionS *exp;
c0f3af97 5952
922d8de8 5953 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5954 && i.tm.opcode_modifier.immext)
5955 {
5956 dest = i.operands - 2;
5957 gas_assert (dest == 3);
5958 }
922d8de8 5959 else
a683cc34 5960 dest = i.operands - 1;
c0f3af97 5961 nds = dest - 1;
922d8de8 5962
a683cc34
SP		 5963 /* There are 2 kinds of instructions:
5964 1. 5 operands: 4 register operands or 3 register operands
5965 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 5966 VexW0 or VexW1. The destination must be either XMM, YMM or
5967 ZMM register.
a683cc34
SP		 5968 2. 4 operands: 4 register operands or 3 register operands
5969 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5970 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5971 || (i.reg_operands == 3 && i.mem_operands == 1))
5972 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5973 && (i.tm.opcode_modifier.veximmext
5974 || (i.imm_operands == 1
5975 && i.types[0].bitfield.vec_imm4
5976 && (i.tm.opcode_modifier.vexw == VEXW0
5977 || i.tm.opcode_modifier.vexw == VEXW1)
5978 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 5979 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
5980 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 5981
5982 if (i.imm_operands == 0)
5983 {
5984 /* When there is no immediate operand, generate an 8bit
5985 immediate operand to encode the first operand. */
5986 exp = &im_expressions[i.imm_operands++];
5987 i.op[i.operands].imms = exp;
5988 i.types[i.operands] = imm8;
5989 i.operands++;
5990 /* If VexW1 is set, the first operand is the source and
5991 the second operand is encoded in the immediate operand. */
5992 if (i.tm.opcode_modifier.vexw == VEXW1)
5993 {
5994 source = 0;
5995 reg_slot = 1;
5996 }
5997 else
5998 {
5999 source = 1;
6000 reg_slot = 0;
6001 }
6002
6003 /* FMA swaps REG and NDS. */
6004 if (i.tm.cpu_flags.bitfield.cpufma)
6005 {
6006 unsigned int tmp;
6007 tmp = reg_slot;
6008 reg_slot = nds;
6009 nds = tmp;
6010 }
6011
24981e7b
L		 6012 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6013 &regxmm)
a683cc34 6014 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6015 &regymm)
6016 || operand_type_equal (&i.tm.operand_types[reg_slot],
6017 &regzmm));
a683cc34 6018 exp->X_op = O_constant;
4c692bc7 6019 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6020 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6021 }
922d8de8 6022 else
a683cc34
SP		 6023 {
6024 unsigned int imm_slot;
6025
6026 if (i.tm.opcode_modifier.vexw == VEXW0)
6027 {
6028 /* If VexW0 is set, the third operand is the source and
6029 the second operand is encoded in the immediate
6030 operand. */
6031 source = 2;
6032 reg_slot = 1;
6033 }
6034 else
6035 {
6036 /* VexW1 is set, the second operand is the source and
6037 the third operand is encoded in the immediate
6038 operand. */
6039 source = 1;
6040 reg_slot = 2;
6041 }
6042
6043 if (i.tm.opcode_modifier.immext)
6044 {
6045 /* When ImmExt is set, the immdiate byte is the last
6046 operand. */
6047 imm_slot = i.operands - 1;
6048 source--;
6049 reg_slot--;
6050 }
6051 else
6052 {
6053 imm_slot = 0;
6054
6055 /* Turn on Imm8 so that output_imm will generate it. */
6056 i.types[imm_slot].bitfield.imm8 = 1;
6057 }
6058
24981e7b
L		 6059 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6060 &regxmm)
6061 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6062 &regymm)
6063 || operand_type_equal (&i.tm.operand_types[reg_slot],
6064 &regzmm));
a683cc34 6065 i.op[imm_slot].imms->X_add_number
4c692bc7 6066 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6067 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6068 }
6069
6070 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6071 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6072 &regymm)
6073 || operand_type_equal (&i.tm.operand_types[nds],
6074 &regzmm));
dae39acc 6075 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6076 }
6077 else
6078 source = dest = 0;
29b0f896
AM		 6079
6080 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6081 implicit registers do not count. If there are 3 register
6082 operands, it must be a instruction with VexNDS. For a
6083 instruction with VexNDD, the destination register is encoded
6084 in VEX prefix. If there are 4 register operands, it must be
6085 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6086 if (i.mem_operands == 0
6087 && ((i.reg_operands == 2
2426c15f 6088 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6089 || (i.reg_operands == 3
2426c15f 6090 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6091 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6092 {
cab737b9
L		 6093 switch (i.operands)
6094 {
6095 case 2:
6096 source = 0;
6097 break;
6098 case 3:
c81128dc
L		 6099 /* When there are 3 operands, one of them may be immediate,
6100 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6101 the first operand must be shift count register (cl) or it
6102 is an instruction with VexNDS. */
9c2799c2 6103 gas_assert (i.imm_operands == 1
7ab9ffdd 6104 || (i.imm_operands == 0
2426c15f 6105 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6106 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6107 if (operand_type_check (i.types[0], imm)
6108 || i.types[0].bitfield.shiftcount)
6109 source = 1;
6110 else
6111 source = 0;
cab737b9
L		 6112 break;
6113 case 4:
368d64cc
L		 6114 /* When there are 4 operands, the first two must be 8bit
6115 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6116 one.
6117
6118 For instructions with VexNDS, if the first operand
6119 an imm8, the source operand is the 2nd one. If the last
6120 operand is imm8, the source operand is the first one. */
9c2799c2 6121 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6122 && i.types[0].bitfield.imm8
6123 && i.types[1].bitfield.imm8)
2426c15f 6124 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6125 && i.imm_operands == 1
6126 && (i.types[0].bitfield.imm8
43234a1e
L		 6127 || i.types[i.operands - 1].bitfield.imm8
6128 || i.rounding)));
9f2670f2
L		 6129 if (i.imm_operands == 2)
6130 source = 2;
6131 else
c0f3af97
L		 6132 {
6133 if (i.types[0].bitfield.imm8)
6134 source = 1;
6135 else
6136 source = 0;
6137 }
c0f3af97
L		 6138 break;
6139 case 5:
43234a1e
L		 6140 if (i.tm.opcode_modifier.evex)
6141 {
6142 /* For EVEX instructions, when there are 5 operands, the
6143 first one must be immediate operand. If the second one
6144 is immediate operand, the source operand is the 3th
6145 one. If the last one is immediate operand, the source
6146 operand is the 2nd one. */
6147 gas_assert (i.imm_operands == 2
6148 && i.tm.opcode_modifier.sae
6149 && operand_type_check (i.types[0], imm));
6150 if (operand_type_check (i.types[1], imm))
6151 source = 2;
6152 else if (operand_type_check (i.types[4], imm))
6153 source = 1;
6154 else
6155 abort ();
6156 }
cab737b9
L		 6157 break;
6158 default:
6159 abort ();
6160 }
6161
c0f3af97
L		 6162 if (!vex_3_sources)
6163 {
6164 dest = source + 1;
6165
43234a1e
L		 6166 /* RC/SAE operand could be between DEST and SRC. That happens
6167 when one operand is GPR and the other one is XMM/YMM/ZMM
6168 register. */
6169 if (i.rounding && i.rounding->operand == (int) dest)
6170 dest++;
6171
2426c15f 6172 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6173 {
43234a1e
L		 6174 /* For instructions with VexNDS, the register-only source
6175 operand must be 32/64bit integer, XMM, YMM or ZMM
6176 register. It is encoded in VEX prefix. We need to
6177 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6178
6179 i386_operand_type op;
6180 unsigned int vvvv;
6181
6182 /* Check register-only source operand when two source
6183 operands are swapped. */
6184 if (!i.tm.operand_types[source].bitfield.baseindex
6185 && i.tm.operand_types[dest].bitfield.baseindex)
6186 {
6187 vvvv = source;
6188 source = dest;
6189 }
6190 else
6191 vvvv = dest;
6192
6193 op = i.tm.operand_types[vvvv];
fa99fab2 6194 op.bitfield.regmem = 0;
c0f3af97 6195 if ((dest + 1) >= i.operands
ac4eb736
AM		 6196 || (!op.bitfield.reg32
6197 && op.bitfield.reg64
f12dc422 6198 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6199 && !operand_type_equal (&op, &regymm)
6200 && !operand_type_equal (&op, &regzmm)
6201 && !operand_type_equal (&op, &regmask)))
c0f3af97 6202 abort ();
f12dc422 6203 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6204 dest++;
6205 }
6206 }
29b0f896
AM		 6207
6208 i.rm.mode = 3;
6209 /* One of the register operands will be encoded in the i.tm.reg
6210 field, the other in the combined i.tm.mode and i.tm.regmem
6211 fields. If no form of this instruction supports a memory
6212 destination operand, then we assume the source operand may
6213 sometimes be a memory operand and so we need to store the
6214 destination in the i.rm.reg field. */
40fb9820
L		 6215 if (!i.tm.operand_types[dest].bitfield.regmem
6216 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6217 {
6218 i.rm.reg = i.op[dest].regs->reg_num;
6219 i.rm.regmem = i.op[source].regs->reg_num;
6220 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6221 i.rex |= REX_R;
43234a1e
L		 6222 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6223 i.vrex |= REX_R;
29b0f896 6224 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6225 i.rex |= REX_B;
43234a1e
L		 6226 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6227 i.vrex |= REX_B;
29b0f896
AM		 6228 }
6229 else
6230 {
6231 i.rm.reg = i.op[source].regs->reg_num;
6232 i.rm.regmem = i.op[dest].regs->reg_num;
6233 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6234 i.rex |= REX_B;
43234a1e
L		 6235 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6236 i.vrex |= REX_B;
29b0f896 6237 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6238 i.rex |= REX_R;
43234a1e
L		 6239 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6240 i.vrex |= REX_R;
29b0f896 6241 }
161a04f6 6242 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6243 {
40fb9820
L		 6244 if (!i.types[0].bitfield.control
6245 && !i.types[1].bitfield.control)
c4a530c5 6246 abort ();
161a04f6 6247 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6248 add_prefix (LOCK_PREFIX_OPCODE);
6249 }
29b0f896
AM		 6250 }
6251 else
6252 { /* If it's not 2 reg operands... */
c0f3af97
L		 6253 unsigned int mem;
6254
29b0f896
AM		 6255 if (i.mem_operands)
6256 {
6257 unsigned int fake_zero_displacement = 0;
99018f42 6258 unsigned int op;
4eed87de 6259
7ab9ffdd
L		 6260 for (op = 0; op < i.operands; op++)
6261 if (operand_type_check (i.types[op], anymem))
6262 break;
7ab9ffdd 6263 gas_assert (op < i.operands);
29b0f896 6264
6c30d220
L		 6265 if (i.tm.opcode_modifier.vecsib)
6266 {
6267 if (i.index_reg->reg_num == RegEiz
6268 || i.index_reg->reg_num == RegRiz)
6269 abort ();
6270
6271 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6272 if (!i.base_reg)
6273 {
6274 i.sib.base = NO_BASE_REGISTER;
6275 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6276 /* No Vec_Disp8 if there is no base. */
6277 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6278 i.types[op].bitfield.disp8 = 0;
6279 i.types[op].bitfield.disp16 = 0;
6280 i.types[op].bitfield.disp64 = 0;
6281 if (flag_code != CODE_64BIT)
6282 {
6283 /* Must be 32 bit */
6284 i.types[op].bitfield.disp32 = 1;
6285 i.types[op].bitfield.disp32s = 0;
6286 }
6287 else
6288 {
6289 i.types[op].bitfield.disp32 = 0;
6290 i.types[op].bitfield.disp32s = 1;
6291 }
6292 }
6293 i.sib.index = i.index_reg->reg_num;
6294 if ((i.index_reg->reg_flags & RegRex) != 0)
6295 i.rex |= REX_X;
43234a1e
L		 6296 if ((i.index_reg->reg_flags & RegVRex) != 0)
6297 i.vrex |= REX_X;
6c30d220
L		 6298 }
6299
29b0f896
AM		 6300 default_seg = &ds;
6301
6302 if (i.base_reg == 0)
6303 {
6304 i.rm.mode = 0;
6305 if (!i.disp_operands)
6c30d220
L		 6306 {
6307 fake_zero_displacement = 1;
6308 /* Instructions with VSIB byte need 32bit displacement
6309 if there is no base register. */
6310 if (i.tm.opcode_modifier.vecsib)
6311 i.types[op].bitfield.disp32 = 1;
6312 }
29b0f896
AM		 6313 if (i.index_reg == 0)
6314 {
6c30d220 6315 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6316 /* Operand is just <disp> */
20f0a1fc 6317 if (flag_code == CODE_64BIT)
29b0f896
AM		 6318 {
6319 /* 64bit mode overwrites the 32bit absolute
6320 addressing by RIP relative addressing and
6321 absolute addressing is encoded by one of the
6322 redundant SIB forms. */
6323 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6324 i.sib.base = NO_BASE_REGISTER;
6325 i.sib.index = NO_INDEX_REGISTER;
fc225355 6326 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6327 ? disp32s : disp32);
20f0a1fc 6328 }
fc225355
L		 6329 else if ((flag_code == CODE_16BIT)
6330 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6331 {
6332 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6333 i.types[op] = disp16;
20f0a1fc
NC		 6334 }
6335 else
6336 {
6337 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6338 i.types[op] = disp32;
29b0f896
AM		 6339 }
6340 }
6c30d220 6341 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6342 {
6c30d220 6343 /* !i.base_reg && i.index_reg */
db51cc60
L		 6344 if (i.index_reg->reg_num == RegEiz
6345 || i.index_reg->reg_num == RegRiz)
6346 i.sib.index = NO_INDEX_REGISTER;
6347 else
6348 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6349 i.sib.base = NO_BASE_REGISTER;
6350 i.sib.scale = i.log2_scale_factor;
6351 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6352 /* No Vec_Disp8 if there is no base. */
6353 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6354 i.types[op].bitfield.disp8 = 0;
6355 i.types[op].bitfield.disp16 = 0;
6356 i.types[op].bitfield.disp64 = 0;
29b0f896 6357 if (flag_code != CODE_64BIT)
40fb9820
L		 6358 {
6359 /* Must be 32 bit */
6360 i.types[op].bitfield.disp32 = 1;
6361 i.types[op].bitfield.disp32s = 0;
6362 }
29b0f896 6363 else
40fb9820
L		 6364 {
6365 i.types[op].bitfield.disp32 = 0;
6366 i.types[op].bitfield.disp32s = 1;
6367 }
29b0f896 6368 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6369 i.rex |= REX_X;
29b0f896
AM		 6370 }
6371 }
6372 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6373 else if (i.base_reg->reg_num == RegRip ||
6374 i.base_reg->reg_num == RegEip)
29b0f896 6375 {
6c30d220 6376 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6377 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6378 i.types[op].bitfield.disp8 = 0;
6379 i.types[op].bitfield.disp16 = 0;
6380 i.types[op].bitfield.disp32 = 0;
6381 i.types[op].bitfield.disp32s = 1;
6382 i.types[op].bitfield.disp64 = 0;
43234a1e 6383 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6384 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6385 if (! i.disp_operands)
6386 fake_zero_displacement = 1;
29b0f896 6387 }
40fb9820 6388 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6389 {
6c30d220 6390 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6391 switch (i.base_reg->reg_num)
6392 {
6393 case 3: /* (%bx) */
6394 if (i.index_reg == 0)
6395 i.rm.regmem = 7;
6396 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6397 i.rm.regmem = i.index_reg->reg_num - 6;
6398 break;
6399 case 5: /* (%bp) */
6400 default_seg = &ss;
6401 if (i.index_reg == 0)
6402 {
6403 i.rm.regmem = 6;
40fb9820 6404 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6405 {
6406 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6407 if (i.tm.operand_types[op].bitfield.vec_disp8)
6408 i.types[op].bitfield.vec_disp8 = 1;
6409 else
6410 i.types[op].bitfield.disp8 = 1;
252b5132 6411 fake_zero_displacement = 1;
29b0f896
AM		 6412 }
6413 }
6414 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6415 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6416 break;
6417 default: /* (%si) -> 4 or (%di) -> 5 */
6418 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6419 }
6420 i.rm.mode = mode_from_disp_size (i.types[op]);
6421 }
6422 else /* i.base_reg and 32/64 bit mode */
6423 {
6424 if (flag_code == CODE_64BIT
40fb9820
L		 6425 && operand_type_check (i.types[op], disp))
6426 {
6427 i386_operand_type temp;
0dfbf9d7 6428 operand_type_set (&temp, 0);
40fb9820 6429 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6430 temp.bitfield.vec_disp8
6431 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6432 i.types[op] = temp;
6433 if (i.prefix[ADDR_PREFIX] == 0)
6434 i.types[op].bitfield.disp32s = 1;
6435 else
6436 i.types[op].bitfield.disp32 = 1;
6437 }
20f0a1fc 6438
6c30d220
L		 6439 if (!i.tm.opcode_modifier.vecsib)
6440 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6441 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6442 i.rex |= REX_B;
29b0f896
AM		 6443 i.sib.base = i.base_reg->reg_num;
6444 /* x86-64 ignores REX prefix bit here to avoid decoder
6445 complications. */
848930b2
JB		 6446 if (!(i.base_reg->reg_flags & RegRex)
6447 && (i.base_reg->reg_num == EBP_REG_NUM
6448 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6449 default_seg = &ss;
848930b2 6450 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6451 {
848930b2 6452 fake_zero_displacement = 1;
43234a1e
L		 6453 if (i.tm.operand_types [op].bitfield.vec_disp8)
6454 i.types[op].bitfield.vec_disp8 = 1;
6455 else
6456 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6457 }
6458 i.sib.scale = i.log2_scale_factor;
6459 if (i.index_reg == 0)
6460 {
6c30d220 6461 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6462 /* <disp>(%esp) becomes two byte modrm with no index
6463 register. We've already stored the code for esp
6464 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6465 Any base register besides %esp will not use the
6466 extra modrm byte. */
6467 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6468 }
6c30d220 6469 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6470 {
db51cc60
L		 6471 if (i.index_reg->reg_num == RegEiz
6472 || i.index_reg->reg_num == RegRiz)
6473 i.sib.index = NO_INDEX_REGISTER;
6474 else
6475 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6476 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6477 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6478 i.rex |= REX_X;
29b0f896 6479 }
67a4f2b7
AO		 6480
6481 if (i.disp_operands
6482 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6483 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6484 i.rm.mode = 0;
6485 else
a501d77e
L		 6486 {
6487 if (!fake_zero_displacement
6488 && !i.disp_operands
6489 && i.disp_encoding)
6490 {
6491 fake_zero_displacement = 1;
6492 if (i.disp_encoding == disp_encoding_8bit)
6493 i.types[op].bitfield.disp8 = 1;
6494 else
6495 i.types[op].bitfield.disp32 = 1;
6496 }
6497 i.rm.mode = mode_from_disp_size (i.types[op]);
6498 }
29b0f896 6499 }
252b5132 6500
29b0f896
AM		 6501 if (fake_zero_displacement)
6502 {
6503 /* Fakes a zero displacement assuming that i.types[op]
6504 holds the correct displacement size. */
6505 expressionS *exp;
6506
9c2799c2 6507 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6508 exp = &disp_expressions[i.disp_operands++];
6509 i.op[op].disps = exp;
6510 exp->X_op = O_constant;
6511 exp->X_add_number = 0;
6512 exp->X_add_symbol = (symbolS *) 0;
6513 exp->X_op_symbol = (symbolS *) 0;
6514 }
c0f3af97
L		 6515
6516 mem = op;
29b0f896 6517 }
c0f3af97
L		 6518 else
6519 mem = ~0;
252b5132 6520
8c43a48b 6521 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6522 {
6523 if (operand_type_check (i.types[0], imm))
6524 i.vex.register_specifier = NULL;
6525 else
6526 {
6527 /* VEX.vvvv encodes one of the sources when the first
6528 operand is not an immediate. */
1ef99a7b 6529 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6530 i.vex.register_specifier = i.op[0].regs;
6531 else
6532 i.vex.register_specifier = i.op[1].regs;
6533 }
6534
6535 /* Destination is a XMM register encoded in the ModRM.reg
6536 and VEX.R bit. */
6537 i.rm.reg = i.op[2].regs->reg_num;
6538 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6539 i.rex |= REX_R;
6540
6541 /* ModRM.rm and VEX.B encodes the other source. */
6542 if (!i.mem_operands)
6543 {
6544 i.rm.mode = 3;
6545
1ef99a7b 6546 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6547 i.rm.regmem = i.op[1].regs->reg_num;
6548 else
6549 i.rm.regmem = i.op[0].regs->reg_num;
6550
6551 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6552 i.rex |= REX_B;
6553 }
6554 }
2426c15f 6555 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6556 {
6557 i.vex.register_specifier = i.op[2].regs;
6558 if (!i.mem_operands)
6559 {
6560 i.rm.mode = 3;
6561 i.rm.regmem = i.op[1].regs->reg_num;
6562 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6563 i.rex |= REX_B;
6564 }
6565 }
29b0f896
AM		 6566 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6567 (if any) based on i.tm.extension_opcode. Again, we must be
6568 careful to make sure that segment/control/debug/test/MMX
6569 registers are coded into the i.rm.reg field. */
f88c9eb0 6570 else if (i.reg_operands)
29b0f896 6571 {
99018f42 6572 unsigned int op;
7ab9ffdd
L		 6573 unsigned int vex_reg = ~0;
6574
6575 for (op = 0; op < i.operands; op++)
6576 if (i.types[op].bitfield.reg8
6577 || i.types[op].bitfield.reg16
6578 || i.types[op].bitfield.reg32
6579 || i.types[op].bitfield.reg64
6580 || i.types[op].bitfield.regmmx
6581 || i.types[op].bitfield.regxmm
6582 || i.types[op].bitfield.regymm
7e8b059b 6583 || i.types[op].bitfield.regbnd
43234a1e
L		 6584 || i.types[op].bitfield.regzmm
6585 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6586 || i.types[op].bitfield.sreg2
6587 || i.types[op].bitfield.sreg3
6588 || i.types[op].bitfield.control
6589 || i.types[op].bitfield.debug
6590 || i.types[op].bitfield.test)
6591 break;
c0209578 6592
7ab9ffdd
L		 6593 if (vex_3_sources)
6594 op = dest;
2426c15f 6595 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6596 {
6597 /* For instructions with VexNDS, the register-only
6598 source operand is encoded in VEX prefix. */
6599 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6600
7ab9ffdd 6601 if (op > mem)
c0f3af97 6602 {
7ab9ffdd
L		 6603 vex_reg = op++;
6604 gas_assert (op < i.operands);
c0f3af97
L		 6605 }
6606 else
c0f3af97 6607 {
f12dc422
L		 6608 /* Check register-only source operand when two source
6609 operands are swapped. */
6610 if (!i.tm.operand_types[op].bitfield.baseindex
6611 && i.tm.operand_types[op + 1].bitfield.baseindex)
6612 {
6613 vex_reg = op;
6614 op += 2;
6615 gas_assert (mem == (vex_reg + 1)
6616 && op < i.operands);
6617 }
6618 else
6619 {
6620 vex_reg = op + 1;
6621 gas_assert (vex_reg < i.operands);
6622 }
c0f3af97 6623 }
7ab9ffdd 6624 }
2426c15f 6625 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6626 {
f12dc422 6627 /* For instructions with VexNDD, the register destination
7ab9ffdd 6628 is encoded in VEX prefix. */
f12dc422
L		 6629 if (i.mem_operands == 0)
6630 {
6631 /* There is no memory operand. */
6632 gas_assert ((op + 2) == i.operands);
6633 vex_reg = op + 1;
6634 }
6635 else
8d63c93e 6636 {
f12dc422
L		 6637 /* There are only 2 operands. */
6638 gas_assert (op < 2 && i.operands == 2);
6639 vex_reg = 1;
6640 }
7ab9ffdd
L		 6641 }
6642 else
6643 gas_assert (op < i.operands);
99018f42 6644
7ab9ffdd
L		 6645 if (vex_reg != (unsigned int) ~0)
6646 {
f12dc422 6647 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6648
f12dc422
L		 6649 if (type->bitfield.reg32 != 1
6650 && type->bitfield.reg64 != 1
6651 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6652 && !operand_type_equal (type, &regymm)
6653 && !operand_type_equal (type, &regzmm)
6654 && !operand_type_equal (type, &regmask))
7ab9ffdd 6655 abort ();
f88c9eb0 6656
7ab9ffdd
L		 6657 i.vex.register_specifier = i.op[vex_reg].regs;
6658 }
6659
1b9f0c97
L		 6660 /* Don't set OP operand twice. */
6661 if (vex_reg != op)
7ab9ffdd 6662 {
1b9f0c97
L		 6663 /* If there is an extension opcode to put here, the
6664 register number must be put into the regmem field. */
6665 if (i.tm.extension_opcode != None)
6666 {
6667 i.rm.regmem = i.op[op].regs->reg_num;
6668 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6669 i.rex |= REX_B;
43234a1e
L		 6670 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6671 i.vrex |= REX_B;
1b9f0c97
L		 6672 }
6673 else
6674 {
6675 i.rm.reg = i.op[op].regs->reg_num;
6676 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6677 i.rex |= REX_R;
43234a1e
L		 6678 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6679 i.vrex |= REX_R;
1b9f0c97 6680 }
7ab9ffdd 6681 }
252b5132 6682
29b0f896
AM		 6683 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6684 must set it to 3 to indicate this is a register operand
6685 in the regmem field. */
6686 if (!i.mem_operands)
6687 i.rm.mode = 3;
6688 }
252b5132 6689
29b0f896 6690 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6691 if (i.tm.extension_opcode != None)
29b0f896
AM		 6692 i.rm.reg = i.tm.extension_opcode;
6693 }
6694 return default_seg;
6695}
252b5132 6696
29b0f896 6697static void
e3bb37b5 6698output_branch (void)
29b0f896
AM		 6699{
6700 char *p;
f8a5c266 6701 int size;
29b0f896
AM		 6702 int code16;
6703 int prefix;
6704 relax_substateT subtype;
6705 symbolS *sym;
6706 offsetT off;
6707
f8a5c266 6708 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6709 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6710
6711 prefix = 0;
6712 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6713 {
29b0f896
AM		 6714 prefix = 1;
6715 i.prefixes -= 1;
6716 code16 ^= CODE16;
252b5132 6717 }
29b0f896
AM		 6718 /* Pentium4 branch hints. */
6719 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6720 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6721 {
29b0f896
AM		 6722 prefix++;
6723 i.prefixes--;
6724 }
6725 if (i.prefix[REX_PREFIX] != 0)
6726 {
6727 prefix++;
6728 i.prefixes--;
2f66722d
AM		 6729 }
6730
7e8b059b
L		 6731 /* BND prefixed jump. */
6732 if (i.prefix[BND_PREFIX] != 0)
6733 {
6734 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6735 i.prefixes -= 1;
6736 }
6737
29b0f896
AM		 6738 if (i.prefixes != 0 && !intel_syntax)
6739 as_warn (_("skipping prefixes on this instruction"));
6740
6741 /* It's always a symbol; End frag & setup for relax.
6742 Make sure there is enough room in this frag for the largest
6743 instruction we may generate in md_convert_frag. This is 2
6744 bytes for the opcode and room for the prefix and largest
6745 displacement. */
6746 frag_grow (prefix + 2 + 4);
6747 /* Prefix and 1 opcode byte go in fr_fix. */
6748 p = frag_more (prefix + 1);
6749 if (i.prefix[DATA_PREFIX] != 0)
6750 *p++ = DATA_PREFIX_OPCODE;
6751 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6752 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6753 *p++ = i.prefix[SEG_PREFIX];
6754 if (i.prefix[REX_PREFIX] != 0)
6755 *p++ = i.prefix[REX_PREFIX];
6756 *p = i.tm.base_opcode;
6757
6758 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6759 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6760 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6761 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6762 else
f8a5c266 6763 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6764 subtype |= code16;
3e73aa7c 6765
29b0f896
AM		 6766 sym = i.op[0].disps->X_add_symbol;
6767 off = i.op[0].disps->X_add_number;
3e73aa7c 6768
29b0f896
AM		 6769 if (i.op[0].disps->X_op != O_constant
6770 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6771 {
29b0f896
AM		 6772 /* Handle complex expressions. */
6773 sym = make_expr_symbol (i.op[0].disps);
6774 off = 0;
6775 }
3e73aa7c 6776
29b0f896
AM		 6777 /* 1 possible extra opcode + 4 byte displacement go in var part.
6778 Pass reloc in fr_var. */
c3320543
L		 6779 frag_var (rs_machine_dependent, 5,
6780 ((!object_64bit
6781 || i.reloc[0] != NO_RELOC
6782 || (i.bnd_prefix == NULL && !add_bnd_prefix))
6783 ? i.reloc[0]
6784 : BFD_RELOC_X86_64_PC32_BND),
6785 subtype, sym, off, p);
29b0f896 6786}
3e73aa7c 6787
29b0f896 6788static void
e3bb37b5 6789output_jump (void)
29b0f896
AM		 6790{
6791 char *p;
6792 int size;
3e02c1cc 6793 fixS *fixP;
29b0f896 6794
40fb9820 6795 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6796 {
6797 /* This is a loop or jecxz type instruction. */
6798 size = 1;
6799 if (i.prefix[ADDR_PREFIX] != 0)
6800 {
6801 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6802 i.prefixes -= 1;
6803 }
6804 /* Pentium4 branch hints. */
6805 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6806 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6807 {
6808 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6809 i.prefixes--;
3e73aa7c
JH		 6810 }
6811 }
29b0f896
AM		 6812 else
6813 {
6814 int code16;
3e73aa7c 6815
29b0f896
AM		 6816 code16 = 0;
6817 if (flag_code == CODE_16BIT)
6818 code16 = CODE16;
3e73aa7c 6819
29b0f896
AM		 6820 if (i.prefix[DATA_PREFIX] != 0)
6821 {
6822 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6823 i.prefixes -= 1;
6824 code16 ^= CODE16;
6825 }
252b5132 6826
29b0f896
AM		 6827 size = 4;
6828 if (code16)
6829 size = 2;
6830 }
9fcc94b6 6831
29b0f896
AM		 6832 if (i.prefix[REX_PREFIX] != 0)
6833 {
6834 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6835 i.prefixes -= 1;
6836 }
252b5132 6837
7e8b059b
L		 6838 /* BND prefixed jump. */
6839 if (i.prefix[BND_PREFIX] != 0)
6840 {
6841 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6842 i.prefixes -= 1;
6843 }
6844
29b0f896
AM		 6845 if (i.prefixes != 0 && !intel_syntax)
6846 as_warn (_("skipping prefixes on this instruction"));
e0890092 6847
42164a71
L		 6848 p = frag_more (i.tm.opcode_length + size);
6849 switch (i.tm.opcode_length)
6850 {
6851 case 2:
6852 *p++ = i.tm.base_opcode >> 8;
6853 case 1:
6854 *p++ = i.tm.base_opcode;
6855 break;
6856 default:
6857 abort ();
6858 }
e0890092 6859
3e02c1cc 6860 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
c3320543
L		 6861 i.op[0].disps, 1, reloc (size, 1, 1,
6862 (i.bnd_prefix != NULL
6863 || add_bnd_prefix),
6864 i.reloc[0]));
3e02c1cc
AM		 6865
6866 /* All jumps handled here are signed, but don't use a signed limit
6867 check for 32 and 16 bit jumps as we want to allow wrap around at
6868 4G and 64k respectively. */
6869 if (size == 1)
6870 fixP->fx_signed = 1;
29b0f896 6871}
e0890092 6872
29b0f896 6873static void
e3bb37b5 6874output_interseg_jump (void)
29b0f896
AM		 6875{
6876 char *p;
6877 int size;
6878 int prefix;
6879 int code16;
252b5132 6880
29b0f896
AM		 6881 code16 = 0;
6882 if (flag_code == CODE_16BIT)
6883 code16 = CODE16;
a217f122 6884
29b0f896
AM		 6885 prefix = 0;
6886 if (i.prefix[DATA_PREFIX] != 0)
6887 {
6888 prefix = 1;
6889 i.prefixes -= 1;
6890 code16 ^= CODE16;
6891 }
6892 if (i.prefix[REX_PREFIX] != 0)
6893 {
6894 prefix++;
6895 i.prefixes -= 1;
6896 }
252b5132 6897
29b0f896
AM		 6898 size = 4;
6899 if (code16)
6900 size = 2;
252b5132 6901
29b0f896
AM		 6902 if (i.prefixes != 0 && !intel_syntax)
6903 as_warn (_("skipping prefixes on this instruction"));
252b5132 6904
29b0f896
AM		 6905 /* 1 opcode; 2 segment; offset */
6906 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6907
29b0f896
AM		 6908 if (i.prefix[DATA_PREFIX] != 0)
6909 *p++ = DATA_PREFIX_OPCODE;
252b5132 6910
29b0f896
AM		 6911 if (i.prefix[REX_PREFIX] != 0)
6912 *p++ = i.prefix[REX_PREFIX];
252b5132 6913
29b0f896
AM		 6914 *p++ = i.tm.base_opcode;
6915 if (i.op[1].imms->X_op == O_constant)
6916 {
6917 offsetT n = i.op[1].imms->X_add_number;
252b5132 6918
29b0f896
AM		 6919 if (size == 2
6920 && !fits_in_unsigned_word (n)
6921 && !fits_in_signed_word (n))
6922 {
6923 as_bad (_("16-bit jump out of range"));
6924 return;
6925 }
6926 md_number_to_chars (p, n, size);
6927 }
6928 else
6929 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
c3320543 6930 i.op[1].imms, 0, reloc (size, 0, 0, 0, i.reloc[1]));
29b0f896
AM		 6931 if (i.op[0].imms->X_op != O_constant)
6932 as_bad (_("can't handle non absolute segment in `%s'"),
6933 i.tm.name);
6934 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6935}
a217f122 6936
29b0f896 6937static void
e3bb37b5 6938output_insn (void)
29b0f896 6939{
2bbd9c25
JJ		 6940 fragS *insn_start_frag;
6941 offsetT insn_start_off;
6942
29b0f896
AM		 6943 /* Tie dwarf2 debug info to the address at the start of the insn.
6944 We can't do this after the insn has been output as the current
6945 frag may have been closed off. eg. by frag_var. */
6946 dwarf2_emit_insn (0);
6947
2bbd9c25
JJ		 6948 insn_start_frag = frag_now;
6949 insn_start_off = frag_now_fix ();
6950
29b0f896 6951 /* Output jumps. */
40fb9820 6952 if (i.tm.opcode_modifier.jump)
29b0f896 6953 output_branch ();
40fb9820
L		 6954 else if (i.tm.opcode_modifier.jumpbyte
6955 || i.tm.opcode_modifier.jumpdword)
29b0f896 6956 output_jump ();
40fb9820 6957 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6958 output_interseg_jump ();
6959 else
6960 {
6961 /* Output normal instructions here. */
6962 char *p;
6963 unsigned char *q;
47465058 6964 unsigned int j;
331d2d0d 6965 unsigned int prefix;
4dffcebc 6966
d022bddd
IT		 6967 /* Some processors fail on LOCK prefix. This options makes
6968 assembler ignore LOCK prefix and serves as a workaround. */
6969 if (omit_lock_prefix)
6970 {
6971 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
6972 return;
6973 i.prefix[LOCK_PREFIX] = 0;
6974 }
6975
43234a1e
L		 6976 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6977 don't need the explicit prefix. */
6978 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 6979 {
c0f3af97 6980 switch (i.tm.opcode_length)
bc4bd9ab 6981 {
c0f3af97
L		 6982 case 3:
6983 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6984 {
c0f3af97
L		 6985 prefix = (i.tm.base_opcode >> 24) & 0xff;
6986 goto check_prefix;
6987 }
6988 break;
6989 case 2:
6990 if ((i.tm.base_opcode & 0xff0000) != 0)
6991 {
6992 prefix = (i.tm.base_opcode >> 16) & 0xff;
6993 if (i.tm.cpu_flags.bitfield.cpupadlock)
6994 {
4dffcebc 6995check_prefix:
c0f3af97 6996 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6997 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6998 != REPE_PREFIX_OPCODE))
6999 add_prefix (prefix);
7000 }
7001 else
4dffcebc
L		 7002 add_prefix (prefix);
7003 }
c0f3af97
L		 7004 break;
7005 case 1:
7006 break;
7007 default:
7008 abort ();
bc4bd9ab 7009 }
c0f3af97 7010
6d19a37a 7011#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7012 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7013 R_X86_64_GOTTPOFF relocation so that linker can safely
7014 perform IE->LE optimization. */
7015 if (x86_elf_abi == X86_64_X32_ABI
7016 && i.operands == 2
7017 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7018 && i.prefix[REX_PREFIX] == 0)
7019 add_prefix (REX_OPCODE);
6d19a37a 7020#endif
cf61b747 7021
c0f3af97
L		 7022 /* The prefix bytes. */
7023 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7024 if (*q)
7025 FRAG_APPEND_1_CHAR (*q);
0f10071e 7026 }
ae5c1c7b 7027 else
c0f3af97
L		 7028 {
7029 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7030 if (*q)
7031 switch (j)
7032 {
7033 case REX_PREFIX:
7034 /* REX byte is encoded in VEX prefix. */
7035 break;
7036 case SEG_PREFIX:
7037 case ADDR_PREFIX:
7038 FRAG_APPEND_1_CHAR (*q);
7039 break;
7040 default:
7041 /* There should be no other prefixes for instructions
7042 with VEX prefix. */
7043 abort ();
7044 }
7045
43234a1e
L		 7046 /* For EVEX instructions i.vrex should become 0 after
7047 build_evex_prefix. For VEX instructions upper 16 registers
7048 aren't available, so VREX should be 0. */
7049 if (i.vrex)
7050 abort ();
c0f3af97
L		 7051 /* Now the VEX prefix. */
7052 p = frag_more (i.vex.length);
7053 for (j = 0; j < i.vex.length; j++)
7054 p[j] = i.vex.bytes[j];
7055 }
252b5132 7056
29b0f896 7057 /* Now the opcode; be careful about word order here! */
4dffcebc 7058 if (i.tm.opcode_length == 1)
29b0f896
AM		 7059 {
7060 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7061 }
7062 else
7063 {
4dffcebc 7064 switch (i.tm.opcode_length)
331d2d0d 7065 {
43234a1e
L		 7066 case 4:
7067 p = frag_more (4);
7068 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7069 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7070 break;
4dffcebc 7071 case 3:
331d2d0d
L		 7072 p = frag_more (3);
7073 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7074 break;
7075 case 2:
7076 p = frag_more (2);
7077 break;
7078 default:
7079 abort ();
7080 break;
331d2d0d 7081 }
0f10071e 7082
29b0f896
AM		 7083 /* Put out high byte first: can't use md_number_to_chars! */
7084 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7085 *p = i.tm.base_opcode & 0xff;
7086 }
3e73aa7c 7087
29b0f896 7088 /* Now the modrm byte and sib byte (if present). */
40fb9820 7089 if (i.tm.opcode_modifier.modrm)
29b0f896 7090 {
4a3523fa
L		 7091 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7092 | i.rm.reg << 3
7093 | i.rm.mode << 6));
29b0f896
AM		 7094 /* If i.rm.regmem == ESP (4)
7095 && i.rm.mode != (Register mode)
7096 && not 16 bit
7097 ==> need second modrm byte. */
7098 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7099 && i.rm.mode != 3
40fb9820 7100 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7101 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7102 | i.sib.index << 3
7103 | i.sib.scale << 6));
29b0f896 7104 }
3e73aa7c 7105
29b0f896 7106 if (i.disp_operands)
2bbd9c25 7107 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7108
29b0f896 7109 if (i.imm_operands)
2bbd9c25 7110 output_imm (insn_start_frag, insn_start_off);
29b0f896 7111 }
252b5132 7112
29b0f896
AM		 7113#ifdef DEBUG386
7114 if (flag_debug)
7115 {
7b81dfbb 7116 pi ("" /*line*/, &i);
29b0f896
AM		 7117 }
7118#endif /* DEBUG386 */
7119}
252b5132 7120
e205caa7
L		 7121/* Return the size of the displacement operand N. */
7122
7123static int
7124disp_size (unsigned int n)
7125{
7126 int size = 4;
43234a1e
L		 7127
7128 /* Vec_Disp8 has to be 8bit. */
7129 if (i.types[n].bitfield.vec_disp8)
7130 size = 1;
7131 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7132 size = 8;
7133 else if (i.types[n].bitfield.disp8)
7134 size = 1;
7135 else if (i.types[n].bitfield.disp16)
7136 size = 2;
e205caa7
L		 7137 return size;
7138}
7139
7140/* Return the size of the immediate operand N. */
7141
7142static int
7143imm_size (unsigned int n)
7144{
7145 int size = 4;
40fb9820
L		 7146 if (i.types[n].bitfield.imm64)
7147 size = 8;
7148 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7149 size = 1;
7150 else if (i.types[n].bitfield.imm16)
7151 size = 2;
e205caa7
L		 7152 return size;
7153}
7154
29b0f896 7155static void
64e74474 7156output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7157{
7158 char *p;
7159 unsigned int n;
252b5132 7160
29b0f896
AM		 7161 for (n = 0; n < i.operands; n++)
7162 {
43234a1e
L		 7163 if (i.types[n].bitfield.vec_disp8
7164 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7165 {
7166 if (i.op[n].disps->X_op == O_constant)
7167 {
e205caa7 7168 int size = disp_size (n);
43234a1e 7169 offsetT val = i.op[n].disps->X_add_number;
252b5132 7170
43234a1e
L		 7171 if (i.types[n].bitfield.vec_disp8)
7172 val >>= i.memshift;
7173 val = offset_in_range (val, size);
29b0f896
AM		 7174 p = frag_more (size);
7175 md_number_to_chars (p, val, size);
7176 }
7177 else
7178 {
f86103b7 7179 enum bfd_reloc_code_real reloc_type;
e205caa7 7180 int size = disp_size (n);
40fb9820 7181 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 7182 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7183
e205caa7 7184 /* We can't have 8 bit displacement here. */
9c2799c2 7185 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7186
29b0f896
AM		 7187 /* The PC relative address is computed relative
7188 to the instruction boundary, so in case immediate
7189 fields follows, we need to adjust the value. */
7190 if (pcrel && i.imm_operands)
7191 {
29b0f896 7192 unsigned int n1;
e205caa7 7193 int sz = 0;
252b5132 7194
29b0f896 7195 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7196 if (operand_type_check (i.types[n1], imm))
252b5132 7197 {
e205caa7
L		 7198 /* Only one immediate is allowed for PC
7199 relative address. */
9c2799c2 7200 gas_assert (sz == 0);
e205caa7
L		 7201 sz = imm_size (n1);
7202 i.op[n].disps->X_add_number -= sz;
252b5132 7203 }
29b0f896 7204 /* We should find the immediate. */
9c2799c2 7205 gas_assert (sz != 0);
29b0f896 7206 }
520dc8e8 7207
29b0f896 7208 p = frag_more (size);
c3320543
L		 7209 reloc_type = reloc (size, pcrel, sign,
7210 (i.bnd_prefix != NULL
7211 || add_bnd_prefix),
7212 i.reloc[n]);
d6ab8113 7213 if (GOT_symbol
2bbd9c25 7214 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7215 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7216 || reloc_type == BFD_RELOC_X86_64_32S
7217 || (reloc_type == BFD_RELOC_64
7218 && object_64bit))
d6ab8113
JB		 7219 && (i.op[n].disps->X_op == O_symbol
7220 || (i.op[n].disps->X_op == O_add
7221 && ((symbol_get_value_expression
7222 (i.op[n].disps->X_op_symbol)->X_op)
7223 == O_subtract))))
7224 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7225 {
7226 offsetT add;
7227
7228 if (insn_start_frag == frag_now)
7229 add = (p - frag_now->fr_literal) - insn_start_off;
7230 else
7231 {
7232 fragS *fr;
7233
7234 add = insn_start_frag->fr_fix - insn_start_off;
7235 for (fr = insn_start_frag->fr_next;
7236 fr && fr != frag_now; fr = fr->fr_next)
7237 add += fr->fr_fix;
7238 add += p - frag_now->fr_literal;
7239 }
7240
4fa24527 7241 if (!object_64bit)
7b81dfbb
AJ		 7242 {
7243 reloc_type = BFD_RELOC_386_GOTPC;
7244 i.op[n].imms->X_add_number += add;
7245 }
7246 else if (reloc_type == BFD_RELOC_64)
7247 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7248 else
7b81dfbb
AJ		 7249 /* Don't do the adjustment for x86-64, as there
7250 the pcrel addressing is relative to the _next_
7251 insn, and that is taken care of in other code. */
d6ab8113 7252 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7253 }
062cd5e7 7254 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 7255 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 7256 }
7257 }
7258 }
7259}
252b5132 7260
29b0f896 7261static void
64e74474 7262output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7263{
7264 char *p;
7265 unsigned int n;
252b5132 7266
29b0f896
AM		 7267 for (n = 0; n < i.operands; n++)
7268 {
43234a1e
L		 7269 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7270 if (i.rounding && (int) n == i.rounding->operand)
7271 continue;
7272
40fb9820 7273 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7274 {
7275 if (i.op[n].imms->X_op == O_constant)
7276 {
e205caa7 7277 int size = imm_size (n);
29b0f896 7278 offsetT val;
b4cac588 7279
29b0f896
AM		 7280 val = offset_in_range (i.op[n].imms->X_add_number,
7281 size);
7282 p = frag_more (size);
7283 md_number_to_chars (p, val, size);
7284 }
7285 else
7286 {
7287 /* Not absolute_section.
7288 Need a 32-bit fixup (don't support 8bit
7289 non-absolute imms). Try to support other
7290 sizes ... */
f86103b7 7291 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7292 int size = imm_size (n);
7293 int sign;
29b0f896 7294
40fb9820 7295 if (i.types[n].bitfield.imm32s
a7d61044 7296 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7297 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7298 sign = 1;
e205caa7
L		 7299 else
7300 sign = 0;
520dc8e8 7301
29b0f896 7302 p = frag_more (size);
c3320543 7303 reloc_type = reloc (size, 0, sign, 0, i.reloc[n]);
f86103b7 7304
2bbd9c25
JJ		 7305 /* This is tough to explain. We end up with this one if we
7306 * have operands that look like
7307 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7308 * obtain the absolute address of the GOT, and it is strongly
7309 * preferable from a performance point of view to avoid using
7310 * a runtime relocation for this. The actual sequence of
7311 * instructions often look something like:
7312 *
7313 * call .L66
7314 * .L66:
7315 * popl %ebx
7316 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7317 *
7318 * The call and pop essentially return the absolute address
7319 * of the label .L66 and store it in %ebx. The linker itself
7320 * will ultimately change the first operand of the addl so
7321 * that %ebx points to the GOT, but to keep things simple, the
7322 * .o file must have this operand set so that it generates not
7323 * the absolute address of .L66, but the absolute address of
7324 * itself. This allows the linker itself simply treat a GOTPC
7325 * relocation as asking for a pcrel offset to the GOT to be
7326 * added in, and the addend of the relocation is stored in the
7327 * operand field for the instruction itself.
7328 *
7329 * Our job here is to fix the operand so that it would add
7330 * the correct offset so that %ebx would point to itself. The
7331 * thing that is tricky is that .-.L66 will point to the
7332 * beginning of the instruction, so we need to further modify
7333 * the operand so that it will point to itself. There are
7334 * other cases where you have something like:
7335 *
7336 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7337 *
7338 * and here no correction would be required. Internally in
7339 * the assembler we treat operands of this form as not being
7340 * pcrel since the '.' is explicitly mentioned, and I wonder
7341 * whether it would simplify matters to do it this way. Who
7342 * knows. In earlier versions of the PIC patches, the
7343 * pcrel_adjust field was used to store the correction, but
7344 * since the expression is not pcrel, I felt it would be
7345 * confusing to do it this way. */
7346
d6ab8113 7347 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7348 || reloc_type == BFD_RELOC_X86_64_32S
7349 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7350 && GOT_symbol
7351 && GOT_symbol == i.op[n].imms->X_add_symbol
7352 && (i.op[n].imms->X_op == O_symbol
7353 || (i.op[n].imms->X_op == O_add
7354 && ((symbol_get_value_expression
7355 (i.op[n].imms->X_op_symbol)->X_op)
7356 == O_subtract))))
7357 {
2bbd9c25
JJ		 7358 offsetT add;
7359
7360 if (insn_start_frag == frag_now)
7361 add = (p - frag_now->fr_literal) - insn_start_off;
7362 else
7363 {
7364 fragS *fr;
7365
7366 add = insn_start_frag->fr_fix - insn_start_off;
7367 for (fr = insn_start_frag->fr_next;
7368 fr && fr != frag_now; fr = fr->fr_next)
7369 add += fr->fr_fix;
7370 add += p - frag_now->fr_literal;
7371 }
7372
4fa24527 7373 if (!object_64bit)
d6ab8113 7374 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7375 else if (size == 4)
d6ab8113 7376 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7377 else if (size == 8)
7378 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7379 i.op[n].imms->X_add_number += add;
29b0f896 7380 }
29b0f896
AM		 7381 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7382 i.op[n].imms, 0, reloc_type);
7383 }
7384 }
7385 }
252b5132
RH		 7386}
7387\f
d182319b
JB		 7388/* x86_cons_fix_new is called via the expression parsing code when a
7389 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7390static int cons_sign = -1;
7391
7392void
e3bb37b5 7393x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7394 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7395{
62ebcb5c 7396 r = reloc (len, 0, cons_sign, 0, r);
d182319b
JB		 7397
7398#ifdef TE_PE
7399 if (exp->X_op == O_secrel)
7400 {
7401 exp->X_op = O_symbol;
7402 r = BFD_RELOC_32_SECREL;
7403 }
7404#endif
7405
7406 fix_new_exp (frag, off, len, exp, 0, r);
7407}
7408
357d1bd8
L		 7409/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7410 purpose of the `.dc.a' internal pseudo-op. */
7411
7412int
7413x86_address_bytes (void)
7414{
7415 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7416 return 4;
7417 return stdoutput->arch_info->bits_per_address / 8;
7418}
7419
d382c579
TG		 7420#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7421 || defined (LEX_AT)
c06ec724 7422# define lex_got(reloc, adjust, types, bnd_prefix) NULL
718ddfc0 7423#else
f3c180ae
AM		 7424/* Parse operands of the form
7425 <symbol>@GOTOFF+<nnn>
7426 and similar .plt or .got references.
7427
7428 If we find one, set up the correct relocation in RELOC and copy the
7429 input string, minus the `@GOTOFF' into a malloc'd buffer for
7430 parsing by the calling routine. Return this buffer, and if ADJUST
7431 is non-null set it to the length of the string we removed from the
7432 input line. Otherwise return NULL. */
7433static char *
91d6fa6a 7434lex_got (enum bfd_reloc_code_real *rel,
64e74474 7435 int *adjust,
c3320543
L		 7436 i386_operand_type *types,
7437 int bnd_prefix)
f3c180ae 7438{
7b81dfbb
AJ		 7439 /* Some of the relocations depend on the size of what field is to
7440 be relocated. But in our callers i386_immediate and i386_displacement
7441 we don't yet know the operand size (this will be set by insn
7442 matching). Hence we record the word32 relocation here,
7443 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7444 static const struct {
7445 const char *str;
cff8d58a 7446 int len;
4fa24527 7447 const enum bfd_reloc_code_real rel[2];
40fb9820 7448 const i386_operand_type types64;
f3c180ae 7449 } gotrel[] = {
8ce3d284 7450#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7451 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7452 BFD_RELOC_SIZE32 },
7453 OPERAND_TYPE_IMM32_64 },
8ce3d284 7454#endif
cff8d58a
L		 7455 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7456 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7457 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7458 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7459 BFD_RELOC_X86_64_PLT32 },
40fb9820 7460 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7461 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7462 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7463 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7464 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7465 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7466 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7467 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7468 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7469 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7470 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7471 BFD_RELOC_X86_64_TLSGD },
40fb9820 7472 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7473 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7474 _dummy_first_bfd_reloc_code_real },
40fb9820 7475 OPERAND_TYPE_NONE },
cff8d58a
L		 7476 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7477 BFD_RELOC_X86_64_TLSLD },
40fb9820 7478 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7479 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7480 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7481 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7482 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7483 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7484 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7485 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7486 _dummy_first_bfd_reloc_code_real },
40fb9820 7487 OPERAND_TYPE_NONE },
cff8d58a
L		 7488 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7489 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7490 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7491 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7492 _dummy_first_bfd_reloc_code_real },
40fb9820 7493 OPERAND_TYPE_NONE },
cff8d58a
L		 7494 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7495 _dummy_first_bfd_reloc_code_real },
40fb9820 7496 OPERAND_TYPE_NONE },
cff8d58a
L		 7497 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7498 BFD_RELOC_X86_64_GOT32 },
40fb9820 7499 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7500 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7501 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7502 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7503 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7504 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7505 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7506 };
7507 char *cp;
7508 unsigned int j;
7509
d382c579 7510#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7511 if (!IS_ELF)
7512 return NULL;
d382c579 7513#endif
718ddfc0 7514
f3c180ae 7515 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7516 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7517 return NULL;
7518
47465058 7519 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7520 {
cff8d58a 7521 int len = gotrel[j].len;
28f81592 7522 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7523 {
4fa24527 7524 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7525 {
28f81592
AM		 7526 int first, second;
7527 char *tmpbuf, *past_reloc;
f3c180ae 7528
91d6fa6a 7529 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7530
3956db08
JB		 7531 if (types)
7532 {
7533 if (flag_code != CODE_64BIT)
40fb9820
L		 7534 {
7535 types->bitfield.imm32 = 1;
7536 types->bitfield.disp32 = 1;
7537 }
3956db08
JB		 7538 else
7539 *types = gotrel[j].types64;
7540 }
7541
8fd4256d 7542 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7543 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7544
28f81592 7545 /* The length of the first part of our input line. */
f3c180ae 7546 first = cp - input_line_pointer;
28f81592
AM		 7547
7548 /* The second part goes from after the reloc token until
67c11a9b 7549 (and including) an end_of_line char or comma. */
28f81592 7550 past_reloc = cp + 1 + len;
67c11a9b
AM		 7551 cp = past_reloc;
7552 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7553 ++cp;
7554 second = cp + 1 - past_reloc;
28f81592
AM		 7555
7556 /* Allocate and copy string. The trailing NUL shouldn't
7557 be necessary, but be safe. */
1e9cc1c2 7558 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 7559 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7560 if (second != 0 && *past_reloc != ' ')
7561 /* Replace the relocation token with ' ', so that
7562 errors like foo@GOTOFF1 will be detected. */
7563 tmpbuf[first++] = ' ';
af89796a
L		 7564 else
7565 /* Increment length by 1 if the relocation token is
7566 removed. */
7567 len++;
7568 if (adjust)
7569 *adjust = len;
0787a12d
AM		 7570 memcpy (tmpbuf + first, past_reloc, second);
7571 tmpbuf[first + second] = '\0';
c3320543
L		 7572 if (bnd_prefix && *rel == BFD_RELOC_X86_64_PLT32)
7573 *rel = BFD_RELOC_X86_64_PLT32_BND;
f3c180ae
AM		 7574 return tmpbuf;
7575 }
7576
4fa24527
JB		 7577 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7578 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7579 return NULL;
7580 }
7581 }
7582
7583 /* Might be a symbol version string. Don't as_bad here. */
7584 return NULL;
7585}
4e4f7c87 7586#endif
f3c180ae 7587
a988325c
NC		 7588#ifdef TE_PE
7589#ifdef lex_got
7590#undef lex_got
7591#endif
7592/* Parse operands of the form
7593 <symbol>@SECREL32+<nnn>
7594
7595 If we find one, set up the correct relocation in RELOC and copy the
7596 input string, minus the `@SECREL32' into a malloc'd buffer for
7597 parsing by the calling routine. Return this buffer, and if ADJUST
7598 is non-null set it to the length of the string we removed from the
34bca508
L		 7599 input line. Otherwise return NULL.
7600
a988325c
NC		 7601 This function is copied from the ELF version above adjusted for PE targets. */
7602
7603static char *
7604lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7605 int *adjust ATTRIBUTE_UNUSED,
c06ec724
L		 7606 i386_operand_type *types,
7607 int bnd_prefix ATTRIBUTE_UNUSED)
a988325c
NC		 7608{
7609 static const struct
7610 {
7611 const char *str;
7612 int len;
7613 const enum bfd_reloc_code_real rel[2];
7614 const i386_operand_type types64;
7615 }
7616 gotrel[] =
7617 {
7618 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7619 BFD_RELOC_32_SECREL },
7620 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7621 };
7622
7623 char *cp;
7624 unsigned j;
7625
7626 for (cp = input_line_pointer; *cp != '@'; cp++)
7627 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7628 return NULL;
7629
7630 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7631 {
7632 int len = gotrel[j].len;
7633
7634 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7635 {
7636 if (gotrel[j].rel[object_64bit] != 0)
7637 {
7638 int first, second;
7639 char *tmpbuf, *past_reloc;
7640
7641 *rel = gotrel[j].rel[object_64bit];
7642 if (adjust)
7643 *adjust = len;
7644
7645 if (types)
7646 {
7647 if (flag_code != CODE_64BIT)
7648 {
7649 types->bitfield.imm32 = 1;
7650 types->bitfield.disp32 = 1;
7651 }
7652 else
7653 *types = gotrel[j].types64;
7654 }
7655
7656 /* The length of the first part of our input line. */
7657 first = cp - input_line_pointer;
7658
7659 /* The second part goes from after the reloc token until
7660 (and including) an end_of_line char or comma. */
7661 past_reloc = cp + 1 + len;
7662 cp = past_reloc;
7663 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7664 ++cp;
7665 second = cp + 1 - past_reloc;
7666
7667 /* Allocate and copy string. The trailing NUL shouldn't
7668 be necessary, but be safe. */
7669 tmpbuf = (char *) xmalloc (first + second + 2);
7670 memcpy (tmpbuf, input_line_pointer, first);
7671 if (second != 0 && *past_reloc != ' ')
7672 /* Replace the relocation token with ' ', so that
7673 errors like foo@SECLREL321 will be detected. */
7674 tmpbuf[first++] = ' ';
7675 memcpy (tmpbuf + first, past_reloc, second);
7676 tmpbuf[first + second] = '\0';
7677 return tmpbuf;
7678 }
7679
7680 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7681 gotrel[j].str, 1 << (5 + object_64bit));
7682 return NULL;
7683 }
7684 }
7685
7686 /* Might be a symbol version string. Don't as_bad here. */
7687 return NULL;
7688}
7689
7690#endif /* TE_PE */
7691
62ebcb5c 7692bfd_reloc_code_real_type
e3bb37b5 7693x86_cons (expressionS *exp, int size)
f3c180ae 7694{
62ebcb5c
AM		 7695 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7696
ee86248c
JB		 7697 intel_syntax = -intel_syntax;
7698
3c7b9c2c 7699 exp->X_md = 0;
4fa24527 7700 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7701 {
7702 /* Handle @GOTOFF and the like in an expression. */
7703 char *save;
7704 char *gotfree_input_line;
4a57f2cf 7705 int adjust = 0;
f3c180ae
AM		 7706
7707 save = input_line_pointer;
c3320543 7708 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL, 0);
f3c180ae
AM		 7709 if (gotfree_input_line)
7710 input_line_pointer = gotfree_input_line;
7711
7712 expression (exp);
7713
7714 if (gotfree_input_line)
7715 {
7716 /* expression () has merrily parsed up to the end of line,
7717 or a comma - in the wrong buffer. Transfer how far
7718 input_line_pointer has moved to the right buffer. */
7719 input_line_pointer = (save
7720 + (input_line_pointer - gotfree_input_line)
7721 + adjust);
7722 free (gotfree_input_line);
3992d3b7
AM		 7723 if (exp->X_op == O_constant
7724 || exp->X_op == O_absent
7725 || exp->X_op == O_illegal
0398aac5 7726 || exp->X_op == O_register
3992d3b7
AM		 7727 || exp->X_op == O_big)
7728 {
7729 char c = *input_line_pointer;
7730 *input_line_pointer = 0;
7731 as_bad (_("missing or invalid expression `%s'"), save);
7732 *input_line_pointer = c;
7733 }
f3c180ae
AM		 7734 }
7735 }
7736 else
7737 expression (exp);
ee86248c
JB		 7738
7739 intel_syntax = -intel_syntax;
7740
7741 if (intel_syntax)
7742 i386_intel_simplify (exp);
62ebcb5c
AM		 7743
7744 return got_reloc;
f3c180ae 7745}
f3c180ae 7746
9f32dd5b
L		 7747static void
7748signed_cons (int size)
6482c264 7749{
d182319b
JB		 7750 if (flag_code == CODE_64BIT)
7751 cons_sign = 1;
7752 cons (size);
7753 cons_sign = -1;
6482c264
NC		 7754}
7755
d182319b 7756#ifdef TE_PE
6482c264 7757static void
7016a5d5 7758pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7759{
7760 expressionS exp;
7761
7762 do
7763 {
7764 expression (&exp);
7765 if (exp.X_op == O_symbol)
7766 exp.X_op = O_secrel;
7767
7768 emit_expr (&exp, 4);
7769 }
7770 while (*input_line_pointer++ == ',');
7771
7772 input_line_pointer--;
7773 demand_empty_rest_of_line ();
7774}
6482c264
NC		 7775#endif
7776
43234a1e
L		 7777/* Handle Vector operations. */
7778
7779static char *
7780check_VecOperations (char *op_string, char *op_end)
7781{
7782 const reg_entry *mask;
7783 const char *saved;
7784 char *end_op;
7785
7786 while (*op_string
7787 && (op_end == NULL || op_string < op_end))
7788 {
7789 saved = op_string;
7790 if (*op_string == '{')
7791 {
7792 op_string++;
7793
7794 /* Check broadcasts. */
7795 if (strncmp (op_string, "1to", 3) == 0)
7796 {
7797 int bcst_type;
7798
7799 if (i.broadcast)
7800 goto duplicated_vec_op;
7801
7802 op_string += 3;
7803 if (*op_string == '8')
7804 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 7805 else if (*op_string == '4')
7806 bcst_type = BROADCAST_1TO4;
7807 else if (*op_string == '2')
7808 bcst_type = BROADCAST_1TO2;
43234a1e
L		 7809 else if (*op_string == '1'
7810 && *(op_string+1) == '6')
7811 {
7812 bcst_type = BROADCAST_1TO16;
7813 op_string++;
7814 }
7815 else
7816 {
7817 as_bad (_("Unsupported broadcast: `%s'"), saved);
7818 return NULL;
7819 }
7820 op_string++;
7821
7822 broadcast_op.type = bcst_type;
7823 broadcast_op.operand = this_operand;
7824 i.broadcast = &broadcast_op;
7825 }
7826 /* Check masking operation. */
7827 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7828 {
7829 /* k0 can't be used for write mask. */
7830 if (mask->reg_num == 0)
7831 {
7832 as_bad (_("`%s' can't be used for write mask"),
7833 op_string);
7834 return NULL;
7835 }
7836
7837 if (!i.mask)
7838 {
7839 mask_op.mask = mask;
7840 mask_op.zeroing = 0;
7841 mask_op.operand = this_operand;
7842 i.mask = &mask_op;
7843 }
7844 else
7845 {
7846 if (i.mask->mask)
7847 goto duplicated_vec_op;
7848
7849 i.mask->mask = mask;
7850
7851 /* Only "{z}" is allowed here. No need to check
7852 zeroing mask explicitly. */
7853 if (i.mask->operand != this_operand)
7854 {
7855 as_bad (_("invalid write mask `%s'"), saved);
7856 return NULL;
7857 }
7858 }
7859
7860 op_string = end_op;
7861 }
7862 /* Check zeroing-flag for masking operation. */
7863 else if (*op_string == 'z')
7864 {
7865 if (!i.mask)
7866 {
7867 mask_op.mask = NULL;
7868 mask_op.zeroing = 1;
7869 mask_op.operand = this_operand;
7870 i.mask = &mask_op;
7871 }
7872 else
7873 {
7874 if (i.mask->zeroing)
7875 {
7876 duplicated_vec_op:
7877 as_bad (_("duplicated `%s'"), saved);
7878 return NULL;
7879 }
7880
7881 i.mask->zeroing = 1;
7882
7883 /* Only "{%k}" is allowed here. No need to check mask
7884 register explicitly. */
7885 if (i.mask->operand != this_operand)
7886 {
7887 as_bad (_("invalid zeroing-masking `%s'"),
7888 saved);
7889 return NULL;
7890 }
7891 }
7892
7893 op_string++;
7894 }
7895 else
7896 goto unknown_vec_op;
7897
7898 if (*op_string != '}')
7899 {
7900 as_bad (_("missing `}' in `%s'"), saved);
7901 return NULL;
7902 }
7903 op_string++;
7904 continue;
7905 }
7906 unknown_vec_op:
7907 /* We don't know this one. */
7908 as_bad (_("unknown vector operation: `%s'"), saved);
7909 return NULL;
7910 }
7911
7912 return op_string;
7913}
7914
252b5132 7915static int
70e41ade 7916i386_immediate (char *imm_start)
252b5132
RH		 7917{
7918 char *save_input_line_pointer;
f3c180ae 7919 char *gotfree_input_line;
252b5132 7920 segT exp_seg = 0;
47926f60 7921 expressionS *exp;
40fb9820
L		 7922 i386_operand_type types;
7923
0dfbf9d7 7924 operand_type_set (&types, ~0);
252b5132
RH		 7925
7926 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7927 {
31b2323c
L		 7928 as_bad (_("at most %d immediate operands are allowed"),
7929 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 7930 return 0;
7931 }
7932
7933 exp = &im_expressions[i.imm_operands++];
520dc8e8 7934 i.op[this_operand].imms = exp;
252b5132
RH		 7935
7936 if (is_space_char (*imm_start))
7937 ++imm_start;
7938
7939 save_input_line_pointer = input_line_pointer;
7940 input_line_pointer = imm_start;
7941
c3320543
L		 7942 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types,
7943 (i.bnd_prefix != NULL
7944 || add_bnd_prefix));
f3c180ae
AM		 7945 if (gotfree_input_line)
7946 input_line_pointer = gotfree_input_line;
252b5132
RH		 7947
7948 exp_seg = expression (exp);
7949
83183c0c 7950 SKIP_WHITESPACE ();
43234a1e
L		 7951
7952 /* Handle vector operations. */
7953 if (*input_line_pointer == '{')
7954 {
7955 input_line_pointer = check_VecOperations (input_line_pointer,
7956 NULL);
7957 if (input_line_pointer == NULL)
7958 return 0;
7959 }
7960
252b5132 7961 if (*input_line_pointer)
f3c180ae 7962 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 7963
7964 input_line_pointer = save_input_line_pointer;
f3c180ae 7965 if (gotfree_input_line)
ee86248c
JB		 7966 {
7967 free (gotfree_input_line);
7968
7969 if (exp->X_op == O_constant || exp->X_op == O_register)
7970 exp->X_op = O_illegal;
7971 }
7972
7973 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7974}
252b5132 7975
ee86248c
JB		 7976static int
7977i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7978 i386_operand_type types, const char *imm_start)
7979{
7980 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 7981 {
313c53d1
L		 7982 if (imm_start)
7983 as_bad (_("missing or invalid immediate expression `%s'"),
7984 imm_start);
3992d3b7 7985 return 0;
252b5132 7986 }
3e73aa7c 7987 else if (exp->X_op == O_constant)
252b5132 7988 {
47926f60 7989 /* Size it properly later. */
40fb9820 7990 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 7991 /* If not 64bit, sign extend val. */
7992 if (flag_code != CODE_64BIT
4eed87de
AM		 7993 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7994 exp->X_add_number
7995 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 7996 }
4c63da97 7997#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 7998 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 7999 && exp_seg != absolute_section
47926f60 8000 && exp_seg != text_section
24eab124
AM		 8001 && exp_seg != data_section
8002 && exp_seg != bss_section
8003 && exp_seg != undefined_section
f86103b7 8004 && !bfd_is_com_section (exp_seg))
252b5132 8005 {
d0b47220 8006 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8007 return 0;
8008 }
8009#endif
a841bdf5 8010 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8011 {
313c53d1
L		 8012 if (imm_start)
8013 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8014 return 0;
8015 }
252b5132
RH		 8016 else
8017 {
8018 /* This is an address. The size of the address will be
24eab124 8019 determined later, depending on destination register,
3e73aa7c 8020 suffix, or the default for the section. */
40fb9820
L		 8021 i.types[this_operand].bitfield.imm8 = 1;
8022 i.types[this_operand].bitfield.imm16 = 1;
8023 i.types[this_operand].bitfield.imm32 = 1;
8024 i.types[this_operand].bitfield.imm32s = 1;
8025 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8026 i.types[this_operand] = operand_type_and (i.types[this_operand],
8027 types);
252b5132
RH		 8028 }
8029
8030 return 1;
8031}
8032
551c1ca1 8033static char *
e3bb37b5 8034i386_scale (char *scale)
252b5132 8035{
551c1ca1
AM		 8036 offsetT val;
8037 char *save = input_line_pointer;
252b5132 8038
551c1ca1
AM		 8039 input_line_pointer = scale;
8040 val = get_absolute_expression ();
8041
8042 switch (val)
252b5132 8043 {
551c1ca1 8044 case 1:
252b5132
RH		 8045 i.log2_scale_factor = 0;
8046 break;
551c1ca1 8047 case 2:
252b5132
RH		 8048 i.log2_scale_factor = 1;
8049 break;
551c1ca1 8050 case 4:
252b5132
RH		 8051 i.log2_scale_factor = 2;
8052 break;
551c1ca1 8053 case 8:
252b5132
RH		 8054 i.log2_scale_factor = 3;
8055 break;
8056 default:
a724f0f4
JB		 8057 {
8058 char sep = *input_line_pointer;
8059
8060 *input_line_pointer = '\0';
8061 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8062 scale);
8063 *input_line_pointer = sep;
8064 input_line_pointer = save;
8065 return NULL;
8066 }
252b5132 8067 }
29b0f896 8068 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8069 {
8070 as_warn (_("scale factor of %d without an index register"),
24eab124 8071 1 << i.log2_scale_factor);
252b5132 8072 i.log2_scale_factor = 0;
252b5132 8073 }
551c1ca1
AM		 8074 scale = input_line_pointer;
8075 input_line_pointer = save;
8076 return scale;
252b5132
RH		 8077}
8078
252b5132 8079static int
e3bb37b5 8080i386_displacement (char *disp_start, char *disp_end)
252b5132 8081{
29b0f896 8082 expressionS *exp;
252b5132
RH		 8083 segT exp_seg = 0;
8084 char *save_input_line_pointer;
f3c180ae 8085 char *gotfree_input_line;
40fb9820
L		 8086 int override;
8087 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8088 int ret;
252b5132 8089
31b2323c
L		 8090 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8091 {
8092 as_bad (_("at most %d displacement operands are allowed"),
8093 MAX_MEMORY_OPERANDS);
8094 return 0;
8095 }
8096
0dfbf9d7 8097 operand_type_set (&bigdisp, 0);
40fb9820
L		 8098 if ((i.types[this_operand].bitfield.jumpabsolute)
8099 || (!current_templates->start->opcode_modifier.jump
8100 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8101 {
40fb9820 8102 bigdisp.bitfield.disp32 = 1;
e05278af 8103 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8104 if (flag_code == CODE_64BIT)
8105 {
8106 if (!override)
8107 {
8108 bigdisp.bitfield.disp32s = 1;
8109 bigdisp.bitfield.disp64 = 1;
8110 }
8111 }
8112 else if ((flag_code == CODE_16BIT) ^ override)
8113 {
8114 bigdisp.bitfield.disp32 = 0;
8115 bigdisp.bitfield.disp16 = 1;
8116 }
e05278af
JB		 8117 }
8118 else
8119 {
8120 /* For PC-relative branches, the width of the displacement
8121 is dependent upon data size, not address size. */
e05278af 8122 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8123 if (flag_code == CODE_64BIT)
8124 {
8125 if (override || i.suffix == WORD_MNEM_SUFFIX)
8126 bigdisp.bitfield.disp16 = 1;
8127 else
8128 {
8129 bigdisp.bitfield.disp32 = 1;
8130 bigdisp.bitfield.disp32s = 1;
8131 }
8132 }
8133 else
e05278af
JB		 8134 {
8135 if (!override)
8136 override = (i.suffix == (flag_code != CODE_16BIT
8137 ? WORD_MNEM_SUFFIX
8138 : LONG_MNEM_SUFFIX));
40fb9820
L		 8139 bigdisp.bitfield.disp32 = 1;
8140 if ((flag_code == CODE_16BIT) ^ override)
8141 {
8142 bigdisp.bitfield.disp32 = 0;
8143 bigdisp.bitfield.disp16 = 1;
8144 }
e05278af 8145 }
e05278af 8146 }
c6fb90c8
L		 8147 i.types[this_operand] = operand_type_or (i.types[this_operand],
8148 bigdisp);
252b5132
RH		 8149
8150 exp = &disp_expressions[i.disp_operands];
520dc8e8 8151 i.op[this_operand].disps = exp;
252b5132
RH		 8152 i.disp_operands++;
8153 save_input_line_pointer = input_line_pointer;
8154 input_line_pointer = disp_start;
8155 END_STRING_AND_SAVE (disp_end);
8156
8157#ifndef GCC_ASM_O_HACK
8158#define GCC_ASM_O_HACK 0
8159#endif
8160#if GCC_ASM_O_HACK
8161 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8162 if (i.types[this_operand].bitfield.baseIndex
24eab124 8163 && displacement_string_end[-1] == '+')
252b5132
RH		 8164 {
8165 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8166 constraint within gcc asm statements.
8167 For instance:
8168
8169 #define _set_tssldt_desc(n,addr,limit,type) \
8170 __asm__ __volatile__ ( \
8171 "movw %w2,%0\n\t" \
8172 "movw %w1,2+%0\n\t" \
8173 "rorl $16,%1\n\t" \
8174 "movb %b1,4+%0\n\t" \
8175 "movb %4,5+%0\n\t" \
8176 "movb $0,6+%0\n\t" \
8177 "movb %h1,7+%0\n\t" \
8178 "rorl $16,%1" \
8179 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8180
8181 This works great except that the output assembler ends
8182 up looking a bit weird if it turns out that there is
8183 no offset. You end up producing code that looks like:
8184
8185 #APP
8186 movw $235,(%eax)
8187 movw %dx,2+(%eax)
8188 rorl $16,%edx
8189 movb %dl,4+(%eax)
8190 movb $137,5+(%eax)
8191 movb $0,6+(%eax)
8192 movb %dh,7+(%eax)
8193 rorl $16,%edx
8194 #NO_APP
8195
47926f60 8196 So here we provide the missing zero. */
24eab124
AM		 8197
8198 *displacement_string_end = '0';
252b5132
RH		 8199 }
8200#endif
c3320543
L		 8201 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types,
8202 (i.bnd_prefix != NULL
8203 || add_bnd_prefix));
f3c180ae
AM		 8204 if (gotfree_input_line)
8205 input_line_pointer = gotfree_input_line;
252b5132 8206
24eab124 8207 exp_seg = expression (exp);
252b5132 8208
636c26b0
AM		 8209 SKIP_WHITESPACE ();
8210 if (*input_line_pointer)
8211 as_bad (_("junk `%s' after expression"), input_line_pointer);
8212#if GCC_ASM_O_HACK
8213 RESTORE_END_STRING (disp_end + 1);
8214#endif
636c26b0 8215 input_line_pointer = save_input_line_pointer;
636c26b0 8216 if (gotfree_input_line)
ee86248c
JB		 8217 {
8218 free (gotfree_input_line);
8219
8220 if (exp->X_op == O_constant || exp->X_op == O_register)
8221 exp->X_op = O_illegal;
8222 }
8223
8224 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8225
8226 RESTORE_END_STRING (disp_end);
8227
8228 return ret;
8229}
8230
8231static int
8232i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8233 i386_operand_type types, const char *disp_start)
8234{
8235 i386_operand_type bigdisp;
8236 int ret = 1;
636c26b0 8237
24eab124
AM		 8238 /* We do this to make sure that the section symbol is in
8239 the symbol table. We will ultimately change the relocation
47926f60 8240 to be relative to the beginning of the section. */
1ae12ab7 8241 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8242 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8243 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8244 {
636c26b0 8245 if (exp->X_op != O_symbol)
3992d3b7 8246 goto inv_disp;
636c26b0 8247
e5cb08ac 8248 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8249 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8250 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8251 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8252 exp->X_op = O_subtract;
8253 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8254 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8255 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8256 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8257 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8258 else
29b0f896 8259 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8260 }
252b5132 8261
3992d3b7
AM		 8262 else if (exp->X_op == O_absent
8263 || exp->X_op == O_illegal
ee86248c 8264 || exp->X_op == O_big)
2daf4fd8 8265 {
3992d3b7
AM		 8266 inv_disp:
8267 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8268 disp_start);
3992d3b7 8269 ret = 0;
2daf4fd8
AM		 8270 }
8271
0e1147d9
L		 8272 else if (flag_code == CODE_64BIT
8273 && !i.prefix[ADDR_PREFIX]
8274 && exp->X_op == O_constant)
8275 {
8276 /* Since displacement is signed extended to 64bit, don't allow
8277 disp32 and turn off disp32s if they are out of range. */
8278 i.types[this_operand].bitfield.disp32 = 0;
8279 if (!fits_in_signed_long (exp->X_add_number))
8280 {
8281 i.types[this_operand].bitfield.disp32s = 0;
8282 if (i.types[this_operand].bitfield.baseindex)
8283 {
8284 as_bad (_("0x%lx out range of signed 32bit displacement"),
8285 (long) exp->X_add_number);
8286 ret = 0;
8287 }
8288 }
8289 }
8290
4c63da97 8291#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8292 else if (exp->X_op != O_constant
8293 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8294 && exp_seg != absolute_section
8295 && exp_seg != text_section
8296 && exp_seg != data_section
8297 && exp_seg != bss_section
8298 && exp_seg != undefined_section
8299 && !bfd_is_com_section (exp_seg))
24eab124 8300 {
d0b47220 8301 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8302 ret = 0;
24eab124 8303 }
252b5132 8304#endif
3956db08 8305
40fb9820
L		 8306 /* Check if this is a displacement only operand. */
8307 bigdisp = i.types[this_operand];
8308 bigdisp.bitfield.disp8 = 0;
8309 bigdisp.bitfield.disp16 = 0;
8310 bigdisp.bitfield.disp32 = 0;
8311 bigdisp.bitfield.disp32s = 0;
8312 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8313 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8314 i.types[this_operand] = operand_type_and (i.types[this_operand],
8315 types);
3956db08 8316
3992d3b7 8317 return ret;
252b5132
RH		 8318}
8319
eecb386c 8320/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8321 Return 1 on success, 0 on a failure. */
8322
252b5132 8323static int
e3bb37b5 8324i386_index_check (const char *operand_string)
252b5132 8325{
fc0763e6 8326 const char *kind = "base/index";
be05d201
L		 8327 enum flag_code addr_mode;
8328
8329 if (i.prefix[ADDR_PREFIX])
8330 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8331 else
8332 {
8333 addr_mode = flag_code;
8334
24eab124 8335#if INFER_ADDR_PREFIX
be05d201
L		 8336 if (i.mem_operands == 0)
8337 {
8338 /* Infer address prefix from the first memory operand. */
8339 const reg_entry *addr_reg = i.base_reg;
8340
8341 if (addr_reg == NULL)
8342 addr_reg = i.index_reg;
eecb386c 8343
be05d201
L		 8344 if (addr_reg)
8345 {
8346 if (addr_reg->reg_num == RegEip
8347 || addr_reg->reg_num == RegEiz
8348 || addr_reg->reg_type.bitfield.reg32)
8349 addr_mode = CODE_32BIT;
8350 else if (flag_code != CODE_64BIT
8351 && addr_reg->reg_type.bitfield.reg16)
8352 addr_mode = CODE_16BIT;
8353
8354 if (addr_mode != flag_code)
8355 {
8356 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8357 i.prefixes += 1;
8358 /* Change the size of any displacement too. At most one
8359 of Disp16 or Disp32 is set.
8360 FIXME. There doesn't seem to be any real need for
8361 separate Disp16 and Disp32 flags. The same goes for
8362 Imm16 and Imm32. Removing them would probably clean
8363 up the code quite a lot. */
8364 if (flag_code != CODE_64BIT
8365 && (i.types[this_operand].bitfield.disp16
8366 || i.types[this_operand].bitfield.disp32))
8367 i.types[this_operand]
8368 = operand_type_xor (i.types[this_operand], disp16_32);
8369 }
8370 }
8371 }
24eab124 8372#endif
be05d201
L		 8373 }
8374
fc0763e6
JB		 8375 if (current_templates->start->opcode_modifier.isstring
8376 && !current_templates->start->opcode_modifier.immext
8377 && (current_templates->end[-1].opcode_modifier.isstring
8378 || i.mem_operands))
8379 {
8380 /* Memory operands of string insns are special in that they only allow
8381 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8382 const reg_entry *expected_reg;
8383 static const char *di_si[][2] =
8384 {
8385 { "esi", "edi" },
8386 { "si", "di" },
8387 { "rsi", "rdi" }
8388 };
8389 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8390
8391 kind = "string address";
8392
8393 if (current_templates->start->opcode_modifier.w)
8394 {
8395 i386_operand_type type = current_templates->end[-1].operand_types[0];
8396
8397 if (!type.bitfield.baseindex
8398 || ((!i.mem_operands != !intel_syntax)
8399 && current_templates->end[-1].operand_types[1]
8400 .bitfield.baseindex))
8401 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8402 expected_reg = hash_find (reg_hash,
8403 di_si[addr_mode][type.bitfield.esseg]);
8404
fc0763e6
JB		 8405 }
8406 else
be05d201 8407 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8408
be05d201
L		 8409 if (i.base_reg != expected_reg
8410 || i.index_reg
fc0763e6 8411 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8412 {
be05d201
L		 8413 /* The second memory operand must have the same size as
8414 the first one. */
8415 if (i.mem_operands
8416 && i.base_reg
8417 && !((addr_mode == CODE_64BIT
8418 && i.base_reg->reg_type.bitfield.reg64)
8419 || (addr_mode == CODE_32BIT
8420 ? i.base_reg->reg_type.bitfield.reg32
8421 : i.base_reg->reg_type.bitfield.reg16)))
8422 goto bad_address;
8423
fc0763e6
JB		 8424 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8425 operand_string,
8426 intel_syntax ? '[' : '(',
8427 register_prefix,
be05d201 8428 expected_reg->reg_name,
fc0763e6 8429 intel_syntax ? ']' : ')');
be05d201 8430 return 1;
fc0763e6 8431 }
be05d201
L		 8432 else
8433 return 1;
8434
8435bad_address:
8436 as_bad (_("`%s' is not a valid %s expression"),
8437 operand_string, kind);
8438 return 0;
3e73aa7c
JH		 8439 }
8440 else
8441 {
be05d201
L		 8442 if (addr_mode != CODE_16BIT)
8443 {
8444 /* 32-bit/64-bit checks. */
8445 if ((i.base_reg
8446 && (addr_mode == CODE_64BIT
8447 ? !i.base_reg->reg_type.bitfield.reg64
8448 : !i.base_reg->reg_type.bitfield.reg32)
8449 && (i.index_reg
8450 || (i.base_reg->reg_num
8451 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8452 || (i.index_reg
8453 && !i.index_reg->reg_type.bitfield.regxmm
8454 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8455 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8456 && ((addr_mode == CODE_64BIT
8457 ? !(i.index_reg->reg_type.bitfield.reg64
8458 || i.index_reg->reg_num == RegRiz)
8459 : !(i.index_reg->reg_type.bitfield.reg32
8460 || i.index_reg->reg_num == RegEiz))
8461 || !i.index_reg->reg_type.bitfield.baseindex)))
8462 goto bad_address;
8463 }
8464 else
3e73aa7c 8465 {
be05d201 8466 /* 16-bit checks. */
3e73aa7c 8467 if ((i.base_reg
40fb9820
L		 8468 && (!i.base_reg->reg_type.bitfield.reg16
8469 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8470 || (i.index_reg
40fb9820
L		 8471 && (!i.index_reg->reg_type.bitfield.reg16
8472 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8473 || !(i.base_reg
8474 && i.base_reg->reg_num < 6
8475 && i.index_reg->reg_num >= 6
8476 && i.log2_scale_factor == 0))))
be05d201 8477 goto bad_address;
3e73aa7c
JH		 8478 }
8479 }
be05d201 8480 return 1;
24eab124 8481}
252b5132 8482
43234a1e
L		 8483/* Handle vector immediates. */
8484
8485static int
8486RC_SAE_immediate (const char *imm_start)
8487{
8488 unsigned int match_found, j;
8489 const char *pstr = imm_start;
8490 expressionS *exp;
8491
8492 if (*pstr != '{')
8493 return 0;
8494
8495 pstr++;
8496 match_found = 0;
8497 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8498 {
8499 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8500 {
8501 if (!i.rounding)
8502 {
8503 rc_op.type = RC_NamesTable[j].type;
8504 rc_op.operand = this_operand;
8505 i.rounding = &rc_op;
8506 }
8507 else
8508 {
8509 as_bad (_("duplicated `%s'"), imm_start);
8510 return 0;
8511 }
8512 pstr += RC_NamesTable[j].len;
8513 match_found = 1;
8514 break;
8515 }
8516 }
8517 if (!match_found)
8518 return 0;
8519
8520 if (*pstr++ != '}')
8521 {
8522 as_bad (_("Missing '}': '%s'"), imm_start);
8523 return 0;
8524 }
8525 /* RC/SAE immediate string should contain nothing more. */;
8526 if (*pstr != 0)
8527 {
8528 as_bad (_("Junk after '}': '%s'"), imm_start);
8529 return 0;
8530 }
8531
8532 exp = &im_expressions[i.imm_operands++];
8533 i.op[this_operand].imms = exp;
8534
8535 exp->X_op = O_constant;
8536 exp->X_add_number = 0;
8537 exp->X_add_symbol = (symbolS *) 0;
8538 exp->X_op_symbol = (symbolS *) 0;
8539
8540 i.types[this_operand].bitfield.imm8 = 1;
8541 return 1;
8542}
8543
fc0763e6 8544/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8545 on error. */
252b5132 8546
252b5132 8547static int
a7619375 8548i386_att_operand (char *operand_string)
252b5132 8549{
af6bdddf
AM		 8550 const reg_entry *r;
8551 char *end_op;
24eab124 8552 char *op_string = operand_string;
252b5132 8553
24eab124 8554 if (is_space_char (*op_string))
252b5132
RH		 8555 ++op_string;
8556
24eab124 8557 /* We check for an absolute prefix (differentiating,
47926f60 8558 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8559 if (*op_string == ABSOLUTE_PREFIX)
8560 {
8561 ++op_string;
8562 if (is_space_char (*op_string))
8563 ++op_string;
40fb9820 8564 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8565 }
252b5132 8566
47926f60 8567 /* Check if operand is a register. */
4d1bb795 8568 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8569 {
40fb9820
L		 8570 i386_operand_type temp;
8571
24eab124
AM		 8572 /* Check for a segment override by searching for ':' after a
8573 segment register. */
8574 op_string = end_op;
8575 if (is_space_char (*op_string))
8576 ++op_string;
40fb9820
L		 8577 if (*op_string == ':'
8578 && (r->reg_type.bitfield.sreg2
8579 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8580 {
8581 switch (r->reg_num)
8582 {
8583 case 0:
8584 i.seg[i.mem_operands] = &es;
8585 break;
8586 case 1:
8587 i.seg[i.mem_operands] = &cs;
8588 break;
8589 case 2:
8590 i.seg[i.mem_operands] = &ss;
8591 break;
8592 case 3:
8593 i.seg[i.mem_operands] = &ds;
8594 break;
8595 case 4:
8596 i.seg[i.mem_operands] = &fs;
8597 break;
8598 case 5:
8599 i.seg[i.mem_operands] = &gs;
8600 break;
8601 }
252b5132 8602
24eab124 8603 /* Skip the ':' and whitespace. */
252b5132
RH		 8604 ++op_string;
8605 if (is_space_char (*op_string))
24eab124 8606 ++op_string;
252b5132 8607
24eab124
AM		 8608 if (!is_digit_char (*op_string)
8609 && !is_identifier_char (*op_string)
8610 && *op_string != '('
8611 && *op_string != ABSOLUTE_PREFIX)
8612 {
8613 as_bad (_("bad memory operand `%s'"), op_string);
8614 return 0;
8615 }
47926f60 8616 /* Handle case of %es:*foo. */
24eab124
AM		 8617 if (*op_string == ABSOLUTE_PREFIX)
8618 {
8619 ++op_string;
8620 if (is_space_char (*op_string))
8621 ++op_string;
40fb9820 8622 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8623 }
8624 goto do_memory_reference;
8625 }
43234a1e
L		 8626
8627 /* Handle vector operations. */
8628 if (*op_string == '{')
8629 {
8630 op_string = check_VecOperations (op_string, NULL);
8631 if (op_string == NULL)
8632 return 0;
8633 }
8634
24eab124
AM		 8635 if (*op_string)
8636 {
d0b47220 8637 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8638 return 0;
8639 }
40fb9820
L		 8640 temp = r->reg_type;
8641 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8642 i.types[this_operand] = operand_type_or (i.types[this_operand],
8643 temp);
7d5e4556 8644 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8645 i.op[this_operand].regs = r;
24eab124
AM		 8646 i.reg_operands++;
8647 }
af6bdddf
AM		 8648 else if (*op_string == REGISTER_PREFIX)
8649 {
8650 as_bad (_("bad register name `%s'"), op_string);
8651 return 0;
8652 }
24eab124 8653 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8654 {
24eab124 8655 ++op_string;
40fb9820 8656 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8657 {
d0b47220 8658 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8659 return 0;
8660 }
8661 if (!i386_immediate (op_string))
8662 return 0;
8663 }
43234a1e
L		 8664 else if (RC_SAE_immediate (operand_string))
8665 {
8666 /* If it is a RC or SAE immediate, do nothing. */
8667 ;
8668 }
24eab124
AM		 8669 else if (is_digit_char (*op_string)
8670 || is_identifier_char (*op_string)
e5cb08ac 8671 || *op_string == '(')
24eab124 8672 {
47926f60 8673 /* This is a memory reference of some sort. */
af6bdddf 8674 char *base_string;
252b5132 8675
47926f60 8676 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8677 char *displacement_string_start;
8678 char *displacement_string_end;
43234a1e 8679 char *vop_start;
252b5132 8680
24eab124 8681 do_memory_reference:
24eab124 8682 if ((i.mem_operands == 1
40fb9820 8683 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8684 || i.mem_operands == 2)
8685 {
8686 as_bad (_("too many memory references for `%s'"),
8687 current_templates->start->name);
8688 return 0;
8689 }
252b5132 8690
24eab124
AM		 8691 /* Check for base index form. We detect the base index form by
8692 looking for an ')' at the end of the operand, searching
8693 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8694 after the '('. */
af6bdddf 8695 base_string = op_string + strlen (op_string);
c3332e24 8696
43234a1e
L		 8697 /* Handle vector operations. */
8698 vop_start = strchr (op_string, '{');
8699 if (vop_start && vop_start < base_string)
8700 {
8701 if (check_VecOperations (vop_start, base_string) == NULL)
8702 return 0;
8703 base_string = vop_start;
8704 }
8705
af6bdddf
AM		 8706 --base_string;
8707 if (is_space_char (*base_string))
8708 --base_string;
252b5132 8709
47926f60 8710 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8711 displacement_string_start = op_string;
8712 displacement_string_end = base_string + 1;
252b5132 8713
24eab124
AM		 8714 if (*base_string == ')')
8715 {
af6bdddf 8716 char *temp_string;
24eab124
AM		 8717 unsigned int parens_balanced = 1;
8718 /* We've already checked that the number of left & right ()'s are
47926f60 8719 equal, so this loop will not be infinite. */
24eab124
AM		 8720 do
8721 {
8722 base_string--;
8723 if (*base_string == ')')
8724 parens_balanced++;
8725 if (*base_string == '(')
8726 parens_balanced--;
8727 }
8728 while (parens_balanced);
c3332e24 8729
af6bdddf 8730 temp_string = base_string;
c3332e24 8731
24eab124 8732 /* Skip past '(' and whitespace. */
252b5132
RH		 8733 ++base_string;
8734 if (is_space_char (*base_string))
24eab124 8735 ++base_string;
252b5132 8736
af6bdddf 8737 if (*base_string == ','
4eed87de
AM		 8738 || ((i.base_reg = parse_register (base_string, &end_op))
8739 != NULL))
252b5132 8740 {
af6bdddf 8741 displacement_string_end = temp_string;
252b5132 8742
40fb9820 8743 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8744
af6bdddf 8745 if (i.base_reg)
24eab124 8746 {
24eab124
AM		 8747 base_string = end_op;
8748 if (is_space_char (*base_string))
8749 ++base_string;
af6bdddf
AM		 8750 }
8751
8752 /* There may be an index reg or scale factor here. */
8753 if (*base_string == ',')
8754 {
8755 ++base_string;
8756 if (is_space_char (*base_string))
8757 ++base_string;
8758
4eed87de
AM		 8759 if ((i.index_reg = parse_register (base_string, &end_op))
8760 != NULL)
24eab124 8761 {
af6bdddf 8762 base_string = end_op;
24eab124
AM		 8763 if (is_space_char (*base_string))
8764 ++base_string;
af6bdddf
AM		 8765 if (*base_string == ',')
8766 {
8767 ++base_string;
8768 if (is_space_char (*base_string))
8769 ++base_string;
8770 }
e5cb08ac 8771 else if (*base_string != ')')
af6bdddf 8772 {
4eed87de
AM		 8773 as_bad (_("expecting `,' or `)' "
8774 "after index register in `%s'"),
af6bdddf
AM		 8775 operand_string);
8776 return 0;
8777 }
24eab124 8778 }
af6bdddf 8779 else if (*base_string == REGISTER_PREFIX)
24eab124 8780 {
f76bf5e0
L		 8781 end_op = strchr (base_string, ',');
8782 if (end_op)
8783 *end_op = '\0';
af6bdddf 8784 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8785 return 0;
8786 }
252b5132 8787
47926f60 8788 /* Check for scale factor. */
551c1ca1 8789 if (*base_string != ')')
af6bdddf 8790 {
551c1ca1
AM		 8791 char *end_scale = i386_scale (base_string);
8792
8793 if (!end_scale)
af6bdddf 8794 return 0;
24eab124 8795
551c1ca1 8796 base_string = end_scale;
af6bdddf
AM		 8797 if (is_space_char (*base_string))
8798 ++base_string;
8799 if (*base_string != ')')
8800 {
4eed87de
AM		 8801 as_bad (_("expecting `)' "
8802 "after scale factor in `%s'"),
af6bdddf
AM		 8803 operand_string);
8804 return 0;
8805 }
8806 }
8807 else if (!i.index_reg)
24eab124 8808 {
4eed87de
AM		 8809 as_bad (_("expecting index register or scale factor "
8810 "after `,'; got '%c'"),
af6bdddf 8811 *base_string);
24eab124
AM		 8812 return 0;
8813 }
8814 }
af6bdddf 8815 else if (*base_string != ')')
24eab124 8816 {
4eed87de
AM		 8817 as_bad (_("expecting `,' or `)' "
8818 "after base register in `%s'"),
af6bdddf 8819 operand_string);
24eab124
AM		 8820 return 0;
8821 }
c3332e24 8822 }
af6bdddf 8823 else if (*base_string == REGISTER_PREFIX)
c3332e24 8824 {
f76bf5e0
L		 8825 end_op = strchr (base_string, ',');
8826 if (end_op)
8827 *end_op = '\0';
af6bdddf 8828 as_bad (_("bad register name `%s'"), base_string);
24eab124 8829 return 0;
c3332e24 8830 }
24eab124
AM		 8831 }
8832
8833 /* If there's an expression beginning the operand, parse it,
8834 assuming displacement_string_start and
8835 displacement_string_end are meaningful. */
8836 if (displacement_string_start != displacement_string_end)
8837 {
8838 if (!i386_displacement (displacement_string_start,
8839 displacement_string_end))
8840 return 0;
8841 }
8842
8843 /* Special case for (%dx) while doing input/output op. */
8844 if (i.base_reg
0dfbf9d7
L		 8845 && operand_type_equal (&i.base_reg->reg_type,
8846 &reg16_inoutportreg)
24eab124
AM		 8847 && i.index_reg == 0
8848 && i.log2_scale_factor == 0
8849 && i.seg[i.mem_operands] == 0
40fb9820 8850 && !operand_type_check (i.types[this_operand], disp))
24eab124 8851 {
65da13b5 8852 i.types[this_operand] = inoutportreg;
24eab124
AM		 8853 return 1;
8854 }
8855
eecb386c
AM		 8856 if (i386_index_check (operand_string) == 0)
8857 return 0;
5c07affc 8858 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 8859 i.mem_operands++;
8860 }
8861 else
ce8a8b2f
AM		 8862 {
8863 /* It's not a memory operand; argh! */
24eab124
AM		 8864 as_bad (_("invalid char %s beginning operand %d `%s'"),
8865 output_invalid (*op_string),
8866 this_operand + 1,
8867 op_string);
8868 return 0;
8869 }
47926f60 8870 return 1; /* Normal return. */
252b5132
RH		 8871}
8872\f
fa94de6b
RM		 8873/* Calculate the maximum variable size (i.e., excluding fr_fix)
8874 that an rs_machine_dependent frag may reach. */
8875
8876unsigned int
8877i386_frag_max_var (fragS *frag)
8878{
8879 /* The only relaxable frags are for jumps.
8880 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8881 gas_assert (frag->fr_type == rs_machine_dependent);
8882 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8883}
8884
ee7fcc42
AM		 8885/* md_estimate_size_before_relax()
8886
8887 Called just before relax() for rs_machine_dependent frags. The x86
8888 assembler uses these frags to handle variable size jump
8889 instructions.
8890
8891 Any symbol that is now undefined will not become defined.
8892 Return the correct fr_subtype in the frag.
8893 Return the initial "guess for variable size of frag" to caller.
8894 The guess is actually the growth beyond the fixed part. Whatever
8895 we do to grow the fixed or variable part contributes to our
8896 returned value. */
8897
252b5132 8898int
7016a5d5 8899md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 8900{
252b5132 8901 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 8902 check for un-relaxable symbols. On an ELF system, we can't relax
8903 an externally visible symbol, because it may be overridden by a
8904 shared library. */
8905 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 8906#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8907 || (IS_ELF
31312f95 8908 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 8909 || S_IS_WEAK (fragP->fr_symbol)
8910 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
8911 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 8912#endif
8913#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 8914 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 8915 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 8916#endif
8917 )
252b5132 8918 {
b98ef147
AM		 8919 /* Symbol is undefined in this segment, or we need to keep a
8920 reloc so that weak symbols can be overridden. */
8921 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 8922 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 8923 unsigned char *opcode;
8924 int old_fr_fix;
f6af82bd 8925
ee7fcc42 8926 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 8927 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 8928 else if (size == 2)
f6af82bd
AM		 8929 reloc_type = BFD_RELOC_16_PCREL;
8930 else
8931 reloc_type = BFD_RELOC_32_PCREL;
252b5132 8932
ee7fcc42
AM		 8933 old_fr_fix = fragP->fr_fix;
8934 opcode = (unsigned char *) fragP->fr_opcode;
8935
fddf5b5b 8936 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 8937 {
fddf5b5b
AM		 8938 case UNCOND_JUMP:
8939 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 8940 opcode[0] = 0xe9;
252b5132 8941 fragP->fr_fix += size;
062cd5e7
AS		 8942 fix_new (fragP, old_fr_fix, size,
8943 fragP->fr_symbol,
8944 fragP->fr_offset, 1,
8945 reloc_type);
252b5132
RH		 8946 break;
8947
fddf5b5b 8948 case COND_JUMP86:
412167cb
AM		 8949 if (size == 2
8950 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 8951 {
8952 /* Negate the condition, and branch past an
8953 unconditional jump. */
8954 opcode[0] ^= 1;
8955 opcode[1] = 3;
8956 /* Insert an unconditional jump. */
8957 opcode[2] = 0xe9;
8958 /* We added two extra opcode bytes, and have a two byte
8959 offset. */
8960 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 8961 fix_new (fragP, old_fr_fix + 2, 2,
8962 fragP->fr_symbol,
8963 fragP->fr_offset, 1,
8964 reloc_type);
fddf5b5b
AM		 8965 break;
8966 }
8967 /* Fall through. */
8968
8969 case COND_JUMP:
412167cb
AM		 8970 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
8971 {
3e02c1cc
AM		 8972 fixS *fixP;
8973
412167cb 8974 fragP->fr_fix += 1;
3e02c1cc
AM		 8975 fixP = fix_new (fragP, old_fr_fix, 1,
8976 fragP->fr_symbol,
8977 fragP->fr_offset, 1,
8978 BFD_RELOC_8_PCREL);
8979 fixP->fx_signed = 1;
412167cb
AM		 8980 break;
8981 }
93c2a809 8982
24eab124 8983 /* This changes the byte-displacement jump 0x7N
fddf5b5b 8984 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 8985 opcode[1] = opcode[0] + 0x10;
f6af82bd 8986 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 8987 /* We've added an opcode byte. */
8988 fragP->fr_fix += 1 + size;
062cd5e7
AS		 8989 fix_new (fragP, old_fr_fix + 1, size,
8990 fragP->fr_symbol,
8991 fragP->fr_offset, 1,
8992 reloc_type);
252b5132 8993 break;
fddf5b5b
AM		 8994
8995 default:
8996 BAD_CASE (fragP->fr_subtype);
8997 break;
252b5132
RH		 8998 }
8999 frag_wane (fragP);
ee7fcc42 9000 return fragP->fr_fix - old_fr_fix;
252b5132 9001 }
93c2a809 9002
93c2a809
AM		 9003 /* Guess size depending on current relax state. Initially the relax
9004 state will correspond to a short jump and we return 1, because
9005 the variable part of the frag (the branch offset) is one byte
9006 long. However, we can relax a section more than once and in that
9007 case we must either set fr_subtype back to the unrelaxed state,
9008 or return the value for the appropriate branch. */
9009 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9010}
9011
47926f60
KH		 9012/* Called after relax() is finished.
9013
9014 In: Address of frag.
9015 fr_type == rs_machine_dependent.
9016 fr_subtype is what the address relaxed to.
9017
9018 Out: Any fixSs and constants are set up.
9019 Caller will turn frag into a ".space 0". */
9020
252b5132 9021void
7016a5d5
TG		 9022md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9023 fragS *fragP)
252b5132 9024{
29b0f896 9025 unsigned char *opcode;
252b5132 9026 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9027 offsetT target_address;
9028 offsetT opcode_address;
252b5132 9029 unsigned int extension = 0;
847f7ad4 9030 offsetT displacement_from_opcode_start;
252b5132
RH		 9031
9032 opcode = (unsigned char *) fragP->fr_opcode;
9033
47926f60 9034 /* Address we want to reach in file space. */
252b5132 9035 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9036
47926f60 9037 /* Address opcode resides at in file space. */
252b5132
RH		 9038 opcode_address = fragP->fr_address + fragP->fr_fix;
9039
47926f60 9040 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9041 displacement_from_opcode_start = target_address - opcode_address;
9042
fddf5b5b 9043 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9044 {
47926f60
KH		 9045 /* Don't have to change opcode. */
9046 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9047 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9048 }
9049 else
9050 {
9051 if (no_cond_jump_promotion
9052 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9053 as_warn_where (fragP->fr_file, fragP->fr_line,
9054 _("long jump required"));
252b5132 9055
fddf5b5b
AM		 9056 switch (fragP->fr_subtype)
9057 {
9058 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9059 extension = 4; /* 1 opcode + 4 displacement */
9060 opcode[0] = 0xe9;
9061 where_to_put_displacement = &opcode[1];
9062 break;
252b5132 9063
fddf5b5b
AM		 9064 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9065 extension = 2; /* 1 opcode + 2 displacement */
9066 opcode[0] = 0xe9;
9067 where_to_put_displacement = &opcode[1];
9068 break;
252b5132 9069
fddf5b5b
AM		 9070 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9071 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9072 extension = 5; /* 2 opcode + 4 displacement */
9073 opcode[1] = opcode[0] + 0x10;
9074 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9075 where_to_put_displacement = &opcode[2];
9076 break;
252b5132 9077
fddf5b5b
AM		 9078 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9079 extension = 3; /* 2 opcode + 2 displacement */
9080 opcode[1] = opcode[0] + 0x10;
9081 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9082 where_to_put_displacement = &opcode[2];
9083 break;
252b5132 9084
fddf5b5b
AM		 9085 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9086 extension = 4;
9087 opcode[0] ^= 1;
9088 opcode[1] = 3;
9089 opcode[2] = 0xe9;
9090 where_to_put_displacement = &opcode[3];
9091 break;
9092
9093 default:
9094 BAD_CASE (fragP->fr_subtype);
9095 break;
9096 }
252b5132 9097 }
fddf5b5b 9098
7b81dfbb
AJ		 9099 /* If size if less then four we are sure that the operand fits,
9100 but if it's 4, then it could be that the displacement is larger
9101 then -/+ 2GB. */
9102 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9103 && object_64bit
9104 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9105 + ((addressT) 1 << 31))
9106 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9107 {
9108 as_bad_where (fragP->fr_file, fragP->fr_line,
9109 _("jump target out of range"));
9110 /* Make us emit 0. */
9111 displacement_from_opcode_start = extension;
9112 }
47926f60 9113 /* Now put displacement after opcode. */
252b5132
RH		 9114 md_number_to_chars ((char *) where_to_put_displacement,
9115 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9116 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9117 fragP->fr_fix += extension;
9118}
9119\f
7016a5d5 9120/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9121 by our caller that we have all the info we need to fix it up.
9122
7016a5d5
TG		 9123 Parameter valP is the pointer to the value of the bits.
9124
252b5132
RH		 9125 On the 386, immediates, displacements, and data pointers are all in
9126 the same (little-endian) format, so we don't need to care about which
9127 we are handling. */
9128
94f592af 9129void
7016a5d5 9130md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9131{
94f592af 9132 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9133 valueT value = *valP;
252b5132 9134
f86103b7 9135#if !defined (TE_Mach)
93382f6d
AM		 9136 if (fixP->fx_pcrel)
9137 {
9138 switch (fixP->fx_r_type)
9139 {
5865bb77
ILT		 9140 default:
9141 break;
9142
d6ab8113
JB		 9143 case BFD_RELOC_64:
9144 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9145 break;
93382f6d 9146 case BFD_RELOC_32:
ae8887b5 9147 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9148 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9149 break;
9150 case BFD_RELOC_16:
9151 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9152 break;
9153 case BFD_RELOC_8:
9154 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9155 break;
9156 }
9157 }
252b5132 9158
a161fe53 9159 if (fixP->fx_addsy != NULL
31312f95 9160 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9161 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9162 || fixP->fx_r_type == BFD_RELOC_16_PCREL
c3320543
L		 9163 || fixP->fx_r_type == BFD_RELOC_8_PCREL
9164 || fixP->fx_r_type == BFD_RELOC_X86_64_PC32_BND)
31312f95 9165 && !use_rela_relocations)
252b5132 9166 {
31312f95
AM		 9167 /* This is a hack. There should be a better way to handle this.
9168 This covers for the fact that bfd_install_relocation will
9169 subtract the current location (for partial_inplace, PC relative
9170 relocations); see more below. */
252b5132 9171#ifndef OBJ_AOUT
718ddfc0 9172 if (IS_ELF
252b5132
RH		 9173#ifdef TE_PE
9174 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9175#endif
9176 )
9177 value += fixP->fx_where + fixP->fx_frag->fr_address;
9178#endif
9179#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9180 if (IS_ELF)
252b5132 9181 {
6539b54b 9182 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9183
6539b54b 9184 if ((sym_seg == seg
2f66722d 9185 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9186 && sym_seg != absolute_section))
af65af87 9187 && !generic_force_reloc (fixP))
2f66722d
AM		 9188 {
9189 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9190 bfd_install_relocation subtracts them out again. I think
9191 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9192 it. FIXME. */
9193 value += fixP->fx_where + fixP->fx_frag->fr_address;
9194 }
252b5132
RH		 9195 }
9196#endif
9197#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9198 /* For some reason, the PE format does not store a
9199 section address offset for a PC relative symbol. */
9200 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9201 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9202 value += md_pcrel_from (fixP);
9203#endif
9204 }
fbeb56a4 9205#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9206 if (fixP->fx_addsy != NULL
9207 && S_IS_WEAK (fixP->fx_addsy)
9208 /* PR 16858: Do not modify weak function references. */
9209 && ! fixP->fx_pcrel)
fbeb56a4 9210 {
296a8689
NC		 9211#if !defined (TE_PEP)
9212 /* For x86 PE weak function symbols are neither PC-relative
9213 nor do they set S_IS_FUNCTION. So the only reliable way
9214 to detect them is to check the flags of their containing
9215 section. */
9216 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9217 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9218 ;
9219 else
9220#endif
fbeb56a4
DK		 9221 value -= S_GET_VALUE (fixP->fx_addsy);
9222 }
9223#endif
252b5132
RH		 9224
9225 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9226 and we must not disappoint it. */
252b5132 9227#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9228 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9229 switch (fixP->fx_r_type)
9230 {
9231 case BFD_RELOC_386_PLT32:
3e73aa7c 9232 case BFD_RELOC_X86_64_PLT32:
c3320543 9233 case BFD_RELOC_X86_64_PLT32_BND:
47926f60
KH		 9234 /* Make the jump instruction point to the address of the operand. At
9235 runtime we merely add the offset to the actual PLT entry. */
9236 value = -4;
9237 break;
31312f95 9238
13ae64f3
JJ		 9239 case BFD_RELOC_386_TLS_GD:
9240 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9241 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9242 case BFD_RELOC_386_TLS_IE:
9243 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9244 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9245 case BFD_RELOC_X86_64_TLSGD:
9246 case BFD_RELOC_X86_64_TLSLD:
9247 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9248 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9249 value = 0; /* Fully resolved at runtime. No addend. */
9250 /* Fallthrough */
9251 case BFD_RELOC_386_TLS_LE:
9252 case BFD_RELOC_386_TLS_LDO_32:
9253 case BFD_RELOC_386_TLS_LE_32:
9254 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9255 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9256 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9257 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9258 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9259 break;
9260
67a4f2b7
AO		 9261 case BFD_RELOC_386_TLS_DESC_CALL:
9262 case BFD_RELOC_X86_64_TLSDESC_CALL:
9263 value = 0; /* Fully resolved at runtime. No addend. */
9264 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9265 fixP->fx_done = 0;
9266 return;
9267
00f7efb6
JJ		 9268 case BFD_RELOC_386_GOT32:
9269 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 9270 value = 0; /* Fully resolved at runtime. No addend. */
9271 break;
47926f60
KH		 9272
9273 case BFD_RELOC_VTABLE_INHERIT:
9274 case BFD_RELOC_VTABLE_ENTRY:
9275 fixP->fx_done = 0;
94f592af 9276 return;
47926f60
KH		 9277
9278 default:
9279 break;
9280 }
9281#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9282 *valP = value;
f86103b7 9283#endif /* !defined (TE_Mach) */
3e73aa7c 9284
3e73aa7c 9285 /* Are we finished with this relocation now? */
c6682705 9286 if (fixP->fx_addsy == NULL)
3e73aa7c 9287 fixP->fx_done = 1;
fbeb56a4
DK		 9288#if defined (OBJ_COFF) && defined (TE_PE)
9289 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9290 {
9291 fixP->fx_done = 0;
9292 /* Remember value for tc_gen_reloc. */
9293 fixP->fx_addnumber = value;
9294 /* Clear out the frag for now. */
9295 value = 0;
9296 }
9297#endif
3e73aa7c
JH		 9298 else if (use_rela_relocations)
9299 {
9300 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9301 /* Remember value for tc_gen_reloc. */
9302 fixP->fx_addnumber = value;
3e73aa7c
JH		 9303 value = 0;
9304 }
f86103b7 9305
94f592af 9306 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9307}
252b5132 9308\f
252b5132 9309char *
499ac353 9310md_atof (int type, char *litP, int *sizeP)
252b5132 9311{
499ac353
NC		 9312 /* This outputs the LITTLENUMs in REVERSE order;
9313 in accord with the bigendian 386. */
9314 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9315}
9316\f
2d545b82 9317static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9318
252b5132 9319static char *
e3bb37b5 9320output_invalid (int c)
252b5132 9321{
3882b010 9322 if (ISPRINT (c))
f9f21a03
L		 9323 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9324 "'%c'", c);
252b5132 9325 else
f9f21a03 9326 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9327 "(0x%x)", (unsigned char) c);
252b5132
RH		 9328 return output_invalid_buf;
9329}
9330
af6bdddf 9331/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9332
9333static const reg_entry *
4d1bb795 9334parse_real_register (char *reg_string, char **end_op)
252b5132 9335{
af6bdddf
AM		 9336 char *s = reg_string;
9337 char *p;
252b5132
RH		 9338 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9339 const reg_entry *r;
9340
9341 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9342 if (*s == REGISTER_PREFIX)
9343 ++s;
9344
9345 if (is_space_char (*s))
9346 ++s;
9347
9348 p = reg_name_given;
af6bdddf 9349 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9350 {
9351 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9352 return (const reg_entry *) NULL;
9353 s++;
252b5132
RH		 9354 }
9355
6588847e
DN		 9356 /* For naked regs, make sure that we are not dealing with an identifier.
9357 This prevents confusing an identifier like `eax_var' with register
9358 `eax'. */
9359 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9360 return (const reg_entry *) NULL;
9361
af6bdddf 9362 *end_op = s;
252b5132
RH		 9363
9364 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9365
5f47d35b 9366 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9367 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9368 {
5f47d35b
AM		 9369 if (is_space_char (*s))
9370 ++s;
9371 if (*s == '(')
9372 {
af6bdddf 9373 ++s;
5f47d35b
AM		 9374 if (is_space_char (*s))
9375 ++s;
9376 if (*s >= '0' && *s <= '7')
9377 {
db557034 9378 int fpr = *s - '0';
af6bdddf 9379 ++s;
5f47d35b
AM		 9380 if (is_space_char (*s))
9381 ++s;
9382 if (*s == ')')
9383 {
9384 *end_op = s + 1;
1e9cc1c2 9385 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9386 know (r);
9387 return r + fpr;
5f47d35b 9388 }
5f47d35b 9389 }
47926f60 9390 /* We have "%st(" then garbage. */
5f47d35b
AM		 9391 return (const reg_entry *) NULL;
9392 }
9393 }
9394
a60de03c
JB		 9395 if (r == NULL || allow_pseudo_reg)
9396 return r;
9397
0dfbf9d7 9398 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9399 return (const reg_entry *) NULL;
9400
192dc9c6
JB		 9401 if ((r->reg_type.bitfield.reg32
9402 || r->reg_type.bitfield.sreg3
9403 || r->reg_type.bitfield.control
9404 || r->reg_type.bitfield.debug
9405 || r->reg_type.bitfield.test)
9406 && !cpu_arch_flags.bitfield.cpui386)
9407 return (const reg_entry *) NULL;
9408
309d3373
JB		 9409 if (r->reg_type.bitfield.floatreg
9410 && !cpu_arch_flags.bitfield.cpu8087
9411 && !cpu_arch_flags.bitfield.cpu287
9412 && !cpu_arch_flags.bitfield.cpu387)
9413 return (const reg_entry *) NULL;
9414
192dc9c6
JB		 9415 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9416 return (const reg_entry *) NULL;
9417
9418 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9419 return (const reg_entry *) NULL;
9420
40f12533
L		 9421 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9422 return (const reg_entry *) NULL;
9423
43234a1e
L		 9424 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9425 && !cpu_arch_flags.bitfield.cpuavx512f)
9426 return (const reg_entry *) NULL;
9427
db51cc60 9428 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9429 if (!allow_index_reg
db51cc60
L		 9430 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9431 return (const reg_entry *) NULL;
9432
43234a1e
L		 9433 /* Upper 16 vector register is only available with VREX in 64bit
9434 mode. */
9435 if ((r->reg_flags & RegVRex))
9436 {
9437 if (!cpu_arch_flags.bitfield.cpuvrex
9438 || flag_code != CODE_64BIT)
9439 return (const reg_entry *) NULL;
9440
9441 i.need_vrex = 1;
9442 }
9443
a60de03c
JB		 9444 if (((r->reg_flags & (RegRex64 | RegRex))
9445 || r->reg_type.bitfield.reg64)
40fb9820 9446 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9447 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9448 && flag_code != CODE_64BIT)
20f0a1fc 9449 return (const reg_entry *) NULL;
1ae00879 9450
b7240065
JB		 9451 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9452 return (const reg_entry *) NULL;
9453
252b5132
RH		 9454 return r;
9455}
4d1bb795
JB		 9456
9457/* REG_STRING starts *before* REGISTER_PREFIX. */
9458
9459static const reg_entry *
9460parse_register (char *reg_string, char **end_op)
9461{
9462 const reg_entry *r;
9463
9464 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9465 r = parse_real_register (reg_string, end_op);
9466 else
9467 r = NULL;
9468 if (!r)
9469 {
9470 char *save = input_line_pointer;
9471 char c;
9472 symbolS *symbolP;
9473
9474 input_line_pointer = reg_string;
9475 c = get_symbol_end ();
9476 symbolP = symbol_find (reg_string);
9477 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9478 {
9479 const expressionS *e = symbol_get_value_expression (symbolP);
9480
0398aac5 9481 know (e->X_op == O_register);
4eed87de 9482 know (e->X_add_number >= 0
c3fe08fa 9483 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9484 r = i386_regtab + e->X_add_number;
d3bb6b49
IT		 9485 if ((r->reg_flags & RegVRex))
9486 i.need_vrex = 1;
4d1bb795
JB		 9487 *end_op = input_line_pointer;
9488 }
9489 *input_line_pointer = c;
9490 input_line_pointer = save;
9491 }
9492 return r;
9493}
9494
9495int
9496i386_parse_name (char *name, expressionS *e, char *nextcharP)
9497{
9498 const reg_entry *r;
9499 char *end = input_line_pointer;
9500
9501 *end = *nextcharP;
9502 r = parse_register (name, &input_line_pointer);
9503 if (r && end <= input_line_pointer)
9504 {
9505 *nextcharP = *input_line_pointer;
9506 *input_line_pointer = 0;
9507 e->X_op = O_register;
9508 e->X_add_number = r - i386_regtab;
9509 return 1;
9510 }
9511 input_line_pointer = end;
9512 *end = 0;
ee86248c 9513 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9514}
9515
9516void
9517md_operand (expressionS *e)
9518{
ee86248c
JB		 9519 char *end;
9520 const reg_entry *r;
4d1bb795 9521
ee86248c
JB		 9522 switch (*input_line_pointer)
9523 {
9524 case REGISTER_PREFIX:
9525 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9526 if (r)
9527 {
9528 e->X_op = O_register;
9529 e->X_add_number = r - i386_regtab;
9530 input_line_pointer = end;
9531 }
ee86248c
JB		 9532 break;
9533
9534 case '[':
9c2799c2 9535 gas_assert (intel_syntax);
ee86248c
JB		 9536 end = input_line_pointer++;
9537 expression (e);
9538 if (*input_line_pointer == ']')
9539 {
9540 ++input_line_pointer;
9541 e->X_op_symbol = make_expr_symbol (e);
9542 e->X_add_symbol = NULL;
9543 e->X_add_number = 0;
9544 e->X_op = O_index;
9545 }
9546 else
9547 {
9548 e->X_op = O_absent;
9549 input_line_pointer = end;
9550 }
9551 break;
4d1bb795
JB		 9552 }
9553}
9554
252b5132 9555\f
4cc782b5 9556#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9557const char *md_shortopts = "kVQ:sqn";
252b5132 9558#else
12b55ccc 9559const char *md_shortopts = "qn";
252b5132 9560#endif
6e0b89ee 9561
3e73aa7c 9562#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9563#define OPTION_64 (OPTION_MD_BASE + 1)
9564#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9565#define OPTION_MARCH (OPTION_MD_BASE + 3)
9566#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9567#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9568#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9569#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9570#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9571#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9572#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9573#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9574#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9575#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9576#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9577#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9578#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9579#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9580#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
a5094208 9581#define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9582#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
b3b91714 9583
99ad8390
NC		 9584struct option md_longopts[] =
9585{
3e73aa7c 9586 {"32", no_argument, NULL, OPTION_32},
321098a5 9587#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9588 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9589 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9590#endif
9591#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9592 {"x32", no_argument, NULL, OPTION_X32},
6e0b89ee 9593#endif
b3b91714 9594 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9595 {"march", required_argument, NULL, OPTION_MARCH},
9596 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9597 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9598 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9599 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9600 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9601 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9602 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9603 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9604 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9605 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9606 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9607 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9608 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9609# if defined (TE_PE) || defined (TE_PEP)
9610 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9611#endif
a5094208 9612 {"momit-lock-prefix", required_argument, NULL, OPTION_OMIT_LOCK_PREFIX},
d3d3c6db 9613 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
252b5132
RH		 9614 {NULL, no_argument, NULL, 0}
9615};
9616size_t md_longopts_size = sizeof (md_longopts);
9617
9618int
9103f4f4 9619md_parse_option (int c, char *arg)
252b5132 9620{
91d6fa6a 9621 unsigned int j;
6305a203 9622 char *arch, *next;
9103f4f4 9623
252b5132
RH		 9624 switch (c)
9625 {
12b55ccc
L		 9626 case 'n':
9627 optimize_align_code = 0;
9628 break;
9629
a38cf1db
AM		 9630 case 'q':
9631 quiet_warnings = 1;
252b5132
RH		 9632 break;
9633
9634#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9635 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9636 should be emitted or not. FIXME: Not implemented. */
9637 case 'Q':
252b5132
RH		 9638 break;
9639
9640 /* -V: SVR4 argument to print version ID. */
9641 case 'V':
9642 print_version_id ();
9643 break;
9644
a38cf1db
AM		 9645 /* -k: Ignore for FreeBSD compatibility. */
9646 case 'k':
252b5132 9647 break;
4cc782b5
ILT		 9648
9649 case 's':
9650 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9651 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9652 break;
99ad8390 9653#endif
321098a5 9654#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9655 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9656 case OPTION_64:
9657 {
9658 const char **list, **l;
9659
3e73aa7c
JH		 9660 list = bfd_target_list ();
9661 for (l = list; *l != NULL; l++)
8620418b 9662 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9663 || strcmp (*l, "coff-x86-64") == 0
9664 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9665 || strcmp (*l, "pei-x86-64") == 0
9666 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9667 {
9668 default_arch = "x86_64";
9669 break;
9670 }
3e73aa7c 9671 if (*l == NULL)
2b5d6a91 9672 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9673 free (list);
9674 }
9675 break;
9676#endif
252b5132 9677
351f65ca 9678#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9679 case OPTION_X32:
351f65ca
L		 9680 if (IS_ELF)
9681 {
9682 const char **list, **l;
9683
9684 list = bfd_target_list ();
9685 for (l = list; *l != NULL; l++)
9686 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9687 {
9688 default_arch = "x86_64:32";
9689 break;
9690 }
9691 if (*l == NULL)
2b5d6a91 9692 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9693 free (list);
9694 }
9695 else
9696 as_fatal (_("32bit x86_64 is only supported for ELF"));
9697 break;
9698#endif
9699
6e0b89ee
AM		 9700 case OPTION_32:
9701 default_arch = "i386";
9702 break;
9703
b3b91714
AM		 9704 case OPTION_DIVIDE:
9705#ifdef SVR4_COMMENT_CHARS
9706 {
9707 char *n, *t;
9708 const char *s;
9709
9710 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
9711 t = n;
9712 for (s = i386_comment_chars; *s != '\0'; s++)
9713 if (*s != '/')
9714 *t++ = *s;
9715 *t = '\0';
9716 i386_comment_chars = n;
9717 }
9718#endif
9719 break;
9720
9103f4f4 9721 case OPTION_MARCH:
6305a203
L		 9722 arch = xstrdup (arg);
9723 do
9103f4f4 9724 {
6305a203 9725 if (*arch == '.')
2b5d6a91 9726 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9727 next = strchr (arch, '+');
9728 if (next)
9729 *next++ = '\0';
91d6fa6a 9730 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9731 {
91d6fa6a 9732 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9733 {
6305a203 9734 /* Processor. */
1ded5609
JB		 9735 if (! cpu_arch[j].flags.bitfield.cpui386)
9736 continue;
9737
91d6fa6a 9738 cpu_arch_name = cpu_arch[j].name;
6305a203 9739 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9740 cpu_arch_flags = cpu_arch[j].flags;
9741 cpu_arch_isa = cpu_arch[j].type;
9742 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9743 if (!cpu_arch_tune_set)
9744 {
9745 cpu_arch_tune = cpu_arch_isa;
9746 cpu_arch_tune_flags = cpu_arch_isa_flags;
9747 }
9748 break;
9749 }
91d6fa6a
NC		 9750 else if (*cpu_arch [j].name == '.'
9751 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9752 {
9753 /* ISA entension. */
9754 i386_cpu_flags flags;
309d3373 9755
49021df2 9756 if (!cpu_arch[j].negated)
309d3373 9757 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 9758 cpu_arch[j].flags);
309d3373
JB		 9759 else
9760 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 9761 cpu_arch[j].flags);
0dfbf9d7 9762 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 9763 {
9764 if (cpu_sub_arch_name)
9765 {
9766 char *name = cpu_sub_arch_name;
9767 cpu_sub_arch_name = concat (name,
91d6fa6a 9768 cpu_arch[j].name,
1bf57e9f 9769 (const char *) NULL);
6305a203
L		 9770 free (name);
9771 }
9772 else
91d6fa6a 9773 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 9774 cpu_arch_flags = flags;
a586129e 9775 cpu_arch_isa_flags = flags;
6305a203
L		 9776 }
9777 break;
ccc9c027 9778 }
9103f4f4 9779 }
6305a203 9780
91d6fa6a 9781 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9782 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9783
9784 arch = next;
9103f4f4 9785 }
6305a203 9786 while (next != NULL );
9103f4f4
L		 9787 break;
9788
9789 case OPTION_MTUNE:
9790 if (*arg == '.')
2b5d6a91 9791 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 9792 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9793 {
91d6fa6a 9794 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 9795 {
ccc9c027 9796 cpu_arch_tune_set = 1;
91d6fa6a
NC		 9797 cpu_arch_tune = cpu_arch [j].type;
9798 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 9799 break;
9800 }
9801 }
91d6fa6a 9802 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9803 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 9804 break;
9805
1efbbeb4
L		 9806 case OPTION_MMNEMONIC:
9807 if (strcasecmp (arg, "att") == 0)
9808 intel_mnemonic = 0;
9809 else if (strcasecmp (arg, "intel") == 0)
9810 intel_mnemonic = 1;
9811 else
2b5d6a91 9812 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 9813 break;
9814
9815 case OPTION_MSYNTAX:
9816 if (strcasecmp (arg, "att") == 0)
9817 intel_syntax = 0;
9818 else if (strcasecmp (arg, "intel") == 0)
9819 intel_syntax = 1;
9820 else
2b5d6a91 9821 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 9822 break;
9823
9824 case OPTION_MINDEX_REG:
9825 allow_index_reg = 1;
9826 break;
9827
9828 case OPTION_MNAKED_REG:
9829 allow_naked_reg = 1;
9830 break;
9831
9832 case OPTION_MOLD_GCC:
9833 old_gcc = 1;
1efbbeb4
L		 9834 break;
9835
c0f3af97
L		 9836 case OPTION_MSSE2AVX:
9837 sse2avx = 1;
9838 break;
9839
daf50ae7
L		 9840 case OPTION_MSSE_CHECK:
9841 if (strcasecmp (arg, "error") == 0)
7bab8ab5 9842 sse_check = check_error;
daf50ae7 9843 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 9844 sse_check = check_warning;
daf50ae7 9845 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 9846 sse_check = check_none;
daf50ae7 9847 else
2b5d6a91 9848 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 9849 break;
9850
7bab8ab5
JB		 9851 case OPTION_MOPERAND_CHECK:
9852 if (strcasecmp (arg, "error") == 0)
9853 operand_check = check_error;
9854 else if (strcasecmp (arg, "warning") == 0)
9855 operand_check = check_warning;
9856 else if (strcasecmp (arg, "none") == 0)
9857 operand_check = check_none;
9858 else
9859 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
9860 break;
9861
539f890d
L		 9862 case OPTION_MAVXSCALAR:
9863 if (strcasecmp (arg, "128") == 0)
9864 avxscalar = vex128;
9865 else if (strcasecmp (arg, "256") == 0)
9866 avxscalar = vex256;
9867 else
2b5d6a91 9868 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 9869 break;
9870
7e8b059b
L		 9871 case OPTION_MADD_BND_PREFIX:
9872 add_bnd_prefix = 1;
9873 break;
9874
43234a1e
L		 9875 case OPTION_MEVEXLIG:
9876 if (strcmp (arg, "128") == 0)
9877 evexlig = evexl128;
9878 else if (strcmp (arg, "256") == 0)
9879 evexlig = evexl256;
9880 else if (strcmp (arg, "512") == 0)
9881 evexlig = evexl512;
9882 else
9883 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
9884 break;
9885
d3d3c6db
IT		 9886 case OPTION_MEVEXRCIG:
9887 if (strcmp (arg, "rne") == 0)
9888 evexrcig = rne;
9889 else if (strcmp (arg, "rd") == 0)
9890 evexrcig = rd;
9891 else if (strcmp (arg, "ru") == 0)
9892 evexrcig = ru;
9893 else if (strcmp (arg, "rz") == 0)
9894 evexrcig = rz;
9895 else
9896 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
9897 break;
9898
43234a1e
L		 9899 case OPTION_MEVEXWIG:
9900 if (strcmp (arg, "0") == 0)
9901 evexwig = evexw0;
9902 else if (strcmp (arg, "1") == 0)
9903 evexwig = evexw1;
9904 else
9905 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
9906 break;
9907
167ad85b
TG		 9908# if defined (TE_PE) || defined (TE_PEP)
9909 case OPTION_MBIG_OBJ:
9910 use_big_obj = 1;
9911 break;
9912#endif
9913
a5094208 9914 case OPTION_OMIT_LOCK_PREFIX:
d022bddd
IT		 9915 if (strcasecmp (arg, "yes") == 0)
9916 omit_lock_prefix = 1;
9917 else if (strcasecmp (arg, "no") == 0)
9918 omit_lock_prefix = 0;
9919 else
9920 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
9921 break;
9922
252b5132
RH		 9923 default:
9924 return 0;
9925 }
9926 return 1;
9927}
9928
8a2c8fef
L		 9929#define MESSAGE_TEMPLATE \
9930" "
9931
9932static void
1ded5609 9933show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 9934{
9935 static char message[] = MESSAGE_TEMPLATE;
9936 char *start = message + 27;
9937 char *p;
9938 int size = sizeof (MESSAGE_TEMPLATE);
9939 int left;
9940 const char *name;
9941 int len;
9942 unsigned int j;
9943
9944 p = start;
9945 left = size - (start - message);
9946 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9947 {
9948 /* Should it be skipped? */
9949 if (cpu_arch [j].skip)
9950 continue;
9951
9952 name = cpu_arch [j].name;
9953 len = cpu_arch [j].len;
9954 if (*name == '.')
9955 {
9956 /* It is an extension. Skip if we aren't asked to show it. */
9957 if (ext)
9958 {
9959 name++;
9960 len--;
9961 }
9962 else
9963 continue;
9964 }
9965 else if (ext)
9966 {
9967 /* It is an processor. Skip if we show only extension. */
9968 continue;
9969 }
1ded5609
JB		 9970 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
9971 {
9972 /* It is an impossible processor - skip. */
9973 continue;
9974 }
8a2c8fef
L		 9975
9976 /* Reserve 2 spaces for ", " or ",\0" */
9977 left -= len + 2;
9978
9979 /* Check if there is any room. */
9980 if (left >= 0)
9981 {
9982 if (p != start)
9983 {
9984 *p++ = ',';
9985 *p++ = ' ';
9986 }
9987 p = mempcpy (p, name, len);
9988 }
9989 else
9990 {
9991 /* Output the current message now and start a new one. */
9992 *p++ = ',';
9993 *p = '\0';
9994 fprintf (stream, "%s\n", message);
9995 p = start;
9996 left = size - (start - message) - len - 2;
8d63c93e 9997
8a2c8fef
L		 9998 gas_assert (left >= 0);
9999
10000 p = mempcpy (p, name, len);
10001 }
10002 }
10003
10004 *p = '\0';
10005 fprintf (stream, "%s\n", message);
10006}
10007
252b5132 10008void
8a2c8fef 10009md_show_usage (FILE *stream)
252b5132 10010{
4cc782b5
ILT		 10011#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10012 fprintf (stream, _("\
a38cf1db
AM		 10013 -Q ignored\n\
10014 -V print assembler version number\n\
b3b91714
AM		 10015 -k ignored\n"));
10016#endif
10017 fprintf (stream, _("\
12b55ccc 10018 -n Do not optimize code alignment\n\
b3b91714
AM		 10019 -q quieten some warnings\n"));
10020#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10021 fprintf (stream, _("\
a38cf1db 10022 -s ignored\n"));
b3b91714 10023#endif
321098a5
L		 10024#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10025 || defined (TE_PE) || defined (TE_PEP))
751d281c 10026 fprintf (stream, _("\
570561f7 10027 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10028#endif
b3b91714
AM		 10029#ifdef SVR4_COMMENT_CHARS
10030 fprintf (stream, _("\
10031 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10032#else
10033 fprintf (stream, _("\
b3b91714 10034 --divide ignored\n"));
4cc782b5 10035#endif
9103f4f4 10036 fprintf (stream, _("\
6305a203 10037 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10038 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10039 show_arch (stream, 0, 1);
8a2c8fef
L		 10040 fprintf (stream, _("\
10041 EXTENSION is combination of:\n"));
1ded5609 10042 show_arch (stream, 1, 0);
6305a203 10043 fprintf (stream, _("\
8a2c8fef 10044 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10045 show_arch (stream, 0, 0);
ba104c83 10046 fprintf (stream, _("\
c0f3af97
L		 10047 -msse2avx encode SSE instructions with VEX prefix\n"));
10048 fprintf (stream, _("\
daf50ae7
L		 10049 -msse-check=[none|error|warning]\n\
10050 check SSE instructions\n"));
10051 fprintf (stream, _("\
7bab8ab5
JB		 10052 -moperand-check=[none|error|warning]\n\
10053 check operand combinations for validity\n"));
10054 fprintf (stream, _("\
539f890d
L		 10055 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10056 length\n"));
10057 fprintf (stream, _("\
43234a1e
L		 10058 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10059 length\n"));
10060 fprintf (stream, _("\
10061 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10062 for EVEX.W bit ignored instructions\n"));
10063 fprintf (stream, _("\
d3d3c6db
IT		 10064 -mevexrcig=[rne|rd|ru|rz]\n\
10065 encode EVEX instructions with specific EVEX.RC value\n\
10066 for SAE-only ignored instructions\n"));
10067 fprintf (stream, _("\
ba104c83
L		 10068 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10069 fprintf (stream, _("\
10070 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10071 fprintf (stream, _("\
10072 -mindex-reg support pseudo index registers\n"));
10073 fprintf (stream, _("\
10074 -mnaked-reg don't require `%%' prefix for registers\n"));
10075 fprintf (stream, _("\
10076 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10077 fprintf (stream, _("\
10078 -madd-bnd-prefix add BND prefix for all valid branches\n"));
167ad85b
TG		 10079# if defined (TE_PE) || defined (TE_PEP)
10080 fprintf (stream, _("\
10081 -mbig-obj generate big object files\n"));
10082#endif
d022bddd
IT		 10083 fprintf (stream, _("\
10084 -momit-lock-prefix=[no|yes]\n\
10085 strip all lock prefixes\n"));
252b5132
RH		 10086}
10087
3e73aa7c 10088#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10089 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10090 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10091
10092/* Pick the target format to use. */
10093
47926f60 10094const char *
e3bb37b5 10095i386_target_format (void)
252b5132 10096{
351f65ca
L		 10097 if (!strncmp (default_arch, "x86_64", 6))
10098 {
10099 update_code_flag (CODE_64BIT, 1);
10100 if (default_arch[6] == '\0')
7f56bc95 10101 x86_elf_abi = X86_64_ABI;
351f65ca 10102 else
7f56bc95 10103 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10104 }
3e73aa7c 10105 else if (!strcmp (default_arch, "i386"))
78f12dd3 10106 update_code_flag (CODE_32BIT, 1);
3e73aa7c 10107 else
2b5d6a91 10108 as_fatal (_("unknown architecture"));
89507696
JB		 10109
10110 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10111 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10112 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10113 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10114
252b5132
RH		 10115 switch (OUTPUT_FLAVOR)
10116 {
9384f2ff 10117#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10118 case bfd_target_aout_flavour:
47926f60 10119 return AOUT_TARGET_FORMAT;
4c63da97 10120#endif
9384f2ff
AM		 10121#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10122# if defined (TE_PE) || defined (TE_PEP)
10123 case bfd_target_coff_flavour:
167ad85b
TG		 10124 if (flag_code == CODE_64BIT)
10125 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10126 else
10127 return "pe-i386";
9384f2ff 10128# elif defined (TE_GO32)
0561d57c
JK		 10129 case bfd_target_coff_flavour:
10130 return "coff-go32";
9384f2ff 10131# else
252b5132
RH		 10132 case bfd_target_coff_flavour:
10133 return "coff-i386";
9384f2ff 10134# endif
4c63da97 10135#endif
3e73aa7c 10136#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10137 case bfd_target_elf_flavour:
3e73aa7c 10138 {
351f65ca
L		 10139 const char *format;
10140
10141 switch (x86_elf_abi)
4fa24527 10142 {
351f65ca
L		 10143 default:
10144 format = ELF_TARGET_FORMAT;
10145 break;
7f56bc95 10146 case X86_64_ABI:
351f65ca 10147 use_rela_relocations = 1;
4fa24527 10148 object_64bit = 1;
351f65ca
L		 10149 format = ELF_TARGET_FORMAT64;
10150 break;
7f56bc95 10151 case X86_64_X32_ABI:
4fa24527 10152 use_rela_relocations = 1;
351f65ca 10153 object_64bit = 1;
862be3fb 10154 disallow_64bit_reloc = 1;
351f65ca
L		 10155 format = ELF_TARGET_FORMAT32;
10156 break;
4fa24527 10157 }
3632d14b 10158 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10159 {
7f56bc95 10160 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10161 as_fatal (_("Intel L1OM is 64bit only"));
10162 return ELF_TARGET_L1OM_FORMAT;
10163 }
7a9068fe
L		 10164 if (cpu_arch_isa == PROCESSOR_K1OM)
10165 {
10166 if (x86_elf_abi != X86_64_ABI)
10167 as_fatal (_("Intel K1OM is 64bit only"));
10168 return ELF_TARGET_K1OM_FORMAT;
10169 }
8a9036a4 10170 else
351f65ca 10171 return format;
3e73aa7c 10172 }
e57f8c65
TG		 10173#endif
10174#if defined (OBJ_MACH_O)
10175 case bfd_target_mach_o_flavour:
d382c579
TG		 10176 if (flag_code == CODE_64BIT)
10177 {
10178 use_rela_relocations = 1;
10179 object_64bit = 1;
10180 return "mach-o-x86-64";
10181 }
10182 else
10183 return "mach-o-i386";
4c63da97 10184#endif
252b5132
RH		 10185 default:
10186 abort ();
10187 return NULL;
10188 }
10189}
10190
47926f60 10191#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 10192
10193#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 10194void
10195i386_elf_emit_arch_note (void)
a847613f 10196{
718ddfc0 10197 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 10198 {
10199 char *p;
10200 asection *seg = now_seg;
10201 subsegT subseg = now_subseg;
10202 Elf_Internal_Note i_note;
10203 Elf_External_Note e_note;
10204 asection *note_secp;
10205 int len;
10206
10207 /* Create the .note section. */
10208 note_secp = subseg_new (".note", 0);
10209 bfd_set_section_flags (stdoutput,
10210 note_secp,
10211 SEC_HAS_CONTENTS | SEC_READONLY);
10212
10213 /* Process the arch string. */
10214 len = strlen (cpu_arch_name);
10215
10216 i_note.namesz = len + 1;
10217 i_note.descsz = 0;
10218 i_note.type = NT_ARCH;
10219 p = frag_more (sizeof (e_note.namesz));
10220 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
10221 p = frag_more (sizeof (e_note.descsz));
10222 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
10223 p = frag_more (sizeof (e_note.type));
10224 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
10225 p = frag_more (len + 1);
10226 strcpy (p, cpu_arch_name);
10227
10228 frag_align (2, 0, 0);
10229
10230 subseg_set (seg, subseg);
10231 }
10232}
10233#endif
252b5132 10234\f
252b5132 10235symbolS *
7016a5d5 10236md_undefined_symbol (char *name)
252b5132 10237{
18dc2407
ILT		 10238 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10239 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10240 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10241 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10242 {
10243 if (!GOT_symbol)
10244 {
10245 if (symbol_find (name))
10246 as_bad (_("GOT already in symbol table"));
10247 GOT_symbol = symbol_new (name, undefined_section,
10248 (valueT) 0, &zero_address_frag);
10249 };
10250 return GOT_symbol;
10251 }
252b5132
RH		 10252 return 0;
10253}
10254
10255/* Round up a section size to the appropriate boundary. */
47926f60 10256
252b5132 10257valueT
7016a5d5 10258md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10259{
4c63da97
AM		 10260#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10261 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10262 {
10263 /* For a.out, force the section size to be aligned. If we don't do
10264 this, BFD will align it for us, but it will not write out the
10265 final bytes of the section. This may be a bug in BFD, but it is
10266 easier to fix it here since that is how the other a.out targets
10267 work. */
10268 int align;
10269
10270 align = bfd_get_section_alignment (stdoutput, segment);
10271 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
10272 }
252b5132
RH		 10273#endif
10274
10275 return size;
10276}
10277
10278/* On the i386, PC-relative offsets are relative to the start of the
10279 next instruction. That is, the address of the offset, plus its
10280 size, since the offset is always the last part of the insn. */
10281
10282long
e3bb37b5 10283md_pcrel_from (fixS *fixP)
252b5132
RH		 10284{
10285 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10286}
10287
10288#ifndef I386COFF
10289
10290static void
e3bb37b5 10291s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10292{
29b0f896 10293 int temp;
252b5132 10294
8a75718c
JB		 10295#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10296 if (IS_ELF)
10297 obj_elf_section_change_hook ();
10298#endif
252b5132
RH		 10299 temp = get_absolute_expression ();
10300 subseg_set (bss_section, (subsegT) temp);
10301 demand_empty_rest_of_line ();
10302}
10303
10304#endif
10305
252b5132 10306void
e3bb37b5 10307i386_validate_fix (fixS *fixp)
252b5132
RH		 10308{
10309 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
10310 {
23df1078
JH		 10311 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10312 {
4fa24527 10313 if (!object_64bit)
23df1078
JH		 10314 abort ();
10315 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10316 }
10317 else
10318 {
4fa24527 10319 if (!object_64bit)
d6ab8113
JB		 10320 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10321 else
10322 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 10323 }
252b5132
RH		 10324 fixp->fx_subsy = 0;
10325 }
10326}
10327
252b5132 10328arelent *
7016a5d5 10329tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10330{
10331 arelent *rel;
10332 bfd_reloc_code_real_type code;
10333
10334 switch (fixp->fx_r_type)
10335 {
8ce3d284 10336#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10337 case BFD_RELOC_SIZE32:
10338 case BFD_RELOC_SIZE64:
10339 if (S_IS_DEFINED (fixp->fx_addsy)
10340 && !S_IS_EXTERNAL (fixp->fx_addsy))
10341 {
10342 /* Resolve size relocation against local symbol to size of
10343 the symbol plus addend. */
10344 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10345 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10346 && !fits_in_unsigned_long (value))
10347 as_bad_where (fixp->fx_file, fixp->fx_line,
10348 _("symbol size computation overflow"));
10349 fixp->fx_addsy = NULL;
10350 fixp->fx_subsy = NULL;
10351 md_apply_fix (fixp, (valueT *) &value, NULL);
10352 return NULL;
10353 }
8ce3d284 10354#endif
8fd4256d 10355
3e73aa7c 10356 case BFD_RELOC_X86_64_PLT32:
c3320543 10357 case BFD_RELOC_X86_64_PLT32_BND:
3e73aa7c
JH		 10358 case BFD_RELOC_X86_64_GOT32:
10359 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 10360 case BFD_RELOC_386_PLT32:
10361 case BFD_RELOC_386_GOT32:
10362 case BFD_RELOC_386_GOTOFF:
10363 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10364 case BFD_RELOC_386_TLS_GD:
10365 case BFD_RELOC_386_TLS_LDM:
10366 case BFD_RELOC_386_TLS_LDO_32:
10367 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10368 case BFD_RELOC_386_TLS_IE:
10369 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10370 case BFD_RELOC_386_TLS_LE_32:
10371 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10372 case BFD_RELOC_386_TLS_GOTDESC:
10373 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10374 case BFD_RELOC_X86_64_TLSGD:
10375 case BFD_RELOC_X86_64_TLSLD:
10376 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10377 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10378 case BFD_RELOC_X86_64_GOTTPOFF:
10379 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10380 case BFD_RELOC_X86_64_TPOFF64:
10381 case BFD_RELOC_X86_64_GOTOFF64:
10382 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10383 case BFD_RELOC_X86_64_GOT64:
10384 case BFD_RELOC_X86_64_GOTPCREL64:
10385 case BFD_RELOC_X86_64_GOTPC64:
10386 case BFD_RELOC_X86_64_GOTPLT64:
10387 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10388 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10389 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10390 case BFD_RELOC_RVA:
10391 case BFD_RELOC_VTABLE_ENTRY:
10392 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10393#ifdef TE_PE
10394 case BFD_RELOC_32_SECREL:
10395#endif
252b5132
RH		 10396 code = fixp->fx_r_type;
10397 break;
dbbaec26
L		 10398 case BFD_RELOC_X86_64_32S:
10399 if (!fixp->fx_pcrel)
10400 {
10401 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10402 code = fixp->fx_r_type;
10403 break;
10404 }
252b5132 10405 default:
93382f6d 10406 if (fixp->fx_pcrel)
252b5132 10407 {
93382f6d
AM		 10408 switch (fixp->fx_size)
10409 {
10410 default:
b091f402
AM		 10411 as_bad_where (fixp->fx_file, fixp->fx_line,
10412 _("can not do %d byte pc-relative relocation"),
10413 fixp->fx_size);
93382f6d
AM		 10414 code = BFD_RELOC_32_PCREL;
10415 break;
10416 case 1: code = BFD_RELOC_8_PCREL; break;
10417 case 2: code = BFD_RELOC_16_PCREL; break;
c3320543
L		 10418 case 4:
10419 code = (fixp->fx_r_type == BFD_RELOC_X86_64_PC32_BND
10420 ? fixp-> fx_r_type : BFD_RELOC_32_PCREL);
10421 break;
d6ab8113
JB		 10422#ifdef BFD64
10423 case 8: code = BFD_RELOC_64_PCREL; break;
10424#endif
93382f6d
AM		 10425 }
10426 }
10427 else
10428 {
10429 switch (fixp->fx_size)
10430 {
10431 default:
b091f402
AM		 10432 as_bad_where (fixp->fx_file, fixp->fx_line,
10433 _("can not do %d byte relocation"),
10434 fixp->fx_size);
93382f6d
AM		 10435 code = BFD_RELOC_32;
10436 break;
10437 case 1: code = BFD_RELOC_8; break;
10438 case 2: code = BFD_RELOC_16; break;
10439 case 4: code = BFD_RELOC_32; break;
937149dd 10440#ifdef BFD64
3e73aa7c 10441 case 8: code = BFD_RELOC_64; break;
937149dd 10442#endif
93382f6d 10443 }
252b5132
RH		 10444 }
10445 break;
10446 }
252b5132 10447
d182319b
JB		 10448 if ((code == BFD_RELOC_32
10449 || code == BFD_RELOC_32_PCREL
10450 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10451 && GOT_symbol
10452 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10453 {
4fa24527 10454 if (!object_64bit)
d6ab8113
JB		 10455 code = BFD_RELOC_386_GOTPC;
10456 else
10457 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10458 }
7b81dfbb
AJ		 10459 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10460 && GOT_symbol
10461 && fixp->fx_addsy == GOT_symbol)
10462 {
10463 code = BFD_RELOC_X86_64_GOTPC64;
10464 }
252b5132
RH		 10465
10466 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 10467 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10468 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10469
10470 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10471
3e73aa7c
JH		 10472 if (!use_rela_relocations)
10473 {
10474 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10475 vtable entry to be used in the relocation's section offset. */
10476 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10477 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10478#if defined (OBJ_COFF) && defined (TE_PE)
10479 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10480 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10481 else
10482#endif
c6682705 10483 rel->addend = 0;
3e73aa7c
JH		 10484 }
10485 /* Use the rela in 64bit mode. */
252b5132 10486 else
3e73aa7c 10487 {
862be3fb
L		 10488 if (disallow_64bit_reloc)
10489 switch (code)
10490 {
862be3fb
L		 10491 case BFD_RELOC_X86_64_DTPOFF64:
10492 case BFD_RELOC_X86_64_TPOFF64:
10493 case BFD_RELOC_64_PCREL:
10494 case BFD_RELOC_X86_64_GOTOFF64:
10495 case BFD_RELOC_X86_64_GOT64:
10496 case BFD_RELOC_X86_64_GOTPCREL64:
10497 case BFD_RELOC_X86_64_GOTPC64:
10498 case BFD_RELOC_X86_64_GOTPLT64:
10499 case BFD_RELOC_X86_64_PLTOFF64:
10500 as_bad_where (fixp->fx_file, fixp->fx_line,
10501 _("cannot represent relocation type %s in x32 mode"),
10502 bfd_get_reloc_code_name (code));
10503 break;
10504 default:
10505 break;
10506 }
10507
062cd5e7
AS		 10508 if (!fixp->fx_pcrel)
10509 rel->addend = fixp->fx_offset;
10510 else
10511 switch (code)
10512 {
10513 case BFD_RELOC_X86_64_PLT32:
c3320543 10514 case BFD_RELOC_X86_64_PLT32_BND:
062cd5e7
AS		 10515 case BFD_RELOC_X86_64_GOT32:
10516 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 10517 case BFD_RELOC_X86_64_TLSGD:
10518 case BFD_RELOC_X86_64_TLSLD:
10519 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10520 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10521 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10522 rel->addend = fixp->fx_offset - fixp->fx_size;
10523 break;
10524 default:
10525 rel->addend = (section->vma
10526 - fixp->fx_size
10527 + fixp->fx_addnumber
10528 + md_pcrel_from (fixp));
10529 break;
10530 }
3e73aa7c
JH		 10531 }
10532
252b5132
RH		 10533 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10534 if (rel->howto == NULL)
10535 {
10536 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10537 _("cannot represent relocation type %s"),
252b5132
RH		 10538 bfd_get_reloc_code_name (code));
10539 /* Set howto to a garbage value so that we can keep going. */
10540 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10541 gas_assert (rel->howto != NULL);
252b5132
RH		 10542 }
10543
10544 return rel;
10545}
10546
ee86248c 10547#include "tc-i386-intel.c"
54cfded0 10548
a60de03c
JB		 10549void
10550tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10551{
a60de03c
JB		 10552 int saved_naked_reg;
10553 char saved_register_dot;
54cfded0 10554
a60de03c
JB		 10555 saved_naked_reg = allow_naked_reg;
10556 allow_naked_reg = 1;
10557 saved_register_dot = register_chars['.'];
10558 register_chars['.'] = '.';
10559 allow_pseudo_reg = 1;
10560 expression_and_evaluate (exp);
10561 allow_pseudo_reg = 0;
10562 register_chars['.'] = saved_register_dot;
10563 allow_naked_reg = saved_naked_reg;
10564
e96d56a1 10565 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10566 {
a60de03c
JB		 10567 if ((addressT) exp->X_add_number < i386_regtab_size)
10568 {
10569 exp->X_op = O_constant;
10570 exp->X_add_number = i386_regtab[exp->X_add_number]
10571 .dw2_regnum[flag_code >> 1];
10572 }
10573 else
10574 exp->X_op = O_illegal;
54cfded0 10575 }
54cfded0
AM		 10576}
10577
10578void
10579tc_x86_frame_initial_instructions (void)
10580{
a60de03c
JB		 10581 static unsigned int sp_regno[2];
10582
10583 if (!sp_regno[flag_code >> 1])
10584 {
10585 char *saved_input = input_line_pointer;
10586 char sp[][4] = {"esp", "rsp"};
10587 expressionS exp;
a4447b93 10588
a60de03c
JB		 10589 input_line_pointer = sp[flag_code >> 1];
10590 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10591 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10592 sp_regno[flag_code >> 1] = exp.X_add_number;
10593 input_line_pointer = saved_input;
10594 }
a4447b93 10595
61ff971f
L		 10596 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10597 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10598}
d2b2c203 10599
d7921315
L		 10600int
10601x86_dwarf2_addr_size (void)
10602{
10603#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10604 if (x86_elf_abi == X86_64_X32_ABI)
10605 return 4;
10606#endif
10607 return bfd_arch_bits_per_address (stdoutput) / 8;
10608}
10609
d2b2c203
DJ		 10610int
10611i386_elf_section_type (const char *str, size_t len)
10612{
10613 if (flag_code == CODE_64BIT
10614 && len == sizeof ("unwind") - 1
10615 && strncmp (str, "unwind", 6) == 0)
10616 return SHT_X86_64_UNWIND;
10617
10618 return -1;
10619}
bb41ade5 10620
ad5fec3b
EB		 10621#ifdef TE_SOLARIS
10622void
10623i386_solaris_fix_up_eh_frame (segT sec)
10624{
10625 if (flag_code == CODE_64BIT)
10626 elf_section_type (sec) = SHT_X86_64_UNWIND;
10627}
10628#endif
10629
bb41ade5
AM		 10630#ifdef TE_PE
10631void
10632tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10633{
91d6fa6a 10634 expressionS exp;
bb41ade5 10635
91d6fa6a
NC		 10636 exp.X_op = O_secrel;
10637 exp.X_add_symbol = symbol;
10638 exp.X_add_number = 0;
10639 emit_expr (&exp, size);
bb41ade5
AM		 10640}
10641#endif
3b22753a
L		 10642
10643#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10644/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10645
01e1a5bc 10646bfd_vma
3b22753a
L		 10647x86_64_section_letter (int letter, char **ptr_msg)
10648{
10649 if (flag_code == CODE_64BIT)
10650 {
10651 if (letter == 'l')
10652 return SHF_X86_64_LARGE;
10653
8f3bae45 10654 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10655 }
3b22753a 10656 else
8f3bae45 10657 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10658 return -1;
10659}
10660
01e1a5bc 10661bfd_vma
3b22753a
L		 10662x86_64_section_word (char *str, size_t len)
10663{
8620418b 10664 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10665 return SHF_X86_64_LARGE;
10666
10667 return -1;
10668}
10669
10670static void
10671handle_large_common (int small ATTRIBUTE_UNUSED)
10672{
10673 if (flag_code != CODE_64BIT)
10674 {
10675 s_comm_internal (0, elf_common_parse);
10676 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10677 }
10678 else
10679 {
10680 static segT lbss_section;
10681 asection *saved_com_section_ptr = elf_com_section_ptr;
10682 asection *saved_bss_section = bss_section;
10683
10684 if (lbss_section == NULL)
10685 {
10686 flagword applicable;
10687 segT seg = now_seg;
10688 subsegT subseg = now_subseg;
10689
10690 /* The .lbss section is for local .largecomm symbols. */
10691 lbss_section = subseg_new (".lbss", 0);
10692 applicable = bfd_applicable_section_flags (stdoutput);
10693 bfd_set_section_flags (stdoutput, lbss_section,
10694 applicable & SEC_ALLOC);
10695 seg_info (lbss_section)->bss = 1;
10696
10697 subseg_set (seg, subseg);
10698 }
10699
10700 elf_com_section_ptr = &_bfd_elf_large_com_section;
10701 bss_section = lbss_section;
10702
10703 s_comm_internal (0, elf_common_parse);
10704
10705 elf_com_section_ptr = saved_com_section_ptr;
10706 bss_section = saved_bss_section;
10707 }
10708}
10709#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
This page took 1.630785 seconds and 4 git commands to generate.