projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
-Wimplicit-fallthrough warning fixes
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
6f2750fe 2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d
L		 68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 136}
137arch_entry;
138
293f5f65
L		 139/* Used to turn off indicated flags. */
140typedef struct
141{
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
145}
146noarch_entry;
147
78f12dd3 148static void update_code_flag (int, int);
e3bb37b5
L		 149static void set_code_flag (int);
150static void set_16bit_gcc_code_flag (int);
151static void set_intel_syntax (int);
1efbbeb4 152static void set_intel_mnemonic (int);
db51cc60 153static void set_allow_index_reg (int);
7bab8ab5 154static void set_check (int);
e3bb37b5 155static void set_cpu_arch (int);
6482c264 156#ifdef TE_PE
e3bb37b5 157static void pe_directive_secrel (int);
6482c264 158#endif
e3bb37b5
L		 159static void signed_cons (int);
160static char *output_invalid (int c);
ee86248c
JB		 161static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
162 const char *);
163static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
164 const char *);
a7619375 165static int i386_att_operand (char *);
e3bb37b5 166static int i386_intel_operand (char *, int);
ee86248c
JB		 167static int i386_intel_simplify (expressionS *);
168static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 169static const reg_entry *parse_register (char *, char **);
170static char *parse_insn (char *, char *);
171static char *parse_operands (char *, const char *);
172static void swap_operands (void);
4d456e3d 173static void swap_2_operands (int, int);
e3bb37b5
L		 174static void optimize_imm (void);
175static void optimize_disp (void);
83b16ac6 176static const insn_template *match_template (char);
e3bb37b5
L		 177static int check_string (void);
178static int process_suffix (void);
179static int check_byte_reg (void);
180static int check_long_reg (void);
181static int check_qword_reg (void);
182static int check_word_reg (void);
183static int finalize_imm (void);
184static int process_operands (void);
185static const seg_entry *build_modrm_byte (void);
186static void output_insn (void);
187static void output_imm (fragS *, offsetT);
188static void output_disp (fragS *, offsetT);
29b0f896 189#ifndef I386COFF
e3bb37b5 190static void s_bss (int);
252b5132 191#endif
17d4e2a2
L		 192#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193static void handle_large_common (int small ATTRIBUTE_UNUSED);
194#endif
252b5132 195
a847613f 196static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 197
43234a1e
L		 198/* This struct describes rounding control and SAE in the instruction. */
199struct RC_Operation
200{
201 enum rc_type
202 {
203 rne = 0,
204 rd,
205 ru,
206 rz,
207 saeonly
208 } type;
209 int operand;
210};
211
212static struct RC_Operation rc_op;
213
214/* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217struct Mask_Operation
218{
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
222 int operand;
223};
224
225static struct Mask_Operation mask_op;
226
227/* The struct describes broadcasting, applied to OPERAND. FACTOR is
228 broadcast factor. */
229struct Broadcast_Operation
230{
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 int type;
233
234 /* Index of broadcasted operand. */
235 int operand;
236};
237
238static struct Broadcast_Operation broadcast_op;
239
c0f3af97
L		 240/* VEX prefix. */
241typedef struct
242{
43234a1e
L		 243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
c0f3af97
L		 245 unsigned int length;
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
248} vex_prefix;
249
252b5132 250/* 'md_assemble ()' gathers together information and puts it into a
47926f60 251 i386_insn. */
252b5132 252
520dc8e8
AM		 253union i386_op
254 {
255 expressionS *disps;
256 expressionS *imms;
257 const reg_entry *regs;
258 };
259
a65babc9
L		 260enum i386_error
261 {
86e026a4 262 operand_size_mismatch,
a65babc9
L		 263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
267 bad_imm4,
268 old_gcc_only,
269 unsupported_with_intel_mnemonic,
270 unsupported_syntax,
6c30d220
L		 271 unsupported,
272 invalid_vsib_address,
7bab8ab5 273 invalid_vector_register_set,
43234a1e
L		 274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
277 broadcast_needed,
278 unsupported_masking,
279 mask_not_on_destination,
280 no_default_mask,
281 unsupported_rc_sae,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
284 try_vector_disp8
a65babc9
L		 285 };
286
252b5132
RH		 287struct _i386_insn
288 {
47926f60 289 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 290 insn_template tm;
252b5132 291
7d5e4556
L		 292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
252b5132
RH		 294 char suffix;
295
47926f60 296 /* OPERANDS gives the number of given operands. */
252b5132
RH		 297 unsigned int operands;
298
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
47926f60 301 operands. */
252b5132
RH		 302 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
303
304 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 305 use OP[i] for the corresponding operand. */
40fb9820 306 i386_operand_type types[MAX_OPERANDS];
252b5132 307
520dc8e8
AM		 308 /* Displacement expression, immediate expression, or register for each
309 operand. */
310 union i386_op op[MAX_OPERANDS];
252b5132 311
3e73aa7c
JH		 312 /* Flags for operands. */
313 unsigned int flags[MAX_OPERANDS];
314#define Operand_PCrel 1
315
252b5132 316 /* Relocation type for operand */
f86103b7 317 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 318
252b5132
RH		 319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry *base_reg;
322 const reg_entry *index_reg;
323 unsigned int log2_scale_factor;
324
325 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 326 explicit segment overrides are given. */
ce8a8b2f 327 const seg_entry *seg[2];
252b5132 328
8325cc63
JB		 329 /* Copied first memory operand string, for re-checking. */
330 char *memop1_string;
331
252b5132
RH		 332 /* PREFIX holds all the given prefix opcodes (usually null).
333 PREFIXES is the number of prefix opcodes. */
334 unsigned int prefixes;
335 unsigned char prefix[MAX_PREFIXES];
336
337 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 338 addressing modes of this insn are encoded. */
252b5132 339 modrm_byte rm;
3e73aa7c 340 rex_byte rex;
43234a1e 341 rex_byte vrex;
252b5132 342 sib_byte sib;
c0f3af97 343 vex_prefix vex;
b6169b20 344
43234a1e
L		 345 /* Masking attributes. */
346 struct Mask_Operation *mask;
347
348 /* Rounding control and SAE attributes. */
349 struct RC_Operation *rounding;
350
351 /* Broadcasting attributes. */
352 struct Broadcast_Operation *broadcast;
353
354 /* Compressed disp8*N attribute. */
355 unsigned int memshift;
356
b6169b20 357 /* Swap operand in encoding. */
4473e004 358 unsigned int swap_operand;
891edac4 359
a501d77e
L		 360 /* Prefer 8bit or 32bit displacement in encoding. */
361 enum
362 {
363 disp_encoding_default = 0,
364 disp_encoding_8bit,
365 disp_encoding_32bit
366 } disp_encoding;
f8a5c266 367
d5de92cf
L		 368 /* REP prefix. */
369 const char *rep_prefix;
370
165de32a
L		 371 /* HLE prefix. */
372 const char *hle_prefix;
42164a71 373
7e8b059b
L		 374 /* Have BND prefix. */
375 const char *bnd_prefix;
376
43234a1e
L		 377 /* Need VREX to support upper 16 registers. */
378 int need_vrex;
379
891edac4 380 /* Error message. */
a65babc9 381 enum i386_error error;
252b5132
RH		 382 };
383
384typedef struct _i386_insn i386_insn;
385
43234a1e
L		 386/* Link RC type with corresponding string, that'll be looked for in
387 asm. */
388struct RC_name
389{
390 enum rc_type type;
391 const char *name;
392 unsigned int len;
393};
394
395static const struct RC_name RC_NamesTable[] =
396{
397 { rne, STRING_COMMA_LEN ("rn-sae") },
398 { rd, STRING_COMMA_LEN ("rd-sae") },
399 { ru, STRING_COMMA_LEN ("ru-sae") },
400 { rz, STRING_COMMA_LEN ("rz-sae") },
401 { saeonly, STRING_COMMA_LEN ("sae") },
402};
403
252b5132
RH		 404/* List of chars besides those in app.c:symbol_chars that can start an
405 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 406const char extra_symbol_chars[] = "*%-([{"
252b5132 407#ifdef LEX_AT
32137342
NC		 408 "@"
409#endif
410#ifdef LEX_QM
411 "?"
252b5132 412#endif
32137342 413 ;
252b5132 414
29b0f896
AM		 415#if (defined (TE_I386AIX) \
416 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 417 && !defined (TE_GNU) \
29b0f896 418 && !defined (TE_LINUX) \
8d63c93e
RM		 419 && !defined (TE_NACL) \
420 && !defined (TE_NETWARE) \
29b0f896 421 && !defined (TE_FreeBSD) \
5b806d27 422 && !defined (TE_DragonFly) \
29b0f896 423 && !defined (TE_NetBSD)))
252b5132 424/* This array holds the chars that always start a comment. If the
b3b91714
AM		 425 pre-processor is disabled, these aren't very useful. The option
426 --divide will remove '/' from this list. */
427const char *i386_comment_chars = "#/";
428#define SVR4_COMMENT_CHARS 1
252b5132 429#define PREFIX_SEPARATOR '\\'
252b5132 430
b3b91714
AM		 431#else
432const char *i386_comment_chars = "#";
433#define PREFIX_SEPARATOR '/'
434#endif
435
252b5132
RH		 436/* This array holds the chars that only start a comment at the beginning of
437 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 438 .line and .file directives will appear in the pre-processed output.
439 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 440 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 441 #NO_APP at the beginning of its output.
442 Also note that comments started like this one will always work if
252b5132 443 '/' isn't otherwise defined. */
b3b91714 444const char line_comment_chars[] = "#/";
252b5132 445
63a0b638 446const char line_separator_chars[] = ";";
252b5132 447
ce8a8b2f
AM		 448/* Chars that can be used to separate mant from exp in floating point
449 nums. */
252b5132
RH		 450const char EXP_CHARS[] = "eE";
451
ce8a8b2f
AM		 452/* Chars that mean this number is a floating point constant
453 As in 0f12.456
454 or 0d1.2345e12. */
252b5132
RH		 455const char FLT_CHARS[] = "fFdDxX";
456
ce8a8b2f 457/* Tables for lexical analysis. */
252b5132
RH		 458static char mnemonic_chars[256];
459static char register_chars[256];
460static char operand_chars[256];
461static char identifier_chars[256];
462static char digit_chars[256];
463
ce8a8b2f 464/* Lexical macros. */
252b5132
RH		 465#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
466#define is_operand_char(x) (operand_chars[(unsigned char) x])
467#define is_register_char(x) (register_chars[(unsigned char) x])
468#define is_space_char(x) ((x) == ' ')
469#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
470#define is_digit_char(x) (digit_chars[(unsigned char) x])
471
0234cb7c 472/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 473static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
474
475/* md_assemble() always leaves the strings it's passed unaltered. To
476 effect this we maintain a stack of saved characters that we've smashed
477 with '\0's (indicating end of strings for various sub-fields of the
47926f60 478 assembler instruction). */
252b5132 479static char save_stack[32];
ce8a8b2f 480static char *save_stack_p;
252b5132
RH		 481#define END_STRING_AND_SAVE(s) \
482 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
483#define RESTORE_END_STRING(s) \
484 do { *(s) = *--save_stack_p; } while (0)
485
47926f60 486/* The instruction we're assembling. */
252b5132
RH		 487static i386_insn i;
488
489/* Possible templates for current insn. */
490static const templates *current_templates;
491
31b2323c
L		 492/* Per instruction expressionS buffers: max displacements & immediates. */
493static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
494static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 495
47926f60 496/* Current operand we are working on. */
ee86248c 497static int this_operand = -1;
252b5132 498
3e73aa7c
JH		 499/* We support four different modes. FLAG_CODE variable is used to distinguish
500 these. */
501
502enum flag_code {
503 CODE_32BIT,
504 CODE_16BIT,
505 CODE_64BIT };
506
507static enum flag_code flag_code;
4fa24527 508static unsigned int object_64bit;
862be3fb 509static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 510static int use_rela_relocations = 0;
511
7af8ed2d
NC		 512#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
513 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
514 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
515
351f65ca
L		 516/* The ELF ABI to use. */
517enum x86_elf_abi
518{
519 I386_ABI,
7f56bc95
L		 520 X86_64_ABI,
521 X86_64_X32_ABI
351f65ca
L		 522};
523
524static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 525#endif
351f65ca 526
167ad85b
TG		 527#if defined (TE_PE) || defined (TE_PEP)
528/* Use big object file format. */
529static int use_big_obj = 0;
530#endif
531
8dcea932
L		 532#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
533/* 1 if generating code for a shared library. */
534static int shared = 0;
535#endif
536
47926f60
KH		 537/* 1 for intel syntax,
538 0 if att syntax. */
539static int intel_syntax = 0;
252b5132 540
e89c5eaa
L		 541/* 1 for Intel64 ISA,
542 0 if AMD64 ISA. */
543static int intel64;
544
1efbbeb4
L		 545/* 1 for intel mnemonic,
546 0 if att mnemonic. */
547static int intel_mnemonic = !SYSV386_COMPAT;
548
5209009a 549/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 550static int old_gcc = OLDGCC_COMPAT;
551
a60de03c
JB		 552/* 1 if pseudo registers are permitted. */
553static int allow_pseudo_reg = 0;
554
47926f60
KH		 555/* 1 if register prefix % not required. */
556static int allow_naked_reg = 0;
252b5132 557
7e8b059b
L		 558/* 1 if the assembler should add BND prefix for all control-tranferring
559 instructions supporting it, even if this prefix wasn't specified
560 explicitly. */
561static int add_bnd_prefix = 0;
562
ba104c83 563/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 564static int allow_index_reg = 0;
565
d022bddd
IT		 566/* 1 if the assembler should ignore LOCK prefix, even if it was
567 specified explicitly. */
568static int omit_lock_prefix = 0;
569
e4e00185
AS		 570/* 1 if the assembler should encode lfence, mfence, and sfence as
571 "lock addl $0, (%{re}sp)". */
572static int avoid_fence = 0;
573
0cb4071e
L		 574/* 1 if the assembler should generate relax relocations. */
575
576static int generate_relax_relocations
577 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
578
7bab8ab5 579static enum check_kind
daf50ae7 580 {
7bab8ab5
JB		 581 check_none = 0,
582 check_warning,
583 check_error
daf50ae7 584 }
7bab8ab5 585sse_check, operand_check = check_warning;
daf50ae7 586
2ca3ace5
L		 587/* Register prefix used for error message. */
588static const char *register_prefix = "%";
589
47926f60
KH		 590/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
591 leave, push, and pop instructions so that gcc has the same stack
592 frame as in 32 bit mode. */
593static char stackop_size = '\0';
eecb386c 594
12b55ccc
L		 595/* Non-zero to optimize code alignment. */
596int optimize_align_code = 1;
597
47926f60
KH		 598/* Non-zero to quieten some warnings. */
599static int quiet_warnings = 0;
a38cf1db 600
47926f60
KH		 601/* CPU name. */
602static const char *cpu_arch_name = NULL;
6305a203 603static char *cpu_sub_arch_name = NULL;
a38cf1db 604
47926f60 605/* CPU feature flags. */
40fb9820
L		 606static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
607
ccc9c027
L		 608/* If we have selected a cpu we are generating instructions for. */
609static int cpu_arch_tune_set = 0;
610
9103f4f4 611/* Cpu we are generating instructions for. */
fbf3f584 612enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 613
614/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 615static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 616
ccc9c027 617/* CPU instruction set architecture used. */
fbf3f584 618enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 619
9103f4f4 620/* CPU feature flags of instruction set architecture used. */
fbf3f584 621i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 622
fddf5b5b
AM		 623/* If set, conditional jumps are not automatically promoted to handle
624 larger than a byte offset. */
625static unsigned int no_cond_jump_promotion = 0;
626
c0f3af97
L		 627/* Encode SSE instructions with VEX prefix. */
628static unsigned int sse2avx;
629
539f890d
L		 630/* Encode scalar AVX instructions with specific vector length. */
631static enum
632 {
633 vex128 = 0,
634 vex256
635 } avxscalar;
636
43234a1e
L		 637/* Encode scalar EVEX LIG instructions with specific vector length. */
638static enum
639 {
640 evexl128 = 0,
641 evexl256,
642 evexl512
643 } evexlig;
644
645/* Encode EVEX WIG instructions with specific evex.w. */
646static enum
647 {
648 evexw0 = 0,
649 evexw1
650 } evexwig;
651
d3d3c6db
IT		 652/* Value to encode in EVEX RC bits, for SAE-only instructions. */
653static enum rc_type evexrcig = rne;
654
29b0f896 655/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 656static symbolS *GOT_symbol;
29b0f896 657
a4447b93
RH		 658/* The dwarf2 return column, adjusted for 32 or 64 bit. */
659unsigned int x86_dwarf2_return_column;
660
661/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
662int x86_cie_data_alignment;
663
252b5132 664/* Interface to relax_segment.
fddf5b5b
AM		 665 There are 3 major relax states for 386 jump insns because the
666 different types of jumps add different sizes to frags when we're
667 figuring out what sort of jump to choose to reach a given label. */
252b5132 668
47926f60 669/* Types. */
93c2a809
AM		 670#define UNCOND_JUMP 0
671#define COND_JUMP 1
672#define COND_JUMP86 2
fddf5b5b 673
47926f60 674/* Sizes. */
252b5132
RH		 675#define CODE16 1
676#define SMALL 0
29b0f896 677#define SMALL16 (SMALL | CODE16)
252b5132 678#define BIG 2
29b0f896 679#define BIG16 (BIG | CODE16)
252b5132
RH		 680
681#ifndef INLINE
682#ifdef __GNUC__
683#define INLINE __inline__
684#else
685#define INLINE
686#endif
687#endif
688
fddf5b5b
AM		 689#define ENCODE_RELAX_STATE(type, size) \
690 ((relax_substateT) (((type) << 2) | (size)))
691#define TYPE_FROM_RELAX_STATE(s) \
692 ((s) >> 2)
693#define DISP_SIZE_FROM_RELAX_STATE(s) \
694 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 695
696/* This table is used by relax_frag to promote short jumps to long
697 ones where necessary. SMALL (short) jumps may be promoted to BIG
698 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
699 don't allow a short jump in a 32 bit code segment to be promoted to
700 a 16 bit offset jump because it's slower (requires data size
701 prefix), and doesn't work, unless the destination is in the bottom
702 64k of the code segment (The top 16 bits of eip are zeroed). */
703
704const relax_typeS md_relax_table[] =
705{
24eab124
AM		 706 /* The fields are:
707 1) most positive reach of this state,
708 2) most negative reach of this state,
93c2a809 709 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 710 4) which index into the table to try if we can't fit into this one. */
252b5132 711
fddf5b5b 712 /* UNCOND_JUMP states. */
93c2a809
AM		 713 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
714 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
715 /* dword jmp adds 4 bytes to frag:
716 0 extra opcode bytes, 4 displacement bytes. */
252b5132 717 {0, 0, 4, 0},
93c2a809
AM		 718 /* word jmp adds 2 byte2 to frag:
719 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 720 {0, 0, 2, 0},
721
93c2a809
AM		 722 /* COND_JUMP states. */
723 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
724 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
725 /* dword conditionals adds 5 bytes to frag:
726 1 extra opcode byte, 4 displacement bytes. */
727 {0, 0, 5, 0},
fddf5b5b 728 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 729 1 extra opcode byte, 2 displacement bytes. */
730 {0, 0, 3, 0},
731
732 /* COND_JUMP86 states. */
733 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
734 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
735 /* dword conditionals adds 5 bytes to frag:
736 1 extra opcode byte, 4 displacement bytes. */
737 {0, 0, 5, 0},
738 /* word conditionals add 4 bytes to frag:
739 1 displacement byte and a 3 byte long branch insn. */
740 {0, 0, 4, 0}
252b5132
RH		 741};
742
9103f4f4
L		 743static const arch_entry cpu_arch[] =
744{
89507696
JB		 745 /* Do not replace the first two entries - i386_target_format()
746 relies on them being there in this order. */
8a2c8fef 747 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 748 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 749 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 750 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 751 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 752 CPU_NONE_FLAGS, 0 },
8a2c8fef 753 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 754 CPU_I186_FLAGS, 0 },
8a2c8fef 755 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 756 CPU_I286_FLAGS, 0 },
8a2c8fef 757 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 758 CPU_I386_FLAGS, 0 },
8a2c8fef 759 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 760 CPU_I486_FLAGS, 0 },
8a2c8fef 761 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 762 CPU_I586_FLAGS, 0 },
8a2c8fef 763 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 764 CPU_I686_FLAGS, 0 },
8a2c8fef 765 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 766 CPU_I586_FLAGS, 0 },
8a2c8fef 767 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 768 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 769 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 770 CPU_P2_FLAGS, 0 },
8a2c8fef 771 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 772 CPU_P3_FLAGS, 0 },
8a2c8fef 773 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 774 CPU_P4_FLAGS, 0 },
8a2c8fef 775 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 776 CPU_CORE_FLAGS, 0 },
8a2c8fef 777 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 778 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 779 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 780 CPU_CORE_FLAGS, 1 },
8a2c8fef 781 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 782 CPU_CORE_FLAGS, 0 },
8a2c8fef 783 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 784 CPU_CORE2_FLAGS, 1 },
8a2c8fef 785 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 786 CPU_CORE2_FLAGS, 0 },
8a2c8fef 787 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 788 CPU_COREI7_FLAGS, 0 },
8a2c8fef 789 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 790 CPU_L1OM_FLAGS, 0 },
7a9068fe 791 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 792 CPU_K1OM_FLAGS, 0 },
81486035 793 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 794 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 795 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 796 CPU_K6_FLAGS, 0 },
8a2c8fef 797 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 798 CPU_K6_2_FLAGS, 0 },
8a2c8fef 799 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 800 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 801 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 802 CPU_K8_FLAGS, 1 },
8a2c8fef 803 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 804 CPU_K8_FLAGS, 0 },
8a2c8fef 805 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 806 CPU_K8_FLAGS, 0 },
8a2c8fef 807 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 808 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 809 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 810 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 811 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 812 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 813 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 814 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 815 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 816 CPU_BDVER4_FLAGS, 0 },
029f3522 817 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 818 CPU_ZNVER1_FLAGS, 0 },
7b458c12 819 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 820 CPU_BTVER1_FLAGS, 0 },
7b458c12 821 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 822 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 823 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 824 CPU_8087_FLAGS, 0 },
8a2c8fef 825 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 826 CPU_287_FLAGS, 0 },
8a2c8fef 827 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 828 CPU_387_FLAGS, 0 },
1848e567
L		 829 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
830 CPU_687_FLAGS, 0 },
8a2c8fef 831 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 832 CPU_MMX_FLAGS, 0 },
8a2c8fef 833 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 834 CPU_SSE_FLAGS, 0 },
8a2c8fef 835 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 836 CPU_SSE2_FLAGS, 0 },
8a2c8fef 837 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 838 CPU_SSE3_FLAGS, 0 },
8a2c8fef 839 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 840 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 841 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 842 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 843 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 844 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 845 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 846 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 847 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 848 CPU_AVX_FLAGS, 0 },
6c30d220 849 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 850 CPU_AVX2_FLAGS, 0 },
43234a1e 851 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 852 CPU_AVX512F_FLAGS, 0 },
43234a1e 853 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 854 CPU_AVX512CD_FLAGS, 0 },
43234a1e 855 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 856 CPU_AVX512ER_FLAGS, 0 },
43234a1e 857 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 858 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 859 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 860 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 861 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 862 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 863 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 864 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 865 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 866 CPU_VMX_FLAGS, 0 },
8729a6f6 867 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 868 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 869 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 870 CPU_SMX_FLAGS, 0 },
8a2c8fef 871 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 872 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 873 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 874 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 875 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 876 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 877 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 878 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 879 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 880 CPU_AES_FLAGS, 0 },
8a2c8fef 881 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 882 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 883 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 884 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 885 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 886 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 887 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 888 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 889 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 890 CPU_F16C_FLAGS, 0 },
6c30d220 891 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 892 CPU_BMI2_FLAGS, 0 },
8a2c8fef 893 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 894 CPU_FMA_FLAGS, 0 },
8a2c8fef 895 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 896 CPU_FMA4_FLAGS, 0 },
8a2c8fef 897 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 898 CPU_XOP_FLAGS, 0 },
8a2c8fef 899 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 900 CPU_LWP_FLAGS, 0 },
8a2c8fef 901 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 902 CPU_MOVBE_FLAGS, 0 },
60aa667e 903 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 904 CPU_CX16_FLAGS, 0 },
8a2c8fef 905 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 906 CPU_EPT_FLAGS, 0 },
6c30d220 907 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 908 CPU_LZCNT_FLAGS, 0 },
42164a71 909 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 910 CPU_HLE_FLAGS, 0 },
42164a71 911 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 912 CPU_RTM_FLAGS, 0 },
6c30d220 913 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 914 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 915 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 916 CPU_CLFLUSH_FLAGS, 0 },
22109423 917 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 918 CPU_NOP_FLAGS, 0 },
8a2c8fef 919 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 920 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 921 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 922 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 923 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 924 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 925 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 926 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 927 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 928 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 929 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 930 CPU_SVME_FLAGS, 1 },
8a2c8fef 931 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 932 CPU_SVME_FLAGS, 0 },
8a2c8fef 933 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 934 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 935 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 936 CPU_ABM_FLAGS, 0 },
87973e9f 937 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 938 CPU_BMI_FLAGS, 0 },
2a2a0f38 939 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 940 CPU_TBM_FLAGS, 0 },
e2e1fcde 941 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 942 CPU_ADX_FLAGS, 0 },
e2e1fcde 943 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 944 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 945 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 946 CPU_PRFCHW_FLAGS, 0 },
5c111e37 947 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 948 CPU_SMAP_FLAGS, 0 },
7e8b059b 949 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 950 CPU_MPX_FLAGS, 0 },
a0046408 951 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 952 CPU_SHA_FLAGS, 0 },
963f3586 953 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 954 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 955 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 956 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 957 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 958 CPU_SE1_FLAGS, 0 },
c5e7287a 959 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 960 CPU_CLWB_FLAGS, 0 },
9d8596f0 961 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN,
293f5f65 962 CPU_PCOMMIT_FLAGS, 0 },
2cc1b5aa 963 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 964 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 965 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 966 CPU_AVX512VBMI_FLAGS, 0 },
029f3522 967 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 968 CPU_CLZERO_FLAGS, 0 },
9916071f 969 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 970 CPU_MWAITX_FLAGS, 0 },
8eab4136 971 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 972 CPU_OSPKE_FLAGS, 0 },
8bc52696 973 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65 974 CPU_RDPID_FLAGS, 0 },
6b40c462
L		 975 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
976 CPU_PTWRITE_FLAGS, 0 },
293f5f65
L		 977};
978
979static const noarch_entry cpu_noarch[] =
980{
981 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1848e567
L		 982 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
983 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
984 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
293f5f65
L		 985 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
986 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1848e567
L		 987 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
988 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
989 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
990 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
991 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
992 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
293f5f65 993 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1848e567 994 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
144b71e2
L		 995 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
996 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
997 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
998 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
999 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1000 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1001 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1002 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1003 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
e413e4e9
AM		 1004};
1005
704209c0 1006#ifdef I386COFF
a6c24e68
NC		 1007/* Like s_lcomm_internal in gas/read.c but the alignment string
1008 is allowed to be optional. */
1009
1010static symbolS *
1011pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1012{
1013 addressT align = 0;
1014
1015 SKIP_WHITESPACE ();
1016
7ab9ffdd 1017 if (needs_align
a6c24e68
NC		 1018 && *input_line_pointer == ',')
1019 {
1020 align = parse_align (needs_align - 1);
7ab9ffdd 1021
a6c24e68
NC		 1022 if (align == (addressT) -1)
1023 return NULL;
1024 }
1025 else
1026 {
1027 if (size >= 8)
1028 align = 3;
1029 else if (size >= 4)
1030 align = 2;
1031 else if (size >= 2)
1032 align = 1;
1033 else
1034 align = 0;
1035 }
1036
1037 bss_alloc (symbolP, size, align);
1038 return symbolP;
1039}
1040
704209c0 1041static void
a6c24e68
NC		 1042pe_lcomm (int needs_align)
1043{
1044 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1045}
704209c0 1046#endif
a6c24e68 1047
29b0f896
AM		 1048const pseudo_typeS md_pseudo_table[] =
1049{
1050#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1051 {"align", s_align_bytes, 0},
1052#else
1053 {"align", s_align_ptwo, 0},
1054#endif
1055 {"arch", set_cpu_arch, 0},
1056#ifndef I386COFF
1057 {"bss", s_bss, 0},
a6c24e68
NC		 1058#else
1059 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1060#endif
1061 {"ffloat", float_cons, 'f'},
1062 {"dfloat", float_cons, 'd'},
1063 {"tfloat", float_cons, 'x'},
1064 {"value", cons, 2},
d182319b 1065 {"slong", signed_cons, 4},
29b0f896
AM		 1066 {"noopt", s_ignore, 0},
1067 {"optim", s_ignore, 0},
1068 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1069 {"code16", set_code_flag, CODE_16BIT},
1070 {"code32", set_code_flag, CODE_32BIT},
1071 {"code64", set_code_flag, CODE_64BIT},
1072 {"intel_syntax", set_intel_syntax, 1},
1073 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1074 {"intel_mnemonic", set_intel_mnemonic, 1},
1075 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1076 {"allow_index_reg", set_allow_index_reg, 1},
1077 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1078 {"sse_check", set_check, 0},
1079 {"operand_check", set_check, 1},
3b22753a
L		 1080#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1081 {"largecomm", handle_large_common, 0},
07a53e5c 1082#else
e3bb37b5 1083 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1084 {"loc", dwarf2_directive_loc, 0},
1085 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1086#endif
6482c264
NC		 1087#ifdef TE_PE
1088 {"secrel32", pe_directive_secrel, 0},
1089#endif
29b0f896
AM		 1090 {0, 0, 0}
1091};
1092
1093/* For interface with expression (). */
1094extern char *input_line_pointer;
1095
1096/* Hash table for instruction mnemonic lookup. */
1097static struct hash_control *op_hash;
1098
1099/* Hash table for register lookup. */
1100static struct hash_control *reg_hash;
1101\f
252b5132 1102void
e3bb37b5 1103i386_align_code (fragS *fragP, int count)
252b5132 1104{
ce8a8b2f
AM		 1105 /* Various efficient no-op patterns for aligning code labels.
1106 Note: Don't try to assemble the instructions in the comments.
1107 0L and 0w are not legal. */
bad6e36d 1108 static const unsigned char f32_1[] =
252b5132 1109 {0x90}; /* nop */
bad6e36d 1110 static const unsigned char f32_2[] =
ccc9c027 1111 {0x66,0x90}; /* xchg %ax,%ax */
bad6e36d 1112 static const unsigned char f32_3[] =
252b5132 1113 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
bad6e36d 1114 static const unsigned char f32_4[] =
252b5132 1115 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1116 static const unsigned char f32_5[] =
252b5132
RH		 1117 {0x90, /* nop */
1118 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1119 static const unsigned char f32_6[] =
252b5132 1120 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
bad6e36d 1121 static const unsigned char f32_7[] =
252b5132 1122 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1123 static const unsigned char f32_8[] =
252b5132
RH		 1124 {0x90, /* nop */
1125 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1126 static const unsigned char f32_9[] =
252b5132
RH		 1127 {0x89,0xf6, /* movl %esi,%esi */
1128 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1129 static const unsigned char f32_10[] =
252b5132
RH		 1130 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1131 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1132 static const unsigned char f32_11[] =
252b5132
RH		 1133 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1134 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1135 static const unsigned char f32_12[] =
252b5132
RH		 1136 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1137 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
bad6e36d 1138 static const unsigned char f32_13[] =
252b5132
RH		 1139 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1140 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1141 static const unsigned char f32_14[] =
252b5132
RH		 1142 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1143 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1144 static const unsigned char f16_3[] =
c3332e24 1145 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
bad6e36d 1146 static const unsigned char f16_4[] =
252b5132 1147 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1148 static const unsigned char f16_5[] =
252b5132
RH		 1149 {0x90, /* nop */
1150 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1151 static const unsigned char f16_6[] =
252b5132
RH		 1152 {0x89,0xf6, /* mov %si,%si */
1153 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1154 static const unsigned char f16_7[] =
252b5132
RH		 1155 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1156 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1157 static const unsigned char f16_8[] =
252b5132
RH		 1158 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1159 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1160 static const unsigned char jump_31[] =
76bc74dc
L		 1161 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1162 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1163 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1164 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
bad6e36d 1165 static const unsigned char *const f32_patt[] = {
252b5132 1166 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1167 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132 1168 };
bad6e36d 1169 static const unsigned char *const f16_patt[] = {
76bc74dc 1170 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1171 };
ccc9c027 1172 /* nopl (%[re]ax) */
bad6e36d 1173 static const unsigned char alt_3[] =
ccc9c027
L		 1174 {0x0f,0x1f,0x00};
1175 /* nopl 0(%[re]ax) */
bad6e36d 1176 static const unsigned char alt_4[] =
ccc9c027
L		 1177 {0x0f,0x1f,0x40,0x00};
1178 /* nopl 0(%[re]ax,%[re]ax,1) */
bad6e36d 1179 static const unsigned char alt_5[] =
ccc9c027
L		 1180 {0x0f,0x1f,0x44,0x00,0x00};
1181 /* nopw 0(%[re]ax,%[re]ax,1) */
bad6e36d 1182 static const unsigned char alt_6[] =
ccc9c027
L		 1183 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1184 /* nopl 0L(%[re]ax) */
bad6e36d 1185 static const unsigned char alt_7[] =
ccc9c027
L		 1186 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1187 /* nopl 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1188 static const unsigned char alt_8[] =
ccc9c027
L		 1189 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1190 /* nopw 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1191 static const unsigned char alt_9[] =
ccc9c027
L		 1192 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1193 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
bad6e36d 1194 static const unsigned char alt_10[] =
ccc9c027 1195 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
bad6e36d 1196 static const unsigned char *const alt_patt[] = {
ccc9c027 1197 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
80b8656c 1198 alt_9, alt_10
ccc9c027 1199 };
252b5132 1200
76bc74dc
L		 1201 /* Only align for at least a positive non-zero boundary. */
1202 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1203 return;
3e73aa7c 1204
ccc9c027
L		 1205 /* We need to decide which NOP sequence to use for 32bit and
1206 64bit. When -mtune= is used:
4eed87de 1207
76bc74dc
L		 1208 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1209 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1210 2. For the rest, alt_patt will be used.
1211
1212 When -mtune= isn't used, alt_patt will be used if
22109423 1213 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1214 be used.
ccc9c027
L		 1215
1216 When -march= or .arch is used, we can't use anything beyond
1217 cpu_arch_isa_flags. */
1218
1219 if (flag_code == CODE_16BIT)
1220 {
ccc9c027 1221 if (count > 8)
33fef721 1222 {
76bc74dc
L		 1223 memcpy (fragP->fr_literal + fragP->fr_fix,
1224 jump_31, count);
1225 /* Adjust jump offset. */
1226 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1227 }
76bc74dc
L		 1228 else
1229 memcpy (fragP->fr_literal + fragP->fr_fix,
1230 f16_patt[count - 1], count);
252b5132 1231 }
33fef721 1232 else
ccc9c027 1233 {
bad6e36d 1234 const unsigned char *const *patt = NULL;
ccc9c027 1235
fbf3f584 1236 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1237 {
1238 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1239 switch (cpu_arch_tune)
1240 {
1241 case PROCESSOR_UNKNOWN:
1242 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1243 optimize with nops. */
1244 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1245 patt = alt_patt;
ccc9c027
L		 1246 else
1247 patt = f32_patt;
1248 break;
ccc9c027
L		 1249 case PROCESSOR_PENTIUM4:
1250 case PROCESSOR_NOCONA:
ef05d495 1251 case PROCESSOR_CORE:
76bc74dc 1252 case PROCESSOR_CORE2:
bd5295b2 1253 case PROCESSOR_COREI7:
3632d14b 1254 case PROCESSOR_L1OM:
7a9068fe 1255 case PROCESSOR_K1OM:
76bc74dc 1256 case PROCESSOR_GENERIC64:
ccc9c027
L		 1257 case PROCESSOR_K6:
1258 case PROCESSOR_ATHLON:
1259 case PROCESSOR_K8:
4eed87de 1260 case PROCESSOR_AMDFAM10:
8aedb9fe 1261 case PROCESSOR_BD:
029f3522 1262 case PROCESSOR_ZNVER:
7b458c12 1263 case PROCESSOR_BT:
80b8656c 1264 patt = alt_patt;
ccc9c027 1265 break;
76bc74dc 1266 case PROCESSOR_I386:
ccc9c027
L		 1267 case PROCESSOR_I486:
1268 case PROCESSOR_PENTIUM:
2dde1948 1269 case PROCESSOR_PENTIUMPRO:
81486035 1270 case PROCESSOR_IAMCU:
ccc9c027
L		 1271 case PROCESSOR_GENERIC32:
1272 patt = f32_patt;
1273 break;
4eed87de 1274 }
ccc9c027
L		 1275 }
1276 else
1277 {
fbf3f584 1278 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1279 {
1280 case PROCESSOR_UNKNOWN:
e6a14101 1281 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1282 PROCESSOR_UNKNOWN. */
1283 abort ();
1284 break;
1285
76bc74dc 1286 case PROCESSOR_I386:
ccc9c027
L		 1287 case PROCESSOR_I486:
1288 case PROCESSOR_PENTIUM:
81486035 1289 case PROCESSOR_IAMCU:
ccc9c027
L		 1290 case PROCESSOR_K6:
1291 case PROCESSOR_ATHLON:
1292 case PROCESSOR_K8:
4eed87de 1293 case PROCESSOR_AMDFAM10:
8aedb9fe 1294 case PROCESSOR_BD:
029f3522 1295 case PROCESSOR_ZNVER:
7b458c12 1296 case PROCESSOR_BT:
ccc9c027
L		 1297 case PROCESSOR_GENERIC32:
1298 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1299 with nops. */
1300 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1301 patt = alt_patt;
ccc9c027
L		 1302 else
1303 patt = f32_patt;
1304 break;
76bc74dc
L		 1305 case PROCESSOR_PENTIUMPRO:
1306 case PROCESSOR_PENTIUM4:
1307 case PROCESSOR_NOCONA:
1308 case PROCESSOR_CORE:
ef05d495 1309 case PROCESSOR_CORE2:
bd5295b2 1310 case PROCESSOR_COREI7:
3632d14b 1311 case PROCESSOR_L1OM:
7a9068fe 1312 case PROCESSOR_K1OM:
22109423 1313 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1314 patt = alt_patt;
ccc9c027
L		 1315 else
1316 patt = f32_patt;
1317 break;
1318 case PROCESSOR_GENERIC64:
80b8656c 1319 patt = alt_patt;
ccc9c027 1320 break;
4eed87de 1321 }
ccc9c027
L		 1322 }
1323
76bc74dc
L		 1324 if (patt == f32_patt)
1325 {
1326 /* If the padding is less than 15 bytes, we use the normal
1327 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1328 its offset. */
1329 int limit;
76ba9986 1330
711eedef
L		 1331 /* For 64bit, the limit is 3 bytes. */
1332 if (flag_code == CODE_64BIT
1333 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1334 limit = 3;
1335 else
1336 limit = 15;
1337 if (count < limit)
76bc74dc
L		 1338 memcpy (fragP->fr_literal + fragP->fr_fix,
1339 patt[count - 1], count);
1340 else
1341 {
1342 memcpy (fragP->fr_literal + fragP->fr_fix,
1343 jump_31, count);
1344 /* Adjust jump offset. */
1345 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1346 }
1347 }
1348 else
1349 {
80b8656c
L		 1350 /* Maximum length of an instruction is 10 byte. If the
1351 padding is greater than 10 bytes and we don't use jump,
76bc74dc
L		 1352 we have to break it into smaller pieces. */
1353 int padding = count;
80b8656c 1354 while (padding > 10)
76bc74dc 1355 {
80b8656c 1356 padding -= 10;
76bc74dc 1357 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
80b8656c 1358 patt [9], 10);
76bc74dc
L		 1359 }
1360
1361 if (padding)
1362 memcpy (fragP->fr_literal + fragP->fr_fix,
1363 patt [padding - 1], padding);
1364 }
ccc9c027 1365 }
33fef721 1366 fragP->fr_var = count;
252b5132
RH		 1367}
1368
c6fb90c8 1369static INLINE int
0dfbf9d7 1370operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1371{
0dfbf9d7 1372 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1373 {
1374 case 3:
0dfbf9d7 1375 if (x->array[2])
c6fb90c8 1376 return 0;
1a0670f3 1377 /* Fall through. */
c6fb90c8 1378 case 2:
0dfbf9d7 1379 if (x->array[1])
c6fb90c8 1380 return 0;
1a0670f3 1381 /* Fall through. */
c6fb90c8 1382 case 1:
0dfbf9d7 1383 return !x->array[0];
c6fb90c8
L		 1384 default:
1385 abort ();
1386 }
40fb9820
L		 1387}
1388
c6fb90c8 1389static INLINE void
0dfbf9d7 1390operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1391{
0dfbf9d7 1392 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1393 {
1394 case 3:
0dfbf9d7 1395 x->array[2] = v;
1a0670f3 1396 /* Fall through. */
c6fb90c8 1397 case 2:
0dfbf9d7 1398 x->array[1] = v;
1a0670f3 1399 /* Fall through. */
c6fb90c8 1400 case 1:
0dfbf9d7 1401 x->array[0] = v;
1a0670f3 1402 /* Fall through. */
c6fb90c8
L		 1403 break;
1404 default:
1405 abort ();
1406 }
1407}
40fb9820 1408
c6fb90c8 1409static INLINE int
0dfbf9d7
L		 1410operand_type_equal (const union i386_operand_type *x,
1411 const union i386_operand_type *y)
c6fb90c8 1412{
0dfbf9d7 1413 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1414 {
1415 case 3:
0dfbf9d7 1416 if (x->array[2] != y->array[2])
c6fb90c8 1417 return 0;
1a0670f3 1418 /* Fall through. */
c6fb90c8 1419 case 2:
0dfbf9d7 1420 if (x->array[1] != y->array[1])
c6fb90c8 1421 return 0;
1a0670f3 1422 /* Fall through. */
c6fb90c8 1423 case 1:
0dfbf9d7 1424 return x->array[0] == y->array[0];
c6fb90c8
L		 1425 break;
1426 default:
1427 abort ();
1428 }
1429}
40fb9820 1430
0dfbf9d7
L		 1431static INLINE int
1432cpu_flags_all_zero (const union i386_cpu_flags *x)
1433{
1434 switch (ARRAY_SIZE(x->array))
1435 {
1436 case 3:
1437 if (x->array[2])
1438 return 0;
1a0670f3 1439 /* Fall through. */
0dfbf9d7
L		 1440 case 2:
1441 if (x->array[1])
1442 return 0;
1a0670f3 1443 /* Fall through. */
0dfbf9d7
L		 1444 case 1:
1445 return !x->array[0];
1446 default:
1447 abort ();
1448 }
1449}
1450
0dfbf9d7
L		 1451static INLINE int
1452cpu_flags_equal (const union i386_cpu_flags *x,
1453 const union i386_cpu_flags *y)
1454{
1455 switch (ARRAY_SIZE(x->array))
1456 {
1457 case 3:
1458 if (x->array[2] != y->array[2])
1459 return 0;
1a0670f3 1460 /* Fall through. */
0dfbf9d7
L		 1461 case 2:
1462 if (x->array[1] != y->array[1])
1463 return 0;
1a0670f3 1464 /* Fall through. */
0dfbf9d7
L		 1465 case 1:
1466 return x->array[0] == y->array[0];
1467 break;
1468 default:
1469 abort ();
1470 }
1471}
c6fb90c8
L		 1472
1473static INLINE int
1474cpu_flags_check_cpu64 (i386_cpu_flags f)
1475{
1476 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1477 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1478}
1479
c6fb90c8
L		 1480static INLINE i386_cpu_flags
1481cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1482{
c6fb90c8
L		 1483 switch (ARRAY_SIZE (x.array))
1484 {
1485 case 3:
1486 x.array [2] &= y.array [2];
1a0670f3 1487 /* Fall through. */
c6fb90c8
L		 1488 case 2:
1489 x.array [1] &= y.array [1];
1a0670f3 1490 /* Fall through. */
c6fb90c8
L		 1491 case 1:
1492 x.array [0] &= y.array [0];
1493 break;
1494 default:
1495 abort ();
1496 }
1497 return x;
1498}
40fb9820 1499
c6fb90c8
L		 1500static INLINE i386_cpu_flags
1501cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1502{
c6fb90c8 1503 switch (ARRAY_SIZE (x.array))
40fb9820 1504 {
c6fb90c8
L		 1505 case 3:
1506 x.array [2] |= y.array [2];
1a0670f3 1507 /* Fall through. */
c6fb90c8
L		 1508 case 2:
1509 x.array [1] |= y.array [1];
1a0670f3 1510 /* Fall through. */
c6fb90c8
L		 1511 case 1:
1512 x.array [0] |= y.array [0];
40fb9820
L		 1513 break;
1514 default:
1515 abort ();
1516 }
40fb9820
L		 1517 return x;
1518}
1519
309d3373
JB		 1520static INLINE i386_cpu_flags
1521cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1522{
1523 switch (ARRAY_SIZE (x.array))
1524 {
1525 case 3:
1526 x.array [2] &= ~y.array [2];
1a0670f3 1527 /* Fall through. */
309d3373
JB		 1528 case 2:
1529 x.array [1] &= ~y.array [1];
1a0670f3 1530 /* Fall through. */
309d3373
JB		 1531 case 1:
1532 x.array [0] &= ~y.array [0];
1533 break;
1534 default:
1535 abort ();
1536 }
1537 return x;
1538}
1539
c0f3af97
L		 1540#define CPU_FLAGS_ARCH_MATCH 0x1
1541#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1542#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1543#define CPU_FLAGS_PCLMUL_MATCH 0x8
1544#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1545
a5ff0eb2 1546#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1547 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1548 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1549#define CPU_FLAGS_PERFECT_MATCH \
1550 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1551
1552/* Return CPU flags match bits. */
3629bb00 1553
40fb9820 1554static int
d3ce72d0 1555cpu_flags_match (const insn_template *t)
40fb9820 1556{
c0f3af97
L		 1557 i386_cpu_flags x = t->cpu_flags;
1558 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1559
1560 x.bitfield.cpu64 = 0;
1561 x.bitfield.cpuno64 = 0;
1562
0dfbf9d7 1563 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1564 {
1565 /* This instruction is available on all archs. */
1566 match |= CPU_FLAGS_32BIT_MATCH;
1567 }
3629bb00
L		 1568 else
1569 {
c0f3af97 1570 /* This instruction is available only on some archs. */
3629bb00
L		 1571 i386_cpu_flags cpu = cpu_arch_flags;
1572
3629bb00 1573 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1574 if (!cpu_flags_all_zero (&cpu))
1575 {
a5ff0eb2
L		 1576 if (x.bitfield.cpuavx)
1577 {
ce2f5b3c 1578 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1579 if (cpu.bitfield.cpuavx)
1580 {
1581 /* Check SSE2AVX. */
1582 if (!t->opcode_modifier.sse2avx|| sse2avx)
1583 {
1584 match |= (CPU_FLAGS_ARCH_MATCH
1585 | CPU_FLAGS_AVX_MATCH);
1586 /* Check AES. */
1587 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1588 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1589 /* Check PCLMUL. */
1590 if (!x.bitfield.cpupclmul
1591 || cpu.bitfield.cpupclmul)
1592 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1593 }
1594 }
1595 else
1596 match |= CPU_FLAGS_ARCH_MATCH;
1597 }
73b090a9
L		 1598 else if (x.bitfield.cpuavx512vl)
1599 {
1600 /* Match AVX512VL. */
1601 if (cpu.bitfield.cpuavx512vl)
1602 {
1603 /* Need another match. */
1604 cpu.bitfield.cpuavx512vl = 0;
1605 if (!cpu_flags_all_zero (&cpu))
1606 match |= CPU_FLAGS_32BIT_MATCH;
1607 else
1608 match |= CPU_FLAGS_ARCH_MATCH;
1609 }
1610 else
1611 match |= CPU_FLAGS_ARCH_MATCH;
1612 }
a5ff0eb2 1613 else
c0f3af97
L		 1614 match |= CPU_FLAGS_32BIT_MATCH;
1615 }
3629bb00 1616 }
c0f3af97 1617 return match;
40fb9820
L		 1618}
1619
c6fb90c8
L		 1620static INLINE i386_operand_type
1621operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1622{
c6fb90c8
L		 1623 switch (ARRAY_SIZE (x.array))
1624 {
1625 case 3:
1626 x.array [2] &= y.array [2];
1a0670f3 1627 /* Fall through. */
c6fb90c8
L		 1628 case 2:
1629 x.array [1] &= y.array [1];
1a0670f3 1630 /* Fall through. */
c6fb90c8
L		 1631 case 1:
1632 x.array [0] &= y.array [0];
1633 break;
1634 default:
1635 abort ();
1636 }
1637 return x;
40fb9820
L		 1638}
1639
c6fb90c8
L		 1640static INLINE i386_operand_type
1641operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1642{
c6fb90c8 1643 switch (ARRAY_SIZE (x.array))
40fb9820 1644 {
c6fb90c8
L		 1645 case 3:
1646 x.array [2] |= y.array [2];
1a0670f3 1647 /* Fall through. */
c6fb90c8
L		 1648 case 2:
1649 x.array [1] |= y.array [1];
1a0670f3 1650 /* Fall through. */
c6fb90c8
L		 1651 case 1:
1652 x.array [0] |= y.array [0];
40fb9820
L		 1653 break;
1654 default:
1655 abort ();
1656 }
c6fb90c8
L		 1657 return x;
1658}
40fb9820 1659
c6fb90c8
L		 1660static INLINE i386_operand_type
1661operand_type_xor (i386_operand_type x, i386_operand_type y)
1662{
1663 switch (ARRAY_SIZE (x.array))
1664 {
1665 case 3:
1666 x.array [2] ^= y.array [2];
1a0670f3 1667 /* Fall through. */
c6fb90c8
L		 1668 case 2:
1669 x.array [1] ^= y.array [1];
1a0670f3 1670 /* Fall through. */
c6fb90c8
L		 1671 case 1:
1672 x.array [0] ^= y.array [0];
1673 break;
1674 default:
1675 abort ();
1676 }
40fb9820
L		 1677 return x;
1678}
1679
1680static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1681static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1682static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1683static const i386_operand_type inoutportreg
1684 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1685static const i386_operand_type reg16_inoutportreg
1686 = OPERAND_TYPE_REG16_INOUTPORTREG;
1687static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1688static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1689static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1690static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1691static const i386_operand_type anydisp
1692 = OPERAND_TYPE_ANYDISP;
40fb9820 1693static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1694static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1695static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1696static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1697static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1698static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1699static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1700static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1701static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1702static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1703static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1704static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1705static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1706static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1707
1708enum operand_type
1709{
1710 reg,
40fb9820
L		 1711 imm,
1712 disp,
1713 anymem
1714};
1715
c6fb90c8 1716static INLINE int
40fb9820
L		 1717operand_type_check (i386_operand_type t, enum operand_type c)
1718{
1719 switch (c)
1720 {
1721 case reg:
1722 return (t.bitfield.reg8
1723 || t.bitfield.reg16
1724 || t.bitfield.reg32
1725 || t.bitfield.reg64);
1726
40fb9820
L		 1727 case imm:
1728 return (t.bitfield.imm8
1729 || t.bitfield.imm8s
1730 || t.bitfield.imm16
1731 || t.bitfield.imm32
1732 || t.bitfield.imm32s
1733 || t.bitfield.imm64);
1734
1735 case disp:
1736 return (t.bitfield.disp8
1737 || t.bitfield.disp16
1738 || t.bitfield.disp32
1739 || t.bitfield.disp32s
1740 || t.bitfield.disp64);
1741
1742 case anymem:
1743 return (t.bitfield.disp8
1744 || t.bitfield.disp16
1745 || t.bitfield.disp32
1746 || t.bitfield.disp32s
1747 || t.bitfield.disp64
1748 || t.bitfield.baseindex);
1749
1750 default:
1751 abort ();
1752 }
2cfe26b6
AM		 1753
1754 return 0;
40fb9820
L		 1755}
1756
5c07affc
L		 1757/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1758 operand J for instruction template T. */
1759
1760static INLINE int
d3ce72d0 1761match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1762{
1763 return !((i.types[j].bitfield.byte
1764 && !t->operand_types[j].bitfield.byte)
1765 || (i.types[j].bitfield.word
1766 && !t->operand_types[j].bitfield.word)
1767 || (i.types[j].bitfield.dword
1768 && !t->operand_types[j].bitfield.dword)
1769 || (i.types[j].bitfield.qword
1770 && !t->operand_types[j].bitfield.qword));
1771}
1772
1773/* Return 1 if there is no conflict in any size on operand J for
1774 instruction template T. */
1775
1776static INLINE int
d3ce72d0 1777match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1778{
1779 return (match_reg_size (t, j)
1780 && !((i.types[j].bitfield.unspecified
af508cb9 1781 && !i.broadcast
5c07affc
L		 1782 && !t->operand_types[j].bitfield.unspecified)
1783 || (i.types[j].bitfield.fword
1784 && !t->operand_types[j].bitfield.fword)
1785 || (i.types[j].bitfield.tbyte
1786 && !t->operand_types[j].bitfield.tbyte)
1787 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1788 && !t->operand_types[j].bitfield.xmmword)
1789 || (i.types[j].bitfield.ymmword
43234a1e
L		 1790 && !t->operand_types[j].bitfield.ymmword)
1791 || (i.types[j].bitfield.zmmword
1792 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1793}
1794
1795/* Return 1 if there is no size conflict on any operands for
1796 instruction template T. */
1797
1798static INLINE int
d3ce72d0 1799operand_size_match (const insn_template *t)
5c07affc
L		 1800{
1801 unsigned int j;
1802 int match = 1;
1803
1804 /* Don't check jump instructions. */
1805 if (t->opcode_modifier.jump
1806 || t->opcode_modifier.jumpbyte
1807 || t->opcode_modifier.jumpdword
1808 || t->opcode_modifier.jumpintersegment)
1809 return match;
1810
1811 /* Check memory and accumulator operand size. */
1812 for (j = 0; j < i.operands; j++)
1813 {
1814 if (t->operand_types[j].bitfield.anysize)
1815 continue;
1816
1817 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1818 {
1819 match = 0;
1820 break;
1821 }
1822
1823 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1824 {
1825 match = 0;
1826 break;
1827 }
1828 }
1829
891edac4 1830 if (match)
5c07affc 1831 return match;
891edac4
L		 1832 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1833 {
1834mismatch:
86e026a4 1835 i.error = operand_size_mismatch;
891edac4
L		 1836 return 0;
1837 }
5c07affc
L		 1838
1839 /* Check reverse. */
9c2799c2 1840 gas_assert (i.operands == 2);
5c07affc
L		 1841
1842 match = 1;
1843 for (j = 0; j < 2; j++)
1844 {
1845 if (t->operand_types[j].bitfield.acc
1846 && !match_reg_size (t, j ? 0 : 1))
891edac4 1847 goto mismatch;
5c07affc
L		 1848
1849 if (i.types[j].bitfield.mem
1850 && !match_mem_size (t, j ? 0 : 1))
891edac4 1851 goto mismatch;
5c07affc
L		 1852 }
1853
1854 return match;
1855}
1856
c6fb90c8 1857static INLINE int
40fb9820
L		 1858operand_type_match (i386_operand_type overlap,
1859 i386_operand_type given)
1860{
1861 i386_operand_type temp = overlap;
1862
1863 temp.bitfield.jumpabsolute = 0;
7d5e4556 1864 temp.bitfield.unspecified = 0;
5c07affc
L		 1865 temp.bitfield.byte = 0;
1866 temp.bitfield.word = 0;
1867 temp.bitfield.dword = 0;
1868 temp.bitfield.fword = 0;
1869 temp.bitfield.qword = 0;
1870 temp.bitfield.tbyte = 0;
1871 temp.bitfield.xmmword = 0;
c0f3af97 1872 temp.bitfield.ymmword = 0;
43234a1e 1873 temp.bitfield.zmmword = 0;
0dfbf9d7 1874 if (operand_type_all_zero (&temp))
891edac4 1875 goto mismatch;
40fb9820 1876
891edac4
L		 1877 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1878 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1879 return 1;
1880
1881mismatch:
a65babc9 1882 i.error = operand_type_mismatch;
891edac4 1883 return 0;
40fb9820
L		 1884}
1885
7d5e4556 1886/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1887 unless the expected operand type register overlap is null.
1888 Note that Acc in a template matches every size of reg. */
1889
c6fb90c8 1890static INLINE int
40fb9820
L		 1891operand_type_register_match (i386_operand_type m0,
1892 i386_operand_type g0,
1893 i386_operand_type t0,
1894 i386_operand_type m1,
1895 i386_operand_type g1,
1896 i386_operand_type t1)
1897{
1898 if (!operand_type_check (g0, reg))
1899 return 1;
1900
1901 if (!operand_type_check (g1, reg))
1902 return 1;
1903
1904 if (g0.bitfield.reg8 == g1.bitfield.reg8
1905 && g0.bitfield.reg16 == g1.bitfield.reg16
1906 && g0.bitfield.reg32 == g1.bitfield.reg32
1907 && g0.bitfield.reg64 == g1.bitfield.reg64)
1908 return 1;
1909
1910 if (m0.bitfield.acc)
1911 {
1912 t0.bitfield.reg8 = 1;
1913 t0.bitfield.reg16 = 1;
1914 t0.bitfield.reg32 = 1;
1915 t0.bitfield.reg64 = 1;
1916 }
1917
1918 if (m1.bitfield.acc)
1919 {
1920 t1.bitfield.reg8 = 1;
1921 t1.bitfield.reg16 = 1;
1922 t1.bitfield.reg32 = 1;
1923 t1.bitfield.reg64 = 1;
1924 }
1925
891edac4
L		 1926 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1927 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1928 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1929 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1930 return 1;
1931
a65babc9 1932 i.error = register_type_mismatch;
891edac4
L		 1933
1934 return 0;
40fb9820
L		 1935}
1936
4c692bc7
JB		 1937static INLINE unsigned int
1938register_number (const reg_entry *r)
1939{
1940 unsigned int nr = r->reg_num;
1941
1942 if (r->reg_flags & RegRex)
1943 nr += 8;
1944
200cbe0f
L		 1945 if (r->reg_flags & RegVRex)
1946 nr += 16;
1947
4c692bc7
JB		 1948 return nr;
1949}
1950
252b5132 1951static INLINE unsigned int
40fb9820 1952mode_from_disp_size (i386_operand_type t)
252b5132 1953{
43234a1e 1954 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1955 return 1;
1956 else if (t.bitfield.disp16
1957 || t.bitfield.disp32
1958 || t.bitfield.disp32s)
1959 return 2;
1960 else
1961 return 0;
252b5132
RH		 1962}
1963
1964static INLINE int
65879393 1965fits_in_signed_byte (addressT num)
252b5132 1966{
65879393 1967 return num + 0x80 <= 0xff;
47926f60 1968}
252b5132
RH		 1969
1970static INLINE int
65879393 1971fits_in_unsigned_byte (addressT num)
252b5132 1972{
65879393 1973 return num <= 0xff;
47926f60 1974}
252b5132
RH		 1975
1976static INLINE int
65879393 1977fits_in_unsigned_word (addressT num)
252b5132 1978{
65879393 1979 return num <= 0xffff;
47926f60 1980}
252b5132
RH		 1981
1982static INLINE int
65879393 1983fits_in_signed_word (addressT num)
252b5132 1984{
65879393 1985 return num + 0x8000 <= 0xffff;
47926f60 1986}
2a962e6d 1987
3e73aa7c 1988static INLINE int
65879393 1989fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1990{
1991#ifndef BFD64
1992 return 1;
1993#else
65879393 1994 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 1995#endif
1996} /* fits_in_signed_long() */
2a962e6d 1997
3e73aa7c 1998static INLINE int
65879393 1999fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2000{
2001#ifndef BFD64
2002 return 1;
2003#else
65879393 2004 return num <= 0xffffffff;
3e73aa7c
JH		 2005#endif
2006} /* fits_in_unsigned_long() */
252b5132 2007
43234a1e
L		 2008static INLINE int
2009fits_in_vec_disp8 (offsetT num)
2010{
2011 int shift = i.memshift;
2012 unsigned int mask;
2013
2014 if (shift == -1)
2015 abort ();
2016
2017 mask = (1 << shift) - 1;
2018
2019 /* Return 0 if NUM isn't properly aligned. */
2020 if ((num & mask))
2021 return 0;
2022
2023 /* Check if NUM will fit in 8bit after shift. */
2024 return fits_in_signed_byte (num >> shift);
2025}
2026
a683cc34
SP		 2027static INLINE int
2028fits_in_imm4 (offsetT num)
2029{
2030 return (num & 0xf) == num;
2031}
2032
40fb9820 2033static i386_operand_type
e3bb37b5 2034smallest_imm_type (offsetT num)
252b5132 2035{
40fb9820 2036 i386_operand_type t;
7ab9ffdd 2037
0dfbf9d7 2038 operand_type_set (&t, 0);
40fb9820
L		 2039 t.bitfield.imm64 = 1;
2040
2041 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2042 {
2043 /* This code is disabled on the 486 because all the Imm1 forms
2044 in the opcode table are slower on the i486. They're the
2045 versions with the implicitly specified single-position
2046 displacement, which has another syntax if you really want to
2047 use that form. */
40fb9820
L		 2048 t.bitfield.imm1 = 1;
2049 t.bitfield.imm8 = 1;
2050 t.bitfield.imm8s = 1;
2051 t.bitfield.imm16 = 1;
2052 t.bitfield.imm32 = 1;
2053 t.bitfield.imm32s = 1;
2054 }
2055 else if (fits_in_signed_byte (num))
2056 {
2057 t.bitfield.imm8 = 1;
2058 t.bitfield.imm8s = 1;
2059 t.bitfield.imm16 = 1;
2060 t.bitfield.imm32 = 1;
2061 t.bitfield.imm32s = 1;
2062 }
2063 else if (fits_in_unsigned_byte (num))
2064 {
2065 t.bitfield.imm8 = 1;
2066 t.bitfield.imm16 = 1;
2067 t.bitfield.imm32 = 1;
2068 t.bitfield.imm32s = 1;
2069 }
2070 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2071 {
2072 t.bitfield.imm16 = 1;
2073 t.bitfield.imm32 = 1;
2074 t.bitfield.imm32s = 1;
2075 }
2076 else if (fits_in_signed_long (num))
2077 {
2078 t.bitfield.imm32 = 1;
2079 t.bitfield.imm32s = 1;
2080 }
2081 else if (fits_in_unsigned_long (num))
2082 t.bitfield.imm32 = 1;
2083
2084 return t;
47926f60 2085}
252b5132 2086
847f7ad4 2087static offsetT
e3bb37b5 2088offset_in_range (offsetT val, int size)
847f7ad4 2089{
508866be 2090 addressT mask;
ba2adb93 2091
847f7ad4
AM		 2092 switch (size)
2093 {
508866be
L		 2094 case 1: mask = ((addressT) 1 << 8) - 1; break;
2095 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2096 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2097#ifdef BFD64
2098 case 8: mask = ((addressT) 2 << 63) - 1; break;
2099#endif
47926f60 2100 default: abort ();
847f7ad4
AM		 2101 }
2102
9de868bf
L		 2103#ifdef BFD64
2104 /* If BFD64, sign extend val for 32bit address mode. */
2105 if (flag_code != CODE_64BIT
2106 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2107 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2108 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2109#endif
ba2adb93 2110
47926f60 2111 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2112 {
2113 char buf1[40], buf2[40];
2114
2115 sprint_value (buf1, val);
2116 sprint_value (buf2, val & mask);
2117 as_warn (_("%s shortened to %s"), buf1, buf2);
2118 }
2119 return val & mask;
2120}
2121
c32fa91d
L		 2122enum PREFIX_GROUP
2123{
2124 PREFIX_EXIST = 0,
2125 PREFIX_LOCK,
2126 PREFIX_REP,
2127 PREFIX_OTHER
2128};
2129
2130/* Returns
2131 a. PREFIX_EXIST if attempting to add a prefix where one from the
2132 same class already exists.
2133 b. PREFIX_LOCK if lock prefix is added.
2134 c. PREFIX_REP if rep/repne prefix is added.
2135 d. PREFIX_OTHER if other prefix is added.
2136 */
2137
2138static enum PREFIX_GROUP
e3bb37b5 2139add_prefix (unsigned int prefix)
252b5132 2140{
c32fa91d 2141 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2142 unsigned int q;
252b5132 2143
29b0f896
AM		 2144 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2145 && flag_code == CODE_64BIT)
b1905489 2146 {
161a04f6
L		 2147 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2148 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2149 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2150 ret = PREFIX_EXIST;
b1905489
JB		 2151 q = REX_PREFIX;
2152 }
3e73aa7c 2153 else
b1905489
JB		 2154 {
2155 switch (prefix)
2156 {
2157 default:
2158 abort ();
2159
2160 case CS_PREFIX_OPCODE:
2161 case DS_PREFIX_OPCODE:
2162 case ES_PREFIX_OPCODE:
2163 case FS_PREFIX_OPCODE:
2164 case GS_PREFIX_OPCODE:
2165 case SS_PREFIX_OPCODE:
2166 q = SEG_PREFIX;
2167 break;
2168
2169 case REPNE_PREFIX_OPCODE:
2170 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2171 q = REP_PREFIX;
2172 ret = PREFIX_REP;
2173 break;
2174
b1905489 2175 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2176 q = LOCK_PREFIX;
2177 ret = PREFIX_LOCK;
b1905489
JB		 2178 break;
2179
2180 case FWAIT_OPCODE:
2181 q = WAIT_PREFIX;
2182 break;
2183
2184 case ADDR_PREFIX_OPCODE:
2185 q = ADDR_PREFIX;
2186 break;
2187
2188 case DATA_PREFIX_OPCODE:
2189 q = DATA_PREFIX;
2190 break;
2191 }
2192 if (i.prefix[q] != 0)
c32fa91d 2193 ret = PREFIX_EXIST;
b1905489 2194 }
252b5132 2195
b1905489 2196 if (ret)
252b5132 2197 {
b1905489
JB		 2198 if (!i.prefix[q])
2199 ++i.prefixes;
2200 i.prefix[q] |= prefix;
252b5132 2201 }
b1905489
JB		 2202 else
2203 as_bad (_("same type of prefix used twice"));
252b5132 2204
252b5132
RH		 2205 return ret;
2206}
2207
2208static void
78f12dd3 2209update_code_flag (int value, int check)
eecb386c 2210{
78f12dd3
L		 2211 PRINTF_LIKE ((*as_error));
2212
1e9cc1c2 2213 flag_code = (enum flag_code) value;
40fb9820
L		 2214 if (flag_code == CODE_64BIT)
2215 {
2216 cpu_arch_flags.bitfield.cpu64 = 1;
2217 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2218 }
2219 else
2220 {
2221 cpu_arch_flags.bitfield.cpu64 = 0;
2222 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2223 }
2224 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2225 {
78f12dd3
L		 2226 if (check)
2227 as_error = as_fatal;
2228 else
2229 as_error = as_bad;
2230 (*as_error) (_("64bit mode not supported on `%s'."),
2231 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2232 }
40fb9820 2233 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2234 {
78f12dd3
L		 2235 if (check)
2236 as_error = as_fatal;
2237 else
2238 as_error = as_bad;
2239 (*as_error) (_("32bit mode not supported on `%s'."),
2240 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2241 }
eecb386c
AM		 2242 stackop_size = '\0';
2243}
2244
78f12dd3
L		 2245static void
2246set_code_flag (int value)
2247{
2248 update_code_flag (value, 0);
2249}
2250
eecb386c 2251static void
e3bb37b5 2252set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2253{
1e9cc1c2 2254 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2255 if (flag_code != CODE_16BIT)
2256 abort ();
2257 cpu_arch_flags.bitfield.cpu64 = 0;
2258 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2259 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2260}
2261
2262static void
e3bb37b5 2263set_intel_syntax (int syntax_flag)
252b5132
RH		 2264{
2265 /* Find out if register prefixing is specified. */
2266 int ask_naked_reg = 0;
2267
2268 SKIP_WHITESPACE ();
29b0f896 2269 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2270 {
d02603dc
NC		 2271 char *string;
2272 int e = get_symbol_name (&string);
252b5132 2273
47926f60 2274 if (strcmp (string, "prefix") == 0)
252b5132 2275 ask_naked_reg = 1;
47926f60 2276 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2277 ask_naked_reg = -1;
2278 else
d0b47220 2279 as_bad (_("bad argument to syntax directive."));
d02603dc 2280 (void) restore_line_pointer (e);
252b5132
RH		 2281 }
2282 demand_empty_rest_of_line ();
c3332e24 2283
252b5132
RH		 2284 intel_syntax = syntax_flag;
2285
2286 if (ask_naked_reg == 0)
f86103b7
AM		 2287 allow_naked_reg = (intel_syntax
2288 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2289 else
2290 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2291
ee86248c 2292 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2293
e4a3b5a4 2294 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2295 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2296 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2297}
2298
1efbbeb4
L		 2299static void
2300set_intel_mnemonic (int mnemonic_flag)
2301{
e1d4d893 2302 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2303}
2304
db51cc60
L		 2305static void
2306set_allow_index_reg (int flag)
2307{
2308 allow_index_reg = flag;
2309}
2310
cb19c032 2311static void
7bab8ab5 2312set_check (int what)
cb19c032 2313{
7bab8ab5
JB		 2314 enum check_kind *kind;
2315 const char *str;
2316
2317 if (what)
2318 {
2319 kind = &operand_check;
2320 str = "operand";
2321 }
2322 else
2323 {
2324 kind = &sse_check;
2325 str = "sse";
2326 }
2327
cb19c032
L		 2328 SKIP_WHITESPACE ();
2329
2330 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2331 {
d02603dc
NC		 2332 char *string;
2333 int e = get_symbol_name (&string);
cb19c032
L		 2334
2335 if (strcmp (string, "none") == 0)
7bab8ab5 2336 *kind = check_none;
cb19c032 2337 else if (strcmp (string, "warning") == 0)
7bab8ab5 2338 *kind = check_warning;
cb19c032 2339 else if (strcmp (string, "error") == 0)
7bab8ab5 2340 *kind = check_error;
cb19c032 2341 else
7bab8ab5 2342 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2343 (void) restore_line_pointer (e);
cb19c032
L		 2344 }
2345 else
7bab8ab5 2346 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2347
2348 demand_empty_rest_of_line ();
2349}
2350
8a9036a4
L		 2351static void
2352check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2353 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2354{
2355#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2356 static const char *arch;
2357
2358 /* Intel LIOM is only supported on ELF. */
2359 if (!IS_ELF)
2360 return;
2361
2362 if (!arch)
2363 {
2364 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2365 use default_arch. */
2366 arch = cpu_arch_name;
2367 if (!arch)
2368 arch = default_arch;
2369 }
2370
81486035
L		 2371 /* If we are targeting Intel MCU, we must enable it. */
2372 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2373 || new_flag.bitfield.cpuiamcu)
2374 return;
2375
3632d14b 2376 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2377 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2378 || new_flag.bitfield.cpul1om)
8a9036a4 2379 return;
76ba9986 2380
7a9068fe
L		 2381 /* If we are targeting Intel K1OM, we must enable it. */
2382 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2383 || new_flag.bitfield.cpuk1om)
2384 return;
2385
8a9036a4
L		 2386 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2387#endif
2388}
2389
e413e4e9 2390static void
e3bb37b5 2391set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2392{
47926f60 2393 SKIP_WHITESPACE ();
e413e4e9 2394
29b0f896 2395 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2396 {
d02603dc
NC		 2397 char *string;
2398 int e = get_symbol_name (&string);
91d6fa6a 2399 unsigned int j;
40fb9820 2400 i386_cpu_flags flags;
e413e4e9 2401
91d6fa6a 2402 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2403 {
91d6fa6a 2404 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2405 {
91d6fa6a 2406 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2407
5c6af06e
JB		 2408 if (*string != '.')
2409 {
91d6fa6a 2410 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2411 cpu_sub_arch_name = NULL;
91d6fa6a 2412 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2413 if (flag_code == CODE_64BIT)
2414 {
2415 cpu_arch_flags.bitfield.cpu64 = 1;
2416 cpu_arch_flags.bitfield.cpuno64 = 0;
2417 }
2418 else
2419 {
2420 cpu_arch_flags.bitfield.cpu64 = 0;
2421 cpu_arch_flags.bitfield.cpuno64 = 1;
2422 }
91d6fa6a
NC		 2423 cpu_arch_isa = cpu_arch[j].type;
2424 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2425 if (!cpu_arch_tune_set)
2426 {
2427 cpu_arch_tune = cpu_arch_isa;
2428 cpu_arch_tune_flags = cpu_arch_isa_flags;
2429 }
5c6af06e
JB		 2430 break;
2431 }
40fb9820 2432
293f5f65
L		 2433 flags = cpu_flags_or (cpu_arch_flags,
2434 cpu_arch[j].flags);
81486035 2435
5b64d091 2436 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2437 {
6305a203
L		 2438 if (cpu_sub_arch_name)
2439 {
2440 char *name = cpu_sub_arch_name;
2441 cpu_sub_arch_name = concat (name,
91d6fa6a 2442 cpu_arch[j].name,
1bf57e9f 2443 (const char *) NULL);
6305a203
L		 2444 free (name);
2445 }
2446 else
91d6fa6a 2447 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2448 cpu_arch_flags = flags;
a586129e 2449 cpu_arch_isa_flags = flags;
5c6af06e 2450 }
d02603dc 2451 (void) restore_line_pointer (e);
5c6af06e
JB		 2452 demand_empty_rest_of_line ();
2453 return;
e413e4e9
AM		 2454 }
2455 }
293f5f65
L		 2456
2457 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2458 {
2459 /* Disable an ISA entension. */
2460 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2461 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2462 {
2463 flags = cpu_flags_and_not (cpu_arch_flags,
2464 cpu_noarch[j].flags);
2465 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2466 {
2467 if (cpu_sub_arch_name)
2468 {
2469 char *name = cpu_sub_arch_name;
2470 cpu_sub_arch_name = concat (name, string,
2471 (const char *) NULL);
2472 free (name);
2473 }
2474 else
2475 cpu_sub_arch_name = xstrdup (string);
2476 cpu_arch_flags = flags;
2477 cpu_arch_isa_flags = flags;
2478 }
2479 (void) restore_line_pointer (e);
2480 demand_empty_rest_of_line ();
2481 return;
2482 }
2483
2484 j = ARRAY_SIZE (cpu_arch);
2485 }
2486
91d6fa6a 2487 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2488 as_bad (_("no such architecture: `%s'"), string);
2489
2490 *input_line_pointer = e;
2491 }
2492 else
2493 as_bad (_("missing cpu architecture"));
2494
fddf5b5b
AM		 2495 no_cond_jump_promotion = 0;
2496 if (*input_line_pointer == ','
29b0f896 2497 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2498 {
d02603dc
NC		 2499 char *string;
2500 char e;
2501
2502 ++input_line_pointer;
2503 e = get_symbol_name (&string);
fddf5b5b
AM		 2504
2505 if (strcmp (string, "nojumps") == 0)
2506 no_cond_jump_promotion = 1;
2507 else if (strcmp (string, "jumps") == 0)
2508 ;
2509 else
2510 as_bad (_("no such architecture modifier: `%s'"), string);
2511
d02603dc 2512 (void) restore_line_pointer (e);
fddf5b5b
AM		 2513 }
2514
e413e4e9
AM		 2515 demand_empty_rest_of_line ();
2516}
2517
8a9036a4
L		 2518enum bfd_architecture
2519i386_arch (void)
2520{
3632d14b 2521 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2522 {
2523 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2524 || flag_code != CODE_64BIT)
2525 as_fatal (_("Intel L1OM is 64bit ELF only"));
2526 return bfd_arch_l1om;
2527 }
7a9068fe
L		 2528 else if (cpu_arch_isa == PROCESSOR_K1OM)
2529 {
2530 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2531 || flag_code != CODE_64BIT)
2532 as_fatal (_("Intel K1OM is 64bit ELF only"));
2533 return bfd_arch_k1om;
2534 }
81486035
L		 2535 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2536 {
2537 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2538 || flag_code == CODE_64BIT)
2539 as_fatal (_("Intel MCU is 32bit ELF only"));
2540 return bfd_arch_iamcu;
2541 }
8a9036a4
L		 2542 else
2543 return bfd_arch_i386;
2544}
2545
b9d79e03 2546unsigned long
7016a5d5 2547i386_mach (void)
b9d79e03 2548{
351f65ca 2549 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2550 {
3632d14b 2551 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2552 {
351f65ca
L		 2553 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2554 || default_arch[6] != '\0')
8a9036a4
L		 2555 as_fatal (_("Intel L1OM is 64bit ELF only"));
2556 return bfd_mach_l1om;
2557 }
7a9068fe
L		 2558 else if (cpu_arch_isa == PROCESSOR_K1OM)
2559 {
2560 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2561 || default_arch[6] != '\0')
2562 as_fatal (_("Intel K1OM is 64bit ELF only"));
2563 return bfd_mach_k1om;
2564 }
351f65ca 2565 else if (default_arch[6] == '\0')
8a9036a4 2566 return bfd_mach_x86_64;
351f65ca
L		 2567 else
2568 return bfd_mach_x64_32;
8a9036a4 2569 }
5197d474
L		 2570 else if (!strcmp (default_arch, "i386")
2571 || !strcmp (default_arch, "iamcu"))
81486035
L		 2572 {
2573 if (cpu_arch_isa == PROCESSOR_IAMCU)
2574 {
2575 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2576 as_fatal (_("Intel MCU is 32bit ELF only"));
2577 return bfd_mach_i386_iamcu;
2578 }
2579 else
2580 return bfd_mach_i386_i386;
2581 }
b9d79e03 2582 else
2b5d6a91 2583 as_fatal (_("unknown architecture"));
b9d79e03 2584}
b9d79e03 2585\f
252b5132 2586void
7016a5d5 2587md_begin (void)
252b5132
RH		 2588{
2589 const char *hash_err;
2590
47926f60 2591 /* Initialize op_hash hash table. */
252b5132
RH		 2592 op_hash = hash_new ();
2593
2594 {
d3ce72d0 2595 const insn_template *optab;
29b0f896 2596 templates *core_optab;
252b5132 2597
47926f60
KH		 2598 /* Setup for loop. */
2599 optab = i386_optab;
add39d23 2600 core_optab = XNEW (templates);
252b5132
RH		 2601 core_optab->start = optab;
2602
2603 while (1)
2604 {
2605 ++optab;
2606 if (optab->name == NULL
2607 || strcmp (optab->name, (optab - 1)->name) != 0)
2608 {
2609 /* different name --> ship out current template list;
47926f60 2610 add to hash table; & begin anew. */
252b5132
RH		 2611 core_optab->end = optab;
2612 hash_err = hash_insert (op_hash,
2613 (optab - 1)->name,
5a49b8ac 2614 (void *) core_optab);
252b5132
RH		 2615 if (hash_err)
2616 {
b37df7c4 2617 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2618 (optab - 1)->name,
2619 hash_err);
2620 }
2621 if (optab->name == NULL)
2622 break;
add39d23 2623 core_optab = XNEW (templates);
252b5132
RH		 2624 core_optab->start = optab;
2625 }
2626 }
2627 }
2628
47926f60 2629 /* Initialize reg_hash hash table. */
252b5132
RH		 2630 reg_hash = hash_new ();
2631 {
29b0f896 2632 const reg_entry *regtab;
c3fe08fa 2633 unsigned int regtab_size = i386_regtab_size;
252b5132 2634
c3fe08fa 2635 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2636 {
5a49b8ac 2637 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2638 if (hash_err)
b37df7c4 2639 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2640 regtab->reg_name,
2641 hash_err);
252b5132
RH		 2642 }
2643 }
2644
47926f60 2645 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2646 {
29b0f896
AM		 2647 int c;
2648 char *p;
252b5132
RH		 2649
2650 for (c = 0; c < 256; c++)
2651 {
3882b010 2652 if (ISDIGIT (c))
252b5132
RH		 2653 {
2654 digit_chars[c] = c;
2655 mnemonic_chars[c] = c;
2656 register_chars[c] = c;
2657 operand_chars[c] = c;
2658 }
3882b010 2659 else if (ISLOWER (c))
252b5132
RH		 2660 {
2661 mnemonic_chars[c] = c;
2662 register_chars[c] = c;
2663 operand_chars[c] = c;
2664 }
3882b010 2665 else if (ISUPPER (c))
252b5132 2666 {
3882b010 2667 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2668 register_chars[c] = mnemonic_chars[c];
2669 operand_chars[c] = c;
2670 }
43234a1e
L		 2671 else if (c == '{' || c == '}')
2672 operand_chars[c] = c;
252b5132 2673
3882b010 2674 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2675 identifier_chars[c] = c;
2676 else if (c >= 128)
2677 {
2678 identifier_chars[c] = c;
2679 operand_chars[c] = c;
2680 }
2681 }
2682
2683#ifdef LEX_AT
2684 identifier_chars['@'] = '@';
32137342
NC		 2685#endif
2686#ifdef LEX_QM
2687 identifier_chars['?'] = '?';
2688 operand_chars['?'] = '?';
252b5132 2689#endif
252b5132 2690 digit_chars['-'] = '-';
c0f3af97 2691 mnemonic_chars['_'] = '_';
791fe849 2692 mnemonic_chars['-'] = '-';
0003779b 2693 mnemonic_chars['.'] = '.';
252b5132
RH		 2694 identifier_chars['_'] = '_';
2695 identifier_chars['.'] = '.';
2696
2697 for (p = operand_special_chars; *p != '\0'; p++)
2698 operand_chars[(unsigned char) *p] = *p;
2699 }
2700
a4447b93
RH		 2701 if (flag_code == CODE_64BIT)
2702 {
ca19b261
KT		 2703#if defined (OBJ_COFF) && defined (TE_PE)
2704 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2705 ? 32 : 16);
2706#else
a4447b93 2707 x86_dwarf2_return_column = 16;
ca19b261 2708#endif
61ff971f 2709 x86_cie_data_alignment = -8;
a4447b93
RH		 2710 }
2711 else
2712 {
2713 x86_dwarf2_return_column = 8;
2714 x86_cie_data_alignment = -4;
2715 }
252b5132
RH		 2716}
2717
2718void
e3bb37b5 2719i386_print_statistics (FILE *file)
252b5132
RH		 2720{
2721 hash_print_statistics (file, "i386 opcode", op_hash);
2722 hash_print_statistics (file, "i386 register", reg_hash);
2723}
2724\f
252b5132
RH		 2725#ifdef DEBUG386
2726
ce8a8b2f 2727/* Debugging routines for md_assemble. */
d3ce72d0 2728static void pte (insn_template *);
40fb9820 2729static void pt (i386_operand_type);
e3bb37b5
L		 2730static void pe (expressionS *);
2731static void ps (symbolS *);
252b5132
RH		 2732
2733static void
e3bb37b5 2734pi (char *line, i386_insn *x)
252b5132 2735{
09137c09 2736 unsigned int j;
252b5132
RH		 2737
2738 fprintf (stdout, "%s: template ", line);
2739 pte (&x->tm);
09f131f2
JH		 2740 fprintf (stdout, " address: base %s index %s scale %x\n",
2741 x->base_reg ? x->base_reg->reg_name : "none",
2742 x->index_reg ? x->index_reg->reg_name : "none",
2743 x->log2_scale_factor);
2744 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2745 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2746 fprintf (stdout, " sib: base %x index %x scale %x\n",
2747 x->sib.base, x->sib.index, x->sib.scale);
2748 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2749 (x->rex & REX_W) != 0,
2750 (x->rex & REX_R) != 0,
2751 (x->rex & REX_X) != 0,
2752 (x->rex & REX_B) != 0);
09137c09 2753 for (j = 0; j < x->operands; j++)
252b5132 2754 {
09137c09
SP		 2755 fprintf (stdout, " #%d: ", j + 1);
2756 pt (x->types[j]);
252b5132 2757 fprintf (stdout, "\n");
09137c09
SP		 2758 if (x->types[j].bitfield.reg8
2759 || x->types[j].bitfield.reg16
2760 || x->types[j].bitfield.reg32
2761 || x->types[j].bitfield.reg64
2762 || x->types[j].bitfield.regmmx
2763 || x->types[j].bitfield.regxmm
2764 || x->types[j].bitfield.regymm
43234a1e 2765 || x->types[j].bitfield.regzmm
09137c09
SP		 2766 || x->types[j].bitfield.sreg2
2767 || x->types[j].bitfield.sreg3
2768 || x->types[j].bitfield.control
2769 || x->types[j].bitfield.debug
2770 || x->types[j].bitfield.test)
2771 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2772 if (operand_type_check (x->types[j], imm))
2773 pe (x->op[j].imms);
2774 if (operand_type_check (x->types[j], disp))
2775 pe (x->op[j].disps);
252b5132
RH		 2776 }
2777}
2778
2779static void
d3ce72d0 2780pte (insn_template *t)
252b5132 2781{
09137c09 2782 unsigned int j;
252b5132 2783 fprintf (stdout, " %d operands ", t->operands);
47926f60 2784 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2785 if (t->extension_opcode != None)
2786 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2787 if (t->opcode_modifier.d)
252b5132 2788 fprintf (stdout, "D");
40fb9820 2789 if (t->opcode_modifier.w)
252b5132
RH		 2790 fprintf (stdout, "W");
2791 fprintf (stdout, "\n");
09137c09 2792 for (j = 0; j < t->operands; j++)
252b5132 2793 {
09137c09
SP		 2794 fprintf (stdout, " #%d type ", j + 1);
2795 pt (t->operand_types[j]);
252b5132
RH		 2796 fprintf (stdout, "\n");
2797 }
2798}
2799
2800static void
e3bb37b5 2801pe (expressionS *e)
252b5132 2802{
24eab124 2803 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2804 fprintf (stdout, " add_number %ld (%lx)\n",
2805 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2806 if (e->X_add_symbol)
2807 {
2808 fprintf (stdout, " add_symbol ");
2809 ps (e->X_add_symbol);
2810 fprintf (stdout, "\n");
2811 }
2812 if (e->X_op_symbol)
2813 {
2814 fprintf (stdout, " op_symbol ");
2815 ps (e->X_op_symbol);
2816 fprintf (stdout, "\n");
2817 }
2818}
2819
2820static void
e3bb37b5 2821ps (symbolS *s)
252b5132
RH		 2822{
2823 fprintf (stdout, "%s type %s%s",
2824 S_GET_NAME (s),
2825 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2826 segment_name (S_GET_SEGMENT (s)));
2827}
2828
7b81dfbb 2829static struct type_name
252b5132 2830 {
40fb9820
L		 2831 i386_operand_type mask;
2832 const char *name;
252b5132 2833 }
7b81dfbb 2834const type_names[] =
252b5132 2835{
40fb9820
L		 2836 { OPERAND_TYPE_REG8, "r8" },
2837 { OPERAND_TYPE_REG16, "r16" },
2838 { OPERAND_TYPE_REG32, "r32" },
2839 { OPERAND_TYPE_REG64, "r64" },
2840 { OPERAND_TYPE_IMM8, "i8" },
2841 { OPERAND_TYPE_IMM8, "i8s" },
2842 { OPERAND_TYPE_IMM16, "i16" },
2843 { OPERAND_TYPE_IMM32, "i32" },
2844 { OPERAND_TYPE_IMM32S, "i32s" },
2845 { OPERAND_TYPE_IMM64, "i64" },
2846 { OPERAND_TYPE_IMM1, "i1" },
2847 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2848 { OPERAND_TYPE_DISP8, "d8" },
2849 { OPERAND_TYPE_DISP16, "d16" },
2850 { OPERAND_TYPE_DISP32, "d32" },
2851 { OPERAND_TYPE_DISP32S, "d32s" },
2852 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2853 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2854 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2855 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2856 { OPERAND_TYPE_CONTROL, "control reg" },
2857 { OPERAND_TYPE_TEST, "test reg" },
2858 { OPERAND_TYPE_DEBUG, "debug reg" },
2859 { OPERAND_TYPE_FLOATREG, "FReg" },
2860 { OPERAND_TYPE_FLOATACC, "FAcc" },
2861 { OPERAND_TYPE_SREG2, "SReg2" },
2862 { OPERAND_TYPE_SREG3, "SReg3" },
2863 { OPERAND_TYPE_ACC, "Acc" },
2864 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2865 { OPERAND_TYPE_REGMMX, "rMMX" },
2866 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2867 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2868 { OPERAND_TYPE_REGZMM, "rZMM" },
2869 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2870 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2871};
2872
2873static void
40fb9820 2874pt (i386_operand_type t)
252b5132 2875{
40fb9820 2876 unsigned int j;
c6fb90c8 2877 i386_operand_type a;
252b5132 2878
40fb9820 2879 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2880 {
2881 a = operand_type_and (t, type_names[j].mask);
0349dc08 2882 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2883 fprintf (stdout, "%s, ", type_names[j].name);
2884 }
252b5132
RH		 2885 fflush (stdout);
2886}
2887
2888#endif /* DEBUG386 */
2889\f
252b5132 2890static bfd_reloc_code_real_type
3956db08 2891reloc (unsigned int size,
64e74474
AM		 2892 int pcrel,
2893 int sign,
2894 bfd_reloc_code_real_type other)
252b5132 2895{
47926f60 2896 if (other != NO_RELOC)
3956db08 2897 {
91d6fa6a 2898 reloc_howto_type *rel;
3956db08
JB		 2899
2900 if (size == 8)
2901 switch (other)
2902 {
64e74474
AM		 2903 case BFD_RELOC_X86_64_GOT32:
2904 return BFD_RELOC_X86_64_GOT64;
2905 break;
553d1284
L		 2906 case BFD_RELOC_X86_64_GOTPLT64:
2907 return BFD_RELOC_X86_64_GOTPLT64;
2908 break;
64e74474
AM		 2909 case BFD_RELOC_X86_64_PLTOFF64:
2910 return BFD_RELOC_X86_64_PLTOFF64;
2911 break;
2912 case BFD_RELOC_X86_64_GOTPC32:
2913 other = BFD_RELOC_X86_64_GOTPC64;
2914 break;
2915 case BFD_RELOC_X86_64_GOTPCREL:
2916 other = BFD_RELOC_X86_64_GOTPCREL64;
2917 break;
2918 case BFD_RELOC_X86_64_TPOFF32:
2919 other = BFD_RELOC_X86_64_TPOFF64;
2920 break;
2921 case BFD_RELOC_X86_64_DTPOFF32:
2922 other = BFD_RELOC_X86_64_DTPOFF64;
2923 break;
2924 default:
2925 break;
3956db08 2926 }
e05278af 2927
8ce3d284 2928#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2929 if (other == BFD_RELOC_SIZE32)
2930 {
2931 if (size == 8)
1ab668bf 2932 other = BFD_RELOC_SIZE64;
8fd4256d 2933 if (pcrel)
1ab668bf
AM		 2934 {
2935 as_bad (_("there are no pc-relative size relocations"));
2936 return NO_RELOC;
2937 }
8fd4256d 2938 }
8ce3d284 2939#endif
8fd4256d 2940
e05278af 2941 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2942 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2943 sign = -1;
2944
91d6fa6a
NC		 2945 rel = bfd_reloc_type_lookup (stdoutput, other);
2946 if (!rel)
3956db08 2947 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2948 else if (size != bfd_get_reloc_size (rel))
3956db08 2949 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2950 bfd_get_reloc_size (rel),
3956db08 2951 size);
91d6fa6a 2952 else if (pcrel && !rel->pc_relative)
3956db08 2953 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2954 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2955 && !sign)
91d6fa6a 2956 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2957 && sign > 0))
3956db08
JB		 2958 as_bad (_("relocated field and relocation type differ in signedness"));
2959 else
2960 return other;
2961 return NO_RELOC;
2962 }
252b5132
RH		 2963
2964 if (pcrel)
2965 {
3e73aa7c 2966 if (!sign)
3956db08 2967 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2968 switch (size)
2969 {
2970 case 1: return BFD_RELOC_8_PCREL;
2971 case 2: return BFD_RELOC_16_PCREL;
d258b828 2972 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2973 case 8: return BFD_RELOC_64_PCREL;
252b5132 2974 }
3956db08 2975 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2976 }
2977 else
2978 {
3956db08 2979 if (sign > 0)
e5cb08ac 2980 switch (size)
3e73aa7c
JH		 2981 {
2982 case 4: return BFD_RELOC_X86_64_32S;
2983 }
2984 else
2985 switch (size)
2986 {
2987 case 1: return BFD_RELOC_8;
2988 case 2: return BFD_RELOC_16;
2989 case 4: return BFD_RELOC_32;
2990 case 8: return BFD_RELOC_64;
2991 }
3956db08
JB		 2992 as_bad (_("cannot do %s %u byte relocation"),
2993 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2994 }
2995
0cc9e1d3 2996 return NO_RELOC;
252b5132
RH		 2997}
2998
47926f60
KH		 2999/* Here we decide which fixups can be adjusted to make them relative to
3000 the beginning of the section instead of the symbol. Basically we need
3001 to make sure that the dynamic relocations are done correctly, so in
3002 some cases we force the original symbol to be used. */
3003
252b5132 3004int
e3bb37b5 3005tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 3006{
6d249963 3007#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 3008 if (!IS_ELF)
31312f95
AM		 3009 return 1;
3010
a161fe53
AM		 3011 /* Don't adjust pc-relative references to merge sections in 64-bit
3012 mode. */
3013 if (use_rela_relocations
3014 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3015 && fixP->fx_pcrel)
252b5132 3016 return 0;
31312f95 3017
8d01d9a9
AJ		 3018 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3019 and changed later by validate_fix. */
3020 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3021 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3022 return 0;
3023
8fd4256d
L		 3024 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3025 for size relocations. */
3026 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3027 || fixP->fx_r_type == BFD_RELOC_SIZE64
3028 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 3029 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3030 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 3031 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3032 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3033 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3034 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3035 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3036 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3037 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3038 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3039 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3040 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3041 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3042 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3043 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3044 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3045 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3046 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3047 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3048 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3049 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3050 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3051 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3052 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3053 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3054 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3055 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3056 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3057 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3058 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3059 return 0;
31312f95 3060#endif
252b5132
RH		 3061 return 1;
3062}
252b5132 3063
b4cac588 3064static int
e3bb37b5 3065intel_float_operand (const char *mnemonic)
252b5132 3066{
9306ca4a
JB		 3067 /* Note that the value returned is meaningful only for opcodes with (memory)
3068 operands, hence the code here is free to improperly handle opcodes that
3069 have no operands (for better performance and smaller code). */
3070
3071 if (mnemonic[0] != 'f')
3072 return 0; /* non-math */
3073
3074 switch (mnemonic[1])
3075 {
3076 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3077 the fs segment override prefix not currently handled because no
3078 call path can make opcodes without operands get here */
3079 case 'i':
3080 return 2 /* integer op */;
3081 case 'l':
3082 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3083 return 3; /* fldcw/fldenv */
3084 break;
3085 case 'n':
3086 if (mnemonic[2] != 'o' /* fnop */)
3087 return 3; /* non-waiting control op */
3088 break;
3089 case 'r':
3090 if (mnemonic[2] == 's')
3091 return 3; /* frstor/frstpm */
3092 break;
3093 case 's':
3094 if (mnemonic[2] == 'a')
3095 return 3; /* fsave */
3096 if (mnemonic[2] == 't')
3097 {
3098 switch (mnemonic[3])
3099 {
3100 case 'c': /* fstcw */
3101 case 'd': /* fstdw */
3102 case 'e': /* fstenv */
3103 case 's': /* fsts[gw] */
3104 return 3;
3105 }
3106 }
3107 break;
3108 case 'x':
3109 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3110 return 0; /* fxsave/fxrstor are not really math ops */
3111 break;
3112 }
252b5132 3113
9306ca4a 3114 return 1;
252b5132
RH		 3115}
3116
c0f3af97
L		 3117/* Build the VEX prefix. */
3118
3119static void
d3ce72d0 3120build_vex_prefix (const insn_template *t)
c0f3af97
L		 3121{
3122 unsigned int register_specifier;
3123 unsigned int implied_prefix;
3124 unsigned int vector_length;
3125
3126 /* Check register specifier. */
3127 if (i.vex.register_specifier)
43234a1e
L		 3128 {
3129 register_specifier =
3130 ~register_number (i.vex.register_specifier) & 0xf;
3131 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3132 }
c0f3af97
L		 3133 else
3134 register_specifier = 0xf;
3135
fa99fab2
L		 3136 /* Use 2-byte VEX prefix by swappping destination and source
3137 operand. */
3138 if (!i.swap_operand
3139 && i.operands == i.reg_operands
7f399153 3140 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3141 && i.tm.opcode_modifier.s
3142 && i.rex == REX_B)
3143 {
3144 unsigned int xchg = i.operands - 1;
3145 union i386_op temp_op;
3146 i386_operand_type temp_type;
3147
3148 temp_type = i.types[xchg];
3149 i.types[xchg] = i.types[0];
3150 i.types[0] = temp_type;
3151 temp_op = i.op[xchg];
3152 i.op[xchg] = i.op[0];
3153 i.op[0] = temp_op;
3154
9c2799c2 3155 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3156
3157 i.rex = REX_R;
3158 xchg = i.rm.regmem;
3159 i.rm.regmem = i.rm.reg;
3160 i.rm.reg = xchg;
3161
3162 /* Use the next insn. */
3163 i.tm = t[1];
3164 }
3165
539f890d
L		 3166 if (i.tm.opcode_modifier.vex == VEXScalar)
3167 vector_length = avxscalar;
3168 else
3169 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3170
3171 switch ((i.tm.base_opcode >> 8) & 0xff)
3172 {
3173 case 0:
3174 implied_prefix = 0;
3175 break;
3176 case DATA_PREFIX_OPCODE:
3177 implied_prefix = 1;
3178 break;
3179 case REPE_PREFIX_OPCODE:
3180 implied_prefix = 2;
3181 break;
3182 case REPNE_PREFIX_OPCODE:
3183 implied_prefix = 3;
3184 break;
3185 default:
3186 abort ();
3187 }
3188
3189 /* Use 2-byte VEX prefix if possible. */
7f399153 3190 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3191 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3192 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3193 {
3194 /* 2-byte VEX prefix. */
3195 unsigned int r;
3196
3197 i.vex.length = 2;
3198 i.vex.bytes[0] = 0xc5;
3199
3200 /* Check the REX.R bit. */
3201 r = (i.rex & REX_R) ? 0 : 1;
3202 i.vex.bytes[1] = (r << 7
3203 | register_specifier << 3
3204 | vector_length << 2
3205 | implied_prefix);
3206 }
3207 else
3208 {
3209 /* 3-byte VEX prefix. */
3210 unsigned int m, w;
3211
f88c9eb0 3212 i.vex.length = 3;
f88c9eb0 3213
7f399153 3214 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3215 {
7f399153
L		 3216 case VEX0F:
3217 m = 0x1;
80de6e00 3218 i.vex.bytes[0] = 0xc4;
7f399153
L		 3219 break;
3220 case VEX0F38:
3221 m = 0x2;
80de6e00 3222 i.vex.bytes[0] = 0xc4;
7f399153
L		 3223 break;
3224 case VEX0F3A:
3225 m = 0x3;
80de6e00 3226 i.vex.bytes[0] = 0xc4;
7f399153
L		 3227 break;
3228 case XOP08:
5dd85c99
SP		 3229 m = 0x8;
3230 i.vex.bytes[0] = 0x8f;
7f399153
L		 3231 break;
3232 case XOP09:
f88c9eb0
SP		 3233 m = 0x9;
3234 i.vex.bytes[0] = 0x8f;
7f399153
L		 3235 break;
3236 case XOP0A:
f88c9eb0
SP		 3237 m = 0xa;
3238 i.vex.bytes[0] = 0x8f;
7f399153
L		 3239 break;
3240 default:
3241 abort ();
f88c9eb0 3242 }
c0f3af97 3243
c0f3af97
L		 3244 /* The high 3 bits of the second VEX byte are 1's compliment
3245 of RXB bits from REX. */
3246 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3247
3248 /* Check the REX.W bit. */
3249 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3250 if (i.tm.opcode_modifier.vexw == VEXW1)
3251 w = 1;
c0f3af97
L		 3252
3253 i.vex.bytes[2] = (w << 7
3254 | register_specifier << 3
3255 | vector_length << 2
3256 | implied_prefix);
3257 }
3258}
3259
43234a1e
L		 3260/* Build the EVEX prefix. */
3261
3262static void
3263build_evex_prefix (void)
3264{
3265 unsigned int register_specifier;
3266 unsigned int implied_prefix;
3267 unsigned int m, w;
3268 rex_byte vrex_used = 0;
3269
3270 /* Check register specifier. */
3271 if (i.vex.register_specifier)
3272 {
3273 gas_assert ((i.vrex & REX_X) == 0);
3274
3275 register_specifier = i.vex.register_specifier->reg_num;
3276 if ((i.vex.register_specifier->reg_flags & RegRex))
3277 register_specifier += 8;
3278 /* The upper 16 registers are encoded in the fourth byte of the
3279 EVEX prefix. */
3280 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3281 i.vex.bytes[3] = 0x8;
3282 register_specifier = ~register_specifier & 0xf;
3283 }
3284 else
3285 {
3286 register_specifier = 0xf;
3287
3288 /* Encode upper 16 vector index register in the fourth byte of
3289 the EVEX prefix. */
3290 if (!(i.vrex & REX_X))
3291 i.vex.bytes[3] = 0x8;
3292 else
3293 vrex_used |= REX_X;
3294 }
3295
3296 switch ((i.tm.base_opcode >> 8) & 0xff)
3297 {
3298 case 0:
3299 implied_prefix = 0;
3300 break;
3301 case DATA_PREFIX_OPCODE:
3302 implied_prefix = 1;
3303 break;
3304 case REPE_PREFIX_OPCODE:
3305 implied_prefix = 2;
3306 break;
3307 case REPNE_PREFIX_OPCODE:
3308 implied_prefix = 3;
3309 break;
3310 default:
3311 abort ();
3312 }
3313
3314 /* 4 byte EVEX prefix. */
3315 i.vex.length = 4;
3316 i.vex.bytes[0] = 0x62;
3317
3318 /* mmmm bits. */
3319 switch (i.tm.opcode_modifier.vexopcode)
3320 {
3321 case VEX0F:
3322 m = 1;
3323 break;
3324 case VEX0F38:
3325 m = 2;
3326 break;
3327 case VEX0F3A:
3328 m = 3;
3329 break;
3330 default:
3331 abort ();
3332 break;
3333 }
3334
3335 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3336 bits from REX. */
3337 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3338
3339 /* The fifth bit of the second EVEX byte is 1's compliment of the
3340 REX_R bit in VREX. */
3341 if (!(i.vrex & REX_R))
3342 i.vex.bytes[1] |= 0x10;
3343 else
3344 vrex_used |= REX_R;
3345
3346 if ((i.reg_operands + i.imm_operands) == i.operands)
3347 {
3348 /* When all operands are registers, the REX_X bit in REX is not
3349 used. We reuse it to encode the upper 16 registers, which is
3350 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3351 as 1's compliment. */
3352 if ((i.vrex & REX_B))
3353 {
3354 vrex_used |= REX_B;
3355 i.vex.bytes[1] &= ~0x40;
3356 }
3357 }
3358
3359 /* EVEX instructions shouldn't need the REX prefix. */
3360 i.vrex &= ~vrex_used;
3361 gas_assert (i.vrex == 0);
3362
3363 /* Check the REX.W bit. */
3364 w = (i.rex & REX_W) ? 1 : 0;
3365 if (i.tm.opcode_modifier.vexw)
3366 {
3367 if (i.tm.opcode_modifier.vexw == VEXW1)
3368 w = 1;
3369 }
3370 /* If w is not set it means we are dealing with WIG instruction. */
3371 else if (!w)
3372 {
3373 if (evexwig == evexw1)
3374 w = 1;
3375 }
3376
3377 /* Encode the U bit. */
3378 implied_prefix |= 0x4;
3379
3380 /* The third byte of the EVEX prefix. */
3381 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3382
3383 /* The fourth byte of the EVEX prefix. */
3384 /* The zeroing-masking bit. */
3385 if (i.mask && i.mask->zeroing)
3386 i.vex.bytes[3] |= 0x80;
3387
3388 /* Don't always set the broadcast bit if there is no RC. */
3389 if (!i.rounding)
3390 {
3391 /* Encode the vector length. */
3392 unsigned int vec_length;
3393
3394 switch (i.tm.opcode_modifier.evex)
3395 {
3396 case EVEXLIG: /* LL' is ignored */
3397 vec_length = evexlig << 5;
3398 break;
3399 case EVEX128:
3400 vec_length = 0 << 5;
3401 break;
3402 case EVEX256:
3403 vec_length = 1 << 5;
3404 break;
3405 case EVEX512:
3406 vec_length = 2 << 5;
3407 break;
3408 default:
3409 abort ();
3410 break;
3411 }
3412 i.vex.bytes[3] |= vec_length;
3413 /* Encode the broadcast bit. */
3414 if (i.broadcast)
3415 i.vex.bytes[3] |= 0x10;
3416 }
3417 else
3418 {
3419 if (i.rounding->type != saeonly)
3420 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3421 else
d3d3c6db 3422 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3423 }
3424
3425 if (i.mask && i.mask->mask)
3426 i.vex.bytes[3] |= i.mask->mask->reg_num;
3427}
3428
65da13b5
L		 3429static void
3430process_immext (void)
3431{
3432 expressionS *exp;
3433
4c692bc7
JB		 3434 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3435 && i.operands > 0)
65da13b5 3436 {
4c692bc7
JB		 3437 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3438 with an opcode suffix which is coded in the same place as an
3439 8-bit immediate field would be.
3440 Here we check those operands and remove them afterwards. */
65da13b5
L		 3441 unsigned int x;
3442
3443 for (x = 0; x < i.operands; x++)
4c692bc7 3444 if (register_number (i.op[x].regs) != x)
65da13b5 3445 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3446 register_prefix, i.op[x].regs->reg_name, x + 1,
3447 i.tm.name);
3448
3449 i.operands = 0;
65da13b5
L		 3450 }
3451
9916071f
AP		 3452 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3453 {
3454 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3455 suffix which is coded in the same place as an 8-bit immediate
3456 field would be.
3457 Here we check those operands and remove them afterwards. */
3458 unsigned int x;
3459
3460 if (i.operands != 3)
3461 abort();
3462
3463 for (x = 0; x < 2; x++)
3464 if (register_number (i.op[x].regs) != x)
3465 goto bad_register_operand;
3466
3467 /* Check for third operand for mwaitx/monitorx insn. */
3468 if (register_number (i.op[x].regs)
3469 != (x + (i.tm.extension_opcode == 0xfb)))
3470 {
3471bad_register_operand:
3472 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3473 register_prefix, i.op[x].regs->reg_name, x+1,
3474 i.tm.name);
3475 }
3476
3477 i.operands = 0;
3478 }
3479
c0f3af97 3480 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3481 which is coded in the same place as an 8-bit immediate field
3482 would be. Here we fake an 8-bit immediate operand from the
3483 opcode suffix stored in tm.extension_opcode.
3484
c1e679ec 3485 AVX instructions also use this encoding, for some of
c0f3af97 3486 3 argument instructions. */
65da13b5 3487
43234a1e 3488 gas_assert (i.imm_operands <= 1
7ab9ffdd 3489 && (i.operands <= 2
43234a1e
L		 3490 || ((i.tm.opcode_modifier.vex
3491 || i.tm.opcode_modifier.evex)
7ab9ffdd 3492 && i.operands <= 4)));
65da13b5
L		 3493
3494 exp = &im_expressions[i.imm_operands++];
3495 i.op[i.operands].imms = exp;
3496 i.types[i.operands] = imm8;
3497 i.operands++;
3498 exp->X_op = O_constant;
3499 exp->X_add_number = i.tm.extension_opcode;
3500 i.tm.extension_opcode = None;
3501}
3502
42164a71
L		 3503
3504static int
3505check_hle (void)
3506{
3507 switch (i.tm.opcode_modifier.hleprefixok)
3508 {
3509 default:
3510 abort ();
82c2def5 3511 case HLEPrefixNone:
165de32a
L		 3512 as_bad (_("invalid instruction `%s' after `%s'"),
3513 i.tm.name, i.hle_prefix);
42164a71 3514 return 0;
82c2def5 3515 case HLEPrefixLock:
42164a71
L		 3516 if (i.prefix[LOCK_PREFIX])
3517 return 1;
165de32a 3518 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3519 return 0;
82c2def5 3520 case HLEPrefixAny:
42164a71 3521 return 1;
82c2def5 3522 case HLEPrefixRelease:
42164a71
L		 3523 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3524 {
3525 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3526 i.tm.name);
3527 return 0;
3528 }
3529 if (i.mem_operands == 0
3530 || !operand_type_check (i.types[i.operands - 1], anymem))
3531 {
3532 as_bad (_("memory destination needed for instruction `%s'"
3533 " after `xrelease'"), i.tm.name);
3534 return 0;
3535 }
3536 return 1;
3537 }
3538}
3539
252b5132
RH		 3540/* This is the guts of the machine-dependent assembler. LINE points to a
3541 machine dependent instruction. This function is supposed to emit
3542 the frags/bytes it assembles to. */
3543
3544void
65da13b5 3545md_assemble (char *line)
252b5132 3546{
40fb9820 3547 unsigned int j;
83b16ac6 3548 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
d3ce72d0 3549 const insn_template *t;
252b5132 3550
47926f60 3551 /* Initialize globals. */
252b5132
RH		 3552 memset (&i, '\0', sizeof (i));
3553 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3554 i.reloc[j] = NO_RELOC;
252b5132
RH		 3555 memset (disp_expressions, '\0', sizeof (disp_expressions));
3556 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3557 save_stack_p = save_stack;
252b5132
RH		 3558
3559 /* First parse an instruction mnemonic & call i386_operand for the operands.
3560 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3561 start of a (possibly prefixed) mnemonic. */
252b5132 3562
29b0f896
AM		 3563 line = parse_insn (line, mnemonic);
3564 if (line == NULL)
3565 return;
83b16ac6 3566 mnem_suffix = i.suffix;
252b5132 3567
29b0f896 3568 line = parse_operands (line, mnemonic);
ee86248c 3569 this_operand = -1;
8325cc63
JB		 3570 xfree (i.memop1_string);
3571 i.memop1_string = NULL;
29b0f896
AM		 3572 if (line == NULL)
3573 return;
252b5132 3574
29b0f896
AM		 3575 /* Now we've parsed the mnemonic into a set of templates, and have the
3576 operands at hand. */
3577
3578 /* All intel opcodes have reversed operands except for "bound" and
3579 "enter". We also don't reverse intersegment "jmp" and "call"
3580 instructions with 2 immediate operands so that the immediate segment
050dfa73 3581 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3582 if (intel_syntax
3583 && i.operands > 1
29b0f896 3584 && (strcmp (mnemonic, "bound") != 0)
30123838 3585 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3586 && !(operand_type_check (i.types[0], imm)
3587 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3588 swap_operands ();
3589
ec56d5c0
JB		 3590 /* The order of the immediates should be reversed
3591 for 2 immediates extrq and insertq instructions */
3592 if (i.imm_operands == 2
3593 && (strcmp (mnemonic, "extrq") == 0
3594 || strcmp (mnemonic, "insertq") == 0))
3595 swap_2_operands (0, 1);
3596
29b0f896
AM		 3597 if (i.imm_operands)
3598 optimize_imm ();
3599
b300c311
L		 3600 /* Don't optimize displacement for movabs since it only takes 64bit
3601 displacement. */
3602 if (i.disp_operands
a501d77e 3603 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3604 && (flag_code != CODE_64BIT
3605 || strcmp (mnemonic, "movabs") != 0))
3606 optimize_disp ();
29b0f896
AM		 3607
3608 /* Next, we find a template that matches the given insn,
3609 making sure the overlap of the given operands types is consistent
3610 with the template operand types. */
252b5132 3611
83b16ac6 3612 if (!(t = match_template (mnem_suffix)))
29b0f896 3613 return;
252b5132 3614
7bab8ab5 3615 if (sse_check != check_none
81f8a913 3616 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3617 && (i.tm.cpu_flags.bitfield.cpusse
3618 || i.tm.cpu_flags.bitfield.cpusse2
3619 || i.tm.cpu_flags.bitfield.cpusse3
3620 || i.tm.cpu_flags.bitfield.cpussse3
3621 || i.tm.cpu_flags.bitfield.cpusse4_1
3622 || i.tm.cpu_flags.bitfield.cpusse4_2))
3623 {
7bab8ab5 3624 (sse_check == check_warning
daf50ae7
L		 3625 ? as_warn
3626 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3627 }
3628
321fd21e
L		 3629 /* Zap movzx and movsx suffix. The suffix has been set from
3630 "word ptr" or "byte ptr" on the source operand in Intel syntax
3631 or extracted from mnemonic in AT&T syntax. But we'll use
3632 the destination register to choose the suffix for encoding. */
3633 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3634 {
321fd21e
L		 3635 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3636 there is no suffix, the default will be byte extension. */
3637 if (i.reg_operands != 2
3638 && !i.suffix
7ab9ffdd 3639 && intel_syntax)
321fd21e
L		 3640 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3641
3642 i.suffix = 0;
cd61ebfe 3643 }
24eab124 3644
40fb9820 3645 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3646 if (!add_prefix (FWAIT_OPCODE))
3647 return;
252b5132 3648
d5de92cf
L		 3649 /* Check if REP prefix is OK. */
3650 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3651 {
3652 as_bad (_("invalid instruction `%s' after `%s'"),
3653 i.tm.name, i.rep_prefix);
3654 return;
3655 }
3656
c1ba0266
L		 3657 /* Check for lock without a lockable instruction. Destination operand
3658 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3659 if (i.prefix[LOCK_PREFIX]
3660 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3661 || i.mem_operands == 0
3662 || (i.tm.base_opcode != 0x86
3663 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3664 {
3665 as_bad (_("expecting lockable instruction after `lock'"));
3666 return;
3667 }
3668
42164a71 3669 /* Check if HLE prefix is OK. */
165de32a 3670 if (i.hle_prefix && !check_hle ())
42164a71
L		 3671 return;
3672
7e8b059b
L		 3673 /* Check BND prefix. */
3674 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3675 as_bad (_("expecting valid branch instruction after `bnd'"));
3676
327e8c42
JB		 3677 if (i.tm.cpu_flags.bitfield.cpumpx)
3678 {
3679 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
3680 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3681 else if (flag_code != CODE_16BIT
3682 ? i.prefix[ADDR_PREFIX]
3683 : i.mem_operands && !i.prefix[ADDR_PREFIX])
3684 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3685 }
7e8b059b
L		 3686
3687 /* Insert BND prefix. */
3688 if (add_bnd_prefix
3689 && i.tm.opcode_modifier.bndprefixok
3690 && !i.prefix[BND_PREFIX])
3691 add_prefix (BND_PREFIX_OPCODE);
3692
29b0f896 3693 /* Check string instruction segment overrides. */
40fb9820 3694 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3695 {
3696 if (!check_string ())
5dd0794d 3697 return;
fc0763e6 3698 i.disp_operands = 0;
29b0f896 3699 }
5dd0794d 3700
29b0f896
AM		 3701 if (!process_suffix ())
3702 return;
e413e4e9 3703
bc0844ae
L		 3704 /* Update operand types. */
3705 for (j = 0; j < i.operands; j++)
3706 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3707
29b0f896
AM		 3708 /* Make still unresolved immediate matches conform to size of immediate
3709 given in i.suffix. */
3710 if (!finalize_imm ())
3711 return;
252b5132 3712
40fb9820 3713 if (i.types[0].bitfield.imm1)
29b0f896 3714 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3715
9afe6eb8
L		 3716 /* We only need to check those implicit registers for instructions
3717 with 3 operands or less. */
3718 if (i.operands <= 3)
3719 for (j = 0; j < i.operands; j++)
3720 if (i.types[j].bitfield.inoutportreg
3721 || i.types[j].bitfield.shiftcount
3722 || i.types[j].bitfield.acc
3723 || i.types[j].bitfield.floatacc)
3724 i.reg_operands--;
40fb9820 3725
c0f3af97
L		 3726 /* ImmExt should be processed after SSE2AVX. */
3727 if (!i.tm.opcode_modifier.sse2avx
3728 && i.tm.opcode_modifier.immext)
65da13b5 3729 process_immext ();
252b5132 3730
29b0f896
AM		 3731 /* For insns with operands there are more diddles to do to the opcode. */
3732 if (i.operands)
3733 {
3734 if (!process_operands ())
3735 return;
3736 }
40fb9820 3737 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3738 {
3739 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3740 as_warn (_("translating to `%sp'"), i.tm.name);
3741 }
252b5132 3742
9e5e5283
L		 3743 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3744 {
3745 if (flag_code == CODE_16BIT)
3746 {
3747 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3748 i.tm.name);
3749 return;
3750 }
c0f3af97 3751
9e5e5283
L		 3752 if (i.tm.opcode_modifier.vex)
3753 build_vex_prefix (t);
3754 else
3755 build_evex_prefix ();
3756 }
43234a1e 3757
5dd85c99
SP		 3758 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3759 instructions may define INT_OPCODE as well, so avoid this corner
3760 case for those instructions that use MODRM. */
3761 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3762 && !i.tm.opcode_modifier.modrm
3763 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3764 {
3765 i.tm.base_opcode = INT3_OPCODE;
3766 i.imm_operands = 0;
3767 }
252b5132 3768
40fb9820
L		 3769 if ((i.tm.opcode_modifier.jump
3770 || i.tm.opcode_modifier.jumpbyte
3771 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3772 && i.op[0].disps->X_op == O_constant)
3773 {
3774 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3775 the absolute address given by the constant. Since ix86 jumps and
3776 calls are pc relative, we need to generate a reloc. */
3777 i.op[0].disps->X_add_symbol = &abs_symbol;
3778 i.op[0].disps->X_op = O_symbol;
3779 }
252b5132 3780
40fb9820 3781 if (i.tm.opcode_modifier.rex64)
161a04f6 3782 i.rex |= REX_W;
252b5132 3783
29b0f896
AM		 3784 /* For 8 bit registers we need an empty rex prefix. Also if the
3785 instruction already has a prefix, we need to convert old
3786 registers to new ones. */
773f551c 3787
40fb9820 3788 if ((i.types[0].bitfield.reg8
29b0f896 3789 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3790 || (i.types[1].bitfield.reg8
29b0f896 3791 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3792 || ((i.types[0].bitfield.reg8
3793 || i.types[1].bitfield.reg8)
29b0f896
AM		 3794 && i.rex != 0))
3795 {
3796 int x;
726c5dcd 3797
29b0f896
AM		 3798 i.rex |= REX_OPCODE;
3799 for (x = 0; x < 2; x++)
3800 {
3801 /* Look for 8 bit operand that uses old registers. */
40fb9820 3802 if (i.types[x].bitfield.reg8
29b0f896 3803 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3804 {
29b0f896
AM		 3805 /* In case it is "hi" register, give up. */
3806 if (i.op[x].regs->reg_num > 3)
a540244d 3807 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3808 "instruction requiring REX prefix."),
a540244d 3809 register_prefix, i.op[x].regs->reg_name);
773f551c 3810
29b0f896
AM		 3811 /* Otherwise it is equivalent to the extended register.
3812 Since the encoding doesn't change this is merely
3813 cosmetic cleanup for debug output. */
3814
3815 i.op[x].regs = i.op[x].regs + 8;
773f551c 3816 }
29b0f896
AM		 3817 }
3818 }
773f551c 3819
7ab9ffdd 3820 if (i.rex != 0)
29b0f896
AM		 3821 add_prefix (REX_OPCODE | i.rex);
3822
3823 /* We are ready to output the insn. */
3824 output_insn ();
3825}
3826
3827static char *
e3bb37b5 3828parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3829{
3830 char *l = line;
3831 char *token_start = l;
3832 char *mnem_p;
5c6af06e 3833 int supported;
d3ce72d0 3834 const insn_template *t;
b6169b20 3835 char *dot_p = NULL;
29b0f896 3836
29b0f896
AM		 3837 while (1)
3838 {
3839 mnem_p = mnemonic;
3840 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3841 {
b6169b20
L		 3842 if (*mnem_p == '.')
3843 dot_p = mnem_p;
29b0f896
AM		 3844 mnem_p++;
3845 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3846 {
29b0f896
AM		 3847 as_bad (_("no such instruction: `%s'"), token_start);
3848 return NULL;
3849 }
3850 l++;
3851 }
3852 if (!is_space_char (*l)
3853 && *l != END_OF_INSN
e44823cf
JB		 3854 && (intel_syntax
3855 || (*l != PREFIX_SEPARATOR
3856 && *l != ',')))
29b0f896
AM		 3857 {
3858 as_bad (_("invalid character %s in mnemonic"),
3859 output_invalid (*l));
3860 return NULL;
3861 }
3862 if (token_start == l)
3863 {
e44823cf 3864 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3865 as_bad (_("expecting prefix; got nothing"));
3866 else
3867 as_bad (_("expecting mnemonic; got nothing"));
3868 return NULL;
3869 }
45288df1 3870
29b0f896 3871 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3872 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3873
29b0f896
AM		 3874 if (*l != END_OF_INSN
3875 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3876 && current_templates
40fb9820 3877 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3878 {
c6fb90c8 3879 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3880 {
3881 as_bad ((flag_code != CODE_64BIT
3882 ? _("`%s' is only supported in 64-bit mode")
3883 : _("`%s' is not supported in 64-bit mode")),
3884 current_templates->start->name);
3885 return NULL;
3886 }
29b0f896
AM		 3887 /* If we are in 16-bit mode, do not allow addr16 or data16.
3888 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3889 if ((current_templates->start->opcode_modifier.size16
3890 || current_templates->start->opcode_modifier.size32)
29b0f896 3891 && flag_code != CODE_64BIT
40fb9820 3892 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3893 ^ (flag_code == CODE_16BIT)))
3894 {
3895 as_bad (_("redundant %s prefix"),
3896 current_templates->start->name);
3897 return NULL;
45288df1 3898 }
29b0f896
AM		 3899 /* Add prefix, checking for repeated prefixes. */
3900 switch (add_prefix (current_templates->start->base_opcode))
3901 {
c32fa91d 3902 case PREFIX_EXIST:
29b0f896 3903 return NULL;
c32fa91d 3904 case PREFIX_REP:
42164a71 3905 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3906 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3907 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3908 i.bnd_prefix = current_templates->start->name;
42164a71 3909 else
d5de92cf 3910 i.rep_prefix = current_templates->start->name;
29b0f896 3911 break;
c32fa91d
L		 3912 default:
3913 break;
29b0f896
AM		 3914 }
3915 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3916 token_start = ++l;
3917 }
3918 else
3919 break;
3920 }
45288df1 3921
30a55f88 3922 if (!current_templates)
b6169b20 3923 {
f8a5c266
L		 3924 /* Check if we should swap operand or force 32bit displacement in
3925 encoding. */
30a55f88
L		 3926 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3927 i.swap_operand = 1;
8d63c93e 3928 else if (mnem_p - 3 == dot_p
a501d77e
L		 3929 && dot_p[1] == 'd'
3930 && dot_p[2] == '8')
3931 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3932 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3933 && dot_p[1] == 'd'
3934 && dot_p[2] == '3'
3935 && dot_p[3] == '2')
a501d77e 3936 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3937 else
3938 goto check_suffix;
3939 mnem_p = dot_p;
3940 *dot_p = '\0';
d3ce72d0 3941 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3942 }
3943
29b0f896
AM		 3944 if (!current_templates)
3945 {
b6169b20 3946check_suffix:
29b0f896
AM		 3947 /* See if we can get a match by trimming off a suffix. */
3948 switch (mnem_p[-1])
3949 {
3950 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3951 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3952 i.suffix = SHORT_MNEM_SUFFIX;
3953 else
1a0670f3 3954 /* Fall through. */
29b0f896
AM		 3955 case BYTE_MNEM_SUFFIX:
3956 case QWORD_MNEM_SUFFIX:
3957 i.suffix = mnem_p[-1];
3958 mnem_p[-1] = '\0';
d3ce72d0
NC		 3959 current_templates = (const templates *) hash_find (op_hash,
3960 mnemonic);
29b0f896
AM		 3961 break;
3962 case SHORT_MNEM_SUFFIX:
3963 case LONG_MNEM_SUFFIX:
3964 if (!intel_syntax)
3965 {
3966 i.suffix = mnem_p[-1];
3967 mnem_p[-1] = '\0';
d3ce72d0
NC		 3968 current_templates = (const templates *) hash_find (op_hash,
3969 mnemonic);
29b0f896
AM		 3970 }
3971 break;
252b5132 3972
29b0f896
AM		 3973 /* Intel Syntax. */
3974 case 'd':
3975 if (intel_syntax)
3976 {
9306ca4a 3977 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3978 i.suffix = SHORT_MNEM_SUFFIX;
3979 else
3980 i.suffix = LONG_MNEM_SUFFIX;
3981 mnem_p[-1] = '\0';
d3ce72d0
NC		 3982 current_templates = (const templates *) hash_find (op_hash,
3983 mnemonic);
29b0f896
AM		 3984 }
3985 break;
3986 }
3987 if (!current_templates)
3988 {
3989 as_bad (_("no such instruction: `%s'"), token_start);
3990 return NULL;
3991 }
3992 }
252b5132 3993
40fb9820
L		 3994 if (current_templates->start->opcode_modifier.jump
3995 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3996 {
3997 /* Check for a branch hint. We allow ",pt" and ",pn" for
3998 predict taken and predict not taken respectively.
3999 I'm not sure that branch hints actually do anything on loop
4000 and jcxz insns (JumpByte) for current Pentium4 chips. They
4001 may work in the future and it doesn't hurt to accept them
4002 now. */
4003 if (l[0] == ',' && l[1] == 'p')
4004 {
4005 if (l[2] == 't')
4006 {
4007 if (!add_prefix (DS_PREFIX_OPCODE))
4008 return NULL;
4009 l += 3;
4010 }
4011 else if (l[2] == 'n')
4012 {
4013 if (!add_prefix (CS_PREFIX_OPCODE))
4014 return NULL;
4015 l += 3;
4016 }
4017 }
4018 }
4019 /* Any other comma loses. */
4020 if (*l == ',')
4021 {
4022 as_bad (_("invalid character %s in mnemonic"),
4023 output_invalid (*l));
4024 return NULL;
4025 }
252b5132 4026
29b0f896 4027 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 4028 supported = 0;
4029 for (t = current_templates->start; t < current_templates->end; ++t)
4030 {
c0f3af97
L		 4031 supported |= cpu_flags_match (t);
4032 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 4033 goto skip;
5c6af06e 4034 }
3629bb00 4035
c0f3af97 4036 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 4037 {
4038 as_bad (flag_code == CODE_64BIT
4039 ? _("`%s' is not supported in 64-bit mode")
4040 : _("`%s' is only supported in 64-bit mode"),
4041 current_templates->start->name);
4042 return NULL;
4043 }
c0f3af97 4044 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 4045 {
3629bb00 4046 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 4047 current_templates->start->name,
41aacd83 4048 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 4049 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4050 return NULL;
29b0f896 4051 }
3629bb00
L		 4052
4053skip:
4054 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 4055 && (flag_code != CODE_16BIT))
29b0f896
AM		 4056 {
4057 as_warn (_("use .code16 to ensure correct addressing mode"));
4058 }
252b5132 4059
29b0f896
AM		 4060 return l;
4061}
252b5132 4062
29b0f896 4063static char *
e3bb37b5 4064parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4065{
4066 char *token_start;
3138f287 4067
29b0f896
AM		 4068 /* 1 if operand is pending after ','. */
4069 unsigned int expecting_operand = 0;
252b5132 4070
29b0f896
AM		 4071 /* Non-zero if operand parens not balanced. */
4072 unsigned int paren_not_balanced;
4073
4074 while (*l != END_OF_INSN)
4075 {
4076 /* Skip optional white space before operand. */
4077 if (is_space_char (*l))
4078 ++l;
d02603dc 4079 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4080 {
4081 as_bad (_("invalid character %s before operand %d"),
4082 output_invalid (*l),
4083 i.operands + 1);
4084 return NULL;
4085 }
d02603dc 4086 token_start = l; /* After white space. */
29b0f896
AM		 4087 paren_not_balanced = 0;
4088 while (paren_not_balanced || *l != ',')
4089 {
4090 if (*l == END_OF_INSN)
4091 {
4092 if (paren_not_balanced)
4093 {
4094 if (!intel_syntax)
4095 as_bad (_("unbalanced parenthesis in operand %d."),
4096 i.operands + 1);
4097 else
4098 as_bad (_("unbalanced brackets in operand %d."),
4099 i.operands + 1);
4100 return NULL;
4101 }
4102 else
4103 break; /* we are done */
4104 }
d02603dc 4105 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4106 {
4107 as_bad (_("invalid character %s in operand %d"),
4108 output_invalid (*l),
4109 i.operands + 1);
4110 return NULL;
4111 }
4112 if (!intel_syntax)
4113 {
4114 if (*l == '(')
4115 ++paren_not_balanced;
4116 if (*l == ')')
4117 --paren_not_balanced;
4118 }
4119 else
4120 {
4121 if (*l == '[')
4122 ++paren_not_balanced;
4123 if (*l == ']')
4124 --paren_not_balanced;
4125 }
4126 l++;
4127 }
4128 if (l != token_start)
4129 { /* Yes, we've read in another operand. */
4130 unsigned int operand_ok;
4131 this_operand = i.operands++;
7d5e4556 4132 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4133 if (i.operands > MAX_OPERANDS)
4134 {
4135 as_bad (_("spurious operands; (%d operands/instruction max)"),
4136 MAX_OPERANDS);
4137 return NULL;
4138 }
4139 /* Now parse operand adding info to 'i' as we go along. */
4140 END_STRING_AND_SAVE (l);
4141
4142 if (intel_syntax)
4143 operand_ok =
4144 i386_intel_operand (token_start,
4145 intel_float_operand (mnemonic));
4146 else
a7619375 4147 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4148
4149 RESTORE_END_STRING (l);
4150 if (!operand_ok)
4151 return NULL;
4152 }
4153 else
4154 {
4155 if (expecting_operand)
4156 {
4157 expecting_operand_after_comma:
4158 as_bad (_("expecting operand after ','; got nothing"));
4159 return NULL;
4160 }
4161 if (*l == ',')
4162 {
4163 as_bad (_("expecting operand before ','; got nothing"));
4164 return NULL;
4165 }
4166 }
7f3f1ea2 4167
29b0f896
AM		 4168 /* Now *l must be either ',' or END_OF_INSN. */
4169 if (*l == ',')
4170 {
4171 if (*++l == END_OF_INSN)
4172 {
4173 /* Just skip it, if it's \n complain. */
4174 goto expecting_operand_after_comma;
4175 }
4176 expecting_operand = 1;
4177 }
4178 }
4179 return l;
4180}
7f3f1ea2 4181
050dfa73 4182static void
4d456e3d 4183swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4184{
4185 union i386_op temp_op;
40fb9820 4186 i386_operand_type temp_type;
050dfa73 4187 enum bfd_reloc_code_real temp_reloc;
4eed87de 4188
050dfa73
MM		 4189 temp_type = i.types[xchg2];
4190 i.types[xchg2] = i.types[xchg1];
4191 i.types[xchg1] = temp_type;
4192 temp_op = i.op[xchg2];
4193 i.op[xchg2] = i.op[xchg1];
4194 i.op[xchg1] = temp_op;
4195 temp_reloc = i.reloc[xchg2];
4196 i.reloc[xchg2] = i.reloc[xchg1];
4197 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4198
4199 if (i.mask)
4200 {
4201 if (i.mask->operand == xchg1)
4202 i.mask->operand = xchg2;
4203 else if (i.mask->operand == xchg2)
4204 i.mask->operand = xchg1;
4205 }
4206 if (i.broadcast)
4207 {
4208 if (i.broadcast->operand == xchg1)
4209 i.broadcast->operand = xchg2;
4210 else if (i.broadcast->operand == xchg2)
4211 i.broadcast->operand = xchg1;
4212 }
4213 if (i.rounding)
4214 {
4215 if (i.rounding->operand == xchg1)
4216 i.rounding->operand = xchg2;
4217 else if (i.rounding->operand == xchg2)
4218 i.rounding->operand = xchg1;
4219 }
050dfa73
MM		 4220}
4221
29b0f896 4222static void
e3bb37b5 4223swap_operands (void)
29b0f896 4224{
b7c61d9a 4225 switch (i.operands)
050dfa73 4226 {
c0f3af97 4227 case 5:
b7c61d9a 4228 case 4:
4d456e3d 4229 swap_2_operands (1, i.operands - 2);
1a0670f3 4230 /* Fall through. */
b7c61d9a
L		 4231 case 3:
4232 case 2:
4d456e3d 4233 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4234 break;
4235 default:
4236 abort ();
29b0f896 4237 }
29b0f896
AM		 4238
4239 if (i.mem_operands == 2)
4240 {
4241 const seg_entry *temp_seg;
4242 temp_seg = i.seg[0];
4243 i.seg[0] = i.seg[1];
4244 i.seg[1] = temp_seg;
4245 }
4246}
252b5132 4247
29b0f896
AM		 4248/* Try to ensure constant immediates are represented in the smallest
4249 opcode possible. */
4250static void
e3bb37b5 4251optimize_imm (void)
29b0f896
AM		 4252{
4253 char guess_suffix = 0;
4254 int op;
252b5132 4255
29b0f896
AM		 4256 if (i.suffix)
4257 guess_suffix = i.suffix;
4258 else if (i.reg_operands)
4259 {
4260 /* Figure out a suffix from the last register operand specified.
4261 We can't do this properly yet, ie. excluding InOutPortReg,
4262 but the following works for instructions with immediates.
4263 In any case, we can't set i.suffix yet. */
4264 for (op = i.operands; --op >= 0;)
40fb9820 4265 if (i.types[op].bitfield.reg8)
7ab9ffdd 4266 {
40fb9820
L		 4267 guess_suffix = BYTE_MNEM_SUFFIX;
4268 break;
4269 }
4270 else if (i.types[op].bitfield.reg16)
252b5132 4271 {
40fb9820
L		 4272 guess_suffix = WORD_MNEM_SUFFIX;
4273 break;
4274 }
4275 else if (i.types[op].bitfield.reg32)
4276 {
4277 guess_suffix = LONG_MNEM_SUFFIX;
4278 break;
4279 }
4280 else if (i.types[op].bitfield.reg64)
4281 {
4282 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4283 break;
252b5132 4284 }
29b0f896
AM		 4285 }
4286 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4287 guess_suffix = WORD_MNEM_SUFFIX;
4288
4289 for (op = i.operands; --op >= 0;)
40fb9820 4290 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4291 {
4292 switch (i.op[op].imms->X_op)
252b5132 4293 {
29b0f896
AM		 4294 case O_constant:
4295 /* If a suffix is given, this operand may be shortened. */
4296 switch (guess_suffix)
252b5132 4297 {
29b0f896 4298 case LONG_MNEM_SUFFIX:
40fb9820
L		 4299 i.types[op].bitfield.imm32 = 1;
4300 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4301 break;
4302 case WORD_MNEM_SUFFIX:
40fb9820
L		 4303 i.types[op].bitfield.imm16 = 1;
4304 i.types[op].bitfield.imm32 = 1;
4305 i.types[op].bitfield.imm32s = 1;
4306 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4307 break;
4308 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4309 i.types[op].bitfield.imm8 = 1;
4310 i.types[op].bitfield.imm8s = 1;
4311 i.types[op].bitfield.imm16 = 1;
4312 i.types[op].bitfield.imm32 = 1;
4313 i.types[op].bitfield.imm32s = 1;
4314 i.types[op].bitfield.imm64 = 1;
29b0f896 4315 break;
252b5132 4316 }
252b5132 4317
29b0f896
AM		 4318 /* If this operand is at most 16 bits, convert it
4319 to a signed 16 bit number before trying to see
4320 whether it will fit in an even smaller size.
4321 This allows a 16-bit operand such as $0xffe0 to
4322 be recognised as within Imm8S range. */
40fb9820 4323 if ((i.types[op].bitfield.imm16)
29b0f896 4324 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4325 {
29b0f896
AM		 4326 i.op[op].imms->X_add_number =
4327 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4328 }
a28def75
L		 4329#ifdef BFD64
4330 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4331 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4332 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4333 == 0))
4334 {
4335 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4336 ^ ((offsetT) 1 << 31))
4337 - ((offsetT) 1 << 31));
4338 }
a28def75 4339#endif
40fb9820 4340 i.types[op]
c6fb90c8
L		 4341 = operand_type_or (i.types[op],
4342 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4343
29b0f896
AM		 4344 /* We must avoid matching of Imm32 templates when 64bit
4345 only immediate is available. */
4346 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4347 i.types[op].bitfield.imm32 = 0;
29b0f896 4348 break;
252b5132 4349
29b0f896
AM		 4350 case O_absent:
4351 case O_register:
4352 abort ();
4353
4354 /* Symbols and expressions. */
4355 default:
9cd96992
JB		 4356 /* Convert symbolic operand to proper sizes for matching, but don't
4357 prevent matching a set of insns that only supports sizes other
4358 than those matching the insn suffix. */
4359 {
40fb9820 4360 i386_operand_type mask, allowed;
d3ce72d0 4361 const insn_template *t;
9cd96992 4362
0dfbf9d7
L		 4363 operand_type_set (&mask, 0);
4364 operand_type_set (&allowed, 0);
40fb9820 4365
4eed87de
AM		 4366 for (t = current_templates->start;
4367 t < current_templates->end;
4368 ++t)
c6fb90c8
L		 4369 allowed = operand_type_or (allowed,
4370 t->operand_types[op]);
9cd96992
JB		 4371 switch (guess_suffix)
4372 {
4373 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4374 mask.bitfield.imm64 = 1;
4375 mask.bitfield.imm32s = 1;
9cd96992
JB		 4376 break;
4377 case LONG_MNEM_SUFFIX:
40fb9820 4378 mask.bitfield.imm32 = 1;
9cd96992
JB		 4379 break;
4380 case WORD_MNEM_SUFFIX:
40fb9820 4381 mask.bitfield.imm16 = 1;
9cd96992
JB		 4382 break;
4383 case BYTE_MNEM_SUFFIX:
40fb9820 4384 mask.bitfield.imm8 = 1;
9cd96992
JB		 4385 break;
4386 default:
9cd96992
JB		 4387 break;
4388 }
c6fb90c8 4389 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4390 if (!operand_type_all_zero (&allowed))
c6fb90c8 4391 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4392 }
29b0f896 4393 break;
252b5132 4394 }
29b0f896
AM		 4395 }
4396}
47926f60 4397
29b0f896
AM		 4398/* Try to use the smallest displacement type too. */
4399static void
e3bb37b5 4400optimize_disp (void)
29b0f896
AM		 4401{
4402 int op;
3e73aa7c 4403
29b0f896 4404 for (op = i.operands; --op >= 0;)
40fb9820 4405 if (operand_type_check (i.types[op], disp))
252b5132 4406 {
b300c311 4407 if (i.op[op].disps->X_op == O_constant)
252b5132 4408 {
91d6fa6a 4409 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4410
40fb9820 4411 if (i.types[op].bitfield.disp16
91d6fa6a 4412 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4413 {
4414 /* If this operand is at most 16 bits, convert
4415 to a signed 16 bit number and don't use 64bit
4416 displacement. */
91d6fa6a 4417 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4418 i.types[op].bitfield.disp64 = 0;
b300c311 4419 }
a28def75
L		 4420#ifdef BFD64
4421 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4422 if (i.types[op].bitfield.disp32
91d6fa6a 4423 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4424 {
4425 /* If this operand is at most 32 bits, convert
4426 to a signed 32 bit number and don't use 64bit
4427 displacement. */
91d6fa6a
NC		 4428 op_disp &= (((offsetT) 2 << 31) - 1);
4429 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4430 i.types[op].bitfield.disp64 = 0;
b300c311 4431 }
a28def75 4432#endif
91d6fa6a 4433 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4434 {
40fb9820
L		 4435 i.types[op].bitfield.disp8 = 0;
4436 i.types[op].bitfield.disp16 = 0;
4437 i.types[op].bitfield.disp32 = 0;
4438 i.types[op].bitfield.disp32s = 0;
4439 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4440 i.op[op].disps = 0;
4441 i.disp_operands--;
4442 }
4443 else if (flag_code == CODE_64BIT)
4444 {
91d6fa6a 4445 if (fits_in_signed_long (op_disp))
28a9d8f5 4446 {
40fb9820
L		 4447 i.types[op].bitfield.disp64 = 0;
4448 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4449 }
0e1147d9 4450 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4451 && fits_in_unsigned_long (op_disp))
40fb9820 4452 i.types[op].bitfield.disp32 = 1;
b300c311 4453 }
40fb9820
L		 4454 if ((i.types[op].bitfield.disp32
4455 || i.types[op].bitfield.disp32s
4456 || i.types[op].bitfield.disp16)
91d6fa6a 4457 && fits_in_signed_byte (op_disp))
40fb9820 4458 i.types[op].bitfield.disp8 = 1;
252b5132 4459 }
67a4f2b7
AO		 4460 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4461 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4462 {
4463 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4464 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4465 i.types[op].bitfield.disp8 = 0;
4466 i.types[op].bitfield.disp16 = 0;
4467 i.types[op].bitfield.disp32 = 0;
4468 i.types[op].bitfield.disp32s = 0;
4469 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4470 }
4471 else
b300c311 4472 /* We only support 64bit displacement on constants. */
40fb9820 4473 i.types[op].bitfield.disp64 = 0;
252b5132 4474 }
29b0f896
AM		 4475}
4476
6c30d220
L		 4477/* Check if operands are valid for the instruction. */
4478
4479static int
4480check_VecOperands (const insn_template *t)
4481{
43234a1e
L		 4482 unsigned int op;
4483
6c30d220
L		 4484 /* Without VSIB byte, we can't have a vector register for index. */
4485 if (!t->opcode_modifier.vecsib
4486 && i.index_reg
4487 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4488 || i.index_reg->reg_type.bitfield.regymm
4489 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4490 {
4491 i.error = unsupported_vector_index_register;
4492 return 1;
4493 }
4494
ad8ecc81
MZ		 4495 /* Check if default mask is allowed. */
4496 if (t->opcode_modifier.nodefmask
4497 && (!i.mask || i.mask->mask->reg_num == 0))
4498 {
4499 i.error = no_default_mask;
4500 return 1;
4501 }
4502
7bab8ab5
JB		 4503 /* For VSIB byte, we need a vector register for index, and all vector
4504 registers must be distinct. */
4505 if (t->opcode_modifier.vecsib)
4506 {
4507 if (!i.index_reg
6c30d220
L		 4508 || !((t->opcode_modifier.vecsib == VecSIB128
4509 && i.index_reg->reg_type.bitfield.regxmm)
4510 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4511 && i.index_reg->reg_type.bitfield.regymm)
4512 || (t->opcode_modifier.vecsib == VecSIB512
4513 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4514 {
4515 i.error = invalid_vsib_address;
4516 return 1;
4517 }
4518
43234a1e
L		 4519 gas_assert (i.reg_operands == 2 || i.mask);
4520 if (i.reg_operands == 2 && !i.mask)
4521 {
4522 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4523 || i.types[0].bitfield.regymm);
43234a1e 4524 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4525 || i.types[2].bitfield.regymm);
43234a1e
L		 4526 if (operand_check == check_none)
4527 return 0;
4528 if (register_number (i.op[0].regs)
4529 != register_number (i.index_reg)
4530 && register_number (i.op[2].regs)
4531 != register_number (i.index_reg)
4532 && register_number (i.op[0].regs)
4533 != register_number (i.op[2].regs))
4534 return 0;
4535 if (operand_check == check_error)
4536 {
4537 i.error = invalid_vector_register_set;
4538 return 1;
4539 }
4540 as_warn (_("mask, index, and destination registers should be distinct"));
4541 }
8444f82a
MZ		 4542 else if (i.reg_operands == 1 && i.mask)
4543 {
4544 if ((i.types[1].bitfield.regymm
4545 || i.types[1].bitfield.regzmm)
4546 && (register_number (i.op[1].regs)
4547 == register_number (i.index_reg)))
4548 {
4549 if (operand_check == check_error)
4550 {
4551 i.error = invalid_vector_register_set;
4552 return 1;
4553 }
4554 if (operand_check != check_none)
4555 as_warn (_("index and destination registers should be distinct"));
4556 }
4557 }
43234a1e 4558 }
7bab8ab5 4559
43234a1e
L		 4560 /* Check if broadcast is supported by the instruction and is applied
4561 to the memory operand. */
4562 if (i.broadcast)
4563 {
4564 int broadcasted_opnd_size;
4565
4566 /* Check if specified broadcast is supported in this instruction,
4567 and it's applied to memory operand of DWORD or QWORD type,
4568 depending on VecESize. */
4569 if (i.broadcast->type != t->opcode_modifier.broadcast
4570 || !i.types[i.broadcast->operand].bitfield.mem
4571 || (t->opcode_modifier.vecesize == 0
4572 && !i.types[i.broadcast->operand].bitfield.dword
4573 && !i.types[i.broadcast->operand].bitfield.unspecified)
4574 || (t->opcode_modifier.vecesize == 1
4575 && !i.types[i.broadcast->operand].bitfield.qword
4576 && !i.types[i.broadcast->operand].bitfield.unspecified))
4577 goto bad_broadcast;
4578
4579 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4580 if (i.broadcast->type == BROADCAST_1TO16)
4581 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4582 else if (i.broadcast->type == BROADCAST_1TO8)
4583 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4584 else if (i.broadcast->type == BROADCAST_1TO4)
4585 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4586 else if (i.broadcast->type == BROADCAST_1TO2)
4587 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4588 else
4589 goto bad_broadcast;
4590
4591 if ((broadcasted_opnd_size == 256
4592 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4593 || (broadcasted_opnd_size == 512
4594 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4595 {
4596 bad_broadcast:
4597 i.error = unsupported_broadcast;
4598 return 1;
4599 }
4600 }
4601 /* If broadcast is supported in this instruction, we need to check if
4602 operand of one-element size isn't specified without broadcast. */
4603 else if (t->opcode_modifier.broadcast && i.mem_operands)
4604 {
4605 /* Find memory operand. */
4606 for (op = 0; op < i.operands; op++)
4607 if (operand_type_check (i.types[op], anymem))
4608 break;
4609 gas_assert (op < i.operands);
4610 /* Check size of the memory operand. */
4611 if ((t->opcode_modifier.vecesize == 0
4612 && i.types[op].bitfield.dword)
4613 || (t->opcode_modifier.vecesize == 1
4614 && i.types[op].bitfield.qword))
4615 {
4616 i.error = broadcast_needed;
4617 return 1;
4618 }
4619 }
4620
4621 /* Check if requested masking is supported. */
4622 if (i.mask
4623 && (!t->opcode_modifier.masking
4624 || (i.mask->zeroing
4625 && t->opcode_modifier.masking == MERGING_MASKING)))
4626 {
4627 i.error = unsupported_masking;
4628 return 1;
4629 }
4630
4631 /* Check if masking is applied to dest operand. */
4632 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4633 {
4634 i.error = mask_not_on_destination;
4635 return 1;
4636 }
4637
43234a1e
L		 4638 /* Check RC/SAE. */
4639 if (i.rounding)
4640 {
4641 if ((i.rounding->type != saeonly
4642 && !t->opcode_modifier.staticrounding)
4643 || (i.rounding->type == saeonly
4644 && (t->opcode_modifier.staticrounding
4645 || !t->opcode_modifier.sae)))
4646 {
4647 i.error = unsupported_rc_sae;
4648 return 1;
4649 }
4650 /* If the instruction has several immediate operands and one of
4651 them is rounding, the rounding operand should be the last
4652 immediate operand. */
4653 if (i.imm_operands > 1
4654 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4655 {
43234a1e 4656 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4657 return 1;
4658 }
6c30d220
L		 4659 }
4660
43234a1e
L		 4661 /* Check vector Disp8 operand. */
4662 if (t->opcode_modifier.disp8memshift)
4663 {
4664 if (i.broadcast)
4665 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4666 else
4667 i.memshift = t->opcode_modifier.disp8memshift;
4668
4669 for (op = 0; op < i.operands; op++)
4670 if (operand_type_check (i.types[op], disp)
4671 && i.op[op].disps->X_op == O_constant)
4672 {
4673 offsetT value = i.op[op].disps->X_add_number;
5be33403
L		 4674 int vec_disp8_ok
4675 = (i.disp_encoding != disp_encoding_32bit
4676 && fits_in_vec_disp8 (value));
43234a1e
L		 4677 if (t->operand_types [op].bitfield.vec_disp8)
4678 {
4679 if (vec_disp8_ok)
4680 i.types[op].bitfield.vec_disp8 = 1;
4681 else
4682 {
4683 /* Vector insn can only have Vec_Disp8/Disp32 in
4684 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4685 mode. */
4686 i.types[op].bitfield.disp8 = 0;
4687 if (flag_code != CODE_16BIT)
4688 i.types[op].bitfield.disp16 = 0;
4689 }
4690 }
4691 else if (flag_code != CODE_16BIT)
4692 {
4693 /* One form of this instruction supports vector Disp8.
4694 Try vector Disp8 if we need to use Disp32. */
4695 if (vec_disp8_ok && !fits_in_signed_byte (value))
4696 {
4697 i.error = try_vector_disp8;
4698 return 1;
4699 }
4700 }
4701 }
4702 }
4703 else
4704 i.memshift = -1;
4705
6c30d220
L		 4706 return 0;
4707}
4708
43f3e2ee 4709/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4710 operand types. */
4711
4712static int
4713VEX_check_operands (const insn_template *t)
4714{
43234a1e
L		 4715 /* VREX is only valid with EVEX prefix. */
4716 if (i.need_vrex && !t->opcode_modifier.evex)
4717 {
4718 i.error = invalid_register_operand;
4719 return 1;
4720 }
4721
a683cc34
SP		 4722 if (!t->opcode_modifier.vex)
4723 return 0;
4724
4725 /* Only check VEX_Imm4, which must be the first operand. */
4726 if (t->operand_types[0].bitfield.vec_imm4)
4727 {
4728 if (i.op[0].imms->X_op != O_constant
4729 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4730 {
a65babc9 4731 i.error = bad_imm4;
891edac4
L		 4732 return 1;
4733 }
a683cc34
SP		 4734
4735 /* Turn off Imm8 so that update_imm won't complain. */
4736 i.types[0] = vec_imm4;
4737 }
4738
4739 return 0;
4740}
4741
d3ce72d0 4742static const insn_template *
83b16ac6 4743match_template (char mnem_suffix)
29b0f896
AM		 4744{
4745 /* Points to template once we've found it. */
d3ce72d0 4746 const insn_template *t;
40fb9820 4747 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4748 i386_operand_type overlap4;
29b0f896 4749 unsigned int found_reverse_match;
83b16ac6 4750 i386_opcode_modifier suffix_check, mnemsuf_check;
40fb9820 4751 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4752 int addr_prefix_disp;
a5c311ca 4753 unsigned int j;
3629bb00 4754 unsigned int found_cpu_match;
45664ddb 4755 unsigned int check_register;
5614d22c 4756 enum i386_error specific_error = 0;
29b0f896 4757
c0f3af97
L		 4758#if MAX_OPERANDS != 5
4759# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4760#endif
4761
29b0f896 4762 found_reverse_match = 0;
539e75ad 4763 addr_prefix_disp = -1;
40fb9820
L		 4764
4765 memset (&suffix_check, 0, sizeof (suffix_check));
4766 if (i.suffix == BYTE_MNEM_SUFFIX)
4767 suffix_check.no_bsuf = 1;
4768 else if (i.suffix == WORD_MNEM_SUFFIX)
4769 suffix_check.no_wsuf = 1;
4770 else if (i.suffix == SHORT_MNEM_SUFFIX)
4771 suffix_check.no_ssuf = 1;
4772 else if (i.suffix == LONG_MNEM_SUFFIX)
4773 suffix_check.no_lsuf = 1;
4774 else if (i.suffix == QWORD_MNEM_SUFFIX)
4775 suffix_check.no_qsuf = 1;
4776 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4777 suffix_check.no_ldsuf = 1;
29b0f896 4778
83b16ac6
JB		 4779 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
4780 if (intel_syntax)
4781 {
4782 switch (mnem_suffix)
4783 {
4784 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
4785 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
4786 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
4787 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
4788 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
4789 }
4790 }
4791
01559ecc
L		 4792 /* Must have right number of operands. */
4793 i.error = number_of_operands_mismatch;
4794
45aa61fe 4795 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4796 {
539e75ad
L		 4797 addr_prefix_disp = -1;
4798
29b0f896
AM		 4799 if (i.operands != t->operands)
4800 continue;
4801
50aecf8c 4802 /* Check processor support. */
a65babc9 4803 i.error = unsupported;
c0f3af97
L		 4804 found_cpu_match = (cpu_flags_match (t)
4805 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4806 if (!found_cpu_match)
4807 continue;
4808
e1d4d893 4809 /* Check old gcc support. */
a65babc9 4810 i.error = old_gcc_only;
e1d4d893
L		 4811 if (!old_gcc && t->opcode_modifier.oldgcc)
4812 continue;
4813
4814 /* Check AT&T mnemonic. */
a65babc9 4815 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4816 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4817 continue;
4818
e92bae62 4819 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
a65babc9 4820 i.error = unsupported_syntax;
5c07affc 4821 if ((intel_syntax && t->opcode_modifier.attsyntax)
e92bae62
L		 4822 || (!intel_syntax && t->opcode_modifier.intelsyntax)
4823 || (intel64 && t->opcode_modifier.amd64)
4824 || (!intel64 && t->opcode_modifier.intel64))
1efbbeb4
L		 4825 continue;
4826
20592a94 4827 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4828 i.error = invalid_instruction_suffix;
567e4e96
L		 4829 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4830 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4831 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4832 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4833 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4834 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4835 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896 4836 continue;
83b16ac6
JB		 4837 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4838 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
4839 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
4840 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
4841 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
4842 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
4843 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
4844 continue;
29b0f896 4845
5c07affc 4846 if (!operand_size_match (t))
7d5e4556 4847 continue;
539e75ad 4848
5c07affc
L		 4849 for (j = 0; j < MAX_OPERANDS; j++)
4850 operand_types[j] = t->operand_types[j];
4851
45aa61fe
AM		 4852 /* In general, don't allow 64-bit operands in 32-bit mode. */
4853 if (i.suffix == QWORD_MNEM_SUFFIX
4854 && flag_code != CODE_64BIT
4855 && (intel_syntax
40fb9820 4856 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4857 && !intel_float_operand (t->name))
4858 : intel_float_operand (t->name) != 2)
40fb9820 4859 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4860 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4861 && !operand_types[0].bitfield.regymm
4862 && !operand_types[0].bitfield.regzmm)
40fb9820 4863 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4864 && operand_types[t->operands > 1].bitfield.regxmm
4865 && operand_types[t->operands > 1].bitfield.regymm
4866 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4867 && (t->base_opcode != 0x0fc7
4868 || t->extension_opcode != 1 /* cmpxchg8b */))
4869 continue;
4870
192dc9c6
JB		 4871 /* In general, don't allow 32-bit operands on pre-386. */
4872 else if (i.suffix == LONG_MNEM_SUFFIX
4873 && !cpu_arch_flags.bitfield.cpui386
4874 && (intel_syntax
4875 ? (!t->opcode_modifier.ignoresize
4876 && !intel_float_operand (t->name))
4877 : intel_float_operand (t->name) != 2)
4878 && ((!operand_types[0].bitfield.regmmx
4879 && !operand_types[0].bitfield.regxmm)
4880 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 4881 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 4882 continue;
4883
29b0f896 4884 /* Do not verify operands when there are none. */
50aecf8c 4885 else
29b0f896 4886 {
c6fb90c8 4887 if (!t->operands)
2dbab7d5
L		 4888 /* We've found a match; break out of loop. */
4889 break;
29b0f896 4890 }
252b5132 4891
539e75ad
L		 4892 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4893 into Disp32/Disp16/Disp32 operand. */
4894 if (i.prefix[ADDR_PREFIX] != 0)
4895 {
40fb9820 4896 /* There should be only one Disp operand. */
539e75ad
L		 4897 switch (flag_code)
4898 {
4899 case CODE_16BIT:
40fb9820
L		 4900 for (j = 0; j < MAX_OPERANDS; j++)
4901 {
4902 if (operand_types[j].bitfield.disp16)
4903 {
4904 addr_prefix_disp = j;
4905 operand_types[j].bitfield.disp32 = 1;
4906 operand_types[j].bitfield.disp16 = 0;
4907 break;
4908 }
4909 }
539e75ad
L		 4910 break;
4911 case CODE_32BIT:
40fb9820
L		 4912 for (j = 0; j < MAX_OPERANDS; j++)
4913 {
4914 if (operand_types[j].bitfield.disp32)
4915 {
4916 addr_prefix_disp = j;
4917 operand_types[j].bitfield.disp32 = 0;
4918 operand_types[j].bitfield.disp16 = 1;
4919 break;
4920 }
4921 }
539e75ad
L		 4922 break;
4923 case CODE_64BIT:
40fb9820
L		 4924 for (j = 0; j < MAX_OPERANDS; j++)
4925 {
4926 if (operand_types[j].bitfield.disp64)
4927 {
4928 addr_prefix_disp = j;
4929 operand_types[j].bitfield.disp64 = 0;
4930 operand_types[j].bitfield.disp32 = 1;
4931 break;
4932 }
4933 }
539e75ad
L		 4934 break;
4935 }
539e75ad
L		 4936 }
4937
02a86693
L		 4938 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4939 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
4940 continue;
4941
56ffb741
L		 4942 /* We check register size if needed. */
4943 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4944 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4945 switch (t->operands)
4946 {
4947 case 1:
40fb9820 4948 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4949 continue;
4950 break;
4951 case 2:
8b38ad71
L		 4952 /* xchg %eax, %eax is a special case. It is an aliase for nop
4953 only in 32bit mode and we can use opcode 0x90. In 64bit
4954 mode, we can't use 0x90 for xchg %eax, %eax since it should
4955 zero-extend %eax to %rax. */
4956 if (flag_code == CODE_64BIT
4957 && t->base_opcode == 0x90
0dfbf9d7
L		 4958 && operand_type_equal (&i.types [0], &acc32)
4959 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4960 continue;
b6169b20
L		 4961 if (i.swap_operand)
4962 {
4963 /* If we swap operand in encoding, we either match
4964 the next one or reverse direction of operands. */
4965 if (t->opcode_modifier.s)
4966 continue;
4967 else if (t->opcode_modifier.d)
4968 goto check_reverse;
4969 }
1a0670f3 4970 /* Fall through. */
b6169b20 4971
29b0f896 4972 case 3:
fa99fab2
L		 4973 /* If we swap operand in encoding, we match the next one. */
4974 if (i.swap_operand && t->opcode_modifier.s)
4975 continue;
1a0670f3 4976 /* Fall through. */
f48ff2ae 4977 case 4:
c0f3af97 4978 case 5:
c6fb90c8 4979 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4980 if (!operand_type_match (overlap0, i.types[0])
4981 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4982 || (check_register
4983 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4984 operand_types[0],
4985 overlap1, i.types[1],
4986 operand_types[1])))
29b0f896
AM		 4987 {
4988 /* Check if other direction is valid ... */
40fb9820 4989 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4990 continue;
4991
b6169b20 4992check_reverse:
29b0f896 4993 /* Try reversing direction of operands. */
c6fb90c8
L		 4994 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4995 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4996 if (!operand_type_match (overlap0, i.types[0])
4997 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4998 || (check_register
4999 && !operand_type_register_match (overlap0,
5000 i.types[0],
5001 operand_types[1],
5002 overlap1,
5003 i.types[1],
5004 operand_types[0])))
29b0f896
AM		 5005 {
5006 /* Does not match either direction. */
5007 continue;
5008 }
5009 /* found_reverse_match holds which of D or FloatDR
5010 we've found. */
40fb9820 5011 if (t->opcode_modifier.d)
8a2ed489 5012 found_reverse_match = Opcode_D;
40fb9820 5013 else if (t->opcode_modifier.floatd)
8a2ed489
L		 5014 found_reverse_match = Opcode_FloatD;
5015 else
5016 found_reverse_match = 0;
40fb9820 5017 if (t->opcode_modifier.floatr)
8a2ed489 5018 found_reverse_match |= Opcode_FloatR;
29b0f896 5019 }
f48ff2ae 5020 else
29b0f896 5021 {
f48ff2ae 5022 /* Found a forward 2 operand match here. */
d1cbb4db
L		 5023 switch (t->operands)
5024 {
c0f3af97
L		 5025 case 5:
5026 overlap4 = operand_type_and (i.types[4],
5027 operand_types[4]);
1a0670f3 5028 /* Fall through. */
d1cbb4db 5029 case 4:
c6fb90c8
L		 5030 overlap3 = operand_type_and (i.types[3],
5031 operand_types[3]);
1a0670f3 5032 /* Fall through. */
d1cbb4db 5033 case 3:
c6fb90c8
L		 5034 overlap2 = operand_type_and (i.types[2],
5035 operand_types[2]);
d1cbb4db
L		 5036 break;
5037 }
29b0f896 5038
f48ff2ae
L		 5039 switch (t->operands)
5040 {
c0f3af97
L		 5041 case 5:
5042 if (!operand_type_match (overlap4, i.types[4])
5043 || !operand_type_register_match (overlap3,
5044 i.types[3],
5045 operand_types[3],
5046 overlap4,
5047 i.types[4],
5048 operand_types[4]))
5049 continue;
1a0670f3 5050 /* Fall through. */
f48ff2ae 5051 case 4:
40fb9820 5052 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 5053 || (check_register
5054 && !operand_type_register_match (overlap2,
5055 i.types[2],
5056 operand_types[2],
5057 overlap3,
5058 i.types[3],
5059 operand_types[3])))
f48ff2ae 5060 continue;
1a0670f3 5061 /* Fall through. */
f48ff2ae
L		 5062 case 3:
5063 /* Here we make use of the fact that there are no
5064 reverse match 3 operand instructions, and all 3
5065 operand instructions only need to be checked for
5066 register consistency between operands 2 and 3. */
40fb9820 5067 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 5068 || (check_register
5069 && !operand_type_register_match (overlap1,
5070 i.types[1],
5071 operand_types[1],
5072 overlap2,
5073 i.types[2],
5074 operand_types[2])))
f48ff2ae
L		 5075 continue;
5076 break;
5077 }
29b0f896 5078 }
f48ff2ae 5079 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5080 slip through to break. */
5081 }
3629bb00 5082 if (!found_cpu_match)
29b0f896
AM		 5083 {
5084 found_reverse_match = 0;
5085 continue;
5086 }
c0f3af97 5087
5614d22c
JB		 5088 /* Check if vector and VEX operands are valid. */
5089 if (check_VecOperands (t) || VEX_check_operands (t))
5090 {
5091 specific_error = i.error;
5092 continue;
5093 }
a683cc34 5094
29b0f896
AM		 5095 /* We've found a match; break out of loop. */
5096 break;
5097 }
5098
5099 if (t == current_templates->end)
5100 {
5101 /* We found no match. */
a65babc9 5102 const char *err_msg;
5614d22c 5103 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5104 {
5105 default:
5106 abort ();
86e026a4 5107 case operand_size_mismatch:
a65babc9
L		 5108 err_msg = _("operand size mismatch");
5109 break;
5110 case operand_type_mismatch:
5111 err_msg = _("operand type mismatch");
5112 break;
5113 case register_type_mismatch:
5114 err_msg = _("register type mismatch");
5115 break;
5116 case number_of_operands_mismatch:
5117 err_msg = _("number of operands mismatch");
5118 break;
5119 case invalid_instruction_suffix:
5120 err_msg = _("invalid instruction suffix");
5121 break;
5122 case bad_imm4:
4a2608e3 5123 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 5124 break;
5125 case old_gcc_only:
5126 err_msg = _("only supported with old gcc");
5127 break;
5128 case unsupported_with_intel_mnemonic:
5129 err_msg = _("unsupported with Intel mnemonic");
5130 break;
5131 case unsupported_syntax:
5132 err_msg = _("unsupported syntax");
5133 break;
5134 case unsupported:
35262a23 5135 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5136 current_templates->start->name);
5137 return NULL;
6c30d220
L		 5138 case invalid_vsib_address:
5139 err_msg = _("invalid VSIB address");
5140 break;
7bab8ab5
JB		 5141 case invalid_vector_register_set:
5142 err_msg = _("mask, index, and destination registers must be distinct");
5143 break;
6c30d220
L		 5144 case unsupported_vector_index_register:
5145 err_msg = _("unsupported vector index register");
5146 break;
43234a1e
L		 5147 case unsupported_broadcast:
5148 err_msg = _("unsupported broadcast");
5149 break;
5150 case broadcast_not_on_src_operand:
5151 err_msg = _("broadcast not on source memory operand");
5152 break;
5153 case broadcast_needed:
5154 err_msg = _("broadcast is needed for operand of such type");
5155 break;
5156 case unsupported_masking:
5157 err_msg = _("unsupported masking");
5158 break;
5159 case mask_not_on_destination:
5160 err_msg = _("mask not on destination operand");
5161 break;
5162 case no_default_mask:
5163 err_msg = _("default mask isn't allowed");
5164 break;
5165 case unsupported_rc_sae:
5166 err_msg = _("unsupported static rounding/sae");
5167 break;
5168 case rc_sae_operand_not_last_imm:
5169 if (intel_syntax)
5170 err_msg = _("RC/SAE operand must precede immediate operands");
5171 else
5172 err_msg = _("RC/SAE operand must follow immediate operands");
5173 break;
5174 case invalid_register_operand:
5175 err_msg = _("invalid register operand");
5176 break;
a65babc9
L		 5177 }
5178 as_bad (_("%s for `%s'"), err_msg,
891edac4 5179 current_templates->start->name);
fa99fab2 5180 return NULL;
29b0f896 5181 }
252b5132 5182
29b0f896
AM		 5183 if (!quiet_warnings)
5184 {
5185 if (!intel_syntax
40fb9820
L		 5186 && (i.types[0].bitfield.jumpabsolute
5187 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5188 {
5189 as_warn (_("indirect %s without `*'"), t->name);
5190 }
5191
40fb9820
L		 5192 if (t->opcode_modifier.isprefix
5193 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5194 {
5195 /* Warn them that a data or address size prefix doesn't
5196 affect assembly of the next line of code. */
5197 as_warn (_("stand-alone `%s' prefix"), t->name);
5198 }
5199 }
5200
5201 /* Copy the template we found. */
5202 i.tm = *t;
539e75ad
L		 5203
5204 if (addr_prefix_disp != -1)
5205 i.tm.operand_types[addr_prefix_disp]
5206 = operand_types[addr_prefix_disp];
5207
29b0f896
AM		 5208 if (found_reverse_match)
5209 {
5210 /* If we found a reverse match we must alter the opcode
5211 direction bit. found_reverse_match holds bits to change
5212 (different for int & float insns). */
5213
5214 i.tm.base_opcode ^= found_reverse_match;
5215
539e75ad
L		 5216 i.tm.operand_types[0] = operand_types[1];
5217 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5218 }
5219
fa99fab2 5220 return t;
29b0f896
AM		 5221}
5222
5223static int
e3bb37b5 5224check_string (void)
29b0f896 5225{
40fb9820
L		 5226 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5227 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5228 {
5229 if (i.seg[0] != NULL && i.seg[0] != &es)
5230 {
a87af027 5231 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5232 i.tm.name,
a87af027
JB		 5233 mem_op + 1,
5234 register_prefix);
29b0f896
AM		 5235 return 0;
5236 }
5237 /* There's only ever one segment override allowed per instruction.
5238 This instruction possibly has a legal segment override on the
5239 second operand, so copy the segment to where non-string
5240 instructions store it, allowing common code. */
5241 i.seg[0] = i.seg[1];
5242 }
40fb9820 5243 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5244 {
5245 if (i.seg[1] != NULL && i.seg[1] != &es)
5246 {
a87af027 5247 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5248 i.tm.name,
a87af027
JB		 5249 mem_op + 2,
5250 register_prefix);
29b0f896
AM		 5251 return 0;
5252 }
5253 }
5254 return 1;
5255}
5256
5257static int
543613e9 5258process_suffix (void)
29b0f896
AM		 5259{
5260 /* If matched instruction specifies an explicit instruction mnemonic
5261 suffix, use it. */
40fb9820
L		 5262 if (i.tm.opcode_modifier.size16)
5263 i.suffix = WORD_MNEM_SUFFIX;
5264 else if (i.tm.opcode_modifier.size32)
5265 i.suffix = LONG_MNEM_SUFFIX;
5266 else if (i.tm.opcode_modifier.size64)
5267 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5268 else if (i.reg_operands)
5269 {
5270 /* If there's no instruction mnemonic suffix we try to invent one
5271 based on register operands. */
5272 if (!i.suffix)
5273 {
5274 /* We take i.suffix from the last register operand specified,
5275 Destination register type is more significant than source
381d071f
L		 5276 register type. crc32 in SSE4.2 prefers source register
5277 type. */
5278 if (i.tm.base_opcode == 0xf20f38f1)
5279 {
40fb9820
L		 5280 if (i.types[0].bitfield.reg16)
5281 i.suffix = WORD_MNEM_SUFFIX;
5282 else if (i.types[0].bitfield.reg32)
5283 i.suffix = LONG_MNEM_SUFFIX;
5284 else if (i.types[0].bitfield.reg64)
5285 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5286 }
9344ff29 5287 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5288 {
40fb9820 5289 if (i.types[0].bitfield.reg8)
20592a94
L		 5290 i.suffix = BYTE_MNEM_SUFFIX;
5291 }
381d071f
L		 5292
5293 if (!i.suffix)
5294 {
5295 int op;
5296
20592a94
L		 5297 if (i.tm.base_opcode == 0xf20f38f1
5298 || i.tm.base_opcode == 0xf20f38f0)
5299 {
5300 /* We have to know the operand size for crc32. */
5301 as_bad (_("ambiguous memory operand size for `%s`"),
5302 i.tm.name);
5303 return 0;
5304 }
5305
381d071f 5306 for (op = i.operands; --op >= 0;)
40fb9820 5307 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5308 {
40fb9820
L		 5309 if (i.types[op].bitfield.reg8)
5310 {
5311 i.suffix = BYTE_MNEM_SUFFIX;
5312 break;
5313 }
5314 else if (i.types[op].bitfield.reg16)
5315 {
5316 i.suffix = WORD_MNEM_SUFFIX;
5317 break;
5318 }
5319 else if (i.types[op].bitfield.reg32)
5320 {
5321 i.suffix = LONG_MNEM_SUFFIX;
5322 break;
5323 }
5324 else if (i.types[op].bitfield.reg64)
5325 {
5326 i.suffix = QWORD_MNEM_SUFFIX;
5327 break;
5328 }
381d071f
L		 5329 }
5330 }
29b0f896
AM		 5331 }
5332 else if (i.suffix == BYTE_MNEM_SUFFIX)
5333 {
2eb952a4
L		 5334 if (intel_syntax
5335 && i.tm.opcode_modifier.ignoresize
5336 && i.tm.opcode_modifier.no_bsuf)
5337 i.suffix = 0;
5338 else if (!check_byte_reg ())
29b0f896
AM		 5339 return 0;
5340 }
5341 else if (i.suffix == LONG_MNEM_SUFFIX)
5342 {
2eb952a4
L		 5343 if (intel_syntax
5344 && i.tm.opcode_modifier.ignoresize
5345 && i.tm.opcode_modifier.no_lsuf)
5346 i.suffix = 0;
5347 else if (!check_long_reg ())
29b0f896
AM		 5348 return 0;
5349 }
5350 else if (i.suffix == QWORD_MNEM_SUFFIX)
5351 {
955e1e6a
L		 5352 if (intel_syntax
5353 && i.tm.opcode_modifier.ignoresize
5354 && i.tm.opcode_modifier.no_qsuf)
5355 i.suffix = 0;
5356 else if (!check_qword_reg ())
29b0f896
AM		 5357 return 0;
5358 }
5359 else if (i.suffix == WORD_MNEM_SUFFIX)
5360 {
2eb952a4
L		 5361 if (intel_syntax
5362 && i.tm.opcode_modifier.ignoresize
5363 && i.tm.opcode_modifier.no_wsuf)
5364 i.suffix = 0;
5365 else if (!check_word_reg ())
29b0f896
AM		 5366 return 0;
5367 }
c0f3af97 5368 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5369 || i.suffix == YMMWORD_MNEM_SUFFIX
5370 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5371 {
43234a1e 5372 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5373 should check if it is a valid suffix. */
5374 }
40fb9820 5375 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5376 /* Do nothing if the instruction is going to ignore the prefix. */
5377 ;
5378 else
5379 abort ();
5380 }
40fb9820 5381 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5382 && !i.suffix
5383 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5384 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5385 {
5386 i.suffix = stackop_size;
5387 }
9306ca4a
JB		 5388 else if (intel_syntax
5389 && !i.suffix
40fb9820
L		 5390 && (i.tm.operand_types[0].bitfield.jumpabsolute
5391 || i.tm.opcode_modifier.jumpbyte
5392 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5393 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5394 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5395 {
5396 switch (flag_code)
5397 {
5398 case CODE_64BIT:
40fb9820 5399 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5400 {
5401 i.suffix = QWORD_MNEM_SUFFIX;
5402 break;
5403 }
1a0670f3 5404 /* Fall through. */
9306ca4a 5405 case CODE_32BIT:
40fb9820 5406 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5407 i.suffix = LONG_MNEM_SUFFIX;
5408 break;
5409 case CODE_16BIT:
40fb9820 5410 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5411 i.suffix = WORD_MNEM_SUFFIX;
5412 break;
5413 }
5414 }
252b5132 5415
9306ca4a 5416 if (!i.suffix)
29b0f896 5417 {
9306ca4a
JB		 5418 if (!intel_syntax)
5419 {
40fb9820 5420 if (i.tm.opcode_modifier.w)
9306ca4a 5421 {
4eed87de
AM		 5422 as_bad (_("no instruction mnemonic suffix given and "
5423 "no register operands; can't size instruction"));
9306ca4a
JB		 5424 return 0;
5425 }
5426 }
5427 else
5428 {
40fb9820 5429 unsigned int suffixes;
7ab9ffdd 5430
40fb9820
L		 5431 suffixes = !i.tm.opcode_modifier.no_bsuf;
5432 if (!i.tm.opcode_modifier.no_wsuf)
5433 suffixes |= 1 << 1;
5434 if (!i.tm.opcode_modifier.no_lsuf)
5435 suffixes |= 1 << 2;
fc4adea1 5436 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5437 suffixes |= 1 << 3;
5438 if (!i.tm.opcode_modifier.no_ssuf)
5439 suffixes |= 1 << 4;
5440 if (!i.tm.opcode_modifier.no_qsuf)
5441 suffixes |= 1 << 5;
5442
5443 /* There are more than suffix matches. */
5444 if (i.tm.opcode_modifier.w
9306ca4a 5445 || ((suffixes & (suffixes - 1))
40fb9820
L		 5446 && !i.tm.opcode_modifier.defaultsize
5447 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5448 {
5449 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5450 return 0;
5451 }
5452 }
29b0f896 5453 }
252b5132 5454
9306ca4a
JB		 5455 /* Change the opcode based on the operand size given by i.suffix;
5456 We don't need to change things for byte insns. */
5457
582d5edd
L		 5458 if (i.suffix
5459 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5460 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5461 && i.suffix != YMMWORD_MNEM_SUFFIX
5462 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5463 {
5464 /* It's not a byte, select word/dword operation. */
40fb9820 5465 if (i.tm.opcode_modifier.w)
29b0f896 5466 {
40fb9820 5467 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5468 i.tm.base_opcode |= 8;
5469 else
5470 i.tm.base_opcode |= 1;
5471 }
0f3f3d8b 5472
29b0f896
AM		 5473 /* Now select between word & dword operations via the operand
5474 size prefix, except for instructions that will ignore this
5475 prefix anyway. */
ca61edf2 5476 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5477 {
ca61edf2
L		 5478 /* The address size override prefix changes the size of the
5479 first operand. */
40fb9820
L		 5480 if ((flag_code == CODE_32BIT
5481 && i.op->regs[0].reg_type.bitfield.reg16)
5482 || (flag_code != CODE_32BIT
5483 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5484 if (!add_prefix (ADDR_PREFIX_OPCODE))
5485 return 0;
5486 }
5487 else if (i.suffix != QWORD_MNEM_SUFFIX
5488 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5489 && !i.tm.opcode_modifier.ignoresize
5490 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5491 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5492 || (flag_code == CODE_64BIT
40fb9820 5493 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5494 {
5495 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5496
40fb9820 5497 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5498 prefix = ADDR_PREFIX_OPCODE;
252b5132 5499
29b0f896
AM		 5500 if (!add_prefix (prefix))
5501 return 0;
24eab124 5502 }
252b5132 5503
29b0f896
AM		 5504 /* Set mode64 for an operand. */
5505 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5506 && flag_code == CODE_64BIT
40fb9820 5507 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5508 {
5509 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5510 need rex64. cmpxchg8b is also a special case. */
5511 if (! (i.operands == 2
5512 && i.tm.base_opcode == 0x90
5513 && i.tm.extension_opcode == None
0dfbf9d7
L		 5514 && operand_type_equal (&i.types [0], &acc64)
5515 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5516 && ! (i.operands == 1
5517 && i.tm.base_opcode == 0xfc7
5518 && i.tm.extension_opcode == 1
40fb9820
L		 5519 && !operand_type_check (i.types [0], reg)
5520 && operand_type_check (i.types [0], anymem)))
f6bee062 5521 i.rex |= REX_W;
46e883c5 5522 }
3e73aa7c 5523
29b0f896
AM		 5524 /* Size floating point instruction. */
5525 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5526 if (i.tm.opcode_modifier.floatmf)
543613e9 5527 i.tm.base_opcode ^= 4;
29b0f896 5528 }
7ecd2f8b 5529
29b0f896
AM		 5530 return 1;
5531}
3e73aa7c 5532
29b0f896 5533static int
543613e9 5534check_byte_reg (void)
29b0f896
AM		 5535{
5536 int op;
543613e9 5537
29b0f896
AM		 5538 for (op = i.operands; --op >= 0;)
5539 {
5540 /* If this is an eight bit register, it's OK. If it's the 16 or
5541 32 bit version of an eight bit register, we will just use the
5542 low portion, and that's OK too. */
40fb9820 5543 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5544 continue;
5545
5a819eb9
JB		 5546 /* I/O port address operands are OK too. */
5547 if (i.tm.operand_types[op].bitfield.inoutportreg)
5548 continue;
5549
9344ff29
L		 5550 /* crc32 doesn't generate this warning. */
5551 if (i.tm.base_opcode == 0xf20f38f0)
5552 continue;
5553
40fb9820
L		 5554 if ((i.types[op].bitfield.reg16
5555 || i.types[op].bitfield.reg32
5556 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5557 && i.op[op].regs->reg_num < 4
5558 /* Prohibit these changes in 64bit mode, since the lowering
5559 would be more complicated. */
5560 && flag_code != CODE_64BIT)
29b0f896 5561 {
29b0f896 5562#if REGISTER_WARNINGS
5a819eb9 5563 if (!quiet_warnings)
a540244d
L		 5564 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5565 register_prefix,
40fb9820 5566 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5567 ? REGNAM_AL - REGNAM_AX
5568 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5569 register_prefix,
29b0f896
AM		 5570 i.op[op].regs->reg_name,
5571 i.suffix);
5572#endif
5573 continue;
5574 }
5575 /* Any other register is bad. */
40fb9820
L		 5576 if (i.types[op].bitfield.reg16
5577 || i.types[op].bitfield.reg32
5578 || i.types[op].bitfield.reg64
5579 || i.types[op].bitfield.regmmx
5580 || i.types[op].bitfield.regxmm
c0f3af97 5581 || i.types[op].bitfield.regymm
43234a1e 5582 || i.types[op].bitfield.regzmm
40fb9820
L		 5583 || i.types[op].bitfield.sreg2
5584 || i.types[op].bitfield.sreg3
5585 || i.types[op].bitfield.control
5586 || i.types[op].bitfield.debug
5587 || i.types[op].bitfield.test
5588 || i.types[op].bitfield.floatreg
5589 || i.types[op].bitfield.floatacc)
29b0f896 5590 {
a540244d
L		 5591 as_bad (_("`%s%s' not allowed with `%s%c'"),
5592 register_prefix,
29b0f896
AM		 5593 i.op[op].regs->reg_name,
5594 i.tm.name,
5595 i.suffix);
5596 return 0;
5597 }
5598 }
5599 return 1;
5600}
5601
5602static int
e3bb37b5 5603check_long_reg (void)
29b0f896
AM		 5604{
5605 int op;
5606
5607 for (op = i.operands; --op >= 0;)
5608 /* Reject eight bit registers, except where the template requires
5609 them. (eg. movzb) */
40fb9820
L		 5610 if (i.types[op].bitfield.reg8
5611 && (i.tm.operand_types[op].bitfield.reg16
5612 || i.tm.operand_types[op].bitfield.reg32
5613 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5614 {
a540244d
L		 5615 as_bad (_("`%s%s' not allowed with `%s%c'"),
5616 register_prefix,
29b0f896
AM		 5617 i.op[op].regs->reg_name,
5618 i.tm.name,
5619 i.suffix);
5620 return 0;
5621 }
e4630f71 5622 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5623 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5624 && i.types[op].bitfield.reg16
5625 && (i.tm.operand_types[op].bitfield.reg32
5626 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5627 {
5628 /* Prohibit these changes in the 64bit mode, since the
5629 lowering is more complicated. */
5630 if (flag_code == CODE_64BIT)
252b5132 5631 {
2b5d6a91 5632 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5633 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5634 i.suffix);
5635 return 0;
252b5132 5636 }
29b0f896 5637#if REGISTER_WARNINGS
cecf1424
JB		 5638 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5639 register_prefix,
5640 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5641 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5642#endif
252b5132 5643 }
e4630f71 5644 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5645 else if (i.types[op].bitfield.reg64
5646 && (i.tm.operand_types[op].bitfield.reg32
5647 || i.tm.operand_types[op].bitfield.acc))
252b5132 5648 {
34828aad 5649 if (intel_syntax
ca61edf2 5650 && i.tm.opcode_modifier.toqword
40fb9820 5651 && !i.types[0].bitfield.regxmm)
34828aad 5652 {
ca61edf2 5653 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5654 i.suffix = QWORD_MNEM_SUFFIX;
5655 }
5656 else
5657 {
2b5d6a91 5658 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5659 register_prefix, i.op[op].regs->reg_name,
5660 i.suffix);
5661 return 0;
5662 }
29b0f896
AM		 5663 }
5664 return 1;
5665}
252b5132 5666
29b0f896 5667static int
e3bb37b5 5668check_qword_reg (void)
29b0f896
AM		 5669{
5670 int op;
252b5132 5671
29b0f896
AM		 5672 for (op = i.operands; --op >= 0; )
5673 /* Reject eight bit registers, except where the template requires
5674 them. (eg. movzb) */
40fb9820
L		 5675 if (i.types[op].bitfield.reg8
5676 && (i.tm.operand_types[op].bitfield.reg16
5677 || i.tm.operand_types[op].bitfield.reg32
5678 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5679 {
a540244d
L		 5680 as_bad (_("`%s%s' not allowed with `%s%c'"),
5681 register_prefix,
29b0f896
AM		 5682 i.op[op].regs->reg_name,
5683 i.tm.name,
5684 i.suffix);
5685 return 0;
5686 }
e4630f71 5687 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5688 else if ((i.types[op].bitfield.reg16
5689 || i.types[op].bitfield.reg32)
33d0ab95 5690 && (i.tm.operand_types[op].bitfield.reg64
40fb9820 5691 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5692 {
5693 /* Prohibit these changes in the 64bit mode, since the
5694 lowering is more complicated. */
34828aad 5695 if (intel_syntax
ca61edf2 5696 && i.tm.opcode_modifier.todword
40fb9820 5697 && !i.types[0].bitfield.regxmm)
34828aad 5698 {
ca61edf2 5699 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5700 i.suffix = LONG_MNEM_SUFFIX;
5701 }
5702 else
5703 {
2b5d6a91 5704 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5705 register_prefix, i.op[op].regs->reg_name,
5706 i.suffix);
5707 return 0;
5708 }
252b5132 5709 }
29b0f896
AM		 5710 return 1;
5711}
252b5132 5712
29b0f896 5713static int
e3bb37b5 5714check_word_reg (void)
29b0f896
AM		 5715{
5716 int op;
5717 for (op = i.operands; --op >= 0;)
5718 /* Reject eight bit registers, except where the template requires
5719 them. (eg. movzb) */
40fb9820
L		 5720 if (i.types[op].bitfield.reg8
5721 && (i.tm.operand_types[op].bitfield.reg16
5722 || i.tm.operand_types[op].bitfield.reg32
5723 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5724 {
a540244d
L		 5725 as_bad (_("`%s%s' not allowed with `%s%c'"),
5726 register_prefix,
29b0f896
AM		 5727 i.op[op].regs->reg_name,
5728 i.tm.name,
5729 i.suffix);
5730 return 0;
5731 }
e4630f71 5732 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5733 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5734 && (i.types[op].bitfield.reg32
5735 || i.types[op].bitfield.reg64)
40fb9820
L		 5736 && (i.tm.operand_types[op].bitfield.reg16
5737 || i.tm.operand_types[op].bitfield.acc))
252b5132 5738 {
29b0f896
AM		 5739 /* Prohibit these changes in the 64bit mode, since the
5740 lowering is more complicated. */
5741 if (flag_code == CODE_64BIT)
252b5132 5742 {
2b5d6a91 5743 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5744 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5745 i.suffix);
5746 return 0;
252b5132 5747 }
29b0f896 5748#if REGISTER_WARNINGS
cecf1424
JB		 5749 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5750 register_prefix,
5751 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5752 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5753#endif
5754 }
5755 return 1;
5756}
252b5132 5757
29b0f896 5758static int
40fb9820 5759update_imm (unsigned int j)
29b0f896 5760{
bc0844ae 5761 i386_operand_type overlap = i.types[j];
40fb9820
L		 5762 if ((overlap.bitfield.imm8
5763 || overlap.bitfield.imm8s
5764 || overlap.bitfield.imm16
5765 || overlap.bitfield.imm32
5766 || overlap.bitfield.imm32s
5767 || overlap.bitfield.imm64)
0dfbf9d7
L		 5768 && !operand_type_equal (&overlap, &imm8)
5769 && !operand_type_equal (&overlap, &imm8s)
5770 && !operand_type_equal (&overlap, &imm16)
5771 && !operand_type_equal (&overlap, &imm32)
5772 && !operand_type_equal (&overlap, &imm32s)
5773 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5774 {
5775 if (i.suffix)
5776 {
40fb9820
L		 5777 i386_operand_type temp;
5778
0dfbf9d7 5779 operand_type_set (&temp, 0);
7ab9ffdd 5780 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5781 {
5782 temp.bitfield.imm8 = overlap.bitfield.imm8;
5783 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5784 }
5785 else if (i.suffix == WORD_MNEM_SUFFIX)
5786 temp.bitfield.imm16 = overlap.bitfield.imm16;
5787 else if (i.suffix == QWORD_MNEM_SUFFIX)
5788 {
5789 temp.bitfield.imm64 = overlap.bitfield.imm64;
5790 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5791 }
5792 else
5793 temp.bitfield.imm32 = overlap.bitfield.imm32;
5794 overlap = temp;
29b0f896 5795 }
0dfbf9d7
L		 5796 else if (operand_type_equal (&overlap, &imm16_32_32s)
5797 || operand_type_equal (&overlap, &imm16_32)
5798 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5799 {
40fb9820 5800 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5801 overlap = imm16;
40fb9820 5802 else
65da13b5 5803 overlap = imm32s;
29b0f896 5804 }
0dfbf9d7
L		 5805 if (!operand_type_equal (&overlap, &imm8)
5806 && !operand_type_equal (&overlap, &imm8s)
5807 && !operand_type_equal (&overlap, &imm16)
5808 && !operand_type_equal (&overlap, &imm32)
5809 && !operand_type_equal (&overlap, &imm32s)
5810 && !operand_type_equal (&overlap, &imm64))
29b0f896 5811 {
4eed87de
AM		 5812 as_bad (_("no instruction mnemonic suffix given; "
5813 "can't determine immediate size"));
29b0f896
AM		 5814 return 0;
5815 }
5816 }
40fb9820 5817 i.types[j] = overlap;
29b0f896 5818
40fb9820
L		 5819 return 1;
5820}
5821
5822static int
5823finalize_imm (void)
5824{
bc0844ae 5825 unsigned int j, n;
29b0f896 5826
bc0844ae
L		 5827 /* Update the first 2 immediate operands. */
5828 n = i.operands > 2 ? 2 : i.operands;
5829 if (n)
5830 {
5831 for (j = 0; j < n; j++)
5832 if (update_imm (j) == 0)
5833 return 0;
40fb9820 5834
bc0844ae
L		 5835 /* The 3rd operand can't be immediate operand. */
5836 gas_assert (operand_type_check (i.types[2], imm) == 0);
5837 }
29b0f896
AM		 5838
5839 return 1;
5840}
5841
c0f3af97
L		 5842static int
5843bad_implicit_operand (int xmm)
5844{
91d6fa6a
NC		 5845 const char *ireg = xmm ? "xmm0" : "ymm0";
5846
c0f3af97
L		 5847 if (intel_syntax)
5848 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5849 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5850 else
5851 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5852 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5853 return 0;
5854}
5855
29b0f896 5856static int
e3bb37b5 5857process_operands (void)
29b0f896
AM		 5858{
5859 /* Default segment register this instruction will use for memory
5860 accesses. 0 means unknown. This is only for optimizing out
5861 unnecessary segment overrides. */
5862 const seg_entry *default_seg = 0;
5863
2426c15f 5864 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5865 {
91d6fa6a
NC		 5866 unsigned int dupl = i.operands;
5867 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5868 unsigned int j;
5869
c0f3af97 5870 /* The destination must be an xmm register. */
9c2799c2 5871 gas_assert (i.reg_operands
91d6fa6a 5872 && MAX_OPERANDS > dupl
7ab9ffdd 5873 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5874
5875 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5876 {
c0f3af97 5877 /* The first operand is implicit and must be xmm0. */
9c2799c2 5878 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5879 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5880 return bad_implicit_operand (1);
5881
8cd7925b 5882 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5883 {
5884 /* Keep xmm0 for instructions with VEX prefix and 3
5885 sources. */
5886 goto duplicate;
5887 }
e2ec9d29 5888 else
c0f3af97
L		 5889 {
5890 /* We remove the first xmm0 and keep the number of
5891 operands unchanged, which in fact duplicates the
5892 destination. */
5893 for (j = 1; j < i.operands; j++)
5894 {
5895 i.op[j - 1] = i.op[j];
5896 i.types[j - 1] = i.types[j];
5897 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5898 }
5899 }
5900 }
5901 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5902 {
91d6fa6a 5903 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5904 && (i.tm.opcode_modifier.vexsources
5905 == VEX3SOURCES));
c0f3af97
L		 5906
5907 /* Add the implicit xmm0 for instructions with VEX prefix
5908 and 3 sources. */
5909 for (j = i.operands; j > 0; j--)
5910 {
5911 i.op[j] = i.op[j - 1];
5912 i.types[j] = i.types[j - 1];
5913 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5914 }
5915 i.op[0].regs
5916 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5917 i.types[0] = regxmm;
c0f3af97
L		 5918 i.tm.operand_types[0] = regxmm;
5919
5920 i.operands += 2;
5921 i.reg_operands += 2;
5922 i.tm.operands += 2;
5923
91d6fa6a 5924 dupl++;
c0f3af97 5925 dest++;
91d6fa6a
NC		 5926 i.op[dupl] = i.op[dest];
5927 i.types[dupl] = i.types[dest];
5928 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5929 }
c0f3af97
L		 5930 else
5931 {
5932duplicate:
5933 i.operands++;
5934 i.reg_operands++;
5935 i.tm.operands++;
5936
91d6fa6a
NC		 5937 i.op[dupl] = i.op[dest];
5938 i.types[dupl] = i.types[dest];
5939 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5940 }
5941
5942 if (i.tm.opcode_modifier.immext)
5943 process_immext ();
5944 }
5945 else if (i.tm.opcode_modifier.firstxmm0)
5946 {
5947 unsigned int j;
5948
43234a1e 5949 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5950 gas_assert (i.reg_operands
7ab9ffdd 5951 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5952 || operand_type_equal (&i.types[0], &regymm)
5953 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5954 if (register_number (i.op[0].regs) != 0)
c0f3af97 5955 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5956
5957 for (j = 1; j < i.operands; j++)
5958 {
5959 i.op[j - 1] = i.op[j];
5960 i.types[j - 1] = i.types[j];
5961
5962 /* We need to adjust fields in i.tm since they are used by
5963 build_modrm_byte. */
5964 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5965 }
5966
e2ec9d29
L		 5967 i.operands--;
5968 i.reg_operands--;
e2ec9d29
L		 5969 i.tm.operands--;
5970 }
5971 else if (i.tm.opcode_modifier.regkludge)
5972 {
5973 /* The imul $imm, %reg instruction is converted into
5974 imul $imm, %reg, %reg, and the clr %reg instruction
5975 is converted into xor %reg, %reg. */
5976
5977 unsigned int first_reg_op;
5978
5979 if (operand_type_check (i.types[0], reg))
5980 first_reg_op = 0;
5981 else
5982 first_reg_op = 1;
5983 /* Pretend we saw the extra register operand. */
9c2799c2 5984 gas_assert (i.reg_operands == 1
7ab9ffdd 5985 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5986 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5987 i.types[first_reg_op + 1] = i.types[first_reg_op];
5988 i.operands++;
5989 i.reg_operands++;
29b0f896
AM		 5990 }
5991
40fb9820 5992 if (i.tm.opcode_modifier.shortform)
29b0f896 5993 {
40fb9820
L		 5994 if (i.types[0].bitfield.sreg2
5995 || i.types[0].bitfield.sreg3)
29b0f896 5996 {
4eed87de
AM		 5997 if (i.tm.base_opcode == POP_SEG_SHORT
5998 && i.op[0].regs->reg_num == 1)
29b0f896 5999 {
a87af027 6000 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 6001 return 0;
29b0f896 6002 }
4eed87de
AM		 6003 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6004 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 6005 i.rex |= REX_B;
4eed87de
AM		 6006 }
6007 else
6008 {
7ab9ffdd 6009 /* The register or float register operand is in operand
85f10a01 6010 0 or 1. */
40fb9820 6011 unsigned int op;
7ab9ffdd
L		 6012
6013 if (i.types[0].bitfield.floatreg
6014 || operand_type_check (i.types[0], reg))
6015 op = 0;
6016 else
6017 op = 1;
4eed87de
AM		 6018 /* Register goes in low 3 bits of opcode. */
6019 i.tm.base_opcode |= i.op[op].regs->reg_num;
6020 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 6021 i.rex |= REX_B;
40fb9820 6022 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 6023 {
4eed87de
AM		 6024 /* Warn about some common errors, but press on regardless.
6025 The first case can be generated by gcc (<= 2.8.1). */
6026 if (i.operands == 2)
6027 {
6028 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 6029 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 6030 register_prefix, i.op[!intel_syntax].regs->reg_name,
6031 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 6032 }
6033 else
6034 {
6035 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 6036 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6037 register_prefix, i.op[0].regs->reg_name);
4eed87de 6038 }
29b0f896
AM		 6039 }
6040 }
6041 }
40fb9820 6042 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 6043 {
6044 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 6045 must be put into the modrm byte). Now, we make the modrm and
6046 index base bytes based on all the info we've collected. */
29b0f896
AM		 6047
6048 default_seg = build_modrm_byte ();
6049 }
8a2ed489 6050 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 6051 {
6052 default_seg = &ds;
6053 }
40fb9820 6054 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 6055 {
6056 /* For the string instructions that allow a segment override
6057 on one of their operands, the default segment is ds. */
6058 default_seg = &ds;
6059 }
6060
75178d9d
L		 6061 if (i.tm.base_opcode == 0x8d /* lea */
6062 && i.seg[0]
6063 && !quiet_warnings)
30123838 6064 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 6065
6066 /* If a segment was explicitly specified, and the specified segment
6067 is not the default, use an opcode prefix to select it. If we
6068 never figured out what the default segment is, then default_seg
6069 will be zero at this point, and the specified segment prefix will
6070 always be used. */
29b0f896
AM		 6071 if ((i.seg[0]) && (i.seg[0] != default_seg))
6072 {
6073 if (!add_prefix (i.seg[0]->seg_prefix))
6074 return 0;
6075 }
6076 return 1;
6077}
6078
6079static const seg_entry *
e3bb37b5 6080build_modrm_byte (void)
29b0f896
AM		 6081{
6082 const seg_entry *default_seg = 0;
c0f3af97 6083 unsigned int source, dest;
8cd7925b 6084 int vex_3_sources;
c0f3af97
L		 6085
6086 /* The first operand of instructions with VEX prefix and 3 sources
6087 must be VEX_Imm4. */
8cd7925b 6088 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6089 if (vex_3_sources)
6090 {
91d6fa6a 6091 unsigned int nds, reg_slot;
4c2c6516 6092 expressionS *exp;
c0f3af97 6093
922d8de8 6094 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 6095 && i.tm.opcode_modifier.immext)
6096 {
6097 dest = i.operands - 2;
6098 gas_assert (dest == 3);
6099 }
922d8de8 6100 else
a683cc34 6101 dest = i.operands - 1;
c0f3af97 6102 nds = dest - 1;
922d8de8 6103
a683cc34
SP		 6104 /* There are 2 kinds of instructions:
6105 1. 5 operands: 4 register operands or 3 register operands
6106 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 6107 VexW0 or VexW1. The destination must be either XMM, YMM or
6108 ZMM register.
a683cc34
SP		 6109 2. 4 operands: 4 register operands or 3 register operands
6110 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 6111 gas_assert ((i.reg_operands == 4
a683cc34
SP		 6112 || (i.reg_operands == 3 && i.mem_operands == 1))
6113 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6114 && (i.tm.opcode_modifier.veximmext
6115 || (i.imm_operands == 1
6116 && i.types[0].bitfield.vec_imm4
6117 && (i.tm.opcode_modifier.vexw == VEXW0
6118 || i.tm.opcode_modifier.vexw == VEXW1)
6119 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 6120 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
6121 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 6122
6123 if (i.imm_operands == 0)
6124 {
6125 /* When there is no immediate operand, generate an 8bit
6126 immediate operand to encode the first operand. */
6127 exp = &im_expressions[i.imm_operands++];
6128 i.op[i.operands].imms = exp;
6129 i.types[i.operands] = imm8;
6130 i.operands++;
6131 /* If VexW1 is set, the first operand is the source and
6132 the second operand is encoded in the immediate operand. */
6133 if (i.tm.opcode_modifier.vexw == VEXW1)
6134 {
6135 source = 0;
6136 reg_slot = 1;
6137 }
6138 else
6139 {
6140 source = 1;
6141 reg_slot = 0;
6142 }
6143
6144 /* FMA swaps REG and NDS. */
6145 if (i.tm.cpu_flags.bitfield.cpufma)
6146 {
6147 unsigned int tmp;
6148 tmp = reg_slot;
6149 reg_slot = nds;
6150 nds = tmp;
6151 }
6152
24981e7b
L		 6153 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6154 &regxmm)
a683cc34 6155 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6156 &regymm)
6157 || operand_type_equal (&i.tm.operand_types[reg_slot],
6158 &regzmm));
a683cc34 6159 exp->X_op = O_constant;
4c692bc7 6160 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6161 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6162 }
922d8de8 6163 else
a683cc34
SP		 6164 {
6165 unsigned int imm_slot;
6166
6167 if (i.tm.opcode_modifier.vexw == VEXW0)
6168 {
6169 /* If VexW0 is set, the third operand is the source and
6170 the second operand is encoded in the immediate
6171 operand. */
6172 source = 2;
6173 reg_slot = 1;
6174 }
6175 else
6176 {
6177 /* VexW1 is set, the second operand is the source and
6178 the third operand is encoded in the immediate
6179 operand. */
6180 source = 1;
6181 reg_slot = 2;
6182 }
6183
6184 if (i.tm.opcode_modifier.immext)
6185 {
6186 /* When ImmExt is set, the immdiate byte is the last
6187 operand. */
6188 imm_slot = i.operands - 1;
6189 source--;
6190 reg_slot--;
6191 }
6192 else
6193 {
6194 imm_slot = 0;
6195
6196 /* Turn on Imm8 so that output_imm will generate it. */
6197 i.types[imm_slot].bitfield.imm8 = 1;
6198 }
6199
24981e7b
L		 6200 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6201 &regxmm)
6202 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6203 &regymm)
6204 || operand_type_equal (&i.tm.operand_types[reg_slot],
6205 &regzmm));
a683cc34 6206 i.op[imm_slot].imms->X_add_number
4c692bc7 6207 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6208 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6209 }
6210
6211 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6212 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6213 &regymm)
6214 || operand_type_equal (&i.tm.operand_types[nds],
6215 &regzmm));
dae39acc 6216 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6217 }
6218 else
6219 source = dest = 0;
29b0f896
AM		 6220
6221 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6222 implicit registers do not count. If there are 3 register
6223 operands, it must be a instruction with VexNDS. For a
6224 instruction with VexNDD, the destination register is encoded
6225 in VEX prefix. If there are 4 register operands, it must be
6226 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6227 if (i.mem_operands == 0
6228 && ((i.reg_operands == 2
2426c15f 6229 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6230 || (i.reg_operands == 3
2426c15f 6231 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6232 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6233 {
cab737b9
L		 6234 switch (i.operands)
6235 {
6236 case 2:
6237 source = 0;
6238 break;
6239 case 3:
c81128dc
L		 6240 /* When there are 3 operands, one of them may be immediate,
6241 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6242 the first operand must be shift count register (cl) or it
6243 is an instruction with VexNDS. */
9c2799c2 6244 gas_assert (i.imm_operands == 1
7ab9ffdd 6245 || (i.imm_operands == 0
2426c15f 6246 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6247 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6248 if (operand_type_check (i.types[0], imm)
6249 || i.types[0].bitfield.shiftcount)
6250 source = 1;
6251 else
6252 source = 0;
cab737b9
L		 6253 break;
6254 case 4:
368d64cc
L		 6255 /* When there are 4 operands, the first two must be 8bit
6256 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6257 one.
6258
6259 For instructions with VexNDS, if the first operand
6260 an imm8, the source operand is the 2nd one. If the last
6261 operand is imm8, the source operand is the first one. */
9c2799c2 6262 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6263 && i.types[0].bitfield.imm8
6264 && i.types[1].bitfield.imm8)
2426c15f 6265 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6266 && i.imm_operands == 1
6267 && (i.types[0].bitfield.imm8
43234a1e
L		 6268 || i.types[i.operands - 1].bitfield.imm8
6269 || i.rounding)));
9f2670f2
L		 6270 if (i.imm_operands == 2)
6271 source = 2;
6272 else
c0f3af97
L		 6273 {
6274 if (i.types[0].bitfield.imm8)
6275 source = 1;
6276 else
6277 source = 0;
6278 }
c0f3af97
L		 6279 break;
6280 case 5:
43234a1e
L		 6281 if (i.tm.opcode_modifier.evex)
6282 {
6283 /* For EVEX instructions, when there are 5 operands, the
6284 first one must be immediate operand. If the second one
6285 is immediate operand, the source operand is the 3th
6286 one. If the last one is immediate operand, the source
6287 operand is the 2nd one. */
6288 gas_assert (i.imm_operands == 2
6289 && i.tm.opcode_modifier.sae
6290 && operand_type_check (i.types[0], imm));
6291 if (operand_type_check (i.types[1], imm))
6292 source = 2;
6293 else if (operand_type_check (i.types[4], imm))
6294 source = 1;
6295 else
6296 abort ();
6297 }
cab737b9
L		 6298 break;
6299 default:
6300 abort ();
6301 }
6302
c0f3af97
L		 6303 if (!vex_3_sources)
6304 {
6305 dest = source + 1;
6306
43234a1e
L		 6307 /* RC/SAE operand could be between DEST and SRC. That happens
6308 when one operand is GPR and the other one is XMM/YMM/ZMM
6309 register. */
6310 if (i.rounding && i.rounding->operand == (int) dest)
6311 dest++;
6312
2426c15f 6313 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6314 {
43234a1e
L		 6315 /* For instructions with VexNDS, the register-only source
6316 operand must be 32/64bit integer, XMM, YMM or ZMM
6317 register. It is encoded in VEX prefix. We need to
6318 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6319
6320 i386_operand_type op;
6321 unsigned int vvvv;
6322
6323 /* Check register-only source operand when two source
6324 operands are swapped. */
6325 if (!i.tm.operand_types[source].bitfield.baseindex
6326 && i.tm.operand_types[dest].bitfield.baseindex)
6327 {
6328 vvvv = source;
6329 source = dest;
6330 }
6331 else
6332 vvvv = dest;
6333
6334 op = i.tm.operand_types[vvvv];
fa99fab2 6335 op.bitfield.regmem = 0;
c0f3af97 6336 if ((dest + 1) >= i.operands
ac4eb736
AM		 6337 || (!op.bitfield.reg32
6338 && op.bitfield.reg64
f12dc422 6339 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6340 && !operand_type_equal (&op, &regymm)
6341 && !operand_type_equal (&op, &regzmm)
6342 && !operand_type_equal (&op, &regmask)))
c0f3af97 6343 abort ();
f12dc422 6344 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6345 dest++;
6346 }
6347 }
29b0f896
AM		 6348
6349 i.rm.mode = 3;
6350 /* One of the register operands will be encoded in the i.tm.reg
6351 field, the other in the combined i.tm.mode and i.tm.regmem
6352 fields. If no form of this instruction supports a memory
6353 destination operand, then we assume the source operand may
6354 sometimes be a memory operand and so we need to store the
6355 destination in the i.rm.reg field. */
40fb9820
L		 6356 if (!i.tm.operand_types[dest].bitfield.regmem
6357 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6358 {
6359 i.rm.reg = i.op[dest].regs->reg_num;
6360 i.rm.regmem = i.op[source].regs->reg_num;
6361 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6362 i.rex |= REX_R;
43234a1e
L		 6363 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6364 i.vrex |= REX_R;
29b0f896 6365 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6366 i.rex |= REX_B;
43234a1e
L		 6367 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6368 i.vrex |= REX_B;
29b0f896
AM		 6369 }
6370 else
6371 {
6372 i.rm.reg = i.op[source].regs->reg_num;
6373 i.rm.regmem = i.op[dest].regs->reg_num;
6374 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6375 i.rex |= REX_B;
43234a1e
L		 6376 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6377 i.vrex |= REX_B;
29b0f896 6378 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6379 i.rex |= REX_R;
43234a1e
L		 6380 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6381 i.vrex |= REX_R;
29b0f896 6382 }
161a04f6 6383 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6384 {
40fb9820
L		 6385 if (!i.types[0].bitfield.control
6386 && !i.types[1].bitfield.control)
c4a530c5 6387 abort ();
161a04f6 6388 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6389 add_prefix (LOCK_PREFIX_OPCODE);
6390 }
29b0f896
AM		 6391 }
6392 else
6393 { /* If it's not 2 reg operands... */
c0f3af97
L		 6394 unsigned int mem;
6395
29b0f896
AM		 6396 if (i.mem_operands)
6397 {
6398 unsigned int fake_zero_displacement = 0;
99018f42 6399 unsigned int op;
4eed87de 6400
7ab9ffdd
L		 6401 for (op = 0; op < i.operands; op++)
6402 if (operand_type_check (i.types[op], anymem))
6403 break;
7ab9ffdd 6404 gas_assert (op < i.operands);
29b0f896 6405
6c30d220
L		 6406 if (i.tm.opcode_modifier.vecsib)
6407 {
6408 if (i.index_reg->reg_num == RegEiz
6409 || i.index_reg->reg_num == RegRiz)
6410 abort ();
6411
6412 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6413 if (!i.base_reg)
6414 {
6415 i.sib.base = NO_BASE_REGISTER;
6416 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6417 /* No Vec_Disp8 if there is no base. */
6418 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6419 i.types[op].bitfield.disp8 = 0;
6420 i.types[op].bitfield.disp16 = 0;
6421 i.types[op].bitfield.disp64 = 0;
6422 if (flag_code != CODE_64BIT)
6423 {
6424 /* Must be 32 bit */
6425 i.types[op].bitfield.disp32 = 1;
6426 i.types[op].bitfield.disp32s = 0;
6427 }
6428 else
6429 {
6430 i.types[op].bitfield.disp32 = 0;
6431 i.types[op].bitfield.disp32s = 1;
6432 }
6433 }
6434 i.sib.index = i.index_reg->reg_num;
6435 if ((i.index_reg->reg_flags & RegRex) != 0)
6436 i.rex |= REX_X;
43234a1e
L		 6437 if ((i.index_reg->reg_flags & RegVRex) != 0)
6438 i.vrex |= REX_X;
6c30d220
L		 6439 }
6440
29b0f896
AM		 6441 default_seg = &ds;
6442
6443 if (i.base_reg == 0)
6444 {
6445 i.rm.mode = 0;
6446 if (!i.disp_operands)
6c30d220
L		 6447 {
6448 fake_zero_displacement = 1;
6449 /* Instructions with VSIB byte need 32bit displacement
6450 if there is no base register. */
6451 if (i.tm.opcode_modifier.vecsib)
6452 i.types[op].bitfield.disp32 = 1;
6453 }
29b0f896
AM		 6454 if (i.index_reg == 0)
6455 {
6c30d220 6456 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6457 /* Operand is just <disp> */
20f0a1fc 6458 if (flag_code == CODE_64BIT)
29b0f896
AM		 6459 {
6460 /* 64bit mode overwrites the 32bit absolute
6461 addressing by RIP relative addressing and
6462 absolute addressing is encoded by one of the
6463 redundant SIB forms. */
6464 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6465 i.sib.base = NO_BASE_REGISTER;
6466 i.sib.index = NO_INDEX_REGISTER;
fc225355 6467 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6468 ? disp32s : disp32);
20f0a1fc 6469 }
fc225355
L		 6470 else if ((flag_code == CODE_16BIT)
6471 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6472 {
6473 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6474 i.types[op] = disp16;
20f0a1fc
NC		 6475 }
6476 else
6477 {
6478 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6479 i.types[op] = disp32;
29b0f896
AM		 6480 }
6481 }
6c30d220 6482 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6483 {
6c30d220 6484 /* !i.base_reg && i.index_reg */
db51cc60
L		 6485 if (i.index_reg->reg_num == RegEiz
6486 || i.index_reg->reg_num == RegRiz)
6487 i.sib.index = NO_INDEX_REGISTER;
6488 else
6489 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6490 i.sib.base = NO_BASE_REGISTER;
6491 i.sib.scale = i.log2_scale_factor;
6492 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6493 /* No Vec_Disp8 if there is no base. */
6494 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6495 i.types[op].bitfield.disp8 = 0;
6496 i.types[op].bitfield.disp16 = 0;
6497 i.types[op].bitfield.disp64 = 0;
29b0f896 6498 if (flag_code != CODE_64BIT)
40fb9820
L		 6499 {
6500 /* Must be 32 bit */
6501 i.types[op].bitfield.disp32 = 1;
6502 i.types[op].bitfield.disp32s = 0;
6503 }
29b0f896 6504 else
40fb9820
L		 6505 {
6506 i.types[op].bitfield.disp32 = 0;
6507 i.types[op].bitfield.disp32s = 1;
6508 }
29b0f896 6509 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6510 i.rex |= REX_X;
29b0f896
AM		 6511 }
6512 }
6513 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6514 else if (i.base_reg->reg_num == RegRip ||
6515 i.base_reg->reg_num == RegEip)
29b0f896 6516 {
6c30d220 6517 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6518 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6519 i.types[op].bitfield.disp8 = 0;
6520 i.types[op].bitfield.disp16 = 0;
6521 i.types[op].bitfield.disp32 = 0;
6522 i.types[op].bitfield.disp32s = 1;
6523 i.types[op].bitfield.disp64 = 0;
43234a1e 6524 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6525 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6526 if (! i.disp_operands)
6527 fake_zero_displacement = 1;
29b0f896 6528 }
40fb9820 6529 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6530 {
6c30d220 6531 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6532 switch (i.base_reg->reg_num)
6533 {
6534 case 3: /* (%bx) */
6535 if (i.index_reg == 0)
6536 i.rm.regmem = 7;
6537 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6538 i.rm.regmem = i.index_reg->reg_num - 6;
6539 break;
6540 case 5: /* (%bp) */
6541 default_seg = &ss;
6542 if (i.index_reg == 0)
6543 {
6544 i.rm.regmem = 6;
40fb9820 6545 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6546 {
6547 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6548 if (i.tm.operand_types[op].bitfield.vec_disp8)
6549 i.types[op].bitfield.vec_disp8 = 1;
6550 else
6551 i.types[op].bitfield.disp8 = 1;
252b5132 6552 fake_zero_displacement = 1;
29b0f896
AM		 6553 }
6554 }
6555 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6556 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6557 break;
6558 default: /* (%si) -> 4 or (%di) -> 5 */
6559 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6560 }
6561 i.rm.mode = mode_from_disp_size (i.types[op]);
6562 }
6563 else /* i.base_reg and 32/64 bit mode */
6564 {
6565 if (flag_code == CODE_64BIT
40fb9820
L		 6566 && operand_type_check (i.types[op], disp))
6567 {
6568 i386_operand_type temp;
0dfbf9d7 6569 operand_type_set (&temp, 0);
40fb9820 6570 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6571 temp.bitfield.vec_disp8
6572 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6573 i.types[op] = temp;
6574 if (i.prefix[ADDR_PREFIX] == 0)
6575 i.types[op].bitfield.disp32s = 1;
6576 else
6577 i.types[op].bitfield.disp32 = 1;
6578 }
20f0a1fc 6579
6c30d220
L		 6580 if (!i.tm.opcode_modifier.vecsib)
6581 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6582 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6583 i.rex |= REX_B;
29b0f896
AM		 6584 i.sib.base = i.base_reg->reg_num;
6585 /* x86-64 ignores REX prefix bit here to avoid decoder
6586 complications. */
848930b2
JB		 6587 if (!(i.base_reg->reg_flags & RegRex)
6588 && (i.base_reg->reg_num == EBP_REG_NUM
6589 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6590 default_seg = &ss;
848930b2 6591 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6592 {
848930b2 6593 fake_zero_displacement = 1;
43234a1e
L		 6594 if (i.tm.operand_types [op].bitfield.vec_disp8)
6595 i.types[op].bitfield.vec_disp8 = 1;
6596 else
6597 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6598 }
6599 i.sib.scale = i.log2_scale_factor;
6600 if (i.index_reg == 0)
6601 {
6c30d220 6602 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6603 /* <disp>(%esp) becomes two byte modrm with no index
6604 register. We've already stored the code for esp
6605 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6606 Any base register besides %esp will not use the
6607 extra modrm byte. */
6608 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6609 }
6c30d220 6610 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6611 {
db51cc60
L		 6612 if (i.index_reg->reg_num == RegEiz
6613 || i.index_reg->reg_num == RegRiz)
6614 i.sib.index = NO_INDEX_REGISTER;
6615 else
6616 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6617 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6618 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6619 i.rex |= REX_X;
29b0f896 6620 }
67a4f2b7
AO		 6621
6622 if (i.disp_operands
6623 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6624 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6625 i.rm.mode = 0;
6626 else
a501d77e
L		 6627 {
6628 if (!fake_zero_displacement
6629 && !i.disp_operands
6630 && i.disp_encoding)
6631 {
6632 fake_zero_displacement = 1;
6633 if (i.disp_encoding == disp_encoding_8bit)
6634 i.types[op].bitfield.disp8 = 1;
6635 else
6636 i.types[op].bitfield.disp32 = 1;
6637 }
6638 i.rm.mode = mode_from_disp_size (i.types[op]);
6639 }
29b0f896 6640 }
252b5132 6641
29b0f896
AM		 6642 if (fake_zero_displacement)
6643 {
6644 /* Fakes a zero displacement assuming that i.types[op]
6645 holds the correct displacement size. */
6646 expressionS *exp;
6647
9c2799c2 6648 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6649 exp = &disp_expressions[i.disp_operands++];
6650 i.op[op].disps = exp;
6651 exp->X_op = O_constant;
6652 exp->X_add_number = 0;
6653 exp->X_add_symbol = (symbolS *) 0;
6654 exp->X_op_symbol = (symbolS *) 0;
6655 }
c0f3af97
L		 6656
6657 mem = op;
29b0f896 6658 }
c0f3af97
L		 6659 else
6660 mem = ~0;
252b5132 6661
8c43a48b 6662 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6663 {
6664 if (operand_type_check (i.types[0], imm))
6665 i.vex.register_specifier = NULL;
6666 else
6667 {
6668 /* VEX.vvvv encodes one of the sources when the first
6669 operand is not an immediate. */
1ef99a7b 6670 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6671 i.vex.register_specifier = i.op[0].regs;
6672 else
6673 i.vex.register_specifier = i.op[1].regs;
6674 }
6675
6676 /* Destination is a XMM register encoded in the ModRM.reg
6677 and VEX.R bit. */
6678 i.rm.reg = i.op[2].regs->reg_num;
6679 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6680 i.rex |= REX_R;
6681
6682 /* ModRM.rm and VEX.B encodes the other source. */
6683 if (!i.mem_operands)
6684 {
6685 i.rm.mode = 3;
6686
1ef99a7b 6687 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6688 i.rm.regmem = i.op[1].regs->reg_num;
6689 else
6690 i.rm.regmem = i.op[0].regs->reg_num;
6691
6692 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6693 i.rex |= REX_B;
6694 }
6695 }
2426c15f 6696 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6697 {
6698 i.vex.register_specifier = i.op[2].regs;
6699 if (!i.mem_operands)
6700 {
6701 i.rm.mode = 3;
6702 i.rm.regmem = i.op[1].regs->reg_num;
6703 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6704 i.rex |= REX_B;
6705 }
6706 }
29b0f896
AM		 6707 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6708 (if any) based on i.tm.extension_opcode. Again, we must be
6709 careful to make sure that segment/control/debug/test/MMX
6710 registers are coded into the i.rm.reg field. */
f88c9eb0 6711 else if (i.reg_operands)
29b0f896 6712 {
99018f42 6713 unsigned int op;
7ab9ffdd
L		 6714 unsigned int vex_reg = ~0;
6715
6716 for (op = 0; op < i.operands; op++)
6717 if (i.types[op].bitfield.reg8
6718 || i.types[op].bitfield.reg16
6719 || i.types[op].bitfield.reg32
6720 || i.types[op].bitfield.reg64
6721 || i.types[op].bitfield.regmmx
6722 || i.types[op].bitfield.regxmm
6723 || i.types[op].bitfield.regymm
7e8b059b 6724 || i.types[op].bitfield.regbnd
43234a1e
L		 6725 || i.types[op].bitfield.regzmm
6726 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6727 || i.types[op].bitfield.sreg2
6728 || i.types[op].bitfield.sreg3
6729 || i.types[op].bitfield.control
6730 || i.types[op].bitfield.debug
6731 || i.types[op].bitfield.test)
6732 break;
c0209578 6733
7ab9ffdd
L		 6734 if (vex_3_sources)
6735 op = dest;
2426c15f 6736 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6737 {
6738 /* For instructions with VexNDS, the register-only
6739 source operand is encoded in VEX prefix. */
6740 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6741
7ab9ffdd 6742 if (op > mem)
c0f3af97 6743 {
7ab9ffdd
L		 6744 vex_reg = op++;
6745 gas_assert (op < i.operands);
c0f3af97
L		 6746 }
6747 else
c0f3af97 6748 {
f12dc422
L		 6749 /* Check register-only source operand when two source
6750 operands are swapped. */
6751 if (!i.tm.operand_types[op].bitfield.baseindex
6752 && i.tm.operand_types[op + 1].bitfield.baseindex)
6753 {
6754 vex_reg = op;
6755 op += 2;
6756 gas_assert (mem == (vex_reg + 1)
6757 && op < i.operands);
6758 }
6759 else
6760 {
6761 vex_reg = op + 1;
6762 gas_assert (vex_reg < i.operands);
6763 }
c0f3af97 6764 }
7ab9ffdd 6765 }
2426c15f 6766 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6767 {
f12dc422 6768 /* For instructions with VexNDD, the register destination
7ab9ffdd 6769 is encoded in VEX prefix. */
f12dc422
L		 6770 if (i.mem_operands == 0)
6771 {
6772 /* There is no memory operand. */
6773 gas_assert ((op + 2) == i.operands);
6774 vex_reg = op + 1;
6775 }
6776 else
8d63c93e 6777 {
f12dc422
L		 6778 /* There are only 2 operands. */
6779 gas_assert (op < 2 && i.operands == 2);
6780 vex_reg = 1;
6781 }
7ab9ffdd
L		 6782 }
6783 else
6784 gas_assert (op < i.operands);
99018f42 6785
7ab9ffdd
L		 6786 if (vex_reg != (unsigned int) ~0)
6787 {
f12dc422 6788 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6789
f12dc422
L		 6790 if (type->bitfield.reg32 != 1
6791 && type->bitfield.reg64 != 1
6792 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6793 && !operand_type_equal (type, &regymm)
6794 && !operand_type_equal (type, &regzmm)
6795 && !operand_type_equal (type, &regmask))
7ab9ffdd 6796 abort ();
f88c9eb0 6797
7ab9ffdd
L		 6798 i.vex.register_specifier = i.op[vex_reg].regs;
6799 }
6800
1b9f0c97
L		 6801 /* Don't set OP operand twice. */
6802 if (vex_reg != op)
7ab9ffdd 6803 {
1b9f0c97
L		 6804 /* If there is an extension opcode to put here, the
6805 register number must be put into the regmem field. */
6806 if (i.tm.extension_opcode != None)
6807 {
6808 i.rm.regmem = i.op[op].regs->reg_num;
6809 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6810 i.rex |= REX_B;
43234a1e
L		 6811 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6812 i.vrex |= REX_B;
1b9f0c97
L		 6813 }
6814 else
6815 {
6816 i.rm.reg = i.op[op].regs->reg_num;
6817 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6818 i.rex |= REX_R;
43234a1e
L		 6819 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6820 i.vrex |= REX_R;
1b9f0c97 6821 }
7ab9ffdd 6822 }
252b5132 6823
29b0f896
AM		 6824 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6825 must set it to 3 to indicate this is a register operand
6826 in the regmem field. */
6827 if (!i.mem_operands)
6828 i.rm.mode = 3;
6829 }
252b5132 6830
29b0f896 6831 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6832 if (i.tm.extension_opcode != None)
29b0f896
AM		 6833 i.rm.reg = i.tm.extension_opcode;
6834 }
6835 return default_seg;
6836}
252b5132 6837
29b0f896 6838static void
e3bb37b5 6839output_branch (void)
29b0f896
AM		 6840{
6841 char *p;
f8a5c266 6842 int size;
29b0f896
AM		 6843 int code16;
6844 int prefix;
6845 relax_substateT subtype;
6846 symbolS *sym;
6847 offsetT off;
6848
f8a5c266 6849 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6850 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6851
6852 prefix = 0;
6853 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6854 {
29b0f896
AM		 6855 prefix = 1;
6856 i.prefixes -= 1;
6857 code16 ^= CODE16;
252b5132 6858 }
29b0f896
AM		 6859 /* Pentium4 branch hints. */
6860 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6861 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6862 {
29b0f896
AM		 6863 prefix++;
6864 i.prefixes--;
6865 }
6866 if (i.prefix[REX_PREFIX] != 0)
6867 {
6868 prefix++;
6869 i.prefixes--;
2f66722d
AM		 6870 }
6871
7e8b059b
L		 6872 /* BND prefixed jump. */
6873 if (i.prefix[BND_PREFIX] != 0)
6874 {
6875 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6876 i.prefixes -= 1;
6877 }
6878
29b0f896
AM		 6879 if (i.prefixes != 0 && !intel_syntax)
6880 as_warn (_("skipping prefixes on this instruction"));
6881
6882 /* It's always a symbol; End frag & setup for relax.
6883 Make sure there is enough room in this frag for the largest
6884 instruction we may generate in md_convert_frag. This is 2
6885 bytes for the opcode and room for the prefix and largest
6886 displacement. */
6887 frag_grow (prefix + 2 + 4);
6888 /* Prefix and 1 opcode byte go in fr_fix. */
6889 p = frag_more (prefix + 1);
6890 if (i.prefix[DATA_PREFIX] != 0)
6891 *p++ = DATA_PREFIX_OPCODE;
6892 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6893 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6894 *p++ = i.prefix[SEG_PREFIX];
6895 if (i.prefix[REX_PREFIX] != 0)
6896 *p++ = i.prefix[REX_PREFIX];
6897 *p = i.tm.base_opcode;
6898
6899 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6900 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6901 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6902 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6903 else
f8a5c266 6904 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6905 subtype |= code16;
3e73aa7c 6906
29b0f896
AM		 6907 sym = i.op[0].disps->X_add_symbol;
6908 off = i.op[0].disps->X_add_number;
3e73aa7c 6909
29b0f896
AM		 6910 if (i.op[0].disps->X_op != O_constant
6911 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6912 {
29b0f896
AM		 6913 /* Handle complex expressions. */
6914 sym = make_expr_symbol (i.op[0].disps);
6915 off = 0;
6916 }
3e73aa7c 6917
29b0f896
AM		 6918 /* 1 possible extra opcode + 4 byte displacement go in var part.
6919 Pass reloc in fr_var. */
d258b828 6920 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 6921}
3e73aa7c 6922
29b0f896 6923static void
e3bb37b5 6924output_jump (void)
29b0f896
AM		 6925{
6926 char *p;
6927 int size;
3e02c1cc 6928 fixS *fixP;
29b0f896 6929
40fb9820 6930 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6931 {
6932 /* This is a loop or jecxz type instruction. */
6933 size = 1;
6934 if (i.prefix[ADDR_PREFIX] != 0)
6935 {
6936 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6937 i.prefixes -= 1;
6938 }
6939 /* Pentium4 branch hints. */
6940 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6941 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6942 {
6943 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6944 i.prefixes--;
3e73aa7c
JH		 6945 }
6946 }
29b0f896
AM		 6947 else
6948 {
6949 int code16;
3e73aa7c 6950
29b0f896
AM		 6951 code16 = 0;
6952 if (flag_code == CODE_16BIT)
6953 code16 = CODE16;
3e73aa7c 6954
29b0f896
AM		 6955 if (i.prefix[DATA_PREFIX] != 0)
6956 {
6957 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6958 i.prefixes -= 1;
6959 code16 ^= CODE16;
6960 }
252b5132 6961
29b0f896
AM		 6962 size = 4;
6963 if (code16)
6964 size = 2;
6965 }
9fcc94b6 6966
29b0f896
AM		 6967 if (i.prefix[REX_PREFIX] != 0)
6968 {
6969 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6970 i.prefixes -= 1;
6971 }
252b5132 6972
7e8b059b
L		 6973 /* BND prefixed jump. */
6974 if (i.prefix[BND_PREFIX] != 0)
6975 {
6976 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6977 i.prefixes -= 1;
6978 }
6979
29b0f896
AM		 6980 if (i.prefixes != 0 && !intel_syntax)
6981 as_warn (_("skipping prefixes on this instruction"));
e0890092 6982
42164a71
L		 6983 p = frag_more (i.tm.opcode_length + size);
6984 switch (i.tm.opcode_length)
6985 {
6986 case 2:
6987 *p++ = i.tm.base_opcode >> 8;
1a0670f3 6988 /* Fall through. */
42164a71
L		 6989 case 1:
6990 *p++ = i.tm.base_opcode;
6991 break;
6992 default:
6993 abort ();
6994 }
e0890092 6995
3e02c1cc 6996 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6997 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 6998
6999 /* All jumps handled here are signed, but don't use a signed limit
7000 check for 32 and 16 bit jumps as we want to allow wrap around at
7001 4G and 64k respectively. */
7002 if (size == 1)
7003 fixP->fx_signed = 1;
29b0f896 7004}
e0890092 7005
29b0f896 7006static void
e3bb37b5 7007output_interseg_jump (void)
29b0f896
AM		 7008{
7009 char *p;
7010 int size;
7011 int prefix;
7012 int code16;
252b5132 7013
29b0f896
AM		 7014 code16 = 0;
7015 if (flag_code == CODE_16BIT)
7016 code16 = CODE16;
a217f122 7017
29b0f896
AM		 7018 prefix = 0;
7019 if (i.prefix[DATA_PREFIX] != 0)
7020 {
7021 prefix = 1;
7022 i.prefixes -= 1;
7023 code16 ^= CODE16;
7024 }
7025 if (i.prefix[REX_PREFIX] != 0)
7026 {
7027 prefix++;
7028 i.prefixes -= 1;
7029 }
252b5132 7030
29b0f896
AM		 7031 size = 4;
7032 if (code16)
7033 size = 2;
252b5132 7034
29b0f896
AM		 7035 if (i.prefixes != 0 && !intel_syntax)
7036 as_warn (_("skipping prefixes on this instruction"));
252b5132 7037
29b0f896
AM		 7038 /* 1 opcode; 2 segment; offset */
7039 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 7040
29b0f896
AM		 7041 if (i.prefix[DATA_PREFIX] != 0)
7042 *p++ = DATA_PREFIX_OPCODE;
252b5132 7043
29b0f896
AM		 7044 if (i.prefix[REX_PREFIX] != 0)
7045 *p++ = i.prefix[REX_PREFIX];
252b5132 7046
29b0f896
AM		 7047 *p++ = i.tm.base_opcode;
7048 if (i.op[1].imms->X_op == O_constant)
7049 {
7050 offsetT n = i.op[1].imms->X_add_number;
252b5132 7051
29b0f896
AM		 7052 if (size == 2
7053 && !fits_in_unsigned_word (n)
7054 && !fits_in_signed_word (n))
7055 {
7056 as_bad (_("16-bit jump out of range"));
7057 return;
7058 }
7059 md_number_to_chars (p, n, size);
7060 }
7061 else
7062 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7063 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 7064 if (i.op[0].imms->X_op != O_constant)
7065 as_bad (_("can't handle non absolute segment in `%s'"),
7066 i.tm.name);
7067 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7068}
a217f122 7069
29b0f896 7070static void
e3bb37b5 7071output_insn (void)
29b0f896 7072{
2bbd9c25
JJ		 7073 fragS *insn_start_frag;
7074 offsetT insn_start_off;
7075
29b0f896
AM		 7076 /* Tie dwarf2 debug info to the address at the start of the insn.
7077 We can't do this after the insn has been output as the current
7078 frag may have been closed off. eg. by frag_var. */
7079 dwarf2_emit_insn (0);
7080
2bbd9c25
JJ		 7081 insn_start_frag = frag_now;
7082 insn_start_off = frag_now_fix ();
7083
29b0f896 7084 /* Output jumps. */
40fb9820 7085 if (i.tm.opcode_modifier.jump)
29b0f896 7086 output_branch ();
40fb9820
L		 7087 else if (i.tm.opcode_modifier.jumpbyte
7088 || i.tm.opcode_modifier.jumpdword)
29b0f896 7089 output_jump ();
40fb9820 7090 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7091 output_interseg_jump ();
7092 else
7093 {
7094 /* Output normal instructions here. */
7095 char *p;
7096 unsigned char *q;
47465058 7097 unsigned int j;
331d2d0d 7098 unsigned int prefix;
4dffcebc 7099
e4e00185
AS		 7100 if (avoid_fence
7101 && i.tm.base_opcode == 0xfae
7102 && i.operands == 1
7103 && i.imm_operands == 1
7104 && (i.op[0].imms->X_add_number == 0xe8
7105 || i.op[0].imms->X_add_number == 0xf0
7106 || i.op[0].imms->X_add_number == 0xf8))
7107 {
7108 /* Encode lfence, mfence, and sfence as
7109 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7110 offsetT val = 0x240483f0ULL;
7111 p = frag_more (5);
7112 md_number_to_chars (p, val, 5);
7113 return;
7114 }
7115
d022bddd
IT		 7116 /* Some processors fail on LOCK prefix. This options makes
7117 assembler ignore LOCK prefix and serves as a workaround. */
7118 if (omit_lock_prefix)
7119 {
7120 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7121 return;
7122 i.prefix[LOCK_PREFIX] = 0;
7123 }
7124
43234a1e
L		 7125 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7126 don't need the explicit prefix. */
7127 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7128 {
c0f3af97 7129 switch (i.tm.opcode_length)
bc4bd9ab 7130 {
c0f3af97
L		 7131 case 3:
7132 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7133 {
c0f3af97
L		 7134 prefix = (i.tm.base_opcode >> 24) & 0xff;
7135 goto check_prefix;
7136 }
7137 break;
7138 case 2:
7139 if ((i.tm.base_opcode & 0xff0000) != 0)
7140 {
7141 prefix = (i.tm.base_opcode >> 16) & 0xff;
7142 if (i.tm.cpu_flags.bitfield.cpupadlock)
7143 {
4dffcebc 7144check_prefix:
c0f3af97 7145 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 7146 || (i.prefix[REP_PREFIX]
c0f3af97
L		 7147 != REPE_PREFIX_OPCODE))
7148 add_prefix (prefix);
7149 }
7150 else
4dffcebc
L		 7151 add_prefix (prefix);
7152 }
c0f3af97
L		 7153 break;
7154 case 1:
7155 break;
7156 default:
7157 abort ();
bc4bd9ab 7158 }
c0f3af97 7159
6d19a37a 7160#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7161 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7162 R_X86_64_GOTTPOFF relocation so that linker can safely
7163 perform IE->LE optimization. */
7164 if (x86_elf_abi == X86_64_X32_ABI
7165 && i.operands == 2
7166 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7167 && i.prefix[REX_PREFIX] == 0)
7168 add_prefix (REX_OPCODE);
6d19a37a 7169#endif
cf61b747 7170
c0f3af97
L		 7171 /* The prefix bytes. */
7172 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7173 if (*q)
7174 FRAG_APPEND_1_CHAR (*q);
0f10071e 7175 }
ae5c1c7b 7176 else
c0f3af97
L		 7177 {
7178 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7179 if (*q)
7180 switch (j)
7181 {
7182 case REX_PREFIX:
7183 /* REX byte is encoded in VEX prefix. */
7184 break;
7185 case SEG_PREFIX:
7186 case ADDR_PREFIX:
7187 FRAG_APPEND_1_CHAR (*q);
7188 break;
7189 default:
7190 /* There should be no other prefixes for instructions
7191 with VEX prefix. */
7192 abort ();
7193 }
7194
43234a1e
L		 7195 /* For EVEX instructions i.vrex should become 0 after
7196 build_evex_prefix. For VEX instructions upper 16 registers
7197 aren't available, so VREX should be 0. */
7198 if (i.vrex)
7199 abort ();
c0f3af97
L		 7200 /* Now the VEX prefix. */
7201 p = frag_more (i.vex.length);
7202 for (j = 0; j < i.vex.length; j++)
7203 p[j] = i.vex.bytes[j];
7204 }
252b5132 7205
29b0f896 7206 /* Now the opcode; be careful about word order here! */
4dffcebc 7207 if (i.tm.opcode_length == 1)
29b0f896
AM		 7208 {
7209 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7210 }
7211 else
7212 {
4dffcebc 7213 switch (i.tm.opcode_length)
331d2d0d 7214 {
43234a1e
L		 7215 case 4:
7216 p = frag_more (4);
7217 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7218 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7219 break;
4dffcebc 7220 case 3:
331d2d0d
L		 7221 p = frag_more (3);
7222 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7223 break;
7224 case 2:
7225 p = frag_more (2);
7226 break;
7227 default:
7228 abort ();
7229 break;
331d2d0d 7230 }
0f10071e 7231
29b0f896
AM		 7232 /* Put out high byte first: can't use md_number_to_chars! */
7233 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7234 *p = i.tm.base_opcode & 0xff;
7235 }
3e73aa7c 7236
29b0f896 7237 /* Now the modrm byte and sib byte (if present). */
40fb9820 7238 if (i.tm.opcode_modifier.modrm)
29b0f896 7239 {
4a3523fa
L		 7240 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7241 | i.rm.reg << 3
7242 | i.rm.mode << 6));
29b0f896
AM		 7243 /* If i.rm.regmem == ESP (4)
7244 && i.rm.mode != (Register mode)
7245 && not 16 bit
7246 ==> need second modrm byte. */
7247 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7248 && i.rm.mode != 3
40fb9820 7249 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7250 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7251 | i.sib.index << 3
7252 | i.sib.scale << 6));
29b0f896 7253 }
3e73aa7c 7254
29b0f896 7255 if (i.disp_operands)
2bbd9c25 7256 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7257
29b0f896 7258 if (i.imm_operands)
2bbd9c25 7259 output_imm (insn_start_frag, insn_start_off);
29b0f896 7260 }
252b5132 7261
29b0f896
AM		 7262#ifdef DEBUG386
7263 if (flag_debug)
7264 {
7b81dfbb 7265 pi ("" /*line*/, &i);
29b0f896
AM		 7266 }
7267#endif /* DEBUG386 */
7268}
252b5132 7269
e205caa7
L		 7270/* Return the size of the displacement operand N. */
7271
7272static int
7273disp_size (unsigned int n)
7274{
7275 int size = 4;
43234a1e
L		 7276
7277 /* Vec_Disp8 has to be 8bit. */
7278 if (i.types[n].bitfield.vec_disp8)
7279 size = 1;
7280 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7281 size = 8;
7282 else if (i.types[n].bitfield.disp8)
7283 size = 1;
7284 else if (i.types[n].bitfield.disp16)
7285 size = 2;
e205caa7
L		 7286 return size;
7287}
7288
7289/* Return the size of the immediate operand N. */
7290
7291static int
7292imm_size (unsigned int n)
7293{
7294 int size = 4;
40fb9820
L		 7295 if (i.types[n].bitfield.imm64)
7296 size = 8;
7297 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7298 size = 1;
7299 else if (i.types[n].bitfield.imm16)
7300 size = 2;
e205caa7
L		 7301 return size;
7302}
7303
29b0f896 7304static void
64e74474 7305output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7306{
7307 char *p;
7308 unsigned int n;
252b5132 7309
29b0f896
AM		 7310 for (n = 0; n < i.operands; n++)
7311 {
43234a1e
L		 7312 if (i.types[n].bitfield.vec_disp8
7313 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7314 {
7315 if (i.op[n].disps->X_op == O_constant)
7316 {
e205caa7 7317 int size = disp_size (n);
43234a1e 7318 offsetT val = i.op[n].disps->X_add_number;
252b5132 7319
43234a1e
L		 7320 if (i.types[n].bitfield.vec_disp8)
7321 val >>= i.memshift;
7322 val = offset_in_range (val, size);
29b0f896
AM		 7323 p = frag_more (size);
7324 md_number_to_chars (p, val, size);
7325 }
7326 else
7327 {
f86103b7 7328 enum bfd_reloc_code_real reloc_type;
e205caa7 7329 int size = disp_size (n);
40fb9820 7330 int sign = i.types[n].bitfield.disp32s;
29b0f896 7331 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7332 fixS *fixP;
29b0f896 7333
e205caa7 7334 /* We can't have 8 bit displacement here. */
9c2799c2 7335 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7336
29b0f896
AM		 7337 /* The PC relative address is computed relative
7338 to the instruction boundary, so in case immediate
7339 fields follows, we need to adjust the value. */
7340 if (pcrel && i.imm_operands)
7341 {
29b0f896 7342 unsigned int n1;
e205caa7 7343 int sz = 0;
252b5132 7344
29b0f896 7345 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7346 if (operand_type_check (i.types[n1], imm))
252b5132 7347 {
e205caa7
L		 7348 /* Only one immediate is allowed for PC
7349 relative address. */
9c2799c2 7350 gas_assert (sz == 0);
e205caa7
L		 7351 sz = imm_size (n1);
7352 i.op[n].disps->X_add_number -= sz;
252b5132 7353 }
29b0f896 7354 /* We should find the immediate. */
9c2799c2 7355 gas_assert (sz != 0);
29b0f896 7356 }
520dc8e8 7357
29b0f896 7358 p = frag_more (size);
d258b828 7359 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7360 if (GOT_symbol
2bbd9c25 7361 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7362 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7363 || reloc_type == BFD_RELOC_X86_64_32S
7364 || (reloc_type == BFD_RELOC_64
7365 && object_64bit))
d6ab8113
JB		 7366 && (i.op[n].disps->X_op == O_symbol
7367 || (i.op[n].disps->X_op == O_add
7368 && ((symbol_get_value_expression
7369 (i.op[n].disps->X_op_symbol)->X_op)
7370 == O_subtract))))
7371 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7372 {
7373 offsetT add;
7374
7375 if (insn_start_frag == frag_now)
7376 add = (p - frag_now->fr_literal) - insn_start_off;
7377 else
7378 {
7379 fragS *fr;
7380
7381 add = insn_start_frag->fr_fix - insn_start_off;
7382 for (fr = insn_start_frag->fr_next;
7383 fr && fr != frag_now; fr = fr->fr_next)
7384 add += fr->fr_fix;
7385 add += p - frag_now->fr_literal;
7386 }
7387
4fa24527 7388 if (!object_64bit)
7b81dfbb
AJ		 7389 {
7390 reloc_type = BFD_RELOC_386_GOTPC;
7391 i.op[n].imms->X_add_number += add;
7392 }
7393 else if (reloc_type == BFD_RELOC_64)
7394 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7395 else
7b81dfbb
AJ		 7396 /* Don't do the adjustment for x86-64, as there
7397 the pcrel addressing is relative to the _next_
7398 insn, and that is taken care of in other code. */
d6ab8113 7399 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7400 }
02a86693
L		 7401 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7402 size, i.op[n].disps, pcrel,
7403 reloc_type);
7404 /* Check for "call/jmp *mem", "mov mem, %reg",
7405 "test %reg, mem" and "binop mem, %reg" where binop
7406 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 7407 instructions. Always generate R_386_GOT32X for
7408 "sym*GOT" operand in 32-bit mode. */
7409 if ((generate_relax_relocations
7410 || (!object_64bit
7411 && i.rm.mode == 0
7412 && i.rm.regmem == 5))
7413 && (i.rm.mode == 2
7414 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 7415 && ((i.operands == 1
7416 && i.tm.base_opcode == 0xff
7417 && (i.rm.reg == 2 || i.rm.reg == 4))
7418 || (i.operands == 2
7419 && (i.tm.base_opcode == 0x8b
7420 || i.tm.base_opcode == 0x85
7421 || (i.tm.base_opcode & 0xc7) == 0x03))))
7422 {
7423 if (object_64bit)
7424 {
7425 fixP->fx_tcbit = i.rex != 0;
7426 if (i.base_reg
7427 && (i.base_reg->reg_num == RegRip
7428 || i.base_reg->reg_num == RegEip))
7429 fixP->fx_tcbit2 = 1;
7430 }
7431 else
7432 fixP->fx_tcbit2 = 1;
7433 }
29b0f896
AM		 7434 }
7435 }
7436 }
7437}
252b5132 7438
29b0f896 7439static void
64e74474 7440output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7441{
7442 char *p;
7443 unsigned int n;
252b5132 7444
29b0f896
AM		 7445 for (n = 0; n < i.operands; n++)
7446 {
43234a1e
L		 7447 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7448 if (i.rounding && (int) n == i.rounding->operand)
7449 continue;
7450
40fb9820 7451 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7452 {
7453 if (i.op[n].imms->X_op == O_constant)
7454 {
e205caa7 7455 int size = imm_size (n);
29b0f896 7456 offsetT val;
b4cac588 7457
29b0f896
AM		 7458 val = offset_in_range (i.op[n].imms->X_add_number,
7459 size);
7460 p = frag_more (size);
7461 md_number_to_chars (p, val, size);
7462 }
7463 else
7464 {
7465 /* Not absolute_section.
7466 Need a 32-bit fixup (don't support 8bit
7467 non-absolute imms). Try to support other
7468 sizes ... */
f86103b7 7469 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7470 int size = imm_size (n);
7471 int sign;
29b0f896 7472
40fb9820 7473 if (i.types[n].bitfield.imm32s
a7d61044 7474 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7475 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7476 sign = 1;
e205caa7
L		 7477 else
7478 sign = 0;
520dc8e8 7479
29b0f896 7480 p = frag_more (size);
d258b828 7481 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7482
2bbd9c25
JJ		 7483 /* This is tough to explain. We end up with this one if we
7484 * have operands that look like
7485 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7486 * obtain the absolute address of the GOT, and it is strongly
7487 * preferable from a performance point of view to avoid using
7488 * a runtime relocation for this. The actual sequence of
7489 * instructions often look something like:
7490 *
7491 * call .L66
7492 * .L66:
7493 * popl %ebx
7494 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7495 *
7496 * The call and pop essentially return the absolute address
7497 * of the label .L66 and store it in %ebx. The linker itself
7498 * will ultimately change the first operand of the addl so
7499 * that %ebx points to the GOT, but to keep things simple, the
7500 * .o file must have this operand set so that it generates not
7501 * the absolute address of .L66, but the absolute address of
7502 * itself. This allows the linker itself simply treat a GOTPC
7503 * relocation as asking for a pcrel offset to the GOT to be
7504 * added in, and the addend of the relocation is stored in the
7505 * operand field for the instruction itself.
7506 *
7507 * Our job here is to fix the operand so that it would add
7508 * the correct offset so that %ebx would point to itself. The
7509 * thing that is tricky is that .-.L66 will point to the
7510 * beginning of the instruction, so we need to further modify
7511 * the operand so that it will point to itself. There are
7512 * other cases where you have something like:
7513 *
7514 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7515 *
7516 * and here no correction would be required. Internally in
7517 * the assembler we treat operands of this form as not being
7518 * pcrel since the '.' is explicitly mentioned, and I wonder
7519 * whether it would simplify matters to do it this way. Who
7520 * knows. In earlier versions of the PIC patches, the
7521 * pcrel_adjust field was used to store the correction, but
7522 * since the expression is not pcrel, I felt it would be
7523 * confusing to do it this way. */
7524
d6ab8113 7525 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7526 || reloc_type == BFD_RELOC_X86_64_32S
7527 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7528 && GOT_symbol
7529 && GOT_symbol == i.op[n].imms->X_add_symbol
7530 && (i.op[n].imms->X_op == O_symbol
7531 || (i.op[n].imms->X_op == O_add
7532 && ((symbol_get_value_expression
7533 (i.op[n].imms->X_op_symbol)->X_op)
7534 == O_subtract))))
7535 {
2bbd9c25
JJ		 7536 offsetT add;
7537
7538 if (insn_start_frag == frag_now)
7539 add = (p - frag_now->fr_literal) - insn_start_off;
7540 else
7541 {
7542 fragS *fr;
7543
7544 add = insn_start_frag->fr_fix - insn_start_off;
7545 for (fr = insn_start_frag->fr_next;
7546 fr && fr != frag_now; fr = fr->fr_next)
7547 add += fr->fr_fix;
7548 add += p - frag_now->fr_literal;
7549 }
7550
4fa24527 7551 if (!object_64bit)
d6ab8113 7552 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7553 else if (size == 4)
d6ab8113 7554 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7555 else if (size == 8)
7556 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7557 i.op[n].imms->X_add_number += add;
29b0f896 7558 }
29b0f896
AM		 7559 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7560 i.op[n].imms, 0, reloc_type);
7561 }
7562 }
7563 }
252b5132
RH		 7564}
7565\f
d182319b
JB		 7566/* x86_cons_fix_new is called via the expression parsing code when a
7567 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7568static int cons_sign = -1;
7569
7570void
e3bb37b5 7571x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7572 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7573{
d258b828 7574 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7575
7576#ifdef TE_PE
7577 if (exp->X_op == O_secrel)
7578 {
7579 exp->X_op = O_symbol;
7580 r = BFD_RELOC_32_SECREL;
7581 }
7582#endif
7583
7584 fix_new_exp (frag, off, len, exp, 0, r);
7585}
7586
357d1bd8
L		 7587/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7588 purpose of the `.dc.a' internal pseudo-op. */
7589
7590int
7591x86_address_bytes (void)
7592{
7593 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7594 return 4;
7595 return stdoutput->arch_info->bits_per_address / 8;
7596}
7597
d382c579
TG		 7598#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7599 || defined (LEX_AT)
d258b828 7600# define lex_got(reloc, adjust, types) NULL
718ddfc0 7601#else
f3c180ae
AM		 7602/* Parse operands of the form
7603 <symbol>@GOTOFF+<nnn>
7604 and similar .plt or .got references.
7605
7606 If we find one, set up the correct relocation in RELOC and copy the
7607 input string, minus the `@GOTOFF' into a malloc'd buffer for
7608 parsing by the calling routine. Return this buffer, and if ADJUST
7609 is non-null set it to the length of the string we removed from the
7610 input line. Otherwise return NULL. */
7611static char *
91d6fa6a 7612lex_got (enum bfd_reloc_code_real *rel,
64e74474 7613 int *adjust,
d258b828 7614 i386_operand_type *types)
f3c180ae 7615{
7b81dfbb
AJ		 7616 /* Some of the relocations depend on the size of what field is to
7617 be relocated. But in our callers i386_immediate and i386_displacement
7618 we don't yet know the operand size (this will be set by insn
7619 matching). Hence we record the word32 relocation here,
7620 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7621 static const struct {
7622 const char *str;
cff8d58a 7623 int len;
4fa24527 7624 const enum bfd_reloc_code_real rel[2];
40fb9820 7625 const i386_operand_type types64;
f3c180ae 7626 } gotrel[] = {
8ce3d284 7627#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7628 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7629 BFD_RELOC_SIZE32 },
7630 OPERAND_TYPE_IMM32_64 },
8ce3d284 7631#endif
cff8d58a
L		 7632 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7633 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7634 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7635 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7636 BFD_RELOC_X86_64_PLT32 },
40fb9820 7637 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7638 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7639 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7640 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7641 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7642 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7643 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7644 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7645 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7646 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7647 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7648 BFD_RELOC_X86_64_TLSGD },
40fb9820 7649 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7650 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7651 _dummy_first_bfd_reloc_code_real },
40fb9820 7652 OPERAND_TYPE_NONE },
cff8d58a
L		 7653 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7654 BFD_RELOC_X86_64_TLSLD },
40fb9820 7655 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7656 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7657 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7658 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7659 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7660 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7661 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7662 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7663 _dummy_first_bfd_reloc_code_real },
40fb9820 7664 OPERAND_TYPE_NONE },
cff8d58a
L		 7665 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7666 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7667 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7668 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7669 _dummy_first_bfd_reloc_code_real },
40fb9820 7670 OPERAND_TYPE_NONE },
cff8d58a
L		 7671 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7672 _dummy_first_bfd_reloc_code_real },
40fb9820 7673 OPERAND_TYPE_NONE },
cff8d58a
L		 7674 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7675 BFD_RELOC_X86_64_GOT32 },
40fb9820 7676 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7677 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7678 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7679 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7680 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7681 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7682 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7683 };
7684 char *cp;
7685 unsigned int j;
7686
d382c579 7687#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7688 if (!IS_ELF)
7689 return NULL;
d382c579 7690#endif
718ddfc0 7691
f3c180ae 7692 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7693 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7694 return NULL;
7695
47465058 7696 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7697 {
cff8d58a 7698 int len = gotrel[j].len;
28f81592 7699 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7700 {
4fa24527 7701 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7702 {
28f81592
AM		 7703 int first, second;
7704 char *tmpbuf, *past_reloc;
f3c180ae 7705
91d6fa6a 7706 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7707
3956db08
JB		 7708 if (types)
7709 {
7710 if (flag_code != CODE_64BIT)
40fb9820
L		 7711 {
7712 types->bitfield.imm32 = 1;
7713 types->bitfield.disp32 = 1;
7714 }
3956db08
JB		 7715 else
7716 *types = gotrel[j].types64;
7717 }
7718
8fd4256d 7719 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7720 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7721
28f81592 7722 /* The length of the first part of our input line. */
f3c180ae 7723 first = cp - input_line_pointer;
28f81592
AM		 7724
7725 /* The second part goes from after the reloc token until
67c11a9b 7726 (and including) an end_of_line char or comma. */
28f81592 7727 past_reloc = cp + 1 + len;
67c11a9b
AM		 7728 cp = past_reloc;
7729 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7730 ++cp;
7731 second = cp + 1 - past_reloc;
28f81592
AM		 7732
7733 /* Allocate and copy string. The trailing NUL shouldn't
7734 be necessary, but be safe. */
add39d23 7735 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 7736 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7737 if (second != 0 && *past_reloc != ' ')
7738 /* Replace the relocation token with ' ', so that
7739 errors like foo@GOTOFF1 will be detected. */
7740 tmpbuf[first++] = ' ';
af89796a
L		 7741 else
7742 /* Increment length by 1 if the relocation token is
7743 removed. */
7744 len++;
7745 if (adjust)
7746 *adjust = len;
0787a12d
AM		 7747 memcpy (tmpbuf + first, past_reloc, second);
7748 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7749 return tmpbuf;
7750 }
7751
4fa24527
JB		 7752 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7753 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7754 return NULL;
7755 }
7756 }
7757
7758 /* Might be a symbol version string. Don't as_bad here. */
7759 return NULL;
7760}
4e4f7c87 7761#endif
f3c180ae 7762
a988325c
NC		 7763#ifdef TE_PE
7764#ifdef lex_got
7765#undef lex_got
7766#endif
7767/* Parse operands of the form
7768 <symbol>@SECREL32+<nnn>
7769
7770 If we find one, set up the correct relocation in RELOC and copy the
7771 input string, minus the `@SECREL32' into a malloc'd buffer for
7772 parsing by the calling routine. Return this buffer, and if ADJUST
7773 is non-null set it to the length of the string we removed from the
34bca508
L		 7774 input line. Otherwise return NULL.
7775
a988325c
NC		 7776 This function is copied from the ELF version above adjusted for PE targets. */
7777
7778static char *
7779lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7780 int *adjust ATTRIBUTE_UNUSED,
d258b828 7781 i386_operand_type *types)
a988325c
NC		 7782{
7783 static const struct
7784 {
7785 const char *str;
7786 int len;
7787 const enum bfd_reloc_code_real rel[2];
7788 const i386_operand_type types64;
7789 }
7790 gotrel[] =
7791 {
7792 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7793 BFD_RELOC_32_SECREL },
7794 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7795 };
7796
7797 char *cp;
7798 unsigned j;
7799
7800 for (cp = input_line_pointer; *cp != '@'; cp++)
7801 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7802 return NULL;
7803
7804 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7805 {
7806 int len = gotrel[j].len;
7807
7808 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7809 {
7810 if (gotrel[j].rel[object_64bit] != 0)
7811 {
7812 int first, second;
7813 char *tmpbuf, *past_reloc;
7814
7815 *rel = gotrel[j].rel[object_64bit];
7816 if (adjust)
7817 *adjust = len;
7818
7819 if (types)
7820 {
7821 if (flag_code != CODE_64BIT)
7822 {
7823 types->bitfield.imm32 = 1;
7824 types->bitfield.disp32 = 1;
7825 }
7826 else
7827 *types = gotrel[j].types64;
7828 }
7829
7830 /* The length of the first part of our input line. */
7831 first = cp - input_line_pointer;
7832
7833 /* The second part goes from after the reloc token until
7834 (and including) an end_of_line char or comma. */
7835 past_reloc = cp + 1 + len;
7836 cp = past_reloc;
7837 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7838 ++cp;
7839 second = cp + 1 - past_reloc;
7840
7841 /* Allocate and copy string. The trailing NUL shouldn't
7842 be necessary, but be safe. */
add39d23 7843 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 7844 memcpy (tmpbuf, input_line_pointer, first);
7845 if (second != 0 && *past_reloc != ' ')
7846 /* Replace the relocation token with ' ', so that
7847 errors like foo@SECLREL321 will be detected. */
7848 tmpbuf[first++] = ' ';
7849 memcpy (tmpbuf + first, past_reloc, second);
7850 tmpbuf[first + second] = '\0';
7851 return tmpbuf;
7852 }
7853
7854 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7855 gotrel[j].str, 1 << (5 + object_64bit));
7856 return NULL;
7857 }
7858 }
7859
7860 /* Might be a symbol version string. Don't as_bad here. */
7861 return NULL;
7862}
7863
7864#endif /* TE_PE */
7865
62ebcb5c 7866bfd_reloc_code_real_type
e3bb37b5 7867x86_cons (expressionS *exp, int size)
f3c180ae 7868{
62ebcb5c
AM		 7869 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7870
ee86248c
JB		 7871 intel_syntax = -intel_syntax;
7872
3c7b9c2c 7873 exp->X_md = 0;
4fa24527 7874 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7875 {
7876 /* Handle @GOTOFF and the like in an expression. */
7877 char *save;
7878 char *gotfree_input_line;
4a57f2cf 7879 int adjust = 0;
f3c180ae
AM		 7880
7881 save = input_line_pointer;
d258b828 7882 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 7883 if (gotfree_input_line)
7884 input_line_pointer = gotfree_input_line;
7885
7886 expression (exp);
7887
7888 if (gotfree_input_line)
7889 {
7890 /* expression () has merrily parsed up to the end of line,
7891 or a comma - in the wrong buffer. Transfer how far
7892 input_line_pointer has moved to the right buffer. */
7893 input_line_pointer = (save
7894 + (input_line_pointer - gotfree_input_line)
7895 + adjust);
7896 free (gotfree_input_line);
3992d3b7
AM		 7897 if (exp->X_op == O_constant
7898 || exp->X_op == O_absent
7899 || exp->X_op == O_illegal
0398aac5 7900 || exp->X_op == O_register
3992d3b7
AM		 7901 || exp->X_op == O_big)
7902 {
7903 char c = *input_line_pointer;
7904 *input_line_pointer = 0;
7905 as_bad (_("missing or invalid expression `%s'"), save);
7906 *input_line_pointer = c;
7907 }
f3c180ae
AM		 7908 }
7909 }
7910 else
7911 expression (exp);
ee86248c
JB		 7912
7913 intel_syntax = -intel_syntax;
7914
7915 if (intel_syntax)
7916 i386_intel_simplify (exp);
62ebcb5c
AM		 7917
7918 return got_reloc;
f3c180ae 7919}
f3c180ae 7920
9f32dd5b
L		 7921static void
7922signed_cons (int size)
6482c264 7923{
d182319b
JB		 7924 if (flag_code == CODE_64BIT)
7925 cons_sign = 1;
7926 cons (size);
7927 cons_sign = -1;
6482c264
NC		 7928}
7929
d182319b 7930#ifdef TE_PE
6482c264 7931static void
7016a5d5 7932pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7933{
7934 expressionS exp;
7935
7936 do
7937 {
7938 expression (&exp);
7939 if (exp.X_op == O_symbol)
7940 exp.X_op = O_secrel;
7941
7942 emit_expr (&exp, 4);
7943 }
7944 while (*input_line_pointer++ == ',');
7945
7946 input_line_pointer--;
7947 demand_empty_rest_of_line ();
7948}
6482c264
NC		 7949#endif
7950
43234a1e
L		 7951/* Handle Vector operations. */
7952
7953static char *
7954check_VecOperations (char *op_string, char *op_end)
7955{
7956 const reg_entry *mask;
7957 const char *saved;
7958 char *end_op;
7959
7960 while (*op_string
7961 && (op_end == NULL || op_string < op_end))
7962 {
7963 saved = op_string;
7964 if (*op_string == '{')
7965 {
7966 op_string++;
7967
7968 /* Check broadcasts. */
7969 if (strncmp (op_string, "1to", 3) == 0)
7970 {
7971 int bcst_type;
7972
7973 if (i.broadcast)
7974 goto duplicated_vec_op;
7975
7976 op_string += 3;
7977 if (*op_string == '8')
7978 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 7979 else if (*op_string == '4')
7980 bcst_type = BROADCAST_1TO4;
7981 else if (*op_string == '2')
7982 bcst_type = BROADCAST_1TO2;
43234a1e
L		 7983 else if (*op_string == '1'
7984 && *(op_string+1) == '6')
7985 {
7986 bcst_type = BROADCAST_1TO16;
7987 op_string++;
7988 }
7989 else
7990 {
7991 as_bad (_("Unsupported broadcast: `%s'"), saved);
7992 return NULL;
7993 }
7994 op_string++;
7995
7996 broadcast_op.type = bcst_type;
7997 broadcast_op.operand = this_operand;
7998 i.broadcast = &broadcast_op;
7999 }
8000 /* Check masking operation. */
8001 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8002 {
8003 /* k0 can't be used for write mask. */
8004 if (mask->reg_num == 0)
8005 {
8006 as_bad (_("`%s' can't be used for write mask"),
8007 op_string);
8008 return NULL;
8009 }
8010
8011 if (!i.mask)
8012 {
8013 mask_op.mask = mask;
8014 mask_op.zeroing = 0;
8015 mask_op.operand = this_operand;
8016 i.mask = &mask_op;
8017 }
8018 else
8019 {
8020 if (i.mask->mask)
8021 goto duplicated_vec_op;
8022
8023 i.mask->mask = mask;
8024
8025 /* Only "{z}" is allowed here. No need to check
8026 zeroing mask explicitly. */
8027 if (i.mask->operand != this_operand)
8028 {
8029 as_bad (_("invalid write mask `%s'"), saved);
8030 return NULL;
8031 }
8032 }
8033
8034 op_string = end_op;
8035 }
8036 /* Check zeroing-flag for masking operation. */
8037 else if (*op_string == 'z')
8038 {
8039 if (!i.mask)
8040 {
8041 mask_op.mask = NULL;
8042 mask_op.zeroing = 1;
8043 mask_op.operand = this_operand;
8044 i.mask = &mask_op;
8045 }
8046 else
8047 {
8048 if (i.mask->zeroing)
8049 {
8050 duplicated_vec_op:
8051 as_bad (_("duplicated `%s'"), saved);
8052 return NULL;
8053 }
8054
8055 i.mask->zeroing = 1;
8056
8057 /* Only "{%k}" is allowed here. No need to check mask
8058 register explicitly. */
8059 if (i.mask->operand != this_operand)
8060 {
8061 as_bad (_("invalid zeroing-masking `%s'"),
8062 saved);
8063 return NULL;
8064 }
8065 }
8066
8067 op_string++;
8068 }
8069 else
8070 goto unknown_vec_op;
8071
8072 if (*op_string != '}')
8073 {
8074 as_bad (_("missing `}' in `%s'"), saved);
8075 return NULL;
8076 }
8077 op_string++;
8078 continue;
8079 }
8080 unknown_vec_op:
8081 /* We don't know this one. */
8082 as_bad (_("unknown vector operation: `%s'"), saved);
8083 return NULL;
8084 }
8085
8086 return op_string;
8087}
8088
252b5132 8089static int
70e41ade 8090i386_immediate (char *imm_start)
252b5132
RH		 8091{
8092 char *save_input_line_pointer;
f3c180ae 8093 char *gotfree_input_line;
252b5132 8094 segT exp_seg = 0;
47926f60 8095 expressionS *exp;
40fb9820
L		 8096 i386_operand_type types;
8097
0dfbf9d7 8098 operand_type_set (&types, ~0);
252b5132
RH		 8099
8100 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8101 {
31b2323c
L		 8102 as_bad (_("at most %d immediate operands are allowed"),
8103 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8104 return 0;
8105 }
8106
8107 exp = &im_expressions[i.imm_operands++];
520dc8e8 8108 i.op[this_operand].imms = exp;
252b5132
RH		 8109
8110 if (is_space_char (*imm_start))
8111 ++imm_start;
8112
8113 save_input_line_pointer = input_line_pointer;
8114 input_line_pointer = imm_start;
8115
d258b828 8116 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8117 if (gotfree_input_line)
8118 input_line_pointer = gotfree_input_line;
252b5132
RH		 8119
8120 exp_seg = expression (exp);
8121
83183c0c 8122 SKIP_WHITESPACE ();
43234a1e
L		 8123
8124 /* Handle vector operations. */
8125 if (*input_line_pointer == '{')
8126 {
8127 input_line_pointer = check_VecOperations (input_line_pointer,
8128 NULL);
8129 if (input_line_pointer == NULL)
8130 return 0;
8131 }
8132
252b5132 8133 if (*input_line_pointer)
f3c180ae 8134 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8135
8136 input_line_pointer = save_input_line_pointer;
f3c180ae 8137 if (gotfree_input_line)
ee86248c
JB		 8138 {
8139 free (gotfree_input_line);
8140
8141 if (exp->X_op == O_constant || exp->X_op == O_register)
8142 exp->X_op = O_illegal;
8143 }
8144
8145 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8146}
252b5132 8147
ee86248c
JB		 8148static int
8149i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8150 i386_operand_type types, const char *imm_start)
8151{
8152 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8153 {
313c53d1
L		 8154 if (imm_start)
8155 as_bad (_("missing or invalid immediate expression `%s'"),
8156 imm_start);
3992d3b7 8157 return 0;
252b5132 8158 }
3e73aa7c 8159 else if (exp->X_op == O_constant)
252b5132 8160 {
47926f60 8161 /* Size it properly later. */
40fb9820 8162 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8163 /* If not 64bit, sign extend val. */
8164 if (flag_code != CODE_64BIT
4eed87de
AM		 8165 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8166 exp->X_add_number
8167 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8168 }
4c63da97 8169#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8170 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8171 && exp_seg != absolute_section
47926f60 8172 && exp_seg != text_section
24eab124
AM		 8173 && exp_seg != data_section
8174 && exp_seg != bss_section
8175 && exp_seg != undefined_section
f86103b7 8176 && !bfd_is_com_section (exp_seg))
252b5132 8177 {
d0b47220 8178 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8179 return 0;
8180 }
8181#endif
a841bdf5 8182 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8183 {
313c53d1
L		 8184 if (imm_start)
8185 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8186 return 0;
8187 }
252b5132
RH		 8188 else
8189 {
8190 /* This is an address. The size of the address will be
24eab124 8191 determined later, depending on destination register,
3e73aa7c 8192 suffix, or the default for the section. */
40fb9820
L		 8193 i.types[this_operand].bitfield.imm8 = 1;
8194 i.types[this_operand].bitfield.imm16 = 1;
8195 i.types[this_operand].bitfield.imm32 = 1;
8196 i.types[this_operand].bitfield.imm32s = 1;
8197 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8198 i.types[this_operand] = operand_type_and (i.types[this_operand],
8199 types);
252b5132
RH		 8200 }
8201
8202 return 1;
8203}
8204
551c1ca1 8205static char *
e3bb37b5 8206i386_scale (char *scale)
252b5132 8207{
551c1ca1
AM		 8208 offsetT val;
8209 char *save = input_line_pointer;
252b5132 8210
551c1ca1
AM		 8211 input_line_pointer = scale;
8212 val = get_absolute_expression ();
8213
8214 switch (val)
252b5132 8215 {
551c1ca1 8216 case 1:
252b5132
RH		 8217 i.log2_scale_factor = 0;
8218 break;
551c1ca1 8219 case 2:
252b5132
RH		 8220 i.log2_scale_factor = 1;
8221 break;
551c1ca1 8222 case 4:
252b5132
RH		 8223 i.log2_scale_factor = 2;
8224 break;
551c1ca1 8225 case 8:
252b5132
RH		 8226 i.log2_scale_factor = 3;
8227 break;
8228 default:
a724f0f4
JB		 8229 {
8230 char sep = *input_line_pointer;
8231
8232 *input_line_pointer = '\0';
8233 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8234 scale);
8235 *input_line_pointer = sep;
8236 input_line_pointer = save;
8237 return NULL;
8238 }
252b5132 8239 }
29b0f896 8240 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8241 {
8242 as_warn (_("scale factor of %d without an index register"),
24eab124 8243 1 << i.log2_scale_factor);
252b5132 8244 i.log2_scale_factor = 0;
252b5132 8245 }
551c1ca1
AM		 8246 scale = input_line_pointer;
8247 input_line_pointer = save;
8248 return scale;
252b5132
RH		 8249}
8250
252b5132 8251static int
e3bb37b5 8252i386_displacement (char *disp_start, char *disp_end)
252b5132 8253{
29b0f896 8254 expressionS *exp;
252b5132
RH		 8255 segT exp_seg = 0;
8256 char *save_input_line_pointer;
f3c180ae 8257 char *gotfree_input_line;
40fb9820
L		 8258 int override;
8259 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8260 int ret;
252b5132 8261
31b2323c
L		 8262 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8263 {
8264 as_bad (_("at most %d displacement operands are allowed"),
8265 MAX_MEMORY_OPERANDS);
8266 return 0;
8267 }
8268
0dfbf9d7 8269 operand_type_set (&bigdisp, 0);
40fb9820
L		 8270 if ((i.types[this_operand].bitfield.jumpabsolute)
8271 || (!current_templates->start->opcode_modifier.jump
8272 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8273 {
40fb9820 8274 bigdisp.bitfield.disp32 = 1;
e05278af 8275 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8276 if (flag_code == CODE_64BIT)
8277 {
8278 if (!override)
8279 {
8280 bigdisp.bitfield.disp32s = 1;
8281 bigdisp.bitfield.disp64 = 1;
8282 }
8283 }
8284 else if ((flag_code == CODE_16BIT) ^ override)
8285 {
8286 bigdisp.bitfield.disp32 = 0;
8287 bigdisp.bitfield.disp16 = 1;
8288 }
e05278af
JB		 8289 }
8290 else
8291 {
8292 /* For PC-relative branches, the width of the displacement
8293 is dependent upon data size, not address size. */
e05278af 8294 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8295 if (flag_code == CODE_64BIT)
8296 {
8297 if (override || i.suffix == WORD_MNEM_SUFFIX)
8298 bigdisp.bitfield.disp16 = 1;
8299 else
8300 {
8301 bigdisp.bitfield.disp32 = 1;
8302 bigdisp.bitfield.disp32s = 1;
8303 }
8304 }
8305 else
e05278af
JB		 8306 {
8307 if (!override)
8308 override = (i.suffix == (flag_code != CODE_16BIT
8309 ? WORD_MNEM_SUFFIX
8310 : LONG_MNEM_SUFFIX));
40fb9820
L		 8311 bigdisp.bitfield.disp32 = 1;
8312 if ((flag_code == CODE_16BIT) ^ override)
8313 {
8314 bigdisp.bitfield.disp32 = 0;
8315 bigdisp.bitfield.disp16 = 1;
8316 }
e05278af 8317 }
e05278af 8318 }
c6fb90c8
L		 8319 i.types[this_operand] = operand_type_or (i.types[this_operand],
8320 bigdisp);
252b5132
RH		 8321
8322 exp = &disp_expressions[i.disp_operands];
520dc8e8 8323 i.op[this_operand].disps = exp;
252b5132
RH		 8324 i.disp_operands++;
8325 save_input_line_pointer = input_line_pointer;
8326 input_line_pointer = disp_start;
8327 END_STRING_AND_SAVE (disp_end);
8328
8329#ifndef GCC_ASM_O_HACK
8330#define GCC_ASM_O_HACK 0
8331#endif
8332#if GCC_ASM_O_HACK
8333 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8334 if (i.types[this_operand].bitfield.baseIndex
24eab124 8335 && displacement_string_end[-1] == '+')
252b5132
RH		 8336 {
8337 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8338 constraint within gcc asm statements.
8339 For instance:
8340
8341 #define _set_tssldt_desc(n,addr,limit,type) \
8342 __asm__ __volatile__ ( \
8343 "movw %w2,%0\n\t" \
8344 "movw %w1,2+%0\n\t" \
8345 "rorl $16,%1\n\t" \
8346 "movb %b1,4+%0\n\t" \
8347 "movb %4,5+%0\n\t" \
8348 "movb $0,6+%0\n\t" \
8349 "movb %h1,7+%0\n\t" \
8350 "rorl $16,%1" \
8351 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8352
8353 This works great except that the output assembler ends
8354 up looking a bit weird if it turns out that there is
8355 no offset. You end up producing code that looks like:
8356
8357 #APP
8358 movw $235,(%eax)
8359 movw %dx,2+(%eax)
8360 rorl $16,%edx
8361 movb %dl,4+(%eax)
8362 movb $137,5+(%eax)
8363 movb $0,6+(%eax)
8364 movb %dh,7+(%eax)
8365 rorl $16,%edx
8366 #NO_APP
8367
47926f60 8368 So here we provide the missing zero. */
24eab124
AM		 8369
8370 *displacement_string_end = '0';
252b5132
RH		 8371 }
8372#endif
d258b828 8373 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8374 if (gotfree_input_line)
8375 input_line_pointer = gotfree_input_line;
252b5132 8376
24eab124 8377 exp_seg = expression (exp);
252b5132 8378
636c26b0
AM		 8379 SKIP_WHITESPACE ();
8380 if (*input_line_pointer)
8381 as_bad (_("junk `%s' after expression"), input_line_pointer);
8382#if GCC_ASM_O_HACK
8383 RESTORE_END_STRING (disp_end + 1);
8384#endif
636c26b0 8385 input_line_pointer = save_input_line_pointer;
636c26b0 8386 if (gotfree_input_line)
ee86248c
JB		 8387 {
8388 free (gotfree_input_line);
8389
8390 if (exp->X_op == O_constant || exp->X_op == O_register)
8391 exp->X_op = O_illegal;
8392 }
8393
8394 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8395
8396 RESTORE_END_STRING (disp_end);
8397
8398 return ret;
8399}
8400
8401static int
8402i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8403 i386_operand_type types, const char *disp_start)
8404{
8405 i386_operand_type bigdisp;
8406 int ret = 1;
636c26b0 8407
24eab124
AM		 8408 /* We do this to make sure that the section symbol is in
8409 the symbol table. We will ultimately change the relocation
47926f60 8410 to be relative to the beginning of the section. */
1ae12ab7 8411 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8412 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8413 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8414 {
636c26b0 8415 if (exp->X_op != O_symbol)
3992d3b7 8416 goto inv_disp;
636c26b0 8417
e5cb08ac 8418 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8419 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8420 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8421 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8422 exp->X_op = O_subtract;
8423 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8424 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8425 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8426 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8427 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8428 else
29b0f896 8429 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8430 }
252b5132 8431
3992d3b7
AM		 8432 else if (exp->X_op == O_absent
8433 || exp->X_op == O_illegal
ee86248c 8434 || exp->X_op == O_big)
2daf4fd8 8435 {
3992d3b7
AM		 8436 inv_disp:
8437 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8438 disp_start);
3992d3b7 8439 ret = 0;
2daf4fd8
AM		 8440 }
8441
0e1147d9
L		 8442 else if (flag_code == CODE_64BIT
8443 && !i.prefix[ADDR_PREFIX]
8444 && exp->X_op == O_constant)
8445 {
8446 /* Since displacement is signed extended to 64bit, don't allow
8447 disp32 and turn off disp32s if they are out of range. */
8448 i.types[this_operand].bitfield.disp32 = 0;
8449 if (!fits_in_signed_long (exp->X_add_number))
8450 {
8451 i.types[this_operand].bitfield.disp32s = 0;
8452 if (i.types[this_operand].bitfield.baseindex)
8453 {
8454 as_bad (_("0x%lx out range of signed 32bit displacement"),
8455 (long) exp->X_add_number);
8456 ret = 0;
8457 }
8458 }
8459 }
8460
4c63da97 8461#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8462 else if (exp->X_op != O_constant
8463 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8464 && exp_seg != absolute_section
8465 && exp_seg != text_section
8466 && exp_seg != data_section
8467 && exp_seg != bss_section
8468 && exp_seg != undefined_section
8469 && !bfd_is_com_section (exp_seg))
24eab124 8470 {
d0b47220 8471 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8472 ret = 0;
24eab124 8473 }
252b5132 8474#endif
3956db08 8475
40fb9820
L		 8476 /* Check if this is a displacement only operand. */
8477 bigdisp = i.types[this_operand];
8478 bigdisp.bitfield.disp8 = 0;
8479 bigdisp.bitfield.disp16 = 0;
8480 bigdisp.bitfield.disp32 = 0;
8481 bigdisp.bitfield.disp32s = 0;
8482 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8483 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8484 i.types[this_operand] = operand_type_and (i.types[this_operand],
8485 types);
3956db08 8486
3992d3b7 8487 return ret;
252b5132
RH		 8488}
8489
eecb386c 8490/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8491 Return 1 on success, 0 on a failure. */
8492
252b5132 8493static int
e3bb37b5 8494i386_index_check (const char *operand_string)
252b5132 8495{
fc0763e6 8496 const char *kind = "base/index";
be05d201
L		 8497 enum flag_code addr_mode;
8498
8499 if (i.prefix[ADDR_PREFIX])
8500 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8501 else
8502 {
8503 addr_mode = flag_code;
8504
24eab124 8505#if INFER_ADDR_PREFIX
be05d201
L		 8506 if (i.mem_operands == 0)
8507 {
8508 /* Infer address prefix from the first memory operand. */
8509 const reg_entry *addr_reg = i.base_reg;
8510
8511 if (addr_reg == NULL)
8512 addr_reg = i.index_reg;
eecb386c 8513
be05d201
L		 8514 if (addr_reg)
8515 {
8516 if (addr_reg->reg_num == RegEip
8517 || addr_reg->reg_num == RegEiz
8518 || addr_reg->reg_type.bitfield.reg32)
8519 addr_mode = CODE_32BIT;
8520 else if (flag_code != CODE_64BIT
8521 && addr_reg->reg_type.bitfield.reg16)
8522 addr_mode = CODE_16BIT;
8523
8524 if (addr_mode != flag_code)
8525 {
8526 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8527 i.prefixes += 1;
8528 /* Change the size of any displacement too. At most one
8529 of Disp16 or Disp32 is set.
8530 FIXME. There doesn't seem to be any real need for
8531 separate Disp16 and Disp32 flags. The same goes for
8532 Imm16 and Imm32. Removing them would probably clean
8533 up the code quite a lot. */
8534 if (flag_code != CODE_64BIT
8535 && (i.types[this_operand].bitfield.disp16
8536 || i.types[this_operand].bitfield.disp32))
8537 i.types[this_operand]
8538 = operand_type_xor (i.types[this_operand], disp16_32);
8539 }
8540 }
8541 }
24eab124 8542#endif
be05d201
L		 8543 }
8544
fc0763e6
JB		 8545 if (current_templates->start->opcode_modifier.isstring
8546 && !current_templates->start->opcode_modifier.immext
8547 && (current_templates->end[-1].opcode_modifier.isstring
8548 || i.mem_operands))
8549 {
8550 /* Memory operands of string insns are special in that they only allow
8551 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8552 const reg_entry *expected_reg;
8553 static const char *di_si[][2] =
8554 {
8555 { "esi", "edi" },
8556 { "si", "di" },
8557 { "rsi", "rdi" }
8558 };
8559 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8560
8561 kind = "string address";
8562
8325cc63 8563 if (current_templates->start->opcode_modifier.repprefixok)
fc0763e6
JB		 8564 {
8565 i386_operand_type type = current_templates->end[-1].operand_types[0];
8566
8567 if (!type.bitfield.baseindex
8568 || ((!i.mem_operands != !intel_syntax)
8569 && current_templates->end[-1].operand_types[1]
8570 .bitfield.baseindex))
8571 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8572 expected_reg = hash_find (reg_hash,
8573 di_si[addr_mode][type.bitfield.esseg]);
8574
fc0763e6
JB		 8575 }
8576 else
be05d201 8577 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8578
be05d201
L		 8579 if (i.base_reg != expected_reg
8580 || i.index_reg
fc0763e6 8581 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8582 {
be05d201
L		 8583 /* The second memory operand must have the same size as
8584 the first one. */
8585 if (i.mem_operands
8586 && i.base_reg
8587 && !((addr_mode == CODE_64BIT
8588 && i.base_reg->reg_type.bitfield.reg64)
8589 || (addr_mode == CODE_32BIT
8590 ? i.base_reg->reg_type.bitfield.reg32
8591 : i.base_reg->reg_type.bitfield.reg16)))
8592 goto bad_address;
8593
fc0763e6
JB		 8594 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8595 operand_string,
8596 intel_syntax ? '[' : '(',
8597 register_prefix,
be05d201 8598 expected_reg->reg_name,
fc0763e6 8599 intel_syntax ? ']' : ')');
be05d201 8600 return 1;
fc0763e6 8601 }
be05d201
L		 8602 else
8603 return 1;
8604
8605bad_address:
8606 as_bad (_("`%s' is not a valid %s expression"),
8607 operand_string, kind);
8608 return 0;
3e73aa7c
JH		 8609 }
8610 else
8611 {
be05d201
L		 8612 if (addr_mode != CODE_16BIT)
8613 {
8614 /* 32-bit/64-bit checks. */
8615 if ((i.base_reg
8616 && (addr_mode == CODE_64BIT
8617 ? !i.base_reg->reg_type.bitfield.reg64
8618 : !i.base_reg->reg_type.bitfield.reg32)
8619 && (i.index_reg
8620 || (i.base_reg->reg_num
8621 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8622 || (i.index_reg
8623 && !i.index_reg->reg_type.bitfield.regxmm
8624 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8625 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8626 && ((addr_mode == CODE_64BIT
8627 ? !(i.index_reg->reg_type.bitfield.reg64
8628 || i.index_reg->reg_num == RegRiz)
8629 : !(i.index_reg->reg_type.bitfield.reg32
8630 || i.index_reg->reg_num == RegEiz))
8631 || !i.index_reg->reg_type.bitfield.baseindex)))
8632 goto bad_address;
8178be5b
JB		 8633
8634 /* bndmk, bndldx, and bndstx have special restrictions. */
8635 if (current_templates->start->base_opcode == 0xf30f1b
8636 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
8637 {
8638 /* They cannot use RIP-relative addressing. */
8639 if (i.base_reg && i.base_reg->reg_num == RegRip)
8640 {
8641 as_bad (_("`%s' cannot be used here"), operand_string);
8642 return 0;
8643 }
8644
8645 /* bndldx and bndstx ignore their scale factor. */
8646 if (current_templates->start->base_opcode != 0xf30f1b
8647 && i.log2_scale_factor)
8648 as_warn (_("register scaling is being ignored here"));
8649 }
be05d201
L		 8650 }
8651 else
3e73aa7c 8652 {
be05d201 8653 /* 16-bit checks. */
3e73aa7c 8654 if ((i.base_reg
40fb9820
L		 8655 && (!i.base_reg->reg_type.bitfield.reg16
8656 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8657 || (i.index_reg
40fb9820
L		 8658 && (!i.index_reg->reg_type.bitfield.reg16
8659 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8660 || !(i.base_reg
8661 && i.base_reg->reg_num < 6
8662 && i.index_reg->reg_num >= 6
8663 && i.log2_scale_factor == 0))))
be05d201 8664 goto bad_address;
3e73aa7c
JH		 8665 }
8666 }
be05d201 8667 return 1;
24eab124 8668}
252b5132 8669
43234a1e
L		 8670/* Handle vector immediates. */
8671
8672static int
8673RC_SAE_immediate (const char *imm_start)
8674{
8675 unsigned int match_found, j;
8676 const char *pstr = imm_start;
8677 expressionS *exp;
8678
8679 if (*pstr != '{')
8680 return 0;
8681
8682 pstr++;
8683 match_found = 0;
8684 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8685 {
8686 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8687 {
8688 if (!i.rounding)
8689 {
8690 rc_op.type = RC_NamesTable[j].type;
8691 rc_op.operand = this_operand;
8692 i.rounding = &rc_op;
8693 }
8694 else
8695 {
8696 as_bad (_("duplicated `%s'"), imm_start);
8697 return 0;
8698 }
8699 pstr += RC_NamesTable[j].len;
8700 match_found = 1;
8701 break;
8702 }
8703 }
8704 if (!match_found)
8705 return 0;
8706
8707 if (*pstr++ != '}')
8708 {
8709 as_bad (_("Missing '}': '%s'"), imm_start);
8710 return 0;
8711 }
8712 /* RC/SAE immediate string should contain nothing more. */;
8713 if (*pstr != 0)
8714 {
8715 as_bad (_("Junk after '}': '%s'"), imm_start);
8716 return 0;
8717 }
8718
8719 exp = &im_expressions[i.imm_operands++];
8720 i.op[this_operand].imms = exp;
8721
8722 exp->X_op = O_constant;
8723 exp->X_add_number = 0;
8724 exp->X_add_symbol = (symbolS *) 0;
8725 exp->X_op_symbol = (symbolS *) 0;
8726
8727 i.types[this_operand].bitfield.imm8 = 1;
8728 return 1;
8729}
8730
8325cc63
JB		 8731/* Only string instructions can have a second memory operand, so
8732 reduce current_templates to just those if it contains any. */
8733static int
8734maybe_adjust_templates (void)
8735{
8736 const insn_template *t;
8737
8738 gas_assert (i.mem_operands == 1);
8739
8740 for (t = current_templates->start; t < current_templates->end; ++t)
8741 if (t->opcode_modifier.isstring)
8742 break;
8743
8744 if (t < current_templates->end)
8745 {
8746 static templates aux_templates;
8747 bfd_boolean recheck;
8748
8749 aux_templates.start = t;
8750 for (; t < current_templates->end; ++t)
8751 if (!t->opcode_modifier.isstring)
8752 break;
8753 aux_templates.end = t;
8754
8755 /* Determine whether to re-check the first memory operand. */
8756 recheck = (aux_templates.start != current_templates->start
8757 || t != current_templates->end);
8758
8759 current_templates = &aux_templates;
8760
8761 if (recheck)
8762 {
8763 i.mem_operands = 0;
8764 if (i.memop1_string != NULL
8765 && i386_index_check (i.memop1_string) == 0)
8766 return 0;
8767 i.mem_operands = 1;
8768 }
8769 }
8770
8771 return 1;
8772}
8773
fc0763e6 8774/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8775 on error. */
252b5132 8776
252b5132 8777static int
a7619375 8778i386_att_operand (char *operand_string)
252b5132 8779{
af6bdddf
AM		 8780 const reg_entry *r;
8781 char *end_op;
24eab124 8782 char *op_string = operand_string;
252b5132 8783
24eab124 8784 if (is_space_char (*op_string))
252b5132
RH		 8785 ++op_string;
8786
24eab124 8787 /* We check for an absolute prefix (differentiating,
47926f60 8788 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8789 if (*op_string == ABSOLUTE_PREFIX)
8790 {
8791 ++op_string;
8792 if (is_space_char (*op_string))
8793 ++op_string;
40fb9820 8794 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8795 }
252b5132 8796
47926f60 8797 /* Check if operand is a register. */
4d1bb795 8798 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8799 {
40fb9820
L		 8800 i386_operand_type temp;
8801
24eab124
AM		 8802 /* Check for a segment override by searching for ':' after a
8803 segment register. */
8804 op_string = end_op;
8805 if (is_space_char (*op_string))
8806 ++op_string;
40fb9820
L		 8807 if (*op_string == ':'
8808 && (r->reg_type.bitfield.sreg2
8809 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8810 {
8811 switch (r->reg_num)
8812 {
8813 case 0:
8814 i.seg[i.mem_operands] = &es;
8815 break;
8816 case 1:
8817 i.seg[i.mem_operands] = &cs;
8818 break;
8819 case 2:
8820 i.seg[i.mem_operands] = &ss;
8821 break;
8822 case 3:
8823 i.seg[i.mem_operands] = &ds;
8824 break;
8825 case 4:
8826 i.seg[i.mem_operands] = &fs;
8827 break;
8828 case 5:
8829 i.seg[i.mem_operands] = &gs;
8830 break;
8831 }
252b5132 8832
24eab124 8833 /* Skip the ':' and whitespace. */
252b5132
RH		 8834 ++op_string;
8835 if (is_space_char (*op_string))
24eab124 8836 ++op_string;
252b5132 8837
24eab124
AM		 8838 if (!is_digit_char (*op_string)
8839 && !is_identifier_char (*op_string)
8840 && *op_string != '('
8841 && *op_string != ABSOLUTE_PREFIX)
8842 {
8843 as_bad (_("bad memory operand `%s'"), op_string);
8844 return 0;
8845 }
47926f60 8846 /* Handle case of %es:*foo. */
24eab124
AM		 8847 if (*op_string == ABSOLUTE_PREFIX)
8848 {
8849 ++op_string;
8850 if (is_space_char (*op_string))
8851 ++op_string;
40fb9820 8852 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8853 }
8854 goto do_memory_reference;
8855 }
43234a1e
L		 8856
8857 /* Handle vector operations. */
8858 if (*op_string == '{')
8859 {
8860 op_string = check_VecOperations (op_string, NULL);
8861 if (op_string == NULL)
8862 return 0;
8863 }
8864
24eab124
AM		 8865 if (*op_string)
8866 {
d0b47220 8867 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8868 return 0;
8869 }
40fb9820
L		 8870 temp = r->reg_type;
8871 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8872 i.types[this_operand] = operand_type_or (i.types[this_operand],
8873 temp);
7d5e4556 8874 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8875 i.op[this_operand].regs = r;
24eab124
AM		 8876 i.reg_operands++;
8877 }
af6bdddf
AM		 8878 else if (*op_string == REGISTER_PREFIX)
8879 {
8880 as_bad (_("bad register name `%s'"), op_string);
8881 return 0;
8882 }
24eab124 8883 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8884 {
24eab124 8885 ++op_string;
40fb9820 8886 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8887 {
d0b47220 8888 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8889 return 0;
8890 }
8891 if (!i386_immediate (op_string))
8892 return 0;
8893 }
43234a1e
L		 8894 else if (RC_SAE_immediate (operand_string))
8895 {
8896 /* If it is a RC or SAE immediate, do nothing. */
8897 ;
8898 }
24eab124
AM		 8899 else if (is_digit_char (*op_string)
8900 || is_identifier_char (*op_string)
d02603dc 8901 || *op_string == '"'
e5cb08ac 8902 || *op_string == '(')
24eab124 8903 {
47926f60 8904 /* This is a memory reference of some sort. */
af6bdddf 8905 char *base_string;
252b5132 8906
47926f60 8907 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8908 char *displacement_string_start;
8909 char *displacement_string_end;
43234a1e 8910 char *vop_start;
252b5132 8911
24eab124 8912 do_memory_reference:
8325cc63
JB		 8913 if (i.mem_operands == 1 && !maybe_adjust_templates ())
8914 return 0;
24eab124 8915 if ((i.mem_operands == 1
40fb9820 8916 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8917 || i.mem_operands == 2)
8918 {
8919 as_bad (_("too many memory references for `%s'"),
8920 current_templates->start->name);
8921 return 0;
8922 }
252b5132 8923
24eab124
AM		 8924 /* Check for base index form. We detect the base index form by
8925 looking for an ')' at the end of the operand, searching
8926 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8927 after the '('. */
af6bdddf 8928 base_string = op_string + strlen (op_string);
c3332e24 8929
43234a1e
L		 8930 /* Handle vector operations. */
8931 vop_start = strchr (op_string, '{');
8932 if (vop_start && vop_start < base_string)
8933 {
8934 if (check_VecOperations (vop_start, base_string) == NULL)
8935 return 0;
8936 base_string = vop_start;
8937 }
8938
af6bdddf
AM		 8939 --base_string;
8940 if (is_space_char (*base_string))
8941 --base_string;
252b5132 8942
47926f60 8943 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8944 displacement_string_start = op_string;
8945 displacement_string_end = base_string + 1;
252b5132 8946
24eab124
AM		 8947 if (*base_string == ')')
8948 {
af6bdddf 8949 char *temp_string;
24eab124
AM		 8950 unsigned int parens_balanced = 1;
8951 /* We've already checked that the number of left & right ()'s are
47926f60 8952 equal, so this loop will not be infinite. */
24eab124
AM		 8953 do
8954 {
8955 base_string--;
8956 if (*base_string == ')')
8957 parens_balanced++;
8958 if (*base_string == '(')
8959 parens_balanced--;
8960 }
8961 while (parens_balanced);
c3332e24 8962
af6bdddf 8963 temp_string = base_string;
c3332e24 8964
24eab124 8965 /* Skip past '(' and whitespace. */
252b5132
RH		 8966 ++base_string;
8967 if (is_space_char (*base_string))
24eab124 8968 ++base_string;
252b5132 8969
af6bdddf 8970 if (*base_string == ','
4eed87de
AM		 8971 || ((i.base_reg = parse_register (base_string, &end_op))
8972 != NULL))
252b5132 8973 {
af6bdddf 8974 displacement_string_end = temp_string;
252b5132 8975
40fb9820 8976 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8977
af6bdddf 8978 if (i.base_reg)
24eab124 8979 {
24eab124
AM		 8980 base_string = end_op;
8981 if (is_space_char (*base_string))
8982 ++base_string;
af6bdddf
AM		 8983 }
8984
8985 /* There may be an index reg or scale factor here. */
8986 if (*base_string == ',')
8987 {
8988 ++base_string;
8989 if (is_space_char (*base_string))
8990 ++base_string;
8991
4eed87de
AM		 8992 if ((i.index_reg = parse_register (base_string, &end_op))
8993 != NULL)
24eab124 8994 {
af6bdddf 8995 base_string = end_op;
24eab124
AM		 8996 if (is_space_char (*base_string))
8997 ++base_string;
af6bdddf
AM		 8998 if (*base_string == ',')
8999 {
9000 ++base_string;
9001 if (is_space_char (*base_string))
9002 ++base_string;
9003 }
e5cb08ac 9004 else if (*base_string != ')')
af6bdddf 9005 {
4eed87de
AM		 9006 as_bad (_("expecting `,' or `)' "
9007 "after index register in `%s'"),
af6bdddf
AM		 9008 operand_string);
9009 return 0;
9010 }
24eab124 9011 }
af6bdddf 9012 else if (*base_string == REGISTER_PREFIX)
24eab124 9013 {
f76bf5e0
L		 9014 end_op = strchr (base_string, ',');
9015 if (end_op)
9016 *end_op = '\0';
af6bdddf 9017 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 9018 return 0;
9019 }
252b5132 9020
47926f60 9021 /* Check for scale factor. */
551c1ca1 9022 if (*base_string != ')')
af6bdddf 9023 {
551c1ca1
AM		 9024 char *end_scale = i386_scale (base_string);
9025
9026 if (!end_scale)
af6bdddf 9027 return 0;
24eab124 9028
551c1ca1 9029 base_string = end_scale;
af6bdddf
AM		 9030 if (is_space_char (*base_string))
9031 ++base_string;
9032 if (*base_string != ')')
9033 {
4eed87de
AM		 9034 as_bad (_("expecting `)' "
9035 "after scale factor in `%s'"),
af6bdddf
AM		 9036 operand_string);
9037 return 0;
9038 }
9039 }
9040 else if (!i.index_reg)
24eab124 9041 {
4eed87de
AM		 9042 as_bad (_("expecting index register or scale factor "
9043 "after `,'; got '%c'"),
af6bdddf 9044 *base_string);
24eab124
AM		 9045 return 0;
9046 }
9047 }
af6bdddf 9048 else if (*base_string != ')')
24eab124 9049 {
4eed87de
AM		 9050 as_bad (_("expecting `,' or `)' "
9051 "after base register in `%s'"),
af6bdddf 9052 operand_string);
24eab124
AM		 9053 return 0;
9054 }
c3332e24 9055 }
af6bdddf 9056 else if (*base_string == REGISTER_PREFIX)
c3332e24 9057 {
f76bf5e0
L		 9058 end_op = strchr (base_string, ',');
9059 if (end_op)
9060 *end_op = '\0';
af6bdddf 9061 as_bad (_("bad register name `%s'"), base_string);
24eab124 9062 return 0;
c3332e24 9063 }
24eab124
AM		 9064 }
9065
9066 /* If there's an expression beginning the operand, parse it,
9067 assuming displacement_string_start and
9068 displacement_string_end are meaningful. */
9069 if (displacement_string_start != displacement_string_end)
9070 {
9071 if (!i386_displacement (displacement_string_start,
9072 displacement_string_end))
9073 return 0;
9074 }
9075
9076 /* Special case for (%dx) while doing input/output op. */
9077 if (i.base_reg
0dfbf9d7
L		 9078 && operand_type_equal (&i.base_reg->reg_type,
9079 &reg16_inoutportreg)
24eab124
AM		 9080 && i.index_reg == 0
9081 && i.log2_scale_factor == 0
9082 && i.seg[i.mem_operands] == 0
40fb9820 9083 && !operand_type_check (i.types[this_operand], disp))
24eab124 9084 {
65da13b5 9085 i.types[this_operand] = inoutportreg;
24eab124
AM		 9086 return 1;
9087 }
9088
eecb386c
AM		 9089 if (i386_index_check (operand_string) == 0)
9090 return 0;
5c07affc 9091 i.types[this_operand].bitfield.mem = 1;
8325cc63
JB		 9092 if (i.mem_operands == 0)
9093 i.memop1_string = xstrdup (operand_string);
24eab124
AM		 9094 i.mem_operands++;
9095 }
9096 else
ce8a8b2f
AM		 9097 {
9098 /* It's not a memory operand; argh! */
24eab124
AM		 9099 as_bad (_("invalid char %s beginning operand %d `%s'"),
9100 output_invalid (*op_string),
9101 this_operand + 1,
9102 op_string);
9103 return 0;
9104 }
47926f60 9105 return 1; /* Normal return. */
252b5132
RH		 9106}
9107\f
fa94de6b
RM		 9108/* Calculate the maximum variable size (i.e., excluding fr_fix)
9109 that an rs_machine_dependent frag may reach. */
9110
9111unsigned int
9112i386_frag_max_var (fragS *frag)
9113{
9114 /* The only relaxable frags are for jumps.
9115 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9116 gas_assert (frag->fr_type == rs_machine_dependent);
9117 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9118}
9119
b084df0b
L		 9120#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9121static int
8dcea932 9122elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 9123{
9124 /* STT_GNU_IFUNC symbol must go through PLT. */
9125 if ((symbol_get_bfdsym (fr_symbol)->flags
9126 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9127 return 0;
9128
9129 if (!S_IS_EXTERNAL (fr_symbol))
9130 /* Symbol may be weak or local. */
9131 return !S_IS_WEAK (fr_symbol);
9132
8dcea932
L		 9133 /* Global symbols with non-default visibility can't be preempted. */
9134 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9135 return 1;
9136
9137 if (fr_var != NO_RELOC)
9138 switch ((enum bfd_reloc_code_real) fr_var)
9139 {
9140 case BFD_RELOC_386_PLT32:
9141 case BFD_RELOC_X86_64_PLT32:
9142 /* Symbol with PLT relocatin may be preempted. */
9143 return 0;
9144 default:
9145 abort ();
9146 }
9147
b084df0b
L		 9148 /* Global symbols with default visibility in a shared library may be
9149 preempted by another definition. */
8dcea932 9150 return !shared;
b084df0b
L		 9151}
9152#endif
9153
ee7fcc42
AM		 9154/* md_estimate_size_before_relax()
9155
9156 Called just before relax() for rs_machine_dependent frags. The x86
9157 assembler uses these frags to handle variable size jump
9158 instructions.
9159
9160 Any symbol that is now undefined will not become defined.
9161 Return the correct fr_subtype in the frag.
9162 Return the initial "guess for variable size of frag" to caller.
9163 The guess is actually the growth beyond the fixed part. Whatever
9164 we do to grow the fixed or variable part contributes to our
9165 returned value. */
9166
252b5132 9167int
7016a5d5 9168md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9169{
252b5132 9170 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9171 check for un-relaxable symbols. On an ELF system, we can't relax
9172 an externally visible symbol, because it may be overridden by a
9173 shared library. */
9174 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9175#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9176 || (IS_ELF
8dcea932
L		 9177 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9178 fragP->fr_var))
fbeb56a4
DK		 9179#endif
9180#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9181 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9182 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9183#endif
9184 )
252b5132 9185 {
b98ef147
AM		 9186 /* Symbol is undefined in this segment, or we need to keep a
9187 reloc so that weak symbols can be overridden. */
9188 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9189 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9190 unsigned char *opcode;
9191 int old_fr_fix;
f6af82bd 9192
ee7fcc42 9193 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9194 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9195 else if (size == 2)
f6af82bd
AM		 9196 reloc_type = BFD_RELOC_16_PCREL;
9197 else
9198 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9199
ee7fcc42
AM		 9200 old_fr_fix = fragP->fr_fix;
9201 opcode = (unsigned char *) fragP->fr_opcode;
9202
fddf5b5b 9203 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9204 {
fddf5b5b
AM		 9205 case UNCOND_JUMP:
9206 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9207 opcode[0] = 0xe9;
252b5132 9208 fragP->fr_fix += size;
062cd5e7
AS		 9209 fix_new (fragP, old_fr_fix, size,
9210 fragP->fr_symbol,
9211 fragP->fr_offset, 1,
9212 reloc_type);
252b5132
RH		 9213 break;
9214
fddf5b5b 9215 case COND_JUMP86:
412167cb
AM		 9216 if (size == 2
9217 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9218 {
9219 /* Negate the condition, and branch past an
9220 unconditional jump. */
9221 opcode[0] ^= 1;
9222 opcode[1] = 3;
9223 /* Insert an unconditional jump. */
9224 opcode[2] = 0xe9;
9225 /* We added two extra opcode bytes, and have a two byte
9226 offset. */
9227 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9228 fix_new (fragP, old_fr_fix + 2, 2,
9229 fragP->fr_symbol,
9230 fragP->fr_offset, 1,
9231 reloc_type);
fddf5b5b
AM		 9232 break;
9233 }
9234 /* Fall through. */
9235
9236 case COND_JUMP:
412167cb
AM		 9237 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9238 {
3e02c1cc
AM		 9239 fixS *fixP;
9240
412167cb 9241 fragP->fr_fix += 1;
3e02c1cc
AM		 9242 fixP = fix_new (fragP, old_fr_fix, 1,
9243 fragP->fr_symbol,
9244 fragP->fr_offset, 1,
9245 BFD_RELOC_8_PCREL);
9246 fixP->fx_signed = 1;
412167cb
AM		 9247 break;
9248 }
93c2a809 9249
24eab124 9250 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9251 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9252 opcode[1] = opcode[0] + 0x10;
f6af82bd 9253 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9254 /* We've added an opcode byte. */
9255 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9256 fix_new (fragP, old_fr_fix + 1, size,
9257 fragP->fr_symbol,
9258 fragP->fr_offset, 1,
9259 reloc_type);
252b5132 9260 break;
fddf5b5b
AM		 9261
9262 default:
9263 BAD_CASE (fragP->fr_subtype);
9264 break;
252b5132
RH		 9265 }
9266 frag_wane (fragP);
ee7fcc42 9267 return fragP->fr_fix - old_fr_fix;
252b5132 9268 }
93c2a809 9269
93c2a809
AM		 9270 /* Guess size depending on current relax state. Initially the relax
9271 state will correspond to a short jump and we return 1, because
9272 the variable part of the frag (the branch offset) is one byte
9273 long. However, we can relax a section more than once and in that
9274 case we must either set fr_subtype back to the unrelaxed state,
9275 or return the value for the appropriate branch. */
9276 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9277}
9278
47926f60
KH		 9279/* Called after relax() is finished.
9280
9281 In: Address of frag.
9282 fr_type == rs_machine_dependent.
9283 fr_subtype is what the address relaxed to.
9284
9285 Out: Any fixSs and constants are set up.
9286 Caller will turn frag into a ".space 0". */
9287
252b5132 9288void
7016a5d5
TG		 9289md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9290 fragS *fragP)
252b5132 9291{
29b0f896 9292 unsigned char *opcode;
252b5132 9293 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9294 offsetT target_address;
9295 offsetT opcode_address;
252b5132 9296 unsigned int extension = 0;
847f7ad4 9297 offsetT displacement_from_opcode_start;
252b5132
RH		 9298
9299 opcode = (unsigned char *) fragP->fr_opcode;
9300
47926f60 9301 /* Address we want to reach in file space. */
252b5132 9302 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9303
47926f60 9304 /* Address opcode resides at in file space. */
252b5132
RH		 9305 opcode_address = fragP->fr_address + fragP->fr_fix;
9306
47926f60 9307 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9308 displacement_from_opcode_start = target_address - opcode_address;
9309
fddf5b5b 9310 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9311 {
47926f60
KH		 9312 /* Don't have to change opcode. */
9313 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9314 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9315 }
9316 else
9317 {
9318 if (no_cond_jump_promotion
9319 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9320 as_warn_where (fragP->fr_file, fragP->fr_line,
9321 _("long jump required"));
252b5132 9322
fddf5b5b
AM		 9323 switch (fragP->fr_subtype)
9324 {
9325 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9326 extension = 4; /* 1 opcode + 4 displacement */
9327 opcode[0] = 0xe9;
9328 where_to_put_displacement = &opcode[1];
9329 break;
252b5132 9330
fddf5b5b
AM		 9331 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9332 extension = 2; /* 1 opcode + 2 displacement */
9333 opcode[0] = 0xe9;
9334 where_to_put_displacement = &opcode[1];
9335 break;
252b5132 9336
fddf5b5b
AM		 9337 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9338 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9339 extension = 5; /* 2 opcode + 4 displacement */
9340 opcode[1] = opcode[0] + 0x10;
9341 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9342 where_to_put_displacement = &opcode[2];
9343 break;
252b5132 9344
fddf5b5b
AM		 9345 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9346 extension = 3; /* 2 opcode + 2 displacement */
9347 opcode[1] = opcode[0] + 0x10;
9348 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9349 where_to_put_displacement = &opcode[2];
9350 break;
252b5132 9351
fddf5b5b
AM		 9352 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9353 extension = 4;
9354 opcode[0] ^= 1;
9355 opcode[1] = 3;
9356 opcode[2] = 0xe9;
9357 where_to_put_displacement = &opcode[3];
9358 break;
9359
9360 default:
9361 BAD_CASE (fragP->fr_subtype);
9362 break;
9363 }
252b5132 9364 }
fddf5b5b 9365
7b81dfbb
AJ		 9366 /* If size if less then four we are sure that the operand fits,
9367 but if it's 4, then it could be that the displacement is larger
9368 then -/+ 2GB. */
9369 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9370 && object_64bit
9371 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9372 + ((addressT) 1 << 31))
9373 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9374 {
9375 as_bad_where (fragP->fr_file, fragP->fr_line,
9376 _("jump target out of range"));
9377 /* Make us emit 0. */
9378 displacement_from_opcode_start = extension;
9379 }
47926f60 9380 /* Now put displacement after opcode. */
252b5132
RH		 9381 md_number_to_chars ((char *) where_to_put_displacement,
9382 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9383 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9384 fragP->fr_fix += extension;
9385}
9386\f
7016a5d5 9387/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9388 by our caller that we have all the info we need to fix it up.
9389
7016a5d5
TG		 9390 Parameter valP is the pointer to the value of the bits.
9391
252b5132
RH		 9392 On the 386, immediates, displacements, and data pointers are all in
9393 the same (little-endian) format, so we don't need to care about which
9394 we are handling. */
9395
94f592af 9396void
7016a5d5 9397md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9398{
94f592af 9399 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9400 valueT value = *valP;
252b5132 9401
f86103b7 9402#if !defined (TE_Mach)
93382f6d
AM		 9403 if (fixP->fx_pcrel)
9404 {
9405 switch (fixP->fx_r_type)
9406 {
5865bb77
ILT		 9407 default:
9408 break;
9409
d6ab8113
JB		 9410 case BFD_RELOC_64:
9411 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9412 break;
93382f6d 9413 case BFD_RELOC_32:
ae8887b5 9414 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9415 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9416 break;
9417 case BFD_RELOC_16:
9418 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9419 break;
9420 case BFD_RELOC_8:
9421 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9422 break;
9423 }
9424 }
252b5132 9425
a161fe53 9426 if (fixP->fx_addsy != NULL
31312f95 9427 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9428 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9429 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9430 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9431 && !use_rela_relocations)
252b5132 9432 {
31312f95
AM		 9433 /* This is a hack. There should be a better way to handle this.
9434 This covers for the fact that bfd_install_relocation will
9435 subtract the current location (for partial_inplace, PC relative
9436 relocations); see more below. */
252b5132 9437#ifndef OBJ_AOUT
718ddfc0 9438 if (IS_ELF
252b5132
RH		 9439#ifdef TE_PE
9440 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9441#endif
9442 )
9443 value += fixP->fx_where + fixP->fx_frag->fr_address;
9444#endif
9445#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9446 if (IS_ELF)
252b5132 9447 {
6539b54b 9448 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9449
6539b54b 9450 if ((sym_seg == seg
2f66722d 9451 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9452 && sym_seg != absolute_section))
af65af87 9453 && !generic_force_reloc (fixP))
2f66722d
AM		 9454 {
9455 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9456 bfd_install_relocation subtracts them out again. I think
9457 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9458 it. FIXME. */
9459 value += fixP->fx_where + fixP->fx_frag->fr_address;
9460 }
252b5132
RH		 9461 }
9462#endif
9463#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9464 /* For some reason, the PE format does not store a
9465 section address offset for a PC relative symbol. */
9466 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9467 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9468 value += md_pcrel_from (fixP);
9469#endif
9470 }
fbeb56a4 9471#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9472 if (fixP->fx_addsy != NULL
9473 && S_IS_WEAK (fixP->fx_addsy)
9474 /* PR 16858: Do not modify weak function references. */
9475 && ! fixP->fx_pcrel)
fbeb56a4 9476 {
296a8689
NC		 9477#if !defined (TE_PEP)
9478 /* For x86 PE weak function symbols are neither PC-relative
9479 nor do they set S_IS_FUNCTION. So the only reliable way
9480 to detect them is to check the flags of their containing
9481 section. */
9482 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9483 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9484 ;
9485 else
9486#endif
fbeb56a4
DK		 9487 value -= S_GET_VALUE (fixP->fx_addsy);
9488 }
9489#endif
252b5132
RH		 9490
9491 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9492 and we must not disappoint it. */
252b5132 9493#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9494 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9495 switch (fixP->fx_r_type)
9496 {
9497 case BFD_RELOC_386_PLT32:
3e73aa7c 9498 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9499 /* Make the jump instruction point to the address of the operand. At
9500 runtime we merely add the offset to the actual PLT entry. */
9501 value = -4;
9502 break;
31312f95 9503
13ae64f3
JJ		 9504 case BFD_RELOC_386_TLS_GD:
9505 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9506 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9507 case BFD_RELOC_386_TLS_IE:
9508 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9509 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9510 case BFD_RELOC_X86_64_TLSGD:
9511 case BFD_RELOC_X86_64_TLSLD:
9512 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9513 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9514 value = 0; /* Fully resolved at runtime. No addend. */
9515 /* Fallthrough */
9516 case BFD_RELOC_386_TLS_LE:
9517 case BFD_RELOC_386_TLS_LDO_32:
9518 case BFD_RELOC_386_TLS_LE_32:
9519 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9520 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9521 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9522 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9523 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9524 break;
9525
67a4f2b7
AO		 9526 case BFD_RELOC_386_TLS_DESC_CALL:
9527 case BFD_RELOC_X86_64_TLSDESC_CALL:
9528 value = 0; /* Fully resolved at runtime. No addend. */
9529 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9530 fixP->fx_done = 0;
9531 return;
9532
47926f60
KH		 9533 case BFD_RELOC_VTABLE_INHERIT:
9534 case BFD_RELOC_VTABLE_ENTRY:
9535 fixP->fx_done = 0;
94f592af 9536 return;
47926f60
KH		 9537
9538 default:
9539 break;
9540 }
9541#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9542 *valP = value;
f86103b7 9543#endif /* !defined (TE_Mach) */
3e73aa7c 9544
3e73aa7c 9545 /* Are we finished with this relocation now? */
c6682705 9546 if (fixP->fx_addsy == NULL)
3e73aa7c 9547 fixP->fx_done = 1;
fbeb56a4
DK		 9548#if defined (OBJ_COFF) && defined (TE_PE)
9549 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9550 {
9551 fixP->fx_done = 0;
9552 /* Remember value for tc_gen_reloc. */
9553 fixP->fx_addnumber = value;
9554 /* Clear out the frag for now. */
9555 value = 0;
9556 }
9557#endif
3e73aa7c
JH		 9558 else if (use_rela_relocations)
9559 {
9560 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9561 /* Remember value for tc_gen_reloc. */
9562 fixP->fx_addnumber = value;
3e73aa7c
JH		 9563 value = 0;
9564 }
f86103b7 9565
94f592af 9566 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9567}
252b5132 9568\f
6d4af3c2 9569const char *
499ac353 9570md_atof (int type, char *litP, int *sizeP)
252b5132 9571{
499ac353
NC		 9572 /* This outputs the LITTLENUMs in REVERSE order;
9573 in accord with the bigendian 386. */
9574 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9575}
9576\f
2d545b82 9577static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9578
252b5132 9579static char *
e3bb37b5 9580output_invalid (int c)
252b5132 9581{
3882b010 9582 if (ISPRINT (c))
f9f21a03
L		 9583 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9584 "'%c'", c);
252b5132 9585 else
f9f21a03 9586 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9587 "(0x%x)", (unsigned char) c);
252b5132
RH		 9588 return output_invalid_buf;
9589}
9590
af6bdddf 9591/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9592
9593static const reg_entry *
4d1bb795 9594parse_real_register (char *reg_string, char **end_op)
252b5132 9595{
af6bdddf
AM		 9596 char *s = reg_string;
9597 char *p;
252b5132
RH		 9598 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9599 const reg_entry *r;
9600
9601 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9602 if (*s == REGISTER_PREFIX)
9603 ++s;
9604
9605 if (is_space_char (*s))
9606 ++s;
9607
9608 p = reg_name_given;
af6bdddf 9609 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9610 {
9611 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9612 return (const reg_entry *) NULL;
9613 s++;
252b5132
RH		 9614 }
9615
6588847e
DN		 9616 /* For naked regs, make sure that we are not dealing with an identifier.
9617 This prevents confusing an identifier like `eax_var' with register
9618 `eax'. */
9619 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9620 return (const reg_entry *) NULL;
9621
af6bdddf 9622 *end_op = s;
252b5132
RH		 9623
9624 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9625
5f47d35b 9626 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9627 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9628 {
5f47d35b
AM		 9629 if (is_space_char (*s))
9630 ++s;
9631 if (*s == '(')
9632 {
af6bdddf 9633 ++s;
5f47d35b
AM		 9634 if (is_space_char (*s))
9635 ++s;
9636 if (*s >= '0' && *s <= '7')
9637 {
db557034 9638 int fpr = *s - '0';
af6bdddf 9639 ++s;
5f47d35b
AM		 9640 if (is_space_char (*s))
9641 ++s;
9642 if (*s == ')')
9643 {
9644 *end_op = s + 1;
1e9cc1c2 9645 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9646 know (r);
9647 return r + fpr;
5f47d35b 9648 }
5f47d35b 9649 }
47926f60 9650 /* We have "%st(" then garbage. */
5f47d35b
AM		 9651 return (const reg_entry *) NULL;
9652 }
9653 }
9654
a60de03c
JB		 9655 if (r == NULL || allow_pseudo_reg)
9656 return r;
9657
0dfbf9d7 9658 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9659 return (const reg_entry *) NULL;
9660
192dc9c6
JB		 9661 if ((r->reg_type.bitfield.reg32
9662 || r->reg_type.bitfield.sreg3
9663 || r->reg_type.bitfield.control
9664 || r->reg_type.bitfield.debug
9665 || r->reg_type.bitfield.test)
9666 && !cpu_arch_flags.bitfield.cpui386)
9667 return (const reg_entry *) NULL;
9668
309d3373
JB		 9669 if (r->reg_type.bitfield.floatreg
9670 && !cpu_arch_flags.bitfield.cpu8087
9671 && !cpu_arch_flags.bitfield.cpu287
9672 && !cpu_arch_flags.bitfield.cpu387)
9673 return (const reg_entry *) NULL;
9674
1848e567 9675 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
192dc9c6
JB		 9676 return (const reg_entry *) NULL;
9677
1848e567 9678 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpuregxmm)
192dc9c6
JB		 9679 return (const reg_entry *) NULL;
9680
1848e567 9681 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuregymm)
40f12533
L		 9682 return (const reg_entry *) NULL;
9683
1848e567
L		 9684 if (r->reg_type.bitfield.regzmm && !cpu_arch_flags.bitfield.cpuregzmm)
9685 return (const reg_entry *) NULL;
9686
9687 if (r->reg_type.bitfield.regmask
9688 && !cpu_arch_flags.bitfield.cpuregmask)
43234a1e
L		 9689 return (const reg_entry *) NULL;
9690
db51cc60 9691 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9692 if (!allow_index_reg
db51cc60
L		 9693 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9694 return (const reg_entry *) NULL;
9695
43234a1e
L		 9696 /* Upper 16 vector register is only available with VREX in 64bit
9697 mode. */
9698 if ((r->reg_flags & RegVRex))
9699 {
9700 if (!cpu_arch_flags.bitfield.cpuvrex
9701 || flag_code != CODE_64BIT)
9702 return (const reg_entry *) NULL;
9703
9704 i.need_vrex = 1;
9705 }
9706
a60de03c
JB		 9707 if (((r->reg_flags & (RegRex64 | RegRex))
9708 || r->reg_type.bitfield.reg64)
40fb9820 9709 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9710 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9711 && flag_code != CODE_64BIT)
20f0a1fc 9712 return (const reg_entry *) NULL;
1ae00879 9713
b7240065
JB		 9714 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9715 return (const reg_entry *) NULL;
9716
252b5132
RH		 9717 return r;
9718}
4d1bb795
JB		 9719
9720/* REG_STRING starts *before* REGISTER_PREFIX. */
9721
9722static const reg_entry *
9723parse_register (char *reg_string, char **end_op)
9724{
9725 const reg_entry *r;
9726
9727 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9728 r = parse_real_register (reg_string, end_op);
9729 else
9730 r = NULL;
9731 if (!r)
9732 {
9733 char *save = input_line_pointer;
9734 char c;
9735 symbolS *symbolP;
9736
9737 input_line_pointer = reg_string;
d02603dc 9738 c = get_symbol_name (&reg_string);
4d1bb795
JB		 9739 symbolP = symbol_find (reg_string);
9740 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9741 {
9742 const expressionS *e = symbol_get_value_expression (symbolP);
9743
0398aac5 9744 know (e->X_op == O_register);
4eed87de 9745 know (e->X_add_number >= 0
c3fe08fa 9746 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9747 r = i386_regtab + e->X_add_number;
d3bb6b49
IT		 9748 if ((r->reg_flags & RegVRex))
9749 i.need_vrex = 1;
4d1bb795
JB		 9750 *end_op = input_line_pointer;
9751 }
9752 *input_line_pointer = c;
9753 input_line_pointer = save;
9754 }
9755 return r;
9756}
9757
9758int
9759i386_parse_name (char *name, expressionS *e, char *nextcharP)
9760{
9761 const reg_entry *r;
9762 char *end = input_line_pointer;
9763
9764 *end = *nextcharP;
9765 r = parse_register (name, &input_line_pointer);
9766 if (r && end <= input_line_pointer)
9767 {
9768 *nextcharP = *input_line_pointer;
9769 *input_line_pointer = 0;
9770 e->X_op = O_register;
9771 e->X_add_number = r - i386_regtab;
9772 return 1;
9773 }
9774 input_line_pointer = end;
9775 *end = 0;
ee86248c 9776 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9777}
9778
9779void
9780md_operand (expressionS *e)
9781{
ee86248c
JB		 9782 char *end;
9783 const reg_entry *r;
4d1bb795 9784
ee86248c
JB		 9785 switch (*input_line_pointer)
9786 {
9787 case REGISTER_PREFIX:
9788 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9789 if (r)
9790 {
9791 e->X_op = O_register;
9792 e->X_add_number = r - i386_regtab;
9793 input_line_pointer = end;
9794 }
ee86248c
JB		 9795 break;
9796
9797 case '[':
9c2799c2 9798 gas_assert (intel_syntax);
ee86248c
JB		 9799 end = input_line_pointer++;
9800 expression (e);
9801 if (*input_line_pointer == ']')
9802 {
9803 ++input_line_pointer;
9804 e->X_op_symbol = make_expr_symbol (e);
9805 e->X_add_symbol = NULL;
9806 e->X_add_number = 0;
9807 e->X_op = O_index;
9808 }
9809 else
9810 {
9811 e->X_op = O_absent;
9812 input_line_pointer = end;
9813 }
9814 break;
4d1bb795
JB		 9815 }
9816}
9817
252b5132 9818\f
4cc782b5 9819#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9820const char *md_shortopts = "kVQ:sqn";
252b5132 9821#else
12b55ccc 9822const char *md_shortopts = "qn";
252b5132 9823#endif
6e0b89ee 9824
3e73aa7c 9825#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9826#define OPTION_64 (OPTION_MD_BASE + 1)
9827#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9828#define OPTION_MARCH (OPTION_MD_BASE + 3)
9829#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9830#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9831#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9832#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9833#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9834#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9835#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9836#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9837#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9838#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9839#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9840#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9841#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9842#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9843#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 9844#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9845#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 9846#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 9847#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9848#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 9849#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
0cb4071e 9850#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
b3b91714 9851
99ad8390
NC		 9852struct option md_longopts[] =
9853{
3e73aa7c 9854 {"32", no_argument, NULL, OPTION_32},
321098a5 9855#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9856 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9857 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9858#endif
9859#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9860 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 9861 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 9862#endif
b3b91714 9863 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9864 {"march", required_argument, NULL, OPTION_MARCH},
9865 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9866 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9867 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9868 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9869 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9870 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9871 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9872 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9873 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9874 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9875 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9876 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9877 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9878# if defined (TE_PE) || defined (TE_PEP)
9879 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9880#endif
d1982f93 9881 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 9882 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 9883 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 9884 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 9885 {"mamd64", no_argument, NULL, OPTION_MAMD64},
9886 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 9887 {NULL, no_argument, NULL, 0}
9888};
9889size_t md_longopts_size = sizeof (md_longopts);
9890
9891int
17b9d67d 9892md_parse_option (int c, const char *arg)
252b5132 9893{
91d6fa6a 9894 unsigned int j;
293f5f65 9895 char *arch, *next, *saved;
9103f4f4 9896
252b5132
RH		 9897 switch (c)
9898 {
12b55ccc
L		 9899 case 'n':
9900 optimize_align_code = 0;
9901 break;
9902
a38cf1db
AM		 9903 case 'q':
9904 quiet_warnings = 1;
252b5132
RH		 9905 break;
9906
9907#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9908 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9909 should be emitted or not. FIXME: Not implemented. */
9910 case 'Q':
252b5132
RH		 9911 break;
9912
9913 /* -V: SVR4 argument to print version ID. */
9914 case 'V':
9915 print_version_id ();
9916 break;
9917
a38cf1db
AM		 9918 /* -k: Ignore for FreeBSD compatibility. */
9919 case 'k':
252b5132 9920 break;
4cc782b5
ILT		 9921
9922 case 's':
9923 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9924 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9925 break;
8dcea932
L		 9926
9927 case OPTION_MSHARED:
9928 shared = 1;
9929 break;
99ad8390 9930#endif
321098a5 9931#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9932 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9933 case OPTION_64:
9934 {
9935 const char **list, **l;
9936
3e73aa7c
JH		 9937 list = bfd_target_list ();
9938 for (l = list; *l != NULL; l++)
8620418b 9939 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9940 || strcmp (*l, "coff-x86-64") == 0
9941 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9942 || strcmp (*l, "pei-x86-64") == 0
9943 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9944 {
9945 default_arch = "x86_64";
9946 break;
9947 }
3e73aa7c 9948 if (*l == NULL)
2b5d6a91 9949 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9950 free (list);
9951 }
9952 break;
9953#endif
252b5132 9954
351f65ca 9955#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9956 case OPTION_X32:
351f65ca
L		 9957 if (IS_ELF)
9958 {
9959 const char **list, **l;
9960
9961 list = bfd_target_list ();
9962 for (l = list; *l != NULL; l++)
9963 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9964 {
9965 default_arch = "x86_64:32";
9966 break;
9967 }
9968 if (*l == NULL)
2b5d6a91 9969 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9970 free (list);
9971 }
9972 else
9973 as_fatal (_("32bit x86_64 is only supported for ELF"));
9974 break;
9975#endif
9976
6e0b89ee
AM		 9977 case OPTION_32:
9978 default_arch = "i386";
9979 break;
9980
b3b91714
AM		 9981 case OPTION_DIVIDE:
9982#ifdef SVR4_COMMENT_CHARS
9983 {
9984 char *n, *t;
9985 const char *s;
9986
add39d23 9987 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 9988 t = n;
9989 for (s = i386_comment_chars; *s != '\0'; s++)
9990 if (*s != '/')
9991 *t++ = *s;
9992 *t = '\0';
9993 i386_comment_chars = n;
9994 }
9995#endif
9996 break;
9997
9103f4f4 9998 case OPTION_MARCH:
293f5f65
L		 9999 saved = xstrdup (arg);
10000 arch = saved;
10001 /* Allow -march=+nosse. */
10002 if (*arch == '+')
10003 arch++;
6305a203 10004 do
9103f4f4 10005 {
6305a203 10006 if (*arch == '.')
2b5d6a91 10007 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10008 next = strchr (arch, '+');
10009 if (next)
10010 *next++ = '\0';
91d6fa6a 10011 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10012 {
91d6fa6a 10013 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 10014 {
6305a203 10015 /* Processor. */
1ded5609
JB		 10016 if (! cpu_arch[j].flags.bitfield.cpui386)
10017 continue;
10018
91d6fa6a 10019 cpu_arch_name = cpu_arch[j].name;
6305a203 10020 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 10021 cpu_arch_flags = cpu_arch[j].flags;
10022 cpu_arch_isa = cpu_arch[j].type;
10023 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 10024 if (!cpu_arch_tune_set)
10025 {
10026 cpu_arch_tune = cpu_arch_isa;
10027 cpu_arch_tune_flags = cpu_arch_isa_flags;
10028 }
10029 break;
10030 }
91d6fa6a
NC		 10031 else if (*cpu_arch [j].name == '.'
10032 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 10033 {
10034 /* ISA entension. */
10035 i386_cpu_flags flags;
309d3373 10036
293f5f65
L		 10037 flags = cpu_flags_or (cpu_arch_flags,
10038 cpu_arch[j].flags);
81486035 10039
5b64d091 10040 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 10041 {
10042 if (cpu_sub_arch_name)
10043 {
10044 char *name = cpu_sub_arch_name;
10045 cpu_sub_arch_name = concat (name,
91d6fa6a 10046 cpu_arch[j].name,
1bf57e9f 10047 (const char *) NULL);
6305a203
L		 10048 free (name);
10049 }
10050 else
91d6fa6a 10051 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 10052 cpu_arch_flags = flags;
a586129e 10053 cpu_arch_isa_flags = flags;
6305a203
L		 10054 }
10055 break;
ccc9c027 10056 }
9103f4f4 10057 }
6305a203 10058
293f5f65
L		 10059 if (j >= ARRAY_SIZE (cpu_arch))
10060 {
10061 /* Disable an ISA entension. */
10062 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10063 if (strcmp (arch, cpu_noarch [j].name) == 0)
10064 {
10065 i386_cpu_flags flags;
10066
10067 flags = cpu_flags_and_not (cpu_arch_flags,
10068 cpu_noarch[j].flags);
10069 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10070 {
10071 if (cpu_sub_arch_name)
10072 {
10073 char *name = cpu_sub_arch_name;
10074 cpu_sub_arch_name = concat (arch,
10075 (const char *) NULL);
10076 free (name);
10077 }
10078 else
10079 cpu_sub_arch_name = xstrdup (arch);
10080 cpu_arch_flags = flags;
10081 cpu_arch_isa_flags = flags;
10082 }
10083 break;
10084 }
10085
10086 if (j >= ARRAY_SIZE (cpu_noarch))
10087 j = ARRAY_SIZE (cpu_arch);
10088 }
10089
91d6fa6a 10090 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10091 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10092
10093 arch = next;
9103f4f4 10094 }
293f5f65
L		 10095 while (next != NULL);
10096 free (saved);
9103f4f4
L		 10097 break;
10098
10099 case OPTION_MTUNE:
10100 if (*arg == '.')
2b5d6a91 10101 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 10102 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10103 {
91d6fa6a 10104 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 10105 {
ccc9c027 10106 cpu_arch_tune_set = 1;
91d6fa6a
NC		 10107 cpu_arch_tune = cpu_arch [j].type;
10108 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 10109 break;
10110 }
10111 }
91d6fa6a 10112 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10113 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 10114 break;
10115
1efbbeb4
L		 10116 case OPTION_MMNEMONIC:
10117 if (strcasecmp (arg, "att") == 0)
10118 intel_mnemonic = 0;
10119 else if (strcasecmp (arg, "intel") == 0)
10120 intel_mnemonic = 1;
10121 else
2b5d6a91 10122 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 10123 break;
10124
10125 case OPTION_MSYNTAX:
10126 if (strcasecmp (arg, "att") == 0)
10127 intel_syntax = 0;
10128 else if (strcasecmp (arg, "intel") == 0)
10129 intel_syntax = 1;
10130 else
2b5d6a91 10131 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 10132 break;
10133
10134 case OPTION_MINDEX_REG:
10135 allow_index_reg = 1;
10136 break;
10137
10138 case OPTION_MNAKED_REG:
10139 allow_naked_reg = 1;
10140 break;
10141
10142 case OPTION_MOLD_GCC:
10143 old_gcc = 1;
1efbbeb4
L		 10144 break;
10145
c0f3af97
L		 10146 case OPTION_MSSE2AVX:
10147 sse2avx = 1;
10148 break;
10149
daf50ae7
L		 10150 case OPTION_MSSE_CHECK:
10151 if (strcasecmp (arg, "error") == 0)
7bab8ab5 10152 sse_check = check_error;
daf50ae7 10153 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 10154 sse_check = check_warning;
daf50ae7 10155 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10156 sse_check = check_none;
daf50ae7 10157 else
2b5d6a91 10158 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10159 break;
10160
7bab8ab5
JB		 10161 case OPTION_MOPERAND_CHECK:
10162 if (strcasecmp (arg, "error") == 0)
10163 operand_check = check_error;
10164 else if (strcasecmp (arg, "warning") == 0)
10165 operand_check = check_warning;
10166 else if (strcasecmp (arg, "none") == 0)
10167 operand_check = check_none;
10168 else
10169 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10170 break;
10171
539f890d
L		 10172 case OPTION_MAVXSCALAR:
10173 if (strcasecmp (arg, "128") == 0)
10174 avxscalar = vex128;
10175 else if (strcasecmp (arg, "256") == 0)
10176 avxscalar = vex256;
10177 else
2b5d6a91 10178 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10179 break;
10180
7e8b059b
L		 10181 case OPTION_MADD_BND_PREFIX:
10182 add_bnd_prefix = 1;
10183 break;
10184
43234a1e
L		 10185 case OPTION_MEVEXLIG:
10186 if (strcmp (arg, "128") == 0)
10187 evexlig = evexl128;
10188 else if (strcmp (arg, "256") == 0)
10189 evexlig = evexl256;
10190 else if (strcmp (arg, "512") == 0)
10191 evexlig = evexl512;
10192 else
10193 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10194 break;
10195
d3d3c6db
IT		 10196 case OPTION_MEVEXRCIG:
10197 if (strcmp (arg, "rne") == 0)
10198 evexrcig = rne;
10199 else if (strcmp (arg, "rd") == 0)
10200 evexrcig = rd;
10201 else if (strcmp (arg, "ru") == 0)
10202 evexrcig = ru;
10203 else if (strcmp (arg, "rz") == 0)
10204 evexrcig = rz;
10205 else
10206 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10207 break;
10208
43234a1e
L		 10209 case OPTION_MEVEXWIG:
10210 if (strcmp (arg, "0") == 0)
10211 evexwig = evexw0;
10212 else if (strcmp (arg, "1") == 0)
10213 evexwig = evexw1;
10214 else
10215 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10216 break;
10217
167ad85b
TG		 10218# if defined (TE_PE) || defined (TE_PEP)
10219 case OPTION_MBIG_OBJ:
10220 use_big_obj = 1;
10221 break;
10222#endif
10223
d1982f93 10224 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10225 if (strcasecmp (arg, "yes") == 0)
10226 omit_lock_prefix = 1;
10227 else if (strcasecmp (arg, "no") == 0)
10228 omit_lock_prefix = 0;
10229 else
10230 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10231 break;
10232
e4e00185
AS		 10233 case OPTION_MFENCE_AS_LOCK_ADD:
10234 if (strcasecmp (arg, "yes") == 0)
10235 avoid_fence = 1;
10236 else if (strcasecmp (arg, "no") == 0)
10237 avoid_fence = 0;
10238 else
10239 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10240 break;
10241
0cb4071e
L		 10242 case OPTION_MRELAX_RELOCATIONS:
10243 if (strcasecmp (arg, "yes") == 0)
10244 generate_relax_relocations = 1;
10245 else if (strcasecmp (arg, "no") == 0)
10246 generate_relax_relocations = 0;
10247 else
10248 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10249 break;
10250
5db04b09 10251 case OPTION_MAMD64:
e89c5eaa 10252 intel64 = 0;
5db04b09
L		 10253 break;
10254
10255 case OPTION_MINTEL64:
e89c5eaa 10256 intel64 = 1;
5db04b09
L		 10257 break;
10258
252b5132
RH		 10259 default:
10260 return 0;
10261 }
10262 return 1;
10263}
10264
8a2c8fef
L		 10265#define MESSAGE_TEMPLATE \
10266" "
10267
293f5f65
L		 10268static char *
10269output_message (FILE *stream, char *p, char *message, char *start,
10270 int *left_p, const char *name, int len)
10271{
10272 int size = sizeof (MESSAGE_TEMPLATE);
10273 int left = *left_p;
10274
10275 /* Reserve 2 spaces for ", " or ",\0" */
10276 left -= len + 2;
10277
10278 /* Check if there is any room. */
10279 if (left >= 0)
10280 {
10281 if (p != start)
10282 {
10283 *p++ = ',';
10284 *p++ = ' ';
10285 }
10286 p = mempcpy (p, name, len);
10287 }
10288 else
10289 {
10290 /* Output the current message now and start a new one. */
10291 *p++ = ',';
10292 *p = '\0';
10293 fprintf (stream, "%s\n", message);
10294 p = start;
10295 left = size - (start - message) - len - 2;
10296
10297 gas_assert (left >= 0);
10298
10299 p = mempcpy (p, name, len);
10300 }
10301
10302 *left_p = left;
10303 return p;
10304}
10305
8a2c8fef 10306static void
1ded5609 10307show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10308{
10309 static char message[] = MESSAGE_TEMPLATE;
10310 char *start = message + 27;
10311 char *p;
10312 int size = sizeof (MESSAGE_TEMPLATE);
10313 int left;
10314 const char *name;
10315 int len;
10316 unsigned int j;
10317
10318 p = start;
10319 left = size - (start - message);
10320 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10321 {
10322 /* Should it be skipped? */
10323 if (cpu_arch [j].skip)
10324 continue;
10325
10326 name = cpu_arch [j].name;
10327 len = cpu_arch [j].len;
10328 if (*name == '.')
10329 {
10330 /* It is an extension. Skip if we aren't asked to show it. */
10331 if (ext)
10332 {
10333 name++;
10334 len--;
10335 }
10336 else
10337 continue;
10338 }
10339 else if (ext)
10340 {
10341 /* It is an processor. Skip if we show only extension. */
10342 continue;
10343 }
1ded5609
JB		 10344 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10345 {
10346 /* It is an impossible processor - skip. */
10347 continue;
10348 }
8a2c8fef 10349
293f5f65 10350 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 10351 }
10352
293f5f65
L		 10353 /* Display disabled extensions. */
10354 if (ext)
10355 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10356 {
10357 name = cpu_noarch [j].name;
10358 len = cpu_noarch [j].len;
10359 p = output_message (stream, p, message, start, &left, name,
10360 len);
10361 }
10362
8a2c8fef
L		 10363 *p = '\0';
10364 fprintf (stream, "%s\n", message);
10365}
10366
252b5132 10367void
8a2c8fef 10368md_show_usage (FILE *stream)
252b5132 10369{
4cc782b5
ILT		 10370#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10371 fprintf (stream, _("\
a38cf1db
AM		 10372 -Q ignored\n\
10373 -V print assembler version number\n\
b3b91714
AM		 10374 -k ignored\n"));
10375#endif
10376 fprintf (stream, _("\
12b55ccc 10377 -n Do not optimize code alignment\n\
b3b91714
AM		 10378 -q quieten some warnings\n"));
10379#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10380 fprintf (stream, _("\
a38cf1db 10381 -s ignored\n"));
b3b91714 10382#endif
321098a5
L		 10383#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10384 || defined (TE_PE) || defined (TE_PEP))
751d281c 10385 fprintf (stream, _("\
570561f7 10386 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10387#endif
b3b91714
AM		 10388#ifdef SVR4_COMMENT_CHARS
10389 fprintf (stream, _("\
10390 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10391#else
10392 fprintf (stream, _("\
b3b91714 10393 --divide ignored\n"));
4cc782b5 10394#endif
9103f4f4 10395 fprintf (stream, _("\
6305a203 10396 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10397 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10398 show_arch (stream, 0, 1);
8a2c8fef
L		 10399 fprintf (stream, _("\
10400 EXTENSION is combination of:\n"));
1ded5609 10401 show_arch (stream, 1, 0);
6305a203 10402 fprintf (stream, _("\
8a2c8fef 10403 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10404 show_arch (stream, 0, 0);
ba104c83 10405 fprintf (stream, _("\
c0f3af97
L		 10406 -msse2avx encode SSE instructions with VEX prefix\n"));
10407 fprintf (stream, _("\
daf50ae7
L		 10408 -msse-check=[none|error|warning]\n\
10409 check SSE instructions\n"));
10410 fprintf (stream, _("\
7bab8ab5
JB		 10411 -moperand-check=[none|error|warning]\n\
10412 check operand combinations for validity\n"));
10413 fprintf (stream, _("\
539f890d
L		 10414 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10415 length\n"));
10416 fprintf (stream, _("\
43234a1e
L		 10417 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10418 length\n"));
10419 fprintf (stream, _("\
10420 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10421 for EVEX.W bit ignored instructions\n"));
10422 fprintf (stream, _("\
d3d3c6db
IT		 10423 -mevexrcig=[rne|rd|ru|rz]\n\
10424 encode EVEX instructions with specific EVEX.RC value\n\
10425 for SAE-only ignored instructions\n"));
10426 fprintf (stream, _("\
ba104c83
L		 10427 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10428 fprintf (stream, _("\
10429 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10430 fprintf (stream, _("\
10431 -mindex-reg support pseudo index registers\n"));
10432 fprintf (stream, _("\
10433 -mnaked-reg don't require `%%' prefix for registers\n"));
10434 fprintf (stream, _("\
10435 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10436 fprintf (stream, _("\
10437 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10438 fprintf (stream, _("\
10439 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10440# if defined (TE_PE) || defined (TE_PEP)
10441 fprintf (stream, _("\
10442 -mbig-obj generate big object files\n"));
10443#endif
d022bddd
IT		 10444 fprintf (stream, _("\
10445 -momit-lock-prefix=[no|yes]\n\
10446 strip all lock prefixes\n"));
5db04b09 10447 fprintf (stream, _("\
e4e00185
AS		 10448 -mfence-as-lock-add=[no|yes]\n\
10449 encode lfence, mfence and sfence as\n\
10450 lock addl $0x0, (%%{re}sp)\n"));
10451 fprintf (stream, _("\
0cb4071e
L		 10452 -mrelax-relocations=[no|yes]\n\
10453 generate relax relocations\n"));
10454 fprintf (stream, _("\
5db04b09
L		 10455 -mamd64 accept only AMD64 ISA\n"));
10456 fprintf (stream, _("\
10457 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10458}
10459
3e73aa7c 10460#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10461 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10462 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10463
10464/* Pick the target format to use. */
10465
47926f60 10466const char *
e3bb37b5 10467i386_target_format (void)
252b5132 10468{
351f65ca
L		 10469 if (!strncmp (default_arch, "x86_64", 6))
10470 {
10471 update_code_flag (CODE_64BIT, 1);
10472 if (default_arch[6] == '\0')
7f56bc95 10473 x86_elf_abi = X86_64_ABI;
351f65ca 10474 else
7f56bc95 10475 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10476 }
3e73aa7c 10477 else if (!strcmp (default_arch, "i386"))
78f12dd3 10478 update_code_flag (CODE_32BIT, 1);
5197d474
L		 10479 else if (!strcmp (default_arch, "iamcu"))
10480 {
10481 update_code_flag (CODE_32BIT, 1);
10482 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10483 {
10484 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10485 cpu_arch_name = "iamcu";
10486 cpu_sub_arch_name = NULL;
10487 cpu_arch_flags = iamcu_flags;
10488 cpu_arch_isa = PROCESSOR_IAMCU;
10489 cpu_arch_isa_flags = iamcu_flags;
10490 if (!cpu_arch_tune_set)
10491 {
10492 cpu_arch_tune = cpu_arch_isa;
10493 cpu_arch_tune_flags = cpu_arch_isa_flags;
10494 }
10495 }
8d471ec1 10496 else if (cpu_arch_isa != PROCESSOR_IAMCU)
5197d474
L		 10497 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10498 cpu_arch_name);
10499 }
3e73aa7c 10500 else
2b5d6a91 10501 as_fatal (_("unknown architecture"));
89507696
JB		 10502
10503 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10504 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10505 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10506 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10507
252b5132
RH		 10508 switch (OUTPUT_FLAVOR)
10509 {
9384f2ff 10510#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10511 case bfd_target_aout_flavour:
47926f60 10512 return AOUT_TARGET_FORMAT;
4c63da97 10513#endif
9384f2ff
AM		 10514#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10515# if defined (TE_PE) || defined (TE_PEP)
10516 case bfd_target_coff_flavour:
167ad85b
TG		 10517 if (flag_code == CODE_64BIT)
10518 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10519 else
10520 return "pe-i386";
9384f2ff 10521# elif defined (TE_GO32)
0561d57c
JK		 10522 case bfd_target_coff_flavour:
10523 return "coff-go32";
9384f2ff 10524# else
252b5132
RH		 10525 case bfd_target_coff_flavour:
10526 return "coff-i386";
9384f2ff 10527# endif
4c63da97 10528#endif
3e73aa7c 10529#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10530 case bfd_target_elf_flavour:
3e73aa7c 10531 {
351f65ca
L		 10532 const char *format;
10533
10534 switch (x86_elf_abi)
4fa24527 10535 {
351f65ca
L		 10536 default:
10537 format = ELF_TARGET_FORMAT;
10538 break;
7f56bc95 10539 case X86_64_ABI:
351f65ca 10540 use_rela_relocations = 1;
4fa24527 10541 object_64bit = 1;
351f65ca
L		 10542 format = ELF_TARGET_FORMAT64;
10543 break;
7f56bc95 10544 case X86_64_X32_ABI:
4fa24527 10545 use_rela_relocations = 1;
351f65ca 10546 object_64bit = 1;
862be3fb 10547 disallow_64bit_reloc = 1;
351f65ca
L		 10548 format = ELF_TARGET_FORMAT32;
10549 break;
4fa24527 10550 }
3632d14b 10551 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10552 {
7f56bc95 10553 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10554 as_fatal (_("Intel L1OM is 64bit only"));
10555 return ELF_TARGET_L1OM_FORMAT;
10556 }
b49f93f6 10557 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 10558 {
10559 if (x86_elf_abi != X86_64_ABI)
10560 as_fatal (_("Intel K1OM is 64bit only"));
10561 return ELF_TARGET_K1OM_FORMAT;
10562 }
81486035
L		 10563 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10564 {
10565 if (x86_elf_abi != I386_ABI)
10566 as_fatal (_("Intel MCU is 32bit only"));
10567 return ELF_TARGET_IAMCU_FORMAT;
10568 }
8a9036a4 10569 else
351f65ca 10570 return format;
3e73aa7c 10571 }
e57f8c65
TG		 10572#endif
10573#if defined (OBJ_MACH_O)
10574 case bfd_target_mach_o_flavour:
d382c579
TG		 10575 if (flag_code == CODE_64BIT)
10576 {
10577 use_rela_relocations = 1;
10578 object_64bit = 1;
10579 return "mach-o-x86-64";
10580 }
10581 else
10582 return "mach-o-i386";
4c63da97 10583#endif
252b5132
RH		 10584 default:
10585 abort ();
10586 return NULL;
10587 }
10588}
10589
47926f60 10590#endif /* OBJ_MAYBE_ more than one */
252b5132 10591\f
252b5132 10592symbolS *
7016a5d5 10593md_undefined_symbol (char *name)
252b5132 10594{
18dc2407
ILT		 10595 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10596 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10597 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10598 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10599 {
10600 if (!GOT_symbol)
10601 {
10602 if (symbol_find (name))
10603 as_bad (_("GOT already in symbol table"));
10604 GOT_symbol = symbol_new (name, undefined_section,
10605 (valueT) 0, &zero_address_frag);
10606 };
10607 return GOT_symbol;
10608 }
252b5132
RH		 10609 return 0;
10610}
10611
10612/* Round up a section size to the appropriate boundary. */
47926f60 10613
252b5132 10614valueT
7016a5d5 10615md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10616{
4c63da97
AM		 10617#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10618 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10619 {
10620 /* For a.out, force the section size to be aligned. If we don't do
10621 this, BFD will align it for us, but it will not write out the
10622 final bytes of the section. This may be a bug in BFD, but it is
10623 easier to fix it here since that is how the other a.out targets
10624 work. */
10625 int align;
10626
10627 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 10628 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 10629 }
252b5132
RH		 10630#endif
10631
10632 return size;
10633}
10634
10635/* On the i386, PC-relative offsets are relative to the start of the
10636 next instruction. That is, the address of the offset, plus its
10637 size, since the offset is always the last part of the insn. */
10638
10639long
e3bb37b5 10640md_pcrel_from (fixS *fixP)
252b5132
RH		 10641{
10642 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10643}
10644
10645#ifndef I386COFF
10646
10647static void
e3bb37b5 10648s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10649{
29b0f896 10650 int temp;
252b5132 10651
8a75718c
JB		 10652#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10653 if (IS_ELF)
10654 obj_elf_section_change_hook ();
10655#endif
252b5132
RH		 10656 temp = get_absolute_expression ();
10657 subseg_set (bss_section, (subsegT) temp);
10658 demand_empty_rest_of_line ();
10659}
10660
10661#endif
10662
252b5132 10663void
e3bb37b5 10664i386_validate_fix (fixS *fixp)
252b5132 10665{
02a86693 10666 if (fixp->fx_subsy)
252b5132 10667 {
02a86693 10668 if (fixp->fx_subsy == GOT_symbol)
23df1078 10669 {
02a86693
L		 10670 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10671 {
10672 if (!object_64bit)
10673 abort ();
10674#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10675 if (fixp->fx_tcbit2)
56ceb5b5
L		 10676 fixp->fx_r_type = (fixp->fx_tcbit
10677 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10678 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 10679 else
10680#endif
10681 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10682 }
d6ab8113 10683 else
02a86693
L		 10684 {
10685 if (!object_64bit)
10686 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10687 else
10688 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10689 }
10690 fixp->fx_subsy = 0;
23df1078 10691 }
252b5132 10692 }
02a86693
L		 10693#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10694 else if (!object_64bit)
10695 {
10696 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
10697 && fixp->fx_tcbit2)
10698 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
10699 }
10700#endif
252b5132
RH		 10701}
10702
252b5132 10703arelent *
7016a5d5 10704tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10705{
10706 arelent *rel;
10707 bfd_reloc_code_real_type code;
10708
10709 switch (fixp->fx_r_type)
10710 {
8ce3d284 10711#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10712 case BFD_RELOC_SIZE32:
10713 case BFD_RELOC_SIZE64:
10714 if (S_IS_DEFINED (fixp->fx_addsy)
10715 && !S_IS_EXTERNAL (fixp->fx_addsy))
10716 {
10717 /* Resolve size relocation against local symbol to size of
10718 the symbol plus addend. */
10719 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10720 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10721 && !fits_in_unsigned_long (value))
10722 as_bad_where (fixp->fx_file, fixp->fx_line,
10723 _("symbol size computation overflow"));
10724 fixp->fx_addsy = NULL;
10725 fixp->fx_subsy = NULL;
10726 md_apply_fix (fixp, (valueT *) &value, NULL);
10727 return NULL;
10728 }
8ce3d284 10729#endif
1a0670f3 10730 /* Fall through. */
8fd4256d 10731
3e73aa7c
JH		 10732 case BFD_RELOC_X86_64_PLT32:
10733 case BFD_RELOC_X86_64_GOT32:
10734 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10735 case BFD_RELOC_X86_64_GOTPCRELX:
10736 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 10737 case BFD_RELOC_386_PLT32:
10738 case BFD_RELOC_386_GOT32:
02a86693 10739 case BFD_RELOC_386_GOT32X:
252b5132
RH		 10740 case BFD_RELOC_386_GOTOFF:
10741 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10742 case BFD_RELOC_386_TLS_GD:
10743 case BFD_RELOC_386_TLS_LDM:
10744 case BFD_RELOC_386_TLS_LDO_32:
10745 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10746 case BFD_RELOC_386_TLS_IE:
10747 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10748 case BFD_RELOC_386_TLS_LE_32:
10749 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10750 case BFD_RELOC_386_TLS_GOTDESC:
10751 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10752 case BFD_RELOC_X86_64_TLSGD:
10753 case BFD_RELOC_X86_64_TLSLD:
10754 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10755 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10756 case BFD_RELOC_X86_64_GOTTPOFF:
10757 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10758 case BFD_RELOC_X86_64_TPOFF64:
10759 case BFD_RELOC_X86_64_GOTOFF64:
10760 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10761 case BFD_RELOC_X86_64_GOT64:
10762 case BFD_RELOC_X86_64_GOTPCREL64:
10763 case BFD_RELOC_X86_64_GOTPC64:
10764 case BFD_RELOC_X86_64_GOTPLT64:
10765 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10766 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10767 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10768 case BFD_RELOC_RVA:
10769 case BFD_RELOC_VTABLE_ENTRY:
10770 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10771#ifdef TE_PE
10772 case BFD_RELOC_32_SECREL:
10773#endif
252b5132
RH		 10774 code = fixp->fx_r_type;
10775 break;
dbbaec26
L		 10776 case BFD_RELOC_X86_64_32S:
10777 if (!fixp->fx_pcrel)
10778 {
10779 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10780 code = fixp->fx_r_type;
10781 break;
10782 }
1a0670f3 10783 /* Fall through. */
252b5132 10784 default:
93382f6d 10785 if (fixp->fx_pcrel)
252b5132 10786 {
93382f6d
AM		 10787 switch (fixp->fx_size)
10788 {
10789 default:
b091f402
AM		 10790 as_bad_where (fixp->fx_file, fixp->fx_line,
10791 _("can not do %d byte pc-relative relocation"),
10792 fixp->fx_size);
93382f6d
AM		 10793 code = BFD_RELOC_32_PCREL;
10794 break;
10795 case 1: code = BFD_RELOC_8_PCREL; break;
10796 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10797 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10798#ifdef BFD64
10799 case 8: code = BFD_RELOC_64_PCREL; break;
10800#endif
93382f6d
AM		 10801 }
10802 }
10803 else
10804 {
10805 switch (fixp->fx_size)
10806 {
10807 default:
b091f402
AM		 10808 as_bad_where (fixp->fx_file, fixp->fx_line,
10809 _("can not do %d byte relocation"),
10810 fixp->fx_size);
93382f6d
AM		 10811 code = BFD_RELOC_32;
10812 break;
10813 case 1: code = BFD_RELOC_8; break;
10814 case 2: code = BFD_RELOC_16; break;
10815 case 4: code = BFD_RELOC_32; break;
937149dd 10816#ifdef BFD64
3e73aa7c 10817 case 8: code = BFD_RELOC_64; break;
937149dd 10818#endif
93382f6d 10819 }
252b5132
RH		 10820 }
10821 break;
10822 }
252b5132 10823
d182319b
JB		 10824 if ((code == BFD_RELOC_32
10825 || code == BFD_RELOC_32_PCREL
10826 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10827 && GOT_symbol
10828 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10829 {
4fa24527 10830 if (!object_64bit)
d6ab8113
JB		 10831 code = BFD_RELOC_386_GOTPC;
10832 else
10833 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10834 }
7b81dfbb
AJ		 10835 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10836 && GOT_symbol
10837 && fixp->fx_addsy == GOT_symbol)
10838 {
10839 code = BFD_RELOC_X86_64_GOTPC64;
10840 }
252b5132 10841
add39d23
TS		 10842 rel = XNEW (arelent);
10843 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 10844 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10845
10846 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10847
3e73aa7c
JH		 10848 if (!use_rela_relocations)
10849 {
10850 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10851 vtable entry to be used in the relocation's section offset. */
10852 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10853 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10854#if defined (OBJ_COFF) && defined (TE_PE)
10855 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10856 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10857 else
10858#endif
c6682705 10859 rel->addend = 0;
3e73aa7c
JH		 10860 }
10861 /* Use the rela in 64bit mode. */
252b5132 10862 else
3e73aa7c 10863 {
862be3fb
L		 10864 if (disallow_64bit_reloc)
10865 switch (code)
10866 {
862be3fb
L		 10867 case BFD_RELOC_X86_64_DTPOFF64:
10868 case BFD_RELOC_X86_64_TPOFF64:
10869 case BFD_RELOC_64_PCREL:
10870 case BFD_RELOC_X86_64_GOTOFF64:
10871 case BFD_RELOC_X86_64_GOT64:
10872 case BFD_RELOC_X86_64_GOTPCREL64:
10873 case BFD_RELOC_X86_64_GOTPC64:
10874 case BFD_RELOC_X86_64_GOTPLT64:
10875 case BFD_RELOC_X86_64_PLTOFF64:
10876 as_bad_where (fixp->fx_file, fixp->fx_line,
10877 _("cannot represent relocation type %s in x32 mode"),
10878 bfd_get_reloc_code_name (code));
10879 break;
10880 default:
10881 break;
10882 }
10883
062cd5e7
AS		 10884 if (!fixp->fx_pcrel)
10885 rel->addend = fixp->fx_offset;
10886 else
10887 switch (code)
10888 {
10889 case BFD_RELOC_X86_64_PLT32:
10890 case BFD_RELOC_X86_64_GOT32:
10891 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10892 case BFD_RELOC_X86_64_GOTPCRELX:
10893 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 10894 case BFD_RELOC_X86_64_TLSGD:
10895 case BFD_RELOC_X86_64_TLSLD:
10896 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10897 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10898 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10899 rel->addend = fixp->fx_offset - fixp->fx_size;
10900 break;
10901 default:
10902 rel->addend = (section->vma
10903 - fixp->fx_size
10904 + fixp->fx_addnumber
10905 + md_pcrel_from (fixp));
10906 break;
10907 }
3e73aa7c
JH		 10908 }
10909
252b5132
RH		 10910 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10911 if (rel->howto == NULL)
10912 {
10913 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10914 _("cannot represent relocation type %s"),
252b5132
RH		 10915 bfd_get_reloc_code_name (code));
10916 /* Set howto to a garbage value so that we can keep going. */
10917 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10918 gas_assert (rel->howto != NULL);
252b5132
RH		 10919 }
10920
10921 return rel;
10922}
10923
ee86248c 10924#include "tc-i386-intel.c"
54cfded0 10925
a60de03c
JB		 10926void
10927tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10928{
a60de03c
JB		 10929 int saved_naked_reg;
10930 char saved_register_dot;
54cfded0 10931
a60de03c
JB		 10932 saved_naked_reg = allow_naked_reg;
10933 allow_naked_reg = 1;
10934 saved_register_dot = register_chars['.'];
10935 register_chars['.'] = '.';
10936 allow_pseudo_reg = 1;
10937 expression_and_evaluate (exp);
10938 allow_pseudo_reg = 0;
10939 register_chars['.'] = saved_register_dot;
10940 allow_naked_reg = saved_naked_reg;
10941
e96d56a1 10942 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10943 {
a60de03c
JB		 10944 if ((addressT) exp->X_add_number < i386_regtab_size)
10945 {
10946 exp->X_op = O_constant;
10947 exp->X_add_number = i386_regtab[exp->X_add_number]
10948 .dw2_regnum[flag_code >> 1];
10949 }
10950 else
10951 exp->X_op = O_illegal;
54cfded0 10952 }
54cfded0
AM		 10953}
10954
10955void
10956tc_x86_frame_initial_instructions (void)
10957{
a60de03c
JB		 10958 static unsigned int sp_regno[2];
10959
10960 if (!sp_regno[flag_code >> 1])
10961 {
10962 char *saved_input = input_line_pointer;
10963 char sp[][4] = {"esp", "rsp"};
10964 expressionS exp;
a4447b93 10965
a60de03c
JB		 10966 input_line_pointer = sp[flag_code >> 1];
10967 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10968 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10969 sp_regno[flag_code >> 1] = exp.X_add_number;
10970 input_line_pointer = saved_input;
10971 }
a4447b93 10972
61ff971f
L		 10973 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10974 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10975}
d2b2c203 10976
d7921315
L		 10977int
10978x86_dwarf2_addr_size (void)
10979{
10980#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10981 if (x86_elf_abi == X86_64_X32_ABI)
10982 return 4;
10983#endif
10984 return bfd_arch_bits_per_address (stdoutput) / 8;
10985}
10986
d2b2c203
DJ		 10987int
10988i386_elf_section_type (const char *str, size_t len)
10989{
10990 if (flag_code == CODE_64BIT
10991 && len == sizeof ("unwind") - 1
10992 && strncmp (str, "unwind", 6) == 0)
10993 return SHT_X86_64_UNWIND;
10994
10995 return -1;
10996}
bb41ade5 10997
ad5fec3b
EB		 10998#ifdef TE_SOLARIS
10999void
11000i386_solaris_fix_up_eh_frame (segT sec)
11001{
11002 if (flag_code == CODE_64BIT)
11003 elf_section_type (sec) = SHT_X86_64_UNWIND;
11004}
11005#endif
11006
bb41ade5
AM		 11007#ifdef TE_PE
11008void
11009tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11010{
91d6fa6a 11011 expressionS exp;
bb41ade5 11012
91d6fa6a
NC		 11013 exp.X_op = O_secrel;
11014 exp.X_add_symbol = symbol;
11015 exp.X_add_number = 0;
11016 emit_expr (&exp, size);
bb41ade5
AM		 11017}
11018#endif
3b22753a
L		 11019
11020#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11021/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11022
01e1a5bc 11023bfd_vma
6d4af3c2 11024x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 11025{
11026 if (flag_code == CODE_64BIT)
11027 {
11028 if (letter == 'l')
11029 return SHF_X86_64_LARGE;
11030
8f3bae45 11031 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 11032 }
3b22753a 11033 else
8f3bae45 11034 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 11035 return -1;
11036}
11037
01e1a5bc 11038bfd_vma
3b22753a
L		 11039x86_64_section_word (char *str, size_t len)
11040{
8620418b 11041 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 11042 return SHF_X86_64_LARGE;
11043
11044 return -1;
11045}
11046
11047static void
11048handle_large_common (int small ATTRIBUTE_UNUSED)
11049{
11050 if (flag_code != CODE_64BIT)
11051 {
11052 s_comm_internal (0, elf_common_parse);
11053 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11054 }
11055 else
11056 {
11057 static segT lbss_section;
11058 asection *saved_com_section_ptr = elf_com_section_ptr;
11059 asection *saved_bss_section = bss_section;
11060
11061 if (lbss_section == NULL)
11062 {
11063 flagword applicable;
11064 segT seg = now_seg;
11065 subsegT subseg = now_subseg;
11066
11067 /* The .lbss section is for local .largecomm symbols. */
11068 lbss_section = subseg_new (".lbss", 0);
11069 applicable = bfd_applicable_section_flags (stdoutput);
11070 bfd_set_section_flags (stdoutput, lbss_section,
11071 applicable & SEC_ALLOC);
11072 seg_info (lbss_section)->bss = 1;
11073
11074 subseg_set (seg, subseg);
11075 }
11076
11077 elf_com_section_ptr = &_bfd_elf_large_com_section;
11078 bss_section = lbss_section;
11079
11080 s_comm_internal (0, elf_common_parse);
11081
11082 elf_com_section_ptr = saved_com_section_ptr;
11083 bss_section = saved_bss_section;
11084 }
11085}
11086#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
This page took 1.915551 seconds and 4 git commands to generate.