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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4dc85607 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
e3bb37b5
L		 66static void set_code_flag (int);
67static void set_16bit_gcc_code_flag (int);
68static void set_intel_syntax (int);
69static void set_cpu_arch (int);
6482c264 70#ifdef TE_PE
e3bb37b5 71static void pe_directive_secrel (int);
6482c264 72#endif
e3bb37b5
L		 73static void signed_cons (int);
74static char *output_invalid (int c);
75static int i386_operand (char *);
76static int i386_intel_operand (char *, int);
77static const reg_entry *parse_register (char *, char **);
78static char *parse_insn (char *, char *);
79static char *parse_operands (char *, const char *);
80static void swap_operands (void);
4d456e3d 81static void swap_2_operands (int, int);
e3bb37b5
L		 82static void optimize_imm (void);
83static void optimize_disp (void);
84static int match_template (void);
85static int check_string (void);
86static int process_suffix (void);
87static int check_byte_reg (void);
88static int check_long_reg (void);
89static int check_qword_reg (void);
90static int check_word_reg (void);
91static int finalize_imm (void);
85f10a01 92static void process_drex (void);
e3bb37b5
L		 93static int process_operands (void);
94static const seg_entry *build_modrm_byte (void);
95static void output_insn (void);
96static void output_imm (fragS *, offsetT);
97static void output_disp (fragS *, offsetT);
29b0f896 98#ifndef I386COFF
e3bb37b5 99static void s_bss (int);
252b5132 100#endif
17d4e2a2
L		 101#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
102static void handle_large_common (int small ATTRIBUTE_UNUSED);
103#endif
252b5132 104
a847613f 105static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 106
252b5132 107/* 'md_assemble ()' gathers together information and puts it into a
47926f60 108 i386_insn. */
252b5132 109
520dc8e8
AM		 110union i386_op
111 {
112 expressionS *disps;
113 expressionS *imms;
114 const reg_entry *regs;
115 };
116
252b5132
RH		 117struct _i386_insn
118 {
47926f60 119 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 120 template tm;
121
122 /* SUFFIX holds the instruction mnemonic suffix if given.
123 (e.g. 'l' for 'movl') */
124 char suffix;
125
47926f60 126 /* OPERANDS gives the number of given operands. */
252b5132
RH		 127 unsigned int operands;
128
129 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
130 of given register, displacement, memory operands and immediate
47926f60 131 operands. */
252b5132
RH		 132 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
133
134 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 135 use OP[i] for the corresponding operand. */
40fb9820 136 i386_operand_type types[MAX_OPERANDS];
252b5132 137
520dc8e8
AM		 138 /* Displacement expression, immediate expression, or register for each
139 operand. */
140 union i386_op op[MAX_OPERANDS];
252b5132 141
3e73aa7c
JH		 142 /* Flags for operands. */
143 unsigned int flags[MAX_OPERANDS];
144#define Operand_PCrel 1
145
252b5132 146 /* Relocation type for operand */
f86103b7 147 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 148
252b5132
RH		 149 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
150 the base index byte below. */
151 const reg_entry *base_reg;
152 const reg_entry *index_reg;
153 unsigned int log2_scale_factor;
154
155 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 156 explicit segment overrides are given. */
ce8a8b2f 157 const seg_entry *seg[2];
252b5132
RH		 158
159 /* PREFIX holds all the given prefix opcodes (usually null).
160 PREFIXES is the number of prefix opcodes. */
161 unsigned int prefixes;
162 unsigned char prefix[MAX_PREFIXES];
163
164 /* RM and SIB are the modrm byte and the sib byte where the
85f10a01
MM		 165 addressing modes of this insn are encoded. DREX is the byte
166 added by the SSE5 instructions. */
252b5132
RH		 167
168 modrm_byte rm;
3e73aa7c 169 rex_byte rex;
252b5132 170 sib_byte sib;
85f10a01 171 drex_byte drex;
252b5132
RH		 172 };
173
174typedef struct _i386_insn i386_insn;
175
176/* List of chars besides those in app.c:symbol_chars that can start an
177 operand. Used to prevent the scrubber eating vital white-space. */
32137342 178const char extra_symbol_chars[] = "*%-(["
252b5132 179#ifdef LEX_AT
32137342
NC		 180 "@"
181#endif
182#ifdef LEX_QM
183 "?"
252b5132 184#endif
32137342 185 ;
252b5132 186
29b0f896
AM		 187#if (defined (TE_I386AIX) \
188 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 189 && !defined (TE_GNU) \
29b0f896 190 && !defined (TE_LINUX) \
32137342 191 && !defined (TE_NETWARE) \
29b0f896
AM		 192 && !defined (TE_FreeBSD) \
193 && !defined (TE_NetBSD)))
252b5132 194/* This array holds the chars that always start a comment. If the
b3b91714
AM		 195 pre-processor is disabled, these aren't very useful. The option
196 --divide will remove '/' from this list. */
197const char *i386_comment_chars = "#/";
198#define SVR4_COMMENT_CHARS 1
252b5132 199#define PREFIX_SEPARATOR '\\'
252b5132 200
b3b91714
AM		 201#else
202const char *i386_comment_chars = "#";
203#define PREFIX_SEPARATOR '/'
204#endif
205
252b5132
RH		 206/* This array holds the chars that only start a comment at the beginning of
207 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 208 .line and .file directives will appear in the pre-processed output.
209 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 210 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 211 #NO_APP at the beginning of its output.
212 Also note that comments started like this one will always work if
252b5132 213 '/' isn't otherwise defined. */
b3b91714 214const char line_comment_chars[] = "#/";
252b5132 215
63a0b638 216const char line_separator_chars[] = ";";
252b5132 217
ce8a8b2f
AM		 218/* Chars that can be used to separate mant from exp in floating point
219 nums. */
252b5132
RH		 220const char EXP_CHARS[] = "eE";
221
ce8a8b2f
AM		 222/* Chars that mean this number is a floating point constant
223 As in 0f12.456
224 or 0d1.2345e12. */
252b5132
RH		 225const char FLT_CHARS[] = "fFdDxX";
226
ce8a8b2f 227/* Tables for lexical analysis. */
252b5132
RH		 228static char mnemonic_chars[256];
229static char register_chars[256];
230static char operand_chars[256];
231static char identifier_chars[256];
232static char digit_chars[256];
233
ce8a8b2f 234/* Lexical macros. */
252b5132
RH		 235#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
236#define is_operand_char(x) (operand_chars[(unsigned char) x])
237#define is_register_char(x) (register_chars[(unsigned char) x])
238#define is_space_char(x) ((x) == ' ')
239#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
240#define is_digit_char(x) (digit_chars[(unsigned char) x])
241
0234cb7c 242/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 243static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
244
245/* md_assemble() always leaves the strings it's passed unaltered. To
246 effect this we maintain a stack of saved characters that we've smashed
247 with '\0's (indicating end of strings for various sub-fields of the
47926f60 248 assembler instruction). */
252b5132 249static char save_stack[32];
ce8a8b2f 250static char *save_stack_p;
252b5132
RH		 251#define END_STRING_AND_SAVE(s) \
252 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
253#define RESTORE_END_STRING(s) \
254 do { *(s) = *--save_stack_p; } while (0)
255
47926f60 256/* The instruction we're assembling. */
252b5132
RH		 257static i386_insn i;
258
259/* Possible templates for current insn. */
260static const templates *current_templates;
261
31b2323c
L		 262/* Per instruction expressionS buffers: max displacements & immediates. */
263static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
264static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 265
47926f60
KH		 266/* Current operand we are working on. */
267static int this_operand;
252b5132 268
3e73aa7c
JH		 269/* We support four different modes. FLAG_CODE variable is used to distinguish
270 these. */
271
272enum flag_code {
273 CODE_32BIT,
274 CODE_16BIT,
275 CODE_64BIT };
f3c180ae 276#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 277
278static enum flag_code flag_code;
4fa24527 279static unsigned int object_64bit;
3e73aa7c
JH		 280static int use_rela_relocations = 0;
281
282/* The names used to print error messages. */
b77a7acd 283static const char *flag_code_names[] =
3e73aa7c
JH		 284 {
285 "32",
286 "16",
287 "64"
288 };
252b5132 289
47926f60
KH		 290/* 1 for intel syntax,
291 0 if att syntax. */
292static int intel_syntax = 0;
252b5132 293
47926f60
KH		 294/* 1 if register prefix % not required. */
295static int allow_naked_reg = 0;
252b5132 296
2ca3ace5
L		 297/* Register prefix used for error message. */
298static const char *register_prefix = "%";
299
47926f60
KH		 300/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
301 leave, push, and pop instructions so that gcc has the same stack
302 frame as in 32 bit mode. */
303static char stackop_size = '\0';
eecb386c 304
12b55ccc
L		 305/* Non-zero to optimize code alignment. */
306int optimize_align_code = 1;
307
47926f60
KH		 308/* Non-zero to quieten some warnings. */
309static int quiet_warnings = 0;
a38cf1db 310
47926f60
KH		 311/* CPU name. */
312static const char *cpu_arch_name = NULL;
5c6af06e 313static const char *cpu_sub_arch_name = NULL;
a38cf1db 314
47926f60 315/* CPU feature flags. */
40fb9820
L		 316static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
317
318/* Bitwise NOT of cpu_arch_flags. */
319static i386_cpu_flags cpu_arch_flags_not;
a38cf1db 320
ccc9c027
L		 321/* If we have selected a cpu we are generating instructions for. */
322static int cpu_arch_tune_set = 0;
323
9103f4f4
L		 324/* Cpu we are generating instructions for. */
325static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
326
327/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 328static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 329
ccc9c027
L		 330/* CPU instruction set architecture used. */
331static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
332
9103f4f4 333/* CPU feature flags of instruction set architecture used. */
40fb9820 334static i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 335
fddf5b5b
AM		 336/* If set, conditional jumps are not automatically promoted to handle
337 larger than a byte offset. */
338static unsigned int no_cond_jump_promotion = 0;
339
29b0f896 340/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 341static symbolS *GOT_symbol;
29b0f896 342
a4447b93
RH		 343/* The dwarf2 return column, adjusted for 32 or 64 bit. */
344unsigned int x86_dwarf2_return_column;
345
346/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
347int x86_cie_data_alignment;
348
252b5132 349/* Interface to relax_segment.
fddf5b5b
AM		 350 There are 3 major relax states for 386 jump insns because the
351 different types of jumps add different sizes to frags when we're
352 figuring out what sort of jump to choose to reach a given label. */
252b5132 353
47926f60 354/* Types. */
93c2a809
AM		 355#define UNCOND_JUMP 0
356#define COND_JUMP 1
357#define COND_JUMP86 2
fddf5b5b 358
47926f60 359/* Sizes. */
252b5132
RH		 360#define CODE16 1
361#define SMALL 0
29b0f896 362#define SMALL16 (SMALL | CODE16)
252b5132 363#define BIG 2
29b0f896 364#define BIG16 (BIG | CODE16)
252b5132
RH		 365
366#ifndef INLINE
367#ifdef __GNUC__
368#define INLINE __inline__
369#else
370#define INLINE
371#endif
372#endif
373
fddf5b5b
AM		 374#define ENCODE_RELAX_STATE(type, size) \
375 ((relax_substateT) (((type) << 2) | (size)))
376#define TYPE_FROM_RELAX_STATE(s) \
377 ((s) >> 2)
378#define DISP_SIZE_FROM_RELAX_STATE(s) \
379 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 380
381/* This table is used by relax_frag to promote short jumps to long
382 ones where necessary. SMALL (short) jumps may be promoted to BIG
383 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
384 don't allow a short jump in a 32 bit code segment to be promoted to
385 a 16 bit offset jump because it's slower (requires data size
386 prefix), and doesn't work, unless the destination is in the bottom
387 64k of the code segment (The top 16 bits of eip are zeroed). */
388
389const relax_typeS md_relax_table[] =
390{
24eab124
AM		 391 /* The fields are:
392 1) most positive reach of this state,
393 2) most negative reach of this state,
93c2a809 394 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 395 4) which index into the table to try if we can't fit into this one. */
252b5132 396
fddf5b5b 397 /* UNCOND_JUMP states. */
93c2a809
AM		 398 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
399 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
400 /* dword jmp adds 4 bytes to frag:
401 0 extra opcode bytes, 4 displacement bytes. */
252b5132 402 {0, 0, 4, 0},
93c2a809
AM		 403 /* word jmp adds 2 byte2 to frag:
404 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 405 {0, 0, 2, 0},
406
93c2a809
AM		 407 /* COND_JUMP states. */
408 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
409 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
410 /* dword conditionals adds 5 bytes to frag:
411 1 extra opcode byte, 4 displacement bytes. */
412 {0, 0, 5, 0},
fddf5b5b 413 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 414 1 extra opcode byte, 2 displacement bytes. */
415 {0, 0, 3, 0},
416
417 /* COND_JUMP86 states. */
418 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
419 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
420 /* dword conditionals adds 5 bytes to frag:
421 1 extra opcode byte, 4 displacement bytes. */
422 {0, 0, 5, 0},
423 /* word conditionals add 4 bytes to frag:
424 1 displacement byte and a 3 byte long branch insn. */
425 {0, 0, 4, 0}
252b5132
RH		 426};
427
9103f4f4
L		 428static const arch_entry cpu_arch[] =
429{
430 {"generic32", PROCESSOR_GENERIC32,
40fb9820 431 CPU_GENERIC32_FLAGS },
9103f4f4 432 {"generic64", PROCESSOR_GENERIC64,
40fb9820 433 CPU_GENERIC64_FLAGS },
9103f4f4 434 {"i8086", PROCESSOR_UNKNOWN,
40fb9820 435 CPU_NONE_FLAGS },
9103f4f4 436 {"i186", PROCESSOR_UNKNOWN,
40fb9820 437 CPU_I186_FLAGS },
9103f4f4 438 {"i286", PROCESSOR_UNKNOWN,
40fb9820 439 CPU_I286_FLAGS },
76bc74dc 440 {"i386", PROCESSOR_I386,
40fb9820 441 CPU_I386_FLAGS },
9103f4f4 442 {"i486", PROCESSOR_I486,
40fb9820 443 CPU_I486_FLAGS },
9103f4f4 444 {"i586", PROCESSOR_PENTIUM,
40fb9820 445 CPU_I586_FLAGS },
9103f4f4 446 {"i686", PROCESSOR_PENTIUMPRO,
40fb9820 447 CPU_I686_FLAGS },
9103f4f4 448 {"pentium", PROCESSOR_PENTIUM,
40fb9820 449 CPU_I586_FLAGS },
9103f4f4 450 {"pentiumpro",PROCESSOR_PENTIUMPRO,
40fb9820 451 CPU_I686_FLAGS },
9103f4f4 452 {"pentiumii", PROCESSOR_PENTIUMPRO,
40fb9820 453 CPU_P2_FLAGS },
9103f4f4 454 {"pentiumiii",PROCESSOR_PENTIUMPRO,
40fb9820 455 CPU_P3_FLAGS },
9103f4f4 456 {"pentium4", PROCESSOR_PENTIUM4,
40fb9820 457 CPU_P4_FLAGS },
9103f4f4 458 {"prescott", PROCESSOR_NOCONA,
40fb9820 459 CPU_CORE_FLAGS },
9103f4f4 460 {"nocona", PROCESSOR_NOCONA,
40fb9820 461 CPU_NOCONA_FLAGS },
ef05d495 462 {"yonah", PROCESSOR_CORE,
40fb9820 463 CPU_CORE_FLAGS },
ef05d495 464 {"core", PROCESSOR_CORE,
40fb9820 465 CPU_CORE_FLAGS },
ef05d495 466 {"merom", PROCESSOR_CORE2,
40fb9820 467 CPU_CORE2_FLAGS },
ef05d495 468 {"core2", PROCESSOR_CORE2,
40fb9820 469 CPU_CORE2_FLAGS },
9103f4f4 470 {"k6", PROCESSOR_K6,
40fb9820 471 CPU_K6_FLAGS },
9103f4f4 472 {"k6_2", PROCESSOR_K6,
40fb9820 473 CPU_K6_2_FLAGS },
9103f4f4 474 {"athlon", PROCESSOR_ATHLON,
40fb9820 475 CPU_ATHLON_FLAGS },
9103f4f4 476 {"sledgehammer", PROCESSOR_K8,
40fb9820 477 CPU_K8_FLAGS },
9103f4f4 478 {"opteron", PROCESSOR_K8,
40fb9820 479 CPU_K8_FLAGS },
9103f4f4 480 {"k8", PROCESSOR_K8,
40fb9820 481 CPU_K8_FLAGS },
050dfa73 482 {"amdfam10", PROCESSOR_AMDFAM10,
40fb9820 483 CPU_AMDFAM10_FLAGS },
9103f4f4 484 {".mmx", PROCESSOR_UNKNOWN,
40fb9820 485 CPU_MMX_FLAGS },
9103f4f4 486 {".sse", PROCESSOR_UNKNOWN,
40fb9820 487 CPU_SSE_FLAGS },
9103f4f4 488 {".sse2", PROCESSOR_UNKNOWN,
40fb9820 489 CPU_SSE2_FLAGS },
9103f4f4 490 {".sse3", PROCESSOR_UNKNOWN,
40fb9820 491 CPU_SSE3_FLAGS },
ef05d495 492 {".ssse3", PROCESSOR_UNKNOWN,
40fb9820 493 CPU_SSSE3_FLAGS },
42903f7f 494 {".sse4.1", PROCESSOR_UNKNOWN,
40fb9820 495 CPU_SSE4_1_FLAGS },
381d071f 496 {".sse4.2", PROCESSOR_UNKNOWN,
40fb9820 497 CPU_SSE4_2_FLAGS },
381d071f 498 {".sse4", PROCESSOR_UNKNOWN,
40fb9820 499 CPU_SSE4_2_FLAGS },
9103f4f4 500 {".3dnow", PROCESSOR_UNKNOWN,
40fb9820 501 CPU_3DNOW_FLAGS },
9103f4f4 502 {".3dnowa", PROCESSOR_UNKNOWN,
40fb9820 503 CPU_3DNOWA_FLAGS },
9103f4f4 504 {".padlock", PROCESSOR_UNKNOWN,
40fb9820 505 CPU_PADLOCK_FLAGS },
9103f4f4 506 {".pacifica", PROCESSOR_UNKNOWN,
40fb9820 507 CPU_SVME_FLAGS },
9103f4f4 508 {".svme", PROCESSOR_UNKNOWN,
40fb9820 509 CPU_SVME_FLAGS },
050dfa73 510 {".sse4a", PROCESSOR_UNKNOWN,
40fb9820 511 CPU_SSE4A_FLAGS },
050dfa73 512 {".abm", PROCESSOR_UNKNOWN,
40fb9820 513 CPU_ABM_FLAGS },
85f10a01
MM		 514 {".sse5", PROCESSOR_UNKNOWN,
515 CPU_SSE5_FLAGS },
e413e4e9
AM		 516};
517
29b0f896
AM		 518const pseudo_typeS md_pseudo_table[] =
519{
520#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
521 {"align", s_align_bytes, 0},
522#else
523 {"align", s_align_ptwo, 0},
524#endif
525 {"arch", set_cpu_arch, 0},
526#ifndef I386COFF
527 {"bss", s_bss, 0},
528#endif
529 {"ffloat", float_cons, 'f'},
530 {"dfloat", float_cons, 'd'},
531 {"tfloat", float_cons, 'x'},
532 {"value", cons, 2},
d182319b 533 {"slong", signed_cons, 4},
29b0f896
AM		 534 {"noopt", s_ignore, 0},
535 {"optim", s_ignore, 0},
536 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
537 {"code16", set_code_flag, CODE_16BIT},
538 {"code32", set_code_flag, CODE_32BIT},
539 {"code64", set_code_flag, CODE_64BIT},
540 {"intel_syntax", set_intel_syntax, 1},
541 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 542#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
543 {"largecomm", handle_large_common, 0},
07a53e5c 544#else
e3bb37b5 545 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 546 {"loc", dwarf2_directive_loc, 0},
547 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 548#endif
6482c264
NC		 549#ifdef TE_PE
550 {"secrel32", pe_directive_secrel, 0},
551#endif
29b0f896
AM		 552 {0, 0, 0}
553};
554
555/* For interface with expression (). */
556extern char *input_line_pointer;
557
558/* Hash table for instruction mnemonic lookup. */
559static struct hash_control *op_hash;
560
561/* Hash table for register lookup. */
562static struct hash_control *reg_hash;
563\f
252b5132 564void
e3bb37b5 565i386_align_code (fragS *fragP, int count)
252b5132 566{
ce8a8b2f
AM		 567 /* Various efficient no-op patterns for aligning code labels.
568 Note: Don't try to assemble the instructions in the comments.
569 0L and 0w are not legal. */
252b5132
RH		 570 static const char f32_1[] =
571 {0x90}; /* nop */
572 static const char f32_2[] =
ccc9c027 573 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 574 static const char f32_3[] =
575 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
576 static const char f32_4[] =
577 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
578 static const char f32_5[] =
579 {0x90, /* nop */
580 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
581 static const char f32_6[] =
582 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
583 static const char f32_7[] =
584 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
585 static const char f32_8[] =
586 {0x90, /* nop */
587 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
588 static const char f32_9[] =
589 {0x89,0xf6, /* movl %esi,%esi */
590 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
591 static const char f32_10[] =
592 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
593 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
594 static const char f32_11[] =
595 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
596 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
597 static const char f32_12[] =
598 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
599 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
600 static const char f32_13[] =
601 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
602 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
603 static const char f32_14[] =
604 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
605 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 606 static const char f16_3[] =
607 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 608 static const char f16_4[] =
609 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
610 static const char f16_5[] =
611 {0x90, /* nop */
612 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
613 static const char f16_6[] =
614 {0x89,0xf6, /* mov %si,%si */
615 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
616 static const char f16_7[] =
617 {0x8d,0x74,0x00, /* lea 0(%si),%si */
618 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
619 static const char f16_8[] =
620 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
621 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 622 static const char jump_31[] =
623 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
624 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
625 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
626 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 627 static const char *const f32_patt[] = {
628 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 629 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 630 };
631 static const char *const f16_patt[] = {
76bc74dc 632 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 633 };
ccc9c027
L		 634 /* nopl (%[re]ax) */
635 static const char alt_3[] =
636 {0x0f,0x1f,0x00};
637 /* nopl 0(%[re]ax) */
638 static const char alt_4[] =
639 {0x0f,0x1f,0x40,0x00};
640 /* nopl 0(%[re]ax,%[re]ax,1) */
641 static const char alt_5[] =
642 {0x0f,0x1f,0x44,0x00,0x00};
643 /* nopw 0(%[re]ax,%[re]ax,1) */
644 static const char alt_6[] =
645 {0x66,0x0f,0x1f,0x44,0x00,0x00};
646 /* nopl 0L(%[re]ax) */
647 static const char alt_7[] =
648 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
649 /* nopl 0L(%[re]ax,%[re]ax,1) */
650 static const char alt_8[] =
651 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
652 /* nopw 0L(%[re]ax,%[re]ax,1) */
653 static const char alt_9[] =
654 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
655 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
656 static const char alt_10[] =
657 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
658 /* data16
659 nopw %cs:0L(%[re]ax,%[re]ax,1) */
660 static const char alt_long_11[] =
661 {0x66,
662 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
663 /* data16
664 data16
665 nopw %cs:0L(%[re]ax,%[re]ax,1) */
666 static const char alt_long_12[] =
667 {0x66,
668 0x66,
669 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
670 /* data16
671 data16
672 data16
673 nopw %cs:0L(%[re]ax,%[re]ax,1) */
674 static const char alt_long_13[] =
675 {0x66,
676 0x66,
677 0x66,
678 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
679 /* data16
680 data16
681 data16
682 data16
683 nopw %cs:0L(%[re]ax,%[re]ax,1) */
684 static const char alt_long_14[] =
685 {0x66,
686 0x66,
687 0x66,
688 0x66,
689 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
690 /* data16
691 data16
692 data16
693 data16
694 data16
695 nopw %cs:0L(%[re]ax,%[re]ax,1) */
696 static const char alt_long_15[] =
697 {0x66,
698 0x66,
699 0x66,
700 0x66,
701 0x66,
702 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
703 /* nopl 0(%[re]ax,%[re]ax,1)
704 nopw 0(%[re]ax,%[re]ax,1) */
705 static const char alt_short_11[] =
706 {0x0f,0x1f,0x44,0x00,0x00,
707 0x66,0x0f,0x1f,0x44,0x00,0x00};
708 /* nopw 0(%[re]ax,%[re]ax,1)
709 nopw 0(%[re]ax,%[re]ax,1) */
710 static const char alt_short_12[] =
711 {0x66,0x0f,0x1f,0x44,0x00,0x00,
712 0x66,0x0f,0x1f,0x44,0x00,0x00};
713 /* nopw 0(%[re]ax,%[re]ax,1)
714 nopl 0L(%[re]ax) */
715 static const char alt_short_13[] =
716 {0x66,0x0f,0x1f,0x44,0x00,0x00,
717 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
718 /* nopl 0L(%[re]ax)
719 nopl 0L(%[re]ax) */
720 static const char alt_short_14[] =
721 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
722 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
723 /* nopl 0L(%[re]ax)
724 nopl 0L(%[re]ax,%[re]ax,1) */
725 static const char alt_short_15[] =
726 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
727 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
728 static const char *const alt_short_patt[] = {
729 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
730 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
731 alt_short_14, alt_short_15
732 };
733 static const char *const alt_long_patt[] = {
734 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
735 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
736 alt_long_14, alt_long_15
737 };
252b5132 738
76bc74dc
L		 739 /* Only align for at least a positive non-zero boundary. */
740 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 741 return;
3e73aa7c 742
ccc9c027
L		 743 /* We need to decide which NOP sequence to use for 32bit and
744 64bit. When -mtune= is used:
4eed87de 745
76bc74dc
L		 746 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
747 PROCESSOR_GENERIC32, f32_patt will be used.
748 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
749 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
750 alt_long_patt will be used.
751 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
752 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 753
76bc74dc
L		 754 When -mtune= isn't used, alt_long_patt will be used if
755 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
756 be used.
ccc9c027
L		 757
758 When -march= or .arch is used, we can't use anything beyond
759 cpu_arch_isa_flags. */
760
761 if (flag_code == CODE_16BIT)
762 {
ccc9c027 763 if (count > 8)
33fef721 764 {
76bc74dc
L		 765 memcpy (fragP->fr_literal + fragP->fr_fix,
766 jump_31, count);
767 /* Adjust jump offset. */
768 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 769 }
76bc74dc
L		 770 else
771 memcpy (fragP->fr_literal + fragP->fr_fix,
772 f16_patt[count - 1], count);
252b5132 773 }
33fef721 774 else
ccc9c027
L		 775 {
776 const char *const *patt = NULL;
777
778 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
779 {
780 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
781 switch (cpu_arch_tune)
782 {
783 case PROCESSOR_UNKNOWN:
784 /* We use cpu_arch_isa_flags to check if we SHOULD
785 optimize for Cpu686. */
40fb9820 786 if (cpu_arch_isa_flags.bitfield.cpui686)
76bc74dc 787 patt = alt_long_patt;
ccc9c027
L		 788 else
789 patt = f32_patt;
790 break;
ccc9c027
L		 791 case PROCESSOR_PENTIUMPRO:
792 case PROCESSOR_PENTIUM4:
793 case PROCESSOR_NOCONA:
ef05d495 794 case PROCESSOR_CORE:
76bc74dc
L		 795 case PROCESSOR_CORE2:
796 case PROCESSOR_GENERIC64:
797 patt = alt_long_patt;
798 break;
ccc9c027
L		 799 case PROCESSOR_K6:
800 case PROCESSOR_ATHLON:
801 case PROCESSOR_K8:
4eed87de 802 case PROCESSOR_AMDFAM10:
ccc9c027
L		 803 patt = alt_short_patt;
804 break;
76bc74dc 805 case PROCESSOR_I386:
ccc9c027
L		 806 case PROCESSOR_I486:
807 case PROCESSOR_PENTIUM:
808 case PROCESSOR_GENERIC32:
809 patt = f32_patt;
810 break;
4eed87de 811 }
ccc9c027
L		 812 }
813 else
814 {
815 switch (cpu_arch_tune)
816 {
817 case PROCESSOR_UNKNOWN:
818 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
819 PROCESSOR_UNKNOWN. */
820 abort ();
821 break;
822
76bc74dc 823 case PROCESSOR_I386:
ccc9c027
L		 824 case PROCESSOR_I486:
825 case PROCESSOR_PENTIUM:
ccc9c027
L		 826 case PROCESSOR_K6:
827 case PROCESSOR_ATHLON:
828 case PROCESSOR_K8:
4eed87de 829 case PROCESSOR_AMDFAM10:
ccc9c027
L		 830 case PROCESSOR_GENERIC32:
831 /* We use cpu_arch_isa_flags to check if we CAN optimize
832 for Cpu686. */
40fb9820 833 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 834 patt = alt_short_patt;
835 else
836 patt = f32_patt;
837 break;
76bc74dc
L		 838 case PROCESSOR_PENTIUMPRO:
839 case PROCESSOR_PENTIUM4:
840 case PROCESSOR_NOCONA:
841 case PROCESSOR_CORE:
ef05d495 842 case PROCESSOR_CORE2:
40fb9820 843 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 844 patt = alt_long_patt;
845 else
846 patt = f32_patt;
847 break;
848 case PROCESSOR_GENERIC64:
76bc74dc 849 patt = alt_long_patt;
ccc9c027 850 break;
4eed87de 851 }
ccc9c027
L		 852 }
853
76bc74dc
L		 854 if (patt == f32_patt)
855 {
856 /* If the padding is less than 15 bytes, we use the normal
857 ones. Otherwise, we use a jump instruction and adjust
858 its offset. */
859 if (count < 15)
860 memcpy (fragP->fr_literal + fragP->fr_fix,
861 patt[count - 1], count);
862 else
863 {
864 memcpy (fragP->fr_literal + fragP->fr_fix,
865 jump_31, count);
866 /* Adjust jump offset. */
867 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
868 }
869 }
870 else
871 {
872 /* Maximum length of an instruction is 15 byte. If the
873 padding is greater than 15 bytes and we don't use jump,
874 we have to break it into smaller pieces. */
875 int padding = count;
876 while (padding > 15)
877 {
878 padding -= 15;
879 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
880 patt [14], 15);
881 }
882
883 if (padding)
884 memcpy (fragP->fr_literal + fragP->fr_fix,
885 patt [padding - 1], padding);
886 }
ccc9c027 887 }
33fef721 888 fragP->fr_var = count;
252b5132
RH		 889}
890
c6fb90c8
L		 891static INLINE int
892uints_all_zero (const unsigned int *x, unsigned int size)
40fb9820 893{
c6fb90c8
L		 894 switch (size)
895 {
896 case 3:
897 if (x[2])
898 return 0;
899 case 2:
900 if (x[1])
901 return 0;
902 case 1:
903 return !x[0];
904 default:
905 abort ();
906 }
40fb9820
L		 907}
908
c6fb90c8
L		 909static INLINE void
910uints_set (unsigned int *x, unsigned int v, unsigned int size)
40fb9820 911{
c6fb90c8
L		 912 switch (size)
913 {
914 case 3:
915 x[2] = v;
916 case 2:
917 x[1] = v;
918 case 1:
919 x[0] = v;
920 break;
921 default:
922 abort ();
923 }
924}
40fb9820 925
c6fb90c8
L		 926static INLINE int
927uints_equal (const unsigned int *x, const unsigned int *y,
928 unsigned int size)
929{
930 switch (size)
931 {
932 case 3:
933 if (x[2] != y [2])
934 return 0;
935 case 2:
936 if (x[1] != y [1])
937 return 0;
938 case 1:
939 return x[0] == y [0];
940 break;
941 default:
942 abort ();
943 }
944}
40fb9820 945
c6fb90c8
L		 946#define UINTS_ALL_ZERO(x) \
947 uints_all_zero ((x).array, ARRAY_SIZE ((x).array))
948#define UINTS_SET(x, v) \
949 uints_set ((x).array, v, ARRAY_SIZE ((x).array))
950#define UINTS_CLEAR(x) \
951 uints_set ((x).array, 0, ARRAY_SIZE ((x).array))
952#define UINTS_EQUAL(x, y) \
953 uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array))
954
955static INLINE int
956cpu_flags_check_cpu64 (i386_cpu_flags f)
957{
958 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
959 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 960}
961
c6fb90c8 962static INLINE i386_cpu_flags
40fb9820
L		 963cpu_flags_not (i386_cpu_flags x)
964{
c6fb90c8
L		 965 switch (ARRAY_SIZE (x.array))
966 {
967 case 3:
968 x.array [2] = ~x.array [2];
969 case 2:
970 x.array [1] = ~x.array [1];
971 case 1:
972 x.array [0] = ~x.array [0];
973 break;
974 default:
975 abort ();
976 }
40fb9820
L		 977
978#ifdef CpuUnused
979 x.bitfield.unused = 0;
980#endif
981
982 return x;
983}
984
c6fb90c8
L		 985static INLINE i386_cpu_flags
986cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 987{
c6fb90c8
L		 988 switch (ARRAY_SIZE (x.array))
989 {
990 case 3:
991 x.array [2] &= y.array [2];
992 case 2:
993 x.array [1] &= y.array [1];
994 case 1:
995 x.array [0] &= y.array [0];
996 break;
997 default:
998 abort ();
999 }
1000 return x;
1001}
40fb9820 1002
c6fb90c8
L		 1003static INLINE i386_cpu_flags
1004cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1005{
c6fb90c8 1006 switch (ARRAY_SIZE (x.array))
40fb9820 1007 {
c6fb90c8
L		 1008 case 3:
1009 x.array [2] |= y.array [2];
1010 case 2:
1011 x.array [1] |= y.array [1];
1012 case 1:
1013 x.array [0] |= y.array [0];
40fb9820
L		 1014 break;
1015 default:
1016 abort ();
1017 }
40fb9820
L		 1018 return x;
1019}
1020
1021static int
1022cpu_flags_match (i386_cpu_flags x)
1023{
1024 i386_cpu_flags not = cpu_arch_flags_not;
1025
1026 not.bitfield.cpu64 = 1;
1027 not.bitfield.cpuno64 = 1;
1028
1029 x.bitfield.cpu64 = 0;
1030 x.bitfield.cpuno64 = 0;
1031
c6fb90c8
L		 1032 not = cpu_flags_and (x, not);
1033 return UINTS_ALL_ZERO (not);
40fb9820
L		 1034}
1035
c6fb90c8
L		 1036static INLINE i386_operand_type
1037operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1038{
c6fb90c8
L		 1039 switch (ARRAY_SIZE (x.array))
1040 {
1041 case 3:
1042 x.array [2] &= y.array [2];
1043 case 2:
1044 x.array [1] &= y.array [1];
1045 case 1:
1046 x.array [0] &= y.array [0];
1047 break;
1048 default:
1049 abort ();
1050 }
1051 return x;
40fb9820
L		 1052}
1053
c6fb90c8
L		 1054static INLINE i386_operand_type
1055operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1056{
c6fb90c8 1057 switch (ARRAY_SIZE (x.array))
40fb9820 1058 {
c6fb90c8
L		 1059 case 3:
1060 x.array [2] |= y.array [2];
1061 case 2:
1062 x.array [1] |= y.array [1];
1063 case 1:
1064 x.array [0] |= y.array [0];
40fb9820
L		 1065 break;
1066 default:
1067 abort ();
1068 }
c6fb90c8
L		 1069 return x;
1070}
40fb9820 1071
c6fb90c8
L		 1072static INLINE i386_operand_type
1073operand_type_xor (i386_operand_type x, i386_operand_type y)
1074{
1075 switch (ARRAY_SIZE (x.array))
1076 {
1077 case 3:
1078 x.array [2] ^= y.array [2];
1079 case 2:
1080 x.array [1] ^= y.array [1];
1081 case 1:
1082 x.array [0] ^= y.array [0];
1083 break;
1084 default:
1085 abort ();
1086 }
40fb9820
L		 1087 return x;
1088}
1089
1090static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1091static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1092static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1093static const i386_operand_type reg16_inoutportreg
1094 = OPERAND_TYPE_REG16_INOUTPORTREG;
1095static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1096static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1097static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1098static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1099static const i386_operand_type anydisp
1100 = OPERAND_TYPE_ANYDISP;
40fb9820
L		 1101static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1102static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1103static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1104static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1105static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1106static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1107static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1108static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1109static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1110static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1111
1112enum operand_type
1113{
1114 reg,
40fb9820
L		 1115 imm,
1116 disp,
1117 anymem
1118};
1119
c6fb90c8 1120static INLINE int
40fb9820
L		 1121operand_type_check (i386_operand_type t, enum operand_type c)
1122{
1123 switch (c)
1124 {
1125 case reg:
1126 return (t.bitfield.reg8
1127 || t.bitfield.reg16
1128 || t.bitfield.reg32
1129 || t.bitfield.reg64);
1130
40fb9820
L		 1131 case imm:
1132 return (t.bitfield.imm8
1133 || t.bitfield.imm8s
1134 || t.bitfield.imm16
1135 || t.bitfield.imm32
1136 || t.bitfield.imm32s
1137 || t.bitfield.imm64);
1138
1139 case disp:
1140 return (t.bitfield.disp8
1141 || t.bitfield.disp16
1142 || t.bitfield.disp32
1143 || t.bitfield.disp32s
1144 || t.bitfield.disp64);
1145
1146 case anymem:
1147 return (t.bitfield.disp8
1148 || t.bitfield.disp16
1149 || t.bitfield.disp32
1150 || t.bitfield.disp32s
1151 || t.bitfield.disp64
1152 || t.bitfield.baseindex);
1153
1154 default:
1155 abort ();
1156 }
1157}
1158
c6fb90c8 1159static INLINE int
40fb9820
L		 1160operand_type_match (i386_operand_type overlap,
1161 i386_operand_type given)
1162{
1163 i386_operand_type temp = overlap;
1164
1165 temp.bitfield.jumpabsolute = 0;
c6fb90c8 1166 if (UINTS_ALL_ZERO (temp))
40fb9820
L		 1167 return 0;
1168
1169 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1170 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1171}
1172
1173/* If given types r0 and r1 are registers they must be of the same type
1174 unless the expected operand type register overlap is null.
1175 Note that Acc in a template matches every size of reg. */
1176
c6fb90c8 1177static INLINE int
40fb9820
L		 1178operand_type_register_match (i386_operand_type m0,
1179 i386_operand_type g0,
1180 i386_operand_type t0,
1181 i386_operand_type m1,
1182 i386_operand_type g1,
1183 i386_operand_type t1)
1184{
1185 if (!operand_type_check (g0, reg))
1186 return 1;
1187
1188 if (!operand_type_check (g1, reg))
1189 return 1;
1190
1191 if (g0.bitfield.reg8 == g1.bitfield.reg8
1192 && g0.bitfield.reg16 == g1.bitfield.reg16
1193 && g0.bitfield.reg32 == g1.bitfield.reg32
1194 && g0.bitfield.reg64 == g1.bitfield.reg64)
1195 return 1;
1196
1197 if (m0.bitfield.acc)
1198 {
1199 t0.bitfield.reg8 = 1;
1200 t0.bitfield.reg16 = 1;
1201 t0.bitfield.reg32 = 1;
1202 t0.bitfield.reg64 = 1;
1203 }
1204
1205 if (m1.bitfield.acc)
1206 {
1207 t1.bitfield.reg8 = 1;
1208 t1.bitfield.reg16 = 1;
1209 t1.bitfield.reg32 = 1;
1210 t1.bitfield.reg64 = 1;
1211 }
1212
1213 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1214 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1215 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1216 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1217}
1218
252b5132 1219static INLINE unsigned int
40fb9820 1220mode_from_disp_size (i386_operand_type t)
252b5132 1221{
40fb9820
L		 1222 if (t.bitfield.disp8)
1223 return 1;
1224 else if (t.bitfield.disp16
1225 || t.bitfield.disp32
1226 || t.bitfield.disp32s)
1227 return 2;
1228 else
1229 return 0;
252b5132
RH		 1230}
1231
1232static INLINE int
e3bb37b5 1233fits_in_signed_byte (offsetT num)
252b5132
RH		 1234{
1235 return (num >= -128) && (num <= 127);
47926f60 1236}
252b5132
RH		 1237
1238static INLINE int
e3bb37b5 1239fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1240{
1241 return (num & 0xff) == num;
47926f60 1242}
252b5132
RH		 1243
1244static INLINE int
e3bb37b5 1245fits_in_unsigned_word (offsetT num)
252b5132
RH		 1246{
1247 return (num & 0xffff) == num;
47926f60 1248}
252b5132
RH		 1249
1250static INLINE int
e3bb37b5 1251fits_in_signed_word (offsetT num)
252b5132
RH		 1252{
1253 return (-32768 <= num) && (num <= 32767);
47926f60 1254}
2a962e6d 1255
3e73aa7c 1256static INLINE int
e3bb37b5 1257fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1258{
1259#ifndef BFD64
1260 return 1;
1261#else
1262 return (!(((offsetT) -1 << 31) & num)
1263 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1264#endif
1265} /* fits_in_signed_long() */
2a962e6d 1266
3e73aa7c 1267static INLINE int
e3bb37b5 1268fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1269{
1270#ifndef BFD64
1271 return 1;
1272#else
1273 return (num & (((offsetT) 2 << 31) - 1)) == num;
1274#endif
1275} /* fits_in_unsigned_long() */
252b5132 1276
40fb9820 1277static i386_operand_type
e3bb37b5 1278smallest_imm_type (offsetT num)
252b5132 1279{
40fb9820
L		 1280 i386_operand_type t;
1281
c6fb90c8 1282 UINTS_CLEAR (t);
40fb9820
L		 1283 t.bitfield.imm64 = 1;
1284
1285 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1286 {
1287 /* This code is disabled on the 486 because all the Imm1 forms
1288 in the opcode table are slower on the i486. They're the
1289 versions with the implicitly specified single-position
1290 displacement, which has another syntax if you really want to
1291 use that form. */
40fb9820
L		 1292 t.bitfield.imm1 = 1;
1293 t.bitfield.imm8 = 1;
1294 t.bitfield.imm8s = 1;
1295 t.bitfield.imm16 = 1;
1296 t.bitfield.imm32 = 1;
1297 t.bitfield.imm32s = 1;
1298 }
1299 else if (fits_in_signed_byte (num))
1300 {
1301 t.bitfield.imm8 = 1;
1302 t.bitfield.imm8s = 1;
1303 t.bitfield.imm16 = 1;
1304 t.bitfield.imm32 = 1;
1305 t.bitfield.imm32s = 1;
1306 }
1307 else if (fits_in_unsigned_byte (num))
1308 {
1309 t.bitfield.imm8 = 1;
1310 t.bitfield.imm16 = 1;
1311 t.bitfield.imm32 = 1;
1312 t.bitfield.imm32s = 1;
1313 }
1314 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1315 {
1316 t.bitfield.imm16 = 1;
1317 t.bitfield.imm32 = 1;
1318 t.bitfield.imm32s = 1;
1319 }
1320 else if (fits_in_signed_long (num))
1321 {
1322 t.bitfield.imm32 = 1;
1323 t.bitfield.imm32s = 1;
1324 }
1325 else if (fits_in_unsigned_long (num))
1326 t.bitfield.imm32 = 1;
1327
1328 return t;
47926f60 1329}
252b5132 1330
847f7ad4 1331static offsetT
e3bb37b5 1332offset_in_range (offsetT val, int size)
847f7ad4 1333{
508866be 1334 addressT mask;
ba2adb93 1335
847f7ad4
AM		 1336 switch (size)
1337 {
508866be
L		 1338 case 1: mask = ((addressT) 1 << 8) - 1; break;
1339 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1340 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1341#ifdef BFD64
1342 case 8: mask = ((addressT) 2 << 63) - 1; break;
1343#endif
47926f60 1344 default: abort ();
847f7ad4
AM		 1345 }
1346
ba2adb93 1347 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1348 if (!use_rela_relocations)
1349 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1350 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1351
47926f60 1352 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1353 {
1354 char buf1[40], buf2[40];
1355
1356 sprint_value (buf1, val);
1357 sprint_value (buf2, val & mask);
1358 as_warn (_("%s shortened to %s"), buf1, buf2);
1359 }
1360 return val & mask;
1361}
1362
252b5132
RH		 1363/* Returns 0 if attempting to add a prefix where one from the same
1364 class already exists, 1 if non rep/repne added, 2 if rep/repne
1365 added. */
1366static int
e3bb37b5 1367add_prefix (unsigned int prefix)
252b5132
RH		 1368{
1369 int ret = 1;
b1905489 1370 unsigned int q;
252b5132 1371
29b0f896
AM		 1372 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1373 && flag_code == CODE_64BIT)
b1905489 1374 {
161a04f6
L		 1375 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1376 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1377 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1378 ret = 0;
1379 q = REX_PREFIX;
1380 }
3e73aa7c 1381 else
b1905489
JB		 1382 {
1383 switch (prefix)
1384 {
1385 default:
1386 abort ();
1387
1388 case CS_PREFIX_OPCODE:
1389 case DS_PREFIX_OPCODE:
1390 case ES_PREFIX_OPCODE:
1391 case FS_PREFIX_OPCODE:
1392 case GS_PREFIX_OPCODE:
1393 case SS_PREFIX_OPCODE:
1394 q = SEG_PREFIX;
1395 break;
1396
1397 case REPNE_PREFIX_OPCODE:
1398 case REPE_PREFIX_OPCODE:
1399 ret = 2;
1400 /* fall thru */
1401 case LOCK_PREFIX_OPCODE:
1402 q = LOCKREP_PREFIX;
1403 break;
1404
1405 case FWAIT_OPCODE:
1406 q = WAIT_PREFIX;
1407 break;
1408
1409 case ADDR_PREFIX_OPCODE:
1410 q = ADDR_PREFIX;
1411 break;
1412
1413 case DATA_PREFIX_OPCODE:
1414 q = DATA_PREFIX;
1415 break;
1416 }
1417 if (i.prefix[q] != 0)
1418 ret = 0;
1419 }
252b5132 1420
b1905489 1421 if (ret)
252b5132 1422 {
b1905489
JB		 1423 if (!i.prefix[q])
1424 ++i.prefixes;
1425 i.prefix[q] |= prefix;
252b5132 1426 }
b1905489
JB		 1427 else
1428 as_bad (_("same type of prefix used twice"));
252b5132 1429
252b5132
RH		 1430 return ret;
1431}
1432
1433static void
e3bb37b5 1434set_code_flag (int value)
eecb386c 1435{
3e73aa7c 1436 flag_code = value;
40fb9820
L		 1437 if (flag_code == CODE_64BIT)
1438 {
1439 cpu_arch_flags.bitfield.cpu64 = 1;
1440 cpu_arch_flags.bitfield.cpuno64 = 0;
1441 cpu_arch_flags_not.bitfield.cpu64 = 0;
1442 cpu_arch_flags_not.bitfield.cpuno64 = 1;
1443 }
1444 else
1445 {
1446 cpu_arch_flags.bitfield.cpu64 = 0;
1447 cpu_arch_flags.bitfield.cpuno64 = 1;
1448 cpu_arch_flags_not.bitfield.cpu64 = 1;
1449 cpu_arch_flags_not.bitfield.cpuno64 = 0;
1450 }
1451 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1452 {
1453 as_bad (_("64bit mode not supported on this CPU."));
1454 }
40fb9820 1455 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1456 {
1457 as_bad (_("32bit mode not supported on this CPU."));
1458 }
eecb386c
AM		 1459 stackop_size = '\0';
1460}
1461
1462static void
e3bb37b5 1463set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1464{
3e73aa7c 1465 flag_code = new_code_flag;
40fb9820
L		 1466 if (flag_code != CODE_16BIT)
1467 abort ();
1468 cpu_arch_flags.bitfield.cpu64 = 0;
1469 cpu_arch_flags.bitfield.cpuno64 = 1;
1470 cpu_arch_flags_not.bitfield.cpu64 = 1;
1471 cpu_arch_flags_not.bitfield.cpuno64 = 0;
9306ca4a 1472 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1473}
1474
1475static void
e3bb37b5 1476set_intel_syntax (int syntax_flag)
252b5132
RH		 1477{
1478 /* Find out if register prefixing is specified. */
1479 int ask_naked_reg = 0;
1480
1481 SKIP_WHITESPACE ();
29b0f896 1482 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1483 {
1484 char *string = input_line_pointer;
1485 int e = get_symbol_end ();
1486
47926f60 1487 if (strcmp (string, "prefix") == 0)
252b5132 1488 ask_naked_reg = 1;
47926f60 1489 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1490 ask_naked_reg = -1;
1491 else
d0b47220 1492 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1493 *input_line_pointer = e;
1494 }
1495 demand_empty_rest_of_line ();
c3332e24 1496
252b5132
RH		 1497 intel_syntax = syntax_flag;
1498
1499 if (ask_naked_reg == 0)
f86103b7
AM		 1500 allow_naked_reg = (intel_syntax
1501 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1502 else
1503 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1504
e4a3b5a4 1505 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1506 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1507 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1508}
1509
e413e4e9 1510static void
e3bb37b5 1511set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1512{
47926f60 1513 SKIP_WHITESPACE ();
e413e4e9 1514
29b0f896 1515 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1516 {
1517 char *string = input_line_pointer;
1518 int e = get_symbol_end ();
9103f4f4 1519 unsigned int i;
40fb9820 1520 i386_cpu_flags flags;
e413e4e9 1521
9103f4f4 1522 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1523 {
1524 if (strcmp (string, cpu_arch[i].name) == 0)
1525 {
5c6af06e
JB		 1526 if (*string != '.')
1527 {
1528 cpu_arch_name = cpu_arch[i].name;
1529 cpu_sub_arch_name = NULL;
40fb9820
L		 1530 cpu_arch_flags = cpu_arch[i].flags;
1531 if (flag_code == CODE_64BIT)
1532 {
1533 cpu_arch_flags.bitfield.cpu64 = 1;
1534 cpu_arch_flags.bitfield.cpuno64 = 0;
1535 }
1536 else
1537 {
1538 cpu_arch_flags.bitfield.cpu64 = 0;
1539 cpu_arch_flags.bitfield.cpuno64 = 1;
1540 }
1541 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
ccc9c027 1542 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1543 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1544 if (!cpu_arch_tune_set)
1545 {
1546 cpu_arch_tune = cpu_arch_isa;
1547 cpu_arch_tune_flags = cpu_arch_isa_flags;
1548 }
5c6af06e
JB		 1549 break;
1550 }
40fb9820 1551
c6fb90c8
L		 1552 flags = cpu_flags_or (cpu_arch_flags,
1553 cpu_arch[i].flags);
1554 if (!UINTS_EQUAL (flags, cpu_arch_flags))
5c6af06e
JB		 1555 {
1556 cpu_sub_arch_name = cpu_arch[i].name;
40fb9820
L		 1557 cpu_arch_flags = flags;
1558 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
5c6af06e
JB		 1559 }
1560 *input_line_pointer = e;
1561 demand_empty_rest_of_line ();
1562 return;
e413e4e9
AM		 1563 }
1564 }
9103f4f4 1565 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1566 as_bad (_("no such architecture: `%s'"), string);
1567
1568 *input_line_pointer = e;
1569 }
1570 else
1571 as_bad (_("missing cpu architecture"));
1572
fddf5b5b
AM		 1573 no_cond_jump_promotion = 0;
1574 if (*input_line_pointer == ','
29b0f896 1575 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1576 {
1577 char *string = ++input_line_pointer;
1578 int e = get_symbol_end ();
1579
1580 if (strcmp (string, "nojumps") == 0)
1581 no_cond_jump_promotion = 1;
1582 else if (strcmp (string, "jumps") == 0)
1583 ;
1584 else
1585 as_bad (_("no such architecture modifier: `%s'"), string);
1586
1587 *input_line_pointer = e;
1588 }
1589
e413e4e9
AM		 1590 demand_empty_rest_of_line ();
1591}
1592
b9d79e03
JH		 1593unsigned long
1594i386_mach ()
1595{
1596 if (!strcmp (default_arch, "x86_64"))
1597 return bfd_mach_x86_64;
1598 else if (!strcmp (default_arch, "i386"))
1599 return bfd_mach_i386_i386;
1600 else
1601 as_fatal (_("Unknown architecture"));
1602}
b9d79e03 1603\f
252b5132
RH		 1604void
1605md_begin ()
1606{
1607 const char *hash_err;
1608
40fb9820
L		 1609 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
1610
47926f60 1611 /* Initialize op_hash hash table. */
252b5132
RH		 1612 op_hash = hash_new ();
1613
1614 {
29b0f896
AM		 1615 const template *optab;
1616 templates *core_optab;
252b5132 1617
47926f60
KH		 1618 /* Setup for loop. */
1619 optab = i386_optab;
252b5132
RH		 1620 core_optab = (templates *) xmalloc (sizeof (templates));
1621 core_optab->start = optab;
1622
1623 while (1)
1624 {
1625 ++optab;
1626 if (optab->name == NULL
1627 || strcmp (optab->name, (optab - 1)->name) != 0)
1628 {
1629 /* different name --> ship out current template list;
47926f60 1630 add to hash table; & begin anew. */
252b5132
RH		 1631 core_optab->end = optab;
1632 hash_err = hash_insert (op_hash,
1633 (optab - 1)->name,
1634 (PTR) core_optab);
1635 if (hash_err)
1636 {
252b5132
RH		 1637 as_fatal (_("Internal Error: Can't hash %s: %s"),
1638 (optab - 1)->name,
1639 hash_err);
1640 }
1641 if (optab->name == NULL)
1642 break;
1643 core_optab = (templates *) xmalloc (sizeof (templates));
1644 core_optab->start = optab;
1645 }
1646 }
1647 }
1648
47926f60 1649 /* Initialize reg_hash hash table. */
252b5132
RH		 1650 reg_hash = hash_new ();
1651 {
29b0f896 1652 const reg_entry *regtab;
c3fe08fa 1653 unsigned int regtab_size = i386_regtab_size;
252b5132 1654
c3fe08fa 1655 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132
RH		 1656 {
1657 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1658 if (hash_err)
3e73aa7c
JH		 1659 as_fatal (_("Internal Error: Can't hash %s: %s"),
1660 regtab->reg_name,
1661 hash_err);
252b5132
RH		 1662 }
1663 }
1664
47926f60 1665 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1666 {
29b0f896
AM		 1667 int c;
1668 char *p;
252b5132
RH		 1669
1670 for (c = 0; c < 256; c++)
1671 {
3882b010 1672 if (ISDIGIT (c))
252b5132
RH		 1673 {
1674 digit_chars[c] = c;
1675 mnemonic_chars[c] = c;
1676 register_chars[c] = c;
1677 operand_chars[c] = c;
1678 }
3882b010 1679 else if (ISLOWER (c))
252b5132
RH		 1680 {
1681 mnemonic_chars[c] = c;
1682 register_chars[c] = c;
1683 operand_chars[c] = c;
1684 }
3882b010 1685 else if (ISUPPER (c))
252b5132 1686 {
3882b010 1687 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1688 register_chars[c] = mnemonic_chars[c];
1689 operand_chars[c] = c;
1690 }
1691
3882b010 1692 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1693 identifier_chars[c] = c;
1694 else if (c >= 128)
1695 {
1696 identifier_chars[c] = c;
1697 operand_chars[c] = c;
1698 }
1699 }
1700
1701#ifdef LEX_AT
1702 identifier_chars['@'] = '@';
32137342
NC		 1703#endif
1704#ifdef LEX_QM
1705 identifier_chars['?'] = '?';
1706 operand_chars['?'] = '?';
252b5132 1707#endif
252b5132 1708 digit_chars['-'] = '-';
791fe849 1709 mnemonic_chars['-'] = '-';
0003779b 1710 mnemonic_chars['.'] = '.';
252b5132
RH		 1711 identifier_chars['_'] = '_';
1712 identifier_chars['.'] = '.';
1713
1714 for (p = operand_special_chars; *p != '\0'; p++)
1715 operand_chars[(unsigned char) *p] = *p;
1716 }
1717
1718#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1719 if (IS_ELF)
252b5132
RH		 1720 {
1721 record_alignment (text_section, 2);
1722 record_alignment (data_section, 2);
1723 record_alignment (bss_section, 2);
1724 }
1725#endif
a4447b93
RH		 1726
1727 if (flag_code == CODE_64BIT)
1728 {
1729 x86_dwarf2_return_column = 16;
1730 x86_cie_data_alignment = -8;
1731 }
1732 else
1733 {
1734 x86_dwarf2_return_column = 8;
1735 x86_cie_data_alignment = -4;
1736 }
252b5132
RH		 1737}
1738
1739void
e3bb37b5 1740i386_print_statistics (FILE *file)
252b5132
RH		 1741{
1742 hash_print_statistics (file, "i386 opcode", op_hash);
1743 hash_print_statistics (file, "i386 register", reg_hash);
1744}
1745\f
252b5132
RH		 1746#ifdef DEBUG386
1747
ce8a8b2f 1748/* Debugging routines for md_assemble. */
e3bb37b5 1749static void pte (template *);
40fb9820 1750static void pt (i386_operand_type);
e3bb37b5
L		 1751static void pe (expressionS *);
1752static void ps (symbolS *);
252b5132
RH		 1753
1754static void
e3bb37b5 1755pi (char *line, i386_insn *x)
252b5132 1756{
09f131f2 1757 unsigned int i;
252b5132
RH		 1758
1759 fprintf (stdout, "%s: template ", line);
1760 pte (&x->tm);
09f131f2
JH		 1761 fprintf (stdout, " address: base %s index %s scale %x\n",
1762 x->base_reg ? x->base_reg->reg_name : "none",
1763 x->index_reg ? x->index_reg->reg_name : "none",
1764 x->log2_scale_factor);
1765 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1766 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1767 fprintf (stdout, " sib: base %x index %x scale %x\n",
1768 x->sib.base, x->sib.index, x->sib.scale);
1769 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 1770 (x->rex & REX_W) != 0,
1771 (x->rex & REX_R) != 0,
1772 (x->rex & REX_X) != 0,
1773 (x->rex & REX_B) != 0);
85f10a01
MM		 1774 fprintf (stdout, " drex: reg %d rex 0x%x\n",
1775 x->drex.reg, x->drex.rex);
252b5132
RH		 1776 for (i = 0; i < x->operands; i++)
1777 {
1778 fprintf (stdout, " #%d: ", i + 1);
1779 pt (x->types[i]);
1780 fprintf (stdout, "\n");
40fb9820
L		 1781 if (x->types[i].bitfield.reg8
1782 || x->types[i].bitfield.reg16
1783 || x->types[i].bitfield.reg32
1784 || x->types[i].bitfield.reg64
1785 || x->types[i].bitfield.regmmx
1786 || x->types[i].bitfield.regxmm
1787 || x->types[i].bitfield.sreg2
1788 || x->types[i].bitfield.sreg3
1789 || x->types[i].bitfield.control
1790 || x->types[i].bitfield.debug
1791 || x->types[i].bitfield.test)
520dc8e8 1792 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 1793 if (operand_type_check (x->types[i], imm))
520dc8e8 1794 pe (x->op[i].imms);
40fb9820 1795 if (operand_type_check (x->types[i], disp))
520dc8e8 1796 pe (x->op[i].disps);
252b5132
RH		 1797 }
1798}
1799
1800static void
e3bb37b5 1801pte (template *t)
252b5132 1802{
09f131f2 1803 unsigned int i;
252b5132 1804 fprintf (stdout, " %d operands ", t->operands);
47926f60 1805 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1806 if (t->extension_opcode != None)
1807 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 1808 if (t->opcode_modifier.d)
252b5132 1809 fprintf (stdout, "D");
40fb9820 1810 if (t->opcode_modifier.w)
252b5132
RH		 1811 fprintf (stdout, "W");
1812 fprintf (stdout, "\n");
1813 for (i = 0; i < t->operands; i++)
1814 {
1815 fprintf (stdout, " #%d type ", i + 1);
1816 pt (t->operand_types[i]);
1817 fprintf (stdout, "\n");
1818 }
1819}
1820
1821static void
e3bb37b5 1822pe (expressionS *e)
252b5132 1823{
24eab124 1824 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1825 fprintf (stdout, " add_number %ld (%lx)\n",
1826 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1827 if (e->X_add_symbol)
1828 {
1829 fprintf (stdout, " add_symbol ");
1830 ps (e->X_add_symbol);
1831 fprintf (stdout, "\n");
1832 }
1833 if (e->X_op_symbol)
1834 {
1835 fprintf (stdout, " op_symbol ");
1836 ps (e->X_op_symbol);
1837 fprintf (stdout, "\n");
1838 }
1839}
1840
1841static void
e3bb37b5 1842ps (symbolS *s)
252b5132
RH		 1843{
1844 fprintf (stdout, "%s type %s%s",
1845 S_GET_NAME (s),
1846 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1847 segment_name (S_GET_SEGMENT (s)));
1848}
1849
7b81dfbb 1850static struct type_name
252b5132 1851 {
40fb9820
L		 1852 i386_operand_type mask;
1853 const char *name;
252b5132 1854 }
7b81dfbb 1855const type_names[] =
252b5132 1856{
40fb9820
L		 1857 { OPERAND_TYPE_REG8, "r8" },
1858 { OPERAND_TYPE_REG16, "r16" },
1859 { OPERAND_TYPE_REG32, "r32" },
1860 { OPERAND_TYPE_REG64, "r64" },
1861 { OPERAND_TYPE_IMM8, "i8" },
1862 { OPERAND_TYPE_IMM8, "i8s" },
1863 { OPERAND_TYPE_IMM16, "i16" },
1864 { OPERAND_TYPE_IMM32, "i32" },
1865 { OPERAND_TYPE_IMM32S, "i32s" },
1866 { OPERAND_TYPE_IMM64, "i64" },
1867 { OPERAND_TYPE_IMM1, "i1" },
1868 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
1869 { OPERAND_TYPE_DISP8, "d8" },
1870 { OPERAND_TYPE_DISP16, "d16" },
1871 { OPERAND_TYPE_DISP32, "d32" },
1872 { OPERAND_TYPE_DISP32S, "d32s" },
1873 { OPERAND_TYPE_DISP64, "d64" },
1874 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
1875 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
1876 { OPERAND_TYPE_CONTROL, "control reg" },
1877 { OPERAND_TYPE_TEST, "test reg" },
1878 { OPERAND_TYPE_DEBUG, "debug reg" },
1879 { OPERAND_TYPE_FLOATREG, "FReg" },
1880 { OPERAND_TYPE_FLOATACC, "FAcc" },
1881 { OPERAND_TYPE_SREG2, "SReg2" },
1882 { OPERAND_TYPE_SREG3, "SReg3" },
1883 { OPERAND_TYPE_ACC, "Acc" },
1884 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
1885 { OPERAND_TYPE_REGMMX, "rMMX" },
1886 { OPERAND_TYPE_REGXMM, "rXMM" },
1887 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 1888};
1889
1890static void
40fb9820 1891pt (i386_operand_type t)
252b5132 1892{
40fb9820 1893 unsigned int j;
c6fb90c8 1894 i386_operand_type a;
252b5132 1895
40fb9820 1896 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 1897 {
1898 a = operand_type_and (t, type_names[j].mask);
1899 if (!UINTS_ALL_ZERO (a))
1900 fprintf (stdout, "%s, ", type_names[j].name);
1901 }
252b5132
RH		 1902 fflush (stdout);
1903}
1904
1905#endif /* DEBUG386 */
1906\f
252b5132 1907static bfd_reloc_code_real_type
3956db08 1908reloc (unsigned int size,
64e74474
AM		 1909 int pcrel,
1910 int sign,
1911 bfd_reloc_code_real_type other)
252b5132 1912{
47926f60 1913 if (other != NO_RELOC)
3956db08
JB		 1914 {
1915 reloc_howto_type *reloc;
1916
1917 if (size == 8)
1918 switch (other)
1919 {
64e74474
AM		 1920 case BFD_RELOC_X86_64_GOT32:
1921 return BFD_RELOC_X86_64_GOT64;
1922 break;
1923 case BFD_RELOC_X86_64_PLTOFF64:
1924 return BFD_RELOC_X86_64_PLTOFF64;
1925 break;
1926 case BFD_RELOC_X86_64_GOTPC32:
1927 other = BFD_RELOC_X86_64_GOTPC64;
1928 break;
1929 case BFD_RELOC_X86_64_GOTPCREL:
1930 other = BFD_RELOC_X86_64_GOTPCREL64;
1931 break;
1932 case BFD_RELOC_X86_64_TPOFF32:
1933 other = BFD_RELOC_X86_64_TPOFF64;
1934 break;
1935 case BFD_RELOC_X86_64_DTPOFF32:
1936 other = BFD_RELOC_X86_64_DTPOFF64;
1937 break;
1938 default:
1939 break;
3956db08 1940 }
e05278af
JB		 1941
1942 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1943 if (size == 4 && flag_code != CODE_64BIT)
1944 sign = -1;
1945
3956db08
JB		 1946 reloc = bfd_reloc_type_lookup (stdoutput, other);
1947 if (!reloc)
1948 as_bad (_("unknown relocation (%u)"), other);
1949 else if (size != bfd_get_reloc_size (reloc))
1950 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1951 bfd_get_reloc_size (reloc),
1952 size);
1953 else if (pcrel && !reloc->pc_relative)
1954 as_bad (_("non-pc-relative relocation for pc-relative field"));
1955 else if ((reloc->complain_on_overflow == complain_overflow_signed
1956 && !sign)
1957 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1958 && sign > 0))
3956db08
JB		 1959 as_bad (_("relocated field and relocation type differ in signedness"));
1960 else
1961 return other;
1962 return NO_RELOC;
1963 }
252b5132
RH		 1964
1965 if (pcrel)
1966 {
3e73aa7c 1967 if (!sign)
3956db08 1968 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1969 switch (size)
1970 {
1971 case 1: return BFD_RELOC_8_PCREL;
1972 case 2: return BFD_RELOC_16_PCREL;
1973 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1974 case 8: return BFD_RELOC_64_PCREL;
252b5132 1975 }
3956db08 1976 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1977 }
1978 else
1979 {
3956db08 1980 if (sign > 0)
e5cb08ac 1981 switch (size)
3e73aa7c
JH		 1982 {
1983 case 4: return BFD_RELOC_X86_64_32S;
1984 }
1985 else
1986 switch (size)
1987 {
1988 case 1: return BFD_RELOC_8;
1989 case 2: return BFD_RELOC_16;
1990 case 4: return BFD_RELOC_32;
1991 case 8: return BFD_RELOC_64;
1992 }
3956db08
JB		 1993 as_bad (_("cannot do %s %u byte relocation"),
1994 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1995 }
1996
bfb32b52 1997 abort ();
252b5132
RH		 1998 return BFD_RELOC_NONE;
1999}
2000
47926f60
KH		 2001/* Here we decide which fixups can be adjusted to make them relative to
2002 the beginning of the section instead of the symbol. Basically we need
2003 to make sure that the dynamic relocations are done correctly, so in
2004 some cases we force the original symbol to be used. */
2005
252b5132 2006int
e3bb37b5 2007tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2008{
6d249963 2009#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2010 if (!IS_ELF)
31312f95
AM		 2011 return 1;
2012
a161fe53
AM		 2013 /* Don't adjust pc-relative references to merge sections in 64-bit
2014 mode. */
2015 if (use_rela_relocations
2016 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2017 && fixP->fx_pcrel)
252b5132 2018 return 0;
31312f95 2019
8d01d9a9
AJ		 2020 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2021 and changed later by validate_fix. */
2022 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2023 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2024 return 0;
2025
ce8a8b2f 2026 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2027 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2028 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2029 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2030 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2031 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2032 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2033 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2034 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2035 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2036 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2037 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2038 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2039 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2040 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2041 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2042 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2043 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2044 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2045 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2046 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2047 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2048 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2049 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2050 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2051 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2052 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2053 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2054 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2055 return 0;
31312f95 2056#endif
252b5132
RH		 2057 return 1;
2058}
252b5132 2059
b4cac588 2060static int
e3bb37b5 2061intel_float_operand (const char *mnemonic)
252b5132 2062{
9306ca4a
JB		 2063 /* Note that the value returned is meaningful only for opcodes with (memory)
2064 operands, hence the code here is free to improperly handle opcodes that
2065 have no operands (for better performance and smaller code). */
2066
2067 if (mnemonic[0] != 'f')
2068 return 0; /* non-math */
2069
2070 switch (mnemonic[1])
2071 {
2072 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2073 the fs segment override prefix not currently handled because no
2074 call path can make opcodes without operands get here */
2075 case 'i':
2076 return 2 /* integer op */;
2077 case 'l':
2078 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2079 return 3; /* fldcw/fldenv */
2080 break;
2081 case 'n':
2082 if (mnemonic[2] != 'o' /* fnop */)
2083 return 3; /* non-waiting control op */
2084 break;
2085 case 'r':
2086 if (mnemonic[2] == 's')
2087 return 3; /* frstor/frstpm */
2088 break;
2089 case 's':
2090 if (mnemonic[2] == 'a')
2091 return 3; /* fsave */
2092 if (mnemonic[2] == 't')
2093 {
2094 switch (mnemonic[3])
2095 {
2096 case 'c': /* fstcw */
2097 case 'd': /* fstdw */
2098 case 'e': /* fstenv */
2099 case 's': /* fsts[gw] */
2100 return 3;
2101 }
2102 }
2103 break;
2104 case 'x':
2105 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2106 return 0; /* fxsave/fxrstor are not really math ops */
2107 break;
2108 }
252b5132 2109
9306ca4a 2110 return 1;
252b5132
RH		 2111}
2112
2113/* This is the guts of the machine-dependent assembler. LINE points to a
2114 machine dependent instruction. This function is supposed to emit
2115 the frags/bytes it assembles to. */
2116
2117void
2118md_assemble (line)
2119 char *line;
2120{
40fb9820 2121 unsigned int j;
252b5132
RH		 2122 char mnemonic[MAX_MNEM_SIZE];
2123
47926f60 2124 /* Initialize globals. */
252b5132
RH		 2125 memset (&i, '\0', sizeof (i));
2126 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2127 i.reloc[j] = NO_RELOC;
252b5132
RH		 2128 memset (disp_expressions, '\0', sizeof (disp_expressions));
2129 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2130 save_stack_p = save_stack;
252b5132
RH		 2131
2132 /* First parse an instruction mnemonic & call i386_operand for the operands.
2133 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2134 start of a (possibly prefixed) mnemonic. */
252b5132 2135
29b0f896
AM		 2136 line = parse_insn (line, mnemonic);
2137 if (line == NULL)
2138 return;
252b5132 2139
29b0f896
AM		 2140 line = parse_operands (line, mnemonic);
2141 if (line == NULL)
2142 return;
252b5132 2143
29b0f896
AM		 2144 /* Now we've parsed the mnemonic into a set of templates, and have the
2145 operands at hand. */
2146
2147 /* All intel opcodes have reversed operands except for "bound" and
2148 "enter". We also don't reverse intersegment "jmp" and "call"
2149 instructions with 2 immediate operands so that the immediate segment
050dfa73 2150 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2151 if (intel_syntax
2152 && i.operands > 1
29b0f896 2153 && (strcmp (mnemonic, "bound") != 0)
30123838 2154 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2155 && !(operand_type_check (i.types[0], imm)
2156 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2157 swap_operands ();
2158
ec56d5c0
JB		 2159 /* The order of the immediates should be reversed
2160 for 2 immediates extrq and insertq instructions */
2161 if (i.imm_operands == 2
2162 && (strcmp (mnemonic, "extrq") == 0
2163 || strcmp (mnemonic, "insertq") == 0))
2164 swap_2_operands (0, 1);
2165
29b0f896
AM		 2166 if (i.imm_operands)
2167 optimize_imm ();
2168
b300c311
L		 2169 /* Don't optimize displacement for movabs since it only takes 64bit
2170 displacement. */
2171 if (i.disp_operands
2172 && (flag_code != CODE_64BIT
2173 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2174 optimize_disp ();
2175
2176 /* Next, we find a template that matches the given insn,
2177 making sure the overlap of the given operands types is consistent
2178 with the template operand types. */
252b5132 2179
29b0f896
AM		 2180 if (!match_template ())
2181 return;
252b5132 2182
cd61ebfe
AM		 2183 if (intel_syntax)
2184 {
2185 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
2186 if (SYSV386_COMPAT
2187 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
8a2ed489 2188 i.tm.base_opcode ^= Opcode_FloatR;
cd61ebfe
AM		 2189
2190 /* Zap movzx and movsx suffix. The suffix may have been set from
2191 "word ptr" or "byte ptr" on the source operand, but we'll use
2192 the suffix later to choose the destination register. */
2193 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 2194 {
2195 if (i.reg_operands < 2
2196 && !i.suffix
40fb9820
L		 2197 && (!i.tm.opcode_modifier.no_bsuf
2198 || !i.tm.opcode_modifier.no_wsuf
2199 || !i.tm.opcode_modifier.no_lsuf
2200 || !i.tm.opcode_modifier.no_ssuf
2201 || !i.tm.opcode_modifier.no_xsuf
2202 || !i.tm.opcode_modifier.no_qsuf))
9306ca4a
JB		 2203 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2204
2205 i.suffix = 0;
2206 }
cd61ebfe 2207 }
24eab124 2208
40fb9820 2209 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2210 if (!add_prefix (FWAIT_OPCODE))
2211 return;
252b5132 2212
29b0f896 2213 /* Check string instruction segment overrides. */
40fb9820 2214 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2215 {
2216 if (!check_string ())
5dd0794d 2217 return;
29b0f896 2218 }
5dd0794d 2219
29b0f896
AM		 2220 if (!process_suffix ())
2221 return;
e413e4e9 2222
29b0f896
AM		 2223 /* Make still unresolved immediate matches conform to size of immediate
2224 given in i.suffix. */
2225 if (!finalize_imm ())
2226 return;
252b5132 2227
40fb9820 2228 if (i.types[0].bitfield.imm1)
29b0f896 2229 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2230
40fb9820 2231 for (j = 0; j < 3; j++)
c6fb90c8
L		 2232 if (i.types[j].bitfield.inoutportreg
2233 || i.types[j].bitfield.shiftcount
2234 || i.types[j].bitfield.acc
2235 || i.types[j].bitfield.floatacc)
40fb9820
L		 2236 i.reg_operands--;
2237
2238 if (i.tm.opcode_modifier.immext)
29b0f896 2239 {
02fc3089
L		 2240 expressionS *exp;
2241
40fb9820 2242 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
ca164297 2243 {
b7d9ef37 2244 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 2245 operands with an opcode suffix which is coded in the same
2246 place as an 8-bit immediate field would be. Here we check
2247 those operands and remove them afterwards. */
2248 unsigned int x;
2249
a4622f40 2250 for (x = 0; x < i.operands; x++)
ca164297 2251 if (i.op[x].regs->reg_num != x)
a540244d
L		 2252 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2253 register_prefix,
2254 i.op[x].regs->reg_name,
2255 x + 1,
2256 i.tm.name);
ca164297
L		 2257 i.operands = 0;
2258 }
2259
29b0f896
AM		 2260 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2261 opcode suffix which is coded in the same place as an 8-bit
2262 immediate field would be. Here we fake an 8-bit immediate
85f10a01
MM		 2263 operand from the opcode suffix stored in tm.extension_opcode.
2264 SSE5 also uses this encoding, for some of its 3 argument
2265 instructions. */
252b5132 2266
85f10a01
MM		 2267 assert (i.imm_operands == 0
2268 && (i.operands <= 2
2269 || (i.tm.cpu_flags.bitfield.cpusse5
2270 && i.operands <= 3)));
252b5132 2271
29b0f896
AM		 2272 exp = &im_expressions[i.imm_operands++];
2273 i.op[i.operands].imms = exp;
c6fb90c8 2274 UINTS_CLEAR (i.types[i.operands]);
40fb9820
L		 2275 i.types[i.operands].bitfield.imm8 = 1;
2276 i.operands++;
29b0f896
AM		 2277 exp->X_op = O_constant;
2278 exp->X_add_number = i.tm.extension_opcode;
2279 i.tm.extension_opcode = None;
2280 }
252b5132 2281
29b0f896
AM		 2282 /* For insns with operands there are more diddles to do to the opcode. */
2283 if (i.operands)
2284 {
2285 if (!process_operands ())
2286 return;
2287 }
40fb9820 2288 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2289 {
2290 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2291 as_warn (_("translating to `%sp'"), i.tm.name);
2292 }
252b5132 2293
29b0f896
AM		 2294 /* Handle conversion of 'int $3' --> special int3 insn. */
2295 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2296 {
2297 i.tm.base_opcode = INT3_OPCODE;
2298 i.imm_operands = 0;
2299 }
252b5132 2300
40fb9820
L		 2301 if ((i.tm.opcode_modifier.jump
2302 || i.tm.opcode_modifier.jumpbyte
2303 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2304 && i.op[0].disps->X_op == O_constant)
2305 {
2306 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2307 the absolute address given by the constant. Since ix86 jumps and
2308 calls are pc relative, we need to generate a reloc. */
2309 i.op[0].disps->X_add_symbol = &abs_symbol;
2310 i.op[0].disps->X_op = O_symbol;
2311 }
252b5132 2312
40fb9820 2313 if (i.tm.opcode_modifier.rex64)
161a04f6 2314 i.rex |= REX_W;
252b5132 2315
29b0f896
AM		 2316 /* For 8 bit registers we need an empty rex prefix. Also if the
2317 instruction already has a prefix, we need to convert old
2318 registers to new ones. */
773f551c 2319
40fb9820 2320 if ((i.types[0].bitfield.reg8
29b0f896 2321 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2322 || (i.types[1].bitfield.reg8
29b0f896 2323 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2324 || ((i.types[0].bitfield.reg8
2325 || i.types[1].bitfield.reg8)
29b0f896
AM		 2326 && i.rex != 0))
2327 {
2328 int x;
726c5dcd 2329
29b0f896
AM		 2330 i.rex |= REX_OPCODE;
2331 for (x = 0; x < 2; x++)
2332 {
2333 /* Look for 8 bit operand that uses old registers. */
40fb9820 2334 if (i.types[x].bitfield.reg8
29b0f896 2335 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2336 {
29b0f896
AM		 2337 /* In case it is "hi" register, give up. */
2338 if (i.op[x].regs->reg_num > 3)
a540244d 2339 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2340 "instruction requiring REX prefix."),
a540244d 2341 register_prefix, i.op[x].regs->reg_name);
773f551c 2342
29b0f896
AM		 2343 /* Otherwise it is equivalent to the extended register.
2344 Since the encoding doesn't change this is merely
2345 cosmetic cleanup for debug output. */
2346
2347 i.op[x].regs = i.op[x].regs + 8;
773f551c 2348 }
29b0f896
AM		 2349 }
2350 }
773f551c 2351
85f10a01
MM		 2352 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2353 REX prefix. */
2354 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2355 {
2356 i.drex.rex = i.rex;
2357 i.rex = 0;
2358 }
2359 else if (i.rex != 0)
29b0f896
AM		 2360 add_prefix (REX_OPCODE | i.rex);
2361
2362 /* We are ready to output the insn. */
2363 output_insn ();
2364}
2365
2366static char *
e3bb37b5 2367parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2368{
2369 char *l = line;
2370 char *token_start = l;
2371 char *mnem_p;
5c6af06e
JB		 2372 int supported;
2373 const template *t;
29b0f896
AM		 2374
2375 /* Non-zero if we found a prefix only acceptable with string insns. */
2376 const char *expecting_string_instruction = NULL;
45288df1 2377
29b0f896
AM		 2378 while (1)
2379 {
2380 mnem_p = mnemonic;
2381 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2382 {
2383 mnem_p++;
2384 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2385 {
29b0f896
AM		 2386 as_bad (_("no such instruction: `%s'"), token_start);
2387 return NULL;
2388 }
2389 l++;
2390 }
2391 if (!is_space_char (*l)
2392 && *l != END_OF_INSN
e44823cf
JB		 2393 && (intel_syntax
2394 || (*l != PREFIX_SEPARATOR
2395 && *l != ',')))
29b0f896
AM		 2396 {
2397 as_bad (_("invalid character %s in mnemonic"),
2398 output_invalid (*l));
2399 return NULL;
2400 }
2401 if (token_start == l)
2402 {
e44823cf 2403 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2404 as_bad (_("expecting prefix; got nothing"));
2405 else
2406 as_bad (_("expecting mnemonic; got nothing"));
2407 return NULL;
2408 }
45288df1 2409
29b0f896
AM		 2410 /* Look up instruction (or prefix) via hash table. */
2411 current_templates = hash_find (op_hash, mnemonic);
47926f60 2412
29b0f896
AM		 2413 if (*l != END_OF_INSN
2414 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2415 && current_templates
40fb9820 2416 && current_templates->start->opcode_modifier.isprefix)
29b0f896 2417 {
c6fb90c8 2418 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 2419 {
2420 as_bad ((flag_code != CODE_64BIT
2421 ? _("`%s' is only supported in 64-bit mode")
2422 : _("`%s' is not supported in 64-bit mode")),
2423 current_templates->start->name);
2424 return NULL;
2425 }
29b0f896
AM		 2426 /* If we are in 16-bit mode, do not allow addr16 or data16.
2427 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 2428 if ((current_templates->start->opcode_modifier.size16
2429 || current_templates->start->opcode_modifier.size32)
29b0f896 2430 && flag_code != CODE_64BIT
40fb9820 2431 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 2432 ^ (flag_code == CODE_16BIT)))
2433 {
2434 as_bad (_("redundant %s prefix"),
2435 current_templates->start->name);
2436 return NULL;
45288df1 2437 }
29b0f896
AM		 2438 /* Add prefix, checking for repeated prefixes. */
2439 switch (add_prefix (current_templates->start->base_opcode))
2440 {
2441 case 0:
2442 return NULL;
2443 case 2:
2444 expecting_string_instruction = current_templates->start->name;
2445 break;
2446 }
2447 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2448 token_start = ++l;
2449 }
2450 else
2451 break;
2452 }
45288df1 2453
29b0f896
AM		 2454 if (!current_templates)
2455 {
2456 /* See if we can get a match by trimming off a suffix. */
2457 switch (mnem_p[-1])
2458 {
2459 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2460 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2461 i.suffix = SHORT_MNEM_SUFFIX;
2462 else
29b0f896
AM		 2463 case BYTE_MNEM_SUFFIX:
2464 case QWORD_MNEM_SUFFIX:
2465 i.suffix = mnem_p[-1];
2466 mnem_p[-1] = '\0';
2467 current_templates = hash_find (op_hash, mnemonic);
2468 break;
2469 case SHORT_MNEM_SUFFIX:
2470 case LONG_MNEM_SUFFIX:
2471 if (!intel_syntax)
2472 {
2473 i.suffix = mnem_p[-1];
2474 mnem_p[-1] = '\0';
2475 current_templates = hash_find (op_hash, mnemonic);
2476 }
2477 break;
252b5132 2478
29b0f896
AM		 2479 /* Intel Syntax. */
2480 case 'd':
2481 if (intel_syntax)
2482 {
9306ca4a 2483 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2484 i.suffix = SHORT_MNEM_SUFFIX;
2485 else
2486 i.suffix = LONG_MNEM_SUFFIX;
2487 mnem_p[-1] = '\0';
2488 current_templates = hash_find (op_hash, mnemonic);
2489 }
2490 break;
2491 }
2492 if (!current_templates)
2493 {
2494 as_bad (_("no such instruction: `%s'"), token_start);
2495 return NULL;
2496 }
2497 }
252b5132 2498
40fb9820
L		 2499 if (current_templates->start->opcode_modifier.jump
2500 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 2501 {
2502 /* Check for a branch hint. We allow ",pt" and ",pn" for
2503 predict taken and predict not taken respectively.
2504 I'm not sure that branch hints actually do anything on loop
2505 and jcxz insns (JumpByte) for current Pentium4 chips. They
2506 may work in the future and it doesn't hurt to accept them
2507 now. */
2508 if (l[0] == ',' && l[1] == 'p')
2509 {
2510 if (l[2] == 't')
2511 {
2512 if (!add_prefix (DS_PREFIX_OPCODE))
2513 return NULL;
2514 l += 3;
2515 }
2516 else if (l[2] == 'n')
2517 {
2518 if (!add_prefix (CS_PREFIX_OPCODE))
2519 return NULL;
2520 l += 3;
2521 }
2522 }
2523 }
2524 /* Any other comma loses. */
2525 if (*l == ',')
2526 {
2527 as_bad (_("invalid character %s in mnemonic"),
2528 output_invalid (*l));
2529 return NULL;
2530 }
252b5132 2531
29b0f896 2532 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2533 supported = 0;
2534 for (t = current_templates->start; t < current_templates->end; ++t)
2535 {
40fb9820 2536 if (cpu_flags_match (t->cpu_flags))
64e74474 2537 supported |= 1;
c6fb90c8 2538 if (cpu_flags_check_cpu64 (t->cpu_flags))
64e74474 2539 supported |= 2;
5c6af06e
JB		 2540 }
2541 if (!(supported & 2))
2542 {
2543 as_bad (flag_code == CODE_64BIT
2544 ? _("`%s' is not supported in 64-bit mode")
2545 : _("`%s' is only supported in 64-bit mode"),
2546 current_templates->start->name);
2547 return NULL;
2548 }
2549 if (!(supported & 1))
29b0f896 2550 {
5c6af06e
JB		 2551 as_warn (_("`%s' is not supported on `%s%s'"),
2552 current_templates->start->name,
2553 cpu_arch_name,
2554 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896 2555 }
40fb9820
L		 2556 else if (!cpu_arch_flags.bitfield.cpui386
2557 && (flag_code != CODE_16BIT))
29b0f896
AM		 2558 {
2559 as_warn (_("use .code16 to ensure correct addressing mode"));
2560 }
252b5132 2561
29b0f896 2562 /* Check for rep/repne without a string instruction. */
f41bbced 2563 if (expecting_string_instruction)
29b0f896 2564 {
f41bbced
JB		 2565 static templates override;
2566
2567 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 2568 if (t->opcode_modifier.isstring)
f41bbced
JB		 2569 break;
2570 if (t >= current_templates->end)
2571 {
2572 as_bad (_("expecting string instruction after `%s'"),
64e74474 2573 expecting_string_instruction);
f41bbced
JB		 2574 return NULL;
2575 }
2576 for (override.start = t; t < current_templates->end; ++t)
40fb9820 2577 if (!t->opcode_modifier.isstring)
f41bbced
JB		 2578 break;
2579 override.end = t;
2580 current_templates = &override;
29b0f896 2581 }
252b5132 2582
29b0f896
AM		 2583 return l;
2584}
252b5132 2585
29b0f896 2586static char *
e3bb37b5 2587parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 2588{
2589 char *token_start;
3138f287 2590
29b0f896
AM		 2591 /* 1 if operand is pending after ','. */
2592 unsigned int expecting_operand = 0;
252b5132 2593
29b0f896
AM		 2594 /* Non-zero if operand parens not balanced. */
2595 unsigned int paren_not_balanced;
2596
2597 while (*l != END_OF_INSN)
2598 {
2599 /* Skip optional white space before operand. */
2600 if (is_space_char (*l))
2601 ++l;
2602 if (!is_operand_char (*l) && *l != END_OF_INSN)
2603 {
2604 as_bad (_("invalid character %s before operand %d"),
2605 output_invalid (*l),
2606 i.operands + 1);
2607 return NULL;
2608 }
2609 token_start = l; /* after white space */
2610 paren_not_balanced = 0;
2611 while (paren_not_balanced || *l != ',')
2612 {
2613 if (*l == END_OF_INSN)
2614 {
2615 if (paren_not_balanced)
2616 {
2617 if (!intel_syntax)
2618 as_bad (_("unbalanced parenthesis in operand %d."),
2619 i.operands + 1);
2620 else
2621 as_bad (_("unbalanced brackets in operand %d."),
2622 i.operands + 1);
2623 return NULL;
2624 }
2625 else
2626 break; /* we are done */
2627 }
2628 else if (!is_operand_char (*l) && !is_space_char (*l))
2629 {
2630 as_bad (_("invalid character %s in operand %d"),
2631 output_invalid (*l),
2632 i.operands + 1);
2633 return NULL;
2634 }
2635 if (!intel_syntax)
2636 {
2637 if (*l == '(')
2638 ++paren_not_balanced;
2639 if (*l == ')')
2640 --paren_not_balanced;
2641 }
2642 else
2643 {
2644 if (*l == '[')
2645 ++paren_not_balanced;
2646 if (*l == ']')
2647 --paren_not_balanced;
2648 }
2649 l++;
2650 }
2651 if (l != token_start)
2652 { /* Yes, we've read in another operand. */
2653 unsigned int operand_ok;
2654 this_operand = i.operands++;
2655 if (i.operands > MAX_OPERANDS)
2656 {
2657 as_bad (_("spurious operands; (%d operands/instruction max)"),
2658 MAX_OPERANDS);
2659 return NULL;
2660 }
2661 /* Now parse operand adding info to 'i' as we go along. */
2662 END_STRING_AND_SAVE (l);
2663
2664 if (intel_syntax)
2665 operand_ok =
2666 i386_intel_operand (token_start,
2667 intel_float_operand (mnemonic));
2668 else
2669 operand_ok = i386_operand (token_start);
2670
2671 RESTORE_END_STRING (l);
2672 if (!operand_ok)
2673 return NULL;
2674 }
2675 else
2676 {
2677 if (expecting_operand)
2678 {
2679 expecting_operand_after_comma:
2680 as_bad (_("expecting operand after ','; got nothing"));
2681 return NULL;
2682 }
2683 if (*l == ',')
2684 {
2685 as_bad (_("expecting operand before ','; got nothing"));
2686 return NULL;
2687 }
2688 }
7f3f1ea2 2689
29b0f896
AM		 2690 /* Now *l must be either ',' or END_OF_INSN. */
2691 if (*l == ',')
2692 {
2693 if (*++l == END_OF_INSN)
2694 {
2695 /* Just skip it, if it's \n complain. */
2696 goto expecting_operand_after_comma;
2697 }
2698 expecting_operand = 1;
2699 }
2700 }
2701 return l;
2702}
7f3f1ea2 2703
050dfa73 2704static void
4d456e3d 2705swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 2706{
2707 union i386_op temp_op;
40fb9820 2708 i386_operand_type temp_type;
050dfa73 2709 enum bfd_reloc_code_real temp_reloc;
4eed87de 2710
050dfa73
MM		 2711 temp_type = i.types[xchg2];
2712 i.types[xchg2] = i.types[xchg1];
2713 i.types[xchg1] = temp_type;
2714 temp_op = i.op[xchg2];
2715 i.op[xchg2] = i.op[xchg1];
2716 i.op[xchg1] = temp_op;
2717 temp_reloc = i.reloc[xchg2];
2718 i.reloc[xchg2] = i.reloc[xchg1];
2719 i.reloc[xchg1] = temp_reloc;
2720}
2721
29b0f896 2722static void
e3bb37b5 2723swap_operands (void)
29b0f896 2724{
b7c61d9a 2725 switch (i.operands)
050dfa73 2726 {
b7c61d9a 2727 case 4:
4d456e3d 2728 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 2729 case 3:
2730 case 2:
4d456e3d 2731 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 2732 break;
2733 default:
2734 abort ();
29b0f896 2735 }
29b0f896
AM		 2736
2737 if (i.mem_operands == 2)
2738 {
2739 const seg_entry *temp_seg;
2740 temp_seg = i.seg[0];
2741 i.seg[0] = i.seg[1];
2742 i.seg[1] = temp_seg;
2743 }
2744}
252b5132 2745
29b0f896
AM		 2746/* Try to ensure constant immediates are represented in the smallest
2747 opcode possible. */
2748static void
e3bb37b5 2749optimize_imm (void)
29b0f896
AM		 2750{
2751 char guess_suffix = 0;
2752 int op;
252b5132 2753
29b0f896
AM		 2754 if (i.suffix)
2755 guess_suffix = i.suffix;
2756 else if (i.reg_operands)
2757 {
2758 /* Figure out a suffix from the last register operand specified.
2759 We can't do this properly yet, ie. excluding InOutPortReg,
2760 but the following works for instructions with immediates.
2761 In any case, we can't set i.suffix yet. */
2762 for (op = i.operands; --op >= 0;)
40fb9820
L		 2763 if (i.types[op].bitfield.reg8)
2764 {
2765 guess_suffix = BYTE_MNEM_SUFFIX;
2766 break;
2767 }
2768 else if (i.types[op].bitfield.reg16)
252b5132 2769 {
40fb9820
L		 2770 guess_suffix = WORD_MNEM_SUFFIX;
2771 break;
2772 }
2773 else if (i.types[op].bitfield.reg32)
2774 {
2775 guess_suffix = LONG_MNEM_SUFFIX;
2776 break;
2777 }
2778 else if (i.types[op].bitfield.reg64)
2779 {
2780 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 2781 break;
252b5132 2782 }
29b0f896
AM		 2783 }
2784 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2785 guess_suffix = WORD_MNEM_SUFFIX;
2786
2787 for (op = i.operands; --op >= 0;)
40fb9820 2788 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 2789 {
2790 switch (i.op[op].imms->X_op)
252b5132 2791 {
29b0f896
AM		 2792 case O_constant:
2793 /* If a suffix is given, this operand may be shortened. */
2794 switch (guess_suffix)
252b5132 2795 {
29b0f896 2796 case LONG_MNEM_SUFFIX:
40fb9820
L		 2797 i.types[op].bitfield.imm32 = 1;
2798 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 2799 break;
2800 case WORD_MNEM_SUFFIX:
40fb9820
L		 2801 i.types[op].bitfield.imm16 = 1;
2802 i.types[op].bitfield.imm32 = 1;
2803 i.types[op].bitfield.imm32s = 1;
2804 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 2805 break;
2806 case BYTE_MNEM_SUFFIX:
40fb9820
L		 2807 i.types[op].bitfield.imm8 = 1;
2808 i.types[op].bitfield.imm8s = 1;
2809 i.types[op].bitfield.imm16 = 1;
2810 i.types[op].bitfield.imm32 = 1;
2811 i.types[op].bitfield.imm32s = 1;
2812 i.types[op].bitfield.imm64 = 1;
29b0f896 2813 break;
252b5132 2814 }
252b5132 2815
29b0f896
AM		 2816 /* If this operand is at most 16 bits, convert it
2817 to a signed 16 bit number before trying to see
2818 whether it will fit in an even smaller size.
2819 This allows a 16-bit operand such as $0xffe0 to
2820 be recognised as within Imm8S range. */
40fb9820 2821 if ((i.types[op].bitfield.imm16)
29b0f896 2822 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2823 {
29b0f896
AM		 2824 i.op[op].imms->X_add_number =
2825 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2826 }
40fb9820 2827 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 2828 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2829 == 0))
2830 {
2831 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2832 ^ ((offsetT) 1 << 31))
2833 - ((offsetT) 1 << 31));
2834 }
40fb9820 2835 i.types[op]
c6fb90c8
L		 2836 = operand_type_or (i.types[op],
2837 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 2838
29b0f896
AM		 2839 /* We must avoid matching of Imm32 templates when 64bit
2840 only immediate is available. */
2841 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 2842 i.types[op].bitfield.imm32 = 0;
29b0f896 2843 break;
252b5132 2844
29b0f896
AM		 2845 case O_absent:
2846 case O_register:
2847 abort ();
2848
2849 /* Symbols and expressions. */
2850 default:
9cd96992
JB		 2851 /* Convert symbolic operand to proper sizes for matching, but don't
2852 prevent matching a set of insns that only supports sizes other
2853 than those matching the insn suffix. */
2854 {
40fb9820 2855 i386_operand_type mask, allowed;
9cd96992
JB		 2856 const template *t;
2857
c6fb90c8
L		 2858 UINTS_CLEAR (mask);
2859 UINTS_CLEAR (allowed);
40fb9820 2860
4eed87de
AM		 2861 for (t = current_templates->start;
2862 t < current_templates->end;
2863 ++t)
c6fb90c8
L		 2864 allowed = operand_type_or (allowed,
2865 t->operand_types[op]);
9cd96992
JB		 2866 switch (guess_suffix)
2867 {
2868 case QWORD_MNEM_SUFFIX:
40fb9820
L		 2869 mask.bitfield.imm64 = 1;
2870 mask.bitfield.imm32s = 1;
9cd96992
JB		 2871 break;
2872 case LONG_MNEM_SUFFIX:
40fb9820 2873 mask.bitfield.imm32 = 1;
9cd96992
JB		 2874 break;
2875 case WORD_MNEM_SUFFIX:
40fb9820 2876 mask.bitfield.imm16 = 1;
9cd96992
JB		 2877 break;
2878 case BYTE_MNEM_SUFFIX:
40fb9820 2879 mask.bitfield.imm8 = 1;
9cd96992
JB		 2880 break;
2881 default:
9cd96992
JB		 2882 break;
2883 }
c6fb90c8
L		 2884 allowed = operand_type_and (mask, allowed);
2885 if (!UINTS_ALL_ZERO (allowed))
2886 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 2887 }
29b0f896 2888 break;
252b5132 2889 }
29b0f896
AM		 2890 }
2891}
47926f60 2892
29b0f896
AM		 2893/* Try to use the smallest displacement type too. */
2894static void
e3bb37b5 2895optimize_disp (void)
29b0f896
AM		 2896{
2897 int op;
3e73aa7c 2898
29b0f896 2899 for (op = i.operands; --op >= 0;)
40fb9820 2900 if (operand_type_check (i.types[op], disp))
252b5132 2901 {
b300c311 2902 if (i.op[op].disps->X_op == O_constant)
252b5132 2903 {
b300c311 2904 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2905
40fb9820 2906 if (i.types[op].bitfield.disp16
b300c311
L		 2907 && (disp & ~(offsetT) 0xffff) == 0)
2908 {
2909 /* If this operand is at most 16 bits, convert
2910 to a signed 16 bit number and don't use 64bit
2911 displacement. */
2912 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 2913 i.types[op].bitfield.disp64 = 0;
b300c311 2914 }
40fb9820 2915 if (i.types[op].bitfield.disp32
b300c311
L		 2916 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2917 {
2918 /* If this operand is at most 32 bits, convert
2919 to a signed 32 bit number and don't use 64bit
2920 displacement. */
2921 disp &= (((offsetT) 2 << 31) - 1);
2922 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 2923 i.types[op].bitfield.disp64 = 0;
b300c311 2924 }
40fb9820 2925 if (!disp && i.types[op].bitfield.baseindex)
b300c311 2926 {
40fb9820
L		 2927 i.types[op].bitfield.disp8 = 0;
2928 i.types[op].bitfield.disp16 = 0;
2929 i.types[op].bitfield.disp32 = 0;
2930 i.types[op].bitfield.disp32s = 0;
2931 i.types[op].bitfield.disp64 = 0;
b300c311
L		 2932 i.op[op].disps = 0;
2933 i.disp_operands--;
2934 }
2935 else if (flag_code == CODE_64BIT)
2936 {
2937 if (fits_in_signed_long (disp))
28a9d8f5 2938 {
40fb9820
L		 2939 i.types[op].bitfield.disp64 = 0;
2940 i.types[op].bitfield.disp32s = 1;
28a9d8f5 2941 }
b300c311 2942 if (fits_in_unsigned_long (disp))
40fb9820 2943 i.types[op].bitfield.disp32 = 1;
b300c311 2944 }
40fb9820
L		 2945 if ((i.types[op].bitfield.disp32
2946 || i.types[op].bitfield.disp32s
2947 || i.types[op].bitfield.disp16)
b300c311 2948 && fits_in_signed_byte (disp))
40fb9820 2949 i.types[op].bitfield.disp8 = 1;
252b5132 2950 }
67a4f2b7
AO		 2951 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2952 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2953 {
2954 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2955 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 2956 i.types[op].bitfield.disp8 = 0;
2957 i.types[op].bitfield.disp16 = 0;
2958 i.types[op].bitfield.disp32 = 0;
2959 i.types[op].bitfield.disp32s = 0;
2960 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 2961 }
2962 else
b300c311 2963 /* We only support 64bit displacement on constants. */
40fb9820 2964 i.types[op].bitfield.disp64 = 0;
252b5132 2965 }
29b0f896
AM		 2966}
2967
2968static int
e3bb37b5 2969match_template (void)
29b0f896
AM		 2970{
2971 /* Points to template once we've found it. */
2972 const template *t;
40fb9820 2973 i386_operand_type overlap0, overlap1, overlap2, overlap3;
29b0f896 2974 unsigned int found_reverse_match;
40fb9820
L		 2975 i386_opcode_modifier suffix_check;
2976 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 2977 int addr_prefix_disp;
a5c311ca 2978 unsigned int j;
c6fb90c8 2979 i386_cpu_flags overlap;
29b0f896 2980
f48ff2ae
L		 2981#if MAX_OPERANDS != 4
2982# error "MAX_OPERANDS must be 4."
2983#endif
2984
29b0f896 2985 found_reverse_match = 0;
539e75ad 2986 addr_prefix_disp = -1;
40fb9820
L		 2987
2988 memset (&suffix_check, 0, sizeof (suffix_check));
2989 if (i.suffix == BYTE_MNEM_SUFFIX)
2990 suffix_check.no_bsuf = 1;
2991 else if (i.suffix == WORD_MNEM_SUFFIX)
2992 suffix_check.no_wsuf = 1;
2993 else if (i.suffix == SHORT_MNEM_SUFFIX)
2994 suffix_check.no_ssuf = 1;
2995 else if (i.suffix == LONG_MNEM_SUFFIX)
2996 suffix_check.no_lsuf = 1;
2997 else if (i.suffix == QWORD_MNEM_SUFFIX)
2998 suffix_check.no_qsuf = 1;
2999 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
3000 suffix_check.no_xsuf = 1;
29b0f896 3001
45aa61fe 3002 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3003 {
539e75ad
L		 3004 addr_prefix_disp = -1;
3005
29b0f896
AM		 3006 /* Must have right number of operands. */
3007 if (i.operands != t->operands)
3008 continue;
3009
20592a94 3010 /* Check the suffix, except for some instructions in intel mode. */
40fb9820
L		 3011 if (((t->opcode_modifier.no_bsuf & suffix_check.no_bsuf)
3012 || (t->opcode_modifier.no_wsuf & suffix_check.no_wsuf)
3013 || (t->opcode_modifier.no_lsuf & suffix_check.no_lsuf)
3014 || (t->opcode_modifier.no_ssuf & suffix_check.no_ssuf)
3015 || (t->opcode_modifier.no_qsuf & suffix_check.no_qsuf)
3016 || (t->opcode_modifier.no_xsuf & suffix_check.no_xsuf))
3017 && !(intel_syntax && t->opcode_modifier.ignoresize))
29b0f896
AM		 3018 continue;
3019
a5c311ca
L		 3020 for (j = 0; j < MAX_OPERANDS; j++)
3021 operand_types [j] = t->operand_types [j];
539e75ad 3022
45aa61fe
AM		 3023 /* In general, don't allow 64-bit operands in 32-bit mode. */
3024 if (i.suffix == QWORD_MNEM_SUFFIX
3025 && flag_code != CODE_64BIT
3026 && (intel_syntax
40fb9820 3027 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3028 && !intel_float_operand (t->name))
3029 : intel_float_operand (t->name) != 2)
40fb9820
L		 3030 && ((!operand_types[0].bitfield.regmmx
3031 && !operand_types[0].bitfield.regxmm)
3032 || (!operand_types[t->operands > 1].bitfield.regmmx
3033 && !!operand_types[t->operands > 1].bitfield.regxmm))
45aa61fe
AM		 3034 && (t->base_opcode != 0x0fc7
3035 || t->extension_opcode != 1 /* cmpxchg8b */))
3036 continue;
3037
29b0f896 3038 /* Do not verify operands when there are none. */
c6fb90c8 3039 else
29b0f896 3040 {
c6fb90c8
L		 3041 overlap = cpu_flags_and (t->cpu_flags, cpu_arch_flags_not);
3042 if (!t->operands)
3043 {
3044 if (!UINTS_ALL_ZERO (overlap))
3045 continue;
3046 /* We've found a match; break out of loop. */
3047 break;
3048 }
29b0f896 3049 }
252b5132 3050
539e75ad
L		 3051 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3052 into Disp32/Disp16/Disp32 operand. */
3053 if (i.prefix[ADDR_PREFIX] != 0)
3054 {
40fb9820 3055 /* There should be only one Disp operand. */
539e75ad
L		 3056 switch (flag_code)
3057 {
3058 case CODE_16BIT:
40fb9820
L		 3059 for (j = 0; j < MAX_OPERANDS; j++)
3060 {
3061 if (operand_types[j].bitfield.disp16)
3062 {
3063 addr_prefix_disp = j;
3064 operand_types[j].bitfield.disp32 = 1;
3065 operand_types[j].bitfield.disp16 = 0;
3066 break;
3067 }
3068 }
539e75ad
L		 3069 break;
3070 case CODE_32BIT:
40fb9820
L		 3071 for (j = 0; j < MAX_OPERANDS; j++)
3072 {
3073 if (operand_types[j].bitfield.disp32)
3074 {
3075 addr_prefix_disp = j;
3076 operand_types[j].bitfield.disp32 = 0;
3077 operand_types[j].bitfield.disp16 = 1;
3078 break;
3079 }
3080 }
539e75ad
L		 3081 break;
3082 case CODE_64BIT:
40fb9820
L		 3083 for (j = 0; j < MAX_OPERANDS; j++)
3084 {
3085 if (operand_types[j].bitfield.disp64)
3086 {
3087 addr_prefix_disp = j;
3088 operand_types[j].bitfield.disp64 = 0;
3089 operand_types[j].bitfield.disp32 = 1;
3090 break;
3091 }
3092 }
539e75ad
L		 3093 break;
3094 }
539e75ad
L		 3095 }
3096
c6fb90c8 3097 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3098 switch (t->operands)
3099 {
3100 case 1:
40fb9820 3101 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3102 continue;
3103 break;
3104 case 2:
8b38ad71
L		 3105 /* xchg %eax, %eax is a special case. It is an aliase for nop
3106 only in 32bit mode and we can use opcode 0x90. In 64bit
3107 mode, we can't use 0x90 for xchg %eax, %eax since it should
3108 zero-extend %eax to %rax. */
3109 if (flag_code == CODE_64BIT
3110 && t->base_opcode == 0x90
c6fb90c8
L		 3111 && UINTS_EQUAL (i.types [0], acc32)
3112 && UINTS_EQUAL (i.types [1], acc32))
8b38ad71 3113 continue;
29b0f896 3114 case 3:
f48ff2ae 3115 case 4:
c6fb90c8 3116 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3117 if (!operand_type_match (overlap0, i.types[0])
3118 || !operand_type_match (overlap1, i.types[1])
cb712a9e 3119 /* monitor in SSE3 is a very special case. The first
708587a4 3120 register and the second register may have different
26186d74
L		 3121 sizes. The same applies to crc32 in SSE4.2. It is
3122 also true for invlpga, vmload, vmrun and vmsave in
3123 SVME. */
cb712a9e 3124 || !((t->base_opcode == 0x0f01
26186d74
L		 3125 && (t->extension_opcode == 0xc8
3126 || t->extension_opcode == 0xd8
3127 || t->extension_opcode == 0xda
3128 || t->extension_opcode == 0xdb
3129 || t->extension_opcode == 0xdf))
381d071f 3130 || t->base_opcode == 0xf20f38f1
40fb9820
L		 3131 || operand_type_register_match (overlap0, i.types[0],
3132 operand_types[0],
3133 overlap1, i.types[1],
3134 operand_types[1])))
29b0f896
AM		 3135 {
3136 /* Check if other direction is valid ... */
40fb9820 3137 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3138 continue;
3139
3140 /* Try reversing direction of operands. */
c6fb90c8
L		 3141 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3142 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3143 if (!operand_type_match (overlap0, i.types[0])
3144 || !operand_type_match (overlap1, i.types[1])
3145 || !operand_type_register_match (overlap0, i.types[0],
3146 operand_types[1],
3147 overlap1, i.types[1],
3148 operand_types[0]))
29b0f896
AM		 3149 {
3150 /* Does not match either direction. */
3151 continue;
3152 }
3153 /* found_reverse_match holds which of D or FloatDR
3154 we've found. */
40fb9820 3155 if (t->opcode_modifier.d)
8a2ed489 3156 found_reverse_match = Opcode_D;
40fb9820 3157 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3158 found_reverse_match = Opcode_FloatD;
3159 else
3160 found_reverse_match = 0;
40fb9820 3161 if (t->opcode_modifier.floatr)
8a2ed489 3162 found_reverse_match |= Opcode_FloatR;
29b0f896 3163 }
f48ff2ae 3164 else
29b0f896 3165 {
f48ff2ae 3166 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3167 switch (t->operands)
3168 {
3169 case 4:
c6fb90c8
L		 3170 overlap3 = operand_type_and (i.types[3],
3171 operand_types[3]);
d1cbb4db 3172 case 3:
c6fb90c8
L		 3173 overlap2 = operand_type_and (i.types[2],
3174 operand_types[2]);
d1cbb4db
L		 3175 break;
3176 }
29b0f896 3177
f48ff2ae
L		 3178 switch (t->operands)
3179 {
3180 case 4:
40fb9820
L		 3181 if (!operand_type_match (overlap3, i.types[3])
3182 || !operand_type_register_match (overlap2,
3183 i.types[2],
3184 operand_types[2],
3185 overlap3,
3186 i.types[3],
3187 operand_types[3]))
f48ff2ae
L		 3188 continue;
3189 case 3:
3190 /* Here we make use of the fact that there are no
3191 reverse match 3 operand instructions, and all 3
3192 operand instructions only need to be checked for
3193 register consistency between operands 2 and 3. */
40fb9820
L		 3194 if (!operand_type_match (overlap2, i.types[2])
3195 || !operand_type_register_match (overlap1,
3196 i.types[1],
3197 operand_types[1],
3198 overlap2,
3199 i.types[2],
3200 operand_types[2]))
f48ff2ae
L		 3201 continue;
3202 break;
3203 }
29b0f896 3204 }
f48ff2ae 3205 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3206 slip through to break. */
3207 }
c6fb90c8 3208 if (!UINTS_ALL_ZERO (overlap))
29b0f896
AM		 3209 {
3210 found_reverse_match = 0;
3211 continue;
3212 }
3213 /* We've found a match; break out of loop. */
3214 break;
3215 }
3216
3217 if (t == current_templates->end)
3218 {
3219 /* We found no match. */
3220 as_bad (_("suffix or operands invalid for `%s'"),
3221 current_templates->start->name);
3222 return 0;
3223 }
252b5132 3224
29b0f896
AM		 3225 if (!quiet_warnings)
3226 {
3227 if (!intel_syntax
40fb9820
L		 3228 && (i.types[0].bitfield.jumpabsolute
3229 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3230 {
3231 as_warn (_("indirect %s without `*'"), t->name);
3232 }
3233
40fb9820
L		 3234 if (t->opcode_modifier.isprefix
3235 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3236 {
3237 /* Warn them that a data or address size prefix doesn't
3238 affect assembly of the next line of code. */
3239 as_warn (_("stand-alone `%s' prefix"), t->name);
3240 }
3241 }
3242
3243 /* Copy the template we found. */
3244 i.tm = *t;
539e75ad
L		 3245
3246 if (addr_prefix_disp != -1)
3247 i.tm.operand_types[addr_prefix_disp]
3248 = operand_types[addr_prefix_disp];
3249
29b0f896
AM		 3250 if (found_reverse_match)
3251 {
3252 /* If we found a reverse match we must alter the opcode
3253 direction bit. found_reverse_match holds bits to change
3254 (different for int & float insns). */
3255
3256 i.tm.base_opcode ^= found_reverse_match;
3257
539e75ad
L		 3258 i.tm.operand_types[0] = operand_types[1];
3259 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3260 }
3261
3262 return 1;
3263}
3264
3265static int
e3bb37b5 3266check_string (void)
29b0f896 3267{
40fb9820
L		 3268 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3269 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3270 {
3271 if (i.seg[0] != NULL && i.seg[0] != &es)
3272 {
3273 as_bad (_("`%s' operand %d must use `%%es' segment"),
3274 i.tm.name,
3275 mem_op + 1);
3276 return 0;
3277 }
3278 /* There's only ever one segment override allowed per instruction.
3279 This instruction possibly has a legal segment override on the
3280 second operand, so copy the segment to where non-string
3281 instructions store it, allowing common code. */
3282 i.seg[0] = i.seg[1];
3283 }
40fb9820 3284 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3285 {
3286 if (i.seg[1] != NULL && i.seg[1] != &es)
3287 {
3288 as_bad (_("`%s' operand %d must use `%%es' segment"),
3289 i.tm.name,
3290 mem_op + 2);
3291 return 0;
3292 }
3293 }
3294 return 1;
3295}
3296
3297static int
543613e9 3298process_suffix (void)
29b0f896
AM		 3299{
3300 /* If matched instruction specifies an explicit instruction mnemonic
3301 suffix, use it. */
40fb9820
L		 3302 if (i.tm.opcode_modifier.size16)
3303 i.suffix = WORD_MNEM_SUFFIX;
3304 else if (i.tm.opcode_modifier.size32)
3305 i.suffix = LONG_MNEM_SUFFIX;
3306 else if (i.tm.opcode_modifier.size64)
3307 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 3308 else if (i.reg_operands)
3309 {
3310 /* If there's no instruction mnemonic suffix we try to invent one
3311 based on register operands. */
3312 if (!i.suffix)
3313 {
3314 /* We take i.suffix from the last register operand specified,
3315 Destination register type is more significant than source
381d071f
L		 3316 register type. crc32 in SSE4.2 prefers source register
3317 type. */
3318 if (i.tm.base_opcode == 0xf20f38f1)
3319 {
40fb9820
L		 3320 if (i.types[0].bitfield.reg16)
3321 i.suffix = WORD_MNEM_SUFFIX;
3322 else if (i.types[0].bitfield.reg32)
3323 i.suffix = LONG_MNEM_SUFFIX;
3324 else if (i.types[0].bitfield.reg64)
3325 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 3326 }
9344ff29 3327 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 3328 {
40fb9820 3329 if (i.types[0].bitfield.reg8)
20592a94
L		 3330 i.suffix = BYTE_MNEM_SUFFIX;
3331 }
381d071f
L		 3332
3333 if (!i.suffix)
3334 {
3335 int op;
3336
20592a94
L		 3337 if (i.tm.base_opcode == 0xf20f38f1
3338 || i.tm.base_opcode == 0xf20f38f0)
3339 {
3340 /* We have to know the operand size for crc32. */
3341 as_bad (_("ambiguous memory operand size for `%s`"),
3342 i.tm.name);
3343 return 0;
3344 }
3345
381d071f 3346 for (op = i.operands; --op >= 0;)
40fb9820 3347 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 3348 {
40fb9820
L		 3349 if (i.types[op].bitfield.reg8)
3350 {
3351 i.suffix = BYTE_MNEM_SUFFIX;
3352 break;
3353 }
3354 else if (i.types[op].bitfield.reg16)
3355 {
3356 i.suffix = WORD_MNEM_SUFFIX;
3357 break;
3358 }
3359 else if (i.types[op].bitfield.reg32)
3360 {
3361 i.suffix = LONG_MNEM_SUFFIX;
3362 break;
3363 }
3364 else if (i.types[op].bitfield.reg64)
3365 {
3366 i.suffix = QWORD_MNEM_SUFFIX;
3367 break;
3368 }
381d071f
L		 3369 }
3370 }
29b0f896
AM		 3371 }
3372 else if (i.suffix == BYTE_MNEM_SUFFIX)
3373 {
3374 if (!check_byte_reg ())
3375 return 0;
3376 }
3377 else if (i.suffix == LONG_MNEM_SUFFIX)
3378 {
3379 if (!check_long_reg ())
3380 return 0;
3381 }
3382 else if (i.suffix == QWORD_MNEM_SUFFIX)
3383 {
3384 if (!check_qword_reg ())
3385 return 0;
3386 }
3387 else if (i.suffix == WORD_MNEM_SUFFIX)
3388 {
3389 if (!check_word_reg ())
3390 return 0;
3391 }
40fb9820 3392 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 3393 /* Do nothing if the instruction is going to ignore the prefix. */
3394 ;
3395 else
3396 abort ();
3397 }
40fb9820 3398 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 3399 && !i.suffix
3400 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 3401 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 3402 {
3403 i.suffix = stackop_size;
3404 }
9306ca4a
JB		 3405 else if (intel_syntax
3406 && !i.suffix
40fb9820
L		 3407 && (i.tm.operand_types[0].bitfield.jumpabsolute
3408 || i.tm.opcode_modifier.jumpbyte
3409 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 3410 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3411 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 3412 {
3413 switch (flag_code)
3414 {
3415 case CODE_64BIT:
40fb9820 3416 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 3417 {
3418 i.suffix = QWORD_MNEM_SUFFIX;
3419 break;
3420 }
3421 case CODE_32BIT:
40fb9820 3422 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 3423 i.suffix = LONG_MNEM_SUFFIX;
3424 break;
3425 case CODE_16BIT:
40fb9820 3426 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 3427 i.suffix = WORD_MNEM_SUFFIX;
3428 break;
3429 }
3430 }
252b5132 3431
9306ca4a 3432 if (!i.suffix)
29b0f896 3433 {
9306ca4a
JB		 3434 if (!intel_syntax)
3435 {
40fb9820 3436 if (i.tm.opcode_modifier.w)
9306ca4a 3437 {
4eed87de
AM		 3438 as_bad (_("no instruction mnemonic suffix given and "
3439 "no register operands; can't size instruction"));
9306ca4a
JB		 3440 return 0;
3441 }
3442 }
3443 else
3444 {
40fb9820
L		 3445 unsigned int suffixes;
3446
3447 suffixes = !i.tm.opcode_modifier.no_bsuf;
3448 if (!i.tm.opcode_modifier.no_wsuf)
3449 suffixes |= 1 << 1;
3450 if (!i.tm.opcode_modifier.no_lsuf)
3451 suffixes |= 1 << 2;
3452 if (!i.tm.opcode_modifier.no_lsuf)
3453 suffixes |= 1 << 3;
3454 if (!i.tm.opcode_modifier.no_ssuf)
3455 suffixes |= 1 << 4;
3456 if (!i.tm.opcode_modifier.no_qsuf)
3457 suffixes |= 1 << 5;
3458
3459 /* There are more than suffix matches. */
3460 if (i.tm.opcode_modifier.w
9306ca4a 3461 || ((suffixes & (suffixes - 1))
40fb9820
L		 3462 && !i.tm.opcode_modifier.defaultsize
3463 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 3464 {
3465 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3466 return 0;
3467 }
3468 }
29b0f896 3469 }
252b5132 3470
9306ca4a
JB		 3471 /* Change the opcode based on the operand size given by i.suffix;
3472 We don't need to change things for byte insns. */
3473
29b0f896
AM		 3474 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
3475 {
3476 /* It's not a byte, select word/dword operation. */
40fb9820 3477 if (i.tm.opcode_modifier.w)
29b0f896 3478 {
40fb9820 3479 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 3480 i.tm.base_opcode |= 8;
3481 else
3482 i.tm.base_opcode |= 1;
3483 }
0f3f3d8b 3484
29b0f896
AM		 3485 /* Now select between word & dword operations via the operand
3486 size prefix, except for instructions that will ignore this
3487 prefix anyway. */
26186d74
L		 3488 if (i.tm.base_opcode == 0x0f01
3489 && (i.tm.extension_opcode == 0xc8
3490 || i.tm.extension_opcode == 0xd8
3491 || i.tm.extension_opcode == 0xda
3492 || i.tm.extension_opcode == 0xdb
3493 || i.tm.extension_opcode == 0xdf))
cb712a9e
L		 3494 {
3495 /* monitor in SSE3 is a very special case. The default size
3496 of AX is the size of mode. The address size override
26186d74
L		 3497 prefix will change the size of AX. It is also true for
3498 invlpga, vmload, vmrun and vmsave in SVME. */
40fb9820
L		 3499 if ((flag_code == CODE_32BIT
3500 && i.op->regs[0].reg_type.bitfield.reg16)
3501 || (flag_code != CODE_32BIT
3502 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 3503 if (!add_prefix (ADDR_PREFIX_OPCODE))
3504 return 0;
3505 }
3506 else if (i.suffix != QWORD_MNEM_SUFFIX
3507 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 3508 && !i.tm.opcode_modifier.ignoresize
3509 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 3510 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3511 || (flag_code == CODE_64BIT
40fb9820 3512 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 3513 {
3514 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 3515
40fb9820 3516 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 3517 prefix = ADDR_PREFIX_OPCODE;
252b5132 3518
29b0f896
AM		 3519 if (!add_prefix (prefix))
3520 return 0;
24eab124 3521 }
252b5132 3522
29b0f896
AM		 3523 /* Set mode64 for an operand. */
3524 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 3525 && flag_code == CODE_64BIT
40fb9820 3526 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 3527 {
3528 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 3529 need rex64. cmpxchg8b is also a special case. */
3530 if (! (i.operands == 2
3531 && i.tm.base_opcode == 0x90
3532 && i.tm.extension_opcode == None
c6fb90c8
L		 3533 && UINTS_EQUAL (i.types [0], acc64)
3534 && UINTS_EQUAL (i.types [1], acc64))
d9a5e5e5
L		 3535 && ! (i.operands == 1
3536 && i.tm.base_opcode == 0xfc7
3537 && i.tm.extension_opcode == 1
40fb9820
L		 3538 && !operand_type_check (i.types [0], reg)
3539 && operand_type_check (i.types [0], anymem)))
f6bee062 3540 i.rex |= REX_W;
46e883c5 3541 }
3e73aa7c 3542
29b0f896
AM		 3543 /* Size floating point instruction. */
3544 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 3545 if (i.tm.opcode_modifier.floatmf)
543613e9 3546 i.tm.base_opcode ^= 4;
29b0f896 3547 }
7ecd2f8b 3548
29b0f896
AM		 3549 return 1;
3550}
3e73aa7c 3551
29b0f896 3552static int
543613e9 3553check_byte_reg (void)
29b0f896
AM		 3554{
3555 int op;
543613e9 3556
29b0f896
AM		 3557 for (op = i.operands; --op >= 0;)
3558 {
3559 /* If this is an eight bit register, it's OK. If it's the 16 or
3560 32 bit version of an eight bit register, we will just use the
3561 low portion, and that's OK too. */
40fb9820 3562 if (i.types[op].bitfield.reg8)
29b0f896
AM		 3563 continue;
3564
c3ad16c0
L		 3565 /* movzx, movsx, pextrb and pinsrb should not generate this
3566 warning. */
29b0f896
AM		 3567 if (intel_syntax
3568 && (i.tm.base_opcode == 0xfb7
3569 || i.tm.base_opcode == 0xfb6
3570 || i.tm.base_opcode == 0x63
3571 || i.tm.base_opcode == 0xfbe
c3ad16c0
L		 3572 || i.tm.base_opcode == 0xfbf
3573 || i.tm.base_opcode == 0x660f3a14
3574 || i.tm.base_opcode == 0x660f3a20))
29b0f896
AM		 3575 continue;
3576
9344ff29
L		 3577 /* crc32 doesn't generate this warning. */
3578 if (i.tm.base_opcode == 0xf20f38f0)
3579 continue;
3580
40fb9820
L		 3581 if ((i.types[op].bitfield.reg16
3582 || i.types[op].bitfield.reg32
3583 || i.types[op].bitfield.reg64)
3584 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3585 {
3586 /* Prohibit these changes in the 64bit mode, since the
3587 lowering is more complicated. */
3588 if (flag_code == CODE_64BIT
40fb9820 3589 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 3590 {
2ca3ace5
L		 3591 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3592 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3593 i.suffix);
3594 return 0;
3595 }
3596#if REGISTER_WARNINGS
3597 if (!quiet_warnings
40fb9820 3598 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 3599 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3600 register_prefix,
40fb9820 3601 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 3602 ? REGNAM_AL - REGNAM_AX
3603 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 3604 register_prefix,
29b0f896
AM		 3605 i.op[op].regs->reg_name,
3606 i.suffix);
3607#endif
3608 continue;
3609 }
3610 /* Any other register is bad. */
40fb9820
L		 3611 if (i.types[op].bitfield.reg16
3612 || i.types[op].bitfield.reg32
3613 || i.types[op].bitfield.reg64
3614 || i.types[op].bitfield.regmmx
3615 || i.types[op].bitfield.regxmm
3616 || i.types[op].bitfield.sreg2
3617 || i.types[op].bitfield.sreg3
3618 || i.types[op].bitfield.control
3619 || i.types[op].bitfield.debug
3620 || i.types[op].bitfield.test
3621 || i.types[op].bitfield.floatreg
3622 || i.types[op].bitfield.floatacc)
29b0f896 3623 {
a540244d
L		 3624 as_bad (_("`%s%s' not allowed with `%s%c'"),
3625 register_prefix,
29b0f896
AM		 3626 i.op[op].regs->reg_name,
3627 i.tm.name,
3628 i.suffix);
3629 return 0;
3630 }
3631 }
3632 return 1;
3633}
3634
3635static int
e3bb37b5 3636check_long_reg (void)
29b0f896
AM		 3637{
3638 int op;
3639
3640 for (op = i.operands; --op >= 0;)
3641 /* Reject eight bit registers, except where the template requires
3642 them. (eg. movzb) */
40fb9820
L		 3643 if (i.types[op].bitfield.reg8
3644 && (i.tm.operand_types[op].bitfield.reg16
3645 || i.tm.operand_types[op].bitfield.reg32
3646 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3647 {
a540244d
L		 3648 as_bad (_("`%s%s' not allowed with `%s%c'"),
3649 register_prefix,
29b0f896
AM		 3650 i.op[op].regs->reg_name,
3651 i.tm.name,
3652 i.suffix);
3653 return 0;
3654 }
3655 /* Warn if the e prefix on a general reg is missing. */
3656 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3657 && i.types[op].bitfield.reg16
3658 && (i.tm.operand_types[op].bitfield.reg32
3659 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3660 {
3661 /* Prohibit these changes in the 64bit mode, since the
3662 lowering is more complicated. */
3663 if (flag_code == CODE_64BIT)
252b5132 3664 {
2ca3ace5
L		 3665 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3666 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3667 i.suffix);
3668 return 0;
252b5132 3669 }
29b0f896
AM		 3670#if REGISTER_WARNINGS
3671 else
a540244d
L		 3672 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3673 register_prefix,
29b0f896 3674 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 3675 register_prefix,
29b0f896
AM		 3676 i.op[op].regs->reg_name,
3677 i.suffix);
3678#endif
252b5132 3679 }
29b0f896 3680 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 3681 else if (i.types[op].bitfield.reg64
3682 && (i.tm.operand_types[op].bitfield.reg32
3683 || i.tm.operand_types[op].bitfield.acc))
252b5132 3684 {
34828aad
L		 3685 if (intel_syntax
3686 && i.tm.base_opcode == 0xf30f2d
40fb9820 3687 && !i.types[0].bitfield.regxmm)
34828aad
L		 3688 {
3689 /* cvtss2si converts DWORD memory to Reg64. We want
3690 REX byte. */
3691 i.suffix = QWORD_MNEM_SUFFIX;
3692 }
3693 else
3694 {
3695 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3696 register_prefix, i.op[op].regs->reg_name,
3697 i.suffix);
3698 return 0;
3699 }
29b0f896
AM		 3700 }
3701 return 1;
3702}
252b5132 3703
29b0f896 3704static int
e3bb37b5 3705check_qword_reg (void)
29b0f896
AM		 3706{
3707 int op;
252b5132 3708
29b0f896
AM		 3709 for (op = i.operands; --op >= 0; )
3710 /* Reject eight bit registers, except where the template requires
3711 them. (eg. movzb) */
40fb9820
L		 3712 if (i.types[op].bitfield.reg8
3713 && (i.tm.operand_types[op].bitfield.reg16
3714 || i.tm.operand_types[op].bitfield.reg32
3715 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3716 {
a540244d
L		 3717 as_bad (_("`%s%s' not allowed with `%s%c'"),
3718 register_prefix,
29b0f896
AM		 3719 i.op[op].regs->reg_name,
3720 i.tm.name,
3721 i.suffix);
3722 return 0;
3723 }
3724 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 3725 else if ((i.types[op].bitfield.reg16
3726 || i.types[op].bitfield.reg32)
3727 && (i.tm.operand_types[op].bitfield.reg32
3728 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3729 {
3730 /* Prohibit these changes in the 64bit mode, since the
3731 lowering is more complicated. */
34828aad
L		 3732 if (intel_syntax
3733 && i.tm.base_opcode == 0xf20f2d
40fb9820 3734 && !i.types[0].bitfield.regxmm)
34828aad
L		 3735 {
3736 /* cvtsd2si converts QWORD memory to Reg32. We don't want
3737 REX byte. */
3738 i.suffix = LONG_MNEM_SUFFIX;
3739 }
3740 else
3741 {
3742 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3743 register_prefix, i.op[op].regs->reg_name,
3744 i.suffix);
3745 return 0;
3746 }
252b5132 3747 }
29b0f896
AM		 3748 return 1;
3749}
252b5132 3750
29b0f896 3751static int
e3bb37b5 3752check_word_reg (void)
29b0f896
AM		 3753{
3754 int op;
3755 for (op = i.operands; --op >= 0;)
3756 /* Reject eight bit registers, except where the template requires
3757 them. (eg. movzb) */
40fb9820
L		 3758 if (i.types[op].bitfield.reg8
3759 && (i.tm.operand_types[op].bitfield.reg16
3760 || i.tm.operand_types[op].bitfield.reg32
3761 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3762 {
a540244d
L		 3763 as_bad (_("`%s%s' not allowed with `%s%c'"),
3764 register_prefix,
29b0f896
AM		 3765 i.op[op].regs->reg_name,
3766 i.tm.name,
3767 i.suffix);
3768 return 0;
3769 }
3770 /* Warn if the e prefix on a general reg is present. */
3771 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3772 && i.types[op].bitfield.reg32
3773 && (i.tm.operand_types[op].bitfield.reg16
3774 || i.tm.operand_types[op].bitfield.acc))
252b5132 3775 {
29b0f896
AM		 3776 /* Prohibit these changes in the 64bit mode, since the
3777 lowering is more complicated. */
3778 if (flag_code == CODE_64BIT)
252b5132 3779 {
2ca3ace5
L		 3780 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3781 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3782 i.suffix);
3783 return 0;
252b5132 3784 }
29b0f896
AM		 3785 else
3786#if REGISTER_WARNINGS
a540244d
L		 3787 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3788 register_prefix,
29b0f896 3789 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 3790 register_prefix,
29b0f896
AM		 3791 i.op[op].regs->reg_name,
3792 i.suffix);
3793#endif
3794 }
3795 return 1;
3796}
252b5132 3797
29b0f896 3798static int
40fb9820 3799update_imm (unsigned int j)
29b0f896 3800{
40fb9820
L		 3801 i386_operand_type overlap;
3802
c6fb90c8 3803 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
40fb9820
L		 3804 if ((overlap.bitfield.imm8
3805 || overlap.bitfield.imm8s
3806 || overlap.bitfield.imm16
3807 || overlap.bitfield.imm32
3808 || overlap.bitfield.imm32s
3809 || overlap.bitfield.imm64)
c6fb90c8
L		 3810 && !UINTS_EQUAL (overlap, imm8)
3811 && !UINTS_EQUAL (overlap, imm8s)
3812 && !UINTS_EQUAL (overlap, imm16)
3813 && !UINTS_EQUAL (overlap, imm32)
3814 && !UINTS_EQUAL (overlap, imm32s)
3815 && !UINTS_EQUAL (overlap, imm64))
29b0f896
AM		 3816 {
3817 if (i.suffix)
3818 {
40fb9820
L		 3819 i386_operand_type temp;
3820
c6fb90c8 3821 UINTS_CLEAR (temp);
40fb9820
L		 3822 if (i.suffix == BYTE_MNEM_SUFFIX)
3823 {
3824 temp.bitfield.imm8 = overlap.bitfield.imm8;
3825 temp.bitfield.imm8s = overlap.bitfield.imm8s;
3826 }
3827 else if (i.suffix == WORD_MNEM_SUFFIX)
3828 temp.bitfield.imm16 = overlap.bitfield.imm16;
3829 else if (i.suffix == QWORD_MNEM_SUFFIX)
3830 {
3831 temp.bitfield.imm64 = overlap.bitfield.imm64;
3832 temp.bitfield.imm32s = overlap.bitfield.imm32s;
3833 }
3834 else
3835 temp.bitfield.imm32 = overlap.bitfield.imm32;
3836 overlap = temp;
29b0f896 3837 }
c6fb90c8
L		 3838 else if (UINTS_EQUAL (overlap, imm16_32_32s)
3839 || UINTS_EQUAL (overlap, imm16_32)
3840 || UINTS_EQUAL (overlap, imm16_32s))
29b0f896 3841 {
c6fb90c8 3842 UINTS_CLEAR (overlap);
40fb9820
L		 3843 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3844 overlap.bitfield.imm16 = 1;
3845 else
3846 overlap.bitfield.imm32s = 1;
29b0f896 3847 }
c6fb90c8
L		 3848 if (!UINTS_EQUAL (overlap, imm8)
3849 && !UINTS_EQUAL (overlap, imm8s)
3850 && !UINTS_EQUAL (overlap, imm16)
3851 && !UINTS_EQUAL (overlap, imm32)
3852 && !UINTS_EQUAL (overlap, imm32s)
3853 && !UINTS_EQUAL (overlap, imm64))
29b0f896 3854 {
4eed87de
AM		 3855 as_bad (_("no instruction mnemonic suffix given; "
3856 "can't determine immediate size"));
29b0f896
AM		 3857 return 0;
3858 }
3859 }
40fb9820 3860 i.types[j] = overlap;
29b0f896 3861
40fb9820
L		 3862 return 1;
3863}
3864
3865static int
3866finalize_imm (void)
3867{
3868 unsigned int j;
29b0f896 3869
40fb9820
L		 3870 for (j = 0; j < 2; j++)
3871 if (update_imm (j) == 0)
3872 return 0;
3873
c6fb90c8 3874 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
40fb9820 3875 assert (operand_type_check (i.types[2], imm) == 0);
29b0f896
AM		 3876
3877 return 1;
3878}
3879
85f10a01
MM		 3880static void
3881process_drex (void)
3882{
3883 i.drex.modrm_reg = None;
3884 i.drex.modrm_regmem = None;
3885
3886 /* SSE5 4 operand instructions must have the destination the same as
3887 one of the inputs. Figure out the destination register and cache
3888 it away in the drex field, and remember which fields to use for
3889 the modrm byte. */
3890 if (i.tm.opcode_modifier.drex
3891 && i.tm.opcode_modifier.drexv
3892 && i.operands == 4)
3893 {
3894 i.tm.extension_opcode = None;
3895
3896 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
3897 if (i.types[0].bitfield.regxmm != 0
3898 && i.types[1].bitfield.regxmm != 0
3899 && i.types[2].bitfield.regxmm != 0
3900 && i.types[3].bitfield.regxmm != 0
3901 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3902 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3903 {
3904 /* Clear the arguments that are stored in drex. */
3905 UINTS_CLEAR (i.types[0]);
3906 UINTS_CLEAR (i.types[3]);
3907 i.reg_operands -= 2;
3908
3909 /* There are two different ways to encode a 4 operand
3910 instruction with all registers that uses OC1 set to
3911 0 or 1. Favor setting OC1 to 0 since this mimics the
3912 actions of other SSE5 assemblers. Use modrm encoding 2
3913 for register/register. Include the high order bit that
3914 is normally stored in the REX byte in the register
3915 field. */
3916 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
3917 i.drex.modrm_reg = 2;
3918 i.drex.modrm_regmem = 1;
3919 i.drex.reg = (i.op[3].regs->reg_num
3920 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3921 }
3922
3923 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
3924 else if (i.types[0].bitfield.regxmm != 0
3925 && i.types[1].bitfield.regxmm != 0
3926 && (i.types[2].bitfield.regxmm
3927 || operand_type_check (i.types[2], anymem))
3928 && i.types[3].bitfield.regxmm != 0
3929 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3930 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3931 {
3932 /* clear the arguments that are stored in drex */
3933 UINTS_CLEAR (i.types[0]);
3934 UINTS_CLEAR (i.types[3]);
3935 i.reg_operands -= 2;
3936
3937 /* Specify the modrm encoding for memory addressing. Include
3938 the high order bit that is normally stored in the REX byte
3939 in the register field. */
3940 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
3941 i.drex.modrm_reg = 1;
3942 i.drex.modrm_regmem = 2;
3943 i.drex.reg = (i.op[3].regs->reg_num
3944 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3945 }
3946
3947 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
3948 else if (i.types[0].bitfield.regxmm != 0
3949 && operand_type_check (i.types[1], anymem) != 0
3950 && i.types[2].bitfield.regxmm != 0
3951 && i.types[3].bitfield.regxmm != 0
3952 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3953 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3954 {
3955 /* Clear the arguments that are stored in drex. */
3956 UINTS_CLEAR (i.types[0]);
3957 UINTS_CLEAR (i.types[3]);
3958 i.reg_operands -= 2;
3959
3960 /* Specify the modrm encoding for memory addressing. Include
3961 the high order bit that is normally stored in the REX byte
3962 in the register field. */
3963 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
3964 i.drex.modrm_reg = 2;
3965 i.drex.modrm_regmem = 1;
3966 i.drex.reg = (i.op[3].regs->reg_num
3967 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3968 }
3969
3970 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
3971 else if (i.types[0].bitfield.regxmm != 0
3972 && i.types[1].bitfield.regxmm != 0
3973 && i.types[2].bitfield.regxmm != 0
3974 && i.types[3].bitfield.regxmm != 0
3975 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
3976 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
3977 {
3978 /* clear the arguments that are stored in drex */
3979 UINTS_CLEAR (i.types[2]);
3980 UINTS_CLEAR (i.types[3]);
3981 i.reg_operands -= 2;
3982
3983 /* There are two different ways to encode a 4 operand
3984 instruction with all registers that uses OC1 set to
3985 0 or 1. Favor setting OC1 to 0 since this mimics the
3986 actions of other SSE5 assemblers. Use modrm encoding
3987 2 for register/register. Include the high order bit that
3988 is normally stored in the REX byte in the register
3989 field. */
3990 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
3991 i.drex.modrm_reg = 1;
3992 i.drex.modrm_regmem = 0;
3993
3994 /* Remember the register, including the upper bits */
3995 i.drex.reg = (i.op[3].regs->reg_num
3996 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3997 }
3998
3999 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4000 else if (i.types[0].bitfield.regxmm != 0
4001 && (i.types[1].bitfield.regxmm
4002 || operand_type_check (i.types[1], anymem))
4003 && i.types[2].bitfield.regxmm != 0
4004 && i.types[3].bitfield.regxmm != 0
4005 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4006 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4007 {
4008 /* Clear the arguments that are stored in drex. */
4009 UINTS_CLEAR (i.types[2]);
4010 UINTS_CLEAR (i.types[3]);
4011 i.reg_operands -= 2;
4012
4013 /* Specify the modrm encoding and remember the register
4014 including the bits normally stored in the REX byte. */
4015 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4016 i.drex.modrm_reg = 0;
4017 i.drex.modrm_regmem = 1;
4018 i.drex.reg = (i.op[3].regs->reg_num
4019 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4020 }
4021
4022 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4023 else if (operand_type_check (i.types[0], anymem) != 0
4024 && i.types[1].bitfield.regxmm != 0
4025 && i.types[2].bitfield.regxmm != 0
4026 && i.types[3].bitfield.regxmm != 0
4027 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4028 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4029 {
4030 /* clear the arguments that are stored in drex */
4031 UINTS_CLEAR (i.types[2]);
4032 UINTS_CLEAR (i.types[3]);
4033 i.reg_operands -= 2;
4034
4035 /* Specify the modrm encoding and remember the register
4036 including the bits normally stored in the REX byte. */
4037 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4038 i.drex.modrm_reg = 1;
4039 i.drex.modrm_regmem = 0;
4040 i.drex.reg = (i.op[3].regs->reg_num
4041 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4042 }
4043
4044 else
4045 as_bad (_("Incorrect operands for the '%s' instruction"),
4046 i.tm.name);
4047 }
4048
4049 /* SSE5 instructions with the DREX byte where the only memory operand
4050 is in the 2nd argument, and the first and last xmm register must
4051 match, and is encoded in the DREX byte. */
4052 else if (i.tm.opcode_modifier.drex
4053 && !i.tm.opcode_modifier.drexv
4054 && i.operands == 4)
4055 {
4056 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4057 if (i.types[0].bitfield.regxmm != 0
4058 && (i.types[1].bitfield.regxmm
4059 || operand_type_check(i.types[1], anymem))
4060 && i.types[2].bitfield.regxmm != 0
4061 && i.types[3].bitfield.regxmm != 0
4062 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4063 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4064 {
4065 /* clear the arguments that are stored in drex */
4066 UINTS_CLEAR (i.types[0]);
4067 UINTS_CLEAR (i.types[3]);
4068 i.reg_operands -= 2;
4069
4070 /* Specify the modrm encoding and remember the register
4071 including the high bit normally stored in the REX
4072 byte. */
4073 i.drex.modrm_reg = 2;
4074 i.drex.modrm_regmem = 1;
4075 i.drex.reg = (i.op[3].regs->reg_num
4076 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4077 }
4078
4079 else
4080 as_bad (_("Incorrect operands for the '%s' instruction"),
4081 i.tm.name);
4082 }
4083
4084 /* SSE5 3 operand instructions that the result is a register, being
4085 either operand can be a memory operand, using OC0 to note which
4086 one is the memory. */
4087 else if (i.tm.opcode_modifier.drex
4088 && i.tm.opcode_modifier.drexv
4089 && i.operands == 3)
4090 {
4091 i.tm.extension_opcode = None;
4092
4093 /* Case 1: 3 operand insn, src1 = register. */
4094 if (i.types[0].bitfield.regxmm != 0
4095 && i.types[1].bitfield.regxmm != 0
4096 && i.types[2].bitfield.regxmm != 0)
4097 {
4098 /* Clear the arguments that are stored in drex. */
4099 UINTS_CLEAR (i.types[2]);
4100 i.reg_operands--;
4101
4102 /* Specify the modrm encoding and remember the register
4103 including the high bit normally stored in the REX byte. */
4104 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4105 i.drex.modrm_reg = 1;
4106 i.drex.modrm_regmem = 0;
4107 i.drex.reg = (i.op[2].regs->reg_num
4108 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4109 }
4110
4111 /* Case 2: 3 operand insn, src1 = memory. */
4112 else if (operand_type_check (i.types[0], anymem) != 0
4113 && i.types[1].bitfield.regxmm != 0
4114 && i.types[2].bitfield.regxmm != 0)
4115 {
4116 /* Clear the arguments that are stored in drex. */
4117 UINTS_CLEAR (i.types[2]);
4118 i.reg_operands--;
4119
4120 /* Specify the modrm encoding and remember the register
4121 including the high bit normally stored in the REX
4122 byte. */
4123 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4124 i.drex.modrm_reg = 1;
4125 i.drex.modrm_regmem = 0;
4126 i.drex.reg = (i.op[2].regs->reg_num
4127 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4128 }
4129
4130 /* Case 3: 3 operand insn, src2 = memory. */
4131 else if (i.types[0].bitfield.regxmm != 0
4132 && operand_type_check (i.types[1], anymem) != 0
4133 && i.types[2].bitfield.regxmm != 0)
4134 {
4135 /* Clear the arguments that are stored in drex. */
4136 UINTS_CLEAR (i.types[2]);
4137 i.reg_operands--;
4138
4139 /* Specify the modrm encoding and remember the register
4140 including the high bit normally stored in the REX byte. */
4141 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4142 i.drex.modrm_reg = 0;
4143 i.drex.modrm_regmem = 1;
4144 i.drex.reg = (i.op[2].regs->reg_num
4145 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4146 }
4147
4148 else
4149 as_bad (_("Incorrect operands for the '%s' instruction"),
4150 i.tm.name);
4151 }
4152
4153 /* SSE5 4 operand instructions that are the comparison instructions
4154 where the first operand is the immediate value of the comparison
4155 to be done. */
4156 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4157 {
4158 /* Case 1: 4 operand insn, src1 = reg/memory. */
4159 if (operand_type_check (i.types[0], imm) != 0
4160 && (i.types[1].bitfield.regxmm
4161 || operand_type_check (i.types[1], anymem))
4162 && i.types[2].bitfield.regxmm != 0
4163 && i.types[3].bitfield.regxmm != 0)
4164 {
4165 /* clear the arguments that are stored in drex */
4166 UINTS_CLEAR (i.types[3]);
4167 i.reg_operands--;
4168
4169 /* Specify the modrm encoding and remember the register
4170 including the high bit normally stored in the REX byte. */
4171 i.drex.modrm_reg = 2;
4172 i.drex.modrm_regmem = 1;
4173 i.drex.reg = (i.op[3].regs->reg_num
4174 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4175 }
4176
4177 /* Case 2: 3 operand insn with ImmExt that places the
4178 opcode_extension as an immediate argument. This is used for
4179 all of the varients of comparison that supplies the appropriate
4180 value as part of the instruction. */
4181 else if ((i.types[0].bitfield.regxmm
4182 || operand_type_check (i.types[0], anymem))
4183 && i.types[1].bitfield.regxmm != 0
4184 && i.types[2].bitfield.regxmm != 0
4185 && operand_type_check (i.types[3], imm) != 0)
4186 {
4187 /* clear the arguments that are stored in drex */
4188 UINTS_CLEAR (i.types[2]);
4189 i.reg_operands--;
4190
4191 /* Specify the modrm encoding and remember the register
4192 including the high bit normally stored in the REX byte. */
4193 i.drex.modrm_reg = 1;
4194 i.drex.modrm_regmem = 0;
4195 i.drex.reg = (i.op[2].regs->reg_num
4196 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4197 }
4198
4199 else
4200 as_bad (_("Incorrect operands for the '%s' instruction"),
4201 i.tm.name);
4202 }
4203
4204 else if (i.tm.opcode_modifier.drex
4205 || i.tm.opcode_modifier.drexv
4206 || i.tm.opcode_modifier.drexc)
4207 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4208}
4209
29b0f896 4210static int
e3bb37b5 4211process_operands (void)
29b0f896
AM		 4212{
4213 /* Default segment register this instruction will use for memory
4214 accesses. 0 means unknown. This is only for optimizing out
4215 unnecessary segment overrides. */
4216 const seg_entry *default_seg = 0;
4217
85f10a01
MM		 4218 /* Handle all of the DREX munging that SSE5 needs. */
4219 if (i.tm.opcode_modifier.drex
4220 || i.tm.opcode_modifier.drexv
4221 || i.tm.opcode_modifier.drexc)
4222 process_drex ();
4223
29b0f896
AM		 4224 /* The imul $imm, %reg instruction is converted into
4225 imul $imm, %reg, %reg, and the clr %reg instruction
4226 is converted into xor %reg, %reg. */
40fb9820 4227 if (i.tm.opcode_modifier.regkludge)
29b0f896 4228 {
40fb9820 4229 if (i.tm.cpu_flags.bitfield.cpusse4_1)
42903f7f
L		 4230 {
4231 /* The first operand in instruction blendvpd, blendvps and
4232 pblendvb in SSE4.1 is implicit and must be xmm0. */
4233 assert (i.operands == 3
4234 && i.reg_operands >= 2
c6fb90c8 4235 && UINTS_EQUAL (i.types[0], regxmm));
42903f7f
L		 4236 if (i.op[0].regs->reg_num != 0)
4237 {
4238 if (intel_syntax)
4239 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4240 i.tm.name, register_prefix);
4241 else
4242 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4243 i.tm.name, register_prefix);
4244 return 0;
4245 }
4246 i.op[0] = i.op[1];
4247 i.op[1] = i.op[2];
4248 i.types[0] = i.types[1];
4249 i.types[1] = i.types[2];
4250 i.operands--;
4251 i.reg_operands--;
4252
4253 /* We need to adjust fields in i.tm since they are used by
4254 build_modrm_byte. */
4255 i.tm.operand_types [0] = i.tm.operand_types [1];
4256 i.tm.operand_types [1] = i.tm.operand_types [2];
4257 i.tm.operands--;
4258 }
4259 else
4260 {
40fb9820
L		 4261 unsigned int first_reg_op;
4262
4263 if (operand_type_check (i.types[0], reg))
4264 first_reg_op = 0;
4265 else
4266 first_reg_op = 1;
42903f7f
L		 4267 /* Pretend we saw the extra register operand. */
4268 assert (i.reg_operands == 1
4269 && i.op[first_reg_op + 1].regs == 0);
4270 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4271 i.types[first_reg_op + 1] = i.types[first_reg_op];
4272 i.operands++;
4273 i.reg_operands++;
4274 }
29b0f896
AM		 4275 }
4276
40fb9820 4277 if (i.tm.opcode_modifier.shortform)
29b0f896 4278 {
40fb9820
L		 4279 if (i.types[0].bitfield.sreg2
4280 || i.types[0].bitfield.sreg3)
29b0f896 4281 {
4eed87de
AM		 4282 if (i.tm.base_opcode == POP_SEG_SHORT
4283 && i.op[0].regs->reg_num == 1)
29b0f896 4284 {
4eed87de
AM		 4285 as_bad (_("you can't `pop %%cs'"));
4286 return 0;
29b0f896 4287 }
4eed87de
AM		 4288 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4289 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4290 i.rex |= REX_B;
4eed87de
AM		 4291 }
4292 else
4293 {
85f10a01
MM		 4294 /* The register or float register operand is in operand
4295 0 or 1. */
40fb9820
L		 4296 unsigned int op;
4297
4298 if (i.types[0].bitfield.floatreg
4299 || operand_type_check (i.types[0], reg))
4300 op = 0;
4301 else
4302 op = 1;
4eed87de
AM		 4303 /* Register goes in low 3 bits of opcode. */
4304 i.tm.base_opcode |= i.op[op].regs->reg_num;
4305 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4306 i.rex |= REX_B;
40fb9820 4307 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4308 {
4eed87de
AM		 4309 /* Warn about some common errors, but press on regardless.
4310 The first case can be generated by gcc (<= 2.8.1). */
4311 if (i.operands == 2)
4312 {
4313 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 4314 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4315 register_prefix, i.op[1].regs->reg_name,
4316 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 4317 }
4318 else
4319 {
4320 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4321 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4322 register_prefix, i.op[0].regs->reg_name);
4eed87de 4323 }
29b0f896
AM		 4324 }
4325 }
4326 }
40fb9820 4327 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4328 {
4329 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4330 must be put into the modrm byte). Now, we make the modrm and
4331 index base bytes based on all the info we've collected. */
29b0f896
AM		 4332
4333 default_seg = build_modrm_byte ();
4334 }
8a2ed489 4335 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4336 {
4337 default_seg = &ds;
4338 }
40fb9820 4339 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4340 {
4341 /* For the string instructions that allow a segment override
4342 on one of their operands, the default segment is ds. */
4343 default_seg = &ds;
4344 }
4345
75178d9d
L		 4346 if (i.tm.base_opcode == 0x8d /* lea */
4347 && i.seg[0]
4348 && !quiet_warnings)
30123838 4349 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 4350
4351 /* If a segment was explicitly specified, and the specified segment
4352 is not the default, use an opcode prefix to select it. If we
4353 never figured out what the default segment is, then default_seg
4354 will be zero at this point, and the specified segment prefix will
4355 always be used. */
29b0f896
AM		 4356 if ((i.seg[0]) && (i.seg[0] != default_seg))
4357 {
4358 if (!add_prefix (i.seg[0]->seg_prefix))
4359 return 0;
4360 }
4361 return 1;
4362}
4363
4364static const seg_entry *
e3bb37b5 4365build_modrm_byte (void)
29b0f896
AM		 4366{
4367 const seg_entry *default_seg = 0;
4368
85f10a01
MM		 4369 /* SSE5 4 operand instructions are encoded in such a way that one of
4370 the inputs must match the destination register. Process_drex hides
4371 the 3rd argument in the drex field, so that by the time we get
4372 here, it looks to GAS as if this is a 2 operand instruction. */
4373 if ((i.tm.opcode_modifier.drex
4374 || i.tm.opcode_modifier.drexv
b5016f89 4375 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4376 && i.reg_operands == 2)
4377 {
4378 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
4379 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
4380
4381 i.rm.reg = reg->reg_num;
4382 i.rm.regmem = regmem->reg_num;
4383 i.rm.mode = 3;
4384 if ((reg->reg_flags & RegRex) != 0)
4385 i.rex |= REX_R;
4386 if ((regmem->reg_flags & RegRex) != 0)
4387 i.rex |= REX_B;
4388 }
4389
29b0f896
AM		 4390 /* i.reg_operands MUST be the number of real register operands;
4391 implicit registers do not count. */
85f10a01 4392 else if (i.reg_operands == 2)
29b0f896
AM		 4393 {
4394 unsigned int source, dest;
cab737b9
L		 4395
4396 switch (i.operands)
4397 {
4398 case 2:
4399 source = 0;
4400 break;
4401 case 3:
c81128dc
L		 4402 /* When there are 3 operands, one of them may be immediate,
4403 which may be the first or the last operand. Otherwise,
4404 the first operand must be shift count register (cl). */
4405 assert (i.imm_operands == 1
4406 || (i.imm_operands == 0
40fb9820
L		 4407 && i.types[0].bitfield.shiftcount));
4408 if (operand_type_check (i.types[0], imm)
4409 || i.types[0].bitfield.shiftcount)
4410 source = 1;
4411 else
4412 source = 0;
cab737b9
L		 4413 break;
4414 case 4:
4415 /* When there are 4 operands, the first two must be immediate
4416 operands. The source operand will be the 3rd one. */
4417 assert (i.imm_operands == 2
40fb9820
L		 4418 && operand_type_check (i.types[0], imm)
4419 && operand_type_check (i.types[1], imm));
cab737b9
L		 4420 source = 2;
4421 break;
4422 default:
4423 abort ();
4424 }
4425
29b0f896
AM		 4426 dest = source + 1;
4427
4428 i.rm.mode = 3;
4429 /* One of the register operands will be encoded in the i.tm.reg
4430 field, the other in the combined i.tm.mode and i.tm.regmem
4431 fields. If no form of this instruction supports a memory
4432 destination operand, then we assume the source operand may
4433 sometimes be a memory operand and so we need to store the
4434 destination in the i.rm.reg field. */
40fb9820
L		 4435 if (!i.tm.operand_types[dest].bitfield.regmem
4436 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 4437 {
4438 i.rm.reg = i.op[dest].regs->reg_num;
4439 i.rm.regmem = i.op[source].regs->reg_num;
4440 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4441 i.rex |= REX_R;
29b0f896 4442 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4443 i.rex |= REX_B;
29b0f896
AM		 4444 }
4445 else
4446 {
4447 i.rm.reg = i.op[source].regs->reg_num;
4448 i.rm.regmem = i.op[dest].regs->reg_num;
4449 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4450 i.rex |= REX_B;
29b0f896 4451 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4452 i.rex |= REX_R;
29b0f896 4453 }
161a04f6 4454 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 4455 {
40fb9820
L		 4456 if (!i.types[0].bitfield.control
4457 && !i.types[1].bitfield.control)
c4a530c5 4458 abort ();
161a04f6 4459 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 4460 add_prefix (LOCK_PREFIX_OPCODE);
4461 }
29b0f896
AM		 4462 }
4463 else
4464 { /* If it's not 2 reg operands... */
4465 if (i.mem_operands)
4466 {
4467 unsigned int fake_zero_displacement = 0;
99018f42 4468 unsigned int op;
4eed87de 4469
85f10a01
MM		 4470 /* This has been precalculated for SSE5 instructions
4471 that have a DREX field earlier in process_drex. */
b5016f89
L		 4472 if (i.tm.opcode_modifier.drex
4473 || i.tm.opcode_modifier.drexv
4474 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4475 op = i.drex.modrm_regmem;
4476 else
4477 {
c0209578
L		 4478 for (op = 0; op < i.operands; op++)
4479 if (operand_type_check (i.types[op], anymem))
4480 break;
4481 assert (op < i.operands);
85f10a01 4482 }
29b0f896
AM		 4483
4484 default_seg = &ds;
4485
4486 if (i.base_reg == 0)
4487 {
4488 i.rm.mode = 0;
4489 if (!i.disp_operands)
4490 fake_zero_displacement = 1;
4491 if (i.index_reg == 0)
4492 {
4493 /* Operand is just <disp> */
20f0a1fc 4494 if (flag_code == CODE_64BIT)
29b0f896
AM		 4495 {
4496 /* 64bit mode overwrites the 32bit absolute
4497 addressing by RIP relative addressing and
4498 absolute addressing is encoded by one of the
4499 redundant SIB forms. */
4500 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4501 i.sib.base = NO_BASE_REGISTER;
4502 i.sib.index = NO_INDEX_REGISTER;
fc225355 4503 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 4504 ? disp32s : disp32);
20f0a1fc 4505 }
fc225355
L		 4506 else if ((flag_code == CODE_16BIT)
4507 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 4508 {
4509 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 4510 i.types[op] = disp16;
20f0a1fc
NC		 4511 }
4512 else
4513 {
4514 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 4515 i.types[op] = disp32;
29b0f896
AM		 4516 }
4517 }
4518 else /* !i.base_reg && i.index_reg */
4519 {
4520 i.sib.index = i.index_reg->reg_num;
4521 i.sib.base = NO_BASE_REGISTER;
4522 i.sib.scale = i.log2_scale_factor;
4523 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 4524 i.types[op].bitfield.disp8 = 0;
4525 i.types[op].bitfield.disp16 = 0;
4526 i.types[op].bitfield.disp64 = 0;
29b0f896 4527 if (flag_code != CODE_64BIT)
40fb9820
L		 4528 {
4529 /* Must be 32 bit */
4530 i.types[op].bitfield.disp32 = 1;
4531 i.types[op].bitfield.disp32s = 0;
4532 }
29b0f896 4533 else
40fb9820
L		 4534 {
4535 i.types[op].bitfield.disp32 = 0;
4536 i.types[op].bitfield.disp32s = 1;
4537 }
29b0f896 4538 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4539 i.rex |= REX_X;
29b0f896
AM		 4540 }
4541 }
4542 /* RIP addressing for 64bit mode. */
20e192ab 4543 else if (i.base_reg->reg_num == RegRip)
29b0f896
AM		 4544 {
4545 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 4546 i.types[op].bitfield.disp8 = 0;
4547 i.types[op].bitfield.disp16 = 0;
4548 i.types[op].bitfield.disp32 = 0;
4549 i.types[op].bitfield.disp32s = 1;
4550 i.types[op].bitfield.disp64 = 0;
71903a11 4551 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 4552 if (! i.disp_operands)
4553 fake_zero_displacement = 1;
29b0f896 4554 }
40fb9820 4555 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 4556 {
4557 switch (i.base_reg->reg_num)
4558 {
4559 case 3: /* (%bx) */
4560 if (i.index_reg == 0)
4561 i.rm.regmem = 7;
4562 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4563 i.rm.regmem = i.index_reg->reg_num - 6;
4564 break;
4565 case 5: /* (%bp) */
4566 default_seg = &ss;
4567 if (i.index_reg == 0)
4568 {
4569 i.rm.regmem = 6;
40fb9820 4570 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 4571 {
4572 /* fake (%bp) into 0(%bp) */
40fb9820 4573 i.types[op].bitfield.disp8 = 1;
252b5132 4574 fake_zero_displacement = 1;
29b0f896
AM		 4575 }
4576 }
4577 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4578 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4579 break;
4580 default: /* (%si) -> 4 or (%di) -> 5 */
4581 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4582 }
4583 i.rm.mode = mode_from_disp_size (i.types[op]);
4584 }
4585 else /* i.base_reg and 32/64 bit mode */
4586 {
4587 if (flag_code == CODE_64BIT
40fb9820
L		 4588 && operand_type_check (i.types[op], disp))
4589 {
4590 i386_operand_type temp;
c6fb90c8 4591 UINTS_CLEAR (temp);
40fb9820
L		 4592 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4593 i.types[op] = temp;
4594 if (i.prefix[ADDR_PREFIX] == 0)
4595 i.types[op].bitfield.disp32s = 1;
4596 else
4597 i.types[op].bitfield.disp32 = 1;
4598 }
20f0a1fc 4599
29b0f896
AM		 4600 i.rm.regmem = i.base_reg->reg_num;
4601 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 4602 i.rex |= REX_B;
29b0f896
AM		 4603 i.sib.base = i.base_reg->reg_num;
4604 /* x86-64 ignores REX prefix bit here to avoid decoder
4605 complications. */
4606 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4607 {
4608 default_seg = &ss;
4609 if (i.disp_operands == 0)
4610 {
4611 fake_zero_displacement = 1;
40fb9820 4612 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 4613 }
4614 }
4615 else if (i.base_reg->reg_num == ESP_REG_NUM)
4616 {
4617 default_seg = &ss;
4618 }
4619 i.sib.scale = i.log2_scale_factor;
4620 if (i.index_reg == 0)
4621 {
4622 /* <disp>(%esp) becomes two byte modrm with no index
4623 register. We've already stored the code for esp
4624 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4625 Any base register besides %esp will not use the
4626 extra modrm byte. */
4627 i.sib.index = NO_INDEX_REGISTER;
4628#if !SCALE1_WHEN_NO_INDEX
8ed77a05
L		 4629 /* Another case where we force the second modrm
4630 byte. */
29b0f896
AM		 4631 if (i.log2_scale_factor)
4632 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 4633#endif
29b0f896
AM		 4634 }
4635 else
4636 {
4637 i.sib.index = i.index_reg->reg_num;
4638 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4639 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4640 i.rex |= REX_X;
29b0f896 4641 }
67a4f2b7
AO		 4642
4643 if (i.disp_operands
4644 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4645 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4646 i.rm.mode = 0;
4647 else
4648 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 4649 }
252b5132 4650
29b0f896
AM		 4651 if (fake_zero_displacement)
4652 {
4653 /* Fakes a zero displacement assuming that i.types[op]
4654 holds the correct displacement size. */
4655 expressionS *exp;
4656
4657 assert (i.op[op].disps == 0);
4658 exp = &disp_expressions[i.disp_operands++];
4659 i.op[op].disps = exp;
4660 exp->X_op = O_constant;
4661 exp->X_add_number = 0;
4662 exp->X_add_symbol = (symbolS *) 0;
4663 exp->X_op_symbol = (symbolS *) 0;
4664 }
4665 }
252b5132 4666
29b0f896
AM		 4667 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4668 (if any) based on i.tm.extension_opcode. Again, we must be
4669 careful to make sure that segment/control/debug/test/MMX
4670 registers are coded into the i.rm.reg field. */
4671 if (i.reg_operands)
4672 {
99018f42
L		 4673 unsigned int op;
4674
85f10a01
MM		 4675 /* This has been precalculated for SSE5 instructions
4676 that have a DREX field earlier in process_drex. */
b5016f89
L		 4677 if (i.tm.opcode_modifier.drex
4678 || i.tm.opcode_modifier.drexv
4679 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4680 {
4681 op = i.drex.modrm_reg;
4682 i.rm.reg = i.op[op].regs->reg_num;
4683 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4684 i.rex |= REX_R;
4685 }
4686 else
4687 {
c0209578
L		 4688 for (op = 0; op < i.operands; op++)
4689 if (i.types[op].bitfield.reg8
4690 || i.types[op].bitfield.reg16
4691 || i.types[op].bitfield.reg32
4692 || i.types[op].bitfield.reg64
4693 || i.types[op].bitfield.regmmx
4694 || i.types[op].bitfield.regxmm
4695 || i.types[op].bitfield.sreg2
4696 || i.types[op].bitfield.sreg3
4697 || i.types[op].bitfield.control
4698 || i.types[op].bitfield.debug
4699 || i.types[op].bitfield.test)
4700 break;
4701
4702 assert (op < i.operands);
99018f42 4703
85f10a01
MM		 4704 /* If there is an extension opcode to put here, the
4705 register number must be put into the regmem field. */
c0209578
L		 4706 if (i.tm.extension_opcode != None)
4707 {
4708 i.rm.regmem = i.op[op].regs->reg_num;
4709 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4710 i.rex |= REX_B;
4711 }
4712 else
4713 {
4714 i.rm.reg = i.op[op].regs->reg_num;
4715 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4716 i.rex |= REX_R;
4717 }
85f10a01 4718 }
252b5132 4719
29b0f896
AM		 4720 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4721 must set it to 3 to indicate this is a register operand
4722 in the regmem field. */
4723 if (!i.mem_operands)
4724 i.rm.mode = 3;
4725 }
252b5132 4726
29b0f896 4727 /* Fill in i.rm.reg field with extension opcode (if any). */
85f10a01
MM		 4728 if (i.tm.extension_opcode != None
4729 && !(i.tm.opcode_modifier.drex
4730 || i.tm.opcode_modifier.drexv
4731 || i.tm.opcode_modifier.drexc))
29b0f896
AM		 4732 i.rm.reg = i.tm.extension_opcode;
4733 }
4734 return default_seg;
4735}
252b5132 4736
29b0f896 4737static void
e3bb37b5 4738output_branch (void)
29b0f896
AM		 4739{
4740 char *p;
4741 int code16;
4742 int prefix;
4743 relax_substateT subtype;
4744 symbolS *sym;
4745 offsetT off;
4746
4747 code16 = 0;
4748 if (flag_code == CODE_16BIT)
4749 code16 = CODE16;
4750
4751 prefix = 0;
4752 if (i.prefix[DATA_PREFIX] != 0)
252b5132 4753 {
29b0f896
AM		 4754 prefix = 1;
4755 i.prefixes -= 1;
4756 code16 ^= CODE16;
252b5132 4757 }
29b0f896
AM		 4758 /* Pentium4 branch hints. */
4759 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4760 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 4761 {
29b0f896
AM		 4762 prefix++;
4763 i.prefixes--;
4764 }
4765 if (i.prefix[REX_PREFIX] != 0)
4766 {
4767 prefix++;
4768 i.prefixes--;
2f66722d
AM		 4769 }
4770
29b0f896
AM		 4771 if (i.prefixes != 0 && !intel_syntax)
4772 as_warn (_("skipping prefixes on this instruction"));
4773
4774 /* It's always a symbol; End frag & setup for relax.
4775 Make sure there is enough room in this frag for the largest
4776 instruction we may generate in md_convert_frag. This is 2
4777 bytes for the opcode and room for the prefix and largest
4778 displacement. */
4779 frag_grow (prefix + 2 + 4);
4780 /* Prefix and 1 opcode byte go in fr_fix. */
4781 p = frag_more (prefix + 1);
4782 if (i.prefix[DATA_PREFIX] != 0)
4783 *p++ = DATA_PREFIX_OPCODE;
4784 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
4785 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
4786 *p++ = i.prefix[SEG_PREFIX];
4787 if (i.prefix[REX_PREFIX] != 0)
4788 *p++ = i.prefix[REX_PREFIX];
4789 *p = i.tm.base_opcode;
4790
4791 if ((unsigned char) *p == JUMP_PC_RELATIVE)
4792 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 4793 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 4794 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
4795 else
4796 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
4797 subtype |= code16;
3e73aa7c 4798
29b0f896
AM		 4799 sym = i.op[0].disps->X_add_symbol;
4800 off = i.op[0].disps->X_add_number;
3e73aa7c 4801
29b0f896
AM		 4802 if (i.op[0].disps->X_op != O_constant
4803 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 4804 {
29b0f896
AM		 4805 /* Handle complex expressions. */
4806 sym = make_expr_symbol (i.op[0].disps);
4807 off = 0;
4808 }
3e73aa7c 4809
29b0f896
AM		 4810 /* 1 possible extra opcode + 4 byte displacement go in var part.
4811 Pass reloc in fr_var. */
4812 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
4813}
3e73aa7c 4814
29b0f896 4815static void
e3bb37b5 4816output_jump (void)
29b0f896
AM		 4817{
4818 char *p;
4819 int size;
3e02c1cc 4820 fixS *fixP;
29b0f896 4821
40fb9820 4822 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 4823 {
4824 /* This is a loop or jecxz type instruction. */
4825 size = 1;
4826 if (i.prefix[ADDR_PREFIX] != 0)
4827 {
4828 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
4829 i.prefixes -= 1;
4830 }
4831 /* Pentium4 branch hints. */
4832 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4833 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
4834 {
4835 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
4836 i.prefixes--;
3e73aa7c
JH		 4837 }
4838 }
29b0f896
AM		 4839 else
4840 {
4841 int code16;
3e73aa7c 4842
29b0f896
AM		 4843 code16 = 0;
4844 if (flag_code == CODE_16BIT)
4845 code16 = CODE16;
3e73aa7c 4846
29b0f896
AM		 4847 if (i.prefix[DATA_PREFIX] != 0)
4848 {
4849 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
4850 i.prefixes -= 1;
4851 code16 ^= CODE16;
4852 }
252b5132 4853
29b0f896
AM		 4854 size = 4;
4855 if (code16)
4856 size = 2;
4857 }
9fcc94b6 4858
29b0f896
AM		 4859 if (i.prefix[REX_PREFIX] != 0)
4860 {
4861 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
4862 i.prefixes -= 1;
4863 }
252b5132 4864
29b0f896
AM		 4865 if (i.prefixes != 0 && !intel_syntax)
4866 as_warn (_("skipping prefixes on this instruction"));
e0890092 4867
29b0f896
AM		 4868 p = frag_more (1 + size);
4869 *p++ = i.tm.base_opcode;
e0890092 4870
3e02c1cc
AM		 4871 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4872 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
4873
4874 /* All jumps handled here are signed, but don't use a signed limit
4875 check for 32 and 16 bit jumps as we want to allow wrap around at
4876 4G and 64k respectively. */
4877 if (size == 1)
4878 fixP->fx_signed = 1;
29b0f896 4879}
e0890092 4880
29b0f896 4881static void
e3bb37b5 4882output_interseg_jump (void)
29b0f896
AM		 4883{
4884 char *p;
4885 int size;
4886 int prefix;
4887 int code16;
252b5132 4888
29b0f896
AM		 4889 code16 = 0;
4890 if (flag_code == CODE_16BIT)
4891 code16 = CODE16;
a217f122 4892
29b0f896
AM		 4893 prefix = 0;
4894 if (i.prefix[DATA_PREFIX] != 0)
4895 {
4896 prefix = 1;
4897 i.prefixes -= 1;
4898 code16 ^= CODE16;
4899 }
4900 if (i.prefix[REX_PREFIX] != 0)
4901 {
4902 prefix++;
4903 i.prefixes -= 1;
4904 }
252b5132 4905
29b0f896
AM		 4906 size = 4;
4907 if (code16)
4908 size = 2;
252b5132 4909
29b0f896
AM		 4910 if (i.prefixes != 0 && !intel_syntax)
4911 as_warn (_("skipping prefixes on this instruction"));
252b5132 4912
29b0f896
AM		 4913 /* 1 opcode; 2 segment; offset */
4914 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 4915
29b0f896
AM		 4916 if (i.prefix[DATA_PREFIX] != 0)
4917 *p++ = DATA_PREFIX_OPCODE;
252b5132 4918
29b0f896
AM		 4919 if (i.prefix[REX_PREFIX] != 0)
4920 *p++ = i.prefix[REX_PREFIX];
252b5132 4921
29b0f896
AM		 4922 *p++ = i.tm.base_opcode;
4923 if (i.op[1].imms->X_op == O_constant)
4924 {
4925 offsetT n = i.op[1].imms->X_add_number;
252b5132 4926
29b0f896
AM		 4927 if (size == 2
4928 && !fits_in_unsigned_word (n)
4929 && !fits_in_signed_word (n))
4930 {
4931 as_bad (_("16-bit jump out of range"));
4932 return;
4933 }
4934 md_number_to_chars (p, n, size);
4935 }
4936 else
4937 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4938 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
4939 if (i.op[0].imms->X_op != O_constant)
4940 as_bad (_("can't handle non absolute segment in `%s'"),
4941 i.tm.name);
4942 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
4943}
a217f122 4944
29b0f896 4945static void
e3bb37b5 4946output_insn (void)
29b0f896 4947{
2bbd9c25
JJ		 4948 fragS *insn_start_frag;
4949 offsetT insn_start_off;
4950
29b0f896
AM		 4951 /* Tie dwarf2 debug info to the address at the start of the insn.
4952 We can't do this after the insn has been output as the current
4953 frag may have been closed off. eg. by frag_var. */
4954 dwarf2_emit_insn (0);
4955
2bbd9c25
JJ		 4956 insn_start_frag = frag_now;
4957 insn_start_off = frag_now_fix ();
4958
29b0f896 4959 /* Output jumps. */
40fb9820 4960 if (i.tm.opcode_modifier.jump)
29b0f896 4961 output_branch ();
40fb9820
L		 4962 else if (i.tm.opcode_modifier.jumpbyte
4963 || i.tm.opcode_modifier.jumpdword)
29b0f896 4964 output_jump ();
40fb9820 4965 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 4966 output_interseg_jump ();
4967 else
4968 {
4969 /* Output normal instructions here. */
4970 char *p;
4971 unsigned char *q;
331d2d0d 4972 unsigned int prefix;
40fb9820 4973 int opc_3b;
252b5132 4974
42903f7f 4975 /* All opcodes on i386 have either 1 or 2 bytes. SSSE3 and
85f10a01
MM		 4976 SSE4 and SSE5 instructions have 3 bytes. We may use one
4977 more higher byte to specify a prefix the instruction
4978 requires. Exclude instructions which are in both SSE4.2
4979 and ABM. */
cf557b51 4980 opc_3b = (i.tm.cpu_flags.bitfield.cpussse3
85f10a01 4981 || i.tm.cpu_flags.bitfield.cpusse5
cf557b51
L		 4982 || i.tm.cpu_flags.bitfield.cpusse4_1
4983 || (i.tm.cpu_flags.bitfield.cpusse4_2
4984 && !i.tm.cpu_flags.bitfield.cpuabm));
40fb9820 4985 if (opc_3b)
bc4bd9ab 4986 {
331d2d0d
L		 4987 if (i.tm.base_opcode & 0xff000000)
4988 {
4989 prefix = (i.tm.base_opcode >> 24) & 0xff;
4990 goto check_prefix;
4991 }
4992 }
4993 else if ((i.tm.base_opcode & 0xff0000) != 0)
4994 {
4995 prefix = (i.tm.base_opcode >> 16) & 0xff;
40fb9820 4996 if (i.tm.cpu_flags.bitfield.cpupadlock)
bc4bd9ab 4997 {
64e74474 4998 check_prefix:
bc4bd9ab
MK		 4999 if (prefix != REPE_PREFIX_OPCODE
5000 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
5001 add_prefix (prefix);
5002 }
5003 else
331d2d0d 5004 add_prefix (prefix);
0f10071e 5005 }
252b5132 5006
29b0f896
AM		 5007 /* The prefix bytes. */
5008 for (q = i.prefix;
5009 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
5010 q++)
5011 {
5012 if (*q)
5013 {
5014 p = frag_more (1);
5015 md_number_to_chars (p, (valueT) *q, 1);
5016 }
5017 }
252b5132 5018
29b0f896
AM		 5019 /* Now the opcode; be careful about word order here! */
5020 if (fits_in_unsigned_byte (i.tm.base_opcode))
5021 {
5022 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5023 }
5024 else
5025 {
40fb9820 5026 if (opc_3b)
331d2d0d
L		 5027 {
5028 p = frag_more (3);
5029 *p++ = (i.tm.base_opcode >> 16) & 0xff;
5030 }
5031 else
5032 p = frag_more (2);
0f10071e 5033
29b0f896
AM		 5034 /* Put out high byte first: can't use md_number_to_chars! */
5035 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5036 *p = i.tm.base_opcode & 0xff;
85f10a01
MM		 5037
5038 /* On SSE5, encode the OC1 bit in the DREX field if this
5039 encoding has multiple formats. */
5040 if (i.tm.opcode_modifier.drex
5041 && i.tm.opcode_modifier.drexv
5042 && DREX_OC1 (i.tm.extension_opcode))
5043 *p |= DREX_OC1_MASK;
29b0f896 5044 }
3e73aa7c 5045
29b0f896 5046 /* Now the modrm byte and sib byte (if present). */
40fb9820 5047 if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5048 {
5049 p = frag_more (1);
5050 md_number_to_chars (p,
5051 (valueT) (i.rm.regmem << 0
5052 | i.rm.reg << 3
5053 | i.rm.mode << 6),
5054 1);
5055 /* If i.rm.regmem == ESP (4)
5056 && i.rm.mode != (Register mode)
5057 && not 16 bit
5058 ==> need second modrm byte. */
5059 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5060 && i.rm.mode != 3
40fb9820 5061 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
29b0f896
AM		 5062 {
5063 p = frag_more (1);
5064 md_number_to_chars (p,
5065 (valueT) (i.sib.base << 0
5066 | i.sib.index << 3
5067 | i.sib.scale << 6),
5068 1);
5069 }
5070 }
3e73aa7c 5071
85f10a01
MM		 5072 /* Write the DREX byte if needed. */
5073 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5074 {
5075 p = frag_more (1);
5076 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5077
5078 /* Encode the OC0 bit if this encoding has multiple
5079 formats. */
5080 if ((i.tm.opcode_modifier.drex
5081 || i.tm.opcode_modifier.drexv)
5082 && DREX_OC0 (i.tm.extension_opcode))
5083 *p |= DREX_OC0_MASK;
5084 }
5085
29b0f896 5086 if (i.disp_operands)
2bbd9c25 5087 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5088
29b0f896 5089 if (i.imm_operands)
2bbd9c25 5090 output_imm (insn_start_frag, insn_start_off);
29b0f896 5091 }
252b5132 5092
29b0f896
AM		 5093#ifdef DEBUG386
5094 if (flag_debug)
5095 {
7b81dfbb 5096 pi ("" /*line*/, &i);
29b0f896
AM		 5097 }
5098#endif /* DEBUG386 */
5099}
252b5132 5100
e205caa7
L		 5101/* Return the size of the displacement operand N. */
5102
5103static int
5104disp_size (unsigned int n)
5105{
5106 int size = 4;
40fb9820
L		 5107 if (i.types[n].bitfield.disp64)
5108 size = 8;
5109 else if (i.types[n].bitfield.disp8)
5110 size = 1;
5111 else if (i.types[n].bitfield.disp16)
5112 size = 2;
e205caa7
L		 5113 return size;
5114}
5115
5116/* Return the size of the immediate operand N. */
5117
5118static int
5119imm_size (unsigned int n)
5120{
5121 int size = 4;
40fb9820
L		 5122 if (i.types[n].bitfield.imm64)
5123 size = 8;
5124 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5125 size = 1;
5126 else if (i.types[n].bitfield.imm16)
5127 size = 2;
e205caa7
L		 5128 return size;
5129}
5130
29b0f896 5131static void
64e74474 5132output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5133{
5134 char *p;
5135 unsigned int n;
252b5132 5136
29b0f896
AM		 5137 for (n = 0; n < i.operands; n++)
5138 {
40fb9820 5139 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 5140 {
5141 if (i.op[n].disps->X_op == O_constant)
5142 {
e205caa7 5143 int size = disp_size (n);
29b0f896 5144 offsetT val;
252b5132 5145
29b0f896
AM		 5146 val = offset_in_range (i.op[n].disps->X_add_number,
5147 size);
5148 p = frag_more (size);
5149 md_number_to_chars (p, val, size);
5150 }
5151 else
5152 {
f86103b7 5153 enum bfd_reloc_code_real reloc_type;
e205caa7 5154 int size = disp_size (n);
40fb9820 5155 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 5156 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5157
e205caa7 5158 /* We can't have 8 bit displacement here. */
40fb9820 5159 assert (!i.types[n].bitfield.disp8);
e205caa7 5160
29b0f896
AM		 5161 /* The PC relative address is computed relative
5162 to the instruction boundary, so in case immediate
5163 fields follows, we need to adjust the value. */
5164 if (pcrel && i.imm_operands)
5165 {
29b0f896 5166 unsigned int n1;
e205caa7 5167 int sz = 0;
252b5132 5168
29b0f896 5169 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 5170 if (operand_type_check (i.types[n1], imm))
252b5132 5171 {
e205caa7
L		 5172 /* Only one immediate is allowed for PC
5173 relative address. */
5174 assert (sz == 0);
5175 sz = imm_size (n1);
5176 i.op[n].disps->X_add_number -= sz;
252b5132 5177 }
29b0f896 5178 /* We should find the immediate. */
e205caa7 5179 assert (sz != 0);
29b0f896 5180 }
520dc8e8 5181
29b0f896 5182 p = frag_more (size);
2bbd9c25 5183 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 5184 if (GOT_symbol
2bbd9c25 5185 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 5186 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5187 || reloc_type == BFD_RELOC_X86_64_32S
5188 || (reloc_type == BFD_RELOC_64
5189 && object_64bit))
d6ab8113
JB		 5190 && (i.op[n].disps->X_op == O_symbol
5191 || (i.op[n].disps->X_op == O_add
5192 && ((symbol_get_value_expression
5193 (i.op[n].disps->X_op_symbol)->X_op)
5194 == O_subtract))))
5195 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 5196 {
5197 offsetT add;
5198
5199 if (insn_start_frag == frag_now)
5200 add = (p - frag_now->fr_literal) - insn_start_off;
5201 else
5202 {
5203 fragS *fr;
5204
5205 add = insn_start_frag->fr_fix - insn_start_off;
5206 for (fr = insn_start_frag->fr_next;
5207 fr && fr != frag_now; fr = fr->fr_next)
5208 add += fr->fr_fix;
5209 add += p - frag_now->fr_literal;
5210 }
5211
4fa24527 5212 if (!object_64bit)
7b81dfbb
AJ		 5213 {
5214 reloc_type = BFD_RELOC_386_GOTPC;
5215 i.op[n].imms->X_add_number += add;
5216 }
5217 else if (reloc_type == BFD_RELOC_64)
5218 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 5219 else
7b81dfbb
AJ		 5220 /* Don't do the adjustment for x86-64, as there
5221 the pcrel addressing is relative to the _next_
5222 insn, and that is taken care of in other code. */
d6ab8113 5223 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 5224 }
062cd5e7 5225 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 5226 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 5227 }
5228 }
5229 }
5230}
252b5132 5231
29b0f896 5232static void
64e74474 5233output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5234{
5235 char *p;
5236 unsigned int n;
252b5132 5237
29b0f896
AM		 5238 for (n = 0; n < i.operands; n++)
5239 {
40fb9820 5240 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 5241 {
5242 if (i.op[n].imms->X_op == O_constant)
5243 {
e205caa7 5244 int size = imm_size (n);
29b0f896 5245 offsetT val;
b4cac588 5246
29b0f896
AM		 5247 val = offset_in_range (i.op[n].imms->X_add_number,
5248 size);
5249 p = frag_more (size);
5250 md_number_to_chars (p, val, size);
5251 }
5252 else
5253 {
5254 /* Not absolute_section.
5255 Need a 32-bit fixup (don't support 8bit
5256 non-absolute imms). Try to support other
5257 sizes ... */
f86103b7 5258 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 5259 int size = imm_size (n);
5260 int sign;
29b0f896 5261
40fb9820 5262 if (i.types[n].bitfield.imm32s
a7d61044 5263 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 5264 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 5265 sign = 1;
e205caa7
L		 5266 else
5267 sign = 0;
520dc8e8 5268
29b0f896
AM		 5269 p = frag_more (size);
5270 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 5271
2bbd9c25
JJ		 5272 /* This is tough to explain. We end up with this one if we
5273 * have operands that look like
5274 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5275 * obtain the absolute address of the GOT, and it is strongly
5276 * preferable from a performance point of view to avoid using
5277 * a runtime relocation for this. The actual sequence of
5278 * instructions often look something like:
5279 *
5280 * call .L66
5281 * .L66:
5282 * popl %ebx
5283 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5284 *
5285 * The call and pop essentially return the absolute address
5286 * of the label .L66 and store it in %ebx. The linker itself
5287 * will ultimately change the first operand of the addl so
5288 * that %ebx points to the GOT, but to keep things simple, the
5289 * .o file must have this operand set so that it generates not
5290 * the absolute address of .L66, but the absolute address of
5291 * itself. This allows the linker itself simply treat a GOTPC
5292 * relocation as asking for a pcrel offset to the GOT to be
5293 * added in, and the addend of the relocation is stored in the
5294 * operand field for the instruction itself.
5295 *
5296 * Our job here is to fix the operand so that it would add
5297 * the correct offset so that %ebx would point to itself. The
5298 * thing that is tricky is that .-.L66 will point to the
5299 * beginning of the instruction, so we need to further modify
5300 * the operand so that it will point to itself. There are
5301 * other cases where you have something like:
5302 *
5303 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5304 *
5305 * and here no correction would be required. Internally in
5306 * the assembler we treat operands of this form as not being
5307 * pcrel since the '.' is explicitly mentioned, and I wonder
5308 * whether it would simplify matters to do it this way. Who
5309 * knows. In earlier versions of the PIC patches, the
5310 * pcrel_adjust field was used to store the correction, but
5311 * since the expression is not pcrel, I felt it would be
5312 * confusing to do it this way. */
5313
d6ab8113 5314 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5315 || reloc_type == BFD_RELOC_X86_64_32S
5316 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 5317 && GOT_symbol
5318 && GOT_symbol == i.op[n].imms->X_add_symbol
5319 && (i.op[n].imms->X_op == O_symbol
5320 || (i.op[n].imms->X_op == O_add
5321 && ((symbol_get_value_expression
5322 (i.op[n].imms->X_op_symbol)->X_op)
5323 == O_subtract))))
5324 {
2bbd9c25
JJ		 5325 offsetT add;
5326
5327 if (insn_start_frag == frag_now)
5328 add = (p - frag_now->fr_literal) - insn_start_off;
5329 else
5330 {
5331 fragS *fr;
5332
5333 add = insn_start_frag->fr_fix - insn_start_off;
5334 for (fr = insn_start_frag->fr_next;
5335 fr && fr != frag_now; fr = fr->fr_next)
5336 add += fr->fr_fix;
5337 add += p - frag_now->fr_literal;
5338 }
5339
4fa24527 5340 if (!object_64bit)
d6ab8113 5341 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 5342 else if (size == 4)
d6ab8113 5343 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 5344 else if (size == 8)
5345 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 5346 i.op[n].imms->X_add_number += add;
29b0f896 5347 }
29b0f896
AM		 5348 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5349 i.op[n].imms, 0, reloc_type);
5350 }
5351 }
5352 }
252b5132
RH		 5353}
5354\f
d182319b
JB		 5355/* x86_cons_fix_new is called via the expression parsing code when a
5356 reloc is needed. We use this hook to get the correct .got reloc. */
5357static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5358static int cons_sign = -1;
5359
5360void
e3bb37b5 5361x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 5362 expressionS *exp)
d182319b
JB		 5363{
5364 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5365
5366 got_reloc = NO_RELOC;
5367
5368#ifdef TE_PE
5369 if (exp->X_op == O_secrel)
5370 {
5371 exp->X_op = O_symbol;
5372 r = BFD_RELOC_32_SECREL;
5373 }
5374#endif
5375
5376 fix_new_exp (frag, off, len, exp, 0, r);
5377}
5378
718ddfc0
JB		 5379#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5380# define lex_got(reloc, adjust, types) NULL
5381#else
f3c180ae
AM		 5382/* Parse operands of the form
5383 <symbol>@GOTOFF+<nnn>
5384 and similar .plt or .got references.
5385
5386 If we find one, set up the correct relocation in RELOC and copy the
5387 input string, minus the `@GOTOFF' into a malloc'd buffer for
5388 parsing by the calling routine. Return this buffer, and if ADJUST
5389 is non-null set it to the length of the string we removed from the
5390 input line. Otherwise return NULL. */
5391static char *
3956db08 5392lex_got (enum bfd_reloc_code_real *reloc,
64e74474 5393 int *adjust,
40fb9820 5394 i386_operand_type *types)
f3c180ae 5395{
7b81dfbb
AJ		 5396 /* Some of the relocations depend on the size of what field is to
5397 be relocated. But in our callers i386_immediate and i386_displacement
5398 we don't yet know the operand size (this will be set by insn
5399 matching). Hence we record the word32 relocation here,
5400 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 5401 static const struct {
5402 const char *str;
4fa24527 5403 const enum bfd_reloc_code_real rel[2];
40fb9820 5404 const i386_operand_type types64;
f3c180ae 5405 } gotrel[] = {
4eed87de
AM		 5406 { "PLTOFF", { 0,
5407 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 5408 OPERAND_TYPE_IMM64 },
4eed87de
AM		 5409 { "PLT", { BFD_RELOC_386_PLT32,
5410 BFD_RELOC_X86_64_PLT32 },
40fb9820 5411 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5412 { "GOTPLT", { 0,
5413 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 5414 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5415 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5416 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 5417 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5418 { "GOTPCREL", { 0,
5419 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 5420 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5421 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5422 BFD_RELOC_X86_64_TLSGD },
40fb9820 5423 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5424 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5425 0 },
40fb9820 5426 OPERAND_TYPE_NONE },
4eed87de
AM		 5427 { "TLSLD", { 0,
5428 BFD_RELOC_X86_64_TLSLD },
40fb9820 5429 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5430 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5431 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 5432 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5433 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5434 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 5435 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5436 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5437 0 },
40fb9820 5438 OPERAND_TYPE_NONE },
4eed87de
AM		 5439 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5440 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820
L		 5441
5442 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5443 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5444 0 },
40fb9820 5445 OPERAND_TYPE_NONE },
4eed87de
AM		 5446 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5447 0 },
40fb9820 5448 OPERAND_TYPE_NONE },
4eed87de
AM		 5449 { "GOT", { BFD_RELOC_386_GOT32,
5450 BFD_RELOC_X86_64_GOT32 },
40fb9820 5451 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 5452 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5453 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 5454 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5455 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5456 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 5457 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 5458 };
5459 char *cp;
5460 unsigned int j;
5461
718ddfc0
JB		 5462 if (!IS_ELF)
5463 return NULL;
5464
f3c180ae 5465 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 5466 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 5467 return NULL;
5468
5469 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
5470 {
5471 int len;
5472
5473 len = strlen (gotrel[j].str);
28f81592 5474 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 5475 {
4fa24527 5476 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 5477 {
28f81592
AM		 5478 int first, second;
5479 char *tmpbuf, *past_reloc;
f3c180ae 5480
4fa24527 5481 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 5482 if (adjust)
5483 *adjust = len;
f3c180ae 5484
3956db08
JB		 5485 if (types)
5486 {
5487 if (flag_code != CODE_64BIT)
40fb9820
L		 5488 {
5489 types->bitfield.imm32 = 1;
5490 types->bitfield.disp32 = 1;
5491 }
3956db08
JB		 5492 else
5493 *types = gotrel[j].types64;
5494 }
5495
f3c180ae
AM		 5496 if (GOT_symbol == NULL)
5497 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5498
28f81592 5499 /* The length of the first part of our input line. */
f3c180ae 5500 first = cp - input_line_pointer;
28f81592
AM		 5501
5502 /* The second part goes from after the reloc token until
67c11a9b 5503 (and including) an end_of_line char or comma. */
28f81592 5504 past_reloc = cp + 1 + len;
67c11a9b
AM		 5505 cp = past_reloc;
5506 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5507 ++cp;
5508 second = cp + 1 - past_reloc;
28f81592
AM		 5509
5510 /* Allocate and copy string. The trailing NUL shouldn't
5511 be necessary, but be safe. */
5512 tmpbuf = xmalloc (first + second + 2);
f3c180ae 5513 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 5514 if (second != 0 && *past_reloc != ' ')
5515 /* Replace the relocation token with ' ', so that
5516 errors like foo@GOTOFF1 will be detected. */
5517 tmpbuf[first++] = ' ';
5518 memcpy (tmpbuf + first, past_reloc, second);
5519 tmpbuf[first + second] = '\0';
f3c180ae
AM		 5520 return tmpbuf;
5521 }
5522
4fa24527
JB		 5523 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5524 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 5525 return NULL;
5526 }
5527 }
5528
5529 /* Might be a symbol version string. Don't as_bad here. */
5530 return NULL;
5531}
5532
f3c180ae 5533void
e3bb37b5 5534x86_cons (expressionS *exp, int size)
f3c180ae 5535{
4fa24527 5536 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 5537 {
5538 /* Handle @GOTOFF and the like in an expression. */
5539 char *save;
5540 char *gotfree_input_line;
5541 int adjust;
5542
5543 save = input_line_pointer;
3956db08 5544 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 5545 if (gotfree_input_line)
5546 input_line_pointer = gotfree_input_line;
5547
5548 expression (exp);
5549
5550 if (gotfree_input_line)
5551 {
5552 /* expression () has merrily parsed up to the end of line,
5553 or a comma - in the wrong buffer. Transfer how far
5554 input_line_pointer has moved to the right buffer. */
5555 input_line_pointer = (save
5556 + (input_line_pointer - gotfree_input_line)
5557 + adjust);
5558 free (gotfree_input_line);
3992d3b7
AM		 5559 if (exp->X_op == O_constant
5560 || exp->X_op == O_absent
5561 || exp->X_op == O_illegal
5562 || exp->X_op == O_register
5563 || exp->X_op == O_big)
5564 {
5565 char c = *input_line_pointer;
5566 *input_line_pointer = 0;
5567 as_bad (_("missing or invalid expression `%s'"), save);
5568 *input_line_pointer = c;
5569 }
f3c180ae
AM		 5570 }
5571 }
5572 else
5573 expression (exp);
5574}
5575#endif
5576
d182319b 5577static void signed_cons (int size)
6482c264 5578{
d182319b
JB		 5579 if (flag_code == CODE_64BIT)
5580 cons_sign = 1;
5581 cons (size);
5582 cons_sign = -1;
6482c264
NC		 5583}
5584
d182319b 5585#ifdef TE_PE
6482c264
NC		 5586static void
5587pe_directive_secrel (dummy)
5588 int dummy ATTRIBUTE_UNUSED;
5589{
5590 expressionS exp;
5591
5592 do
5593 {
5594 expression (&exp);
5595 if (exp.X_op == O_symbol)
5596 exp.X_op = O_secrel;
5597
5598 emit_expr (&exp, 4);
5599 }
5600 while (*input_line_pointer++ == ',');
5601
5602 input_line_pointer--;
5603 demand_empty_rest_of_line ();
5604}
6482c264
NC		 5605#endif
5606
252b5132 5607static int
70e41ade 5608i386_immediate (char *imm_start)
252b5132
RH		 5609{
5610 char *save_input_line_pointer;
f3c180ae 5611 char *gotfree_input_line;
252b5132 5612 segT exp_seg = 0;
47926f60 5613 expressionS *exp;
40fb9820
L		 5614 i386_operand_type types;
5615
c6fb90c8 5616 UINTS_SET (types, ~0);
252b5132
RH		 5617
5618 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5619 {
31b2323c
L		 5620 as_bad (_("at most %d immediate operands are allowed"),
5621 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 5622 return 0;
5623 }
5624
5625 exp = &im_expressions[i.imm_operands++];
520dc8e8 5626 i.op[this_operand].imms = exp;
252b5132
RH		 5627
5628 if (is_space_char (*imm_start))
5629 ++imm_start;
5630
5631 save_input_line_pointer = input_line_pointer;
5632 input_line_pointer = imm_start;
5633
3956db08 5634 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5635 if (gotfree_input_line)
5636 input_line_pointer = gotfree_input_line;
252b5132
RH		 5637
5638 exp_seg = expression (exp);
5639
83183c0c 5640 SKIP_WHITESPACE ();
252b5132 5641 if (*input_line_pointer)
f3c180ae 5642 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 5643
5644 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 5645 if (gotfree_input_line)
5646 free (gotfree_input_line);
252b5132 5647
3992d3b7
AM		 5648 if (exp->X_op == O_absent
5649 || exp->X_op == O_illegal
5650 || exp->X_op == O_big
5651 || (gotfree_input_line
5652 && (exp->X_op == O_constant
5653 || exp->X_op == O_register)))
252b5132 5654 {
3992d3b7 5655 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 5656 imm_start);
3992d3b7 5657 return 0;
252b5132 5658 }
3e73aa7c 5659 else if (exp->X_op == O_constant)
252b5132 5660 {
47926f60 5661 /* Size it properly later. */
40fb9820 5662 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 5663 /* If BFD64, sign extend val. */
4eed87de
AM		 5664 if (!use_rela_relocations
5665 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5666 exp->X_add_number
5667 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 5668 }
4c63da97 5669#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 5670 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 5671 && exp_seg != absolute_section
47926f60 5672 && exp_seg != text_section
24eab124
AM		 5673 && exp_seg != data_section
5674 && exp_seg != bss_section
5675 && exp_seg != undefined_section
f86103b7 5676 && !bfd_is_com_section (exp_seg))
252b5132 5677 {
d0b47220 5678 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 5679 return 0;
5680 }
5681#endif
bb8f5920
L		 5682 else if (!intel_syntax && exp->X_op == O_register)
5683 {
5684 as_bad (_("illegal immediate register operand %s"), imm_start);
5685 return 0;
5686 }
252b5132
RH		 5687 else
5688 {
5689 /* This is an address. The size of the address will be
24eab124 5690 determined later, depending on destination register,
3e73aa7c 5691 suffix, or the default for the section. */
40fb9820
L		 5692 i.types[this_operand].bitfield.imm8 = 1;
5693 i.types[this_operand].bitfield.imm16 = 1;
5694 i.types[this_operand].bitfield.imm32 = 1;
5695 i.types[this_operand].bitfield.imm32s = 1;
5696 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 5697 i.types[this_operand] = operand_type_and (i.types[this_operand],
5698 types);
252b5132
RH		 5699 }
5700
5701 return 1;
5702}
5703
551c1ca1 5704static char *
e3bb37b5 5705i386_scale (char *scale)
252b5132 5706{
551c1ca1
AM		 5707 offsetT val;
5708 char *save = input_line_pointer;
252b5132 5709
551c1ca1
AM		 5710 input_line_pointer = scale;
5711 val = get_absolute_expression ();
5712
5713 switch (val)
252b5132 5714 {
551c1ca1 5715 case 1:
252b5132
RH		 5716 i.log2_scale_factor = 0;
5717 break;
551c1ca1 5718 case 2:
252b5132
RH		 5719 i.log2_scale_factor = 1;
5720 break;
551c1ca1 5721 case 4:
252b5132
RH		 5722 i.log2_scale_factor = 2;
5723 break;
551c1ca1 5724 case 8:
252b5132
RH		 5725 i.log2_scale_factor = 3;
5726 break;
5727 default:
a724f0f4
JB		 5728 {
5729 char sep = *input_line_pointer;
5730
5731 *input_line_pointer = '\0';
5732 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5733 scale);
5734 *input_line_pointer = sep;
5735 input_line_pointer = save;
5736 return NULL;
5737 }
252b5132 5738 }
29b0f896 5739 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 5740 {
5741 as_warn (_("scale factor of %d without an index register"),
24eab124 5742 1 << i.log2_scale_factor);
252b5132
RH		 5743#if SCALE1_WHEN_NO_INDEX
5744 i.log2_scale_factor = 0;
5745#endif
5746 }
551c1ca1
AM		 5747 scale = input_line_pointer;
5748 input_line_pointer = save;
5749 return scale;
252b5132
RH		 5750}
5751
252b5132 5752static int
e3bb37b5 5753i386_displacement (char *disp_start, char *disp_end)
252b5132 5754{
29b0f896 5755 expressionS *exp;
252b5132
RH		 5756 segT exp_seg = 0;
5757 char *save_input_line_pointer;
f3c180ae 5758 char *gotfree_input_line;
40fb9820
L		 5759 int override;
5760 i386_operand_type bigdisp, types = anydisp;
3992d3b7 5761 int ret;
252b5132 5762
31b2323c
L		 5763 if (i.disp_operands == MAX_MEMORY_OPERANDS)
5764 {
5765 as_bad (_("at most %d displacement operands are allowed"),
5766 MAX_MEMORY_OPERANDS);
5767 return 0;
5768 }
5769
c6fb90c8 5770 UINTS_CLEAR (bigdisp);
40fb9820
L		 5771 if ((i.types[this_operand].bitfield.jumpabsolute)
5772 || (!current_templates->start->opcode_modifier.jump
5773 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 5774 {
40fb9820 5775 bigdisp.bitfield.disp32 = 1;
e05278af 5776 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 5777 if (flag_code == CODE_64BIT)
5778 {
5779 if (!override)
5780 {
5781 bigdisp.bitfield.disp32s = 1;
5782 bigdisp.bitfield.disp64 = 1;
5783 }
5784 }
5785 else if ((flag_code == CODE_16BIT) ^ override)
5786 {
5787 bigdisp.bitfield.disp32 = 0;
5788 bigdisp.bitfield.disp16 = 1;
5789 }
e05278af
JB		 5790 }
5791 else
5792 {
5793 /* For PC-relative branches, the width of the displacement
5794 is dependent upon data size, not address size. */
e05278af 5795 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 5796 if (flag_code == CODE_64BIT)
5797 {
5798 if (override || i.suffix == WORD_MNEM_SUFFIX)
5799 bigdisp.bitfield.disp16 = 1;
5800 else
5801 {
5802 bigdisp.bitfield.disp32 = 1;
5803 bigdisp.bitfield.disp32s = 1;
5804 }
5805 }
5806 else
e05278af
JB		 5807 {
5808 if (!override)
5809 override = (i.suffix == (flag_code != CODE_16BIT
5810 ? WORD_MNEM_SUFFIX
5811 : LONG_MNEM_SUFFIX));
40fb9820
L		 5812 bigdisp.bitfield.disp32 = 1;
5813 if ((flag_code == CODE_16BIT) ^ override)
5814 {
5815 bigdisp.bitfield.disp32 = 0;
5816 bigdisp.bitfield.disp16 = 1;
5817 }
e05278af 5818 }
e05278af 5819 }
c6fb90c8
L		 5820 i.types[this_operand] = operand_type_or (i.types[this_operand],
5821 bigdisp);
252b5132
RH		 5822
5823 exp = &disp_expressions[i.disp_operands];
520dc8e8 5824 i.op[this_operand].disps = exp;
252b5132
RH		 5825 i.disp_operands++;
5826 save_input_line_pointer = input_line_pointer;
5827 input_line_pointer = disp_start;
5828 END_STRING_AND_SAVE (disp_end);
5829
5830#ifndef GCC_ASM_O_HACK
5831#define GCC_ASM_O_HACK 0
5832#endif
5833#if GCC_ASM_O_HACK
5834 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 5835 if (i.types[this_operand].bitfield.baseIndex
24eab124 5836 && displacement_string_end[-1] == '+')
252b5132
RH		 5837 {
5838 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 5839 constraint within gcc asm statements.
5840 For instance:
5841
5842 #define _set_tssldt_desc(n,addr,limit,type) \
5843 __asm__ __volatile__ ( \
5844 "movw %w2,%0\n\t" \
5845 "movw %w1,2+%0\n\t" \
5846 "rorl $16,%1\n\t" \
5847 "movb %b1,4+%0\n\t" \
5848 "movb %4,5+%0\n\t" \
5849 "movb $0,6+%0\n\t" \
5850 "movb %h1,7+%0\n\t" \
5851 "rorl $16,%1" \
5852 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
5853
5854 This works great except that the output assembler ends
5855 up looking a bit weird if it turns out that there is
5856 no offset. You end up producing code that looks like:
5857
5858 #APP
5859 movw $235,(%eax)
5860 movw %dx,2+(%eax)
5861 rorl $16,%edx
5862 movb %dl,4+(%eax)
5863 movb $137,5+(%eax)
5864 movb $0,6+(%eax)
5865 movb %dh,7+(%eax)
5866 rorl $16,%edx
5867 #NO_APP
5868
47926f60 5869 So here we provide the missing zero. */
24eab124
AM		 5870
5871 *displacement_string_end = '0';
252b5132
RH		 5872 }
5873#endif
3956db08 5874 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5875 if (gotfree_input_line)
5876 input_line_pointer = gotfree_input_line;
252b5132 5877
24eab124 5878 exp_seg = expression (exp);
252b5132 5879
636c26b0
AM		 5880 SKIP_WHITESPACE ();
5881 if (*input_line_pointer)
5882 as_bad (_("junk `%s' after expression"), input_line_pointer);
5883#if GCC_ASM_O_HACK
5884 RESTORE_END_STRING (disp_end + 1);
5885#endif
636c26b0 5886 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 5887 if (gotfree_input_line)
5888 free (gotfree_input_line);
3992d3b7 5889 ret = 1;
636c26b0 5890
24eab124
AM		 5891 /* We do this to make sure that the section symbol is in
5892 the symbol table. We will ultimately change the relocation
47926f60 5893 to be relative to the beginning of the section. */
1ae12ab7 5894 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 5895 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
5896 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 5897 {
636c26b0 5898 if (exp->X_op != O_symbol)
3992d3b7 5899 goto inv_disp;
636c26b0 5900
e5cb08ac 5901 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 5902 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
5903 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 5904 exp->X_op = O_subtract;
5905 exp->X_op_symbol = GOT_symbol;
1ae12ab7 5906 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 5907 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 5908 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
5909 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 5910 else
29b0f896 5911 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 5912 }
252b5132 5913
3992d3b7
AM		 5914 else if (exp->X_op == O_absent
5915 || exp->X_op == O_illegal
5916 || exp->X_op == O_big
5917 || (gotfree_input_line
5918 && (exp->X_op == O_constant
5919 || exp->X_op == O_register)))
2daf4fd8 5920 {
3992d3b7
AM		 5921 inv_disp:
5922 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 5923 disp_start);
3992d3b7 5924 ret = 0;
2daf4fd8
AM		 5925 }
5926
4c63da97 5927#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 5928 else if (exp->X_op != O_constant
5929 && OUTPUT_FLAVOR == bfd_target_aout_flavour
5930 && exp_seg != absolute_section
5931 && exp_seg != text_section
5932 && exp_seg != data_section
5933 && exp_seg != bss_section
5934 && exp_seg != undefined_section
5935 && !bfd_is_com_section (exp_seg))
24eab124 5936 {
d0b47220 5937 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 5938 ret = 0;
24eab124 5939 }
252b5132 5940#endif
3956db08 5941
3992d3b7
AM		 5942 RESTORE_END_STRING (disp_end);
5943
40fb9820
L		 5944 /* Check if this is a displacement only operand. */
5945 bigdisp = i.types[this_operand];
5946 bigdisp.bitfield.disp8 = 0;
5947 bigdisp.bitfield.disp16 = 0;
5948 bigdisp.bitfield.disp32 = 0;
5949 bigdisp.bitfield.disp32s = 0;
5950 bigdisp.bitfield.disp64 = 0;
c6fb90c8
L		 5951 if (UINTS_ALL_ZERO (bigdisp))
5952 i.types[this_operand] = operand_type_and (i.types[this_operand],
5953 types);
3956db08 5954
3992d3b7 5955 return ret;
252b5132
RH		 5956}
5957
eecb386c 5958/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 5959 Return 1 on success, 0 on a failure. */
5960
252b5132 5961static int
e3bb37b5 5962i386_index_check (const char *operand_string)
252b5132 5963{
3e73aa7c 5964 int ok;
24eab124 5965#if INFER_ADDR_PREFIX
eecb386c
AM		 5966 int fudged = 0;
5967
24eab124
AM		 5968 tryprefix:
5969#endif
3e73aa7c 5970 ok = 1;
75178d9d 5971 if (flag_code == CODE_64BIT)
64e74474 5972 {
64e74474 5973 if ((i.base_reg
40fb9820
L		 5974 && ((i.prefix[ADDR_PREFIX] == 0
5975 && !i.base_reg->reg_type.bitfield.reg64)
5976 || (i.prefix[ADDR_PREFIX]
5977 && !i.base_reg->reg_type.bitfield.reg32))
5978 && (i.index_reg
20e192ab 5979 || i.base_reg->reg_num != RegRip))
64e74474 5980 || (i.index_reg
40fb9820
L		 5981 && (!i.index_reg->reg_type.bitfield.baseindex
5982 || (i.prefix[ADDR_PREFIX] == 0
5983 && !i.index_reg->reg_type.bitfield.reg64)
5984 || (i.prefix[ADDR_PREFIX]
5985 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 5986 ok = 0;
3e73aa7c
JH		 5987 }
5988 else
5989 {
5990 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
5991 {
5992 /* 16bit checks. */
5993 if ((i.base_reg
40fb9820
L		 5994 && (!i.base_reg->reg_type.bitfield.reg16
5995 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 5996 || (i.index_reg
40fb9820
L		 5997 && (!i.index_reg->reg_type.bitfield.reg16
5998 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 5999 || !(i.base_reg
6000 && i.base_reg->reg_num < 6
6001 && i.index_reg->reg_num >= 6
6002 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6003 ok = 0;
6004 }
6005 else
e5cb08ac 6006 {
3e73aa7c
JH		 6007 /* 32bit checks. */
6008 if ((i.base_reg
40fb9820 6009 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6010 || (i.index_reg
40fb9820
L		 6011 && (!i.index_reg->reg_type.bitfield.reg32
6012 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6013 ok = 0;
3e73aa7c
JH		 6014 }
6015 }
6016 if (!ok)
24eab124
AM		 6017 {
6018#if INFER_ADDR_PREFIX
20f0a1fc 6019 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 6020 {
6021 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6022 i.prefixes += 1;
b23bac36
AM		 6023 /* Change the size of any displacement too. At most one of
6024 Disp16 or Disp32 is set.
6025 FIXME. There doesn't seem to be any real need for separate
6026 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6027 Removing them would probably clean up the code quite a lot. */
4eed87de 6028 if (flag_code != CODE_64BIT
40fb9820
L		 6029 && (i.types[this_operand].bitfield.disp16
6030 || i.types[this_operand].bitfield.disp32))
6031 i.types[this_operand]
c6fb90c8 6032 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6033 fudged = 1;
24eab124
AM		 6034 goto tryprefix;
6035 }
eecb386c
AM		 6036 if (fudged)
6037 as_bad (_("`%s' is not a valid base/index expression"),
6038 operand_string);
6039 else
c388dee8 6040#endif
eecb386c
AM		 6041 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6042 operand_string,
3e73aa7c 6043 flag_code_names[flag_code]);
24eab124 6044 }
20f0a1fc 6045 return ok;
24eab124 6046}
252b5132 6047
252b5132 6048/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 6049 on error. */
252b5132 6050
252b5132 6051static int
e3bb37b5 6052i386_operand (char *operand_string)
252b5132 6053{
af6bdddf
AM		 6054 const reg_entry *r;
6055 char *end_op;
24eab124 6056 char *op_string = operand_string;
252b5132 6057
24eab124 6058 if (is_space_char (*op_string))
252b5132
RH		 6059 ++op_string;
6060
24eab124 6061 /* We check for an absolute prefix (differentiating,
47926f60 6062 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 6063 if (*op_string == ABSOLUTE_PREFIX)
6064 {
6065 ++op_string;
6066 if (is_space_char (*op_string))
6067 ++op_string;
40fb9820 6068 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 6069 }
252b5132 6070
47926f60 6071 /* Check if operand is a register. */
4d1bb795 6072 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 6073 {
40fb9820
L		 6074 i386_operand_type temp;
6075
24eab124
AM		 6076 /* Check for a segment override by searching for ':' after a
6077 segment register. */
6078 op_string = end_op;
6079 if (is_space_char (*op_string))
6080 ++op_string;
40fb9820
L		 6081 if (*op_string == ':'
6082 && (r->reg_type.bitfield.sreg2
6083 || r->reg_type.bitfield.sreg3))
24eab124
AM		 6084 {
6085 switch (r->reg_num)
6086 {
6087 case 0:
6088 i.seg[i.mem_operands] = &es;
6089 break;
6090 case 1:
6091 i.seg[i.mem_operands] = &cs;
6092 break;
6093 case 2:
6094 i.seg[i.mem_operands] = &ss;
6095 break;
6096 case 3:
6097 i.seg[i.mem_operands] = &ds;
6098 break;
6099 case 4:
6100 i.seg[i.mem_operands] = &fs;
6101 break;
6102 case 5:
6103 i.seg[i.mem_operands] = &gs;
6104 break;
6105 }
252b5132 6106
24eab124 6107 /* Skip the ':' and whitespace. */
252b5132
RH		 6108 ++op_string;
6109 if (is_space_char (*op_string))
24eab124 6110 ++op_string;
252b5132 6111
24eab124
AM		 6112 if (!is_digit_char (*op_string)
6113 && !is_identifier_char (*op_string)
6114 && *op_string != '('
6115 && *op_string != ABSOLUTE_PREFIX)
6116 {
6117 as_bad (_("bad memory operand `%s'"), op_string);
6118 return 0;
6119 }
47926f60 6120 /* Handle case of %es:*foo. */
24eab124
AM		 6121 if (*op_string == ABSOLUTE_PREFIX)
6122 {
6123 ++op_string;
6124 if (is_space_char (*op_string))
6125 ++op_string;
40fb9820 6126 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 6127 }
6128 goto do_memory_reference;
6129 }
6130 if (*op_string)
6131 {
d0b47220 6132 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 6133 return 0;
6134 }
40fb9820
L		 6135 temp = r->reg_type;
6136 temp.bitfield.baseindex = 0;
c6fb90c8
L		 6137 i.types[this_operand] = operand_type_or (i.types[this_operand],
6138 temp);
520dc8e8 6139 i.op[this_operand].regs = r;
24eab124
AM		 6140 i.reg_operands++;
6141 }
af6bdddf
AM		 6142 else if (*op_string == REGISTER_PREFIX)
6143 {
6144 as_bad (_("bad register name `%s'"), op_string);
6145 return 0;
6146 }
24eab124 6147 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 6148 {
24eab124 6149 ++op_string;
40fb9820 6150 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 6151 {
d0b47220 6152 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 6153 return 0;
6154 }
6155 if (!i386_immediate (op_string))
6156 return 0;
6157 }
6158 else if (is_digit_char (*op_string)
6159 || is_identifier_char (*op_string)
e5cb08ac 6160 || *op_string == '(')
24eab124 6161 {
47926f60 6162 /* This is a memory reference of some sort. */
af6bdddf 6163 char *base_string;
252b5132 6164
47926f60 6165 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 6166 char *displacement_string_start;
6167 char *displacement_string_end;
252b5132 6168
24eab124 6169 do_memory_reference:
24eab124 6170 if ((i.mem_operands == 1
40fb9820 6171 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 6172 || i.mem_operands == 2)
6173 {
6174 as_bad (_("too many memory references for `%s'"),
6175 current_templates->start->name);
6176 return 0;
6177 }
252b5132 6178
24eab124
AM		 6179 /* Check for base index form. We detect the base index form by
6180 looking for an ')' at the end of the operand, searching
6181 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6182 after the '('. */
af6bdddf 6183 base_string = op_string + strlen (op_string);
c3332e24 6184
af6bdddf
AM		 6185 --base_string;
6186 if (is_space_char (*base_string))
6187 --base_string;
252b5132 6188
47926f60 6189 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 6190 displacement_string_start = op_string;
6191 displacement_string_end = base_string + 1;
252b5132 6192
24eab124
AM		 6193 if (*base_string == ')')
6194 {
af6bdddf 6195 char *temp_string;
24eab124
AM		 6196 unsigned int parens_balanced = 1;
6197 /* We've already checked that the number of left & right ()'s are
47926f60 6198 equal, so this loop will not be infinite. */
24eab124
AM		 6199 do
6200 {
6201 base_string--;
6202 if (*base_string == ')')
6203 parens_balanced++;
6204 if (*base_string == '(')
6205 parens_balanced--;
6206 }
6207 while (parens_balanced);
c3332e24 6208
af6bdddf 6209 temp_string = base_string;
c3332e24 6210
24eab124 6211 /* Skip past '(' and whitespace. */
252b5132
RH		 6212 ++base_string;
6213 if (is_space_char (*base_string))
24eab124 6214 ++base_string;
252b5132 6215
af6bdddf 6216 if (*base_string == ','
4eed87de
AM		 6217 || ((i.base_reg = parse_register (base_string, &end_op))
6218 != NULL))
252b5132 6219 {
af6bdddf 6220 displacement_string_end = temp_string;
252b5132 6221
40fb9820 6222 i.types[this_operand].bitfield.baseindex = 1;
252b5132 6223
af6bdddf 6224 if (i.base_reg)
24eab124 6225 {
24eab124
AM		 6226 base_string = end_op;
6227 if (is_space_char (*base_string))
6228 ++base_string;
af6bdddf
AM		 6229 }
6230
6231 /* There may be an index reg or scale factor here. */
6232 if (*base_string == ',')
6233 {
6234 ++base_string;
6235 if (is_space_char (*base_string))
6236 ++base_string;
6237
4eed87de
AM		 6238 if ((i.index_reg = parse_register (base_string, &end_op))
6239 != NULL)
24eab124 6240 {
af6bdddf 6241 base_string = end_op;
24eab124
AM		 6242 if (is_space_char (*base_string))
6243 ++base_string;
af6bdddf
AM		 6244 if (*base_string == ',')
6245 {
6246 ++base_string;
6247 if (is_space_char (*base_string))
6248 ++base_string;
6249 }
e5cb08ac 6250 else if (*base_string != ')')
af6bdddf 6251 {
4eed87de
AM		 6252 as_bad (_("expecting `,' or `)' "
6253 "after index register in `%s'"),
af6bdddf
AM		 6254 operand_string);
6255 return 0;
6256 }
24eab124 6257 }
af6bdddf 6258 else if (*base_string == REGISTER_PREFIX)
24eab124 6259 {
af6bdddf 6260 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 6261 return 0;
6262 }
252b5132 6263
47926f60 6264 /* Check for scale factor. */
551c1ca1 6265 if (*base_string != ')')
af6bdddf 6266 {
551c1ca1
AM		 6267 char *end_scale = i386_scale (base_string);
6268
6269 if (!end_scale)
af6bdddf 6270 return 0;
24eab124 6271
551c1ca1 6272 base_string = end_scale;
af6bdddf
AM		 6273 if (is_space_char (*base_string))
6274 ++base_string;
6275 if (*base_string != ')')
6276 {
4eed87de
AM		 6277 as_bad (_("expecting `)' "
6278 "after scale factor in `%s'"),
af6bdddf
AM		 6279 operand_string);
6280 return 0;
6281 }
6282 }
6283 else if (!i.index_reg)
24eab124 6284 {
4eed87de
AM		 6285 as_bad (_("expecting index register or scale factor "
6286 "after `,'; got '%c'"),
af6bdddf 6287 *base_string);
24eab124
AM		 6288 return 0;
6289 }
6290 }
af6bdddf 6291 else if (*base_string != ')')
24eab124 6292 {
4eed87de
AM		 6293 as_bad (_("expecting `,' or `)' "
6294 "after base register in `%s'"),
af6bdddf 6295 operand_string);
24eab124
AM		 6296 return 0;
6297 }
c3332e24 6298 }
af6bdddf 6299 else if (*base_string == REGISTER_PREFIX)
c3332e24 6300 {
af6bdddf 6301 as_bad (_("bad register name `%s'"), base_string);
24eab124 6302 return 0;
c3332e24 6303 }
24eab124
AM		 6304 }
6305
6306 /* If there's an expression beginning the operand, parse it,
6307 assuming displacement_string_start and
6308 displacement_string_end are meaningful. */
6309 if (displacement_string_start != displacement_string_end)
6310 {
6311 if (!i386_displacement (displacement_string_start,
6312 displacement_string_end))
6313 return 0;
6314 }
6315
6316 /* Special case for (%dx) while doing input/output op. */
6317 if (i.base_reg
c6fb90c8 6318 && UINTS_EQUAL (i.base_reg->reg_type, reg16_inoutportreg)
24eab124
AM		 6319 && i.index_reg == 0
6320 && i.log2_scale_factor == 0
6321 && i.seg[i.mem_operands] == 0
40fb9820 6322 && !operand_type_check (i.types[this_operand], disp))
24eab124 6323 {
c6fb90c8 6324 UINTS_CLEAR (i.types[this_operand]);
40fb9820 6325 i.types[this_operand].bitfield.inoutportreg = 1;
24eab124
AM		 6326 return 1;
6327 }
6328
eecb386c
AM		 6329 if (i386_index_check (operand_string) == 0)
6330 return 0;
24eab124
AM		 6331 i.mem_operands++;
6332 }
6333 else
ce8a8b2f
AM		 6334 {
6335 /* It's not a memory operand; argh! */
24eab124
AM		 6336 as_bad (_("invalid char %s beginning operand %d `%s'"),
6337 output_invalid (*op_string),
6338 this_operand + 1,
6339 op_string);
6340 return 0;
6341 }
47926f60 6342 return 1; /* Normal return. */
252b5132
RH		 6343}
6344\f
ee7fcc42
AM		 6345/* md_estimate_size_before_relax()
6346
6347 Called just before relax() for rs_machine_dependent frags. The x86
6348 assembler uses these frags to handle variable size jump
6349 instructions.
6350
6351 Any symbol that is now undefined will not become defined.
6352 Return the correct fr_subtype in the frag.
6353 Return the initial "guess for variable size of frag" to caller.
6354 The guess is actually the growth beyond the fixed part. Whatever
6355 we do to grow the fixed or variable part contributes to our
6356 returned value. */
6357
252b5132
RH		 6358int
6359md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 6360 fragS *fragP;
6361 segT segment;
252b5132 6362{
252b5132 6363 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 6364 check for un-relaxable symbols. On an ELF system, we can't relax
6365 an externally visible symbol, because it may be overridden by a
6366 shared library. */
6367 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 6368#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6369 || (IS_ELF
31312f95
AM		 6370 && (S_IS_EXTERNAL (fragP->fr_symbol)
6371 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 6372#endif
6373 )
252b5132 6374 {
b98ef147
AM		 6375 /* Symbol is undefined in this segment, or we need to keep a
6376 reloc so that weak symbols can be overridden. */
6377 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 6378 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 6379 unsigned char *opcode;
6380 int old_fr_fix;
f6af82bd 6381
ee7fcc42
AM		 6382 if (fragP->fr_var != NO_RELOC)
6383 reloc_type = fragP->fr_var;
b98ef147 6384 else if (size == 2)
f6af82bd
AM		 6385 reloc_type = BFD_RELOC_16_PCREL;
6386 else
6387 reloc_type = BFD_RELOC_32_PCREL;
252b5132 6388
ee7fcc42
AM		 6389 old_fr_fix = fragP->fr_fix;
6390 opcode = (unsigned char *) fragP->fr_opcode;
6391
fddf5b5b 6392 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 6393 {
fddf5b5b
AM		 6394 case UNCOND_JUMP:
6395 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 6396 opcode[0] = 0xe9;
252b5132 6397 fragP->fr_fix += size;
062cd5e7
AS		 6398 fix_new (fragP, old_fr_fix, size,
6399 fragP->fr_symbol,
6400 fragP->fr_offset, 1,
6401 reloc_type);
252b5132
RH		 6402 break;
6403
fddf5b5b 6404 case COND_JUMP86:
412167cb
AM		 6405 if (size == 2
6406 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 6407 {
6408 /* Negate the condition, and branch past an
6409 unconditional jump. */
6410 opcode[0] ^= 1;
6411 opcode[1] = 3;
6412 /* Insert an unconditional jump. */
6413 opcode[2] = 0xe9;
6414 /* We added two extra opcode bytes, and have a two byte
6415 offset. */
6416 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 6417 fix_new (fragP, old_fr_fix + 2, 2,
6418 fragP->fr_symbol,
6419 fragP->fr_offset, 1,
6420 reloc_type);
fddf5b5b
AM		 6421 break;
6422 }
6423 /* Fall through. */
6424
6425 case COND_JUMP:
412167cb
AM		 6426 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
6427 {
3e02c1cc
AM		 6428 fixS *fixP;
6429
412167cb 6430 fragP->fr_fix += 1;
3e02c1cc
AM		 6431 fixP = fix_new (fragP, old_fr_fix, 1,
6432 fragP->fr_symbol,
6433 fragP->fr_offset, 1,
6434 BFD_RELOC_8_PCREL);
6435 fixP->fx_signed = 1;
412167cb
AM		 6436 break;
6437 }
93c2a809 6438
24eab124 6439 /* This changes the byte-displacement jump 0x7N
fddf5b5b 6440 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 6441 opcode[1] = opcode[0] + 0x10;
f6af82bd 6442 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 6443 /* We've added an opcode byte. */
6444 fragP->fr_fix += 1 + size;
062cd5e7
AS		 6445 fix_new (fragP, old_fr_fix + 1, size,
6446 fragP->fr_symbol,
6447 fragP->fr_offset, 1,
6448 reloc_type);
252b5132 6449 break;
fddf5b5b
AM		 6450
6451 default:
6452 BAD_CASE (fragP->fr_subtype);
6453 break;
252b5132
RH		 6454 }
6455 frag_wane (fragP);
ee7fcc42 6456 return fragP->fr_fix - old_fr_fix;
252b5132 6457 }
93c2a809 6458
93c2a809
AM		 6459 /* Guess size depending on current relax state. Initially the relax
6460 state will correspond to a short jump and we return 1, because
6461 the variable part of the frag (the branch offset) is one byte
6462 long. However, we can relax a section more than once and in that
6463 case we must either set fr_subtype back to the unrelaxed state,
6464 or return the value for the appropriate branch. */
6465 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 6466}
6467
47926f60
KH		 6468/* Called after relax() is finished.
6469
6470 In: Address of frag.
6471 fr_type == rs_machine_dependent.
6472 fr_subtype is what the address relaxed to.
6473
6474 Out: Any fixSs and constants are set up.
6475 Caller will turn frag into a ".space 0". */
6476
252b5132
RH		 6477void
6478md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 6479 bfd *abfd ATTRIBUTE_UNUSED;
6480 segT sec ATTRIBUTE_UNUSED;
29b0f896 6481 fragS *fragP;
252b5132 6482{
29b0f896 6483 unsigned char *opcode;
252b5132 6484 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 6485 offsetT target_address;
6486 offsetT opcode_address;
252b5132 6487 unsigned int extension = 0;
847f7ad4 6488 offsetT displacement_from_opcode_start;
252b5132
RH		 6489
6490 opcode = (unsigned char *) fragP->fr_opcode;
6491
47926f60 6492 /* Address we want to reach in file space. */
252b5132 6493 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 6494
47926f60 6495 /* Address opcode resides at in file space. */
252b5132
RH		 6496 opcode_address = fragP->fr_address + fragP->fr_fix;
6497
47926f60 6498 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 6499 displacement_from_opcode_start = target_address - opcode_address;
6500
fddf5b5b 6501 if ((fragP->fr_subtype & BIG) == 0)
252b5132 6502 {
47926f60
KH		 6503 /* Don't have to change opcode. */
6504 extension = 1; /* 1 opcode + 1 displacement */
252b5132 6505 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 6506 }
6507 else
6508 {
6509 if (no_cond_jump_promotion
6510 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 6511 as_warn_where (fragP->fr_file, fragP->fr_line,
6512 _("long jump required"));
252b5132 6513
fddf5b5b
AM		 6514 switch (fragP->fr_subtype)
6515 {
6516 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6517 extension = 4; /* 1 opcode + 4 displacement */
6518 opcode[0] = 0xe9;
6519 where_to_put_displacement = &opcode[1];
6520 break;
252b5132 6521
fddf5b5b
AM		 6522 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6523 extension = 2; /* 1 opcode + 2 displacement */
6524 opcode[0] = 0xe9;
6525 where_to_put_displacement = &opcode[1];
6526 break;
252b5132 6527
fddf5b5b
AM		 6528 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6529 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6530 extension = 5; /* 2 opcode + 4 displacement */
6531 opcode[1] = opcode[0] + 0x10;
6532 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6533 where_to_put_displacement = &opcode[2];
6534 break;
252b5132 6535
fddf5b5b
AM		 6536 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6537 extension = 3; /* 2 opcode + 2 displacement */
6538 opcode[1] = opcode[0] + 0x10;
6539 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6540 where_to_put_displacement = &opcode[2];
6541 break;
252b5132 6542
fddf5b5b
AM		 6543 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6544 extension = 4;
6545 opcode[0] ^= 1;
6546 opcode[1] = 3;
6547 opcode[2] = 0xe9;
6548 where_to_put_displacement = &opcode[3];
6549 break;
6550
6551 default:
6552 BAD_CASE (fragP->fr_subtype);
6553 break;
6554 }
252b5132 6555 }
fddf5b5b 6556
7b81dfbb
AJ		 6557 /* If size if less then four we are sure that the operand fits,
6558 but if it's 4, then it could be that the displacement is larger
6559 then -/+ 2GB. */
6560 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6561 && object_64bit
6562 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 6563 + ((addressT) 1 << 31))
6564 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 6565 {
6566 as_bad_where (fragP->fr_file, fragP->fr_line,
6567 _("jump target out of range"));
6568 /* Make us emit 0. */
6569 displacement_from_opcode_start = extension;
6570 }
47926f60 6571 /* Now put displacement after opcode. */
252b5132
RH		 6572 md_number_to_chars ((char *) where_to_put_displacement,
6573 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 6574 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 6575 fragP->fr_fix += extension;
6576}
6577\f
47926f60
KH		 6578/* Size of byte displacement jmp. */
6579int md_short_jump_size = 2;
6580
6581/* Size of dword displacement jmp. */
6582int md_long_jump_size = 5;
252b5132 6583
252b5132
RH		 6584void
6585md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
6586 char *ptr;
6587 addressT from_addr, to_addr;
ab9da554
ILT		 6588 fragS *frag ATTRIBUTE_UNUSED;
6589 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 6590{
847f7ad4 6591 offsetT offset;
252b5132
RH		 6592
6593 offset = to_addr - (from_addr + 2);
47926f60
KH		 6594 /* Opcode for byte-disp jump. */
6595 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 6596 md_number_to_chars (ptr + 1, (valueT) offset, 1);
6597}
6598
6599void
6600md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
6601 char *ptr;
6602 addressT from_addr, to_addr;
a38cf1db
AM		 6603 fragS *frag ATTRIBUTE_UNUSED;
6604 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 6605{
847f7ad4 6606 offsetT offset;
252b5132 6607
a38cf1db
AM		 6608 offset = to_addr - (from_addr + 5);
6609 md_number_to_chars (ptr, (valueT) 0xe9, 1);
6610 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 6611}
6612\f
6613/* Apply a fixup (fixS) to segment data, once it has been determined
6614 by our caller that we have all the info we need to fix it up.
6615
6616 On the 386, immediates, displacements, and data pointers are all in
6617 the same (little-endian) format, so we don't need to care about which
6618 we are handling. */
6619
94f592af 6620void
55cf6793 6621md_apply_fix (fixP, valP, seg)
47926f60
KH		 6622 /* The fix we're to put in. */
6623 fixS *fixP;
47926f60 6624 /* Pointer to the value of the bits. */
c6682705 6625 valueT *valP;
47926f60
KH		 6626 /* Segment fix is from. */
6627 segT seg ATTRIBUTE_UNUSED;
252b5132 6628{
94f592af 6629 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 6630 valueT value = *valP;
252b5132 6631
f86103b7 6632#if !defined (TE_Mach)
93382f6d
AM		 6633 if (fixP->fx_pcrel)
6634 {
6635 switch (fixP->fx_r_type)
6636 {
5865bb77
ILT		 6637 default:
6638 break;
6639
d6ab8113
JB		 6640 case BFD_RELOC_64:
6641 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6642 break;
93382f6d 6643 case BFD_RELOC_32:
ae8887b5 6644 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 6645 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6646 break;
6647 case BFD_RELOC_16:
6648 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6649 break;
6650 case BFD_RELOC_8:
6651 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6652 break;
6653 }
6654 }
252b5132 6655
a161fe53 6656 if (fixP->fx_addsy != NULL
31312f95 6657 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 6658 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 6659 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6660 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6661 && !use_rela_relocations)
252b5132 6662 {
31312f95
AM		 6663 /* This is a hack. There should be a better way to handle this.
6664 This covers for the fact that bfd_install_relocation will
6665 subtract the current location (for partial_inplace, PC relative
6666 relocations); see more below. */
252b5132 6667#ifndef OBJ_AOUT
718ddfc0 6668 if (IS_ELF
252b5132
RH		 6669#ifdef TE_PE
6670 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6671#endif
6672 )
6673 value += fixP->fx_where + fixP->fx_frag->fr_address;
6674#endif
6675#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6676 if (IS_ELF)
252b5132 6677 {
6539b54b 6678 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 6679
6539b54b 6680 if ((sym_seg == seg
2f66722d 6681 || (symbol_section_p (fixP->fx_addsy)
6539b54b 6682 && sym_seg != absolute_section))
ae6063d4 6683 && !generic_force_reloc (fixP))
2f66722d
AM		 6684 {
6685 /* Yes, we add the values in twice. This is because
6539b54b
AM		 6686 bfd_install_relocation subtracts them out again. I think
6687 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 6688 it. FIXME. */
6689 value += fixP->fx_where + fixP->fx_frag->fr_address;
6690 }
252b5132
RH		 6691 }
6692#endif
6693#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 6694 /* For some reason, the PE format does not store a
6695 section address offset for a PC relative symbol. */
6696 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 6697 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 6698 value += md_pcrel_from (fixP);
6699#endif
6700 }
6701
6702 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 6703 and we must not disappoint it. */
252b5132 6704#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6705 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 6706 switch (fixP->fx_r_type)
6707 {
6708 case BFD_RELOC_386_PLT32:
3e73aa7c 6709 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 6710 /* Make the jump instruction point to the address of the operand. At
6711 runtime we merely add the offset to the actual PLT entry. */
6712 value = -4;
6713 break;
31312f95 6714
13ae64f3
JJ		 6715 case BFD_RELOC_386_TLS_GD:
6716 case BFD_RELOC_386_TLS_LDM:
13ae64f3 6717 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6718 case BFD_RELOC_386_TLS_IE:
6719 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 6720 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 6721 case BFD_RELOC_X86_64_TLSGD:
6722 case BFD_RELOC_X86_64_TLSLD:
6723 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 6724 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 6725 value = 0; /* Fully resolved at runtime. No addend. */
6726 /* Fallthrough */
6727 case BFD_RELOC_386_TLS_LE:
6728 case BFD_RELOC_386_TLS_LDO_32:
6729 case BFD_RELOC_386_TLS_LE_32:
6730 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6731 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 6732 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 6733 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 6734 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6735 break;
6736
67a4f2b7
AO		 6737 case BFD_RELOC_386_TLS_DESC_CALL:
6738 case BFD_RELOC_X86_64_TLSDESC_CALL:
6739 value = 0; /* Fully resolved at runtime. No addend. */
6740 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6741 fixP->fx_done = 0;
6742 return;
6743
00f7efb6
JJ		 6744 case BFD_RELOC_386_GOT32:
6745 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 6746 value = 0; /* Fully resolved at runtime. No addend. */
6747 break;
47926f60
KH		 6748
6749 case BFD_RELOC_VTABLE_INHERIT:
6750 case BFD_RELOC_VTABLE_ENTRY:
6751 fixP->fx_done = 0;
94f592af 6752 return;
47926f60
KH		 6753
6754 default:
6755 break;
6756 }
6757#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 6758 *valP = value;
f86103b7 6759#endif /* !defined (TE_Mach) */
3e73aa7c 6760
3e73aa7c 6761 /* Are we finished with this relocation now? */
c6682705 6762 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 6763 fixP->fx_done = 1;
6764 else if (use_rela_relocations)
6765 {
6766 fixP->fx_no_overflow = 1;
062cd5e7
AS		 6767 /* Remember value for tc_gen_reloc. */
6768 fixP->fx_addnumber = value;
3e73aa7c
JH		 6769 value = 0;
6770 }
f86103b7 6771
94f592af 6772 md_number_to_chars (p, value, fixP->fx_size);
252b5132 6773}
252b5132 6774\f
252b5132
RH		 6775#define MAX_LITTLENUMS 6
6776
47926f60
KH		 6777/* Turn the string pointed to by litP into a floating point constant
6778 of type TYPE, and emit the appropriate bytes. The number of
6779 LITTLENUMS emitted is stored in *SIZEP. An error message is
6780 returned, or NULL on OK. */
6781
252b5132
RH		 6782char *
6783md_atof (type, litP, sizeP)
2ab9b79e 6784 int type;
252b5132
RH		 6785 char *litP;
6786 int *sizeP;
6787{
6788 int prec;
6789 LITTLENUM_TYPE words[MAX_LITTLENUMS];
6790 LITTLENUM_TYPE *wordP;
6791 char *t;
6792
6793 switch (type)
6794 {
6795 case 'f':
6796 case 'F':
6797 prec = 2;
6798 break;
6799
6800 case 'd':
6801 case 'D':
6802 prec = 4;
6803 break;
6804
6805 case 'x':
6806 case 'X':
6807 prec = 5;
6808 break;
6809
6810 default:
6811 *sizeP = 0;
6812 return _("Bad call to md_atof ()");
6813 }
6814 t = atof_ieee (input_line_pointer, type, words);
6815 if (t)
6816 input_line_pointer = t;
6817
6818 *sizeP = prec * sizeof (LITTLENUM_TYPE);
6819 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
6820 the bigendian 386. */
6821 for (wordP = words + prec - 1; prec--;)
6822 {
6823 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
6824 litP += sizeof (LITTLENUM_TYPE);
6825 }
6826 return 0;
6827}
6828\f
2d545b82 6829static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 6830
252b5132 6831static char *
e3bb37b5 6832output_invalid (int c)
252b5132 6833{
3882b010 6834 if (ISPRINT (c))
f9f21a03
L		 6835 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6836 "'%c'", c);
252b5132 6837 else
f9f21a03 6838 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 6839 "(0x%x)", (unsigned char) c);
252b5132
RH		 6840 return output_invalid_buf;
6841}
6842
af6bdddf 6843/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 6844
6845static const reg_entry *
4d1bb795 6846parse_real_register (char *reg_string, char **end_op)
252b5132 6847{
af6bdddf
AM		 6848 char *s = reg_string;
6849 char *p;
252b5132
RH		 6850 char reg_name_given[MAX_REG_NAME_SIZE + 1];
6851 const reg_entry *r;
6852
6853 /* Skip possible REGISTER_PREFIX and possible whitespace. */
6854 if (*s == REGISTER_PREFIX)
6855 ++s;
6856
6857 if (is_space_char (*s))
6858 ++s;
6859
6860 p = reg_name_given;
af6bdddf 6861 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 6862 {
6863 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 6864 return (const reg_entry *) NULL;
6865 s++;
252b5132
RH		 6866 }
6867
6588847e
DN		 6868 /* For naked regs, make sure that we are not dealing with an identifier.
6869 This prevents confusing an identifier like `eax_var' with register
6870 `eax'. */
6871 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
6872 return (const reg_entry *) NULL;
6873
af6bdddf 6874 *end_op = s;
252b5132
RH		 6875
6876 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
6877
5f47d35b 6878 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 6879 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 6880 {
5f47d35b
AM		 6881 if (is_space_char (*s))
6882 ++s;
6883 if (*s == '(')
6884 {
af6bdddf 6885 ++s;
5f47d35b
AM		 6886 if (is_space_char (*s))
6887 ++s;
6888 if (*s >= '0' && *s <= '7')
6889 {
db557034 6890 int fpr = *s - '0';
af6bdddf 6891 ++s;
5f47d35b
AM		 6892 if (is_space_char (*s))
6893 ++s;
6894 if (*s == ')')
6895 {
6896 *end_op = s + 1;
db557034
AM		 6897 r = hash_find (reg_hash, "st(0)");
6898 know (r);
6899 return r + fpr;
5f47d35b 6900 }
5f47d35b 6901 }
47926f60 6902 /* We have "%st(" then garbage. */
5f47d35b
AM		 6903 return (const reg_entry *) NULL;
6904 }
6905 }
6906
1ae00879 6907 if (r != NULL
d946b91f 6908 && ((r->reg_flags & (RegRex64 | RegRex))
40fb9820
L		 6909 || r->reg_type.bitfield.reg64)
6910 && (!cpu_arch_flags.bitfield.cpulm
c6fb90c8 6911 || !UINTS_EQUAL (r->reg_type, control))
1ae00879 6912 && flag_code != CODE_64BIT)
20f0a1fc 6913 return (const reg_entry *) NULL;
1ae00879 6914
252b5132
RH		 6915 return r;
6916}
4d1bb795
JB		 6917
6918/* REG_STRING starts *before* REGISTER_PREFIX. */
6919
6920static const reg_entry *
6921parse_register (char *reg_string, char **end_op)
6922{
6923 const reg_entry *r;
6924
6925 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
6926 r = parse_real_register (reg_string, end_op);
6927 else
6928 r = NULL;
6929 if (!r)
6930 {
6931 char *save = input_line_pointer;
6932 char c;
6933 symbolS *symbolP;
6934
6935 input_line_pointer = reg_string;
6936 c = get_symbol_end ();
6937 symbolP = symbol_find (reg_string);
6938 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
6939 {
6940 const expressionS *e = symbol_get_value_expression (symbolP);
6941
6942 know (e->X_op == O_register);
4eed87de 6943 know (e->X_add_number >= 0
c3fe08fa 6944 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 6945 r = i386_regtab + e->X_add_number;
6946 *end_op = input_line_pointer;
6947 }
6948 *input_line_pointer = c;
6949 input_line_pointer = save;
6950 }
6951 return r;
6952}
6953
6954int
6955i386_parse_name (char *name, expressionS *e, char *nextcharP)
6956{
6957 const reg_entry *r;
6958 char *end = input_line_pointer;
6959
6960 *end = *nextcharP;
6961 r = parse_register (name, &input_line_pointer);
6962 if (r && end <= input_line_pointer)
6963 {
6964 *nextcharP = *input_line_pointer;
6965 *input_line_pointer = 0;
6966 e->X_op = O_register;
6967 e->X_add_number = r - i386_regtab;
6968 return 1;
6969 }
6970 input_line_pointer = end;
6971 *end = 0;
6972 return 0;
6973}
6974
6975void
6976md_operand (expressionS *e)
6977{
6978 if (*input_line_pointer == REGISTER_PREFIX)
6979 {
6980 char *end;
6981 const reg_entry *r = parse_real_register (input_line_pointer, &end);
6982
6983 if (r)
6984 {
6985 e->X_op = O_register;
6986 e->X_add_number = r - i386_regtab;
6987 input_line_pointer = end;
6988 }
6989 }
6990}
6991
252b5132 6992\f
4cc782b5 6993#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 6994const char *md_shortopts = "kVQ:sqn";
252b5132 6995#else
12b55ccc 6996const char *md_shortopts = "qn";
252b5132 6997#endif
6e0b89ee 6998
3e73aa7c 6999#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7000#define OPTION_64 (OPTION_MD_BASE + 1)
7001#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7002#define OPTION_MARCH (OPTION_MD_BASE + 3)
7003#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714 7004
99ad8390
NC		 7005struct option md_longopts[] =
7006{
3e73aa7c 7007 {"32", no_argument, NULL, OPTION_32},
99ad8390 7008#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 7009 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7010#endif
b3b91714 7011 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7012 {"march", required_argument, NULL, OPTION_MARCH},
7013 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH		 7014 {NULL, no_argument, NULL, 0}
7015};
7016size_t md_longopts_size = sizeof (md_longopts);
7017
7018int
9103f4f4 7019md_parse_option (int c, char *arg)
252b5132 7020{
9103f4f4
L		 7021 unsigned int i;
7022
252b5132
RH		 7023 switch (c)
7024 {
12b55ccc
L		 7025 case 'n':
7026 optimize_align_code = 0;
7027 break;
7028
a38cf1db
AM		 7029 case 'q':
7030 quiet_warnings = 1;
252b5132
RH		 7031 break;
7032
7033#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7034 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7035 should be emitted or not. FIXME: Not implemented. */
7036 case 'Q':
252b5132
RH		 7037 break;
7038
7039 /* -V: SVR4 argument to print version ID. */
7040 case 'V':
7041 print_version_id ();
7042 break;
7043
a38cf1db
AM		 7044 /* -k: Ignore for FreeBSD compatibility. */
7045 case 'k':
252b5132 7046 break;
4cc782b5
ILT		 7047
7048 case 's':
7049 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 7050 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 7051 break;
99ad8390
NC		 7052#endif
7053#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 7054 case OPTION_64:
7055 {
7056 const char **list, **l;
7057
3e73aa7c
JH		 7058 list = bfd_target_list ();
7059 for (l = list; *l != NULL; l++)
8620418b 7060 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 7061 || strcmp (*l, "coff-x86-64") == 0
7062 || strcmp (*l, "pe-x86-64") == 0
7063 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 7064 {
7065 default_arch = "x86_64";
7066 break;
7067 }
3e73aa7c 7068 if (*l == NULL)
6e0b89ee 7069 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 7070 free (list);
7071 }
7072 break;
7073#endif
252b5132 7074
6e0b89ee
AM		 7075 case OPTION_32:
7076 default_arch = "i386";
7077 break;
7078
b3b91714
AM		 7079 case OPTION_DIVIDE:
7080#ifdef SVR4_COMMENT_CHARS
7081 {
7082 char *n, *t;
7083 const char *s;
7084
7085 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7086 t = n;
7087 for (s = i386_comment_chars; *s != '\0'; s++)
7088 if (*s != '/')
7089 *t++ = *s;
7090 *t = '\0';
7091 i386_comment_chars = n;
7092 }
7093#endif
7094 break;
7095
9103f4f4
L		 7096 case OPTION_MARCH:
7097 if (*arg == '.')
7098 as_fatal (_("Invalid -march= option: `%s'"), arg);
7099 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7100 {
7101 if (strcmp (arg, cpu_arch [i].name) == 0)
7102 {
ccc9c027 7103 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 7104 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 7105 if (!cpu_arch_tune_set)
7106 {
7107 cpu_arch_tune = cpu_arch_isa;
7108 cpu_arch_tune_flags = cpu_arch_isa_flags;
7109 }
9103f4f4
L		 7110 break;
7111 }
7112 }
7113 if (i >= ARRAY_SIZE (cpu_arch))
7114 as_fatal (_("Invalid -march= option: `%s'"), arg);
7115 break;
7116
7117 case OPTION_MTUNE:
7118 if (*arg == '.')
7119 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7120 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7121 {
7122 if (strcmp (arg, cpu_arch [i].name) == 0)
7123 {
ccc9c027 7124 cpu_arch_tune_set = 1;
9103f4f4
L		 7125 cpu_arch_tune = cpu_arch [i].type;
7126 cpu_arch_tune_flags = cpu_arch[i].flags;
7127 break;
7128 }
7129 }
7130 if (i >= ARRAY_SIZE (cpu_arch))
7131 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7132 break;
7133
252b5132
RH		 7134 default:
7135 return 0;
7136 }
7137 return 1;
7138}
7139
7140void
7141md_show_usage (stream)
7142 FILE *stream;
7143{
4cc782b5
ILT		 7144#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7145 fprintf (stream, _("\
a38cf1db
AM		 7146 -Q ignored\n\
7147 -V print assembler version number\n\
b3b91714
AM		 7148 -k ignored\n"));
7149#endif
7150 fprintf (stream, _("\
12b55ccc 7151 -n Do not optimize code alignment\n\
b3b91714
AM		 7152 -q quieten some warnings\n"));
7153#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7154 fprintf (stream, _("\
a38cf1db 7155 -s ignored\n"));
b3b91714 7156#endif
751d281c
L		 7157#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7158 fprintf (stream, _("\
7159 --32/--64 generate 32bit/64bit code\n"));
7160#endif
b3b91714
AM		 7161#ifdef SVR4_COMMENT_CHARS
7162 fprintf (stream, _("\
7163 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 7164#else
7165 fprintf (stream, _("\
b3b91714 7166 --divide ignored\n"));
4cc782b5 7167#endif
9103f4f4
L		 7168 fprintf (stream, _("\
7169 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
7170 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
4eed87de 7171 core, core2, k6, athlon, k8, generic32, generic64\n"));
9103f4f4 7172
252b5132
RH		 7173}
7174
3e73aa7c 7175#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 7176 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH		 7177
7178/* Pick the target format to use. */
7179
47926f60 7180const char *
e3bb37b5 7181i386_target_format (void)
252b5132 7182{
3e73aa7c 7183 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 7184 {
7185 set_code_flag (CODE_64BIT);
c6fb90c8 7186 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
40fb9820
L		 7187 {
7188 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7189 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7190 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7191 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7192 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7193 cpu_arch_isa_flags.bitfield.cpui686 = 1;
7194 cpu_arch_isa_flags.bitfield.cpup4 = 1;
7195 cpu_arch_isa_flags.bitfield.cpummx= 1;
7196 cpu_arch_isa_flags.bitfield.cpummx2 = 1;
7197 cpu_arch_isa_flags.bitfield.cpusse = 1;
7198 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7199 }
c6fb90c8 7200 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
40fb9820
L		 7201 {
7202 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7203 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7204 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7205 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7206 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7207 cpu_arch_tune_flags.bitfield.cpui686 = 1;
7208 cpu_arch_tune_flags.bitfield.cpup4 = 1;
7209 cpu_arch_tune_flags.bitfield.cpummx= 1;
7210 cpu_arch_tune_flags.bitfield.cpummx2 = 1;
7211 cpu_arch_tune_flags.bitfield.cpusse = 1;
7212 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7213 }
9103f4f4 7214 }
3e73aa7c 7215 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 7216 {
7217 set_code_flag (CODE_32BIT);
c6fb90c8 7218 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
40fb9820
L		 7219 {
7220 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7221 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7222 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7223 }
c6fb90c8 7224 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
40fb9820
L		 7225 {
7226 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7227 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7228 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7229 }
9103f4f4 7230 }
3e73aa7c
JH		 7231 else
7232 as_fatal (_("Unknown architecture"));
252b5132
RH		 7233 switch (OUTPUT_FLAVOR)
7234 {
872ce6ff
L		 7235#ifdef TE_PEP
7236 case bfd_target_coff_flavour:
7237 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
7238 break;
7239#endif
4c63da97
AM		 7240#ifdef OBJ_MAYBE_AOUT
7241 case bfd_target_aout_flavour:
47926f60 7242 return AOUT_TARGET_FORMAT;
4c63da97
AM		 7243#endif
7244#ifdef OBJ_MAYBE_COFF
252b5132
RH		 7245 case bfd_target_coff_flavour:
7246 return "coff-i386";
4c63da97 7247#endif
3e73aa7c 7248#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 7249 case bfd_target_elf_flavour:
3e73aa7c 7250 {
e5cb08ac 7251 if (flag_code == CODE_64BIT)
4fa24527
JB		 7252 {
7253 object_64bit = 1;
7254 use_rela_relocations = 1;
7255 }
9d7cbccd 7256 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 7257 }
4c63da97 7258#endif
252b5132
RH		 7259 default:
7260 abort ();
7261 return NULL;
7262 }
7263}
7264
47926f60 7265#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 7266
7267#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 7268void
7269i386_elf_emit_arch_note (void)
a847613f 7270{
718ddfc0 7271 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 7272 {
7273 char *p;
7274 asection *seg = now_seg;
7275 subsegT subseg = now_subseg;
7276 Elf_Internal_Note i_note;
7277 Elf_External_Note e_note;
7278 asection *note_secp;
7279 int len;
7280
7281 /* Create the .note section. */
7282 note_secp = subseg_new (".note", 0);
7283 bfd_set_section_flags (stdoutput,
7284 note_secp,
7285 SEC_HAS_CONTENTS | SEC_READONLY);
7286
7287 /* Process the arch string. */
7288 len = strlen (cpu_arch_name);
7289
7290 i_note.namesz = len + 1;
7291 i_note.descsz = 0;
7292 i_note.type = NT_ARCH;
7293 p = frag_more (sizeof (e_note.namesz));
7294 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
7295 p = frag_more (sizeof (e_note.descsz));
7296 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
7297 p = frag_more (sizeof (e_note.type));
7298 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
7299 p = frag_more (len + 1);
7300 strcpy (p, cpu_arch_name);
7301
7302 frag_align (2, 0, 0);
7303
7304 subseg_set (seg, subseg);
7305 }
7306}
7307#endif
252b5132 7308\f
252b5132
RH		 7309symbolS *
7310md_undefined_symbol (name)
7311 char *name;
7312{
18dc2407
ILT		 7313 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
7314 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
7315 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
7316 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 7317 {
7318 if (!GOT_symbol)
7319 {
7320 if (symbol_find (name))
7321 as_bad (_("GOT already in symbol table"));
7322 GOT_symbol = symbol_new (name, undefined_section,
7323 (valueT) 0, &zero_address_frag);
7324 };
7325 return GOT_symbol;
7326 }
252b5132
RH		 7327 return 0;
7328}
7329
7330/* Round up a section size to the appropriate boundary. */
47926f60 7331
252b5132
RH		 7332valueT
7333md_section_align (segment, size)
ab9da554 7334 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 7335 valueT size;
7336{
4c63da97
AM		 7337#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7338 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
7339 {
7340 /* For a.out, force the section size to be aligned. If we don't do
7341 this, BFD will align it for us, but it will not write out the
7342 final bytes of the section. This may be a bug in BFD, but it is
7343 easier to fix it here since that is how the other a.out targets
7344 work. */
7345 int align;
7346
7347 align = bfd_get_section_alignment (stdoutput, segment);
7348 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7349 }
252b5132
RH		 7350#endif
7351
7352 return size;
7353}
7354
7355/* On the i386, PC-relative offsets are relative to the start of the
7356 next instruction. That is, the address of the offset, plus its
7357 size, since the offset is always the last part of the insn. */
7358
7359long
e3bb37b5 7360md_pcrel_from (fixS *fixP)
252b5132
RH		 7361{
7362 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
7363}
7364
7365#ifndef I386COFF
7366
7367static void
e3bb37b5 7368s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 7369{
29b0f896 7370 int temp;
252b5132 7371
8a75718c
JB		 7372#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7373 if (IS_ELF)
7374 obj_elf_section_change_hook ();
7375#endif
252b5132
RH		 7376 temp = get_absolute_expression ();
7377 subseg_set (bss_section, (subsegT) temp);
7378 demand_empty_rest_of_line ();
7379}
7380
7381#endif
7382
252b5132 7383void
e3bb37b5 7384i386_validate_fix (fixS *fixp)
252b5132
RH		 7385{
7386 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
7387 {
23df1078
JH		 7388 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
7389 {
4fa24527 7390 if (!object_64bit)
23df1078
JH		 7391 abort ();
7392 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
7393 }
7394 else
7395 {
4fa24527 7396 if (!object_64bit)
d6ab8113
JB		 7397 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
7398 else
7399 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 7400 }
252b5132
RH		 7401 fixp->fx_subsy = 0;
7402 }
7403}
7404
252b5132
RH		 7405arelent *
7406tc_gen_reloc (section, fixp)
ab9da554 7407 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 7408 fixS *fixp;
7409{
7410 arelent *rel;
7411 bfd_reloc_code_real_type code;
7412
7413 switch (fixp->fx_r_type)
7414 {
3e73aa7c
JH		 7415 case BFD_RELOC_X86_64_PLT32:
7416 case BFD_RELOC_X86_64_GOT32:
7417 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 7418 case BFD_RELOC_386_PLT32:
7419 case BFD_RELOC_386_GOT32:
7420 case BFD_RELOC_386_GOTOFF:
7421 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 7422 case BFD_RELOC_386_TLS_GD:
7423 case BFD_RELOC_386_TLS_LDM:
7424 case BFD_RELOC_386_TLS_LDO_32:
7425 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7426 case BFD_RELOC_386_TLS_IE:
7427 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 7428 case BFD_RELOC_386_TLS_LE_32:
7429 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 7430 case BFD_RELOC_386_TLS_GOTDESC:
7431 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 7432 case BFD_RELOC_X86_64_TLSGD:
7433 case BFD_RELOC_X86_64_TLSLD:
7434 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7435 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 7436 case BFD_RELOC_X86_64_GOTTPOFF:
7437 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 7438 case BFD_RELOC_X86_64_TPOFF64:
7439 case BFD_RELOC_X86_64_GOTOFF64:
7440 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 7441 case BFD_RELOC_X86_64_GOT64:
7442 case BFD_RELOC_X86_64_GOTPCREL64:
7443 case BFD_RELOC_X86_64_GOTPC64:
7444 case BFD_RELOC_X86_64_GOTPLT64:
7445 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 7446 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7447 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 7448 case BFD_RELOC_RVA:
7449 case BFD_RELOC_VTABLE_ENTRY:
7450 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 7451#ifdef TE_PE
7452 case BFD_RELOC_32_SECREL:
7453#endif
252b5132
RH		 7454 code = fixp->fx_r_type;
7455 break;
dbbaec26
L		 7456 case BFD_RELOC_X86_64_32S:
7457 if (!fixp->fx_pcrel)
7458 {
7459 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7460 code = fixp->fx_r_type;
7461 break;
7462 }
252b5132 7463 default:
93382f6d 7464 if (fixp->fx_pcrel)
252b5132 7465 {
93382f6d
AM		 7466 switch (fixp->fx_size)
7467 {
7468 default:
b091f402
AM		 7469 as_bad_where (fixp->fx_file, fixp->fx_line,
7470 _("can not do %d byte pc-relative relocation"),
7471 fixp->fx_size);
93382f6d
AM		 7472 code = BFD_RELOC_32_PCREL;
7473 break;
7474 case 1: code = BFD_RELOC_8_PCREL; break;
7475 case 2: code = BFD_RELOC_16_PCREL; break;
7476 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 7477#ifdef BFD64
7478 case 8: code = BFD_RELOC_64_PCREL; break;
7479#endif
93382f6d
AM		 7480 }
7481 }
7482 else
7483 {
7484 switch (fixp->fx_size)
7485 {
7486 default:
b091f402
AM		 7487 as_bad_where (fixp->fx_file, fixp->fx_line,
7488 _("can not do %d byte relocation"),
7489 fixp->fx_size);
93382f6d
AM		 7490 code = BFD_RELOC_32;
7491 break;
7492 case 1: code = BFD_RELOC_8; break;
7493 case 2: code = BFD_RELOC_16; break;
7494 case 4: code = BFD_RELOC_32; break;
937149dd 7495#ifdef BFD64
3e73aa7c 7496 case 8: code = BFD_RELOC_64; break;
937149dd 7497#endif
93382f6d 7498 }
252b5132
RH		 7499 }
7500 break;
7501 }
252b5132 7502
d182319b
JB		 7503 if ((code == BFD_RELOC_32
7504 || code == BFD_RELOC_32_PCREL
7505 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 7506 && GOT_symbol
7507 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 7508 {
4fa24527 7509 if (!object_64bit)
d6ab8113
JB		 7510 code = BFD_RELOC_386_GOTPC;
7511 else
7512 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 7513 }
7b81dfbb
AJ		 7514 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7515 && GOT_symbol
7516 && fixp->fx_addsy == GOT_symbol)
7517 {
7518 code = BFD_RELOC_X86_64_GOTPC64;
7519 }
252b5132
RH		 7520
7521 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 7522 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7523 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 7524
7525 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 7526
3e73aa7c
JH		 7527 if (!use_rela_relocations)
7528 {
7529 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7530 vtable entry to be used in the relocation's section offset. */
7531 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7532 rel->address = fixp->fx_offset;
252b5132 7533
c6682705 7534 rel->addend = 0;
3e73aa7c
JH		 7535 }
7536 /* Use the rela in 64bit mode. */
252b5132 7537 else
3e73aa7c 7538 {
062cd5e7
AS		 7539 if (!fixp->fx_pcrel)
7540 rel->addend = fixp->fx_offset;
7541 else
7542 switch (code)
7543 {
7544 case BFD_RELOC_X86_64_PLT32:
7545 case BFD_RELOC_X86_64_GOT32:
7546 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 7547 case BFD_RELOC_X86_64_TLSGD:
7548 case BFD_RELOC_X86_64_TLSLD:
7549 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 7550 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7551 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 7552 rel->addend = fixp->fx_offset - fixp->fx_size;
7553 break;
7554 default:
7555 rel->addend = (section->vma
7556 - fixp->fx_size
7557 + fixp->fx_addnumber
7558 + md_pcrel_from (fixp));
7559 break;
7560 }
3e73aa7c
JH		 7561 }
7562
252b5132
RH		 7563 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7564 if (rel->howto == NULL)
7565 {
7566 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 7567 _("cannot represent relocation type %s"),
252b5132
RH		 7568 bfd_get_reloc_code_name (code));
7569 /* Set howto to a garbage value so that we can keep going. */
7570 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7571 assert (rel->howto != NULL);
7572 }
7573
7574 return rel;
7575}
7576
64a0c779
DN		 7577\f
7578/* Parse operands using Intel syntax. This implements a recursive descent
7579 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7580 Programmer's Guide.
7581
7582 FIXME: We do not recognize the full operand grammar defined in the MASM
7583 documentation. In particular, all the structure/union and
7584 high-level macro operands are missing.
7585
7586 Uppercase words are terminals, lower case words are non-terminals.
7587 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7588 bars '|' denote choices. Most grammar productions are implemented in
7589 functions called 'intel_<production>'.
7590
7591 Initial production is 'expr'.
7592
9306ca4a 7593 addOp + | -
64a0c779
DN		 7594
7595 alpha [a-zA-Z]
7596
9306ca4a
JB		 7597 binOp & | AND | \| | OR | ^ | XOR
7598
64a0c779
DN		 7599 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7600
7601 constant digits [[ radixOverride ]]
7602
9306ca4a 7603 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 7604
7605 digits decdigit
b77a7acd
AJ		 7606 | digits decdigit
7607 | digits hexdigit
64a0c779
DN		 7608
7609 decdigit [0-9]
7610
9306ca4a
JB		 7611 e04 e04 addOp e05
7612 | e05
7613
7614 e05 e05 binOp e06
b77a7acd 7615 | e06
64a0c779
DN		 7616
7617 e06 e06 mulOp e09
b77a7acd 7618 | e09
64a0c779
DN		 7619
7620 e09 OFFSET e10
a724f0f4
JB		 7621 | SHORT e10
7622 | + e10
7623 | - e10
9306ca4a
JB		 7624 | ~ e10
7625 | NOT e10
64a0c779
DN		 7626 | e09 PTR e10
7627 | e09 : e10
7628 | e10
7629
7630 e10 e10 [ expr ]
b77a7acd 7631 | e11
64a0c779
DN		 7632
7633 e11 ( expr )
b77a7acd 7634 | [ expr ]
64a0c779
DN		 7635 | constant
7636 | dataType
7637 | id
7638 | $
7639 | register
7640
a724f0f4 7641 => expr expr cmpOp e04
9306ca4a 7642 | e04
64a0c779
DN		 7643
7644 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 7645 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 7646
7647 hexdigit a | b | c | d | e | f
b77a7acd 7648 | A | B | C | D | E | F
64a0c779
DN		 7649
7650 id alpha
b77a7acd 7651 | id alpha
64a0c779
DN		 7652 | id decdigit
7653
9306ca4a 7654 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 7655
7656 quote " | '
7657
7658 register specialRegister
b77a7acd 7659 | gpRegister
64a0c779
DN		 7660 | byteRegister
7661
7662 segmentRegister CS | DS | ES | FS | GS | SS
7663
9306ca4a 7664 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 7665 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 7666 | TR3 | TR4 | TR5 | TR6 | TR7
7667
64a0c779
DN		 7668 We simplify the grammar in obvious places (e.g., register parsing is
7669 done by calling parse_register) and eliminate immediate left recursion
7670 to implement a recursive-descent parser.
7671
a724f0f4
JB		 7672 expr e04 expr'
7673
7674 expr' cmpOp e04 expr'
7675 | Empty
9306ca4a
JB		 7676
7677 e04 e05 e04'
7678
7679 e04' addOp e05 e04'
7680 | Empty
64a0c779
DN		 7681
7682 e05 e06 e05'
7683
9306ca4a 7684 e05' binOp e06 e05'
b77a7acd 7685 | Empty
64a0c779
DN		 7686
7687 e06 e09 e06'
7688
7689 e06' mulOp e09 e06'
b77a7acd 7690 | Empty
64a0c779
DN		 7691
7692 e09 OFFSET e10 e09'
a724f0f4
JB		 7693 | SHORT e10'
7694 | + e10'
7695 | - e10'
7696 | ~ e10'
7697 | NOT e10'
b77a7acd 7698 | e10 e09'
64a0c779
DN		 7699
7700 e09' PTR e10 e09'
b77a7acd 7701 | : e10 e09'
64a0c779
DN		 7702 | Empty
7703
7704 e10 e11 e10'
7705
7706 e10' [ expr ] e10'
b77a7acd 7707 | Empty
64a0c779
DN		 7708
7709 e11 ( expr )
b77a7acd 7710 | [ expr ]
64a0c779
DN		 7711 | BYTE
7712 | WORD
7713 | DWORD
9306ca4a 7714 | FWORD
64a0c779 7715 | QWORD
9306ca4a
JB		 7716 | TBYTE
7717 | OWORD
7718 | XMMWORD
64a0c779
DN		 7719 | .
7720 | $
7721 | register
7722 | id
7723 | constant */
7724
7725/* Parsing structure for the intel syntax parser. Used to implement the
7726 semantic actions for the operand grammar. */
7727struct intel_parser_s
7728 {
7729 char *op_string; /* The string being parsed. */
7730 int got_a_float; /* Whether the operand is a float. */
4a1805b1 7731 int op_modifier; /* Operand modifier. */
64a0c779 7732 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 7733 int in_offset; /* >=1 if parsing operand of offset. */
7734 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 7735 const reg_entry *reg; /* Last register reference found. */
7736 char *disp; /* Displacement string being built. */
a724f0f4 7737 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 7738 };
7739
7740static struct intel_parser_s intel_parser;
7741
7742/* Token structure for parsing intel syntax. */
7743struct intel_token
7744 {
7745 int code; /* Token code. */
7746 const reg_entry *reg; /* Register entry for register tokens. */
7747 char *str; /* String representation. */
7748 };
7749
7750static struct intel_token cur_token, prev_token;
7751
50705ef4
AM		 7752/* Token codes for the intel parser. Since T_SHORT is already used
7753 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 7754#define T_NIL -1
7755#define T_CONST 1
7756#define T_REG 2
7757#define T_BYTE 3
7758#define T_WORD 4
9306ca4a
JB		 7759#define T_DWORD 5
7760#define T_FWORD 6
7761#define T_QWORD 7
7762#define T_TBYTE 8
7763#define T_XMMWORD 9
50705ef4 7764#undef T_SHORT
9306ca4a
JB		 7765#define T_SHORT 10
7766#define T_OFFSET 11
7767#define T_PTR 12
7768#define T_ID 13
7769#define T_SHL 14
7770#define T_SHR 15
64a0c779
DN		 7771
7772/* Prototypes for intel parser functions. */
e3bb37b5
L		 7773static int intel_match_token (int);
7774static void intel_putback_token (void);
7775static void intel_get_token (void);
7776static int intel_expr (void);
7777static int intel_e04 (void);
7778static int intel_e05 (void);
7779static int intel_e06 (void);
7780static int intel_e09 (void);
7781static int intel_e10 (void);
7782static int intel_e11 (void);
64a0c779 7783
64a0c779 7784static int
e3bb37b5 7785i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 7786{
7787 int ret;
7788 char *p;
7789
a724f0f4
JB		 7790 p = intel_parser.op_string = xstrdup (operand_string);
7791 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
7792
7793 for (;;)
64a0c779 7794 {
a724f0f4
JB		 7795 /* Initialize token holders. */
7796 cur_token.code = prev_token.code = T_NIL;
7797 cur_token.reg = prev_token.reg = NULL;
7798 cur_token.str = prev_token.str = NULL;
7799
7800 /* Initialize parser structure. */
7801 intel_parser.got_a_float = got_a_float;
7802 intel_parser.op_modifier = 0;
7803 intel_parser.is_mem = 0;
7804 intel_parser.in_offset = 0;
7805 intel_parser.in_bracket = 0;
7806 intel_parser.reg = NULL;
7807 intel_parser.disp[0] = '\0';
7808 intel_parser.next_operand = NULL;
7809
7810 /* Read the first token and start the parser. */
7811 intel_get_token ();
7812 ret = intel_expr ();
7813
7814 if (!ret)
7815 break;
7816
9306ca4a
JB		 7817 if (cur_token.code != T_NIL)
7818 {
7819 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
7820 current_templates->start->name, cur_token.str);
7821 ret = 0;
7822 }
64a0c779
DN		 7823 /* If we found a memory reference, hand it over to i386_displacement
7824 to fill in the rest of the operand fields. */
9306ca4a 7825 else if (intel_parser.is_mem)
64a0c779
DN		 7826 {
7827 if ((i.mem_operands == 1
40fb9820 7828 && !current_templates->start->opcode_modifier.isstring)
64a0c779
DN		 7829 || i.mem_operands == 2)
7830 {
7831 as_bad (_("too many memory references for '%s'"),
7832 current_templates->start->name);
7833 ret = 0;
7834 }
7835 else
7836 {
7837 char *s = intel_parser.disp;
7838 i.mem_operands++;
7839
a724f0f4
JB		 7840 if (!quiet_warnings && intel_parser.is_mem < 0)
7841 /* See the comments in intel_bracket_expr. */
7842 as_warn (_("Treating `%s' as memory reference"), operand_string);
7843
64a0c779
DN		 7844 /* Add the displacement expression. */
7845 if (*s != '\0')
a4622f40
AM		 7846 ret = i386_displacement (s, s + strlen (s));
7847 if (ret)
a724f0f4
JB		 7848 {
7849 /* Swap base and index in 16-bit memory operands like
7850 [si+bx]. Since i386_index_check is also used in AT&T
7851 mode we have to do that here. */
7852 if (i.base_reg
7853 && i.index_reg
40fb9820
L		 7854 && i.base_reg->reg_type.bitfield.reg16
7855 && i.index_reg->reg_type.bitfield.reg16
a724f0f4
JB		 7856 && i.base_reg->reg_num >= 6
7857 && i.index_reg->reg_num < 6)
7858 {
7859 const reg_entry *base = i.index_reg;
7860
7861 i.index_reg = i.base_reg;
7862 i.base_reg = base;
7863 }
7864 ret = i386_index_check (operand_string);
7865 }
64a0c779
DN		 7866 }
7867 }
7868
7869 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 7870 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 7871 || intel_parser.reg == NULL)
7872 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 7873
7874 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 7875 ret = 0;
a724f0f4
JB		 7876 if (!ret || !intel_parser.next_operand)
7877 break;
7878 intel_parser.op_string = intel_parser.next_operand;
7879 this_operand = i.operands++;
64a0c779
DN		 7880 }
7881
7882 free (p);
7883 free (intel_parser.disp);
7884
7885 return ret;
7886}
7887
a724f0f4
JB		 7888#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
7889
7890/* expr e04 expr'
7891
7892 expr' cmpOp e04 expr'
7893 | Empty */
64a0c779 7894static int
e3bb37b5 7895intel_expr (void)
64a0c779 7896{
a724f0f4
JB		 7897 /* XXX Implement the comparison operators. */
7898 return intel_e04 ();
9306ca4a
JB		 7899}
7900
a724f0f4 7901/* e04 e05 e04'
9306ca4a 7902
a724f0f4 7903 e04' addOp e05 e04'
9306ca4a
JB		 7904 | Empty */
7905static int
e3bb37b5 7906intel_e04 (void)
9306ca4a 7907{
a724f0f4 7908 int nregs = -1;
9306ca4a 7909
a724f0f4 7910 for (;;)
9306ca4a 7911 {
a724f0f4
JB		 7912 if (!intel_e05())
7913 return 0;
9306ca4a 7914
a724f0f4
JB		 7915 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7916 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 7917
a724f0f4
JB		 7918 if (cur_token.code == '+')
7919 nregs = -1;
7920 else if (cur_token.code == '-')
7921 nregs = NUM_ADDRESS_REGS;
7922 else
7923 return 1;
64a0c779 7924
a724f0f4
JB		 7925 strcat (intel_parser.disp, cur_token.str);
7926 intel_match_token (cur_token.code);
7927 }
64a0c779
DN		 7928}
7929
64a0c779
DN		 7930/* e05 e06 e05'
7931
9306ca4a 7932 e05' binOp e06 e05'
64a0c779
DN		 7933 | Empty */
7934static int
e3bb37b5 7935intel_e05 (void)
64a0c779 7936{
a724f0f4 7937 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 7938
a724f0f4 7939 for (;;)
64a0c779 7940 {
a724f0f4
JB		 7941 if (!intel_e06())
7942 return 0;
7943
4eed87de
AM		 7944 if (cur_token.code == '&'
7945 || cur_token.code == '|'
7946 || cur_token.code == '^')
a724f0f4
JB		 7947 {
7948 char str[2];
7949
7950 str[0] = cur_token.code;
7951 str[1] = 0;
7952 strcat (intel_parser.disp, str);
7953 }
7954 else
7955 break;
9306ca4a 7956
64a0c779
DN		 7957 intel_match_token (cur_token.code);
7958
a724f0f4
JB		 7959 if (nregs < 0)
7960 nregs = ~nregs;
64a0c779 7961 }
a724f0f4
JB		 7962 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7963 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
7964 return 1;
4a1805b1 7965}
64a0c779
DN		 7966
7967/* e06 e09 e06'
7968
7969 e06' mulOp e09 e06'
b77a7acd 7970 | Empty */
64a0c779 7971static int
e3bb37b5 7972intel_e06 (void)
64a0c779 7973{
a724f0f4 7974 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 7975
a724f0f4 7976 for (;;)
64a0c779 7977 {
a724f0f4
JB		 7978 if (!intel_e09())
7979 return 0;
9306ca4a 7980
4eed87de
AM		 7981 if (cur_token.code == '*'
7982 || cur_token.code == '/'
7983 || cur_token.code == '%')
a724f0f4
JB		 7984 {
7985 char str[2];
9306ca4a 7986
a724f0f4
JB		 7987 str[0] = cur_token.code;
7988 str[1] = 0;
7989 strcat (intel_parser.disp, str);
7990 }
7991 else if (cur_token.code == T_SHL)
7992 strcat (intel_parser.disp, "<<");
7993 else if (cur_token.code == T_SHR)
7994 strcat (intel_parser.disp, ">>");
7995 else
7996 break;
9306ca4a 7997
64e74474 7998 intel_match_token (cur_token.code);
64a0c779 7999
a724f0f4
JB		 8000 if (nregs < 0)
8001 nregs = ~nregs;
64a0c779 8002 }
a724f0f4
JB		 8003 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8004 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
8005 return 1;
64a0c779
DN		 8006}
8007
a724f0f4
JB		 8008/* e09 OFFSET e09
8009 | SHORT e09
8010 | + e09
8011 | - e09
8012 | ~ e09
8013 | NOT e09
9306ca4a
JB		 8014 | e10 e09'
8015
64a0c779 8016 e09' PTR e10 e09'
b77a7acd 8017 | : e10 e09'
64a0c779
DN		 8018 | Empty */
8019static int
e3bb37b5 8020intel_e09 (void)
64a0c779 8021{
a724f0f4
JB		 8022 int nregs = ~NUM_ADDRESS_REGS;
8023 int in_offset = 0;
8024
8025 for (;;)
64a0c779 8026 {
a724f0f4
JB		 8027 /* Don't consume constants here. */
8028 if (cur_token.code == '+' || cur_token.code == '-')
8029 {
8030 /* Need to look one token ahead - if the next token
8031 is a constant, the current token is its sign. */
8032 int next_code;
8033
8034 intel_match_token (cur_token.code);
8035 next_code = cur_token.code;
8036 intel_putback_token ();
8037 if (next_code == T_CONST)
8038 break;
8039 }
8040
8041 /* e09 OFFSET e09 */
8042 if (cur_token.code == T_OFFSET)
8043 {
8044 if (!in_offset++)
8045 ++intel_parser.in_offset;
8046 }
8047
8048 /* e09 SHORT e09 */
8049 else if (cur_token.code == T_SHORT)
8050 intel_parser.op_modifier |= 1 << T_SHORT;
8051
8052 /* e09 + e09 */
8053 else if (cur_token.code == '+')
8054 strcat (intel_parser.disp, "+");
8055
8056 /* e09 - e09
8057 | ~ e09
8058 | NOT e09 */
8059 else if (cur_token.code == '-' || cur_token.code == '~')
8060 {
8061 char str[2];
64a0c779 8062
a724f0f4
JB		 8063 if (nregs < 0)
8064 nregs = ~nregs;
8065 str[0] = cur_token.code;
8066 str[1] = 0;
8067 strcat (intel_parser.disp, str);
8068 }
8069
8070 /* e09 e10 e09' */
8071 else
8072 break;
8073
8074 intel_match_token (cur_token.code);
64a0c779
DN		 8075 }
8076
a724f0f4 8077 for (;;)
9306ca4a 8078 {
a724f0f4
JB		 8079 if (!intel_e10 ())
8080 return 0;
9306ca4a 8081
a724f0f4
JB		 8082 /* e09' PTR e10 e09' */
8083 if (cur_token.code == T_PTR)
8084 {
8085 char suffix;
9306ca4a 8086
a724f0f4
JB		 8087 if (prev_token.code == T_BYTE)
8088 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 8089
a724f0f4
JB		 8090 else if (prev_token.code == T_WORD)
8091 {
8092 if (current_templates->start->name[0] == 'l'
8093 && current_templates->start->name[2] == 's'
8094 && current_templates->start->name[3] == 0)
8095 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8096 else if (intel_parser.got_a_float == 2) /* "fi..." */
8097 suffix = SHORT_MNEM_SUFFIX;
8098 else
8099 suffix = WORD_MNEM_SUFFIX;
8100 }
64a0c779 8101
a724f0f4
JB		 8102 else if (prev_token.code == T_DWORD)
8103 {
8104 if (current_templates->start->name[0] == 'l'
8105 && current_templates->start->name[2] == 's'
8106 && current_templates->start->name[3] == 0)
8107 suffix = WORD_MNEM_SUFFIX;
8108 else if (flag_code == CODE_16BIT
40fb9820
L		 8109 && (current_templates->start->opcode_modifier.jump
8110 || current_templates->start->opcode_modifier.jumpdword))
a724f0f4
JB		 8111 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8112 else if (intel_parser.got_a_float == 1) /* "f..." */
8113 suffix = SHORT_MNEM_SUFFIX;
8114 else
8115 suffix = LONG_MNEM_SUFFIX;
8116 }
9306ca4a 8117
a724f0f4
JB		 8118 else if (prev_token.code == T_FWORD)
8119 {
8120 if (current_templates->start->name[0] == 'l'
8121 && current_templates->start->name[2] == 's'
8122 && current_templates->start->name[3] == 0)
8123 suffix = LONG_MNEM_SUFFIX;
8124 else if (!intel_parser.got_a_float)
8125 {
8126 if (flag_code == CODE_16BIT)
8127 add_prefix (DATA_PREFIX_OPCODE);
8128 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8129 }
8130 else
8131 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8132 }
64a0c779 8133
a724f0f4
JB		 8134 else if (prev_token.code == T_QWORD)
8135 {
8136 if (intel_parser.got_a_float == 1) /* "f..." */
8137 suffix = LONG_MNEM_SUFFIX;
8138 else
8139 suffix = QWORD_MNEM_SUFFIX;
8140 }
64a0c779 8141
a724f0f4
JB		 8142 else if (prev_token.code == T_TBYTE)
8143 {
8144 if (intel_parser.got_a_float == 1)
8145 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8146 else
8147 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8148 }
9306ca4a 8149
a724f0f4 8150 else if (prev_token.code == T_XMMWORD)
9306ca4a 8151 {
a724f0f4
JB		 8152 /* XXX ignored for now, but accepted since gcc uses it */
8153 suffix = 0;
9306ca4a 8154 }
64a0c779 8155
f16b83df 8156 else
a724f0f4
JB		 8157 {
8158 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
8159 return 0;
8160 }
8161
435acd52
JB		 8162 /* Operands for jump/call using 'ptr' notation denote absolute
8163 addresses. */
40fb9820
L		 8164 if (current_templates->start->opcode_modifier.jump
8165 || current_templates->start->opcode_modifier.jumpdword)
8166 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 8167
a724f0f4
JB		 8168 if (current_templates->start->base_opcode == 0x8d /* lea */)
8169 ;
8170 else if (!i.suffix)
8171 i.suffix = suffix;
8172 else if (i.suffix != suffix)
8173 {
8174 as_bad (_("Conflicting operand modifiers"));
8175 return 0;
8176 }
64a0c779 8177
9306ca4a
JB		 8178 }
8179
a724f0f4
JB		 8180 /* e09' : e10 e09' */
8181 else if (cur_token.code == ':')
9306ca4a 8182 {
a724f0f4
JB		 8183 if (prev_token.code != T_REG)
8184 {
8185 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8186 segment/group identifier (which we don't have), using comma
8187 as the operand separator there is even less consistent, since
8188 there all branches only have a single operand. */
8189 if (this_operand != 0
8190 || intel_parser.in_offset
8191 || intel_parser.in_bracket
40fb9820
L		 8192 || (!current_templates->start->opcode_modifier.jump
8193 && !current_templates->start->opcode_modifier.jumpdword
8194 && !current_templates->start->opcode_modifier.jumpintersegment
8195 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
a724f0f4
JB		 8196 return intel_match_token (T_NIL);
8197 /* Remember the start of the 2nd operand and terminate 1st
8198 operand here.
8199 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8200 another expression), but it gets at least the simplest case
8201 (a plain number or symbol on the left side) right. */
8202 intel_parser.next_operand = intel_parser.op_string;
8203 *--intel_parser.op_string = '\0';
8204 return intel_match_token (':');
8205 }
9306ca4a 8206 }
64a0c779 8207
a724f0f4 8208 /* e09' Empty */
64a0c779 8209 else
a724f0f4 8210 break;
64a0c779 8211
a724f0f4
JB		 8212 intel_match_token (cur_token.code);
8213
8214 }
8215
8216 if (in_offset)
8217 {
8218 --intel_parser.in_offset;
8219 if (nregs < 0)
8220 nregs = ~nregs;
8221 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 8222 {
a724f0f4 8223 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 8224 return 0;
8225 }
a724f0f4
JB		 8226 intel_parser.op_modifier |= 1 << T_OFFSET;
8227 }
9306ca4a 8228
a724f0f4
JB		 8229 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8230 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
8231 return 1;
8232}
64a0c779 8233
a724f0f4 8234static int
e3bb37b5 8235intel_bracket_expr (void)
a724f0f4
JB		 8236{
8237 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
8238 const char *start = intel_parser.op_string;
8239 int len;
8240
8241 if (i.op[this_operand].regs)
8242 return intel_match_token (T_NIL);
8243
8244 intel_match_token ('[');
8245
8246 /* Mark as a memory operand only if it's not already known to be an
8247 offset expression. If it's an offset expression, we need to keep
8248 the brace in. */
8249 if (!intel_parser.in_offset)
8250 {
8251 ++intel_parser.in_bracket;
435acd52
JB		 8252
8253 /* Operands for jump/call inside brackets denote absolute addresses. */
40fb9820
L		 8254 if (current_templates->start->opcode_modifier.jump
8255 || current_templates->start->opcode_modifier.jumpdword)
8256 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 8257
a724f0f4
JB		 8258 /* Unfortunately gas always diverged from MASM in a respect that can't
8259 be easily fixed without risking to break code sequences likely to be
8260 encountered (the testsuite even check for this): MASM doesn't consider
8261 an expression inside brackets unconditionally as a memory reference.
8262 When that is e.g. a constant, an offset expression, or the sum of the
8263 two, this is still taken as a constant load. gas, however, always
8264 treated these as memory references. As a compromise, we'll try to make
8265 offset expressions inside brackets work the MASM way (since that's
8266 less likely to be found in real world code), but make constants alone
8267 continue to work the traditional gas way. In either case, issue a
8268 warning. */
8269 intel_parser.op_modifier &= ~was_offset;
64a0c779 8270 }
a724f0f4 8271 else
64e74474 8272 strcat (intel_parser.disp, "[");
a724f0f4
JB		 8273
8274 /* Add a '+' to the displacement string if necessary. */
8275 if (*intel_parser.disp != '\0'
8276 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
8277 strcat (intel_parser.disp, "+");
64a0c779 8278
a724f0f4
JB		 8279 if (intel_expr ()
8280 && (len = intel_parser.op_string - start - 1,
8281 intel_match_token (']')))
64a0c779 8282 {
a724f0f4
JB		 8283 /* Preserve brackets when the operand is an offset expression. */
8284 if (intel_parser.in_offset)
8285 strcat (intel_parser.disp, "]");
8286 else
8287 {
8288 --intel_parser.in_bracket;
8289 if (i.base_reg || i.index_reg)
8290 intel_parser.is_mem = 1;
8291 if (!intel_parser.is_mem)
8292 {
8293 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8294 /* Defer the warning until all of the operand was parsed. */
8295 intel_parser.is_mem = -1;
8296 else if (!quiet_warnings)
4eed87de
AM		 8297 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8298 len, start, len, start);
a724f0f4
JB		 8299 }
8300 }
8301 intel_parser.op_modifier |= was_offset;
64a0c779 8302
a724f0f4 8303 return 1;
64a0c779 8304 }
a724f0f4 8305 return 0;
64a0c779
DN		 8306}
8307
8308/* e10 e11 e10'
8309
8310 e10' [ expr ] e10'
b77a7acd 8311 | Empty */
64a0c779 8312static int
e3bb37b5 8313intel_e10 (void)
64a0c779 8314{
a724f0f4
JB		 8315 if (!intel_e11 ())
8316 return 0;
64a0c779 8317
a724f0f4 8318 while (cur_token.code == '[')
64a0c779 8319 {
a724f0f4 8320 if (!intel_bracket_expr ())
21d6c4af 8321 return 0;
64a0c779
DN		 8322 }
8323
a724f0f4 8324 return 1;
64a0c779
DN		 8325}
8326
64a0c779 8327/* e11 ( expr )
b77a7acd 8328 | [ expr ]
64a0c779
DN		 8329 | BYTE
8330 | WORD
8331 | DWORD
9306ca4a 8332 | FWORD
64a0c779 8333 | QWORD
9306ca4a
JB		 8334 | TBYTE
8335 | OWORD
8336 | XMMWORD
4a1805b1 8337 | $
64a0c779
DN		 8338 | .
8339 | register
8340 | id
8341 | constant */
8342static int
e3bb37b5 8343intel_e11 (void)
64a0c779 8344{
a724f0f4 8345 switch (cur_token.code)
64a0c779 8346 {
a724f0f4
JB		 8347 /* e11 ( expr ) */
8348 case '(':
64a0c779
DN		 8349 intel_match_token ('(');
8350 strcat (intel_parser.disp, "(");
8351
8352 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 8353 {
8354 strcat (intel_parser.disp, ")");
8355 return 1;
8356 }
a724f0f4 8357 return 0;
4a1805b1 8358
a724f0f4
JB		 8359 /* e11 [ expr ] */
8360 case '[':
a724f0f4 8361 return intel_bracket_expr ();
64a0c779 8362
a724f0f4
JB		 8363 /* e11 $
8364 | . */
8365 case '.':
64a0c779
DN		 8366 strcat (intel_parser.disp, cur_token.str);
8367 intel_match_token (cur_token.code);
21d6c4af
DN		 8368
8369 /* Mark as a memory operand only if it's not already known to be an
8370 offset expression. */
a724f0f4 8371 if (!intel_parser.in_offset)
21d6c4af 8372 intel_parser.is_mem = 1;
64a0c779
DN		 8373
8374 return 1;
64a0c779 8375
a724f0f4
JB		 8376 /* e11 register */
8377 case T_REG:
8378 {
8379 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 8380
a724f0f4 8381 intel_match_token (T_REG);
64a0c779 8382
a724f0f4
JB		 8383 /* Check for segment change. */
8384 if (cur_token.code == ':')
8385 {
40fb9820
L		 8386 if (!reg->reg_type.bitfield.sreg2
8387 && !reg->reg_type.bitfield.sreg3)
a724f0f4 8388 {
4eed87de
AM		 8389 as_bad (_("`%s' is not a valid segment register"),
8390 reg->reg_name);
a724f0f4
JB		 8391 return 0;
8392 }
8393 else if (i.seg[i.mem_operands])
8394 as_warn (_("Extra segment override ignored"));
8395 else
8396 {
8397 if (!intel_parser.in_offset)
8398 intel_parser.is_mem = 1;
8399 switch (reg->reg_num)
8400 {
8401 case 0:
8402 i.seg[i.mem_operands] = &es;
8403 break;
8404 case 1:
8405 i.seg[i.mem_operands] = &cs;
8406 break;
8407 case 2:
8408 i.seg[i.mem_operands] = &ss;
8409 break;
8410 case 3:
8411 i.seg[i.mem_operands] = &ds;
8412 break;
8413 case 4:
8414 i.seg[i.mem_operands] = &fs;
8415 break;
8416 case 5:
8417 i.seg[i.mem_operands] = &gs;
8418 break;
8419 }
8420 }
8421 }
64a0c779 8422
a724f0f4
JB		 8423 /* Not a segment register. Check for register scaling. */
8424 else if (cur_token.code == '*')
8425 {
8426 if (!intel_parser.in_bracket)
8427 {
8428 as_bad (_("Register scaling only allowed in memory operands"));
8429 return 0;
8430 }
64a0c779 8431
40fb9820 8432 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
a724f0f4
JB		 8433 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
8434 else if (i.index_reg)
8435 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 8436
a724f0f4
JB		 8437 /* What follows must be a valid scale. */
8438 intel_match_token ('*');
8439 i.index_reg = reg;
40fb9820 8440 i.types[this_operand].bitfield.baseindex = 1;
64a0c779 8441
a724f0f4
JB		 8442 /* Set the scale after setting the register (otherwise,
8443 i386_scale will complain) */
8444 if (cur_token.code == '+' || cur_token.code == '-')
8445 {
8446 char *str, sign = cur_token.code;
8447 intel_match_token (cur_token.code);
8448 if (cur_token.code != T_CONST)
8449 {
8450 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8451 cur_token.str);
8452 return 0;
8453 }
8454 str = (char *) xmalloc (strlen (cur_token.str) + 2);
8455 strcpy (str + 1, cur_token.str);
8456 *str = sign;
8457 if (!i386_scale (str))
8458 return 0;
8459 free (str);
8460 }
8461 else if (!i386_scale (cur_token.str))
64a0c779 8462 return 0;
a724f0f4
JB		 8463 intel_match_token (cur_token.code);
8464 }
64a0c779 8465
a724f0f4
JB		 8466 /* No scaling. If this is a memory operand, the register is either a
8467 base register (first occurrence) or an index register (second
8468 occurrence). */
7b0441f6 8469 else if (intel_parser.in_bracket)
a724f0f4 8470 {
64a0c779 8471
a724f0f4
JB		 8472 if (!i.base_reg)
8473 i.base_reg = reg;
8474 else if (!i.index_reg)
8475 i.index_reg = reg;
8476 else
8477 {
8478 as_bad (_("Too many register references in memory operand"));
8479 return 0;
8480 }
64a0c779 8481
40fb9820 8482 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4 8483 }
4a1805b1 8484
4d1bb795
JB		 8485 /* It's neither base nor index. */
8486 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4 8487 {
40fb9820
L		 8488 i386_operand_type temp = reg->reg_type;
8489 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8490 i.types[this_operand] = operand_type_or (i.types[this_operand],
8491 temp);
a724f0f4
JB		 8492 i.op[this_operand].regs = reg;
8493 i.reg_operands++;
8494 }
8495 else
8496 {
8497 as_bad (_("Invalid use of register"));
8498 return 0;
8499 }
64a0c779 8500
a724f0f4
JB		 8501 /* Since registers are not part of the displacement string (except
8502 when we're parsing offset operands), we may need to remove any
8503 preceding '+' from the displacement string. */
8504 if (*intel_parser.disp != '\0'
8505 && !intel_parser.in_offset)
8506 {
8507 char *s = intel_parser.disp;
8508 s += strlen (s) - 1;
8509 if (*s == '+')
8510 *s = '\0';
8511 }
4a1805b1 8512
a724f0f4
JB		 8513 return 1;
8514 }
8515
8516 /* e11 BYTE
8517 | WORD
8518 | DWORD
8519 | FWORD
8520 | QWORD
8521 | TBYTE
8522 | OWORD
8523 | XMMWORD */
8524 case T_BYTE:
8525 case T_WORD:
8526 case T_DWORD:
8527 case T_FWORD:
8528 case T_QWORD:
8529 case T_TBYTE:
8530 case T_XMMWORD:
8531 intel_match_token (cur_token.code);
64a0c779 8532
a724f0f4
JB		 8533 if (cur_token.code == T_PTR)
8534 return 1;
8535
8536 /* It must have been an identifier. */
8537 intel_putback_token ();
8538 cur_token.code = T_ID;
8539 /* FALLTHRU */
8540
8541 /* e11 id
8542 | constant */
8543 case T_ID:
8544 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 8545 {
8546 symbolS *symbolP;
8547
a724f0f4
JB		 8548 /* The identifier represents a memory reference only if it's not
8549 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 8550 symbolP = symbol_find(cur_token.str);
8551 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8552 intel_parser.is_mem = 1;
8553 }
a724f0f4 8554 /* FALLTHRU */
64a0c779 8555
a724f0f4
JB		 8556 case T_CONST:
8557 case '-':
8558 case '+':
8559 {
8560 char *save_str, sign = 0;
64a0c779 8561
a724f0f4
JB		 8562 /* Allow constants that start with `+' or `-'. */
8563 if (cur_token.code == '-' || cur_token.code == '+')
8564 {
8565 sign = cur_token.code;
8566 intel_match_token (cur_token.code);
8567 if (cur_token.code != T_CONST)
8568 {
8569 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8570 cur_token.str);
8571 return 0;
8572 }
8573 }
64a0c779 8574
a724f0f4
JB		 8575 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8576 strcpy (save_str + !!sign, cur_token.str);
8577 if (sign)
8578 *save_str = sign;
64a0c779 8579
a724f0f4
JB		 8580 /* Get the next token to check for register scaling. */
8581 intel_match_token (cur_token.code);
64a0c779 8582
4eed87de
AM		 8583 /* Check if this constant is a scaling factor for an
8584 index register. */
a724f0f4
JB		 8585 if (cur_token.code == '*')
8586 {
8587 if (intel_match_token ('*') && cur_token.code == T_REG)
8588 {
8589 const reg_entry *reg = cur_token.reg;
8590
8591 if (!intel_parser.in_bracket)
8592 {
4eed87de
AM		 8593 as_bad (_("Register scaling only allowed "
8594 "in memory operands"));
a724f0f4
JB		 8595 return 0;
8596 }
8597
4eed87de
AM		 8598 /* Disallow things like [1*si].
8599 sp and esp are invalid as index. */
40fb9820 8600 if (reg->reg_type.bitfield.reg16)
4eed87de 8601 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 8602 else if (i.index_reg)
4eed87de 8603 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 8604
8605 /* The constant is followed by `* reg', so it must be
8606 a valid scale. */
8607 i.index_reg = reg;
40fb9820 8608 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4
JB		 8609
8610 /* Set the scale after setting the register (otherwise,
8611 i386_scale will complain) */
8612 if (!i386_scale (save_str))
64a0c779 8613 return 0;
a724f0f4
JB		 8614 intel_match_token (T_REG);
8615
8616 /* Since registers are not part of the displacement
8617 string, we may need to remove any preceding '+' from
8618 the displacement string. */
8619 if (*intel_parser.disp != '\0')
8620 {
8621 char *s = intel_parser.disp;
8622 s += strlen (s) - 1;
8623 if (*s == '+')
8624 *s = '\0';
8625 }
8626
8627 free (save_str);
8628
8629 return 1;
8630 }
64a0c779 8631
a724f0f4
JB		 8632 /* The constant was not used for register scaling. Since we have
8633 already consumed the token following `*' we now need to put it
8634 back in the stream. */
64a0c779 8635 intel_putback_token ();
a724f0f4 8636 }
64a0c779 8637
a724f0f4
JB		 8638 /* Add the constant to the displacement string. */
8639 strcat (intel_parser.disp, save_str);
8640 free (save_str);
64a0c779 8641
a724f0f4
JB		 8642 return 1;
8643 }
64a0c779
DN		 8644 }
8645
64a0c779
DN		 8646 as_bad (_("Unrecognized token '%s'"), cur_token.str);
8647 return 0;
8648}
8649
64a0c779
DN		 8650/* Match the given token against cur_token. If they match, read the next
8651 token from the operand string. */
8652static int
e3bb37b5 8653intel_match_token (int code)
64a0c779
DN		 8654{
8655 if (cur_token.code == code)
8656 {
8657 intel_get_token ();
8658 return 1;
8659 }
8660 else
8661 {
0477af35 8662 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 8663 return 0;
8664 }
8665}
8666
64a0c779
DN		 8667/* Read a new token from intel_parser.op_string and store it in cur_token. */
8668static void
e3bb37b5 8669intel_get_token (void)
64a0c779
DN		 8670{
8671 char *end_op;
8672 const reg_entry *reg;
8673 struct intel_token new_token;
8674
8675 new_token.code = T_NIL;
8676 new_token.reg = NULL;
8677 new_token.str = NULL;
8678
4a1805b1 8679 /* Free the memory allocated to the previous token and move
64a0c779
DN		 8680 cur_token to prev_token. */
8681 if (prev_token.str)
8682 free (prev_token.str);
8683
8684 prev_token = cur_token;
8685
8686 /* Skip whitespace. */
8687 while (is_space_char (*intel_parser.op_string))
8688 intel_parser.op_string++;
8689
8690 /* Return an empty token if we find nothing else on the line. */
8691 if (*intel_parser.op_string == '\0')
8692 {
8693 cur_token = new_token;
8694 return;
8695 }
8696
8697 /* The new token cannot be larger than the remainder of the operand
8698 string. */
a724f0f4 8699 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 8700 new_token.str[0] = '\0';
8701
8702 if (strchr ("0123456789", *intel_parser.op_string))
8703 {
8704 char *p = new_token.str;
8705 char *q = intel_parser.op_string;
8706 new_token.code = T_CONST;
8707
8708 /* Allow any kind of identifier char to encompass floating point and
8709 hexadecimal numbers. */
8710 while (is_identifier_char (*q))
8711 *p++ = *q++;
8712 *p = '\0';
8713
8714 /* Recognize special symbol names [0-9][bf]. */
8715 if (strlen (intel_parser.op_string) == 2
4a1805b1 8716 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 8717 || intel_parser.op_string[1] == 'f'))
8718 new_token.code = T_ID;
8719 }
8720
4d1bb795 8721 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 8722 {
4d1bb795
JB		 8723 size_t len = end_op - intel_parser.op_string;
8724
64a0c779
DN		 8725 new_token.code = T_REG;
8726 new_token.reg = reg;
8727
4d1bb795
JB		 8728 memcpy (new_token.str, intel_parser.op_string, len);
8729 new_token.str[len] = '\0';
64a0c779
DN		 8730 }
8731
8732 else if (is_identifier_char (*intel_parser.op_string))
8733 {
8734 char *p = new_token.str;
8735 char *q = intel_parser.op_string;
8736
8737 /* A '.' or '$' followed by an identifier char is an identifier.
8738 Otherwise, it's operator '.' followed by an expression. */
8739 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
8740 {
9306ca4a
JB		 8741 new_token.code = '.';
8742 new_token.str[0] = '.';
64a0c779
DN		 8743 new_token.str[1] = '\0';
8744 }
8745 else
8746 {
8747 while (is_identifier_char (*q) || *q == '@')
8748 *p++ = *q++;
8749 *p = '\0';
8750
9306ca4a
JB		 8751 if (strcasecmp (new_token.str, "NOT") == 0)
8752 new_token.code = '~';
8753
8754 else if (strcasecmp (new_token.str, "MOD") == 0)
8755 new_token.code = '%';
8756
8757 else if (strcasecmp (new_token.str, "AND") == 0)
8758 new_token.code = '&';
8759
8760 else if (strcasecmp (new_token.str, "OR") == 0)
8761 new_token.code = '|';
8762
8763 else if (strcasecmp (new_token.str, "XOR") == 0)
8764 new_token.code = '^';
8765
8766 else if (strcasecmp (new_token.str, "SHL") == 0)
8767 new_token.code = T_SHL;
8768
8769 else if (strcasecmp (new_token.str, "SHR") == 0)
8770 new_token.code = T_SHR;
8771
8772 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 8773 new_token.code = T_BYTE;
8774
8775 else if (strcasecmp (new_token.str, "WORD") == 0)
8776 new_token.code = T_WORD;
8777
8778 else if (strcasecmp (new_token.str, "DWORD") == 0)
8779 new_token.code = T_DWORD;
8780
9306ca4a
JB		 8781 else if (strcasecmp (new_token.str, "FWORD") == 0)
8782 new_token.code = T_FWORD;
8783
64a0c779
DN		 8784 else if (strcasecmp (new_token.str, "QWORD") == 0)
8785 new_token.code = T_QWORD;
8786
9306ca4a
JB		 8787 else if (strcasecmp (new_token.str, "TBYTE") == 0
8788 /* XXX remove (gcc still uses it) */
8789 || strcasecmp (new_token.str, "XWORD") == 0)
8790 new_token.code = T_TBYTE;
8791
8792 else if (strcasecmp (new_token.str, "XMMWORD") == 0
8793 || strcasecmp (new_token.str, "OWORD") == 0)
8794 new_token.code = T_XMMWORD;
64a0c779
DN		 8795
8796 else if (strcasecmp (new_token.str, "PTR") == 0)
8797 new_token.code = T_PTR;
8798
8799 else if (strcasecmp (new_token.str, "SHORT") == 0)
8800 new_token.code = T_SHORT;
8801
8802 else if (strcasecmp (new_token.str, "OFFSET") == 0)
8803 {
8804 new_token.code = T_OFFSET;
8805
8806 /* ??? This is not mentioned in the MASM grammar but gcc
8807 makes use of it with -mintel-syntax. OFFSET may be
8808 followed by FLAT: */
8809 if (strncasecmp (q, " FLAT:", 6) == 0)
8810 strcat (new_token.str, " FLAT:");
8811 }
8812
8813 /* ??? This is not mentioned in the MASM grammar. */
8814 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 8815 {
8816 new_token.code = T_OFFSET;
8817 if (*q == ':')
8818 strcat (new_token.str, ":");
8819 else
8820 as_bad (_("`:' expected"));
8821 }
64a0c779
DN		 8822
8823 else
8824 new_token.code = T_ID;
8825 }
8826 }
8827
9306ca4a
JB		 8828 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
8829 {
8830 new_token.code = *intel_parser.op_string;
8831 new_token.str[0] = *intel_parser.op_string;
8832 new_token.str[1] = '\0';
8833 }
8834
8835 else if (strchr ("<>", *intel_parser.op_string)
8836 && *intel_parser.op_string == *(intel_parser.op_string + 1))
8837 {
8838 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
8839 new_token.str[0] = *intel_parser.op_string;
8840 new_token.str[1] = *intel_parser.op_string;
8841 new_token.str[2] = '\0';
8842 }
8843
64a0c779 8844 else
0477af35 8845 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 8846
8847 intel_parser.op_string += strlen (new_token.str);
8848 cur_token = new_token;
8849}
8850
64a0c779
DN		 8851/* Put cur_token back into the token stream and make cur_token point to
8852 prev_token. */
8853static void
e3bb37b5 8854intel_putback_token (void)
64a0c779 8855{
a724f0f4
JB		 8856 if (cur_token.code != T_NIL)
8857 {
8858 intel_parser.op_string -= strlen (cur_token.str);
8859 free (cur_token.str);
8860 }
64a0c779 8861 cur_token = prev_token;
4a1805b1 8862
64a0c779
DN		 8863 /* Forget prev_token. */
8864 prev_token.code = T_NIL;
8865 prev_token.reg = NULL;
8866 prev_token.str = NULL;
8867}
54cfded0 8868
a4447b93 8869int
1df69f4f 8870tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 8871{
8872 unsigned int regnum;
8873 unsigned int regnames_count;
089dfecd 8874 static const char *const regnames_32[] =
54cfded0 8875 {
a4447b93
RH		 8876 "eax", "ecx", "edx", "ebx",
8877 "esp", "ebp", "esi", "edi",
089dfecd
JB		 8878 "eip", "eflags", NULL,
8879 "st0", "st1", "st2", "st3",
8880 "st4", "st5", "st6", "st7",
8881 NULL, NULL,
8882 "xmm0", "xmm1", "xmm2", "xmm3",
8883 "xmm4", "xmm5", "xmm6", "xmm7",
8884 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 8885 "mm4", "mm5", "mm6", "mm7",
8886 "fcw", "fsw", "mxcsr",
8887 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8888 "tr", "ldtr"
54cfded0 8889 };
089dfecd 8890 static const char *const regnames_64[] =
54cfded0 8891 {
089dfecd
JB		 8892 "rax", "rdx", "rcx", "rbx",
8893 "rsi", "rdi", "rbp", "rsp",
8894 "r8", "r9", "r10", "r11",
54cfded0 8895 "r12", "r13", "r14", "r15",
089dfecd
JB		 8896 "rip",
8897 "xmm0", "xmm1", "xmm2", "xmm3",
8898 "xmm4", "xmm5", "xmm6", "xmm7",
8899 "xmm8", "xmm9", "xmm10", "xmm11",
8900 "xmm12", "xmm13", "xmm14", "xmm15",
8901 "st0", "st1", "st2", "st3",
8902 "st4", "st5", "st6", "st7",
8903 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 8904 "mm4", "mm5", "mm6", "mm7",
8905 "rflags",
8906 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8907 "fs.base", "gs.base", NULL, NULL,
8908 "tr", "ldtr",
8909 "mxcsr", "fcw", "fsw"
54cfded0 8910 };
089dfecd 8911 const char *const *regnames;
54cfded0
AM		 8912
8913 if (flag_code == CODE_64BIT)
8914 {
8915 regnames = regnames_64;
0cea6190 8916 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 8917 }
8918 else
8919 {
8920 regnames = regnames_32;
0cea6190 8921 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 8922 }
8923
8924 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 8925 if (regnames[regnum] != NULL
8926 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 8927 return regnum;
8928
54cfded0
AM		 8929 return -1;
8930}
8931
8932void
8933tc_x86_frame_initial_instructions (void)
8934{
a4447b93
RH		 8935 static unsigned int sp_regno;
8936
8937 if (!sp_regno)
8938 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
8939 ? "rsp" : "esp");
8940
8941 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
8942 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8943}
d2b2c203
DJ		 8944
8945int
8946i386_elf_section_type (const char *str, size_t len)
8947{
8948 if (flag_code == CODE_64BIT
8949 && len == sizeof ("unwind") - 1
8950 && strncmp (str, "unwind", 6) == 0)
8951 return SHT_X86_64_UNWIND;
8952
8953 return -1;
8954}
bb41ade5
AM		 8955
8956#ifdef TE_PE
8957void
8958tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8959{
8960 expressionS expr;
8961
8962 expr.X_op = O_secrel;
8963 expr.X_add_symbol = symbol;
8964 expr.X_add_number = 0;
8965 emit_expr (&expr, size);
8966}
8967#endif
3b22753a
L		 8968
8969#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8970/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8971
8972int
8973x86_64_section_letter (int letter, char **ptr_msg)
8974{
8975 if (flag_code == CODE_64BIT)
8976 {
8977 if (letter == 'l')
8978 return SHF_X86_64_LARGE;
8979
8980 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 8981 }
3b22753a 8982 else
64e74474 8983 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 8984 return -1;
8985}
8986
8987int
8988x86_64_section_word (char *str, size_t len)
8989{
8620418b 8990 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 8991 return SHF_X86_64_LARGE;
8992
8993 return -1;
8994}
8995
8996static void
8997handle_large_common (int small ATTRIBUTE_UNUSED)
8998{
8999 if (flag_code != CODE_64BIT)
9000 {
9001 s_comm_internal (0, elf_common_parse);
9002 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9003 }
9004 else
9005 {
9006 static segT lbss_section;
9007 asection *saved_com_section_ptr = elf_com_section_ptr;
9008 asection *saved_bss_section = bss_section;
9009
9010 if (lbss_section == NULL)
9011 {
9012 flagword applicable;
9013 segT seg = now_seg;
9014 subsegT subseg = now_subseg;
9015
9016 /* The .lbss section is for local .largecomm symbols. */
9017 lbss_section = subseg_new (".lbss", 0);
9018 applicable = bfd_applicable_section_flags (stdoutput);
9019 bfd_set_section_flags (stdoutput, lbss_section,
9020 applicable & SEC_ALLOC);
9021 seg_info (lbss_section)->bss = 1;
9022
9023 subseg_set (seg, subseg);
9024 }
9025
9026 elf_com_section_ptr = &_bfd_elf_large_com_section;
9027 bss_section = lbss_section;
9028
9029 s_comm_internal (0, elf_common_parse);
9030
9031 elf_com_section_ptr = saved_com_section_ptr;
9032 bss_section = saved_bss_section;
9033 }
9034}
9035#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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