Commit | Line | Data |
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252b5132 | 1 | /* i386.c -- Assemble code for the Intel 80386 |
4c63da97 | 2 | Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000 |
252b5132 RH |
3 | Free Software Foundation. |
4 | ||
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to the Free | |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
21 | ||
22 | /* | |
23 | Intel 80386 machine specific gas. | |
24 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
25 | Bugs & suggestions are completely welcome. This is free software. | |
26 | Please help us make it better. | |
27 | */ | |
28 | ||
29 | #include <ctype.h> | |
30 | ||
31 | #include "as.h" | |
32 | #include "subsegs.h" | |
33 | #include "opcode/i386.h" | |
34 | ||
252b5132 RH |
35 | #ifndef REGISTER_WARNINGS |
36 | #define REGISTER_WARNINGS 1 | |
37 | #endif | |
38 | ||
c3332e24 | 39 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 40 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
41 | #endif |
42 | ||
252b5132 RH |
43 | #ifndef SCALE1_WHEN_NO_INDEX |
44 | /* Specifying a scale factor besides 1 when there is no index is | |
45 | futile. eg. `mov (%ebx,2),%al' does exactly the same as | |
46 | `mov (%ebx),%al'. To slavishly follow what the programmer | |
47 | specified, set SCALE1_WHEN_NO_INDEX to 0. */ | |
48 | #define SCALE1_WHEN_NO_INDEX 1 | |
49 | #endif | |
50 | ||
51 | #define true 1 | |
52 | #define false 0 | |
53 | ||
54 | static unsigned int mode_from_disp_size PARAMS ((unsigned int)); | |
847f7ad4 AM |
55 | static int fits_in_signed_byte PARAMS ((offsetT)); |
56 | static int fits_in_unsigned_byte PARAMS ((offsetT)); | |
57 | static int fits_in_unsigned_word PARAMS ((offsetT)); | |
58 | static int fits_in_signed_word PARAMS ((offsetT)); | |
59 | static int smallest_imm_type PARAMS ((offsetT)); | |
60 | static offsetT offset_in_range PARAMS ((offsetT, int)); | |
252b5132 RH |
61 | static int add_prefix PARAMS ((unsigned int)); |
62 | static void set_16bit_code_flag PARAMS ((int)); | |
eecb386c | 63 | static void set_16bit_gcc_code_flag PARAMS((int)); |
252b5132 | 64 | static void set_intel_syntax PARAMS ((int)); |
e413e4e9 | 65 | static void set_cpu_arch PARAMS ((int)); |
252b5132 RH |
66 | |
67 | #ifdef BFD_ASSEMBLER | |
68 | static bfd_reloc_code_real_type reloc | |
69 | PARAMS ((int, int, bfd_reloc_code_real_type)); | |
70 | #endif | |
71 | ||
72 | /* 'md_assemble ()' gathers together information and puts it into a | |
73 | i386_insn. */ | |
74 | ||
520dc8e8 AM |
75 | union i386_op |
76 | { | |
77 | expressionS *disps; | |
78 | expressionS *imms; | |
79 | const reg_entry *regs; | |
80 | }; | |
81 | ||
252b5132 RH |
82 | struct _i386_insn |
83 | { | |
84 | /* TM holds the template for the insn were currently assembling. */ | |
85 | template tm; | |
86 | ||
87 | /* SUFFIX holds the instruction mnemonic suffix if given. | |
88 | (e.g. 'l' for 'movl') */ | |
89 | char suffix; | |
90 | ||
252b5132 RH |
91 | /* OPERANDS gives the number of given operands. */ |
92 | unsigned int operands; | |
93 | ||
94 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
95 | of given register, displacement, memory operands and immediate | |
96 | operands. */ | |
97 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; | |
98 | ||
99 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 100 | use OP[i] for the corresponding operand. */ |
252b5132 RH |
101 | unsigned int types[MAX_OPERANDS]; |
102 | ||
520dc8e8 AM |
103 | /* Displacement expression, immediate expression, or register for each |
104 | operand. */ | |
105 | union i386_op op[MAX_OPERANDS]; | |
252b5132 RH |
106 | |
107 | /* Relocation type for operand */ | |
108 | #ifdef BFD_ASSEMBLER | |
109 | enum bfd_reloc_code_real disp_reloc[MAX_OPERANDS]; | |
110 | #else | |
111 | int disp_reloc[MAX_OPERANDS]; | |
112 | #endif | |
113 | ||
252b5132 RH |
114 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
115 | the base index byte below. */ | |
116 | const reg_entry *base_reg; | |
117 | const reg_entry *index_reg; | |
118 | unsigned int log2_scale_factor; | |
119 | ||
120 | /* SEG gives the seg_entries of this insn. They are zero unless | |
121 | explicit segment overrides are given. */ | |
122 | const seg_entry *seg[2]; /* segments for memory operands (if given) */ | |
123 | ||
124 | /* PREFIX holds all the given prefix opcodes (usually null). | |
125 | PREFIXES is the number of prefix opcodes. */ | |
126 | unsigned int prefixes; | |
127 | unsigned char prefix[MAX_PREFIXES]; | |
128 | ||
129 | /* RM and SIB are the modrm byte and the sib byte where the | |
130 | addressing modes of this insn are encoded. */ | |
131 | ||
132 | modrm_byte rm; | |
133 | sib_byte sib; | |
134 | }; | |
135 | ||
136 | typedef struct _i386_insn i386_insn; | |
137 | ||
138 | /* List of chars besides those in app.c:symbol_chars that can start an | |
139 | operand. Used to prevent the scrubber eating vital white-space. */ | |
140 | #ifdef LEX_AT | |
141 | const char extra_symbol_chars[] = "*%-(@"; | |
142 | #else | |
143 | const char extra_symbol_chars[] = "*%-("; | |
144 | #endif | |
145 | ||
146 | /* This array holds the chars that always start a comment. If the | |
147 | pre-processor is disabled, these aren't very useful */ | |
60bcf0fa | 148 | #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD)) |
252b5132 RH |
149 | /* Putting '/' here makes it impossible to use the divide operator. |
150 | However, we need it for compatibility with SVR4 systems. */ | |
151 | const char comment_chars[] = "#/"; | |
152 | #define PREFIX_SEPARATOR '\\' | |
153 | #else | |
154 | const char comment_chars[] = "#"; | |
155 | #define PREFIX_SEPARATOR '/' | |
156 | #endif | |
157 | ||
158 | /* This array holds the chars that only start a comment at the beginning of | |
159 | a line. If the line seems to have the form '# 123 filename' | |
160 | .line and .file directives will appear in the pre-processed output */ | |
161 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
162 | first line of the input file. This is because the compiler outputs | |
163 | #NO_APP at the beginning of its output. */ | |
164 | /* Also note that comments started like this one will always work if | |
165 | '/' isn't otherwise defined. */ | |
60bcf0fa | 166 | #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD)) |
252b5132 RH |
167 | const char line_comment_chars[] = ""; |
168 | #else | |
169 | const char line_comment_chars[] = "/"; | |
170 | #endif | |
171 | ||
63a0b638 | 172 | const char line_separator_chars[] = ";"; |
252b5132 RH |
173 | |
174 | /* Chars that can be used to separate mant from exp in floating point nums */ | |
175 | const char EXP_CHARS[] = "eE"; | |
176 | ||
177 | /* Chars that mean this number is a floating point constant */ | |
178 | /* As in 0f12.456 */ | |
179 | /* or 0d1.2345e12 */ | |
180 | const char FLT_CHARS[] = "fFdDxX"; | |
181 | ||
182 | /* tables for lexical analysis */ | |
183 | static char mnemonic_chars[256]; | |
184 | static char register_chars[256]; | |
185 | static char operand_chars[256]; | |
186 | static char identifier_chars[256]; | |
187 | static char digit_chars[256]; | |
188 | ||
189 | /* lexical macros */ | |
190 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) | |
191 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
192 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
193 | #define is_space_char(x) ((x) == ' ') | |
194 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
195 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
196 | ||
197 | /* put here all non-digit non-letter charcters that may occur in an operand */ | |
198 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; | |
199 | ||
200 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
201 | effect this we maintain a stack of saved characters that we've smashed | |
202 | with '\0's (indicating end of strings for various sub-fields of the | |
203 | assembler instruction). */ | |
204 | static char save_stack[32]; | |
205 | static char *save_stack_p; /* stack pointer */ | |
206 | #define END_STRING_AND_SAVE(s) \ | |
207 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
208 | #define RESTORE_END_STRING(s) \ | |
209 | do { *(s) = *--save_stack_p; } while (0) | |
210 | ||
211 | /* The instruction we're assembling. */ | |
212 | static i386_insn i; | |
213 | ||
214 | /* Possible templates for current insn. */ | |
215 | static const templates *current_templates; | |
216 | ||
217 | /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */ | |
218 | static expressionS disp_expressions[2], im_expressions[2]; | |
219 | ||
e413e4e9 | 220 | static int this_operand; /* Current operand we are working on. */ |
252b5132 | 221 | |
e413e4e9 AM |
222 | static int flag_16bit_code; /* 1 if we're writing 16-bit code, |
223 | 0 if 32-bit. */ | |
252b5132 | 224 | |
e413e4e9 | 225 | static int intel_syntax = 0; /* 1 for intel syntax, 0 if att syntax. */ |
252b5132 | 226 | |
e413e4e9 | 227 | static int allow_naked_reg = 0; /* 1 if register prefix % not required */ |
252b5132 | 228 | |
eecb386c AM |
229 | static char stackop_size = '\0'; /* Used in 16 bit gcc mode to add an l |
230 | suffix to call, ret, enter, leave, push, | |
add0c677 AM |
231 | and pop instructions so that gcc has the |
232 | same stack frame as in 32 bit mode. */ | |
eecb386c | 233 | |
a38cf1db AM |
234 | static int quiet_warnings = 0; /* Non-zero to quieten some warnings. */ |
235 | ||
236 | static const char *cpu_arch_name = NULL; /* cpu name */ | |
237 | ||
238 | static unsigned int cpu_arch_flags = 0; /* cpu feature flags */ | |
239 | ||
252b5132 RH |
240 | /* Interface to relax_segment. |
241 | There are 2 relax states for 386 jump insns: one for conditional & | |
a217f122 AM |
242 | one for unconditional jumps. This is because these two types of |
243 | jumps add different sizes to frags when we're figuring out what | |
252b5132 RH |
244 | sort of jump to choose to reach a given label. */ |
245 | ||
246 | /* types */ | |
247 | #define COND_JUMP 1 /* conditional jump */ | |
248 | #define UNCOND_JUMP 2 /* unconditional jump */ | |
249 | /* sizes */ | |
250 | #define CODE16 1 | |
251 | #define SMALL 0 | |
252 | #define SMALL16 (SMALL|CODE16) | |
253 | #define BIG 2 | |
254 | #define BIG16 (BIG|CODE16) | |
255 | ||
256 | #ifndef INLINE | |
257 | #ifdef __GNUC__ | |
258 | #define INLINE __inline__ | |
259 | #else | |
260 | #define INLINE | |
261 | #endif | |
262 | #endif | |
263 | ||
264 | #define ENCODE_RELAX_STATE(type,size) \ | |
265 | ((relax_substateT)((type<<2) | (size))) | |
266 | #define SIZE_FROM_RELAX_STATE(s) \ | |
267 | ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) ) | |
268 | ||
269 | /* This table is used by relax_frag to promote short jumps to long | |
270 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
271 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
272 | don't allow a short jump in a 32 bit code segment to be promoted to | |
273 | a 16 bit offset jump because it's slower (requires data size | |
274 | prefix), and doesn't work, unless the destination is in the bottom | |
275 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
276 | ||
277 | const relax_typeS md_relax_table[] = | |
278 | { | |
24eab124 AM |
279 | /* The fields are: |
280 | 1) most positive reach of this state, | |
281 | 2) most negative reach of this state, | |
282 | 3) how many bytes this mode will add to the size of the current frag | |
283 | 4) which index into the table to try if we can't fit into this one. | |
284 | */ | |
252b5132 RH |
285 | {1, 1, 0, 0}, |
286 | {1, 1, 0, 0}, | |
287 | {1, 1, 0, 0}, | |
288 | {1, 1, 0, 0}, | |
289 | ||
290 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
291 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
292 | /* dword conditionals adds 4 bytes to frag: | |
293 | 1 extra opcode byte, 3 extra displacement bytes. */ | |
294 | {0, 0, 4, 0}, | |
295 | /* word conditionals add 2 bytes to frag: | |
296 | 1 extra opcode byte, 1 extra displacement byte. */ | |
297 | {0, 0, 2, 0}, | |
298 | ||
299 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, | |
300 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
301 | /* dword jmp adds 3 bytes to frag: | |
302 | 0 extra opcode bytes, 3 extra displacement bytes. */ | |
303 | {0, 0, 3, 0}, | |
304 | /* word jmp adds 1 byte to frag: | |
305 | 0 extra opcode bytes, 1 extra displacement byte. */ | |
306 | {0, 0, 1, 0} | |
307 | ||
308 | }; | |
309 | ||
e413e4e9 AM |
310 | static const arch_entry cpu_arch[] = { |
311 | {"i8086", Cpu086 }, | |
312 | {"i186", Cpu086|Cpu186 }, | |
313 | {"i286", Cpu086|Cpu186|Cpu286 }, | |
314 | {"i386", Cpu086|Cpu186|Cpu286|Cpu386 }, | |
315 | {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 }, | |
316 | {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX }, | |
317 | {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE }, | |
318 | {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX }, | |
319 | {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE }, | |
320 | {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX|Cpu3dnow }, | |
321 | {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|Cpu3dnow }, | |
322 | {NULL, 0 } | |
323 | }; | |
324 | ||
252b5132 RH |
325 | |
326 | void | |
327 | i386_align_code (fragP, count) | |
328 | fragS *fragP; | |
329 | int count; | |
330 | { | |
331 | /* Various efficient no-op patterns for aligning code labels. */ | |
332 | /* Note: Don't try to assemble the instructions in the comments. */ | |
333 | /* 0L and 0w are not legal */ | |
334 | static const char f32_1[] = | |
335 | {0x90}; /* nop */ | |
336 | static const char f32_2[] = | |
337 | {0x89,0xf6}; /* movl %esi,%esi */ | |
338 | static const char f32_3[] = | |
339 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
340 | static const char f32_4[] = | |
341 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
342 | static const char f32_5[] = | |
343 | {0x90, /* nop */ | |
344 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
345 | static const char f32_6[] = | |
346 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
347 | static const char f32_7[] = | |
348 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
349 | static const char f32_8[] = | |
350 | {0x90, /* nop */ | |
351 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
352 | static const char f32_9[] = | |
353 | {0x89,0xf6, /* movl %esi,%esi */ | |
354 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
355 | static const char f32_10[] = | |
356 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ | |
357 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
358 | static const char f32_11[] = | |
359 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ | |
360 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
361 | static const char f32_12[] = | |
362 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
363 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
364 | static const char f32_13[] = | |
365 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
366 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
367 | static const char f32_14[] = | |
368 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ | |
369 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
370 | static const char f32_15[] = | |
371 | {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */ | |
372 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
c3332e24 AM |
373 | static const char f16_3[] = |
374 | {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ | |
252b5132 RH |
375 | static const char f16_4[] = |
376 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
377 | static const char f16_5[] = | |
378 | {0x90, /* nop */ | |
379 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
380 | static const char f16_6[] = | |
381 | {0x89,0xf6, /* mov %si,%si */ | |
382 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
383 | static const char f16_7[] = | |
384 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ | |
385 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
386 | static const char f16_8[] = | |
387 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ | |
388 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
389 | static const char *const f32_patt[] = { | |
390 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, | |
391 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15 | |
392 | }; | |
393 | static const char *const f16_patt[] = { | |
c3332e24 | 394 | f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8, |
252b5132 RH |
395 | f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15 |
396 | }; | |
397 | ||
398 | if (count > 0 && count <= 15) | |
399 | { | |
400 | if (flag_16bit_code) | |
401 | { | |
402 | memcpy(fragP->fr_literal + fragP->fr_fix, | |
403 | f16_patt[count - 1], count); | |
404 | if (count > 8) /* adjust jump offset */ | |
405 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
406 | } | |
407 | else | |
408 | memcpy(fragP->fr_literal + fragP->fr_fix, | |
409 | f32_patt[count - 1], count); | |
410 | fragP->fr_var = count; | |
411 | } | |
412 | } | |
413 | ||
414 | static char *output_invalid PARAMS ((int c)); | |
415 | static int i386_operand PARAMS ((char *operand_string)); | |
416 | static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float)); | |
417 | static const reg_entry *parse_register PARAMS ((char *reg_string, | |
418 | char **end_op)); | |
419 | ||
420 | #ifndef I386COFF | |
421 | static void s_bss PARAMS ((int)); | |
422 | #endif | |
423 | ||
424 | symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ | |
425 | ||
426 | static INLINE unsigned int | |
427 | mode_from_disp_size (t) | |
428 | unsigned int t; | |
429 | { | |
430 | return (t & Disp8) ? 1 : (t & (Disp16|Disp32)) ? 2 : 0; | |
431 | } | |
432 | ||
433 | static INLINE int | |
434 | fits_in_signed_byte (num) | |
847f7ad4 | 435 | offsetT num; |
252b5132 RH |
436 | { |
437 | return (num >= -128) && (num <= 127); | |
438 | } /* fits_in_signed_byte() */ | |
439 | ||
440 | static INLINE int | |
441 | fits_in_unsigned_byte (num) | |
847f7ad4 | 442 | offsetT num; |
252b5132 RH |
443 | { |
444 | return (num & 0xff) == num; | |
445 | } /* fits_in_unsigned_byte() */ | |
446 | ||
447 | static INLINE int | |
448 | fits_in_unsigned_word (num) | |
847f7ad4 | 449 | offsetT num; |
252b5132 RH |
450 | { |
451 | return (num & 0xffff) == num; | |
452 | } /* fits_in_unsigned_word() */ | |
453 | ||
454 | static INLINE int | |
455 | fits_in_signed_word (num) | |
847f7ad4 | 456 | offsetT num; |
252b5132 RH |
457 | { |
458 | return (-32768 <= num) && (num <= 32767); | |
459 | } /* fits_in_signed_word() */ | |
460 | ||
461 | static int | |
462 | smallest_imm_type (num) | |
847f7ad4 | 463 | offsetT num; |
252b5132 | 464 | { |
e413e4e9 AM |
465 | if (cpu_arch_flags != 0 |
466 | && cpu_arch_flags != (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486)) | |
467 | { | |
468 | /* This code is disabled on the 486 because all the Imm1 forms | |
469 | in the opcode table are slower on the i486. They're the | |
470 | versions with the implicitly specified single-position | |
471 | displacement, which has another syntax if you really want to | |
472 | use that form. */ | |
473 | if (num == 1) | |
474 | return Imm1 | Imm8 | Imm8S | Imm16 | Imm32; | |
475 | } | |
252b5132 RH |
476 | return (fits_in_signed_byte (num) |
477 | ? (Imm8S | Imm8 | Imm16 | Imm32) | |
478 | : fits_in_unsigned_byte (num) | |
479 | ? (Imm8 | Imm16 | Imm32) | |
480 | : (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
481 | ? (Imm16 | Imm32) | |
482 | : (Imm32)); | |
483 | } /* smallest_imm_type() */ | |
484 | ||
847f7ad4 AM |
485 | static offsetT |
486 | offset_in_range (val, size) | |
487 | offsetT val; | |
488 | int size; | |
489 | { | |
508866be | 490 | addressT mask; |
ba2adb93 | 491 | |
847f7ad4 AM |
492 | switch (size) |
493 | { | |
508866be L |
494 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
495 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 496 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
847f7ad4 AM |
497 | default: abort(); |
498 | } | |
499 | ||
ba2adb93 | 500 | /* If BFD64, sign extend val. */ |
3b0ec529 | 501 | if ((val & ~ (((addressT) 2 << 31) - 1)) == 0) |
508866be | 502 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); |
ba2adb93 | 503 | |
847f7ad4 AM |
504 | if ((val & ~ mask) != 0 && (val & ~ mask) != ~ mask) |
505 | { | |
506 | char buf1[40], buf2[40]; | |
507 | ||
508 | sprint_value (buf1, val); | |
509 | sprint_value (buf2, val & mask); | |
510 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
511 | } | |
512 | return val & mask; | |
513 | } | |
514 | ||
252b5132 RH |
515 | /* Returns 0 if attempting to add a prefix where one from the same |
516 | class already exists, 1 if non rep/repne added, 2 if rep/repne | |
517 | added. */ | |
518 | static int | |
519 | add_prefix (prefix) | |
520 | unsigned int prefix; | |
521 | { | |
522 | int ret = 1; | |
523 | int q; | |
524 | ||
525 | switch (prefix) | |
526 | { | |
527 | default: | |
528 | abort (); | |
529 | ||
530 | case CS_PREFIX_OPCODE: | |
531 | case DS_PREFIX_OPCODE: | |
532 | case ES_PREFIX_OPCODE: | |
533 | case FS_PREFIX_OPCODE: | |
534 | case GS_PREFIX_OPCODE: | |
535 | case SS_PREFIX_OPCODE: | |
536 | q = SEG_PREFIX; | |
537 | break; | |
538 | ||
539 | case REPNE_PREFIX_OPCODE: | |
540 | case REPE_PREFIX_OPCODE: | |
541 | ret = 2; | |
542 | /* fall thru */ | |
543 | case LOCK_PREFIX_OPCODE: | |
544 | q = LOCKREP_PREFIX; | |
545 | break; | |
546 | ||
547 | case FWAIT_OPCODE: | |
548 | q = WAIT_PREFIX; | |
549 | break; | |
550 | ||
551 | case ADDR_PREFIX_OPCODE: | |
552 | q = ADDR_PREFIX; | |
553 | break; | |
554 | ||
555 | case DATA_PREFIX_OPCODE: | |
556 | q = DATA_PREFIX; | |
557 | break; | |
558 | } | |
559 | ||
560 | if (i.prefix[q]) | |
561 | { | |
562 | as_bad (_("same type of prefix used twice")); | |
563 | return 0; | |
564 | } | |
565 | ||
566 | i.prefixes += 1; | |
567 | i.prefix[q] = prefix; | |
568 | return ret; | |
569 | } | |
570 | ||
571 | static void | |
572 | set_16bit_code_flag (new_16bit_code_flag) | |
eecb386c AM |
573 | int new_16bit_code_flag; |
574 | { | |
575 | flag_16bit_code = new_16bit_code_flag; | |
576 | stackop_size = '\0'; | |
577 | } | |
578 | ||
579 | static void | |
580 | set_16bit_gcc_code_flag (new_16bit_code_flag) | |
581 | int new_16bit_code_flag; | |
252b5132 RH |
582 | { |
583 | flag_16bit_code = new_16bit_code_flag; | |
eecb386c | 584 | stackop_size = new_16bit_code_flag ? 'l' : '\0'; |
252b5132 RH |
585 | } |
586 | ||
587 | static void | |
588 | set_intel_syntax (syntax_flag) | |
eecb386c | 589 | int syntax_flag; |
252b5132 RH |
590 | { |
591 | /* Find out if register prefixing is specified. */ | |
592 | int ask_naked_reg = 0; | |
593 | ||
594 | SKIP_WHITESPACE (); | |
595 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
596 | { | |
597 | char *string = input_line_pointer; | |
598 | int e = get_symbol_end (); | |
599 | ||
600 | if (strcmp(string, "prefix") == 0) | |
601 | ask_naked_reg = 1; | |
602 | else if (strcmp(string, "noprefix") == 0) | |
603 | ask_naked_reg = -1; | |
604 | else | |
d0b47220 | 605 | as_bad (_("bad argument to syntax directive.")); |
252b5132 RH |
606 | *input_line_pointer = e; |
607 | } | |
608 | demand_empty_rest_of_line (); | |
c3332e24 | 609 | |
252b5132 RH |
610 | intel_syntax = syntax_flag; |
611 | ||
612 | if (ask_naked_reg == 0) | |
613 | { | |
614 | #ifdef BFD_ASSEMBLER | |
615 | allow_naked_reg = (intel_syntax | |
24eab124 | 616 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); |
252b5132 RH |
617 | #else |
618 | allow_naked_reg = 0; /* conservative default */ | |
619 | #endif | |
620 | } | |
621 | else | |
622 | allow_naked_reg = (ask_naked_reg < 0); | |
623 | } | |
624 | ||
e413e4e9 AM |
625 | static void |
626 | set_cpu_arch (dummy) | |
627 | int dummy ATTRIBUTE_UNUSED; | |
628 | { | |
629 | SKIP_WHITESPACE(); | |
630 | ||
631 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
632 | { | |
633 | char *string = input_line_pointer; | |
634 | int e = get_symbol_end (); | |
635 | int i; | |
636 | ||
637 | for (i = 0; cpu_arch[i].name; i++) | |
638 | { | |
639 | if (strcmp (string, cpu_arch[i].name) == 0) | |
640 | { | |
641 | cpu_arch_name = cpu_arch[i].name; | |
642 | cpu_arch_flags = cpu_arch[i].flags; | |
643 | break; | |
644 | } | |
645 | } | |
646 | if (!cpu_arch[i].name) | |
647 | as_bad (_("no such architecture: `%s'"), string); | |
648 | ||
649 | *input_line_pointer = e; | |
650 | } | |
651 | else | |
652 | as_bad (_("missing cpu architecture")); | |
653 | ||
654 | demand_empty_rest_of_line (); | |
655 | } | |
656 | ||
252b5132 RH |
657 | const pseudo_typeS md_pseudo_table[] = |
658 | { | |
252b5132 RH |
659 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) |
660 | {"align", s_align_bytes, 0}, | |
661 | #else | |
662 | {"align", s_align_ptwo, 0}, | |
e413e4e9 AM |
663 | #endif |
664 | {"arch", set_cpu_arch, 0}, | |
665 | #ifndef I386COFF | |
666 | {"bss", s_bss, 0}, | |
252b5132 RH |
667 | #endif |
668 | {"ffloat", float_cons, 'f'}, | |
669 | {"dfloat", float_cons, 'd'}, | |
670 | {"tfloat", float_cons, 'x'}, | |
671 | {"value", cons, 2}, | |
672 | {"noopt", s_ignore, 0}, | |
673 | {"optim", s_ignore, 0}, | |
eecb386c | 674 | {"code16gcc", set_16bit_gcc_code_flag, 1}, |
252b5132 RH |
675 | {"code16", set_16bit_code_flag, 1}, |
676 | {"code32", set_16bit_code_flag, 0}, | |
677 | {"intel_syntax", set_intel_syntax, 1}, | |
678 | {"att_syntax", set_intel_syntax, 0}, | |
679 | {0, 0, 0} | |
680 | }; | |
681 | ||
682 | /* for interface with expression () */ | |
683 | extern char *input_line_pointer; | |
684 | ||
685 | /* hash table for instruction mnemonic lookup */ | |
686 | static struct hash_control *op_hash; | |
687 | /* hash table for register lookup */ | |
688 | static struct hash_control *reg_hash; | |
689 | \f | |
690 | ||
691 | void | |
692 | md_begin () | |
693 | { | |
694 | const char *hash_err; | |
695 | ||
696 | /* initialize op_hash hash table */ | |
697 | op_hash = hash_new (); | |
698 | ||
699 | { | |
700 | register const template *optab; | |
701 | register templates *core_optab; | |
702 | ||
703 | optab = i386_optab; /* setup for loop */ | |
704 | core_optab = (templates *) xmalloc (sizeof (templates)); | |
705 | core_optab->start = optab; | |
706 | ||
707 | while (1) | |
708 | { | |
709 | ++optab; | |
710 | if (optab->name == NULL | |
711 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
712 | { | |
713 | /* different name --> ship out current template list; | |
714 | add to hash table; & begin anew */ | |
715 | core_optab->end = optab; | |
716 | hash_err = hash_insert (op_hash, | |
717 | (optab - 1)->name, | |
718 | (PTR) core_optab); | |
719 | if (hash_err) | |
720 | { | |
721 | hash_error: | |
722 | as_fatal (_("Internal Error: Can't hash %s: %s"), | |
723 | (optab - 1)->name, | |
724 | hash_err); | |
725 | } | |
726 | if (optab->name == NULL) | |
727 | break; | |
728 | core_optab = (templates *) xmalloc (sizeof (templates)); | |
729 | core_optab->start = optab; | |
730 | } | |
731 | } | |
732 | } | |
733 | ||
734 | /* initialize reg_hash hash table */ | |
735 | reg_hash = hash_new (); | |
736 | { | |
737 | register const reg_entry *regtab; | |
738 | ||
739 | for (regtab = i386_regtab; | |
740 | regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]); | |
741 | regtab++) | |
742 | { | |
743 | hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab); | |
744 | if (hash_err) | |
745 | goto hash_error; | |
746 | } | |
747 | } | |
748 | ||
749 | /* fill in lexical tables: mnemonic_chars, operand_chars. */ | |
750 | { | |
751 | register int c; | |
752 | register char *p; | |
753 | ||
754 | for (c = 0; c < 256; c++) | |
755 | { | |
756 | if (isdigit (c)) | |
757 | { | |
758 | digit_chars[c] = c; | |
759 | mnemonic_chars[c] = c; | |
760 | register_chars[c] = c; | |
761 | operand_chars[c] = c; | |
762 | } | |
763 | else if (islower (c)) | |
764 | { | |
765 | mnemonic_chars[c] = c; | |
766 | register_chars[c] = c; | |
767 | operand_chars[c] = c; | |
768 | } | |
769 | else if (isupper (c)) | |
770 | { | |
771 | mnemonic_chars[c] = tolower (c); | |
772 | register_chars[c] = mnemonic_chars[c]; | |
773 | operand_chars[c] = c; | |
774 | } | |
775 | ||
776 | if (isalpha (c) || isdigit (c)) | |
777 | identifier_chars[c] = c; | |
778 | else if (c >= 128) | |
779 | { | |
780 | identifier_chars[c] = c; | |
781 | operand_chars[c] = c; | |
782 | } | |
783 | } | |
784 | ||
785 | #ifdef LEX_AT | |
786 | identifier_chars['@'] = '@'; | |
787 | #endif | |
252b5132 RH |
788 | digit_chars['-'] = '-'; |
789 | identifier_chars['_'] = '_'; | |
790 | identifier_chars['.'] = '.'; | |
791 | ||
792 | for (p = operand_special_chars; *p != '\0'; p++) | |
793 | operand_chars[(unsigned char) *p] = *p; | |
794 | } | |
795 | ||
796 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
797 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
798 | { | |
799 | record_alignment (text_section, 2); | |
800 | record_alignment (data_section, 2); | |
801 | record_alignment (bss_section, 2); | |
802 | } | |
803 | #endif | |
804 | } | |
805 | ||
806 | void | |
807 | i386_print_statistics (file) | |
808 | FILE *file; | |
809 | { | |
810 | hash_print_statistics (file, "i386 opcode", op_hash); | |
811 | hash_print_statistics (file, "i386 register", reg_hash); | |
812 | } | |
813 | \f | |
814 | ||
815 | #ifdef DEBUG386 | |
816 | ||
817 | /* debugging routines for md_assemble */ | |
818 | static void pi PARAMS ((char *, i386_insn *)); | |
819 | static void pte PARAMS ((template *)); | |
820 | static void pt PARAMS ((unsigned int)); | |
821 | static void pe PARAMS ((expressionS *)); | |
822 | static void ps PARAMS ((symbolS *)); | |
823 | ||
824 | static void | |
825 | pi (line, x) | |
826 | char *line; | |
827 | i386_insn *x; | |
828 | { | |
829 | register template *p; | |
830 | int i; | |
831 | ||
832 | fprintf (stdout, "%s: template ", line); | |
833 | pte (&x->tm); | |
834 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x", | |
835 | x->rm.mode, x->rm.reg, x->rm.regmem); | |
836 | fprintf (stdout, " base %x index %x scale %x\n", | |
837 | x->bi.base, x->bi.index, x->bi.scale); | |
838 | for (i = 0; i < x->operands; i++) | |
839 | { | |
840 | fprintf (stdout, " #%d: ", i + 1); | |
841 | pt (x->types[i]); | |
842 | fprintf (stdout, "\n"); | |
843 | if (x->types[i] | |
3f4438ab | 844 | & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM)) |
520dc8e8 | 845 | fprintf (stdout, "%s\n", x->op[i].regs->reg_name); |
252b5132 | 846 | if (x->types[i] & Imm) |
520dc8e8 | 847 | pe (x->op[i].imms); |
252b5132 | 848 | if (x->types[i] & Disp) |
520dc8e8 | 849 | pe (x->op[i].disps); |
252b5132 RH |
850 | } |
851 | } | |
852 | ||
853 | static void | |
854 | pte (t) | |
855 | template *t; | |
856 | { | |
857 | int i; | |
858 | fprintf (stdout, " %d operands ", t->operands); | |
859 | fprintf (stdout, "opcode %x ", | |
860 | t->base_opcode); | |
861 | if (t->extension_opcode != None) | |
862 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
863 | if (t->opcode_modifier & D) | |
864 | fprintf (stdout, "D"); | |
865 | if (t->opcode_modifier & W) | |
866 | fprintf (stdout, "W"); | |
867 | fprintf (stdout, "\n"); | |
868 | for (i = 0; i < t->operands; i++) | |
869 | { | |
870 | fprintf (stdout, " #%d type ", i + 1); | |
871 | pt (t->operand_types[i]); | |
872 | fprintf (stdout, "\n"); | |
873 | } | |
874 | } | |
875 | ||
876 | static void | |
877 | pe (e) | |
878 | expressionS *e; | |
879 | { | |
24eab124 | 880 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
881 | fprintf (stdout, " add_number %ld (%lx)\n", |
882 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
883 | if (e->X_add_symbol) |
884 | { | |
885 | fprintf (stdout, " add_symbol "); | |
886 | ps (e->X_add_symbol); | |
887 | fprintf (stdout, "\n"); | |
888 | } | |
889 | if (e->X_op_symbol) | |
890 | { | |
891 | fprintf (stdout, " op_symbol "); | |
892 | ps (e->X_op_symbol); | |
893 | fprintf (stdout, "\n"); | |
894 | } | |
895 | } | |
896 | ||
897 | static void | |
898 | ps (s) | |
899 | symbolS *s; | |
900 | { | |
901 | fprintf (stdout, "%s type %s%s", | |
902 | S_GET_NAME (s), | |
903 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
904 | segment_name (S_GET_SEGMENT (s))); | |
905 | } | |
906 | ||
907 | struct type_name | |
908 | { | |
909 | unsigned int mask; | |
910 | char *tname; | |
911 | } | |
912 | ||
913 | type_names[] = | |
914 | { | |
915 | { Reg8, "r8" }, | |
916 | { Reg16, "r16" }, | |
917 | { Reg32, "r32" }, | |
918 | { Imm8, "i8" }, | |
919 | { Imm8S, "i8s" }, | |
920 | { Imm16, "i16" }, | |
921 | { Imm32, "i32" }, | |
922 | { Imm1, "i1" }, | |
923 | { BaseIndex, "BaseIndex" }, | |
924 | { Disp8, "d8" }, | |
925 | { Disp16, "d16" }, | |
926 | { Disp32, "d32" }, | |
927 | { InOutPortReg, "InOutPortReg" }, | |
928 | { ShiftCount, "ShiftCount" }, | |
929 | { Control, "control reg" }, | |
930 | { Test, "test reg" }, | |
931 | { Debug, "debug reg" }, | |
932 | { FloatReg, "FReg" }, | |
933 | { FloatAcc, "FAcc" }, | |
934 | { SReg2, "SReg2" }, | |
935 | { SReg3, "SReg3" }, | |
936 | { Acc, "Acc" }, | |
937 | { JumpAbsolute, "Jump Absolute" }, | |
938 | { RegMMX, "rMMX" }, | |
3f4438ab | 939 | { RegXMM, "rXMM" }, |
252b5132 RH |
940 | { EsSeg, "es" }, |
941 | { 0, "" } | |
942 | }; | |
943 | ||
944 | static void | |
945 | pt (t) | |
946 | unsigned int t; | |
947 | { | |
948 | register struct type_name *ty; | |
949 | ||
950 | if (t == Unknown) | |
951 | { | |
952 | fprintf (stdout, _("Unknown")); | |
953 | } | |
954 | else | |
955 | { | |
956 | for (ty = type_names; ty->mask; ty++) | |
957 | if (t & ty->mask) | |
958 | fprintf (stdout, "%s, ", ty->tname); | |
959 | } | |
960 | fflush (stdout); | |
961 | } | |
962 | ||
963 | #endif /* DEBUG386 */ | |
964 | \f | |
965 | int | |
966 | tc_i386_force_relocation (fixp) | |
967 | struct fix *fixp; | |
968 | { | |
969 | #ifdef BFD_ASSEMBLER | |
970 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
971 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
972 | return 1; | |
973 | return 0; | |
974 | #else | |
975 | /* For COFF */ | |
f6af82bd | 976 | return fixp->fx_r_type == 7; |
252b5132 RH |
977 | #endif |
978 | } | |
979 | ||
980 | #ifdef BFD_ASSEMBLER | |
981 | static bfd_reloc_code_real_type reloc | |
982 | PARAMS ((int, int, bfd_reloc_code_real_type)); | |
983 | ||
984 | static bfd_reloc_code_real_type | |
985 | reloc (size, pcrel, other) | |
986 | int size; | |
987 | int pcrel; | |
988 | bfd_reloc_code_real_type other; | |
989 | { | |
990 | if (other != NO_RELOC) return other; | |
991 | ||
992 | if (pcrel) | |
993 | { | |
994 | switch (size) | |
995 | { | |
996 | case 1: return BFD_RELOC_8_PCREL; | |
997 | case 2: return BFD_RELOC_16_PCREL; | |
998 | case 4: return BFD_RELOC_32_PCREL; | |
999 | } | |
d0b47220 | 1000 | as_bad (_("can not do %d byte pc-relative relocation"), size); |
252b5132 RH |
1001 | } |
1002 | else | |
1003 | { | |
1004 | switch (size) | |
1005 | { | |
1006 | case 1: return BFD_RELOC_8; | |
1007 | case 2: return BFD_RELOC_16; | |
1008 | case 4: return BFD_RELOC_32; | |
1009 | } | |
d0b47220 | 1010 | as_bad (_("can not do %d byte relocation"), size); |
252b5132 RH |
1011 | } |
1012 | ||
1013 | return BFD_RELOC_NONE; | |
1014 | } | |
1015 | ||
1016 | /* | |
1017 | * Here we decide which fixups can be adjusted to make them relative to | |
1018 | * the beginning of the section instead of the symbol. Basically we need | |
1019 | * to make sure that the dynamic relocations are done correctly, so in | |
1020 | * some cases we force the original symbol to be used. | |
1021 | */ | |
1022 | int | |
c0c949c7 | 1023 | tc_i386_fix_adjustable (fixP) |
60bcf0fa | 1024 | fixS * fixP; |
252b5132 | 1025 | { |
6d249963 | 1026 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
79d292aa ILT |
1027 | /* Prevent all adjustments to global symbols, or else dynamic |
1028 | linking will not work correctly. */ | |
b98ef147 AM |
1029 | if (S_IS_EXTERNAL (fixP->fx_addsy) |
1030 | || S_IS_WEAK (fixP->fx_addsy)) | |
252b5132 RH |
1031 | return 0; |
1032 | #endif | |
1033 | /* adjust_reloc_syms doesn't know about the GOT */ | |
1034 | if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF | |
1035 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 | |
1036 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
1037 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
1038 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1039 | return 0; | |
1040 | return 1; | |
1041 | } | |
1042 | #else | |
1043 | #define reloc(SIZE,PCREL,OTHER) 0 | |
1044 | #define BFD_RELOC_16 0 | |
1045 | #define BFD_RELOC_32 0 | |
1046 | #define BFD_RELOC_16_PCREL 0 | |
1047 | #define BFD_RELOC_32_PCREL 0 | |
1048 | #define BFD_RELOC_386_PLT32 0 | |
1049 | #define BFD_RELOC_386_GOT32 0 | |
1050 | #define BFD_RELOC_386_GOTOFF 0 | |
1051 | #endif | |
1052 | ||
b4cac588 AM |
1053 | static int |
1054 | intel_float_operand PARAMS ((char *mnemonic)); | |
1055 | ||
1056 | static int | |
252b5132 RH |
1057 | intel_float_operand (mnemonic) |
1058 | char *mnemonic; | |
1059 | { | |
1060 | if (mnemonic[0] == 'f' && mnemonic[1] =='i') | |
cc5ca5ce | 1061 | return 2; |
252b5132 RH |
1062 | |
1063 | if (mnemonic[0] == 'f') | |
1064 | return 1; | |
1065 | ||
1066 | return 0; | |
1067 | } | |
1068 | ||
1069 | /* This is the guts of the machine-dependent assembler. LINE points to a | |
1070 | machine dependent instruction. This function is supposed to emit | |
1071 | the frags/bytes it assembles to. */ | |
1072 | ||
1073 | void | |
1074 | md_assemble (line) | |
1075 | char *line; | |
1076 | { | |
1077 | /* Points to template once we've found it. */ | |
1078 | const template *t; | |
1079 | ||
1080 | /* Count the size of the instruction generated. */ | |
1081 | int insn_size = 0; | |
1082 | ||
1083 | int j; | |
1084 | ||
1085 | char mnemonic[MAX_MNEM_SIZE]; | |
1086 | ||
1087 | /* Initialize globals. */ | |
1088 | memset (&i, '\0', sizeof (i)); | |
1089 | for (j = 0; j < MAX_OPERANDS; j++) | |
1090 | i.disp_reloc[j] = NO_RELOC; | |
1091 | memset (disp_expressions, '\0', sizeof (disp_expressions)); | |
1092 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
1093 | save_stack_p = save_stack; /* reset stack pointer */ | |
1094 | ||
1095 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
1096 | We assume that the scrubber has arranged it so that line[0] is the valid | |
1097 | start of a (possibly prefixed) mnemonic. */ | |
1098 | { | |
1099 | char *l = line; | |
1100 | char *token_start = l; | |
1101 | char *mnem_p; | |
1102 | ||
1103 | /* Non-zero if we found a prefix only acceptable with string insns. */ | |
1104 | const char *expecting_string_instruction = NULL; | |
1105 | ||
1106 | while (1) | |
1107 | { | |
1108 | mnem_p = mnemonic; | |
1109 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
1110 | { | |
1111 | mnem_p++; | |
1112 | if (mnem_p >= mnemonic + sizeof (mnemonic)) | |
1113 | { | |
e413e4e9 | 1114 | as_bad (_("no such instruction: `%s'"), token_start); |
252b5132 RH |
1115 | return; |
1116 | } | |
1117 | l++; | |
1118 | } | |
1119 | if (!is_space_char (*l) | |
1120 | && *l != END_OF_INSN | |
1121 | && *l != PREFIX_SEPARATOR) | |
1122 | { | |
1123 | as_bad (_("invalid character %s in mnemonic"), | |
1124 | output_invalid (*l)); | |
1125 | return; | |
1126 | } | |
1127 | if (token_start == l) | |
1128 | { | |
1129 | if (*l == PREFIX_SEPARATOR) | |
1130 | as_bad (_("expecting prefix; got nothing")); | |
1131 | else | |
1132 | as_bad (_("expecting mnemonic; got nothing")); | |
1133 | return; | |
1134 | } | |
1135 | ||
1136 | /* Look up instruction (or prefix) via hash table. */ | |
1137 | current_templates = hash_find (op_hash, mnemonic); | |
1138 | ||
1139 | if (*l != END_OF_INSN | |
1140 | && (! is_space_char (*l) || l[1] != END_OF_INSN) | |
1141 | && current_templates | |
1142 | && (current_templates->start->opcode_modifier & IsPrefix)) | |
1143 | { | |
1144 | /* If we are in 16-bit mode, do not allow addr16 or data16. | |
1145 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
1146 | if ((current_templates->start->opcode_modifier & (Size16 | Size32)) | |
1147 | && (((current_templates->start->opcode_modifier & Size32) != 0) | |
1148 | ^ flag_16bit_code)) | |
1149 | { | |
1150 | as_bad (_("redundant %s prefix"), | |
1151 | current_templates->start->name); | |
1152 | return; | |
1153 | } | |
1154 | /* Add prefix, checking for repeated prefixes. */ | |
1155 | switch (add_prefix (current_templates->start->base_opcode)) | |
1156 | { | |
1157 | case 0: | |
1158 | return; | |
1159 | case 2: | |
1160 | expecting_string_instruction = | |
1161 | current_templates->start->name; | |
1162 | break; | |
1163 | } | |
1164 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
1165 | token_start = ++l; | |
1166 | } | |
1167 | else | |
1168 | break; | |
1169 | } | |
1170 | ||
1171 | if (!current_templates) | |
1172 | { | |
24eab124 | 1173 | /* See if we can get a match by trimming off a suffix. */ |
252b5132 RH |
1174 | switch (mnem_p[-1]) |
1175 | { | |
252b5132 RH |
1176 | case WORD_MNEM_SUFFIX: |
1177 | case BYTE_MNEM_SUFFIX: | |
1178 | case SHORT_MNEM_SUFFIX: | |
252b5132 | 1179 | case LONG_MNEM_SUFFIX: |
252b5132 RH |
1180 | i.suffix = mnem_p[-1]; |
1181 | mnem_p[-1] = '\0'; | |
1182 | current_templates = hash_find (op_hash, mnemonic); | |
24eab124 AM |
1183 | break; |
1184 | ||
1185 | /* Intel Syntax */ | |
add0c677 | 1186 | case DWORD_MNEM_SUFFIX: |
24eab124 AM |
1187 | if (intel_syntax) |
1188 | { | |
1189 | i.suffix = mnem_p[-1]; | |
1190 | mnem_p[-1] = '\0'; | |
1191 | current_templates = hash_find (op_hash, mnemonic); | |
1192 | break; | |
1193 | } | |
252b5132 RH |
1194 | } |
1195 | if (!current_templates) | |
1196 | { | |
e413e4e9 | 1197 | as_bad (_("no such instruction: `%s'"), token_start); |
252b5132 RH |
1198 | return; |
1199 | } | |
1200 | } | |
1201 | ||
e413e4e9 AM |
1202 | /* Check if instruction is supported on specified architecture. */ |
1203 | if (cpu_arch_flags != 0) | |
1204 | { | |
1205 | if (current_templates->start->cpu_flags & ~ cpu_arch_flags) | |
1206 | { | |
1207 | as_warn (_("`%s' is not supported on `%s'"), | |
1208 | current_templates->start->name, cpu_arch_name); | |
1209 | } | |
1210 | else if ((Cpu386 & ~ cpu_arch_flags) && !flag_16bit_code) | |
1211 | { | |
1212 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
1213 | } | |
1214 | } | |
1215 | ||
252b5132 RH |
1216 | /* check for rep/repne without a string instruction */ |
1217 | if (expecting_string_instruction | |
1218 | && !(current_templates->start->opcode_modifier & IsString)) | |
1219 | { | |
1220 | as_bad (_("expecting string instruction after `%s'"), | |
1221 | expecting_string_instruction); | |
1222 | return; | |
1223 | } | |
1224 | ||
1225 | /* There may be operands to parse. */ | |
1226 | if (*l != END_OF_INSN) | |
1227 | { | |
1228 | /* parse operands */ | |
1229 | ||
1230 | /* 1 if operand is pending after ','. */ | |
1231 | unsigned int expecting_operand = 0; | |
1232 | ||
1233 | /* Non-zero if operand parens not balanced. */ | |
1234 | unsigned int paren_not_balanced; | |
1235 | ||
1236 | do | |
1237 | { | |
1238 | /* skip optional white space before operand */ | |
1239 | if (is_space_char (*l)) | |
1240 | ++l; | |
1241 | if (!is_operand_char (*l) && *l != END_OF_INSN) | |
1242 | { | |
1243 | as_bad (_("invalid character %s before operand %d"), | |
1244 | output_invalid (*l), | |
1245 | i.operands + 1); | |
1246 | return; | |
1247 | } | |
1248 | token_start = l; /* after white space */ | |
1249 | paren_not_balanced = 0; | |
1250 | while (paren_not_balanced || *l != ',') | |
1251 | { | |
1252 | if (*l == END_OF_INSN) | |
1253 | { | |
1254 | if (paren_not_balanced) | |
1255 | { | |
24eab124 | 1256 | if (!intel_syntax) |
252b5132 RH |
1257 | as_bad (_("unbalanced parenthesis in operand %d."), |
1258 | i.operands + 1); | |
24eab124 | 1259 | else |
252b5132 RH |
1260 | as_bad (_("unbalanced brackets in operand %d."), |
1261 | i.operands + 1); | |
1262 | return; | |
1263 | } | |
1264 | else | |
1265 | break; /* we are done */ | |
1266 | } | |
1267 | else if (!is_operand_char (*l) && !is_space_char (*l)) | |
1268 | { | |
1269 | as_bad (_("invalid character %s in operand %d"), | |
1270 | output_invalid (*l), | |
1271 | i.operands + 1); | |
1272 | return; | |
1273 | } | |
24eab124 AM |
1274 | if (!intel_syntax) |
1275 | { | |
252b5132 RH |
1276 | if (*l == '(') |
1277 | ++paren_not_balanced; | |
1278 | if (*l == ')') | |
1279 | --paren_not_balanced; | |
24eab124 AM |
1280 | } |
1281 | else | |
1282 | { | |
252b5132 RH |
1283 | if (*l == '[') |
1284 | ++paren_not_balanced; | |
1285 | if (*l == ']') | |
1286 | --paren_not_balanced; | |
24eab124 | 1287 | } |
252b5132 RH |
1288 | l++; |
1289 | } | |
1290 | if (l != token_start) | |
1291 | { /* yes, we've read in another operand */ | |
1292 | unsigned int operand_ok; | |
1293 | this_operand = i.operands++; | |
1294 | if (i.operands > MAX_OPERANDS) | |
1295 | { | |
1296 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
1297 | MAX_OPERANDS); | |
1298 | return; | |
1299 | } | |
1300 | /* now parse operand adding info to 'i' as we go along */ | |
1301 | END_STRING_AND_SAVE (l); | |
1302 | ||
24eab124 AM |
1303 | if (intel_syntax) |
1304 | operand_ok = i386_intel_operand (token_start, intel_float_operand (mnemonic)); | |
1305 | else | |
1306 | operand_ok = i386_operand (token_start); | |
252b5132 RH |
1307 | |
1308 | RESTORE_END_STRING (l); /* restore old contents */ | |
1309 | if (!operand_ok) | |
1310 | return; | |
1311 | } | |
1312 | else | |
1313 | { | |
1314 | if (expecting_operand) | |
1315 | { | |
1316 | expecting_operand_after_comma: | |
1317 | as_bad (_("expecting operand after ','; got nothing")); | |
1318 | return; | |
1319 | } | |
1320 | if (*l == ',') | |
1321 | { | |
1322 | as_bad (_("expecting operand before ','; got nothing")); | |
1323 | return; | |
1324 | } | |
1325 | } | |
1326 | ||
1327 | /* now *l must be either ',' or END_OF_INSN */ | |
1328 | if (*l == ',') | |
1329 | { | |
1330 | if (*++l == END_OF_INSN) | |
1331 | { /* just skip it, if it's \n complain */ | |
1332 | goto expecting_operand_after_comma; | |
1333 | } | |
1334 | expecting_operand = 1; | |
1335 | } | |
1336 | } | |
1337 | while (*l != END_OF_INSN); /* until we get end of insn */ | |
1338 | } | |
1339 | } | |
1340 | ||
1341 | /* Now we've parsed the mnemonic into a set of templates, and have the | |
1342 | operands at hand. | |
1343 | ||
1344 | Next, we find a template that matches the given insn, | |
1345 | making sure the overlap of the given operands types is consistent | |
1346 | with the template operand types. */ | |
1347 | ||
1348 | #define MATCH(overlap, given, template) \ | |
3138f287 AM |
1349 | ((overlap & ~JumpAbsolute) \ |
1350 | && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute))) | |
252b5132 RH |
1351 | |
1352 | /* If given types r0 and r1 are registers they must be of the same type | |
1353 | unless the expected operand type register overlap is null. | |
1354 | Note that Acc in a template matches every size of reg. */ | |
1355 | #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \ | |
1356 | ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \ | |
1357 | ((g0) & Reg) == ((g1) & Reg) || \ | |
1358 | ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 ) | |
1359 | ||
1360 | { | |
1361 | register unsigned int overlap0, overlap1; | |
252b5132 RH |
1362 | unsigned int overlap2; |
1363 | unsigned int found_reverse_match; | |
1364 | int suffix_check; | |
1365 | ||
cc5ca5ce AM |
1366 | /* All intel opcodes have reversed operands except for "bound" and |
1367 | "enter". We also don't reverse intersegment "jmp" and "call" | |
1368 | instructions with 2 immediate operands so that the immediate segment | |
1369 | precedes the offset, as it does when in AT&T mode. "enter" and the | |
1370 | intersegment "jmp" and "call" instructions are the only ones that | |
1371 | have two immediate operands. */ | |
520dc8e8 | 1372 | if (intel_syntax && i.operands > 1 |
cc5ca5ce AM |
1373 | && (strcmp (mnemonic, "bound") != 0) |
1374 | && !((i.types[0] & Imm) && (i.types[1] & Imm))) | |
252b5132 | 1375 | { |
520dc8e8 | 1376 | union i386_op temp_op; |
24eab124 AM |
1377 | unsigned int temp_type; |
1378 | int xchg1 = 0; | |
ab9da554 | 1379 | int xchg2 = 0; |
252b5132 | 1380 | |
24eab124 AM |
1381 | if (i.operands == 2) |
1382 | { | |
1383 | xchg1 = 0; | |
1384 | xchg2 = 1; | |
1385 | } | |
1386 | else if (i.operands == 3) | |
1387 | { | |
1388 | xchg1 = 0; | |
1389 | xchg2 = 2; | |
1390 | } | |
520dc8e8 AM |
1391 | temp_type = i.types[xchg2]; |
1392 | i.types[xchg2] = i.types[xchg1]; | |
1393 | i.types[xchg1] = temp_type; | |
1394 | temp_op = i.op[xchg2]; | |
1395 | i.op[xchg2] = i.op[xchg1]; | |
1396 | i.op[xchg1] = temp_op; | |
36bf8ab9 AM |
1397 | |
1398 | if (i.mem_operands == 2) | |
1399 | { | |
1400 | const seg_entry *temp_seg; | |
1401 | temp_seg = i.seg[0]; | |
1402 | i.seg[0] = i.seg[1]; | |
1403 | i.seg[1] = temp_seg; | |
1404 | } | |
24eab124 | 1405 | } |
773f551c AM |
1406 | |
1407 | if (i.imm_operands) | |
1408 | { | |
1409 | /* Try to ensure constant immediates are represented in the smallest | |
1410 | opcode possible. */ | |
1411 | char guess_suffix = 0; | |
1412 | int op; | |
1413 | ||
1414 | if (i.suffix) | |
1415 | guess_suffix = i.suffix; | |
1416 | else if (i.reg_operands) | |
1417 | { | |
1418 | /* Figure out a suffix from the last register operand specified. | |
1419 | We can't do this properly yet, ie. excluding InOutPortReg, | |
1420 | but the following works for instructions with immediates. | |
1421 | In any case, we can't set i.suffix yet. */ | |
1422 | for (op = i.operands; --op >= 0; ) | |
1423 | if (i.types[op] & Reg) | |
1424 | { | |
1425 | if (i.types[op] & Reg8) | |
1426 | guess_suffix = BYTE_MNEM_SUFFIX; | |
1427 | else if (i.types[op] & Reg16) | |
1428 | guess_suffix = WORD_MNEM_SUFFIX; | |
1429 | break; | |
1430 | } | |
1431 | } | |
726c5dcd AM |
1432 | else if (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) |
1433 | guess_suffix = WORD_MNEM_SUFFIX; | |
1434 | ||
773f551c AM |
1435 | for (op = i.operands; --op >= 0; ) |
1436 | if ((i.types[op] & Imm) | |
1437 | && i.op[op].imms->X_op == O_constant) | |
1438 | { | |
1439 | /* If a suffix is given, this operand may be shortened. */ | |
1440 | switch (guess_suffix) | |
1441 | { | |
1442 | case WORD_MNEM_SUFFIX: | |
1443 | i.types[op] |= Imm16; | |
1444 | break; | |
1445 | case BYTE_MNEM_SUFFIX: | |
1446 | i.types[op] |= Imm16 | Imm8 | Imm8S; | |
1447 | break; | |
1448 | } | |
1449 | ||
1450 | /* If this operand is at most 16 bits, convert it to a | |
1451 | signed 16 bit number before trying to see whether it will | |
1452 | fit in an even smaller size. This allows a 16-bit operand | |
1453 | such as $0xffe0 to be recognised as within Imm8S range. */ | |
1454 | if ((i.types[op] & Imm16) | |
1455 | && (i.op[op].imms->X_add_number & ~(offsetT)0xffff) == 0) | |
1456 | { | |
1457 | i.op[op].imms->X_add_number = | |
1458 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
1459 | } | |
1460 | i.types[op] |= smallest_imm_type ((long) i.op[op].imms->X_add_number); | |
1461 | } | |
1462 | } | |
1463 | ||
45288df1 AM |
1464 | if (i.disp_operands) |
1465 | { | |
1466 | /* Try to use the smallest displacement type too. */ | |
1467 | int op; | |
1468 | ||
1469 | for (op = i.operands; --op >= 0; ) | |
1470 | if ((i.types[op] & Disp) | |
1471 | && i.op[op].imms->X_op == O_constant) | |
1472 | { | |
1473 | offsetT disp = i.op[op].disps->X_add_number; | |
1474 | ||
1475 | if (i.types[op] & Disp16) | |
1476 | { | |
1477 | /* We know this operand is at most 16 bits, so | |
1478 | convert to a signed 16 bit number before trying | |
1479 | to see whether it will fit in an even smaller | |
1480 | size. */ | |
1481 | ||
1482 | disp = (((disp & 0xffff) ^ 0x8000) - 0x8000); | |
1483 | } | |
1484 | if (fits_in_signed_byte (disp)) | |
1485 | i.types[op] |= Disp8; | |
1486 | } | |
1487 | } | |
1488 | ||
252b5132 RH |
1489 | overlap0 = 0; |
1490 | overlap1 = 0; | |
1491 | overlap2 = 0; | |
1492 | found_reverse_match = 0; | |
1493 | suffix_check = (i.suffix == BYTE_MNEM_SUFFIX | |
1494 | ? No_bSuf | |
1495 | : (i.suffix == WORD_MNEM_SUFFIX | |
1496 | ? No_wSuf | |
1497 | : (i.suffix == SHORT_MNEM_SUFFIX | |
1498 | ? No_sSuf | |
1499 | : (i.suffix == LONG_MNEM_SUFFIX | |
24eab124 | 1500 | ? No_lSuf |
add0c677 | 1501 | : (i.suffix == DWORD_MNEM_SUFFIX |
24eab124 AM |
1502 | ? No_dSuf |
1503 | : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX ? No_xSuf : 0)))))); | |
252b5132 RH |
1504 | |
1505 | for (t = current_templates->start; | |
1506 | t < current_templates->end; | |
1507 | t++) | |
1508 | { | |
1509 | /* Must have right number of operands. */ | |
1510 | if (i.operands != t->operands) | |
1511 | continue; | |
1512 | ||
7f3f1ea2 AM |
1513 | /* Check the suffix, except for some instructions in intel mode. */ |
1514 | if ((t->opcode_modifier & suffix_check) | |
1515 | && !(intel_syntax | |
1516 | && t->base_opcode == 0xd9 | |
1517 | && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */ | |
1518 | || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */ | |
24eab124 | 1519 | continue; |
252b5132 RH |
1520 | |
1521 | else if (!t->operands) | |
1522 | break; /* 0 operands always matches */ | |
1523 | ||
1524 | overlap0 = i.types[0] & t->operand_types[0]; | |
1525 | switch (t->operands) | |
1526 | { | |
1527 | case 1: | |
1528 | if (!MATCH (overlap0, i.types[0], t->operand_types[0])) | |
1529 | continue; | |
1530 | break; | |
1531 | case 2: | |
1532 | case 3: | |
1533 | overlap1 = i.types[1] & t->operand_types[1]; | |
1534 | if (!MATCH (overlap0, i.types[0], t->operand_types[0]) | |
1535 | || !MATCH (overlap1, i.types[1], t->operand_types[1]) | |
1536 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], | |
1537 | t->operand_types[0], | |
1538 | overlap1, i.types[1], | |
1539 | t->operand_types[1])) | |
1540 | { | |
1541 | ||
1542 | /* check if other direction is valid ... */ | |
1543 | if ((t->opcode_modifier & (D|FloatD)) == 0) | |
1544 | continue; | |
1545 | ||
1546 | /* try reversing direction of operands */ | |
1547 | overlap0 = i.types[0] & t->operand_types[1]; | |
1548 | overlap1 = i.types[1] & t->operand_types[0]; | |
1549 | if (!MATCH (overlap0, i.types[0], t->operand_types[1]) | |
1550 | || !MATCH (overlap1, i.types[1], t->operand_types[0]) | |
1551 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], | |
1552 | t->operand_types[1], | |
1553 | overlap1, i.types[1], | |
1554 | t->operand_types[0])) | |
1555 | { | |
1556 | /* does not match either direction */ | |
1557 | continue; | |
1558 | } | |
1559 | /* found_reverse_match holds which of D or FloatDR | |
1560 | we've found. */ | |
1561 | found_reverse_match = t->opcode_modifier & (D|FloatDR); | |
1562 | break; | |
1563 | } | |
1564 | /* found a forward 2 operand match here */ | |
1565 | if (t->operands == 3) | |
1566 | { | |
1567 | /* Here we make use of the fact that there are no | |
1568 | reverse match 3 operand instructions, and all 3 | |
1569 | operand instructions only need to be checked for | |
1570 | register consistency between operands 2 and 3. */ | |
1571 | overlap2 = i.types[2] & t->operand_types[2]; | |
1572 | if (!MATCH (overlap2, i.types[2], t->operand_types[2]) | |
1573 | || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1], | |
1574 | t->operand_types[1], | |
1575 | overlap2, i.types[2], | |
24eab124 | 1576 | t->operand_types[2])) |
252b5132 | 1577 | |
24eab124 | 1578 | continue; |
252b5132 RH |
1579 | } |
1580 | /* found either forward/reverse 2 or 3 operand match here: | |
1581 | slip through to break */ | |
1582 | } | |
1583 | break; /* we've found a match; break out of loop */ | |
1584 | } /* for (t = ... */ | |
1585 | if (t == current_templates->end) | |
1586 | { /* we found no match */ | |
1587 | as_bad (_("suffix or operands invalid for `%s'"), | |
1588 | current_templates->start->name); | |
1589 | return; | |
1590 | } | |
1591 | ||
a38cf1db | 1592 | if (!quiet_warnings) |
3138f287 | 1593 | { |
a38cf1db AM |
1594 | if (!intel_syntax |
1595 | && ((i.types[0] & JumpAbsolute) | |
1596 | != (t->operand_types[0] & JumpAbsolute))) | |
1597 | { | |
1598 | as_warn (_("indirect %s without `*'"), t->name); | |
1599 | } | |
3138f287 | 1600 | |
a38cf1db AM |
1601 | if ((t->opcode_modifier & (IsPrefix|IgnoreSize)) |
1602 | == (IsPrefix|IgnoreSize)) | |
1603 | { | |
1604 | /* Warn them that a data or address size prefix doesn't | |
1605 | affect assembly of the next line of code. */ | |
1606 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
1607 | } | |
252b5132 RH |
1608 | } |
1609 | ||
1610 | /* Copy the template we found. */ | |
1611 | i.tm = *t; | |
1612 | if (found_reverse_match) | |
1613 | { | |
7f3f1ea2 AM |
1614 | /* If we found a reverse match we must alter the opcode |
1615 | direction bit. found_reverse_match holds bits to change | |
1616 | (different for int & float insns). */ | |
1617 | ||
1618 | i.tm.base_opcode ^= found_reverse_match; | |
1619 | ||
252b5132 RH |
1620 | i.tm.operand_types[0] = t->operand_types[1]; |
1621 | i.tm.operand_types[1] = t->operand_types[0]; | |
1622 | } | |
1623 | ||
d0b47220 AM |
1624 | /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */ |
1625 | if (SYSV386_COMPAT | |
7f3f1ea2 AM |
1626 | && intel_syntax |
1627 | && (i.tm.base_opcode & 0xfffffde0) == 0xdce0) | |
1628 | i.tm.base_opcode ^= FloatR; | |
252b5132 RH |
1629 | |
1630 | if (i.tm.opcode_modifier & FWait) | |
1631 | if (! add_prefix (FWAIT_OPCODE)) | |
1632 | return; | |
1633 | ||
1634 | /* Check string instruction segment overrides */ | |
1635 | if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0) | |
1636 | { | |
1637 | int mem_op = (i.types[0] & AnyMem) ? 0 : 1; | |
1638 | if ((i.tm.operand_types[mem_op] & EsSeg) != 0) | |
1639 | { | |
1640 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
1641 | { | |
1642 | as_bad (_("`%s' operand %d must use `%%es' segment"), | |
1643 | i.tm.name, | |
1644 | mem_op + 1); | |
1645 | return; | |
1646 | } | |
1647 | /* There's only ever one segment override allowed per instruction. | |
1648 | This instruction possibly has a legal segment override on the | |
1649 | second operand, so copy the segment to where non-string | |
1650 | instructions store it, allowing common code. */ | |
1651 | i.seg[0] = i.seg[1]; | |
1652 | } | |
1653 | else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0) | |
1654 | { | |
1655 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
1656 | { | |
1657 | as_bad (_("`%s' operand %d must use `%%es' segment"), | |
1658 | i.tm.name, | |
1659 | mem_op + 2); | |
1660 | return; | |
1661 | } | |
1662 | } | |
1663 | } | |
1664 | ||
1665 | /* If matched instruction specifies an explicit instruction mnemonic | |
1666 | suffix, use it. */ | |
1667 | if (i.tm.opcode_modifier & (Size16 | Size32)) | |
1668 | { | |
1669 | if (i.tm.opcode_modifier & Size16) | |
1670 | i.suffix = WORD_MNEM_SUFFIX; | |
1671 | else | |
add0c677 | 1672 | i.suffix = LONG_MNEM_SUFFIX; |
252b5132 RH |
1673 | } |
1674 | else if (i.reg_operands) | |
1675 | { | |
1676 | /* If there's no instruction mnemonic suffix we try to invent one | |
1677 | based on register operands. */ | |
1678 | if (!i.suffix) | |
1679 | { | |
1680 | /* We take i.suffix from the last register operand specified, | |
1681 | Destination register type is more significant than source | |
1682 | register type. */ | |
1683 | int op; | |
1684 | for (op = i.operands; --op >= 0; ) | |
cc5ca5ce AM |
1685 | if ((i.types[op] & Reg) |
1686 | && !(i.tm.operand_types[op] & InOutPortReg)) | |
252b5132 RH |
1687 | { |
1688 | i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX : | |
1689 | (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX : | |
add0c677 | 1690 | LONG_MNEM_SUFFIX); |
252b5132 RH |
1691 | break; |
1692 | } | |
1693 | } | |
1694 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
1695 | { | |
1696 | int op; | |
1697 | for (op = i.operands; --op >= 0; ) | |
1698 | { | |
1699 | /* If this is an eight bit register, it's OK. If it's | |
1700 | the 16 or 32 bit version of an eight bit register, | |
1701 | we will just use the low portion, and that's OK too. */ | |
1702 | if (i.types[op] & Reg8) | |
1703 | continue; | |
1704 | ||
24eab124 AM |
1705 | /* movzx and movsx should not generate this warning. */ |
1706 | if (intel_syntax | |
1707 | && (i.tm.base_opcode == 0xfb7 | |
1708 | || i.tm.base_opcode == 0xfb6 | |
1709 | || i.tm.base_opcode == 0xfbe | |
1710 | || i.tm.base_opcode == 0xfbf)) | |
1711 | continue; | |
252b5132 | 1712 | |
520dc8e8 | 1713 | if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4 |
252b5132 RH |
1714 | #if 0 |
1715 | /* Check that the template allows eight bit regs | |
1716 | This kills insns such as `orb $1,%edx', which | |
1717 | maybe should be allowed. */ | |
1718 | && (i.tm.operand_types[op] & (Reg8|InOutPortReg)) | |
1719 | #endif | |
1720 | ) | |
1721 | { | |
1722 | #if REGISTER_WARNINGS | |
a38cf1db AM |
1723 | if (!quiet_warnings |
1724 | && (i.tm.operand_types[op] & InOutPortReg) == 0) | |
252b5132 | 1725 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), |
520dc8e8 AM |
1726 | (i.op[op].regs - (i.types[op] & Reg16 ? 8 : 16))->reg_name, |
1727 | i.op[op].regs->reg_name, | |
252b5132 RH |
1728 | i.suffix); |
1729 | #endif | |
1730 | continue; | |
1731 | } | |
1732 | /* Any other register is bad */ | |
3f4438ab AM |
1733 | if (i.types[op] & (Reg | RegMMX | RegXMM |
1734 | | SReg2 | SReg3 | |
1735 | | Control | Debug | Test | |
1736 | | FloatReg | FloatAcc)) | |
252b5132 RH |
1737 | { |
1738 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
520dc8e8 | 1739 | i.op[op].regs->reg_name, |
252b5132 RH |
1740 | i.tm.name, |
1741 | i.suffix); | |
1742 | return; | |
1743 | } | |
1744 | } | |
1745 | } | |
add0c677 | 1746 | else if (i.suffix == LONG_MNEM_SUFFIX) |
252b5132 RH |
1747 | { |
1748 | int op; | |
1749 | for (op = i.operands; --op >= 0; ) | |
1750 | /* Reject eight bit registers, except where the template | |
1751 | requires them. (eg. movzb) */ | |
1752 | if ((i.types[op] & Reg8) != 0 | |
1753 | && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0) | |
1754 | { | |
1755 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
520dc8e8 | 1756 | i.op[op].regs->reg_name, |
252b5132 RH |
1757 | i.tm.name, |
1758 | i.suffix); | |
1759 | return; | |
1760 | } | |
1761 | #if REGISTER_WARNINGS | |
1762 | /* Warn if the e prefix on a general reg is missing. */ | |
a38cf1db AM |
1763 | else if (!quiet_warnings |
1764 | && (i.types[op] & Reg16) != 0 | |
252b5132 RH |
1765 | && (i.tm.operand_types[op] & (Reg32|Acc)) != 0) |
1766 | { | |
1767 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
520dc8e8 AM |
1768 | (i.op[op].regs + 8)->reg_name, |
1769 | i.op[op].regs->reg_name, | |
252b5132 RH |
1770 | i.suffix); |
1771 | } | |
1772 | #endif | |
1773 | } | |
1774 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
1775 | { | |
1776 | int op; | |
1777 | for (op = i.operands; --op >= 0; ) | |
1778 | /* Reject eight bit registers, except where the template | |
1779 | requires them. (eg. movzb) */ | |
1780 | if ((i.types[op] & Reg8) != 0 | |
1781 | && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0) | |
1782 | { | |
1783 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
520dc8e8 | 1784 | i.op[op].regs->reg_name, |
252b5132 RH |
1785 | i.tm.name, |
1786 | i.suffix); | |
1787 | return; | |
1788 | } | |
1789 | #if REGISTER_WARNINGS | |
1790 | /* Warn if the e prefix on a general reg is present. */ | |
a38cf1db AM |
1791 | else if (!quiet_warnings |
1792 | && (i.types[op] & Reg32) != 0 | |
252b5132 RH |
1793 | && (i.tm.operand_types[op] & (Reg16|Acc)) != 0) |
1794 | { | |
1795 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
520dc8e8 AM |
1796 | (i.op[op].regs - 8)->reg_name, |
1797 | i.op[op].regs->reg_name, | |
252b5132 RH |
1798 | i.suffix); |
1799 | } | |
1800 | #endif | |
1801 | } | |
1802 | else | |
1803 | abort(); | |
1804 | } | |
eecb386c AM |
1805 | else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix) |
1806 | { | |
1807 | i.suffix = stackop_size; | |
1808 | } | |
252b5132 RH |
1809 | |
1810 | /* Make still unresolved immediate matches conform to size of immediate | |
1811 | given in i.suffix. Note: overlap2 cannot be an immediate! */ | |
1812 | if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32)) | |
1813 | && overlap0 != Imm8 && overlap0 != Imm8S | |
1814 | && overlap0 != Imm16 && overlap0 != Imm32) | |
1815 | { | |
1816 | if (i.suffix) | |
1817 | { | |
24eab124 AM |
1818 | overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) : |
1819 | (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : Imm32)); | |
252b5132 RH |
1820 | } |
1821 | else if (overlap0 == (Imm16 | Imm32)) | |
1822 | { | |
24eab124 | 1823 | overlap0 = |
252b5132 RH |
1824 | (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32; |
1825 | } | |
1826 | else | |
1827 | { | |
1828 | as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")); | |
1829 | return; | |
1830 | } | |
1831 | } | |
1832 | if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32)) | |
1833 | && overlap1 != Imm8 && overlap1 != Imm8S | |
1834 | && overlap1 != Imm16 && overlap1 != Imm32) | |
1835 | { | |
1836 | if (i.suffix) | |
1837 | { | |
24eab124 AM |
1838 | overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) : |
1839 | (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : Imm32)); | |
252b5132 RH |
1840 | } |
1841 | else if (overlap1 == (Imm16 | Imm32)) | |
1842 | { | |
24eab124 | 1843 | overlap1 = |
252b5132 RH |
1844 | (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32; |
1845 | } | |
1846 | else | |
1847 | { | |
1848 | as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")); | |
1849 | return; | |
1850 | } | |
1851 | } | |
1852 | assert ((overlap2 & Imm) == 0); | |
1853 | ||
1854 | i.types[0] = overlap0; | |
1855 | if (overlap0 & ImplicitRegister) | |
1856 | i.reg_operands--; | |
1857 | if (overlap0 & Imm1) | |
1858 | i.imm_operands = 0; /* kludge for shift insns */ | |
1859 | ||
1860 | i.types[1] = overlap1; | |
1861 | if (overlap1 & ImplicitRegister) | |
1862 | i.reg_operands--; | |
1863 | ||
1864 | i.types[2] = overlap2; | |
1865 | if (overlap2 & ImplicitRegister) | |
1866 | i.reg_operands--; | |
1867 | ||
1868 | /* Finalize opcode. First, we change the opcode based on the operand | |
1869 | size given by i.suffix: We need not change things for byte insns. */ | |
1870 | ||
1871 | if (!i.suffix && (i.tm.opcode_modifier & W)) | |
1872 | { | |
1873 | as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction")); | |
1874 | return; | |
1875 | } | |
1876 | ||
1877 | /* For movzx and movsx, need to check the register type */ | |
1878 | if (intel_syntax | |
24eab124 | 1879 | && (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe)) |
252b5132 | 1880 | if (i.suffix && i.suffix == BYTE_MNEM_SUFFIX) |
24eab124 AM |
1881 | { |
1882 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
252b5132 | 1883 | |
520dc8e8 | 1884 | if ((i.op[1].regs->reg_type & Reg16) != 0) |
24eab124 AM |
1885 | if (!add_prefix (prefix)) |
1886 | return; | |
1887 | } | |
252b5132 RH |
1888 | |
1889 | if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX) | |
1890 | { | |
1891 | /* It's not a byte, select word/dword operation. */ | |
1892 | if (i.tm.opcode_modifier & W) | |
1893 | { | |
1894 | if (i.tm.opcode_modifier & ShortForm) | |
1895 | i.tm.base_opcode |= 8; | |
1896 | else | |
1897 | i.tm.base_opcode |= 1; | |
1898 | } | |
1899 | /* Now select between word & dword operations via the operand | |
1900 | size prefix, except for instructions that will ignore this | |
1901 | prefix anyway. */ | |
add0c677 | 1902 | if (((intel_syntax && (i.suffix == DWORD_MNEM_SUFFIX)) |
252b5132 RH |
1903 | || i.suffix == LONG_MNEM_SUFFIX) == flag_16bit_code |
1904 | && !(i.tm.opcode_modifier & IgnoreSize)) | |
1905 | { | |
1906 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
1907 | if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */ | |
1908 | prefix = ADDR_PREFIX_OPCODE; | |
1909 | ||
1910 | if (! add_prefix (prefix)) | |
1911 | return; | |
1912 | } | |
1913 | /* Size floating point instruction. */ | |
1914 | if (i.suffix == LONG_MNEM_SUFFIX | |
add0c677 | 1915 | || (intel_syntax && i.suffix == DWORD_MNEM_SUFFIX)) |
252b5132 RH |
1916 | { |
1917 | if (i.tm.opcode_modifier & FloatMF) | |
1918 | i.tm.base_opcode ^= 4; | |
1919 | } | |
252b5132 RH |
1920 | } |
1921 | ||
3f4438ab | 1922 | if (i.tm.opcode_modifier & ImmExt) |
252b5132 | 1923 | { |
3f4438ab AM |
1924 | /* These AMD 3DNow! and Intel Katmai New Instructions have an |
1925 | opcode suffix which is coded in the same place as an 8-bit | |
1926 | immediate field would be. Here we fake an 8-bit immediate | |
1927 | operand from the opcode suffix stored in tm.extension_opcode. */ | |
252b5132 RH |
1928 | |
1929 | expressionS *exp; | |
1930 | ||
520dc8e8 | 1931 | assert(i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS); |
252b5132 RH |
1932 | |
1933 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 1934 | i.op[i.operands].imms = exp; |
252b5132 RH |
1935 | i.types[i.operands++] = Imm8; |
1936 | exp->X_op = O_constant; | |
1937 | exp->X_add_number = i.tm.extension_opcode; | |
1938 | i.tm.extension_opcode = None; | |
1939 | } | |
1940 | ||
1941 | /* For insns with operands there are more diddles to do to the opcode. */ | |
1942 | if (i.operands) | |
1943 | { | |
24eab124 | 1944 | /* Default segment register this instruction will use |
252b5132 RH |
1945 | for memory accesses. 0 means unknown. |
1946 | This is only for optimizing out unnecessary segment overrides. */ | |
1947 | const seg_entry *default_seg = 0; | |
1948 | ||
252b5132 RH |
1949 | /* The imul $imm, %reg instruction is converted into |
1950 | imul $imm, %reg, %reg, and the clr %reg instruction | |
1951 | is converted into xor %reg, %reg. */ | |
1952 | if (i.tm.opcode_modifier & regKludge) | |
1953 | { | |
1954 | unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1; | |
1955 | /* Pretend we saw the extra register operand. */ | |
520dc8e8 AM |
1956 | assert (i.op[first_reg_op+1].regs == 0); |
1957 | i.op[first_reg_op+1].regs = i.op[first_reg_op].regs; | |
1958 | i.types[first_reg_op+1] = i.types[first_reg_op]; | |
252b5132 RH |
1959 | i.reg_operands = 2; |
1960 | } | |
1961 | ||
1962 | if (i.tm.opcode_modifier & ShortForm) | |
1963 | { | |
1964 | /* The register or float register operand is in operand 0 or 1. */ | |
1965 | unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1; | |
1966 | /* Register goes in low 3 bits of opcode. */ | |
520dc8e8 | 1967 | i.tm.base_opcode |= i.op[op].regs->reg_num; |
a38cf1db | 1968 | if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) |
252b5132 RH |
1969 | { |
1970 | /* Warn about some common errors, but press on regardless. | |
1971 | The first case can be generated by gcc (<= 2.8.1). */ | |
1972 | if (i.operands == 2) | |
1973 | { | |
1974 | /* reversed arguments on faddp, fsubp, etc. */ | |
1975 | as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name, | |
520dc8e8 AM |
1976 | i.op[1].regs->reg_name, |
1977 | i.op[0].regs->reg_name); | |
252b5132 RH |
1978 | } |
1979 | else | |
1980 | { | |
1981 | /* extraneous `l' suffix on fp insn */ | |
1982 | as_warn (_("translating to `%s %%%s'"), i.tm.name, | |
520dc8e8 | 1983 | i.op[0].regs->reg_name); |
252b5132 RH |
1984 | } |
1985 | } | |
1986 | } | |
1987 | else if (i.tm.opcode_modifier & Modrm) | |
1988 | { | |
1989 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
1990 | must be put into the modrm byte). | |
1991 | Now, we make the modrm & index base bytes based on all the | |
1992 | info we've collected. */ | |
1993 | ||
1994 | /* i.reg_operands MUST be the number of real register operands; | |
1995 | implicit registers do not count. */ | |
1996 | if (i.reg_operands == 2) | |
1997 | { | |
1998 | unsigned int source, dest; | |
1999 | source = ((i.types[0] | |
3f4438ab AM |
2000 | & (Reg | RegMMX | RegXMM |
2001 | | SReg2 | SReg3 | |
2002 | | Control | Debug | Test)) | |
252b5132 RH |
2003 | ? 0 : 1); |
2004 | dest = source + 1; | |
2005 | ||
252b5132 | 2006 | i.rm.mode = 3; |
3f4438ab AM |
2007 | /* One of the register operands will be encoded in the |
2008 | i.tm.reg field, the other in the combined i.tm.mode | |
2009 | and i.tm.regmem fields. If no form of this | |
2010 | instruction supports a memory destination operand, | |
2011 | then we assume the source operand may sometimes be | |
2012 | a memory operand and so we need to store the | |
2013 | destination in the i.rm.reg field. */ | |
2014 | if ((i.tm.operand_types[dest] & AnyMem) == 0) | |
252b5132 | 2015 | { |
520dc8e8 AM |
2016 | i.rm.reg = i.op[dest].regs->reg_num; |
2017 | i.rm.regmem = i.op[source].regs->reg_num; | |
252b5132 RH |
2018 | } |
2019 | else | |
2020 | { | |
520dc8e8 AM |
2021 | i.rm.reg = i.op[source].regs->reg_num; |
2022 | i.rm.regmem = i.op[dest].regs->reg_num; | |
252b5132 RH |
2023 | } |
2024 | } | |
2025 | else | |
2026 | { /* if it's not 2 reg operands... */ | |
2027 | if (i.mem_operands) | |
2028 | { | |
2029 | unsigned int fake_zero_displacement = 0; | |
2030 | unsigned int op = ((i.types[0] & AnyMem) | |
2031 | ? 0 | |
2032 | : (i.types[1] & AnyMem) ? 1 : 2); | |
2033 | ||
2034 | default_seg = &ds; | |
2035 | ||
2036 | if (! i.base_reg) | |
2037 | { | |
2038 | i.rm.mode = 0; | |
2039 | if (! i.disp_operands) | |
2040 | fake_zero_displacement = 1; | |
2041 | if (! i.index_reg) | |
2042 | { | |
2043 | /* Operand is just <disp> */ | |
2044 | if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0)) | |
2045 | { | |
2046 | i.rm.regmem = NO_BASE_REGISTER_16; | |
2047 | i.types[op] &= ~Disp; | |
2048 | i.types[op] |= Disp16; | |
2049 | } | |
2050 | else | |
2051 | { | |
2052 | i.rm.regmem = NO_BASE_REGISTER; | |
2053 | i.types[op] &= ~Disp; | |
2054 | i.types[op] |= Disp32; | |
2055 | } | |
2056 | } | |
2057 | else /* ! i.base_reg && i.index_reg */ | |
2058 | { | |
2059 | i.sib.index = i.index_reg->reg_num; | |
2060 | i.sib.base = NO_BASE_REGISTER; | |
2061 | i.sib.scale = i.log2_scale_factor; | |
2062 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2063 | i.types[op] &= ~Disp; | |
2064 | i.types[op] |= Disp32; /* Must be 32 bit */ | |
2065 | } | |
2066 | } | |
2067 | else if (i.base_reg->reg_type & Reg16) | |
2068 | { | |
2069 | switch (i.base_reg->reg_num) | |
2070 | { | |
2071 | case 3: /* (%bx) */ | |
2072 | if (! i.index_reg) | |
2073 | i.rm.regmem = 7; | |
2074 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
2075 | i.rm.regmem = i.index_reg->reg_num - 6; | |
2076 | break; | |
2077 | case 5: /* (%bp) */ | |
2078 | default_seg = &ss; | |
2079 | if (! i.index_reg) | |
2080 | { | |
2081 | i.rm.regmem = 6; | |
2082 | if ((i.types[op] & Disp) == 0) | |
2083 | { | |
2084 | /* fake (%bp) into 0(%bp) */ | |
2085 | i.types[op] |= Disp8; | |
2086 | fake_zero_displacement = 1; | |
2087 | } | |
2088 | } | |
2089 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
2090 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
2091 | break; | |
2092 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
2093 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
2094 | } | |
2095 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
2096 | } | |
2097 | else /* i.base_reg and 32 bit mode */ | |
2098 | { | |
2099 | i.rm.regmem = i.base_reg->reg_num; | |
2100 | i.sib.base = i.base_reg->reg_num; | |
2101 | if (i.base_reg->reg_num == EBP_REG_NUM) | |
2102 | { | |
2103 | default_seg = &ss; | |
2104 | if (i.disp_operands == 0) | |
2105 | { | |
2106 | fake_zero_displacement = 1; | |
2107 | i.types[op] |= Disp8; | |
2108 | } | |
2109 | } | |
2110 | else if (i.base_reg->reg_num == ESP_REG_NUM) | |
2111 | { | |
2112 | default_seg = &ss; | |
2113 | } | |
2114 | i.sib.scale = i.log2_scale_factor; | |
2115 | if (! i.index_reg) | |
2116 | { | |
2117 | /* <disp>(%esp) becomes two byte modrm | |
2118 | with no index register. We've already | |
2119 | stored the code for esp in i.rm.regmem | |
2120 | ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any | |
2121 | base register besides %esp will not use | |
2122 | the extra modrm byte. */ | |
2123 | i.sib.index = NO_INDEX_REGISTER; | |
2124 | #if ! SCALE1_WHEN_NO_INDEX | |
2125 | /* Another case where we force the second | |
2126 | modrm byte. */ | |
2127 | if (i.log2_scale_factor) | |
2128 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2129 | #endif | |
2130 | } | |
2131 | else | |
2132 | { | |
2133 | i.sib.index = i.index_reg->reg_num; | |
2134 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2135 | } | |
2136 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
2137 | } | |
2138 | ||
2139 | if (fake_zero_displacement) | |
2140 | { | |
2141 | /* Fakes a zero displacement assuming that i.types[op] | |
2142 | holds the correct displacement size. */ | |
b4cac588 AM |
2143 | expressionS *exp; |
2144 | ||
520dc8e8 | 2145 | assert (i.op[op].disps == 0); |
252b5132 | 2146 | exp = &disp_expressions[i.disp_operands++]; |
520dc8e8 | 2147 | i.op[op].disps = exp; |
252b5132 RH |
2148 | exp->X_op = O_constant; |
2149 | exp->X_add_number = 0; | |
2150 | exp->X_add_symbol = (symbolS *) 0; | |
2151 | exp->X_op_symbol = (symbolS *) 0; | |
2152 | } | |
2153 | } | |
2154 | ||
2155 | /* Fill in i.rm.reg or i.rm.regmem field with register | |
2156 | operand (if any) based on i.tm.extension_opcode. | |
2157 | Again, we must be careful to make sure that | |
2158 | segment/control/debug/test/MMX registers are coded | |
2159 | into the i.rm.reg field. */ | |
2160 | if (i.reg_operands) | |
2161 | { | |
2162 | unsigned int op = | |
2163 | ((i.types[0] | |
3f4438ab AM |
2164 | & (Reg | RegMMX | RegXMM |
2165 | | SReg2 | SReg3 | |
2166 | | Control | Debug | Test)) | |
252b5132 RH |
2167 | ? 0 |
2168 | : ((i.types[1] | |
3f4438ab AM |
2169 | & (Reg | RegMMX | RegXMM |
2170 | | SReg2 | SReg3 | |
2171 | | Control | Debug | Test)) | |
252b5132 RH |
2172 | ? 1 |
2173 | : 2)); | |
2174 | /* If there is an extension opcode to put here, the | |
2175 | register number must be put into the regmem field. */ | |
2176 | if (i.tm.extension_opcode != None) | |
520dc8e8 | 2177 | i.rm.regmem = i.op[op].regs->reg_num; |
252b5132 | 2178 | else |
520dc8e8 | 2179 | i.rm.reg = i.op[op].regs->reg_num; |
252b5132 RH |
2180 | |
2181 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 | |
2182 | we must set it to 3 to indicate this is a register | |
2183 | operand in the regmem field. */ | |
2184 | if (!i.mem_operands) | |
2185 | i.rm.mode = 3; | |
2186 | } | |
2187 | ||
2188 | /* Fill in i.rm.reg field with extension opcode (if any). */ | |
2189 | if (i.tm.extension_opcode != None) | |
2190 | i.rm.reg = i.tm.extension_opcode; | |
2191 | } | |
2192 | } | |
2193 | else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm)) | |
2194 | { | |
520dc8e8 | 2195 | if (i.tm.base_opcode == POP_SEG_SHORT && i.op[0].regs->reg_num == 1) |
252b5132 RH |
2196 | { |
2197 | as_bad (_("you can't `pop %%cs'")); | |
2198 | return; | |
2199 | } | |
520dc8e8 | 2200 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
252b5132 RH |
2201 | } |
2202 | else if ((i.tm.base_opcode & ~(D|W)) == MOV_AX_DISP32) | |
2203 | { | |
2204 | default_seg = &ds; | |
2205 | } | |
2206 | else if ((i.tm.opcode_modifier & IsString) != 0) | |
2207 | { | |
2208 | /* For the string instructions that allow a segment override | |
2209 | on one of their operands, the default segment is ds. */ | |
2210 | default_seg = &ds; | |
2211 | } | |
2212 | ||
2213 | /* If a segment was explicitly specified, | |
2214 | and the specified segment is not the default, | |
2215 | use an opcode prefix to select it. | |
2216 | If we never figured out what the default segment is, | |
2217 | then default_seg will be zero at this point, | |
2218 | and the specified segment prefix will always be used. */ | |
2219 | if ((i.seg[0]) && (i.seg[0] != default_seg)) | |
2220 | { | |
2221 | if (! add_prefix (i.seg[0]->seg_prefix)) | |
2222 | return; | |
2223 | } | |
2224 | } | |
a38cf1db | 2225 | else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) |
252b5132 | 2226 | { |
24eab124 AM |
2227 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ |
2228 | as_warn (_("translating to `%sp'"), i.tm.name); | |
252b5132 RH |
2229 | } |
2230 | } | |
2231 | ||
2232 | /* Handle conversion of 'int $3' --> special int3 insn. */ | |
520dc8e8 | 2233 | if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3) |
252b5132 RH |
2234 | { |
2235 | i.tm.base_opcode = INT3_OPCODE; | |
2236 | i.imm_operands = 0; | |
2237 | } | |
2238 | ||
2f66722d | 2239 | if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword)) |
520dc8e8 | 2240 | && i.op[0].disps->X_op == O_constant) |
2f66722d AM |
2241 | { |
2242 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
2243 | the absolute address given by the constant. Since ix86 jumps and | |
2244 | calls are pc relative, we need to generate a reloc. */ | |
520dc8e8 AM |
2245 | i.op[0].disps->X_add_symbol = &abs_symbol; |
2246 | i.op[0].disps->X_op = O_symbol; | |
2f66722d AM |
2247 | } |
2248 | ||
252b5132 RH |
2249 | /* We are ready to output the insn. */ |
2250 | { | |
2251 | register char *p; | |
2252 | ||
2253 | /* Output jumps. */ | |
2254 | if (i.tm.opcode_modifier & Jump) | |
2255 | { | |
a217f122 AM |
2256 | int size; |
2257 | int code16; | |
2258 | int prefix; | |
252b5132 | 2259 | |
a217f122 AM |
2260 | code16 = 0; |
2261 | if (flag_16bit_code) | |
2262 | code16 = CODE16; | |
2263 | ||
2264 | prefix = 0; | |
2265 | if (i.prefix[DATA_PREFIX]) | |
252b5132 | 2266 | { |
a217f122 | 2267 | prefix = 1; |
252b5132 | 2268 | i.prefixes -= 1; |
a217f122 | 2269 | code16 ^= CODE16; |
252b5132 | 2270 | } |
252b5132 | 2271 | |
a217f122 AM |
2272 | size = 4; |
2273 | if (code16) | |
2274 | size = 2; | |
2275 | ||
2276 | if (i.prefixes != 0 && !intel_syntax) | |
252b5132 RH |
2277 | as_warn (_("skipping prefixes on this instruction")); |
2278 | ||
2f66722d AM |
2279 | /* It's always a symbol; End frag & setup for relax. |
2280 | Make sure there is enough room in this frag for the largest | |
2281 | instruction we may generate in md_convert_frag. This is 2 | |
2282 | bytes for the opcode and room for the prefix and largest | |
2283 | displacement. */ | |
2284 | frag_grow (prefix + 2 + size); | |
2285 | insn_size += prefix + 1; | |
2286 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
2287 | p = frag_more (prefix + 1); | |
2288 | if (prefix) | |
2289 | *p++ = DATA_PREFIX_OPCODE; | |
2290 | *p = i.tm.base_opcode; | |
ee7fcc42 AM |
2291 | /* 1 possible extra opcode + displacement go in var part. |
2292 | Pass reloc in fr_var. */ | |
2f66722d AM |
2293 | frag_var (rs_machine_dependent, |
2294 | 1 + size, | |
ee7fcc42 | 2295 | i.disp_reloc[0], |
2f66722d AM |
2296 | ((unsigned char) *p == JUMP_PC_RELATIVE |
2297 | ? ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL) | code16 | |
2298 | : ENCODE_RELAX_STATE (COND_JUMP, SMALL) | code16), | |
520dc8e8 AM |
2299 | i.op[0].disps->X_add_symbol, |
2300 | i.op[0].disps->X_add_number, | |
2f66722d | 2301 | p); |
252b5132 RH |
2302 | } |
2303 | else if (i.tm.opcode_modifier & (JumpByte | JumpDword)) | |
2304 | { | |
a217f122 | 2305 | int size; |
252b5132 | 2306 | |
a217f122 | 2307 | if (i.tm.opcode_modifier & JumpByte) |
252b5132 | 2308 | { |
a217f122 AM |
2309 | /* This is a loop or jecxz type instruction. */ |
2310 | size = 1; | |
252b5132 RH |
2311 | if (i.prefix[ADDR_PREFIX]) |
2312 | { | |
2313 | insn_size += 1; | |
2314 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
2315 | i.prefixes -= 1; | |
2316 | } | |
2317 | } | |
2318 | else | |
2319 | { | |
a217f122 AM |
2320 | int code16; |
2321 | ||
2322 | code16 = 0; | |
2323 | if (flag_16bit_code) | |
2324 | code16 = CODE16; | |
252b5132 RH |
2325 | |
2326 | if (i.prefix[DATA_PREFIX]) | |
2327 | { | |
2328 | insn_size += 1; | |
2329 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
2330 | i.prefixes -= 1; | |
a217f122 | 2331 | code16 ^= CODE16; |
252b5132 | 2332 | } |
252b5132 | 2333 | |
a217f122 | 2334 | size = 4; |
252b5132 RH |
2335 | if (code16) |
2336 | size = 2; | |
2337 | } | |
2338 | ||
a217f122 | 2339 | if (i.prefixes != 0 && !intel_syntax) |
252b5132 RH |
2340 | as_warn (_("skipping prefixes on this instruction")); |
2341 | ||
2342 | if (fits_in_unsigned_byte (i.tm.base_opcode)) | |
2343 | { | |
2344 | insn_size += 1 + size; | |
2345 | p = frag_more (1 + size); | |
2346 | } | |
2347 | else | |
2348 | { | |
a217f122 AM |
2349 | /* opcode can be at most two bytes */ |
2350 | insn_size += 2 + size; | |
252b5132 RH |
2351 | p = frag_more (2 + size); |
2352 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
2353 | } | |
2354 | *p++ = i.tm.base_opcode & 0xff; | |
2355 | ||
2f66722d | 2356 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
520dc8e8 | 2357 | i.op[0].disps, 1, reloc (size, 1, i.disp_reloc[0])); |
252b5132 RH |
2358 | } |
2359 | else if (i.tm.opcode_modifier & JumpInterSegment) | |
2360 | { | |
2361 | int size; | |
a217f122 AM |
2362 | int prefix; |
2363 | int code16; | |
252b5132 | 2364 | |
a217f122 AM |
2365 | code16 = 0; |
2366 | if (flag_16bit_code) | |
2367 | code16 = CODE16; | |
2368 | ||
2369 | prefix = 0; | |
2370 | if (i.prefix[DATA_PREFIX]) | |
252b5132 | 2371 | { |
a217f122 | 2372 | prefix = 1; |
252b5132 | 2373 | i.prefixes -= 1; |
a217f122 | 2374 | code16 ^= CODE16; |
252b5132 | 2375 | } |
252b5132 RH |
2376 | |
2377 | size = 4; | |
252b5132 | 2378 | if (code16) |
f6af82bd | 2379 | size = 2; |
252b5132 | 2380 | |
a217f122 | 2381 | if (i.prefixes != 0 && !intel_syntax) |
252b5132 RH |
2382 | as_warn (_("skipping prefixes on this instruction")); |
2383 | ||
2384 | insn_size += prefix + 1 + 2 + size; /* 1 opcode; 2 segment; offset */ | |
2385 | p = frag_more (prefix + 1 + 2 + size); | |
2386 | if (prefix) | |
2387 | *p++ = DATA_PREFIX_OPCODE; | |
2388 | *p++ = i.tm.base_opcode; | |
520dc8e8 | 2389 | if (i.op[1].imms->X_op == O_constant) |
252b5132 | 2390 | { |
847f7ad4 | 2391 | offsetT n = i.op[1].imms->X_add_number; |
252b5132 | 2392 | |
773f551c AM |
2393 | if (size == 2 |
2394 | && !fits_in_unsigned_word (n) | |
2395 | && !fits_in_signed_word (n)) | |
252b5132 RH |
2396 | { |
2397 | as_bad (_("16-bit jump out of range")); | |
2398 | return; | |
2399 | } | |
847f7ad4 | 2400 | md_number_to_chars (p, n, size); |
252b5132 RH |
2401 | } |
2402 | else | |
2403 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
520dc8e8 AM |
2404 | i.op[1].imms, 0, reloc (size, 0, i.disp_reloc[0])); |
2405 | if (i.op[0].imms->X_op != O_constant) | |
252b5132 RH |
2406 | as_bad (_("can't handle non absolute segment in `%s'"), |
2407 | i.tm.name); | |
520dc8e8 | 2408 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); |
252b5132 RH |
2409 | } |
2410 | else | |
2411 | { | |
2412 | /* Output normal instructions here. */ | |
2413 | unsigned char *q; | |
2414 | ||
2415 | /* The prefix bytes. */ | |
2416 | for (q = i.prefix; | |
2417 | q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]); | |
2418 | q++) | |
2419 | { | |
2420 | if (*q) | |
2421 | { | |
2422 | insn_size += 1; | |
2423 | p = frag_more (1); | |
2424 | md_number_to_chars (p, (valueT) *q, 1); | |
2425 | } | |
2426 | } | |
2427 | ||
2428 | /* Now the opcode; be careful about word order here! */ | |
2429 | if (fits_in_unsigned_byte (i.tm.base_opcode)) | |
2430 | { | |
2431 | insn_size += 1; | |
2432 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
2433 | } | |
2434 | else if (fits_in_unsigned_word (i.tm.base_opcode)) | |
2435 | { | |
2436 | insn_size += 2; | |
2437 | p = frag_more (2); | |
2438 | /* put out high byte first: can't use md_number_to_chars! */ | |
2439 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
2440 | *p = i.tm.base_opcode & 0xff; | |
2441 | } | |
2442 | else | |
2443 | { /* opcode is either 3 or 4 bytes */ | |
2444 | if (i.tm.base_opcode & 0xff000000) | |
2445 | { | |
2446 | insn_size += 4; | |
2447 | p = frag_more (4); | |
2448 | *p++ = (i.tm.base_opcode >> 24) & 0xff; | |
2449 | } | |
2450 | else | |
2451 | { | |
2452 | insn_size += 3; | |
2453 | p = frag_more (3); | |
2454 | } | |
2455 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
2456 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
2457 | *p = (i.tm.base_opcode) & 0xff; | |
2458 | } | |
2459 | ||
2460 | /* Now the modrm byte and sib byte (if present). */ | |
2461 | if (i.tm.opcode_modifier & Modrm) | |
2462 | { | |
2463 | insn_size += 1; | |
2464 | p = frag_more (1); | |
2465 | md_number_to_chars (p, | |
2466 | (valueT) (i.rm.regmem << 0 | |
2467 | | i.rm.reg << 3 | |
2468 | | i.rm.mode << 6), | |
2469 | 1); | |
2470 | /* If i.rm.regmem == ESP (4) | |
2471 | && i.rm.mode != (Register mode) | |
2472 | && not 16 bit | |
2473 | ==> need second modrm byte. */ | |
2474 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
2475 | && i.rm.mode != 3 | |
2476 | && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0)) | |
2477 | { | |
2478 | insn_size += 1; | |
2479 | p = frag_more (1); | |
2480 | md_number_to_chars (p, | |
2481 | (valueT) (i.sib.base << 0 | |
2482 | | i.sib.index << 3 | |
2483 | | i.sib.scale << 6), | |
2484 | 1); | |
2485 | } | |
2486 | } | |
2487 | ||
2488 | if (i.disp_operands) | |
2489 | { | |
2490 | register unsigned int n; | |
2491 | ||
2492 | for (n = 0; n < i.operands; n++) | |
2493 | { | |
520dc8e8 | 2494 | if (i.types[n] & Disp) |
252b5132 | 2495 | { |
520dc8e8 | 2496 | if (i.op[n].disps->X_op == O_constant) |
252b5132 | 2497 | { |
847f7ad4 AM |
2498 | int size; |
2499 | offsetT val; | |
b4cac588 | 2500 | |
847f7ad4 | 2501 | size = 4; |
b4cac588 | 2502 | if (i.types[n] & (Disp8 | Disp16)) |
252b5132 | 2503 | { |
b4cac588 | 2504 | size = 2; |
b4cac588 | 2505 | if (i.types[n] & Disp8) |
847f7ad4 | 2506 | size = 1; |
252b5132 | 2507 | } |
847f7ad4 AM |
2508 | val = offset_in_range (i.op[n].disps->X_add_number, |
2509 | size); | |
b4cac588 AM |
2510 | insn_size += size; |
2511 | p = frag_more (size); | |
847f7ad4 | 2512 | md_number_to_chars (p, val, size); |
252b5132 | 2513 | } |
252b5132 | 2514 | else |
520dc8e8 AM |
2515 | { |
2516 | int size = 4; | |
2517 | ||
2518 | if (i.types[n] & Disp16) | |
2519 | size = 2; | |
2520 | ||
2521 | insn_size += size; | |
2522 | p = frag_more (size); | |
2523 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
2524 | i.op[n].disps, 0, | |
2525 | reloc (size, 0, i.disp_reloc[n])); | |
252b5132 RH |
2526 | } |
2527 | } | |
2528 | } | |
2529 | } /* end displacement output */ | |
2530 | ||
2531 | /* output immediate */ | |
2532 | if (i.imm_operands) | |
2533 | { | |
2534 | register unsigned int n; | |
2535 | ||
2536 | for (n = 0; n < i.operands; n++) | |
2537 | { | |
520dc8e8 | 2538 | if (i.types[n] & Imm) |
252b5132 | 2539 | { |
520dc8e8 | 2540 | if (i.op[n].imms->X_op == O_constant) |
252b5132 | 2541 | { |
847f7ad4 AM |
2542 | int size; |
2543 | offsetT val; | |
b4cac588 | 2544 | |
847f7ad4 | 2545 | size = 4; |
b4cac588 | 2546 | if (i.types[n] & (Imm8 | Imm8S | Imm16)) |
252b5132 | 2547 | { |
b4cac588 | 2548 | size = 2; |
b4cac588 | 2549 | if (i.types[n] & (Imm8 | Imm8S)) |
847f7ad4 | 2550 | size = 1; |
252b5132 | 2551 | } |
847f7ad4 AM |
2552 | val = offset_in_range (i.op[n].imms->X_add_number, |
2553 | size); | |
b4cac588 AM |
2554 | insn_size += size; |
2555 | p = frag_more (size); | |
847f7ad4 | 2556 | md_number_to_chars (p, val, size); |
252b5132 RH |
2557 | } |
2558 | else | |
2559 | { /* not absolute_section */ | |
2560 | /* Need a 32-bit fixup (don't support 8bit | |
520dc8e8 | 2561 | non-absolute imms). Try to support other |
252b5132 | 2562 | sizes ... */ |
f6af82bd AM |
2563 | #ifdef BFD_ASSEMBLER |
2564 | enum bfd_reloc_code_real reloc_type; | |
2565 | #else | |
2566 | int reloc_type; | |
2567 | #endif | |
520dc8e8 | 2568 | int size = 4; |
252b5132 | 2569 | |
520dc8e8 | 2570 | if (i.types[n] & Imm16) |
252b5132 | 2571 | size = 2; |
520dc8e8 AM |
2572 | else if (i.types[n] & (Imm8 | Imm8S)) |
2573 | size = 1; | |
2574 | ||
252b5132 RH |
2575 | insn_size += size; |
2576 | p = frag_more (size); | |
f6af82bd | 2577 | reloc_type = reloc (size, 0, i.disp_reloc[0]); |
252b5132 | 2578 | #ifdef BFD_ASSEMBLER |
f6af82bd | 2579 | if (reloc_type == BFD_RELOC_32 |
252b5132 | 2580 | && GOT_symbol |
520dc8e8 AM |
2581 | && GOT_symbol == i.op[n].imms->X_add_symbol |
2582 | && (i.op[n].imms->X_op == O_symbol | |
2583 | || (i.op[n].imms->X_op == O_add | |
49309057 | 2584 | && ((symbol_get_value_expression |
520dc8e8 | 2585 | (i.op[n].imms->X_op_symbol)->X_op) |
252b5132 RH |
2586 | == O_subtract)))) |
2587 | { | |
f6af82bd | 2588 | reloc_type = BFD_RELOC_386_GOTPC; |
520dc8e8 | 2589 | i.op[n].imms->X_add_number += 3; |
252b5132 RH |
2590 | } |
2591 | #endif | |
2592 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
520dc8e8 | 2593 | i.op[n].imms, 0, reloc_type); |
252b5132 RH |
2594 | } |
2595 | } | |
2596 | } | |
2597 | } /* end immediate output */ | |
2598 | } | |
2599 | ||
2600 | #ifdef DEBUG386 | |
2601 | if (flag_debug) | |
2602 | { | |
2603 | pi (line, &i); | |
2604 | } | |
2605 | #endif /* DEBUG386 */ | |
2606 | } | |
2607 | } | |
2608 | \f | |
252b5132 RH |
2609 | static int i386_immediate PARAMS ((char *)); |
2610 | ||
2611 | static int | |
2612 | i386_immediate (imm_start) | |
2613 | char *imm_start; | |
2614 | { | |
2615 | char *save_input_line_pointer; | |
2616 | segT exp_seg = 0; | |
2617 | expressionS * exp; | |
2618 | ||
2619 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
2620 | { | |
d0b47220 | 2621 | as_bad (_("only 1 or 2 immediate operands are allowed")); |
252b5132 RH |
2622 | return 0; |
2623 | } | |
2624 | ||
2625 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 2626 | i.op[this_operand].imms = exp; |
252b5132 RH |
2627 | |
2628 | if (is_space_char (*imm_start)) | |
2629 | ++imm_start; | |
2630 | ||
2631 | save_input_line_pointer = input_line_pointer; | |
2632 | input_line_pointer = imm_start; | |
2633 | ||
2634 | #ifndef LEX_AT | |
24eab124 AM |
2635 | { |
2636 | /* | |
2637 | * We can have operands of the form | |
2638 | * <symbol>@GOTOFF+<nnn> | |
2639 | * Take the easy way out here and copy everything | |
2640 | * into a temporary buffer... | |
2641 | */ | |
2642 | register char *cp; | |
2643 | ||
2644 | cp = strchr (input_line_pointer, '@'); | |
2645 | if (cp != NULL) | |
2646 | { | |
2647 | char *tmpbuf; | |
2648 | int len = 0; | |
2649 | int first; | |
2650 | ||
2651 | /* GOT relocations are not supported in 16 bit mode */ | |
2652 | if (flag_16bit_code) | |
2653 | as_bad (_("GOT relocations not supported in 16 bit mode")); | |
2654 | ||
2655 | if (GOT_symbol == NULL) | |
2656 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
2657 | ||
2658 | if (strncmp (cp + 1, "PLT", 3) == 0) | |
2659 | { | |
2660 | i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32; | |
2661 | len = 3; | |
2662 | } | |
2663 | else if (strncmp (cp + 1, "GOTOFF", 6) == 0) | |
2664 | { | |
2665 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF; | |
2666 | len = 6; | |
2667 | } | |
2668 | else if (strncmp (cp + 1, "GOT", 3) == 0) | |
2669 | { | |
2670 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32; | |
2671 | len = 3; | |
2672 | } | |
2673 | else | |
d0b47220 | 2674 | as_bad (_("bad reloc specifier in expression")); |
24eab124 AM |
2675 | |
2676 | /* Replace the relocation token with ' ', so that errors like | |
2677 | foo@GOTOFF1 will be detected. */ | |
2678 | first = cp - input_line_pointer; | |
2679 | tmpbuf = (char *) alloca (strlen(input_line_pointer)); | |
2680 | memcpy (tmpbuf, input_line_pointer, first); | |
2681 | tmpbuf[first] = ' '; | |
2682 | strcpy (tmpbuf + first + 1, cp + 1 + len); | |
2683 | input_line_pointer = tmpbuf; | |
2684 | } | |
2685 | } | |
252b5132 RH |
2686 | #endif |
2687 | ||
2688 | exp_seg = expression (exp); | |
2689 | ||
83183c0c | 2690 | SKIP_WHITESPACE (); |
252b5132 | 2691 | if (*input_line_pointer) |
d0b47220 | 2692 | as_bad (_("ignoring junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
2693 | |
2694 | input_line_pointer = save_input_line_pointer; | |
2695 | ||
2daf4fd8 | 2696 | if (exp->X_op == O_absent || exp->X_op == O_big) |
252b5132 RH |
2697 | { |
2698 | /* missing or bad expr becomes absolute 0 */ | |
d0b47220 | 2699 | as_bad (_("missing or invalid immediate expression `%s' taken as 0"), |
24eab124 | 2700 | imm_start); |
252b5132 RH |
2701 | exp->X_op = O_constant; |
2702 | exp->X_add_number = 0; | |
2703 | exp->X_add_symbol = (symbolS *) 0; | |
2704 | exp->X_op_symbol = (symbolS *) 0; | |
252b5132 | 2705 | } |
2daf4fd8 AM |
2706 | |
2707 | if (exp->X_op == O_constant) | |
252b5132 | 2708 | { |
726c5dcd | 2709 | i.types[this_operand] |= Imm32; /* Size it properly later. */ |
252b5132 | 2710 | } |
4c63da97 AM |
2711 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
2712 | else if ( | |
2713 | #ifdef BFD_ASSEMBLER | |
2714 | OUTPUT_FLAVOR == bfd_target_aout_flavour && | |
2715 | #endif | |
2716 | exp_seg != text_section | |
24eab124 AM |
2717 | && exp_seg != data_section |
2718 | && exp_seg != bss_section | |
2719 | && exp_seg != undefined_section | |
252b5132 | 2720 | #ifdef BFD_ASSEMBLER |
24eab124 | 2721 | && !bfd_is_com_section (exp_seg) |
252b5132 | 2722 | #endif |
24eab124 | 2723 | ) |
252b5132 | 2724 | { |
4c63da97 | 2725 | #ifdef BFD_ASSEMBLER |
d0b47220 | 2726 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
4c63da97 | 2727 | #else |
d0b47220 | 2728 | as_bad (_("unimplemented segment type %d in operand"), exp_seg); |
4c63da97 | 2729 | #endif |
252b5132 RH |
2730 | return 0; |
2731 | } | |
2732 | #endif | |
2733 | else | |
2734 | { | |
2735 | /* This is an address. The size of the address will be | |
24eab124 AM |
2736 | determined later, depending on destination register, |
2737 | suffix, or the default for the section. We exclude | |
2738 | Imm8S here so that `push $foo' and other instructions | |
2739 | with an Imm8S form will use Imm16 or Imm32. */ | |
252b5132 RH |
2740 | i.types[this_operand] |= (Imm8 | Imm16 | Imm32); |
2741 | } | |
2742 | ||
2743 | return 1; | |
2744 | } | |
2745 | ||
2746 | static int i386_scale PARAMS ((char *)); | |
2747 | ||
2748 | static int | |
2749 | i386_scale (scale) | |
2750 | char *scale; | |
2751 | { | |
2752 | if (!isdigit (*scale)) | |
2753 | goto bad_scale; | |
2754 | ||
2755 | switch (*scale) | |
2756 | { | |
2757 | case '0': | |
2758 | case '1': | |
2759 | i.log2_scale_factor = 0; | |
2760 | break; | |
2761 | case '2': | |
2762 | i.log2_scale_factor = 1; | |
2763 | break; | |
2764 | case '4': | |
2765 | i.log2_scale_factor = 2; | |
2766 | break; | |
2767 | case '8': | |
2768 | i.log2_scale_factor = 3; | |
2769 | break; | |
2770 | default: | |
2771 | bad_scale: | |
2772 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
24eab124 | 2773 | scale); |
252b5132 RH |
2774 | return 0; |
2775 | } | |
2776 | if (i.log2_scale_factor != 0 && ! i.index_reg) | |
2777 | { | |
2778 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 2779 | 1 << i.log2_scale_factor); |
252b5132 RH |
2780 | #if SCALE1_WHEN_NO_INDEX |
2781 | i.log2_scale_factor = 0; | |
2782 | #endif | |
2783 | } | |
2784 | return 1; | |
2785 | } | |
2786 | ||
2787 | static int i386_displacement PARAMS ((char *, char *)); | |
2788 | ||
2789 | static int | |
2790 | i386_displacement (disp_start, disp_end) | |
2791 | char *disp_start; | |
2792 | char *disp_end; | |
2793 | { | |
2794 | register expressionS *exp; | |
2795 | segT exp_seg = 0; | |
2796 | char *save_input_line_pointer; | |
2797 | int bigdisp = Disp32; | |
2798 | ||
252b5132 RH |
2799 | if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0)) |
2800 | bigdisp = Disp16; | |
2801 | i.types[this_operand] |= bigdisp; | |
2802 | ||
2803 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 2804 | i.op[this_operand].disps = exp; |
252b5132 RH |
2805 | i.disp_operands++; |
2806 | save_input_line_pointer = input_line_pointer; | |
2807 | input_line_pointer = disp_start; | |
2808 | END_STRING_AND_SAVE (disp_end); | |
2809 | ||
2810 | #ifndef GCC_ASM_O_HACK | |
2811 | #define GCC_ASM_O_HACK 0 | |
2812 | #endif | |
2813 | #if GCC_ASM_O_HACK | |
2814 | END_STRING_AND_SAVE (disp_end + 1); | |
2815 | if ((i.types[this_operand] & BaseIndex) != 0 | |
24eab124 | 2816 | && displacement_string_end[-1] == '+') |
252b5132 RH |
2817 | { |
2818 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
2819 | constraint within gcc asm statements. |
2820 | For instance: | |
2821 | ||
2822 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
2823 | __asm__ __volatile__ ( \ | |
2824 | "movw %w2,%0\n\t" \ | |
2825 | "movw %w1,2+%0\n\t" \ | |
2826 | "rorl $16,%1\n\t" \ | |
2827 | "movb %b1,4+%0\n\t" \ | |
2828 | "movb %4,5+%0\n\t" \ | |
2829 | "movb $0,6+%0\n\t" \ | |
2830 | "movb %h1,7+%0\n\t" \ | |
2831 | "rorl $16,%1" \ | |
2832 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
2833 | ||
2834 | This works great except that the output assembler ends | |
2835 | up looking a bit weird if it turns out that there is | |
2836 | no offset. You end up producing code that looks like: | |
2837 | ||
2838 | #APP | |
2839 | movw $235,(%eax) | |
2840 | movw %dx,2+(%eax) | |
2841 | rorl $16,%edx | |
2842 | movb %dl,4+(%eax) | |
2843 | movb $137,5+(%eax) | |
2844 | movb $0,6+(%eax) | |
2845 | movb %dh,7+(%eax) | |
2846 | rorl $16,%edx | |
2847 | #NO_APP | |
2848 | ||
2849 | So here we provide the missing zero. | |
2850 | */ | |
2851 | ||
2852 | *displacement_string_end = '0'; | |
252b5132 RH |
2853 | } |
2854 | #endif | |
2855 | #ifndef LEX_AT | |
24eab124 AM |
2856 | { |
2857 | /* | |
2858 | * We can have operands of the form | |
2859 | * <symbol>@GOTOFF+<nnn> | |
2860 | * Take the easy way out here and copy everything | |
2861 | * into a temporary buffer... | |
2862 | */ | |
2863 | register char *cp; | |
2864 | ||
2865 | cp = strchr (input_line_pointer, '@'); | |
2866 | if (cp != NULL) | |
2867 | { | |
2868 | char *tmpbuf; | |
2869 | int len = 0; | |
2870 | int first; | |
2871 | ||
2872 | /* GOT relocations are not supported in 16 bit mode */ | |
2873 | if (flag_16bit_code) | |
2874 | as_bad (_("GOT relocations not supported in 16 bit mode")); | |
2875 | ||
2876 | if (GOT_symbol == NULL) | |
2877 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
2878 | ||
2879 | if (strncmp (cp + 1, "PLT", 3) == 0) | |
2880 | { | |
2881 | i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32; | |
2882 | len = 3; | |
2883 | } | |
2884 | else if (strncmp (cp + 1, "GOTOFF", 6) == 0) | |
2885 | { | |
2886 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF; | |
2887 | len = 6; | |
2888 | } | |
2889 | else if (strncmp (cp + 1, "GOT", 3) == 0) | |
2890 | { | |
2891 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32; | |
2892 | len = 3; | |
2893 | } | |
2894 | else | |
d0b47220 | 2895 | as_bad (_("bad reloc specifier in expression")); |
24eab124 AM |
2896 | |
2897 | /* Replace the relocation token with ' ', so that errors like | |
2898 | foo@GOTOFF1 will be detected. */ | |
2899 | first = cp - input_line_pointer; | |
2900 | tmpbuf = (char *) alloca (strlen(input_line_pointer)); | |
2901 | memcpy (tmpbuf, input_line_pointer, first); | |
2902 | tmpbuf[first] = ' '; | |
2903 | strcpy (tmpbuf + first + 1, cp + 1 + len); | |
2904 | input_line_pointer = tmpbuf; | |
2905 | } | |
2906 | } | |
252b5132 RH |
2907 | #endif |
2908 | ||
24eab124 | 2909 | exp_seg = expression (exp); |
252b5132 RH |
2910 | |
2911 | #ifdef BFD_ASSEMBLER | |
24eab124 AM |
2912 | /* We do this to make sure that the section symbol is in |
2913 | the symbol table. We will ultimately change the relocation | |
2914 | to be relative to the beginning of the section */ | |
2915 | if (i.disp_reloc[this_operand] == BFD_RELOC_386_GOTOFF) | |
2916 | { | |
2917 | if (S_IS_LOCAL(exp->X_add_symbol) | |
2918 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section) | |
2919 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); | |
2920 | assert (exp->X_op == O_symbol); | |
2921 | exp->X_op = O_subtract; | |
2922 | exp->X_op_symbol = GOT_symbol; | |
2923 | i.disp_reloc[this_operand] = BFD_RELOC_32; | |
2924 | } | |
252b5132 RH |
2925 | #endif |
2926 | ||
24eab124 AM |
2927 | SKIP_WHITESPACE (); |
2928 | if (*input_line_pointer) | |
d0b47220 | 2929 | as_bad (_("ignoring junk `%s' after expression"), |
24eab124 | 2930 | input_line_pointer); |
252b5132 | 2931 | #if GCC_ASM_O_HACK |
24eab124 | 2932 | RESTORE_END_STRING (disp_end + 1); |
252b5132 | 2933 | #endif |
24eab124 AM |
2934 | RESTORE_END_STRING (disp_end); |
2935 | input_line_pointer = save_input_line_pointer; | |
2936 | ||
2daf4fd8 AM |
2937 | if (exp->X_op == O_absent || exp->X_op == O_big) |
2938 | { | |
2939 | /* missing or bad expr becomes absolute 0 */ | |
d0b47220 | 2940 | as_bad (_("missing or invalid displacement expression `%s' taken as 0"), |
2daf4fd8 AM |
2941 | disp_start); |
2942 | exp->X_op = O_constant; | |
2943 | exp->X_add_number = 0; | |
2944 | exp->X_add_symbol = (symbolS *) 0; | |
2945 | exp->X_op_symbol = (symbolS *) 0; | |
2946 | } | |
2947 | ||
4c63da97 | 2948 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
45288df1 | 2949 | if (exp->X_op != O_constant |
4c63da97 | 2950 | #ifdef BFD_ASSEMBLER |
45288df1 | 2951 | && OUTPUT_FLAVOR == bfd_target_aout_flavour |
4c63da97 | 2952 | #endif |
45288df1 AM |
2953 | && exp_seg != text_section |
2954 | && exp_seg != data_section | |
2955 | && exp_seg != bss_section | |
2956 | && exp_seg != undefined_section) | |
24eab124 | 2957 | { |
4c63da97 | 2958 | #ifdef BFD_ASSEMBLER |
d0b47220 | 2959 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
4c63da97 | 2960 | #else |
d0b47220 | 2961 | as_bad (_("unimplemented segment type %d in operand"), exp_seg); |
4c63da97 | 2962 | #endif |
24eab124 AM |
2963 | return 0; |
2964 | } | |
252b5132 RH |
2965 | #endif |
2966 | return 1; | |
2967 | } | |
2968 | ||
2969 | static int i386_operand_modifier PARAMS ((char **, int)); | |
2970 | ||
2971 | static int | |
2972 | i386_operand_modifier (op_string, got_a_float) | |
2973 | char **op_string; | |
2974 | int got_a_float; | |
2975 | { | |
24eab124 AM |
2976 | if (!strncasecmp (*op_string, "BYTE PTR", 8)) |
2977 | { | |
2978 | i.suffix = BYTE_MNEM_SUFFIX; | |
2979 | *op_string += 8; | |
2980 | return BYTE_PTR; | |
252b5132 | 2981 | |
24eab124 AM |
2982 | } |
2983 | else if (!strncasecmp (*op_string, "WORD PTR", 8)) | |
2984 | { | |
cc5ca5ce AM |
2985 | if (got_a_float == 2) /* "fi..." */ |
2986 | i.suffix = SHORT_MNEM_SUFFIX; | |
2987 | else | |
2988 | i.suffix = WORD_MNEM_SUFFIX; | |
24eab124 AM |
2989 | *op_string += 8; |
2990 | return WORD_PTR; | |
2991 | } | |
252b5132 | 2992 | |
24eab124 AM |
2993 | else if (!strncasecmp (*op_string, "DWORD PTR", 9)) |
2994 | { | |
cc5ca5ce | 2995 | if (got_a_float == 1) /* "f..." */ |
24eab124 AM |
2996 | i.suffix = SHORT_MNEM_SUFFIX; |
2997 | else | |
add0c677 | 2998 | i.suffix = LONG_MNEM_SUFFIX; |
24eab124 AM |
2999 | *op_string += 9; |
3000 | return DWORD_PTR; | |
3001 | } | |
252b5132 | 3002 | |
24eab124 AM |
3003 | else if (!strncasecmp (*op_string, "QWORD PTR", 9)) |
3004 | { | |
add0c677 | 3005 | i.suffix = DWORD_MNEM_SUFFIX; |
24eab124 AM |
3006 | *op_string += 9; |
3007 | return QWORD_PTR; | |
3008 | } | |
252b5132 | 3009 | |
24eab124 AM |
3010 | else if (!strncasecmp (*op_string, "XWORD PTR", 9)) |
3011 | { | |
3012 | i.suffix = LONG_DOUBLE_MNEM_SUFFIX; | |
3013 | *op_string += 9; | |
3014 | return XWORD_PTR; | |
3015 | } | |
252b5132 | 3016 | |
24eab124 AM |
3017 | else if (!strncasecmp (*op_string, "SHORT", 5)) |
3018 | { | |
3019 | *op_string += 5; | |
3020 | return SHORT; | |
3021 | } | |
252b5132 | 3022 | |
24eab124 AM |
3023 | else if (!strncasecmp (*op_string, "OFFSET FLAT:", 12)) |
3024 | { | |
3025 | *op_string += 12; | |
3026 | return OFFSET_FLAT; | |
3027 | } | |
252b5132 | 3028 | |
24eab124 AM |
3029 | else if (!strncasecmp (*op_string, "FLAT", 4)) |
3030 | { | |
3031 | *op_string += 4; | |
3032 | return FLAT; | |
3033 | } | |
252b5132 | 3034 | |
24eab124 | 3035 | else return NONE_FOUND; |
c3332e24 | 3036 | } |
252b5132 RH |
3037 | |
3038 | static char * build_displacement_string PARAMS ((int, char *)); | |
3039 | ||
3040 | static char * | |
3041 | build_displacement_string (initial_disp, op_string) | |
3042 | int initial_disp; | |
3043 | char *op_string; | |
3044 | { | |
3045 | char *temp_string = (char *) malloc (strlen (op_string) + 1); | |
3046 | char *end_of_operand_string; | |
3047 | char *tc; | |
3048 | char *temp_disp; | |
3049 | ||
3050 | temp_string[0] = '\0'; | |
3051 | tc = end_of_operand_string = strchr (op_string, '['); | |
36bf8ab9 | 3052 | if (initial_disp && !end_of_operand_string) |
252b5132 RH |
3053 | { |
3054 | strcpy (temp_string, op_string); | |
36bf8ab9 | 3055 | return temp_string; |
252b5132 RH |
3056 | } |
3057 | ||
3058 | /* Build the whole displacement string */ | |
3059 | if (initial_disp) | |
3060 | { | |
3061 | strncpy (temp_string, op_string, end_of_operand_string - op_string); | |
3062 | temp_string[end_of_operand_string - op_string] = '\0'; | |
3063 | temp_disp = tc; | |
3064 | } | |
c3332e24 | 3065 | else |
252b5132 RH |
3066 | temp_disp = op_string; |
3067 | ||
3068 | while (*temp_disp != '\0') | |
3069 | { | |
af6bdddf | 3070 | char *end_op; |
252b5132 RH |
3071 | int add_minus = (*temp_disp == '-'); |
3072 | ||
3073 | if (*temp_disp == '+' || *temp_disp == '-' || *temp_disp == '[') | |
24eab124 | 3074 | temp_disp++; |
252b5132 RH |
3075 | |
3076 | if (is_space_char (*temp_disp)) | |
24eab124 | 3077 | temp_disp++; |
252b5132 RH |
3078 | |
3079 | /* Don't consider registers */ | |
af6bdddf AM |
3080 | if ( !((*temp_disp == REGISTER_PREFIX || allow_naked_reg) |
3081 | && parse_register (temp_disp, &end_op)) ) | |
24eab124 AM |
3082 | { |
3083 | char *string_start = temp_disp; | |
3084 | ||
3085 | while (*temp_disp != ']' | |
3086 | && *temp_disp != '+' | |
3087 | && *temp_disp != '-' | |
3088 | && *temp_disp != '*') | |
3089 | ++temp_disp; | |
3090 | ||
3091 | if (add_minus) | |
3092 | strcat (temp_string, "-"); | |
3093 | else | |
3094 | strcat (temp_string, "+"); | |
3095 | ||
3096 | strncat (temp_string, string_start, temp_disp - string_start); | |
3097 | if (*temp_disp == '+' || *temp_disp == '-') | |
3098 | --temp_disp; | |
3099 | } | |
252b5132 RH |
3100 | |
3101 | while (*temp_disp != '\0' | |
24eab124 AM |
3102 | && *temp_disp != '+' |
3103 | && *temp_disp != '-') | |
3104 | ++temp_disp; | |
252b5132 RH |
3105 | } |
3106 | ||
3107 | return temp_string; | |
3108 | } | |
3109 | ||
3110 | static int i386_parse_seg PARAMS ((char *)); | |
3111 | ||
3112 | static int | |
3113 | i386_parse_seg (op_string) | |
3114 | char *op_string; | |
3115 | { | |
3116 | if (is_space_char (*op_string)) | |
3117 | ++op_string; | |
3118 | ||
3119 | /* Should be one of es, cs, ss, ds fs or gs */ | |
3120 | switch (*op_string++) | |
3121 | { | |
3122 | case 'e': | |
3123 | i.seg[i.mem_operands] = &es; | |
3124 | break; | |
3125 | case 'c': | |
3126 | i.seg[i.mem_operands] = &cs; | |
3127 | break; | |
3128 | case 's': | |
3129 | i.seg[i.mem_operands] = &ss; | |
3130 | break; | |
3131 | case 'd': | |
3132 | i.seg[i.mem_operands] = &ds; | |
3133 | break; | |
3134 | case 'f': | |
3135 | i.seg[i.mem_operands] = &fs; | |
3136 | break; | |
3137 | case 'g': | |
3138 | i.seg[i.mem_operands] = &gs; | |
3139 | break; | |
3140 | default: | |
3141 | as_bad (_("bad segment name `%s'"), op_string); | |
3142 | return 0; | |
3143 | } | |
3144 | ||
3145 | if (*op_string++ != 's') | |
3146 | { | |
24eab124 AM |
3147 | as_bad (_("bad segment name `%s'"), op_string); |
3148 | return 0; | |
252b5132 RH |
3149 | } |
3150 | ||
3151 | if (is_space_char (*op_string)) | |
3152 | ++op_string; | |
3153 | ||
3154 | if (*op_string != ':') | |
3155 | { | |
24eab124 AM |
3156 | as_bad (_("bad segment name `%s'"), op_string); |
3157 | return 0; | |
252b5132 RH |
3158 | } |
3159 | ||
c3332e24 AM |
3160 | return 1; |
3161 | ||
252b5132 RH |
3162 | } |
3163 | ||
eecb386c | 3164 | static int i386_index_check PARAMS((const char *)); |
252b5132 | 3165 | |
eecb386c AM |
3166 | /* Make sure the memory operand we've been dealt is valid. |
3167 | Returns 1 on success, 0 on a failure. | |
3168 | */ | |
252b5132 | 3169 | static int |
eecb386c AM |
3170 | i386_index_check (operand_string) |
3171 | const char *operand_string; | |
252b5132 | 3172 | { |
24eab124 | 3173 | #if INFER_ADDR_PREFIX |
eecb386c AM |
3174 | int fudged = 0; |
3175 | ||
24eab124 AM |
3176 | tryprefix: |
3177 | #endif | |
d0b47220 | 3178 | if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0) |
24eab124 | 3179 | /* 16 bit mode checks */ |
d0b47220 AM |
3180 | ? ((i.base_reg |
3181 | && ((i.base_reg->reg_type & (Reg16|BaseIndex)) | |
3182 | != (Reg16|BaseIndex))) | |
3183 | || (i.index_reg | |
3184 | && (((i.index_reg->reg_type & (Reg16|BaseIndex)) | |
3185 | != (Reg16|BaseIndex)) | |
3186 | || ! (i.base_reg | |
3187 | && i.base_reg->reg_num < 6 | |
3188 | && i.index_reg->reg_num >= 6 | |
3189 | && i.log2_scale_factor == 0)))) | |
24eab124 | 3190 | /* 32 bit mode checks */ |
d0b47220 AM |
3191 | : ((i.base_reg |
3192 | && (i.base_reg->reg_type & Reg32) == 0) | |
3193 | || (i.index_reg | |
3194 | && ((i.index_reg->reg_type & (Reg32|BaseIndex)) | |
3195 | != (Reg32|BaseIndex))))) | |
24eab124 AM |
3196 | { |
3197 | #if INFER_ADDR_PREFIX | |
eecb386c | 3198 | if (i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0') |
24eab124 AM |
3199 | { |
3200 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
3201 | i.prefixes += 1; | |
b23bac36 AM |
3202 | /* Change the size of any displacement too. At most one of |
3203 | Disp16 or Disp32 is set. | |
3204 | FIXME. There doesn't seem to be any real need for separate | |
3205 | Disp16 and Disp32 flags. The same goes for Imm16 and Imm32. | |
3206 | Removing them would probably clean up the code quite a lot. | |
3207 | */ | |
3208 | if (i.types[this_operand] & (Disp16|Disp32)) | |
3209 | i.types[this_operand] ^= (Disp16|Disp32); | |
eecb386c | 3210 | fudged = 1; |
24eab124 AM |
3211 | goto tryprefix; |
3212 | } | |
eecb386c AM |
3213 | if (fudged) |
3214 | as_bad (_("`%s' is not a valid base/index expression"), | |
3215 | operand_string); | |
3216 | else | |
c388dee8 | 3217 | #endif |
eecb386c AM |
3218 | as_bad (_("`%s' is not a valid %s bit base/index expression"), |
3219 | operand_string, | |
3220 | flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0) ? "16" : "32"); | |
3221 | return 0; | |
24eab124 AM |
3222 | } |
3223 | return 1; | |
3224 | } | |
252b5132 | 3225 | |
24eab124 AM |
3226 | static int i386_intel_memory_operand PARAMS ((char *)); |
3227 | ||
3228 | static int | |
3229 | i386_intel_memory_operand (operand_string) | |
3230 | char *operand_string; | |
3231 | { | |
3232 | char *op_string = operand_string; | |
252b5132 RH |
3233 | char *end_of_operand_string; |
3234 | ||
24eab124 AM |
3235 | if ((i.mem_operands == 1 |
3236 | && (current_templates->start->opcode_modifier & IsString) == 0) | |
3237 | || i.mem_operands == 2) | |
252b5132 | 3238 | { |
24eab124 AM |
3239 | as_bad (_("too many memory references for `%s'"), |
3240 | current_templates->start->name); | |
3241 | return 0; | |
252b5132 RH |
3242 | } |
3243 | ||
36bf8ab9 | 3244 | /* First check for a segment override. */ |
252b5132 RH |
3245 | if (*op_string != '[') |
3246 | { | |
3247 | char *end_seg; | |
252b5132 RH |
3248 | |
3249 | end_seg = strchr (op_string, ':'); | |
3250 | if (end_seg) | |
24eab124 AM |
3251 | { |
3252 | if (!i386_parse_seg (op_string)) | |
3253 | return 0; | |
3254 | op_string = end_seg + 1; | |
3255 | } | |
36bf8ab9 | 3256 | } |
252b5132 | 3257 | |
36bf8ab9 AM |
3258 | /* Look for displacement preceding open bracket */ |
3259 | if (*op_string != '[') | |
3260 | { | |
3261 | char *temp_string; | |
24eab124 | 3262 | |
36bf8ab9 | 3263 | if (i.disp_operands) |
24eab124 | 3264 | return 0; |
252b5132 | 3265 | |
36bf8ab9 AM |
3266 | temp_string = build_displacement_string (true, op_string); |
3267 | ||
3268 | if (!i386_displacement (temp_string, temp_string + strlen (temp_string))) | |
3269 | { | |
3270 | free (temp_string); | |
3271 | return 0; | |
3272 | } | |
3273 | free (temp_string); | |
3274 | ||
252b5132 RH |
3275 | end_of_operand_string = strchr (op_string, '['); |
3276 | if (!end_of_operand_string) | |
24eab124 | 3277 | end_of_operand_string = op_string + strlen (op_string); |
252b5132 RH |
3278 | |
3279 | if (is_space_char (*end_of_operand_string)) | |
24eab124 | 3280 | --end_of_operand_string; |
252b5132 RH |
3281 | |
3282 | op_string = end_of_operand_string; | |
24eab124 | 3283 | } |
252b5132 RH |
3284 | |
3285 | if (*op_string == '[') | |
3286 | { | |
3287 | ++op_string; | |
3288 | ||
3289 | /* Pick off each component and figure out where it belongs */ | |
3290 | ||
3291 | end_of_operand_string = op_string; | |
3292 | ||
3293 | while (*op_string != ']') | |
24eab124 | 3294 | { |
af6bdddf AM |
3295 | const reg_entry *temp_reg; |
3296 | char *end_op; | |
3297 | char *temp_string; | |
24eab124 AM |
3298 | |
3299 | while (*end_of_operand_string != '+' | |
3300 | && *end_of_operand_string != '-' | |
3301 | && *end_of_operand_string != '*' | |
3302 | && *end_of_operand_string != ']') | |
3303 | end_of_operand_string++; | |
3304 | ||
af6bdddf AM |
3305 | temp_string = op_string; |
3306 | if (*temp_string == '+') | |
24eab124 | 3307 | { |
af6bdddf | 3308 | ++temp_string; |
24eab124 AM |
3309 | if (is_space_char (*temp_string)) |
3310 | ++temp_string; | |
24eab124 AM |
3311 | } |
3312 | ||
af6bdddf AM |
3313 | if ((*temp_string == REGISTER_PREFIX || allow_naked_reg) |
3314 | && (temp_reg = parse_register (temp_string, &end_op)) != NULL) | |
24eab124 | 3315 | { |
24eab124 AM |
3316 | if (i.base_reg == NULL) |
3317 | i.base_reg = temp_reg; | |
3318 | else | |
3319 | i.index_reg = temp_reg; | |
3320 | ||
3321 | i.types[this_operand] |= BaseIndex; | |
24eab124 | 3322 | } |
af6bdddf | 3323 | else if (*temp_string == REGISTER_PREFIX) |
24eab124 | 3324 | { |
af6bdddf AM |
3325 | as_bad (_("bad register name `%s'"), temp_string); |
3326 | return 0; | |
3327 | } | |
3328 | else if (is_digit_char (*op_string) | |
3329 | || *op_string == '+' || *op_string == '-') | |
3330 | { | |
36bf8ab9 AM |
3331 | char *temp_str; |
3332 | ||
3333 | if (i.disp_operands != 0) | |
3334 | return 0; | |
3335 | ||
af6bdddf | 3336 | temp_string = build_displacement_string (false, op_string); |
24eab124 | 3337 | |
36bf8ab9 AM |
3338 | temp_str = temp_string; |
3339 | if (*temp_str == '+') | |
3340 | ++temp_str; | |
24eab124 | 3341 | |
36bf8ab9 AM |
3342 | if (!i386_displacement (temp_str, temp_str + strlen (temp_str))) |
3343 | { | |
3344 | free (temp_string); | |
3345 | return 0; | |
3346 | } | |
3347 | free (temp_string); | |
24eab124 AM |
3348 | |
3349 | ++op_string; | |
3350 | end_of_operand_string = op_string; | |
3351 | while (*end_of_operand_string != ']' | |
3352 | && *end_of_operand_string != '+' | |
3353 | && *end_of_operand_string != '-' | |
3354 | && *end_of_operand_string != '*') | |
3355 | ++end_of_operand_string; | |
3356 | } | |
3357 | else if (*op_string == '*') | |
3358 | { | |
3359 | ++op_string; | |
3360 | ||
3361 | if (i.base_reg && !i.index_reg) | |
3362 | { | |
3363 | i.index_reg = i.base_reg; | |
3364 | i.base_reg = 0; | |
3365 | } | |
3366 | ||
3367 | if (!i386_scale (op_string)) | |
3368 | return 0; | |
3369 | } | |
3370 | op_string = end_of_operand_string; | |
3371 | ++end_of_operand_string; | |
3372 | } | |
3373 | } | |
3374 | ||
eecb386c AM |
3375 | if (i386_index_check (operand_string) == 0) |
3376 | return 0; | |
252b5132 | 3377 | |
24eab124 | 3378 | i.mem_operands++; |
252b5132 RH |
3379 | return 1; |
3380 | } | |
3381 | ||
252b5132 RH |
3382 | static int |
3383 | i386_intel_operand (operand_string, got_a_float) | |
3384 | char *operand_string; | |
3385 | int got_a_float; | |
3386 | { | |
af6bdddf AM |
3387 | const reg_entry * r; |
3388 | char *end_op; | |
252b5132 RH |
3389 | char *op_string = operand_string; |
3390 | ||
3391 | int operand_modifier = i386_operand_modifier (&op_string, got_a_float); | |
3392 | if (is_space_char (*op_string)) | |
3393 | ++op_string; | |
3394 | ||
3395 | switch (operand_modifier) | |
3396 | { | |
3397 | case BYTE_PTR: | |
3398 | case WORD_PTR: | |
3399 | case DWORD_PTR: | |
3400 | case QWORD_PTR: | |
3401 | case XWORD_PTR: | |
252b5132 | 3402 | if (!i386_intel_memory_operand (op_string)) |
24eab124 | 3403 | return 0; |
252b5132 RH |
3404 | break; |
3405 | ||
3406 | case FLAT: | |
252b5132 RH |
3407 | case OFFSET_FLAT: |
3408 | if (!i386_immediate (op_string)) | |
24eab124 | 3409 | return 0; |
252b5132 RH |
3410 | break; |
3411 | ||
3412 | case SHORT: | |
252b5132 | 3413 | case NONE_FOUND: |
c3332e24 AM |
3414 | /* Should be register or immediate */ |
3415 | if (is_digit_char (*op_string) | |
3416 | && strchr (op_string, '[') == 0) | |
3417 | { | |
3418 | if (!i386_immediate (op_string)) | |
3419 | return 0; | |
3420 | } | |
af6bdddf AM |
3421 | else if ((*op_string == REGISTER_PREFIX || allow_naked_reg) |
3422 | && (r = parse_register (op_string, &end_op)) != NULL) | |
c3332e24 | 3423 | { |
c3332e24 AM |
3424 | /* Check for a segment override by searching for ':' after a |
3425 | segment register. */ | |
3426 | op_string = end_op; | |
3427 | if (is_space_char (*op_string)) | |
3428 | ++op_string; | |
3429 | if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3))) | |
3430 | { | |
3431 | switch (r->reg_num) | |
3432 | { | |
3433 | case 0: | |
3434 | i.seg[i.mem_operands] = &es; | |
3435 | break; | |
3436 | case 1: | |
3437 | i.seg[i.mem_operands] = &cs; | |
3438 | break; | |
3439 | case 2: | |
3440 | i.seg[i.mem_operands] = &ss; | |
3441 | break; | |
3442 | case 3: | |
3443 | i.seg[i.mem_operands] = &ds; | |
3444 | break; | |
3445 | case 4: | |
3446 | i.seg[i.mem_operands] = &fs; | |
3447 | break; | |
3448 | case 5: | |
3449 | i.seg[i.mem_operands] = &gs; | |
3450 | break; | |
3451 | } | |
252b5132 | 3452 | |
c3332e24 AM |
3453 | } |
3454 | i.types[this_operand] |= r->reg_type & ~BaseIndex; | |
520dc8e8 | 3455 | i.op[this_operand].regs = r; |
c3332e24 AM |
3456 | i.reg_operands++; |
3457 | } | |
af6bdddf | 3458 | else if (*op_string == REGISTER_PREFIX) |
c3332e24 | 3459 | { |
af6bdddf AM |
3460 | as_bad (_("bad register name `%s'"), op_string); |
3461 | return 0; | |
c3332e24 | 3462 | } |
af6bdddf AM |
3463 | else if (!i386_intel_memory_operand (op_string)) |
3464 | return 0; | |
3465 | ||
c3332e24 | 3466 | break; |
c3332e24 | 3467 | } /* end switch */ |
24eab124 | 3468 | |
252b5132 RH |
3469 | return 1; |
3470 | } | |
3471 | ||
3472 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero | |
3473 | on error. */ | |
3474 | ||
252b5132 RH |
3475 | static int |
3476 | i386_operand (operand_string) | |
3477 | char *operand_string; | |
3478 | { | |
af6bdddf AM |
3479 | const reg_entry *r; |
3480 | char *end_op; | |
24eab124 | 3481 | char *op_string = operand_string; |
252b5132 | 3482 | |
24eab124 | 3483 | if (is_space_char (*op_string)) |
252b5132 RH |
3484 | ++op_string; |
3485 | ||
24eab124 AM |
3486 | /* We check for an absolute prefix (differentiating, |
3487 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ | |
3488 | if (*op_string == ABSOLUTE_PREFIX) | |
3489 | { | |
3490 | ++op_string; | |
3491 | if (is_space_char (*op_string)) | |
3492 | ++op_string; | |
3493 | i.types[this_operand] |= JumpAbsolute; | |
3494 | } | |
252b5132 | 3495 | |
24eab124 | 3496 | /* Check if operand is a register. */ |
af6bdddf AM |
3497 | if ((*op_string == REGISTER_PREFIX || allow_naked_reg) |
3498 | && (r = parse_register (op_string, &end_op)) != NULL) | |
24eab124 | 3499 | { |
24eab124 AM |
3500 | /* Check for a segment override by searching for ':' after a |
3501 | segment register. */ | |
3502 | op_string = end_op; | |
3503 | if (is_space_char (*op_string)) | |
3504 | ++op_string; | |
3505 | if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3))) | |
3506 | { | |
3507 | switch (r->reg_num) | |
3508 | { | |
3509 | case 0: | |
3510 | i.seg[i.mem_operands] = &es; | |
3511 | break; | |
3512 | case 1: | |
3513 | i.seg[i.mem_operands] = &cs; | |
3514 | break; | |
3515 | case 2: | |
3516 | i.seg[i.mem_operands] = &ss; | |
3517 | break; | |
3518 | case 3: | |
3519 | i.seg[i.mem_operands] = &ds; | |
3520 | break; | |
3521 | case 4: | |
3522 | i.seg[i.mem_operands] = &fs; | |
3523 | break; | |
3524 | case 5: | |
3525 | i.seg[i.mem_operands] = &gs; | |
3526 | break; | |
3527 | } | |
252b5132 | 3528 | |
24eab124 | 3529 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
3530 | ++op_string; |
3531 | if (is_space_char (*op_string)) | |
24eab124 | 3532 | ++op_string; |
252b5132 | 3533 | |
24eab124 AM |
3534 | if (!is_digit_char (*op_string) |
3535 | && !is_identifier_char (*op_string) | |
3536 | && *op_string != '(' | |
3537 | && *op_string != ABSOLUTE_PREFIX) | |
3538 | { | |
3539 | as_bad (_("bad memory operand `%s'"), op_string); | |
3540 | return 0; | |
3541 | } | |
3542 | /* Handle case of %es:*foo. */ | |
3543 | if (*op_string == ABSOLUTE_PREFIX) | |
3544 | { | |
3545 | ++op_string; | |
3546 | if (is_space_char (*op_string)) | |
3547 | ++op_string; | |
3548 | i.types[this_operand] |= JumpAbsolute; | |
3549 | } | |
3550 | goto do_memory_reference; | |
3551 | } | |
3552 | if (*op_string) | |
3553 | { | |
d0b47220 | 3554 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
3555 | return 0; |
3556 | } | |
3557 | i.types[this_operand] |= r->reg_type & ~BaseIndex; | |
520dc8e8 | 3558 | i.op[this_operand].regs = r; |
24eab124 AM |
3559 | i.reg_operands++; |
3560 | } | |
af6bdddf AM |
3561 | else if (*op_string == REGISTER_PREFIX) |
3562 | { | |
3563 | as_bad (_("bad register name `%s'"), op_string); | |
3564 | return 0; | |
3565 | } | |
24eab124 AM |
3566 | else if (*op_string == IMMEDIATE_PREFIX) |
3567 | { /* ... or an immediate */ | |
3568 | ++op_string; | |
3569 | if (i.types[this_operand] & JumpAbsolute) | |
3570 | { | |
d0b47220 | 3571 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
3572 | return 0; |
3573 | } | |
3574 | if (!i386_immediate (op_string)) | |
3575 | return 0; | |
3576 | } | |
3577 | else if (is_digit_char (*op_string) | |
3578 | || is_identifier_char (*op_string) | |
3579 | || *op_string == '(' ) | |
3580 | { | |
3581 | /* This is a memory reference of some sort. */ | |
af6bdddf | 3582 | char *base_string; |
252b5132 | 3583 | |
24eab124 | 3584 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
3585 | char *displacement_string_start; |
3586 | char *displacement_string_end; | |
252b5132 | 3587 | |
24eab124 | 3588 | do_memory_reference: |
24eab124 AM |
3589 | if ((i.mem_operands == 1 |
3590 | && (current_templates->start->opcode_modifier & IsString) == 0) | |
3591 | || i.mem_operands == 2) | |
3592 | { | |
3593 | as_bad (_("too many memory references for `%s'"), | |
3594 | current_templates->start->name); | |
3595 | return 0; | |
3596 | } | |
252b5132 | 3597 | |
24eab124 AM |
3598 | /* Check for base index form. We detect the base index form by |
3599 | looking for an ')' at the end of the operand, searching | |
3600 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
3601 | after the '('. */ | |
af6bdddf | 3602 | base_string = op_string + strlen (op_string); |
c3332e24 | 3603 | |
af6bdddf AM |
3604 | --base_string; |
3605 | if (is_space_char (*base_string)) | |
3606 | --base_string; | |
252b5132 | 3607 | |
af6bdddf AM |
3608 | /* If we only have a displacement, set-up for it to be parsed later. */ |
3609 | displacement_string_start = op_string; | |
3610 | displacement_string_end = base_string + 1; | |
252b5132 | 3611 | |
24eab124 AM |
3612 | if (*base_string == ')') |
3613 | { | |
af6bdddf | 3614 | char *temp_string; |
24eab124 AM |
3615 | unsigned int parens_balanced = 1; |
3616 | /* We've already checked that the number of left & right ()'s are | |
3617 | equal, so this loop will not be infinite. */ | |
3618 | do | |
3619 | { | |
3620 | base_string--; | |
3621 | if (*base_string == ')') | |
3622 | parens_balanced++; | |
3623 | if (*base_string == '(') | |
3624 | parens_balanced--; | |
3625 | } | |
3626 | while (parens_balanced); | |
c3332e24 | 3627 | |
af6bdddf | 3628 | temp_string = base_string; |
c3332e24 | 3629 | |
24eab124 | 3630 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
3631 | ++base_string; |
3632 | if (is_space_char (*base_string)) | |
24eab124 | 3633 | ++base_string; |
252b5132 | 3634 | |
af6bdddf AM |
3635 | if (*base_string == ',' |
3636 | || ((*base_string == REGISTER_PREFIX || allow_naked_reg) | |
3637 | && (i.base_reg = parse_register (base_string, &end_op)) != NULL)) | |
252b5132 | 3638 | { |
af6bdddf | 3639 | displacement_string_end = temp_string; |
252b5132 | 3640 | |
af6bdddf | 3641 | i.types[this_operand] |= BaseIndex; |
252b5132 | 3642 | |
af6bdddf | 3643 | if (i.base_reg) |
24eab124 | 3644 | { |
24eab124 AM |
3645 | base_string = end_op; |
3646 | if (is_space_char (*base_string)) | |
3647 | ++base_string; | |
af6bdddf AM |
3648 | } |
3649 | ||
3650 | /* There may be an index reg or scale factor here. */ | |
3651 | if (*base_string == ',') | |
3652 | { | |
3653 | ++base_string; | |
3654 | if (is_space_char (*base_string)) | |
3655 | ++base_string; | |
3656 | ||
3657 | if ((*base_string == REGISTER_PREFIX || allow_naked_reg) | |
3658 | && (i.index_reg = parse_register (base_string, &end_op)) != NULL) | |
24eab124 | 3659 | { |
af6bdddf | 3660 | base_string = end_op; |
24eab124 AM |
3661 | if (is_space_char (*base_string)) |
3662 | ++base_string; | |
af6bdddf AM |
3663 | if (*base_string == ',') |
3664 | { | |
3665 | ++base_string; | |
3666 | if (is_space_char (*base_string)) | |
3667 | ++base_string; | |
3668 | } | |
3669 | else if (*base_string != ')' ) | |
3670 | { | |
3671 | as_bad (_("expecting `,' or `)' after index register in `%s'"), | |
3672 | operand_string); | |
3673 | return 0; | |
3674 | } | |
24eab124 | 3675 | } |
af6bdddf | 3676 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 3677 | { |
af6bdddf | 3678 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
3679 | return 0; |
3680 | } | |
252b5132 | 3681 | |
af6bdddf AM |
3682 | /* Check for scale factor. */ |
3683 | if (isdigit ((unsigned char) *base_string)) | |
3684 | { | |
3685 | if (!i386_scale (base_string)) | |
3686 | return 0; | |
24eab124 | 3687 | |
af6bdddf AM |
3688 | ++base_string; |
3689 | if (is_space_char (*base_string)) | |
3690 | ++base_string; | |
3691 | if (*base_string != ')') | |
3692 | { | |
3693 | as_bad (_("expecting `)' after scale factor in `%s'"), | |
3694 | operand_string); | |
3695 | return 0; | |
3696 | } | |
3697 | } | |
3698 | else if (!i.index_reg) | |
24eab124 | 3699 | { |
af6bdddf AM |
3700 | as_bad (_("expecting index register or scale factor after `,'; got '%c'"), |
3701 | *base_string); | |
24eab124 AM |
3702 | return 0; |
3703 | } | |
3704 | } | |
af6bdddf | 3705 | else if (*base_string != ')') |
24eab124 | 3706 | { |
af6bdddf AM |
3707 | as_bad (_("expecting `,' or `)' after base register in `%s'"), |
3708 | operand_string); | |
24eab124 AM |
3709 | return 0; |
3710 | } | |
c3332e24 | 3711 | } |
af6bdddf | 3712 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 3713 | { |
af6bdddf | 3714 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 3715 | return 0; |
c3332e24 | 3716 | } |
24eab124 AM |
3717 | } |
3718 | ||
3719 | /* If there's an expression beginning the operand, parse it, | |
3720 | assuming displacement_string_start and | |
3721 | displacement_string_end are meaningful. */ | |
3722 | if (displacement_string_start != displacement_string_end) | |
3723 | { | |
3724 | if (!i386_displacement (displacement_string_start, | |
3725 | displacement_string_end)) | |
3726 | return 0; | |
3727 | } | |
3728 | ||
3729 | /* Special case for (%dx) while doing input/output op. */ | |
3730 | if (i.base_reg | |
3731 | && i.base_reg->reg_type == (Reg16 | InOutPortReg) | |
3732 | && i.index_reg == 0 | |
3733 | && i.log2_scale_factor == 0 | |
3734 | && i.seg[i.mem_operands] == 0 | |
3735 | && (i.types[this_operand] & Disp) == 0) | |
3736 | { | |
3737 | i.types[this_operand] = InOutPortReg; | |
3738 | return 1; | |
3739 | } | |
3740 | ||
eecb386c AM |
3741 | if (i386_index_check (operand_string) == 0) |
3742 | return 0; | |
24eab124 AM |
3743 | i.mem_operands++; |
3744 | } | |
3745 | else | |
3746 | { /* it's not a memory operand; argh! */ | |
3747 | as_bad (_("invalid char %s beginning operand %d `%s'"), | |
3748 | output_invalid (*op_string), | |
3749 | this_operand + 1, | |
3750 | op_string); | |
3751 | return 0; | |
3752 | } | |
3753 | return 1; /* normal return */ | |
252b5132 RH |
3754 | } |
3755 | \f | |
ee7fcc42 AM |
3756 | /* md_estimate_size_before_relax() |
3757 | ||
3758 | Called just before relax() for rs_machine_dependent frags. The x86 | |
3759 | assembler uses these frags to handle variable size jump | |
3760 | instructions. | |
3761 | ||
3762 | Any symbol that is now undefined will not become defined. | |
3763 | Return the correct fr_subtype in the frag. | |
3764 | Return the initial "guess for variable size of frag" to caller. | |
3765 | The guess is actually the growth beyond the fixed part. Whatever | |
3766 | we do to grow the fixed or variable part contributes to our | |
3767 | returned value. */ | |
3768 | ||
252b5132 RH |
3769 | int |
3770 | md_estimate_size_before_relax (fragP, segment) | |
3771 | register fragS *fragP; | |
3772 | register segT segment; | |
3773 | { | |
252b5132 | 3774 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
3775 | check for un-relaxable symbols. On an ELF system, we can't relax |
3776 | an externally visible symbol, because it may be overridden by a | |
3777 | shared library. */ | |
3778 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 3779 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
b98ef147 AM |
3780 | || S_IS_EXTERNAL (fragP->fr_symbol) |
3781 | || S_IS_WEAK (fragP->fr_symbol) | |
3782 | #endif | |
3783 | ) | |
252b5132 | 3784 | { |
b98ef147 AM |
3785 | /* Symbol is undefined in this segment, or we need to keep a |
3786 | reloc so that weak symbols can be overridden. */ | |
3787 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f6af82bd AM |
3788 | #ifdef BFD_ASSEMBLER |
3789 | enum bfd_reloc_code_real reloc_type; | |
3790 | #else | |
3791 | int reloc_type; | |
3792 | #endif | |
ee7fcc42 AM |
3793 | unsigned char *opcode; |
3794 | int old_fr_fix; | |
f6af82bd | 3795 | |
ee7fcc42 AM |
3796 | if (fragP->fr_var != NO_RELOC) |
3797 | reloc_type = fragP->fr_var; | |
b98ef147 | 3798 | else if (size == 2) |
f6af82bd AM |
3799 | reloc_type = BFD_RELOC_16_PCREL; |
3800 | else | |
3801 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 3802 | |
ee7fcc42 AM |
3803 | old_fr_fix = fragP->fr_fix; |
3804 | opcode = (unsigned char *) fragP->fr_opcode; | |
3805 | ||
252b5132 RH |
3806 | switch (opcode[0]) |
3807 | { | |
3808 | case JUMP_PC_RELATIVE: /* make jmp (0xeb) a dword displacement jump */ | |
3809 | opcode[0] = 0xe9; /* dword disp jmp */ | |
3810 | fragP->fr_fix += size; | |
3811 | fix_new (fragP, old_fr_fix, size, | |
3812 | fragP->fr_symbol, | |
3813 | fragP->fr_offset, 1, | |
f6af82bd | 3814 | reloc_type); |
252b5132 RH |
3815 | break; |
3816 | ||
3817 | default: | |
24eab124 | 3818 | /* This changes the byte-displacement jump 0x7N |
f6af82bd | 3819 | to the dword-displacement jump 0x0f,0x8N. */ |
252b5132 | 3820 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 3821 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
252b5132 RH |
3822 | fragP->fr_fix += 1 + size; /* we've added an opcode byte */ |
3823 | fix_new (fragP, old_fr_fix + 1, size, | |
3824 | fragP->fr_symbol, | |
3825 | fragP->fr_offset, 1, | |
f6af82bd | 3826 | reloc_type); |
252b5132 RH |
3827 | break; |
3828 | } | |
3829 | frag_wane (fragP); | |
ee7fcc42 | 3830 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 3831 | } |
ee7fcc42 AM |
3832 | return 1; /* Guess a short jump. */ |
3833 | } | |
3834 | ||
252b5132 RH |
3835 | /* |
3836 | * md_convert_frag(); | |
3837 | * | |
3838 | * Called after relax() is finished. | |
3839 | * In: Address of frag. | |
3840 | * fr_type == rs_machine_dependent. | |
3841 | * fr_subtype is what the address relaxed to. | |
3842 | * | |
3843 | * Out: Any fixSs and constants are set up. | |
3844 | * Caller will turn frag into a ".space 0". | |
3845 | */ | |
3846 | #ifndef BFD_ASSEMBLER | |
3847 | void | |
3848 | md_convert_frag (headers, sec, fragP) | |
a04b544b ILT |
3849 | object_headers *headers ATTRIBUTE_UNUSED; |
3850 | segT sec ATTRIBUTE_UNUSED; | |
252b5132 RH |
3851 | register fragS *fragP; |
3852 | #else | |
3853 | void | |
3854 | md_convert_frag (abfd, sec, fragP) | |
ab9da554 ILT |
3855 | bfd *abfd ATTRIBUTE_UNUSED; |
3856 | segT sec ATTRIBUTE_UNUSED; | |
252b5132 RH |
3857 | register fragS *fragP; |
3858 | #endif | |
3859 | { | |
3860 | register unsigned char *opcode; | |
3861 | unsigned char *where_to_put_displacement = NULL; | |
847f7ad4 AM |
3862 | offsetT target_address; |
3863 | offsetT opcode_address; | |
252b5132 | 3864 | unsigned int extension = 0; |
847f7ad4 | 3865 | offsetT displacement_from_opcode_start; |
252b5132 RH |
3866 | |
3867 | opcode = (unsigned char *) fragP->fr_opcode; | |
3868 | ||
3869 | /* Address we want to reach in file space. */ | |
3870 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; | |
3871 | #ifdef BFD_ASSEMBLER /* not needed otherwise? */ | |
49309057 | 3872 | target_address += symbol_get_frag (fragP->fr_symbol)->fr_address; |
252b5132 RH |
3873 | #endif |
3874 | ||
3875 | /* Address opcode resides at in file space. */ | |
3876 | opcode_address = fragP->fr_address + fragP->fr_fix; | |
3877 | ||
3878 | /* Displacement from opcode start to fill into instruction. */ | |
3879 | displacement_from_opcode_start = target_address - opcode_address; | |
3880 | ||
3881 | switch (fragP->fr_subtype) | |
3882 | { | |
3883 | case ENCODE_RELAX_STATE (COND_JUMP, SMALL): | |
3884 | case ENCODE_RELAX_STATE (COND_JUMP, SMALL16): | |
3885 | case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL): | |
3886 | case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL16): | |
3887 | /* don't have to change opcode */ | |
3888 | extension = 1; /* 1 opcode + 1 displacement */ | |
3889 | where_to_put_displacement = &opcode[1]; | |
3890 | break; | |
3891 | ||
3892 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): | |
3893 | extension = 5; /* 2 opcode + 4 displacement */ | |
3894 | opcode[1] = opcode[0] + 0x10; | |
3895 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
3896 | where_to_put_displacement = &opcode[2]; | |
3897 | break; | |
3898 | ||
3899 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
3900 | extension = 4; /* 1 opcode + 4 displacement */ | |
3901 | opcode[0] = 0xe9; | |
3902 | where_to_put_displacement = &opcode[1]; | |
3903 | break; | |
3904 | ||
3905 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): | |
3906 | extension = 3; /* 2 opcode + 2 displacement */ | |
3907 | opcode[1] = opcode[0] + 0x10; | |
3908 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
3909 | where_to_put_displacement = &opcode[2]; | |
3910 | break; | |
3911 | ||
3912 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): | |
3913 | extension = 2; /* 1 opcode + 2 displacement */ | |
3914 | opcode[0] = 0xe9; | |
3915 | where_to_put_displacement = &opcode[1]; | |
3916 | break; | |
3917 | ||
3918 | default: | |
3919 | BAD_CASE (fragP->fr_subtype); | |
3920 | break; | |
3921 | } | |
3922 | /* now put displacement after opcode */ | |
3923 | md_number_to_chars ((char *) where_to_put_displacement, | |
3924 | (valueT) (displacement_from_opcode_start - extension), | |
3925 | SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); | |
3926 | fragP->fr_fix += extension; | |
3927 | } | |
3928 | \f | |
3929 | ||
3930 | int md_short_jump_size = 2; /* size of byte displacement jmp */ | |
3931 | int md_long_jump_size = 5; /* size of dword displacement jmp */ | |
3932 | const int md_reloc_size = 8; /* Size of relocation record */ | |
3933 | ||
3934 | void | |
3935 | md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
3936 | char *ptr; | |
3937 | addressT from_addr, to_addr; | |
ab9da554 ILT |
3938 | fragS *frag ATTRIBUTE_UNUSED; |
3939 | symbolS *to_symbol ATTRIBUTE_UNUSED; | |
252b5132 | 3940 | { |
847f7ad4 | 3941 | offsetT offset; |
252b5132 RH |
3942 | |
3943 | offset = to_addr - (from_addr + 2); | |
3944 | md_number_to_chars (ptr, (valueT) 0xeb, 1); /* opcode for byte-disp jump */ | |
3945 | md_number_to_chars (ptr + 1, (valueT) offset, 1); | |
3946 | } | |
3947 | ||
3948 | void | |
3949 | md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
3950 | char *ptr; | |
3951 | addressT from_addr, to_addr; | |
a38cf1db AM |
3952 | fragS *frag ATTRIBUTE_UNUSED; |
3953 | symbolS *to_symbol ATTRIBUTE_UNUSED; | |
252b5132 | 3954 | { |
847f7ad4 | 3955 | offsetT offset; |
252b5132 | 3956 | |
a38cf1db AM |
3957 | offset = to_addr - (from_addr + 5); |
3958 | md_number_to_chars (ptr, (valueT) 0xe9, 1); | |
3959 | md_number_to_chars (ptr + 1, (valueT) offset, 4); | |
252b5132 RH |
3960 | } |
3961 | \f | |
3962 | /* Apply a fixup (fixS) to segment data, once it has been determined | |
3963 | by our caller that we have all the info we need to fix it up. | |
3964 | ||
3965 | On the 386, immediates, displacements, and data pointers are all in | |
3966 | the same (little-endian) format, so we don't need to care about which | |
3967 | we are handling. */ | |
3968 | ||
3969 | int | |
3970 | md_apply_fix3 (fixP, valp, seg) | |
3971 | fixS *fixP; /* The fix we're to put in. */ | |
3972 | valueT *valp; /* Pointer to the value of the bits. */ | |
a04b544b | 3973 | segT seg ATTRIBUTE_UNUSED; /* Segment fix is from. */ |
252b5132 RH |
3974 | { |
3975 | register char *p = fixP->fx_where + fixP->fx_frag->fr_literal; | |
3976 | valueT value = *valp; | |
3977 | ||
e1b283bb | 3978 | #if defined (BFD_ASSEMBLER) && !defined (TE_Mach) |
93382f6d AM |
3979 | if (fixP->fx_pcrel) |
3980 | { | |
3981 | switch (fixP->fx_r_type) | |
3982 | { | |
5865bb77 ILT |
3983 | default: |
3984 | break; | |
3985 | ||
93382f6d AM |
3986 | case BFD_RELOC_32: |
3987 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
3988 | break; | |
3989 | case BFD_RELOC_16: | |
3990 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
3991 | break; | |
3992 | case BFD_RELOC_8: | |
3993 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
3994 | break; | |
3995 | } | |
3996 | } | |
252b5132 | 3997 | |
0723899b ILT |
3998 | /* This is a hack. There should be a better way to handle this. |
3999 | This covers for the fact that bfd_install_relocation will | |
4000 | subtract the current location (for partial_inplace, PC relative | |
4001 | relocations); see more below. */ | |
93382f6d AM |
4002 | if ((fixP->fx_r_type == BFD_RELOC_32_PCREL |
4003 | || fixP->fx_r_type == BFD_RELOC_16_PCREL | |
4004 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) | |
4005 | && fixP->fx_addsy) | |
252b5132 RH |
4006 | { |
4007 | #ifndef OBJ_AOUT | |
4008 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
4009 | #ifdef TE_PE | |
4010 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
4011 | #endif | |
4012 | ) | |
4013 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
4014 | #endif | |
4015 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2f66722d | 4016 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
252b5132 | 4017 | { |
2f66722d AM |
4018 | segT fseg = S_GET_SEGMENT (fixP->fx_addsy); |
4019 | ||
4020 | if ((fseg == seg | |
4021 | || (symbol_section_p (fixP->fx_addsy) | |
4022 | && fseg != absolute_section)) | |
4023 | && ! S_IS_EXTERNAL (fixP->fx_addsy) | |
4024 | && ! S_IS_WEAK (fixP->fx_addsy) | |
4025 | && S_IS_DEFINED (fixP->fx_addsy) | |
4026 | && ! S_IS_COMMON (fixP->fx_addsy)) | |
4027 | { | |
4028 | /* Yes, we add the values in twice. This is because | |
4029 | bfd_perform_relocation subtracts them out again. I think | |
4030 | bfd_perform_relocation is broken, but I don't dare change | |
4031 | it. FIXME. */ | |
4032 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
4033 | } | |
252b5132 RH |
4034 | } |
4035 | #endif | |
4036 | #if defined (OBJ_COFF) && defined (TE_PE) | |
4037 | /* For some reason, the PE format does not store a section | |
24eab124 | 4038 | address offset for a PC relative symbol. */ |
252b5132 RH |
4039 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg) |
4040 | value += md_pcrel_from (fixP); | |
4041 | #endif | |
4042 | } | |
4043 | ||
4044 | /* Fix a few things - the dynamic linker expects certain values here, | |
4045 | and we must not dissappoint it. */ | |
4046 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
4047 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
4048 | && fixP->fx_addsy) | |
4049 | switch (fixP->fx_r_type) { | |
4050 | case BFD_RELOC_386_PLT32: | |
4051 | /* Make the jump instruction point to the address of the operand. At | |
4052 | runtime we merely add the offset to the actual PLT entry. */ | |
847f7ad4 | 4053 | value = -4; |
252b5132 RH |
4054 | break; |
4055 | case BFD_RELOC_386_GOTPC: | |
4056 | /* | |
24eab124 | 4057 | * This is tough to explain. We end up with this one if we have |
252b5132 RH |
4058 | * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal |
4059 | * here is to obtain the absolute address of the GOT, and it is strongly | |
4060 | * preferable from a performance point of view to avoid using a runtime | |
c3332e24 | 4061 | * relocation for this. The actual sequence of instructions often look |
252b5132 | 4062 | * something like: |
c3332e24 | 4063 | * |
24eab124 | 4064 | * call .L66 |
252b5132 | 4065 | * .L66: |
24eab124 AM |
4066 | * popl %ebx |
4067 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
c3332e24 | 4068 | * |
24eab124 | 4069 | * The call and pop essentially return the absolute address of |
252b5132 RH |
4070 | * the label .L66 and store it in %ebx. The linker itself will |
4071 | * ultimately change the first operand of the addl so that %ebx points to | |
4072 | * the GOT, but to keep things simple, the .o file must have this operand | |
4073 | * set so that it generates not the absolute address of .L66, but the | |
4074 | * absolute address of itself. This allows the linker itself simply | |
4075 | * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be | |
4076 | * added in, and the addend of the relocation is stored in the operand | |
4077 | * field for the instruction itself. | |
c3332e24 | 4078 | * |
24eab124 | 4079 | * Our job here is to fix the operand so that it would add the correct |
252b5132 RH |
4080 | * offset so that %ebx would point to itself. The thing that is tricky is |
4081 | * that .-.L66 will point to the beginning of the instruction, so we need | |
4082 | * to further modify the operand so that it will point to itself. | |
4083 | * There are other cases where you have something like: | |
c3332e24 | 4084 | * |
24eab124 | 4085 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] |
c3332e24 | 4086 | * |
252b5132 | 4087 | * and here no correction would be required. Internally in the assembler |
c3332e24 | 4088 | * we treat operands of this form as not being pcrel since the '.' is |
252b5132 RH |
4089 | * explicitly mentioned, and I wonder whether it would simplify matters |
4090 | * to do it this way. Who knows. In earlier versions of the PIC patches, | |
4091 | * the pcrel_adjust field was used to store the correction, but since the | |
4092 | * expression is not pcrel, I felt it would be confusing to do it this way. | |
4093 | */ | |
4094 | value -= 1; | |
4095 | break; | |
4096 | case BFD_RELOC_386_GOT32: | |
24eab124 | 4097 | value = 0; /* Fully resolved at runtime. No addend. */ |
252b5132 RH |
4098 | break; |
4099 | case BFD_RELOC_386_GOTOFF: | |
4100 | break; | |
4101 | ||
4102 | case BFD_RELOC_VTABLE_INHERIT: | |
4103 | case BFD_RELOC_VTABLE_ENTRY: | |
4104 | fixP->fx_done = 0; | |
4105 | return 1; | |
4106 | ||
4107 | default: | |
4108 | break; | |
4109 | } | |
93382f6d AM |
4110 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ |
4111 | *valp = value; | |
4112 | #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */ | |
252b5132 RH |
4113 | md_number_to_chars (p, value, fixP->fx_size); |
4114 | ||
4115 | return 1; | |
4116 | } | |
252b5132 RH |
4117 | \f |
4118 | ||
4119 | #define MAX_LITTLENUMS 6 | |
4120 | ||
4121 | /* Turn the string pointed to by litP into a floating point constant of type | |
4122 | type, and emit the appropriate bytes. The number of LITTLENUMS emitted | |
4123 | is stored in *sizeP . An error message is returned, or NULL on OK. */ | |
4124 | char * | |
4125 | md_atof (type, litP, sizeP) | |
2ab9b79e | 4126 | int type; |
252b5132 RH |
4127 | char *litP; |
4128 | int *sizeP; | |
4129 | { | |
4130 | int prec; | |
4131 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
4132 | LITTLENUM_TYPE *wordP; | |
4133 | char *t; | |
4134 | ||
4135 | switch (type) | |
4136 | { | |
4137 | case 'f': | |
4138 | case 'F': | |
4139 | prec = 2; | |
4140 | break; | |
4141 | ||
4142 | case 'd': | |
4143 | case 'D': | |
4144 | prec = 4; | |
4145 | break; | |
4146 | ||
4147 | case 'x': | |
4148 | case 'X': | |
4149 | prec = 5; | |
4150 | break; | |
4151 | ||
4152 | default: | |
4153 | *sizeP = 0; | |
4154 | return _("Bad call to md_atof ()"); | |
4155 | } | |
4156 | t = atof_ieee (input_line_pointer, type, words); | |
4157 | if (t) | |
4158 | input_line_pointer = t; | |
4159 | ||
4160 | *sizeP = prec * sizeof (LITTLENUM_TYPE); | |
4161 | /* This loops outputs the LITTLENUMs in REVERSE order; in accord with | |
4162 | the bigendian 386. */ | |
4163 | for (wordP = words + prec - 1; prec--;) | |
4164 | { | |
4165 | md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE)); | |
4166 | litP += sizeof (LITTLENUM_TYPE); | |
4167 | } | |
4168 | return 0; | |
4169 | } | |
4170 | \f | |
4171 | char output_invalid_buf[8]; | |
4172 | ||
252b5132 RH |
4173 | static char * |
4174 | output_invalid (c) | |
4175 | int c; | |
4176 | { | |
4177 | if (isprint (c)) | |
4178 | sprintf (output_invalid_buf, "'%c'", c); | |
4179 | else | |
4180 | sprintf (output_invalid_buf, "(0x%x)", (unsigned) c); | |
4181 | return output_invalid_buf; | |
4182 | } | |
4183 | ||
252b5132 | 4184 | |
af6bdddf | 4185 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
4186 | |
4187 | static const reg_entry * | |
4188 | parse_register (reg_string, end_op) | |
4189 | char *reg_string; | |
4190 | char **end_op; | |
4191 | { | |
af6bdddf AM |
4192 | char *s = reg_string; |
4193 | char *p; | |
252b5132 RH |
4194 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
4195 | const reg_entry *r; | |
4196 | ||
4197 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
4198 | if (*s == REGISTER_PREFIX) | |
4199 | ++s; | |
4200 | ||
4201 | if (is_space_char (*s)) | |
4202 | ++s; | |
4203 | ||
4204 | p = reg_name_given; | |
af6bdddf | 4205 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
4206 | { |
4207 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
4208 | return (const reg_entry *) NULL; |
4209 | s++; | |
252b5132 RH |
4210 | } |
4211 | ||
af6bdddf | 4212 | *end_op = s; |
252b5132 RH |
4213 | |
4214 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
4215 | ||
5f47d35b AM |
4216 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
4217 | if (r == i386_regtab /* %st is first entry of table */) | |
4218 | { | |
5f47d35b AM |
4219 | if (is_space_char (*s)) |
4220 | ++s; | |
4221 | if (*s == '(') | |
4222 | { | |
af6bdddf | 4223 | ++s; |
5f47d35b AM |
4224 | if (is_space_char (*s)) |
4225 | ++s; | |
4226 | if (*s >= '0' && *s <= '7') | |
4227 | { | |
4228 | r = &i386_float_regtab[*s - '0']; | |
af6bdddf | 4229 | ++s; |
5f47d35b AM |
4230 | if (is_space_char (*s)) |
4231 | ++s; | |
4232 | if (*s == ')') | |
4233 | { | |
4234 | *end_op = s + 1; | |
4235 | return r; | |
4236 | } | |
5f47d35b | 4237 | } |
af6bdddf | 4238 | /* We have "%st(" then garbage */ |
5f47d35b AM |
4239 | return (const reg_entry *) NULL; |
4240 | } | |
4241 | } | |
4242 | ||
252b5132 RH |
4243 | return r; |
4244 | } | |
4245 | \f | |
4cc782b5 | 4246 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
65172ab8 | 4247 | const char *md_shortopts = "kVQ:sq"; |
252b5132 | 4248 | #else |
65172ab8 | 4249 | const char *md_shortopts = "q"; |
252b5132 RH |
4250 | #endif |
4251 | struct option md_longopts[] = { | |
4252 | {NULL, no_argument, NULL, 0} | |
4253 | }; | |
4254 | size_t md_longopts_size = sizeof (md_longopts); | |
4255 | ||
4256 | int | |
4257 | md_parse_option (c, arg) | |
4258 | int c; | |
ab9da554 | 4259 | char *arg ATTRIBUTE_UNUSED; |
252b5132 RH |
4260 | { |
4261 | switch (c) | |
4262 | { | |
a38cf1db AM |
4263 | case 'q': |
4264 | quiet_warnings = 1; | |
252b5132 RH |
4265 | break; |
4266 | ||
4267 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
4268 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
4269 | should be emitted or not. FIXME: Not implemented. */ | |
4270 | case 'Q': | |
252b5132 RH |
4271 | break; |
4272 | ||
4273 | /* -V: SVR4 argument to print version ID. */ | |
4274 | case 'V': | |
4275 | print_version_id (); | |
4276 | break; | |
4277 | ||
a38cf1db AM |
4278 | /* -k: Ignore for FreeBSD compatibility. */ |
4279 | case 'k': | |
252b5132 | 4280 | break; |
4cc782b5 ILT |
4281 | |
4282 | case 's': | |
4283 | /* -s: On i386 Solaris, this tells the native assembler to use | |
4284 | .stab instead of .stab.excl. We always use .stab anyhow. */ | |
4285 | break; | |
252b5132 RH |
4286 | #endif |
4287 | ||
4288 | default: | |
4289 | return 0; | |
4290 | } | |
4291 | return 1; | |
4292 | } | |
4293 | ||
4294 | void | |
4295 | md_show_usage (stream) | |
4296 | FILE *stream; | |
4297 | { | |
4cc782b5 ILT |
4298 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
4299 | fprintf (stream, _("\ | |
a38cf1db AM |
4300 | -Q ignored\n\ |
4301 | -V print assembler version number\n\ | |
4302 | -k ignored\n\ | |
4303 | -q quieten some warnings\n\ | |
4304 | -s ignored\n")); | |
4305 | #else | |
4306 | fprintf (stream, _("\ | |
4307 | -q quieten some warnings\n")); | |
4cc782b5 | 4308 | #endif |
252b5132 RH |
4309 | } |
4310 | ||
4311 | #ifdef BFD_ASSEMBLER | |
4c63da97 AM |
4312 | #if ((defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_COFF)) \ |
4313 | || (defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_AOUT)) \ | |
4314 | || (defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT))) | |
252b5132 RH |
4315 | |
4316 | /* Pick the target format to use. */ | |
4317 | ||
4318 | const char * | |
4319 | i386_target_format () | |
4320 | { | |
4321 | switch (OUTPUT_FLAVOR) | |
4322 | { | |
4c63da97 AM |
4323 | #ifdef OBJ_MAYBE_AOUT |
4324 | case bfd_target_aout_flavour: | |
4325 | return AOUT_TARGET_FORMAT; | |
4326 | #endif | |
4327 | #ifdef OBJ_MAYBE_COFF | |
252b5132 RH |
4328 | case bfd_target_coff_flavour: |
4329 | return "coff-i386"; | |
4c63da97 AM |
4330 | #endif |
4331 | #ifdef OBJ_MAYBE_ELF | |
252b5132 RH |
4332 | case bfd_target_elf_flavour: |
4333 | return "elf32-i386"; | |
4c63da97 | 4334 | #endif |
252b5132 RH |
4335 | default: |
4336 | abort (); | |
4337 | return NULL; | |
4338 | } | |
4339 | } | |
4340 | ||
4c63da97 | 4341 | #endif /* OBJ_MAYBE_ more than one */ |
252b5132 RH |
4342 | #endif /* BFD_ASSEMBLER */ |
4343 | \f | |
252b5132 RH |
4344 | symbolS * |
4345 | md_undefined_symbol (name) | |
4346 | char *name; | |
4347 | { | |
18dc2407 ILT |
4348 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
4349 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
4350 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
4351 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
4352 | { |
4353 | if (!GOT_symbol) | |
4354 | { | |
4355 | if (symbol_find (name)) | |
4356 | as_bad (_("GOT already in symbol table")); | |
4357 | GOT_symbol = symbol_new (name, undefined_section, | |
4358 | (valueT) 0, &zero_address_frag); | |
4359 | }; | |
4360 | return GOT_symbol; | |
4361 | } | |
252b5132 RH |
4362 | return 0; |
4363 | } | |
4364 | ||
4365 | /* Round up a section size to the appropriate boundary. */ | |
4366 | valueT | |
4367 | md_section_align (segment, size) | |
ab9da554 | 4368 | segT segment ATTRIBUTE_UNUSED; |
252b5132 RH |
4369 | valueT size; |
4370 | { | |
252b5132 | 4371 | #ifdef BFD_ASSEMBLER |
4c63da97 AM |
4372 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
4373 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
4374 | { | |
4375 | /* For a.out, force the section size to be aligned. If we don't do | |
4376 | this, BFD will align it for us, but it will not write out the | |
4377 | final bytes of the section. This may be a bug in BFD, but it is | |
4378 | easier to fix it here since that is how the other a.out targets | |
4379 | work. */ | |
4380 | int align; | |
4381 | ||
4382 | align = bfd_get_section_alignment (stdoutput, segment); | |
4383 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
4384 | } | |
252b5132 RH |
4385 | #endif |
4386 | #endif | |
4387 | ||
4388 | return size; | |
4389 | } | |
4390 | ||
4391 | /* On the i386, PC-relative offsets are relative to the start of the | |
4392 | next instruction. That is, the address of the offset, plus its | |
4393 | size, since the offset is always the last part of the insn. */ | |
4394 | ||
4395 | long | |
4396 | md_pcrel_from (fixP) | |
4397 | fixS *fixP; | |
4398 | { | |
4399 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
4400 | } | |
4401 | ||
4402 | #ifndef I386COFF | |
4403 | ||
4404 | static void | |
4405 | s_bss (ignore) | |
ab9da554 | 4406 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
4407 | { |
4408 | register int temp; | |
4409 | ||
4410 | temp = get_absolute_expression (); | |
4411 | subseg_set (bss_section, (subsegT) temp); | |
4412 | demand_empty_rest_of_line (); | |
4413 | } | |
4414 | ||
4415 | #endif | |
4416 | ||
4417 | ||
4418 | #ifdef BFD_ASSEMBLER | |
4419 | ||
4420 | void | |
4421 | i386_validate_fix (fixp) | |
4422 | fixS *fixp; | |
4423 | { | |
4424 | if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) | |
4425 | { | |
4426 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
4427 | fixp->fx_subsy = 0; | |
4428 | } | |
4429 | } | |
4430 | ||
252b5132 RH |
4431 | arelent * |
4432 | tc_gen_reloc (section, fixp) | |
ab9da554 | 4433 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
4434 | fixS *fixp; |
4435 | { | |
4436 | arelent *rel; | |
4437 | bfd_reloc_code_real_type code; | |
4438 | ||
4439 | switch (fixp->fx_r_type) | |
4440 | { | |
4441 | case BFD_RELOC_386_PLT32: | |
4442 | case BFD_RELOC_386_GOT32: | |
4443 | case BFD_RELOC_386_GOTOFF: | |
4444 | case BFD_RELOC_386_GOTPC: | |
4445 | case BFD_RELOC_RVA: | |
4446 | case BFD_RELOC_VTABLE_ENTRY: | |
4447 | case BFD_RELOC_VTABLE_INHERIT: | |
4448 | code = fixp->fx_r_type; | |
4449 | break; | |
4450 | default: | |
93382f6d | 4451 | if (fixp->fx_pcrel) |
252b5132 | 4452 | { |
93382f6d AM |
4453 | switch (fixp->fx_size) |
4454 | { | |
4455 | default: | |
d0b47220 | 4456 | as_bad (_("can not do %d byte pc-relative relocation"), |
93382f6d AM |
4457 | fixp->fx_size); |
4458 | code = BFD_RELOC_32_PCREL; | |
4459 | break; | |
4460 | case 1: code = BFD_RELOC_8_PCREL; break; | |
4461 | case 2: code = BFD_RELOC_16_PCREL; break; | |
4462 | case 4: code = BFD_RELOC_32_PCREL; break; | |
4463 | } | |
4464 | } | |
4465 | else | |
4466 | { | |
4467 | switch (fixp->fx_size) | |
4468 | { | |
4469 | default: | |
d0b47220 | 4470 | as_bad (_("can not do %d byte relocation"), fixp->fx_size); |
93382f6d AM |
4471 | code = BFD_RELOC_32; |
4472 | break; | |
4473 | case 1: code = BFD_RELOC_8; break; | |
4474 | case 2: code = BFD_RELOC_16; break; | |
4475 | case 4: code = BFD_RELOC_32; break; | |
4476 | } | |
252b5132 RH |
4477 | } |
4478 | break; | |
4479 | } | |
252b5132 RH |
4480 | |
4481 | if (code == BFD_RELOC_32 | |
4482 | && GOT_symbol | |
4483 | && fixp->fx_addsy == GOT_symbol) | |
4484 | code = BFD_RELOC_386_GOTPC; | |
4485 | ||
4486 | rel = (arelent *) xmalloc (sizeof (arelent)); | |
49309057 ILT |
4487 | rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
4488 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
4489 | |
4490 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
4491 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
4492 | vtable entry to be used in the relocation's section offset. */ | |
4493 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
4494 | rel->address = fixp->fx_offset; | |
4495 | ||
4496 | if (fixp->fx_pcrel) | |
4497 | rel->addend = fixp->fx_addnumber; | |
4498 | else | |
4499 | rel->addend = 0; | |
4500 | ||
4501 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); | |
4502 | if (rel->howto == NULL) | |
4503 | { | |
4504 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 4505 | _("cannot represent relocation type %s"), |
252b5132 RH |
4506 | bfd_get_reloc_code_name (code)); |
4507 | /* Set howto to a garbage value so that we can keep going. */ | |
4508 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
4509 | assert (rel->howto != NULL); | |
4510 | } | |
4511 | ||
4512 | return rel; | |
4513 | } | |
4514 | ||
4515 | #else /* ! BFD_ASSEMBLER */ | |
4516 | ||
4517 | #if (defined(OBJ_AOUT) | defined(OBJ_BOUT)) | |
4518 | void | |
4519 | tc_aout_fix_to_chars (where, fixP, segment_address_in_file) | |
4520 | char *where; | |
4521 | fixS *fixP; | |
4522 | relax_addressT segment_address_in_file; | |
4523 | { | |
4524 | /* | |
4525 | * In: length of relocation (or of address) in chars: 1, 2 or 4. | |
4526 | * Out: GNU LD relocation length code: 0, 1, or 2. | |
4527 | */ | |
4528 | ||
4529 | static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2}; | |
4530 | long r_symbolnum; | |
4531 | ||
4532 | know (fixP->fx_addsy != NULL); | |
4533 | ||
4534 | md_number_to_chars (where, | |
4535 | (valueT) (fixP->fx_frag->fr_address | |
4536 | + fixP->fx_where - segment_address_in_file), | |
4537 | 4); | |
4538 | ||
4539 | r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy) | |
4540 | ? S_GET_TYPE (fixP->fx_addsy) | |
4541 | : fixP->fx_addsy->sy_number); | |
4542 | ||
4543 | where[6] = (r_symbolnum >> 16) & 0x0ff; | |
4544 | where[5] = (r_symbolnum >> 8) & 0x0ff; | |
4545 | where[4] = r_symbolnum & 0x0ff; | |
4546 | where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08) | |
4547 | | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06) | |
4548 | | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f)); | |
4549 | } | |
4550 | ||
4551 | #endif /* OBJ_AOUT or OBJ_BOUT */ | |
4552 | ||
4553 | #if defined (I386COFF) | |
4554 | ||
4555 | short | |
4556 | tc_coff_fix2rtype (fixP) | |
4557 | fixS *fixP; | |
4558 | { | |
4559 | if (fixP->fx_r_type == R_IMAGEBASE) | |
4560 | return R_IMAGEBASE; | |
4561 | ||
4562 | return (fixP->fx_pcrel ? | |
4563 | (fixP->fx_size == 1 ? R_PCRBYTE : | |
4564 | fixP->fx_size == 2 ? R_PCRWORD : | |
4565 | R_PCRLONG) : | |
4566 | (fixP->fx_size == 1 ? R_RELBYTE : | |
4567 | fixP->fx_size == 2 ? R_RELWORD : | |
4568 | R_DIR32)); | |
4569 | } | |
4570 | ||
4571 | int | |
4572 | tc_coff_sizemachdep (frag) | |
4573 | fragS *frag; | |
4574 | { | |
4575 | if (frag->fr_next) | |
4576 | return (frag->fr_next->fr_address - frag->fr_address); | |
4577 | else | |
4578 | return 0; | |
4579 | } | |
4580 | ||
4581 | #endif /* I386COFF */ | |
4582 | ||
93382f6d | 4583 | #endif /* ! BFD_ASSEMBLER */ |
252b5132 RH |
4584 | \f |
4585 | /* end of tc-i386.c */ |