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* value.c (value_from_contents_and_address): Always return
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
0bfee649 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 LOCKREP_PREFIX. */
63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
67#define LOCKREP_PREFIX 4
68#define REX_PREFIX 5 /* must come last. */
69#define MAX_PREFIXES 6 /* max prefixes per opcode */
70
71/* we define the syntax here (modulo base,index,scale syntax) */
72#define REGISTER_PREFIX '%'
73#define IMMEDIATE_PREFIX '$'
74#define ABSOLUTE_PREFIX '*'
75
76/* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78#define WORD_MNEM_SUFFIX 'w'
79#define BYTE_MNEM_SUFFIX 'b'
80#define SHORT_MNEM_SUFFIX 's'
81#define LONG_MNEM_SUFFIX 'l'
82#define QWORD_MNEM_SUFFIX 'q'
83#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 84#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 85/* Intel Syntax. Use a non-ascii letter since since it never appears
86 in instructions. */
87#define LONG_DOUBLE_MNEM_SUFFIX '\1'
88
89#define END_OF_INSN '\0'
90
91/*
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
96 END.
97 */
98typedef struct
99{
100 const template *start;
101 const template *end;
102}
103templates;
104
105/* 386 operand encoding bytes: see 386 book for details of this. */
106typedef struct
107{
108 unsigned int regmem; /* codes register or memory operand */
109 unsigned int reg; /* codes register operand (or extended opcode) */
110 unsigned int mode; /* how to interpret regmem & reg */
111}
112modrm_byte;
113
114/* x86-64 extension prefix. */
115typedef int rex_byte;
116
117/* The SSE5 instructions have a two bit instruction modifier (OC) that
118 is stored in two separate bytes in the instruction. Pick apart OC
119 into the 2 separate bits for instruction. */
120#define DREX_OC0(x) (((x) & 1) != 0)
121#define DREX_OC1(x) (((x) & 2) != 0)
122
123#define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
124#define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
125
126/* OC mappings */
127#define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
128#define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
129#define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
130#define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
131
132#define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
133#define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
134
135/* Information needed to create the DREX byte in SSE5 instructions. */
136typedef struct
137{
138 unsigned int reg; /* register */
139 unsigned int rex; /* REX flags */
140 unsigned int modrm_reg; /* which arg goes in the modrm.reg field */
141 unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */
142} drex_byte;
143
144/* 386 opcode byte to code indirect addressing. */
145typedef struct
146{
147 unsigned base;
148 unsigned index;
149 unsigned scale;
150}
151sib_byte;
152
6305a203
L		 153/* x86 arch names, types and features */
154typedef struct
155{
156 const char *name; /* arch name */
157 enum processor_type type; /* arch type */
158 i386_cpu_flags flags; /* cpu feature flags */
159}
160arch_entry;
161
e3bb37b5
L		 162static void set_code_flag (int);
163static void set_16bit_gcc_code_flag (int);
164static void set_intel_syntax (int);
1efbbeb4 165static void set_intel_mnemonic (int);
db51cc60 166static void set_allow_index_reg (int);
cb19c032 167static void set_sse_check (int);
e3bb37b5 168static void set_cpu_arch (int);
6482c264 169#ifdef TE_PE
e3bb37b5 170static void pe_directive_secrel (int);
6482c264 171#endif
e3bb37b5
L		 172static void signed_cons (int);
173static char *output_invalid (int c);
a7619375 174static int i386_att_operand (char *);
e3bb37b5
L		 175static int i386_intel_operand (char *, int);
176static const reg_entry *parse_register (char *, char **);
177static char *parse_insn (char *, char *);
178static char *parse_operands (char *, const char *);
179static void swap_operands (void);
4d456e3d 180static void swap_2_operands (int, int);
e3bb37b5
L		 181static void optimize_imm (void);
182static void optimize_disp (void);
fa99fab2 183static const template *match_template (void);
e3bb37b5
L		 184static int check_string (void);
185static int process_suffix (void);
186static int check_byte_reg (void);
187static int check_long_reg (void);
188static int check_qword_reg (void);
189static int check_word_reg (void);
190static int finalize_imm (void);
85f10a01 191static void process_drex (void);
e3bb37b5
L		 192static int process_operands (void);
193static const seg_entry *build_modrm_byte (void);
194static void output_insn (void);
195static void output_imm (fragS *, offsetT);
196static void output_disp (fragS *, offsetT);
29b0f896 197#ifndef I386COFF
e3bb37b5 198static void s_bss (int);
252b5132 199#endif
17d4e2a2
L		 200#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201static void handle_large_common (int small ATTRIBUTE_UNUSED);
202#endif
252b5132 203
a847613f 204static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 205
c0f3af97
L		 206/* VEX prefix. */
207typedef struct
208{
209 /* VEX prefix is either 2 byte or 3 byte. */
210 unsigned char bytes[3];
211 unsigned int length;
212 /* Destination or source register specifier. */
213 const reg_entry *register_specifier;
214} vex_prefix;
215
252b5132 216/* 'md_assemble ()' gathers together information and puts it into a
47926f60 217 i386_insn. */
252b5132 218
520dc8e8
AM		 219union i386_op
220 {
221 expressionS *disps;
222 expressionS *imms;
223 const reg_entry *regs;
224 };
225
252b5132
RH		 226struct _i386_insn
227 {
47926f60 228 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 229 template tm;
230
7d5e4556
L		 231 /* SUFFIX holds the instruction size suffix for byte, word, dword
232 or qword, if given. */
252b5132
RH		 233 char suffix;
234
47926f60 235 /* OPERANDS gives the number of given operands. */
252b5132
RH		 236 unsigned int operands;
237
238 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
239 of given register, displacement, memory operands and immediate
47926f60 240 operands. */
252b5132
RH		 241 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
242
243 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 244 use OP[i] for the corresponding operand. */
40fb9820 245 i386_operand_type types[MAX_OPERANDS];
252b5132 246
520dc8e8
AM		 247 /* Displacement expression, immediate expression, or register for each
248 operand. */
249 union i386_op op[MAX_OPERANDS];
252b5132 250
3e73aa7c
JH		 251 /* Flags for operands. */
252 unsigned int flags[MAX_OPERANDS];
253#define Operand_PCrel 1
254
252b5132 255 /* Relocation type for operand */
f86103b7 256 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 257
252b5132
RH		 258 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
259 the base index byte below. */
260 const reg_entry *base_reg;
261 const reg_entry *index_reg;
262 unsigned int log2_scale_factor;
263
264 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 265 explicit segment overrides are given. */
ce8a8b2f 266 const seg_entry *seg[2];
252b5132
RH		 267
268 /* PREFIX holds all the given prefix opcodes (usually null).
269 PREFIXES is the number of prefix opcodes. */
270 unsigned int prefixes;
271 unsigned char prefix[MAX_PREFIXES];
272
273 /* RM and SIB are the modrm byte and the sib byte where the
85f10a01
MM		 274 addressing modes of this insn are encoded. DREX is the byte
275 added by the SSE5 instructions. */
252b5132
RH		 276
277 modrm_byte rm;
3e73aa7c 278 rex_byte rex;
252b5132 279 sib_byte sib;
85f10a01 280 drex_byte drex;
c0f3af97 281 vex_prefix vex;
b6169b20
L		 282
283 /* Swap operand in encoding. */
284 unsigned int swap_operand : 1;
252b5132
RH		 285 };
286
287typedef struct _i386_insn i386_insn;
288
289/* List of chars besides those in app.c:symbol_chars that can start an
290 operand. Used to prevent the scrubber eating vital white-space. */
32137342 291const char extra_symbol_chars[] = "*%-(["
252b5132 292#ifdef LEX_AT
32137342
NC		 293 "@"
294#endif
295#ifdef LEX_QM
296 "?"
252b5132 297#endif
32137342 298 ;
252b5132 299
29b0f896
AM		 300#if (defined (TE_I386AIX) \
301 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 302 && !defined (TE_GNU) \
29b0f896 303 && !defined (TE_LINUX) \
32137342 304 && !defined (TE_NETWARE) \
29b0f896
AM		 305 && !defined (TE_FreeBSD) \
306 && !defined (TE_NetBSD)))
252b5132 307/* This array holds the chars that always start a comment. If the
b3b91714
AM		 308 pre-processor is disabled, these aren't very useful. The option
309 --divide will remove '/' from this list. */
310const char *i386_comment_chars = "#/";
311#define SVR4_COMMENT_CHARS 1
252b5132 312#define PREFIX_SEPARATOR '\\'
252b5132 313
b3b91714
AM		 314#else
315const char *i386_comment_chars = "#";
316#define PREFIX_SEPARATOR '/'
317#endif
318
252b5132
RH		 319/* This array holds the chars that only start a comment at the beginning of
320 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 321 .line and .file directives will appear in the pre-processed output.
322 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 323 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 324 #NO_APP at the beginning of its output.
325 Also note that comments started like this one will always work if
252b5132 326 '/' isn't otherwise defined. */
b3b91714 327const char line_comment_chars[] = "#/";
252b5132 328
63a0b638 329const char line_separator_chars[] = ";";
252b5132 330
ce8a8b2f
AM		 331/* Chars that can be used to separate mant from exp in floating point
332 nums. */
252b5132
RH		 333const char EXP_CHARS[] = "eE";
334
ce8a8b2f
AM		 335/* Chars that mean this number is a floating point constant
336 As in 0f12.456
337 or 0d1.2345e12. */
252b5132
RH		 338const char FLT_CHARS[] = "fFdDxX";
339
ce8a8b2f 340/* Tables for lexical analysis. */
252b5132
RH		 341static char mnemonic_chars[256];
342static char register_chars[256];
343static char operand_chars[256];
344static char identifier_chars[256];
345static char digit_chars[256];
346
ce8a8b2f 347/* Lexical macros. */
252b5132
RH		 348#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
349#define is_operand_char(x) (operand_chars[(unsigned char) x])
350#define is_register_char(x) (register_chars[(unsigned char) x])
351#define is_space_char(x) ((x) == ' ')
352#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
353#define is_digit_char(x) (digit_chars[(unsigned char) x])
354
0234cb7c 355/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 356static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
357
358/* md_assemble() always leaves the strings it's passed unaltered. To
359 effect this we maintain a stack of saved characters that we've smashed
360 with '\0's (indicating end of strings for various sub-fields of the
47926f60 361 assembler instruction). */
252b5132 362static char save_stack[32];
ce8a8b2f 363static char *save_stack_p;
252b5132
RH		 364#define END_STRING_AND_SAVE(s) \
365 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
366#define RESTORE_END_STRING(s) \
367 do { *(s) = *--save_stack_p; } while (0)
368
47926f60 369/* The instruction we're assembling. */
252b5132
RH		 370static i386_insn i;
371
372/* Possible templates for current insn. */
373static const templates *current_templates;
374
31b2323c
L		 375/* Per instruction expressionS buffers: max displacements & immediates. */
376static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
377static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 378
47926f60
KH		 379/* Current operand we are working on. */
380static int this_operand;
252b5132 381
3e73aa7c
JH		 382/* We support four different modes. FLAG_CODE variable is used to distinguish
383 these. */
384
385enum flag_code {
386 CODE_32BIT,
387 CODE_16BIT,
388 CODE_64BIT };
389
390static enum flag_code flag_code;
4fa24527 391static unsigned int object_64bit;
3e73aa7c
JH		 392static int use_rela_relocations = 0;
393
394/* The names used to print error messages. */
b77a7acd 395static const char *flag_code_names[] =
3e73aa7c
JH		 396 {
397 "32",
398 "16",
399 "64"
400 };
252b5132 401
47926f60
KH		 402/* 1 for intel syntax,
403 0 if att syntax. */
404static int intel_syntax = 0;
252b5132 405
1efbbeb4
L		 406/* 1 for intel mnemonic,
407 0 if att mnemonic. */
408static int intel_mnemonic = !SYSV386_COMPAT;
409
5209009a 410/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 411static int old_gcc = OLDGCC_COMPAT;
412
a60de03c
JB		 413/* 1 if pseudo registers are permitted. */
414static int allow_pseudo_reg = 0;
415
47926f60
KH		 416/* 1 if register prefix % not required. */
417static int allow_naked_reg = 0;
252b5132 418
ba104c83 419/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 420static int allow_index_reg = 0;
421
daf50ae7
L		 422static enum
423 {
424 sse_check_none = 0,
425 sse_check_warning,
426 sse_check_error
427 }
428sse_check;
429
2ca3ace5
L		 430/* Register prefix used for error message. */
431static const char *register_prefix = "%";
432
47926f60
KH		 433/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
434 leave, push, and pop instructions so that gcc has the same stack
435 frame as in 32 bit mode. */
436static char stackop_size = '\0';
eecb386c 437
12b55ccc
L		 438/* Non-zero to optimize code alignment. */
439int optimize_align_code = 1;
440
47926f60
KH		 441/* Non-zero to quieten some warnings. */
442static int quiet_warnings = 0;
a38cf1db 443
47926f60
KH		 444/* CPU name. */
445static const char *cpu_arch_name = NULL;
6305a203 446static char *cpu_sub_arch_name = NULL;
a38cf1db 447
47926f60 448/* CPU feature flags. */
40fb9820
L		 449static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
450
ccc9c027
L		 451/* If we have selected a cpu we are generating instructions for. */
452static int cpu_arch_tune_set = 0;
453
9103f4f4 454/* Cpu we are generating instructions for. */
fbf3f584 455enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 456
457/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 458static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 459
ccc9c027 460/* CPU instruction set architecture used. */
fbf3f584 461enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 462
9103f4f4 463/* CPU feature flags of instruction set architecture used. */
fbf3f584 464i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 465
fddf5b5b
AM		 466/* If set, conditional jumps are not automatically promoted to handle
467 larger than a byte offset. */
468static unsigned int no_cond_jump_promotion = 0;
469
c0f3af97
L		 470/* Encode SSE instructions with VEX prefix. */
471static unsigned int sse2avx;
472
29b0f896 473/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 474static symbolS *GOT_symbol;
29b0f896 475
a4447b93
RH		 476/* The dwarf2 return column, adjusted for 32 or 64 bit. */
477unsigned int x86_dwarf2_return_column;
478
479/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
480int x86_cie_data_alignment;
481
252b5132 482/* Interface to relax_segment.
fddf5b5b
AM		 483 There are 3 major relax states for 386 jump insns because the
484 different types of jumps add different sizes to frags when we're
485 figuring out what sort of jump to choose to reach a given label. */
252b5132 486
47926f60 487/* Types. */
93c2a809
AM		 488#define UNCOND_JUMP 0
489#define COND_JUMP 1
490#define COND_JUMP86 2
fddf5b5b 491
47926f60 492/* Sizes. */
252b5132
RH		 493#define CODE16 1
494#define SMALL 0
29b0f896 495#define SMALL16 (SMALL | CODE16)
252b5132 496#define BIG 2
29b0f896 497#define BIG16 (BIG | CODE16)
252b5132
RH		 498
499#ifndef INLINE
500#ifdef __GNUC__
501#define INLINE __inline__
502#else
503#define INLINE
504#endif
505#endif
506
fddf5b5b
AM		 507#define ENCODE_RELAX_STATE(type, size) \
508 ((relax_substateT) (((type) << 2) | (size)))
509#define TYPE_FROM_RELAX_STATE(s) \
510 ((s) >> 2)
511#define DISP_SIZE_FROM_RELAX_STATE(s) \
512 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 513
514/* This table is used by relax_frag to promote short jumps to long
515 ones where necessary. SMALL (short) jumps may be promoted to BIG
516 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
517 don't allow a short jump in a 32 bit code segment to be promoted to
518 a 16 bit offset jump because it's slower (requires data size
519 prefix), and doesn't work, unless the destination is in the bottom
520 64k of the code segment (The top 16 bits of eip are zeroed). */
521
522const relax_typeS md_relax_table[] =
523{
24eab124
AM		 524 /* The fields are:
525 1) most positive reach of this state,
526 2) most negative reach of this state,
93c2a809 527 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 528 4) which index into the table to try if we can't fit into this one. */
252b5132 529
fddf5b5b 530 /* UNCOND_JUMP states. */
93c2a809
AM		 531 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
532 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
533 /* dword jmp adds 4 bytes to frag:
534 0 extra opcode bytes, 4 displacement bytes. */
252b5132 535 {0, 0, 4, 0},
93c2a809
AM		 536 /* word jmp adds 2 byte2 to frag:
537 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 538 {0, 0, 2, 0},
539
93c2a809
AM		 540 /* COND_JUMP states. */
541 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
542 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
543 /* dword conditionals adds 5 bytes to frag:
544 1 extra opcode byte, 4 displacement bytes. */
545 {0, 0, 5, 0},
fddf5b5b 546 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 547 1 extra opcode byte, 2 displacement bytes. */
548 {0, 0, 3, 0},
549
550 /* COND_JUMP86 states. */
551 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
552 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
553 /* dword conditionals adds 5 bytes to frag:
554 1 extra opcode byte, 4 displacement bytes. */
555 {0, 0, 5, 0},
556 /* word conditionals add 4 bytes to frag:
557 1 displacement byte and a 3 byte long branch insn. */
558 {0, 0, 4, 0}
252b5132
RH		 559};
560
9103f4f4
L		 561static const arch_entry cpu_arch[] =
562{
6305a203
L		 563 { "generic32", PROCESSOR_GENERIC32,
564 CPU_GENERIC32_FLAGS },
565 { "generic64", PROCESSOR_GENERIC64,
566 CPU_GENERIC64_FLAGS },
567 { "i8086", PROCESSOR_UNKNOWN,
568 CPU_NONE_FLAGS },
569 { "i186", PROCESSOR_UNKNOWN,
570 CPU_I186_FLAGS },
571 { "i286", PROCESSOR_UNKNOWN,
572 CPU_I286_FLAGS },
573 { "i386", PROCESSOR_I386,
574 CPU_I386_FLAGS },
575 { "i486", PROCESSOR_I486,
576 CPU_I486_FLAGS },
577 { "i586", PROCESSOR_PENTIUM,
578 CPU_I586_FLAGS },
579 { "i686", PROCESSOR_PENTIUMPRO,
580 CPU_I686_FLAGS },
581 { "pentium", PROCESSOR_PENTIUM,
582 CPU_I586_FLAGS },
583 { "pentiumpro", PROCESSOR_PENTIUMPRO,
584 CPU_I686_FLAGS },
585 { "pentiumii", PROCESSOR_PENTIUMPRO,
586 CPU_P2_FLAGS },
587 { "pentiumiii",PROCESSOR_PENTIUMPRO,
588 CPU_P3_FLAGS },
589 { "pentium4", PROCESSOR_PENTIUM4,
590 CPU_P4_FLAGS },
591 { "prescott", PROCESSOR_NOCONA,
592 CPU_CORE_FLAGS },
593 { "nocona", PROCESSOR_NOCONA,
594 CPU_NOCONA_FLAGS },
595 { "yonah", PROCESSOR_CORE,
596 CPU_CORE_FLAGS },
597 { "core", PROCESSOR_CORE,
598 CPU_CORE_FLAGS },
599 { "merom", PROCESSOR_CORE2,
600 CPU_CORE2_FLAGS },
601 { "core2", PROCESSOR_CORE2,
602 CPU_CORE2_FLAGS },
bd5295b2
L		 603 { "corei7", PROCESSOR_COREI7,
604 CPU_COREI7_FLAGS },
6305a203
L		 605 { "k6", PROCESSOR_K6,
606 CPU_K6_FLAGS },
607 { "k6_2", PROCESSOR_K6,
608 CPU_K6_2_FLAGS },
609 { "athlon", PROCESSOR_ATHLON,
610 CPU_ATHLON_FLAGS },
611 { "sledgehammer", PROCESSOR_K8,
612 CPU_K8_FLAGS },
613 { "opteron", PROCESSOR_K8,
614 CPU_K8_FLAGS },
615 { "k8", PROCESSOR_K8,
616 CPU_K8_FLAGS },
617 { "amdfam10", PROCESSOR_AMDFAM10,
618 CPU_AMDFAM10_FLAGS },
619 { ".mmx", PROCESSOR_UNKNOWN,
620 CPU_MMX_FLAGS },
621 { ".sse", PROCESSOR_UNKNOWN,
622 CPU_SSE_FLAGS },
623 { ".sse2", PROCESSOR_UNKNOWN,
624 CPU_SSE2_FLAGS },
625 { ".sse3", PROCESSOR_UNKNOWN,
626 CPU_SSE3_FLAGS },
627 { ".ssse3", PROCESSOR_UNKNOWN,
628 CPU_SSSE3_FLAGS },
629 { ".sse4.1", PROCESSOR_UNKNOWN,
630 CPU_SSE4_1_FLAGS },
631 { ".sse4.2", PROCESSOR_UNKNOWN,
632 CPU_SSE4_2_FLAGS },
633 { ".sse4", PROCESSOR_UNKNOWN,
634 CPU_SSE4_2_FLAGS },
c0f3af97
L		 635 { ".avx", PROCESSOR_UNKNOWN,
636 CPU_AVX_FLAGS },
6305a203
L		 637 { ".vmx", PROCESSOR_UNKNOWN,
638 CPU_VMX_FLAGS },
639 { ".smx", PROCESSOR_UNKNOWN,
640 CPU_SMX_FLAGS },
f03fe4c1
L		 641 { ".xsave", PROCESSOR_UNKNOWN,
642 CPU_XSAVE_FLAGS },
c0f3af97
L		 643 { ".aes", PROCESSOR_UNKNOWN,
644 CPU_AES_FLAGS },
594ab6a3
L		 645 { ".pclmul", PROCESSOR_UNKNOWN,
646 CPU_PCLMUL_FLAGS },
c0f3af97 647 { ".clmul", PROCESSOR_UNKNOWN,
594ab6a3 648 CPU_PCLMUL_FLAGS },
c0f3af97
L		 649 { ".fma", PROCESSOR_UNKNOWN,
650 CPU_FMA_FLAGS },
f1f8f695
L		 651 { ".movbe", PROCESSOR_UNKNOWN,
652 CPU_MOVBE_FLAGS },
653 { ".ept", PROCESSOR_UNKNOWN,
654 CPU_EPT_FLAGS },
bd5295b2
L		 655 { ".clflush", PROCESSOR_UNKNOWN,
656 CPU_CLFLUSH_FLAGS },
657 { ".syscall", PROCESSOR_UNKNOWN,
658 CPU_SYSCALL_FLAGS },
1b7f3fb0
L		 659 { ".rdtscp", PROCESSOR_UNKNOWN,
660 CPU_RDTSCP_FLAGS },
6305a203
L		 661 { ".3dnow", PROCESSOR_UNKNOWN,
662 CPU_3DNOW_FLAGS },
663 { ".3dnowa", PROCESSOR_UNKNOWN,
664 CPU_3DNOWA_FLAGS },
665 { ".padlock", PROCESSOR_UNKNOWN,
666 CPU_PADLOCK_FLAGS },
667 { ".pacifica", PROCESSOR_UNKNOWN,
668 CPU_SVME_FLAGS },
669 { ".svme", PROCESSOR_UNKNOWN,
670 CPU_SVME_FLAGS },
671 { ".sse4a", PROCESSOR_UNKNOWN,
672 CPU_SSE4A_FLAGS },
673 { ".abm", PROCESSOR_UNKNOWN,
674 CPU_ABM_FLAGS },
675 { ".sse5", PROCESSOR_UNKNOWN,
676 CPU_SSE5_FLAGS },
e413e4e9
AM		 677};
678
704209c0 679#ifdef I386COFF
a6c24e68
NC		 680/* Like s_lcomm_internal in gas/read.c but the alignment string
681 is allowed to be optional. */
682
683static symbolS *
684pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
685{
686 addressT align = 0;
687
688 SKIP_WHITESPACE ();
689
690 if (needs_align
691 && *input_line_pointer == ',')
692 {
693 align = parse_align (needs_align - 1);
694
695 if (align == (addressT) -1)
696 return NULL;
697 }
698 else
699 {
700 if (size >= 8)
701 align = 3;
702 else if (size >= 4)
703 align = 2;
704 else if (size >= 2)
705 align = 1;
706 else
707 align = 0;
708 }
709
710 bss_alloc (symbolP, size, align);
711 return symbolP;
712}
713
704209c0 714static void
a6c24e68
NC		 715pe_lcomm (int needs_align)
716{
717 s_comm_internal (needs_align * 2, pe_lcomm_internal);
718}
704209c0 719#endif
a6c24e68 720
29b0f896
AM		 721const pseudo_typeS md_pseudo_table[] =
722{
723#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
724 {"align", s_align_bytes, 0},
725#else
726 {"align", s_align_ptwo, 0},
727#endif
728 {"arch", set_cpu_arch, 0},
729#ifndef I386COFF
730 {"bss", s_bss, 0},
a6c24e68
NC		 731#else
732 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 733#endif
734 {"ffloat", float_cons, 'f'},
735 {"dfloat", float_cons, 'd'},
736 {"tfloat", float_cons, 'x'},
737 {"value", cons, 2},
d182319b 738 {"slong", signed_cons, 4},
29b0f896
AM		 739 {"noopt", s_ignore, 0},
740 {"optim", s_ignore, 0},
741 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
742 {"code16", set_code_flag, CODE_16BIT},
743 {"code32", set_code_flag, CODE_32BIT},
744 {"code64", set_code_flag, CODE_64BIT},
745 {"intel_syntax", set_intel_syntax, 1},
746 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 747 {"intel_mnemonic", set_intel_mnemonic, 1},
748 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 749 {"allow_index_reg", set_allow_index_reg, 1},
750 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 751 {"sse_check", set_sse_check, 0},
3b22753a
L		 752#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
753 {"largecomm", handle_large_common, 0},
07a53e5c 754#else
e3bb37b5 755 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 756 {"loc", dwarf2_directive_loc, 0},
757 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 758#endif
6482c264
NC		 759#ifdef TE_PE
760 {"secrel32", pe_directive_secrel, 0},
761#endif
29b0f896
AM		 762 {0, 0, 0}
763};
764
765/* For interface with expression (). */
766extern char *input_line_pointer;
767
768/* Hash table for instruction mnemonic lookup. */
769static struct hash_control *op_hash;
770
771/* Hash table for register lookup. */
772static struct hash_control *reg_hash;
773\f
252b5132 774void
e3bb37b5 775i386_align_code (fragS *fragP, int count)
252b5132 776{
ce8a8b2f
AM		 777 /* Various efficient no-op patterns for aligning code labels.
778 Note: Don't try to assemble the instructions in the comments.
779 0L and 0w are not legal. */
252b5132
RH		 780 static const char f32_1[] =
781 {0x90}; /* nop */
782 static const char f32_2[] =
ccc9c027 783 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 784 static const char f32_3[] =
785 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
786 static const char f32_4[] =
787 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
788 static const char f32_5[] =
789 {0x90, /* nop */
790 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
791 static const char f32_6[] =
792 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
793 static const char f32_7[] =
794 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
795 static const char f32_8[] =
796 {0x90, /* nop */
797 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
798 static const char f32_9[] =
799 {0x89,0xf6, /* movl %esi,%esi */
800 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
801 static const char f32_10[] =
802 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
803 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
804 static const char f32_11[] =
805 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
806 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
807 static const char f32_12[] =
808 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
809 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
810 static const char f32_13[] =
811 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
812 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
813 static const char f32_14[] =
814 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
815 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 816 static const char f16_3[] =
817 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 818 static const char f16_4[] =
819 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
820 static const char f16_5[] =
821 {0x90, /* nop */
822 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
823 static const char f16_6[] =
824 {0x89,0xf6, /* mov %si,%si */
825 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
826 static const char f16_7[] =
827 {0x8d,0x74,0x00, /* lea 0(%si),%si */
828 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
829 static const char f16_8[] =
830 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
831 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 832 static const char jump_31[] =
833 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
834 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
835 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
836 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 837 static const char *const f32_patt[] = {
838 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 839 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 840 };
841 static const char *const f16_patt[] = {
76bc74dc 842 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 843 };
ccc9c027
L		 844 /* nopl (%[re]ax) */
845 static const char alt_3[] =
846 {0x0f,0x1f,0x00};
847 /* nopl 0(%[re]ax) */
848 static const char alt_4[] =
849 {0x0f,0x1f,0x40,0x00};
850 /* nopl 0(%[re]ax,%[re]ax,1) */
851 static const char alt_5[] =
852 {0x0f,0x1f,0x44,0x00,0x00};
853 /* nopw 0(%[re]ax,%[re]ax,1) */
854 static const char alt_6[] =
855 {0x66,0x0f,0x1f,0x44,0x00,0x00};
856 /* nopl 0L(%[re]ax) */
857 static const char alt_7[] =
858 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
859 /* nopl 0L(%[re]ax,%[re]ax,1) */
860 static const char alt_8[] =
861 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
862 /* nopw 0L(%[re]ax,%[re]ax,1) */
863 static const char alt_9[] =
864 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
865 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
866 static const char alt_10[] =
867 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
868 /* data16
869 nopw %cs:0L(%[re]ax,%[re]ax,1) */
870 static const char alt_long_11[] =
871 {0x66,
872 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
873 /* data16
874 data16
875 nopw %cs:0L(%[re]ax,%[re]ax,1) */
876 static const char alt_long_12[] =
877 {0x66,
878 0x66,
879 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
880 /* data16
881 data16
882 data16
883 nopw %cs:0L(%[re]ax,%[re]ax,1) */
884 static const char alt_long_13[] =
885 {0x66,
886 0x66,
887 0x66,
888 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
889 /* data16
890 data16
891 data16
892 data16
893 nopw %cs:0L(%[re]ax,%[re]ax,1) */
894 static const char alt_long_14[] =
895 {0x66,
896 0x66,
897 0x66,
898 0x66,
899 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
900 /* data16
901 data16
902 data16
903 data16
904 data16
905 nopw %cs:0L(%[re]ax,%[re]ax,1) */
906 static const char alt_long_15[] =
907 {0x66,
908 0x66,
909 0x66,
910 0x66,
911 0x66,
912 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
913 /* nopl 0(%[re]ax,%[re]ax,1)
914 nopw 0(%[re]ax,%[re]ax,1) */
915 static const char alt_short_11[] =
916 {0x0f,0x1f,0x44,0x00,0x00,
917 0x66,0x0f,0x1f,0x44,0x00,0x00};
918 /* nopw 0(%[re]ax,%[re]ax,1)
919 nopw 0(%[re]ax,%[re]ax,1) */
920 static const char alt_short_12[] =
921 {0x66,0x0f,0x1f,0x44,0x00,0x00,
922 0x66,0x0f,0x1f,0x44,0x00,0x00};
923 /* nopw 0(%[re]ax,%[re]ax,1)
924 nopl 0L(%[re]ax) */
925 static const char alt_short_13[] =
926 {0x66,0x0f,0x1f,0x44,0x00,0x00,
927 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
928 /* nopl 0L(%[re]ax)
929 nopl 0L(%[re]ax) */
930 static const char alt_short_14[] =
931 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
932 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
933 /* nopl 0L(%[re]ax)
934 nopl 0L(%[re]ax,%[re]ax,1) */
935 static const char alt_short_15[] =
936 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
937 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
938 static const char *const alt_short_patt[] = {
939 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
940 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
941 alt_short_14, alt_short_15
942 };
943 static const char *const alt_long_patt[] = {
944 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
945 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
946 alt_long_14, alt_long_15
947 };
252b5132 948
76bc74dc
L		 949 /* Only align for at least a positive non-zero boundary. */
950 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 951 return;
3e73aa7c 952
ccc9c027
L		 953 /* We need to decide which NOP sequence to use for 32bit and
954 64bit. When -mtune= is used:
4eed87de 955
76bc74dc
L		 956 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
957 PROCESSOR_GENERIC32, f32_patt will be used.
958 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 959 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
960 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc
L		 961 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
962 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 963
76bc74dc
L		 964 When -mtune= isn't used, alt_long_patt will be used if
965 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
966 be used.
ccc9c027
L		 967
968 When -march= or .arch is used, we can't use anything beyond
969 cpu_arch_isa_flags. */
970
971 if (flag_code == CODE_16BIT)
972 {
ccc9c027 973 if (count > 8)
33fef721 974 {
76bc74dc
L		 975 memcpy (fragP->fr_literal + fragP->fr_fix,
976 jump_31, count);
977 /* Adjust jump offset. */
978 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 979 }
76bc74dc
L		 980 else
981 memcpy (fragP->fr_literal + fragP->fr_fix,
982 f16_patt[count - 1], count);
252b5132 983 }
33fef721 984 else
ccc9c027
L		 985 {
986 const char *const *patt = NULL;
987
fbf3f584 988 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 989 {
990 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
991 switch (cpu_arch_tune)
992 {
993 case PROCESSOR_UNKNOWN:
994 /* We use cpu_arch_isa_flags to check if we SHOULD
995 optimize for Cpu686. */
fbf3f584 996 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
76bc74dc 997 patt = alt_long_patt;
ccc9c027
L		 998 else
999 patt = f32_patt;
1000 break;
ccc9c027
L		 1001 case PROCESSOR_PENTIUMPRO:
1002 case PROCESSOR_PENTIUM4:
1003 case PROCESSOR_NOCONA:
ef05d495 1004 case PROCESSOR_CORE:
76bc74dc 1005 case PROCESSOR_CORE2:
bd5295b2 1006 case PROCESSOR_COREI7:
76bc74dc
L		 1007 case PROCESSOR_GENERIC64:
1008 patt = alt_long_patt;
1009 break;
ccc9c027
L		 1010 case PROCESSOR_K6:
1011 case PROCESSOR_ATHLON:
1012 case PROCESSOR_K8:
4eed87de 1013 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1014 patt = alt_short_patt;
1015 break;
76bc74dc 1016 case PROCESSOR_I386:
ccc9c027
L		 1017 case PROCESSOR_I486:
1018 case PROCESSOR_PENTIUM:
1019 case PROCESSOR_GENERIC32:
1020 patt = f32_patt;
1021 break;
4eed87de 1022 }
ccc9c027
L		 1023 }
1024 else
1025 {
fbf3f584 1026 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1027 {
1028 case PROCESSOR_UNKNOWN:
e6a14101 1029 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1030 PROCESSOR_UNKNOWN. */
1031 abort ();
1032 break;
1033
76bc74dc 1034 case PROCESSOR_I386:
ccc9c027
L		 1035 case PROCESSOR_I486:
1036 case PROCESSOR_PENTIUM:
ccc9c027
L		 1037 case PROCESSOR_K6:
1038 case PROCESSOR_ATHLON:
1039 case PROCESSOR_K8:
4eed87de 1040 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1041 case PROCESSOR_GENERIC32:
1042 /* We use cpu_arch_isa_flags to check if we CAN optimize
1043 for Cpu686. */
fbf3f584 1044 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1045 patt = alt_short_patt;
1046 else
1047 patt = f32_patt;
1048 break;
76bc74dc
L		 1049 case PROCESSOR_PENTIUMPRO:
1050 case PROCESSOR_PENTIUM4:
1051 case PROCESSOR_NOCONA:
1052 case PROCESSOR_CORE:
ef05d495 1053 case PROCESSOR_CORE2:
bd5295b2 1054 case PROCESSOR_COREI7:
fbf3f584 1055 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1056 patt = alt_long_patt;
1057 else
1058 patt = f32_patt;
1059 break;
1060 case PROCESSOR_GENERIC64:
76bc74dc 1061 patt = alt_long_patt;
ccc9c027 1062 break;
4eed87de 1063 }
ccc9c027
L		 1064 }
1065
76bc74dc
L		 1066 if (patt == f32_patt)
1067 {
1068 /* If the padding is less than 15 bytes, we use the normal
1069 ones. Otherwise, we use a jump instruction and adjust
1070 its offset. */
1071 if (count < 15)
1072 memcpy (fragP->fr_literal + fragP->fr_fix,
1073 patt[count - 1], count);
1074 else
1075 {
1076 memcpy (fragP->fr_literal + fragP->fr_fix,
1077 jump_31, count);
1078 /* Adjust jump offset. */
1079 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1080 }
1081 }
1082 else
1083 {
1084 /* Maximum length of an instruction is 15 byte. If the
1085 padding is greater than 15 bytes and we don't use jump,
1086 we have to break it into smaller pieces. */
1087 int padding = count;
1088 while (padding > 15)
1089 {
1090 padding -= 15;
1091 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1092 patt [14], 15);
1093 }
1094
1095 if (padding)
1096 memcpy (fragP->fr_literal + fragP->fr_fix,
1097 patt [padding - 1], padding);
1098 }
ccc9c027 1099 }
33fef721 1100 fragP->fr_var = count;
252b5132
RH		 1101}
1102
c6fb90c8 1103static INLINE int
0dfbf9d7 1104operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1105{
0dfbf9d7 1106 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1107 {
1108 case 3:
0dfbf9d7 1109 if (x->array[2])
c6fb90c8
L		 1110 return 0;
1111 case 2:
0dfbf9d7 1112 if (x->array[1])
c6fb90c8
L		 1113 return 0;
1114 case 1:
0dfbf9d7 1115 return !x->array[0];
c6fb90c8
L		 1116 default:
1117 abort ();
1118 }
40fb9820
L		 1119}
1120
c6fb90c8 1121static INLINE void
0dfbf9d7 1122operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1123{
0dfbf9d7 1124 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1125 {
1126 case 3:
0dfbf9d7 1127 x->array[2] = v;
c6fb90c8 1128 case 2:
0dfbf9d7 1129 x->array[1] = v;
c6fb90c8 1130 case 1:
0dfbf9d7 1131 x->array[0] = v;
c6fb90c8
L		 1132 break;
1133 default:
1134 abort ();
1135 }
1136}
40fb9820 1137
c6fb90c8 1138static INLINE int
0dfbf9d7
L		 1139operand_type_equal (const union i386_operand_type *x,
1140 const union i386_operand_type *y)
c6fb90c8 1141{
0dfbf9d7 1142 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1143 {
1144 case 3:
0dfbf9d7 1145 if (x->array[2] != y->array[2])
c6fb90c8
L		 1146 return 0;
1147 case 2:
0dfbf9d7 1148 if (x->array[1] != y->array[1])
c6fb90c8
L		 1149 return 0;
1150 case 1:
0dfbf9d7 1151 return x->array[0] == y->array[0];
c6fb90c8
L		 1152 break;
1153 default:
1154 abort ();
1155 }
1156}
40fb9820 1157
0dfbf9d7
L		 1158static INLINE int
1159cpu_flags_all_zero (const union i386_cpu_flags *x)
1160{
1161 switch (ARRAY_SIZE(x->array))
1162 {
1163 case 3:
1164 if (x->array[2])
1165 return 0;
1166 case 2:
1167 if (x->array[1])
1168 return 0;
1169 case 1:
1170 return !x->array[0];
1171 default:
1172 abort ();
1173 }
1174}
1175
1176static INLINE void
1177cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1178{
1179 switch (ARRAY_SIZE(x->array))
1180 {
1181 case 3:
1182 x->array[2] = v;
1183 case 2:
1184 x->array[1] = v;
1185 case 1:
1186 x->array[0] = v;
1187 break;
1188 default:
1189 abort ();
1190 }
1191}
1192
1193static INLINE int
1194cpu_flags_equal (const union i386_cpu_flags *x,
1195 const union i386_cpu_flags *y)
1196{
1197 switch (ARRAY_SIZE(x->array))
1198 {
1199 case 3:
1200 if (x->array[2] != y->array[2])
1201 return 0;
1202 case 2:
1203 if (x->array[1] != y->array[1])
1204 return 0;
1205 case 1:
1206 return x->array[0] == y->array[0];
1207 break;
1208 default:
1209 abort ();
1210 }
1211}
c6fb90c8
L		 1212
1213static INLINE int
1214cpu_flags_check_cpu64 (i386_cpu_flags f)
1215{
1216 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1217 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1218}
1219
c6fb90c8
L		 1220static INLINE i386_cpu_flags
1221cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1222{
c6fb90c8
L		 1223 switch (ARRAY_SIZE (x.array))
1224 {
1225 case 3:
1226 x.array [2] &= y.array [2];
1227 case 2:
1228 x.array [1] &= y.array [1];
1229 case 1:
1230 x.array [0] &= y.array [0];
1231 break;
1232 default:
1233 abort ();
1234 }
1235 return x;
1236}
40fb9820 1237
c6fb90c8
L		 1238static INLINE i386_cpu_flags
1239cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1240{
c6fb90c8 1241 switch (ARRAY_SIZE (x.array))
40fb9820 1242 {
c6fb90c8
L		 1243 case 3:
1244 x.array [2] |= y.array [2];
1245 case 2:
1246 x.array [1] |= y.array [1];
1247 case 1:
1248 x.array [0] |= y.array [0];
40fb9820
L		 1249 break;
1250 default:
1251 abort ();
1252 }
40fb9820
L		 1253 return x;
1254}
1255
c0f3af97
L		 1256#define CPU_FLAGS_ARCH_MATCH 0x1
1257#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2
L		 1258#define CPU_FLAGS_AES_MATCH 0x4
1259#define CPU_FLAGS_AVX_MATCH 0x8
c0f3af97 1260
a5ff0eb2
L		 1261#define CPU_FLAGS_32BIT_MATCH \
1262 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1263#define CPU_FLAGS_PERFECT_MATCH \
1264 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1265
1266/* Return CPU flags match bits. */
3629bb00 1267
40fb9820 1268static int
c0f3af97 1269cpu_flags_match (const template *t)
40fb9820 1270{
c0f3af97
L		 1271 i386_cpu_flags x = t->cpu_flags;
1272 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1273
1274 x.bitfield.cpu64 = 0;
1275 x.bitfield.cpuno64 = 0;
1276
0dfbf9d7 1277 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1278 {
1279 /* This instruction is available on all archs. */
1280 match |= CPU_FLAGS_32BIT_MATCH;
1281 }
3629bb00
L		 1282 else
1283 {
c0f3af97 1284 /* This instruction is available only on some archs. */
3629bb00
L		 1285 i386_cpu_flags cpu = cpu_arch_flags;
1286
1287 cpu.bitfield.cpu64 = 0;
1288 cpu.bitfield.cpuno64 = 0;
1289 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1290 if (!cpu_flags_all_zero (&cpu))
1291 {
a5ff0eb2
L		 1292 if (x.bitfield.cpuavx)
1293 {
1294 /* We only need to check AES/SSE2AVX with AVX. */
1295 if (cpu.bitfield.cpuavx)
1296 {
1297 /* Check SSE2AVX. */
1298 if (!t->opcode_modifier.sse2avx|| sse2avx)
1299 {
1300 match |= (CPU_FLAGS_ARCH_MATCH
1301 | CPU_FLAGS_AVX_MATCH);
1302 /* Check AES. */
1303 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1304 match |= CPU_FLAGS_AES_MATCH;
1305 }
1306 }
1307 else
1308 match |= CPU_FLAGS_ARCH_MATCH;
1309 }
1310 else
c0f3af97
L		 1311 match |= CPU_FLAGS_32BIT_MATCH;
1312 }
3629bb00 1313 }
c0f3af97 1314 return match;
40fb9820
L		 1315}
1316
c6fb90c8
L		 1317static INLINE i386_operand_type
1318operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1319{
c6fb90c8
L		 1320 switch (ARRAY_SIZE (x.array))
1321 {
1322 case 3:
1323 x.array [2] &= y.array [2];
1324 case 2:
1325 x.array [1] &= y.array [1];
1326 case 1:
1327 x.array [0] &= y.array [0];
1328 break;
1329 default:
1330 abort ();
1331 }
1332 return x;
40fb9820
L		 1333}
1334
c6fb90c8
L		 1335static INLINE i386_operand_type
1336operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1337{
c6fb90c8 1338 switch (ARRAY_SIZE (x.array))
40fb9820 1339 {
c6fb90c8
L		 1340 case 3:
1341 x.array [2] |= y.array [2];
1342 case 2:
1343 x.array [1] |= y.array [1];
1344 case 1:
1345 x.array [0] |= y.array [0];
40fb9820
L		 1346 break;
1347 default:
1348 abort ();
1349 }
c6fb90c8
L		 1350 return x;
1351}
40fb9820 1352
c6fb90c8
L		 1353static INLINE i386_operand_type
1354operand_type_xor (i386_operand_type x, i386_operand_type y)
1355{
1356 switch (ARRAY_SIZE (x.array))
1357 {
1358 case 3:
1359 x.array [2] ^= y.array [2];
1360 case 2:
1361 x.array [1] ^= y.array [1];
1362 case 1:
1363 x.array [0] ^= y.array [0];
1364 break;
1365 default:
1366 abort ();
1367 }
40fb9820
L		 1368 return x;
1369}
1370
1371static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1372static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1373static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1374static const i386_operand_type inoutportreg
1375 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1376static const i386_operand_type reg16_inoutportreg
1377 = OPERAND_TYPE_REG16_INOUTPORTREG;
1378static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1379static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1380static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1381static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1382static const i386_operand_type anydisp
1383 = OPERAND_TYPE_ANYDISP;
40fb9820 1384static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1385static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1386static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1387static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1388static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1389static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1390static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1391static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1392static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1393static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1394static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
c0f3af97 1395static const i386_operand_type vex_imm4 = OPERAND_TYPE_VEX_IMM4;
40fb9820
L		 1396
1397enum operand_type
1398{
1399 reg,
40fb9820
L		 1400 imm,
1401 disp,
1402 anymem
1403};
1404
c6fb90c8 1405static INLINE int
40fb9820
L		 1406operand_type_check (i386_operand_type t, enum operand_type c)
1407{
1408 switch (c)
1409 {
1410 case reg:
1411 return (t.bitfield.reg8
1412 || t.bitfield.reg16
1413 || t.bitfield.reg32
1414 || t.bitfield.reg64);
1415
40fb9820
L		 1416 case imm:
1417 return (t.bitfield.imm8
1418 || t.bitfield.imm8s
1419 || t.bitfield.imm16
1420 || t.bitfield.imm32
1421 || t.bitfield.imm32s
1422 || t.bitfield.imm64);
1423
1424 case disp:
1425 return (t.bitfield.disp8
1426 || t.bitfield.disp16
1427 || t.bitfield.disp32
1428 || t.bitfield.disp32s
1429 || t.bitfield.disp64);
1430
1431 case anymem:
1432 return (t.bitfield.disp8
1433 || t.bitfield.disp16
1434 || t.bitfield.disp32
1435 || t.bitfield.disp32s
1436 || t.bitfield.disp64
1437 || t.bitfield.baseindex);
1438
1439 default:
1440 abort ();
1441 }
2cfe26b6
AM		 1442
1443 return 0;
40fb9820
L		 1444}
1445
5c07affc
L		 1446/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1447 operand J for instruction template T. */
1448
1449static INLINE int
1450match_reg_size (const template *t, unsigned int j)
1451{
1452 return !((i.types[j].bitfield.byte
1453 && !t->operand_types[j].bitfield.byte)
1454 || (i.types[j].bitfield.word
1455 && !t->operand_types[j].bitfield.word)
1456 || (i.types[j].bitfield.dword
1457 && !t->operand_types[j].bitfield.dword)
1458 || (i.types[j].bitfield.qword
1459 && !t->operand_types[j].bitfield.qword));
1460}
1461
1462/* Return 1 if there is no conflict in any size on operand J for
1463 instruction template T. */
1464
1465static INLINE int
1466match_mem_size (const template *t, unsigned int j)
1467{
1468 return (match_reg_size (t, j)
1469 && !((i.types[j].bitfield.unspecified
1470 && !t->operand_types[j].bitfield.unspecified)
1471 || (i.types[j].bitfield.fword
1472 && !t->operand_types[j].bitfield.fword)
1473 || (i.types[j].bitfield.tbyte
1474 && !t->operand_types[j].bitfield.tbyte)
1475 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1476 && !t->operand_types[j].bitfield.xmmword)
1477 || (i.types[j].bitfield.ymmword
1478 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1479}
1480
1481/* Return 1 if there is no size conflict on any operands for
1482 instruction template T. */
1483
1484static INLINE int
1485operand_size_match (const template *t)
1486{
1487 unsigned int j;
1488 int match = 1;
1489
1490 /* Don't check jump instructions. */
1491 if (t->opcode_modifier.jump
1492 || t->opcode_modifier.jumpbyte
1493 || t->opcode_modifier.jumpdword
1494 || t->opcode_modifier.jumpintersegment)
1495 return match;
1496
1497 /* Check memory and accumulator operand size. */
1498 for (j = 0; j < i.operands; j++)
1499 {
1500 if (t->operand_types[j].bitfield.anysize)
1501 continue;
1502
1503 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1504 {
1505 match = 0;
1506 break;
1507 }
1508
1509 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1510 {
1511 match = 0;
1512 break;
1513 }
1514 }
1515
1516 if (match
1517 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1518 return match;
1519
1520 /* Check reverse. */
1521 assert (i.operands == 2);
1522
1523 match = 1;
1524 for (j = 0; j < 2; j++)
1525 {
1526 if (t->operand_types[j].bitfield.acc
1527 && !match_reg_size (t, j ? 0 : 1))
1528 {
1529 match = 0;
1530 break;
1531 }
1532
1533 if (i.types[j].bitfield.mem
1534 && !match_mem_size (t, j ? 0 : 1))
1535 {
1536 match = 0;
1537 break;
1538 }
1539 }
1540
1541 return match;
1542}
1543
c6fb90c8 1544static INLINE int
40fb9820
L		 1545operand_type_match (i386_operand_type overlap,
1546 i386_operand_type given)
1547{
1548 i386_operand_type temp = overlap;
1549
1550 temp.bitfield.jumpabsolute = 0;
7d5e4556 1551 temp.bitfield.unspecified = 0;
5c07affc
L		 1552 temp.bitfield.byte = 0;
1553 temp.bitfield.word = 0;
1554 temp.bitfield.dword = 0;
1555 temp.bitfield.fword = 0;
1556 temp.bitfield.qword = 0;
1557 temp.bitfield.tbyte = 0;
1558 temp.bitfield.xmmword = 0;
c0f3af97 1559 temp.bitfield.ymmword = 0;
0dfbf9d7 1560 if (operand_type_all_zero (&temp))
40fb9820
L		 1561 return 0;
1562
1563 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1564 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1565}
1566
7d5e4556 1567/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1568 unless the expected operand type register overlap is null.
1569 Note that Acc in a template matches every size of reg. */
1570
c6fb90c8 1571static INLINE int
40fb9820
L		 1572operand_type_register_match (i386_operand_type m0,
1573 i386_operand_type g0,
1574 i386_operand_type t0,
1575 i386_operand_type m1,
1576 i386_operand_type g1,
1577 i386_operand_type t1)
1578{
1579 if (!operand_type_check (g0, reg))
1580 return 1;
1581
1582 if (!operand_type_check (g1, reg))
1583 return 1;
1584
1585 if (g0.bitfield.reg8 == g1.bitfield.reg8
1586 && g0.bitfield.reg16 == g1.bitfield.reg16
1587 && g0.bitfield.reg32 == g1.bitfield.reg32
1588 && g0.bitfield.reg64 == g1.bitfield.reg64)
1589 return 1;
1590
1591 if (m0.bitfield.acc)
1592 {
1593 t0.bitfield.reg8 = 1;
1594 t0.bitfield.reg16 = 1;
1595 t0.bitfield.reg32 = 1;
1596 t0.bitfield.reg64 = 1;
1597 }
1598
1599 if (m1.bitfield.acc)
1600 {
1601 t1.bitfield.reg8 = 1;
1602 t1.bitfield.reg16 = 1;
1603 t1.bitfield.reg32 = 1;
1604 t1.bitfield.reg64 = 1;
1605 }
1606
1607 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1608 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1609 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1610 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1611}
1612
252b5132 1613static INLINE unsigned int
40fb9820 1614mode_from_disp_size (i386_operand_type t)
252b5132 1615{
40fb9820
L		 1616 if (t.bitfield.disp8)
1617 return 1;
1618 else if (t.bitfield.disp16
1619 || t.bitfield.disp32
1620 || t.bitfield.disp32s)
1621 return 2;
1622 else
1623 return 0;
252b5132
RH		 1624}
1625
1626static INLINE int
e3bb37b5 1627fits_in_signed_byte (offsetT num)
252b5132
RH		 1628{
1629 return (num >= -128) && (num <= 127);
47926f60 1630}
252b5132
RH		 1631
1632static INLINE int
e3bb37b5 1633fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1634{
1635 return (num & 0xff) == num;
47926f60 1636}
252b5132
RH		 1637
1638static INLINE int
e3bb37b5 1639fits_in_unsigned_word (offsetT num)
252b5132
RH		 1640{
1641 return (num & 0xffff) == num;
47926f60 1642}
252b5132
RH		 1643
1644static INLINE int
e3bb37b5 1645fits_in_signed_word (offsetT num)
252b5132
RH		 1646{
1647 return (-32768 <= num) && (num <= 32767);
47926f60 1648}
2a962e6d 1649
3e73aa7c 1650static INLINE int
e3bb37b5 1651fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1652{
1653#ifndef BFD64
1654 return 1;
1655#else
1656 return (!(((offsetT) -1 << 31) & num)
1657 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1658#endif
1659} /* fits_in_signed_long() */
2a962e6d 1660
3e73aa7c 1661static INLINE int
e3bb37b5 1662fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1663{
1664#ifndef BFD64
1665 return 1;
1666#else
1667 return (num & (((offsetT) 2 << 31) - 1)) == num;
1668#endif
1669} /* fits_in_unsigned_long() */
252b5132 1670
c0f3af97
L		 1671static INLINE int
1672fits_in_imm4 (offsetT num)
1673{
1674 return (num & 0xf) == num;
1675}
1676
40fb9820 1677static i386_operand_type
e3bb37b5 1678smallest_imm_type (offsetT num)
252b5132 1679{
40fb9820
L		 1680 i386_operand_type t;
1681
0dfbf9d7 1682 operand_type_set (&t, 0);
40fb9820
L		 1683 t.bitfield.imm64 = 1;
1684
1685 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1686 {
1687 /* This code is disabled on the 486 because all the Imm1 forms
1688 in the opcode table are slower on the i486. They're the
1689 versions with the implicitly specified single-position
1690 displacement, which has another syntax if you really want to
1691 use that form. */
40fb9820
L		 1692 t.bitfield.imm1 = 1;
1693 t.bitfield.imm8 = 1;
1694 t.bitfield.imm8s = 1;
1695 t.bitfield.imm16 = 1;
1696 t.bitfield.imm32 = 1;
1697 t.bitfield.imm32s = 1;
1698 }
1699 else if (fits_in_signed_byte (num))
1700 {
1701 t.bitfield.imm8 = 1;
1702 t.bitfield.imm8s = 1;
1703 t.bitfield.imm16 = 1;
1704 t.bitfield.imm32 = 1;
1705 t.bitfield.imm32s = 1;
1706 }
1707 else if (fits_in_unsigned_byte (num))
1708 {
1709 t.bitfield.imm8 = 1;
1710 t.bitfield.imm16 = 1;
1711 t.bitfield.imm32 = 1;
1712 t.bitfield.imm32s = 1;
1713 }
1714 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1715 {
1716 t.bitfield.imm16 = 1;
1717 t.bitfield.imm32 = 1;
1718 t.bitfield.imm32s = 1;
1719 }
1720 else if (fits_in_signed_long (num))
1721 {
1722 t.bitfield.imm32 = 1;
1723 t.bitfield.imm32s = 1;
1724 }
1725 else if (fits_in_unsigned_long (num))
1726 t.bitfield.imm32 = 1;
1727
1728 return t;
47926f60 1729}
252b5132 1730
847f7ad4 1731static offsetT
e3bb37b5 1732offset_in_range (offsetT val, int size)
847f7ad4 1733{
508866be 1734 addressT mask;
ba2adb93 1735
847f7ad4
AM		 1736 switch (size)
1737 {
508866be
L		 1738 case 1: mask = ((addressT) 1 << 8) - 1; break;
1739 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1740 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1741#ifdef BFD64
1742 case 8: mask = ((addressT) 2 << 63) - 1; break;
1743#endif
47926f60 1744 default: abort ();
847f7ad4
AM		 1745 }
1746
ba2adb93 1747 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1748 if (!use_rela_relocations)
1749 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1750 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1751
47926f60 1752 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1753 {
1754 char buf1[40], buf2[40];
1755
1756 sprint_value (buf1, val);
1757 sprint_value (buf2, val & mask);
1758 as_warn (_("%s shortened to %s"), buf1, buf2);
1759 }
1760 return val & mask;
1761}
1762
252b5132
RH		 1763/* Returns 0 if attempting to add a prefix where one from the same
1764 class already exists, 1 if non rep/repne added, 2 if rep/repne
1765 added. */
1766static int
e3bb37b5 1767add_prefix (unsigned int prefix)
252b5132
RH		 1768{
1769 int ret = 1;
b1905489 1770 unsigned int q;
252b5132 1771
29b0f896
AM		 1772 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1773 && flag_code == CODE_64BIT)
b1905489 1774 {
161a04f6
L		 1775 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1776 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1777 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1778 ret = 0;
1779 q = REX_PREFIX;
1780 }
3e73aa7c 1781 else
b1905489
JB		 1782 {
1783 switch (prefix)
1784 {
1785 default:
1786 abort ();
1787
1788 case CS_PREFIX_OPCODE:
1789 case DS_PREFIX_OPCODE:
1790 case ES_PREFIX_OPCODE:
1791 case FS_PREFIX_OPCODE:
1792 case GS_PREFIX_OPCODE:
1793 case SS_PREFIX_OPCODE:
1794 q = SEG_PREFIX;
1795 break;
1796
1797 case REPNE_PREFIX_OPCODE:
1798 case REPE_PREFIX_OPCODE:
1799 ret = 2;
1800 /* fall thru */
1801 case LOCK_PREFIX_OPCODE:
1802 q = LOCKREP_PREFIX;
1803 break;
1804
1805 case FWAIT_OPCODE:
1806 q = WAIT_PREFIX;
1807 break;
1808
1809 case ADDR_PREFIX_OPCODE:
1810 q = ADDR_PREFIX;
1811 break;
1812
1813 case DATA_PREFIX_OPCODE:
1814 q = DATA_PREFIX;
1815 break;
1816 }
1817 if (i.prefix[q] != 0)
1818 ret = 0;
1819 }
252b5132 1820
b1905489 1821 if (ret)
252b5132 1822 {
b1905489
JB		 1823 if (!i.prefix[q])
1824 ++i.prefixes;
1825 i.prefix[q] |= prefix;
252b5132 1826 }
b1905489
JB		 1827 else
1828 as_bad (_("same type of prefix used twice"));
252b5132 1829
252b5132
RH		 1830 return ret;
1831}
1832
1833static void
e3bb37b5 1834set_code_flag (int value)
eecb386c 1835{
3e73aa7c 1836 flag_code = value;
40fb9820
L		 1837 if (flag_code == CODE_64BIT)
1838 {
1839 cpu_arch_flags.bitfield.cpu64 = 1;
1840 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1841 }
1842 else
1843 {
1844 cpu_arch_flags.bitfield.cpu64 = 0;
1845 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1846 }
1847 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1848 {
1849 as_bad (_("64bit mode not supported on this CPU."));
1850 }
40fb9820 1851 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1852 {
1853 as_bad (_("32bit mode not supported on this CPU."));
1854 }
eecb386c
AM		 1855 stackop_size = '\0';
1856}
1857
1858static void
e3bb37b5 1859set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1860{
3e73aa7c 1861 flag_code = new_code_flag;
40fb9820
L		 1862 if (flag_code != CODE_16BIT)
1863 abort ();
1864 cpu_arch_flags.bitfield.cpu64 = 0;
1865 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1866 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1867}
1868
1869static void
e3bb37b5 1870set_intel_syntax (int syntax_flag)
252b5132
RH		 1871{
1872 /* Find out if register prefixing is specified. */
1873 int ask_naked_reg = 0;
1874
1875 SKIP_WHITESPACE ();
29b0f896 1876 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1877 {
1878 char *string = input_line_pointer;
1879 int e = get_symbol_end ();
1880
47926f60 1881 if (strcmp (string, "prefix") == 0)
252b5132 1882 ask_naked_reg = 1;
47926f60 1883 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1884 ask_naked_reg = -1;
1885 else
d0b47220 1886 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1887 *input_line_pointer = e;
1888 }
1889 demand_empty_rest_of_line ();
c3332e24 1890
252b5132
RH		 1891 intel_syntax = syntax_flag;
1892
1893 if (ask_naked_reg == 0)
f86103b7
AM		 1894 allow_naked_reg = (intel_syntax
1895 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1896 else
1897 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1898
e4a3b5a4 1899 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1900 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1901 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1902}
1903
1efbbeb4
L		 1904static void
1905set_intel_mnemonic (int mnemonic_flag)
1906{
e1d4d893 1907 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1908}
1909
db51cc60
L		 1910static void
1911set_allow_index_reg (int flag)
1912{
1913 allow_index_reg = flag;
1914}
1915
cb19c032
L		 1916static void
1917set_sse_check (int dummy ATTRIBUTE_UNUSED)
1918{
1919 SKIP_WHITESPACE ();
1920
1921 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1922 {
1923 char *string = input_line_pointer;
1924 int e = get_symbol_end ();
1925
1926 if (strcmp (string, "none") == 0)
1927 sse_check = sse_check_none;
1928 else if (strcmp (string, "warning") == 0)
1929 sse_check = sse_check_warning;
1930 else if (strcmp (string, "error") == 0)
1931 sse_check = sse_check_error;
1932 else
1933 as_bad (_("bad argument to sse_check directive."));
1934 *input_line_pointer = e;
1935 }
1936 else
1937 as_bad (_("missing argument for sse_check directive"));
1938
1939 demand_empty_rest_of_line ();
1940}
1941
e413e4e9 1942static void
e3bb37b5 1943set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1944{
47926f60 1945 SKIP_WHITESPACE ();
e413e4e9 1946
29b0f896 1947 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1948 {
1949 char *string = input_line_pointer;
1950 int e = get_symbol_end ();
9103f4f4 1951 unsigned int i;
40fb9820 1952 i386_cpu_flags flags;
e413e4e9 1953
9103f4f4 1954 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1955 {
1956 if (strcmp (string, cpu_arch[i].name) == 0)
1957 {
5c6af06e
JB		 1958 if (*string != '.')
1959 {
1960 cpu_arch_name = cpu_arch[i].name;
1961 cpu_sub_arch_name = NULL;
40fb9820
L		 1962 cpu_arch_flags = cpu_arch[i].flags;
1963 if (flag_code == CODE_64BIT)
1964 {
1965 cpu_arch_flags.bitfield.cpu64 = 1;
1966 cpu_arch_flags.bitfield.cpuno64 = 0;
1967 }
1968 else
1969 {
1970 cpu_arch_flags.bitfield.cpu64 = 0;
1971 cpu_arch_flags.bitfield.cpuno64 = 1;
1972 }
ccc9c027 1973 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1974 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1975 if (!cpu_arch_tune_set)
1976 {
1977 cpu_arch_tune = cpu_arch_isa;
1978 cpu_arch_tune_flags = cpu_arch_isa_flags;
1979 }
5c6af06e
JB		 1980 break;
1981 }
40fb9820 1982
c6fb90c8
L		 1983 flags = cpu_flags_or (cpu_arch_flags,
1984 cpu_arch[i].flags);
0dfbf9d7 1985 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 1986 {
6305a203
L		 1987 if (cpu_sub_arch_name)
1988 {
1989 char *name = cpu_sub_arch_name;
1990 cpu_sub_arch_name = concat (name,
1991 cpu_arch[i].name,
1bf57e9f 1992 (const char *) NULL);
6305a203
L		 1993 free (name);
1994 }
1995 else
1996 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
40fb9820 1997 cpu_arch_flags = flags;
5c6af06e
JB		 1998 }
1999 *input_line_pointer = e;
2000 demand_empty_rest_of_line ();
2001 return;
e413e4e9
AM		 2002 }
2003 }
9103f4f4 2004 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2005 as_bad (_("no such architecture: `%s'"), string);
2006
2007 *input_line_pointer = e;
2008 }
2009 else
2010 as_bad (_("missing cpu architecture"));
2011
fddf5b5b
AM		 2012 no_cond_jump_promotion = 0;
2013 if (*input_line_pointer == ','
29b0f896 2014 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2015 {
2016 char *string = ++input_line_pointer;
2017 int e = get_symbol_end ();
2018
2019 if (strcmp (string, "nojumps") == 0)
2020 no_cond_jump_promotion = 1;
2021 else if (strcmp (string, "jumps") == 0)
2022 ;
2023 else
2024 as_bad (_("no such architecture modifier: `%s'"), string);
2025
2026 *input_line_pointer = e;
2027 }
2028
e413e4e9
AM		 2029 demand_empty_rest_of_line ();
2030}
2031
b9d79e03
JH		 2032unsigned long
2033i386_mach ()
2034{
2035 if (!strcmp (default_arch, "x86_64"))
2036 return bfd_mach_x86_64;
2037 else if (!strcmp (default_arch, "i386"))
2038 return bfd_mach_i386_i386;
2039 else
2040 as_fatal (_("Unknown architecture"));
2041}
b9d79e03 2042\f
252b5132
RH		 2043void
2044md_begin ()
2045{
2046 const char *hash_err;
2047
47926f60 2048 /* Initialize op_hash hash table. */
252b5132
RH		 2049 op_hash = hash_new ();
2050
2051 {
29b0f896
AM		 2052 const template *optab;
2053 templates *core_optab;
252b5132 2054
47926f60
KH		 2055 /* Setup for loop. */
2056 optab = i386_optab;
252b5132
RH		 2057 core_optab = (templates *) xmalloc (sizeof (templates));
2058 core_optab->start = optab;
2059
2060 while (1)
2061 {
2062 ++optab;
2063 if (optab->name == NULL
2064 || strcmp (optab->name, (optab - 1)->name) != 0)
2065 {
2066 /* different name --> ship out current template list;
47926f60 2067 add to hash table; & begin anew. */
252b5132
RH		 2068 core_optab->end = optab;
2069 hash_err = hash_insert (op_hash,
2070 (optab - 1)->name,
5a49b8ac 2071 (void *) core_optab);
252b5132
RH		 2072 if (hash_err)
2073 {
252b5132
RH		 2074 as_fatal (_("Internal Error: Can't hash %s: %s"),
2075 (optab - 1)->name,
2076 hash_err);
2077 }
2078 if (optab->name == NULL)
2079 break;
2080 core_optab = (templates *) xmalloc (sizeof (templates));
2081 core_optab->start = optab;
2082 }
2083 }
2084 }
2085
47926f60 2086 /* Initialize reg_hash hash table. */
252b5132
RH		 2087 reg_hash = hash_new ();
2088 {
29b0f896 2089 const reg_entry *regtab;
c3fe08fa 2090 unsigned int regtab_size = i386_regtab_size;
252b5132 2091
c3fe08fa 2092 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2093 {
5a49b8ac 2094 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2095 if (hash_err)
3e73aa7c
JH		 2096 as_fatal (_("Internal Error: Can't hash %s: %s"),
2097 regtab->reg_name,
2098 hash_err);
252b5132
RH		 2099 }
2100 }
2101
47926f60 2102 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2103 {
29b0f896
AM		 2104 int c;
2105 char *p;
252b5132
RH		 2106
2107 for (c = 0; c < 256; c++)
2108 {
3882b010 2109 if (ISDIGIT (c))
252b5132
RH		 2110 {
2111 digit_chars[c] = c;
2112 mnemonic_chars[c] = c;
2113 register_chars[c] = c;
2114 operand_chars[c] = c;
2115 }
3882b010 2116 else if (ISLOWER (c))
252b5132
RH		 2117 {
2118 mnemonic_chars[c] = c;
2119 register_chars[c] = c;
2120 operand_chars[c] = c;
2121 }
3882b010 2122 else if (ISUPPER (c))
252b5132 2123 {
3882b010 2124 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2125 register_chars[c] = mnemonic_chars[c];
2126 operand_chars[c] = c;
2127 }
2128
3882b010 2129 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2130 identifier_chars[c] = c;
2131 else if (c >= 128)
2132 {
2133 identifier_chars[c] = c;
2134 operand_chars[c] = c;
2135 }
2136 }
2137
2138#ifdef LEX_AT
2139 identifier_chars['@'] = '@';
32137342
NC		 2140#endif
2141#ifdef LEX_QM
2142 identifier_chars['?'] = '?';
2143 operand_chars['?'] = '?';
252b5132 2144#endif
252b5132 2145 digit_chars['-'] = '-';
c0f3af97 2146 mnemonic_chars['_'] = '_';
791fe849 2147 mnemonic_chars['-'] = '-';
0003779b 2148 mnemonic_chars['.'] = '.';
252b5132
RH		 2149 identifier_chars['_'] = '_';
2150 identifier_chars['.'] = '.';
2151
2152 for (p = operand_special_chars; *p != '\0'; p++)
2153 operand_chars[(unsigned char) *p] = *p;
2154 }
2155
2156#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2157 if (IS_ELF)
252b5132
RH		 2158 {
2159 record_alignment (text_section, 2);
2160 record_alignment (data_section, 2);
2161 record_alignment (bss_section, 2);
2162 }
2163#endif
a4447b93
RH		 2164
2165 if (flag_code == CODE_64BIT)
2166 {
2167 x86_dwarf2_return_column = 16;
2168 x86_cie_data_alignment = -8;
2169 }
2170 else
2171 {
2172 x86_dwarf2_return_column = 8;
2173 x86_cie_data_alignment = -4;
2174 }
252b5132
RH		 2175}
2176
2177void
e3bb37b5 2178i386_print_statistics (FILE *file)
252b5132
RH		 2179{
2180 hash_print_statistics (file, "i386 opcode", op_hash);
2181 hash_print_statistics (file, "i386 register", reg_hash);
2182}
2183\f
252b5132
RH		 2184#ifdef DEBUG386
2185
ce8a8b2f 2186/* Debugging routines for md_assemble. */
e3bb37b5 2187static void pte (template *);
40fb9820 2188static void pt (i386_operand_type);
e3bb37b5
L		 2189static void pe (expressionS *);
2190static void ps (symbolS *);
252b5132
RH		 2191
2192static void
e3bb37b5 2193pi (char *line, i386_insn *x)
252b5132 2194{
09f131f2 2195 unsigned int i;
252b5132
RH		 2196
2197 fprintf (stdout, "%s: template ", line);
2198 pte (&x->tm);
09f131f2
JH		 2199 fprintf (stdout, " address: base %s index %s scale %x\n",
2200 x->base_reg ? x->base_reg->reg_name : "none",
2201 x->index_reg ? x->index_reg->reg_name : "none",
2202 x->log2_scale_factor);
2203 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2204 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2205 fprintf (stdout, " sib: base %x index %x scale %x\n",
2206 x->sib.base, x->sib.index, x->sib.scale);
2207 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2208 (x->rex & REX_W) != 0,
2209 (x->rex & REX_R) != 0,
2210 (x->rex & REX_X) != 0,
2211 (x->rex & REX_B) != 0);
85f10a01
MM		 2212 fprintf (stdout, " drex: reg %d rex 0x%x\n",
2213 x->drex.reg, x->drex.rex);
252b5132
RH		 2214 for (i = 0; i < x->operands; i++)
2215 {
2216 fprintf (stdout, " #%d: ", i + 1);
2217 pt (x->types[i]);
2218 fprintf (stdout, "\n");
40fb9820
L		 2219 if (x->types[i].bitfield.reg8
2220 || x->types[i].bitfield.reg16
2221 || x->types[i].bitfield.reg32
2222 || x->types[i].bitfield.reg64
2223 || x->types[i].bitfield.regmmx
2224 || x->types[i].bitfield.regxmm
c0f3af97 2225 || x->types[i].bitfield.regymm
40fb9820
L		 2226 || x->types[i].bitfield.sreg2
2227 || x->types[i].bitfield.sreg3
2228 || x->types[i].bitfield.control
2229 || x->types[i].bitfield.debug
2230 || x->types[i].bitfield.test)
520dc8e8 2231 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 2232 if (operand_type_check (x->types[i], imm))
520dc8e8 2233 pe (x->op[i].imms);
40fb9820 2234 if (operand_type_check (x->types[i], disp))
520dc8e8 2235 pe (x->op[i].disps);
252b5132
RH		 2236 }
2237}
2238
2239static void
e3bb37b5 2240pte (template *t)
252b5132 2241{
09f131f2 2242 unsigned int i;
252b5132 2243 fprintf (stdout, " %d operands ", t->operands);
47926f60 2244 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2245 if (t->extension_opcode != None)
2246 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2247 if (t->opcode_modifier.d)
252b5132 2248 fprintf (stdout, "D");
40fb9820 2249 if (t->opcode_modifier.w)
252b5132
RH		 2250 fprintf (stdout, "W");
2251 fprintf (stdout, "\n");
2252 for (i = 0; i < t->operands; i++)
2253 {
2254 fprintf (stdout, " #%d type ", i + 1);
2255 pt (t->operand_types[i]);
2256 fprintf (stdout, "\n");
2257 }
2258}
2259
2260static void
e3bb37b5 2261pe (expressionS *e)
252b5132 2262{
24eab124 2263 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2264 fprintf (stdout, " add_number %ld (%lx)\n",
2265 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2266 if (e->X_add_symbol)
2267 {
2268 fprintf (stdout, " add_symbol ");
2269 ps (e->X_add_symbol);
2270 fprintf (stdout, "\n");
2271 }
2272 if (e->X_op_symbol)
2273 {
2274 fprintf (stdout, " op_symbol ");
2275 ps (e->X_op_symbol);
2276 fprintf (stdout, "\n");
2277 }
2278}
2279
2280static void
e3bb37b5 2281ps (symbolS *s)
252b5132
RH		 2282{
2283 fprintf (stdout, "%s type %s%s",
2284 S_GET_NAME (s),
2285 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2286 segment_name (S_GET_SEGMENT (s)));
2287}
2288
7b81dfbb 2289static struct type_name
252b5132 2290 {
40fb9820
L		 2291 i386_operand_type mask;
2292 const char *name;
252b5132 2293 }
7b81dfbb 2294const type_names[] =
252b5132 2295{
40fb9820
L		 2296 { OPERAND_TYPE_REG8, "r8" },
2297 { OPERAND_TYPE_REG16, "r16" },
2298 { OPERAND_TYPE_REG32, "r32" },
2299 { OPERAND_TYPE_REG64, "r64" },
2300 { OPERAND_TYPE_IMM8, "i8" },
2301 { OPERAND_TYPE_IMM8, "i8s" },
2302 { OPERAND_TYPE_IMM16, "i16" },
2303 { OPERAND_TYPE_IMM32, "i32" },
2304 { OPERAND_TYPE_IMM32S, "i32s" },
2305 { OPERAND_TYPE_IMM64, "i64" },
2306 { OPERAND_TYPE_IMM1, "i1" },
2307 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2308 { OPERAND_TYPE_DISP8, "d8" },
2309 { OPERAND_TYPE_DISP16, "d16" },
2310 { OPERAND_TYPE_DISP32, "d32" },
2311 { OPERAND_TYPE_DISP32S, "d32s" },
2312 { OPERAND_TYPE_DISP64, "d64" },
2313 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2314 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2315 { OPERAND_TYPE_CONTROL, "control reg" },
2316 { OPERAND_TYPE_TEST, "test reg" },
2317 { OPERAND_TYPE_DEBUG, "debug reg" },
2318 { OPERAND_TYPE_FLOATREG, "FReg" },
2319 { OPERAND_TYPE_FLOATACC, "FAcc" },
2320 { OPERAND_TYPE_SREG2, "SReg2" },
2321 { OPERAND_TYPE_SREG3, "SReg3" },
2322 { OPERAND_TYPE_ACC, "Acc" },
2323 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2324 { OPERAND_TYPE_REGMMX, "rMMX" },
2325 { OPERAND_TYPE_REGXMM, "rXMM" },
2326 { OPERAND_TYPE_ESSEG, "es" },
c0f3af97 2327 { OPERAND_TYPE_VEX_IMM4, "VEX i4" },
252b5132
RH		 2328};
2329
2330static void
40fb9820 2331pt (i386_operand_type t)
252b5132 2332{
40fb9820 2333 unsigned int j;
c6fb90c8 2334 i386_operand_type a;
252b5132 2335
40fb9820 2336 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2337 {
2338 a = operand_type_and (t, type_names[j].mask);
2339 if (!UINTS_ALL_ZERO (a))
2340 fprintf (stdout, "%s, ", type_names[j].name);
2341 }
252b5132
RH		 2342 fflush (stdout);
2343}
2344
2345#endif /* DEBUG386 */
2346\f
252b5132 2347static bfd_reloc_code_real_type
3956db08 2348reloc (unsigned int size,
64e74474
AM		 2349 int pcrel,
2350 int sign,
2351 bfd_reloc_code_real_type other)
252b5132 2352{
47926f60 2353 if (other != NO_RELOC)
3956db08
JB		 2354 {
2355 reloc_howto_type *reloc;
2356
2357 if (size == 8)
2358 switch (other)
2359 {
64e74474
AM		 2360 case BFD_RELOC_X86_64_GOT32:
2361 return BFD_RELOC_X86_64_GOT64;
2362 break;
2363 case BFD_RELOC_X86_64_PLTOFF64:
2364 return BFD_RELOC_X86_64_PLTOFF64;
2365 break;
2366 case BFD_RELOC_X86_64_GOTPC32:
2367 other = BFD_RELOC_X86_64_GOTPC64;
2368 break;
2369 case BFD_RELOC_X86_64_GOTPCREL:
2370 other = BFD_RELOC_X86_64_GOTPCREL64;
2371 break;
2372 case BFD_RELOC_X86_64_TPOFF32:
2373 other = BFD_RELOC_X86_64_TPOFF64;
2374 break;
2375 case BFD_RELOC_X86_64_DTPOFF32:
2376 other = BFD_RELOC_X86_64_DTPOFF64;
2377 break;
2378 default:
2379 break;
3956db08 2380 }
e05278af
JB		 2381
2382 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2383 if (size == 4 && flag_code != CODE_64BIT)
2384 sign = -1;
2385
3956db08
JB		 2386 reloc = bfd_reloc_type_lookup (stdoutput, other);
2387 if (!reloc)
2388 as_bad (_("unknown relocation (%u)"), other);
2389 else if (size != bfd_get_reloc_size (reloc))
2390 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2391 bfd_get_reloc_size (reloc),
2392 size);
2393 else if (pcrel && !reloc->pc_relative)
2394 as_bad (_("non-pc-relative relocation for pc-relative field"));
2395 else if ((reloc->complain_on_overflow == complain_overflow_signed
2396 && !sign)
2397 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 2398 && sign > 0))
3956db08
JB		 2399 as_bad (_("relocated field and relocation type differ in signedness"));
2400 else
2401 return other;
2402 return NO_RELOC;
2403 }
252b5132
RH		 2404
2405 if (pcrel)
2406 {
3e73aa7c 2407 if (!sign)
3956db08 2408 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2409 switch (size)
2410 {
2411 case 1: return BFD_RELOC_8_PCREL;
2412 case 2: return BFD_RELOC_16_PCREL;
2413 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2414 case 8: return BFD_RELOC_64_PCREL;
252b5132 2415 }
3956db08 2416 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2417 }
2418 else
2419 {
3956db08 2420 if (sign > 0)
e5cb08ac 2421 switch (size)
3e73aa7c
JH		 2422 {
2423 case 4: return BFD_RELOC_X86_64_32S;
2424 }
2425 else
2426 switch (size)
2427 {
2428 case 1: return BFD_RELOC_8;
2429 case 2: return BFD_RELOC_16;
2430 case 4: return BFD_RELOC_32;
2431 case 8: return BFD_RELOC_64;
2432 }
3956db08
JB		 2433 as_bad (_("cannot do %s %u byte relocation"),
2434 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2435 }
2436
bfb32b52 2437 abort ();
252b5132
RH		 2438 return BFD_RELOC_NONE;
2439}
2440
47926f60
KH		 2441/* Here we decide which fixups can be adjusted to make them relative to
2442 the beginning of the section instead of the symbol. Basically we need
2443 to make sure that the dynamic relocations are done correctly, so in
2444 some cases we force the original symbol to be used. */
2445
252b5132 2446int
e3bb37b5 2447tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2448{
6d249963 2449#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2450 if (!IS_ELF)
31312f95
AM		 2451 return 1;
2452
a161fe53
AM		 2453 /* Don't adjust pc-relative references to merge sections in 64-bit
2454 mode. */
2455 if (use_rela_relocations
2456 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2457 && fixP->fx_pcrel)
252b5132 2458 return 0;
31312f95 2459
8d01d9a9
AJ		 2460 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2461 and changed later by validate_fix. */
2462 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2463 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2464 return 0;
2465
ce8a8b2f 2466 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2467 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2468 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2469 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2470 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2471 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2472 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2473 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2474 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2475 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2476 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2477 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2478 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2479 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2480 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2481 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2482 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2483 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2484 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2485 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2486 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2487 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2488 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2489 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2490 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2491 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2492 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2493 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2494 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2495 return 0;
31312f95 2496#endif
252b5132
RH		 2497 return 1;
2498}
252b5132 2499
b4cac588 2500static int
e3bb37b5 2501intel_float_operand (const char *mnemonic)
252b5132 2502{
9306ca4a
JB		 2503 /* Note that the value returned is meaningful only for opcodes with (memory)
2504 operands, hence the code here is free to improperly handle opcodes that
2505 have no operands (for better performance and smaller code). */
2506
2507 if (mnemonic[0] != 'f')
2508 return 0; /* non-math */
2509
2510 switch (mnemonic[1])
2511 {
2512 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2513 the fs segment override prefix not currently handled because no
2514 call path can make opcodes without operands get here */
2515 case 'i':
2516 return 2 /* integer op */;
2517 case 'l':
2518 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2519 return 3; /* fldcw/fldenv */
2520 break;
2521 case 'n':
2522 if (mnemonic[2] != 'o' /* fnop */)
2523 return 3; /* non-waiting control op */
2524 break;
2525 case 'r':
2526 if (mnemonic[2] == 's')
2527 return 3; /* frstor/frstpm */
2528 break;
2529 case 's':
2530 if (mnemonic[2] == 'a')
2531 return 3; /* fsave */
2532 if (mnemonic[2] == 't')
2533 {
2534 switch (mnemonic[3])
2535 {
2536 case 'c': /* fstcw */
2537 case 'd': /* fstdw */
2538 case 'e': /* fstenv */
2539 case 's': /* fsts[gw] */
2540 return 3;
2541 }
2542 }
2543 break;
2544 case 'x':
2545 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2546 return 0; /* fxsave/fxrstor are not really math ops */
2547 break;
2548 }
252b5132 2549
9306ca4a 2550 return 1;
252b5132
RH		 2551}
2552
c0f3af97
L		 2553/* Build the VEX prefix. */
2554
2555static void
fa99fab2 2556build_vex_prefix (const template *t)
c0f3af97
L		 2557{
2558 unsigned int register_specifier;
2559 unsigned int implied_prefix;
2560 unsigned int vector_length;
2561
2562 /* Check register specifier. */
2563 if (i.vex.register_specifier)
2564 {
2565 register_specifier = i.vex.register_specifier->reg_num;
2566 if ((i.vex.register_specifier->reg_flags & RegRex))
2567 register_specifier += 8;
2568 register_specifier = ~register_specifier & 0xf;
2569 }
2570 else
2571 register_specifier = 0xf;
2572
fa99fab2
L		 2573 /* Use 2-byte VEX prefix by swappping destination and source
2574 operand. */
2575 if (!i.swap_operand
2576 && i.operands == i.reg_operands
2577 && i.tm.opcode_modifier.vex0f
2578 && i.tm.opcode_modifier.s
2579 && i.rex == REX_B)
2580 {
2581 unsigned int xchg = i.operands - 1;
2582 union i386_op temp_op;
2583 i386_operand_type temp_type;
2584
2585 temp_type = i.types[xchg];
2586 i.types[xchg] = i.types[0];
2587 i.types[0] = temp_type;
2588 temp_op = i.op[xchg];
2589 i.op[xchg] = i.op[0];
2590 i.op[0] = temp_op;
2591
2592 assert (i.rm.mode == 3);
2593
2594 i.rex = REX_R;
2595 xchg = i.rm.regmem;
2596 i.rm.regmem = i.rm.reg;
2597 i.rm.reg = xchg;
2598
2599 /* Use the next insn. */
2600 i.tm = t[1];
2601 }
2602
c0f3af97
L		 2603 vector_length = i.tm.opcode_modifier.vex256 ? 1 : 0;
2604
2605 switch ((i.tm.base_opcode >> 8) & 0xff)
2606 {
2607 case 0:
2608 implied_prefix = 0;
2609 break;
2610 case DATA_PREFIX_OPCODE:
2611 implied_prefix = 1;
2612 break;
2613 case REPE_PREFIX_OPCODE:
2614 implied_prefix = 2;
2615 break;
2616 case REPNE_PREFIX_OPCODE:
2617 implied_prefix = 3;
2618 break;
2619 default:
2620 abort ();
2621 }
2622
2623 /* Use 2-byte VEX prefix if possible. */
2624 if (i.tm.opcode_modifier.vex0f
2625 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2626 {
2627 /* 2-byte VEX prefix. */
2628 unsigned int r;
2629
2630 i.vex.length = 2;
2631 i.vex.bytes[0] = 0xc5;
2632
2633 /* Check the REX.R bit. */
2634 r = (i.rex & REX_R) ? 0 : 1;
2635 i.vex.bytes[1] = (r << 7
2636 | register_specifier << 3
2637 | vector_length << 2
2638 | implied_prefix);
2639 }
2640 else
2641 {
2642 /* 3-byte VEX prefix. */
2643 unsigned int m, w;
2644
2645 if (i.tm.opcode_modifier.vex0f)
2646 m = 0x1;
2647 else if (i.tm.opcode_modifier.vex0f38)
2648 m = 0x2;
2649 else if (i.tm.opcode_modifier.vex0f3a)
2650 m = 0x3;
2651 else
2652 abort ();
2653
2654 i.vex.length = 3;
2655 i.vex.bytes[0] = 0xc4;
2656
2657 /* The high 3 bits of the second VEX byte are 1's compliment
2658 of RXB bits from REX. */
2659 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2660
2661 /* Check the REX.W bit. */
2662 w = (i.rex & REX_W) ? 1 : 0;
2663 if (i.tm.opcode_modifier.vexw0 || i.tm.opcode_modifier.vexw1)
2664 {
2665 if (w)
2666 abort ();
2667
2668 if (i.tm.opcode_modifier.vexw1)
2669 w = 1;
2670 }
2671
2672 i.vex.bytes[2] = (w << 7
2673 | register_specifier << 3
2674 | vector_length << 2
2675 | implied_prefix);
2676 }
2677}
2678
65da13b5
L		 2679static void
2680process_immext (void)
2681{
2682 expressionS *exp;
2683
2684 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2685 {
1fed0ba1
L		 2686 /* SSE3 Instructions have the fixed operands with an opcode
2687 suffix which is coded in the same place as an 8-bit immediate
2688 field would be. Here we check those operands and remove them
2689 afterwards. */
65da13b5
L		 2690 unsigned int x;
2691
2692 for (x = 0; x < i.operands; x++)
2693 if (i.op[x].regs->reg_num != x)
2694 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2695 register_prefix, i.op[x].regs->reg_name, x + 1,
2696 i.tm.name);
2697
2698 i.operands = 0;
65da13b5
L		 2699 }
2700
c0f3af97 2701 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2702 which is coded in the same place as an 8-bit immediate field
2703 would be. Here we fake an 8-bit immediate operand from the
2704 opcode suffix stored in tm.extension_opcode.
2705
c0f3af97
L		 2706 SSE5 and AVX instructions also use this encoding, for some of
2707 3 argument instructions. */
65da13b5
L		 2708
2709 assert (i.imm_operands == 0
2710 && (i.operands <= 2
2711 || (i.tm.cpu_flags.bitfield.cpusse5
c0f3af97
L		 2712 && i.operands <= 3)
2713 || (i.tm.opcode_modifier.vex
2714 && i.operands <= 4)));
65da13b5
L		 2715
2716 exp = &im_expressions[i.imm_operands++];
2717 i.op[i.operands].imms = exp;
2718 i.types[i.operands] = imm8;
2719 i.operands++;
2720 exp->X_op = O_constant;
2721 exp->X_add_number = i.tm.extension_opcode;
2722 i.tm.extension_opcode = None;
2723}
2724
252b5132
RH		 2725/* This is the guts of the machine-dependent assembler. LINE points to a
2726 machine dependent instruction. This function is supposed to emit
2727 the frags/bytes it assembles to. */
2728
2729void
65da13b5 2730md_assemble (char *line)
252b5132 2731{
40fb9820 2732 unsigned int j;
252b5132 2733 char mnemonic[MAX_MNEM_SIZE];
fa99fab2 2734 const template *t;
252b5132 2735
47926f60 2736 /* Initialize globals. */
252b5132
RH		 2737 memset (&i, '\0', sizeof (i));
2738 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2739 i.reloc[j] = NO_RELOC;
252b5132
RH		 2740 memset (disp_expressions, '\0', sizeof (disp_expressions));
2741 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2742 save_stack_p = save_stack;
252b5132
RH		 2743
2744 /* First parse an instruction mnemonic & call i386_operand for the operands.
2745 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2746 start of a (possibly prefixed) mnemonic. */
252b5132 2747
29b0f896
AM		 2748 line = parse_insn (line, mnemonic);
2749 if (line == NULL)
2750 return;
252b5132 2751
29b0f896
AM		 2752 line = parse_operands (line, mnemonic);
2753 if (line == NULL)
2754 return;
252b5132 2755
29b0f896
AM		 2756 /* Now we've parsed the mnemonic into a set of templates, and have the
2757 operands at hand. */
2758
2759 /* All intel opcodes have reversed operands except for "bound" and
2760 "enter". We also don't reverse intersegment "jmp" and "call"
2761 instructions with 2 immediate operands so that the immediate segment
050dfa73 2762 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2763 if (intel_syntax
2764 && i.operands > 1
29b0f896 2765 && (strcmp (mnemonic, "bound") != 0)
30123838 2766 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2767 && !(operand_type_check (i.types[0], imm)
2768 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2769 swap_operands ();
2770
ec56d5c0
JB		 2771 /* The order of the immediates should be reversed
2772 for 2 immediates extrq and insertq instructions */
2773 if (i.imm_operands == 2
2774 && (strcmp (mnemonic, "extrq") == 0
2775 || strcmp (mnemonic, "insertq") == 0))
2776 swap_2_operands (0, 1);
2777
29b0f896
AM		 2778 if (i.imm_operands)
2779 optimize_imm ();
2780
b300c311
L		 2781 /* Don't optimize displacement for movabs since it only takes 64bit
2782 displacement. */
2783 if (i.disp_operands
2784 && (flag_code != CODE_64BIT
2785 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2786 optimize_disp ();
2787
2788 /* Next, we find a template that matches the given insn,
2789 making sure the overlap of the given operands types is consistent
2790 with the template operand types. */
252b5132 2791
fa99fab2 2792 if (!(t = match_template ()))
29b0f896 2793 return;
252b5132 2794
daf50ae7 2795 if (sse_check != sse_check_none
81f8a913 2796 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 2797 && (i.tm.cpu_flags.bitfield.cpusse
2798 || i.tm.cpu_flags.bitfield.cpusse2
2799 || i.tm.cpu_flags.bitfield.cpusse3
2800 || i.tm.cpu_flags.bitfield.cpussse3
2801 || i.tm.cpu_flags.bitfield.cpusse4_1
2802 || i.tm.cpu_flags.bitfield.cpusse4_2))
2803 {
2804 (sse_check == sse_check_warning
2805 ? as_warn
2806 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
2807 }
2808
321fd21e
L		 2809 /* Zap movzx and movsx suffix. The suffix has been set from
2810 "word ptr" or "byte ptr" on the source operand in Intel syntax
2811 or extracted from mnemonic in AT&T syntax. But we'll use
2812 the destination register to choose the suffix for encoding. */
2813 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 2814 {
321fd21e
L		 2815 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2816 there is no suffix, the default will be byte extension. */
2817 if (i.reg_operands != 2
2818 && !i.suffix
2819 && intel_syntax)
2820 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2821
2822 i.suffix = 0;
cd61ebfe 2823 }
24eab124 2824
40fb9820 2825 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2826 if (!add_prefix (FWAIT_OPCODE))
2827 return;
252b5132 2828
29b0f896 2829 /* Check string instruction segment overrides. */
40fb9820 2830 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2831 {
2832 if (!check_string ())
5dd0794d 2833 return;
fc0763e6 2834 i.disp_operands = 0;
29b0f896 2835 }
5dd0794d 2836
29b0f896
AM		 2837 if (!process_suffix ())
2838 return;
e413e4e9 2839
29b0f896
AM		 2840 /* Make still unresolved immediate matches conform to size of immediate
2841 given in i.suffix. */
2842 if (!finalize_imm ())
2843 return;
252b5132 2844
40fb9820 2845 if (i.types[0].bitfield.imm1)
29b0f896 2846 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2847
40fb9820 2848 for (j = 0; j < 3; j++)
c6fb90c8
L		 2849 if (i.types[j].bitfield.inoutportreg
2850 || i.types[j].bitfield.shiftcount
2851 || i.types[j].bitfield.acc
2852 || i.types[j].bitfield.floatacc)
40fb9820
L		 2853 i.reg_operands--;
2854
c0f3af97
L		 2855 /* ImmExt should be processed after SSE2AVX. */
2856 if (!i.tm.opcode_modifier.sse2avx
2857 && i.tm.opcode_modifier.immext)
65da13b5 2858 process_immext ();
252b5132 2859
29b0f896
AM		 2860 /* For insns with operands there are more diddles to do to the opcode. */
2861 if (i.operands)
2862 {
2863 if (!process_operands ())
2864 return;
2865 }
40fb9820 2866 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2867 {
2868 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2869 as_warn (_("translating to `%sp'"), i.tm.name);
2870 }
252b5132 2871
c0f3af97 2872 if (i.tm.opcode_modifier.vex)
fa99fab2 2873 build_vex_prefix (t);
c0f3af97 2874
29b0f896
AM		 2875 /* Handle conversion of 'int $3' --> special int3 insn. */
2876 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2877 {
2878 i.tm.base_opcode = INT3_OPCODE;
2879 i.imm_operands = 0;
2880 }
252b5132 2881
40fb9820
L		 2882 if ((i.tm.opcode_modifier.jump
2883 || i.tm.opcode_modifier.jumpbyte
2884 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2885 && i.op[0].disps->X_op == O_constant)
2886 {
2887 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2888 the absolute address given by the constant. Since ix86 jumps and
2889 calls are pc relative, we need to generate a reloc. */
2890 i.op[0].disps->X_add_symbol = &abs_symbol;
2891 i.op[0].disps->X_op = O_symbol;
2892 }
252b5132 2893
40fb9820 2894 if (i.tm.opcode_modifier.rex64)
161a04f6 2895 i.rex |= REX_W;
252b5132 2896
29b0f896
AM		 2897 /* For 8 bit registers we need an empty rex prefix. Also if the
2898 instruction already has a prefix, we need to convert old
2899 registers to new ones. */
773f551c 2900
40fb9820 2901 if ((i.types[0].bitfield.reg8
29b0f896 2902 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2903 || (i.types[1].bitfield.reg8
29b0f896 2904 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2905 || ((i.types[0].bitfield.reg8
2906 || i.types[1].bitfield.reg8)
29b0f896
AM		 2907 && i.rex != 0))
2908 {
2909 int x;
726c5dcd 2910
29b0f896
AM		 2911 i.rex |= REX_OPCODE;
2912 for (x = 0; x < 2; x++)
2913 {
2914 /* Look for 8 bit operand that uses old registers. */
40fb9820 2915 if (i.types[x].bitfield.reg8
29b0f896 2916 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2917 {
29b0f896
AM		 2918 /* In case it is "hi" register, give up. */
2919 if (i.op[x].regs->reg_num > 3)
a540244d 2920 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2921 "instruction requiring REX prefix."),
a540244d 2922 register_prefix, i.op[x].regs->reg_name);
773f551c 2923
29b0f896
AM		 2924 /* Otherwise it is equivalent to the extended register.
2925 Since the encoding doesn't change this is merely
2926 cosmetic cleanup for debug output. */
2927
2928 i.op[x].regs = i.op[x].regs + 8;
773f551c 2929 }
29b0f896
AM		 2930 }
2931 }
773f551c 2932
85f10a01
MM		 2933 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2934 REX prefix. */
2935 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2936 {
2937 i.drex.rex = i.rex;
2938 i.rex = 0;
2939 }
2940 else if (i.rex != 0)
29b0f896
AM		 2941 add_prefix (REX_OPCODE | i.rex);
2942
2943 /* We are ready to output the insn. */
2944 output_insn ();
2945}
2946
2947static char *
e3bb37b5 2948parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2949{
2950 char *l = line;
2951 char *token_start = l;
2952 char *mnem_p;
5c6af06e
JB		 2953 int supported;
2954 const template *t;
b6169b20 2955 char *dot_p = NULL;
29b0f896
AM		 2956
2957 /* Non-zero if we found a prefix only acceptable with string insns. */
2958 const char *expecting_string_instruction = NULL;
45288df1 2959
29b0f896
AM		 2960 while (1)
2961 {
2962 mnem_p = mnemonic;
2963 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2964 {
b6169b20
L		 2965 if (*mnem_p == '.')
2966 dot_p = mnem_p;
29b0f896
AM		 2967 mnem_p++;
2968 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2969 {
29b0f896
AM		 2970 as_bad (_("no such instruction: `%s'"), token_start);
2971 return NULL;
2972 }
2973 l++;
2974 }
2975 if (!is_space_char (*l)
2976 && *l != END_OF_INSN
e44823cf
JB		 2977 && (intel_syntax
2978 || (*l != PREFIX_SEPARATOR
2979 && *l != ',')))
29b0f896
AM		 2980 {
2981 as_bad (_("invalid character %s in mnemonic"),
2982 output_invalid (*l));
2983 return NULL;
2984 }
2985 if (token_start == l)
2986 {
e44823cf 2987 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2988 as_bad (_("expecting prefix; got nothing"));
2989 else
2990 as_bad (_("expecting mnemonic; got nothing"));
2991 return NULL;
2992 }
45288df1 2993
29b0f896
AM		 2994 /* Look up instruction (or prefix) via hash table. */
2995 current_templates = hash_find (op_hash, mnemonic);
47926f60 2996
29b0f896
AM		 2997 if (*l != END_OF_INSN
2998 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2999 && current_templates
40fb9820 3000 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3001 {
c6fb90c8 3002 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3003 {
3004 as_bad ((flag_code != CODE_64BIT
3005 ? _("`%s' is only supported in 64-bit mode")
3006 : _("`%s' is not supported in 64-bit mode")),
3007 current_templates->start->name);
3008 return NULL;
3009 }
29b0f896
AM		 3010 /* If we are in 16-bit mode, do not allow addr16 or data16.
3011 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3012 if ((current_templates->start->opcode_modifier.size16
3013 || current_templates->start->opcode_modifier.size32)
29b0f896 3014 && flag_code != CODE_64BIT
40fb9820 3015 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3016 ^ (flag_code == CODE_16BIT)))
3017 {
3018 as_bad (_("redundant %s prefix"),
3019 current_templates->start->name);
3020 return NULL;
45288df1 3021 }
29b0f896
AM		 3022 /* Add prefix, checking for repeated prefixes. */
3023 switch (add_prefix (current_templates->start->base_opcode))
3024 {
3025 case 0:
3026 return NULL;
3027 case 2:
3028 expecting_string_instruction = current_templates->start->name;
3029 break;
3030 }
3031 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3032 token_start = ++l;
3033 }
3034 else
3035 break;
3036 }
45288df1 3037
30a55f88 3038 if (!current_templates)
b6169b20 3039 {
30a55f88
L		 3040 /* Check if we should swap operand in encoding. */
3041 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3042 i.swap_operand = 1;
3043 else
3044 goto check_suffix;
3045 mnem_p = dot_p;
3046 *dot_p = '\0';
3047 current_templates = hash_find (op_hash, mnemonic);
b6169b20
L		 3048 }
3049
29b0f896
AM		 3050 if (!current_templates)
3051 {
b6169b20 3052check_suffix:
29b0f896
AM		 3053 /* See if we can get a match by trimming off a suffix. */
3054 switch (mnem_p[-1])
3055 {
3056 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3057 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3058 i.suffix = SHORT_MNEM_SUFFIX;
3059 else
29b0f896
AM		 3060 case BYTE_MNEM_SUFFIX:
3061 case QWORD_MNEM_SUFFIX:
3062 i.suffix = mnem_p[-1];
3063 mnem_p[-1] = '\0';
3064 current_templates = hash_find (op_hash, mnemonic);
3065 break;
3066 case SHORT_MNEM_SUFFIX:
3067 case LONG_MNEM_SUFFIX:
3068 if (!intel_syntax)
3069 {
3070 i.suffix = mnem_p[-1];
3071 mnem_p[-1] = '\0';
3072 current_templates = hash_find (op_hash, mnemonic);
3073 }
3074 break;
252b5132 3075
29b0f896
AM		 3076 /* Intel Syntax. */
3077 case 'd':
3078 if (intel_syntax)
3079 {
9306ca4a 3080 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3081 i.suffix = SHORT_MNEM_SUFFIX;
3082 else
3083 i.suffix = LONG_MNEM_SUFFIX;
3084 mnem_p[-1] = '\0';
3085 current_templates = hash_find (op_hash, mnemonic);
3086 }
3087 break;
3088 }
3089 if (!current_templates)
3090 {
3091 as_bad (_("no such instruction: `%s'"), token_start);
3092 return NULL;
3093 }
3094 }
252b5132 3095
40fb9820
L		 3096 if (current_templates->start->opcode_modifier.jump
3097 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3098 {
3099 /* Check for a branch hint. We allow ",pt" and ",pn" for
3100 predict taken and predict not taken respectively.
3101 I'm not sure that branch hints actually do anything on loop
3102 and jcxz insns (JumpByte) for current Pentium4 chips. They
3103 may work in the future and it doesn't hurt to accept them
3104 now. */
3105 if (l[0] == ',' && l[1] == 'p')
3106 {
3107 if (l[2] == 't')
3108 {
3109 if (!add_prefix (DS_PREFIX_OPCODE))
3110 return NULL;
3111 l += 3;
3112 }
3113 else if (l[2] == 'n')
3114 {
3115 if (!add_prefix (CS_PREFIX_OPCODE))
3116 return NULL;
3117 l += 3;
3118 }
3119 }
3120 }
3121 /* Any other comma loses. */
3122 if (*l == ',')
3123 {
3124 as_bad (_("invalid character %s in mnemonic"),
3125 output_invalid (*l));
3126 return NULL;
3127 }
252b5132 3128
29b0f896 3129 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3130 supported = 0;
3131 for (t = current_templates->start; t < current_templates->end; ++t)
3132 {
c0f3af97
L		 3133 supported |= cpu_flags_match (t);
3134 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3135 goto skip;
5c6af06e 3136 }
3629bb00 3137
c0f3af97 3138 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3139 {
3140 as_bad (flag_code == CODE_64BIT
3141 ? _("`%s' is not supported in 64-bit mode")
3142 : _("`%s' is only supported in 64-bit mode"),
3143 current_templates->start->name);
3144 return NULL;
3145 }
c0f3af97 3146 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3147 {
3629bb00
L		 3148 as_bad (_("`%s' is not supported on `%s%s'"),
3149 current_templates->start->name, cpu_arch_name,
3150 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3151 return NULL;
29b0f896 3152 }
3629bb00
L		 3153
3154skip:
3155 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3156 && (flag_code != CODE_16BIT))
29b0f896
AM		 3157 {
3158 as_warn (_("use .code16 to ensure correct addressing mode"));
3159 }
252b5132 3160
29b0f896 3161 /* Check for rep/repne without a string instruction. */
f41bbced 3162 if (expecting_string_instruction)
29b0f896 3163 {
f41bbced
JB		 3164 static templates override;
3165
3166 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3167 if (t->opcode_modifier.isstring)
f41bbced
JB		 3168 break;
3169 if (t >= current_templates->end)
3170 {
3171 as_bad (_("expecting string instruction after `%s'"),
64e74474 3172 expecting_string_instruction);
f41bbced
JB		 3173 return NULL;
3174 }
3175 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3176 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3177 break;
3178 override.end = t;
3179 current_templates = &override;
29b0f896 3180 }
252b5132 3181
29b0f896
AM		 3182 return l;
3183}
252b5132 3184
29b0f896 3185static char *
e3bb37b5 3186parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3187{
3188 char *token_start;
3138f287 3189
29b0f896
AM		 3190 /* 1 if operand is pending after ','. */
3191 unsigned int expecting_operand = 0;
252b5132 3192
29b0f896
AM		 3193 /* Non-zero if operand parens not balanced. */
3194 unsigned int paren_not_balanced;
3195
3196 while (*l != END_OF_INSN)
3197 {
3198 /* Skip optional white space before operand. */
3199 if (is_space_char (*l))
3200 ++l;
3201 if (!is_operand_char (*l) && *l != END_OF_INSN)
3202 {
3203 as_bad (_("invalid character %s before operand %d"),
3204 output_invalid (*l),
3205 i.operands + 1);
3206 return NULL;
3207 }
3208 token_start = l; /* after white space */
3209 paren_not_balanced = 0;
3210 while (paren_not_balanced || *l != ',')
3211 {
3212 if (*l == END_OF_INSN)
3213 {
3214 if (paren_not_balanced)
3215 {
3216 if (!intel_syntax)
3217 as_bad (_("unbalanced parenthesis in operand %d."),
3218 i.operands + 1);
3219 else
3220 as_bad (_("unbalanced brackets in operand %d."),
3221 i.operands + 1);
3222 return NULL;
3223 }
3224 else
3225 break; /* we are done */
3226 }
3227 else if (!is_operand_char (*l) && !is_space_char (*l))
3228 {
3229 as_bad (_("invalid character %s in operand %d"),
3230 output_invalid (*l),
3231 i.operands + 1);
3232 return NULL;
3233 }
3234 if (!intel_syntax)
3235 {
3236 if (*l == '(')
3237 ++paren_not_balanced;
3238 if (*l == ')')
3239 --paren_not_balanced;
3240 }
3241 else
3242 {
3243 if (*l == '[')
3244 ++paren_not_balanced;
3245 if (*l == ']')
3246 --paren_not_balanced;
3247 }
3248 l++;
3249 }
3250 if (l != token_start)
3251 { /* Yes, we've read in another operand. */
3252 unsigned int operand_ok;
3253 this_operand = i.operands++;
7d5e4556 3254 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3255 if (i.operands > MAX_OPERANDS)
3256 {
3257 as_bad (_("spurious operands; (%d operands/instruction max)"),
3258 MAX_OPERANDS);
3259 return NULL;
3260 }
3261 /* Now parse operand adding info to 'i' as we go along. */
3262 END_STRING_AND_SAVE (l);
3263
3264 if (intel_syntax)
3265 operand_ok =
3266 i386_intel_operand (token_start,
3267 intel_float_operand (mnemonic));
3268 else
a7619375 3269 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3270
3271 RESTORE_END_STRING (l);
3272 if (!operand_ok)
3273 return NULL;
3274 }
3275 else
3276 {
3277 if (expecting_operand)
3278 {
3279 expecting_operand_after_comma:
3280 as_bad (_("expecting operand after ','; got nothing"));
3281 return NULL;
3282 }
3283 if (*l == ',')
3284 {
3285 as_bad (_("expecting operand before ','; got nothing"));
3286 return NULL;
3287 }
3288 }
7f3f1ea2 3289
29b0f896
AM		 3290 /* Now *l must be either ',' or END_OF_INSN. */
3291 if (*l == ',')
3292 {
3293 if (*++l == END_OF_INSN)
3294 {
3295 /* Just skip it, if it's \n complain. */
3296 goto expecting_operand_after_comma;
3297 }
3298 expecting_operand = 1;
3299 }
3300 }
3301 return l;
3302}
7f3f1ea2 3303
050dfa73 3304static void
4d456e3d 3305swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3306{
3307 union i386_op temp_op;
40fb9820 3308 i386_operand_type temp_type;
050dfa73 3309 enum bfd_reloc_code_real temp_reloc;
4eed87de 3310
050dfa73
MM		 3311 temp_type = i.types[xchg2];
3312 i.types[xchg2] = i.types[xchg1];
3313 i.types[xchg1] = temp_type;
3314 temp_op = i.op[xchg2];
3315 i.op[xchg2] = i.op[xchg1];
3316 i.op[xchg1] = temp_op;
3317 temp_reloc = i.reloc[xchg2];
3318 i.reloc[xchg2] = i.reloc[xchg1];
3319 i.reloc[xchg1] = temp_reloc;
3320}
3321
29b0f896 3322static void
e3bb37b5 3323swap_operands (void)
29b0f896 3324{
b7c61d9a 3325 switch (i.operands)
050dfa73 3326 {
c0f3af97 3327 case 5:
b7c61d9a 3328 case 4:
4d456e3d 3329 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3330 case 3:
3331 case 2:
4d456e3d 3332 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3333 break;
3334 default:
3335 abort ();
29b0f896 3336 }
29b0f896
AM		 3337
3338 if (i.mem_operands == 2)
3339 {
3340 const seg_entry *temp_seg;
3341 temp_seg = i.seg[0];
3342 i.seg[0] = i.seg[1];
3343 i.seg[1] = temp_seg;
3344 }
3345}
252b5132 3346
29b0f896
AM		 3347/* Try to ensure constant immediates are represented in the smallest
3348 opcode possible. */
3349static void
e3bb37b5 3350optimize_imm (void)
29b0f896
AM		 3351{
3352 char guess_suffix = 0;
3353 int op;
252b5132 3354
29b0f896
AM		 3355 if (i.suffix)
3356 guess_suffix = i.suffix;
3357 else if (i.reg_operands)
3358 {
3359 /* Figure out a suffix from the last register operand specified.
3360 We can't do this properly yet, ie. excluding InOutPortReg,
3361 but the following works for instructions with immediates.
3362 In any case, we can't set i.suffix yet. */
3363 for (op = i.operands; --op >= 0;)
40fb9820
L		 3364 if (i.types[op].bitfield.reg8)
3365 {
3366 guess_suffix = BYTE_MNEM_SUFFIX;
3367 break;
3368 }
3369 else if (i.types[op].bitfield.reg16)
252b5132 3370 {
40fb9820
L		 3371 guess_suffix = WORD_MNEM_SUFFIX;
3372 break;
3373 }
3374 else if (i.types[op].bitfield.reg32)
3375 {
3376 guess_suffix = LONG_MNEM_SUFFIX;
3377 break;
3378 }
3379 else if (i.types[op].bitfield.reg64)
3380 {
3381 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3382 break;
252b5132 3383 }
29b0f896
AM		 3384 }
3385 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3386 guess_suffix = WORD_MNEM_SUFFIX;
3387
3388 for (op = i.operands; --op >= 0;)
40fb9820 3389 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3390 {
3391 switch (i.op[op].imms->X_op)
252b5132 3392 {
29b0f896
AM		 3393 case O_constant:
3394 /* If a suffix is given, this operand may be shortened. */
3395 switch (guess_suffix)
252b5132 3396 {
29b0f896 3397 case LONG_MNEM_SUFFIX:
40fb9820
L		 3398 i.types[op].bitfield.imm32 = 1;
3399 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3400 break;
3401 case WORD_MNEM_SUFFIX:
40fb9820
L		 3402 i.types[op].bitfield.imm16 = 1;
3403 i.types[op].bitfield.imm32 = 1;
3404 i.types[op].bitfield.imm32s = 1;
3405 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3406 break;
3407 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3408 i.types[op].bitfield.imm8 = 1;
3409 i.types[op].bitfield.imm8s = 1;
3410 i.types[op].bitfield.imm16 = 1;
3411 i.types[op].bitfield.imm32 = 1;
3412 i.types[op].bitfield.imm32s = 1;
3413 i.types[op].bitfield.imm64 = 1;
29b0f896 3414 break;
252b5132 3415 }
252b5132 3416
29b0f896
AM		 3417 /* If this operand is at most 16 bits, convert it
3418 to a signed 16 bit number before trying to see
3419 whether it will fit in an even smaller size.
3420 This allows a 16-bit operand such as $0xffe0 to
3421 be recognised as within Imm8S range. */
40fb9820 3422 if ((i.types[op].bitfield.imm16)
29b0f896 3423 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3424 {
29b0f896
AM		 3425 i.op[op].imms->X_add_number =
3426 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3427 }
40fb9820 3428 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3429 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3430 == 0))
3431 {
3432 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3433 ^ ((offsetT) 1 << 31))
3434 - ((offsetT) 1 << 31));
3435 }
40fb9820 3436 i.types[op]
c6fb90c8
L		 3437 = operand_type_or (i.types[op],
3438 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3439
29b0f896
AM		 3440 /* We must avoid matching of Imm32 templates when 64bit
3441 only immediate is available. */
3442 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3443 i.types[op].bitfield.imm32 = 0;
29b0f896 3444 break;
252b5132 3445
29b0f896
AM		 3446 case O_absent:
3447 case O_register:
3448 abort ();
3449
3450 /* Symbols and expressions. */
3451 default:
9cd96992
JB		 3452 /* Convert symbolic operand to proper sizes for matching, but don't
3453 prevent matching a set of insns that only supports sizes other
3454 than those matching the insn suffix. */
3455 {
40fb9820 3456 i386_operand_type mask, allowed;
9cd96992
JB		 3457 const template *t;
3458
0dfbf9d7
L		 3459 operand_type_set (&mask, 0);
3460 operand_type_set (&allowed, 0);
40fb9820 3461
4eed87de
AM		 3462 for (t = current_templates->start;
3463 t < current_templates->end;
3464 ++t)
c6fb90c8
L		 3465 allowed = operand_type_or (allowed,
3466 t->operand_types[op]);
9cd96992
JB		 3467 switch (guess_suffix)
3468 {
3469 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3470 mask.bitfield.imm64 = 1;
3471 mask.bitfield.imm32s = 1;
9cd96992
JB		 3472 break;
3473 case LONG_MNEM_SUFFIX:
40fb9820 3474 mask.bitfield.imm32 = 1;
9cd96992
JB		 3475 break;
3476 case WORD_MNEM_SUFFIX:
40fb9820 3477 mask.bitfield.imm16 = 1;
9cd96992
JB		 3478 break;
3479 case BYTE_MNEM_SUFFIX:
40fb9820 3480 mask.bitfield.imm8 = 1;
9cd96992
JB		 3481 break;
3482 default:
9cd96992
JB		 3483 break;
3484 }
c6fb90c8 3485 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3486 if (!operand_type_all_zero (&allowed))
c6fb90c8 3487 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3488 }
29b0f896 3489 break;
252b5132 3490 }
29b0f896
AM		 3491 }
3492}
47926f60 3493
29b0f896
AM		 3494/* Try to use the smallest displacement type too. */
3495static void
e3bb37b5 3496optimize_disp (void)
29b0f896
AM		 3497{
3498 int op;
3e73aa7c 3499
29b0f896 3500 for (op = i.operands; --op >= 0;)
40fb9820 3501 if (operand_type_check (i.types[op], disp))
252b5132 3502 {
b300c311 3503 if (i.op[op].disps->X_op == O_constant)
252b5132 3504 {
b300c311 3505 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 3506
40fb9820 3507 if (i.types[op].bitfield.disp16
b300c311
L		 3508 && (disp & ~(offsetT) 0xffff) == 0)
3509 {
3510 /* If this operand is at most 16 bits, convert
3511 to a signed 16 bit number and don't use 64bit
3512 displacement. */
3513 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3514 i.types[op].bitfield.disp64 = 0;
b300c311 3515 }
40fb9820 3516 if (i.types[op].bitfield.disp32
b300c311
L		 3517 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3518 {
3519 /* If this operand is at most 32 bits, convert
3520 to a signed 32 bit number and don't use 64bit
3521 displacement. */
3522 disp &= (((offsetT) 2 << 31) - 1);
3523 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3524 i.types[op].bitfield.disp64 = 0;
b300c311 3525 }
40fb9820 3526 if (!disp && i.types[op].bitfield.baseindex)
b300c311 3527 {
40fb9820
L		 3528 i.types[op].bitfield.disp8 = 0;
3529 i.types[op].bitfield.disp16 = 0;
3530 i.types[op].bitfield.disp32 = 0;
3531 i.types[op].bitfield.disp32s = 0;
3532 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3533 i.op[op].disps = 0;
3534 i.disp_operands--;
3535 }
3536 else if (flag_code == CODE_64BIT)
3537 {
3538 if (fits_in_signed_long (disp))
28a9d8f5 3539 {
40fb9820
L		 3540 i.types[op].bitfield.disp64 = 0;
3541 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3542 }
b300c311 3543 if (fits_in_unsigned_long (disp))
40fb9820 3544 i.types[op].bitfield.disp32 = 1;
b300c311 3545 }
40fb9820
L		 3546 if ((i.types[op].bitfield.disp32
3547 || i.types[op].bitfield.disp32s
3548 || i.types[op].bitfield.disp16)
b300c311 3549 && fits_in_signed_byte (disp))
40fb9820 3550 i.types[op].bitfield.disp8 = 1;
252b5132 3551 }
67a4f2b7
AO		 3552 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3553 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3554 {
3555 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3556 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3557 i.types[op].bitfield.disp8 = 0;
3558 i.types[op].bitfield.disp16 = 0;
3559 i.types[op].bitfield.disp32 = 0;
3560 i.types[op].bitfield.disp32s = 0;
3561 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3562 }
3563 else
b300c311 3564 /* We only support 64bit displacement on constants. */
40fb9820 3565 i.types[op].bitfield.disp64 = 0;
252b5132 3566 }
29b0f896
AM		 3567}
3568
c0f3af97
L		 3569/* Check if operands are valid for the instrucrtion. Update VEX
3570 operand types. */
3571
3572static int
3573VEX_check_operands (const template *t)
3574{
3575 if (!t->opcode_modifier.vex)
3576 return 0;
3577
3578 /* Only check VEX_Imm4, which must be the first operand. */
3579 if (t->operand_types[0].bitfield.vex_imm4)
3580 {
3581 if (i.op[0].imms->X_op != O_constant
3582 || !fits_in_imm4 (i.op[0].imms->X_add_number))
3583 return 1;
3584
3585 /* Turn off Imm8 so that update_imm won't complain. */
3586 i.types[0] = vex_imm4;
3587 }
3588
3589 return 0;
3590}
3591
fa99fab2 3592static const template *
e3bb37b5 3593match_template (void)
29b0f896
AM		 3594{
3595 /* Points to template once we've found it. */
3596 const template *t;
40fb9820 3597 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3598 i386_operand_type overlap4;
29b0f896 3599 unsigned int found_reverse_match;
40fb9820
L		 3600 i386_opcode_modifier suffix_check;
3601 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3602 int addr_prefix_disp;
a5c311ca 3603 unsigned int j;
3629bb00 3604 unsigned int found_cpu_match;
45664ddb 3605 unsigned int check_register;
29b0f896 3606
c0f3af97
L		 3607#if MAX_OPERANDS != 5
3608# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3609#endif
3610
29b0f896 3611 found_reverse_match = 0;
539e75ad 3612 addr_prefix_disp = -1;
40fb9820
L		 3613
3614 memset (&suffix_check, 0, sizeof (suffix_check));
3615 if (i.suffix == BYTE_MNEM_SUFFIX)
3616 suffix_check.no_bsuf = 1;
3617 else if (i.suffix == WORD_MNEM_SUFFIX)
3618 suffix_check.no_wsuf = 1;
3619 else if (i.suffix == SHORT_MNEM_SUFFIX)
3620 suffix_check.no_ssuf = 1;
3621 else if (i.suffix == LONG_MNEM_SUFFIX)
3622 suffix_check.no_lsuf = 1;
3623 else if (i.suffix == QWORD_MNEM_SUFFIX)
3624 suffix_check.no_qsuf = 1;
3625 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3626 suffix_check.no_ldsuf = 1;
29b0f896 3627
45aa61fe 3628 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3629 {
539e75ad
L		 3630 addr_prefix_disp = -1;
3631
29b0f896
AM		 3632 /* Must have right number of operands. */
3633 if (i.operands != t->operands)
3634 continue;
3635
50aecf8c 3636 /* Check processor support. */
c0f3af97
L		 3637 found_cpu_match = (cpu_flags_match (t)
3638 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3639 if (!found_cpu_match)
3640 continue;
3641
e1d4d893
L		 3642 /* Check old gcc support. */
3643 if (!old_gcc && t->opcode_modifier.oldgcc)
3644 continue;
3645
3646 /* Check AT&T mnemonic. */
3647 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3648 continue;
3649
5c07affc
L		 3650 /* Check AT&T syntax Intel syntax. */
3651 if ((intel_syntax && t->opcode_modifier.attsyntax)
3652 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3653 continue;
3654
20592a94 3655 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3656 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3657 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3658 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3659 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3660 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3661 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3662 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3663 continue;
3664
5c07affc 3665 if (!operand_size_match (t))
7d5e4556 3666 continue;
539e75ad 3667
5c07affc
L		 3668 for (j = 0; j < MAX_OPERANDS; j++)
3669 operand_types[j] = t->operand_types[j];
3670
45aa61fe
AM		 3671 /* In general, don't allow 64-bit operands in 32-bit mode. */
3672 if (i.suffix == QWORD_MNEM_SUFFIX
3673 && flag_code != CODE_64BIT
3674 && (intel_syntax
40fb9820 3675 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3676 && !intel_float_operand (t->name))
3677 : intel_float_operand (t->name) != 2)
40fb9820 3678 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3679 && !operand_types[0].bitfield.regxmm
3680 && !operand_types[0].bitfield.regymm)
40fb9820 3681 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3682 && !!operand_types[t->operands > 1].bitfield.regxmm
3683 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3684 && (t->base_opcode != 0x0fc7
3685 || t->extension_opcode != 1 /* cmpxchg8b */))
3686 continue;
3687
192dc9c6
JB		 3688 /* In general, don't allow 32-bit operands on pre-386. */
3689 else if (i.suffix == LONG_MNEM_SUFFIX
3690 && !cpu_arch_flags.bitfield.cpui386
3691 && (intel_syntax
3692 ? (!t->opcode_modifier.ignoresize
3693 && !intel_float_operand (t->name))
3694 : intel_float_operand (t->name) != 2)
3695 && ((!operand_types[0].bitfield.regmmx
3696 && !operand_types[0].bitfield.regxmm)
3697 || (!operand_types[t->operands > 1].bitfield.regmmx
3698 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3699 continue;
3700
29b0f896 3701 /* Do not verify operands when there are none. */
50aecf8c 3702 else
29b0f896 3703 {
c6fb90c8 3704 if (!t->operands)
2dbab7d5
L		 3705 /* We've found a match; break out of loop. */
3706 break;
29b0f896 3707 }
252b5132 3708
539e75ad
L		 3709 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3710 into Disp32/Disp16/Disp32 operand. */
3711 if (i.prefix[ADDR_PREFIX] != 0)
3712 {
40fb9820 3713 /* There should be only one Disp operand. */
539e75ad
L		 3714 switch (flag_code)
3715 {
3716 case CODE_16BIT:
40fb9820
L		 3717 for (j = 0; j < MAX_OPERANDS; j++)
3718 {
3719 if (operand_types[j].bitfield.disp16)
3720 {
3721 addr_prefix_disp = j;
3722 operand_types[j].bitfield.disp32 = 1;
3723 operand_types[j].bitfield.disp16 = 0;
3724 break;
3725 }
3726 }
539e75ad
L		 3727 break;
3728 case CODE_32BIT:
40fb9820
L		 3729 for (j = 0; j < MAX_OPERANDS; j++)
3730 {
3731 if (operand_types[j].bitfield.disp32)
3732 {
3733 addr_prefix_disp = j;
3734 operand_types[j].bitfield.disp32 = 0;
3735 operand_types[j].bitfield.disp16 = 1;
3736 break;
3737 }
3738 }
539e75ad
L		 3739 break;
3740 case CODE_64BIT:
40fb9820
L		 3741 for (j = 0; j < MAX_OPERANDS; j++)
3742 {
3743 if (operand_types[j].bitfield.disp64)
3744 {
3745 addr_prefix_disp = j;
3746 operand_types[j].bitfield.disp64 = 0;
3747 operand_types[j].bitfield.disp32 = 1;
3748 break;
3749 }
3750 }
539e75ad
L		 3751 break;
3752 }
539e75ad
L		 3753 }
3754
45664ddb
L		 3755 /* We check register size only if size of operands can be
3756 encoded the canonical way. */
3757 check_register = t->opcode_modifier.w;
c6fb90c8 3758 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3759 switch (t->operands)
3760 {
3761 case 1:
40fb9820 3762 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3763 continue;
3764 break;
3765 case 2:
8b38ad71
L		 3766 /* xchg %eax, %eax is a special case. It is an aliase for nop
3767 only in 32bit mode and we can use opcode 0x90. In 64bit
3768 mode, we can't use 0x90 for xchg %eax, %eax since it should
3769 zero-extend %eax to %rax. */
3770 if (flag_code == CODE_64BIT
3771 && t->base_opcode == 0x90
0dfbf9d7
L		 3772 && operand_type_equal (&i.types [0], &acc32)
3773 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 3774 continue;
b6169b20
L		 3775 if (i.swap_operand)
3776 {
3777 /* If we swap operand in encoding, we either match
3778 the next one or reverse direction of operands. */
3779 if (t->opcode_modifier.s)
3780 continue;
3781 else if (t->opcode_modifier.d)
3782 goto check_reverse;
3783 }
3784
29b0f896 3785 case 3:
fa99fab2
L		 3786 /* If we swap operand in encoding, we match the next one. */
3787 if (i.swap_operand && t->opcode_modifier.s)
3788 continue;
f48ff2ae 3789 case 4:
c0f3af97 3790 case 5:
c6fb90c8 3791 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3792 if (!operand_type_match (overlap0, i.types[0])
3793 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3794 || (check_register
3795 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3796 operand_types[0],
3797 overlap1, i.types[1],
3798 operand_types[1])))
29b0f896
AM		 3799 {
3800 /* Check if other direction is valid ... */
40fb9820 3801 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3802 continue;
3803
b6169b20 3804check_reverse:
29b0f896 3805 /* Try reversing direction of operands. */
c6fb90c8
L		 3806 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3807 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3808 if (!operand_type_match (overlap0, i.types[0])
3809 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3810 || (check_register
3811 && !operand_type_register_match (overlap0,
3812 i.types[0],
3813 operand_types[1],
3814 overlap1,
3815 i.types[1],
3816 operand_types[0])))
29b0f896
AM		 3817 {
3818 /* Does not match either direction. */
3819 continue;
3820 }
3821 /* found_reverse_match holds which of D or FloatDR
3822 we've found. */
40fb9820 3823 if (t->opcode_modifier.d)
8a2ed489 3824 found_reverse_match = Opcode_D;
40fb9820 3825 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3826 found_reverse_match = Opcode_FloatD;
3827 else
3828 found_reverse_match = 0;
40fb9820 3829 if (t->opcode_modifier.floatr)
8a2ed489 3830 found_reverse_match |= Opcode_FloatR;
29b0f896 3831 }
f48ff2ae 3832 else
29b0f896 3833 {
f48ff2ae 3834 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3835 switch (t->operands)
3836 {
c0f3af97
L		 3837 case 5:
3838 overlap4 = operand_type_and (i.types[4],
3839 operand_types[4]);
d1cbb4db 3840 case 4:
c6fb90c8
L		 3841 overlap3 = operand_type_and (i.types[3],
3842 operand_types[3]);
d1cbb4db 3843 case 3:
c6fb90c8
L		 3844 overlap2 = operand_type_and (i.types[2],
3845 operand_types[2]);
d1cbb4db
L		 3846 break;
3847 }
29b0f896 3848
f48ff2ae
L		 3849 switch (t->operands)
3850 {
c0f3af97
L		 3851 case 5:
3852 if (!operand_type_match (overlap4, i.types[4])
3853 || !operand_type_register_match (overlap3,
3854 i.types[3],
3855 operand_types[3],
3856 overlap4,
3857 i.types[4],
3858 operand_types[4]))
3859 continue;
f48ff2ae 3860 case 4:
40fb9820 3861 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 3862 || (check_register
3863 && !operand_type_register_match (overlap2,
3864 i.types[2],
3865 operand_types[2],
3866 overlap3,
3867 i.types[3],
3868 operand_types[3])))
f48ff2ae
L		 3869 continue;
3870 case 3:
3871 /* Here we make use of the fact that there are no
3872 reverse match 3 operand instructions, and all 3
3873 operand instructions only need to be checked for
3874 register consistency between operands 2 and 3. */
40fb9820 3875 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 3876 || (check_register
3877 && !operand_type_register_match (overlap1,
3878 i.types[1],
3879 operand_types[1],
3880 overlap2,
3881 i.types[2],
3882 operand_types[2])))
f48ff2ae
L		 3883 continue;
3884 break;
3885 }
29b0f896 3886 }
f48ff2ae 3887 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3888 slip through to break. */
3889 }
3629bb00 3890 if (!found_cpu_match)
29b0f896
AM		 3891 {
3892 found_reverse_match = 0;
3893 continue;
3894 }
c0f3af97
L		 3895
3896 /* Check if VEX operands are valid. */
3897 if (VEX_check_operands (t))
3898 continue;
3899
29b0f896
AM		 3900 /* We've found a match; break out of loop. */
3901 break;
3902 }
3903
3904 if (t == current_templates->end)
3905 {
3906 /* We found no match. */
95f283e8
L		 3907 if (intel_syntax)
3908 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3909 current_templates->start->name);
3910 else
3911 as_bad (_("suffix or operands invalid for `%s'"),
3912 current_templates->start->name);
fa99fab2 3913 return NULL;
29b0f896 3914 }
252b5132 3915
29b0f896
AM		 3916 if (!quiet_warnings)
3917 {
3918 if (!intel_syntax
40fb9820
L		 3919 && (i.types[0].bitfield.jumpabsolute
3920 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3921 {
3922 as_warn (_("indirect %s without `*'"), t->name);
3923 }
3924
40fb9820
L		 3925 if (t->opcode_modifier.isprefix
3926 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3927 {
3928 /* Warn them that a data or address size prefix doesn't
3929 affect assembly of the next line of code. */
3930 as_warn (_("stand-alone `%s' prefix"), t->name);
3931 }
3932 }
3933
3934 /* Copy the template we found. */
3935 i.tm = *t;
539e75ad
L		 3936
3937 if (addr_prefix_disp != -1)
3938 i.tm.operand_types[addr_prefix_disp]
3939 = operand_types[addr_prefix_disp];
3940
29b0f896
AM		 3941 if (found_reverse_match)
3942 {
3943 /* If we found a reverse match we must alter the opcode
3944 direction bit. found_reverse_match holds bits to change
3945 (different for int & float insns). */
3946
3947 i.tm.base_opcode ^= found_reverse_match;
3948
539e75ad
L		 3949 i.tm.operand_types[0] = operand_types[1];
3950 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3951 }
3952
fa99fab2 3953 return t;
29b0f896
AM		 3954}
3955
3956static int
e3bb37b5 3957check_string (void)
29b0f896 3958{
40fb9820
L		 3959 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3960 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3961 {
3962 if (i.seg[0] != NULL && i.seg[0] != &es)
3963 {
a87af027 3964 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 3965 i.tm.name,
a87af027
JB		 3966 mem_op + 1,
3967 register_prefix);
29b0f896
AM		 3968 return 0;
3969 }
3970 /* There's only ever one segment override allowed per instruction.
3971 This instruction possibly has a legal segment override on the
3972 second operand, so copy the segment to where non-string
3973 instructions store it, allowing common code. */
3974 i.seg[0] = i.seg[1];
3975 }
40fb9820 3976 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3977 {
3978 if (i.seg[1] != NULL && i.seg[1] != &es)
3979 {
a87af027 3980 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 3981 i.tm.name,
a87af027
JB		 3982 mem_op + 2,
3983 register_prefix);
29b0f896
AM		 3984 return 0;
3985 }
3986 }
3987 return 1;
3988}
3989
3990static int
543613e9 3991process_suffix (void)
29b0f896
AM		 3992{
3993 /* If matched instruction specifies an explicit instruction mnemonic
3994 suffix, use it. */
40fb9820
L		 3995 if (i.tm.opcode_modifier.size16)
3996 i.suffix = WORD_MNEM_SUFFIX;
3997 else if (i.tm.opcode_modifier.size32)
3998 i.suffix = LONG_MNEM_SUFFIX;
3999 else if (i.tm.opcode_modifier.size64)
4000 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 4001 else if (i.reg_operands)
4002 {
4003 /* If there's no instruction mnemonic suffix we try to invent one
4004 based on register operands. */
4005 if (!i.suffix)
4006 {
4007 /* We take i.suffix from the last register operand specified,
4008 Destination register type is more significant than source
381d071f
L		 4009 register type. crc32 in SSE4.2 prefers source register
4010 type. */
4011 if (i.tm.base_opcode == 0xf20f38f1)
4012 {
40fb9820
L		 4013 if (i.types[0].bitfield.reg16)
4014 i.suffix = WORD_MNEM_SUFFIX;
4015 else if (i.types[0].bitfield.reg32)
4016 i.suffix = LONG_MNEM_SUFFIX;
4017 else if (i.types[0].bitfield.reg64)
4018 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4019 }
9344ff29 4020 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4021 {
40fb9820 4022 if (i.types[0].bitfield.reg8)
20592a94
L		 4023 i.suffix = BYTE_MNEM_SUFFIX;
4024 }
381d071f
L		 4025
4026 if (!i.suffix)
4027 {
4028 int op;
4029
20592a94
L		 4030 if (i.tm.base_opcode == 0xf20f38f1
4031 || i.tm.base_opcode == 0xf20f38f0)
4032 {
4033 /* We have to know the operand size for crc32. */
4034 as_bad (_("ambiguous memory operand size for `%s`"),
4035 i.tm.name);
4036 return 0;
4037 }
4038
381d071f 4039 for (op = i.operands; --op >= 0;)
40fb9820 4040 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4041 {
40fb9820
L		 4042 if (i.types[op].bitfield.reg8)
4043 {
4044 i.suffix = BYTE_MNEM_SUFFIX;
4045 break;
4046 }
4047 else if (i.types[op].bitfield.reg16)
4048 {
4049 i.suffix = WORD_MNEM_SUFFIX;
4050 break;
4051 }
4052 else if (i.types[op].bitfield.reg32)
4053 {
4054 i.suffix = LONG_MNEM_SUFFIX;
4055 break;
4056 }
4057 else if (i.types[op].bitfield.reg64)
4058 {
4059 i.suffix = QWORD_MNEM_SUFFIX;
4060 break;
4061 }
381d071f
L		 4062 }
4063 }
29b0f896
AM		 4064 }
4065 else if (i.suffix == BYTE_MNEM_SUFFIX)
4066 {
4067 if (!check_byte_reg ())
4068 return 0;
4069 }
4070 else if (i.suffix == LONG_MNEM_SUFFIX)
4071 {
4072 if (!check_long_reg ())
4073 return 0;
4074 }
4075 else if (i.suffix == QWORD_MNEM_SUFFIX)
4076 {
955e1e6a
L		 4077 if (intel_syntax
4078 && i.tm.opcode_modifier.ignoresize
4079 && i.tm.opcode_modifier.no_qsuf)
4080 i.suffix = 0;
4081 else if (!check_qword_reg ())
29b0f896
AM		 4082 return 0;
4083 }
4084 else if (i.suffix == WORD_MNEM_SUFFIX)
4085 {
4086 if (!check_word_reg ())
4087 return 0;
4088 }
c0f3af97
L		 4089 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4090 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4091 {
c0f3af97 4092 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4093 should check if it is a valid suffix. */
4094 }
40fb9820 4095 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4096 /* Do nothing if the instruction is going to ignore the prefix. */
4097 ;
4098 else
4099 abort ();
4100 }
40fb9820 4101 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4102 && !i.suffix
4103 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4104 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4105 {
4106 i.suffix = stackop_size;
4107 }
9306ca4a
JB		 4108 else if (intel_syntax
4109 && !i.suffix
40fb9820
L		 4110 && (i.tm.operand_types[0].bitfield.jumpabsolute
4111 || i.tm.opcode_modifier.jumpbyte
4112 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4113 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4114 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4115 {
4116 switch (flag_code)
4117 {
4118 case CODE_64BIT:
40fb9820 4119 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4120 {
4121 i.suffix = QWORD_MNEM_SUFFIX;
4122 break;
4123 }
4124 case CODE_32BIT:
40fb9820 4125 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4126 i.suffix = LONG_MNEM_SUFFIX;
4127 break;
4128 case CODE_16BIT:
40fb9820 4129 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4130 i.suffix = WORD_MNEM_SUFFIX;
4131 break;
4132 }
4133 }
252b5132 4134
9306ca4a 4135 if (!i.suffix)
29b0f896 4136 {
9306ca4a
JB		 4137 if (!intel_syntax)
4138 {
40fb9820 4139 if (i.tm.opcode_modifier.w)
9306ca4a 4140 {
4eed87de
AM		 4141 as_bad (_("no instruction mnemonic suffix given and "
4142 "no register operands; can't size instruction"));
9306ca4a
JB		 4143 return 0;
4144 }
4145 }
4146 else
4147 {
40fb9820
L		 4148 unsigned int suffixes;
4149
4150 suffixes = !i.tm.opcode_modifier.no_bsuf;
4151 if (!i.tm.opcode_modifier.no_wsuf)
4152 suffixes |= 1 << 1;
4153 if (!i.tm.opcode_modifier.no_lsuf)
4154 suffixes |= 1 << 2;
fc4adea1 4155 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4156 suffixes |= 1 << 3;
4157 if (!i.tm.opcode_modifier.no_ssuf)
4158 suffixes |= 1 << 4;
4159 if (!i.tm.opcode_modifier.no_qsuf)
4160 suffixes |= 1 << 5;
4161
4162 /* There are more than suffix matches. */
4163 if (i.tm.opcode_modifier.w
9306ca4a 4164 || ((suffixes & (suffixes - 1))
40fb9820
L		 4165 && !i.tm.opcode_modifier.defaultsize
4166 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4167 {
4168 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4169 return 0;
4170 }
4171 }
29b0f896 4172 }
252b5132 4173
9306ca4a
JB		 4174 /* Change the opcode based on the operand size given by i.suffix;
4175 We don't need to change things for byte insns. */
4176
582d5edd
L		 4177 if (i.suffix
4178 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4179 && i.suffix != XMMWORD_MNEM_SUFFIX
4180 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4181 {
4182 /* It's not a byte, select word/dword operation. */
40fb9820 4183 if (i.tm.opcode_modifier.w)
29b0f896 4184 {
40fb9820 4185 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4186 i.tm.base_opcode |= 8;
4187 else
4188 i.tm.base_opcode |= 1;
4189 }
0f3f3d8b 4190
29b0f896
AM		 4191 /* Now select between word & dword operations via the operand
4192 size prefix, except for instructions that will ignore this
4193 prefix anyway. */
ca61edf2 4194 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4195 {
ca61edf2
L		 4196 /* The address size override prefix changes the size of the
4197 first operand. */
40fb9820
L		 4198 if ((flag_code == CODE_32BIT
4199 && i.op->regs[0].reg_type.bitfield.reg16)
4200 || (flag_code != CODE_32BIT
4201 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4202 if (!add_prefix (ADDR_PREFIX_OPCODE))
4203 return 0;
4204 }
4205 else if (i.suffix != QWORD_MNEM_SUFFIX
4206 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4207 && !i.tm.opcode_modifier.ignoresize
4208 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4209 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4210 || (flag_code == CODE_64BIT
40fb9820 4211 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4212 {
4213 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4214
40fb9820 4215 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4216 prefix = ADDR_PREFIX_OPCODE;
252b5132 4217
29b0f896
AM		 4218 if (!add_prefix (prefix))
4219 return 0;
24eab124 4220 }
252b5132 4221
29b0f896
AM		 4222 /* Set mode64 for an operand. */
4223 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4224 && flag_code == CODE_64BIT
40fb9820 4225 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4226 {
4227 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4228 need rex64. cmpxchg8b is also a special case. */
4229 if (! (i.operands == 2
4230 && i.tm.base_opcode == 0x90
4231 && i.tm.extension_opcode == None
0dfbf9d7
L		 4232 && operand_type_equal (&i.types [0], &acc64)
4233 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4234 && ! (i.operands == 1
4235 && i.tm.base_opcode == 0xfc7
4236 && i.tm.extension_opcode == 1
40fb9820
L		 4237 && !operand_type_check (i.types [0], reg)
4238 && operand_type_check (i.types [0], anymem)))
f6bee062 4239 i.rex |= REX_W;
46e883c5 4240 }
3e73aa7c 4241
29b0f896
AM		 4242 /* Size floating point instruction. */
4243 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4244 if (i.tm.opcode_modifier.floatmf)
543613e9 4245 i.tm.base_opcode ^= 4;
29b0f896 4246 }
7ecd2f8b 4247
29b0f896
AM		 4248 return 1;
4249}
3e73aa7c 4250
29b0f896 4251static int
543613e9 4252check_byte_reg (void)
29b0f896
AM		 4253{
4254 int op;
543613e9 4255
29b0f896
AM		 4256 for (op = i.operands; --op >= 0;)
4257 {
4258 /* If this is an eight bit register, it's OK. If it's the 16 or
4259 32 bit version of an eight bit register, we will just use the
4260 low portion, and that's OK too. */
40fb9820 4261 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4262 continue;
4263
ca61edf2
L		 4264 /* Don't generate this warning if not needed. */
4265 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
29b0f896
AM		 4266 continue;
4267
9344ff29
L		 4268 /* crc32 doesn't generate this warning. */
4269 if (i.tm.base_opcode == 0xf20f38f0)
4270 continue;
4271
40fb9820
L		 4272 if ((i.types[op].bitfield.reg16
4273 || i.types[op].bitfield.reg32
4274 || i.types[op].bitfield.reg64)
4275 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4276 {
4277 /* Prohibit these changes in the 64bit mode, since the
4278 lowering is more complicated. */
4279 if (flag_code == CODE_64BIT
40fb9820 4280 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4281 {
2ca3ace5
L		 4282 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4283 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4284 i.suffix);
4285 return 0;
4286 }
4287#if REGISTER_WARNINGS
4288 if (!quiet_warnings
40fb9820 4289 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4290 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4291 register_prefix,
40fb9820 4292 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4293 ? REGNAM_AL - REGNAM_AX
4294 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4295 register_prefix,
29b0f896
AM		 4296 i.op[op].regs->reg_name,
4297 i.suffix);
4298#endif
4299 continue;
4300 }
4301 /* Any other register is bad. */
40fb9820
L		 4302 if (i.types[op].bitfield.reg16
4303 || i.types[op].bitfield.reg32
4304 || i.types[op].bitfield.reg64
4305 || i.types[op].bitfield.regmmx
4306 || i.types[op].bitfield.regxmm
c0f3af97 4307 || i.types[op].bitfield.regymm
40fb9820
L		 4308 || i.types[op].bitfield.sreg2
4309 || i.types[op].bitfield.sreg3
4310 || i.types[op].bitfield.control
4311 || i.types[op].bitfield.debug
4312 || i.types[op].bitfield.test
4313 || i.types[op].bitfield.floatreg
4314 || i.types[op].bitfield.floatacc)
29b0f896 4315 {
a540244d
L		 4316 as_bad (_("`%s%s' not allowed with `%s%c'"),
4317 register_prefix,
29b0f896
AM		 4318 i.op[op].regs->reg_name,
4319 i.tm.name,
4320 i.suffix);
4321 return 0;
4322 }
4323 }
4324 return 1;
4325}
4326
4327static int
e3bb37b5 4328check_long_reg (void)
29b0f896
AM		 4329{
4330 int op;
4331
4332 for (op = i.operands; --op >= 0;)
4333 /* Reject eight bit registers, except where the template requires
4334 them. (eg. movzb) */
40fb9820
L		 4335 if (i.types[op].bitfield.reg8
4336 && (i.tm.operand_types[op].bitfield.reg16
4337 || i.tm.operand_types[op].bitfield.reg32
4338 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4339 {
a540244d
L		 4340 as_bad (_("`%s%s' not allowed with `%s%c'"),
4341 register_prefix,
29b0f896
AM		 4342 i.op[op].regs->reg_name,
4343 i.tm.name,
4344 i.suffix);
4345 return 0;
4346 }
4347 /* Warn if the e prefix on a general reg is missing. */
4348 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4349 && i.types[op].bitfield.reg16
4350 && (i.tm.operand_types[op].bitfield.reg32
4351 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4352 {
4353 /* Prohibit these changes in the 64bit mode, since the
4354 lowering is more complicated. */
4355 if (flag_code == CODE_64BIT)
252b5132 4356 {
2ca3ace5
L		 4357 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4358 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4359 i.suffix);
4360 return 0;
252b5132 4361 }
29b0f896
AM		 4362#if REGISTER_WARNINGS
4363 else
a540244d
L		 4364 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4365 register_prefix,
29b0f896 4366 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4367 register_prefix,
29b0f896
AM		 4368 i.op[op].regs->reg_name,
4369 i.suffix);
4370#endif
252b5132 4371 }
29b0f896 4372 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4373 else if (i.types[op].bitfield.reg64
4374 && (i.tm.operand_types[op].bitfield.reg32
4375 || i.tm.operand_types[op].bitfield.acc))
252b5132 4376 {
34828aad 4377 if (intel_syntax
ca61edf2 4378 && i.tm.opcode_modifier.toqword
40fb9820 4379 && !i.types[0].bitfield.regxmm)
34828aad 4380 {
ca61edf2 4381 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4382 i.suffix = QWORD_MNEM_SUFFIX;
4383 }
4384 else
4385 {
4386 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4387 register_prefix, i.op[op].regs->reg_name,
4388 i.suffix);
4389 return 0;
4390 }
29b0f896
AM		 4391 }
4392 return 1;
4393}
252b5132 4394
29b0f896 4395static int
e3bb37b5 4396check_qword_reg (void)
29b0f896
AM		 4397{
4398 int op;
252b5132 4399
29b0f896
AM		 4400 for (op = i.operands; --op >= 0; )
4401 /* Reject eight bit registers, except where the template requires
4402 them. (eg. movzb) */
40fb9820
L		 4403 if (i.types[op].bitfield.reg8
4404 && (i.tm.operand_types[op].bitfield.reg16
4405 || i.tm.operand_types[op].bitfield.reg32
4406 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4407 {
a540244d
L		 4408 as_bad (_("`%s%s' not allowed with `%s%c'"),
4409 register_prefix,
29b0f896
AM		 4410 i.op[op].regs->reg_name,
4411 i.tm.name,
4412 i.suffix);
4413 return 0;
4414 }
4415 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4416 else if ((i.types[op].bitfield.reg16
4417 || i.types[op].bitfield.reg32)
4418 && (i.tm.operand_types[op].bitfield.reg32
4419 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4420 {
4421 /* Prohibit these changes in the 64bit mode, since the
4422 lowering is more complicated. */
34828aad 4423 if (intel_syntax
ca61edf2 4424 && i.tm.opcode_modifier.todword
40fb9820 4425 && !i.types[0].bitfield.regxmm)
34828aad 4426 {
ca61edf2 4427 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4428 i.suffix = LONG_MNEM_SUFFIX;
4429 }
4430 else
4431 {
4432 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4433 register_prefix, i.op[op].regs->reg_name,
4434 i.suffix);
4435 return 0;
4436 }
252b5132 4437 }
29b0f896
AM		 4438 return 1;
4439}
252b5132 4440
29b0f896 4441static int
e3bb37b5 4442check_word_reg (void)
29b0f896
AM		 4443{
4444 int op;
4445 for (op = i.operands; --op >= 0;)
4446 /* Reject eight bit registers, except where the template requires
4447 them. (eg. movzb) */
40fb9820
L		 4448 if (i.types[op].bitfield.reg8
4449 && (i.tm.operand_types[op].bitfield.reg16
4450 || i.tm.operand_types[op].bitfield.reg32
4451 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4452 {
a540244d
L		 4453 as_bad (_("`%s%s' not allowed with `%s%c'"),
4454 register_prefix,
29b0f896
AM		 4455 i.op[op].regs->reg_name,
4456 i.tm.name,
4457 i.suffix);
4458 return 0;
4459 }
4460 /* Warn if the e prefix on a general reg is present. */
4461 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4462 && i.types[op].bitfield.reg32
4463 && (i.tm.operand_types[op].bitfield.reg16
4464 || i.tm.operand_types[op].bitfield.acc))
252b5132 4465 {
29b0f896
AM		 4466 /* Prohibit these changes in the 64bit mode, since the
4467 lowering is more complicated. */
4468 if (flag_code == CODE_64BIT)
252b5132 4469 {
2ca3ace5
L		 4470 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4471 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4472 i.suffix);
4473 return 0;
252b5132 4474 }
29b0f896
AM		 4475 else
4476#if REGISTER_WARNINGS
a540244d
L		 4477 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4478 register_prefix,
29b0f896 4479 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4480 register_prefix,
29b0f896
AM		 4481 i.op[op].regs->reg_name,
4482 i.suffix);
4483#endif
4484 }
4485 return 1;
4486}
252b5132 4487
29b0f896 4488static int
40fb9820 4489update_imm (unsigned int j)
29b0f896 4490{
40fb9820
L		 4491 i386_operand_type overlap;
4492
c6fb90c8 4493 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
40fb9820
L		 4494 if ((overlap.bitfield.imm8
4495 || overlap.bitfield.imm8s
4496 || overlap.bitfield.imm16
4497 || overlap.bitfield.imm32
4498 || overlap.bitfield.imm32s
4499 || overlap.bitfield.imm64)
0dfbf9d7
L		 4500 && !operand_type_equal (&overlap, &imm8)
4501 && !operand_type_equal (&overlap, &imm8s)
4502 && !operand_type_equal (&overlap, &imm16)
4503 && !operand_type_equal (&overlap, &imm32)
4504 && !operand_type_equal (&overlap, &imm32s)
4505 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4506 {
4507 if (i.suffix)
4508 {
40fb9820
L		 4509 i386_operand_type temp;
4510
0dfbf9d7 4511 operand_type_set (&temp, 0);
40fb9820
L		 4512 if (i.suffix == BYTE_MNEM_SUFFIX)
4513 {
4514 temp.bitfield.imm8 = overlap.bitfield.imm8;
4515 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4516 }
4517 else if (i.suffix == WORD_MNEM_SUFFIX)
4518 temp.bitfield.imm16 = overlap.bitfield.imm16;
4519 else if (i.suffix == QWORD_MNEM_SUFFIX)
4520 {
4521 temp.bitfield.imm64 = overlap.bitfield.imm64;
4522 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4523 }
4524 else
4525 temp.bitfield.imm32 = overlap.bitfield.imm32;
4526 overlap = temp;
29b0f896 4527 }
0dfbf9d7
L		 4528 else if (operand_type_equal (&overlap, &imm16_32_32s)
4529 || operand_type_equal (&overlap, &imm16_32)
4530 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4531 {
40fb9820 4532 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4533 overlap = imm16;
40fb9820 4534 else
65da13b5 4535 overlap = imm32s;
29b0f896 4536 }
0dfbf9d7
L		 4537 if (!operand_type_equal (&overlap, &imm8)
4538 && !operand_type_equal (&overlap, &imm8s)
4539 && !operand_type_equal (&overlap, &imm16)
4540 && !operand_type_equal (&overlap, &imm32)
4541 && !operand_type_equal (&overlap, &imm32s)
4542 && !operand_type_equal (&overlap, &imm64))
29b0f896 4543 {
4eed87de
AM		 4544 as_bad (_("no instruction mnemonic suffix given; "
4545 "can't determine immediate size"));
29b0f896
AM		 4546 return 0;
4547 }
4548 }
40fb9820 4549 i.types[j] = overlap;
29b0f896 4550
40fb9820
L		 4551 return 1;
4552}
4553
4554static int
4555finalize_imm (void)
4556{
4557 unsigned int j;
29b0f896 4558
40fb9820
L		 4559 for (j = 0; j < 2; j++)
4560 if (update_imm (j) == 0)
4561 return 0;
4562
c6fb90c8 4563 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
40fb9820 4564 assert (operand_type_check (i.types[2], imm) == 0);
29b0f896
AM		 4565
4566 return 1;
4567}
4568
85f10a01
MM		 4569static void
4570process_drex (void)
4571{
5dd15031
JJ		 4572 i.drex.modrm_reg = 0;
4573 i.drex.modrm_regmem = 0;
85f10a01
MM		 4574
4575 /* SSE5 4 operand instructions must have the destination the same as
4576 one of the inputs. Figure out the destination register and cache
4577 it away in the drex field, and remember which fields to use for
4578 the modrm byte. */
4579 if (i.tm.opcode_modifier.drex
4580 && i.tm.opcode_modifier.drexv
4581 && i.operands == 4)
4582 {
4583 i.tm.extension_opcode = None;
4584
4585 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4586 if (i.types[0].bitfield.regxmm != 0
4587 && i.types[1].bitfield.regxmm != 0
4588 && i.types[2].bitfield.regxmm != 0
4589 && i.types[3].bitfield.regxmm != 0
4590 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4591 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4592 {
4593 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4594 operand_type_set (&i.types[0], 0);
4595 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4596 i.reg_operands -= 2;
4597
4598 /* There are two different ways to encode a 4 operand
4599 instruction with all registers that uses OC1 set to
4600 0 or 1. Favor setting OC1 to 0 since this mimics the
4601 actions of other SSE5 assemblers. Use modrm encoding 2
4602 for register/register. Include the high order bit that
4603 is normally stored in the REX byte in the register
4604 field. */
4605 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4606 i.drex.modrm_reg = 2;
4607 i.drex.modrm_regmem = 1;
4608 i.drex.reg = (i.op[3].regs->reg_num
4609 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4610 }
4611
4612 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4613 else if (i.types[0].bitfield.regxmm != 0
4614 && i.types[1].bitfield.regxmm != 0
4615 && (i.types[2].bitfield.regxmm
4616 || operand_type_check (i.types[2], anymem))
4617 && i.types[3].bitfield.regxmm != 0
4618 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4619 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4620 {
4621 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4622 operand_type_set (&i.types[0], 0);
4623 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4624 i.reg_operands -= 2;
4625
4626 /* Specify the modrm encoding for memory addressing. Include
4627 the high order bit that is normally stored in the REX byte
4628 in the register field. */
4629 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
4630 i.drex.modrm_reg = 1;
4631 i.drex.modrm_regmem = 2;
4632 i.drex.reg = (i.op[3].regs->reg_num
4633 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4634 }
4635
4636 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4637 else if (i.types[0].bitfield.regxmm != 0
4638 && operand_type_check (i.types[1], anymem) != 0
4639 && i.types[2].bitfield.regxmm != 0
4640 && i.types[3].bitfield.regxmm != 0
4641 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4642 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4643 {
4644 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4645 operand_type_set (&i.types[0], 0);
4646 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4647 i.reg_operands -= 2;
4648
4649 /* Specify the modrm encoding for memory addressing. Include
4650 the high order bit that is normally stored in the REX byte
4651 in the register field. */
4652 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4653 i.drex.modrm_reg = 2;
4654 i.drex.modrm_regmem = 1;
4655 i.drex.reg = (i.op[3].regs->reg_num
4656 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4657 }
4658
4659 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4660 else if (i.types[0].bitfield.regxmm != 0
4661 && i.types[1].bitfield.regxmm != 0
4662 && i.types[2].bitfield.regxmm != 0
4663 && i.types[3].bitfield.regxmm != 0
4664 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4665 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4666 {
4667 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4668 operand_type_set (&i.types[2], 0);
4669 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4670 i.reg_operands -= 2;
4671
4672 /* There are two different ways to encode a 4 operand
4673 instruction with all registers that uses OC1 set to
4674 0 or 1. Favor setting OC1 to 0 since this mimics the
4675 actions of other SSE5 assemblers. Use modrm encoding
4676 2 for register/register. Include the high order bit that
4677 is normally stored in the REX byte in the register
4678 field. */
4679 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4680 i.drex.modrm_reg = 1;
4681 i.drex.modrm_regmem = 0;
4682
4683 /* Remember the register, including the upper bits */
4684 i.drex.reg = (i.op[3].regs->reg_num
4685 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4686 }
4687
4688 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4689 else if (i.types[0].bitfield.regxmm != 0
4690 && (i.types[1].bitfield.regxmm
4691 || operand_type_check (i.types[1], anymem))
4692 && i.types[2].bitfield.regxmm != 0
4693 && i.types[3].bitfield.regxmm != 0
4694 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4695 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4696 {
4697 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4698 operand_type_set (&i.types[2], 0);
4699 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4700 i.reg_operands -= 2;
4701
4702 /* Specify the modrm encoding and remember the register
4703 including the bits normally stored in the REX byte. */
4704 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4705 i.drex.modrm_reg = 0;
4706 i.drex.modrm_regmem = 1;
4707 i.drex.reg = (i.op[3].regs->reg_num
4708 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4709 }
4710
4711 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4712 else if (operand_type_check (i.types[0], anymem) != 0
4713 && i.types[1].bitfield.regxmm != 0
4714 && i.types[2].bitfield.regxmm != 0
4715 && i.types[3].bitfield.regxmm != 0
4716 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4717 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4718 {
4719 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4720 operand_type_set (&i.types[2], 0);
4721 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4722 i.reg_operands -= 2;
4723
4724 /* Specify the modrm encoding and remember the register
4725 including the bits normally stored in the REX byte. */
4726 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4727 i.drex.modrm_reg = 1;
4728 i.drex.modrm_regmem = 0;
4729 i.drex.reg = (i.op[3].regs->reg_num
4730 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4731 }
4732
4733 else
4734 as_bad (_("Incorrect operands for the '%s' instruction"),
4735 i.tm.name);
4736 }
4737
4738 /* SSE5 instructions with the DREX byte where the only memory operand
4739 is in the 2nd argument, and the first and last xmm register must
4740 match, and is encoded in the DREX byte. */
4741 else if (i.tm.opcode_modifier.drex
4742 && !i.tm.opcode_modifier.drexv
4743 && i.operands == 4)
4744 {
4745 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4746 if (i.types[0].bitfield.regxmm != 0
4747 && (i.types[1].bitfield.regxmm
4748 || operand_type_check(i.types[1], anymem))
4749 && i.types[2].bitfield.regxmm != 0
4750 && i.types[3].bitfield.regxmm != 0
4751 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4752 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4753 {
4754 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4755 operand_type_set (&i.types[0], 0);
4756 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4757 i.reg_operands -= 2;
4758
4759 /* Specify the modrm encoding and remember the register
4760 including the high bit normally stored in the REX
4761 byte. */
4762 i.drex.modrm_reg = 2;
4763 i.drex.modrm_regmem = 1;
4764 i.drex.reg = (i.op[3].regs->reg_num
4765 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4766 }
4767
4768 else
4769 as_bad (_("Incorrect operands for the '%s' instruction"),
4770 i.tm.name);
4771 }
4772
4773 /* SSE5 3 operand instructions that the result is a register, being
4774 either operand can be a memory operand, using OC0 to note which
4775 one is the memory. */
4776 else if (i.tm.opcode_modifier.drex
4777 && i.tm.opcode_modifier.drexv
4778 && i.operands == 3)
4779 {
4780 i.tm.extension_opcode = None;
4781
4782 /* Case 1: 3 operand insn, src1 = register. */
4783 if (i.types[0].bitfield.regxmm != 0
4784 && i.types[1].bitfield.regxmm != 0
4785 && i.types[2].bitfield.regxmm != 0)
4786 {
4787 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4788 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4789 i.reg_operands--;
4790
4791 /* Specify the modrm encoding and remember the register
4792 including the high bit normally stored in the REX byte. */
4793 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4794 i.drex.modrm_reg = 1;
4795 i.drex.modrm_regmem = 0;
4796 i.drex.reg = (i.op[2].regs->reg_num
4797 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4798 }
4799
4800 /* Case 2: 3 operand insn, src1 = memory. */
4801 else if (operand_type_check (i.types[0], anymem) != 0
4802 && i.types[1].bitfield.regxmm != 0
4803 && i.types[2].bitfield.regxmm != 0)
4804 {
4805 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4806 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4807 i.reg_operands--;
4808
4809 /* Specify the modrm encoding and remember the register
4810 including the high bit normally stored in the REX
4811 byte. */
4812 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4813 i.drex.modrm_reg = 1;
4814 i.drex.modrm_regmem = 0;
4815 i.drex.reg = (i.op[2].regs->reg_num
4816 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4817 }
4818
4819 /* Case 3: 3 operand insn, src2 = memory. */
4820 else if (i.types[0].bitfield.regxmm != 0
4821 && operand_type_check (i.types[1], anymem) != 0
4822 && i.types[2].bitfield.regxmm != 0)
4823 {
4824 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4825 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4826 i.reg_operands--;
4827
4828 /* Specify the modrm encoding and remember the register
4829 including the high bit normally stored in the REX byte. */
4830 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4831 i.drex.modrm_reg = 0;
4832 i.drex.modrm_regmem = 1;
4833 i.drex.reg = (i.op[2].regs->reg_num
4834 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4835 }
4836
4837 else
4838 as_bad (_("Incorrect operands for the '%s' instruction"),
4839 i.tm.name);
4840 }
4841
4842 /* SSE5 4 operand instructions that are the comparison instructions
4843 where the first operand is the immediate value of the comparison
4844 to be done. */
4845 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4846 {
4847 /* Case 1: 4 operand insn, src1 = reg/memory. */
4848 if (operand_type_check (i.types[0], imm) != 0
4849 && (i.types[1].bitfield.regxmm
4850 || operand_type_check (i.types[1], anymem))
4851 && i.types[2].bitfield.regxmm != 0
4852 && i.types[3].bitfield.regxmm != 0)
4853 {
4854 /* clear the arguments that are stored in drex */
0dfbf9d7 4855 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4856 i.reg_operands--;
4857
4858 /* Specify the modrm encoding and remember the register
4859 including the high bit normally stored in the REX byte. */
4860 i.drex.modrm_reg = 2;
4861 i.drex.modrm_regmem = 1;
4862 i.drex.reg = (i.op[3].regs->reg_num
4863 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4864 }
4865
4866 /* Case 2: 3 operand insn with ImmExt that places the
4867 opcode_extension as an immediate argument. This is used for
4868 all of the varients of comparison that supplies the appropriate
4869 value as part of the instruction. */
4870 else if ((i.types[0].bitfield.regxmm
4871 || operand_type_check (i.types[0], anymem))
4872 && i.types[1].bitfield.regxmm != 0
4873 && i.types[2].bitfield.regxmm != 0
4874 && operand_type_check (i.types[3], imm) != 0)
4875 {
4876 /* clear the arguments that are stored in drex */
0dfbf9d7 4877 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4878 i.reg_operands--;
4879
4880 /* Specify the modrm encoding and remember the register
4881 including the high bit normally stored in the REX byte. */
4882 i.drex.modrm_reg = 1;
4883 i.drex.modrm_regmem = 0;
4884 i.drex.reg = (i.op[2].regs->reg_num
4885 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4886 }
4887
4888 else
4889 as_bad (_("Incorrect operands for the '%s' instruction"),
4890 i.tm.name);
4891 }
4892
4893 else if (i.tm.opcode_modifier.drex
4894 || i.tm.opcode_modifier.drexv
4895 || i.tm.opcode_modifier.drexc)
4896 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4897}
4898
c0f3af97
L		 4899static int
4900bad_implicit_operand (int xmm)
4901{
4902 const char *reg = xmm ? "xmm0" : "ymm0";
4903 if (intel_syntax)
4904 as_bad (_("the last operand of `%s' must be `%s%s'"),
4905 i.tm.name, register_prefix, reg);
4906 else
4907 as_bad (_("the first operand of `%s' must be `%s%s'"),
4908 i.tm.name, register_prefix, reg);
4909 return 0;
4910}
4911
29b0f896 4912static int
e3bb37b5 4913process_operands (void)
29b0f896
AM		 4914{
4915 /* Default segment register this instruction will use for memory
4916 accesses. 0 means unknown. This is only for optimizing out
4917 unnecessary segment overrides. */
4918 const seg_entry *default_seg = 0;
4919
85f10a01
MM		 4920 /* Handle all of the DREX munging that SSE5 needs. */
4921 if (i.tm.opcode_modifier.drex
4922 || i.tm.opcode_modifier.drexv
4923 || i.tm.opcode_modifier.drexc)
4924 process_drex ();
4925
c0f3af97
L		 4926 if (i.tm.opcode_modifier.sse2avx
4927 && (i.tm.opcode_modifier.vexnds
4928 || i.tm.opcode_modifier.vexndd))
29b0f896 4929 {
c0f3af97
L		 4930 unsigned int dup = i.operands;
4931 unsigned int dest = dup - 1;
9fcfb3d7
L		 4932 unsigned int j;
4933
c0f3af97 4934 /* The destination must be an xmm register. */
0dfbf9d7 4935 assert (i.reg_operands
c0f3af97
L		 4936 && MAX_OPERANDS > dup
4937 && operand_type_equal (&i.types[dest], &regxmm));
4938
4939 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4940 {
c0f3af97
L		 4941 /* The first operand is implicit and must be xmm0. */
4942 assert (operand_type_equal (&i.types[0], &regxmm));
4943 if (i.op[0].regs->reg_num != 0)
4944 return bad_implicit_operand (1);
4945
4946 if (i.tm.opcode_modifier.vex3sources)
4947 {
4948 /* Keep xmm0 for instructions with VEX prefix and 3
4949 sources. */
4950 goto duplicate;
4951 }
e2ec9d29 4952 else
c0f3af97
L		 4953 {
4954 /* We remove the first xmm0 and keep the number of
4955 operands unchanged, which in fact duplicates the
4956 destination. */
4957 for (j = 1; j < i.operands; j++)
4958 {
4959 i.op[j - 1] = i.op[j];
4960 i.types[j - 1] = i.types[j];
4961 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4962 }
4963 }
4964 }
4965 else if (i.tm.opcode_modifier.implicit1stxmm0)
4966 {
4967 assert ((MAX_OPERANDS - 1) > dup
4968 && i.tm.opcode_modifier.vex3sources);
4969
4970 /* Add the implicit xmm0 for instructions with VEX prefix
4971 and 3 sources. */
4972 for (j = i.operands; j > 0; j--)
4973 {
4974 i.op[j] = i.op[j - 1];
4975 i.types[j] = i.types[j - 1];
4976 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4977 }
4978 i.op[0].regs
4979 = (const reg_entry *) hash_find (reg_hash, "xmm0");
4980 i.types[0] = regxmm;
4981 i.tm.operand_types[0] = regxmm;
4982
4983 i.operands += 2;
4984 i.reg_operands += 2;
4985 i.tm.operands += 2;
4986
4987 dup++;
4988 dest++;
4989 i.op[dup] = i.op[dest];
4990 i.types[dup] = i.types[dest];
4991 i.tm.operand_types[dup] = i.tm.operand_types[dest];
e2ec9d29 4992 }
c0f3af97
L		 4993 else
4994 {
4995duplicate:
4996 i.operands++;
4997 i.reg_operands++;
4998 i.tm.operands++;
4999
5000 i.op[dup] = i.op[dest];
5001 i.types[dup] = i.types[dest];
5002 i.tm.operand_types[dup] = i.tm.operand_types[dest];
5003 }
5004
5005 if (i.tm.opcode_modifier.immext)
5006 process_immext ();
5007 }
5008 else if (i.tm.opcode_modifier.firstxmm0)
5009 {
5010 unsigned int j;
5011
5012 /* The first operand is implicit and must be xmm0/ymm0. */
5013 assert (i.reg_operands
5014 && (operand_type_equal (&i.types[0], &regxmm)
5015 || operand_type_equal (&i.types[0], &regymm)));
5016 if (i.op[0].regs->reg_num != 0)
5017 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5018
5019 for (j = 1; j < i.operands; j++)
5020 {
5021 i.op[j - 1] = i.op[j];
5022 i.types[j - 1] = i.types[j];
5023
5024 /* We need to adjust fields in i.tm since they are used by
5025 build_modrm_byte. */
5026 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5027 }
5028
e2ec9d29
L		 5029 i.operands--;
5030 i.reg_operands--;
e2ec9d29
L		 5031 i.tm.operands--;
5032 }
5033 else if (i.tm.opcode_modifier.regkludge)
5034 {
5035 /* The imul $imm, %reg instruction is converted into
5036 imul $imm, %reg, %reg, and the clr %reg instruction
5037 is converted into xor %reg, %reg. */
5038
5039 unsigned int first_reg_op;
5040
5041 if (operand_type_check (i.types[0], reg))
5042 first_reg_op = 0;
5043 else
5044 first_reg_op = 1;
5045 /* Pretend we saw the extra register operand. */
5046 assert (i.reg_operands == 1
5047 && i.op[first_reg_op + 1].regs == 0);
5048 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5049 i.types[first_reg_op + 1] = i.types[first_reg_op];
5050 i.operands++;
5051 i.reg_operands++;
29b0f896
AM		 5052 }
5053
40fb9820 5054 if (i.tm.opcode_modifier.shortform)
29b0f896 5055 {
40fb9820
L		 5056 if (i.types[0].bitfield.sreg2
5057 || i.types[0].bitfield.sreg3)
29b0f896 5058 {
4eed87de
AM		 5059 if (i.tm.base_opcode == POP_SEG_SHORT
5060 && i.op[0].regs->reg_num == 1)
29b0f896 5061 {
a87af027 5062 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5063 return 0;
29b0f896 5064 }
4eed87de
AM		 5065 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5066 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5067 i.rex |= REX_B;
4eed87de
AM		 5068 }
5069 else
5070 {
85f10a01
MM		 5071 /* The register or float register operand is in operand
5072 0 or 1. */
40fb9820
L		 5073 unsigned int op;
5074
5075 if (i.types[0].bitfield.floatreg
5076 || operand_type_check (i.types[0], reg))
5077 op = 0;
5078 else
5079 op = 1;
4eed87de
AM		 5080 /* Register goes in low 3 bits of opcode. */
5081 i.tm.base_opcode |= i.op[op].regs->reg_num;
5082 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5083 i.rex |= REX_B;
40fb9820 5084 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5085 {
4eed87de
AM		 5086 /* Warn about some common errors, but press on regardless.
5087 The first case can be generated by gcc (<= 2.8.1). */
5088 if (i.operands == 2)
5089 {
5090 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 5091 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
5092 register_prefix, i.op[1].regs->reg_name,
5093 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 5094 }
5095 else
5096 {
5097 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5098 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5099 register_prefix, i.op[0].regs->reg_name);
4eed87de 5100 }
29b0f896
AM		 5101 }
5102 }
5103 }
40fb9820 5104 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5105 {
5106 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5107 must be put into the modrm byte). Now, we make the modrm and
5108 index base bytes based on all the info we've collected. */
29b0f896
AM		 5109
5110 default_seg = build_modrm_byte ();
5111 }
8a2ed489 5112 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5113 {
5114 default_seg = &ds;
5115 }
40fb9820 5116 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5117 {
5118 /* For the string instructions that allow a segment override
5119 on one of their operands, the default segment is ds. */
5120 default_seg = &ds;
5121 }
5122
75178d9d
L		 5123 if (i.tm.base_opcode == 0x8d /* lea */
5124 && i.seg[0]
5125 && !quiet_warnings)
30123838 5126 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5127
5128 /* If a segment was explicitly specified, and the specified segment
5129 is not the default, use an opcode prefix to select it. If we
5130 never figured out what the default segment is, then default_seg
5131 will be zero at this point, and the specified segment prefix will
5132 always be used. */
29b0f896
AM		 5133 if ((i.seg[0]) && (i.seg[0] != default_seg))
5134 {
5135 if (!add_prefix (i.seg[0]->seg_prefix))
5136 return 0;
5137 }
5138 return 1;
5139}
5140
5141static const seg_entry *
e3bb37b5 5142build_modrm_byte (void)
29b0f896
AM		 5143{
5144 const seg_entry *default_seg = 0;
c0f3af97
L		 5145 unsigned int source, dest;
5146 int vex_3_sources;
5147
5148 /* The first operand of instructions with VEX prefix and 3 sources
5149 must be VEX_Imm4. */
5150 vex_3_sources = i.tm.opcode_modifier.vex3sources;
5151 if (vex_3_sources)
5152 {
5153 unsigned int nds, reg;
5154
0bfee649 5155 dest = i.operands - 1;
c0f3af97 5156 nds = dest - 1;
0bfee649
L		 5157 source = 1;
5158 reg = 0;
5159
5160 /* This instruction must have 4 operands: 4 register operands
5161 or 3 register operands plus 1 memory operand. It must have
5162 VexNDS and VexImmExt. */
5163 assert (i.operands == 4
5164 && (i.reg_operands == 4
5165 || (i.reg_operands == 3 && i.mem_operands == 1))
5166 && i.tm.opcode_modifier.vexnds
5167 && i.tm.opcode_modifier.veximmext
5168 && (operand_type_equal (&i.tm.operand_types[dest],
5169 &regxmm)
5170 || operand_type_equal (&i.tm.operand_types[dest],
5171 &regymm))
5172 && (operand_type_equal (&i.tm.operand_types[nds],
5173 &regxmm)
5174 || operand_type_equal (&i.tm.operand_types[nds],
5175 &regymm))
5176 && (operand_type_equal (&i.tm.operand_types[reg],
5177 &regxmm)
c0f3af97 5178 || operand_type_equal (&i.tm.operand_types[reg],
0bfee649 5179 &regymm)));
c0f3af97 5180
0bfee649
L		 5181 /* Generate an 8bit immediate operand to encode the register
5182 operand. */
5183 expressionS *exp = &im_expressions[i.imm_operands++];
5184 i.op[i.operands].imms = exp;
5185 i.types[i.operands] = imm8;
5186 i.operands++;
5187 exp->X_op = O_constant;
5188 exp->X_add_number
5189 = ((i.op[0].regs->reg_num
5190 + ((i.op[0].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
dae39acc 5191
dae39acc 5192 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 5193 }
5194 else
5195 source = dest = 0;
29b0f896 5196
85f10a01
MM		 5197 /* SSE5 4 operand instructions are encoded in such a way that one of
5198 the inputs must match the destination register. Process_drex hides
5199 the 3rd argument in the drex field, so that by the time we get
5200 here, it looks to GAS as if this is a 2 operand instruction. */
5201 if ((i.tm.opcode_modifier.drex
5202 || i.tm.opcode_modifier.drexv
b5016f89 5203 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 5204 && i.reg_operands == 2)
5205 {
5206 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
5207 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
5208
5209 i.rm.reg = reg->reg_num;
5210 i.rm.regmem = regmem->reg_num;
5211 i.rm.mode = 3;
5212 if ((reg->reg_flags & RegRex) != 0)
5213 i.rex |= REX_R;
5214 if ((regmem->reg_flags & RegRex) != 0)
5215 i.rex |= REX_B;
5216 }
5217
29b0f896 5218 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5219 implicit registers do not count. If there are 3 register
5220 operands, it must be a instruction with VexNDS. For a
5221 instruction with VexNDD, the destination register is encoded
5222 in VEX prefix. If there are 4 register operands, it must be
5223 a instruction with VEX prefix and 3 sources. */
5224 else if (i.mem_operands == 0
5225 && ((i.reg_operands == 2
5226 && !i.tm.opcode_modifier.vexndd)
5227 || (i.reg_operands == 3
5228 && i.tm.opcode_modifier.vexnds)
5229 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5230 {
cab737b9
L		 5231 switch (i.operands)
5232 {
5233 case 2:
5234 source = 0;
5235 break;
5236 case 3:
c81128dc
L		 5237 /* When there are 3 operands, one of them may be immediate,
5238 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5239 the first operand must be shift count register (cl) or it
5240 is an instruction with VexNDS. */
c81128dc
L		 5241 assert (i.imm_operands == 1
5242 || (i.imm_operands == 0
c0f3af97
L		 5243 && (i.tm.opcode_modifier.vexnds
5244 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5245 if (operand_type_check (i.types[0], imm)
5246 || i.types[0].bitfield.shiftcount)
5247 source = 1;
5248 else
5249 source = 0;
cab737b9
L		 5250 break;
5251 case 4:
368d64cc
L		 5252 /* When there are 4 operands, the first two must be 8bit
5253 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5254 one.
5255
5256 For instructions with VexNDS, if the first operand
5257 an imm8, the source operand is the 2nd one. If the last
5258 operand is imm8, the source operand is the first one. */
5259 assert ((i.imm_operands == 2
5260 && i.types[0].bitfield.imm8
5261 && i.types[1].bitfield.imm8)
5262 || (i.tm.opcode_modifier.vexnds
5263 && i.imm_operands == 1
5264 && (i.types[0].bitfield.imm8
5265 || i.types[i.operands - 1].bitfield.imm8)));
5266 if (i.tm.opcode_modifier.vexnds)
5267 {
5268 if (i.types[0].bitfield.imm8)
5269 source = 1;
5270 else
5271 source = 0;
5272 }
5273 else
5274 source = 2;
5275 break;
5276 case 5:
cab737b9
L		 5277 break;
5278 default:
5279 abort ();
5280 }
5281
c0f3af97
L		 5282 if (!vex_3_sources)
5283 {
5284 dest = source + 1;
5285
5286 if (i.tm.opcode_modifier.vexnds)
5287 {
5288 /* For instructions with VexNDS, the register-only
5289 source operand must be XMM or YMM register. It is
fa99fab2
L		 5290 encoded in VEX prefix. We need to clear RegMem bit
5291 before calling operand_type_equal. */
5292 i386_operand_type op = i.tm.operand_types[dest];
5293 op.bitfield.regmem = 0;
c0f3af97 5294 if ((dest + 1) >= i.operands
fa99fab2
L		 5295 || (!operand_type_equal (&op, &regxmm)
5296 && !operand_type_equal (&op, &regymm)))
c0f3af97
L		 5297 abort ();
5298 i.vex.register_specifier = i.op[dest].regs;
5299 dest++;
5300 }
5301 }
29b0f896
AM		 5302
5303 i.rm.mode = 3;
5304 /* One of the register operands will be encoded in the i.tm.reg
5305 field, the other in the combined i.tm.mode and i.tm.regmem
5306 fields. If no form of this instruction supports a memory
5307 destination operand, then we assume the source operand may
5308 sometimes be a memory operand and so we need to store the
5309 destination in the i.rm.reg field. */
40fb9820
L		 5310 if (!i.tm.operand_types[dest].bitfield.regmem
5311 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5312 {
5313 i.rm.reg = i.op[dest].regs->reg_num;
5314 i.rm.regmem = i.op[source].regs->reg_num;
5315 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5316 i.rex |= REX_R;
29b0f896 5317 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5318 i.rex |= REX_B;
29b0f896
AM		 5319 }
5320 else
5321 {
5322 i.rm.reg = i.op[source].regs->reg_num;
5323 i.rm.regmem = i.op[dest].regs->reg_num;
5324 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5325 i.rex |= REX_B;
29b0f896 5326 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5327 i.rex |= REX_R;
29b0f896 5328 }
161a04f6 5329 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5330 {
40fb9820
L		 5331 if (!i.types[0].bitfield.control
5332 && !i.types[1].bitfield.control)
c4a530c5 5333 abort ();
161a04f6 5334 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5335 add_prefix (LOCK_PREFIX_OPCODE);
5336 }
29b0f896
AM		 5337 }
5338 else
5339 { /* If it's not 2 reg operands... */
c0f3af97
L		 5340 unsigned int mem;
5341
29b0f896
AM		 5342 if (i.mem_operands)
5343 {
5344 unsigned int fake_zero_displacement = 0;
99018f42 5345 unsigned int op;
4eed87de 5346
85f10a01
MM		 5347 /* This has been precalculated for SSE5 instructions
5348 that have a DREX field earlier in process_drex. */
b5016f89
L		 5349 if (i.tm.opcode_modifier.drex
5350 || i.tm.opcode_modifier.drexv
5351 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 5352 op = i.drex.modrm_regmem;
5353 else
5354 {
c0209578
L		 5355 for (op = 0; op < i.operands; op++)
5356 if (operand_type_check (i.types[op], anymem))
5357 break;
5358 assert (op < i.operands);
85f10a01 5359 }
29b0f896
AM		 5360
5361 default_seg = &ds;
5362
5363 if (i.base_reg == 0)
5364 {
5365 i.rm.mode = 0;
5366 if (!i.disp_operands)
5367 fake_zero_displacement = 1;
5368 if (i.index_reg == 0)
5369 {
5370 /* Operand is just <disp> */
20f0a1fc 5371 if (flag_code == CODE_64BIT)
29b0f896
AM		 5372 {
5373 /* 64bit mode overwrites the 32bit absolute
5374 addressing by RIP relative addressing and
5375 absolute addressing is encoded by one of the
5376 redundant SIB forms. */
5377 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5378 i.sib.base = NO_BASE_REGISTER;
5379 i.sib.index = NO_INDEX_REGISTER;
fc225355 5380 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5381 ? disp32s : disp32);
20f0a1fc 5382 }
fc225355
L		 5383 else if ((flag_code == CODE_16BIT)
5384 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5385 {
5386 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5387 i.types[op] = disp16;
20f0a1fc
NC		 5388 }
5389 else
5390 {
5391 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5392 i.types[op] = disp32;
29b0f896
AM		 5393 }
5394 }
5395 else /* !i.base_reg && i.index_reg */
5396 {
db51cc60
L		 5397 if (i.index_reg->reg_num == RegEiz
5398 || i.index_reg->reg_num == RegRiz)
5399 i.sib.index = NO_INDEX_REGISTER;
5400 else
5401 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5402 i.sib.base = NO_BASE_REGISTER;
5403 i.sib.scale = i.log2_scale_factor;
5404 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5405 i.types[op].bitfield.disp8 = 0;
5406 i.types[op].bitfield.disp16 = 0;
5407 i.types[op].bitfield.disp64 = 0;
29b0f896 5408 if (flag_code != CODE_64BIT)
40fb9820
L		 5409 {
5410 /* Must be 32 bit */
5411 i.types[op].bitfield.disp32 = 1;
5412 i.types[op].bitfield.disp32s = 0;
5413 }
29b0f896 5414 else
40fb9820
L		 5415 {
5416 i.types[op].bitfield.disp32 = 0;
5417 i.types[op].bitfield.disp32s = 1;
5418 }
29b0f896 5419 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5420 i.rex |= REX_X;
29b0f896
AM		 5421 }
5422 }
5423 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5424 else if (i.base_reg->reg_num == RegRip ||
5425 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5426 {
5427 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5428 i.types[op].bitfield.disp8 = 0;
5429 i.types[op].bitfield.disp16 = 0;
5430 i.types[op].bitfield.disp32 = 0;
5431 i.types[op].bitfield.disp32s = 1;
5432 i.types[op].bitfield.disp64 = 0;
71903a11 5433 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5434 if (! i.disp_operands)
5435 fake_zero_displacement = 1;
29b0f896 5436 }
40fb9820 5437 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5438 {
5439 switch (i.base_reg->reg_num)
5440 {
5441 case 3: /* (%bx) */
5442 if (i.index_reg == 0)
5443 i.rm.regmem = 7;
5444 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5445 i.rm.regmem = i.index_reg->reg_num - 6;
5446 break;
5447 case 5: /* (%bp) */
5448 default_seg = &ss;
5449 if (i.index_reg == 0)
5450 {
5451 i.rm.regmem = 6;
40fb9820 5452 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5453 {
5454 /* fake (%bp) into 0(%bp) */
40fb9820 5455 i.types[op].bitfield.disp8 = 1;
252b5132 5456 fake_zero_displacement = 1;
29b0f896
AM		 5457 }
5458 }
5459 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5460 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5461 break;
5462 default: /* (%si) -> 4 or (%di) -> 5 */
5463 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5464 }
5465 i.rm.mode = mode_from_disp_size (i.types[op]);
5466 }
5467 else /* i.base_reg and 32/64 bit mode */
5468 {
5469 if (flag_code == CODE_64BIT
40fb9820
L		 5470 && operand_type_check (i.types[op], disp))
5471 {
5472 i386_operand_type temp;
0dfbf9d7 5473 operand_type_set (&temp, 0);
40fb9820
L		 5474 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5475 i.types[op] = temp;
5476 if (i.prefix[ADDR_PREFIX] == 0)
5477 i.types[op].bitfield.disp32s = 1;
5478 else
5479 i.types[op].bitfield.disp32 = 1;
5480 }
20f0a1fc 5481
29b0f896
AM		 5482 i.rm.regmem = i.base_reg->reg_num;
5483 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5484 i.rex |= REX_B;
29b0f896
AM		 5485 i.sib.base = i.base_reg->reg_num;
5486 /* x86-64 ignores REX prefix bit here to avoid decoder
5487 complications. */
5488 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5489 {
5490 default_seg = &ss;
5491 if (i.disp_operands == 0)
5492 {
5493 fake_zero_displacement = 1;
40fb9820 5494 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5495 }
5496 }
5497 else if (i.base_reg->reg_num == ESP_REG_NUM)
5498 {
5499 default_seg = &ss;
5500 }
5501 i.sib.scale = i.log2_scale_factor;
5502 if (i.index_reg == 0)
5503 {
5504 /* <disp>(%esp) becomes two byte modrm with no index
5505 register. We've already stored the code for esp
5506 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5507 Any base register besides %esp will not use the
5508 extra modrm byte. */
5509 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5510 }
5511 else
5512 {
db51cc60
L		 5513 if (i.index_reg->reg_num == RegEiz
5514 || i.index_reg->reg_num == RegRiz)
5515 i.sib.index = NO_INDEX_REGISTER;
5516 else
5517 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5518 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5519 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5520 i.rex |= REX_X;
29b0f896 5521 }
67a4f2b7
AO		 5522
5523 if (i.disp_operands
5524 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5525 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5526 i.rm.mode = 0;
5527 else
5528 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5529 }
252b5132 5530
29b0f896
AM		 5531 if (fake_zero_displacement)
5532 {
5533 /* Fakes a zero displacement assuming that i.types[op]
5534 holds the correct displacement size. */
5535 expressionS *exp;
5536
5537 assert (i.op[op].disps == 0);
5538 exp = &disp_expressions[i.disp_operands++];
5539 i.op[op].disps = exp;
5540 exp->X_op = O_constant;
5541 exp->X_add_number = 0;
5542 exp->X_add_symbol = (symbolS *) 0;
5543 exp->X_op_symbol = (symbolS *) 0;
5544 }
c0f3af97
L		 5545
5546 mem = op;
29b0f896 5547 }
c0f3af97
L		 5548 else
5549 mem = ~0;
252b5132 5550
29b0f896
AM		 5551 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5552 (if any) based on i.tm.extension_opcode. Again, we must be
5553 careful to make sure that segment/control/debug/test/MMX
5554 registers are coded into the i.rm.reg field. */
5555 if (i.reg_operands)
5556 {
99018f42
L		 5557 unsigned int op;
5558
85f10a01
MM		 5559 /* This has been precalculated for SSE5 instructions
5560 that have a DREX field earlier in process_drex. */
b5016f89
L		 5561 if (i.tm.opcode_modifier.drex
5562 || i.tm.opcode_modifier.drexv
5563 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 5564 {
5565 op = i.drex.modrm_reg;
5566 i.rm.reg = i.op[op].regs->reg_num;
5567 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5568 i.rex |= REX_R;
5569 }
5570 else
5571 {
c0f3af97
L		 5572 unsigned int vex_reg = ~0;
5573
c0209578
L		 5574 for (op = 0; op < i.operands; op++)
5575 if (i.types[op].bitfield.reg8
5576 || i.types[op].bitfield.reg16
5577 || i.types[op].bitfield.reg32
5578 || i.types[op].bitfield.reg64
5579 || i.types[op].bitfield.regmmx
5580 || i.types[op].bitfield.regxmm
c0f3af97 5581 || i.types[op].bitfield.regymm
c0209578
L		 5582 || i.types[op].bitfield.sreg2
5583 || i.types[op].bitfield.sreg3
5584 || i.types[op].bitfield.control
5585 || i.types[op].bitfield.debug
5586 || i.types[op].bitfield.test)
5587 break;
5588
c0f3af97
L		 5589 if (vex_3_sources)
5590 op = dest;
5591 else if (i.tm.opcode_modifier.vexnds)
5592 {
5593 /* For instructions with VexNDS, the register-only
5594 source operand is encoded in VEX prefix. */
5595 assert (mem != (unsigned int) ~0);
5596
5597 if (op > mem)
5598 {
5599 vex_reg = op++;
5600 assert (op < i.operands);
5601 }
5602 else
5603 {
5604 vex_reg = op + 1;
5605 assert (vex_reg < i.operands);
5606 }
5607 }
5608 else if (i.tm.opcode_modifier.vexndd)
5609 {
5610 /* For instructions with VexNDD, there should be
5611 no memory operand and the register destination
5612 is encoded in VEX prefix. */
5613 assert (i.mem_operands == 0
5614 && (op + 2) == i.operands);
5615 vex_reg = op + 1;
5616 }
5617 else
5618 assert (op < i.operands);
5619
5620 if (vex_reg != (unsigned int) ~0)
5621 {
5622 assert (i.reg_operands == 2);
5623
5624 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
5625 & regxmm)
5626 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5627 &regymm))
5628 abort ();
5629 i.vex.register_specifier = i.op[vex_reg].regs;
5630 }
99018f42 5631
85f10a01
MM		 5632 /* If there is an extension opcode to put here, the
5633 register number must be put into the regmem field. */
c0209578
L		 5634 if (i.tm.extension_opcode != None)
5635 {
5636 i.rm.regmem = i.op[op].regs->reg_num;
5637 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5638 i.rex |= REX_B;
5639 }
5640 else
5641 {
5642 i.rm.reg = i.op[op].regs->reg_num;
5643 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5644 i.rex |= REX_R;
5645 }
85f10a01 5646 }
252b5132 5647
29b0f896
AM		 5648 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5649 must set it to 3 to indicate this is a register operand
5650 in the regmem field. */
5651 if (!i.mem_operands)
5652 i.rm.mode = 3;
5653 }
252b5132 5654
29b0f896 5655 /* Fill in i.rm.reg field with extension opcode (if any). */
85f10a01
MM		 5656 if (i.tm.extension_opcode != None
5657 && !(i.tm.opcode_modifier.drex
5658 || i.tm.opcode_modifier.drexv
5659 || i.tm.opcode_modifier.drexc))
29b0f896
AM		 5660 i.rm.reg = i.tm.extension_opcode;
5661 }
5662 return default_seg;
5663}
252b5132 5664
29b0f896 5665static void
e3bb37b5 5666output_branch (void)
29b0f896
AM		 5667{
5668 char *p;
5669 int code16;
5670 int prefix;
5671 relax_substateT subtype;
5672 symbolS *sym;
5673 offsetT off;
5674
5675 code16 = 0;
5676 if (flag_code == CODE_16BIT)
5677 code16 = CODE16;
5678
5679 prefix = 0;
5680 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5681 {
29b0f896
AM		 5682 prefix = 1;
5683 i.prefixes -= 1;
5684 code16 ^= CODE16;
252b5132 5685 }
29b0f896
AM		 5686 /* Pentium4 branch hints. */
5687 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5688 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5689 {
29b0f896
AM		 5690 prefix++;
5691 i.prefixes--;
5692 }
5693 if (i.prefix[REX_PREFIX] != 0)
5694 {
5695 prefix++;
5696 i.prefixes--;
2f66722d
AM		 5697 }
5698
29b0f896
AM		 5699 if (i.prefixes != 0 && !intel_syntax)
5700 as_warn (_("skipping prefixes on this instruction"));
5701
5702 /* It's always a symbol; End frag & setup for relax.
5703 Make sure there is enough room in this frag for the largest
5704 instruction we may generate in md_convert_frag. This is 2
5705 bytes for the opcode and room for the prefix and largest
5706 displacement. */
5707 frag_grow (prefix + 2 + 4);
5708 /* Prefix and 1 opcode byte go in fr_fix. */
5709 p = frag_more (prefix + 1);
5710 if (i.prefix[DATA_PREFIX] != 0)
5711 *p++ = DATA_PREFIX_OPCODE;
5712 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5713 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5714 *p++ = i.prefix[SEG_PREFIX];
5715 if (i.prefix[REX_PREFIX] != 0)
5716 *p++ = i.prefix[REX_PREFIX];
5717 *p = i.tm.base_opcode;
5718
5719 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5720 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5721 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5722 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5723 else
5724 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5725 subtype |= code16;
3e73aa7c 5726
29b0f896
AM		 5727 sym = i.op[0].disps->X_add_symbol;
5728 off = i.op[0].disps->X_add_number;
3e73aa7c 5729
29b0f896
AM		 5730 if (i.op[0].disps->X_op != O_constant
5731 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5732 {
29b0f896
AM		 5733 /* Handle complex expressions. */
5734 sym = make_expr_symbol (i.op[0].disps);
5735 off = 0;
5736 }
3e73aa7c 5737
29b0f896
AM		 5738 /* 1 possible extra opcode + 4 byte displacement go in var part.
5739 Pass reloc in fr_var. */
5740 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5741}
3e73aa7c 5742
29b0f896 5743static void
e3bb37b5 5744output_jump (void)
29b0f896
AM		 5745{
5746 char *p;
5747 int size;
3e02c1cc 5748 fixS *fixP;
29b0f896 5749
40fb9820 5750 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5751 {
5752 /* This is a loop or jecxz type instruction. */
5753 size = 1;
5754 if (i.prefix[ADDR_PREFIX] != 0)
5755 {
5756 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5757 i.prefixes -= 1;
5758 }
5759 /* Pentium4 branch hints. */
5760 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5761 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5762 {
5763 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5764 i.prefixes--;
3e73aa7c
JH		 5765 }
5766 }
29b0f896
AM		 5767 else
5768 {
5769 int code16;
3e73aa7c 5770
29b0f896
AM		 5771 code16 = 0;
5772 if (flag_code == CODE_16BIT)
5773 code16 = CODE16;
3e73aa7c 5774
29b0f896
AM		 5775 if (i.prefix[DATA_PREFIX] != 0)
5776 {
5777 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5778 i.prefixes -= 1;
5779 code16 ^= CODE16;
5780 }
252b5132 5781
29b0f896
AM		 5782 size = 4;
5783 if (code16)
5784 size = 2;
5785 }
9fcc94b6 5786
29b0f896
AM		 5787 if (i.prefix[REX_PREFIX] != 0)
5788 {
5789 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5790 i.prefixes -= 1;
5791 }
252b5132 5792
29b0f896
AM		 5793 if (i.prefixes != 0 && !intel_syntax)
5794 as_warn (_("skipping prefixes on this instruction"));
e0890092 5795
29b0f896
AM		 5796 p = frag_more (1 + size);
5797 *p++ = i.tm.base_opcode;
e0890092 5798
3e02c1cc
AM		 5799 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5800 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5801
5802 /* All jumps handled here are signed, but don't use a signed limit
5803 check for 32 and 16 bit jumps as we want to allow wrap around at
5804 4G and 64k respectively. */
5805 if (size == 1)
5806 fixP->fx_signed = 1;
29b0f896 5807}
e0890092 5808
29b0f896 5809static void
e3bb37b5 5810output_interseg_jump (void)
29b0f896
AM		 5811{
5812 char *p;
5813 int size;
5814 int prefix;
5815 int code16;
252b5132 5816
29b0f896
AM		 5817 code16 = 0;
5818 if (flag_code == CODE_16BIT)
5819 code16 = CODE16;
a217f122 5820
29b0f896
AM		 5821 prefix = 0;
5822 if (i.prefix[DATA_PREFIX] != 0)
5823 {
5824 prefix = 1;
5825 i.prefixes -= 1;
5826 code16 ^= CODE16;
5827 }
5828 if (i.prefix[REX_PREFIX] != 0)
5829 {
5830 prefix++;
5831 i.prefixes -= 1;
5832 }
252b5132 5833
29b0f896
AM		 5834 size = 4;
5835 if (code16)
5836 size = 2;
252b5132 5837
29b0f896
AM		 5838 if (i.prefixes != 0 && !intel_syntax)
5839 as_warn (_("skipping prefixes on this instruction"));
252b5132 5840
29b0f896
AM		 5841 /* 1 opcode; 2 segment; offset */
5842 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5843
29b0f896
AM		 5844 if (i.prefix[DATA_PREFIX] != 0)
5845 *p++ = DATA_PREFIX_OPCODE;
252b5132 5846
29b0f896
AM		 5847 if (i.prefix[REX_PREFIX] != 0)
5848 *p++ = i.prefix[REX_PREFIX];
252b5132 5849
29b0f896
AM		 5850 *p++ = i.tm.base_opcode;
5851 if (i.op[1].imms->X_op == O_constant)
5852 {
5853 offsetT n = i.op[1].imms->X_add_number;
252b5132 5854
29b0f896
AM		 5855 if (size == 2
5856 && !fits_in_unsigned_word (n)
5857 && !fits_in_signed_word (n))
5858 {
5859 as_bad (_("16-bit jump out of range"));
5860 return;
5861 }
5862 md_number_to_chars (p, n, size);
5863 }
5864 else
5865 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5866 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5867 if (i.op[0].imms->X_op != O_constant)
5868 as_bad (_("can't handle non absolute segment in `%s'"),
5869 i.tm.name);
5870 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5871}
a217f122 5872
29b0f896 5873static void
e3bb37b5 5874output_insn (void)
29b0f896 5875{
2bbd9c25
JJ		 5876 fragS *insn_start_frag;
5877 offsetT insn_start_off;
5878
29b0f896
AM		 5879 /* Tie dwarf2 debug info to the address at the start of the insn.
5880 We can't do this after the insn has been output as the current
5881 frag may have been closed off. eg. by frag_var. */
5882 dwarf2_emit_insn (0);
5883
2bbd9c25
JJ		 5884 insn_start_frag = frag_now;
5885 insn_start_off = frag_now_fix ();
5886
29b0f896 5887 /* Output jumps. */
40fb9820 5888 if (i.tm.opcode_modifier.jump)
29b0f896 5889 output_branch ();
40fb9820
L		 5890 else if (i.tm.opcode_modifier.jumpbyte
5891 || i.tm.opcode_modifier.jumpdword)
29b0f896 5892 output_jump ();
40fb9820 5893 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5894 output_interseg_jump ();
5895 else
5896 {
5897 /* Output normal instructions here. */
5898 char *p;
5899 unsigned char *q;
47465058 5900 unsigned int j;
331d2d0d 5901 unsigned int prefix;
4dffcebc 5902
c0f3af97
L		 5903 /* Since the VEX prefix contains the implicit prefix, we don't
5904 need the explicit prefix. */
5905 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5906 {
c0f3af97 5907 switch (i.tm.opcode_length)
bc4bd9ab 5908 {
c0f3af97
L		 5909 case 3:
5910 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5911 {
c0f3af97
L		 5912 prefix = (i.tm.base_opcode >> 24) & 0xff;
5913 goto check_prefix;
5914 }
5915 break;
5916 case 2:
5917 if ((i.tm.base_opcode & 0xff0000) != 0)
5918 {
5919 prefix = (i.tm.base_opcode >> 16) & 0xff;
5920 if (i.tm.cpu_flags.bitfield.cpupadlock)
5921 {
4dffcebc 5922check_prefix:
c0f3af97
L		 5923 if (prefix != REPE_PREFIX_OPCODE
5924 || (i.prefix[LOCKREP_PREFIX]
5925 != REPE_PREFIX_OPCODE))
5926 add_prefix (prefix);
5927 }
5928 else
4dffcebc
L		 5929 add_prefix (prefix);
5930 }
c0f3af97
L		 5931 break;
5932 case 1:
5933 break;
5934 default:
5935 abort ();
bc4bd9ab 5936 }
c0f3af97
L		 5937
5938 /* The prefix bytes. */
5939 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5940 if (*q)
5941 FRAG_APPEND_1_CHAR (*q);
0f10071e 5942 }
252b5132 5943
c0f3af97
L		 5944 if (i.tm.opcode_modifier.vex)
5945 {
5946 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5947 if (*q)
5948 switch (j)
5949 {
5950 case REX_PREFIX:
5951 /* REX byte is encoded in VEX prefix. */
5952 break;
5953 case SEG_PREFIX:
5954 case ADDR_PREFIX:
5955 FRAG_APPEND_1_CHAR (*q);
5956 break;
5957 default:
5958 /* There should be no other prefixes for instructions
5959 with VEX prefix. */
5960 abort ();
5961 }
5962
5963 /* Now the VEX prefix. */
5964 p = frag_more (i.vex.length);
5965 for (j = 0; j < i.vex.length; j++)
5966 p[j] = i.vex.bytes[j];
5967 }
252b5132 5968
29b0f896 5969 /* Now the opcode; be careful about word order here! */
4dffcebc 5970 if (i.tm.opcode_length == 1)
29b0f896
AM		 5971 {
5972 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5973 }
5974 else
5975 {
4dffcebc 5976 switch (i.tm.opcode_length)
331d2d0d 5977 {
4dffcebc 5978 case 3:
331d2d0d
L		 5979 p = frag_more (3);
5980 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5981 break;
5982 case 2:
5983 p = frag_more (2);
5984 break;
5985 default:
5986 abort ();
5987 break;
331d2d0d 5988 }
0f10071e 5989
29b0f896
AM		 5990 /* Put out high byte first: can't use md_number_to_chars! */
5991 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5992 *p = i.tm.base_opcode & 0xff;
85f10a01
MM		 5993
5994 /* On SSE5, encode the OC1 bit in the DREX field if this
5995 encoding has multiple formats. */
5996 if (i.tm.opcode_modifier.drex
5997 && i.tm.opcode_modifier.drexv
5998 && DREX_OC1 (i.tm.extension_opcode))
5999 *p |= DREX_OC1_MASK;
29b0f896 6000 }
3e73aa7c 6001
29b0f896 6002 /* Now the modrm byte and sib byte (if present). */
40fb9820 6003 if (i.tm.opcode_modifier.modrm)
29b0f896 6004 {
4a3523fa
L		 6005 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
6006 | i.rm.reg << 3
6007 | i.rm.mode << 6));
29b0f896
AM		 6008 /* If i.rm.regmem == ESP (4)
6009 && i.rm.mode != (Register mode)
6010 && not 16 bit
6011 ==> need second modrm byte. */
6012 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
6013 && i.rm.mode != 3
40fb9820 6014 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 6015 FRAG_APPEND_1_CHAR ((i.sib.base << 0
6016 | i.sib.index << 3
6017 | i.sib.scale << 6));
29b0f896 6018 }
3e73aa7c 6019
85f10a01
MM		 6020 /* Write the DREX byte if needed. */
6021 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
6022 {
6023 p = frag_more (1);
6024 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
6025
6026 /* Encode the OC0 bit if this encoding has multiple
6027 formats. */
6028 if ((i.tm.opcode_modifier.drex
6029 || i.tm.opcode_modifier.drexv)
6030 && DREX_OC0 (i.tm.extension_opcode))
6031 *p |= DREX_OC0_MASK;
6032 }
6033
29b0f896 6034 if (i.disp_operands)
2bbd9c25 6035 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 6036
29b0f896 6037 if (i.imm_operands)
2bbd9c25 6038 output_imm (insn_start_frag, insn_start_off);
29b0f896 6039 }
252b5132 6040
29b0f896
AM		 6041#ifdef DEBUG386
6042 if (flag_debug)
6043 {
7b81dfbb 6044 pi ("" /*line*/, &i);
29b0f896
AM		 6045 }
6046#endif /* DEBUG386 */
6047}
252b5132 6048
e205caa7
L		 6049/* Return the size of the displacement operand N. */
6050
6051static int
6052disp_size (unsigned int n)
6053{
6054 int size = 4;
40fb9820
L		 6055 if (i.types[n].bitfield.disp64)
6056 size = 8;
6057 else if (i.types[n].bitfield.disp8)
6058 size = 1;
6059 else if (i.types[n].bitfield.disp16)
6060 size = 2;
e205caa7
L		 6061 return size;
6062}
6063
6064/* Return the size of the immediate operand N. */
6065
6066static int
6067imm_size (unsigned int n)
6068{
6069 int size = 4;
40fb9820
L		 6070 if (i.types[n].bitfield.imm64)
6071 size = 8;
6072 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
6073 size = 1;
6074 else if (i.types[n].bitfield.imm16)
6075 size = 2;
e205caa7
L		 6076 return size;
6077}
6078
29b0f896 6079static void
64e74474 6080output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6081{
6082 char *p;
6083 unsigned int n;
252b5132 6084
29b0f896
AM		 6085 for (n = 0; n < i.operands; n++)
6086 {
40fb9820 6087 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 6088 {
6089 if (i.op[n].disps->X_op == O_constant)
6090 {
e205caa7 6091 int size = disp_size (n);
29b0f896 6092 offsetT val;
252b5132 6093
29b0f896
AM		 6094 val = offset_in_range (i.op[n].disps->X_add_number,
6095 size);
6096 p = frag_more (size);
6097 md_number_to_chars (p, val, size);
6098 }
6099 else
6100 {
f86103b7 6101 enum bfd_reloc_code_real reloc_type;
e205caa7 6102 int size = disp_size (n);
40fb9820 6103 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 6104 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6105
e205caa7 6106 /* We can't have 8 bit displacement here. */
40fb9820 6107 assert (!i.types[n].bitfield.disp8);
e205caa7 6108
29b0f896
AM		 6109 /* The PC relative address is computed relative
6110 to the instruction boundary, so in case immediate
6111 fields follows, we need to adjust the value. */
6112 if (pcrel && i.imm_operands)
6113 {
29b0f896 6114 unsigned int n1;
e205caa7 6115 int sz = 0;
252b5132 6116
29b0f896 6117 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 6118 if (operand_type_check (i.types[n1], imm))
252b5132 6119 {
e205caa7
L		 6120 /* Only one immediate is allowed for PC
6121 relative address. */
6122 assert (sz == 0);
6123 sz = imm_size (n1);
6124 i.op[n].disps->X_add_number -= sz;
252b5132 6125 }
29b0f896 6126 /* We should find the immediate. */
e205caa7 6127 assert (sz != 0);
29b0f896 6128 }
520dc8e8 6129
29b0f896 6130 p = frag_more (size);
2bbd9c25 6131 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 6132 if (GOT_symbol
2bbd9c25 6133 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 6134 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6135 || reloc_type == BFD_RELOC_X86_64_32S
6136 || (reloc_type == BFD_RELOC_64
6137 && object_64bit))
d6ab8113
JB		 6138 && (i.op[n].disps->X_op == O_symbol
6139 || (i.op[n].disps->X_op == O_add
6140 && ((symbol_get_value_expression
6141 (i.op[n].disps->X_op_symbol)->X_op)
6142 == O_subtract))))
6143 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 6144 {
6145 offsetT add;
6146
6147 if (insn_start_frag == frag_now)
6148 add = (p - frag_now->fr_literal) - insn_start_off;
6149 else
6150 {
6151 fragS *fr;
6152
6153 add = insn_start_frag->fr_fix - insn_start_off;
6154 for (fr = insn_start_frag->fr_next;
6155 fr && fr != frag_now; fr = fr->fr_next)
6156 add += fr->fr_fix;
6157 add += p - frag_now->fr_literal;
6158 }
6159
4fa24527 6160 if (!object_64bit)
7b81dfbb
AJ		 6161 {
6162 reloc_type = BFD_RELOC_386_GOTPC;
6163 i.op[n].imms->X_add_number += add;
6164 }
6165 else if (reloc_type == BFD_RELOC_64)
6166 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 6167 else
7b81dfbb
AJ		 6168 /* Don't do the adjustment for x86-64, as there
6169 the pcrel addressing is relative to the _next_
6170 insn, and that is taken care of in other code. */
d6ab8113 6171 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 6172 }
062cd5e7 6173 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 6174 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 6175 }
6176 }
6177 }
6178}
252b5132 6179
29b0f896 6180static void
64e74474 6181output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6182{
6183 char *p;
6184 unsigned int n;
252b5132 6185
29b0f896
AM		 6186 for (n = 0; n < i.operands; n++)
6187 {
40fb9820 6188 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 6189 {
6190 if (i.op[n].imms->X_op == O_constant)
6191 {
e205caa7 6192 int size = imm_size (n);
29b0f896 6193 offsetT val;
b4cac588 6194
29b0f896
AM		 6195 val = offset_in_range (i.op[n].imms->X_add_number,
6196 size);
6197 p = frag_more (size);
6198 md_number_to_chars (p, val, size);
6199 }
6200 else
6201 {
6202 /* Not absolute_section.
6203 Need a 32-bit fixup (don't support 8bit
6204 non-absolute imms). Try to support other
6205 sizes ... */
f86103b7 6206 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 6207 int size = imm_size (n);
6208 int sign;
29b0f896 6209
40fb9820 6210 if (i.types[n].bitfield.imm32s
a7d61044 6211 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6212 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6213 sign = 1;
e205caa7
L		 6214 else
6215 sign = 0;
520dc8e8 6216
29b0f896
AM		 6217 p = frag_more (size);
6218 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6219
2bbd9c25
JJ		 6220 /* This is tough to explain. We end up with this one if we
6221 * have operands that look like
6222 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6223 * obtain the absolute address of the GOT, and it is strongly
6224 * preferable from a performance point of view to avoid using
6225 * a runtime relocation for this. The actual sequence of
6226 * instructions often look something like:
6227 *
6228 * call .L66
6229 * .L66:
6230 * popl %ebx
6231 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6232 *
6233 * The call and pop essentially return the absolute address
6234 * of the label .L66 and store it in %ebx. The linker itself
6235 * will ultimately change the first operand of the addl so
6236 * that %ebx points to the GOT, but to keep things simple, the
6237 * .o file must have this operand set so that it generates not
6238 * the absolute address of .L66, but the absolute address of
6239 * itself. This allows the linker itself simply treat a GOTPC
6240 * relocation as asking for a pcrel offset to the GOT to be
6241 * added in, and the addend of the relocation is stored in the
6242 * operand field for the instruction itself.
6243 *
6244 * Our job here is to fix the operand so that it would add
6245 * the correct offset so that %ebx would point to itself. The
6246 * thing that is tricky is that .-.L66 will point to the
6247 * beginning of the instruction, so we need to further modify
6248 * the operand so that it will point to itself. There are
6249 * other cases where you have something like:
6250 *
6251 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6252 *
6253 * and here no correction would be required. Internally in
6254 * the assembler we treat operands of this form as not being
6255 * pcrel since the '.' is explicitly mentioned, and I wonder
6256 * whether it would simplify matters to do it this way. Who
6257 * knows. In earlier versions of the PIC patches, the
6258 * pcrel_adjust field was used to store the correction, but
6259 * since the expression is not pcrel, I felt it would be
6260 * confusing to do it this way. */
6261
d6ab8113 6262 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6263 || reloc_type == BFD_RELOC_X86_64_32S
6264 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6265 && GOT_symbol
6266 && GOT_symbol == i.op[n].imms->X_add_symbol
6267 && (i.op[n].imms->X_op == O_symbol
6268 || (i.op[n].imms->X_op == O_add
6269 && ((symbol_get_value_expression
6270 (i.op[n].imms->X_op_symbol)->X_op)
6271 == O_subtract))))
6272 {
2bbd9c25
JJ		 6273 offsetT add;
6274
6275 if (insn_start_frag == frag_now)
6276 add = (p - frag_now->fr_literal) - insn_start_off;
6277 else
6278 {
6279 fragS *fr;
6280
6281 add = insn_start_frag->fr_fix - insn_start_off;
6282 for (fr = insn_start_frag->fr_next;
6283 fr && fr != frag_now; fr = fr->fr_next)
6284 add += fr->fr_fix;
6285 add += p - frag_now->fr_literal;
6286 }
6287
4fa24527 6288 if (!object_64bit)
d6ab8113 6289 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6290 else if (size == 4)
d6ab8113 6291 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6292 else if (size == 8)
6293 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6294 i.op[n].imms->X_add_number += add;
29b0f896 6295 }
29b0f896
AM		 6296 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6297 i.op[n].imms, 0, reloc_type);
6298 }
6299 }
6300 }
252b5132
RH		 6301}
6302\f
d182319b
JB		 6303/* x86_cons_fix_new is called via the expression parsing code when a
6304 reloc is needed. We use this hook to get the correct .got reloc. */
6305static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6306static int cons_sign = -1;
6307
6308void
e3bb37b5 6309x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6310 expressionS *exp)
d182319b
JB		 6311{
6312 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6313
6314 got_reloc = NO_RELOC;
6315
6316#ifdef TE_PE
6317 if (exp->X_op == O_secrel)
6318 {
6319 exp->X_op = O_symbol;
6320 r = BFD_RELOC_32_SECREL;
6321 }
6322#endif
6323
6324 fix_new_exp (frag, off, len, exp, 0, r);
6325}
6326
718ddfc0
JB		 6327#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6328# define lex_got(reloc, adjust, types) NULL
6329#else
f3c180ae
AM		 6330/* Parse operands of the form
6331 <symbol>@GOTOFF+<nnn>
6332 and similar .plt or .got references.
6333
6334 If we find one, set up the correct relocation in RELOC and copy the
6335 input string, minus the `@GOTOFF' into a malloc'd buffer for
6336 parsing by the calling routine. Return this buffer, and if ADJUST
6337 is non-null set it to the length of the string we removed from the
6338 input line. Otherwise return NULL. */
6339static char *
3956db08 6340lex_got (enum bfd_reloc_code_real *reloc,
64e74474 6341 int *adjust,
40fb9820 6342 i386_operand_type *types)
f3c180ae 6343{
7b81dfbb
AJ		 6344 /* Some of the relocations depend on the size of what field is to
6345 be relocated. But in our callers i386_immediate and i386_displacement
6346 we don't yet know the operand size (this will be set by insn
6347 matching). Hence we record the word32 relocation here,
6348 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6349 static const struct {
6350 const char *str;
4fa24527 6351 const enum bfd_reloc_code_real rel[2];
40fb9820 6352 const i386_operand_type types64;
f3c180ae 6353 } gotrel[] = {
4eed87de
AM		 6354 { "PLTOFF", { 0,
6355 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6356 OPERAND_TYPE_IMM64 },
4eed87de
AM		 6357 { "PLT", { BFD_RELOC_386_PLT32,
6358 BFD_RELOC_X86_64_PLT32 },
40fb9820 6359 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6360 { "GOTPLT", { 0,
6361 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6362 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 6363 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
6364 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6365 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 6366 { "GOTPCREL", { 0,
6367 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6368 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6369 { "TLSGD", { BFD_RELOC_386_TLS_GD,
6370 BFD_RELOC_X86_64_TLSGD },
40fb9820 6371 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6372 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
6373 0 },
40fb9820 6374 OPERAND_TYPE_NONE },
4eed87de
AM		 6375 { "TLSLD", { 0,
6376 BFD_RELOC_X86_64_TLSLD },
40fb9820 6377 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6378 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
6379 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6380 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6381 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
6382 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6383 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 6384 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
6385 0 },
40fb9820 6386 OPERAND_TYPE_NONE },
4eed87de
AM		 6387 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
6388 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820
L		 6389
6390 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 6391 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
6392 0 },
40fb9820 6393 OPERAND_TYPE_NONE },
4eed87de
AM		 6394 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
6395 0 },
40fb9820 6396 OPERAND_TYPE_NONE },
4eed87de
AM		 6397 { "GOT", { BFD_RELOC_386_GOT32,
6398 BFD_RELOC_X86_64_GOT32 },
40fb9820 6399 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 6400 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
6401 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6402 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6403 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
6404 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6405 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6406 };
6407 char *cp;
6408 unsigned int j;
6409
718ddfc0
JB		 6410 if (!IS_ELF)
6411 return NULL;
6412
f3c180ae 6413 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6414 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6415 return NULL;
6416
47465058 6417 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 6418 {
6419 int len;
6420
6421 len = strlen (gotrel[j].str);
28f81592 6422 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6423 {
4fa24527 6424 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6425 {
28f81592
AM		 6426 int first, second;
6427 char *tmpbuf, *past_reloc;
f3c180ae 6428
4fa24527 6429 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 6430 if (adjust)
6431 *adjust = len;
f3c180ae 6432
3956db08
JB		 6433 if (types)
6434 {
6435 if (flag_code != CODE_64BIT)
40fb9820
L		 6436 {
6437 types->bitfield.imm32 = 1;
6438 types->bitfield.disp32 = 1;
6439 }
3956db08
JB		 6440 else
6441 *types = gotrel[j].types64;
6442 }
6443
f3c180ae
AM		 6444 if (GOT_symbol == NULL)
6445 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6446
28f81592 6447 /* The length of the first part of our input line. */
f3c180ae 6448 first = cp - input_line_pointer;
28f81592
AM		 6449
6450 /* The second part goes from after the reloc token until
67c11a9b 6451 (and including) an end_of_line char or comma. */
28f81592 6452 past_reloc = cp + 1 + len;
67c11a9b
AM		 6453 cp = past_reloc;
6454 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6455 ++cp;
6456 second = cp + 1 - past_reloc;
28f81592
AM		 6457
6458 /* Allocate and copy string. The trailing NUL shouldn't
6459 be necessary, but be safe. */
6460 tmpbuf = xmalloc (first + second + 2);
f3c180ae 6461 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6462 if (second != 0 && *past_reloc != ' ')
6463 /* Replace the relocation token with ' ', so that
6464 errors like foo@GOTOFF1 will be detected. */
6465 tmpbuf[first++] = ' ';
6466 memcpy (tmpbuf + first, past_reloc, second);
6467 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6468 return tmpbuf;
6469 }
6470
4fa24527
JB		 6471 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6472 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6473 return NULL;
6474 }
6475 }
6476
6477 /* Might be a symbol version string. Don't as_bad here. */
6478 return NULL;
6479}
6480
f3c180ae 6481void
e3bb37b5 6482x86_cons (expressionS *exp, int size)
f3c180ae 6483{
4fa24527 6484 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6485 {
6486 /* Handle @GOTOFF and the like in an expression. */
6487 char *save;
6488 char *gotfree_input_line;
6489 int adjust;
6490
6491 save = input_line_pointer;
3956db08 6492 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6493 if (gotfree_input_line)
6494 input_line_pointer = gotfree_input_line;
6495
6496 expression (exp);
6497
6498 if (gotfree_input_line)
6499 {
6500 /* expression () has merrily parsed up to the end of line,
6501 or a comma - in the wrong buffer. Transfer how far
6502 input_line_pointer has moved to the right buffer. */
6503 input_line_pointer = (save
6504 + (input_line_pointer - gotfree_input_line)
6505 + adjust);
6506 free (gotfree_input_line);
3992d3b7
AM		 6507 if (exp->X_op == O_constant
6508 || exp->X_op == O_absent
6509 || exp->X_op == O_illegal
6510 || exp->X_op == O_register
6511 || exp->X_op == O_big)
6512 {
6513 char c = *input_line_pointer;
6514 *input_line_pointer = 0;
6515 as_bad (_("missing or invalid expression `%s'"), save);
6516 *input_line_pointer = c;
6517 }
f3c180ae
AM		 6518 }
6519 }
6520 else
6521 expression (exp);
6522}
6523#endif
6524
d182319b 6525static void signed_cons (int size)
6482c264 6526{
d182319b
JB		 6527 if (flag_code == CODE_64BIT)
6528 cons_sign = 1;
6529 cons (size);
6530 cons_sign = -1;
6482c264
NC		 6531}
6532
d182319b 6533#ifdef TE_PE
6482c264
NC		 6534static void
6535pe_directive_secrel (dummy)
6536 int dummy ATTRIBUTE_UNUSED;
6537{
6538 expressionS exp;
6539
6540 do
6541 {
6542 expression (&exp);
6543 if (exp.X_op == O_symbol)
6544 exp.X_op = O_secrel;
6545
6546 emit_expr (&exp, 4);
6547 }
6548 while (*input_line_pointer++ == ',');
6549
6550 input_line_pointer--;
6551 demand_empty_rest_of_line ();
6552}
6482c264
NC		 6553#endif
6554
252b5132 6555static int
70e41ade 6556i386_immediate (char *imm_start)
252b5132
RH		 6557{
6558 char *save_input_line_pointer;
f3c180ae 6559 char *gotfree_input_line;
252b5132 6560 segT exp_seg = 0;
47926f60 6561 expressionS *exp;
40fb9820
L		 6562 i386_operand_type types;
6563
0dfbf9d7 6564 operand_type_set (&types, ~0);
252b5132
RH		 6565
6566 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6567 {
31b2323c
L		 6568 as_bad (_("at most %d immediate operands are allowed"),
6569 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6570 return 0;
6571 }
6572
6573 exp = &im_expressions[i.imm_operands++];
520dc8e8 6574 i.op[this_operand].imms = exp;
252b5132
RH		 6575
6576 if (is_space_char (*imm_start))
6577 ++imm_start;
6578
6579 save_input_line_pointer = input_line_pointer;
6580 input_line_pointer = imm_start;
6581
3956db08 6582 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6583 if (gotfree_input_line)
6584 input_line_pointer = gotfree_input_line;
252b5132
RH		 6585
6586 exp_seg = expression (exp);
6587
83183c0c 6588 SKIP_WHITESPACE ();
252b5132 6589 if (*input_line_pointer)
f3c180ae 6590 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6591
6592 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 6593 if (gotfree_input_line)
6594 free (gotfree_input_line);
252b5132 6595
3992d3b7
AM		 6596 if (exp->X_op == O_absent
6597 || exp->X_op == O_illegal
6598 || exp->X_op == O_big
6599 || (gotfree_input_line
6600 && (exp->X_op == O_constant
6601 || exp->X_op == O_register)))
252b5132 6602 {
3992d3b7 6603 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 6604 imm_start);
3992d3b7 6605 return 0;
252b5132 6606 }
3e73aa7c 6607 else if (exp->X_op == O_constant)
252b5132 6608 {
47926f60 6609 /* Size it properly later. */
40fb9820 6610 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 6611 /* If BFD64, sign extend val. */
4eed87de
AM		 6612 if (!use_rela_relocations
6613 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6614 exp->X_add_number
6615 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6616 }
4c63da97 6617#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6618 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6619 && exp_seg != absolute_section
47926f60 6620 && exp_seg != text_section
24eab124
AM		 6621 && exp_seg != data_section
6622 && exp_seg != bss_section
6623 && exp_seg != undefined_section
f86103b7 6624 && !bfd_is_com_section (exp_seg))
252b5132 6625 {
d0b47220 6626 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6627 return 0;
6628 }
6629#endif
bb8f5920
L		 6630 else if (!intel_syntax && exp->X_op == O_register)
6631 {
6632 as_bad (_("illegal immediate register operand %s"), imm_start);
6633 return 0;
6634 }
252b5132
RH		 6635 else
6636 {
6637 /* This is an address. The size of the address will be
24eab124 6638 determined later, depending on destination register,
3e73aa7c 6639 suffix, or the default for the section. */
40fb9820
L		 6640 i.types[this_operand].bitfield.imm8 = 1;
6641 i.types[this_operand].bitfield.imm16 = 1;
6642 i.types[this_operand].bitfield.imm32 = 1;
6643 i.types[this_operand].bitfield.imm32s = 1;
6644 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6645 i.types[this_operand] = operand_type_and (i.types[this_operand],
6646 types);
252b5132
RH		 6647 }
6648
6649 return 1;
6650}
6651
551c1ca1 6652static char *
e3bb37b5 6653i386_scale (char *scale)
252b5132 6654{
551c1ca1
AM		 6655 offsetT val;
6656 char *save = input_line_pointer;
252b5132 6657
551c1ca1
AM		 6658 input_line_pointer = scale;
6659 val = get_absolute_expression ();
6660
6661 switch (val)
252b5132 6662 {
551c1ca1 6663 case 1:
252b5132
RH		 6664 i.log2_scale_factor = 0;
6665 break;
551c1ca1 6666 case 2:
252b5132
RH		 6667 i.log2_scale_factor = 1;
6668 break;
551c1ca1 6669 case 4:
252b5132
RH		 6670 i.log2_scale_factor = 2;
6671 break;
551c1ca1 6672 case 8:
252b5132
RH		 6673 i.log2_scale_factor = 3;
6674 break;
6675 default:
a724f0f4
JB		 6676 {
6677 char sep = *input_line_pointer;
6678
6679 *input_line_pointer = '\0';
6680 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6681 scale);
6682 *input_line_pointer = sep;
6683 input_line_pointer = save;
6684 return NULL;
6685 }
252b5132 6686 }
29b0f896 6687 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6688 {
6689 as_warn (_("scale factor of %d without an index register"),
24eab124 6690 1 << i.log2_scale_factor);
252b5132 6691 i.log2_scale_factor = 0;
252b5132 6692 }
551c1ca1
AM		 6693 scale = input_line_pointer;
6694 input_line_pointer = save;
6695 return scale;
252b5132
RH		 6696}
6697
252b5132 6698static int
e3bb37b5 6699i386_displacement (char *disp_start, char *disp_end)
252b5132 6700{
29b0f896 6701 expressionS *exp;
252b5132
RH		 6702 segT exp_seg = 0;
6703 char *save_input_line_pointer;
f3c180ae 6704 char *gotfree_input_line;
40fb9820
L		 6705 int override;
6706 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6707 int ret;
252b5132 6708
31b2323c
L		 6709 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6710 {
6711 as_bad (_("at most %d displacement operands are allowed"),
6712 MAX_MEMORY_OPERANDS);
6713 return 0;
6714 }
6715
0dfbf9d7 6716 operand_type_set (&bigdisp, 0);
40fb9820
L		 6717 if ((i.types[this_operand].bitfield.jumpabsolute)
6718 || (!current_templates->start->opcode_modifier.jump
6719 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6720 {
40fb9820 6721 bigdisp.bitfield.disp32 = 1;
e05278af 6722 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6723 if (flag_code == CODE_64BIT)
6724 {
6725 if (!override)
6726 {
6727 bigdisp.bitfield.disp32s = 1;
6728 bigdisp.bitfield.disp64 = 1;
6729 }
6730 }
6731 else if ((flag_code == CODE_16BIT) ^ override)
6732 {
6733 bigdisp.bitfield.disp32 = 0;
6734 bigdisp.bitfield.disp16 = 1;
6735 }
e05278af
JB		 6736 }
6737 else
6738 {
6739 /* For PC-relative branches, the width of the displacement
6740 is dependent upon data size, not address size. */
e05278af 6741 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6742 if (flag_code == CODE_64BIT)
6743 {
6744 if (override || i.suffix == WORD_MNEM_SUFFIX)
6745 bigdisp.bitfield.disp16 = 1;
6746 else
6747 {
6748 bigdisp.bitfield.disp32 = 1;
6749 bigdisp.bitfield.disp32s = 1;
6750 }
6751 }
6752 else
e05278af
JB		 6753 {
6754 if (!override)
6755 override = (i.suffix == (flag_code != CODE_16BIT
6756 ? WORD_MNEM_SUFFIX
6757 : LONG_MNEM_SUFFIX));
40fb9820
L		 6758 bigdisp.bitfield.disp32 = 1;
6759 if ((flag_code == CODE_16BIT) ^ override)
6760 {
6761 bigdisp.bitfield.disp32 = 0;
6762 bigdisp.bitfield.disp16 = 1;
6763 }
e05278af 6764 }
e05278af 6765 }
c6fb90c8
L		 6766 i.types[this_operand] = operand_type_or (i.types[this_operand],
6767 bigdisp);
252b5132
RH		 6768
6769 exp = &disp_expressions[i.disp_operands];
520dc8e8 6770 i.op[this_operand].disps = exp;
252b5132
RH		 6771 i.disp_operands++;
6772 save_input_line_pointer = input_line_pointer;
6773 input_line_pointer = disp_start;
6774 END_STRING_AND_SAVE (disp_end);
6775
6776#ifndef GCC_ASM_O_HACK
6777#define GCC_ASM_O_HACK 0
6778#endif
6779#if GCC_ASM_O_HACK
6780 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6781 if (i.types[this_operand].bitfield.baseIndex
24eab124 6782 && displacement_string_end[-1] == '+')
252b5132
RH		 6783 {
6784 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6785 constraint within gcc asm statements.
6786 For instance:
6787
6788 #define _set_tssldt_desc(n,addr,limit,type) \
6789 __asm__ __volatile__ ( \
6790 "movw %w2,%0\n\t" \
6791 "movw %w1,2+%0\n\t" \
6792 "rorl $16,%1\n\t" \
6793 "movb %b1,4+%0\n\t" \
6794 "movb %4,5+%0\n\t" \
6795 "movb $0,6+%0\n\t" \
6796 "movb %h1,7+%0\n\t" \
6797 "rorl $16,%1" \
6798 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6799
6800 This works great except that the output assembler ends
6801 up looking a bit weird if it turns out that there is
6802 no offset. You end up producing code that looks like:
6803
6804 #APP
6805 movw $235,(%eax)
6806 movw %dx,2+(%eax)
6807 rorl $16,%edx
6808 movb %dl,4+(%eax)
6809 movb $137,5+(%eax)
6810 movb $0,6+(%eax)
6811 movb %dh,7+(%eax)
6812 rorl $16,%edx
6813 #NO_APP
6814
47926f60 6815 So here we provide the missing zero. */
24eab124
AM		 6816
6817 *displacement_string_end = '0';
252b5132
RH		 6818 }
6819#endif
3956db08 6820 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6821 if (gotfree_input_line)
6822 input_line_pointer = gotfree_input_line;
252b5132 6823
24eab124 6824 exp_seg = expression (exp);
252b5132 6825
636c26b0
AM		 6826 SKIP_WHITESPACE ();
6827 if (*input_line_pointer)
6828 as_bad (_("junk `%s' after expression"), input_line_pointer);
6829#if GCC_ASM_O_HACK
6830 RESTORE_END_STRING (disp_end + 1);
6831#endif
636c26b0 6832 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 6833 if (gotfree_input_line)
6834 free (gotfree_input_line);
3992d3b7 6835 ret = 1;
636c26b0 6836
24eab124
AM		 6837 /* We do this to make sure that the section symbol is in
6838 the symbol table. We will ultimately change the relocation
47926f60 6839 to be relative to the beginning of the section. */
1ae12ab7 6840 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6841 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6842 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6843 {
636c26b0 6844 if (exp->X_op != O_symbol)
3992d3b7 6845 goto inv_disp;
636c26b0 6846
e5cb08ac 6847 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 6848 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6849 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6850 exp->X_op = O_subtract;
6851 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6852 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6853 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6854 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6855 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6856 else
29b0f896 6857 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6858 }
252b5132 6859
3992d3b7
AM		 6860 else if (exp->X_op == O_absent
6861 || exp->X_op == O_illegal
6862 || exp->X_op == O_big
6863 || (gotfree_input_line
6864 && (exp->X_op == O_constant
6865 || exp->X_op == O_register)))
2daf4fd8 6866 {
3992d3b7
AM		 6867 inv_disp:
6868 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6869 disp_start);
3992d3b7 6870 ret = 0;
2daf4fd8
AM		 6871 }
6872
4c63da97 6873#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6874 else if (exp->X_op != O_constant
6875 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6876 && exp_seg != absolute_section
6877 && exp_seg != text_section
6878 && exp_seg != data_section
6879 && exp_seg != bss_section
6880 && exp_seg != undefined_section
6881 && !bfd_is_com_section (exp_seg))
24eab124 6882 {
d0b47220 6883 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6884 ret = 0;
24eab124 6885 }
252b5132 6886#endif
3956db08 6887
3992d3b7
AM		 6888 RESTORE_END_STRING (disp_end);
6889
40fb9820
L		 6890 /* Check if this is a displacement only operand. */
6891 bigdisp = i.types[this_operand];
6892 bigdisp.bitfield.disp8 = 0;
6893 bigdisp.bitfield.disp16 = 0;
6894 bigdisp.bitfield.disp32 = 0;
6895 bigdisp.bitfield.disp32s = 0;
6896 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6897 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6898 i.types[this_operand] = operand_type_and (i.types[this_operand],
6899 types);
3956db08 6900
3992d3b7 6901 return ret;
252b5132
RH		 6902}
6903
eecb386c 6904/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6905 Return 1 on success, 0 on a failure. */
6906
252b5132 6907static int
e3bb37b5 6908i386_index_check (const char *operand_string)
252b5132 6909{
3e73aa7c 6910 int ok;
fc0763e6 6911 const char *kind = "base/index";
24eab124 6912#if INFER_ADDR_PREFIX
eecb386c
AM		 6913 int fudged = 0;
6914
24eab124
AM		 6915 tryprefix:
6916#endif
3e73aa7c 6917 ok = 1;
fc0763e6
JB		 6918 if (current_templates->start->opcode_modifier.isstring
6919 && !current_templates->start->opcode_modifier.immext
6920 && (current_templates->end[-1].opcode_modifier.isstring
6921 || i.mem_operands))
6922 {
6923 /* Memory operands of string insns are special in that they only allow
6924 a single register (rDI, rSI, or rBX) as their memory address. */
6925 unsigned int expected;
6926
6927 kind = "string address";
6928
6929 if (current_templates->start->opcode_modifier.w)
6930 {
6931 i386_operand_type type = current_templates->end[-1].operand_types[0];
6932
6933 if (!type.bitfield.baseindex
6934 || ((!i.mem_operands != !intel_syntax)
6935 && current_templates->end[-1].operand_types[1]
6936 .bitfield.baseindex))
6937 type = current_templates->end[-1].operand_types[1];
6938 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
6939 }
6940 else
6941 expected = 3 /* rBX */;
6942
6943 if (!i.base_reg || i.index_reg
6944 || operand_type_check (i.types[this_operand], disp))
6945 ok = -1;
6946 else if (!(flag_code == CODE_64BIT
6947 ? i.prefix[ADDR_PREFIX]
6948 ? i.base_reg->reg_type.bitfield.reg32
6949 : i.base_reg->reg_type.bitfield.reg64
6950 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6951 ? i.base_reg->reg_type.bitfield.reg32
6952 : i.base_reg->reg_type.bitfield.reg16))
6953 ok = 0;
6954 else if (i.base_reg->reg_num != expected)
6955 ok = -1;
6956
6957 if (ok < 0)
6958 {
6959 unsigned int j;
6960
6961 for (j = 0; j < i386_regtab_size; ++j)
6962 if ((flag_code == CODE_64BIT
6963 ? i.prefix[ADDR_PREFIX]
6964 ? i386_regtab[j].reg_type.bitfield.reg32
6965 : i386_regtab[j].reg_type.bitfield.reg64
6966 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6967 ? i386_regtab[j].reg_type.bitfield.reg32
6968 : i386_regtab[j].reg_type.bitfield.reg16)
6969 && i386_regtab[j].reg_num == expected)
6970 break;
6971 assert (j < i386_regtab_size);
6972 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6973 operand_string,
6974 intel_syntax ? '[' : '(',
6975 register_prefix,
6976 i386_regtab[j].reg_name,
6977 intel_syntax ? ']' : ')');
6978 ok = 1;
6979 }
6980 }
6981 else if (flag_code == CODE_64BIT)
64e74474 6982 {
64e74474 6983 if ((i.base_reg
40fb9820
L		 6984 && ((i.prefix[ADDR_PREFIX] == 0
6985 && !i.base_reg->reg_type.bitfield.reg64)
6986 || (i.prefix[ADDR_PREFIX]
6987 && !i.base_reg->reg_type.bitfield.reg32))
6988 && (i.index_reg
9a04903e
JB		 6989 || i.base_reg->reg_num !=
6990 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6991 || (i.index_reg
40fb9820
L		 6992 && (!i.index_reg->reg_type.bitfield.baseindex
6993 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 6994 && i.index_reg->reg_num != RegRiz
6995 && !i.index_reg->reg_type.bitfield.reg64
6996 )
40fb9820 6997 || (i.prefix[ADDR_PREFIX]
db51cc60 6998 && i.index_reg->reg_num != RegEiz
40fb9820 6999 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 7000 ok = 0;
3e73aa7c
JH		 7001 }
7002 else
7003 {
7004 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
7005 {
7006 /* 16bit checks. */
7007 if ((i.base_reg
40fb9820
L		 7008 && (!i.base_reg->reg_type.bitfield.reg16
7009 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 7010 || (i.index_reg
40fb9820
L		 7011 && (!i.index_reg->reg_type.bitfield.reg16
7012 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 7013 || !(i.base_reg
7014 && i.base_reg->reg_num < 6
7015 && i.index_reg->reg_num >= 6
7016 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 7017 ok = 0;
7018 }
7019 else
e5cb08ac 7020 {
3e73aa7c
JH		 7021 /* 32bit checks. */
7022 if ((i.base_reg
40fb9820 7023 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 7024 || (i.index_reg
db51cc60
L		 7025 && ((!i.index_reg->reg_type.bitfield.reg32
7026 && i.index_reg->reg_num != RegEiz)
40fb9820 7027 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 7028 ok = 0;
3e73aa7c
JH		 7029 }
7030 }
7031 if (!ok)
24eab124
AM		 7032 {
7033#if INFER_ADDR_PREFIX
fc0763e6 7034 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 7035 {
7036 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
7037 i.prefixes += 1;
b23bac36
AM		 7038 /* Change the size of any displacement too. At most one of
7039 Disp16 or Disp32 is set.
7040 FIXME. There doesn't seem to be any real need for separate
7041 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 7042 Removing them would probably clean up the code quite a lot. */
4eed87de 7043 if (flag_code != CODE_64BIT
40fb9820
L		 7044 && (i.types[this_operand].bitfield.disp16
7045 || i.types[this_operand].bitfield.disp32))
7046 i.types[this_operand]
c6fb90c8 7047 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 7048 fudged = 1;
24eab124
AM		 7049 goto tryprefix;
7050 }
eecb386c 7051 if (fudged)
fc0763e6
JB		 7052 as_bad (_("`%s' is not a valid %s expression"),
7053 operand_string,
7054 kind);
eecb386c 7055 else
c388dee8 7056#endif
fc0763e6 7057 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 7058 operand_string,
fc0763e6
JB		 7059 flag_code_names[i.prefix[ADDR_PREFIX]
7060 ? flag_code == CODE_32BIT
7061 ? CODE_16BIT
7062 : CODE_32BIT
7063 : flag_code],
7064 kind);
24eab124 7065 }
20f0a1fc 7066 return ok;
24eab124 7067}
252b5132 7068
fc0763e6 7069/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 7070 on error. */
252b5132 7071
252b5132 7072static int
a7619375 7073i386_att_operand (char *operand_string)
252b5132 7074{
af6bdddf
AM		 7075 const reg_entry *r;
7076 char *end_op;
24eab124 7077 char *op_string = operand_string;
252b5132 7078
24eab124 7079 if (is_space_char (*op_string))
252b5132
RH		 7080 ++op_string;
7081
24eab124 7082 /* We check for an absolute prefix (differentiating,
47926f60 7083 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 7084 if (*op_string == ABSOLUTE_PREFIX)
7085 {
7086 ++op_string;
7087 if (is_space_char (*op_string))
7088 ++op_string;
40fb9820 7089 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 7090 }
252b5132 7091
47926f60 7092 /* Check if operand is a register. */
4d1bb795 7093 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 7094 {
40fb9820
L		 7095 i386_operand_type temp;
7096
24eab124
AM		 7097 /* Check for a segment override by searching for ':' after a
7098 segment register. */
7099 op_string = end_op;
7100 if (is_space_char (*op_string))
7101 ++op_string;
40fb9820
L		 7102 if (*op_string == ':'
7103 && (r->reg_type.bitfield.sreg2
7104 || r->reg_type.bitfield.sreg3))
24eab124
AM		 7105 {
7106 switch (r->reg_num)
7107 {
7108 case 0:
7109 i.seg[i.mem_operands] = &es;
7110 break;
7111 case 1:
7112 i.seg[i.mem_operands] = &cs;
7113 break;
7114 case 2:
7115 i.seg[i.mem_operands] = &ss;
7116 break;
7117 case 3:
7118 i.seg[i.mem_operands] = &ds;
7119 break;
7120 case 4:
7121 i.seg[i.mem_operands] = &fs;
7122 break;
7123 case 5:
7124 i.seg[i.mem_operands] = &gs;
7125 break;
7126 }
252b5132 7127
24eab124 7128 /* Skip the ':' and whitespace. */
252b5132
RH		 7129 ++op_string;
7130 if (is_space_char (*op_string))
24eab124 7131 ++op_string;
252b5132 7132
24eab124
AM		 7133 if (!is_digit_char (*op_string)
7134 && !is_identifier_char (*op_string)
7135 && *op_string != '('
7136 && *op_string != ABSOLUTE_PREFIX)
7137 {
7138 as_bad (_("bad memory operand `%s'"), op_string);
7139 return 0;
7140 }
47926f60 7141 /* Handle case of %es:*foo. */
24eab124
AM		 7142 if (*op_string == ABSOLUTE_PREFIX)
7143 {
7144 ++op_string;
7145 if (is_space_char (*op_string))
7146 ++op_string;
40fb9820 7147 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 7148 }
7149 goto do_memory_reference;
7150 }
7151 if (*op_string)
7152 {
d0b47220 7153 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 7154 return 0;
7155 }
40fb9820
L		 7156 temp = r->reg_type;
7157 temp.bitfield.baseindex = 0;
c6fb90c8
L		 7158 i.types[this_operand] = operand_type_or (i.types[this_operand],
7159 temp);
7d5e4556 7160 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 7161 i.op[this_operand].regs = r;
24eab124
AM		 7162 i.reg_operands++;
7163 }
af6bdddf
AM		 7164 else if (*op_string == REGISTER_PREFIX)
7165 {
7166 as_bad (_("bad register name `%s'"), op_string);
7167 return 0;
7168 }
24eab124 7169 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7170 {
24eab124 7171 ++op_string;
40fb9820 7172 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7173 {
d0b47220 7174 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7175 return 0;
7176 }
7177 if (!i386_immediate (op_string))
7178 return 0;
7179 }
7180 else if (is_digit_char (*op_string)
7181 || is_identifier_char (*op_string)
e5cb08ac 7182 || *op_string == '(')
24eab124 7183 {
47926f60 7184 /* This is a memory reference of some sort. */
af6bdddf 7185 char *base_string;
252b5132 7186
47926f60 7187 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7188 char *displacement_string_start;
7189 char *displacement_string_end;
252b5132 7190
24eab124 7191 do_memory_reference:
24eab124 7192 if ((i.mem_operands == 1
40fb9820 7193 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7194 || i.mem_operands == 2)
7195 {
7196 as_bad (_("too many memory references for `%s'"),
7197 current_templates->start->name);
7198 return 0;
7199 }
252b5132 7200
24eab124
AM		 7201 /* Check for base index form. We detect the base index form by
7202 looking for an ')' at the end of the operand, searching
7203 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7204 after the '('. */
af6bdddf 7205 base_string = op_string + strlen (op_string);
c3332e24 7206
af6bdddf
AM		 7207 --base_string;
7208 if (is_space_char (*base_string))
7209 --base_string;
252b5132 7210
47926f60 7211 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7212 displacement_string_start = op_string;
7213 displacement_string_end = base_string + 1;
252b5132 7214
24eab124
AM		 7215 if (*base_string == ')')
7216 {
af6bdddf 7217 char *temp_string;
24eab124
AM		 7218 unsigned int parens_balanced = 1;
7219 /* We've already checked that the number of left & right ()'s are
47926f60 7220 equal, so this loop will not be infinite. */
24eab124
AM		 7221 do
7222 {
7223 base_string--;
7224 if (*base_string == ')')
7225 parens_balanced++;
7226 if (*base_string == '(')
7227 parens_balanced--;
7228 }
7229 while (parens_balanced);
c3332e24 7230
af6bdddf 7231 temp_string = base_string;
c3332e24 7232
24eab124 7233 /* Skip past '(' and whitespace. */
252b5132
RH		 7234 ++base_string;
7235 if (is_space_char (*base_string))
24eab124 7236 ++base_string;
252b5132 7237
af6bdddf 7238 if (*base_string == ','
4eed87de
AM		 7239 || ((i.base_reg = parse_register (base_string, &end_op))
7240 != NULL))
252b5132 7241 {
af6bdddf 7242 displacement_string_end = temp_string;
252b5132 7243
40fb9820 7244 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7245
af6bdddf 7246 if (i.base_reg)
24eab124 7247 {
24eab124
AM		 7248 base_string = end_op;
7249 if (is_space_char (*base_string))
7250 ++base_string;
af6bdddf
AM		 7251 }
7252
7253 /* There may be an index reg or scale factor here. */
7254 if (*base_string == ',')
7255 {
7256 ++base_string;
7257 if (is_space_char (*base_string))
7258 ++base_string;
7259
4eed87de
AM		 7260 if ((i.index_reg = parse_register (base_string, &end_op))
7261 != NULL)
24eab124 7262 {
af6bdddf 7263 base_string = end_op;
24eab124
AM		 7264 if (is_space_char (*base_string))
7265 ++base_string;
af6bdddf
AM		 7266 if (*base_string == ',')
7267 {
7268 ++base_string;
7269 if (is_space_char (*base_string))
7270 ++base_string;
7271 }
e5cb08ac 7272 else if (*base_string != ')')
af6bdddf 7273 {
4eed87de
AM		 7274 as_bad (_("expecting `,' or `)' "
7275 "after index register in `%s'"),
af6bdddf
AM		 7276 operand_string);
7277 return 0;
7278 }
24eab124 7279 }
af6bdddf 7280 else if (*base_string == REGISTER_PREFIX)
24eab124 7281 {
af6bdddf 7282 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7283 return 0;
7284 }
252b5132 7285
47926f60 7286 /* Check for scale factor. */
551c1ca1 7287 if (*base_string != ')')
af6bdddf 7288 {
551c1ca1
AM		 7289 char *end_scale = i386_scale (base_string);
7290
7291 if (!end_scale)
af6bdddf 7292 return 0;
24eab124 7293
551c1ca1 7294 base_string = end_scale;
af6bdddf
AM		 7295 if (is_space_char (*base_string))
7296 ++base_string;
7297 if (*base_string != ')')
7298 {
4eed87de
AM		 7299 as_bad (_("expecting `)' "
7300 "after scale factor in `%s'"),
af6bdddf
AM		 7301 operand_string);
7302 return 0;
7303 }
7304 }
7305 else if (!i.index_reg)
24eab124 7306 {
4eed87de
AM		 7307 as_bad (_("expecting index register or scale factor "
7308 "after `,'; got '%c'"),
af6bdddf 7309 *base_string);
24eab124
AM		 7310 return 0;
7311 }
7312 }
af6bdddf 7313 else if (*base_string != ')')
24eab124 7314 {
4eed87de
AM		 7315 as_bad (_("expecting `,' or `)' "
7316 "after base register in `%s'"),
af6bdddf 7317 operand_string);
24eab124
AM		 7318 return 0;
7319 }
c3332e24 7320 }
af6bdddf 7321 else if (*base_string == REGISTER_PREFIX)
c3332e24 7322 {
af6bdddf 7323 as_bad (_("bad register name `%s'"), base_string);
24eab124 7324 return 0;
c3332e24 7325 }
24eab124
AM		 7326 }
7327
7328 /* If there's an expression beginning the operand, parse it,
7329 assuming displacement_string_start and
7330 displacement_string_end are meaningful. */
7331 if (displacement_string_start != displacement_string_end)
7332 {
7333 if (!i386_displacement (displacement_string_start,
7334 displacement_string_end))
7335 return 0;
7336 }
7337
7338 /* Special case for (%dx) while doing input/output op. */
7339 if (i.base_reg
0dfbf9d7
L		 7340 && operand_type_equal (&i.base_reg->reg_type,
7341 &reg16_inoutportreg)
24eab124
AM		 7342 && i.index_reg == 0
7343 && i.log2_scale_factor == 0
7344 && i.seg[i.mem_operands] == 0
40fb9820 7345 && !operand_type_check (i.types[this_operand], disp))
24eab124 7346 {
65da13b5 7347 i.types[this_operand] = inoutportreg;
24eab124
AM		 7348 return 1;
7349 }
7350
eecb386c
AM		 7351 if (i386_index_check (operand_string) == 0)
7352 return 0;
5c07affc 7353 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7354 i.mem_operands++;
7355 }
7356 else
ce8a8b2f
AM		 7357 {
7358 /* It's not a memory operand; argh! */
24eab124
AM		 7359 as_bad (_("invalid char %s beginning operand %d `%s'"),
7360 output_invalid (*op_string),
7361 this_operand + 1,
7362 op_string);
7363 return 0;
7364 }
47926f60 7365 return 1; /* Normal return. */
252b5132
RH		 7366}
7367\f
ee7fcc42
AM		 7368/* md_estimate_size_before_relax()
7369
7370 Called just before relax() for rs_machine_dependent frags. The x86
7371 assembler uses these frags to handle variable size jump
7372 instructions.
7373
7374 Any symbol that is now undefined will not become defined.
7375 Return the correct fr_subtype in the frag.
7376 Return the initial "guess for variable size of frag" to caller.
7377 The guess is actually the growth beyond the fixed part. Whatever
7378 we do to grow the fixed or variable part contributes to our
7379 returned value. */
7380
252b5132
RH		 7381int
7382md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 7383 fragS *fragP;
7384 segT segment;
252b5132 7385{
252b5132 7386 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7387 check for un-relaxable symbols. On an ELF system, we can't relax
7388 an externally visible symbol, because it may be overridden by a
7389 shared library. */
7390 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7391#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7392 || (IS_ELF
31312f95
AM		 7393 && (S_IS_EXTERNAL (fragP->fr_symbol)
7394 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 7395#endif
7396 )
252b5132 7397 {
b98ef147
AM		 7398 /* Symbol is undefined in this segment, or we need to keep a
7399 reloc so that weak symbols can be overridden. */
7400 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7401 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7402 unsigned char *opcode;
7403 int old_fr_fix;
f6af82bd 7404
ee7fcc42
AM		 7405 if (fragP->fr_var != NO_RELOC)
7406 reloc_type = fragP->fr_var;
b98ef147 7407 else if (size == 2)
f6af82bd
AM		 7408 reloc_type = BFD_RELOC_16_PCREL;
7409 else
7410 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7411
ee7fcc42
AM		 7412 old_fr_fix = fragP->fr_fix;
7413 opcode = (unsigned char *) fragP->fr_opcode;
7414
fddf5b5b 7415 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7416 {
fddf5b5b
AM		 7417 case UNCOND_JUMP:
7418 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7419 opcode[0] = 0xe9;
252b5132 7420 fragP->fr_fix += size;
062cd5e7
AS		 7421 fix_new (fragP, old_fr_fix, size,
7422 fragP->fr_symbol,
7423 fragP->fr_offset, 1,
7424 reloc_type);
252b5132
RH		 7425 break;
7426
fddf5b5b 7427 case COND_JUMP86:
412167cb
AM		 7428 if (size == 2
7429 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7430 {
7431 /* Negate the condition, and branch past an
7432 unconditional jump. */
7433 opcode[0] ^= 1;
7434 opcode[1] = 3;
7435 /* Insert an unconditional jump. */
7436 opcode[2] = 0xe9;
7437 /* We added two extra opcode bytes, and have a two byte
7438 offset. */
7439 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7440 fix_new (fragP, old_fr_fix + 2, 2,
7441 fragP->fr_symbol,
7442 fragP->fr_offset, 1,
7443 reloc_type);
fddf5b5b
AM		 7444 break;
7445 }
7446 /* Fall through. */
7447
7448 case COND_JUMP:
412167cb
AM		 7449 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7450 {
3e02c1cc
AM		 7451 fixS *fixP;
7452
412167cb 7453 fragP->fr_fix += 1;
3e02c1cc
AM		 7454 fixP = fix_new (fragP, old_fr_fix, 1,
7455 fragP->fr_symbol,
7456 fragP->fr_offset, 1,
7457 BFD_RELOC_8_PCREL);
7458 fixP->fx_signed = 1;
412167cb
AM		 7459 break;
7460 }
93c2a809 7461
24eab124 7462 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7463 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7464 opcode[1] = opcode[0] + 0x10;
f6af82bd 7465 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7466 /* We've added an opcode byte. */
7467 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7468 fix_new (fragP, old_fr_fix + 1, size,
7469 fragP->fr_symbol,
7470 fragP->fr_offset, 1,
7471 reloc_type);
252b5132 7472 break;
fddf5b5b
AM		 7473
7474 default:
7475 BAD_CASE (fragP->fr_subtype);
7476 break;
252b5132
RH		 7477 }
7478 frag_wane (fragP);
ee7fcc42 7479 return fragP->fr_fix - old_fr_fix;
252b5132 7480 }
93c2a809 7481
93c2a809
AM		 7482 /* Guess size depending on current relax state. Initially the relax
7483 state will correspond to a short jump and we return 1, because
7484 the variable part of the frag (the branch offset) is one byte
7485 long. However, we can relax a section more than once and in that
7486 case we must either set fr_subtype back to the unrelaxed state,
7487 or return the value for the appropriate branch. */
7488 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7489}
7490
47926f60
KH		 7491/* Called after relax() is finished.
7492
7493 In: Address of frag.
7494 fr_type == rs_machine_dependent.
7495 fr_subtype is what the address relaxed to.
7496
7497 Out: Any fixSs and constants are set up.
7498 Caller will turn frag into a ".space 0". */
7499
252b5132
RH		 7500void
7501md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7502 bfd *abfd ATTRIBUTE_UNUSED;
7503 segT sec ATTRIBUTE_UNUSED;
29b0f896 7504 fragS *fragP;
252b5132 7505{
29b0f896 7506 unsigned char *opcode;
252b5132 7507 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7508 offsetT target_address;
7509 offsetT opcode_address;
252b5132 7510 unsigned int extension = 0;
847f7ad4 7511 offsetT displacement_from_opcode_start;
252b5132
RH		 7512
7513 opcode = (unsigned char *) fragP->fr_opcode;
7514
47926f60 7515 /* Address we want to reach in file space. */
252b5132 7516 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7517
47926f60 7518 /* Address opcode resides at in file space. */
252b5132
RH		 7519 opcode_address = fragP->fr_address + fragP->fr_fix;
7520
47926f60 7521 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7522 displacement_from_opcode_start = target_address - opcode_address;
7523
fddf5b5b 7524 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7525 {
47926f60
KH		 7526 /* Don't have to change opcode. */
7527 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7528 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7529 }
7530 else
7531 {
7532 if (no_cond_jump_promotion
7533 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7534 as_warn_where (fragP->fr_file, fragP->fr_line,
7535 _("long jump required"));
252b5132 7536
fddf5b5b
AM		 7537 switch (fragP->fr_subtype)
7538 {
7539 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7540 extension = 4; /* 1 opcode + 4 displacement */
7541 opcode[0] = 0xe9;
7542 where_to_put_displacement = &opcode[1];
7543 break;
252b5132 7544
fddf5b5b
AM		 7545 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7546 extension = 2; /* 1 opcode + 2 displacement */
7547 opcode[0] = 0xe9;
7548 where_to_put_displacement = &opcode[1];
7549 break;
252b5132 7550
fddf5b5b
AM		 7551 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7552 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7553 extension = 5; /* 2 opcode + 4 displacement */
7554 opcode[1] = opcode[0] + 0x10;
7555 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7556 where_to_put_displacement = &opcode[2];
7557 break;
252b5132 7558
fddf5b5b
AM		 7559 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7560 extension = 3; /* 2 opcode + 2 displacement */
7561 opcode[1] = opcode[0] + 0x10;
7562 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7563 where_to_put_displacement = &opcode[2];
7564 break;
252b5132 7565
fddf5b5b
AM		 7566 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7567 extension = 4;
7568 opcode[0] ^= 1;
7569 opcode[1] = 3;
7570 opcode[2] = 0xe9;
7571 where_to_put_displacement = &opcode[3];
7572 break;
7573
7574 default:
7575 BAD_CASE (fragP->fr_subtype);
7576 break;
7577 }
252b5132 7578 }
fddf5b5b 7579
7b81dfbb
AJ		 7580 /* If size if less then four we are sure that the operand fits,
7581 but if it's 4, then it could be that the displacement is larger
7582 then -/+ 2GB. */
7583 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7584 && object_64bit
7585 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7586 + ((addressT) 1 << 31))
7587 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7588 {
7589 as_bad_where (fragP->fr_file, fragP->fr_line,
7590 _("jump target out of range"));
7591 /* Make us emit 0. */
7592 displacement_from_opcode_start = extension;
7593 }
47926f60 7594 /* Now put displacement after opcode. */
252b5132
RH		 7595 md_number_to_chars ((char *) where_to_put_displacement,
7596 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7597 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7598 fragP->fr_fix += extension;
7599}
7600\f
252b5132
RH		 7601/* Apply a fixup (fixS) to segment data, once it has been determined
7602 by our caller that we have all the info we need to fix it up.
7603
7604 On the 386, immediates, displacements, and data pointers are all in
7605 the same (little-endian) format, so we don't need to care about which
7606 we are handling. */
7607
94f592af 7608void
55cf6793 7609md_apply_fix (fixP, valP, seg)
47926f60
KH		 7610 /* The fix we're to put in. */
7611 fixS *fixP;
47926f60 7612 /* Pointer to the value of the bits. */
c6682705 7613 valueT *valP;
47926f60
KH		 7614 /* Segment fix is from. */
7615 segT seg ATTRIBUTE_UNUSED;
252b5132 7616{
94f592af 7617 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7618 valueT value = *valP;
252b5132 7619
f86103b7 7620#if !defined (TE_Mach)
93382f6d
AM		 7621 if (fixP->fx_pcrel)
7622 {
7623 switch (fixP->fx_r_type)
7624 {
5865bb77
ILT		 7625 default:
7626 break;
7627
d6ab8113
JB		 7628 case BFD_RELOC_64:
7629 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7630 break;
93382f6d 7631 case BFD_RELOC_32:
ae8887b5 7632 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7633 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7634 break;
7635 case BFD_RELOC_16:
7636 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7637 break;
7638 case BFD_RELOC_8:
7639 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7640 break;
7641 }
7642 }
252b5132 7643
a161fe53 7644 if (fixP->fx_addsy != NULL
31312f95 7645 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7646 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7647 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7648 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7649 && !use_rela_relocations)
252b5132 7650 {
31312f95
AM		 7651 /* This is a hack. There should be a better way to handle this.
7652 This covers for the fact that bfd_install_relocation will
7653 subtract the current location (for partial_inplace, PC relative
7654 relocations); see more below. */
252b5132 7655#ifndef OBJ_AOUT
718ddfc0 7656 if (IS_ELF
252b5132
RH		 7657#ifdef TE_PE
7658 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7659#endif
7660 )
7661 value += fixP->fx_where + fixP->fx_frag->fr_address;
7662#endif
7663#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7664 if (IS_ELF)
252b5132 7665 {
6539b54b 7666 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7667
6539b54b 7668 if ((sym_seg == seg
2f66722d 7669 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7670 && sym_seg != absolute_section))
ae6063d4 7671 && !generic_force_reloc (fixP))
2f66722d
AM		 7672 {
7673 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7674 bfd_install_relocation subtracts them out again. I think
7675 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7676 it. FIXME. */
7677 value += fixP->fx_where + fixP->fx_frag->fr_address;
7678 }
252b5132
RH		 7679 }
7680#endif
7681#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7682 /* For some reason, the PE format does not store a
7683 section address offset for a PC relative symbol. */
7684 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7685 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7686 value += md_pcrel_from (fixP);
7687#endif
7688 }
7689
7690 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7691 and we must not disappoint it. */
252b5132 7692#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7693 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7694 switch (fixP->fx_r_type)
7695 {
7696 case BFD_RELOC_386_PLT32:
3e73aa7c 7697 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7698 /* Make the jump instruction point to the address of the operand. At
7699 runtime we merely add the offset to the actual PLT entry. */
7700 value = -4;
7701 break;
31312f95 7702
13ae64f3
JJ		 7703 case BFD_RELOC_386_TLS_GD:
7704 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7705 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7706 case BFD_RELOC_386_TLS_IE:
7707 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7708 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7709 case BFD_RELOC_X86_64_TLSGD:
7710 case BFD_RELOC_X86_64_TLSLD:
7711 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7712 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7713 value = 0; /* Fully resolved at runtime. No addend. */
7714 /* Fallthrough */
7715 case BFD_RELOC_386_TLS_LE:
7716 case BFD_RELOC_386_TLS_LDO_32:
7717 case BFD_RELOC_386_TLS_LE_32:
7718 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7719 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7720 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7721 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7722 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7723 break;
7724
67a4f2b7
AO		 7725 case BFD_RELOC_386_TLS_DESC_CALL:
7726 case BFD_RELOC_X86_64_TLSDESC_CALL:
7727 value = 0; /* Fully resolved at runtime. No addend. */
7728 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7729 fixP->fx_done = 0;
7730 return;
7731
00f7efb6
JJ		 7732 case BFD_RELOC_386_GOT32:
7733 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7734 value = 0; /* Fully resolved at runtime. No addend. */
7735 break;
47926f60
KH		 7736
7737 case BFD_RELOC_VTABLE_INHERIT:
7738 case BFD_RELOC_VTABLE_ENTRY:
7739 fixP->fx_done = 0;
94f592af 7740 return;
47926f60
KH		 7741
7742 default:
7743 break;
7744 }
7745#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7746 *valP = value;
f86103b7 7747#endif /* !defined (TE_Mach) */
3e73aa7c 7748
3e73aa7c 7749 /* Are we finished with this relocation now? */
c6682705 7750 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 7751 fixP->fx_done = 1;
7752 else if (use_rela_relocations)
7753 {
7754 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7755 /* Remember value for tc_gen_reloc. */
7756 fixP->fx_addnumber = value;
3e73aa7c
JH		 7757 value = 0;
7758 }
f86103b7 7759
94f592af 7760 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7761}
252b5132 7762\f
252b5132 7763char *
499ac353 7764md_atof (int type, char *litP, int *sizeP)
252b5132 7765{
499ac353
NC		 7766 /* This outputs the LITTLENUMs in REVERSE order;
7767 in accord with the bigendian 386. */
7768 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7769}
7770\f
2d545b82 7771static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7772
252b5132 7773static char *
e3bb37b5 7774output_invalid (int c)
252b5132 7775{
3882b010 7776 if (ISPRINT (c))
f9f21a03
L		 7777 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7778 "'%c'", c);
252b5132 7779 else
f9f21a03 7780 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7781 "(0x%x)", (unsigned char) c);
252b5132
RH		 7782 return output_invalid_buf;
7783}
7784
af6bdddf 7785/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7786
7787static const reg_entry *
4d1bb795 7788parse_real_register (char *reg_string, char **end_op)
252b5132 7789{
af6bdddf
AM		 7790 char *s = reg_string;
7791 char *p;
252b5132
RH		 7792 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7793 const reg_entry *r;
7794
7795 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7796 if (*s == REGISTER_PREFIX)
7797 ++s;
7798
7799 if (is_space_char (*s))
7800 ++s;
7801
7802 p = reg_name_given;
af6bdddf 7803 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7804 {
7805 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7806 return (const reg_entry *) NULL;
7807 s++;
252b5132
RH		 7808 }
7809
6588847e
DN		 7810 /* For naked regs, make sure that we are not dealing with an identifier.
7811 This prevents confusing an identifier like `eax_var' with register
7812 `eax'. */
7813 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7814 return (const reg_entry *) NULL;
7815
af6bdddf 7816 *end_op = s;
252b5132
RH		 7817
7818 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7819
5f47d35b 7820 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7821 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7822 {
5f47d35b
AM		 7823 if (is_space_char (*s))
7824 ++s;
7825 if (*s == '(')
7826 {
af6bdddf 7827 ++s;
5f47d35b
AM		 7828 if (is_space_char (*s))
7829 ++s;
7830 if (*s >= '0' && *s <= '7')
7831 {
db557034 7832 int fpr = *s - '0';
af6bdddf 7833 ++s;
5f47d35b
AM		 7834 if (is_space_char (*s))
7835 ++s;
7836 if (*s == ')')
7837 {
7838 *end_op = s + 1;
db557034
AM		 7839 r = hash_find (reg_hash, "st(0)");
7840 know (r);
7841 return r + fpr;
5f47d35b 7842 }
5f47d35b 7843 }
47926f60 7844 /* We have "%st(" then garbage. */
5f47d35b
AM		 7845 return (const reg_entry *) NULL;
7846 }
7847 }
7848
a60de03c
JB		 7849 if (r == NULL || allow_pseudo_reg)
7850 return r;
7851
0dfbf9d7 7852 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7853 return (const reg_entry *) NULL;
7854
192dc9c6
JB		 7855 if ((r->reg_type.bitfield.reg32
7856 || r->reg_type.bitfield.sreg3
7857 || r->reg_type.bitfield.control
7858 || r->reg_type.bitfield.debug
7859 || r->reg_type.bitfield.test)
7860 && !cpu_arch_flags.bitfield.cpui386)
7861 return (const reg_entry *) NULL;
7862
7863 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7864 return (const reg_entry *) NULL;
7865
7866 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7867 return (const reg_entry *) NULL;
7868
40f12533
L		 7869 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7870 return (const reg_entry *) NULL;
7871
db51cc60 7872 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7873 if (!allow_index_reg
db51cc60
L		 7874 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7875 return (const reg_entry *) NULL;
7876
a60de03c
JB		 7877 if (((r->reg_flags & (RegRex64 | RegRex))
7878 || r->reg_type.bitfield.reg64)
40fb9820 7879 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7880 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7881 && flag_code != CODE_64BIT)
20f0a1fc 7882 return (const reg_entry *) NULL;
1ae00879 7883
b7240065
JB		 7884 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7885 return (const reg_entry *) NULL;
7886
252b5132
RH		 7887 return r;
7888}
4d1bb795
JB		 7889
7890/* REG_STRING starts *before* REGISTER_PREFIX. */
7891
7892static const reg_entry *
7893parse_register (char *reg_string, char **end_op)
7894{
7895 const reg_entry *r;
7896
7897 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7898 r = parse_real_register (reg_string, end_op);
7899 else
7900 r = NULL;
7901 if (!r)
7902 {
7903 char *save = input_line_pointer;
7904 char c;
7905 symbolS *symbolP;
7906
7907 input_line_pointer = reg_string;
7908 c = get_symbol_end ();
7909 symbolP = symbol_find (reg_string);
7910 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7911 {
7912 const expressionS *e = symbol_get_value_expression (symbolP);
7913
7914 know (e->X_op == O_register);
4eed87de 7915 know (e->X_add_number >= 0
c3fe08fa 7916 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7917 r = i386_regtab + e->X_add_number;
7918 *end_op = input_line_pointer;
7919 }
7920 *input_line_pointer = c;
7921 input_line_pointer = save;
7922 }
7923 return r;
7924}
7925
7926int
7927i386_parse_name (char *name, expressionS *e, char *nextcharP)
7928{
7929 const reg_entry *r;
7930 char *end = input_line_pointer;
7931
7932 *end = *nextcharP;
7933 r = parse_register (name, &input_line_pointer);
7934 if (r && end <= input_line_pointer)
7935 {
7936 *nextcharP = *input_line_pointer;
7937 *input_line_pointer = 0;
7938 e->X_op = O_register;
7939 e->X_add_number = r - i386_regtab;
7940 return 1;
7941 }
7942 input_line_pointer = end;
7943 *end = 0;
7944 return 0;
7945}
7946
7947void
7948md_operand (expressionS *e)
7949{
7950 if (*input_line_pointer == REGISTER_PREFIX)
7951 {
7952 char *end;
7953 const reg_entry *r = parse_real_register (input_line_pointer, &end);
7954
7955 if (r)
7956 {
7957 e->X_op = O_register;
7958 e->X_add_number = r - i386_regtab;
7959 input_line_pointer = end;
7960 }
7961 }
7962}
7963
252b5132 7964\f
4cc782b5 7965#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7966const char *md_shortopts = "kVQ:sqn";
252b5132 7967#else
12b55ccc 7968const char *md_shortopts = "qn";
252b5132 7969#endif
6e0b89ee 7970
3e73aa7c 7971#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7972#define OPTION_64 (OPTION_MD_BASE + 1)
7973#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7974#define OPTION_MARCH (OPTION_MD_BASE + 3)
7975#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 7976#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7977#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7978#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7979#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7980#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 7981#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 7982#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
b3b91714 7983
99ad8390
NC		 7984struct option md_longopts[] =
7985{
3e73aa7c 7986 {"32", no_argument, NULL, OPTION_32},
99ad8390 7987#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 7988 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7989#endif
b3b91714 7990 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7991 {"march", required_argument, NULL, OPTION_MARCH},
7992 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 7993 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7994 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7995 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7996 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7997 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 7998 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 7999 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
252b5132
RH		 8000 {NULL, no_argument, NULL, 0}
8001};
8002size_t md_longopts_size = sizeof (md_longopts);
8003
8004int
9103f4f4 8005md_parse_option (int c, char *arg)
252b5132 8006{
9103f4f4 8007 unsigned int i;
6305a203 8008 char *arch, *next;
9103f4f4 8009
252b5132
RH		 8010 switch (c)
8011 {
12b55ccc
L		 8012 case 'n':
8013 optimize_align_code = 0;
8014 break;
8015
a38cf1db
AM		 8016 case 'q':
8017 quiet_warnings = 1;
252b5132
RH		 8018 break;
8019
8020#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 8021 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8022 should be emitted or not. FIXME: Not implemented. */
8023 case 'Q':
252b5132
RH		 8024 break;
8025
8026 /* -V: SVR4 argument to print version ID. */
8027 case 'V':
8028 print_version_id ();
8029 break;
8030
a38cf1db
AM		 8031 /* -k: Ignore for FreeBSD compatibility. */
8032 case 'k':
252b5132 8033 break;
4cc782b5
ILT		 8034
8035 case 's':
8036 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 8037 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 8038 break;
99ad8390
NC		 8039#endif
8040#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 8041 case OPTION_64:
8042 {
8043 const char **list, **l;
8044
3e73aa7c
JH		 8045 list = bfd_target_list ();
8046 for (l = list; *l != NULL; l++)
8620418b 8047 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 8048 || strcmp (*l, "coff-x86-64") == 0
8049 || strcmp (*l, "pe-x86-64") == 0
8050 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 8051 {
8052 default_arch = "x86_64";
8053 break;
8054 }
3e73aa7c 8055 if (*l == NULL)
6e0b89ee 8056 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 8057 free (list);
8058 }
8059 break;
8060#endif
252b5132 8061
6e0b89ee
AM		 8062 case OPTION_32:
8063 default_arch = "i386";
8064 break;
8065
b3b91714
AM		 8066 case OPTION_DIVIDE:
8067#ifdef SVR4_COMMENT_CHARS
8068 {
8069 char *n, *t;
8070 const char *s;
8071
8072 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
8073 t = n;
8074 for (s = i386_comment_chars; *s != '\0'; s++)
8075 if (*s != '/')
8076 *t++ = *s;
8077 *t = '\0';
8078 i386_comment_chars = n;
8079 }
8080#endif
8081 break;
8082
9103f4f4 8083 case OPTION_MARCH:
6305a203
L		 8084 arch = xstrdup (arg);
8085 do
9103f4f4 8086 {
6305a203
L		 8087 if (*arch == '.')
8088 as_fatal (_("Invalid -march= option: `%s'"), arg);
8089 next = strchr (arch, '+');
8090 if (next)
8091 *next++ = '\0';
8092 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
9103f4f4 8093 {
6305a203 8094 if (strcmp (arch, cpu_arch [i].name) == 0)
ccc9c027 8095 {
6305a203
L		 8096 /* Processor. */
8097 cpu_arch_name = cpu_arch[i].name;
8098 cpu_sub_arch_name = NULL;
8099 cpu_arch_flags = cpu_arch[i].flags;
8100 cpu_arch_isa = cpu_arch[i].type;
8101 cpu_arch_isa_flags = cpu_arch[i].flags;
8102 if (!cpu_arch_tune_set)
8103 {
8104 cpu_arch_tune = cpu_arch_isa;
8105 cpu_arch_tune_flags = cpu_arch_isa_flags;
8106 }
8107 break;
8108 }
8109 else if (*cpu_arch [i].name == '.'
8110 && strcmp (arch, cpu_arch [i].name + 1) == 0)
8111 {
8112 /* ISA entension. */
8113 i386_cpu_flags flags;
8114 flags = cpu_flags_or (cpu_arch_flags,
8115 cpu_arch[i].flags);
0dfbf9d7 8116 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8117 {
8118 if (cpu_sub_arch_name)
8119 {
8120 char *name = cpu_sub_arch_name;
8121 cpu_sub_arch_name = concat (name,
8122 cpu_arch[i].name,
1bf57e9f 8123 (const char *) NULL);
6305a203
L		 8124 free (name);
8125 }
8126 else
8127 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
8128 cpu_arch_flags = flags;
8129 }
8130 break;
ccc9c027 8131 }
9103f4f4 8132 }
6305a203
L		 8133
8134 if (i >= ARRAY_SIZE (cpu_arch))
8135 as_fatal (_("Invalid -march= option: `%s'"), arg);
8136
8137 arch = next;
9103f4f4 8138 }
6305a203 8139 while (next != NULL );
9103f4f4
L		 8140 break;
8141
8142 case OPTION_MTUNE:
8143 if (*arg == '.')
8144 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8145 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
8146 {
8147 if (strcmp (arg, cpu_arch [i].name) == 0)
8148 {
ccc9c027 8149 cpu_arch_tune_set = 1;
9103f4f4
L		 8150 cpu_arch_tune = cpu_arch [i].type;
8151 cpu_arch_tune_flags = cpu_arch[i].flags;
8152 break;
8153 }
8154 }
8155 if (i >= ARRAY_SIZE (cpu_arch))
8156 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8157 break;
8158
1efbbeb4
L		 8159 case OPTION_MMNEMONIC:
8160 if (strcasecmp (arg, "att") == 0)
8161 intel_mnemonic = 0;
8162 else if (strcasecmp (arg, "intel") == 0)
8163 intel_mnemonic = 1;
8164 else
8165 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
8166 break;
8167
8168 case OPTION_MSYNTAX:
8169 if (strcasecmp (arg, "att") == 0)
8170 intel_syntax = 0;
8171 else if (strcasecmp (arg, "intel") == 0)
8172 intel_syntax = 1;
8173 else
8174 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
8175 break;
8176
8177 case OPTION_MINDEX_REG:
8178 allow_index_reg = 1;
8179 break;
8180
8181 case OPTION_MNAKED_REG:
8182 allow_naked_reg = 1;
8183 break;
8184
8185 case OPTION_MOLD_GCC:
8186 old_gcc = 1;
1efbbeb4
L		 8187 break;
8188
c0f3af97
L		 8189 case OPTION_MSSE2AVX:
8190 sse2avx = 1;
8191 break;
8192
daf50ae7
L		 8193 case OPTION_MSSE_CHECK:
8194 if (strcasecmp (arg, "error") == 0)
8195 sse_check = sse_check_error;
8196 else if (strcasecmp (arg, "warning") == 0)
8197 sse_check = sse_check_warning;
8198 else if (strcasecmp (arg, "none") == 0)
8199 sse_check = sse_check_none;
8200 else
8201 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
8202 break;
8203
252b5132
RH		 8204 default:
8205 return 0;
8206 }
8207 return 1;
8208}
8209
8210void
8211md_show_usage (stream)
8212 FILE *stream;
8213{
4cc782b5
ILT		 8214#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8215 fprintf (stream, _("\
a38cf1db
AM		 8216 -Q ignored\n\
8217 -V print assembler version number\n\
b3b91714
AM		 8218 -k ignored\n"));
8219#endif
8220 fprintf (stream, _("\
12b55ccc 8221 -n Do not optimize code alignment\n\
b3b91714
AM		 8222 -q quieten some warnings\n"));
8223#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8224 fprintf (stream, _("\
a38cf1db 8225 -s ignored\n"));
b3b91714 8226#endif
751d281c
L		 8227#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8228 fprintf (stream, _("\
8229 --32/--64 generate 32bit/64bit code\n"));
8230#endif
b3b91714
AM		 8231#ifdef SVR4_COMMENT_CHARS
8232 fprintf (stream, _("\
8233 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8234#else
8235 fprintf (stream, _("\
b3b91714 8236 --divide ignored\n"));
4cc782b5 8237#endif
9103f4f4 8238 fprintf (stream, _("\
6305a203
L		 8239 -march=CPU[,+EXTENSION...]\n\
8240 generate code for CPU and EXTENSION, CPU is one of:\n\
2cb4f3d5
L		 8241 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8242 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
bd5295b2 8243 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
2cb4f3d5 8244 generic32, generic64\n\
599121aa
L		 8245 EXTENSION is combination of:\n\
8246 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
f1f8f695 8247 avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
bd5295b2
L		 8248 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
8249 sse5, svme, abm, padlock\n"));
6305a203 8250 fprintf (stream, _("\
2cb4f3d5
L		 8251 -mtune=CPU optimize for CPU, CPU is one of:\n\
8252 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8253 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
bd5295b2 8254 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
2cb4f3d5 8255 generic32, generic64\n"));
ba104c83 8256 fprintf (stream, _("\
c0f3af97
L		 8257 -msse2avx encode SSE instructions with VEX prefix\n"));
8258 fprintf (stream, _("\
daf50ae7
L		 8259 -msse-check=[none|error|warning]\n\
8260 check SSE instructions\n"));
8261 fprintf (stream, _("\
ba104c83
L		 8262 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8263 fprintf (stream, _("\
8264 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8265 fprintf (stream, _("\
8266 -mindex-reg support pseudo index registers\n"));
8267 fprintf (stream, _("\
8268 -mnaked-reg don't require `%%' prefix for registers\n"));
8269 fprintf (stream, _("\
8270 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8271}
8272
3e73aa7c 8273#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 8274 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH		 8275
8276/* Pick the target format to use. */
8277
47926f60 8278const char *
e3bb37b5 8279i386_target_format (void)
252b5132 8280{
3e73aa7c 8281 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 8282 {
8283 set_code_flag (CODE_64BIT);
0dfbf9d7 8284 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8285 {
8286 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8287 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8288 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8289 cpu_arch_isa_flags.bitfield.cpui486 = 1;
8290 cpu_arch_isa_flags.bitfield.cpui586 = 1;
8291 cpu_arch_isa_flags.bitfield.cpui686 = 1;
bd5295b2 8292 cpu_arch_isa_flags.bitfield.cpuclflush = 1;
40fb9820 8293 cpu_arch_isa_flags.bitfield.cpummx= 1;
40fb9820
L		 8294 cpu_arch_isa_flags.bitfield.cpusse = 1;
8295 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
8296 }
0dfbf9d7 8297 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8298 {
8299 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8300 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8301 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8302 cpu_arch_tune_flags.bitfield.cpui486 = 1;
8303 cpu_arch_tune_flags.bitfield.cpui586 = 1;
8304 cpu_arch_tune_flags.bitfield.cpui686 = 1;
bd5295b2 8305 cpu_arch_tune_flags.bitfield.cpuclflush = 1;
40fb9820 8306 cpu_arch_tune_flags.bitfield.cpummx= 1;
40fb9820
L		 8307 cpu_arch_tune_flags.bitfield.cpusse = 1;
8308 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
8309 }
9103f4f4 8310 }
3e73aa7c 8311 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 8312 {
8313 set_code_flag (CODE_32BIT);
0dfbf9d7 8314 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8315 {
8316 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8317 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8318 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8319 }
0dfbf9d7 8320 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8321 {
8322 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8323 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8324 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8325 }
9103f4f4 8326 }
3e73aa7c
JH		 8327 else
8328 as_fatal (_("Unknown architecture"));
252b5132
RH		 8329 switch (OUTPUT_FLAVOR)
8330 {
872ce6ff
L		 8331#ifdef TE_PEP
8332 case bfd_target_coff_flavour:
b01ee69d 8333 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "pe-i386";
872ce6ff
L		 8334 break;
8335#endif
4c63da97
AM		 8336#ifdef OBJ_MAYBE_AOUT
8337 case bfd_target_aout_flavour:
47926f60 8338 return AOUT_TARGET_FORMAT;
4c63da97
AM		 8339#endif
8340#ifdef OBJ_MAYBE_COFF
252b5132
RH		 8341 case bfd_target_coff_flavour:
8342 return "coff-i386";
4c63da97 8343#endif
3e73aa7c 8344#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8345 case bfd_target_elf_flavour:
3e73aa7c 8346 {
e5cb08ac 8347 if (flag_code == CODE_64BIT)
4fa24527
JB		 8348 {
8349 object_64bit = 1;
8350 use_rela_relocations = 1;
8351 }
9d7cbccd 8352 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 8353 }
4c63da97 8354#endif
252b5132
RH		 8355 default:
8356 abort ();
8357 return NULL;
8358 }
8359}
8360
47926f60 8361#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8362
8363#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8364void
8365i386_elf_emit_arch_note (void)
a847613f 8366{
718ddfc0 8367 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8368 {
8369 char *p;
8370 asection *seg = now_seg;
8371 subsegT subseg = now_subseg;
8372 Elf_Internal_Note i_note;
8373 Elf_External_Note e_note;
8374 asection *note_secp;
8375 int len;
8376
8377 /* Create the .note section. */
8378 note_secp = subseg_new (".note", 0);
8379 bfd_set_section_flags (stdoutput,
8380 note_secp,
8381 SEC_HAS_CONTENTS | SEC_READONLY);
8382
8383 /* Process the arch string. */
8384 len = strlen (cpu_arch_name);
8385
8386 i_note.namesz = len + 1;
8387 i_note.descsz = 0;
8388 i_note.type = NT_ARCH;
8389 p = frag_more (sizeof (e_note.namesz));
8390 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8391 p = frag_more (sizeof (e_note.descsz));
8392 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8393 p = frag_more (sizeof (e_note.type));
8394 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8395 p = frag_more (len + 1);
8396 strcpy (p, cpu_arch_name);
8397
8398 frag_align (2, 0, 0);
8399
8400 subseg_set (seg, subseg);
8401 }
8402}
8403#endif
252b5132 8404\f
252b5132
RH		 8405symbolS *
8406md_undefined_symbol (name)
8407 char *name;
8408{
18dc2407
ILT		 8409 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8410 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8411 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8412 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8413 {
8414 if (!GOT_symbol)
8415 {
8416 if (symbol_find (name))
8417 as_bad (_("GOT already in symbol table"));
8418 GOT_symbol = symbol_new (name, undefined_section,
8419 (valueT) 0, &zero_address_frag);
8420 };
8421 return GOT_symbol;
8422 }
252b5132
RH		 8423 return 0;
8424}
8425
8426/* Round up a section size to the appropriate boundary. */
47926f60 8427
252b5132
RH		 8428valueT
8429md_section_align (segment, size)
ab9da554 8430 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8431 valueT size;
8432{
4c63da97
AM		 8433#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8434 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8435 {
8436 /* For a.out, force the section size to be aligned. If we don't do
8437 this, BFD will align it for us, but it will not write out the
8438 final bytes of the section. This may be a bug in BFD, but it is
8439 easier to fix it here since that is how the other a.out targets
8440 work. */
8441 int align;
8442
8443 align = bfd_get_section_alignment (stdoutput, segment);
8444 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8445 }
252b5132
RH		 8446#endif
8447
8448 return size;
8449}
8450
8451/* On the i386, PC-relative offsets are relative to the start of the
8452 next instruction. That is, the address of the offset, plus its
8453 size, since the offset is always the last part of the insn. */
8454
8455long
e3bb37b5 8456md_pcrel_from (fixS *fixP)
252b5132
RH		 8457{
8458 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8459}
8460
8461#ifndef I386COFF
8462
8463static void
e3bb37b5 8464s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8465{
29b0f896 8466 int temp;
252b5132 8467
8a75718c
JB		 8468#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8469 if (IS_ELF)
8470 obj_elf_section_change_hook ();
8471#endif
252b5132
RH		 8472 temp = get_absolute_expression ();
8473 subseg_set (bss_section, (subsegT) temp);
8474 demand_empty_rest_of_line ();
8475}
8476
8477#endif
8478
252b5132 8479void
e3bb37b5 8480i386_validate_fix (fixS *fixp)
252b5132
RH		 8481{
8482 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8483 {
23df1078
JH		 8484 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8485 {
4fa24527 8486 if (!object_64bit)
23df1078
JH		 8487 abort ();
8488 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8489 }
8490 else
8491 {
4fa24527 8492 if (!object_64bit)
d6ab8113
JB		 8493 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8494 else
8495 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8496 }
252b5132
RH		 8497 fixp->fx_subsy = 0;
8498 }
8499}
8500
252b5132
RH		 8501arelent *
8502tc_gen_reloc (section, fixp)
ab9da554 8503 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8504 fixS *fixp;
8505{
8506 arelent *rel;
8507 bfd_reloc_code_real_type code;
8508
8509 switch (fixp->fx_r_type)
8510 {
3e73aa7c
JH		 8511 case BFD_RELOC_X86_64_PLT32:
8512 case BFD_RELOC_X86_64_GOT32:
8513 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8514 case BFD_RELOC_386_PLT32:
8515 case BFD_RELOC_386_GOT32:
8516 case BFD_RELOC_386_GOTOFF:
8517 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8518 case BFD_RELOC_386_TLS_GD:
8519 case BFD_RELOC_386_TLS_LDM:
8520 case BFD_RELOC_386_TLS_LDO_32:
8521 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8522 case BFD_RELOC_386_TLS_IE:
8523 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8524 case BFD_RELOC_386_TLS_LE_32:
8525 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8526 case BFD_RELOC_386_TLS_GOTDESC:
8527 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8528 case BFD_RELOC_X86_64_TLSGD:
8529 case BFD_RELOC_X86_64_TLSLD:
8530 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8531 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8532 case BFD_RELOC_X86_64_GOTTPOFF:
8533 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8534 case BFD_RELOC_X86_64_TPOFF64:
8535 case BFD_RELOC_X86_64_GOTOFF64:
8536 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8537 case BFD_RELOC_X86_64_GOT64:
8538 case BFD_RELOC_X86_64_GOTPCREL64:
8539 case BFD_RELOC_X86_64_GOTPC64:
8540 case BFD_RELOC_X86_64_GOTPLT64:
8541 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8542 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8543 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8544 case BFD_RELOC_RVA:
8545 case BFD_RELOC_VTABLE_ENTRY:
8546 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8547#ifdef TE_PE
8548 case BFD_RELOC_32_SECREL:
8549#endif
252b5132
RH		 8550 code = fixp->fx_r_type;
8551 break;
dbbaec26
L		 8552 case BFD_RELOC_X86_64_32S:
8553 if (!fixp->fx_pcrel)
8554 {
8555 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8556 code = fixp->fx_r_type;
8557 break;
8558 }
252b5132 8559 default:
93382f6d 8560 if (fixp->fx_pcrel)
252b5132 8561 {
93382f6d
AM		 8562 switch (fixp->fx_size)
8563 {
8564 default:
b091f402
AM		 8565 as_bad_where (fixp->fx_file, fixp->fx_line,
8566 _("can not do %d byte pc-relative relocation"),
8567 fixp->fx_size);
93382f6d
AM		 8568 code = BFD_RELOC_32_PCREL;
8569 break;
8570 case 1: code = BFD_RELOC_8_PCREL; break;
8571 case 2: code = BFD_RELOC_16_PCREL; break;
8572 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8573#ifdef BFD64
8574 case 8: code = BFD_RELOC_64_PCREL; break;
8575#endif
93382f6d
AM		 8576 }
8577 }
8578 else
8579 {
8580 switch (fixp->fx_size)
8581 {
8582 default:
b091f402
AM		 8583 as_bad_where (fixp->fx_file, fixp->fx_line,
8584 _("can not do %d byte relocation"),
8585 fixp->fx_size);
93382f6d
AM		 8586 code = BFD_RELOC_32;
8587 break;
8588 case 1: code = BFD_RELOC_8; break;
8589 case 2: code = BFD_RELOC_16; break;
8590 case 4: code = BFD_RELOC_32; break;
937149dd 8591#ifdef BFD64
3e73aa7c 8592 case 8: code = BFD_RELOC_64; break;
937149dd 8593#endif
93382f6d 8594 }
252b5132
RH		 8595 }
8596 break;
8597 }
252b5132 8598
d182319b
JB		 8599 if ((code == BFD_RELOC_32
8600 || code == BFD_RELOC_32_PCREL
8601 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8602 && GOT_symbol
8603 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8604 {
4fa24527 8605 if (!object_64bit)
d6ab8113
JB		 8606 code = BFD_RELOC_386_GOTPC;
8607 else
8608 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8609 }
7b81dfbb
AJ		 8610 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8611 && GOT_symbol
8612 && fixp->fx_addsy == GOT_symbol)
8613 {
8614 code = BFD_RELOC_X86_64_GOTPC64;
8615 }
252b5132
RH		 8616
8617 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8618 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8619 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8620
8621 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8622
3e73aa7c
JH		 8623 if (!use_rela_relocations)
8624 {
8625 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8626 vtable entry to be used in the relocation's section offset. */
8627 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8628 rel->address = fixp->fx_offset;
252b5132 8629
c6682705 8630 rel->addend = 0;
3e73aa7c
JH		 8631 }
8632 /* Use the rela in 64bit mode. */
252b5132 8633 else
3e73aa7c 8634 {
062cd5e7
AS		 8635 if (!fixp->fx_pcrel)
8636 rel->addend = fixp->fx_offset;
8637 else
8638 switch (code)
8639 {
8640 case BFD_RELOC_X86_64_PLT32:
8641 case BFD_RELOC_X86_64_GOT32:
8642 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8643 case BFD_RELOC_X86_64_TLSGD:
8644 case BFD_RELOC_X86_64_TLSLD:
8645 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8646 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8647 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8648 rel->addend = fixp->fx_offset - fixp->fx_size;
8649 break;
8650 default:
8651 rel->addend = (section->vma
8652 - fixp->fx_size
8653 + fixp->fx_addnumber
8654 + md_pcrel_from (fixp));
8655 break;
8656 }
3e73aa7c
JH		 8657 }
8658
252b5132
RH		 8659 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8660 if (rel->howto == NULL)
8661 {
8662 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8663 _("cannot represent relocation type %s"),
252b5132
RH		 8664 bfd_get_reloc_code_name (code));
8665 /* Set howto to a garbage value so that we can keep going. */
8666 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
8667 assert (rel->howto != NULL);
8668 }
8669
8670 return rel;
8671}
8672
64a0c779
DN		 8673\f
8674/* Parse operands using Intel syntax. This implements a recursive descent
8675 parser based on the BNF grammar published in Appendix B of the MASM 6.1
8676 Programmer's Guide.
8677
8678 FIXME: We do not recognize the full operand grammar defined in the MASM
8679 documentation. In particular, all the structure/union and
8680 high-level macro operands are missing.
8681
8682 Uppercase words are terminals, lower case words are non-terminals.
8683 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
8684 bars '|' denote choices. Most grammar productions are implemented in
8685 functions called 'intel_<production>'.
8686
8687 Initial production is 'expr'.
8688
9306ca4a 8689 addOp + | -
64a0c779
DN		 8690
8691 alpha [a-zA-Z]
8692
9306ca4a
JB		 8693 binOp & | AND | \| | OR | ^ | XOR
8694
64a0c779
DN		 8695 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
8696
8697 constant digits [[ radixOverride ]]
8698
c0f3af97 8699 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD | YMMWORD
64a0c779
DN		 8700
8701 digits decdigit
b77a7acd
AJ		 8702 | digits decdigit
8703 | digits hexdigit
64a0c779
DN		 8704
8705 decdigit [0-9]
8706
9306ca4a
JB		 8707 e04 e04 addOp e05
8708 | e05
8709
8710 e05 e05 binOp e06
b77a7acd 8711 | e06
64a0c779
DN		 8712
8713 e06 e06 mulOp e09
b77a7acd 8714 | e09
64a0c779
DN		 8715
8716 e09 OFFSET e10
a724f0f4
JB		 8717 | SHORT e10
8718 | + e10
8719 | - e10
9306ca4a
JB		 8720 | ~ e10
8721 | NOT e10
64a0c779
DN		 8722 | e09 PTR e10
8723 | e09 : e10
8724 | e10
8725
8726 e10 e10 [ expr ]
b77a7acd 8727 | e11
64a0c779
DN		 8728
8729 e11 ( expr )
b77a7acd 8730 | [ expr ]
64a0c779
DN		 8731 | constant
8732 | dataType
8733 | id
8734 | $
8735 | register
8736
a724f0f4 8737 => expr expr cmpOp e04
9306ca4a 8738 | e04
64a0c779
DN		 8739
8740 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 8741 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 8742
8743 hexdigit a | b | c | d | e | f
b77a7acd 8744 | A | B | C | D | E | F
64a0c779
DN		 8745
8746 id alpha
b77a7acd 8747 | id alpha
64a0c779
DN		 8748 | id decdigit
8749
9306ca4a 8750 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 8751
8752 quote " | '
8753
8754 register specialRegister
b77a7acd 8755 | gpRegister
64a0c779
DN		 8756 | byteRegister
8757
8758 segmentRegister CS | DS | ES | FS | GS | SS
8759
9306ca4a 8760 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 8761 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 8762 | TR3 | TR4 | TR5 | TR6 | TR7
8763
64a0c779
DN		 8764 We simplify the grammar in obvious places (e.g., register parsing is
8765 done by calling parse_register) and eliminate immediate left recursion
8766 to implement a recursive-descent parser.
8767
a724f0f4
JB		 8768 expr e04 expr'
8769
8770 expr' cmpOp e04 expr'
8771 | Empty
9306ca4a
JB		 8772
8773 e04 e05 e04'
8774
8775 e04' addOp e05 e04'
8776 | Empty
64a0c779
DN		 8777
8778 e05 e06 e05'
8779
9306ca4a 8780 e05' binOp e06 e05'
b77a7acd 8781 | Empty
64a0c779
DN		 8782
8783 e06 e09 e06'
8784
8785 e06' mulOp e09 e06'
b77a7acd 8786 | Empty
64a0c779
DN		 8787
8788 e09 OFFSET e10 e09'
a724f0f4
JB		 8789 | SHORT e10'
8790 | + e10'
8791 | - e10'
8792 | ~ e10'
8793 | NOT e10'
b77a7acd 8794 | e10 e09'
64a0c779
DN		 8795
8796 e09' PTR e10 e09'
b77a7acd 8797 | : e10 e09'
64a0c779
DN		 8798 | Empty
8799
8800 e10 e11 e10'
8801
8802 e10' [ expr ] e10'
b77a7acd 8803 | Empty
64a0c779
DN		 8804
8805 e11 ( expr )
b77a7acd 8806 | [ expr ]
64a0c779
DN		 8807 | BYTE
8808 | WORD
8809 | DWORD
9306ca4a 8810 | FWORD
64a0c779 8811 | QWORD
9306ca4a
JB		 8812 | TBYTE
8813 | OWORD
8814 | XMMWORD
c0f3af97 8815 | YMMWORD
64a0c779
DN		 8816 | .
8817 | $
8818 | register
8819 | id
8820 | constant */
8821
8822/* Parsing structure for the intel syntax parser. Used to implement the
8823 semantic actions for the operand grammar. */
8824struct intel_parser_s
8825 {
8826 char *op_string; /* The string being parsed. */
8827 int got_a_float; /* Whether the operand is a float. */
4a1805b1 8828 int op_modifier; /* Operand modifier. */
64a0c779 8829 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 8830 int in_offset; /* >=1 if parsing operand of offset. */
8831 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 8832 const reg_entry *reg; /* Last register reference found. */
8833 char *disp; /* Displacement string being built. */
a724f0f4 8834 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 8835 };
8836
8837static struct intel_parser_s intel_parser;
8838
8839/* Token structure for parsing intel syntax. */
8840struct intel_token
8841 {
8842 int code; /* Token code. */
8843 const reg_entry *reg; /* Register entry for register tokens. */
8844 char *str; /* String representation. */
8845 };
8846
8847static struct intel_token cur_token, prev_token;
8848
50705ef4
AM		 8849/* Token codes for the intel parser. Since T_SHORT is already used
8850 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 8851#define T_NIL -1
8852#define T_CONST 1
8853#define T_REG 2
8854#define T_BYTE 3
8855#define T_WORD 4
9306ca4a
JB		 8856#define T_DWORD 5
8857#define T_FWORD 6
8858#define T_QWORD 7
8859#define T_TBYTE 8
8860#define T_XMMWORD 9
50705ef4 8861#undef T_SHORT
9306ca4a
JB		 8862#define T_SHORT 10
8863#define T_OFFSET 11
8864#define T_PTR 12
8865#define T_ID 13
8866#define T_SHL 14
8867#define T_SHR 15
c0f3af97 8868#define T_YMMWORD 16
64a0c779
DN		 8869
8870/* Prototypes for intel parser functions. */
e3bb37b5
L		 8871static int intel_match_token (int);
8872static void intel_putback_token (void);
8873static void intel_get_token (void);
8874static int intel_expr (void);
8875static int intel_e04 (void);
8876static int intel_e05 (void);
8877static int intel_e06 (void);
8878static int intel_e09 (void);
8879static int intel_e10 (void);
8880static int intel_e11 (void);
64a0c779 8881
64a0c779 8882static int
e3bb37b5 8883i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 8884{
8885 int ret;
8886 char *p;
fc0763e6
JB		 8887 const reg_entry *final_base = i.base_reg;
8888 const reg_entry *final_index = i.index_reg;
64a0c779 8889
a724f0f4
JB		 8890 p = intel_parser.op_string = xstrdup (operand_string);
8891 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
8892
8893 for (;;)
64a0c779 8894 {
a724f0f4
JB		 8895 /* Initialize token holders. */
8896 cur_token.code = prev_token.code = T_NIL;
8897 cur_token.reg = prev_token.reg = NULL;
8898 cur_token.str = prev_token.str = NULL;
8899
8900 /* Initialize parser structure. */
8901 intel_parser.got_a_float = got_a_float;
8902 intel_parser.op_modifier = 0;
8903 intel_parser.is_mem = 0;
8904 intel_parser.in_offset = 0;
8905 intel_parser.in_bracket = 0;
8906 intel_parser.reg = NULL;
8907 intel_parser.disp[0] = '\0';
8908 intel_parser.next_operand = NULL;
8909
fc0763e6
JB		 8910 i.base_reg = NULL;
8911 i.index_reg = NULL;
8912
a724f0f4
JB		 8913 /* Read the first token and start the parser. */
8914 intel_get_token ();
8915 ret = intel_expr ();
8916
8917 if (!ret)
8918 break;
8919
9306ca4a
JB		 8920 if (cur_token.code != T_NIL)
8921 {
8922 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8923 current_templates->start->name, cur_token.str);
8924 ret = 0;
8925 }
64a0c779
DN		 8926 /* If we found a memory reference, hand it over to i386_displacement
8927 to fill in the rest of the operand fields. */
9306ca4a 8928 else if (intel_parser.is_mem)
64a0c779
DN		 8929 {
8930 if ((i.mem_operands == 1
40fb9820 8931 && !current_templates->start->opcode_modifier.isstring)
64a0c779
DN		 8932 || i.mem_operands == 2)
8933 {
8934 as_bad (_("too many memory references for '%s'"),
8935 current_templates->start->name);
8936 ret = 0;
8937 }
8938 else
8939 {
8940 char *s = intel_parser.disp;
64a0c779 8941
a724f0f4
JB		 8942 if (!quiet_warnings && intel_parser.is_mem < 0)
8943 /* See the comments in intel_bracket_expr. */
8944 as_warn (_("Treating `%s' as memory reference"), operand_string);
8945
64a0c779
DN		 8946 /* Add the displacement expression. */
8947 if (*s != '\0')
a4622f40
AM		 8948 ret = i386_displacement (s, s + strlen (s));
8949 if (ret)
a724f0f4
JB		 8950 {
8951 /* Swap base and index in 16-bit memory operands like
8952 [si+bx]. Since i386_index_check is also used in AT&T
8953 mode we have to do that here. */
8954 if (i.base_reg
8955 && i.index_reg
40fb9820
L		 8956 && i.base_reg->reg_type.bitfield.reg16
8957 && i.index_reg->reg_type.bitfield.reg16
a724f0f4
JB		 8958 && i.base_reg->reg_num >= 6
8959 && i.index_reg->reg_num < 6)
8960 {
8961 const reg_entry *base = i.index_reg;
8962
8963 i.index_reg = i.base_reg;
8964 i.base_reg = base;
8965 }
8966 ret = i386_index_check (operand_string);
8967 }
fc0763e6
JB		 8968 if (ret)
8969 {
8970 i.types[this_operand].bitfield.mem = 1;
8971 i.mem_operands++;
8972 }
64a0c779
DN		 8973 }
8974 }
8975
8976 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 8977 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779 8978 || intel_parser.reg == NULL)
b7240065
JB		 8979 {
8980 if (i.mem_operands < 2 && i.seg[i.mem_operands])
8981 {
8982 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8983 as_warn (_("Segment override ignored"));
8984 i.seg[i.mem_operands] = NULL;
8985 }
8986 ret = i386_immediate (intel_parser.disp);
8987 }
a724f0f4 8988
fc0763e6
JB		 8989 if (!final_base && !final_index)
8990 {
8991 final_base = i.base_reg;
8992 final_index = i.index_reg;
8993 }
8994
a724f0f4 8995 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 8996 ret = 0;
a724f0f4
JB		 8997 if (!ret || !intel_parser.next_operand)
8998 break;
8999 intel_parser.op_string = intel_parser.next_operand;
9000 this_operand = i.operands++;
7d5e4556 9001 i.types[this_operand].bitfield.unspecified = 1;
64a0c779
DN		 9002 }
9003
9004 free (p);
9005 free (intel_parser.disp);
9006
fc0763e6
JB		 9007 if (final_base || final_index)
9008 {
9009 i.base_reg = final_base;
9010 i.index_reg = final_index;
9011 }
9012
64a0c779
DN		 9013 return ret;
9014}
9015
a724f0f4
JB		 9016#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
9017
9018/* expr e04 expr'
9019
9020 expr' cmpOp e04 expr'
9021 | Empty */
64a0c779 9022static int
e3bb37b5 9023intel_expr (void)
64a0c779 9024{
a724f0f4
JB		 9025 /* XXX Implement the comparison operators. */
9026 return intel_e04 ();
9306ca4a
JB		 9027}
9028
a724f0f4 9029/* e04 e05 e04'
9306ca4a 9030
a724f0f4 9031 e04' addOp e05 e04'
9306ca4a
JB		 9032 | Empty */
9033static int
e3bb37b5 9034intel_e04 (void)
9306ca4a 9035{
a724f0f4 9036 int nregs = -1;
9306ca4a 9037
a724f0f4 9038 for (;;)
9306ca4a 9039 {
a724f0f4
JB		 9040 if (!intel_e05())
9041 return 0;
9306ca4a 9042
a724f0f4
JB		 9043 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9044 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 9045
a724f0f4
JB		 9046 if (cur_token.code == '+')
9047 nregs = -1;
9048 else if (cur_token.code == '-')
9049 nregs = NUM_ADDRESS_REGS;
9050 else
9051 return 1;
64a0c779 9052
a724f0f4
JB		 9053 strcat (intel_parser.disp, cur_token.str);
9054 intel_match_token (cur_token.code);
9055 }
64a0c779
DN		 9056}
9057
64a0c779
DN		 9058/* e05 e06 e05'
9059
9306ca4a 9060 e05' binOp e06 e05'
64a0c779
DN		 9061 | Empty */
9062static int
e3bb37b5 9063intel_e05 (void)
64a0c779 9064{
a724f0f4 9065 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 9066
a724f0f4 9067 for (;;)
64a0c779 9068 {
a724f0f4
JB		 9069 if (!intel_e06())
9070 return 0;
9071
4eed87de
AM		 9072 if (cur_token.code == '&'
9073 || cur_token.code == '|'
9074 || cur_token.code == '^')
a724f0f4
JB		 9075 {
9076 char str[2];
9077
9078 str[0] = cur_token.code;
9079 str[1] = 0;
9080 strcat (intel_parser.disp, str);
9081 }
9082 else
9083 break;
9306ca4a 9084
64a0c779
DN		 9085 intel_match_token (cur_token.code);
9086
a724f0f4
JB		 9087 if (nregs < 0)
9088 nregs = ~nregs;
64a0c779 9089 }
a724f0f4
JB		 9090 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9091 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
9092 return 1;
4a1805b1 9093}
64a0c779
DN		 9094
9095/* e06 e09 e06'
9096
9097 e06' mulOp e09 e06'
b77a7acd 9098 | Empty */
64a0c779 9099static int
e3bb37b5 9100intel_e06 (void)
64a0c779 9101{
a724f0f4 9102 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 9103
a724f0f4 9104 for (;;)
64a0c779 9105 {
a724f0f4
JB		 9106 if (!intel_e09())
9107 return 0;
9306ca4a 9108
4eed87de
AM		 9109 if (cur_token.code == '*'
9110 || cur_token.code == '/'
9111 || cur_token.code == '%')
a724f0f4
JB		 9112 {
9113 char str[2];
9306ca4a 9114
a724f0f4
JB		 9115 str[0] = cur_token.code;
9116 str[1] = 0;
9117 strcat (intel_parser.disp, str);
9118 }
9119 else if (cur_token.code == T_SHL)
9120 strcat (intel_parser.disp, "<<");
9121 else if (cur_token.code == T_SHR)
9122 strcat (intel_parser.disp, ">>");
9123 else
9124 break;
9306ca4a 9125
64e74474 9126 intel_match_token (cur_token.code);
64a0c779 9127
a724f0f4
JB		 9128 if (nregs < 0)
9129 nregs = ~nregs;
64a0c779 9130 }
a724f0f4
JB		 9131 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9132 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
9133 return 1;
64a0c779
DN		 9134}
9135
a724f0f4
JB		 9136/* e09 OFFSET e09
9137 | SHORT e09
9138 | + e09
9139 | - e09
9140 | ~ e09
9141 | NOT e09
9306ca4a
JB		 9142 | e10 e09'
9143
64a0c779 9144 e09' PTR e10 e09'
b77a7acd 9145 | : e10 e09'
64a0c779
DN		 9146 | Empty */
9147static int
e3bb37b5 9148intel_e09 (void)
64a0c779 9149{
a724f0f4
JB		 9150 int nregs = ~NUM_ADDRESS_REGS;
9151 int in_offset = 0;
9152
9153 for (;;)
64a0c779 9154 {
a724f0f4
JB		 9155 /* Don't consume constants here. */
9156 if (cur_token.code == '+' || cur_token.code == '-')
9157 {
9158 /* Need to look one token ahead - if the next token
9159 is a constant, the current token is its sign. */
9160 int next_code;
9161
9162 intel_match_token (cur_token.code);
9163 next_code = cur_token.code;
9164 intel_putback_token ();
9165 if (next_code == T_CONST)
9166 break;
9167 }
9168
9169 /* e09 OFFSET e09 */
9170 if (cur_token.code == T_OFFSET)
9171 {
9172 if (!in_offset++)
9173 ++intel_parser.in_offset;
9174 }
9175
9176 /* e09 SHORT e09 */
9177 else if (cur_token.code == T_SHORT)
9178 intel_parser.op_modifier |= 1 << T_SHORT;
9179
9180 /* e09 + e09 */
9181 else if (cur_token.code == '+')
9182 strcat (intel_parser.disp, "+");
9183
9184 /* e09 - e09
9185 | ~ e09
9186 | NOT e09 */
9187 else if (cur_token.code == '-' || cur_token.code == '~')
9188 {
9189 char str[2];
64a0c779 9190
a724f0f4
JB		 9191 if (nregs < 0)
9192 nregs = ~nregs;
9193 str[0] = cur_token.code;
9194 str[1] = 0;
9195 strcat (intel_parser.disp, str);
9196 }
9197
9198 /* e09 e10 e09' */
9199 else
9200 break;
9201
9202 intel_match_token (cur_token.code);
64a0c779
DN		 9203 }
9204
a724f0f4 9205 for (;;)
9306ca4a 9206 {
a724f0f4
JB		 9207 if (!intel_e10 ())
9208 return 0;
9306ca4a 9209
a724f0f4
JB		 9210 /* e09' PTR e10 e09' */
9211 if (cur_token.code == T_PTR)
9212 {
9213 char suffix;
9306ca4a 9214
a724f0f4 9215 if (prev_token.code == T_BYTE)
7d5e4556
L		 9216 {
9217 suffix = BYTE_MNEM_SUFFIX;
9218 i.types[this_operand].bitfield.byte = 1;
9219 }
9306ca4a 9220
a724f0f4
JB		 9221 else if (prev_token.code == T_WORD)
9222 {
34b772a6
JB		 9223 if ((current_templates->start->name[0] == 'l'
9224 && current_templates->start->name[2] == 's'
9225 && current_templates->start->name[3] == 0)
9226 || current_templates->start->base_opcode == 0x62 /* bound */)
a724f0f4
JB		 9227 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
9228 else if (intel_parser.got_a_float == 2) /* "fi..." */
9229 suffix = SHORT_MNEM_SUFFIX;
9230 else
9231 suffix = WORD_MNEM_SUFFIX;
7d5e4556 9232 i.types[this_operand].bitfield.word = 1;
a724f0f4 9233 }
64a0c779 9234
a724f0f4
JB		 9235 else if (prev_token.code == T_DWORD)
9236 {
34b772a6
JB		 9237 if ((current_templates->start->name[0] == 'l'
9238 && current_templates->start->name[2] == 's'
9239 && current_templates->start->name[3] == 0)
9240 || current_templates->start->base_opcode == 0x62 /* bound */)
a724f0f4
JB		 9241 suffix = WORD_MNEM_SUFFIX;
9242 else if (flag_code == CODE_16BIT
40fb9820
L		 9243 && (current_templates->start->opcode_modifier.jump
9244 || current_templates->start->opcode_modifier.jumpdword))
a724f0f4
JB		 9245 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9246 else if (intel_parser.got_a_float == 1) /* "f..." */
9247 suffix = SHORT_MNEM_SUFFIX;
9248 else
9249 suffix = LONG_MNEM_SUFFIX;
7d5e4556 9250 i.types[this_operand].bitfield.dword = 1;
a724f0f4 9251 }
9306ca4a 9252
a724f0f4
JB		 9253 else if (prev_token.code == T_FWORD)
9254 {
9255 if (current_templates->start->name[0] == 'l'
9256 && current_templates->start->name[2] == 's'
9257 && current_templates->start->name[3] == 0)
9258 suffix = LONG_MNEM_SUFFIX;
9259 else if (!intel_parser.got_a_float)
9260 {
9261 if (flag_code == CODE_16BIT)
9262 add_prefix (DATA_PREFIX_OPCODE);
9263 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9264 }
9265 else
9266 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7d5e4556 9267 i.types[this_operand].bitfield.fword = 1;
a724f0f4 9268 }
64a0c779 9269
a724f0f4
JB		 9270 else if (prev_token.code == T_QWORD)
9271 {
34b772a6
JB		 9272 if (current_templates->start->base_opcode == 0x62 /* bound */
9273 || intel_parser.got_a_float == 1) /* "f..." */
a724f0f4
JB		 9274 suffix = LONG_MNEM_SUFFIX;
9275 else
34b772a6 9276 suffix = QWORD_MNEM_SUFFIX;
7d5e4556 9277 i.types[this_operand].bitfield.qword = 1;
a724f0f4 9278 }
64a0c779 9279
a724f0f4
JB		 9280 else if (prev_token.code == T_TBYTE)
9281 {
9282 if (intel_parser.got_a_float == 1)
9283 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9284 else
9285 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
9286 }
9306ca4a 9287
a724f0f4 9288 else if (prev_token.code == T_XMMWORD)
9306ca4a 9289 {
582d5edd 9290 suffix = XMMWORD_MNEM_SUFFIX;
7d5e4556 9291 i.types[this_operand].bitfield.xmmword = 1;
9306ca4a 9292 }
64a0c779 9293
c0f3af97
L		 9294 else if (prev_token.code == T_YMMWORD)
9295 {
9296 suffix = YMMWORD_MNEM_SUFFIX;
9297 i.types[this_operand].bitfield.ymmword = 1;
9298 }
9299
f16b83df 9300 else
a724f0f4
JB		 9301 {
9302 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
9303 return 0;
9304 }
9305
7d5e4556
L		 9306 i.types[this_operand].bitfield.unspecified = 0;
9307
435acd52
JB		 9308 /* Operands for jump/call using 'ptr' notation denote absolute
9309 addresses. */
40fb9820
L		 9310 if (current_templates->start->opcode_modifier.jump
9311 || current_templates->start->opcode_modifier.jumpdword)
9312 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 9313
a724f0f4
JB		 9314 if (current_templates->start->base_opcode == 0x8d /* lea */)
9315 ;
9316 else if (!i.suffix)
9317 i.suffix = suffix;
9318 else if (i.suffix != suffix)
9319 {
9320 as_bad (_("Conflicting operand modifiers"));
9321 return 0;
9322 }
64a0c779 9323
9306ca4a
JB		 9324 }
9325
a724f0f4
JB		 9326 /* e09' : e10 e09' */
9327 else if (cur_token.code == ':')
9306ca4a 9328 {
a724f0f4
JB		 9329 if (prev_token.code != T_REG)
9330 {
9331 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
9332 segment/group identifier (which we don't have), using comma
9333 as the operand separator there is even less consistent, since
9334 there all branches only have a single operand. */
9335 if (this_operand != 0
9336 || intel_parser.in_offset
9337 || intel_parser.in_bracket
40fb9820
L		 9338 || (!current_templates->start->opcode_modifier.jump
9339 && !current_templates->start->opcode_modifier.jumpdword
9340 && !current_templates->start->opcode_modifier.jumpintersegment
9341 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
a724f0f4
JB		 9342 return intel_match_token (T_NIL);
9343 /* Remember the start of the 2nd operand and terminate 1st
9344 operand here.
9345 XXX This isn't right, yet (when SSSS:OOOO is right operand of
9346 another expression), but it gets at least the simplest case
9347 (a plain number or symbol on the left side) right. */
9348 intel_parser.next_operand = intel_parser.op_string;
9349 *--intel_parser.op_string = '\0';
9350 return intel_match_token (':');
9351 }
9306ca4a 9352 }
64a0c779 9353
a724f0f4 9354 /* e09' Empty */
64a0c779 9355 else
a724f0f4 9356 break;
64a0c779 9357
a724f0f4
JB		 9358 intel_match_token (cur_token.code);
9359
9360 }
9361
9362 if (in_offset)
9363 {
9364 --intel_parser.in_offset;
9365 if (nregs < 0)
9366 nregs = ~nregs;
9367 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 9368 {
a724f0f4 9369 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 9370 return 0;
9371 }
a724f0f4
JB		 9372 intel_parser.op_modifier |= 1 << T_OFFSET;
9373 }
9306ca4a 9374
a724f0f4
JB		 9375 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9376 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
9377 return 1;
9378}
64a0c779 9379
a724f0f4 9380static int
e3bb37b5 9381intel_bracket_expr (void)
a724f0f4
JB		 9382{
9383 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
9384 const char *start = intel_parser.op_string;
9385 int len;
9386
9387 if (i.op[this_operand].regs)
9388 return intel_match_token (T_NIL);
9389
9390 intel_match_token ('[');
9391
9392 /* Mark as a memory operand only if it's not already known to be an
9393 offset expression. If it's an offset expression, we need to keep
9394 the brace in. */
9395 if (!intel_parser.in_offset)
9396 {
9397 ++intel_parser.in_bracket;
435acd52
JB		 9398
9399 /* Operands for jump/call inside brackets denote absolute addresses. */
40fb9820
L		 9400 if (current_templates->start->opcode_modifier.jump
9401 || current_templates->start->opcode_modifier.jumpdword)
9402 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 9403
a724f0f4
JB		 9404 /* Unfortunately gas always diverged from MASM in a respect that can't
9405 be easily fixed without risking to break code sequences likely to be
9406 encountered (the testsuite even check for this): MASM doesn't consider
9407 an expression inside brackets unconditionally as a memory reference.
9408 When that is e.g. a constant, an offset expression, or the sum of the
9409 two, this is still taken as a constant load. gas, however, always
9410 treated these as memory references. As a compromise, we'll try to make
9411 offset expressions inside brackets work the MASM way (since that's
9412 less likely to be found in real world code), but make constants alone
9413 continue to work the traditional gas way. In either case, issue a
9414 warning. */
9415 intel_parser.op_modifier &= ~was_offset;
64a0c779 9416 }
a724f0f4 9417 else
64e74474 9418 strcat (intel_parser.disp, "[");
a724f0f4
JB		 9419
9420 /* Add a '+' to the displacement string if necessary. */
9421 if (*intel_parser.disp != '\0'
9422 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
9423 strcat (intel_parser.disp, "+");
64a0c779 9424
a724f0f4
JB		 9425 if (intel_expr ()
9426 && (len = intel_parser.op_string - start - 1,
9427 intel_match_token (']')))
64a0c779 9428 {
a724f0f4
JB		 9429 /* Preserve brackets when the operand is an offset expression. */
9430 if (intel_parser.in_offset)
9431 strcat (intel_parser.disp, "]");
9432 else
9433 {
9434 --intel_parser.in_bracket;
9435 if (i.base_reg || i.index_reg)
9436 intel_parser.is_mem = 1;
9437 if (!intel_parser.is_mem)
9438 {
9439 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
9440 /* Defer the warning until all of the operand was parsed. */
9441 intel_parser.is_mem = -1;
9442 else if (!quiet_warnings)
4eed87de
AM		 9443 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
9444 len, start, len, start);
a724f0f4
JB		 9445 }
9446 }
9447 intel_parser.op_modifier |= was_offset;
64a0c779 9448
a724f0f4 9449 return 1;
64a0c779 9450 }
a724f0f4 9451 return 0;
64a0c779
DN		 9452}
9453
9454/* e10 e11 e10'
9455
9456 e10' [ expr ] e10'
b77a7acd 9457 | Empty */
64a0c779 9458static int
e3bb37b5 9459intel_e10 (void)
64a0c779 9460{
a724f0f4
JB		 9461 if (!intel_e11 ())
9462 return 0;
64a0c779 9463
a724f0f4 9464 while (cur_token.code == '[')
64a0c779 9465 {
a724f0f4 9466 if (!intel_bracket_expr ())
21d6c4af 9467 return 0;
64a0c779
DN		 9468 }
9469
a724f0f4 9470 return 1;
64a0c779
DN		 9471}
9472
64a0c779 9473/* e11 ( expr )
b77a7acd 9474 | [ expr ]
64a0c779
DN		 9475 | BYTE
9476 | WORD
9477 | DWORD
9306ca4a 9478 | FWORD
64a0c779 9479 | QWORD
9306ca4a
JB		 9480 | TBYTE
9481 | OWORD
9482 | XMMWORD
c0f3af97 9483 | YMMWORD
4a1805b1 9484 | $
64a0c779
DN		 9485 | .
9486 | register
9487 | id
9488 | constant */
9489static int
e3bb37b5 9490intel_e11 (void)
64a0c779 9491{
a724f0f4 9492 switch (cur_token.code)
64a0c779 9493 {
a724f0f4
JB		 9494 /* e11 ( expr ) */
9495 case '(':
64a0c779
DN		 9496 intel_match_token ('(');
9497 strcat (intel_parser.disp, "(");
9498
9499 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 9500 {
9501 strcat (intel_parser.disp, ")");
9502 return 1;
9503 }
a724f0f4 9504 return 0;
4a1805b1 9505
a724f0f4
JB		 9506 /* e11 [ expr ] */
9507 case '[':
a724f0f4 9508 return intel_bracket_expr ();
64a0c779 9509
a724f0f4
JB		 9510 /* e11 $
9511 | . */
9512 case '.':
64a0c779
DN		 9513 strcat (intel_parser.disp, cur_token.str);
9514 intel_match_token (cur_token.code);
21d6c4af
DN		 9515
9516 /* Mark as a memory operand only if it's not already known to be an
9517 offset expression. */
a724f0f4 9518 if (!intel_parser.in_offset)
21d6c4af 9519 intel_parser.is_mem = 1;
64a0c779
DN		 9520
9521 return 1;
64a0c779 9522
a724f0f4
JB		 9523 /* e11 register */
9524 case T_REG:
9525 {
9526 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 9527
a724f0f4 9528 intel_match_token (T_REG);
64a0c779 9529
a724f0f4
JB		 9530 /* Check for segment change. */
9531 if (cur_token.code == ':')
9532 {
40fb9820
L		 9533 if (!reg->reg_type.bitfield.sreg2
9534 && !reg->reg_type.bitfield.sreg3)
a724f0f4 9535 {
4eed87de
AM		 9536 as_bad (_("`%s' is not a valid segment register"),
9537 reg->reg_name);
a724f0f4
JB		 9538 return 0;
9539 }
b7240065
JB		 9540 else if (i.mem_operands >= 2)
9541 as_warn (_("Segment override ignored"));
a724f0f4
JB		 9542 else if (i.seg[i.mem_operands])
9543 as_warn (_("Extra segment override ignored"));
9544 else
9545 {
9546 if (!intel_parser.in_offset)
9547 intel_parser.is_mem = 1;
9548 switch (reg->reg_num)
9549 {
9550 case 0:
9551 i.seg[i.mem_operands] = &es;
9552 break;
9553 case 1:
9554 i.seg[i.mem_operands] = &cs;
9555 break;
9556 case 2:
9557 i.seg[i.mem_operands] = &ss;
9558 break;
9559 case 3:
9560 i.seg[i.mem_operands] = &ds;
9561 break;
9562 case 4:
9563 i.seg[i.mem_operands] = &fs;
9564 break;
9565 case 5:
9566 i.seg[i.mem_operands] = &gs;
9567 break;
9568 }
9569 }
9570 }
64a0c779 9571
b7240065
JB		 9572 else if (reg->reg_type.bitfield.sreg3 && reg->reg_num == RegFlat)
9573 {
9574 as_bad (_("cannot use `FLAT' here"));
9575 return 0;
9576 }
9577
a724f0f4
JB		 9578 /* Not a segment register. Check for register scaling. */
9579 else if (cur_token.code == '*')
9580 {
9581 if (!intel_parser.in_bracket)
9582 {
9583 as_bad (_("Register scaling only allowed in memory operands"));
9584 return 0;
9585 }
64a0c779 9586
40fb9820 9587 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
a724f0f4
JB		 9588 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
9589 else if (i.index_reg)
9590 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 9591
a724f0f4
JB		 9592 /* What follows must be a valid scale. */
9593 intel_match_token ('*');
9594 i.index_reg = reg;
40fb9820 9595 i.types[this_operand].bitfield.baseindex = 1;
64a0c779 9596
a724f0f4
JB		 9597 /* Set the scale after setting the register (otherwise,
9598 i386_scale will complain) */
9599 if (cur_token.code == '+' || cur_token.code == '-')
9600 {
9601 char *str, sign = cur_token.code;
9602 intel_match_token (cur_token.code);
9603 if (cur_token.code != T_CONST)
9604 {
9605 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9606 cur_token.str);
9607 return 0;
9608 }
9609 str = (char *) xmalloc (strlen (cur_token.str) + 2);
9610 strcpy (str + 1, cur_token.str);
9611 *str = sign;
9612 if (!i386_scale (str))
9613 return 0;
9614 free (str);
9615 }
9616 else if (!i386_scale (cur_token.str))
64a0c779 9617 return 0;
a724f0f4
JB		 9618 intel_match_token (cur_token.code);
9619 }
64a0c779 9620
a724f0f4
JB		 9621 /* No scaling. If this is a memory operand, the register is either a
9622 base register (first occurrence) or an index register (second
9623 occurrence). */
7b0441f6 9624 else if (intel_parser.in_bracket)
a724f0f4 9625 {
64a0c779 9626
a724f0f4
JB		 9627 if (!i.base_reg)
9628 i.base_reg = reg;
9629 else if (!i.index_reg)
9630 i.index_reg = reg;
9631 else
9632 {
9633 as_bad (_("Too many register references in memory operand"));
9634 return 0;
9635 }
64a0c779 9636
40fb9820 9637 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4 9638 }
4a1805b1 9639
4d1bb795
JB		 9640 /* It's neither base nor index. */
9641 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4 9642 {
40fb9820
L		 9643 i386_operand_type temp = reg->reg_type;
9644 temp.bitfield.baseindex = 0;
c6fb90c8
L		 9645 i.types[this_operand] = operand_type_or (i.types[this_operand],
9646 temp);
7d5e4556 9647 i.types[this_operand].bitfield.unspecified = 0;
a724f0f4
JB		 9648 i.op[this_operand].regs = reg;
9649 i.reg_operands++;
9650 }
9651 else
9652 {
9653 as_bad (_("Invalid use of register"));
9654 return 0;
9655 }
64a0c779 9656
a724f0f4
JB		 9657 /* Since registers are not part of the displacement string (except
9658 when we're parsing offset operands), we may need to remove any
9659 preceding '+' from the displacement string. */
9660 if (*intel_parser.disp != '\0'
9661 && !intel_parser.in_offset)
9662 {
9663 char *s = intel_parser.disp;
9664 s += strlen (s) - 1;
9665 if (*s == '+')
9666 *s = '\0';
9667 }
4a1805b1 9668
a724f0f4
JB		 9669 return 1;
9670 }
9671
9672 /* e11 BYTE
9673 | WORD
9674 | DWORD
9675 | FWORD
9676 | QWORD
9677 | TBYTE
9678 | OWORD
c0f3af97
L		 9679 | XMMWORD
9680 | YMMWORD */
a724f0f4
JB		 9681 case T_BYTE:
9682 case T_WORD:
9683 case T_DWORD:
9684 case T_FWORD:
9685 case T_QWORD:
9686 case T_TBYTE:
9687 case T_XMMWORD:
c0f3af97 9688 case T_YMMWORD:
a724f0f4 9689 intel_match_token (cur_token.code);
64a0c779 9690
a724f0f4
JB		 9691 if (cur_token.code == T_PTR)
9692 return 1;
9693
9694 /* It must have been an identifier. */
9695 intel_putback_token ();
9696 cur_token.code = T_ID;
9697 /* FALLTHRU */
9698
9699 /* e11 id
9700 | constant */
9701 case T_ID:
9702 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 9703 {
9704 symbolS *symbolP;
9705
a724f0f4
JB		 9706 /* The identifier represents a memory reference only if it's not
9707 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 9708 symbolP = symbol_find(cur_token.str);
9709 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
9710 intel_parser.is_mem = 1;
9711 }
a724f0f4 9712 /* FALLTHRU */
64a0c779 9713
a724f0f4
JB		 9714 case T_CONST:
9715 case '-':
9716 case '+':
9717 {
9718 char *save_str, sign = 0;
64a0c779 9719
a724f0f4
JB		 9720 /* Allow constants that start with `+' or `-'. */
9721 if (cur_token.code == '-' || cur_token.code == '+')
9722 {
9723 sign = cur_token.code;
9724 intel_match_token (cur_token.code);
9725 if (cur_token.code != T_CONST)
9726 {
9727 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9728 cur_token.str);
9729 return 0;
9730 }
9731 }
64a0c779 9732
a724f0f4
JB		 9733 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
9734 strcpy (save_str + !!sign, cur_token.str);
9735 if (sign)
9736 *save_str = sign;
64a0c779 9737
a724f0f4
JB		 9738 /* Get the next token to check for register scaling. */
9739 intel_match_token (cur_token.code);
64a0c779 9740
4eed87de
AM		 9741 /* Check if this constant is a scaling factor for an
9742 index register. */
a724f0f4
JB		 9743 if (cur_token.code == '*')
9744 {
9745 if (intel_match_token ('*') && cur_token.code == T_REG)
9746 {
9747 const reg_entry *reg = cur_token.reg;
9748
9749 if (!intel_parser.in_bracket)
9750 {
4eed87de
AM		 9751 as_bad (_("Register scaling only allowed "
9752 "in memory operands"));
a724f0f4
JB		 9753 return 0;
9754 }
9755
4eed87de
AM		 9756 /* Disallow things like [1*si].
9757 sp and esp are invalid as index. */
40fb9820 9758 if (reg->reg_type.bitfield.reg16)
4eed87de 9759 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 9760 else if (i.index_reg)
4eed87de 9761 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 9762
9763 /* The constant is followed by `* reg', so it must be
9764 a valid scale. */
9765 i.index_reg = reg;
40fb9820 9766 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4
JB		 9767
9768 /* Set the scale after setting the register (otherwise,
9769 i386_scale will complain) */
9770 if (!i386_scale (save_str))
64a0c779 9771 return 0;
a724f0f4
JB		 9772 intel_match_token (T_REG);
9773
9774 /* Since registers are not part of the displacement
9775 string, we may need to remove any preceding '+' from
9776 the displacement string. */
9777 if (*intel_parser.disp != '\0')
9778 {
9779 char *s = intel_parser.disp;
9780 s += strlen (s) - 1;
9781 if (*s == '+')
9782 *s = '\0';
9783 }
9784
9785 free (save_str);
9786
9787 return 1;
9788 }
64a0c779 9789
a724f0f4
JB		 9790 /* The constant was not used for register scaling. Since we have
9791 already consumed the token following `*' we now need to put it
9792 back in the stream. */
64a0c779 9793 intel_putback_token ();
a724f0f4 9794 }
64a0c779 9795
a724f0f4
JB		 9796 /* Add the constant to the displacement string. */
9797 strcat (intel_parser.disp, save_str);
9798 free (save_str);
64a0c779 9799
a724f0f4
JB		 9800 return 1;
9801 }
64a0c779
DN		 9802 }
9803
64a0c779
DN		 9804 as_bad (_("Unrecognized token '%s'"), cur_token.str);
9805 return 0;
9806}
9807
64a0c779
DN		 9808/* Match the given token against cur_token. If they match, read the next
9809 token from the operand string. */
9810static int
e3bb37b5 9811intel_match_token (int code)
64a0c779
DN		 9812{
9813 if (cur_token.code == code)
9814 {
9815 intel_get_token ();
9816 return 1;
9817 }
9818 else
9819 {
0477af35 9820 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 9821 return 0;
9822 }
9823}
9824
64a0c779
DN		 9825/* Read a new token from intel_parser.op_string and store it in cur_token. */
9826static void
e3bb37b5 9827intel_get_token (void)
64a0c779
DN		 9828{
9829 char *end_op;
9830 const reg_entry *reg;
9831 struct intel_token new_token;
9832
9833 new_token.code = T_NIL;
9834 new_token.reg = NULL;
9835 new_token.str = NULL;
9836
4a1805b1 9837 /* Free the memory allocated to the previous token and move
64a0c779
DN		 9838 cur_token to prev_token. */
9839 if (prev_token.str)
9840 free (prev_token.str);
9841
9842 prev_token = cur_token;
9843
9844 /* Skip whitespace. */
9845 while (is_space_char (*intel_parser.op_string))
9846 intel_parser.op_string++;
9847
9848 /* Return an empty token if we find nothing else on the line. */
9849 if (*intel_parser.op_string == '\0')
9850 {
9851 cur_token = new_token;
9852 return;
9853 }
9854
9855 /* The new token cannot be larger than the remainder of the operand
9856 string. */
a724f0f4 9857 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 9858 new_token.str[0] = '\0';
9859
9860 if (strchr ("0123456789", *intel_parser.op_string))
9861 {
9862 char *p = new_token.str;
9863 char *q = intel_parser.op_string;
9864 new_token.code = T_CONST;
9865
9866 /* Allow any kind of identifier char to encompass floating point and
9867 hexadecimal numbers. */
9868 while (is_identifier_char (*q))
9869 *p++ = *q++;
9870 *p = '\0';
9871
9872 /* Recognize special symbol names [0-9][bf]. */
9873 if (strlen (intel_parser.op_string) == 2
4a1805b1 9874 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 9875 || intel_parser.op_string[1] == 'f'))
9876 new_token.code = T_ID;
9877 }
9878
4d1bb795 9879 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 9880 {
4d1bb795
JB		 9881 size_t len = end_op - intel_parser.op_string;
9882
64a0c779
DN		 9883 new_token.code = T_REG;
9884 new_token.reg = reg;
9885
4d1bb795
JB		 9886 memcpy (new_token.str, intel_parser.op_string, len);
9887 new_token.str[len] = '\0';
64a0c779
DN		 9888 }
9889
9890 else if (is_identifier_char (*intel_parser.op_string))
9891 {
9892 char *p = new_token.str;
9893 char *q = intel_parser.op_string;
9894
9895 /* A '.' or '$' followed by an identifier char is an identifier.
9896 Otherwise, it's operator '.' followed by an expression. */
9897 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
9898 {
9306ca4a
JB		 9899 new_token.code = '.';
9900 new_token.str[0] = '.';
64a0c779
DN		 9901 new_token.str[1] = '\0';
9902 }
9903 else
9904 {
9905 while (is_identifier_char (*q) || *q == '@')
9906 *p++ = *q++;
9907 *p = '\0';
9908
9306ca4a
JB		 9909 if (strcasecmp (new_token.str, "NOT") == 0)
9910 new_token.code = '~';
9911
9912 else if (strcasecmp (new_token.str, "MOD") == 0)
9913 new_token.code = '%';
9914
9915 else if (strcasecmp (new_token.str, "AND") == 0)
9916 new_token.code = '&';
9917
9918 else if (strcasecmp (new_token.str, "OR") == 0)
9919 new_token.code = '|';
9920
9921 else if (strcasecmp (new_token.str, "XOR") == 0)
9922 new_token.code = '^';
9923
9924 else if (strcasecmp (new_token.str, "SHL") == 0)
9925 new_token.code = T_SHL;
9926
9927 else if (strcasecmp (new_token.str, "SHR") == 0)
9928 new_token.code = T_SHR;
9929
9930 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 9931 new_token.code = T_BYTE;
9932
9933 else if (strcasecmp (new_token.str, "WORD") == 0)
9934 new_token.code = T_WORD;
9935
9936 else if (strcasecmp (new_token.str, "DWORD") == 0)
9937 new_token.code = T_DWORD;
9938
9306ca4a
JB		 9939 else if (strcasecmp (new_token.str, "FWORD") == 0)
9940 new_token.code = T_FWORD;
9941
64a0c779
DN		 9942 else if (strcasecmp (new_token.str, "QWORD") == 0)
9943 new_token.code = T_QWORD;
9944
9306ca4a
JB		 9945 else if (strcasecmp (new_token.str, "TBYTE") == 0
9946 /* XXX remove (gcc still uses it) */
9947 || strcasecmp (new_token.str, "XWORD") == 0)
9948 new_token.code = T_TBYTE;
9949
9950 else if (strcasecmp (new_token.str, "XMMWORD") == 0
9951 || strcasecmp (new_token.str, "OWORD") == 0)
9952 new_token.code = T_XMMWORD;
64a0c779 9953
c0f3af97
L		 9954 else if (strcasecmp (new_token.str, "YMMWORD") == 0)
9955 new_token.code = T_YMMWORD;
9956
64a0c779
DN		 9957 else if (strcasecmp (new_token.str, "PTR") == 0)
9958 new_token.code = T_PTR;
9959
9960 else if (strcasecmp (new_token.str, "SHORT") == 0)
9961 new_token.code = T_SHORT;
9962
9963 else if (strcasecmp (new_token.str, "OFFSET") == 0)
9964 {
9965 new_token.code = T_OFFSET;
9966
9967 /* ??? This is not mentioned in the MASM grammar but gcc
9968 makes use of it with -mintel-syntax. OFFSET may be
9969 followed by FLAT: */
9970 if (strncasecmp (q, " FLAT:", 6) == 0)
9971 strcat (new_token.str, " FLAT:");
9972 }
9973
64a0c779
DN		 9974 else
9975 new_token.code = T_ID;
9976 }
9977 }
9978
9306ca4a
JB		 9979 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
9980 {
9981 new_token.code = *intel_parser.op_string;
9982 new_token.str[0] = *intel_parser.op_string;
9983 new_token.str[1] = '\0';
9984 }
9985
9986 else if (strchr ("<>", *intel_parser.op_string)
9987 && *intel_parser.op_string == *(intel_parser.op_string + 1))
9988 {
9989 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
9990 new_token.str[0] = *intel_parser.op_string;
9991 new_token.str[1] = *intel_parser.op_string;
9992 new_token.str[2] = '\0';
9993 }
9994
64a0c779 9995 else
0477af35 9996 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 9997
9998 intel_parser.op_string += strlen (new_token.str);
9999 cur_token = new_token;
10000}
10001
64a0c779
DN		 10002/* Put cur_token back into the token stream and make cur_token point to
10003 prev_token. */
10004static void
e3bb37b5 10005intel_putback_token (void)
64a0c779 10006{
a724f0f4
JB		 10007 if (cur_token.code != T_NIL)
10008 {
10009 intel_parser.op_string -= strlen (cur_token.str);
10010 free (cur_token.str);
10011 }
64a0c779 10012 cur_token = prev_token;
4a1805b1 10013
64a0c779
DN		 10014 /* Forget prev_token. */
10015 prev_token.code = T_NIL;
10016 prev_token.reg = NULL;
10017 prev_token.str = NULL;
10018}
54cfded0 10019
a60de03c
JB		 10020void
10021tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10022{
a60de03c
JB		 10023 int saved_naked_reg;
10024 char saved_register_dot;
54cfded0 10025
a60de03c
JB		 10026 saved_naked_reg = allow_naked_reg;
10027 allow_naked_reg = 1;
10028 saved_register_dot = register_chars['.'];
10029 register_chars['.'] = '.';
10030 allow_pseudo_reg = 1;
10031 expression_and_evaluate (exp);
10032 allow_pseudo_reg = 0;
10033 register_chars['.'] = saved_register_dot;
10034 allow_naked_reg = saved_naked_reg;
10035
10036 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10037 {
a60de03c
JB		 10038 if ((addressT) exp->X_add_number < i386_regtab_size)
10039 {
10040 exp->X_op = O_constant;
10041 exp->X_add_number = i386_regtab[exp->X_add_number]
10042 .dw2_regnum[flag_code >> 1];
10043 }
10044 else
10045 exp->X_op = O_illegal;
54cfded0 10046 }
54cfded0
AM		 10047}
10048
10049void
10050tc_x86_frame_initial_instructions (void)
10051{
a60de03c
JB		 10052 static unsigned int sp_regno[2];
10053
10054 if (!sp_regno[flag_code >> 1])
10055 {
10056 char *saved_input = input_line_pointer;
10057 char sp[][4] = {"esp", "rsp"};
10058 expressionS exp;
a4447b93 10059
a60de03c
JB		 10060 input_line_pointer = sp[flag_code >> 1];
10061 tc_x86_parse_to_dw2regnum (&exp);
10062 assert (exp.X_op == O_constant);
10063 sp_regno[flag_code >> 1] = exp.X_add_number;
10064 input_line_pointer = saved_input;
10065 }
a4447b93 10066
a60de03c 10067 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 10068 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10069}
d2b2c203
DJ		 10070
10071int
10072i386_elf_section_type (const char *str, size_t len)
10073{
10074 if (flag_code == CODE_64BIT
10075 && len == sizeof ("unwind") - 1
10076 && strncmp (str, "unwind", 6) == 0)
10077 return SHT_X86_64_UNWIND;
10078
10079 return -1;
10080}
bb41ade5 10081
ad5fec3b
EB		 10082#ifdef TE_SOLARIS
10083void
10084i386_solaris_fix_up_eh_frame (segT sec)
10085{
10086 if (flag_code == CODE_64BIT)
10087 elf_section_type (sec) = SHT_X86_64_UNWIND;
10088}
10089#endif
10090
bb41ade5
AM		 10091#ifdef TE_PE
10092void
10093tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10094{
10095 expressionS expr;
10096
10097 expr.X_op = O_secrel;
10098 expr.X_add_symbol = symbol;
10099 expr.X_add_number = 0;
10100 emit_expr (&expr, size);
10101}
10102#endif
3b22753a
L		 10103
10104#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10105/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10106
01e1a5bc 10107bfd_vma
3b22753a
L		 10108x86_64_section_letter (int letter, char **ptr_msg)
10109{
10110 if (flag_code == CODE_64BIT)
10111 {
10112 if (letter == 'l')
10113 return SHF_X86_64_LARGE;
10114
10115 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10116 }
3b22753a 10117 else
64e74474 10118 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10119 return -1;
10120}
10121
01e1a5bc 10122bfd_vma
3b22753a
L		 10123x86_64_section_word (char *str, size_t len)
10124{
8620418b 10125 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10126 return SHF_X86_64_LARGE;
10127
10128 return -1;
10129}
10130
10131static void
10132handle_large_common (int small ATTRIBUTE_UNUSED)
10133{
10134 if (flag_code != CODE_64BIT)
10135 {
10136 s_comm_internal (0, elf_common_parse);
10137 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10138 }
10139 else
10140 {
10141 static segT lbss_section;
10142 asection *saved_com_section_ptr = elf_com_section_ptr;
10143 asection *saved_bss_section = bss_section;
10144
10145 if (lbss_section == NULL)
10146 {
10147 flagword applicable;
10148 segT seg = now_seg;
10149 subsegT subseg = now_subseg;
10150
10151 /* The .lbss section is for local .largecomm symbols. */
10152 lbss_section = subseg_new (".lbss", 0);
10153 applicable = bfd_applicable_section_flags (stdoutput);
10154 bfd_set_section_flags (stdoutput, lbss_section,
10155 applicable & SEC_ALLOC);
10156 seg_info (lbss_section)->bss = 1;
10157
10158 subseg_set (seg, subseg);
10159 }
10160
10161 elf_com_section_ptr = &_bfd_elf_large_com_section;
10162 bss_section = lbss_section;
10163
10164 s_comm_internal (0, elf_common_parse);
10165
10166 elf_com_section_ptr = saved_com_section_ptr;
10167 bss_section = saved_bss_section;
10168 }
10169}
10170#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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