Commit | Line | Data |
---|---|---|
b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
b3adc24a | 2 | Copyright (C) 1989-2020 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
47926f60 KH |
21 | /* Intel 80386 machine specific gas. |
22 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 23 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 24 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
25 | Bugs & suggestions are completely welcome. This is free software. |
26 | Please help us make it better. */ | |
252b5132 | 27 | |
252b5132 | 28 | #include "as.h" |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | #include "subsegs.h" |
316e2c05 | 31 | #include "dwarf2dbg.h" |
54cfded0 | 32 | #include "dw2gencfi.h" |
d2b2c203 | 33 | #include "elf/x86-64.h" |
40fb9820 | 34 | #include "opcodes/i386-init.h" |
252b5132 | 35 | |
41fd2579 L |
36 | #ifdef HAVE_LIMITS_H |
37 | #include <limits.h> | |
38 | #else | |
39 | #ifdef HAVE_SYS_PARAM_H | |
40 | #include <sys/param.h> | |
41 | #endif | |
42 | #ifndef INT_MAX | |
43 | #define INT_MAX (int) (((unsigned) (-1)) >> 1) | |
44 | #endif | |
45 | #endif | |
46 | ||
c3332e24 | 47 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 48 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
49 | #endif |
50 | ||
29b0f896 AM |
51 | #ifndef DEFAULT_ARCH |
52 | #define DEFAULT_ARCH "i386" | |
246fcdee | 53 | #endif |
252b5132 | 54 | |
edde18a5 AM |
55 | #ifndef INLINE |
56 | #if __GNUC__ >= 2 | |
57 | #define INLINE __inline__ | |
58 | #else | |
59 | #define INLINE | |
60 | #endif | |
61 | #endif | |
62 | ||
6305a203 L |
63 | /* Prefixes will be emitted in the order defined below. |
64 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
65 | instruction, and so must come before any prefixes. | |
66 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
42164a71 | 67 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
6305a203 L |
68 | #define WAIT_PREFIX 0 |
69 | #define SEG_PREFIX 1 | |
70 | #define ADDR_PREFIX 2 | |
71 | #define DATA_PREFIX 3 | |
c32fa91d | 72 | #define REP_PREFIX 4 |
42164a71 | 73 | #define HLE_PREFIX REP_PREFIX |
7e8b059b | 74 | #define BND_PREFIX REP_PREFIX |
c32fa91d | 75 | #define LOCK_PREFIX 5 |
4e9ac44a L |
76 | #define REX_PREFIX 6 /* must come last. */ |
77 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ | |
6305a203 L |
78 | |
79 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
80 | #define REGISTER_PREFIX '%' | |
81 | #define IMMEDIATE_PREFIX '$' | |
82 | #define ABSOLUTE_PREFIX '*' | |
83 | ||
84 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
85 | memory operand size in Intel syntax. */ | |
86 | #define WORD_MNEM_SUFFIX 'w' | |
87 | #define BYTE_MNEM_SUFFIX 'b' | |
88 | #define SHORT_MNEM_SUFFIX 's' | |
89 | #define LONG_MNEM_SUFFIX 'l' | |
90 | #define QWORD_MNEM_SUFFIX 'q' | |
6305a203 L |
91 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
92 | in instructions. */ | |
93 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' | |
94 | ||
95 | #define END_OF_INSN '\0' | |
96 | ||
79dec6b7 JB |
97 | /* This matches the C -> StaticRounding alias in the opcode table. */ |
98 | #define commutative staticrounding | |
99 | ||
6305a203 L |
100 | /* |
101 | 'templates' is for grouping together 'template' structures for opcodes | |
102 | of the same name. This is only used for storing the insns in the grand | |
103 | ole hash table of insns. | |
104 | The templates themselves start at START and range up to (but not including) | |
105 | END. | |
106 | */ | |
107 | typedef struct | |
108 | { | |
d3ce72d0 NC |
109 | const insn_template *start; |
110 | const insn_template *end; | |
6305a203 L |
111 | } |
112 | templates; | |
113 | ||
114 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
115 | typedef struct | |
116 | { | |
117 | unsigned int regmem; /* codes register or memory operand */ | |
118 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
119 | unsigned int mode; /* how to interpret regmem & reg */ | |
120 | } | |
121 | modrm_byte; | |
122 | ||
123 | /* x86-64 extension prefix. */ | |
124 | typedef int rex_byte; | |
125 | ||
6305a203 L |
126 | /* 386 opcode byte to code indirect addressing. */ |
127 | typedef struct | |
128 | { | |
129 | unsigned base; | |
130 | unsigned index; | |
131 | unsigned scale; | |
132 | } | |
133 | sib_byte; | |
134 | ||
6305a203 L |
135 | /* x86 arch names, types and features */ |
136 | typedef struct | |
137 | { | |
138 | const char *name; /* arch name */ | |
8a2c8fef | 139 | unsigned int len; /* arch string length */ |
6305a203 L |
140 | enum processor_type type; /* arch type */ |
141 | i386_cpu_flags flags; /* cpu feature flags */ | |
8a2c8fef | 142 | unsigned int skip; /* show_arch should skip this. */ |
6305a203 L |
143 | } |
144 | arch_entry; | |
145 | ||
293f5f65 L |
146 | /* Used to turn off indicated flags. */ |
147 | typedef struct | |
148 | { | |
149 | const char *name; /* arch name */ | |
150 | unsigned int len; /* arch string length */ | |
151 | i386_cpu_flags flags; /* cpu feature flags */ | |
152 | } | |
153 | noarch_entry; | |
154 | ||
78f12dd3 | 155 | static void update_code_flag (int, int); |
e3bb37b5 L |
156 | static void set_code_flag (int); |
157 | static void set_16bit_gcc_code_flag (int); | |
158 | static void set_intel_syntax (int); | |
1efbbeb4 | 159 | static void set_intel_mnemonic (int); |
db51cc60 | 160 | static void set_allow_index_reg (int); |
7bab8ab5 | 161 | static void set_check (int); |
e3bb37b5 | 162 | static void set_cpu_arch (int); |
6482c264 | 163 | #ifdef TE_PE |
e3bb37b5 | 164 | static void pe_directive_secrel (int); |
6482c264 | 165 | #endif |
e3bb37b5 L |
166 | static void signed_cons (int); |
167 | static char *output_invalid (int c); | |
ee86248c JB |
168 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
169 | const char *); | |
170 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
171 | const char *); | |
a7619375 | 172 | static int i386_att_operand (char *); |
e3bb37b5 | 173 | static int i386_intel_operand (char *, int); |
ee86248c JB |
174 | static int i386_intel_simplify (expressionS *); |
175 | static int i386_intel_parse_name (const char *, expressionS *); | |
e3bb37b5 L |
176 | static const reg_entry *parse_register (char *, char **); |
177 | static char *parse_insn (char *, char *); | |
178 | static char *parse_operands (char *, const char *); | |
179 | static void swap_operands (void); | |
4d456e3d | 180 | static void swap_2_operands (int, int); |
48bcea9f | 181 | static enum flag_code i386_addressing_mode (void); |
e3bb37b5 L |
182 | static void optimize_imm (void); |
183 | static void optimize_disp (void); | |
83b16ac6 | 184 | static const insn_template *match_template (char); |
e3bb37b5 L |
185 | static int check_string (void); |
186 | static int process_suffix (void); | |
187 | static int check_byte_reg (void); | |
188 | static int check_long_reg (void); | |
189 | static int check_qword_reg (void); | |
190 | static int check_word_reg (void); | |
191 | static int finalize_imm (void); | |
192 | static int process_operands (void); | |
193 | static const seg_entry *build_modrm_byte (void); | |
194 | static void output_insn (void); | |
195 | static void output_imm (fragS *, offsetT); | |
196 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 197 | #ifndef I386COFF |
e3bb37b5 | 198 | static void s_bss (int); |
252b5132 | 199 | #endif |
17d4e2a2 L |
200 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
201 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
b4a3a7b4 L |
202 | |
203 | /* GNU_PROPERTY_X86_ISA_1_USED. */ | |
204 | static unsigned int x86_isa_1_used; | |
205 | /* GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
206 | static unsigned int x86_feature_2_used; | |
207 | /* Generate x86 used ISA and feature properties. */ | |
208 | static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE; | |
17d4e2a2 | 209 | #endif |
252b5132 | 210 | |
a847613f | 211 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 212 | |
8a6fb3f9 JB |
213 | /* parse_register() returns this when a register alias cannot be used. */ |
214 | static const reg_entry bad_reg = { "<bad>", OPERAND_TYPE_NONE, 0, 0, | |
215 | { Dw2Inval, Dw2Inval } }; | |
216 | ||
43234a1e L |
217 | /* This struct describes rounding control and SAE in the instruction. */ |
218 | struct RC_Operation | |
219 | { | |
220 | enum rc_type | |
221 | { | |
222 | rne = 0, | |
223 | rd, | |
224 | ru, | |
225 | rz, | |
226 | saeonly | |
227 | } type; | |
228 | int operand; | |
229 | }; | |
230 | ||
231 | static struct RC_Operation rc_op; | |
232 | ||
233 | /* The struct describes masking, applied to OPERAND in the instruction. | |
234 | MASK is a pointer to the corresponding mask register. ZEROING tells | |
235 | whether merging or zeroing mask is used. */ | |
236 | struct Mask_Operation | |
237 | { | |
238 | const reg_entry *mask; | |
239 | unsigned int zeroing; | |
240 | /* The operand where this operation is associated. */ | |
241 | int operand; | |
242 | }; | |
243 | ||
244 | static struct Mask_Operation mask_op; | |
245 | ||
246 | /* The struct describes broadcasting, applied to OPERAND. FACTOR is | |
247 | broadcast factor. */ | |
248 | struct Broadcast_Operation | |
249 | { | |
8e6e0792 | 250 | /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */ |
43234a1e L |
251 | int type; |
252 | ||
253 | /* Index of broadcasted operand. */ | |
254 | int operand; | |
4a1b91ea L |
255 | |
256 | /* Number of bytes to broadcast. */ | |
257 | int bytes; | |
43234a1e L |
258 | }; |
259 | ||
260 | static struct Broadcast_Operation broadcast_op; | |
261 | ||
c0f3af97 L |
262 | /* VEX prefix. */ |
263 | typedef struct | |
264 | { | |
43234a1e L |
265 | /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ |
266 | unsigned char bytes[4]; | |
c0f3af97 L |
267 | unsigned int length; |
268 | /* Destination or source register specifier. */ | |
269 | const reg_entry *register_specifier; | |
270 | } vex_prefix; | |
271 | ||
252b5132 | 272 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 273 | i386_insn. */ |
252b5132 | 274 | |
520dc8e8 AM |
275 | union i386_op |
276 | { | |
277 | expressionS *disps; | |
278 | expressionS *imms; | |
279 | const reg_entry *regs; | |
280 | }; | |
281 | ||
a65babc9 L |
282 | enum i386_error |
283 | { | |
86e026a4 | 284 | operand_size_mismatch, |
a65babc9 L |
285 | operand_type_mismatch, |
286 | register_type_mismatch, | |
287 | number_of_operands_mismatch, | |
288 | invalid_instruction_suffix, | |
289 | bad_imm4, | |
a65babc9 L |
290 | unsupported_with_intel_mnemonic, |
291 | unsupported_syntax, | |
6c30d220 | 292 | unsupported, |
260cd341 | 293 | invalid_sib_address, |
6c30d220 | 294 | invalid_vsib_address, |
7bab8ab5 | 295 | invalid_vector_register_set, |
260cd341 | 296 | invalid_tmm_register_set, |
43234a1e L |
297 | unsupported_vector_index_register, |
298 | unsupported_broadcast, | |
43234a1e L |
299 | broadcast_needed, |
300 | unsupported_masking, | |
301 | mask_not_on_destination, | |
302 | no_default_mask, | |
303 | unsupported_rc_sae, | |
304 | rc_sae_operand_not_last_imm, | |
305 | invalid_register_operand, | |
a65babc9 L |
306 | }; |
307 | ||
252b5132 RH |
308 | struct _i386_insn |
309 | { | |
47926f60 | 310 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 311 | insn_template tm; |
252b5132 | 312 | |
7d5e4556 L |
313 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
314 | or qword, if given. */ | |
252b5132 RH |
315 | char suffix; |
316 | ||
47926f60 | 317 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
318 | unsigned int operands; |
319 | ||
320 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
321 | of given register, displacement, memory operands and immediate | |
47926f60 | 322 | operands. */ |
252b5132 RH |
323 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
324 | ||
325 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 326 | use OP[i] for the corresponding operand. */ |
40fb9820 | 327 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 328 | |
520dc8e8 AM |
329 | /* Displacement expression, immediate expression, or register for each |
330 | operand. */ | |
331 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 332 | |
3e73aa7c JH |
333 | /* Flags for operands. */ |
334 | unsigned int flags[MAX_OPERANDS]; | |
335 | #define Operand_PCrel 1 | |
c48dadc9 | 336 | #define Operand_Mem 2 |
3e73aa7c | 337 | |
252b5132 | 338 | /* Relocation type for operand */ |
f86103b7 | 339 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 340 | |
252b5132 RH |
341 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
342 | the base index byte below. */ | |
343 | const reg_entry *base_reg; | |
344 | const reg_entry *index_reg; | |
345 | unsigned int log2_scale_factor; | |
346 | ||
347 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 348 | explicit segment overrides are given. */ |
ce8a8b2f | 349 | const seg_entry *seg[2]; |
252b5132 | 350 | |
8325cc63 JB |
351 | /* Copied first memory operand string, for re-checking. */ |
352 | char *memop1_string; | |
353 | ||
252b5132 RH |
354 | /* PREFIX holds all the given prefix opcodes (usually null). |
355 | PREFIXES is the number of prefix opcodes. */ | |
356 | unsigned int prefixes; | |
357 | unsigned char prefix[MAX_PREFIXES]; | |
358 | ||
50128d0c JB |
359 | /* Register is in low 3 bits of opcode. */ |
360 | bfd_boolean short_form; | |
361 | ||
6f2f06be JB |
362 | /* The operand to a branch insn indicates an absolute branch. */ |
363 | bfd_boolean jumpabsolute; | |
364 | ||
921eafea L |
365 | /* Extended states. */ |
366 | enum | |
367 | { | |
368 | /* Use MMX state. */ | |
369 | xstate_mmx = 1 << 0, | |
370 | /* Use XMM state. */ | |
371 | xstate_xmm = 1 << 1, | |
372 | /* Use YMM state. */ | |
373 | xstate_ymm = 1 << 2 | xstate_xmm, | |
374 | /* Use ZMM state. */ | |
375 | xstate_zmm = 1 << 3 | xstate_ymm, | |
376 | /* Use TMM state. */ | |
377 | xstate_tmm = 1 << 4 | |
378 | } xstate; | |
260cd341 | 379 | |
e379e5f3 L |
380 | /* Has GOTPC or TLS relocation. */ |
381 | bfd_boolean has_gotpc_tls_reloc; | |
382 | ||
252b5132 | 383 | /* RM and SIB are the modrm byte and the sib byte where the |
c1e679ec | 384 | addressing modes of this insn are encoded. */ |
252b5132 | 385 | modrm_byte rm; |
3e73aa7c | 386 | rex_byte rex; |
43234a1e | 387 | rex_byte vrex; |
252b5132 | 388 | sib_byte sib; |
c0f3af97 | 389 | vex_prefix vex; |
b6169b20 | 390 | |
43234a1e L |
391 | /* Masking attributes. */ |
392 | struct Mask_Operation *mask; | |
393 | ||
394 | /* Rounding control and SAE attributes. */ | |
395 | struct RC_Operation *rounding; | |
396 | ||
397 | /* Broadcasting attributes. */ | |
398 | struct Broadcast_Operation *broadcast; | |
399 | ||
400 | /* Compressed disp8*N attribute. */ | |
401 | unsigned int memshift; | |
402 | ||
86fa6981 L |
403 | /* Prefer load or store in encoding. */ |
404 | enum | |
405 | { | |
406 | dir_encoding_default = 0, | |
407 | dir_encoding_load, | |
64c49ab3 JB |
408 | dir_encoding_store, |
409 | dir_encoding_swap | |
86fa6981 | 410 | } dir_encoding; |
891edac4 | 411 | |
41eb8e88 | 412 | /* Prefer 8bit, 16bit, 32bit displacement in encoding. */ |
a501d77e L |
413 | enum |
414 | { | |
415 | disp_encoding_default = 0, | |
416 | disp_encoding_8bit, | |
41eb8e88 | 417 | disp_encoding_16bit, |
a501d77e L |
418 | disp_encoding_32bit |
419 | } disp_encoding; | |
f8a5c266 | 420 | |
6b6b6807 L |
421 | /* Prefer the REX byte in encoding. */ |
422 | bfd_boolean rex_encoding; | |
423 | ||
b6f8c7c4 L |
424 | /* Disable instruction size optimization. */ |
425 | bfd_boolean no_optimize; | |
426 | ||
86fa6981 L |
427 | /* How to encode vector instructions. */ |
428 | enum | |
429 | { | |
430 | vex_encoding_default = 0, | |
42e04b36 | 431 | vex_encoding_vex, |
86fa6981 | 432 | vex_encoding_vex3, |
da4977e0 JB |
433 | vex_encoding_evex, |
434 | vex_encoding_error | |
86fa6981 L |
435 | } vec_encoding; |
436 | ||
d5de92cf L |
437 | /* REP prefix. */ |
438 | const char *rep_prefix; | |
439 | ||
165de32a L |
440 | /* HLE prefix. */ |
441 | const char *hle_prefix; | |
42164a71 | 442 | |
7e8b059b L |
443 | /* Have BND prefix. */ |
444 | const char *bnd_prefix; | |
445 | ||
04ef582a L |
446 | /* Have NOTRACK prefix. */ |
447 | const char *notrack_prefix; | |
448 | ||
891edac4 | 449 | /* Error message. */ |
a65babc9 | 450 | enum i386_error error; |
252b5132 RH |
451 | }; |
452 | ||
453 | typedef struct _i386_insn i386_insn; | |
454 | ||
43234a1e L |
455 | /* Link RC type with corresponding string, that'll be looked for in |
456 | asm. */ | |
457 | struct RC_name | |
458 | { | |
459 | enum rc_type type; | |
460 | const char *name; | |
461 | unsigned int len; | |
462 | }; | |
463 | ||
464 | static const struct RC_name RC_NamesTable[] = | |
465 | { | |
466 | { rne, STRING_COMMA_LEN ("rn-sae") }, | |
467 | { rd, STRING_COMMA_LEN ("rd-sae") }, | |
468 | { ru, STRING_COMMA_LEN ("ru-sae") }, | |
469 | { rz, STRING_COMMA_LEN ("rz-sae") }, | |
470 | { saeonly, STRING_COMMA_LEN ("sae") }, | |
471 | }; | |
472 | ||
252b5132 RH |
473 | /* List of chars besides those in app.c:symbol_chars that can start an |
474 | operand. Used to prevent the scrubber eating vital white-space. */ | |
86fa6981 | 475 | const char extra_symbol_chars[] = "*%-([{}" |
252b5132 | 476 | #ifdef LEX_AT |
32137342 NC |
477 | "@" |
478 | #endif | |
479 | #ifdef LEX_QM | |
480 | "?" | |
252b5132 | 481 | #endif |
32137342 | 482 | ; |
252b5132 | 483 | |
b3983e5f JB |
484 | #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ |
485 | && !defined (TE_GNU) \ | |
486 | && !defined (TE_LINUX) \ | |
487 | && !defined (TE_FreeBSD) \ | |
488 | && !defined (TE_DragonFly) \ | |
489 | && !defined (TE_NetBSD)) | |
252b5132 | 490 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
491 | pre-processor is disabled, these aren't very useful. The option |
492 | --divide will remove '/' from this list. */ | |
493 | const char *i386_comment_chars = "#/"; | |
494 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 495 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 496 | |
b3b91714 AM |
497 | #else |
498 | const char *i386_comment_chars = "#"; | |
499 | #define PREFIX_SEPARATOR '/' | |
500 | #endif | |
501 | ||
252b5132 RH |
502 | /* This array holds the chars that only start a comment at the beginning of |
503 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
504 | .line and .file directives will appear in the pre-processed output. |
505 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 506 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
507 | #NO_APP at the beginning of its output. |
508 | Also note that comments started like this one will always work if | |
252b5132 | 509 | '/' isn't otherwise defined. */ |
b3b91714 | 510 | const char line_comment_chars[] = "#/"; |
252b5132 | 511 | |
63a0b638 | 512 | const char line_separator_chars[] = ";"; |
252b5132 | 513 | |
ce8a8b2f AM |
514 | /* Chars that can be used to separate mant from exp in floating point |
515 | nums. */ | |
252b5132 RH |
516 | const char EXP_CHARS[] = "eE"; |
517 | ||
ce8a8b2f AM |
518 | /* Chars that mean this number is a floating point constant |
519 | As in 0f12.456 | |
520 | or 0d1.2345e12. */ | |
252b5132 RH |
521 | const char FLT_CHARS[] = "fFdDxX"; |
522 | ||
ce8a8b2f | 523 | /* Tables for lexical analysis. */ |
252b5132 RH |
524 | static char mnemonic_chars[256]; |
525 | static char register_chars[256]; | |
526 | static char operand_chars[256]; | |
527 | static char identifier_chars[256]; | |
528 | static char digit_chars[256]; | |
529 | ||
ce8a8b2f | 530 | /* Lexical macros. */ |
252b5132 RH |
531 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
532 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
533 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
534 | #define is_space_char(x) ((x) == ' ') | |
535 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
536 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
537 | ||
0234cb7c | 538 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
539 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
540 | ||
541 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
542 | effect this we maintain a stack of saved characters that we've smashed | |
543 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 544 | assembler instruction). */ |
252b5132 | 545 | static char save_stack[32]; |
ce8a8b2f | 546 | static char *save_stack_p; |
252b5132 RH |
547 | #define END_STRING_AND_SAVE(s) \ |
548 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
549 | #define RESTORE_END_STRING(s) \ | |
550 | do { *(s) = *--save_stack_p; } while (0) | |
551 | ||
47926f60 | 552 | /* The instruction we're assembling. */ |
252b5132 RH |
553 | static i386_insn i; |
554 | ||
555 | /* Possible templates for current insn. */ | |
556 | static const templates *current_templates; | |
557 | ||
31b2323c L |
558 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
559 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
560 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 561 | |
47926f60 | 562 | /* Current operand we are working on. */ |
ee86248c | 563 | static int this_operand = -1; |
252b5132 | 564 | |
3e73aa7c JH |
565 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
566 | these. */ | |
567 | ||
568 | enum flag_code { | |
569 | CODE_32BIT, | |
570 | CODE_16BIT, | |
571 | CODE_64BIT }; | |
572 | ||
573 | static enum flag_code flag_code; | |
4fa24527 | 574 | static unsigned int object_64bit; |
862be3fb | 575 | static unsigned int disallow_64bit_reloc; |
3e73aa7c | 576 | static int use_rela_relocations = 0; |
e379e5f3 L |
577 | /* __tls_get_addr/___tls_get_addr symbol for TLS. */ |
578 | static const char *tls_get_addr; | |
3e73aa7c | 579 | |
7af8ed2d NC |
580 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
581 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ | |
582 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) | |
583 | ||
351f65ca L |
584 | /* The ELF ABI to use. */ |
585 | enum x86_elf_abi | |
586 | { | |
587 | I386_ABI, | |
7f56bc95 L |
588 | X86_64_ABI, |
589 | X86_64_X32_ABI | |
351f65ca L |
590 | }; |
591 | ||
592 | static enum x86_elf_abi x86_elf_abi = I386_ABI; | |
7af8ed2d | 593 | #endif |
351f65ca | 594 | |
167ad85b TG |
595 | #if defined (TE_PE) || defined (TE_PEP) |
596 | /* Use big object file format. */ | |
597 | static int use_big_obj = 0; | |
598 | #endif | |
599 | ||
8dcea932 L |
600 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
601 | /* 1 if generating code for a shared library. */ | |
602 | static int shared = 0; | |
603 | #endif | |
604 | ||
47926f60 KH |
605 | /* 1 for intel syntax, |
606 | 0 if att syntax. */ | |
607 | static int intel_syntax = 0; | |
252b5132 | 608 | |
4b5aaf5f L |
609 | static enum x86_64_isa |
610 | { | |
611 | amd64 = 1, /* AMD64 ISA. */ | |
612 | intel64 /* Intel64 ISA. */ | |
613 | } isa64; | |
e89c5eaa | 614 | |
1efbbeb4 L |
615 | /* 1 for intel mnemonic, |
616 | 0 if att mnemonic. */ | |
617 | static int intel_mnemonic = !SYSV386_COMPAT; | |
618 | ||
a60de03c JB |
619 | /* 1 if pseudo registers are permitted. */ |
620 | static int allow_pseudo_reg = 0; | |
621 | ||
47926f60 KH |
622 | /* 1 if register prefix % not required. */ |
623 | static int allow_naked_reg = 0; | |
252b5132 | 624 | |
33eaf5de | 625 | /* 1 if the assembler should add BND prefix for all control-transferring |
7e8b059b L |
626 | instructions supporting it, even if this prefix wasn't specified |
627 | explicitly. */ | |
628 | static int add_bnd_prefix = 0; | |
629 | ||
ba104c83 | 630 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
631 | static int allow_index_reg = 0; |
632 | ||
d022bddd IT |
633 | /* 1 if the assembler should ignore LOCK prefix, even if it was |
634 | specified explicitly. */ | |
635 | static int omit_lock_prefix = 0; | |
636 | ||
e4e00185 AS |
637 | /* 1 if the assembler should encode lfence, mfence, and sfence as |
638 | "lock addl $0, (%{re}sp)". */ | |
639 | static int avoid_fence = 0; | |
640 | ||
ae531041 L |
641 | /* 1 if lfence should be inserted after every load. */ |
642 | static int lfence_after_load = 0; | |
643 | ||
644 | /* Non-zero if lfence should be inserted before indirect branch. */ | |
645 | static enum lfence_before_indirect_branch_kind | |
646 | { | |
647 | lfence_branch_none = 0, | |
648 | lfence_branch_register, | |
649 | lfence_branch_memory, | |
650 | lfence_branch_all | |
651 | } | |
652 | lfence_before_indirect_branch; | |
653 | ||
654 | /* Non-zero if lfence should be inserted before ret. */ | |
655 | static enum lfence_before_ret_kind | |
656 | { | |
657 | lfence_before_ret_none = 0, | |
658 | lfence_before_ret_not, | |
a09f656b | 659 | lfence_before_ret_or, |
660 | lfence_before_ret_shl | |
ae531041 L |
661 | } |
662 | lfence_before_ret; | |
663 | ||
664 | /* Types of previous instruction is .byte or prefix. */ | |
e379e5f3 L |
665 | static struct |
666 | { | |
667 | segT seg; | |
668 | const char *file; | |
669 | const char *name; | |
670 | unsigned int line; | |
671 | enum last_insn_kind | |
672 | { | |
673 | last_insn_other = 0, | |
674 | last_insn_directive, | |
675 | last_insn_prefix | |
676 | } kind; | |
677 | } last_insn; | |
678 | ||
0cb4071e L |
679 | /* 1 if the assembler should generate relax relocations. */ |
680 | ||
681 | static int generate_relax_relocations | |
682 | = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; | |
683 | ||
7bab8ab5 | 684 | static enum check_kind |
daf50ae7 | 685 | { |
7bab8ab5 JB |
686 | check_none = 0, |
687 | check_warning, | |
688 | check_error | |
daf50ae7 | 689 | } |
7bab8ab5 | 690 | sse_check, operand_check = check_warning; |
daf50ae7 | 691 | |
e379e5f3 L |
692 | /* Non-zero if branches should be aligned within power of 2 boundary. */ |
693 | static int align_branch_power = 0; | |
694 | ||
695 | /* Types of branches to align. */ | |
696 | enum align_branch_kind | |
697 | { | |
698 | align_branch_none = 0, | |
699 | align_branch_jcc = 1, | |
700 | align_branch_fused = 2, | |
701 | align_branch_jmp = 3, | |
702 | align_branch_call = 4, | |
703 | align_branch_indirect = 5, | |
704 | align_branch_ret = 6 | |
705 | }; | |
706 | ||
707 | /* Type bits of branches to align. */ | |
708 | enum align_branch_bit | |
709 | { | |
710 | align_branch_jcc_bit = 1 << align_branch_jcc, | |
711 | align_branch_fused_bit = 1 << align_branch_fused, | |
712 | align_branch_jmp_bit = 1 << align_branch_jmp, | |
713 | align_branch_call_bit = 1 << align_branch_call, | |
714 | align_branch_indirect_bit = 1 << align_branch_indirect, | |
715 | align_branch_ret_bit = 1 << align_branch_ret | |
716 | }; | |
717 | ||
718 | static unsigned int align_branch = (align_branch_jcc_bit | |
719 | | align_branch_fused_bit | |
720 | | align_branch_jmp_bit); | |
721 | ||
79d72f45 HL |
722 | /* Types of condition jump used by macro-fusion. */ |
723 | enum mf_jcc_kind | |
724 | { | |
725 | mf_jcc_jo = 0, /* base opcode 0x70 */ | |
726 | mf_jcc_jc, /* base opcode 0x72 */ | |
727 | mf_jcc_je, /* base opcode 0x74 */ | |
728 | mf_jcc_jna, /* base opcode 0x76 */ | |
729 | mf_jcc_js, /* base opcode 0x78 */ | |
730 | mf_jcc_jp, /* base opcode 0x7a */ | |
731 | mf_jcc_jl, /* base opcode 0x7c */ | |
732 | mf_jcc_jle, /* base opcode 0x7e */ | |
733 | }; | |
734 | ||
735 | /* Types of compare flag-modifying insntructions used by macro-fusion. */ | |
736 | enum mf_cmp_kind | |
737 | { | |
738 | mf_cmp_test_and, /* test/cmp */ | |
739 | mf_cmp_alu_cmp, /* add/sub/cmp */ | |
740 | mf_cmp_incdec /* inc/dec */ | |
741 | }; | |
742 | ||
e379e5f3 L |
743 | /* The maximum padding size for fused jcc. CMP like instruction can |
744 | be 9 bytes and jcc can be 6 bytes. Leave room just in case for | |
745 | prefixes. */ | |
746 | #define MAX_FUSED_JCC_PADDING_SIZE 20 | |
747 | ||
748 | /* The maximum number of prefixes added for an instruction. */ | |
749 | static unsigned int align_branch_prefix_size = 5; | |
750 | ||
b6f8c7c4 L |
751 | /* Optimization: |
752 | 1. Clear the REX_W bit with register operand if possible. | |
753 | 2. Above plus use 128bit vector instruction to clear the full vector | |
754 | register. | |
755 | */ | |
756 | static int optimize = 0; | |
757 | ||
758 | /* Optimization: | |
759 | 1. Clear the REX_W bit with register operand if possible. | |
760 | 2. Above plus use 128bit vector instruction to clear the full vector | |
761 | register. | |
762 | 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to | |
763 | "testb $imm7,%r8". | |
764 | */ | |
765 | static int optimize_for_space = 0; | |
766 | ||
2ca3ace5 L |
767 | /* Register prefix used for error message. */ |
768 | static const char *register_prefix = "%"; | |
769 | ||
47926f60 KH |
770 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
771 | leave, push, and pop instructions so that gcc has the same stack | |
772 | frame as in 32 bit mode. */ | |
773 | static char stackop_size = '\0'; | |
eecb386c | 774 | |
12b55ccc L |
775 | /* Non-zero to optimize code alignment. */ |
776 | int optimize_align_code = 1; | |
777 | ||
47926f60 KH |
778 | /* Non-zero to quieten some warnings. */ |
779 | static int quiet_warnings = 0; | |
a38cf1db | 780 | |
47926f60 KH |
781 | /* CPU name. */ |
782 | static const char *cpu_arch_name = NULL; | |
6305a203 | 783 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 784 | |
47926f60 | 785 | /* CPU feature flags. */ |
40fb9820 L |
786 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
787 | ||
ccc9c027 L |
788 | /* If we have selected a cpu we are generating instructions for. */ |
789 | static int cpu_arch_tune_set = 0; | |
790 | ||
9103f4f4 | 791 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 792 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 L |
793 | |
794 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 795 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 796 | |
ccc9c027 | 797 | /* CPU instruction set architecture used. */ |
fbf3f584 | 798 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 799 | |
9103f4f4 | 800 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 801 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 802 | |
fddf5b5b AM |
803 | /* If set, conditional jumps are not automatically promoted to handle |
804 | larger than a byte offset. */ | |
805 | static unsigned int no_cond_jump_promotion = 0; | |
806 | ||
c0f3af97 L |
807 | /* Encode SSE instructions with VEX prefix. */ |
808 | static unsigned int sse2avx; | |
809 | ||
539f890d L |
810 | /* Encode scalar AVX instructions with specific vector length. */ |
811 | static enum | |
812 | { | |
813 | vex128 = 0, | |
814 | vex256 | |
815 | } avxscalar; | |
816 | ||
03751133 L |
817 | /* Encode VEX WIG instructions with specific vex.w. */ |
818 | static enum | |
819 | { | |
820 | vexw0 = 0, | |
821 | vexw1 | |
822 | } vexwig; | |
823 | ||
43234a1e L |
824 | /* Encode scalar EVEX LIG instructions with specific vector length. */ |
825 | static enum | |
826 | { | |
827 | evexl128 = 0, | |
828 | evexl256, | |
829 | evexl512 | |
830 | } evexlig; | |
831 | ||
832 | /* Encode EVEX WIG instructions with specific evex.w. */ | |
833 | static enum | |
834 | { | |
835 | evexw0 = 0, | |
836 | evexw1 | |
837 | } evexwig; | |
838 | ||
d3d3c6db IT |
839 | /* Value to encode in EVEX RC bits, for SAE-only instructions. */ |
840 | static enum rc_type evexrcig = rne; | |
841 | ||
29b0f896 | 842 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 843 | static symbolS *GOT_symbol; |
29b0f896 | 844 | |
a4447b93 RH |
845 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
846 | unsigned int x86_dwarf2_return_column; | |
847 | ||
848 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
849 | int x86_cie_data_alignment; | |
850 | ||
252b5132 | 851 | /* Interface to relax_segment. |
fddf5b5b AM |
852 | There are 3 major relax states for 386 jump insns because the |
853 | different types of jumps add different sizes to frags when we're | |
e379e5f3 L |
854 | figuring out what sort of jump to choose to reach a given label. |
855 | ||
856 | BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align | |
857 | branches which are handled by md_estimate_size_before_relax() and | |
858 | i386_generic_table_relax_frag(). */ | |
252b5132 | 859 | |
47926f60 | 860 | /* Types. */ |
93c2a809 AM |
861 | #define UNCOND_JUMP 0 |
862 | #define COND_JUMP 1 | |
863 | #define COND_JUMP86 2 | |
e379e5f3 L |
864 | #define BRANCH_PADDING 3 |
865 | #define BRANCH_PREFIX 4 | |
866 | #define FUSED_JCC_PADDING 5 | |
fddf5b5b | 867 | |
47926f60 | 868 | /* Sizes. */ |
252b5132 RH |
869 | #define CODE16 1 |
870 | #define SMALL 0 | |
29b0f896 | 871 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 872 | #define BIG 2 |
29b0f896 | 873 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
874 | |
875 | #ifndef INLINE | |
876 | #ifdef __GNUC__ | |
877 | #define INLINE __inline__ | |
878 | #else | |
879 | #define INLINE | |
880 | #endif | |
881 | #endif | |
882 | ||
fddf5b5b AM |
883 | #define ENCODE_RELAX_STATE(type, size) \ |
884 | ((relax_substateT) (((type) << 2) | (size))) | |
885 | #define TYPE_FROM_RELAX_STATE(s) \ | |
886 | ((s) >> 2) | |
887 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
888 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
889 | |
890 | /* This table is used by relax_frag to promote short jumps to long | |
891 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
892 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
893 | don't allow a short jump in a 32 bit code segment to be promoted to | |
894 | a 16 bit offset jump because it's slower (requires data size | |
895 | prefix), and doesn't work, unless the destination is in the bottom | |
896 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
897 | ||
898 | const relax_typeS md_relax_table[] = | |
899 | { | |
24eab124 AM |
900 | /* The fields are: |
901 | 1) most positive reach of this state, | |
902 | 2) most negative reach of this state, | |
93c2a809 | 903 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 904 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 905 | |
fddf5b5b | 906 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
907 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
908 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
909 | /* dword jmp adds 4 bytes to frag: | |
910 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 911 | {0, 0, 4, 0}, |
93c2a809 AM |
912 | /* word jmp adds 2 byte2 to frag: |
913 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
914 | {0, 0, 2, 0}, |
915 | ||
93c2a809 AM |
916 | /* COND_JUMP states. */ |
917 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
918 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
919 | /* dword conditionals adds 5 bytes to frag: | |
920 | 1 extra opcode byte, 4 displacement bytes. */ | |
921 | {0, 0, 5, 0}, | |
fddf5b5b | 922 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
923 | 1 extra opcode byte, 2 displacement bytes. */ |
924 | {0, 0, 3, 0}, | |
925 | ||
926 | /* COND_JUMP86 states. */ | |
927 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
928 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
929 | /* dword conditionals adds 5 bytes to frag: | |
930 | 1 extra opcode byte, 4 displacement bytes. */ | |
931 | {0, 0, 5, 0}, | |
932 | /* word conditionals add 4 bytes to frag: | |
933 | 1 displacement byte and a 3 byte long branch insn. */ | |
934 | {0, 0, 4, 0} | |
252b5132 RH |
935 | }; |
936 | ||
9103f4f4 L |
937 | static const arch_entry cpu_arch[] = |
938 | { | |
89507696 JB |
939 | /* Do not replace the first two entries - i386_target_format() |
940 | relies on them being there in this order. */ | |
8a2c8fef | 941 | { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, |
293f5f65 | 942 | CPU_GENERIC32_FLAGS, 0 }, |
8a2c8fef | 943 | { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, |
293f5f65 | 944 | CPU_GENERIC64_FLAGS, 0 }, |
8a2c8fef | 945 | { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, |
293f5f65 | 946 | CPU_NONE_FLAGS, 0 }, |
8a2c8fef | 947 | { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, |
293f5f65 | 948 | CPU_I186_FLAGS, 0 }, |
8a2c8fef | 949 | { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, |
293f5f65 | 950 | CPU_I286_FLAGS, 0 }, |
8a2c8fef | 951 | { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, |
293f5f65 | 952 | CPU_I386_FLAGS, 0 }, |
8a2c8fef | 953 | { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, |
293f5f65 | 954 | CPU_I486_FLAGS, 0 }, |
8a2c8fef | 955 | { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, |
293f5f65 | 956 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 957 | { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 958 | CPU_I686_FLAGS, 0 }, |
8a2c8fef | 959 | { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, |
293f5f65 | 960 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 961 | { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 962 | CPU_PENTIUMPRO_FLAGS, 0 }, |
8a2c8fef | 963 | { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 964 | CPU_P2_FLAGS, 0 }, |
8a2c8fef | 965 | { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, |
293f5f65 | 966 | CPU_P3_FLAGS, 0 }, |
8a2c8fef | 967 | { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, |
293f5f65 | 968 | CPU_P4_FLAGS, 0 }, |
8a2c8fef | 969 | { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, |
293f5f65 | 970 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 971 | { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, |
293f5f65 | 972 | CPU_NOCONA_FLAGS, 0 }, |
8a2c8fef | 973 | { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, |
293f5f65 | 974 | CPU_CORE_FLAGS, 1 }, |
8a2c8fef | 975 | { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, |
293f5f65 | 976 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 977 | { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, |
293f5f65 | 978 | CPU_CORE2_FLAGS, 1 }, |
8a2c8fef | 979 | { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, |
293f5f65 | 980 | CPU_CORE2_FLAGS, 0 }, |
8a2c8fef | 981 | { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, |
293f5f65 | 982 | CPU_COREI7_FLAGS, 0 }, |
8a2c8fef | 983 | { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, |
293f5f65 | 984 | CPU_L1OM_FLAGS, 0 }, |
7a9068fe | 985 | { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, |
293f5f65 | 986 | CPU_K1OM_FLAGS, 0 }, |
81486035 | 987 | { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU, |
293f5f65 | 988 | CPU_IAMCU_FLAGS, 0 }, |
8a2c8fef | 989 | { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, |
293f5f65 | 990 | CPU_K6_FLAGS, 0 }, |
8a2c8fef | 991 | { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, |
293f5f65 | 992 | CPU_K6_2_FLAGS, 0 }, |
8a2c8fef | 993 | { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, |
293f5f65 | 994 | CPU_ATHLON_FLAGS, 0 }, |
8a2c8fef | 995 | { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, |
293f5f65 | 996 | CPU_K8_FLAGS, 1 }, |
8a2c8fef | 997 | { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, |
293f5f65 | 998 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 999 | { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, |
293f5f65 | 1000 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 1001 | { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, |
293f5f65 | 1002 | CPU_AMDFAM10_FLAGS, 0 }, |
8aedb9fe | 1003 | { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, |
293f5f65 | 1004 | CPU_BDVER1_FLAGS, 0 }, |
8aedb9fe | 1005 | { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, |
293f5f65 | 1006 | CPU_BDVER2_FLAGS, 0 }, |
5e5c50d3 | 1007 | { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD, |
293f5f65 | 1008 | CPU_BDVER3_FLAGS, 0 }, |
c7b0bd56 | 1009 | { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD, |
293f5f65 | 1010 | CPU_BDVER4_FLAGS, 0 }, |
029f3522 | 1011 | { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER, |
293f5f65 | 1012 | CPU_ZNVER1_FLAGS, 0 }, |
a9660a6f AP |
1013 | { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER, |
1014 | CPU_ZNVER2_FLAGS, 0 }, | |
7b458c12 | 1015 | { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, |
293f5f65 | 1016 | CPU_BTVER1_FLAGS, 0 }, |
7b458c12 | 1017 | { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, |
293f5f65 | 1018 | CPU_BTVER2_FLAGS, 0 }, |
8a2c8fef | 1019 | { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, |
293f5f65 | 1020 | CPU_8087_FLAGS, 0 }, |
8a2c8fef | 1021 | { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, |
293f5f65 | 1022 | CPU_287_FLAGS, 0 }, |
8a2c8fef | 1023 | { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, |
293f5f65 | 1024 | CPU_387_FLAGS, 0 }, |
1848e567 L |
1025 | { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN, |
1026 | CPU_687_FLAGS, 0 }, | |
d871f3f4 L |
1027 | { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN, |
1028 | CPU_CMOV_FLAGS, 0 }, | |
1029 | { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN, | |
1030 | CPU_FXSR_FLAGS, 0 }, | |
8a2c8fef | 1031 | { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1032 | CPU_MMX_FLAGS, 0 }, |
8a2c8fef | 1033 | { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, |
293f5f65 | 1034 | CPU_SSE_FLAGS, 0 }, |
8a2c8fef | 1035 | { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, |
293f5f65 | 1036 | CPU_SSE2_FLAGS, 0 }, |
8a2c8fef | 1037 | { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 1038 | CPU_SSE3_FLAGS, 0 }, |
af5c13b0 L |
1039 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
1040 | CPU_SSE4A_FLAGS, 0 }, | |
8a2c8fef | 1041 | { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 1042 | CPU_SSSE3_FLAGS, 0 }, |
8a2c8fef | 1043 | { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1044 | CPU_SSE4_1_FLAGS, 0 }, |
8a2c8fef | 1045 | { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, |
293f5f65 | 1046 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 1047 | { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, |
293f5f65 | 1048 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 1049 | { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1050 | CPU_AVX_FLAGS, 0 }, |
6c30d220 | 1051 | { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, |
293f5f65 | 1052 | CPU_AVX2_FLAGS, 0 }, |
43234a1e | 1053 | { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN, |
293f5f65 | 1054 | CPU_AVX512F_FLAGS, 0 }, |
43234a1e | 1055 | { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN, |
293f5f65 | 1056 | CPU_AVX512CD_FLAGS, 0 }, |
43234a1e | 1057 | { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN, |
293f5f65 | 1058 | CPU_AVX512ER_FLAGS, 0 }, |
43234a1e | 1059 | { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN, |
293f5f65 | 1060 | CPU_AVX512PF_FLAGS, 0 }, |
1dfc6506 | 1061 | { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN, |
293f5f65 | 1062 | CPU_AVX512DQ_FLAGS, 0 }, |
1dfc6506 | 1063 | { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN, |
293f5f65 | 1064 | CPU_AVX512BW_FLAGS, 0 }, |
1dfc6506 | 1065 | { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN, |
293f5f65 | 1066 | CPU_AVX512VL_FLAGS, 0 }, |
8a2c8fef | 1067 | { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1068 | CPU_VMX_FLAGS, 0 }, |
8729a6f6 | 1069 | { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, |
293f5f65 | 1070 | CPU_VMFUNC_FLAGS, 0 }, |
8a2c8fef | 1071 | { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1072 | CPU_SMX_FLAGS, 0 }, |
8a2c8fef | 1073 | { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, |
293f5f65 | 1074 | CPU_XSAVE_FLAGS, 0 }, |
c7b8aa3a | 1075 | { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1076 | CPU_XSAVEOPT_FLAGS, 0 }, |
1dfc6506 | 1077 | { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN, |
293f5f65 | 1078 | CPU_XSAVEC_FLAGS, 0 }, |
1dfc6506 | 1079 | { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN, |
293f5f65 | 1080 | CPU_XSAVES_FLAGS, 0 }, |
8a2c8fef | 1081 | { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, |
293f5f65 | 1082 | CPU_AES_FLAGS, 0 }, |
8a2c8fef | 1083 | { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 1084 | CPU_PCLMUL_FLAGS, 0 }, |
8a2c8fef | 1085 | { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 1086 | CPU_PCLMUL_FLAGS, 1 }, |
c7b8aa3a | 1087 | { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, |
293f5f65 | 1088 | CPU_FSGSBASE_FLAGS, 0 }, |
c7b8aa3a | 1089 | { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, |
293f5f65 | 1090 | CPU_RDRND_FLAGS, 0 }, |
c7b8aa3a | 1091 | { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, |
293f5f65 | 1092 | CPU_F16C_FLAGS, 0 }, |
6c30d220 | 1093 | { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, |
293f5f65 | 1094 | CPU_BMI2_FLAGS, 0 }, |
8a2c8fef | 1095 | { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, |
293f5f65 | 1096 | CPU_FMA_FLAGS, 0 }, |
8a2c8fef | 1097 | { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, |
293f5f65 | 1098 | CPU_FMA4_FLAGS, 0 }, |
8a2c8fef | 1099 | { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, |
293f5f65 | 1100 | CPU_XOP_FLAGS, 0 }, |
8a2c8fef | 1101 | { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, |
293f5f65 | 1102 | CPU_LWP_FLAGS, 0 }, |
8a2c8fef | 1103 | { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, |
293f5f65 | 1104 | CPU_MOVBE_FLAGS, 0 }, |
60aa667e | 1105 | { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN, |
293f5f65 | 1106 | CPU_CX16_FLAGS, 0 }, |
8a2c8fef | 1107 | { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, |
293f5f65 | 1108 | CPU_EPT_FLAGS, 0 }, |
6c30d220 | 1109 | { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1110 | CPU_LZCNT_FLAGS, 0 }, |
272a84b1 L |
1111 | { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN, |
1112 | CPU_POPCNT_FLAGS, 0 }, | |
42164a71 | 1113 | { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, |
293f5f65 | 1114 | CPU_HLE_FLAGS, 0 }, |
42164a71 | 1115 | { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1116 | CPU_RTM_FLAGS, 0 }, |
6c30d220 | 1117 | { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, |
293f5f65 | 1118 | CPU_INVPCID_FLAGS, 0 }, |
8a2c8fef | 1119 | { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, |
293f5f65 | 1120 | CPU_CLFLUSH_FLAGS, 0 }, |
22109423 | 1121 | { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, |
293f5f65 | 1122 | CPU_NOP_FLAGS, 0 }, |
8a2c8fef | 1123 | { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, |
293f5f65 | 1124 | CPU_SYSCALL_FLAGS, 0 }, |
8a2c8fef | 1125 | { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, |
293f5f65 | 1126 | CPU_RDTSCP_FLAGS, 0 }, |
8a2c8fef | 1127 | { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, |
293f5f65 | 1128 | CPU_3DNOW_FLAGS, 0 }, |
8a2c8fef | 1129 | { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, |
293f5f65 | 1130 | CPU_3DNOWA_FLAGS, 0 }, |
8a2c8fef | 1131 | { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, |
293f5f65 | 1132 | CPU_PADLOCK_FLAGS, 0 }, |
8a2c8fef | 1133 | { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, |
293f5f65 | 1134 | CPU_SVME_FLAGS, 1 }, |
8a2c8fef | 1135 | { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, |
293f5f65 | 1136 | CPU_SVME_FLAGS, 0 }, |
8a2c8fef | 1137 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
293f5f65 | 1138 | CPU_SSE4A_FLAGS, 0 }, |
8a2c8fef | 1139 | { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1140 | CPU_ABM_FLAGS, 0 }, |
87973e9f | 1141 | { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 1142 | CPU_BMI_FLAGS, 0 }, |
2a2a0f38 | 1143 | { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1144 | CPU_TBM_FLAGS, 0 }, |
e2e1fcde | 1145 | { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1146 | CPU_ADX_FLAGS, 0 }, |
e2e1fcde | 1147 | { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, |
293f5f65 | 1148 | CPU_RDSEED_FLAGS, 0 }, |
e2e1fcde | 1149 | { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, |
293f5f65 | 1150 | CPU_PRFCHW_FLAGS, 0 }, |
5c111e37 | 1151 | { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN, |
293f5f65 | 1152 | CPU_SMAP_FLAGS, 0 }, |
7e8b059b | 1153 | { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1154 | CPU_MPX_FLAGS, 0 }, |
a0046408 | 1155 | { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN, |
293f5f65 | 1156 | CPU_SHA_FLAGS, 0 }, |
963f3586 | 1157 | { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1158 | CPU_CLFLUSHOPT_FLAGS, 0 }, |
dcf893b5 | 1159 | { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1160 | CPU_PREFETCHWT1_FLAGS, 0 }, |
2cf200a4 | 1161 | { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1162 | CPU_SE1_FLAGS, 0 }, |
c5e7287a | 1163 | { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN, |
293f5f65 | 1164 | CPU_CLWB_FLAGS, 0 }, |
2cc1b5aa | 1165 | { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN, |
293f5f65 | 1166 | CPU_AVX512IFMA_FLAGS, 0 }, |
14f195c9 | 1167 | { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 1168 | CPU_AVX512VBMI_FLAGS, 0 }, |
920d2ddc IT |
1169 | { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN, |
1170 | CPU_AVX512_4FMAPS_FLAGS, 0 }, | |
47acf0bd IT |
1171 | { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN, |
1172 | CPU_AVX512_4VNNIW_FLAGS, 0 }, | |
620214f7 IT |
1173 | { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN, |
1174 | CPU_AVX512_VPOPCNTDQ_FLAGS, 0 }, | |
53467f57 IT |
1175 | { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN, |
1176 | CPU_AVX512_VBMI2_FLAGS, 0 }, | |
8cfcb765 IT |
1177 | { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN, |
1178 | CPU_AVX512_VNNI_FLAGS, 0 }, | |
ee6872be IT |
1179 | { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN, |
1180 | CPU_AVX512_BITALG_FLAGS, 0 }, | |
029f3522 | 1181 | { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN, |
293f5f65 | 1182 | CPU_CLZERO_FLAGS, 0 }, |
9916071f | 1183 | { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1184 | CPU_MWAITX_FLAGS, 0 }, |
8eab4136 | 1185 | { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN, |
293f5f65 | 1186 | CPU_OSPKE_FLAGS, 0 }, |
8bc52696 | 1187 | { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN, |
293f5f65 | 1188 | CPU_RDPID_FLAGS, 0 }, |
6b40c462 L |
1189 | { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN, |
1190 | CPU_PTWRITE_FLAGS, 0 }, | |
d777820b IT |
1191 | { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN, |
1192 | CPU_IBT_FLAGS, 0 }, | |
1193 | { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN, | |
1194 | CPU_SHSTK_FLAGS, 0 }, | |
48521003 IT |
1195 | { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN, |
1196 | CPU_GFNI_FLAGS, 0 }, | |
8dcf1fad IT |
1197 | { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN, |
1198 | CPU_VAES_FLAGS, 0 }, | |
ff1982d5 IT |
1199 | { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN, |
1200 | CPU_VPCLMULQDQ_FLAGS, 0 }, | |
3233d7d0 IT |
1201 | { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN, |
1202 | CPU_WBNOINVD_FLAGS, 0 }, | |
be3a8dca IT |
1203 | { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN, |
1204 | CPU_PCONFIG_FLAGS, 0 }, | |
de89d0a3 IT |
1205 | { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN, |
1206 | CPU_WAITPKG_FLAGS, 0 }, | |
c48935d7 IT |
1207 | { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN, |
1208 | CPU_CLDEMOTE_FLAGS, 0 }, | |
260cd341 LC |
1209 | { STRING_COMMA_LEN (".amx_int8"), PROCESSOR_UNKNOWN, |
1210 | CPU_AMX_INT8_FLAGS, 0 }, | |
1211 | { STRING_COMMA_LEN (".amx_bf16"), PROCESSOR_UNKNOWN, | |
1212 | CPU_AMX_BF16_FLAGS, 0 }, | |
1213 | { STRING_COMMA_LEN (".amx_tile"), PROCESSOR_UNKNOWN, | |
1214 | CPU_AMX_TILE_FLAGS, 0 }, | |
c0a30a9f L |
1215 | { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN, |
1216 | CPU_MOVDIRI_FLAGS, 0 }, | |
1217 | { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN, | |
1218 | CPU_MOVDIR64B_FLAGS, 0 }, | |
d6aab7a1 XG |
1219 | { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN, |
1220 | CPU_AVX512_BF16_FLAGS, 0 }, | |
9186c494 L |
1221 | { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN, |
1222 | CPU_AVX512_VP2INTERSECT_FLAGS, 0 }, | |
dd455cf5 L |
1223 | { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN, |
1224 | CPU_ENQCMD_FLAGS, 0 }, | |
4b27d27c L |
1225 | { STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN, |
1226 | CPU_SERIALIZE_FLAGS, 0 }, | |
142861df JB |
1227 | { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN, |
1228 | CPU_RDPRU_FLAGS, 0 }, | |
1229 | { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN, | |
1230 | CPU_MCOMMIT_FLAGS, 0 }, | |
a847e322 JB |
1231 | { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN, |
1232 | CPU_SEV_ES_FLAGS, 0 }, | |
bb651e8b CL |
1233 | { STRING_COMMA_LEN (".tsxldtrk"), PROCESSOR_UNKNOWN, |
1234 | CPU_TSXLDTRK_FLAGS, 0 }, | |
293f5f65 L |
1235 | }; |
1236 | ||
1237 | static const noarch_entry cpu_noarch[] = | |
1238 | { | |
1239 | { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS }, | |
1848e567 L |
1240 | { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS }, |
1241 | { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS }, | |
1242 | { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS }, | |
d871f3f4 L |
1243 | { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS }, |
1244 | { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS }, | |
293f5f65 L |
1245 | { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS }, |
1246 | { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS }, | |
1848e567 L |
1247 | { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS }, |
1248 | { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS }, | |
af5c13b0 | 1249 | { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS }, |
1848e567 L |
1250 | { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS }, |
1251 | { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS }, | |
1252 | { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS }, | |
af5c13b0 | 1253 | { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS }, |
293f5f65 | 1254 | { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS }, |
1848e567 | 1255 | { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS }, |
144b71e2 L |
1256 | { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS }, |
1257 | { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS }, | |
1258 | { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS }, | |
1259 | { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS }, | |
1260 | { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS }, | |
1261 | { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS }, | |
1262 | { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS }, | |
1263 | { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS }, | |
1264 | { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS }, | |
920d2ddc | 1265 | { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS }, |
47acf0bd | 1266 | { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS }, |
620214f7 | 1267 | { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS }, |
53467f57 | 1268 | { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS }, |
8cfcb765 | 1269 | { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS }, |
ee6872be | 1270 | { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS }, |
d777820b IT |
1271 | { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS }, |
1272 | { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS }, | |
260cd341 LC |
1273 | { STRING_COMMA_LEN ("noamx_int8"), CPU_ANY_AMX_INT8_FLAGS }, |
1274 | { STRING_COMMA_LEN ("noamx_bf16"), CPU_ANY_AMX_BF16_FLAGS }, | |
1275 | { STRING_COMMA_LEN ("noamx_tile"), CPU_ANY_AMX_TILE_FLAGS }, | |
c0a30a9f L |
1276 | { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS }, |
1277 | { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS }, | |
d6aab7a1 | 1278 | { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS }, |
708a2fff CL |
1279 | { STRING_COMMA_LEN ("noavx512_vp2intersect"), |
1280 | CPU_ANY_AVX512_VP2INTERSECT_FLAGS }, | |
dd455cf5 | 1281 | { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS }, |
4b27d27c | 1282 | { STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS }, |
bb651e8b | 1283 | { STRING_COMMA_LEN ("notsxldtrk"), CPU_ANY_TSXLDTRK_FLAGS }, |
e413e4e9 AM |
1284 | }; |
1285 | ||
704209c0 | 1286 | #ifdef I386COFF |
a6c24e68 NC |
1287 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
1288 | is allowed to be optional. */ | |
1289 | ||
1290 | static symbolS * | |
1291 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
1292 | { | |
1293 | addressT align = 0; | |
1294 | ||
1295 | SKIP_WHITESPACE (); | |
1296 | ||
7ab9ffdd | 1297 | if (needs_align |
a6c24e68 NC |
1298 | && *input_line_pointer == ',') |
1299 | { | |
1300 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 1301 | |
a6c24e68 NC |
1302 | if (align == (addressT) -1) |
1303 | return NULL; | |
1304 | } | |
1305 | else | |
1306 | { | |
1307 | if (size >= 8) | |
1308 | align = 3; | |
1309 | else if (size >= 4) | |
1310 | align = 2; | |
1311 | else if (size >= 2) | |
1312 | align = 1; | |
1313 | else | |
1314 | align = 0; | |
1315 | } | |
1316 | ||
1317 | bss_alloc (symbolP, size, align); | |
1318 | return symbolP; | |
1319 | } | |
1320 | ||
704209c0 | 1321 | static void |
a6c24e68 NC |
1322 | pe_lcomm (int needs_align) |
1323 | { | |
1324 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
1325 | } | |
704209c0 | 1326 | #endif |
a6c24e68 | 1327 | |
29b0f896 AM |
1328 | const pseudo_typeS md_pseudo_table[] = |
1329 | { | |
1330 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
1331 | {"align", s_align_bytes, 0}, | |
1332 | #else | |
1333 | {"align", s_align_ptwo, 0}, | |
1334 | #endif | |
1335 | {"arch", set_cpu_arch, 0}, | |
1336 | #ifndef I386COFF | |
1337 | {"bss", s_bss, 0}, | |
a6c24e68 NC |
1338 | #else |
1339 | {"lcomm", pe_lcomm, 1}, | |
29b0f896 AM |
1340 | #endif |
1341 | {"ffloat", float_cons, 'f'}, | |
1342 | {"dfloat", float_cons, 'd'}, | |
1343 | {"tfloat", float_cons, 'x'}, | |
1344 | {"value", cons, 2}, | |
d182319b | 1345 | {"slong", signed_cons, 4}, |
29b0f896 AM |
1346 | {"noopt", s_ignore, 0}, |
1347 | {"optim", s_ignore, 0}, | |
1348 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
1349 | {"code16", set_code_flag, CODE_16BIT}, | |
1350 | {"code32", set_code_flag, CODE_32BIT}, | |
da5f19a2 | 1351 | #ifdef BFD64 |
29b0f896 | 1352 | {"code64", set_code_flag, CODE_64BIT}, |
da5f19a2 | 1353 | #endif |
29b0f896 AM |
1354 | {"intel_syntax", set_intel_syntax, 1}, |
1355 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
1356 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
1357 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
1358 | {"allow_index_reg", set_allow_index_reg, 1}, |
1359 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
7bab8ab5 JB |
1360 | {"sse_check", set_check, 0}, |
1361 | {"operand_check", set_check, 1}, | |
3b22753a L |
1362 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1363 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 1364 | #else |
68d20676 | 1365 | {"file", dwarf2_directive_file, 0}, |
07a53e5c RH |
1366 | {"loc", dwarf2_directive_loc, 0}, |
1367 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 1368 | #endif |
6482c264 NC |
1369 | #ifdef TE_PE |
1370 | {"secrel32", pe_directive_secrel, 0}, | |
1371 | #endif | |
29b0f896 AM |
1372 | {0, 0, 0} |
1373 | }; | |
1374 | ||
1375 | /* For interface with expression (). */ | |
1376 | extern char *input_line_pointer; | |
1377 | ||
1378 | /* Hash table for instruction mnemonic lookup. */ | |
1379 | static struct hash_control *op_hash; | |
1380 | ||
1381 | /* Hash table for register lookup. */ | |
1382 | static struct hash_control *reg_hash; | |
1383 | \f | |
ce8a8b2f AM |
1384 | /* Various efficient no-op patterns for aligning code labels. |
1385 | Note: Don't try to assemble the instructions in the comments. | |
1386 | 0L and 0w are not legal. */ | |
62a02d25 L |
1387 | static const unsigned char f32_1[] = |
1388 | {0x90}; /* nop */ | |
1389 | static const unsigned char f32_2[] = | |
1390 | {0x66,0x90}; /* xchg %ax,%ax */ | |
1391 | static const unsigned char f32_3[] = | |
1392 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
1393 | static const unsigned char f32_4[] = | |
1394 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
62a02d25 L |
1395 | static const unsigned char f32_6[] = |
1396 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
1397 | static const unsigned char f32_7[] = | |
1398 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
62a02d25 | 1399 | static const unsigned char f16_3[] = |
3ae729d5 | 1400 | {0x8d,0x74,0x00}; /* lea 0(%si),%si */ |
62a02d25 | 1401 | static const unsigned char f16_4[] = |
3ae729d5 L |
1402 | {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */ |
1403 | static const unsigned char jump_disp8[] = | |
1404 | {0xeb}; /* jmp disp8 */ | |
1405 | static const unsigned char jump32_disp32[] = | |
1406 | {0xe9}; /* jmp disp32 */ | |
1407 | static const unsigned char jump16_disp32[] = | |
1408 | {0x66,0xe9}; /* jmp disp32 */ | |
62a02d25 L |
1409 | /* 32-bit NOPs patterns. */ |
1410 | static const unsigned char *const f32_patt[] = { | |
3ae729d5 | 1411 | f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7 |
62a02d25 L |
1412 | }; |
1413 | /* 16-bit NOPs patterns. */ | |
1414 | static const unsigned char *const f16_patt[] = { | |
3ae729d5 | 1415 | f32_1, f32_2, f16_3, f16_4 |
62a02d25 L |
1416 | }; |
1417 | /* nopl (%[re]ax) */ | |
1418 | static const unsigned char alt_3[] = | |
1419 | {0x0f,0x1f,0x00}; | |
1420 | /* nopl 0(%[re]ax) */ | |
1421 | static const unsigned char alt_4[] = | |
1422 | {0x0f,0x1f,0x40,0x00}; | |
1423 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
1424 | static const unsigned char alt_5[] = | |
1425 | {0x0f,0x1f,0x44,0x00,0x00}; | |
1426 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
1427 | static const unsigned char alt_6[] = | |
1428 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
1429 | /* nopl 0L(%[re]ax) */ | |
1430 | static const unsigned char alt_7[] = | |
1431 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
1432 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
1433 | static const unsigned char alt_8[] = | |
1434 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1435 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
1436 | static const unsigned char alt_9[] = | |
1437 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1438 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
1439 | static const unsigned char alt_10[] = | |
1440 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
3ae729d5 L |
1441 | /* data16 nopw %cs:0L(%eax,%eax,1) */ |
1442 | static const unsigned char alt_11[] = | |
1443 | {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
62a02d25 L |
1444 | /* 32-bit and 64-bit NOPs patterns. */ |
1445 | static const unsigned char *const alt_patt[] = { | |
1446 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
3ae729d5 | 1447 | alt_9, alt_10, alt_11 |
62a02d25 L |
1448 | }; |
1449 | ||
1450 | /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum | |
1451 | size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */ | |
1452 | ||
1453 | static void | |
1454 | i386_output_nops (char *where, const unsigned char *const *patt, | |
1455 | int count, int max_single_nop_size) | |
1456 | ||
1457 | { | |
3ae729d5 L |
1458 | /* Place the longer NOP first. */ |
1459 | int last; | |
1460 | int offset; | |
3076e594 NC |
1461 | const unsigned char *nops; |
1462 | ||
1463 | if (max_single_nop_size < 1) | |
1464 | { | |
1465 | as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"), | |
1466 | max_single_nop_size); | |
1467 | return; | |
1468 | } | |
1469 | ||
1470 | nops = patt[max_single_nop_size - 1]; | |
3ae729d5 L |
1471 | |
1472 | /* Use the smaller one if the requsted one isn't available. */ | |
1473 | if (nops == NULL) | |
62a02d25 | 1474 | { |
3ae729d5 L |
1475 | max_single_nop_size--; |
1476 | nops = patt[max_single_nop_size - 1]; | |
62a02d25 L |
1477 | } |
1478 | ||
3ae729d5 L |
1479 | last = count % max_single_nop_size; |
1480 | ||
1481 | count -= last; | |
1482 | for (offset = 0; offset < count; offset += max_single_nop_size) | |
1483 | memcpy (where + offset, nops, max_single_nop_size); | |
1484 | ||
1485 | if (last) | |
1486 | { | |
1487 | nops = patt[last - 1]; | |
1488 | if (nops == NULL) | |
1489 | { | |
1490 | /* Use the smaller one plus one-byte NOP if the needed one | |
1491 | isn't available. */ | |
1492 | last--; | |
1493 | nops = patt[last - 1]; | |
1494 | memcpy (where + offset, nops, last); | |
1495 | where[offset + last] = *patt[0]; | |
1496 | } | |
1497 | else | |
1498 | memcpy (where + offset, nops, last); | |
1499 | } | |
62a02d25 L |
1500 | } |
1501 | ||
3ae729d5 L |
1502 | static INLINE int |
1503 | fits_in_imm7 (offsetT num) | |
1504 | { | |
1505 | return (num & 0x7f) == num; | |
1506 | } | |
1507 | ||
1508 | static INLINE int | |
1509 | fits_in_imm31 (offsetT num) | |
1510 | { | |
1511 | return (num & 0x7fffffff) == num; | |
1512 | } | |
62a02d25 L |
1513 | |
1514 | /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a | |
1515 | single NOP instruction LIMIT. */ | |
1516 | ||
1517 | void | |
3ae729d5 | 1518 | i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit) |
62a02d25 | 1519 | { |
3ae729d5 | 1520 | const unsigned char *const *patt = NULL; |
62a02d25 | 1521 | int max_single_nop_size; |
3ae729d5 L |
1522 | /* Maximum number of NOPs before switching to jump over NOPs. */ |
1523 | int max_number_of_nops; | |
62a02d25 | 1524 | |
3ae729d5 | 1525 | switch (fragP->fr_type) |
62a02d25 | 1526 | { |
3ae729d5 L |
1527 | case rs_fill_nop: |
1528 | case rs_align_code: | |
1529 | break; | |
e379e5f3 L |
1530 | case rs_machine_dependent: |
1531 | /* Allow NOP padding for jumps and calls. */ | |
1532 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING | |
1533 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
1534 | break; | |
1535 | /* Fall through. */ | |
3ae729d5 | 1536 | default: |
62a02d25 L |
1537 | return; |
1538 | } | |
1539 | ||
ccc9c027 L |
1540 | /* We need to decide which NOP sequence to use for 32bit and |
1541 | 64bit. When -mtune= is used: | |
4eed87de | 1542 | |
76bc74dc L |
1543 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
1544 | PROCESSOR_GENERIC32, f32_patt will be used. | |
80b8656c L |
1545 | 2. For the rest, alt_patt will be used. |
1546 | ||
1547 | When -mtune= isn't used, alt_patt will be used if | |
22109423 | 1548 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will |
76bc74dc | 1549 | be used. |
ccc9c027 L |
1550 | |
1551 | When -march= or .arch is used, we can't use anything beyond | |
1552 | cpu_arch_isa_flags. */ | |
1553 | ||
1554 | if (flag_code == CODE_16BIT) | |
1555 | { | |
3ae729d5 L |
1556 | patt = f16_patt; |
1557 | max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]); | |
1558 | /* Limit number of NOPs to 2 in 16-bit mode. */ | |
1559 | max_number_of_nops = 2; | |
252b5132 | 1560 | } |
33fef721 | 1561 | else |
ccc9c027 | 1562 | { |
fbf3f584 | 1563 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 L |
1564 | { |
1565 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
1566 | switch (cpu_arch_tune) | |
1567 | { | |
1568 | case PROCESSOR_UNKNOWN: | |
1569 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
22109423 L |
1570 | optimize with nops. */ |
1571 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1572 | patt = alt_patt; |
ccc9c027 L |
1573 | else |
1574 | patt = f32_patt; | |
1575 | break; | |
ccc9c027 L |
1576 | case PROCESSOR_PENTIUM4: |
1577 | case PROCESSOR_NOCONA: | |
ef05d495 | 1578 | case PROCESSOR_CORE: |
76bc74dc | 1579 | case PROCESSOR_CORE2: |
bd5295b2 | 1580 | case PROCESSOR_COREI7: |
3632d14b | 1581 | case PROCESSOR_L1OM: |
7a9068fe | 1582 | case PROCESSOR_K1OM: |
76bc74dc | 1583 | case PROCESSOR_GENERIC64: |
ccc9c027 L |
1584 | case PROCESSOR_K6: |
1585 | case PROCESSOR_ATHLON: | |
1586 | case PROCESSOR_K8: | |
4eed87de | 1587 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1588 | case PROCESSOR_BD: |
029f3522 | 1589 | case PROCESSOR_ZNVER: |
7b458c12 | 1590 | case PROCESSOR_BT: |
80b8656c | 1591 | patt = alt_patt; |
ccc9c027 | 1592 | break; |
76bc74dc | 1593 | case PROCESSOR_I386: |
ccc9c027 L |
1594 | case PROCESSOR_I486: |
1595 | case PROCESSOR_PENTIUM: | |
2dde1948 | 1596 | case PROCESSOR_PENTIUMPRO: |
81486035 | 1597 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1598 | case PROCESSOR_GENERIC32: |
1599 | patt = f32_patt; | |
1600 | break; | |
4eed87de | 1601 | } |
ccc9c027 L |
1602 | } |
1603 | else | |
1604 | { | |
fbf3f584 | 1605 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1606 | { |
1607 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1608 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1609 | PROCESSOR_UNKNOWN. */ |
1610 | abort (); | |
1611 | break; | |
1612 | ||
76bc74dc | 1613 | case PROCESSOR_I386: |
ccc9c027 L |
1614 | case PROCESSOR_I486: |
1615 | case PROCESSOR_PENTIUM: | |
81486035 | 1616 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1617 | case PROCESSOR_K6: |
1618 | case PROCESSOR_ATHLON: | |
1619 | case PROCESSOR_K8: | |
4eed87de | 1620 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1621 | case PROCESSOR_BD: |
029f3522 | 1622 | case PROCESSOR_ZNVER: |
7b458c12 | 1623 | case PROCESSOR_BT: |
ccc9c027 L |
1624 | case PROCESSOR_GENERIC32: |
1625 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
22109423 L |
1626 | with nops. */ |
1627 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1628 | patt = alt_patt; |
ccc9c027 L |
1629 | else |
1630 | patt = f32_patt; | |
1631 | break; | |
76bc74dc L |
1632 | case PROCESSOR_PENTIUMPRO: |
1633 | case PROCESSOR_PENTIUM4: | |
1634 | case PROCESSOR_NOCONA: | |
1635 | case PROCESSOR_CORE: | |
ef05d495 | 1636 | case PROCESSOR_CORE2: |
bd5295b2 | 1637 | case PROCESSOR_COREI7: |
3632d14b | 1638 | case PROCESSOR_L1OM: |
7a9068fe | 1639 | case PROCESSOR_K1OM: |
22109423 | 1640 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
80b8656c | 1641 | patt = alt_patt; |
ccc9c027 L |
1642 | else |
1643 | patt = f32_patt; | |
1644 | break; | |
1645 | case PROCESSOR_GENERIC64: | |
80b8656c | 1646 | patt = alt_patt; |
ccc9c027 | 1647 | break; |
4eed87de | 1648 | } |
ccc9c027 L |
1649 | } |
1650 | ||
76bc74dc L |
1651 | if (patt == f32_patt) |
1652 | { | |
3ae729d5 L |
1653 | max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]); |
1654 | /* Limit number of NOPs to 2 for older processors. */ | |
1655 | max_number_of_nops = 2; | |
76bc74dc L |
1656 | } |
1657 | else | |
1658 | { | |
3ae729d5 L |
1659 | max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]); |
1660 | /* Limit number of NOPs to 7 for newer processors. */ | |
1661 | max_number_of_nops = 7; | |
1662 | } | |
1663 | } | |
1664 | ||
1665 | if (limit == 0) | |
1666 | limit = max_single_nop_size; | |
1667 | ||
1668 | if (fragP->fr_type == rs_fill_nop) | |
1669 | { | |
1670 | /* Output NOPs for .nop directive. */ | |
1671 | if (limit > max_single_nop_size) | |
1672 | { | |
1673 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1674 | _("invalid single nop size: %d " | |
1675 | "(expect within [0, %d])"), | |
1676 | limit, max_single_nop_size); | |
1677 | return; | |
1678 | } | |
1679 | } | |
e379e5f3 | 1680 | else if (fragP->fr_type != rs_machine_dependent) |
3ae729d5 L |
1681 | fragP->fr_var = count; |
1682 | ||
1683 | if ((count / max_single_nop_size) > max_number_of_nops) | |
1684 | { | |
1685 | /* Generate jump over NOPs. */ | |
1686 | offsetT disp = count - 2; | |
1687 | if (fits_in_imm7 (disp)) | |
1688 | { | |
1689 | /* Use "jmp disp8" if possible. */ | |
1690 | count = disp; | |
1691 | where[0] = jump_disp8[0]; | |
1692 | where[1] = count; | |
1693 | where += 2; | |
1694 | } | |
1695 | else | |
1696 | { | |
1697 | unsigned int size_of_jump; | |
1698 | ||
1699 | if (flag_code == CODE_16BIT) | |
1700 | { | |
1701 | where[0] = jump16_disp32[0]; | |
1702 | where[1] = jump16_disp32[1]; | |
1703 | size_of_jump = 2; | |
1704 | } | |
1705 | else | |
1706 | { | |
1707 | where[0] = jump32_disp32[0]; | |
1708 | size_of_jump = 1; | |
1709 | } | |
1710 | ||
1711 | count -= size_of_jump + 4; | |
1712 | if (!fits_in_imm31 (count)) | |
1713 | { | |
1714 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1715 | _("jump over nop padding out of range")); | |
1716 | return; | |
1717 | } | |
1718 | ||
1719 | md_number_to_chars (where + size_of_jump, count, 4); | |
1720 | where += size_of_jump + 4; | |
76bc74dc | 1721 | } |
ccc9c027 | 1722 | } |
3ae729d5 L |
1723 | |
1724 | /* Generate multiple NOPs. */ | |
1725 | i386_output_nops (where, patt, count, limit); | |
252b5132 RH |
1726 | } |
1727 | ||
c6fb90c8 | 1728 | static INLINE int |
0dfbf9d7 | 1729 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1730 | { |
0dfbf9d7 | 1731 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1732 | { |
1733 | case 3: | |
0dfbf9d7 | 1734 | if (x->array[2]) |
c6fb90c8 | 1735 | return 0; |
1a0670f3 | 1736 | /* Fall through. */ |
c6fb90c8 | 1737 | case 2: |
0dfbf9d7 | 1738 | if (x->array[1]) |
c6fb90c8 | 1739 | return 0; |
1a0670f3 | 1740 | /* Fall through. */ |
c6fb90c8 | 1741 | case 1: |
0dfbf9d7 | 1742 | return !x->array[0]; |
c6fb90c8 L |
1743 | default: |
1744 | abort (); | |
1745 | } | |
40fb9820 L |
1746 | } |
1747 | ||
c6fb90c8 | 1748 | static INLINE void |
0dfbf9d7 | 1749 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1750 | { |
0dfbf9d7 | 1751 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1752 | { |
1753 | case 3: | |
0dfbf9d7 | 1754 | x->array[2] = v; |
1a0670f3 | 1755 | /* Fall through. */ |
c6fb90c8 | 1756 | case 2: |
0dfbf9d7 | 1757 | x->array[1] = v; |
1a0670f3 | 1758 | /* Fall through. */ |
c6fb90c8 | 1759 | case 1: |
0dfbf9d7 | 1760 | x->array[0] = v; |
1a0670f3 | 1761 | /* Fall through. */ |
c6fb90c8 L |
1762 | break; |
1763 | default: | |
1764 | abort (); | |
1765 | } | |
bab6aec1 JB |
1766 | |
1767 | x->bitfield.class = ClassNone; | |
75e5731b | 1768 | x->bitfield.instance = InstanceNone; |
c6fb90c8 | 1769 | } |
40fb9820 | 1770 | |
c6fb90c8 | 1771 | static INLINE int |
0dfbf9d7 L |
1772 | operand_type_equal (const union i386_operand_type *x, |
1773 | const union i386_operand_type *y) | |
c6fb90c8 | 1774 | { |
0dfbf9d7 | 1775 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1776 | { |
1777 | case 3: | |
0dfbf9d7 | 1778 | if (x->array[2] != y->array[2]) |
c6fb90c8 | 1779 | return 0; |
1a0670f3 | 1780 | /* Fall through. */ |
c6fb90c8 | 1781 | case 2: |
0dfbf9d7 | 1782 | if (x->array[1] != y->array[1]) |
c6fb90c8 | 1783 | return 0; |
1a0670f3 | 1784 | /* Fall through. */ |
c6fb90c8 | 1785 | case 1: |
0dfbf9d7 | 1786 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1787 | break; |
1788 | default: | |
1789 | abort (); | |
1790 | } | |
1791 | } | |
40fb9820 | 1792 | |
0dfbf9d7 L |
1793 | static INLINE int |
1794 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1795 | { | |
1796 | switch (ARRAY_SIZE(x->array)) | |
1797 | { | |
53467f57 IT |
1798 | case 4: |
1799 | if (x->array[3]) | |
1800 | return 0; | |
1801 | /* Fall through. */ | |
0dfbf9d7 L |
1802 | case 3: |
1803 | if (x->array[2]) | |
1804 | return 0; | |
1a0670f3 | 1805 | /* Fall through. */ |
0dfbf9d7 L |
1806 | case 2: |
1807 | if (x->array[1]) | |
1808 | return 0; | |
1a0670f3 | 1809 | /* Fall through. */ |
0dfbf9d7 L |
1810 | case 1: |
1811 | return !x->array[0]; | |
1812 | default: | |
1813 | abort (); | |
1814 | } | |
1815 | } | |
1816 | ||
0dfbf9d7 L |
1817 | static INLINE int |
1818 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1819 | const union i386_cpu_flags *y) | |
1820 | { | |
1821 | switch (ARRAY_SIZE(x->array)) | |
1822 | { | |
53467f57 IT |
1823 | case 4: |
1824 | if (x->array[3] != y->array[3]) | |
1825 | return 0; | |
1826 | /* Fall through. */ | |
0dfbf9d7 L |
1827 | case 3: |
1828 | if (x->array[2] != y->array[2]) | |
1829 | return 0; | |
1a0670f3 | 1830 | /* Fall through. */ |
0dfbf9d7 L |
1831 | case 2: |
1832 | if (x->array[1] != y->array[1]) | |
1833 | return 0; | |
1a0670f3 | 1834 | /* Fall through. */ |
0dfbf9d7 L |
1835 | case 1: |
1836 | return x->array[0] == y->array[0]; | |
1837 | break; | |
1838 | default: | |
1839 | abort (); | |
1840 | } | |
1841 | } | |
c6fb90c8 L |
1842 | |
1843 | static INLINE int | |
1844 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1845 | { | |
1846 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1847 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1848 | } |
1849 | ||
c6fb90c8 L |
1850 | static INLINE i386_cpu_flags |
1851 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1852 | { |
c6fb90c8 L |
1853 | switch (ARRAY_SIZE (x.array)) |
1854 | { | |
53467f57 IT |
1855 | case 4: |
1856 | x.array [3] &= y.array [3]; | |
1857 | /* Fall through. */ | |
c6fb90c8 L |
1858 | case 3: |
1859 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1860 | /* Fall through. */ |
c6fb90c8 L |
1861 | case 2: |
1862 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1863 | /* Fall through. */ |
c6fb90c8 L |
1864 | case 1: |
1865 | x.array [0] &= y.array [0]; | |
1866 | break; | |
1867 | default: | |
1868 | abort (); | |
1869 | } | |
1870 | return x; | |
1871 | } | |
40fb9820 | 1872 | |
c6fb90c8 L |
1873 | static INLINE i386_cpu_flags |
1874 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1875 | { |
c6fb90c8 | 1876 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1877 | { |
53467f57 IT |
1878 | case 4: |
1879 | x.array [3] |= y.array [3]; | |
1880 | /* Fall through. */ | |
c6fb90c8 L |
1881 | case 3: |
1882 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1883 | /* Fall through. */ |
c6fb90c8 L |
1884 | case 2: |
1885 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1886 | /* Fall through. */ |
c6fb90c8 L |
1887 | case 1: |
1888 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1889 | break; |
1890 | default: | |
1891 | abort (); | |
1892 | } | |
40fb9820 L |
1893 | return x; |
1894 | } | |
1895 | ||
309d3373 JB |
1896 | static INLINE i386_cpu_flags |
1897 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1898 | { | |
1899 | switch (ARRAY_SIZE (x.array)) | |
1900 | { | |
53467f57 IT |
1901 | case 4: |
1902 | x.array [3] &= ~y.array [3]; | |
1903 | /* Fall through. */ | |
309d3373 JB |
1904 | case 3: |
1905 | x.array [2] &= ~y.array [2]; | |
1a0670f3 | 1906 | /* Fall through. */ |
309d3373 JB |
1907 | case 2: |
1908 | x.array [1] &= ~y.array [1]; | |
1a0670f3 | 1909 | /* Fall through. */ |
309d3373 JB |
1910 | case 1: |
1911 | x.array [0] &= ~y.array [0]; | |
1912 | break; | |
1913 | default: | |
1914 | abort (); | |
1915 | } | |
1916 | return x; | |
1917 | } | |
1918 | ||
6c0946d0 JB |
1919 | static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS; |
1920 | ||
c0f3af97 L |
1921 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1922 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
1923 | ||
c0f3af97 | 1924 | #define CPU_FLAGS_PERFECT_MATCH \ |
db12e14e | 1925 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH) |
c0f3af97 L |
1926 | |
1927 | /* Return CPU flags match bits. */ | |
3629bb00 | 1928 | |
40fb9820 | 1929 | static int |
d3ce72d0 | 1930 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1931 | { |
c0f3af97 L |
1932 | i386_cpu_flags x = t->cpu_flags; |
1933 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; | |
40fb9820 L |
1934 | |
1935 | x.bitfield.cpu64 = 0; | |
1936 | x.bitfield.cpuno64 = 0; | |
1937 | ||
0dfbf9d7 | 1938 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1939 | { |
1940 | /* This instruction is available on all archs. */ | |
db12e14e | 1941 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1942 | } |
3629bb00 L |
1943 | else |
1944 | { | |
c0f3af97 | 1945 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1946 | i386_cpu_flags cpu = cpu_arch_flags; |
1947 | ||
ab592e75 JB |
1948 | /* AVX512VL is no standalone feature - match it and then strip it. */ |
1949 | if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl) | |
1950 | return match; | |
1951 | x.bitfield.cpuavx512vl = 0; | |
1952 | ||
3629bb00 | 1953 | cpu = cpu_flags_and (x, cpu); |
c0f3af97 L |
1954 | if (!cpu_flags_all_zero (&cpu)) |
1955 | { | |
a5ff0eb2 L |
1956 | if (x.bitfield.cpuavx) |
1957 | { | |
929f69fa | 1958 | /* We need to check a few extra flags with AVX. */ |
b9d49817 | 1959 | if (cpu.bitfield.cpuavx |
40d231b4 JB |
1960 | && (!t->opcode_modifier.sse2avx |
1961 | || (sse2avx && !i.prefix[DATA_PREFIX])) | |
b9d49817 | 1962 | && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) |
929f69fa | 1963 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) |
b9d49817 JB |
1964 | && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul)) |
1965 | match |= CPU_FLAGS_ARCH_MATCH; | |
a5ff0eb2 | 1966 | } |
929f69fa JB |
1967 | else if (x.bitfield.cpuavx512f) |
1968 | { | |
1969 | /* We need to check a few extra flags with AVX512F. */ | |
1970 | if (cpu.bitfield.cpuavx512f | |
1971 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) | |
1972 | && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes) | |
1973 | && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq)) | |
1974 | match |= CPU_FLAGS_ARCH_MATCH; | |
1975 | } | |
a5ff0eb2 | 1976 | else |
db12e14e | 1977 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1978 | } |
3629bb00 | 1979 | } |
c0f3af97 | 1980 | return match; |
40fb9820 L |
1981 | } |
1982 | ||
c6fb90c8 L |
1983 | static INLINE i386_operand_type |
1984 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1985 | { |
bab6aec1 JB |
1986 | if (x.bitfield.class != y.bitfield.class) |
1987 | x.bitfield.class = ClassNone; | |
75e5731b JB |
1988 | if (x.bitfield.instance != y.bitfield.instance) |
1989 | x.bitfield.instance = InstanceNone; | |
bab6aec1 | 1990 | |
c6fb90c8 L |
1991 | switch (ARRAY_SIZE (x.array)) |
1992 | { | |
1993 | case 3: | |
1994 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1995 | /* Fall through. */ |
c6fb90c8 L |
1996 | case 2: |
1997 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1998 | /* Fall through. */ |
c6fb90c8 L |
1999 | case 1: |
2000 | x.array [0] &= y.array [0]; | |
2001 | break; | |
2002 | default: | |
2003 | abort (); | |
2004 | } | |
2005 | return x; | |
40fb9820 L |
2006 | } |
2007 | ||
73053c1f JB |
2008 | static INLINE i386_operand_type |
2009 | operand_type_and_not (i386_operand_type x, i386_operand_type y) | |
2010 | { | |
bab6aec1 | 2011 | gas_assert (y.bitfield.class == ClassNone); |
75e5731b | 2012 | gas_assert (y.bitfield.instance == InstanceNone); |
bab6aec1 | 2013 | |
73053c1f JB |
2014 | switch (ARRAY_SIZE (x.array)) |
2015 | { | |
2016 | case 3: | |
2017 | x.array [2] &= ~y.array [2]; | |
2018 | /* Fall through. */ | |
2019 | case 2: | |
2020 | x.array [1] &= ~y.array [1]; | |
2021 | /* Fall through. */ | |
2022 | case 1: | |
2023 | x.array [0] &= ~y.array [0]; | |
2024 | break; | |
2025 | default: | |
2026 | abort (); | |
2027 | } | |
2028 | return x; | |
2029 | } | |
2030 | ||
c6fb90c8 L |
2031 | static INLINE i386_operand_type |
2032 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 2033 | { |
bab6aec1 JB |
2034 | gas_assert (x.bitfield.class == ClassNone || |
2035 | y.bitfield.class == ClassNone || | |
2036 | x.bitfield.class == y.bitfield.class); | |
75e5731b JB |
2037 | gas_assert (x.bitfield.instance == InstanceNone || |
2038 | y.bitfield.instance == InstanceNone || | |
2039 | x.bitfield.instance == y.bitfield.instance); | |
bab6aec1 | 2040 | |
c6fb90c8 | 2041 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 2042 | { |
c6fb90c8 L |
2043 | case 3: |
2044 | x.array [2] |= y.array [2]; | |
1a0670f3 | 2045 | /* Fall through. */ |
c6fb90c8 L |
2046 | case 2: |
2047 | x.array [1] |= y.array [1]; | |
1a0670f3 | 2048 | /* Fall through. */ |
c6fb90c8 L |
2049 | case 1: |
2050 | x.array [0] |= y.array [0]; | |
40fb9820 L |
2051 | break; |
2052 | default: | |
2053 | abort (); | |
2054 | } | |
c6fb90c8 L |
2055 | return x; |
2056 | } | |
40fb9820 | 2057 | |
c6fb90c8 L |
2058 | static INLINE i386_operand_type |
2059 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
2060 | { | |
bab6aec1 | 2061 | gas_assert (y.bitfield.class == ClassNone); |
75e5731b | 2062 | gas_assert (y.bitfield.instance == InstanceNone); |
bab6aec1 | 2063 | |
c6fb90c8 L |
2064 | switch (ARRAY_SIZE (x.array)) |
2065 | { | |
2066 | case 3: | |
2067 | x.array [2] ^= y.array [2]; | |
1a0670f3 | 2068 | /* Fall through. */ |
c6fb90c8 L |
2069 | case 2: |
2070 | x.array [1] ^= y.array [1]; | |
1a0670f3 | 2071 | /* Fall through. */ |
c6fb90c8 L |
2072 | case 1: |
2073 | x.array [0] ^= y.array [0]; | |
2074 | break; | |
2075 | default: | |
2076 | abort (); | |
2077 | } | |
40fb9820 L |
2078 | return x; |
2079 | } | |
2080 | ||
40fb9820 L |
2081 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; |
2082 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; | |
2083 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; | |
2084 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; | |
bab6aec1 JB |
2085 | static const i386_operand_type anydisp = OPERAND_TYPE_ANYDISP; |
2086 | static const i386_operand_type anyimm = OPERAND_TYPE_ANYIMM; | |
40fb9820 | 2087 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
43234a1e | 2088 | static const i386_operand_type regmask = OPERAND_TYPE_REGMASK; |
40fb9820 L |
2089 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
2090 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; | |
2091 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; | |
2092 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
2093 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
2094 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; | |
2095 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; | |
2096 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
2097 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
2098 | ||
2099 | enum operand_type | |
2100 | { | |
2101 | reg, | |
40fb9820 L |
2102 | imm, |
2103 | disp, | |
2104 | anymem | |
2105 | }; | |
2106 | ||
c6fb90c8 | 2107 | static INLINE int |
40fb9820 L |
2108 | operand_type_check (i386_operand_type t, enum operand_type c) |
2109 | { | |
2110 | switch (c) | |
2111 | { | |
2112 | case reg: | |
bab6aec1 | 2113 | return t.bitfield.class == Reg; |
40fb9820 | 2114 | |
40fb9820 L |
2115 | case imm: |
2116 | return (t.bitfield.imm8 | |
2117 | || t.bitfield.imm8s | |
2118 | || t.bitfield.imm16 | |
2119 | || t.bitfield.imm32 | |
2120 | || t.bitfield.imm32s | |
2121 | || t.bitfield.imm64); | |
2122 | ||
2123 | case disp: | |
2124 | return (t.bitfield.disp8 | |
2125 | || t.bitfield.disp16 | |
2126 | || t.bitfield.disp32 | |
2127 | || t.bitfield.disp32s | |
2128 | || t.bitfield.disp64); | |
2129 | ||
2130 | case anymem: | |
2131 | return (t.bitfield.disp8 | |
2132 | || t.bitfield.disp16 | |
2133 | || t.bitfield.disp32 | |
2134 | || t.bitfield.disp32s | |
2135 | || t.bitfield.disp64 | |
2136 | || t.bitfield.baseindex); | |
2137 | ||
2138 | default: | |
2139 | abort (); | |
2140 | } | |
2cfe26b6 AM |
2141 | |
2142 | return 0; | |
40fb9820 L |
2143 | } |
2144 | ||
7a54636a L |
2145 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size |
2146 | between operand GIVEN and opeand WANTED for instruction template T. */ | |
5c07affc L |
2147 | |
2148 | static INLINE int | |
7a54636a L |
2149 | match_operand_size (const insn_template *t, unsigned int wanted, |
2150 | unsigned int given) | |
5c07affc | 2151 | { |
3ac21baa JB |
2152 | return !((i.types[given].bitfield.byte |
2153 | && !t->operand_types[wanted].bitfield.byte) | |
2154 | || (i.types[given].bitfield.word | |
2155 | && !t->operand_types[wanted].bitfield.word) | |
2156 | || (i.types[given].bitfield.dword | |
2157 | && !t->operand_types[wanted].bitfield.dword) | |
2158 | || (i.types[given].bitfield.qword | |
2159 | && !t->operand_types[wanted].bitfield.qword) | |
2160 | || (i.types[given].bitfield.tbyte | |
2161 | && !t->operand_types[wanted].bitfield.tbyte)); | |
5c07affc L |
2162 | } |
2163 | ||
dd40ce22 L |
2164 | /* Return 1 if there is no conflict in SIMD register between operand |
2165 | GIVEN and opeand WANTED for instruction template T. */ | |
1b54b8d7 JB |
2166 | |
2167 | static INLINE int | |
dd40ce22 L |
2168 | match_simd_size (const insn_template *t, unsigned int wanted, |
2169 | unsigned int given) | |
1b54b8d7 | 2170 | { |
3ac21baa JB |
2171 | return !((i.types[given].bitfield.xmmword |
2172 | && !t->operand_types[wanted].bitfield.xmmword) | |
2173 | || (i.types[given].bitfield.ymmword | |
2174 | && !t->operand_types[wanted].bitfield.ymmword) | |
2175 | || (i.types[given].bitfield.zmmword | |
260cd341 LC |
2176 | && !t->operand_types[wanted].bitfield.zmmword) |
2177 | || (i.types[given].bitfield.tmmword | |
2178 | && !t->operand_types[wanted].bitfield.tmmword)); | |
1b54b8d7 JB |
2179 | } |
2180 | ||
7a54636a L |
2181 | /* Return 1 if there is no conflict in any size between operand GIVEN |
2182 | and opeand WANTED for instruction template T. */ | |
5c07affc L |
2183 | |
2184 | static INLINE int | |
dd40ce22 L |
2185 | match_mem_size (const insn_template *t, unsigned int wanted, |
2186 | unsigned int given) | |
5c07affc | 2187 | { |
7a54636a | 2188 | return (match_operand_size (t, wanted, given) |
3ac21baa | 2189 | && !((i.types[given].bitfield.unspecified |
af508cb9 | 2190 | && !i.broadcast |
3ac21baa JB |
2191 | && !t->operand_types[wanted].bitfield.unspecified) |
2192 | || (i.types[given].bitfield.fword | |
2193 | && !t->operand_types[wanted].bitfield.fword) | |
1b54b8d7 JB |
2194 | /* For scalar opcode templates to allow register and memory |
2195 | operands at the same time, some special casing is needed | |
d6793fa1 JB |
2196 | here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and |
2197 | down-conversion vpmov*. */ | |
3528c362 | 2198 | || ((t->operand_types[wanted].bitfield.class == RegSIMD |
bc49bfd8 JB |
2199 | && t->operand_types[wanted].bitfield.byte |
2200 | + t->operand_types[wanted].bitfield.word | |
2201 | + t->operand_types[wanted].bitfield.dword | |
2202 | + t->operand_types[wanted].bitfield.qword | |
2203 | > !!t->opcode_modifier.broadcast) | |
3ac21baa JB |
2204 | ? (i.types[given].bitfield.xmmword |
2205 | || i.types[given].bitfield.ymmword | |
2206 | || i.types[given].bitfield.zmmword) | |
2207 | : !match_simd_size(t, wanted, given)))); | |
5c07affc L |
2208 | } |
2209 | ||
3ac21baa JB |
2210 | /* Return value has MATCH_STRAIGHT set if there is no size conflict on any |
2211 | operands for instruction template T, and it has MATCH_REVERSE set if there | |
2212 | is no size conflict on any operands for the template with operands reversed | |
2213 | (and the template allows for reversing in the first place). */ | |
5c07affc | 2214 | |
3ac21baa JB |
2215 | #define MATCH_STRAIGHT 1 |
2216 | #define MATCH_REVERSE 2 | |
2217 | ||
2218 | static INLINE unsigned int | |
d3ce72d0 | 2219 | operand_size_match (const insn_template *t) |
5c07affc | 2220 | { |
3ac21baa | 2221 | unsigned int j, match = MATCH_STRAIGHT; |
5c07affc | 2222 | |
0cfa3eb3 | 2223 | /* Don't check non-absolute jump instructions. */ |
5c07affc | 2224 | if (t->opcode_modifier.jump |
0cfa3eb3 | 2225 | && t->opcode_modifier.jump != JUMP_ABSOLUTE) |
5c07affc L |
2226 | return match; |
2227 | ||
2228 | /* Check memory and accumulator operand size. */ | |
2229 | for (j = 0; j < i.operands; j++) | |
2230 | { | |
3528c362 JB |
2231 | if (i.types[j].bitfield.class != Reg |
2232 | && i.types[j].bitfield.class != RegSIMD | |
601e8564 | 2233 | && t->opcode_modifier.anysize) |
5c07affc L |
2234 | continue; |
2235 | ||
bab6aec1 | 2236 | if (t->operand_types[j].bitfield.class == Reg |
7a54636a | 2237 | && !match_operand_size (t, j, j)) |
5c07affc L |
2238 | { |
2239 | match = 0; | |
2240 | break; | |
2241 | } | |
2242 | ||
3528c362 | 2243 | if (t->operand_types[j].bitfield.class == RegSIMD |
3ac21baa | 2244 | && !match_simd_size (t, j, j)) |
1b54b8d7 JB |
2245 | { |
2246 | match = 0; | |
2247 | break; | |
2248 | } | |
2249 | ||
75e5731b | 2250 | if (t->operand_types[j].bitfield.instance == Accum |
7a54636a | 2251 | && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j))) |
1b54b8d7 JB |
2252 | { |
2253 | match = 0; | |
2254 | break; | |
2255 | } | |
2256 | ||
c48dadc9 | 2257 | if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j)) |
5c07affc L |
2258 | { |
2259 | match = 0; | |
2260 | break; | |
2261 | } | |
2262 | } | |
2263 | ||
3ac21baa | 2264 | if (!t->opcode_modifier.d) |
891edac4 | 2265 | { |
dc1e8a47 | 2266 | mismatch: |
3ac21baa JB |
2267 | if (!match) |
2268 | i.error = operand_size_mismatch; | |
2269 | return match; | |
891edac4 | 2270 | } |
5c07affc L |
2271 | |
2272 | /* Check reverse. */ | |
f5eb1d70 | 2273 | gas_assert (i.operands >= 2 && i.operands <= 3); |
5c07affc | 2274 | |
f5eb1d70 | 2275 | for (j = 0; j < i.operands; j++) |
5c07affc | 2276 | { |
f5eb1d70 JB |
2277 | unsigned int given = i.operands - j - 1; |
2278 | ||
bab6aec1 | 2279 | if (t->operand_types[j].bitfield.class == Reg |
f5eb1d70 | 2280 | && !match_operand_size (t, j, given)) |
891edac4 | 2281 | goto mismatch; |
5c07affc | 2282 | |
3528c362 | 2283 | if (t->operand_types[j].bitfield.class == RegSIMD |
f5eb1d70 | 2284 | && !match_simd_size (t, j, given)) |
dbbc8b7e JB |
2285 | goto mismatch; |
2286 | ||
75e5731b | 2287 | if (t->operand_types[j].bitfield.instance == Accum |
f5eb1d70 JB |
2288 | && (!match_operand_size (t, j, given) |
2289 | || !match_simd_size (t, j, given))) | |
dbbc8b7e JB |
2290 | goto mismatch; |
2291 | ||
f5eb1d70 | 2292 | if ((i.flags[given] & Operand_Mem) && !match_mem_size (t, j, given)) |
891edac4 | 2293 | goto mismatch; |
5c07affc L |
2294 | } |
2295 | ||
3ac21baa | 2296 | return match | MATCH_REVERSE; |
5c07affc L |
2297 | } |
2298 | ||
c6fb90c8 | 2299 | static INLINE int |
40fb9820 L |
2300 | operand_type_match (i386_operand_type overlap, |
2301 | i386_operand_type given) | |
2302 | { | |
2303 | i386_operand_type temp = overlap; | |
2304 | ||
7d5e4556 | 2305 | temp.bitfield.unspecified = 0; |
5c07affc L |
2306 | temp.bitfield.byte = 0; |
2307 | temp.bitfield.word = 0; | |
2308 | temp.bitfield.dword = 0; | |
2309 | temp.bitfield.fword = 0; | |
2310 | temp.bitfield.qword = 0; | |
2311 | temp.bitfield.tbyte = 0; | |
2312 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 2313 | temp.bitfield.ymmword = 0; |
43234a1e | 2314 | temp.bitfield.zmmword = 0; |
260cd341 | 2315 | temp.bitfield.tmmword = 0; |
0dfbf9d7 | 2316 | if (operand_type_all_zero (&temp)) |
891edac4 | 2317 | goto mismatch; |
40fb9820 | 2318 | |
6f2f06be | 2319 | if (given.bitfield.baseindex == overlap.bitfield.baseindex) |
891edac4 L |
2320 | return 1; |
2321 | ||
dc1e8a47 | 2322 | mismatch: |
a65babc9 | 2323 | i.error = operand_type_mismatch; |
891edac4 | 2324 | return 0; |
40fb9820 L |
2325 | } |
2326 | ||
7d5e4556 | 2327 | /* If given types g0 and g1 are registers they must be of the same type |
10c17abd | 2328 | unless the expected operand type register overlap is null. |
5de4d9ef | 2329 | Some Intel syntax memory operand size checking also happens here. */ |
40fb9820 | 2330 | |
c6fb90c8 | 2331 | static INLINE int |
dc821c5f | 2332 | operand_type_register_match (i386_operand_type g0, |
40fb9820 | 2333 | i386_operand_type t0, |
40fb9820 L |
2334 | i386_operand_type g1, |
2335 | i386_operand_type t1) | |
2336 | { | |
bab6aec1 | 2337 | if (g0.bitfield.class != Reg |
3528c362 | 2338 | && g0.bitfield.class != RegSIMD |
10c17abd JB |
2339 | && (!operand_type_check (g0, anymem) |
2340 | || g0.bitfield.unspecified | |
5de4d9ef JB |
2341 | || (t0.bitfield.class != Reg |
2342 | && t0.bitfield.class != RegSIMD))) | |
40fb9820 L |
2343 | return 1; |
2344 | ||
bab6aec1 | 2345 | if (g1.bitfield.class != Reg |
3528c362 | 2346 | && g1.bitfield.class != RegSIMD |
10c17abd JB |
2347 | && (!operand_type_check (g1, anymem) |
2348 | || g1.bitfield.unspecified | |
5de4d9ef JB |
2349 | || (t1.bitfield.class != Reg |
2350 | && t1.bitfield.class != RegSIMD))) | |
40fb9820 L |
2351 | return 1; |
2352 | ||
dc821c5f JB |
2353 | if (g0.bitfield.byte == g1.bitfield.byte |
2354 | && g0.bitfield.word == g1.bitfield.word | |
2355 | && g0.bitfield.dword == g1.bitfield.dword | |
10c17abd JB |
2356 | && g0.bitfield.qword == g1.bitfield.qword |
2357 | && g0.bitfield.xmmword == g1.bitfield.xmmword | |
2358 | && g0.bitfield.ymmword == g1.bitfield.ymmword | |
2359 | && g0.bitfield.zmmword == g1.bitfield.zmmword) | |
40fb9820 L |
2360 | return 1; |
2361 | ||
dc821c5f JB |
2362 | if (!(t0.bitfield.byte & t1.bitfield.byte) |
2363 | && !(t0.bitfield.word & t1.bitfield.word) | |
2364 | && !(t0.bitfield.dword & t1.bitfield.dword) | |
10c17abd JB |
2365 | && !(t0.bitfield.qword & t1.bitfield.qword) |
2366 | && !(t0.bitfield.xmmword & t1.bitfield.xmmword) | |
2367 | && !(t0.bitfield.ymmword & t1.bitfield.ymmword) | |
2368 | && !(t0.bitfield.zmmword & t1.bitfield.zmmword)) | |
891edac4 L |
2369 | return 1; |
2370 | ||
a65babc9 | 2371 | i.error = register_type_mismatch; |
891edac4 L |
2372 | |
2373 | return 0; | |
40fb9820 L |
2374 | } |
2375 | ||
4c692bc7 JB |
2376 | static INLINE unsigned int |
2377 | register_number (const reg_entry *r) | |
2378 | { | |
2379 | unsigned int nr = r->reg_num; | |
2380 | ||
2381 | if (r->reg_flags & RegRex) | |
2382 | nr += 8; | |
2383 | ||
200cbe0f L |
2384 | if (r->reg_flags & RegVRex) |
2385 | nr += 16; | |
2386 | ||
4c692bc7 JB |
2387 | return nr; |
2388 | } | |
2389 | ||
252b5132 | 2390 | static INLINE unsigned int |
40fb9820 | 2391 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 2392 | { |
b5014f7a | 2393 | if (t.bitfield.disp8) |
40fb9820 L |
2394 | return 1; |
2395 | else if (t.bitfield.disp16 | |
2396 | || t.bitfield.disp32 | |
2397 | || t.bitfield.disp32s) | |
2398 | return 2; | |
2399 | else | |
2400 | return 0; | |
252b5132 RH |
2401 | } |
2402 | ||
2403 | static INLINE int | |
65879393 | 2404 | fits_in_signed_byte (addressT num) |
252b5132 | 2405 | { |
65879393 | 2406 | return num + 0x80 <= 0xff; |
47926f60 | 2407 | } |
252b5132 RH |
2408 | |
2409 | static INLINE int | |
65879393 | 2410 | fits_in_unsigned_byte (addressT num) |
252b5132 | 2411 | { |
65879393 | 2412 | return num <= 0xff; |
47926f60 | 2413 | } |
252b5132 RH |
2414 | |
2415 | static INLINE int | |
65879393 | 2416 | fits_in_unsigned_word (addressT num) |
252b5132 | 2417 | { |
65879393 | 2418 | return num <= 0xffff; |
47926f60 | 2419 | } |
252b5132 RH |
2420 | |
2421 | static INLINE int | |
65879393 | 2422 | fits_in_signed_word (addressT num) |
252b5132 | 2423 | { |
65879393 | 2424 | return num + 0x8000 <= 0xffff; |
47926f60 | 2425 | } |
2a962e6d | 2426 | |
3e73aa7c | 2427 | static INLINE int |
65879393 | 2428 | fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2429 | { |
2430 | #ifndef BFD64 | |
2431 | return 1; | |
2432 | #else | |
65879393 | 2433 | return num + 0x80000000 <= 0xffffffff; |
3e73aa7c JH |
2434 | #endif |
2435 | } /* fits_in_signed_long() */ | |
2a962e6d | 2436 | |
3e73aa7c | 2437 | static INLINE int |
65879393 | 2438 | fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2439 | { |
2440 | #ifndef BFD64 | |
2441 | return 1; | |
2442 | #else | |
65879393 | 2443 | return num <= 0xffffffff; |
3e73aa7c JH |
2444 | #endif |
2445 | } /* fits_in_unsigned_long() */ | |
252b5132 | 2446 | |
43234a1e | 2447 | static INLINE int |
b5014f7a | 2448 | fits_in_disp8 (offsetT num) |
43234a1e L |
2449 | { |
2450 | int shift = i.memshift; | |
2451 | unsigned int mask; | |
2452 | ||
2453 | if (shift == -1) | |
2454 | abort (); | |
2455 | ||
2456 | mask = (1 << shift) - 1; | |
2457 | ||
2458 | /* Return 0 if NUM isn't properly aligned. */ | |
2459 | if ((num & mask)) | |
2460 | return 0; | |
2461 | ||
2462 | /* Check if NUM will fit in 8bit after shift. */ | |
2463 | return fits_in_signed_byte (num >> shift); | |
2464 | } | |
2465 | ||
a683cc34 SP |
2466 | static INLINE int |
2467 | fits_in_imm4 (offsetT num) | |
2468 | { | |
2469 | return (num & 0xf) == num; | |
2470 | } | |
2471 | ||
40fb9820 | 2472 | static i386_operand_type |
e3bb37b5 | 2473 | smallest_imm_type (offsetT num) |
252b5132 | 2474 | { |
40fb9820 | 2475 | i386_operand_type t; |
7ab9ffdd | 2476 | |
0dfbf9d7 | 2477 | operand_type_set (&t, 0); |
40fb9820 L |
2478 | t.bitfield.imm64 = 1; |
2479 | ||
2480 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
2481 | { |
2482 | /* This code is disabled on the 486 because all the Imm1 forms | |
2483 | in the opcode table are slower on the i486. They're the | |
2484 | versions with the implicitly specified single-position | |
2485 | displacement, which has another syntax if you really want to | |
2486 | use that form. */ | |
40fb9820 L |
2487 | t.bitfield.imm1 = 1; |
2488 | t.bitfield.imm8 = 1; | |
2489 | t.bitfield.imm8s = 1; | |
2490 | t.bitfield.imm16 = 1; | |
2491 | t.bitfield.imm32 = 1; | |
2492 | t.bitfield.imm32s = 1; | |
2493 | } | |
2494 | else if (fits_in_signed_byte (num)) | |
2495 | { | |
2496 | t.bitfield.imm8 = 1; | |
2497 | t.bitfield.imm8s = 1; | |
2498 | t.bitfield.imm16 = 1; | |
2499 | t.bitfield.imm32 = 1; | |
2500 | t.bitfield.imm32s = 1; | |
2501 | } | |
2502 | else if (fits_in_unsigned_byte (num)) | |
2503 | { | |
2504 | t.bitfield.imm8 = 1; | |
2505 | t.bitfield.imm16 = 1; | |
2506 | t.bitfield.imm32 = 1; | |
2507 | t.bitfield.imm32s = 1; | |
2508 | } | |
2509 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
2510 | { | |
2511 | t.bitfield.imm16 = 1; | |
2512 | t.bitfield.imm32 = 1; | |
2513 | t.bitfield.imm32s = 1; | |
2514 | } | |
2515 | else if (fits_in_signed_long (num)) | |
2516 | { | |
2517 | t.bitfield.imm32 = 1; | |
2518 | t.bitfield.imm32s = 1; | |
2519 | } | |
2520 | else if (fits_in_unsigned_long (num)) | |
2521 | t.bitfield.imm32 = 1; | |
2522 | ||
2523 | return t; | |
47926f60 | 2524 | } |
252b5132 | 2525 | |
847f7ad4 | 2526 | static offsetT |
e3bb37b5 | 2527 | offset_in_range (offsetT val, int size) |
847f7ad4 | 2528 | { |
508866be | 2529 | addressT mask; |
ba2adb93 | 2530 | |
847f7ad4 AM |
2531 | switch (size) |
2532 | { | |
508866be L |
2533 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
2534 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 2535 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
2536 | #ifdef BFD64 |
2537 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
2538 | #endif | |
47926f60 | 2539 | default: abort (); |
847f7ad4 AM |
2540 | } |
2541 | ||
47926f60 | 2542 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
2543 | { |
2544 | char buf1[40], buf2[40]; | |
2545 | ||
2546 | sprint_value (buf1, val); | |
2547 | sprint_value (buf2, val & mask); | |
2548 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
2549 | } | |
2550 | return val & mask; | |
2551 | } | |
2552 | ||
c32fa91d L |
2553 | enum PREFIX_GROUP |
2554 | { | |
2555 | PREFIX_EXIST = 0, | |
2556 | PREFIX_LOCK, | |
2557 | PREFIX_REP, | |
04ef582a | 2558 | PREFIX_DS, |
c32fa91d L |
2559 | PREFIX_OTHER |
2560 | }; | |
2561 | ||
2562 | /* Returns | |
2563 | a. PREFIX_EXIST if attempting to add a prefix where one from the | |
2564 | same class already exists. | |
2565 | b. PREFIX_LOCK if lock prefix is added. | |
2566 | c. PREFIX_REP if rep/repne prefix is added. | |
04ef582a L |
2567 | d. PREFIX_DS if ds prefix is added. |
2568 | e. PREFIX_OTHER if other prefix is added. | |
c32fa91d L |
2569 | */ |
2570 | ||
2571 | static enum PREFIX_GROUP | |
e3bb37b5 | 2572 | add_prefix (unsigned int prefix) |
252b5132 | 2573 | { |
c32fa91d | 2574 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
b1905489 | 2575 | unsigned int q; |
252b5132 | 2576 | |
29b0f896 AM |
2577 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
2578 | && flag_code == CODE_64BIT) | |
b1905489 | 2579 | { |
161a04f6 | 2580 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
44846f29 JB |
2581 | || (i.prefix[REX_PREFIX] & prefix & REX_R) |
2582 | || (i.prefix[REX_PREFIX] & prefix & REX_X) | |
2583 | || (i.prefix[REX_PREFIX] & prefix & REX_B)) | |
c32fa91d | 2584 | ret = PREFIX_EXIST; |
b1905489 JB |
2585 | q = REX_PREFIX; |
2586 | } | |
3e73aa7c | 2587 | else |
b1905489 JB |
2588 | { |
2589 | switch (prefix) | |
2590 | { | |
2591 | default: | |
2592 | abort (); | |
2593 | ||
b1905489 | 2594 | case DS_PREFIX_OPCODE: |
04ef582a L |
2595 | ret = PREFIX_DS; |
2596 | /* Fall through. */ | |
2597 | case CS_PREFIX_OPCODE: | |
b1905489 JB |
2598 | case ES_PREFIX_OPCODE: |
2599 | case FS_PREFIX_OPCODE: | |
2600 | case GS_PREFIX_OPCODE: | |
2601 | case SS_PREFIX_OPCODE: | |
2602 | q = SEG_PREFIX; | |
2603 | break; | |
2604 | ||
2605 | case REPNE_PREFIX_OPCODE: | |
2606 | case REPE_PREFIX_OPCODE: | |
c32fa91d L |
2607 | q = REP_PREFIX; |
2608 | ret = PREFIX_REP; | |
2609 | break; | |
2610 | ||
b1905489 | 2611 | case LOCK_PREFIX_OPCODE: |
c32fa91d L |
2612 | q = LOCK_PREFIX; |
2613 | ret = PREFIX_LOCK; | |
b1905489 JB |
2614 | break; |
2615 | ||
2616 | case FWAIT_OPCODE: | |
2617 | q = WAIT_PREFIX; | |
2618 | break; | |
2619 | ||
2620 | case ADDR_PREFIX_OPCODE: | |
2621 | q = ADDR_PREFIX; | |
2622 | break; | |
2623 | ||
2624 | case DATA_PREFIX_OPCODE: | |
2625 | q = DATA_PREFIX; | |
2626 | break; | |
2627 | } | |
2628 | if (i.prefix[q] != 0) | |
c32fa91d | 2629 | ret = PREFIX_EXIST; |
b1905489 | 2630 | } |
252b5132 | 2631 | |
b1905489 | 2632 | if (ret) |
252b5132 | 2633 | { |
b1905489 JB |
2634 | if (!i.prefix[q]) |
2635 | ++i.prefixes; | |
2636 | i.prefix[q] |= prefix; | |
252b5132 | 2637 | } |
b1905489 JB |
2638 | else |
2639 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 2640 | |
252b5132 RH |
2641 | return ret; |
2642 | } | |
2643 | ||
2644 | static void | |
78f12dd3 | 2645 | update_code_flag (int value, int check) |
eecb386c | 2646 | { |
78f12dd3 L |
2647 | PRINTF_LIKE ((*as_error)); |
2648 | ||
1e9cc1c2 | 2649 | flag_code = (enum flag_code) value; |
40fb9820 L |
2650 | if (flag_code == CODE_64BIT) |
2651 | { | |
2652 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2653 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
2654 | } |
2655 | else | |
2656 | { | |
2657 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2658 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
2659 | } |
2660 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c | 2661 | { |
78f12dd3 L |
2662 | if (check) |
2663 | as_error = as_fatal; | |
2664 | else | |
2665 | as_error = as_bad; | |
2666 | (*as_error) (_("64bit mode not supported on `%s'."), | |
2667 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2668 | } |
40fb9820 | 2669 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c | 2670 | { |
78f12dd3 L |
2671 | if (check) |
2672 | as_error = as_fatal; | |
2673 | else | |
2674 | as_error = as_bad; | |
2675 | (*as_error) (_("32bit mode not supported on `%s'."), | |
2676 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2677 | } |
eecb386c AM |
2678 | stackop_size = '\0'; |
2679 | } | |
2680 | ||
78f12dd3 L |
2681 | static void |
2682 | set_code_flag (int value) | |
2683 | { | |
2684 | update_code_flag (value, 0); | |
2685 | } | |
2686 | ||
eecb386c | 2687 | static void |
e3bb37b5 | 2688 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 2689 | { |
1e9cc1c2 | 2690 | flag_code = (enum flag_code) new_code_flag; |
40fb9820 L |
2691 | if (flag_code != CODE_16BIT) |
2692 | abort (); | |
2693 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2694 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 2695 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
2696 | } |
2697 | ||
2698 | static void | |
e3bb37b5 | 2699 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
2700 | { |
2701 | /* Find out if register prefixing is specified. */ | |
2702 | int ask_naked_reg = 0; | |
2703 | ||
2704 | SKIP_WHITESPACE (); | |
29b0f896 | 2705 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 | 2706 | { |
d02603dc NC |
2707 | char *string; |
2708 | int e = get_symbol_name (&string); | |
252b5132 | 2709 | |
47926f60 | 2710 | if (strcmp (string, "prefix") == 0) |
252b5132 | 2711 | ask_naked_reg = 1; |
47926f60 | 2712 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
2713 | ask_naked_reg = -1; |
2714 | else | |
d0b47220 | 2715 | as_bad (_("bad argument to syntax directive.")); |
d02603dc | 2716 | (void) restore_line_pointer (e); |
252b5132 RH |
2717 | } |
2718 | demand_empty_rest_of_line (); | |
c3332e24 | 2719 | |
252b5132 RH |
2720 | intel_syntax = syntax_flag; |
2721 | ||
2722 | if (ask_naked_reg == 0) | |
f86103b7 AM |
2723 | allow_naked_reg = (intel_syntax |
2724 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
2725 | else |
2726 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 2727 | |
ee86248c | 2728 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
7ab9ffdd | 2729 | |
e4a3b5a4 | 2730 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 2731 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 2732 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
2733 | } |
2734 | ||
1efbbeb4 L |
2735 | static void |
2736 | set_intel_mnemonic (int mnemonic_flag) | |
2737 | { | |
e1d4d893 | 2738 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
2739 | } |
2740 | ||
db51cc60 L |
2741 | static void |
2742 | set_allow_index_reg (int flag) | |
2743 | { | |
2744 | allow_index_reg = flag; | |
2745 | } | |
2746 | ||
cb19c032 | 2747 | static void |
7bab8ab5 | 2748 | set_check (int what) |
cb19c032 | 2749 | { |
7bab8ab5 JB |
2750 | enum check_kind *kind; |
2751 | const char *str; | |
2752 | ||
2753 | if (what) | |
2754 | { | |
2755 | kind = &operand_check; | |
2756 | str = "operand"; | |
2757 | } | |
2758 | else | |
2759 | { | |
2760 | kind = &sse_check; | |
2761 | str = "sse"; | |
2762 | } | |
2763 | ||
cb19c032 L |
2764 | SKIP_WHITESPACE (); |
2765 | ||
2766 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2767 | { | |
d02603dc NC |
2768 | char *string; |
2769 | int e = get_symbol_name (&string); | |
cb19c032 L |
2770 | |
2771 | if (strcmp (string, "none") == 0) | |
7bab8ab5 | 2772 | *kind = check_none; |
cb19c032 | 2773 | else if (strcmp (string, "warning") == 0) |
7bab8ab5 | 2774 | *kind = check_warning; |
cb19c032 | 2775 | else if (strcmp (string, "error") == 0) |
7bab8ab5 | 2776 | *kind = check_error; |
cb19c032 | 2777 | else |
7bab8ab5 | 2778 | as_bad (_("bad argument to %s_check directive."), str); |
d02603dc | 2779 | (void) restore_line_pointer (e); |
cb19c032 L |
2780 | } |
2781 | else | |
7bab8ab5 | 2782 | as_bad (_("missing argument for %s_check directive"), str); |
cb19c032 L |
2783 | |
2784 | demand_empty_rest_of_line (); | |
2785 | } | |
2786 | ||
8a9036a4 L |
2787 | static void |
2788 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1e9cc1c2 | 2789 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
8a9036a4 L |
2790 | { |
2791 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2792 | static const char *arch; | |
2793 | ||
2794 | /* Intel LIOM is only supported on ELF. */ | |
2795 | if (!IS_ELF) | |
2796 | return; | |
2797 | ||
2798 | if (!arch) | |
2799 | { | |
2800 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
2801 | use default_arch. */ | |
2802 | arch = cpu_arch_name; | |
2803 | if (!arch) | |
2804 | arch = default_arch; | |
2805 | } | |
2806 | ||
81486035 L |
2807 | /* If we are targeting Intel MCU, we must enable it. */ |
2808 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU | |
2809 | || new_flag.bitfield.cpuiamcu) | |
2810 | return; | |
2811 | ||
3632d14b | 2812 | /* If we are targeting Intel L1OM, we must enable it. */ |
8a9036a4 | 2813 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM |
1e9cc1c2 | 2814 | || new_flag.bitfield.cpul1om) |
8a9036a4 | 2815 | return; |
76ba9986 | 2816 | |
7a9068fe L |
2817 | /* If we are targeting Intel K1OM, we must enable it. */ |
2818 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM | |
2819 | || new_flag.bitfield.cpuk1om) | |
2820 | return; | |
2821 | ||
8a9036a4 L |
2822 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
2823 | #endif | |
2824 | } | |
2825 | ||
e413e4e9 | 2826 | static void |
e3bb37b5 | 2827 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 2828 | { |
47926f60 | 2829 | SKIP_WHITESPACE (); |
e413e4e9 | 2830 | |
29b0f896 | 2831 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 | 2832 | { |
d02603dc NC |
2833 | char *string; |
2834 | int e = get_symbol_name (&string); | |
91d6fa6a | 2835 | unsigned int j; |
40fb9820 | 2836 | i386_cpu_flags flags; |
e413e4e9 | 2837 | |
91d6fa6a | 2838 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
e413e4e9 | 2839 | { |
91d6fa6a | 2840 | if (strcmp (string, cpu_arch[j].name) == 0) |
e413e4e9 | 2841 | { |
91d6fa6a | 2842 | check_cpu_arch_compatible (string, cpu_arch[j].flags); |
8a9036a4 | 2843 | |
5c6af06e JB |
2844 | if (*string != '.') |
2845 | { | |
91d6fa6a | 2846 | cpu_arch_name = cpu_arch[j].name; |
5c6af06e | 2847 | cpu_sub_arch_name = NULL; |
91d6fa6a | 2848 | cpu_arch_flags = cpu_arch[j].flags; |
40fb9820 L |
2849 | if (flag_code == CODE_64BIT) |
2850 | { | |
2851 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2852 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
2853 | } | |
2854 | else | |
2855 | { | |
2856 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2857 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
2858 | } | |
91d6fa6a NC |
2859 | cpu_arch_isa = cpu_arch[j].type; |
2860 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
ccc9c027 L |
2861 | if (!cpu_arch_tune_set) |
2862 | { | |
2863 | cpu_arch_tune = cpu_arch_isa; | |
2864 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2865 | } | |
5c6af06e JB |
2866 | break; |
2867 | } | |
40fb9820 | 2868 | |
293f5f65 L |
2869 | flags = cpu_flags_or (cpu_arch_flags, |
2870 | cpu_arch[j].flags); | |
81486035 | 2871 | |
5b64d091 | 2872 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
5c6af06e | 2873 | { |
6305a203 L |
2874 | if (cpu_sub_arch_name) |
2875 | { | |
2876 | char *name = cpu_sub_arch_name; | |
2877 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 2878 | cpu_arch[j].name, |
1bf57e9f | 2879 | (const char *) NULL); |
6305a203 L |
2880 | free (name); |
2881 | } | |
2882 | else | |
91d6fa6a | 2883 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
40fb9820 | 2884 | cpu_arch_flags = flags; |
a586129e | 2885 | cpu_arch_isa_flags = flags; |
5c6af06e | 2886 | } |
0089dace L |
2887 | else |
2888 | cpu_arch_isa_flags | |
2889 | = cpu_flags_or (cpu_arch_isa_flags, | |
2890 | cpu_arch[j].flags); | |
d02603dc | 2891 | (void) restore_line_pointer (e); |
5c6af06e JB |
2892 | demand_empty_rest_of_line (); |
2893 | return; | |
e413e4e9 AM |
2894 | } |
2895 | } | |
293f5f65 L |
2896 | |
2897 | if (*string == '.' && j >= ARRAY_SIZE (cpu_arch)) | |
2898 | { | |
33eaf5de | 2899 | /* Disable an ISA extension. */ |
293f5f65 L |
2900 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
2901 | if (strcmp (string + 1, cpu_noarch [j].name) == 0) | |
2902 | { | |
2903 | flags = cpu_flags_and_not (cpu_arch_flags, | |
2904 | cpu_noarch[j].flags); | |
2905 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
2906 | { | |
2907 | if (cpu_sub_arch_name) | |
2908 | { | |
2909 | char *name = cpu_sub_arch_name; | |
2910 | cpu_sub_arch_name = concat (name, string, | |
2911 | (const char *) NULL); | |
2912 | free (name); | |
2913 | } | |
2914 | else | |
2915 | cpu_sub_arch_name = xstrdup (string); | |
2916 | cpu_arch_flags = flags; | |
2917 | cpu_arch_isa_flags = flags; | |
2918 | } | |
2919 | (void) restore_line_pointer (e); | |
2920 | demand_empty_rest_of_line (); | |
2921 | return; | |
2922 | } | |
2923 | ||
2924 | j = ARRAY_SIZE (cpu_arch); | |
2925 | } | |
2926 | ||
91d6fa6a | 2927 | if (j >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
2928 | as_bad (_("no such architecture: `%s'"), string); |
2929 | ||
2930 | *input_line_pointer = e; | |
2931 | } | |
2932 | else | |
2933 | as_bad (_("missing cpu architecture")); | |
2934 | ||
fddf5b5b AM |
2935 | no_cond_jump_promotion = 0; |
2936 | if (*input_line_pointer == ',' | |
29b0f896 | 2937 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b | 2938 | { |
d02603dc NC |
2939 | char *string; |
2940 | char e; | |
2941 | ||
2942 | ++input_line_pointer; | |
2943 | e = get_symbol_name (&string); | |
fddf5b5b AM |
2944 | |
2945 | if (strcmp (string, "nojumps") == 0) | |
2946 | no_cond_jump_promotion = 1; | |
2947 | else if (strcmp (string, "jumps") == 0) | |
2948 | ; | |
2949 | else | |
2950 | as_bad (_("no such architecture modifier: `%s'"), string); | |
2951 | ||
d02603dc | 2952 | (void) restore_line_pointer (e); |
fddf5b5b AM |
2953 | } |
2954 | ||
e413e4e9 AM |
2955 | demand_empty_rest_of_line (); |
2956 | } | |
2957 | ||
8a9036a4 L |
2958 | enum bfd_architecture |
2959 | i386_arch (void) | |
2960 | { | |
3632d14b | 2961 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 L |
2962 | { |
2963 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2964 | || flag_code != CODE_64BIT) | |
2965 | as_fatal (_("Intel L1OM is 64bit ELF only")); | |
2966 | return bfd_arch_l1om; | |
2967 | } | |
7a9068fe L |
2968 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2969 | { | |
2970 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2971 | || flag_code != CODE_64BIT) | |
2972 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2973 | return bfd_arch_k1om; | |
2974 | } | |
81486035 L |
2975 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
2976 | { | |
2977 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2978 | || flag_code == CODE_64BIT) | |
2979 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2980 | return bfd_arch_iamcu; | |
2981 | } | |
8a9036a4 L |
2982 | else |
2983 | return bfd_arch_i386; | |
2984 | } | |
2985 | ||
b9d79e03 | 2986 | unsigned long |
7016a5d5 | 2987 | i386_mach (void) |
b9d79e03 | 2988 | { |
351f65ca | 2989 | if (!strncmp (default_arch, "x86_64", 6)) |
8a9036a4 | 2990 | { |
3632d14b | 2991 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 2992 | { |
351f65ca L |
2993 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
2994 | || default_arch[6] != '\0') | |
8a9036a4 L |
2995 | as_fatal (_("Intel L1OM is 64bit ELF only")); |
2996 | return bfd_mach_l1om; | |
2997 | } | |
7a9068fe L |
2998 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2999 | { | |
3000 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
3001 | || default_arch[6] != '\0') | |
3002 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
3003 | return bfd_mach_k1om; | |
3004 | } | |
351f65ca | 3005 | else if (default_arch[6] == '\0') |
8a9036a4 | 3006 | return bfd_mach_x86_64; |
351f65ca L |
3007 | else |
3008 | return bfd_mach_x64_32; | |
8a9036a4 | 3009 | } |
5197d474 L |
3010 | else if (!strcmp (default_arch, "i386") |
3011 | || !strcmp (default_arch, "iamcu")) | |
81486035 L |
3012 | { |
3013 | if (cpu_arch_isa == PROCESSOR_IAMCU) | |
3014 | { | |
3015 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
3016 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
3017 | return bfd_mach_i386_iamcu; | |
3018 | } | |
3019 | else | |
3020 | return bfd_mach_i386_i386; | |
3021 | } | |
b9d79e03 | 3022 | else |
2b5d6a91 | 3023 | as_fatal (_("unknown architecture")); |
b9d79e03 | 3024 | } |
b9d79e03 | 3025 | \f |
252b5132 | 3026 | void |
7016a5d5 | 3027 | md_begin (void) |
252b5132 RH |
3028 | { |
3029 | const char *hash_err; | |
3030 | ||
86fa6981 L |
3031 | /* Support pseudo prefixes like {disp32}. */ |
3032 | lex_type ['{'] = LEX_BEGIN_NAME; | |
3033 | ||
47926f60 | 3034 | /* Initialize op_hash hash table. */ |
252b5132 RH |
3035 | op_hash = hash_new (); |
3036 | ||
3037 | { | |
d3ce72d0 | 3038 | const insn_template *optab; |
29b0f896 | 3039 | templates *core_optab; |
252b5132 | 3040 | |
47926f60 KH |
3041 | /* Setup for loop. */ |
3042 | optab = i386_optab; | |
add39d23 | 3043 | core_optab = XNEW (templates); |
252b5132 RH |
3044 | core_optab->start = optab; |
3045 | ||
3046 | while (1) | |
3047 | { | |
3048 | ++optab; | |
3049 | if (optab->name == NULL | |
3050 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
3051 | { | |
3052 | /* different name --> ship out current template list; | |
47926f60 | 3053 | add to hash table; & begin anew. */ |
252b5132 RH |
3054 | core_optab->end = optab; |
3055 | hash_err = hash_insert (op_hash, | |
3056 | (optab - 1)->name, | |
5a49b8ac | 3057 | (void *) core_optab); |
252b5132 RH |
3058 | if (hash_err) |
3059 | { | |
b37df7c4 | 3060 | as_fatal (_("can't hash %s: %s"), |
252b5132 RH |
3061 | (optab - 1)->name, |
3062 | hash_err); | |
3063 | } | |
3064 | if (optab->name == NULL) | |
3065 | break; | |
add39d23 | 3066 | core_optab = XNEW (templates); |
252b5132 RH |
3067 | core_optab->start = optab; |
3068 | } | |
3069 | } | |
3070 | } | |
3071 | ||
47926f60 | 3072 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
3073 | reg_hash = hash_new (); |
3074 | { | |
29b0f896 | 3075 | const reg_entry *regtab; |
c3fe08fa | 3076 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 3077 | |
c3fe08fa | 3078 | for (regtab = i386_regtab; regtab_size--; regtab++) |
252b5132 | 3079 | { |
5a49b8ac | 3080 | hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); |
252b5132 | 3081 | if (hash_err) |
b37df7c4 | 3082 | as_fatal (_("can't hash %s: %s"), |
3e73aa7c JH |
3083 | regtab->reg_name, |
3084 | hash_err); | |
252b5132 RH |
3085 | } |
3086 | } | |
3087 | ||
47926f60 | 3088 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 3089 | { |
29b0f896 AM |
3090 | int c; |
3091 | char *p; | |
252b5132 RH |
3092 | |
3093 | for (c = 0; c < 256; c++) | |
3094 | { | |
3882b010 | 3095 | if (ISDIGIT (c)) |
252b5132 RH |
3096 | { |
3097 | digit_chars[c] = c; | |
3098 | mnemonic_chars[c] = c; | |
3099 | register_chars[c] = c; | |
3100 | operand_chars[c] = c; | |
3101 | } | |
3882b010 | 3102 | else if (ISLOWER (c)) |
252b5132 RH |
3103 | { |
3104 | mnemonic_chars[c] = c; | |
3105 | register_chars[c] = c; | |
3106 | operand_chars[c] = c; | |
3107 | } | |
3882b010 | 3108 | else if (ISUPPER (c)) |
252b5132 | 3109 | { |
3882b010 | 3110 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
3111 | register_chars[c] = mnemonic_chars[c]; |
3112 | operand_chars[c] = c; | |
3113 | } | |
43234a1e | 3114 | else if (c == '{' || c == '}') |
86fa6981 L |
3115 | { |
3116 | mnemonic_chars[c] = c; | |
3117 | operand_chars[c] = c; | |
3118 | } | |
b3983e5f JB |
3119 | #ifdef SVR4_COMMENT_CHARS |
3120 | else if (c == '\\' && strchr (i386_comment_chars, '/')) | |
3121 | operand_chars[c] = c; | |
3122 | #endif | |
252b5132 | 3123 | |
3882b010 | 3124 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
3125 | identifier_chars[c] = c; |
3126 | else if (c >= 128) | |
3127 | { | |
3128 | identifier_chars[c] = c; | |
3129 | operand_chars[c] = c; | |
3130 | } | |
3131 | } | |
3132 | ||
3133 | #ifdef LEX_AT | |
3134 | identifier_chars['@'] = '@'; | |
32137342 NC |
3135 | #endif |
3136 | #ifdef LEX_QM | |
3137 | identifier_chars['?'] = '?'; | |
3138 | operand_chars['?'] = '?'; | |
252b5132 | 3139 | #endif |
252b5132 | 3140 | digit_chars['-'] = '-'; |
c0f3af97 | 3141 | mnemonic_chars['_'] = '_'; |
791fe849 | 3142 | mnemonic_chars['-'] = '-'; |
0003779b | 3143 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
3144 | identifier_chars['_'] = '_'; |
3145 | identifier_chars['.'] = '.'; | |
3146 | ||
3147 | for (p = operand_special_chars; *p != '\0'; p++) | |
3148 | operand_chars[(unsigned char) *p] = *p; | |
3149 | } | |
3150 | ||
a4447b93 RH |
3151 | if (flag_code == CODE_64BIT) |
3152 | { | |
ca19b261 KT |
3153 | #if defined (OBJ_COFF) && defined (TE_PE) |
3154 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour | |
3155 | ? 32 : 16); | |
3156 | #else | |
a4447b93 | 3157 | x86_dwarf2_return_column = 16; |
ca19b261 | 3158 | #endif |
61ff971f | 3159 | x86_cie_data_alignment = -8; |
a4447b93 RH |
3160 | } |
3161 | else | |
3162 | { | |
3163 | x86_dwarf2_return_column = 8; | |
3164 | x86_cie_data_alignment = -4; | |
3165 | } | |
e379e5f3 L |
3166 | |
3167 | /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it | |
3168 | can be turned into BRANCH_PREFIX frag. */ | |
3169 | if (align_branch_prefix_size > MAX_FUSED_JCC_PADDING_SIZE) | |
3170 | abort (); | |
252b5132 RH |
3171 | } |
3172 | ||
3173 | void | |
e3bb37b5 | 3174 | i386_print_statistics (FILE *file) |
252b5132 RH |
3175 | { |
3176 | hash_print_statistics (file, "i386 opcode", op_hash); | |
3177 | hash_print_statistics (file, "i386 register", reg_hash); | |
3178 | } | |
3179 | \f | |
252b5132 RH |
3180 | #ifdef DEBUG386 |
3181 | ||
ce8a8b2f | 3182 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 3183 | static void pte (insn_template *); |
40fb9820 | 3184 | static void pt (i386_operand_type); |
e3bb37b5 L |
3185 | static void pe (expressionS *); |
3186 | static void ps (symbolS *); | |
252b5132 RH |
3187 | |
3188 | static void | |
2c703856 | 3189 | pi (const char *line, i386_insn *x) |
252b5132 | 3190 | { |
09137c09 | 3191 | unsigned int j; |
252b5132 RH |
3192 | |
3193 | fprintf (stdout, "%s: template ", line); | |
3194 | pte (&x->tm); | |
09f131f2 JH |
3195 | fprintf (stdout, " address: base %s index %s scale %x\n", |
3196 | x->base_reg ? x->base_reg->reg_name : "none", | |
3197 | x->index_reg ? x->index_reg->reg_name : "none", | |
3198 | x->log2_scale_factor); | |
3199 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 3200 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
3201 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
3202 | x->sib.base, x->sib.index, x->sib.scale); | |
3203 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
3204 | (x->rex & REX_W) != 0, |
3205 | (x->rex & REX_R) != 0, | |
3206 | (x->rex & REX_X) != 0, | |
3207 | (x->rex & REX_B) != 0); | |
09137c09 | 3208 | for (j = 0; j < x->operands; j++) |
252b5132 | 3209 | { |
09137c09 SP |
3210 | fprintf (stdout, " #%d: ", j + 1); |
3211 | pt (x->types[j]); | |
252b5132 | 3212 | fprintf (stdout, "\n"); |
bab6aec1 | 3213 | if (x->types[j].bitfield.class == Reg |
3528c362 JB |
3214 | || x->types[j].bitfield.class == RegMMX |
3215 | || x->types[j].bitfield.class == RegSIMD | |
dd6b8a0b | 3216 | || x->types[j].bitfield.class == RegMask |
00cee14f | 3217 | || x->types[j].bitfield.class == SReg |
4a5c67ed JB |
3218 | || x->types[j].bitfield.class == RegCR |
3219 | || x->types[j].bitfield.class == RegDR | |
dd6b8a0b JB |
3220 | || x->types[j].bitfield.class == RegTR |
3221 | || x->types[j].bitfield.class == RegBND) | |
09137c09 SP |
3222 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); |
3223 | if (operand_type_check (x->types[j], imm)) | |
3224 | pe (x->op[j].imms); | |
3225 | if (operand_type_check (x->types[j], disp)) | |
3226 | pe (x->op[j].disps); | |
252b5132 RH |
3227 | } |
3228 | } | |
3229 | ||
3230 | static void | |
d3ce72d0 | 3231 | pte (insn_template *t) |
252b5132 | 3232 | { |
09137c09 | 3233 | unsigned int j; |
252b5132 | 3234 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 3235 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
3236 | if (t->extension_opcode != None) |
3237 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 3238 | if (t->opcode_modifier.d) |
252b5132 | 3239 | fprintf (stdout, "D"); |
40fb9820 | 3240 | if (t->opcode_modifier.w) |
252b5132 RH |
3241 | fprintf (stdout, "W"); |
3242 | fprintf (stdout, "\n"); | |
09137c09 | 3243 | for (j = 0; j < t->operands; j++) |
252b5132 | 3244 | { |
09137c09 SP |
3245 | fprintf (stdout, " #%d type ", j + 1); |
3246 | pt (t->operand_types[j]); | |
252b5132 RH |
3247 | fprintf (stdout, "\n"); |
3248 | } | |
3249 | } | |
3250 | ||
3251 | static void | |
e3bb37b5 | 3252 | pe (expressionS *e) |
252b5132 | 3253 | { |
24eab124 | 3254 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
3255 | fprintf (stdout, " add_number %ld (%lx)\n", |
3256 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
3257 | if (e->X_add_symbol) |
3258 | { | |
3259 | fprintf (stdout, " add_symbol "); | |
3260 | ps (e->X_add_symbol); | |
3261 | fprintf (stdout, "\n"); | |
3262 | } | |
3263 | if (e->X_op_symbol) | |
3264 | { | |
3265 | fprintf (stdout, " op_symbol "); | |
3266 | ps (e->X_op_symbol); | |
3267 | fprintf (stdout, "\n"); | |
3268 | } | |
3269 | } | |
3270 | ||
3271 | static void | |
e3bb37b5 | 3272 | ps (symbolS *s) |
252b5132 RH |
3273 | { |
3274 | fprintf (stdout, "%s type %s%s", | |
3275 | S_GET_NAME (s), | |
3276 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
3277 | segment_name (S_GET_SEGMENT (s))); | |
3278 | } | |
3279 | ||
7b81dfbb | 3280 | static struct type_name |
252b5132 | 3281 | { |
40fb9820 L |
3282 | i386_operand_type mask; |
3283 | const char *name; | |
252b5132 | 3284 | } |
7b81dfbb | 3285 | const type_names[] = |
252b5132 | 3286 | { |
40fb9820 L |
3287 | { OPERAND_TYPE_REG8, "r8" }, |
3288 | { OPERAND_TYPE_REG16, "r16" }, | |
3289 | { OPERAND_TYPE_REG32, "r32" }, | |
3290 | { OPERAND_TYPE_REG64, "r64" }, | |
2c703856 JB |
3291 | { OPERAND_TYPE_ACC8, "acc8" }, |
3292 | { OPERAND_TYPE_ACC16, "acc16" }, | |
3293 | { OPERAND_TYPE_ACC32, "acc32" }, | |
3294 | { OPERAND_TYPE_ACC64, "acc64" }, | |
40fb9820 L |
3295 | { OPERAND_TYPE_IMM8, "i8" }, |
3296 | { OPERAND_TYPE_IMM8, "i8s" }, | |
3297 | { OPERAND_TYPE_IMM16, "i16" }, | |
3298 | { OPERAND_TYPE_IMM32, "i32" }, | |
3299 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
3300 | { OPERAND_TYPE_IMM64, "i64" }, | |
3301 | { OPERAND_TYPE_IMM1, "i1" }, | |
3302 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
3303 | { OPERAND_TYPE_DISP8, "d8" }, | |
3304 | { OPERAND_TYPE_DISP16, "d16" }, | |
3305 | { OPERAND_TYPE_DISP32, "d32" }, | |
3306 | { OPERAND_TYPE_DISP32S, "d32s" }, | |
3307 | { OPERAND_TYPE_DISP64, "d64" }, | |
3308 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, | |
3309 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
3310 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
3311 | { OPERAND_TYPE_TEST, "test reg" }, | |
3312 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
3313 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
3314 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
21df382b | 3315 | { OPERAND_TYPE_SREG, "SReg" }, |
40fb9820 L |
3316 | { OPERAND_TYPE_REGMMX, "rMMX" }, |
3317 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
0349dc08 | 3318 | { OPERAND_TYPE_REGYMM, "rYMM" }, |
43234a1e | 3319 | { OPERAND_TYPE_REGZMM, "rZMM" }, |
260cd341 | 3320 | { OPERAND_TYPE_REGTMM, "rTMM" }, |
43234a1e | 3321 | { OPERAND_TYPE_REGMASK, "Mask reg" }, |
252b5132 RH |
3322 | }; |
3323 | ||
3324 | static void | |
40fb9820 | 3325 | pt (i386_operand_type t) |
252b5132 | 3326 | { |
40fb9820 | 3327 | unsigned int j; |
c6fb90c8 | 3328 | i386_operand_type a; |
252b5132 | 3329 | |
40fb9820 | 3330 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
3331 | { |
3332 | a = operand_type_and (t, type_names[j].mask); | |
2c703856 | 3333 | if (operand_type_equal (&a, &type_names[j].mask)) |
c6fb90c8 L |
3334 | fprintf (stdout, "%s, ", type_names[j].name); |
3335 | } | |
252b5132 RH |
3336 | fflush (stdout); |
3337 | } | |
3338 | ||
3339 | #endif /* DEBUG386 */ | |
3340 | \f | |
252b5132 | 3341 | static bfd_reloc_code_real_type |
3956db08 | 3342 | reloc (unsigned int size, |
64e74474 AM |
3343 | int pcrel, |
3344 | int sign, | |
3345 | bfd_reloc_code_real_type other) | |
252b5132 | 3346 | { |
47926f60 | 3347 | if (other != NO_RELOC) |
3956db08 | 3348 | { |
91d6fa6a | 3349 | reloc_howto_type *rel; |
3956db08 JB |
3350 | |
3351 | if (size == 8) | |
3352 | switch (other) | |
3353 | { | |
64e74474 AM |
3354 | case BFD_RELOC_X86_64_GOT32: |
3355 | return BFD_RELOC_X86_64_GOT64; | |
3356 | break; | |
553d1284 L |
3357 | case BFD_RELOC_X86_64_GOTPLT64: |
3358 | return BFD_RELOC_X86_64_GOTPLT64; | |
3359 | break; | |
64e74474 AM |
3360 | case BFD_RELOC_X86_64_PLTOFF64: |
3361 | return BFD_RELOC_X86_64_PLTOFF64; | |
3362 | break; | |
3363 | case BFD_RELOC_X86_64_GOTPC32: | |
3364 | other = BFD_RELOC_X86_64_GOTPC64; | |
3365 | break; | |
3366 | case BFD_RELOC_X86_64_GOTPCREL: | |
3367 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
3368 | break; | |
3369 | case BFD_RELOC_X86_64_TPOFF32: | |
3370 | other = BFD_RELOC_X86_64_TPOFF64; | |
3371 | break; | |
3372 | case BFD_RELOC_X86_64_DTPOFF32: | |
3373 | other = BFD_RELOC_X86_64_DTPOFF64; | |
3374 | break; | |
3375 | default: | |
3376 | break; | |
3956db08 | 3377 | } |
e05278af | 3378 | |
8ce3d284 | 3379 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
3380 | if (other == BFD_RELOC_SIZE32) |
3381 | { | |
3382 | if (size == 8) | |
1ab668bf | 3383 | other = BFD_RELOC_SIZE64; |
8fd4256d | 3384 | if (pcrel) |
1ab668bf AM |
3385 | { |
3386 | as_bad (_("there are no pc-relative size relocations")); | |
3387 | return NO_RELOC; | |
3388 | } | |
8fd4256d | 3389 | } |
8ce3d284 | 3390 | #endif |
8fd4256d | 3391 | |
e05278af | 3392 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
f2d8a97c | 3393 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
e05278af JB |
3394 | sign = -1; |
3395 | ||
91d6fa6a NC |
3396 | rel = bfd_reloc_type_lookup (stdoutput, other); |
3397 | if (!rel) | |
3956db08 | 3398 | as_bad (_("unknown relocation (%u)"), other); |
91d6fa6a | 3399 | else if (size != bfd_get_reloc_size (rel)) |
3956db08 | 3400 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
91d6fa6a | 3401 | bfd_get_reloc_size (rel), |
3956db08 | 3402 | size); |
91d6fa6a | 3403 | else if (pcrel && !rel->pc_relative) |
3956db08 | 3404 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
91d6fa6a | 3405 | else if ((rel->complain_on_overflow == complain_overflow_signed |
3956db08 | 3406 | && !sign) |
91d6fa6a | 3407 | || (rel->complain_on_overflow == complain_overflow_unsigned |
64e74474 | 3408 | && sign > 0)) |
3956db08 JB |
3409 | as_bad (_("relocated field and relocation type differ in signedness")); |
3410 | else | |
3411 | return other; | |
3412 | return NO_RELOC; | |
3413 | } | |
252b5132 RH |
3414 | |
3415 | if (pcrel) | |
3416 | { | |
3e73aa7c | 3417 | if (!sign) |
3956db08 | 3418 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
3419 | switch (size) |
3420 | { | |
3421 | case 1: return BFD_RELOC_8_PCREL; | |
3422 | case 2: return BFD_RELOC_16_PCREL; | |
d258b828 | 3423 | case 4: return BFD_RELOC_32_PCREL; |
d6ab8113 | 3424 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 3425 | } |
3956db08 | 3426 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
3427 | } |
3428 | else | |
3429 | { | |
3956db08 | 3430 | if (sign > 0) |
e5cb08ac | 3431 | switch (size) |
3e73aa7c JH |
3432 | { |
3433 | case 4: return BFD_RELOC_X86_64_32S; | |
3434 | } | |
3435 | else | |
3436 | switch (size) | |
3437 | { | |
3438 | case 1: return BFD_RELOC_8; | |
3439 | case 2: return BFD_RELOC_16; | |
3440 | case 4: return BFD_RELOC_32; | |
3441 | case 8: return BFD_RELOC_64; | |
3442 | } | |
3956db08 JB |
3443 | as_bad (_("cannot do %s %u byte relocation"), |
3444 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
3445 | } |
3446 | ||
0cc9e1d3 | 3447 | return NO_RELOC; |
252b5132 RH |
3448 | } |
3449 | ||
47926f60 KH |
3450 | /* Here we decide which fixups can be adjusted to make them relative to |
3451 | the beginning of the section instead of the symbol. Basically we need | |
3452 | to make sure that the dynamic relocations are done correctly, so in | |
3453 | some cases we force the original symbol to be used. */ | |
3454 | ||
252b5132 | 3455 | int |
e3bb37b5 | 3456 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 3457 | { |
6d249963 | 3458 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 3459 | if (!IS_ELF) |
31312f95 AM |
3460 | return 1; |
3461 | ||
a161fe53 AM |
3462 | /* Don't adjust pc-relative references to merge sections in 64-bit |
3463 | mode. */ | |
3464 | if (use_rela_relocations | |
3465 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
3466 | && fixP->fx_pcrel) | |
252b5132 | 3467 | return 0; |
31312f95 | 3468 | |
8d01d9a9 AJ |
3469 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
3470 | and changed later by validate_fix. */ | |
3471 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
3472 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
3473 | return 0; | |
3474 | ||
8fd4256d L |
3475 | /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol |
3476 | for size relocations. */ | |
3477 | if (fixP->fx_r_type == BFD_RELOC_SIZE32 | |
3478 | || fixP->fx_r_type == BFD_RELOC_SIZE64 | |
3479 | || fixP->fx_r_type == BFD_RELOC_386_GOTOFF | |
252b5132 | 3480 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 |
02a86693 | 3481 | || fixP->fx_r_type == BFD_RELOC_386_GOT32X |
13ae64f3 JJ |
3482 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
3483 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
3484 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
3485 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
3486 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
3487 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
3488 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
3489 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
3490 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
3491 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c | 3492 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 |
80b3ee89 | 3493 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
56ceb5b5 L |
3494 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX |
3495 | || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX | |
bffbf940 JJ |
3496 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
3497 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
3498 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 3499 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
3500 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
3501 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
3502 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
3503 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
3504 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
3505 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
3506 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
3507 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3508 | return 0; | |
31312f95 | 3509 | #endif |
252b5132 RH |
3510 | return 1; |
3511 | } | |
252b5132 | 3512 | |
b4cac588 | 3513 | static int |
e3bb37b5 | 3514 | intel_float_operand (const char *mnemonic) |
252b5132 | 3515 | { |
9306ca4a JB |
3516 | /* Note that the value returned is meaningful only for opcodes with (memory) |
3517 | operands, hence the code here is free to improperly handle opcodes that | |
3518 | have no operands (for better performance and smaller code). */ | |
3519 | ||
3520 | if (mnemonic[0] != 'f') | |
3521 | return 0; /* non-math */ | |
3522 | ||
3523 | switch (mnemonic[1]) | |
3524 | { | |
3525 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
3526 | the fs segment override prefix not currently handled because no | |
3527 | call path can make opcodes without operands get here */ | |
3528 | case 'i': | |
3529 | return 2 /* integer op */; | |
3530 | case 'l': | |
3531 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
3532 | return 3; /* fldcw/fldenv */ | |
3533 | break; | |
3534 | case 'n': | |
3535 | if (mnemonic[2] != 'o' /* fnop */) | |
3536 | return 3; /* non-waiting control op */ | |
3537 | break; | |
3538 | case 'r': | |
3539 | if (mnemonic[2] == 's') | |
3540 | return 3; /* frstor/frstpm */ | |
3541 | break; | |
3542 | case 's': | |
3543 | if (mnemonic[2] == 'a') | |
3544 | return 3; /* fsave */ | |
3545 | if (mnemonic[2] == 't') | |
3546 | { | |
3547 | switch (mnemonic[3]) | |
3548 | { | |
3549 | case 'c': /* fstcw */ | |
3550 | case 'd': /* fstdw */ | |
3551 | case 'e': /* fstenv */ | |
3552 | case 's': /* fsts[gw] */ | |
3553 | return 3; | |
3554 | } | |
3555 | } | |
3556 | break; | |
3557 | case 'x': | |
3558 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
3559 | return 0; /* fxsave/fxrstor are not really math ops */ | |
3560 | break; | |
3561 | } | |
252b5132 | 3562 | |
9306ca4a | 3563 | return 1; |
252b5132 RH |
3564 | } |
3565 | ||
c0f3af97 L |
3566 | /* Build the VEX prefix. */ |
3567 | ||
3568 | static void | |
d3ce72d0 | 3569 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
3570 | { |
3571 | unsigned int register_specifier; | |
3572 | unsigned int implied_prefix; | |
3573 | unsigned int vector_length; | |
03751133 | 3574 | unsigned int w; |
c0f3af97 L |
3575 | |
3576 | /* Check register specifier. */ | |
3577 | if (i.vex.register_specifier) | |
43234a1e L |
3578 | { |
3579 | register_specifier = | |
3580 | ~register_number (i.vex.register_specifier) & 0xf; | |
3581 | gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); | |
3582 | } | |
c0f3af97 L |
3583 | else |
3584 | register_specifier = 0xf; | |
3585 | ||
79f0fa25 L |
3586 | /* Use 2-byte VEX prefix by swapping destination and source operand |
3587 | if there are more than 1 register operand. */ | |
3588 | if (i.reg_operands > 1 | |
3589 | && i.vec_encoding != vex_encoding_vex3 | |
86fa6981 | 3590 | && i.dir_encoding == dir_encoding_default |
fa99fab2 | 3591 | && i.operands == i.reg_operands |
dbbc8b7e | 3592 | && operand_type_equal (&i.types[0], &i.types[i.operands - 1]) |
7f399153 | 3593 | && i.tm.opcode_modifier.vexopcode == VEX0F |
dbbc8b7e | 3594 | && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d) |
fa99fab2 L |
3595 | && i.rex == REX_B) |
3596 | { | |
3597 | unsigned int xchg = i.operands - 1; | |
3598 | union i386_op temp_op; | |
3599 | i386_operand_type temp_type; | |
3600 | ||
3601 | temp_type = i.types[xchg]; | |
3602 | i.types[xchg] = i.types[0]; | |
3603 | i.types[0] = temp_type; | |
3604 | temp_op = i.op[xchg]; | |
3605 | i.op[xchg] = i.op[0]; | |
3606 | i.op[0] = temp_op; | |
3607 | ||
9c2799c2 | 3608 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
3609 | |
3610 | i.rex = REX_R; | |
3611 | xchg = i.rm.regmem; | |
3612 | i.rm.regmem = i.rm.reg; | |
3613 | i.rm.reg = xchg; | |
3614 | ||
dbbc8b7e JB |
3615 | if (i.tm.opcode_modifier.d) |
3616 | i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e | |
3617 | ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; | |
3618 | else /* Use the next insn. */ | |
3619 | i.tm = t[1]; | |
fa99fab2 L |
3620 | } |
3621 | ||
79dec6b7 JB |
3622 | /* Use 2-byte VEX prefix by swapping commutative source operands if there |
3623 | are no memory operands and at least 3 register ones. */ | |
3624 | if (i.reg_operands >= 3 | |
3625 | && i.vec_encoding != vex_encoding_vex3 | |
3626 | && i.reg_operands == i.operands - i.imm_operands | |
3627 | && i.tm.opcode_modifier.vex | |
3628 | && i.tm.opcode_modifier.commutative | |
3629 | && (i.tm.opcode_modifier.sse2avx || optimize > 1) | |
3630 | && i.rex == REX_B | |
3631 | && i.vex.register_specifier | |
3632 | && !(i.vex.register_specifier->reg_flags & RegRex)) | |
3633 | { | |
3634 | unsigned int xchg = i.operands - i.reg_operands; | |
3635 | union i386_op temp_op; | |
3636 | i386_operand_type temp_type; | |
3637 | ||
3638 | gas_assert (i.tm.opcode_modifier.vexopcode == VEX0F); | |
3639 | gas_assert (!i.tm.opcode_modifier.sae); | |
3640 | gas_assert (operand_type_equal (&i.types[i.operands - 2], | |
3641 | &i.types[i.operands - 3])); | |
3642 | gas_assert (i.rm.mode == 3); | |
3643 | ||
3644 | temp_type = i.types[xchg]; | |
3645 | i.types[xchg] = i.types[xchg + 1]; | |
3646 | i.types[xchg + 1] = temp_type; | |
3647 | temp_op = i.op[xchg]; | |
3648 | i.op[xchg] = i.op[xchg + 1]; | |
3649 | i.op[xchg + 1] = temp_op; | |
3650 | ||
3651 | i.rex = 0; | |
3652 | xchg = i.rm.regmem | 8; | |
3653 | i.rm.regmem = ~register_specifier & 0xf; | |
3654 | gas_assert (!(i.rm.regmem & 8)); | |
3655 | i.vex.register_specifier += xchg - i.rm.regmem; | |
3656 | register_specifier = ~xchg & 0xf; | |
3657 | } | |
3658 | ||
539f890d L |
3659 | if (i.tm.opcode_modifier.vex == VEXScalar) |
3660 | vector_length = avxscalar; | |
10c17abd JB |
3661 | else if (i.tm.opcode_modifier.vex == VEX256) |
3662 | vector_length = 1; | |
539f890d | 3663 | else |
10c17abd | 3664 | { |
56522fc5 | 3665 | unsigned int op; |
10c17abd | 3666 | |
c7213af9 L |
3667 | /* Determine vector length from the last multi-length vector |
3668 | operand. */ | |
10c17abd | 3669 | vector_length = 0; |
56522fc5 | 3670 | for (op = t->operands; op--;) |
10c17abd JB |
3671 | if (t->operand_types[op].bitfield.xmmword |
3672 | && t->operand_types[op].bitfield.ymmword | |
3673 | && i.types[op].bitfield.ymmword) | |
3674 | { | |
3675 | vector_length = 1; | |
3676 | break; | |
3677 | } | |
3678 | } | |
c0f3af97 | 3679 | |
8c190ce0 | 3680 | switch ((i.tm.base_opcode >> (i.tm.opcode_length << 3)) & 0xff) |
c0f3af97 L |
3681 | { |
3682 | case 0: | |
3683 | implied_prefix = 0; | |
3684 | break; | |
3685 | case DATA_PREFIX_OPCODE: | |
3686 | implied_prefix = 1; | |
3687 | break; | |
3688 | case REPE_PREFIX_OPCODE: | |
3689 | implied_prefix = 2; | |
3690 | break; | |
3691 | case REPNE_PREFIX_OPCODE: | |
3692 | implied_prefix = 3; | |
3693 | break; | |
3694 | default: | |
3695 | abort (); | |
3696 | } | |
3697 | ||
03751133 L |
3698 | /* Check the REX.W bit and VEXW. */ |
3699 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3700 | w = (vexwig == vexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3701 | else if (i.tm.opcode_modifier.vexw) | |
3702 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3703 | else | |
931d03b7 | 3704 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : vexwig == vexw1) ? 1 : 0; |
03751133 | 3705 | |
c0f3af97 | 3706 | /* Use 2-byte VEX prefix if possible. */ |
03751133 L |
3707 | if (w == 0 |
3708 | && i.vec_encoding != vex_encoding_vex3 | |
86fa6981 | 3709 | && i.tm.opcode_modifier.vexopcode == VEX0F |
c0f3af97 L |
3710 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
3711 | { | |
3712 | /* 2-byte VEX prefix. */ | |
3713 | unsigned int r; | |
3714 | ||
3715 | i.vex.length = 2; | |
3716 | i.vex.bytes[0] = 0xc5; | |
3717 | ||
3718 | /* Check the REX.R bit. */ | |
3719 | r = (i.rex & REX_R) ? 0 : 1; | |
3720 | i.vex.bytes[1] = (r << 7 | |
3721 | | register_specifier << 3 | |
3722 | | vector_length << 2 | |
3723 | | implied_prefix); | |
3724 | } | |
3725 | else | |
3726 | { | |
3727 | /* 3-byte VEX prefix. */ | |
03751133 | 3728 | unsigned int m; |
c0f3af97 | 3729 | |
f88c9eb0 | 3730 | i.vex.length = 3; |
f88c9eb0 | 3731 | |
7f399153 | 3732 | switch (i.tm.opcode_modifier.vexopcode) |
5dd85c99 | 3733 | { |
7f399153 L |
3734 | case VEX0F: |
3735 | m = 0x1; | |
80de6e00 | 3736 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3737 | break; |
3738 | case VEX0F38: | |
3739 | m = 0x2; | |
80de6e00 | 3740 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3741 | break; |
3742 | case VEX0F3A: | |
3743 | m = 0x3; | |
80de6e00 | 3744 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3745 | break; |
3746 | case XOP08: | |
5dd85c99 SP |
3747 | m = 0x8; |
3748 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3749 | break; |
3750 | case XOP09: | |
f88c9eb0 SP |
3751 | m = 0x9; |
3752 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3753 | break; |
3754 | case XOP0A: | |
f88c9eb0 SP |
3755 | m = 0xa; |
3756 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3757 | break; |
3758 | default: | |
3759 | abort (); | |
f88c9eb0 | 3760 | } |
c0f3af97 | 3761 | |
c0f3af97 L |
3762 | /* The high 3 bits of the second VEX byte are 1's compliment |
3763 | of RXB bits from REX. */ | |
3764 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3765 | ||
c0f3af97 L |
3766 | i.vex.bytes[2] = (w << 7 |
3767 | | register_specifier << 3 | |
3768 | | vector_length << 2 | |
3769 | | implied_prefix); | |
3770 | } | |
3771 | } | |
3772 | ||
e771e7c9 JB |
3773 | static INLINE bfd_boolean |
3774 | is_evex_encoding (const insn_template *t) | |
3775 | { | |
7091c612 | 3776 | return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift |
e771e7c9 | 3777 | || t->opcode_modifier.broadcast || t->opcode_modifier.masking |
a80195f1 | 3778 | || t->opcode_modifier.sae; |
e771e7c9 JB |
3779 | } |
3780 | ||
7a8655d2 JB |
3781 | static INLINE bfd_boolean |
3782 | is_any_vex_encoding (const insn_template *t) | |
3783 | { | |
3784 | return t->opcode_modifier.vex || t->opcode_modifier.vexopcode | |
3785 | || is_evex_encoding (t); | |
3786 | } | |
3787 | ||
43234a1e L |
3788 | /* Build the EVEX prefix. */ |
3789 | ||
3790 | static void | |
3791 | build_evex_prefix (void) | |
3792 | { | |
3793 | unsigned int register_specifier; | |
3794 | unsigned int implied_prefix; | |
3795 | unsigned int m, w; | |
3796 | rex_byte vrex_used = 0; | |
3797 | ||
3798 | /* Check register specifier. */ | |
3799 | if (i.vex.register_specifier) | |
3800 | { | |
3801 | gas_assert ((i.vrex & REX_X) == 0); | |
3802 | ||
3803 | register_specifier = i.vex.register_specifier->reg_num; | |
3804 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
3805 | register_specifier += 8; | |
3806 | /* The upper 16 registers are encoded in the fourth byte of the | |
3807 | EVEX prefix. */ | |
3808 | if (!(i.vex.register_specifier->reg_flags & RegVRex)) | |
3809 | i.vex.bytes[3] = 0x8; | |
3810 | register_specifier = ~register_specifier & 0xf; | |
3811 | } | |
3812 | else | |
3813 | { | |
3814 | register_specifier = 0xf; | |
3815 | ||
3816 | /* Encode upper 16 vector index register in the fourth byte of | |
3817 | the EVEX prefix. */ | |
3818 | if (!(i.vrex & REX_X)) | |
3819 | i.vex.bytes[3] = 0x8; | |
3820 | else | |
3821 | vrex_used |= REX_X; | |
3822 | } | |
3823 | ||
3824 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3825 | { | |
3826 | case 0: | |
3827 | implied_prefix = 0; | |
3828 | break; | |
3829 | case DATA_PREFIX_OPCODE: | |
3830 | implied_prefix = 1; | |
3831 | break; | |
3832 | case REPE_PREFIX_OPCODE: | |
3833 | implied_prefix = 2; | |
3834 | break; | |
3835 | case REPNE_PREFIX_OPCODE: | |
3836 | implied_prefix = 3; | |
3837 | break; | |
3838 | default: | |
3839 | abort (); | |
3840 | } | |
3841 | ||
3842 | /* 4 byte EVEX prefix. */ | |
3843 | i.vex.length = 4; | |
3844 | i.vex.bytes[0] = 0x62; | |
3845 | ||
3846 | /* mmmm bits. */ | |
3847 | switch (i.tm.opcode_modifier.vexopcode) | |
3848 | { | |
3849 | case VEX0F: | |
3850 | m = 1; | |
3851 | break; | |
3852 | case VEX0F38: | |
3853 | m = 2; | |
3854 | break; | |
3855 | case VEX0F3A: | |
3856 | m = 3; | |
3857 | break; | |
3858 | default: | |
3859 | abort (); | |
3860 | break; | |
3861 | } | |
3862 | ||
3863 | /* The high 3 bits of the second EVEX byte are 1's compliment of RXB | |
3864 | bits from REX. */ | |
3865 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3866 | ||
3867 | /* The fifth bit of the second EVEX byte is 1's compliment of the | |
3868 | REX_R bit in VREX. */ | |
3869 | if (!(i.vrex & REX_R)) | |
3870 | i.vex.bytes[1] |= 0x10; | |
3871 | else | |
3872 | vrex_used |= REX_R; | |
3873 | ||
3874 | if ((i.reg_operands + i.imm_operands) == i.operands) | |
3875 | { | |
3876 | /* When all operands are registers, the REX_X bit in REX is not | |
3877 | used. We reuse it to encode the upper 16 registers, which is | |
3878 | indicated by the REX_B bit in VREX. The REX_X bit is encoded | |
3879 | as 1's compliment. */ | |
3880 | if ((i.vrex & REX_B)) | |
3881 | { | |
3882 | vrex_used |= REX_B; | |
3883 | i.vex.bytes[1] &= ~0x40; | |
3884 | } | |
3885 | } | |
3886 | ||
3887 | /* EVEX instructions shouldn't need the REX prefix. */ | |
3888 | i.vrex &= ~vrex_used; | |
3889 | gas_assert (i.vrex == 0); | |
3890 | ||
6865c043 L |
3891 | /* Check the REX.W bit and VEXW. */ |
3892 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3893 | w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3894 | else if (i.tm.opcode_modifier.vexw) | |
3895 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3896 | else | |
931d03b7 | 3897 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0; |
43234a1e L |
3898 | |
3899 | /* Encode the U bit. */ | |
3900 | implied_prefix |= 0x4; | |
3901 | ||
3902 | /* The third byte of the EVEX prefix. */ | |
3903 | i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix); | |
3904 | ||
3905 | /* The fourth byte of the EVEX prefix. */ | |
3906 | /* The zeroing-masking bit. */ | |
3907 | if (i.mask && i.mask->zeroing) | |
3908 | i.vex.bytes[3] |= 0x80; | |
3909 | ||
3910 | /* Don't always set the broadcast bit if there is no RC. */ | |
3911 | if (!i.rounding) | |
3912 | { | |
3913 | /* Encode the vector length. */ | |
3914 | unsigned int vec_length; | |
3915 | ||
e771e7c9 JB |
3916 | if (!i.tm.opcode_modifier.evex |
3917 | || i.tm.opcode_modifier.evex == EVEXDYN) | |
3918 | { | |
56522fc5 | 3919 | unsigned int op; |
e771e7c9 | 3920 | |
c7213af9 L |
3921 | /* Determine vector length from the last multi-length vector |
3922 | operand. */ | |
56522fc5 | 3923 | for (op = i.operands; op--;) |
e771e7c9 JB |
3924 | if (i.tm.operand_types[op].bitfield.xmmword |
3925 | + i.tm.operand_types[op].bitfield.ymmword | |
3926 | + i.tm.operand_types[op].bitfield.zmmword > 1) | |
3927 | { | |
3928 | if (i.types[op].bitfield.zmmword) | |
c7213af9 L |
3929 | { |
3930 | i.tm.opcode_modifier.evex = EVEX512; | |
3931 | break; | |
3932 | } | |
e771e7c9 | 3933 | else if (i.types[op].bitfield.ymmword) |
c7213af9 L |
3934 | { |
3935 | i.tm.opcode_modifier.evex = EVEX256; | |
3936 | break; | |
3937 | } | |
e771e7c9 | 3938 | else if (i.types[op].bitfield.xmmword) |
c7213af9 L |
3939 | { |
3940 | i.tm.opcode_modifier.evex = EVEX128; | |
3941 | break; | |
3942 | } | |
625cbd7a JB |
3943 | else if (i.broadcast && (int) op == i.broadcast->operand) |
3944 | { | |
4a1b91ea | 3945 | switch (i.broadcast->bytes) |
625cbd7a JB |
3946 | { |
3947 | case 64: | |
3948 | i.tm.opcode_modifier.evex = EVEX512; | |
3949 | break; | |
3950 | case 32: | |
3951 | i.tm.opcode_modifier.evex = EVEX256; | |
3952 | break; | |
3953 | case 16: | |
3954 | i.tm.opcode_modifier.evex = EVEX128; | |
3955 | break; | |
3956 | default: | |
c7213af9 | 3957 | abort (); |
625cbd7a | 3958 | } |
c7213af9 | 3959 | break; |
625cbd7a | 3960 | } |
e771e7c9 | 3961 | } |
c7213af9 | 3962 | |
56522fc5 | 3963 | if (op >= MAX_OPERANDS) |
c7213af9 | 3964 | abort (); |
e771e7c9 JB |
3965 | } |
3966 | ||
43234a1e L |
3967 | switch (i.tm.opcode_modifier.evex) |
3968 | { | |
3969 | case EVEXLIG: /* LL' is ignored */ | |
3970 | vec_length = evexlig << 5; | |
3971 | break; | |
3972 | case EVEX128: | |
3973 | vec_length = 0 << 5; | |
3974 | break; | |
3975 | case EVEX256: | |
3976 | vec_length = 1 << 5; | |
3977 | break; | |
3978 | case EVEX512: | |
3979 | vec_length = 2 << 5; | |
3980 | break; | |
3981 | default: | |
3982 | abort (); | |
3983 | break; | |
3984 | } | |
3985 | i.vex.bytes[3] |= vec_length; | |
3986 | /* Encode the broadcast bit. */ | |
3987 | if (i.broadcast) | |
3988 | i.vex.bytes[3] |= 0x10; | |
3989 | } | |
3990 | else | |
3991 | { | |
3992 | if (i.rounding->type != saeonly) | |
3993 | i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5); | |
3994 | else | |
d3d3c6db | 3995 | i.vex.bytes[3] |= 0x10 | (evexrcig << 5); |
43234a1e L |
3996 | } |
3997 | ||
3998 | if (i.mask && i.mask->mask) | |
3999 | i.vex.bytes[3] |= i.mask->mask->reg_num; | |
4000 | } | |
4001 | ||
65da13b5 L |
4002 | static void |
4003 | process_immext (void) | |
4004 | { | |
4005 | expressionS *exp; | |
4006 | ||
c0f3af97 | 4007 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
4008 | which is coded in the same place as an 8-bit immediate field |
4009 | would be. Here we fake an 8-bit immediate operand from the | |
4010 | opcode suffix stored in tm.extension_opcode. | |
4011 | ||
c1e679ec | 4012 | AVX instructions also use this encoding, for some of |
c0f3af97 | 4013 | 3 argument instructions. */ |
65da13b5 | 4014 | |
43234a1e | 4015 | gas_assert (i.imm_operands <= 1 |
7ab9ffdd | 4016 | && (i.operands <= 2 |
7a8655d2 | 4017 | || (is_any_vex_encoding (&i.tm) |
7ab9ffdd | 4018 | && i.operands <= 4))); |
65da13b5 L |
4019 | |
4020 | exp = &im_expressions[i.imm_operands++]; | |
4021 | i.op[i.operands].imms = exp; | |
4022 | i.types[i.operands] = imm8; | |
4023 | i.operands++; | |
4024 | exp->X_op = O_constant; | |
4025 | exp->X_add_number = i.tm.extension_opcode; | |
4026 | i.tm.extension_opcode = None; | |
4027 | } | |
4028 | ||
42164a71 L |
4029 | |
4030 | static int | |
4031 | check_hle (void) | |
4032 | { | |
4033 | switch (i.tm.opcode_modifier.hleprefixok) | |
4034 | { | |
4035 | default: | |
4036 | abort (); | |
82c2def5 | 4037 | case HLEPrefixNone: |
165de32a L |
4038 | as_bad (_("invalid instruction `%s' after `%s'"), |
4039 | i.tm.name, i.hle_prefix); | |
42164a71 | 4040 | return 0; |
82c2def5 | 4041 | case HLEPrefixLock: |
42164a71 L |
4042 | if (i.prefix[LOCK_PREFIX]) |
4043 | return 1; | |
165de32a | 4044 | as_bad (_("missing `lock' with `%s'"), i.hle_prefix); |
42164a71 | 4045 | return 0; |
82c2def5 | 4046 | case HLEPrefixAny: |
42164a71 | 4047 | return 1; |
82c2def5 | 4048 | case HLEPrefixRelease: |
42164a71 L |
4049 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
4050 | { | |
4051 | as_bad (_("instruction `%s' after `xacquire' not allowed"), | |
4052 | i.tm.name); | |
4053 | return 0; | |
4054 | } | |
8dc0818e | 4055 | if (i.mem_operands == 0 || !(i.flags[i.operands - 1] & Operand_Mem)) |
42164a71 L |
4056 | { |
4057 | as_bad (_("memory destination needed for instruction `%s'" | |
4058 | " after `xrelease'"), i.tm.name); | |
4059 | return 0; | |
4060 | } | |
4061 | return 1; | |
4062 | } | |
4063 | } | |
4064 | ||
b6f8c7c4 L |
4065 | /* Try the shortest encoding by shortening operand size. */ |
4066 | ||
4067 | static void | |
4068 | optimize_encoding (void) | |
4069 | { | |
a0a1771e | 4070 | unsigned int j; |
b6f8c7c4 L |
4071 | |
4072 | if (optimize_for_space | |
72aea328 | 4073 | && !is_any_vex_encoding (&i.tm) |
b6f8c7c4 L |
4074 | && i.reg_operands == 1 |
4075 | && i.imm_operands == 1 | |
4076 | && !i.types[1].bitfield.byte | |
4077 | && i.op[0].imms->X_op == O_constant | |
4078 | && fits_in_imm7 (i.op[0].imms->X_add_number) | |
72aea328 | 4079 | && (i.tm.base_opcode == 0xa8 |
b6f8c7c4 L |
4080 | || (i.tm.base_opcode == 0xf6 |
4081 | && i.tm.extension_opcode == 0x0))) | |
4082 | { | |
4083 | /* Optimize: -Os: | |
4084 | test $imm7, %r64/%r32/%r16 -> test $imm7, %r8 | |
4085 | */ | |
4086 | unsigned int base_regnum = i.op[1].regs->reg_num; | |
4087 | if (flag_code == CODE_64BIT || base_regnum < 4) | |
4088 | { | |
4089 | i.types[1].bitfield.byte = 1; | |
4090 | /* Ignore the suffix. */ | |
4091 | i.suffix = 0; | |
7697afb6 JB |
4092 | /* Convert to byte registers. */ |
4093 | if (i.types[1].bitfield.word) | |
4094 | j = 16; | |
4095 | else if (i.types[1].bitfield.dword) | |
4096 | j = 32; | |
4097 | else | |
4098 | j = 48; | |
4099 | if (!(i.op[1].regs->reg_flags & RegRex) && base_regnum < 4) | |
4100 | j += 8; | |
4101 | i.op[1].regs -= j; | |
b6f8c7c4 L |
4102 | } |
4103 | } | |
4104 | else if (flag_code == CODE_64BIT | |
72aea328 | 4105 | && !is_any_vex_encoding (&i.tm) |
d3d50934 L |
4106 | && ((i.types[1].bitfield.qword |
4107 | && i.reg_operands == 1 | |
b6f8c7c4 L |
4108 | && i.imm_operands == 1 |
4109 | && i.op[0].imms->X_op == O_constant | |
507916b8 | 4110 | && ((i.tm.base_opcode == 0xb8 |
b6f8c7c4 L |
4111 | && i.tm.extension_opcode == None |
4112 | && fits_in_unsigned_long (i.op[0].imms->X_add_number)) | |
4113 | || (fits_in_imm31 (i.op[0].imms->X_add_number) | |
72aea328 JB |
4114 | && ((i.tm.base_opcode == 0x24 |
4115 | || i.tm.base_opcode == 0xa8) | |
b6f8c7c4 L |
4116 | || (i.tm.base_opcode == 0x80 |
4117 | && i.tm.extension_opcode == 0x4) | |
4118 | || ((i.tm.base_opcode == 0xf6 | |
507916b8 | 4119 | || (i.tm.base_opcode | 1) == 0xc7) |
b8364fa7 JB |
4120 | && i.tm.extension_opcode == 0x0))) |
4121 | || (fits_in_imm7 (i.op[0].imms->X_add_number) | |
4122 | && i.tm.base_opcode == 0x83 | |
4123 | && i.tm.extension_opcode == 0x4))) | |
d3d50934 L |
4124 | || (i.types[0].bitfield.qword |
4125 | && ((i.reg_operands == 2 | |
4126 | && i.op[0].regs == i.op[1].regs | |
72aea328 JB |
4127 | && (i.tm.base_opcode == 0x30 |
4128 | || i.tm.base_opcode == 0x28)) | |
d3d50934 L |
4129 | || (i.reg_operands == 1 |
4130 | && i.operands == 1 | |
72aea328 | 4131 | && i.tm.base_opcode == 0x30))))) |
b6f8c7c4 L |
4132 | { |
4133 | /* Optimize: -O: | |
4134 | andq $imm31, %r64 -> andl $imm31, %r32 | |
b8364fa7 | 4135 | andq $imm7, %r64 -> andl $imm7, %r32 |
b6f8c7c4 L |
4136 | testq $imm31, %r64 -> testl $imm31, %r32 |
4137 | xorq %r64, %r64 -> xorl %r32, %r32 | |
4138 | subq %r64, %r64 -> subl %r32, %r32 | |
4139 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4140 | movq $imm32, %r64 -> movl $imm32, %r32 | |
4141 | */ | |
4142 | i.tm.opcode_modifier.norex64 = 1; | |
507916b8 | 4143 | if (i.tm.base_opcode == 0xb8 || (i.tm.base_opcode | 1) == 0xc7) |
b6f8c7c4 L |
4144 | { |
4145 | /* Handle | |
4146 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4147 | movq $imm32, %r64 -> movl $imm32, %r32 | |
4148 | */ | |
4149 | i.tm.operand_types[0].bitfield.imm32 = 1; | |
4150 | i.tm.operand_types[0].bitfield.imm32s = 0; | |
4151 | i.tm.operand_types[0].bitfield.imm64 = 0; | |
4152 | i.types[0].bitfield.imm32 = 1; | |
4153 | i.types[0].bitfield.imm32s = 0; | |
4154 | i.types[0].bitfield.imm64 = 0; | |
4155 | i.types[1].bitfield.dword = 1; | |
4156 | i.types[1].bitfield.qword = 0; | |
507916b8 | 4157 | if ((i.tm.base_opcode | 1) == 0xc7) |
b6f8c7c4 L |
4158 | { |
4159 | /* Handle | |
4160 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4161 | */ | |
507916b8 | 4162 | i.tm.base_opcode = 0xb8; |
b6f8c7c4 | 4163 | i.tm.extension_opcode = None; |
507916b8 | 4164 | i.tm.opcode_modifier.w = 0; |
b6f8c7c4 L |
4165 | i.tm.opcode_modifier.modrm = 0; |
4166 | } | |
4167 | } | |
4168 | } | |
5641ec01 JB |
4169 | else if (optimize > 1 |
4170 | && !optimize_for_space | |
72aea328 | 4171 | && !is_any_vex_encoding (&i.tm) |
5641ec01 JB |
4172 | && i.reg_operands == 2 |
4173 | && i.op[0].regs == i.op[1].regs | |
4174 | && ((i.tm.base_opcode & ~(Opcode_D | 1)) == 0x8 | |
4175 | || (i.tm.base_opcode & ~(Opcode_D | 1)) == 0x20) | |
4176 | && (flag_code != CODE_64BIT || !i.types[0].bitfield.dword)) | |
4177 | { | |
4178 | /* Optimize: -O2: | |
4179 | andb %rN, %rN -> testb %rN, %rN | |
4180 | andw %rN, %rN -> testw %rN, %rN | |
4181 | andq %rN, %rN -> testq %rN, %rN | |
4182 | orb %rN, %rN -> testb %rN, %rN | |
4183 | orw %rN, %rN -> testw %rN, %rN | |
4184 | orq %rN, %rN -> testq %rN, %rN | |
4185 | ||
4186 | and outside of 64-bit mode | |
4187 | ||
4188 | andl %rN, %rN -> testl %rN, %rN | |
4189 | orl %rN, %rN -> testl %rN, %rN | |
4190 | */ | |
4191 | i.tm.base_opcode = 0x84 | (i.tm.base_opcode & 1); | |
4192 | } | |
99112332 | 4193 | else if (i.reg_operands == 3 |
b6f8c7c4 L |
4194 | && i.op[0].regs == i.op[1].regs |
4195 | && !i.types[2].bitfield.xmmword | |
4196 | && (i.tm.opcode_modifier.vex | |
7a69eac3 | 4197 | || ((!i.mask || i.mask->zeroing) |
b6f8c7c4 | 4198 | && !i.rounding |
e771e7c9 | 4199 | && is_evex_encoding (&i.tm) |
80c34c38 | 4200 | && (i.vec_encoding != vex_encoding_evex |
dd22218c | 4201 | || cpu_arch_isa_flags.bitfield.cpuavx512vl |
80c34c38 | 4202 | || i.tm.cpu_flags.bitfield.cpuavx512vl |
7091c612 | 4203 | || (i.tm.operand_types[2].bitfield.zmmword |
dd22218c | 4204 | && i.types[2].bitfield.ymmword)))) |
b6f8c7c4 L |
4205 | && ((i.tm.base_opcode == 0x55 |
4206 | || i.tm.base_opcode == 0x6655 | |
4207 | || i.tm.base_opcode == 0x66df | |
4208 | || i.tm.base_opcode == 0x57 | |
4209 | || i.tm.base_opcode == 0x6657 | |
8305403a L |
4210 | || i.tm.base_opcode == 0x66ef |
4211 | || i.tm.base_opcode == 0x66f8 | |
4212 | || i.tm.base_opcode == 0x66f9 | |
4213 | || i.tm.base_opcode == 0x66fa | |
1424ad86 JB |
4214 | || i.tm.base_opcode == 0x66fb |
4215 | || i.tm.base_opcode == 0x42 | |
4216 | || i.tm.base_opcode == 0x6642 | |
4217 | || i.tm.base_opcode == 0x47 | |
4218 | || i.tm.base_opcode == 0x6647) | |
b6f8c7c4 L |
4219 | && i.tm.extension_opcode == None)) |
4220 | { | |
99112332 | 4221 | /* Optimize: -O1: |
8305403a L |
4222 | VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd, |
4223 | vpsubq and vpsubw: | |
b6f8c7c4 L |
4224 | EVEX VOP %zmmM, %zmmM, %zmmN |
4225 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4226 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4227 | EVEX VOP %ymmM, %ymmM, %ymmN |
4228 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4229 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4230 | VEX VOP %ymmM, %ymmM, %ymmN |
4231 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4232 | VOP, one of vpandn and vpxor: | |
4233 | VEX VOP %ymmM, %ymmM, %ymmN | |
4234 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4235 | VOP, one of vpandnd and vpandnq: | |
4236 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4237 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4238 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4239 | EVEX VOP %ymmM, %ymmM, %ymmN |
4240 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4241 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4242 | VOP, one of vpxord and vpxorq: |
4243 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4244 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4245 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4246 | EVEX VOP %ymmM, %ymmM, %ymmN |
4247 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4248 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
1424ad86 JB |
4249 | VOP, one of kxord and kxorq: |
4250 | VEX VOP %kM, %kM, %kN | |
4251 | -> VEX kxorw %kM, %kM, %kN | |
4252 | VOP, one of kandnd and kandnq: | |
4253 | VEX VOP %kM, %kM, %kN | |
4254 | -> VEX kandnw %kM, %kM, %kN | |
b6f8c7c4 | 4255 | */ |
e771e7c9 | 4256 | if (is_evex_encoding (&i.tm)) |
b6f8c7c4 | 4257 | { |
7b1d7ca1 | 4258 | if (i.vec_encoding != vex_encoding_evex) |
b6f8c7c4 L |
4259 | { |
4260 | i.tm.opcode_modifier.vex = VEX128; | |
4261 | i.tm.opcode_modifier.vexw = VEXW0; | |
4262 | i.tm.opcode_modifier.evex = 0; | |
4263 | } | |
7b1d7ca1 | 4264 | else if (optimize > 1) |
dd22218c L |
4265 | i.tm.opcode_modifier.evex = EVEX128; |
4266 | else | |
4267 | return; | |
b6f8c7c4 | 4268 | } |
f74a6307 | 4269 | else if (i.tm.operand_types[0].bitfield.class == RegMask) |
1424ad86 JB |
4270 | { |
4271 | i.tm.base_opcode &= 0xff; | |
4272 | i.tm.opcode_modifier.vexw = VEXW0; | |
4273 | } | |
b6f8c7c4 L |
4274 | else |
4275 | i.tm.opcode_modifier.vex = VEX128; | |
4276 | ||
4277 | if (i.tm.opcode_modifier.vex) | |
4278 | for (j = 0; j < 3; j++) | |
4279 | { | |
4280 | i.types[j].bitfield.xmmword = 1; | |
4281 | i.types[j].bitfield.ymmword = 0; | |
4282 | } | |
4283 | } | |
392a5972 | 4284 | else if (i.vec_encoding != vex_encoding_evex |
97ed31ae | 4285 | && !i.types[0].bitfield.zmmword |
392a5972 | 4286 | && !i.types[1].bitfield.zmmword |
97ed31ae | 4287 | && !i.mask |
a0a1771e | 4288 | && !i.broadcast |
97ed31ae | 4289 | && is_evex_encoding (&i.tm) |
392a5972 L |
4290 | && ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x666f |
4291 | || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf36f | |
a0a1771e JB |
4292 | || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f |
4293 | || (i.tm.base_opcode & ~4) == 0x66db | |
4294 | || (i.tm.base_opcode & ~4) == 0x66eb) | |
97ed31ae L |
4295 | && i.tm.extension_opcode == None) |
4296 | { | |
4297 | /* Optimize: -O1: | |
4298 | VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, | |
4299 | vmovdqu32 and vmovdqu64: | |
4300 | EVEX VOP %xmmM, %xmmN | |
4301 | -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16) | |
4302 | EVEX VOP %ymmM, %ymmN | |
4303 | -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16) | |
4304 | EVEX VOP %xmmM, mem | |
4305 | -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16) | |
4306 | EVEX VOP %ymmM, mem | |
4307 | -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16) | |
4308 | EVEX VOP mem, %xmmN | |
4309 | -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16) | |
4310 | EVEX VOP mem, %ymmN | |
4311 | -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16) | |
a0a1771e JB |
4312 | VOP, one of vpand, vpandn, vpor, vpxor: |
4313 | EVEX VOP{d,q} %xmmL, %xmmM, %xmmN | |
4314 | -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16) | |
4315 | EVEX VOP{d,q} %ymmL, %ymmM, %ymmN | |
4316 | -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16) | |
4317 | EVEX VOP{d,q} mem, %xmmM, %xmmN | |
4318 | -> VEX VOP mem, %xmmM, %xmmN (M and N < 16) | |
4319 | EVEX VOP{d,q} mem, %ymmM, %ymmN | |
4320 | -> VEX VOP mem, %ymmM, %ymmN (M and N < 16) | |
97ed31ae | 4321 | */ |
a0a1771e | 4322 | for (j = 0; j < i.operands; j++) |
392a5972 L |
4323 | if (operand_type_check (i.types[j], disp) |
4324 | && i.op[j].disps->X_op == O_constant) | |
4325 | { | |
4326 | /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix | |
4327 | has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4 | |
4328 | bytes, we choose EVEX Disp8 over VEX Disp32. */ | |
4329 | int evex_disp8, vex_disp8; | |
4330 | unsigned int memshift = i.memshift; | |
4331 | offsetT n = i.op[j].disps->X_add_number; | |
4332 | ||
4333 | evex_disp8 = fits_in_disp8 (n); | |
4334 | i.memshift = 0; | |
4335 | vex_disp8 = fits_in_disp8 (n); | |
4336 | if (evex_disp8 != vex_disp8) | |
4337 | { | |
4338 | i.memshift = memshift; | |
4339 | return; | |
4340 | } | |
4341 | ||
4342 | i.types[j].bitfield.disp8 = vex_disp8; | |
4343 | break; | |
4344 | } | |
4345 | if ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f) | |
4346 | i.tm.base_opcode ^= 0xf36f ^ 0xf26f; | |
97ed31ae L |
4347 | i.tm.opcode_modifier.vex |
4348 | = i.types[0].bitfield.ymmword ? VEX256 : VEX128; | |
4349 | i.tm.opcode_modifier.vexw = VEXW0; | |
79dec6b7 JB |
4350 | /* VPAND, VPOR, and VPXOR are commutative. */ |
4351 | if (i.reg_operands == 3 && i.tm.base_opcode != 0x66df) | |
4352 | i.tm.opcode_modifier.commutative = 1; | |
97ed31ae L |
4353 | i.tm.opcode_modifier.evex = 0; |
4354 | i.tm.opcode_modifier.masking = 0; | |
a0a1771e | 4355 | i.tm.opcode_modifier.broadcast = 0; |
97ed31ae L |
4356 | i.tm.opcode_modifier.disp8memshift = 0; |
4357 | i.memshift = 0; | |
a0a1771e JB |
4358 | if (j < i.operands) |
4359 | i.types[j].bitfield.disp8 | |
4360 | = fits_in_disp8 (i.op[j].disps->X_add_number); | |
97ed31ae | 4361 | } |
b6f8c7c4 L |
4362 | } |
4363 | ||
ae531041 L |
4364 | /* Return non-zero for load instruction. */ |
4365 | ||
4366 | static int | |
4367 | load_insn_p (void) | |
4368 | { | |
4369 | unsigned int dest; | |
4370 | int any_vex_p = is_any_vex_encoding (&i.tm); | |
4371 | unsigned int base_opcode = i.tm.base_opcode | 1; | |
4372 | ||
4373 | if (!any_vex_p) | |
4374 | { | |
a09f656b | 4375 | /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0, |
4376 | prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn, | |
4377 | bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */ | |
4378 | if (i.tm.opcode_modifier.anysize) | |
ae531041 L |
4379 | return 0; |
4380 | ||
a09f656b | 4381 | /* pop, popf, popa. */ |
4382 | if (strcmp (i.tm.name, "pop") == 0 | |
4383 | || i.tm.base_opcode == 0x9d | |
4384 | || i.tm.base_opcode == 0x61) | |
ae531041 L |
4385 | return 1; |
4386 | ||
4387 | /* movs, cmps, lods, scas. */ | |
4388 | if ((i.tm.base_opcode | 0xb) == 0xaf) | |
4389 | return 1; | |
4390 | ||
a09f656b | 4391 | /* outs, xlatb. */ |
4392 | if (base_opcode == 0x6f | |
4393 | || i.tm.base_opcode == 0xd7) | |
ae531041 | 4394 | return 1; |
a09f656b | 4395 | /* NB: For AMD-specific insns with implicit memory operands, |
4396 | they're intentionally not covered. */ | |
ae531041 L |
4397 | } |
4398 | ||
4399 | /* No memory operand. */ | |
4400 | if (!i.mem_operands) | |
4401 | return 0; | |
4402 | ||
4403 | if (any_vex_p) | |
4404 | { | |
4405 | /* vldmxcsr. */ | |
4406 | if (i.tm.base_opcode == 0xae | |
4407 | && i.tm.opcode_modifier.vex | |
4408 | && i.tm.opcode_modifier.vexopcode == VEX0F | |
4409 | && i.tm.extension_opcode == 2) | |
4410 | return 1; | |
4411 | } | |
4412 | else | |
4413 | { | |
4414 | /* test, not, neg, mul, imul, div, idiv. */ | |
4415 | if ((i.tm.base_opcode == 0xf6 || i.tm.base_opcode == 0xf7) | |
4416 | && i.tm.extension_opcode != 1) | |
4417 | return 1; | |
4418 | ||
4419 | /* inc, dec. */ | |
4420 | if (base_opcode == 0xff && i.tm.extension_opcode <= 1) | |
4421 | return 1; | |
4422 | ||
4423 | /* add, or, adc, sbb, and, sub, xor, cmp. */ | |
4424 | if (i.tm.base_opcode >= 0x80 && i.tm.base_opcode <= 0x83) | |
4425 | return 1; | |
4426 | ||
4427 | /* bt, bts, btr, btc. */ | |
4428 | if (i.tm.base_opcode == 0xfba | |
4429 | && (i.tm.extension_opcode >= 4 && i.tm.extension_opcode <= 7)) | |
4430 | return 1; | |
4431 | ||
4432 | /* rol, ror, rcl, rcr, shl/sal, shr, sar. */ | |
4433 | if ((base_opcode == 0xc1 | |
4434 | || (i.tm.base_opcode >= 0xd0 && i.tm.base_opcode <= 0xd3)) | |
4435 | && i.tm.extension_opcode != 6) | |
4436 | return 1; | |
4437 | ||
4438 | /* cmpxchg8b, cmpxchg16b, xrstors. */ | |
4439 | if (i.tm.base_opcode == 0xfc7 | |
4440 | && (i.tm.extension_opcode == 1 || i.tm.extension_opcode == 3)) | |
4441 | return 1; | |
4442 | ||
4443 | /* fxrstor, ldmxcsr, xrstor. */ | |
4444 | if (i.tm.base_opcode == 0xfae | |
4445 | && (i.tm.extension_opcode == 1 | |
4446 | || i.tm.extension_opcode == 2 | |
4447 | || i.tm.extension_opcode == 5)) | |
4448 | return 1; | |
4449 | ||
4450 | /* lgdt, lidt, lmsw. */ | |
4451 | if (i.tm.base_opcode == 0xf01 | |
4452 | && (i.tm.extension_opcode == 2 | |
4453 | || i.tm.extension_opcode == 3 | |
4454 | || i.tm.extension_opcode == 6)) | |
4455 | return 1; | |
4456 | ||
4457 | /* vmptrld */ | |
4458 | if (i.tm.base_opcode == 0xfc7 | |
4459 | && i.tm.extension_opcode == 6) | |
4460 | return 1; | |
4461 | ||
4462 | /* Check for x87 instructions. */ | |
4463 | if (i.tm.base_opcode >= 0xd8 && i.tm.base_opcode <= 0xdf) | |
4464 | { | |
4465 | /* Skip fst, fstp, fstenv, fstcw. */ | |
4466 | if (i.tm.base_opcode == 0xd9 | |
4467 | && (i.tm.extension_opcode == 2 | |
4468 | || i.tm.extension_opcode == 3 | |
4469 | || i.tm.extension_opcode == 6 | |
4470 | || i.tm.extension_opcode == 7)) | |
4471 | return 0; | |
4472 | ||
4473 | /* Skip fisttp, fist, fistp, fstp. */ | |
4474 | if (i.tm.base_opcode == 0xdb | |
4475 | && (i.tm.extension_opcode == 1 | |
4476 | || i.tm.extension_opcode == 2 | |
4477 | || i.tm.extension_opcode == 3 | |
4478 | || i.tm.extension_opcode == 7)) | |
4479 | return 0; | |
4480 | ||
4481 | /* Skip fisttp, fst, fstp, fsave, fstsw. */ | |
4482 | if (i.tm.base_opcode == 0xdd | |
4483 | && (i.tm.extension_opcode == 1 | |
4484 | || i.tm.extension_opcode == 2 | |
4485 | || i.tm.extension_opcode == 3 | |
4486 | || i.tm.extension_opcode == 6 | |
4487 | || i.tm.extension_opcode == 7)) | |
4488 | return 0; | |
4489 | ||
4490 | /* Skip fisttp, fist, fistp, fbstp, fistp. */ | |
4491 | if (i.tm.base_opcode == 0xdf | |
4492 | && (i.tm.extension_opcode == 1 | |
4493 | || i.tm.extension_opcode == 2 | |
4494 | || i.tm.extension_opcode == 3 | |
4495 | || i.tm.extension_opcode == 6 | |
4496 | || i.tm.extension_opcode == 7)) | |
4497 | return 0; | |
4498 | ||
4499 | return 1; | |
4500 | } | |
4501 | } | |
4502 | ||
4503 | dest = i.operands - 1; | |
4504 | ||
4505 | /* Check fake imm8 operand and 3 source operands. */ | |
4506 | if ((i.tm.opcode_modifier.immext | |
4507 | || i.tm.opcode_modifier.vexsources == VEX3SOURCES) | |
4508 | && i.types[dest].bitfield.imm8) | |
4509 | dest--; | |
4510 | ||
4511 | /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg, xadd */ | |
4512 | if (!any_vex_p | |
4513 | && (base_opcode == 0x1 | |
4514 | || base_opcode == 0x9 | |
4515 | || base_opcode == 0x11 | |
4516 | || base_opcode == 0x19 | |
4517 | || base_opcode == 0x21 | |
4518 | || base_opcode == 0x29 | |
4519 | || base_opcode == 0x31 | |
4520 | || base_opcode == 0x39 | |
4521 | || (i.tm.base_opcode >= 0x84 && i.tm.base_opcode <= 0x87) | |
4522 | || base_opcode == 0xfc1)) | |
4523 | return 1; | |
4524 | ||
4525 | /* Check for load instruction. */ | |
4526 | return (i.types[dest].bitfield.class != ClassNone | |
4527 | || i.types[dest].bitfield.instance == Accum); | |
4528 | } | |
4529 | ||
4530 | /* Output lfence, 0xfaee8, after instruction. */ | |
4531 | ||
4532 | static void | |
4533 | insert_lfence_after (void) | |
4534 | { | |
4535 | if (lfence_after_load && load_insn_p ()) | |
4536 | { | |
a09f656b | 4537 | /* There are also two REP string instructions that require |
4538 | special treatment. Specifically, the compare string (CMPS) | |
4539 | and scan string (SCAS) instructions set EFLAGS in a manner | |
4540 | that depends on the data being compared/scanned. When used | |
4541 | with a REP prefix, the number of iterations may therefore | |
4542 | vary depending on this data. If the data is a program secret | |
4543 | chosen by the adversary using an LVI method, | |
4544 | then this data-dependent behavior may leak some aspect | |
4545 | of the secret. */ | |
4546 | if (((i.tm.base_opcode | 0x1) == 0xa7 | |
4547 | || (i.tm.base_opcode | 0x1) == 0xaf) | |
4548 | && i.prefix[REP_PREFIX]) | |
4549 | { | |
4550 | as_warn (_("`%s` changes flags which would affect control flow behavior"), | |
4551 | i.tm.name); | |
4552 | } | |
ae531041 L |
4553 | char *p = frag_more (3); |
4554 | *p++ = 0xf; | |
4555 | *p++ = 0xae; | |
4556 | *p = 0xe8; | |
4557 | } | |
4558 | } | |
4559 | ||
4560 | /* Output lfence, 0xfaee8, before instruction. */ | |
4561 | ||
4562 | static void | |
4563 | insert_lfence_before (void) | |
4564 | { | |
4565 | char *p; | |
4566 | ||
4567 | if (is_any_vex_encoding (&i.tm)) | |
4568 | return; | |
4569 | ||
4570 | if (i.tm.base_opcode == 0xff | |
4571 | && (i.tm.extension_opcode == 2 || i.tm.extension_opcode == 4)) | |
4572 | { | |
4573 | /* Insert lfence before indirect branch if needed. */ | |
4574 | ||
4575 | if (lfence_before_indirect_branch == lfence_branch_none) | |
4576 | return; | |
4577 | ||
4578 | if (i.operands != 1) | |
4579 | abort (); | |
4580 | ||
4581 | if (i.reg_operands == 1) | |
4582 | { | |
4583 | /* Indirect branch via register. Don't insert lfence with | |
4584 | -mlfence-after-load=yes. */ | |
4585 | if (lfence_after_load | |
4586 | || lfence_before_indirect_branch == lfence_branch_memory) | |
4587 | return; | |
4588 | } | |
4589 | else if (i.mem_operands == 1 | |
4590 | && lfence_before_indirect_branch != lfence_branch_register) | |
4591 | { | |
4592 | as_warn (_("indirect `%s` with memory operand should be avoided"), | |
4593 | i.tm.name); | |
4594 | return; | |
4595 | } | |
4596 | else | |
4597 | return; | |
4598 | ||
4599 | if (last_insn.kind != last_insn_other | |
4600 | && last_insn.seg == now_seg) | |
4601 | { | |
4602 | as_warn_where (last_insn.file, last_insn.line, | |
4603 | _("`%s` skips -mlfence-before-indirect-branch on `%s`"), | |
4604 | last_insn.name, i.tm.name); | |
4605 | return; | |
4606 | } | |
4607 | ||
4608 | p = frag_more (3); | |
4609 | *p++ = 0xf; | |
4610 | *p++ = 0xae; | |
4611 | *p = 0xe8; | |
4612 | return; | |
4613 | } | |
4614 | ||
503648e4 | 4615 | /* Output or/not/shl and lfence before near ret. */ |
ae531041 L |
4616 | if (lfence_before_ret != lfence_before_ret_none |
4617 | && (i.tm.base_opcode == 0xc2 | |
503648e4 | 4618 | || i.tm.base_opcode == 0xc3)) |
ae531041 L |
4619 | { |
4620 | if (last_insn.kind != last_insn_other | |
4621 | && last_insn.seg == now_seg) | |
4622 | { | |
4623 | as_warn_where (last_insn.file, last_insn.line, | |
4624 | _("`%s` skips -mlfence-before-ret on `%s`"), | |
4625 | last_insn.name, i.tm.name); | |
4626 | return; | |
4627 | } | |
a09f656b | 4628 | |
a09f656b | 4629 | /* Near ret ingore operand size override under CPU64. */ |
503648e4 | 4630 | char prefix = flag_code == CODE_64BIT |
4631 | ? 0x48 | |
4632 | : i.prefix[DATA_PREFIX] ? 0x66 : 0x0; | |
a09f656b | 4633 | |
4634 | if (lfence_before_ret == lfence_before_ret_not) | |
4635 | { | |
4636 | /* not: 0xf71424, may add prefix | |
4637 | for operand size override or 64-bit code. */ | |
4638 | p = frag_more ((prefix ? 2 : 0) + 6 + 3); | |
4639 | if (prefix) | |
4640 | *p++ = prefix; | |
ae531041 L |
4641 | *p++ = 0xf7; |
4642 | *p++ = 0x14; | |
4643 | *p++ = 0x24; | |
a09f656b | 4644 | if (prefix) |
4645 | *p++ = prefix; | |
ae531041 L |
4646 | *p++ = 0xf7; |
4647 | *p++ = 0x14; | |
4648 | *p++ = 0x24; | |
4649 | } | |
a09f656b | 4650 | else |
4651 | { | |
4652 | p = frag_more ((prefix ? 1 : 0) + 4 + 3); | |
4653 | if (prefix) | |
4654 | *p++ = prefix; | |
4655 | if (lfence_before_ret == lfence_before_ret_or) | |
4656 | { | |
4657 | /* or: 0x830c2400, may add prefix | |
4658 | for operand size override or 64-bit code. */ | |
4659 | *p++ = 0x83; | |
4660 | *p++ = 0x0c; | |
4661 | } | |
4662 | else | |
4663 | { | |
4664 | /* shl: 0xc1242400, may add prefix | |
4665 | for operand size override or 64-bit code. */ | |
4666 | *p++ = 0xc1; | |
4667 | *p++ = 0x24; | |
4668 | } | |
4669 | ||
4670 | *p++ = 0x24; | |
4671 | *p++ = 0x0; | |
4672 | } | |
4673 | ||
ae531041 L |
4674 | *p++ = 0xf; |
4675 | *p++ = 0xae; | |
4676 | *p = 0xe8; | |
4677 | } | |
4678 | } | |
4679 | ||
252b5132 RH |
4680 | /* This is the guts of the machine-dependent assembler. LINE points to a |
4681 | machine dependent instruction. This function is supposed to emit | |
4682 | the frags/bytes it assembles to. */ | |
4683 | ||
4684 | void | |
65da13b5 | 4685 | md_assemble (char *line) |
252b5132 | 4686 | { |
40fb9820 | 4687 | unsigned int j; |
83b16ac6 | 4688 | char mnemonic[MAX_MNEM_SIZE], mnem_suffix; |
d3ce72d0 | 4689 | const insn_template *t; |
252b5132 | 4690 | |
47926f60 | 4691 | /* Initialize globals. */ |
252b5132 RH |
4692 | memset (&i, '\0', sizeof (i)); |
4693 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 4694 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
4695 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
4696 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 4697 | save_stack_p = save_stack; |
252b5132 RH |
4698 | |
4699 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
4700 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 4701 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 4702 | |
29b0f896 AM |
4703 | line = parse_insn (line, mnemonic); |
4704 | if (line == NULL) | |
4705 | return; | |
83b16ac6 | 4706 | mnem_suffix = i.suffix; |
252b5132 | 4707 | |
29b0f896 | 4708 | line = parse_operands (line, mnemonic); |
ee86248c | 4709 | this_operand = -1; |
8325cc63 JB |
4710 | xfree (i.memop1_string); |
4711 | i.memop1_string = NULL; | |
29b0f896 AM |
4712 | if (line == NULL) |
4713 | return; | |
252b5132 | 4714 | |
29b0f896 AM |
4715 | /* Now we've parsed the mnemonic into a set of templates, and have the |
4716 | operands at hand. */ | |
4717 | ||
b630c145 JB |
4718 | /* All Intel opcodes have reversed operands except for "bound", "enter", |
4719 | "monitor*", "mwait*", "tpause", and "umwait". We also don't reverse | |
4720 | intersegment "jmp" and "call" instructions with 2 immediate operands so | |
4721 | that the immediate segment precedes the offset, as it does when in AT&T | |
4722 | mode. */ | |
4d456e3d L |
4723 | if (intel_syntax |
4724 | && i.operands > 1 | |
29b0f896 | 4725 | && (strcmp (mnemonic, "bound") != 0) |
30123838 | 4726 | && (strcmp (mnemonic, "invlpga") != 0) |
eedb0f2c JB |
4727 | && (strncmp (mnemonic, "monitor", 7) != 0) |
4728 | && (strncmp (mnemonic, "mwait", 5) != 0) | |
b630c145 JB |
4729 | && (strcmp (mnemonic, "tpause") != 0) |
4730 | && (strcmp (mnemonic, "umwait") != 0) | |
40fb9820 L |
4731 | && !(operand_type_check (i.types[0], imm) |
4732 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
4733 | swap_operands (); |
4734 | ||
ec56d5c0 JB |
4735 | /* The order of the immediates should be reversed |
4736 | for 2 immediates extrq and insertq instructions */ | |
4737 | if (i.imm_operands == 2 | |
4738 | && (strcmp (mnemonic, "extrq") == 0 | |
4739 | || strcmp (mnemonic, "insertq") == 0)) | |
4740 | swap_2_operands (0, 1); | |
4741 | ||
29b0f896 AM |
4742 | if (i.imm_operands) |
4743 | optimize_imm (); | |
4744 | ||
b300c311 L |
4745 | /* Don't optimize displacement for movabs since it only takes 64bit |
4746 | displacement. */ | |
4747 | if (i.disp_operands | |
a501d77e | 4748 | && i.disp_encoding != disp_encoding_32bit |
862be3fb L |
4749 | && (flag_code != CODE_64BIT |
4750 | || strcmp (mnemonic, "movabs") != 0)) | |
4751 | optimize_disp (); | |
29b0f896 AM |
4752 | |
4753 | /* Next, we find a template that matches the given insn, | |
4754 | making sure the overlap of the given operands types is consistent | |
4755 | with the template operand types. */ | |
252b5132 | 4756 | |
83b16ac6 | 4757 | if (!(t = match_template (mnem_suffix))) |
29b0f896 | 4758 | return; |
252b5132 | 4759 | |
7bab8ab5 | 4760 | if (sse_check != check_none |
81f8a913 | 4761 | && !i.tm.opcode_modifier.noavx |
6e3e5c9e | 4762 | && !i.tm.cpu_flags.bitfield.cpuavx |
569d50f1 | 4763 | && !i.tm.cpu_flags.bitfield.cpuavx512f |
daf50ae7 L |
4764 | && (i.tm.cpu_flags.bitfield.cpusse |
4765 | || i.tm.cpu_flags.bitfield.cpusse2 | |
4766 | || i.tm.cpu_flags.bitfield.cpusse3 | |
4767 | || i.tm.cpu_flags.bitfield.cpussse3 | |
4768 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
6e3e5c9e JB |
4769 | || i.tm.cpu_flags.bitfield.cpusse4_2 |
4770 | || i.tm.cpu_flags.bitfield.cpupclmul | |
4771 | || i.tm.cpu_flags.bitfield.cpuaes | |
569d50f1 | 4772 | || i.tm.cpu_flags.bitfield.cpusha |
6e3e5c9e | 4773 | || i.tm.cpu_flags.bitfield.cpugfni)) |
daf50ae7 | 4774 | { |
7bab8ab5 | 4775 | (sse_check == check_warning |
daf50ae7 L |
4776 | ? as_warn |
4777 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); | |
4778 | } | |
4779 | ||
40fb9820 | 4780 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
4781 | if (!add_prefix (FWAIT_OPCODE)) |
4782 | return; | |
252b5132 | 4783 | |
d5de92cf L |
4784 | /* Check if REP prefix is OK. */ |
4785 | if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok) | |
4786 | { | |
4787 | as_bad (_("invalid instruction `%s' after `%s'"), | |
4788 | i.tm.name, i.rep_prefix); | |
4789 | return; | |
4790 | } | |
4791 | ||
c1ba0266 L |
4792 | /* Check for lock without a lockable instruction. Destination operand |
4793 | must be memory unless it is xchg (0x86). */ | |
c32fa91d L |
4794 | if (i.prefix[LOCK_PREFIX] |
4795 | && (!i.tm.opcode_modifier.islockable | |
c1ba0266 L |
4796 | || i.mem_operands == 0 |
4797 | || (i.tm.base_opcode != 0x86 | |
8dc0818e | 4798 | && !(i.flags[i.operands - 1] & Operand_Mem)))) |
c32fa91d L |
4799 | { |
4800 | as_bad (_("expecting lockable instruction after `lock'")); | |
4801 | return; | |
4802 | } | |
4803 | ||
40d231b4 JB |
4804 | /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */ |
4805 | if (i.prefix[DATA_PREFIX] | |
4806 | && (is_any_vex_encoding (&i.tm) | |
4807 | || i.tm.operand_types[i.imm_operands].bitfield.class >= RegMMX | |
4808 | || i.tm.operand_types[i.imm_operands + 1].bitfield.class >= RegMMX)) | |
7a8655d2 JB |
4809 | { |
4810 | as_bad (_("data size prefix invalid with `%s'"), i.tm.name); | |
4811 | return; | |
4812 | } | |
4813 | ||
42164a71 | 4814 | /* Check if HLE prefix is OK. */ |
165de32a | 4815 | if (i.hle_prefix && !check_hle ()) |
42164a71 L |
4816 | return; |
4817 | ||
7e8b059b L |
4818 | /* Check BND prefix. */ |
4819 | if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) | |
4820 | as_bad (_("expecting valid branch instruction after `bnd'")); | |
4821 | ||
04ef582a | 4822 | /* Check NOTRACK prefix. */ |
9fef80d6 L |
4823 | if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok) |
4824 | as_bad (_("expecting indirect branch instruction after `notrack'")); | |
04ef582a | 4825 | |
327e8c42 JB |
4826 | if (i.tm.cpu_flags.bitfield.cpumpx) |
4827 | { | |
4828 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
4829 | as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); | |
4830 | else if (flag_code != CODE_16BIT | |
4831 | ? i.prefix[ADDR_PREFIX] | |
4832 | : i.mem_operands && !i.prefix[ADDR_PREFIX]) | |
4833 | as_bad (_("16-bit address isn't allowed in MPX instructions")); | |
4834 | } | |
7e8b059b L |
4835 | |
4836 | /* Insert BND prefix. */ | |
76d3a78a JB |
4837 | if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok) |
4838 | { | |
4839 | if (!i.prefix[BND_PREFIX]) | |
4840 | add_prefix (BND_PREFIX_OPCODE); | |
4841 | else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE) | |
4842 | { | |
4843 | as_warn (_("replacing `rep'/`repe' prefix by `bnd'")); | |
4844 | i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE; | |
4845 | } | |
4846 | } | |
7e8b059b | 4847 | |
29b0f896 | 4848 | /* Check string instruction segment overrides. */ |
51c8edf6 | 4849 | if (i.tm.opcode_modifier.isstring >= IS_STRING_ES_OP0) |
29b0f896 | 4850 | { |
51c8edf6 | 4851 | gas_assert (i.mem_operands); |
29b0f896 | 4852 | if (!check_string ()) |
5dd0794d | 4853 | return; |
fc0763e6 | 4854 | i.disp_operands = 0; |
29b0f896 | 4855 | } |
5dd0794d | 4856 | |
b6f8c7c4 L |
4857 | if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize) |
4858 | optimize_encoding (); | |
4859 | ||
29b0f896 AM |
4860 | if (!process_suffix ()) |
4861 | return; | |
e413e4e9 | 4862 | |
921eafea | 4863 | /* Update operand types and check extended states. */ |
bc0844ae | 4864 | for (j = 0; j < i.operands; j++) |
921eafea L |
4865 | { |
4866 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
4867 | switch (i.tm.operand_types[j].bitfield.class) | |
4868 | { | |
4869 | default: | |
4870 | break; | |
4871 | case RegMMX: | |
4872 | i.xstate |= xstate_mmx; | |
4873 | break; | |
4874 | case RegMask: | |
4875 | i.xstate |= xstate_zmm; | |
4876 | break; | |
4877 | case RegSIMD: | |
4878 | if (i.tm.operand_types[j].bitfield.tmmword) | |
4879 | i.xstate |= xstate_tmm; | |
4880 | else if (i.tm.operand_types[j].bitfield.zmmword) | |
4881 | i.xstate |= xstate_zmm; | |
4882 | else if (i.tm.operand_types[j].bitfield.ymmword) | |
4883 | i.xstate |= xstate_ymm; | |
4884 | else if (i.tm.operand_types[j].bitfield.xmmword) | |
4885 | i.xstate |= xstate_xmm; | |
4886 | break; | |
4887 | } | |
4888 | } | |
bc0844ae | 4889 | |
29b0f896 AM |
4890 | /* Make still unresolved immediate matches conform to size of immediate |
4891 | given in i.suffix. */ | |
4892 | if (!finalize_imm ()) | |
4893 | return; | |
252b5132 | 4894 | |
40fb9820 | 4895 | if (i.types[0].bitfield.imm1) |
29b0f896 | 4896 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 4897 | |
9afe6eb8 L |
4898 | /* We only need to check those implicit registers for instructions |
4899 | with 3 operands or less. */ | |
4900 | if (i.operands <= 3) | |
4901 | for (j = 0; j < i.operands; j++) | |
75e5731b JB |
4902 | if (i.types[j].bitfield.instance != InstanceNone |
4903 | && !i.types[j].bitfield.xmmword) | |
9afe6eb8 | 4904 | i.reg_operands--; |
40fb9820 | 4905 | |
29b0f896 AM |
4906 | /* For insns with operands there are more diddles to do to the opcode. */ |
4907 | if (i.operands) | |
4908 | { | |
4909 | if (!process_operands ()) | |
4910 | return; | |
4911 | } | |
8c190ce0 | 4912 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
4913 | { |
4914 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
4915 | as_warn (_("translating to `%sp'"), i.tm.name); | |
4916 | } | |
252b5132 | 4917 | |
7a8655d2 | 4918 | if (is_any_vex_encoding (&i.tm)) |
9e5e5283 | 4919 | { |
c1dc7af5 | 4920 | if (!cpu_arch_flags.bitfield.cpui286) |
9e5e5283 | 4921 | { |
c1dc7af5 | 4922 | as_bad (_("instruction `%s' isn't supported outside of protected mode."), |
9e5e5283 L |
4923 | i.tm.name); |
4924 | return; | |
4925 | } | |
c0f3af97 | 4926 | |
0b9404fd JB |
4927 | /* Check for explicit REX prefix. */ |
4928 | if (i.prefix[REX_PREFIX] || i.rex_encoding) | |
4929 | { | |
4930 | as_bad (_("REX prefix invalid with `%s'"), i.tm.name); | |
4931 | return; | |
4932 | } | |
4933 | ||
9e5e5283 L |
4934 | if (i.tm.opcode_modifier.vex) |
4935 | build_vex_prefix (t); | |
4936 | else | |
4937 | build_evex_prefix (); | |
0b9404fd JB |
4938 | |
4939 | /* The individual REX.RXBW bits got consumed. */ | |
4940 | i.rex &= REX_OPCODE; | |
9e5e5283 | 4941 | } |
43234a1e | 4942 | |
5dd85c99 SP |
4943 | /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 |
4944 | instructions may define INT_OPCODE as well, so avoid this corner | |
4945 | case for those instructions that use MODRM. */ | |
4946 | if (i.tm.base_opcode == INT_OPCODE | |
a6461c02 SP |
4947 | && !i.tm.opcode_modifier.modrm |
4948 | && i.op[0].imms->X_add_number == 3) | |
29b0f896 AM |
4949 | { |
4950 | i.tm.base_opcode = INT3_OPCODE; | |
4951 | i.imm_operands = 0; | |
4952 | } | |
252b5132 | 4953 | |
0cfa3eb3 JB |
4954 | if ((i.tm.opcode_modifier.jump == JUMP |
4955 | || i.tm.opcode_modifier.jump == JUMP_BYTE | |
4956 | || i.tm.opcode_modifier.jump == JUMP_DWORD) | |
29b0f896 AM |
4957 | && i.op[0].disps->X_op == O_constant) |
4958 | { | |
4959 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
4960 | the absolute address given by the constant. Since ix86 jumps and | |
4961 | calls are pc relative, we need to generate a reloc. */ | |
4962 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
4963 | i.op[0].disps->X_op = O_symbol; | |
4964 | } | |
252b5132 | 4965 | |
29b0f896 AM |
4966 | /* For 8 bit registers we need an empty rex prefix. Also if the |
4967 | instruction already has a prefix, we need to convert old | |
4968 | registers to new ones. */ | |
773f551c | 4969 | |
bab6aec1 | 4970 | if ((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte |
29b0f896 | 4971 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
bab6aec1 | 4972 | || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte |
29b0f896 | 4973 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
bab6aec1 JB |
4974 | || (((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte) |
4975 | || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte)) | |
29b0f896 AM |
4976 | && i.rex != 0)) |
4977 | { | |
4978 | int x; | |
726c5dcd | 4979 | |
29b0f896 AM |
4980 | i.rex |= REX_OPCODE; |
4981 | for (x = 0; x < 2; x++) | |
4982 | { | |
4983 | /* Look for 8 bit operand that uses old registers. */ | |
bab6aec1 | 4984 | if (i.types[x].bitfield.class == Reg && i.types[x].bitfield.byte |
29b0f896 | 4985 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 4986 | { |
3f93af61 | 4987 | gas_assert (!(i.op[x].regs->reg_flags & RegRex)); |
29b0f896 AM |
4988 | /* In case it is "hi" register, give up. */ |
4989 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 4990 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 4991 | "instruction requiring REX prefix."), |
a540244d | 4992 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 4993 | |
29b0f896 AM |
4994 | /* Otherwise it is equivalent to the extended register. |
4995 | Since the encoding doesn't change this is merely | |
4996 | cosmetic cleanup for debug output. */ | |
4997 | ||
4998 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 4999 | } |
29b0f896 AM |
5000 | } |
5001 | } | |
773f551c | 5002 | |
6b6b6807 L |
5003 | if (i.rex == 0 && i.rex_encoding) |
5004 | { | |
5005 | /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand | |
3f93af61 | 5006 | that uses legacy register. If it is "hi" register, don't add |
6b6b6807 L |
5007 | the REX_OPCODE byte. */ |
5008 | int x; | |
5009 | for (x = 0; x < 2; x++) | |
bab6aec1 | 5010 | if (i.types[x].bitfield.class == Reg |
6b6b6807 L |
5011 | && i.types[x].bitfield.byte |
5012 | && (i.op[x].regs->reg_flags & RegRex64) == 0 | |
5013 | && i.op[x].regs->reg_num > 3) | |
5014 | { | |
3f93af61 | 5015 | gas_assert (!(i.op[x].regs->reg_flags & RegRex)); |
6b6b6807 L |
5016 | i.rex_encoding = FALSE; |
5017 | break; | |
5018 | } | |
5019 | ||
5020 | if (i.rex_encoding) | |
5021 | i.rex = REX_OPCODE; | |
5022 | } | |
5023 | ||
7ab9ffdd | 5024 | if (i.rex != 0) |
29b0f896 AM |
5025 | add_prefix (REX_OPCODE | i.rex); |
5026 | ||
ae531041 L |
5027 | insert_lfence_before (); |
5028 | ||
29b0f896 AM |
5029 | /* We are ready to output the insn. */ |
5030 | output_insn (); | |
e379e5f3 | 5031 | |
ae531041 L |
5032 | insert_lfence_after (); |
5033 | ||
e379e5f3 L |
5034 | last_insn.seg = now_seg; |
5035 | ||
5036 | if (i.tm.opcode_modifier.isprefix) | |
5037 | { | |
5038 | last_insn.kind = last_insn_prefix; | |
5039 | last_insn.name = i.tm.name; | |
5040 | last_insn.file = as_where (&last_insn.line); | |
5041 | } | |
5042 | else | |
5043 | last_insn.kind = last_insn_other; | |
29b0f896 AM |
5044 | } |
5045 | ||
5046 | static char * | |
e3bb37b5 | 5047 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
5048 | { |
5049 | char *l = line; | |
5050 | char *token_start = l; | |
5051 | char *mnem_p; | |
5c6af06e | 5052 | int supported; |
d3ce72d0 | 5053 | const insn_template *t; |
b6169b20 | 5054 | char *dot_p = NULL; |
29b0f896 | 5055 | |
29b0f896 AM |
5056 | while (1) |
5057 | { | |
5058 | mnem_p = mnemonic; | |
5059 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
5060 | { | |
b6169b20 L |
5061 | if (*mnem_p == '.') |
5062 | dot_p = mnem_p; | |
29b0f896 AM |
5063 | mnem_p++; |
5064 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 5065 | { |
29b0f896 AM |
5066 | as_bad (_("no such instruction: `%s'"), token_start); |
5067 | return NULL; | |
5068 | } | |
5069 | l++; | |
5070 | } | |
5071 | if (!is_space_char (*l) | |
5072 | && *l != END_OF_INSN | |
e44823cf JB |
5073 | && (intel_syntax |
5074 | || (*l != PREFIX_SEPARATOR | |
5075 | && *l != ','))) | |
29b0f896 AM |
5076 | { |
5077 | as_bad (_("invalid character %s in mnemonic"), | |
5078 | output_invalid (*l)); | |
5079 | return NULL; | |
5080 | } | |
5081 | if (token_start == l) | |
5082 | { | |
e44823cf | 5083 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
5084 | as_bad (_("expecting prefix; got nothing")); |
5085 | else | |
5086 | as_bad (_("expecting mnemonic; got nothing")); | |
5087 | return NULL; | |
5088 | } | |
45288df1 | 5089 | |
29b0f896 | 5090 | /* Look up instruction (or prefix) via hash table. */ |
d3ce72d0 | 5091 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
47926f60 | 5092 | |
29b0f896 AM |
5093 | if (*l != END_OF_INSN |
5094 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
5095 | && current_templates | |
40fb9820 | 5096 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 5097 | { |
c6fb90c8 | 5098 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
5099 | { |
5100 | as_bad ((flag_code != CODE_64BIT | |
5101 | ? _("`%s' is only supported in 64-bit mode") | |
5102 | : _("`%s' is not supported in 64-bit mode")), | |
5103 | current_templates->start->name); | |
5104 | return NULL; | |
5105 | } | |
29b0f896 AM |
5106 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
5107 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
673fe0f0 JB |
5108 | if ((current_templates->start->opcode_modifier.size == SIZE16 |
5109 | || current_templates->start->opcode_modifier.size == SIZE32) | |
29b0f896 | 5110 | && flag_code != CODE_64BIT |
673fe0f0 | 5111 | && ((current_templates->start->opcode_modifier.size == SIZE32) |
29b0f896 AM |
5112 | ^ (flag_code == CODE_16BIT))) |
5113 | { | |
5114 | as_bad (_("redundant %s prefix"), | |
5115 | current_templates->start->name); | |
5116 | return NULL; | |
45288df1 | 5117 | } |
86fa6981 | 5118 | if (current_templates->start->opcode_length == 0) |
29b0f896 | 5119 | { |
86fa6981 L |
5120 | /* Handle pseudo prefixes. */ |
5121 | switch (current_templates->start->base_opcode) | |
5122 | { | |
41eb8e88 | 5123 | case Prefix_Disp8: |
86fa6981 L |
5124 | /* {disp8} */ |
5125 | i.disp_encoding = disp_encoding_8bit; | |
5126 | break; | |
41eb8e88 L |
5127 | case Prefix_Disp16: |
5128 | /* {disp16} */ | |
5129 | i.disp_encoding = disp_encoding_16bit; | |
5130 | break; | |
5131 | case Prefix_Disp32: | |
86fa6981 L |
5132 | /* {disp32} */ |
5133 | i.disp_encoding = disp_encoding_32bit; | |
5134 | break; | |
41eb8e88 | 5135 | case Prefix_Load: |
86fa6981 L |
5136 | /* {load} */ |
5137 | i.dir_encoding = dir_encoding_load; | |
5138 | break; | |
41eb8e88 | 5139 | case Prefix_Store: |
86fa6981 L |
5140 | /* {store} */ |
5141 | i.dir_encoding = dir_encoding_store; | |
5142 | break; | |
41eb8e88 | 5143 | case Prefix_VEX: |
42e04b36 L |
5144 | /* {vex} */ |
5145 | i.vec_encoding = vex_encoding_vex; | |
86fa6981 | 5146 | break; |
41eb8e88 | 5147 | case Prefix_VEX3: |
86fa6981 L |
5148 | /* {vex3} */ |
5149 | i.vec_encoding = vex_encoding_vex3; | |
5150 | break; | |
41eb8e88 | 5151 | case Prefix_EVEX: |
86fa6981 L |
5152 | /* {evex} */ |
5153 | i.vec_encoding = vex_encoding_evex; | |
5154 | break; | |
41eb8e88 | 5155 | case Prefix_REX: |
6b6b6807 L |
5156 | /* {rex} */ |
5157 | i.rex_encoding = TRUE; | |
5158 | break; | |
41eb8e88 | 5159 | case Prefix_NoOptimize: |
b6f8c7c4 L |
5160 | /* {nooptimize} */ |
5161 | i.no_optimize = TRUE; | |
5162 | break; | |
86fa6981 L |
5163 | default: |
5164 | abort (); | |
5165 | } | |
5166 | } | |
5167 | else | |
5168 | { | |
5169 | /* Add prefix, checking for repeated prefixes. */ | |
4e9ac44a | 5170 | switch (add_prefix (current_templates->start->base_opcode)) |
86fa6981 | 5171 | { |
4e9ac44a L |
5172 | case PREFIX_EXIST: |
5173 | return NULL; | |
5174 | case PREFIX_DS: | |
d777820b | 5175 | if (current_templates->start->cpu_flags.bitfield.cpuibt) |
4e9ac44a L |
5176 | i.notrack_prefix = current_templates->start->name; |
5177 | break; | |
5178 | case PREFIX_REP: | |
5179 | if (current_templates->start->cpu_flags.bitfield.cpuhle) | |
5180 | i.hle_prefix = current_templates->start->name; | |
5181 | else if (current_templates->start->cpu_flags.bitfield.cpumpx) | |
5182 | i.bnd_prefix = current_templates->start->name; | |
5183 | else | |
5184 | i.rep_prefix = current_templates->start->name; | |
5185 | break; | |
5186 | default: | |
5187 | break; | |
86fa6981 | 5188 | } |
29b0f896 AM |
5189 | } |
5190 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
5191 | token_start = ++l; | |
5192 | } | |
5193 | else | |
5194 | break; | |
5195 | } | |
45288df1 | 5196 | |
30a55f88 | 5197 | if (!current_templates) |
b6169b20 | 5198 | { |
07d5e953 JB |
5199 | /* Deprecated functionality (new code should use pseudo-prefixes instead): |
5200 | Check if we should swap operand or force 32bit displacement in | |
f8a5c266 | 5201 | encoding. */ |
30a55f88 | 5202 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
64c49ab3 | 5203 | i.dir_encoding = dir_encoding_swap; |
8d63c93e | 5204 | else if (mnem_p - 3 == dot_p |
a501d77e L |
5205 | && dot_p[1] == 'd' |
5206 | && dot_p[2] == '8') | |
5207 | i.disp_encoding = disp_encoding_8bit; | |
8d63c93e | 5208 | else if (mnem_p - 4 == dot_p |
f8a5c266 L |
5209 | && dot_p[1] == 'd' |
5210 | && dot_p[2] == '3' | |
5211 | && dot_p[3] == '2') | |
a501d77e | 5212 | i.disp_encoding = disp_encoding_32bit; |
30a55f88 L |
5213 | else |
5214 | goto check_suffix; | |
5215 | mnem_p = dot_p; | |
5216 | *dot_p = '\0'; | |
d3ce72d0 | 5217 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
b6169b20 L |
5218 | } |
5219 | ||
29b0f896 AM |
5220 | if (!current_templates) |
5221 | { | |
dc1e8a47 | 5222 | check_suffix: |
1c529385 | 5223 | if (mnem_p > mnemonic) |
29b0f896 | 5224 | { |
1c529385 LH |
5225 | /* See if we can get a match by trimming off a suffix. */ |
5226 | switch (mnem_p[-1]) | |
29b0f896 | 5227 | { |
1c529385 LH |
5228 | case WORD_MNEM_SUFFIX: |
5229 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) | |
29b0f896 AM |
5230 | i.suffix = SHORT_MNEM_SUFFIX; |
5231 | else | |
1c529385 LH |
5232 | /* Fall through. */ |
5233 | case BYTE_MNEM_SUFFIX: | |
5234 | case QWORD_MNEM_SUFFIX: | |
5235 | i.suffix = mnem_p[-1]; | |
29b0f896 | 5236 | mnem_p[-1] = '\0'; |
d3ce72d0 | 5237 | current_templates = (const templates *) hash_find (op_hash, |
1c529385 LH |
5238 | mnemonic); |
5239 | break; | |
5240 | case SHORT_MNEM_SUFFIX: | |
5241 | case LONG_MNEM_SUFFIX: | |
5242 | if (!intel_syntax) | |
5243 | { | |
5244 | i.suffix = mnem_p[-1]; | |
5245 | mnem_p[-1] = '\0'; | |
5246 | current_templates = (const templates *) hash_find (op_hash, | |
5247 | mnemonic); | |
5248 | } | |
5249 | break; | |
5250 | ||
5251 | /* Intel Syntax. */ | |
5252 | case 'd': | |
5253 | if (intel_syntax) | |
5254 | { | |
5255 | if (intel_float_operand (mnemonic) == 1) | |
5256 | i.suffix = SHORT_MNEM_SUFFIX; | |
5257 | else | |
5258 | i.suffix = LONG_MNEM_SUFFIX; | |
5259 | mnem_p[-1] = '\0'; | |
5260 | current_templates = (const templates *) hash_find (op_hash, | |
5261 | mnemonic); | |
5262 | } | |
5263 | break; | |
29b0f896 | 5264 | } |
29b0f896 | 5265 | } |
1c529385 | 5266 | |
29b0f896 AM |
5267 | if (!current_templates) |
5268 | { | |
5269 | as_bad (_("no such instruction: `%s'"), token_start); | |
5270 | return NULL; | |
5271 | } | |
5272 | } | |
252b5132 | 5273 | |
0cfa3eb3 JB |
5274 | if (current_templates->start->opcode_modifier.jump == JUMP |
5275 | || current_templates->start->opcode_modifier.jump == JUMP_BYTE) | |
29b0f896 AM |
5276 | { |
5277 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
5278 | predict taken and predict not taken respectively. | |
5279 | I'm not sure that branch hints actually do anything on loop | |
5280 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
5281 | may work in the future and it doesn't hurt to accept them | |
5282 | now. */ | |
5283 | if (l[0] == ',' && l[1] == 'p') | |
5284 | { | |
5285 | if (l[2] == 't') | |
5286 | { | |
5287 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
5288 | return NULL; | |
5289 | l += 3; | |
5290 | } | |
5291 | else if (l[2] == 'n') | |
5292 | { | |
5293 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
5294 | return NULL; | |
5295 | l += 3; | |
5296 | } | |
5297 | } | |
5298 | } | |
5299 | /* Any other comma loses. */ | |
5300 | if (*l == ',') | |
5301 | { | |
5302 | as_bad (_("invalid character %s in mnemonic"), | |
5303 | output_invalid (*l)); | |
5304 | return NULL; | |
5305 | } | |
252b5132 | 5306 | |
29b0f896 | 5307 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
5308 | supported = 0; |
5309 | for (t = current_templates->start; t < current_templates->end; ++t) | |
5310 | { | |
c0f3af97 L |
5311 | supported |= cpu_flags_match (t); |
5312 | if (supported == CPU_FLAGS_PERFECT_MATCH) | |
548d0ee6 JB |
5313 | { |
5314 | if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT)) | |
5315 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
3629bb00 | 5316 | |
548d0ee6 JB |
5317 | return l; |
5318 | } | |
29b0f896 | 5319 | } |
3629bb00 | 5320 | |
548d0ee6 JB |
5321 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
5322 | as_bad (flag_code == CODE_64BIT | |
5323 | ? _("`%s' is not supported in 64-bit mode") | |
5324 | : _("`%s' is only supported in 64-bit mode"), | |
5325 | current_templates->start->name); | |
5326 | else | |
5327 | as_bad (_("`%s' is not supported on `%s%s'"), | |
5328 | current_templates->start->name, | |
5329 | cpu_arch_name ? cpu_arch_name : default_arch, | |
5330 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); | |
252b5132 | 5331 | |
548d0ee6 | 5332 | return NULL; |
29b0f896 | 5333 | } |
252b5132 | 5334 | |
29b0f896 | 5335 | static char * |
e3bb37b5 | 5336 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
5337 | { |
5338 | char *token_start; | |
3138f287 | 5339 | |
29b0f896 AM |
5340 | /* 1 if operand is pending after ','. */ |
5341 | unsigned int expecting_operand = 0; | |
252b5132 | 5342 | |
29b0f896 AM |
5343 | /* Non-zero if operand parens not balanced. */ |
5344 | unsigned int paren_not_balanced; | |
5345 | ||
5346 | while (*l != END_OF_INSN) | |
5347 | { | |
5348 | /* Skip optional white space before operand. */ | |
5349 | if (is_space_char (*l)) | |
5350 | ++l; | |
d02603dc | 5351 | if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') |
29b0f896 AM |
5352 | { |
5353 | as_bad (_("invalid character %s before operand %d"), | |
5354 | output_invalid (*l), | |
5355 | i.operands + 1); | |
5356 | return NULL; | |
5357 | } | |
d02603dc | 5358 | token_start = l; /* After white space. */ |
29b0f896 AM |
5359 | paren_not_balanced = 0; |
5360 | while (paren_not_balanced || *l != ',') | |
5361 | { | |
5362 | if (*l == END_OF_INSN) | |
5363 | { | |
5364 | if (paren_not_balanced) | |
5365 | { | |
5366 | if (!intel_syntax) | |
5367 | as_bad (_("unbalanced parenthesis in operand %d."), | |
5368 | i.operands + 1); | |
5369 | else | |
5370 | as_bad (_("unbalanced brackets in operand %d."), | |
5371 | i.operands + 1); | |
5372 | return NULL; | |
5373 | } | |
5374 | else | |
5375 | break; /* we are done */ | |
5376 | } | |
d02603dc | 5377 | else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"') |
29b0f896 AM |
5378 | { |
5379 | as_bad (_("invalid character %s in operand %d"), | |
5380 | output_invalid (*l), | |
5381 | i.operands + 1); | |
5382 | return NULL; | |
5383 | } | |
5384 | if (!intel_syntax) | |
5385 | { | |
5386 | if (*l == '(') | |
5387 | ++paren_not_balanced; | |
5388 | if (*l == ')') | |
5389 | --paren_not_balanced; | |
5390 | } | |
5391 | else | |
5392 | { | |
5393 | if (*l == '[') | |
5394 | ++paren_not_balanced; | |
5395 | if (*l == ']') | |
5396 | --paren_not_balanced; | |
5397 | } | |
5398 | l++; | |
5399 | } | |
5400 | if (l != token_start) | |
5401 | { /* Yes, we've read in another operand. */ | |
5402 | unsigned int operand_ok; | |
5403 | this_operand = i.operands++; | |
5404 | if (i.operands > MAX_OPERANDS) | |
5405 | { | |
5406 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
5407 | MAX_OPERANDS); | |
5408 | return NULL; | |
5409 | } | |
9d46ce34 | 5410 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
5411 | /* Now parse operand adding info to 'i' as we go along. */ |
5412 | END_STRING_AND_SAVE (l); | |
5413 | ||
1286ab78 L |
5414 | if (i.mem_operands > 1) |
5415 | { | |
5416 | as_bad (_("too many memory references for `%s'"), | |
5417 | mnemonic); | |
5418 | return 0; | |
5419 | } | |
5420 | ||
29b0f896 AM |
5421 | if (intel_syntax) |
5422 | operand_ok = | |
5423 | i386_intel_operand (token_start, | |
5424 | intel_float_operand (mnemonic)); | |
5425 | else | |
a7619375 | 5426 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
5427 | |
5428 | RESTORE_END_STRING (l); | |
5429 | if (!operand_ok) | |
5430 | return NULL; | |
5431 | } | |
5432 | else | |
5433 | { | |
5434 | if (expecting_operand) | |
5435 | { | |
5436 | expecting_operand_after_comma: | |
5437 | as_bad (_("expecting operand after ','; got nothing")); | |
5438 | return NULL; | |
5439 | } | |
5440 | if (*l == ',') | |
5441 | { | |
5442 | as_bad (_("expecting operand before ','; got nothing")); | |
5443 | return NULL; | |
5444 | } | |
5445 | } | |
7f3f1ea2 | 5446 | |
29b0f896 AM |
5447 | /* Now *l must be either ',' or END_OF_INSN. */ |
5448 | if (*l == ',') | |
5449 | { | |
5450 | if (*++l == END_OF_INSN) | |
5451 | { | |
5452 | /* Just skip it, if it's \n complain. */ | |
5453 | goto expecting_operand_after_comma; | |
5454 | } | |
5455 | expecting_operand = 1; | |
5456 | } | |
5457 | } | |
5458 | return l; | |
5459 | } | |
7f3f1ea2 | 5460 | |
050dfa73 | 5461 | static void |
4d456e3d | 5462 | swap_2_operands (int xchg1, int xchg2) |
050dfa73 MM |
5463 | { |
5464 | union i386_op temp_op; | |
40fb9820 | 5465 | i386_operand_type temp_type; |
c48dadc9 | 5466 | unsigned int temp_flags; |
050dfa73 | 5467 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 5468 | |
050dfa73 MM |
5469 | temp_type = i.types[xchg2]; |
5470 | i.types[xchg2] = i.types[xchg1]; | |
5471 | i.types[xchg1] = temp_type; | |
c48dadc9 JB |
5472 | |
5473 | temp_flags = i.flags[xchg2]; | |
5474 | i.flags[xchg2] = i.flags[xchg1]; | |
5475 | i.flags[xchg1] = temp_flags; | |
5476 | ||
050dfa73 MM |
5477 | temp_op = i.op[xchg2]; |
5478 | i.op[xchg2] = i.op[xchg1]; | |
5479 | i.op[xchg1] = temp_op; | |
c48dadc9 | 5480 | |
050dfa73 MM |
5481 | temp_reloc = i.reloc[xchg2]; |
5482 | i.reloc[xchg2] = i.reloc[xchg1]; | |
5483 | i.reloc[xchg1] = temp_reloc; | |
43234a1e L |
5484 | |
5485 | if (i.mask) | |
5486 | { | |
5487 | if (i.mask->operand == xchg1) | |
5488 | i.mask->operand = xchg2; | |
5489 | else if (i.mask->operand == xchg2) | |
5490 | i.mask->operand = xchg1; | |
5491 | } | |
5492 | if (i.broadcast) | |
5493 | { | |
5494 | if (i.broadcast->operand == xchg1) | |
5495 | i.broadcast->operand = xchg2; | |
5496 | else if (i.broadcast->operand == xchg2) | |
5497 | i.broadcast->operand = xchg1; | |
5498 | } | |
5499 | if (i.rounding) | |
5500 | { | |
5501 | if (i.rounding->operand == xchg1) | |
5502 | i.rounding->operand = xchg2; | |
5503 | else if (i.rounding->operand == xchg2) | |
5504 | i.rounding->operand = xchg1; | |
5505 | } | |
050dfa73 MM |
5506 | } |
5507 | ||
29b0f896 | 5508 | static void |
e3bb37b5 | 5509 | swap_operands (void) |
29b0f896 | 5510 | { |
b7c61d9a | 5511 | switch (i.operands) |
050dfa73 | 5512 | { |
c0f3af97 | 5513 | case 5: |
b7c61d9a | 5514 | case 4: |
4d456e3d | 5515 | swap_2_operands (1, i.operands - 2); |
1a0670f3 | 5516 | /* Fall through. */ |
b7c61d9a L |
5517 | case 3: |
5518 | case 2: | |
4d456e3d | 5519 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
5520 | break; |
5521 | default: | |
5522 | abort (); | |
29b0f896 | 5523 | } |
29b0f896 AM |
5524 | |
5525 | if (i.mem_operands == 2) | |
5526 | { | |
5527 | const seg_entry *temp_seg; | |
5528 | temp_seg = i.seg[0]; | |
5529 | i.seg[0] = i.seg[1]; | |
5530 | i.seg[1] = temp_seg; | |
5531 | } | |
5532 | } | |
252b5132 | 5533 | |
29b0f896 AM |
5534 | /* Try to ensure constant immediates are represented in the smallest |
5535 | opcode possible. */ | |
5536 | static void | |
e3bb37b5 | 5537 | optimize_imm (void) |
29b0f896 AM |
5538 | { |
5539 | char guess_suffix = 0; | |
5540 | int op; | |
252b5132 | 5541 | |
29b0f896 AM |
5542 | if (i.suffix) |
5543 | guess_suffix = i.suffix; | |
5544 | else if (i.reg_operands) | |
5545 | { | |
5546 | /* Figure out a suffix from the last register operand specified. | |
75e5731b JB |
5547 | We can't do this properly yet, i.e. excluding special register |
5548 | instances, but the following works for instructions with | |
5549 | immediates. In any case, we can't set i.suffix yet. */ | |
29b0f896 | 5550 | for (op = i.operands; --op >= 0;) |
bab6aec1 JB |
5551 | if (i.types[op].bitfield.class != Reg) |
5552 | continue; | |
5553 | else if (i.types[op].bitfield.byte) | |
7ab9ffdd | 5554 | { |
40fb9820 L |
5555 | guess_suffix = BYTE_MNEM_SUFFIX; |
5556 | break; | |
5557 | } | |
bab6aec1 | 5558 | else if (i.types[op].bitfield.word) |
252b5132 | 5559 | { |
40fb9820 L |
5560 | guess_suffix = WORD_MNEM_SUFFIX; |
5561 | break; | |
5562 | } | |
bab6aec1 | 5563 | else if (i.types[op].bitfield.dword) |
40fb9820 L |
5564 | { |
5565 | guess_suffix = LONG_MNEM_SUFFIX; | |
5566 | break; | |
5567 | } | |
bab6aec1 | 5568 | else if (i.types[op].bitfield.qword) |
40fb9820 L |
5569 | { |
5570 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 5571 | break; |
252b5132 | 5572 | } |
29b0f896 AM |
5573 | } |
5574 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
5575 | guess_suffix = WORD_MNEM_SUFFIX; | |
5576 | ||
5577 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 5578 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
5579 | { |
5580 | switch (i.op[op].imms->X_op) | |
252b5132 | 5581 | { |
29b0f896 AM |
5582 | case O_constant: |
5583 | /* If a suffix is given, this operand may be shortened. */ | |
5584 | switch (guess_suffix) | |
252b5132 | 5585 | { |
29b0f896 | 5586 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
5587 | i.types[op].bitfield.imm32 = 1; |
5588 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
5589 | break; |
5590 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
5591 | i.types[op].bitfield.imm16 = 1; |
5592 | i.types[op].bitfield.imm32 = 1; | |
5593 | i.types[op].bitfield.imm32s = 1; | |
5594 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
5595 | break; |
5596 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
5597 | i.types[op].bitfield.imm8 = 1; |
5598 | i.types[op].bitfield.imm8s = 1; | |
5599 | i.types[op].bitfield.imm16 = 1; | |
5600 | i.types[op].bitfield.imm32 = 1; | |
5601 | i.types[op].bitfield.imm32s = 1; | |
5602 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 5603 | break; |
252b5132 | 5604 | } |
252b5132 | 5605 | |
29b0f896 AM |
5606 | /* If this operand is at most 16 bits, convert it |
5607 | to a signed 16 bit number before trying to see | |
5608 | whether it will fit in an even smaller size. | |
5609 | This allows a 16-bit operand such as $0xffe0 to | |
5610 | be recognised as within Imm8S range. */ | |
40fb9820 | 5611 | if ((i.types[op].bitfield.imm16) |
29b0f896 | 5612 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
252b5132 | 5613 | { |
29b0f896 AM |
5614 | i.op[op].imms->X_add_number = |
5615 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
5616 | } | |
a28def75 L |
5617 | #ifdef BFD64 |
5618 | /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ | |
40fb9820 | 5619 | if ((i.types[op].bitfield.imm32) |
29b0f896 AM |
5620 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
5621 | == 0)) | |
5622 | { | |
5623 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
5624 | ^ ((offsetT) 1 << 31)) | |
5625 | - ((offsetT) 1 << 31)); | |
5626 | } | |
a28def75 | 5627 | #endif |
40fb9820 | 5628 | i.types[op] |
c6fb90c8 L |
5629 | = operand_type_or (i.types[op], |
5630 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 5631 | |
29b0f896 AM |
5632 | /* We must avoid matching of Imm32 templates when 64bit |
5633 | only immediate is available. */ | |
5634 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 5635 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 5636 | break; |
252b5132 | 5637 | |
29b0f896 AM |
5638 | case O_absent: |
5639 | case O_register: | |
5640 | abort (); | |
5641 | ||
5642 | /* Symbols and expressions. */ | |
5643 | default: | |
9cd96992 JB |
5644 | /* Convert symbolic operand to proper sizes for matching, but don't |
5645 | prevent matching a set of insns that only supports sizes other | |
5646 | than those matching the insn suffix. */ | |
5647 | { | |
40fb9820 | 5648 | i386_operand_type mask, allowed; |
d3ce72d0 | 5649 | const insn_template *t; |
9cd96992 | 5650 | |
0dfbf9d7 L |
5651 | operand_type_set (&mask, 0); |
5652 | operand_type_set (&allowed, 0); | |
40fb9820 | 5653 | |
4eed87de AM |
5654 | for (t = current_templates->start; |
5655 | t < current_templates->end; | |
5656 | ++t) | |
bab6aec1 JB |
5657 | { |
5658 | allowed = operand_type_or (allowed, t->operand_types[op]); | |
5659 | allowed = operand_type_and (allowed, anyimm); | |
5660 | } | |
9cd96992 JB |
5661 | switch (guess_suffix) |
5662 | { | |
5663 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
5664 | mask.bitfield.imm64 = 1; |
5665 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
5666 | break; |
5667 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 5668 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
5669 | break; |
5670 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 5671 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
5672 | break; |
5673 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 5674 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
5675 | break; |
5676 | default: | |
9cd96992 JB |
5677 | break; |
5678 | } | |
c6fb90c8 | 5679 | allowed = operand_type_and (mask, allowed); |
0dfbf9d7 | 5680 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 5681 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 5682 | } |
29b0f896 | 5683 | break; |
252b5132 | 5684 | } |
29b0f896 AM |
5685 | } |
5686 | } | |
47926f60 | 5687 | |
29b0f896 AM |
5688 | /* Try to use the smallest displacement type too. */ |
5689 | static void | |
e3bb37b5 | 5690 | optimize_disp (void) |
29b0f896 AM |
5691 | { |
5692 | int op; | |
3e73aa7c | 5693 | |
29b0f896 | 5694 | for (op = i.operands; --op >= 0;) |
40fb9820 | 5695 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 5696 | { |
b300c311 | 5697 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 5698 | { |
91d6fa6a | 5699 | offsetT op_disp = i.op[op].disps->X_add_number; |
29b0f896 | 5700 | |
40fb9820 | 5701 | if (i.types[op].bitfield.disp16 |
91d6fa6a | 5702 | && (op_disp & ~(offsetT) 0xffff) == 0) |
b300c311 L |
5703 | { |
5704 | /* If this operand is at most 16 bits, convert | |
5705 | to a signed 16 bit number and don't use 64bit | |
5706 | displacement. */ | |
91d6fa6a | 5707 | op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); |
40fb9820 | 5708 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 5709 | } |
a28def75 L |
5710 | #ifdef BFD64 |
5711 | /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ | |
40fb9820 | 5712 | if (i.types[op].bitfield.disp32 |
91d6fa6a | 5713 | && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
b300c311 L |
5714 | { |
5715 | /* If this operand is at most 32 bits, convert | |
5716 | to a signed 32 bit number and don't use 64bit | |
5717 | displacement. */ | |
91d6fa6a NC |
5718 | op_disp &= (((offsetT) 2 << 31) - 1); |
5719 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
40fb9820 | 5720 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 5721 | } |
a28def75 | 5722 | #endif |
91d6fa6a | 5723 | if (!op_disp && i.types[op].bitfield.baseindex) |
b300c311 | 5724 | { |
40fb9820 L |
5725 | i.types[op].bitfield.disp8 = 0; |
5726 | i.types[op].bitfield.disp16 = 0; | |
5727 | i.types[op].bitfield.disp32 = 0; | |
5728 | i.types[op].bitfield.disp32s = 0; | |
5729 | i.types[op].bitfield.disp64 = 0; | |
b300c311 L |
5730 | i.op[op].disps = 0; |
5731 | i.disp_operands--; | |
5732 | } | |
5733 | else if (flag_code == CODE_64BIT) | |
5734 | { | |
91d6fa6a | 5735 | if (fits_in_signed_long (op_disp)) |
28a9d8f5 | 5736 | { |
40fb9820 L |
5737 | i.types[op].bitfield.disp64 = 0; |
5738 | i.types[op].bitfield.disp32s = 1; | |
28a9d8f5 | 5739 | } |
0e1147d9 | 5740 | if (i.prefix[ADDR_PREFIX] |
91d6fa6a | 5741 | && fits_in_unsigned_long (op_disp)) |
40fb9820 | 5742 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 5743 | } |
40fb9820 L |
5744 | if ((i.types[op].bitfield.disp32 |
5745 | || i.types[op].bitfield.disp32s | |
5746 | || i.types[op].bitfield.disp16) | |
b5014f7a | 5747 | && fits_in_disp8 (op_disp)) |
40fb9820 | 5748 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 5749 | } |
67a4f2b7 AO |
5750 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
5751 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
5752 | { | |
5753 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
5754 | i.op[op].disps, 0, i.reloc[op]); | |
40fb9820 L |
5755 | i.types[op].bitfield.disp8 = 0; |
5756 | i.types[op].bitfield.disp16 = 0; | |
5757 | i.types[op].bitfield.disp32 = 0; | |
5758 | i.types[op].bitfield.disp32s = 0; | |
5759 | i.types[op].bitfield.disp64 = 0; | |
67a4f2b7 AO |
5760 | } |
5761 | else | |
b300c311 | 5762 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 5763 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 5764 | } |
29b0f896 AM |
5765 | } |
5766 | ||
4a1b91ea L |
5767 | /* Return 1 if there is a match in broadcast bytes between operand |
5768 | GIVEN and instruction template T. */ | |
5769 | ||
5770 | static INLINE int | |
5771 | match_broadcast_size (const insn_template *t, unsigned int given) | |
5772 | { | |
5773 | return ((t->opcode_modifier.broadcast == BYTE_BROADCAST | |
5774 | && i.types[given].bitfield.byte) | |
5775 | || (t->opcode_modifier.broadcast == WORD_BROADCAST | |
5776 | && i.types[given].bitfield.word) | |
5777 | || (t->opcode_modifier.broadcast == DWORD_BROADCAST | |
5778 | && i.types[given].bitfield.dword) | |
5779 | || (t->opcode_modifier.broadcast == QWORD_BROADCAST | |
5780 | && i.types[given].bitfield.qword)); | |
5781 | } | |
5782 | ||
6c30d220 L |
5783 | /* Check if operands are valid for the instruction. */ |
5784 | ||
5785 | static int | |
5786 | check_VecOperands (const insn_template *t) | |
5787 | { | |
43234a1e | 5788 | unsigned int op; |
e2195274 | 5789 | i386_cpu_flags cpu; |
e2195274 JB |
5790 | |
5791 | /* Templates allowing for ZMMword as well as YMMword and/or XMMword for | |
5792 | any one operand are implicity requiring AVX512VL support if the actual | |
5793 | operand size is YMMword or XMMword. Since this function runs after | |
5794 | template matching, there's no need to check for YMMword/XMMword in | |
5795 | the template. */ | |
5796 | cpu = cpu_flags_and (t->cpu_flags, avx512); | |
5797 | if (!cpu_flags_all_zero (&cpu) | |
5798 | && !t->cpu_flags.bitfield.cpuavx512vl | |
5799 | && !cpu_arch_flags.bitfield.cpuavx512vl) | |
5800 | { | |
5801 | for (op = 0; op < t->operands; ++op) | |
5802 | { | |
5803 | if (t->operand_types[op].bitfield.zmmword | |
5804 | && (i.types[op].bitfield.ymmword | |
5805 | || i.types[op].bitfield.xmmword)) | |
5806 | { | |
5807 | i.error = unsupported; | |
5808 | return 1; | |
5809 | } | |
5810 | } | |
5811 | } | |
43234a1e | 5812 | |
6c30d220 | 5813 | /* Without VSIB byte, we can't have a vector register for index. */ |
63112cd6 | 5814 | if (!t->opcode_modifier.sib |
6c30d220 | 5815 | && i.index_reg |
1b54b8d7 JB |
5816 | && (i.index_reg->reg_type.bitfield.xmmword |
5817 | || i.index_reg->reg_type.bitfield.ymmword | |
5818 | || i.index_reg->reg_type.bitfield.zmmword)) | |
6c30d220 L |
5819 | { |
5820 | i.error = unsupported_vector_index_register; | |
5821 | return 1; | |
5822 | } | |
5823 | ||
ad8ecc81 MZ |
5824 | /* Check if default mask is allowed. */ |
5825 | if (t->opcode_modifier.nodefmask | |
5826 | && (!i.mask || i.mask->mask->reg_num == 0)) | |
5827 | { | |
5828 | i.error = no_default_mask; | |
5829 | return 1; | |
5830 | } | |
5831 | ||
7bab8ab5 JB |
5832 | /* For VSIB byte, we need a vector register for index, and all vector |
5833 | registers must be distinct. */ | |
260cd341 | 5834 | if (t->opcode_modifier.sib && t->opcode_modifier.sib != SIBMEM) |
7bab8ab5 JB |
5835 | { |
5836 | if (!i.index_reg | |
63112cd6 | 5837 | || !((t->opcode_modifier.sib == VECSIB128 |
1b54b8d7 | 5838 | && i.index_reg->reg_type.bitfield.xmmword) |
63112cd6 | 5839 | || (t->opcode_modifier.sib == VECSIB256 |
1b54b8d7 | 5840 | && i.index_reg->reg_type.bitfield.ymmword) |
63112cd6 | 5841 | || (t->opcode_modifier.sib == VECSIB512 |
1b54b8d7 | 5842 | && i.index_reg->reg_type.bitfield.zmmword))) |
7bab8ab5 JB |
5843 | { |
5844 | i.error = invalid_vsib_address; | |
5845 | return 1; | |
5846 | } | |
5847 | ||
43234a1e L |
5848 | gas_assert (i.reg_operands == 2 || i.mask); |
5849 | if (i.reg_operands == 2 && !i.mask) | |
5850 | { | |
3528c362 | 5851 | gas_assert (i.types[0].bitfield.class == RegSIMD); |
1b54b8d7 JB |
5852 | gas_assert (i.types[0].bitfield.xmmword |
5853 | || i.types[0].bitfield.ymmword); | |
3528c362 | 5854 | gas_assert (i.types[2].bitfield.class == RegSIMD); |
1b54b8d7 JB |
5855 | gas_assert (i.types[2].bitfield.xmmword |
5856 | || i.types[2].bitfield.ymmword); | |
43234a1e L |
5857 | if (operand_check == check_none) |
5858 | return 0; | |
5859 | if (register_number (i.op[0].regs) | |
5860 | != register_number (i.index_reg) | |
5861 | && register_number (i.op[2].regs) | |
5862 | != register_number (i.index_reg) | |
5863 | && register_number (i.op[0].regs) | |
5864 | != register_number (i.op[2].regs)) | |
5865 | return 0; | |
5866 | if (operand_check == check_error) | |
5867 | { | |
5868 | i.error = invalid_vector_register_set; | |
5869 | return 1; | |
5870 | } | |
5871 | as_warn (_("mask, index, and destination registers should be distinct")); | |
5872 | } | |
8444f82a MZ |
5873 | else if (i.reg_operands == 1 && i.mask) |
5874 | { | |
3528c362 | 5875 | if (i.types[1].bitfield.class == RegSIMD |
1b54b8d7 JB |
5876 | && (i.types[1].bitfield.xmmword |
5877 | || i.types[1].bitfield.ymmword | |
5878 | || i.types[1].bitfield.zmmword) | |
8444f82a MZ |
5879 | && (register_number (i.op[1].regs) |
5880 | == register_number (i.index_reg))) | |
5881 | { | |
5882 | if (operand_check == check_error) | |
5883 | { | |
5884 | i.error = invalid_vector_register_set; | |
5885 | return 1; | |
5886 | } | |
5887 | if (operand_check != check_none) | |
5888 | as_warn (_("index and destination registers should be distinct")); | |
5889 | } | |
5890 | } | |
43234a1e | 5891 | } |
7bab8ab5 | 5892 | |
260cd341 LC |
5893 | /* For AMX instructions with three tmmword operands, all tmmword operand must be |
5894 | distinct */ | |
5895 | if (t->operand_types[0].bitfield.tmmword | |
5896 | && i.reg_operands == 3) | |
5897 | { | |
5898 | if (register_number (i.op[0].regs) | |
5899 | == register_number (i.op[1].regs) | |
5900 | || register_number (i.op[0].regs) | |
5901 | == register_number (i.op[2].regs) | |
5902 | || register_number (i.op[1].regs) | |
5903 | == register_number (i.op[2].regs)) | |
5904 | { | |
5905 | i.error = invalid_tmm_register_set; | |
5906 | return 1; | |
5907 | } | |
5908 | } | |
5909 | ||
43234a1e L |
5910 | /* Check if broadcast is supported by the instruction and is applied |
5911 | to the memory operand. */ | |
5912 | if (i.broadcast) | |
5913 | { | |
8e6e0792 | 5914 | i386_operand_type type, overlap; |
43234a1e L |
5915 | |
5916 | /* Check if specified broadcast is supported in this instruction, | |
4a1b91ea | 5917 | and its broadcast bytes match the memory operand. */ |
32546502 | 5918 | op = i.broadcast->operand; |
8e6e0792 | 5919 | if (!t->opcode_modifier.broadcast |
c48dadc9 | 5920 | || !(i.flags[op] & Operand_Mem) |
c39e5b26 | 5921 | || (!i.types[op].bitfield.unspecified |
4a1b91ea | 5922 | && !match_broadcast_size (t, op))) |
43234a1e L |
5923 | { |
5924 | bad_broadcast: | |
5925 | i.error = unsupported_broadcast; | |
5926 | return 1; | |
5927 | } | |
8e6e0792 | 5928 | |
4a1b91ea L |
5929 | i.broadcast->bytes = ((1 << (t->opcode_modifier.broadcast - 1)) |
5930 | * i.broadcast->type); | |
8e6e0792 | 5931 | operand_type_set (&type, 0); |
4a1b91ea | 5932 | switch (i.broadcast->bytes) |
8e6e0792 | 5933 | { |
4a1b91ea L |
5934 | case 2: |
5935 | type.bitfield.word = 1; | |
5936 | break; | |
5937 | case 4: | |
5938 | type.bitfield.dword = 1; | |
5939 | break; | |
8e6e0792 JB |
5940 | case 8: |
5941 | type.bitfield.qword = 1; | |
5942 | break; | |
5943 | case 16: | |
5944 | type.bitfield.xmmword = 1; | |
5945 | break; | |
5946 | case 32: | |
5947 | type.bitfield.ymmword = 1; | |
5948 | break; | |
5949 | case 64: | |
5950 | type.bitfield.zmmword = 1; | |
5951 | break; | |
5952 | default: | |
5953 | goto bad_broadcast; | |
5954 | } | |
5955 | ||
5956 | overlap = operand_type_and (type, t->operand_types[op]); | |
bc49bfd8 JB |
5957 | if (t->operand_types[op].bitfield.class == RegSIMD |
5958 | && t->operand_types[op].bitfield.byte | |
5959 | + t->operand_types[op].bitfield.word | |
5960 | + t->operand_types[op].bitfield.dword | |
5961 | + t->operand_types[op].bitfield.qword > 1) | |
5962 | { | |
5963 | overlap.bitfield.xmmword = 0; | |
5964 | overlap.bitfield.ymmword = 0; | |
5965 | overlap.bitfield.zmmword = 0; | |
5966 | } | |
8e6e0792 JB |
5967 | if (operand_type_all_zero (&overlap)) |
5968 | goto bad_broadcast; | |
5969 | ||
5970 | if (t->opcode_modifier.checkregsize) | |
5971 | { | |
5972 | unsigned int j; | |
5973 | ||
e2195274 | 5974 | type.bitfield.baseindex = 1; |
8e6e0792 JB |
5975 | for (j = 0; j < i.operands; ++j) |
5976 | { | |
5977 | if (j != op | |
5978 | && !operand_type_register_match(i.types[j], | |
5979 | t->operand_types[j], | |
5980 | type, | |
5981 | t->operand_types[op])) | |
5982 | goto bad_broadcast; | |
5983 | } | |
5984 | } | |
43234a1e L |
5985 | } |
5986 | /* If broadcast is supported in this instruction, we need to check if | |
5987 | operand of one-element size isn't specified without broadcast. */ | |
5988 | else if (t->opcode_modifier.broadcast && i.mem_operands) | |
5989 | { | |
5990 | /* Find memory operand. */ | |
5991 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 5992 | if (i.flags[op] & Operand_Mem) |
43234a1e L |
5993 | break; |
5994 | gas_assert (op < i.operands); | |
5995 | /* Check size of the memory operand. */ | |
4a1b91ea | 5996 | if (match_broadcast_size (t, op)) |
43234a1e L |
5997 | { |
5998 | i.error = broadcast_needed; | |
5999 | return 1; | |
6000 | } | |
6001 | } | |
c39e5b26 JB |
6002 | else |
6003 | op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */ | |
43234a1e L |
6004 | |
6005 | /* Check if requested masking is supported. */ | |
ae2387fe | 6006 | if (i.mask) |
43234a1e | 6007 | { |
ae2387fe JB |
6008 | switch (t->opcode_modifier.masking) |
6009 | { | |
6010 | case BOTH_MASKING: | |
6011 | break; | |
6012 | case MERGING_MASKING: | |
6013 | if (i.mask->zeroing) | |
6014 | { | |
6015 | case 0: | |
6016 | i.error = unsupported_masking; | |
6017 | return 1; | |
6018 | } | |
6019 | break; | |
6020 | case DYNAMIC_MASKING: | |
6021 | /* Memory destinations allow only merging masking. */ | |
6022 | if (i.mask->zeroing && i.mem_operands) | |
6023 | { | |
6024 | /* Find memory operand. */ | |
6025 | for (op = 0; op < i.operands; op++) | |
c48dadc9 | 6026 | if (i.flags[op] & Operand_Mem) |
ae2387fe JB |
6027 | break; |
6028 | gas_assert (op < i.operands); | |
6029 | if (op == i.operands - 1) | |
6030 | { | |
6031 | i.error = unsupported_masking; | |
6032 | return 1; | |
6033 | } | |
6034 | } | |
6035 | break; | |
6036 | default: | |
6037 | abort (); | |
6038 | } | |
43234a1e L |
6039 | } |
6040 | ||
6041 | /* Check if masking is applied to dest operand. */ | |
6042 | if (i.mask && (i.mask->operand != (int) (i.operands - 1))) | |
6043 | { | |
6044 | i.error = mask_not_on_destination; | |
6045 | return 1; | |
6046 | } | |
6047 | ||
43234a1e L |
6048 | /* Check RC/SAE. */ |
6049 | if (i.rounding) | |
6050 | { | |
a80195f1 JB |
6051 | if (!t->opcode_modifier.sae |
6052 | || (i.rounding->type != saeonly && !t->opcode_modifier.staticrounding)) | |
43234a1e L |
6053 | { |
6054 | i.error = unsupported_rc_sae; | |
6055 | return 1; | |
6056 | } | |
6057 | /* If the instruction has several immediate operands and one of | |
6058 | them is rounding, the rounding operand should be the last | |
6059 | immediate operand. */ | |
6060 | if (i.imm_operands > 1 | |
6061 | && i.rounding->operand != (int) (i.imm_operands - 1)) | |
7bab8ab5 | 6062 | { |
43234a1e | 6063 | i.error = rc_sae_operand_not_last_imm; |
7bab8ab5 JB |
6064 | return 1; |
6065 | } | |
6c30d220 L |
6066 | } |
6067 | ||
da4977e0 JB |
6068 | /* Check the special Imm4 cases; must be the first operand. */ |
6069 | if (t->cpu_flags.bitfield.cpuxop && t->operands == 5) | |
6070 | { | |
6071 | if (i.op[0].imms->X_op != O_constant | |
6072 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
6073 | { | |
6074 | i.error = bad_imm4; | |
6075 | return 1; | |
6076 | } | |
6077 | ||
6078 | /* Turn off Imm<N> so that update_imm won't complain. */ | |
6079 | operand_type_set (&i.types[0], 0); | |
6080 | } | |
6081 | ||
43234a1e | 6082 | /* Check vector Disp8 operand. */ |
b5014f7a JB |
6083 | if (t->opcode_modifier.disp8memshift |
6084 | && i.disp_encoding != disp_encoding_32bit) | |
43234a1e L |
6085 | { |
6086 | if (i.broadcast) | |
4a1b91ea | 6087 | i.memshift = t->opcode_modifier.broadcast - 1; |
7091c612 | 6088 | else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL) |
43234a1e | 6089 | i.memshift = t->opcode_modifier.disp8memshift; |
7091c612 JB |
6090 | else |
6091 | { | |
6092 | const i386_operand_type *type = NULL; | |
6093 | ||
6094 | i.memshift = 0; | |
6095 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 6096 | if (i.flags[op] & Operand_Mem) |
7091c612 | 6097 | { |
4174bfff JB |
6098 | if (t->opcode_modifier.evex == EVEXLIG) |
6099 | i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX); | |
6100 | else if (t->operand_types[op].bitfield.xmmword | |
6101 | + t->operand_types[op].bitfield.ymmword | |
6102 | + t->operand_types[op].bitfield.zmmword <= 1) | |
7091c612 JB |
6103 | type = &t->operand_types[op]; |
6104 | else if (!i.types[op].bitfield.unspecified) | |
6105 | type = &i.types[op]; | |
6106 | } | |
3528c362 | 6107 | else if (i.types[op].bitfield.class == RegSIMD |
4174bfff | 6108 | && t->opcode_modifier.evex != EVEXLIG) |
7091c612 JB |
6109 | { |
6110 | if (i.types[op].bitfield.zmmword) | |
6111 | i.memshift = 6; | |
6112 | else if (i.types[op].bitfield.ymmword && i.memshift < 5) | |
6113 | i.memshift = 5; | |
6114 | else if (i.types[op].bitfield.xmmword && i.memshift < 4) | |
6115 | i.memshift = 4; | |
6116 | } | |
6117 | ||
6118 | if (type) | |
6119 | { | |
6120 | if (type->bitfield.zmmword) | |
6121 | i.memshift = 6; | |
6122 | else if (type->bitfield.ymmword) | |
6123 | i.memshift = 5; | |
6124 | else if (type->bitfield.xmmword) | |
6125 | i.memshift = 4; | |
6126 | } | |
6127 | ||
6128 | /* For the check in fits_in_disp8(). */ | |
6129 | if (i.memshift == 0) | |
6130 | i.memshift = -1; | |
6131 | } | |
43234a1e L |
6132 | |
6133 | for (op = 0; op < i.operands; op++) | |
6134 | if (operand_type_check (i.types[op], disp) | |
6135 | && i.op[op].disps->X_op == O_constant) | |
6136 | { | |
b5014f7a | 6137 | if (fits_in_disp8 (i.op[op].disps->X_add_number)) |
43234a1e | 6138 | { |
b5014f7a JB |
6139 | i.types[op].bitfield.disp8 = 1; |
6140 | return 0; | |
43234a1e | 6141 | } |
b5014f7a | 6142 | i.types[op].bitfield.disp8 = 0; |
43234a1e L |
6143 | } |
6144 | } | |
b5014f7a JB |
6145 | |
6146 | i.memshift = 0; | |
43234a1e | 6147 | |
6c30d220 L |
6148 | return 0; |
6149 | } | |
6150 | ||
da4977e0 | 6151 | /* Check if encoding requirements are met by the instruction. */ |
a683cc34 SP |
6152 | |
6153 | static int | |
da4977e0 | 6154 | VEX_check_encoding (const insn_template *t) |
a683cc34 | 6155 | { |
da4977e0 JB |
6156 | if (i.vec_encoding == vex_encoding_error) |
6157 | { | |
6158 | i.error = unsupported; | |
6159 | return 1; | |
6160 | } | |
6161 | ||
86fa6981 | 6162 | if (i.vec_encoding == vex_encoding_evex) |
43234a1e | 6163 | { |
86fa6981 | 6164 | /* This instruction must be encoded with EVEX prefix. */ |
e771e7c9 | 6165 | if (!is_evex_encoding (t)) |
86fa6981 L |
6166 | { |
6167 | i.error = unsupported; | |
6168 | return 1; | |
6169 | } | |
6170 | return 0; | |
43234a1e L |
6171 | } |
6172 | ||
a683cc34 | 6173 | if (!t->opcode_modifier.vex) |
86fa6981 L |
6174 | { |
6175 | /* This instruction template doesn't have VEX prefix. */ | |
6176 | if (i.vec_encoding != vex_encoding_default) | |
6177 | { | |
6178 | i.error = unsupported; | |
6179 | return 1; | |
6180 | } | |
6181 | return 0; | |
6182 | } | |
a683cc34 | 6183 | |
a683cc34 SP |
6184 | return 0; |
6185 | } | |
6186 | ||
d3ce72d0 | 6187 | static const insn_template * |
83b16ac6 | 6188 | match_template (char mnem_suffix) |
29b0f896 AM |
6189 | { |
6190 | /* Points to template once we've found it. */ | |
d3ce72d0 | 6191 | const insn_template *t; |
40fb9820 | 6192 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 6193 | i386_operand_type overlap4; |
29b0f896 | 6194 | unsigned int found_reverse_match; |
dc2be329 | 6195 | i386_opcode_modifier suffix_check; |
40fb9820 | 6196 | i386_operand_type operand_types [MAX_OPERANDS]; |
539e75ad | 6197 | int addr_prefix_disp; |
45a4bb20 | 6198 | unsigned int j, size_match, check_register; |
5614d22c | 6199 | enum i386_error specific_error = 0; |
29b0f896 | 6200 | |
c0f3af97 L |
6201 | #if MAX_OPERANDS != 5 |
6202 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
6203 | #endif |
6204 | ||
29b0f896 | 6205 | found_reverse_match = 0; |
539e75ad | 6206 | addr_prefix_disp = -1; |
40fb9820 | 6207 | |
dc2be329 | 6208 | /* Prepare for mnemonic suffix check. */ |
40fb9820 | 6209 | memset (&suffix_check, 0, sizeof (suffix_check)); |
dc2be329 L |
6210 | switch (mnem_suffix) |
6211 | { | |
6212 | case BYTE_MNEM_SUFFIX: | |
6213 | suffix_check.no_bsuf = 1; | |
6214 | break; | |
6215 | case WORD_MNEM_SUFFIX: | |
6216 | suffix_check.no_wsuf = 1; | |
6217 | break; | |
6218 | case SHORT_MNEM_SUFFIX: | |
6219 | suffix_check.no_ssuf = 1; | |
6220 | break; | |
6221 | case LONG_MNEM_SUFFIX: | |
6222 | suffix_check.no_lsuf = 1; | |
6223 | break; | |
6224 | case QWORD_MNEM_SUFFIX: | |
6225 | suffix_check.no_qsuf = 1; | |
6226 | break; | |
6227 | default: | |
6228 | /* NB: In Intel syntax, normally we can check for memory operand | |
6229 | size when there is no mnemonic suffix. But jmp and call have | |
6230 | 2 different encodings with Dword memory operand size, one with | |
6231 | No_ldSuf and the other without. i.suffix is set to | |
6232 | LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */ | |
6233 | if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
6234 | suffix_check.no_ldsuf = 1; | |
83b16ac6 JB |
6235 | } |
6236 | ||
01559ecc L |
6237 | /* Must have right number of operands. */ |
6238 | i.error = number_of_operands_mismatch; | |
6239 | ||
45aa61fe | 6240 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 6241 | { |
539e75ad | 6242 | addr_prefix_disp = -1; |
dbbc8b7e | 6243 | found_reverse_match = 0; |
539e75ad | 6244 | |
29b0f896 AM |
6245 | if (i.operands != t->operands) |
6246 | continue; | |
6247 | ||
50aecf8c | 6248 | /* Check processor support. */ |
a65babc9 | 6249 | i.error = unsupported; |
45a4bb20 | 6250 | if (cpu_flags_match (t) != CPU_FLAGS_PERFECT_MATCH) |
50aecf8c L |
6251 | continue; |
6252 | ||
e1d4d893 | 6253 | /* Check AT&T mnemonic. */ |
a65babc9 | 6254 | i.error = unsupported_with_intel_mnemonic; |
e1d4d893 | 6255 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) |
1efbbeb4 L |
6256 | continue; |
6257 | ||
4b5aaf5f | 6258 | /* Check AT&T/Intel syntax. */ |
a65babc9 | 6259 | i.error = unsupported_syntax; |
5c07affc | 6260 | if ((intel_syntax && t->opcode_modifier.attsyntax) |
4b5aaf5f | 6261 | || (!intel_syntax && t->opcode_modifier.intelsyntax)) |
1efbbeb4 L |
6262 | continue; |
6263 | ||
4b5aaf5f L |
6264 | /* Check Intel64/AMD64 ISA. */ |
6265 | switch (isa64) | |
6266 | { | |
6267 | default: | |
6268 | /* Default: Don't accept Intel64. */ | |
6269 | if (t->opcode_modifier.isa64 == INTEL64) | |
6270 | continue; | |
6271 | break; | |
6272 | case amd64: | |
6273 | /* -mamd64: Don't accept Intel64 and Intel64 only. */ | |
6274 | if (t->opcode_modifier.isa64 >= INTEL64) | |
6275 | continue; | |
6276 | break; | |
6277 | case intel64: | |
6278 | /* -mintel64: Don't accept AMD64. */ | |
5990e377 | 6279 | if (t->opcode_modifier.isa64 == AMD64 && flag_code == CODE_64BIT) |
4b5aaf5f L |
6280 | continue; |
6281 | break; | |
6282 | } | |
6283 | ||
dc2be329 | 6284 | /* Check the suffix. */ |
a65babc9 | 6285 | i.error = invalid_instruction_suffix; |
dc2be329 L |
6286 | if ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) |
6287 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
6288 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
6289 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
6290 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
6291 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)) | |
83b16ac6 | 6292 | continue; |
29b0f896 | 6293 | |
3ac21baa JB |
6294 | size_match = operand_size_match (t); |
6295 | if (!size_match) | |
7d5e4556 | 6296 | continue; |
539e75ad | 6297 | |
6f2f06be JB |
6298 | /* This is intentionally not |
6299 | ||
0cfa3eb3 | 6300 | if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE)) |
6f2f06be JB |
6301 | |
6302 | as the case of a missing * on the operand is accepted (perhaps with | |
6303 | a warning, issued further down). */ | |
0cfa3eb3 | 6304 | if (i.jumpabsolute && t->opcode_modifier.jump != JUMP_ABSOLUTE) |
6f2f06be JB |
6305 | { |
6306 | i.error = operand_type_mismatch; | |
6307 | continue; | |
6308 | } | |
6309 | ||
5c07affc L |
6310 | for (j = 0; j < MAX_OPERANDS; j++) |
6311 | operand_types[j] = t->operand_types[j]; | |
6312 | ||
e365e234 JB |
6313 | /* In general, don't allow |
6314 | - 64-bit operands outside of 64-bit mode, | |
6315 | - 32-bit operands on pre-386. */ | |
4873e243 | 6316 | j = i.imm_operands + (t->operands > i.imm_operands + 1); |
e365e234 JB |
6317 | if (((i.suffix == QWORD_MNEM_SUFFIX |
6318 | && flag_code != CODE_64BIT | |
6319 | && (t->base_opcode != 0x0fc7 | |
6320 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
6321 | || (i.suffix == LONG_MNEM_SUFFIX | |
6322 | && !cpu_arch_flags.bitfield.cpui386)) | |
45aa61fe | 6323 | && (intel_syntax |
3cd7f3e3 | 6324 | ? (t->opcode_modifier.mnemonicsize != IGNORESIZE |
45aa61fe AM |
6325 | && !intel_float_operand (t->name)) |
6326 | : intel_float_operand (t->name) != 2) | |
4873e243 JB |
6327 | && (t->operands == i.imm_operands |
6328 | || (operand_types[i.imm_operands].bitfield.class != RegMMX | |
6329 | && operand_types[i.imm_operands].bitfield.class != RegSIMD | |
6330 | && operand_types[i.imm_operands].bitfield.class != RegMask) | |
6331 | || (operand_types[j].bitfield.class != RegMMX | |
6332 | && operand_types[j].bitfield.class != RegSIMD | |
6333 | && operand_types[j].bitfield.class != RegMask)) | |
63112cd6 | 6334 | && !t->opcode_modifier.sib) |
192dc9c6 JB |
6335 | continue; |
6336 | ||
29b0f896 | 6337 | /* Do not verify operands when there are none. */ |
e365e234 | 6338 | if (!t->operands) |
da4977e0 JB |
6339 | { |
6340 | if (VEX_check_encoding (t)) | |
6341 | { | |
6342 | specific_error = i.error; | |
6343 | continue; | |
6344 | } | |
6345 | ||
6346 | /* We've found a match; break out of loop. */ | |
6347 | break; | |
6348 | } | |
252b5132 | 6349 | |
48bcea9f JB |
6350 | if (!t->opcode_modifier.jump |
6351 | || t->opcode_modifier.jump == JUMP_ABSOLUTE) | |
6352 | { | |
6353 | /* There should be only one Disp operand. */ | |
6354 | for (j = 0; j < MAX_OPERANDS; j++) | |
6355 | if (operand_type_check (operand_types[j], disp)) | |
539e75ad | 6356 | break; |
48bcea9f JB |
6357 | if (j < MAX_OPERANDS) |
6358 | { | |
6359 | bfd_boolean override = (i.prefix[ADDR_PREFIX] != 0); | |
6360 | ||
6361 | addr_prefix_disp = j; | |
6362 | ||
6363 | /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16 | |
6364 | operand into Disp32/Disp32/Disp16/Disp32 operand. */ | |
6365 | switch (flag_code) | |
40fb9820 | 6366 | { |
48bcea9f JB |
6367 | case CODE_16BIT: |
6368 | override = !override; | |
6369 | /* Fall through. */ | |
6370 | case CODE_32BIT: | |
6371 | if (operand_types[j].bitfield.disp32 | |
6372 | && operand_types[j].bitfield.disp16) | |
40fb9820 | 6373 | { |
48bcea9f JB |
6374 | operand_types[j].bitfield.disp16 = override; |
6375 | operand_types[j].bitfield.disp32 = !override; | |
40fb9820 | 6376 | } |
48bcea9f JB |
6377 | operand_types[j].bitfield.disp32s = 0; |
6378 | operand_types[j].bitfield.disp64 = 0; | |
6379 | break; | |
6380 | ||
6381 | case CODE_64BIT: | |
6382 | if (operand_types[j].bitfield.disp32s | |
6383 | || operand_types[j].bitfield.disp64) | |
40fb9820 | 6384 | { |
48bcea9f JB |
6385 | operand_types[j].bitfield.disp64 &= !override; |
6386 | operand_types[j].bitfield.disp32s &= !override; | |
6387 | operand_types[j].bitfield.disp32 = override; | |
40fb9820 | 6388 | } |
48bcea9f JB |
6389 | operand_types[j].bitfield.disp16 = 0; |
6390 | break; | |
40fb9820 | 6391 | } |
539e75ad | 6392 | } |
48bcea9f | 6393 | } |
539e75ad | 6394 | |
02a86693 L |
6395 | /* Force 0x8b encoding for "mov foo@GOT, %eax". */ |
6396 | if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0) | |
6397 | continue; | |
6398 | ||
56ffb741 | 6399 | /* We check register size if needed. */ |
e2195274 JB |
6400 | if (t->opcode_modifier.checkregsize) |
6401 | { | |
6402 | check_register = (1 << t->operands) - 1; | |
6403 | if (i.broadcast) | |
6404 | check_register &= ~(1 << i.broadcast->operand); | |
6405 | } | |
6406 | else | |
6407 | check_register = 0; | |
6408 | ||
c6fb90c8 | 6409 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
6410 | switch (t->operands) |
6411 | { | |
6412 | case 1: | |
40fb9820 | 6413 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
6414 | continue; |
6415 | break; | |
6416 | case 2: | |
33eaf5de | 6417 | /* xchg %eax, %eax is a special case. It is an alias for nop |
8b38ad71 L |
6418 | only in 32bit mode and we can use opcode 0x90. In 64bit |
6419 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
6420 | zero-extend %eax to %rax. */ | |
6421 | if (flag_code == CODE_64BIT | |
6422 | && t->base_opcode == 0x90 | |
75e5731b JB |
6423 | && i.types[0].bitfield.instance == Accum |
6424 | && i.types[0].bitfield.dword | |
6425 | && i.types[1].bitfield.instance == Accum | |
6426 | && i.types[1].bitfield.dword) | |
8b38ad71 | 6427 | continue; |
1212781b JB |
6428 | /* xrelease mov %eax, <disp> is another special case. It must not |
6429 | match the accumulator-only encoding of mov. */ | |
6430 | if (flag_code != CODE_64BIT | |
6431 | && i.hle_prefix | |
6432 | && t->base_opcode == 0xa0 | |
75e5731b | 6433 | && i.types[0].bitfield.instance == Accum |
8dc0818e | 6434 | && (i.flags[1] & Operand_Mem)) |
1212781b | 6435 | continue; |
f5eb1d70 JB |
6436 | /* Fall through. */ |
6437 | ||
6438 | case 3: | |
3ac21baa JB |
6439 | if (!(size_match & MATCH_STRAIGHT)) |
6440 | goto check_reverse; | |
64c49ab3 JB |
6441 | /* Reverse direction of operands if swapping is possible in the first |
6442 | place (operands need to be symmetric) and | |
6443 | - the load form is requested, and the template is a store form, | |
6444 | - the store form is requested, and the template is a load form, | |
6445 | - the non-default (swapped) form is requested. */ | |
6446 | overlap1 = operand_type_and (operand_types[0], operand_types[1]); | |
f5eb1d70 | 6447 | if (t->opcode_modifier.d && i.reg_operands == i.operands |
64c49ab3 JB |
6448 | && !operand_type_all_zero (&overlap1)) |
6449 | switch (i.dir_encoding) | |
6450 | { | |
6451 | case dir_encoding_load: | |
6452 | if (operand_type_check (operand_types[i.operands - 1], anymem) | |
dfd69174 | 6453 | || t->opcode_modifier.regmem) |
64c49ab3 JB |
6454 | goto check_reverse; |
6455 | break; | |
6456 | ||
6457 | case dir_encoding_store: | |
6458 | if (!operand_type_check (operand_types[i.operands - 1], anymem) | |
dfd69174 | 6459 | && !t->opcode_modifier.regmem) |
64c49ab3 JB |
6460 | goto check_reverse; |
6461 | break; | |
6462 | ||
6463 | case dir_encoding_swap: | |
6464 | goto check_reverse; | |
6465 | ||
6466 | case dir_encoding_default: | |
6467 | break; | |
6468 | } | |
86fa6981 | 6469 | /* If we want store form, we skip the current load. */ |
64c49ab3 JB |
6470 | if ((i.dir_encoding == dir_encoding_store |
6471 | || i.dir_encoding == dir_encoding_swap) | |
86fa6981 L |
6472 | && i.mem_operands == 0 |
6473 | && t->opcode_modifier.load) | |
fa99fab2 | 6474 | continue; |
1a0670f3 | 6475 | /* Fall through. */ |
f48ff2ae | 6476 | case 4: |
c0f3af97 | 6477 | case 5: |
c6fb90c8 | 6478 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
6479 | if (!operand_type_match (overlap0, i.types[0]) |
6480 | || !operand_type_match (overlap1, i.types[1]) | |
e2195274 | 6481 | || ((check_register & 3) == 3 |
dc821c5f | 6482 | && !operand_type_register_match (i.types[0], |
40fb9820 | 6483 | operand_types[0], |
dc821c5f | 6484 | i.types[1], |
40fb9820 | 6485 | operand_types[1]))) |
29b0f896 AM |
6486 | { |
6487 | /* Check if other direction is valid ... */ | |
38e314eb | 6488 | if (!t->opcode_modifier.d) |
29b0f896 AM |
6489 | continue; |
6490 | ||
dc1e8a47 | 6491 | check_reverse: |
3ac21baa JB |
6492 | if (!(size_match & MATCH_REVERSE)) |
6493 | continue; | |
29b0f896 | 6494 | /* Try reversing direction of operands. */ |
f5eb1d70 JB |
6495 | overlap0 = operand_type_and (i.types[0], operand_types[i.operands - 1]); |
6496 | overlap1 = operand_type_and (i.types[i.operands - 1], operand_types[0]); | |
40fb9820 | 6497 | if (!operand_type_match (overlap0, i.types[0]) |
f5eb1d70 | 6498 | || !operand_type_match (overlap1, i.types[i.operands - 1]) |
45664ddb | 6499 | || (check_register |
dc821c5f | 6500 | && !operand_type_register_match (i.types[0], |
f5eb1d70 JB |
6501 | operand_types[i.operands - 1], |
6502 | i.types[i.operands - 1], | |
45664ddb | 6503 | operand_types[0]))) |
29b0f896 AM |
6504 | { |
6505 | /* Does not match either direction. */ | |
6506 | continue; | |
6507 | } | |
38e314eb | 6508 | /* found_reverse_match holds which of D or FloatR |
29b0f896 | 6509 | we've found. */ |
38e314eb JB |
6510 | if (!t->opcode_modifier.d) |
6511 | found_reverse_match = 0; | |
6512 | else if (operand_types[0].bitfield.tbyte) | |
8a2ed489 | 6513 | found_reverse_match = Opcode_FloatD; |
dbbc8b7e | 6514 | else if (operand_types[0].bitfield.xmmword |
f5eb1d70 | 6515 | || operand_types[i.operands - 1].bitfield.xmmword |
3528c362 JB |
6516 | || operand_types[0].bitfield.class == RegMMX |
6517 | || operand_types[i.operands - 1].bitfield.class == RegMMX | |
dbbc8b7e JB |
6518 | || is_any_vex_encoding(t)) |
6519 | found_reverse_match = (t->base_opcode & 0xee) != 0x6e | |
6520 | ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; | |
8a2ed489 | 6521 | else |
38e314eb | 6522 | found_reverse_match = Opcode_D; |
40fb9820 | 6523 | if (t->opcode_modifier.floatr) |
8a2ed489 | 6524 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 6525 | } |
f48ff2ae | 6526 | else |
29b0f896 | 6527 | { |
f48ff2ae | 6528 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
6529 | switch (t->operands) |
6530 | { | |
c0f3af97 L |
6531 | case 5: |
6532 | overlap4 = operand_type_and (i.types[4], | |
6533 | operand_types[4]); | |
1a0670f3 | 6534 | /* Fall through. */ |
d1cbb4db | 6535 | case 4: |
c6fb90c8 L |
6536 | overlap3 = operand_type_and (i.types[3], |
6537 | operand_types[3]); | |
1a0670f3 | 6538 | /* Fall through. */ |
d1cbb4db | 6539 | case 3: |
c6fb90c8 L |
6540 | overlap2 = operand_type_and (i.types[2], |
6541 | operand_types[2]); | |
d1cbb4db L |
6542 | break; |
6543 | } | |
29b0f896 | 6544 | |
f48ff2ae L |
6545 | switch (t->operands) |
6546 | { | |
c0f3af97 L |
6547 | case 5: |
6548 | if (!operand_type_match (overlap4, i.types[4]) | |
dc821c5f | 6549 | || !operand_type_register_match (i.types[3], |
c0f3af97 | 6550 | operand_types[3], |
c0f3af97 L |
6551 | i.types[4], |
6552 | operand_types[4])) | |
6553 | continue; | |
1a0670f3 | 6554 | /* Fall through. */ |
f48ff2ae | 6555 | case 4: |
40fb9820 | 6556 | if (!operand_type_match (overlap3, i.types[3]) |
e2195274 JB |
6557 | || ((check_register & 0xa) == 0xa |
6558 | && !operand_type_register_match (i.types[1], | |
f7768225 JB |
6559 | operand_types[1], |
6560 | i.types[3], | |
e2195274 JB |
6561 | operand_types[3])) |
6562 | || ((check_register & 0xc) == 0xc | |
6563 | && !operand_type_register_match (i.types[2], | |
6564 | operand_types[2], | |
6565 | i.types[3], | |
6566 | operand_types[3]))) | |
f48ff2ae | 6567 | continue; |
1a0670f3 | 6568 | /* Fall through. */ |
f48ff2ae L |
6569 | case 3: |
6570 | /* Here we make use of the fact that there are no | |
23e42951 | 6571 | reverse match 3 operand instructions. */ |
40fb9820 | 6572 | if (!operand_type_match (overlap2, i.types[2]) |
e2195274 JB |
6573 | || ((check_register & 5) == 5 |
6574 | && !operand_type_register_match (i.types[0], | |
23e42951 JB |
6575 | operand_types[0], |
6576 | i.types[2], | |
e2195274 JB |
6577 | operand_types[2])) |
6578 | || ((check_register & 6) == 6 | |
6579 | && !operand_type_register_match (i.types[1], | |
6580 | operand_types[1], | |
6581 | i.types[2], | |
6582 | operand_types[2]))) | |
f48ff2ae L |
6583 | continue; |
6584 | break; | |
6585 | } | |
29b0f896 | 6586 | } |
f48ff2ae | 6587 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
6588 | slip through to break. */ |
6589 | } | |
c0f3af97 | 6590 | |
da4977e0 JB |
6591 | /* Check if vector operands are valid. */ |
6592 | if (check_VecOperands (t)) | |
6593 | { | |
6594 | specific_error = i.error; | |
6595 | continue; | |
6596 | } | |
6597 | ||
6598 | /* Check if VEX/EVEX encoding requirements can be satisfied. */ | |
6599 | if (VEX_check_encoding (t)) | |
5614d22c JB |
6600 | { |
6601 | specific_error = i.error; | |
6602 | continue; | |
6603 | } | |
a683cc34 | 6604 | |
29b0f896 AM |
6605 | /* We've found a match; break out of loop. */ |
6606 | break; | |
6607 | } | |
6608 | ||
6609 | if (t == current_templates->end) | |
6610 | { | |
6611 | /* We found no match. */ | |
a65babc9 | 6612 | const char *err_msg; |
5614d22c | 6613 | switch (specific_error ? specific_error : i.error) |
a65babc9 L |
6614 | { |
6615 | default: | |
6616 | abort (); | |
86e026a4 | 6617 | case operand_size_mismatch: |
a65babc9 L |
6618 | err_msg = _("operand size mismatch"); |
6619 | break; | |
6620 | case operand_type_mismatch: | |
6621 | err_msg = _("operand type mismatch"); | |
6622 | break; | |
6623 | case register_type_mismatch: | |
6624 | err_msg = _("register type mismatch"); | |
6625 | break; | |
6626 | case number_of_operands_mismatch: | |
6627 | err_msg = _("number of operands mismatch"); | |
6628 | break; | |
6629 | case invalid_instruction_suffix: | |
6630 | err_msg = _("invalid instruction suffix"); | |
6631 | break; | |
6632 | case bad_imm4: | |
4a2608e3 | 6633 | err_msg = _("constant doesn't fit in 4 bits"); |
a65babc9 | 6634 | break; |
a65babc9 L |
6635 | case unsupported_with_intel_mnemonic: |
6636 | err_msg = _("unsupported with Intel mnemonic"); | |
6637 | break; | |
6638 | case unsupported_syntax: | |
6639 | err_msg = _("unsupported syntax"); | |
6640 | break; | |
6641 | case unsupported: | |
35262a23 | 6642 | as_bad (_("unsupported instruction `%s'"), |
10efe3f6 L |
6643 | current_templates->start->name); |
6644 | return NULL; | |
260cd341 LC |
6645 | case invalid_sib_address: |
6646 | err_msg = _("invalid SIB address"); | |
6647 | break; | |
6c30d220 L |
6648 | case invalid_vsib_address: |
6649 | err_msg = _("invalid VSIB address"); | |
6650 | break; | |
7bab8ab5 JB |
6651 | case invalid_vector_register_set: |
6652 | err_msg = _("mask, index, and destination registers must be distinct"); | |
6653 | break; | |
260cd341 LC |
6654 | case invalid_tmm_register_set: |
6655 | err_msg = _("all tmm registers must be distinct"); | |
6656 | break; | |
6c30d220 L |
6657 | case unsupported_vector_index_register: |
6658 | err_msg = _("unsupported vector index register"); | |
6659 | break; | |
43234a1e L |
6660 | case unsupported_broadcast: |
6661 | err_msg = _("unsupported broadcast"); | |
6662 | break; | |
43234a1e L |
6663 | case broadcast_needed: |
6664 | err_msg = _("broadcast is needed for operand of such type"); | |
6665 | break; | |
6666 | case unsupported_masking: | |
6667 | err_msg = _("unsupported masking"); | |
6668 | break; | |
6669 | case mask_not_on_destination: | |
6670 | err_msg = _("mask not on destination operand"); | |
6671 | break; | |
6672 | case no_default_mask: | |
6673 | err_msg = _("default mask isn't allowed"); | |
6674 | break; | |
6675 | case unsupported_rc_sae: | |
6676 | err_msg = _("unsupported static rounding/sae"); | |
6677 | break; | |
6678 | case rc_sae_operand_not_last_imm: | |
6679 | if (intel_syntax) | |
6680 | err_msg = _("RC/SAE operand must precede immediate operands"); | |
6681 | else | |
6682 | err_msg = _("RC/SAE operand must follow immediate operands"); | |
6683 | break; | |
6684 | case invalid_register_operand: | |
6685 | err_msg = _("invalid register operand"); | |
6686 | break; | |
a65babc9 L |
6687 | } |
6688 | as_bad (_("%s for `%s'"), err_msg, | |
891edac4 | 6689 | current_templates->start->name); |
fa99fab2 | 6690 | return NULL; |
29b0f896 | 6691 | } |
252b5132 | 6692 | |
29b0f896 AM |
6693 | if (!quiet_warnings) |
6694 | { | |
6695 | if (!intel_syntax | |
0cfa3eb3 | 6696 | && (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))) |
6f2f06be | 6697 | as_warn (_("indirect %s without `*'"), t->name); |
29b0f896 | 6698 | |
40fb9820 | 6699 | if (t->opcode_modifier.isprefix |
3cd7f3e3 | 6700 | && t->opcode_modifier.mnemonicsize == IGNORESIZE) |
29b0f896 AM |
6701 | { |
6702 | /* Warn them that a data or address size prefix doesn't | |
6703 | affect assembly of the next line of code. */ | |
6704 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
6705 | } | |
6706 | } | |
6707 | ||
6708 | /* Copy the template we found. */ | |
6709 | i.tm = *t; | |
539e75ad L |
6710 | |
6711 | if (addr_prefix_disp != -1) | |
6712 | i.tm.operand_types[addr_prefix_disp] | |
6713 | = operand_types[addr_prefix_disp]; | |
6714 | ||
29b0f896 AM |
6715 | if (found_reverse_match) |
6716 | { | |
dfd69174 JB |
6717 | /* If we found a reverse match we must alter the opcode direction |
6718 | bit and clear/flip the regmem modifier one. found_reverse_match | |
6719 | holds bits to change (different for int & float insns). */ | |
29b0f896 AM |
6720 | |
6721 | i.tm.base_opcode ^= found_reverse_match; | |
6722 | ||
f5eb1d70 JB |
6723 | i.tm.operand_types[0] = operand_types[i.operands - 1]; |
6724 | i.tm.operand_types[i.operands - 1] = operand_types[0]; | |
dfd69174 JB |
6725 | |
6726 | /* Certain SIMD insns have their load forms specified in the opcode | |
6727 | table, and hence we need to _set_ RegMem instead of clearing it. | |
6728 | We need to avoid setting the bit though on insns like KMOVW. */ | |
6729 | i.tm.opcode_modifier.regmem | |
6730 | = i.tm.opcode_modifier.modrm && i.tm.opcode_modifier.d | |
6731 | && i.tm.operands > 2U - i.tm.opcode_modifier.sse2avx | |
6732 | && !i.tm.opcode_modifier.regmem; | |
29b0f896 AM |
6733 | } |
6734 | ||
fa99fab2 | 6735 | return t; |
29b0f896 AM |
6736 | } |
6737 | ||
6738 | static int | |
e3bb37b5 | 6739 | check_string (void) |
29b0f896 | 6740 | { |
51c8edf6 JB |
6741 | unsigned int es_op = i.tm.opcode_modifier.isstring - IS_STRING_ES_OP0; |
6742 | unsigned int op = i.tm.operand_types[0].bitfield.baseindex ? es_op : 0; | |
8dc0818e | 6743 | |
51c8edf6 | 6744 | if (i.seg[op] != NULL && i.seg[op] != &es) |
29b0f896 | 6745 | { |
51c8edf6 JB |
6746 | as_bad (_("`%s' operand %u must use `%ses' segment"), |
6747 | i.tm.name, | |
6748 | intel_syntax ? i.tm.operands - es_op : es_op + 1, | |
6749 | register_prefix); | |
6750 | return 0; | |
29b0f896 | 6751 | } |
51c8edf6 JB |
6752 | |
6753 | /* There's only ever one segment override allowed per instruction. | |
6754 | This instruction possibly has a legal segment override on the | |
6755 | second operand, so copy the segment to where non-string | |
6756 | instructions store it, allowing common code. */ | |
6757 | i.seg[op] = i.seg[1]; | |
6758 | ||
29b0f896 AM |
6759 | return 1; |
6760 | } | |
6761 | ||
6762 | static int | |
543613e9 | 6763 | process_suffix (void) |
29b0f896 AM |
6764 | { |
6765 | /* If matched instruction specifies an explicit instruction mnemonic | |
6766 | suffix, use it. */ | |
673fe0f0 | 6767 | if (i.tm.opcode_modifier.size == SIZE16) |
40fb9820 | 6768 | i.suffix = WORD_MNEM_SUFFIX; |
673fe0f0 | 6769 | else if (i.tm.opcode_modifier.size == SIZE32) |
40fb9820 | 6770 | i.suffix = LONG_MNEM_SUFFIX; |
673fe0f0 | 6771 | else if (i.tm.opcode_modifier.size == SIZE64) |
40fb9820 | 6772 | i.suffix = QWORD_MNEM_SUFFIX; |
13e600d0 | 6773 | else if (i.reg_operands |
c8f8eebc JB |
6774 | && (i.operands > 1 || i.types[0].bitfield.class == Reg) |
6775 | && !i.tm.opcode_modifier.addrprefixopreg) | |
29b0f896 | 6776 | { |
65fca059 JB |
6777 | unsigned int numop = i.operands; |
6778 | ||
6779 | /* movsx/movzx want only their source operand considered here, for the | |
6780 | ambiguity checking below. The suffix will be replaced afterwards | |
6781 | to represent the destination (register). */ | |
6782 | if (((i.tm.base_opcode | 8) == 0xfbe && i.tm.opcode_modifier.w) | |
6783 | || (i.tm.base_opcode == 0x63 && i.tm.cpu_flags.bitfield.cpu64)) | |
6784 | --i.operands; | |
6785 | ||
643bb870 JB |
6786 | /* crc32 needs REX.W set regardless of suffix / source operand size. */ |
6787 | if (i.tm.base_opcode == 0xf20f38f0 | |
6788 | && i.tm.operand_types[1].bitfield.qword) | |
6789 | i.rex |= REX_W; | |
6790 | ||
29b0f896 | 6791 | /* If there's no instruction mnemonic suffix we try to invent one |
13e600d0 | 6792 | based on GPR operands. */ |
29b0f896 AM |
6793 | if (!i.suffix) |
6794 | { | |
6795 | /* We take i.suffix from the last register operand specified, | |
6796 | Destination register type is more significant than source | |
381d071f L |
6797 | register type. crc32 in SSE4.2 prefers source register |
6798 | type. */ | |
1a035124 | 6799 | unsigned int op = i.tm.base_opcode != 0xf20f38f0 ? i.operands : 1; |
20592a94 | 6800 | |
1a035124 JB |
6801 | while (op--) |
6802 | if (i.tm.operand_types[op].bitfield.instance == InstanceNone | |
6803 | || i.tm.operand_types[op].bitfield.instance == Accum) | |
6804 | { | |
6805 | if (i.types[op].bitfield.class != Reg) | |
6806 | continue; | |
6807 | if (i.types[op].bitfield.byte) | |
6808 | i.suffix = BYTE_MNEM_SUFFIX; | |
6809 | else if (i.types[op].bitfield.word) | |
6810 | i.suffix = WORD_MNEM_SUFFIX; | |
6811 | else if (i.types[op].bitfield.dword) | |
6812 | i.suffix = LONG_MNEM_SUFFIX; | |
6813 | else if (i.types[op].bitfield.qword) | |
6814 | i.suffix = QWORD_MNEM_SUFFIX; | |
6815 | else | |
6816 | continue; | |
6817 | break; | |
6818 | } | |
65fca059 JB |
6819 | |
6820 | /* As an exception, movsx/movzx silently default to a byte source | |
6821 | in AT&T mode. */ | |
6822 | if ((i.tm.base_opcode | 8) == 0xfbe && i.tm.opcode_modifier.w | |
6823 | && !i.suffix && !intel_syntax) | |
6824 | i.suffix = BYTE_MNEM_SUFFIX; | |
29b0f896 AM |
6825 | } |
6826 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
6827 | { | |
2eb952a4 | 6828 | if (intel_syntax |
3cd7f3e3 | 6829 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE |
2eb952a4 L |
6830 | && i.tm.opcode_modifier.no_bsuf) |
6831 | i.suffix = 0; | |
6832 | else if (!check_byte_reg ()) | |
29b0f896 AM |
6833 | return 0; |
6834 | } | |
6835 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
6836 | { | |
2eb952a4 | 6837 | if (intel_syntax |
3cd7f3e3 | 6838 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE |
9f123b91 JB |
6839 | && i.tm.opcode_modifier.no_lsuf |
6840 | && !i.tm.opcode_modifier.todword | |
6841 | && !i.tm.opcode_modifier.toqword) | |
2eb952a4 L |
6842 | i.suffix = 0; |
6843 | else if (!check_long_reg ()) | |
29b0f896 AM |
6844 | return 0; |
6845 | } | |
6846 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
6847 | { | |
955e1e6a | 6848 | if (intel_syntax |
3cd7f3e3 | 6849 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE |
9f123b91 JB |
6850 | && i.tm.opcode_modifier.no_qsuf |
6851 | && !i.tm.opcode_modifier.todword | |
6852 | && !i.tm.opcode_modifier.toqword) | |
955e1e6a L |
6853 | i.suffix = 0; |
6854 | else if (!check_qword_reg ()) | |
29b0f896 AM |
6855 | return 0; |
6856 | } | |
6857 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
6858 | { | |
2eb952a4 | 6859 | if (intel_syntax |
3cd7f3e3 | 6860 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE |
2eb952a4 L |
6861 | && i.tm.opcode_modifier.no_wsuf) |
6862 | i.suffix = 0; | |
6863 | else if (!check_word_reg ()) | |
29b0f896 AM |
6864 | return 0; |
6865 | } | |
3cd7f3e3 L |
6866 | else if (intel_syntax |
6867 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE) | |
29b0f896 AM |
6868 | /* Do nothing if the instruction is going to ignore the prefix. */ |
6869 | ; | |
6870 | else | |
6871 | abort (); | |
65fca059 JB |
6872 | |
6873 | /* Undo the movsx/movzx change done above. */ | |
6874 | i.operands = numop; | |
29b0f896 | 6875 | } |
3cd7f3e3 L |
6876 | else if (i.tm.opcode_modifier.mnemonicsize == DEFAULTSIZE |
6877 | && !i.suffix) | |
29b0f896 | 6878 | { |
13e600d0 JB |
6879 | i.suffix = stackop_size; |
6880 | if (stackop_size == LONG_MNEM_SUFFIX) | |
06f74c5c L |
6881 | { |
6882 | /* stackop_size is set to LONG_MNEM_SUFFIX for the | |
6883 | .code16gcc directive to support 16-bit mode with | |
6884 | 32-bit address. For IRET without a suffix, generate | |
6885 | 16-bit IRET (opcode 0xcf) to return from an interrupt | |
6886 | handler. */ | |
13e600d0 JB |
6887 | if (i.tm.base_opcode == 0xcf) |
6888 | { | |
6889 | i.suffix = WORD_MNEM_SUFFIX; | |
6890 | as_warn (_("generating 16-bit `iret' for .code16gcc directive")); | |
6891 | } | |
6892 | /* Warn about changed behavior for segment register push/pop. */ | |
6893 | else if ((i.tm.base_opcode | 1) == 0x07) | |
6894 | as_warn (_("generating 32-bit `%s', unlike earlier gas versions"), | |
6895 | i.tm.name); | |
06f74c5c | 6896 | } |
29b0f896 | 6897 | } |
c006a730 | 6898 | else if (!i.suffix |
0cfa3eb3 JB |
6899 | && (i.tm.opcode_modifier.jump == JUMP_ABSOLUTE |
6900 | || i.tm.opcode_modifier.jump == JUMP_BYTE | |
6901 | || i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT | |
64e74474 AM |
6902 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
6903 | && i.tm.extension_opcode <= 3))) | |
9306ca4a JB |
6904 | { |
6905 | switch (flag_code) | |
6906 | { | |
6907 | case CODE_64BIT: | |
40fb9820 | 6908 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a | 6909 | { |
828c2a25 JB |
6910 | if (i.tm.opcode_modifier.jump == JUMP_BYTE |
6911 | || i.tm.opcode_modifier.no_lsuf) | |
6912 | i.suffix = QWORD_MNEM_SUFFIX; | |
9306ca4a JB |
6913 | break; |
6914 | } | |
1a0670f3 | 6915 | /* Fall through. */ |
9306ca4a | 6916 | case CODE_32BIT: |
40fb9820 | 6917 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
6918 | i.suffix = LONG_MNEM_SUFFIX; |
6919 | break; | |
6920 | case CODE_16BIT: | |
40fb9820 | 6921 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
6922 | i.suffix = WORD_MNEM_SUFFIX; |
6923 | break; | |
6924 | } | |
6925 | } | |
252b5132 | 6926 | |
c006a730 | 6927 | if (!i.suffix |
3cd7f3e3 | 6928 | && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE |
873494c8 JB |
6929 | /* Also cover lret/retf/iret in 64-bit mode. */ |
6930 | || (flag_code == CODE_64BIT | |
6931 | && !i.tm.opcode_modifier.no_lsuf | |
6932 | && !i.tm.opcode_modifier.no_qsuf)) | |
3cd7f3e3 | 6933 | && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE |
8bbb3ad8 JB |
6934 | /* Explicit sizing prefixes are assumed to disambiguate insns. */ |
6935 | && !i.prefix[DATA_PREFIX] && !(i.prefix[REX_PREFIX] & REX_W) | |
62b3f548 JB |
6936 | /* Accept FLDENV et al without suffix. */ |
6937 | && (i.tm.opcode_modifier.no_ssuf || i.tm.opcode_modifier.floatmf)) | |
29b0f896 | 6938 | { |
6c0946d0 | 6939 | unsigned int suffixes, evex = 0; |
c006a730 JB |
6940 | |
6941 | suffixes = !i.tm.opcode_modifier.no_bsuf; | |
6942 | if (!i.tm.opcode_modifier.no_wsuf) | |
6943 | suffixes |= 1 << 1; | |
6944 | if (!i.tm.opcode_modifier.no_lsuf) | |
6945 | suffixes |= 1 << 2; | |
6946 | if (!i.tm.opcode_modifier.no_ldsuf) | |
6947 | suffixes |= 1 << 3; | |
6948 | if (!i.tm.opcode_modifier.no_ssuf) | |
6949 | suffixes |= 1 << 4; | |
6950 | if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) | |
6951 | suffixes |= 1 << 5; | |
6952 | ||
6c0946d0 JB |
6953 | /* For [XYZ]MMWORD operands inspect operand sizes. While generally |
6954 | also suitable for AT&T syntax mode, it was requested that this be | |
6955 | restricted to just Intel syntax. */ | |
b9915cbc | 6956 | if (intel_syntax && is_any_vex_encoding (&i.tm) && !i.broadcast) |
6c0946d0 | 6957 | { |
b9915cbc | 6958 | unsigned int op; |
6c0946d0 | 6959 | |
b9915cbc | 6960 | for (op = 0; op < i.tm.operands; ++op) |
6c0946d0 | 6961 | { |
b9915cbc JB |
6962 | if (is_evex_encoding (&i.tm) |
6963 | && !cpu_arch_flags.bitfield.cpuavx512vl) | |
6c0946d0 | 6964 | { |
b9915cbc JB |
6965 | if (i.tm.operand_types[op].bitfield.ymmword) |
6966 | i.tm.operand_types[op].bitfield.xmmword = 0; | |
6967 | if (i.tm.operand_types[op].bitfield.zmmword) | |
6968 | i.tm.operand_types[op].bitfield.ymmword = 0; | |
6969 | if (!i.tm.opcode_modifier.evex | |
6970 | || i.tm.opcode_modifier.evex == EVEXDYN) | |
6971 | i.tm.opcode_modifier.evex = EVEX512; | |
6972 | } | |
6c0946d0 | 6973 | |
b9915cbc JB |
6974 | if (i.tm.operand_types[op].bitfield.xmmword |
6975 | + i.tm.operand_types[op].bitfield.ymmword | |
6976 | + i.tm.operand_types[op].bitfield.zmmword < 2) | |
6977 | continue; | |
6c0946d0 | 6978 | |
b9915cbc JB |
6979 | /* Any properly sized operand disambiguates the insn. */ |
6980 | if (i.types[op].bitfield.xmmword | |
6981 | || i.types[op].bitfield.ymmword | |
6982 | || i.types[op].bitfield.zmmword) | |
6983 | { | |
6984 | suffixes &= ~(7 << 6); | |
6985 | evex = 0; | |
6986 | break; | |
6987 | } | |
6c0946d0 | 6988 | |
b9915cbc JB |
6989 | if ((i.flags[op] & Operand_Mem) |
6990 | && i.tm.operand_types[op].bitfield.unspecified) | |
6991 | { | |
6992 | if (i.tm.operand_types[op].bitfield.xmmword) | |
6993 | suffixes |= 1 << 6; | |
6994 | if (i.tm.operand_types[op].bitfield.ymmword) | |
6995 | suffixes |= 1 << 7; | |
6996 | if (i.tm.operand_types[op].bitfield.zmmword) | |
6997 | suffixes |= 1 << 8; | |
6998 | if (is_evex_encoding (&i.tm)) | |
6999 | evex = EVEX512; | |
6c0946d0 JB |
7000 | } |
7001 | } | |
7002 | } | |
7003 | ||
7004 | /* Are multiple suffixes / operand sizes allowed? */ | |
c006a730 | 7005 | if (suffixes & (suffixes - 1)) |
9306ca4a | 7006 | { |
873494c8 | 7007 | if (intel_syntax |
3cd7f3e3 | 7008 | && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE |
873494c8 | 7009 | || operand_check == check_error)) |
9306ca4a | 7010 | { |
c006a730 | 7011 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
9306ca4a JB |
7012 | return 0; |
7013 | } | |
c006a730 | 7014 | if (operand_check == check_error) |
9306ca4a | 7015 | { |
c006a730 JB |
7016 | as_bad (_("no instruction mnemonic suffix given and " |
7017 | "no register operands; can't size `%s'"), i.tm.name); | |
9306ca4a JB |
7018 | return 0; |
7019 | } | |
c006a730 | 7020 | if (operand_check == check_warning) |
873494c8 JB |
7021 | as_warn (_("%s; using default for `%s'"), |
7022 | intel_syntax | |
7023 | ? _("ambiguous operand size") | |
7024 | : _("no instruction mnemonic suffix given and " | |
7025 | "no register operands"), | |
7026 | i.tm.name); | |
c006a730 JB |
7027 | |
7028 | if (i.tm.opcode_modifier.floatmf) | |
7029 | i.suffix = SHORT_MNEM_SUFFIX; | |
65fca059 JB |
7030 | else if ((i.tm.base_opcode | 8) == 0xfbe |
7031 | || (i.tm.base_opcode == 0x63 | |
7032 | && i.tm.cpu_flags.bitfield.cpu64)) | |
7033 | /* handled below */; | |
6c0946d0 JB |
7034 | else if (evex) |
7035 | i.tm.opcode_modifier.evex = evex; | |
c006a730 JB |
7036 | else if (flag_code == CODE_16BIT) |
7037 | i.suffix = WORD_MNEM_SUFFIX; | |
1a035124 | 7038 | else if (!i.tm.opcode_modifier.no_lsuf) |
c006a730 | 7039 | i.suffix = LONG_MNEM_SUFFIX; |
1a035124 JB |
7040 | else |
7041 | i.suffix = QWORD_MNEM_SUFFIX; | |
9306ca4a | 7042 | } |
29b0f896 | 7043 | } |
252b5132 | 7044 | |
65fca059 JB |
7045 | if ((i.tm.base_opcode | 8) == 0xfbe |
7046 | || (i.tm.base_opcode == 0x63 && i.tm.cpu_flags.bitfield.cpu64)) | |
7047 | { | |
7048 | /* In Intel syntax, movsx/movzx must have a "suffix" (checked above). | |
7049 | In AT&T syntax, if there is no suffix (warned about above), the default | |
7050 | will be byte extension. */ | |
7051 | if (i.tm.opcode_modifier.w && i.suffix && i.suffix != BYTE_MNEM_SUFFIX) | |
7052 | i.tm.base_opcode |= 1; | |
7053 | ||
7054 | /* For further processing, the suffix should represent the destination | |
7055 | (register). This is already the case when one was used with | |
7056 | mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was | |
7057 | no suffix to begin with. */ | |
7058 | if (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63 || !i.suffix) | |
7059 | { | |
7060 | if (i.types[1].bitfield.word) | |
7061 | i.suffix = WORD_MNEM_SUFFIX; | |
7062 | else if (i.types[1].bitfield.qword) | |
7063 | i.suffix = QWORD_MNEM_SUFFIX; | |
7064 | else | |
7065 | i.suffix = LONG_MNEM_SUFFIX; | |
7066 | ||
7067 | i.tm.opcode_modifier.w = 0; | |
7068 | } | |
7069 | } | |
7070 | ||
50128d0c JB |
7071 | if (!i.tm.opcode_modifier.modrm && i.reg_operands && i.tm.operands < 3) |
7072 | i.short_form = (i.tm.operand_types[0].bitfield.class == Reg) | |
7073 | != (i.tm.operand_types[1].bitfield.class == Reg); | |
7074 | ||
d2224064 JB |
7075 | /* Change the opcode based on the operand size given by i.suffix. */ |
7076 | switch (i.suffix) | |
29b0f896 | 7077 | { |
d2224064 JB |
7078 | /* Size floating point instruction. */ |
7079 | case LONG_MNEM_SUFFIX: | |
7080 | if (i.tm.opcode_modifier.floatmf) | |
7081 | { | |
7082 | i.tm.base_opcode ^= 4; | |
7083 | break; | |
7084 | } | |
7085 | /* fall through */ | |
7086 | case WORD_MNEM_SUFFIX: | |
7087 | case QWORD_MNEM_SUFFIX: | |
29b0f896 | 7088 | /* It's not a byte, select word/dword operation. */ |
40fb9820 | 7089 | if (i.tm.opcode_modifier.w) |
29b0f896 | 7090 | { |
50128d0c | 7091 | if (i.short_form) |
29b0f896 AM |
7092 | i.tm.base_opcode |= 8; |
7093 | else | |
7094 | i.tm.base_opcode |= 1; | |
7095 | } | |
d2224064 JB |
7096 | /* fall through */ |
7097 | case SHORT_MNEM_SUFFIX: | |
29b0f896 AM |
7098 | /* Now select between word & dword operations via the operand |
7099 | size prefix, except for instructions that will ignore this | |
7100 | prefix anyway. */ | |
c8f8eebc | 7101 | if (i.suffix != QWORD_MNEM_SUFFIX |
3cd7f3e3 | 7102 | && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE |
c8f8eebc JB |
7103 | && !i.tm.opcode_modifier.floatmf |
7104 | && !is_any_vex_encoding (&i.tm) | |
7105 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) | |
7106 | || (flag_code == CODE_64BIT | |
7107 | && i.tm.opcode_modifier.jump == JUMP_BYTE))) | |
24eab124 AM |
7108 | { |
7109 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 7110 | |
0cfa3eb3 | 7111 | if (i.tm.opcode_modifier.jump == JUMP_BYTE) /* jcxz, loop */ |
29b0f896 | 7112 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 7113 | |
29b0f896 AM |
7114 | if (!add_prefix (prefix)) |
7115 | return 0; | |
24eab124 | 7116 | } |
252b5132 | 7117 | |
29b0f896 AM |
7118 | /* Set mode64 for an operand. */ |
7119 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 7120 | && flag_code == CODE_64BIT |
d2224064 | 7121 | && !i.tm.opcode_modifier.norex64 |
4ed21b58 | 7122 | && !i.tm.opcode_modifier.vexw |
46e883c5 | 7123 | /* Special case for xchg %rax,%rax. It is NOP and doesn't |
d2224064 JB |
7124 | need rex64. */ |
7125 | && ! (i.operands == 2 | |
7126 | && i.tm.base_opcode == 0x90 | |
7127 | && i.tm.extension_opcode == None | |
75e5731b JB |
7128 | && i.types[0].bitfield.instance == Accum |
7129 | && i.types[0].bitfield.qword | |
7130 | && i.types[1].bitfield.instance == Accum | |
7131 | && i.types[1].bitfield.qword)) | |
d2224064 | 7132 | i.rex |= REX_W; |
3e73aa7c | 7133 | |
d2224064 | 7134 | break; |
8bbb3ad8 JB |
7135 | |
7136 | case 0: | |
7137 | /* Select word/dword/qword operation with explict data sizing prefix | |
7138 | when there are no suitable register operands. */ | |
7139 | if (i.tm.opcode_modifier.w | |
7140 | && (i.prefix[DATA_PREFIX] || (i.prefix[REX_PREFIX] & REX_W)) | |
7141 | && (!i.reg_operands | |
7142 | || (i.reg_operands == 1 | |
7143 | /* ShiftCount */ | |
7144 | && (i.tm.operand_types[0].bitfield.instance == RegC | |
7145 | /* InOutPortReg */ | |
7146 | || i.tm.operand_types[0].bitfield.instance == RegD | |
7147 | || i.tm.operand_types[1].bitfield.instance == RegD | |
7148 | /* CRC32 */ | |
7149 | || i.tm.base_opcode == 0xf20f38f0)))) | |
7150 | i.tm.base_opcode |= 1; | |
7151 | break; | |
29b0f896 | 7152 | } |
7ecd2f8b | 7153 | |
c8f8eebc | 7154 | if (i.tm.opcode_modifier.addrprefixopreg) |
c0a30a9f | 7155 | { |
c8f8eebc JB |
7156 | gas_assert (!i.suffix); |
7157 | gas_assert (i.reg_operands); | |
c0a30a9f | 7158 | |
c8f8eebc JB |
7159 | if (i.tm.operand_types[0].bitfield.instance == Accum |
7160 | || i.operands == 1) | |
7161 | { | |
7162 | /* The address size override prefix changes the size of the | |
7163 | first operand. */ | |
7164 | if (flag_code == CODE_64BIT | |
7165 | && i.op[0].regs->reg_type.bitfield.word) | |
7166 | { | |
7167 | as_bad (_("16-bit addressing unavailable for `%s'"), | |
7168 | i.tm.name); | |
7169 | return 0; | |
7170 | } | |
7171 | ||
7172 | if ((flag_code == CODE_32BIT | |
7173 | ? i.op[0].regs->reg_type.bitfield.word | |
7174 | : i.op[0].regs->reg_type.bitfield.dword) | |
7175 | && !add_prefix (ADDR_PREFIX_OPCODE)) | |
7176 | return 0; | |
7177 | } | |
c0a30a9f L |
7178 | else |
7179 | { | |
c8f8eebc JB |
7180 | /* Check invalid register operand when the address size override |
7181 | prefix changes the size of register operands. */ | |
7182 | unsigned int op; | |
7183 | enum { need_word, need_dword, need_qword } need; | |
7184 | ||
7185 | if (flag_code == CODE_32BIT) | |
7186 | need = i.prefix[ADDR_PREFIX] ? need_word : need_dword; | |
7187 | else if (i.prefix[ADDR_PREFIX]) | |
c0a30a9f L |
7188 | need = need_dword; |
7189 | else | |
7190 | need = flag_code == CODE_64BIT ? need_qword : need_word; | |
c0a30a9f | 7191 | |
c8f8eebc JB |
7192 | for (op = 0; op < i.operands; op++) |
7193 | { | |
7194 | if (i.types[op].bitfield.class != Reg) | |
7195 | continue; | |
7196 | ||
7197 | switch (need) | |
7198 | { | |
7199 | case need_word: | |
7200 | if (i.op[op].regs->reg_type.bitfield.word) | |
7201 | continue; | |
7202 | break; | |
7203 | case need_dword: | |
7204 | if (i.op[op].regs->reg_type.bitfield.dword) | |
7205 | continue; | |
7206 | break; | |
7207 | case need_qword: | |
7208 | if (i.op[op].regs->reg_type.bitfield.qword) | |
7209 | continue; | |
7210 | break; | |
7211 | } | |
7212 | ||
7213 | as_bad (_("invalid register operand size for `%s'"), | |
7214 | i.tm.name); | |
7215 | return 0; | |
7216 | } | |
7217 | } | |
c0a30a9f L |
7218 | } |
7219 | ||
29b0f896 AM |
7220 | return 1; |
7221 | } | |
3e73aa7c | 7222 | |
29b0f896 | 7223 | static int |
543613e9 | 7224 | check_byte_reg (void) |
29b0f896 AM |
7225 | { |
7226 | int op; | |
543613e9 | 7227 | |
29b0f896 AM |
7228 | for (op = i.operands; --op >= 0;) |
7229 | { | |
dc821c5f | 7230 | /* Skip non-register operands. */ |
bab6aec1 | 7231 | if (i.types[op].bitfield.class != Reg) |
dc821c5f JB |
7232 | continue; |
7233 | ||
29b0f896 AM |
7234 | /* If this is an eight bit register, it's OK. If it's the 16 or |
7235 | 32 bit version of an eight bit register, we will just use the | |
7236 | low portion, and that's OK too. */ | |
dc821c5f | 7237 | if (i.types[op].bitfield.byte) |
29b0f896 AM |
7238 | continue; |
7239 | ||
5a819eb9 | 7240 | /* I/O port address operands are OK too. */ |
75e5731b JB |
7241 | if (i.tm.operand_types[op].bitfield.instance == RegD |
7242 | && i.tm.operand_types[op].bitfield.word) | |
5a819eb9 JB |
7243 | continue; |
7244 | ||
9706160a JB |
7245 | /* crc32 only wants its source operand checked here. */ |
7246 | if (i.tm.base_opcode == 0xf20f38f0 && op) | |
9344ff29 L |
7247 | continue; |
7248 | ||
29b0f896 | 7249 | /* Any other register is bad. */ |
73c76375 JB |
7250 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
7251 | register_prefix, i.op[op].regs->reg_name, | |
7252 | i.tm.name, i.suffix); | |
7253 | return 0; | |
29b0f896 AM |
7254 | } |
7255 | return 1; | |
7256 | } | |
7257 | ||
7258 | static int | |
e3bb37b5 | 7259 | check_long_reg (void) |
29b0f896 AM |
7260 | { |
7261 | int op; | |
7262 | ||
7263 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 7264 | /* Skip non-register operands. */ |
bab6aec1 | 7265 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 7266 | continue; |
29b0f896 AM |
7267 | /* Reject eight bit registers, except where the template requires |
7268 | them. (eg. movzb) */ | |
dc821c5f | 7269 | else if (i.types[op].bitfield.byte |
bab6aec1 | 7270 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7271 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
7272 | && (i.tm.operand_types[op].bitfield.word |
7273 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 7274 | { |
a540244d L |
7275 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
7276 | register_prefix, | |
29b0f896 AM |
7277 | i.op[op].regs->reg_name, |
7278 | i.tm.name, | |
7279 | i.suffix); | |
7280 | return 0; | |
7281 | } | |
be4c5e58 L |
7282 | /* Error if the e prefix on a general reg is missing. */ |
7283 | else if (i.types[op].bitfield.word | |
bab6aec1 | 7284 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7285 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 7286 | && i.tm.operand_types[op].bitfield.dword) |
29b0f896 | 7287 | { |
be4c5e58 L |
7288 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
7289 | register_prefix, i.op[op].regs->reg_name, | |
7290 | i.suffix); | |
7291 | return 0; | |
252b5132 | 7292 | } |
e4630f71 | 7293 | /* Warn if the r prefix on a general reg is present. */ |
dc821c5f | 7294 | else if (i.types[op].bitfield.qword |
bab6aec1 | 7295 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7296 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 7297 | && i.tm.operand_types[op].bitfield.dword) |
252b5132 | 7298 | { |
34828aad | 7299 | if (intel_syntax |
65fca059 | 7300 | && i.tm.opcode_modifier.toqword |
3528c362 | 7301 | && i.types[0].bitfield.class != RegSIMD) |
34828aad | 7302 | { |
ca61edf2 | 7303 | /* Convert to QWORD. We want REX byte. */ |
34828aad L |
7304 | i.suffix = QWORD_MNEM_SUFFIX; |
7305 | } | |
7306 | else | |
7307 | { | |
2b5d6a91 | 7308 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
7309 | register_prefix, i.op[op].regs->reg_name, |
7310 | i.suffix); | |
7311 | return 0; | |
7312 | } | |
29b0f896 AM |
7313 | } |
7314 | return 1; | |
7315 | } | |
252b5132 | 7316 | |
29b0f896 | 7317 | static int |
e3bb37b5 | 7318 | check_qword_reg (void) |
29b0f896 AM |
7319 | { |
7320 | int op; | |
252b5132 | 7321 | |
29b0f896 | 7322 | for (op = i.operands; --op >= 0; ) |
dc821c5f | 7323 | /* Skip non-register operands. */ |
bab6aec1 | 7324 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 7325 | continue; |
29b0f896 AM |
7326 | /* Reject eight bit registers, except where the template requires |
7327 | them. (eg. movzb) */ | |
dc821c5f | 7328 | else if (i.types[op].bitfield.byte |
bab6aec1 | 7329 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7330 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
7331 | && (i.tm.operand_types[op].bitfield.word |
7332 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 7333 | { |
a540244d L |
7334 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
7335 | register_prefix, | |
29b0f896 AM |
7336 | i.op[op].regs->reg_name, |
7337 | i.tm.name, | |
7338 | i.suffix); | |
7339 | return 0; | |
7340 | } | |
e4630f71 | 7341 | /* Warn if the r prefix on a general reg is missing. */ |
dc821c5f JB |
7342 | else if ((i.types[op].bitfield.word |
7343 | || i.types[op].bitfield.dword) | |
bab6aec1 | 7344 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7345 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 7346 | && i.tm.operand_types[op].bitfield.qword) |
29b0f896 AM |
7347 | { |
7348 | /* Prohibit these changes in the 64bit mode, since the | |
7349 | lowering is more complicated. */ | |
34828aad | 7350 | if (intel_syntax |
ca61edf2 | 7351 | && i.tm.opcode_modifier.todword |
3528c362 | 7352 | && i.types[0].bitfield.class != RegSIMD) |
34828aad | 7353 | { |
ca61edf2 | 7354 | /* Convert to DWORD. We don't want REX byte. */ |
34828aad L |
7355 | i.suffix = LONG_MNEM_SUFFIX; |
7356 | } | |
7357 | else | |
7358 | { | |
2b5d6a91 | 7359 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
7360 | register_prefix, i.op[op].regs->reg_name, |
7361 | i.suffix); | |
7362 | return 0; | |
7363 | } | |
252b5132 | 7364 | } |
29b0f896 AM |
7365 | return 1; |
7366 | } | |
252b5132 | 7367 | |
29b0f896 | 7368 | static int |
e3bb37b5 | 7369 | check_word_reg (void) |
29b0f896 AM |
7370 | { |
7371 | int op; | |
7372 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 7373 | /* Skip non-register operands. */ |
bab6aec1 | 7374 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 7375 | continue; |
29b0f896 AM |
7376 | /* Reject eight bit registers, except where the template requires |
7377 | them. (eg. movzb) */ | |
dc821c5f | 7378 | else if (i.types[op].bitfield.byte |
bab6aec1 | 7379 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7380 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
7381 | && (i.tm.operand_types[op].bitfield.word |
7382 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 7383 | { |
a540244d L |
7384 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
7385 | register_prefix, | |
29b0f896 AM |
7386 | i.op[op].regs->reg_name, |
7387 | i.tm.name, | |
7388 | i.suffix); | |
7389 | return 0; | |
7390 | } | |
9706160a JB |
7391 | /* Error if the e or r prefix on a general reg is present. */ |
7392 | else if ((i.types[op].bitfield.dword | |
dc821c5f | 7393 | || i.types[op].bitfield.qword) |
bab6aec1 | 7394 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7395 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 7396 | && i.tm.operand_types[op].bitfield.word) |
252b5132 | 7397 | { |
9706160a JB |
7398 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
7399 | register_prefix, i.op[op].regs->reg_name, | |
7400 | i.suffix); | |
7401 | return 0; | |
29b0f896 AM |
7402 | } |
7403 | return 1; | |
7404 | } | |
252b5132 | 7405 | |
29b0f896 | 7406 | static int |
40fb9820 | 7407 | update_imm (unsigned int j) |
29b0f896 | 7408 | { |
bc0844ae | 7409 | i386_operand_type overlap = i.types[j]; |
40fb9820 L |
7410 | if ((overlap.bitfield.imm8 |
7411 | || overlap.bitfield.imm8s | |
7412 | || overlap.bitfield.imm16 | |
7413 | || overlap.bitfield.imm32 | |
7414 | || overlap.bitfield.imm32s | |
7415 | || overlap.bitfield.imm64) | |
0dfbf9d7 L |
7416 | && !operand_type_equal (&overlap, &imm8) |
7417 | && !operand_type_equal (&overlap, &imm8s) | |
7418 | && !operand_type_equal (&overlap, &imm16) | |
7419 | && !operand_type_equal (&overlap, &imm32) | |
7420 | && !operand_type_equal (&overlap, &imm32s) | |
7421 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 AM |
7422 | { |
7423 | if (i.suffix) | |
7424 | { | |
40fb9820 L |
7425 | i386_operand_type temp; |
7426 | ||
0dfbf9d7 | 7427 | operand_type_set (&temp, 0); |
7ab9ffdd | 7428 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
7429 | { |
7430 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
7431 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
7432 | } | |
7433 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
7434 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
7435 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
7436 | { | |
7437 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
7438 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
7439 | } | |
7440 | else | |
7441 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
7442 | overlap = temp; | |
29b0f896 | 7443 | } |
0dfbf9d7 L |
7444 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
7445 | || operand_type_equal (&overlap, &imm16_32) | |
7446 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 7447 | { |
40fb9820 | 7448 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 7449 | overlap = imm16; |
40fb9820 | 7450 | else |
65da13b5 | 7451 | overlap = imm32s; |
29b0f896 | 7452 | } |
8bbb3ad8 JB |
7453 | else if (i.prefix[REX_PREFIX] & REX_W) |
7454 | overlap = operand_type_and (overlap, imm32s); | |
7455 | else if (i.prefix[DATA_PREFIX]) | |
7456 | overlap = operand_type_and (overlap, | |
7457 | flag_code != CODE_16BIT ? imm16 : imm32); | |
0dfbf9d7 L |
7458 | if (!operand_type_equal (&overlap, &imm8) |
7459 | && !operand_type_equal (&overlap, &imm8s) | |
7460 | && !operand_type_equal (&overlap, &imm16) | |
7461 | && !operand_type_equal (&overlap, &imm32) | |
7462 | && !operand_type_equal (&overlap, &imm32s) | |
7463 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 | 7464 | { |
4eed87de AM |
7465 | as_bad (_("no instruction mnemonic suffix given; " |
7466 | "can't determine immediate size")); | |
29b0f896 AM |
7467 | return 0; |
7468 | } | |
7469 | } | |
40fb9820 | 7470 | i.types[j] = overlap; |
29b0f896 | 7471 | |
40fb9820 L |
7472 | return 1; |
7473 | } | |
7474 | ||
7475 | static int | |
7476 | finalize_imm (void) | |
7477 | { | |
bc0844ae | 7478 | unsigned int j, n; |
29b0f896 | 7479 | |
bc0844ae L |
7480 | /* Update the first 2 immediate operands. */ |
7481 | n = i.operands > 2 ? 2 : i.operands; | |
7482 | if (n) | |
7483 | { | |
7484 | for (j = 0; j < n; j++) | |
7485 | if (update_imm (j) == 0) | |
7486 | return 0; | |
40fb9820 | 7487 | |
bc0844ae L |
7488 | /* The 3rd operand can't be immediate operand. */ |
7489 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
7490 | } | |
29b0f896 AM |
7491 | |
7492 | return 1; | |
7493 | } | |
7494 | ||
7495 | static int | |
e3bb37b5 | 7496 | process_operands (void) |
29b0f896 AM |
7497 | { |
7498 | /* Default segment register this instruction will use for memory | |
7499 | accesses. 0 means unknown. This is only for optimizing out | |
7500 | unnecessary segment overrides. */ | |
7501 | const seg_entry *default_seg = 0; | |
7502 | ||
a5aeccd9 JB |
7503 | if (i.tm.opcode_modifier.sse2avx) |
7504 | { | |
7505 | /* Legacy encoded insns allow explicit REX prefixes, so these prefixes | |
7506 | need converting. */ | |
7507 | i.rex |= i.prefix[REX_PREFIX] & (REX_W | REX_R | REX_X | REX_B); | |
7508 | i.prefix[REX_PREFIX] = 0; | |
7509 | i.rex_encoding = 0; | |
7510 | } | |
c423d21a JB |
7511 | /* ImmExt should be processed after SSE2AVX. */ |
7512 | else if (i.tm.opcode_modifier.immext) | |
7513 | process_immext (); | |
a5aeccd9 | 7514 | |
2426c15f | 7515 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
29b0f896 | 7516 | { |
91d6fa6a NC |
7517 | unsigned int dupl = i.operands; |
7518 | unsigned int dest = dupl - 1; | |
9fcfb3d7 L |
7519 | unsigned int j; |
7520 | ||
c0f3af97 | 7521 | /* The destination must be an xmm register. */ |
9c2799c2 | 7522 | gas_assert (i.reg_operands |
91d6fa6a | 7523 | && MAX_OPERANDS > dupl |
7ab9ffdd | 7524 | && operand_type_equal (&i.types[dest], ®xmm)); |
c0f3af97 | 7525 | |
75e5731b | 7526 | if (i.tm.operand_types[0].bitfield.instance == Accum |
1b54b8d7 | 7527 | && i.tm.operand_types[0].bitfield.xmmword) |
e2ec9d29 | 7528 | { |
8cd7925b | 7529 | if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) |
c0f3af97 L |
7530 | { |
7531 | /* Keep xmm0 for instructions with VEX prefix and 3 | |
7532 | sources. */ | |
75e5731b | 7533 | i.tm.operand_types[0].bitfield.instance = InstanceNone; |
3528c362 | 7534 | i.tm.operand_types[0].bitfield.class = RegSIMD; |
c0f3af97 L |
7535 | goto duplicate; |
7536 | } | |
e2ec9d29 | 7537 | else |
c0f3af97 L |
7538 | { |
7539 | /* We remove the first xmm0 and keep the number of | |
7540 | operands unchanged, which in fact duplicates the | |
7541 | destination. */ | |
7542 | for (j = 1; j < i.operands; j++) | |
7543 | { | |
7544 | i.op[j - 1] = i.op[j]; | |
7545 | i.types[j - 1] = i.types[j]; | |
7546 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; | |
8dc0818e | 7547 | i.flags[j - 1] = i.flags[j]; |
c0f3af97 L |
7548 | } |
7549 | } | |
7550 | } | |
7551 | else if (i.tm.opcode_modifier.implicit1stxmm0) | |
7ab9ffdd | 7552 | { |
91d6fa6a | 7553 | gas_assert ((MAX_OPERANDS - 1) > dupl |
8cd7925b L |
7554 | && (i.tm.opcode_modifier.vexsources |
7555 | == VEX3SOURCES)); | |
c0f3af97 L |
7556 | |
7557 | /* Add the implicit xmm0 for instructions with VEX prefix | |
7558 | and 3 sources. */ | |
7559 | for (j = i.operands; j > 0; j--) | |
7560 | { | |
7561 | i.op[j] = i.op[j - 1]; | |
7562 | i.types[j] = i.types[j - 1]; | |
7563 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
8dc0818e | 7564 | i.flags[j] = i.flags[j - 1]; |
c0f3af97 L |
7565 | } |
7566 | i.op[0].regs | |
7567 | = (const reg_entry *) hash_find (reg_hash, "xmm0"); | |
7ab9ffdd | 7568 | i.types[0] = regxmm; |
c0f3af97 L |
7569 | i.tm.operand_types[0] = regxmm; |
7570 | ||
7571 | i.operands += 2; | |
7572 | i.reg_operands += 2; | |
7573 | i.tm.operands += 2; | |
7574 | ||
91d6fa6a | 7575 | dupl++; |
c0f3af97 | 7576 | dest++; |
91d6fa6a NC |
7577 | i.op[dupl] = i.op[dest]; |
7578 | i.types[dupl] = i.types[dest]; | |
7579 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 7580 | i.flags[dupl] = i.flags[dest]; |
e2ec9d29 | 7581 | } |
c0f3af97 L |
7582 | else |
7583 | { | |
dc1e8a47 | 7584 | duplicate: |
c0f3af97 L |
7585 | i.operands++; |
7586 | i.reg_operands++; | |
7587 | i.tm.operands++; | |
7588 | ||
91d6fa6a NC |
7589 | i.op[dupl] = i.op[dest]; |
7590 | i.types[dupl] = i.types[dest]; | |
7591 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 7592 | i.flags[dupl] = i.flags[dest]; |
c0f3af97 L |
7593 | } |
7594 | ||
7595 | if (i.tm.opcode_modifier.immext) | |
7596 | process_immext (); | |
7597 | } | |
75e5731b | 7598 | else if (i.tm.operand_types[0].bitfield.instance == Accum |
1b54b8d7 | 7599 | && i.tm.operand_types[0].bitfield.xmmword) |
c0f3af97 L |
7600 | { |
7601 | unsigned int j; | |
7602 | ||
9fcfb3d7 L |
7603 | for (j = 1; j < i.operands; j++) |
7604 | { | |
7605 | i.op[j - 1] = i.op[j]; | |
7606 | i.types[j - 1] = i.types[j]; | |
7607 | ||
7608 | /* We need to adjust fields in i.tm since they are used by | |
7609 | build_modrm_byte. */ | |
7610 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
8dc0818e JB |
7611 | |
7612 | i.flags[j - 1] = i.flags[j]; | |
9fcfb3d7 L |
7613 | } |
7614 | ||
e2ec9d29 L |
7615 | i.operands--; |
7616 | i.reg_operands--; | |
e2ec9d29 L |
7617 | i.tm.operands--; |
7618 | } | |
920d2ddc IT |
7619 | else if (i.tm.opcode_modifier.implicitquadgroup) |
7620 | { | |
a477a8c4 JB |
7621 | unsigned int regnum, first_reg_in_group, last_reg_in_group; |
7622 | ||
920d2ddc | 7623 | /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ |
3528c362 | 7624 | gas_assert (i.operands >= 2 && i.types[1].bitfield.class == RegSIMD); |
a477a8c4 JB |
7625 | regnum = register_number (i.op[1].regs); |
7626 | first_reg_in_group = regnum & ~3; | |
7627 | last_reg_in_group = first_reg_in_group + 3; | |
7628 | if (regnum != first_reg_in_group) | |
7629 | as_warn (_("source register `%s%s' implicitly denotes" | |
7630 | " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"), | |
7631 | register_prefix, i.op[1].regs->reg_name, | |
7632 | register_prefix, i.op[1].regs->reg_name, first_reg_in_group, | |
7633 | register_prefix, i.op[1].regs->reg_name, last_reg_in_group, | |
7634 | i.tm.name); | |
7635 | } | |
e2ec9d29 L |
7636 | else if (i.tm.opcode_modifier.regkludge) |
7637 | { | |
7638 | /* The imul $imm, %reg instruction is converted into | |
7639 | imul $imm, %reg, %reg, and the clr %reg instruction | |
7640 | is converted into xor %reg, %reg. */ | |
7641 | ||
7642 | unsigned int first_reg_op; | |
7643 | ||
7644 | if (operand_type_check (i.types[0], reg)) | |
7645 | first_reg_op = 0; | |
7646 | else | |
7647 | first_reg_op = 1; | |
7648 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 7649 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 7650 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
7651 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
7652 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
7653 | i.operands++; | |
7654 | i.reg_operands++; | |
29b0f896 AM |
7655 | } |
7656 | ||
85b80b0f | 7657 | if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
7658 | { |
7659 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
7660 | must be put into the modrm byte). Now, we make the modrm and |
7661 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
7662 | |
7663 | default_seg = build_modrm_byte (); | |
7664 | } | |
00cee14f | 7665 | else if (i.types[0].bitfield.class == SReg) |
85b80b0f JB |
7666 | { |
7667 | if (flag_code != CODE_64BIT | |
7668 | ? i.tm.base_opcode == POP_SEG_SHORT | |
7669 | && i.op[0].regs->reg_num == 1 | |
7670 | : (i.tm.base_opcode | 1) == POP_SEG386_SHORT | |
7671 | && i.op[0].regs->reg_num < 4) | |
7672 | { | |
7673 | as_bad (_("you can't `%s %s%s'"), | |
7674 | i.tm.name, register_prefix, i.op[0].regs->reg_name); | |
7675 | return 0; | |
7676 | } | |
7677 | if ( i.op[0].regs->reg_num > 3 && i.tm.opcode_length == 1 ) | |
7678 | { | |
7679 | i.tm.base_opcode ^= POP_SEG_SHORT ^ POP_SEG386_SHORT; | |
7680 | i.tm.opcode_length = 2; | |
7681 | } | |
7682 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); | |
7683 | } | |
8a2ed489 | 7684 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
29b0f896 AM |
7685 | { |
7686 | default_seg = &ds; | |
7687 | } | |
40fb9820 | 7688 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
7689 | { |
7690 | /* For the string instructions that allow a segment override | |
7691 | on one of their operands, the default segment is ds. */ | |
7692 | default_seg = &ds; | |
7693 | } | |
50128d0c | 7694 | else if (i.short_form) |
85b80b0f JB |
7695 | { |
7696 | /* The register or float register operand is in operand | |
7697 | 0 or 1. */ | |
bab6aec1 | 7698 | unsigned int op = i.tm.operand_types[0].bitfield.class != Reg; |
85b80b0f JB |
7699 | |
7700 | /* Register goes in low 3 bits of opcode. */ | |
7701 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
7702 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7703 | i.rex |= REX_B; | |
7704 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) | |
7705 | { | |
7706 | /* Warn about some common errors, but press on regardless. | |
7707 | The first case can be generated by gcc (<= 2.8.1). */ | |
7708 | if (i.operands == 2) | |
7709 | { | |
7710 | /* Reversed arguments on faddp, fsubp, etc. */ | |
7711 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, | |
7712 | register_prefix, i.op[!intel_syntax].regs->reg_name, | |
7713 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
7714 | } | |
7715 | else | |
7716 | { | |
7717 | /* Extraneous `l' suffix on fp insn. */ | |
7718 | as_warn (_("translating to `%s %s%s'"), i.tm.name, | |
7719 | register_prefix, i.op[0].regs->reg_name); | |
7720 | } | |
7721 | } | |
7722 | } | |
29b0f896 | 7723 | |
514a8bb0 | 7724 | if ((i.seg[0] || i.prefix[SEG_PREFIX]) |
514a8bb0 JB |
7725 | && i.tm.base_opcode == 0x8d /* lea */ |
7726 | && !is_any_vex_encoding(&i.tm)) | |
92334ad2 JB |
7727 | { |
7728 | if (!quiet_warnings) | |
7729 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); | |
7730 | if (optimize) | |
7731 | { | |
7732 | i.seg[0] = NULL; | |
7733 | i.prefix[SEG_PREFIX] = 0; | |
7734 | } | |
7735 | } | |
52271982 AM |
7736 | |
7737 | /* If a segment was explicitly specified, and the specified segment | |
b6773884 JB |
7738 | is neither the default nor the one already recorded from a prefix, |
7739 | use an opcode prefix to select it. If we never figured out what | |
7740 | the default segment is, then default_seg will be zero at this | |
7741 | point, and the specified segment prefix will always be used. */ | |
7742 | if (i.seg[0] | |
7743 | && i.seg[0] != default_seg | |
7744 | && i.seg[0]->seg_prefix != i.prefix[SEG_PREFIX]) | |
29b0f896 AM |
7745 | { |
7746 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
7747 | return 0; | |
7748 | } | |
7749 | return 1; | |
7750 | } | |
7751 | ||
a5aeccd9 JB |
7752 | static INLINE void set_rex_vrex (const reg_entry *r, unsigned int rex_bit, |
7753 | bfd_boolean do_sse2avx) | |
7754 | { | |
7755 | if (r->reg_flags & RegRex) | |
7756 | { | |
7757 | if (i.rex & rex_bit) | |
7758 | as_bad (_("same type of prefix used twice")); | |
7759 | i.rex |= rex_bit; | |
7760 | } | |
7761 | else if (do_sse2avx && (i.rex & rex_bit) && i.vex.register_specifier) | |
7762 | { | |
7763 | gas_assert (i.vex.register_specifier == r); | |
7764 | i.vex.register_specifier += 8; | |
7765 | } | |
7766 | ||
7767 | if (r->reg_flags & RegVRex) | |
7768 | i.vrex |= rex_bit; | |
7769 | } | |
7770 | ||
29b0f896 | 7771 | static const seg_entry * |
e3bb37b5 | 7772 | build_modrm_byte (void) |
29b0f896 AM |
7773 | { |
7774 | const seg_entry *default_seg = 0; | |
c0f3af97 | 7775 | unsigned int source, dest; |
8cd7925b | 7776 | int vex_3_sources; |
c0f3af97 | 7777 | |
8cd7925b | 7778 | vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; |
c0f3af97 L |
7779 | if (vex_3_sources) |
7780 | { | |
91d6fa6a | 7781 | unsigned int nds, reg_slot; |
4c2c6516 | 7782 | expressionS *exp; |
c0f3af97 | 7783 | |
6b8d3588 | 7784 | dest = i.operands - 1; |
c0f3af97 | 7785 | nds = dest - 1; |
922d8de8 | 7786 | |
a683cc34 | 7787 | /* There are 2 kinds of instructions: |
bed3d976 | 7788 | 1. 5 operands: 4 register operands or 3 register operands |
9d3bf266 | 7789 | plus 1 memory operand plus one Imm4 operand, VexXDS, and |
bed3d976 | 7790 | VexW0 or VexW1. The destination must be either XMM, YMM or |
43234a1e | 7791 | ZMM register. |
bed3d976 | 7792 | 2. 4 operands: 4 register operands or 3 register operands |
2f1bada2 | 7793 | plus 1 memory operand, with VexXDS. */ |
922d8de8 | 7794 | gas_assert ((i.reg_operands == 4 |
bed3d976 JB |
7795 | || (i.reg_operands == 3 && i.mem_operands == 1)) |
7796 | && i.tm.opcode_modifier.vexvvvv == VEXXDS | |
dcd7e323 | 7797 | && i.tm.opcode_modifier.vexw |
3528c362 | 7798 | && i.tm.operand_types[dest].bitfield.class == RegSIMD); |
a683cc34 | 7799 | |
48db9223 JB |
7800 | /* If VexW1 is set, the first non-immediate operand is the source and |
7801 | the second non-immediate one is encoded in the immediate operand. */ | |
7802 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
7803 | { | |
7804 | source = i.imm_operands; | |
7805 | reg_slot = i.imm_operands + 1; | |
7806 | } | |
7807 | else | |
7808 | { | |
7809 | source = i.imm_operands + 1; | |
7810 | reg_slot = i.imm_operands; | |
7811 | } | |
7812 | ||
a683cc34 | 7813 | if (i.imm_operands == 0) |
bed3d976 JB |
7814 | { |
7815 | /* When there is no immediate operand, generate an 8bit | |
7816 | immediate operand to encode the first operand. */ | |
7817 | exp = &im_expressions[i.imm_operands++]; | |
7818 | i.op[i.operands].imms = exp; | |
7819 | i.types[i.operands] = imm8; | |
7820 | i.operands++; | |
7821 | ||
3528c362 | 7822 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); |
bed3d976 JB |
7823 | exp->X_op = O_constant; |
7824 | exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; | |
43234a1e L |
7825 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
7826 | } | |
922d8de8 | 7827 | else |
bed3d976 | 7828 | { |
9d3bf266 JB |
7829 | gas_assert (i.imm_operands == 1); |
7830 | gas_assert (fits_in_imm4 (i.op[0].imms->X_add_number)); | |
7831 | gas_assert (!i.tm.opcode_modifier.immext); | |
a683cc34 | 7832 | |
9d3bf266 JB |
7833 | /* Turn on Imm8 again so that output_imm will generate it. */ |
7834 | i.types[0].bitfield.imm8 = 1; | |
bed3d976 | 7835 | |
3528c362 | 7836 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); |
9d3bf266 | 7837 | i.op[0].imms->X_add_number |
bed3d976 | 7838 | |= register_number (i.op[reg_slot].regs) << 4; |
43234a1e | 7839 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
bed3d976 | 7840 | } |
a683cc34 | 7841 | |
3528c362 | 7842 | gas_assert (i.tm.operand_types[nds].bitfield.class == RegSIMD); |
dae39acc | 7843 | i.vex.register_specifier = i.op[nds].regs; |
c0f3af97 L |
7844 | } |
7845 | else | |
7846 | source = dest = 0; | |
29b0f896 AM |
7847 | |
7848 | /* i.reg_operands MUST be the number of real register operands; | |
c0f3af97 L |
7849 | implicit registers do not count. If there are 3 register |
7850 | operands, it must be a instruction with VexNDS. For a | |
7851 | instruction with VexNDD, the destination register is encoded | |
7852 | in VEX prefix. If there are 4 register operands, it must be | |
7853 | a instruction with VEX prefix and 3 sources. */ | |
7ab9ffdd L |
7854 | if (i.mem_operands == 0 |
7855 | && ((i.reg_operands == 2 | |
2426c15f | 7856 | && i.tm.opcode_modifier.vexvvvv <= VEXXDS) |
7ab9ffdd | 7857 | || (i.reg_operands == 3 |
2426c15f | 7858 | && i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd | 7859 | || (i.reg_operands == 4 && vex_3_sources))) |
29b0f896 | 7860 | { |
cab737b9 L |
7861 | switch (i.operands) |
7862 | { | |
7863 | case 2: | |
7864 | source = 0; | |
7865 | break; | |
7866 | case 3: | |
c81128dc L |
7867 | /* When there are 3 operands, one of them may be immediate, |
7868 | which may be the first or the last operand. Otherwise, | |
c0f3af97 L |
7869 | the first operand must be shift count register (cl) or it |
7870 | is an instruction with VexNDS. */ | |
9c2799c2 | 7871 | gas_assert (i.imm_operands == 1 |
7ab9ffdd | 7872 | || (i.imm_operands == 0 |
2426c15f | 7873 | && (i.tm.opcode_modifier.vexvvvv == VEXXDS |
75e5731b JB |
7874 | || (i.types[0].bitfield.instance == RegC |
7875 | && i.types[0].bitfield.byte)))); | |
40fb9820 | 7876 | if (operand_type_check (i.types[0], imm) |
75e5731b JB |
7877 | || (i.types[0].bitfield.instance == RegC |
7878 | && i.types[0].bitfield.byte)) | |
40fb9820 L |
7879 | source = 1; |
7880 | else | |
7881 | source = 0; | |
cab737b9 L |
7882 | break; |
7883 | case 4: | |
368d64cc L |
7884 | /* When there are 4 operands, the first two must be 8bit |
7885 | immediate operands. The source operand will be the 3rd | |
c0f3af97 L |
7886 | one. |
7887 | ||
7888 | For instructions with VexNDS, if the first operand | |
7889 | an imm8, the source operand is the 2nd one. If the last | |
7890 | operand is imm8, the source operand is the first one. */ | |
9c2799c2 | 7891 | gas_assert ((i.imm_operands == 2 |
7ab9ffdd L |
7892 | && i.types[0].bitfield.imm8 |
7893 | && i.types[1].bitfield.imm8) | |
2426c15f | 7894 | || (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd L |
7895 | && i.imm_operands == 1 |
7896 | && (i.types[0].bitfield.imm8 | |
43234a1e L |
7897 | || i.types[i.operands - 1].bitfield.imm8 |
7898 | || i.rounding))); | |
9f2670f2 L |
7899 | if (i.imm_operands == 2) |
7900 | source = 2; | |
7901 | else | |
c0f3af97 L |
7902 | { |
7903 | if (i.types[0].bitfield.imm8) | |
7904 | source = 1; | |
7905 | else | |
7906 | source = 0; | |
7907 | } | |
c0f3af97 L |
7908 | break; |
7909 | case 5: | |
e771e7c9 | 7910 | if (is_evex_encoding (&i.tm)) |
43234a1e L |
7911 | { |
7912 | /* For EVEX instructions, when there are 5 operands, the | |
7913 | first one must be immediate operand. If the second one | |
7914 | is immediate operand, the source operand is the 3th | |
7915 | one. If the last one is immediate operand, the source | |
7916 | operand is the 2nd one. */ | |
7917 | gas_assert (i.imm_operands == 2 | |
7918 | && i.tm.opcode_modifier.sae | |
7919 | && operand_type_check (i.types[0], imm)); | |
7920 | if (operand_type_check (i.types[1], imm)) | |
7921 | source = 2; | |
7922 | else if (operand_type_check (i.types[4], imm)) | |
7923 | source = 1; | |
7924 | else | |
7925 | abort (); | |
7926 | } | |
cab737b9 L |
7927 | break; |
7928 | default: | |
7929 | abort (); | |
7930 | } | |
7931 | ||
c0f3af97 L |
7932 | if (!vex_3_sources) |
7933 | { | |
7934 | dest = source + 1; | |
7935 | ||
43234a1e L |
7936 | /* RC/SAE operand could be between DEST and SRC. That happens |
7937 | when one operand is GPR and the other one is XMM/YMM/ZMM | |
7938 | register. */ | |
7939 | if (i.rounding && i.rounding->operand == (int) dest) | |
7940 | dest++; | |
7941 | ||
2426c15f | 7942 | if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
c0f3af97 | 7943 | { |
43234a1e | 7944 | /* For instructions with VexNDS, the register-only source |
c5d0745b | 7945 | operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask |
dfd69174 | 7946 | register. It is encoded in VEX prefix. */ |
f12dc422 L |
7947 | |
7948 | i386_operand_type op; | |
7949 | unsigned int vvvv; | |
7950 | ||
c2ecccb3 L |
7951 | /* Swap two source operands if needed. */ |
7952 | if (i.tm.opcode_modifier.swapsources) | |
f12dc422 L |
7953 | { |
7954 | vvvv = source; | |
7955 | source = dest; | |
7956 | } | |
7957 | else | |
7958 | vvvv = dest; | |
7959 | ||
7960 | op = i.tm.operand_types[vvvv]; | |
c0f3af97 | 7961 | if ((dest + 1) >= i.operands |
bab6aec1 | 7962 | || ((op.bitfield.class != Reg |
dc821c5f | 7963 | || (!op.bitfield.dword && !op.bitfield.qword)) |
3528c362 | 7964 | && op.bitfield.class != RegSIMD |
43234a1e | 7965 | && !operand_type_equal (&op, ®mask))) |
c0f3af97 | 7966 | abort (); |
f12dc422 | 7967 | i.vex.register_specifier = i.op[vvvv].regs; |
c0f3af97 L |
7968 | dest++; |
7969 | } | |
7970 | } | |
29b0f896 AM |
7971 | |
7972 | i.rm.mode = 3; | |
dfd69174 JB |
7973 | /* One of the register operands will be encoded in the i.rm.reg |
7974 | field, the other in the combined i.rm.mode and i.rm.regmem | |
29b0f896 AM |
7975 | fields. If no form of this instruction supports a memory |
7976 | destination operand, then we assume the source operand may | |
7977 | sometimes be a memory operand and so we need to store the | |
7978 | destination in the i.rm.reg field. */ | |
dfd69174 | 7979 | if (!i.tm.opcode_modifier.regmem |
40fb9820 | 7980 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) |
29b0f896 AM |
7981 | { |
7982 | i.rm.reg = i.op[dest].regs->reg_num; | |
7983 | i.rm.regmem = i.op[source].regs->reg_num; | |
a5aeccd9 JB |
7984 | set_rex_vrex (i.op[dest].regs, REX_R, i.tm.opcode_modifier.sse2avx); |
7985 | set_rex_vrex (i.op[source].regs, REX_B, FALSE); | |
29b0f896 AM |
7986 | } |
7987 | else | |
7988 | { | |
7989 | i.rm.reg = i.op[source].regs->reg_num; | |
7990 | i.rm.regmem = i.op[dest].regs->reg_num; | |
a5aeccd9 JB |
7991 | set_rex_vrex (i.op[dest].regs, REX_B, i.tm.opcode_modifier.sse2avx); |
7992 | set_rex_vrex (i.op[source].regs, REX_R, FALSE); | |
29b0f896 | 7993 | } |
e0c7f900 | 7994 | if (flag_code != CODE_64BIT && (i.rex & REX_R)) |
c4a530c5 | 7995 | { |
4a5c67ed | 7996 | if (i.types[!i.tm.opcode_modifier.regmem].bitfield.class != RegCR) |
c4a530c5 | 7997 | abort (); |
e0c7f900 | 7998 | i.rex &= ~REX_R; |
c4a530c5 JB |
7999 | add_prefix (LOCK_PREFIX_OPCODE); |
8000 | } | |
29b0f896 AM |
8001 | } |
8002 | else | |
8003 | { /* If it's not 2 reg operands... */ | |
c0f3af97 L |
8004 | unsigned int mem; |
8005 | ||
29b0f896 AM |
8006 | if (i.mem_operands) |
8007 | { | |
8008 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 8009 | unsigned int op; |
4eed87de | 8010 | |
7ab9ffdd | 8011 | for (op = 0; op < i.operands; op++) |
8dc0818e | 8012 | if (i.flags[op] & Operand_Mem) |
7ab9ffdd | 8013 | break; |
7ab9ffdd | 8014 | gas_assert (op < i.operands); |
29b0f896 | 8015 | |
63112cd6 | 8016 | if (i.tm.opcode_modifier.sib) |
6c30d220 | 8017 | { |
260cd341 LC |
8018 | /* The index register of VSIB shouldn't be RegIZ. */ |
8019 | if (i.tm.opcode_modifier.sib != SIBMEM | |
8020 | && i.index_reg->reg_num == RegIZ) | |
6c30d220 L |
8021 | abort (); |
8022 | ||
8023 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
8024 | if (!i.base_reg) | |
8025 | { | |
8026 | i.sib.base = NO_BASE_REGISTER; | |
8027 | i.sib.scale = i.log2_scale_factor; | |
8028 | i.types[op].bitfield.disp8 = 0; | |
8029 | i.types[op].bitfield.disp16 = 0; | |
8030 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 8031 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
6c30d220 L |
8032 | { |
8033 | /* Must be 32 bit */ | |
8034 | i.types[op].bitfield.disp32 = 1; | |
8035 | i.types[op].bitfield.disp32s = 0; | |
8036 | } | |
8037 | else | |
8038 | { | |
8039 | i.types[op].bitfield.disp32 = 0; | |
8040 | i.types[op].bitfield.disp32s = 1; | |
8041 | } | |
8042 | } | |
260cd341 LC |
8043 | |
8044 | /* Since the mandatory SIB always has index register, so | |
8045 | the code logic remains unchanged. The non-mandatory SIB | |
8046 | without index register is allowed and will be handled | |
8047 | later. */ | |
8048 | if (i.index_reg) | |
8049 | { | |
8050 | if (i.index_reg->reg_num == RegIZ) | |
8051 | i.sib.index = NO_INDEX_REGISTER; | |
8052 | else | |
8053 | i.sib.index = i.index_reg->reg_num; | |
8054 | set_rex_vrex (i.index_reg, REX_X, FALSE); | |
8055 | } | |
6c30d220 L |
8056 | } |
8057 | ||
29b0f896 AM |
8058 | default_seg = &ds; |
8059 | ||
8060 | if (i.base_reg == 0) | |
8061 | { | |
8062 | i.rm.mode = 0; | |
8063 | if (!i.disp_operands) | |
9bb129e8 | 8064 | fake_zero_displacement = 1; |
29b0f896 AM |
8065 | if (i.index_reg == 0) |
8066 | { | |
73053c1f JB |
8067 | i386_operand_type newdisp; |
8068 | ||
260cd341 LC |
8069 | /* Both check for VSIB and mandatory non-vector SIB. */ |
8070 | gas_assert (!i.tm.opcode_modifier.sib | |
8071 | || i.tm.opcode_modifier.sib == SIBMEM); | |
29b0f896 | 8072 | /* Operand is just <disp> */ |
20f0a1fc | 8073 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
8074 | { |
8075 | /* 64bit mode overwrites the 32bit absolute | |
8076 | addressing by RIP relative addressing and | |
8077 | absolute addressing is encoded by one of the | |
8078 | redundant SIB forms. */ | |
8079 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
8080 | i.sib.base = NO_BASE_REGISTER; | |
8081 | i.sib.index = NO_INDEX_REGISTER; | |
73053c1f | 8082 | newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32); |
20f0a1fc | 8083 | } |
fc225355 L |
8084 | else if ((flag_code == CODE_16BIT) |
8085 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
8086 | { |
8087 | i.rm.regmem = NO_BASE_REGISTER_16; | |
73053c1f | 8088 | newdisp = disp16; |
20f0a1fc NC |
8089 | } |
8090 | else | |
8091 | { | |
8092 | i.rm.regmem = NO_BASE_REGISTER; | |
73053c1f | 8093 | newdisp = disp32; |
29b0f896 | 8094 | } |
73053c1f JB |
8095 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
8096 | i.types[op] = operand_type_or (i.types[op], newdisp); | |
29b0f896 | 8097 | } |
63112cd6 | 8098 | else if (!i.tm.opcode_modifier.sib) |
29b0f896 | 8099 | { |
6c30d220 | 8100 | /* !i.base_reg && i.index_reg */ |
e968fc9b | 8101 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
8102 | i.sib.index = NO_INDEX_REGISTER; |
8103 | else | |
8104 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
8105 | i.sib.base = NO_BASE_REGISTER; |
8106 | i.sib.scale = i.log2_scale_factor; | |
8107 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
40fb9820 L |
8108 | i.types[op].bitfield.disp8 = 0; |
8109 | i.types[op].bitfield.disp16 = 0; | |
8110 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 8111 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
40fb9820 L |
8112 | { |
8113 | /* Must be 32 bit */ | |
8114 | i.types[op].bitfield.disp32 = 1; | |
8115 | i.types[op].bitfield.disp32s = 0; | |
8116 | } | |
29b0f896 | 8117 | else |
40fb9820 L |
8118 | { |
8119 | i.types[op].bitfield.disp32 = 0; | |
8120 | i.types[op].bitfield.disp32s = 1; | |
8121 | } | |
29b0f896 | 8122 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 8123 | i.rex |= REX_X; |
29b0f896 AM |
8124 | } |
8125 | } | |
8126 | /* RIP addressing for 64bit mode. */ | |
e968fc9b | 8127 | else if (i.base_reg->reg_num == RegIP) |
29b0f896 | 8128 | { |
63112cd6 | 8129 | gas_assert (!i.tm.opcode_modifier.sib); |
29b0f896 | 8130 | i.rm.regmem = NO_BASE_REGISTER; |
40fb9820 L |
8131 | i.types[op].bitfield.disp8 = 0; |
8132 | i.types[op].bitfield.disp16 = 0; | |
8133 | i.types[op].bitfield.disp32 = 0; | |
8134 | i.types[op].bitfield.disp32s = 1; | |
8135 | i.types[op].bitfield.disp64 = 0; | |
71903a11 | 8136 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
8137 | if (! i.disp_operands) |
8138 | fake_zero_displacement = 1; | |
29b0f896 | 8139 | } |
dc821c5f | 8140 | else if (i.base_reg->reg_type.bitfield.word) |
29b0f896 | 8141 | { |
63112cd6 | 8142 | gas_assert (!i.tm.opcode_modifier.sib); |
29b0f896 AM |
8143 | switch (i.base_reg->reg_num) |
8144 | { | |
8145 | case 3: /* (%bx) */ | |
8146 | if (i.index_reg == 0) | |
8147 | i.rm.regmem = 7; | |
8148 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
8149 | i.rm.regmem = i.index_reg->reg_num - 6; | |
8150 | break; | |
8151 | case 5: /* (%bp) */ | |
8152 | default_seg = &ss; | |
8153 | if (i.index_reg == 0) | |
8154 | { | |
8155 | i.rm.regmem = 6; | |
40fb9820 | 8156 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
8157 | { |
8158 | /* fake (%bp) into 0(%bp) */ | |
41eb8e88 | 8159 | if (i.disp_encoding == disp_encoding_16bit) |
1a02d6b0 L |
8160 | i.types[op].bitfield.disp16 = 1; |
8161 | else | |
8162 | i.types[op].bitfield.disp8 = 1; | |
252b5132 | 8163 | fake_zero_displacement = 1; |
29b0f896 AM |
8164 | } |
8165 | } | |
8166 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
8167 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
8168 | break; | |
8169 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
8170 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
8171 | } | |
41eb8e88 L |
8172 | if (!fake_zero_displacement |
8173 | && !i.disp_operands | |
8174 | && i.disp_encoding) | |
8175 | { | |
8176 | fake_zero_displacement = 1; | |
8177 | if (i.disp_encoding == disp_encoding_8bit) | |
8178 | i.types[op].bitfield.disp8 = 1; | |
8179 | else | |
8180 | i.types[op].bitfield.disp16 = 1; | |
8181 | } | |
29b0f896 AM |
8182 | i.rm.mode = mode_from_disp_size (i.types[op]); |
8183 | } | |
8184 | else /* i.base_reg and 32/64 bit mode */ | |
8185 | { | |
8186 | if (flag_code == CODE_64BIT | |
40fb9820 L |
8187 | && operand_type_check (i.types[op], disp)) |
8188 | { | |
73053c1f JB |
8189 | i.types[op].bitfield.disp16 = 0; |
8190 | i.types[op].bitfield.disp64 = 0; | |
40fb9820 | 8191 | if (i.prefix[ADDR_PREFIX] == 0) |
73053c1f JB |
8192 | { |
8193 | i.types[op].bitfield.disp32 = 0; | |
8194 | i.types[op].bitfield.disp32s = 1; | |
8195 | } | |
40fb9820 | 8196 | else |
73053c1f JB |
8197 | { |
8198 | i.types[op].bitfield.disp32 = 1; | |
8199 | i.types[op].bitfield.disp32s = 0; | |
8200 | } | |
40fb9820 | 8201 | } |
20f0a1fc | 8202 | |
63112cd6 | 8203 | if (!i.tm.opcode_modifier.sib) |
6c30d220 | 8204 | i.rm.regmem = i.base_reg->reg_num; |
29b0f896 | 8205 | if ((i.base_reg->reg_flags & RegRex) != 0) |
161a04f6 | 8206 | i.rex |= REX_B; |
29b0f896 AM |
8207 | i.sib.base = i.base_reg->reg_num; |
8208 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
8209 | complications. */ | |
848930b2 JB |
8210 | if (!(i.base_reg->reg_flags & RegRex) |
8211 | && (i.base_reg->reg_num == EBP_REG_NUM | |
8212 | || i.base_reg->reg_num == ESP_REG_NUM)) | |
29b0f896 | 8213 | default_seg = &ss; |
848930b2 | 8214 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
29b0f896 | 8215 | { |
848930b2 | 8216 | fake_zero_displacement = 1; |
1a02d6b0 L |
8217 | if (i.disp_encoding == disp_encoding_32bit) |
8218 | i.types[op].bitfield.disp32 = 1; | |
8219 | else | |
8220 | i.types[op].bitfield.disp8 = 1; | |
29b0f896 AM |
8221 | } |
8222 | i.sib.scale = i.log2_scale_factor; | |
8223 | if (i.index_reg == 0) | |
8224 | { | |
260cd341 LC |
8225 | /* Only check for VSIB. */ |
8226 | gas_assert (i.tm.opcode_modifier.sib != VECSIB128 | |
8227 | && i.tm.opcode_modifier.sib != VECSIB256 | |
8228 | && i.tm.opcode_modifier.sib != VECSIB512); | |
8229 | ||
29b0f896 AM |
8230 | /* <disp>(%esp) becomes two byte modrm with no index |
8231 | register. We've already stored the code for esp | |
8232 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
8233 | Any base register besides %esp will not use the | |
8234 | extra modrm byte. */ | |
8235 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 | 8236 | } |
63112cd6 | 8237 | else if (!i.tm.opcode_modifier.sib) |
29b0f896 | 8238 | { |
e968fc9b | 8239 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
8240 | i.sib.index = NO_INDEX_REGISTER; |
8241 | else | |
8242 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
8243 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
8244 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 8245 | i.rex |= REX_X; |
29b0f896 | 8246 | } |
67a4f2b7 AO |
8247 | |
8248 | if (i.disp_operands | |
8249 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
8250 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
8251 | i.rm.mode = 0; | |
8252 | else | |
a501d77e L |
8253 | { |
8254 | if (!fake_zero_displacement | |
8255 | && !i.disp_operands | |
8256 | && i.disp_encoding) | |
8257 | { | |
8258 | fake_zero_displacement = 1; | |
8259 | if (i.disp_encoding == disp_encoding_8bit) | |
8260 | i.types[op].bitfield.disp8 = 1; | |
8261 | else | |
8262 | i.types[op].bitfield.disp32 = 1; | |
8263 | } | |
8264 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
8265 | } | |
29b0f896 | 8266 | } |
252b5132 | 8267 | |
29b0f896 AM |
8268 | if (fake_zero_displacement) |
8269 | { | |
8270 | /* Fakes a zero displacement assuming that i.types[op] | |
8271 | holds the correct displacement size. */ | |
8272 | expressionS *exp; | |
8273 | ||
9c2799c2 | 8274 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
8275 | exp = &disp_expressions[i.disp_operands++]; |
8276 | i.op[op].disps = exp; | |
8277 | exp->X_op = O_constant; | |
8278 | exp->X_add_number = 0; | |
8279 | exp->X_add_symbol = (symbolS *) 0; | |
8280 | exp->X_op_symbol = (symbolS *) 0; | |
8281 | } | |
c0f3af97 L |
8282 | |
8283 | mem = op; | |
29b0f896 | 8284 | } |
c0f3af97 L |
8285 | else |
8286 | mem = ~0; | |
252b5132 | 8287 | |
8c43a48b | 8288 | if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) |
5dd85c99 SP |
8289 | { |
8290 | if (operand_type_check (i.types[0], imm)) | |
8291 | i.vex.register_specifier = NULL; | |
8292 | else | |
8293 | { | |
8294 | /* VEX.vvvv encodes one of the sources when the first | |
8295 | operand is not an immediate. */ | |
1ef99a7b | 8296 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
8297 | i.vex.register_specifier = i.op[0].regs; |
8298 | else | |
8299 | i.vex.register_specifier = i.op[1].regs; | |
8300 | } | |
8301 | ||
8302 | /* Destination is a XMM register encoded in the ModRM.reg | |
8303 | and VEX.R bit. */ | |
8304 | i.rm.reg = i.op[2].regs->reg_num; | |
8305 | if ((i.op[2].regs->reg_flags & RegRex) != 0) | |
8306 | i.rex |= REX_R; | |
8307 | ||
8308 | /* ModRM.rm and VEX.B encodes the other source. */ | |
8309 | if (!i.mem_operands) | |
8310 | { | |
8311 | i.rm.mode = 3; | |
8312 | ||
1ef99a7b | 8313 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
8314 | i.rm.regmem = i.op[1].regs->reg_num; |
8315 | else | |
8316 | i.rm.regmem = i.op[0].regs->reg_num; | |
8317 | ||
8318 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
8319 | i.rex |= REX_B; | |
8320 | } | |
8321 | } | |
2426c15f | 8322 | else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) |
f88c9eb0 SP |
8323 | { |
8324 | i.vex.register_specifier = i.op[2].regs; | |
8325 | if (!i.mem_operands) | |
8326 | { | |
8327 | i.rm.mode = 3; | |
8328 | i.rm.regmem = i.op[1].regs->reg_num; | |
8329 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
8330 | i.rex |= REX_B; | |
8331 | } | |
8332 | } | |
29b0f896 AM |
8333 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
8334 | (if any) based on i.tm.extension_opcode. Again, we must be | |
8335 | careful to make sure that segment/control/debug/test/MMX | |
8336 | registers are coded into the i.rm.reg field. */ | |
f88c9eb0 | 8337 | else if (i.reg_operands) |
29b0f896 | 8338 | { |
99018f42 | 8339 | unsigned int op; |
7ab9ffdd L |
8340 | unsigned int vex_reg = ~0; |
8341 | ||
8342 | for (op = 0; op < i.operands; op++) | |
921eafea L |
8343 | if (i.types[op].bitfield.class == Reg |
8344 | || i.types[op].bitfield.class == RegBND | |
8345 | || i.types[op].bitfield.class == RegMask | |
8346 | || i.types[op].bitfield.class == SReg | |
8347 | || i.types[op].bitfield.class == RegCR | |
8348 | || i.types[op].bitfield.class == RegDR | |
8349 | || i.types[op].bitfield.class == RegTR | |
8350 | || i.types[op].bitfield.class == RegSIMD | |
8351 | || i.types[op].bitfield.class == RegMMX) | |
8352 | break; | |
c0209578 | 8353 | |
7ab9ffdd L |
8354 | if (vex_3_sources) |
8355 | op = dest; | |
2426c15f | 8356 | else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd L |
8357 | { |
8358 | /* For instructions with VexNDS, the register-only | |
8359 | source operand is encoded in VEX prefix. */ | |
8360 | gas_assert (mem != (unsigned int) ~0); | |
c0f3af97 | 8361 | |
7ab9ffdd | 8362 | if (op > mem) |
c0f3af97 | 8363 | { |
7ab9ffdd L |
8364 | vex_reg = op++; |
8365 | gas_assert (op < i.operands); | |
c0f3af97 L |
8366 | } |
8367 | else | |
c0f3af97 | 8368 | { |
f12dc422 L |
8369 | /* Check register-only source operand when two source |
8370 | operands are swapped. */ | |
8371 | if (!i.tm.operand_types[op].bitfield.baseindex | |
8372 | && i.tm.operand_types[op + 1].bitfield.baseindex) | |
8373 | { | |
8374 | vex_reg = op; | |
8375 | op += 2; | |
8376 | gas_assert (mem == (vex_reg + 1) | |
8377 | && op < i.operands); | |
8378 | } | |
8379 | else | |
8380 | { | |
8381 | vex_reg = op + 1; | |
8382 | gas_assert (vex_reg < i.operands); | |
8383 | } | |
c0f3af97 | 8384 | } |
7ab9ffdd | 8385 | } |
2426c15f | 8386 | else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) |
7ab9ffdd | 8387 | { |
f12dc422 | 8388 | /* For instructions with VexNDD, the register destination |
7ab9ffdd | 8389 | is encoded in VEX prefix. */ |
f12dc422 L |
8390 | if (i.mem_operands == 0) |
8391 | { | |
8392 | /* There is no memory operand. */ | |
8393 | gas_assert ((op + 2) == i.operands); | |
8394 | vex_reg = op + 1; | |
8395 | } | |
8396 | else | |
8d63c93e | 8397 | { |
ed438a93 JB |
8398 | /* There are only 2 non-immediate operands. */ |
8399 | gas_assert (op < i.imm_operands + 2 | |
8400 | && i.operands == i.imm_operands + 2); | |
8401 | vex_reg = i.imm_operands + 1; | |
f12dc422 | 8402 | } |
7ab9ffdd L |
8403 | } |
8404 | else | |
8405 | gas_assert (op < i.operands); | |
99018f42 | 8406 | |
7ab9ffdd L |
8407 | if (vex_reg != (unsigned int) ~0) |
8408 | { | |
f12dc422 | 8409 | i386_operand_type *type = &i.tm.operand_types[vex_reg]; |
7ab9ffdd | 8410 | |
bab6aec1 | 8411 | if ((type->bitfield.class != Reg |
dc821c5f | 8412 | || (!type->bitfield.dword && !type->bitfield.qword)) |
3528c362 | 8413 | && type->bitfield.class != RegSIMD |
43234a1e | 8414 | && !operand_type_equal (type, ®mask)) |
7ab9ffdd | 8415 | abort (); |
f88c9eb0 | 8416 | |
7ab9ffdd L |
8417 | i.vex.register_specifier = i.op[vex_reg].regs; |
8418 | } | |
8419 | ||
1b9f0c97 L |
8420 | /* Don't set OP operand twice. */ |
8421 | if (vex_reg != op) | |
7ab9ffdd | 8422 | { |
1b9f0c97 L |
8423 | /* If there is an extension opcode to put here, the |
8424 | register number must be put into the regmem field. */ | |
8425 | if (i.tm.extension_opcode != None) | |
8426 | { | |
8427 | i.rm.regmem = i.op[op].regs->reg_num; | |
a5aeccd9 JB |
8428 | set_rex_vrex (i.op[op].regs, REX_B, |
8429 | i.tm.opcode_modifier.sse2avx); | |
1b9f0c97 L |
8430 | } |
8431 | else | |
8432 | { | |
8433 | i.rm.reg = i.op[op].regs->reg_num; | |
a5aeccd9 JB |
8434 | set_rex_vrex (i.op[op].regs, REX_R, |
8435 | i.tm.opcode_modifier.sse2avx); | |
1b9f0c97 | 8436 | } |
7ab9ffdd | 8437 | } |
252b5132 | 8438 | |
29b0f896 AM |
8439 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
8440 | must set it to 3 to indicate this is a register operand | |
8441 | in the regmem field. */ | |
8442 | if (!i.mem_operands) | |
8443 | i.rm.mode = 3; | |
8444 | } | |
252b5132 | 8445 | |
29b0f896 | 8446 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
c1e679ec | 8447 | if (i.tm.extension_opcode != None) |
29b0f896 AM |
8448 | i.rm.reg = i.tm.extension_opcode; |
8449 | } | |
8450 | return default_seg; | |
8451 | } | |
252b5132 | 8452 | |
48ef937e JB |
8453 | static INLINE void |
8454 | frag_opcode_byte (unsigned char byte) | |
8455 | { | |
8456 | if (now_seg != absolute_section) | |
8457 | FRAG_APPEND_1_CHAR (byte); | |
8458 | else | |
8459 | ++abs_section_offset; | |
8460 | } | |
8461 | ||
376cd056 JB |
8462 | static unsigned int |
8463 | flip_code16 (unsigned int code16) | |
8464 | { | |
8465 | gas_assert (i.tm.operands == 1); | |
8466 | ||
8467 | return !(i.prefix[REX_PREFIX] & REX_W) | |
8468 | && (code16 ? i.tm.operand_types[0].bitfield.disp32 | |
8469 | || i.tm.operand_types[0].bitfield.disp32s | |
8470 | : i.tm.operand_types[0].bitfield.disp16) | |
8471 | ? CODE16 : 0; | |
8472 | } | |
8473 | ||
29b0f896 | 8474 | static void |
e3bb37b5 | 8475 | output_branch (void) |
29b0f896 AM |
8476 | { |
8477 | char *p; | |
f8a5c266 | 8478 | int size; |
29b0f896 AM |
8479 | int code16; |
8480 | int prefix; | |
8481 | relax_substateT subtype; | |
8482 | symbolS *sym; | |
8483 | offsetT off; | |
8484 | ||
48ef937e JB |
8485 | if (now_seg == absolute_section) |
8486 | { | |
8487 | as_bad (_("relaxable branches not supported in absolute section")); | |
8488 | return; | |
8489 | } | |
8490 | ||
f8a5c266 | 8491 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
a501d77e | 8492 | size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL; |
29b0f896 AM |
8493 | |
8494 | prefix = 0; | |
8495 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 8496 | { |
29b0f896 AM |
8497 | prefix = 1; |
8498 | i.prefixes -= 1; | |
376cd056 | 8499 | code16 ^= flip_code16(code16); |
252b5132 | 8500 | } |
29b0f896 AM |
8501 | /* Pentium4 branch hints. */ |
8502 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
8503 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 8504 | { |
29b0f896 AM |
8505 | prefix++; |
8506 | i.prefixes--; | |
8507 | } | |
8508 | if (i.prefix[REX_PREFIX] != 0) | |
8509 | { | |
8510 | prefix++; | |
8511 | i.prefixes--; | |
2f66722d AM |
8512 | } |
8513 | ||
7e8b059b L |
8514 | /* BND prefixed jump. */ |
8515 | if (i.prefix[BND_PREFIX] != 0) | |
8516 | { | |
6cb0a70e JB |
8517 | prefix++; |
8518 | i.prefixes--; | |
7e8b059b L |
8519 | } |
8520 | ||
f2810fe0 JB |
8521 | if (i.prefixes != 0) |
8522 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); | |
29b0f896 AM |
8523 | |
8524 | /* It's always a symbol; End frag & setup for relax. | |
8525 | Make sure there is enough room in this frag for the largest | |
8526 | instruction we may generate in md_convert_frag. This is 2 | |
8527 | bytes for the opcode and room for the prefix and largest | |
8528 | displacement. */ | |
8529 | frag_grow (prefix + 2 + 4); | |
8530 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
8531 | p = frag_more (prefix + 1); | |
8532 | if (i.prefix[DATA_PREFIX] != 0) | |
8533 | *p++ = DATA_PREFIX_OPCODE; | |
8534 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
8535 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
8536 | *p++ = i.prefix[SEG_PREFIX]; | |
6cb0a70e JB |
8537 | if (i.prefix[BND_PREFIX] != 0) |
8538 | *p++ = BND_PREFIX_OPCODE; | |
29b0f896 AM |
8539 | if (i.prefix[REX_PREFIX] != 0) |
8540 | *p++ = i.prefix[REX_PREFIX]; | |
8541 | *p = i.tm.base_opcode; | |
8542 | ||
8543 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
f8a5c266 | 8544 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
40fb9820 | 8545 | else if (cpu_arch_flags.bitfield.cpui386) |
f8a5c266 | 8546 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
29b0f896 | 8547 | else |
f8a5c266 | 8548 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
29b0f896 | 8549 | subtype |= code16; |
3e73aa7c | 8550 | |
29b0f896 AM |
8551 | sym = i.op[0].disps->X_add_symbol; |
8552 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 8553 | |
29b0f896 AM |
8554 | if (i.op[0].disps->X_op != O_constant |
8555 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 8556 | { |
29b0f896 AM |
8557 | /* Handle complex expressions. */ |
8558 | sym = make_expr_symbol (i.op[0].disps); | |
8559 | off = 0; | |
8560 | } | |
3e73aa7c | 8561 | |
29b0f896 AM |
8562 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
8563 | Pass reloc in fr_var. */ | |
d258b828 | 8564 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
29b0f896 | 8565 | } |
3e73aa7c | 8566 | |
bd7ab16b L |
8567 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8568 | /* Return TRUE iff PLT32 relocation should be used for branching to | |
8569 | symbol S. */ | |
8570 | ||
8571 | static bfd_boolean | |
8572 | need_plt32_p (symbolS *s) | |
8573 | { | |
8574 | /* PLT32 relocation is ELF only. */ | |
8575 | if (!IS_ELF) | |
8576 | return FALSE; | |
8577 | ||
a5def729 RO |
8578 | #ifdef TE_SOLARIS |
8579 | /* Don't emit PLT32 relocation on Solaris: neither native linker nor | |
8580 | krtld support it. */ | |
8581 | return FALSE; | |
8582 | #endif | |
8583 | ||
bd7ab16b L |
8584 | /* Since there is no need to prepare for PLT branch on x86-64, we |
8585 | can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can | |
8586 | be used as a marker for 32-bit PC-relative branches. */ | |
8587 | if (!object_64bit) | |
8588 | return FALSE; | |
8589 | ||
8590 | /* Weak or undefined symbol need PLT32 relocation. */ | |
8591 | if (S_IS_WEAK (s) || !S_IS_DEFINED (s)) | |
8592 | return TRUE; | |
8593 | ||
8594 | /* Non-global symbol doesn't need PLT32 relocation. */ | |
8595 | if (! S_IS_EXTERNAL (s)) | |
8596 | return FALSE; | |
8597 | ||
8598 | /* Other global symbols need PLT32 relocation. NB: Symbol with | |
8599 | non-default visibilities are treated as normal global symbol | |
8600 | so that PLT32 relocation can be used as a marker for 32-bit | |
8601 | PC-relative branches. It is useful for linker relaxation. */ | |
8602 | return TRUE; | |
8603 | } | |
8604 | #endif | |
8605 | ||
29b0f896 | 8606 | static void |
e3bb37b5 | 8607 | output_jump (void) |
29b0f896 AM |
8608 | { |
8609 | char *p; | |
8610 | int size; | |
3e02c1cc | 8611 | fixS *fixP; |
bd7ab16b | 8612 | bfd_reloc_code_real_type jump_reloc = i.reloc[0]; |
29b0f896 | 8613 | |
0cfa3eb3 | 8614 | if (i.tm.opcode_modifier.jump == JUMP_BYTE) |
29b0f896 AM |
8615 | { |
8616 | /* This is a loop or jecxz type instruction. */ | |
8617 | size = 1; | |
8618 | if (i.prefix[ADDR_PREFIX] != 0) | |
8619 | { | |
48ef937e | 8620 | frag_opcode_byte (ADDR_PREFIX_OPCODE); |
29b0f896 AM |
8621 | i.prefixes -= 1; |
8622 | } | |
8623 | /* Pentium4 branch hints. */ | |
8624 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
8625 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
8626 | { | |
48ef937e | 8627 | frag_opcode_byte (i.prefix[SEG_PREFIX]); |
29b0f896 | 8628 | i.prefixes--; |
3e73aa7c JH |
8629 | } |
8630 | } | |
29b0f896 AM |
8631 | else |
8632 | { | |
8633 | int code16; | |
3e73aa7c | 8634 | |
29b0f896 AM |
8635 | code16 = 0; |
8636 | if (flag_code == CODE_16BIT) | |
8637 | code16 = CODE16; | |
3e73aa7c | 8638 | |
29b0f896 AM |
8639 | if (i.prefix[DATA_PREFIX] != 0) |
8640 | { | |
48ef937e | 8641 | frag_opcode_byte (DATA_PREFIX_OPCODE); |
29b0f896 | 8642 | i.prefixes -= 1; |
376cd056 | 8643 | code16 ^= flip_code16(code16); |
29b0f896 | 8644 | } |
252b5132 | 8645 | |
29b0f896 AM |
8646 | size = 4; |
8647 | if (code16) | |
8648 | size = 2; | |
8649 | } | |
9fcc94b6 | 8650 | |
6cb0a70e JB |
8651 | /* BND prefixed jump. */ |
8652 | if (i.prefix[BND_PREFIX] != 0) | |
29b0f896 | 8653 | { |
48ef937e | 8654 | frag_opcode_byte (i.prefix[BND_PREFIX]); |
29b0f896 AM |
8655 | i.prefixes -= 1; |
8656 | } | |
252b5132 | 8657 | |
6cb0a70e | 8658 | if (i.prefix[REX_PREFIX] != 0) |
7e8b059b | 8659 | { |
48ef937e | 8660 | frag_opcode_byte (i.prefix[REX_PREFIX]); |
7e8b059b L |
8661 | i.prefixes -= 1; |
8662 | } | |
8663 | ||
f2810fe0 JB |
8664 | if (i.prefixes != 0) |
8665 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); | |
e0890092 | 8666 | |
48ef937e JB |
8667 | if (now_seg == absolute_section) |
8668 | { | |
8669 | abs_section_offset += i.tm.opcode_length + size; | |
8670 | return; | |
8671 | } | |
8672 | ||
42164a71 L |
8673 | p = frag_more (i.tm.opcode_length + size); |
8674 | switch (i.tm.opcode_length) | |
8675 | { | |
8676 | case 2: | |
8677 | *p++ = i.tm.base_opcode >> 8; | |
1a0670f3 | 8678 | /* Fall through. */ |
42164a71 L |
8679 | case 1: |
8680 | *p++ = i.tm.base_opcode; | |
8681 | break; | |
8682 | default: | |
8683 | abort (); | |
8684 | } | |
e0890092 | 8685 | |
bd7ab16b L |
8686 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8687 | if (size == 4 | |
8688 | && jump_reloc == NO_RELOC | |
8689 | && need_plt32_p (i.op[0].disps->X_add_symbol)) | |
8690 | jump_reloc = BFD_RELOC_X86_64_PLT32; | |
8691 | #endif | |
8692 | ||
8693 | jump_reloc = reloc (size, 1, 1, jump_reloc); | |
8694 | ||
3e02c1cc | 8695 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
bd7ab16b | 8696 | i.op[0].disps, 1, jump_reloc); |
3e02c1cc AM |
8697 | |
8698 | /* All jumps handled here are signed, but don't use a signed limit | |
8699 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
8700 | 4G and 64k respectively. */ | |
8701 | if (size == 1) | |
8702 | fixP->fx_signed = 1; | |
29b0f896 | 8703 | } |
e0890092 | 8704 | |
29b0f896 | 8705 | static void |
e3bb37b5 | 8706 | output_interseg_jump (void) |
29b0f896 AM |
8707 | { |
8708 | char *p; | |
8709 | int size; | |
8710 | int prefix; | |
8711 | int code16; | |
252b5132 | 8712 | |
29b0f896 AM |
8713 | code16 = 0; |
8714 | if (flag_code == CODE_16BIT) | |
8715 | code16 = CODE16; | |
a217f122 | 8716 | |
29b0f896 AM |
8717 | prefix = 0; |
8718 | if (i.prefix[DATA_PREFIX] != 0) | |
8719 | { | |
8720 | prefix = 1; | |
8721 | i.prefixes -= 1; | |
8722 | code16 ^= CODE16; | |
8723 | } | |
6cb0a70e JB |
8724 | |
8725 | gas_assert (!i.prefix[REX_PREFIX]); | |
252b5132 | 8726 | |
29b0f896 AM |
8727 | size = 4; |
8728 | if (code16) | |
8729 | size = 2; | |
252b5132 | 8730 | |
f2810fe0 JB |
8731 | if (i.prefixes != 0) |
8732 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); | |
252b5132 | 8733 | |
48ef937e JB |
8734 | if (now_seg == absolute_section) |
8735 | { | |
8736 | abs_section_offset += prefix + 1 + 2 + size; | |
8737 | return; | |
8738 | } | |
8739 | ||
29b0f896 AM |
8740 | /* 1 opcode; 2 segment; offset */ |
8741 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 8742 | |
29b0f896 AM |
8743 | if (i.prefix[DATA_PREFIX] != 0) |
8744 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 8745 | |
29b0f896 AM |
8746 | if (i.prefix[REX_PREFIX] != 0) |
8747 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 8748 | |
29b0f896 AM |
8749 | *p++ = i.tm.base_opcode; |
8750 | if (i.op[1].imms->X_op == O_constant) | |
8751 | { | |
8752 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 8753 | |
29b0f896 AM |
8754 | if (size == 2 |
8755 | && !fits_in_unsigned_word (n) | |
8756 | && !fits_in_signed_word (n)) | |
8757 | { | |
8758 | as_bad (_("16-bit jump out of range")); | |
8759 | return; | |
8760 | } | |
8761 | md_number_to_chars (p, n, size); | |
8762 | } | |
8763 | else | |
8764 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
d258b828 | 8765 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
29b0f896 AM |
8766 | if (i.op[0].imms->X_op != O_constant) |
8767 | as_bad (_("can't handle non absolute segment in `%s'"), | |
8768 | i.tm.name); | |
8769 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
8770 | } | |
a217f122 | 8771 | |
b4a3a7b4 L |
8772 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8773 | void | |
8774 | x86_cleanup (void) | |
8775 | { | |
8776 | char *p; | |
8777 | asection *seg = now_seg; | |
8778 | subsegT subseg = now_subseg; | |
8779 | asection *sec; | |
8780 | unsigned int alignment, align_size_1; | |
8781 | unsigned int isa_1_descsz, feature_2_descsz, descsz; | |
8782 | unsigned int isa_1_descsz_raw, feature_2_descsz_raw; | |
8783 | unsigned int padding; | |
8784 | ||
8785 | if (!IS_ELF || !x86_used_note) | |
8786 | return; | |
8787 | ||
b4a3a7b4 L |
8788 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86; |
8789 | ||
8790 | /* The .note.gnu.property section layout: | |
8791 | ||
8792 | Field Length Contents | |
8793 | ---- ---- ---- | |
8794 | n_namsz 4 4 | |
8795 | n_descsz 4 The note descriptor size | |
8796 | n_type 4 NT_GNU_PROPERTY_TYPE_0 | |
8797 | n_name 4 "GNU" | |
8798 | n_desc n_descsz The program property array | |
8799 | .... .... .... | |
8800 | */ | |
8801 | ||
8802 | /* Create the .note.gnu.property section. */ | |
8803 | sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0); | |
fd361982 | 8804 | bfd_set_section_flags (sec, |
b4a3a7b4 L |
8805 | (SEC_ALLOC |
8806 | | SEC_LOAD | |
8807 | | SEC_DATA | |
8808 | | SEC_HAS_CONTENTS | |
8809 | | SEC_READONLY)); | |
8810 | ||
8811 | if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64) | |
8812 | { | |
8813 | align_size_1 = 7; | |
8814 | alignment = 3; | |
8815 | } | |
8816 | else | |
8817 | { | |
8818 | align_size_1 = 3; | |
8819 | alignment = 2; | |
8820 | } | |
8821 | ||
fd361982 | 8822 | bfd_set_section_alignment (sec, alignment); |
b4a3a7b4 L |
8823 | elf_section_type (sec) = SHT_NOTE; |
8824 | ||
8825 | /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size | |
8826 | + 4-byte data */ | |
8827 | isa_1_descsz_raw = 4 + 4 + 4; | |
8828 | /* Align GNU_PROPERTY_X86_ISA_1_USED. */ | |
8829 | isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1; | |
8830 | ||
8831 | feature_2_descsz_raw = isa_1_descsz; | |
8832 | /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size | |
8833 | + 4-byte data */ | |
8834 | feature_2_descsz_raw += 4 + 4 + 4; | |
8835 | /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
8836 | feature_2_descsz = ((feature_2_descsz_raw + align_size_1) | |
8837 | & ~align_size_1); | |
8838 | ||
8839 | descsz = feature_2_descsz; | |
8840 | /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */ | |
8841 | p = frag_more (4 + 4 + 4 + 4 + descsz); | |
8842 | ||
8843 | /* Write n_namsz. */ | |
8844 | md_number_to_chars (p, (valueT) 4, 4); | |
8845 | ||
8846 | /* Write n_descsz. */ | |
8847 | md_number_to_chars (p + 4, (valueT) descsz, 4); | |
8848 | ||
8849 | /* Write n_type. */ | |
8850 | md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4); | |
8851 | ||
8852 | /* Write n_name. */ | |
8853 | memcpy (p + 4 * 3, "GNU", 4); | |
8854 | ||
8855 | /* Write 4-byte type. */ | |
8856 | md_number_to_chars (p + 4 * 4, | |
8857 | (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4); | |
8858 | ||
8859 | /* Write 4-byte data size. */ | |
8860 | md_number_to_chars (p + 4 * 5, (valueT) 4, 4); | |
8861 | ||
8862 | /* Write 4-byte data. */ | |
8863 | md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4); | |
8864 | ||
8865 | /* Zero out paddings. */ | |
8866 | padding = isa_1_descsz - isa_1_descsz_raw; | |
8867 | if (padding) | |
8868 | memset (p + 4 * 7, 0, padding); | |
8869 | ||
8870 | /* Write 4-byte type. */ | |
8871 | md_number_to_chars (p + isa_1_descsz + 4 * 4, | |
8872 | (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4); | |
8873 | ||
8874 | /* Write 4-byte data size. */ | |
8875 | md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4); | |
8876 | ||
8877 | /* Write 4-byte data. */ | |
8878 | md_number_to_chars (p + isa_1_descsz + 4 * 6, | |
8879 | (valueT) x86_feature_2_used, 4); | |
8880 | ||
8881 | /* Zero out paddings. */ | |
8882 | padding = feature_2_descsz - feature_2_descsz_raw; | |
8883 | if (padding) | |
8884 | memset (p + isa_1_descsz + 4 * 7, 0, padding); | |
8885 | ||
8886 | /* We probably can't restore the current segment, for there likely | |
8887 | isn't one yet... */ | |
8888 | if (seg && subseg) | |
8889 | subseg_set (seg, subseg); | |
8890 | } | |
8891 | #endif | |
8892 | ||
9c33702b JB |
8893 | static unsigned int |
8894 | encoding_length (const fragS *start_frag, offsetT start_off, | |
8895 | const char *frag_now_ptr) | |
8896 | { | |
8897 | unsigned int len = 0; | |
8898 | ||
8899 | if (start_frag != frag_now) | |
8900 | { | |
8901 | const fragS *fr = start_frag; | |
8902 | ||
8903 | do { | |
8904 | len += fr->fr_fix; | |
8905 | fr = fr->fr_next; | |
8906 | } while (fr && fr != frag_now); | |
8907 | } | |
8908 | ||
8909 | return len - start_off + (frag_now_ptr - frag_now->fr_literal); | |
8910 | } | |
8911 | ||
e379e5f3 | 8912 | /* Return 1 for test, and, cmp, add, sub, inc and dec which may |
79d72f45 HL |
8913 | be macro-fused with conditional jumps. |
8914 | NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address, | |
8915 | or is one of the following format: | |
8916 | ||
8917 | cmp m, imm | |
8918 | add m, imm | |
8919 | sub m, imm | |
8920 | test m, imm | |
8921 | and m, imm | |
8922 | inc m | |
8923 | dec m | |
8924 | ||
8925 | it is unfusible. */ | |
e379e5f3 L |
8926 | |
8927 | static int | |
79d72f45 | 8928 | maybe_fused_with_jcc_p (enum mf_cmp_kind* mf_cmp_p) |
e379e5f3 L |
8929 | { |
8930 | /* No RIP address. */ | |
8931 | if (i.base_reg && i.base_reg->reg_num == RegIP) | |
8932 | return 0; | |
8933 | ||
8934 | /* No VEX/EVEX encoding. */ | |
8935 | if (is_any_vex_encoding (&i.tm)) | |
8936 | return 0; | |
8937 | ||
79d72f45 HL |
8938 | /* add, sub without add/sub m, imm. */ |
8939 | if (i.tm.base_opcode <= 5 | |
e379e5f3 L |
8940 | || (i.tm.base_opcode >= 0x28 && i.tm.base_opcode <= 0x2d) |
8941 | || ((i.tm.base_opcode | 3) == 0x83 | |
79d72f45 | 8942 | && (i.tm.extension_opcode == 0x5 |
e379e5f3 | 8943 | || i.tm.extension_opcode == 0x0))) |
79d72f45 HL |
8944 | { |
8945 | *mf_cmp_p = mf_cmp_alu_cmp; | |
8946 | return !(i.mem_operands && i.imm_operands); | |
8947 | } | |
e379e5f3 | 8948 | |
79d72f45 HL |
8949 | /* and without and m, imm. */ |
8950 | if ((i.tm.base_opcode >= 0x20 && i.tm.base_opcode <= 0x25) | |
8951 | || ((i.tm.base_opcode | 3) == 0x83 | |
8952 | && i.tm.extension_opcode == 0x4)) | |
8953 | { | |
8954 | *mf_cmp_p = mf_cmp_test_and; | |
8955 | return !(i.mem_operands && i.imm_operands); | |
8956 | } | |
8957 | ||
8958 | /* test without test m imm. */ | |
e379e5f3 L |
8959 | if ((i.tm.base_opcode | 1) == 0x85 |
8960 | || (i.tm.base_opcode | 1) == 0xa9 | |
8961 | || ((i.tm.base_opcode | 1) == 0xf7 | |
79d72f45 HL |
8962 | && i.tm.extension_opcode == 0)) |
8963 | { | |
8964 | *mf_cmp_p = mf_cmp_test_and; | |
8965 | return !(i.mem_operands && i.imm_operands); | |
8966 | } | |
8967 | ||
8968 | /* cmp without cmp m, imm. */ | |
8969 | if ((i.tm.base_opcode >= 0x38 && i.tm.base_opcode <= 0x3d) | |
e379e5f3 L |
8970 | || ((i.tm.base_opcode | 3) == 0x83 |
8971 | && (i.tm.extension_opcode == 0x7))) | |
79d72f45 HL |
8972 | { |
8973 | *mf_cmp_p = mf_cmp_alu_cmp; | |
8974 | return !(i.mem_operands && i.imm_operands); | |
8975 | } | |
e379e5f3 | 8976 | |
79d72f45 | 8977 | /* inc, dec without inc/dec m. */ |
e379e5f3 L |
8978 | if ((i.tm.cpu_flags.bitfield.cpuno64 |
8979 | && (i.tm.base_opcode | 0xf) == 0x4f) | |
8980 | || ((i.tm.base_opcode | 1) == 0xff | |
8981 | && i.tm.extension_opcode <= 0x1)) | |
79d72f45 HL |
8982 | { |
8983 | *mf_cmp_p = mf_cmp_incdec; | |
8984 | return !i.mem_operands; | |
8985 | } | |
e379e5f3 L |
8986 | |
8987 | return 0; | |
8988 | } | |
8989 | ||
8990 | /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */ | |
8991 | ||
8992 | static int | |
79d72f45 | 8993 | add_fused_jcc_padding_frag_p (enum mf_cmp_kind* mf_cmp_p) |
e379e5f3 L |
8994 | { |
8995 | /* NB: Don't work with COND_JUMP86 without i386. */ | |
8996 | if (!align_branch_power | |
8997 | || now_seg == absolute_section | |
8998 | || !cpu_arch_flags.bitfield.cpui386 | |
8999 | || !(align_branch & align_branch_fused_bit)) | |
9000 | return 0; | |
9001 | ||
79d72f45 | 9002 | if (maybe_fused_with_jcc_p (mf_cmp_p)) |
e379e5f3 L |
9003 | { |
9004 | if (last_insn.kind == last_insn_other | |
9005 | || last_insn.seg != now_seg) | |
9006 | return 1; | |
9007 | if (flag_debug) | |
9008 | as_warn_where (last_insn.file, last_insn.line, | |
9009 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
9010 | last_insn.name, i.tm.name); | |
9011 | } | |
9012 | ||
9013 | return 0; | |
9014 | } | |
9015 | ||
9016 | /* Return 1 if a BRANCH_PREFIX frag should be generated. */ | |
9017 | ||
9018 | static int | |
9019 | add_branch_prefix_frag_p (void) | |
9020 | { | |
9021 | /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix | |
9022 | to PadLock instructions since they include prefixes in opcode. */ | |
9023 | if (!align_branch_power | |
9024 | || !align_branch_prefix_size | |
9025 | || now_seg == absolute_section | |
9026 | || i.tm.cpu_flags.bitfield.cpupadlock | |
9027 | || !cpu_arch_flags.bitfield.cpui386) | |
9028 | return 0; | |
9029 | ||
9030 | /* Don't add prefix if it is a prefix or there is no operand in case | |
9031 | that segment prefix is special. */ | |
9032 | if (!i.operands || i.tm.opcode_modifier.isprefix) | |
9033 | return 0; | |
9034 | ||
9035 | if (last_insn.kind == last_insn_other | |
9036 | || last_insn.seg != now_seg) | |
9037 | return 1; | |
9038 | ||
9039 | if (flag_debug) | |
9040 | as_warn_where (last_insn.file, last_insn.line, | |
9041 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
9042 | last_insn.name, i.tm.name); | |
9043 | ||
9044 | return 0; | |
9045 | } | |
9046 | ||
9047 | /* Return 1 if a BRANCH_PADDING frag should be generated. */ | |
9048 | ||
9049 | static int | |
79d72f45 HL |
9050 | add_branch_padding_frag_p (enum align_branch_kind *branch_p, |
9051 | enum mf_jcc_kind *mf_jcc_p) | |
e379e5f3 L |
9052 | { |
9053 | int add_padding; | |
9054 | ||
9055 | /* NB: Don't work with COND_JUMP86 without i386. */ | |
9056 | if (!align_branch_power | |
9057 | || now_seg == absolute_section | |
9058 | || !cpu_arch_flags.bitfield.cpui386) | |
9059 | return 0; | |
9060 | ||
9061 | add_padding = 0; | |
9062 | ||
9063 | /* Check for jcc and direct jmp. */ | |
9064 | if (i.tm.opcode_modifier.jump == JUMP) | |
9065 | { | |
9066 | if (i.tm.base_opcode == JUMP_PC_RELATIVE) | |
9067 | { | |
9068 | *branch_p = align_branch_jmp; | |
9069 | add_padding = align_branch & align_branch_jmp_bit; | |
9070 | } | |
9071 | else | |
9072 | { | |
79d72f45 HL |
9073 | /* Because J<cc> and JN<cc> share same group in macro-fusible table, |
9074 | igore the lowest bit. */ | |
9075 | *mf_jcc_p = (i.tm.base_opcode & 0x0e) >> 1; | |
e379e5f3 L |
9076 | *branch_p = align_branch_jcc; |
9077 | if ((align_branch & align_branch_jcc_bit)) | |
9078 | add_padding = 1; | |
9079 | } | |
9080 | } | |
9081 | else if (is_any_vex_encoding (&i.tm)) | |
9082 | return 0; | |
9083 | else if ((i.tm.base_opcode | 1) == 0xc3) | |
9084 | { | |
9085 | /* Near ret. */ | |
9086 | *branch_p = align_branch_ret; | |
9087 | if ((align_branch & align_branch_ret_bit)) | |
9088 | add_padding = 1; | |
9089 | } | |
9090 | else | |
9091 | { | |
9092 | /* Check for indirect jmp, direct and indirect calls. */ | |
9093 | if (i.tm.base_opcode == 0xe8) | |
9094 | { | |
9095 | /* Direct call. */ | |
9096 | *branch_p = align_branch_call; | |
9097 | if ((align_branch & align_branch_call_bit)) | |
9098 | add_padding = 1; | |
9099 | } | |
9100 | else if (i.tm.base_opcode == 0xff | |
9101 | && (i.tm.extension_opcode == 2 | |
9102 | || i.tm.extension_opcode == 4)) | |
9103 | { | |
9104 | /* Indirect call and jmp. */ | |
9105 | *branch_p = align_branch_indirect; | |
9106 | if ((align_branch & align_branch_indirect_bit)) | |
9107 | add_padding = 1; | |
9108 | } | |
9109 | ||
9110 | if (add_padding | |
9111 | && i.disp_operands | |
9112 | && tls_get_addr | |
9113 | && (i.op[0].disps->X_op == O_symbol | |
9114 | || (i.op[0].disps->X_op == O_subtract | |
9115 | && i.op[0].disps->X_op_symbol == GOT_symbol))) | |
9116 | { | |
9117 | symbolS *s = i.op[0].disps->X_add_symbol; | |
9118 | /* No padding to call to global or undefined tls_get_addr. */ | |
9119 | if ((S_IS_EXTERNAL (s) || !S_IS_DEFINED (s)) | |
9120 | && strcmp (S_GET_NAME (s), tls_get_addr) == 0) | |
9121 | return 0; | |
9122 | } | |
9123 | } | |
9124 | ||
9125 | if (add_padding | |
9126 | && last_insn.kind != last_insn_other | |
9127 | && last_insn.seg == now_seg) | |
9128 | { | |
9129 | if (flag_debug) | |
9130 | as_warn_where (last_insn.file, last_insn.line, | |
9131 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
9132 | last_insn.name, i.tm.name); | |
9133 | return 0; | |
9134 | } | |
9135 | ||
9136 | return add_padding; | |
9137 | } | |
9138 | ||
29b0f896 | 9139 | static void |
e3bb37b5 | 9140 | output_insn (void) |
29b0f896 | 9141 | { |
2bbd9c25 JJ |
9142 | fragS *insn_start_frag; |
9143 | offsetT insn_start_off; | |
e379e5f3 L |
9144 | fragS *fragP = NULL; |
9145 | enum align_branch_kind branch = align_branch_none; | |
79d72f45 HL |
9146 | /* The initializer is arbitrary just to avoid uninitialized error. |
9147 | it's actually either assigned in add_branch_padding_frag_p | |
9148 | or never be used. */ | |
9149 | enum mf_jcc_kind mf_jcc = mf_jcc_jo; | |
2bbd9c25 | 9150 | |
b4a3a7b4 | 9151 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
48ef937e | 9152 | if (IS_ELF && x86_used_note && now_seg != absolute_section) |
b4a3a7b4 L |
9153 | { |
9154 | if (i.tm.cpu_flags.bitfield.cpucmov) | |
9155 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_CMOV; | |
9156 | if (i.tm.cpu_flags.bitfield.cpusse) | |
9157 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE; | |
9158 | if (i.tm.cpu_flags.bitfield.cpusse2) | |
9159 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE2; | |
9160 | if (i.tm.cpu_flags.bitfield.cpusse3) | |
9161 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE3; | |
9162 | if (i.tm.cpu_flags.bitfield.cpussse3) | |
9163 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSSE3; | |
9164 | if (i.tm.cpu_flags.bitfield.cpusse4_1) | |
9165 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_1; | |
9166 | if (i.tm.cpu_flags.bitfield.cpusse4_2) | |
9167 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_2; | |
9168 | if (i.tm.cpu_flags.bitfield.cpuavx) | |
9169 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX; | |
9170 | if (i.tm.cpu_flags.bitfield.cpuavx2) | |
9171 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX2; | |
9172 | if (i.tm.cpu_flags.bitfield.cpufma) | |
9173 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_FMA; | |
9174 | if (i.tm.cpu_flags.bitfield.cpuavx512f) | |
9175 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512F; | |
9176 | if (i.tm.cpu_flags.bitfield.cpuavx512cd) | |
9177 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512CD; | |
9178 | if (i.tm.cpu_flags.bitfield.cpuavx512er) | |
9179 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512ER; | |
9180 | if (i.tm.cpu_flags.bitfield.cpuavx512pf) | |
9181 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512PF; | |
9182 | if (i.tm.cpu_flags.bitfield.cpuavx512vl) | |
9183 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512VL; | |
9184 | if (i.tm.cpu_flags.bitfield.cpuavx512dq) | |
9185 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512DQ; | |
9186 | if (i.tm.cpu_flags.bitfield.cpuavx512bw) | |
9187 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512BW; | |
9188 | if (i.tm.cpu_flags.bitfield.cpuavx512_4fmaps) | |
9189 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS; | |
9190 | if (i.tm.cpu_flags.bitfield.cpuavx512_4vnniw) | |
9191 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW; | |
9192 | if (i.tm.cpu_flags.bitfield.cpuavx512_bitalg) | |
9193 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG; | |
9194 | if (i.tm.cpu_flags.bitfield.cpuavx512ifma) | |
9195 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA; | |
9196 | if (i.tm.cpu_flags.bitfield.cpuavx512vbmi) | |
9197 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI; | |
9198 | if (i.tm.cpu_flags.bitfield.cpuavx512_vbmi2) | |
9199 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2; | |
9200 | if (i.tm.cpu_flags.bitfield.cpuavx512_vnni) | |
9201 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI; | |
462cac58 L |
9202 | if (i.tm.cpu_flags.bitfield.cpuavx512_bf16) |
9203 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BF16; | |
b4a3a7b4 L |
9204 | |
9205 | if (i.tm.cpu_flags.bitfield.cpu8087 | |
9206 | || i.tm.cpu_flags.bitfield.cpu287 | |
9207 | || i.tm.cpu_flags.bitfield.cpu387 | |
9208 | || i.tm.cpu_flags.bitfield.cpu687 | |
9209 | || i.tm.cpu_flags.bitfield.cpufisttp) | |
9210 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87; | |
921eafea | 9211 | if ((i.xstate & xstate_mmx) |
319ff62c | 9212 | || i.tm.base_opcode == 0xf77 /* emms */ |
921eafea | 9213 | || i.tm.base_opcode == 0xf0e /* femms */) |
b4a3a7b4 | 9214 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX; |
921eafea | 9215 | if ((i.xstate & xstate_xmm)) |
b4a3a7b4 | 9216 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM; |
921eafea | 9217 | if ((i.xstate & xstate_ymm) == xstate_ymm) |
b4a3a7b4 | 9218 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM; |
921eafea | 9219 | if ((i.xstate & xstate_zmm) == xstate_zmm) |
b4a3a7b4 L |
9220 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM; |
9221 | if (i.tm.cpu_flags.bitfield.cpufxsr) | |
9222 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR; | |
9223 | if (i.tm.cpu_flags.bitfield.cpuxsave) | |
9224 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE; | |
9225 | if (i.tm.cpu_flags.bitfield.cpuxsaveopt) | |
9226 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT; | |
9227 | if (i.tm.cpu_flags.bitfield.cpuxsavec) | |
9228 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC; | |
a308b89d L |
9229 | |
9230 | if ((i.xstate & xstate_tmm) == xstate_tmm | |
9231 | || i.tm.cpu_flags.bitfield.cpuamx_tile) | |
9232 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_TMM; | |
b4a3a7b4 L |
9233 | } |
9234 | #endif | |
9235 | ||
29b0f896 AM |
9236 | /* Tie dwarf2 debug info to the address at the start of the insn. |
9237 | We can't do this after the insn has been output as the current | |
9238 | frag may have been closed off. eg. by frag_var. */ | |
9239 | dwarf2_emit_insn (0); | |
9240 | ||
2bbd9c25 JJ |
9241 | insn_start_frag = frag_now; |
9242 | insn_start_off = frag_now_fix (); | |
9243 | ||
79d72f45 | 9244 | if (add_branch_padding_frag_p (&branch, &mf_jcc)) |
e379e5f3 L |
9245 | { |
9246 | char *p; | |
9247 | /* Branch can be 8 bytes. Leave some room for prefixes. */ | |
9248 | unsigned int max_branch_padding_size = 14; | |
9249 | ||
9250 | /* Align section to boundary. */ | |
9251 | record_alignment (now_seg, align_branch_power); | |
9252 | ||
9253 | /* Make room for padding. */ | |
9254 | frag_grow (max_branch_padding_size); | |
9255 | ||
9256 | /* Start of the padding. */ | |
9257 | p = frag_more (0); | |
9258 | ||
9259 | fragP = frag_now; | |
9260 | ||
9261 | frag_var (rs_machine_dependent, max_branch_padding_size, 0, | |
9262 | ENCODE_RELAX_STATE (BRANCH_PADDING, 0), | |
9263 | NULL, 0, p); | |
9264 | ||
79d72f45 | 9265 | fragP->tc_frag_data.mf_type = mf_jcc; |
e379e5f3 L |
9266 | fragP->tc_frag_data.branch_type = branch; |
9267 | fragP->tc_frag_data.max_bytes = max_branch_padding_size; | |
9268 | } | |
9269 | ||
29b0f896 | 9270 | /* Output jumps. */ |
0cfa3eb3 | 9271 | if (i.tm.opcode_modifier.jump == JUMP) |
29b0f896 | 9272 | output_branch (); |
0cfa3eb3 JB |
9273 | else if (i.tm.opcode_modifier.jump == JUMP_BYTE |
9274 | || i.tm.opcode_modifier.jump == JUMP_DWORD) | |
29b0f896 | 9275 | output_jump (); |
0cfa3eb3 | 9276 | else if (i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT) |
29b0f896 AM |
9277 | output_interseg_jump (); |
9278 | else | |
9279 | { | |
9280 | /* Output normal instructions here. */ | |
9281 | char *p; | |
9282 | unsigned char *q; | |
47465058 | 9283 | unsigned int j; |
331d2d0d | 9284 | unsigned int prefix; |
79d72f45 | 9285 | enum mf_cmp_kind mf_cmp; |
4dffcebc | 9286 | |
e4e00185 | 9287 | if (avoid_fence |
c3949f43 JB |
9288 | && (i.tm.base_opcode == 0xfaee8 |
9289 | || i.tm.base_opcode == 0xfaef0 | |
9290 | || i.tm.base_opcode == 0xfaef8)) | |
48ef937e JB |
9291 | { |
9292 | /* Encode lfence, mfence, and sfence as | |
9293 | f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ | |
9294 | if (now_seg != absolute_section) | |
9295 | { | |
9296 | offsetT val = 0x240483f0ULL; | |
9297 | ||
9298 | p = frag_more (5); | |
9299 | md_number_to_chars (p, val, 5); | |
9300 | } | |
9301 | else | |
9302 | abs_section_offset += 5; | |
9303 | return; | |
9304 | } | |
e4e00185 | 9305 | |
d022bddd IT |
9306 | /* Some processors fail on LOCK prefix. This options makes |
9307 | assembler ignore LOCK prefix and serves as a workaround. */ | |
9308 | if (omit_lock_prefix) | |
9309 | { | |
9310 | if (i.tm.base_opcode == LOCK_PREFIX_OPCODE) | |
9311 | return; | |
9312 | i.prefix[LOCK_PREFIX] = 0; | |
9313 | } | |
9314 | ||
e379e5f3 L |
9315 | if (branch) |
9316 | /* Skip if this is a branch. */ | |
9317 | ; | |
79d72f45 | 9318 | else if (add_fused_jcc_padding_frag_p (&mf_cmp)) |
e379e5f3 L |
9319 | { |
9320 | /* Make room for padding. */ | |
9321 | frag_grow (MAX_FUSED_JCC_PADDING_SIZE); | |
9322 | p = frag_more (0); | |
9323 | ||
9324 | fragP = frag_now; | |
9325 | ||
9326 | frag_var (rs_machine_dependent, MAX_FUSED_JCC_PADDING_SIZE, 0, | |
9327 | ENCODE_RELAX_STATE (FUSED_JCC_PADDING, 0), | |
9328 | NULL, 0, p); | |
9329 | ||
79d72f45 | 9330 | fragP->tc_frag_data.mf_type = mf_cmp; |
e379e5f3 L |
9331 | fragP->tc_frag_data.branch_type = align_branch_fused; |
9332 | fragP->tc_frag_data.max_bytes = MAX_FUSED_JCC_PADDING_SIZE; | |
9333 | } | |
9334 | else if (add_branch_prefix_frag_p ()) | |
9335 | { | |
9336 | unsigned int max_prefix_size = align_branch_prefix_size; | |
9337 | ||
9338 | /* Make room for padding. */ | |
9339 | frag_grow (max_prefix_size); | |
9340 | p = frag_more (0); | |
9341 | ||
9342 | fragP = frag_now; | |
9343 | ||
9344 | frag_var (rs_machine_dependent, max_prefix_size, 0, | |
9345 | ENCODE_RELAX_STATE (BRANCH_PREFIX, 0), | |
9346 | NULL, 0, p); | |
9347 | ||
9348 | fragP->tc_frag_data.max_bytes = max_prefix_size; | |
9349 | } | |
9350 | ||
43234a1e L |
9351 | /* Since the VEX/EVEX prefix contains the implicit prefix, we |
9352 | don't need the explicit prefix. */ | |
9353 | if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex) | |
bc4bd9ab | 9354 | { |
c0f3af97 | 9355 | switch (i.tm.opcode_length) |
bc4bd9ab | 9356 | { |
c0f3af97 L |
9357 | case 3: |
9358 | if (i.tm.base_opcode & 0xff000000) | |
4dffcebc | 9359 | { |
c0f3af97 | 9360 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
c3949f43 JB |
9361 | if (!i.tm.cpu_flags.bitfield.cpupadlock |
9362 | || prefix != REPE_PREFIX_OPCODE | |
9363 | || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE)) | |
9364 | add_prefix (prefix); | |
c0f3af97 L |
9365 | } |
9366 | break; | |
9367 | case 2: | |
9368 | if ((i.tm.base_opcode & 0xff0000) != 0) | |
9369 | { | |
9370 | prefix = (i.tm.base_opcode >> 16) & 0xff; | |
c3949f43 | 9371 | add_prefix (prefix); |
4dffcebc | 9372 | } |
c0f3af97 L |
9373 | break; |
9374 | case 1: | |
9375 | break; | |
390c91cf L |
9376 | case 0: |
9377 | /* Check for pseudo prefixes. */ | |
9378 | as_bad_where (insn_start_frag->fr_file, | |
9379 | insn_start_frag->fr_line, | |
9380 | _("pseudo prefix without instruction")); | |
9381 | return; | |
c0f3af97 L |
9382 | default: |
9383 | abort (); | |
bc4bd9ab | 9384 | } |
c0f3af97 | 9385 | |
6d19a37a | 9386 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
cf61b747 L |
9387 | /* For x32, add a dummy REX_OPCODE prefix for mov/add with |
9388 | R_X86_64_GOTTPOFF relocation so that linker can safely | |
14470f07 L |
9389 | perform IE->LE optimization. A dummy REX_OPCODE prefix |
9390 | is also needed for lea with R_X86_64_GOTPC32_TLSDESC | |
9391 | relocation for GDesc -> IE/LE optimization. */ | |
cf61b747 L |
9392 | if (x86_elf_abi == X86_64_X32_ABI |
9393 | && i.operands == 2 | |
14470f07 L |
9394 | && (i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF |
9395 | || i.reloc[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC) | |
cf61b747 L |
9396 | && i.prefix[REX_PREFIX] == 0) |
9397 | add_prefix (REX_OPCODE); | |
6d19a37a | 9398 | #endif |
cf61b747 | 9399 | |
c0f3af97 L |
9400 | /* The prefix bytes. */ |
9401 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
9402 | if (*q) | |
48ef937e | 9403 | frag_opcode_byte (*q); |
0f10071e | 9404 | } |
ae5c1c7b | 9405 | else |
c0f3af97 L |
9406 | { |
9407 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
9408 | if (*q) | |
9409 | switch (j) | |
9410 | { | |
c0f3af97 L |
9411 | case SEG_PREFIX: |
9412 | case ADDR_PREFIX: | |
48ef937e | 9413 | frag_opcode_byte (*q); |
c0f3af97 L |
9414 | break; |
9415 | default: | |
9416 | /* There should be no other prefixes for instructions | |
9417 | with VEX prefix. */ | |
9418 | abort (); | |
9419 | } | |
9420 | ||
43234a1e L |
9421 | /* For EVEX instructions i.vrex should become 0 after |
9422 | build_evex_prefix. For VEX instructions upper 16 registers | |
9423 | aren't available, so VREX should be 0. */ | |
9424 | if (i.vrex) | |
9425 | abort (); | |
c0f3af97 | 9426 | /* Now the VEX prefix. */ |
48ef937e JB |
9427 | if (now_seg != absolute_section) |
9428 | { | |
9429 | p = frag_more (i.vex.length); | |
9430 | for (j = 0; j < i.vex.length; j++) | |
9431 | p[j] = i.vex.bytes[j]; | |
9432 | } | |
9433 | else | |
9434 | abs_section_offset += i.vex.length; | |
c0f3af97 | 9435 | } |
252b5132 | 9436 | |
29b0f896 | 9437 | /* Now the opcode; be careful about word order here! */ |
48ef937e JB |
9438 | if (now_seg == absolute_section) |
9439 | abs_section_offset += i.tm.opcode_length; | |
9440 | else if (i.tm.opcode_length == 1) | |
29b0f896 AM |
9441 | { |
9442 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
9443 | } | |
9444 | else | |
9445 | { | |
4dffcebc | 9446 | switch (i.tm.opcode_length) |
331d2d0d | 9447 | { |
43234a1e L |
9448 | case 4: |
9449 | p = frag_more (4); | |
9450 | *p++ = (i.tm.base_opcode >> 24) & 0xff; | |
9451 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
9452 | break; | |
4dffcebc | 9453 | case 3: |
331d2d0d L |
9454 | p = frag_more (3); |
9455 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
4dffcebc L |
9456 | break; |
9457 | case 2: | |
9458 | p = frag_more (2); | |
9459 | break; | |
9460 | default: | |
9461 | abort (); | |
9462 | break; | |
331d2d0d | 9463 | } |
0f10071e | 9464 | |
29b0f896 AM |
9465 | /* Put out high byte first: can't use md_number_to_chars! */ |
9466 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
9467 | *p = i.tm.base_opcode & 0xff; | |
9468 | } | |
3e73aa7c | 9469 | |
29b0f896 | 9470 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 9471 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 9472 | { |
48ef937e JB |
9473 | frag_opcode_byte ((i.rm.regmem << 0) |
9474 | | (i.rm.reg << 3) | |
9475 | | (i.rm.mode << 6)); | |
29b0f896 AM |
9476 | /* If i.rm.regmem == ESP (4) |
9477 | && i.rm.mode != (Register mode) | |
9478 | && not 16 bit | |
9479 | ==> need second modrm byte. */ | |
9480 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
9481 | && i.rm.mode != 3 | |
dc821c5f | 9482 | && !(i.base_reg && i.base_reg->reg_type.bitfield.word)) |
48ef937e JB |
9483 | frag_opcode_byte ((i.sib.base << 0) |
9484 | | (i.sib.index << 3) | |
9485 | | (i.sib.scale << 6)); | |
29b0f896 | 9486 | } |
3e73aa7c | 9487 | |
29b0f896 | 9488 | if (i.disp_operands) |
2bbd9c25 | 9489 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 9490 | |
29b0f896 | 9491 | if (i.imm_operands) |
2bbd9c25 | 9492 | output_imm (insn_start_frag, insn_start_off); |
9c33702b JB |
9493 | |
9494 | /* | |
9495 | * frag_now_fix () returning plain abs_section_offset when we're in the | |
9496 | * absolute section, and abs_section_offset not getting updated as data | |
9497 | * gets added to the frag breaks the logic below. | |
9498 | */ | |
9499 | if (now_seg != absolute_section) | |
9500 | { | |
9501 | j = encoding_length (insn_start_frag, insn_start_off, frag_more (0)); | |
9502 | if (j > 15) | |
9503 | as_warn (_("instruction length of %u bytes exceeds the limit of 15"), | |
9504 | j); | |
e379e5f3 L |
9505 | else if (fragP) |
9506 | { | |
9507 | /* NB: Don't add prefix with GOTPC relocation since | |
9508 | output_disp() above depends on the fixed encoding | |
9509 | length. Can't add prefix with TLS relocation since | |
9510 | it breaks TLS linker optimization. */ | |
9511 | unsigned int max = i.has_gotpc_tls_reloc ? 0 : 15 - j; | |
9512 | /* Prefix count on the current instruction. */ | |
9513 | unsigned int count = i.vex.length; | |
9514 | unsigned int k; | |
9515 | for (k = 0; k < ARRAY_SIZE (i.prefix); k++) | |
9516 | /* REX byte is encoded in VEX/EVEX prefix. */ | |
9517 | if (i.prefix[k] && (k != REX_PREFIX || !i.vex.length)) | |
9518 | count++; | |
9519 | ||
9520 | /* Count prefixes for extended opcode maps. */ | |
9521 | if (!i.vex.length) | |
9522 | switch (i.tm.opcode_length) | |
9523 | { | |
9524 | case 3: | |
9525 | if (((i.tm.base_opcode >> 16) & 0xff) == 0xf) | |
9526 | { | |
9527 | count++; | |
9528 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
9529 | { | |
9530 | case 0x38: | |
9531 | case 0x3a: | |
9532 | count++; | |
9533 | break; | |
9534 | default: | |
9535 | break; | |
9536 | } | |
9537 | } | |
9538 | break; | |
9539 | case 2: | |
9540 | if (((i.tm.base_opcode >> 8) & 0xff) == 0xf) | |
9541 | count++; | |
9542 | break; | |
9543 | case 1: | |
9544 | break; | |
9545 | default: | |
9546 | abort (); | |
9547 | } | |
9548 | ||
9549 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
9550 | == BRANCH_PREFIX) | |
9551 | { | |
9552 | /* Set the maximum prefix size in BRANCH_PREFIX | |
9553 | frag. */ | |
9554 | if (fragP->tc_frag_data.max_bytes > max) | |
9555 | fragP->tc_frag_data.max_bytes = max; | |
9556 | if (fragP->tc_frag_data.max_bytes > count) | |
9557 | fragP->tc_frag_data.max_bytes -= count; | |
9558 | else | |
9559 | fragP->tc_frag_data.max_bytes = 0; | |
9560 | } | |
9561 | else | |
9562 | { | |
9563 | /* Remember the maximum prefix size in FUSED_JCC_PADDING | |
9564 | frag. */ | |
9565 | unsigned int max_prefix_size; | |
9566 | if (align_branch_prefix_size > max) | |
9567 | max_prefix_size = max; | |
9568 | else | |
9569 | max_prefix_size = align_branch_prefix_size; | |
9570 | if (max_prefix_size > count) | |
9571 | fragP->tc_frag_data.max_prefix_length | |
9572 | = max_prefix_size - count; | |
9573 | } | |
9574 | ||
9575 | /* Use existing segment prefix if possible. Use CS | |
9576 | segment prefix in 64-bit mode. In 32-bit mode, use SS | |
9577 | segment prefix with ESP/EBP base register and use DS | |
9578 | segment prefix without ESP/EBP base register. */ | |
9579 | if (i.prefix[SEG_PREFIX]) | |
9580 | fragP->tc_frag_data.default_prefix = i.prefix[SEG_PREFIX]; | |
9581 | else if (flag_code == CODE_64BIT) | |
9582 | fragP->tc_frag_data.default_prefix = CS_PREFIX_OPCODE; | |
9583 | else if (i.base_reg | |
9584 | && (i.base_reg->reg_num == 4 | |
9585 | || i.base_reg->reg_num == 5)) | |
9586 | fragP->tc_frag_data.default_prefix = SS_PREFIX_OPCODE; | |
9587 | else | |
9588 | fragP->tc_frag_data.default_prefix = DS_PREFIX_OPCODE; | |
9589 | } | |
9c33702b | 9590 | } |
29b0f896 | 9591 | } |
252b5132 | 9592 | |
e379e5f3 L |
9593 | /* NB: Don't work with COND_JUMP86 without i386. */ |
9594 | if (align_branch_power | |
9595 | && now_seg != absolute_section | |
9596 | && cpu_arch_flags.bitfield.cpui386) | |
9597 | { | |
9598 | /* Terminate each frag so that we can add prefix and check for | |
9599 | fused jcc. */ | |
9600 | frag_wane (frag_now); | |
9601 | frag_new (0); | |
9602 | } | |
9603 | ||
29b0f896 AM |
9604 | #ifdef DEBUG386 |
9605 | if (flag_debug) | |
9606 | { | |
7b81dfbb | 9607 | pi ("" /*line*/, &i); |
29b0f896 AM |
9608 | } |
9609 | #endif /* DEBUG386 */ | |
9610 | } | |
252b5132 | 9611 | |
e205caa7 L |
9612 | /* Return the size of the displacement operand N. */ |
9613 | ||
9614 | static int | |
9615 | disp_size (unsigned int n) | |
9616 | { | |
9617 | int size = 4; | |
43234a1e | 9618 | |
b5014f7a | 9619 | if (i.types[n].bitfield.disp64) |
40fb9820 L |
9620 | size = 8; |
9621 | else if (i.types[n].bitfield.disp8) | |
9622 | size = 1; | |
9623 | else if (i.types[n].bitfield.disp16) | |
9624 | size = 2; | |
e205caa7 L |
9625 | return size; |
9626 | } | |
9627 | ||
9628 | /* Return the size of the immediate operand N. */ | |
9629 | ||
9630 | static int | |
9631 | imm_size (unsigned int n) | |
9632 | { | |
9633 | int size = 4; | |
40fb9820 L |
9634 | if (i.types[n].bitfield.imm64) |
9635 | size = 8; | |
9636 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
9637 | size = 1; | |
9638 | else if (i.types[n].bitfield.imm16) | |
9639 | size = 2; | |
e205caa7 L |
9640 | return size; |
9641 | } | |
9642 | ||
29b0f896 | 9643 | static void |
64e74474 | 9644 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
9645 | { |
9646 | char *p; | |
9647 | unsigned int n; | |
252b5132 | 9648 | |
29b0f896 AM |
9649 | for (n = 0; n < i.operands; n++) |
9650 | { | |
b5014f7a | 9651 | if (operand_type_check (i.types[n], disp)) |
29b0f896 | 9652 | { |
48ef937e JB |
9653 | int size = disp_size (n); |
9654 | ||
9655 | if (now_seg == absolute_section) | |
9656 | abs_section_offset += size; | |
9657 | else if (i.op[n].disps->X_op == O_constant) | |
29b0f896 | 9658 | { |
43234a1e | 9659 | offsetT val = i.op[n].disps->X_add_number; |
252b5132 | 9660 | |
629cfaf1 JB |
9661 | val = offset_in_range (val >> (size == 1 ? i.memshift : 0), |
9662 | size); | |
29b0f896 AM |
9663 | p = frag_more (size); |
9664 | md_number_to_chars (p, val, size); | |
9665 | } | |
9666 | else | |
9667 | { | |
f86103b7 | 9668 | enum bfd_reloc_code_real reloc_type; |
40fb9820 | 9669 | int sign = i.types[n].bitfield.disp32s; |
29b0f896 | 9670 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
02a86693 | 9671 | fixS *fixP; |
29b0f896 | 9672 | |
e205caa7 | 9673 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 9674 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 9675 | |
29b0f896 AM |
9676 | /* The PC relative address is computed relative |
9677 | to the instruction boundary, so in case immediate | |
9678 | fields follows, we need to adjust the value. */ | |
9679 | if (pcrel && i.imm_operands) | |
9680 | { | |
29b0f896 | 9681 | unsigned int n1; |
e205caa7 | 9682 | int sz = 0; |
252b5132 | 9683 | |
29b0f896 | 9684 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 9685 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 9686 | { |
e205caa7 L |
9687 | /* Only one immediate is allowed for PC |
9688 | relative address. */ | |
9c2799c2 | 9689 | gas_assert (sz == 0); |
e205caa7 L |
9690 | sz = imm_size (n1); |
9691 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 9692 | } |
29b0f896 | 9693 | /* We should find the immediate. */ |
9c2799c2 | 9694 | gas_assert (sz != 0); |
29b0f896 | 9695 | } |
520dc8e8 | 9696 | |
29b0f896 | 9697 | p = frag_more (size); |
d258b828 | 9698 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 9699 | if (GOT_symbol |
2bbd9c25 | 9700 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 9701 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
9702 | || reloc_type == BFD_RELOC_X86_64_32S |
9703 | || (reloc_type == BFD_RELOC_64 | |
9704 | && object_64bit)) | |
d6ab8113 JB |
9705 | && (i.op[n].disps->X_op == O_symbol |
9706 | || (i.op[n].disps->X_op == O_add | |
9707 | && ((symbol_get_value_expression | |
9708 | (i.op[n].disps->X_op_symbol)->X_op) | |
9709 | == O_subtract)))) | |
9710 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 | 9711 | { |
4fa24527 | 9712 | if (!object_64bit) |
7b81dfbb AJ |
9713 | { |
9714 | reloc_type = BFD_RELOC_386_GOTPC; | |
e379e5f3 | 9715 | i.has_gotpc_tls_reloc = TRUE; |
d583596c JB |
9716 | i.op[n].imms->X_add_number += |
9717 | encoding_length (insn_start_frag, insn_start_off, p); | |
7b81dfbb AJ |
9718 | } |
9719 | else if (reloc_type == BFD_RELOC_64) | |
9720 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 9721 | else |
7b81dfbb AJ |
9722 | /* Don't do the adjustment for x86-64, as there |
9723 | the pcrel addressing is relative to the _next_ | |
9724 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 9725 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 9726 | } |
e379e5f3 L |
9727 | else if (align_branch_power) |
9728 | { | |
9729 | switch (reloc_type) | |
9730 | { | |
9731 | case BFD_RELOC_386_TLS_GD: | |
9732 | case BFD_RELOC_386_TLS_LDM: | |
9733 | case BFD_RELOC_386_TLS_IE: | |
9734 | case BFD_RELOC_386_TLS_IE_32: | |
9735 | case BFD_RELOC_386_TLS_GOTIE: | |
9736 | case BFD_RELOC_386_TLS_GOTDESC: | |
9737 | case BFD_RELOC_386_TLS_DESC_CALL: | |
9738 | case BFD_RELOC_X86_64_TLSGD: | |
9739 | case BFD_RELOC_X86_64_TLSLD: | |
9740 | case BFD_RELOC_X86_64_GOTTPOFF: | |
9741 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: | |
9742 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
9743 | i.has_gotpc_tls_reloc = TRUE; | |
9744 | default: | |
9745 | break; | |
9746 | } | |
9747 | } | |
02a86693 L |
9748 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, |
9749 | size, i.op[n].disps, pcrel, | |
9750 | reloc_type); | |
9751 | /* Check for "call/jmp *mem", "mov mem, %reg", | |
9752 | "test %reg, mem" and "binop mem, %reg" where binop | |
9753 | is one of adc, add, and, cmp, or, sbb, sub, xor | |
e60f4d3b L |
9754 | instructions without data prefix. Always generate |
9755 | R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */ | |
9756 | if (i.prefix[DATA_PREFIX] == 0 | |
9757 | && (generate_relax_relocations | |
9758 | || (!object_64bit | |
9759 | && i.rm.mode == 0 | |
9760 | && i.rm.regmem == 5)) | |
0cb4071e L |
9761 | && (i.rm.mode == 2 |
9762 | || (i.rm.mode == 0 && i.rm.regmem == 5)) | |
2ae4c703 | 9763 | && !is_any_vex_encoding(&i.tm) |
02a86693 L |
9764 | && ((i.operands == 1 |
9765 | && i.tm.base_opcode == 0xff | |
9766 | && (i.rm.reg == 2 || i.rm.reg == 4)) | |
9767 | || (i.operands == 2 | |
9768 | && (i.tm.base_opcode == 0x8b | |
9769 | || i.tm.base_opcode == 0x85 | |
2ae4c703 | 9770 | || (i.tm.base_opcode & ~0x38) == 0x03)))) |
02a86693 L |
9771 | { |
9772 | if (object_64bit) | |
9773 | { | |
9774 | fixP->fx_tcbit = i.rex != 0; | |
9775 | if (i.base_reg | |
e968fc9b | 9776 | && (i.base_reg->reg_num == RegIP)) |
02a86693 L |
9777 | fixP->fx_tcbit2 = 1; |
9778 | } | |
9779 | else | |
9780 | fixP->fx_tcbit2 = 1; | |
9781 | } | |
29b0f896 AM |
9782 | } |
9783 | } | |
9784 | } | |
9785 | } | |
252b5132 | 9786 | |
29b0f896 | 9787 | static void |
64e74474 | 9788 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
9789 | { |
9790 | char *p; | |
9791 | unsigned int n; | |
252b5132 | 9792 | |
29b0f896 AM |
9793 | for (n = 0; n < i.operands; n++) |
9794 | { | |
43234a1e L |
9795 | /* Skip SAE/RC Imm operand in EVEX. They are already handled. */ |
9796 | if (i.rounding && (int) n == i.rounding->operand) | |
9797 | continue; | |
9798 | ||
40fb9820 | 9799 | if (operand_type_check (i.types[n], imm)) |
29b0f896 | 9800 | { |
48ef937e JB |
9801 | int size = imm_size (n); |
9802 | ||
9803 | if (now_seg == absolute_section) | |
9804 | abs_section_offset += size; | |
9805 | else if (i.op[n].imms->X_op == O_constant) | |
29b0f896 | 9806 | { |
29b0f896 | 9807 | offsetT val; |
b4cac588 | 9808 | |
29b0f896 AM |
9809 | val = offset_in_range (i.op[n].imms->X_add_number, |
9810 | size); | |
9811 | p = frag_more (size); | |
9812 | md_number_to_chars (p, val, size); | |
9813 | } | |
9814 | else | |
9815 | { | |
9816 | /* Not absolute_section. | |
9817 | Need a 32-bit fixup (don't support 8bit | |
9818 | non-absolute imms). Try to support other | |
9819 | sizes ... */ | |
f86103b7 | 9820 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 9821 | int sign; |
29b0f896 | 9822 | |
40fb9820 | 9823 | if (i.types[n].bitfield.imm32s |
a7d61044 | 9824 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 9825 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 9826 | sign = 1; |
e205caa7 L |
9827 | else |
9828 | sign = 0; | |
520dc8e8 | 9829 | |
29b0f896 | 9830 | p = frag_more (size); |
d258b828 | 9831 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
f86103b7 | 9832 | |
2bbd9c25 JJ |
9833 | /* This is tough to explain. We end up with this one if we |
9834 | * have operands that look like | |
9835 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
9836 | * obtain the absolute address of the GOT, and it is strongly | |
9837 | * preferable from a performance point of view to avoid using | |
9838 | * a runtime relocation for this. The actual sequence of | |
9839 | * instructions often look something like: | |
9840 | * | |
9841 | * call .L66 | |
9842 | * .L66: | |
9843 | * popl %ebx | |
9844 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
9845 | * | |
9846 | * The call and pop essentially return the absolute address | |
9847 | * of the label .L66 and store it in %ebx. The linker itself | |
9848 | * will ultimately change the first operand of the addl so | |
9849 | * that %ebx points to the GOT, but to keep things simple, the | |
9850 | * .o file must have this operand set so that it generates not | |
9851 | * the absolute address of .L66, but the absolute address of | |
9852 | * itself. This allows the linker itself simply treat a GOTPC | |
9853 | * relocation as asking for a pcrel offset to the GOT to be | |
9854 | * added in, and the addend of the relocation is stored in the | |
9855 | * operand field for the instruction itself. | |
9856 | * | |
9857 | * Our job here is to fix the operand so that it would add | |
9858 | * the correct offset so that %ebx would point to itself. The | |
9859 | * thing that is tricky is that .-.L66 will point to the | |
9860 | * beginning of the instruction, so we need to further modify | |
9861 | * the operand so that it will point to itself. There are | |
9862 | * other cases where you have something like: | |
9863 | * | |
9864 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
9865 | * | |
9866 | * and here no correction would be required. Internally in | |
9867 | * the assembler we treat operands of this form as not being | |
9868 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
9869 | * whether it would simplify matters to do it this way. Who | |
9870 | * knows. In earlier versions of the PIC patches, the | |
9871 | * pcrel_adjust field was used to store the correction, but | |
9872 | * since the expression is not pcrel, I felt it would be | |
9873 | * confusing to do it this way. */ | |
9874 | ||
d6ab8113 | 9875 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
9876 | || reloc_type == BFD_RELOC_X86_64_32S |
9877 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
9878 | && GOT_symbol |
9879 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
9880 | && (i.op[n].imms->X_op == O_symbol | |
9881 | || (i.op[n].imms->X_op == O_add | |
9882 | && ((symbol_get_value_expression | |
9883 | (i.op[n].imms->X_op_symbol)->X_op) | |
9884 | == O_subtract)))) | |
9885 | { | |
4fa24527 | 9886 | if (!object_64bit) |
d6ab8113 | 9887 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 9888 | else if (size == 4) |
d6ab8113 | 9889 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
9890 | else if (size == 8) |
9891 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
e379e5f3 | 9892 | i.has_gotpc_tls_reloc = TRUE; |
d583596c JB |
9893 | i.op[n].imms->X_add_number += |
9894 | encoding_length (insn_start_frag, insn_start_off, p); | |
29b0f896 | 9895 | } |
29b0f896 AM |
9896 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
9897 | i.op[n].imms, 0, reloc_type); | |
9898 | } | |
9899 | } | |
9900 | } | |
252b5132 RH |
9901 | } |
9902 | \f | |
d182319b JB |
9903 | /* x86_cons_fix_new is called via the expression parsing code when a |
9904 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
d182319b JB |
9905 | static int cons_sign = -1; |
9906 | ||
9907 | void | |
e3bb37b5 | 9908 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
62ebcb5c | 9909 | expressionS *exp, bfd_reloc_code_real_type r) |
d182319b | 9910 | { |
d258b828 | 9911 | r = reloc (len, 0, cons_sign, r); |
d182319b JB |
9912 | |
9913 | #ifdef TE_PE | |
9914 | if (exp->X_op == O_secrel) | |
9915 | { | |
9916 | exp->X_op = O_symbol; | |
9917 | r = BFD_RELOC_32_SECREL; | |
9918 | } | |
9919 | #endif | |
9920 | ||
9921 | fix_new_exp (frag, off, len, exp, 0, r); | |
9922 | } | |
9923 | ||
357d1bd8 L |
9924 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
9925 | purpose of the `.dc.a' internal pseudo-op. */ | |
9926 | ||
9927 | int | |
9928 | x86_address_bytes (void) | |
9929 | { | |
9930 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) | |
9931 | return 4; | |
9932 | return stdoutput->arch_info->bits_per_address / 8; | |
9933 | } | |
9934 | ||
d382c579 TG |
9935 | #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
9936 | || defined (LEX_AT) | |
d258b828 | 9937 | # define lex_got(reloc, adjust, types) NULL |
718ddfc0 | 9938 | #else |
f3c180ae AM |
9939 | /* Parse operands of the form |
9940 | <symbol>@GOTOFF+<nnn> | |
9941 | and similar .plt or .got references. | |
9942 | ||
9943 | If we find one, set up the correct relocation in RELOC and copy the | |
9944 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
9945 | parsing by the calling routine. Return this buffer, and if ADJUST | |
9946 | is non-null set it to the length of the string we removed from the | |
9947 | input line. Otherwise return NULL. */ | |
9948 | static char * | |
91d6fa6a | 9949 | lex_got (enum bfd_reloc_code_real *rel, |
64e74474 | 9950 | int *adjust, |
d258b828 | 9951 | i386_operand_type *types) |
f3c180ae | 9952 | { |
7b81dfbb AJ |
9953 | /* Some of the relocations depend on the size of what field is to |
9954 | be relocated. But in our callers i386_immediate and i386_displacement | |
9955 | we don't yet know the operand size (this will be set by insn | |
9956 | matching). Hence we record the word32 relocation here, | |
9957 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
9958 | static const struct { |
9959 | const char *str; | |
cff8d58a | 9960 | int len; |
4fa24527 | 9961 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 9962 | const i386_operand_type types64; |
f3c180ae | 9963 | } gotrel[] = { |
8ce3d284 | 9964 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
9965 | { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, |
9966 | BFD_RELOC_SIZE32 }, | |
9967 | OPERAND_TYPE_IMM32_64 }, | |
8ce3d284 | 9968 | #endif |
cff8d58a L |
9969 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
9970 | BFD_RELOC_X86_64_PLTOFF64 }, | |
40fb9820 | 9971 | OPERAND_TYPE_IMM64 }, |
cff8d58a L |
9972 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
9973 | BFD_RELOC_X86_64_PLT32 }, | |
40fb9820 | 9974 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9975 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
9976 | BFD_RELOC_X86_64_GOTPLT64 }, | |
40fb9820 | 9977 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
9978 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
9979 | BFD_RELOC_X86_64_GOTOFF64 }, | |
40fb9820 | 9980 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
9981 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
9982 | BFD_RELOC_X86_64_GOTPCREL }, | |
40fb9820 | 9983 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9984 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
9985 | BFD_RELOC_X86_64_TLSGD }, | |
40fb9820 | 9986 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9987 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
9988 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 9989 | OPERAND_TYPE_NONE }, |
cff8d58a L |
9990 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
9991 | BFD_RELOC_X86_64_TLSLD }, | |
40fb9820 | 9992 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9993 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
9994 | BFD_RELOC_X86_64_GOTTPOFF }, | |
40fb9820 | 9995 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9996 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
9997 | BFD_RELOC_X86_64_TPOFF32 }, | |
40fb9820 | 9998 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
9999 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
10000 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 10001 | OPERAND_TYPE_NONE }, |
cff8d58a L |
10002 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
10003 | BFD_RELOC_X86_64_DTPOFF32 }, | |
40fb9820 | 10004 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
10005 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
10006 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 10007 | OPERAND_TYPE_NONE }, |
cff8d58a L |
10008 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
10009 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 10010 | OPERAND_TYPE_NONE }, |
cff8d58a L |
10011 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
10012 | BFD_RELOC_X86_64_GOT32 }, | |
40fb9820 | 10013 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
cff8d58a L |
10014 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
10015 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
40fb9820 | 10016 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
10017 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
10018 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
40fb9820 | 10019 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
f3c180ae AM |
10020 | }; |
10021 | char *cp; | |
10022 | unsigned int j; | |
10023 | ||
d382c579 | 10024 | #if defined (OBJ_MAYBE_ELF) |
718ddfc0 JB |
10025 | if (!IS_ELF) |
10026 | return NULL; | |
d382c579 | 10027 | #endif |
718ddfc0 | 10028 | |
f3c180ae | 10029 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 10030 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
10031 | return NULL; |
10032 | ||
47465058 | 10033 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae | 10034 | { |
cff8d58a | 10035 | int len = gotrel[j].len; |
28f81592 | 10036 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 10037 | { |
4fa24527 | 10038 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 10039 | { |
28f81592 AM |
10040 | int first, second; |
10041 | char *tmpbuf, *past_reloc; | |
f3c180ae | 10042 | |
91d6fa6a | 10043 | *rel = gotrel[j].rel[object_64bit]; |
f3c180ae | 10044 | |
3956db08 JB |
10045 | if (types) |
10046 | { | |
10047 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
10048 | { |
10049 | types->bitfield.imm32 = 1; | |
10050 | types->bitfield.disp32 = 1; | |
10051 | } | |
3956db08 JB |
10052 | else |
10053 | *types = gotrel[j].types64; | |
10054 | } | |
10055 | ||
8fd4256d | 10056 | if (j != 0 && GOT_symbol == NULL) |
f3c180ae AM |
10057 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
10058 | ||
28f81592 | 10059 | /* The length of the first part of our input line. */ |
f3c180ae | 10060 | first = cp - input_line_pointer; |
28f81592 AM |
10061 | |
10062 | /* The second part goes from after the reloc token until | |
67c11a9b | 10063 | (and including) an end_of_line char or comma. */ |
28f81592 | 10064 | past_reloc = cp + 1 + len; |
67c11a9b AM |
10065 | cp = past_reloc; |
10066 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
10067 | ++cp; | |
10068 | second = cp + 1 - past_reloc; | |
28f81592 AM |
10069 | |
10070 | /* Allocate and copy string. The trailing NUL shouldn't | |
10071 | be necessary, but be safe. */ | |
add39d23 | 10072 | tmpbuf = XNEWVEC (char, first + second + 2); |
f3c180ae | 10073 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
10074 | if (second != 0 && *past_reloc != ' ') |
10075 | /* Replace the relocation token with ' ', so that | |
10076 | errors like foo@GOTOFF1 will be detected. */ | |
10077 | tmpbuf[first++] = ' '; | |
af89796a L |
10078 | else |
10079 | /* Increment length by 1 if the relocation token is | |
10080 | removed. */ | |
10081 | len++; | |
10082 | if (adjust) | |
10083 | *adjust = len; | |
0787a12d AM |
10084 | memcpy (tmpbuf + first, past_reloc, second); |
10085 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
10086 | return tmpbuf; |
10087 | } | |
10088 | ||
4fa24527 JB |
10089 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
10090 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
10091 | return NULL; |
10092 | } | |
10093 | } | |
10094 | ||
10095 | /* Might be a symbol version string. Don't as_bad here. */ | |
10096 | return NULL; | |
10097 | } | |
4e4f7c87 | 10098 | #endif |
f3c180ae | 10099 | |
a988325c NC |
10100 | #ifdef TE_PE |
10101 | #ifdef lex_got | |
10102 | #undef lex_got | |
10103 | #endif | |
10104 | /* Parse operands of the form | |
10105 | <symbol>@SECREL32+<nnn> | |
10106 | ||
10107 | If we find one, set up the correct relocation in RELOC and copy the | |
10108 | input string, minus the `@SECREL32' into a malloc'd buffer for | |
10109 | parsing by the calling routine. Return this buffer, and if ADJUST | |
10110 | is non-null set it to the length of the string we removed from the | |
34bca508 L |
10111 | input line. Otherwise return NULL. |
10112 | ||
a988325c NC |
10113 | This function is copied from the ELF version above adjusted for PE targets. */ |
10114 | ||
10115 | static char * | |
10116 | lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED, | |
10117 | int *adjust ATTRIBUTE_UNUSED, | |
d258b828 | 10118 | i386_operand_type *types) |
a988325c NC |
10119 | { |
10120 | static const struct | |
10121 | { | |
10122 | const char *str; | |
10123 | int len; | |
10124 | const enum bfd_reloc_code_real rel[2]; | |
10125 | const i386_operand_type types64; | |
10126 | } | |
10127 | gotrel[] = | |
10128 | { | |
10129 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, | |
10130 | BFD_RELOC_32_SECREL }, | |
10131 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, | |
10132 | }; | |
10133 | ||
10134 | char *cp; | |
10135 | unsigned j; | |
10136 | ||
10137 | for (cp = input_line_pointer; *cp != '@'; cp++) | |
10138 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') | |
10139 | return NULL; | |
10140 | ||
10141 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) | |
10142 | { | |
10143 | int len = gotrel[j].len; | |
10144 | ||
10145 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) | |
10146 | { | |
10147 | if (gotrel[j].rel[object_64bit] != 0) | |
10148 | { | |
10149 | int first, second; | |
10150 | char *tmpbuf, *past_reloc; | |
10151 | ||
10152 | *rel = gotrel[j].rel[object_64bit]; | |
10153 | if (adjust) | |
10154 | *adjust = len; | |
10155 | ||
10156 | if (types) | |
10157 | { | |
10158 | if (flag_code != CODE_64BIT) | |
10159 | { | |
10160 | types->bitfield.imm32 = 1; | |
10161 | types->bitfield.disp32 = 1; | |
10162 | } | |
10163 | else | |
10164 | *types = gotrel[j].types64; | |
10165 | } | |
10166 | ||
10167 | /* The length of the first part of our input line. */ | |
10168 | first = cp - input_line_pointer; | |
10169 | ||
10170 | /* The second part goes from after the reloc token until | |
10171 | (and including) an end_of_line char or comma. */ | |
10172 | past_reloc = cp + 1 + len; | |
10173 | cp = past_reloc; | |
10174 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
10175 | ++cp; | |
10176 | second = cp + 1 - past_reloc; | |
10177 | ||
10178 | /* Allocate and copy string. The trailing NUL shouldn't | |
10179 | be necessary, but be safe. */ | |
add39d23 | 10180 | tmpbuf = XNEWVEC (char, first + second + 2); |
a988325c NC |
10181 | memcpy (tmpbuf, input_line_pointer, first); |
10182 | if (second != 0 && *past_reloc != ' ') | |
10183 | /* Replace the relocation token with ' ', so that | |
10184 | errors like foo@SECLREL321 will be detected. */ | |
10185 | tmpbuf[first++] = ' '; | |
10186 | memcpy (tmpbuf + first, past_reloc, second); | |
10187 | tmpbuf[first + second] = '\0'; | |
10188 | return tmpbuf; | |
10189 | } | |
10190 | ||
10191 | as_bad (_("@%s reloc is not supported with %d-bit output format"), | |
10192 | gotrel[j].str, 1 << (5 + object_64bit)); | |
10193 | return NULL; | |
10194 | } | |
10195 | } | |
10196 | ||
10197 | /* Might be a symbol version string. Don't as_bad here. */ | |
10198 | return NULL; | |
10199 | } | |
10200 | ||
10201 | #endif /* TE_PE */ | |
10202 | ||
62ebcb5c | 10203 | bfd_reloc_code_real_type |
e3bb37b5 | 10204 | x86_cons (expressionS *exp, int size) |
f3c180ae | 10205 | { |
62ebcb5c AM |
10206 | bfd_reloc_code_real_type got_reloc = NO_RELOC; |
10207 | ||
ee86248c JB |
10208 | intel_syntax = -intel_syntax; |
10209 | ||
3c7b9c2c | 10210 | exp->X_md = 0; |
4fa24527 | 10211 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
10212 | { |
10213 | /* Handle @GOTOFF and the like in an expression. */ | |
10214 | char *save; | |
10215 | char *gotfree_input_line; | |
4a57f2cf | 10216 | int adjust = 0; |
f3c180ae AM |
10217 | |
10218 | save = input_line_pointer; | |
d258b828 | 10219 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
10220 | if (gotfree_input_line) |
10221 | input_line_pointer = gotfree_input_line; | |
10222 | ||
10223 | expression (exp); | |
10224 | ||
10225 | if (gotfree_input_line) | |
10226 | { | |
10227 | /* expression () has merrily parsed up to the end of line, | |
10228 | or a comma - in the wrong buffer. Transfer how far | |
10229 | input_line_pointer has moved to the right buffer. */ | |
10230 | input_line_pointer = (save | |
10231 | + (input_line_pointer - gotfree_input_line) | |
10232 | + adjust); | |
10233 | free (gotfree_input_line); | |
3992d3b7 AM |
10234 | if (exp->X_op == O_constant |
10235 | || exp->X_op == O_absent | |
10236 | || exp->X_op == O_illegal | |
0398aac5 | 10237 | || exp->X_op == O_register |
3992d3b7 AM |
10238 | || exp->X_op == O_big) |
10239 | { | |
10240 | char c = *input_line_pointer; | |
10241 | *input_line_pointer = 0; | |
10242 | as_bad (_("missing or invalid expression `%s'"), save); | |
10243 | *input_line_pointer = c; | |
10244 | } | |
b9519cfe L |
10245 | else if ((got_reloc == BFD_RELOC_386_PLT32 |
10246 | || got_reloc == BFD_RELOC_X86_64_PLT32) | |
10247 | && exp->X_op != O_symbol) | |
10248 | { | |
10249 | char c = *input_line_pointer; | |
10250 | *input_line_pointer = 0; | |
10251 | as_bad (_("invalid PLT expression `%s'"), save); | |
10252 | *input_line_pointer = c; | |
10253 | } | |
f3c180ae AM |
10254 | } |
10255 | } | |
10256 | else | |
10257 | expression (exp); | |
ee86248c JB |
10258 | |
10259 | intel_syntax = -intel_syntax; | |
10260 | ||
10261 | if (intel_syntax) | |
10262 | i386_intel_simplify (exp); | |
62ebcb5c AM |
10263 | |
10264 | return got_reloc; | |
f3c180ae | 10265 | } |
f3c180ae | 10266 | |
9f32dd5b L |
10267 | static void |
10268 | signed_cons (int size) | |
6482c264 | 10269 | { |
d182319b JB |
10270 | if (flag_code == CODE_64BIT) |
10271 | cons_sign = 1; | |
10272 | cons (size); | |
10273 | cons_sign = -1; | |
6482c264 NC |
10274 | } |
10275 | ||
d182319b | 10276 | #ifdef TE_PE |
6482c264 | 10277 | static void |
7016a5d5 | 10278 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
6482c264 NC |
10279 | { |
10280 | expressionS exp; | |
10281 | ||
10282 | do | |
10283 | { | |
10284 | expression (&exp); | |
10285 | if (exp.X_op == O_symbol) | |
10286 | exp.X_op = O_secrel; | |
10287 | ||
10288 | emit_expr (&exp, 4); | |
10289 | } | |
10290 | while (*input_line_pointer++ == ','); | |
10291 | ||
10292 | input_line_pointer--; | |
10293 | demand_empty_rest_of_line (); | |
10294 | } | |
6482c264 NC |
10295 | #endif |
10296 | ||
43234a1e L |
10297 | /* Handle Vector operations. */ |
10298 | ||
10299 | static char * | |
10300 | check_VecOperations (char *op_string, char *op_end) | |
10301 | { | |
10302 | const reg_entry *mask; | |
10303 | const char *saved; | |
10304 | char *end_op; | |
10305 | ||
10306 | while (*op_string | |
10307 | && (op_end == NULL || op_string < op_end)) | |
10308 | { | |
10309 | saved = op_string; | |
10310 | if (*op_string == '{') | |
10311 | { | |
10312 | op_string++; | |
10313 | ||
10314 | /* Check broadcasts. */ | |
10315 | if (strncmp (op_string, "1to", 3) == 0) | |
10316 | { | |
10317 | int bcst_type; | |
10318 | ||
10319 | if (i.broadcast) | |
10320 | goto duplicated_vec_op; | |
10321 | ||
10322 | op_string += 3; | |
10323 | if (*op_string == '8') | |
8e6e0792 | 10324 | bcst_type = 8; |
b28d1bda | 10325 | else if (*op_string == '4') |
8e6e0792 | 10326 | bcst_type = 4; |
b28d1bda | 10327 | else if (*op_string == '2') |
8e6e0792 | 10328 | bcst_type = 2; |
43234a1e L |
10329 | else if (*op_string == '1' |
10330 | && *(op_string+1) == '6') | |
10331 | { | |
8e6e0792 | 10332 | bcst_type = 16; |
43234a1e L |
10333 | op_string++; |
10334 | } | |
10335 | else | |
10336 | { | |
10337 | as_bad (_("Unsupported broadcast: `%s'"), saved); | |
10338 | return NULL; | |
10339 | } | |
10340 | op_string++; | |
10341 | ||
10342 | broadcast_op.type = bcst_type; | |
10343 | broadcast_op.operand = this_operand; | |
1f75763a | 10344 | broadcast_op.bytes = 0; |
43234a1e L |
10345 | i.broadcast = &broadcast_op; |
10346 | } | |
10347 | /* Check masking operation. */ | |
10348 | else if ((mask = parse_register (op_string, &end_op)) != NULL) | |
10349 | { | |
8a6fb3f9 JB |
10350 | if (mask == &bad_reg) |
10351 | return NULL; | |
10352 | ||
43234a1e | 10353 | /* k0 can't be used for write mask. */ |
f74a6307 | 10354 | if (mask->reg_type.bitfield.class != RegMask || !mask->reg_num) |
43234a1e | 10355 | { |
6d2cd6b2 JB |
10356 | as_bad (_("`%s%s' can't be used for write mask"), |
10357 | register_prefix, mask->reg_name); | |
43234a1e L |
10358 | return NULL; |
10359 | } | |
10360 | ||
10361 | if (!i.mask) | |
10362 | { | |
10363 | mask_op.mask = mask; | |
10364 | mask_op.zeroing = 0; | |
10365 | mask_op.operand = this_operand; | |
10366 | i.mask = &mask_op; | |
10367 | } | |
10368 | else | |
10369 | { | |
10370 | if (i.mask->mask) | |
10371 | goto duplicated_vec_op; | |
10372 | ||
10373 | i.mask->mask = mask; | |
10374 | ||
10375 | /* Only "{z}" is allowed here. No need to check | |
10376 | zeroing mask explicitly. */ | |
10377 | if (i.mask->operand != this_operand) | |
10378 | { | |
10379 | as_bad (_("invalid write mask `%s'"), saved); | |
10380 | return NULL; | |
10381 | } | |
10382 | } | |
10383 | ||
10384 | op_string = end_op; | |
10385 | } | |
10386 | /* Check zeroing-flag for masking operation. */ | |
10387 | else if (*op_string == 'z') | |
10388 | { | |
10389 | if (!i.mask) | |
10390 | { | |
10391 | mask_op.mask = NULL; | |
10392 | mask_op.zeroing = 1; | |
10393 | mask_op.operand = this_operand; | |
10394 | i.mask = &mask_op; | |
10395 | } | |
10396 | else | |
10397 | { | |
10398 | if (i.mask->zeroing) | |
10399 | { | |
10400 | duplicated_vec_op: | |
10401 | as_bad (_("duplicated `%s'"), saved); | |
10402 | return NULL; | |
10403 | } | |
10404 | ||
10405 | i.mask->zeroing = 1; | |
10406 | ||
10407 | /* Only "{%k}" is allowed here. No need to check mask | |
10408 | register explicitly. */ | |
10409 | if (i.mask->operand != this_operand) | |
10410 | { | |
10411 | as_bad (_("invalid zeroing-masking `%s'"), | |
10412 | saved); | |
10413 | return NULL; | |
10414 | } | |
10415 | } | |
10416 | ||
10417 | op_string++; | |
10418 | } | |
10419 | else | |
10420 | goto unknown_vec_op; | |
10421 | ||
10422 | if (*op_string != '}') | |
10423 | { | |
10424 | as_bad (_("missing `}' in `%s'"), saved); | |
10425 | return NULL; | |
10426 | } | |
10427 | op_string++; | |
0ba3a731 L |
10428 | |
10429 | /* Strip whitespace since the addition of pseudo prefixes | |
10430 | changed how the scrubber treats '{'. */ | |
10431 | if (is_space_char (*op_string)) | |
10432 | ++op_string; | |
10433 | ||
43234a1e L |
10434 | continue; |
10435 | } | |
10436 | unknown_vec_op: | |
10437 | /* We don't know this one. */ | |
10438 | as_bad (_("unknown vector operation: `%s'"), saved); | |
10439 | return NULL; | |
10440 | } | |
10441 | ||
6d2cd6b2 JB |
10442 | if (i.mask && i.mask->zeroing && !i.mask->mask) |
10443 | { | |
10444 | as_bad (_("zeroing-masking only allowed with write mask")); | |
10445 | return NULL; | |
10446 | } | |
10447 | ||
43234a1e L |
10448 | return op_string; |
10449 | } | |
10450 | ||
252b5132 | 10451 | static int |
70e41ade | 10452 | i386_immediate (char *imm_start) |
252b5132 RH |
10453 | { |
10454 | char *save_input_line_pointer; | |
f3c180ae | 10455 | char *gotfree_input_line; |
252b5132 | 10456 | segT exp_seg = 0; |
47926f60 | 10457 | expressionS *exp; |
40fb9820 L |
10458 | i386_operand_type types; |
10459 | ||
0dfbf9d7 | 10460 | operand_type_set (&types, ~0); |
252b5132 RH |
10461 | |
10462 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
10463 | { | |
31b2323c L |
10464 | as_bad (_("at most %d immediate operands are allowed"), |
10465 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
10466 | return 0; |
10467 | } | |
10468 | ||
10469 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 10470 | i.op[this_operand].imms = exp; |
252b5132 RH |
10471 | |
10472 | if (is_space_char (*imm_start)) | |
10473 | ++imm_start; | |
10474 | ||
10475 | save_input_line_pointer = input_line_pointer; | |
10476 | input_line_pointer = imm_start; | |
10477 | ||
d258b828 | 10478 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
10479 | if (gotfree_input_line) |
10480 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
10481 | |
10482 | exp_seg = expression (exp); | |
10483 | ||
83183c0c | 10484 | SKIP_WHITESPACE (); |
43234a1e L |
10485 | |
10486 | /* Handle vector operations. */ | |
10487 | if (*input_line_pointer == '{') | |
10488 | { | |
10489 | input_line_pointer = check_VecOperations (input_line_pointer, | |
10490 | NULL); | |
10491 | if (input_line_pointer == NULL) | |
10492 | return 0; | |
10493 | } | |
10494 | ||
252b5132 | 10495 | if (*input_line_pointer) |
f3c180ae | 10496 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
10497 | |
10498 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 10499 | if (gotfree_input_line) |
ee86248c JB |
10500 | { |
10501 | free (gotfree_input_line); | |
10502 | ||
10503 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
10504 | exp->X_op = O_illegal; | |
10505 | } | |
10506 | ||
10507 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); | |
10508 | } | |
252b5132 | 10509 | |
ee86248c JB |
10510 | static int |
10511 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
10512 | i386_operand_type types, const char *imm_start) | |
10513 | { | |
10514 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 10515 | { |
313c53d1 L |
10516 | if (imm_start) |
10517 | as_bad (_("missing or invalid immediate expression `%s'"), | |
10518 | imm_start); | |
3992d3b7 | 10519 | return 0; |
252b5132 | 10520 | } |
3e73aa7c | 10521 | else if (exp->X_op == O_constant) |
252b5132 | 10522 | { |
47926f60 | 10523 | /* Size it properly later. */ |
40fb9820 | 10524 | i.types[this_operand].bitfield.imm64 = 1; |
13f864ae L |
10525 | /* If not 64bit, sign extend val. */ |
10526 | if (flag_code != CODE_64BIT | |
4eed87de AM |
10527 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) |
10528 | exp->X_add_number | |
10529 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 10530 | } |
4c63da97 | 10531 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 10532 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 10533 | && exp_seg != absolute_section |
47926f60 | 10534 | && exp_seg != text_section |
24eab124 AM |
10535 | && exp_seg != data_section |
10536 | && exp_seg != bss_section | |
10537 | && exp_seg != undefined_section | |
f86103b7 | 10538 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 10539 | { |
d0b47220 | 10540 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
10541 | return 0; |
10542 | } | |
10543 | #endif | |
a841bdf5 | 10544 | else if (!intel_syntax && exp_seg == reg_section) |
bb8f5920 | 10545 | { |
313c53d1 L |
10546 | if (imm_start) |
10547 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
bb8f5920 L |
10548 | return 0; |
10549 | } | |
252b5132 RH |
10550 | else |
10551 | { | |
10552 | /* This is an address. The size of the address will be | |
24eab124 | 10553 | determined later, depending on destination register, |
3e73aa7c | 10554 | suffix, or the default for the section. */ |
40fb9820 L |
10555 | i.types[this_operand].bitfield.imm8 = 1; |
10556 | i.types[this_operand].bitfield.imm16 = 1; | |
10557 | i.types[this_operand].bitfield.imm32 = 1; | |
10558 | i.types[this_operand].bitfield.imm32s = 1; | |
10559 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
10560 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
10561 | types); | |
252b5132 RH |
10562 | } |
10563 | ||
10564 | return 1; | |
10565 | } | |
10566 | ||
551c1ca1 | 10567 | static char * |
e3bb37b5 | 10568 | i386_scale (char *scale) |
252b5132 | 10569 | { |
551c1ca1 AM |
10570 | offsetT val; |
10571 | char *save = input_line_pointer; | |
252b5132 | 10572 | |
551c1ca1 AM |
10573 | input_line_pointer = scale; |
10574 | val = get_absolute_expression (); | |
10575 | ||
10576 | switch (val) | |
252b5132 | 10577 | { |
551c1ca1 | 10578 | case 1: |
252b5132 RH |
10579 | i.log2_scale_factor = 0; |
10580 | break; | |
551c1ca1 | 10581 | case 2: |
252b5132 RH |
10582 | i.log2_scale_factor = 1; |
10583 | break; | |
551c1ca1 | 10584 | case 4: |
252b5132 RH |
10585 | i.log2_scale_factor = 2; |
10586 | break; | |
551c1ca1 | 10587 | case 8: |
252b5132 RH |
10588 | i.log2_scale_factor = 3; |
10589 | break; | |
10590 | default: | |
a724f0f4 JB |
10591 | { |
10592 | char sep = *input_line_pointer; | |
10593 | ||
10594 | *input_line_pointer = '\0'; | |
10595 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
10596 | scale); | |
10597 | *input_line_pointer = sep; | |
10598 | input_line_pointer = save; | |
10599 | return NULL; | |
10600 | } | |
252b5132 | 10601 | } |
29b0f896 | 10602 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
10603 | { |
10604 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 10605 | 1 << i.log2_scale_factor); |
252b5132 | 10606 | i.log2_scale_factor = 0; |
252b5132 | 10607 | } |
551c1ca1 AM |
10608 | scale = input_line_pointer; |
10609 | input_line_pointer = save; | |
10610 | return scale; | |
252b5132 RH |
10611 | } |
10612 | ||
252b5132 | 10613 | static int |
e3bb37b5 | 10614 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 10615 | { |
29b0f896 | 10616 | expressionS *exp; |
252b5132 RH |
10617 | segT exp_seg = 0; |
10618 | char *save_input_line_pointer; | |
f3c180ae | 10619 | char *gotfree_input_line; |
40fb9820 L |
10620 | int override; |
10621 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 10622 | int ret; |
252b5132 | 10623 | |
31b2323c L |
10624 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
10625 | { | |
10626 | as_bad (_("at most %d displacement operands are allowed"), | |
10627 | MAX_MEMORY_OPERANDS); | |
10628 | return 0; | |
10629 | } | |
10630 | ||
0dfbf9d7 | 10631 | operand_type_set (&bigdisp, 0); |
6f2f06be | 10632 | if (i.jumpabsolute |
48bcea9f | 10633 | || i.types[this_operand].bitfield.baseindex |
0cfa3eb3 JB |
10634 | || (current_templates->start->opcode_modifier.jump != JUMP |
10635 | && current_templates->start->opcode_modifier.jump != JUMP_DWORD)) | |
e05278af | 10636 | { |
48bcea9f | 10637 | i386_addressing_mode (); |
e05278af | 10638 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
10639 | if (flag_code == CODE_64BIT) |
10640 | { | |
10641 | if (!override) | |
10642 | { | |
10643 | bigdisp.bitfield.disp32s = 1; | |
10644 | bigdisp.bitfield.disp64 = 1; | |
10645 | } | |
48bcea9f JB |
10646 | else |
10647 | bigdisp.bitfield.disp32 = 1; | |
40fb9820 L |
10648 | } |
10649 | else if ((flag_code == CODE_16BIT) ^ override) | |
40fb9820 | 10650 | bigdisp.bitfield.disp16 = 1; |
48bcea9f JB |
10651 | else |
10652 | bigdisp.bitfield.disp32 = 1; | |
e05278af JB |
10653 | } |
10654 | else | |
10655 | { | |
376cd056 JB |
10656 | /* For PC-relative branches, the width of the displacement may be |
10657 | dependent upon data size, but is never dependent upon address size. | |
10658 | Also make sure to not unintentionally match against a non-PC-relative | |
10659 | branch template. */ | |
10660 | static templates aux_templates; | |
10661 | const insn_template *t = current_templates->start; | |
10662 | bfd_boolean has_intel64 = FALSE; | |
10663 | ||
10664 | aux_templates.start = t; | |
10665 | while (++t < current_templates->end) | |
10666 | { | |
10667 | if (t->opcode_modifier.jump | |
10668 | != current_templates->start->opcode_modifier.jump) | |
10669 | break; | |
4b5aaf5f | 10670 | if ((t->opcode_modifier.isa64 >= INTEL64)) |
376cd056 JB |
10671 | has_intel64 = TRUE; |
10672 | } | |
10673 | if (t < current_templates->end) | |
10674 | { | |
10675 | aux_templates.end = t; | |
10676 | current_templates = &aux_templates; | |
10677 | } | |
10678 | ||
e05278af | 10679 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
10680 | if (flag_code == CODE_64BIT) |
10681 | { | |
376cd056 JB |
10682 | if ((override || i.suffix == WORD_MNEM_SUFFIX) |
10683 | && (!intel64 || !has_intel64)) | |
40fb9820 L |
10684 | bigdisp.bitfield.disp16 = 1; |
10685 | else | |
48bcea9f | 10686 | bigdisp.bitfield.disp32s = 1; |
40fb9820 L |
10687 | } |
10688 | else | |
e05278af JB |
10689 | { |
10690 | if (!override) | |
10691 | override = (i.suffix == (flag_code != CODE_16BIT | |
10692 | ? WORD_MNEM_SUFFIX | |
10693 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
10694 | bigdisp.bitfield.disp32 = 1; |
10695 | if ((flag_code == CODE_16BIT) ^ override) | |
10696 | { | |
10697 | bigdisp.bitfield.disp32 = 0; | |
10698 | bigdisp.bitfield.disp16 = 1; | |
10699 | } | |
e05278af | 10700 | } |
e05278af | 10701 | } |
c6fb90c8 L |
10702 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
10703 | bigdisp); | |
252b5132 RH |
10704 | |
10705 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 10706 | i.op[this_operand].disps = exp; |
252b5132 RH |
10707 | i.disp_operands++; |
10708 | save_input_line_pointer = input_line_pointer; | |
10709 | input_line_pointer = disp_start; | |
10710 | END_STRING_AND_SAVE (disp_end); | |
10711 | ||
10712 | #ifndef GCC_ASM_O_HACK | |
10713 | #define GCC_ASM_O_HACK 0 | |
10714 | #endif | |
10715 | #if GCC_ASM_O_HACK | |
10716 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 10717 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 10718 | && displacement_string_end[-1] == '+') |
252b5132 RH |
10719 | { |
10720 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
10721 | constraint within gcc asm statements. |
10722 | For instance: | |
10723 | ||
10724 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
10725 | __asm__ __volatile__ ( \ | |
10726 | "movw %w2,%0\n\t" \ | |
10727 | "movw %w1,2+%0\n\t" \ | |
10728 | "rorl $16,%1\n\t" \ | |
10729 | "movb %b1,4+%0\n\t" \ | |
10730 | "movb %4,5+%0\n\t" \ | |
10731 | "movb $0,6+%0\n\t" \ | |
10732 | "movb %h1,7+%0\n\t" \ | |
10733 | "rorl $16,%1" \ | |
10734 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
10735 | ||
10736 | This works great except that the output assembler ends | |
10737 | up looking a bit weird if it turns out that there is | |
10738 | no offset. You end up producing code that looks like: | |
10739 | ||
10740 | #APP | |
10741 | movw $235,(%eax) | |
10742 | movw %dx,2+(%eax) | |
10743 | rorl $16,%edx | |
10744 | movb %dl,4+(%eax) | |
10745 | movb $137,5+(%eax) | |
10746 | movb $0,6+(%eax) | |
10747 | movb %dh,7+(%eax) | |
10748 | rorl $16,%edx | |
10749 | #NO_APP | |
10750 | ||
47926f60 | 10751 | So here we provide the missing zero. */ |
24eab124 AM |
10752 | |
10753 | *displacement_string_end = '0'; | |
252b5132 RH |
10754 | } |
10755 | #endif | |
d258b828 | 10756 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
10757 | if (gotfree_input_line) |
10758 | input_line_pointer = gotfree_input_line; | |
252b5132 | 10759 | |
24eab124 | 10760 | exp_seg = expression (exp); |
252b5132 | 10761 | |
636c26b0 AM |
10762 | SKIP_WHITESPACE (); |
10763 | if (*input_line_pointer) | |
10764 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
10765 | #if GCC_ASM_O_HACK | |
10766 | RESTORE_END_STRING (disp_end + 1); | |
10767 | #endif | |
636c26b0 | 10768 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 10769 | if (gotfree_input_line) |
ee86248c JB |
10770 | { |
10771 | free (gotfree_input_line); | |
10772 | ||
10773 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
10774 | exp->X_op = O_illegal; | |
10775 | } | |
10776 | ||
10777 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
10778 | ||
10779 | RESTORE_END_STRING (disp_end); | |
10780 | ||
10781 | return ret; | |
10782 | } | |
10783 | ||
10784 | static int | |
10785 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
10786 | i386_operand_type types, const char *disp_start) | |
10787 | { | |
10788 | i386_operand_type bigdisp; | |
10789 | int ret = 1; | |
636c26b0 | 10790 | |
24eab124 AM |
10791 | /* We do this to make sure that the section symbol is in |
10792 | the symbol table. We will ultimately change the relocation | |
47926f60 | 10793 | to be relative to the beginning of the section. */ |
1ae12ab7 | 10794 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
10795 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
10796 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 10797 | { |
636c26b0 | 10798 | if (exp->X_op != O_symbol) |
3992d3b7 | 10799 | goto inv_disp; |
636c26b0 | 10800 | |
e5cb08ac | 10801 | if (S_IS_LOCAL (exp->X_add_symbol) |
c64efb4b L |
10802 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
10803 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) | |
24eab124 | 10804 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
24eab124 AM |
10805 | exp->X_op = O_subtract; |
10806 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 10807 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 10808 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
10809 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
10810 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 10811 | else |
29b0f896 | 10812 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 10813 | } |
252b5132 | 10814 | |
3992d3b7 AM |
10815 | else if (exp->X_op == O_absent |
10816 | || exp->X_op == O_illegal | |
ee86248c | 10817 | || exp->X_op == O_big) |
2daf4fd8 | 10818 | { |
3992d3b7 AM |
10819 | inv_disp: |
10820 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 10821 | disp_start); |
3992d3b7 | 10822 | ret = 0; |
2daf4fd8 AM |
10823 | } |
10824 | ||
0e1147d9 L |
10825 | else if (flag_code == CODE_64BIT |
10826 | && !i.prefix[ADDR_PREFIX] | |
10827 | && exp->X_op == O_constant) | |
10828 | { | |
10829 | /* Since displacement is signed extended to 64bit, don't allow | |
10830 | disp32 and turn off disp32s if they are out of range. */ | |
10831 | i.types[this_operand].bitfield.disp32 = 0; | |
10832 | if (!fits_in_signed_long (exp->X_add_number)) | |
10833 | { | |
10834 | i.types[this_operand].bitfield.disp32s = 0; | |
10835 | if (i.types[this_operand].bitfield.baseindex) | |
10836 | { | |
10837 | as_bad (_("0x%lx out range of signed 32bit displacement"), | |
10838 | (long) exp->X_add_number); | |
10839 | ret = 0; | |
10840 | } | |
10841 | } | |
10842 | } | |
10843 | ||
4c63da97 | 10844 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3992d3b7 AM |
10845 | else if (exp->X_op != O_constant |
10846 | && OUTPUT_FLAVOR == bfd_target_aout_flavour | |
10847 | && exp_seg != absolute_section | |
10848 | && exp_seg != text_section | |
10849 | && exp_seg != data_section | |
10850 | && exp_seg != bss_section | |
10851 | && exp_seg != undefined_section | |
10852 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 10853 | { |
d0b47220 | 10854 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 10855 | ret = 0; |
24eab124 | 10856 | } |
252b5132 | 10857 | #endif |
3956db08 | 10858 | |
48bcea9f JB |
10859 | if (current_templates->start->opcode_modifier.jump == JUMP_BYTE |
10860 | /* Constants get taken care of by optimize_disp(). */ | |
10861 | && exp->X_op != O_constant) | |
10862 | i.types[this_operand].bitfield.disp8 = 1; | |
10863 | ||
40fb9820 L |
10864 | /* Check if this is a displacement only operand. */ |
10865 | bigdisp = i.types[this_operand]; | |
10866 | bigdisp.bitfield.disp8 = 0; | |
10867 | bigdisp.bitfield.disp16 = 0; | |
10868 | bigdisp.bitfield.disp32 = 0; | |
10869 | bigdisp.bitfield.disp32s = 0; | |
10870 | bigdisp.bitfield.disp64 = 0; | |
0dfbf9d7 | 10871 | if (operand_type_all_zero (&bigdisp)) |
c6fb90c8 L |
10872 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
10873 | types); | |
3956db08 | 10874 | |
3992d3b7 | 10875 | return ret; |
252b5132 RH |
10876 | } |
10877 | ||
2abc2bec JB |
10878 | /* Return the active addressing mode, taking address override and |
10879 | registers forming the address into consideration. Update the | |
10880 | address override prefix if necessary. */ | |
47926f60 | 10881 | |
2abc2bec JB |
10882 | static enum flag_code |
10883 | i386_addressing_mode (void) | |
252b5132 | 10884 | { |
be05d201 L |
10885 | enum flag_code addr_mode; |
10886 | ||
10887 | if (i.prefix[ADDR_PREFIX]) | |
10888 | addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; | |
a23b33b3 JB |
10889 | else if (flag_code == CODE_16BIT |
10890 | && current_templates->start->cpu_flags.bitfield.cpumpx | |
10891 | /* Avoid replacing the "16-bit addressing not allowed" diagnostic | |
10892 | from md_assemble() by "is not a valid base/index expression" | |
10893 | when there is a base and/or index. */ | |
10894 | && !i.types[this_operand].bitfield.baseindex) | |
10895 | { | |
10896 | /* MPX insn memory operands with neither base nor index must be forced | |
10897 | to use 32-bit addressing in 16-bit mode. */ | |
10898 | addr_mode = CODE_32BIT; | |
10899 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
10900 | ++i.prefixes; | |
10901 | gas_assert (!i.types[this_operand].bitfield.disp16); | |
10902 | gas_assert (!i.types[this_operand].bitfield.disp32); | |
10903 | } | |
be05d201 L |
10904 | else |
10905 | { | |
10906 | addr_mode = flag_code; | |
10907 | ||
24eab124 | 10908 | #if INFER_ADDR_PREFIX |
be05d201 L |
10909 | if (i.mem_operands == 0) |
10910 | { | |
10911 | /* Infer address prefix from the first memory operand. */ | |
10912 | const reg_entry *addr_reg = i.base_reg; | |
10913 | ||
10914 | if (addr_reg == NULL) | |
10915 | addr_reg = i.index_reg; | |
eecb386c | 10916 | |
be05d201 L |
10917 | if (addr_reg) |
10918 | { | |
e968fc9b | 10919 | if (addr_reg->reg_type.bitfield.dword) |
be05d201 L |
10920 | addr_mode = CODE_32BIT; |
10921 | else if (flag_code != CODE_64BIT | |
dc821c5f | 10922 | && addr_reg->reg_type.bitfield.word) |
be05d201 L |
10923 | addr_mode = CODE_16BIT; |
10924 | ||
10925 | if (addr_mode != flag_code) | |
10926 | { | |
10927 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
10928 | i.prefixes += 1; | |
10929 | /* Change the size of any displacement too. At most one | |
10930 | of Disp16 or Disp32 is set. | |
10931 | FIXME. There doesn't seem to be any real need for | |
10932 | separate Disp16 and Disp32 flags. The same goes for | |
10933 | Imm16 and Imm32. Removing them would probably clean | |
10934 | up the code quite a lot. */ | |
10935 | if (flag_code != CODE_64BIT | |
10936 | && (i.types[this_operand].bitfield.disp16 | |
10937 | || i.types[this_operand].bitfield.disp32)) | |
10938 | i.types[this_operand] | |
10939 | = operand_type_xor (i.types[this_operand], disp16_32); | |
10940 | } | |
10941 | } | |
10942 | } | |
24eab124 | 10943 | #endif |
be05d201 L |
10944 | } |
10945 | ||
2abc2bec JB |
10946 | return addr_mode; |
10947 | } | |
10948 | ||
10949 | /* Make sure the memory operand we've been dealt is valid. | |
10950 | Return 1 on success, 0 on a failure. */ | |
10951 | ||
10952 | static int | |
10953 | i386_index_check (const char *operand_string) | |
10954 | { | |
10955 | const char *kind = "base/index"; | |
10956 | enum flag_code addr_mode = i386_addressing_mode (); | |
10957 | ||
fc0763e6 | 10958 | if (current_templates->start->opcode_modifier.isstring |
c3949f43 | 10959 | && !current_templates->start->cpu_flags.bitfield.cpupadlock |
fc0763e6 JB |
10960 | && (current_templates->end[-1].opcode_modifier.isstring |
10961 | || i.mem_operands)) | |
10962 | { | |
10963 | /* Memory operands of string insns are special in that they only allow | |
10964 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
be05d201 L |
10965 | const reg_entry *expected_reg; |
10966 | static const char *di_si[][2] = | |
10967 | { | |
10968 | { "esi", "edi" }, | |
10969 | { "si", "di" }, | |
10970 | { "rsi", "rdi" } | |
10971 | }; | |
10972 | static const char *bx[] = { "ebx", "bx", "rbx" }; | |
fc0763e6 JB |
10973 | |
10974 | kind = "string address"; | |
10975 | ||
8325cc63 | 10976 | if (current_templates->start->opcode_modifier.repprefixok) |
fc0763e6 | 10977 | { |
51c8edf6 JB |
10978 | int es_op = current_templates->end[-1].opcode_modifier.isstring |
10979 | - IS_STRING_ES_OP0; | |
10980 | int op = 0; | |
fc0763e6 | 10981 | |
51c8edf6 | 10982 | if (!current_templates->end[-1].operand_types[0].bitfield.baseindex |
fc0763e6 JB |
10983 | || ((!i.mem_operands != !intel_syntax) |
10984 | && current_templates->end[-1].operand_types[1] | |
10985 | .bitfield.baseindex)) | |
51c8edf6 JB |
10986 | op = 1; |
10987 | expected_reg = hash_find (reg_hash, di_si[addr_mode][op == es_op]); | |
fc0763e6 JB |
10988 | } |
10989 | else | |
be05d201 | 10990 | expected_reg = hash_find (reg_hash, bx[addr_mode]); |
fc0763e6 | 10991 | |
be05d201 L |
10992 | if (i.base_reg != expected_reg |
10993 | || i.index_reg | |
fc0763e6 | 10994 | || operand_type_check (i.types[this_operand], disp)) |
fc0763e6 | 10995 | { |
be05d201 L |
10996 | /* The second memory operand must have the same size as |
10997 | the first one. */ | |
10998 | if (i.mem_operands | |
10999 | && i.base_reg | |
11000 | && !((addr_mode == CODE_64BIT | |
dc821c5f | 11001 | && i.base_reg->reg_type.bitfield.qword) |
be05d201 | 11002 | || (addr_mode == CODE_32BIT |
dc821c5f JB |
11003 | ? i.base_reg->reg_type.bitfield.dword |
11004 | : i.base_reg->reg_type.bitfield.word))) | |
be05d201 L |
11005 | goto bad_address; |
11006 | ||
fc0763e6 JB |
11007 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
11008 | operand_string, | |
11009 | intel_syntax ? '[' : '(', | |
11010 | register_prefix, | |
be05d201 | 11011 | expected_reg->reg_name, |
fc0763e6 | 11012 | intel_syntax ? ']' : ')'); |
be05d201 | 11013 | return 1; |
fc0763e6 | 11014 | } |
be05d201 L |
11015 | else |
11016 | return 1; | |
11017 | ||
dc1e8a47 | 11018 | bad_address: |
be05d201 L |
11019 | as_bad (_("`%s' is not a valid %s expression"), |
11020 | operand_string, kind); | |
11021 | return 0; | |
3e73aa7c JH |
11022 | } |
11023 | else | |
11024 | { | |
be05d201 L |
11025 | if (addr_mode != CODE_16BIT) |
11026 | { | |
11027 | /* 32-bit/64-bit checks. */ | |
41eb8e88 L |
11028 | if (i.disp_encoding == disp_encoding_16bit) |
11029 | { | |
11030 | bad_disp: | |
11031 | as_bad (_("invalid `%s' prefix"), | |
11032 | addr_mode == CODE_16BIT ? "{disp32}" : "{disp16}"); | |
11033 | return 0; | |
11034 | } | |
11035 | ||
be05d201 | 11036 | if ((i.base_reg |
e968fc9b JB |
11037 | && ((addr_mode == CODE_64BIT |
11038 | ? !i.base_reg->reg_type.bitfield.qword | |
11039 | : !i.base_reg->reg_type.bitfield.dword) | |
11040 | || (i.index_reg && i.base_reg->reg_num == RegIP) | |
11041 | || i.base_reg->reg_num == RegIZ)) | |
be05d201 | 11042 | || (i.index_reg |
1b54b8d7 JB |
11043 | && !i.index_reg->reg_type.bitfield.xmmword |
11044 | && !i.index_reg->reg_type.bitfield.ymmword | |
11045 | && !i.index_reg->reg_type.bitfield.zmmword | |
be05d201 | 11046 | && ((addr_mode == CODE_64BIT |
e968fc9b JB |
11047 | ? !i.index_reg->reg_type.bitfield.qword |
11048 | : !i.index_reg->reg_type.bitfield.dword) | |
be05d201 L |
11049 | || !i.index_reg->reg_type.bitfield.baseindex))) |
11050 | goto bad_address; | |
8178be5b | 11051 | |
260cd341 | 11052 | /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */ |
8178be5b | 11053 | if (current_templates->start->base_opcode == 0xf30f1b |
260cd341 LC |
11054 | || (current_templates->start->base_opcode & ~1) == 0x0f1a |
11055 | || current_templates->start->opcode_modifier.sib == SIBMEM) | |
8178be5b JB |
11056 | { |
11057 | /* They cannot use RIP-relative addressing. */ | |
e968fc9b | 11058 | if (i.base_reg && i.base_reg->reg_num == RegIP) |
8178be5b JB |
11059 | { |
11060 | as_bad (_("`%s' cannot be used here"), operand_string); | |
11061 | return 0; | |
11062 | } | |
11063 | ||
11064 | /* bndldx and bndstx ignore their scale factor. */ | |
260cd341 | 11065 | if ((current_templates->start->base_opcode & ~1) == 0x0f1a |
8178be5b JB |
11066 | && i.log2_scale_factor) |
11067 | as_warn (_("register scaling is being ignored here")); | |
11068 | } | |
be05d201 L |
11069 | } |
11070 | else | |
3e73aa7c | 11071 | { |
be05d201 | 11072 | /* 16-bit checks. */ |
41eb8e88 L |
11073 | if (i.disp_encoding == disp_encoding_32bit) |
11074 | goto bad_disp; | |
11075 | ||
3e73aa7c | 11076 | if ((i.base_reg |
dc821c5f | 11077 | && (!i.base_reg->reg_type.bitfield.word |
40fb9820 | 11078 | || !i.base_reg->reg_type.bitfield.baseindex)) |
3e73aa7c | 11079 | || (i.index_reg |
dc821c5f | 11080 | && (!i.index_reg->reg_type.bitfield.word |
40fb9820 | 11081 | || !i.index_reg->reg_type.bitfield.baseindex |
29b0f896 AM |
11082 | || !(i.base_reg |
11083 | && i.base_reg->reg_num < 6 | |
11084 | && i.index_reg->reg_num >= 6 | |
11085 | && i.log2_scale_factor == 0)))) | |
be05d201 | 11086 | goto bad_address; |
3e73aa7c JH |
11087 | } |
11088 | } | |
be05d201 | 11089 | return 1; |
24eab124 | 11090 | } |
252b5132 | 11091 | |
43234a1e L |
11092 | /* Handle vector immediates. */ |
11093 | ||
11094 | static int | |
11095 | RC_SAE_immediate (const char *imm_start) | |
11096 | { | |
11097 | unsigned int match_found, j; | |
11098 | const char *pstr = imm_start; | |
11099 | expressionS *exp; | |
11100 | ||
11101 | if (*pstr != '{') | |
11102 | return 0; | |
11103 | ||
11104 | pstr++; | |
11105 | match_found = 0; | |
11106 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) | |
11107 | { | |
11108 | if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) | |
11109 | { | |
11110 | if (!i.rounding) | |
11111 | { | |
11112 | rc_op.type = RC_NamesTable[j].type; | |
11113 | rc_op.operand = this_operand; | |
11114 | i.rounding = &rc_op; | |
11115 | } | |
11116 | else | |
11117 | { | |
11118 | as_bad (_("duplicated `%s'"), imm_start); | |
11119 | return 0; | |
11120 | } | |
11121 | pstr += RC_NamesTable[j].len; | |
11122 | match_found = 1; | |
11123 | break; | |
11124 | } | |
11125 | } | |
11126 | if (!match_found) | |
11127 | return 0; | |
11128 | ||
11129 | if (*pstr++ != '}') | |
11130 | { | |
11131 | as_bad (_("Missing '}': '%s'"), imm_start); | |
11132 | return 0; | |
11133 | } | |
11134 | /* RC/SAE immediate string should contain nothing more. */; | |
11135 | if (*pstr != 0) | |
11136 | { | |
11137 | as_bad (_("Junk after '}': '%s'"), imm_start); | |
11138 | return 0; | |
11139 | } | |
11140 | ||
11141 | exp = &im_expressions[i.imm_operands++]; | |
11142 | i.op[this_operand].imms = exp; | |
11143 | ||
11144 | exp->X_op = O_constant; | |
11145 | exp->X_add_number = 0; | |
11146 | exp->X_add_symbol = (symbolS *) 0; | |
11147 | exp->X_op_symbol = (symbolS *) 0; | |
11148 | ||
11149 | i.types[this_operand].bitfield.imm8 = 1; | |
11150 | return 1; | |
11151 | } | |
11152 | ||
8325cc63 JB |
11153 | /* Only string instructions can have a second memory operand, so |
11154 | reduce current_templates to just those if it contains any. */ | |
11155 | static int | |
11156 | maybe_adjust_templates (void) | |
11157 | { | |
11158 | const insn_template *t; | |
11159 | ||
11160 | gas_assert (i.mem_operands == 1); | |
11161 | ||
11162 | for (t = current_templates->start; t < current_templates->end; ++t) | |
11163 | if (t->opcode_modifier.isstring) | |
11164 | break; | |
11165 | ||
11166 | if (t < current_templates->end) | |
11167 | { | |
11168 | static templates aux_templates; | |
11169 | bfd_boolean recheck; | |
11170 | ||
11171 | aux_templates.start = t; | |
11172 | for (; t < current_templates->end; ++t) | |
11173 | if (!t->opcode_modifier.isstring) | |
11174 | break; | |
11175 | aux_templates.end = t; | |
11176 | ||
11177 | /* Determine whether to re-check the first memory operand. */ | |
11178 | recheck = (aux_templates.start != current_templates->start | |
11179 | || t != current_templates->end); | |
11180 | ||
11181 | current_templates = &aux_templates; | |
11182 | ||
11183 | if (recheck) | |
11184 | { | |
11185 | i.mem_operands = 0; | |
11186 | if (i.memop1_string != NULL | |
11187 | && i386_index_check (i.memop1_string) == 0) | |
11188 | return 0; | |
11189 | i.mem_operands = 1; | |
11190 | } | |
11191 | } | |
11192 | ||
11193 | return 1; | |
11194 | } | |
11195 | ||
fc0763e6 | 11196 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 11197 | on error. */ |
252b5132 | 11198 | |
252b5132 | 11199 | static int |
a7619375 | 11200 | i386_att_operand (char *operand_string) |
252b5132 | 11201 | { |
af6bdddf AM |
11202 | const reg_entry *r; |
11203 | char *end_op; | |
24eab124 | 11204 | char *op_string = operand_string; |
252b5132 | 11205 | |
24eab124 | 11206 | if (is_space_char (*op_string)) |
252b5132 RH |
11207 | ++op_string; |
11208 | ||
24eab124 | 11209 | /* We check for an absolute prefix (differentiating, |
47926f60 | 11210 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
11211 | if (*op_string == ABSOLUTE_PREFIX) |
11212 | { | |
11213 | ++op_string; | |
11214 | if (is_space_char (*op_string)) | |
11215 | ++op_string; | |
6f2f06be | 11216 | i.jumpabsolute = TRUE; |
24eab124 | 11217 | } |
252b5132 | 11218 | |
47926f60 | 11219 | /* Check if operand is a register. */ |
4d1bb795 | 11220 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 11221 | { |
40fb9820 L |
11222 | i386_operand_type temp; |
11223 | ||
8a6fb3f9 JB |
11224 | if (r == &bad_reg) |
11225 | return 0; | |
11226 | ||
24eab124 AM |
11227 | /* Check for a segment override by searching for ':' after a |
11228 | segment register. */ | |
11229 | op_string = end_op; | |
11230 | if (is_space_char (*op_string)) | |
11231 | ++op_string; | |
00cee14f | 11232 | if (*op_string == ':' && r->reg_type.bitfield.class == SReg) |
24eab124 AM |
11233 | { |
11234 | switch (r->reg_num) | |
11235 | { | |
11236 | case 0: | |
11237 | i.seg[i.mem_operands] = &es; | |
11238 | break; | |
11239 | case 1: | |
11240 | i.seg[i.mem_operands] = &cs; | |
11241 | break; | |
11242 | case 2: | |
11243 | i.seg[i.mem_operands] = &ss; | |
11244 | break; | |
11245 | case 3: | |
11246 | i.seg[i.mem_operands] = &ds; | |
11247 | break; | |
11248 | case 4: | |
11249 | i.seg[i.mem_operands] = &fs; | |
11250 | break; | |
11251 | case 5: | |
11252 | i.seg[i.mem_operands] = &gs; | |
11253 | break; | |
11254 | } | |
252b5132 | 11255 | |
24eab124 | 11256 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
11257 | ++op_string; |
11258 | if (is_space_char (*op_string)) | |
24eab124 | 11259 | ++op_string; |
252b5132 | 11260 | |
24eab124 AM |
11261 | if (!is_digit_char (*op_string) |
11262 | && !is_identifier_char (*op_string) | |
11263 | && *op_string != '(' | |
11264 | && *op_string != ABSOLUTE_PREFIX) | |
11265 | { | |
11266 | as_bad (_("bad memory operand `%s'"), op_string); | |
11267 | return 0; | |
11268 | } | |
47926f60 | 11269 | /* Handle case of %es:*foo. */ |
24eab124 AM |
11270 | if (*op_string == ABSOLUTE_PREFIX) |
11271 | { | |
11272 | ++op_string; | |
11273 | if (is_space_char (*op_string)) | |
11274 | ++op_string; | |
6f2f06be | 11275 | i.jumpabsolute = TRUE; |
24eab124 AM |
11276 | } |
11277 | goto do_memory_reference; | |
11278 | } | |
43234a1e L |
11279 | |
11280 | /* Handle vector operations. */ | |
11281 | if (*op_string == '{') | |
11282 | { | |
11283 | op_string = check_VecOperations (op_string, NULL); | |
11284 | if (op_string == NULL) | |
11285 | return 0; | |
11286 | } | |
11287 | ||
24eab124 AM |
11288 | if (*op_string) |
11289 | { | |
d0b47220 | 11290 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
11291 | return 0; |
11292 | } | |
40fb9820 L |
11293 | temp = r->reg_type; |
11294 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
11295 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
11296 | temp); | |
7d5e4556 | 11297 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 11298 | i.op[this_operand].regs = r; |
24eab124 AM |
11299 | i.reg_operands++; |
11300 | } | |
af6bdddf AM |
11301 | else if (*op_string == REGISTER_PREFIX) |
11302 | { | |
11303 | as_bad (_("bad register name `%s'"), op_string); | |
11304 | return 0; | |
11305 | } | |
24eab124 | 11306 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 11307 | { |
24eab124 | 11308 | ++op_string; |
6f2f06be | 11309 | if (i.jumpabsolute) |
24eab124 | 11310 | { |
d0b47220 | 11311 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
11312 | return 0; |
11313 | } | |
11314 | if (!i386_immediate (op_string)) | |
11315 | return 0; | |
11316 | } | |
43234a1e L |
11317 | else if (RC_SAE_immediate (operand_string)) |
11318 | { | |
11319 | /* If it is a RC or SAE immediate, do nothing. */ | |
11320 | ; | |
11321 | } | |
24eab124 AM |
11322 | else if (is_digit_char (*op_string) |
11323 | || is_identifier_char (*op_string) | |
d02603dc | 11324 | || *op_string == '"' |
e5cb08ac | 11325 | || *op_string == '(') |
24eab124 | 11326 | { |
47926f60 | 11327 | /* This is a memory reference of some sort. */ |
af6bdddf | 11328 | char *base_string; |
252b5132 | 11329 | |
47926f60 | 11330 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
11331 | char *displacement_string_start; |
11332 | char *displacement_string_end; | |
43234a1e | 11333 | char *vop_start; |
252b5132 | 11334 | |
24eab124 | 11335 | do_memory_reference: |
8325cc63 JB |
11336 | if (i.mem_operands == 1 && !maybe_adjust_templates ()) |
11337 | return 0; | |
24eab124 | 11338 | if ((i.mem_operands == 1 |
40fb9820 | 11339 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
11340 | || i.mem_operands == 2) |
11341 | { | |
11342 | as_bad (_("too many memory references for `%s'"), | |
11343 | current_templates->start->name); | |
11344 | return 0; | |
11345 | } | |
252b5132 | 11346 | |
24eab124 AM |
11347 | /* Check for base index form. We detect the base index form by |
11348 | looking for an ')' at the end of the operand, searching | |
11349 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
11350 | after the '('. */ | |
af6bdddf | 11351 | base_string = op_string + strlen (op_string); |
c3332e24 | 11352 | |
43234a1e L |
11353 | /* Handle vector operations. */ |
11354 | vop_start = strchr (op_string, '{'); | |
11355 | if (vop_start && vop_start < base_string) | |
11356 | { | |
11357 | if (check_VecOperations (vop_start, base_string) == NULL) | |
11358 | return 0; | |
11359 | base_string = vop_start; | |
11360 | } | |
11361 | ||
af6bdddf AM |
11362 | --base_string; |
11363 | if (is_space_char (*base_string)) | |
11364 | --base_string; | |
252b5132 | 11365 | |
47926f60 | 11366 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
11367 | displacement_string_start = op_string; |
11368 | displacement_string_end = base_string + 1; | |
252b5132 | 11369 | |
24eab124 AM |
11370 | if (*base_string == ')') |
11371 | { | |
af6bdddf | 11372 | char *temp_string; |
24eab124 AM |
11373 | unsigned int parens_balanced = 1; |
11374 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 11375 | equal, so this loop will not be infinite. */ |
24eab124 AM |
11376 | do |
11377 | { | |
11378 | base_string--; | |
11379 | if (*base_string == ')') | |
11380 | parens_balanced++; | |
11381 | if (*base_string == '(') | |
11382 | parens_balanced--; | |
11383 | } | |
11384 | while (parens_balanced); | |
c3332e24 | 11385 | |
af6bdddf | 11386 | temp_string = base_string; |
c3332e24 | 11387 | |
24eab124 | 11388 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
11389 | ++base_string; |
11390 | if (is_space_char (*base_string)) | |
24eab124 | 11391 | ++base_string; |
252b5132 | 11392 | |
af6bdddf | 11393 | if (*base_string == ',' |
4eed87de AM |
11394 | || ((i.base_reg = parse_register (base_string, &end_op)) |
11395 | != NULL)) | |
252b5132 | 11396 | { |
af6bdddf | 11397 | displacement_string_end = temp_string; |
252b5132 | 11398 | |
40fb9820 | 11399 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 11400 | |
af6bdddf | 11401 | if (i.base_reg) |
24eab124 | 11402 | { |
8a6fb3f9 JB |
11403 | if (i.base_reg == &bad_reg) |
11404 | return 0; | |
24eab124 AM |
11405 | base_string = end_op; |
11406 | if (is_space_char (*base_string)) | |
11407 | ++base_string; | |
af6bdddf AM |
11408 | } |
11409 | ||
11410 | /* There may be an index reg or scale factor here. */ | |
11411 | if (*base_string == ',') | |
11412 | { | |
11413 | ++base_string; | |
11414 | if (is_space_char (*base_string)) | |
11415 | ++base_string; | |
11416 | ||
4eed87de AM |
11417 | if ((i.index_reg = parse_register (base_string, &end_op)) |
11418 | != NULL) | |
24eab124 | 11419 | { |
8a6fb3f9 JB |
11420 | if (i.index_reg == &bad_reg) |
11421 | return 0; | |
af6bdddf | 11422 | base_string = end_op; |
24eab124 AM |
11423 | if (is_space_char (*base_string)) |
11424 | ++base_string; | |
af6bdddf AM |
11425 | if (*base_string == ',') |
11426 | { | |
11427 | ++base_string; | |
11428 | if (is_space_char (*base_string)) | |
11429 | ++base_string; | |
11430 | } | |
e5cb08ac | 11431 | else if (*base_string != ')') |
af6bdddf | 11432 | { |
4eed87de AM |
11433 | as_bad (_("expecting `,' or `)' " |
11434 | "after index register in `%s'"), | |
af6bdddf AM |
11435 | operand_string); |
11436 | return 0; | |
11437 | } | |
24eab124 | 11438 | } |
af6bdddf | 11439 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 11440 | { |
f76bf5e0 L |
11441 | end_op = strchr (base_string, ','); |
11442 | if (end_op) | |
11443 | *end_op = '\0'; | |
af6bdddf | 11444 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
11445 | return 0; |
11446 | } | |
252b5132 | 11447 | |
47926f60 | 11448 | /* Check for scale factor. */ |
551c1ca1 | 11449 | if (*base_string != ')') |
af6bdddf | 11450 | { |
551c1ca1 AM |
11451 | char *end_scale = i386_scale (base_string); |
11452 | ||
11453 | if (!end_scale) | |
af6bdddf | 11454 | return 0; |
24eab124 | 11455 | |
551c1ca1 | 11456 | base_string = end_scale; |
af6bdddf AM |
11457 | if (is_space_char (*base_string)) |
11458 | ++base_string; | |
11459 | if (*base_string != ')') | |
11460 | { | |
4eed87de AM |
11461 | as_bad (_("expecting `)' " |
11462 | "after scale factor in `%s'"), | |
af6bdddf AM |
11463 | operand_string); |
11464 | return 0; | |
11465 | } | |
11466 | } | |
11467 | else if (!i.index_reg) | |
24eab124 | 11468 | { |
4eed87de AM |
11469 | as_bad (_("expecting index register or scale factor " |
11470 | "after `,'; got '%c'"), | |
af6bdddf | 11471 | *base_string); |
24eab124 AM |
11472 | return 0; |
11473 | } | |
11474 | } | |
af6bdddf | 11475 | else if (*base_string != ')') |
24eab124 | 11476 | { |
4eed87de AM |
11477 | as_bad (_("expecting `,' or `)' " |
11478 | "after base register in `%s'"), | |
af6bdddf | 11479 | operand_string); |
24eab124 AM |
11480 | return 0; |
11481 | } | |
c3332e24 | 11482 | } |
af6bdddf | 11483 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 11484 | { |
f76bf5e0 L |
11485 | end_op = strchr (base_string, ','); |
11486 | if (end_op) | |
11487 | *end_op = '\0'; | |
af6bdddf | 11488 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 11489 | return 0; |
c3332e24 | 11490 | } |
24eab124 AM |
11491 | } |
11492 | ||
11493 | /* If there's an expression beginning the operand, parse it, | |
11494 | assuming displacement_string_start and | |
11495 | displacement_string_end are meaningful. */ | |
11496 | if (displacement_string_start != displacement_string_end) | |
11497 | { | |
11498 | if (!i386_displacement (displacement_string_start, | |
11499 | displacement_string_end)) | |
11500 | return 0; | |
11501 | } | |
11502 | ||
11503 | /* Special case for (%dx) while doing input/output op. */ | |
11504 | if (i.base_reg | |
75e5731b JB |
11505 | && i.base_reg->reg_type.bitfield.instance == RegD |
11506 | && i.base_reg->reg_type.bitfield.word | |
24eab124 AM |
11507 | && i.index_reg == 0 |
11508 | && i.log2_scale_factor == 0 | |
11509 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 11510 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 11511 | { |
2fb5be8d | 11512 | i.types[this_operand] = i.base_reg->reg_type; |
24eab124 AM |
11513 | return 1; |
11514 | } | |
11515 | ||
eecb386c AM |
11516 | if (i386_index_check (operand_string) == 0) |
11517 | return 0; | |
c48dadc9 | 11518 | i.flags[this_operand] |= Operand_Mem; |
8325cc63 JB |
11519 | if (i.mem_operands == 0) |
11520 | i.memop1_string = xstrdup (operand_string); | |
24eab124 AM |
11521 | i.mem_operands++; |
11522 | } | |
11523 | else | |
ce8a8b2f AM |
11524 | { |
11525 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
11526 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
11527 | output_invalid (*op_string), | |
11528 | this_operand + 1, | |
11529 | op_string); | |
11530 | return 0; | |
11531 | } | |
47926f60 | 11532 | return 1; /* Normal return. */ |
252b5132 RH |
11533 | } |
11534 | \f | |
fa94de6b RM |
11535 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
11536 | that an rs_machine_dependent frag may reach. */ | |
11537 | ||
11538 | unsigned int | |
11539 | i386_frag_max_var (fragS *frag) | |
11540 | { | |
11541 | /* The only relaxable frags are for jumps. | |
11542 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ | |
11543 | gas_assert (frag->fr_type == rs_machine_dependent); | |
11544 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; | |
11545 | } | |
11546 | ||
b084df0b L |
11547 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11548 | static int | |
8dcea932 | 11549 | elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) |
b084df0b L |
11550 | { |
11551 | /* STT_GNU_IFUNC symbol must go through PLT. */ | |
11552 | if ((symbol_get_bfdsym (fr_symbol)->flags | |
11553 | & BSF_GNU_INDIRECT_FUNCTION) != 0) | |
11554 | return 0; | |
11555 | ||
11556 | if (!S_IS_EXTERNAL (fr_symbol)) | |
11557 | /* Symbol may be weak or local. */ | |
11558 | return !S_IS_WEAK (fr_symbol); | |
11559 | ||
8dcea932 L |
11560 | /* Global symbols with non-default visibility can't be preempted. */ |
11561 | if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) | |
11562 | return 1; | |
11563 | ||
11564 | if (fr_var != NO_RELOC) | |
11565 | switch ((enum bfd_reloc_code_real) fr_var) | |
11566 | { | |
11567 | case BFD_RELOC_386_PLT32: | |
11568 | case BFD_RELOC_X86_64_PLT32: | |
33eaf5de | 11569 | /* Symbol with PLT relocation may be preempted. */ |
8dcea932 L |
11570 | return 0; |
11571 | default: | |
11572 | abort (); | |
11573 | } | |
11574 | ||
b084df0b L |
11575 | /* Global symbols with default visibility in a shared library may be |
11576 | preempted by another definition. */ | |
8dcea932 | 11577 | return !shared; |
b084df0b L |
11578 | } |
11579 | #endif | |
11580 | ||
79d72f45 HL |
11581 | /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture |
11582 | Note also work for Skylake and Cascadelake. | |
11583 | --------------------------------------------------------------------- | |
11584 | | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND | | |
11585 | | ------ | ----------- | ------- | -------- | | |
11586 | | Jo | N | N | Y | | |
11587 | | Jno | N | N | Y | | |
11588 | | Jc/Jb | Y | N | Y | | |
11589 | | Jae/Jnb | Y | N | Y | | |
11590 | | Je/Jz | Y | Y | Y | | |
11591 | | Jne/Jnz | Y | Y | Y | | |
11592 | | Jna/Jbe | Y | N | Y | | |
11593 | | Ja/Jnbe | Y | N | Y | | |
11594 | | Js | N | N | Y | | |
11595 | | Jns | N | N | Y | | |
11596 | | Jp/Jpe | N | N | Y | | |
11597 | | Jnp/Jpo | N | N | Y | | |
11598 | | Jl/Jnge | Y | Y | Y | | |
11599 | | Jge/Jnl | Y | Y | Y | | |
11600 | | Jle/Jng | Y | Y | Y | | |
11601 | | Jg/Jnle | Y | Y | Y | | |
11602 | --------------------------------------------------------------------- */ | |
11603 | static int | |
11604 | i386_macro_fusible_p (enum mf_cmp_kind mf_cmp, enum mf_jcc_kind mf_jcc) | |
11605 | { | |
11606 | if (mf_cmp == mf_cmp_alu_cmp) | |
11607 | return ((mf_jcc >= mf_jcc_jc && mf_jcc <= mf_jcc_jna) | |
11608 | || mf_jcc == mf_jcc_jl || mf_jcc == mf_jcc_jle); | |
11609 | if (mf_cmp == mf_cmp_incdec) | |
11610 | return (mf_jcc == mf_jcc_je || mf_jcc == mf_jcc_jl | |
11611 | || mf_jcc == mf_jcc_jle); | |
11612 | if (mf_cmp == mf_cmp_test_and) | |
11613 | return 1; | |
11614 | return 0; | |
11615 | } | |
11616 | ||
e379e5f3 L |
11617 | /* Return the next non-empty frag. */ |
11618 | ||
11619 | static fragS * | |
11620 | i386_next_non_empty_frag (fragS *fragP) | |
11621 | { | |
11622 | /* There may be a frag with a ".fill 0" when there is no room in | |
11623 | the current frag for frag_grow in output_insn. */ | |
11624 | for (fragP = fragP->fr_next; | |
11625 | (fragP != NULL | |
11626 | && fragP->fr_type == rs_fill | |
11627 | && fragP->fr_fix == 0); | |
11628 | fragP = fragP->fr_next) | |
11629 | ; | |
11630 | return fragP; | |
11631 | } | |
11632 | ||
11633 | /* Return the next jcc frag after BRANCH_PADDING. */ | |
11634 | ||
11635 | static fragS * | |
79d72f45 | 11636 | i386_next_fusible_jcc_frag (fragS *maybe_cmp_fragP, fragS *pad_fragP) |
e379e5f3 | 11637 | { |
79d72f45 HL |
11638 | fragS *branch_fragP; |
11639 | if (!pad_fragP) | |
e379e5f3 L |
11640 | return NULL; |
11641 | ||
79d72f45 HL |
11642 | if (pad_fragP->fr_type == rs_machine_dependent |
11643 | && (TYPE_FROM_RELAX_STATE (pad_fragP->fr_subtype) | |
e379e5f3 L |
11644 | == BRANCH_PADDING)) |
11645 | { | |
79d72f45 HL |
11646 | branch_fragP = i386_next_non_empty_frag (pad_fragP); |
11647 | if (branch_fragP->fr_type != rs_machine_dependent) | |
e379e5f3 | 11648 | return NULL; |
79d72f45 HL |
11649 | if (TYPE_FROM_RELAX_STATE (branch_fragP->fr_subtype) == COND_JUMP |
11650 | && i386_macro_fusible_p (maybe_cmp_fragP->tc_frag_data.mf_type, | |
11651 | pad_fragP->tc_frag_data.mf_type)) | |
11652 | return branch_fragP; | |
e379e5f3 L |
11653 | } |
11654 | ||
11655 | return NULL; | |
11656 | } | |
11657 | ||
11658 | /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */ | |
11659 | ||
11660 | static void | |
11661 | i386_classify_machine_dependent_frag (fragS *fragP) | |
11662 | { | |
11663 | fragS *cmp_fragP; | |
11664 | fragS *pad_fragP; | |
11665 | fragS *branch_fragP; | |
11666 | fragS *next_fragP; | |
11667 | unsigned int max_prefix_length; | |
11668 | ||
11669 | if (fragP->tc_frag_data.classified) | |
11670 | return; | |
11671 | ||
11672 | /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert | |
11673 | FUSED_JCC_PADDING and merge BRANCH_PADDING. */ | |
11674 | for (next_fragP = fragP; | |
11675 | next_fragP != NULL; | |
11676 | next_fragP = next_fragP->fr_next) | |
11677 | { | |
11678 | next_fragP->tc_frag_data.classified = 1; | |
11679 | if (next_fragP->fr_type == rs_machine_dependent) | |
11680 | switch (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)) | |
11681 | { | |
11682 | case BRANCH_PADDING: | |
11683 | /* The BRANCH_PADDING frag must be followed by a branch | |
11684 | frag. */ | |
11685 | branch_fragP = i386_next_non_empty_frag (next_fragP); | |
11686 | next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; | |
11687 | break; | |
11688 | case FUSED_JCC_PADDING: | |
11689 | /* Check if this is a fused jcc: | |
11690 | FUSED_JCC_PADDING | |
11691 | CMP like instruction | |
11692 | BRANCH_PADDING | |
11693 | COND_JUMP | |
11694 | */ | |
11695 | cmp_fragP = i386_next_non_empty_frag (next_fragP); | |
11696 | pad_fragP = i386_next_non_empty_frag (cmp_fragP); | |
79d72f45 | 11697 | branch_fragP = i386_next_fusible_jcc_frag (next_fragP, pad_fragP); |
e379e5f3 L |
11698 | if (branch_fragP) |
11699 | { | |
11700 | /* The BRANCH_PADDING frag is merged with the | |
11701 | FUSED_JCC_PADDING frag. */ | |
11702 | next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; | |
11703 | /* CMP like instruction size. */ | |
11704 | next_fragP->tc_frag_data.cmp_size = cmp_fragP->fr_fix; | |
11705 | frag_wane (pad_fragP); | |
11706 | /* Skip to branch_fragP. */ | |
11707 | next_fragP = branch_fragP; | |
11708 | } | |
11709 | else if (next_fragP->tc_frag_data.max_prefix_length) | |
11710 | { | |
11711 | /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't | |
11712 | a fused jcc. */ | |
11713 | next_fragP->fr_subtype | |
11714 | = ENCODE_RELAX_STATE (BRANCH_PREFIX, 0); | |
11715 | next_fragP->tc_frag_data.max_bytes | |
11716 | = next_fragP->tc_frag_data.max_prefix_length; | |
11717 | /* This will be updated in the BRANCH_PREFIX scan. */ | |
11718 | next_fragP->tc_frag_data.max_prefix_length = 0; | |
11719 | } | |
11720 | else | |
11721 | frag_wane (next_fragP); | |
11722 | break; | |
11723 | } | |
11724 | } | |
11725 | ||
11726 | /* Stop if there is no BRANCH_PREFIX. */ | |
11727 | if (!align_branch_prefix_size) | |
11728 | return; | |
11729 | ||
11730 | /* Scan for BRANCH_PREFIX. */ | |
11731 | for (; fragP != NULL; fragP = fragP->fr_next) | |
11732 | { | |
11733 | if (fragP->fr_type != rs_machine_dependent | |
11734 | || (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
11735 | != BRANCH_PREFIX)) | |
11736 | continue; | |
11737 | ||
11738 | /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and | |
11739 | COND_JUMP_PREFIX. */ | |
11740 | max_prefix_length = 0; | |
11741 | for (next_fragP = fragP; | |
11742 | next_fragP != NULL; | |
11743 | next_fragP = next_fragP->fr_next) | |
11744 | { | |
11745 | if (next_fragP->fr_type == rs_fill) | |
11746 | /* Skip rs_fill frags. */ | |
11747 | continue; | |
11748 | else if (next_fragP->fr_type != rs_machine_dependent) | |
11749 | /* Stop for all other frags. */ | |
11750 | break; | |
11751 | ||
11752 | /* rs_machine_dependent frags. */ | |
11753 | if (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11754 | == BRANCH_PREFIX) | |
11755 | { | |
11756 | /* Count BRANCH_PREFIX frags. */ | |
11757 | if (max_prefix_length >= MAX_FUSED_JCC_PADDING_SIZE) | |
11758 | { | |
11759 | max_prefix_length = MAX_FUSED_JCC_PADDING_SIZE; | |
11760 | frag_wane (next_fragP); | |
11761 | } | |
11762 | else | |
11763 | max_prefix_length | |
11764 | += next_fragP->tc_frag_data.max_bytes; | |
11765 | } | |
11766 | else if ((TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11767 | == BRANCH_PADDING) | |
11768 | || (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11769 | == FUSED_JCC_PADDING)) | |
11770 | { | |
11771 | /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */ | |
11772 | fragP->tc_frag_data.u.padding_fragP = next_fragP; | |
11773 | break; | |
11774 | } | |
11775 | else | |
11776 | /* Stop for other rs_machine_dependent frags. */ | |
11777 | break; | |
11778 | } | |
11779 | ||
11780 | fragP->tc_frag_data.max_prefix_length = max_prefix_length; | |
11781 | ||
11782 | /* Skip to the next frag. */ | |
11783 | fragP = next_fragP; | |
11784 | } | |
11785 | } | |
11786 | ||
11787 | /* Compute padding size for | |
11788 | ||
11789 | FUSED_JCC_PADDING | |
11790 | CMP like instruction | |
11791 | BRANCH_PADDING | |
11792 | COND_JUMP/UNCOND_JUMP | |
11793 | ||
11794 | or | |
11795 | ||
11796 | BRANCH_PADDING | |
11797 | COND_JUMP/UNCOND_JUMP | |
11798 | */ | |
11799 | ||
11800 | static int | |
11801 | i386_branch_padding_size (fragS *fragP, offsetT address) | |
11802 | { | |
11803 | unsigned int offset, size, padding_size; | |
11804 | fragS *branch_fragP = fragP->tc_frag_data.u.branch_fragP; | |
11805 | ||
11806 | /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */ | |
11807 | if (!address) | |
11808 | address = fragP->fr_address; | |
11809 | address += fragP->fr_fix; | |
11810 | ||
11811 | /* CMP like instrunction size. */ | |
11812 | size = fragP->tc_frag_data.cmp_size; | |
11813 | ||
11814 | /* The base size of the branch frag. */ | |
11815 | size += branch_fragP->fr_fix; | |
11816 | ||
11817 | /* Add opcode and displacement bytes for the rs_machine_dependent | |
11818 | branch frag. */ | |
11819 | if (branch_fragP->fr_type == rs_machine_dependent) | |
11820 | size += md_relax_table[branch_fragP->fr_subtype].rlx_length; | |
11821 | ||
11822 | /* Check if branch is within boundary and doesn't end at the last | |
11823 | byte. */ | |
11824 | offset = address & ((1U << align_branch_power) - 1); | |
11825 | if ((offset + size) >= (1U << align_branch_power)) | |
11826 | /* Padding needed to avoid crossing boundary. */ | |
11827 | padding_size = (1U << align_branch_power) - offset; | |
11828 | else | |
11829 | /* No padding needed. */ | |
11830 | padding_size = 0; | |
11831 | ||
11832 | /* The return value may be saved in tc_frag_data.length which is | |
11833 | unsigned byte. */ | |
11834 | if (!fits_in_unsigned_byte (padding_size)) | |
11835 | abort (); | |
11836 | ||
11837 | return padding_size; | |
11838 | } | |
11839 | ||
11840 | /* i386_generic_table_relax_frag() | |
11841 | ||
11842 | Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to | |
11843 | grow/shrink padding to align branch frags. Hand others to | |
11844 | relax_frag(). */ | |
11845 | ||
11846 | long | |
11847 | i386_generic_table_relax_frag (segT segment, fragS *fragP, long stretch) | |
11848 | { | |
11849 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING | |
11850 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
11851 | { | |
11852 | long padding_size = i386_branch_padding_size (fragP, 0); | |
11853 | long grow = padding_size - fragP->tc_frag_data.length; | |
11854 | ||
11855 | /* When the BRANCH_PREFIX frag is used, the computed address | |
11856 | must match the actual address and there should be no padding. */ | |
11857 | if (fragP->tc_frag_data.padding_address | |
11858 | && (fragP->tc_frag_data.padding_address != fragP->fr_address | |
11859 | || padding_size)) | |
11860 | abort (); | |
11861 | ||
11862 | /* Update the padding size. */ | |
11863 | if (grow) | |
11864 | fragP->tc_frag_data.length = padding_size; | |
11865 | ||
11866 | return grow; | |
11867 | } | |
11868 | else if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
11869 | { | |
11870 | fragS *padding_fragP, *next_fragP; | |
11871 | long padding_size, left_size, last_size; | |
11872 | ||
11873 | padding_fragP = fragP->tc_frag_data.u.padding_fragP; | |
11874 | if (!padding_fragP) | |
11875 | /* Use the padding set by the leading BRANCH_PREFIX frag. */ | |
11876 | return (fragP->tc_frag_data.length | |
11877 | - fragP->tc_frag_data.last_length); | |
11878 | ||
11879 | /* Compute the relative address of the padding frag in the very | |
11880 | first time where the BRANCH_PREFIX frag sizes are zero. */ | |
11881 | if (!fragP->tc_frag_data.padding_address) | |
11882 | fragP->tc_frag_data.padding_address | |
11883 | = padding_fragP->fr_address - (fragP->fr_address - stretch); | |
11884 | ||
11885 | /* First update the last length from the previous interation. */ | |
11886 | left_size = fragP->tc_frag_data.prefix_length; | |
11887 | for (next_fragP = fragP; | |
11888 | next_fragP != padding_fragP; | |
11889 | next_fragP = next_fragP->fr_next) | |
11890 | if (next_fragP->fr_type == rs_machine_dependent | |
11891 | && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11892 | == BRANCH_PREFIX)) | |
11893 | { | |
11894 | if (left_size) | |
11895 | { | |
11896 | int max = next_fragP->tc_frag_data.max_bytes; | |
11897 | if (max) | |
11898 | { | |
11899 | int size; | |
11900 | if (max > left_size) | |
11901 | size = left_size; | |
11902 | else | |
11903 | size = max; | |
11904 | left_size -= size; | |
11905 | next_fragP->tc_frag_data.last_length = size; | |
11906 | } | |
11907 | } | |
11908 | else | |
11909 | next_fragP->tc_frag_data.last_length = 0; | |
11910 | } | |
11911 | ||
11912 | /* Check the padding size for the padding frag. */ | |
11913 | padding_size = i386_branch_padding_size | |
11914 | (padding_fragP, (fragP->fr_address | |
11915 | + fragP->tc_frag_data.padding_address)); | |
11916 | ||
11917 | last_size = fragP->tc_frag_data.prefix_length; | |
11918 | /* Check if there is change from the last interation. */ | |
11919 | if (padding_size == last_size) | |
11920 | { | |
11921 | /* Update the expected address of the padding frag. */ | |
11922 | padding_fragP->tc_frag_data.padding_address | |
11923 | = (fragP->fr_address + padding_size | |
11924 | + fragP->tc_frag_data.padding_address); | |
11925 | return 0; | |
11926 | } | |
11927 | ||
11928 | if (padding_size > fragP->tc_frag_data.max_prefix_length) | |
11929 | { | |
11930 | /* No padding if there is no sufficient room. Clear the | |
11931 | expected address of the padding frag. */ | |
11932 | padding_fragP->tc_frag_data.padding_address = 0; | |
11933 | padding_size = 0; | |
11934 | } | |
11935 | else | |
11936 | /* Store the expected address of the padding frag. */ | |
11937 | padding_fragP->tc_frag_data.padding_address | |
11938 | = (fragP->fr_address + padding_size | |
11939 | + fragP->tc_frag_data.padding_address); | |
11940 | ||
11941 | fragP->tc_frag_data.prefix_length = padding_size; | |
11942 | ||
11943 | /* Update the length for the current interation. */ | |
11944 | left_size = padding_size; | |
11945 | for (next_fragP = fragP; | |
11946 | next_fragP != padding_fragP; | |
11947 | next_fragP = next_fragP->fr_next) | |
11948 | if (next_fragP->fr_type == rs_machine_dependent | |
11949 | && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11950 | == BRANCH_PREFIX)) | |
11951 | { | |
11952 | if (left_size) | |
11953 | { | |
11954 | int max = next_fragP->tc_frag_data.max_bytes; | |
11955 | if (max) | |
11956 | { | |
11957 | int size; | |
11958 | if (max > left_size) | |
11959 | size = left_size; | |
11960 | else | |
11961 | size = max; | |
11962 | left_size -= size; | |
11963 | next_fragP->tc_frag_data.length = size; | |
11964 | } | |
11965 | } | |
11966 | else | |
11967 | next_fragP->tc_frag_data.length = 0; | |
11968 | } | |
11969 | ||
11970 | return (fragP->tc_frag_data.length | |
11971 | - fragP->tc_frag_data.last_length); | |
11972 | } | |
11973 | return relax_frag (segment, fragP, stretch); | |
11974 | } | |
11975 | ||
ee7fcc42 AM |
11976 | /* md_estimate_size_before_relax() |
11977 | ||
11978 | Called just before relax() for rs_machine_dependent frags. The x86 | |
11979 | assembler uses these frags to handle variable size jump | |
11980 | instructions. | |
11981 | ||
11982 | Any symbol that is now undefined will not become defined. | |
11983 | Return the correct fr_subtype in the frag. | |
11984 | Return the initial "guess for variable size of frag" to caller. | |
11985 | The guess is actually the growth beyond the fixed part. Whatever | |
11986 | we do to grow the fixed or variable part contributes to our | |
11987 | returned value. */ | |
11988 | ||
252b5132 | 11989 | int |
7016a5d5 | 11990 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 11991 | { |
e379e5f3 L |
11992 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
11993 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX | |
11994 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
11995 | { | |
11996 | i386_classify_machine_dependent_frag (fragP); | |
11997 | return fragP->tc_frag_data.length; | |
11998 | } | |
11999 | ||
252b5132 | 12000 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
12001 | check for un-relaxable symbols. On an ELF system, we can't relax |
12002 | an externally visible symbol, because it may be overridden by a | |
12003 | shared library. */ | |
12004 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 12005 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 12006 | || (IS_ELF |
8dcea932 L |
12007 | && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, |
12008 | fragP->fr_var)) | |
fbeb56a4 DK |
12009 | #endif |
12010 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 12011 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 12012 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
12013 | #endif |
12014 | ) | |
252b5132 | 12015 | { |
b98ef147 AM |
12016 | /* Symbol is undefined in this segment, or we need to keep a |
12017 | reloc so that weak symbols can be overridden. */ | |
12018 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 12019 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
12020 | unsigned char *opcode; |
12021 | int old_fr_fix; | |
f6af82bd | 12022 | |
ee7fcc42 | 12023 | if (fragP->fr_var != NO_RELOC) |
1e9cc1c2 | 12024 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
b98ef147 | 12025 | else if (size == 2) |
f6af82bd | 12026 | reloc_type = BFD_RELOC_16_PCREL; |
bd7ab16b L |
12027 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
12028 | else if (need_plt32_p (fragP->fr_symbol)) | |
12029 | reloc_type = BFD_RELOC_X86_64_PLT32; | |
12030 | #endif | |
f6af82bd AM |
12031 | else |
12032 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 12033 | |
ee7fcc42 AM |
12034 | old_fr_fix = fragP->fr_fix; |
12035 | opcode = (unsigned char *) fragP->fr_opcode; | |
12036 | ||
fddf5b5b | 12037 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 12038 | { |
fddf5b5b AM |
12039 | case UNCOND_JUMP: |
12040 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 12041 | opcode[0] = 0xe9; |
252b5132 | 12042 | fragP->fr_fix += size; |
062cd5e7 AS |
12043 | fix_new (fragP, old_fr_fix, size, |
12044 | fragP->fr_symbol, | |
12045 | fragP->fr_offset, 1, | |
12046 | reloc_type); | |
252b5132 RH |
12047 | break; |
12048 | ||
fddf5b5b | 12049 | case COND_JUMP86: |
412167cb AM |
12050 | if (size == 2 |
12051 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
12052 | { |
12053 | /* Negate the condition, and branch past an | |
12054 | unconditional jump. */ | |
12055 | opcode[0] ^= 1; | |
12056 | opcode[1] = 3; | |
12057 | /* Insert an unconditional jump. */ | |
12058 | opcode[2] = 0xe9; | |
12059 | /* We added two extra opcode bytes, and have a two byte | |
12060 | offset. */ | |
12061 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
12062 | fix_new (fragP, old_fr_fix + 2, 2, |
12063 | fragP->fr_symbol, | |
12064 | fragP->fr_offset, 1, | |
12065 | reloc_type); | |
fddf5b5b AM |
12066 | break; |
12067 | } | |
12068 | /* Fall through. */ | |
12069 | ||
12070 | case COND_JUMP: | |
412167cb AM |
12071 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
12072 | { | |
3e02c1cc AM |
12073 | fixS *fixP; |
12074 | ||
412167cb | 12075 | fragP->fr_fix += 1; |
3e02c1cc AM |
12076 | fixP = fix_new (fragP, old_fr_fix, 1, |
12077 | fragP->fr_symbol, | |
12078 | fragP->fr_offset, 1, | |
12079 | BFD_RELOC_8_PCREL); | |
12080 | fixP->fx_signed = 1; | |
412167cb AM |
12081 | break; |
12082 | } | |
93c2a809 | 12083 | |
24eab124 | 12084 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 12085 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 12086 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 12087 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
12088 | /* We've added an opcode byte. */ |
12089 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
12090 | fix_new (fragP, old_fr_fix + 1, size, |
12091 | fragP->fr_symbol, | |
12092 | fragP->fr_offset, 1, | |
12093 | reloc_type); | |
252b5132 | 12094 | break; |
fddf5b5b AM |
12095 | |
12096 | default: | |
12097 | BAD_CASE (fragP->fr_subtype); | |
12098 | break; | |
252b5132 RH |
12099 | } |
12100 | frag_wane (fragP); | |
ee7fcc42 | 12101 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 12102 | } |
93c2a809 | 12103 | |
93c2a809 AM |
12104 | /* Guess size depending on current relax state. Initially the relax |
12105 | state will correspond to a short jump and we return 1, because | |
12106 | the variable part of the frag (the branch offset) is one byte | |
12107 | long. However, we can relax a section more than once and in that | |
12108 | case we must either set fr_subtype back to the unrelaxed state, | |
12109 | or return the value for the appropriate branch. */ | |
12110 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
12111 | } |
12112 | ||
47926f60 KH |
12113 | /* Called after relax() is finished. |
12114 | ||
12115 | In: Address of frag. | |
12116 | fr_type == rs_machine_dependent. | |
12117 | fr_subtype is what the address relaxed to. | |
12118 | ||
12119 | Out: Any fixSs and constants are set up. | |
12120 | Caller will turn frag into a ".space 0". */ | |
12121 | ||
252b5132 | 12122 | void |
7016a5d5 TG |
12123 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
12124 | fragS *fragP) | |
252b5132 | 12125 | { |
29b0f896 | 12126 | unsigned char *opcode; |
252b5132 | 12127 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
12128 | offsetT target_address; |
12129 | offsetT opcode_address; | |
252b5132 | 12130 | unsigned int extension = 0; |
847f7ad4 | 12131 | offsetT displacement_from_opcode_start; |
252b5132 | 12132 | |
e379e5f3 L |
12133 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
12134 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING | |
12135 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
12136 | { | |
12137 | /* Generate nop padding. */ | |
12138 | unsigned int size = fragP->tc_frag_data.length; | |
12139 | if (size) | |
12140 | { | |
12141 | if (size > fragP->tc_frag_data.max_bytes) | |
12142 | abort (); | |
12143 | ||
12144 | if (flag_debug) | |
12145 | { | |
12146 | const char *msg; | |
12147 | const char *branch = "branch"; | |
12148 | const char *prefix = ""; | |
12149 | fragS *padding_fragP; | |
12150 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
12151 | == BRANCH_PREFIX) | |
12152 | { | |
12153 | padding_fragP = fragP->tc_frag_data.u.padding_fragP; | |
12154 | switch (fragP->tc_frag_data.default_prefix) | |
12155 | { | |
12156 | default: | |
12157 | abort (); | |
12158 | break; | |
12159 | case CS_PREFIX_OPCODE: | |
12160 | prefix = " cs"; | |
12161 | break; | |
12162 | case DS_PREFIX_OPCODE: | |
12163 | prefix = " ds"; | |
12164 | break; | |
12165 | case ES_PREFIX_OPCODE: | |
12166 | prefix = " es"; | |
12167 | break; | |
12168 | case FS_PREFIX_OPCODE: | |
12169 | prefix = " fs"; | |
12170 | break; | |
12171 | case GS_PREFIX_OPCODE: | |
12172 | prefix = " gs"; | |
12173 | break; | |
12174 | case SS_PREFIX_OPCODE: | |
12175 | prefix = " ss"; | |
12176 | break; | |
12177 | } | |
12178 | if (padding_fragP) | |
12179 | msg = _("%s:%u: add %d%s at 0x%llx to align " | |
12180 | "%s within %d-byte boundary\n"); | |
12181 | else | |
12182 | msg = _("%s:%u: add additional %d%s at 0x%llx to " | |
12183 | "align %s within %d-byte boundary\n"); | |
12184 | } | |
12185 | else | |
12186 | { | |
12187 | padding_fragP = fragP; | |
12188 | msg = _("%s:%u: add %d%s-byte nop at 0x%llx to align " | |
12189 | "%s within %d-byte boundary\n"); | |
12190 | } | |
12191 | ||
12192 | if (padding_fragP) | |
12193 | switch (padding_fragP->tc_frag_data.branch_type) | |
12194 | { | |
12195 | case align_branch_jcc: | |
12196 | branch = "jcc"; | |
12197 | break; | |
12198 | case align_branch_fused: | |
12199 | branch = "fused jcc"; | |
12200 | break; | |
12201 | case align_branch_jmp: | |
12202 | branch = "jmp"; | |
12203 | break; | |
12204 | case align_branch_call: | |
12205 | branch = "call"; | |
12206 | break; | |
12207 | case align_branch_indirect: | |
12208 | branch = "indiret branch"; | |
12209 | break; | |
12210 | case align_branch_ret: | |
12211 | branch = "ret"; | |
12212 | break; | |
12213 | default: | |
12214 | break; | |
12215 | } | |
12216 | ||
12217 | fprintf (stdout, msg, | |
12218 | fragP->fr_file, fragP->fr_line, size, prefix, | |
12219 | (long long) fragP->fr_address, branch, | |
12220 | 1 << align_branch_power); | |
12221 | } | |
12222 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
12223 | memset (fragP->fr_opcode, | |
12224 | fragP->tc_frag_data.default_prefix, size); | |
12225 | else | |
12226 | i386_generate_nops (fragP, (char *) fragP->fr_opcode, | |
12227 | size, 0); | |
12228 | fragP->fr_fix += size; | |
12229 | } | |
12230 | return; | |
12231 | } | |
12232 | ||
252b5132 RH |
12233 | opcode = (unsigned char *) fragP->fr_opcode; |
12234 | ||
47926f60 | 12235 | /* Address we want to reach in file space. */ |
252b5132 | 12236 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 12237 | |
47926f60 | 12238 | /* Address opcode resides at in file space. */ |
252b5132 RH |
12239 | opcode_address = fragP->fr_address + fragP->fr_fix; |
12240 | ||
47926f60 | 12241 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
12242 | displacement_from_opcode_start = target_address - opcode_address; |
12243 | ||
fddf5b5b | 12244 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 12245 | { |
47926f60 KH |
12246 | /* Don't have to change opcode. */ |
12247 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 12248 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
12249 | } |
12250 | else | |
12251 | { | |
12252 | if (no_cond_jump_promotion | |
12253 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
12254 | as_warn_where (fragP->fr_file, fragP->fr_line, |
12255 | _("long jump required")); | |
252b5132 | 12256 | |
fddf5b5b AM |
12257 | switch (fragP->fr_subtype) |
12258 | { | |
12259 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
12260 | extension = 4; /* 1 opcode + 4 displacement */ | |
12261 | opcode[0] = 0xe9; | |
12262 | where_to_put_displacement = &opcode[1]; | |
12263 | break; | |
252b5132 | 12264 | |
fddf5b5b AM |
12265 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
12266 | extension = 2; /* 1 opcode + 2 displacement */ | |
12267 | opcode[0] = 0xe9; | |
12268 | where_to_put_displacement = &opcode[1]; | |
12269 | break; | |
252b5132 | 12270 | |
fddf5b5b AM |
12271 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
12272 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
12273 | extension = 5; /* 2 opcode + 4 displacement */ | |
12274 | opcode[1] = opcode[0] + 0x10; | |
12275 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
12276 | where_to_put_displacement = &opcode[2]; | |
12277 | break; | |
252b5132 | 12278 | |
fddf5b5b AM |
12279 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
12280 | extension = 3; /* 2 opcode + 2 displacement */ | |
12281 | opcode[1] = opcode[0] + 0x10; | |
12282 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
12283 | where_to_put_displacement = &opcode[2]; | |
12284 | break; | |
252b5132 | 12285 | |
fddf5b5b AM |
12286 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
12287 | extension = 4; | |
12288 | opcode[0] ^= 1; | |
12289 | opcode[1] = 3; | |
12290 | opcode[2] = 0xe9; | |
12291 | where_to_put_displacement = &opcode[3]; | |
12292 | break; | |
12293 | ||
12294 | default: | |
12295 | BAD_CASE (fragP->fr_subtype); | |
12296 | break; | |
12297 | } | |
252b5132 | 12298 | } |
fddf5b5b | 12299 | |
7b81dfbb AJ |
12300 | /* If size if less then four we are sure that the operand fits, |
12301 | but if it's 4, then it could be that the displacement is larger | |
12302 | then -/+ 2GB. */ | |
12303 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
12304 | && object_64bit | |
12305 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
12306 | + ((addressT) 1 << 31)) |
12307 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
12308 | { |
12309 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
12310 | _("jump target out of range")); | |
12311 | /* Make us emit 0. */ | |
12312 | displacement_from_opcode_start = extension; | |
12313 | } | |
47926f60 | 12314 | /* Now put displacement after opcode. */ |
252b5132 RH |
12315 | md_number_to_chars ((char *) where_to_put_displacement, |
12316 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 12317 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
12318 | fragP->fr_fix += extension; |
12319 | } | |
12320 | \f | |
7016a5d5 | 12321 | /* Apply a fixup (fixP) to segment data, once it has been determined |
252b5132 RH |
12322 | by our caller that we have all the info we need to fix it up. |
12323 | ||
7016a5d5 TG |
12324 | Parameter valP is the pointer to the value of the bits. |
12325 | ||
252b5132 RH |
12326 | On the 386, immediates, displacements, and data pointers are all in |
12327 | the same (little-endian) format, so we don't need to care about which | |
12328 | we are handling. */ | |
12329 | ||
94f592af | 12330 | void |
7016a5d5 | 12331 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 12332 | { |
94f592af | 12333 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 12334 | valueT value = *valP; |
252b5132 | 12335 | |
f86103b7 | 12336 | #if !defined (TE_Mach) |
93382f6d AM |
12337 | if (fixP->fx_pcrel) |
12338 | { | |
12339 | switch (fixP->fx_r_type) | |
12340 | { | |
5865bb77 ILT |
12341 | default: |
12342 | break; | |
12343 | ||
d6ab8113 JB |
12344 | case BFD_RELOC_64: |
12345 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
12346 | break; | |
93382f6d | 12347 | case BFD_RELOC_32: |
ae8887b5 | 12348 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
12349 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
12350 | break; | |
12351 | case BFD_RELOC_16: | |
12352 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
12353 | break; | |
12354 | case BFD_RELOC_8: | |
12355 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
12356 | break; | |
12357 | } | |
12358 | } | |
252b5132 | 12359 | |
a161fe53 | 12360 | if (fixP->fx_addsy != NULL |
31312f95 | 12361 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 12362 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 | 12363 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
d258b828 | 12364 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
31312f95 | 12365 | && !use_rela_relocations) |
252b5132 | 12366 | { |
31312f95 AM |
12367 | /* This is a hack. There should be a better way to handle this. |
12368 | This covers for the fact that bfd_install_relocation will | |
12369 | subtract the current location (for partial_inplace, PC relative | |
12370 | relocations); see more below. */ | |
252b5132 | 12371 | #ifndef OBJ_AOUT |
718ddfc0 | 12372 | if (IS_ELF |
252b5132 RH |
12373 | #ifdef TE_PE |
12374 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
12375 | #endif | |
12376 | ) | |
12377 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
12378 | #endif | |
12379 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 12380 | if (IS_ELF) |
252b5132 | 12381 | { |
6539b54b | 12382 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 12383 | |
6539b54b | 12384 | if ((sym_seg == seg |
2f66722d | 12385 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 12386 | && sym_seg != absolute_section)) |
af65af87 | 12387 | && !generic_force_reloc (fixP)) |
2f66722d AM |
12388 | { |
12389 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
12390 | bfd_install_relocation subtracts them out again. I think |
12391 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
12392 | it. FIXME. */ |
12393 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
12394 | } | |
252b5132 RH |
12395 | } |
12396 | #endif | |
12397 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
12398 | /* For some reason, the PE format does not store a |
12399 | section address offset for a PC relative symbol. */ | |
12400 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 12401 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
12402 | value += md_pcrel_from (fixP); |
12403 | #endif | |
12404 | } | |
fbeb56a4 | 12405 | #if defined (OBJ_COFF) && defined (TE_PE) |
f01c1a09 NC |
12406 | if (fixP->fx_addsy != NULL |
12407 | && S_IS_WEAK (fixP->fx_addsy) | |
12408 | /* PR 16858: Do not modify weak function references. */ | |
12409 | && ! fixP->fx_pcrel) | |
fbeb56a4 | 12410 | { |
296a8689 NC |
12411 | #if !defined (TE_PEP) |
12412 | /* For x86 PE weak function symbols are neither PC-relative | |
12413 | nor do they set S_IS_FUNCTION. So the only reliable way | |
12414 | to detect them is to check the flags of their containing | |
12415 | section. */ | |
12416 | if (S_GET_SEGMENT (fixP->fx_addsy) != NULL | |
12417 | && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) | |
12418 | ; | |
12419 | else | |
12420 | #endif | |
fbeb56a4 DK |
12421 | value -= S_GET_VALUE (fixP->fx_addsy); |
12422 | } | |
12423 | #endif | |
252b5132 RH |
12424 | |
12425 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 12426 | and we must not disappoint it. */ |
252b5132 | 12427 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 12428 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
12429 | switch (fixP->fx_r_type) |
12430 | { | |
12431 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 12432 | case BFD_RELOC_X86_64_PLT32: |
b9519cfe L |
12433 | /* Make the jump instruction point to the address of the operand. |
12434 | At runtime we merely add the offset to the actual PLT entry. | |
12435 | NB: Subtract the offset size only for jump instructions. */ | |
12436 | if (fixP->fx_pcrel) | |
12437 | value = -4; | |
47926f60 | 12438 | break; |
31312f95 | 12439 | |
13ae64f3 JJ |
12440 | case BFD_RELOC_386_TLS_GD: |
12441 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 12442 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
12443 | case BFD_RELOC_386_TLS_IE: |
12444 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 12445 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
12446 | case BFD_RELOC_X86_64_TLSGD: |
12447 | case BFD_RELOC_X86_64_TLSLD: | |
12448 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 12449 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
12450 | value = 0; /* Fully resolved at runtime. No addend. */ |
12451 | /* Fallthrough */ | |
12452 | case BFD_RELOC_386_TLS_LE: | |
12453 | case BFD_RELOC_386_TLS_LDO_32: | |
12454 | case BFD_RELOC_386_TLS_LE_32: | |
12455 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 12456 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 12457 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 12458 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
12459 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
12460 | break; | |
12461 | ||
67a4f2b7 AO |
12462 | case BFD_RELOC_386_TLS_DESC_CALL: |
12463 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
12464 | value = 0; /* Fully resolved at runtime. No addend. */ | |
12465 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
12466 | fixP->fx_done = 0; | |
12467 | return; | |
12468 | ||
47926f60 KH |
12469 | case BFD_RELOC_VTABLE_INHERIT: |
12470 | case BFD_RELOC_VTABLE_ENTRY: | |
12471 | fixP->fx_done = 0; | |
94f592af | 12472 | return; |
47926f60 KH |
12473 | |
12474 | default: | |
12475 | break; | |
12476 | } | |
12477 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 12478 | *valP = value; |
f86103b7 | 12479 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 12480 | |
3e73aa7c | 12481 | /* Are we finished with this relocation now? */ |
c6682705 | 12482 | if (fixP->fx_addsy == NULL) |
3e73aa7c | 12483 | fixP->fx_done = 1; |
fbeb56a4 DK |
12484 | #if defined (OBJ_COFF) && defined (TE_PE) |
12485 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
12486 | { | |
12487 | fixP->fx_done = 0; | |
12488 | /* Remember value for tc_gen_reloc. */ | |
12489 | fixP->fx_addnumber = value; | |
12490 | /* Clear out the frag for now. */ | |
12491 | value = 0; | |
12492 | } | |
12493 | #endif | |
3e73aa7c JH |
12494 | else if (use_rela_relocations) |
12495 | { | |
12496 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
12497 | /* Remember value for tc_gen_reloc. */ |
12498 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
12499 | value = 0; |
12500 | } | |
f86103b7 | 12501 | |
94f592af | 12502 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 12503 | } |
252b5132 | 12504 | \f |
6d4af3c2 | 12505 | const char * |
499ac353 | 12506 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 12507 | { |
499ac353 NC |
12508 | /* This outputs the LITTLENUMs in REVERSE order; |
12509 | in accord with the bigendian 386. */ | |
12510 | return ieee_md_atof (type, litP, sizeP, FALSE); | |
252b5132 RH |
12511 | } |
12512 | \f | |
2d545b82 | 12513 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 12514 | |
252b5132 | 12515 | static char * |
e3bb37b5 | 12516 | output_invalid (int c) |
252b5132 | 12517 | { |
3882b010 | 12518 | if (ISPRINT (c)) |
f9f21a03 L |
12519 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
12520 | "'%c'", c); | |
252b5132 | 12521 | else |
f9f21a03 | 12522 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 12523 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
12524 | return output_invalid_buf; |
12525 | } | |
12526 | ||
8a6fb3f9 JB |
12527 | /* Verify that @r can be used in the current context. */ |
12528 | ||
12529 | static bfd_boolean check_register (const reg_entry *r) | |
12530 | { | |
12531 | if (allow_pseudo_reg) | |
12532 | return TRUE; | |
12533 | ||
12534 | if (operand_type_all_zero (&r->reg_type)) | |
12535 | return FALSE; | |
12536 | ||
12537 | if ((r->reg_type.bitfield.dword | |
12538 | || (r->reg_type.bitfield.class == SReg && r->reg_num > 3) | |
12539 | || r->reg_type.bitfield.class == RegCR | |
22e00a3f | 12540 | || r->reg_type.bitfield.class == RegDR) |
8a6fb3f9 JB |
12541 | && !cpu_arch_flags.bitfield.cpui386) |
12542 | return FALSE; | |
12543 | ||
22e00a3f JB |
12544 | if (r->reg_type.bitfield.class == RegTR |
12545 | && (flag_code == CODE_64BIT | |
12546 | || !cpu_arch_flags.bitfield.cpui386 | |
12547 | || cpu_arch_isa_flags.bitfield.cpui586 | |
12548 | || cpu_arch_isa_flags.bitfield.cpui686)) | |
12549 | return FALSE; | |
12550 | ||
8a6fb3f9 JB |
12551 | if (r->reg_type.bitfield.class == RegMMX && !cpu_arch_flags.bitfield.cpummx) |
12552 | return FALSE; | |
12553 | ||
12554 | if (!cpu_arch_flags.bitfield.cpuavx512f) | |
12555 | { | |
12556 | if (r->reg_type.bitfield.zmmword | |
12557 | || r->reg_type.bitfield.class == RegMask) | |
12558 | return FALSE; | |
12559 | ||
12560 | if (!cpu_arch_flags.bitfield.cpuavx) | |
12561 | { | |
12562 | if (r->reg_type.bitfield.ymmword) | |
12563 | return FALSE; | |
12564 | ||
12565 | if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword) | |
12566 | return FALSE; | |
12567 | } | |
12568 | } | |
12569 | ||
260cd341 LC |
12570 | if (r->reg_type.bitfield.tmmword |
12571 | && (!cpu_arch_flags.bitfield.cpuamx_tile | |
12572 | || flag_code != CODE_64BIT)) | |
12573 | return FALSE; | |
12574 | ||
8a6fb3f9 JB |
12575 | if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx) |
12576 | return FALSE; | |
12577 | ||
12578 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ | |
12579 | if (!allow_index_reg && r->reg_num == RegIZ) | |
12580 | return FALSE; | |
12581 | ||
12582 | /* Upper 16 vector registers are only available with VREX in 64bit | |
12583 | mode, and require EVEX encoding. */ | |
12584 | if (r->reg_flags & RegVRex) | |
12585 | { | |
12586 | if (!cpu_arch_flags.bitfield.cpuavx512f | |
12587 | || flag_code != CODE_64BIT) | |
12588 | return FALSE; | |
12589 | ||
da4977e0 JB |
12590 | if (i.vec_encoding == vex_encoding_default) |
12591 | i.vec_encoding = vex_encoding_evex; | |
12592 | else if (i.vec_encoding != vex_encoding_evex) | |
12593 | i.vec_encoding = vex_encoding_error; | |
8a6fb3f9 JB |
12594 | } |
12595 | ||
12596 | if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword) | |
12597 | && (!cpu_arch_flags.bitfield.cpulm || r->reg_type.bitfield.class != RegCR) | |
12598 | && flag_code != CODE_64BIT) | |
12599 | return FALSE; | |
12600 | ||
12601 | if (r->reg_type.bitfield.class == SReg && r->reg_num == RegFlat | |
12602 | && !intel_syntax) | |
12603 | return FALSE; | |
12604 | ||
12605 | return TRUE; | |
12606 | } | |
12607 | ||
af6bdddf | 12608 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
12609 | |
12610 | static const reg_entry * | |
4d1bb795 | 12611 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 12612 | { |
af6bdddf AM |
12613 | char *s = reg_string; |
12614 | char *p; | |
252b5132 RH |
12615 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
12616 | const reg_entry *r; | |
12617 | ||
12618 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
12619 | if (*s == REGISTER_PREFIX) | |
12620 | ++s; | |
12621 | ||
12622 | if (is_space_char (*s)) | |
12623 | ++s; | |
12624 | ||
12625 | p = reg_name_given; | |
af6bdddf | 12626 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
12627 | { |
12628 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
12629 | return (const reg_entry *) NULL; |
12630 | s++; | |
252b5132 RH |
12631 | } |
12632 | ||
6588847e DN |
12633 | /* For naked regs, make sure that we are not dealing with an identifier. |
12634 | This prevents confusing an identifier like `eax_var' with register | |
12635 | `eax'. */ | |
12636 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
12637 | return (const reg_entry *) NULL; | |
12638 | ||
af6bdddf | 12639 | *end_op = s; |
252b5132 RH |
12640 | |
12641 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
12642 | ||
5f47d35b | 12643 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 12644 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 12645 | { |
0e0eea78 JB |
12646 | if (!cpu_arch_flags.bitfield.cpu8087 |
12647 | && !cpu_arch_flags.bitfield.cpu287 | |
af32b722 JB |
12648 | && !cpu_arch_flags.bitfield.cpu387 |
12649 | && !allow_pseudo_reg) | |
0e0eea78 JB |
12650 | return (const reg_entry *) NULL; |
12651 | ||
5f47d35b AM |
12652 | if (is_space_char (*s)) |
12653 | ++s; | |
12654 | if (*s == '(') | |
12655 | { | |
af6bdddf | 12656 | ++s; |
5f47d35b AM |
12657 | if (is_space_char (*s)) |
12658 | ++s; | |
12659 | if (*s >= '0' && *s <= '7') | |
12660 | { | |
db557034 | 12661 | int fpr = *s - '0'; |
af6bdddf | 12662 | ++s; |
5f47d35b AM |
12663 | if (is_space_char (*s)) |
12664 | ++s; | |
12665 | if (*s == ')') | |
12666 | { | |
12667 | *end_op = s + 1; | |
1e9cc1c2 | 12668 | r = (const reg_entry *) hash_find (reg_hash, "st(0)"); |
db557034 AM |
12669 | know (r); |
12670 | return r + fpr; | |
5f47d35b | 12671 | } |
5f47d35b | 12672 | } |
47926f60 | 12673 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
12674 | return (const reg_entry *) NULL; |
12675 | } | |
12676 | } | |
12677 | ||
8a6fb3f9 | 12678 | return r && check_register (r) ? r : NULL; |
252b5132 | 12679 | } |
4d1bb795 JB |
12680 | |
12681 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
12682 | ||
12683 | static const reg_entry * | |
12684 | parse_register (char *reg_string, char **end_op) | |
12685 | { | |
12686 | const reg_entry *r; | |
12687 | ||
12688 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
12689 | r = parse_real_register (reg_string, end_op); | |
12690 | else | |
12691 | r = NULL; | |
12692 | if (!r) | |
12693 | { | |
12694 | char *save = input_line_pointer; | |
12695 | char c; | |
12696 | symbolS *symbolP; | |
12697 | ||
12698 | input_line_pointer = reg_string; | |
d02603dc | 12699 | c = get_symbol_name (®_string); |
4d1bb795 JB |
12700 | symbolP = symbol_find (reg_string); |
12701 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
12702 | { | |
12703 | const expressionS *e = symbol_get_value_expression (symbolP); | |
12704 | ||
0398aac5 | 12705 | know (e->X_op == O_register); |
4eed87de | 12706 | know (e->X_add_number >= 0 |
c3fe08fa | 12707 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 | 12708 | r = i386_regtab + e->X_add_number; |
8a6fb3f9 JB |
12709 | if (!check_register (r)) |
12710 | { | |
12711 | as_bad (_("register '%s%s' cannot be used here"), | |
12712 | register_prefix, r->reg_name); | |
12713 | r = &bad_reg; | |
12714 | } | |
4d1bb795 JB |
12715 | *end_op = input_line_pointer; |
12716 | } | |
12717 | *input_line_pointer = c; | |
12718 | input_line_pointer = save; | |
12719 | } | |
12720 | return r; | |
12721 | } | |
12722 | ||
12723 | int | |
12724 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
12725 | { | |
12726 | const reg_entry *r; | |
12727 | char *end = input_line_pointer; | |
12728 | ||
12729 | *end = *nextcharP; | |
12730 | r = parse_register (name, &input_line_pointer); | |
12731 | if (r && end <= input_line_pointer) | |
12732 | { | |
12733 | *nextcharP = *input_line_pointer; | |
12734 | *input_line_pointer = 0; | |
8a6fb3f9 JB |
12735 | if (r != &bad_reg) |
12736 | { | |
12737 | e->X_op = O_register; | |
12738 | e->X_add_number = r - i386_regtab; | |
12739 | } | |
12740 | else | |
12741 | e->X_op = O_illegal; | |
4d1bb795 JB |
12742 | return 1; |
12743 | } | |
12744 | input_line_pointer = end; | |
12745 | *end = 0; | |
ee86248c | 12746 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
12747 | } |
12748 | ||
12749 | void | |
12750 | md_operand (expressionS *e) | |
12751 | { | |
ee86248c JB |
12752 | char *end; |
12753 | const reg_entry *r; | |
4d1bb795 | 12754 | |
ee86248c JB |
12755 | switch (*input_line_pointer) |
12756 | { | |
12757 | case REGISTER_PREFIX: | |
12758 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
12759 | if (r) |
12760 | { | |
12761 | e->X_op = O_register; | |
12762 | e->X_add_number = r - i386_regtab; | |
12763 | input_line_pointer = end; | |
12764 | } | |
ee86248c JB |
12765 | break; |
12766 | ||
12767 | case '[': | |
9c2799c2 | 12768 | gas_assert (intel_syntax); |
ee86248c JB |
12769 | end = input_line_pointer++; |
12770 | expression (e); | |
12771 | if (*input_line_pointer == ']') | |
12772 | { | |
12773 | ++input_line_pointer; | |
12774 | e->X_op_symbol = make_expr_symbol (e); | |
12775 | e->X_add_symbol = NULL; | |
12776 | e->X_add_number = 0; | |
12777 | e->X_op = O_index; | |
12778 | } | |
12779 | else | |
12780 | { | |
12781 | e->X_op = O_absent; | |
12782 | input_line_pointer = end; | |
12783 | } | |
12784 | break; | |
4d1bb795 JB |
12785 | } |
12786 | } | |
12787 | ||
252b5132 | 12788 | \f |
4cc782b5 | 12789 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
b6f8c7c4 | 12790 | const char *md_shortopts = "kVQ:sqnO::"; |
252b5132 | 12791 | #else |
b6f8c7c4 | 12792 | const char *md_shortopts = "qnO::"; |
252b5132 | 12793 | #endif |
6e0b89ee | 12794 | |
3e73aa7c | 12795 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
12796 | #define OPTION_64 (OPTION_MD_BASE + 1) |
12797 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
12798 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
12799 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
12800 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
12801 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
12802 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
12803 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
bd5dea88 | 12804 | #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9) |
c0f3af97 | 12805 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 12806 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
7bab8ab5 JB |
12807 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
12808 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) | |
12809 | #define OPTION_X32 (OPTION_MD_BASE + 14) | |
7e8b059b | 12810 | #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) |
43234a1e L |
12811 | #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) |
12812 | #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) | |
167ad85b | 12813 | #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) |
d1982f93 | 12814 | #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) |
d3d3c6db | 12815 | #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) |
8dcea932 | 12816 | #define OPTION_MSHARED (OPTION_MD_BASE + 21) |
5db04b09 L |
12817 | #define OPTION_MAMD64 (OPTION_MD_BASE + 22) |
12818 | #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) | |
e4e00185 | 12819 | #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) |
b4a3a7b4 | 12820 | #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25) |
03751133 | 12821 | #define OPTION_MVEXWIG (OPTION_MD_BASE + 26) |
e379e5f3 L |
12822 | #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27) |
12823 | #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28) | |
12824 | #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29) | |
76cf450b | 12825 | #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30) |
ae531041 L |
12826 | #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31) |
12827 | #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32) | |
12828 | #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33) | |
b3b91714 | 12829 | |
99ad8390 NC |
12830 | struct option md_longopts[] = |
12831 | { | |
3e73aa7c | 12832 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 | 12833 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 12834 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c | 12835 | {"64", no_argument, NULL, OPTION_64}, |
351f65ca L |
12836 | #endif |
12837 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
570561f7 | 12838 | {"x32", no_argument, NULL, OPTION_X32}, |
8dcea932 | 12839 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
b4a3a7b4 | 12840 | {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE}, |
6e0b89ee | 12841 | #endif |
b3b91714 | 12842 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
12843 | {"march", required_argument, NULL, OPTION_MARCH}, |
12844 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
12845 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
12846 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
12847 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
12848 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
c0f3af97 | 12849 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
daf50ae7 | 12850 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
7bab8ab5 | 12851 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
539f890d | 12852 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
03751133 | 12853 | {"mvexwig", required_argument, NULL, OPTION_MVEXWIG}, |
7e8b059b | 12854 | {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, |
43234a1e L |
12855 | {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, |
12856 | {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, | |
167ad85b TG |
12857 | # if defined (TE_PE) || defined (TE_PEP) |
12858 | {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, | |
12859 | #endif | |
d1982f93 | 12860 | {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, |
e4e00185 | 12861 | {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, |
0cb4071e | 12862 | {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, |
d3d3c6db | 12863 | {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, |
e379e5f3 L |
12864 | {"malign-branch-boundary", required_argument, NULL, OPTION_MALIGN_BRANCH_BOUNDARY}, |
12865 | {"malign-branch-prefix-size", required_argument, NULL, OPTION_MALIGN_BRANCH_PREFIX_SIZE}, | |
12866 | {"malign-branch", required_argument, NULL, OPTION_MALIGN_BRANCH}, | |
76cf450b | 12867 | {"mbranches-within-32B-boundaries", no_argument, NULL, OPTION_MBRANCHES_WITH_32B_BOUNDARIES}, |
ae531041 L |
12868 | {"mlfence-after-load", required_argument, NULL, OPTION_MLFENCE_AFTER_LOAD}, |
12869 | {"mlfence-before-indirect-branch", required_argument, NULL, | |
12870 | OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH}, | |
12871 | {"mlfence-before-ret", required_argument, NULL, OPTION_MLFENCE_BEFORE_RET}, | |
5db04b09 L |
12872 | {"mamd64", no_argument, NULL, OPTION_MAMD64}, |
12873 | {"mintel64", no_argument, NULL, OPTION_MINTEL64}, | |
252b5132 RH |
12874 | {NULL, no_argument, NULL, 0} |
12875 | }; | |
12876 | size_t md_longopts_size = sizeof (md_longopts); | |
12877 | ||
12878 | int | |
17b9d67d | 12879 | md_parse_option (int c, const char *arg) |
252b5132 | 12880 | { |
91d6fa6a | 12881 | unsigned int j; |
e379e5f3 | 12882 | char *arch, *next, *saved, *type; |
9103f4f4 | 12883 | |
252b5132 RH |
12884 | switch (c) |
12885 | { | |
12b55ccc L |
12886 | case 'n': |
12887 | optimize_align_code = 0; | |
12888 | break; | |
12889 | ||
a38cf1db AM |
12890 | case 'q': |
12891 | quiet_warnings = 1; | |
252b5132 RH |
12892 | break; |
12893 | ||
12894 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
12895 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
12896 | should be emitted or not. FIXME: Not implemented. */ | |
12897 | case 'Q': | |
d4693039 JB |
12898 | if ((arg[0] != 'y' && arg[0] != 'n') || arg[1]) |
12899 | return 0; | |
252b5132 RH |
12900 | break; |
12901 | ||
12902 | /* -V: SVR4 argument to print version ID. */ | |
12903 | case 'V': | |
12904 | print_version_id (); | |
12905 | break; | |
12906 | ||
a38cf1db AM |
12907 | /* -k: Ignore for FreeBSD compatibility. */ |
12908 | case 'k': | |
252b5132 | 12909 | break; |
4cc782b5 ILT |
12910 | |
12911 | case 's': | |
12912 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 12913 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 12914 | break; |
8dcea932 L |
12915 | |
12916 | case OPTION_MSHARED: | |
12917 | shared = 1; | |
12918 | break; | |
b4a3a7b4 L |
12919 | |
12920 | case OPTION_X86_USED_NOTE: | |
12921 | if (strcasecmp (arg, "yes") == 0) | |
12922 | x86_used_note = 1; | |
12923 | else if (strcasecmp (arg, "no") == 0) | |
12924 | x86_used_note = 0; | |
12925 | else | |
12926 | as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg); | |
12927 | break; | |
12928 | ||
12929 | ||
99ad8390 | 12930 | #endif |
321098a5 | 12931 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 12932 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c JH |
12933 | case OPTION_64: |
12934 | { | |
12935 | const char **list, **l; | |
12936 | ||
3e73aa7c JH |
12937 | list = bfd_target_list (); |
12938 | for (l = list; *l != NULL; l++) | |
8620418b | 12939 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
99ad8390 NC |
12940 | || strcmp (*l, "coff-x86-64") == 0 |
12941 | || strcmp (*l, "pe-x86-64") == 0 | |
d382c579 TG |
12942 | || strcmp (*l, "pei-x86-64") == 0 |
12943 | || strcmp (*l, "mach-o-x86-64") == 0) | |
6e0b89ee AM |
12944 | { |
12945 | default_arch = "x86_64"; | |
12946 | break; | |
12947 | } | |
3e73aa7c | 12948 | if (*l == NULL) |
2b5d6a91 | 12949 | as_fatal (_("no compiled in support for x86_64")); |
3e73aa7c JH |
12950 | free (list); |
12951 | } | |
12952 | break; | |
12953 | #endif | |
252b5132 | 12954 | |
351f65ca | 12955 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570561f7 | 12956 | case OPTION_X32: |
351f65ca L |
12957 | if (IS_ELF) |
12958 | { | |
12959 | const char **list, **l; | |
12960 | ||
12961 | list = bfd_target_list (); | |
12962 | for (l = list; *l != NULL; l++) | |
12963 | if (CONST_STRNEQ (*l, "elf32-x86-64")) | |
12964 | { | |
12965 | default_arch = "x86_64:32"; | |
12966 | break; | |
12967 | } | |
12968 | if (*l == NULL) | |
2b5d6a91 | 12969 | as_fatal (_("no compiled in support for 32bit x86_64")); |
351f65ca L |
12970 | free (list); |
12971 | } | |
12972 | else | |
12973 | as_fatal (_("32bit x86_64 is only supported for ELF")); | |
12974 | break; | |
12975 | #endif | |
12976 | ||
6e0b89ee AM |
12977 | case OPTION_32: |
12978 | default_arch = "i386"; | |
12979 | break; | |
12980 | ||
b3b91714 AM |
12981 | case OPTION_DIVIDE: |
12982 | #ifdef SVR4_COMMENT_CHARS | |
12983 | { | |
12984 | char *n, *t; | |
12985 | const char *s; | |
12986 | ||
add39d23 | 12987 | n = XNEWVEC (char, strlen (i386_comment_chars) + 1); |
b3b91714 AM |
12988 | t = n; |
12989 | for (s = i386_comment_chars; *s != '\0'; s++) | |
12990 | if (*s != '/') | |
12991 | *t++ = *s; | |
12992 | *t = '\0'; | |
12993 | i386_comment_chars = n; | |
12994 | } | |
12995 | #endif | |
12996 | break; | |
12997 | ||
9103f4f4 | 12998 | case OPTION_MARCH: |
293f5f65 L |
12999 | saved = xstrdup (arg); |
13000 | arch = saved; | |
13001 | /* Allow -march=+nosse. */ | |
13002 | if (*arch == '+') | |
13003 | arch++; | |
6305a203 | 13004 | do |
9103f4f4 | 13005 | { |
6305a203 | 13006 | if (*arch == '.') |
2b5d6a91 | 13007 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
13008 | next = strchr (arch, '+'); |
13009 | if (next) | |
13010 | *next++ = '\0'; | |
91d6fa6a | 13011 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 13012 | { |
91d6fa6a | 13013 | if (strcmp (arch, cpu_arch [j].name) == 0) |
ccc9c027 | 13014 | { |
6305a203 | 13015 | /* Processor. */ |
1ded5609 JB |
13016 | if (! cpu_arch[j].flags.bitfield.cpui386) |
13017 | continue; | |
13018 | ||
91d6fa6a | 13019 | cpu_arch_name = cpu_arch[j].name; |
6305a203 | 13020 | cpu_sub_arch_name = NULL; |
91d6fa6a NC |
13021 | cpu_arch_flags = cpu_arch[j].flags; |
13022 | cpu_arch_isa = cpu_arch[j].type; | |
13023 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
6305a203 L |
13024 | if (!cpu_arch_tune_set) |
13025 | { | |
13026 | cpu_arch_tune = cpu_arch_isa; | |
13027 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
13028 | } | |
13029 | break; | |
13030 | } | |
91d6fa6a NC |
13031 | else if (*cpu_arch [j].name == '.' |
13032 | && strcmp (arch, cpu_arch [j].name + 1) == 0) | |
6305a203 | 13033 | { |
33eaf5de | 13034 | /* ISA extension. */ |
6305a203 | 13035 | i386_cpu_flags flags; |
309d3373 | 13036 | |
293f5f65 L |
13037 | flags = cpu_flags_or (cpu_arch_flags, |
13038 | cpu_arch[j].flags); | |
81486035 | 13039 | |
5b64d091 | 13040 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
6305a203 L |
13041 | { |
13042 | if (cpu_sub_arch_name) | |
13043 | { | |
13044 | char *name = cpu_sub_arch_name; | |
13045 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 13046 | cpu_arch[j].name, |
1bf57e9f | 13047 | (const char *) NULL); |
6305a203 L |
13048 | free (name); |
13049 | } | |
13050 | else | |
91d6fa6a | 13051 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
6305a203 | 13052 | cpu_arch_flags = flags; |
a586129e | 13053 | cpu_arch_isa_flags = flags; |
6305a203 | 13054 | } |
0089dace L |
13055 | else |
13056 | cpu_arch_isa_flags | |
13057 | = cpu_flags_or (cpu_arch_isa_flags, | |
13058 | cpu_arch[j].flags); | |
6305a203 | 13059 | break; |
ccc9c027 | 13060 | } |
9103f4f4 | 13061 | } |
6305a203 | 13062 | |
293f5f65 L |
13063 | if (j >= ARRAY_SIZE (cpu_arch)) |
13064 | { | |
33eaf5de | 13065 | /* Disable an ISA extension. */ |
293f5f65 L |
13066 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
13067 | if (strcmp (arch, cpu_noarch [j].name) == 0) | |
13068 | { | |
13069 | i386_cpu_flags flags; | |
13070 | ||
13071 | flags = cpu_flags_and_not (cpu_arch_flags, | |
13072 | cpu_noarch[j].flags); | |
13073 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
13074 | { | |
13075 | if (cpu_sub_arch_name) | |
13076 | { | |
13077 | char *name = cpu_sub_arch_name; | |
13078 | cpu_sub_arch_name = concat (arch, | |
13079 | (const char *) NULL); | |
13080 | free (name); | |
13081 | } | |
13082 | else | |
13083 | cpu_sub_arch_name = xstrdup (arch); | |
13084 | cpu_arch_flags = flags; | |
13085 | cpu_arch_isa_flags = flags; | |
13086 | } | |
13087 | break; | |
13088 | } | |
13089 | ||
13090 | if (j >= ARRAY_SIZE (cpu_noarch)) | |
13091 | j = ARRAY_SIZE (cpu_arch); | |
13092 | } | |
13093 | ||
91d6fa6a | 13094 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 13095 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
13096 | |
13097 | arch = next; | |
9103f4f4 | 13098 | } |
293f5f65 L |
13099 | while (next != NULL); |
13100 | free (saved); | |
9103f4f4 L |
13101 | break; |
13102 | ||
13103 | case OPTION_MTUNE: | |
13104 | if (*arg == '.') | |
2b5d6a91 | 13105 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
91d6fa6a | 13106 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 13107 | { |
91d6fa6a | 13108 | if (strcmp (arg, cpu_arch [j].name) == 0) |
9103f4f4 | 13109 | { |
ccc9c027 | 13110 | cpu_arch_tune_set = 1; |
91d6fa6a NC |
13111 | cpu_arch_tune = cpu_arch [j].type; |
13112 | cpu_arch_tune_flags = cpu_arch[j].flags; | |
9103f4f4 L |
13113 | break; |
13114 | } | |
13115 | } | |
91d6fa6a | 13116 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 13117 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
9103f4f4 L |
13118 | break; |
13119 | ||
1efbbeb4 L |
13120 | case OPTION_MMNEMONIC: |
13121 | if (strcasecmp (arg, "att") == 0) | |
13122 | intel_mnemonic = 0; | |
13123 | else if (strcasecmp (arg, "intel") == 0) | |
13124 | intel_mnemonic = 1; | |
13125 | else | |
2b5d6a91 | 13126 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
1efbbeb4 L |
13127 | break; |
13128 | ||
13129 | case OPTION_MSYNTAX: | |
13130 | if (strcasecmp (arg, "att") == 0) | |
13131 | intel_syntax = 0; | |
13132 | else if (strcasecmp (arg, "intel") == 0) | |
13133 | intel_syntax = 1; | |
13134 | else | |
2b5d6a91 | 13135 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
1efbbeb4 L |
13136 | break; |
13137 | ||
13138 | case OPTION_MINDEX_REG: | |
13139 | allow_index_reg = 1; | |
13140 | break; | |
13141 | ||
13142 | case OPTION_MNAKED_REG: | |
13143 | allow_naked_reg = 1; | |
13144 | break; | |
13145 | ||
c0f3af97 L |
13146 | case OPTION_MSSE2AVX: |
13147 | sse2avx = 1; | |
13148 | break; | |
13149 | ||
daf50ae7 L |
13150 | case OPTION_MSSE_CHECK: |
13151 | if (strcasecmp (arg, "error") == 0) | |
7bab8ab5 | 13152 | sse_check = check_error; |
daf50ae7 | 13153 | else if (strcasecmp (arg, "warning") == 0) |
7bab8ab5 | 13154 | sse_check = check_warning; |
daf50ae7 | 13155 | else if (strcasecmp (arg, "none") == 0) |
7bab8ab5 | 13156 | sse_check = check_none; |
daf50ae7 | 13157 | else |
2b5d6a91 | 13158 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
daf50ae7 L |
13159 | break; |
13160 | ||
7bab8ab5 JB |
13161 | case OPTION_MOPERAND_CHECK: |
13162 | if (strcasecmp (arg, "error") == 0) | |
13163 | operand_check = check_error; | |
13164 | else if (strcasecmp (arg, "warning") == 0) | |
13165 | operand_check = check_warning; | |
13166 | else if (strcasecmp (arg, "none") == 0) | |
13167 | operand_check = check_none; | |
13168 | else | |
13169 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); | |
13170 | break; | |
13171 | ||
539f890d L |
13172 | case OPTION_MAVXSCALAR: |
13173 | if (strcasecmp (arg, "128") == 0) | |
13174 | avxscalar = vex128; | |
13175 | else if (strcasecmp (arg, "256") == 0) | |
13176 | avxscalar = vex256; | |
13177 | else | |
2b5d6a91 | 13178 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
539f890d L |
13179 | break; |
13180 | ||
03751133 L |
13181 | case OPTION_MVEXWIG: |
13182 | if (strcmp (arg, "0") == 0) | |
40c9c8de | 13183 | vexwig = vexw0; |
03751133 | 13184 | else if (strcmp (arg, "1") == 0) |
40c9c8de | 13185 | vexwig = vexw1; |
03751133 L |
13186 | else |
13187 | as_fatal (_("invalid -mvexwig= option: `%s'"), arg); | |
13188 | break; | |
13189 | ||
7e8b059b L |
13190 | case OPTION_MADD_BND_PREFIX: |
13191 | add_bnd_prefix = 1; | |
13192 | break; | |
13193 | ||
43234a1e L |
13194 | case OPTION_MEVEXLIG: |
13195 | if (strcmp (arg, "128") == 0) | |
13196 | evexlig = evexl128; | |
13197 | else if (strcmp (arg, "256") == 0) | |
13198 | evexlig = evexl256; | |
13199 | else if (strcmp (arg, "512") == 0) | |
13200 | evexlig = evexl512; | |
13201 | else | |
13202 | as_fatal (_("invalid -mevexlig= option: `%s'"), arg); | |
13203 | break; | |
13204 | ||
d3d3c6db IT |
13205 | case OPTION_MEVEXRCIG: |
13206 | if (strcmp (arg, "rne") == 0) | |
13207 | evexrcig = rne; | |
13208 | else if (strcmp (arg, "rd") == 0) | |
13209 | evexrcig = rd; | |
13210 | else if (strcmp (arg, "ru") == 0) | |
13211 | evexrcig = ru; | |
13212 | else if (strcmp (arg, "rz") == 0) | |
13213 | evexrcig = rz; | |
13214 | else | |
13215 | as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); | |
13216 | break; | |
13217 | ||
43234a1e L |
13218 | case OPTION_MEVEXWIG: |
13219 | if (strcmp (arg, "0") == 0) | |
13220 | evexwig = evexw0; | |
13221 | else if (strcmp (arg, "1") == 0) | |
13222 | evexwig = evexw1; | |
13223 | else | |
13224 | as_fatal (_("invalid -mevexwig= option: `%s'"), arg); | |
13225 | break; | |
13226 | ||
167ad85b TG |
13227 | # if defined (TE_PE) || defined (TE_PEP) |
13228 | case OPTION_MBIG_OBJ: | |
13229 | use_big_obj = 1; | |
13230 | break; | |
13231 | #endif | |
13232 | ||
d1982f93 | 13233 | case OPTION_MOMIT_LOCK_PREFIX: |
d022bddd IT |
13234 | if (strcasecmp (arg, "yes") == 0) |
13235 | omit_lock_prefix = 1; | |
13236 | else if (strcasecmp (arg, "no") == 0) | |
13237 | omit_lock_prefix = 0; | |
13238 | else | |
13239 | as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); | |
13240 | break; | |
13241 | ||
e4e00185 AS |
13242 | case OPTION_MFENCE_AS_LOCK_ADD: |
13243 | if (strcasecmp (arg, "yes") == 0) | |
13244 | avoid_fence = 1; | |
13245 | else if (strcasecmp (arg, "no") == 0) | |
13246 | avoid_fence = 0; | |
13247 | else | |
13248 | as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); | |
13249 | break; | |
13250 | ||
ae531041 L |
13251 | case OPTION_MLFENCE_AFTER_LOAD: |
13252 | if (strcasecmp (arg, "yes") == 0) | |
13253 | lfence_after_load = 1; | |
13254 | else if (strcasecmp (arg, "no") == 0) | |
13255 | lfence_after_load = 0; | |
13256 | else | |
13257 | as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg); | |
13258 | break; | |
13259 | ||
13260 | case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH: | |
13261 | if (strcasecmp (arg, "all") == 0) | |
a09f656b | 13262 | { |
13263 | lfence_before_indirect_branch = lfence_branch_all; | |
13264 | if (lfence_before_ret == lfence_before_ret_none) | |
13265 | lfence_before_ret = lfence_before_ret_shl; | |
13266 | } | |
ae531041 L |
13267 | else if (strcasecmp (arg, "memory") == 0) |
13268 | lfence_before_indirect_branch = lfence_branch_memory; | |
13269 | else if (strcasecmp (arg, "register") == 0) | |
13270 | lfence_before_indirect_branch = lfence_branch_register; | |
13271 | else if (strcasecmp (arg, "none") == 0) | |
13272 | lfence_before_indirect_branch = lfence_branch_none; | |
13273 | else | |
13274 | as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"), | |
13275 | arg); | |
13276 | break; | |
13277 | ||
13278 | case OPTION_MLFENCE_BEFORE_RET: | |
13279 | if (strcasecmp (arg, "or") == 0) | |
13280 | lfence_before_ret = lfence_before_ret_or; | |
13281 | else if (strcasecmp (arg, "not") == 0) | |
13282 | lfence_before_ret = lfence_before_ret_not; | |
a09f656b | 13283 | else if (strcasecmp (arg, "shl") == 0 || strcasecmp (arg, "yes") == 0) |
13284 | lfence_before_ret = lfence_before_ret_shl; | |
ae531041 L |
13285 | else if (strcasecmp (arg, "none") == 0) |
13286 | lfence_before_ret = lfence_before_ret_none; | |
13287 | else | |
13288 | as_fatal (_("invalid -mlfence-before-ret= option: `%s'"), | |
13289 | arg); | |
13290 | break; | |
13291 | ||
0cb4071e L |
13292 | case OPTION_MRELAX_RELOCATIONS: |
13293 | if (strcasecmp (arg, "yes") == 0) | |
13294 | generate_relax_relocations = 1; | |
13295 | else if (strcasecmp (arg, "no") == 0) | |
13296 | generate_relax_relocations = 0; | |
13297 | else | |
13298 | as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); | |
13299 | break; | |
13300 | ||
e379e5f3 L |
13301 | case OPTION_MALIGN_BRANCH_BOUNDARY: |
13302 | { | |
13303 | char *end; | |
13304 | long int align = strtoul (arg, &end, 0); | |
13305 | if (*end == '\0') | |
13306 | { | |
13307 | if (align == 0) | |
13308 | { | |
13309 | align_branch_power = 0; | |
13310 | break; | |
13311 | } | |
13312 | else if (align >= 16) | |
13313 | { | |
13314 | int align_power; | |
13315 | for (align_power = 0; | |
13316 | (align & 1) == 0; | |
13317 | align >>= 1, align_power++) | |
13318 | continue; | |
13319 | /* Limit alignment power to 31. */ | |
13320 | if (align == 1 && align_power < 32) | |
13321 | { | |
13322 | align_branch_power = align_power; | |
13323 | break; | |
13324 | } | |
13325 | } | |
13326 | } | |
13327 | as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg); | |
13328 | } | |
13329 | break; | |
13330 | ||
13331 | case OPTION_MALIGN_BRANCH_PREFIX_SIZE: | |
13332 | { | |
13333 | char *end; | |
13334 | int align = strtoul (arg, &end, 0); | |
13335 | /* Some processors only support 5 prefixes. */ | |
13336 | if (*end == '\0' && align >= 0 && align < 6) | |
13337 | { | |
13338 | align_branch_prefix_size = align; | |
13339 | break; | |
13340 | } | |
13341 | as_fatal (_("invalid -malign-branch-prefix-size= value: %s"), | |
13342 | arg); | |
13343 | } | |
13344 | break; | |
13345 | ||
13346 | case OPTION_MALIGN_BRANCH: | |
13347 | align_branch = 0; | |
13348 | saved = xstrdup (arg); | |
13349 | type = saved; | |
13350 | do | |
13351 | { | |
13352 | next = strchr (type, '+'); | |
13353 | if (next) | |
13354 | *next++ = '\0'; | |
13355 | if (strcasecmp (type, "jcc") == 0) | |
13356 | align_branch |= align_branch_jcc_bit; | |
13357 | else if (strcasecmp (type, "fused") == 0) | |
13358 | align_branch |= align_branch_fused_bit; | |
13359 | else if (strcasecmp (type, "jmp") == 0) | |
13360 | align_branch |= align_branch_jmp_bit; | |
13361 | else if (strcasecmp (type, "call") == 0) | |
13362 | align_branch |= align_branch_call_bit; | |
13363 | else if (strcasecmp (type, "ret") == 0) | |
13364 | align_branch |= align_branch_ret_bit; | |
13365 | else if (strcasecmp (type, "indirect") == 0) | |
13366 | align_branch |= align_branch_indirect_bit; | |
13367 | else | |
13368 | as_fatal (_("invalid -malign-branch= option: `%s'"), arg); | |
13369 | type = next; | |
13370 | } | |
13371 | while (next != NULL); | |
13372 | free (saved); | |
13373 | break; | |
13374 | ||
76cf450b L |
13375 | case OPTION_MBRANCHES_WITH_32B_BOUNDARIES: |
13376 | align_branch_power = 5; | |
13377 | align_branch_prefix_size = 5; | |
13378 | align_branch = (align_branch_jcc_bit | |
13379 | | align_branch_fused_bit | |
13380 | | align_branch_jmp_bit); | |
13381 | break; | |
13382 | ||
5db04b09 | 13383 | case OPTION_MAMD64: |
4b5aaf5f | 13384 | isa64 = amd64; |
5db04b09 L |
13385 | break; |
13386 | ||
13387 | case OPTION_MINTEL64: | |
4b5aaf5f | 13388 | isa64 = intel64; |
5db04b09 L |
13389 | break; |
13390 | ||
b6f8c7c4 L |
13391 | case 'O': |
13392 | if (arg == NULL) | |
13393 | { | |
13394 | optimize = 1; | |
13395 | /* Turn off -Os. */ | |
13396 | optimize_for_space = 0; | |
13397 | } | |
13398 | else if (*arg == 's') | |
13399 | { | |
13400 | optimize_for_space = 1; | |
13401 | /* Turn on all encoding optimizations. */ | |
41fd2579 | 13402 | optimize = INT_MAX; |
b6f8c7c4 L |
13403 | } |
13404 | else | |
13405 | { | |
13406 | optimize = atoi (arg); | |
13407 | /* Turn off -Os. */ | |
13408 | optimize_for_space = 0; | |
13409 | } | |
13410 | break; | |
13411 | ||
252b5132 RH |
13412 | default: |
13413 | return 0; | |
13414 | } | |
13415 | return 1; | |
13416 | } | |
13417 | ||
8a2c8fef L |
13418 | #define MESSAGE_TEMPLATE \ |
13419 | " " | |
13420 | ||
293f5f65 L |
13421 | static char * |
13422 | output_message (FILE *stream, char *p, char *message, char *start, | |
13423 | int *left_p, const char *name, int len) | |
13424 | { | |
13425 | int size = sizeof (MESSAGE_TEMPLATE); | |
13426 | int left = *left_p; | |
13427 | ||
13428 | /* Reserve 2 spaces for ", " or ",\0" */ | |
13429 | left -= len + 2; | |
13430 | ||
13431 | /* Check if there is any room. */ | |
13432 | if (left >= 0) | |
13433 | { | |
13434 | if (p != start) | |
13435 | { | |
13436 | *p++ = ','; | |
13437 | *p++ = ' '; | |
13438 | } | |
13439 | p = mempcpy (p, name, len); | |
13440 | } | |
13441 | else | |
13442 | { | |
13443 | /* Output the current message now and start a new one. */ | |
13444 | *p++ = ','; | |
13445 | *p = '\0'; | |
13446 | fprintf (stream, "%s\n", message); | |
13447 | p = start; | |
13448 | left = size - (start - message) - len - 2; | |
13449 | ||
13450 | gas_assert (left >= 0); | |
13451 | ||
13452 | p = mempcpy (p, name, len); | |
13453 | } | |
13454 | ||
13455 | *left_p = left; | |
13456 | return p; | |
13457 | } | |
13458 | ||
8a2c8fef | 13459 | static void |
1ded5609 | 13460 | show_arch (FILE *stream, int ext, int check) |
8a2c8fef L |
13461 | { |
13462 | static char message[] = MESSAGE_TEMPLATE; | |
13463 | char *start = message + 27; | |
13464 | char *p; | |
13465 | int size = sizeof (MESSAGE_TEMPLATE); | |
13466 | int left; | |
13467 | const char *name; | |
13468 | int len; | |
13469 | unsigned int j; | |
13470 | ||
13471 | p = start; | |
13472 | left = size - (start - message); | |
13473 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) | |
13474 | { | |
13475 | /* Should it be skipped? */ | |
13476 | if (cpu_arch [j].skip) | |
13477 | continue; | |
13478 | ||
13479 | name = cpu_arch [j].name; | |
13480 | len = cpu_arch [j].len; | |
13481 | if (*name == '.') | |
13482 | { | |
13483 | /* It is an extension. Skip if we aren't asked to show it. */ | |
13484 | if (ext) | |
13485 | { | |
13486 | name++; | |
13487 | len--; | |
13488 | } | |
13489 | else | |
13490 | continue; | |
13491 | } | |
13492 | else if (ext) | |
13493 | { | |
13494 | /* It is an processor. Skip if we show only extension. */ | |
13495 | continue; | |
13496 | } | |
1ded5609 JB |
13497 | else if (check && ! cpu_arch[j].flags.bitfield.cpui386) |
13498 | { | |
13499 | /* It is an impossible processor - skip. */ | |
13500 | continue; | |
13501 | } | |
8a2c8fef | 13502 | |
293f5f65 | 13503 | p = output_message (stream, p, message, start, &left, name, len); |
8a2c8fef L |
13504 | } |
13505 | ||
293f5f65 L |
13506 | /* Display disabled extensions. */ |
13507 | if (ext) | |
13508 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) | |
13509 | { | |
13510 | name = cpu_noarch [j].name; | |
13511 | len = cpu_noarch [j].len; | |
13512 | p = output_message (stream, p, message, start, &left, name, | |
13513 | len); | |
13514 | } | |
13515 | ||
8a2c8fef L |
13516 | *p = '\0'; |
13517 | fprintf (stream, "%s\n", message); | |
13518 | } | |
13519 | ||
252b5132 | 13520 | void |
8a2c8fef | 13521 | md_show_usage (FILE *stream) |
252b5132 | 13522 | { |
4cc782b5 ILT |
13523 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
13524 | fprintf (stream, _("\ | |
d4693039 | 13525 | -Qy, -Qn ignored\n\ |
a38cf1db | 13526 | -V print assembler version number\n\ |
b3b91714 AM |
13527 | -k ignored\n")); |
13528 | #endif | |
13529 | fprintf (stream, _("\ | |
12b55ccc | 13530 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
13531 | -q quieten some warnings\n")); |
13532 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13533 | fprintf (stream, _("\ | |
a38cf1db | 13534 | -s ignored\n")); |
b3b91714 | 13535 | #endif |
d7f449c0 L |
13536 | #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
13537 | || defined (TE_PE) || defined (TE_PEP)) | |
751d281c | 13538 | fprintf (stream, _("\ |
570561f7 | 13539 | --32/--64/--x32 generate 32bit/64bit/x32 code\n")); |
751d281c | 13540 | #endif |
b3b91714 AM |
13541 | #ifdef SVR4_COMMENT_CHARS |
13542 | fprintf (stream, _("\ | |
13543 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
13544 | #else |
13545 | fprintf (stream, _("\ | |
b3b91714 | 13546 | --divide ignored\n")); |
4cc782b5 | 13547 | #endif |
9103f4f4 | 13548 | fprintf (stream, _("\ |
6305a203 | 13549 | -march=CPU[,+EXTENSION...]\n\ |
8a2c8fef | 13550 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
1ded5609 | 13551 | show_arch (stream, 0, 1); |
8a2c8fef L |
13552 | fprintf (stream, _("\ |
13553 | EXTENSION is combination of:\n")); | |
1ded5609 | 13554 | show_arch (stream, 1, 0); |
6305a203 | 13555 | fprintf (stream, _("\ |
8a2c8fef | 13556 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
1ded5609 | 13557 | show_arch (stream, 0, 0); |
ba104c83 | 13558 | fprintf (stream, _("\ |
c0f3af97 L |
13559 | -msse2avx encode SSE instructions with VEX prefix\n")); |
13560 | fprintf (stream, _("\ | |
7c5c05ef | 13561 | -msse-check=[none|error|warning] (default: warning)\n\ |
daf50ae7 L |
13562 | check SSE instructions\n")); |
13563 | fprintf (stream, _("\ | |
7c5c05ef | 13564 | -moperand-check=[none|error|warning] (default: warning)\n\ |
7bab8ab5 JB |
13565 | check operand combinations for validity\n")); |
13566 | fprintf (stream, _("\ | |
7c5c05ef L |
13567 | -mavxscalar=[128|256] (default: 128)\n\ |
13568 | encode scalar AVX instructions with specific vector\n\ | |
539f890d L |
13569 | length\n")); |
13570 | fprintf (stream, _("\ | |
03751133 L |
13571 | -mvexwig=[0|1] (default: 0)\n\ |
13572 | encode VEX instructions with specific VEX.W value\n\ | |
13573 | for VEX.W bit ignored instructions\n")); | |
13574 | fprintf (stream, _("\ | |
7c5c05ef L |
13575 | -mevexlig=[128|256|512] (default: 128)\n\ |
13576 | encode scalar EVEX instructions with specific vector\n\ | |
43234a1e L |
13577 | length\n")); |
13578 | fprintf (stream, _("\ | |
7c5c05ef L |
13579 | -mevexwig=[0|1] (default: 0)\n\ |
13580 | encode EVEX instructions with specific EVEX.W value\n\ | |
43234a1e L |
13581 | for EVEX.W bit ignored instructions\n")); |
13582 | fprintf (stream, _("\ | |
7c5c05ef | 13583 | -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\ |
d3d3c6db IT |
13584 | encode EVEX instructions with specific EVEX.RC value\n\ |
13585 | for SAE-only ignored instructions\n")); | |
13586 | fprintf (stream, _("\ | |
7c5c05ef L |
13587 | -mmnemonic=[att|intel] ")); |
13588 | if (SYSV386_COMPAT) | |
13589 | fprintf (stream, _("(default: att)\n")); | |
13590 | else | |
13591 | fprintf (stream, _("(default: intel)\n")); | |
13592 | fprintf (stream, _("\ | |
13593 | use AT&T/Intel mnemonic\n")); | |
ba104c83 | 13594 | fprintf (stream, _("\ |
7c5c05ef L |
13595 | -msyntax=[att|intel] (default: att)\n\ |
13596 | use AT&T/Intel syntax\n")); | |
ba104c83 L |
13597 | fprintf (stream, _("\ |
13598 | -mindex-reg support pseudo index registers\n")); | |
13599 | fprintf (stream, _("\ | |
13600 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
13601 | fprintf (stream, _("\ | |
7e8b059b | 13602 | -madd-bnd-prefix add BND prefix for all valid branches\n")); |
b4a3a7b4 | 13603 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8dcea932 L |
13604 | fprintf (stream, _("\ |
13605 | -mshared disable branch optimization for shared code\n")); | |
b4a3a7b4 L |
13606 | fprintf (stream, _("\ |
13607 | -mx86-used-note=[no|yes] ")); | |
13608 | if (DEFAULT_X86_USED_NOTE) | |
13609 | fprintf (stream, _("(default: yes)\n")); | |
13610 | else | |
13611 | fprintf (stream, _("(default: no)\n")); | |
13612 | fprintf (stream, _("\ | |
13613 | generate x86 used ISA and feature properties\n")); | |
13614 | #endif | |
13615 | #if defined (TE_PE) || defined (TE_PEP) | |
167ad85b TG |
13616 | fprintf (stream, _("\ |
13617 | -mbig-obj generate big object files\n")); | |
13618 | #endif | |
d022bddd | 13619 | fprintf (stream, _("\ |
7c5c05ef | 13620 | -momit-lock-prefix=[no|yes] (default: no)\n\ |
d022bddd | 13621 | strip all lock prefixes\n")); |
5db04b09 | 13622 | fprintf (stream, _("\ |
7c5c05ef | 13623 | -mfence-as-lock-add=[no|yes] (default: no)\n\ |
e4e00185 AS |
13624 | encode lfence, mfence and sfence as\n\ |
13625 | lock addl $0x0, (%%{re}sp)\n")); | |
13626 | fprintf (stream, _("\ | |
7c5c05ef L |
13627 | -mrelax-relocations=[no|yes] ")); |
13628 | if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS) | |
13629 | fprintf (stream, _("(default: yes)\n")); | |
13630 | else | |
13631 | fprintf (stream, _("(default: no)\n")); | |
13632 | fprintf (stream, _("\ | |
0cb4071e L |
13633 | generate relax relocations\n")); |
13634 | fprintf (stream, _("\ | |
e379e5f3 L |
13635 | -malign-branch-boundary=NUM (default: 0)\n\ |
13636 | align branches within NUM byte boundary\n")); | |
13637 | fprintf (stream, _("\ | |
13638 | -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\ | |
13639 | TYPE is combination of jcc, fused, jmp, call, ret,\n\ | |
13640 | indirect\n\ | |
13641 | specify types of branches to align\n")); | |
13642 | fprintf (stream, _("\ | |
13643 | -malign-branch-prefix-size=NUM (default: 5)\n\ | |
13644 | align branches with NUM prefixes per instruction\n")); | |
13645 | fprintf (stream, _("\ | |
76cf450b L |
13646 | -mbranches-within-32B-boundaries\n\ |
13647 | align branches within 32 byte boundary\n")); | |
13648 | fprintf (stream, _("\ | |
ae531041 L |
13649 | -mlfence-after-load=[no|yes] (default: no)\n\ |
13650 | generate lfence after load\n")); | |
13651 | fprintf (stream, _("\ | |
13652 | -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\ | |
13653 | generate lfence before indirect near branch\n")); | |
13654 | fprintf (stream, _("\ | |
a09f656b | 13655 | -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\ |
ae531041 L |
13656 | generate lfence before ret\n")); |
13657 | fprintf (stream, _("\ | |
7c5c05ef | 13658 | -mamd64 accept only AMD64 ISA [default]\n")); |
5db04b09 L |
13659 | fprintf (stream, _("\ |
13660 | -mintel64 accept only Intel64 ISA\n")); | |
252b5132 RH |
13661 | } |
13662 | ||
3e73aa7c | 13663 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 13664 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 13665 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
13666 | |
13667 | /* Pick the target format to use. */ | |
13668 | ||
47926f60 | 13669 | const char * |
e3bb37b5 | 13670 | i386_target_format (void) |
252b5132 | 13671 | { |
351f65ca L |
13672 | if (!strncmp (default_arch, "x86_64", 6)) |
13673 | { | |
13674 | update_code_flag (CODE_64BIT, 1); | |
13675 | if (default_arch[6] == '\0') | |
7f56bc95 | 13676 | x86_elf_abi = X86_64_ABI; |
351f65ca | 13677 | else |
7f56bc95 | 13678 | x86_elf_abi = X86_64_X32_ABI; |
351f65ca | 13679 | } |
3e73aa7c | 13680 | else if (!strcmp (default_arch, "i386")) |
78f12dd3 | 13681 | update_code_flag (CODE_32BIT, 1); |
5197d474 L |
13682 | else if (!strcmp (default_arch, "iamcu")) |
13683 | { | |
13684 | update_code_flag (CODE_32BIT, 1); | |
13685 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
13686 | { | |
13687 | static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; | |
13688 | cpu_arch_name = "iamcu"; | |
13689 | cpu_sub_arch_name = NULL; | |
13690 | cpu_arch_flags = iamcu_flags; | |
13691 | cpu_arch_isa = PROCESSOR_IAMCU; | |
13692 | cpu_arch_isa_flags = iamcu_flags; | |
13693 | if (!cpu_arch_tune_set) | |
13694 | { | |
13695 | cpu_arch_tune = cpu_arch_isa; | |
13696 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
13697 | } | |
13698 | } | |
8d471ec1 | 13699 | else if (cpu_arch_isa != PROCESSOR_IAMCU) |
5197d474 L |
13700 | as_fatal (_("Intel MCU doesn't support `%s' architecture"), |
13701 | cpu_arch_name); | |
13702 | } | |
3e73aa7c | 13703 | else |
2b5d6a91 | 13704 | as_fatal (_("unknown architecture")); |
89507696 JB |
13705 | |
13706 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) | |
13707 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
13708 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) | |
13709 | cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
13710 | ||
252b5132 RH |
13711 | switch (OUTPUT_FLAVOR) |
13712 | { | |
9384f2ff | 13713 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
4c63da97 | 13714 | case bfd_target_aout_flavour: |
47926f60 | 13715 | return AOUT_TARGET_FORMAT; |
4c63da97 | 13716 | #endif |
9384f2ff AM |
13717 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
13718 | # if defined (TE_PE) || defined (TE_PEP) | |
13719 | case bfd_target_coff_flavour: | |
167ad85b TG |
13720 | if (flag_code == CODE_64BIT) |
13721 | return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; | |
13722 | else | |
251dae91 | 13723 | return use_big_obj ? "pe-bigobj-i386" : "pe-i386"; |
9384f2ff | 13724 | # elif defined (TE_GO32) |
0561d57c JK |
13725 | case bfd_target_coff_flavour: |
13726 | return "coff-go32"; | |
9384f2ff | 13727 | # else |
252b5132 RH |
13728 | case bfd_target_coff_flavour: |
13729 | return "coff-i386"; | |
9384f2ff | 13730 | # endif |
4c63da97 | 13731 | #endif |
3e73aa7c | 13732 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 13733 | case bfd_target_elf_flavour: |
3e73aa7c | 13734 | { |
351f65ca L |
13735 | const char *format; |
13736 | ||
13737 | switch (x86_elf_abi) | |
4fa24527 | 13738 | { |
351f65ca L |
13739 | default: |
13740 | format = ELF_TARGET_FORMAT; | |
e379e5f3 L |
13741 | #ifndef TE_SOLARIS |
13742 | tls_get_addr = "___tls_get_addr"; | |
13743 | #endif | |
351f65ca | 13744 | break; |
7f56bc95 | 13745 | case X86_64_ABI: |
351f65ca | 13746 | use_rela_relocations = 1; |
4fa24527 | 13747 | object_64bit = 1; |
e379e5f3 L |
13748 | #ifndef TE_SOLARIS |
13749 | tls_get_addr = "__tls_get_addr"; | |
13750 | #endif | |
351f65ca L |
13751 | format = ELF_TARGET_FORMAT64; |
13752 | break; | |
7f56bc95 | 13753 | case X86_64_X32_ABI: |
4fa24527 | 13754 | use_rela_relocations = 1; |
351f65ca | 13755 | object_64bit = 1; |
e379e5f3 L |
13756 | #ifndef TE_SOLARIS |
13757 | tls_get_addr = "__tls_get_addr"; | |
13758 | #endif | |
862be3fb | 13759 | disallow_64bit_reloc = 1; |
351f65ca L |
13760 | format = ELF_TARGET_FORMAT32; |
13761 | break; | |
4fa24527 | 13762 | } |
3632d14b | 13763 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 13764 | { |
7f56bc95 | 13765 | if (x86_elf_abi != X86_64_ABI) |
8a9036a4 L |
13766 | as_fatal (_("Intel L1OM is 64bit only")); |
13767 | return ELF_TARGET_L1OM_FORMAT; | |
13768 | } | |
b49f93f6 | 13769 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
7a9068fe L |
13770 | { |
13771 | if (x86_elf_abi != X86_64_ABI) | |
13772 | as_fatal (_("Intel K1OM is 64bit only")); | |
13773 | return ELF_TARGET_K1OM_FORMAT; | |
13774 | } | |
81486035 L |
13775 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
13776 | { | |
13777 | if (x86_elf_abi != I386_ABI) | |
13778 | as_fatal (_("Intel MCU is 32bit only")); | |
13779 | return ELF_TARGET_IAMCU_FORMAT; | |
13780 | } | |
8a9036a4 | 13781 | else |
351f65ca | 13782 | return format; |
3e73aa7c | 13783 | } |
e57f8c65 TG |
13784 | #endif |
13785 | #if defined (OBJ_MACH_O) | |
13786 | case bfd_target_mach_o_flavour: | |
d382c579 TG |
13787 | if (flag_code == CODE_64BIT) |
13788 | { | |
13789 | use_rela_relocations = 1; | |
13790 | object_64bit = 1; | |
13791 | return "mach-o-x86-64"; | |
13792 | } | |
13793 | else | |
13794 | return "mach-o-i386"; | |
4c63da97 | 13795 | #endif |
252b5132 RH |
13796 | default: |
13797 | abort (); | |
13798 | return NULL; | |
13799 | } | |
13800 | } | |
13801 | ||
47926f60 | 13802 | #endif /* OBJ_MAYBE_ more than one */ |
252b5132 | 13803 | \f |
252b5132 | 13804 | symbolS * |
7016a5d5 | 13805 | md_undefined_symbol (char *name) |
252b5132 | 13806 | { |
18dc2407 ILT |
13807 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
13808 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
13809 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
13810 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
13811 | { |
13812 | if (!GOT_symbol) | |
13813 | { | |
13814 | if (symbol_find (name)) | |
13815 | as_bad (_("GOT already in symbol table")); | |
13816 | GOT_symbol = symbol_new (name, undefined_section, | |
13817 | (valueT) 0, &zero_address_frag); | |
13818 | }; | |
13819 | return GOT_symbol; | |
13820 | } | |
252b5132 RH |
13821 | return 0; |
13822 | } | |
13823 | ||
13824 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 13825 | |
252b5132 | 13826 | valueT |
7016a5d5 | 13827 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 | 13828 | { |
4c63da97 AM |
13829 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
13830 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
13831 | { | |
13832 | /* For a.out, force the section size to be aligned. If we don't do | |
13833 | this, BFD will align it for us, but it will not write out the | |
13834 | final bytes of the section. This may be a bug in BFD, but it is | |
13835 | easier to fix it here since that is how the other a.out targets | |
13836 | work. */ | |
13837 | int align; | |
13838 | ||
fd361982 | 13839 | align = bfd_section_alignment (segment); |
8d3842cd | 13840 | size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); |
4c63da97 | 13841 | } |
252b5132 RH |
13842 | #endif |
13843 | ||
13844 | return size; | |
13845 | } | |
13846 | ||
13847 | /* On the i386, PC-relative offsets are relative to the start of the | |
13848 | next instruction. That is, the address of the offset, plus its | |
13849 | size, since the offset is always the last part of the insn. */ | |
13850 | ||
13851 | long | |
e3bb37b5 | 13852 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
13853 | { |
13854 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
13855 | } | |
13856 | ||
13857 | #ifndef I386COFF | |
13858 | ||
13859 | static void | |
e3bb37b5 | 13860 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13861 | { |
29b0f896 | 13862 | int temp; |
252b5132 | 13863 | |
8a75718c JB |
13864 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
13865 | if (IS_ELF) | |
13866 | obj_elf_section_change_hook (); | |
13867 | #endif | |
252b5132 RH |
13868 | temp = get_absolute_expression (); |
13869 | subseg_set (bss_section, (subsegT) temp); | |
13870 | demand_empty_rest_of_line (); | |
13871 | } | |
13872 | ||
13873 | #endif | |
13874 | ||
e379e5f3 L |
13875 | /* Remember constant directive. */ |
13876 | ||
13877 | void | |
13878 | i386_cons_align (int ignore ATTRIBUTE_UNUSED) | |
13879 | { | |
13880 | if (last_insn.kind != last_insn_directive | |
13881 | && (bfd_section_flags (now_seg) & SEC_CODE)) | |
13882 | { | |
13883 | last_insn.seg = now_seg; | |
13884 | last_insn.kind = last_insn_directive; | |
13885 | last_insn.name = "constant directive"; | |
13886 | last_insn.file = as_where (&last_insn.line); | |
ae531041 L |
13887 | if (lfence_before_ret != lfence_before_ret_none) |
13888 | { | |
13889 | if (lfence_before_indirect_branch != lfence_branch_none) | |
13890 | as_warn (_("constant directive skips -mlfence-before-ret " | |
13891 | "and -mlfence-before-indirect-branch")); | |
13892 | else | |
13893 | as_warn (_("constant directive skips -mlfence-before-ret")); | |
13894 | } | |
13895 | else if (lfence_before_indirect_branch != lfence_branch_none) | |
13896 | as_warn (_("constant directive skips -mlfence-before-indirect-branch")); | |
e379e5f3 L |
13897 | } |
13898 | } | |
13899 | ||
252b5132 | 13900 | void |
e3bb37b5 | 13901 | i386_validate_fix (fixS *fixp) |
252b5132 | 13902 | { |
02a86693 | 13903 | if (fixp->fx_subsy) |
252b5132 | 13904 | { |
02a86693 | 13905 | if (fixp->fx_subsy == GOT_symbol) |
23df1078 | 13906 | { |
02a86693 L |
13907 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
13908 | { | |
13909 | if (!object_64bit) | |
13910 | abort (); | |
13911 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13912 | if (fixp->fx_tcbit2) | |
56ceb5b5 L |
13913 | fixp->fx_r_type = (fixp->fx_tcbit |
13914 | ? BFD_RELOC_X86_64_REX_GOTPCRELX | |
13915 | : BFD_RELOC_X86_64_GOTPCRELX); | |
02a86693 L |
13916 | else |
13917 | #endif | |
13918 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
13919 | } | |
d6ab8113 | 13920 | else |
02a86693 L |
13921 | { |
13922 | if (!object_64bit) | |
13923 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
13924 | else | |
13925 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
13926 | } | |
13927 | fixp->fx_subsy = 0; | |
23df1078 | 13928 | } |
252b5132 | 13929 | } |
02a86693 | 13930 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
2585b7a5 | 13931 | else |
02a86693 | 13932 | { |
2585b7a5 L |
13933 | /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol |
13934 | to section. Since PLT32 relocation must be against symbols, | |
13935 | turn such PLT32 relocation into PC32 relocation. */ | |
13936 | if (fixp->fx_addsy | |
13937 | && (fixp->fx_r_type == BFD_RELOC_386_PLT32 | |
13938 | || fixp->fx_r_type == BFD_RELOC_X86_64_PLT32) | |
13939 | && symbol_section_p (fixp->fx_addsy)) | |
13940 | fixp->fx_r_type = BFD_RELOC_32_PCREL; | |
13941 | if (!object_64bit) | |
13942 | { | |
13943 | if (fixp->fx_r_type == BFD_RELOC_386_GOT32 | |
13944 | && fixp->fx_tcbit2) | |
13945 | fixp->fx_r_type = BFD_RELOC_386_GOT32X; | |
13946 | } | |
02a86693 L |
13947 | } |
13948 | #endif | |
252b5132 RH |
13949 | } |
13950 | ||
252b5132 | 13951 | arelent * |
7016a5d5 | 13952 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
13953 | { |
13954 | arelent *rel; | |
13955 | bfd_reloc_code_real_type code; | |
13956 | ||
13957 | switch (fixp->fx_r_type) | |
13958 | { | |
8ce3d284 | 13959 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
13960 | case BFD_RELOC_SIZE32: |
13961 | case BFD_RELOC_SIZE64: | |
13962 | if (S_IS_DEFINED (fixp->fx_addsy) | |
13963 | && !S_IS_EXTERNAL (fixp->fx_addsy)) | |
13964 | { | |
13965 | /* Resolve size relocation against local symbol to size of | |
13966 | the symbol plus addend. */ | |
13967 | valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset; | |
13968 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 | |
13969 | && !fits_in_unsigned_long (value)) | |
13970 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13971 | _("symbol size computation overflow")); | |
13972 | fixp->fx_addsy = NULL; | |
13973 | fixp->fx_subsy = NULL; | |
13974 | md_apply_fix (fixp, (valueT *) &value, NULL); | |
13975 | return NULL; | |
13976 | } | |
8ce3d284 | 13977 | #endif |
1a0670f3 | 13978 | /* Fall through. */ |
8fd4256d | 13979 | |
3e73aa7c JH |
13980 | case BFD_RELOC_X86_64_PLT32: |
13981 | case BFD_RELOC_X86_64_GOT32: | |
13982 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
13983 | case BFD_RELOC_X86_64_GOTPCRELX: |
13984 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
252b5132 RH |
13985 | case BFD_RELOC_386_PLT32: |
13986 | case BFD_RELOC_386_GOT32: | |
02a86693 | 13987 | case BFD_RELOC_386_GOT32X: |
252b5132 RH |
13988 | case BFD_RELOC_386_GOTOFF: |
13989 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
13990 | case BFD_RELOC_386_TLS_GD: |
13991 | case BFD_RELOC_386_TLS_LDM: | |
13992 | case BFD_RELOC_386_TLS_LDO_32: | |
13993 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
13994 | case BFD_RELOC_386_TLS_IE: |
13995 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
13996 | case BFD_RELOC_386_TLS_LE_32: |
13997 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
13998 | case BFD_RELOC_386_TLS_GOTDESC: |
13999 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
14000 | case BFD_RELOC_X86_64_TLSGD: |
14001 | case BFD_RELOC_X86_64_TLSLD: | |
14002 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 14003 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
14004 | case BFD_RELOC_X86_64_GOTTPOFF: |
14005 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
14006 | case BFD_RELOC_X86_64_TPOFF64: |
14007 | case BFD_RELOC_X86_64_GOTOFF64: | |
14008 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
14009 | case BFD_RELOC_X86_64_GOT64: |
14010 | case BFD_RELOC_X86_64_GOTPCREL64: | |
14011 | case BFD_RELOC_X86_64_GOTPC64: | |
14012 | case BFD_RELOC_X86_64_GOTPLT64: | |
14013 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
14014 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
14015 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
14016 | case BFD_RELOC_RVA: |
14017 | case BFD_RELOC_VTABLE_ENTRY: | |
14018 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
14019 | #ifdef TE_PE |
14020 | case BFD_RELOC_32_SECREL: | |
14021 | #endif | |
252b5132 RH |
14022 | code = fixp->fx_r_type; |
14023 | break; | |
dbbaec26 L |
14024 | case BFD_RELOC_X86_64_32S: |
14025 | if (!fixp->fx_pcrel) | |
14026 | { | |
14027 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
14028 | code = fixp->fx_r_type; | |
14029 | break; | |
14030 | } | |
1a0670f3 | 14031 | /* Fall through. */ |
252b5132 | 14032 | default: |
93382f6d | 14033 | if (fixp->fx_pcrel) |
252b5132 | 14034 | { |
93382f6d AM |
14035 | switch (fixp->fx_size) |
14036 | { | |
14037 | default: | |
b091f402 AM |
14038 | as_bad_where (fixp->fx_file, fixp->fx_line, |
14039 | _("can not do %d byte pc-relative relocation"), | |
14040 | fixp->fx_size); | |
93382f6d AM |
14041 | code = BFD_RELOC_32_PCREL; |
14042 | break; | |
14043 | case 1: code = BFD_RELOC_8_PCREL; break; | |
14044 | case 2: code = BFD_RELOC_16_PCREL; break; | |
d258b828 | 14045 | case 4: code = BFD_RELOC_32_PCREL; break; |
d6ab8113 JB |
14046 | #ifdef BFD64 |
14047 | case 8: code = BFD_RELOC_64_PCREL; break; | |
14048 | #endif | |
93382f6d AM |
14049 | } |
14050 | } | |
14051 | else | |
14052 | { | |
14053 | switch (fixp->fx_size) | |
14054 | { | |
14055 | default: | |
b091f402 AM |
14056 | as_bad_where (fixp->fx_file, fixp->fx_line, |
14057 | _("can not do %d byte relocation"), | |
14058 | fixp->fx_size); | |
93382f6d AM |
14059 | code = BFD_RELOC_32; |
14060 | break; | |
14061 | case 1: code = BFD_RELOC_8; break; | |
14062 | case 2: code = BFD_RELOC_16; break; | |
14063 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 14064 | #ifdef BFD64 |
3e73aa7c | 14065 | case 8: code = BFD_RELOC_64; break; |
937149dd | 14066 | #endif |
93382f6d | 14067 | } |
252b5132 RH |
14068 | } |
14069 | break; | |
14070 | } | |
252b5132 | 14071 | |
d182319b JB |
14072 | if ((code == BFD_RELOC_32 |
14073 | || code == BFD_RELOC_32_PCREL | |
14074 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
14075 | && GOT_symbol |
14076 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 14077 | { |
4fa24527 | 14078 | if (!object_64bit) |
d6ab8113 JB |
14079 | code = BFD_RELOC_386_GOTPC; |
14080 | else | |
14081 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 14082 | } |
7b81dfbb AJ |
14083 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
14084 | && GOT_symbol | |
14085 | && fixp->fx_addsy == GOT_symbol) | |
14086 | { | |
14087 | code = BFD_RELOC_X86_64_GOTPC64; | |
14088 | } | |
252b5132 | 14089 | |
add39d23 TS |
14090 | rel = XNEW (arelent); |
14091 | rel->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 14092 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
14093 | |
14094 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 14095 | |
3e73aa7c JH |
14096 | if (!use_rela_relocations) |
14097 | { | |
14098 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
14099 | vtable entry to be used in the relocation's section offset. */ | |
14100 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
14101 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
14102 | #if defined (OBJ_COFF) && defined (TE_PE) |
14103 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
14104 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
14105 | else | |
14106 | #endif | |
c6682705 | 14107 | rel->addend = 0; |
3e73aa7c JH |
14108 | } |
14109 | /* Use the rela in 64bit mode. */ | |
252b5132 | 14110 | else |
3e73aa7c | 14111 | { |
862be3fb L |
14112 | if (disallow_64bit_reloc) |
14113 | switch (code) | |
14114 | { | |
862be3fb L |
14115 | case BFD_RELOC_X86_64_DTPOFF64: |
14116 | case BFD_RELOC_X86_64_TPOFF64: | |
14117 | case BFD_RELOC_64_PCREL: | |
14118 | case BFD_RELOC_X86_64_GOTOFF64: | |
14119 | case BFD_RELOC_X86_64_GOT64: | |
14120 | case BFD_RELOC_X86_64_GOTPCREL64: | |
14121 | case BFD_RELOC_X86_64_GOTPC64: | |
14122 | case BFD_RELOC_X86_64_GOTPLT64: | |
14123 | case BFD_RELOC_X86_64_PLTOFF64: | |
14124 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
14125 | _("cannot represent relocation type %s in x32 mode"), | |
14126 | bfd_get_reloc_code_name (code)); | |
14127 | break; | |
14128 | default: | |
14129 | break; | |
14130 | } | |
14131 | ||
062cd5e7 AS |
14132 | if (!fixp->fx_pcrel) |
14133 | rel->addend = fixp->fx_offset; | |
14134 | else | |
14135 | switch (code) | |
14136 | { | |
14137 | case BFD_RELOC_X86_64_PLT32: | |
14138 | case BFD_RELOC_X86_64_GOT32: | |
14139 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
14140 | case BFD_RELOC_X86_64_GOTPCRELX: |
14141 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
bffbf940 JJ |
14142 | case BFD_RELOC_X86_64_TLSGD: |
14143 | case BFD_RELOC_X86_64_TLSLD: | |
14144 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
14145 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
14146 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
14147 | rel->addend = fixp->fx_offset - fixp->fx_size; |
14148 | break; | |
14149 | default: | |
14150 | rel->addend = (section->vma | |
14151 | - fixp->fx_size | |
14152 | + fixp->fx_addnumber | |
14153 | + md_pcrel_from (fixp)); | |
14154 | break; | |
14155 | } | |
3e73aa7c JH |
14156 | } |
14157 | ||
252b5132 RH |
14158 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
14159 | if (rel->howto == NULL) | |
14160 | { | |
14161 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 14162 | _("cannot represent relocation type %s"), |
252b5132 RH |
14163 | bfd_get_reloc_code_name (code)); |
14164 | /* Set howto to a garbage value so that we can keep going. */ | |
14165 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 14166 | gas_assert (rel->howto != NULL); |
252b5132 RH |
14167 | } |
14168 | ||
14169 | return rel; | |
14170 | } | |
14171 | ||
ee86248c | 14172 | #include "tc-i386-intel.c" |
54cfded0 | 14173 | |
a60de03c JB |
14174 | void |
14175 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 14176 | { |
a60de03c JB |
14177 | int saved_naked_reg; |
14178 | char saved_register_dot; | |
54cfded0 | 14179 | |
a60de03c JB |
14180 | saved_naked_reg = allow_naked_reg; |
14181 | allow_naked_reg = 1; | |
14182 | saved_register_dot = register_chars['.']; | |
14183 | register_chars['.'] = '.'; | |
14184 | allow_pseudo_reg = 1; | |
14185 | expression_and_evaluate (exp); | |
14186 | allow_pseudo_reg = 0; | |
14187 | register_chars['.'] = saved_register_dot; | |
14188 | allow_naked_reg = saved_naked_reg; | |
14189 | ||
e96d56a1 | 14190 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
54cfded0 | 14191 | { |
a60de03c JB |
14192 | if ((addressT) exp->X_add_number < i386_regtab_size) |
14193 | { | |
14194 | exp->X_op = O_constant; | |
14195 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
14196 | .dw2_regnum[flag_code >> 1]; | |
14197 | } | |
14198 | else | |
14199 | exp->X_op = O_illegal; | |
54cfded0 | 14200 | } |
54cfded0 AM |
14201 | } |
14202 | ||
14203 | void | |
14204 | tc_x86_frame_initial_instructions (void) | |
14205 | { | |
a60de03c JB |
14206 | static unsigned int sp_regno[2]; |
14207 | ||
14208 | if (!sp_regno[flag_code >> 1]) | |
14209 | { | |
14210 | char *saved_input = input_line_pointer; | |
14211 | char sp[][4] = {"esp", "rsp"}; | |
14212 | expressionS exp; | |
a4447b93 | 14213 | |
a60de03c JB |
14214 | input_line_pointer = sp[flag_code >> 1]; |
14215 | tc_x86_parse_to_dw2regnum (&exp); | |
9c2799c2 | 14216 | gas_assert (exp.X_op == O_constant); |
a60de03c JB |
14217 | sp_regno[flag_code >> 1] = exp.X_add_number; |
14218 | input_line_pointer = saved_input; | |
14219 | } | |
a4447b93 | 14220 | |
61ff971f L |
14221 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
14222 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 14223 | } |
d2b2c203 | 14224 | |
d7921315 L |
14225 | int |
14226 | x86_dwarf2_addr_size (void) | |
14227 | { | |
14228 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
14229 | if (x86_elf_abi == X86_64_X32_ABI) | |
14230 | return 4; | |
14231 | #endif | |
14232 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
14233 | } | |
14234 | ||
d2b2c203 DJ |
14235 | int |
14236 | i386_elf_section_type (const char *str, size_t len) | |
14237 | { | |
14238 | if (flag_code == CODE_64BIT | |
14239 | && len == sizeof ("unwind") - 1 | |
14240 | && strncmp (str, "unwind", 6) == 0) | |
14241 | return SHT_X86_64_UNWIND; | |
14242 | ||
14243 | return -1; | |
14244 | } | |
bb41ade5 | 14245 | |
ad5fec3b EB |
14246 | #ifdef TE_SOLARIS |
14247 | void | |
14248 | i386_solaris_fix_up_eh_frame (segT sec) | |
14249 | { | |
14250 | if (flag_code == CODE_64BIT) | |
14251 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
14252 | } | |
14253 | #endif | |
14254 | ||
bb41ade5 AM |
14255 | #ifdef TE_PE |
14256 | void | |
14257 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
14258 | { | |
91d6fa6a | 14259 | expressionS exp; |
bb41ade5 | 14260 | |
91d6fa6a NC |
14261 | exp.X_op = O_secrel; |
14262 | exp.X_add_symbol = symbol; | |
14263 | exp.X_add_number = 0; | |
14264 | emit_expr (&exp, size); | |
bb41ade5 AM |
14265 | } |
14266 | #endif | |
3b22753a L |
14267 | |
14268 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
14269 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
14270 | ||
01e1a5bc | 14271 | bfd_vma |
6d4af3c2 | 14272 | x86_64_section_letter (int letter, const char **ptr_msg) |
3b22753a L |
14273 | { |
14274 | if (flag_code == CODE_64BIT) | |
14275 | { | |
14276 | if (letter == 'l') | |
14277 | return SHF_X86_64_LARGE; | |
14278 | ||
8f3bae45 | 14279 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
64e74474 | 14280 | } |
3b22753a | 14281 | else |
8f3bae45 | 14282 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
14283 | return -1; |
14284 | } | |
14285 | ||
01e1a5bc | 14286 | bfd_vma |
3b22753a L |
14287 | x86_64_section_word (char *str, size_t len) |
14288 | { | |
8620418b | 14289 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
3b22753a L |
14290 | return SHF_X86_64_LARGE; |
14291 | ||
14292 | return -1; | |
14293 | } | |
14294 | ||
14295 | static void | |
14296 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
14297 | { | |
14298 | if (flag_code != CODE_64BIT) | |
14299 | { | |
14300 | s_comm_internal (0, elf_common_parse); | |
14301 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
14302 | } | |
14303 | else | |
14304 | { | |
14305 | static segT lbss_section; | |
14306 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
14307 | asection *saved_bss_section = bss_section; | |
14308 | ||
14309 | if (lbss_section == NULL) | |
14310 | { | |
14311 | flagword applicable; | |
14312 | segT seg = now_seg; | |
14313 | subsegT subseg = now_subseg; | |
14314 | ||
14315 | /* The .lbss section is for local .largecomm symbols. */ | |
14316 | lbss_section = subseg_new (".lbss", 0); | |
14317 | applicable = bfd_applicable_section_flags (stdoutput); | |
fd361982 | 14318 | bfd_set_section_flags (lbss_section, applicable & SEC_ALLOC); |
3b22753a L |
14319 | seg_info (lbss_section)->bss = 1; |
14320 | ||
14321 | subseg_set (seg, subseg); | |
14322 | } | |
14323 | ||
14324 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
14325 | bss_section = lbss_section; | |
14326 | ||
14327 | s_comm_internal (0, elf_common_parse); | |
14328 | ||
14329 | elf_com_section_ptr = saved_com_section_ptr; | |
14330 | bss_section = saved_bss_section; | |
14331 | } | |
14332 | } | |
14333 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |