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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4dc85607 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
252b5132 36
252b5132
RH		 37#ifndef REGISTER_WARNINGS
38#define REGISTER_WARNINGS 1
39#endif
40
c3332e24 41#ifndef INFER_ADDR_PREFIX
eecb386c 42#define INFER_ADDR_PREFIX 1
c3332e24
AM		 43#endif
44
252b5132
RH		 45#ifndef SCALE1_WHEN_NO_INDEX
46/* Specifying a scale factor besides 1 when there is no index is
47 futile. eg. `mov (%ebx,2),%al' does exactly the same as
48 `mov (%ebx),%al'. To slavishly follow what the programmer
49 specified, set SCALE1_WHEN_NO_INDEX to 0. */
50#define SCALE1_WHEN_NO_INDEX 1
51#endif
52
29b0f896
AM		 53#ifndef DEFAULT_ARCH
54#define DEFAULT_ARCH "i386"
246fcdee 55#endif
252b5132 56
edde18a5
AM		 57#ifndef INLINE
58#if __GNUC__ >= 2
59#define INLINE __inline__
60#else
61#define INLINE
62#endif
63#endif
64
e3bb37b5
L		 65static void set_code_flag (int);
66static void set_16bit_gcc_code_flag (int);
67static void set_intel_syntax (int);
68static void set_cpu_arch (int);
6482c264 69#ifdef TE_PE
e3bb37b5 70static void pe_directive_secrel (int);
6482c264 71#endif
e3bb37b5
L		 72static void signed_cons (int);
73static char *output_invalid (int c);
74static int i386_operand (char *);
75static int i386_intel_operand (char *, int);
76static const reg_entry *parse_register (char *, char **);
77static char *parse_insn (char *, char *);
78static char *parse_operands (char *, const char *);
79static void swap_operands (void);
4d456e3d 80static void swap_2_operands (int, int);
e3bb37b5
L		 81static void optimize_imm (void);
82static void optimize_disp (void);
83static int match_template (void);
84static int check_string (void);
85static int process_suffix (void);
86static int check_byte_reg (void);
87static int check_long_reg (void);
88static int check_qword_reg (void);
89static int check_word_reg (void);
90static int finalize_imm (void);
91static int process_operands (void);
92static const seg_entry *build_modrm_byte (void);
93static void output_insn (void);
94static void output_imm (fragS *, offsetT);
95static void output_disp (fragS *, offsetT);
29b0f896 96#ifndef I386COFF
e3bb37b5 97static void s_bss (int);
252b5132 98#endif
17d4e2a2
L		 99#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
100static void handle_large_common (int small ATTRIBUTE_UNUSED);
101#endif
252b5132 102
a847613f 103static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 104
252b5132 105/* 'md_assemble ()' gathers together information and puts it into a
47926f60 106 i386_insn. */
252b5132 107
520dc8e8
AM		 108union i386_op
109 {
110 expressionS *disps;
111 expressionS *imms;
112 const reg_entry *regs;
113 };
114
252b5132
RH		 115struct _i386_insn
116 {
47926f60 117 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 118 template tm;
119
120 /* SUFFIX holds the instruction mnemonic suffix if given.
121 (e.g. 'l' for 'movl') */
122 char suffix;
123
47926f60 124 /* OPERANDS gives the number of given operands. */
252b5132
RH		 125 unsigned int operands;
126
127 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
128 of given register, displacement, memory operands and immediate
47926f60 129 operands. */
252b5132
RH		 130 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
131
132 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 133 use OP[i] for the corresponding operand. */
252b5132
RH		 134 unsigned int types[MAX_OPERANDS];
135
520dc8e8
AM		 136 /* Displacement expression, immediate expression, or register for each
137 operand. */
138 union i386_op op[MAX_OPERANDS];
252b5132 139
3e73aa7c
JH		 140 /* Flags for operands. */
141 unsigned int flags[MAX_OPERANDS];
142#define Operand_PCrel 1
143
252b5132 144 /* Relocation type for operand */
f86103b7 145 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 146
252b5132
RH		 147 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
148 the base index byte below. */
149 const reg_entry *base_reg;
150 const reg_entry *index_reg;
151 unsigned int log2_scale_factor;
152
153 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 154 explicit segment overrides are given. */
ce8a8b2f 155 const seg_entry *seg[2];
252b5132
RH		 156
157 /* PREFIX holds all the given prefix opcodes (usually null).
158 PREFIXES is the number of prefix opcodes. */
159 unsigned int prefixes;
160 unsigned char prefix[MAX_PREFIXES];
161
162 /* RM and SIB are the modrm byte and the sib byte where the
163 addressing modes of this insn are encoded. */
164
165 modrm_byte rm;
3e73aa7c 166 rex_byte rex;
252b5132
RH		 167 sib_byte sib;
168 };
169
170typedef struct _i386_insn i386_insn;
171
172/* List of chars besides those in app.c:symbol_chars that can start an
173 operand. Used to prevent the scrubber eating vital white-space. */
32137342 174const char extra_symbol_chars[] = "*%-(["
252b5132 175#ifdef LEX_AT
32137342
NC		 176 "@"
177#endif
178#ifdef LEX_QM
179 "?"
252b5132 180#endif
32137342 181 ;
252b5132 182
29b0f896
AM		 183#if (defined (TE_I386AIX) \
184 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 185 && !defined (TE_GNU) \
29b0f896 186 && !defined (TE_LINUX) \
32137342 187 && !defined (TE_NETWARE) \
29b0f896
AM		 188 && !defined (TE_FreeBSD) \
189 && !defined (TE_NetBSD)))
252b5132 190/* This array holds the chars that always start a comment. If the
b3b91714
AM		 191 pre-processor is disabled, these aren't very useful. The option
192 --divide will remove '/' from this list. */
193const char *i386_comment_chars = "#/";
194#define SVR4_COMMENT_CHARS 1
252b5132 195#define PREFIX_SEPARATOR '\\'
252b5132 196
b3b91714
AM		 197#else
198const char *i386_comment_chars = "#";
199#define PREFIX_SEPARATOR '/'
200#endif
201
252b5132
RH		 202/* This array holds the chars that only start a comment at the beginning of
203 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 204 .line and .file directives will appear in the pre-processed output.
205 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 206 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 207 #NO_APP at the beginning of its output.
208 Also note that comments started like this one will always work if
252b5132 209 '/' isn't otherwise defined. */
b3b91714 210const char line_comment_chars[] = "#/";
252b5132 211
63a0b638 212const char line_separator_chars[] = ";";
252b5132 213
ce8a8b2f
AM		 214/* Chars that can be used to separate mant from exp in floating point
215 nums. */
252b5132
RH		 216const char EXP_CHARS[] = "eE";
217
ce8a8b2f
AM		 218/* Chars that mean this number is a floating point constant
219 As in 0f12.456
220 or 0d1.2345e12. */
252b5132
RH		 221const char FLT_CHARS[] = "fFdDxX";
222
ce8a8b2f 223/* Tables for lexical analysis. */
252b5132
RH		 224static char mnemonic_chars[256];
225static char register_chars[256];
226static char operand_chars[256];
227static char identifier_chars[256];
228static char digit_chars[256];
229
ce8a8b2f 230/* Lexical macros. */
252b5132
RH		 231#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
232#define is_operand_char(x) (operand_chars[(unsigned char) x])
233#define is_register_char(x) (register_chars[(unsigned char) x])
234#define is_space_char(x) ((x) == ' ')
235#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
236#define is_digit_char(x) (digit_chars[(unsigned char) x])
237
0234cb7c 238/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 239static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
240
241/* md_assemble() always leaves the strings it's passed unaltered. To
242 effect this we maintain a stack of saved characters that we've smashed
243 with '\0's (indicating end of strings for various sub-fields of the
47926f60 244 assembler instruction). */
252b5132 245static char save_stack[32];
ce8a8b2f 246static char *save_stack_p;
252b5132
RH		 247#define END_STRING_AND_SAVE(s) \
248 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
249#define RESTORE_END_STRING(s) \
250 do { *(s) = *--save_stack_p; } while (0)
251
47926f60 252/* The instruction we're assembling. */
252b5132
RH		 253static i386_insn i;
254
255/* Possible templates for current insn. */
256static const templates *current_templates;
257
31b2323c
L		 258/* Per instruction expressionS buffers: max displacements & immediates. */
259static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
260static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 261
47926f60
KH		 262/* Current operand we are working on. */
263static int this_operand;
252b5132 264
3e73aa7c
JH		 265/* We support four different modes. FLAG_CODE variable is used to distinguish
266 these. */
267
268enum flag_code {
269 CODE_32BIT,
270 CODE_16BIT,
271 CODE_64BIT };
f3c180ae 272#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 273
274static enum flag_code flag_code;
4fa24527 275static unsigned int object_64bit;
3e73aa7c
JH		 276static int use_rela_relocations = 0;
277
278/* The names used to print error messages. */
b77a7acd 279static const char *flag_code_names[] =
3e73aa7c
JH		 280 {
281 "32",
282 "16",
283 "64"
284 };
252b5132 285
47926f60
KH		 286/* 1 for intel syntax,
287 0 if att syntax. */
288static int intel_syntax = 0;
252b5132 289
47926f60
KH		 290/* 1 if register prefix % not required. */
291static int allow_naked_reg = 0;
252b5132 292
2ca3ace5
L		 293/* Register prefix used for error message. */
294static const char *register_prefix = "%";
295
47926f60
KH		 296/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
297 leave, push, and pop instructions so that gcc has the same stack
298 frame as in 32 bit mode. */
299static char stackop_size = '\0';
eecb386c 300
12b55ccc
L		 301/* Non-zero to optimize code alignment. */
302int optimize_align_code = 1;
303
47926f60
KH		 304/* Non-zero to quieten some warnings. */
305static int quiet_warnings = 0;
a38cf1db 306
47926f60
KH		 307/* CPU name. */
308static const char *cpu_arch_name = NULL;
5c6af06e 309static const char *cpu_sub_arch_name = NULL;
a38cf1db 310
47926f60 311/* CPU feature flags. */
29b0f896 312static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 313
ccc9c027
L		 314/* If we have selected a cpu we are generating instructions for. */
315static int cpu_arch_tune_set = 0;
316
9103f4f4
L		 317/* Cpu we are generating instructions for. */
318static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
319
320/* CPU feature flags of cpu we are generating instructions for. */
321static unsigned int cpu_arch_tune_flags = 0;
322
ccc9c027
L		 323/* CPU instruction set architecture used. */
324static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
325
9103f4f4
L		 326/* CPU feature flags of instruction set architecture used. */
327static unsigned int cpu_arch_isa_flags = 0;
328
fddf5b5b
AM		 329/* If set, conditional jumps are not automatically promoted to handle
330 larger than a byte offset. */
331static unsigned int no_cond_jump_promotion = 0;
332
29b0f896 333/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 334static symbolS *GOT_symbol;
29b0f896 335
a4447b93
RH		 336/* The dwarf2 return column, adjusted for 32 or 64 bit. */
337unsigned int x86_dwarf2_return_column;
338
339/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
340int x86_cie_data_alignment;
341
252b5132 342/* Interface to relax_segment.
fddf5b5b
AM		 343 There are 3 major relax states for 386 jump insns because the
344 different types of jumps add different sizes to frags when we're
345 figuring out what sort of jump to choose to reach a given label. */
252b5132 346
47926f60 347/* Types. */
93c2a809
AM		 348#define UNCOND_JUMP 0
349#define COND_JUMP 1
350#define COND_JUMP86 2
fddf5b5b 351
47926f60 352/* Sizes. */
252b5132
RH		 353#define CODE16 1
354#define SMALL 0
29b0f896 355#define SMALL16 (SMALL | CODE16)
252b5132 356#define BIG 2
29b0f896 357#define BIG16 (BIG | CODE16)
252b5132
RH		 358
359#ifndef INLINE
360#ifdef __GNUC__
361#define INLINE __inline__
362#else
363#define INLINE
364#endif
365#endif
366
fddf5b5b
AM		 367#define ENCODE_RELAX_STATE(type, size) \
368 ((relax_substateT) (((type) << 2) | (size)))
369#define TYPE_FROM_RELAX_STATE(s) \
370 ((s) >> 2)
371#define DISP_SIZE_FROM_RELAX_STATE(s) \
372 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 373
374/* This table is used by relax_frag to promote short jumps to long
375 ones where necessary. SMALL (short) jumps may be promoted to BIG
376 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
377 don't allow a short jump in a 32 bit code segment to be promoted to
378 a 16 bit offset jump because it's slower (requires data size
379 prefix), and doesn't work, unless the destination is in the bottom
380 64k of the code segment (The top 16 bits of eip are zeroed). */
381
382const relax_typeS md_relax_table[] =
383{
24eab124
AM		 384 /* The fields are:
385 1) most positive reach of this state,
386 2) most negative reach of this state,
93c2a809 387 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 388 4) which index into the table to try if we can't fit into this one. */
252b5132 389
fddf5b5b 390 /* UNCOND_JUMP states. */
93c2a809
AM		 391 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
392 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
393 /* dword jmp adds 4 bytes to frag:
394 0 extra opcode bytes, 4 displacement bytes. */
252b5132 395 {0, 0, 4, 0},
93c2a809
AM		 396 /* word jmp adds 2 byte2 to frag:
397 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 398 {0, 0, 2, 0},
399
93c2a809
AM		 400 /* COND_JUMP states. */
401 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
402 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
403 /* dword conditionals adds 5 bytes to frag:
404 1 extra opcode byte, 4 displacement bytes. */
405 {0, 0, 5, 0},
fddf5b5b 406 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 407 1 extra opcode byte, 2 displacement bytes. */
408 {0, 0, 3, 0},
409
410 /* COND_JUMP86 states. */
411 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
412 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
413 /* dword conditionals adds 5 bytes to frag:
414 1 extra opcode byte, 4 displacement bytes. */
415 {0, 0, 5, 0},
416 /* word conditionals add 4 bytes to frag:
417 1 displacement byte and a 3 byte long branch insn. */
418 {0, 0, 4, 0}
252b5132
RH		 419};
420
9103f4f4
L		 421static const arch_entry cpu_arch[] =
422{
423 {"generic32", PROCESSOR_GENERIC32,
d32cad65 424 Cpu186|Cpu286|Cpu386},
9103f4f4 425 {"generic64", PROCESSOR_GENERIC64,
d32cad65 426 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 427 |CpuMMX2|CpuSSE|CpuSSE2},
428 {"i8086", PROCESSOR_UNKNOWN,
d32cad65 429 0},
9103f4f4 430 {"i186", PROCESSOR_UNKNOWN,
d32cad65 431 Cpu186},
9103f4f4 432 {"i286", PROCESSOR_UNKNOWN,
d32cad65 433 Cpu186|Cpu286},
9103f4f4 434 {"i386", PROCESSOR_GENERIC32,
d32cad65 435 Cpu186|Cpu286|Cpu386},
9103f4f4 436 {"i486", PROCESSOR_I486,
d32cad65 437 Cpu186|Cpu286|Cpu386|Cpu486},
9103f4f4 438 {"i586", PROCESSOR_PENTIUM,
d32cad65 439 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 440 {"i686", PROCESSOR_PENTIUMPRO,
d32cad65 441 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 442 {"pentium", PROCESSOR_PENTIUM,
d32cad65 443 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 444 {"pentiumpro",PROCESSOR_PENTIUMPRO,
d32cad65 445 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 446 {"pentiumii", PROCESSOR_PENTIUMPRO,
d32cad65 447 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
9103f4f4 448 {"pentiumiii",PROCESSOR_PENTIUMPRO,
d32cad65 449 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
9103f4f4 450 {"pentium4", PROCESSOR_PENTIUM4,
d32cad65 451 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 452 |CpuMMX2|CpuSSE|CpuSSE2},
453 {"prescott", PROCESSOR_NOCONA,
d32cad65 454 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 455 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
456 {"nocona", PROCESSOR_NOCONA,
d32cad65 457 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 458 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 459 {"yonah", PROCESSOR_CORE,
d32cad65 460 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 461 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 462 {"core", PROCESSOR_CORE,
d32cad65 463 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
ef05d495
L		 464 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
465 {"merom", PROCESSOR_CORE2,
466 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
467 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
468 {"core2", PROCESSOR_CORE2,
469 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
470 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
9103f4f4 471 {"k6", PROCESSOR_K6,
d32cad65 472 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
9103f4f4 473 {"k6_2", PROCESSOR_K6,
d32cad65 474 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
9103f4f4 475 {"athlon", PROCESSOR_ATHLON,
d32cad65 476 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 477 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
478 {"sledgehammer", PROCESSOR_K8,
d32cad65 479 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 480 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
481 {"opteron", PROCESSOR_K8,
d32cad65 482 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 483 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
484 {"k8", PROCESSOR_K8,
d32cad65 485 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4 486 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
050dfa73 487 {"amdfam10", PROCESSOR_AMDFAM10,
d32cad65
L		 488 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
489 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
490 |CpuABM},
9103f4f4
L		 491 {".mmx", PROCESSOR_UNKNOWN,
492 CpuMMX},
493 {".sse", PROCESSOR_UNKNOWN,
494 CpuMMX|CpuMMX2|CpuSSE},
495 {".sse2", PROCESSOR_UNKNOWN,
496 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
497 {".sse3", PROCESSOR_UNKNOWN,
498 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495
L		 499 {".ssse3", PROCESSOR_UNKNOWN,
500 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
42903f7f
L		 501 {".sse4.1", PROCESSOR_UNKNOWN,
502 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1},
9103f4f4
L		 503 {".3dnow", PROCESSOR_UNKNOWN,
504 CpuMMX|Cpu3dnow},
505 {".3dnowa", PROCESSOR_UNKNOWN,
506 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
507 {".padlock", PROCESSOR_UNKNOWN,
508 CpuPadLock},
509 {".pacifica", PROCESSOR_UNKNOWN,
510 CpuSVME},
511 {".svme", PROCESSOR_UNKNOWN,
050dfa73
MM		 512 CpuSVME},
513 {".sse4a", PROCESSOR_UNKNOWN,
514 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
515 {".abm", PROCESSOR_UNKNOWN,
516 CpuABM}
e413e4e9
AM		 517};
518
29b0f896
AM		 519const pseudo_typeS md_pseudo_table[] =
520{
521#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
522 {"align", s_align_bytes, 0},
523#else
524 {"align", s_align_ptwo, 0},
525#endif
526 {"arch", set_cpu_arch, 0},
527#ifndef I386COFF
528 {"bss", s_bss, 0},
529#endif
530 {"ffloat", float_cons, 'f'},
531 {"dfloat", float_cons, 'd'},
532 {"tfloat", float_cons, 'x'},
533 {"value", cons, 2},
d182319b 534 {"slong", signed_cons, 4},
29b0f896
AM		 535 {"noopt", s_ignore, 0},
536 {"optim", s_ignore, 0},
537 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
538 {"code16", set_code_flag, CODE_16BIT},
539 {"code32", set_code_flag, CODE_32BIT},
540 {"code64", set_code_flag, CODE_64BIT},
541 {"intel_syntax", set_intel_syntax, 1},
542 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 543#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
544 {"largecomm", handle_large_common, 0},
07a53e5c 545#else
e3bb37b5 546 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 547 {"loc", dwarf2_directive_loc, 0},
548 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 549#endif
6482c264
NC		 550#ifdef TE_PE
551 {"secrel32", pe_directive_secrel, 0},
552#endif
29b0f896
AM		 553 {0, 0, 0}
554};
555
556/* For interface with expression (). */
557extern char *input_line_pointer;
558
559/* Hash table for instruction mnemonic lookup. */
560static struct hash_control *op_hash;
561
562/* Hash table for register lookup. */
563static struct hash_control *reg_hash;
564\f
252b5132 565void
e3bb37b5 566i386_align_code (fragS *fragP, int count)
252b5132 567{
ce8a8b2f
AM		 568 /* Various efficient no-op patterns for aligning code labels.
569 Note: Don't try to assemble the instructions in the comments.
570 0L and 0w are not legal. */
252b5132
RH		 571 static const char f32_1[] =
572 {0x90}; /* nop */
573 static const char f32_2[] =
ccc9c027 574 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 575 static const char f32_3[] =
576 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
577 static const char f32_4[] =
578 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
579 static const char f32_5[] =
580 {0x90, /* nop */
581 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
582 static const char f32_6[] =
583 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
584 static const char f32_7[] =
585 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
586 static const char f32_8[] =
587 {0x90, /* nop */
588 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
589 static const char f32_9[] =
590 {0x89,0xf6, /* movl %esi,%esi */
591 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
592 static const char f32_10[] =
593 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
594 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
595 static const char f32_11[] =
596 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
597 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
598 static const char f32_12[] =
599 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
600 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
601 static const char f32_13[] =
602 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
603 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
604 static const char f32_14[] =
605 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
606 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
607 static const char f32_15[] =
608 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
609 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 610 static const char f16_3[] =
611 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 612 static const char f16_4[] =
613 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
614 static const char f16_5[] =
615 {0x90, /* nop */
616 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
617 static const char f16_6[] =
618 {0x89,0xf6, /* mov %si,%si */
619 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
620 static const char f16_7[] =
621 {0x8d,0x74,0x00, /* lea 0(%si),%si */
622 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
623 static const char f16_8[] =
624 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
625 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
626 static const char *const f32_patt[] = {
627 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
628 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
629 };
630 static const char *const f16_patt[] = {
c3332e24 631 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 632 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
633 };
ccc9c027
L		 634 /* nopl (%[re]ax) */
635 static const char alt_3[] =
636 {0x0f,0x1f,0x00};
637 /* nopl 0(%[re]ax) */
638 static const char alt_4[] =
639 {0x0f,0x1f,0x40,0x00};
640 /* nopl 0(%[re]ax,%[re]ax,1) */
641 static const char alt_5[] =
642 {0x0f,0x1f,0x44,0x00,0x00};
643 /* nopw 0(%[re]ax,%[re]ax,1) */
644 static const char alt_6[] =
645 {0x66,0x0f,0x1f,0x44,0x00,0x00};
646 /* nopl 0L(%[re]ax) */
647 static const char alt_7[] =
648 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
649 /* nopl 0L(%[re]ax,%[re]ax,1) */
650 static const char alt_8[] =
651 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
652 /* nopw 0L(%[re]ax,%[re]ax,1) */
653 static const char alt_9[] =
654 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
655 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
656 static const char alt_10[] =
657 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
658 /* data16
659 nopw %cs:0L(%[re]ax,%[re]ax,1) */
660 static const char alt_long_11[] =
661 {0x66,
662 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
663 /* data16
664 data16
665 nopw %cs:0L(%[re]ax,%[re]ax,1) */
666 static const char alt_long_12[] =
667 {0x66,
668 0x66,
669 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
670 /* data16
671 data16
672 data16
673 nopw %cs:0L(%[re]ax,%[re]ax,1) */
674 static const char alt_long_13[] =
675 {0x66,
676 0x66,
677 0x66,
678 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
679 /* data16
680 data16
681 data16
682 data16
683 nopw %cs:0L(%[re]ax,%[re]ax,1) */
684 static const char alt_long_14[] =
685 {0x66,
686 0x66,
687 0x66,
688 0x66,
689 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
690 /* data16
691 data16
692 data16
693 data16
694 data16
695 nopw %cs:0L(%[re]ax,%[re]ax,1) */
696 static const char alt_long_15[] =
697 {0x66,
698 0x66,
699 0x66,
700 0x66,
701 0x66,
702 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
703 /* nopl 0(%[re]ax,%[re]ax,1)
704 nopw 0(%[re]ax,%[re]ax,1) */
705 static const char alt_short_11[] =
706 {0x0f,0x1f,0x44,0x00,0x00,
707 0x66,0x0f,0x1f,0x44,0x00,0x00};
708 /* nopw 0(%[re]ax,%[re]ax,1)
709 nopw 0(%[re]ax,%[re]ax,1) */
710 static const char alt_short_12[] =
711 {0x66,0x0f,0x1f,0x44,0x00,0x00,
712 0x66,0x0f,0x1f,0x44,0x00,0x00};
713 /* nopw 0(%[re]ax,%[re]ax,1)
714 nopl 0L(%[re]ax) */
715 static const char alt_short_13[] =
716 {0x66,0x0f,0x1f,0x44,0x00,0x00,
717 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
718 /* nopl 0L(%[re]ax)
719 nopl 0L(%[re]ax) */
720 static const char alt_short_14[] =
721 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
722 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
723 /* nopl 0L(%[re]ax)
724 nopl 0L(%[re]ax,%[re]ax,1) */
725 static const char alt_short_15[] =
726 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
727 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
728 static const char *const alt_short_patt[] = {
729 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
730 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
731 alt_short_14, alt_short_15
732 };
733 static const char *const alt_long_patt[] = {
734 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
735 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
736 alt_long_14, alt_long_15
737 };
252b5132 738
33fef721
JH		 739 if (count <= 0 || count > 15)
740 return;
3e73aa7c 741
ccc9c027
L		 742 /* We need to decide which NOP sequence to use for 32bit and
743 64bit. When -mtune= is used:
4eed87de 744
ccc9c027
L		 745 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
746 f32_patt will be used.
4eed87de
AM		 747 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with
748 0x66 prefix will be used.
ef05d495 749 3. For PROCESSOR_CORE2, alt_long_patt will be used.
ccc9c027 750 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
ef05d495 751 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
ccc9c027
L		 752 and PROCESSOR_GENERIC64, alt_short_patt will be used.
753
754 When -mtune= isn't used, alt_short_patt will be used if
755 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
756
757 When -march= or .arch is used, we can't use anything beyond
758 cpu_arch_isa_flags. */
759
760 if (flag_code == CODE_16BIT)
761 {
762 memcpy (fragP->fr_literal + fragP->fr_fix,
763 f16_patt[count - 1], count);
764 if (count > 8)
765 /* Adjust jump offset. */
766 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
767 }
768 else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
252b5132 769 {
33fef721
JH		 770 int i;
771 int nnops = (count + 3) / 4;
772 int len = count / nnops;
773 int remains = count - nnops * len;
774 int pos = 0;
775
ccc9c027 776 /* The recommended way to pad 64bit code is to use NOPs preceded
4eed87de 777 by maximally four 0x66 prefixes. Balance the size of nops. */
33fef721 778 for (i = 0; i < remains; i++)
252b5132 779 {
33fef721
JH		 780 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
781 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
782 pos += len + 1;
783 }
784 for (; i < nnops; i++)
785 {
786 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
787 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
788 pos += len;
252b5132 789 }
252b5132 790 }
33fef721 791 else
ccc9c027
L		 792 {
793 const char *const *patt = NULL;
794
795 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
796 {
797 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
798 switch (cpu_arch_tune)
799 {
800 case PROCESSOR_UNKNOWN:
801 /* We use cpu_arch_isa_flags to check if we SHOULD
802 optimize for Cpu686. */
803 if ((cpu_arch_isa_flags & Cpu686) != 0)
804 patt = alt_short_patt;
805 else
806 patt = f32_patt;
807 break;
ef05d495 808 case PROCESSOR_CORE2:
ccc9c027
L		 809 patt = alt_long_patt;
810 break;
811 case PROCESSOR_PENTIUMPRO:
812 case PROCESSOR_PENTIUM4:
813 case PROCESSOR_NOCONA:
ef05d495 814 case PROCESSOR_CORE:
ccc9c027
L		 815 case PROCESSOR_K6:
816 case PROCESSOR_ATHLON:
817 case PROCESSOR_K8:
818 case PROCESSOR_GENERIC64:
4eed87de 819 case PROCESSOR_AMDFAM10:
ccc9c027
L		 820 patt = alt_short_patt;
821 break;
822 case PROCESSOR_I486:
823 case PROCESSOR_PENTIUM:
824 case PROCESSOR_GENERIC32:
825 patt = f32_patt;
826 break;
4eed87de 827 }
ccc9c027
L		 828 }
829 else
830 {
831 switch (cpu_arch_tune)
832 {
833 case PROCESSOR_UNKNOWN:
834 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
835 PROCESSOR_UNKNOWN. */
836 abort ();
837 break;
838
839 case PROCESSOR_I486:
840 case PROCESSOR_PENTIUM:
841 case PROCESSOR_PENTIUMPRO:
842 case PROCESSOR_PENTIUM4:
843 case PROCESSOR_NOCONA:
ef05d495 844 case PROCESSOR_CORE:
ccc9c027
L		 845 case PROCESSOR_K6:
846 case PROCESSOR_ATHLON:
847 case PROCESSOR_K8:
4eed87de 848 case PROCESSOR_AMDFAM10:
ccc9c027
L		 849 case PROCESSOR_GENERIC32:
850 /* We use cpu_arch_isa_flags to check if we CAN optimize
851 for Cpu686. */
852 if ((cpu_arch_isa_flags & Cpu686) != 0)
853 patt = alt_short_patt;
854 else
855 patt = f32_patt;
856 break;
ef05d495 857 case PROCESSOR_CORE2:
ccc9c027
L		 858 if ((cpu_arch_isa_flags & Cpu686) != 0)
859 patt = alt_long_patt;
860 else
861 patt = f32_patt;
862 break;
863 case PROCESSOR_GENERIC64:
864 patt = alt_short_patt;
865 break;
4eed87de 866 }
ccc9c027
L		 867 }
868
33fef721 869 memcpy (fragP->fr_literal + fragP->fr_fix,
ccc9c027
L		 870 patt[count - 1], count);
871 }
33fef721 872 fragP->fr_var = count;
252b5132
RH		 873}
874
252b5132 875static INLINE unsigned int
e3bb37b5 876mode_from_disp_size (unsigned int t)
252b5132 877{
3e73aa7c 878 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 879}
880
881static INLINE int
e3bb37b5 882fits_in_signed_byte (offsetT num)
252b5132
RH		 883{
884 return (num >= -128) && (num <= 127);
47926f60 885}
252b5132
RH		 886
887static INLINE int
e3bb37b5 888fits_in_unsigned_byte (offsetT num)
252b5132
RH		 889{
890 return (num & 0xff) == num;
47926f60 891}
252b5132
RH		 892
893static INLINE int
e3bb37b5 894fits_in_unsigned_word (offsetT num)
252b5132
RH		 895{
896 return (num & 0xffff) == num;
47926f60 897}
252b5132
RH		 898
899static INLINE int
e3bb37b5 900fits_in_signed_word (offsetT num)
252b5132
RH		 901{
902 return (-32768 <= num) && (num <= 32767);
47926f60 903}
2a962e6d 904
3e73aa7c 905static INLINE int
e3bb37b5 906fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 907{
908#ifndef BFD64
909 return 1;
910#else
911 return (!(((offsetT) -1 << 31) & num)
912 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
913#endif
914} /* fits_in_signed_long() */
2a962e6d 915
3e73aa7c 916static INLINE int
e3bb37b5 917fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 918{
919#ifndef BFD64
920 return 1;
921#else
922 return (num & (((offsetT) 2 << 31) - 1)) == num;
923#endif
924} /* fits_in_unsigned_long() */
252b5132 925
1509aa9a 926static unsigned int
e3bb37b5 927smallest_imm_type (offsetT num)
252b5132 928{
d32cad65 929 if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 930 {
931 /* This code is disabled on the 486 because all the Imm1 forms
932 in the opcode table are slower on the i486. They're the
933 versions with the implicitly specified single-position
934 displacement, which has another syntax if you really want to
935 use that form. */
936 if (num == 1)
3e73aa7c 937 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 938 }
252b5132 939 return (fits_in_signed_byte (num)
3e73aa7c 940 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 941 : fits_in_unsigned_byte (num)
3e73aa7c 942 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 943 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 944 ? (Imm16 | Imm32 | Imm32S | Imm64)
945 : fits_in_signed_long (num)
946 ? (Imm32 | Imm32S | Imm64)
947 : fits_in_unsigned_long (num)
948 ? (Imm32 | Imm64)
949 : Imm64);
47926f60 950}
252b5132 951
847f7ad4 952static offsetT
e3bb37b5 953offset_in_range (offsetT val, int size)
847f7ad4 954{
508866be 955 addressT mask;
ba2adb93 956
847f7ad4
AM		 957 switch (size)
958 {
508866be
L		 959 case 1: mask = ((addressT) 1 << 8) - 1; break;
960 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 961 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 962#ifdef BFD64
963 case 8: mask = ((addressT) 2 << 63) - 1; break;
964#endif
47926f60 965 default: abort ();
847f7ad4
AM		 966 }
967
ba2adb93 968 /* If BFD64, sign extend val. */
3e73aa7c
JH		 969 if (!use_rela_relocations)
970 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
971 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 972
47926f60 973 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 974 {
975 char buf1[40], buf2[40];
976
977 sprint_value (buf1, val);
978 sprint_value (buf2, val & mask);
979 as_warn (_("%s shortened to %s"), buf1, buf2);
980 }
981 return val & mask;
982}
983
252b5132
RH		 984/* Returns 0 if attempting to add a prefix where one from the same
985 class already exists, 1 if non rep/repne added, 2 if rep/repne
986 added. */
987static int
e3bb37b5 988add_prefix (unsigned int prefix)
252b5132
RH		 989{
990 int ret = 1;
b1905489 991 unsigned int q;
252b5132 992
29b0f896
AM		 993 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
994 && flag_code == CODE_64BIT)
b1905489 995 {
161a04f6
L		 996 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
997 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
998 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 999 ret = 0;
1000 q = REX_PREFIX;
1001 }
3e73aa7c 1002 else
b1905489
JB		 1003 {
1004 switch (prefix)
1005 {
1006 default:
1007 abort ();
1008
1009 case CS_PREFIX_OPCODE:
1010 case DS_PREFIX_OPCODE:
1011 case ES_PREFIX_OPCODE:
1012 case FS_PREFIX_OPCODE:
1013 case GS_PREFIX_OPCODE:
1014 case SS_PREFIX_OPCODE:
1015 q = SEG_PREFIX;
1016 break;
1017
1018 case REPNE_PREFIX_OPCODE:
1019 case REPE_PREFIX_OPCODE:
1020 ret = 2;
1021 /* fall thru */
1022 case LOCK_PREFIX_OPCODE:
1023 q = LOCKREP_PREFIX;
1024 break;
1025
1026 case FWAIT_OPCODE:
1027 q = WAIT_PREFIX;
1028 break;
1029
1030 case ADDR_PREFIX_OPCODE:
1031 q = ADDR_PREFIX;
1032 break;
1033
1034 case DATA_PREFIX_OPCODE:
1035 q = DATA_PREFIX;
1036 break;
1037 }
1038 if (i.prefix[q] != 0)
1039 ret = 0;
1040 }
252b5132 1041
b1905489 1042 if (ret)
252b5132 1043 {
b1905489
JB		 1044 if (!i.prefix[q])
1045 ++i.prefixes;
1046 i.prefix[q] |= prefix;
252b5132 1047 }
b1905489
JB		 1048 else
1049 as_bad (_("same type of prefix used twice"));
252b5132 1050
252b5132
RH		 1051 return ret;
1052}
1053
1054static void
e3bb37b5 1055set_code_flag (int value)
eecb386c 1056{
3e73aa7c
JH		 1057 flag_code = value;
1058 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1059 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1060 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1061 {
1062 as_bad (_("64bit mode not supported on this CPU."));
1063 }
1064 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1065 {
1066 as_bad (_("32bit mode not supported on this CPU."));
1067 }
eecb386c
AM		 1068 stackop_size = '\0';
1069}
1070
1071static void
e3bb37b5 1072set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1073{
3e73aa7c
JH		 1074 flag_code = new_code_flag;
1075 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1076 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 1077 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1078}
1079
1080static void
e3bb37b5 1081set_intel_syntax (int syntax_flag)
252b5132
RH		 1082{
1083 /* Find out if register prefixing is specified. */
1084 int ask_naked_reg = 0;
1085
1086 SKIP_WHITESPACE ();
29b0f896 1087 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1088 {
1089 char *string = input_line_pointer;
1090 int e = get_symbol_end ();
1091
47926f60 1092 if (strcmp (string, "prefix") == 0)
252b5132 1093 ask_naked_reg = 1;
47926f60 1094 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1095 ask_naked_reg = -1;
1096 else
d0b47220 1097 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1098 *input_line_pointer = e;
1099 }
1100 demand_empty_rest_of_line ();
c3332e24 1101
252b5132
RH		 1102 intel_syntax = syntax_flag;
1103
1104 if (ask_naked_reg == 0)
f86103b7
AM		 1105 allow_naked_reg = (intel_syntax
1106 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1107 else
1108 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1109
e4a3b5a4 1110 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1111 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1112 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1113}
1114
e413e4e9 1115static void
e3bb37b5 1116set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1117{
47926f60 1118 SKIP_WHITESPACE ();
e413e4e9 1119
29b0f896 1120 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1121 {
1122 char *string = input_line_pointer;
1123 int e = get_symbol_end ();
9103f4f4 1124 unsigned int i;
e413e4e9 1125
9103f4f4 1126 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1127 {
1128 if (strcmp (string, cpu_arch[i].name) == 0)
1129 {
5c6af06e
JB		 1130 if (*string != '.')
1131 {
1132 cpu_arch_name = cpu_arch[i].name;
1133 cpu_sub_arch_name = NULL;
1134 cpu_arch_flags = (cpu_arch[i].flags
4eed87de
AM		 1135 | (flag_code == CODE_64BIT
1136 ? Cpu64 : CpuNo64));
ccc9c027 1137 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1138 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1139 if (!cpu_arch_tune_set)
1140 {
1141 cpu_arch_tune = cpu_arch_isa;
1142 cpu_arch_tune_flags = cpu_arch_isa_flags;
1143 }
5c6af06e
JB		 1144 break;
1145 }
1146 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1147 {
1148 cpu_sub_arch_name = cpu_arch[i].name;
1149 cpu_arch_flags |= cpu_arch[i].flags;
1150 }
1151 *input_line_pointer = e;
1152 demand_empty_rest_of_line ();
1153 return;
e413e4e9
AM		 1154 }
1155 }
9103f4f4 1156 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1157 as_bad (_("no such architecture: `%s'"), string);
1158
1159 *input_line_pointer = e;
1160 }
1161 else
1162 as_bad (_("missing cpu architecture"));
1163
fddf5b5b
AM		 1164 no_cond_jump_promotion = 0;
1165 if (*input_line_pointer == ','
29b0f896 1166 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1167 {
1168 char *string = ++input_line_pointer;
1169 int e = get_symbol_end ();
1170
1171 if (strcmp (string, "nojumps") == 0)
1172 no_cond_jump_promotion = 1;
1173 else if (strcmp (string, "jumps") == 0)
1174 ;
1175 else
1176 as_bad (_("no such architecture modifier: `%s'"), string);
1177
1178 *input_line_pointer = e;
1179 }
1180
e413e4e9
AM		 1181 demand_empty_rest_of_line ();
1182}
1183
b9d79e03
JH		 1184unsigned long
1185i386_mach ()
1186{
1187 if (!strcmp (default_arch, "x86_64"))
1188 return bfd_mach_x86_64;
1189 else if (!strcmp (default_arch, "i386"))
1190 return bfd_mach_i386_i386;
1191 else
1192 as_fatal (_("Unknown architecture"));
1193}
b9d79e03 1194\f
252b5132
RH		 1195void
1196md_begin ()
1197{
1198 const char *hash_err;
1199
47926f60 1200 /* Initialize op_hash hash table. */
252b5132
RH		 1201 op_hash = hash_new ();
1202
1203 {
29b0f896
AM		 1204 const template *optab;
1205 templates *core_optab;
252b5132 1206
47926f60
KH		 1207 /* Setup for loop. */
1208 optab = i386_optab;
252b5132
RH		 1209 core_optab = (templates *) xmalloc (sizeof (templates));
1210 core_optab->start = optab;
1211
1212 while (1)
1213 {
1214 ++optab;
1215 if (optab->name == NULL
1216 || strcmp (optab->name, (optab - 1)->name) != 0)
1217 {
1218 /* different name --> ship out current template list;
47926f60 1219 add to hash table; & begin anew. */
252b5132
RH		 1220 core_optab->end = optab;
1221 hash_err = hash_insert (op_hash,
1222 (optab - 1)->name,
1223 (PTR) core_optab);
1224 if (hash_err)
1225 {
252b5132
RH		 1226 as_fatal (_("Internal Error: Can't hash %s: %s"),
1227 (optab - 1)->name,
1228 hash_err);
1229 }
1230 if (optab->name == NULL)
1231 break;
1232 core_optab = (templates *) xmalloc (sizeof (templates));
1233 core_optab->start = optab;
1234 }
1235 }
1236 }
1237
47926f60 1238 /* Initialize reg_hash hash table. */
252b5132
RH		 1239 reg_hash = hash_new ();
1240 {
29b0f896 1241 const reg_entry *regtab;
c3fe08fa 1242 unsigned int regtab_size = i386_regtab_size;
252b5132 1243
c3fe08fa 1244 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132
RH		 1245 {
1246 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1247 if (hash_err)
3e73aa7c
JH		 1248 as_fatal (_("Internal Error: Can't hash %s: %s"),
1249 regtab->reg_name,
1250 hash_err);
252b5132
RH		 1251 }
1252 }
1253
47926f60 1254 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1255 {
29b0f896
AM		 1256 int c;
1257 char *p;
252b5132
RH		 1258
1259 for (c = 0; c < 256; c++)
1260 {
3882b010 1261 if (ISDIGIT (c))
252b5132
RH		 1262 {
1263 digit_chars[c] = c;
1264 mnemonic_chars[c] = c;
1265 register_chars[c] = c;
1266 operand_chars[c] = c;
1267 }
3882b010 1268 else if (ISLOWER (c))
252b5132
RH		 1269 {
1270 mnemonic_chars[c] = c;
1271 register_chars[c] = c;
1272 operand_chars[c] = c;
1273 }
3882b010 1274 else if (ISUPPER (c))
252b5132 1275 {
3882b010 1276 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1277 register_chars[c] = mnemonic_chars[c];
1278 operand_chars[c] = c;
1279 }
1280
3882b010 1281 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1282 identifier_chars[c] = c;
1283 else if (c >= 128)
1284 {
1285 identifier_chars[c] = c;
1286 operand_chars[c] = c;
1287 }
1288 }
1289
1290#ifdef LEX_AT
1291 identifier_chars['@'] = '@';
32137342
NC		 1292#endif
1293#ifdef LEX_QM
1294 identifier_chars['?'] = '?';
1295 operand_chars['?'] = '?';
252b5132 1296#endif
252b5132 1297 digit_chars['-'] = '-';
791fe849 1298 mnemonic_chars['-'] = '-';
0003779b 1299 mnemonic_chars['.'] = '.';
252b5132
RH		 1300 identifier_chars['_'] = '_';
1301 identifier_chars['.'] = '.';
1302
1303 for (p = operand_special_chars; *p != '\0'; p++)
1304 operand_chars[(unsigned char) *p] = *p;
1305 }
1306
1307#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1308 if (IS_ELF)
252b5132
RH		 1309 {
1310 record_alignment (text_section, 2);
1311 record_alignment (data_section, 2);
1312 record_alignment (bss_section, 2);
1313 }
1314#endif
a4447b93
RH		 1315
1316 if (flag_code == CODE_64BIT)
1317 {
1318 x86_dwarf2_return_column = 16;
1319 x86_cie_data_alignment = -8;
1320 }
1321 else
1322 {
1323 x86_dwarf2_return_column = 8;
1324 x86_cie_data_alignment = -4;
1325 }
252b5132
RH		 1326}
1327
1328void
e3bb37b5 1329i386_print_statistics (FILE *file)
252b5132
RH		 1330{
1331 hash_print_statistics (file, "i386 opcode", op_hash);
1332 hash_print_statistics (file, "i386 register", reg_hash);
1333}
1334\f
252b5132
RH		 1335#ifdef DEBUG386
1336
ce8a8b2f 1337/* Debugging routines for md_assemble. */
e3bb37b5
L		 1338static void pte (template *);
1339static void pt (unsigned int);
1340static void pe (expressionS *);
1341static void ps (symbolS *);
252b5132
RH		 1342
1343static void
e3bb37b5 1344pi (char *line, i386_insn *x)
252b5132 1345{
09f131f2 1346 unsigned int i;
252b5132
RH		 1347
1348 fprintf (stdout, "%s: template ", line);
1349 pte (&x->tm);
09f131f2
JH		 1350 fprintf (stdout, " address: base %s index %s scale %x\n",
1351 x->base_reg ? x->base_reg->reg_name : "none",
1352 x->index_reg ? x->index_reg->reg_name : "none",
1353 x->log2_scale_factor);
1354 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1355 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1356 fprintf (stdout, " sib: base %x index %x scale %x\n",
1357 x->sib.base, x->sib.index, x->sib.scale);
1358 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 1359 (x->rex & REX_W) != 0,
1360 (x->rex & REX_R) != 0,
1361 (x->rex & REX_X) != 0,
1362 (x->rex & REX_B) != 0);
252b5132
RH		 1363 for (i = 0; i < x->operands; i++)
1364 {
1365 fprintf (stdout, " #%d: ", i + 1);
1366 pt (x->types[i]);
1367 fprintf (stdout, "\n");
1368 if (x->types[i]
3f4438ab 1369 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1370 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1371 if (x->types[i] & Imm)
520dc8e8 1372 pe (x->op[i].imms);
252b5132 1373 if (x->types[i] & Disp)
520dc8e8 1374 pe (x->op[i].disps);
252b5132
RH		 1375 }
1376}
1377
1378static void
e3bb37b5 1379pte (template *t)
252b5132 1380{
09f131f2 1381 unsigned int i;
252b5132 1382 fprintf (stdout, " %d operands ", t->operands);
47926f60 1383 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1384 if (t->extension_opcode != None)
1385 fprintf (stdout, "ext %x ", t->extension_opcode);
1386 if (t->opcode_modifier & D)
1387 fprintf (stdout, "D");
1388 if (t->opcode_modifier & W)
1389 fprintf (stdout, "W");
1390 fprintf (stdout, "\n");
1391 for (i = 0; i < t->operands; i++)
1392 {
1393 fprintf (stdout, " #%d type ", i + 1);
1394 pt (t->operand_types[i]);
1395 fprintf (stdout, "\n");
1396 }
1397}
1398
1399static void
e3bb37b5 1400pe (expressionS *e)
252b5132 1401{
24eab124 1402 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1403 fprintf (stdout, " add_number %ld (%lx)\n",
1404 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1405 if (e->X_add_symbol)
1406 {
1407 fprintf (stdout, " add_symbol ");
1408 ps (e->X_add_symbol);
1409 fprintf (stdout, "\n");
1410 }
1411 if (e->X_op_symbol)
1412 {
1413 fprintf (stdout, " op_symbol ");
1414 ps (e->X_op_symbol);
1415 fprintf (stdout, "\n");
1416 }
1417}
1418
1419static void
e3bb37b5 1420ps (symbolS *s)
252b5132
RH		 1421{
1422 fprintf (stdout, "%s type %s%s",
1423 S_GET_NAME (s),
1424 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1425 segment_name (S_GET_SEGMENT (s)));
1426}
1427
7b81dfbb 1428static struct type_name
252b5132
RH		 1429 {
1430 unsigned int mask;
1431 char *tname;
1432 }
7b81dfbb 1433const type_names[] =
252b5132
RH		 1434{
1435 { Reg8, "r8" },
1436 { Reg16, "r16" },
1437 { Reg32, "r32" },
09f131f2 1438 { Reg64, "r64" },
252b5132
RH		 1439 { Imm8, "i8" },
1440 { Imm8S, "i8s" },
1441 { Imm16, "i16" },
1442 { Imm32, "i32" },
09f131f2
JH		 1443 { Imm32S, "i32s" },
1444 { Imm64, "i64" },
252b5132
RH		 1445 { Imm1, "i1" },
1446 { BaseIndex, "BaseIndex" },
1447 { Disp8, "d8" },
1448 { Disp16, "d16" },
1449 { Disp32, "d32" },
09f131f2
JH		 1450 { Disp32S, "d32s" },
1451 { Disp64, "d64" },
252b5132
RH		 1452 { InOutPortReg, "InOutPortReg" },
1453 { ShiftCount, "ShiftCount" },
1454 { Control, "control reg" },
1455 { Test, "test reg" },
1456 { Debug, "debug reg" },
1457 { FloatReg, "FReg" },
1458 { FloatAcc, "FAcc" },
1459 { SReg2, "SReg2" },
1460 { SReg3, "SReg3" },
1461 { Acc, "Acc" },
1462 { JumpAbsolute, "Jump Absolute" },
1463 { RegMMX, "rMMX" },
3f4438ab 1464 { RegXMM, "rXMM" },
252b5132
RH		 1465 { EsSeg, "es" },
1466 { 0, "" }
1467};
1468
1469static void
1470pt (t)
1471 unsigned int t;
1472{
29b0f896 1473 const struct type_name *ty;
252b5132 1474
09f131f2
JH		 1475 for (ty = type_names; ty->mask; ty++)
1476 if (t & ty->mask)
1477 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1478 fflush (stdout);
1479}
1480
1481#endif /* DEBUG386 */
1482\f
252b5132 1483static bfd_reloc_code_real_type
3956db08 1484reloc (unsigned int size,
64e74474
AM		 1485 int pcrel,
1486 int sign,
1487 bfd_reloc_code_real_type other)
252b5132 1488{
47926f60 1489 if (other != NO_RELOC)
3956db08
JB		 1490 {
1491 reloc_howto_type *reloc;
1492
1493 if (size == 8)
1494 switch (other)
1495 {
64e74474
AM		 1496 case BFD_RELOC_X86_64_GOT32:
1497 return BFD_RELOC_X86_64_GOT64;
1498 break;
1499 case BFD_RELOC_X86_64_PLTOFF64:
1500 return BFD_RELOC_X86_64_PLTOFF64;
1501 break;
1502 case BFD_RELOC_X86_64_GOTPC32:
1503 other = BFD_RELOC_X86_64_GOTPC64;
1504 break;
1505 case BFD_RELOC_X86_64_GOTPCREL:
1506 other = BFD_RELOC_X86_64_GOTPCREL64;
1507 break;
1508 case BFD_RELOC_X86_64_TPOFF32:
1509 other = BFD_RELOC_X86_64_TPOFF64;
1510 break;
1511 case BFD_RELOC_X86_64_DTPOFF32:
1512 other = BFD_RELOC_X86_64_DTPOFF64;
1513 break;
1514 default:
1515 break;
3956db08 1516 }
e05278af
JB		 1517
1518 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1519 if (size == 4 && flag_code != CODE_64BIT)
1520 sign = -1;
1521
3956db08
JB		 1522 reloc = bfd_reloc_type_lookup (stdoutput, other);
1523 if (!reloc)
1524 as_bad (_("unknown relocation (%u)"), other);
1525 else if (size != bfd_get_reloc_size (reloc))
1526 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1527 bfd_get_reloc_size (reloc),
1528 size);
1529 else if (pcrel && !reloc->pc_relative)
1530 as_bad (_("non-pc-relative relocation for pc-relative field"));
1531 else if ((reloc->complain_on_overflow == complain_overflow_signed
1532 && !sign)
1533 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1534 && sign > 0))
3956db08
JB		 1535 as_bad (_("relocated field and relocation type differ in signedness"));
1536 else
1537 return other;
1538 return NO_RELOC;
1539 }
252b5132
RH		 1540
1541 if (pcrel)
1542 {
3e73aa7c 1543 if (!sign)
3956db08 1544 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1545 switch (size)
1546 {
1547 case 1: return BFD_RELOC_8_PCREL;
1548 case 2: return BFD_RELOC_16_PCREL;
1549 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1550 case 8: return BFD_RELOC_64_PCREL;
252b5132 1551 }
3956db08 1552 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1553 }
1554 else
1555 {
3956db08 1556 if (sign > 0)
e5cb08ac 1557 switch (size)
3e73aa7c
JH		 1558 {
1559 case 4: return BFD_RELOC_X86_64_32S;
1560 }
1561 else
1562 switch (size)
1563 {
1564 case 1: return BFD_RELOC_8;
1565 case 2: return BFD_RELOC_16;
1566 case 4: return BFD_RELOC_32;
1567 case 8: return BFD_RELOC_64;
1568 }
3956db08
JB		 1569 as_bad (_("cannot do %s %u byte relocation"),
1570 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1571 }
1572
bfb32b52 1573 abort ();
252b5132
RH		 1574 return BFD_RELOC_NONE;
1575}
1576
47926f60
KH		 1577/* Here we decide which fixups can be adjusted to make them relative to
1578 the beginning of the section instead of the symbol. Basically we need
1579 to make sure that the dynamic relocations are done correctly, so in
1580 some cases we force the original symbol to be used. */
1581
252b5132 1582int
e3bb37b5 1583tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 1584{
6d249963 1585#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1586 if (!IS_ELF)
31312f95
AM		 1587 return 1;
1588
a161fe53
AM		 1589 /* Don't adjust pc-relative references to merge sections in 64-bit
1590 mode. */
1591 if (use_rela_relocations
1592 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1593 && fixP->fx_pcrel)
252b5132 1594 return 0;
31312f95 1595
8d01d9a9
AJ		 1596 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1597 and changed later by validate_fix. */
1598 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1599 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1600 return 0;
1601
ce8a8b2f 1602 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1603 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1604 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1605 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1606 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1607 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1608 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1609 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1610 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1611 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1612 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1613 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 1614 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1615 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 1616 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1617 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1618 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1619 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1620 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1621 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1622 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1623 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1624 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1625 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1626 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 1627 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1628 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 1629 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1630 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1631 return 0;
31312f95 1632#endif
252b5132
RH		 1633 return 1;
1634}
252b5132 1635
b4cac588 1636static int
e3bb37b5 1637intel_float_operand (const char *mnemonic)
252b5132 1638{
9306ca4a
JB		 1639 /* Note that the value returned is meaningful only for opcodes with (memory)
1640 operands, hence the code here is free to improperly handle opcodes that
1641 have no operands (for better performance and smaller code). */
1642
1643 if (mnemonic[0] != 'f')
1644 return 0; /* non-math */
1645
1646 switch (mnemonic[1])
1647 {
1648 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1649 the fs segment override prefix not currently handled because no
1650 call path can make opcodes without operands get here */
1651 case 'i':
1652 return 2 /* integer op */;
1653 case 'l':
1654 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1655 return 3; /* fldcw/fldenv */
1656 break;
1657 case 'n':
1658 if (mnemonic[2] != 'o' /* fnop */)
1659 return 3; /* non-waiting control op */
1660 break;
1661 case 'r':
1662 if (mnemonic[2] == 's')
1663 return 3; /* frstor/frstpm */
1664 break;
1665 case 's':
1666 if (mnemonic[2] == 'a')
1667 return 3; /* fsave */
1668 if (mnemonic[2] == 't')
1669 {
1670 switch (mnemonic[3])
1671 {
1672 case 'c': /* fstcw */
1673 case 'd': /* fstdw */
1674 case 'e': /* fstenv */
1675 case 's': /* fsts[gw] */
1676 return 3;
1677 }
1678 }
1679 break;
1680 case 'x':
1681 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1682 return 0; /* fxsave/fxrstor are not really math ops */
1683 break;
1684 }
252b5132 1685
9306ca4a 1686 return 1;
252b5132
RH		 1687}
1688
1689/* This is the guts of the machine-dependent assembler. LINE points to a
1690 machine dependent instruction. This function is supposed to emit
1691 the frags/bytes it assembles to. */
1692
1693void
1694md_assemble (line)
1695 char *line;
1696{
252b5132 1697 int j;
252b5132
RH		 1698 char mnemonic[MAX_MNEM_SIZE];
1699
47926f60 1700 /* Initialize globals. */
252b5132
RH		 1701 memset (&i, '\0', sizeof (i));
1702 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1703 i.reloc[j] = NO_RELOC;
252b5132
RH		 1704 memset (disp_expressions, '\0', sizeof (disp_expressions));
1705 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1706 save_stack_p = save_stack;
252b5132
RH		 1707
1708 /* First parse an instruction mnemonic & call i386_operand for the operands.
1709 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1710 start of a (possibly prefixed) mnemonic. */
252b5132 1711
29b0f896
AM		 1712 line = parse_insn (line, mnemonic);
1713 if (line == NULL)
1714 return;
252b5132 1715
29b0f896
AM		 1716 line = parse_operands (line, mnemonic);
1717 if (line == NULL)
1718 return;
252b5132 1719
4eed87de 1720 /* The order of the immediates should be reversed
050dfa73 1721 for 2 immediates extrq and insertq instructions */
4d456e3d
L		 1722 if ((i.imm_operands == 2)
1723 && ((strcmp (mnemonic, "extrq") == 0)
1724 || (strcmp (mnemonic, "insertq") == 0)))
050dfa73 1725 {
4eed87de
AM		 1726 swap_2_operands (0, 1);
1727 /* "extrq" and insertq" are the only two instructions whose operands
050dfa73
MM		 1728 have to be reversed even though they have two immediate operands.
1729 */
1730 if (intel_syntax)
1731 swap_operands ();
1732 }
1733
29b0f896
AM		 1734 /* Now we've parsed the mnemonic into a set of templates, and have the
1735 operands at hand. */
1736
1737 /* All intel opcodes have reversed operands except for "bound" and
1738 "enter". We also don't reverse intersegment "jmp" and "call"
1739 instructions with 2 immediate operands so that the immediate segment
050dfa73 1740 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 1741 if (intel_syntax
1742 && i.operands > 1
29b0f896 1743 && (strcmp (mnemonic, "bound") != 0)
30123838 1744 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1745 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1746 swap_operands ();
1747
1748 if (i.imm_operands)
1749 optimize_imm ();
1750
b300c311
L		 1751 /* Don't optimize displacement for movabs since it only takes 64bit
1752 displacement. */
1753 if (i.disp_operands
1754 && (flag_code != CODE_64BIT
1755 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1756 optimize_disp ();
1757
1758 /* Next, we find a template that matches the given insn,
1759 making sure the overlap of the given operands types is consistent
1760 with the template operand types. */
252b5132 1761
29b0f896
AM		 1762 if (!match_template ())
1763 return;
252b5132 1764
cd61ebfe
AM		 1765 if (intel_syntax)
1766 {
1767 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1768 if (SYSV386_COMPAT
1769 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
8a2ed489 1770 i.tm.base_opcode ^= Opcode_FloatR;
cd61ebfe
AM		 1771
1772 /* Zap movzx and movsx suffix. The suffix may have been set from
1773 "word ptr" or "byte ptr" on the source operand, but we'll use
1774 the suffix later to choose the destination register. */
1775 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1776 {
1777 if (i.reg_operands < 2
1778 && !i.suffix
1779 && (~i.tm.opcode_modifier
1780 & (No_bSuf
1781 | No_wSuf
1782 | No_lSuf
1783 | No_sSuf
1784 | No_xSuf
1785 | No_qSuf)))
1786 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1787
1788 i.suffix = 0;
1789 }
cd61ebfe 1790 }
24eab124 1791
29b0f896
AM		 1792 if (i.tm.opcode_modifier & FWait)
1793 if (!add_prefix (FWAIT_OPCODE))
1794 return;
252b5132 1795
29b0f896
AM		 1796 /* Check string instruction segment overrides. */
1797 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1798 {
1799 if (!check_string ())
5dd0794d 1800 return;
29b0f896 1801 }
5dd0794d 1802
29b0f896
AM		 1803 if (!process_suffix ())
1804 return;
e413e4e9 1805
29b0f896
AM		 1806 /* Make still unresolved immediate matches conform to size of immediate
1807 given in i.suffix. */
1808 if (!finalize_imm ())
1809 return;
252b5132 1810
29b0f896
AM		 1811 if (i.types[0] & Imm1)
1812 i.imm_operands = 0; /* kludge for shift insns. */
1813 if (i.types[0] & ImplicitRegister)
1814 i.reg_operands--;
1815 if (i.types[1] & ImplicitRegister)
1816 i.reg_operands--;
1817 if (i.types[2] & ImplicitRegister)
1818 i.reg_operands--;
252b5132 1819
29b0f896
AM		 1820 if (i.tm.opcode_modifier & ImmExt)
1821 {
02fc3089
L		 1822 expressionS *exp;
1823
b7d9ef37 1824 if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
ca164297 1825 {
b7d9ef37 1826 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 1827 operands with an opcode suffix which is coded in the same
1828 place as an 8-bit immediate field would be. Here we check
1829 those operands and remove them afterwards. */
1830 unsigned int x;
1831
a4622f40 1832 for (x = 0; x < i.operands; x++)
ca164297
L		 1833 if (i.op[x].regs->reg_num != x)
1834 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
64e74474 1835 i.op[x].regs->reg_name, x + 1, i.tm.name);
ca164297
L		 1836 i.operands = 0;
1837 }
1838
29b0f896
AM		 1839 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1840 opcode suffix which is coded in the same place as an 8-bit
1841 immediate field would be. Here we fake an 8-bit immediate
1842 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1843
29b0f896 1844 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1845
29b0f896
AM		 1846 exp = &im_expressions[i.imm_operands++];
1847 i.op[i.operands].imms = exp;
1848 i.types[i.operands++] = Imm8;
1849 exp->X_op = O_constant;
1850 exp->X_add_number = i.tm.extension_opcode;
1851 i.tm.extension_opcode = None;
1852 }
252b5132 1853
29b0f896
AM		 1854 /* For insns with operands there are more diddles to do to the opcode. */
1855 if (i.operands)
1856 {
1857 if (!process_operands ())
1858 return;
1859 }
1860 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1861 {
1862 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1863 as_warn (_("translating to `%sp'"), i.tm.name);
1864 }
252b5132 1865
29b0f896
AM		 1866 /* Handle conversion of 'int $3' --> special int3 insn. */
1867 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1868 {
1869 i.tm.base_opcode = INT3_OPCODE;
1870 i.imm_operands = 0;
1871 }
252b5132 1872
29b0f896
AM		 1873 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1874 && i.op[0].disps->X_op == O_constant)
1875 {
1876 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1877 the absolute address given by the constant. Since ix86 jumps and
1878 calls are pc relative, we need to generate a reloc. */
1879 i.op[0].disps->X_add_symbol = &abs_symbol;
1880 i.op[0].disps->X_op = O_symbol;
1881 }
252b5132 1882
29b0f896 1883 if ((i.tm.opcode_modifier & Rex64) != 0)
161a04f6 1884 i.rex |= REX_W;
252b5132 1885
29b0f896
AM		 1886 /* For 8 bit registers we need an empty rex prefix. Also if the
1887 instruction already has a prefix, we need to convert old
1888 registers to new ones. */
773f551c 1889
29b0f896
AM		 1890 if (((i.types[0] & Reg8) != 0
1891 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1892 || ((i.types[1] & Reg8) != 0
1893 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1894 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1895 && i.rex != 0))
1896 {
1897 int x;
726c5dcd 1898
29b0f896
AM		 1899 i.rex |= REX_OPCODE;
1900 for (x = 0; x < 2; x++)
1901 {
1902 /* Look for 8 bit operand that uses old registers. */
1903 if ((i.types[x] & Reg8) != 0
1904 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1905 {
29b0f896
AM		 1906 /* In case it is "hi" register, give up. */
1907 if (i.op[x].regs->reg_num > 3)
4eed87de
AM		 1908 as_bad (_("can't encode register '%%%s' in an "
1909 "instruction requiring REX prefix."),
29b0f896 1910 i.op[x].regs->reg_name);
773f551c 1911
29b0f896
AM		 1912 /* Otherwise it is equivalent to the extended register.
1913 Since the encoding doesn't change this is merely
1914 cosmetic cleanup for debug output. */
1915
1916 i.op[x].regs = i.op[x].regs + 8;
773f551c 1917 }
29b0f896
AM		 1918 }
1919 }
773f551c 1920
29b0f896
AM		 1921 if (i.rex != 0)
1922 add_prefix (REX_OPCODE | i.rex);
1923
1924 /* We are ready to output the insn. */
1925 output_insn ();
1926}
1927
1928static char *
e3bb37b5 1929parse_insn (char *line, char *mnemonic)
29b0f896
AM		 1930{
1931 char *l = line;
1932 char *token_start = l;
1933 char *mnem_p;
5c6af06e
JB		 1934 int supported;
1935 const template *t;
29b0f896
AM		 1936
1937 /* Non-zero if we found a prefix only acceptable with string insns. */
1938 const char *expecting_string_instruction = NULL;
45288df1 1939
29b0f896
AM		 1940 while (1)
1941 {
1942 mnem_p = mnemonic;
1943 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1944 {
1945 mnem_p++;
1946 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1947 {
29b0f896
AM		 1948 as_bad (_("no such instruction: `%s'"), token_start);
1949 return NULL;
1950 }
1951 l++;
1952 }
1953 if (!is_space_char (*l)
1954 && *l != END_OF_INSN
e44823cf
JB		 1955 && (intel_syntax
1956 || (*l != PREFIX_SEPARATOR
1957 && *l != ',')))
29b0f896
AM		 1958 {
1959 as_bad (_("invalid character %s in mnemonic"),
1960 output_invalid (*l));
1961 return NULL;
1962 }
1963 if (token_start == l)
1964 {
e44823cf 1965 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 1966 as_bad (_("expecting prefix; got nothing"));
1967 else
1968 as_bad (_("expecting mnemonic; got nothing"));
1969 return NULL;
1970 }
45288df1 1971
29b0f896
AM		 1972 /* Look up instruction (or prefix) via hash table. */
1973 current_templates = hash_find (op_hash, mnemonic);
47926f60 1974
29b0f896
AM		 1975 if (*l != END_OF_INSN
1976 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1977 && current_templates
1978 && (current_templates->start->opcode_modifier & IsPrefix))
1979 {
2dd88dca
JB		 1980 if (current_templates->start->cpu_flags
1981 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1982 {
1983 as_bad ((flag_code != CODE_64BIT
1984 ? _("`%s' is only supported in 64-bit mode")
1985 : _("`%s' is not supported in 64-bit mode")),
1986 current_templates->start->name);
1987 return NULL;
1988 }
29b0f896
AM		 1989 /* If we are in 16-bit mode, do not allow addr16 or data16.
1990 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1991 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1992 && flag_code != CODE_64BIT
1993 && (((current_templates->start->opcode_modifier & Size32) != 0)
1994 ^ (flag_code == CODE_16BIT)))
1995 {
1996 as_bad (_("redundant %s prefix"),
1997 current_templates->start->name);
1998 return NULL;
45288df1 1999 }
29b0f896
AM		 2000 /* Add prefix, checking for repeated prefixes. */
2001 switch (add_prefix (current_templates->start->base_opcode))
2002 {
2003 case 0:
2004 return NULL;
2005 case 2:
2006 expecting_string_instruction = current_templates->start->name;
2007 break;
2008 }
2009 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2010 token_start = ++l;
2011 }
2012 else
2013 break;
2014 }
45288df1 2015
29b0f896
AM		 2016 if (!current_templates)
2017 {
2018 /* See if we can get a match by trimming off a suffix. */
2019 switch (mnem_p[-1])
2020 {
2021 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2022 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2023 i.suffix = SHORT_MNEM_SUFFIX;
2024 else
29b0f896
AM		 2025 case BYTE_MNEM_SUFFIX:
2026 case QWORD_MNEM_SUFFIX:
2027 i.suffix = mnem_p[-1];
2028 mnem_p[-1] = '\0';
2029 current_templates = hash_find (op_hash, mnemonic);
2030 break;
2031 case SHORT_MNEM_SUFFIX:
2032 case LONG_MNEM_SUFFIX:
2033 if (!intel_syntax)
2034 {
2035 i.suffix = mnem_p[-1];
2036 mnem_p[-1] = '\0';
2037 current_templates = hash_find (op_hash, mnemonic);
2038 }
2039 break;
252b5132 2040
29b0f896
AM		 2041 /* Intel Syntax. */
2042 case 'd':
2043 if (intel_syntax)
2044 {
9306ca4a 2045 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2046 i.suffix = SHORT_MNEM_SUFFIX;
2047 else
2048 i.suffix = LONG_MNEM_SUFFIX;
2049 mnem_p[-1] = '\0';
2050 current_templates = hash_find (op_hash, mnemonic);
2051 }
2052 break;
2053 }
2054 if (!current_templates)
2055 {
2056 as_bad (_("no such instruction: `%s'"), token_start);
2057 return NULL;
2058 }
2059 }
252b5132 2060
29b0f896
AM		 2061 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2062 {
2063 /* Check for a branch hint. We allow ",pt" and ",pn" for
2064 predict taken and predict not taken respectively.
2065 I'm not sure that branch hints actually do anything on loop
2066 and jcxz insns (JumpByte) for current Pentium4 chips. They
2067 may work in the future and it doesn't hurt to accept them
2068 now. */
2069 if (l[0] == ',' && l[1] == 'p')
2070 {
2071 if (l[2] == 't')
2072 {
2073 if (!add_prefix (DS_PREFIX_OPCODE))
2074 return NULL;
2075 l += 3;
2076 }
2077 else if (l[2] == 'n')
2078 {
2079 if (!add_prefix (CS_PREFIX_OPCODE))
2080 return NULL;
2081 l += 3;
2082 }
2083 }
2084 }
2085 /* Any other comma loses. */
2086 if (*l == ',')
2087 {
2088 as_bad (_("invalid character %s in mnemonic"),
2089 output_invalid (*l));
2090 return NULL;
2091 }
252b5132 2092
29b0f896 2093 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2094 supported = 0;
2095 for (t = current_templates->start; t < current_templates->end; ++t)
2096 {
2097 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2098 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
64e74474 2099 supported |= 1;
5c6af06e 2100 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
64e74474 2101 supported |= 2;
5c6af06e
JB		 2102 }
2103 if (!(supported & 2))
2104 {
2105 as_bad (flag_code == CODE_64BIT
2106 ? _("`%s' is not supported in 64-bit mode")
2107 : _("`%s' is only supported in 64-bit mode"),
2108 current_templates->start->name);
2109 return NULL;
2110 }
2111 if (!(supported & 1))
29b0f896 2112 {
5c6af06e
JB		 2113 as_warn (_("`%s' is not supported on `%s%s'"),
2114 current_templates->start->name,
2115 cpu_arch_name,
2116 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 2117 }
2118 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2119 {
2120 as_warn (_("use .code16 to ensure correct addressing mode"));
2121 }
252b5132 2122
29b0f896 2123 /* Check for rep/repne without a string instruction. */
f41bbced 2124 if (expecting_string_instruction)
29b0f896 2125 {
f41bbced
JB		 2126 static templates override;
2127
2128 for (t = current_templates->start; t < current_templates->end; ++t)
2129 if (t->opcode_modifier & IsString)
2130 break;
2131 if (t >= current_templates->end)
2132 {
2133 as_bad (_("expecting string instruction after `%s'"),
64e74474 2134 expecting_string_instruction);
f41bbced
JB		 2135 return NULL;
2136 }
2137 for (override.start = t; t < current_templates->end; ++t)
2138 if (!(t->opcode_modifier & IsString))
2139 break;
2140 override.end = t;
2141 current_templates = &override;
29b0f896 2142 }
252b5132 2143
29b0f896
AM		 2144 return l;
2145}
252b5132 2146
29b0f896 2147static char *
e3bb37b5 2148parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 2149{
2150 char *token_start;
3138f287 2151
29b0f896
AM		 2152 /* 1 if operand is pending after ','. */
2153 unsigned int expecting_operand = 0;
252b5132 2154
29b0f896
AM		 2155 /* Non-zero if operand parens not balanced. */
2156 unsigned int paren_not_balanced;
2157
2158 while (*l != END_OF_INSN)
2159 {
2160 /* Skip optional white space before operand. */
2161 if (is_space_char (*l))
2162 ++l;
2163 if (!is_operand_char (*l) && *l != END_OF_INSN)
2164 {
2165 as_bad (_("invalid character %s before operand %d"),
2166 output_invalid (*l),
2167 i.operands + 1);
2168 return NULL;
2169 }
2170 token_start = l; /* after white space */
2171 paren_not_balanced = 0;
2172 while (paren_not_balanced || *l != ',')
2173 {
2174 if (*l == END_OF_INSN)
2175 {
2176 if (paren_not_balanced)
2177 {
2178 if (!intel_syntax)
2179 as_bad (_("unbalanced parenthesis in operand %d."),
2180 i.operands + 1);
2181 else
2182 as_bad (_("unbalanced brackets in operand %d."),
2183 i.operands + 1);
2184 return NULL;
2185 }
2186 else
2187 break; /* we are done */
2188 }
2189 else if (!is_operand_char (*l) && !is_space_char (*l))
2190 {
2191 as_bad (_("invalid character %s in operand %d"),
2192 output_invalid (*l),
2193 i.operands + 1);
2194 return NULL;
2195 }
2196 if (!intel_syntax)
2197 {
2198 if (*l == '(')
2199 ++paren_not_balanced;
2200 if (*l == ')')
2201 --paren_not_balanced;
2202 }
2203 else
2204 {
2205 if (*l == '[')
2206 ++paren_not_balanced;
2207 if (*l == ']')
2208 --paren_not_balanced;
2209 }
2210 l++;
2211 }
2212 if (l != token_start)
2213 { /* Yes, we've read in another operand. */
2214 unsigned int operand_ok;
2215 this_operand = i.operands++;
2216 if (i.operands > MAX_OPERANDS)
2217 {
2218 as_bad (_("spurious operands; (%d operands/instruction max)"),
2219 MAX_OPERANDS);
2220 return NULL;
2221 }
2222 /* Now parse operand adding info to 'i' as we go along. */
2223 END_STRING_AND_SAVE (l);
2224
2225 if (intel_syntax)
2226 operand_ok =
2227 i386_intel_operand (token_start,
2228 intel_float_operand (mnemonic));
2229 else
2230 operand_ok = i386_operand (token_start);
2231
2232 RESTORE_END_STRING (l);
2233 if (!operand_ok)
2234 return NULL;
2235 }
2236 else
2237 {
2238 if (expecting_operand)
2239 {
2240 expecting_operand_after_comma:
2241 as_bad (_("expecting operand after ','; got nothing"));
2242 return NULL;
2243 }
2244 if (*l == ',')
2245 {
2246 as_bad (_("expecting operand before ','; got nothing"));
2247 return NULL;
2248 }
2249 }
7f3f1ea2 2250
29b0f896
AM		 2251 /* Now *l must be either ',' or END_OF_INSN. */
2252 if (*l == ',')
2253 {
2254 if (*++l == END_OF_INSN)
2255 {
2256 /* Just skip it, if it's \n complain. */
2257 goto expecting_operand_after_comma;
2258 }
2259 expecting_operand = 1;
2260 }
2261 }
2262 return l;
2263}
7f3f1ea2 2264
050dfa73 2265static void
4d456e3d 2266swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 2267{
2268 union i386_op temp_op;
2269 unsigned int temp_type;
2270 enum bfd_reloc_code_real temp_reloc;
4eed87de 2271
050dfa73
MM		 2272 temp_type = i.types[xchg2];
2273 i.types[xchg2] = i.types[xchg1];
2274 i.types[xchg1] = temp_type;
2275 temp_op = i.op[xchg2];
2276 i.op[xchg2] = i.op[xchg1];
2277 i.op[xchg1] = temp_op;
2278 temp_reloc = i.reloc[xchg2];
2279 i.reloc[xchg2] = i.reloc[xchg1];
2280 i.reloc[xchg1] = temp_reloc;
2281}
2282
29b0f896 2283static void
e3bb37b5 2284swap_operands (void)
29b0f896 2285{
b7c61d9a 2286 switch (i.operands)
050dfa73 2287 {
b7c61d9a 2288 case 4:
4d456e3d 2289 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 2290 case 3:
2291 case 2:
4d456e3d 2292 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 2293 break;
2294 default:
2295 abort ();
29b0f896 2296 }
29b0f896
AM		 2297
2298 if (i.mem_operands == 2)
2299 {
2300 const seg_entry *temp_seg;
2301 temp_seg = i.seg[0];
2302 i.seg[0] = i.seg[1];
2303 i.seg[1] = temp_seg;
2304 }
2305}
252b5132 2306
29b0f896
AM		 2307/* Try to ensure constant immediates are represented in the smallest
2308 opcode possible. */
2309static void
e3bb37b5 2310optimize_imm (void)
29b0f896
AM		 2311{
2312 char guess_suffix = 0;
2313 int op;
252b5132 2314
29b0f896
AM		 2315 if (i.suffix)
2316 guess_suffix = i.suffix;
2317 else if (i.reg_operands)
2318 {
2319 /* Figure out a suffix from the last register operand specified.
2320 We can't do this properly yet, ie. excluding InOutPortReg,
2321 but the following works for instructions with immediates.
2322 In any case, we can't set i.suffix yet. */
2323 for (op = i.operands; --op >= 0;)
2324 if (i.types[op] & Reg)
252b5132 2325 {
29b0f896
AM		 2326 if (i.types[op] & Reg8)
2327 guess_suffix = BYTE_MNEM_SUFFIX;
2328 else if (i.types[op] & Reg16)
2329 guess_suffix = WORD_MNEM_SUFFIX;
2330 else if (i.types[op] & Reg32)
2331 guess_suffix = LONG_MNEM_SUFFIX;
2332 else if (i.types[op] & Reg64)
2333 guess_suffix = QWORD_MNEM_SUFFIX;
2334 break;
252b5132 2335 }
29b0f896
AM		 2336 }
2337 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2338 guess_suffix = WORD_MNEM_SUFFIX;
2339
2340 for (op = i.operands; --op >= 0;)
2341 if (i.types[op] & Imm)
2342 {
2343 switch (i.op[op].imms->X_op)
252b5132 2344 {
29b0f896
AM		 2345 case O_constant:
2346 /* If a suffix is given, this operand may be shortened. */
2347 switch (guess_suffix)
252b5132 2348 {
29b0f896
AM		 2349 case LONG_MNEM_SUFFIX:
2350 i.types[op] |= Imm32 | Imm64;
2351 break;
2352 case WORD_MNEM_SUFFIX:
2353 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2354 break;
2355 case BYTE_MNEM_SUFFIX:
2356 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2357 break;
252b5132 2358 }
252b5132 2359
29b0f896
AM		 2360 /* If this operand is at most 16 bits, convert it
2361 to a signed 16 bit number before trying to see
2362 whether it will fit in an even smaller size.
2363 This allows a 16-bit operand such as $0xffe0 to
2364 be recognised as within Imm8S range. */
2365 if ((i.types[op] & Imm16)
2366 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2367 {
29b0f896
AM		 2368 i.op[op].imms->X_add_number =
2369 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2370 }
2371 if ((i.types[op] & Imm32)
2372 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2373 == 0))
2374 {
2375 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2376 ^ ((offsetT) 1 << 31))
2377 - ((offsetT) 1 << 31));
2378 }
2379 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2380
29b0f896
AM		 2381 /* We must avoid matching of Imm32 templates when 64bit
2382 only immediate is available. */
2383 if (guess_suffix == QWORD_MNEM_SUFFIX)
2384 i.types[op] &= ~Imm32;
2385 break;
252b5132 2386
29b0f896
AM		 2387 case O_absent:
2388 case O_register:
2389 abort ();
2390
2391 /* Symbols and expressions. */
2392 default:
9cd96992
JB		 2393 /* Convert symbolic operand to proper sizes for matching, but don't
2394 prevent matching a set of insns that only supports sizes other
2395 than those matching the insn suffix. */
2396 {
2397 unsigned int mask, allowed = 0;
2398 const template *t;
2399
4eed87de
AM		 2400 for (t = current_templates->start;
2401 t < current_templates->end;
2402 ++t)
2403 allowed |= t->operand_types[op];
9cd96992
JB		 2404 switch (guess_suffix)
2405 {
2406 case QWORD_MNEM_SUFFIX:
2407 mask = Imm64 | Imm32S;
2408 break;
2409 case LONG_MNEM_SUFFIX:
2410 mask = Imm32;
2411 break;
2412 case WORD_MNEM_SUFFIX:
2413 mask = Imm16;
2414 break;
2415 case BYTE_MNEM_SUFFIX:
2416 mask = Imm8;
2417 break;
2418 default:
2419 mask = 0;
2420 break;
2421 }
64e74474
AM		 2422 if (mask & allowed)
2423 i.types[op] &= mask;
9cd96992 2424 }
29b0f896 2425 break;
252b5132 2426 }
29b0f896
AM		 2427 }
2428}
47926f60 2429
29b0f896
AM		 2430/* Try to use the smallest displacement type too. */
2431static void
e3bb37b5 2432optimize_disp (void)
29b0f896
AM		 2433{
2434 int op;
3e73aa7c 2435
29b0f896 2436 for (op = i.operands; --op >= 0;)
b300c311 2437 if (i.types[op] & Disp)
252b5132 2438 {
b300c311 2439 if (i.op[op].disps->X_op == O_constant)
252b5132 2440 {
b300c311 2441 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2442
b300c311
L		 2443 if ((i.types[op] & Disp16)
2444 && (disp & ~(offsetT) 0xffff) == 0)
2445 {
2446 /* If this operand is at most 16 bits, convert
2447 to a signed 16 bit number and don't use 64bit
2448 displacement. */
2449 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2450 i.types[op] &= ~Disp64;
2451 }
2452 if ((i.types[op] & Disp32)
2453 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2454 {
2455 /* If this operand is at most 32 bits, convert
2456 to a signed 32 bit number and don't use 64bit
2457 displacement. */
2458 disp &= (((offsetT) 2 << 31) - 1);
2459 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2460 i.types[op] &= ~Disp64;
2461 }
2462 if (!disp && (i.types[op] & BaseIndex))
2463 {
2464 i.types[op] &= ~Disp;
2465 i.op[op].disps = 0;
2466 i.disp_operands--;
2467 }
2468 else if (flag_code == CODE_64BIT)
2469 {
2470 if (fits_in_signed_long (disp))
28a9d8f5
L		 2471 {
2472 i.types[op] &= ~Disp64;
2473 i.types[op] |= Disp32S;
2474 }
b300c311
L		 2475 if (fits_in_unsigned_long (disp))
2476 i.types[op] |= Disp32;
2477 }
2478 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2479 && fits_in_signed_byte (disp))
2480 i.types[op] |= Disp8;
252b5132 2481 }
67a4f2b7
AO		 2482 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2483 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2484 {
2485 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2486 i.op[op].disps, 0, i.reloc[op]);
2487 i.types[op] &= ~Disp;
2488 }
2489 else
b300c311
L		 2490 /* We only support 64bit displacement on constants. */
2491 i.types[op] &= ~Disp64;
252b5132 2492 }
29b0f896
AM		 2493}
2494
2495static int
e3bb37b5 2496match_template (void)
29b0f896
AM		 2497{
2498 /* Points to template once we've found it. */
2499 const template *t;
f48ff2ae 2500 unsigned int overlap0, overlap1, overlap2, overlap3;
29b0f896
AM		 2501 unsigned int found_reverse_match;
2502 int suffix_check;
f48ff2ae 2503 unsigned int operand_types [MAX_OPERANDS];
539e75ad 2504 int addr_prefix_disp;
a5c311ca 2505 unsigned int j;
29b0f896 2506
f48ff2ae
L		 2507#if MAX_OPERANDS != 4
2508# error "MAX_OPERANDS must be 4."
2509#endif
2510
29b0f896
AM		 2511#define MATCH(overlap, given, template) \
2512 ((overlap & ~JumpAbsolute) \
2513 && (((given) & (BaseIndex | JumpAbsolute)) \
2514 == ((overlap) & (BaseIndex | JumpAbsolute))))
2515
2516 /* If given types r0 and r1 are registers they must be of the same type
2517 unless the expected operand type register overlap is null.
2518 Note that Acc in a template matches every size of reg. */
2519#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2520 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2521 || ((g0) & Reg) == ((g1) & Reg) \
2522 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2523
2524 overlap0 = 0;
2525 overlap1 = 0;
2526 overlap2 = 0;
f48ff2ae 2527 overlap3 = 0;
29b0f896 2528 found_reverse_match = 0;
a5c311ca
L		 2529 for (j = 0; j < MAX_OPERANDS; j++)
2530 operand_types [j] = 0;
539e75ad 2531 addr_prefix_disp = -1;
29b0f896
AM		 2532 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2533 ? No_bSuf
2534 : (i.suffix == WORD_MNEM_SUFFIX
2535 ? No_wSuf
2536 : (i.suffix == SHORT_MNEM_SUFFIX
2537 ? No_sSuf
2538 : (i.suffix == LONG_MNEM_SUFFIX
2539 ? No_lSuf
2540 : (i.suffix == QWORD_MNEM_SUFFIX
2541 ? No_qSuf
2542 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2543 ? No_xSuf : 0))))));
2544
45aa61fe 2545 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 2546 {
539e75ad
L		 2547 addr_prefix_disp = -1;
2548
29b0f896
AM		 2549 /* Must have right number of operands. */
2550 if (i.operands != t->operands)
2551 continue;
2552
2553 /* Check the suffix, except for some instructions in intel mode. */
2554 if ((t->opcode_modifier & suffix_check)
2555 && !(intel_syntax
9306ca4a 2556 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2557 continue;
2558
a5c311ca
L		 2559 for (j = 0; j < MAX_OPERANDS; j++)
2560 operand_types [j] = t->operand_types [j];
539e75ad 2561
45aa61fe
AM		 2562 /* In general, don't allow 64-bit operands in 32-bit mode. */
2563 if (i.suffix == QWORD_MNEM_SUFFIX
2564 && flag_code != CODE_64BIT
2565 && (intel_syntax
2566 ? (!(t->opcode_modifier & IgnoreSize)
2567 && !intel_float_operand (t->name))
2568 : intel_float_operand (t->name) != 2)
539e75ad
L		 2569 && (!(operand_types[0] & (RegMMX | RegXMM))
2570 || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
45aa61fe
AM		 2571 && (t->base_opcode != 0x0fc7
2572 || t->extension_opcode != 1 /* cmpxchg8b */))
2573 continue;
2574
29b0f896
AM		 2575 /* Do not verify operands when there are none. */
2576 else if (!t->operands)
2577 {
2578 if (t->cpu_flags & ~cpu_arch_flags)
2579 continue;
2580 /* We've found a match; break out of loop. */
2581 break;
2582 }
252b5132 2583
539e75ad
L		 2584 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2585 into Disp32/Disp16/Disp32 operand. */
2586 if (i.prefix[ADDR_PREFIX] != 0)
2587 {
a5c311ca 2588 unsigned int DispOn = 0, DispOff = 0;
539e75ad
L		 2589
2590 switch (flag_code)
2591 {
2592 case CODE_16BIT:
2593 DispOn = Disp32;
2594 DispOff = Disp16;
2595 break;
2596 case CODE_32BIT:
2597 DispOn = Disp16;
2598 DispOff = Disp32;
2599 break;
2600 case CODE_64BIT:
2601 DispOn = Disp32;
2602 DispOff = Disp64;
2603 break;
2604 }
2605
f48ff2ae 2606 for (j = 0; j < MAX_OPERANDS; j++)
539e75ad
L		 2607 {
2608 /* There should be only one Disp operand. */
2609 if ((operand_types[j] & DispOff))
2610 {
2611 addr_prefix_disp = j;
2612 operand_types[j] |= DispOn;
2613 operand_types[j] &= ~DispOff;
2614 break;
2615 }
2616 }
2617 }
2618
2619 overlap0 = i.types[0] & operand_types[0];
29b0f896
AM		 2620 switch (t->operands)
2621 {
2622 case 1:
539e75ad 2623 if (!MATCH (overlap0, i.types[0], operand_types[0]))
29b0f896
AM		 2624 continue;
2625 break;
2626 case 2:
8b38ad71
L		 2627 /* xchg %eax, %eax is a special case. It is an aliase for nop
2628 only in 32bit mode and we can use opcode 0x90. In 64bit
2629 mode, we can't use 0x90 for xchg %eax, %eax since it should
2630 zero-extend %eax to %rax. */
2631 if (flag_code == CODE_64BIT
2632 && t->base_opcode == 0x90
2633 && i.types [0] == (Acc | Reg32)
2634 && i.types [1] == (Acc | Reg32))
2635 continue;
29b0f896 2636 case 3:
f48ff2ae 2637 case 4:
539e75ad
L		 2638 overlap1 = i.types[1] & operand_types[1];
2639 if (!MATCH (overlap0, i.types[0], operand_types[0])
2640 || !MATCH (overlap1, i.types[1], operand_types[1])
cb712a9e 2641 /* monitor in SSE3 is a very special case. The first
708587a4 2642 register and the second register may have different
cb712a9e
L		 2643 sizes. */
2644 || !((t->base_opcode == 0x0f01
2645 && t->extension_opcode == 0xc8)
2646 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2647 operand_types[0],
cb712a9e 2648 overlap1, i.types[1],
539e75ad 2649 operand_types[1])))
29b0f896
AM		 2650 {
2651 /* Check if other direction is valid ... */
2652 if ((t->opcode_modifier & (D | FloatD)) == 0)
2653 continue;
2654
2655 /* Try reversing direction of operands. */
539e75ad
L		 2656 overlap0 = i.types[0] & operand_types[1];
2657 overlap1 = i.types[1] & operand_types[0];
2658 if (!MATCH (overlap0, i.types[0], operand_types[1])
2659 || !MATCH (overlap1, i.types[1], operand_types[0])
29b0f896 2660 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2661 operand_types[1],
29b0f896 2662 overlap1, i.types[1],
539e75ad 2663 operand_types[0]))
29b0f896
AM		 2664 {
2665 /* Does not match either direction. */
2666 continue;
2667 }
2668 /* found_reverse_match holds which of D or FloatDR
2669 we've found. */
8a2ed489
L		 2670 if ((t->opcode_modifier & D))
2671 found_reverse_match = Opcode_D;
2672 else if ((t->opcode_modifier & FloatD))
2673 found_reverse_match = Opcode_FloatD;
2674 else
2675 found_reverse_match = 0;
2676 if ((t->opcode_modifier & FloatR))
2677 found_reverse_match |= Opcode_FloatR;
29b0f896 2678 }
f48ff2ae 2679 else
29b0f896 2680 {
f48ff2ae 2681 /* Found a forward 2 operand match here. */
d1cbb4db
L		 2682 switch (t->operands)
2683 {
2684 case 4:
2685 overlap3 = i.types[3] & operand_types[3];
2686 case 3:
2687 overlap2 = i.types[2] & operand_types[2];
2688 break;
2689 }
29b0f896 2690
f48ff2ae
L		 2691 switch (t->operands)
2692 {
2693 case 4:
2694 if (!MATCH (overlap3, i.types[3], operand_types[3])
2695 || !CONSISTENT_REGISTER_MATCH (overlap2,
2696 i.types[2],
2697 operand_types[2],
2698 overlap3,
2699 i.types[3],
2700 operand_types[3]))
2701 continue;
2702 case 3:
2703 /* Here we make use of the fact that there are no
2704 reverse match 3 operand instructions, and all 3
2705 operand instructions only need to be checked for
2706 register consistency between operands 2 and 3. */
2707 if (!MATCH (overlap2, i.types[2], operand_types[2])
2708 || !CONSISTENT_REGISTER_MATCH (overlap1,
2709 i.types[1],
2710 operand_types[1],
2711 overlap2,
2712 i.types[2],
2713 operand_types[2]))
2714 continue;
2715 break;
2716 }
29b0f896 2717 }
f48ff2ae 2718 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 2719 slip through to break. */
2720 }
2721 if (t->cpu_flags & ~cpu_arch_flags)
2722 {
2723 found_reverse_match = 0;
2724 continue;
2725 }
2726 /* We've found a match; break out of loop. */
2727 break;
2728 }
2729
2730 if (t == current_templates->end)
2731 {
2732 /* We found no match. */
2733 as_bad (_("suffix or operands invalid for `%s'"),
2734 current_templates->start->name);
2735 return 0;
2736 }
252b5132 2737
29b0f896
AM		 2738 if (!quiet_warnings)
2739 {
2740 if (!intel_syntax
2741 && ((i.types[0] & JumpAbsolute)
539e75ad 2742 != (operand_types[0] & JumpAbsolute)))
29b0f896
AM		 2743 {
2744 as_warn (_("indirect %s without `*'"), t->name);
2745 }
2746
2747 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2748 == (IsPrefix | IgnoreSize))
2749 {
2750 /* Warn them that a data or address size prefix doesn't
2751 affect assembly of the next line of code. */
2752 as_warn (_("stand-alone `%s' prefix"), t->name);
2753 }
2754 }
2755
2756 /* Copy the template we found. */
2757 i.tm = *t;
539e75ad
L		 2758
2759 if (addr_prefix_disp != -1)
2760 i.tm.operand_types[addr_prefix_disp]
2761 = operand_types[addr_prefix_disp];
2762
29b0f896
AM		 2763 if (found_reverse_match)
2764 {
2765 /* If we found a reverse match we must alter the opcode
2766 direction bit. found_reverse_match holds bits to change
2767 (different for int & float insns). */
2768
2769 i.tm.base_opcode ^= found_reverse_match;
2770
539e75ad
L		 2771 i.tm.operand_types[0] = operand_types[1];
2772 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 2773 }
2774
2775 return 1;
2776}
2777
2778static int
e3bb37b5 2779check_string (void)
29b0f896
AM		 2780{
2781 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2782 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2783 {
2784 if (i.seg[0] != NULL && i.seg[0] != &es)
2785 {
2786 as_bad (_("`%s' operand %d must use `%%es' segment"),
2787 i.tm.name,
2788 mem_op + 1);
2789 return 0;
2790 }
2791 /* There's only ever one segment override allowed per instruction.
2792 This instruction possibly has a legal segment override on the
2793 second operand, so copy the segment to where non-string
2794 instructions store it, allowing common code. */
2795 i.seg[0] = i.seg[1];
2796 }
2797 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2798 {
2799 if (i.seg[1] != NULL && i.seg[1] != &es)
2800 {
2801 as_bad (_("`%s' operand %d must use `%%es' segment"),
2802 i.tm.name,
2803 mem_op + 2);
2804 return 0;
2805 }
2806 }
2807 return 1;
2808}
2809
2810static int
543613e9 2811process_suffix (void)
29b0f896
AM		 2812{
2813 /* If matched instruction specifies an explicit instruction mnemonic
2814 suffix, use it. */
2815 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2816 {
2817 if (i.tm.opcode_modifier & Size16)
2818 i.suffix = WORD_MNEM_SUFFIX;
2819 else if (i.tm.opcode_modifier & Size64)
2820 i.suffix = QWORD_MNEM_SUFFIX;
2821 else
2822 i.suffix = LONG_MNEM_SUFFIX;
2823 }
2824 else if (i.reg_operands)
2825 {
2826 /* If there's no instruction mnemonic suffix we try to invent one
2827 based on register operands. */
2828 if (!i.suffix)
2829 {
2830 /* We take i.suffix from the last register operand specified,
2831 Destination register type is more significant than source
2832 register type. */
2833 int op;
543613e9 2834
29b0f896
AM		 2835 for (op = i.operands; --op >= 0;)
2836 if ((i.types[op] & Reg)
2837 && !(i.tm.operand_types[op] & InOutPortReg))
2838 {
2839 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2840 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2841 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2842 LONG_MNEM_SUFFIX);
2843 break;
2844 }
2845 }
2846 else if (i.suffix == BYTE_MNEM_SUFFIX)
2847 {
2848 if (!check_byte_reg ())
2849 return 0;
2850 }
2851 else if (i.suffix == LONG_MNEM_SUFFIX)
2852 {
2853 if (!check_long_reg ())
2854 return 0;
2855 }
2856 else if (i.suffix == QWORD_MNEM_SUFFIX)
2857 {
2858 if (!check_qword_reg ())
2859 return 0;
2860 }
2861 else if (i.suffix == WORD_MNEM_SUFFIX)
2862 {
2863 if (!check_word_reg ())
2864 return 0;
2865 }
2866 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2867 /* Do nothing if the instruction is going to ignore the prefix. */
2868 ;
2869 else
2870 abort ();
2871 }
9306ca4a
JB		 2872 else if ((i.tm.opcode_modifier & DefaultSize)
2873 && !i.suffix
2874 /* exclude fldenv/frstor/fsave/fstenv */
2875 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2876 {
2877 i.suffix = stackop_size;
2878 }
9306ca4a
JB		 2879 else if (intel_syntax
2880 && !i.suffix
2881 && ((i.tm.operand_types[0] & JumpAbsolute)
64e74474
AM		 2882 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2883 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2884 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 2885 {
2886 switch (flag_code)
2887 {
2888 case CODE_64BIT:
2889 if (!(i.tm.opcode_modifier & No_qSuf))
2890 {
2891 i.suffix = QWORD_MNEM_SUFFIX;
2892 break;
2893 }
2894 case CODE_32BIT:
2895 if (!(i.tm.opcode_modifier & No_lSuf))
2896 i.suffix = LONG_MNEM_SUFFIX;
2897 break;
2898 case CODE_16BIT:
2899 if (!(i.tm.opcode_modifier & No_wSuf))
2900 i.suffix = WORD_MNEM_SUFFIX;
2901 break;
2902 }
2903 }
252b5132 2904
9306ca4a 2905 if (!i.suffix)
29b0f896 2906 {
9306ca4a
JB		 2907 if (!intel_syntax)
2908 {
2909 if (i.tm.opcode_modifier & W)
2910 {
4eed87de
AM		 2911 as_bad (_("no instruction mnemonic suffix given and "
2912 "no register operands; can't size instruction"));
9306ca4a
JB		 2913 return 0;
2914 }
2915 }
2916 else
2917 {
64e74474
AM		 2918 unsigned int suffixes = (~i.tm.opcode_modifier
2919 & (No_bSuf
2920 | No_wSuf
2921 | No_lSuf
2922 | No_sSuf
2923 | No_xSuf
2924 | No_qSuf));
9306ca4a
JB		 2925
2926 if ((i.tm.opcode_modifier & W)
2927 || ((suffixes & (suffixes - 1))
2928 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2929 {
2930 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2931 return 0;
2932 }
2933 }
29b0f896 2934 }
252b5132 2935
9306ca4a
JB		 2936 /* Change the opcode based on the operand size given by i.suffix;
2937 We don't need to change things for byte insns. */
2938
29b0f896
AM		 2939 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2940 {
2941 /* It's not a byte, select word/dword operation. */
2942 if (i.tm.opcode_modifier & W)
2943 {
2944 if (i.tm.opcode_modifier & ShortForm)
2945 i.tm.base_opcode |= 8;
2946 else
2947 i.tm.base_opcode |= 1;
2948 }
0f3f3d8b 2949
29b0f896
AM		 2950 /* Now select between word & dword operations via the operand
2951 size prefix, except for instructions that will ignore this
2952 prefix anyway. */
cb712a9e
L		 2953 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
2954 {
2955 /* monitor in SSE3 is a very special case. The default size
2956 of AX is the size of mode. The address size override
2957 prefix will change the size of AX. */
2958 if (i.op->regs[0].reg_type &
2959 (flag_code == CODE_32BIT ? Reg16 : Reg32))
2960 if (!add_prefix (ADDR_PREFIX_OPCODE))
2961 return 0;
2962 }
2963 else if (i.suffix != QWORD_MNEM_SUFFIX
2964 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2965 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2966 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2967 || (flag_code == CODE_64BIT
2968 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2969 {
2970 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 2971
29b0f896
AM		 2972 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2973 prefix = ADDR_PREFIX_OPCODE;
252b5132 2974
29b0f896
AM		 2975 if (!add_prefix (prefix))
2976 return 0;
24eab124 2977 }
252b5132 2978
29b0f896
AM		 2979 /* Set mode64 for an operand. */
2980 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2981 && flag_code == CODE_64BIT
29b0f896 2982 && (i.tm.opcode_modifier & NoRex64) == 0)
46e883c5
L		 2983 {
2984 /* Special case for xchg %rax,%rax. It is NOP and doesn't
2985 need rex64. */
2986 if (i.operands != 2
2987 || i.types [0] != (Acc | Reg64)
2988 || i.types [1] != (Acc | Reg64)
13a1e313 2989 || i.tm.base_opcode != 0x90)
f6bee062 2990 i.rex |= REX_W;
46e883c5 2991 }
3e73aa7c 2992
29b0f896
AM		 2993 /* Size floating point instruction. */
2994 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 2995 if (i.tm.opcode_modifier & FloatMF)
2996 i.tm.base_opcode ^= 4;
29b0f896 2997 }
7ecd2f8b 2998
29b0f896
AM		 2999 return 1;
3000}
3e73aa7c 3001
29b0f896 3002static int
543613e9 3003check_byte_reg (void)
29b0f896
AM		 3004{
3005 int op;
543613e9 3006
29b0f896
AM		 3007 for (op = i.operands; --op >= 0;)
3008 {
3009 /* If this is an eight bit register, it's OK. If it's the 16 or
3010 32 bit version of an eight bit register, we will just use the
3011 low portion, and that's OK too. */
3012 if (i.types[op] & Reg8)
3013 continue;
3014
3015 /* movzx and movsx should not generate this warning. */
3016 if (intel_syntax
3017 && (i.tm.base_opcode == 0xfb7
3018 || i.tm.base_opcode == 0xfb6
3019 || i.tm.base_opcode == 0x63
3020 || i.tm.base_opcode == 0xfbe
3021 || i.tm.base_opcode == 0xfbf))
3022 continue;
3023
65ec77d2 3024 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3025 {
3026 /* Prohibit these changes in the 64bit mode, since the
3027 lowering is more complicated. */
3028 if (flag_code == CODE_64BIT
3029 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3030 {
2ca3ace5
L		 3031 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3032 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3033 i.suffix);
3034 return 0;
3035 }
3036#if REGISTER_WARNINGS
3037 if (!quiet_warnings
3038 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3039 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3040 (i.op[op].regs + (i.types[op] & Reg16
3041 ? REGNAM_AL - REGNAM_AX
3042 : REGNAM_AL - REGNAM_EAX))->reg_name,
3043 i.op[op].regs->reg_name,
3044 i.suffix);
3045#endif
3046 continue;
3047 }
3048 /* Any other register is bad. */
3049 if (i.types[op] & (Reg | RegMMX | RegXMM
3050 | SReg2 | SReg3
3051 | Control | Debug | Test
3052 | FloatReg | FloatAcc))
3053 {
3054 as_bad (_("`%%%s' not allowed with `%s%c'"),
3055 i.op[op].regs->reg_name,
3056 i.tm.name,
3057 i.suffix);
3058 return 0;
3059 }
3060 }
3061 return 1;
3062}
3063
3064static int
e3bb37b5 3065check_long_reg (void)
29b0f896
AM		 3066{
3067 int op;
3068
3069 for (op = i.operands; --op >= 0;)
3070 /* Reject eight bit registers, except where the template requires
3071 them. (eg. movzb) */
3072 if ((i.types[op] & Reg8) != 0
3073 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3074 {
3075 as_bad (_("`%%%s' not allowed with `%s%c'"),
3076 i.op[op].regs->reg_name,
3077 i.tm.name,
3078 i.suffix);
3079 return 0;
3080 }
3081 /* Warn if the e prefix on a general reg is missing. */
3082 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3083 && (i.types[op] & Reg16) != 0
3084 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3085 {
3086 /* Prohibit these changes in the 64bit mode, since the
3087 lowering is more complicated. */
3088 if (flag_code == CODE_64BIT)
252b5132 3089 {
2ca3ace5
L		 3090 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3091 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3092 i.suffix);
3093 return 0;
252b5132 3094 }
29b0f896
AM		 3095#if REGISTER_WARNINGS
3096 else
3097 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3098 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3099 i.op[op].regs->reg_name,
3100 i.suffix);
3101#endif
252b5132 3102 }
29b0f896
AM		 3103 /* Warn if the r prefix on a general reg is missing. */
3104 else if ((i.types[op] & Reg64) != 0
3105 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 3106 {
2ca3ace5
L		 3107 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3108 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3109 i.suffix);
3110 return 0;
3111 }
3112 return 1;
3113}
252b5132 3114
29b0f896 3115static int
e3bb37b5 3116check_qword_reg (void)
29b0f896
AM		 3117{
3118 int op;
252b5132 3119
29b0f896
AM		 3120 for (op = i.operands; --op >= 0; )
3121 /* Reject eight bit registers, except where the template requires
3122 them. (eg. movzb) */
3123 if ((i.types[op] & Reg8) != 0
3124 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3125 {
3126 as_bad (_("`%%%s' not allowed with `%s%c'"),
3127 i.op[op].regs->reg_name,
3128 i.tm.name,
3129 i.suffix);
3130 return 0;
3131 }
3132 /* Warn if the e prefix on a general reg is missing. */
3133 else if (((i.types[op] & Reg16) != 0
3134 || (i.types[op] & Reg32) != 0)
3135 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3136 {
3137 /* Prohibit these changes in the 64bit mode, since the
3138 lowering is more complicated. */
2ca3ace5
L		 3139 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3140 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3141 i.suffix);
3142 return 0;
252b5132 3143 }
29b0f896
AM		 3144 return 1;
3145}
252b5132 3146
29b0f896 3147static int
e3bb37b5 3148check_word_reg (void)
29b0f896
AM		 3149{
3150 int op;
3151 for (op = i.operands; --op >= 0;)
3152 /* Reject eight bit registers, except where the template requires
3153 them. (eg. movzb) */
3154 if ((i.types[op] & Reg8) != 0
3155 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3156 {
3157 as_bad (_("`%%%s' not allowed with `%s%c'"),
3158 i.op[op].regs->reg_name,
3159 i.tm.name,
3160 i.suffix);
3161 return 0;
3162 }
3163 /* Warn if the e prefix on a general reg is present. */
3164 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3165 && (i.types[op] & Reg32) != 0
3166 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 3167 {
29b0f896
AM		 3168 /* Prohibit these changes in the 64bit mode, since the
3169 lowering is more complicated. */
3170 if (flag_code == CODE_64BIT)
252b5132 3171 {
2ca3ace5
L		 3172 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3173 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3174 i.suffix);
3175 return 0;
252b5132 3176 }
29b0f896
AM		 3177 else
3178#if REGISTER_WARNINGS
3179 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3180 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3181 i.op[op].regs->reg_name,
3182 i.suffix);
3183#endif
3184 }
3185 return 1;
3186}
252b5132 3187
29b0f896 3188static int
e3bb37b5 3189finalize_imm (void)
29b0f896
AM		 3190{
3191 unsigned int overlap0, overlap1, overlap2;
3192
3193 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 3194 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 3195 && overlap0 != Imm8 && overlap0 != Imm8S
3196 && overlap0 != Imm16 && overlap0 != Imm32S
3197 && overlap0 != Imm32 && overlap0 != Imm64)
3198 {
3199 if (i.suffix)
3200 {
3201 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3202 ? Imm8 | Imm8S
3203 : (i.suffix == WORD_MNEM_SUFFIX
3204 ? Imm16
3205 : (i.suffix == QWORD_MNEM_SUFFIX
3206 ? Imm64 | Imm32S
3207 : Imm32)));
3208 }
3209 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3210 || overlap0 == (Imm16 | Imm32)
3211 || overlap0 == (Imm16 | Imm32S))
3212 {
3213 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3214 ? Imm16 : Imm32S);
3215 }
3216 if (overlap0 != Imm8 && overlap0 != Imm8S
3217 && overlap0 != Imm16 && overlap0 != Imm32S
3218 && overlap0 != Imm32 && overlap0 != Imm64)
3219 {
4eed87de
AM		 3220 as_bad (_("no instruction mnemonic suffix given; "
3221 "can't determine immediate size"));
29b0f896
AM		 3222 return 0;
3223 }
3224 }
3225 i.types[0] = overlap0;
3226
3227 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 3228 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 3229 && overlap1 != Imm8 && overlap1 != Imm8S
3230 && overlap1 != Imm16 && overlap1 != Imm32S
3231 && overlap1 != Imm32 && overlap1 != Imm64)
3232 {
3233 if (i.suffix)
3234 {
3235 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3236 ? Imm8 | Imm8S
3237 : (i.suffix == WORD_MNEM_SUFFIX
3238 ? Imm16
3239 : (i.suffix == QWORD_MNEM_SUFFIX
3240 ? Imm64 | Imm32S
3241 : Imm32)));
3242 }
3243 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3244 || overlap1 == (Imm16 | Imm32)
3245 || overlap1 == (Imm16 | Imm32S))
3246 {
3247 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3248 ? Imm16 : Imm32S);
3249 }
3250 if (overlap1 != Imm8 && overlap1 != Imm8S
3251 && overlap1 != Imm16 && overlap1 != Imm32S
3252 && overlap1 != Imm32 && overlap1 != Imm64)
3253 {
4eed87de
AM		 3254 as_bad (_("no instruction mnemonic suffix given; "
3255 "can't determine immediate size %x %c"),
3256 overlap1, i.suffix);
29b0f896
AM		 3257 return 0;
3258 }
3259 }
3260 i.types[1] = overlap1;
3261
3262 overlap2 = i.types[2] & i.tm.operand_types[2];
3263 assert ((overlap2 & Imm) == 0);
3264 i.types[2] = overlap2;
3265
3266 return 1;
3267}
3268
3269static int
e3bb37b5 3270process_operands (void)
29b0f896
AM		 3271{
3272 /* Default segment register this instruction will use for memory
3273 accesses. 0 means unknown. This is only for optimizing out
3274 unnecessary segment overrides. */
3275 const seg_entry *default_seg = 0;
3276
3277 /* The imul $imm, %reg instruction is converted into
3278 imul $imm, %reg, %reg, and the clr %reg instruction
3279 is converted into xor %reg, %reg. */
3280 if (i.tm.opcode_modifier & regKludge)
3281 {
42903f7f
L		 3282 if ((i.tm.cpu_flags & CpuSSE4_1))
3283 {
3284 /* The first operand in instruction blendvpd, blendvps and
3285 pblendvb in SSE4.1 is implicit and must be xmm0. */
3286 assert (i.operands == 3
3287 && i.reg_operands >= 2
3288 && i.types[0] == RegXMM);
3289 if (i.op[0].regs->reg_num != 0)
3290 {
3291 if (intel_syntax)
3292 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
3293 i.tm.name, register_prefix);
3294 else
3295 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
3296 i.tm.name, register_prefix);
3297 return 0;
3298 }
3299 i.op[0] = i.op[1];
3300 i.op[1] = i.op[2];
3301 i.types[0] = i.types[1];
3302 i.types[1] = i.types[2];
3303 i.operands--;
3304 i.reg_operands--;
3305
3306 /* We need to adjust fields in i.tm since they are used by
3307 build_modrm_byte. */
3308 i.tm.operand_types [0] = i.tm.operand_types [1];
3309 i.tm.operand_types [1] = i.tm.operand_types [2];
3310 i.tm.operands--;
3311 }
3312 else
3313 {
3314 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3315 /* Pretend we saw the extra register operand. */
3316 assert (i.reg_operands == 1
3317 && i.op[first_reg_op + 1].regs == 0);
3318 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3319 i.types[first_reg_op + 1] = i.types[first_reg_op];
3320 i.operands++;
3321 i.reg_operands++;
3322 }
29b0f896
AM		 3323 }
3324
3325 if (i.tm.opcode_modifier & ShortForm)
3326 {
4eed87de 3327 if (i.types[0] & (SReg2 | SReg3))
29b0f896 3328 {
4eed87de
AM		 3329 if (i.tm.base_opcode == POP_SEG_SHORT
3330 && i.op[0].regs->reg_num == 1)
29b0f896 3331 {
4eed87de
AM		 3332 as_bad (_("you can't `pop %%cs'"));
3333 return 0;
29b0f896 3334 }
4eed87de
AM		 3335 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3336 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 3337 i.rex |= REX_B;
4eed87de
AM		 3338 }
3339 else
3340 {
3341 /* The register or float register operand is in operand 0 or 1. */
3342 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3343 /* Register goes in low 3 bits of opcode. */
3344 i.tm.base_opcode |= i.op[op].regs->reg_num;
3345 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 3346 i.rex |= REX_B;
4eed87de 3347 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
29b0f896 3348 {
4eed87de
AM		 3349 /* Warn about some common errors, but press on regardless.
3350 The first case can be generated by gcc (<= 2.8.1). */
3351 if (i.operands == 2)
3352 {
3353 /* Reversed arguments on faddp, fsubp, etc. */
3354 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
3355 i.op[1].regs->reg_name,
3356 i.op[0].regs->reg_name);
3357 }
3358 else
3359 {
3360 /* Extraneous `l' suffix on fp insn. */
3361 as_warn (_("translating to `%s %%%s'"), i.tm.name,
3362 i.op[0].regs->reg_name);
3363 }
29b0f896
AM		 3364 }
3365 }
3366 }
3367 else if (i.tm.opcode_modifier & Modrm)
3368 {
3369 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 3370 must be put into the modrm byte). Now, we make the modrm and
3371 index base bytes based on all the info we've collected. */
29b0f896
AM		 3372
3373 default_seg = build_modrm_byte ();
3374 }
8a2ed489 3375 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 3376 {
3377 default_seg = &ds;
3378 }
3379 else if ((i.tm.opcode_modifier & IsString) != 0)
3380 {
3381 /* For the string instructions that allow a segment override
3382 on one of their operands, the default segment is ds. */
3383 default_seg = &ds;
3384 }
3385
30123838
JB		 3386 if ((i.tm.base_opcode == 0x8d /* lea */
3387 || (i.tm.cpu_flags & CpuSVME))
3388 && i.seg[0] && !quiet_warnings)
3389 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 3390
3391 /* If a segment was explicitly specified, and the specified segment
3392 is not the default, use an opcode prefix to select it. If we
3393 never figured out what the default segment is, then default_seg
3394 will be zero at this point, and the specified segment prefix will
3395 always be used. */
29b0f896
AM		 3396 if ((i.seg[0]) && (i.seg[0] != default_seg))
3397 {
3398 if (!add_prefix (i.seg[0]->seg_prefix))
3399 return 0;
3400 }
3401 return 1;
3402}
3403
3404static const seg_entry *
e3bb37b5 3405build_modrm_byte (void)
29b0f896
AM		 3406{
3407 const seg_entry *default_seg = 0;
3408
3409 /* i.reg_operands MUST be the number of real register operands;
3410 implicit registers do not count. */
3411 if (i.reg_operands == 2)
3412 {
3413 unsigned int source, dest;
cab737b9
L		 3414
3415 switch (i.operands)
3416 {
3417 case 2:
3418 source = 0;
3419 break;
3420 case 3:
c81128dc
L		 3421 /* When there are 3 operands, one of them may be immediate,
3422 which may be the first or the last operand. Otherwise,
3423 the first operand must be shift count register (cl). */
3424 assert (i.imm_operands == 1
3425 || (i.imm_operands == 0
3426 && (i.types[0] & ShiftCount)));
3427 source = (i.types[0] & (Imm | ShiftCount)) ? 1 : 0;
cab737b9
L		 3428 break;
3429 case 4:
3430 /* When there are 4 operands, the first two must be immediate
3431 operands. The source operand will be the 3rd one. */
3432 assert (i.imm_operands == 2
3433 && (i.types[0] & Imm)
3434 && (i.types[1] & Imm));
3435 source = 2;
3436 break;
3437 default:
3438 abort ();
3439 }
3440
29b0f896
AM		 3441 dest = source + 1;
3442
3443 i.rm.mode = 3;
3444 /* One of the register operands will be encoded in the i.tm.reg
3445 field, the other in the combined i.tm.mode and i.tm.regmem
3446 fields. If no form of this instruction supports a memory
3447 destination operand, then we assume the source operand may
3448 sometimes be a memory operand and so we need to store the
3449 destination in the i.rm.reg field. */
e72cf3ec 3450 if ((i.tm.operand_types[dest] & (AnyMem | RegMem)) == 0)
29b0f896
AM		 3451 {
3452 i.rm.reg = i.op[dest].regs->reg_num;
3453 i.rm.regmem = i.op[source].regs->reg_num;
3454 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 3455 i.rex |= REX_R;
29b0f896 3456 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 3457 i.rex |= REX_B;
29b0f896
AM		 3458 }
3459 else
3460 {
3461 i.rm.reg = i.op[source].regs->reg_num;
3462 i.rm.regmem = i.op[dest].regs->reg_num;
3463 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 3464 i.rex |= REX_B;
29b0f896 3465 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 3466 i.rex |= REX_R;
29b0f896 3467 }
161a04f6 3468 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5
JB		 3469 {
3470 if (!((i.types[0] | i.types[1]) & Control))
3471 abort ();
161a04f6 3472 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 3473 add_prefix (LOCK_PREFIX_OPCODE);
3474 }
29b0f896
AM		 3475 }
3476 else
3477 { /* If it's not 2 reg operands... */
3478 if (i.mem_operands)
3479 {
3480 unsigned int fake_zero_displacement = 0;
99018f42 3481 unsigned int op;
4eed87de 3482
99018f42
L		 3483 for (op = 0; op < i.operands; op++)
3484 if ((i.types[op] & AnyMem))
3485 break;
3486 assert (op < i.operands);
29b0f896
AM		 3487
3488 default_seg = &ds;
3489
3490 if (i.base_reg == 0)
3491 {
3492 i.rm.mode = 0;
3493 if (!i.disp_operands)
3494 fake_zero_displacement = 1;
3495 if (i.index_reg == 0)
3496 {
3497 /* Operand is just <disp> */
20f0a1fc 3498 if (flag_code == CODE_64BIT)
29b0f896
AM		 3499 {
3500 /* 64bit mode overwrites the 32bit absolute
3501 addressing by RIP relative addressing and
3502 absolute addressing is encoded by one of the
3503 redundant SIB forms. */
3504 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3505 i.sib.base = NO_BASE_REGISTER;
3506 i.sib.index = NO_INDEX_REGISTER;
fc225355
L		 3507 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
3508 ? Disp32S : Disp32);
20f0a1fc 3509 }
fc225355
L		 3510 else if ((flag_code == CODE_16BIT)
3511 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 3512 {
3513 i.rm.regmem = NO_BASE_REGISTER_16;
3514 i.types[op] = Disp16;
3515 }
3516 else
3517 {
3518 i.rm.regmem = NO_BASE_REGISTER;
3519 i.types[op] = Disp32;
29b0f896
AM		 3520 }
3521 }
3522 else /* !i.base_reg && i.index_reg */
3523 {
3524 i.sib.index = i.index_reg->reg_num;
3525 i.sib.base = NO_BASE_REGISTER;
3526 i.sib.scale = i.log2_scale_factor;
3527 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3528 i.types[op] &= ~Disp;
3529 if (flag_code != CODE_64BIT)
3530 i.types[op] |= Disp32; /* Must be 32 bit */
3531 else
3532 i.types[op] |= Disp32S;
3533 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 3534 i.rex |= REX_X;
29b0f896
AM		 3535 }
3536 }
3537 /* RIP addressing for 64bit mode. */
3538 else if (i.base_reg->reg_type == BaseIndex)
3539 {
3540 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3541 i.types[op] &= ~ Disp;
29b0f896 3542 i.types[op] |= Disp32S;
71903a11 3543 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 3544 if (! i.disp_operands)
3545 fake_zero_displacement = 1;
29b0f896
AM		 3546 }
3547 else if (i.base_reg->reg_type & Reg16)
3548 {
3549 switch (i.base_reg->reg_num)
3550 {
3551 case 3: /* (%bx) */
3552 if (i.index_reg == 0)
3553 i.rm.regmem = 7;
3554 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3555 i.rm.regmem = i.index_reg->reg_num - 6;
3556 break;
3557 case 5: /* (%bp) */
3558 default_seg = &ss;
3559 if (i.index_reg == 0)
3560 {
3561 i.rm.regmem = 6;
3562 if ((i.types[op] & Disp) == 0)
3563 {
3564 /* fake (%bp) into 0(%bp) */
3565 i.types[op] |= Disp8;
252b5132 3566 fake_zero_displacement = 1;
29b0f896
AM		 3567 }
3568 }
3569 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3570 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3571 break;
3572 default: /* (%si) -> 4 or (%di) -> 5 */
3573 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3574 }
3575 i.rm.mode = mode_from_disp_size (i.types[op]);
3576 }
3577 else /* i.base_reg and 32/64 bit mode */
3578 {
3579 if (flag_code == CODE_64BIT
3580 && (i.types[op] & Disp))
fc225355
L		 3581 i.types[op] = ((i.types[op] & Disp8)
3582 | (i.prefix[ADDR_PREFIX] == 0
3583 ? Disp32S : Disp32));
20f0a1fc 3584
29b0f896
AM		 3585 i.rm.regmem = i.base_reg->reg_num;
3586 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 3587 i.rex |= REX_B;
29b0f896
AM		 3588 i.sib.base = i.base_reg->reg_num;
3589 /* x86-64 ignores REX prefix bit here to avoid decoder
3590 complications. */
3591 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3592 {
3593 default_seg = &ss;
3594 if (i.disp_operands == 0)
3595 {
3596 fake_zero_displacement = 1;
3597 i.types[op] |= Disp8;
3598 }
3599 }
3600 else if (i.base_reg->reg_num == ESP_REG_NUM)
3601 {
3602 default_seg = &ss;
3603 }
3604 i.sib.scale = i.log2_scale_factor;
3605 if (i.index_reg == 0)
3606 {
3607 /* <disp>(%esp) becomes two byte modrm with no index
3608 register. We've already stored the code for esp
3609 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3610 Any base register besides %esp will not use the
3611 extra modrm byte. */
3612 i.sib.index = NO_INDEX_REGISTER;
3613#if !SCALE1_WHEN_NO_INDEX
3614 /* Another case where we force the second modrm byte. */
3615 if (i.log2_scale_factor)
3616 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3617#endif
29b0f896
AM		 3618 }
3619 else
3620 {
3621 i.sib.index = i.index_reg->reg_num;
3622 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3623 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 3624 i.rex |= REX_X;
29b0f896 3625 }
67a4f2b7
AO		 3626
3627 if (i.disp_operands
3628 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3629 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3630 i.rm.mode = 0;
3631 else
3632 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 3633 }
252b5132 3634
29b0f896
AM		 3635 if (fake_zero_displacement)
3636 {
3637 /* Fakes a zero displacement assuming that i.types[op]
3638 holds the correct displacement size. */
3639 expressionS *exp;
3640
3641 assert (i.op[op].disps == 0);
3642 exp = &disp_expressions[i.disp_operands++];
3643 i.op[op].disps = exp;
3644 exp->X_op = O_constant;
3645 exp->X_add_number = 0;
3646 exp->X_add_symbol = (symbolS *) 0;
3647 exp->X_op_symbol = (symbolS *) 0;
3648 }
3649 }
252b5132 3650
29b0f896
AM		 3651 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3652 (if any) based on i.tm.extension_opcode. Again, we must be
3653 careful to make sure that segment/control/debug/test/MMX
3654 registers are coded into the i.rm.reg field. */
3655 if (i.reg_operands)
3656 {
99018f42
L		 3657 unsigned int op;
3658
3659 for (op = 0; op < i.operands; op++)
3660 if ((i.types[op] & (Reg | RegMMX | RegXMM
3661 | SReg2 | SReg3
3662 | Control | Debug | Test)))
3663 break;
3664 assert (op < i.operands);
3665
29b0f896
AM		 3666 /* If there is an extension opcode to put here, the register
3667 number must be put into the regmem field. */
3668 if (i.tm.extension_opcode != None)
3669 {
3670 i.rm.regmem = i.op[op].regs->reg_num;
3671 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 3672 i.rex |= REX_B;
29b0f896
AM		 3673 }
3674 else
3675 {
3676 i.rm.reg = i.op[op].regs->reg_num;
3677 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 3678 i.rex |= REX_R;
29b0f896 3679 }
252b5132 3680
29b0f896
AM		 3681 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3682 must set it to 3 to indicate this is a register operand
3683 in the regmem field. */
3684 if (!i.mem_operands)
3685 i.rm.mode = 3;
3686 }
252b5132 3687
29b0f896
AM		 3688 /* Fill in i.rm.reg field with extension opcode (if any). */
3689 if (i.tm.extension_opcode != None)
3690 i.rm.reg = i.tm.extension_opcode;
3691 }
3692 return default_seg;
3693}
252b5132 3694
29b0f896 3695static void
e3bb37b5 3696output_branch (void)
29b0f896
AM		 3697{
3698 char *p;
3699 int code16;
3700 int prefix;
3701 relax_substateT subtype;
3702 symbolS *sym;
3703 offsetT off;
3704
3705 code16 = 0;
3706 if (flag_code == CODE_16BIT)
3707 code16 = CODE16;
3708
3709 prefix = 0;
3710 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3711 {
29b0f896
AM		 3712 prefix = 1;
3713 i.prefixes -= 1;
3714 code16 ^= CODE16;
252b5132 3715 }
29b0f896
AM		 3716 /* Pentium4 branch hints. */
3717 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3718 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3719 {
29b0f896
AM		 3720 prefix++;
3721 i.prefixes--;
3722 }
3723 if (i.prefix[REX_PREFIX] != 0)
3724 {
3725 prefix++;
3726 i.prefixes--;
2f66722d
AM		 3727 }
3728
29b0f896
AM		 3729 if (i.prefixes != 0 && !intel_syntax)
3730 as_warn (_("skipping prefixes on this instruction"));
3731
3732 /* It's always a symbol; End frag & setup for relax.
3733 Make sure there is enough room in this frag for the largest
3734 instruction we may generate in md_convert_frag. This is 2
3735 bytes for the opcode and room for the prefix and largest
3736 displacement. */
3737 frag_grow (prefix + 2 + 4);
3738 /* Prefix and 1 opcode byte go in fr_fix. */
3739 p = frag_more (prefix + 1);
3740 if (i.prefix[DATA_PREFIX] != 0)
3741 *p++ = DATA_PREFIX_OPCODE;
3742 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3743 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3744 *p++ = i.prefix[SEG_PREFIX];
3745 if (i.prefix[REX_PREFIX] != 0)
3746 *p++ = i.prefix[REX_PREFIX];
3747 *p = i.tm.base_opcode;
3748
3749 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3750 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3751 else if ((cpu_arch_flags & Cpu386) != 0)
3752 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3753 else
3754 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3755 subtype |= code16;
3e73aa7c 3756
29b0f896
AM		 3757 sym = i.op[0].disps->X_add_symbol;
3758 off = i.op[0].disps->X_add_number;
3e73aa7c 3759
29b0f896
AM		 3760 if (i.op[0].disps->X_op != O_constant
3761 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3762 {
29b0f896
AM		 3763 /* Handle complex expressions. */
3764 sym = make_expr_symbol (i.op[0].disps);
3765 off = 0;
3766 }
3e73aa7c 3767
29b0f896
AM		 3768 /* 1 possible extra opcode + 4 byte displacement go in var part.
3769 Pass reloc in fr_var. */
3770 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3771}
3e73aa7c 3772
29b0f896 3773static void
e3bb37b5 3774output_jump (void)
29b0f896
AM		 3775{
3776 char *p;
3777 int size;
3e02c1cc 3778 fixS *fixP;
29b0f896
AM		 3779
3780 if (i.tm.opcode_modifier & JumpByte)
3781 {
3782 /* This is a loop or jecxz type instruction. */
3783 size = 1;
3784 if (i.prefix[ADDR_PREFIX] != 0)
3785 {
3786 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3787 i.prefixes -= 1;
3788 }
3789 /* Pentium4 branch hints. */
3790 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3791 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3792 {
3793 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3794 i.prefixes--;
3e73aa7c
JH		 3795 }
3796 }
29b0f896
AM		 3797 else
3798 {
3799 int code16;
3e73aa7c 3800
29b0f896
AM		 3801 code16 = 0;
3802 if (flag_code == CODE_16BIT)
3803 code16 = CODE16;
3e73aa7c 3804
29b0f896
AM		 3805 if (i.prefix[DATA_PREFIX] != 0)
3806 {
3807 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3808 i.prefixes -= 1;
3809 code16 ^= CODE16;
3810 }
252b5132 3811
29b0f896
AM		 3812 size = 4;
3813 if (code16)
3814 size = 2;
3815 }
9fcc94b6 3816
29b0f896
AM		 3817 if (i.prefix[REX_PREFIX] != 0)
3818 {
3819 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3820 i.prefixes -= 1;
3821 }
252b5132 3822
29b0f896
AM		 3823 if (i.prefixes != 0 && !intel_syntax)
3824 as_warn (_("skipping prefixes on this instruction"));
e0890092 3825
29b0f896
AM		 3826 p = frag_more (1 + size);
3827 *p++ = i.tm.base_opcode;
e0890092 3828
3e02c1cc
AM		 3829 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3830 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3831
3832 /* All jumps handled here are signed, but don't use a signed limit
3833 check for 32 and 16 bit jumps as we want to allow wrap around at
3834 4G and 64k respectively. */
3835 if (size == 1)
3836 fixP->fx_signed = 1;
29b0f896 3837}
e0890092 3838
29b0f896 3839static void
e3bb37b5 3840output_interseg_jump (void)
29b0f896
AM		 3841{
3842 char *p;
3843 int size;
3844 int prefix;
3845 int code16;
252b5132 3846
29b0f896
AM		 3847 code16 = 0;
3848 if (flag_code == CODE_16BIT)
3849 code16 = CODE16;
a217f122 3850
29b0f896
AM		 3851 prefix = 0;
3852 if (i.prefix[DATA_PREFIX] != 0)
3853 {
3854 prefix = 1;
3855 i.prefixes -= 1;
3856 code16 ^= CODE16;
3857 }
3858 if (i.prefix[REX_PREFIX] != 0)
3859 {
3860 prefix++;
3861 i.prefixes -= 1;
3862 }
252b5132 3863
29b0f896
AM		 3864 size = 4;
3865 if (code16)
3866 size = 2;
252b5132 3867
29b0f896
AM		 3868 if (i.prefixes != 0 && !intel_syntax)
3869 as_warn (_("skipping prefixes on this instruction"));
252b5132 3870
29b0f896
AM		 3871 /* 1 opcode; 2 segment; offset */
3872 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3873
29b0f896
AM		 3874 if (i.prefix[DATA_PREFIX] != 0)
3875 *p++ = DATA_PREFIX_OPCODE;
252b5132 3876
29b0f896
AM		 3877 if (i.prefix[REX_PREFIX] != 0)
3878 *p++ = i.prefix[REX_PREFIX];
252b5132 3879
29b0f896
AM		 3880 *p++ = i.tm.base_opcode;
3881 if (i.op[1].imms->X_op == O_constant)
3882 {
3883 offsetT n = i.op[1].imms->X_add_number;
252b5132 3884
29b0f896
AM		 3885 if (size == 2
3886 && !fits_in_unsigned_word (n)
3887 && !fits_in_signed_word (n))
3888 {
3889 as_bad (_("16-bit jump out of range"));
3890 return;
3891 }
3892 md_number_to_chars (p, n, size);
3893 }
3894 else
3895 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3896 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3897 if (i.op[0].imms->X_op != O_constant)
3898 as_bad (_("can't handle non absolute segment in `%s'"),
3899 i.tm.name);
3900 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3901}
a217f122 3902
29b0f896 3903static void
e3bb37b5 3904output_insn (void)
29b0f896 3905{
2bbd9c25
JJ		 3906 fragS *insn_start_frag;
3907 offsetT insn_start_off;
3908
29b0f896
AM		 3909 /* Tie dwarf2 debug info to the address at the start of the insn.
3910 We can't do this after the insn has been output as the current
3911 frag may have been closed off. eg. by frag_var. */
3912 dwarf2_emit_insn (0);
3913
2bbd9c25
JJ		 3914 insn_start_frag = frag_now;
3915 insn_start_off = frag_now_fix ();
3916
29b0f896
AM		 3917 /* Output jumps. */
3918 if (i.tm.opcode_modifier & Jump)
3919 output_branch ();
3920 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3921 output_jump ();
3922 else if (i.tm.opcode_modifier & JumpInterSegment)
3923 output_interseg_jump ();
3924 else
3925 {
3926 /* Output normal instructions here. */
3927 char *p;
3928 unsigned char *q;
331d2d0d 3929 unsigned int prefix;
252b5132 3930
42903f7f
L		 3931 /* All opcodes on i386 have either 1 or 2 bytes. SSSE3 and
3932 SSE4.1 instructions have 3 bytes. We may use one more higher
3933 byte to specify a prefix the instruction requires. */
3934 if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4_1)) != 0)
bc4bd9ab 3935 {
331d2d0d
L		 3936 if (i.tm.base_opcode & 0xff000000)
3937 {
3938 prefix = (i.tm.base_opcode >> 24) & 0xff;
3939 goto check_prefix;
3940 }
3941 }
3942 else if ((i.tm.base_opcode & 0xff0000) != 0)
3943 {
3944 prefix = (i.tm.base_opcode >> 16) & 0xff;
bc4bd9ab
MK		 3945 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3946 {
64e74474 3947 check_prefix:
bc4bd9ab
MK		 3948 if (prefix != REPE_PREFIX_OPCODE
3949 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3950 add_prefix (prefix);
3951 }
3952 else
331d2d0d 3953 add_prefix (prefix);
0f10071e 3954 }
252b5132 3955
29b0f896
AM		 3956 /* The prefix bytes. */
3957 for (q = i.prefix;
3958 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3959 q++)
3960 {
3961 if (*q)
3962 {
3963 p = frag_more (1);
3964 md_number_to_chars (p, (valueT) *q, 1);
3965 }
3966 }
252b5132 3967
29b0f896
AM		 3968 /* Now the opcode; be careful about word order here! */
3969 if (fits_in_unsigned_byte (i.tm.base_opcode))
3970 {
3971 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3972 }
3973 else
3974 {
42903f7f 3975 if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4_1)) != 0)
331d2d0d
L		 3976 {
3977 p = frag_more (3);
3978 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3979 }
3980 else
3981 p = frag_more (2);
0f10071e 3982
29b0f896
AM		 3983 /* Put out high byte first: can't use md_number_to_chars! */
3984 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3985 *p = i.tm.base_opcode & 0xff;
3986 }
3e73aa7c 3987
29b0f896
AM		 3988 /* Now the modrm byte and sib byte (if present). */
3989 if (i.tm.opcode_modifier & Modrm)
3990 {
3991 p = frag_more (1);
3992 md_number_to_chars (p,
3993 (valueT) (i.rm.regmem << 0
3994 | i.rm.reg << 3
3995 | i.rm.mode << 6),
3996 1);
3997 /* If i.rm.regmem == ESP (4)
3998 && i.rm.mode != (Register mode)
3999 && not 16 bit
4000 ==> need second modrm byte. */
4001 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
4002 && i.rm.mode != 3
4003 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
4004 {
4005 p = frag_more (1);
4006 md_number_to_chars (p,
4007 (valueT) (i.sib.base << 0
4008 | i.sib.index << 3
4009 | i.sib.scale << 6),
4010 1);
4011 }
4012 }
3e73aa7c 4013
29b0f896 4014 if (i.disp_operands)
2bbd9c25 4015 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 4016
29b0f896 4017 if (i.imm_operands)
2bbd9c25 4018 output_imm (insn_start_frag, insn_start_off);
29b0f896 4019 }
252b5132 4020
29b0f896
AM		 4021#ifdef DEBUG386
4022 if (flag_debug)
4023 {
7b81dfbb 4024 pi ("" /*line*/, &i);
29b0f896
AM		 4025 }
4026#endif /* DEBUG386 */
4027}
252b5132 4028
29b0f896 4029static void
64e74474 4030output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4031{
4032 char *p;
4033 unsigned int n;
252b5132 4034
29b0f896
AM		 4035 for (n = 0; n < i.operands; n++)
4036 {
4037 if (i.types[n] & Disp)
4038 {
4039 if (i.op[n].disps->X_op == O_constant)
4040 {
4041 int size;
4042 offsetT val;
252b5132 4043
29b0f896
AM		 4044 size = 4;
4045 if (i.types[n] & (Disp8 | Disp16 | Disp64))
4046 {
4047 size = 2;
4048 if (i.types[n] & Disp8)
4049 size = 1;
4050 if (i.types[n] & Disp64)
4051 size = 8;
4052 }
4053 val = offset_in_range (i.op[n].disps->X_add_number,
4054 size);
4055 p = frag_more (size);
4056 md_number_to_chars (p, val, size);
4057 }
4058 else
4059 {
f86103b7 4060 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4061 int size = 4;
4062 int sign = 0;
4063 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
4064
4065 /* The PC relative address is computed relative
4066 to the instruction boundary, so in case immediate
4067 fields follows, we need to adjust the value. */
4068 if (pcrel && i.imm_operands)
4069 {
4070 int imm_size = 4;
4071 unsigned int n1;
252b5132 4072
29b0f896
AM		 4073 for (n1 = 0; n1 < i.operands; n1++)
4074 if (i.types[n1] & Imm)
252b5132 4075 {
29b0f896 4076 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 4077 {
29b0f896
AM		 4078 imm_size = 2;
4079 if (i.types[n1] & (Imm8 | Imm8S))
4080 imm_size = 1;
4081 if (i.types[n1] & Imm64)
4082 imm_size = 8;
252b5132 4083 }
29b0f896 4084 break;
252b5132 4085 }
29b0f896
AM		 4086 /* We should find the immediate. */
4087 if (n1 == i.operands)
4088 abort ();
4089 i.op[n].disps->X_add_number -= imm_size;
4090 }
520dc8e8 4091
29b0f896
AM		 4092 if (i.types[n] & Disp32S)
4093 sign = 1;
3e73aa7c 4094
29b0f896
AM		 4095 if (i.types[n] & (Disp16 | Disp64))
4096 {
4097 size = 2;
4098 if (i.types[n] & Disp64)
4099 size = 8;
4100 }
520dc8e8 4101
29b0f896 4102 p = frag_more (size);
2bbd9c25 4103 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 4104 if (GOT_symbol
2bbd9c25 4105 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 4106 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4107 || reloc_type == BFD_RELOC_X86_64_32S
4108 || (reloc_type == BFD_RELOC_64
4109 && object_64bit))
d6ab8113
JB		 4110 && (i.op[n].disps->X_op == O_symbol
4111 || (i.op[n].disps->X_op == O_add
4112 && ((symbol_get_value_expression
4113 (i.op[n].disps->X_op_symbol)->X_op)
4114 == O_subtract))))
4115 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 4116 {
4117 offsetT add;
4118
4119 if (insn_start_frag == frag_now)
4120 add = (p - frag_now->fr_literal) - insn_start_off;
4121 else
4122 {
4123 fragS *fr;
4124
4125 add = insn_start_frag->fr_fix - insn_start_off;
4126 for (fr = insn_start_frag->fr_next;
4127 fr && fr != frag_now; fr = fr->fr_next)
4128 add += fr->fr_fix;
4129 add += p - frag_now->fr_literal;
4130 }
4131
4fa24527 4132 if (!object_64bit)
7b81dfbb
AJ		 4133 {
4134 reloc_type = BFD_RELOC_386_GOTPC;
4135 i.op[n].imms->X_add_number += add;
4136 }
4137 else if (reloc_type == BFD_RELOC_64)
4138 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 4139 else
7b81dfbb
AJ		 4140 /* Don't do the adjustment for x86-64, as there
4141 the pcrel addressing is relative to the _next_
4142 insn, and that is taken care of in other code. */
d6ab8113 4143 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 4144 }
062cd5e7 4145 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 4146 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 4147 }
4148 }
4149 }
4150}
252b5132 4151
29b0f896 4152static void
64e74474 4153output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4154{
4155 char *p;
4156 unsigned int n;
252b5132 4157
29b0f896
AM		 4158 for (n = 0; n < i.operands; n++)
4159 {
4160 if (i.types[n] & Imm)
4161 {
4162 if (i.op[n].imms->X_op == O_constant)
4163 {
4164 int size;
4165 offsetT val;
b4cac588 4166
29b0f896
AM		 4167 size = 4;
4168 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4169 {
4170 size = 2;
4171 if (i.types[n] & (Imm8 | Imm8S))
4172 size = 1;
4173 else if (i.types[n] & Imm64)
4174 size = 8;
4175 }
4176 val = offset_in_range (i.op[n].imms->X_add_number,
4177 size);
4178 p = frag_more (size);
4179 md_number_to_chars (p, val, size);
4180 }
4181 else
4182 {
4183 /* Not absolute_section.
4184 Need a 32-bit fixup (don't support 8bit
4185 non-absolute imms). Try to support other
4186 sizes ... */
f86103b7 4187 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4188 int size = 4;
4189 int sign = 0;
4190
4191 if ((i.types[n] & (Imm32S))
a7d61044
JB		 4192 && (i.suffix == QWORD_MNEM_SUFFIX
4193 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 4194 sign = 1;
4195 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4196 {
4197 size = 2;
4198 if (i.types[n] & (Imm8 | Imm8S))
4199 size = 1;
4200 if (i.types[n] & Imm64)
4201 size = 8;
4202 }
520dc8e8 4203
29b0f896
AM		 4204 p = frag_more (size);
4205 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 4206
2bbd9c25
JJ		 4207 /* This is tough to explain. We end up with this one if we
4208 * have operands that look like
4209 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4210 * obtain the absolute address of the GOT, and it is strongly
4211 * preferable from a performance point of view to avoid using
4212 * a runtime relocation for this. The actual sequence of
4213 * instructions often look something like:
4214 *
4215 * call .L66
4216 * .L66:
4217 * popl %ebx
4218 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4219 *
4220 * The call and pop essentially return the absolute address
4221 * of the label .L66 and store it in %ebx. The linker itself
4222 * will ultimately change the first operand of the addl so
4223 * that %ebx points to the GOT, but to keep things simple, the
4224 * .o file must have this operand set so that it generates not
4225 * the absolute address of .L66, but the absolute address of
4226 * itself. This allows the linker itself simply treat a GOTPC
4227 * relocation as asking for a pcrel offset to the GOT to be
4228 * added in, and the addend of the relocation is stored in the
4229 * operand field for the instruction itself.
4230 *
4231 * Our job here is to fix the operand so that it would add
4232 * the correct offset so that %ebx would point to itself. The
4233 * thing that is tricky is that .-.L66 will point to the
4234 * beginning of the instruction, so we need to further modify
4235 * the operand so that it will point to itself. There are
4236 * other cases where you have something like:
4237 *
4238 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4239 *
4240 * and here no correction would be required. Internally in
4241 * the assembler we treat operands of this form as not being
4242 * pcrel since the '.' is explicitly mentioned, and I wonder
4243 * whether it would simplify matters to do it this way. Who
4244 * knows. In earlier versions of the PIC patches, the
4245 * pcrel_adjust field was used to store the correction, but
4246 * since the expression is not pcrel, I felt it would be
4247 * confusing to do it this way. */
4248
d6ab8113 4249 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4250 || reloc_type == BFD_RELOC_X86_64_32S
4251 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 4252 && GOT_symbol
4253 && GOT_symbol == i.op[n].imms->X_add_symbol
4254 && (i.op[n].imms->X_op == O_symbol
4255 || (i.op[n].imms->X_op == O_add
4256 && ((symbol_get_value_expression
4257 (i.op[n].imms->X_op_symbol)->X_op)
4258 == O_subtract))))
4259 {
2bbd9c25
JJ		 4260 offsetT add;
4261
4262 if (insn_start_frag == frag_now)
4263 add = (p - frag_now->fr_literal) - insn_start_off;
4264 else
4265 {
4266 fragS *fr;
4267
4268 add = insn_start_frag->fr_fix - insn_start_off;
4269 for (fr = insn_start_frag->fr_next;
4270 fr && fr != frag_now; fr = fr->fr_next)
4271 add += fr->fr_fix;
4272 add += p - frag_now->fr_literal;
4273 }
4274
4fa24527 4275 if (!object_64bit)
d6ab8113 4276 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 4277 else if (size == 4)
d6ab8113 4278 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 4279 else if (size == 8)
4280 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 4281 i.op[n].imms->X_add_number += add;
29b0f896 4282 }
29b0f896
AM		 4283 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4284 i.op[n].imms, 0, reloc_type);
4285 }
4286 }
4287 }
252b5132
RH		 4288}
4289\f
d182319b
JB		 4290/* x86_cons_fix_new is called via the expression parsing code when a
4291 reloc is needed. We use this hook to get the correct .got reloc. */
4292static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4293static int cons_sign = -1;
4294
4295void
e3bb37b5 4296x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 4297 expressionS *exp)
d182319b
JB		 4298{
4299 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4300
4301 got_reloc = NO_RELOC;
4302
4303#ifdef TE_PE
4304 if (exp->X_op == O_secrel)
4305 {
4306 exp->X_op = O_symbol;
4307 r = BFD_RELOC_32_SECREL;
4308 }
4309#endif
4310
4311 fix_new_exp (frag, off, len, exp, 0, r);
4312}
4313
718ddfc0
JB		 4314#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4315# define lex_got(reloc, adjust, types) NULL
4316#else
f3c180ae
AM		 4317/* Parse operands of the form
4318 <symbol>@GOTOFF+<nnn>
4319 and similar .plt or .got references.
4320
4321 If we find one, set up the correct relocation in RELOC and copy the
4322 input string, minus the `@GOTOFF' into a malloc'd buffer for
4323 parsing by the calling routine. Return this buffer, and if ADJUST
4324 is non-null set it to the length of the string we removed from the
4325 input line. Otherwise return NULL. */
4326static char *
3956db08 4327lex_got (enum bfd_reloc_code_real *reloc,
64e74474
AM		 4328 int *adjust,
4329 unsigned int *types)
f3c180ae 4330{
7b81dfbb
AJ		 4331 /* Some of the relocations depend on the size of what field is to
4332 be relocated. But in our callers i386_immediate and i386_displacement
4333 we don't yet know the operand size (this will be set by insn
4334 matching). Hence we record the word32 relocation here,
4335 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 4336 static const struct {
4337 const char *str;
4fa24527 4338 const enum bfd_reloc_code_real rel[2];
3956db08 4339 const unsigned int types64;
f3c180ae 4340 } gotrel[] = {
4eed87de
AM		 4341 { "PLTOFF", { 0,
4342 BFD_RELOC_X86_64_PLTOFF64 },
4343 Imm64 },
4344 { "PLT", { BFD_RELOC_386_PLT32,
4345 BFD_RELOC_X86_64_PLT32 },
4346 Imm32 | Imm32S | Disp32 },
4347 { "GOTPLT", { 0,
4348 BFD_RELOC_X86_64_GOTPLT64 },
4349 Imm64 | Disp64 },
4350 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
4351 BFD_RELOC_X86_64_GOTOFF64 },
4352 Imm64 | Disp64 },
4353 { "GOTPCREL", { 0,
4354 BFD_RELOC_X86_64_GOTPCREL },
4355 Imm32 | Imm32S | Disp32 },
4356 { "TLSGD", { BFD_RELOC_386_TLS_GD,
4357 BFD_RELOC_X86_64_TLSGD },
4358 Imm32 | Imm32S | Disp32 },
4359 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
4360 0 },
4361 0 },
4362 { "TLSLD", { 0,
4363 BFD_RELOC_X86_64_TLSLD },
4364 Imm32 | Imm32S | Disp32 },
4365 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
4366 BFD_RELOC_X86_64_GOTTPOFF },
4367 Imm32 | Imm32S | Disp32 },
4368 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
4369 BFD_RELOC_X86_64_TPOFF32 },
4370 Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
4371 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
4372 0 },
4373 0 },
4374 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
4375 BFD_RELOC_X86_64_DTPOFF32 },
4376 Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
4377 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
4378 0 },
4379 0 },
4380 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
4381 0 },
4382 0 },
4383 { "GOT", { BFD_RELOC_386_GOT32,
4384 BFD_RELOC_X86_64_GOT32 },
4385 Imm32 | Imm32S | Disp32 | Imm64 },
4386 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
4387 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
4388 Imm32 | Imm32S | Disp32 },
4389 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
4390 BFD_RELOC_X86_64_TLSDESC_CALL },
4391 Imm32 | Imm32S | Disp32 }
f3c180ae
AM		 4392 };
4393 char *cp;
4394 unsigned int j;
4395
718ddfc0
JB		 4396 if (!IS_ELF)
4397 return NULL;
4398
f3c180ae
AM		 4399 for (cp = input_line_pointer; *cp != '@'; cp++)
4400 if (is_end_of_line[(unsigned char) *cp])
4401 return NULL;
4402
4403 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4404 {
4405 int len;
4406
4407 len = strlen (gotrel[j].str);
28f81592 4408 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 4409 {
4fa24527 4410 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 4411 {
28f81592
AM		 4412 int first, second;
4413 char *tmpbuf, *past_reloc;
f3c180ae 4414
4fa24527 4415 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 4416 if (adjust)
4417 *adjust = len;
f3c180ae 4418
3956db08
JB		 4419 if (types)
4420 {
4421 if (flag_code != CODE_64BIT)
4eed87de 4422 *types = Imm32 | Disp32;
3956db08
JB		 4423 else
4424 *types = gotrel[j].types64;
4425 }
4426
f3c180ae
AM		 4427 if (GOT_symbol == NULL)
4428 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4429
4430 /* Replace the relocation token with ' ', so that
4431 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 4432
4433 /* The length of the first part of our input line. */
f3c180ae 4434 first = cp - input_line_pointer;
28f81592
AM		 4435
4436 /* The second part goes from after the reloc token until
4437 (and including) an end_of_line char. Don't use strlen
4438 here as the end_of_line char may not be a NUL. */
4439 past_reloc = cp + 1 + len;
4440 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4441 ;
4442 second = cp - past_reloc;
4443
4444 /* Allocate and copy string. The trailing NUL shouldn't
4445 be necessary, but be safe. */
4446 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 4447 memcpy (tmpbuf, input_line_pointer, first);
4448 tmpbuf[first] = ' ';
28f81592
AM		 4449 memcpy (tmpbuf + first + 1, past_reloc, second);
4450 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 4451 return tmpbuf;
4452 }
4453
4fa24527
JB		 4454 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4455 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 4456 return NULL;
4457 }
4458 }
4459
4460 /* Might be a symbol version string. Don't as_bad here. */
4461 return NULL;
4462}
4463
f3c180ae 4464void
e3bb37b5 4465x86_cons (expressionS *exp, int size)
f3c180ae 4466{
4fa24527 4467 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 4468 {
4469 /* Handle @GOTOFF and the like in an expression. */
4470 char *save;
4471 char *gotfree_input_line;
4472 int adjust;
4473
4474 save = input_line_pointer;
3956db08 4475 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 4476 if (gotfree_input_line)
4477 input_line_pointer = gotfree_input_line;
4478
4479 expression (exp);
4480
4481 if (gotfree_input_line)
4482 {
4483 /* expression () has merrily parsed up to the end of line,
4484 or a comma - in the wrong buffer. Transfer how far
4485 input_line_pointer has moved to the right buffer. */
4486 input_line_pointer = (save
4487 + (input_line_pointer - gotfree_input_line)
4488 + adjust);
4489 free (gotfree_input_line);
4490 }
4491 }
4492 else
4493 expression (exp);
4494}
4495#endif
4496
d182319b 4497static void signed_cons (int size)
6482c264 4498{
d182319b
JB		 4499 if (flag_code == CODE_64BIT)
4500 cons_sign = 1;
4501 cons (size);
4502 cons_sign = -1;
6482c264
NC		 4503}
4504
d182319b 4505#ifdef TE_PE
6482c264
NC		 4506static void
4507pe_directive_secrel (dummy)
4508 int dummy ATTRIBUTE_UNUSED;
4509{
4510 expressionS exp;
4511
4512 do
4513 {
4514 expression (&exp);
4515 if (exp.X_op == O_symbol)
4516 exp.X_op = O_secrel;
4517
4518 emit_expr (&exp, 4);
4519 }
4520 while (*input_line_pointer++ == ',');
4521
4522 input_line_pointer--;
4523 demand_empty_rest_of_line ();
4524}
6482c264
NC		 4525#endif
4526
252b5132 4527static int
70e41ade 4528i386_immediate (char *imm_start)
252b5132
RH		 4529{
4530 char *save_input_line_pointer;
f3c180ae 4531 char *gotfree_input_line;
252b5132 4532 segT exp_seg = 0;
47926f60 4533 expressionS *exp;
3956db08 4534 unsigned int types = ~0U;
252b5132
RH		 4535
4536 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4537 {
31b2323c
L		 4538 as_bad (_("at most %d immediate operands are allowed"),
4539 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 4540 return 0;
4541 }
4542
4543 exp = &im_expressions[i.imm_operands++];
520dc8e8 4544 i.op[this_operand].imms = exp;
252b5132
RH		 4545
4546 if (is_space_char (*imm_start))
4547 ++imm_start;
4548
4549 save_input_line_pointer = input_line_pointer;
4550 input_line_pointer = imm_start;
4551
3956db08 4552 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4553 if (gotfree_input_line)
4554 input_line_pointer = gotfree_input_line;
252b5132
RH		 4555
4556 exp_seg = expression (exp);
4557
83183c0c 4558 SKIP_WHITESPACE ();
252b5132 4559 if (*input_line_pointer)
f3c180ae 4560 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 4561
4562 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4563 if (gotfree_input_line)
4564 free (gotfree_input_line);
252b5132 4565
2daf4fd8 4566 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 4567 {
47926f60 4568 /* Missing or bad expr becomes absolute 0. */
d0b47220 4569 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 4570 imm_start);
252b5132
RH		 4571 exp->X_op = O_constant;
4572 exp->X_add_number = 0;
4573 exp->X_add_symbol = (symbolS *) 0;
4574 exp->X_op_symbol = (symbolS *) 0;
252b5132 4575 }
3e73aa7c 4576 else if (exp->X_op == O_constant)
252b5132 4577 {
47926f60 4578 /* Size it properly later. */
3e73aa7c
JH		 4579 i.types[this_operand] |= Imm64;
4580 /* If BFD64, sign extend val. */
4eed87de
AM		 4581 if (!use_rela_relocations
4582 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4583 exp->X_add_number
4584 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4585 }
4c63da97 4586#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4587 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4588 && exp_seg != absolute_section
47926f60 4589 && exp_seg != text_section
24eab124
AM		 4590 && exp_seg != data_section
4591 && exp_seg != bss_section
4592 && exp_seg != undefined_section
f86103b7 4593 && !bfd_is_com_section (exp_seg))
252b5132 4594 {
d0b47220 4595 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4596 return 0;
4597 }
4598#endif
bb8f5920
L		 4599 else if (!intel_syntax && exp->X_op == O_register)
4600 {
4601 as_bad (_("illegal immediate register operand %s"), imm_start);
4602 return 0;
4603 }
252b5132
RH		 4604 else
4605 {
4606 /* This is an address. The size of the address will be
24eab124 4607 determined later, depending on destination register,
3e73aa7c
JH		 4608 suffix, or the default for the section. */
4609 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4610 i.types[this_operand] &= types;
252b5132
RH		 4611 }
4612
4613 return 1;
4614}
4615
551c1ca1 4616static char *
e3bb37b5 4617i386_scale (char *scale)
252b5132 4618{
551c1ca1
AM		 4619 offsetT val;
4620 char *save = input_line_pointer;
252b5132 4621
551c1ca1
AM		 4622 input_line_pointer = scale;
4623 val = get_absolute_expression ();
4624
4625 switch (val)
252b5132 4626 {
551c1ca1 4627 case 1:
252b5132
RH		 4628 i.log2_scale_factor = 0;
4629 break;
551c1ca1 4630 case 2:
252b5132
RH		 4631 i.log2_scale_factor = 1;
4632 break;
551c1ca1 4633 case 4:
252b5132
RH		 4634 i.log2_scale_factor = 2;
4635 break;
551c1ca1 4636 case 8:
252b5132
RH		 4637 i.log2_scale_factor = 3;
4638 break;
4639 default:
a724f0f4
JB		 4640 {
4641 char sep = *input_line_pointer;
4642
4643 *input_line_pointer = '\0';
4644 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4645 scale);
4646 *input_line_pointer = sep;
4647 input_line_pointer = save;
4648 return NULL;
4649 }
252b5132 4650 }
29b0f896 4651 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4652 {
4653 as_warn (_("scale factor of %d without an index register"),
24eab124 4654 1 << i.log2_scale_factor);
252b5132
RH		 4655#if SCALE1_WHEN_NO_INDEX
4656 i.log2_scale_factor = 0;
4657#endif
4658 }
551c1ca1
AM		 4659 scale = input_line_pointer;
4660 input_line_pointer = save;
4661 return scale;
252b5132
RH		 4662}
4663
252b5132 4664static int
e3bb37b5 4665i386_displacement (char *disp_start, char *disp_end)
252b5132 4666{
29b0f896 4667 expressionS *exp;
252b5132
RH		 4668 segT exp_seg = 0;
4669 char *save_input_line_pointer;
f3c180ae 4670 char *gotfree_input_line;
e05278af 4671 int bigdisp, override;
3956db08 4672 unsigned int types = Disp;
252b5132 4673
31b2323c
L		 4674 if (i.disp_operands == MAX_MEMORY_OPERANDS)
4675 {
4676 as_bad (_("at most %d displacement operands are allowed"),
4677 MAX_MEMORY_OPERANDS);
4678 return 0;
4679 }
4680
e05278af
JB		 4681 if ((i.types[this_operand] & JumpAbsolute)
4682 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4683 {
4684 bigdisp = Disp32;
4685 override = (i.prefix[ADDR_PREFIX] != 0);
4686 }
4687 else
4688 {
4689 /* For PC-relative branches, the width of the displacement
4690 is dependent upon data size, not address size. */
4691 bigdisp = 0;
4692 override = (i.prefix[DATA_PREFIX] != 0);
4693 }
3e73aa7c 4694 if (flag_code == CODE_64BIT)
7ecd2f8b 4695 {
e05278af 4696 if (!bigdisp)
64e74474
AM		 4697 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4698 ? Disp16
4699 : Disp32S | Disp32);
e05278af 4700 else if (!override)
3956db08 4701 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b 4702 }
e05278af
JB		 4703 else
4704 {
4705 if (!bigdisp)
4706 {
4707 if (!override)
4708 override = (i.suffix == (flag_code != CODE_16BIT
4709 ? WORD_MNEM_SUFFIX
4710 : LONG_MNEM_SUFFIX));
4711 bigdisp = Disp32;
4712 }
4713 if ((flag_code == CODE_16BIT) ^ override)
4714 bigdisp = Disp16;
4715 }
252b5132
RH		 4716 i.types[this_operand] |= bigdisp;
4717
4718 exp = &disp_expressions[i.disp_operands];
520dc8e8 4719 i.op[this_operand].disps = exp;
252b5132
RH		 4720 i.disp_operands++;
4721 save_input_line_pointer = input_line_pointer;
4722 input_line_pointer = disp_start;
4723 END_STRING_AND_SAVE (disp_end);
4724
4725#ifndef GCC_ASM_O_HACK
4726#define GCC_ASM_O_HACK 0
4727#endif
4728#if GCC_ASM_O_HACK
4729 END_STRING_AND_SAVE (disp_end + 1);
4730 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4731 && displacement_string_end[-1] == '+')
252b5132
RH		 4732 {
4733 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4734 constraint within gcc asm statements.
4735 For instance:
4736
4737 #define _set_tssldt_desc(n,addr,limit,type) \
4738 __asm__ __volatile__ ( \
4739 "movw %w2,%0\n\t" \
4740 "movw %w1,2+%0\n\t" \
4741 "rorl $16,%1\n\t" \
4742 "movb %b1,4+%0\n\t" \
4743 "movb %4,5+%0\n\t" \
4744 "movb $0,6+%0\n\t" \
4745 "movb %h1,7+%0\n\t" \
4746 "rorl $16,%1" \
4747 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4748
4749 This works great except that the output assembler ends
4750 up looking a bit weird if it turns out that there is
4751 no offset. You end up producing code that looks like:
4752
4753 #APP
4754 movw $235,(%eax)
4755 movw %dx,2+(%eax)
4756 rorl $16,%edx
4757 movb %dl,4+(%eax)
4758 movb $137,5+(%eax)
4759 movb $0,6+(%eax)
4760 movb %dh,7+(%eax)
4761 rorl $16,%edx
4762 #NO_APP
4763
47926f60 4764 So here we provide the missing zero. */
24eab124
AM		 4765
4766 *displacement_string_end = '0';
252b5132
RH		 4767 }
4768#endif
3956db08 4769 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4770 if (gotfree_input_line)
4771 input_line_pointer = gotfree_input_line;
252b5132 4772
24eab124 4773 exp_seg = expression (exp);
252b5132 4774
636c26b0
AM		 4775 SKIP_WHITESPACE ();
4776 if (*input_line_pointer)
4777 as_bad (_("junk `%s' after expression"), input_line_pointer);
4778#if GCC_ASM_O_HACK
4779 RESTORE_END_STRING (disp_end + 1);
4780#endif
4781 RESTORE_END_STRING (disp_end);
4782 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4783 if (gotfree_input_line)
4784 free (gotfree_input_line);
636c26b0 4785
24eab124
AM		 4786 /* We do this to make sure that the section symbol is in
4787 the symbol table. We will ultimately change the relocation
47926f60 4788 to be relative to the beginning of the section. */
1ae12ab7 4789 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4790 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4791 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4792 {
636c26b0
AM		 4793 if (exp->X_op != O_symbol)
4794 {
4795 as_bad (_("bad expression used with @%s"),
4796 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4797 ? "GOTPCREL"
4798 : "GOTOFF"));
4799 return 0;
4800 }
4801
e5cb08ac 4802 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4803 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4804 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4805 exp->X_op = O_subtract;
4806 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4807 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4808 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4809 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4810 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4811 else
29b0f896 4812 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4813 }
252b5132 4814
2daf4fd8
AM		 4815 if (exp->X_op == O_absent || exp->X_op == O_big)
4816 {
47926f60 4817 /* Missing or bad expr becomes absolute 0. */
d0b47220 4818 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4819 disp_start);
4820 exp->X_op = O_constant;
4821 exp->X_add_number = 0;
4822 exp->X_add_symbol = (symbolS *) 0;
4823 exp->X_op_symbol = (symbolS *) 0;
4824 }
4825
4c63da97 4826#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4827 if (exp->X_op != O_constant
45288df1 4828 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4829 && exp_seg != absolute_section
45288df1
AM		 4830 && exp_seg != text_section
4831 && exp_seg != data_section
4832 && exp_seg != bss_section
31312f95 4833 && exp_seg != undefined_section
f86103b7 4834 && !bfd_is_com_section (exp_seg))
24eab124 4835 {
d0b47220 4836 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4837 return 0;
4838 }
252b5132 4839#endif
3956db08
JB		 4840
4841 if (!(i.types[this_operand] & ~Disp))
4842 i.types[this_operand] &= types;
4843
252b5132
RH		 4844 return 1;
4845}
4846
eecb386c 4847/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4848 Return 1 on success, 0 on a failure. */
4849
252b5132 4850static int
e3bb37b5 4851i386_index_check (const char *operand_string)
252b5132 4852{
3e73aa7c 4853 int ok;
24eab124 4854#if INFER_ADDR_PREFIX
eecb386c
AM		 4855 int fudged = 0;
4856
24eab124
AM		 4857 tryprefix:
4858#endif
3e73aa7c 4859 ok = 1;
30123838
JB		 4860 if ((current_templates->start->cpu_flags & CpuSVME)
4861 && current_templates->end[-1].operand_types[0] == AnyMem)
4862 {
4863 /* Memory operands of SVME insns are special in that they only allow
4864 rAX as their memory address and ignore any segment override. */
4865 unsigned RegXX;
4866
4867 /* SKINIT is even more restrictive: it always requires EAX. */
4868 if (strcmp (current_templates->start->name, "skinit") == 0)
4869 RegXX = Reg32;
4870 else if (flag_code == CODE_64BIT)
4871 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4872 else
64e74474
AM		 4873 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4874 ? Reg16
4875 : Reg32);
30123838
JB		 4876 if (!i.base_reg
4877 || !(i.base_reg->reg_type & Acc)
4878 || !(i.base_reg->reg_type & RegXX)
4879 || i.index_reg
4880 || (i.types[0] & Disp))
4881 ok = 0;
4882 }
4883 else if (flag_code == CODE_64BIT)
64e74474
AM		 4884 {
4885 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4886
4887 if ((i.base_reg
4888 && ((i.base_reg->reg_type & RegXX) == 0)
4889 && (i.base_reg->reg_type != BaseIndex
4890 || i.index_reg))
4891 || (i.index_reg
4892 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4893 != (RegXX | BaseIndex))))
4894 ok = 0;
3e73aa7c
JH		 4895 }
4896 else
4897 {
4898 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4899 {
4900 /* 16bit checks. */
4901 if ((i.base_reg
29b0f896
AM		 4902 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4903 != (Reg16 | BaseIndex)))
3e73aa7c 4904 || (i.index_reg
29b0f896
AM		 4905 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4906 != (Reg16 | BaseIndex))
4907 || !(i.base_reg
4908 && i.base_reg->reg_num < 6
4909 && i.index_reg->reg_num >= 6
4910 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4911 ok = 0;
4912 }
4913 else
e5cb08ac 4914 {
3e73aa7c
JH		 4915 /* 32bit checks. */
4916 if ((i.base_reg
4917 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4918 || (i.index_reg
29b0f896
AM		 4919 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4920 != (Reg32 | BaseIndex))))
e5cb08ac 4921 ok = 0;
3e73aa7c
JH		 4922 }
4923 }
4924 if (!ok)
24eab124
AM		 4925 {
4926#if INFER_ADDR_PREFIX
20f0a1fc 4927 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4928 {
4929 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4930 i.prefixes += 1;
b23bac36
AM		 4931 /* Change the size of any displacement too. At most one of
4932 Disp16 or Disp32 is set.
4933 FIXME. There doesn't seem to be any real need for separate
4934 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4935 Removing them would probably clean up the code quite a lot. */
4eed87de
AM		 4936 if (flag_code != CODE_64BIT
4937 && (i.types[this_operand] & (Disp16 | Disp32)))
64e74474 4938 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4939 fudged = 1;
24eab124
AM		 4940 goto tryprefix;
4941 }
eecb386c
AM		 4942 if (fudged)
4943 as_bad (_("`%s' is not a valid base/index expression"),
4944 operand_string);
4945 else
c388dee8 4946#endif
eecb386c
AM		 4947 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4948 operand_string,
3e73aa7c 4949 flag_code_names[flag_code]);
24eab124 4950 }
20f0a1fc 4951 return ok;
24eab124 4952}
252b5132 4953
252b5132 4954/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4955 on error. */
252b5132 4956
252b5132 4957static int
e3bb37b5 4958i386_operand (char *operand_string)
252b5132 4959{
af6bdddf
AM		 4960 const reg_entry *r;
4961 char *end_op;
24eab124 4962 char *op_string = operand_string;
252b5132 4963
24eab124 4964 if (is_space_char (*op_string))
252b5132
RH		 4965 ++op_string;
4966
24eab124 4967 /* We check for an absolute prefix (differentiating,
47926f60 4968 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4969 if (*op_string == ABSOLUTE_PREFIX)
4970 {
4971 ++op_string;
4972 if (is_space_char (*op_string))
4973 ++op_string;
4974 i.types[this_operand] |= JumpAbsolute;
4975 }
252b5132 4976
47926f60 4977 /* Check if operand is a register. */
4d1bb795 4978 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 4979 {
24eab124
AM		 4980 /* Check for a segment override by searching for ':' after a
4981 segment register. */
4982 op_string = end_op;
4983 if (is_space_char (*op_string))
4984 ++op_string;
4985 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4986 {
4987 switch (r->reg_num)
4988 {
4989 case 0:
4990 i.seg[i.mem_operands] = &es;
4991 break;
4992 case 1:
4993 i.seg[i.mem_operands] = &cs;
4994 break;
4995 case 2:
4996 i.seg[i.mem_operands] = &ss;
4997 break;
4998 case 3:
4999 i.seg[i.mem_operands] = &ds;
5000 break;
5001 case 4:
5002 i.seg[i.mem_operands] = &fs;
5003 break;
5004 case 5:
5005 i.seg[i.mem_operands] = &gs;
5006 break;
5007 }
252b5132 5008
24eab124 5009 /* Skip the ':' and whitespace. */
252b5132
RH		 5010 ++op_string;
5011 if (is_space_char (*op_string))
24eab124 5012 ++op_string;
252b5132 5013
24eab124
AM		 5014 if (!is_digit_char (*op_string)
5015 && !is_identifier_char (*op_string)
5016 && *op_string != '('
5017 && *op_string != ABSOLUTE_PREFIX)
5018 {
5019 as_bad (_("bad memory operand `%s'"), op_string);
5020 return 0;
5021 }
47926f60 5022 /* Handle case of %es:*foo. */
24eab124
AM		 5023 if (*op_string == ABSOLUTE_PREFIX)
5024 {
5025 ++op_string;
5026 if (is_space_char (*op_string))
5027 ++op_string;
5028 i.types[this_operand] |= JumpAbsolute;
5029 }
5030 goto do_memory_reference;
5031 }
5032 if (*op_string)
5033 {
d0b47220 5034 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 5035 return 0;
5036 }
5037 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 5038 i.op[this_operand].regs = r;
24eab124
AM		 5039 i.reg_operands++;
5040 }
af6bdddf
AM		 5041 else if (*op_string == REGISTER_PREFIX)
5042 {
5043 as_bad (_("bad register name `%s'"), op_string);
5044 return 0;
5045 }
24eab124 5046 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 5047 {
24eab124
AM		 5048 ++op_string;
5049 if (i.types[this_operand] & JumpAbsolute)
5050 {
d0b47220 5051 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 5052 return 0;
5053 }
5054 if (!i386_immediate (op_string))
5055 return 0;
5056 }
5057 else if (is_digit_char (*op_string)
5058 || is_identifier_char (*op_string)
e5cb08ac 5059 || *op_string == '(')
24eab124 5060 {
47926f60 5061 /* This is a memory reference of some sort. */
af6bdddf 5062 char *base_string;
252b5132 5063
47926f60 5064 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 5065 char *displacement_string_start;
5066 char *displacement_string_end;
252b5132 5067
24eab124 5068 do_memory_reference:
24eab124
AM		 5069 if ((i.mem_operands == 1
5070 && (current_templates->start->opcode_modifier & IsString) == 0)
5071 || i.mem_operands == 2)
5072 {
5073 as_bad (_("too many memory references for `%s'"),
5074 current_templates->start->name);
5075 return 0;
5076 }
252b5132 5077
24eab124
AM		 5078 /* Check for base index form. We detect the base index form by
5079 looking for an ')' at the end of the operand, searching
5080 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5081 after the '('. */
af6bdddf 5082 base_string = op_string + strlen (op_string);
c3332e24 5083
af6bdddf
AM		 5084 --base_string;
5085 if (is_space_char (*base_string))
5086 --base_string;
252b5132 5087
47926f60 5088 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 5089 displacement_string_start = op_string;
5090 displacement_string_end = base_string + 1;
252b5132 5091
24eab124
AM		 5092 if (*base_string == ')')
5093 {
af6bdddf 5094 char *temp_string;
24eab124
AM		 5095 unsigned int parens_balanced = 1;
5096 /* We've already checked that the number of left & right ()'s are
47926f60 5097 equal, so this loop will not be infinite. */
24eab124
AM		 5098 do
5099 {
5100 base_string--;
5101 if (*base_string == ')')
5102 parens_balanced++;
5103 if (*base_string == '(')
5104 parens_balanced--;
5105 }
5106 while (parens_balanced);
c3332e24 5107
af6bdddf 5108 temp_string = base_string;
c3332e24 5109
24eab124 5110 /* Skip past '(' and whitespace. */
252b5132
RH		 5111 ++base_string;
5112 if (is_space_char (*base_string))
24eab124 5113 ++base_string;
252b5132 5114
af6bdddf 5115 if (*base_string == ','
4eed87de
AM		 5116 || ((i.base_reg = parse_register (base_string, &end_op))
5117 != NULL))
252b5132 5118 {
af6bdddf 5119 displacement_string_end = temp_string;
252b5132 5120
af6bdddf 5121 i.types[this_operand] |= BaseIndex;
252b5132 5122
af6bdddf 5123 if (i.base_reg)
24eab124 5124 {
24eab124
AM		 5125 base_string = end_op;
5126 if (is_space_char (*base_string))
5127 ++base_string;
af6bdddf
AM		 5128 }
5129
5130 /* There may be an index reg or scale factor here. */
5131 if (*base_string == ',')
5132 {
5133 ++base_string;
5134 if (is_space_char (*base_string))
5135 ++base_string;
5136
4eed87de
AM		 5137 if ((i.index_reg = parse_register (base_string, &end_op))
5138 != NULL)
24eab124 5139 {
af6bdddf 5140 base_string = end_op;
24eab124
AM		 5141 if (is_space_char (*base_string))
5142 ++base_string;
af6bdddf
AM		 5143 if (*base_string == ',')
5144 {
5145 ++base_string;
5146 if (is_space_char (*base_string))
5147 ++base_string;
5148 }
e5cb08ac 5149 else if (*base_string != ')')
af6bdddf 5150 {
4eed87de
AM		 5151 as_bad (_("expecting `,' or `)' "
5152 "after index register in `%s'"),
af6bdddf
AM		 5153 operand_string);
5154 return 0;
5155 }
24eab124 5156 }
af6bdddf 5157 else if (*base_string == REGISTER_PREFIX)
24eab124 5158 {
af6bdddf 5159 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 5160 return 0;
5161 }
252b5132 5162
47926f60 5163 /* Check for scale factor. */
551c1ca1 5164 if (*base_string != ')')
af6bdddf 5165 {
551c1ca1
AM		 5166 char *end_scale = i386_scale (base_string);
5167
5168 if (!end_scale)
af6bdddf 5169 return 0;
24eab124 5170
551c1ca1 5171 base_string = end_scale;
af6bdddf
AM		 5172 if (is_space_char (*base_string))
5173 ++base_string;
5174 if (*base_string != ')')
5175 {
4eed87de
AM		 5176 as_bad (_("expecting `)' "
5177 "after scale factor in `%s'"),
af6bdddf
AM		 5178 operand_string);
5179 return 0;
5180 }
5181 }
5182 else if (!i.index_reg)
24eab124 5183 {
4eed87de
AM		 5184 as_bad (_("expecting index register or scale factor "
5185 "after `,'; got '%c'"),
af6bdddf 5186 *base_string);
24eab124
AM		 5187 return 0;
5188 }
5189 }
af6bdddf 5190 else if (*base_string != ')')
24eab124 5191 {
4eed87de
AM		 5192 as_bad (_("expecting `,' or `)' "
5193 "after base register in `%s'"),
af6bdddf 5194 operand_string);
24eab124
AM		 5195 return 0;
5196 }
c3332e24 5197 }
af6bdddf 5198 else if (*base_string == REGISTER_PREFIX)
c3332e24 5199 {
af6bdddf 5200 as_bad (_("bad register name `%s'"), base_string);
24eab124 5201 return 0;
c3332e24 5202 }
24eab124
AM		 5203 }
5204
5205 /* If there's an expression beginning the operand, parse it,
5206 assuming displacement_string_start and
5207 displacement_string_end are meaningful. */
5208 if (displacement_string_start != displacement_string_end)
5209 {
5210 if (!i386_displacement (displacement_string_start,
5211 displacement_string_end))
5212 return 0;
5213 }
5214
5215 /* Special case for (%dx) while doing input/output op. */
5216 if (i.base_reg
5217 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5218 && i.index_reg == 0
5219 && i.log2_scale_factor == 0
5220 && i.seg[i.mem_operands] == 0
5221 && (i.types[this_operand] & Disp) == 0)
5222 {
5223 i.types[this_operand] = InOutPortReg;
5224 return 1;
5225 }
5226
eecb386c
AM		 5227 if (i386_index_check (operand_string) == 0)
5228 return 0;
24eab124
AM		 5229 i.mem_operands++;
5230 }
5231 else
ce8a8b2f
AM		 5232 {
5233 /* It's not a memory operand; argh! */
24eab124
AM		 5234 as_bad (_("invalid char %s beginning operand %d `%s'"),
5235 output_invalid (*op_string),
5236 this_operand + 1,
5237 op_string);
5238 return 0;
5239 }
47926f60 5240 return 1; /* Normal return. */
252b5132
RH		 5241}
5242\f
ee7fcc42
AM		 5243/* md_estimate_size_before_relax()
5244
5245 Called just before relax() for rs_machine_dependent frags. The x86
5246 assembler uses these frags to handle variable size jump
5247 instructions.
5248
5249 Any symbol that is now undefined will not become defined.
5250 Return the correct fr_subtype in the frag.
5251 Return the initial "guess for variable size of frag" to caller.
5252 The guess is actually the growth beyond the fixed part. Whatever
5253 we do to grow the fixed or variable part contributes to our
5254 returned value. */
5255
252b5132
RH		 5256int
5257md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 5258 fragS *fragP;
5259 segT segment;
252b5132 5260{
252b5132 5261 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 5262 check for un-relaxable symbols. On an ELF system, we can't relax
5263 an externally visible symbol, because it may be overridden by a
5264 shared library. */
5265 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 5266#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5267 || (IS_ELF
31312f95
AM		 5268 && (S_IS_EXTERNAL (fragP->fr_symbol)
5269 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 5270#endif
5271 )
252b5132 5272 {
b98ef147
AM		 5273 /* Symbol is undefined in this segment, or we need to keep a
5274 reloc so that weak symbols can be overridden. */
5275 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 5276 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 5277 unsigned char *opcode;
5278 int old_fr_fix;
f6af82bd 5279
ee7fcc42
AM		 5280 if (fragP->fr_var != NO_RELOC)
5281 reloc_type = fragP->fr_var;
b98ef147 5282 else if (size == 2)
f6af82bd
AM		 5283 reloc_type = BFD_RELOC_16_PCREL;
5284 else
5285 reloc_type = BFD_RELOC_32_PCREL;
252b5132 5286
ee7fcc42
AM		 5287 old_fr_fix = fragP->fr_fix;
5288 opcode = (unsigned char *) fragP->fr_opcode;
5289
fddf5b5b 5290 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 5291 {
fddf5b5b
AM		 5292 case UNCOND_JUMP:
5293 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 5294 opcode[0] = 0xe9;
252b5132 5295 fragP->fr_fix += size;
062cd5e7
AS		 5296 fix_new (fragP, old_fr_fix, size,
5297 fragP->fr_symbol,
5298 fragP->fr_offset, 1,
5299 reloc_type);
252b5132
RH		 5300 break;
5301
fddf5b5b 5302 case COND_JUMP86:
412167cb
AM		 5303 if (size == 2
5304 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 5305 {
5306 /* Negate the condition, and branch past an
5307 unconditional jump. */
5308 opcode[0] ^= 1;
5309 opcode[1] = 3;
5310 /* Insert an unconditional jump. */
5311 opcode[2] = 0xe9;
5312 /* We added two extra opcode bytes, and have a two byte
5313 offset. */
5314 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 5315 fix_new (fragP, old_fr_fix + 2, 2,
5316 fragP->fr_symbol,
5317 fragP->fr_offset, 1,
5318 reloc_type);
fddf5b5b
AM		 5319 break;
5320 }
5321 /* Fall through. */
5322
5323 case COND_JUMP:
412167cb
AM		 5324 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5325 {
3e02c1cc
AM		 5326 fixS *fixP;
5327
412167cb 5328 fragP->fr_fix += 1;
3e02c1cc
AM		 5329 fixP = fix_new (fragP, old_fr_fix, 1,
5330 fragP->fr_symbol,
5331 fragP->fr_offset, 1,
5332 BFD_RELOC_8_PCREL);
5333 fixP->fx_signed = 1;
412167cb
AM		 5334 break;
5335 }
93c2a809 5336
24eab124 5337 /* This changes the byte-displacement jump 0x7N
fddf5b5b 5338 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 5339 opcode[1] = opcode[0] + 0x10;
f6af82bd 5340 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 5341 /* We've added an opcode byte. */
5342 fragP->fr_fix += 1 + size;
062cd5e7
AS		 5343 fix_new (fragP, old_fr_fix + 1, size,
5344 fragP->fr_symbol,
5345 fragP->fr_offset, 1,
5346 reloc_type);
252b5132 5347 break;
fddf5b5b
AM		 5348
5349 default:
5350 BAD_CASE (fragP->fr_subtype);
5351 break;
252b5132
RH		 5352 }
5353 frag_wane (fragP);
ee7fcc42 5354 return fragP->fr_fix - old_fr_fix;
252b5132 5355 }
93c2a809 5356
93c2a809
AM		 5357 /* Guess size depending on current relax state. Initially the relax
5358 state will correspond to a short jump and we return 1, because
5359 the variable part of the frag (the branch offset) is one byte
5360 long. However, we can relax a section more than once and in that
5361 case we must either set fr_subtype back to the unrelaxed state,
5362 or return the value for the appropriate branch. */
5363 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 5364}
5365
47926f60
KH		 5366/* Called after relax() is finished.
5367
5368 In: Address of frag.
5369 fr_type == rs_machine_dependent.
5370 fr_subtype is what the address relaxed to.
5371
5372 Out: Any fixSs and constants are set up.
5373 Caller will turn frag into a ".space 0". */
5374
252b5132
RH		 5375void
5376md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 5377 bfd *abfd ATTRIBUTE_UNUSED;
5378 segT sec ATTRIBUTE_UNUSED;
29b0f896 5379 fragS *fragP;
252b5132 5380{
29b0f896 5381 unsigned char *opcode;
252b5132 5382 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 5383 offsetT target_address;
5384 offsetT opcode_address;
252b5132 5385 unsigned int extension = 0;
847f7ad4 5386 offsetT displacement_from_opcode_start;
252b5132
RH		 5387
5388 opcode = (unsigned char *) fragP->fr_opcode;
5389
47926f60 5390 /* Address we want to reach in file space. */
252b5132 5391 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 5392
47926f60 5393 /* Address opcode resides at in file space. */
252b5132
RH		 5394 opcode_address = fragP->fr_address + fragP->fr_fix;
5395
47926f60 5396 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 5397 displacement_from_opcode_start = target_address - opcode_address;
5398
fddf5b5b 5399 if ((fragP->fr_subtype & BIG) == 0)
252b5132 5400 {
47926f60
KH		 5401 /* Don't have to change opcode. */
5402 extension = 1; /* 1 opcode + 1 displacement */
252b5132 5403 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 5404 }
5405 else
5406 {
5407 if (no_cond_jump_promotion
5408 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 5409 as_warn_where (fragP->fr_file, fragP->fr_line,
5410 _("long jump required"));
252b5132 5411
fddf5b5b
AM		 5412 switch (fragP->fr_subtype)
5413 {
5414 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5415 extension = 4; /* 1 opcode + 4 displacement */
5416 opcode[0] = 0xe9;
5417 where_to_put_displacement = &opcode[1];
5418 break;
252b5132 5419
fddf5b5b
AM		 5420 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5421 extension = 2; /* 1 opcode + 2 displacement */
5422 opcode[0] = 0xe9;
5423 where_to_put_displacement = &opcode[1];
5424 break;
252b5132 5425
fddf5b5b
AM		 5426 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5427 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5428 extension = 5; /* 2 opcode + 4 displacement */
5429 opcode[1] = opcode[0] + 0x10;
5430 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5431 where_to_put_displacement = &opcode[2];
5432 break;
252b5132 5433
fddf5b5b
AM		 5434 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5435 extension = 3; /* 2 opcode + 2 displacement */
5436 opcode[1] = opcode[0] + 0x10;
5437 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5438 where_to_put_displacement = &opcode[2];
5439 break;
252b5132 5440
fddf5b5b
AM		 5441 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5442 extension = 4;
5443 opcode[0] ^= 1;
5444 opcode[1] = 3;
5445 opcode[2] = 0xe9;
5446 where_to_put_displacement = &opcode[3];
5447 break;
5448
5449 default:
5450 BAD_CASE (fragP->fr_subtype);
5451 break;
5452 }
252b5132 5453 }
fddf5b5b 5454
7b81dfbb
AJ		 5455 /* If size if less then four we are sure that the operand fits,
5456 but if it's 4, then it could be that the displacement is larger
5457 then -/+ 2GB. */
5458 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5459 && object_64bit
5460 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 5461 + ((addressT) 1 << 31))
5462 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 5463 {
5464 as_bad_where (fragP->fr_file, fragP->fr_line,
5465 _("jump target out of range"));
5466 /* Make us emit 0. */
5467 displacement_from_opcode_start = extension;
5468 }
47926f60 5469 /* Now put displacement after opcode. */
252b5132
RH		 5470 md_number_to_chars ((char *) where_to_put_displacement,
5471 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 5472 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 5473 fragP->fr_fix += extension;
5474}
5475\f
47926f60
KH		 5476/* Size of byte displacement jmp. */
5477int md_short_jump_size = 2;
5478
5479/* Size of dword displacement jmp. */
5480int md_long_jump_size = 5;
252b5132 5481
252b5132
RH		 5482void
5483md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5484 char *ptr;
5485 addressT from_addr, to_addr;
ab9da554
ILT		 5486 fragS *frag ATTRIBUTE_UNUSED;
5487 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5488{
847f7ad4 5489 offsetT offset;
252b5132
RH		 5490
5491 offset = to_addr - (from_addr + 2);
47926f60
KH		 5492 /* Opcode for byte-disp jump. */
5493 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 5494 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5495}
5496
5497void
5498md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5499 char *ptr;
5500 addressT from_addr, to_addr;
a38cf1db
AM		 5501 fragS *frag ATTRIBUTE_UNUSED;
5502 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5503{
847f7ad4 5504 offsetT offset;
252b5132 5505
a38cf1db
AM		 5506 offset = to_addr - (from_addr + 5);
5507 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5508 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 5509}
5510\f
5511/* Apply a fixup (fixS) to segment data, once it has been determined
5512 by our caller that we have all the info we need to fix it up.
5513
5514 On the 386, immediates, displacements, and data pointers are all in
5515 the same (little-endian) format, so we don't need to care about which
5516 we are handling. */
5517
94f592af 5518void
55cf6793 5519md_apply_fix (fixP, valP, seg)
47926f60
KH		 5520 /* The fix we're to put in. */
5521 fixS *fixP;
47926f60 5522 /* Pointer to the value of the bits. */
c6682705 5523 valueT *valP;
47926f60
KH		 5524 /* Segment fix is from. */
5525 segT seg ATTRIBUTE_UNUSED;
252b5132 5526{
94f592af 5527 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 5528 valueT value = *valP;
252b5132 5529
f86103b7 5530#if !defined (TE_Mach)
93382f6d
AM		 5531 if (fixP->fx_pcrel)
5532 {
5533 switch (fixP->fx_r_type)
5534 {
5865bb77
ILT		 5535 default:
5536 break;
5537
d6ab8113
JB		 5538 case BFD_RELOC_64:
5539 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5540 break;
93382f6d 5541 case BFD_RELOC_32:
ae8887b5 5542 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 5543 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5544 break;
5545 case BFD_RELOC_16:
5546 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5547 break;
5548 case BFD_RELOC_8:
5549 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5550 break;
5551 }
5552 }
252b5132 5553
a161fe53 5554 if (fixP->fx_addsy != NULL
31312f95 5555 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 5556 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 5557 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5558 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5559 && !use_rela_relocations)
252b5132 5560 {
31312f95
AM		 5561 /* This is a hack. There should be a better way to handle this.
5562 This covers for the fact that bfd_install_relocation will
5563 subtract the current location (for partial_inplace, PC relative
5564 relocations); see more below. */
252b5132 5565#ifndef OBJ_AOUT
718ddfc0 5566 if (IS_ELF
252b5132
RH		 5567#ifdef TE_PE
5568 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5569#endif
5570 )
5571 value += fixP->fx_where + fixP->fx_frag->fr_address;
5572#endif
5573#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5574 if (IS_ELF)
252b5132 5575 {
6539b54b 5576 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 5577
6539b54b 5578 if ((sym_seg == seg
2f66722d 5579 || (symbol_section_p (fixP->fx_addsy)
6539b54b 5580 && sym_seg != absolute_section))
ae6063d4 5581 && !generic_force_reloc (fixP))
2f66722d
AM		 5582 {
5583 /* Yes, we add the values in twice. This is because
6539b54b
AM		 5584 bfd_install_relocation subtracts them out again. I think
5585 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 5586 it. FIXME. */
5587 value += fixP->fx_where + fixP->fx_frag->fr_address;
5588 }
252b5132
RH		 5589 }
5590#endif
5591#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 5592 /* For some reason, the PE format does not store a
5593 section address offset for a PC relative symbol. */
5594 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 5595 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 5596 value += md_pcrel_from (fixP);
5597#endif
5598 }
5599
5600 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 5601 and we must not disappoint it. */
252b5132 5602#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5603 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 5604 switch (fixP->fx_r_type)
5605 {
5606 case BFD_RELOC_386_PLT32:
3e73aa7c 5607 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 5608 /* Make the jump instruction point to the address of the operand. At
5609 runtime we merely add the offset to the actual PLT entry. */
5610 value = -4;
5611 break;
31312f95 5612
13ae64f3
JJ		 5613 case BFD_RELOC_386_TLS_GD:
5614 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5615 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5616 case BFD_RELOC_386_TLS_IE:
5617 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 5618 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 5619 case BFD_RELOC_X86_64_TLSGD:
5620 case BFD_RELOC_X86_64_TLSLD:
5621 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 5622 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 5623 value = 0; /* Fully resolved at runtime. No addend. */
5624 /* Fallthrough */
5625 case BFD_RELOC_386_TLS_LE:
5626 case BFD_RELOC_386_TLS_LDO_32:
5627 case BFD_RELOC_386_TLS_LE_32:
5628 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5629 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5630 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5631 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5632 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5633 break;
5634
67a4f2b7
AO		 5635 case BFD_RELOC_386_TLS_DESC_CALL:
5636 case BFD_RELOC_X86_64_TLSDESC_CALL:
5637 value = 0; /* Fully resolved at runtime. No addend. */
5638 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5639 fixP->fx_done = 0;
5640 return;
5641
00f7efb6
JJ		 5642 case BFD_RELOC_386_GOT32:
5643 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5644 value = 0; /* Fully resolved at runtime. No addend. */
5645 break;
47926f60
KH		 5646
5647 case BFD_RELOC_VTABLE_INHERIT:
5648 case BFD_RELOC_VTABLE_ENTRY:
5649 fixP->fx_done = 0;
94f592af 5650 return;
47926f60
KH		 5651
5652 default:
5653 break;
5654 }
5655#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5656 *valP = value;
f86103b7 5657#endif /* !defined (TE_Mach) */
3e73aa7c 5658
3e73aa7c 5659 /* Are we finished with this relocation now? */
c6682705 5660 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5661 fixP->fx_done = 1;
5662 else if (use_rela_relocations)
5663 {
5664 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5665 /* Remember value for tc_gen_reloc. */
5666 fixP->fx_addnumber = value;
3e73aa7c
JH		 5667 value = 0;
5668 }
f86103b7 5669
94f592af 5670 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5671}
252b5132 5672\f
252b5132
RH		 5673#define MAX_LITTLENUMS 6
5674
47926f60
KH		 5675/* Turn the string pointed to by litP into a floating point constant
5676 of type TYPE, and emit the appropriate bytes. The number of
5677 LITTLENUMS emitted is stored in *SIZEP. An error message is
5678 returned, or NULL on OK. */
5679
252b5132
RH		 5680char *
5681md_atof (type, litP, sizeP)
2ab9b79e 5682 int type;
252b5132
RH		 5683 char *litP;
5684 int *sizeP;
5685{
5686 int prec;
5687 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5688 LITTLENUM_TYPE *wordP;
5689 char *t;
5690
5691 switch (type)
5692 {
5693 case 'f':
5694 case 'F':
5695 prec = 2;
5696 break;
5697
5698 case 'd':
5699 case 'D':
5700 prec = 4;
5701 break;
5702
5703 case 'x':
5704 case 'X':
5705 prec = 5;
5706 break;
5707
5708 default:
5709 *sizeP = 0;
5710 return _("Bad call to md_atof ()");
5711 }
5712 t = atof_ieee (input_line_pointer, type, words);
5713 if (t)
5714 input_line_pointer = t;
5715
5716 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5717 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5718 the bigendian 386. */
5719 for (wordP = words + prec - 1; prec--;)
5720 {
5721 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5722 litP += sizeof (LITTLENUM_TYPE);
5723 }
5724 return 0;
5725}
5726\f
2d545b82 5727static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 5728
252b5132 5729static char *
e3bb37b5 5730output_invalid (int c)
252b5132 5731{
3882b010 5732 if (ISPRINT (c))
f9f21a03
L		 5733 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5734 "'%c'", c);
252b5132 5735 else
f9f21a03 5736 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 5737 "(0x%x)", (unsigned char) c);
252b5132
RH		 5738 return output_invalid_buf;
5739}
5740
af6bdddf 5741/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5742
5743static const reg_entry *
4d1bb795 5744parse_real_register (char *reg_string, char **end_op)
252b5132 5745{
af6bdddf
AM		 5746 char *s = reg_string;
5747 char *p;
252b5132
RH		 5748 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5749 const reg_entry *r;
5750
5751 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5752 if (*s == REGISTER_PREFIX)
5753 ++s;
5754
5755 if (is_space_char (*s))
5756 ++s;
5757
5758 p = reg_name_given;
af6bdddf 5759 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5760 {
5761 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5762 return (const reg_entry *) NULL;
5763 s++;
252b5132
RH		 5764 }
5765
6588847e
DN		 5766 /* For naked regs, make sure that we are not dealing with an identifier.
5767 This prevents confusing an identifier like `eax_var' with register
5768 `eax'. */
5769 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5770 return (const reg_entry *) NULL;
5771
af6bdddf 5772 *end_op = s;
252b5132
RH		 5773
5774 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5775
5f47d35b 5776 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5777 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5778 {
5f47d35b
AM		 5779 if (is_space_char (*s))
5780 ++s;
5781 if (*s == '(')
5782 {
af6bdddf 5783 ++s;
5f47d35b
AM		 5784 if (is_space_char (*s))
5785 ++s;
5786 if (*s >= '0' && *s <= '7')
5787 {
5788 r = &i386_float_regtab[*s - '0'];
af6bdddf 5789 ++s;
5f47d35b
AM		 5790 if (is_space_char (*s))
5791 ++s;
5792 if (*s == ')')
5793 {
5794 *end_op = s + 1;
5795 return r;
5796 }
5f47d35b 5797 }
47926f60 5798 /* We have "%st(" then garbage. */
5f47d35b
AM		 5799 return (const reg_entry *) NULL;
5800 }
5801 }
5802
1ae00879 5803 if (r != NULL
20f0a1fc 5804 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5805 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5806 && flag_code != CODE_64BIT)
20f0a1fc 5807 return (const reg_entry *) NULL;
1ae00879 5808
252b5132
RH		 5809 return r;
5810}
4d1bb795
JB		 5811
5812/* REG_STRING starts *before* REGISTER_PREFIX. */
5813
5814static const reg_entry *
5815parse_register (char *reg_string, char **end_op)
5816{
5817 const reg_entry *r;
5818
5819 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5820 r = parse_real_register (reg_string, end_op);
5821 else
5822 r = NULL;
5823 if (!r)
5824 {
5825 char *save = input_line_pointer;
5826 char c;
5827 symbolS *symbolP;
5828
5829 input_line_pointer = reg_string;
5830 c = get_symbol_end ();
5831 symbolP = symbol_find (reg_string);
5832 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5833 {
5834 const expressionS *e = symbol_get_value_expression (symbolP);
5835
5836 know (e->X_op == O_register);
4eed87de 5837 know (e->X_add_number >= 0
c3fe08fa 5838 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 5839 r = i386_regtab + e->X_add_number;
5840 *end_op = input_line_pointer;
5841 }
5842 *input_line_pointer = c;
5843 input_line_pointer = save;
5844 }
5845 return r;
5846}
5847
5848int
5849i386_parse_name (char *name, expressionS *e, char *nextcharP)
5850{
5851 const reg_entry *r;
5852 char *end = input_line_pointer;
5853
5854 *end = *nextcharP;
5855 r = parse_register (name, &input_line_pointer);
5856 if (r && end <= input_line_pointer)
5857 {
5858 *nextcharP = *input_line_pointer;
5859 *input_line_pointer = 0;
5860 e->X_op = O_register;
5861 e->X_add_number = r - i386_regtab;
5862 return 1;
5863 }
5864 input_line_pointer = end;
5865 *end = 0;
5866 return 0;
5867}
5868
5869void
5870md_operand (expressionS *e)
5871{
5872 if (*input_line_pointer == REGISTER_PREFIX)
5873 {
5874 char *end;
5875 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5876
5877 if (r)
5878 {
5879 e->X_op = O_register;
5880 e->X_add_number = r - i386_regtab;
5881 input_line_pointer = end;
5882 }
5883 }
5884}
5885
252b5132 5886\f
4cc782b5 5887#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5888const char *md_shortopts = "kVQ:sqn";
252b5132 5889#else
12b55ccc 5890const char *md_shortopts = "qn";
252b5132 5891#endif
6e0b89ee 5892
3e73aa7c 5893#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 5894#define OPTION_64 (OPTION_MD_BASE + 1)
5895#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 5896#define OPTION_MARCH (OPTION_MD_BASE + 3)
5897#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714 5898
99ad8390
NC		 5899struct option md_longopts[] =
5900{
3e73aa7c 5901 {"32", no_argument, NULL, OPTION_32},
99ad8390 5902#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 5903 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5904#endif
b3b91714 5905 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 5906 {"march", required_argument, NULL, OPTION_MARCH},
5907 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH		 5908 {NULL, no_argument, NULL, 0}
5909};
5910size_t md_longopts_size = sizeof (md_longopts);
5911
5912int
9103f4f4 5913md_parse_option (int c, char *arg)
252b5132 5914{
9103f4f4
L		 5915 unsigned int i;
5916
252b5132
RH		 5917 switch (c)
5918 {
12b55ccc
L		 5919 case 'n':
5920 optimize_align_code = 0;
5921 break;
5922
a38cf1db
AM		 5923 case 'q':
5924 quiet_warnings = 1;
252b5132
RH		 5925 break;
5926
5927#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5928 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5929 should be emitted or not. FIXME: Not implemented. */
5930 case 'Q':
252b5132
RH		 5931 break;
5932
5933 /* -V: SVR4 argument to print version ID. */
5934 case 'V':
5935 print_version_id ();
5936 break;
5937
a38cf1db
AM		 5938 /* -k: Ignore for FreeBSD compatibility. */
5939 case 'k':
252b5132 5940 break;
4cc782b5
ILT		 5941
5942 case 's':
5943 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5944 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5945 break;
99ad8390
NC		 5946#endif
5947#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 5948 case OPTION_64:
5949 {
5950 const char **list, **l;
5951
3e73aa7c
JH		 5952 list = bfd_target_list ();
5953 for (l = list; *l != NULL; l++)
8620418b 5954 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 5955 || strcmp (*l, "coff-x86-64") == 0
5956 || strcmp (*l, "pe-x86-64") == 0
5957 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 5958 {
5959 default_arch = "x86_64";
5960 break;
5961 }
3e73aa7c 5962 if (*l == NULL)
6e0b89ee 5963 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5964 free (list);
5965 }
5966 break;
5967#endif
252b5132 5968
6e0b89ee
AM		 5969 case OPTION_32:
5970 default_arch = "i386";
5971 break;
5972
b3b91714
AM		 5973 case OPTION_DIVIDE:
5974#ifdef SVR4_COMMENT_CHARS
5975 {
5976 char *n, *t;
5977 const char *s;
5978
5979 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5980 t = n;
5981 for (s = i386_comment_chars; *s != '\0'; s++)
5982 if (*s != '/')
5983 *t++ = *s;
5984 *t = '\0';
5985 i386_comment_chars = n;
5986 }
5987#endif
5988 break;
5989
9103f4f4
L		 5990 case OPTION_MARCH:
5991 if (*arg == '.')
5992 as_fatal (_("Invalid -march= option: `%s'"), arg);
5993 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5994 {
5995 if (strcmp (arg, cpu_arch [i].name) == 0)
5996 {
ccc9c027 5997 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 5998 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 5999 if (!cpu_arch_tune_set)
6000 {
6001 cpu_arch_tune = cpu_arch_isa;
6002 cpu_arch_tune_flags = cpu_arch_isa_flags;
6003 }
9103f4f4
L		 6004 break;
6005 }
6006 }
6007 if (i >= ARRAY_SIZE (cpu_arch))
6008 as_fatal (_("Invalid -march= option: `%s'"), arg);
6009 break;
6010
6011 case OPTION_MTUNE:
6012 if (*arg == '.')
6013 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
6014 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
6015 {
6016 if (strcmp (arg, cpu_arch [i].name) == 0)
6017 {
ccc9c027 6018 cpu_arch_tune_set = 1;
9103f4f4
L		 6019 cpu_arch_tune = cpu_arch [i].type;
6020 cpu_arch_tune_flags = cpu_arch[i].flags;
6021 break;
6022 }
6023 }
6024 if (i >= ARRAY_SIZE (cpu_arch))
6025 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
6026 break;
6027
252b5132
RH		 6028 default:
6029 return 0;
6030 }
6031 return 1;
6032}
6033
6034void
6035md_show_usage (stream)
6036 FILE *stream;
6037{
4cc782b5
ILT		 6038#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6039 fprintf (stream, _("\
a38cf1db
AM		 6040 -Q ignored\n\
6041 -V print assembler version number\n\
b3b91714
AM		 6042 -k ignored\n"));
6043#endif
6044 fprintf (stream, _("\
12b55ccc 6045 -n Do not optimize code alignment\n\
b3b91714
AM		 6046 -q quieten some warnings\n"));
6047#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6048 fprintf (stream, _("\
a38cf1db 6049 -s ignored\n"));
b3b91714 6050#endif
751d281c
L		 6051#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6052 fprintf (stream, _("\
6053 --32/--64 generate 32bit/64bit code\n"));
6054#endif
b3b91714
AM		 6055#ifdef SVR4_COMMENT_CHARS
6056 fprintf (stream, _("\
6057 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 6058#else
6059 fprintf (stream, _("\
b3b91714 6060 --divide ignored\n"));
4cc782b5 6061#endif
9103f4f4
L		 6062 fprintf (stream, _("\
6063 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6064 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
4eed87de 6065 core, core2, k6, athlon, k8, generic32, generic64\n"));
9103f4f4 6066
252b5132
RH		 6067}
6068
99ad8390
NC		 6069#if defined(TE_PEP)
6070const char *
6071x86_64_target_format (void)
6072{
6073 if (strcmp (default_arch, "x86_64") == 0)
6074 {
6075 set_code_flag (CODE_64BIT);
6076 return COFF_TARGET_FORMAT;
6077 }
6078 else if (strcmp (default_arch, "i386") == 0)
6079 {
6080 set_code_flag (CODE_32BIT);
6081 return "coff-i386";
6082 }
6083
6084 as_fatal (_("Unknown architecture"));
6085 return NULL;
6086}
6087#endif
6088
3e73aa7c
JH		 6089#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6090 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 6091
6092/* Pick the target format to use. */
6093
47926f60 6094const char *
e3bb37b5 6095i386_target_format (void)
252b5132 6096{
3e73aa7c 6097 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 6098 {
6099 set_code_flag (CODE_64BIT);
6100 if (cpu_arch_isa_flags == 0)
d32cad65 6101 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
9103f4f4
L		 6102 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6103 |CpuSSE|CpuSSE2;
ccc9c027 6104 if (cpu_arch_tune_flags == 0)
d32cad65 6105 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
ccc9c027
L		 6106 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6107 |CpuSSE|CpuSSE2;
9103f4f4 6108 }
3e73aa7c 6109 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 6110 {
6111 set_code_flag (CODE_32BIT);
6112 if (cpu_arch_isa_flags == 0)
d32cad65 6113 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
ccc9c027 6114 if (cpu_arch_tune_flags == 0)
d32cad65 6115 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
9103f4f4 6116 }
3e73aa7c
JH		 6117 else
6118 as_fatal (_("Unknown architecture"));
252b5132
RH		 6119 switch (OUTPUT_FLAVOR)
6120 {
4c63da97
AM		 6121#ifdef OBJ_MAYBE_AOUT
6122 case bfd_target_aout_flavour:
47926f60 6123 return AOUT_TARGET_FORMAT;
4c63da97
AM		 6124#endif
6125#ifdef OBJ_MAYBE_COFF
252b5132
RH		 6126 case bfd_target_coff_flavour:
6127 return "coff-i386";
4c63da97 6128#endif
3e73aa7c 6129#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 6130 case bfd_target_elf_flavour:
3e73aa7c 6131 {
e5cb08ac 6132 if (flag_code == CODE_64BIT)
4fa24527
JB		 6133 {
6134 object_64bit = 1;
6135 use_rela_relocations = 1;
6136 }
9d7cbccd 6137 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 6138 }
4c63da97 6139#endif
252b5132
RH		 6140 default:
6141 abort ();
6142 return NULL;
6143 }
6144}
6145
47926f60 6146#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 6147
6148#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 6149void
6150i386_elf_emit_arch_note (void)
a847613f 6151{
718ddfc0 6152 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 6153 {
6154 char *p;
6155 asection *seg = now_seg;
6156 subsegT subseg = now_subseg;
6157 Elf_Internal_Note i_note;
6158 Elf_External_Note e_note;
6159 asection *note_secp;
6160 int len;
6161
6162 /* Create the .note section. */
6163 note_secp = subseg_new (".note", 0);
6164 bfd_set_section_flags (stdoutput,
6165 note_secp,
6166 SEC_HAS_CONTENTS | SEC_READONLY);
6167
6168 /* Process the arch string. */
6169 len = strlen (cpu_arch_name);
6170
6171 i_note.namesz = len + 1;
6172 i_note.descsz = 0;
6173 i_note.type = NT_ARCH;
6174 p = frag_more (sizeof (e_note.namesz));
6175 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6176 p = frag_more (sizeof (e_note.descsz));
6177 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6178 p = frag_more (sizeof (e_note.type));
6179 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6180 p = frag_more (len + 1);
6181 strcpy (p, cpu_arch_name);
6182
6183 frag_align (2, 0, 0);
6184
6185 subseg_set (seg, subseg);
6186 }
6187}
6188#endif
252b5132 6189\f
252b5132
RH		 6190symbolS *
6191md_undefined_symbol (name)
6192 char *name;
6193{
18dc2407
ILT		 6194 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6195 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6196 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6197 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 6198 {
6199 if (!GOT_symbol)
6200 {
6201 if (symbol_find (name))
6202 as_bad (_("GOT already in symbol table"));
6203 GOT_symbol = symbol_new (name, undefined_section,
6204 (valueT) 0, &zero_address_frag);
6205 };
6206 return GOT_symbol;
6207 }
252b5132
RH		 6208 return 0;
6209}
6210
6211/* Round up a section size to the appropriate boundary. */
47926f60 6212
252b5132
RH		 6213valueT
6214md_section_align (segment, size)
ab9da554 6215 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 6216 valueT size;
6217{
4c63da97
AM		 6218#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6219 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6220 {
6221 /* For a.out, force the section size to be aligned. If we don't do
6222 this, BFD will align it for us, but it will not write out the
6223 final bytes of the section. This may be a bug in BFD, but it is
6224 easier to fix it here since that is how the other a.out targets
6225 work. */
6226 int align;
6227
6228 align = bfd_get_section_alignment (stdoutput, segment);
6229 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6230 }
252b5132
RH		 6231#endif
6232
6233 return size;
6234}
6235
6236/* On the i386, PC-relative offsets are relative to the start of the
6237 next instruction. That is, the address of the offset, plus its
6238 size, since the offset is always the last part of the insn. */
6239
6240long
e3bb37b5 6241md_pcrel_from (fixS *fixP)
252b5132
RH		 6242{
6243 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6244}
6245
6246#ifndef I386COFF
6247
6248static void
e3bb37b5 6249s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 6250{
29b0f896 6251 int temp;
252b5132 6252
8a75718c
JB		 6253#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6254 if (IS_ELF)
6255 obj_elf_section_change_hook ();
6256#endif
252b5132
RH		 6257 temp = get_absolute_expression ();
6258 subseg_set (bss_section, (subsegT) temp);
6259 demand_empty_rest_of_line ();
6260}
6261
6262#endif
6263
252b5132 6264void
e3bb37b5 6265i386_validate_fix (fixS *fixp)
252b5132
RH		 6266{
6267 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6268 {
23df1078
JH		 6269 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6270 {
4fa24527 6271 if (!object_64bit)
23df1078
JH		 6272 abort ();
6273 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6274 }
6275 else
6276 {
4fa24527 6277 if (!object_64bit)
d6ab8113
JB		 6278 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6279 else
6280 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 6281 }
252b5132
RH		 6282 fixp->fx_subsy = 0;
6283 }
6284}
6285
252b5132
RH		 6286arelent *
6287tc_gen_reloc (section, fixp)
ab9da554 6288 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 6289 fixS *fixp;
6290{
6291 arelent *rel;
6292 bfd_reloc_code_real_type code;
6293
6294 switch (fixp->fx_r_type)
6295 {
3e73aa7c
JH		 6296 case BFD_RELOC_X86_64_PLT32:
6297 case BFD_RELOC_X86_64_GOT32:
6298 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 6299 case BFD_RELOC_386_PLT32:
6300 case BFD_RELOC_386_GOT32:
6301 case BFD_RELOC_386_GOTOFF:
6302 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 6303 case BFD_RELOC_386_TLS_GD:
6304 case BFD_RELOC_386_TLS_LDM:
6305 case BFD_RELOC_386_TLS_LDO_32:
6306 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6307 case BFD_RELOC_386_TLS_IE:
6308 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 6309 case BFD_RELOC_386_TLS_LE_32:
6310 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 6311 case BFD_RELOC_386_TLS_GOTDESC:
6312 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 6313 case BFD_RELOC_X86_64_TLSGD:
6314 case BFD_RELOC_X86_64_TLSLD:
6315 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6316 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 6317 case BFD_RELOC_X86_64_GOTTPOFF:
6318 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 6319 case BFD_RELOC_X86_64_TPOFF64:
6320 case BFD_RELOC_X86_64_GOTOFF64:
6321 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 6322 case BFD_RELOC_X86_64_GOT64:
6323 case BFD_RELOC_X86_64_GOTPCREL64:
6324 case BFD_RELOC_X86_64_GOTPC64:
6325 case BFD_RELOC_X86_64_GOTPLT64:
6326 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 6327 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6328 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 6329 case BFD_RELOC_RVA:
6330 case BFD_RELOC_VTABLE_ENTRY:
6331 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 6332#ifdef TE_PE
6333 case BFD_RELOC_32_SECREL:
6334#endif
252b5132
RH		 6335 code = fixp->fx_r_type;
6336 break;
dbbaec26
L		 6337 case BFD_RELOC_X86_64_32S:
6338 if (!fixp->fx_pcrel)
6339 {
6340 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6341 code = fixp->fx_r_type;
6342 break;
6343 }
252b5132 6344 default:
93382f6d 6345 if (fixp->fx_pcrel)
252b5132 6346 {
93382f6d
AM		 6347 switch (fixp->fx_size)
6348 {
6349 default:
b091f402
AM		 6350 as_bad_where (fixp->fx_file, fixp->fx_line,
6351 _("can not do %d byte pc-relative relocation"),
6352 fixp->fx_size);
93382f6d
AM		 6353 code = BFD_RELOC_32_PCREL;
6354 break;
6355 case 1: code = BFD_RELOC_8_PCREL; break;
6356 case 2: code = BFD_RELOC_16_PCREL; break;
6357 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 6358#ifdef BFD64
6359 case 8: code = BFD_RELOC_64_PCREL; break;
6360#endif
93382f6d
AM		 6361 }
6362 }
6363 else
6364 {
6365 switch (fixp->fx_size)
6366 {
6367 default:
b091f402
AM		 6368 as_bad_where (fixp->fx_file, fixp->fx_line,
6369 _("can not do %d byte relocation"),
6370 fixp->fx_size);
93382f6d
AM		 6371 code = BFD_RELOC_32;
6372 break;
6373 case 1: code = BFD_RELOC_8; break;
6374 case 2: code = BFD_RELOC_16; break;
6375 case 4: code = BFD_RELOC_32; break;
937149dd 6376#ifdef BFD64
3e73aa7c 6377 case 8: code = BFD_RELOC_64; break;
937149dd 6378#endif
93382f6d 6379 }
252b5132
RH		 6380 }
6381 break;
6382 }
252b5132 6383
d182319b
JB		 6384 if ((code == BFD_RELOC_32
6385 || code == BFD_RELOC_32_PCREL
6386 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 6387 && GOT_symbol
6388 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 6389 {
4fa24527 6390 if (!object_64bit)
d6ab8113
JB		 6391 code = BFD_RELOC_386_GOTPC;
6392 else
6393 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 6394 }
7b81dfbb
AJ		 6395 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6396 && GOT_symbol
6397 && fixp->fx_addsy == GOT_symbol)
6398 {
6399 code = BFD_RELOC_X86_64_GOTPC64;
6400 }
252b5132
RH		 6401
6402 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 6403 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6404 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 6405
6406 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 6407
3e73aa7c
JH		 6408 if (!use_rela_relocations)
6409 {
6410 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6411 vtable entry to be used in the relocation's section offset. */
6412 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6413 rel->address = fixp->fx_offset;
252b5132 6414
c6682705 6415 rel->addend = 0;
3e73aa7c
JH		 6416 }
6417 /* Use the rela in 64bit mode. */
252b5132 6418 else
3e73aa7c 6419 {
062cd5e7
AS		 6420 if (!fixp->fx_pcrel)
6421 rel->addend = fixp->fx_offset;
6422 else
6423 switch (code)
6424 {
6425 case BFD_RELOC_X86_64_PLT32:
6426 case BFD_RELOC_X86_64_GOT32:
6427 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 6428 case BFD_RELOC_X86_64_TLSGD:
6429 case BFD_RELOC_X86_64_TLSLD:
6430 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 6431 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6432 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 6433 rel->addend = fixp->fx_offset - fixp->fx_size;
6434 break;
6435 default:
6436 rel->addend = (section->vma
6437 - fixp->fx_size
6438 + fixp->fx_addnumber
6439 + md_pcrel_from (fixp));
6440 break;
6441 }
3e73aa7c
JH		 6442 }
6443
252b5132
RH		 6444 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6445 if (rel->howto == NULL)
6446 {
6447 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 6448 _("cannot represent relocation type %s"),
252b5132
RH		 6449 bfd_get_reloc_code_name (code));
6450 /* Set howto to a garbage value so that we can keep going. */
6451 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6452 assert (rel->howto != NULL);
6453 }
6454
6455 return rel;
6456}
6457
64a0c779
DN		 6458\f
6459/* Parse operands using Intel syntax. This implements a recursive descent
6460 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6461 Programmer's Guide.
6462
6463 FIXME: We do not recognize the full operand grammar defined in the MASM
6464 documentation. In particular, all the structure/union and
6465 high-level macro operands are missing.
6466
6467 Uppercase words are terminals, lower case words are non-terminals.
6468 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6469 bars '|' denote choices. Most grammar productions are implemented in
6470 functions called 'intel_<production>'.
6471
6472 Initial production is 'expr'.
6473
9306ca4a 6474 addOp + | -
64a0c779
DN		 6475
6476 alpha [a-zA-Z]
6477
9306ca4a
JB		 6478 binOp & | AND | \| | OR | ^ | XOR
6479
64a0c779
DN		 6480 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6481
6482 constant digits [[ radixOverride ]]
6483
9306ca4a 6484 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 6485
6486 digits decdigit
b77a7acd
AJ		 6487 | digits decdigit
6488 | digits hexdigit
64a0c779
DN		 6489
6490 decdigit [0-9]
6491
9306ca4a
JB		 6492 e04 e04 addOp e05
6493 | e05
6494
6495 e05 e05 binOp e06
b77a7acd 6496 | e06
64a0c779
DN		 6497
6498 e06 e06 mulOp e09
b77a7acd 6499 | e09
64a0c779
DN		 6500
6501 e09 OFFSET e10
a724f0f4
JB		 6502 | SHORT e10
6503 | + e10
6504 | - e10
9306ca4a
JB		 6505 | ~ e10
6506 | NOT e10
64a0c779
DN		 6507 | e09 PTR e10
6508 | e09 : e10
6509 | e10
6510
6511 e10 e10 [ expr ]
b77a7acd 6512 | e11
64a0c779
DN		 6513
6514 e11 ( expr )
b77a7acd 6515 | [ expr ]
64a0c779
DN		 6516 | constant
6517 | dataType
6518 | id
6519 | $
6520 | register
6521
a724f0f4 6522 => expr expr cmpOp e04
9306ca4a 6523 | e04
64a0c779
DN		 6524
6525 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 6526 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 6527
6528 hexdigit a | b | c | d | e | f
b77a7acd 6529 | A | B | C | D | E | F
64a0c779
DN		 6530
6531 id alpha
b77a7acd 6532 | id alpha
64a0c779
DN		 6533 | id decdigit
6534
9306ca4a 6535 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 6536
6537 quote " | '
6538
6539 register specialRegister
b77a7acd 6540 | gpRegister
64a0c779
DN		 6541 | byteRegister
6542
6543 segmentRegister CS | DS | ES | FS | GS | SS
6544
9306ca4a 6545 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 6546 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 6547 | TR3 | TR4 | TR5 | TR6 | TR7
6548
64a0c779
DN		 6549 We simplify the grammar in obvious places (e.g., register parsing is
6550 done by calling parse_register) and eliminate immediate left recursion
6551 to implement a recursive-descent parser.
6552
a724f0f4
JB		 6553 expr e04 expr'
6554
6555 expr' cmpOp e04 expr'
6556 | Empty
9306ca4a
JB		 6557
6558 e04 e05 e04'
6559
6560 e04' addOp e05 e04'
6561 | Empty
64a0c779
DN		 6562
6563 e05 e06 e05'
6564
9306ca4a 6565 e05' binOp e06 e05'
b77a7acd 6566 | Empty
64a0c779
DN		 6567
6568 e06 e09 e06'
6569
6570 e06' mulOp e09 e06'
b77a7acd 6571 | Empty
64a0c779
DN		 6572
6573 e09 OFFSET e10 e09'
a724f0f4
JB		 6574 | SHORT e10'
6575 | + e10'
6576 | - e10'
6577 | ~ e10'
6578 | NOT e10'
b77a7acd 6579 | e10 e09'
64a0c779
DN		 6580
6581 e09' PTR e10 e09'
b77a7acd 6582 | : e10 e09'
64a0c779
DN		 6583 | Empty
6584
6585 e10 e11 e10'
6586
6587 e10' [ expr ] e10'
b77a7acd 6588 | Empty
64a0c779
DN		 6589
6590 e11 ( expr )
b77a7acd 6591 | [ expr ]
64a0c779
DN		 6592 | BYTE
6593 | WORD
6594 | DWORD
9306ca4a 6595 | FWORD
64a0c779 6596 | QWORD
9306ca4a
JB		 6597 | TBYTE
6598 | OWORD
6599 | XMMWORD
64a0c779
DN		 6600 | .
6601 | $
6602 | register
6603 | id
6604 | constant */
6605
6606/* Parsing structure for the intel syntax parser. Used to implement the
6607 semantic actions for the operand grammar. */
6608struct intel_parser_s
6609 {
6610 char *op_string; /* The string being parsed. */
6611 int got_a_float; /* Whether the operand is a float. */
4a1805b1 6612 int op_modifier; /* Operand modifier. */
64a0c779 6613 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 6614 int in_offset; /* >=1 if parsing operand of offset. */
6615 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 6616 const reg_entry *reg; /* Last register reference found. */
6617 char *disp; /* Displacement string being built. */
a724f0f4 6618 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 6619 };
6620
6621static struct intel_parser_s intel_parser;
6622
6623/* Token structure for parsing intel syntax. */
6624struct intel_token
6625 {
6626 int code; /* Token code. */
6627 const reg_entry *reg; /* Register entry for register tokens. */
6628 char *str; /* String representation. */
6629 };
6630
6631static struct intel_token cur_token, prev_token;
6632
50705ef4
AM		 6633/* Token codes for the intel parser. Since T_SHORT is already used
6634 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 6635#define T_NIL -1
6636#define T_CONST 1
6637#define T_REG 2
6638#define T_BYTE 3
6639#define T_WORD 4
9306ca4a
JB		 6640#define T_DWORD 5
6641#define T_FWORD 6
6642#define T_QWORD 7
6643#define T_TBYTE 8
6644#define T_XMMWORD 9
50705ef4 6645#undef T_SHORT
9306ca4a
JB		 6646#define T_SHORT 10
6647#define T_OFFSET 11
6648#define T_PTR 12
6649#define T_ID 13
6650#define T_SHL 14
6651#define T_SHR 15
64a0c779
DN		 6652
6653/* Prototypes for intel parser functions. */
e3bb37b5
L		 6654static int intel_match_token (int);
6655static void intel_putback_token (void);
6656static void intel_get_token (void);
6657static int intel_expr (void);
6658static int intel_e04 (void);
6659static int intel_e05 (void);
6660static int intel_e06 (void);
6661static int intel_e09 (void);
6662static int intel_e10 (void);
6663static int intel_e11 (void);
64a0c779 6664
64a0c779 6665static int
e3bb37b5 6666i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 6667{
6668 int ret;
6669 char *p;
6670
a724f0f4
JB		 6671 p = intel_parser.op_string = xstrdup (operand_string);
6672 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6673
6674 for (;;)
64a0c779 6675 {
a724f0f4
JB		 6676 /* Initialize token holders. */
6677 cur_token.code = prev_token.code = T_NIL;
6678 cur_token.reg = prev_token.reg = NULL;
6679 cur_token.str = prev_token.str = NULL;
6680
6681 /* Initialize parser structure. */
6682 intel_parser.got_a_float = got_a_float;
6683 intel_parser.op_modifier = 0;
6684 intel_parser.is_mem = 0;
6685 intel_parser.in_offset = 0;
6686 intel_parser.in_bracket = 0;
6687 intel_parser.reg = NULL;
6688 intel_parser.disp[0] = '\0';
6689 intel_parser.next_operand = NULL;
6690
6691 /* Read the first token and start the parser. */
6692 intel_get_token ();
6693 ret = intel_expr ();
6694
6695 if (!ret)
6696 break;
6697
9306ca4a
JB		 6698 if (cur_token.code != T_NIL)
6699 {
6700 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6701 current_templates->start->name, cur_token.str);
6702 ret = 0;
6703 }
64a0c779
DN		 6704 /* If we found a memory reference, hand it over to i386_displacement
6705 to fill in the rest of the operand fields. */
9306ca4a 6706 else if (intel_parser.is_mem)
64a0c779
DN		 6707 {
6708 if ((i.mem_operands == 1
6709 && (current_templates->start->opcode_modifier & IsString) == 0)
6710 || i.mem_operands == 2)
6711 {
6712 as_bad (_("too many memory references for '%s'"),
6713 current_templates->start->name);
6714 ret = 0;
6715 }
6716 else
6717 {
6718 char *s = intel_parser.disp;
6719 i.mem_operands++;
6720
a724f0f4
JB		 6721 if (!quiet_warnings && intel_parser.is_mem < 0)
6722 /* See the comments in intel_bracket_expr. */
6723 as_warn (_("Treating `%s' as memory reference"), operand_string);
6724
64a0c779
DN		 6725 /* Add the displacement expression. */
6726 if (*s != '\0')
a4622f40
AM		 6727 ret = i386_displacement (s, s + strlen (s));
6728 if (ret)
a724f0f4
JB		 6729 {
6730 /* Swap base and index in 16-bit memory operands like
6731 [si+bx]. Since i386_index_check is also used in AT&T
6732 mode we have to do that here. */
6733 if (i.base_reg
6734 && i.index_reg
6735 && (i.base_reg->reg_type & Reg16)
6736 && (i.index_reg->reg_type & Reg16)
6737 && i.base_reg->reg_num >= 6
6738 && i.index_reg->reg_num < 6)
6739 {
6740 const reg_entry *base = i.index_reg;
6741
6742 i.index_reg = i.base_reg;
6743 i.base_reg = base;
6744 }
6745 ret = i386_index_check (operand_string);
6746 }
64a0c779
DN		 6747 }
6748 }
6749
6750 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 6751 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 6752 || intel_parser.reg == NULL)
6753 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 6754
6755 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 6756 ret = 0;
a724f0f4
JB		 6757 if (!ret || !intel_parser.next_operand)
6758 break;
6759 intel_parser.op_string = intel_parser.next_operand;
6760 this_operand = i.operands++;
64a0c779
DN		 6761 }
6762
6763 free (p);
6764 free (intel_parser.disp);
6765
6766 return ret;
6767}
6768
a724f0f4
JB		 6769#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6770
6771/* expr e04 expr'
6772
6773 expr' cmpOp e04 expr'
6774 | Empty */
64a0c779 6775static int
e3bb37b5 6776intel_expr (void)
64a0c779 6777{
a724f0f4
JB		 6778 /* XXX Implement the comparison operators. */
6779 return intel_e04 ();
9306ca4a
JB		 6780}
6781
a724f0f4 6782/* e04 e05 e04'
9306ca4a 6783
a724f0f4 6784 e04' addOp e05 e04'
9306ca4a
JB		 6785 | Empty */
6786static int
e3bb37b5 6787intel_e04 (void)
9306ca4a 6788{
a724f0f4 6789 int nregs = -1;
9306ca4a 6790
a724f0f4 6791 for (;;)
9306ca4a 6792 {
a724f0f4
JB		 6793 if (!intel_e05())
6794 return 0;
9306ca4a 6795
a724f0f4
JB		 6796 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6797 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 6798
a724f0f4
JB		 6799 if (cur_token.code == '+')
6800 nregs = -1;
6801 else if (cur_token.code == '-')
6802 nregs = NUM_ADDRESS_REGS;
6803 else
6804 return 1;
64a0c779 6805
a724f0f4
JB		 6806 strcat (intel_parser.disp, cur_token.str);
6807 intel_match_token (cur_token.code);
6808 }
64a0c779
DN		 6809}
6810
64a0c779
DN		 6811/* e05 e06 e05'
6812
9306ca4a 6813 e05' binOp e06 e05'
64a0c779
DN		 6814 | Empty */
6815static int
e3bb37b5 6816intel_e05 (void)
64a0c779 6817{
a724f0f4 6818 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6819
a724f0f4 6820 for (;;)
64a0c779 6821 {
a724f0f4
JB		 6822 if (!intel_e06())
6823 return 0;
6824
4eed87de
AM		 6825 if (cur_token.code == '&'
6826 || cur_token.code == '|'
6827 || cur_token.code == '^')
a724f0f4
JB		 6828 {
6829 char str[2];
6830
6831 str[0] = cur_token.code;
6832 str[1] = 0;
6833 strcat (intel_parser.disp, str);
6834 }
6835 else
6836 break;
9306ca4a 6837
64a0c779
DN		 6838 intel_match_token (cur_token.code);
6839
a724f0f4
JB		 6840 if (nregs < 0)
6841 nregs = ~nregs;
64a0c779 6842 }
a724f0f4
JB		 6843 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6844 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6845 return 1;
4a1805b1 6846}
64a0c779
DN		 6847
6848/* e06 e09 e06'
6849
6850 e06' mulOp e09 e06'
b77a7acd 6851 | Empty */
64a0c779 6852static int
e3bb37b5 6853intel_e06 (void)
64a0c779 6854{
a724f0f4 6855 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6856
a724f0f4 6857 for (;;)
64a0c779 6858 {
a724f0f4
JB		 6859 if (!intel_e09())
6860 return 0;
9306ca4a 6861
4eed87de
AM		 6862 if (cur_token.code == '*'
6863 || cur_token.code == '/'
6864 || cur_token.code == '%')
a724f0f4
JB		 6865 {
6866 char str[2];
9306ca4a 6867
a724f0f4
JB		 6868 str[0] = cur_token.code;
6869 str[1] = 0;
6870 strcat (intel_parser.disp, str);
6871 }
6872 else if (cur_token.code == T_SHL)
6873 strcat (intel_parser.disp, "<<");
6874 else if (cur_token.code == T_SHR)
6875 strcat (intel_parser.disp, ">>");
6876 else
6877 break;
9306ca4a 6878
64e74474 6879 intel_match_token (cur_token.code);
64a0c779 6880
a724f0f4
JB		 6881 if (nregs < 0)
6882 nregs = ~nregs;
64a0c779 6883 }
a724f0f4
JB		 6884 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6885 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6886 return 1;
64a0c779
DN		 6887}
6888
a724f0f4
JB		 6889/* e09 OFFSET e09
6890 | SHORT e09
6891 | + e09
6892 | - e09
6893 | ~ e09
6894 | NOT e09
9306ca4a
JB		 6895 | e10 e09'
6896
64a0c779 6897 e09' PTR e10 e09'
b77a7acd 6898 | : e10 e09'
64a0c779
DN		 6899 | Empty */
6900static int
e3bb37b5 6901intel_e09 (void)
64a0c779 6902{
a724f0f4
JB		 6903 int nregs = ~NUM_ADDRESS_REGS;
6904 int in_offset = 0;
6905
6906 for (;;)
64a0c779 6907 {
a724f0f4
JB		 6908 /* Don't consume constants here. */
6909 if (cur_token.code == '+' || cur_token.code == '-')
6910 {
6911 /* Need to look one token ahead - if the next token
6912 is a constant, the current token is its sign. */
6913 int next_code;
6914
6915 intel_match_token (cur_token.code);
6916 next_code = cur_token.code;
6917 intel_putback_token ();
6918 if (next_code == T_CONST)
6919 break;
6920 }
6921
6922 /* e09 OFFSET e09 */
6923 if (cur_token.code == T_OFFSET)
6924 {
6925 if (!in_offset++)
6926 ++intel_parser.in_offset;
6927 }
6928
6929 /* e09 SHORT e09 */
6930 else if (cur_token.code == T_SHORT)
6931 intel_parser.op_modifier |= 1 << T_SHORT;
6932
6933 /* e09 + e09 */
6934 else if (cur_token.code == '+')
6935 strcat (intel_parser.disp, "+");
6936
6937 /* e09 - e09
6938 | ~ e09
6939 | NOT e09 */
6940 else if (cur_token.code == '-' || cur_token.code == '~')
6941 {
6942 char str[2];
64a0c779 6943
a724f0f4
JB		 6944 if (nregs < 0)
6945 nregs = ~nregs;
6946 str[0] = cur_token.code;
6947 str[1] = 0;
6948 strcat (intel_parser.disp, str);
6949 }
6950
6951 /* e09 e10 e09' */
6952 else
6953 break;
6954
6955 intel_match_token (cur_token.code);
64a0c779
DN		 6956 }
6957
a724f0f4 6958 for (;;)
9306ca4a 6959 {
a724f0f4
JB		 6960 if (!intel_e10 ())
6961 return 0;
9306ca4a 6962
a724f0f4
JB		 6963 /* e09' PTR e10 e09' */
6964 if (cur_token.code == T_PTR)
6965 {
6966 char suffix;
9306ca4a 6967
a724f0f4
JB		 6968 if (prev_token.code == T_BYTE)
6969 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 6970
a724f0f4
JB		 6971 else if (prev_token.code == T_WORD)
6972 {
6973 if (current_templates->start->name[0] == 'l'
6974 && current_templates->start->name[2] == 's'
6975 && current_templates->start->name[3] == 0)
6976 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6977 else if (intel_parser.got_a_float == 2) /* "fi..." */
6978 suffix = SHORT_MNEM_SUFFIX;
6979 else
6980 suffix = WORD_MNEM_SUFFIX;
6981 }
64a0c779 6982
a724f0f4
JB		 6983 else if (prev_token.code == T_DWORD)
6984 {
6985 if (current_templates->start->name[0] == 'l'
6986 && current_templates->start->name[2] == 's'
6987 && current_templates->start->name[3] == 0)
6988 suffix = WORD_MNEM_SUFFIX;
6989 else if (flag_code == CODE_16BIT
6990 && (current_templates->start->opcode_modifier
435acd52 6991 & (Jump | JumpDword)))
a724f0f4
JB		 6992 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6993 else if (intel_parser.got_a_float == 1) /* "f..." */
6994 suffix = SHORT_MNEM_SUFFIX;
6995 else
6996 suffix = LONG_MNEM_SUFFIX;
6997 }
9306ca4a 6998
a724f0f4
JB		 6999 else if (prev_token.code == T_FWORD)
7000 {
7001 if (current_templates->start->name[0] == 'l'
7002 && current_templates->start->name[2] == 's'
7003 && current_templates->start->name[3] == 0)
7004 suffix = LONG_MNEM_SUFFIX;
7005 else if (!intel_parser.got_a_float)
7006 {
7007 if (flag_code == CODE_16BIT)
7008 add_prefix (DATA_PREFIX_OPCODE);
7009 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7010 }
7011 else
7012 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7013 }
64a0c779 7014
a724f0f4
JB		 7015 else if (prev_token.code == T_QWORD)
7016 {
7017 if (intel_parser.got_a_float == 1) /* "f..." */
7018 suffix = LONG_MNEM_SUFFIX;
7019 else
7020 suffix = QWORD_MNEM_SUFFIX;
7021 }
64a0c779 7022
a724f0f4
JB		 7023 else if (prev_token.code == T_TBYTE)
7024 {
7025 if (intel_parser.got_a_float == 1)
7026 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7027 else
7028 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7029 }
9306ca4a 7030
a724f0f4 7031 else if (prev_token.code == T_XMMWORD)
9306ca4a 7032 {
a724f0f4
JB		 7033 /* XXX ignored for now, but accepted since gcc uses it */
7034 suffix = 0;
9306ca4a 7035 }
64a0c779 7036
f16b83df 7037 else
a724f0f4
JB		 7038 {
7039 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
7040 return 0;
7041 }
7042
435acd52
JB		 7043 /* Operands for jump/call using 'ptr' notation denote absolute
7044 addresses. */
7045 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7046 i.types[this_operand] |= JumpAbsolute;
7047
a724f0f4
JB		 7048 if (current_templates->start->base_opcode == 0x8d /* lea */)
7049 ;
7050 else if (!i.suffix)
7051 i.suffix = suffix;
7052 else if (i.suffix != suffix)
7053 {
7054 as_bad (_("Conflicting operand modifiers"));
7055 return 0;
7056 }
64a0c779 7057
9306ca4a
JB		 7058 }
7059
a724f0f4
JB		 7060 /* e09' : e10 e09' */
7061 else if (cur_token.code == ':')
9306ca4a 7062 {
a724f0f4
JB		 7063 if (prev_token.code != T_REG)
7064 {
7065 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7066 segment/group identifier (which we don't have), using comma
7067 as the operand separator there is even less consistent, since
7068 there all branches only have a single operand. */
7069 if (this_operand != 0
7070 || intel_parser.in_offset
7071 || intel_parser.in_bracket
7072 || (!(current_templates->start->opcode_modifier
7073 & (Jump|JumpDword|JumpInterSegment))
7074 && !(current_templates->start->operand_types[0]
7075 & JumpAbsolute)))
7076 return intel_match_token (T_NIL);
7077 /* Remember the start of the 2nd operand and terminate 1st
7078 operand here.
7079 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7080 another expression), but it gets at least the simplest case
7081 (a plain number or symbol on the left side) right. */
7082 intel_parser.next_operand = intel_parser.op_string;
7083 *--intel_parser.op_string = '\0';
7084 return intel_match_token (':');
7085 }
9306ca4a 7086 }
64a0c779 7087
a724f0f4 7088 /* e09' Empty */
64a0c779 7089 else
a724f0f4 7090 break;
64a0c779 7091
a724f0f4
JB		 7092 intel_match_token (cur_token.code);
7093
7094 }
7095
7096 if (in_offset)
7097 {
7098 --intel_parser.in_offset;
7099 if (nregs < 0)
7100 nregs = ~nregs;
7101 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 7102 {
a724f0f4 7103 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 7104 return 0;
7105 }
a724f0f4
JB		 7106 intel_parser.op_modifier |= 1 << T_OFFSET;
7107 }
9306ca4a 7108
a724f0f4
JB		 7109 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7110 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
7111 return 1;
7112}
64a0c779 7113
a724f0f4 7114static int
e3bb37b5 7115intel_bracket_expr (void)
a724f0f4
JB		 7116{
7117 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
7118 const char *start = intel_parser.op_string;
7119 int len;
7120
7121 if (i.op[this_operand].regs)
7122 return intel_match_token (T_NIL);
7123
7124 intel_match_token ('[');
7125
7126 /* Mark as a memory operand only if it's not already known to be an
7127 offset expression. If it's an offset expression, we need to keep
7128 the brace in. */
7129 if (!intel_parser.in_offset)
7130 {
7131 ++intel_parser.in_bracket;
435acd52
JB		 7132
7133 /* Operands for jump/call inside brackets denote absolute addresses. */
7134 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7135 i.types[this_operand] |= JumpAbsolute;
7136
a724f0f4
JB		 7137 /* Unfortunately gas always diverged from MASM in a respect that can't
7138 be easily fixed without risking to break code sequences likely to be
7139 encountered (the testsuite even check for this): MASM doesn't consider
7140 an expression inside brackets unconditionally as a memory reference.
7141 When that is e.g. a constant, an offset expression, or the sum of the
7142 two, this is still taken as a constant load. gas, however, always
7143 treated these as memory references. As a compromise, we'll try to make
7144 offset expressions inside brackets work the MASM way (since that's
7145 less likely to be found in real world code), but make constants alone
7146 continue to work the traditional gas way. In either case, issue a
7147 warning. */
7148 intel_parser.op_modifier &= ~was_offset;
64a0c779 7149 }
a724f0f4 7150 else
64e74474 7151 strcat (intel_parser.disp, "[");
a724f0f4
JB		 7152
7153 /* Add a '+' to the displacement string if necessary. */
7154 if (*intel_parser.disp != '\0'
7155 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7156 strcat (intel_parser.disp, "+");
64a0c779 7157
a724f0f4
JB		 7158 if (intel_expr ()
7159 && (len = intel_parser.op_string - start - 1,
7160 intel_match_token (']')))
64a0c779 7161 {
a724f0f4
JB		 7162 /* Preserve brackets when the operand is an offset expression. */
7163 if (intel_parser.in_offset)
7164 strcat (intel_parser.disp, "]");
7165 else
7166 {
7167 --intel_parser.in_bracket;
7168 if (i.base_reg || i.index_reg)
7169 intel_parser.is_mem = 1;
7170 if (!intel_parser.is_mem)
7171 {
7172 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7173 /* Defer the warning until all of the operand was parsed. */
7174 intel_parser.is_mem = -1;
7175 else if (!quiet_warnings)
4eed87de
AM		 7176 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
7177 len, start, len, start);
a724f0f4
JB		 7178 }
7179 }
7180 intel_parser.op_modifier |= was_offset;
64a0c779 7181
a724f0f4 7182 return 1;
64a0c779 7183 }
a724f0f4 7184 return 0;
64a0c779
DN		 7185}
7186
7187/* e10 e11 e10'
7188
7189 e10' [ expr ] e10'
b77a7acd 7190 | Empty */
64a0c779 7191static int
e3bb37b5 7192intel_e10 (void)
64a0c779 7193{
a724f0f4
JB		 7194 if (!intel_e11 ())
7195 return 0;
64a0c779 7196
a724f0f4 7197 while (cur_token.code == '[')
64a0c779 7198 {
a724f0f4 7199 if (!intel_bracket_expr ())
21d6c4af 7200 return 0;
64a0c779
DN		 7201 }
7202
a724f0f4 7203 return 1;
64a0c779
DN		 7204}
7205
64a0c779 7206/* e11 ( expr )
b77a7acd 7207 | [ expr ]
64a0c779
DN		 7208 | BYTE
7209 | WORD
7210 | DWORD
9306ca4a 7211 | FWORD
64a0c779 7212 | QWORD
9306ca4a
JB		 7213 | TBYTE
7214 | OWORD
7215 | XMMWORD
4a1805b1 7216 | $
64a0c779
DN		 7217 | .
7218 | register
7219 | id
7220 | constant */
7221static int
e3bb37b5 7222intel_e11 (void)
64a0c779 7223{
a724f0f4 7224 switch (cur_token.code)
64a0c779 7225 {
a724f0f4
JB		 7226 /* e11 ( expr ) */
7227 case '(':
64a0c779
DN		 7228 intel_match_token ('(');
7229 strcat (intel_parser.disp, "(");
7230
7231 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 7232 {
7233 strcat (intel_parser.disp, ")");
7234 return 1;
7235 }
a724f0f4 7236 return 0;
4a1805b1 7237
a724f0f4
JB		 7238 /* e11 [ expr ] */
7239 case '[':
a724f0f4 7240 return intel_bracket_expr ();
64a0c779 7241
a724f0f4
JB		 7242 /* e11 $
7243 | . */
7244 case '.':
64a0c779
DN		 7245 strcat (intel_parser.disp, cur_token.str);
7246 intel_match_token (cur_token.code);
21d6c4af
DN		 7247
7248 /* Mark as a memory operand only if it's not already known to be an
7249 offset expression. */
a724f0f4 7250 if (!intel_parser.in_offset)
21d6c4af 7251 intel_parser.is_mem = 1;
64a0c779
DN		 7252
7253 return 1;
64a0c779 7254
a724f0f4
JB		 7255 /* e11 register */
7256 case T_REG:
7257 {
7258 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 7259
a724f0f4 7260 intel_match_token (T_REG);
64a0c779 7261
a724f0f4
JB		 7262 /* Check for segment change. */
7263 if (cur_token.code == ':')
7264 {
7265 if (!(reg->reg_type & (SReg2 | SReg3)))
7266 {
4eed87de
AM		 7267 as_bad (_("`%s' is not a valid segment register"),
7268 reg->reg_name);
a724f0f4
JB		 7269 return 0;
7270 }
7271 else if (i.seg[i.mem_operands])
7272 as_warn (_("Extra segment override ignored"));
7273 else
7274 {
7275 if (!intel_parser.in_offset)
7276 intel_parser.is_mem = 1;
7277 switch (reg->reg_num)
7278 {
7279 case 0:
7280 i.seg[i.mem_operands] = &es;
7281 break;
7282 case 1:
7283 i.seg[i.mem_operands] = &cs;
7284 break;
7285 case 2:
7286 i.seg[i.mem_operands] = &ss;
7287 break;
7288 case 3:
7289 i.seg[i.mem_operands] = &ds;
7290 break;
7291 case 4:
7292 i.seg[i.mem_operands] = &fs;
7293 break;
7294 case 5:
7295 i.seg[i.mem_operands] = &gs;
7296 break;
7297 }
7298 }
7299 }
64a0c779 7300
a724f0f4
JB		 7301 /* Not a segment register. Check for register scaling. */
7302 else if (cur_token.code == '*')
7303 {
7304 if (!intel_parser.in_bracket)
7305 {
7306 as_bad (_("Register scaling only allowed in memory operands"));
7307 return 0;
7308 }
64a0c779 7309
a724f0f4
JB		 7310 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7311 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7312 else if (i.index_reg)
7313 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 7314
a724f0f4
JB		 7315 /* What follows must be a valid scale. */
7316 intel_match_token ('*');
7317 i.index_reg = reg;
7318 i.types[this_operand] |= BaseIndex;
64a0c779 7319
a724f0f4
JB		 7320 /* Set the scale after setting the register (otherwise,
7321 i386_scale will complain) */
7322 if (cur_token.code == '+' || cur_token.code == '-')
7323 {
7324 char *str, sign = cur_token.code;
7325 intel_match_token (cur_token.code);
7326 if (cur_token.code != T_CONST)
7327 {
7328 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7329 cur_token.str);
7330 return 0;
7331 }
7332 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7333 strcpy (str + 1, cur_token.str);
7334 *str = sign;
7335 if (!i386_scale (str))
7336 return 0;
7337 free (str);
7338 }
7339 else if (!i386_scale (cur_token.str))
64a0c779 7340 return 0;
a724f0f4
JB		 7341 intel_match_token (cur_token.code);
7342 }
64a0c779 7343
a724f0f4
JB		 7344 /* No scaling. If this is a memory operand, the register is either a
7345 base register (first occurrence) or an index register (second
7346 occurrence). */
7b0441f6 7347 else if (intel_parser.in_bracket)
a724f0f4 7348 {
64a0c779 7349
a724f0f4
JB		 7350 if (!i.base_reg)
7351 i.base_reg = reg;
7352 else if (!i.index_reg)
7353 i.index_reg = reg;
7354 else
7355 {
7356 as_bad (_("Too many register references in memory operand"));
7357 return 0;
7358 }
64a0c779 7359
a724f0f4
JB		 7360 i.types[this_operand] |= BaseIndex;
7361 }
4a1805b1 7362
4d1bb795
JB		 7363 /* It's neither base nor index. */
7364 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4
JB		 7365 {
7366 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7367 i.op[this_operand].regs = reg;
7368 i.reg_operands++;
7369 }
7370 else
7371 {
7372 as_bad (_("Invalid use of register"));
7373 return 0;
7374 }
64a0c779 7375
a724f0f4
JB		 7376 /* Since registers are not part of the displacement string (except
7377 when we're parsing offset operands), we may need to remove any
7378 preceding '+' from the displacement string. */
7379 if (*intel_parser.disp != '\0'
7380 && !intel_parser.in_offset)
7381 {
7382 char *s = intel_parser.disp;
7383 s += strlen (s) - 1;
7384 if (*s == '+')
7385 *s = '\0';
7386 }
4a1805b1 7387
a724f0f4
JB		 7388 return 1;
7389 }
7390
7391 /* e11 BYTE
7392 | WORD
7393 | DWORD
7394 | FWORD
7395 | QWORD
7396 | TBYTE
7397 | OWORD
7398 | XMMWORD */
7399 case T_BYTE:
7400 case T_WORD:
7401 case T_DWORD:
7402 case T_FWORD:
7403 case T_QWORD:
7404 case T_TBYTE:
7405 case T_XMMWORD:
7406 intel_match_token (cur_token.code);
64a0c779 7407
a724f0f4
JB		 7408 if (cur_token.code == T_PTR)
7409 return 1;
7410
7411 /* It must have been an identifier. */
7412 intel_putback_token ();
7413 cur_token.code = T_ID;
7414 /* FALLTHRU */
7415
7416 /* e11 id
7417 | constant */
7418 case T_ID:
7419 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 7420 {
7421 symbolS *symbolP;
7422
a724f0f4
JB		 7423 /* The identifier represents a memory reference only if it's not
7424 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 7425 symbolP = symbol_find(cur_token.str);
7426 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7427 intel_parser.is_mem = 1;
7428 }
a724f0f4 7429 /* FALLTHRU */
64a0c779 7430
a724f0f4
JB		 7431 case T_CONST:
7432 case '-':
7433 case '+':
7434 {
7435 char *save_str, sign = 0;
64a0c779 7436
a724f0f4
JB		 7437 /* Allow constants that start with `+' or `-'. */
7438 if (cur_token.code == '-' || cur_token.code == '+')
7439 {
7440 sign = cur_token.code;
7441 intel_match_token (cur_token.code);
7442 if (cur_token.code != T_CONST)
7443 {
7444 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7445 cur_token.str);
7446 return 0;
7447 }
7448 }
64a0c779 7449
a724f0f4
JB		 7450 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7451 strcpy (save_str + !!sign, cur_token.str);
7452 if (sign)
7453 *save_str = sign;
64a0c779 7454
a724f0f4
JB		 7455 /* Get the next token to check for register scaling. */
7456 intel_match_token (cur_token.code);
64a0c779 7457
4eed87de
AM		 7458 /* Check if this constant is a scaling factor for an
7459 index register. */
a724f0f4
JB		 7460 if (cur_token.code == '*')
7461 {
7462 if (intel_match_token ('*') && cur_token.code == T_REG)
7463 {
7464 const reg_entry *reg = cur_token.reg;
7465
7466 if (!intel_parser.in_bracket)
7467 {
4eed87de
AM		 7468 as_bad (_("Register scaling only allowed "
7469 "in memory operands"));
a724f0f4
JB		 7470 return 0;
7471 }
7472
4eed87de
AM		 7473 /* Disallow things like [1*si].
7474 sp and esp are invalid as index. */
7475 if (reg->reg_type & Reg16)
7476 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 7477 else if (i.index_reg)
4eed87de 7478 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 7479
7480 /* The constant is followed by `* reg', so it must be
7481 a valid scale. */
7482 i.index_reg = reg;
7483 i.types[this_operand] |= BaseIndex;
7484
7485 /* Set the scale after setting the register (otherwise,
7486 i386_scale will complain) */
7487 if (!i386_scale (save_str))
64a0c779 7488 return 0;
a724f0f4
JB		 7489 intel_match_token (T_REG);
7490
7491 /* Since registers are not part of the displacement
7492 string, we may need to remove any preceding '+' from
7493 the displacement string. */
7494 if (*intel_parser.disp != '\0')
7495 {
7496 char *s = intel_parser.disp;
7497 s += strlen (s) - 1;
7498 if (*s == '+')
7499 *s = '\0';
7500 }
7501
7502 free (save_str);
7503
7504 return 1;
7505 }
64a0c779 7506
a724f0f4
JB		 7507 /* The constant was not used for register scaling. Since we have
7508 already consumed the token following `*' we now need to put it
7509 back in the stream. */
64a0c779 7510 intel_putback_token ();
a724f0f4 7511 }
64a0c779 7512
a724f0f4
JB		 7513 /* Add the constant to the displacement string. */
7514 strcat (intel_parser.disp, save_str);
7515 free (save_str);
64a0c779 7516
a724f0f4
JB		 7517 return 1;
7518 }
64a0c779
DN		 7519 }
7520
64a0c779
DN		 7521 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7522 return 0;
7523}
7524
64a0c779
DN		 7525/* Match the given token against cur_token. If they match, read the next
7526 token from the operand string. */
7527static int
e3bb37b5 7528intel_match_token (int code)
64a0c779
DN		 7529{
7530 if (cur_token.code == code)
7531 {
7532 intel_get_token ();
7533 return 1;
7534 }
7535 else
7536 {
0477af35 7537 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 7538 return 0;
7539 }
7540}
7541
64a0c779
DN		 7542/* Read a new token from intel_parser.op_string and store it in cur_token. */
7543static void
e3bb37b5 7544intel_get_token (void)
64a0c779
DN		 7545{
7546 char *end_op;
7547 const reg_entry *reg;
7548 struct intel_token new_token;
7549
7550 new_token.code = T_NIL;
7551 new_token.reg = NULL;
7552 new_token.str = NULL;
7553
4a1805b1 7554 /* Free the memory allocated to the previous token and move
64a0c779
DN		 7555 cur_token to prev_token. */
7556 if (prev_token.str)
7557 free (prev_token.str);
7558
7559 prev_token = cur_token;
7560
7561 /* Skip whitespace. */
7562 while (is_space_char (*intel_parser.op_string))
7563 intel_parser.op_string++;
7564
7565 /* Return an empty token if we find nothing else on the line. */
7566 if (*intel_parser.op_string == '\0')
7567 {
7568 cur_token = new_token;
7569 return;
7570 }
7571
7572 /* The new token cannot be larger than the remainder of the operand
7573 string. */
a724f0f4 7574 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 7575 new_token.str[0] = '\0';
7576
7577 if (strchr ("0123456789", *intel_parser.op_string))
7578 {
7579 char *p = new_token.str;
7580 char *q = intel_parser.op_string;
7581 new_token.code = T_CONST;
7582
7583 /* Allow any kind of identifier char to encompass floating point and
7584 hexadecimal numbers. */
7585 while (is_identifier_char (*q))
7586 *p++ = *q++;
7587 *p = '\0';
7588
7589 /* Recognize special symbol names [0-9][bf]. */
7590 if (strlen (intel_parser.op_string) == 2
4a1805b1 7591 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 7592 || intel_parser.op_string[1] == 'f'))
7593 new_token.code = T_ID;
7594 }
7595
4d1bb795 7596 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 7597 {
4d1bb795
JB		 7598 size_t len = end_op - intel_parser.op_string;
7599
64a0c779
DN		 7600 new_token.code = T_REG;
7601 new_token.reg = reg;
7602
4d1bb795
JB		 7603 memcpy (new_token.str, intel_parser.op_string, len);
7604 new_token.str[len] = '\0';
64a0c779
DN		 7605 }
7606
7607 else if (is_identifier_char (*intel_parser.op_string))
7608 {
7609 char *p = new_token.str;
7610 char *q = intel_parser.op_string;
7611
7612 /* A '.' or '$' followed by an identifier char is an identifier.
7613 Otherwise, it's operator '.' followed by an expression. */
7614 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7615 {
9306ca4a
JB		 7616 new_token.code = '.';
7617 new_token.str[0] = '.';
64a0c779
DN		 7618 new_token.str[1] = '\0';
7619 }
7620 else
7621 {
7622 while (is_identifier_char (*q) || *q == '@')
7623 *p++ = *q++;
7624 *p = '\0';
7625
9306ca4a
JB		 7626 if (strcasecmp (new_token.str, "NOT") == 0)
7627 new_token.code = '~';
7628
7629 else if (strcasecmp (new_token.str, "MOD") == 0)
7630 new_token.code = '%';
7631
7632 else if (strcasecmp (new_token.str, "AND") == 0)
7633 new_token.code = '&';
7634
7635 else if (strcasecmp (new_token.str, "OR") == 0)
7636 new_token.code = '|';
7637
7638 else if (strcasecmp (new_token.str, "XOR") == 0)
7639 new_token.code = '^';
7640
7641 else if (strcasecmp (new_token.str, "SHL") == 0)
7642 new_token.code = T_SHL;
7643
7644 else if (strcasecmp (new_token.str, "SHR") == 0)
7645 new_token.code = T_SHR;
7646
7647 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 7648 new_token.code = T_BYTE;
7649
7650 else if (strcasecmp (new_token.str, "WORD") == 0)
7651 new_token.code = T_WORD;
7652
7653 else if (strcasecmp (new_token.str, "DWORD") == 0)
7654 new_token.code = T_DWORD;
7655
9306ca4a
JB		 7656 else if (strcasecmp (new_token.str, "FWORD") == 0)
7657 new_token.code = T_FWORD;
7658
64a0c779
DN		 7659 else if (strcasecmp (new_token.str, "QWORD") == 0)
7660 new_token.code = T_QWORD;
7661
9306ca4a
JB		 7662 else if (strcasecmp (new_token.str, "TBYTE") == 0
7663 /* XXX remove (gcc still uses it) */
7664 || strcasecmp (new_token.str, "XWORD") == 0)
7665 new_token.code = T_TBYTE;
7666
7667 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7668 || strcasecmp (new_token.str, "OWORD") == 0)
7669 new_token.code = T_XMMWORD;
64a0c779
DN		 7670
7671 else if (strcasecmp (new_token.str, "PTR") == 0)
7672 new_token.code = T_PTR;
7673
7674 else if (strcasecmp (new_token.str, "SHORT") == 0)
7675 new_token.code = T_SHORT;
7676
7677 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7678 {
7679 new_token.code = T_OFFSET;
7680
7681 /* ??? This is not mentioned in the MASM grammar but gcc
7682 makes use of it with -mintel-syntax. OFFSET may be
7683 followed by FLAT: */
7684 if (strncasecmp (q, " FLAT:", 6) == 0)
7685 strcat (new_token.str, " FLAT:");
7686 }
7687
7688 /* ??? This is not mentioned in the MASM grammar. */
7689 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 7690 {
7691 new_token.code = T_OFFSET;
7692 if (*q == ':')
7693 strcat (new_token.str, ":");
7694 else
7695 as_bad (_("`:' expected"));
7696 }
64a0c779
DN		 7697
7698 else
7699 new_token.code = T_ID;
7700 }
7701 }
7702
9306ca4a
JB		 7703 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7704 {
7705 new_token.code = *intel_parser.op_string;
7706 new_token.str[0] = *intel_parser.op_string;
7707 new_token.str[1] = '\0';
7708 }
7709
7710 else if (strchr ("<>", *intel_parser.op_string)
7711 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7712 {
7713 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7714 new_token.str[0] = *intel_parser.op_string;
7715 new_token.str[1] = *intel_parser.op_string;
7716 new_token.str[2] = '\0';
7717 }
7718
64a0c779 7719 else
0477af35 7720 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 7721
7722 intel_parser.op_string += strlen (new_token.str);
7723 cur_token = new_token;
7724}
7725
64a0c779
DN		 7726/* Put cur_token back into the token stream and make cur_token point to
7727 prev_token. */
7728static void
e3bb37b5 7729intel_putback_token (void)
64a0c779 7730{
a724f0f4
JB		 7731 if (cur_token.code != T_NIL)
7732 {
7733 intel_parser.op_string -= strlen (cur_token.str);
7734 free (cur_token.str);
7735 }
64a0c779 7736 cur_token = prev_token;
4a1805b1 7737
64a0c779
DN		 7738 /* Forget prev_token. */
7739 prev_token.code = T_NIL;
7740 prev_token.reg = NULL;
7741 prev_token.str = NULL;
7742}
54cfded0 7743
a4447b93 7744int
1df69f4f 7745tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 7746{
7747 unsigned int regnum;
7748 unsigned int regnames_count;
089dfecd 7749 static const char *const regnames_32[] =
54cfded0 7750 {
a4447b93
RH		 7751 "eax", "ecx", "edx", "ebx",
7752 "esp", "ebp", "esi", "edi",
089dfecd
JB		 7753 "eip", "eflags", NULL,
7754 "st0", "st1", "st2", "st3",
7755 "st4", "st5", "st6", "st7",
7756 NULL, NULL,
7757 "xmm0", "xmm1", "xmm2", "xmm3",
7758 "xmm4", "xmm5", "xmm6", "xmm7",
7759 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7760 "mm4", "mm5", "mm6", "mm7",
7761 "fcw", "fsw", "mxcsr",
7762 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7763 "tr", "ldtr"
54cfded0 7764 };
089dfecd 7765 static const char *const regnames_64[] =
54cfded0 7766 {
089dfecd
JB		 7767 "rax", "rdx", "rcx", "rbx",
7768 "rsi", "rdi", "rbp", "rsp",
7769 "r8", "r9", "r10", "r11",
54cfded0 7770 "r12", "r13", "r14", "r15",
089dfecd
JB		 7771 "rip",
7772 "xmm0", "xmm1", "xmm2", "xmm3",
7773 "xmm4", "xmm5", "xmm6", "xmm7",
7774 "xmm8", "xmm9", "xmm10", "xmm11",
7775 "xmm12", "xmm13", "xmm14", "xmm15",
7776 "st0", "st1", "st2", "st3",
7777 "st4", "st5", "st6", "st7",
7778 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7779 "mm4", "mm5", "mm6", "mm7",
7780 "rflags",
7781 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7782 "fs.base", "gs.base", NULL, NULL,
7783 "tr", "ldtr",
7784 "mxcsr", "fcw", "fsw"
54cfded0 7785 };
089dfecd 7786 const char *const *regnames;
54cfded0
AM		 7787
7788 if (flag_code == CODE_64BIT)
7789 {
7790 regnames = regnames_64;
0cea6190 7791 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 7792 }
7793 else
7794 {
7795 regnames = regnames_32;
0cea6190 7796 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 7797 }
7798
7799 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 7800 if (regnames[regnum] != NULL
7801 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 7802 return regnum;
7803
54cfded0
AM		 7804 return -1;
7805}
7806
7807void
7808tc_x86_frame_initial_instructions (void)
7809{
a4447b93
RH		 7810 static unsigned int sp_regno;
7811
7812 if (!sp_regno)
7813 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7814 ? "rsp" : "esp");
7815
7816 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7817 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 7818}
d2b2c203
DJ		 7819
7820int
7821i386_elf_section_type (const char *str, size_t len)
7822{
7823 if (flag_code == CODE_64BIT
7824 && len == sizeof ("unwind") - 1
7825 && strncmp (str, "unwind", 6) == 0)
7826 return SHT_X86_64_UNWIND;
7827
7828 return -1;
7829}
bb41ade5
AM		 7830
7831#ifdef TE_PE
7832void
7833tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7834{
7835 expressionS expr;
7836
7837 expr.X_op = O_secrel;
7838 expr.X_add_symbol = symbol;
7839 expr.X_add_number = 0;
7840 emit_expr (&expr, size);
7841}
7842#endif
3b22753a
L		 7843
7844#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7845/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7846
7847int
7848x86_64_section_letter (int letter, char **ptr_msg)
7849{
7850 if (flag_code == CODE_64BIT)
7851 {
7852 if (letter == 'l')
7853 return SHF_X86_64_LARGE;
7854
7855 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 7856 }
3b22753a 7857 else
64e74474 7858 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 7859 return -1;
7860}
7861
7862int
7863x86_64_section_word (char *str, size_t len)
7864{
8620418b 7865 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 7866 return SHF_X86_64_LARGE;
7867
7868 return -1;
7869}
7870
7871static void
7872handle_large_common (int small ATTRIBUTE_UNUSED)
7873{
7874 if (flag_code != CODE_64BIT)
7875 {
7876 s_comm_internal (0, elf_common_parse);
7877 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7878 }
7879 else
7880 {
7881 static segT lbss_section;
7882 asection *saved_com_section_ptr = elf_com_section_ptr;
7883 asection *saved_bss_section = bss_section;
7884
7885 if (lbss_section == NULL)
7886 {
7887 flagword applicable;
7888 segT seg = now_seg;
7889 subsegT subseg = now_subseg;
7890
7891 /* The .lbss section is for local .largecomm symbols. */
7892 lbss_section = subseg_new (".lbss", 0);
7893 applicable = bfd_applicable_section_flags (stdoutput);
7894 bfd_set_section_flags (stdoutput, lbss_section,
7895 applicable & SEC_ALLOC);
7896 seg_info (lbss_section)->bss = 1;
7897
7898 subseg_set (seg, subseg);
7899 }
7900
7901 elf_com_section_ptr = &_bfd_elf_large_com_section;
7902 bss_section = lbss_section;
7903
7904 s_comm_internal (0, elf_common_parse);
7905
7906 elf_com_section_ptr = saved_com_section_ptr;
7907 bss_section = saved_bss_section;
7908 }
7909}
7910#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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