projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
*** empty log message ***
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
5dd15031 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 LOCKREP_PREFIX. */
63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
67#define LOCKREP_PREFIX 4
68#define REX_PREFIX 5 /* must come last. */
69#define MAX_PREFIXES 6 /* max prefixes per opcode */
70
71/* we define the syntax here (modulo base,index,scale syntax) */
72#define REGISTER_PREFIX '%'
73#define IMMEDIATE_PREFIX '$'
74#define ABSOLUTE_PREFIX '*'
75
76/* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78#define WORD_MNEM_SUFFIX 'w'
79#define BYTE_MNEM_SUFFIX 'b'
80#define SHORT_MNEM_SUFFIX 's'
81#define LONG_MNEM_SUFFIX 'l'
82#define QWORD_MNEM_SUFFIX 'q'
83#define XMMWORD_MNEM_SUFFIX 'x'
84/* Intel Syntax. Use a non-ascii letter since since it never appears
85 in instructions. */
86#define LONG_DOUBLE_MNEM_SUFFIX '\1'
87
88#define END_OF_INSN '\0'
89
90/*
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
95 END.
96 */
97typedef struct
98{
99 const template *start;
100 const template *end;
101}
102templates;
103
104/* 386 operand encoding bytes: see 386 book for details of this. */
105typedef struct
106{
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
110}
111modrm_byte;
112
113/* x86-64 extension prefix. */
114typedef int rex_byte;
115
116/* The SSE5 instructions have a two bit instruction modifier (OC) that
117 is stored in two separate bytes in the instruction. Pick apart OC
118 into the 2 separate bits for instruction. */
119#define DREX_OC0(x) (((x) & 1) != 0)
120#define DREX_OC1(x) (((x) & 2) != 0)
121
122#define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
123#define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
124
125/* OC mappings */
126#define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
127#define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
128#define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
129#define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
130
131#define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
132#define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
133
134/* Information needed to create the DREX byte in SSE5 instructions. */
135typedef struct
136{
137 unsigned int reg; /* register */
138 unsigned int rex; /* REX flags */
139 unsigned int modrm_reg; /* which arg goes in the modrm.reg field */
140 unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */
141} drex_byte;
142
143/* 386 opcode byte to code indirect addressing. */
144typedef struct
145{
146 unsigned base;
147 unsigned index;
148 unsigned scale;
149}
150sib_byte;
151
152enum processor_type
153{
154 PROCESSOR_UNKNOWN,
155 PROCESSOR_I386,
156 PROCESSOR_I486,
157 PROCESSOR_PENTIUM,
158 PROCESSOR_PENTIUMPRO,
159 PROCESSOR_PENTIUM4,
160 PROCESSOR_NOCONA,
161 PROCESSOR_CORE,
162 PROCESSOR_CORE2,
163 PROCESSOR_K6,
164 PROCESSOR_ATHLON,
165 PROCESSOR_K8,
166 PROCESSOR_GENERIC32,
167 PROCESSOR_GENERIC64,
168 PROCESSOR_AMDFAM10
169};
170
171/* x86 arch names, types and features */
172typedef struct
173{
174 const char *name; /* arch name */
175 enum processor_type type; /* arch type */
176 i386_cpu_flags flags; /* cpu feature flags */
177}
178arch_entry;
179
e3bb37b5
L		 180static void set_code_flag (int);
181static void set_16bit_gcc_code_flag (int);
182static void set_intel_syntax (int);
1efbbeb4 183static void set_intel_mnemonic (int);
db51cc60 184static void set_allow_index_reg (int);
e3bb37b5 185static void set_cpu_arch (int);
6482c264 186#ifdef TE_PE
e3bb37b5 187static void pe_directive_secrel (int);
6482c264 188#endif
e3bb37b5
L		 189static void signed_cons (int);
190static char *output_invalid (int c);
a7619375 191static int i386_att_operand (char *);
e3bb37b5
L		 192static int i386_intel_operand (char *, int);
193static const reg_entry *parse_register (char *, char **);
194static char *parse_insn (char *, char *);
195static char *parse_operands (char *, const char *);
196static void swap_operands (void);
4d456e3d 197static void swap_2_operands (int, int);
e3bb37b5
L		 198static void optimize_imm (void);
199static void optimize_disp (void);
200static int match_template (void);
201static int check_string (void);
202static int process_suffix (void);
203static int check_byte_reg (void);
204static int check_long_reg (void);
205static int check_qword_reg (void);
206static int check_word_reg (void);
207static int finalize_imm (void);
85f10a01 208static void process_drex (void);
e3bb37b5
L		 209static int process_operands (void);
210static const seg_entry *build_modrm_byte (void);
211static void output_insn (void);
212static void output_imm (fragS *, offsetT);
213static void output_disp (fragS *, offsetT);
29b0f896 214#ifndef I386COFF
e3bb37b5 215static void s_bss (int);
252b5132 216#endif
17d4e2a2
L		 217#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
218static void handle_large_common (int small ATTRIBUTE_UNUSED);
219#endif
252b5132 220
a847613f 221static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 222
252b5132 223/* 'md_assemble ()' gathers together information and puts it into a
47926f60 224 i386_insn. */
252b5132 225
520dc8e8
AM		 226union i386_op
227 {
228 expressionS *disps;
229 expressionS *imms;
230 const reg_entry *regs;
231 };
232
252b5132
RH		 233struct _i386_insn
234 {
47926f60 235 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 236 template tm;
237
7d5e4556
L		 238 /* SUFFIX holds the instruction size suffix for byte, word, dword
239 or qword, if given. */
252b5132
RH		 240 char suffix;
241
47926f60 242 /* OPERANDS gives the number of given operands. */
252b5132
RH		 243 unsigned int operands;
244
245 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
246 of given register, displacement, memory operands and immediate
47926f60 247 operands. */
252b5132
RH		 248 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
249
250 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 251 use OP[i] for the corresponding operand. */
40fb9820 252 i386_operand_type types[MAX_OPERANDS];
252b5132 253
520dc8e8
AM		 254 /* Displacement expression, immediate expression, or register for each
255 operand. */
256 union i386_op op[MAX_OPERANDS];
252b5132 257
3e73aa7c
JH		 258 /* Flags for operands. */
259 unsigned int flags[MAX_OPERANDS];
260#define Operand_PCrel 1
261
252b5132 262 /* Relocation type for operand */
f86103b7 263 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 264
252b5132
RH		 265 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
266 the base index byte below. */
267 const reg_entry *base_reg;
268 const reg_entry *index_reg;
269 unsigned int log2_scale_factor;
270
271 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 272 explicit segment overrides are given. */
ce8a8b2f 273 const seg_entry *seg[2];
252b5132
RH		 274
275 /* PREFIX holds all the given prefix opcodes (usually null).
276 PREFIXES is the number of prefix opcodes. */
277 unsigned int prefixes;
278 unsigned char prefix[MAX_PREFIXES];
279
280 /* RM and SIB are the modrm byte and the sib byte where the
85f10a01
MM		 281 addressing modes of this insn are encoded. DREX is the byte
282 added by the SSE5 instructions. */
252b5132
RH		 283
284 modrm_byte rm;
3e73aa7c 285 rex_byte rex;
252b5132 286 sib_byte sib;
85f10a01 287 drex_byte drex;
252b5132
RH		 288 };
289
290typedef struct _i386_insn i386_insn;
291
292/* List of chars besides those in app.c:symbol_chars that can start an
293 operand. Used to prevent the scrubber eating vital white-space. */
32137342 294const char extra_symbol_chars[] = "*%-(["
252b5132 295#ifdef LEX_AT
32137342
NC		 296 "@"
297#endif
298#ifdef LEX_QM
299 "?"
252b5132 300#endif
32137342 301 ;
252b5132 302
29b0f896
AM		 303#if (defined (TE_I386AIX) \
304 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 305 && !defined (TE_GNU) \
29b0f896 306 && !defined (TE_LINUX) \
32137342 307 && !defined (TE_NETWARE) \
29b0f896
AM		 308 && !defined (TE_FreeBSD) \
309 && !defined (TE_NetBSD)))
252b5132 310/* This array holds the chars that always start a comment. If the
b3b91714
AM		 311 pre-processor is disabled, these aren't very useful. The option
312 --divide will remove '/' from this list. */
313const char *i386_comment_chars = "#/";
314#define SVR4_COMMENT_CHARS 1
252b5132 315#define PREFIX_SEPARATOR '\\'
252b5132 316
b3b91714
AM		 317#else
318const char *i386_comment_chars = "#";
319#define PREFIX_SEPARATOR '/'
320#endif
321
252b5132
RH		 322/* This array holds the chars that only start a comment at the beginning of
323 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 324 .line and .file directives will appear in the pre-processed output.
325 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 326 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 327 #NO_APP at the beginning of its output.
328 Also note that comments started like this one will always work if
252b5132 329 '/' isn't otherwise defined. */
b3b91714 330const char line_comment_chars[] = "#/";
252b5132 331
63a0b638 332const char line_separator_chars[] = ";";
252b5132 333
ce8a8b2f
AM		 334/* Chars that can be used to separate mant from exp in floating point
335 nums. */
252b5132
RH		 336const char EXP_CHARS[] = "eE";
337
ce8a8b2f
AM		 338/* Chars that mean this number is a floating point constant
339 As in 0f12.456
340 or 0d1.2345e12. */
252b5132
RH		 341const char FLT_CHARS[] = "fFdDxX";
342
ce8a8b2f 343/* Tables for lexical analysis. */
252b5132
RH		 344static char mnemonic_chars[256];
345static char register_chars[256];
346static char operand_chars[256];
347static char identifier_chars[256];
348static char digit_chars[256];
349
ce8a8b2f 350/* Lexical macros. */
252b5132
RH		 351#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
352#define is_operand_char(x) (operand_chars[(unsigned char) x])
353#define is_register_char(x) (register_chars[(unsigned char) x])
354#define is_space_char(x) ((x) == ' ')
355#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
356#define is_digit_char(x) (digit_chars[(unsigned char) x])
357
0234cb7c 358/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 359static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
360
361/* md_assemble() always leaves the strings it's passed unaltered. To
362 effect this we maintain a stack of saved characters that we've smashed
363 with '\0's (indicating end of strings for various sub-fields of the
47926f60 364 assembler instruction). */
252b5132 365static char save_stack[32];
ce8a8b2f 366static char *save_stack_p;
252b5132
RH		 367#define END_STRING_AND_SAVE(s) \
368 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
369#define RESTORE_END_STRING(s) \
370 do { *(s) = *--save_stack_p; } while (0)
371
47926f60 372/* The instruction we're assembling. */
252b5132
RH		 373static i386_insn i;
374
375/* Possible templates for current insn. */
376static const templates *current_templates;
377
31b2323c
L		 378/* Per instruction expressionS buffers: max displacements & immediates. */
379static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
380static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 381
47926f60
KH		 382/* Current operand we are working on. */
383static int this_operand;
252b5132 384
3e73aa7c
JH		 385/* We support four different modes. FLAG_CODE variable is used to distinguish
386 these. */
387
388enum flag_code {
389 CODE_32BIT,
390 CODE_16BIT,
391 CODE_64BIT };
392
393static enum flag_code flag_code;
4fa24527 394static unsigned int object_64bit;
3e73aa7c
JH		 395static int use_rela_relocations = 0;
396
397/* The names used to print error messages. */
b77a7acd 398static const char *flag_code_names[] =
3e73aa7c
JH		 399 {
400 "32",
401 "16",
402 "64"
403 };
252b5132 404
47926f60
KH		 405/* 1 for intel syntax,
406 0 if att syntax. */
407static int intel_syntax = 0;
252b5132 408
1efbbeb4
L		 409/* 1 for intel mnemonic,
410 0 if att mnemonic. */
411static int intel_mnemonic = !SYSV386_COMPAT;
412
5209009a 413/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 414static int old_gcc = OLDGCC_COMPAT;
415
a60de03c
JB		 416/* 1 if pseudo registers are permitted. */
417static int allow_pseudo_reg = 0;
418
47926f60
KH		 419/* 1 if register prefix % not required. */
420static int allow_naked_reg = 0;
252b5132 421
ba104c83 422/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 423static int allow_index_reg = 0;
424
2ca3ace5
L		 425/* Register prefix used for error message. */
426static const char *register_prefix = "%";
427
47926f60
KH		 428/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
429 leave, push, and pop instructions so that gcc has the same stack
430 frame as in 32 bit mode. */
431static char stackop_size = '\0';
eecb386c 432
12b55ccc
L		 433/* Non-zero to optimize code alignment. */
434int optimize_align_code = 1;
435
47926f60
KH		 436/* Non-zero to quieten some warnings. */
437static int quiet_warnings = 0;
a38cf1db 438
47926f60
KH		 439/* CPU name. */
440static const char *cpu_arch_name = NULL;
6305a203 441static char *cpu_sub_arch_name = NULL;
a38cf1db 442
47926f60 443/* CPU feature flags. */
40fb9820
L		 444static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
445
ccc9c027
L		 446/* If we have selected a cpu we are generating instructions for. */
447static int cpu_arch_tune_set = 0;
448
9103f4f4
L		 449/* Cpu we are generating instructions for. */
450static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
451
452/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 453static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 454
ccc9c027
L		 455/* CPU instruction set architecture used. */
456static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
457
9103f4f4 458/* CPU feature flags of instruction set architecture used. */
40fb9820 459static i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 460
fddf5b5b
AM		 461/* If set, conditional jumps are not automatically promoted to handle
462 larger than a byte offset. */
463static unsigned int no_cond_jump_promotion = 0;
464
29b0f896 465/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 466static symbolS *GOT_symbol;
29b0f896 467
a4447b93
RH		 468/* The dwarf2 return column, adjusted for 32 or 64 bit. */
469unsigned int x86_dwarf2_return_column;
470
471/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
472int x86_cie_data_alignment;
473
252b5132 474/* Interface to relax_segment.
fddf5b5b
AM		 475 There are 3 major relax states for 386 jump insns because the
476 different types of jumps add different sizes to frags when we're
477 figuring out what sort of jump to choose to reach a given label. */
252b5132 478
47926f60 479/* Types. */
93c2a809
AM		 480#define UNCOND_JUMP 0
481#define COND_JUMP 1
482#define COND_JUMP86 2
fddf5b5b 483
47926f60 484/* Sizes. */
252b5132
RH		 485#define CODE16 1
486#define SMALL 0
29b0f896 487#define SMALL16 (SMALL | CODE16)
252b5132 488#define BIG 2
29b0f896 489#define BIG16 (BIG | CODE16)
252b5132
RH		 490
491#ifndef INLINE
492#ifdef __GNUC__
493#define INLINE __inline__
494#else
495#define INLINE
496#endif
497#endif
498
fddf5b5b
AM		 499#define ENCODE_RELAX_STATE(type, size) \
500 ((relax_substateT) (((type) << 2) | (size)))
501#define TYPE_FROM_RELAX_STATE(s) \
502 ((s) >> 2)
503#define DISP_SIZE_FROM_RELAX_STATE(s) \
504 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 505
506/* This table is used by relax_frag to promote short jumps to long
507 ones where necessary. SMALL (short) jumps may be promoted to BIG
508 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
509 don't allow a short jump in a 32 bit code segment to be promoted to
510 a 16 bit offset jump because it's slower (requires data size
511 prefix), and doesn't work, unless the destination is in the bottom
512 64k of the code segment (The top 16 bits of eip are zeroed). */
513
514const relax_typeS md_relax_table[] =
515{
24eab124
AM		 516 /* The fields are:
517 1) most positive reach of this state,
518 2) most negative reach of this state,
93c2a809 519 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 520 4) which index into the table to try if we can't fit into this one. */
252b5132 521
fddf5b5b 522 /* UNCOND_JUMP states. */
93c2a809
AM		 523 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
524 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
525 /* dword jmp adds 4 bytes to frag:
526 0 extra opcode bytes, 4 displacement bytes. */
252b5132 527 {0, 0, 4, 0},
93c2a809
AM		 528 /* word jmp adds 2 byte2 to frag:
529 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 530 {0, 0, 2, 0},
531
93c2a809
AM		 532 /* COND_JUMP states. */
533 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
534 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
535 /* dword conditionals adds 5 bytes to frag:
536 1 extra opcode byte, 4 displacement bytes. */
537 {0, 0, 5, 0},
fddf5b5b 538 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 539 1 extra opcode byte, 2 displacement bytes. */
540 {0, 0, 3, 0},
541
542 /* COND_JUMP86 states. */
543 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
544 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
545 /* dword conditionals adds 5 bytes to frag:
546 1 extra opcode byte, 4 displacement bytes. */
547 {0, 0, 5, 0},
548 /* word conditionals add 4 bytes to frag:
549 1 displacement byte and a 3 byte long branch insn. */
550 {0, 0, 4, 0}
252b5132
RH		 551};
552
9103f4f4
L		 553static const arch_entry cpu_arch[] =
554{
6305a203
L		 555 { "generic32", PROCESSOR_GENERIC32,
556 CPU_GENERIC32_FLAGS },
557 { "generic64", PROCESSOR_GENERIC64,
558 CPU_GENERIC64_FLAGS },
559 { "i8086", PROCESSOR_UNKNOWN,
560 CPU_NONE_FLAGS },
561 { "i186", PROCESSOR_UNKNOWN,
562 CPU_I186_FLAGS },
563 { "i286", PROCESSOR_UNKNOWN,
564 CPU_I286_FLAGS },
565 { "i386", PROCESSOR_I386,
566 CPU_I386_FLAGS },
567 { "i486", PROCESSOR_I486,
568 CPU_I486_FLAGS },
569 { "i586", PROCESSOR_PENTIUM,
570 CPU_I586_FLAGS },
571 { "i686", PROCESSOR_PENTIUMPRO,
572 CPU_I686_FLAGS },
573 { "pentium", PROCESSOR_PENTIUM,
574 CPU_I586_FLAGS },
575 { "pentiumpro", PROCESSOR_PENTIUMPRO,
576 CPU_I686_FLAGS },
577 { "pentiumii", PROCESSOR_PENTIUMPRO,
578 CPU_P2_FLAGS },
579 { "pentiumiii",PROCESSOR_PENTIUMPRO,
580 CPU_P3_FLAGS },
581 { "pentium4", PROCESSOR_PENTIUM4,
582 CPU_P4_FLAGS },
583 { "prescott", PROCESSOR_NOCONA,
584 CPU_CORE_FLAGS },
585 { "nocona", PROCESSOR_NOCONA,
586 CPU_NOCONA_FLAGS },
587 { "yonah", PROCESSOR_CORE,
588 CPU_CORE_FLAGS },
589 { "core", PROCESSOR_CORE,
590 CPU_CORE_FLAGS },
591 { "merom", PROCESSOR_CORE2,
592 CPU_CORE2_FLAGS },
593 { "core2", PROCESSOR_CORE2,
594 CPU_CORE2_FLAGS },
595 { "k6", PROCESSOR_K6,
596 CPU_K6_FLAGS },
597 { "k6_2", PROCESSOR_K6,
598 CPU_K6_2_FLAGS },
599 { "athlon", PROCESSOR_ATHLON,
600 CPU_ATHLON_FLAGS },
601 { "sledgehammer", PROCESSOR_K8,
602 CPU_K8_FLAGS },
603 { "opteron", PROCESSOR_K8,
604 CPU_K8_FLAGS },
605 { "k8", PROCESSOR_K8,
606 CPU_K8_FLAGS },
607 { "amdfam10", PROCESSOR_AMDFAM10,
608 CPU_AMDFAM10_FLAGS },
609 { ".mmx", PROCESSOR_UNKNOWN,
610 CPU_MMX_FLAGS },
611 { ".sse", PROCESSOR_UNKNOWN,
612 CPU_SSE_FLAGS },
613 { ".sse2", PROCESSOR_UNKNOWN,
614 CPU_SSE2_FLAGS },
615 { ".sse3", PROCESSOR_UNKNOWN,
616 CPU_SSE3_FLAGS },
617 { ".ssse3", PROCESSOR_UNKNOWN,
618 CPU_SSSE3_FLAGS },
619 { ".sse4.1", PROCESSOR_UNKNOWN,
620 CPU_SSE4_1_FLAGS },
621 { ".sse4.2", PROCESSOR_UNKNOWN,
622 CPU_SSE4_2_FLAGS },
623 { ".sse4", PROCESSOR_UNKNOWN,
624 CPU_SSE4_2_FLAGS },
625 { ".vmx", PROCESSOR_UNKNOWN,
626 CPU_VMX_FLAGS },
627 { ".smx", PROCESSOR_UNKNOWN,
628 CPU_SMX_FLAGS },
f03fe4c1
L		 629 { ".xsave", PROCESSOR_UNKNOWN,
630 CPU_XSAVE_FLAGS },
6305a203
L		 631 { ".3dnow", PROCESSOR_UNKNOWN,
632 CPU_3DNOW_FLAGS },
633 { ".3dnowa", PROCESSOR_UNKNOWN,
634 CPU_3DNOWA_FLAGS },
635 { ".padlock", PROCESSOR_UNKNOWN,
636 CPU_PADLOCK_FLAGS },
637 { ".pacifica", PROCESSOR_UNKNOWN,
638 CPU_SVME_FLAGS },
639 { ".svme", PROCESSOR_UNKNOWN,
640 CPU_SVME_FLAGS },
641 { ".sse4a", PROCESSOR_UNKNOWN,
642 CPU_SSE4A_FLAGS },
643 { ".abm", PROCESSOR_UNKNOWN,
644 CPU_ABM_FLAGS },
645 { ".sse5", PROCESSOR_UNKNOWN,
646 CPU_SSE5_FLAGS },
e413e4e9
AM		 647};
648
29b0f896
AM		 649const pseudo_typeS md_pseudo_table[] =
650{
651#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
652 {"align", s_align_bytes, 0},
653#else
654 {"align", s_align_ptwo, 0},
655#endif
656 {"arch", set_cpu_arch, 0},
657#ifndef I386COFF
658 {"bss", s_bss, 0},
659#endif
660 {"ffloat", float_cons, 'f'},
661 {"dfloat", float_cons, 'd'},
662 {"tfloat", float_cons, 'x'},
663 {"value", cons, 2},
d182319b 664 {"slong", signed_cons, 4},
29b0f896
AM		 665 {"noopt", s_ignore, 0},
666 {"optim", s_ignore, 0},
667 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
668 {"code16", set_code_flag, CODE_16BIT},
669 {"code32", set_code_flag, CODE_32BIT},
670 {"code64", set_code_flag, CODE_64BIT},
671 {"intel_syntax", set_intel_syntax, 1},
672 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 673 {"intel_mnemonic", set_intel_mnemonic, 1},
674 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 675 {"allow_index_reg", set_allow_index_reg, 1},
676 {"disallow_index_reg", set_allow_index_reg, 0},
3b22753a
L		 677#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
678 {"largecomm", handle_large_common, 0},
07a53e5c 679#else
e3bb37b5 680 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 681 {"loc", dwarf2_directive_loc, 0},
682 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 683#endif
6482c264
NC		 684#ifdef TE_PE
685 {"secrel32", pe_directive_secrel, 0},
686#endif
29b0f896
AM		 687 {0, 0, 0}
688};
689
690/* For interface with expression (). */
691extern char *input_line_pointer;
692
693/* Hash table for instruction mnemonic lookup. */
694static struct hash_control *op_hash;
695
696/* Hash table for register lookup. */
697static struct hash_control *reg_hash;
698\f
252b5132 699void
e3bb37b5 700i386_align_code (fragS *fragP, int count)
252b5132 701{
ce8a8b2f
AM		 702 /* Various efficient no-op patterns for aligning code labels.
703 Note: Don't try to assemble the instructions in the comments.
704 0L and 0w are not legal. */
252b5132
RH		 705 static const char f32_1[] =
706 {0x90}; /* nop */
707 static const char f32_2[] =
ccc9c027 708 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 709 static const char f32_3[] =
710 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
711 static const char f32_4[] =
712 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
713 static const char f32_5[] =
714 {0x90, /* nop */
715 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
716 static const char f32_6[] =
717 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
718 static const char f32_7[] =
719 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
720 static const char f32_8[] =
721 {0x90, /* nop */
722 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
723 static const char f32_9[] =
724 {0x89,0xf6, /* movl %esi,%esi */
725 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
726 static const char f32_10[] =
727 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
728 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
729 static const char f32_11[] =
730 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
731 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
732 static const char f32_12[] =
733 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
734 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
735 static const char f32_13[] =
736 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
737 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
738 static const char f32_14[] =
739 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
740 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 741 static const char f16_3[] =
742 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 743 static const char f16_4[] =
744 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
745 static const char f16_5[] =
746 {0x90, /* nop */
747 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
748 static const char f16_6[] =
749 {0x89,0xf6, /* mov %si,%si */
750 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
751 static const char f16_7[] =
752 {0x8d,0x74,0x00, /* lea 0(%si),%si */
753 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
754 static const char f16_8[] =
755 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
756 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 757 static const char jump_31[] =
758 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
759 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
760 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
761 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 762 static const char *const f32_patt[] = {
763 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 764 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 765 };
766 static const char *const f16_patt[] = {
76bc74dc 767 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 768 };
ccc9c027
L		 769 /* nopl (%[re]ax) */
770 static const char alt_3[] =
771 {0x0f,0x1f,0x00};
772 /* nopl 0(%[re]ax) */
773 static const char alt_4[] =
774 {0x0f,0x1f,0x40,0x00};
775 /* nopl 0(%[re]ax,%[re]ax,1) */
776 static const char alt_5[] =
777 {0x0f,0x1f,0x44,0x00,0x00};
778 /* nopw 0(%[re]ax,%[re]ax,1) */
779 static const char alt_6[] =
780 {0x66,0x0f,0x1f,0x44,0x00,0x00};
781 /* nopl 0L(%[re]ax) */
782 static const char alt_7[] =
783 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
784 /* nopl 0L(%[re]ax,%[re]ax,1) */
785 static const char alt_8[] =
786 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
787 /* nopw 0L(%[re]ax,%[re]ax,1) */
788 static const char alt_9[] =
789 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
790 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
791 static const char alt_10[] =
792 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
793 /* data16
794 nopw %cs:0L(%[re]ax,%[re]ax,1) */
795 static const char alt_long_11[] =
796 {0x66,
797 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
798 /* data16
799 data16
800 nopw %cs:0L(%[re]ax,%[re]ax,1) */
801 static const char alt_long_12[] =
802 {0x66,
803 0x66,
804 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
805 /* data16
806 data16
807 data16
808 nopw %cs:0L(%[re]ax,%[re]ax,1) */
809 static const char alt_long_13[] =
810 {0x66,
811 0x66,
812 0x66,
813 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
814 /* data16
815 data16
816 data16
817 data16
818 nopw %cs:0L(%[re]ax,%[re]ax,1) */
819 static const char alt_long_14[] =
820 {0x66,
821 0x66,
822 0x66,
823 0x66,
824 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
825 /* data16
826 data16
827 data16
828 data16
829 data16
830 nopw %cs:0L(%[re]ax,%[re]ax,1) */
831 static const char alt_long_15[] =
832 {0x66,
833 0x66,
834 0x66,
835 0x66,
836 0x66,
837 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
838 /* nopl 0(%[re]ax,%[re]ax,1)
839 nopw 0(%[re]ax,%[re]ax,1) */
840 static const char alt_short_11[] =
841 {0x0f,0x1f,0x44,0x00,0x00,
842 0x66,0x0f,0x1f,0x44,0x00,0x00};
843 /* nopw 0(%[re]ax,%[re]ax,1)
844 nopw 0(%[re]ax,%[re]ax,1) */
845 static const char alt_short_12[] =
846 {0x66,0x0f,0x1f,0x44,0x00,0x00,
847 0x66,0x0f,0x1f,0x44,0x00,0x00};
848 /* nopw 0(%[re]ax,%[re]ax,1)
849 nopl 0L(%[re]ax) */
850 static const char alt_short_13[] =
851 {0x66,0x0f,0x1f,0x44,0x00,0x00,
852 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
853 /* nopl 0L(%[re]ax)
854 nopl 0L(%[re]ax) */
855 static const char alt_short_14[] =
856 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
857 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
858 /* nopl 0L(%[re]ax)
859 nopl 0L(%[re]ax,%[re]ax,1) */
860 static const char alt_short_15[] =
861 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
862 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
863 static const char *const alt_short_patt[] = {
864 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
865 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
866 alt_short_14, alt_short_15
867 };
868 static const char *const alt_long_patt[] = {
869 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
870 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
871 alt_long_14, alt_long_15
872 };
252b5132 873
76bc74dc
L		 874 /* Only align for at least a positive non-zero boundary. */
875 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 876 return;
3e73aa7c 877
ccc9c027
L		 878 /* We need to decide which NOP sequence to use for 32bit and
879 64bit. When -mtune= is used:
4eed87de 880
76bc74dc
L		 881 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
882 PROCESSOR_GENERIC32, f32_patt will be used.
883 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
884 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
885 alt_long_patt will be used.
886 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
887 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 888
76bc74dc
L		 889 When -mtune= isn't used, alt_long_patt will be used if
890 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
891 be used.
ccc9c027
L		 892
893 When -march= or .arch is used, we can't use anything beyond
894 cpu_arch_isa_flags. */
895
896 if (flag_code == CODE_16BIT)
897 {
ccc9c027 898 if (count > 8)
33fef721 899 {
76bc74dc
L		 900 memcpy (fragP->fr_literal + fragP->fr_fix,
901 jump_31, count);
902 /* Adjust jump offset. */
903 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 904 }
76bc74dc
L		 905 else
906 memcpy (fragP->fr_literal + fragP->fr_fix,
907 f16_patt[count - 1], count);
252b5132 908 }
33fef721 909 else
ccc9c027
L		 910 {
911 const char *const *patt = NULL;
912
913 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
914 {
915 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
916 switch (cpu_arch_tune)
917 {
918 case PROCESSOR_UNKNOWN:
919 /* We use cpu_arch_isa_flags to check if we SHOULD
920 optimize for Cpu686. */
40fb9820 921 if (cpu_arch_isa_flags.bitfield.cpui686)
76bc74dc 922 patt = alt_long_patt;
ccc9c027
L		 923 else
924 patt = f32_patt;
925 break;
ccc9c027
L		 926 case PROCESSOR_PENTIUMPRO:
927 case PROCESSOR_PENTIUM4:
928 case PROCESSOR_NOCONA:
ef05d495 929 case PROCESSOR_CORE:
76bc74dc
L		 930 case PROCESSOR_CORE2:
931 case PROCESSOR_GENERIC64:
932 patt = alt_long_patt;
933 break;
ccc9c027
L		 934 case PROCESSOR_K6:
935 case PROCESSOR_ATHLON:
936 case PROCESSOR_K8:
4eed87de 937 case PROCESSOR_AMDFAM10:
ccc9c027
L		 938 patt = alt_short_patt;
939 break;
76bc74dc 940 case PROCESSOR_I386:
ccc9c027
L		 941 case PROCESSOR_I486:
942 case PROCESSOR_PENTIUM:
943 case PROCESSOR_GENERIC32:
944 patt = f32_patt;
945 break;
4eed87de 946 }
ccc9c027
L		 947 }
948 else
949 {
950 switch (cpu_arch_tune)
951 {
952 case PROCESSOR_UNKNOWN:
953 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
954 PROCESSOR_UNKNOWN. */
955 abort ();
956 break;
957
76bc74dc 958 case PROCESSOR_I386:
ccc9c027
L		 959 case PROCESSOR_I486:
960 case PROCESSOR_PENTIUM:
ccc9c027
L		 961 case PROCESSOR_K6:
962 case PROCESSOR_ATHLON:
963 case PROCESSOR_K8:
4eed87de 964 case PROCESSOR_AMDFAM10:
ccc9c027
L		 965 case PROCESSOR_GENERIC32:
966 /* We use cpu_arch_isa_flags to check if we CAN optimize
967 for Cpu686. */
40fb9820 968 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 969 patt = alt_short_patt;
970 else
971 patt = f32_patt;
972 break;
76bc74dc
L		 973 case PROCESSOR_PENTIUMPRO:
974 case PROCESSOR_PENTIUM4:
975 case PROCESSOR_NOCONA:
976 case PROCESSOR_CORE:
ef05d495 977 case PROCESSOR_CORE2:
40fb9820 978 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 979 patt = alt_long_patt;
980 else
981 patt = f32_patt;
982 break;
983 case PROCESSOR_GENERIC64:
76bc74dc 984 patt = alt_long_patt;
ccc9c027 985 break;
4eed87de 986 }
ccc9c027
L		 987 }
988
76bc74dc
L		 989 if (patt == f32_patt)
990 {
991 /* If the padding is less than 15 bytes, we use the normal
992 ones. Otherwise, we use a jump instruction and adjust
993 its offset. */
994 if (count < 15)
995 memcpy (fragP->fr_literal + fragP->fr_fix,
996 patt[count - 1], count);
997 else
998 {
999 memcpy (fragP->fr_literal + fragP->fr_fix,
1000 jump_31, count);
1001 /* Adjust jump offset. */
1002 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1003 }
1004 }
1005 else
1006 {
1007 /* Maximum length of an instruction is 15 byte. If the
1008 padding is greater than 15 bytes and we don't use jump,
1009 we have to break it into smaller pieces. */
1010 int padding = count;
1011 while (padding > 15)
1012 {
1013 padding -= 15;
1014 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1015 patt [14], 15);
1016 }
1017
1018 if (padding)
1019 memcpy (fragP->fr_literal + fragP->fr_fix,
1020 patt [padding - 1], padding);
1021 }
ccc9c027 1022 }
33fef721 1023 fragP->fr_var = count;
252b5132
RH		 1024}
1025
c6fb90c8 1026static INLINE int
0dfbf9d7 1027operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1028{
0dfbf9d7 1029 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1030 {
1031 case 3:
0dfbf9d7 1032 if (x->array[2])
c6fb90c8
L		 1033 return 0;
1034 case 2:
0dfbf9d7 1035 if (x->array[1])
c6fb90c8
L		 1036 return 0;
1037 case 1:
0dfbf9d7 1038 return !x->array[0];
c6fb90c8
L		 1039 default:
1040 abort ();
1041 }
40fb9820
L		 1042}
1043
c6fb90c8 1044static INLINE void
0dfbf9d7 1045operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1046{
0dfbf9d7 1047 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1048 {
1049 case 3:
0dfbf9d7 1050 x->array[2] = v;
c6fb90c8 1051 case 2:
0dfbf9d7 1052 x->array[1] = v;
c6fb90c8 1053 case 1:
0dfbf9d7 1054 x->array[0] = v;
c6fb90c8
L		 1055 break;
1056 default:
1057 abort ();
1058 }
1059}
40fb9820 1060
c6fb90c8 1061static INLINE int
0dfbf9d7
L		 1062operand_type_equal (const union i386_operand_type *x,
1063 const union i386_operand_type *y)
c6fb90c8 1064{
0dfbf9d7 1065 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1066 {
1067 case 3:
0dfbf9d7 1068 if (x->array[2] != y->array[2])
c6fb90c8
L		 1069 return 0;
1070 case 2:
0dfbf9d7 1071 if (x->array[1] != y->array[1])
c6fb90c8
L		 1072 return 0;
1073 case 1:
0dfbf9d7 1074 return x->array[0] == y->array[0];
c6fb90c8
L		 1075 break;
1076 default:
1077 abort ();
1078 }
1079}
40fb9820 1080
0dfbf9d7
L		 1081static INLINE int
1082cpu_flags_all_zero (const union i386_cpu_flags *x)
1083{
1084 switch (ARRAY_SIZE(x->array))
1085 {
1086 case 3:
1087 if (x->array[2])
1088 return 0;
1089 case 2:
1090 if (x->array[1])
1091 return 0;
1092 case 1:
1093 return !x->array[0];
1094 default:
1095 abort ();
1096 }
1097}
1098
1099static INLINE void
1100cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1101{
1102 switch (ARRAY_SIZE(x->array))
1103 {
1104 case 3:
1105 x->array[2] = v;
1106 case 2:
1107 x->array[1] = v;
1108 case 1:
1109 x->array[0] = v;
1110 break;
1111 default:
1112 abort ();
1113 }
1114}
1115
1116static INLINE int
1117cpu_flags_equal (const union i386_cpu_flags *x,
1118 const union i386_cpu_flags *y)
1119{
1120 switch (ARRAY_SIZE(x->array))
1121 {
1122 case 3:
1123 if (x->array[2] != y->array[2])
1124 return 0;
1125 case 2:
1126 if (x->array[1] != y->array[1])
1127 return 0;
1128 case 1:
1129 return x->array[0] == y->array[0];
1130 break;
1131 default:
1132 abort ();
1133 }
1134}
c6fb90c8
L		 1135
1136static INLINE int
1137cpu_flags_check_cpu64 (i386_cpu_flags f)
1138{
1139 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1140 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1141}
1142
c6fb90c8
L		 1143static INLINE i386_cpu_flags
1144cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1145{
c6fb90c8
L		 1146 switch (ARRAY_SIZE (x.array))
1147 {
1148 case 3:
1149 x.array [2] &= y.array [2];
1150 case 2:
1151 x.array [1] &= y.array [1];
1152 case 1:
1153 x.array [0] &= y.array [0];
1154 break;
1155 default:
1156 abort ();
1157 }
1158 return x;
1159}
40fb9820 1160
c6fb90c8
L		 1161static INLINE i386_cpu_flags
1162cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1163{
c6fb90c8 1164 switch (ARRAY_SIZE (x.array))
40fb9820 1165 {
c6fb90c8
L		 1166 case 3:
1167 x.array [2] |= y.array [2];
1168 case 2:
1169 x.array [1] |= y.array [1];
1170 case 1:
1171 x.array [0] |= y.array [0];
40fb9820
L		 1172 break;
1173 default:
1174 abort ();
1175 }
40fb9820
L		 1176 return x;
1177}
1178
3629bb00
L		 1179/* Return 3 if there is a perfect match, 2 if compatible with 64bit,
1180 1 if compatible with arch, 0 if there is no match. */
1181
40fb9820
L		 1182static int
1183cpu_flags_match (i386_cpu_flags x)
1184{
3629bb00 1185 int overlap = cpu_flags_check_cpu64 (x) ? 2 : 0;
40fb9820
L		 1186
1187 x.bitfield.cpu64 = 0;
1188 x.bitfield.cpuno64 = 0;
1189
0dfbf9d7 1190 if (cpu_flags_all_zero (&x))
3629bb00
L		 1191 overlap |= 1;
1192 else
1193 {
1194 i386_cpu_flags cpu = cpu_arch_flags;
1195
1196 cpu.bitfield.cpu64 = 0;
1197 cpu.bitfield.cpuno64 = 0;
1198 cpu = cpu_flags_and (x, cpu);
0dfbf9d7 1199 overlap |= cpu_flags_all_zero (&cpu) ? 0 : 1;
3629bb00
L		 1200 }
1201 return overlap;
40fb9820
L		 1202}
1203
c6fb90c8
L		 1204static INLINE i386_operand_type
1205operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1206{
c6fb90c8
L		 1207 switch (ARRAY_SIZE (x.array))
1208 {
1209 case 3:
1210 x.array [2] &= y.array [2];
1211 case 2:
1212 x.array [1] &= y.array [1];
1213 case 1:
1214 x.array [0] &= y.array [0];
1215 break;
1216 default:
1217 abort ();
1218 }
1219 return x;
40fb9820
L		 1220}
1221
c6fb90c8
L		 1222static INLINE i386_operand_type
1223operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1224{
c6fb90c8 1225 switch (ARRAY_SIZE (x.array))
40fb9820 1226 {
c6fb90c8
L		 1227 case 3:
1228 x.array [2] |= y.array [2];
1229 case 2:
1230 x.array [1] |= y.array [1];
1231 case 1:
1232 x.array [0] |= y.array [0];
40fb9820
L		 1233 break;
1234 default:
1235 abort ();
1236 }
c6fb90c8
L		 1237 return x;
1238}
40fb9820 1239
c6fb90c8
L		 1240static INLINE i386_operand_type
1241operand_type_xor (i386_operand_type x, i386_operand_type y)
1242{
1243 switch (ARRAY_SIZE (x.array))
1244 {
1245 case 3:
1246 x.array [2] ^= y.array [2];
1247 case 2:
1248 x.array [1] ^= y.array [1];
1249 case 1:
1250 x.array [0] ^= y.array [0];
1251 break;
1252 default:
1253 abort ();
1254 }
40fb9820
L		 1255 return x;
1256}
1257
1258static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1259static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1260static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1261static const i386_operand_type inoutportreg
1262 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1263static const i386_operand_type reg16_inoutportreg
1264 = OPERAND_TYPE_REG16_INOUTPORTREG;
1265static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1266static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1267static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1268static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1269static const i386_operand_type anydisp
1270 = OPERAND_TYPE_ANYDISP;
40fb9820
L		 1271static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1272static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1273static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1274static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1275static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1276static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1277static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1278static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1279static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1280static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1281
1282enum operand_type
1283{
1284 reg,
40fb9820
L		 1285 imm,
1286 disp,
1287 anymem
1288};
1289
c6fb90c8 1290static INLINE int
40fb9820
L		 1291operand_type_check (i386_operand_type t, enum operand_type c)
1292{
1293 switch (c)
1294 {
1295 case reg:
1296 return (t.bitfield.reg8
1297 || t.bitfield.reg16
1298 || t.bitfield.reg32
1299 || t.bitfield.reg64);
1300
40fb9820
L		 1301 case imm:
1302 return (t.bitfield.imm8
1303 || t.bitfield.imm8s
1304 || t.bitfield.imm16
1305 || t.bitfield.imm32
1306 || t.bitfield.imm32s
1307 || t.bitfield.imm64);
1308
1309 case disp:
1310 return (t.bitfield.disp8
1311 || t.bitfield.disp16
1312 || t.bitfield.disp32
1313 || t.bitfield.disp32s
1314 || t.bitfield.disp64);
1315
1316 case anymem:
1317 return (t.bitfield.disp8
1318 || t.bitfield.disp16
1319 || t.bitfield.disp32
1320 || t.bitfield.disp32s
1321 || t.bitfield.disp64
1322 || t.bitfield.baseindex);
1323
1324 default:
1325 abort ();
1326 }
1327}
1328
5c07affc
L		 1329/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1330 operand J for instruction template T. */
1331
1332static INLINE int
1333match_reg_size (const template *t, unsigned int j)
1334{
1335 return !((i.types[j].bitfield.byte
1336 && !t->operand_types[j].bitfield.byte)
1337 || (i.types[j].bitfield.word
1338 && !t->operand_types[j].bitfield.word)
1339 || (i.types[j].bitfield.dword
1340 && !t->operand_types[j].bitfield.dword)
1341 || (i.types[j].bitfield.qword
1342 && !t->operand_types[j].bitfield.qword));
1343}
1344
1345/* Return 1 if there is no conflict in any size on operand J for
1346 instruction template T. */
1347
1348static INLINE int
1349match_mem_size (const template *t, unsigned int j)
1350{
1351 return (match_reg_size (t, j)
1352 && !((i.types[j].bitfield.unspecified
1353 && !t->operand_types[j].bitfield.unspecified)
1354 || (i.types[j].bitfield.fword
1355 && !t->operand_types[j].bitfield.fword)
1356 || (i.types[j].bitfield.tbyte
1357 && !t->operand_types[j].bitfield.tbyte)
1358 || (i.types[j].bitfield.xmmword
1359 && !t->operand_types[j].bitfield.xmmword)));
1360}
1361
1362/* Return 1 if there is no size conflict on any operands for
1363 instruction template T. */
1364
1365static INLINE int
1366operand_size_match (const template *t)
1367{
1368 unsigned int j;
1369 int match = 1;
1370
1371 /* Don't check jump instructions. */
1372 if (t->opcode_modifier.jump
1373 || t->opcode_modifier.jumpbyte
1374 || t->opcode_modifier.jumpdword
1375 || t->opcode_modifier.jumpintersegment)
1376 return match;
1377
1378 /* Check memory and accumulator operand size. */
1379 for (j = 0; j < i.operands; j++)
1380 {
1381 if (t->operand_types[j].bitfield.anysize)
1382 continue;
1383
1384 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1385 {
1386 match = 0;
1387 break;
1388 }
1389
1390 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1391 {
1392 match = 0;
1393 break;
1394 }
1395 }
1396
1397 if (match
1398 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1399 return match;
1400
1401 /* Check reverse. */
1402 assert (i.operands == 2);
1403
1404 match = 1;
1405 for (j = 0; j < 2; j++)
1406 {
1407 if (t->operand_types[j].bitfield.acc
1408 && !match_reg_size (t, j ? 0 : 1))
1409 {
1410 match = 0;
1411 break;
1412 }
1413
1414 if (i.types[j].bitfield.mem
1415 && !match_mem_size (t, j ? 0 : 1))
1416 {
1417 match = 0;
1418 break;
1419 }
1420 }
1421
1422 return match;
1423}
1424
c6fb90c8 1425static INLINE int
40fb9820
L		 1426operand_type_match (i386_operand_type overlap,
1427 i386_operand_type given)
1428{
1429 i386_operand_type temp = overlap;
1430
1431 temp.bitfield.jumpabsolute = 0;
7d5e4556 1432 temp.bitfield.unspecified = 0;
5c07affc
L		 1433 temp.bitfield.byte = 0;
1434 temp.bitfield.word = 0;
1435 temp.bitfield.dword = 0;
1436 temp.bitfield.fword = 0;
1437 temp.bitfield.qword = 0;
1438 temp.bitfield.tbyte = 0;
1439 temp.bitfield.xmmword = 0;
0dfbf9d7 1440 if (operand_type_all_zero (&temp))
40fb9820
L		 1441 return 0;
1442
1443 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1444 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1445}
1446
7d5e4556 1447/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1448 unless the expected operand type register overlap is null.
1449 Note that Acc in a template matches every size of reg. */
1450
c6fb90c8 1451static INLINE int
40fb9820
L		 1452operand_type_register_match (i386_operand_type m0,
1453 i386_operand_type g0,
1454 i386_operand_type t0,
1455 i386_operand_type m1,
1456 i386_operand_type g1,
1457 i386_operand_type t1)
1458{
1459 if (!operand_type_check (g0, reg))
1460 return 1;
1461
1462 if (!operand_type_check (g1, reg))
1463 return 1;
1464
1465 if (g0.bitfield.reg8 == g1.bitfield.reg8
1466 && g0.bitfield.reg16 == g1.bitfield.reg16
1467 && g0.bitfield.reg32 == g1.bitfield.reg32
1468 && g0.bitfield.reg64 == g1.bitfield.reg64)
1469 return 1;
1470
1471 if (m0.bitfield.acc)
1472 {
1473 t0.bitfield.reg8 = 1;
1474 t0.bitfield.reg16 = 1;
1475 t0.bitfield.reg32 = 1;
1476 t0.bitfield.reg64 = 1;
1477 }
1478
1479 if (m1.bitfield.acc)
1480 {
1481 t1.bitfield.reg8 = 1;
1482 t1.bitfield.reg16 = 1;
1483 t1.bitfield.reg32 = 1;
1484 t1.bitfield.reg64 = 1;
1485 }
1486
1487 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1488 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1489 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1490 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1491}
1492
252b5132 1493static INLINE unsigned int
40fb9820 1494mode_from_disp_size (i386_operand_type t)
252b5132 1495{
40fb9820
L		 1496 if (t.bitfield.disp8)
1497 return 1;
1498 else if (t.bitfield.disp16
1499 || t.bitfield.disp32
1500 || t.bitfield.disp32s)
1501 return 2;
1502 else
1503 return 0;
252b5132
RH		 1504}
1505
1506static INLINE int
e3bb37b5 1507fits_in_signed_byte (offsetT num)
252b5132
RH		 1508{
1509 return (num >= -128) && (num <= 127);
47926f60 1510}
252b5132
RH		 1511
1512static INLINE int
e3bb37b5 1513fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1514{
1515 return (num & 0xff) == num;
47926f60 1516}
252b5132
RH		 1517
1518static INLINE int
e3bb37b5 1519fits_in_unsigned_word (offsetT num)
252b5132
RH		 1520{
1521 return (num & 0xffff) == num;
47926f60 1522}
252b5132
RH		 1523
1524static INLINE int
e3bb37b5 1525fits_in_signed_word (offsetT num)
252b5132
RH		 1526{
1527 return (-32768 <= num) && (num <= 32767);
47926f60 1528}
2a962e6d 1529
3e73aa7c 1530static INLINE int
e3bb37b5 1531fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1532{
1533#ifndef BFD64
1534 return 1;
1535#else
1536 return (!(((offsetT) -1 << 31) & num)
1537 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1538#endif
1539} /* fits_in_signed_long() */
2a962e6d 1540
3e73aa7c 1541static INLINE int
e3bb37b5 1542fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1543{
1544#ifndef BFD64
1545 return 1;
1546#else
1547 return (num & (((offsetT) 2 << 31) - 1)) == num;
1548#endif
1549} /* fits_in_unsigned_long() */
252b5132 1550
40fb9820 1551static i386_operand_type
e3bb37b5 1552smallest_imm_type (offsetT num)
252b5132 1553{
40fb9820
L		 1554 i386_operand_type t;
1555
0dfbf9d7 1556 operand_type_set (&t, 0);
40fb9820
L		 1557 t.bitfield.imm64 = 1;
1558
1559 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1560 {
1561 /* This code is disabled on the 486 because all the Imm1 forms
1562 in the opcode table are slower on the i486. They're the
1563 versions with the implicitly specified single-position
1564 displacement, which has another syntax if you really want to
1565 use that form. */
40fb9820
L		 1566 t.bitfield.imm1 = 1;
1567 t.bitfield.imm8 = 1;
1568 t.bitfield.imm8s = 1;
1569 t.bitfield.imm16 = 1;
1570 t.bitfield.imm32 = 1;
1571 t.bitfield.imm32s = 1;
1572 }
1573 else if (fits_in_signed_byte (num))
1574 {
1575 t.bitfield.imm8 = 1;
1576 t.bitfield.imm8s = 1;
1577 t.bitfield.imm16 = 1;
1578 t.bitfield.imm32 = 1;
1579 t.bitfield.imm32s = 1;
1580 }
1581 else if (fits_in_unsigned_byte (num))
1582 {
1583 t.bitfield.imm8 = 1;
1584 t.bitfield.imm16 = 1;
1585 t.bitfield.imm32 = 1;
1586 t.bitfield.imm32s = 1;
1587 }
1588 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1589 {
1590 t.bitfield.imm16 = 1;
1591 t.bitfield.imm32 = 1;
1592 t.bitfield.imm32s = 1;
1593 }
1594 else if (fits_in_signed_long (num))
1595 {
1596 t.bitfield.imm32 = 1;
1597 t.bitfield.imm32s = 1;
1598 }
1599 else if (fits_in_unsigned_long (num))
1600 t.bitfield.imm32 = 1;
1601
1602 return t;
47926f60 1603}
252b5132 1604
847f7ad4 1605static offsetT
e3bb37b5 1606offset_in_range (offsetT val, int size)
847f7ad4 1607{
508866be 1608 addressT mask;
ba2adb93 1609
847f7ad4
AM		 1610 switch (size)
1611 {
508866be
L		 1612 case 1: mask = ((addressT) 1 << 8) - 1; break;
1613 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1614 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1615#ifdef BFD64
1616 case 8: mask = ((addressT) 2 << 63) - 1; break;
1617#endif
47926f60 1618 default: abort ();
847f7ad4
AM		 1619 }
1620
ba2adb93 1621 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1622 if (!use_rela_relocations)
1623 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1624 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1625
47926f60 1626 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1627 {
1628 char buf1[40], buf2[40];
1629
1630 sprint_value (buf1, val);
1631 sprint_value (buf2, val & mask);
1632 as_warn (_("%s shortened to %s"), buf1, buf2);
1633 }
1634 return val & mask;
1635}
1636
252b5132
RH		 1637/* Returns 0 if attempting to add a prefix where one from the same
1638 class already exists, 1 if non rep/repne added, 2 if rep/repne
1639 added. */
1640static int
e3bb37b5 1641add_prefix (unsigned int prefix)
252b5132
RH		 1642{
1643 int ret = 1;
b1905489 1644 unsigned int q;
252b5132 1645
29b0f896
AM		 1646 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1647 && flag_code == CODE_64BIT)
b1905489 1648 {
161a04f6
L		 1649 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1650 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1651 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1652 ret = 0;
1653 q = REX_PREFIX;
1654 }
3e73aa7c 1655 else
b1905489
JB		 1656 {
1657 switch (prefix)
1658 {
1659 default:
1660 abort ();
1661
1662 case CS_PREFIX_OPCODE:
1663 case DS_PREFIX_OPCODE:
1664 case ES_PREFIX_OPCODE:
1665 case FS_PREFIX_OPCODE:
1666 case GS_PREFIX_OPCODE:
1667 case SS_PREFIX_OPCODE:
1668 q = SEG_PREFIX;
1669 break;
1670
1671 case REPNE_PREFIX_OPCODE:
1672 case REPE_PREFIX_OPCODE:
1673 ret = 2;
1674 /* fall thru */
1675 case LOCK_PREFIX_OPCODE:
1676 q = LOCKREP_PREFIX;
1677 break;
1678
1679 case FWAIT_OPCODE:
1680 q = WAIT_PREFIX;
1681 break;
1682
1683 case ADDR_PREFIX_OPCODE:
1684 q = ADDR_PREFIX;
1685 break;
1686
1687 case DATA_PREFIX_OPCODE:
1688 q = DATA_PREFIX;
1689 break;
1690 }
1691 if (i.prefix[q] != 0)
1692 ret = 0;
1693 }
252b5132 1694
b1905489 1695 if (ret)
252b5132 1696 {
b1905489
JB		 1697 if (!i.prefix[q])
1698 ++i.prefixes;
1699 i.prefix[q] |= prefix;
252b5132 1700 }
b1905489
JB		 1701 else
1702 as_bad (_("same type of prefix used twice"));
252b5132 1703
252b5132
RH		 1704 return ret;
1705}
1706
1707static void
e3bb37b5 1708set_code_flag (int value)
eecb386c 1709{
3e73aa7c 1710 flag_code = value;
40fb9820
L		 1711 if (flag_code == CODE_64BIT)
1712 {
1713 cpu_arch_flags.bitfield.cpu64 = 1;
1714 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1715 }
1716 else
1717 {
1718 cpu_arch_flags.bitfield.cpu64 = 0;
1719 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1720 }
1721 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1722 {
1723 as_bad (_("64bit mode not supported on this CPU."));
1724 }
40fb9820 1725 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1726 {
1727 as_bad (_("32bit mode not supported on this CPU."));
1728 }
eecb386c
AM		 1729 stackop_size = '\0';
1730}
1731
1732static void
e3bb37b5 1733set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1734{
3e73aa7c 1735 flag_code = new_code_flag;
40fb9820
L		 1736 if (flag_code != CODE_16BIT)
1737 abort ();
1738 cpu_arch_flags.bitfield.cpu64 = 0;
1739 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1740 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1741}
1742
1743static void
e3bb37b5 1744set_intel_syntax (int syntax_flag)
252b5132
RH		 1745{
1746 /* Find out if register prefixing is specified. */
1747 int ask_naked_reg = 0;
1748
1749 SKIP_WHITESPACE ();
29b0f896 1750 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1751 {
1752 char *string = input_line_pointer;
1753 int e = get_symbol_end ();
1754
47926f60 1755 if (strcmp (string, "prefix") == 0)
252b5132 1756 ask_naked_reg = 1;
47926f60 1757 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1758 ask_naked_reg = -1;
1759 else
d0b47220 1760 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1761 *input_line_pointer = e;
1762 }
1763 demand_empty_rest_of_line ();
c3332e24 1764
252b5132
RH		 1765 intel_syntax = syntax_flag;
1766
1767 if (ask_naked_reg == 0)
f86103b7
AM		 1768 allow_naked_reg = (intel_syntax
1769 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1770 else
1771 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1772
e4a3b5a4 1773 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1774 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1775 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1776}
1777
1efbbeb4
L		 1778static void
1779set_intel_mnemonic (int mnemonic_flag)
1780{
e1d4d893 1781 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1782}
1783
db51cc60
L		 1784static void
1785set_allow_index_reg (int flag)
1786{
1787 allow_index_reg = flag;
1788}
1789
e413e4e9 1790static void
e3bb37b5 1791set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1792{
47926f60 1793 SKIP_WHITESPACE ();
e413e4e9 1794
29b0f896 1795 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1796 {
1797 char *string = input_line_pointer;
1798 int e = get_symbol_end ();
9103f4f4 1799 unsigned int i;
40fb9820 1800 i386_cpu_flags flags;
e413e4e9 1801
9103f4f4 1802 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1803 {
1804 if (strcmp (string, cpu_arch[i].name) == 0)
1805 {
5c6af06e
JB		 1806 if (*string != '.')
1807 {
1808 cpu_arch_name = cpu_arch[i].name;
1809 cpu_sub_arch_name = NULL;
40fb9820
L		 1810 cpu_arch_flags = cpu_arch[i].flags;
1811 if (flag_code == CODE_64BIT)
1812 {
1813 cpu_arch_flags.bitfield.cpu64 = 1;
1814 cpu_arch_flags.bitfield.cpuno64 = 0;
1815 }
1816 else
1817 {
1818 cpu_arch_flags.bitfield.cpu64 = 0;
1819 cpu_arch_flags.bitfield.cpuno64 = 1;
1820 }
ccc9c027 1821 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1822 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1823 if (!cpu_arch_tune_set)
1824 {
1825 cpu_arch_tune = cpu_arch_isa;
1826 cpu_arch_tune_flags = cpu_arch_isa_flags;
1827 }
5c6af06e
JB		 1828 break;
1829 }
40fb9820 1830
c6fb90c8
L		 1831 flags = cpu_flags_or (cpu_arch_flags,
1832 cpu_arch[i].flags);
0dfbf9d7 1833 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 1834 {
6305a203
L		 1835 if (cpu_sub_arch_name)
1836 {
1837 char *name = cpu_sub_arch_name;
1838 cpu_sub_arch_name = concat (name,
1839 cpu_arch[i].name,
1bf57e9f 1840 (const char *) NULL);
6305a203
L		 1841 free (name);
1842 }
1843 else
1844 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
40fb9820 1845 cpu_arch_flags = flags;
5c6af06e
JB		 1846 }
1847 *input_line_pointer = e;
1848 demand_empty_rest_of_line ();
1849 return;
e413e4e9
AM		 1850 }
1851 }
9103f4f4 1852 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1853 as_bad (_("no such architecture: `%s'"), string);
1854
1855 *input_line_pointer = e;
1856 }
1857 else
1858 as_bad (_("missing cpu architecture"));
1859
fddf5b5b
AM		 1860 no_cond_jump_promotion = 0;
1861 if (*input_line_pointer == ','
29b0f896 1862 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1863 {
1864 char *string = ++input_line_pointer;
1865 int e = get_symbol_end ();
1866
1867 if (strcmp (string, "nojumps") == 0)
1868 no_cond_jump_promotion = 1;
1869 else if (strcmp (string, "jumps") == 0)
1870 ;
1871 else
1872 as_bad (_("no such architecture modifier: `%s'"), string);
1873
1874 *input_line_pointer = e;
1875 }
1876
e413e4e9
AM		 1877 demand_empty_rest_of_line ();
1878}
1879
b9d79e03
JH		 1880unsigned long
1881i386_mach ()
1882{
1883 if (!strcmp (default_arch, "x86_64"))
1884 return bfd_mach_x86_64;
1885 else if (!strcmp (default_arch, "i386"))
1886 return bfd_mach_i386_i386;
1887 else
1888 as_fatal (_("Unknown architecture"));
1889}
b9d79e03 1890\f
252b5132
RH		 1891void
1892md_begin ()
1893{
1894 const char *hash_err;
1895
47926f60 1896 /* Initialize op_hash hash table. */
252b5132
RH		 1897 op_hash = hash_new ();
1898
1899 {
29b0f896
AM		 1900 const template *optab;
1901 templates *core_optab;
252b5132 1902
47926f60
KH		 1903 /* Setup for loop. */
1904 optab = i386_optab;
252b5132
RH		 1905 core_optab = (templates *) xmalloc (sizeof (templates));
1906 core_optab->start = optab;
1907
1908 while (1)
1909 {
1910 ++optab;
1911 if (optab->name == NULL
1912 || strcmp (optab->name, (optab - 1)->name) != 0)
1913 {
1914 /* different name --> ship out current template list;
47926f60 1915 add to hash table; & begin anew. */
252b5132
RH		 1916 core_optab->end = optab;
1917 hash_err = hash_insert (op_hash,
1918 (optab - 1)->name,
1919 (PTR) core_optab);
1920 if (hash_err)
1921 {
252b5132
RH		 1922 as_fatal (_("Internal Error: Can't hash %s: %s"),
1923 (optab - 1)->name,
1924 hash_err);
1925 }
1926 if (optab->name == NULL)
1927 break;
1928 core_optab = (templates *) xmalloc (sizeof (templates));
1929 core_optab->start = optab;
1930 }
1931 }
1932 }
1933
47926f60 1934 /* Initialize reg_hash hash table. */
252b5132
RH		 1935 reg_hash = hash_new ();
1936 {
29b0f896 1937 const reg_entry *regtab;
c3fe08fa 1938 unsigned int regtab_size = i386_regtab_size;
252b5132 1939
c3fe08fa 1940 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132
RH		 1941 {
1942 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1943 if (hash_err)
3e73aa7c
JH		 1944 as_fatal (_("Internal Error: Can't hash %s: %s"),
1945 regtab->reg_name,
1946 hash_err);
252b5132
RH		 1947 }
1948 }
1949
47926f60 1950 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1951 {
29b0f896
AM		 1952 int c;
1953 char *p;
252b5132
RH		 1954
1955 for (c = 0; c < 256; c++)
1956 {
3882b010 1957 if (ISDIGIT (c))
252b5132
RH		 1958 {
1959 digit_chars[c] = c;
1960 mnemonic_chars[c] = c;
1961 register_chars[c] = c;
1962 operand_chars[c] = c;
1963 }
3882b010 1964 else if (ISLOWER (c))
252b5132
RH		 1965 {
1966 mnemonic_chars[c] = c;
1967 register_chars[c] = c;
1968 operand_chars[c] = c;
1969 }
3882b010 1970 else if (ISUPPER (c))
252b5132 1971 {
3882b010 1972 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1973 register_chars[c] = mnemonic_chars[c];
1974 operand_chars[c] = c;
1975 }
1976
3882b010 1977 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1978 identifier_chars[c] = c;
1979 else if (c >= 128)
1980 {
1981 identifier_chars[c] = c;
1982 operand_chars[c] = c;
1983 }
1984 }
1985
1986#ifdef LEX_AT
1987 identifier_chars['@'] = '@';
32137342
NC		 1988#endif
1989#ifdef LEX_QM
1990 identifier_chars['?'] = '?';
1991 operand_chars['?'] = '?';
252b5132 1992#endif
252b5132 1993 digit_chars['-'] = '-';
791fe849 1994 mnemonic_chars['-'] = '-';
0003779b 1995 mnemonic_chars['.'] = '.';
252b5132
RH		 1996 identifier_chars['_'] = '_';
1997 identifier_chars['.'] = '.';
1998
1999 for (p = operand_special_chars; *p != '\0'; p++)
2000 operand_chars[(unsigned char) *p] = *p;
2001 }
2002
2003#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2004 if (IS_ELF)
252b5132
RH		 2005 {
2006 record_alignment (text_section, 2);
2007 record_alignment (data_section, 2);
2008 record_alignment (bss_section, 2);
2009 }
2010#endif
a4447b93
RH		 2011
2012 if (flag_code == CODE_64BIT)
2013 {
2014 x86_dwarf2_return_column = 16;
2015 x86_cie_data_alignment = -8;
2016 }
2017 else
2018 {
2019 x86_dwarf2_return_column = 8;
2020 x86_cie_data_alignment = -4;
2021 }
252b5132
RH		 2022}
2023
2024void
e3bb37b5 2025i386_print_statistics (FILE *file)
252b5132
RH		 2026{
2027 hash_print_statistics (file, "i386 opcode", op_hash);
2028 hash_print_statistics (file, "i386 register", reg_hash);
2029}
2030\f
252b5132
RH		 2031#ifdef DEBUG386
2032
ce8a8b2f 2033/* Debugging routines for md_assemble. */
e3bb37b5 2034static void pte (template *);
40fb9820 2035static void pt (i386_operand_type);
e3bb37b5
L		 2036static void pe (expressionS *);
2037static void ps (symbolS *);
252b5132
RH		 2038
2039static void
e3bb37b5 2040pi (char *line, i386_insn *x)
252b5132 2041{
09f131f2 2042 unsigned int i;
252b5132
RH		 2043
2044 fprintf (stdout, "%s: template ", line);
2045 pte (&x->tm);
09f131f2
JH		 2046 fprintf (stdout, " address: base %s index %s scale %x\n",
2047 x->base_reg ? x->base_reg->reg_name : "none",
2048 x->index_reg ? x->index_reg->reg_name : "none",
2049 x->log2_scale_factor);
2050 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2051 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2052 fprintf (stdout, " sib: base %x index %x scale %x\n",
2053 x->sib.base, x->sib.index, x->sib.scale);
2054 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2055 (x->rex & REX_W) != 0,
2056 (x->rex & REX_R) != 0,
2057 (x->rex & REX_X) != 0,
2058 (x->rex & REX_B) != 0);
85f10a01
MM		 2059 fprintf (stdout, " drex: reg %d rex 0x%x\n",
2060 x->drex.reg, x->drex.rex);
252b5132
RH		 2061 for (i = 0; i < x->operands; i++)
2062 {
2063 fprintf (stdout, " #%d: ", i + 1);
2064 pt (x->types[i]);
2065 fprintf (stdout, "\n");
40fb9820
L		 2066 if (x->types[i].bitfield.reg8
2067 || x->types[i].bitfield.reg16
2068 || x->types[i].bitfield.reg32
2069 || x->types[i].bitfield.reg64
2070 || x->types[i].bitfield.regmmx
2071 || x->types[i].bitfield.regxmm
2072 || x->types[i].bitfield.sreg2
2073 || x->types[i].bitfield.sreg3
2074 || x->types[i].bitfield.control
2075 || x->types[i].bitfield.debug
2076 || x->types[i].bitfield.test)
520dc8e8 2077 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 2078 if (operand_type_check (x->types[i], imm))
520dc8e8 2079 pe (x->op[i].imms);
40fb9820 2080 if (operand_type_check (x->types[i], disp))
520dc8e8 2081 pe (x->op[i].disps);
252b5132
RH		 2082 }
2083}
2084
2085static void
e3bb37b5 2086pte (template *t)
252b5132 2087{
09f131f2 2088 unsigned int i;
252b5132 2089 fprintf (stdout, " %d operands ", t->operands);
47926f60 2090 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2091 if (t->extension_opcode != None)
2092 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2093 if (t->opcode_modifier.d)
252b5132 2094 fprintf (stdout, "D");
40fb9820 2095 if (t->opcode_modifier.w)
252b5132
RH		 2096 fprintf (stdout, "W");
2097 fprintf (stdout, "\n");
2098 for (i = 0; i < t->operands; i++)
2099 {
2100 fprintf (stdout, " #%d type ", i + 1);
2101 pt (t->operand_types[i]);
2102 fprintf (stdout, "\n");
2103 }
2104}
2105
2106static void
e3bb37b5 2107pe (expressionS *e)
252b5132 2108{
24eab124 2109 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2110 fprintf (stdout, " add_number %ld (%lx)\n",
2111 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2112 if (e->X_add_symbol)
2113 {
2114 fprintf (stdout, " add_symbol ");
2115 ps (e->X_add_symbol);
2116 fprintf (stdout, "\n");
2117 }
2118 if (e->X_op_symbol)
2119 {
2120 fprintf (stdout, " op_symbol ");
2121 ps (e->X_op_symbol);
2122 fprintf (stdout, "\n");
2123 }
2124}
2125
2126static void
e3bb37b5 2127ps (symbolS *s)
252b5132
RH		 2128{
2129 fprintf (stdout, "%s type %s%s",
2130 S_GET_NAME (s),
2131 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2132 segment_name (S_GET_SEGMENT (s)));
2133}
2134
7b81dfbb 2135static struct type_name
252b5132 2136 {
40fb9820
L		 2137 i386_operand_type mask;
2138 const char *name;
252b5132 2139 }
7b81dfbb 2140const type_names[] =
252b5132 2141{
40fb9820
L		 2142 { OPERAND_TYPE_REG8, "r8" },
2143 { OPERAND_TYPE_REG16, "r16" },
2144 { OPERAND_TYPE_REG32, "r32" },
2145 { OPERAND_TYPE_REG64, "r64" },
2146 { OPERAND_TYPE_IMM8, "i8" },
2147 { OPERAND_TYPE_IMM8, "i8s" },
2148 { OPERAND_TYPE_IMM16, "i16" },
2149 { OPERAND_TYPE_IMM32, "i32" },
2150 { OPERAND_TYPE_IMM32S, "i32s" },
2151 { OPERAND_TYPE_IMM64, "i64" },
2152 { OPERAND_TYPE_IMM1, "i1" },
2153 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2154 { OPERAND_TYPE_DISP8, "d8" },
2155 { OPERAND_TYPE_DISP16, "d16" },
2156 { OPERAND_TYPE_DISP32, "d32" },
2157 { OPERAND_TYPE_DISP32S, "d32s" },
2158 { OPERAND_TYPE_DISP64, "d64" },
2159 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2160 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2161 { OPERAND_TYPE_CONTROL, "control reg" },
2162 { OPERAND_TYPE_TEST, "test reg" },
2163 { OPERAND_TYPE_DEBUG, "debug reg" },
2164 { OPERAND_TYPE_FLOATREG, "FReg" },
2165 { OPERAND_TYPE_FLOATACC, "FAcc" },
2166 { OPERAND_TYPE_SREG2, "SReg2" },
2167 { OPERAND_TYPE_SREG3, "SReg3" },
2168 { OPERAND_TYPE_ACC, "Acc" },
2169 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2170 { OPERAND_TYPE_REGMMX, "rMMX" },
2171 { OPERAND_TYPE_REGXMM, "rXMM" },
2172 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2173};
2174
2175static void
40fb9820 2176pt (i386_operand_type t)
252b5132 2177{
40fb9820 2178 unsigned int j;
c6fb90c8 2179 i386_operand_type a;
252b5132 2180
40fb9820 2181 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2182 {
2183 a = operand_type_and (t, type_names[j].mask);
2184 if (!UINTS_ALL_ZERO (a))
2185 fprintf (stdout, "%s, ", type_names[j].name);
2186 }
252b5132
RH		 2187 fflush (stdout);
2188}
2189
2190#endif /* DEBUG386 */
2191\f
252b5132 2192static bfd_reloc_code_real_type
3956db08 2193reloc (unsigned int size,
64e74474
AM		 2194 int pcrel,
2195 int sign,
2196 bfd_reloc_code_real_type other)
252b5132 2197{
47926f60 2198 if (other != NO_RELOC)
3956db08
JB		 2199 {
2200 reloc_howto_type *reloc;
2201
2202 if (size == 8)
2203 switch (other)
2204 {
64e74474
AM		 2205 case BFD_RELOC_X86_64_GOT32:
2206 return BFD_RELOC_X86_64_GOT64;
2207 break;
2208 case BFD_RELOC_X86_64_PLTOFF64:
2209 return BFD_RELOC_X86_64_PLTOFF64;
2210 break;
2211 case BFD_RELOC_X86_64_GOTPC32:
2212 other = BFD_RELOC_X86_64_GOTPC64;
2213 break;
2214 case BFD_RELOC_X86_64_GOTPCREL:
2215 other = BFD_RELOC_X86_64_GOTPCREL64;
2216 break;
2217 case BFD_RELOC_X86_64_TPOFF32:
2218 other = BFD_RELOC_X86_64_TPOFF64;
2219 break;
2220 case BFD_RELOC_X86_64_DTPOFF32:
2221 other = BFD_RELOC_X86_64_DTPOFF64;
2222 break;
2223 default:
2224 break;
3956db08 2225 }
e05278af
JB		 2226
2227 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2228 if (size == 4 && flag_code != CODE_64BIT)
2229 sign = -1;
2230
3956db08
JB		 2231 reloc = bfd_reloc_type_lookup (stdoutput, other);
2232 if (!reloc)
2233 as_bad (_("unknown relocation (%u)"), other);
2234 else if (size != bfd_get_reloc_size (reloc))
2235 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2236 bfd_get_reloc_size (reloc),
2237 size);
2238 else if (pcrel && !reloc->pc_relative)
2239 as_bad (_("non-pc-relative relocation for pc-relative field"));
2240 else if ((reloc->complain_on_overflow == complain_overflow_signed
2241 && !sign)
2242 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 2243 && sign > 0))
3956db08
JB		 2244 as_bad (_("relocated field and relocation type differ in signedness"));
2245 else
2246 return other;
2247 return NO_RELOC;
2248 }
252b5132
RH		 2249
2250 if (pcrel)
2251 {
3e73aa7c 2252 if (!sign)
3956db08 2253 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2254 switch (size)
2255 {
2256 case 1: return BFD_RELOC_8_PCREL;
2257 case 2: return BFD_RELOC_16_PCREL;
2258 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2259 case 8: return BFD_RELOC_64_PCREL;
252b5132 2260 }
3956db08 2261 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2262 }
2263 else
2264 {
3956db08 2265 if (sign > 0)
e5cb08ac 2266 switch (size)
3e73aa7c
JH		 2267 {
2268 case 4: return BFD_RELOC_X86_64_32S;
2269 }
2270 else
2271 switch (size)
2272 {
2273 case 1: return BFD_RELOC_8;
2274 case 2: return BFD_RELOC_16;
2275 case 4: return BFD_RELOC_32;
2276 case 8: return BFD_RELOC_64;
2277 }
3956db08
JB		 2278 as_bad (_("cannot do %s %u byte relocation"),
2279 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2280 }
2281
bfb32b52 2282 abort ();
252b5132
RH		 2283 return BFD_RELOC_NONE;
2284}
2285
47926f60
KH		 2286/* Here we decide which fixups can be adjusted to make them relative to
2287 the beginning of the section instead of the symbol. Basically we need
2288 to make sure that the dynamic relocations are done correctly, so in
2289 some cases we force the original symbol to be used. */
2290
252b5132 2291int
e3bb37b5 2292tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2293{
6d249963 2294#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2295 if (!IS_ELF)
31312f95
AM		 2296 return 1;
2297
a161fe53
AM		 2298 /* Don't adjust pc-relative references to merge sections in 64-bit
2299 mode. */
2300 if (use_rela_relocations
2301 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2302 && fixP->fx_pcrel)
252b5132 2303 return 0;
31312f95 2304
8d01d9a9
AJ		 2305 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2306 and changed later by validate_fix. */
2307 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2308 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2309 return 0;
2310
ce8a8b2f 2311 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2312 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2313 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2314 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2315 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2316 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2317 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2318 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2319 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2320 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2321 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2322 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2323 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2324 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2325 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2326 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2327 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2328 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2329 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2330 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2331 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2332 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2333 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2334 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2335 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2336 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2337 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2338 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2339 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2340 return 0;
31312f95 2341#endif
252b5132
RH		 2342 return 1;
2343}
252b5132 2344
b4cac588 2345static int
e3bb37b5 2346intel_float_operand (const char *mnemonic)
252b5132 2347{
9306ca4a
JB		 2348 /* Note that the value returned is meaningful only for opcodes with (memory)
2349 operands, hence the code here is free to improperly handle opcodes that
2350 have no operands (for better performance and smaller code). */
2351
2352 if (mnemonic[0] != 'f')
2353 return 0; /* non-math */
2354
2355 switch (mnemonic[1])
2356 {
2357 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2358 the fs segment override prefix not currently handled because no
2359 call path can make opcodes without operands get here */
2360 case 'i':
2361 return 2 /* integer op */;
2362 case 'l':
2363 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2364 return 3; /* fldcw/fldenv */
2365 break;
2366 case 'n':
2367 if (mnemonic[2] != 'o' /* fnop */)
2368 return 3; /* non-waiting control op */
2369 break;
2370 case 'r':
2371 if (mnemonic[2] == 's')
2372 return 3; /* frstor/frstpm */
2373 break;
2374 case 's':
2375 if (mnemonic[2] == 'a')
2376 return 3; /* fsave */
2377 if (mnemonic[2] == 't')
2378 {
2379 switch (mnemonic[3])
2380 {
2381 case 'c': /* fstcw */
2382 case 'd': /* fstdw */
2383 case 'e': /* fstenv */
2384 case 's': /* fsts[gw] */
2385 return 3;
2386 }
2387 }
2388 break;
2389 case 'x':
2390 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2391 return 0; /* fxsave/fxrstor are not really math ops */
2392 break;
2393 }
252b5132 2394
9306ca4a 2395 return 1;
252b5132
RH		 2396}
2397
65da13b5
L		 2398static void
2399process_immext (void)
2400{
2401 expressionS *exp;
2402
2403 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2404 {
2405 /* SSE3 Instructions have the fixed operands with an opcode
2406 suffix which is coded in the same place as an 8-bit immediate
2407 field would be. Here we check those operands and remove them
2408 afterwards. */
2409 unsigned int x;
2410
2411 for (x = 0; x < i.operands; x++)
2412 if (i.op[x].regs->reg_num != x)
2413 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2414 register_prefix,
2415 i.op[x].regs->reg_name,
2416 x + 1,
2417
2418 i.tm.name); i.operands = 0;
2419 }
2420
2421 /* These AMD 3DNow! and SSE2 Instructions have an opcode suffix
2422 which is coded in the same place as an 8-bit immediate field
2423 would be. Here we fake an 8-bit immediate operand from the
2424 opcode suffix stored in tm.extension_opcode.
2425
2426 SSE5 also uses this encoding, for some of its 3 argument
2427 instructions. */
2428
2429 assert (i.imm_operands == 0
2430 && (i.operands <= 2
2431 || (i.tm.cpu_flags.bitfield.cpusse5
2432 && i.operands <= 3)));
2433
2434 exp = &im_expressions[i.imm_operands++];
2435 i.op[i.operands].imms = exp;
2436 i.types[i.operands] = imm8;
2437 i.operands++;
2438 exp->X_op = O_constant;
2439 exp->X_add_number = i.tm.extension_opcode;
2440 i.tm.extension_opcode = None;
2441}
2442
252b5132
RH		 2443/* This is the guts of the machine-dependent assembler. LINE points to a
2444 machine dependent instruction. This function is supposed to emit
2445 the frags/bytes it assembles to. */
2446
2447void
65da13b5 2448md_assemble (char *line)
252b5132 2449{
40fb9820 2450 unsigned int j;
252b5132
RH		 2451 char mnemonic[MAX_MNEM_SIZE];
2452
47926f60 2453 /* Initialize globals. */
252b5132
RH		 2454 memset (&i, '\0', sizeof (i));
2455 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2456 i.reloc[j] = NO_RELOC;
252b5132
RH		 2457 memset (disp_expressions, '\0', sizeof (disp_expressions));
2458 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2459 save_stack_p = save_stack;
252b5132
RH		 2460
2461 /* First parse an instruction mnemonic & call i386_operand for the operands.
2462 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2463 start of a (possibly prefixed) mnemonic. */
252b5132 2464
29b0f896
AM		 2465 line = parse_insn (line, mnemonic);
2466 if (line == NULL)
2467 return;
252b5132 2468
29b0f896
AM		 2469 line = parse_operands (line, mnemonic);
2470 if (line == NULL)
2471 return;
252b5132 2472
29b0f896
AM		 2473 /* Now we've parsed the mnemonic into a set of templates, and have the
2474 operands at hand. */
2475
2476 /* All intel opcodes have reversed operands except for "bound" and
2477 "enter". We also don't reverse intersegment "jmp" and "call"
2478 instructions with 2 immediate operands so that the immediate segment
050dfa73 2479 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2480 if (intel_syntax
2481 && i.operands > 1
29b0f896 2482 && (strcmp (mnemonic, "bound") != 0)
30123838 2483 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2484 && !(operand_type_check (i.types[0], imm)
2485 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2486 swap_operands ();
2487
ec56d5c0
JB		 2488 /* The order of the immediates should be reversed
2489 for 2 immediates extrq and insertq instructions */
2490 if (i.imm_operands == 2
2491 && (strcmp (mnemonic, "extrq") == 0
2492 || strcmp (mnemonic, "insertq") == 0))
2493 swap_2_operands (0, 1);
2494
29b0f896
AM		 2495 if (i.imm_operands)
2496 optimize_imm ();
2497
b300c311
L		 2498 /* Don't optimize displacement for movabs since it only takes 64bit
2499 displacement. */
2500 if (i.disp_operands
2501 && (flag_code != CODE_64BIT
2502 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2503 optimize_disp ();
2504
2505 /* Next, we find a template that matches the given insn,
2506 making sure the overlap of the given operands types is consistent
2507 with the template operand types. */
252b5132 2508
29b0f896
AM		 2509 if (!match_template ())
2510 return;
252b5132 2511
321fd21e
L		 2512 /* Zap movzx and movsx suffix. The suffix has been set from
2513 "word ptr" or "byte ptr" on the source operand in Intel syntax
2514 or extracted from mnemonic in AT&T syntax. But we'll use
2515 the destination register to choose the suffix for encoding. */
2516 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 2517 {
321fd21e
L		 2518 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2519 there is no suffix, the default will be byte extension. */
2520 if (i.reg_operands != 2
2521 && !i.suffix
2522 && intel_syntax)
2523 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2524
2525 i.suffix = 0;
cd61ebfe 2526 }
24eab124 2527
40fb9820 2528 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2529 if (!add_prefix (FWAIT_OPCODE))
2530 return;
252b5132 2531
29b0f896 2532 /* Check string instruction segment overrides. */
40fb9820 2533 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2534 {
2535 if (!check_string ())
5dd0794d 2536 return;
29b0f896 2537 }
5dd0794d 2538
29b0f896
AM		 2539 if (!process_suffix ())
2540 return;
e413e4e9 2541
29b0f896
AM		 2542 /* Make still unresolved immediate matches conform to size of immediate
2543 given in i.suffix. */
2544 if (!finalize_imm ())
2545 return;
252b5132 2546
40fb9820 2547 if (i.types[0].bitfield.imm1)
29b0f896 2548 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2549
40fb9820 2550 for (j = 0; j < 3; j++)
c6fb90c8
L		 2551 if (i.types[j].bitfield.inoutportreg
2552 || i.types[j].bitfield.shiftcount
2553 || i.types[j].bitfield.acc
2554 || i.types[j].bitfield.floatacc)
40fb9820
L		 2555 i.reg_operands--;
2556
2557 if (i.tm.opcode_modifier.immext)
65da13b5 2558 process_immext ();
252b5132 2559
29b0f896
AM		 2560 /* For insns with operands there are more diddles to do to the opcode. */
2561 if (i.operands)
2562 {
2563 if (!process_operands ())
2564 return;
2565 }
40fb9820 2566 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2567 {
2568 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2569 as_warn (_("translating to `%sp'"), i.tm.name);
2570 }
252b5132 2571
29b0f896
AM		 2572 /* Handle conversion of 'int $3' --> special int3 insn. */
2573 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2574 {
2575 i.tm.base_opcode = INT3_OPCODE;
2576 i.imm_operands = 0;
2577 }
252b5132 2578
40fb9820
L		 2579 if ((i.tm.opcode_modifier.jump
2580 || i.tm.opcode_modifier.jumpbyte
2581 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2582 && i.op[0].disps->X_op == O_constant)
2583 {
2584 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2585 the absolute address given by the constant. Since ix86 jumps and
2586 calls are pc relative, we need to generate a reloc. */
2587 i.op[0].disps->X_add_symbol = &abs_symbol;
2588 i.op[0].disps->X_op = O_symbol;
2589 }
252b5132 2590
40fb9820 2591 if (i.tm.opcode_modifier.rex64)
161a04f6 2592 i.rex |= REX_W;
252b5132 2593
29b0f896
AM		 2594 /* For 8 bit registers we need an empty rex prefix. Also if the
2595 instruction already has a prefix, we need to convert old
2596 registers to new ones. */
773f551c 2597
40fb9820 2598 if ((i.types[0].bitfield.reg8
29b0f896 2599 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2600 || (i.types[1].bitfield.reg8
29b0f896 2601 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2602 || ((i.types[0].bitfield.reg8
2603 || i.types[1].bitfield.reg8)
29b0f896
AM		 2604 && i.rex != 0))
2605 {
2606 int x;
726c5dcd 2607
29b0f896
AM		 2608 i.rex |= REX_OPCODE;
2609 for (x = 0; x < 2; x++)
2610 {
2611 /* Look for 8 bit operand that uses old registers. */
40fb9820 2612 if (i.types[x].bitfield.reg8
29b0f896 2613 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2614 {
29b0f896
AM		 2615 /* In case it is "hi" register, give up. */
2616 if (i.op[x].regs->reg_num > 3)
a540244d 2617 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2618 "instruction requiring REX prefix."),
a540244d 2619 register_prefix, i.op[x].regs->reg_name);
773f551c 2620
29b0f896
AM		 2621 /* Otherwise it is equivalent to the extended register.
2622 Since the encoding doesn't change this is merely
2623 cosmetic cleanup for debug output. */
2624
2625 i.op[x].regs = i.op[x].regs + 8;
773f551c 2626 }
29b0f896
AM		 2627 }
2628 }
773f551c 2629
85f10a01
MM		 2630 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2631 REX prefix. */
2632 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2633 {
2634 i.drex.rex = i.rex;
2635 i.rex = 0;
2636 }
2637 else if (i.rex != 0)
29b0f896
AM		 2638 add_prefix (REX_OPCODE | i.rex);
2639
2640 /* We are ready to output the insn. */
2641 output_insn ();
2642}
2643
2644static char *
e3bb37b5 2645parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2646{
2647 char *l = line;
2648 char *token_start = l;
2649 char *mnem_p;
5c6af06e
JB		 2650 int supported;
2651 const template *t;
29b0f896
AM		 2652
2653 /* Non-zero if we found a prefix only acceptable with string insns. */
2654 const char *expecting_string_instruction = NULL;
45288df1 2655
29b0f896
AM		 2656 while (1)
2657 {
2658 mnem_p = mnemonic;
2659 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2660 {
2661 mnem_p++;
2662 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2663 {
29b0f896
AM		 2664 as_bad (_("no such instruction: `%s'"), token_start);
2665 return NULL;
2666 }
2667 l++;
2668 }
2669 if (!is_space_char (*l)
2670 && *l != END_OF_INSN
e44823cf
JB		 2671 && (intel_syntax
2672 || (*l != PREFIX_SEPARATOR
2673 && *l != ',')))
29b0f896
AM		 2674 {
2675 as_bad (_("invalid character %s in mnemonic"),
2676 output_invalid (*l));
2677 return NULL;
2678 }
2679 if (token_start == l)
2680 {
e44823cf 2681 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2682 as_bad (_("expecting prefix; got nothing"));
2683 else
2684 as_bad (_("expecting mnemonic; got nothing"));
2685 return NULL;
2686 }
45288df1 2687
29b0f896
AM		 2688 /* Look up instruction (or prefix) via hash table. */
2689 current_templates = hash_find (op_hash, mnemonic);
47926f60 2690
29b0f896
AM		 2691 if (*l != END_OF_INSN
2692 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2693 && current_templates
40fb9820 2694 && current_templates->start->opcode_modifier.isprefix)
29b0f896 2695 {
c6fb90c8 2696 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 2697 {
2698 as_bad ((flag_code != CODE_64BIT
2699 ? _("`%s' is only supported in 64-bit mode")
2700 : _("`%s' is not supported in 64-bit mode")),
2701 current_templates->start->name);
2702 return NULL;
2703 }
29b0f896
AM		 2704 /* If we are in 16-bit mode, do not allow addr16 or data16.
2705 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 2706 if ((current_templates->start->opcode_modifier.size16
2707 || current_templates->start->opcode_modifier.size32)
29b0f896 2708 && flag_code != CODE_64BIT
40fb9820 2709 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 2710 ^ (flag_code == CODE_16BIT)))
2711 {
2712 as_bad (_("redundant %s prefix"),
2713 current_templates->start->name);
2714 return NULL;
45288df1 2715 }
29b0f896
AM		 2716 /* Add prefix, checking for repeated prefixes. */
2717 switch (add_prefix (current_templates->start->base_opcode))
2718 {
2719 case 0:
2720 return NULL;
2721 case 2:
2722 expecting_string_instruction = current_templates->start->name;
2723 break;
2724 }
2725 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2726 token_start = ++l;
2727 }
2728 else
2729 break;
2730 }
45288df1 2731
29b0f896
AM		 2732 if (!current_templates)
2733 {
2734 /* See if we can get a match by trimming off a suffix. */
2735 switch (mnem_p[-1])
2736 {
2737 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2738 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2739 i.suffix = SHORT_MNEM_SUFFIX;
2740 else
29b0f896
AM		 2741 case BYTE_MNEM_SUFFIX:
2742 case QWORD_MNEM_SUFFIX:
2743 i.suffix = mnem_p[-1];
2744 mnem_p[-1] = '\0';
2745 current_templates = hash_find (op_hash, mnemonic);
2746 break;
2747 case SHORT_MNEM_SUFFIX:
2748 case LONG_MNEM_SUFFIX:
2749 if (!intel_syntax)
2750 {
2751 i.suffix = mnem_p[-1];
2752 mnem_p[-1] = '\0';
2753 current_templates = hash_find (op_hash, mnemonic);
2754 }
2755 break;
252b5132 2756
29b0f896
AM		 2757 /* Intel Syntax. */
2758 case 'd':
2759 if (intel_syntax)
2760 {
9306ca4a 2761 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2762 i.suffix = SHORT_MNEM_SUFFIX;
2763 else
2764 i.suffix = LONG_MNEM_SUFFIX;
2765 mnem_p[-1] = '\0';
2766 current_templates = hash_find (op_hash, mnemonic);
2767 }
2768 break;
2769 }
2770 if (!current_templates)
2771 {
2772 as_bad (_("no such instruction: `%s'"), token_start);
2773 return NULL;
2774 }
2775 }
252b5132 2776
40fb9820
L		 2777 if (current_templates->start->opcode_modifier.jump
2778 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 2779 {
2780 /* Check for a branch hint. We allow ",pt" and ",pn" for
2781 predict taken and predict not taken respectively.
2782 I'm not sure that branch hints actually do anything on loop
2783 and jcxz insns (JumpByte) for current Pentium4 chips. They
2784 may work in the future and it doesn't hurt to accept them
2785 now. */
2786 if (l[0] == ',' && l[1] == 'p')
2787 {
2788 if (l[2] == 't')
2789 {
2790 if (!add_prefix (DS_PREFIX_OPCODE))
2791 return NULL;
2792 l += 3;
2793 }
2794 else if (l[2] == 'n')
2795 {
2796 if (!add_prefix (CS_PREFIX_OPCODE))
2797 return NULL;
2798 l += 3;
2799 }
2800 }
2801 }
2802 /* Any other comma loses. */
2803 if (*l == ',')
2804 {
2805 as_bad (_("invalid character %s in mnemonic"),
2806 output_invalid (*l));
2807 return NULL;
2808 }
252b5132 2809
29b0f896 2810 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2811 supported = 0;
2812 for (t = current_templates->start; t < current_templates->end; ++t)
2813 {
3629bb00
L		 2814 supported |= cpu_flags_match (t->cpu_flags);
2815 if (supported == 3)
2816 goto skip;
5c6af06e 2817 }
3629bb00 2818
5c6af06e
JB		 2819 if (!(supported & 2))
2820 {
2821 as_bad (flag_code == CODE_64BIT
2822 ? _("`%s' is not supported in 64-bit mode")
2823 : _("`%s' is only supported in 64-bit mode"),
2824 current_templates->start->name);
2825 return NULL;
2826 }
2827 if (!(supported & 1))
29b0f896 2828 {
3629bb00
L		 2829 as_bad (_("`%s' is not supported on `%s%s'"),
2830 current_templates->start->name, cpu_arch_name,
2831 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2832 return NULL;
29b0f896 2833 }
3629bb00
L		 2834
2835skip:
2836 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 2837 && (flag_code != CODE_16BIT))
29b0f896
AM		 2838 {
2839 as_warn (_("use .code16 to ensure correct addressing mode"));
2840 }
252b5132 2841
29b0f896 2842 /* Check for rep/repne without a string instruction. */
f41bbced 2843 if (expecting_string_instruction)
29b0f896 2844 {
f41bbced
JB		 2845 static templates override;
2846
2847 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 2848 if (t->opcode_modifier.isstring)
f41bbced
JB		 2849 break;
2850 if (t >= current_templates->end)
2851 {
2852 as_bad (_("expecting string instruction after `%s'"),
64e74474 2853 expecting_string_instruction);
f41bbced
JB		 2854 return NULL;
2855 }
2856 for (override.start = t; t < current_templates->end; ++t)
40fb9820 2857 if (!t->opcode_modifier.isstring)
f41bbced
JB		 2858 break;
2859 override.end = t;
2860 current_templates = &override;
29b0f896 2861 }
252b5132 2862
29b0f896
AM		 2863 return l;
2864}
252b5132 2865
29b0f896 2866static char *
e3bb37b5 2867parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 2868{
2869 char *token_start;
3138f287 2870
29b0f896
AM		 2871 /* 1 if operand is pending after ','. */
2872 unsigned int expecting_operand = 0;
252b5132 2873
29b0f896
AM		 2874 /* Non-zero if operand parens not balanced. */
2875 unsigned int paren_not_balanced;
2876
2877 while (*l != END_OF_INSN)
2878 {
2879 /* Skip optional white space before operand. */
2880 if (is_space_char (*l))
2881 ++l;
2882 if (!is_operand_char (*l) && *l != END_OF_INSN)
2883 {
2884 as_bad (_("invalid character %s before operand %d"),
2885 output_invalid (*l),
2886 i.operands + 1);
2887 return NULL;
2888 }
2889 token_start = l; /* after white space */
2890 paren_not_balanced = 0;
2891 while (paren_not_balanced || *l != ',')
2892 {
2893 if (*l == END_OF_INSN)
2894 {
2895 if (paren_not_balanced)
2896 {
2897 if (!intel_syntax)
2898 as_bad (_("unbalanced parenthesis in operand %d."),
2899 i.operands + 1);
2900 else
2901 as_bad (_("unbalanced brackets in operand %d."),
2902 i.operands + 1);
2903 return NULL;
2904 }
2905 else
2906 break; /* we are done */
2907 }
2908 else if (!is_operand_char (*l) && !is_space_char (*l))
2909 {
2910 as_bad (_("invalid character %s in operand %d"),
2911 output_invalid (*l),
2912 i.operands + 1);
2913 return NULL;
2914 }
2915 if (!intel_syntax)
2916 {
2917 if (*l == '(')
2918 ++paren_not_balanced;
2919 if (*l == ')')
2920 --paren_not_balanced;
2921 }
2922 else
2923 {
2924 if (*l == '[')
2925 ++paren_not_balanced;
2926 if (*l == ']')
2927 --paren_not_balanced;
2928 }
2929 l++;
2930 }
2931 if (l != token_start)
2932 { /* Yes, we've read in another operand. */
2933 unsigned int operand_ok;
2934 this_operand = i.operands++;
7d5e4556 2935 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 2936 if (i.operands > MAX_OPERANDS)
2937 {
2938 as_bad (_("spurious operands; (%d operands/instruction max)"),
2939 MAX_OPERANDS);
2940 return NULL;
2941 }
2942 /* Now parse operand adding info to 'i' as we go along. */
2943 END_STRING_AND_SAVE (l);
2944
2945 if (intel_syntax)
2946 operand_ok =
2947 i386_intel_operand (token_start,
2948 intel_float_operand (mnemonic));
2949 else
a7619375 2950 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 2951
2952 RESTORE_END_STRING (l);
2953 if (!operand_ok)
2954 return NULL;
2955 }
2956 else
2957 {
2958 if (expecting_operand)
2959 {
2960 expecting_operand_after_comma:
2961 as_bad (_("expecting operand after ','; got nothing"));
2962 return NULL;
2963 }
2964 if (*l == ',')
2965 {
2966 as_bad (_("expecting operand before ','; got nothing"));
2967 return NULL;
2968 }
2969 }
7f3f1ea2 2970
29b0f896
AM		 2971 /* Now *l must be either ',' or END_OF_INSN. */
2972 if (*l == ',')
2973 {
2974 if (*++l == END_OF_INSN)
2975 {
2976 /* Just skip it, if it's \n complain. */
2977 goto expecting_operand_after_comma;
2978 }
2979 expecting_operand = 1;
2980 }
2981 }
2982 return l;
2983}
7f3f1ea2 2984
050dfa73 2985static void
4d456e3d 2986swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 2987{
2988 union i386_op temp_op;
40fb9820 2989 i386_operand_type temp_type;
050dfa73 2990 enum bfd_reloc_code_real temp_reloc;
4eed87de 2991
050dfa73
MM		 2992 temp_type = i.types[xchg2];
2993 i.types[xchg2] = i.types[xchg1];
2994 i.types[xchg1] = temp_type;
2995 temp_op = i.op[xchg2];
2996 i.op[xchg2] = i.op[xchg1];
2997 i.op[xchg1] = temp_op;
2998 temp_reloc = i.reloc[xchg2];
2999 i.reloc[xchg2] = i.reloc[xchg1];
3000 i.reloc[xchg1] = temp_reloc;
3001}
3002
29b0f896 3003static void
e3bb37b5 3004swap_operands (void)
29b0f896 3005{
b7c61d9a 3006 switch (i.operands)
050dfa73 3007 {
b7c61d9a 3008 case 4:
4d456e3d 3009 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3010 case 3:
3011 case 2:
4d456e3d 3012 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3013 break;
3014 default:
3015 abort ();
29b0f896 3016 }
29b0f896
AM		 3017
3018 if (i.mem_operands == 2)
3019 {
3020 const seg_entry *temp_seg;
3021 temp_seg = i.seg[0];
3022 i.seg[0] = i.seg[1];
3023 i.seg[1] = temp_seg;
3024 }
3025}
252b5132 3026
29b0f896
AM		 3027/* Try to ensure constant immediates are represented in the smallest
3028 opcode possible. */
3029static void
e3bb37b5 3030optimize_imm (void)
29b0f896
AM		 3031{
3032 char guess_suffix = 0;
3033 int op;
252b5132 3034
29b0f896
AM		 3035 if (i.suffix)
3036 guess_suffix = i.suffix;
3037 else if (i.reg_operands)
3038 {
3039 /* Figure out a suffix from the last register operand specified.
3040 We can't do this properly yet, ie. excluding InOutPortReg,
3041 but the following works for instructions with immediates.
3042 In any case, we can't set i.suffix yet. */
3043 for (op = i.operands; --op >= 0;)
40fb9820
L		 3044 if (i.types[op].bitfield.reg8)
3045 {
3046 guess_suffix = BYTE_MNEM_SUFFIX;
3047 break;
3048 }
3049 else if (i.types[op].bitfield.reg16)
252b5132 3050 {
40fb9820
L		 3051 guess_suffix = WORD_MNEM_SUFFIX;
3052 break;
3053 }
3054 else if (i.types[op].bitfield.reg32)
3055 {
3056 guess_suffix = LONG_MNEM_SUFFIX;
3057 break;
3058 }
3059 else if (i.types[op].bitfield.reg64)
3060 {
3061 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3062 break;
252b5132 3063 }
29b0f896
AM		 3064 }
3065 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3066 guess_suffix = WORD_MNEM_SUFFIX;
3067
3068 for (op = i.operands; --op >= 0;)
40fb9820 3069 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3070 {
3071 switch (i.op[op].imms->X_op)
252b5132 3072 {
29b0f896
AM		 3073 case O_constant:
3074 /* If a suffix is given, this operand may be shortened. */
3075 switch (guess_suffix)
252b5132 3076 {
29b0f896 3077 case LONG_MNEM_SUFFIX:
40fb9820
L		 3078 i.types[op].bitfield.imm32 = 1;
3079 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3080 break;
3081 case WORD_MNEM_SUFFIX:
40fb9820
L		 3082 i.types[op].bitfield.imm16 = 1;
3083 i.types[op].bitfield.imm32 = 1;
3084 i.types[op].bitfield.imm32s = 1;
3085 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3086 break;
3087 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3088 i.types[op].bitfield.imm8 = 1;
3089 i.types[op].bitfield.imm8s = 1;
3090 i.types[op].bitfield.imm16 = 1;
3091 i.types[op].bitfield.imm32 = 1;
3092 i.types[op].bitfield.imm32s = 1;
3093 i.types[op].bitfield.imm64 = 1;
29b0f896 3094 break;
252b5132 3095 }
252b5132 3096
29b0f896
AM		 3097 /* If this operand is at most 16 bits, convert it
3098 to a signed 16 bit number before trying to see
3099 whether it will fit in an even smaller size.
3100 This allows a 16-bit operand such as $0xffe0 to
3101 be recognised as within Imm8S range. */
40fb9820 3102 if ((i.types[op].bitfield.imm16)
29b0f896 3103 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3104 {
29b0f896
AM		 3105 i.op[op].imms->X_add_number =
3106 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3107 }
40fb9820 3108 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3109 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3110 == 0))
3111 {
3112 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3113 ^ ((offsetT) 1 << 31))
3114 - ((offsetT) 1 << 31));
3115 }
40fb9820 3116 i.types[op]
c6fb90c8
L		 3117 = operand_type_or (i.types[op],
3118 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3119
29b0f896
AM		 3120 /* We must avoid matching of Imm32 templates when 64bit
3121 only immediate is available. */
3122 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3123 i.types[op].bitfield.imm32 = 0;
29b0f896 3124 break;
252b5132 3125
29b0f896
AM		 3126 case O_absent:
3127 case O_register:
3128 abort ();
3129
3130 /* Symbols and expressions. */
3131 default:
9cd96992
JB		 3132 /* Convert symbolic operand to proper sizes for matching, but don't
3133 prevent matching a set of insns that only supports sizes other
3134 than those matching the insn suffix. */
3135 {
40fb9820 3136 i386_operand_type mask, allowed;
9cd96992
JB		 3137 const template *t;
3138
0dfbf9d7
L		 3139 operand_type_set (&mask, 0);
3140 operand_type_set (&allowed, 0);
40fb9820 3141
4eed87de
AM		 3142 for (t = current_templates->start;
3143 t < current_templates->end;
3144 ++t)
c6fb90c8
L		 3145 allowed = operand_type_or (allowed,
3146 t->operand_types[op]);
9cd96992
JB		 3147 switch (guess_suffix)
3148 {
3149 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3150 mask.bitfield.imm64 = 1;
3151 mask.bitfield.imm32s = 1;
9cd96992
JB		 3152 break;
3153 case LONG_MNEM_SUFFIX:
40fb9820 3154 mask.bitfield.imm32 = 1;
9cd96992
JB		 3155 break;
3156 case WORD_MNEM_SUFFIX:
40fb9820 3157 mask.bitfield.imm16 = 1;
9cd96992
JB		 3158 break;
3159 case BYTE_MNEM_SUFFIX:
40fb9820 3160 mask.bitfield.imm8 = 1;
9cd96992
JB		 3161 break;
3162 default:
9cd96992
JB		 3163 break;
3164 }
c6fb90c8 3165 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3166 if (!operand_type_all_zero (&allowed))
c6fb90c8 3167 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3168 }
29b0f896 3169 break;
252b5132 3170 }
29b0f896
AM		 3171 }
3172}
47926f60 3173
29b0f896
AM		 3174/* Try to use the smallest displacement type too. */
3175static void
e3bb37b5 3176optimize_disp (void)
29b0f896
AM		 3177{
3178 int op;
3e73aa7c 3179
29b0f896 3180 for (op = i.operands; --op >= 0;)
40fb9820 3181 if (operand_type_check (i.types[op], disp))
252b5132 3182 {
b300c311 3183 if (i.op[op].disps->X_op == O_constant)
252b5132 3184 {
b300c311 3185 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 3186
40fb9820 3187 if (i.types[op].bitfield.disp16
b300c311
L		 3188 && (disp & ~(offsetT) 0xffff) == 0)
3189 {
3190 /* If this operand is at most 16 bits, convert
3191 to a signed 16 bit number and don't use 64bit
3192 displacement. */
3193 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3194 i.types[op].bitfield.disp64 = 0;
b300c311 3195 }
40fb9820 3196 if (i.types[op].bitfield.disp32
b300c311
L		 3197 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3198 {
3199 /* If this operand is at most 32 bits, convert
3200 to a signed 32 bit number and don't use 64bit
3201 displacement. */
3202 disp &= (((offsetT) 2 << 31) - 1);
3203 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3204 i.types[op].bitfield.disp64 = 0;
b300c311 3205 }
40fb9820 3206 if (!disp && i.types[op].bitfield.baseindex)
b300c311 3207 {
40fb9820
L		 3208 i.types[op].bitfield.disp8 = 0;
3209 i.types[op].bitfield.disp16 = 0;
3210 i.types[op].bitfield.disp32 = 0;
3211 i.types[op].bitfield.disp32s = 0;
3212 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3213 i.op[op].disps = 0;
3214 i.disp_operands--;
3215 }
3216 else if (flag_code == CODE_64BIT)
3217 {
3218 if (fits_in_signed_long (disp))
28a9d8f5 3219 {
40fb9820
L		 3220 i.types[op].bitfield.disp64 = 0;
3221 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3222 }
b300c311 3223 if (fits_in_unsigned_long (disp))
40fb9820 3224 i.types[op].bitfield.disp32 = 1;
b300c311 3225 }
40fb9820
L		 3226 if ((i.types[op].bitfield.disp32
3227 || i.types[op].bitfield.disp32s
3228 || i.types[op].bitfield.disp16)
b300c311 3229 && fits_in_signed_byte (disp))
40fb9820 3230 i.types[op].bitfield.disp8 = 1;
252b5132 3231 }
67a4f2b7
AO		 3232 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3233 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3234 {
3235 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3236 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3237 i.types[op].bitfield.disp8 = 0;
3238 i.types[op].bitfield.disp16 = 0;
3239 i.types[op].bitfield.disp32 = 0;
3240 i.types[op].bitfield.disp32s = 0;
3241 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3242 }
3243 else
b300c311 3244 /* We only support 64bit displacement on constants. */
40fb9820 3245 i.types[op].bitfield.disp64 = 0;
252b5132 3246 }
29b0f896
AM		 3247}
3248
3249static int
e3bb37b5 3250match_template (void)
29b0f896
AM		 3251{
3252 /* Points to template once we've found it. */
3253 const template *t;
40fb9820 3254 i386_operand_type overlap0, overlap1, overlap2, overlap3;
29b0f896 3255 unsigned int found_reverse_match;
40fb9820
L		 3256 i386_opcode_modifier suffix_check;
3257 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3258 int addr_prefix_disp;
a5c311ca 3259 unsigned int j;
3629bb00 3260 unsigned int found_cpu_match;
45664ddb 3261 unsigned int check_register;
29b0f896 3262
f48ff2ae
L		 3263#if MAX_OPERANDS != 4
3264# error "MAX_OPERANDS must be 4."
3265#endif
3266
29b0f896 3267 found_reverse_match = 0;
539e75ad 3268 addr_prefix_disp = -1;
40fb9820
L		 3269
3270 memset (&suffix_check, 0, sizeof (suffix_check));
3271 if (i.suffix == BYTE_MNEM_SUFFIX)
3272 suffix_check.no_bsuf = 1;
3273 else if (i.suffix == WORD_MNEM_SUFFIX)
3274 suffix_check.no_wsuf = 1;
3275 else if (i.suffix == SHORT_MNEM_SUFFIX)
3276 suffix_check.no_ssuf = 1;
3277 else if (i.suffix == LONG_MNEM_SUFFIX)
3278 suffix_check.no_lsuf = 1;
3279 else if (i.suffix == QWORD_MNEM_SUFFIX)
3280 suffix_check.no_qsuf = 1;
3281 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3282 suffix_check.no_ldsuf = 1;
29b0f896 3283
45aa61fe 3284 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3285 {
539e75ad
L		 3286 addr_prefix_disp = -1;
3287
29b0f896
AM		 3288 /* Must have right number of operands. */
3289 if (i.operands != t->operands)
3290 continue;
3291
50aecf8c
L		 3292 /* Check processor support. */
3293 found_cpu_match = cpu_flags_match (t->cpu_flags) == 3;
3294 if (!found_cpu_match)
3295 continue;
3296
e1d4d893
L		 3297 /* Check old gcc support. */
3298 if (!old_gcc && t->opcode_modifier.oldgcc)
3299 continue;
3300
3301 /* Check AT&T mnemonic. */
3302 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3303 continue;
3304
5c07affc
L		 3305 /* Check AT&T syntax Intel syntax. */
3306 if ((intel_syntax && t->opcode_modifier.attsyntax)
3307 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3308 continue;
3309
20592a94 3310 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3311 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3312 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3313 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3314 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3315 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3316 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3317 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3318 continue;
3319
5c07affc 3320 if (!operand_size_match (t))
7d5e4556 3321 continue;
539e75ad 3322
5c07affc
L		 3323 for (j = 0; j < MAX_OPERANDS; j++)
3324 operand_types[j] = t->operand_types[j];
3325
45aa61fe
AM		 3326 /* In general, don't allow 64-bit operands in 32-bit mode. */
3327 if (i.suffix == QWORD_MNEM_SUFFIX
3328 && flag_code != CODE_64BIT
3329 && (intel_syntax
40fb9820 3330 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3331 && !intel_float_operand (t->name))
3332 : intel_float_operand (t->name) != 2)
40fb9820
L		 3333 && ((!operand_types[0].bitfield.regmmx
3334 && !operand_types[0].bitfield.regxmm)
3335 || (!operand_types[t->operands > 1].bitfield.regmmx
3336 && !!operand_types[t->operands > 1].bitfield.regxmm))
45aa61fe
AM		 3337 && (t->base_opcode != 0x0fc7
3338 || t->extension_opcode != 1 /* cmpxchg8b */))
3339 continue;
3340
29b0f896 3341 /* Do not verify operands when there are none. */
50aecf8c 3342 else
29b0f896 3343 {
c6fb90c8 3344 if (!t->operands)
2dbab7d5
L		 3345 /* We've found a match; break out of loop. */
3346 break;
29b0f896 3347 }
252b5132 3348
539e75ad
L		 3349 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3350 into Disp32/Disp16/Disp32 operand. */
3351 if (i.prefix[ADDR_PREFIX] != 0)
3352 {
40fb9820 3353 /* There should be only one Disp operand. */
539e75ad
L		 3354 switch (flag_code)
3355 {
3356 case CODE_16BIT:
40fb9820
L		 3357 for (j = 0; j < MAX_OPERANDS; j++)
3358 {
3359 if (operand_types[j].bitfield.disp16)
3360 {
3361 addr_prefix_disp = j;
3362 operand_types[j].bitfield.disp32 = 1;
3363 operand_types[j].bitfield.disp16 = 0;
3364 break;
3365 }
3366 }
539e75ad
L		 3367 break;
3368 case CODE_32BIT:
40fb9820
L		 3369 for (j = 0; j < MAX_OPERANDS; j++)
3370 {
3371 if (operand_types[j].bitfield.disp32)
3372 {
3373 addr_prefix_disp = j;
3374 operand_types[j].bitfield.disp32 = 0;
3375 operand_types[j].bitfield.disp16 = 1;
3376 break;
3377 }
3378 }
539e75ad
L		 3379 break;
3380 case CODE_64BIT:
40fb9820
L		 3381 for (j = 0; j < MAX_OPERANDS; j++)
3382 {
3383 if (operand_types[j].bitfield.disp64)
3384 {
3385 addr_prefix_disp = j;
3386 operand_types[j].bitfield.disp64 = 0;
3387 operand_types[j].bitfield.disp32 = 1;
3388 break;
3389 }
3390 }
539e75ad
L		 3391 break;
3392 }
539e75ad
L		 3393 }
3394
45664ddb
L		 3395 /* We check register size only if size of operands can be
3396 encoded the canonical way. */
3397 check_register = t->opcode_modifier.w;
c6fb90c8 3398 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3399 switch (t->operands)
3400 {
3401 case 1:
40fb9820 3402 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3403 continue;
3404 break;
3405 case 2:
8b38ad71
L		 3406 /* xchg %eax, %eax is a special case. It is an aliase for nop
3407 only in 32bit mode and we can use opcode 0x90. In 64bit
3408 mode, we can't use 0x90 for xchg %eax, %eax since it should
3409 zero-extend %eax to %rax. */
3410 if (flag_code == CODE_64BIT
3411 && t->base_opcode == 0x90
0dfbf9d7
L		 3412 && operand_type_equal (&i.types [0], &acc32)
3413 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 3414 continue;
29b0f896 3415 case 3:
f48ff2ae 3416 case 4:
c6fb90c8 3417 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3418 if (!operand_type_match (overlap0, i.types[0])
3419 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3420 || (check_register
3421 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3422 operand_types[0],
3423 overlap1, i.types[1],
3424 operand_types[1])))
29b0f896
AM		 3425 {
3426 /* Check if other direction is valid ... */
40fb9820 3427 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3428 continue;
3429
3430 /* Try reversing direction of operands. */
c6fb90c8
L		 3431 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3432 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3433 if (!operand_type_match (overlap0, i.types[0])
3434 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3435 || (check_register
3436 && !operand_type_register_match (overlap0,
3437 i.types[0],
3438 operand_types[1],
3439 overlap1,
3440 i.types[1],
3441 operand_types[0])))
29b0f896
AM		 3442 {
3443 /* Does not match either direction. */
3444 continue;
3445 }
3446 /* found_reverse_match holds which of D or FloatDR
3447 we've found. */
40fb9820 3448 if (t->opcode_modifier.d)
8a2ed489 3449 found_reverse_match = Opcode_D;
40fb9820 3450 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3451 found_reverse_match = Opcode_FloatD;
3452 else
3453 found_reverse_match = 0;
40fb9820 3454 if (t->opcode_modifier.floatr)
8a2ed489 3455 found_reverse_match |= Opcode_FloatR;
29b0f896 3456 }
f48ff2ae 3457 else
29b0f896 3458 {
f48ff2ae 3459 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3460 switch (t->operands)
3461 {
3462 case 4:
c6fb90c8
L		 3463 overlap3 = operand_type_and (i.types[3],
3464 operand_types[3]);
d1cbb4db 3465 case 3:
c6fb90c8
L		 3466 overlap2 = operand_type_and (i.types[2],
3467 operand_types[2]);
d1cbb4db
L		 3468 break;
3469 }
29b0f896 3470
f48ff2ae
L		 3471 switch (t->operands)
3472 {
3473 case 4:
40fb9820 3474 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 3475 || (check_register
3476 && !operand_type_register_match (overlap2,
3477 i.types[2],
3478 operand_types[2],
3479 overlap3,
3480 i.types[3],
3481 operand_types[3])))
f48ff2ae
L		 3482 continue;
3483 case 3:
3484 /* Here we make use of the fact that there are no
3485 reverse match 3 operand instructions, and all 3
3486 operand instructions only need to be checked for
3487 register consistency between operands 2 and 3. */
40fb9820 3488 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 3489 || (check_register
3490 && !operand_type_register_match (overlap1,
3491 i.types[1],
3492 operand_types[1],
3493 overlap2,
3494 i.types[2],
3495 operand_types[2])))
f48ff2ae
L		 3496 continue;
3497 break;
3498 }
29b0f896 3499 }
f48ff2ae 3500 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3501 slip through to break. */
3502 }
3629bb00 3503 if (!found_cpu_match)
29b0f896
AM		 3504 {
3505 found_reverse_match = 0;
3506 continue;
3507 }
3508 /* We've found a match; break out of loop. */
3509 break;
3510 }
3511
3512 if (t == current_templates->end)
3513 {
3514 /* We found no match. */
3515 as_bad (_("suffix or operands invalid for `%s'"),
3516 current_templates->start->name);
3517 return 0;
3518 }
252b5132 3519
29b0f896
AM		 3520 if (!quiet_warnings)
3521 {
3522 if (!intel_syntax
40fb9820
L		 3523 && (i.types[0].bitfield.jumpabsolute
3524 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3525 {
3526 as_warn (_("indirect %s without `*'"), t->name);
3527 }
3528
40fb9820
L		 3529 if (t->opcode_modifier.isprefix
3530 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3531 {
3532 /* Warn them that a data or address size prefix doesn't
3533 affect assembly of the next line of code. */
3534 as_warn (_("stand-alone `%s' prefix"), t->name);
3535 }
3536 }
3537
3538 /* Copy the template we found. */
3539 i.tm = *t;
539e75ad
L		 3540
3541 if (addr_prefix_disp != -1)
3542 i.tm.operand_types[addr_prefix_disp]
3543 = operand_types[addr_prefix_disp];
3544
29b0f896
AM		 3545 if (found_reverse_match)
3546 {
3547 /* If we found a reverse match we must alter the opcode
3548 direction bit. found_reverse_match holds bits to change
3549 (different for int & float insns). */
3550
3551 i.tm.base_opcode ^= found_reverse_match;
3552
539e75ad
L		 3553 i.tm.operand_types[0] = operand_types[1];
3554 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3555 }
3556
3557 return 1;
3558}
3559
3560static int
e3bb37b5 3561check_string (void)
29b0f896 3562{
40fb9820
L		 3563 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3564 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3565 {
3566 if (i.seg[0] != NULL && i.seg[0] != &es)
3567 {
3568 as_bad (_("`%s' operand %d must use `%%es' segment"),
3569 i.tm.name,
3570 mem_op + 1);
3571 return 0;
3572 }
3573 /* There's only ever one segment override allowed per instruction.
3574 This instruction possibly has a legal segment override on the
3575 second operand, so copy the segment to where non-string
3576 instructions store it, allowing common code. */
3577 i.seg[0] = i.seg[1];
3578 }
40fb9820 3579 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3580 {
3581 if (i.seg[1] != NULL && i.seg[1] != &es)
3582 {
3583 as_bad (_("`%s' operand %d must use `%%es' segment"),
3584 i.tm.name,
3585 mem_op + 2);
3586 return 0;
3587 }
3588 }
3589 return 1;
3590}
3591
3592static int
543613e9 3593process_suffix (void)
29b0f896
AM		 3594{
3595 /* If matched instruction specifies an explicit instruction mnemonic
3596 suffix, use it. */
40fb9820
L		 3597 if (i.tm.opcode_modifier.size16)
3598 i.suffix = WORD_MNEM_SUFFIX;
3599 else if (i.tm.opcode_modifier.size32)
3600 i.suffix = LONG_MNEM_SUFFIX;
3601 else if (i.tm.opcode_modifier.size64)
3602 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 3603 else if (i.reg_operands)
3604 {
3605 /* If there's no instruction mnemonic suffix we try to invent one
3606 based on register operands. */
3607 if (!i.suffix)
3608 {
3609 /* We take i.suffix from the last register operand specified,
3610 Destination register type is more significant than source
381d071f
L		 3611 register type. crc32 in SSE4.2 prefers source register
3612 type. */
3613 if (i.tm.base_opcode == 0xf20f38f1)
3614 {
40fb9820
L		 3615 if (i.types[0].bitfield.reg16)
3616 i.suffix = WORD_MNEM_SUFFIX;
3617 else if (i.types[0].bitfield.reg32)
3618 i.suffix = LONG_MNEM_SUFFIX;
3619 else if (i.types[0].bitfield.reg64)
3620 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 3621 }
9344ff29 3622 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 3623 {
40fb9820 3624 if (i.types[0].bitfield.reg8)
20592a94
L		 3625 i.suffix = BYTE_MNEM_SUFFIX;
3626 }
381d071f
L		 3627
3628 if (!i.suffix)
3629 {
3630 int op;
3631
20592a94
L		 3632 if (i.tm.base_opcode == 0xf20f38f1
3633 || i.tm.base_opcode == 0xf20f38f0)
3634 {
3635 /* We have to know the operand size for crc32. */
3636 as_bad (_("ambiguous memory operand size for `%s`"),
3637 i.tm.name);
3638 return 0;
3639 }
3640
381d071f 3641 for (op = i.operands; --op >= 0;)
40fb9820 3642 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 3643 {
40fb9820
L		 3644 if (i.types[op].bitfield.reg8)
3645 {
3646 i.suffix = BYTE_MNEM_SUFFIX;
3647 break;
3648 }
3649 else if (i.types[op].bitfield.reg16)
3650 {
3651 i.suffix = WORD_MNEM_SUFFIX;
3652 break;
3653 }
3654 else if (i.types[op].bitfield.reg32)
3655 {
3656 i.suffix = LONG_MNEM_SUFFIX;
3657 break;
3658 }
3659 else if (i.types[op].bitfield.reg64)
3660 {
3661 i.suffix = QWORD_MNEM_SUFFIX;
3662 break;
3663 }
381d071f
L		 3664 }
3665 }
29b0f896
AM		 3666 }
3667 else if (i.suffix == BYTE_MNEM_SUFFIX)
3668 {
3669 if (!check_byte_reg ())
3670 return 0;
3671 }
3672 else if (i.suffix == LONG_MNEM_SUFFIX)
3673 {
3674 if (!check_long_reg ())
3675 return 0;
3676 }
3677 else if (i.suffix == QWORD_MNEM_SUFFIX)
3678 {
955e1e6a
L		 3679 if (intel_syntax
3680 && i.tm.opcode_modifier.ignoresize
3681 && i.tm.opcode_modifier.no_qsuf)
3682 i.suffix = 0;
3683 else if (!check_qword_reg ())
29b0f896
AM		 3684 return 0;
3685 }
3686 else if (i.suffix == WORD_MNEM_SUFFIX)
3687 {
3688 if (!check_word_reg ())
3689 return 0;
3690 }
582d5edd
L		 3691 else if (i.suffix == XMMWORD_MNEM_SUFFIX)
3692 {
3693 /* Skip if the instruction has x suffix. match_template
3694 should check if it is a valid suffix. */
3695 }
40fb9820 3696 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 3697 /* Do nothing if the instruction is going to ignore the prefix. */
3698 ;
3699 else
3700 abort ();
3701 }
40fb9820 3702 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 3703 && !i.suffix
3704 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 3705 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 3706 {
3707 i.suffix = stackop_size;
3708 }
9306ca4a
JB		 3709 else if (intel_syntax
3710 && !i.suffix
40fb9820
L		 3711 && (i.tm.operand_types[0].bitfield.jumpabsolute
3712 || i.tm.opcode_modifier.jumpbyte
3713 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 3714 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3715 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 3716 {
3717 switch (flag_code)
3718 {
3719 case CODE_64BIT:
40fb9820 3720 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 3721 {
3722 i.suffix = QWORD_MNEM_SUFFIX;
3723 break;
3724 }
3725 case CODE_32BIT:
40fb9820 3726 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 3727 i.suffix = LONG_MNEM_SUFFIX;
3728 break;
3729 case CODE_16BIT:
40fb9820 3730 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 3731 i.suffix = WORD_MNEM_SUFFIX;
3732 break;
3733 }
3734 }
252b5132 3735
9306ca4a 3736 if (!i.suffix)
29b0f896 3737 {
9306ca4a
JB		 3738 if (!intel_syntax)
3739 {
40fb9820 3740 if (i.tm.opcode_modifier.w)
9306ca4a 3741 {
4eed87de
AM		 3742 as_bad (_("no instruction mnemonic suffix given and "
3743 "no register operands; can't size instruction"));
9306ca4a
JB		 3744 return 0;
3745 }
3746 }
3747 else
3748 {
40fb9820
L		 3749 unsigned int suffixes;
3750
3751 suffixes = !i.tm.opcode_modifier.no_bsuf;
3752 if (!i.tm.opcode_modifier.no_wsuf)
3753 suffixes |= 1 << 1;
3754 if (!i.tm.opcode_modifier.no_lsuf)
3755 suffixes |= 1 << 2;
fc4adea1 3756 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 3757 suffixes |= 1 << 3;
3758 if (!i.tm.opcode_modifier.no_ssuf)
3759 suffixes |= 1 << 4;
3760 if (!i.tm.opcode_modifier.no_qsuf)
3761 suffixes |= 1 << 5;
3762
3763 /* There are more than suffix matches. */
3764 if (i.tm.opcode_modifier.w
9306ca4a 3765 || ((suffixes & (suffixes - 1))
40fb9820
L		 3766 && !i.tm.opcode_modifier.defaultsize
3767 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 3768 {
3769 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3770 return 0;
3771 }
3772 }
29b0f896 3773 }
252b5132 3774
9306ca4a
JB		 3775 /* Change the opcode based on the operand size given by i.suffix;
3776 We don't need to change things for byte insns. */
3777
582d5edd
L		 3778 if (i.suffix
3779 && i.suffix != BYTE_MNEM_SUFFIX
3780 && i.suffix != XMMWORD_MNEM_SUFFIX)
29b0f896
AM		 3781 {
3782 /* It's not a byte, select word/dword operation. */
40fb9820 3783 if (i.tm.opcode_modifier.w)
29b0f896 3784 {
40fb9820 3785 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 3786 i.tm.base_opcode |= 8;
3787 else
3788 i.tm.base_opcode |= 1;
3789 }
0f3f3d8b 3790
29b0f896
AM		 3791 /* Now select between word & dword operations via the operand
3792 size prefix, except for instructions that will ignore this
3793 prefix anyway. */
ca61edf2 3794 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 3795 {
ca61edf2
L		 3796 /* The address size override prefix changes the size of the
3797 first operand. */
40fb9820
L		 3798 if ((flag_code == CODE_32BIT
3799 && i.op->regs[0].reg_type.bitfield.reg16)
3800 || (flag_code != CODE_32BIT
3801 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 3802 if (!add_prefix (ADDR_PREFIX_OPCODE))
3803 return 0;
3804 }
3805 else if (i.suffix != QWORD_MNEM_SUFFIX
3806 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 3807 && !i.tm.opcode_modifier.ignoresize
3808 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 3809 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3810 || (flag_code == CODE_64BIT
40fb9820 3811 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 3812 {
3813 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 3814
40fb9820 3815 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 3816 prefix = ADDR_PREFIX_OPCODE;
252b5132 3817
29b0f896
AM		 3818 if (!add_prefix (prefix))
3819 return 0;
24eab124 3820 }
252b5132 3821
29b0f896
AM		 3822 /* Set mode64 for an operand. */
3823 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 3824 && flag_code == CODE_64BIT
40fb9820 3825 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 3826 {
3827 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 3828 need rex64. cmpxchg8b is also a special case. */
3829 if (! (i.operands == 2
3830 && i.tm.base_opcode == 0x90
3831 && i.tm.extension_opcode == None
0dfbf9d7
L		 3832 && operand_type_equal (&i.types [0], &acc64)
3833 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 3834 && ! (i.operands == 1
3835 && i.tm.base_opcode == 0xfc7
3836 && i.tm.extension_opcode == 1
40fb9820
L		 3837 && !operand_type_check (i.types [0], reg)
3838 && operand_type_check (i.types [0], anymem)))
f6bee062 3839 i.rex |= REX_W;
46e883c5 3840 }
3e73aa7c 3841
29b0f896
AM		 3842 /* Size floating point instruction. */
3843 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 3844 if (i.tm.opcode_modifier.floatmf)
543613e9 3845 i.tm.base_opcode ^= 4;
29b0f896 3846 }
7ecd2f8b 3847
29b0f896
AM		 3848 return 1;
3849}
3e73aa7c 3850
29b0f896 3851static int
543613e9 3852check_byte_reg (void)
29b0f896
AM		 3853{
3854 int op;
543613e9 3855
29b0f896
AM		 3856 for (op = i.operands; --op >= 0;)
3857 {
3858 /* If this is an eight bit register, it's OK. If it's the 16 or
3859 32 bit version of an eight bit register, we will just use the
3860 low portion, and that's OK too. */
40fb9820 3861 if (i.types[op].bitfield.reg8)
29b0f896
AM		 3862 continue;
3863
ca61edf2
L		 3864 /* Don't generate this warning if not needed. */
3865 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
29b0f896
AM		 3866 continue;
3867
9344ff29
L		 3868 /* crc32 doesn't generate this warning. */
3869 if (i.tm.base_opcode == 0xf20f38f0)
3870 continue;
3871
40fb9820
L		 3872 if ((i.types[op].bitfield.reg16
3873 || i.types[op].bitfield.reg32
3874 || i.types[op].bitfield.reg64)
3875 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3876 {
3877 /* Prohibit these changes in the 64bit mode, since the
3878 lowering is more complicated. */
3879 if (flag_code == CODE_64BIT
40fb9820 3880 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 3881 {
2ca3ace5
L		 3882 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3883 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3884 i.suffix);
3885 return 0;
3886 }
3887#if REGISTER_WARNINGS
3888 if (!quiet_warnings
40fb9820 3889 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 3890 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3891 register_prefix,
40fb9820 3892 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 3893 ? REGNAM_AL - REGNAM_AX
3894 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 3895 register_prefix,
29b0f896
AM		 3896 i.op[op].regs->reg_name,
3897 i.suffix);
3898#endif
3899 continue;
3900 }
3901 /* Any other register is bad. */
40fb9820
L		 3902 if (i.types[op].bitfield.reg16
3903 || i.types[op].bitfield.reg32
3904 || i.types[op].bitfield.reg64
3905 || i.types[op].bitfield.regmmx
3906 || i.types[op].bitfield.regxmm
3907 || i.types[op].bitfield.sreg2
3908 || i.types[op].bitfield.sreg3
3909 || i.types[op].bitfield.control
3910 || i.types[op].bitfield.debug
3911 || i.types[op].bitfield.test
3912 || i.types[op].bitfield.floatreg
3913 || i.types[op].bitfield.floatacc)
29b0f896 3914 {
a540244d
L		 3915 as_bad (_("`%s%s' not allowed with `%s%c'"),
3916 register_prefix,
29b0f896
AM		 3917 i.op[op].regs->reg_name,
3918 i.tm.name,
3919 i.suffix);
3920 return 0;
3921 }
3922 }
3923 return 1;
3924}
3925
3926static int
e3bb37b5 3927check_long_reg (void)
29b0f896
AM		 3928{
3929 int op;
3930
3931 for (op = i.operands; --op >= 0;)
3932 /* Reject eight bit registers, except where the template requires
3933 them. (eg. movzb) */
40fb9820
L		 3934 if (i.types[op].bitfield.reg8
3935 && (i.tm.operand_types[op].bitfield.reg16
3936 || i.tm.operand_types[op].bitfield.reg32
3937 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3938 {
a540244d
L		 3939 as_bad (_("`%s%s' not allowed with `%s%c'"),
3940 register_prefix,
29b0f896
AM		 3941 i.op[op].regs->reg_name,
3942 i.tm.name,
3943 i.suffix);
3944 return 0;
3945 }
3946 /* Warn if the e prefix on a general reg is missing. */
3947 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3948 && i.types[op].bitfield.reg16
3949 && (i.tm.operand_types[op].bitfield.reg32
3950 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3951 {
3952 /* Prohibit these changes in the 64bit mode, since the
3953 lowering is more complicated. */
3954 if (flag_code == CODE_64BIT)
252b5132 3955 {
2ca3ace5
L		 3956 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3957 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3958 i.suffix);
3959 return 0;
252b5132 3960 }
29b0f896
AM		 3961#if REGISTER_WARNINGS
3962 else
a540244d
L		 3963 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3964 register_prefix,
29b0f896 3965 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 3966 register_prefix,
29b0f896
AM		 3967 i.op[op].regs->reg_name,
3968 i.suffix);
3969#endif
252b5132 3970 }
29b0f896 3971 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 3972 else if (i.types[op].bitfield.reg64
3973 && (i.tm.operand_types[op].bitfield.reg32
3974 || i.tm.operand_types[op].bitfield.acc))
252b5132 3975 {
34828aad 3976 if (intel_syntax
ca61edf2 3977 && i.tm.opcode_modifier.toqword
40fb9820 3978 && !i.types[0].bitfield.regxmm)
34828aad 3979 {
ca61edf2 3980 /* Convert to QWORD. We want REX byte. */
34828aad
L		 3981 i.suffix = QWORD_MNEM_SUFFIX;
3982 }
3983 else
3984 {
3985 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3986 register_prefix, i.op[op].regs->reg_name,
3987 i.suffix);
3988 return 0;
3989 }
29b0f896
AM		 3990 }
3991 return 1;
3992}
252b5132 3993
29b0f896 3994static int
e3bb37b5 3995check_qword_reg (void)
29b0f896
AM		 3996{
3997 int op;
252b5132 3998
29b0f896
AM		 3999 for (op = i.operands; --op >= 0; )
4000 /* Reject eight bit registers, except where the template requires
4001 them. (eg. movzb) */
40fb9820
L		 4002 if (i.types[op].bitfield.reg8
4003 && (i.tm.operand_types[op].bitfield.reg16
4004 || i.tm.operand_types[op].bitfield.reg32
4005 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4006 {
a540244d
L		 4007 as_bad (_("`%s%s' not allowed with `%s%c'"),
4008 register_prefix,
29b0f896
AM		 4009 i.op[op].regs->reg_name,
4010 i.tm.name,
4011 i.suffix);
4012 return 0;
4013 }
4014 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4015 else if ((i.types[op].bitfield.reg16
4016 || i.types[op].bitfield.reg32)
4017 && (i.tm.operand_types[op].bitfield.reg32
4018 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4019 {
4020 /* Prohibit these changes in the 64bit mode, since the
4021 lowering is more complicated. */
34828aad 4022 if (intel_syntax
ca61edf2 4023 && i.tm.opcode_modifier.todword
40fb9820 4024 && !i.types[0].bitfield.regxmm)
34828aad 4025 {
ca61edf2 4026 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4027 i.suffix = LONG_MNEM_SUFFIX;
4028 }
4029 else
4030 {
4031 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4032 register_prefix, i.op[op].regs->reg_name,
4033 i.suffix);
4034 return 0;
4035 }
252b5132 4036 }
29b0f896
AM		 4037 return 1;
4038}
252b5132 4039
29b0f896 4040static int
e3bb37b5 4041check_word_reg (void)
29b0f896
AM		 4042{
4043 int op;
4044 for (op = i.operands; --op >= 0;)
4045 /* Reject eight bit registers, except where the template requires
4046 them. (eg. movzb) */
40fb9820
L		 4047 if (i.types[op].bitfield.reg8
4048 && (i.tm.operand_types[op].bitfield.reg16
4049 || i.tm.operand_types[op].bitfield.reg32
4050 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4051 {
a540244d
L		 4052 as_bad (_("`%s%s' not allowed with `%s%c'"),
4053 register_prefix,
29b0f896
AM		 4054 i.op[op].regs->reg_name,
4055 i.tm.name,
4056 i.suffix);
4057 return 0;
4058 }
4059 /* Warn if the e prefix on a general reg is present. */
4060 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4061 && i.types[op].bitfield.reg32
4062 && (i.tm.operand_types[op].bitfield.reg16
4063 || i.tm.operand_types[op].bitfield.acc))
252b5132 4064 {
29b0f896
AM		 4065 /* Prohibit these changes in the 64bit mode, since the
4066 lowering is more complicated. */
4067 if (flag_code == CODE_64BIT)
252b5132 4068 {
2ca3ace5
L		 4069 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4070 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4071 i.suffix);
4072 return 0;
252b5132 4073 }
29b0f896
AM		 4074 else
4075#if REGISTER_WARNINGS
a540244d
L		 4076 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4077 register_prefix,
29b0f896 4078 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4079 register_prefix,
29b0f896
AM		 4080 i.op[op].regs->reg_name,
4081 i.suffix);
4082#endif
4083 }
4084 return 1;
4085}
252b5132 4086
29b0f896 4087static int
40fb9820 4088update_imm (unsigned int j)
29b0f896 4089{
40fb9820
L		 4090 i386_operand_type overlap;
4091
c6fb90c8 4092 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
40fb9820
L		 4093 if ((overlap.bitfield.imm8
4094 || overlap.bitfield.imm8s
4095 || overlap.bitfield.imm16
4096 || overlap.bitfield.imm32
4097 || overlap.bitfield.imm32s
4098 || overlap.bitfield.imm64)
0dfbf9d7
L		 4099 && !operand_type_equal (&overlap, &imm8)
4100 && !operand_type_equal (&overlap, &imm8s)
4101 && !operand_type_equal (&overlap, &imm16)
4102 && !operand_type_equal (&overlap, &imm32)
4103 && !operand_type_equal (&overlap, &imm32s)
4104 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4105 {
4106 if (i.suffix)
4107 {
40fb9820
L		 4108 i386_operand_type temp;
4109
0dfbf9d7 4110 operand_type_set (&temp, 0);
40fb9820
L		 4111 if (i.suffix == BYTE_MNEM_SUFFIX)
4112 {
4113 temp.bitfield.imm8 = overlap.bitfield.imm8;
4114 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4115 }
4116 else if (i.suffix == WORD_MNEM_SUFFIX)
4117 temp.bitfield.imm16 = overlap.bitfield.imm16;
4118 else if (i.suffix == QWORD_MNEM_SUFFIX)
4119 {
4120 temp.bitfield.imm64 = overlap.bitfield.imm64;
4121 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4122 }
4123 else
4124 temp.bitfield.imm32 = overlap.bitfield.imm32;
4125 overlap = temp;
29b0f896 4126 }
0dfbf9d7
L		 4127 else if (operand_type_equal (&overlap, &imm16_32_32s)
4128 || operand_type_equal (&overlap, &imm16_32)
4129 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4130 {
40fb9820 4131 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4132 overlap = imm16;
40fb9820 4133 else
65da13b5 4134 overlap = imm32s;
29b0f896 4135 }
0dfbf9d7
L		 4136 if (!operand_type_equal (&overlap, &imm8)
4137 && !operand_type_equal (&overlap, &imm8s)
4138 && !operand_type_equal (&overlap, &imm16)
4139 && !operand_type_equal (&overlap, &imm32)
4140 && !operand_type_equal (&overlap, &imm32s)
4141 && !operand_type_equal (&overlap, &imm64))
29b0f896 4142 {
4eed87de
AM		 4143 as_bad (_("no instruction mnemonic suffix given; "
4144 "can't determine immediate size"));
29b0f896
AM		 4145 return 0;
4146 }
4147 }
40fb9820 4148 i.types[j] = overlap;
29b0f896 4149
40fb9820
L		 4150 return 1;
4151}
4152
4153static int
4154finalize_imm (void)
4155{
4156 unsigned int j;
29b0f896 4157
40fb9820
L		 4158 for (j = 0; j < 2; j++)
4159 if (update_imm (j) == 0)
4160 return 0;
4161
c6fb90c8 4162 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
40fb9820 4163 assert (operand_type_check (i.types[2], imm) == 0);
29b0f896
AM		 4164
4165 return 1;
4166}
4167
85f10a01
MM		 4168static void
4169process_drex (void)
4170{
5dd15031
JJ		 4171 i.drex.modrm_reg = 0;
4172 i.drex.modrm_regmem = 0;
85f10a01
MM		 4173
4174 /* SSE5 4 operand instructions must have the destination the same as
4175 one of the inputs. Figure out the destination register and cache
4176 it away in the drex field, and remember which fields to use for
4177 the modrm byte. */
4178 if (i.tm.opcode_modifier.drex
4179 && i.tm.opcode_modifier.drexv
4180 && i.operands == 4)
4181 {
4182 i.tm.extension_opcode = None;
4183
4184 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4185 if (i.types[0].bitfield.regxmm != 0
4186 && i.types[1].bitfield.regxmm != 0
4187 && i.types[2].bitfield.regxmm != 0
4188 && i.types[3].bitfield.regxmm != 0
4189 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4190 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4191 {
4192 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4193 operand_type_set (&i.types[0], 0);
4194 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4195 i.reg_operands -= 2;
4196
4197 /* There are two different ways to encode a 4 operand
4198 instruction with all registers that uses OC1 set to
4199 0 or 1. Favor setting OC1 to 0 since this mimics the
4200 actions of other SSE5 assemblers. Use modrm encoding 2
4201 for register/register. Include the high order bit that
4202 is normally stored in the REX byte in the register
4203 field. */
4204 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4205 i.drex.modrm_reg = 2;
4206 i.drex.modrm_regmem = 1;
4207 i.drex.reg = (i.op[3].regs->reg_num
4208 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4209 }
4210
4211 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4212 else if (i.types[0].bitfield.regxmm != 0
4213 && i.types[1].bitfield.regxmm != 0
4214 && (i.types[2].bitfield.regxmm
4215 || operand_type_check (i.types[2], anymem))
4216 && i.types[3].bitfield.regxmm != 0
4217 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4218 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4219 {
4220 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4221 operand_type_set (&i.types[0], 0);
4222 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4223 i.reg_operands -= 2;
4224
4225 /* Specify the modrm encoding for memory addressing. Include
4226 the high order bit that is normally stored in the REX byte
4227 in the register field. */
4228 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
4229 i.drex.modrm_reg = 1;
4230 i.drex.modrm_regmem = 2;
4231 i.drex.reg = (i.op[3].regs->reg_num
4232 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4233 }
4234
4235 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4236 else if (i.types[0].bitfield.regxmm != 0
4237 && operand_type_check (i.types[1], anymem) != 0
4238 && i.types[2].bitfield.regxmm != 0
4239 && i.types[3].bitfield.regxmm != 0
4240 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4241 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4242 {
4243 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4244 operand_type_set (&i.types[0], 0);
4245 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4246 i.reg_operands -= 2;
4247
4248 /* Specify the modrm encoding for memory addressing. Include
4249 the high order bit that is normally stored in the REX byte
4250 in the register field. */
4251 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4252 i.drex.modrm_reg = 2;
4253 i.drex.modrm_regmem = 1;
4254 i.drex.reg = (i.op[3].regs->reg_num
4255 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4256 }
4257
4258 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4259 else if (i.types[0].bitfield.regxmm != 0
4260 && i.types[1].bitfield.regxmm != 0
4261 && i.types[2].bitfield.regxmm != 0
4262 && i.types[3].bitfield.regxmm != 0
4263 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4264 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4265 {
4266 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4267 operand_type_set (&i.types[2], 0);
4268 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4269 i.reg_operands -= 2;
4270
4271 /* There are two different ways to encode a 4 operand
4272 instruction with all registers that uses OC1 set to
4273 0 or 1. Favor setting OC1 to 0 since this mimics the
4274 actions of other SSE5 assemblers. Use modrm encoding
4275 2 for register/register. Include the high order bit that
4276 is normally stored in the REX byte in the register
4277 field. */
4278 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4279 i.drex.modrm_reg = 1;
4280 i.drex.modrm_regmem = 0;
4281
4282 /* Remember the register, including the upper bits */
4283 i.drex.reg = (i.op[3].regs->reg_num
4284 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4285 }
4286
4287 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4288 else if (i.types[0].bitfield.regxmm != 0
4289 && (i.types[1].bitfield.regxmm
4290 || operand_type_check (i.types[1], anymem))
4291 && i.types[2].bitfield.regxmm != 0
4292 && i.types[3].bitfield.regxmm != 0
4293 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4294 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4295 {
4296 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4297 operand_type_set (&i.types[2], 0);
4298 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4299 i.reg_operands -= 2;
4300
4301 /* Specify the modrm encoding and remember the register
4302 including the bits normally stored in the REX byte. */
4303 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4304 i.drex.modrm_reg = 0;
4305 i.drex.modrm_regmem = 1;
4306 i.drex.reg = (i.op[3].regs->reg_num
4307 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4308 }
4309
4310 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4311 else if (operand_type_check (i.types[0], anymem) != 0
4312 && i.types[1].bitfield.regxmm != 0
4313 && i.types[2].bitfield.regxmm != 0
4314 && i.types[3].bitfield.regxmm != 0
4315 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4316 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4317 {
4318 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4319 operand_type_set (&i.types[2], 0);
4320 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4321 i.reg_operands -= 2;
4322
4323 /* Specify the modrm encoding and remember the register
4324 including the bits normally stored in the REX byte. */
4325 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4326 i.drex.modrm_reg = 1;
4327 i.drex.modrm_regmem = 0;
4328 i.drex.reg = (i.op[3].regs->reg_num
4329 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4330 }
4331
4332 else
4333 as_bad (_("Incorrect operands for the '%s' instruction"),
4334 i.tm.name);
4335 }
4336
4337 /* SSE5 instructions with the DREX byte where the only memory operand
4338 is in the 2nd argument, and the first and last xmm register must
4339 match, and is encoded in the DREX byte. */
4340 else if (i.tm.opcode_modifier.drex
4341 && !i.tm.opcode_modifier.drexv
4342 && i.operands == 4)
4343 {
4344 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4345 if (i.types[0].bitfield.regxmm != 0
4346 && (i.types[1].bitfield.regxmm
4347 || operand_type_check(i.types[1], anymem))
4348 && i.types[2].bitfield.regxmm != 0
4349 && i.types[3].bitfield.regxmm != 0
4350 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4351 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4352 {
4353 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4354 operand_type_set (&i.types[0], 0);
4355 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4356 i.reg_operands -= 2;
4357
4358 /* Specify the modrm encoding and remember the register
4359 including the high bit normally stored in the REX
4360 byte. */
4361 i.drex.modrm_reg = 2;
4362 i.drex.modrm_regmem = 1;
4363 i.drex.reg = (i.op[3].regs->reg_num
4364 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4365 }
4366
4367 else
4368 as_bad (_("Incorrect operands for the '%s' instruction"),
4369 i.tm.name);
4370 }
4371
4372 /* SSE5 3 operand instructions that the result is a register, being
4373 either operand can be a memory operand, using OC0 to note which
4374 one is the memory. */
4375 else if (i.tm.opcode_modifier.drex
4376 && i.tm.opcode_modifier.drexv
4377 && i.operands == 3)
4378 {
4379 i.tm.extension_opcode = None;
4380
4381 /* Case 1: 3 operand insn, src1 = register. */
4382 if (i.types[0].bitfield.regxmm != 0
4383 && i.types[1].bitfield.regxmm != 0
4384 && i.types[2].bitfield.regxmm != 0)
4385 {
4386 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4387 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4388 i.reg_operands--;
4389
4390 /* Specify the modrm encoding and remember the register
4391 including the high bit normally stored in the REX byte. */
4392 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4393 i.drex.modrm_reg = 1;
4394 i.drex.modrm_regmem = 0;
4395 i.drex.reg = (i.op[2].regs->reg_num
4396 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4397 }
4398
4399 /* Case 2: 3 operand insn, src1 = memory. */
4400 else if (operand_type_check (i.types[0], anymem) != 0
4401 && i.types[1].bitfield.regxmm != 0
4402 && i.types[2].bitfield.regxmm != 0)
4403 {
4404 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4405 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4406 i.reg_operands--;
4407
4408 /* Specify the modrm encoding and remember the register
4409 including the high bit normally stored in the REX
4410 byte. */
4411 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4412 i.drex.modrm_reg = 1;
4413 i.drex.modrm_regmem = 0;
4414 i.drex.reg = (i.op[2].regs->reg_num
4415 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4416 }
4417
4418 /* Case 3: 3 operand insn, src2 = memory. */
4419 else if (i.types[0].bitfield.regxmm != 0
4420 && operand_type_check (i.types[1], anymem) != 0
4421 && i.types[2].bitfield.regxmm != 0)
4422 {
4423 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4424 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4425 i.reg_operands--;
4426
4427 /* Specify the modrm encoding and remember the register
4428 including the high bit normally stored in the REX byte. */
4429 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4430 i.drex.modrm_reg = 0;
4431 i.drex.modrm_regmem = 1;
4432 i.drex.reg = (i.op[2].regs->reg_num
4433 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4434 }
4435
4436 else
4437 as_bad (_("Incorrect operands for the '%s' instruction"),
4438 i.tm.name);
4439 }
4440
4441 /* SSE5 4 operand instructions that are the comparison instructions
4442 where the first operand is the immediate value of the comparison
4443 to be done. */
4444 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4445 {
4446 /* Case 1: 4 operand insn, src1 = reg/memory. */
4447 if (operand_type_check (i.types[0], imm) != 0
4448 && (i.types[1].bitfield.regxmm
4449 || operand_type_check (i.types[1], anymem))
4450 && i.types[2].bitfield.regxmm != 0
4451 && i.types[3].bitfield.regxmm != 0)
4452 {
4453 /* clear the arguments that are stored in drex */
0dfbf9d7 4454 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4455 i.reg_operands--;
4456
4457 /* Specify the modrm encoding and remember the register
4458 including the high bit normally stored in the REX byte. */
4459 i.drex.modrm_reg = 2;
4460 i.drex.modrm_regmem = 1;
4461 i.drex.reg = (i.op[3].regs->reg_num
4462 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4463 }
4464
4465 /* Case 2: 3 operand insn with ImmExt that places the
4466 opcode_extension as an immediate argument. This is used for
4467 all of the varients of comparison that supplies the appropriate
4468 value as part of the instruction. */
4469 else if ((i.types[0].bitfield.regxmm
4470 || operand_type_check (i.types[0], anymem))
4471 && i.types[1].bitfield.regxmm != 0
4472 && i.types[2].bitfield.regxmm != 0
4473 && operand_type_check (i.types[3], imm) != 0)
4474 {
4475 /* clear the arguments that are stored in drex */
0dfbf9d7 4476 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4477 i.reg_operands--;
4478
4479 /* Specify the modrm encoding and remember the register
4480 including the high bit normally stored in the REX byte. */
4481 i.drex.modrm_reg = 1;
4482 i.drex.modrm_regmem = 0;
4483 i.drex.reg = (i.op[2].regs->reg_num
4484 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4485 }
4486
4487 else
4488 as_bad (_("Incorrect operands for the '%s' instruction"),
4489 i.tm.name);
4490 }
4491
4492 else if (i.tm.opcode_modifier.drex
4493 || i.tm.opcode_modifier.drexv
4494 || i.tm.opcode_modifier.drexc)
4495 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4496}
4497
29b0f896 4498static int
e3bb37b5 4499process_operands (void)
29b0f896
AM		 4500{
4501 /* Default segment register this instruction will use for memory
4502 accesses. 0 means unknown. This is only for optimizing out
4503 unnecessary segment overrides. */
4504 const seg_entry *default_seg = 0;
4505
85f10a01
MM		 4506 /* Handle all of the DREX munging that SSE5 needs. */
4507 if (i.tm.opcode_modifier.drex
4508 || i.tm.opcode_modifier.drexv
4509 || i.tm.opcode_modifier.drexc)
4510 process_drex ();
4511
e2ec9d29 4512 if (i.tm.opcode_modifier.firstxmm0)
29b0f896 4513 {
9fcfb3d7
L		 4514 unsigned int j;
4515
e2ec9d29 4516 /* The first operand is implicit and must be xmm0. */
0dfbf9d7
L		 4517 assert (i.reg_operands
4518 && operand_type_equal (&i.types[0], &regxmm));
e2ec9d29
L		 4519 if (i.op[0].regs->reg_num != 0)
4520 {
4521 if (intel_syntax)
4522 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4523 i.tm.name, register_prefix);
4524 else
4525 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4526 i.tm.name, register_prefix);
4527 return 0;
4528 }
9fcfb3d7
L		 4529
4530 for (j = 1; j < i.operands; j++)
4531 {
4532 i.op[j - 1] = i.op[j];
4533 i.types[j - 1] = i.types[j];
4534
4535 /* We need to adjust fields in i.tm since they are used by
4536 build_modrm_byte. */
4537 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4538 }
4539
e2ec9d29
L		 4540 i.operands--;
4541 i.reg_operands--;
e2ec9d29
L		 4542 i.tm.operands--;
4543 }
4544 else if (i.tm.opcode_modifier.regkludge)
4545 {
4546 /* The imul $imm, %reg instruction is converted into
4547 imul $imm, %reg, %reg, and the clr %reg instruction
4548 is converted into xor %reg, %reg. */
4549
4550 unsigned int first_reg_op;
4551
4552 if (operand_type_check (i.types[0], reg))
4553 first_reg_op = 0;
4554 else
4555 first_reg_op = 1;
4556 /* Pretend we saw the extra register operand. */
4557 assert (i.reg_operands == 1
4558 && i.op[first_reg_op + 1].regs == 0);
4559 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4560 i.types[first_reg_op + 1] = i.types[first_reg_op];
4561 i.operands++;
4562 i.reg_operands++;
29b0f896
AM		 4563 }
4564
40fb9820 4565 if (i.tm.opcode_modifier.shortform)
29b0f896 4566 {
40fb9820
L		 4567 if (i.types[0].bitfield.sreg2
4568 || i.types[0].bitfield.sreg3)
29b0f896 4569 {
4eed87de
AM		 4570 if (i.tm.base_opcode == POP_SEG_SHORT
4571 && i.op[0].regs->reg_num == 1)
29b0f896 4572 {
4eed87de
AM		 4573 as_bad (_("you can't `pop %%cs'"));
4574 return 0;
29b0f896 4575 }
4eed87de
AM		 4576 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4577 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4578 i.rex |= REX_B;
4eed87de
AM		 4579 }
4580 else
4581 {
85f10a01
MM		 4582 /* The register or float register operand is in operand
4583 0 or 1. */
40fb9820
L		 4584 unsigned int op;
4585
4586 if (i.types[0].bitfield.floatreg
4587 || operand_type_check (i.types[0], reg))
4588 op = 0;
4589 else
4590 op = 1;
4eed87de
AM		 4591 /* Register goes in low 3 bits of opcode. */
4592 i.tm.base_opcode |= i.op[op].regs->reg_num;
4593 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4594 i.rex |= REX_B;
40fb9820 4595 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4596 {
4eed87de
AM		 4597 /* Warn about some common errors, but press on regardless.
4598 The first case can be generated by gcc (<= 2.8.1). */
4599 if (i.operands == 2)
4600 {
4601 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 4602 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4603 register_prefix, i.op[1].regs->reg_name,
4604 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 4605 }
4606 else
4607 {
4608 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4609 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4610 register_prefix, i.op[0].regs->reg_name);
4eed87de 4611 }
29b0f896
AM		 4612 }
4613 }
4614 }
40fb9820 4615 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4616 {
4617 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4618 must be put into the modrm byte). Now, we make the modrm and
4619 index base bytes based on all the info we've collected. */
29b0f896
AM		 4620
4621 default_seg = build_modrm_byte ();
4622 }
8a2ed489 4623 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4624 {
4625 default_seg = &ds;
4626 }
40fb9820 4627 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4628 {
4629 /* For the string instructions that allow a segment override
4630 on one of their operands, the default segment is ds. */
4631 default_seg = &ds;
4632 }
4633
75178d9d
L		 4634 if (i.tm.base_opcode == 0x8d /* lea */
4635 && i.seg[0]
4636 && !quiet_warnings)
30123838 4637 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 4638
4639 /* If a segment was explicitly specified, and the specified segment
4640 is not the default, use an opcode prefix to select it. If we
4641 never figured out what the default segment is, then default_seg
4642 will be zero at this point, and the specified segment prefix will
4643 always be used. */
29b0f896
AM		 4644 if ((i.seg[0]) && (i.seg[0] != default_seg))
4645 {
4646 if (!add_prefix (i.seg[0]->seg_prefix))
4647 return 0;
4648 }
4649 return 1;
4650}
4651
4652static const seg_entry *
e3bb37b5 4653build_modrm_byte (void)
29b0f896
AM		 4654{
4655 const seg_entry *default_seg = 0;
4656
85f10a01
MM		 4657 /* SSE5 4 operand instructions are encoded in such a way that one of
4658 the inputs must match the destination register. Process_drex hides
4659 the 3rd argument in the drex field, so that by the time we get
4660 here, it looks to GAS as if this is a 2 operand instruction. */
4661 if ((i.tm.opcode_modifier.drex
4662 || i.tm.opcode_modifier.drexv
b5016f89 4663 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4664 && i.reg_operands == 2)
4665 {
4666 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
4667 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
4668
4669 i.rm.reg = reg->reg_num;
4670 i.rm.regmem = regmem->reg_num;
4671 i.rm.mode = 3;
4672 if ((reg->reg_flags & RegRex) != 0)
4673 i.rex |= REX_R;
4674 if ((regmem->reg_flags & RegRex) != 0)
4675 i.rex |= REX_B;
4676 }
4677
29b0f896
AM		 4678 /* i.reg_operands MUST be the number of real register operands;
4679 implicit registers do not count. */
85f10a01 4680 else if (i.reg_operands == 2)
29b0f896
AM		 4681 {
4682 unsigned int source, dest;
cab737b9
L		 4683
4684 switch (i.operands)
4685 {
4686 case 2:
4687 source = 0;
4688 break;
4689 case 3:
c81128dc
L		 4690 /* When there are 3 operands, one of them may be immediate,
4691 which may be the first or the last operand. Otherwise,
4692 the first operand must be shift count register (cl). */
4693 assert (i.imm_operands == 1
4694 || (i.imm_operands == 0
40fb9820
L		 4695 && i.types[0].bitfield.shiftcount));
4696 if (operand_type_check (i.types[0], imm)
4697 || i.types[0].bitfield.shiftcount)
4698 source = 1;
4699 else
4700 source = 0;
cab737b9
L		 4701 break;
4702 case 4:
368d64cc
L		 4703 /* When there are 4 operands, the first two must be 8bit
4704 immediate operands. The source operand will be the 3rd
4705 one. */
cab737b9 4706 assert (i.imm_operands == 2
368d64cc
L		 4707 && i.types[0].bitfield.imm8
4708 && i.types[1].bitfield.imm8);
cab737b9
L		 4709 source = 2;
4710 break;
4711 default:
4712 abort ();
4713 }
4714
29b0f896
AM		 4715 dest = source + 1;
4716
4717 i.rm.mode = 3;
4718 /* One of the register operands will be encoded in the i.tm.reg
4719 field, the other in the combined i.tm.mode and i.tm.regmem
4720 fields. If no form of this instruction supports a memory
4721 destination operand, then we assume the source operand may
4722 sometimes be a memory operand and so we need to store the
4723 destination in the i.rm.reg field. */
40fb9820
L		 4724 if (!i.tm.operand_types[dest].bitfield.regmem
4725 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 4726 {
4727 i.rm.reg = i.op[dest].regs->reg_num;
4728 i.rm.regmem = i.op[source].regs->reg_num;
4729 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4730 i.rex |= REX_R;
29b0f896 4731 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4732 i.rex |= REX_B;
29b0f896
AM		 4733 }
4734 else
4735 {
4736 i.rm.reg = i.op[source].regs->reg_num;
4737 i.rm.regmem = i.op[dest].regs->reg_num;
4738 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4739 i.rex |= REX_B;
29b0f896 4740 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4741 i.rex |= REX_R;
29b0f896 4742 }
161a04f6 4743 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 4744 {
40fb9820
L		 4745 if (!i.types[0].bitfield.control
4746 && !i.types[1].bitfield.control)
c4a530c5 4747 abort ();
161a04f6 4748 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 4749 add_prefix (LOCK_PREFIX_OPCODE);
4750 }
29b0f896
AM		 4751 }
4752 else
4753 { /* If it's not 2 reg operands... */
4754 if (i.mem_operands)
4755 {
4756 unsigned int fake_zero_displacement = 0;
99018f42 4757 unsigned int op;
4eed87de 4758
85f10a01
MM		 4759 /* This has been precalculated for SSE5 instructions
4760 that have a DREX field earlier in process_drex. */
b5016f89
L		 4761 if (i.tm.opcode_modifier.drex
4762 || i.tm.opcode_modifier.drexv
4763 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4764 op = i.drex.modrm_regmem;
4765 else
4766 {
c0209578
L		 4767 for (op = 0; op < i.operands; op++)
4768 if (operand_type_check (i.types[op], anymem))
4769 break;
4770 assert (op < i.operands);
85f10a01 4771 }
29b0f896
AM		 4772
4773 default_seg = &ds;
4774
4775 if (i.base_reg == 0)
4776 {
4777 i.rm.mode = 0;
4778 if (!i.disp_operands)
4779 fake_zero_displacement = 1;
4780 if (i.index_reg == 0)
4781 {
4782 /* Operand is just <disp> */
20f0a1fc 4783 if (flag_code == CODE_64BIT)
29b0f896
AM		 4784 {
4785 /* 64bit mode overwrites the 32bit absolute
4786 addressing by RIP relative addressing and
4787 absolute addressing is encoded by one of the
4788 redundant SIB forms. */
4789 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4790 i.sib.base = NO_BASE_REGISTER;
4791 i.sib.index = NO_INDEX_REGISTER;
fc225355 4792 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 4793 ? disp32s : disp32);
20f0a1fc 4794 }
fc225355
L		 4795 else if ((flag_code == CODE_16BIT)
4796 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 4797 {
4798 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 4799 i.types[op] = disp16;
20f0a1fc
NC		 4800 }
4801 else
4802 {
4803 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 4804 i.types[op] = disp32;
29b0f896
AM		 4805 }
4806 }
4807 else /* !i.base_reg && i.index_reg */
4808 {
db51cc60
L		 4809 if (i.index_reg->reg_num == RegEiz
4810 || i.index_reg->reg_num == RegRiz)
4811 i.sib.index = NO_INDEX_REGISTER;
4812 else
4813 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 4814 i.sib.base = NO_BASE_REGISTER;
4815 i.sib.scale = i.log2_scale_factor;
4816 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 4817 i.types[op].bitfield.disp8 = 0;
4818 i.types[op].bitfield.disp16 = 0;
4819 i.types[op].bitfield.disp64 = 0;
29b0f896 4820 if (flag_code != CODE_64BIT)
40fb9820
L		 4821 {
4822 /* Must be 32 bit */
4823 i.types[op].bitfield.disp32 = 1;
4824 i.types[op].bitfield.disp32s = 0;
4825 }
29b0f896 4826 else
40fb9820
L		 4827 {
4828 i.types[op].bitfield.disp32 = 0;
4829 i.types[op].bitfield.disp32s = 1;
4830 }
29b0f896 4831 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4832 i.rex |= REX_X;
29b0f896
AM		 4833 }
4834 }
4835 /* RIP addressing for 64bit mode. */
9a04903e
JB		 4836 else if (i.base_reg->reg_num == RegRip ||
4837 i.base_reg->reg_num == RegEip)
29b0f896
AM		 4838 {
4839 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 4840 i.types[op].bitfield.disp8 = 0;
4841 i.types[op].bitfield.disp16 = 0;
4842 i.types[op].bitfield.disp32 = 0;
4843 i.types[op].bitfield.disp32s = 1;
4844 i.types[op].bitfield.disp64 = 0;
71903a11 4845 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 4846 if (! i.disp_operands)
4847 fake_zero_displacement = 1;
29b0f896 4848 }
40fb9820 4849 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 4850 {
4851 switch (i.base_reg->reg_num)
4852 {
4853 case 3: /* (%bx) */
4854 if (i.index_reg == 0)
4855 i.rm.regmem = 7;
4856 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4857 i.rm.regmem = i.index_reg->reg_num - 6;
4858 break;
4859 case 5: /* (%bp) */
4860 default_seg = &ss;
4861 if (i.index_reg == 0)
4862 {
4863 i.rm.regmem = 6;
40fb9820 4864 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 4865 {
4866 /* fake (%bp) into 0(%bp) */
40fb9820 4867 i.types[op].bitfield.disp8 = 1;
252b5132 4868 fake_zero_displacement = 1;
29b0f896
AM		 4869 }
4870 }
4871 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4872 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4873 break;
4874 default: /* (%si) -> 4 or (%di) -> 5 */
4875 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4876 }
4877 i.rm.mode = mode_from_disp_size (i.types[op]);
4878 }
4879 else /* i.base_reg and 32/64 bit mode */
4880 {
4881 if (flag_code == CODE_64BIT
40fb9820
L		 4882 && operand_type_check (i.types[op], disp))
4883 {
4884 i386_operand_type temp;
0dfbf9d7 4885 operand_type_set (&temp, 0);
40fb9820
L		 4886 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4887 i.types[op] = temp;
4888 if (i.prefix[ADDR_PREFIX] == 0)
4889 i.types[op].bitfield.disp32s = 1;
4890 else
4891 i.types[op].bitfield.disp32 = 1;
4892 }
20f0a1fc 4893
29b0f896
AM		 4894 i.rm.regmem = i.base_reg->reg_num;
4895 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 4896 i.rex |= REX_B;
29b0f896
AM		 4897 i.sib.base = i.base_reg->reg_num;
4898 /* x86-64 ignores REX prefix bit here to avoid decoder
4899 complications. */
4900 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4901 {
4902 default_seg = &ss;
4903 if (i.disp_operands == 0)
4904 {
4905 fake_zero_displacement = 1;
40fb9820 4906 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 4907 }
4908 }
4909 else if (i.base_reg->reg_num == ESP_REG_NUM)
4910 {
4911 default_seg = &ss;
4912 }
4913 i.sib.scale = i.log2_scale_factor;
4914 if (i.index_reg == 0)
4915 {
4916 /* <disp>(%esp) becomes two byte modrm with no index
4917 register. We've already stored the code for esp
4918 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4919 Any base register besides %esp will not use the
4920 extra modrm byte. */
4921 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 4922 }
4923 else
4924 {
db51cc60
L		 4925 if (i.index_reg->reg_num == RegEiz
4926 || i.index_reg->reg_num == RegRiz)
4927 i.sib.index = NO_INDEX_REGISTER;
4928 else
4929 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 4930 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4931 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4932 i.rex |= REX_X;
29b0f896 4933 }
67a4f2b7
AO		 4934
4935 if (i.disp_operands
4936 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4937 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4938 i.rm.mode = 0;
4939 else
4940 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 4941 }
252b5132 4942
29b0f896
AM		 4943 if (fake_zero_displacement)
4944 {
4945 /* Fakes a zero displacement assuming that i.types[op]
4946 holds the correct displacement size. */
4947 expressionS *exp;
4948
4949 assert (i.op[op].disps == 0);
4950 exp = &disp_expressions[i.disp_operands++];
4951 i.op[op].disps = exp;
4952 exp->X_op = O_constant;
4953 exp->X_add_number = 0;
4954 exp->X_add_symbol = (symbolS *) 0;
4955 exp->X_op_symbol = (symbolS *) 0;
4956 }
4957 }
252b5132 4958
29b0f896
AM		 4959 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4960 (if any) based on i.tm.extension_opcode. Again, we must be
4961 careful to make sure that segment/control/debug/test/MMX
4962 registers are coded into the i.rm.reg field. */
4963 if (i.reg_operands)
4964 {
99018f42
L		 4965 unsigned int op;
4966
85f10a01
MM		 4967 /* This has been precalculated for SSE5 instructions
4968 that have a DREX field earlier in process_drex. */
b5016f89
L		 4969 if (i.tm.opcode_modifier.drex
4970 || i.tm.opcode_modifier.drexv
4971 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4972 {
4973 op = i.drex.modrm_reg;
4974 i.rm.reg = i.op[op].regs->reg_num;
4975 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4976 i.rex |= REX_R;
4977 }
4978 else
4979 {
c0209578
L		 4980 for (op = 0; op < i.operands; op++)
4981 if (i.types[op].bitfield.reg8
4982 || i.types[op].bitfield.reg16
4983 || i.types[op].bitfield.reg32
4984 || i.types[op].bitfield.reg64
4985 || i.types[op].bitfield.regmmx
4986 || i.types[op].bitfield.regxmm
4987 || i.types[op].bitfield.sreg2
4988 || i.types[op].bitfield.sreg3
4989 || i.types[op].bitfield.control
4990 || i.types[op].bitfield.debug
4991 || i.types[op].bitfield.test)
4992 break;
4993
4994 assert (op < i.operands);
99018f42 4995
85f10a01
MM		 4996 /* If there is an extension opcode to put here, the
4997 register number must be put into the regmem field. */
c0209578
L		 4998 if (i.tm.extension_opcode != None)
4999 {
5000 i.rm.regmem = i.op[op].regs->reg_num;
5001 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5002 i.rex |= REX_B;
5003 }
5004 else
5005 {
5006 i.rm.reg = i.op[op].regs->reg_num;
5007 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5008 i.rex |= REX_R;
5009 }
85f10a01 5010 }
252b5132 5011
29b0f896
AM		 5012 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5013 must set it to 3 to indicate this is a register operand
5014 in the regmem field. */
5015 if (!i.mem_operands)
5016 i.rm.mode = 3;
5017 }
252b5132 5018
29b0f896 5019 /* Fill in i.rm.reg field with extension opcode (if any). */
85f10a01
MM		 5020 if (i.tm.extension_opcode != None
5021 && !(i.tm.opcode_modifier.drex
5022 || i.tm.opcode_modifier.drexv
5023 || i.tm.opcode_modifier.drexc))
29b0f896
AM		 5024 i.rm.reg = i.tm.extension_opcode;
5025 }
5026 return default_seg;
5027}
252b5132 5028
29b0f896 5029static void
e3bb37b5 5030output_branch (void)
29b0f896
AM		 5031{
5032 char *p;
5033 int code16;
5034 int prefix;
5035 relax_substateT subtype;
5036 symbolS *sym;
5037 offsetT off;
5038
5039 code16 = 0;
5040 if (flag_code == CODE_16BIT)
5041 code16 = CODE16;
5042
5043 prefix = 0;
5044 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5045 {
29b0f896
AM		 5046 prefix = 1;
5047 i.prefixes -= 1;
5048 code16 ^= CODE16;
252b5132 5049 }
29b0f896
AM		 5050 /* Pentium4 branch hints. */
5051 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5052 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5053 {
29b0f896
AM		 5054 prefix++;
5055 i.prefixes--;
5056 }
5057 if (i.prefix[REX_PREFIX] != 0)
5058 {
5059 prefix++;
5060 i.prefixes--;
2f66722d
AM		 5061 }
5062
29b0f896
AM		 5063 if (i.prefixes != 0 && !intel_syntax)
5064 as_warn (_("skipping prefixes on this instruction"));
5065
5066 /* It's always a symbol; End frag & setup for relax.
5067 Make sure there is enough room in this frag for the largest
5068 instruction we may generate in md_convert_frag. This is 2
5069 bytes for the opcode and room for the prefix and largest
5070 displacement. */
5071 frag_grow (prefix + 2 + 4);
5072 /* Prefix and 1 opcode byte go in fr_fix. */
5073 p = frag_more (prefix + 1);
5074 if (i.prefix[DATA_PREFIX] != 0)
5075 *p++ = DATA_PREFIX_OPCODE;
5076 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5077 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5078 *p++ = i.prefix[SEG_PREFIX];
5079 if (i.prefix[REX_PREFIX] != 0)
5080 *p++ = i.prefix[REX_PREFIX];
5081 *p = i.tm.base_opcode;
5082
5083 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5084 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5085 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5086 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5087 else
5088 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5089 subtype |= code16;
3e73aa7c 5090
29b0f896
AM		 5091 sym = i.op[0].disps->X_add_symbol;
5092 off = i.op[0].disps->X_add_number;
3e73aa7c 5093
29b0f896
AM		 5094 if (i.op[0].disps->X_op != O_constant
5095 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5096 {
29b0f896
AM		 5097 /* Handle complex expressions. */
5098 sym = make_expr_symbol (i.op[0].disps);
5099 off = 0;
5100 }
3e73aa7c 5101
29b0f896
AM		 5102 /* 1 possible extra opcode + 4 byte displacement go in var part.
5103 Pass reloc in fr_var. */
5104 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5105}
3e73aa7c 5106
29b0f896 5107static void
e3bb37b5 5108output_jump (void)
29b0f896
AM		 5109{
5110 char *p;
5111 int size;
3e02c1cc 5112 fixS *fixP;
29b0f896 5113
40fb9820 5114 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5115 {
5116 /* This is a loop or jecxz type instruction. */
5117 size = 1;
5118 if (i.prefix[ADDR_PREFIX] != 0)
5119 {
5120 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5121 i.prefixes -= 1;
5122 }
5123 /* Pentium4 branch hints. */
5124 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5125 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5126 {
5127 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5128 i.prefixes--;
3e73aa7c
JH		 5129 }
5130 }
29b0f896
AM		 5131 else
5132 {
5133 int code16;
3e73aa7c 5134
29b0f896
AM		 5135 code16 = 0;
5136 if (flag_code == CODE_16BIT)
5137 code16 = CODE16;
3e73aa7c 5138
29b0f896
AM		 5139 if (i.prefix[DATA_PREFIX] != 0)
5140 {
5141 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5142 i.prefixes -= 1;
5143 code16 ^= CODE16;
5144 }
252b5132 5145
29b0f896
AM		 5146 size = 4;
5147 if (code16)
5148 size = 2;
5149 }
9fcc94b6 5150
29b0f896
AM		 5151 if (i.prefix[REX_PREFIX] != 0)
5152 {
5153 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5154 i.prefixes -= 1;
5155 }
252b5132 5156
29b0f896
AM		 5157 if (i.prefixes != 0 && !intel_syntax)
5158 as_warn (_("skipping prefixes on this instruction"));
e0890092 5159
29b0f896
AM		 5160 p = frag_more (1 + size);
5161 *p++ = i.tm.base_opcode;
e0890092 5162
3e02c1cc
AM		 5163 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5164 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5165
5166 /* All jumps handled here are signed, but don't use a signed limit
5167 check for 32 and 16 bit jumps as we want to allow wrap around at
5168 4G and 64k respectively. */
5169 if (size == 1)
5170 fixP->fx_signed = 1;
29b0f896 5171}
e0890092 5172
29b0f896 5173static void
e3bb37b5 5174output_interseg_jump (void)
29b0f896
AM		 5175{
5176 char *p;
5177 int size;
5178 int prefix;
5179 int code16;
252b5132 5180
29b0f896
AM		 5181 code16 = 0;
5182 if (flag_code == CODE_16BIT)
5183 code16 = CODE16;
a217f122 5184
29b0f896
AM		 5185 prefix = 0;
5186 if (i.prefix[DATA_PREFIX] != 0)
5187 {
5188 prefix = 1;
5189 i.prefixes -= 1;
5190 code16 ^= CODE16;
5191 }
5192 if (i.prefix[REX_PREFIX] != 0)
5193 {
5194 prefix++;
5195 i.prefixes -= 1;
5196 }
252b5132 5197
29b0f896
AM		 5198 size = 4;
5199 if (code16)
5200 size = 2;
252b5132 5201
29b0f896
AM		 5202 if (i.prefixes != 0 && !intel_syntax)
5203 as_warn (_("skipping prefixes on this instruction"));
252b5132 5204
29b0f896
AM		 5205 /* 1 opcode; 2 segment; offset */
5206 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5207
29b0f896
AM		 5208 if (i.prefix[DATA_PREFIX] != 0)
5209 *p++ = DATA_PREFIX_OPCODE;
252b5132 5210
29b0f896
AM		 5211 if (i.prefix[REX_PREFIX] != 0)
5212 *p++ = i.prefix[REX_PREFIX];
252b5132 5213
29b0f896
AM		 5214 *p++ = i.tm.base_opcode;
5215 if (i.op[1].imms->X_op == O_constant)
5216 {
5217 offsetT n = i.op[1].imms->X_add_number;
252b5132 5218
29b0f896
AM		 5219 if (size == 2
5220 && !fits_in_unsigned_word (n)
5221 && !fits_in_signed_word (n))
5222 {
5223 as_bad (_("16-bit jump out of range"));
5224 return;
5225 }
5226 md_number_to_chars (p, n, size);
5227 }
5228 else
5229 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5230 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5231 if (i.op[0].imms->X_op != O_constant)
5232 as_bad (_("can't handle non absolute segment in `%s'"),
5233 i.tm.name);
5234 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5235}
a217f122 5236
29b0f896 5237static void
e3bb37b5 5238output_insn (void)
29b0f896 5239{
2bbd9c25
JJ		 5240 fragS *insn_start_frag;
5241 offsetT insn_start_off;
5242
29b0f896
AM		 5243 /* Tie dwarf2 debug info to the address at the start of the insn.
5244 We can't do this after the insn has been output as the current
5245 frag may have been closed off. eg. by frag_var. */
5246 dwarf2_emit_insn (0);
5247
2bbd9c25
JJ		 5248 insn_start_frag = frag_now;
5249 insn_start_off = frag_now_fix ();
5250
29b0f896 5251 /* Output jumps. */
40fb9820 5252 if (i.tm.opcode_modifier.jump)
29b0f896 5253 output_branch ();
40fb9820
L		 5254 else if (i.tm.opcode_modifier.jumpbyte
5255 || i.tm.opcode_modifier.jumpdword)
29b0f896 5256 output_jump ();
40fb9820 5257 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5258 output_interseg_jump ();
5259 else
5260 {
5261 /* Output normal instructions here. */
5262 char *p;
5263 unsigned char *q;
47465058 5264 unsigned int j;
331d2d0d 5265 unsigned int prefix;
4dffcebc
L		 5266
5267 switch (i.tm.opcode_length)
bc4bd9ab 5268 {
4dffcebc 5269 case 3:
331d2d0d
L		 5270 if (i.tm.base_opcode & 0xff000000)
5271 {
5272 prefix = (i.tm.base_opcode >> 24) & 0xff;
5273 goto check_prefix;
5274 }
4dffcebc
L		 5275 break;
5276 case 2:
5277 if ((i.tm.base_opcode & 0xff0000) != 0)
bc4bd9ab 5278 {
4dffcebc
L		 5279 prefix = (i.tm.base_opcode >> 16) & 0xff;
5280 if (i.tm.cpu_flags.bitfield.cpupadlock)
5281 {
5282check_prefix:
5283 if (prefix != REPE_PREFIX_OPCODE
5284 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
5285 add_prefix (prefix);
5286 }
5287 else
bc4bd9ab
MK		 5288 add_prefix (prefix);
5289 }
4dffcebc
L		 5290 break;
5291 case 1:
5292 break;
5293 default:
5294 abort ();
0f10071e 5295 }
252b5132 5296
29b0f896 5297 /* The prefix bytes. */
47465058
L		 5298 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5299 if (*q)
5300 FRAG_APPEND_1_CHAR (*q);
252b5132 5301
29b0f896 5302 /* Now the opcode; be careful about word order here! */
4dffcebc 5303 if (i.tm.opcode_length == 1)
29b0f896
AM		 5304 {
5305 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5306 }
5307 else
5308 {
4dffcebc 5309 switch (i.tm.opcode_length)
331d2d0d 5310 {
4dffcebc 5311 case 3:
331d2d0d
L		 5312 p = frag_more (3);
5313 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5314 break;
5315 case 2:
5316 p = frag_more (2);
5317 break;
5318 default:
5319 abort ();
5320 break;
331d2d0d 5321 }
0f10071e 5322
29b0f896
AM		 5323 /* Put out high byte first: can't use md_number_to_chars! */
5324 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5325 *p = i.tm.base_opcode & 0xff;
85f10a01
MM		 5326
5327 /* On SSE5, encode the OC1 bit in the DREX field if this
5328 encoding has multiple formats. */
5329 if (i.tm.opcode_modifier.drex
5330 && i.tm.opcode_modifier.drexv
5331 && DREX_OC1 (i.tm.extension_opcode))
5332 *p |= DREX_OC1_MASK;
29b0f896 5333 }
3e73aa7c 5334
29b0f896 5335 /* Now the modrm byte and sib byte (if present). */
40fb9820 5336 if (i.tm.opcode_modifier.modrm)
29b0f896 5337 {
4a3523fa
L		 5338 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5339 | i.rm.reg << 3
5340 | i.rm.mode << 6));
29b0f896
AM		 5341 /* If i.rm.regmem == ESP (4)
5342 && i.rm.mode != (Register mode)
5343 && not 16 bit
5344 ==> need second modrm byte. */
5345 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5346 && i.rm.mode != 3
40fb9820 5347 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 5348 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5349 | i.sib.index << 3
5350 | i.sib.scale << 6));
29b0f896 5351 }
3e73aa7c 5352
85f10a01
MM		 5353 /* Write the DREX byte if needed. */
5354 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5355 {
5356 p = frag_more (1);
5357 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5358
5359 /* Encode the OC0 bit if this encoding has multiple
5360 formats. */
5361 if ((i.tm.opcode_modifier.drex
5362 || i.tm.opcode_modifier.drexv)
5363 && DREX_OC0 (i.tm.extension_opcode))
5364 *p |= DREX_OC0_MASK;
5365 }
5366
29b0f896 5367 if (i.disp_operands)
2bbd9c25 5368 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5369
29b0f896 5370 if (i.imm_operands)
2bbd9c25 5371 output_imm (insn_start_frag, insn_start_off);
29b0f896 5372 }
252b5132 5373
29b0f896
AM		 5374#ifdef DEBUG386
5375 if (flag_debug)
5376 {
7b81dfbb 5377 pi ("" /*line*/, &i);
29b0f896
AM		 5378 }
5379#endif /* DEBUG386 */
5380}
252b5132 5381
e205caa7
L		 5382/* Return the size of the displacement operand N. */
5383
5384static int
5385disp_size (unsigned int n)
5386{
5387 int size = 4;
40fb9820
L		 5388 if (i.types[n].bitfield.disp64)
5389 size = 8;
5390 else if (i.types[n].bitfield.disp8)
5391 size = 1;
5392 else if (i.types[n].bitfield.disp16)
5393 size = 2;
e205caa7
L		 5394 return size;
5395}
5396
5397/* Return the size of the immediate operand N. */
5398
5399static int
5400imm_size (unsigned int n)
5401{
5402 int size = 4;
40fb9820
L		 5403 if (i.types[n].bitfield.imm64)
5404 size = 8;
5405 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5406 size = 1;
5407 else if (i.types[n].bitfield.imm16)
5408 size = 2;
e205caa7
L		 5409 return size;
5410}
5411
29b0f896 5412static void
64e74474 5413output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5414{
5415 char *p;
5416 unsigned int n;
252b5132 5417
29b0f896
AM		 5418 for (n = 0; n < i.operands; n++)
5419 {
40fb9820 5420 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 5421 {
5422 if (i.op[n].disps->X_op == O_constant)
5423 {
e205caa7 5424 int size = disp_size (n);
29b0f896 5425 offsetT val;
252b5132 5426
29b0f896
AM		 5427 val = offset_in_range (i.op[n].disps->X_add_number,
5428 size);
5429 p = frag_more (size);
5430 md_number_to_chars (p, val, size);
5431 }
5432 else
5433 {
f86103b7 5434 enum bfd_reloc_code_real reloc_type;
e205caa7 5435 int size = disp_size (n);
40fb9820 5436 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 5437 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5438
e205caa7 5439 /* We can't have 8 bit displacement here. */
40fb9820 5440 assert (!i.types[n].bitfield.disp8);
e205caa7 5441
29b0f896
AM		 5442 /* The PC relative address is computed relative
5443 to the instruction boundary, so in case immediate
5444 fields follows, we need to adjust the value. */
5445 if (pcrel && i.imm_operands)
5446 {
29b0f896 5447 unsigned int n1;
e205caa7 5448 int sz = 0;
252b5132 5449
29b0f896 5450 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 5451 if (operand_type_check (i.types[n1], imm))
252b5132 5452 {
e205caa7
L		 5453 /* Only one immediate is allowed for PC
5454 relative address. */
5455 assert (sz == 0);
5456 sz = imm_size (n1);
5457 i.op[n].disps->X_add_number -= sz;
252b5132 5458 }
29b0f896 5459 /* We should find the immediate. */
e205caa7 5460 assert (sz != 0);
29b0f896 5461 }
520dc8e8 5462
29b0f896 5463 p = frag_more (size);
2bbd9c25 5464 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 5465 if (GOT_symbol
2bbd9c25 5466 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 5467 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5468 || reloc_type == BFD_RELOC_X86_64_32S
5469 || (reloc_type == BFD_RELOC_64
5470 && object_64bit))
d6ab8113
JB		 5471 && (i.op[n].disps->X_op == O_symbol
5472 || (i.op[n].disps->X_op == O_add
5473 && ((symbol_get_value_expression
5474 (i.op[n].disps->X_op_symbol)->X_op)
5475 == O_subtract))))
5476 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 5477 {
5478 offsetT add;
5479
5480 if (insn_start_frag == frag_now)
5481 add = (p - frag_now->fr_literal) - insn_start_off;
5482 else
5483 {
5484 fragS *fr;
5485
5486 add = insn_start_frag->fr_fix - insn_start_off;
5487 for (fr = insn_start_frag->fr_next;
5488 fr && fr != frag_now; fr = fr->fr_next)
5489 add += fr->fr_fix;
5490 add += p - frag_now->fr_literal;
5491 }
5492
4fa24527 5493 if (!object_64bit)
7b81dfbb
AJ		 5494 {
5495 reloc_type = BFD_RELOC_386_GOTPC;
5496 i.op[n].imms->X_add_number += add;
5497 }
5498 else if (reloc_type == BFD_RELOC_64)
5499 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 5500 else
7b81dfbb
AJ		 5501 /* Don't do the adjustment for x86-64, as there
5502 the pcrel addressing is relative to the _next_
5503 insn, and that is taken care of in other code. */
d6ab8113 5504 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 5505 }
062cd5e7 5506 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 5507 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 5508 }
5509 }
5510 }
5511}
252b5132 5512
29b0f896 5513static void
64e74474 5514output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5515{
5516 char *p;
5517 unsigned int n;
252b5132 5518
29b0f896
AM		 5519 for (n = 0; n < i.operands; n++)
5520 {
40fb9820 5521 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 5522 {
5523 if (i.op[n].imms->X_op == O_constant)
5524 {
e205caa7 5525 int size = imm_size (n);
29b0f896 5526 offsetT val;
b4cac588 5527
29b0f896
AM		 5528 val = offset_in_range (i.op[n].imms->X_add_number,
5529 size);
5530 p = frag_more (size);
5531 md_number_to_chars (p, val, size);
5532 }
5533 else
5534 {
5535 /* Not absolute_section.
5536 Need a 32-bit fixup (don't support 8bit
5537 non-absolute imms). Try to support other
5538 sizes ... */
f86103b7 5539 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 5540 int size = imm_size (n);
5541 int sign;
29b0f896 5542
40fb9820 5543 if (i.types[n].bitfield.imm32s
a7d61044 5544 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 5545 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 5546 sign = 1;
e205caa7
L		 5547 else
5548 sign = 0;
520dc8e8 5549
29b0f896
AM		 5550 p = frag_more (size);
5551 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 5552
2bbd9c25
JJ		 5553 /* This is tough to explain. We end up with this one if we
5554 * have operands that look like
5555 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5556 * obtain the absolute address of the GOT, and it is strongly
5557 * preferable from a performance point of view to avoid using
5558 * a runtime relocation for this. The actual sequence of
5559 * instructions often look something like:
5560 *
5561 * call .L66
5562 * .L66:
5563 * popl %ebx
5564 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5565 *
5566 * The call and pop essentially return the absolute address
5567 * of the label .L66 and store it in %ebx. The linker itself
5568 * will ultimately change the first operand of the addl so
5569 * that %ebx points to the GOT, but to keep things simple, the
5570 * .o file must have this operand set so that it generates not
5571 * the absolute address of .L66, but the absolute address of
5572 * itself. This allows the linker itself simply treat a GOTPC
5573 * relocation as asking for a pcrel offset to the GOT to be
5574 * added in, and the addend of the relocation is stored in the
5575 * operand field for the instruction itself.
5576 *
5577 * Our job here is to fix the operand so that it would add
5578 * the correct offset so that %ebx would point to itself. The
5579 * thing that is tricky is that .-.L66 will point to the
5580 * beginning of the instruction, so we need to further modify
5581 * the operand so that it will point to itself. There are
5582 * other cases where you have something like:
5583 *
5584 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5585 *
5586 * and here no correction would be required. Internally in
5587 * the assembler we treat operands of this form as not being
5588 * pcrel since the '.' is explicitly mentioned, and I wonder
5589 * whether it would simplify matters to do it this way. Who
5590 * knows. In earlier versions of the PIC patches, the
5591 * pcrel_adjust field was used to store the correction, but
5592 * since the expression is not pcrel, I felt it would be
5593 * confusing to do it this way. */
5594
d6ab8113 5595 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5596 || reloc_type == BFD_RELOC_X86_64_32S
5597 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 5598 && GOT_symbol
5599 && GOT_symbol == i.op[n].imms->X_add_symbol
5600 && (i.op[n].imms->X_op == O_symbol
5601 || (i.op[n].imms->X_op == O_add
5602 && ((symbol_get_value_expression
5603 (i.op[n].imms->X_op_symbol)->X_op)
5604 == O_subtract))))
5605 {
2bbd9c25
JJ		 5606 offsetT add;
5607
5608 if (insn_start_frag == frag_now)
5609 add = (p - frag_now->fr_literal) - insn_start_off;
5610 else
5611 {
5612 fragS *fr;
5613
5614 add = insn_start_frag->fr_fix - insn_start_off;
5615 for (fr = insn_start_frag->fr_next;
5616 fr && fr != frag_now; fr = fr->fr_next)
5617 add += fr->fr_fix;
5618 add += p - frag_now->fr_literal;
5619 }
5620
4fa24527 5621 if (!object_64bit)
d6ab8113 5622 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 5623 else if (size == 4)
d6ab8113 5624 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 5625 else if (size == 8)
5626 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 5627 i.op[n].imms->X_add_number += add;
29b0f896 5628 }
29b0f896
AM		 5629 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5630 i.op[n].imms, 0, reloc_type);
5631 }
5632 }
5633 }
252b5132
RH		 5634}
5635\f
d182319b
JB		 5636/* x86_cons_fix_new is called via the expression parsing code when a
5637 reloc is needed. We use this hook to get the correct .got reloc. */
5638static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5639static int cons_sign = -1;
5640
5641void
e3bb37b5 5642x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 5643 expressionS *exp)
d182319b
JB		 5644{
5645 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5646
5647 got_reloc = NO_RELOC;
5648
5649#ifdef TE_PE
5650 if (exp->X_op == O_secrel)
5651 {
5652 exp->X_op = O_symbol;
5653 r = BFD_RELOC_32_SECREL;
5654 }
5655#endif
5656
5657 fix_new_exp (frag, off, len, exp, 0, r);
5658}
5659
718ddfc0
JB		 5660#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5661# define lex_got(reloc, adjust, types) NULL
5662#else
f3c180ae
AM		 5663/* Parse operands of the form
5664 <symbol>@GOTOFF+<nnn>
5665 and similar .plt or .got references.
5666
5667 If we find one, set up the correct relocation in RELOC and copy the
5668 input string, minus the `@GOTOFF' into a malloc'd buffer for
5669 parsing by the calling routine. Return this buffer, and if ADJUST
5670 is non-null set it to the length of the string we removed from the
5671 input line. Otherwise return NULL. */
5672static char *
3956db08 5673lex_got (enum bfd_reloc_code_real *reloc,
64e74474 5674 int *adjust,
40fb9820 5675 i386_operand_type *types)
f3c180ae 5676{
7b81dfbb
AJ		 5677 /* Some of the relocations depend on the size of what field is to
5678 be relocated. But in our callers i386_immediate and i386_displacement
5679 we don't yet know the operand size (this will be set by insn
5680 matching). Hence we record the word32 relocation here,
5681 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 5682 static const struct {
5683 const char *str;
4fa24527 5684 const enum bfd_reloc_code_real rel[2];
40fb9820 5685 const i386_operand_type types64;
f3c180ae 5686 } gotrel[] = {
4eed87de
AM		 5687 { "PLTOFF", { 0,
5688 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 5689 OPERAND_TYPE_IMM64 },
4eed87de
AM		 5690 { "PLT", { BFD_RELOC_386_PLT32,
5691 BFD_RELOC_X86_64_PLT32 },
40fb9820 5692 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5693 { "GOTPLT", { 0,
5694 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 5695 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5696 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5697 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 5698 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5699 { "GOTPCREL", { 0,
5700 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 5701 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5702 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5703 BFD_RELOC_X86_64_TLSGD },
40fb9820 5704 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5705 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5706 0 },
40fb9820 5707 OPERAND_TYPE_NONE },
4eed87de
AM		 5708 { "TLSLD", { 0,
5709 BFD_RELOC_X86_64_TLSLD },
40fb9820 5710 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5711 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5712 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 5713 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5714 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5715 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 5716 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5717 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5718 0 },
40fb9820 5719 OPERAND_TYPE_NONE },
4eed87de
AM		 5720 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5721 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820
L		 5722
5723 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5724 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5725 0 },
40fb9820 5726 OPERAND_TYPE_NONE },
4eed87de
AM		 5727 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5728 0 },
40fb9820 5729 OPERAND_TYPE_NONE },
4eed87de
AM		 5730 { "GOT", { BFD_RELOC_386_GOT32,
5731 BFD_RELOC_X86_64_GOT32 },
40fb9820 5732 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 5733 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5734 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 5735 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5736 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5737 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 5738 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 5739 };
5740 char *cp;
5741 unsigned int j;
5742
718ddfc0
JB		 5743 if (!IS_ELF)
5744 return NULL;
5745
f3c180ae 5746 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 5747 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 5748 return NULL;
5749
47465058 5750 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 5751 {
5752 int len;
5753
5754 len = strlen (gotrel[j].str);
28f81592 5755 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 5756 {
4fa24527 5757 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 5758 {
28f81592
AM		 5759 int first, second;
5760 char *tmpbuf, *past_reloc;
f3c180ae 5761
4fa24527 5762 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 5763 if (adjust)
5764 *adjust = len;
f3c180ae 5765
3956db08
JB		 5766 if (types)
5767 {
5768 if (flag_code != CODE_64BIT)
40fb9820
L		 5769 {
5770 types->bitfield.imm32 = 1;
5771 types->bitfield.disp32 = 1;
5772 }
3956db08
JB		 5773 else
5774 *types = gotrel[j].types64;
5775 }
5776
f3c180ae
AM		 5777 if (GOT_symbol == NULL)
5778 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5779
28f81592 5780 /* The length of the first part of our input line. */
f3c180ae 5781 first = cp - input_line_pointer;
28f81592
AM		 5782
5783 /* The second part goes from after the reloc token until
67c11a9b 5784 (and including) an end_of_line char or comma. */
28f81592 5785 past_reloc = cp + 1 + len;
67c11a9b
AM		 5786 cp = past_reloc;
5787 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5788 ++cp;
5789 second = cp + 1 - past_reloc;
28f81592
AM		 5790
5791 /* Allocate and copy string. The trailing NUL shouldn't
5792 be necessary, but be safe. */
5793 tmpbuf = xmalloc (first + second + 2);
f3c180ae 5794 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 5795 if (second != 0 && *past_reloc != ' ')
5796 /* Replace the relocation token with ' ', so that
5797 errors like foo@GOTOFF1 will be detected. */
5798 tmpbuf[first++] = ' ';
5799 memcpy (tmpbuf + first, past_reloc, second);
5800 tmpbuf[first + second] = '\0';
f3c180ae
AM		 5801 return tmpbuf;
5802 }
5803
4fa24527
JB		 5804 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5805 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 5806 return NULL;
5807 }
5808 }
5809
5810 /* Might be a symbol version string. Don't as_bad here. */
5811 return NULL;
5812}
5813
f3c180ae 5814void
e3bb37b5 5815x86_cons (expressionS *exp, int size)
f3c180ae 5816{
4fa24527 5817 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 5818 {
5819 /* Handle @GOTOFF and the like in an expression. */
5820 char *save;
5821 char *gotfree_input_line;
5822 int adjust;
5823
5824 save = input_line_pointer;
3956db08 5825 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 5826 if (gotfree_input_line)
5827 input_line_pointer = gotfree_input_line;
5828
5829 expression (exp);
5830
5831 if (gotfree_input_line)
5832 {
5833 /* expression () has merrily parsed up to the end of line,
5834 or a comma - in the wrong buffer. Transfer how far
5835 input_line_pointer has moved to the right buffer. */
5836 input_line_pointer = (save
5837 + (input_line_pointer - gotfree_input_line)
5838 + adjust);
5839 free (gotfree_input_line);
3992d3b7
AM		 5840 if (exp->X_op == O_constant
5841 || exp->X_op == O_absent
5842 || exp->X_op == O_illegal
5843 || exp->X_op == O_register
5844 || exp->X_op == O_big)
5845 {
5846 char c = *input_line_pointer;
5847 *input_line_pointer = 0;
5848 as_bad (_("missing or invalid expression `%s'"), save);
5849 *input_line_pointer = c;
5850 }
f3c180ae
AM		 5851 }
5852 }
5853 else
5854 expression (exp);
5855}
5856#endif
5857
d182319b 5858static void signed_cons (int size)
6482c264 5859{
d182319b
JB		 5860 if (flag_code == CODE_64BIT)
5861 cons_sign = 1;
5862 cons (size);
5863 cons_sign = -1;
6482c264
NC		 5864}
5865
d182319b 5866#ifdef TE_PE
6482c264
NC		 5867static void
5868pe_directive_secrel (dummy)
5869 int dummy ATTRIBUTE_UNUSED;
5870{
5871 expressionS exp;
5872
5873 do
5874 {
5875 expression (&exp);
5876 if (exp.X_op == O_symbol)
5877 exp.X_op = O_secrel;
5878
5879 emit_expr (&exp, 4);
5880 }
5881 while (*input_line_pointer++ == ',');
5882
5883 input_line_pointer--;
5884 demand_empty_rest_of_line ();
5885}
6482c264
NC		 5886#endif
5887
252b5132 5888static int
70e41ade 5889i386_immediate (char *imm_start)
252b5132
RH		 5890{
5891 char *save_input_line_pointer;
f3c180ae 5892 char *gotfree_input_line;
252b5132 5893 segT exp_seg = 0;
47926f60 5894 expressionS *exp;
40fb9820
L		 5895 i386_operand_type types;
5896
0dfbf9d7 5897 operand_type_set (&types, ~0);
252b5132
RH		 5898
5899 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5900 {
31b2323c
L		 5901 as_bad (_("at most %d immediate operands are allowed"),
5902 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 5903 return 0;
5904 }
5905
5906 exp = &im_expressions[i.imm_operands++];
520dc8e8 5907 i.op[this_operand].imms = exp;
252b5132
RH		 5908
5909 if (is_space_char (*imm_start))
5910 ++imm_start;
5911
5912 save_input_line_pointer = input_line_pointer;
5913 input_line_pointer = imm_start;
5914
3956db08 5915 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5916 if (gotfree_input_line)
5917 input_line_pointer = gotfree_input_line;
252b5132
RH		 5918
5919 exp_seg = expression (exp);
5920
83183c0c 5921 SKIP_WHITESPACE ();
252b5132 5922 if (*input_line_pointer)
f3c180ae 5923 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 5924
5925 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 5926 if (gotfree_input_line)
5927 free (gotfree_input_line);
252b5132 5928
3992d3b7
AM		 5929 if (exp->X_op == O_absent
5930 || exp->X_op == O_illegal
5931 || exp->X_op == O_big
5932 || (gotfree_input_line
5933 && (exp->X_op == O_constant
5934 || exp->X_op == O_register)))
252b5132 5935 {
3992d3b7 5936 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 5937 imm_start);
3992d3b7 5938 return 0;
252b5132 5939 }
3e73aa7c 5940 else if (exp->X_op == O_constant)
252b5132 5941 {
47926f60 5942 /* Size it properly later. */
40fb9820 5943 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 5944 /* If BFD64, sign extend val. */
4eed87de
AM		 5945 if (!use_rela_relocations
5946 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5947 exp->X_add_number
5948 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 5949 }
4c63da97 5950#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 5951 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 5952 && exp_seg != absolute_section
47926f60 5953 && exp_seg != text_section
24eab124
AM		 5954 && exp_seg != data_section
5955 && exp_seg != bss_section
5956 && exp_seg != undefined_section
f86103b7 5957 && !bfd_is_com_section (exp_seg))
252b5132 5958 {
d0b47220 5959 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 5960 return 0;
5961 }
5962#endif
bb8f5920
L		 5963 else if (!intel_syntax && exp->X_op == O_register)
5964 {
5965 as_bad (_("illegal immediate register operand %s"), imm_start);
5966 return 0;
5967 }
252b5132
RH		 5968 else
5969 {
5970 /* This is an address. The size of the address will be
24eab124 5971 determined later, depending on destination register,
3e73aa7c 5972 suffix, or the default for the section. */
40fb9820
L		 5973 i.types[this_operand].bitfield.imm8 = 1;
5974 i.types[this_operand].bitfield.imm16 = 1;
5975 i.types[this_operand].bitfield.imm32 = 1;
5976 i.types[this_operand].bitfield.imm32s = 1;
5977 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 5978 i.types[this_operand] = operand_type_and (i.types[this_operand],
5979 types);
252b5132
RH		 5980 }
5981
5982 return 1;
5983}
5984
551c1ca1 5985static char *
e3bb37b5 5986i386_scale (char *scale)
252b5132 5987{
551c1ca1
AM		 5988 offsetT val;
5989 char *save = input_line_pointer;
252b5132 5990
551c1ca1
AM		 5991 input_line_pointer = scale;
5992 val = get_absolute_expression ();
5993
5994 switch (val)
252b5132 5995 {
551c1ca1 5996 case 1:
252b5132
RH		 5997 i.log2_scale_factor = 0;
5998 break;
551c1ca1 5999 case 2:
252b5132
RH		 6000 i.log2_scale_factor = 1;
6001 break;
551c1ca1 6002 case 4:
252b5132
RH		 6003 i.log2_scale_factor = 2;
6004 break;
551c1ca1 6005 case 8:
252b5132
RH		 6006 i.log2_scale_factor = 3;
6007 break;
6008 default:
a724f0f4
JB		 6009 {
6010 char sep = *input_line_pointer;
6011
6012 *input_line_pointer = '\0';
6013 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6014 scale);
6015 *input_line_pointer = sep;
6016 input_line_pointer = save;
6017 return NULL;
6018 }
252b5132 6019 }
29b0f896 6020 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6021 {
6022 as_warn (_("scale factor of %d without an index register"),
24eab124 6023 1 << i.log2_scale_factor);
252b5132 6024 i.log2_scale_factor = 0;
252b5132 6025 }
551c1ca1
AM		 6026 scale = input_line_pointer;
6027 input_line_pointer = save;
6028 return scale;
252b5132
RH		 6029}
6030
252b5132 6031static int
e3bb37b5 6032i386_displacement (char *disp_start, char *disp_end)
252b5132 6033{
29b0f896 6034 expressionS *exp;
252b5132
RH		 6035 segT exp_seg = 0;
6036 char *save_input_line_pointer;
f3c180ae 6037 char *gotfree_input_line;
40fb9820
L		 6038 int override;
6039 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6040 int ret;
252b5132 6041
31b2323c
L		 6042 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6043 {
6044 as_bad (_("at most %d displacement operands are allowed"),
6045 MAX_MEMORY_OPERANDS);
6046 return 0;
6047 }
6048
0dfbf9d7 6049 operand_type_set (&bigdisp, 0);
40fb9820
L		 6050 if ((i.types[this_operand].bitfield.jumpabsolute)
6051 || (!current_templates->start->opcode_modifier.jump
6052 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6053 {
40fb9820 6054 bigdisp.bitfield.disp32 = 1;
e05278af 6055 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6056 if (flag_code == CODE_64BIT)
6057 {
6058 if (!override)
6059 {
6060 bigdisp.bitfield.disp32s = 1;
6061 bigdisp.bitfield.disp64 = 1;
6062 }
6063 }
6064 else if ((flag_code == CODE_16BIT) ^ override)
6065 {
6066 bigdisp.bitfield.disp32 = 0;
6067 bigdisp.bitfield.disp16 = 1;
6068 }
e05278af
JB		 6069 }
6070 else
6071 {
6072 /* For PC-relative branches, the width of the displacement
6073 is dependent upon data size, not address size. */
e05278af 6074 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6075 if (flag_code == CODE_64BIT)
6076 {
6077 if (override || i.suffix == WORD_MNEM_SUFFIX)
6078 bigdisp.bitfield.disp16 = 1;
6079 else
6080 {
6081 bigdisp.bitfield.disp32 = 1;
6082 bigdisp.bitfield.disp32s = 1;
6083 }
6084 }
6085 else
e05278af
JB		 6086 {
6087 if (!override)
6088 override = (i.suffix == (flag_code != CODE_16BIT
6089 ? WORD_MNEM_SUFFIX
6090 : LONG_MNEM_SUFFIX));
40fb9820
L		 6091 bigdisp.bitfield.disp32 = 1;
6092 if ((flag_code == CODE_16BIT) ^ override)
6093 {
6094 bigdisp.bitfield.disp32 = 0;
6095 bigdisp.bitfield.disp16 = 1;
6096 }
e05278af 6097 }
e05278af 6098 }
c6fb90c8
L		 6099 i.types[this_operand] = operand_type_or (i.types[this_operand],
6100 bigdisp);
252b5132
RH		 6101
6102 exp = &disp_expressions[i.disp_operands];
520dc8e8 6103 i.op[this_operand].disps = exp;
252b5132
RH		 6104 i.disp_operands++;
6105 save_input_line_pointer = input_line_pointer;
6106 input_line_pointer = disp_start;
6107 END_STRING_AND_SAVE (disp_end);
6108
6109#ifndef GCC_ASM_O_HACK
6110#define GCC_ASM_O_HACK 0
6111#endif
6112#if GCC_ASM_O_HACK
6113 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6114 if (i.types[this_operand].bitfield.baseIndex
24eab124 6115 && displacement_string_end[-1] == '+')
252b5132
RH		 6116 {
6117 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6118 constraint within gcc asm statements.
6119 For instance:
6120
6121 #define _set_tssldt_desc(n,addr,limit,type) \
6122 __asm__ __volatile__ ( \
6123 "movw %w2,%0\n\t" \
6124 "movw %w1,2+%0\n\t" \
6125 "rorl $16,%1\n\t" \
6126 "movb %b1,4+%0\n\t" \
6127 "movb %4,5+%0\n\t" \
6128 "movb $0,6+%0\n\t" \
6129 "movb %h1,7+%0\n\t" \
6130 "rorl $16,%1" \
6131 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6132
6133 This works great except that the output assembler ends
6134 up looking a bit weird if it turns out that there is
6135 no offset. You end up producing code that looks like:
6136
6137 #APP
6138 movw $235,(%eax)
6139 movw %dx,2+(%eax)
6140 rorl $16,%edx
6141 movb %dl,4+(%eax)
6142 movb $137,5+(%eax)
6143 movb $0,6+(%eax)
6144 movb %dh,7+(%eax)
6145 rorl $16,%edx
6146 #NO_APP
6147
47926f60 6148 So here we provide the missing zero. */
24eab124
AM		 6149
6150 *displacement_string_end = '0';
252b5132
RH		 6151 }
6152#endif
3956db08 6153 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6154 if (gotfree_input_line)
6155 input_line_pointer = gotfree_input_line;
252b5132 6156
24eab124 6157 exp_seg = expression (exp);
252b5132 6158
636c26b0
AM		 6159 SKIP_WHITESPACE ();
6160 if (*input_line_pointer)
6161 as_bad (_("junk `%s' after expression"), input_line_pointer);
6162#if GCC_ASM_O_HACK
6163 RESTORE_END_STRING (disp_end + 1);
6164#endif
636c26b0 6165 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 6166 if (gotfree_input_line)
6167 free (gotfree_input_line);
3992d3b7 6168 ret = 1;
636c26b0 6169
24eab124
AM		 6170 /* We do this to make sure that the section symbol is in
6171 the symbol table. We will ultimately change the relocation
47926f60 6172 to be relative to the beginning of the section. */
1ae12ab7 6173 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6174 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6175 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6176 {
636c26b0 6177 if (exp->X_op != O_symbol)
3992d3b7 6178 goto inv_disp;
636c26b0 6179
e5cb08ac 6180 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 6181 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6182 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6183 exp->X_op = O_subtract;
6184 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6185 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6186 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6187 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6188 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6189 else
29b0f896 6190 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6191 }
252b5132 6192
3992d3b7
AM		 6193 else if (exp->X_op == O_absent
6194 || exp->X_op == O_illegal
6195 || exp->X_op == O_big
6196 || (gotfree_input_line
6197 && (exp->X_op == O_constant
6198 || exp->X_op == O_register)))
2daf4fd8 6199 {
3992d3b7
AM		 6200 inv_disp:
6201 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6202 disp_start);
3992d3b7 6203 ret = 0;
2daf4fd8
AM		 6204 }
6205
4c63da97 6206#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6207 else if (exp->X_op != O_constant
6208 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6209 && exp_seg != absolute_section
6210 && exp_seg != text_section
6211 && exp_seg != data_section
6212 && exp_seg != bss_section
6213 && exp_seg != undefined_section
6214 && !bfd_is_com_section (exp_seg))
24eab124 6215 {
d0b47220 6216 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6217 ret = 0;
24eab124 6218 }
252b5132 6219#endif
3956db08 6220
3992d3b7
AM		 6221 RESTORE_END_STRING (disp_end);
6222
40fb9820
L		 6223 /* Check if this is a displacement only operand. */
6224 bigdisp = i.types[this_operand];
6225 bigdisp.bitfield.disp8 = 0;
6226 bigdisp.bitfield.disp16 = 0;
6227 bigdisp.bitfield.disp32 = 0;
6228 bigdisp.bitfield.disp32s = 0;
6229 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6230 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6231 i.types[this_operand] = operand_type_and (i.types[this_operand],
6232 types);
3956db08 6233
3992d3b7 6234 return ret;
252b5132
RH		 6235}
6236
eecb386c 6237/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6238 Return 1 on success, 0 on a failure. */
6239
252b5132 6240static int
e3bb37b5 6241i386_index_check (const char *operand_string)
252b5132 6242{
3e73aa7c 6243 int ok;
24eab124 6244#if INFER_ADDR_PREFIX
eecb386c
AM		 6245 int fudged = 0;
6246
24eab124
AM		 6247 tryprefix:
6248#endif
3e73aa7c 6249 ok = 1;
75178d9d 6250 if (flag_code == CODE_64BIT)
64e74474 6251 {
64e74474 6252 if ((i.base_reg
40fb9820
L		 6253 && ((i.prefix[ADDR_PREFIX] == 0
6254 && !i.base_reg->reg_type.bitfield.reg64)
6255 || (i.prefix[ADDR_PREFIX]
6256 && !i.base_reg->reg_type.bitfield.reg32))
6257 && (i.index_reg
9a04903e
JB		 6258 || i.base_reg->reg_num !=
6259 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6260 || (i.index_reg
40fb9820
L		 6261 && (!i.index_reg->reg_type.bitfield.baseindex
6262 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 6263 && i.index_reg->reg_num != RegRiz
6264 && !i.index_reg->reg_type.bitfield.reg64
6265 )
40fb9820 6266 || (i.prefix[ADDR_PREFIX]
db51cc60 6267 && i.index_reg->reg_num != RegEiz
40fb9820 6268 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 6269 ok = 0;
3e73aa7c
JH		 6270 }
6271 else
6272 {
6273 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6274 {
6275 /* 16bit checks. */
6276 if ((i.base_reg
40fb9820
L		 6277 && (!i.base_reg->reg_type.bitfield.reg16
6278 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6279 || (i.index_reg
40fb9820
L		 6280 && (!i.index_reg->reg_type.bitfield.reg16
6281 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6282 || !(i.base_reg
6283 && i.base_reg->reg_num < 6
6284 && i.index_reg->reg_num >= 6
6285 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6286 ok = 0;
6287 }
6288 else
e5cb08ac 6289 {
3e73aa7c
JH		 6290 /* 32bit checks. */
6291 if ((i.base_reg
40fb9820 6292 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6293 || (i.index_reg
db51cc60
L		 6294 && ((!i.index_reg->reg_type.bitfield.reg32
6295 && i.index_reg->reg_num != RegEiz)
40fb9820 6296 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6297 ok = 0;
3e73aa7c
JH		 6298 }
6299 }
6300 if (!ok)
24eab124
AM		 6301 {
6302#if INFER_ADDR_PREFIX
20f0a1fc 6303 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 6304 {
6305 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6306 i.prefixes += 1;
b23bac36
AM		 6307 /* Change the size of any displacement too. At most one of
6308 Disp16 or Disp32 is set.
6309 FIXME. There doesn't seem to be any real need for separate
6310 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6311 Removing them would probably clean up the code quite a lot. */
4eed87de 6312 if (flag_code != CODE_64BIT
40fb9820
L		 6313 && (i.types[this_operand].bitfield.disp16
6314 || i.types[this_operand].bitfield.disp32))
6315 i.types[this_operand]
c6fb90c8 6316 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6317 fudged = 1;
24eab124
AM		 6318 goto tryprefix;
6319 }
eecb386c
AM		 6320 if (fudged)
6321 as_bad (_("`%s' is not a valid base/index expression"),
6322 operand_string);
6323 else
c388dee8 6324#endif
eecb386c
AM		 6325 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6326 operand_string,
3e73aa7c 6327 flag_code_names[flag_code]);
24eab124 6328 }
20f0a1fc 6329 return ok;
24eab124 6330}
252b5132 6331
252b5132 6332/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 6333 on error. */
252b5132 6334
252b5132 6335static int
a7619375 6336i386_att_operand (char *operand_string)
252b5132 6337{
af6bdddf
AM		 6338 const reg_entry *r;
6339 char *end_op;
24eab124 6340 char *op_string = operand_string;
252b5132 6341
24eab124 6342 if (is_space_char (*op_string))
252b5132
RH		 6343 ++op_string;
6344
24eab124 6345 /* We check for an absolute prefix (differentiating,
47926f60 6346 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 6347 if (*op_string == ABSOLUTE_PREFIX)
6348 {
6349 ++op_string;
6350 if (is_space_char (*op_string))
6351 ++op_string;
40fb9820 6352 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 6353 }
252b5132 6354
47926f60 6355 /* Check if operand is a register. */
4d1bb795 6356 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 6357 {
40fb9820
L		 6358 i386_operand_type temp;
6359
24eab124
AM		 6360 /* Check for a segment override by searching for ':' after a
6361 segment register. */
6362 op_string = end_op;
6363 if (is_space_char (*op_string))
6364 ++op_string;
40fb9820
L		 6365 if (*op_string == ':'
6366 && (r->reg_type.bitfield.sreg2
6367 || r->reg_type.bitfield.sreg3))
24eab124
AM		 6368 {
6369 switch (r->reg_num)
6370 {
6371 case 0:
6372 i.seg[i.mem_operands] = &es;
6373 break;
6374 case 1:
6375 i.seg[i.mem_operands] = &cs;
6376 break;
6377 case 2:
6378 i.seg[i.mem_operands] = &ss;
6379 break;
6380 case 3:
6381 i.seg[i.mem_operands] = &ds;
6382 break;
6383 case 4:
6384 i.seg[i.mem_operands] = &fs;
6385 break;
6386 case 5:
6387 i.seg[i.mem_operands] = &gs;
6388 break;
6389 }
252b5132 6390
24eab124 6391 /* Skip the ':' and whitespace. */
252b5132
RH		 6392 ++op_string;
6393 if (is_space_char (*op_string))
24eab124 6394 ++op_string;
252b5132 6395
24eab124
AM		 6396 if (!is_digit_char (*op_string)
6397 && !is_identifier_char (*op_string)
6398 && *op_string != '('
6399 && *op_string != ABSOLUTE_PREFIX)
6400 {
6401 as_bad (_("bad memory operand `%s'"), op_string);
6402 return 0;
6403 }
47926f60 6404 /* Handle case of %es:*foo. */
24eab124
AM		 6405 if (*op_string == ABSOLUTE_PREFIX)
6406 {
6407 ++op_string;
6408 if (is_space_char (*op_string))
6409 ++op_string;
40fb9820 6410 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 6411 }
6412 goto do_memory_reference;
6413 }
6414 if (*op_string)
6415 {
d0b47220 6416 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 6417 return 0;
6418 }
40fb9820
L		 6419 temp = r->reg_type;
6420 temp.bitfield.baseindex = 0;
c6fb90c8
L		 6421 i.types[this_operand] = operand_type_or (i.types[this_operand],
6422 temp);
7d5e4556 6423 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 6424 i.op[this_operand].regs = r;
24eab124
AM		 6425 i.reg_operands++;
6426 }
af6bdddf
AM		 6427 else if (*op_string == REGISTER_PREFIX)
6428 {
6429 as_bad (_("bad register name `%s'"), op_string);
6430 return 0;
6431 }
24eab124 6432 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 6433 {
24eab124 6434 ++op_string;
40fb9820 6435 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 6436 {
d0b47220 6437 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 6438 return 0;
6439 }
6440 if (!i386_immediate (op_string))
6441 return 0;
6442 }
6443 else if (is_digit_char (*op_string)
6444 || is_identifier_char (*op_string)
e5cb08ac 6445 || *op_string == '(')
24eab124 6446 {
47926f60 6447 /* This is a memory reference of some sort. */
af6bdddf 6448 char *base_string;
252b5132 6449
47926f60 6450 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 6451 char *displacement_string_start;
6452 char *displacement_string_end;
252b5132 6453
24eab124 6454 do_memory_reference:
24eab124 6455 if ((i.mem_operands == 1
40fb9820 6456 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 6457 || i.mem_operands == 2)
6458 {
6459 as_bad (_("too many memory references for `%s'"),
6460 current_templates->start->name);
6461 return 0;
6462 }
252b5132 6463
24eab124
AM		 6464 /* Check for base index form. We detect the base index form by
6465 looking for an ')' at the end of the operand, searching
6466 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6467 after the '('. */
af6bdddf 6468 base_string = op_string + strlen (op_string);
c3332e24 6469
af6bdddf
AM		 6470 --base_string;
6471 if (is_space_char (*base_string))
6472 --base_string;
252b5132 6473
47926f60 6474 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 6475 displacement_string_start = op_string;
6476 displacement_string_end = base_string + 1;
252b5132 6477
24eab124
AM		 6478 if (*base_string == ')')
6479 {
af6bdddf 6480 char *temp_string;
24eab124
AM		 6481 unsigned int parens_balanced = 1;
6482 /* We've already checked that the number of left & right ()'s are
47926f60 6483 equal, so this loop will not be infinite. */
24eab124
AM		 6484 do
6485 {
6486 base_string--;
6487 if (*base_string == ')')
6488 parens_balanced++;
6489 if (*base_string == '(')
6490 parens_balanced--;
6491 }
6492 while (parens_balanced);
c3332e24 6493
af6bdddf 6494 temp_string = base_string;
c3332e24 6495
24eab124 6496 /* Skip past '(' and whitespace. */
252b5132
RH		 6497 ++base_string;
6498 if (is_space_char (*base_string))
24eab124 6499 ++base_string;
252b5132 6500
af6bdddf 6501 if (*base_string == ','
4eed87de
AM		 6502 || ((i.base_reg = parse_register (base_string, &end_op))
6503 != NULL))
252b5132 6504 {
af6bdddf 6505 displacement_string_end = temp_string;
252b5132 6506
40fb9820 6507 i.types[this_operand].bitfield.baseindex = 1;
252b5132 6508
af6bdddf 6509 if (i.base_reg)
24eab124 6510 {
24eab124
AM		 6511 base_string = end_op;
6512 if (is_space_char (*base_string))
6513 ++base_string;
af6bdddf
AM		 6514 }
6515
6516 /* There may be an index reg or scale factor here. */
6517 if (*base_string == ',')
6518 {
6519 ++base_string;
6520 if (is_space_char (*base_string))
6521 ++base_string;
6522
4eed87de
AM		 6523 if ((i.index_reg = parse_register (base_string, &end_op))
6524 != NULL)
24eab124 6525 {
af6bdddf 6526 base_string = end_op;
24eab124
AM		 6527 if (is_space_char (*base_string))
6528 ++base_string;
af6bdddf
AM		 6529 if (*base_string == ',')
6530 {
6531 ++base_string;
6532 if (is_space_char (*base_string))
6533 ++base_string;
6534 }
e5cb08ac 6535 else if (*base_string != ')')
af6bdddf 6536 {
4eed87de
AM		 6537 as_bad (_("expecting `,' or `)' "
6538 "after index register in `%s'"),
af6bdddf
AM		 6539 operand_string);
6540 return 0;
6541 }
24eab124 6542 }
af6bdddf 6543 else if (*base_string == REGISTER_PREFIX)
24eab124 6544 {
af6bdddf 6545 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 6546 return 0;
6547 }
252b5132 6548
47926f60 6549 /* Check for scale factor. */
551c1ca1 6550 if (*base_string != ')')
af6bdddf 6551 {
551c1ca1
AM		 6552 char *end_scale = i386_scale (base_string);
6553
6554 if (!end_scale)
af6bdddf 6555 return 0;
24eab124 6556
551c1ca1 6557 base_string = end_scale;
af6bdddf
AM		 6558 if (is_space_char (*base_string))
6559 ++base_string;
6560 if (*base_string != ')')
6561 {
4eed87de
AM		 6562 as_bad (_("expecting `)' "
6563 "after scale factor in `%s'"),
af6bdddf
AM		 6564 operand_string);
6565 return 0;
6566 }
6567 }
6568 else if (!i.index_reg)
24eab124 6569 {
4eed87de
AM		 6570 as_bad (_("expecting index register or scale factor "
6571 "after `,'; got '%c'"),
af6bdddf 6572 *base_string);
24eab124
AM		 6573 return 0;
6574 }
6575 }
af6bdddf 6576 else if (*base_string != ')')
24eab124 6577 {
4eed87de
AM		 6578 as_bad (_("expecting `,' or `)' "
6579 "after base register in `%s'"),
af6bdddf 6580 operand_string);
24eab124
AM		 6581 return 0;
6582 }
c3332e24 6583 }
af6bdddf 6584 else if (*base_string == REGISTER_PREFIX)
c3332e24 6585 {
af6bdddf 6586 as_bad (_("bad register name `%s'"), base_string);
24eab124 6587 return 0;
c3332e24 6588 }
24eab124
AM		 6589 }
6590
6591 /* If there's an expression beginning the operand, parse it,
6592 assuming displacement_string_start and
6593 displacement_string_end are meaningful. */
6594 if (displacement_string_start != displacement_string_end)
6595 {
6596 if (!i386_displacement (displacement_string_start,
6597 displacement_string_end))
6598 return 0;
6599 }
6600
6601 /* Special case for (%dx) while doing input/output op. */
6602 if (i.base_reg
0dfbf9d7
L		 6603 && operand_type_equal (&i.base_reg->reg_type,
6604 &reg16_inoutportreg)
24eab124
AM		 6605 && i.index_reg == 0
6606 && i.log2_scale_factor == 0
6607 && i.seg[i.mem_operands] == 0
40fb9820 6608 && !operand_type_check (i.types[this_operand], disp))
24eab124 6609 {
65da13b5 6610 i.types[this_operand] = inoutportreg;
24eab124
AM		 6611 return 1;
6612 }
6613
eecb386c
AM		 6614 if (i386_index_check (operand_string) == 0)
6615 return 0;
5c07affc 6616 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 6617 i.mem_operands++;
6618 }
6619 else
ce8a8b2f
AM		 6620 {
6621 /* It's not a memory operand; argh! */
24eab124
AM		 6622 as_bad (_("invalid char %s beginning operand %d `%s'"),
6623 output_invalid (*op_string),
6624 this_operand + 1,
6625 op_string);
6626 return 0;
6627 }
47926f60 6628 return 1; /* Normal return. */
252b5132
RH		 6629}
6630\f
ee7fcc42
AM		 6631/* md_estimate_size_before_relax()
6632
6633 Called just before relax() for rs_machine_dependent frags. The x86
6634 assembler uses these frags to handle variable size jump
6635 instructions.
6636
6637 Any symbol that is now undefined will not become defined.
6638 Return the correct fr_subtype in the frag.
6639 Return the initial "guess for variable size of frag" to caller.
6640 The guess is actually the growth beyond the fixed part. Whatever
6641 we do to grow the fixed or variable part contributes to our
6642 returned value. */
6643
252b5132
RH		 6644int
6645md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 6646 fragS *fragP;
6647 segT segment;
252b5132 6648{
252b5132 6649 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 6650 check for un-relaxable symbols. On an ELF system, we can't relax
6651 an externally visible symbol, because it may be overridden by a
6652 shared library. */
6653 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 6654#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6655 || (IS_ELF
31312f95
AM		 6656 && (S_IS_EXTERNAL (fragP->fr_symbol)
6657 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 6658#endif
6659 )
252b5132 6660 {
b98ef147
AM		 6661 /* Symbol is undefined in this segment, or we need to keep a
6662 reloc so that weak symbols can be overridden. */
6663 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 6664 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 6665 unsigned char *opcode;
6666 int old_fr_fix;
f6af82bd 6667
ee7fcc42
AM		 6668 if (fragP->fr_var != NO_RELOC)
6669 reloc_type = fragP->fr_var;
b98ef147 6670 else if (size == 2)
f6af82bd
AM		 6671 reloc_type = BFD_RELOC_16_PCREL;
6672 else
6673 reloc_type = BFD_RELOC_32_PCREL;
252b5132 6674
ee7fcc42
AM		 6675 old_fr_fix = fragP->fr_fix;
6676 opcode = (unsigned char *) fragP->fr_opcode;
6677
fddf5b5b 6678 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 6679 {
fddf5b5b
AM		 6680 case UNCOND_JUMP:
6681 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 6682 opcode[0] = 0xe9;
252b5132 6683 fragP->fr_fix += size;
062cd5e7
AS		 6684 fix_new (fragP, old_fr_fix, size,
6685 fragP->fr_symbol,
6686 fragP->fr_offset, 1,
6687 reloc_type);
252b5132
RH		 6688 break;
6689
fddf5b5b 6690 case COND_JUMP86:
412167cb
AM		 6691 if (size == 2
6692 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 6693 {
6694 /* Negate the condition, and branch past an
6695 unconditional jump. */
6696 opcode[0] ^= 1;
6697 opcode[1] = 3;
6698 /* Insert an unconditional jump. */
6699 opcode[2] = 0xe9;
6700 /* We added two extra opcode bytes, and have a two byte
6701 offset. */
6702 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 6703 fix_new (fragP, old_fr_fix + 2, 2,
6704 fragP->fr_symbol,
6705 fragP->fr_offset, 1,
6706 reloc_type);
fddf5b5b
AM		 6707 break;
6708 }
6709 /* Fall through. */
6710
6711 case COND_JUMP:
412167cb
AM		 6712 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
6713 {
3e02c1cc
AM		 6714 fixS *fixP;
6715
412167cb 6716 fragP->fr_fix += 1;
3e02c1cc
AM		 6717 fixP = fix_new (fragP, old_fr_fix, 1,
6718 fragP->fr_symbol,
6719 fragP->fr_offset, 1,
6720 BFD_RELOC_8_PCREL);
6721 fixP->fx_signed = 1;
412167cb
AM		 6722 break;
6723 }
93c2a809 6724
24eab124 6725 /* This changes the byte-displacement jump 0x7N
fddf5b5b 6726 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 6727 opcode[1] = opcode[0] + 0x10;
f6af82bd 6728 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 6729 /* We've added an opcode byte. */
6730 fragP->fr_fix += 1 + size;
062cd5e7
AS		 6731 fix_new (fragP, old_fr_fix + 1, size,
6732 fragP->fr_symbol,
6733 fragP->fr_offset, 1,
6734 reloc_type);
252b5132 6735 break;
fddf5b5b
AM		 6736
6737 default:
6738 BAD_CASE (fragP->fr_subtype);
6739 break;
252b5132
RH		 6740 }
6741 frag_wane (fragP);
ee7fcc42 6742 return fragP->fr_fix - old_fr_fix;
252b5132 6743 }
93c2a809 6744
93c2a809
AM		 6745 /* Guess size depending on current relax state. Initially the relax
6746 state will correspond to a short jump and we return 1, because
6747 the variable part of the frag (the branch offset) is one byte
6748 long. However, we can relax a section more than once and in that
6749 case we must either set fr_subtype back to the unrelaxed state,
6750 or return the value for the appropriate branch. */
6751 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 6752}
6753
47926f60
KH		 6754/* Called after relax() is finished.
6755
6756 In: Address of frag.
6757 fr_type == rs_machine_dependent.
6758 fr_subtype is what the address relaxed to.
6759
6760 Out: Any fixSs and constants are set up.
6761 Caller will turn frag into a ".space 0". */
6762
252b5132
RH		 6763void
6764md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 6765 bfd *abfd ATTRIBUTE_UNUSED;
6766 segT sec ATTRIBUTE_UNUSED;
29b0f896 6767 fragS *fragP;
252b5132 6768{
29b0f896 6769 unsigned char *opcode;
252b5132 6770 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 6771 offsetT target_address;
6772 offsetT opcode_address;
252b5132 6773 unsigned int extension = 0;
847f7ad4 6774 offsetT displacement_from_opcode_start;
252b5132
RH		 6775
6776 opcode = (unsigned char *) fragP->fr_opcode;
6777
47926f60 6778 /* Address we want to reach in file space. */
252b5132 6779 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 6780
47926f60 6781 /* Address opcode resides at in file space. */
252b5132
RH		 6782 opcode_address = fragP->fr_address + fragP->fr_fix;
6783
47926f60 6784 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 6785 displacement_from_opcode_start = target_address - opcode_address;
6786
fddf5b5b 6787 if ((fragP->fr_subtype & BIG) == 0)
252b5132 6788 {
47926f60
KH		 6789 /* Don't have to change opcode. */
6790 extension = 1; /* 1 opcode + 1 displacement */
252b5132 6791 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 6792 }
6793 else
6794 {
6795 if (no_cond_jump_promotion
6796 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 6797 as_warn_where (fragP->fr_file, fragP->fr_line,
6798 _("long jump required"));
252b5132 6799
fddf5b5b
AM		 6800 switch (fragP->fr_subtype)
6801 {
6802 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6803 extension = 4; /* 1 opcode + 4 displacement */
6804 opcode[0] = 0xe9;
6805 where_to_put_displacement = &opcode[1];
6806 break;
252b5132 6807
fddf5b5b
AM		 6808 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6809 extension = 2; /* 1 opcode + 2 displacement */
6810 opcode[0] = 0xe9;
6811 where_to_put_displacement = &opcode[1];
6812 break;
252b5132 6813
fddf5b5b
AM		 6814 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6815 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6816 extension = 5; /* 2 opcode + 4 displacement */
6817 opcode[1] = opcode[0] + 0x10;
6818 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6819 where_to_put_displacement = &opcode[2];
6820 break;
252b5132 6821
fddf5b5b
AM		 6822 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6823 extension = 3; /* 2 opcode + 2 displacement */
6824 opcode[1] = opcode[0] + 0x10;
6825 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6826 where_to_put_displacement = &opcode[2];
6827 break;
252b5132 6828
fddf5b5b
AM		 6829 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6830 extension = 4;
6831 opcode[0] ^= 1;
6832 opcode[1] = 3;
6833 opcode[2] = 0xe9;
6834 where_to_put_displacement = &opcode[3];
6835 break;
6836
6837 default:
6838 BAD_CASE (fragP->fr_subtype);
6839 break;
6840 }
252b5132 6841 }
fddf5b5b 6842
7b81dfbb
AJ		 6843 /* If size if less then four we are sure that the operand fits,
6844 but if it's 4, then it could be that the displacement is larger
6845 then -/+ 2GB. */
6846 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6847 && object_64bit
6848 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 6849 + ((addressT) 1 << 31))
6850 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 6851 {
6852 as_bad_where (fragP->fr_file, fragP->fr_line,
6853 _("jump target out of range"));
6854 /* Make us emit 0. */
6855 displacement_from_opcode_start = extension;
6856 }
47926f60 6857 /* Now put displacement after opcode. */
252b5132
RH		 6858 md_number_to_chars ((char *) where_to_put_displacement,
6859 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 6860 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 6861 fragP->fr_fix += extension;
6862}
6863\f
252b5132
RH		 6864/* Apply a fixup (fixS) to segment data, once it has been determined
6865 by our caller that we have all the info we need to fix it up.
6866
6867 On the 386, immediates, displacements, and data pointers are all in
6868 the same (little-endian) format, so we don't need to care about which
6869 we are handling. */
6870
94f592af 6871void
55cf6793 6872md_apply_fix (fixP, valP, seg)
47926f60
KH		 6873 /* The fix we're to put in. */
6874 fixS *fixP;
47926f60 6875 /* Pointer to the value of the bits. */
c6682705 6876 valueT *valP;
47926f60
KH		 6877 /* Segment fix is from. */
6878 segT seg ATTRIBUTE_UNUSED;
252b5132 6879{
94f592af 6880 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 6881 valueT value = *valP;
252b5132 6882
f86103b7 6883#if !defined (TE_Mach)
93382f6d
AM		 6884 if (fixP->fx_pcrel)
6885 {
6886 switch (fixP->fx_r_type)
6887 {
5865bb77
ILT		 6888 default:
6889 break;
6890
d6ab8113
JB		 6891 case BFD_RELOC_64:
6892 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6893 break;
93382f6d 6894 case BFD_RELOC_32:
ae8887b5 6895 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 6896 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6897 break;
6898 case BFD_RELOC_16:
6899 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6900 break;
6901 case BFD_RELOC_8:
6902 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6903 break;
6904 }
6905 }
252b5132 6906
a161fe53 6907 if (fixP->fx_addsy != NULL
31312f95 6908 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 6909 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 6910 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6911 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6912 && !use_rela_relocations)
252b5132 6913 {
31312f95
AM		 6914 /* This is a hack. There should be a better way to handle this.
6915 This covers for the fact that bfd_install_relocation will
6916 subtract the current location (for partial_inplace, PC relative
6917 relocations); see more below. */
252b5132 6918#ifndef OBJ_AOUT
718ddfc0 6919 if (IS_ELF
252b5132
RH		 6920#ifdef TE_PE
6921 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6922#endif
6923 )
6924 value += fixP->fx_where + fixP->fx_frag->fr_address;
6925#endif
6926#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6927 if (IS_ELF)
252b5132 6928 {
6539b54b 6929 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 6930
6539b54b 6931 if ((sym_seg == seg
2f66722d 6932 || (symbol_section_p (fixP->fx_addsy)
6539b54b 6933 && sym_seg != absolute_section))
ae6063d4 6934 && !generic_force_reloc (fixP))
2f66722d
AM		 6935 {
6936 /* Yes, we add the values in twice. This is because
6539b54b
AM		 6937 bfd_install_relocation subtracts them out again. I think
6938 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 6939 it. FIXME. */
6940 value += fixP->fx_where + fixP->fx_frag->fr_address;
6941 }
252b5132
RH		 6942 }
6943#endif
6944#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 6945 /* For some reason, the PE format does not store a
6946 section address offset for a PC relative symbol. */
6947 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 6948 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 6949 value += md_pcrel_from (fixP);
6950#endif
6951 }
6952
6953 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 6954 and we must not disappoint it. */
252b5132 6955#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6956 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 6957 switch (fixP->fx_r_type)
6958 {
6959 case BFD_RELOC_386_PLT32:
3e73aa7c 6960 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 6961 /* Make the jump instruction point to the address of the operand. At
6962 runtime we merely add the offset to the actual PLT entry. */
6963 value = -4;
6964 break;
31312f95 6965
13ae64f3
JJ		 6966 case BFD_RELOC_386_TLS_GD:
6967 case BFD_RELOC_386_TLS_LDM:
13ae64f3 6968 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6969 case BFD_RELOC_386_TLS_IE:
6970 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 6971 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 6972 case BFD_RELOC_X86_64_TLSGD:
6973 case BFD_RELOC_X86_64_TLSLD:
6974 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 6975 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 6976 value = 0; /* Fully resolved at runtime. No addend. */
6977 /* Fallthrough */
6978 case BFD_RELOC_386_TLS_LE:
6979 case BFD_RELOC_386_TLS_LDO_32:
6980 case BFD_RELOC_386_TLS_LE_32:
6981 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6982 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 6983 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 6984 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 6985 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6986 break;
6987
67a4f2b7
AO		 6988 case BFD_RELOC_386_TLS_DESC_CALL:
6989 case BFD_RELOC_X86_64_TLSDESC_CALL:
6990 value = 0; /* Fully resolved at runtime. No addend. */
6991 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6992 fixP->fx_done = 0;
6993 return;
6994
00f7efb6
JJ		 6995 case BFD_RELOC_386_GOT32:
6996 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 6997 value = 0; /* Fully resolved at runtime. No addend. */
6998 break;
47926f60
KH		 6999
7000 case BFD_RELOC_VTABLE_INHERIT:
7001 case BFD_RELOC_VTABLE_ENTRY:
7002 fixP->fx_done = 0;
94f592af 7003 return;
47926f60
KH		 7004
7005 default:
7006 break;
7007 }
7008#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7009 *valP = value;
f86103b7 7010#endif /* !defined (TE_Mach) */
3e73aa7c 7011
3e73aa7c 7012 /* Are we finished with this relocation now? */
c6682705 7013 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 7014 fixP->fx_done = 1;
7015 else if (use_rela_relocations)
7016 {
7017 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7018 /* Remember value for tc_gen_reloc. */
7019 fixP->fx_addnumber = value;
3e73aa7c
JH		 7020 value = 0;
7021 }
f86103b7 7022
94f592af 7023 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7024}
252b5132 7025\f
252b5132 7026char *
499ac353 7027md_atof (int type, char *litP, int *sizeP)
252b5132 7028{
499ac353
NC		 7029 /* This outputs the LITTLENUMs in REVERSE order;
7030 in accord with the bigendian 386. */
7031 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7032}
7033\f
2d545b82 7034static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7035
252b5132 7036static char *
e3bb37b5 7037output_invalid (int c)
252b5132 7038{
3882b010 7039 if (ISPRINT (c))
f9f21a03
L		 7040 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7041 "'%c'", c);
252b5132 7042 else
f9f21a03 7043 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7044 "(0x%x)", (unsigned char) c);
252b5132
RH		 7045 return output_invalid_buf;
7046}
7047
af6bdddf 7048/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7049
7050static const reg_entry *
4d1bb795 7051parse_real_register (char *reg_string, char **end_op)
252b5132 7052{
af6bdddf
AM		 7053 char *s = reg_string;
7054 char *p;
252b5132
RH		 7055 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7056 const reg_entry *r;
7057
7058 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7059 if (*s == REGISTER_PREFIX)
7060 ++s;
7061
7062 if (is_space_char (*s))
7063 ++s;
7064
7065 p = reg_name_given;
af6bdddf 7066 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7067 {
7068 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7069 return (const reg_entry *) NULL;
7070 s++;
252b5132
RH		 7071 }
7072
6588847e
DN		 7073 /* For naked regs, make sure that we are not dealing with an identifier.
7074 This prevents confusing an identifier like `eax_var' with register
7075 `eax'. */
7076 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7077 return (const reg_entry *) NULL;
7078
af6bdddf 7079 *end_op = s;
252b5132
RH		 7080
7081 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7082
5f47d35b 7083 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7084 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7085 {
5f47d35b
AM		 7086 if (is_space_char (*s))
7087 ++s;
7088 if (*s == '(')
7089 {
af6bdddf 7090 ++s;
5f47d35b
AM		 7091 if (is_space_char (*s))
7092 ++s;
7093 if (*s >= '0' && *s <= '7')
7094 {
db557034 7095 int fpr = *s - '0';
af6bdddf 7096 ++s;
5f47d35b
AM		 7097 if (is_space_char (*s))
7098 ++s;
7099 if (*s == ')')
7100 {
7101 *end_op = s + 1;
db557034
AM		 7102 r = hash_find (reg_hash, "st(0)");
7103 know (r);
7104 return r + fpr;
5f47d35b 7105 }
5f47d35b 7106 }
47926f60 7107 /* We have "%st(" then garbage. */
5f47d35b
AM		 7108 return (const reg_entry *) NULL;
7109 }
7110 }
7111
a60de03c
JB		 7112 if (r == NULL || allow_pseudo_reg)
7113 return r;
7114
0dfbf9d7 7115 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7116 return (const reg_entry *) NULL;
7117
db51cc60 7118 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7119 if (!allow_index_reg
db51cc60
L		 7120 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7121 return (const reg_entry *) NULL;
7122
a60de03c
JB		 7123 if (((r->reg_flags & (RegRex64 | RegRex))
7124 || r->reg_type.bitfield.reg64)
40fb9820 7125 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7126 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7127 && flag_code != CODE_64BIT)
20f0a1fc 7128 return (const reg_entry *) NULL;
1ae00879 7129
b7240065
JB		 7130 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7131 return (const reg_entry *) NULL;
7132
252b5132
RH		 7133 return r;
7134}
4d1bb795
JB		 7135
7136/* REG_STRING starts *before* REGISTER_PREFIX. */
7137
7138static const reg_entry *
7139parse_register (char *reg_string, char **end_op)
7140{
7141 const reg_entry *r;
7142
7143 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7144 r = parse_real_register (reg_string, end_op);
7145 else
7146 r = NULL;
7147 if (!r)
7148 {
7149 char *save = input_line_pointer;
7150 char c;
7151 symbolS *symbolP;
7152
7153 input_line_pointer = reg_string;
7154 c = get_symbol_end ();
7155 symbolP = symbol_find (reg_string);
7156 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7157 {
7158 const expressionS *e = symbol_get_value_expression (symbolP);
7159
7160 know (e->X_op == O_register);
4eed87de 7161 know (e->X_add_number >= 0
c3fe08fa 7162 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7163 r = i386_regtab + e->X_add_number;
7164 *end_op = input_line_pointer;
7165 }
7166 *input_line_pointer = c;
7167 input_line_pointer = save;
7168 }
7169 return r;
7170}
7171
7172int
7173i386_parse_name (char *name, expressionS *e, char *nextcharP)
7174{
7175 const reg_entry *r;
7176 char *end = input_line_pointer;
7177
7178 *end = *nextcharP;
7179 r = parse_register (name, &input_line_pointer);
7180 if (r && end <= input_line_pointer)
7181 {
7182 *nextcharP = *input_line_pointer;
7183 *input_line_pointer = 0;
7184 e->X_op = O_register;
7185 e->X_add_number = r - i386_regtab;
7186 return 1;
7187 }
7188 input_line_pointer = end;
7189 *end = 0;
7190 return 0;
7191}
7192
7193void
7194md_operand (expressionS *e)
7195{
7196 if (*input_line_pointer == REGISTER_PREFIX)
7197 {
7198 char *end;
7199 const reg_entry *r = parse_real_register (input_line_pointer, &end);
7200
7201 if (r)
7202 {
7203 e->X_op = O_register;
7204 e->X_add_number = r - i386_regtab;
7205 input_line_pointer = end;
7206 }
7207 }
7208}
7209
252b5132 7210\f
4cc782b5 7211#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7212const char *md_shortopts = "kVQ:sqn";
252b5132 7213#else
12b55ccc 7214const char *md_shortopts = "qn";
252b5132 7215#endif
6e0b89ee 7216
3e73aa7c 7217#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7218#define OPTION_64 (OPTION_MD_BASE + 1)
7219#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7220#define OPTION_MARCH (OPTION_MD_BASE + 3)
7221#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 7222#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7223#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7224#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7225#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7226#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
b3b91714 7227
99ad8390
NC		 7228struct option md_longopts[] =
7229{
3e73aa7c 7230 {"32", no_argument, NULL, OPTION_32},
99ad8390 7231#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 7232 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7233#endif
b3b91714 7234 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7235 {"march", required_argument, NULL, OPTION_MARCH},
7236 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 7237 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7238 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7239 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7240 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7241 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
252b5132
RH		 7242 {NULL, no_argument, NULL, 0}
7243};
7244size_t md_longopts_size = sizeof (md_longopts);
7245
7246int
9103f4f4 7247md_parse_option (int c, char *arg)
252b5132 7248{
9103f4f4 7249 unsigned int i;
6305a203 7250 char *arch, *next;
9103f4f4 7251
252b5132
RH		 7252 switch (c)
7253 {
12b55ccc
L		 7254 case 'n':
7255 optimize_align_code = 0;
7256 break;
7257
a38cf1db
AM		 7258 case 'q':
7259 quiet_warnings = 1;
252b5132
RH		 7260 break;
7261
7262#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7263 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7264 should be emitted or not. FIXME: Not implemented. */
7265 case 'Q':
252b5132
RH		 7266 break;
7267
7268 /* -V: SVR4 argument to print version ID. */
7269 case 'V':
7270 print_version_id ();
7271 break;
7272
a38cf1db
AM		 7273 /* -k: Ignore for FreeBSD compatibility. */
7274 case 'k':
252b5132 7275 break;
4cc782b5
ILT		 7276
7277 case 's':
7278 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 7279 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 7280 break;
99ad8390
NC		 7281#endif
7282#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 7283 case OPTION_64:
7284 {
7285 const char **list, **l;
7286
3e73aa7c
JH		 7287 list = bfd_target_list ();
7288 for (l = list; *l != NULL; l++)
8620418b 7289 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 7290 || strcmp (*l, "coff-x86-64") == 0
7291 || strcmp (*l, "pe-x86-64") == 0
7292 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 7293 {
7294 default_arch = "x86_64";
7295 break;
7296 }
3e73aa7c 7297 if (*l == NULL)
6e0b89ee 7298 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 7299 free (list);
7300 }
7301 break;
7302#endif
252b5132 7303
6e0b89ee
AM		 7304 case OPTION_32:
7305 default_arch = "i386";
7306 break;
7307
b3b91714
AM		 7308 case OPTION_DIVIDE:
7309#ifdef SVR4_COMMENT_CHARS
7310 {
7311 char *n, *t;
7312 const char *s;
7313
7314 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7315 t = n;
7316 for (s = i386_comment_chars; *s != '\0'; s++)
7317 if (*s != '/')
7318 *t++ = *s;
7319 *t = '\0';
7320 i386_comment_chars = n;
7321 }
7322#endif
7323 break;
7324
9103f4f4 7325 case OPTION_MARCH:
6305a203
L		 7326 arch = xstrdup (arg);
7327 do
9103f4f4 7328 {
6305a203
L		 7329 if (*arch == '.')
7330 as_fatal (_("Invalid -march= option: `%s'"), arg);
7331 next = strchr (arch, '+');
7332 if (next)
7333 *next++ = '\0';
7334 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
9103f4f4 7335 {
6305a203 7336 if (strcmp (arch, cpu_arch [i].name) == 0)
ccc9c027 7337 {
6305a203
L		 7338 /* Processor. */
7339 cpu_arch_name = cpu_arch[i].name;
7340 cpu_sub_arch_name = NULL;
7341 cpu_arch_flags = cpu_arch[i].flags;
7342 cpu_arch_isa = cpu_arch[i].type;
7343 cpu_arch_isa_flags = cpu_arch[i].flags;
7344 if (!cpu_arch_tune_set)
7345 {
7346 cpu_arch_tune = cpu_arch_isa;
7347 cpu_arch_tune_flags = cpu_arch_isa_flags;
7348 }
7349 break;
7350 }
7351 else if (*cpu_arch [i].name == '.'
7352 && strcmp (arch, cpu_arch [i].name + 1) == 0)
7353 {
7354 /* ISA entension. */
7355 i386_cpu_flags flags;
7356 flags = cpu_flags_or (cpu_arch_flags,
7357 cpu_arch[i].flags);
0dfbf9d7 7358 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 7359 {
7360 if (cpu_sub_arch_name)
7361 {
7362 char *name = cpu_sub_arch_name;
7363 cpu_sub_arch_name = concat (name,
7364 cpu_arch[i].name,
1bf57e9f 7365 (const char *) NULL);
6305a203
L		 7366 free (name);
7367 }
7368 else
7369 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
7370 cpu_arch_flags = flags;
7371 }
7372 break;
ccc9c027 7373 }
9103f4f4 7374 }
6305a203
L		 7375
7376 if (i >= ARRAY_SIZE (cpu_arch))
7377 as_fatal (_("Invalid -march= option: `%s'"), arg);
7378
7379 arch = next;
9103f4f4 7380 }
6305a203 7381 while (next != NULL );
9103f4f4
L		 7382 break;
7383
7384 case OPTION_MTUNE:
7385 if (*arg == '.')
7386 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7387 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7388 {
7389 if (strcmp (arg, cpu_arch [i].name) == 0)
7390 {
ccc9c027 7391 cpu_arch_tune_set = 1;
9103f4f4
L		 7392 cpu_arch_tune = cpu_arch [i].type;
7393 cpu_arch_tune_flags = cpu_arch[i].flags;
7394 break;
7395 }
7396 }
7397 if (i >= ARRAY_SIZE (cpu_arch))
7398 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7399 break;
7400
1efbbeb4
L		 7401 case OPTION_MMNEMONIC:
7402 if (strcasecmp (arg, "att") == 0)
7403 intel_mnemonic = 0;
7404 else if (strcasecmp (arg, "intel") == 0)
7405 intel_mnemonic = 1;
7406 else
7407 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
7408 break;
7409
7410 case OPTION_MSYNTAX:
7411 if (strcasecmp (arg, "att") == 0)
7412 intel_syntax = 0;
7413 else if (strcasecmp (arg, "intel") == 0)
7414 intel_syntax = 1;
7415 else
7416 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
7417 break;
7418
7419 case OPTION_MINDEX_REG:
7420 allow_index_reg = 1;
7421 break;
7422
7423 case OPTION_MNAKED_REG:
7424 allow_naked_reg = 1;
7425 break;
7426
7427 case OPTION_MOLD_GCC:
7428 old_gcc = 1;
1efbbeb4
L		 7429 break;
7430
252b5132
RH		 7431 default:
7432 return 0;
7433 }
7434 return 1;
7435}
7436
7437void
7438md_show_usage (stream)
7439 FILE *stream;
7440{
4cc782b5
ILT		 7441#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7442 fprintf (stream, _("\
a38cf1db
AM		 7443 -Q ignored\n\
7444 -V print assembler version number\n\
b3b91714
AM		 7445 -k ignored\n"));
7446#endif
7447 fprintf (stream, _("\
12b55ccc 7448 -n Do not optimize code alignment\n\
b3b91714
AM		 7449 -q quieten some warnings\n"));
7450#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7451 fprintf (stream, _("\
a38cf1db 7452 -s ignored\n"));
b3b91714 7453#endif
751d281c
L		 7454#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7455 fprintf (stream, _("\
7456 --32/--64 generate 32bit/64bit code\n"));
7457#endif
b3b91714
AM		 7458#ifdef SVR4_COMMENT_CHARS
7459 fprintf (stream, _("\
7460 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 7461#else
7462 fprintf (stream, _("\
b3b91714 7463 --divide ignored\n"));
4cc782b5 7464#endif
9103f4f4 7465 fprintf (stream, _("\
6305a203
L		 7466 -march=CPU[,+EXTENSION...]\n\
7467 generate code for CPU and EXTENSION, CPU is one of:\n\
2cb4f3d5
L		 7468 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7469 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7470 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
7471 generic32, generic64\n\
599121aa
L		 7472 EXTENSION is combination of:\n\
7473 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
f03fe4c1
L		 7474 vmx, smx, xsave, 3dnow, 3dnowa, sse4a, sse5, svme,\n\
7475 abm, padlock\n"));
6305a203 7476 fprintf (stream, _("\
2cb4f3d5
L		 7477 -mtune=CPU optimize for CPU, CPU is one of:\n\
7478 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7479 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7480 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
7481 generic32, generic64\n"));
ba104c83
L		 7482 fprintf (stream, _("\
7483 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
7484 fprintf (stream, _("\
7485 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
7486 fprintf (stream, _("\
7487 -mindex-reg support pseudo index registers\n"));
7488 fprintf (stream, _("\
7489 -mnaked-reg don't require `%%' prefix for registers\n"));
7490 fprintf (stream, _("\
7491 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 7492}
7493
3e73aa7c 7494#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 7495 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH		 7496
7497/* Pick the target format to use. */
7498
47926f60 7499const char *
e3bb37b5 7500i386_target_format (void)
252b5132 7501{
3e73aa7c 7502 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 7503 {
7504 set_code_flag (CODE_64BIT);
0dfbf9d7 7505 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 7506 {
7507 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7508 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7509 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7510 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7511 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7512 cpu_arch_isa_flags.bitfield.cpui686 = 1;
7513 cpu_arch_isa_flags.bitfield.cpup4 = 1;
7514 cpu_arch_isa_flags.bitfield.cpummx= 1;
40fb9820
L		 7515 cpu_arch_isa_flags.bitfield.cpusse = 1;
7516 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7517 }
0dfbf9d7 7518 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 7519 {
7520 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7521 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7522 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7523 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7524 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7525 cpu_arch_tune_flags.bitfield.cpui686 = 1;
7526 cpu_arch_tune_flags.bitfield.cpup4 = 1;
7527 cpu_arch_tune_flags.bitfield.cpummx= 1;
40fb9820
L		 7528 cpu_arch_tune_flags.bitfield.cpusse = 1;
7529 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7530 }
9103f4f4 7531 }
3e73aa7c 7532 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 7533 {
7534 set_code_flag (CODE_32BIT);
0dfbf9d7 7535 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 7536 {
7537 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7538 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7539 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7540 }
0dfbf9d7 7541 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 7542 {
7543 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7544 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7545 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7546 }
9103f4f4 7547 }
3e73aa7c
JH		 7548 else
7549 as_fatal (_("Unknown architecture"));
252b5132
RH		 7550 switch (OUTPUT_FLAVOR)
7551 {
872ce6ff
L		 7552#ifdef TE_PEP
7553 case bfd_target_coff_flavour:
7554 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
7555 break;
7556#endif
4c63da97
AM		 7557#ifdef OBJ_MAYBE_AOUT
7558 case bfd_target_aout_flavour:
47926f60 7559 return AOUT_TARGET_FORMAT;
4c63da97
AM		 7560#endif
7561#ifdef OBJ_MAYBE_COFF
252b5132
RH		 7562 case bfd_target_coff_flavour:
7563 return "coff-i386";
4c63da97 7564#endif
3e73aa7c 7565#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 7566 case bfd_target_elf_flavour:
3e73aa7c 7567 {
e5cb08ac 7568 if (flag_code == CODE_64BIT)
4fa24527
JB		 7569 {
7570 object_64bit = 1;
7571 use_rela_relocations = 1;
7572 }
9d7cbccd 7573 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 7574 }
4c63da97 7575#endif
252b5132
RH		 7576 default:
7577 abort ();
7578 return NULL;
7579 }
7580}
7581
47926f60 7582#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 7583
7584#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 7585void
7586i386_elf_emit_arch_note (void)
a847613f 7587{
718ddfc0 7588 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 7589 {
7590 char *p;
7591 asection *seg = now_seg;
7592 subsegT subseg = now_subseg;
7593 Elf_Internal_Note i_note;
7594 Elf_External_Note e_note;
7595 asection *note_secp;
7596 int len;
7597
7598 /* Create the .note section. */
7599 note_secp = subseg_new (".note", 0);
7600 bfd_set_section_flags (stdoutput,
7601 note_secp,
7602 SEC_HAS_CONTENTS | SEC_READONLY);
7603
7604 /* Process the arch string. */
7605 len = strlen (cpu_arch_name);
7606
7607 i_note.namesz = len + 1;
7608 i_note.descsz = 0;
7609 i_note.type = NT_ARCH;
7610 p = frag_more (sizeof (e_note.namesz));
7611 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
7612 p = frag_more (sizeof (e_note.descsz));
7613 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
7614 p = frag_more (sizeof (e_note.type));
7615 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
7616 p = frag_more (len + 1);
7617 strcpy (p, cpu_arch_name);
7618
7619 frag_align (2, 0, 0);
7620
7621 subseg_set (seg, subseg);
7622 }
7623}
7624#endif
252b5132 7625\f
252b5132
RH		 7626symbolS *
7627md_undefined_symbol (name)
7628 char *name;
7629{
18dc2407
ILT		 7630 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
7631 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
7632 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
7633 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 7634 {
7635 if (!GOT_symbol)
7636 {
7637 if (symbol_find (name))
7638 as_bad (_("GOT already in symbol table"));
7639 GOT_symbol = symbol_new (name, undefined_section,
7640 (valueT) 0, &zero_address_frag);
7641 };
7642 return GOT_symbol;
7643 }
252b5132
RH		 7644 return 0;
7645}
7646
7647/* Round up a section size to the appropriate boundary. */
47926f60 7648
252b5132
RH		 7649valueT
7650md_section_align (segment, size)
ab9da554 7651 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 7652 valueT size;
7653{
4c63da97
AM		 7654#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7655 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
7656 {
7657 /* For a.out, force the section size to be aligned. If we don't do
7658 this, BFD will align it for us, but it will not write out the
7659 final bytes of the section. This may be a bug in BFD, but it is
7660 easier to fix it here since that is how the other a.out targets
7661 work. */
7662 int align;
7663
7664 align = bfd_get_section_alignment (stdoutput, segment);
7665 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7666 }
252b5132
RH		 7667#endif
7668
7669 return size;
7670}
7671
7672/* On the i386, PC-relative offsets are relative to the start of the
7673 next instruction. That is, the address of the offset, plus its
7674 size, since the offset is always the last part of the insn. */
7675
7676long
e3bb37b5 7677md_pcrel_from (fixS *fixP)
252b5132
RH		 7678{
7679 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
7680}
7681
7682#ifndef I386COFF
7683
7684static void
e3bb37b5 7685s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 7686{
29b0f896 7687 int temp;
252b5132 7688
8a75718c
JB		 7689#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7690 if (IS_ELF)
7691 obj_elf_section_change_hook ();
7692#endif
252b5132
RH		 7693 temp = get_absolute_expression ();
7694 subseg_set (bss_section, (subsegT) temp);
7695 demand_empty_rest_of_line ();
7696}
7697
7698#endif
7699
252b5132 7700void
e3bb37b5 7701i386_validate_fix (fixS *fixp)
252b5132
RH		 7702{
7703 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
7704 {
23df1078
JH		 7705 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
7706 {
4fa24527 7707 if (!object_64bit)
23df1078
JH		 7708 abort ();
7709 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
7710 }
7711 else
7712 {
4fa24527 7713 if (!object_64bit)
d6ab8113
JB		 7714 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
7715 else
7716 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 7717 }
252b5132
RH		 7718 fixp->fx_subsy = 0;
7719 }
7720}
7721
252b5132
RH		 7722arelent *
7723tc_gen_reloc (section, fixp)
ab9da554 7724 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 7725 fixS *fixp;
7726{
7727 arelent *rel;
7728 bfd_reloc_code_real_type code;
7729
7730 switch (fixp->fx_r_type)
7731 {
3e73aa7c
JH		 7732 case BFD_RELOC_X86_64_PLT32:
7733 case BFD_RELOC_X86_64_GOT32:
7734 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 7735 case BFD_RELOC_386_PLT32:
7736 case BFD_RELOC_386_GOT32:
7737 case BFD_RELOC_386_GOTOFF:
7738 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 7739 case BFD_RELOC_386_TLS_GD:
7740 case BFD_RELOC_386_TLS_LDM:
7741 case BFD_RELOC_386_TLS_LDO_32:
7742 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7743 case BFD_RELOC_386_TLS_IE:
7744 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 7745 case BFD_RELOC_386_TLS_LE_32:
7746 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 7747 case BFD_RELOC_386_TLS_GOTDESC:
7748 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 7749 case BFD_RELOC_X86_64_TLSGD:
7750 case BFD_RELOC_X86_64_TLSLD:
7751 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7752 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 7753 case BFD_RELOC_X86_64_GOTTPOFF:
7754 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 7755 case BFD_RELOC_X86_64_TPOFF64:
7756 case BFD_RELOC_X86_64_GOTOFF64:
7757 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 7758 case BFD_RELOC_X86_64_GOT64:
7759 case BFD_RELOC_X86_64_GOTPCREL64:
7760 case BFD_RELOC_X86_64_GOTPC64:
7761 case BFD_RELOC_X86_64_GOTPLT64:
7762 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 7763 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7764 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 7765 case BFD_RELOC_RVA:
7766 case BFD_RELOC_VTABLE_ENTRY:
7767 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 7768#ifdef TE_PE
7769 case BFD_RELOC_32_SECREL:
7770#endif
252b5132
RH		 7771 code = fixp->fx_r_type;
7772 break;
dbbaec26
L		 7773 case BFD_RELOC_X86_64_32S:
7774 if (!fixp->fx_pcrel)
7775 {
7776 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7777 code = fixp->fx_r_type;
7778 break;
7779 }
252b5132 7780 default:
93382f6d 7781 if (fixp->fx_pcrel)
252b5132 7782 {
93382f6d
AM		 7783 switch (fixp->fx_size)
7784 {
7785 default:
b091f402
AM		 7786 as_bad_where (fixp->fx_file, fixp->fx_line,
7787 _("can not do %d byte pc-relative relocation"),
7788 fixp->fx_size);
93382f6d
AM		 7789 code = BFD_RELOC_32_PCREL;
7790 break;
7791 case 1: code = BFD_RELOC_8_PCREL; break;
7792 case 2: code = BFD_RELOC_16_PCREL; break;
7793 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 7794#ifdef BFD64
7795 case 8: code = BFD_RELOC_64_PCREL; break;
7796#endif
93382f6d
AM		 7797 }
7798 }
7799 else
7800 {
7801 switch (fixp->fx_size)
7802 {
7803 default:
b091f402
AM		 7804 as_bad_where (fixp->fx_file, fixp->fx_line,
7805 _("can not do %d byte relocation"),
7806 fixp->fx_size);
93382f6d
AM		 7807 code = BFD_RELOC_32;
7808 break;
7809 case 1: code = BFD_RELOC_8; break;
7810 case 2: code = BFD_RELOC_16; break;
7811 case 4: code = BFD_RELOC_32; break;
937149dd 7812#ifdef BFD64
3e73aa7c 7813 case 8: code = BFD_RELOC_64; break;
937149dd 7814#endif
93382f6d 7815 }
252b5132
RH		 7816 }
7817 break;
7818 }
252b5132 7819
d182319b
JB		 7820 if ((code == BFD_RELOC_32
7821 || code == BFD_RELOC_32_PCREL
7822 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 7823 && GOT_symbol
7824 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 7825 {
4fa24527 7826 if (!object_64bit)
d6ab8113
JB		 7827 code = BFD_RELOC_386_GOTPC;
7828 else
7829 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 7830 }
7b81dfbb
AJ		 7831 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7832 && GOT_symbol
7833 && fixp->fx_addsy == GOT_symbol)
7834 {
7835 code = BFD_RELOC_X86_64_GOTPC64;
7836 }
252b5132
RH		 7837
7838 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 7839 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7840 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 7841
7842 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 7843
3e73aa7c
JH		 7844 if (!use_rela_relocations)
7845 {
7846 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7847 vtable entry to be used in the relocation's section offset. */
7848 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7849 rel->address = fixp->fx_offset;
252b5132 7850
c6682705 7851 rel->addend = 0;
3e73aa7c
JH		 7852 }
7853 /* Use the rela in 64bit mode. */
252b5132 7854 else
3e73aa7c 7855 {
062cd5e7
AS		 7856 if (!fixp->fx_pcrel)
7857 rel->addend = fixp->fx_offset;
7858 else
7859 switch (code)
7860 {
7861 case BFD_RELOC_X86_64_PLT32:
7862 case BFD_RELOC_X86_64_GOT32:
7863 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 7864 case BFD_RELOC_X86_64_TLSGD:
7865 case BFD_RELOC_X86_64_TLSLD:
7866 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 7867 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7868 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 7869 rel->addend = fixp->fx_offset - fixp->fx_size;
7870 break;
7871 default:
7872 rel->addend = (section->vma
7873 - fixp->fx_size
7874 + fixp->fx_addnumber
7875 + md_pcrel_from (fixp));
7876 break;
7877 }
3e73aa7c
JH		 7878 }
7879
252b5132
RH		 7880 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7881 if (rel->howto == NULL)
7882 {
7883 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 7884 _("cannot represent relocation type %s"),
252b5132
RH		 7885 bfd_get_reloc_code_name (code));
7886 /* Set howto to a garbage value so that we can keep going. */
7887 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7888 assert (rel->howto != NULL);
7889 }
7890
7891 return rel;
7892}
7893
64a0c779
DN		 7894\f
7895/* Parse operands using Intel syntax. This implements a recursive descent
7896 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7897 Programmer's Guide.
7898
7899 FIXME: We do not recognize the full operand grammar defined in the MASM
7900 documentation. In particular, all the structure/union and
7901 high-level macro operands are missing.
7902
7903 Uppercase words are terminals, lower case words are non-terminals.
7904 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7905 bars '|' denote choices. Most grammar productions are implemented in
7906 functions called 'intel_<production>'.
7907
7908 Initial production is 'expr'.
7909
9306ca4a 7910 addOp + | -
64a0c779
DN		 7911
7912 alpha [a-zA-Z]
7913
9306ca4a
JB		 7914 binOp & | AND | \| | OR | ^ | XOR
7915
64a0c779
DN		 7916 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7917
7918 constant digits [[ radixOverride ]]
7919
9306ca4a 7920 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 7921
7922 digits decdigit
b77a7acd
AJ		 7923 | digits decdigit
7924 | digits hexdigit
64a0c779
DN		 7925
7926 decdigit [0-9]
7927
9306ca4a
JB		 7928 e04 e04 addOp e05
7929 | e05
7930
7931 e05 e05 binOp e06
b77a7acd 7932 | e06
64a0c779
DN		 7933
7934 e06 e06 mulOp e09
b77a7acd 7935 | e09
64a0c779
DN		 7936
7937 e09 OFFSET e10
a724f0f4
JB		 7938 | SHORT e10
7939 | + e10
7940 | - e10
9306ca4a
JB		 7941 | ~ e10
7942 | NOT e10
64a0c779
DN		 7943 | e09 PTR e10
7944 | e09 : e10
7945 | e10
7946
7947 e10 e10 [ expr ]
b77a7acd 7948 | e11
64a0c779
DN		 7949
7950 e11 ( expr )
b77a7acd 7951 | [ expr ]
64a0c779
DN		 7952 | constant
7953 | dataType
7954 | id
7955 | $
7956 | register
7957
a724f0f4 7958 => expr expr cmpOp e04
9306ca4a 7959 | e04
64a0c779
DN		 7960
7961 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 7962 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 7963
7964 hexdigit a | b | c | d | e | f
b77a7acd 7965 | A | B | C | D | E | F
64a0c779
DN		 7966
7967 id alpha
b77a7acd 7968 | id alpha
64a0c779
DN		 7969 | id decdigit
7970
9306ca4a 7971 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 7972
7973 quote " | '
7974
7975 register specialRegister
b77a7acd 7976 | gpRegister
64a0c779
DN		 7977 | byteRegister
7978
7979 segmentRegister CS | DS | ES | FS | GS | SS
7980
9306ca4a 7981 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 7982 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 7983 | TR3 | TR4 | TR5 | TR6 | TR7
7984
64a0c779
DN		 7985 We simplify the grammar in obvious places (e.g., register parsing is
7986 done by calling parse_register) and eliminate immediate left recursion
7987 to implement a recursive-descent parser.
7988
a724f0f4
JB		 7989 expr e04 expr'
7990
7991 expr' cmpOp e04 expr'
7992 | Empty
9306ca4a
JB		 7993
7994 e04 e05 e04'
7995
7996 e04' addOp e05 e04'
7997 | Empty
64a0c779
DN		 7998
7999 e05 e06 e05'
8000
9306ca4a 8001 e05' binOp e06 e05'
b77a7acd 8002 | Empty
64a0c779
DN		 8003
8004 e06 e09 e06'
8005
8006 e06' mulOp e09 e06'
b77a7acd 8007 | Empty
64a0c779
DN		 8008
8009 e09 OFFSET e10 e09'
a724f0f4
JB		 8010 | SHORT e10'
8011 | + e10'
8012 | - e10'
8013 | ~ e10'
8014 | NOT e10'
b77a7acd 8015 | e10 e09'
64a0c779
DN		 8016
8017 e09' PTR e10 e09'
b77a7acd 8018 | : e10 e09'
64a0c779
DN		 8019 | Empty
8020
8021 e10 e11 e10'
8022
8023 e10' [ expr ] e10'
b77a7acd 8024 | Empty
64a0c779
DN		 8025
8026 e11 ( expr )
b77a7acd 8027 | [ expr ]
64a0c779
DN		 8028 | BYTE
8029 | WORD
8030 | DWORD
9306ca4a 8031 | FWORD
64a0c779 8032 | QWORD
9306ca4a
JB		 8033 | TBYTE
8034 | OWORD
8035 | XMMWORD
64a0c779
DN		 8036 | .
8037 | $
8038 | register
8039 | id
8040 | constant */
8041
8042/* Parsing structure for the intel syntax parser. Used to implement the
8043 semantic actions for the operand grammar. */
8044struct intel_parser_s
8045 {
8046 char *op_string; /* The string being parsed. */
8047 int got_a_float; /* Whether the operand is a float. */
4a1805b1 8048 int op_modifier; /* Operand modifier. */
64a0c779 8049 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 8050 int in_offset; /* >=1 if parsing operand of offset. */
8051 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 8052 const reg_entry *reg; /* Last register reference found. */
8053 char *disp; /* Displacement string being built. */
a724f0f4 8054 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 8055 };
8056
8057static struct intel_parser_s intel_parser;
8058
8059/* Token structure for parsing intel syntax. */
8060struct intel_token
8061 {
8062 int code; /* Token code. */
8063 const reg_entry *reg; /* Register entry for register tokens. */
8064 char *str; /* String representation. */
8065 };
8066
8067static struct intel_token cur_token, prev_token;
8068
50705ef4
AM		 8069/* Token codes for the intel parser. Since T_SHORT is already used
8070 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 8071#define T_NIL -1
8072#define T_CONST 1
8073#define T_REG 2
8074#define T_BYTE 3
8075#define T_WORD 4
9306ca4a
JB		 8076#define T_DWORD 5
8077#define T_FWORD 6
8078#define T_QWORD 7
8079#define T_TBYTE 8
8080#define T_XMMWORD 9
50705ef4 8081#undef T_SHORT
9306ca4a
JB		 8082#define T_SHORT 10
8083#define T_OFFSET 11
8084#define T_PTR 12
8085#define T_ID 13
8086#define T_SHL 14
8087#define T_SHR 15
64a0c779
DN		 8088
8089/* Prototypes for intel parser functions. */
e3bb37b5
L		 8090static int intel_match_token (int);
8091static void intel_putback_token (void);
8092static void intel_get_token (void);
8093static int intel_expr (void);
8094static int intel_e04 (void);
8095static int intel_e05 (void);
8096static int intel_e06 (void);
8097static int intel_e09 (void);
8098static int intel_e10 (void);
8099static int intel_e11 (void);
64a0c779 8100
64a0c779 8101static int
e3bb37b5 8102i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 8103{
8104 int ret;
8105 char *p;
8106
a724f0f4
JB		 8107 p = intel_parser.op_string = xstrdup (operand_string);
8108 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
8109
8110 for (;;)
64a0c779 8111 {
a724f0f4
JB		 8112 /* Initialize token holders. */
8113 cur_token.code = prev_token.code = T_NIL;
8114 cur_token.reg = prev_token.reg = NULL;
8115 cur_token.str = prev_token.str = NULL;
8116
8117 /* Initialize parser structure. */
8118 intel_parser.got_a_float = got_a_float;
8119 intel_parser.op_modifier = 0;
8120 intel_parser.is_mem = 0;
8121 intel_parser.in_offset = 0;
8122 intel_parser.in_bracket = 0;
8123 intel_parser.reg = NULL;
8124 intel_parser.disp[0] = '\0';
8125 intel_parser.next_operand = NULL;
8126
8127 /* Read the first token and start the parser. */
8128 intel_get_token ();
8129 ret = intel_expr ();
8130
8131 if (!ret)
8132 break;
8133
9306ca4a
JB		 8134 if (cur_token.code != T_NIL)
8135 {
8136 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8137 current_templates->start->name, cur_token.str);
8138 ret = 0;
8139 }
64a0c779
DN		 8140 /* If we found a memory reference, hand it over to i386_displacement
8141 to fill in the rest of the operand fields. */
9306ca4a 8142 else if (intel_parser.is_mem)
64a0c779
DN		 8143 {
8144 if ((i.mem_operands == 1
40fb9820 8145 && !current_templates->start->opcode_modifier.isstring)
64a0c779
DN		 8146 || i.mem_operands == 2)
8147 {
8148 as_bad (_("too many memory references for '%s'"),
8149 current_templates->start->name);
8150 ret = 0;
8151 }
8152 else
8153 {
8154 char *s = intel_parser.disp;
5c07affc 8155 i.types[this_operand].bitfield.mem = 1;
64a0c779
DN		 8156 i.mem_operands++;
8157
a724f0f4
JB		 8158 if (!quiet_warnings && intel_parser.is_mem < 0)
8159 /* See the comments in intel_bracket_expr. */
8160 as_warn (_("Treating `%s' as memory reference"), operand_string);
8161
64a0c779
DN		 8162 /* Add the displacement expression. */
8163 if (*s != '\0')
a4622f40
AM		 8164 ret = i386_displacement (s, s + strlen (s));
8165 if (ret)
a724f0f4
JB		 8166 {
8167 /* Swap base and index in 16-bit memory operands like
8168 [si+bx]. Since i386_index_check is also used in AT&T
8169 mode we have to do that here. */
8170 if (i.base_reg
8171 && i.index_reg
40fb9820
L		 8172 && i.base_reg->reg_type.bitfield.reg16
8173 && i.index_reg->reg_type.bitfield.reg16
a724f0f4
JB		 8174 && i.base_reg->reg_num >= 6
8175 && i.index_reg->reg_num < 6)
8176 {
8177 const reg_entry *base = i.index_reg;
8178
8179 i.index_reg = i.base_reg;
8180 i.base_reg = base;
8181 }
8182 ret = i386_index_check (operand_string);
8183 }
64a0c779
DN		 8184 }
8185 }
8186
8187 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 8188 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779 8189 || intel_parser.reg == NULL)
b7240065
JB		 8190 {
8191 if (i.mem_operands < 2 && i.seg[i.mem_operands])
8192 {
8193 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8194 as_warn (_("Segment override ignored"));
8195 i.seg[i.mem_operands] = NULL;
8196 }
8197 ret = i386_immediate (intel_parser.disp);
8198 }
a724f0f4
JB		 8199
8200 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 8201 ret = 0;
a724f0f4
JB		 8202 if (!ret || !intel_parser.next_operand)
8203 break;
8204 intel_parser.op_string = intel_parser.next_operand;
8205 this_operand = i.operands++;
7d5e4556 8206 i.types[this_operand].bitfield.unspecified = 1;
64a0c779
DN		 8207 }
8208
8209 free (p);
8210 free (intel_parser.disp);
8211
8212 return ret;
8213}
8214
a724f0f4
JB		 8215#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
8216
8217/* expr e04 expr'
8218
8219 expr' cmpOp e04 expr'
8220 | Empty */
64a0c779 8221static int
e3bb37b5 8222intel_expr (void)
64a0c779 8223{
a724f0f4
JB		 8224 /* XXX Implement the comparison operators. */
8225 return intel_e04 ();
9306ca4a
JB		 8226}
8227
a724f0f4 8228/* e04 e05 e04'
9306ca4a 8229
a724f0f4 8230 e04' addOp e05 e04'
9306ca4a
JB		 8231 | Empty */
8232static int
e3bb37b5 8233intel_e04 (void)
9306ca4a 8234{
a724f0f4 8235 int nregs = -1;
9306ca4a 8236
a724f0f4 8237 for (;;)
9306ca4a 8238 {
a724f0f4
JB		 8239 if (!intel_e05())
8240 return 0;
9306ca4a 8241
a724f0f4
JB		 8242 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8243 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 8244
a724f0f4
JB		 8245 if (cur_token.code == '+')
8246 nregs = -1;
8247 else if (cur_token.code == '-')
8248 nregs = NUM_ADDRESS_REGS;
8249 else
8250 return 1;
64a0c779 8251
a724f0f4
JB		 8252 strcat (intel_parser.disp, cur_token.str);
8253 intel_match_token (cur_token.code);
8254 }
64a0c779
DN		 8255}
8256
64a0c779
DN		 8257/* e05 e06 e05'
8258
9306ca4a 8259 e05' binOp e06 e05'
64a0c779
DN		 8260 | Empty */
8261static int
e3bb37b5 8262intel_e05 (void)
64a0c779 8263{
a724f0f4 8264 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 8265
a724f0f4 8266 for (;;)
64a0c779 8267 {
a724f0f4
JB		 8268 if (!intel_e06())
8269 return 0;
8270
4eed87de
AM		 8271 if (cur_token.code == '&'
8272 || cur_token.code == '|'
8273 || cur_token.code == '^')
a724f0f4
JB		 8274 {
8275 char str[2];
8276
8277 str[0] = cur_token.code;
8278 str[1] = 0;
8279 strcat (intel_parser.disp, str);
8280 }
8281 else
8282 break;
9306ca4a 8283
64a0c779
DN		 8284 intel_match_token (cur_token.code);
8285
a724f0f4
JB		 8286 if (nregs < 0)
8287 nregs = ~nregs;
64a0c779 8288 }
a724f0f4
JB		 8289 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8290 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
8291 return 1;
4a1805b1 8292}
64a0c779
DN		 8293
8294/* e06 e09 e06'
8295
8296 e06' mulOp e09 e06'
b77a7acd 8297 | Empty */
64a0c779 8298static int
e3bb37b5 8299intel_e06 (void)
64a0c779 8300{
a724f0f4 8301 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 8302
a724f0f4 8303 for (;;)
64a0c779 8304 {
a724f0f4
JB		 8305 if (!intel_e09())
8306 return 0;
9306ca4a 8307
4eed87de
AM		 8308 if (cur_token.code == '*'
8309 || cur_token.code == '/'
8310 || cur_token.code == '%')
a724f0f4
JB		 8311 {
8312 char str[2];
9306ca4a 8313
a724f0f4
JB		 8314 str[0] = cur_token.code;
8315 str[1] = 0;
8316 strcat (intel_parser.disp, str);
8317 }
8318 else if (cur_token.code == T_SHL)
8319 strcat (intel_parser.disp, "<<");
8320 else if (cur_token.code == T_SHR)
8321 strcat (intel_parser.disp, ">>");
8322 else
8323 break;
9306ca4a 8324
64e74474 8325 intel_match_token (cur_token.code);
64a0c779 8326
a724f0f4
JB		 8327 if (nregs < 0)
8328 nregs = ~nregs;
64a0c779 8329 }
a724f0f4
JB		 8330 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8331 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
8332 return 1;
64a0c779
DN		 8333}
8334
a724f0f4
JB		 8335/* e09 OFFSET e09
8336 | SHORT e09
8337 | + e09
8338 | - e09
8339 | ~ e09
8340 | NOT e09
9306ca4a
JB		 8341 | e10 e09'
8342
64a0c779 8343 e09' PTR e10 e09'
b77a7acd 8344 | : e10 e09'
64a0c779
DN		 8345 | Empty */
8346static int
e3bb37b5 8347intel_e09 (void)
64a0c779 8348{
a724f0f4
JB		 8349 int nregs = ~NUM_ADDRESS_REGS;
8350 int in_offset = 0;
8351
8352 for (;;)
64a0c779 8353 {
a724f0f4
JB		 8354 /* Don't consume constants here. */
8355 if (cur_token.code == '+' || cur_token.code == '-')
8356 {
8357 /* Need to look one token ahead - if the next token
8358 is a constant, the current token is its sign. */
8359 int next_code;
8360
8361 intel_match_token (cur_token.code);
8362 next_code = cur_token.code;
8363 intel_putback_token ();
8364 if (next_code == T_CONST)
8365 break;
8366 }
8367
8368 /* e09 OFFSET e09 */
8369 if (cur_token.code == T_OFFSET)
8370 {
8371 if (!in_offset++)
8372 ++intel_parser.in_offset;
8373 }
8374
8375 /* e09 SHORT e09 */
8376 else if (cur_token.code == T_SHORT)
8377 intel_parser.op_modifier |= 1 << T_SHORT;
8378
8379 /* e09 + e09 */
8380 else if (cur_token.code == '+')
8381 strcat (intel_parser.disp, "+");
8382
8383 /* e09 - e09
8384 | ~ e09
8385 | NOT e09 */
8386 else if (cur_token.code == '-' || cur_token.code == '~')
8387 {
8388 char str[2];
64a0c779 8389
a724f0f4
JB		 8390 if (nregs < 0)
8391 nregs = ~nregs;
8392 str[0] = cur_token.code;
8393 str[1] = 0;
8394 strcat (intel_parser.disp, str);
8395 }
8396
8397 /* e09 e10 e09' */
8398 else
8399 break;
8400
8401 intel_match_token (cur_token.code);
64a0c779
DN		 8402 }
8403
a724f0f4 8404 for (;;)
9306ca4a 8405 {
a724f0f4
JB		 8406 if (!intel_e10 ())
8407 return 0;
9306ca4a 8408
a724f0f4
JB		 8409 /* e09' PTR e10 e09' */
8410 if (cur_token.code == T_PTR)
8411 {
8412 char suffix;
9306ca4a 8413
a724f0f4 8414 if (prev_token.code == T_BYTE)
7d5e4556
L		 8415 {
8416 suffix = BYTE_MNEM_SUFFIX;
8417 i.types[this_operand].bitfield.byte = 1;
8418 }
9306ca4a 8419
a724f0f4
JB		 8420 else if (prev_token.code == T_WORD)
8421 {
34b772a6
JB		 8422 if ((current_templates->start->name[0] == 'l'
8423 && current_templates->start->name[2] == 's'
8424 && current_templates->start->name[3] == 0)
8425 || current_templates->start->base_opcode == 0x62 /* bound */)
a724f0f4
JB		 8426 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8427 else if (intel_parser.got_a_float == 2) /* "fi..." */
8428 suffix = SHORT_MNEM_SUFFIX;
8429 else
8430 suffix = WORD_MNEM_SUFFIX;
7d5e4556 8431 i.types[this_operand].bitfield.word = 1;
a724f0f4 8432 }
64a0c779 8433
a724f0f4
JB		 8434 else if (prev_token.code == T_DWORD)
8435 {
34b772a6
JB		 8436 if ((current_templates->start->name[0] == 'l'
8437 && current_templates->start->name[2] == 's'
8438 && current_templates->start->name[3] == 0)
8439 || current_templates->start->base_opcode == 0x62 /* bound */)
a724f0f4
JB		 8440 suffix = WORD_MNEM_SUFFIX;
8441 else if (flag_code == CODE_16BIT
40fb9820
L		 8442 && (current_templates->start->opcode_modifier.jump
8443 || current_templates->start->opcode_modifier.jumpdword))
a724f0f4
JB		 8444 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8445 else if (intel_parser.got_a_float == 1) /* "f..." */
8446 suffix = SHORT_MNEM_SUFFIX;
8447 else
8448 suffix = LONG_MNEM_SUFFIX;
7d5e4556 8449 i.types[this_operand].bitfield.dword = 1;
a724f0f4 8450 }
9306ca4a 8451
a724f0f4
JB		 8452 else if (prev_token.code == T_FWORD)
8453 {
8454 if (current_templates->start->name[0] == 'l'
8455 && current_templates->start->name[2] == 's'
8456 && current_templates->start->name[3] == 0)
8457 suffix = LONG_MNEM_SUFFIX;
8458 else if (!intel_parser.got_a_float)
8459 {
8460 if (flag_code == CODE_16BIT)
8461 add_prefix (DATA_PREFIX_OPCODE);
8462 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8463 }
8464 else
8465 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7d5e4556 8466 i.types[this_operand].bitfield.fword = 1;
a724f0f4 8467 }
64a0c779 8468
a724f0f4
JB		 8469 else if (prev_token.code == T_QWORD)
8470 {
34b772a6
JB		 8471 if (current_templates->start->base_opcode == 0x62 /* bound */
8472 || intel_parser.got_a_float == 1) /* "f..." */
a724f0f4
JB		 8473 suffix = LONG_MNEM_SUFFIX;
8474 else
34b772a6 8475 suffix = QWORD_MNEM_SUFFIX;
7d5e4556 8476 i.types[this_operand].bitfield.qword = 1;
a724f0f4 8477 }
64a0c779 8478
a724f0f4
JB		 8479 else if (prev_token.code == T_TBYTE)
8480 {
8481 if (intel_parser.got_a_float == 1)
8482 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8483 else
8484 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8485 }
9306ca4a 8486
a724f0f4 8487 else if (prev_token.code == T_XMMWORD)
9306ca4a 8488 {
582d5edd 8489 suffix = XMMWORD_MNEM_SUFFIX;
7d5e4556 8490 i.types[this_operand].bitfield.xmmword = 1;
9306ca4a 8491 }
64a0c779 8492
f16b83df 8493 else
a724f0f4
JB		 8494 {
8495 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
8496 return 0;
8497 }
8498
7d5e4556
L		 8499 i.types[this_operand].bitfield.unspecified = 0;
8500
435acd52
JB		 8501 /* Operands for jump/call using 'ptr' notation denote absolute
8502 addresses. */
40fb9820
L		 8503 if (current_templates->start->opcode_modifier.jump
8504 || current_templates->start->opcode_modifier.jumpdword)
8505 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 8506
a724f0f4
JB		 8507 if (current_templates->start->base_opcode == 0x8d /* lea */)
8508 ;
8509 else if (!i.suffix)
8510 i.suffix = suffix;
8511 else if (i.suffix != suffix)
8512 {
8513 as_bad (_("Conflicting operand modifiers"));
8514 return 0;
8515 }
64a0c779 8516
9306ca4a
JB		 8517 }
8518
a724f0f4
JB		 8519 /* e09' : e10 e09' */
8520 else if (cur_token.code == ':')
9306ca4a 8521 {
a724f0f4
JB		 8522 if (prev_token.code != T_REG)
8523 {
8524 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8525 segment/group identifier (which we don't have), using comma
8526 as the operand separator there is even less consistent, since
8527 there all branches only have a single operand. */
8528 if (this_operand != 0
8529 || intel_parser.in_offset
8530 || intel_parser.in_bracket
40fb9820
L		 8531 || (!current_templates->start->opcode_modifier.jump
8532 && !current_templates->start->opcode_modifier.jumpdword
8533 && !current_templates->start->opcode_modifier.jumpintersegment
8534 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
a724f0f4
JB		 8535 return intel_match_token (T_NIL);
8536 /* Remember the start of the 2nd operand and terminate 1st
8537 operand here.
8538 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8539 another expression), but it gets at least the simplest case
8540 (a plain number or symbol on the left side) right. */
8541 intel_parser.next_operand = intel_parser.op_string;
8542 *--intel_parser.op_string = '\0';
8543 return intel_match_token (':');
8544 }
9306ca4a 8545 }
64a0c779 8546
a724f0f4 8547 /* e09' Empty */
64a0c779 8548 else
a724f0f4 8549 break;
64a0c779 8550
a724f0f4
JB		 8551 intel_match_token (cur_token.code);
8552
8553 }
8554
8555 if (in_offset)
8556 {
8557 --intel_parser.in_offset;
8558 if (nregs < 0)
8559 nregs = ~nregs;
8560 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 8561 {
a724f0f4 8562 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 8563 return 0;
8564 }
a724f0f4
JB		 8565 intel_parser.op_modifier |= 1 << T_OFFSET;
8566 }
9306ca4a 8567
a724f0f4
JB		 8568 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8569 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
8570 return 1;
8571}
64a0c779 8572
a724f0f4 8573static int
e3bb37b5 8574intel_bracket_expr (void)
a724f0f4
JB		 8575{
8576 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
8577 const char *start = intel_parser.op_string;
8578 int len;
8579
8580 if (i.op[this_operand].regs)
8581 return intel_match_token (T_NIL);
8582
8583 intel_match_token ('[');
8584
8585 /* Mark as a memory operand only if it's not already known to be an
8586 offset expression. If it's an offset expression, we need to keep
8587 the brace in. */
8588 if (!intel_parser.in_offset)
8589 {
8590 ++intel_parser.in_bracket;
435acd52
JB		 8591
8592 /* Operands for jump/call inside brackets denote absolute addresses. */
40fb9820
L		 8593 if (current_templates->start->opcode_modifier.jump
8594 || current_templates->start->opcode_modifier.jumpdword)
8595 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 8596
a724f0f4
JB		 8597 /* Unfortunately gas always diverged from MASM in a respect that can't
8598 be easily fixed without risking to break code sequences likely to be
8599 encountered (the testsuite even check for this): MASM doesn't consider
8600 an expression inside brackets unconditionally as a memory reference.
8601 When that is e.g. a constant, an offset expression, or the sum of the
8602 two, this is still taken as a constant load. gas, however, always
8603 treated these as memory references. As a compromise, we'll try to make
8604 offset expressions inside brackets work the MASM way (since that's
8605 less likely to be found in real world code), but make constants alone
8606 continue to work the traditional gas way. In either case, issue a
8607 warning. */
8608 intel_parser.op_modifier &= ~was_offset;
64a0c779 8609 }
a724f0f4 8610 else
64e74474 8611 strcat (intel_parser.disp, "[");
a724f0f4
JB		 8612
8613 /* Add a '+' to the displacement string if necessary. */
8614 if (*intel_parser.disp != '\0'
8615 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
8616 strcat (intel_parser.disp, "+");
64a0c779 8617
a724f0f4
JB		 8618 if (intel_expr ()
8619 && (len = intel_parser.op_string - start - 1,
8620 intel_match_token (']')))
64a0c779 8621 {
a724f0f4
JB		 8622 /* Preserve brackets when the operand is an offset expression. */
8623 if (intel_parser.in_offset)
8624 strcat (intel_parser.disp, "]");
8625 else
8626 {
8627 --intel_parser.in_bracket;
8628 if (i.base_reg || i.index_reg)
8629 intel_parser.is_mem = 1;
8630 if (!intel_parser.is_mem)
8631 {
8632 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8633 /* Defer the warning until all of the operand was parsed. */
8634 intel_parser.is_mem = -1;
8635 else if (!quiet_warnings)
4eed87de
AM		 8636 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8637 len, start, len, start);
a724f0f4
JB		 8638 }
8639 }
8640 intel_parser.op_modifier |= was_offset;
64a0c779 8641
a724f0f4 8642 return 1;
64a0c779 8643 }
a724f0f4 8644 return 0;
64a0c779
DN		 8645}
8646
8647/* e10 e11 e10'
8648
8649 e10' [ expr ] e10'
b77a7acd 8650 | Empty */
64a0c779 8651static int
e3bb37b5 8652intel_e10 (void)
64a0c779 8653{
a724f0f4
JB		 8654 if (!intel_e11 ())
8655 return 0;
64a0c779 8656
a724f0f4 8657 while (cur_token.code == '[')
64a0c779 8658 {
a724f0f4 8659 if (!intel_bracket_expr ())
21d6c4af 8660 return 0;
64a0c779
DN		 8661 }
8662
a724f0f4 8663 return 1;
64a0c779
DN		 8664}
8665
64a0c779 8666/* e11 ( expr )
b77a7acd 8667 | [ expr ]
64a0c779
DN		 8668 | BYTE
8669 | WORD
8670 | DWORD
9306ca4a 8671 | FWORD
64a0c779 8672 | QWORD
9306ca4a
JB		 8673 | TBYTE
8674 | OWORD
8675 | XMMWORD
4a1805b1 8676 | $
64a0c779
DN		 8677 | .
8678 | register
8679 | id
8680 | constant */
8681static int
e3bb37b5 8682intel_e11 (void)
64a0c779 8683{
a724f0f4 8684 switch (cur_token.code)
64a0c779 8685 {
a724f0f4
JB		 8686 /* e11 ( expr ) */
8687 case '(':
64a0c779
DN		 8688 intel_match_token ('(');
8689 strcat (intel_parser.disp, "(");
8690
8691 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 8692 {
8693 strcat (intel_parser.disp, ")");
8694 return 1;
8695 }
a724f0f4 8696 return 0;
4a1805b1 8697
a724f0f4
JB		 8698 /* e11 [ expr ] */
8699 case '[':
a724f0f4 8700 return intel_bracket_expr ();
64a0c779 8701
a724f0f4
JB		 8702 /* e11 $
8703 | . */
8704 case '.':
64a0c779
DN		 8705 strcat (intel_parser.disp, cur_token.str);
8706 intel_match_token (cur_token.code);
21d6c4af
DN		 8707
8708 /* Mark as a memory operand only if it's not already known to be an
8709 offset expression. */
a724f0f4 8710 if (!intel_parser.in_offset)
21d6c4af 8711 intel_parser.is_mem = 1;
64a0c779
DN		 8712
8713 return 1;
64a0c779 8714
a724f0f4
JB		 8715 /* e11 register */
8716 case T_REG:
8717 {
8718 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 8719
a724f0f4 8720 intel_match_token (T_REG);
64a0c779 8721
a724f0f4
JB		 8722 /* Check for segment change. */
8723 if (cur_token.code == ':')
8724 {
40fb9820
L		 8725 if (!reg->reg_type.bitfield.sreg2
8726 && !reg->reg_type.bitfield.sreg3)
a724f0f4 8727 {
4eed87de
AM		 8728 as_bad (_("`%s' is not a valid segment register"),
8729 reg->reg_name);
a724f0f4
JB		 8730 return 0;
8731 }
b7240065
JB		 8732 else if (i.mem_operands >= 2)
8733 as_warn (_("Segment override ignored"));
a724f0f4
JB		 8734 else if (i.seg[i.mem_operands])
8735 as_warn (_("Extra segment override ignored"));
8736 else
8737 {
8738 if (!intel_parser.in_offset)
8739 intel_parser.is_mem = 1;
8740 switch (reg->reg_num)
8741 {
8742 case 0:
8743 i.seg[i.mem_operands] = &es;
8744 break;
8745 case 1:
8746 i.seg[i.mem_operands] = &cs;
8747 break;
8748 case 2:
8749 i.seg[i.mem_operands] = &ss;
8750 break;
8751 case 3:
8752 i.seg[i.mem_operands] = &ds;
8753 break;
8754 case 4:
8755 i.seg[i.mem_operands] = &fs;
8756 break;
8757 case 5:
8758 i.seg[i.mem_operands] = &gs;
8759 break;
8760 }
8761 }
8762 }
64a0c779 8763
b7240065
JB		 8764 else if (reg->reg_type.bitfield.sreg3 && reg->reg_num == RegFlat)
8765 {
8766 as_bad (_("cannot use `FLAT' here"));
8767 return 0;
8768 }
8769
a724f0f4
JB		 8770 /* Not a segment register. Check for register scaling. */
8771 else if (cur_token.code == '*')
8772 {
8773 if (!intel_parser.in_bracket)
8774 {
8775 as_bad (_("Register scaling only allowed in memory operands"));
8776 return 0;
8777 }
64a0c779 8778
40fb9820 8779 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
a724f0f4
JB		 8780 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
8781 else if (i.index_reg)
8782 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 8783
a724f0f4
JB		 8784 /* What follows must be a valid scale. */
8785 intel_match_token ('*');
8786 i.index_reg = reg;
40fb9820 8787 i.types[this_operand].bitfield.baseindex = 1;
64a0c779 8788
a724f0f4
JB		 8789 /* Set the scale after setting the register (otherwise,
8790 i386_scale will complain) */
8791 if (cur_token.code == '+' || cur_token.code == '-')
8792 {
8793 char *str, sign = cur_token.code;
8794 intel_match_token (cur_token.code);
8795 if (cur_token.code != T_CONST)
8796 {
8797 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8798 cur_token.str);
8799 return 0;
8800 }
8801 str = (char *) xmalloc (strlen (cur_token.str) + 2);
8802 strcpy (str + 1, cur_token.str);
8803 *str = sign;
8804 if (!i386_scale (str))
8805 return 0;
8806 free (str);
8807 }
8808 else if (!i386_scale (cur_token.str))
64a0c779 8809 return 0;
a724f0f4
JB		 8810 intel_match_token (cur_token.code);
8811 }
64a0c779 8812
a724f0f4
JB		 8813 /* No scaling. If this is a memory operand, the register is either a
8814 base register (first occurrence) or an index register (second
8815 occurrence). */
7b0441f6 8816 else if (intel_parser.in_bracket)
a724f0f4 8817 {
64a0c779 8818
a724f0f4
JB		 8819 if (!i.base_reg)
8820 i.base_reg = reg;
8821 else if (!i.index_reg)
8822 i.index_reg = reg;
8823 else
8824 {
8825 as_bad (_("Too many register references in memory operand"));
8826 return 0;
8827 }
64a0c779 8828
40fb9820 8829 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4 8830 }
4a1805b1 8831
4d1bb795
JB		 8832 /* It's neither base nor index. */
8833 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4 8834 {
40fb9820
L		 8835 i386_operand_type temp = reg->reg_type;
8836 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8837 i.types[this_operand] = operand_type_or (i.types[this_operand],
8838 temp);
7d5e4556 8839 i.types[this_operand].bitfield.unspecified = 0;
a724f0f4
JB		 8840 i.op[this_operand].regs = reg;
8841 i.reg_operands++;
8842 }
8843 else
8844 {
8845 as_bad (_("Invalid use of register"));
8846 return 0;
8847 }
64a0c779 8848
a724f0f4
JB		 8849 /* Since registers are not part of the displacement string (except
8850 when we're parsing offset operands), we may need to remove any
8851 preceding '+' from the displacement string. */
8852 if (*intel_parser.disp != '\0'
8853 && !intel_parser.in_offset)
8854 {
8855 char *s = intel_parser.disp;
8856 s += strlen (s) - 1;
8857 if (*s == '+')
8858 *s = '\0';
8859 }
4a1805b1 8860
a724f0f4
JB		 8861 return 1;
8862 }
8863
8864 /* e11 BYTE
8865 | WORD
8866 | DWORD
8867 | FWORD
8868 | QWORD
8869 | TBYTE
8870 | OWORD
8871 | XMMWORD */
8872 case T_BYTE:
8873 case T_WORD:
8874 case T_DWORD:
8875 case T_FWORD:
8876 case T_QWORD:
8877 case T_TBYTE:
8878 case T_XMMWORD:
8879 intel_match_token (cur_token.code);
64a0c779 8880
a724f0f4
JB		 8881 if (cur_token.code == T_PTR)
8882 return 1;
8883
8884 /* It must have been an identifier. */
8885 intel_putback_token ();
8886 cur_token.code = T_ID;
8887 /* FALLTHRU */
8888
8889 /* e11 id
8890 | constant */
8891 case T_ID:
8892 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 8893 {
8894 symbolS *symbolP;
8895
a724f0f4
JB		 8896 /* The identifier represents a memory reference only if it's not
8897 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 8898 symbolP = symbol_find(cur_token.str);
8899 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8900 intel_parser.is_mem = 1;
8901 }
a724f0f4 8902 /* FALLTHRU */
64a0c779 8903
a724f0f4
JB		 8904 case T_CONST:
8905 case '-':
8906 case '+':
8907 {
8908 char *save_str, sign = 0;
64a0c779 8909
a724f0f4
JB		 8910 /* Allow constants that start with `+' or `-'. */
8911 if (cur_token.code == '-' || cur_token.code == '+')
8912 {
8913 sign = cur_token.code;
8914 intel_match_token (cur_token.code);
8915 if (cur_token.code != T_CONST)
8916 {
8917 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8918 cur_token.str);
8919 return 0;
8920 }
8921 }
64a0c779 8922
a724f0f4
JB		 8923 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8924 strcpy (save_str + !!sign, cur_token.str);
8925 if (sign)
8926 *save_str = sign;
64a0c779 8927
a724f0f4
JB		 8928 /* Get the next token to check for register scaling. */
8929 intel_match_token (cur_token.code);
64a0c779 8930
4eed87de
AM		 8931 /* Check if this constant is a scaling factor for an
8932 index register. */
a724f0f4
JB		 8933 if (cur_token.code == '*')
8934 {
8935 if (intel_match_token ('*') && cur_token.code == T_REG)
8936 {
8937 const reg_entry *reg = cur_token.reg;
8938
8939 if (!intel_parser.in_bracket)
8940 {
4eed87de
AM		 8941 as_bad (_("Register scaling only allowed "
8942 "in memory operands"));
a724f0f4
JB		 8943 return 0;
8944 }
8945
4eed87de
AM		 8946 /* Disallow things like [1*si].
8947 sp and esp are invalid as index. */
40fb9820 8948 if (reg->reg_type.bitfield.reg16)
4eed87de 8949 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 8950 else if (i.index_reg)
4eed87de 8951 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 8952
8953 /* The constant is followed by `* reg', so it must be
8954 a valid scale. */
8955 i.index_reg = reg;
40fb9820 8956 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4
JB		 8957
8958 /* Set the scale after setting the register (otherwise,
8959 i386_scale will complain) */
8960 if (!i386_scale (save_str))
64a0c779 8961 return 0;
a724f0f4
JB		 8962 intel_match_token (T_REG);
8963
8964 /* Since registers are not part of the displacement
8965 string, we may need to remove any preceding '+' from
8966 the displacement string. */
8967 if (*intel_parser.disp != '\0')
8968 {
8969 char *s = intel_parser.disp;
8970 s += strlen (s) - 1;
8971 if (*s == '+')
8972 *s = '\0';
8973 }
8974
8975 free (save_str);
8976
8977 return 1;
8978 }
64a0c779 8979
a724f0f4
JB		 8980 /* The constant was not used for register scaling. Since we have
8981 already consumed the token following `*' we now need to put it
8982 back in the stream. */
64a0c779 8983 intel_putback_token ();
a724f0f4 8984 }
64a0c779 8985
a724f0f4
JB		 8986 /* Add the constant to the displacement string. */
8987 strcat (intel_parser.disp, save_str);
8988 free (save_str);
64a0c779 8989
a724f0f4
JB		 8990 return 1;
8991 }
64a0c779
DN		 8992 }
8993
64a0c779
DN		 8994 as_bad (_("Unrecognized token '%s'"), cur_token.str);
8995 return 0;
8996}
8997
64a0c779
DN		 8998/* Match the given token against cur_token. If they match, read the next
8999 token from the operand string. */
9000static int
e3bb37b5 9001intel_match_token (int code)
64a0c779
DN		 9002{
9003 if (cur_token.code == code)
9004 {
9005 intel_get_token ();
9006 return 1;
9007 }
9008 else
9009 {
0477af35 9010 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 9011 return 0;
9012 }
9013}
9014
64a0c779
DN		 9015/* Read a new token from intel_parser.op_string and store it in cur_token. */
9016static void
e3bb37b5 9017intel_get_token (void)
64a0c779
DN		 9018{
9019 char *end_op;
9020 const reg_entry *reg;
9021 struct intel_token new_token;
9022
9023 new_token.code = T_NIL;
9024 new_token.reg = NULL;
9025 new_token.str = NULL;
9026
4a1805b1 9027 /* Free the memory allocated to the previous token and move
64a0c779
DN		 9028 cur_token to prev_token. */
9029 if (prev_token.str)
9030 free (prev_token.str);
9031
9032 prev_token = cur_token;
9033
9034 /* Skip whitespace. */
9035 while (is_space_char (*intel_parser.op_string))
9036 intel_parser.op_string++;
9037
9038 /* Return an empty token if we find nothing else on the line. */
9039 if (*intel_parser.op_string == '\0')
9040 {
9041 cur_token = new_token;
9042 return;
9043 }
9044
9045 /* The new token cannot be larger than the remainder of the operand
9046 string. */
a724f0f4 9047 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 9048 new_token.str[0] = '\0';
9049
9050 if (strchr ("0123456789", *intel_parser.op_string))
9051 {
9052 char *p = new_token.str;
9053 char *q = intel_parser.op_string;
9054 new_token.code = T_CONST;
9055
9056 /* Allow any kind of identifier char to encompass floating point and
9057 hexadecimal numbers. */
9058 while (is_identifier_char (*q))
9059 *p++ = *q++;
9060 *p = '\0';
9061
9062 /* Recognize special symbol names [0-9][bf]. */
9063 if (strlen (intel_parser.op_string) == 2
4a1805b1 9064 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 9065 || intel_parser.op_string[1] == 'f'))
9066 new_token.code = T_ID;
9067 }
9068
4d1bb795 9069 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 9070 {
4d1bb795
JB		 9071 size_t len = end_op - intel_parser.op_string;
9072
64a0c779
DN		 9073 new_token.code = T_REG;
9074 new_token.reg = reg;
9075
4d1bb795
JB		 9076 memcpy (new_token.str, intel_parser.op_string, len);
9077 new_token.str[len] = '\0';
64a0c779
DN		 9078 }
9079
9080 else if (is_identifier_char (*intel_parser.op_string))
9081 {
9082 char *p = new_token.str;
9083 char *q = intel_parser.op_string;
9084
9085 /* A '.' or '$' followed by an identifier char is an identifier.
9086 Otherwise, it's operator '.' followed by an expression. */
9087 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
9088 {
9306ca4a
JB		 9089 new_token.code = '.';
9090 new_token.str[0] = '.';
64a0c779
DN		 9091 new_token.str[1] = '\0';
9092 }
9093 else
9094 {
9095 while (is_identifier_char (*q) || *q == '@')
9096 *p++ = *q++;
9097 *p = '\0';
9098
9306ca4a
JB		 9099 if (strcasecmp (new_token.str, "NOT") == 0)
9100 new_token.code = '~';
9101
9102 else if (strcasecmp (new_token.str, "MOD") == 0)
9103 new_token.code = '%';
9104
9105 else if (strcasecmp (new_token.str, "AND") == 0)
9106 new_token.code = '&';
9107
9108 else if (strcasecmp (new_token.str, "OR") == 0)
9109 new_token.code = '|';
9110
9111 else if (strcasecmp (new_token.str, "XOR") == 0)
9112 new_token.code = '^';
9113
9114 else if (strcasecmp (new_token.str, "SHL") == 0)
9115 new_token.code = T_SHL;
9116
9117 else if (strcasecmp (new_token.str, "SHR") == 0)
9118 new_token.code = T_SHR;
9119
9120 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 9121 new_token.code = T_BYTE;
9122
9123 else if (strcasecmp (new_token.str, "WORD") == 0)
9124 new_token.code = T_WORD;
9125
9126 else if (strcasecmp (new_token.str, "DWORD") == 0)
9127 new_token.code = T_DWORD;
9128
9306ca4a
JB		 9129 else if (strcasecmp (new_token.str, "FWORD") == 0)
9130 new_token.code = T_FWORD;
9131
64a0c779
DN		 9132 else if (strcasecmp (new_token.str, "QWORD") == 0)
9133 new_token.code = T_QWORD;
9134
9306ca4a
JB		 9135 else if (strcasecmp (new_token.str, "TBYTE") == 0
9136 /* XXX remove (gcc still uses it) */
9137 || strcasecmp (new_token.str, "XWORD") == 0)
9138 new_token.code = T_TBYTE;
9139
9140 else if (strcasecmp (new_token.str, "XMMWORD") == 0
9141 || strcasecmp (new_token.str, "OWORD") == 0)
9142 new_token.code = T_XMMWORD;
64a0c779
DN		 9143
9144 else if (strcasecmp (new_token.str, "PTR") == 0)
9145 new_token.code = T_PTR;
9146
9147 else if (strcasecmp (new_token.str, "SHORT") == 0)
9148 new_token.code = T_SHORT;
9149
9150 else if (strcasecmp (new_token.str, "OFFSET") == 0)
9151 {
9152 new_token.code = T_OFFSET;
9153
9154 /* ??? This is not mentioned in the MASM grammar but gcc
9155 makes use of it with -mintel-syntax. OFFSET may be
9156 followed by FLAT: */
9157 if (strncasecmp (q, " FLAT:", 6) == 0)
9158 strcat (new_token.str, " FLAT:");
9159 }
9160
64a0c779
DN		 9161 else
9162 new_token.code = T_ID;
9163 }
9164 }
9165
9306ca4a
JB		 9166 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
9167 {
9168 new_token.code = *intel_parser.op_string;
9169 new_token.str[0] = *intel_parser.op_string;
9170 new_token.str[1] = '\0';
9171 }
9172
9173 else if (strchr ("<>", *intel_parser.op_string)
9174 && *intel_parser.op_string == *(intel_parser.op_string + 1))
9175 {
9176 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
9177 new_token.str[0] = *intel_parser.op_string;
9178 new_token.str[1] = *intel_parser.op_string;
9179 new_token.str[2] = '\0';
9180 }
9181
64a0c779 9182 else
0477af35 9183 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 9184
9185 intel_parser.op_string += strlen (new_token.str);
9186 cur_token = new_token;
9187}
9188
64a0c779
DN		 9189/* Put cur_token back into the token stream and make cur_token point to
9190 prev_token. */
9191static void
e3bb37b5 9192intel_putback_token (void)
64a0c779 9193{
a724f0f4
JB		 9194 if (cur_token.code != T_NIL)
9195 {
9196 intel_parser.op_string -= strlen (cur_token.str);
9197 free (cur_token.str);
9198 }
64a0c779 9199 cur_token = prev_token;
4a1805b1 9200
64a0c779
DN		 9201 /* Forget prev_token. */
9202 prev_token.code = T_NIL;
9203 prev_token.reg = NULL;
9204 prev_token.str = NULL;
9205}
54cfded0 9206
a60de03c
JB		 9207void
9208tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 9209{
a60de03c
JB		 9210 int saved_naked_reg;
9211 char saved_register_dot;
54cfded0 9212
a60de03c
JB		 9213 saved_naked_reg = allow_naked_reg;
9214 allow_naked_reg = 1;
9215 saved_register_dot = register_chars['.'];
9216 register_chars['.'] = '.';
9217 allow_pseudo_reg = 1;
9218 expression_and_evaluate (exp);
9219 allow_pseudo_reg = 0;
9220 register_chars['.'] = saved_register_dot;
9221 allow_naked_reg = saved_naked_reg;
9222
9223 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 9224 {
a60de03c
JB		 9225 if ((addressT) exp->X_add_number < i386_regtab_size)
9226 {
9227 exp->X_op = O_constant;
9228 exp->X_add_number = i386_regtab[exp->X_add_number]
9229 .dw2_regnum[flag_code >> 1];
9230 }
9231 else
9232 exp->X_op = O_illegal;
54cfded0 9233 }
54cfded0
AM		 9234}
9235
9236void
9237tc_x86_frame_initial_instructions (void)
9238{
a60de03c
JB		 9239 static unsigned int sp_regno[2];
9240
9241 if (!sp_regno[flag_code >> 1])
9242 {
9243 char *saved_input = input_line_pointer;
9244 char sp[][4] = {"esp", "rsp"};
9245 expressionS exp;
a4447b93 9246
a60de03c
JB		 9247 input_line_pointer = sp[flag_code >> 1];
9248 tc_x86_parse_to_dw2regnum (&exp);
9249 assert (exp.X_op == O_constant);
9250 sp_regno[flag_code >> 1] = exp.X_add_number;
9251 input_line_pointer = saved_input;
9252 }
a4447b93 9253
a60de03c 9254 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 9255 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 9256}
d2b2c203
DJ		 9257
9258int
9259i386_elf_section_type (const char *str, size_t len)
9260{
9261 if (flag_code == CODE_64BIT
9262 && len == sizeof ("unwind") - 1
9263 && strncmp (str, "unwind", 6) == 0)
9264 return SHT_X86_64_UNWIND;
9265
9266 return -1;
9267}
bb41ade5
AM		 9268
9269#ifdef TE_PE
9270void
9271tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
9272{
9273 expressionS expr;
9274
9275 expr.X_op = O_secrel;
9276 expr.X_add_symbol = symbol;
9277 expr.X_add_number = 0;
9278 emit_expr (&expr, size);
9279}
9280#endif
3b22753a
L		 9281
9282#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9283/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9284
9285int
9286x86_64_section_letter (int letter, char **ptr_msg)
9287{
9288 if (flag_code == CODE_64BIT)
9289 {
9290 if (letter == 'l')
9291 return SHF_X86_64_LARGE;
9292
9293 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 9294 }
3b22753a 9295 else
64e74474 9296 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 9297 return -1;
9298}
9299
9300int
9301x86_64_section_word (char *str, size_t len)
9302{
8620418b 9303 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 9304 return SHF_X86_64_LARGE;
9305
9306 return -1;
9307}
9308
9309static void
9310handle_large_common (int small ATTRIBUTE_UNUSED)
9311{
9312 if (flag_code != CODE_64BIT)
9313 {
9314 s_comm_internal (0, elf_common_parse);
9315 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9316 }
9317 else
9318 {
9319 static segT lbss_section;
9320 asection *saved_com_section_ptr = elf_com_section_ptr;
9321 asection *saved_bss_section = bss_section;
9322
9323 if (lbss_section == NULL)
9324 {
9325 flagword applicable;
9326 segT seg = now_seg;
9327 subsegT subseg = now_subseg;
9328
9329 /* The .lbss section is for local .largecomm symbols. */
9330 lbss_section = subseg_new (".lbss", 0);
9331 applicable = bfd_applicable_section_flags (stdoutput);
9332 bfd_set_section_flags (stdoutput, lbss_section,
9333 applicable & SEC_ALLOC);
9334 seg_info (lbss_section)->bss = 1;
9335
9336 subseg_set (seg, subseg);
9337 }
9338
9339 elf_com_section_ptr = &_bfd_elf_large_com_section;
9340 bss_section = lbss_section;
9341
9342 s_comm_internal (0, elf_common_parse);
9343
9344 elf_com_section_ptr = saved_com_section_ptr;
9345 bss_section = saved_bss_section;
9346 }
9347}
9348#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
This page took 1.06009 seconds and 4 git commands to generate.