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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4dc85607 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
e3bb37b5
L		 58static void set_code_flag (int);
59static void set_16bit_gcc_code_flag (int);
60static void set_intel_syntax (int);
db51cc60 61static void set_allow_index_reg (int);
e3bb37b5 62static void set_cpu_arch (int);
6482c264 63#ifdef TE_PE
e3bb37b5 64static void pe_directive_secrel (int);
6482c264 65#endif
e3bb37b5
L		 66static void signed_cons (int);
67static char *output_invalid (int c);
68static int i386_operand (char *);
69static int i386_intel_operand (char *, int);
70static const reg_entry *parse_register (char *, char **);
71static char *parse_insn (char *, char *);
72static char *parse_operands (char *, const char *);
73static void swap_operands (void);
4d456e3d 74static void swap_2_operands (int, int);
e3bb37b5
L		 75static void optimize_imm (void);
76static void optimize_disp (void);
77static int match_template (void);
78static int check_string (void);
79static int process_suffix (void);
80static int check_byte_reg (void);
81static int check_long_reg (void);
82static int check_qword_reg (void);
83static int check_word_reg (void);
84static int finalize_imm (void);
85f10a01 85static void process_drex (void);
e3bb37b5
L		 86static int process_operands (void);
87static const seg_entry *build_modrm_byte (void);
88static void output_insn (void);
89static void output_imm (fragS *, offsetT);
90static void output_disp (fragS *, offsetT);
29b0f896 91#ifndef I386COFF
e3bb37b5 92static void s_bss (int);
252b5132 93#endif
17d4e2a2
L		 94#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
95static void handle_large_common (int small ATTRIBUTE_UNUSED);
96#endif
252b5132 97
a847613f 98static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 99
252b5132 100/* 'md_assemble ()' gathers together information and puts it into a
47926f60 101 i386_insn. */
252b5132 102
520dc8e8
AM		 103union i386_op
104 {
105 expressionS *disps;
106 expressionS *imms;
107 const reg_entry *regs;
108 };
109
252b5132
RH		 110struct _i386_insn
111 {
47926f60 112 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 113 template tm;
114
115 /* SUFFIX holds the instruction mnemonic suffix if given.
116 (e.g. 'l' for 'movl') */
117 char suffix;
118
47926f60 119 /* OPERANDS gives the number of given operands. */
252b5132
RH		 120 unsigned int operands;
121
122 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
123 of given register, displacement, memory operands and immediate
47926f60 124 operands. */
252b5132
RH		 125 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
126
127 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 128 use OP[i] for the corresponding operand. */
40fb9820 129 i386_operand_type types[MAX_OPERANDS];
252b5132 130
520dc8e8
AM		 131 /* Displacement expression, immediate expression, or register for each
132 operand. */
133 union i386_op op[MAX_OPERANDS];
252b5132 134
3e73aa7c
JH		 135 /* Flags for operands. */
136 unsigned int flags[MAX_OPERANDS];
137#define Operand_PCrel 1
138
252b5132 139 /* Relocation type for operand */
f86103b7 140 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 141
252b5132
RH		 142 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
143 the base index byte below. */
144 const reg_entry *base_reg;
145 const reg_entry *index_reg;
146 unsigned int log2_scale_factor;
147
148 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 149 explicit segment overrides are given. */
ce8a8b2f 150 const seg_entry *seg[2];
252b5132
RH		 151
152 /* PREFIX holds all the given prefix opcodes (usually null).
153 PREFIXES is the number of prefix opcodes. */
154 unsigned int prefixes;
155 unsigned char prefix[MAX_PREFIXES];
156
157 /* RM and SIB are the modrm byte and the sib byte where the
85f10a01
MM		 158 addressing modes of this insn are encoded. DREX is the byte
159 added by the SSE5 instructions. */
252b5132
RH		 160
161 modrm_byte rm;
3e73aa7c 162 rex_byte rex;
252b5132 163 sib_byte sib;
85f10a01 164 drex_byte drex;
252b5132
RH		 165 };
166
167typedef struct _i386_insn i386_insn;
168
169/* List of chars besides those in app.c:symbol_chars that can start an
170 operand. Used to prevent the scrubber eating vital white-space. */
32137342 171const char extra_symbol_chars[] = "*%-(["
252b5132 172#ifdef LEX_AT
32137342
NC		 173 "@"
174#endif
175#ifdef LEX_QM
176 "?"
252b5132 177#endif
32137342 178 ;
252b5132 179
29b0f896
AM		 180#if (defined (TE_I386AIX) \
181 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 182 && !defined (TE_GNU) \
29b0f896 183 && !defined (TE_LINUX) \
32137342 184 && !defined (TE_NETWARE) \
29b0f896
AM		 185 && !defined (TE_FreeBSD) \
186 && !defined (TE_NetBSD)))
252b5132 187/* This array holds the chars that always start a comment. If the
b3b91714
AM		 188 pre-processor is disabled, these aren't very useful. The option
189 --divide will remove '/' from this list. */
190const char *i386_comment_chars = "#/";
191#define SVR4_COMMENT_CHARS 1
252b5132 192#define PREFIX_SEPARATOR '\\'
252b5132 193
b3b91714
AM		 194#else
195const char *i386_comment_chars = "#";
196#define PREFIX_SEPARATOR '/'
197#endif
198
252b5132
RH		 199/* This array holds the chars that only start a comment at the beginning of
200 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 201 .line and .file directives will appear in the pre-processed output.
202 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 203 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 204 #NO_APP at the beginning of its output.
205 Also note that comments started like this one will always work if
252b5132 206 '/' isn't otherwise defined. */
b3b91714 207const char line_comment_chars[] = "#/";
252b5132 208
63a0b638 209const char line_separator_chars[] = ";";
252b5132 210
ce8a8b2f
AM		 211/* Chars that can be used to separate mant from exp in floating point
212 nums. */
252b5132
RH		 213const char EXP_CHARS[] = "eE";
214
ce8a8b2f
AM		 215/* Chars that mean this number is a floating point constant
216 As in 0f12.456
217 or 0d1.2345e12. */
252b5132
RH		 218const char FLT_CHARS[] = "fFdDxX";
219
ce8a8b2f 220/* Tables for lexical analysis. */
252b5132
RH		 221static char mnemonic_chars[256];
222static char register_chars[256];
223static char operand_chars[256];
224static char identifier_chars[256];
225static char digit_chars[256];
226
ce8a8b2f 227/* Lexical macros. */
252b5132
RH		 228#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
229#define is_operand_char(x) (operand_chars[(unsigned char) x])
230#define is_register_char(x) (register_chars[(unsigned char) x])
231#define is_space_char(x) ((x) == ' ')
232#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
233#define is_digit_char(x) (digit_chars[(unsigned char) x])
234
0234cb7c 235/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 236static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
237
238/* md_assemble() always leaves the strings it's passed unaltered. To
239 effect this we maintain a stack of saved characters that we've smashed
240 with '\0's (indicating end of strings for various sub-fields of the
47926f60 241 assembler instruction). */
252b5132 242static char save_stack[32];
ce8a8b2f 243static char *save_stack_p;
252b5132
RH		 244#define END_STRING_AND_SAVE(s) \
245 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
246#define RESTORE_END_STRING(s) \
247 do { *(s) = *--save_stack_p; } while (0)
248
47926f60 249/* The instruction we're assembling. */
252b5132
RH		 250static i386_insn i;
251
252/* Possible templates for current insn. */
253static const templates *current_templates;
254
31b2323c
L		 255/* Per instruction expressionS buffers: max displacements & immediates. */
256static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
257static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 258
47926f60
KH		 259/* Current operand we are working on. */
260static int this_operand;
252b5132 261
3e73aa7c
JH		 262/* We support four different modes. FLAG_CODE variable is used to distinguish
263 these. */
264
265enum flag_code {
266 CODE_32BIT,
267 CODE_16BIT,
268 CODE_64BIT };
f3c180ae 269#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 270
271static enum flag_code flag_code;
4fa24527 272static unsigned int object_64bit;
3e73aa7c
JH		 273static int use_rela_relocations = 0;
274
275/* The names used to print error messages. */
b77a7acd 276static const char *flag_code_names[] =
3e73aa7c
JH		 277 {
278 "32",
279 "16",
280 "64"
281 };
252b5132 282
47926f60
KH		 283/* 1 for intel syntax,
284 0 if att syntax. */
285static int intel_syntax = 0;
252b5132 286
47926f60
KH		 287/* 1 if register prefix % not required. */
288static int allow_naked_reg = 0;
252b5132 289
db51cc60
L		 290/* 1 if fake index register, eiz/riz, is allowed . */
291static int allow_index_reg = 0;
292
2ca3ace5
L		 293/* Register prefix used for error message. */
294static const char *register_prefix = "%";
295
47926f60
KH		 296/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
297 leave, push, and pop instructions so that gcc has the same stack
298 frame as in 32 bit mode. */
299static char stackop_size = '\0';
eecb386c 300
12b55ccc
L		 301/* Non-zero to optimize code alignment. */
302int optimize_align_code = 1;
303
47926f60
KH		 304/* Non-zero to quieten some warnings. */
305static int quiet_warnings = 0;
a38cf1db 306
47926f60
KH		 307/* CPU name. */
308static const char *cpu_arch_name = NULL;
5c6af06e 309static const char *cpu_sub_arch_name = NULL;
a38cf1db 310
47926f60 311/* CPU feature flags. */
40fb9820
L		 312static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
313
314/* Bitwise NOT of cpu_arch_flags. */
315static i386_cpu_flags cpu_arch_flags_not;
a38cf1db 316
ccc9c027
L		 317/* If we have selected a cpu we are generating instructions for. */
318static int cpu_arch_tune_set = 0;
319
9103f4f4
L		 320/* Cpu we are generating instructions for. */
321static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
322
323/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 324static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 325
ccc9c027
L		 326/* CPU instruction set architecture used. */
327static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
328
9103f4f4 329/* CPU feature flags of instruction set architecture used. */
40fb9820 330static i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 331
fddf5b5b
AM		 332/* If set, conditional jumps are not automatically promoted to handle
333 larger than a byte offset. */
334static unsigned int no_cond_jump_promotion = 0;
335
29b0f896 336/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 337static symbolS *GOT_symbol;
29b0f896 338
a4447b93
RH		 339/* The dwarf2 return column, adjusted for 32 or 64 bit. */
340unsigned int x86_dwarf2_return_column;
341
342/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
343int x86_cie_data_alignment;
344
252b5132 345/* Interface to relax_segment.
fddf5b5b
AM		 346 There are 3 major relax states for 386 jump insns because the
347 different types of jumps add different sizes to frags when we're
348 figuring out what sort of jump to choose to reach a given label. */
252b5132 349
47926f60 350/* Types. */
93c2a809
AM		 351#define UNCOND_JUMP 0
352#define COND_JUMP 1
353#define COND_JUMP86 2
fddf5b5b 354
47926f60 355/* Sizes. */
252b5132
RH		 356#define CODE16 1
357#define SMALL 0
29b0f896 358#define SMALL16 (SMALL | CODE16)
252b5132 359#define BIG 2
29b0f896 360#define BIG16 (BIG | CODE16)
252b5132
RH		 361
362#ifndef INLINE
363#ifdef __GNUC__
364#define INLINE __inline__
365#else
366#define INLINE
367#endif
368#endif
369
fddf5b5b
AM		 370#define ENCODE_RELAX_STATE(type, size) \
371 ((relax_substateT) (((type) << 2) | (size)))
372#define TYPE_FROM_RELAX_STATE(s) \
373 ((s) >> 2)
374#define DISP_SIZE_FROM_RELAX_STATE(s) \
375 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 376
377/* This table is used by relax_frag to promote short jumps to long
378 ones where necessary. SMALL (short) jumps may be promoted to BIG
379 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
380 don't allow a short jump in a 32 bit code segment to be promoted to
381 a 16 bit offset jump because it's slower (requires data size
382 prefix), and doesn't work, unless the destination is in the bottom
383 64k of the code segment (The top 16 bits of eip are zeroed). */
384
385const relax_typeS md_relax_table[] =
386{
24eab124
AM		 387 /* The fields are:
388 1) most positive reach of this state,
389 2) most negative reach of this state,
93c2a809 390 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 391 4) which index into the table to try if we can't fit into this one. */
252b5132 392
fddf5b5b 393 /* UNCOND_JUMP states. */
93c2a809
AM		 394 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
395 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
396 /* dword jmp adds 4 bytes to frag:
397 0 extra opcode bytes, 4 displacement bytes. */
252b5132 398 {0, 0, 4, 0},
93c2a809
AM		 399 /* word jmp adds 2 byte2 to frag:
400 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 401 {0, 0, 2, 0},
402
93c2a809
AM		 403 /* COND_JUMP states. */
404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
406 /* dword conditionals adds 5 bytes to frag:
407 1 extra opcode byte, 4 displacement bytes. */
408 {0, 0, 5, 0},
fddf5b5b 409 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 410 1 extra opcode byte, 2 displacement bytes. */
411 {0, 0, 3, 0},
412
413 /* COND_JUMP86 states. */
414 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
415 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
416 /* dword conditionals adds 5 bytes to frag:
417 1 extra opcode byte, 4 displacement bytes. */
418 {0, 0, 5, 0},
419 /* word conditionals add 4 bytes to frag:
420 1 displacement byte and a 3 byte long branch insn. */
421 {0, 0, 4, 0}
252b5132
RH		 422};
423
9103f4f4
L		 424static const arch_entry cpu_arch[] =
425{
426 {"generic32", PROCESSOR_GENERIC32,
40fb9820 427 CPU_GENERIC32_FLAGS },
9103f4f4 428 {"generic64", PROCESSOR_GENERIC64,
40fb9820 429 CPU_GENERIC64_FLAGS },
9103f4f4 430 {"i8086", PROCESSOR_UNKNOWN,
40fb9820 431 CPU_NONE_FLAGS },
9103f4f4 432 {"i186", PROCESSOR_UNKNOWN,
40fb9820 433 CPU_I186_FLAGS },
9103f4f4 434 {"i286", PROCESSOR_UNKNOWN,
40fb9820 435 CPU_I286_FLAGS },
76bc74dc 436 {"i386", PROCESSOR_I386,
40fb9820 437 CPU_I386_FLAGS },
9103f4f4 438 {"i486", PROCESSOR_I486,
40fb9820 439 CPU_I486_FLAGS },
9103f4f4 440 {"i586", PROCESSOR_PENTIUM,
40fb9820 441 CPU_I586_FLAGS },
9103f4f4 442 {"i686", PROCESSOR_PENTIUMPRO,
40fb9820 443 CPU_I686_FLAGS },
9103f4f4 444 {"pentium", PROCESSOR_PENTIUM,
40fb9820 445 CPU_I586_FLAGS },
9103f4f4 446 {"pentiumpro",PROCESSOR_PENTIUMPRO,
40fb9820 447 CPU_I686_FLAGS },
9103f4f4 448 {"pentiumii", PROCESSOR_PENTIUMPRO,
40fb9820 449 CPU_P2_FLAGS },
9103f4f4 450 {"pentiumiii",PROCESSOR_PENTIUMPRO,
40fb9820 451 CPU_P3_FLAGS },
9103f4f4 452 {"pentium4", PROCESSOR_PENTIUM4,
40fb9820 453 CPU_P4_FLAGS },
9103f4f4 454 {"prescott", PROCESSOR_NOCONA,
40fb9820 455 CPU_CORE_FLAGS },
9103f4f4 456 {"nocona", PROCESSOR_NOCONA,
40fb9820 457 CPU_NOCONA_FLAGS },
ef05d495 458 {"yonah", PROCESSOR_CORE,
40fb9820 459 CPU_CORE_FLAGS },
ef05d495 460 {"core", PROCESSOR_CORE,
40fb9820 461 CPU_CORE_FLAGS },
ef05d495 462 {"merom", PROCESSOR_CORE2,
40fb9820 463 CPU_CORE2_FLAGS },
ef05d495 464 {"core2", PROCESSOR_CORE2,
40fb9820 465 CPU_CORE2_FLAGS },
9103f4f4 466 {"k6", PROCESSOR_K6,
40fb9820 467 CPU_K6_FLAGS },
9103f4f4 468 {"k6_2", PROCESSOR_K6,
40fb9820 469 CPU_K6_2_FLAGS },
9103f4f4 470 {"athlon", PROCESSOR_ATHLON,
40fb9820 471 CPU_ATHLON_FLAGS },
9103f4f4 472 {"sledgehammer", PROCESSOR_K8,
40fb9820 473 CPU_K8_FLAGS },
9103f4f4 474 {"opteron", PROCESSOR_K8,
40fb9820 475 CPU_K8_FLAGS },
9103f4f4 476 {"k8", PROCESSOR_K8,
40fb9820 477 CPU_K8_FLAGS },
050dfa73 478 {"amdfam10", PROCESSOR_AMDFAM10,
40fb9820 479 CPU_AMDFAM10_FLAGS },
9103f4f4 480 {".mmx", PROCESSOR_UNKNOWN,
40fb9820 481 CPU_MMX_FLAGS },
9103f4f4 482 {".sse", PROCESSOR_UNKNOWN,
40fb9820 483 CPU_SSE_FLAGS },
9103f4f4 484 {".sse2", PROCESSOR_UNKNOWN,
40fb9820 485 CPU_SSE2_FLAGS },
9103f4f4 486 {".sse3", PROCESSOR_UNKNOWN,
40fb9820 487 CPU_SSE3_FLAGS },
ef05d495 488 {".ssse3", PROCESSOR_UNKNOWN,
40fb9820 489 CPU_SSSE3_FLAGS },
42903f7f 490 {".sse4.1", PROCESSOR_UNKNOWN,
40fb9820 491 CPU_SSE4_1_FLAGS },
381d071f 492 {".sse4.2", PROCESSOR_UNKNOWN,
40fb9820 493 CPU_SSE4_2_FLAGS },
381d071f 494 {".sse4", PROCESSOR_UNKNOWN,
40fb9820 495 CPU_SSE4_2_FLAGS },
9103f4f4 496 {".3dnow", PROCESSOR_UNKNOWN,
40fb9820 497 CPU_3DNOW_FLAGS },
9103f4f4 498 {".3dnowa", PROCESSOR_UNKNOWN,
40fb9820 499 CPU_3DNOWA_FLAGS },
9103f4f4 500 {".padlock", PROCESSOR_UNKNOWN,
40fb9820 501 CPU_PADLOCK_FLAGS },
9103f4f4 502 {".pacifica", PROCESSOR_UNKNOWN,
40fb9820 503 CPU_SVME_FLAGS },
9103f4f4 504 {".svme", PROCESSOR_UNKNOWN,
40fb9820 505 CPU_SVME_FLAGS },
050dfa73 506 {".sse4a", PROCESSOR_UNKNOWN,
40fb9820 507 CPU_SSE4A_FLAGS },
050dfa73 508 {".abm", PROCESSOR_UNKNOWN,
40fb9820 509 CPU_ABM_FLAGS },
85f10a01
MM		 510 {".sse5", PROCESSOR_UNKNOWN,
511 CPU_SSE5_FLAGS },
e413e4e9
AM		 512};
513
29b0f896
AM		 514const pseudo_typeS md_pseudo_table[] =
515{
516#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
517 {"align", s_align_bytes, 0},
518#else
519 {"align", s_align_ptwo, 0},
520#endif
521 {"arch", set_cpu_arch, 0},
522#ifndef I386COFF
523 {"bss", s_bss, 0},
524#endif
525 {"ffloat", float_cons, 'f'},
526 {"dfloat", float_cons, 'd'},
527 {"tfloat", float_cons, 'x'},
528 {"value", cons, 2},
d182319b 529 {"slong", signed_cons, 4},
29b0f896
AM		 530 {"noopt", s_ignore, 0},
531 {"optim", s_ignore, 0},
532 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
533 {"code16", set_code_flag, CODE_16BIT},
534 {"code32", set_code_flag, CODE_32BIT},
535 {"code64", set_code_flag, CODE_64BIT},
536 {"intel_syntax", set_intel_syntax, 1},
537 {"att_syntax", set_intel_syntax, 0},
db51cc60
L		 538 {"allow_index_reg", set_allow_index_reg, 1},
539 {"disallow_index_reg", set_allow_index_reg, 0},
3b22753a
L		 540#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
541 {"largecomm", handle_large_common, 0},
07a53e5c 542#else
e3bb37b5 543 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 544 {"loc", dwarf2_directive_loc, 0},
545 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 546#endif
6482c264
NC		 547#ifdef TE_PE
548 {"secrel32", pe_directive_secrel, 0},
549#endif
29b0f896
AM		 550 {0, 0, 0}
551};
552
553/* For interface with expression (). */
554extern char *input_line_pointer;
555
556/* Hash table for instruction mnemonic lookup. */
557static struct hash_control *op_hash;
558
559/* Hash table for register lookup. */
560static struct hash_control *reg_hash;
561\f
252b5132 562void
e3bb37b5 563i386_align_code (fragS *fragP, int count)
252b5132 564{
ce8a8b2f
AM		 565 /* Various efficient no-op patterns for aligning code labels.
566 Note: Don't try to assemble the instructions in the comments.
567 0L and 0w are not legal. */
252b5132
RH		 568 static const char f32_1[] =
569 {0x90}; /* nop */
570 static const char f32_2[] =
ccc9c027 571 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 572 static const char f32_3[] =
573 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
574 static const char f32_4[] =
575 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
576 static const char f32_5[] =
577 {0x90, /* nop */
578 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
579 static const char f32_6[] =
580 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
581 static const char f32_7[] =
582 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
583 static const char f32_8[] =
584 {0x90, /* nop */
585 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
586 static const char f32_9[] =
587 {0x89,0xf6, /* movl %esi,%esi */
588 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
589 static const char f32_10[] =
590 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
591 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
592 static const char f32_11[] =
593 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
594 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
595 static const char f32_12[] =
596 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
597 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
598 static const char f32_13[] =
599 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
600 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
601 static const char f32_14[] =
602 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
603 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 604 static const char f16_3[] =
605 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 606 static const char f16_4[] =
607 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
608 static const char f16_5[] =
609 {0x90, /* nop */
610 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
611 static const char f16_6[] =
612 {0x89,0xf6, /* mov %si,%si */
613 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
614 static const char f16_7[] =
615 {0x8d,0x74,0x00, /* lea 0(%si),%si */
616 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
617 static const char f16_8[] =
618 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
619 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 620 static const char jump_31[] =
621 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
622 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
623 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
624 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 625 static const char *const f32_patt[] = {
626 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 627 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 628 };
629 static const char *const f16_patt[] = {
76bc74dc 630 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 631 };
ccc9c027
L		 632 /* nopl (%[re]ax) */
633 static const char alt_3[] =
634 {0x0f,0x1f,0x00};
635 /* nopl 0(%[re]ax) */
636 static const char alt_4[] =
637 {0x0f,0x1f,0x40,0x00};
638 /* nopl 0(%[re]ax,%[re]ax,1) */
639 static const char alt_5[] =
640 {0x0f,0x1f,0x44,0x00,0x00};
641 /* nopw 0(%[re]ax,%[re]ax,1) */
642 static const char alt_6[] =
643 {0x66,0x0f,0x1f,0x44,0x00,0x00};
644 /* nopl 0L(%[re]ax) */
645 static const char alt_7[] =
646 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
647 /* nopl 0L(%[re]ax,%[re]ax,1) */
648 static const char alt_8[] =
649 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
650 /* nopw 0L(%[re]ax,%[re]ax,1) */
651 static const char alt_9[] =
652 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
653 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
654 static const char alt_10[] =
655 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
656 /* data16
657 nopw %cs:0L(%[re]ax,%[re]ax,1) */
658 static const char alt_long_11[] =
659 {0x66,
660 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
661 /* data16
662 data16
663 nopw %cs:0L(%[re]ax,%[re]ax,1) */
664 static const char alt_long_12[] =
665 {0x66,
666 0x66,
667 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
668 /* data16
669 data16
670 data16
671 nopw %cs:0L(%[re]ax,%[re]ax,1) */
672 static const char alt_long_13[] =
673 {0x66,
674 0x66,
675 0x66,
676 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
677 /* data16
678 data16
679 data16
680 data16
681 nopw %cs:0L(%[re]ax,%[re]ax,1) */
682 static const char alt_long_14[] =
683 {0x66,
684 0x66,
685 0x66,
686 0x66,
687 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
688 /* data16
689 data16
690 data16
691 data16
692 data16
693 nopw %cs:0L(%[re]ax,%[re]ax,1) */
694 static const char alt_long_15[] =
695 {0x66,
696 0x66,
697 0x66,
698 0x66,
699 0x66,
700 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
701 /* nopl 0(%[re]ax,%[re]ax,1)
702 nopw 0(%[re]ax,%[re]ax,1) */
703 static const char alt_short_11[] =
704 {0x0f,0x1f,0x44,0x00,0x00,
705 0x66,0x0f,0x1f,0x44,0x00,0x00};
706 /* nopw 0(%[re]ax,%[re]ax,1)
707 nopw 0(%[re]ax,%[re]ax,1) */
708 static const char alt_short_12[] =
709 {0x66,0x0f,0x1f,0x44,0x00,0x00,
710 0x66,0x0f,0x1f,0x44,0x00,0x00};
711 /* nopw 0(%[re]ax,%[re]ax,1)
712 nopl 0L(%[re]ax) */
713 static const char alt_short_13[] =
714 {0x66,0x0f,0x1f,0x44,0x00,0x00,
715 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
716 /* nopl 0L(%[re]ax)
717 nopl 0L(%[re]ax) */
718 static const char alt_short_14[] =
719 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
720 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
721 /* nopl 0L(%[re]ax)
722 nopl 0L(%[re]ax,%[re]ax,1) */
723 static const char alt_short_15[] =
724 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
725 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
726 static const char *const alt_short_patt[] = {
727 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
728 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
729 alt_short_14, alt_short_15
730 };
731 static const char *const alt_long_patt[] = {
732 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
733 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
734 alt_long_14, alt_long_15
735 };
252b5132 736
76bc74dc
L		 737 /* Only align for at least a positive non-zero boundary. */
738 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 739 return;
3e73aa7c 740
ccc9c027
L		 741 /* We need to decide which NOP sequence to use for 32bit and
742 64bit. When -mtune= is used:
4eed87de 743
76bc74dc
L		 744 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
745 PROCESSOR_GENERIC32, f32_patt will be used.
746 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
747 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
748 alt_long_patt will be used.
749 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
750 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 751
76bc74dc
L		 752 When -mtune= isn't used, alt_long_patt will be used if
753 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
754 be used.
ccc9c027
L		 755
756 When -march= or .arch is used, we can't use anything beyond
757 cpu_arch_isa_flags. */
758
759 if (flag_code == CODE_16BIT)
760 {
ccc9c027 761 if (count > 8)
33fef721 762 {
76bc74dc
L		 763 memcpy (fragP->fr_literal + fragP->fr_fix,
764 jump_31, count);
765 /* Adjust jump offset. */
766 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 767 }
76bc74dc
L		 768 else
769 memcpy (fragP->fr_literal + fragP->fr_fix,
770 f16_patt[count - 1], count);
252b5132 771 }
33fef721 772 else
ccc9c027
L		 773 {
774 const char *const *patt = NULL;
775
776 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
777 {
778 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
779 switch (cpu_arch_tune)
780 {
781 case PROCESSOR_UNKNOWN:
782 /* We use cpu_arch_isa_flags to check if we SHOULD
783 optimize for Cpu686. */
40fb9820 784 if (cpu_arch_isa_flags.bitfield.cpui686)
76bc74dc 785 patt = alt_long_patt;
ccc9c027
L		 786 else
787 patt = f32_patt;
788 break;
ccc9c027
L		 789 case PROCESSOR_PENTIUMPRO:
790 case PROCESSOR_PENTIUM4:
791 case PROCESSOR_NOCONA:
ef05d495 792 case PROCESSOR_CORE:
76bc74dc
L		 793 case PROCESSOR_CORE2:
794 case PROCESSOR_GENERIC64:
795 patt = alt_long_patt;
796 break;
ccc9c027
L		 797 case PROCESSOR_K6:
798 case PROCESSOR_ATHLON:
799 case PROCESSOR_K8:
4eed87de 800 case PROCESSOR_AMDFAM10:
ccc9c027
L		 801 patt = alt_short_patt;
802 break;
76bc74dc 803 case PROCESSOR_I386:
ccc9c027
L		 804 case PROCESSOR_I486:
805 case PROCESSOR_PENTIUM:
806 case PROCESSOR_GENERIC32:
807 patt = f32_patt;
808 break;
4eed87de 809 }
ccc9c027
L		 810 }
811 else
812 {
813 switch (cpu_arch_tune)
814 {
815 case PROCESSOR_UNKNOWN:
816 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
817 PROCESSOR_UNKNOWN. */
818 abort ();
819 break;
820
76bc74dc 821 case PROCESSOR_I386:
ccc9c027
L		 822 case PROCESSOR_I486:
823 case PROCESSOR_PENTIUM:
ccc9c027
L		 824 case PROCESSOR_K6:
825 case PROCESSOR_ATHLON:
826 case PROCESSOR_K8:
4eed87de 827 case PROCESSOR_AMDFAM10:
ccc9c027
L		 828 case PROCESSOR_GENERIC32:
829 /* We use cpu_arch_isa_flags to check if we CAN optimize
830 for Cpu686. */
40fb9820 831 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 832 patt = alt_short_patt;
833 else
834 patt = f32_patt;
835 break;
76bc74dc
L		 836 case PROCESSOR_PENTIUMPRO:
837 case PROCESSOR_PENTIUM4:
838 case PROCESSOR_NOCONA:
839 case PROCESSOR_CORE:
ef05d495 840 case PROCESSOR_CORE2:
40fb9820 841 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 842 patt = alt_long_patt;
843 else
844 patt = f32_patt;
845 break;
846 case PROCESSOR_GENERIC64:
76bc74dc 847 patt = alt_long_patt;
ccc9c027 848 break;
4eed87de 849 }
ccc9c027
L		 850 }
851
76bc74dc
L		 852 if (patt == f32_patt)
853 {
854 /* If the padding is less than 15 bytes, we use the normal
855 ones. Otherwise, we use a jump instruction and adjust
856 its offset. */
857 if (count < 15)
858 memcpy (fragP->fr_literal + fragP->fr_fix,
859 patt[count - 1], count);
860 else
861 {
862 memcpy (fragP->fr_literal + fragP->fr_fix,
863 jump_31, count);
864 /* Adjust jump offset. */
865 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
866 }
867 }
868 else
869 {
870 /* Maximum length of an instruction is 15 byte. If the
871 padding is greater than 15 bytes and we don't use jump,
872 we have to break it into smaller pieces. */
873 int padding = count;
874 while (padding > 15)
875 {
876 padding -= 15;
877 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
878 patt [14], 15);
879 }
880
881 if (padding)
882 memcpy (fragP->fr_literal + fragP->fr_fix,
883 patt [padding - 1], padding);
884 }
ccc9c027 885 }
33fef721 886 fragP->fr_var = count;
252b5132
RH		 887}
888
c6fb90c8
L		 889static INLINE int
890uints_all_zero (const unsigned int *x, unsigned int size)
40fb9820 891{
c6fb90c8
L		 892 switch (size)
893 {
894 case 3:
895 if (x[2])
896 return 0;
897 case 2:
898 if (x[1])
899 return 0;
900 case 1:
901 return !x[0];
902 default:
903 abort ();
904 }
40fb9820
L		 905}
906
c6fb90c8
L		 907static INLINE void
908uints_set (unsigned int *x, unsigned int v, unsigned int size)
40fb9820 909{
c6fb90c8
L		 910 switch (size)
911 {
912 case 3:
913 x[2] = v;
914 case 2:
915 x[1] = v;
916 case 1:
917 x[0] = v;
918 break;
919 default:
920 abort ();
921 }
922}
40fb9820 923
c6fb90c8
L		 924static INLINE int
925uints_equal (const unsigned int *x, const unsigned int *y,
926 unsigned int size)
927{
928 switch (size)
929 {
930 case 3:
931 if (x[2] != y [2])
932 return 0;
933 case 2:
934 if (x[1] != y [1])
935 return 0;
936 case 1:
937 return x[0] == y [0];
938 break;
939 default:
940 abort ();
941 }
942}
40fb9820 943
c6fb90c8
L		 944#define UINTS_ALL_ZERO(x) \
945 uints_all_zero ((x).array, ARRAY_SIZE ((x).array))
946#define UINTS_SET(x, v) \
947 uints_set ((x).array, v, ARRAY_SIZE ((x).array))
948#define UINTS_CLEAR(x) \
949 uints_set ((x).array, 0, ARRAY_SIZE ((x).array))
950#define UINTS_EQUAL(x, y) \
951 uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array))
952
953static INLINE int
954cpu_flags_check_cpu64 (i386_cpu_flags f)
955{
956 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
957 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 958}
959
c6fb90c8 960static INLINE i386_cpu_flags
40fb9820
L		 961cpu_flags_not (i386_cpu_flags x)
962{
c6fb90c8
L		 963 switch (ARRAY_SIZE (x.array))
964 {
965 case 3:
966 x.array [2] = ~x.array [2];
967 case 2:
968 x.array [1] = ~x.array [1];
969 case 1:
970 x.array [0] = ~x.array [0];
971 break;
972 default:
973 abort ();
974 }
40fb9820
L		 975
976#ifdef CpuUnused
977 x.bitfield.unused = 0;
978#endif
979
980 return x;
981}
982
c6fb90c8
L		 983static INLINE i386_cpu_flags
984cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 985{
c6fb90c8
L		 986 switch (ARRAY_SIZE (x.array))
987 {
988 case 3:
989 x.array [2] &= y.array [2];
990 case 2:
991 x.array [1] &= y.array [1];
992 case 1:
993 x.array [0] &= y.array [0];
994 break;
995 default:
996 abort ();
997 }
998 return x;
999}
40fb9820 1000
c6fb90c8
L		 1001static INLINE i386_cpu_flags
1002cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1003{
c6fb90c8 1004 switch (ARRAY_SIZE (x.array))
40fb9820 1005 {
c6fb90c8
L		 1006 case 3:
1007 x.array [2] |= y.array [2];
1008 case 2:
1009 x.array [1] |= y.array [1];
1010 case 1:
1011 x.array [0] |= y.array [0];
40fb9820
L		 1012 break;
1013 default:
1014 abort ();
1015 }
40fb9820
L		 1016 return x;
1017}
1018
1019static int
1020cpu_flags_match (i386_cpu_flags x)
1021{
1022 i386_cpu_flags not = cpu_arch_flags_not;
1023
1024 not.bitfield.cpu64 = 1;
1025 not.bitfield.cpuno64 = 1;
1026
1027 x.bitfield.cpu64 = 0;
1028 x.bitfield.cpuno64 = 0;
1029
c6fb90c8
L		 1030 not = cpu_flags_and (x, not);
1031 return UINTS_ALL_ZERO (not);
40fb9820
L		 1032}
1033
c6fb90c8
L		 1034static INLINE i386_operand_type
1035operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1036{
c6fb90c8
L		 1037 switch (ARRAY_SIZE (x.array))
1038 {
1039 case 3:
1040 x.array [2] &= y.array [2];
1041 case 2:
1042 x.array [1] &= y.array [1];
1043 case 1:
1044 x.array [0] &= y.array [0];
1045 break;
1046 default:
1047 abort ();
1048 }
1049 return x;
40fb9820
L		 1050}
1051
c6fb90c8
L		 1052static INLINE i386_operand_type
1053operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1054{
c6fb90c8 1055 switch (ARRAY_SIZE (x.array))
40fb9820 1056 {
c6fb90c8
L		 1057 case 3:
1058 x.array [2] |= y.array [2];
1059 case 2:
1060 x.array [1] |= y.array [1];
1061 case 1:
1062 x.array [0] |= y.array [0];
40fb9820
L		 1063 break;
1064 default:
1065 abort ();
1066 }
c6fb90c8
L		 1067 return x;
1068}
40fb9820 1069
c6fb90c8
L		 1070static INLINE i386_operand_type
1071operand_type_xor (i386_operand_type x, i386_operand_type y)
1072{
1073 switch (ARRAY_SIZE (x.array))
1074 {
1075 case 3:
1076 x.array [2] ^= y.array [2];
1077 case 2:
1078 x.array [1] ^= y.array [1];
1079 case 1:
1080 x.array [0] ^= y.array [0];
1081 break;
1082 default:
1083 abort ();
1084 }
40fb9820
L		 1085 return x;
1086}
1087
1088static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1089static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1090static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1091static const i386_operand_type reg16_inoutportreg
1092 = OPERAND_TYPE_REG16_INOUTPORTREG;
1093static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1094static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1095static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1096static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1097static const i386_operand_type anydisp
1098 = OPERAND_TYPE_ANYDISP;
40fb9820
L		 1099static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1100static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1101static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1102static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1103static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1104static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1105static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1106static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1107static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1108static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1109
1110enum operand_type
1111{
1112 reg,
40fb9820
L		 1113 imm,
1114 disp,
1115 anymem
1116};
1117
c6fb90c8 1118static INLINE int
40fb9820
L		 1119operand_type_check (i386_operand_type t, enum operand_type c)
1120{
1121 switch (c)
1122 {
1123 case reg:
1124 return (t.bitfield.reg8
1125 || t.bitfield.reg16
1126 || t.bitfield.reg32
1127 || t.bitfield.reg64);
1128
40fb9820
L		 1129 case imm:
1130 return (t.bitfield.imm8
1131 || t.bitfield.imm8s
1132 || t.bitfield.imm16
1133 || t.bitfield.imm32
1134 || t.bitfield.imm32s
1135 || t.bitfield.imm64);
1136
1137 case disp:
1138 return (t.bitfield.disp8
1139 || t.bitfield.disp16
1140 || t.bitfield.disp32
1141 || t.bitfield.disp32s
1142 || t.bitfield.disp64);
1143
1144 case anymem:
1145 return (t.bitfield.disp8
1146 || t.bitfield.disp16
1147 || t.bitfield.disp32
1148 || t.bitfield.disp32s
1149 || t.bitfield.disp64
1150 || t.bitfield.baseindex);
1151
1152 default:
1153 abort ();
1154 }
1155}
1156
c6fb90c8 1157static INLINE int
40fb9820
L		 1158operand_type_match (i386_operand_type overlap,
1159 i386_operand_type given)
1160{
1161 i386_operand_type temp = overlap;
1162
1163 temp.bitfield.jumpabsolute = 0;
c6fb90c8 1164 if (UINTS_ALL_ZERO (temp))
40fb9820
L		 1165 return 0;
1166
1167 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1168 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1169}
1170
1171/* If given types r0 and r1 are registers they must be of the same type
1172 unless the expected operand type register overlap is null.
1173 Note that Acc in a template matches every size of reg. */
1174
c6fb90c8 1175static INLINE int
40fb9820
L		 1176operand_type_register_match (i386_operand_type m0,
1177 i386_operand_type g0,
1178 i386_operand_type t0,
1179 i386_operand_type m1,
1180 i386_operand_type g1,
1181 i386_operand_type t1)
1182{
1183 if (!operand_type_check (g0, reg))
1184 return 1;
1185
1186 if (!operand_type_check (g1, reg))
1187 return 1;
1188
1189 if (g0.bitfield.reg8 == g1.bitfield.reg8
1190 && g0.bitfield.reg16 == g1.bitfield.reg16
1191 && g0.bitfield.reg32 == g1.bitfield.reg32
1192 && g0.bitfield.reg64 == g1.bitfield.reg64)
1193 return 1;
1194
1195 if (m0.bitfield.acc)
1196 {
1197 t0.bitfield.reg8 = 1;
1198 t0.bitfield.reg16 = 1;
1199 t0.bitfield.reg32 = 1;
1200 t0.bitfield.reg64 = 1;
1201 }
1202
1203 if (m1.bitfield.acc)
1204 {
1205 t1.bitfield.reg8 = 1;
1206 t1.bitfield.reg16 = 1;
1207 t1.bitfield.reg32 = 1;
1208 t1.bitfield.reg64 = 1;
1209 }
1210
1211 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1212 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1213 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1214 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1215}
1216
252b5132 1217static INLINE unsigned int
40fb9820 1218mode_from_disp_size (i386_operand_type t)
252b5132 1219{
40fb9820
L		 1220 if (t.bitfield.disp8)
1221 return 1;
1222 else if (t.bitfield.disp16
1223 || t.bitfield.disp32
1224 || t.bitfield.disp32s)
1225 return 2;
1226 else
1227 return 0;
252b5132
RH		 1228}
1229
1230static INLINE int
e3bb37b5 1231fits_in_signed_byte (offsetT num)
252b5132
RH		 1232{
1233 return (num >= -128) && (num <= 127);
47926f60 1234}
252b5132
RH		 1235
1236static INLINE int
e3bb37b5 1237fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1238{
1239 return (num & 0xff) == num;
47926f60 1240}
252b5132
RH		 1241
1242static INLINE int
e3bb37b5 1243fits_in_unsigned_word (offsetT num)
252b5132
RH		 1244{
1245 return (num & 0xffff) == num;
47926f60 1246}
252b5132
RH		 1247
1248static INLINE int
e3bb37b5 1249fits_in_signed_word (offsetT num)
252b5132
RH		 1250{
1251 return (-32768 <= num) && (num <= 32767);
47926f60 1252}
2a962e6d 1253
3e73aa7c 1254static INLINE int
e3bb37b5 1255fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1256{
1257#ifndef BFD64
1258 return 1;
1259#else
1260 return (!(((offsetT) -1 << 31) & num)
1261 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1262#endif
1263} /* fits_in_signed_long() */
2a962e6d 1264
3e73aa7c 1265static INLINE int
e3bb37b5 1266fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1267{
1268#ifndef BFD64
1269 return 1;
1270#else
1271 return (num & (((offsetT) 2 << 31) - 1)) == num;
1272#endif
1273} /* fits_in_unsigned_long() */
252b5132 1274
40fb9820 1275static i386_operand_type
e3bb37b5 1276smallest_imm_type (offsetT num)
252b5132 1277{
40fb9820
L		 1278 i386_operand_type t;
1279
c6fb90c8 1280 UINTS_CLEAR (t);
40fb9820
L		 1281 t.bitfield.imm64 = 1;
1282
1283 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1284 {
1285 /* This code is disabled on the 486 because all the Imm1 forms
1286 in the opcode table are slower on the i486. They're the
1287 versions with the implicitly specified single-position
1288 displacement, which has another syntax if you really want to
1289 use that form. */
40fb9820
L		 1290 t.bitfield.imm1 = 1;
1291 t.bitfield.imm8 = 1;
1292 t.bitfield.imm8s = 1;
1293 t.bitfield.imm16 = 1;
1294 t.bitfield.imm32 = 1;
1295 t.bitfield.imm32s = 1;
1296 }
1297 else if (fits_in_signed_byte (num))
1298 {
1299 t.bitfield.imm8 = 1;
1300 t.bitfield.imm8s = 1;
1301 t.bitfield.imm16 = 1;
1302 t.bitfield.imm32 = 1;
1303 t.bitfield.imm32s = 1;
1304 }
1305 else if (fits_in_unsigned_byte (num))
1306 {
1307 t.bitfield.imm8 = 1;
1308 t.bitfield.imm16 = 1;
1309 t.bitfield.imm32 = 1;
1310 t.bitfield.imm32s = 1;
1311 }
1312 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1313 {
1314 t.bitfield.imm16 = 1;
1315 t.bitfield.imm32 = 1;
1316 t.bitfield.imm32s = 1;
1317 }
1318 else if (fits_in_signed_long (num))
1319 {
1320 t.bitfield.imm32 = 1;
1321 t.bitfield.imm32s = 1;
1322 }
1323 else if (fits_in_unsigned_long (num))
1324 t.bitfield.imm32 = 1;
1325
1326 return t;
47926f60 1327}
252b5132 1328
847f7ad4 1329static offsetT
e3bb37b5 1330offset_in_range (offsetT val, int size)
847f7ad4 1331{
508866be 1332 addressT mask;
ba2adb93 1333
847f7ad4
AM		 1334 switch (size)
1335 {
508866be
L		 1336 case 1: mask = ((addressT) 1 << 8) - 1; break;
1337 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1338 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1339#ifdef BFD64
1340 case 8: mask = ((addressT) 2 << 63) - 1; break;
1341#endif
47926f60 1342 default: abort ();
847f7ad4
AM		 1343 }
1344
ba2adb93 1345 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1346 if (!use_rela_relocations)
1347 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1348 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1349
47926f60 1350 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1351 {
1352 char buf1[40], buf2[40];
1353
1354 sprint_value (buf1, val);
1355 sprint_value (buf2, val & mask);
1356 as_warn (_("%s shortened to %s"), buf1, buf2);
1357 }
1358 return val & mask;
1359}
1360
252b5132
RH		 1361/* Returns 0 if attempting to add a prefix where one from the same
1362 class already exists, 1 if non rep/repne added, 2 if rep/repne
1363 added. */
1364static int
e3bb37b5 1365add_prefix (unsigned int prefix)
252b5132
RH		 1366{
1367 int ret = 1;
b1905489 1368 unsigned int q;
252b5132 1369
29b0f896
AM		 1370 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1371 && flag_code == CODE_64BIT)
b1905489 1372 {
161a04f6
L		 1373 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1374 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1375 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1376 ret = 0;
1377 q = REX_PREFIX;
1378 }
3e73aa7c 1379 else
b1905489
JB		 1380 {
1381 switch (prefix)
1382 {
1383 default:
1384 abort ();
1385
1386 case CS_PREFIX_OPCODE:
1387 case DS_PREFIX_OPCODE:
1388 case ES_PREFIX_OPCODE:
1389 case FS_PREFIX_OPCODE:
1390 case GS_PREFIX_OPCODE:
1391 case SS_PREFIX_OPCODE:
1392 q = SEG_PREFIX;
1393 break;
1394
1395 case REPNE_PREFIX_OPCODE:
1396 case REPE_PREFIX_OPCODE:
1397 ret = 2;
1398 /* fall thru */
1399 case LOCK_PREFIX_OPCODE:
1400 q = LOCKREP_PREFIX;
1401 break;
1402
1403 case FWAIT_OPCODE:
1404 q = WAIT_PREFIX;
1405 break;
1406
1407 case ADDR_PREFIX_OPCODE:
1408 q = ADDR_PREFIX;
1409 break;
1410
1411 case DATA_PREFIX_OPCODE:
1412 q = DATA_PREFIX;
1413 break;
1414 }
1415 if (i.prefix[q] != 0)
1416 ret = 0;
1417 }
252b5132 1418
b1905489 1419 if (ret)
252b5132 1420 {
b1905489
JB		 1421 if (!i.prefix[q])
1422 ++i.prefixes;
1423 i.prefix[q] |= prefix;
252b5132 1424 }
b1905489
JB		 1425 else
1426 as_bad (_("same type of prefix used twice"));
252b5132 1427
252b5132
RH		 1428 return ret;
1429}
1430
1431static void
e3bb37b5 1432set_code_flag (int value)
eecb386c 1433{
3e73aa7c 1434 flag_code = value;
40fb9820
L		 1435 if (flag_code == CODE_64BIT)
1436 {
1437 cpu_arch_flags.bitfield.cpu64 = 1;
1438 cpu_arch_flags.bitfield.cpuno64 = 0;
1439 cpu_arch_flags_not.bitfield.cpu64 = 0;
1440 cpu_arch_flags_not.bitfield.cpuno64 = 1;
1441 }
1442 else
1443 {
1444 cpu_arch_flags.bitfield.cpu64 = 0;
1445 cpu_arch_flags.bitfield.cpuno64 = 1;
1446 cpu_arch_flags_not.bitfield.cpu64 = 1;
1447 cpu_arch_flags_not.bitfield.cpuno64 = 0;
1448 }
1449 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1450 {
1451 as_bad (_("64bit mode not supported on this CPU."));
1452 }
40fb9820 1453 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1454 {
1455 as_bad (_("32bit mode not supported on this CPU."));
1456 }
eecb386c
AM		 1457 stackop_size = '\0';
1458}
1459
1460static void
e3bb37b5 1461set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1462{
3e73aa7c 1463 flag_code = new_code_flag;
40fb9820
L		 1464 if (flag_code != CODE_16BIT)
1465 abort ();
1466 cpu_arch_flags.bitfield.cpu64 = 0;
1467 cpu_arch_flags.bitfield.cpuno64 = 1;
1468 cpu_arch_flags_not.bitfield.cpu64 = 1;
1469 cpu_arch_flags_not.bitfield.cpuno64 = 0;
9306ca4a 1470 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1471}
1472
1473static void
e3bb37b5 1474set_intel_syntax (int syntax_flag)
252b5132
RH		 1475{
1476 /* Find out if register prefixing is specified. */
1477 int ask_naked_reg = 0;
1478
1479 SKIP_WHITESPACE ();
29b0f896 1480 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1481 {
1482 char *string = input_line_pointer;
1483 int e = get_symbol_end ();
1484
47926f60 1485 if (strcmp (string, "prefix") == 0)
252b5132 1486 ask_naked_reg = 1;
47926f60 1487 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1488 ask_naked_reg = -1;
1489 else
d0b47220 1490 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1491 *input_line_pointer = e;
1492 }
1493 demand_empty_rest_of_line ();
c3332e24 1494
252b5132
RH		 1495 intel_syntax = syntax_flag;
1496
1497 if (ask_naked_reg == 0)
f86103b7
AM		 1498 allow_naked_reg = (intel_syntax
1499 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1500 else
1501 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1502
e4a3b5a4 1503 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1504 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1505 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1506}
1507
db51cc60
L		 1508static void
1509set_allow_index_reg (int flag)
1510{
1511 allow_index_reg = flag;
1512}
1513
e413e4e9 1514static void
e3bb37b5 1515set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1516{
47926f60 1517 SKIP_WHITESPACE ();
e413e4e9 1518
29b0f896 1519 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1520 {
1521 char *string = input_line_pointer;
1522 int e = get_symbol_end ();
9103f4f4 1523 unsigned int i;
40fb9820 1524 i386_cpu_flags flags;
e413e4e9 1525
9103f4f4 1526 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1527 {
1528 if (strcmp (string, cpu_arch[i].name) == 0)
1529 {
5c6af06e
JB		 1530 if (*string != '.')
1531 {
1532 cpu_arch_name = cpu_arch[i].name;
1533 cpu_sub_arch_name = NULL;
40fb9820
L		 1534 cpu_arch_flags = cpu_arch[i].flags;
1535 if (flag_code == CODE_64BIT)
1536 {
1537 cpu_arch_flags.bitfield.cpu64 = 1;
1538 cpu_arch_flags.bitfield.cpuno64 = 0;
1539 }
1540 else
1541 {
1542 cpu_arch_flags.bitfield.cpu64 = 0;
1543 cpu_arch_flags.bitfield.cpuno64 = 1;
1544 }
1545 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
ccc9c027 1546 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1547 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1548 if (!cpu_arch_tune_set)
1549 {
1550 cpu_arch_tune = cpu_arch_isa;
1551 cpu_arch_tune_flags = cpu_arch_isa_flags;
1552 }
5c6af06e
JB		 1553 break;
1554 }
40fb9820 1555
c6fb90c8
L		 1556 flags = cpu_flags_or (cpu_arch_flags,
1557 cpu_arch[i].flags);
1558 if (!UINTS_EQUAL (flags, cpu_arch_flags))
5c6af06e
JB		 1559 {
1560 cpu_sub_arch_name = cpu_arch[i].name;
40fb9820
L		 1561 cpu_arch_flags = flags;
1562 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
5c6af06e
JB		 1563 }
1564 *input_line_pointer = e;
1565 demand_empty_rest_of_line ();
1566 return;
e413e4e9
AM		 1567 }
1568 }
9103f4f4 1569 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1570 as_bad (_("no such architecture: `%s'"), string);
1571
1572 *input_line_pointer = e;
1573 }
1574 else
1575 as_bad (_("missing cpu architecture"));
1576
fddf5b5b
AM		 1577 no_cond_jump_promotion = 0;
1578 if (*input_line_pointer == ','
29b0f896 1579 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1580 {
1581 char *string = ++input_line_pointer;
1582 int e = get_symbol_end ();
1583
1584 if (strcmp (string, "nojumps") == 0)
1585 no_cond_jump_promotion = 1;
1586 else if (strcmp (string, "jumps") == 0)
1587 ;
1588 else
1589 as_bad (_("no such architecture modifier: `%s'"), string);
1590
1591 *input_line_pointer = e;
1592 }
1593
e413e4e9
AM		 1594 demand_empty_rest_of_line ();
1595}
1596
b9d79e03
JH		 1597unsigned long
1598i386_mach ()
1599{
1600 if (!strcmp (default_arch, "x86_64"))
1601 return bfd_mach_x86_64;
1602 else if (!strcmp (default_arch, "i386"))
1603 return bfd_mach_i386_i386;
1604 else
1605 as_fatal (_("Unknown architecture"));
1606}
b9d79e03 1607\f
252b5132
RH		 1608void
1609md_begin ()
1610{
1611 const char *hash_err;
1612
40fb9820
L		 1613 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
1614
47926f60 1615 /* Initialize op_hash hash table. */
252b5132
RH		 1616 op_hash = hash_new ();
1617
1618 {
29b0f896
AM		 1619 const template *optab;
1620 templates *core_optab;
252b5132 1621
47926f60
KH		 1622 /* Setup for loop. */
1623 optab = i386_optab;
252b5132
RH		 1624 core_optab = (templates *) xmalloc (sizeof (templates));
1625 core_optab->start = optab;
1626
1627 while (1)
1628 {
1629 ++optab;
1630 if (optab->name == NULL
1631 || strcmp (optab->name, (optab - 1)->name) != 0)
1632 {
1633 /* different name --> ship out current template list;
47926f60 1634 add to hash table; & begin anew. */
252b5132
RH		 1635 core_optab->end = optab;
1636 hash_err = hash_insert (op_hash,
1637 (optab - 1)->name,
1638 (PTR) core_optab);
1639 if (hash_err)
1640 {
252b5132
RH		 1641 as_fatal (_("Internal Error: Can't hash %s: %s"),
1642 (optab - 1)->name,
1643 hash_err);
1644 }
1645 if (optab->name == NULL)
1646 break;
1647 core_optab = (templates *) xmalloc (sizeof (templates));
1648 core_optab->start = optab;
1649 }
1650 }
1651 }
1652
47926f60 1653 /* Initialize reg_hash hash table. */
252b5132
RH		 1654 reg_hash = hash_new ();
1655 {
29b0f896 1656 const reg_entry *regtab;
c3fe08fa 1657 unsigned int regtab_size = i386_regtab_size;
252b5132 1658
c3fe08fa 1659 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132
RH		 1660 {
1661 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1662 if (hash_err)
3e73aa7c
JH		 1663 as_fatal (_("Internal Error: Can't hash %s: %s"),
1664 regtab->reg_name,
1665 hash_err);
252b5132
RH		 1666 }
1667 }
1668
47926f60 1669 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1670 {
29b0f896
AM		 1671 int c;
1672 char *p;
252b5132
RH		 1673
1674 for (c = 0; c < 256; c++)
1675 {
3882b010 1676 if (ISDIGIT (c))
252b5132
RH		 1677 {
1678 digit_chars[c] = c;
1679 mnemonic_chars[c] = c;
1680 register_chars[c] = c;
1681 operand_chars[c] = c;
1682 }
3882b010 1683 else if (ISLOWER (c))
252b5132
RH		 1684 {
1685 mnemonic_chars[c] = c;
1686 register_chars[c] = c;
1687 operand_chars[c] = c;
1688 }
3882b010 1689 else if (ISUPPER (c))
252b5132 1690 {
3882b010 1691 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1692 register_chars[c] = mnemonic_chars[c];
1693 operand_chars[c] = c;
1694 }
1695
3882b010 1696 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1697 identifier_chars[c] = c;
1698 else if (c >= 128)
1699 {
1700 identifier_chars[c] = c;
1701 operand_chars[c] = c;
1702 }
1703 }
1704
1705#ifdef LEX_AT
1706 identifier_chars['@'] = '@';
32137342
NC		 1707#endif
1708#ifdef LEX_QM
1709 identifier_chars['?'] = '?';
1710 operand_chars['?'] = '?';
252b5132 1711#endif
252b5132 1712 digit_chars['-'] = '-';
791fe849 1713 mnemonic_chars['-'] = '-';
0003779b 1714 mnemonic_chars['.'] = '.';
252b5132
RH		 1715 identifier_chars['_'] = '_';
1716 identifier_chars['.'] = '.';
1717
1718 for (p = operand_special_chars; *p != '\0'; p++)
1719 operand_chars[(unsigned char) *p] = *p;
1720 }
1721
1722#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1723 if (IS_ELF)
252b5132
RH		 1724 {
1725 record_alignment (text_section, 2);
1726 record_alignment (data_section, 2);
1727 record_alignment (bss_section, 2);
1728 }
1729#endif
a4447b93
RH		 1730
1731 if (flag_code == CODE_64BIT)
1732 {
1733 x86_dwarf2_return_column = 16;
1734 x86_cie_data_alignment = -8;
1735 }
1736 else
1737 {
1738 x86_dwarf2_return_column = 8;
1739 x86_cie_data_alignment = -4;
1740 }
252b5132
RH		 1741}
1742
1743void
e3bb37b5 1744i386_print_statistics (FILE *file)
252b5132
RH		 1745{
1746 hash_print_statistics (file, "i386 opcode", op_hash);
1747 hash_print_statistics (file, "i386 register", reg_hash);
1748}
1749\f
252b5132
RH		 1750#ifdef DEBUG386
1751
ce8a8b2f 1752/* Debugging routines for md_assemble. */
e3bb37b5 1753static void pte (template *);
40fb9820 1754static void pt (i386_operand_type);
e3bb37b5
L		 1755static void pe (expressionS *);
1756static void ps (symbolS *);
252b5132
RH		 1757
1758static void
e3bb37b5 1759pi (char *line, i386_insn *x)
252b5132 1760{
09f131f2 1761 unsigned int i;
252b5132
RH		 1762
1763 fprintf (stdout, "%s: template ", line);
1764 pte (&x->tm);
09f131f2
JH		 1765 fprintf (stdout, " address: base %s index %s scale %x\n",
1766 x->base_reg ? x->base_reg->reg_name : "none",
1767 x->index_reg ? x->index_reg->reg_name : "none",
1768 x->log2_scale_factor);
1769 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1770 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1771 fprintf (stdout, " sib: base %x index %x scale %x\n",
1772 x->sib.base, x->sib.index, x->sib.scale);
1773 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 1774 (x->rex & REX_W) != 0,
1775 (x->rex & REX_R) != 0,
1776 (x->rex & REX_X) != 0,
1777 (x->rex & REX_B) != 0);
85f10a01
MM		 1778 fprintf (stdout, " drex: reg %d rex 0x%x\n",
1779 x->drex.reg, x->drex.rex);
252b5132
RH		 1780 for (i = 0; i < x->operands; i++)
1781 {
1782 fprintf (stdout, " #%d: ", i + 1);
1783 pt (x->types[i]);
1784 fprintf (stdout, "\n");
40fb9820
L		 1785 if (x->types[i].bitfield.reg8
1786 || x->types[i].bitfield.reg16
1787 || x->types[i].bitfield.reg32
1788 || x->types[i].bitfield.reg64
1789 || x->types[i].bitfield.regmmx
1790 || x->types[i].bitfield.regxmm
1791 || x->types[i].bitfield.sreg2
1792 || x->types[i].bitfield.sreg3
1793 || x->types[i].bitfield.control
1794 || x->types[i].bitfield.debug
1795 || x->types[i].bitfield.test)
520dc8e8 1796 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 1797 if (operand_type_check (x->types[i], imm))
520dc8e8 1798 pe (x->op[i].imms);
40fb9820 1799 if (operand_type_check (x->types[i], disp))
520dc8e8 1800 pe (x->op[i].disps);
252b5132
RH		 1801 }
1802}
1803
1804static void
e3bb37b5 1805pte (template *t)
252b5132 1806{
09f131f2 1807 unsigned int i;
252b5132 1808 fprintf (stdout, " %d operands ", t->operands);
47926f60 1809 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1810 if (t->extension_opcode != None)
1811 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 1812 if (t->opcode_modifier.d)
252b5132 1813 fprintf (stdout, "D");
40fb9820 1814 if (t->opcode_modifier.w)
252b5132
RH		 1815 fprintf (stdout, "W");
1816 fprintf (stdout, "\n");
1817 for (i = 0; i < t->operands; i++)
1818 {
1819 fprintf (stdout, " #%d type ", i + 1);
1820 pt (t->operand_types[i]);
1821 fprintf (stdout, "\n");
1822 }
1823}
1824
1825static void
e3bb37b5 1826pe (expressionS *e)
252b5132 1827{
24eab124 1828 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1829 fprintf (stdout, " add_number %ld (%lx)\n",
1830 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1831 if (e->X_add_symbol)
1832 {
1833 fprintf (stdout, " add_symbol ");
1834 ps (e->X_add_symbol);
1835 fprintf (stdout, "\n");
1836 }
1837 if (e->X_op_symbol)
1838 {
1839 fprintf (stdout, " op_symbol ");
1840 ps (e->X_op_symbol);
1841 fprintf (stdout, "\n");
1842 }
1843}
1844
1845static void
e3bb37b5 1846ps (symbolS *s)
252b5132
RH		 1847{
1848 fprintf (stdout, "%s type %s%s",
1849 S_GET_NAME (s),
1850 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1851 segment_name (S_GET_SEGMENT (s)));
1852}
1853
7b81dfbb 1854static struct type_name
252b5132 1855 {
40fb9820
L		 1856 i386_operand_type mask;
1857 const char *name;
252b5132 1858 }
7b81dfbb 1859const type_names[] =
252b5132 1860{
40fb9820
L		 1861 { OPERAND_TYPE_REG8, "r8" },
1862 { OPERAND_TYPE_REG16, "r16" },
1863 { OPERAND_TYPE_REG32, "r32" },
1864 { OPERAND_TYPE_REG64, "r64" },
1865 { OPERAND_TYPE_IMM8, "i8" },
1866 { OPERAND_TYPE_IMM8, "i8s" },
1867 { OPERAND_TYPE_IMM16, "i16" },
1868 { OPERAND_TYPE_IMM32, "i32" },
1869 { OPERAND_TYPE_IMM32S, "i32s" },
1870 { OPERAND_TYPE_IMM64, "i64" },
1871 { OPERAND_TYPE_IMM1, "i1" },
1872 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
1873 { OPERAND_TYPE_DISP8, "d8" },
1874 { OPERAND_TYPE_DISP16, "d16" },
1875 { OPERAND_TYPE_DISP32, "d32" },
1876 { OPERAND_TYPE_DISP32S, "d32s" },
1877 { OPERAND_TYPE_DISP64, "d64" },
1878 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
1879 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
1880 { OPERAND_TYPE_CONTROL, "control reg" },
1881 { OPERAND_TYPE_TEST, "test reg" },
1882 { OPERAND_TYPE_DEBUG, "debug reg" },
1883 { OPERAND_TYPE_FLOATREG, "FReg" },
1884 { OPERAND_TYPE_FLOATACC, "FAcc" },
1885 { OPERAND_TYPE_SREG2, "SReg2" },
1886 { OPERAND_TYPE_SREG3, "SReg3" },
1887 { OPERAND_TYPE_ACC, "Acc" },
1888 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
1889 { OPERAND_TYPE_REGMMX, "rMMX" },
1890 { OPERAND_TYPE_REGXMM, "rXMM" },
1891 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 1892};
1893
1894static void
40fb9820 1895pt (i386_operand_type t)
252b5132 1896{
40fb9820 1897 unsigned int j;
c6fb90c8 1898 i386_operand_type a;
252b5132 1899
40fb9820 1900 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 1901 {
1902 a = operand_type_and (t, type_names[j].mask);
1903 if (!UINTS_ALL_ZERO (a))
1904 fprintf (stdout, "%s, ", type_names[j].name);
1905 }
252b5132
RH		 1906 fflush (stdout);
1907}
1908
1909#endif /* DEBUG386 */
1910\f
252b5132 1911static bfd_reloc_code_real_type
3956db08 1912reloc (unsigned int size,
64e74474
AM		 1913 int pcrel,
1914 int sign,
1915 bfd_reloc_code_real_type other)
252b5132 1916{
47926f60 1917 if (other != NO_RELOC)
3956db08
JB		 1918 {
1919 reloc_howto_type *reloc;
1920
1921 if (size == 8)
1922 switch (other)
1923 {
64e74474
AM		 1924 case BFD_RELOC_X86_64_GOT32:
1925 return BFD_RELOC_X86_64_GOT64;
1926 break;
1927 case BFD_RELOC_X86_64_PLTOFF64:
1928 return BFD_RELOC_X86_64_PLTOFF64;
1929 break;
1930 case BFD_RELOC_X86_64_GOTPC32:
1931 other = BFD_RELOC_X86_64_GOTPC64;
1932 break;
1933 case BFD_RELOC_X86_64_GOTPCREL:
1934 other = BFD_RELOC_X86_64_GOTPCREL64;
1935 break;
1936 case BFD_RELOC_X86_64_TPOFF32:
1937 other = BFD_RELOC_X86_64_TPOFF64;
1938 break;
1939 case BFD_RELOC_X86_64_DTPOFF32:
1940 other = BFD_RELOC_X86_64_DTPOFF64;
1941 break;
1942 default:
1943 break;
3956db08 1944 }
e05278af
JB		 1945
1946 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1947 if (size == 4 && flag_code != CODE_64BIT)
1948 sign = -1;
1949
3956db08
JB		 1950 reloc = bfd_reloc_type_lookup (stdoutput, other);
1951 if (!reloc)
1952 as_bad (_("unknown relocation (%u)"), other);
1953 else if (size != bfd_get_reloc_size (reloc))
1954 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1955 bfd_get_reloc_size (reloc),
1956 size);
1957 else if (pcrel && !reloc->pc_relative)
1958 as_bad (_("non-pc-relative relocation for pc-relative field"));
1959 else if ((reloc->complain_on_overflow == complain_overflow_signed
1960 && !sign)
1961 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1962 && sign > 0))
3956db08
JB		 1963 as_bad (_("relocated field and relocation type differ in signedness"));
1964 else
1965 return other;
1966 return NO_RELOC;
1967 }
252b5132
RH		 1968
1969 if (pcrel)
1970 {
3e73aa7c 1971 if (!sign)
3956db08 1972 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1973 switch (size)
1974 {
1975 case 1: return BFD_RELOC_8_PCREL;
1976 case 2: return BFD_RELOC_16_PCREL;
1977 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1978 case 8: return BFD_RELOC_64_PCREL;
252b5132 1979 }
3956db08 1980 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1981 }
1982 else
1983 {
3956db08 1984 if (sign > 0)
e5cb08ac 1985 switch (size)
3e73aa7c
JH		 1986 {
1987 case 4: return BFD_RELOC_X86_64_32S;
1988 }
1989 else
1990 switch (size)
1991 {
1992 case 1: return BFD_RELOC_8;
1993 case 2: return BFD_RELOC_16;
1994 case 4: return BFD_RELOC_32;
1995 case 8: return BFD_RELOC_64;
1996 }
3956db08
JB		 1997 as_bad (_("cannot do %s %u byte relocation"),
1998 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1999 }
2000
bfb32b52 2001 abort ();
252b5132
RH		 2002 return BFD_RELOC_NONE;
2003}
2004
47926f60
KH		 2005/* Here we decide which fixups can be adjusted to make them relative to
2006 the beginning of the section instead of the symbol. Basically we need
2007 to make sure that the dynamic relocations are done correctly, so in
2008 some cases we force the original symbol to be used. */
2009
252b5132 2010int
e3bb37b5 2011tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2012{
6d249963 2013#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2014 if (!IS_ELF)
31312f95
AM		 2015 return 1;
2016
a161fe53
AM		 2017 /* Don't adjust pc-relative references to merge sections in 64-bit
2018 mode. */
2019 if (use_rela_relocations
2020 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2021 && fixP->fx_pcrel)
252b5132 2022 return 0;
31312f95 2023
8d01d9a9
AJ		 2024 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2025 and changed later by validate_fix. */
2026 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2027 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2028 return 0;
2029
ce8a8b2f 2030 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2031 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2032 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2033 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2034 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2035 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2036 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2037 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2038 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2039 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2040 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2041 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2042 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2043 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2044 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2045 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2046 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2047 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2048 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2049 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2050 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2051 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2052 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2053 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2054 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2055 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2056 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2057 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2058 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2059 return 0;
31312f95 2060#endif
252b5132
RH		 2061 return 1;
2062}
252b5132 2063
b4cac588 2064static int
e3bb37b5 2065intel_float_operand (const char *mnemonic)
252b5132 2066{
9306ca4a
JB		 2067 /* Note that the value returned is meaningful only for opcodes with (memory)
2068 operands, hence the code here is free to improperly handle opcodes that
2069 have no operands (for better performance and smaller code). */
2070
2071 if (mnemonic[0] != 'f')
2072 return 0; /* non-math */
2073
2074 switch (mnemonic[1])
2075 {
2076 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2077 the fs segment override prefix not currently handled because no
2078 call path can make opcodes without operands get here */
2079 case 'i':
2080 return 2 /* integer op */;
2081 case 'l':
2082 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2083 return 3; /* fldcw/fldenv */
2084 break;
2085 case 'n':
2086 if (mnemonic[2] != 'o' /* fnop */)
2087 return 3; /* non-waiting control op */
2088 break;
2089 case 'r':
2090 if (mnemonic[2] == 's')
2091 return 3; /* frstor/frstpm */
2092 break;
2093 case 's':
2094 if (mnemonic[2] == 'a')
2095 return 3; /* fsave */
2096 if (mnemonic[2] == 't')
2097 {
2098 switch (mnemonic[3])
2099 {
2100 case 'c': /* fstcw */
2101 case 'd': /* fstdw */
2102 case 'e': /* fstenv */
2103 case 's': /* fsts[gw] */
2104 return 3;
2105 }
2106 }
2107 break;
2108 case 'x':
2109 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2110 return 0; /* fxsave/fxrstor are not really math ops */
2111 break;
2112 }
252b5132 2113
9306ca4a 2114 return 1;
252b5132
RH		 2115}
2116
2117/* This is the guts of the machine-dependent assembler. LINE points to a
2118 machine dependent instruction. This function is supposed to emit
2119 the frags/bytes it assembles to. */
2120
2121void
2122md_assemble (line)
2123 char *line;
2124{
40fb9820 2125 unsigned int j;
252b5132
RH		 2126 char mnemonic[MAX_MNEM_SIZE];
2127
47926f60 2128 /* Initialize globals. */
252b5132
RH		 2129 memset (&i, '\0', sizeof (i));
2130 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2131 i.reloc[j] = NO_RELOC;
252b5132
RH		 2132 memset (disp_expressions, '\0', sizeof (disp_expressions));
2133 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2134 save_stack_p = save_stack;
252b5132
RH		 2135
2136 /* First parse an instruction mnemonic & call i386_operand for the operands.
2137 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2138 start of a (possibly prefixed) mnemonic. */
252b5132 2139
29b0f896
AM		 2140 line = parse_insn (line, mnemonic);
2141 if (line == NULL)
2142 return;
252b5132 2143
29b0f896
AM		 2144 line = parse_operands (line, mnemonic);
2145 if (line == NULL)
2146 return;
252b5132 2147
29b0f896
AM		 2148 /* Now we've parsed the mnemonic into a set of templates, and have the
2149 operands at hand. */
2150
2151 /* All intel opcodes have reversed operands except for "bound" and
2152 "enter". We also don't reverse intersegment "jmp" and "call"
2153 instructions with 2 immediate operands so that the immediate segment
050dfa73 2154 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2155 if (intel_syntax
2156 && i.operands > 1
29b0f896 2157 && (strcmp (mnemonic, "bound") != 0)
30123838 2158 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2159 && !(operand_type_check (i.types[0], imm)
2160 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2161 swap_operands ();
2162
ec56d5c0
JB		 2163 /* The order of the immediates should be reversed
2164 for 2 immediates extrq and insertq instructions */
2165 if (i.imm_operands == 2
2166 && (strcmp (mnemonic, "extrq") == 0
2167 || strcmp (mnemonic, "insertq") == 0))
2168 swap_2_operands (0, 1);
2169
29b0f896
AM		 2170 if (i.imm_operands)
2171 optimize_imm ();
2172
b300c311
L		 2173 /* Don't optimize displacement for movabs since it only takes 64bit
2174 displacement. */
2175 if (i.disp_operands
2176 && (flag_code != CODE_64BIT
2177 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2178 optimize_disp ();
2179
2180 /* Next, we find a template that matches the given insn,
2181 making sure the overlap of the given operands types is consistent
2182 with the template operand types. */
252b5132 2183
29b0f896
AM		 2184 if (!match_template ())
2185 return;
252b5132 2186
cd61ebfe
AM		 2187 if (intel_syntax)
2188 {
2189 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
2190 if (SYSV386_COMPAT
2191 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
8a2ed489 2192 i.tm.base_opcode ^= Opcode_FloatR;
cd61ebfe
AM		 2193
2194 /* Zap movzx and movsx suffix. The suffix may have been set from
2195 "word ptr" or "byte ptr" on the source operand, but we'll use
2196 the suffix later to choose the destination register. */
2197 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 2198 {
2199 if (i.reg_operands < 2
2200 && !i.suffix
40fb9820
L		 2201 && (!i.tm.opcode_modifier.no_bsuf
2202 || !i.tm.opcode_modifier.no_wsuf
2203 || !i.tm.opcode_modifier.no_lsuf
2204 || !i.tm.opcode_modifier.no_ssuf
2205 || !i.tm.opcode_modifier.no_xsuf
2206 || !i.tm.opcode_modifier.no_qsuf))
9306ca4a
JB		 2207 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2208
2209 i.suffix = 0;
2210 }
cd61ebfe 2211 }
24eab124 2212
40fb9820 2213 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2214 if (!add_prefix (FWAIT_OPCODE))
2215 return;
252b5132 2216
29b0f896 2217 /* Check string instruction segment overrides. */
40fb9820 2218 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2219 {
2220 if (!check_string ())
5dd0794d 2221 return;
29b0f896 2222 }
5dd0794d 2223
29b0f896
AM		 2224 if (!process_suffix ())
2225 return;
e413e4e9 2226
29b0f896
AM		 2227 /* Make still unresolved immediate matches conform to size of immediate
2228 given in i.suffix. */
2229 if (!finalize_imm ())
2230 return;
252b5132 2231
40fb9820 2232 if (i.types[0].bitfield.imm1)
29b0f896 2233 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2234
40fb9820 2235 for (j = 0; j < 3; j++)
c6fb90c8
L		 2236 if (i.types[j].bitfield.inoutportreg
2237 || i.types[j].bitfield.shiftcount
2238 || i.types[j].bitfield.acc
2239 || i.types[j].bitfield.floatacc)
40fb9820
L		 2240 i.reg_operands--;
2241
2242 if (i.tm.opcode_modifier.immext)
29b0f896 2243 {
02fc3089
L		 2244 expressionS *exp;
2245
40fb9820 2246 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
ca164297 2247 {
b7d9ef37 2248 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 2249 operands with an opcode suffix which is coded in the same
2250 place as an 8-bit immediate field would be. Here we check
2251 those operands and remove them afterwards. */
2252 unsigned int x;
2253
a4622f40 2254 for (x = 0; x < i.operands; x++)
ca164297 2255 if (i.op[x].regs->reg_num != x)
a540244d
L		 2256 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2257 register_prefix,
2258 i.op[x].regs->reg_name,
2259 x + 1,
2260 i.tm.name);
ca164297
L		 2261 i.operands = 0;
2262 }
2263
29b0f896
AM		 2264 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2265 opcode suffix which is coded in the same place as an 8-bit
2266 immediate field would be. Here we fake an 8-bit immediate
85f10a01
MM		 2267 operand from the opcode suffix stored in tm.extension_opcode.
2268 SSE5 also uses this encoding, for some of its 3 argument
2269 instructions. */
252b5132 2270
85f10a01
MM		 2271 assert (i.imm_operands == 0
2272 && (i.operands <= 2
2273 || (i.tm.cpu_flags.bitfield.cpusse5
2274 && i.operands <= 3)));
252b5132 2275
29b0f896
AM		 2276 exp = &im_expressions[i.imm_operands++];
2277 i.op[i.operands].imms = exp;
c6fb90c8 2278 UINTS_CLEAR (i.types[i.operands]);
40fb9820
L		 2279 i.types[i.operands].bitfield.imm8 = 1;
2280 i.operands++;
29b0f896
AM		 2281 exp->X_op = O_constant;
2282 exp->X_add_number = i.tm.extension_opcode;
2283 i.tm.extension_opcode = None;
2284 }
252b5132 2285
29b0f896
AM		 2286 /* For insns with operands there are more diddles to do to the opcode. */
2287 if (i.operands)
2288 {
2289 if (!process_operands ())
2290 return;
2291 }
40fb9820 2292 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2293 {
2294 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2295 as_warn (_("translating to `%sp'"), i.tm.name);
2296 }
252b5132 2297
29b0f896
AM		 2298 /* Handle conversion of 'int $3' --> special int3 insn. */
2299 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2300 {
2301 i.tm.base_opcode = INT3_OPCODE;
2302 i.imm_operands = 0;
2303 }
252b5132 2304
40fb9820
L		 2305 if ((i.tm.opcode_modifier.jump
2306 || i.tm.opcode_modifier.jumpbyte
2307 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2308 && i.op[0].disps->X_op == O_constant)
2309 {
2310 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2311 the absolute address given by the constant. Since ix86 jumps and
2312 calls are pc relative, we need to generate a reloc. */
2313 i.op[0].disps->X_add_symbol = &abs_symbol;
2314 i.op[0].disps->X_op = O_symbol;
2315 }
252b5132 2316
40fb9820 2317 if (i.tm.opcode_modifier.rex64)
161a04f6 2318 i.rex |= REX_W;
252b5132 2319
29b0f896
AM		 2320 /* For 8 bit registers we need an empty rex prefix. Also if the
2321 instruction already has a prefix, we need to convert old
2322 registers to new ones. */
773f551c 2323
40fb9820 2324 if ((i.types[0].bitfield.reg8
29b0f896 2325 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2326 || (i.types[1].bitfield.reg8
29b0f896 2327 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2328 || ((i.types[0].bitfield.reg8
2329 || i.types[1].bitfield.reg8)
29b0f896
AM		 2330 && i.rex != 0))
2331 {
2332 int x;
726c5dcd 2333
29b0f896
AM		 2334 i.rex |= REX_OPCODE;
2335 for (x = 0; x < 2; x++)
2336 {
2337 /* Look for 8 bit operand that uses old registers. */
40fb9820 2338 if (i.types[x].bitfield.reg8
29b0f896 2339 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2340 {
29b0f896
AM		 2341 /* In case it is "hi" register, give up. */
2342 if (i.op[x].regs->reg_num > 3)
a540244d 2343 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2344 "instruction requiring REX prefix."),
a540244d 2345 register_prefix, i.op[x].regs->reg_name);
773f551c 2346
29b0f896
AM		 2347 /* Otherwise it is equivalent to the extended register.
2348 Since the encoding doesn't change this is merely
2349 cosmetic cleanup for debug output. */
2350
2351 i.op[x].regs = i.op[x].regs + 8;
773f551c 2352 }
29b0f896
AM		 2353 }
2354 }
773f551c 2355
85f10a01
MM		 2356 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2357 REX prefix. */
2358 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2359 {
2360 i.drex.rex = i.rex;
2361 i.rex = 0;
2362 }
2363 else if (i.rex != 0)
29b0f896
AM		 2364 add_prefix (REX_OPCODE | i.rex);
2365
2366 /* We are ready to output the insn. */
2367 output_insn ();
2368}
2369
2370static char *
e3bb37b5 2371parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2372{
2373 char *l = line;
2374 char *token_start = l;
2375 char *mnem_p;
5c6af06e
JB		 2376 int supported;
2377 const template *t;
29b0f896
AM		 2378
2379 /* Non-zero if we found a prefix only acceptable with string insns. */
2380 const char *expecting_string_instruction = NULL;
45288df1 2381
29b0f896
AM		 2382 while (1)
2383 {
2384 mnem_p = mnemonic;
2385 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2386 {
2387 mnem_p++;
2388 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2389 {
29b0f896
AM		 2390 as_bad (_("no such instruction: `%s'"), token_start);
2391 return NULL;
2392 }
2393 l++;
2394 }
2395 if (!is_space_char (*l)
2396 && *l != END_OF_INSN
e44823cf
JB		 2397 && (intel_syntax
2398 || (*l != PREFIX_SEPARATOR
2399 && *l != ',')))
29b0f896
AM		 2400 {
2401 as_bad (_("invalid character %s in mnemonic"),
2402 output_invalid (*l));
2403 return NULL;
2404 }
2405 if (token_start == l)
2406 {
e44823cf 2407 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2408 as_bad (_("expecting prefix; got nothing"));
2409 else
2410 as_bad (_("expecting mnemonic; got nothing"));
2411 return NULL;
2412 }
45288df1 2413
29b0f896
AM		 2414 /* Look up instruction (or prefix) via hash table. */
2415 current_templates = hash_find (op_hash, mnemonic);
47926f60 2416
29b0f896
AM		 2417 if (*l != END_OF_INSN
2418 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2419 && current_templates
40fb9820 2420 && current_templates->start->opcode_modifier.isprefix)
29b0f896 2421 {
c6fb90c8 2422 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 2423 {
2424 as_bad ((flag_code != CODE_64BIT
2425 ? _("`%s' is only supported in 64-bit mode")
2426 : _("`%s' is not supported in 64-bit mode")),
2427 current_templates->start->name);
2428 return NULL;
2429 }
29b0f896
AM		 2430 /* If we are in 16-bit mode, do not allow addr16 or data16.
2431 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 2432 if ((current_templates->start->opcode_modifier.size16
2433 || current_templates->start->opcode_modifier.size32)
29b0f896 2434 && flag_code != CODE_64BIT
40fb9820 2435 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 2436 ^ (flag_code == CODE_16BIT)))
2437 {
2438 as_bad (_("redundant %s prefix"),
2439 current_templates->start->name);
2440 return NULL;
45288df1 2441 }
29b0f896
AM		 2442 /* Add prefix, checking for repeated prefixes. */
2443 switch (add_prefix (current_templates->start->base_opcode))
2444 {
2445 case 0:
2446 return NULL;
2447 case 2:
2448 expecting_string_instruction = current_templates->start->name;
2449 break;
2450 }
2451 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2452 token_start = ++l;
2453 }
2454 else
2455 break;
2456 }
45288df1 2457
29b0f896
AM		 2458 if (!current_templates)
2459 {
2460 /* See if we can get a match by trimming off a suffix. */
2461 switch (mnem_p[-1])
2462 {
2463 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2464 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2465 i.suffix = SHORT_MNEM_SUFFIX;
2466 else
29b0f896
AM		 2467 case BYTE_MNEM_SUFFIX:
2468 case QWORD_MNEM_SUFFIX:
2469 i.suffix = mnem_p[-1];
2470 mnem_p[-1] = '\0';
2471 current_templates = hash_find (op_hash, mnemonic);
2472 break;
2473 case SHORT_MNEM_SUFFIX:
2474 case LONG_MNEM_SUFFIX:
2475 if (!intel_syntax)
2476 {
2477 i.suffix = mnem_p[-1];
2478 mnem_p[-1] = '\0';
2479 current_templates = hash_find (op_hash, mnemonic);
2480 }
2481 break;
252b5132 2482
29b0f896
AM		 2483 /* Intel Syntax. */
2484 case 'd':
2485 if (intel_syntax)
2486 {
9306ca4a 2487 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2488 i.suffix = SHORT_MNEM_SUFFIX;
2489 else
2490 i.suffix = LONG_MNEM_SUFFIX;
2491 mnem_p[-1] = '\0';
2492 current_templates = hash_find (op_hash, mnemonic);
2493 }
2494 break;
2495 }
2496 if (!current_templates)
2497 {
2498 as_bad (_("no such instruction: `%s'"), token_start);
2499 return NULL;
2500 }
2501 }
252b5132 2502
40fb9820
L		 2503 if (current_templates->start->opcode_modifier.jump
2504 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 2505 {
2506 /* Check for a branch hint. We allow ",pt" and ",pn" for
2507 predict taken and predict not taken respectively.
2508 I'm not sure that branch hints actually do anything on loop
2509 and jcxz insns (JumpByte) for current Pentium4 chips. They
2510 may work in the future and it doesn't hurt to accept them
2511 now. */
2512 if (l[0] == ',' && l[1] == 'p')
2513 {
2514 if (l[2] == 't')
2515 {
2516 if (!add_prefix (DS_PREFIX_OPCODE))
2517 return NULL;
2518 l += 3;
2519 }
2520 else if (l[2] == 'n')
2521 {
2522 if (!add_prefix (CS_PREFIX_OPCODE))
2523 return NULL;
2524 l += 3;
2525 }
2526 }
2527 }
2528 /* Any other comma loses. */
2529 if (*l == ',')
2530 {
2531 as_bad (_("invalid character %s in mnemonic"),
2532 output_invalid (*l));
2533 return NULL;
2534 }
252b5132 2535
29b0f896 2536 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2537 supported = 0;
2538 for (t = current_templates->start; t < current_templates->end; ++t)
2539 {
40fb9820 2540 if (cpu_flags_match (t->cpu_flags))
64e74474 2541 supported |= 1;
c6fb90c8 2542 if (cpu_flags_check_cpu64 (t->cpu_flags))
64e74474 2543 supported |= 2;
5c6af06e
JB		 2544 }
2545 if (!(supported & 2))
2546 {
2547 as_bad (flag_code == CODE_64BIT
2548 ? _("`%s' is not supported in 64-bit mode")
2549 : _("`%s' is only supported in 64-bit mode"),
2550 current_templates->start->name);
2551 return NULL;
2552 }
2553 if (!(supported & 1))
29b0f896 2554 {
5c6af06e
JB		 2555 as_warn (_("`%s' is not supported on `%s%s'"),
2556 current_templates->start->name,
2557 cpu_arch_name,
2558 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896 2559 }
40fb9820
L		 2560 else if (!cpu_arch_flags.bitfield.cpui386
2561 && (flag_code != CODE_16BIT))
29b0f896
AM		 2562 {
2563 as_warn (_("use .code16 to ensure correct addressing mode"));
2564 }
252b5132 2565
29b0f896 2566 /* Check for rep/repne without a string instruction. */
f41bbced 2567 if (expecting_string_instruction)
29b0f896 2568 {
f41bbced
JB		 2569 static templates override;
2570
2571 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 2572 if (t->opcode_modifier.isstring)
f41bbced
JB		 2573 break;
2574 if (t >= current_templates->end)
2575 {
2576 as_bad (_("expecting string instruction after `%s'"),
64e74474 2577 expecting_string_instruction);
f41bbced
JB		 2578 return NULL;
2579 }
2580 for (override.start = t; t < current_templates->end; ++t)
40fb9820 2581 if (!t->opcode_modifier.isstring)
f41bbced
JB		 2582 break;
2583 override.end = t;
2584 current_templates = &override;
29b0f896 2585 }
252b5132 2586
29b0f896
AM		 2587 return l;
2588}
252b5132 2589
29b0f896 2590static char *
e3bb37b5 2591parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 2592{
2593 char *token_start;
3138f287 2594
29b0f896
AM		 2595 /* 1 if operand is pending after ','. */
2596 unsigned int expecting_operand = 0;
252b5132 2597
29b0f896
AM		 2598 /* Non-zero if operand parens not balanced. */
2599 unsigned int paren_not_balanced;
2600
2601 while (*l != END_OF_INSN)
2602 {
2603 /* Skip optional white space before operand. */
2604 if (is_space_char (*l))
2605 ++l;
2606 if (!is_operand_char (*l) && *l != END_OF_INSN)
2607 {
2608 as_bad (_("invalid character %s before operand %d"),
2609 output_invalid (*l),
2610 i.operands + 1);
2611 return NULL;
2612 }
2613 token_start = l; /* after white space */
2614 paren_not_balanced = 0;
2615 while (paren_not_balanced || *l != ',')
2616 {
2617 if (*l == END_OF_INSN)
2618 {
2619 if (paren_not_balanced)
2620 {
2621 if (!intel_syntax)
2622 as_bad (_("unbalanced parenthesis in operand %d."),
2623 i.operands + 1);
2624 else
2625 as_bad (_("unbalanced brackets in operand %d."),
2626 i.operands + 1);
2627 return NULL;
2628 }
2629 else
2630 break; /* we are done */
2631 }
2632 else if (!is_operand_char (*l) && !is_space_char (*l))
2633 {
2634 as_bad (_("invalid character %s in operand %d"),
2635 output_invalid (*l),
2636 i.operands + 1);
2637 return NULL;
2638 }
2639 if (!intel_syntax)
2640 {
2641 if (*l == '(')
2642 ++paren_not_balanced;
2643 if (*l == ')')
2644 --paren_not_balanced;
2645 }
2646 else
2647 {
2648 if (*l == '[')
2649 ++paren_not_balanced;
2650 if (*l == ']')
2651 --paren_not_balanced;
2652 }
2653 l++;
2654 }
2655 if (l != token_start)
2656 { /* Yes, we've read in another operand. */
2657 unsigned int operand_ok;
2658 this_operand = i.operands++;
2659 if (i.operands > MAX_OPERANDS)
2660 {
2661 as_bad (_("spurious operands; (%d operands/instruction max)"),
2662 MAX_OPERANDS);
2663 return NULL;
2664 }
2665 /* Now parse operand adding info to 'i' as we go along. */
2666 END_STRING_AND_SAVE (l);
2667
2668 if (intel_syntax)
2669 operand_ok =
2670 i386_intel_operand (token_start,
2671 intel_float_operand (mnemonic));
2672 else
2673 operand_ok = i386_operand (token_start);
2674
2675 RESTORE_END_STRING (l);
2676 if (!operand_ok)
2677 return NULL;
2678 }
2679 else
2680 {
2681 if (expecting_operand)
2682 {
2683 expecting_operand_after_comma:
2684 as_bad (_("expecting operand after ','; got nothing"));
2685 return NULL;
2686 }
2687 if (*l == ',')
2688 {
2689 as_bad (_("expecting operand before ','; got nothing"));
2690 return NULL;
2691 }
2692 }
7f3f1ea2 2693
29b0f896
AM		 2694 /* Now *l must be either ',' or END_OF_INSN. */
2695 if (*l == ',')
2696 {
2697 if (*++l == END_OF_INSN)
2698 {
2699 /* Just skip it, if it's \n complain. */
2700 goto expecting_operand_after_comma;
2701 }
2702 expecting_operand = 1;
2703 }
2704 }
2705 return l;
2706}
7f3f1ea2 2707
050dfa73 2708static void
4d456e3d 2709swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 2710{
2711 union i386_op temp_op;
40fb9820 2712 i386_operand_type temp_type;
050dfa73 2713 enum bfd_reloc_code_real temp_reloc;
4eed87de 2714
050dfa73
MM		 2715 temp_type = i.types[xchg2];
2716 i.types[xchg2] = i.types[xchg1];
2717 i.types[xchg1] = temp_type;
2718 temp_op = i.op[xchg2];
2719 i.op[xchg2] = i.op[xchg1];
2720 i.op[xchg1] = temp_op;
2721 temp_reloc = i.reloc[xchg2];
2722 i.reloc[xchg2] = i.reloc[xchg1];
2723 i.reloc[xchg1] = temp_reloc;
2724}
2725
29b0f896 2726static void
e3bb37b5 2727swap_operands (void)
29b0f896 2728{
b7c61d9a 2729 switch (i.operands)
050dfa73 2730 {
b7c61d9a 2731 case 4:
4d456e3d 2732 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 2733 case 3:
2734 case 2:
4d456e3d 2735 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 2736 break;
2737 default:
2738 abort ();
29b0f896 2739 }
29b0f896
AM		 2740
2741 if (i.mem_operands == 2)
2742 {
2743 const seg_entry *temp_seg;
2744 temp_seg = i.seg[0];
2745 i.seg[0] = i.seg[1];
2746 i.seg[1] = temp_seg;
2747 }
2748}
252b5132 2749
29b0f896
AM		 2750/* Try to ensure constant immediates are represented in the smallest
2751 opcode possible. */
2752static void
e3bb37b5 2753optimize_imm (void)
29b0f896
AM		 2754{
2755 char guess_suffix = 0;
2756 int op;
252b5132 2757
29b0f896
AM		 2758 if (i.suffix)
2759 guess_suffix = i.suffix;
2760 else if (i.reg_operands)
2761 {
2762 /* Figure out a suffix from the last register operand specified.
2763 We can't do this properly yet, ie. excluding InOutPortReg,
2764 but the following works for instructions with immediates.
2765 In any case, we can't set i.suffix yet. */
2766 for (op = i.operands; --op >= 0;)
40fb9820
L		 2767 if (i.types[op].bitfield.reg8)
2768 {
2769 guess_suffix = BYTE_MNEM_SUFFIX;
2770 break;
2771 }
2772 else if (i.types[op].bitfield.reg16)
252b5132 2773 {
40fb9820
L		 2774 guess_suffix = WORD_MNEM_SUFFIX;
2775 break;
2776 }
2777 else if (i.types[op].bitfield.reg32)
2778 {
2779 guess_suffix = LONG_MNEM_SUFFIX;
2780 break;
2781 }
2782 else if (i.types[op].bitfield.reg64)
2783 {
2784 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 2785 break;
252b5132 2786 }
29b0f896
AM		 2787 }
2788 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2789 guess_suffix = WORD_MNEM_SUFFIX;
2790
2791 for (op = i.operands; --op >= 0;)
40fb9820 2792 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 2793 {
2794 switch (i.op[op].imms->X_op)
252b5132 2795 {
29b0f896
AM		 2796 case O_constant:
2797 /* If a suffix is given, this operand may be shortened. */
2798 switch (guess_suffix)
252b5132 2799 {
29b0f896 2800 case LONG_MNEM_SUFFIX:
40fb9820
L		 2801 i.types[op].bitfield.imm32 = 1;
2802 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 2803 break;
2804 case WORD_MNEM_SUFFIX:
40fb9820
L		 2805 i.types[op].bitfield.imm16 = 1;
2806 i.types[op].bitfield.imm32 = 1;
2807 i.types[op].bitfield.imm32s = 1;
2808 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 2809 break;
2810 case BYTE_MNEM_SUFFIX:
40fb9820
L		 2811 i.types[op].bitfield.imm8 = 1;
2812 i.types[op].bitfield.imm8s = 1;
2813 i.types[op].bitfield.imm16 = 1;
2814 i.types[op].bitfield.imm32 = 1;
2815 i.types[op].bitfield.imm32s = 1;
2816 i.types[op].bitfield.imm64 = 1;
29b0f896 2817 break;
252b5132 2818 }
252b5132 2819
29b0f896
AM		 2820 /* If this operand is at most 16 bits, convert it
2821 to a signed 16 bit number before trying to see
2822 whether it will fit in an even smaller size.
2823 This allows a 16-bit operand such as $0xffe0 to
2824 be recognised as within Imm8S range. */
40fb9820 2825 if ((i.types[op].bitfield.imm16)
29b0f896 2826 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2827 {
29b0f896
AM		 2828 i.op[op].imms->X_add_number =
2829 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2830 }
40fb9820 2831 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 2832 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2833 == 0))
2834 {
2835 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2836 ^ ((offsetT) 1 << 31))
2837 - ((offsetT) 1 << 31));
2838 }
40fb9820 2839 i.types[op]
c6fb90c8
L		 2840 = operand_type_or (i.types[op],
2841 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 2842
29b0f896
AM		 2843 /* We must avoid matching of Imm32 templates when 64bit
2844 only immediate is available. */
2845 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 2846 i.types[op].bitfield.imm32 = 0;
29b0f896 2847 break;
252b5132 2848
29b0f896
AM		 2849 case O_absent:
2850 case O_register:
2851 abort ();
2852
2853 /* Symbols and expressions. */
2854 default:
9cd96992
JB		 2855 /* Convert symbolic operand to proper sizes for matching, but don't
2856 prevent matching a set of insns that only supports sizes other
2857 than those matching the insn suffix. */
2858 {
40fb9820 2859 i386_operand_type mask, allowed;
9cd96992
JB		 2860 const template *t;
2861
c6fb90c8
L		 2862 UINTS_CLEAR (mask);
2863 UINTS_CLEAR (allowed);
40fb9820 2864
4eed87de
AM		 2865 for (t = current_templates->start;
2866 t < current_templates->end;
2867 ++t)
c6fb90c8
L		 2868 allowed = operand_type_or (allowed,
2869 t->operand_types[op]);
9cd96992
JB		 2870 switch (guess_suffix)
2871 {
2872 case QWORD_MNEM_SUFFIX:
40fb9820
L		 2873 mask.bitfield.imm64 = 1;
2874 mask.bitfield.imm32s = 1;
9cd96992
JB		 2875 break;
2876 case LONG_MNEM_SUFFIX:
40fb9820 2877 mask.bitfield.imm32 = 1;
9cd96992
JB		 2878 break;
2879 case WORD_MNEM_SUFFIX:
40fb9820 2880 mask.bitfield.imm16 = 1;
9cd96992
JB		 2881 break;
2882 case BYTE_MNEM_SUFFIX:
40fb9820 2883 mask.bitfield.imm8 = 1;
9cd96992
JB		 2884 break;
2885 default:
9cd96992
JB		 2886 break;
2887 }
c6fb90c8
L		 2888 allowed = operand_type_and (mask, allowed);
2889 if (!UINTS_ALL_ZERO (allowed))
2890 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 2891 }
29b0f896 2892 break;
252b5132 2893 }
29b0f896
AM		 2894 }
2895}
47926f60 2896
29b0f896
AM		 2897/* Try to use the smallest displacement type too. */
2898static void
e3bb37b5 2899optimize_disp (void)
29b0f896
AM		 2900{
2901 int op;
3e73aa7c 2902
29b0f896 2903 for (op = i.operands; --op >= 0;)
40fb9820 2904 if (operand_type_check (i.types[op], disp))
252b5132 2905 {
b300c311 2906 if (i.op[op].disps->X_op == O_constant)
252b5132 2907 {
b300c311 2908 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2909
40fb9820 2910 if (i.types[op].bitfield.disp16
b300c311
L		 2911 && (disp & ~(offsetT) 0xffff) == 0)
2912 {
2913 /* If this operand is at most 16 bits, convert
2914 to a signed 16 bit number and don't use 64bit
2915 displacement. */
2916 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 2917 i.types[op].bitfield.disp64 = 0;
b300c311 2918 }
40fb9820 2919 if (i.types[op].bitfield.disp32
b300c311
L		 2920 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2921 {
2922 /* If this operand is at most 32 bits, convert
2923 to a signed 32 bit number and don't use 64bit
2924 displacement. */
2925 disp &= (((offsetT) 2 << 31) - 1);
2926 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 2927 i.types[op].bitfield.disp64 = 0;
b300c311 2928 }
40fb9820 2929 if (!disp && i.types[op].bitfield.baseindex)
b300c311 2930 {
40fb9820
L		 2931 i.types[op].bitfield.disp8 = 0;
2932 i.types[op].bitfield.disp16 = 0;
2933 i.types[op].bitfield.disp32 = 0;
2934 i.types[op].bitfield.disp32s = 0;
2935 i.types[op].bitfield.disp64 = 0;
b300c311
L		 2936 i.op[op].disps = 0;
2937 i.disp_operands--;
2938 }
2939 else if (flag_code == CODE_64BIT)
2940 {
2941 if (fits_in_signed_long (disp))
28a9d8f5 2942 {
40fb9820
L		 2943 i.types[op].bitfield.disp64 = 0;
2944 i.types[op].bitfield.disp32s = 1;
28a9d8f5 2945 }
b300c311 2946 if (fits_in_unsigned_long (disp))
40fb9820 2947 i.types[op].bitfield.disp32 = 1;
b300c311 2948 }
40fb9820
L		 2949 if ((i.types[op].bitfield.disp32
2950 || i.types[op].bitfield.disp32s
2951 || i.types[op].bitfield.disp16)
b300c311 2952 && fits_in_signed_byte (disp))
40fb9820 2953 i.types[op].bitfield.disp8 = 1;
252b5132 2954 }
67a4f2b7
AO		 2955 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2956 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2957 {
2958 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2959 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 2960 i.types[op].bitfield.disp8 = 0;
2961 i.types[op].bitfield.disp16 = 0;
2962 i.types[op].bitfield.disp32 = 0;
2963 i.types[op].bitfield.disp32s = 0;
2964 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 2965 }
2966 else
b300c311 2967 /* We only support 64bit displacement on constants. */
40fb9820 2968 i.types[op].bitfield.disp64 = 0;
252b5132 2969 }
29b0f896
AM		 2970}
2971
2972static int
e3bb37b5 2973match_template (void)
29b0f896
AM		 2974{
2975 /* Points to template once we've found it. */
2976 const template *t;
40fb9820 2977 i386_operand_type overlap0, overlap1, overlap2, overlap3;
29b0f896 2978 unsigned int found_reverse_match;
40fb9820
L		 2979 i386_opcode_modifier suffix_check;
2980 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 2981 int addr_prefix_disp;
a5c311ca 2982 unsigned int j;
c6fb90c8 2983 i386_cpu_flags overlap;
29b0f896 2984
f48ff2ae
L		 2985#if MAX_OPERANDS != 4
2986# error "MAX_OPERANDS must be 4."
2987#endif
2988
29b0f896 2989 found_reverse_match = 0;
539e75ad 2990 addr_prefix_disp = -1;
40fb9820
L		 2991
2992 memset (&suffix_check, 0, sizeof (suffix_check));
2993 if (i.suffix == BYTE_MNEM_SUFFIX)
2994 suffix_check.no_bsuf = 1;
2995 else if (i.suffix == WORD_MNEM_SUFFIX)
2996 suffix_check.no_wsuf = 1;
2997 else if (i.suffix == SHORT_MNEM_SUFFIX)
2998 suffix_check.no_ssuf = 1;
2999 else if (i.suffix == LONG_MNEM_SUFFIX)
3000 suffix_check.no_lsuf = 1;
3001 else if (i.suffix == QWORD_MNEM_SUFFIX)
3002 suffix_check.no_qsuf = 1;
3003 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
3004 suffix_check.no_xsuf = 1;
29b0f896 3005
45aa61fe 3006 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3007 {
539e75ad
L		 3008 addr_prefix_disp = -1;
3009
29b0f896
AM		 3010 /* Must have right number of operands. */
3011 if (i.operands != t->operands)
3012 continue;
3013
20592a94 3014 /* Check the suffix, except for some instructions in intel mode. */
40fb9820
L		 3015 if (((t->opcode_modifier.no_bsuf & suffix_check.no_bsuf)
3016 || (t->opcode_modifier.no_wsuf & suffix_check.no_wsuf)
3017 || (t->opcode_modifier.no_lsuf & suffix_check.no_lsuf)
3018 || (t->opcode_modifier.no_ssuf & suffix_check.no_ssuf)
3019 || (t->opcode_modifier.no_qsuf & suffix_check.no_qsuf)
3020 || (t->opcode_modifier.no_xsuf & suffix_check.no_xsuf))
3021 && !(intel_syntax && t->opcode_modifier.ignoresize))
29b0f896
AM		 3022 continue;
3023
a5c311ca
L		 3024 for (j = 0; j < MAX_OPERANDS; j++)
3025 operand_types [j] = t->operand_types [j];
539e75ad 3026
45aa61fe
AM		 3027 /* In general, don't allow 64-bit operands in 32-bit mode. */
3028 if (i.suffix == QWORD_MNEM_SUFFIX
3029 && flag_code != CODE_64BIT
3030 && (intel_syntax
40fb9820 3031 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3032 && !intel_float_operand (t->name))
3033 : intel_float_operand (t->name) != 2)
40fb9820
L		 3034 && ((!operand_types[0].bitfield.regmmx
3035 && !operand_types[0].bitfield.regxmm)
3036 || (!operand_types[t->operands > 1].bitfield.regmmx
3037 && !!operand_types[t->operands > 1].bitfield.regxmm))
45aa61fe
AM		 3038 && (t->base_opcode != 0x0fc7
3039 || t->extension_opcode != 1 /* cmpxchg8b */))
3040 continue;
3041
29b0f896 3042 /* Do not verify operands when there are none. */
c6fb90c8 3043 else
29b0f896 3044 {
c6fb90c8
L		 3045 overlap = cpu_flags_and (t->cpu_flags, cpu_arch_flags_not);
3046 if (!t->operands)
3047 {
3048 if (!UINTS_ALL_ZERO (overlap))
3049 continue;
3050 /* We've found a match; break out of loop. */
3051 break;
3052 }
29b0f896 3053 }
252b5132 3054
539e75ad
L		 3055 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3056 into Disp32/Disp16/Disp32 operand. */
3057 if (i.prefix[ADDR_PREFIX] != 0)
3058 {
40fb9820 3059 /* There should be only one Disp operand. */
539e75ad
L		 3060 switch (flag_code)
3061 {
3062 case CODE_16BIT:
40fb9820
L		 3063 for (j = 0; j < MAX_OPERANDS; j++)
3064 {
3065 if (operand_types[j].bitfield.disp16)
3066 {
3067 addr_prefix_disp = j;
3068 operand_types[j].bitfield.disp32 = 1;
3069 operand_types[j].bitfield.disp16 = 0;
3070 break;
3071 }
3072 }
539e75ad
L		 3073 break;
3074 case CODE_32BIT:
40fb9820
L		 3075 for (j = 0; j < MAX_OPERANDS; j++)
3076 {
3077 if (operand_types[j].bitfield.disp32)
3078 {
3079 addr_prefix_disp = j;
3080 operand_types[j].bitfield.disp32 = 0;
3081 operand_types[j].bitfield.disp16 = 1;
3082 break;
3083 }
3084 }
539e75ad
L		 3085 break;
3086 case CODE_64BIT:
40fb9820
L		 3087 for (j = 0; j < MAX_OPERANDS; j++)
3088 {
3089 if (operand_types[j].bitfield.disp64)
3090 {
3091 addr_prefix_disp = j;
3092 operand_types[j].bitfield.disp64 = 0;
3093 operand_types[j].bitfield.disp32 = 1;
3094 break;
3095 }
3096 }
539e75ad
L		 3097 break;
3098 }
539e75ad
L		 3099 }
3100
c6fb90c8 3101 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3102 switch (t->operands)
3103 {
3104 case 1:
40fb9820 3105 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3106 continue;
3107 break;
3108 case 2:
8b38ad71
L		 3109 /* xchg %eax, %eax is a special case. It is an aliase for nop
3110 only in 32bit mode and we can use opcode 0x90. In 64bit
3111 mode, we can't use 0x90 for xchg %eax, %eax since it should
3112 zero-extend %eax to %rax. */
3113 if (flag_code == CODE_64BIT
3114 && t->base_opcode == 0x90
c6fb90c8
L		 3115 && UINTS_EQUAL (i.types [0], acc32)
3116 && UINTS_EQUAL (i.types [1], acc32))
8b38ad71 3117 continue;
29b0f896 3118 case 3:
f48ff2ae 3119 case 4:
c6fb90c8 3120 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3121 if (!operand_type_match (overlap0, i.types[0])
3122 || !operand_type_match (overlap1, i.types[1])
cb712a9e 3123 /* monitor in SSE3 is a very special case. The first
708587a4 3124 register and the second register may have different
26186d74
L		 3125 sizes. The same applies to crc32 in SSE4.2. It is
3126 also true for invlpga, vmload, vmrun and vmsave in
3127 SVME. */
cb712a9e 3128 || !((t->base_opcode == 0x0f01
26186d74
L		 3129 && (t->extension_opcode == 0xc8
3130 || t->extension_opcode == 0xd8
3131 || t->extension_opcode == 0xda
3132 || t->extension_opcode == 0xdb
3133 || t->extension_opcode == 0xdf))
381d071f 3134 || t->base_opcode == 0xf20f38f1
40fb9820
L		 3135 || operand_type_register_match (overlap0, i.types[0],
3136 operand_types[0],
3137 overlap1, i.types[1],
3138 operand_types[1])))
29b0f896
AM		 3139 {
3140 /* Check if other direction is valid ... */
40fb9820 3141 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3142 continue;
3143
3144 /* Try reversing direction of operands. */
c6fb90c8
L		 3145 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3146 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3147 if (!operand_type_match (overlap0, i.types[0])
3148 || !operand_type_match (overlap1, i.types[1])
3149 || !operand_type_register_match (overlap0, i.types[0],
3150 operand_types[1],
3151 overlap1, i.types[1],
3152 operand_types[0]))
29b0f896
AM		 3153 {
3154 /* Does not match either direction. */
3155 continue;
3156 }
3157 /* found_reverse_match holds which of D or FloatDR
3158 we've found. */
40fb9820 3159 if (t->opcode_modifier.d)
8a2ed489 3160 found_reverse_match = Opcode_D;
40fb9820 3161 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3162 found_reverse_match = Opcode_FloatD;
3163 else
3164 found_reverse_match = 0;
40fb9820 3165 if (t->opcode_modifier.floatr)
8a2ed489 3166 found_reverse_match |= Opcode_FloatR;
29b0f896 3167 }
f48ff2ae 3168 else
29b0f896 3169 {
f48ff2ae 3170 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3171 switch (t->operands)
3172 {
3173 case 4:
c6fb90c8
L		 3174 overlap3 = operand_type_and (i.types[3],
3175 operand_types[3]);
d1cbb4db 3176 case 3:
c6fb90c8
L		 3177 overlap2 = operand_type_and (i.types[2],
3178 operand_types[2]);
d1cbb4db
L		 3179 break;
3180 }
29b0f896 3181
f48ff2ae
L		 3182 switch (t->operands)
3183 {
3184 case 4:
40fb9820
L		 3185 if (!operand_type_match (overlap3, i.types[3])
3186 || !operand_type_register_match (overlap2,
3187 i.types[2],
3188 operand_types[2],
3189 overlap3,
3190 i.types[3],
3191 operand_types[3]))
f48ff2ae
L		 3192 continue;
3193 case 3:
3194 /* Here we make use of the fact that there are no
3195 reverse match 3 operand instructions, and all 3
3196 operand instructions only need to be checked for
3197 register consistency between operands 2 and 3. */
40fb9820
L		 3198 if (!operand_type_match (overlap2, i.types[2])
3199 || !operand_type_register_match (overlap1,
3200 i.types[1],
3201 operand_types[1],
3202 overlap2,
3203 i.types[2],
3204 operand_types[2]))
f48ff2ae
L		 3205 continue;
3206 break;
3207 }
29b0f896 3208 }
f48ff2ae 3209 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3210 slip through to break. */
3211 }
c6fb90c8 3212 if (!UINTS_ALL_ZERO (overlap))
29b0f896
AM		 3213 {
3214 found_reverse_match = 0;
3215 continue;
3216 }
3217 /* We've found a match; break out of loop. */
3218 break;
3219 }
3220
3221 if (t == current_templates->end)
3222 {
3223 /* We found no match. */
3224 as_bad (_("suffix or operands invalid for `%s'"),
3225 current_templates->start->name);
3226 return 0;
3227 }
252b5132 3228
29b0f896
AM		 3229 if (!quiet_warnings)
3230 {
3231 if (!intel_syntax
40fb9820
L		 3232 && (i.types[0].bitfield.jumpabsolute
3233 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3234 {
3235 as_warn (_("indirect %s without `*'"), t->name);
3236 }
3237
40fb9820
L		 3238 if (t->opcode_modifier.isprefix
3239 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3240 {
3241 /* Warn them that a data or address size prefix doesn't
3242 affect assembly of the next line of code. */
3243 as_warn (_("stand-alone `%s' prefix"), t->name);
3244 }
3245 }
3246
3247 /* Copy the template we found. */
3248 i.tm = *t;
539e75ad
L		 3249
3250 if (addr_prefix_disp != -1)
3251 i.tm.operand_types[addr_prefix_disp]
3252 = operand_types[addr_prefix_disp];
3253
29b0f896
AM		 3254 if (found_reverse_match)
3255 {
3256 /* If we found a reverse match we must alter the opcode
3257 direction bit. found_reverse_match holds bits to change
3258 (different for int & float insns). */
3259
3260 i.tm.base_opcode ^= found_reverse_match;
3261
539e75ad
L		 3262 i.tm.operand_types[0] = operand_types[1];
3263 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3264 }
3265
3266 return 1;
3267}
3268
3269static int
e3bb37b5 3270check_string (void)
29b0f896 3271{
40fb9820
L		 3272 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3273 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3274 {
3275 if (i.seg[0] != NULL && i.seg[0] != &es)
3276 {
3277 as_bad (_("`%s' operand %d must use `%%es' segment"),
3278 i.tm.name,
3279 mem_op + 1);
3280 return 0;
3281 }
3282 /* There's only ever one segment override allowed per instruction.
3283 This instruction possibly has a legal segment override on the
3284 second operand, so copy the segment to where non-string
3285 instructions store it, allowing common code. */
3286 i.seg[0] = i.seg[1];
3287 }
40fb9820 3288 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3289 {
3290 if (i.seg[1] != NULL && i.seg[1] != &es)
3291 {
3292 as_bad (_("`%s' operand %d must use `%%es' segment"),
3293 i.tm.name,
3294 mem_op + 2);
3295 return 0;
3296 }
3297 }
3298 return 1;
3299}
3300
3301static int
543613e9 3302process_suffix (void)
29b0f896
AM		 3303{
3304 /* If matched instruction specifies an explicit instruction mnemonic
3305 suffix, use it. */
40fb9820
L		 3306 if (i.tm.opcode_modifier.size16)
3307 i.suffix = WORD_MNEM_SUFFIX;
3308 else if (i.tm.opcode_modifier.size32)
3309 i.suffix = LONG_MNEM_SUFFIX;
3310 else if (i.tm.opcode_modifier.size64)
3311 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 3312 else if (i.reg_operands)
3313 {
3314 /* If there's no instruction mnemonic suffix we try to invent one
3315 based on register operands. */
3316 if (!i.suffix)
3317 {
3318 /* We take i.suffix from the last register operand specified,
3319 Destination register type is more significant than source
381d071f
L		 3320 register type. crc32 in SSE4.2 prefers source register
3321 type. */
3322 if (i.tm.base_opcode == 0xf20f38f1)
3323 {
40fb9820
L		 3324 if (i.types[0].bitfield.reg16)
3325 i.suffix = WORD_MNEM_SUFFIX;
3326 else if (i.types[0].bitfield.reg32)
3327 i.suffix = LONG_MNEM_SUFFIX;
3328 else if (i.types[0].bitfield.reg64)
3329 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 3330 }
9344ff29 3331 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 3332 {
40fb9820 3333 if (i.types[0].bitfield.reg8)
20592a94
L		 3334 i.suffix = BYTE_MNEM_SUFFIX;
3335 }
381d071f
L		 3336
3337 if (!i.suffix)
3338 {
3339 int op;
3340
20592a94
L		 3341 if (i.tm.base_opcode == 0xf20f38f1
3342 || i.tm.base_opcode == 0xf20f38f0)
3343 {
3344 /* We have to know the operand size for crc32. */
3345 as_bad (_("ambiguous memory operand size for `%s`"),
3346 i.tm.name);
3347 return 0;
3348 }
3349
381d071f 3350 for (op = i.operands; --op >= 0;)
40fb9820 3351 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 3352 {
40fb9820
L		 3353 if (i.types[op].bitfield.reg8)
3354 {
3355 i.suffix = BYTE_MNEM_SUFFIX;
3356 break;
3357 }
3358 else if (i.types[op].bitfield.reg16)
3359 {
3360 i.suffix = WORD_MNEM_SUFFIX;
3361 break;
3362 }
3363 else if (i.types[op].bitfield.reg32)
3364 {
3365 i.suffix = LONG_MNEM_SUFFIX;
3366 break;
3367 }
3368 else if (i.types[op].bitfield.reg64)
3369 {
3370 i.suffix = QWORD_MNEM_SUFFIX;
3371 break;
3372 }
381d071f
L		 3373 }
3374 }
29b0f896
AM		 3375 }
3376 else if (i.suffix == BYTE_MNEM_SUFFIX)
3377 {
3378 if (!check_byte_reg ())
3379 return 0;
3380 }
3381 else if (i.suffix == LONG_MNEM_SUFFIX)
3382 {
3383 if (!check_long_reg ())
3384 return 0;
3385 }
3386 else if (i.suffix == QWORD_MNEM_SUFFIX)
3387 {
3388 if (!check_qword_reg ())
3389 return 0;
3390 }
3391 else if (i.suffix == WORD_MNEM_SUFFIX)
3392 {
3393 if (!check_word_reg ())
3394 return 0;
3395 }
40fb9820 3396 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 3397 /* Do nothing if the instruction is going to ignore the prefix. */
3398 ;
3399 else
3400 abort ();
3401 }
40fb9820 3402 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 3403 && !i.suffix
3404 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 3405 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 3406 {
3407 i.suffix = stackop_size;
3408 }
9306ca4a
JB		 3409 else if (intel_syntax
3410 && !i.suffix
40fb9820
L		 3411 && (i.tm.operand_types[0].bitfield.jumpabsolute
3412 || i.tm.opcode_modifier.jumpbyte
3413 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 3414 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3415 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 3416 {
3417 switch (flag_code)
3418 {
3419 case CODE_64BIT:
40fb9820 3420 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 3421 {
3422 i.suffix = QWORD_MNEM_SUFFIX;
3423 break;
3424 }
3425 case CODE_32BIT:
40fb9820 3426 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 3427 i.suffix = LONG_MNEM_SUFFIX;
3428 break;
3429 case CODE_16BIT:
40fb9820 3430 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 3431 i.suffix = WORD_MNEM_SUFFIX;
3432 break;
3433 }
3434 }
252b5132 3435
9306ca4a 3436 if (!i.suffix)
29b0f896 3437 {
9306ca4a
JB		 3438 if (!intel_syntax)
3439 {
40fb9820 3440 if (i.tm.opcode_modifier.w)
9306ca4a 3441 {
4eed87de
AM		 3442 as_bad (_("no instruction mnemonic suffix given and "
3443 "no register operands; can't size instruction"));
9306ca4a
JB		 3444 return 0;
3445 }
3446 }
3447 else
3448 {
40fb9820
L		 3449 unsigned int suffixes;
3450
3451 suffixes = !i.tm.opcode_modifier.no_bsuf;
3452 if (!i.tm.opcode_modifier.no_wsuf)
3453 suffixes |= 1 << 1;
3454 if (!i.tm.opcode_modifier.no_lsuf)
3455 suffixes |= 1 << 2;
3456 if (!i.tm.opcode_modifier.no_lsuf)
3457 suffixes |= 1 << 3;
3458 if (!i.tm.opcode_modifier.no_ssuf)
3459 suffixes |= 1 << 4;
3460 if (!i.tm.opcode_modifier.no_qsuf)
3461 suffixes |= 1 << 5;
3462
3463 /* There are more than suffix matches. */
3464 if (i.tm.opcode_modifier.w
9306ca4a 3465 || ((suffixes & (suffixes - 1))
40fb9820
L		 3466 && !i.tm.opcode_modifier.defaultsize
3467 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 3468 {
3469 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3470 return 0;
3471 }
3472 }
29b0f896 3473 }
252b5132 3474
9306ca4a
JB		 3475 /* Change the opcode based on the operand size given by i.suffix;
3476 We don't need to change things for byte insns. */
3477
29b0f896
AM		 3478 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
3479 {
3480 /* It's not a byte, select word/dword operation. */
40fb9820 3481 if (i.tm.opcode_modifier.w)
29b0f896 3482 {
40fb9820 3483 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 3484 i.tm.base_opcode |= 8;
3485 else
3486 i.tm.base_opcode |= 1;
3487 }
0f3f3d8b 3488
29b0f896
AM		 3489 /* Now select between word & dword operations via the operand
3490 size prefix, except for instructions that will ignore this
3491 prefix anyway. */
26186d74
L		 3492 if (i.tm.base_opcode == 0x0f01
3493 && (i.tm.extension_opcode == 0xc8
3494 || i.tm.extension_opcode == 0xd8
3495 || i.tm.extension_opcode == 0xda
3496 || i.tm.extension_opcode == 0xdb
3497 || i.tm.extension_opcode == 0xdf))
cb712a9e
L		 3498 {
3499 /* monitor in SSE3 is a very special case. The default size
3500 of AX is the size of mode. The address size override
26186d74
L		 3501 prefix will change the size of AX. It is also true for
3502 invlpga, vmload, vmrun and vmsave in SVME. */
40fb9820
L		 3503 if ((flag_code == CODE_32BIT
3504 && i.op->regs[0].reg_type.bitfield.reg16)
3505 || (flag_code != CODE_32BIT
3506 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 3507 if (!add_prefix (ADDR_PREFIX_OPCODE))
3508 return 0;
3509 }
3510 else if (i.suffix != QWORD_MNEM_SUFFIX
3511 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 3512 && !i.tm.opcode_modifier.ignoresize
3513 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 3514 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3515 || (flag_code == CODE_64BIT
40fb9820 3516 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 3517 {
3518 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 3519
40fb9820 3520 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 3521 prefix = ADDR_PREFIX_OPCODE;
252b5132 3522
29b0f896
AM		 3523 if (!add_prefix (prefix))
3524 return 0;
24eab124 3525 }
252b5132 3526
29b0f896
AM		 3527 /* Set mode64 for an operand. */
3528 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 3529 && flag_code == CODE_64BIT
40fb9820 3530 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 3531 {
3532 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 3533 need rex64. cmpxchg8b is also a special case. */
3534 if (! (i.operands == 2
3535 && i.tm.base_opcode == 0x90
3536 && i.tm.extension_opcode == None
c6fb90c8
L		 3537 && UINTS_EQUAL (i.types [0], acc64)
3538 && UINTS_EQUAL (i.types [1], acc64))
d9a5e5e5
L		 3539 && ! (i.operands == 1
3540 && i.tm.base_opcode == 0xfc7
3541 && i.tm.extension_opcode == 1
40fb9820
L		 3542 && !operand_type_check (i.types [0], reg)
3543 && operand_type_check (i.types [0], anymem)))
f6bee062 3544 i.rex |= REX_W;
46e883c5 3545 }
3e73aa7c 3546
29b0f896
AM		 3547 /* Size floating point instruction. */
3548 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 3549 if (i.tm.opcode_modifier.floatmf)
543613e9 3550 i.tm.base_opcode ^= 4;
29b0f896 3551 }
7ecd2f8b 3552
29b0f896
AM		 3553 return 1;
3554}
3e73aa7c 3555
29b0f896 3556static int
543613e9 3557check_byte_reg (void)
29b0f896
AM		 3558{
3559 int op;
543613e9 3560
29b0f896
AM		 3561 for (op = i.operands; --op >= 0;)
3562 {
3563 /* If this is an eight bit register, it's OK. If it's the 16 or
3564 32 bit version of an eight bit register, we will just use the
3565 low portion, and that's OK too. */
40fb9820 3566 if (i.types[op].bitfield.reg8)
29b0f896
AM		 3567 continue;
3568
c3ad16c0
L		 3569 /* movzx, movsx, pextrb and pinsrb should not generate this
3570 warning. */
29b0f896
AM		 3571 if (intel_syntax
3572 && (i.tm.base_opcode == 0xfb7
3573 || i.tm.base_opcode == 0xfb6
3574 || i.tm.base_opcode == 0x63
3575 || i.tm.base_opcode == 0xfbe
c3ad16c0
L		 3576 || i.tm.base_opcode == 0xfbf
3577 || i.tm.base_opcode == 0x660f3a14
3578 || i.tm.base_opcode == 0x660f3a20))
29b0f896
AM		 3579 continue;
3580
9344ff29
L		 3581 /* crc32 doesn't generate this warning. */
3582 if (i.tm.base_opcode == 0xf20f38f0)
3583 continue;
3584
40fb9820
L		 3585 if ((i.types[op].bitfield.reg16
3586 || i.types[op].bitfield.reg32
3587 || i.types[op].bitfield.reg64)
3588 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3589 {
3590 /* Prohibit these changes in the 64bit mode, since the
3591 lowering is more complicated. */
3592 if (flag_code == CODE_64BIT
40fb9820 3593 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 3594 {
2ca3ace5
L		 3595 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3596 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3597 i.suffix);
3598 return 0;
3599 }
3600#if REGISTER_WARNINGS
3601 if (!quiet_warnings
40fb9820 3602 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 3603 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3604 register_prefix,
40fb9820 3605 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 3606 ? REGNAM_AL - REGNAM_AX
3607 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 3608 register_prefix,
29b0f896
AM		 3609 i.op[op].regs->reg_name,
3610 i.suffix);
3611#endif
3612 continue;
3613 }
3614 /* Any other register is bad. */
40fb9820
L		 3615 if (i.types[op].bitfield.reg16
3616 || i.types[op].bitfield.reg32
3617 || i.types[op].bitfield.reg64
3618 || i.types[op].bitfield.regmmx
3619 || i.types[op].bitfield.regxmm
3620 || i.types[op].bitfield.sreg2
3621 || i.types[op].bitfield.sreg3
3622 || i.types[op].bitfield.control
3623 || i.types[op].bitfield.debug
3624 || i.types[op].bitfield.test
3625 || i.types[op].bitfield.floatreg
3626 || i.types[op].bitfield.floatacc)
29b0f896 3627 {
a540244d
L		 3628 as_bad (_("`%s%s' not allowed with `%s%c'"),
3629 register_prefix,
29b0f896
AM		 3630 i.op[op].regs->reg_name,
3631 i.tm.name,
3632 i.suffix);
3633 return 0;
3634 }
3635 }
3636 return 1;
3637}
3638
3639static int
e3bb37b5 3640check_long_reg (void)
29b0f896
AM		 3641{
3642 int op;
3643
3644 for (op = i.operands; --op >= 0;)
3645 /* Reject eight bit registers, except where the template requires
3646 them. (eg. movzb) */
40fb9820
L		 3647 if (i.types[op].bitfield.reg8
3648 && (i.tm.operand_types[op].bitfield.reg16
3649 || i.tm.operand_types[op].bitfield.reg32
3650 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3651 {
a540244d
L		 3652 as_bad (_("`%s%s' not allowed with `%s%c'"),
3653 register_prefix,
29b0f896
AM		 3654 i.op[op].regs->reg_name,
3655 i.tm.name,
3656 i.suffix);
3657 return 0;
3658 }
3659 /* Warn if the e prefix on a general reg is missing. */
3660 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3661 && i.types[op].bitfield.reg16
3662 && (i.tm.operand_types[op].bitfield.reg32
3663 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3664 {
3665 /* Prohibit these changes in the 64bit mode, since the
3666 lowering is more complicated. */
3667 if (flag_code == CODE_64BIT)
252b5132 3668 {
2ca3ace5
L		 3669 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3670 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3671 i.suffix);
3672 return 0;
252b5132 3673 }
29b0f896
AM		 3674#if REGISTER_WARNINGS
3675 else
a540244d
L		 3676 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3677 register_prefix,
29b0f896 3678 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 3679 register_prefix,
29b0f896
AM		 3680 i.op[op].regs->reg_name,
3681 i.suffix);
3682#endif
252b5132 3683 }
29b0f896 3684 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 3685 else if (i.types[op].bitfield.reg64
3686 && (i.tm.operand_types[op].bitfield.reg32
3687 || i.tm.operand_types[op].bitfield.acc))
252b5132 3688 {
34828aad
L		 3689 if (intel_syntax
3690 && i.tm.base_opcode == 0xf30f2d
40fb9820 3691 && !i.types[0].bitfield.regxmm)
34828aad
L		 3692 {
3693 /* cvtss2si converts DWORD memory to Reg64. We want
3694 REX byte. */
3695 i.suffix = QWORD_MNEM_SUFFIX;
3696 }
3697 else
3698 {
3699 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3700 register_prefix, i.op[op].regs->reg_name,
3701 i.suffix);
3702 return 0;
3703 }
29b0f896
AM		 3704 }
3705 return 1;
3706}
252b5132 3707
29b0f896 3708static int
e3bb37b5 3709check_qword_reg (void)
29b0f896
AM		 3710{
3711 int op;
252b5132 3712
29b0f896
AM		 3713 for (op = i.operands; --op >= 0; )
3714 /* Reject eight bit registers, except where the template requires
3715 them. (eg. movzb) */
40fb9820
L		 3716 if (i.types[op].bitfield.reg8
3717 && (i.tm.operand_types[op].bitfield.reg16
3718 || i.tm.operand_types[op].bitfield.reg32
3719 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3720 {
a540244d
L		 3721 as_bad (_("`%s%s' not allowed with `%s%c'"),
3722 register_prefix,
29b0f896
AM		 3723 i.op[op].regs->reg_name,
3724 i.tm.name,
3725 i.suffix);
3726 return 0;
3727 }
3728 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 3729 else if ((i.types[op].bitfield.reg16
3730 || i.types[op].bitfield.reg32)
3731 && (i.tm.operand_types[op].bitfield.reg32
3732 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3733 {
3734 /* Prohibit these changes in the 64bit mode, since the
3735 lowering is more complicated. */
34828aad
L		 3736 if (intel_syntax
3737 && i.tm.base_opcode == 0xf20f2d
40fb9820 3738 && !i.types[0].bitfield.regxmm)
34828aad
L		 3739 {
3740 /* cvtsd2si converts QWORD memory to Reg32. We don't want
3741 REX byte. */
3742 i.suffix = LONG_MNEM_SUFFIX;
3743 }
3744 else
3745 {
3746 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3747 register_prefix, i.op[op].regs->reg_name,
3748 i.suffix);
3749 return 0;
3750 }
252b5132 3751 }
29b0f896
AM		 3752 return 1;
3753}
252b5132 3754
29b0f896 3755static int
e3bb37b5 3756check_word_reg (void)
29b0f896
AM		 3757{
3758 int op;
3759 for (op = i.operands; --op >= 0;)
3760 /* Reject eight bit registers, except where the template requires
3761 them. (eg. movzb) */
40fb9820
L		 3762 if (i.types[op].bitfield.reg8
3763 && (i.tm.operand_types[op].bitfield.reg16
3764 || i.tm.operand_types[op].bitfield.reg32
3765 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3766 {
a540244d
L		 3767 as_bad (_("`%s%s' not allowed with `%s%c'"),
3768 register_prefix,
29b0f896
AM		 3769 i.op[op].regs->reg_name,
3770 i.tm.name,
3771 i.suffix);
3772 return 0;
3773 }
3774 /* Warn if the e prefix on a general reg is present. */
3775 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3776 && i.types[op].bitfield.reg32
3777 && (i.tm.operand_types[op].bitfield.reg16
3778 || i.tm.operand_types[op].bitfield.acc))
252b5132 3779 {
29b0f896
AM		 3780 /* Prohibit these changes in the 64bit mode, since the
3781 lowering is more complicated. */
3782 if (flag_code == CODE_64BIT)
252b5132 3783 {
2ca3ace5
L		 3784 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3785 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3786 i.suffix);
3787 return 0;
252b5132 3788 }
29b0f896
AM		 3789 else
3790#if REGISTER_WARNINGS
a540244d
L		 3791 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3792 register_prefix,
29b0f896 3793 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 3794 register_prefix,
29b0f896
AM		 3795 i.op[op].regs->reg_name,
3796 i.suffix);
3797#endif
3798 }
3799 return 1;
3800}
252b5132 3801
29b0f896 3802static int
40fb9820 3803update_imm (unsigned int j)
29b0f896 3804{
40fb9820
L		 3805 i386_operand_type overlap;
3806
c6fb90c8 3807 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
40fb9820
L		 3808 if ((overlap.bitfield.imm8
3809 || overlap.bitfield.imm8s
3810 || overlap.bitfield.imm16
3811 || overlap.bitfield.imm32
3812 || overlap.bitfield.imm32s
3813 || overlap.bitfield.imm64)
c6fb90c8
L		 3814 && !UINTS_EQUAL (overlap, imm8)
3815 && !UINTS_EQUAL (overlap, imm8s)
3816 && !UINTS_EQUAL (overlap, imm16)
3817 && !UINTS_EQUAL (overlap, imm32)
3818 && !UINTS_EQUAL (overlap, imm32s)
3819 && !UINTS_EQUAL (overlap, imm64))
29b0f896
AM		 3820 {
3821 if (i.suffix)
3822 {
40fb9820
L		 3823 i386_operand_type temp;
3824
c6fb90c8 3825 UINTS_CLEAR (temp);
40fb9820
L		 3826 if (i.suffix == BYTE_MNEM_SUFFIX)
3827 {
3828 temp.bitfield.imm8 = overlap.bitfield.imm8;
3829 temp.bitfield.imm8s = overlap.bitfield.imm8s;
3830 }
3831 else if (i.suffix == WORD_MNEM_SUFFIX)
3832 temp.bitfield.imm16 = overlap.bitfield.imm16;
3833 else if (i.suffix == QWORD_MNEM_SUFFIX)
3834 {
3835 temp.bitfield.imm64 = overlap.bitfield.imm64;
3836 temp.bitfield.imm32s = overlap.bitfield.imm32s;
3837 }
3838 else
3839 temp.bitfield.imm32 = overlap.bitfield.imm32;
3840 overlap = temp;
29b0f896 3841 }
c6fb90c8
L		 3842 else if (UINTS_EQUAL (overlap, imm16_32_32s)
3843 || UINTS_EQUAL (overlap, imm16_32)
3844 || UINTS_EQUAL (overlap, imm16_32s))
29b0f896 3845 {
c6fb90c8 3846 UINTS_CLEAR (overlap);
40fb9820
L		 3847 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3848 overlap.bitfield.imm16 = 1;
3849 else
3850 overlap.bitfield.imm32s = 1;
29b0f896 3851 }
c6fb90c8
L		 3852 if (!UINTS_EQUAL (overlap, imm8)
3853 && !UINTS_EQUAL (overlap, imm8s)
3854 && !UINTS_EQUAL (overlap, imm16)
3855 && !UINTS_EQUAL (overlap, imm32)
3856 && !UINTS_EQUAL (overlap, imm32s)
3857 && !UINTS_EQUAL (overlap, imm64))
29b0f896 3858 {
4eed87de
AM		 3859 as_bad (_("no instruction mnemonic suffix given; "
3860 "can't determine immediate size"));
29b0f896
AM		 3861 return 0;
3862 }
3863 }
40fb9820 3864 i.types[j] = overlap;
29b0f896 3865
40fb9820
L		 3866 return 1;
3867}
3868
3869static int
3870finalize_imm (void)
3871{
3872 unsigned int j;
29b0f896 3873
40fb9820
L		 3874 for (j = 0; j < 2; j++)
3875 if (update_imm (j) == 0)
3876 return 0;
3877
c6fb90c8 3878 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
40fb9820 3879 assert (operand_type_check (i.types[2], imm) == 0);
29b0f896
AM		 3880
3881 return 1;
3882}
3883
85f10a01
MM		 3884static void
3885process_drex (void)
3886{
3887 i.drex.modrm_reg = None;
3888 i.drex.modrm_regmem = None;
3889
3890 /* SSE5 4 operand instructions must have the destination the same as
3891 one of the inputs. Figure out the destination register and cache
3892 it away in the drex field, and remember which fields to use for
3893 the modrm byte. */
3894 if (i.tm.opcode_modifier.drex
3895 && i.tm.opcode_modifier.drexv
3896 && i.operands == 4)
3897 {
3898 i.tm.extension_opcode = None;
3899
3900 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
3901 if (i.types[0].bitfield.regxmm != 0
3902 && i.types[1].bitfield.regxmm != 0
3903 && i.types[2].bitfield.regxmm != 0
3904 && i.types[3].bitfield.regxmm != 0
3905 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3906 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3907 {
3908 /* Clear the arguments that are stored in drex. */
3909 UINTS_CLEAR (i.types[0]);
3910 UINTS_CLEAR (i.types[3]);
3911 i.reg_operands -= 2;
3912
3913 /* There are two different ways to encode a 4 operand
3914 instruction with all registers that uses OC1 set to
3915 0 or 1. Favor setting OC1 to 0 since this mimics the
3916 actions of other SSE5 assemblers. Use modrm encoding 2
3917 for register/register. Include the high order bit that
3918 is normally stored in the REX byte in the register
3919 field. */
3920 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
3921 i.drex.modrm_reg = 2;
3922 i.drex.modrm_regmem = 1;
3923 i.drex.reg = (i.op[3].regs->reg_num
3924 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3925 }
3926
3927 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
3928 else if (i.types[0].bitfield.regxmm != 0
3929 && i.types[1].bitfield.regxmm != 0
3930 && (i.types[2].bitfield.regxmm
3931 || operand_type_check (i.types[2], anymem))
3932 && i.types[3].bitfield.regxmm != 0
3933 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3934 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3935 {
3936 /* clear the arguments that are stored in drex */
3937 UINTS_CLEAR (i.types[0]);
3938 UINTS_CLEAR (i.types[3]);
3939 i.reg_operands -= 2;
3940
3941 /* Specify the modrm encoding for memory addressing. Include
3942 the high order bit that is normally stored in the REX byte
3943 in the register field. */
3944 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
3945 i.drex.modrm_reg = 1;
3946 i.drex.modrm_regmem = 2;
3947 i.drex.reg = (i.op[3].regs->reg_num
3948 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3949 }
3950
3951 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
3952 else if (i.types[0].bitfield.regxmm != 0
3953 && operand_type_check (i.types[1], anymem) != 0
3954 && i.types[2].bitfield.regxmm != 0
3955 && i.types[3].bitfield.regxmm != 0
3956 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3957 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3958 {
3959 /* Clear the arguments that are stored in drex. */
3960 UINTS_CLEAR (i.types[0]);
3961 UINTS_CLEAR (i.types[3]);
3962 i.reg_operands -= 2;
3963
3964 /* Specify the modrm encoding for memory addressing. Include
3965 the high order bit that is normally stored in the REX byte
3966 in the register field. */
3967 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
3968 i.drex.modrm_reg = 2;
3969 i.drex.modrm_regmem = 1;
3970 i.drex.reg = (i.op[3].regs->reg_num
3971 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3972 }
3973
3974 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
3975 else if (i.types[0].bitfield.regxmm != 0
3976 && i.types[1].bitfield.regxmm != 0
3977 && i.types[2].bitfield.regxmm != 0
3978 && i.types[3].bitfield.regxmm != 0
3979 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
3980 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
3981 {
3982 /* clear the arguments that are stored in drex */
3983 UINTS_CLEAR (i.types[2]);
3984 UINTS_CLEAR (i.types[3]);
3985 i.reg_operands -= 2;
3986
3987 /* There are two different ways to encode a 4 operand
3988 instruction with all registers that uses OC1 set to
3989 0 or 1. Favor setting OC1 to 0 since this mimics the
3990 actions of other SSE5 assemblers. Use modrm encoding
3991 2 for register/register. Include the high order bit that
3992 is normally stored in the REX byte in the register
3993 field. */
3994 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
3995 i.drex.modrm_reg = 1;
3996 i.drex.modrm_regmem = 0;
3997
3998 /* Remember the register, including the upper bits */
3999 i.drex.reg = (i.op[3].regs->reg_num
4000 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4001 }
4002
4003 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4004 else if (i.types[0].bitfield.regxmm != 0
4005 && (i.types[1].bitfield.regxmm
4006 || operand_type_check (i.types[1], anymem))
4007 && i.types[2].bitfield.regxmm != 0
4008 && i.types[3].bitfield.regxmm != 0
4009 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4010 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4011 {
4012 /* Clear the arguments that are stored in drex. */
4013 UINTS_CLEAR (i.types[2]);
4014 UINTS_CLEAR (i.types[3]);
4015 i.reg_operands -= 2;
4016
4017 /* Specify the modrm encoding and remember the register
4018 including the bits normally stored in the REX byte. */
4019 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4020 i.drex.modrm_reg = 0;
4021 i.drex.modrm_regmem = 1;
4022 i.drex.reg = (i.op[3].regs->reg_num
4023 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4024 }
4025
4026 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4027 else if (operand_type_check (i.types[0], anymem) != 0
4028 && i.types[1].bitfield.regxmm != 0
4029 && i.types[2].bitfield.regxmm != 0
4030 && i.types[3].bitfield.regxmm != 0
4031 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4032 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4033 {
4034 /* clear the arguments that are stored in drex */
4035 UINTS_CLEAR (i.types[2]);
4036 UINTS_CLEAR (i.types[3]);
4037 i.reg_operands -= 2;
4038
4039 /* Specify the modrm encoding and remember the register
4040 including the bits normally stored in the REX byte. */
4041 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4042 i.drex.modrm_reg = 1;
4043 i.drex.modrm_regmem = 0;
4044 i.drex.reg = (i.op[3].regs->reg_num
4045 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4046 }
4047
4048 else
4049 as_bad (_("Incorrect operands for the '%s' instruction"),
4050 i.tm.name);
4051 }
4052
4053 /* SSE5 instructions with the DREX byte where the only memory operand
4054 is in the 2nd argument, and the first and last xmm register must
4055 match, and is encoded in the DREX byte. */
4056 else if (i.tm.opcode_modifier.drex
4057 && !i.tm.opcode_modifier.drexv
4058 && i.operands == 4)
4059 {
4060 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4061 if (i.types[0].bitfield.regxmm != 0
4062 && (i.types[1].bitfield.regxmm
4063 || operand_type_check(i.types[1], anymem))
4064 && i.types[2].bitfield.regxmm != 0
4065 && i.types[3].bitfield.regxmm != 0
4066 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4067 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4068 {
4069 /* clear the arguments that are stored in drex */
4070 UINTS_CLEAR (i.types[0]);
4071 UINTS_CLEAR (i.types[3]);
4072 i.reg_operands -= 2;
4073
4074 /* Specify the modrm encoding and remember the register
4075 including the high bit normally stored in the REX
4076 byte. */
4077 i.drex.modrm_reg = 2;
4078 i.drex.modrm_regmem = 1;
4079 i.drex.reg = (i.op[3].regs->reg_num
4080 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4081 }
4082
4083 else
4084 as_bad (_("Incorrect operands for the '%s' instruction"),
4085 i.tm.name);
4086 }
4087
4088 /* SSE5 3 operand instructions that the result is a register, being
4089 either operand can be a memory operand, using OC0 to note which
4090 one is the memory. */
4091 else if (i.tm.opcode_modifier.drex
4092 && i.tm.opcode_modifier.drexv
4093 && i.operands == 3)
4094 {
4095 i.tm.extension_opcode = None;
4096
4097 /* Case 1: 3 operand insn, src1 = register. */
4098 if (i.types[0].bitfield.regxmm != 0
4099 && i.types[1].bitfield.regxmm != 0
4100 && i.types[2].bitfield.regxmm != 0)
4101 {
4102 /* Clear the arguments that are stored in drex. */
4103 UINTS_CLEAR (i.types[2]);
4104 i.reg_operands--;
4105
4106 /* Specify the modrm encoding and remember the register
4107 including the high bit normally stored in the REX byte. */
4108 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4109 i.drex.modrm_reg = 1;
4110 i.drex.modrm_regmem = 0;
4111 i.drex.reg = (i.op[2].regs->reg_num
4112 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4113 }
4114
4115 /* Case 2: 3 operand insn, src1 = memory. */
4116 else if (operand_type_check (i.types[0], anymem) != 0
4117 && i.types[1].bitfield.regxmm != 0
4118 && i.types[2].bitfield.regxmm != 0)
4119 {
4120 /* Clear the arguments that are stored in drex. */
4121 UINTS_CLEAR (i.types[2]);
4122 i.reg_operands--;
4123
4124 /* Specify the modrm encoding and remember the register
4125 including the high bit normally stored in the REX
4126 byte. */
4127 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4128 i.drex.modrm_reg = 1;
4129 i.drex.modrm_regmem = 0;
4130 i.drex.reg = (i.op[2].regs->reg_num
4131 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4132 }
4133
4134 /* Case 3: 3 operand insn, src2 = memory. */
4135 else if (i.types[0].bitfield.regxmm != 0
4136 && operand_type_check (i.types[1], anymem) != 0
4137 && i.types[2].bitfield.regxmm != 0)
4138 {
4139 /* Clear the arguments that are stored in drex. */
4140 UINTS_CLEAR (i.types[2]);
4141 i.reg_operands--;
4142
4143 /* Specify the modrm encoding and remember the register
4144 including the high bit normally stored in the REX byte. */
4145 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4146 i.drex.modrm_reg = 0;
4147 i.drex.modrm_regmem = 1;
4148 i.drex.reg = (i.op[2].regs->reg_num
4149 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4150 }
4151
4152 else
4153 as_bad (_("Incorrect operands for the '%s' instruction"),
4154 i.tm.name);
4155 }
4156
4157 /* SSE5 4 operand instructions that are the comparison instructions
4158 where the first operand is the immediate value of the comparison
4159 to be done. */
4160 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4161 {
4162 /* Case 1: 4 operand insn, src1 = reg/memory. */
4163 if (operand_type_check (i.types[0], imm) != 0
4164 && (i.types[1].bitfield.regxmm
4165 || operand_type_check (i.types[1], anymem))
4166 && i.types[2].bitfield.regxmm != 0
4167 && i.types[3].bitfield.regxmm != 0)
4168 {
4169 /* clear the arguments that are stored in drex */
4170 UINTS_CLEAR (i.types[3]);
4171 i.reg_operands--;
4172
4173 /* Specify the modrm encoding and remember the register
4174 including the high bit normally stored in the REX byte. */
4175 i.drex.modrm_reg = 2;
4176 i.drex.modrm_regmem = 1;
4177 i.drex.reg = (i.op[3].regs->reg_num
4178 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4179 }
4180
4181 /* Case 2: 3 operand insn with ImmExt that places the
4182 opcode_extension as an immediate argument. This is used for
4183 all of the varients of comparison that supplies the appropriate
4184 value as part of the instruction. */
4185 else if ((i.types[0].bitfield.regxmm
4186 || operand_type_check (i.types[0], anymem))
4187 && i.types[1].bitfield.regxmm != 0
4188 && i.types[2].bitfield.regxmm != 0
4189 && operand_type_check (i.types[3], imm) != 0)
4190 {
4191 /* clear the arguments that are stored in drex */
4192 UINTS_CLEAR (i.types[2]);
4193 i.reg_operands--;
4194
4195 /* Specify the modrm encoding and remember the register
4196 including the high bit normally stored in the REX byte. */
4197 i.drex.modrm_reg = 1;
4198 i.drex.modrm_regmem = 0;
4199 i.drex.reg = (i.op[2].regs->reg_num
4200 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4201 }
4202
4203 else
4204 as_bad (_("Incorrect operands for the '%s' instruction"),
4205 i.tm.name);
4206 }
4207
4208 else if (i.tm.opcode_modifier.drex
4209 || i.tm.opcode_modifier.drexv
4210 || i.tm.opcode_modifier.drexc)
4211 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4212}
4213
29b0f896 4214static int
e3bb37b5 4215process_operands (void)
29b0f896
AM		 4216{
4217 /* Default segment register this instruction will use for memory
4218 accesses. 0 means unknown. This is only for optimizing out
4219 unnecessary segment overrides. */
4220 const seg_entry *default_seg = 0;
4221
85f10a01
MM		 4222 /* Handle all of the DREX munging that SSE5 needs. */
4223 if (i.tm.opcode_modifier.drex
4224 || i.tm.opcode_modifier.drexv
4225 || i.tm.opcode_modifier.drexc)
4226 process_drex ();
4227
29b0f896
AM		 4228 /* The imul $imm, %reg instruction is converted into
4229 imul $imm, %reg, %reg, and the clr %reg instruction
4230 is converted into xor %reg, %reg. */
40fb9820 4231 if (i.tm.opcode_modifier.regkludge)
29b0f896 4232 {
40fb9820 4233 if (i.tm.cpu_flags.bitfield.cpusse4_1)
42903f7f
L		 4234 {
4235 /* The first operand in instruction blendvpd, blendvps and
4236 pblendvb in SSE4.1 is implicit and must be xmm0. */
4237 assert (i.operands == 3
4238 && i.reg_operands >= 2
c6fb90c8 4239 && UINTS_EQUAL (i.types[0], regxmm));
42903f7f
L		 4240 if (i.op[0].regs->reg_num != 0)
4241 {
4242 if (intel_syntax)
4243 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4244 i.tm.name, register_prefix);
4245 else
4246 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4247 i.tm.name, register_prefix);
4248 return 0;
4249 }
4250 i.op[0] = i.op[1];
4251 i.op[1] = i.op[2];
4252 i.types[0] = i.types[1];
4253 i.types[1] = i.types[2];
4254 i.operands--;
4255 i.reg_operands--;
4256
4257 /* We need to adjust fields in i.tm since they are used by
4258 build_modrm_byte. */
4259 i.tm.operand_types [0] = i.tm.operand_types [1];
4260 i.tm.operand_types [1] = i.tm.operand_types [2];
4261 i.tm.operands--;
4262 }
4263 else
4264 {
40fb9820
L		 4265 unsigned int first_reg_op;
4266
4267 if (operand_type_check (i.types[0], reg))
4268 first_reg_op = 0;
4269 else
4270 first_reg_op = 1;
42903f7f
L		 4271 /* Pretend we saw the extra register operand. */
4272 assert (i.reg_operands == 1
4273 && i.op[first_reg_op + 1].regs == 0);
4274 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4275 i.types[first_reg_op + 1] = i.types[first_reg_op];
4276 i.operands++;
4277 i.reg_operands++;
4278 }
29b0f896
AM		 4279 }
4280
40fb9820 4281 if (i.tm.opcode_modifier.shortform)
29b0f896 4282 {
40fb9820
L		 4283 if (i.types[0].bitfield.sreg2
4284 || i.types[0].bitfield.sreg3)
29b0f896 4285 {
4eed87de
AM		 4286 if (i.tm.base_opcode == POP_SEG_SHORT
4287 && i.op[0].regs->reg_num == 1)
29b0f896 4288 {
4eed87de
AM		 4289 as_bad (_("you can't `pop %%cs'"));
4290 return 0;
29b0f896 4291 }
4eed87de
AM		 4292 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4293 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4294 i.rex |= REX_B;
4eed87de
AM		 4295 }
4296 else
4297 {
85f10a01
MM		 4298 /* The register or float register operand is in operand
4299 0 or 1. */
40fb9820
L		 4300 unsigned int op;
4301
4302 if (i.types[0].bitfield.floatreg
4303 || operand_type_check (i.types[0], reg))
4304 op = 0;
4305 else
4306 op = 1;
4eed87de
AM		 4307 /* Register goes in low 3 bits of opcode. */
4308 i.tm.base_opcode |= i.op[op].regs->reg_num;
4309 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4310 i.rex |= REX_B;
40fb9820 4311 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4312 {
4eed87de
AM		 4313 /* Warn about some common errors, but press on regardless.
4314 The first case can be generated by gcc (<= 2.8.1). */
4315 if (i.operands == 2)
4316 {
4317 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 4318 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4319 register_prefix, i.op[1].regs->reg_name,
4320 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 4321 }
4322 else
4323 {
4324 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4325 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4326 register_prefix, i.op[0].regs->reg_name);
4eed87de 4327 }
29b0f896
AM		 4328 }
4329 }
4330 }
40fb9820 4331 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4332 {
4333 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4334 must be put into the modrm byte). Now, we make the modrm and
4335 index base bytes based on all the info we've collected. */
29b0f896
AM		 4336
4337 default_seg = build_modrm_byte ();
4338 }
8a2ed489 4339 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4340 {
4341 default_seg = &ds;
4342 }
40fb9820 4343 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4344 {
4345 /* For the string instructions that allow a segment override
4346 on one of their operands, the default segment is ds. */
4347 default_seg = &ds;
4348 }
4349
75178d9d
L		 4350 if (i.tm.base_opcode == 0x8d /* lea */
4351 && i.seg[0]
4352 && !quiet_warnings)
30123838 4353 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 4354
4355 /* If a segment was explicitly specified, and the specified segment
4356 is not the default, use an opcode prefix to select it. If we
4357 never figured out what the default segment is, then default_seg
4358 will be zero at this point, and the specified segment prefix will
4359 always be used. */
29b0f896
AM		 4360 if ((i.seg[0]) && (i.seg[0] != default_seg))
4361 {
4362 if (!add_prefix (i.seg[0]->seg_prefix))
4363 return 0;
4364 }
4365 return 1;
4366}
4367
4368static const seg_entry *
e3bb37b5 4369build_modrm_byte (void)
29b0f896
AM		 4370{
4371 const seg_entry *default_seg = 0;
4372
85f10a01
MM		 4373 /* SSE5 4 operand instructions are encoded in such a way that one of
4374 the inputs must match the destination register. Process_drex hides
4375 the 3rd argument in the drex field, so that by the time we get
4376 here, it looks to GAS as if this is a 2 operand instruction. */
4377 if ((i.tm.opcode_modifier.drex
4378 || i.tm.opcode_modifier.drexv
b5016f89 4379 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4380 && i.reg_operands == 2)
4381 {
4382 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
4383 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
4384
4385 i.rm.reg = reg->reg_num;
4386 i.rm.regmem = regmem->reg_num;
4387 i.rm.mode = 3;
4388 if ((reg->reg_flags & RegRex) != 0)
4389 i.rex |= REX_R;
4390 if ((regmem->reg_flags & RegRex) != 0)
4391 i.rex |= REX_B;
4392 }
4393
29b0f896
AM		 4394 /* i.reg_operands MUST be the number of real register operands;
4395 implicit registers do not count. */
85f10a01 4396 else if (i.reg_operands == 2)
29b0f896
AM		 4397 {
4398 unsigned int source, dest;
cab737b9
L		 4399
4400 switch (i.operands)
4401 {
4402 case 2:
4403 source = 0;
4404 break;
4405 case 3:
c81128dc
L		 4406 /* When there are 3 operands, one of them may be immediate,
4407 which may be the first or the last operand. Otherwise,
4408 the first operand must be shift count register (cl). */
4409 assert (i.imm_operands == 1
4410 || (i.imm_operands == 0
40fb9820
L		 4411 && i.types[0].bitfield.shiftcount));
4412 if (operand_type_check (i.types[0], imm)
4413 || i.types[0].bitfield.shiftcount)
4414 source = 1;
4415 else
4416 source = 0;
cab737b9
L		 4417 break;
4418 case 4:
4419 /* When there are 4 operands, the first two must be immediate
4420 operands. The source operand will be the 3rd one. */
4421 assert (i.imm_operands == 2
40fb9820
L		 4422 && operand_type_check (i.types[0], imm)
4423 && operand_type_check (i.types[1], imm));
cab737b9
L		 4424 source = 2;
4425 break;
4426 default:
4427 abort ();
4428 }
4429
29b0f896
AM		 4430 dest = source + 1;
4431
4432 i.rm.mode = 3;
4433 /* One of the register operands will be encoded in the i.tm.reg
4434 field, the other in the combined i.tm.mode and i.tm.regmem
4435 fields. If no form of this instruction supports a memory
4436 destination operand, then we assume the source operand may
4437 sometimes be a memory operand and so we need to store the
4438 destination in the i.rm.reg field. */
40fb9820
L		 4439 if (!i.tm.operand_types[dest].bitfield.regmem
4440 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 4441 {
4442 i.rm.reg = i.op[dest].regs->reg_num;
4443 i.rm.regmem = i.op[source].regs->reg_num;
4444 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4445 i.rex |= REX_R;
29b0f896 4446 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4447 i.rex |= REX_B;
29b0f896
AM		 4448 }
4449 else
4450 {
4451 i.rm.reg = i.op[source].regs->reg_num;
4452 i.rm.regmem = i.op[dest].regs->reg_num;
4453 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4454 i.rex |= REX_B;
29b0f896 4455 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4456 i.rex |= REX_R;
29b0f896 4457 }
161a04f6 4458 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 4459 {
40fb9820
L		 4460 if (!i.types[0].bitfield.control
4461 && !i.types[1].bitfield.control)
c4a530c5 4462 abort ();
161a04f6 4463 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 4464 add_prefix (LOCK_PREFIX_OPCODE);
4465 }
29b0f896
AM		 4466 }
4467 else
4468 { /* If it's not 2 reg operands... */
4469 if (i.mem_operands)
4470 {
4471 unsigned int fake_zero_displacement = 0;
99018f42 4472 unsigned int op;
4eed87de 4473
85f10a01
MM		 4474 /* This has been precalculated for SSE5 instructions
4475 that have a DREX field earlier in process_drex. */
b5016f89
L		 4476 if (i.tm.opcode_modifier.drex
4477 || i.tm.opcode_modifier.drexv
4478 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4479 op = i.drex.modrm_regmem;
4480 else
4481 {
c0209578
L		 4482 for (op = 0; op < i.operands; op++)
4483 if (operand_type_check (i.types[op], anymem))
4484 break;
4485 assert (op < i.operands);
85f10a01 4486 }
29b0f896
AM		 4487
4488 default_seg = &ds;
4489
4490 if (i.base_reg == 0)
4491 {
4492 i.rm.mode = 0;
4493 if (!i.disp_operands)
4494 fake_zero_displacement = 1;
4495 if (i.index_reg == 0)
4496 {
4497 /* Operand is just <disp> */
20f0a1fc 4498 if (flag_code == CODE_64BIT)
29b0f896
AM		 4499 {
4500 /* 64bit mode overwrites the 32bit absolute
4501 addressing by RIP relative addressing and
4502 absolute addressing is encoded by one of the
4503 redundant SIB forms. */
4504 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4505 i.sib.base = NO_BASE_REGISTER;
4506 i.sib.index = NO_INDEX_REGISTER;
fc225355 4507 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 4508 ? disp32s : disp32);
20f0a1fc 4509 }
fc225355
L		 4510 else if ((flag_code == CODE_16BIT)
4511 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 4512 {
4513 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 4514 i.types[op] = disp16;
20f0a1fc
NC		 4515 }
4516 else
4517 {
4518 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 4519 i.types[op] = disp32;
29b0f896
AM		 4520 }
4521 }
4522 else /* !i.base_reg && i.index_reg */
4523 {
db51cc60
L		 4524 if (i.index_reg->reg_num == RegEiz
4525 || i.index_reg->reg_num == RegRiz)
4526 i.sib.index = NO_INDEX_REGISTER;
4527 else
4528 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 4529 i.sib.base = NO_BASE_REGISTER;
4530 i.sib.scale = i.log2_scale_factor;
4531 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 4532 i.types[op].bitfield.disp8 = 0;
4533 i.types[op].bitfield.disp16 = 0;
4534 i.types[op].bitfield.disp64 = 0;
29b0f896 4535 if (flag_code != CODE_64BIT)
40fb9820
L		 4536 {
4537 /* Must be 32 bit */
4538 i.types[op].bitfield.disp32 = 1;
4539 i.types[op].bitfield.disp32s = 0;
4540 }
29b0f896 4541 else
40fb9820
L		 4542 {
4543 i.types[op].bitfield.disp32 = 0;
4544 i.types[op].bitfield.disp32s = 1;
4545 }
29b0f896 4546 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4547 i.rex |= REX_X;
29b0f896
AM		 4548 }
4549 }
4550 /* RIP addressing for 64bit mode. */
20e192ab 4551 else if (i.base_reg->reg_num == RegRip)
29b0f896
AM		 4552 {
4553 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 4554 i.types[op].bitfield.disp8 = 0;
4555 i.types[op].bitfield.disp16 = 0;
4556 i.types[op].bitfield.disp32 = 0;
4557 i.types[op].bitfield.disp32s = 1;
4558 i.types[op].bitfield.disp64 = 0;
71903a11 4559 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 4560 if (! i.disp_operands)
4561 fake_zero_displacement = 1;
29b0f896 4562 }
40fb9820 4563 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 4564 {
4565 switch (i.base_reg->reg_num)
4566 {
4567 case 3: /* (%bx) */
4568 if (i.index_reg == 0)
4569 i.rm.regmem = 7;
4570 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4571 i.rm.regmem = i.index_reg->reg_num - 6;
4572 break;
4573 case 5: /* (%bp) */
4574 default_seg = &ss;
4575 if (i.index_reg == 0)
4576 {
4577 i.rm.regmem = 6;
40fb9820 4578 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 4579 {
4580 /* fake (%bp) into 0(%bp) */
40fb9820 4581 i.types[op].bitfield.disp8 = 1;
252b5132 4582 fake_zero_displacement = 1;
29b0f896
AM		 4583 }
4584 }
4585 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4586 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4587 break;
4588 default: /* (%si) -> 4 or (%di) -> 5 */
4589 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4590 }
4591 i.rm.mode = mode_from_disp_size (i.types[op]);
4592 }
4593 else /* i.base_reg and 32/64 bit mode */
4594 {
4595 if (flag_code == CODE_64BIT
40fb9820
L		 4596 && operand_type_check (i.types[op], disp))
4597 {
4598 i386_operand_type temp;
c6fb90c8 4599 UINTS_CLEAR (temp);
40fb9820
L		 4600 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4601 i.types[op] = temp;
4602 if (i.prefix[ADDR_PREFIX] == 0)
4603 i.types[op].bitfield.disp32s = 1;
4604 else
4605 i.types[op].bitfield.disp32 = 1;
4606 }
20f0a1fc 4607
29b0f896
AM		 4608 i.rm.regmem = i.base_reg->reg_num;
4609 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 4610 i.rex |= REX_B;
29b0f896
AM		 4611 i.sib.base = i.base_reg->reg_num;
4612 /* x86-64 ignores REX prefix bit here to avoid decoder
4613 complications. */
4614 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4615 {
4616 default_seg = &ss;
4617 if (i.disp_operands == 0)
4618 {
4619 fake_zero_displacement = 1;
40fb9820 4620 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 4621 }
4622 }
4623 else if (i.base_reg->reg_num == ESP_REG_NUM)
4624 {
4625 default_seg = &ss;
4626 }
4627 i.sib.scale = i.log2_scale_factor;
4628 if (i.index_reg == 0)
4629 {
4630 /* <disp>(%esp) becomes two byte modrm with no index
4631 register. We've already stored the code for esp
4632 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4633 Any base register besides %esp will not use the
4634 extra modrm byte. */
4635 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 4636 }
4637 else
4638 {
db51cc60
L		 4639 if (i.index_reg->reg_num == RegEiz
4640 || i.index_reg->reg_num == RegRiz)
4641 i.sib.index = NO_INDEX_REGISTER;
4642 else
4643 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 4644 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4645 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4646 i.rex |= REX_X;
29b0f896 4647 }
67a4f2b7
AO		 4648
4649 if (i.disp_operands
4650 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4651 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4652 i.rm.mode = 0;
4653 else
4654 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 4655 }
252b5132 4656
29b0f896
AM		 4657 if (fake_zero_displacement)
4658 {
4659 /* Fakes a zero displacement assuming that i.types[op]
4660 holds the correct displacement size. */
4661 expressionS *exp;
4662
4663 assert (i.op[op].disps == 0);
4664 exp = &disp_expressions[i.disp_operands++];
4665 i.op[op].disps = exp;
4666 exp->X_op = O_constant;
4667 exp->X_add_number = 0;
4668 exp->X_add_symbol = (symbolS *) 0;
4669 exp->X_op_symbol = (symbolS *) 0;
4670 }
4671 }
252b5132 4672
29b0f896
AM		 4673 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4674 (if any) based on i.tm.extension_opcode. Again, we must be
4675 careful to make sure that segment/control/debug/test/MMX
4676 registers are coded into the i.rm.reg field. */
4677 if (i.reg_operands)
4678 {
99018f42
L		 4679 unsigned int op;
4680
85f10a01
MM		 4681 /* This has been precalculated for SSE5 instructions
4682 that have a DREX field earlier in process_drex. */
b5016f89
L		 4683 if (i.tm.opcode_modifier.drex
4684 || i.tm.opcode_modifier.drexv
4685 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4686 {
4687 op = i.drex.modrm_reg;
4688 i.rm.reg = i.op[op].regs->reg_num;
4689 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4690 i.rex |= REX_R;
4691 }
4692 else
4693 {
c0209578
L		 4694 for (op = 0; op < i.operands; op++)
4695 if (i.types[op].bitfield.reg8
4696 || i.types[op].bitfield.reg16
4697 || i.types[op].bitfield.reg32
4698 || i.types[op].bitfield.reg64
4699 || i.types[op].bitfield.regmmx
4700 || i.types[op].bitfield.regxmm
4701 || i.types[op].bitfield.sreg2
4702 || i.types[op].bitfield.sreg3
4703 || i.types[op].bitfield.control
4704 || i.types[op].bitfield.debug
4705 || i.types[op].bitfield.test)
4706 break;
4707
4708 assert (op < i.operands);
99018f42 4709
85f10a01
MM		 4710 /* If there is an extension opcode to put here, the
4711 register number must be put into the regmem field. */
c0209578
L		 4712 if (i.tm.extension_opcode != None)
4713 {
4714 i.rm.regmem = i.op[op].regs->reg_num;
4715 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4716 i.rex |= REX_B;
4717 }
4718 else
4719 {
4720 i.rm.reg = i.op[op].regs->reg_num;
4721 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4722 i.rex |= REX_R;
4723 }
85f10a01 4724 }
252b5132 4725
29b0f896
AM		 4726 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4727 must set it to 3 to indicate this is a register operand
4728 in the regmem field. */
4729 if (!i.mem_operands)
4730 i.rm.mode = 3;
4731 }
252b5132 4732
29b0f896 4733 /* Fill in i.rm.reg field with extension opcode (if any). */
85f10a01
MM		 4734 if (i.tm.extension_opcode != None
4735 && !(i.tm.opcode_modifier.drex
4736 || i.tm.opcode_modifier.drexv
4737 || i.tm.opcode_modifier.drexc))
29b0f896
AM		 4738 i.rm.reg = i.tm.extension_opcode;
4739 }
4740 return default_seg;
4741}
252b5132 4742
29b0f896 4743static void
e3bb37b5 4744output_branch (void)
29b0f896
AM		 4745{
4746 char *p;
4747 int code16;
4748 int prefix;
4749 relax_substateT subtype;
4750 symbolS *sym;
4751 offsetT off;
4752
4753 code16 = 0;
4754 if (flag_code == CODE_16BIT)
4755 code16 = CODE16;
4756
4757 prefix = 0;
4758 if (i.prefix[DATA_PREFIX] != 0)
252b5132 4759 {
29b0f896
AM		 4760 prefix = 1;
4761 i.prefixes -= 1;
4762 code16 ^= CODE16;
252b5132 4763 }
29b0f896
AM		 4764 /* Pentium4 branch hints. */
4765 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4766 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 4767 {
29b0f896
AM		 4768 prefix++;
4769 i.prefixes--;
4770 }
4771 if (i.prefix[REX_PREFIX] != 0)
4772 {
4773 prefix++;
4774 i.prefixes--;
2f66722d
AM		 4775 }
4776
29b0f896
AM		 4777 if (i.prefixes != 0 && !intel_syntax)
4778 as_warn (_("skipping prefixes on this instruction"));
4779
4780 /* It's always a symbol; End frag & setup for relax.
4781 Make sure there is enough room in this frag for the largest
4782 instruction we may generate in md_convert_frag. This is 2
4783 bytes for the opcode and room for the prefix and largest
4784 displacement. */
4785 frag_grow (prefix + 2 + 4);
4786 /* Prefix and 1 opcode byte go in fr_fix. */
4787 p = frag_more (prefix + 1);
4788 if (i.prefix[DATA_PREFIX] != 0)
4789 *p++ = DATA_PREFIX_OPCODE;
4790 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
4791 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
4792 *p++ = i.prefix[SEG_PREFIX];
4793 if (i.prefix[REX_PREFIX] != 0)
4794 *p++ = i.prefix[REX_PREFIX];
4795 *p = i.tm.base_opcode;
4796
4797 if ((unsigned char) *p == JUMP_PC_RELATIVE)
4798 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 4799 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 4800 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
4801 else
4802 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
4803 subtype |= code16;
3e73aa7c 4804
29b0f896
AM		 4805 sym = i.op[0].disps->X_add_symbol;
4806 off = i.op[0].disps->X_add_number;
3e73aa7c 4807
29b0f896
AM		 4808 if (i.op[0].disps->X_op != O_constant
4809 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 4810 {
29b0f896
AM		 4811 /* Handle complex expressions. */
4812 sym = make_expr_symbol (i.op[0].disps);
4813 off = 0;
4814 }
3e73aa7c 4815
29b0f896
AM		 4816 /* 1 possible extra opcode + 4 byte displacement go in var part.
4817 Pass reloc in fr_var. */
4818 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
4819}
3e73aa7c 4820
29b0f896 4821static void
e3bb37b5 4822output_jump (void)
29b0f896
AM		 4823{
4824 char *p;
4825 int size;
3e02c1cc 4826 fixS *fixP;
29b0f896 4827
40fb9820 4828 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 4829 {
4830 /* This is a loop or jecxz type instruction. */
4831 size = 1;
4832 if (i.prefix[ADDR_PREFIX] != 0)
4833 {
4834 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
4835 i.prefixes -= 1;
4836 }
4837 /* Pentium4 branch hints. */
4838 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4839 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
4840 {
4841 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
4842 i.prefixes--;
3e73aa7c
JH		 4843 }
4844 }
29b0f896
AM		 4845 else
4846 {
4847 int code16;
3e73aa7c 4848
29b0f896
AM		 4849 code16 = 0;
4850 if (flag_code == CODE_16BIT)
4851 code16 = CODE16;
3e73aa7c 4852
29b0f896
AM		 4853 if (i.prefix[DATA_PREFIX] != 0)
4854 {
4855 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
4856 i.prefixes -= 1;
4857 code16 ^= CODE16;
4858 }
252b5132 4859
29b0f896
AM		 4860 size = 4;
4861 if (code16)
4862 size = 2;
4863 }
9fcc94b6 4864
29b0f896
AM		 4865 if (i.prefix[REX_PREFIX] != 0)
4866 {
4867 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
4868 i.prefixes -= 1;
4869 }
252b5132 4870
29b0f896
AM		 4871 if (i.prefixes != 0 && !intel_syntax)
4872 as_warn (_("skipping prefixes on this instruction"));
e0890092 4873
29b0f896
AM		 4874 p = frag_more (1 + size);
4875 *p++ = i.tm.base_opcode;
e0890092 4876
3e02c1cc
AM		 4877 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4878 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
4879
4880 /* All jumps handled here are signed, but don't use a signed limit
4881 check for 32 and 16 bit jumps as we want to allow wrap around at
4882 4G and 64k respectively. */
4883 if (size == 1)
4884 fixP->fx_signed = 1;
29b0f896 4885}
e0890092 4886
29b0f896 4887static void
e3bb37b5 4888output_interseg_jump (void)
29b0f896
AM		 4889{
4890 char *p;
4891 int size;
4892 int prefix;
4893 int code16;
252b5132 4894
29b0f896
AM		 4895 code16 = 0;
4896 if (flag_code == CODE_16BIT)
4897 code16 = CODE16;
a217f122 4898
29b0f896
AM		 4899 prefix = 0;
4900 if (i.prefix[DATA_PREFIX] != 0)
4901 {
4902 prefix = 1;
4903 i.prefixes -= 1;
4904 code16 ^= CODE16;
4905 }
4906 if (i.prefix[REX_PREFIX] != 0)
4907 {
4908 prefix++;
4909 i.prefixes -= 1;
4910 }
252b5132 4911
29b0f896
AM		 4912 size = 4;
4913 if (code16)
4914 size = 2;
252b5132 4915
29b0f896
AM		 4916 if (i.prefixes != 0 && !intel_syntax)
4917 as_warn (_("skipping prefixes on this instruction"));
252b5132 4918
29b0f896
AM		 4919 /* 1 opcode; 2 segment; offset */
4920 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 4921
29b0f896
AM		 4922 if (i.prefix[DATA_PREFIX] != 0)
4923 *p++ = DATA_PREFIX_OPCODE;
252b5132 4924
29b0f896
AM		 4925 if (i.prefix[REX_PREFIX] != 0)
4926 *p++ = i.prefix[REX_PREFIX];
252b5132 4927
29b0f896
AM		 4928 *p++ = i.tm.base_opcode;
4929 if (i.op[1].imms->X_op == O_constant)
4930 {
4931 offsetT n = i.op[1].imms->X_add_number;
252b5132 4932
29b0f896
AM		 4933 if (size == 2
4934 && !fits_in_unsigned_word (n)
4935 && !fits_in_signed_word (n))
4936 {
4937 as_bad (_("16-bit jump out of range"));
4938 return;
4939 }
4940 md_number_to_chars (p, n, size);
4941 }
4942 else
4943 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4944 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
4945 if (i.op[0].imms->X_op != O_constant)
4946 as_bad (_("can't handle non absolute segment in `%s'"),
4947 i.tm.name);
4948 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
4949}
a217f122 4950
29b0f896 4951static void
e3bb37b5 4952output_insn (void)
29b0f896 4953{
2bbd9c25
JJ		 4954 fragS *insn_start_frag;
4955 offsetT insn_start_off;
4956
29b0f896
AM		 4957 /* Tie dwarf2 debug info to the address at the start of the insn.
4958 We can't do this after the insn has been output as the current
4959 frag may have been closed off. eg. by frag_var. */
4960 dwarf2_emit_insn (0);
4961
2bbd9c25
JJ		 4962 insn_start_frag = frag_now;
4963 insn_start_off = frag_now_fix ();
4964
29b0f896 4965 /* Output jumps. */
40fb9820 4966 if (i.tm.opcode_modifier.jump)
29b0f896 4967 output_branch ();
40fb9820
L		 4968 else if (i.tm.opcode_modifier.jumpbyte
4969 || i.tm.opcode_modifier.jumpdword)
29b0f896 4970 output_jump ();
40fb9820 4971 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 4972 output_interseg_jump ();
4973 else
4974 {
4975 /* Output normal instructions here. */
4976 char *p;
4977 unsigned char *q;
331d2d0d 4978 unsigned int prefix;
4dffcebc
L		 4979
4980 switch (i.tm.opcode_length)
bc4bd9ab 4981 {
4dffcebc 4982 case 3:
331d2d0d
L		 4983 if (i.tm.base_opcode & 0xff000000)
4984 {
4985 prefix = (i.tm.base_opcode >> 24) & 0xff;
4986 goto check_prefix;
4987 }
4dffcebc
L		 4988 break;
4989 case 2:
4990 if ((i.tm.base_opcode & 0xff0000) != 0)
bc4bd9ab 4991 {
4dffcebc
L		 4992 prefix = (i.tm.base_opcode >> 16) & 0xff;
4993 if (i.tm.cpu_flags.bitfield.cpupadlock)
4994 {
4995check_prefix:
4996 if (prefix != REPE_PREFIX_OPCODE
4997 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
4998 add_prefix (prefix);
4999 }
5000 else
bc4bd9ab
MK		 5001 add_prefix (prefix);
5002 }
4dffcebc
L		 5003 break;
5004 case 1:
5005 break;
5006 default:
5007 abort ();
0f10071e 5008 }
252b5132 5009
29b0f896
AM		 5010 /* The prefix bytes. */
5011 for (q = i.prefix;
5012 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
5013 q++)
5014 {
5015 if (*q)
5016 {
5017 p = frag_more (1);
5018 md_number_to_chars (p, (valueT) *q, 1);
5019 }
5020 }
252b5132 5021
29b0f896 5022 /* Now the opcode; be careful about word order here! */
4dffcebc 5023 if (i.tm.opcode_length == 1)
29b0f896
AM		 5024 {
5025 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5026 }
5027 else
5028 {
4dffcebc 5029 switch (i.tm.opcode_length)
331d2d0d 5030 {
4dffcebc 5031 case 3:
331d2d0d
L		 5032 p = frag_more (3);
5033 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5034 break;
5035 case 2:
5036 p = frag_more (2);
5037 break;
5038 default:
5039 abort ();
5040 break;
331d2d0d 5041 }
0f10071e 5042
29b0f896
AM		 5043 /* Put out high byte first: can't use md_number_to_chars! */
5044 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5045 *p = i.tm.base_opcode & 0xff;
85f10a01
MM		 5046
5047 /* On SSE5, encode the OC1 bit in the DREX field if this
5048 encoding has multiple formats. */
5049 if (i.tm.opcode_modifier.drex
5050 && i.tm.opcode_modifier.drexv
5051 && DREX_OC1 (i.tm.extension_opcode))
5052 *p |= DREX_OC1_MASK;
29b0f896 5053 }
3e73aa7c 5054
29b0f896 5055 /* Now the modrm byte and sib byte (if present). */
40fb9820 5056 if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5057 {
5058 p = frag_more (1);
5059 md_number_to_chars (p,
5060 (valueT) (i.rm.regmem << 0
5061 | i.rm.reg << 3
5062 | i.rm.mode << 6),
5063 1);
5064 /* If i.rm.regmem == ESP (4)
5065 && i.rm.mode != (Register mode)
5066 && not 16 bit
5067 ==> need second modrm byte. */
5068 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5069 && i.rm.mode != 3
40fb9820 5070 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
29b0f896
AM		 5071 {
5072 p = frag_more (1);
5073 md_number_to_chars (p,
5074 (valueT) (i.sib.base << 0
5075 | i.sib.index << 3
5076 | i.sib.scale << 6),
5077 1);
5078 }
5079 }
3e73aa7c 5080
85f10a01
MM		 5081 /* Write the DREX byte if needed. */
5082 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5083 {
5084 p = frag_more (1);
5085 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5086
5087 /* Encode the OC0 bit if this encoding has multiple
5088 formats. */
5089 if ((i.tm.opcode_modifier.drex
5090 || i.tm.opcode_modifier.drexv)
5091 && DREX_OC0 (i.tm.extension_opcode))
5092 *p |= DREX_OC0_MASK;
5093 }
5094
29b0f896 5095 if (i.disp_operands)
2bbd9c25 5096 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5097
29b0f896 5098 if (i.imm_operands)
2bbd9c25 5099 output_imm (insn_start_frag, insn_start_off);
29b0f896 5100 }
252b5132 5101
29b0f896
AM		 5102#ifdef DEBUG386
5103 if (flag_debug)
5104 {
7b81dfbb 5105 pi ("" /*line*/, &i);
29b0f896
AM		 5106 }
5107#endif /* DEBUG386 */
5108}
252b5132 5109
e205caa7
L		 5110/* Return the size of the displacement operand N. */
5111
5112static int
5113disp_size (unsigned int n)
5114{
5115 int size = 4;
40fb9820
L		 5116 if (i.types[n].bitfield.disp64)
5117 size = 8;
5118 else if (i.types[n].bitfield.disp8)
5119 size = 1;
5120 else if (i.types[n].bitfield.disp16)
5121 size = 2;
e205caa7
L		 5122 return size;
5123}
5124
5125/* Return the size of the immediate operand N. */
5126
5127static int
5128imm_size (unsigned int n)
5129{
5130 int size = 4;
40fb9820
L		 5131 if (i.types[n].bitfield.imm64)
5132 size = 8;
5133 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5134 size = 1;
5135 else if (i.types[n].bitfield.imm16)
5136 size = 2;
e205caa7
L		 5137 return size;
5138}
5139
29b0f896 5140static void
64e74474 5141output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5142{
5143 char *p;
5144 unsigned int n;
252b5132 5145
29b0f896
AM		 5146 for (n = 0; n < i.operands; n++)
5147 {
40fb9820 5148 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 5149 {
5150 if (i.op[n].disps->X_op == O_constant)
5151 {
e205caa7 5152 int size = disp_size (n);
29b0f896 5153 offsetT val;
252b5132 5154
29b0f896
AM		 5155 val = offset_in_range (i.op[n].disps->X_add_number,
5156 size);
5157 p = frag_more (size);
5158 md_number_to_chars (p, val, size);
5159 }
5160 else
5161 {
f86103b7 5162 enum bfd_reloc_code_real reloc_type;
e205caa7 5163 int size = disp_size (n);
40fb9820 5164 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 5165 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5166
e205caa7 5167 /* We can't have 8 bit displacement here. */
40fb9820 5168 assert (!i.types[n].bitfield.disp8);
e205caa7 5169
29b0f896
AM		 5170 /* The PC relative address is computed relative
5171 to the instruction boundary, so in case immediate
5172 fields follows, we need to adjust the value. */
5173 if (pcrel && i.imm_operands)
5174 {
29b0f896 5175 unsigned int n1;
e205caa7 5176 int sz = 0;
252b5132 5177
29b0f896 5178 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 5179 if (operand_type_check (i.types[n1], imm))
252b5132 5180 {
e205caa7
L		 5181 /* Only one immediate is allowed for PC
5182 relative address. */
5183 assert (sz == 0);
5184 sz = imm_size (n1);
5185 i.op[n].disps->X_add_number -= sz;
252b5132 5186 }
29b0f896 5187 /* We should find the immediate. */
e205caa7 5188 assert (sz != 0);
29b0f896 5189 }
520dc8e8 5190
29b0f896 5191 p = frag_more (size);
2bbd9c25 5192 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 5193 if (GOT_symbol
2bbd9c25 5194 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 5195 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5196 || reloc_type == BFD_RELOC_X86_64_32S
5197 || (reloc_type == BFD_RELOC_64
5198 && object_64bit))
d6ab8113
JB		 5199 && (i.op[n].disps->X_op == O_symbol
5200 || (i.op[n].disps->X_op == O_add
5201 && ((symbol_get_value_expression
5202 (i.op[n].disps->X_op_symbol)->X_op)
5203 == O_subtract))))
5204 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 5205 {
5206 offsetT add;
5207
5208 if (insn_start_frag == frag_now)
5209 add = (p - frag_now->fr_literal) - insn_start_off;
5210 else
5211 {
5212 fragS *fr;
5213
5214 add = insn_start_frag->fr_fix - insn_start_off;
5215 for (fr = insn_start_frag->fr_next;
5216 fr && fr != frag_now; fr = fr->fr_next)
5217 add += fr->fr_fix;
5218 add += p - frag_now->fr_literal;
5219 }
5220
4fa24527 5221 if (!object_64bit)
7b81dfbb
AJ		 5222 {
5223 reloc_type = BFD_RELOC_386_GOTPC;
5224 i.op[n].imms->X_add_number += add;
5225 }
5226 else if (reloc_type == BFD_RELOC_64)
5227 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 5228 else
7b81dfbb
AJ		 5229 /* Don't do the adjustment for x86-64, as there
5230 the pcrel addressing is relative to the _next_
5231 insn, and that is taken care of in other code. */
d6ab8113 5232 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 5233 }
062cd5e7 5234 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 5235 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 5236 }
5237 }
5238 }
5239}
252b5132 5240
29b0f896 5241static void
64e74474 5242output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5243{
5244 char *p;
5245 unsigned int n;
252b5132 5246
29b0f896
AM		 5247 for (n = 0; n < i.operands; n++)
5248 {
40fb9820 5249 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 5250 {
5251 if (i.op[n].imms->X_op == O_constant)
5252 {
e205caa7 5253 int size = imm_size (n);
29b0f896 5254 offsetT val;
b4cac588 5255
29b0f896
AM		 5256 val = offset_in_range (i.op[n].imms->X_add_number,
5257 size);
5258 p = frag_more (size);
5259 md_number_to_chars (p, val, size);
5260 }
5261 else
5262 {
5263 /* Not absolute_section.
5264 Need a 32-bit fixup (don't support 8bit
5265 non-absolute imms). Try to support other
5266 sizes ... */
f86103b7 5267 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 5268 int size = imm_size (n);
5269 int sign;
29b0f896 5270
40fb9820 5271 if (i.types[n].bitfield.imm32s
a7d61044 5272 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 5273 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 5274 sign = 1;
e205caa7
L		 5275 else
5276 sign = 0;
520dc8e8 5277
29b0f896
AM		 5278 p = frag_more (size);
5279 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 5280
2bbd9c25
JJ		 5281 /* This is tough to explain. We end up with this one if we
5282 * have operands that look like
5283 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5284 * obtain the absolute address of the GOT, and it is strongly
5285 * preferable from a performance point of view to avoid using
5286 * a runtime relocation for this. The actual sequence of
5287 * instructions often look something like:
5288 *
5289 * call .L66
5290 * .L66:
5291 * popl %ebx
5292 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5293 *
5294 * The call and pop essentially return the absolute address
5295 * of the label .L66 and store it in %ebx. The linker itself
5296 * will ultimately change the first operand of the addl so
5297 * that %ebx points to the GOT, but to keep things simple, the
5298 * .o file must have this operand set so that it generates not
5299 * the absolute address of .L66, but the absolute address of
5300 * itself. This allows the linker itself simply treat a GOTPC
5301 * relocation as asking for a pcrel offset to the GOT to be
5302 * added in, and the addend of the relocation is stored in the
5303 * operand field for the instruction itself.
5304 *
5305 * Our job here is to fix the operand so that it would add
5306 * the correct offset so that %ebx would point to itself. The
5307 * thing that is tricky is that .-.L66 will point to the
5308 * beginning of the instruction, so we need to further modify
5309 * the operand so that it will point to itself. There are
5310 * other cases where you have something like:
5311 *
5312 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5313 *
5314 * and here no correction would be required. Internally in
5315 * the assembler we treat operands of this form as not being
5316 * pcrel since the '.' is explicitly mentioned, and I wonder
5317 * whether it would simplify matters to do it this way. Who
5318 * knows. In earlier versions of the PIC patches, the
5319 * pcrel_adjust field was used to store the correction, but
5320 * since the expression is not pcrel, I felt it would be
5321 * confusing to do it this way. */
5322
d6ab8113 5323 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5324 || reloc_type == BFD_RELOC_X86_64_32S
5325 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 5326 && GOT_symbol
5327 && GOT_symbol == i.op[n].imms->X_add_symbol
5328 && (i.op[n].imms->X_op == O_symbol
5329 || (i.op[n].imms->X_op == O_add
5330 && ((symbol_get_value_expression
5331 (i.op[n].imms->X_op_symbol)->X_op)
5332 == O_subtract))))
5333 {
2bbd9c25
JJ		 5334 offsetT add;
5335
5336 if (insn_start_frag == frag_now)
5337 add = (p - frag_now->fr_literal) - insn_start_off;
5338 else
5339 {
5340 fragS *fr;
5341
5342 add = insn_start_frag->fr_fix - insn_start_off;
5343 for (fr = insn_start_frag->fr_next;
5344 fr && fr != frag_now; fr = fr->fr_next)
5345 add += fr->fr_fix;
5346 add += p - frag_now->fr_literal;
5347 }
5348
4fa24527 5349 if (!object_64bit)
d6ab8113 5350 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 5351 else if (size == 4)
d6ab8113 5352 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 5353 else if (size == 8)
5354 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 5355 i.op[n].imms->X_add_number += add;
29b0f896 5356 }
29b0f896
AM		 5357 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5358 i.op[n].imms, 0, reloc_type);
5359 }
5360 }
5361 }
252b5132
RH		 5362}
5363\f
d182319b
JB		 5364/* x86_cons_fix_new is called via the expression parsing code when a
5365 reloc is needed. We use this hook to get the correct .got reloc. */
5366static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5367static int cons_sign = -1;
5368
5369void
e3bb37b5 5370x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 5371 expressionS *exp)
d182319b
JB		 5372{
5373 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5374
5375 got_reloc = NO_RELOC;
5376
5377#ifdef TE_PE
5378 if (exp->X_op == O_secrel)
5379 {
5380 exp->X_op = O_symbol;
5381 r = BFD_RELOC_32_SECREL;
5382 }
5383#endif
5384
5385 fix_new_exp (frag, off, len, exp, 0, r);
5386}
5387
718ddfc0
JB		 5388#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5389# define lex_got(reloc, adjust, types) NULL
5390#else
f3c180ae
AM		 5391/* Parse operands of the form
5392 <symbol>@GOTOFF+<nnn>
5393 and similar .plt or .got references.
5394
5395 If we find one, set up the correct relocation in RELOC and copy the
5396 input string, minus the `@GOTOFF' into a malloc'd buffer for
5397 parsing by the calling routine. Return this buffer, and if ADJUST
5398 is non-null set it to the length of the string we removed from the
5399 input line. Otherwise return NULL. */
5400static char *
3956db08 5401lex_got (enum bfd_reloc_code_real *reloc,
64e74474 5402 int *adjust,
40fb9820 5403 i386_operand_type *types)
f3c180ae 5404{
7b81dfbb
AJ		 5405 /* Some of the relocations depend on the size of what field is to
5406 be relocated. But in our callers i386_immediate and i386_displacement
5407 we don't yet know the operand size (this will be set by insn
5408 matching). Hence we record the word32 relocation here,
5409 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 5410 static const struct {
5411 const char *str;
4fa24527 5412 const enum bfd_reloc_code_real rel[2];
40fb9820 5413 const i386_operand_type types64;
f3c180ae 5414 } gotrel[] = {
4eed87de
AM		 5415 { "PLTOFF", { 0,
5416 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 5417 OPERAND_TYPE_IMM64 },
4eed87de
AM		 5418 { "PLT", { BFD_RELOC_386_PLT32,
5419 BFD_RELOC_X86_64_PLT32 },
40fb9820 5420 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5421 { "GOTPLT", { 0,
5422 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 5423 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5424 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5425 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 5426 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5427 { "GOTPCREL", { 0,
5428 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 5429 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5430 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5431 BFD_RELOC_X86_64_TLSGD },
40fb9820 5432 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5433 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5434 0 },
40fb9820 5435 OPERAND_TYPE_NONE },
4eed87de
AM		 5436 { "TLSLD", { 0,
5437 BFD_RELOC_X86_64_TLSLD },
40fb9820 5438 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5439 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5440 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 5441 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5442 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5443 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 5444 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5445 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5446 0 },
40fb9820 5447 OPERAND_TYPE_NONE },
4eed87de
AM		 5448 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5449 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820
L		 5450
5451 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5452 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5453 0 },
40fb9820 5454 OPERAND_TYPE_NONE },
4eed87de
AM		 5455 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5456 0 },
40fb9820 5457 OPERAND_TYPE_NONE },
4eed87de
AM		 5458 { "GOT", { BFD_RELOC_386_GOT32,
5459 BFD_RELOC_X86_64_GOT32 },
40fb9820 5460 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 5461 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5462 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 5463 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5464 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5465 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 5466 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 5467 };
5468 char *cp;
5469 unsigned int j;
5470
718ddfc0
JB		 5471 if (!IS_ELF)
5472 return NULL;
5473
f3c180ae 5474 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 5475 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 5476 return NULL;
5477
5478 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
5479 {
5480 int len;
5481
5482 len = strlen (gotrel[j].str);
28f81592 5483 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 5484 {
4fa24527 5485 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 5486 {
28f81592
AM		 5487 int first, second;
5488 char *tmpbuf, *past_reloc;
f3c180ae 5489
4fa24527 5490 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 5491 if (adjust)
5492 *adjust = len;
f3c180ae 5493
3956db08
JB		 5494 if (types)
5495 {
5496 if (flag_code != CODE_64BIT)
40fb9820
L		 5497 {
5498 types->bitfield.imm32 = 1;
5499 types->bitfield.disp32 = 1;
5500 }
3956db08
JB		 5501 else
5502 *types = gotrel[j].types64;
5503 }
5504
f3c180ae
AM		 5505 if (GOT_symbol == NULL)
5506 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5507
28f81592 5508 /* The length of the first part of our input line. */
f3c180ae 5509 first = cp - input_line_pointer;
28f81592
AM		 5510
5511 /* The second part goes from after the reloc token until
67c11a9b 5512 (and including) an end_of_line char or comma. */
28f81592 5513 past_reloc = cp + 1 + len;
67c11a9b
AM		 5514 cp = past_reloc;
5515 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5516 ++cp;
5517 second = cp + 1 - past_reloc;
28f81592
AM		 5518
5519 /* Allocate and copy string. The trailing NUL shouldn't
5520 be necessary, but be safe. */
5521 tmpbuf = xmalloc (first + second + 2);
f3c180ae 5522 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 5523 if (second != 0 && *past_reloc != ' ')
5524 /* Replace the relocation token with ' ', so that
5525 errors like foo@GOTOFF1 will be detected. */
5526 tmpbuf[first++] = ' ';
5527 memcpy (tmpbuf + first, past_reloc, second);
5528 tmpbuf[first + second] = '\0';
f3c180ae
AM		 5529 return tmpbuf;
5530 }
5531
4fa24527
JB		 5532 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5533 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 5534 return NULL;
5535 }
5536 }
5537
5538 /* Might be a symbol version string. Don't as_bad here. */
5539 return NULL;
5540}
5541
f3c180ae 5542void
e3bb37b5 5543x86_cons (expressionS *exp, int size)
f3c180ae 5544{
4fa24527 5545 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 5546 {
5547 /* Handle @GOTOFF and the like in an expression. */
5548 char *save;
5549 char *gotfree_input_line;
5550 int adjust;
5551
5552 save = input_line_pointer;
3956db08 5553 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 5554 if (gotfree_input_line)
5555 input_line_pointer = gotfree_input_line;
5556
5557 expression (exp);
5558
5559 if (gotfree_input_line)
5560 {
5561 /* expression () has merrily parsed up to the end of line,
5562 or a comma - in the wrong buffer. Transfer how far
5563 input_line_pointer has moved to the right buffer. */
5564 input_line_pointer = (save
5565 + (input_line_pointer - gotfree_input_line)
5566 + adjust);
5567 free (gotfree_input_line);
3992d3b7
AM		 5568 if (exp->X_op == O_constant
5569 || exp->X_op == O_absent
5570 || exp->X_op == O_illegal
5571 || exp->X_op == O_register
5572 || exp->X_op == O_big)
5573 {
5574 char c = *input_line_pointer;
5575 *input_line_pointer = 0;
5576 as_bad (_("missing or invalid expression `%s'"), save);
5577 *input_line_pointer = c;
5578 }
f3c180ae
AM		 5579 }
5580 }
5581 else
5582 expression (exp);
5583}
5584#endif
5585
d182319b 5586static void signed_cons (int size)
6482c264 5587{
d182319b
JB		 5588 if (flag_code == CODE_64BIT)
5589 cons_sign = 1;
5590 cons (size);
5591 cons_sign = -1;
6482c264
NC		 5592}
5593
d182319b 5594#ifdef TE_PE
6482c264
NC		 5595static void
5596pe_directive_secrel (dummy)
5597 int dummy ATTRIBUTE_UNUSED;
5598{
5599 expressionS exp;
5600
5601 do
5602 {
5603 expression (&exp);
5604 if (exp.X_op == O_symbol)
5605 exp.X_op = O_secrel;
5606
5607 emit_expr (&exp, 4);
5608 }
5609 while (*input_line_pointer++ == ',');
5610
5611 input_line_pointer--;
5612 demand_empty_rest_of_line ();
5613}
6482c264
NC		 5614#endif
5615
252b5132 5616static int
70e41ade 5617i386_immediate (char *imm_start)
252b5132
RH		 5618{
5619 char *save_input_line_pointer;
f3c180ae 5620 char *gotfree_input_line;
252b5132 5621 segT exp_seg = 0;
47926f60 5622 expressionS *exp;
40fb9820
L		 5623 i386_operand_type types;
5624
c6fb90c8 5625 UINTS_SET (types, ~0);
252b5132
RH		 5626
5627 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5628 {
31b2323c
L		 5629 as_bad (_("at most %d immediate operands are allowed"),
5630 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 5631 return 0;
5632 }
5633
5634 exp = &im_expressions[i.imm_operands++];
520dc8e8 5635 i.op[this_operand].imms = exp;
252b5132
RH		 5636
5637 if (is_space_char (*imm_start))
5638 ++imm_start;
5639
5640 save_input_line_pointer = input_line_pointer;
5641 input_line_pointer = imm_start;
5642
3956db08 5643 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5644 if (gotfree_input_line)
5645 input_line_pointer = gotfree_input_line;
252b5132
RH		 5646
5647 exp_seg = expression (exp);
5648
83183c0c 5649 SKIP_WHITESPACE ();
252b5132 5650 if (*input_line_pointer)
f3c180ae 5651 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 5652
5653 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 5654 if (gotfree_input_line)
5655 free (gotfree_input_line);
252b5132 5656
3992d3b7
AM		 5657 if (exp->X_op == O_absent
5658 || exp->X_op == O_illegal
5659 || exp->X_op == O_big
5660 || (gotfree_input_line
5661 && (exp->X_op == O_constant
5662 || exp->X_op == O_register)))
252b5132 5663 {
3992d3b7 5664 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 5665 imm_start);
3992d3b7 5666 return 0;
252b5132 5667 }
3e73aa7c 5668 else if (exp->X_op == O_constant)
252b5132 5669 {
47926f60 5670 /* Size it properly later. */
40fb9820 5671 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 5672 /* If BFD64, sign extend val. */
4eed87de
AM		 5673 if (!use_rela_relocations
5674 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5675 exp->X_add_number
5676 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 5677 }
4c63da97 5678#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 5679 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 5680 && exp_seg != absolute_section
47926f60 5681 && exp_seg != text_section
24eab124
AM		 5682 && exp_seg != data_section
5683 && exp_seg != bss_section
5684 && exp_seg != undefined_section
f86103b7 5685 && !bfd_is_com_section (exp_seg))
252b5132 5686 {
d0b47220 5687 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 5688 return 0;
5689 }
5690#endif
bb8f5920
L		 5691 else if (!intel_syntax && exp->X_op == O_register)
5692 {
5693 as_bad (_("illegal immediate register operand %s"), imm_start);
5694 return 0;
5695 }
252b5132
RH		 5696 else
5697 {
5698 /* This is an address. The size of the address will be
24eab124 5699 determined later, depending on destination register,
3e73aa7c 5700 suffix, or the default for the section. */
40fb9820
L		 5701 i.types[this_operand].bitfield.imm8 = 1;
5702 i.types[this_operand].bitfield.imm16 = 1;
5703 i.types[this_operand].bitfield.imm32 = 1;
5704 i.types[this_operand].bitfield.imm32s = 1;
5705 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 5706 i.types[this_operand] = operand_type_and (i.types[this_operand],
5707 types);
252b5132
RH		 5708 }
5709
5710 return 1;
5711}
5712
551c1ca1 5713static char *
e3bb37b5 5714i386_scale (char *scale)
252b5132 5715{
551c1ca1
AM		 5716 offsetT val;
5717 char *save = input_line_pointer;
252b5132 5718
551c1ca1
AM		 5719 input_line_pointer = scale;
5720 val = get_absolute_expression ();
5721
5722 switch (val)
252b5132 5723 {
551c1ca1 5724 case 1:
252b5132
RH		 5725 i.log2_scale_factor = 0;
5726 break;
551c1ca1 5727 case 2:
252b5132
RH		 5728 i.log2_scale_factor = 1;
5729 break;
551c1ca1 5730 case 4:
252b5132
RH		 5731 i.log2_scale_factor = 2;
5732 break;
551c1ca1 5733 case 8:
252b5132
RH		 5734 i.log2_scale_factor = 3;
5735 break;
5736 default:
a724f0f4
JB		 5737 {
5738 char sep = *input_line_pointer;
5739
5740 *input_line_pointer = '\0';
5741 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5742 scale);
5743 *input_line_pointer = sep;
5744 input_line_pointer = save;
5745 return NULL;
5746 }
252b5132 5747 }
29b0f896 5748 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 5749 {
5750 as_warn (_("scale factor of %d without an index register"),
24eab124 5751 1 << i.log2_scale_factor);
252b5132 5752 i.log2_scale_factor = 0;
252b5132 5753 }
551c1ca1
AM		 5754 scale = input_line_pointer;
5755 input_line_pointer = save;
5756 return scale;
252b5132
RH		 5757}
5758
252b5132 5759static int
e3bb37b5 5760i386_displacement (char *disp_start, char *disp_end)
252b5132 5761{
29b0f896 5762 expressionS *exp;
252b5132
RH		 5763 segT exp_seg = 0;
5764 char *save_input_line_pointer;
f3c180ae 5765 char *gotfree_input_line;
40fb9820
L		 5766 int override;
5767 i386_operand_type bigdisp, types = anydisp;
3992d3b7 5768 int ret;
252b5132 5769
31b2323c
L		 5770 if (i.disp_operands == MAX_MEMORY_OPERANDS)
5771 {
5772 as_bad (_("at most %d displacement operands are allowed"),
5773 MAX_MEMORY_OPERANDS);
5774 return 0;
5775 }
5776
c6fb90c8 5777 UINTS_CLEAR (bigdisp);
40fb9820
L		 5778 if ((i.types[this_operand].bitfield.jumpabsolute)
5779 || (!current_templates->start->opcode_modifier.jump
5780 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 5781 {
40fb9820 5782 bigdisp.bitfield.disp32 = 1;
e05278af 5783 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 5784 if (flag_code == CODE_64BIT)
5785 {
5786 if (!override)
5787 {
5788 bigdisp.bitfield.disp32s = 1;
5789 bigdisp.bitfield.disp64 = 1;
5790 }
5791 }
5792 else if ((flag_code == CODE_16BIT) ^ override)
5793 {
5794 bigdisp.bitfield.disp32 = 0;
5795 bigdisp.bitfield.disp16 = 1;
5796 }
e05278af
JB		 5797 }
5798 else
5799 {
5800 /* For PC-relative branches, the width of the displacement
5801 is dependent upon data size, not address size. */
e05278af 5802 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 5803 if (flag_code == CODE_64BIT)
5804 {
5805 if (override || i.suffix == WORD_MNEM_SUFFIX)
5806 bigdisp.bitfield.disp16 = 1;
5807 else
5808 {
5809 bigdisp.bitfield.disp32 = 1;
5810 bigdisp.bitfield.disp32s = 1;
5811 }
5812 }
5813 else
e05278af
JB		 5814 {
5815 if (!override)
5816 override = (i.suffix == (flag_code != CODE_16BIT
5817 ? WORD_MNEM_SUFFIX
5818 : LONG_MNEM_SUFFIX));
40fb9820
L		 5819 bigdisp.bitfield.disp32 = 1;
5820 if ((flag_code == CODE_16BIT) ^ override)
5821 {
5822 bigdisp.bitfield.disp32 = 0;
5823 bigdisp.bitfield.disp16 = 1;
5824 }
e05278af 5825 }
e05278af 5826 }
c6fb90c8
L		 5827 i.types[this_operand] = operand_type_or (i.types[this_operand],
5828 bigdisp);
252b5132
RH		 5829
5830 exp = &disp_expressions[i.disp_operands];
520dc8e8 5831 i.op[this_operand].disps = exp;
252b5132
RH		 5832 i.disp_operands++;
5833 save_input_line_pointer = input_line_pointer;
5834 input_line_pointer = disp_start;
5835 END_STRING_AND_SAVE (disp_end);
5836
5837#ifndef GCC_ASM_O_HACK
5838#define GCC_ASM_O_HACK 0
5839#endif
5840#if GCC_ASM_O_HACK
5841 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 5842 if (i.types[this_operand].bitfield.baseIndex
24eab124 5843 && displacement_string_end[-1] == '+')
252b5132
RH		 5844 {
5845 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 5846 constraint within gcc asm statements.
5847 For instance:
5848
5849 #define _set_tssldt_desc(n,addr,limit,type) \
5850 __asm__ __volatile__ ( \
5851 "movw %w2,%0\n\t" \
5852 "movw %w1,2+%0\n\t" \
5853 "rorl $16,%1\n\t" \
5854 "movb %b1,4+%0\n\t" \
5855 "movb %4,5+%0\n\t" \
5856 "movb $0,6+%0\n\t" \
5857 "movb %h1,7+%0\n\t" \
5858 "rorl $16,%1" \
5859 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
5860
5861 This works great except that the output assembler ends
5862 up looking a bit weird if it turns out that there is
5863 no offset. You end up producing code that looks like:
5864
5865 #APP
5866 movw $235,(%eax)
5867 movw %dx,2+(%eax)
5868 rorl $16,%edx
5869 movb %dl,4+(%eax)
5870 movb $137,5+(%eax)
5871 movb $0,6+(%eax)
5872 movb %dh,7+(%eax)
5873 rorl $16,%edx
5874 #NO_APP
5875
47926f60 5876 So here we provide the missing zero. */
24eab124
AM		 5877
5878 *displacement_string_end = '0';
252b5132
RH		 5879 }
5880#endif
3956db08 5881 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5882 if (gotfree_input_line)
5883 input_line_pointer = gotfree_input_line;
252b5132 5884
24eab124 5885 exp_seg = expression (exp);
252b5132 5886
636c26b0
AM		 5887 SKIP_WHITESPACE ();
5888 if (*input_line_pointer)
5889 as_bad (_("junk `%s' after expression"), input_line_pointer);
5890#if GCC_ASM_O_HACK
5891 RESTORE_END_STRING (disp_end + 1);
5892#endif
636c26b0 5893 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 5894 if (gotfree_input_line)
5895 free (gotfree_input_line);
3992d3b7 5896 ret = 1;
636c26b0 5897
24eab124
AM		 5898 /* We do this to make sure that the section symbol is in
5899 the symbol table. We will ultimately change the relocation
47926f60 5900 to be relative to the beginning of the section. */
1ae12ab7 5901 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 5902 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
5903 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 5904 {
636c26b0 5905 if (exp->X_op != O_symbol)
3992d3b7 5906 goto inv_disp;
636c26b0 5907
e5cb08ac 5908 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 5909 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
5910 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 5911 exp->X_op = O_subtract;
5912 exp->X_op_symbol = GOT_symbol;
1ae12ab7 5913 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 5914 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 5915 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
5916 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 5917 else
29b0f896 5918 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 5919 }
252b5132 5920
3992d3b7
AM		 5921 else if (exp->X_op == O_absent
5922 || exp->X_op == O_illegal
5923 || exp->X_op == O_big
5924 || (gotfree_input_line
5925 && (exp->X_op == O_constant
5926 || exp->X_op == O_register)))
2daf4fd8 5927 {
3992d3b7
AM		 5928 inv_disp:
5929 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 5930 disp_start);
3992d3b7 5931 ret = 0;
2daf4fd8
AM		 5932 }
5933
4c63da97 5934#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 5935 else if (exp->X_op != O_constant
5936 && OUTPUT_FLAVOR == bfd_target_aout_flavour
5937 && exp_seg != absolute_section
5938 && exp_seg != text_section
5939 && exp_seg != data_section
5940 && exp_seg != bss_section
5941 && exp_seg != undefined_section
5942 && !bfd_is_com_section (exp_seg))
24eab124 5943 {
d0b47220 5944 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 5945 ret = 0;
24eab124 5946 }
252b5132 5947#endif
3956db08 5948
3992d3b7
AM		 5949 RESTORE_END_STRING (disp_end);
5950
40fb9820
L		 5951 /* Check if this is a displacement only operand. */
5952 bigdisp = i.types[this_operand];
5953 bigdisp.bitfield.disp8 = 0;
5954 bigdisp.bitfield.disp16 = 0;
5955 bigdisp.bitfield.disp32 = 0;
5956 bigdisp.bitfield.disp32s = 0;
5957 bigdisp.bitfield.disp64 = 0;
c6fb90c8
L		 5958 if (UINTS_ALL_ZERO (bigdisp))
5959 i.types[this_operand] = operand_type_and (i.types[this_operand],
5960 types);
3956db08 5961
3992d3b7 5962 return ret;
252b5132
RH		 5963}
5964
eecb386c 5965/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 5966 Return 1 on success, 0 on a failure. */
5967
252b5132 5968static int
e3bb37b5 5969i386_index_check (const char *operand_string)
252b5132 5970{
3e73aa7c 5971 int ok;
24eab124 5972#if INFER_ADDR_PREFIX
eecb386c
AM		 5973 int fudged = 0;
5974
24eab124
AM		 5975 tryprefix:
5976#endif
3e73aa7c 5977 ok = 1;
75178d9d 5978 if (flag_code == CODE_64BIT)
64e74474 5979 {
64e74474 5980 if ((i.base_reg
40fb9820
L		 5981 && ((i.prefix[ADDR_PREFIX] == 0
5982 && !i.base_reg->reg_type.bitfield.reg64)
5983 || (i.prefix[ADDR_PREFIX]
5984 && !i.base_reg->reg_type.bitfield.reg32))
5985 && (i.index_reg
20e192ab 5986 || i.base_reg->reg_num != RegRip))
64e74474 5987 || (i.index_reg
40fb9820
L		 5988 && (!i.index_reg->reg_type.bitfield.baseindex
5989 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 5990 && i.index_reg->reg_num != RegRiz
5991 && !i.index_reg->reg_type.bitfield.reg64
5992 )
40fb9820 5993 || (i.prefix[ADDR_PREFIX]
db51cc60 5994 && i.index_reg->reg_num != RegEiz
40fb9820 5995 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 5996 ok = 0;
3e73aa7c
JH		 5997 }
5998 else
5999 {
6000 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6001 {
6002 /* 16bit checks. */
6003 if ((i.base_reg
40fb9820
L		 6004 && (!i.base_reg->reg_type.bitfield.reg16
6005 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6006 || (i.index_reg
40fb9820
L		 6007 && (!i.index_reg->reg_type.bitfield.reg16
6008 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6009 || !(i.base_reg
6010 && i.base_reg->reg_num < 6
6011 && i.index_reg->reg_num >= 6
6012 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6013 ok = 0;
6014 }
6015 else
e5cb08ac 6016 {
3e73aa7c
JH		 6017 /* 32bit checks. */
6018 if ((i.base_reg
40fb9820 6019 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6020 || (i.index_reg
db51cc60
L		 6021 && ((!i.index_reg->reg_type.bitfield.reg32
6022 && i.index_reg->reg_num != RegEiz)
40fb9820 6023 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6024 ok = 0;
3e73aa7c
JH		 6025 }
6026 }
6027 if (!ok)
24eab124
AM		 6028 {
6029#if INFER_ADDR_PREFIX
20f0a1fc 6030 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 6031 {
6032 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6033 i.prefixes += 1;
b23bac36
AM		 6034 /* Change the size of any displacement too. At most one of
6035 Disp16 or Disp32 is set.
6036 FIXME. There doesn't seem to be any real need for separate
6037 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6038 Removing them would probably clean up the code quite a lot. */
4eed87de 6039 if (flag_code != CODE_64BIT
40fb9820
L		 6040 && (i.types[this_operand].bitfield.disp16
6041 || i.types[this_operand].bitfield.disp32))
6042 i.types[this_operand]
c6fb90c8 6043 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6044 fudged = 1;
24eab124
AM		 6045 goto tryprefix;
6046 }
eecb386c
AM		 6047 if (fudged)
6048 as_bad (_("`%s' is not a valid base/index expression"),
6049 operand_string);
6050 else
c388dee8 6051#endif
eecb386c
AM		 6052 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6053 operand_string,
3e73aa7c 6054 flag_code_names[flag_code]);
24eab124 6055 }
20f0a1fc 6056 return ok;
24eab124 6057}
252b5132 6058
252b5132 6059/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 6060 on error. */
252b5132 6061
252b5132 6062static int
e3bb37b5 6063i386_operand (char *operand_string)
252b5132 6064{
af6bdddf
AM		 6065 const reg_entry *r;
6066 char *end_op;
24eab124 6067 char *op_string = operand_string;
252b5132 6068
24eab124 6069 if (is_space_char (*op_string))
252b5132
RH		 6070 ++op_string;
6071
24eab124 6072 /* We check for an absolute prefix (differentiating,
47926f60 6073 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 6074 if (*op_string == ABSOLUTE_PREFIX)
6075 {
6076 ++op_string;
6077 if (is_space_char (*op_string))
6078 ++op_string;
40fb9820 6079 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 6080 }
252b5132 6081
47926f60 6082 /* Check if operand is a register. */
4d1bb795 6083 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 6084 {
40fb9820
L		 6085 i386_operand_type temp;
6086
24eab124
AM		 6087 /* Check for a segment override by searching for ':' after a
6088 segment register. */
6089 op_string = end_op;
6090 if (is_space_char (*op_string))
6091 ++op_string;
40fb9820
L		 6092 if (*op_string == ':'
6093 && (r->reg_type.bitfield.sreg2
6094 || r->reg_type.bitfield.sreg3))
24eab124
AM		 6095 {
6096 switch (r->reg_num)
6097 {
6098 case 0:
6099 i.seg[i.mem_operands] = &es;
6100 break;
6101 case 1:
6102 i.seg[i.mem_operands] = &cs;
6103 break;
6104 case 2:
6105 i.seg[i.mem_operands] = &ss;
6106 break;
6107 case 3:
6108 i.seg[i.mem_operands] = &ds;
6109 break;
6110 case 4:
6111 i.seg[i.mem_operands] = &fs;
6112 break;
6113 case 5:
6114 i.seg[i.mem_operands] = &gs;
6115 break;
6116 }
252b5132 6117
24eab124 6118 /* Skip the ':' and whitespace. */
252b5132
RH		 6119 ++op_string;
6120 if (is_space_char (*op_string))
24eab124 6121 ++op_string;
252b5132 6122
24eab124
AM		 6123 if (!is_digit_char (*op_string)
6124 && !is_identifier_char (*op_string)
6125 && *op_string != '('
6126 && *op_string != ABSOLUTE_PREFIX)
6127 {
6128 as_bad (_("bad memory operand `%s'"), op_string);
6129 return 0;
6130 }
47926f60 6131 /* Handle case of %es:*foo. */
24eab124
AM		 6132 if (*op_string == ABSOLUTE_PREFIX)
6133 {
6134 ++op_string;
6135 if (is_space_char (*op_string))
6136 ++op_string;
40fb9820 6137 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 6138 }
6139 goto do_memory_reference;
6140 }
6141 if (*op_string)
6142 {
d0b47220 6143 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 6144 return 0;
6145 }
40fb9820
L		 6146 temp = r->reg_type;
6147 temp.bitfield.baseindex = 0;
c6fb90c8
L		 6148 i.types[this_operand] = operand_type_or (i.types[this_operand],
6149 temp);
520dc8e8 6150 i.op[this_operand].regs = r;
24eab124
AM		 6151 i.reg_operands++;
6152 }
af6bdddf
AM		 6153 else if (*op_string == REGISTER_PREFIX)
6154 {
6155 as_bad (_("bad register name `%s'"), op_string);
6156 return 0;
6157 }
24eab124 6158 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 6159 {
24eab124 6160 ++op_string;
40fb9820 6161 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 6162 {
d0b47220 6163 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 6164 return 0;
6165 }
6166 if (!i386_immediate (op_string))
6167 return 0;
6168 }
6169 else if (is_digit_char (*op_string)
6170 || is_identifier_char (*op_string)
e5cb08ac 6171 || *op_string == '(')
24eab124 6172 {
47926f60 6173 /* This is a memory reference of some sort. */
af6bdddf 6174 char *base_string;
252b5132 6175
47926f60 6176 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 6177 char *displacement_string_start;
6178 char *displacement_string_end;
252b5132 6179
24eab124 6180 do_memory_reference:
24eab124 6181 if ((i.mem_operands == 1
40fb9820 6182 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 6183 || i.mem_operands == 2)
6184 {
6185 as_bad (_("too many memory references for `%s'"),
6186 current_templates->start->name);
6187 return 0;
6188 }
252b5132 6189
24eab124
AM		 6190 /* Check for base index form. We detect the base index form by
6191 looking for an ')' at the end of the operand, searching
6192 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6193 after the '('. */
af6bdddf 6194 base_string = op_string + strlen (op_string);
c3332e24 6195
af6bdddf
AM		 6196 --base_string;
6197 if (is_space_char (*base_string))
6198 --base_string;
252b5132 6199
47926f60 6200 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 6201 displacement_string_start = op_string;
6202 displacement_string_end = base_string + 1;
252b5132 6203
24eab124
AM		 6204 if (*base_string == ')')
6205 {
af6bdddf 6206 char *temp_string;
24eab124
AM		 6207 unsigned int parens_balanced = 1;
6208 /* We've already checked that the number of left & right ()'s are
47926f60 6209 equal, so this loop will not be infinite. */
24eab124
AM		 6210 do
6211 {
6212 base_string--;
6213 if (*base_string == ')')
6214 parens_balanced++;
6215 if (*base_string == '(')
6216 parens_balanced--;
6217 }
6218 while (parens_balanced);
c3332e24 6219
af6bdddf 6220 temp_string = base_string;
c3332e24 6221
24eab124 6222 /* Skip past '(' and whitespace. */
252b5132
RH		 6223 ++base_string;
6224 if (is_space_char (*base_string))
24eab124 6225 ++base_string;
252b5132 6226
af6bdddf 6227 if (*base_string == ','
4eed87de
AM		 6228 || ((i.base_reg = parse_register (base_string, &end_op))
6229 != NULL))
252b5132 6230 {
af6bdddf 6231 displacement_string_end = temp_string;
252b5132 6232
40fb9820 6233 i.types[this_operand].bitfield.baseindex = 1;
252b5132 6234
af6bdddf 6235 if (i.base_reg)
24eab124 6236 {
24eab124
AM		 6237 base_string = end_op;
6238 if (is_space_char (*base_string))
6239 ++base_string;
af6bdddf
AM		 6240 }
6241
6242 /* There may be an index reg or scale factor here. */
6243 if (*base_string == ',')
6244 {
6245 ++base_string;
6246 if (is_space_char (*base_string))
6247 ++base_string;
6248
4eed87de
AM		 6249 if ((i.index_reg = parse_register (base_string, &end_op))
6250 != NULL)
24eab124 6251 {
af6bdddf 6252 base_string = end_op;
24eab124
AM		 6253 if (is_space_char (*base_string))
6254 ++base_string;
af6bdddf
AM		 6255 if (*base_string == ',')
6256 {
6257 ++base_string;
6258 if (is_space_char (*base_string))
6259 ++base_string;
6260 }
e5cb08ac 6261 else if (*base_string != ')')
af6bdddf 6262 {
4eed87de
AM		 6263 as_bad (_("expecting `,' or `)' "
6264 "after index register in `%s'"),
af6bdddf
AM		 6265 operand_string);
6266 return 0;
6267 }
24eab124 6268 }
af6bdddf 6269 else if (*base_string == REGISTER_PREFIX)
24eab124 6270 {
af6bdddf 6271 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 6272 return 0;
6273 }
252b5132 6274
47926f60 6275 /* Check for scale factor. */
551c1ca1 6276 if (*base_string != ')')
af6bdddf 6277 {
551c1ca1
AM		 6278 char *end_scale = i386_scale (base_string);
6279
6280 if (!end_scale)
af6bdddf 6281 return 0;
24eab124 6282
551c1ca1 6283 base_string = end_scale;
af6bdddf
AM		 6284 if (is_space_char (*base_string))
6285 ++base_string;
6286 if (*base_string != ')')
6287 {
4eed87de
AM		 6288 as_bad (_("expecting `)' "
6289 "after scale factor in `%s'"),
af6bdddf
AM		 6290 operand_string);
6291 return 0;
6292 }
6293 }
6294 else if (!i.index_reg)
24eab124 6295 {
4eed87de
AM		 6296 as_bad (_("expecting index register or scale factor "
6297 "after `,'; got '%c'"),
af6bdddf 6298 *base_string);
24eab124
AM		 6299 return 0;
6300 }
6301 }
af6bdddf 6302 else if (*base_string != ')')
24eab124 6303 {
4eed87de
AM		 6304 as_bad (_("expecting `,' or `)' "
6305 "after base register in `%s'"),
af6bdddf 6306 operand_string);
24eab124
AM		 6307 return 0;
6308 }
c3332e24 6309 }
af6bdddf 6310 else if (*base_string == REGISTER_PREFIX)
c3332e24 6311 {
af6bdddf 6312 as_bad (_("bad register name `%s'"), base_string);
24eab124 6313 return 0;
c3332e24 6314 }
24eab124
AM		 6315 }
6316
6317 /* If there's an expression beginning the operand, parse it,
6318 assuming displacement_string_start and
6319 displacement_string_end are meaningful. */
6320 if (displacement_string_start != displacement_string_end)
6321 {
6322 if (!i386_displacement (displacement_string_start,
6323 displacement_string_end))
6324 return 0;
6325 }
6326
6327 /* Special case for (%dx) while doing input/output op. */
6328 if (i.base_reg
c6fb90c8 6329 && UINTS_EQUAL (i.base_reg->reg_type, reg16_inoutportreg)
24eab124
AM		 6330 && i.index_reg == 0
6331 && i.log2_scale_factor == 0
6332 && i.seg[i.mem_operands] == 0
40fb9820 6333 && !operand_type_check (i.types[this_operand], disp))
24eab124 6334 {
c6fb90c8 6335 UINTS_CLEAR (i.types[this_operand]);
40fb9820 6336 i.types[this_operand].bitfield.inoutportreg = 1;
24eab124
AM		 6337 return 1;
6338 }
6339
eecb386c
AM		 6340 if (i386_index_check (operand_string) == 0)
6341 return 0;
24eab124
AM		 6342 i.mem_operands++;
6343 }
6344 else
ce8a8b2f
AM		 6345 {
6346 /* It's not a memory operand; argh! */
24eab124
AM		 6347 as_bad (_("invalid char %s beginning operand %d `%s'"),
6348 output_invalid (*op_string),
6349 this_operand + 1,
6350 op_string);
6351 return 0;
6352 }
47926f60 6353 return 1; /* Normal return. */
252b5132
RH		 6354}
6355\f
ee7fcc42
AM		 6356/* md_estimate_size_before_relax()
6357
6358 Called just before relax() for rs_machine_dependent frags. The x86
6359 assembler uses these frags to handle variable size jump
6360 instructions.
6361
6362 Any symbol that is now undefined will not become defined.
6363 Return the correct fr_subtype in the frag.
6364 Return the initial "guess for variable size of frag" to caller.
6365 The guess is actually the growth beyond the fixed part. Whatever
6366 we do to grow the fixed or variable part contributes to our
6367 returned value. */
6368
252b5132
RH		 6369int
6370md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 6371 fragS *fragP;
6372 segT segment;
252b5132 6373{
252b5132 6374 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 6375 check for un-relaxable symbols. On an ELF system, we can't relax
6376 an externally visible symbol, because it may be overridden by a
6377 shared library. */
6378 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 6379#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6380 || (IS_ELF
31312f95
AM		 6381 && (S_IS_EXTERNAL (fragP->fr_symbol)
6382 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 6383#endif
6384 )
252b5132 6385 {
b98ef147
AM		 6386 /* Symbol is undefined in this segment, or we need to keep a
6387 reloc so that weak symbols can be overridden. */
6388 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 6389 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 6390 unsigned char *opcode;
6391 int old_fr_fix;
f6af82bd 6392
ee7fcc42
AM		 6393 if (fragP->fr_var != NO_RELOC)
6394 reloc_type = fragP->fr_var;
b98ef147 6395 else if (size == 2)
f6af82bd
AM		 6396 reloc_type = BFD_RELOC_16_PCREL;
6397 else
6398 reloc_type = BFD_RELOC_32_PCREL;
252b5132 6399
ee7fcc42
AM		 6400 old_fr_fix = fragP->fr_fix;
6401 opcode = (unsigned char *) fragP->fr_opcode;
6402
fddf5b5b 6403 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 6404 {
fddf5b5b
AM		 6405 case UNCOND_JUMP:
6406 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 6407 opcode[0] = 0xe9;
252b5132 6408 fragP->fr_fix += size;
062cd5e7
AS		 6409 fix_new (fragP, old_fr_fix, size,
6410 fragP->fr_symbol,
6411 fragP->fr_offset, 1,
6412 reloc_type);
252b5132
RH		 6413 break;
6414
fddf5b5b 6415 case COND_JUMP86:
412167cb
AM		 6416 if (size == 2
6417 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 6418 {
6419 /* Negate the condition, and branch past an
6420 unconditional jump. */
6421 opcode[0] ^= 1;
6422 opcode[1] = 3;
6423 /* Insert an unconditional jump. */
6424 opcode[2] = 0xe9;
6425 /* We added two extra opcode bytes, and have a two byte
6426 offset. */
6427 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 6428 fix_new (fragP, old_fr_fix + 2, 2,
6429 fragP->fr_symbol,
6430 fragP->fr_offset, 1,
6431 reloc_type);
fddf5b5b
AM		 6432 break;
6433 }
6434 /* Fall through. */
6435
6436 case COND_JUMP:
412167cb
AM		 6437 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
6438 {
3e02c1cc
AM		 6439 fixS *fixP;
6440
412167cb 6441 fragP->fr_fix += 1;
3e02c1cc
AM		 6442 fixP = fix_new (fragP, old_fr_fix, 1,
6443 fragP->fr_symbol,
6444 fragP->fr_offset, 1,
6445 BFD_RELOC_8_PCREL);
6446 fixP->fx_signed = 1;
412167cb
AM		 6447 break;
6448 }
93c2a809 6449
24eab124 6450 /* This changes the byte-displacement jump 0x7N
fddf5b5b 6451 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 6452 opcode[1] = opcode[0] + 0x10;
f6af82bd 6453 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 6454 /* We've added an opcode byte. */
6455 fragP->fr_fix += 1 + size;
062cd5e7
AS		 6456 fix_new (fragP, old_fr_fix + 1, size,
6457 fragP->fr_symbol,
6458 fragP->fr_offset, 1,
6459 reloc_type);
252b5132 6460 break;
fddf5b5b
AM		 6461
6462 default:
6463 BAD_CASE (fragP->fr_subtype);
6464 break;
252b5132
RH		 6465 }
6466 frag_wane (fragP);
ee7fcc42 6467 return fragP->fr_fix - old_fr_fix;
252b5132 6468 }
93c2a809 6469
93c2a809
AM		 6470 /* Guess size depending on current relax state. Initially the relax
6471 state will correspond to a short jump and we return 1, because
6472 the variable part of the frag (the branch offset) is one byte
6473 long. However, we can relax a section more than once and in that
6474 case we must either set fr_subtype back to the unrelaxed state,
6475 or return the value for the appropriate branch. */
6476 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 6477}
6478
47926f60
KH		 6479/* Called after relax() is finished.
6480
6481 In: Address of frag.
6482 fr_type == rs_machine_dependent.
6483 fr_subtype is what the address relaxed to.
6484
6485 Out: Any fixSs and constants are set up.
6486 Caller will turn frag into a ".space 0". */
6487
252b5132
RH		 6488void
6489md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 6490 bfd *abfd ATTRIBUTE_UNUSED;
6491 segT sec ATTRIBUTE_UNUSED;
29b0f896 6492 fragS *fragP;
252b5132 6493{
29b0f896 6494 unsigned char *opcode;
252b5132 6495 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 6496 offsetT target_address;
6497 offsetT opcode_address;
252b5132 6498 unsigned int extension = 0;
847f7ad4 6499 offsetT displacement_from_opcode_start;
252b5132
RH		 6500
6501 opcode = (unsigned char *) fragP->fr_opcode;
6502
47926f60 6503 /* Address we want to reach in file space. */
252b5132 6504 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 6505
47926f60 6506 /* Address opcode resides at in file space. */
252b5132
RH		 6507 opcode_address = fragP->fr_address + fragP->fr_fix;
6508
47926f60 6509 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 6510 displacement_from_opcode_start = target_address - opcode_address;
6511
fddf5b5b 6512 if ((fragP->fr_subtype & BIG) == 0)
252b5132 6513 {
47926f60
KH		 6514 /* Don't have to change opcode. */
6515 extension = 1; /* 1 opcode + 1 displacement */
252b5132 6516 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 6517 }
6518 else
6519 {
6520 if (no_cond_jump_promotion
6521 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 6522 as_warn_where (fragP->fr_file, fragP->fr_line,
6523 _("long jump required"));
252b5132 6524
fddf5b5b
AM		 6525 switch (fragP->fr_subtype)
6526 {
6527 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6528 extension = 4; /* 1 opcode + 4 displacement */
6529 opcode[0] = 0xe9;
6530 where_to_put_displacement = &opcode[1];
6531 break;
252b5132 6532
fddf5b5b
AM		 6533 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6534 extension = 2; /* 1 opcode + 2 displacement */
6535 opcode[0] = 0xe9;
6536 where_to_put_displacement = &opcode[1];
6537 break;
252b5132 6538
fddf5b5b
AM		 6539 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6540 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6541 extension = 5; /* 2 opcode + 4 displacement */
6542 opcode[1] = opcode[0] + 0x10;
6543 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6544 where_to_put_displacement = &opcode[2];
6545 break;
252b5132 6546
fddf5b5b
AM		 6547 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6548 extension = 3; /* 2 opcode + 2 displacement */
6549 opcode[1] = opcode[0] + 0x10;
6550 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6551 where_to_put_displacement = &opcode[2];
6552 break;
252b5132 6553
fddf5b5b
AM		 6554 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6555 extension = 4;
6556 opcode[0] ^= 1;
6557 opcode[1] = 3;
6558 opcode[2] = 0xe9;
6559 where_to_put_displacement = &opcode[3];
6560 break;
6561
6562 default:
6563 BAD_CASE (fragP->fr_subtype);
6564 break;
6565 }
252b5132 6566 }
fddf5b5b 6567
7b81dfbb
AJ		 6568 /* If size if less then four we are sure that the operand fits,
6569 but if it's 4, then it could be that the displacement is larger
6570 then -/+ 2GB. */
6571 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6572 && object_64bit
6573 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 6574 + ((addressT) 1 << 31))
6575 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 6576 {
6577 as_bad_where (fragP->fr_file, fragP->fr_line,
6578 _("jump target out of range"));
6579 /* Make us emit 0. */
6580 displacement_from_opcode_start = extension;
6581 }
47926f60 6582 /* Now put displacement after opcode. */
252b5132
RH		 6583 md_number_to_chars ((char *) where_to_put_displacement,
6584 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 6585 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 6586 fragP->fr_fix += extension;
6587}
6588\f
47926f60
KH		 6589/* Size of byte displacement jmp. */
6590int md_short_jump_size = 2;
6591
6592/* Size of dword displacement jmp. */
6593int md_long_jump_size = 5;
252b5132 6594
252b5132
RH		 6595void
6596md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
6597 char *ptr;
6598 addressT from_addr, to_addr;
ab9da554
ILT		 6599 fragS *frag ATTRIBUTE_UNUSED;
6600 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 6601{
847f7ad4 6602 offsetT offset;
252b5132
RH		 6603
6604 offset = to_addr - (from_addr + 2);
47926f60
KH		 6605 /* Opcode for byte-disp jump. */
6606 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 6607 md_number_to_chars (ptr + 1, (valueT) offset, 1);
6608}
6609
6610void
6611md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
6612 char *ptr;
6613 addressT from_addr, to_addr;
a38cf1db
AM		 6614 fragS *frag ATTRIBUTE_UNUSED;
6615 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 6616{
847f7ad4 6617 offsetT offset;
252b5132 6618
a38cf1db
AM		 6619 offset = to_addr - (from_addr + 5);
6620 md_number_to_chars (ptr, (valueT) 0xe9, 1);
6621 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 6622}
6623\f
6624/* Apply a fixup (fixS) to segment data, once it has been determined
6625 by our caller that we have all the info we need to fix it up.
6626
6627 On the 386, immediates, displacements, and data pointers are all in
6628 the same (little-endian) format, so we don't need to care about which
6629 we are handling. */
6630
94f592af 6631void
55cf6793 6632md_apply_fix (fixP, valP, seg)
47926f60
KH		 6633 /* The fix we're to put in. */
6634 fixS *fixP;
47926f60 6635 /* Pointer to the value of the bits. */
c6682705 6636 valueT *valP;
47926f60
KH		 6637 /* Segment fix is from. */
6638 segT seg ATTRIBUTE_UNUSED;
252b5132 6639{
94f592af 6640 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 6641 valueT value = *valP;
252b5132 6642
f86103b7 6643#if !defined (TE_Mach)
93382f6d
AM		 6644 if (fixP->fx_pcrel)
6645 {
6646 switch (fixP->fx_r_type)
6647 {
5865bb77
ILT		 6648 default:
6649 break;
6650
d6ab8113
JB		 6651 case BFD_RELOC_64:
6652 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6653 break;
93382f6d 6654 case BFD_RELOC_32:
ae8887b5 6655 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 6656 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6657 break;
6658 case BFD_RELOC_16:
6659 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6660 break;
6661 case BFD_RELOC_8:
6662 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6663 break;
6664 }
6665 }
252b5132 6666
a161fe53 6667 if (fixP->fx_addsy != NULL
31312f95 6668 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 6669 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 6670 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6671 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6672 && !use_rela_relocations)
252b5132 6673 {
31312f95
AM		 6674 /* This is a hack. There should be a better way to handle this.
6675 This covers for the fact that bfd_install_relocation will
6676 subtract the current location (for partial_inplace, PC relative
6677 relocations); see more below. */
252b5132 6678#ifndef OBJ_AOUT
718ddfc0 6679 if (IS_ELF
252b5132
RH		 6680#ifdef TE_PE
6681 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6682#endif
6683 )
6684 value += fixP->fx_where + fixP->fx_frag->fr_address;
6685#endif
6686#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6687 if (IS_ELF)
252b5132 6688 {
6539b54b 6689 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 6690
6539b54b 6691 if ((sym_seg == seg
2f66722d 6692 || (symbol_section_p (fixP->fx_addsy)
6539b54b 6693 && sym_seg != absolute_section))
ae6063d4 6694 && !generic_force_reloc (fixP))
2f66722d
AM		 6695 {
6696 /* Yes, we add the values in twice. This is because
6539b54b
AM		 6697 bfd_install_relocation subtracts them out again. I think
6698 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 6699 it. FIXME. */
6700 value += fixP->fx_where + fixP->fx_frag->fr_address;
6701 }
252b5132
RH		 6702 }
6703#endif
6704#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 6705 /* For some reason, the PE format does not store a
6706 section address offset for a PC relative symbol. */
6707 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 6708 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 6709 value += md_pcrel_from (fixP);
6710#endif
6711 }
6712
6713 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 6714 and we must not disappoint it. */
252b5132 6715#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6716 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 6717 switch (fixP->fx_r_type)
6718 {
6719 case BFD_RELOC_386_PLT32:
3e73aa7c 6720 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 6721 /* Make the jump instruction point to the address of the operand. At
6722 runtime we merely add the offset to the actual PLT entry. */
6723 value = -4;
6724 break;
31312f95 6725
13ae64f3
JJ		 6726 case BFD_RELOC_386_TLS_GD:
6727 case BFD_RELOC_386_TLS_LDM:
13ae64f3 6728 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6729 case BFD_RELOC_386_TLS_IE:
6730 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 6731 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 6732 case BFD_RELOC_X86_64_TLSGD:
6733 case BFD_RELOC_X86_64_TLSLD:
6734 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 6735 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 6736 value = 0; /* Fully resolved at runtime. No addend. */
6737 /* Fallthrough */
6738 case BFD_RELOC_386_TLS_LE:
6739 case BFD_RELOC_386_TLS_LDO_32:
6740 case BFD_RELOC_386_TLS_LE_32:
6741 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6742 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 6743 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 6744 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 6745 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6746 break;
6747
67a4f2b7
AO		 6748 case BFD_RELOC_386_TLS_DESC_CALL:
6749 case BFD_RELOC_X86_64_TLSDESC_CALL:
6750 value = 0; /* Fully resolved at runtime. No addend. */
6751 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6752 fixP->fx_done = 0;
6753 return;
6754
00f7efb6
JJ		 6755 case BFD_RELOC_386_GOT32:
6756 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 6757 value = 0; /* Fully resolved at runtime. No addend. */
6758 break;
47926f60
KH		 6759
6760 case BFD_RELOC_VTABLE_INHERIT:
6761 case BFD_RELOC_VTABLE_ENTRY:
6762 fixP->fx_done = 0;
94f592af 6763 return;
47926f60
KH		 6764
6765 default:
6766 break;
6767 }
6768#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 6769 *valP = value;
f86103b7 6770#endif /* !defined (TE_Mach) */
3e73aa7c 6771
3e73aa7c 6772 /* Are we finished with this relocation now? */
c6682705 6773 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 6774 fixP->fx_done = 1;
6775 else if (use_rela_relocations)
6776 {
6777 fixP->fx_no_overflow = 1;
062cd5e7
AS		 6778 /* Remember value for tc_gen_reloc. */
6779 fixP->fx_addnumber = value;
3e73aa7c
JH		 6780 value = 0;
6781 }
f86103b7 6782
94f592af 6783 md_number_to_chars (p, value, fixP->fx_size);
252b5132 6784}
252b5132 6785\f
252b5132
RH		 6786#define MAX_LITTLENUMS 6
6787
47926f60
KH		 6788/* Turn the string pointed to by litP into a floating point constant
6789 of type TYPE, and emit the appropriate bytes. The number of
6790 LITTLENUMS emitted is stored in *SIZEP. An error message is
6791 returned, or NULL on OK. */
6792
252b5132
RH		 6793char *
6794md_atof (type, litP, sizeP)
2ab9b79e 6795 int type;
252b5132
RH		 6796 char *litP;
6797 int *sizeP;
6798{
6799 int prec;
6800 LITTLENUM_TYPE words[MAX_LITTLENUMS];
6801 LITTLENUM_TYPE *wordP;
6802 char *t;
6803
6804 switch (type)
6805 {
6806 case 'f':
6807 case 'F':
6808 prec = 2;
6809 break;
6810
6811 case 'd':
6812 case 'D':
6813 prec = 4;
6814 break;
6815
6816 case 'x':
6817 case 'X':
6818 prec = 5;
6819 break;
6820
6821 default:
6822 *sizeP = 0;
6823 return _("Bad call to md_atof ()");
6824 }
6825 t = atof_ieee (input_line_pointer, type, words);
6826 if (t)
6827 input_line_pointer = t;
6828
6829 *sizeP = prec * sizeof (LITTLENUM_TYPE);
6830 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
6831 the bigendian 386. */
6832 for (wordP = words + prec - 1; prec--;)
6833 {
6834 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
6835 litP += sizeof (LITTLENUM_TYPE);
6836 }
6837 return 0;
6838}
6839\f
2d545b82 6840static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 6841
252b5132 6842static char *
e3bb37b5 6843output_invalid (int c)
252b5132 6844{
3882b010 6845 if (ISPRINT (c))
f9f21a03
L		 6846 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6847 "'%c'", c);
252b5132 6848 else
f9f21a03 6849 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 6850 "(0x%x)", (unsigned char) c);
252b5132
RH		 6851 return output_invalid_buf;
6852}
6853
af6bdddf 6854/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 6855
6856static const reg_entry *
4d1bb795 6857parse_real_register (char *reg_string, char **end_op)
252b5132 6858{
af6bdddf
AM		 6859 char *s = reg_string;
6860 char *p;
252b5132
RH		 6861 char reg_name_given[MAX_REG_NAME_SIZE + 1];
6862 const reg_entry *r;
6863
6864 /* Skip possible REGISTER_PREFIX and possible whitespace. */
6865 if (*s == REGISTER_PREFIX)
6866 ++s;
6867
6868 if (is_space_char (*s))
6869 ++s;
6870
6871 p = reg_name_given;
af6bdddf 6872 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 6873 {
6874 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 6875 return (const reg_entry *) NULL;
6876 s++;
252b5132
RH		 6877 }
6878
6588847e
DN		 6879 /* For naked regs, make sure that we are not dealing with an identifier.
6880 This prevents confusing an identifier like `eax_var' with register
6881 `eax'. */
6882 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
6883 return (const reg_entry *) NULL;
6884
af6bdddf 6885 *end_op = s;
252b5132
RH		 6886
6887 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
6888
5f47d35b 6889 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 6890 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 6891 {
5f47d35b
AM		 6892 if (is_space_char (*s))
6893 ++s;
6894 if (*s == '(')
6895 {
af6bdddf 6896 ++s;
5f47d35b
AM		 6897 if (is_space_char (*s))
6898 ++s;
6899 if (*s >= '0' && *s <= '7')
6900 {
db557034 6901 int fpr = *s - '0';
af6bdddf 6902 ++s;
5f47d35b
AM		 6903 if (is_space_char (*s))
6904 ++s;
6905 if (*s == ')')
6906 {
6907 *end_op = s + 1;
db557034
AM		 6908 r = hash_find (reg_hash, "st(0)");
6909 know (r);
6910 return r + fpr;
5f47d35b 6911 }
5f47d35b 6912 }
47926f60 6913 /* We have "%st(" then garbage. */
5f47d35b
AM		 6914 return (const reg_entry *) NULL;
6915 }
6916 }
6917
db51cc60
L		 6918 /* Don't allow fake index register unless allow_index_reg isn't 0. */
6919 if (r != NULL
6920 && !allow_index_reg
6921 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
6922 return (const reg_entry *) NULL;
6923
1ae00879 6924 if (r != NULL
d946b91f 6925 && ((r->reg_flags & (RegRex64 | RegRex))
40fb9820
L		 6926 || r->reg_type.bitfield.reg64)
6927 && (!cpu_arch_flags.bitfield.cpulm
c6fb90c8 6928 || !UINTS_EQUAL (r->reg_type, control))
1ae00879 6929 && flag_code != CODE_64BIT)
20f0a1fc 6930 return (const reg_entry *) NULL;
1ae00879 6931
252b5132
RH		 6932 return r;
6933}
4d1bb795
JB		 6934
6935/* REG_STRING starts *before* REGISTER_PREFIX. */
6936
6937static const reg_entry *
6938parse_register (char *reg_string, char **end_op)
6939{
6940 const reg_entry *r;
6941
6942 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
6943 r = parse_real_register (reg_string, end_op);
6944 else
6945 r = NULL;
6946 if (!r)
6947 {
6948 char *save = input_line_pointer;
6949 char c;
6950 symbolS *symbolP;
6951
6952 input_line_pointer = reg_string;
6953 c = get_symbol_end ();
6954 symbolP = symbol_find (reg_string);
6955 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
6956 {
6957 const expressionS *e = symbol_get_value_expression (symbolP);
6958
6959 know (e->X_op == O_register);
4eed87de 6960 know (e->X_add_number >= 0
c3fe08fa 6961 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 6962 r = i386_regtab + e->X_add_number;
6963 *end_op = input_line_pointer;
6964 }
6965 *input_line_pointer = c;
6966 input_line_pointer = save;
6967 }
6968 return r;
6969}
6970
6971int
6972i386_parse_name (char *name, expressionS *e, char *nextcharP)
6973{
6974 const reg_entry *r;
6975 char *end = input_line_pointer;
6976
6977 *end = *nextcharP;
6978 r = parse_register (name, &input_line_pointer);
6979 if (r && end <= input_line_pointer)
6980 {
6981 *nextcharP = *input_line_pointer;
6982 *input_line_pointer = 0;
6983 e->X_op = O_register;
6984 e->X_add_number = r - i386_regtab;
6985 return 1;
6986 }
6987 input_line_pointer = end;
6988 *end = 0;
6989 return 0;
6990}
6991
6992void
6993md_operand (expressionS *e)
6994{
6995 if (*input_line_pointer == REGISTER_PREFIX)
6996 {
6997 char *end;
6998 const reg_entry *r = parse_real_register (input_line_pointer, &end);
6999
7000 if (r)
7001 {
7002 e->X_op = O_register;
7003 e->X_add_number = r - i386_regtab;
7004 input_line_pointer = end;
7005 }
7006 }
7007}
7008
252b5132 7009\f
4cc782b5 7010#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7011const char *md_shortopts = "kVQ:sqn";
252b5132 7012#else
12b55ccc 7013const char *md_shortopts = "qn";
252b5132 7014#endif
6e0b89ee 7015
3e73aa7c 7016#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7017#define OPTION_64 (OPTION_MD_BASE + 1)
7018#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7019#define OPTION_MARCH (OPTION_MD_BASE + 3)
7020#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714 7021
99ad8390
NC		 7022struct option md_longopts[] =
7023{
3e73aa7c 7024 {"32", no_argument, NULL, OPTION_32},
99ad8390 7025#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 7026 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7027#endif
b3b91714 7028 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7029 {"march", required_argument, NULL, OPTION_MARCH},
7030 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH		 7031 {NULL, no_argument, NULL, 0}
7032};
7033size_t md_longopts_size = sizeof (md_longopts);
7034
7035int
9103f4f4 7036md_parse_option (int c, char *arg)
252b5132 7037{
9103f4f4
L		 7038 unsigned int i;
7039
252b5132
RH		 7040 switch (c)
7041 {
12b55ccc
L		 7042 case 'n':
7043 optimize_align_code = 0;
7044 break;
7045
a38cf1db
AM		 7046 case 'q':
7047 quiet_warnings = 1;
252b5132
RH		 7048 break;
7049
7050#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7051 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7052 should be emitted or not. FIXME: Not implemented. */
7053 case 'Q':
252b5132
RH		 7054 break;
7055
7056 /* -V: SVR4 argument to print version ID. */
7057 case 'V':
7058 print_version_id ();
7059 break;
7060
a38cf1db
AM		 7061 /* -k: Ignore for FreeBSD compatibility. */
7062 case 'k':
252b5132 7063 break;
4cc782b5
ILT		 7064
7065 case 's':
7066 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 7067 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 7068 break;
99ad8390
NC		 7069#endif
7070#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 7071 case OPTION_64:
7072 {
7073 const char **list, **l;
7074
3e73aa7c
JH		 7075 list = bfd_target_list ();
7076 for (l = list; *l != NULL; l++)
8620418b 7077 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 7078 || strcmp (*l, "coff-x86-64") == 0
7079 || strcmp (*l, "pe-x86-64") == 0
7080 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 7081 {
7082 default_arch = "x86_64";
7083 break;
7084 }
3e73aa7c 7085 if (*l == NULL)
6e0b89ee 7086 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 7087 free (list);
7088 }
7089 break;
7090#endif
252b5132 7091
6e0b89ee
AM		 7092 case OPTION_32:
7093 default_arch = "i386";
7094 break;
7095
b3b91714
AM		 7096 case OPTION_DIVIDE:
7097#ifdef SVR4_COMMENT_CHARS
7098 {
7099 char *n, *t;
7100 const char *s;
7101
7102 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7103 t = n;
7104 for (s = i386_comment_chars; *s != '\0'; s++)
7105 if (*s != '/')
7106 *t++ = *s;
7107 *t = '\0';
7108 i386_comment_chars = n;
7109 }
7110#endif
7111 break;
7112
9103f4f4
L		 7113 case OPTION_MARCH:
7114 if (*arg == '.')
7115 as_fatal (_("Invalid -march= option: `%s'"), arg);
7116 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7117 {
7118 if (strcmp (arg, cpu_arch [i].name) == 0)
7119 {
ccc9c027 7120 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 7121 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 7122 if (!cpu_arch_tune_set)
7123 {
7124 cpu_arch_tune = cpu_arch_isa;
7125 cpu_arch_tune_flags = cpu_arch_isa_flags;
7126 }
9103f4f4
L		 7127 break;
7128 }
7129 }
7130 if (i >= ARRAY_SIZE (cpu_arch))
7131 as_fatal (_("Invalid -march= option: `%s'"), arg);
7132 break;
7133
7134 case OPTION_MTUNE:
7135 if (*arg == '.')
7136 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7137 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7138 {
7139 if (strcmp (arg, cpu_arch [i].name) == 0)
7140 {
ccc9c027 7141 cpu_arch_tune_set = 1;
9103f4f4
L		 7142 cpu_arch_tune = cpu_arch [i].type;
7143 cpu_arch_tune_flags = cpu_arch[i].flags;
7144 break;
7145 }
7146 }
7147 if (i >= ARRAY_SIZE (cpu_arch))
7148 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7149 break;
7150
252b5132
RH		 7151 default:
7152 return 0;
7153 }
7154 return 1;
7155}
7156
7157void
7158md_show_usage (stream)
7159 FILE *stream;
7160{
4cc782b5
ILT		 7161#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7162 fprintf (stream, _("\
a38cf1db
AM		 7163 -Q ignored\n\
7164 -V print assembler version number\n\
b3b91714
AM		 7165 -k ignored\n"));
7166#endif
7167 fprintf (stream, _("\
12b55ccc 7168 -n Do not optimize code alignment\n\
b3b91714
AM		 7169 -q quieten some warnings\n"));
7170#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7171 fprintf (stream, _("\
a38cf1db 7172 -s ignored\n"));
b3b91714 7173#endif
751d281c
L		 7174#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7175 fprintf (stream, _("\
7176 --32/--64 generate 32bit/64bit code\n"));
7177#endif
b3b91714
AM		 7178#ifdef SVR4_COMMENT_CHARS
7179 fprintf (stream, _("\
7180 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 7181#else
7182 fprintf (stream, _("\
b3b91714 7183 --divide ignored\n"));
4cc782b5 7184#endif
9103f4f4
L		 7185 fprintf (stream, _("\
7186 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
7187 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
4eed87de 7188 core, core2, k6, athlon, k8, generic32, generic64\n"));
9103f4f4 7189
252b5132
RH		 7190}
7191
3e73aa7c 7192#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 7193 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH		 7194
7195/* Pick the target format to use. */
7196
47926f60 7197const char *
e3bb37b5 7198i386_target_format (void)
252b5132 7199{
3e73aa7c 7200 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 7201 {
7202 set_code_flag (CODE_64BIT);
c6fb90c8 7203 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
40fb9820
L		 7204 {
7205 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7206 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7207 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7208 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7209 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7210 cpu_arch_isa_flags.bitfield.cpui686 = 1;
7211 cpu_arch_isa_flags.bitfield.cpup4 = 1;
7212 cpu_arch_isa_flags.bitfield.cpummx= 1;
7213 cpu_arch_isa_flags.bitfield.cpummx2 = 1;
7214 cpu_arch_isa_flags.bitfield.cpusse = 1;
7215 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7216 }
c6fb90c8 7217 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
40fb9820
L		 7218 {
7219 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7220 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7221 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7222 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7223 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7224 cpu_arch_tune_flags.bitfield.cpui686 = 1;
7225 cpu_arch_tune_flags.bitfield.cpup4 = 1;
7226 cpu_arch_tune_flags.bitfield.cpummx= 1;
7227 cpu_arch_tune_flags.bitfield.cpummx2 = 1;
7228 cpu_arch_tune_flags.bitfield.cpusse = 1;
7229 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7230 }
9103f4f4 7231 }
3e73aa7c 7232 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 7233 {
7234 set_code_flag (CODE_32BIT);
c6fb90c8 7235 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
40fb9820
L		 7236 {
7237 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7238 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7239 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7240 }
c6fb90c8 7241 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
40fb9820
L		 7242 {
7243 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7244 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7245 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7246 }
9103f4f4 7247 }
3e73aa7c
JH		 7248 else
7249 as_fatal (_("Unknown architecture"));
252b5132
RH		 7250 switch (OUTPUT_FLAVOR)
7251 {
872ce6ff
L		 7252#ifdef TE_PEP
7253 case bfd_target_coff_flavour:
7254 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
7255 break;
7256#endif
4c63da97
AM		 7257#ifdef OBJ_MAYBE_AOUT
7258 case bfd_target_aout_flavour:
47926f60 7259 return AOUT_TARGET_FORMAT;
4c63da97
AM		 7260#endif
7261#ifdef OBJ_MAYBE_COFF
252b5132
RH		 7262 case bfd_target_coff_flavour:
7263 return "coff-i386";
4c63da97 7264#endif
3e73aa7c 7265#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 7266 case bfd_target_elf_flavour:
3e73aa7c 7267 {
e5cb08ac 7268 if (flag_code == CODE_64BIT)
4fa24527
JB		 7269 {
7270 object_64bit = 1;
7271 use_rela_relocations = 1;
7272 }
9d7cbccd 7273 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 7274 }
4c63da97 7275#endif
252b5132
RH		 7276 default:
7277 abort ();
7278 return NULL;
7279 }
7280}
7281
47926f60 7282#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 7283
7284#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 7285void
7286i386_elf_emit_arch_note (void)
a847613f 7287{
718ddfc0 7288 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 7289 {
7290 char *p;
7291 asection *seg = now_seg;
7292 subsegT subseg = now_subseg;
7293 Elf_Internal_Note i_note;
7294 Elf_External_Note e_note;
7295 asection *note_secp;
7296 int len;
7297
7298 /* Create the .note section. */
7299 note_secp = subseg_new (".note", 0);
7300 bfd_set_section_flags (stdoutput,
7301 note_secp,
7302 SEC_HAS_CONTENTS | SEC_READONLY);
7303
7304 /* Process the arch string. */
7305 len = strlen (cpu_arch_name);
7306
7307 i_note.namesz = len + 1;
7308 i_note.descsz = 0;
7309 i_note.type = NT_ARCH;
7310 p = frag_more (sizeof (e_note.namesz));
7311 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
7312 p = frag_more (sizeof (e_note.descsz));
7313 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
7314 p = frag_more (sizeof (e_note.type));
7315 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
7316 p = frag_more (len + 1);
7317 strcpy (p, cpu_arch_name);
7318
7319 frag_align (2, 0, 0);
7320
7321 subseg_set (seg, subseg);
7322 }
7323}
7324#endif
252b5132 7325\f
252b5132
RH		 7326symbolS *
7327md_undefined_symbol (name)
7328 char *name;
7329{
18dc2407
ILT		 7330 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
7331 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
7332 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
7333 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 7334 {
7335 if (!GOT_symbol)
7336 {
7337 if (symbol_find (name))
7338 as_bad (_("GOT already in symbol table"));
7339 GOT_symbol = symbol_new (name, undefined_section,
7340 (valueT) 0, &zero_address_frag);
7341 };
7342 return GOT_symbol;
7343 }
252b5132
RH		 7344 return 0;
7345}
7346
7347/* Round up a section size to the appropriate boundary. */
47926f60 7348
252b5132
RH		 7349valueT
7350md_section_align (segment, size)
ab9da554 7351 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 7352 valueT size;
7353{
4c63da97
AM		 7354#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7355 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
7356 {
7357 /* For a.out, force the section size to be aligned. If we don't do
7358 this, BFD will align it for us, but it will not write out the
7359 final bytes of the section. This may be a bug in BFD, but it is
7360 easier to fix it here since that is how the other a.out targets
7361 work. */
7362 int align;
7363
7364 align = bfd_get_section_alignment (stdoutput, segment);
7365 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7366 }
252b5132
RH		 7367#endif
7368
7369 return size;
7370}
7371
7372/* On the i386, PC-relative offsets are relative to the start of the
7373 next instruction. That is, the address of the offset, plus its
7374 size, since the offset is always the last part of the insn. */
7375
7376long
e3bb37b5 7377md_pcrel_from (fixS *fixP)
252b5132
RH		 7378{
7379 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
7380}
7381
7382#ifndef I386COFF
7383
7384static void
e3bb37b5 7385s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 7386{
29b0f896 7387 int temp;
252b5132 7388
8a75718c
JB		 7389#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7390 if (IS_ELF)
7391 obj_elf_section_change_hook ();
7392#endif
252b5132
RH		 7393 temp = get_absolute_expression ();
7394 subseg_set (bss_section, (subsegT) temp);
7395 demand_empty_rest_of_line ();
7396}
7397
7398#endif
7399
252b5132 7400void
e3bb37b5 7401i386_validate_fix (fixS *fixp)
252b5132
RH		 7402{
7403 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
7404 {
23df1078
JH		 7405 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
7406 {
4fa24527 7407 if (!object_64bit)
23df1078
JH		 7408 abort ();
7409 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
7410 }
7411 else
7412 {
4fa24527 7413 if (!object_64bit)
d6ab8113
JB		 7414 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
7415 else
7416 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 7417 }
252b5132
RH		 7418 fixp->fx_subsy = 0;
7419 }
7420}
7421
252b5132
RH		 7422arelent *
7423tc_gen_reloc (section, fixp)
ab9da554 7424 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 7425 fixS *fixp;
7426{
7427 arelent *rel;
7428 bfd_reloc_code_real_type code;
7429
7430 switch (fixp->fx_r_type)
7431 {
3e73aa7c
JH		 7432 case BFD_RELOC_X86_64_PLT32:
7433 case BFD_RELOC_X86_64_GOT32:
7434 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 7435 case BFD_RELOC_386_PLT32:
7436 case BFD_RELOC_386_GOT32:
7437 case BFD_RELOC_386_GOTOFF:
7438 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 7439 case BFD_RELOC_386_TLS_GD:
7440 case BFD_RELOC_386_TLS_LDM:
7441 case BFD_RELOC_386_TLS_LDO_32:
7442 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7443 case BFD_RELOC_386_TLS_IE:
7444 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 7445 case BFD_RELOC_386_TLS_LE_32:
7446 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 7447 case BFD_RELOC_386_TLS_GOTDESC:
7448 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 7449 case BFD_RELOC_X86_64_TLSGD:
7450 case BFD_RELOC_X86_64_TLSLD:
7451 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7452 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 7453 case BFD_RELOC_X86_64_GOTTPOFF:
7454 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 7455 case BFD_RELOC_X86_64_TPOFF64:
7456 case BFD_RELOC_X86_64_GOTOFF64:
7457 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 7458 case BFD_RELOC_X86_64_GOT64:
7459 case BFD_RELOC_X86_64_GOTPCREL64:
7460 case BFD_RELOC_X86_64_GOTPC64:
7461 case BFD_RELOC_X86_64_GOTPLT64:
7462 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 7463 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7464 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 7465 case BFD_RELOC_RVA:
7466 case BFD_RELOC_VTABLE_ENTRY:
7467 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 7468#ifdef TE_PE
7469 case BFD_RELOC_32_SECREL:
7470#endif
252b5132
RH		 7471 code = fixp->fx_r_type;
7472 break;
dbbaec26
L		 7473 case BFD_RELOC_X86_64_32S:
7474 if (!fixp->fx_pcrel)
7475 {
7476 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7477 code = fixp->fx_r_type;
7478 break;
7479 }
252b5132 7480 default:
93382f6d 7481 if (fixp->fx_pcrel)
252b5132 7482 {
93382f6d
AM		 7483 switch (fixp->fx_size)
7484 {
7485 default:
b091f402
AM		 7486 as_bad_where (fixp->fx_file, fixp->fx_line,
7487 _("can not do %d byte pc-relative relocation"),
7488 fixp->fx_size);
93382f6d
AM		 7489 code = BFD_RELOC_32_PCREL;
7490 break;
7491 case 1: code = BFD_RELOC_8_PCREL; break;
7492 case 2: code = BFD_RELOC_16_PCREL; break;
7493 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 7494#ifdef BFD64
7495 case 8: code = BFD_RELOC_64_PCREL; break;
7496#endif
93382f6d
AM		 7497 }
7498 }
7499 else
7500 {
7501 switch (fixp->fx_size)
7502 {
7503 default:
b091f402
AM		 7504 as_bad_where (fixp->fx_file, fixp->fx_line,
7505 _("can not do %d byte relocation"),
7506 fixp->fx_size);
93382f6d
AM		 7507 code = BFD_RELOC_32;
7508 break;
7509 case 1: code = BFD_RELOC_8; break;
7510 case 2: code = BFD_RELOC_16; break;
7511 case 4: code = BFD_RELOC_32; break;
937149dd 7512#ifdef BFD64
3e73aa7c 7513 case 8: code = BFD_RELOC_64; break;
937149dd 7514#endif
93382f6d 7515 }
252b5132
RH		 7516 }
7517 break;
7518 }
252b5132 7519
d182319b
JB		 7520 if ((code == BFD_RELOC_32
7521 || code == BFD_RELOC_32_PCREL
7522 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 7523 && GOT_symbol
7524 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 7525 {
4fa24527 7526 if (!object_64bit)
d6ab8113
JB		 7527 code = BFD_RELOC_386_GOTPC;
7528 else
7529 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 7530 }
7b81dfbb
AJ		 7531 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7532 && GOT_symbol
7533 && fixp->fx_addsy == GOT_symbol)
7534 {
7535 code = BFD_RELOC_X86_64_GOTPC64;
7536 }
252b5132
RH		 7537
7538 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 7539 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7540 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 7541
7542 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 7543
3e73aa7c
JH		 7544 if (!use_rela_relocations)
7545 {
7546 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7547 vtable entry to be used in the relocation's section offset. */
7548 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7549 rel->address = fixp->fx_offset;
252b5132 7550
c6682705 7551 rel->addend = 0;
3e73aa7c
JH		 7552 }
7553 /* Use the rela in 64bit mode. */
252b5132 7554 else
3e73aa7c 7555 {
062cd5e7
AS		 7556 if (!fixp->fx_pcrel)
7557 rel->addend = fixp->fx_offset;
7558 else
7559 switch (code)
7560 {
7561 case BFD_RELOC_X86_64_PLT32:
7562 case BFD_RELOC_X86_64_GOT32:
7563 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 7564 case BFD_RELOC_X86_64_TLSGD:
7565 case BFD_RELOC_X86_64_TLSLD:
7566 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 7567 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7568 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 7569 rel->addend = fixp->fx_offset - fixp->fx_size;
7570 break;
7571 default:
7572 rel->addend = (section->vma
7573 - fixp->fx_size
7574 + fixp->fx_addnumber
7575 + md_pcrel_from (fixp));
7576 break;
7577 }
3e73aa7c
JH		 7578 }
7579
252b5132
RH		 7580 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7581 if (rel->howto == NULL)
7582 {
7583 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 7584 _("cannot represent relocation type %s"),
252b5132
RH		 7585 bfd_get_reloc_code_name (code));
7586 /* Set howto to a garbage value so that we can keep going. */
7587 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7588 assert (rel->howto != NULL);
7589 }
7590
7591 return rel;
7592}
7593
64a0c779
DN		 7594\f
7595/* Parse operands using Intel syntax. This implements a recursive descent
7596 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7597 Programmer's Guide.
7598
7599 FIXME: We do not recognize the full operand grammar defined in the MASM
7600 documentation. In particular, all the structure/union and
7601 high-level macro operands are missing.
7602
7603 Uppercase words are terminals, lower case words are non-terminals.
7604 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7605 bars '|' denote choices. Most grammar productions are implemented in
7606 functions called 'intel_<production>'.
7607
7608 Initial production is 'expr'.
7609
9306ca4a 7610 addOp + | -
64a0c779
DN		 7611
7612 alpha [a-zA-Z]
7613
9306ca4a
JB		 7614 binOp & | AND | \| | OR | ^ | XOR
7615
64a0c779
DN		 7616 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7617
7618 constant digits [[ radixOverride ]]
7619
9306ca4a 7620 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 7621
7622 digits decdigit
b77a7acd
AJ		 7623 | digits decdigit
7624 | digits hexdigit
64a0c779
DN		 7625
7626 decdigit [0-9]
7627
9306ca4a
JB		 7628 e04 e04 addOp e05
7629 | e05
7630
7631 e05 e05 binOp e06
b77a7acd 7632 | e06
64a0c779
DN		 7633
7634 e06 e06 mulOp e09
b77a7acd 7635 | e09
64a0c779
DN		 7636
7637 e09 OFFSET e10
a724f0f4
JB		 7638 | SHORT e10
7639 | + e10
7640 | - e10
9306ca4a
JB		 7641 | ~ e10
7642 | NOT e10
64a0c779
DN		 7643 | e09 PTR e10
7644 | e09 : e10
7645 | e10
7646
7647 e10 e10 [ expr ]
b77a7acd 7648 | e11
64a0c779
DN		 7649
7650 e11 ( expr )
b77a7acd 7651 | [ expr ]
64a0c779
DN		 7652 | constant
7653 | dataType
7654 | id
7655 | $
7656 | register
7657
a724f0f4 7658 => expr expr cmpOp e04
9306ca4a 7659 | e04
64a0c779
DN		 7660
7661 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 7662 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 7663
7664 hexdigit a | b | c | d | e | f
b77a7acd 7665 | A | B | C | D | E | F
64a0c779
DN		 7666
7667 id alpha
b77a7acd 7668 | id alpha
64a0c779
DN		 7669 | id decdigit
7670
9306ca4a 7671 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 7672
7673 quote " | '
7674
7675 register specialRegister
b77a7acd 7676 | gpRegister
64a0c779
DN		 7677 | byteRegister
7678
7679 segmentRegister CS | DS | ES | FS | GS | SS
7680
9306ca4a 7681 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 7682 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 7683 | TR3 | TR4 | TR5 | TR6 | TR7
7684
64a0c779
DN		 7685 We simplify the grammar in obvious places (e.g., register parsing is
7686 done by calling parse_register) and eliminate immediate left recursion
7687 to implement a recursive-descent parser.
7688
a724f0f4
JB		 7689 expr e04 expr'
7690
7691 expr' cmpOp e04 expr'
7692 | Empty
9306ca4a
JB		 7693
7694 e04 e05 e04'
7695
7696 e04' addOp e05 e04'
7697 | Empty
64a0c779
DN		 7698
7699 e05 e06 e05'
7700
9306ca4a 7701 e05' binOp e06 e05'
b77a7acd 7702 | Empty
64a0c779
DN		 7703
7704 e06 e09 e06'
7705
7706 e06' mulOp e09 e06'
b77a7acd 7707 | Empty
64a0c779
DN		 7708
7709 e09 OFFSET e10 e09'
a724f0f4
JB		 7710 | SHORT e10'
7711 | + e10'
7712 | - e10'
7713 | ~ e10'
7714 | NOT e10'
b77a7acd 7715 | e10 e09'
64a0c779
DN		 7716
7717 e09' PTR e10 e09'
b77a7acd 7718 | : e10 e09'
64a0c779
DN		 7719 | Empty
7720
7721 e10 e11 e10'
7722
7723 e10' [ expr ] e10'
b77a7acd 7724 | Empty
64a0c779
DN		 7725
7726 e11 ( expr )
b77a7acd 7727 | [ expr ]
64a0c779
DN		 7728 | BYTE
7729 | WORD
7730 | DWORD
9306ca4a 7731 | FWORD
64a0c779 7732 | QWORD
9306ca4a
JB		 7733 | TBYTE
7734 | OWORD
7735 | XMMWORD
64a0c779
DN		 7736 | .
7737 | $
7738 | register
7739 | id
7740 | constant */
7741
7742/* Parsing structure for the intel syntax parser. Used to implement the
7743 semantic actions for the operand grammar. */
7744struct intel_parser_s
7745 {
7746 char *op_string; /* The string being parsed. */
7747 int got_a_float; /* Whether the operand is a float. */
4a1805b1 7748 int op_modifier; /* Operand modifier. */
64a0c779 7749 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 7750 int in_offset; /* >=1 if parsing operand of offset. */
7751 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 7752 const reg_entry *reg; /* Last register reference found. */
7753 char *disp; /* Displacement string being built. */
a724f0f4 7754 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 7755 };
7756
7757static struct intel_parser_s intel_parser;
7758
7759/* Token structure for parsing intel syntax. */
7760struct intel_token
7761 {
7762 int code; /* Token code. */
7763 const reg_entry *reg; /* Register entry for register tokens. */
7764 char *str; /* String representation. */
7765 };
7766
7767static struct intel_token cur_token, prev_token;
7768
50705ef4
AM		 7769/* Token codes for the intel parser. Since T_SHORT is already used
7770 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 7771#define T_NIL -1
7772#define T_CONST 1
7773#define T_REG 2
7774#define T_BYTE 3
7775#define T_WORD 4
9306ca4a
JB		 7776#define T_DWORD 5
7777#define T_FWORD 6
7778#define T_QWORD 7
7779#define T_TBYTE 8
7780#define T_XMMWORD 9
50705ef4 7781#undef T_SHORT
9306ca4a
JB		 7782#define T_SHORT 10
7783#define T_OFFSET 11
7784#define T_PTR 12
7785#define T_ID 13
7786#define T_SHL 14
7787#define T_SHR 15
64a0c779
DN		 7788
7789/* Prototypes for intel parser functions. */
e3bb37b5
L		 7790static int intel_match_token (int);
7791static void intel_putback_token (void);
7792static void intel_get_token (void);
7793static int intel_expr (void);
7794static int intel_e04 (void);
7795static int intel_e05 (void);
7796static int intel_e06 (void);
7797static int intel_e09 (void);
7798static int intel_e10 (void);
7799static int intel_e11 (void);
64a0c779 7800
64a0c779 7801static int
e3bb37b5 7802i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 7803{
7804 int ret;
7805 char *p;
7806
a724f0f4
JB		 7807 p = intel_parser.op_string = xstrdup (operand_string);
7808 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
7809
7810 for (;;)
64a0c779 7811 {
a724f0f4
JB		 7812 /* Initialize token holders. */
7813 cur_token.code = prev_token.code = T_NIL;
7814 cur_token.reg = prev_token.reg = NULL;
7815 cur_token.str = prev_token.str = NULL;
7816
7817 /* Initialize parser structure. */
7818 intel_parser.got_a_float = got_a_float;
7819 intel_parser.op_modifier = 0;
7820 intel_parser.is_mem = 0;
7821 intel_parser.in_offset = 0;
7822 intel_parser.in_bracket = 0;
7823 intel_parser.reg = NULL;
7824 intel_parser.disp[0] = '\0';
7825 intel_parser.next_operand = NULL;
7826
7827 /* Read the first token and start the parser. */
7828 intel_get_token ();
7829 ret = intel_expr ();
7830
7831 if (!ret)
7832 break;
7833
9306ca4a
JB		 7834 if (cur_token.code != T_NIL)
7835 {
7836 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
7837 current_templates->start->name, cur_token.str);
7838 ret = 0;
7839 }
64a0c779
DN		 7840 /* If we found a memory reference, hand it over to i386_displacement
7841 to fill in the rest of the operand fields. */
9306ca4a 7842 else if (intel_parser.is_mem)
64a0c779
DN		 7843 {
7844 if ((i.mem_operands == 1
40fb9820 7845 && !current_templates->start->opcode_modifier.isstring)
64a0c779
DN		 7846 || i.mem_operands == 2)
7847 {
7848 as_bad (_("too many memory references for '%s'"),
7849 current_templates->start->name);
7850 ret = 0;
7851 }
7852 else
7853 {
7854 char *s = intel_parser.disp;
7855 i.mem_operands++;
7856
a724f0f4
JB		 7857 if (!quiet_warnings && intel_parser.is_mem < 0)
7858 /* See the comments in intel_bracket_expr. */
7859 as_warn (_("Treating `%s' as memory reference"), operand_string);
7860
64a0c779
DN		 7861 /* Add the displacement expression. */
7862 if (*s != '\0')
a4622f40
AM		 7863 ret = i386_displacement (s, s + strlen (s));
7864 if (ret)
a724f0f4
JB		 7865 {
7866 /* Swap base and index in 16-bit memory operands like
7867 [si+bx]. Since i386_index_check is also used in AT&T
7868 mode we have to do that here. */
7869 if (i.base_reg
7870 && i.index_reg
40fb9820
L		 7871 && i.base_reg->reg_type.bitfield.reg16
7872 && i.index_reg->reg_type.bitfield.reg16
a724f0f4
JB		 7873 && i.base_reg->reg_num >= 6
7874 && i.index_reg->reg_num < 6)
7875 {
7876 const reg_entry *base = i.index_reg;
7877
7878 i.index_reg = i.base_reg;
7879 i.base_reg = base;
7880 }
7881 ret = i386_index_check (operand_string);
7882 }
64a0c779
DN		 7883 }
7884 }
7885
7886 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 7887 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 7888 || intel_parser.reg == NULL)
7889 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 7890
7891 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 7892 ret = 0;
a724f0f4
JB		 7893 if (!ret || !intel_parser.next_operand)
7894 break;
7895 intel_parser.op_string = intel_parser.next_operand;
7896 this_operand = i.operands++;
64a0c779
DN		 7897 }
7898
7899 free (p);
7900 free (intel_parser.disp);
7901
7902 return ret;
7903}
7904
a724f0f4
JB		 7905#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
7906
7907/* expr e04 expr'
7908
7909 expr' cmpOp e04 expr'
7910 | Empty */
64a0c779 7911static int
e3bb37b5 7912intel_expr (void)
64a0c779 7913{
a724f0f4
JB		 7914 /* XXX Implement the comparison operators. */
7915 return intel_e04 ();
9306ca4a
JB		 7916}
7917
a724f0f4 7918/* e04 e05 e04'
9306ca4a 7919
a724f0f4 7920 e04' addOp e05 e04'
9306ca4a
JB		 7921 | Empty */
7922static int
e3bb37b5 7923intel_e04 (void)
9306ca4a 7924{
a724f0f4 7925 int nregs = -1;
9306ca4a 7926
a724f0f4 7927 for (;;)
9306ca4a 7928 {
a724f0f4
JB		 7929 if (!intel_e05())
7930 return 0;
9306ca4a 7931
a724f0f4
JB		 7932 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7933 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 7934
a724f0f4
JB		 7935 if (cur_token.code == '+')
7936 nregs = -1;
7937 else if (cur_token.code == '-')
7938 nregs = NUM_ADDRESS_REGS;
7939 else
7940 return 1;
64a0c779 7941
a724f0f4
JB		 7942 strcat (intel_parser.disp, cur_token.str);
7943 intel_match_token (cur_token.code);
7944 }
64a0c779
DN		 7945}
7946
64a0c779
DN		 7947/* e05 e06 e05'
7948
9306ca4a 7949 e05' binOp e06 e05'
64a0c779
DN		 7950 | Empty */
7951static int
e3bb37b5 7952intel_e05 (void)
64a0c779 7953{
a724f0f4 7954 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 7955
a724f0f4 7956 for (;;)
64a0c779 7957 {
a724f0f4
JB		 7958 if (!intel_e06())
7959 return 0;
7960
4eed87de
AM		 7961 if (cur_token.code == '&'
7962 || cur_token.code == '|'
7963 || cur_token.code == '^')
a724f0f4
JB		 7964 {
7965 char str[2];
7966
7967 str[0] = cur_token.code;
7968 str[1] = 0;
7969 strcat (intel_parser.disp, str);
7970 }
7971 else
7972 break;
9306ca4a 7973
64a0c779
DN		 7974 intel_match_token (cur_token.code);
7975
a724f0f4
JB		 7976 if (nregs < 0)
7977 nregs = ~nregs;
64a0c779 7978 }
a724f0f4
JB		 7979 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7980 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
7981 return 1;
4a1805b1 7982}
64a0c779
DN		 7983
7984/* e06 e09 e06'
7985
7986 e06' mulOp e09 e06'
b77a7acd 7987 | Empty */
64a0c779 7988static int
e3bb37b5 7989intel_e06 (void)
64a0c779 7990{
a724f0f4 7991 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 7992
a724f0f4 7993 for (;;)
64a0c779 7994 {
a724f0f4
JB		 7995 if (!intel_e09())
7996 return 0;
9306ca4a 7997
4eed87de
AM		 7998 if (cur_token.code == '*'
7999 || cur_token.code == '/'
8000 || cur_token.code == '%')
a724f0f4
JB		 8001 {
8002 char str[2];
9306ca4a 8003
a724f0f4
JB		 8004 str[0] = cur_token.code;
8005 str[1] = 0;
8006 strcat (intel_parser.disp, str);
8007 }
8008 else if (cur_token.code == T_SHL)
8009 strcat (intel_parser.disp, "<<");
8010 else if (cur_token.code == T_SHR)
8011 strcat (intel_parser.disp, ">>");
8012 else
8013 break;
9306ca4a 8014
64e74474 8015 intel_match_token (cur_token.code);
64a0c779 8016
a724f0f4
JB		 8017 if (nregs < 0)
8018 nregs = ~nregs;
64a0c779 8019 }
a724f0f4
JB		 8020 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8021 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
8022 return 1;
64a0c779
DN		 8023}
8024
a724f0f4
JB		 8025/* e09 OFFSET e09
8026 | SHORT e09
8027 | + e09
8028 | - e09
8029 | ~ e09
8030 | NOT e09
9306ca4a
JB		 8031 | e10 e09'
8032
64a0c779 8033 e09' PTR e10 e09'
b77a7acd 8034 | : e10 e09'
64a0c779
DN		 8035 | Empty */
8036static int
e3bb37b5 8037intel_e09 (void)
64a0c779 8038{
a724f0f4
JB		 8039 int nregs = ~NUM_ADDRESS_REGS;
8040 int in_offset = 0;
8041
8042 for (;;)
64a0c779 8043 {
a724f0f4
JB		 8044 /* Don't consume constants here. */
8045 if (cur_token.code == '+' || cur_token.code == '-')
8046 {
8047 /* Need to look one token ahead - if the next token
8048 is a constant, the current token is its sign. */
8049 int next_code;
8050
8051 intel_match_token (cur_token.code);
8052 next_code = cur_token.code;
8053 intel_putback_token ();
8054 if (next_code == T_CONST)
8055 break;
8056 }
8057
8058 /* e09 OFFSET e09 */
8059 if (cur_token.code == T_OFFSET)
8060 {
8061 if (!in_offset++)
8062 ++intel_parser.in_offset;
8063 }
8064
8065 /* e09 SHORT e09 */
8066 else if (cur_token.code == T_SHORT)
8067 intel_parser.op_modifier |= 1 << T_SHORT;
8068
8069 /* e09 + e09 */
8070 else if (cur_token.code == '+')
8071 strcat (intel_parser.disp, "+");
8072
8073 /* e09 - e09
8074 | ~ e09
8075 | NOT e09 */
8076 else if (cur_token.code == '-' || cur_token.code == '~')
8077 {
8078 char str[2];
64a0c779 8079
a724f0f4
JB		 8080 if (nregs < 0)
8081 nregs = ~nregs;
8082 str[0] = cur_token.code;
8083 str[1] = 0;
8084 strcat (intel_parser.disp, str);
8085 }
8086
8087 /* e09 e10 e09' */
8088 else
8089 break;
8090
8091 intel_match_token (cur_token.code);
64a0c779
DN		 8092 }
8093
a724f0f4 8094 for (;;)
9306ca4a 8095 {
a724f0f4
JB		 8096 if (!intel_e10 ())
8097 return 0;
9306ca4a 8098
a724f0f4
JB		 8099 /* e09' PTR e10 e09' */
8100 if (cur_token.code == T_PTR)
8101 {
8102 char suffix;
9306ca4a 8103
a724f0f4
JB		 8104 if (prev_token.code == T_BYTE)
8105 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 8106
a724f0f4
JB		 8107 else if (prev_token.code == T_WORD)
8108 {
8109 if (current_templates->start->name[0] == 'l'
8110 && current_templates->start->name[2] == 's'
8111 && current_templates->start->name[3] == 0)
8112 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8113 else if (intel_parser.got_a_float == 2) /* "fi..." */
8114 suffix = SHORT_MNEM_SUFFIX;
8115 else
8116 suffix = WORD_MNEM_SUFFIX;
8117 }
64a0c779 8118
a724f0f4
JB		 8119 else if (prev_token.code == T_DWORD)
8120 {
8121 if (current_templates->start->name[0] == 'l'
8122 && current_templates->start->name[2] == 's'
8123 && current_templates->start->name[3] == 0)
8124 suffix = WORD_MNEM_SUFFIX;
8125 else if (flag_code == CODE_16BIT
40fb9820
L		 8126 && (current_templates->start->opcode_modifier.jump
8127 || current_templates->start->opcode_modifier.jumpdword))
a724f0f4
JB		 8128 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8129 else if (intel_parser.got_a_float == 1) /* "f..." */
8130 suffix = SHORT_MNEM_SUFFIX;
8131 else
8132 suffix = LONG_MNEM_SUFFIX;
8133 }
9306ca4a 8134
a724f0f4
JB		 8135 else if (prev_token.code == T_FWORD)
8136 {
8137 if (current_templates->start->name[0] == 'l'
8138 && current_templates->start->name[2] == 's'
8139 && current_templates->start->name[3] == 0)
8140 suffix = LONG_MNEM_SUFFIX;
8141 else if (!intel_parser.got_a_float)
8142 {
8143 if (flag_code == CODE_16BIT)
8144 add_prefix (DATA_PREFIX_OPCODE);
8145 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8146 }
8147 else
8148 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8149 }
64a0c779 8150
a724f0f4
JB		 8151 else if (prev_token.code == T_QWORD)
8152 {
8153 if (intel_parser.got_a_float == 1) /* "f..." */
8154 suffix = LONG_MNEM_SUFFIX;
8155 else
8156 suffix = QWORD_MNEM_SUFFIX;
8157 }
64a0c779 8158
a724f0f4
JB		 8159 else if (prev_token.code == T_TBYTE)
8160 {
8161 if (intel_parser.got_a_float == 1)
8162 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8163 else
8164 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8165 }
9306ca4a 8166
a724f0f4 8167 else if (prev_token.code == T_XMMWORD)
9306ca4a 8168 {
a724f0f4
JB		 8169 /* XXX ignored for now, but accepted since gcc uses it */
8170 suffix = 0;
9306ca4a 8171 }
64a0c779 8172
f16b83df 8173 else
a724f0f4
JB		 8174 {
8175 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
8176 return 0;
8177 }
8178
435acd52
JB		 8179 /* Operands for jump/call using 'ptr' notation denote absolute
8180 addresses. */
40fb9820
L		 8181 if (current_templates->start->opcode_modifier.jump
8182 || current_templates->start->opcode_modifier.jumpdword)
8183 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 8184
a724f0f4
JB		 8185 if (current_templates->start->base_opcode == 0x8d /* lea */)
8186 ;
8187 else if (!i.suffix)
8188 i.suffix = suffix;
8189 else if (i.suffix != suffix)
8190 {
8191 as_bad (_("Conflicting operand modifiers"));
8192 return 0;
8193 }
64a0c779 8194
9306ca4a
JB		 8195 }
8196
a724f0f4
JB		 8197 /* e09' : e10 e09' */
8198 else if (cur_token.code == ':')
9306ca4a 8199 {
a724f0f4
JB		 8200 if (prev_token.code != T_REG)
8201 {
8202 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8203 segment/group identifier (which we don't have), using comma
8204 as the operand separator there is even less consistent, since
8205 there all branches only have a single operand. */
8206 if (this_operand != 0
8207 || intel_parser.in_offset
8208 || intel_parser.in_bracket
40fb9820
L		 8209 || (!current_templates->start->opcode_modifier.jump
8210 && !current_templates->start->opcode_modifier.jumpdword
8211 && !current_templates->start->opcode_modifier.jumpintersegment
8212 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
a724f0f4
JB		 8213 return intel_match_token (T_NIL);
8214 /* Remember the start of the 2nd operand and terminate 1st
8215 operand here.
8216 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8217 another expression), but it gets at least the simplest case
8218 (a plain number or symbol on the left side) right. */
8219 intel_parser.next_operand = intel_parser.op_string;
8220 *--intel_parser.op_string = '\0';
8221 return intel_match_token (':');
8222 }
9306ca4a 8223 }
64a0c779 8224
a724f0f4 8225 /* e09' Empty */
64a0c779 8226 else
a724f0f4 8227 break;
64a0c779 8228
a724f0f4
JB		 8229 intel_match_token (cur_token.code);
8230
8231 }
8232
8233 if (in_offset)
8234 {
8235 --intel_parser.in_offset;
8236 if (nregs < 0)
8237 nregs = ~nregs;
8238 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 8239 {
a724f0f4 8240 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 8241 return 0;
8242 }
a724f0f4
JB		 8243 intel_parser.op_modifier |= 1 << T_OFFSET;
8244 }
9306ca4a 8245
a724f0f4
JB		 8246 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8247 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
8248 return 1;
8249}
64a0c779 8250
a724f0f4 8251static int
e3bb37b5 8252intel_bracket_expr (void)
a724f0f4
JB		 8253{
8254 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
8255 const char *start = intel_parser.op_string;
8256 int len;
8257
8258 if (i.op[this_operand].regs)
8259 return intel_match_token (T_NIL);
8260
8261 intel_match_token ('[');
8262
8263 /* Mark as a memory operand only if it's not already known to be an
8264 offset expression. If it's an offset expression, we need to keep
8265 the brace in. */
8266 if (!intel_parser.in_offset)
8267 {
8268 ++intel_parser.in_bracket;
435acd52
JB		 8269
8270 /* Operands for jump/call inside brackets denote absolute addresses. */
40fb9820
L		 8271 if (current_templates->start->opcode_modifier.jump
8272 || current_templates->start->opcode_modifier.jumpdword)
8273 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 8274
a724f0f4
JB		 8275 /* Unfortunately gas always diverged from MASM in a respect that can't
8276 be easily fixed without risking to break code sequences likely to be
8277 encountered (the testsuite even check for this): MASM doesn't consider
8278 an expression inside brackets unconditionally as a memory reference.
8279 When that is e.g. a constant, an offset expression, or the sum of the
8280 two, this is still taken as a constant load. gas, however, always
8281 treated these as memory references. As a compromise, we'll try to make
8282 offset expressions inside brackets work the MASM way (since that's
8283 less likely to be found in real world code), but make constants alone
8284 continue to work the traditional gas way. In either case, issue a
8285 warning. */
8286 intel_parser.op_modifier &= ~was_offset;
64a0c779 8287 }
a724f0f4 8288 else
64e74474 8289 strcat (intel_parser.disp, "[");
a724f0f4
JB		 8290
8291 /* Add a '+' to the displacement string if necessary. */
8292 if (*intel_parser.disp != '\0'
8293 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
8294 strcat (intel_parser.disp, "+");
64a0c779 8295
a724f0f4
JB		 8296 if (intel_expr ()
8297 && (len = intel_parser.op_string - start - 1,
8298 intel_match_token (']')))
64a0c779 8299 {
a724f0f4
JB		 8300 /* Preserve brackets when the operand is an offset expression. */
8301 if (intel_parser.in_offset)
8302 strcat (intel_parser.disp, "]");
8303 else
8304 {
8305 --intel_parser.in_bracket;
8306 if (i.base_reg || i.index_reg)
8307 intel_parser.is_mem = 1;
8308 if (!intel_parser.is_mem)
8309 {
8310 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8311 /* Defer the warning until all of the operand was parsed. */
8312 intel_parser.is_mem = -1;
8313 else if (!quiet_warnings)
4eed87de
AM		 8314 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8315 len, start, len, start);
a724f0f4
JB		 8316 }
8317 }
8318 intel_parser.op_modifier |= was_offset;
64a0c779 8319
a724f0f4 8320 return 1;
64a0c779 8321 }
a724f0f4 8322 return 0;
64a0c779
DN		 8323}
8324
8325/* e10 e11 e10'
8326
8327 e10' [ expr ] e10'
b77a7acd 8328 | Empty */
64a0c779 8329static int
e3bb37b5 8330intel_e10 (void)
64a0c779 8331{
a724f0f4
JB		 8332 if (!intel_e11 ())
8333 return 0;
64a0c779 8334
a724f0f4 8335 while (cur_token.code == '[')
64a0c779 8336 {
a724f0f4 8337 if (!intel_bracket_expr ())
21d6c4af 8338 return 0;
64a0c779
DN		 8339 }
8340
a724f0f4 8341 return 1;
64a0c779
DN		 8342}
8343
64a0c779 8344/* e11 ( expr )
b77a7acd 8345 | [ expr ]
64a0c779
DN		 8346 | BYTE
8347 | WORD
8348 | DWORD
9306ca4a 8349 | FWORD
64a0c779 8350 | QWORD
9306ca4a
JB		 8351 | TBYTE
8352 | OWORD
8353 | XMMWORD
4a1805b1 8354 | $
64a0c779
DN		 8355 | .
8356 | register
8357 | id
8358 | constant */
8359static int
e3bb37b5 8360intel_e11 (void)
64a0c779 8361{
a724f0f4 8362 switch (cur_token.code)
64a0c779 8363 {
a724f0f4
JB		 8364 /* e11 ( expr ) */
8365 case '(':
64a0c779
DN		 8366 intel_match_token ('(');
8367 strcat (intel_parser.disp, "(");
8368
8369 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 8370 {
8371 strcat (intel_parser.disp, ")");
8372 return 1;
8373 }
a724f0f4 8374 return 0;
4a1805b1 8375
a724f0f4
JB		 8376 /* e11 [ expr ] */
8377 case '[':
a724f0f4 8378 return intel_bracket_expr ();
64a0c779 8379
a724f0f4
JB		 8380 /* e11 $
8381 | . */
8382 case '.':
64a0c779
DN		 8383 strcat (intel_parser.disp, cur_token.str);
8384 intel_match_token (cur_token.code);
21d6c4af
DN		 8385
8386 /* Mark as a memory operand only if it's not already known to be an
8387 offset expression. */
a724f0f4 8388 if (!intel_parser.in_offset)
21d6c4af 8389 intel_parser.is_mem = 1;
64a0c779
DN		 8390
8391 return 1;
64a0c779 8392
a724f0f4
JB		 8393 /* e11 register */
8394 case T_REG:
8395 {
8396 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 8397
a724f0f4 8398 intel_match_token (T_REG);
64a0c779 8399
a724f0f4
JB		 8400 /* Check for segment change. */
8401 if (cur_token.code == ':')
8402 {
40fb9820
L		 8403 if (!reg->reg_type.bitfield.sreg2
8404 && !reg->reg_type.bitfield.sreg3)
a724f0f4 8405 {
4eed87de
AM		 8406 as_bad (_("`%s' is not a valid segment register"),
8407 reg->reg_name);
a724f0f4
JB		 8408 return 0;
8409 }
8410 else if (i.seg[i.mem_operands])
8411 as_warn (_("Extra segment override ignored"));
8412 else
8413 {
8414 if (!intel_parser.in_offset)
8415 intel_parser.is_mem = 1;
8416 switch (reg->reg_num)
8417 {
8418 case 0:
8419 i.seg[i.mem_operands] = &es;
8420 break;
8421 case 1:
8422 i.seg[i.mem_operands] = &cs;
8423 break;
8424 case 2:
8425 i.seg[i.mem_operands] = &ss;
8426 break;
8427 case 3:
8428 i.seg[i.mem_operands] = &ds;
8429 break;
8430 case 4:
8431 i.seg[i.mem_operands] = &fs;
8432 break;
8433 case 5:
8434 i.seg[i.mem_operands] = &gs;
8435 break;
8436 }
8437 }
8438 }
64a0c779 8439
a724f0f4
JB		 8440 /* Not a segment register. Check for register scaling. */
8441 else if (cur_token.code == '*')
8442 {
8443 if (!intel_parser.in_bracket)
8444 {
8445 as_bad (_("Register scaling only allowed in memory operands"));
8446 return 0;
8447 }
64a0c779 8448
40fb9820 8449 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
a724f0f4
JB		 8450 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
8451 else if (i.index_reg)
8452 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 8453
a724f0f4
JB		 8454 /* What follows must be a valid scale. */
8455 intel_match_token ('*');
8456 i.index_reg = reg;
40fb9820 8457 i.types[this_operand].bitfield.baseindex = 1;
64a0c779 8458
a724f0f4
JB		 8459 /* Set the scale after setting the register (otherwise,
8460 i386_scale will complain) */
8461 if (cur_token.code == '+' || cur_token.code == '-')
8462 {
8463 char *str, sign = cur_token.code;
8464 intel_match_token (cur_token.code);
8465 if (cur_token.code != T_CONST)
8466 {
8467 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8468 cur_token.str);
8469 return 0;
8470 }
8471 str = (char *) xmalloc (strlen (cur_token.str) + 2);
8472 strcpy (str + 1, cur_token.str);
8473 *str = sign;
8474 if (!i386_scale (str))
8475 return 0;
8476 free (str);
8477 }
8478 else if (!i386_scale (cur_token.str))
64a0c779 8479 return 0;
a724f0f4
JB		 8480 intel_match_token (cur_token.code);
8481 }
64a0c779 8482
a724f0f4
JB		 8483 /* No scaling. If this is a memory operand, the register is either a
8484 base register (first occurrence) or an index register (second
8485 occurrence). */
7b0441f6 8486 else if (intel_parser.in_bracket)
a724f0f4 8487 {
64a0c779 8488
a724f0f4
JB		 8489 if (!i.base_reg)
8490 i.base_reg = reg;
8491 else if (!i.index_reg)
8492 i.index_reg = reg;
8493 else
8494 {
8495 as_bad (_("Too many register references in memory operand"));
8496 return 0;
8497 }
64a0c779 8498
40fb9820 8499 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4 8500 }
4a1805b1 8501
4d1bb795
JB		 8502 /* It's neither base nor index. */
8503 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4 8504 {
40fb9820
L		 8505 i386_operand_type temp = reg->reg_type;
8506 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8507 i.types[this_operand] = operand_type_or (i.types[this_operand],
8508 temp);
a724f0f4
JB		 8509 i.op[this_operand].regs = reg;
8510 i.reg_operands++;
8511 }
8512 else
8513 {
8514 as_bad (_("Invalid use of register"));
8515 return 0;
8516 }
64a0c779 8517
a724f0f4
JB		 8518 /* Since registers are not part of the displacement string (except
8519 when we're parsing offset operands), we may need to remove any
8520 preceding '+' from the displacement string. */
8521 if (*intel_parser.disp != '\0'
8522 && !intel_parser.in_offset)
8523 {
8524 char *s = intel_parser.disp;
8525 s += strlen (s) - 1;
8526 if (*s == '+')
8527 *s = '\0';
8528 }
4a1805b1 8529
a724f0f4
JB		 8530 return 1;
8531 }
8532
8533 /* e11 BYTE
8534 | WORD
8535 | DWORD
8536 | FWORD
8537 | QWORD
8538 | TBYTE
8539 | OWORD
8540 | XMMWORD */
8541 case T_BYTE:
8542 case T_WORD:
8543 case T_DWORD:
8544 case T_FWORD:
8545 case T_QWORD:
8546 case T_TBYTE:
8547 case T_XMMWORD:
8548 intel_match_token (cur_token.code);
64a0c779 8549
a724f0f4
JB		 8550 if (cur_token.code == T_PTR)
8551 return 1;
8552
8553 /* It must have been an identifier. */
8554 intel_putback_token ();
8555 cur_token.code = T_ID;
8556 /* FALLTHRU */
8557
8558 /* e11 id
8559 | constant */
8560 case T_ID:
8561 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 8562 {
8563 symbolS *symbolP;
8564
a724f0f4
JB		 8565 /* The identifier represents a memory reference only if it's not
8566 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 8567 symbolP = symbol_find(cur_token.str);
8568 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8569 intel_parser.is_mem = 1;
8570 }
a724f0f4 8571 /* FALLTHRU */
64a0c779 8572
a724f0f4
JB		 8573 case T_CONST:
8574 case '-':
8575 case '+':
8576 {
8577 char *save_str, sign = 0;
64a0c779 8578
a724f0f4
JB		 8579 /* Allow constants that start with `+' or `-'. */
8580 if (cur_token.code == '-' || cur_token.code == '+')
8581 {
8582 sign = cur_token.code;
8583 intel_match_token (cur_token.code);
8584 if (cur_token.code != T_CONST)
8585 {
8586 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8587 cur_token.str);
8588 return 0;
8589 }
8590 }
64a0c779 8591
a724f0f4
JB		 8592 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8593 strcpy (save_str + !!sign, cur_token.str);
8594 if (sign)
8595 *save_str = sign;
64a0c779 8596
a724f0f4
JB		 8597 /* Get the next token to check for register scaling. */
8598 intel_match_token (cur_token.code);
64a0c779 8599
4eed87de
AM		 8600 /* Check if this constant is a scaling factor for an
8601 index register. */
a724f0f4
JB		 8602 if (cur_token.code == '*')
8603 {
8604 if (intel_match_token ('*') && cur_token.code == T_REG)
8605 {
8606 const reg_entry *reg = cur_token.reg;
8607
8608 if (!intel_parser.in_bracket)
8609 {
4eed87de
AM		 8610 as_bad (_("Register scaling only allowed "
8611 "in memory operands"));
a724f0f4
JB		 8612 return 0;
8613 }
8614
4eed87de
AM		 8615 /* Disallow things like [1*si].
8616 sp and esp are invalid as index. */
40fb9820 8617 if (reg->reg_type.bitfield.reg16)
4eed87de 8618 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 8619 else if (i.index_reg)
4eed87de 8620 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 8621
8622 /* The constant is followed by `* reg', so it must be
8623 a valid scale. */
8624 i.index_reg = reg;
40fb9820 8625 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4
JB		 8626
8627 /* Set the scale after setting the register (otherwise,
8628 i386_scale will complain) */
8629 if (!i386_scale (save_str))
64a0c779 8630 return 0;
a724f0f4
JB		 8631 intel_match_token (T_REG);
8632
8633 /* Since registers are not part of the displacement
8634 string, we may need to remove any preceding '+' from
8635 the displacement string. */
8636 if (*intel_parser.disp != '\0')
8637 {
8638 char *s = intel_parser.disp;
8639 s += strlen (s) - 1;
8640 if (*s == '+')
8641 *s = '\0';
8642 }
8643
8644 free (save_str);
8645
8646 return 1;
8647 }
64a0c779 8648
a724f0f4
JB		 8649 /* The constant was not used for register scaling. Since we have
8650 already consumed the token following `*' we now need to put it
8651 back in the stream. */
64a0c779 8652 intel_putback_token ();
a724f0f4 8653 }
64a0c779 8654
a724f0f4
JB		 8655 /* Add the constant to the displacement string. */
8656 strcat (intel_parser.disp, save_str);
8657 free (save_str);
64a0c779 8658
a724f0f4
JB		 8659 return 1;
8660 }
64a0c779
DN		 8661 }
8662
64a0c779
DN		 8663 as_bad (_("Unrecognized token '%s'"), cur_token.str);
8664 return 0;
8665}
8666
64a0c779
DN		 8667/* Match the given token against cur_token. If they match, read the next
8668 token from the operand string. */
8669static int
e3bb37b5 8670intel_match_token (int code)
64a0c779
DN		 8671{
8672 if (cur_token.code == code)
8673 {
8674 intel_get_token ();
8675 return 1;
8676 }
8677 else
8678 {
0477af35 8679 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 8680 return 0;
8681 }
8682}
8683
64a0c779
DN		 8684/* Read a new token from intel_parser.op_string and store it in cur_token. */
8685static void
e3bb37b5 8686intel_get_token (void)
64a0c779
DN		 8687{
8688 char *end_op;
8689 const reg_entry *reg;
8690 struct intel_token new_token;
8691
8692 new_token.code = T_NIL;
8693 new_token.reg = NULL;
8694 new_token.str = NULL;
8695
4a1805b1 8696 /* Free the memory allocated to the previous token and move
64a0c779
DN		 8697 cur_token to prev_token. */
8698 if (prev_token.str)
8699 free (prev_token.str);
8700
8701 prev_token = cur_token;
8702
8703 /* Skip whitespace. */
8704 while (is_space_char (*intel_parser.op_string))
8705 intel_parser.op_string++;
8706
8707 /* Return an empty token if we find nothing else on the line. */
8708 if (*intel_parser.op_string == '\0')
8709 {
8710 cur_token = new_token;
8711 return;
8712 }
8713
8714 /* The new token cannot be larger than the remainder of the operand
8715 string. */
a724f0f4 8716 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 8717 new_token.str[0] = '\0';
8718
8719 if (strchr ("0123456789", *intel_parser.op_string))
8720 {
8721 char *p = new_token.str;
8722 char *q = intel_parser.op_string;
8723 new_token.code = T_CONST;
8724
8725 /* Allow any kind of identifier char to encompass floating point and
8726 hexadecimal numbers. */
8727 while (is_identifier_char (*q))
8728 *p++ = *q++;
8729 *p = '\0';
8730
8731 /* Recognize special symbol names [0-9][bf]. */
8732 if (strlen (intel_parser.op_string) == 2
4a1805b1 8733 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 8734 || intel_parser.op_string[1] == 'f'))
8735 new_token.code = T_ID;
8736 }
8737
4d1bb795 8738 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 8739 {
4d1bb795
JB		 8740 size_t len = end_op - intel_parser.op_string;
8741
64a0c779
DN		 8742 new_token.code = T_REG;
8743 new_token.reg = reg;
8744
4d1bb795
JB		 8745 memcpy (new_token.str, intel_parser.op_string, len);
8746 new_token.str[len] = '\0';
64a0c779
DN		 8747 }
8748
8749 else if (is_identifier_char (*intel_parser.op_string))
8750 {
8751 char *p = new_token.str;
8752 char *q = intel_parser.op_string;
8753
8754 /* A '.' or '$' followed by an identifier char is an identifier.
8755 Otherwise, it's operator '.' followed by an expression. */
8756 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
8757 {
9306ca4a
JB		 8758 new_token.code = '.';
8759 new_token.str[0] = '.';
64a0c779
DN		 8760 new_token.str[1] = '\0';
8761 }
8762 else
8763 {
8764 while (is_identifier_char (*q) || *q == '@')
8765 *p++ = *q++;
8766 *p = '\0';
8767
9306ca4a
JB		 8768 if (strcasecmp (new_token.str, "NOT") == 0)
8769 new_token.code = '~';
8770
8771 else if (strcasecmp (new_token.str, "MOD") == 0)
8772 new_token.code = '%';
8773
8774 else if (strcasecmp (new_token.str, "AND") == 0)
8775 new_token.code = '&';
8776
8777 else if (strcasecmp (new_token.str, "OR") == 0)
8778 new_token.code = '|';
8779
8780 else if (strcasecmp (new_token.str, "XOR") == 0)
8781 new_token.code = '^';
8782
8783 else if (strcasecmp (new_token.str, "SHL") == 0)
8784 new_token.code = T_SHL;
8785
8786 else if (strcasecmp (new_token.str, "SHR") == 0)
8787 new_token.code = T_SHR;
8788
8789 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 8790 new_token.code = T_BYTE;
8791
8792 else if (strcasecmp (new_token.str, "WORD") == 0)
8793 new_token.code = T_WORD;
8794
8795 else if (strcasecmp (new_token.str, "DWORD") == 0)
8796 new_token.code = T_DWORD;
8797
9306ca4a
JB		 8798 else if (strcasecmp (new_token.str, "FWORD") == 0)
8799 new_token.code = T_FWORD;
8800
64a0c779
DN		 8801 else if (strcasecmp (new_token.str, "QWORD") == 0)
8802 new_token.code = T_QWORD;
8803
9306ca4a
JB		 8804 else if (strcasecmp (new_token.str, "TBYTE") == 0
8805 /* XXX remove (gcc still uses it) */
8806 || strcasecmp (new_token.str, "XWORD") == 0)
8807 new_token.code = T_TBYTE;
8808
8809 else if (strcasecmp (new_token.str, "XMMWORD") == 0
8810 || strcasecmp (new_token.str, "OWORD") == 0)
8811 new_token.code = T_XMMWORD;
64a0c779
DN		 8812
8813 else if (strcasecmp (new_token.str, "PTR") == 0)
8814 new_token.code = T_PTR;
8815
8816 else if (strcasecmp (new_token.str, "SHORT") == 0)
8817 new_token.code = T_SHORT;
8818
8819 else if (strcasecmp (new_token.str, "OFFSET") == 0)
8820 {
8821 new_token.code = T_OFFSET;
8822
8823 /* ??? This is not mentioned in the MASM grammar but gcc
8824 makes use of it with -mintel-syntax. OFFSET may be
8825 followed by FLAT: */
8826 if (strncasecmp (q, " FLAT:", 6) == 0)
8827 strcat (new_token.str, " FLAT:");
8828 }
8829
8830 /* ??? This is not mentioned in the MASM grammar. */
8831 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 8832 {
8833 new_token.code = T_OFFSET;
8834 if (*q == ':')
8835 strcat (new_token.str, ":");
8836 else
8837 as_bad (_("`:' expected"));
8838 }
64a0c779
DN		 8839
8840 else
8841 new_token.code = T_ID;
8842 }
8843 }
8844
9306ca4a
JB		 8845 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
8846 {
8847 new_token.code = *intel_parser.op_string;
8848 new_token.str[0] = *intel_parser.op_string;
8849 new_token.str[1] = '\0';
8850 }
8851
8852 else if (strchr ("<>", *intel_parser.op_string)
8853 && *intel_parser.op_string == *(intel_parser.op_string + 1))
8854 {
8855 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
8856 new_token.str[0] = *intel_parser.op_string;
8857 new_token.str[1] = *intel_parser.op_string;
8858 new_token.str[2] = '\0';
8859 }
8860
64a0c779 8861 else
0477af35 8862 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 8863
8864 intel_parser.op_string += strlen (new_token.str);
8865 cur_token = new_token;
8866}
8867
64a0c779
DN		 8868/* Put cur_token back into the token stream and make cur_token point to
8869 prev_token. */
8870static void
e3bb37b5 8871intel_putback_token (void)
64a0c779 8872{
a724f0f4
JB		 8873 if (cur_token.code != T_NIL)
8874 {
8875 intel_parser.op_string -= strlen (cur_token.str);
8876 free (cur_token.str);
8877 }
64a0c779 8878 cur_token = prev_token;
4a1805b1 8879
64a0c779
DN		 8880 /* Forget prev_token. */
8881 prev_token.code = T_NIL;
8882 prev_token.reg = NULL;
8883 prev_token.str = NULL;
8884}
54cfded0 8885
a4447b93 8886int
1df69f4f 8887tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 8888{
8889 unsigned int regnum;
8890 unsigned int regnames_count;
089dfecd 8891 static const char *const regnames_32[] =
54cfded0 8892 {
a4447b93
RH		 8893 "eax", "ecx", "edx", "ebx",
8894 "esp", "ebp", "esi", "edi",
089dfecd
JB		 8895 "eip", "eflags", NULL,
8896 "st0", "st1", "st2", "st3",
8897 "st4", "st5", "st6", "st7",
8898 NULL, NULL,
8899 "xmm0", "xmm1", "xmm2", "xmm3",
8900 "xmm4", "xmm5", "xmm6", "xmm7",
8901 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 8902 "mm4", "mm5", "mm6", "mm7",
8903 "fcw", "fsw", "mxcsr",
8904 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8905 "tr", "ldtr"
54cfded0 8906 };
089dfecd 8907 static const char *const regnames_64[] =
54cfded0 8908 {
089dfecd
JB		 8909 "rax", "rdx", "rcx", "rbx",
8910 "rsi", "rdi", "rbp", "rsp",
8911 "r8", "r9", "r10", "r11",
54cfded0 8912 "r12", "r13", "r14", "r15",
089dfecd
JB		 8913 "rip",
8914 "xmm0", "xmm1", "xmm2", "xmm3",
8915 "xmm4", "xmm5", "xmm6", "xmm7",
8916 "xmm8", "xmm9", "xmm10", "xmm11",
8917 "xmm12", "xmm13", "xmm14", "xmm15",
8918 "st0", "st1", "st2", "st3",
8919 "st4", "st5", "st6", "st7",
8920 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 8921 "mm4", "mm5", "mm6", "mm7",
8922 "rflags",
8923 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8924 "fs.base", "gs.base", NULL, NULL,
8925 "tr", "ldtr",
8926 "mxcsr", "fcw", "fsw"
54cfded0 8927 };
089dfecd 8928 const char *const *regnames;
54cfded0
AM		 8929
8930 if (flag_code == CODE_64BIT)
8931 {
8932 regnames = regnames_64;
0cea6190 8933 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 8934 }
8935 else
8936 {
8937 regnames = regnames_32;
0cea6190 8938 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 8939 }
8940
8941 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 8942 if (regnames[regnum] != NULL
8943 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 8944 return regnum;
8945
54cfded0
AM		 8946 return -1;
8947}
8948
8949void
8950tc_x86_frame_initial_instructions (void)
8951{
a4447b93
RH		 8952 static unsigned int sp_regno;
8953
8954 if (!sp_regno)
8955 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
8956 ? "rsp" : "esp");
8957
8958 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
8959 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8960}
d2b2c203
DJ		 8961
8962int
8963i386_elf_section_type (const char *str, size_t len)
8964{
8965 if (flag_code == CODE_64BIT
8966 && len == sizeof ("unwind") - 1
8967 && strncmp (str, "unwind", 6) == 0)
8968 return SHT_X86_64_UNWIND;
8969
8970 return -1;
8971}
bb41ade5
AM		 8972
8973#ifdef TE_PE
8974void
8975tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8976{
8977 expressionS expr;
8978
8979 expr.X_op = O_secrel;
8980 expr.X_add_symbol = symbol;
8981 expr.X_add_number = 0;
8982 emit_expr (&expr, size);
8983}
8984#endif
3b22753a
L		 8985
8986#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8987/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8988
8989int
8990x86_64_section_letter (int letter, char **ptr_msg)
8991{
8992 if (flag_code == CODE_64BIT)
8993 {
8994 if (letter == 'l')
8995 return SHF_X86_64_LARGE;
8996
8997 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 8998 }
3b22753a 8999 else
64e74474 9000 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 9001 return -1;
9002}
9003
9004int
9005x86_64_section_word (char *str, size_t len)
9006{
8620418b 9007 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 9008 return SHF_X86_64_LARGE;
9009
9010 return -1;
9011}
9012
9013static void
9014handle_large_common (int small ATTRIBUTE_UNUSED)
9015{
9016 if (flag_code != CODE_64BIT)
9017 {
9018 s_comm_internal (0, elf_common_parse);
9019 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9020 }
9021 else
9022 {
9023 static segT lbss_section;
9024 asection *saved_com_section_ptr = elf_com_section_ptr;
9025 asection *saved_bss_section = bss_section;
9026
9027 if (lbss_section == NULL)
9028 {
9029 flagword applicable;
9030 segT seg = now_seg;
9031 subsegT subseg = now_subseg;
9032
9033 /* The .lbss section is for local .largecomm symbols. */
9034 lbss_section = subseg_new (".lbss", 0);
9035 applicable = bfd_applicable_section_flags (stdoutput);
9036 bfd_set_section_flags (stdoutput, lbss_section,
9037 applicable & SEC_ALLOC);
9038 seg_info (lbss_section)->bss = 1;
9039
9040 subseg_set (seg, subseg);
9041 }
9042
9043 elf_com_section_ptr = &_bfd_elf_large_com_section;
9044 bss_section = lbss_section;
9045
9046 s_comm_internal (0, elf_common_parse);
9047
9048 elf_com_section_ptr = saved_com_section_ptr;
9049 bss_section = saved_bss_section;
9050 }
9051}
9052#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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