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x86: Check invalid XMM register in AVX512 gathers
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
2571583a 2 Copyright (C) 1989-2017 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d 68#define LOCK_PREFIX 5
4e9ac44a
L		 69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 136}
137arch_entry;
138
293f5f65
L		 139/* Used to turn off indicated flags. */
140typedef struct
141{
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
145}
146noarch_entry;
147
78f12dd3 148static void update_code_flag (int, int);
e3bb37b5
L		 149static void set_code_flag (int);
150static void set_16bit_gcc_code_flag (int);
151static void set_intel_syntax (int);
1efbbeb4 152static void set_intel_mnemonic (int);
db51cc60 153static void set_allow_index_reg (int);
7bab8ab5 154static void set_check (int);
e3bb37b5 155static void set_cpu_arch (int);
6482c264 156#ifdef TE_PE
e3bb37b5 157static void pe_directive_secrel (int);
6482c264 158#endif
e3bb37b5
L		 159static void signed_cons (int);
160static char *output_invalid (int c);
ee86248c
JB		 161static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
162 const char *);
163static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
164 const char *);
a7619375 165static int i386_att_operand (char *);
e3bb37b5 166static int i386_intel_operand (char *, int);
ee86248c
JB		 167static int i386_intel_simplify (expressionS *);
168static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 169static const reg_entry *parse_register (char *, char **);
170static char *parse_insn (char *, char *);
171static char *parse_operands (char *, const char *);
172static void swap_operands (void);
4d456e3d 173static void swap_2_operands (int, int);
e3bb37b5
L		 174static void optimize_imm (void);
175static void optimize_disp (void);
83b16ac6 176static const insn_template *match_template (char);
e3bb37b5
L		 177static int check_string (void);
178static int process_suffix (void);
179static int check_byte_reg (void);
180static int check_long_reg (void);
181static int check_qword_reg (void);
182static int check_word_reg (void);
183static int finalize_imm (void);
184static int process_operands (void);
185static const seg_entry *build_modrm_byte (void);
186static void output_insn (void);
187static void output_imm (fragS *, offsetT);
188static void output_disp (fragS *, offsetT);
29b0f896 189#ifndef I386COFF
e3bb37b5 190static void s_bss (int);
252b5132 191#endif
17d4e2a2
L		 192#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193static void handle_large_common (int small ATTRIBUTE_UNUSED);
194#endif
252b5132 195
a847613f 196static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 197
43234a1e
L		 198/* This struct describes rounding control and SAE in the instruction. */
199struct RC_Operation
200{
201 enum rc_type
202 {
203 rne = 0,
204 rd,
205 ru,
206 rz,
207 saeonly
208 } type;
209 int operand;
210};
211
212static struct RC_Operation rc_op;
213
214/* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217struct Mask_Operation
218{
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
222 int operand;
223};
224
225static struct Mask_Operation mask_op;
226
227/* The struct describes broadcasting, applied to OPERAND. FACTOR is
228 broadcast factor. */
229struct Broadcast_Operation
230{
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 int type;
233
234 /* Index of broadcasted operand. */
235 int operand;
236};
237
238static struct Broadcast_Operation broadcast_op;
239
c0f3af97
L		 240/* VEX prefix. */
241typedef struct
242{
43234a1e
L		 243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
c0f3af97
L		 245 unsigned int length;
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
248} vex_prefix;
249
252b5132 250/* 'md_assemble ()' gathers together information and puts it into a
47926f60 251 i386_insn. */
252b5132 252
520dc8e8
AM		 253union i386_op
254 {
255 expressionS *disps;
256 expressionS *imms;
257 const reg_entry *regs;
258 };
259
a65babc9
L		 260enum i386_error
261 {
86e026a4 262 operand_size_mismatch,
a65babc9
L		 263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
267 bad_imm4,
268 old_gcc_only,
269 unsupported_with_intel_mnemonic,
270 unsupported_syntax,
6c30d220
L		 271 unsupported,
272 invalid_vsib_address,
7bab8ab5 273 invalid_vector_register_set,
43234a1e
L		 274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
277 broadcast_needed,
278 unsupported_masking,
279 mask_not_on_destination,
280 no_default_mask,
281 unsupported_rc_sae,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
284 try_vector_disp8
a65babc9
L		 285 };
286
252b5132
RH		 287struct _i386_insn
288 {
47926f60 289 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 290 insn_template tm;
252b5132 291
7d5e4556
L		 292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
252b5132
RH		 294 char suffix;
295
47926f60 296 /* OPERANDS gives the number of given operands. */
252b5132
RH		 297 unsigned int operands;
298
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
47926f60 301 operands. */
252b5132
RH		 302 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
303
304 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 305 use OP[i] for the corresponding operand. */
40fb9820 306 i386_operand_type types[MAX_OPERANDS];
252b5132 307
520dc8e8
AM		 308 /* Displacement expression, immediate expression, or register for each
309 operand. */
310 union i386_op op[MAX_OPERANDS];
252b5132 311
3e73aa7c
JH		 312 /* Flags for operands. */
313 unsigned int flags[MAX_OPERANDS];
314#define Operand_PCrel 1
315
252b5132 316 /* Relocation type for operand */
f86103b7 317 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 318
252b5132
RH		 319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry *base_reg;
322 const reg_entry *index_reg;
323 unsigned int log2_scale_factor;
324
325 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 326 explicit segment overrides are given. */
ce8a8b2f 327 const seg_entry *seg[2];
252b5132 328
8325cc63
JB		 329 /* Copied first memory operand string, for re-checking. */
330 char *memop1_string;
331
252b5132
RH		 332 /* PREFIX holds all the given prefix opcodes (usually null).
333 PREFIXES is the number of prefix opcodes. */
334 unsigned int prefixes;
335 unsigned char prefix[MAX_PREFIXES];
336
337 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 338 addressing modes of this insn are encoded. */
252b5132 339 modrm_byte rm;
3e73aa7c 340 rex_byte rex;
43234a1e 341 rex_byte vrex;
252b5132 342 sib_byte sib;
c0f3af97 343 vex_prefix vex;
b6169b20 344
43234a1e
L		 345 /* Masking attributes. */
346 struct Mask_Operation *mask;
347
348 /* Rounding control and SAE attributes. */
349 struct RC_Operation *rounding;
350
351 /* Broadcasting attributes. */
352 struct Broadcast_Operation *broadcast;
353
354 /* Compressed disp8*N attribute. */
355 unsigned int memshift;
356
86fa6981
L		 357 /* Prefer load or store in encoding. */
358 enum
359 {
360 dir_encoding_default = 0,
361 dir_encoding_load,
362 dir_encoding_store
363 } dir_encoding;
891edac4 364
a501d77e
L		 365 /* Prefer 8bit or 32bit displacement in encoding. */
366 enum
367 {
368 disp_encoding_default = 0,
369 disp_encoding_8bit,
370 disp_encoding_32bit
371 } disp_encoding;
f8a5c266 372
86fa6981
L		 373 /* How to encode vector instructions. */
374 enum
375 {
376 vex_encoding_default = 0,
377 vex_encoding_vex2,
378 vex_encoding_vex3,
379 vex_encoding_evex
380 } vec_encoding;
381
d5de92cf
L		 382 /* REP prefix. */
383 const char *rep_prefix;
384
165de32a
L		 385 /* HLE prefix. */
386 const char *hle_prefix;
42164a71 387
7e8b059b
L		 388 /* Have BND prefix. */
389 const char *bnd_prefix;
390
04ef582a
L		 391 /* Have NOTRACK prefix. */
392 const char *notrack_prefix;
393
891edac4 394 /* Error message. */
a65babc9 395 enum i386_error error;
252b5132
RH		 396 };
397
398typedef struct _i386_insn i386_insn;
399
43234a1e
L		 400/* Link RC type with corresponding string, that'll be looked for in
401 asm. */
402struct RC_name
403{
404 enum rc_type type;
405 const char *name;
406 unsigned int len;
407};
408
409static const struct RC_name RC_NamesTable[] =
410{
411 { rne, STRING_COMMA_LEN ("rn-sae") },
412 { rd, STRING_COMMA_LEN ("rd-sae") },
413 { ru, STRING_COMMA_LEN ("ru-sae") },
414 { rz, STRING_COMMA_LEN ("rz-sae") },
415 { saeonly, STRING_COMMA_LEN ("sae") },
416};
417
252b5132
RH		 418/* List of chars besides those in app.c:symbol_chars that can start an
419 operand. Used to prevent the scrubber eating vital white-space. */
86fa6981 420const char extra_symbol_chars[] = "*%-([{}"
252b5132 421#ifdef LEX_AT
32137342
NC		 422 "@"
423#endif
424#ifdef LEX_QM
425 "?"
252b5132 426#endif
32137342 427 ;
252b5132 428
29b0f896
AM		 429#if (defined (TE_I386AIX) \
430 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 431 && !defined (TE_GNU) \
29b0f896 432 && !defined (TE_LINUX) \
8d63c93e
RM		 433 && !defined (TE_NACL) \
434 && !defined (TE_NETWARE) \
29b0f896 435 && !defined (TE_FreeBSD) \
5b806d27 436 && !defined (TE_DragonFly) \
29b0f896 437 && !defined (TE_NetBSD)))
252b5132 438/* This array holds the chars that always start a comment. If the
b3b91714
AM		 439 pre-processor is disabled, these aren't very useful. The option
440 --divide will remove '/' from this list. */
441const char *i386_comment_chars = "#/";
442#define SVR4_COMMENT_CHARS 1
252b5132 443#define PREFIX_SEPARATOR '\\'
252b5132 444
b3b91714
AM		 445#else
446const char *i386_comment_chars = "#";
447#define PREFIX_SEPARATOR '/'
448#endif
449
252b5132
RH		 450/* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 452 .line and .file directives will appear in the pre-processed output.
453 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 454 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 455 #NO_APP at the beginning of its output.
456 Also note that comments started like this one will always work if
252b5132 457 '/' isn't otherwise defined. */
b3b91714 458const char line_comment_chars[] = "#/";
252b5132 459
63a0b638 460const char line_separator_chars[] = ";";
252b5132 461
ce8a8b2f
AM		 462/* Chars that can be used to separate mant from exp in floating point
463 nums. */
252b5132
RH		 464const char EXP_CHARS[] = "eE";
465
ce8a8b2f
AM		 466/* Chars that mean this number is a floating point constant
467 As in 0f12.456
468 or 0d1.2345e12. */
252b5132
RH		 469const char FLT_CHARS[] = "fFdDxX";
470
ce8a8b2f 471/* Tables for lexical analysis. */
252b5132
RH		 472static char mnemonic_chars[256];
473static char register_chars[256];
474static char operand_chars[256];
475static char identifier_chars[256];
476static char digit_chars[256];
477
ce8a8b2f 478/* Lexical macros. */
252b5132
RH		 479#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
480#define is_operand_char(x) (operand_chars[(unsigned char) x])
481#define is_register_char(x) (register_chars[(unsigned char) x])
482#define is_space_char(x) ((x) == ' ')
483#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
484#define is_digit_char(x) (digit_chars[(unsigned char) x])
485
0234cb7c 486/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 487static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
488
489/* md_assemble() always leaves the strings it's passed unaltered. To
490 effect this we maintain a stack of saved characters that we've smashed
491 with '\0's (indicating end of strings for various sub-fields of the
47926f60 492 assembler instruction). */
252b5132 493static char save_stack[32];
ce8a8b2f 494static char *save_stack_p;
252b5132
RH		 495#define END_STRING_AND_SAVE(s) \
496 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
497#define RESTORE_END_STRING(s) \
498 do { *(s) = *--save_stack_p; } while (0)
499
47926f60 500/* The instruction we're assembling. */
252b5132
RH		 501static i386_insn i;
502
503/* Possible templates for current insn. */
504static const templates *current_templates;
505
31b2323c
L		 506/* Per instruction expressionS buffers: max displacements & immediates. */
507static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
508static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 509
47926f60 510/* Current operand we are working on. */
ee86248c 511static int this_operand = -1;
252b5132 512
3e73aa7c
JH		 513/* We support four different modes. FLAG_CODE variable is used to distinguish
514 these. */
515
516enum flag_code {
517 CODE_32BIT,
518 CODE_16BIT,
519 CODE_64BIT };
520
521static enum flag_code flag_code;
4fa24527 522static unsigned int object_64bit;
862be3fb 523static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 524static int use_rela_relocations = 0;
525
7af8ed2d
NC		 526#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
527 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
528 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
529
351f65ca
L		 530/* The ELF ABI to use. */
531enum x86_elf_abi
532{
533 I386_ABI,
7f56bc95
L		 534 X86_64_ABI,
535 X86_64_X32_ABI
351f65ca
L		 536};
537
538static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 539#endif
351f65ca 540
167ad85b
TG		 541#if defined (TE_PE) || defined (TE_PEP)
542/* Use big object file format. */
543static int use_big_obj = 0;
544#endif
545
8dcea932
L		 546#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547/* 1 if generating code for a shared library. */
548static int shared = 0;
549#endif
550
47926f60
KH		 551/* 1 for intel syntax,
552 0 if att syntax. */
553static int intel_syntax = 0;
252b5132 554
e89c5eaa
L		 555/* 1 for Intel64 ISA,
556 0 if AMD64 ISA. */
557static int intel64;
558
1efbbeb4
L		 559/* 1 for intel mnemonic,
560 0 if att mnemonic. */
561static int intel_mnemonic = !SYSV386_COMPAT;
562
5209009a 563/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 564static int old_gcc = OLDGCC_COMPAT;
565
a60de03c
JB		 566/* 1 if pseudo registers are permitted. */
567static int allow_pseudo_reg = 0;
568
47926f60
KH		 569/* 1 if register prefix % not required. */
570static int allow_naked_reg = 0;
252b5132 571
33eaf5de 572/* 1 if the assembler should add BND prefix for all control-transferring
7e8b059b
L		 573 instructions supporting it, even if this prefix wasn't specified
574 explicitly. */
575static int add_bnd_prefix = 0;
576
ba104c83 577/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 578static int allow_index_reg = 0;
579
d022bddd
IT		 580/* 1 if the assembler should ignore LOCK prefix, even if it was
581 specified explicitly. */
582static int omit_lock_prefix = 0;
583
e4e00185
AS		 584/* 1 if the assembler should encode lfence, mfence, and sfence as
585 "lock addl $0, (%{re}sp)". */
586static int avoid_fence = 0;
587
0cb4071e
L		 588/* 1 if the assembler should generate relax relocations. */
589
590static int generate_relax_relocations
591 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
592
7bab8ab5 593static enum check_kind
daf50ae7 594 {
7bab8ab5
JB		 595 check_none = 0,
596 check_warning,
597 check_error
daf50ae7 598 }
7bab8ab5 599sse_check, operand_check = check_warning;
daf50ae7 600
2ca3ace5
L		 601/* Register prefix used for error message. */
602static const char *register_prefix = "%";
603
47926f60
KH		 604/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
605 leave, push, and pop instructions so that gcc has the same stack
606 frame as in 32 bit mode. */
607static char stackop_size = '\0';
eecb386c 608
12b55ccc
L		 609/* Non-zero to optimize code alignment. */
610int optimize_align_code = 1;
611
47926f60
KH		 612/* Non-zero to quieten some warnings. */
613static int quiet_warnings = 0;
a38cf1db 614
47926f60
KH		 615/* CPU name. */
616static const char *cpu_arch_name = NULL;
6305a203 617static char *cpu_sub_arch_name = NULL;
a38cf1db 618
47926f60 619/* CPU feature flags. */
40fb9820
L		 620static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
621
ccc9c027
L		 622/* If we have selected a cpu we are generating instructions for. */
623static int cpu_arch_tune_set = 0;
624
9103f4f4 625/* Cpu we are generating instructions for. */
fbf3f584 626enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 627
628/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 629static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 630
ccc9c027 631/* CPU instruction set architecture used. */
fbf3f584 632enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 633
9103f4f4 634/* CPU feature flags of instruction set architecture used. */
fbf3f584 635i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 636
fddf5b5b
AM		 637/* If set, conditional jumps are not automatically promoted to handle
638 larger than a byte offset. */
639static unsigned int no_cond_jump_promotion = 0;
640
c0f3af97
L		 641/* Encode SSE instructions with VEX prefix. */
642static unsigned int sse2avx;
643
539f890d
L		 644/* Encode scalar AVX instructions with specific vector length. */
645static enum
646 {
647 vex128 = 0,
648 vex256
649 } avxscalar;
650
43234a1e
L		 651/* Encode scalar EVEX LIG instructions with specific vector length. */
652static enum
653 {
654 evexl128 = 0,
655 evexl256,
656 evexl512
657 } evexlig;
658
659/* Encode EVEX WIG instructions with specific evex.w. */
660static enum
661 {
662 evexw0 = 0,
663 evexw1
664 } evexwig;
665
d3d3c6db
IT		 666/* Value to encode in EVEX RC bits, for SAE-only instructions. */
667static enum rc_type evexrcig = rne;
668
29b0f896 669/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 670static symbolS *GOT_symbol;
29b0f896 671
a4447b93
RH		 672/* The dwarf2 return column, adjusted for 32 or 64 bit. */
673unsigned int x86_dwarf2_return_column;
674
675/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
676int x86_cie_data_alignment;
677
252b5132 678/* Interface to relax_segment.
fddf5b5b
AM		 679 There are 3 major relax states for 386 jump insns because the
680 different types of jumps add different sizes to frags when we're
681 figuring out what sort of jump to choose to reach a given label. */
252b5132 682
47926f60 683/* Types. */
93c2a809
AM		 684#define UNCOND_JUMP 0
685#define COND_JUMP 1
686#define COND_JUMP86 2
fddf5b5b 687
47926f60 688/* Sizes. */
252b5132
RH		 689#define CODE16 1
690#define SMALL 0
29b0f896 691#define SMALL16 (SMALL | CODE16)
252b5132 692#define BIG 2
29b0f896 693#define BIG16 (BIG | CODE16)
252b5132
RH		 694
695#ifndef INLINE
696#ifdef __GNUC__
697#define INLINE __inline__
698#else
699#define INLINE
700#endif
701#endif
702
fddf5b5b
AM		 703#define ENCODE_RELAX_STATE(type, size) \
704 ((relax_substateT) (((type) << 2) | (size)))
705#define TYPE_FROM_RELAX_STATE(s) \
706 ((s) >> 2)
707#define DISP_SIZE_FROM_RELAX_STATE(s) \
708 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 709
710/* This table is used by relax_frag to promote short jumps to long
711 ones where necessary. SMALL (short) jumps may be promoted to BIG
712 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
713 don't allow a short jump in a 32 bit code segment to be promoted to
714 a 16 bit offset jump because it's slower (requires data size
715 prefix), and doesn't work, unless the destination is in the bottom
716 64k of the code segment (The top 16 bits of eip are zeroed). */
717
718const relax_typeS md_relax_table[] =
719{
24eab124
AM		 720 /* The fields are:
721 1) most positive reach of this state,
722 2) most negative reach of this state,
93c2a809 723 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 724 4) which index into the table to try if we can't fit into this one. */
252b5132 725
fddf5b5b 726 /* UNCOND_JUMP states. */
93c2a809
AM		 727 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
728 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
729 /* dword jmp adds 4 bytes to frag:
730 0 extra opcode bytes, 4 displacement bytes. */
252b5132 731 {0, 0, 4, 0},
93c2a809
AM		 732 /* word jmp adds 2 byte2 to frag:
733 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 734 {0, 0, 2, 0},
735
93c2a809
AM		 736 /* COND_JUMP states. */
737 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
738 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
739 /* dword conditionals adds 5 bytes to frag:
740 1 extra opcode byte, 4 displacement bytes. */
741 {0, 0, 5, 0},
fddf5b5b 742 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 743 1 extra opcode byte, 2 displacement bytes. */
744 {0, 0, 3, 0},
745
746 /* COND_JUMP86 states. */
747 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
748 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
749 /* dword conditionals adds 5 bytes to frag:
750 1 extra opcode byte, 4 displacement bytes. */
751 {0, 0, 5, 0},
752 /* word conditionals add 4 bytes to frag:
753 1 displacement byte and a 3 byte long branch insn. */
754 {0, 0, 4, 0}
252b5132
RH		 755};
756
9103f4f4
L		 757static const arch_entry cpu_arch[] =
758{
89507696
JB		 759 /* Do not replace the first two entries - i386_target_format()
760 relies on them being there in this order. */
8a2c8fef 761 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 762 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 763 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 764 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 765 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 766 CPU_NONE_FLAGS, 0 },
8a2c8fef 767 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 768 CPU_I186_FLAGS, 0 },
8a2c8fef 769 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 770 CPU_I286_FLAGS, 0 },
8a2c8fef 771 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 772 CPU_I386_FLAGS, 0 },
8a2c8fef 773 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 774 CPU_I486_FLAGS, 0 },
8a2c8fef 775 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 776 CPU_I586_FLAGS, 0 },
8a2c8fef 777 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 778 CPU_I686_FLAGS, 0 },
8a2c8fef 779 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 780 CPU_I586_FLAGS, 0 },
8a2c8fef 781 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 782 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 783 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 784 CPU_P2_FLAGS, 0 },
8a2c8fef 785 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 786 CPU_P3_FLAGS, 0 },
8a2c8fef 787 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 788 CPU_P4_FLAGS, 0 },
8a2c8fef 789 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 790 CPU_CORE_FLAGS, 0 },
8a2c8fef 791 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 792 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 793 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 794 CPU_CORE_FLAGS, 1 },
8a2c8fef 795 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 796 CPU_CORE_FLAGS, 0 },
8a2c8fef 797 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 798 CPU_CORE2_FLAGS, 1 },
8a2c8fef 799 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 800 CPU_CORE2_FLAGS, 0 },
8a2c8fef 801 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 802 CPU_COREI7_FLAGS, 0 },
8a2c8fef 803 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 804 CPU_L1OM_FLAGS, 0 },
7a9068fe 805 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 806 CPU_K1OM_FLAGS, 0 },
81486035 807 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 808 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 809 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 810 CPU_K6_FLAGS, 0 },
8a2c8fef 811 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 812 CPU_K6_2_FLAGS, 0 },
8a2c8fef 813 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 814 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 815 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 816 CPU_K8_FLAGS, 1 },
8a2c8fef 817 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 818 CPU_K8_FLAGS, 0 },
8a2c8fef 819 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 820 CPU_K8_FLAGS, 0 },
8a2c8fef 821 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 822 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 823 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 824 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 825 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 826 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 827 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 828 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 829 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 830 CPU_BDVER4_FLAGS, 0 },
029f3522 831 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 832 CPU_ZNVER1_FLAGS, 0 },
7b458c12 833 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 834 CPU_BTVER1_FLAGS, 0 },
7b458c12 835 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 836 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 837 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 838 CPU_8087_FLAGS, 0 },
8a2c8fef 839 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 840 CPU_287_FLAGS, 0 },
8a2c8fef 841 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 842 CPU_387_FLAGS, 0 },
1848e567
L		 843 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
844 CPU_687_FLAGS, 0 },
8a2c8fef 845 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 846 CPU_MMX_FLAGS, 0 },
8a2c8fef 847 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 848 CPU_SSE_FLAGS, 0 },
8a2c8fef 849 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 850 CPU_SSE2_FLAGS, 0 },
8a2c8fef 851 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 852 CPU_SSE3_FLAGS, 0 },
8a2c8fef 853 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 854 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 855 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 856 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 857 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 858 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 859 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 860 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 861 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 862 CPU_AVX_FLAGS, 0 },
6c30d220 863 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 864 CPU_AVX2_FLAGS, 0 },
43234a1e 865 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 866 CPU_AVX512F_FLAGS, 0 },
43234a1e 867 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 868 CPU_AVX512CD_FLAGS, 0 },
43234a1e 869 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 870 CPU_AVX512ER_FLAGS, 0 },
43234a1e 871 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 872 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 873 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 874 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 875 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 876 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 877 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 878 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 879 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 880 CPU_VMX_FLAGS, 0 },
8729a6f6 881 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 882 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 883 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 884 CPU_SMX_FLAGS, 0 },
8a2c8fef 885 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 886 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 887 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 888 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 889 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 890 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 891 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 892 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 893 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 894 CPU_AES_FLAGS, 0 },
8a2c8fef 895 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 896 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 897 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 898 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 899 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 900 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 901 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 902 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 903 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 904 CPU_F16C_FLAGS, 0 },
6c30d220 905 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 906 CPU_BMI2_FLAGS, 0 },
8a2c8fef 907 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 908 CPU_FMA_FLAGS, 0 },
8a2c8fef 909 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 910 CPU_FMA4_FLAGS, 0 },
8a2c8fef 911 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 912 CPU_XOP_FLAGS, 0 },
8a2c8fef 913 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 914 CPU_LWP_FLAGS, 0 },
8a2c8fef 915 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 916 CPU_MOVBE_FLAGS, 0 },
60aa667e 917 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 918 CPU_CX16_FLAGS, 0 },
8a2c8fef 919 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 920 CPU_EPT_FLAGS, 0 },
6c30d220 921 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 922 CPU_LZCNT_FLAGS, 0 },
42164a71 923 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 924 CPU_HLE_FLAGS, 0 },
42164a71 925 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 926 CPU_RTM_FLAGS, 0 },
6c30d220 927 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 928 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 929 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 930 CPU_CLFLUSH_FLAGS, 0 },
22109423 931 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 932 CPU_NOP_FLAGS, 0 },
8a2c8fef 933 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 934 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 935 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 936 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 937 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 938 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 939 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 940 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 941 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 942 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 943 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 944 CPU_SVME_FLAGS, 1 },
8a2c8fef 945 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 946 CPU_SVME_FLAGS, 0 },
8a2c8fef 947 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 948 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 949 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 950 CPU_ABM_FLAGS, 0 },
87973e9f 951 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 952 CPU_BMI_FLAGS, 0 },
2a2a0f38 953 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 954 CPU_TBM_FLAGS, 0 },
e2e1fcde 955 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 956 CPU_ADX_FLAGS, 0 },
e2e1fcde 957 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 958 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 959 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 960 CPU_PRFCHW_FLAGS, 0 },
5c111e37 961 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 962 CPU_SMAP_FLAGS, 0 },
7e8b059b 963 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 964 CPU_MPX_FLAGS, 0 },
a0046408 965 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 966 CPU_SHA_FLAGS, 0 },
963f3586 967 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 968 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 969 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 970 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 971 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 972 CPU_SE1_FLAGS, 0 },
c5e7287a 973 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 974 CPU_CLWB_FLAGS, 0 },
2cc1b5aa 975 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 976 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 977 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 978 CPU_AVX512VBMI_FLAGS, 0 },
920d2ddc
IT		 979 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
980 CPU_AVX512_4FMAPS_FLAGS, 0 },
47acf0bd
IT		 981 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
982 CPU_AVX512_4VNNIW_FLAGS, 0 },
620214f7
IT		 983 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
984 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
53467f57
IT		 985 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
986 CPU_AVX512_VBMI2_FLAGS, 0 },
8cfcb765
IT		 987 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
988 CPU_AVX512_VNNI_FLAGS, 0 },
ee6872be
IT		 989 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
990 CPU_AVX512_BITALG_FLAGS, 0 },
029f3522 991 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 992 CPU_CLZERO_FLAGS, 0 },
9916071f 993 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 994 CPU_MWAITX_FLAGS, 0 },
8eab4136 995 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 996 CPU_OSPKE_FLAGS, 0 },
8bc52696 997 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65 998 CPU_RDPID_FLAGS, 0 },
6b40c462
L		 999 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1000 CPU_PTWRITE_FLAGS, 0 },
603555e5
L		 1001 { STRING_COMMA_LEN (".cet"), PROCESSOR_UNKNOWN,
1002 CPU_CET_FLAGS, 0 },
48521003
IT		 1003 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1004 CPU_GFNI_FLAGS, 0 },
8dcf1fad
IT		 1005 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1006 CPU_VAES_FLAGS, 0 },
ff1982d5
IT		 1007 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1008 CPU_VPCLMULQDQ_FLAGS, 0 },
293f5f65
L		 1009};
1010
1011static const noarch_entry cpu_noarch[] =
1012{
1013 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1848e567
L		 1014 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1015 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1016 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
293f5f65
L		 1017 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1018 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1848e567
L		 1019 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1020 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1021 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1022 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1023 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1024 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
293f5f65 1025 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1848e567 1026 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
144b71e2
L		 1027 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1028 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1029 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1030 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1031 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1032 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1033 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1034 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1035 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
920d2ddc 1036 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
47acf0bd 1037 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
620214f7 1038 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
53467f57 1039 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
8cfcb765 1040 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
ee6872be 1041 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
e413e4e9
AM		 1042};
1043
704209c0 1044#ifdef I386COFF
a6c24e68
NC		 1045/* Like s_lcomm_internal in gas/read.c but the alignment string
1046 is allowed to be optional. */
1047
1048static symbolS *
1049pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1050{
1051 addressT align = 0;
1052
1053 SKIP_WHITESPACE ();
1054
7ab9ffdd 1055 if (needs_align
a6c24e68
NC		 1056 && *input_line_pointer == ',')
1057 {
1058 align = parse_align (needs_align - 1);
7ab9ffdd 1059
a6c24e68
NC		 1060 if (align == (addressT) -1)
1061 return NULL;
1062 }
1063 else
1064 {
1065 if (size >= 8)
1066 align = 3;
1067 else if (size >= 4)
1068 align = 2;
1069 else if (size >= 2)
1070 align = 1;
1071 else
1072 align = 0;
1073 }
1074
1075 bss_alloc (symbolP, size, align);
1076 return symbolP;
1077}
1078
704209c0 1079static void
a6c24e68
NC		 1080pe_lcomm (int needs_align)
1081{
1082 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1083}
704209c0 1084#endif
a6c24e68 1085
29b0f896
AM		 1086const pseudo_typeS md_pseudo_table[] =
1087{
1088#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1089 {"align", s_align_bytes, 0},
1090#else
1091 {"align", s_align_ptwo, 0},
1092#endif
1093 {"arch", set_cpu_arch, 0},
1094#ifndef I386COFF
1095 {"bss", s_bss, 0},
a6c24e68
NC		 1096#else
1097 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1098#endif
1099 {"ffloat", float_cons, 'f'},
1100 {"dfloat", float_cons, 'd'},
1101 {"tfloat", float_cons, 'x'},
1102 {"value", cons, 2},
d182319b 1103 {"slong", signed_cons, 4},
29b0f896
AM		 1104 {"noopt", s_ignore, 0},
1105 {"optim", s_ignore, 0},
1106 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1107 {"code16", set_code_flag, CODE_16BIT},
1108 {"code32", set_code_flag, CODE_32BIT},
da5f19a2 1109#ifdef BFD64
29b0f896 1110 {"code64", set_code_flag, CODE_64BIT},
da5f19a2 1111#endif
29b0f896
AM		 1112 {"intel_syntax", set_intel_syntax, 1},
1113 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1114 {"intel_mnemonic", set_intel_mnemonic, 1},
1115 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1116 {"allow_index_reg", set_allow_index_reg, 1},
1117 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1118 {"sse_check", set_check, 0},
1119 {"operand_check", set_check, 1},
3b22753a
L		 1120#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1121 {"largecomm", handle_large_common, 0},
07a53e5c 1122#else
e3bb37b5 1123 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1124 {"loc", dwarf2_directive_loc, 0},
1125 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1126#endif
6482c264
NC		 1127#ifdef TE_PE
1128 {"secrel32", pe_directive_secrel, 0},
1129#endif
29b0f896
AM		 1130 {0, 0, 0}
1131};
1132
1133/* For interface with expression (). */
1134extern char *input_line_pointer;
1135
1136/* Hash table for instruction mnemonic lookup. */
1137static struct hash_control *op_hash;
1138
1139/* Hash table for register lookup. */
1140static struct hash_control *reg_hash;
1141\f
252b5132 1142void
e3bb37b5 1143i386_align_code (fragS *fragP, int count)
252b5132 1144{
ce8a8b2f
AM		 1145 /* Various efficient no-op patterns for aligning code labels.
1146 Note: Don't try to assemble the instructions in the comments.
1147 0L and 0w are not legal. */
bad6e36d 1148 static const unsigned char f32_1[] =
252b5132 1149 {0x90}; /* nop */
bad6e36d 1150 static const unsigned char f32_2[] =
ccc9c027 1151 {0x66,0x90}; /* xchg %ax,%ax */
bad6e36d 1152 static const unsigned char f32_3[] =
252b5132 1153 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
bad6e36d 1154 static const unsigned char f32_4[] =
252b5132 1155 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1156 static const unsigned char f32_5[] =
252b5132
RH		 1157 {0x90, /* nop */
1158 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1159 static const unsigned char f32_6[] =
252b5132 1160 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
bad6e36d 1161 static const unsigned char f32_7[] =
252b5132 1162 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1163 static const unsigned char f32_8[] =
252b5132
RH		 1164 {0x90, /* nop */
1165 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1166 static const unsigned char f32_9[] =
252b5132
RH		 1167 {0x89,0xf6, /* movl %esi,%esi */
1168 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1169 static const unsigned char f32_10[] =
252b5132
RH		 1170 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1171 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1172 static const unsigned char f32_11[] =
252b5132
RH		 1173 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1174 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1175 static const unsigned char f32_12[] =
252b5132
RH		 1176 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1177 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
bad6e36d 1178 static const unsigned char f32_13[] =
252b5132
RH		 1179 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1180 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1181 static const unsigned char f32_14[] =
252b5132
RH		 1182 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1183 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1184 static const unsigned char f16_3[] =
c3332e24 1185 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
bad6e36d 1186 static const unsigned char f16_4[] =
252b5132 1187 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1188 static const unsigned char f16_5[] =
252b5132
RH		 1189 {0x90, /* nop */
1190 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1191 static const unsigned char f16_6[] =
252b5132
RH		 1192 {0x89,0xf6, /* mov %si,%si */
1193 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1194 static const unsigned char f16_7[] =
252b5132
RH		 1195 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1196 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1197 static const unsigned char f16_8[] =
252b5132
RH		 1198 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1199 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1200 static const unsigned char jump_31[] =
76bc74dc
L		 1201 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1202 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1203 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1204 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
bad6e36d 1205 static const unsigned char *const f32_patt[] = {
252b5132 1206 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1207 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132 1208 };
bad6e36d 1209 static const unsigned char *const f16_patt[] = {
76bc74dc 1210 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1211 };
ccc9c027 1212 /* nopl (%[re]ax) */
bad6e36d 1213 static const unsigned char alt_3[] =
ccc9c027
L		 1214 {0x0f,0x1f,0x00};
1215 /* nopl 0(%[re]ax) */
bad6e36d 1216 static const unsigned char alt_4[] =
ccc9c027
L		 1217 {0x0f,0x1f,0x40,0x00};
1218 /* nopl 0(%[re]ax,%[re]ax,1) */
bad6e36d 1219 static const unsigned char alt_5[] =
ccc9c027
L		 1220 {0x0f,0x1f,0x44,0x00,0x00};
1221 /* nopw 0(%[re]ax,%[re]ax,1) */
bad6e36d 1222 static const unsigned char alt_6[] =
ccc9c027
L		 1223 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1224 /* nopl 0L(%[re]ax) */
bad6e36d 1225 static const unsigned char alt_7[] =
ccc9c027
L		 1226 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1227 /* nopl 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1228 static const unsigned char alt_8[] =
ccc9c027
L		 1229 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1230 /* nopw 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1231 static const unsigned char alt_9[] =
ccc9c027
L		 1232 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1233 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
bad6e36d 1234 static const unsigned char alt_10[] =
ccc9c027 1235 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
bad6e36d 1236 static const unsigned char *const alt_patt[] = {
ccc9c027 1237 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
80b8656c 1238 alt_9, alt_10
ccc9c027 1239 };
252b5132 1240
76bc74dc
L		 1241 /* Only align for at least a positive non-zero boundary. */
1242 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1243 return;
3e73aa7c 1244
ccc9c027
L		 1245 /* We need to decide which NOP sequence to use for 32bit and
1246 64bit. When -mtune= is used:
4eed87de 1247
76bc74dc
L		 1248 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1249 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1250 2. For the rest, alt_patt will be used.
1251
1252 When -mtune= isn't used, alt_patt will be used if
22109423 1253 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1254 be used.
ccc9c027
L		 1255
1256 When -march= or .arch is used, we can't use anything beyond
1257 cpu_arch_isa_flags. */
1258
1259 if (flag_code == CODE_16BIT)
1260 {
ccc9c027 1261 if (count > 8)
33fef721 1262 {
76bc74dc
L		 1263 memcpy (fragP->fr_literal + fragP->fr_fix,
1264 jump_31, count);
1265 /* Adjust jump offset. */
1266 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1267 }
76bc74dc
L		 1268 else
1269 memcpy (fragP->fr_literal + fragP->fr_fix,
1270 f16_patt[count - 1], count);
252b5132 1271 }
33fef721 1272 else
ccc9c027 1273 {
bad6e36d 1274 const unsigned char *const *patt = NULL;
ccc9c027 1275
fbf3f584 1276 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1277 {
1278 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1279 switch (cpu_arch_tune)
1280 {
1281 case PROCESSOR_UNKNOWN:
1282 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1283 optimize with nops. */
1284 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1285 patt = alt_patt;
ccc9c027
L		 1286 else
1287 patt = f32_patt;
1288 break;
ccc9c027
L		 1289 case PROCESSOR_PENTIUM4:
1290 case PROCESSOR_NOCONA:
ef05d495 1291 case PROCESSOR_CORE:
76bc74dc 1292 case PROCESSOR_CORE2:
bd5295b2 1293 case PROCESSOR_COREI7:
3632d14b 1294 case PROCESSOR_L1OM:
7a9068fe 1295 case PROCESSOR_K1OM:
76bc74dc 1296 case PROCESSOR_GENERIC64:
ccc9c027
L		 1297 case PROCESSOR_K6:
1298 case PROCESSOR_ATHLON:
1299 case PROCESSOR_K8:
4eed87de 1300 case PROCESSOR_AMDFAM10:
8aedb9fe 1301 case PROCESSOR_BD:
029f3522 1302 case PROCESSOR_ZNVER:
7b458c12 1303 case PROCESSOR_BT:
80b8656c 1304 patt = alt_patt;
ccc9c027 1305 break;
76bc74dc 1306 case PROCESSOR_I386:
ccc9c027
L		 1307 case PROCESSOR_I486:
1308 case PROCESSOR_PENTIUM:
2dde1948 1309 case PROCESSOR_PENTIUMPRO:
81486035 1310 case PROCESSOR_IAMCU:
ccc9c027
L		 1311 case PROCESSOR_GENERIC32:
1312 patt = f32_patt;
1313 break;
4eed87de 1314 }
ccc9c027
L		 1315 }
1316 else
1317 {
fbf3f584 1318 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1319 {
1320 case PROCESSOR_UNKNOWN:
e6a14101 1321 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1322 PROCESSOR_UNKNOWN. */
1323 abort ();
1324 break;
1325
76bc74dc 1326 case PROCESSOR_I386:
ccc9c027
L		 1327 case PROCESSOR_I486:
1328 case PROCESSOR_PENTIUM:
81486035 1329 case PROCESSOR_IAMCU:
ccc9c027
L		 1330 case PROCESSOR_K6:
1331 case PROCESSOR_ATHLON:
1332 case PROCESSOR_K8:
4eed87de 1333 case PROCESSOR_AMDFAM10:
8aedb9fe 1334 case PROCESSOR_BD:
029f3522 1335 case PROCESSOR_ZNVER:
7b458c12 1336 case PROCESSOR_BT:
ccc9c027
L		 1337 case PROCESSOR_GENERIC32:
1338 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1339 with nops. */
1340 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1341 patt = alt_patt;
ccc9c027
L		 1342 else
1343 patt = f32_patt;
1344 break;
76bc74dc
L		 1345 case PROCESSOR_PENTIUMPRO:
1346 case PROCESSOR_PENTIUM4:
1347 case PROCESSOR_NOCONA:
1348 case PROCESSOR_CORE:
ef05d495 1349 case PROCESSOR_CORE2:
bd5295b2 1350 case PROCESSOR_COREI7:
3632d14b 1351 case PROCESSOR_L1OM:
7a9068fe 1352 case PROCESSOR_K1OM:
22109423 1353 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1354 patt = alt_patt;
ccc9c027
L		 1355 else
1356 patt = f32_patt;
1357 break;
1358 case PROCESSOR_GENERIC64:
80b8656c 1359 patt = alt_patt;
ccc9c027 1360 break;
4eed87de 1361 }
ccc9c027
L		 1362 }
1363
76bc74dc
L		 1364 if (patt == f32_patt)
1365 {
1366 /* If the padding is less than 15 bytes, we use the normal
1367 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1368 its offset. */
1369 int limit;
76ba9986 1370
711eedef
L		 1371 /* For 64bit, the limit is 3 bytes. */
1372 if (flag_code == CODE_64BIT
1373 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1374 limit = 3;
1375 else
1376 limit = 15;
1377 if (count < limit)
76bc74dc
L		 1378 memcpy (fragP->fr_literal + fragP->fr_fix,
1379 patt[count - 1], count);
1380 else
1381 {
1382 memcpy (fragP->fr_literal + fragP->fr_fix,
1383 jump_31, count);
1384 /* Adjust jump offset. */
1385 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1386 }
1387 }
1388 else
1389 {
80b8656c
L		 1390 /* Maximum length of an instruction is 10 byte. If the
1391 padding is greater than 10 bytes and we don't use jump,
76bc74dc
L		 1392 we have to break it into smaller pieces. */
1393 int padding = count;
80b8656c 1394 while (padding > 10)
76bc74dc 1395 {
80b8656c 1396 padding -= 10;
76bc74dc 1397 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
80b8656c 1398 patt [9], 10);
76bc74dc
L		 1399 }
1400
1401 if (padding)
1402 memcpy (fragP->fr_literal + fragP->fr_fix,
1403 patt [padding - 1], padding);
1404 }
ccc9c027 1405 }
33fef721 1406 fragP->fr_var = count;
252b5132
RH		 1407}
1408
c6fb90c8 1409static INLINE int
0dfbf9d7 1410operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1411{
0dfbf9d7 1412 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1413 {
1414 case 3:
0dfbf9d7 1415 if (x->array[2])
c6fb90c8 1416 return 0;
1a0670f3 1417 /* Fall through. */
c6fb90c8 1418 case 2:
0dfbf9d7 1419 if (x->array[1])
c6fb90c8 1420 return 0;
1a0670f3 1421 /* Fall through. */
c6fb90c8 1422 case 1:
0dfbf9d7 1423 return !x->array[0];
c6fb90c8
L		 1424 default:
1425 abort ();
1426 }
40fb9820
L		 1427}
1428
c6fb90c8 1429static INLINE void
0dfbf9d7 1430operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1431{
0dfbf9d7 1432 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1433 {
1434 case 3:
0dfbf9d7 1435 x->array[2] = v;
1a0670f3 1436 /* Fall through. */
c6fb90c8 1437 case 2:
0dfbf9d7 1438 x->array[1] = v;
1a0670f3 1439 /* Fall through. */
c6fb90c8 1440 case 1:
0dfbf9d7 1441 x->array[0] = v;
1a0670f3 1442 /* Fall through. */
c6fb90c8
L		 1443 break;
1444 default:
1445 abort ();
1446 }
1447}
40fb9820 1448
c6fb90c8 1449static INLINE int
0dfbf9d7
L		 1450operand_type_equal (const union i386_operand_type *x,
1451 const union i386_operand_type *y)
c6fb90c8 1452{
0dfbf9d7 1453 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1454 {
1455 case 3:
0dfbf9d7 1456 if (x->array[2] != y->array[2])
c6fb90c8 1457 return 0;
1a0670f3 1458 /* Fall through. */
c6fb90c8 1459 case 2:
0dfbf9d7 1460 if (x->array[1] != y->array[1])
c6fb90c8 1461 return 0;
1a0670f3 1462 /* Fall through. */
c6fb90c8 1463 case 1:
0dfbf9d7 1464 return x->array[0] == y->array[0];
c6fb90c8
L		 1465 break;
1466 default:
1467 abort ();
1468 }
1469}
40fb9820 1470
0dfbf9d7
L		 1471static INLINE int
1472cpu_flags_all_zero (const union i386_cpu_flags *x)
1473{
1474 switch (ARRAY_SIZE(x->array))
1475 {
53467f57
IT		 1476 case 4:
1477 if (x->array[3])
1478 return 0;
1479 /* Fall through. */
0dfbf9d7
L		 1480 case 3:
1481 if (x->array[2])
1482 return 0;
1a0670f3 1483 /* Fall through. */
0dfbf9d7
L		 1484 case 2:
1485 if (x->array[1])
1486 return 0;
1a0670f3 1487 /* Fall through. */
0dfbf9d7
L		 1488 case 1:
1489 return !x->array[0];
1490 default:
1491 abort ();
1492 }
1493}
1494
0dfbf9d7
L		 1495static INLINE int
1496cpu_flags_equal (const union i386_cpu_flags *x,
1497 const union i386_cpu_flags *y)
1498{
1499 switch (ARRAY_SIZE(x->array))
1500 {
53467f57
IT		 1501 case 4:
1502 if (x->array[3] != y->array[3])
1503 return 0;
1504 /* Fall through. */
0dfbf9d7
L		 1505 case 3:
1506 if (x->array[2] != y->array[2])
1507 return 0;
1a0670f3 1508 /* Fall through. */
0dfbf9d7
L		 1509 case 2:
1510 if (x->array[1] != y->array[1])
1511 return 0;
1a0670f3 1512 /* Fall through. */
0dfbf9d7
L		 1513 case 1:
1514 return x->array[0] == y->array[0];
1515 break;
1516 default:
1517 abort ();
1518 }
1519}
c6fb90c8
L		 1520
1521static INLINE int
1522cpu_flags_check_cpu64 (i386_cpu_flags f)
1523{
1524 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1525 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1526}
1527
c6fb90c8
L		 1528static INLINE i386_cpu_flags
1529cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1530{
c6fb90c8
L		 1531 switch (ARRAY_SIZE (x.array))
1532 {
53467f57
IT		 1533 case 4:
1534 x.array [3] &= y.array [3];
1535 /* Fall through. */
c6fb90c8
L		 1536 case 3:
1537 x.array [2] &= y.array [2];
1a0670f3 1538 /* Fall through. */
c6fb90c8
L		 1539 case 2:
1540 x.array [1] &= y.array [1];
1a0670f3 1541 /* Fall through. */
c6fb90c8
L		 1542 case 1:
1543 x.array [0] &= y.array [0];
1544 break;
1545 default:
1546 abort ();
1547 }
1548 return x;
1549}
40fb9820 1550
c6fb90c8
L		 1551static INLINE i386_cpu_flags
1552cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1553{
c6fb90c8 1554 switch (ARRAY_SIZE (x.array))
40fb9820 1555 {
53467f57
IT		 1556 case 4:
1557 x.array [3] |= y.array [3];
1558 /* Fall through. */
c6fb90c8
L		 1559 case 3:
1560 x.array [2] |= y.array [2];
1a0670f3 1561 /* Fall through. */
c6fb90c8
L		 1562 case 2:
1563 x.array [1] |= y.array [1];
1a0670f3 1564 /* Fall through. */
c6fb90c8
L		 1565 case 1:
1566 x.array [0] |= y.array [0];
40fb9820
L		 1567 break;
1568 default:
1569 abort ();
1570 }
40fb9820
L		 1571 return x;
1572}
1573
309d3373
JB		 1574static INLINE i386_cpu_flags
1575cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1576{
1577 switch (ARRAY_SIZE (x.array))
1578 {
53467f57
IT		 1579 case 4:
1580 x.array [3] &= ~y.array [3];
1581 /* Fall through. */
309d3373
JB		 1582 case 3:
1583 x.array [2] &= ~y.array [2];
1a0670f3 1584 /* Fall through. */
309d3373
JB		 1585 case 2:
1586 x.array [1] &= ~y.array [1];
1a0670f3 1587 /* Fall through. */
309d3373
JB		 1588 case 1:
1589 x.array [0] &= ~y.array [0];
1590 break;
1591 default:
1592 abort ();
1593 }
1594 return x;
1595}
1596
c0f3af97
L		 1597#define CPU_FLAGS_ARCH_MATCH 0x1
1598#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1599#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1600#define CPU_FLAGS_PCLMUL_MATCH 0x8
1601#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1602
a5ff0eb2 1603#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1604 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1605 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1606#define CPU_FLAGS_PERFECT_MATCH \
1607 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1608
1609/* Return CPU flags match bits. */
3629bb00 1610
40fb9820 1611static int
d3ce72d0 1612cpu_flags_match (const insn_template *t)
40fb9820 1613{
c0f3af97
L		 1614 i386_cpu_flags x = t->cpu_flags;
1615 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1616
1617 x.bitfield.cpu64 = 0;
1618 x.bitfield.cpuno64 = 0;
1619
0dfbf9d7 1620 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1621 {
1622 /* This instruction is available on all archs. */
1623 match |= CPU_FLAGS_32BIT_MATCH;
1624 }
3629bb00
L		 1625 else
1626 {
c0f3af97 1627 /* This instruction is available only on some archs. */
3629bb00
L		 1628 i386_cpu_flags cpu = cpu_arch_flags;
1629
3629bb00 1630 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1631 if (!cpu_flags_all_zero (&cpu))
1632 {
a5ff0eb2
L		 1633 if (x.bitfield.cpuavx)
1634 {
ce2f5b3c 1635 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1636 if (cpu.bitfield.cpuavx)
1637 {
1638 /* Check SSE2AVX. */
1639 if (!t->opcode_modifier.sse2avx|| sse2avx)
1640 {
1641 match |= (CPU_FLAGS_ARCH_MATCH
1642 | CPU_FLAGS_AVX_MATCH);
1643 /* Check AES. */
1644 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1645 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1646 /* Check PCLMUL. */
1647 if (!x.bitfield.cpupclmul
1648 || cpu.bitfield.cpupclmul)
1649 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1650 }
1651 }
1652 else
1653 match |= CPU_FLAGS_ARCH_MATCH;
1654 }
73b090a9
L		 1655 else if (x.bitfield.cpuavx512vl)
1656 {
1657 /* Match AVX512VL. */
1658 if (cpu.bitfield.cpuavx512vl)
1659 {
1660 /* Need another match. */
1661 cpu.bitfield.cpuavx512vl = 0;
1662 if (!cpu_flags_all_zero (&cpu))
1663 match |= CPU_FLAGS_32BIT_MATCH;
1664 else
1665 match |= CPU_FLAGS_ARCH_MATCH;
1666 }
1667 else
1668 match |= CPU_FLAGS_ARCH_MATCH;
1669 }
a5ff0eb2 1670 else
c0f3af97
L		 1671 match |= CPU_FLAGS_32BIT_MATCH;
1672 }
3629bb00 1673 }
c0f3af97 1674 return match;
40fb9820
L		 1675}
1676
c6fb90c8
L		 1677static INLINE i386_operand_type
1678operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1679{
c6fb90c8
L		 1680 switch (ARRAY_SIZE (x.array))
1681 {
1682 case 3:
1683 x.array [2] &= y.array [2];
1a0670f3 1684 /* Fall through. */
c6fb90c8
L		 1685 case 2:
1686 x.array [1] &= y.array [1];
1a0670f3 1687 /* Fall through. */
c6fb90c8
L		 1688 case 1:
1689 x.array [0] &= y.array [0];
1690 break;
1691 default:
1692 abort ();
1693 }
1694 return x;
40fb9820
L		 1695}
1696
c6fb90c8
L		 1697static INLINE i386_operand_type
1698operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1699{
c6fb90c8 1700 switch (ARRAY_SIZE (x.array))
40fb9820 1701 {
c6fb90c8
L		 1702 case 3:
1703 x.array [2] |= y.array [2];
1a0670f3 1704 /* Fall through. */
c6fb90c8
L		 1705 case 2:
1706 x.array [1] |= y.array [1];
1a0670f3 1707 /* Fall through. */
c6fb90c8
L		 1708 case 1:
1709 x.array [0] |= y.array [0];
40fb9820
L		 1710 break;
1711 default:
1712 abort ();
1713 }
c6fb90c8
L		 1714 return x;
1715}
40fb9820 1716
c6fb90c8
L		 1717static INLINE i386_operand_type
1718operand_type_xor (i386_operand_type x, i386_operand_type y)
1719{
1720 switch (ARRAY_SIZE (x.array))
1721 {
1722 case 3:
1723 x.array [2] ^= y.array [2];
1a0670f3 1724 /* Fall through. */
c6fb90c8
L		 1725 case 2:
1726 x.array [1] ^= y.array [1];
1a0670f3 1727 /* Fall through. */
c6fb90c8
L		 1728 case 1:
1729 x.array [0] ^= y.array [0];
1730 break;
1731 default:
1732 abort ();
1733 }
40fb9820
L		 1734 return x;
1735}
1736
1737static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1738static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1739static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1740static const i386_operand_type inoutportreg
1741 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1742static const i386_operand_type reg16_inoutportreg
1743 = OPERAND_TYPE_REG16_INOUTPORTREG;
1744static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1745static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1746static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1747static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1748static const i386_operand_type anydisp
1749 = OPERAND_TYPE_ANYDISP;
40fb9820 1750static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1751static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1752static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1753static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1754static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1755static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1756static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1757static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1758static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1759static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1760static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1761static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1762static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1763static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1764
1765enum operand_type
1766{
1767 reg,
40fb9820
L		 1768 imm,
1769 disp,
1770 anymem
1771};
1772
c6fb90c8 1773static INLINE int
40fb9820
L		 1774operand_type_check (i386_operand_type t, enum operand_type c)
1775{
1776 switch (c)
1777 {
1778 case reg:
1779 return (t.bitfield.reg8
1780 || t.bitfield.reg16
1781 || t.bitfield.reg32
1782 || t.bitfield.reg64);
1783
40fb9820
L		 1784 case imm:
1785 return (t.bitfield.imm8
1786 || t.bitfield.imm8s
1787 || t.bitfield.imm16
1788 || t.bitfield.imm32
1789 || t.bitfield.imm32s
1790 || t.bitfield.imm64);
1791
1792 case disp:
1793 return (t.bitfield.disp8
1794 || t.bitfield.disp16
1795 || t.bitfield.disp32
1796 || t.bitfield.disp32s
1797 || t.bitfield.disp64);
1798
1799 case anymem:
1800 return (t.bitfield.disp8
1801 || t.bitfield.disp16
1802 || t.bitfield.disp32
1803 || t.bitfield.disp32s
1804 || t.bitfield.disp64
1805 || t.bitfield.baseindex);
1806
1807 default:
1808 abort ();
1809 }
2cfe26b6
AM		 1810
1811 return 0;
40fb9820
L		 1812}
1813
5c07affc
L		 1814/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1815 operand J for instruction template T. */
1816
1817static INLINE int
d3ce72d0 1818match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1819{
1820 return !((i.types[j].bitfield.byte
1821 && !t->operand_types[j].bitfield.byte)
1822 || (i.types[j].bitfield.word
1823 && !t->operand_types[j].bitfield.word)
1824 || (i.types[j].bitfield.dword
1825 && !t->operand_types[j].bitfield.dword)
1826 || (i.types[j].bitfield.qword
1827 && !t->operand_types[j].bitfield.qword));
1828}
1829
1830/* Return 1 if there is no conflict in any size on operand J for
1831 instruction template T. */
1832
1833static INLINE int
d3ce72d0 1834match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1835{
1836 return (match_reg_size (t, j)
1837 && !((i.types[j].bitfield.unspecified
af508cb9 1838 && !i.broadcast
5c07affc
L		 1839 && !t->operand_types[j].bitfield.unspecified)
1840 || (i.types[j].bitfield.fword
1841 && !t->operand_types[j].bitfield.fword)
1842 || (i.types[j].bitfield.tbyte
1843 && !t->operand_types[j].bitfield.tbyte)
1844 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1845 && !t->operand_types[j].bitfield.xmmword)
1846 || (i.types[j].bitfield.ymmword
43234a1e
L		 1847 && !t->operand_types[j].bitfield.ymmword)
1848 || (i.types[j].bitfield.zmmword
1849 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1850}
1851
1852/* Return 1 if there is no size conflict on any operands for
1853 instruction template T. */
1854
1855static INLINE int
d3ce72d0 1856operand_size_match (const insn_template *t)
5c07affc
L		 1857{
1858 unsigned int j;
1859 int match = 1;
1860
1861 /* Don't check jump instructions. */
1862 if (t->opcode_modifier.jump
1863 || t->opcode_modifier.jumpbyte
1864 || t->opcode_modifier.jumpdword
1865 || t->opcode_modifier.jumpintersegment)
1866 return match;
1867
1868 /* Check memory and accumulator operand size. */
1869 for (j = 0; j < i.operands; j++)
1870 {
1871 if (t->operand_types[j].bitfield.anysize)
1872 continue;
1873
1874 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1875 {
1876 match = 0;
1877 break;
1878 }
1879
1880 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1881 {
1882 match = 0;
1883 break;
1884 }
1885 }
1886
891edac4 1887 if (match)
5c07affc 1888 return match;
891edac4
L		 1889 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1890 {
1891mismatch:
86e026a4 1892 i.error = operand_size_mismatch;
891edac4
L		 1893 return 0;
1894 }
5c07affc
L		 1895
1896 /* Check reverse. */
9c2799c2 1897 gas_assert (i.operands == 2);
5c07affc
L		 1898
1899 match = 1;
1900 for (j = 0; j < 2; j++)
1901 {
1902 if (t->operand_types[j].bitfield.acc
1903 && !match_reg_size (t, j ? 0 : 1))
891edac4 1904 goto mismatch;
5c07affc
L		 1905
1906 if (i.types[j].bitfield.mem
1907 && !match_mem_size (t, j ? 0 : 1))
891edac4 1908 goto mismatch;
5c07affc
L		 1909 }
1910
1911 return match;
1912}
1913
c6fb90c8 1914static INLINE int
40fb9820
L		 1915operand_type_match (i386_operand_type overlap,
1916 i386_operand_type given)
1917{
1918 i386_operand_type temp = overlap;
1919
1920 temp.bitfield.jumpabsolute = 0;
7d5e4556 1921 temp.bitfield.unspecified = 0;
5c07affc
L		 1922 temp.bitfield.byte = 0;
1923 temp.bitfield.word = 0;
1924 temp.bitfield.dword = 0;
1925 temp.bitfield.fword = 0;
1926 temp.bitfield.qword = 0;
1927 temp.bitfield.tbyte = 0;
1928 temp.bitfield.xmmword = 0;
c0f3af97 1929 temp.bitfield.ymmword = 0;
43234a1e 1930 temp.bitfield.zmmword = 0;
0dfbf9d7 1931 if (operand_type_all_zero (&temp))
891edac4 1932 goto mismatch;
40fb9820 1933
891edac4
L		 1934 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1935 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1936 return 1;
1937
1938mismatch:
a65babc9 1939 i.error = operand_type_mismatch;
891edac4 1940 return 0;
40fb9820
L		 1941}
1942
7d5e4556 1943/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1944 unless the expected operand type register overlap is null.
1945 Note that Acc in a template matches every size of reg. */
1946
c6fb90c8 1947static INLINE int
40fb9820
L		 1948operand_type_register_match (i386_operand_type m0,
1949 i386_operand_type g0,
1950 i386_operand_type t0,
1951 i386_operand_type m1,
1952 i386_operand_type g1,
1953 i386_operand_type t1)
1954{
1955 if (!operand_type_check (g0, reg))
1956 return 1;
1957
1958 if (!operand_type_check (g1, reg))
1959 return 1;
1960
1961 if (g0.bitfield.reg8 == g1.bitfield.reg8
1962 && g0.bitfield.reg16 == g1.bitfield.reg16
1963 && g0.bitfield.reg32 == g1.bitfield.reg32
1964 && g0.bitfield.reg64 == g1.bitfield.reg64)
1965 return 1;
1966
1967 if (m0.bitfield.acc)
1968 {
1969 t0.bitfield.reg8 = 1;
1970 t0.bitfield.reg16 = 1;
1971 t0.bitfield.reg32 = 1;
1972 t0.bitfield.reg64 = 1;
1973 }
1974
1975 if (m1.bitfield.acc)
1976 {
1977 t1.bitfield.reg8 = 1;
1978 t1.bitfield.reg16 = 1;
1979 t1.bitfield.reg32 = 1;
1980 t1.bitfield.reg64 = 1;
1981 }
1982
891edac4
L		 1983 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1984 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1985 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1986 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1987 return 1;
1988
a65babc9 1989 i.error = register_type_mismatch;
891edac4
L		 1990
1991 return 0;
40fb9820
L		 1992}
1993
4c692bc7
JB		 1994static INLINE unsigned int
1995register_number (const reg_entry *r)
1996{
1997 unsigned int nr = r->reg_num;
1998
1999 if (r->reg_flags & RegRex)
2000 nr += 8;
2001
200cbe0f
L		 2002 if (r->reg_flags & RegVRex)
2003 nr += 16;
2004
4c692bc7
JB		 2005 return nr;
2006}
2007
252b5132 2008static INLINE unsigned int
40fb9820 2009mode_from_disp_size (i386_operand_type t)
252b5132 2010{
43234a1e 2011 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 2012 return 1;
2013 else if (t.bitfield.disp16
2014 || t.bitfield.disp32
2015 || t.bitfield.disp32s)
2016 return 2;
2017 else
2018 return 0;
252b5132
RH		 2019}
2020
2021static INLINE int
65879393 2022fits_in_signed_byte (addressT num)
252b5132 2023{
65879393 2024 return num + 0x80 <= 0xff;
47926f60 2025}
252b5132
RH		 2026
2027static INLINE int
65879393 2028fits_in_unsigned_byte (addressT num)
252b5132 2029{
65879393 2030 return num <= 0xff;
47926f60 2031}
252b5132
RH		 2032
2033static INLINE int
65879393 2034fits_in_unsigned_word (addressT num)
252b5132 2035{
65879393 2036 return num <= 0xffff;
47926f60 2037}
252b5132
RH		 2038
2039static INLINE int
65879393 2040fits_in_signed_word (addressT num)
252b5132 2041{
65879393 2042 return num + 0x8000 <= 0xffff;
47926f60 2043}
2a962e6d 2044
3e73aa7c 2045static INLINE int
65879393 2046fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2047{
2048#ifndef BFD64
2049 return 1;
2050#else
65879393 2051 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 2052#endif
2053} /* fits_in_signed_long() */
2a962e6d 2054
3e73aa7c 2055static INLINE int
65879393 2056fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2057{
2058#ifndef BFD64
2059 return 1;
2060#else
65879393 2061 return num <= 0xffffffff;
3e73aa7c
JH		 2062#endif
2063} /* fits_in_unsigned_long() */
252b5132 2064
43234a1e
L		 2065static INLINE int
2066fits_in_vec_disp8 (offsetT num)
2067{
2068 int shift = i.memshift;
2069 unsigned int mask;
2070
2071 if (shift == -1)
2072 abort ();
2073
2074 mask = (1 << shift) - 1;
2075
2076 /* Return 0 if NUM isn't properly aligned. */
2077 if ((num & mask))
2078 return 0;
2079
2080 /* Check if NUM will fit in 8bit after shift. */
2081 return fits_in_signed_byte (num >> shift);
2082}
2083
a683cc34
SP		 2084static INLINE int
2085fits_in_imm4 (offsetT num)
2086{
2087 return (num & 0xf) == num;
2088}
2089
40fb9820 2090static i386_operand_type
e3bb37b5 2091smallest_imm_type (offsetT num)
252b5132 2092{
40fb9820 2093 i386_operand_type t;
7ab9ffdd 2094
0dfbf9d7 2095 operand_type_set (&t, 0);
40fb9820
L		 2096 t.bitfield.imm64 = 1;
2097
2098 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2099 {
2100 /* This code is disabled on the 486 because all the Imm1 forms
2101 in the opcode table are slower on the i486. They're the
2102 versions with the implicitly specified single-position
2103 displacement, which has another syntax if you really want to
2104 use that form. */
40fb9820
L		 2105 t.bitfield.imm1 = 1;
2106 t.bitfield.imm8 = 1;
2107 t.bitfield.imm8s = 1;
2108 t.bitfield.imm16 = 1;
2109 t.bitfield.imm32 = 1;
2110 t.bitfield.imm32s = 1;
2111 }
2112 else if (fits_in_signed_byte (num))
2113 {
2114 t.bitfield.imm8 = 1;
2115 t.bitfield.imm8s = 1;
2116 t.bitfield.imm16 = 1;
2117 t.bitfield.imm32 = 1;
2118 t.bitfield.imm32s = 1;
2119 }
2120 else if (fits_in_unsigned_byte (num))
2121 {
2122 t.bitfield.imm8 = 1;
2123 t.bitfield.imm16 = 1;
2124 t.bitfield.imm32 = 1;
2125 t.bitfield.imm32s = 1;
2126 }
2127 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2128 {
2129 t.bitfield.imm16 = 1;
2130 t.bitfield.imm32 = 1;
2131 t.bitfield.imm32s = 1;
2132 }
2133 else if (fits_in_signed_long (num))
2134 {
2135 t.bitfield.imm32 = 1;
2136 t.bitfield.imm32s = 1;
2137 }
2138 else if (fits_in_unsigned_long (num))
2139 t.bitfield.imm32 = 1;
2140
2141 return t;
47926f60 2142}
252b5132 2143
847f7ad4 2144static offsetT
e3bb37b5 2145offset_in_range (offsetT val, int size)
847f7ad4 2146{
508866be 2147 addressT mask;
ba2adb93 2148
847f7ad4
AM		 2149 switch (size)
2150 {
508866be
L		 2151 case 1: mask = ((addressT) 1 << 8) - 1; break;
2152 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2153 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2154#ifdef BFD64
2155 case 8: mask = ((addressT) 2 << 63) - 1; break;
2156#endif
47926f60 2157 default: abort ();
847f7ad4
AM		 2158 }
2159
9de868bf
L		 2160#ifdef BFD64
2161 /* If BFD64, sign extend val for 32bit address mode. */
2162 if (flag_code != CODE_64BIT
2163 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2164 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2165 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2166#endif
ba2adb93 2167
47926f60 2168 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2169 {
2170 char buf1[40], buf2[40];
2171
2172 sprint_value (buf1, val);
2173 sprint_value (buf2, val & mask);
2174 as_warn (_("%s shortened to %s"), buf1, buf2);
2175 }
2176 return val & mask;
2177}
2178
c32fa91d
L		 2179enum PREFIX_GROUP
2180{
2181 PREFIX_EXIST = 0,
2182 PREFIX_LOCK,
2183 PREFIX_REP,
04ef582a 2184 PREFIX_DS,
c32fa91d
L		 2185 PREFIX_OTHER
2186};
2187
2188/* Returns
2189 a. PREFIX_EXIST if attempting to add a prefix where one from the
2190 same class already exists.
2191 b. PREFIX_LOCK if lock prefix is added.
2192 c. PREFIX_REP if rep/repne prefix is added.
04ef582a
L		 2193 d. PREFIX_DS if ds prefix is added.
2194 e. PREFIX_OTHER if other prefix is added.
c32fa91d
L		 2195 */
2196
2197static enum PREFIX_GROUP
e3bb37b5 2198add_prefix (unsigned int prefix)
252b5132 2199{
c32fa91d 2200 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2201 unsigned int q;
252b5132 2202
29b0f896
AM		 2203 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2204 && flag_code == CODE_64BIT)
b1905489 2205 {
161a04f6
L		 2206 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2207 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2208 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2209 ret = PREFIX_EXIST;
b1905489
JB		 2210 q = REX_PREFIX;
2211 }
3e73aa7c 2212 else
b1905489
JB		 2213 {
2214 switch (prefix)
2215 {
2216 default:
2217 abort ();
2218
b1905489 2219 case DS_PREFIX_OPCODE:
04ef582a
L		 2220 ret = PREFIX_DS;
2221 /* Fall through. */
2222 case CS_PREFIX_OPCODE:
b1905489
JB		 2223 case ES_PREFIX_OPCODE:
2224 case FS_PREFIX_OPCODE:
2225 case GS_PREFIX_OPCODE:
2226 case SS_PREFIX_OPCODE:
2227 q = SEG_PREFIX;
2228 break;
2229
2230 case REPNE_PREFIX_OPCODE:
2231 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2232 q = REP_PREFIX;
2233 ret = PREFIX_REP;
2234 break;
2235
b1905489 2236 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2237 q = LOCK_PREFIX;
2238 ret = PREFIX_LOCK;
b1905489
JB		 2239 break;
2240
2241 case FWAIT_OPCODE:
2242 q = WAIT_PREFIX;
2243 break;
2244
2245 case ADDR_PREFIX_OPCODE:
2246 q = ADDR_PREFIX;
2247 break;
2248
2249 case DATA_PREFIX_OPCODE:
2250 q = DATA_PREFIX;
2251 break;
2252 }
2253 if (i.prefix[q] != 0)
c32fa91d 2254 ret = PREFIX_EXIST;
b1905489 2255 }
252b5132 2256
b1905489 2257 if (ret)
252b5132 2258 {
b1905489
JB		 2259 if (!i.prefix[q])
2260 ++i.prefixes;
2261 i.prefix[q] |= prefix;
252b5132 2262 }
b1905489
JB		 2263 else
2264 as_bad (_("same type of prefix used twice"));
252b5132 2265
252b5132
RH		 2266 return ret;
2267}
2268
2269static void
78f12dd3 2270update_code_flag (int value, int check)
eecb386c 2271{
78f12dd3
L		 2272 PRINTF_LIKE ((*as_error));
2273
1e9cc1c2 2274 flag_code = (enum flag_code) value;
40fb9820
L		 2275 if (flag_code == CODE_64BIT)
2276 {
2277 cpu_arch_flags.bitfield.cpu64 = 1;
2278 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2279 }
2280 else
2281 {
2282 cpu_arch_flags.bitfield.cpu64 = 0;
2283 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2284 }
2285 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2286 {
78f12dd3
L		 2287 if (check)
2288 as_error = as_fatal;
2289 else
2290 as_error = as_bad;
2291 (*as_error) (_("64bit mode not supported on `%s'."),
2292 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2293 }
40fb9820 2294 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2295 {
78f12dd3
L		 2296 if (check)
2297 as_error = as_fatal;
2298 else
2299 as_error = as_bad;
2300 (*as_error) (_("32bit mode not supported on `%s'."),
2301 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2302 }
eecb386c
AM		 2303 stackop_size = '\0';
2304}
2305
78f12dd3
L		 2306static void
2307set_code_flag (int value)
2308{
2309 update_code_flag (value, 0);
2310}
2311
eecb386c 2312static void
e3bb37b5 2313set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2314{
1e9cc1c2 2315 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2316 if (flag_code != CODE_16BIT)
2317 abort ();
2318 cpu_arch_flags.bitfield.cpu64 = 0;
2319 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2320 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2321}
2322
2323static void
e3bb37b5 2324set_intel_syntax (int syntax_flag)
252b5132
RH		 2325{
2326 /* Find out if register prefixing is specified. */
2327 int ask_naked_reg = 0;
2328
2329 SKIP_WHITESPACE ();
29b0f896 2330 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2331 {
d02603dc
NC		 2332 char *string;
2333 int e = get_symbol_name (&string);
252b5132 2334
47926f60 2335 if (strcmp (string, "prefix") == 0)
252b5132 2336 ask_naked_reg = 1;
47926f60 2337 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2338 ask_naked_reg = -1;
2339 else
d0b47220 2340 as_bad (_("bad argument to syntax directive."));
d02603dc 2341 (void) restore_line_pointer (e);
252b5132
RH		 2342 }
2343 demand_empty_rest_of_line ();
c3332e24 2344
252b5132
RH		 2345 intel_syntax = syntax_flag;
2346
2347 if (ask_naked_reg == 0)
f86103b7
AM		 2348 allow_naked_reg = (intel_syntax
2349 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2350 else
2351 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2352
ee86248c 2353 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2354
e4a3b5a4 2355 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2356 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2357 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2358}
2359
1efbbeb4
L		 2360static void
2361set_intel_mnemonic (int mnemonic_flag)
2362{
e1d4d893 2363 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2364}
2365
db51cc60
L		 2366static void
2367set_allow_index_reg (int flag)
2368{
2369 allow_index_reg = flag;
2370}
2371
cb19c032 2372static void
7bab8ab5 2373set_check (int what)
cb19c032 2374{
7bab8ab5
JB		 2375 enum check_kind *kind;
2376 const char *str;
2377
2378 if (what)
2379 {
2380 kind = &operand_check;
2381 str = "operand";
2382 }
2383 else
2384 {
2385 kind = &sse_check;
2386 str = "sse";
2387 }
2388
cb19c032
L		 2389 SKIP_WHITESPACE ();
2390
2391 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2392 {
d02603dc
NC		 2393 char *string;
2394 int e = get_symbol_name (&string);
cb19c032
L		 2395
2396 if (strcmp (string, "none") == 0)
7bab8ab5 2397 *kind = check_none;
cb19c032 2398 else if (strcmp (string, "warning") == 0)
7bab8ab5 2399 *kind = check_warning;
cb19c032 2400 else if (strcmp (string, "error") == 0)
7bab8ab5 2401 *kind = check_error;
cb19c032 2402 else
7bab8ab5 2403 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2404 (void) restore_line_pointer (e);
cb19c032
L		 2405 }
2406 else
7bab8ab5 2407 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2408
2409 demand_empty_rest_of_line ();
2410}
2411
8a9036a4
L		 2412static void
2413check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2414 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2415{
2416#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2417 static const char *arch;
2418
2419 /* Intel LIOM is only supported on ELF. */
2420 if (!IS_ELF)
2421 return;
2422
2423 if (!arch)
2424 {
2425 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2426 use default_arch. */
2427 arch = cpu_arch_name;
2428 if (!arch)
2429 arch = default_arch;
2430 }
2431
81486035
L		 2432 /* If we are targeting Intel MCU, we must enable it. */
2433 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2434 || new_flag.bitfield.cpuiamcu)
2435 return;
2436
3632d14b 2437 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2438 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2439 || new_flag.bitfield.cpul1om)
8a9036a4 2440 return;
76ba9986 2441
7a9068fe
L		 2442 /* If we are targeting Intel K1OM, we must enable it. */
2443 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2444 || new_flag.bitfield.cpuk1om)
2445 return;
2446
8a9036a4
L		 2447 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2448#endif
2449}
2450
e413e4e9 2451static void
e3bb37b5 2452set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2453{
47926f60 2454 SKIP_WHITESPACE ();
e413e4e9 2455
29b0f896 2456 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2457 {
d02603dc
NC		 2458 char *string;
2459 int e = get_symbol_name (&string);
91d6fa6a 2460 unsigned int j;
40fb9820 2461 i386_cpu_flags flags;
e413e4e9 2462
91d6fa6a 2463 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2464 {
91d6fa6a 2465 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2466 {
91d6fa6a 2467 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2468
5c6af06e
JB		 2469 if (*string != '.')
2470 {
91d6fa6a 2471 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2472 cpu_sub_arch_name = NULL;
91d6fa6a 2473 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2474 if (flag_code == CODE_64BIT)
2475 {
2476 cpu_arch_flags.bitfield.cpu64 = 1;
2477 cpu_arch_flags.bitfield.cpuno64 = 0;
2478 }
2479 else
2480 {
2481 cpu_arch_flags.bitfield.cpu64 = 0;
2482 cpu_arch_flags.bitfield.cpuno64 = 1;
2483 }
91d6fa6a
NC		 2484 cpu_arch_isa = cpu_arch[j].type;
2485 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2486 if (!cpu_arch_tune_set)
2487 {
2488 cpu_arch_tune = cpu_arch_isa;
2489 cpu_arch_tune_flags = cpu_arch_isa_flags;
2490 }
5c6af06e
JB		 2491 break;
2492 }
40fb9820 2493
293f5f65
L		 2494 flags = cpu_flags_or (cpu_arch_flags,
2495 cpu_arch[j].flags);
81486035 2496
5b64d091 2497 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2498 {
6305a203
L		 2499 if (cpu_sub_arch_name)
2500 {
2501 char *name = cpu_sub_arch_name;
2502 cpu_sub_arch_name = concat (name,
91d6fa6a 2503 cpu_arch[j].name,
1bf57e9f 2504 (const char *) NULL);
6305a203
L		 2505 free (name);
2506 }
2507 else
91d6fa6a 2508 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2509 cpu_arch_flags = flags;
a586129e 2510 cpu_arch_isa_flags = flags;
5c6af06e 2511 }
d02603dc 2512 (void) restore_line_pointer (e);
5c6af06e
JB		 2513 demand_empty_rest_of_line ();
2514 return;
e413e4e9
AM		 2515 }
2516 }
293f5f65
L		 2517
2518 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2519 {
33eaf5de 2520 /* Disable an ISA extension. */
293f5f65
L		 2521 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2522 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2523 {
2524 flags = cpu_flags_and_not (cpu_arch_flags,
2525 cpu_noarch[j].flags);
2526 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2527 {
2528 if (cpu_sub_arch_name)
2529 {
2530 char *name = cpu_sub_arch_name;
2531 cpu_sub_arch_name = concat (name, string,
2532 (const char *) NULL);
2533 free (name);
2534 }
2535 else
2536 cpu_sub_arch_name = xstrdup (string);
2537 cpu_arch_flags = flags;
2538 cpu_arch_isa_flags = flags;
2539 }
2540 (void) restore_line_pointer (e);
2541 demand_empty_rest_of_line ();
2542 return;
2543 }
2544
2545 j = ARRAY_SIZE (cpu_arch);
2546 }
2547
91d6fa6a 2548 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2549 as_bad (_("no such architecture: `%s'"), string);
2550
2551 *input_line_pointer = e;
2552 }
2553 else
2554 as_bad (_("missing cpu architecture"));
2555
fddf5b5b
AM		 2556 no_cond_jump_promotion = 0;
2557 if (*input_line_pointer == ','
29b0f896 2558 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2559 {
d02603dc
NC		 2560 char *string;
2561 char e;
2562
2563 ++input_line_pointer;
2564 e = get_symbol_name (&string);
fddf5b5b
AM		 2565
2566 if (strcmp (string, "nojumps") == 0)
2567 no_cond_jump_promotion = 1;
2568 else if (strcmp (string, "jumps") == 0)
2569 ;
2570 else
2571 as_bad (_("no such architecture modifier: `%s'"), string);
2572
d02603dc 2573 (void) restore_line_pointer (e);
fddf5b5b
AM		 2574 }
2575
e413e4e9
AM		 2576 demand_empty_rest_of_line ();
2577}
2578
8a9036a4
L		 2579enum bfd_architecture
2580i386_arch (void)
2581{
3632d14b 2582 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2583 {
2584 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2585 || flag_code != CODE_64BIT)
2586 as_fatal (_("Intel L1OM is 64bit ELF only"));
2587 return bfd_arch_l1om;
2588 }
7a9068fe
L		 2589 else if (cpu_arch_isa == PROCESSOR_K1OM)
2590 {
2591 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2592 || flag_code != CODE_64BIT)
2593 as_fatal (_("Intel K1OM is 64bit ELF only"));
2594 return bfd_arch_k1om;
2595 }
81486035
L		 2596 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2597 {
2598 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2599 || flag_code == CODE_64BIT)
2600 as_fatal (_("Intel MCU is 32bit ELF only"));
2601 return bfd_arch_iamcu;
2602 }
8a9036a4
L		 2603 else
2604 return bfd_arch_i386;
2605}
2606
b9d79e03 2607unsigned long
7016a5d5 2608i386_mach (void)
b9d79e03 2609{
351f65ca 2610 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2611 {
3632d14b 2612 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2613 {
351f65ca
L		 2614 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2615 || default_arch[6] != '\0')
8a9036a4
L		 2616 as_fatal (_("Intel L1OM is 64bit ELF only"));
2617 return bfd_mach_l1om;
2618 }
7a9068fe
L		 2619 else if (cpu_arch_isa == PROCESSOR_K1OM)
2620 {
2621 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2622 || default_arch[6] != '\0')
2623 as_fatal (_("Intel K1OM is 64bit ELF only"));
2624 return bfd_mach_k1om;
2625 }
351f65ca 2626 else if (default_arch[6] == '\0')
8a9036a4 2627 return bfd_mach_x86_64;
351f65ca
L		 2628 else
2629 return bfd_mach_x64_32;
8a9036a4 2630 }
5197d474
L		 2631 else if (!strcmp (default_arch, "i386")
2632 || !strcmp (default_arch, "iamcu"))
81486035
L		 2633 {
2634 if (cpu_arch_isa == PROCESSOR_IAMCU)
2635 {
2636 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2637 as_fatal (_("Intel MCU is 32bit ELF only"));
2638 return bfd_mach_i386_iamcu;
2639 }
2640 else
2641 return bfd_mach_i386_i386;
2642 }
b9d79e03 2643 else
2b5d6a91 2644 as_fatal (_("unknown architecture"));
b9d79e03 2645}
b9d79e03 2646\f
252b5132 2647void
7016a5d5 2648md_begin (void)
252b5132
RH		 2649{
2650 const char *hash_err;
2651
86fa6981
L		 2652 /* Support pseudo prefixes like {disp32}. */
2653 lex_type ['{'] = LEX_BEGIN_NAME;
2654
47926f60 2655 /* Initialize op_hash hash table. */
252b5132
RH		 2656 op_hash = hash_new ();
2657
2658 {
d3ce72d0 2659 const insn_template *optab;
29b0f896 2660 templates *core_optab;
252b5132 2661
47926f60
KH		 2662 /* Setup for loop. */
2663 optab = i386_optab;
add39d23 2664 core_optab = XNEW (templates);
252b5132
RH		 2665 core_optab->start = optab;
2666
2667 while (1)
2668 {
2669 ++optab;
2670 if (optab->name == NULL
2671 || strcmp (optab->name, (optab - 1)->name) != 0)
2672 {
2673 /* different name --> ship out current template list;
47926f60 2674 add to hash table; & begin anew. */
252b5132
RH		 2675 core_optab->end = optab;
2676 hash_err = hash_insert (op_hash,
2677 (optab - 1)->name,
5a49b8ac 2678 (void *) core_optab);
252b5132
RH		 2679 if (hash_err)
2680 {
b37df7c4 2681 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2682 (optab - 1)->name,
2683 hash_err);
2684 }
2685 if (optab->name == NULL)
2686 break;
add39d23 2687 core_optab = XNEW (templates);
252b5132
RH		 2688 core_optab->start = optab;
2689 }
2690 }
2691 }
2692
47926f60 2693 /* Initialize reg_hash hash table. */
252b5132
RH		 2694 reg_hash = hash_new ();
2695 {
29b0f896 2696 const reg_entry *regtab;
c3fe08fa 2697 unsigned int regtab_size = i386_regtab_size;
252b5132 2698
c3fe08fa 2699 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2700 {
5a49b8ac 2701 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2702 if (hash_err)
b37df7c4 2703 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2704 regtab->reg_name,
2705 hash_err);
252b5132
RH		 2706 }
2707 }
2708
47926f60 2709 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2710 {
29b0f896
AM		 2711 int c;
2712 char *p;
252b5132
RH		 2713
2714 for (c = 0; c < 256; c++)
2715 {
3882b010 2716 if (ISDIGIT (c))
252b5132
RH		 2717 {
2718 digit_chars[c] = c;
2719 mnemonic_chars[c] = c;
2720 register_chars[c] = c;
2721 operand_chars[c] = c;
2722 }
3882b010 2723 else if (ISLOWER (c))
252b5132
RH		 2724 {
2725 mnemonic_chars[c] = c;
2726 register_chars[c] = c;
2727 operand_chars[c] = c;
2728 }
3882b010 2729 else if (ISUPPER (c))
252b5132 2730 {
3882b010 2731 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2732 register_chars[c] = mnemonic_chars[c];
2733 operand_chars[c] = c;
2734 }
43234a1e 2735 else if (c == '{' || c == '}')
86fa6981
L		 2736 {
2737 mnemonic_chars[c] = c;
2738 operand_chars[c] = c;
2739 }
252b5132 2740
3882b010 2741 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2742 identifier_chars[c] = c;
2743 else if (c >= 128)
2744 {
2745 identifier_chars[c] = c;
2746 operand_chars[c] = c;
2747 }
2748 }
2749
2750#ifdef LEX_AT
2751 identifier_chars['@'] = '@';
32137342
NC		 2752#endif
2753#ifdef LEX_QM
2754 identifier_chars['?'] = '?';
2755 operand_chars['?'] = '?';
252b5132 2756#endif
252b5132 2757 digit_chars['-'] = '-';
c0f3af97 2758 mnemonic_chars['_'] = '_';
791fe849 2759 mnemonic_chars['-'] = '-';
0003779b 2760 mnemonic_chars['.'] = '.';
252b5132
RH		 2761 identifier_chars['_'] = '_';
2762 identifier_chars['.'] = '.';
2763
2764 for (p = operand_special_chars; *p != '\0'; p++)
2765 operand_chars[(unsigned char) *p] = *p;
2766 }
2767
a4447b93
RH		 2768 if (flag_code == CODE_64BIT)
2769 {
ca19b261
KT		 2770#if defined (OBJ_COFF) && defined (TE_PE)
2771 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2772 ? 32 : 16);
2773#else
a4447b93 2774 x86_dwarf2_return_column = 16;
ca19b261 2775#endif
61ff971f 2776 x86_cie_data_alignment = -8;
a4447b93
RH		 2777 }
2778 else
2779 {
2780 x86_dwarf2_return_column = 8;
2781 x86_cie_data_alignment = -4;
2782 }
252b5132
RH		 2783}
2784
2785void
e3bb37b5 2786i386_print_statistics (FILE *file)
252b5132
RH		 2787{
2788 hash_print_statistics (file, "i386 opcode", op_hash);
2789 hash_print_statistics (file, "i386 register", reg_hash);
2790}
2791\f
252b5132
RH		 2792#ifdef DEBUG386
2793
ce8a8b2f 2794/* Debugging routines for md_assemble. */
d3ce72d0 2795static void pte (insn_template *);
40fb9820 2796static void pt (i386_operand_type);
e3bb37b5
L		 2797static void pe (expressionS *);
2798static void ps (symbolS *);
252b5132
RH		 2799
2800static void
e3bb37b5 2801pi (char *line, i386_insn *x)
252b5132 2802{
09137c09 2803 unsigned int j;
252b5132
RH		 2804
2805 fprintf (stdout, "%s: template ", line);
2806 pte (&x->tm);
09f131f2
JH		 2807 fprintf (stdout, " address: base %s index %s scale %x\n",
2808 x->base_reg ? x->base_reg->reg_name : "none",
2809 x->index_reg ? x->index_reg->reg_name : "none",
2810 x->log2_scale_factor);
2811 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2812 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2813 fprintf (stdout, " sib: base %x index %x scale %x\n",
2814 x->sib.base, x->sib.index, x->sib.scale);
2815 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2816 (x->rex & REX_W) != 0,
2817 (x->rex & REX_R) != 0,
2818 (x->rex & REX_X) != 0,
2819 (x->rex & REX_B) != 0);
09137c09 2820 for (j = 0; j < x->operands; j++)
252b5132 2821 {
09137c09
SP		 2822 fprintf (stdout, " #%d: ", j + 1);
2823 pt (x->types[j]);
252b5132 2824 fprintf (stdout, "\n");
09137c09
SP		 2825 if (x->types[j].bitfield.reg8
2826 || x->types[j].bitfield.reg16
2827 || x->types[j].bitfield.reg32
2828 || x->types[j].bitfield.reg64
2829 || x->types[j].bitfield.regmmx
2830 || x->types[j].bitfield.regxmm
2831 || x->types[j].bitfield.regymm
43234a1e 2832 || x->types[j].bitfield.regzmm
09137c09
SP		 2833 || x->types[j].bitfield.sreg2
2834 || x->types[j].bitfield.sreg3
2835 || x->types[j].bitfield.control
2836 || x->types[j].bitfield.debug
2837 || x->types[j].bitfield.test)
2838 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2839 if (operand_type_check (x->types[j], imm))
2840 pe (x->op[j].imms);
2841 if (operand_type_check (x->types[j], disp))
2842 pe (x->op[j].disps);
252b5132
RH		 2843 }
2844}
2845
2846static void
d3ce72d0 2847pte (insn_template *t)
252b5132 2848{
09137c09 2849 unsigned int j;
252b5132 2850 fprintf (stdout, " %d operands ", t->operands);
47926f60 2851 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2852 if (t->extension_opcode != None)
2853 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2854 if (t->opcode_modifier.d)
252b5132 2855 fprintf (stdout, "D");
40fb9820 2856 if (t->opcode_modifier.w)
252b5132
RH		 2857 fprintf (stdout, "W");
2858 fprintf (stdout, "\n");
09137c09 2859 for (j = 0; j < t->operands; j++)
252b5132 2860 {
09137c09
SP		 2861 fprintf (stdout, " #%d type ", j + 1);
2862 pt (t->operand_types[j]);
252b5132
RH		 2863 fprintf (stdout, "\n");
2864 }
2865}
2866
2867static void
e3bb37b5 2868pe (expressionS *e)
252b5132 2869{
24eab124 2870 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2871 fprintf (stdout, " add_number %ld (%lx)\n",
2872 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2873 if (e->X_add_symbol)
2874 {
2875 fprintf (stdout, " add_symbol ");
2876 ps (e->X_add_symbol);
2877 fprintf (stdout, "\n");
2878 }
2879 if (e->X_op_symbol)
2880 {
2881 fprintf (stdout, " op_symbol ");
2882 ps (e->X_op_symbol);
2883 fprintf (stdout, "\n");
2884 }
2885}
2886
2887static void
e3bb37b5 2888ps (symbolS *s)
252b5132
RH		 2889{
2890 fprintf (stdout, "%s type %s%s",
2891 S_GET_NAME (s),
2892 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2893 segment_name (S_GET_SEGMENT (s)));
2894}
2895
7b81dfbb 2896static struct type_name
252b5132 2897 {
40fb9820
L		 2898 i386_operand_type mask;
2899 const char *name;
252b5132 2900 }
7b81dfbb 2901const type_names[] =
252b5132 2902{
40fb9820
L		 2903 { OPERAND_TYPE_REG8, "r8" },
2904 { OPERAND_TYPE_REG16, "r16" },
2905 { OPERAND_TYPE_REG32, "r32" },
2906 { OPERAND_TYPE_REG64, "r64" },
2907 { OPERAND_TYPE_IMM8, "i8" },
2908 { OPERAND_TYPE_IMM8, "i8s" },
2909 { OPERAND_TYPE_IMM16, "i16" },
2910 { OPERAND_TYPE_IMM32, "i32" },
2911 { OPERAND_TYPE_IMM32S, "i32s" },
2912 { OPERAND_TYPE_IMM64, "i64" },
2913 { OPERAND_TYPE_IMM1, "i1" },
2914 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2915 { OPERAND_TYPE_DISP8, "d8" },
2916 { OPERAND_TYPE_DISP16, "d16" },
2917 { OPERAND_TYPE_DISP32, "d32" },
2918 { OPERAND_TYPE_DISP32S, "d32s" },
2919 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2920 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2921 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2922 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2923 { OPERAND_TYPE_CONTROL, "control reg" },
2924 { OPERAND_TYPE_TEST, "test reg" },
2925 { OPERAND_TYPE_DEBUG, "debug reg" },
2926 { OPERAND_TYPE_FLOATREG, "FReg" },
2927 { OPERAND_TYPE_FLOATACC, "FAcc" },
2928 { OPERAND_TYPE_SREG2, "SReg2" },
2929 { OPERAND_TYPE_SREG3, "SReg3" },
2930 { OPERAND_TYPE_ACC, "Acc" },
2931 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2932 { OPERAND_TYPE_REGMMX, "rMMX" },
2933 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2934 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2935 { OPERAND_TYPE_REGZMM, "rZMM" },
2936 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2937 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2938};
2939
2940static void
40fb9820 2941pt (i386_operand_type t)
252b5132 2942{
40fb9820 2943 unsigned int j;
c6fb90c8 2944 i386_operand_type a;
252b5132 2945
40fb9820 2946 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2947 {
2948 a = operand_type_and (t, type_names[j].mask);
0349dc08 2949 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2950 fprintf (stdout, "%s, ", type_names[j].name);
2951 }
252b5132
RH		 2952 fflush (stdout);
2953}
2954
2955#endif /* DEBUG386 */
2956\f
252b5132 2957static bfd_reloc_code_real_type
3956db08 2958reloc (unsigned int size,
64e74474
AM		 2959 int pcrel,
2960 int sign,
2961 bfd_reloc_code_real_type other)
252b5132 2962{
47926f60 2963 if (other != NO_RELOC)
3956db08 2964 {
91d6fa6a 2965 reloc_howto_type *rel;
3956db08
JB		 2966
2967 if (size == 8)
2968 switch (other)
2969 {
64e74474
AM		 2970 case BFD_RELOC_X86_64_GOT32:
2971 return BFD_RELOC_X86_64_GOT64;
2972 break;
553d1284
L		 2973 case BFD_RELOC_X86_64_GOTPLT64:
2974 return BFD_RELOC_X86_64_GOTPLT64;
2975 break;
64e74474
AM		 2976 case BFD_RELOC_X86_64_PLTOFF64:
2977 return BFD_RELOC_X86_64_PLTOFF64;
2978 break;
2979 case BFD_RELOC_X86_64_GOTPC32:
2980 other = BFD_RELOC_X86_64_GOTPC64;
2981 break;
2982 case BFD_RELOC_X86_64_GOTPCREL:
2983 other = BFD_RELOC_X86_64_GOTPCREL64;
2984 break;
2985 case BFD_RELOC_X86_64_TPOFF32:
2986 other = BFD_RELOC_X86_64_TPOFF64;
2987 break;
2988 case BFD_RELOC_X86_64_DTPOFF32:
2989 other = BFD_RELOC_X86_64_DTPOFF64;
2990 break;
2991 default:
2992 break;
3956db08 2993 }
e05278af 2994
8ce3d284 2995#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2996 if (other == BFD_RELOC_SIZE32)
2997 {
2998 if (size == 8)
1ab668bf 2999 other = BFD_RELOC_SIZE64;
8fd4256d 3000 if (pcrel)
1ab668bf
AM		 3001 {
3002 as_bad (_("there are no pc-relative size relocations"));
3003 return NO_RELOC;
3004 }
8fd4256d 3005 }
8ce3d284 3006#endif
8fd4256d 3007
e05278af 3008 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 3009 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 3010 sign = -1;
3011
91d6fa6a
NC		 3012 rel = bfd_reloc_type_lookup (stdoutput, other);
3013 if (!rel)
3956db08 3014 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 3015 else if (size != bfd_get_reloc_size (rel))
3956db08 3016 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 3017 bfd_get_reloc_size (rel),
3956db08 3018 size);
91d6fa6a 3019 else if (pcrel && !rel->pc_relative)
3956db08 3020 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 3021 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 3022 && !sign)
91d6fa6a 3023 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 3024 && sign > 0))
3956db08
JB		 3025 as_bad (_("relocated field and relocation type differ in signedness"));
3026 else
3027 return other;
3028 return NO_RELOC;
3029 }
252b5132
RH		 3030
3031 if (pcrel)
3032 {
3e73aa7c 3033 if (!sign)
3956db08 3034 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 3035 switch (size)
3036 {
3037 case 1: return BFD_RELOC_8_PCREL;
3038 case 2: return BFD_RELOC_16_PCREL;
d258b828 3039 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 3040 case 8: return BFD_RELOC_64_PCREL;
252b5132 3041 }
3956db08 3042 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 3043 }
3044 else
3045 {
3956db08 3046 if (sign > 0)
e5cb08ac 3047 switch (size)
3e73aa7c
JH		 3048 {
3049 case 4: return BFD_RELOC_X86_64_32S;
3050 }
3051 else
3052 switch (size)
3053 {
3054 case 1: return BFD_RELOC_8;
3055 case 2: return BFD_RELOC_16;
3056 case 4: return BFD_RELOC_32;
3057 case 8: return BFD_RELOC_64;
3058 }
3956db08
JB		 3059 as_bad (_("cannot do %s %u byte relocation"),
3060 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 3061 }
3062
0cc9e1d3 3063 return NO_RELOC;
252b5132
RH		 3064}
3065
47926f60
KH		 3066/* Here we decide which fixups can be adjusted to make them relative to
3067 the beginning of the section instead of the symbol. Basically we need
3068 to make sure that the dynamic relocations are done correctly, so in
3069 some cases we force the original symbol to be used. */
3070
252b5132 3071int
e3bb37b5 3072tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 3073{
6d249963 3074#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 3075 if (!IS_ELF)
31312f95
AM		 3076 return 1;
3077
a161fe53
AM		 3078 /* Don't adjust pc-relative references to merge sections in 64-bit
3079 mode. */
3080 if (use_rela_relocations
3081 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3082 && fixP->fx_pcrel)
252b5132 3083 return 0;
31312f95 3084
8d01d9a9
AJ		 3085 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3086 and changed later by validate_fix. */
3087 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3088 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3089 return 0;
3090
8fd4256d
L		 3091 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3092 for size relocations. */
3093 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3094 || fixP->fx_r_type == BFD_RELOC_SIZE64
3095 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 3096 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3097 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 3098 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3099 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3100 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3101 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3102 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3103 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3104 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3105 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3106 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3107 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3108 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3109 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3110 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3111 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3112 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3113 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3114 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3115 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3116 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3117 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3118 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3119 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3120 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3121 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3122 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3123 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3124 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3125 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3126 return 0;
31312f95 3127#endif
252b5132
RH		 3128 return 1;
3129}
252b5132 3130
b4cac588 3131static int
e3bb37b5 3132intel_float_operand (const char *mnemonic)
252b5132 3133{
9306ca4a
JB		 3134 /* Note that the value returned is meaningful only for opcodes with (memory)
3135 operands, hence the code here is free to improperly handle opcodes that
3136 have no operands (for better performance and smaller code). */
3137
3138 if (mnemonic[0] != 'f')
3139 return 0; /* non-math */
3140
3141 switch (mnemonic[1])
3142 {
3143 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3144 the fs segment override prefix not currently handled because no
3145 call path can make opcodes without operands get here */
3146 case 'i':
3147 return 2 /* integer op */;
3148 case 'l':
3149 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3150 return 3; /* fldcw/fldenv */
3151 break;
3152 case 'n':
3153 if (mnemonic[2] != 'o' /* fnop */)
3154 return 3; /* non-waiting control op */
3155 break;
3156 case 'r':
3157 if (mnemonic[2] == 's')
3158 return 3; /* frstor/frstpm */
3159 break;
3160 case 's':
3161 if (mnemonic[2] == 'a')
3162 return 3; /* fsave */
3163 if (mnemonic[2] == 't')
3164 {
3165 switch (mnemonic[3])
3166 {
3167 case 'c': /* fstcw */
3168 case 'd': /* fstdw */
3169 case 'e': /* fstenv */
3170 case 's': /* fsts[gw] */
3171 return 3;
3172 }
3173 }
3174 break;
3175 case 'x':
3176 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3177 return 0; /* fxsave/fxrstor are not really math ops */
3178 break;
3179 }
252b5132 3180
9306ca4a 3181 return 1;
252b5132
RH		 3182}
3183
c0f3af97
L		 3184/* Build the VEX prefix. */
3185
3186static void
d3ce72d0 3187build_vex_prefix (const insn_template *t)
c0f3af97
L		 3188{
3189 unsigned int register_specifier;
3190 unsigned int implied_prefix;
3191 unsigned int vector_length;
3192
3193 /* Check register specifier. */
3194 if (i.vex.register_specifier)
43234a1e
L		 3195 {
3196 register_specifier =
3197 ~register_number (i.vex.register_specifier) & 0xf;
3198 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3199 }
c0f3af97
L		 3200 else
3201 register_specifier = 0xf;
3202
33eaf5de 3203 /* Use 2-byte VEX prefix by swapping destination and source
fa99fab2 3204 operand. */
86fa6981
L		 3205 if (i.vec_encoding != vex_encoding_vex3
3206 && i.dir_encoding == dir_encoding_default
fa99fab2 3207 && i.operands == i.reg_operands
7f399153 3208 && i.tm.opcode_modifier.vexopcode == VEX0F
86fa6981 3209 && i.tm.opcode_modifier.load
fa99fab2
L		 3210 && i.rex == REX_B)
3211 {
3212 unsigned int xchg = i.operands - 1;
3213 union i386_op temp_op;
3214 i386_operand_type temp_type;
3215
3216 temp_type = i.types[xchg];
3217 i.types[xchg] = i.types[0];
3218 i.types[0] = temp_type;
3219 temp_op = i.op[xchg];
3220 i.op[xchg] = i.op[0];
3221 i.op[0] = temp_op;
3222
9c2799c2 3223 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3224
3225 i.rex = REX_R;
3226 xchg = i.rm.regmem;
3227 i.rm.regmem = i.rm.reg;
3228 i.rm.reg = xchg;
3229
3230 /* Use the next insn. */
3231 i.tm = t[1];
3232 }
3233
539f890d
L		 3234 if (i.tm.opcode_modifier.vex == VEXScalar)
3235 vector_length = avxscalar;
3236 else
3237 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3238
3239 switch ((i.tm.base_opcode >> 8) & 0xff)
3240 {
3241 case 0:
3242 implied_prefix = 0;
3243 break;
3244 case DATA_PREFIX_OPCODE:
3245 implied_prefix = 1;
3246 break;
3247 case REPE_PREFIX_OPCODE:
3248 implied_prefix = 2;
3249 break;
3250 case REPNE_PREFIX_OPCODE:
3251 implied_prefix = 3;
3252 break;
3253 default:
3254 abort ();
3255 }
3256
3257 /* Use 2-byte VEX prefix if possible. */
86fa6981
L		 3258 if (i.vec_encoding != vex_encoding_vex3
3259 && i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3260 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3261 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3262 {
3263 /* 2-byte VEX prefix. */
3264 unsigned int r;
3265
3266 i.vex.length = 2;
3267 i.vex.bytes[0] = 0xc5;
3268
3269 /* Check the REX.R bit. */
3270 r = (i.rex & REX_R) ? 0 : 1;
3271 i.vex.bytes[1] = (r << 7
3272 | register_specifier << 3
3273 | vector_length << 2
3274 | implied_prefix);
3275 }
3276 else
3277 {
3278 /* 3-byte VEX prefix. */
3279 unsigned int m, w;
3280
f88c9eb0 3281 i.vex.length = 3;
f88c9eb0 3282
7f399153 3283 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3284 {
7f399153
L		 3285 case VEX0F:
3286 m = 0x1;
80de6e00 3287 i.vex.bytes[0] = 0xc4;
7f399153
L		 3288 break;
3289 case VEX0F38:
3290 m = 0x2;
80de6e00 3291 i.vex.bytes[0] = 0xc4;
7f399153
L		 3292 break;
3293 case VEX0F3A:
3294 m = 0x3;
80de6e00 3295 i.vex.bytes[0] = 0xc4;
7f399153
L		 3296 break;
3297 case XOP08:
5dd85c99
SP		 3298 m = 0x8;
3299 i.vex.bytes[0] = 0x8f;
7f399153
L		 3300 break;
3301 case XOP09:
f88c9eb0
SP		 3302 m = 0x9;
3303 i.vex.bytes[0] = 0x8f;
7f399153
L		 3304 break;
3305 case XOP0A:
f88c9eb0
SP		 3306 m = 0xa;
3307 i.vex.bytes[0] = 0x8f;
7f399153
L		 3308 break;
3309 default:
3310 abort ();
f88c9eb0 3311 }
c0f3af97 3312
c0f3af97
L		 3313 /* The high 3 bits of the second VEX byte are 1's compliment
3314 of RXB bits from REX. */
3315 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3316
3317 /* Check the REX.W bit. */
3318 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3319 if (i.tm.opcode_modifier.vexw == VEXW1)
3320 w = 1;
c0f3af97
L		 3321
3322 i.vex.bytes[2] = (w << 7
3323 | register_specifier << 3
3324 | vector_length << 2
3325 | implied_prefix);
3326 }
3327}
3328
43234a1e
L		 3329/* Build the EVEX prefix. */
3330
3331static void
3332build_evex_prefix (void)
3333{
3334 unsigned int register_specifier;
3335 unsigned int implied_prefix;
3336 unsigned int m, w;
3337 rex_byte vrex_used = 0;
3338
3339 /* Check register specifier. */
3340 if (i.vex.register_specifier)
3341 {
3342 gas_assert ((i.vrex & REX_X) == 0);
3343
3344 register_specifier = i.vex.register_specifier->reg_num;
3345 if ((i.vex.register_specifier->reg_flags & RegRex))
3346 register_specifier += 8;
3347 /* The upper 16 registers are encoded in the fourth byte of the
3348 EVEX prefix. */
3349 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3350 i.vex.bytes[3] = 0x8;
3351 register_specifier = ~register_specifier & 0xf;
3352 }
3353 else
3354 {
3355 register_specifier = 0xf;
3356
3357 /* Encode upper 16 vector index register in the fourth byte of
3358 the EVEX prefix. */
3359 if (!(i.vrex & REX_X))
3360 i.vex.bytes[3] = 0x8;
3361 else
3362 vrex_used |= REX_X;
3363 }
3364
3365 switch ((i.tm.base_opcode >> 8) & 0xff)
3366 {
3367 case 0:
3368 implied_prefix = 0;
3369 break;
3370 case DATA_PREFIX_OPCODE:
3371 implied_prefix = 1;
3372 break;
3373 case REPE_PREFIX_OPCODE:
3374 implied_prefix = 2;
3375 break;
3376 case REPNE_PREFIX_OPCODE:
3377 implied_prefix = 3;
3378 break;
3379 default:
3380 abort ();
3381 }
3382
3383 /* 4 byte EVEX prefix. */
3384 i.vex.length = 4;
3385 i.vex.bytes[0] = 0x62;
3386
3387 /* mmmm bits. */
3388 switch (i.tm.opcode_modifier.vexopcode)
3389 {
3390 case VEX0F:
3391 m = 1;
3392 break;
3393 case VEX0F38:
3394 m = 2;
3395 break;
3396 case VEX0F3A:
3397 m = 3;
3398 break;
3399 default:
3400 abort ();
3401 break;
3402 }
3403
3404 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3405 bits from REX. */
3406 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3407
3408 /* The fifth bit of the second EVEX byte is 1's compliment of the
3409 REX_R bit in VREX. */
3410 if (!(i.vrex & REX_R))
3411 i.vex.bytes[1] |= 0x10;
3412 else
3413 vrex_used |= REX_R;
3414
3415 if ((i.reg_operands + i.imm_operands) == i.operands)
3416 {
3417 /* When all operands are registers, the REX_X bit in REX is not
3418 used. We reuse it to encode the upper 16 registers, which is
3419 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3420 as 1's compliment. */
3421 if ((i.vrex & REX_B))
3422 {
3423 vrex_used |= REX_B;
3424 i.vex.bytes[1] &= ~0x40;
3425 }
3426 }
3427
3428 /* EVEX instructions shouldn't need the REX prefix. */
3429 i.vrex &= ~vrex_used;
3430 gas_assert (i.vrex == 0);
3431
3432 /* Check the REX.W bit. */
3433 w = (i.rex & REX_W) ? 1 : 0;
3434 if (i.tm.opcode_modifier.vexw)
3435 {
3436 if (i.tm.opcode_modifier.vexw == VEXW1)
3437 w = 1;
3438 }
3439 /* If w is not set it means we are dealing with WIG instruction. */
3440 else if (!w)
3441 {
3442 if (evexwig == evexw1)
3443 w = 1;
3444 }
3445
3446 /* Encode the U bit. */
3447 implied_prefix |= 0x4;
3448
3449 /* The third byte of the EVEX prefix. */
3450 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3451
3452 /* The fourth byte of the EVEX prefix. */
3453 /* The zeroing-masking bit. */
3454 if (i.mask && i.mask->zeroing)
3455 i.vex.bytes[3] |= 0x80;
3456
3457 /* Don't always set the broadcast bit if there is no RC. */
3458 if (!i.rounding)
3459 {
3460 /* Encode the vector length. */
3461 unsigned int vec_length;
3462
3463 switch (i.tm.opcode_modifier.evex)
3464 {
3465 case EVEXLIG: /* LL' is ignored */
3466 vec_length = evexlig << 5;
3467 break;
3468 case EVEX128:
3469 vec_length = 0 << 5;
3470 break;
3471 case EVEX256:
3472 vec_length = 1 << 5;
3473 break;
3474 case EVEX512:
3475 vec_length = 2 << 5;
3476 break;
3477 default:
3478 abort ();
3479 break;
3480 }
3481 i.vex.bytes[3] |= vec_length;
3482 /* Encode the broadcast bit. */
3483 if (i.broadcast)
3484 i.vex.bytes[3] |= 0x10;
3485 }
3486 else
3487 {
3488 if (i.rounding->type != saeonly)
3489 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3490 else
d3d3c6db 3491 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3492 }
3493
3494 if (i.mask && i.mask->mask)
3495 i.vex.bytes[3] |= i.mask->mask->reg_num;
3496}
3497
65da13b5
L		 3498static void
3499process_immext (void)
3500{
3501 expressionS *exp;
3502
4c692bc7
JB		 3503 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3504 && i.operands > 0)
65da13b5 3505 {
4c692bc7
JB		 3506 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3507 with an opcode suffix which is coded in the same place as an
3508 8-bit immediate field would be.
3509 Here we check those operands and remove them afterwards. */
65da13b5
L		 3510 unsigned int x;
3511
3512 for (x = 0; x < i.operands; x++)
4c692bc7 3513 if (register_number (i.op[x].regs) != x)
65da13b5 3514 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3515 register_prefix, i.op[x].regs->reg_name, x + 1,
3516 i.tm.name);
3517
3518 i.operands = 0;
65da13b5
L		 3519 }
3520
9916071f
AP		 3521 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3522 {
3523 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3524 suffix which is coded in the same place as an 8-bit immediate
3525 field would be.
3526 Here we check those operands and remove them afterwards. */
3527 unsigned int x;
3528
3529 if (i.operands != 3)
3530 abort();
3531
3532 for (x = 0; x < 2; x++)
3533 if (register_number (i.op[x].regs) != x)
3534 goto bad_register_operand;
3535
3536 /* Check for third operand for mwaitx/monitorx insn. */
3537 if (register_number (i.op[x].regs)
3538 != (x + (i.tm.extension_opcode == 0xfb)))
3539 {
3540bad_register_operand:
3541 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3542 register_prefix, i.op[x].regs->reg_name, x+1,
3543 i.tm.name);
3544 }
3545
3546 i.operands = 0;
3547 }
3548
c0f3af97 3549 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3550 which is coded in the same place as an 8-bit immediate field
3551 would be. Here we fake an 8-bit immediate operand from the
3552 opcode suffix stored in tm.extension_opcode.
3553
c1e679ec 3554 AVX instructions also use this encoding, for some of
c0f3af97 3555 3 argument instructions. */
65da13b5 3556
43234a1e 3557 gas_assert (i.imm_operands <= 1
7ab9ffdd 3558 && (i.operands <= 2
43234a1e
L		 3559 || ((i.tm.opcode_modifier.vex
3560 || i.tm.opcode_modifier.evex)
7ab9ffdd 3561 && i.operands <= 4)));
65da13b5
L		 3562
3563 exp = &im_expressions[i.imm_operands++];
3564 i.op[i.operands].imms = exp;
3565 i.types[i.operands] = imm8;
3566 i.operands++;
3567 exp->X_op = O_constant;
3568 exp->X_add_number = i.tm.extension_opcode;
3569 i.tm.extension_opcode = None;
3570}
3571
42164a71
L		 3572
3573static int
3574check_hle (void)
3575{
3576 switch (i.tm.opcode_modifier.hleprefixok)
3577 {
3578 default:
3579 abort ();
82c2def5 3580 case HLEPrefixNone:
165de32a
L		 3581 as_bad (_("invalid instruction `%s' after `%s'"),
3582 i.tm.name, i.hle_prefix);
42164a71 3583 return 0;
82c2def5 3584 case HLEPrefixLock:
42164a71
L		 3585 if (i.prefix[LOCK_PREFIX])
3586 return 1;
165de32a 3587 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3588 return 0;
82c2def5 3589 case HLEPrefixAny:
42164a71 3590 return 1;
82c2def5 3591 case HLEPrefixRelease:
42164a71
L		 3592 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3593 {
3594 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3595 i.tm.name);
3596 return 0;
3597 }
3598 if (i.mem_operands == 0
3599 || !operand_type_check (i.types[i.operands - 1], anymem))
3600 {
3601 as_bad (_("memory destination needed for instruction `%s'"
3602 " after `xrelease'"), i.tm.name);
3603 return 0;
3604 }
3605 return 1;
3606 }
3607}
3608
252b5132
RH		 3609/* This is the guts of the machine-dependent assembler. LINE points to a
3610 machine dependent instruction. This function is supposed to emit
3611 the frags/bytes it assembles to. */
3612
3613void
65da13b5 3614md_assemble (char *line)
252b5132 3615{
40fb9820 3616 unsigned int j;
83b16ac6 3617 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
d3ce72d0 3618 const insn_template *t;
252b5132 3619
47926f60 3620 /* Initialize globals. */
252b5132
RH		 3621 memset (&i, '\0', sizeof (i));
3622 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3623 i.reloc[j] = NO_RELOC;
252b5132
RH		 3624 memset (disp_expressions, '\0', sizeof (disp_expressions));
3625 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3626 save_stack_p = save_stack;
252b5132
RH		 3627
3628 /* First parse an instruction mnemonic & call i386_operand for the operands.
3629 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3630 start of a (possibly prefixed) mnemonic. */
252b5132 3631
29b0f896
AM		 3632 line = parse_insn (line, mnemonic);
3633 if (line == NULL)
3634 return;
83b16ac6 3635 mnem_suffix = i.suffix;
252b5132 3636
29b0f896 3637 line = parse_operands (line, mnemonic);
ee86248c 3638 this_operand = -1;
8325cc63
JB		 3639 xfree (i.memop1_string);
3640 i.memop1_string = NULL;
29b0f896
AM		 3641 if (line == NULL)
3642 return;
252b5132 3643
29b0f896
AM		 3644 /* Now we've parsed the mnemonic into a set of templates, and have the
3645 operands at hand. */
3646
3647 /* All intel opcodes have reversed operands except for "bound" and
3648 "enter". We also don't reverse intersegment "jmp" and "call"
3649 instructions with 2 immediate operands so that the immediate segment
050dfa73 3650 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3651 if (intel_syntax
3652 && i.operands > 1
29b0f896 3653 && (strcmp (mnemonic, "bound") != 0)
30123838 3654 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3655 && !(operand_type_check (i.types[0], imm)
3656 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3657 swap_operands ();
3658
ec56d5c0
JB		 3659 /* The order of the immediates should be reversed
3660 for 2 immediates extrq and insertq instructions */
3661 if (i.imm_operands == 2
3662 && (strcmp (mnemonic, "extrq") == 0
3663 || strcmp (mnemonic, "insertq") == 0))
3664 swap_2_operands (0, 1);
3665
29b0f896
AM		 3666 if (i.imm_operands)
3667 optimize_imm ();
3668
b300c311
L		 3669 /* Don't optimize displacement for movabs since it only takes 64bit
3670 displacement. */
3671 if (i.disp_operands
a501d77e 3672 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3673 && (flag_code != CODE_64BIT
3674 || strcmp (mnemonic, "movabs") != 0))
3675 optimize_disp ();
29b0f896
AM		 3676
3677 /* Next, we find a template that matches the given insn,
3678 making sure the overlap of the given operands types is consistent
3679 with the template operand types. */
252b5132 3680
83b16ac6 3681 if (!(t = match_template (mnem_suffix)))
29b0f896 3682 return;
252b5132 3683
7bab8ab5 3684 if (sse_check != check_none
81f8a913 3685 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3686 && (i.tm.cpu_flags.bitfield.cpusse
3687 || i.tm.cpu_flags.bitfield.cpusse2
3688 || i.tm.cpu_flags.bitfield.cpusse3
3689 || i.tm.cpu_flags.bitfield.cpussse3
3690 || i.tm.cpu_flags.bitfield.cpusse4_1
3691 || i.tm.cpu_flags.bitfield.cpusse4_2))
3692 {
7bab8ab5 3693 (sse_check == check_warning
daf50ae7
L		 3694 ? as_warn
3695 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3696 }
3697
321fd21e
L		 3698 /* Zap movzx and movsx suffix. The suffix has been set from
3699 "word ptr" or "byte ptr" on the source operand in Intel syntax
3700 or extracted from mnemonic in AT&T syntax. But we'll use
3701 the destination register to choose the suffix for encoding. */
3702 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3703 {
321fd21e
L		 3704 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3705 there is no suffix, the default will be byte extension. */
3706 if (i.reg_operands != 2
3707 && !i.suffix
7ab9ffdd 3708 && intel_syntax)
321fd21e
L		 3709 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3710
3711 i.suffix = 0;
cd61ebfe 3712 }
24eab124 3713
40fb9820 3714 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3715 if (!add_prefix (FWAIT_OPCODE))
3716 return;
252b5132 3717
d5de92cf
L		 3718 /* Check if REP prefix is OK. */
3719 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3720 {
3721 as_bad (_("invalid instruction `%s' after `%s'"),
3722 i.tm.name, i.rep_prefix);
3723 return;
3724 }
3725
c1ba0266
L		 3726 /* Check for lock without a lockable instruction. Destination operand
3727 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3728 if (i.prefix[LOCK_PREFIX]
3729 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3730 || i.mem_operands == 0
3731 || (i.tm.base_opcode != 0x86
3732 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3733 {
3734 as_bad (_("expecting lockable instruction after `lock'"));
3735 return;
3736 }
3737
42164a71 3738 /* Check if HLE prefix is OK. */
165de32a 3739 if (i.hle_prefix && !check_hle ())
42164a71
L		 3740 return;
3741
7e8b059b
L		 3742 /* Check BND prefix. */
3743 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3744 as_bad (_("expecting valid branch instruction after `bnd'"));
3745
04ef582a 3746 /* Check NOTRACK prefix. */
9fef80d6
L		 3747 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
3748 as_bad (_("expecting indirect branch instruction after `notrack'"));
04ef582a 3749
327e8c42
JB		 3750 if (i.tm.cpu_flags.bitfield.cpumpx)
3751 {
3752 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
3753 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3754 else if (flag_code != CODE_16BIT
3755 ? i.prefix[ADDR_PREFIX]
3756 : i.mem_operands && !i.prefix[ADDR_PREFIX])
3757 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3758 }
7e8b059b
L		 3759
3760 /* Insert BND prefix. */
3761 if (add_bnd_prefix
3762 && i.tm.opcode_modifier.bndprefixok
3763 && !i.prefix[BND_PREFIX])
3764 add_prefix (BND_PREFIX_OPCODE);
3765
29b0f896 3766 /* Check string instruction segment overrides. */
40fb9820 3767 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3768 {
3769 if (!check_string ())
5dd0794d 3770 return;
fc0763e6 3771 i.disp_operands = 0;
29b0f896 3772 }
5dd0794d 3773
29b0f896
AM		 3774 if (!process_suffix ())
3775 return;
e413e4e9 3776
bc0844ae
L		 3777 /* Update operand types. */
3778 for (j = 0; j < i.operands; j++)
3779 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3780
29b0f896
AM		 3781 /* Make still unresolved immediate matches conform to size of immediate
3782 given in i.suffix. */
3783 if (!finalize_imm ())
3784 return;
252b5132 3785
40fb9820 3786 if (i.types[0].bitfield.imm1)
29b0f896 3787 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3788
9afe6eb8
L		 3789 /* We only need to check those implicit registers for instructions
3790 with 3 operands or less. */
3791 if (i.operands <= 3)
3792 for (j = 0; j < i.operands; j++)
3793 if (i.types[j].bitfield.inoutportreg
3794 || i.types[j].bitfield.shiftcount
3795 || i.types[j].bitfield.acc
3796 || i.types[j].bitfield.floatacc)
3797 i.reg_operands--;
40fb9820 3798
c0f3af97
L		 3799 /* ImmExt should be processed after SSE2AVX. */
3800 if (!i.tm.opcode_modifier.sse2avx
3801 && i.tm.opcode_modifier.immext)
65da13b5 3802 process_immext ();
252b5132 3803
29b0f896
AM		 3804 /* For insns with operands there are more diddles to do to the opcode. */
3805 if (i.operands)
3806 {
3807 if (!process_operands ())
3808 return;
3809 }
40fb9820 3810 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3811 {
3812 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3813 as_warn (_("translating to `%sp'"), i.tm.name);
3814 }
252b5132 3815
9e5e5283
L		 3816 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3817 {
3818 if (flag_code == CODE_16BIT)
3819 {
3820 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3821 i.tm.name);
3822 return;
3823 }
c0f3af97 3824
9e5e5283
L		 3825 if (i.tm.opcode_modifier.vex)
3826 build_vex_prefix (t);
3827 else
3828 build_evex_prefix ();
3829 }
43234a1e 3830
5dd85c99
SP		 3831 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3832 instructions may define INT_OPCODE as well, so avoid this corner
3833 case for those instructions that use MODRM. */
3834 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3835 && !i.tm.opcode_modifier.modrm
3836 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3837 {
3838 i.tm.base_opcode = INT3_OPCODE;
3839 i.imm_operands = 0;
3840 }
252b5132 3841
40fb9820
L		 3842 if ((i.tm.opcode_modifier.jump
3843 || i.tm.opcode_modifier.jumpbyte
3844 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3845 && i.op[0].disps->X_op == O_constant)
3846 {
3847 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3848 the absolute address given by the constant. Since ix86 jumps and
3849 calls are pc relative, we need to generate a reloc. */
3850 i.op[0].disps->X_add_symbol = &abs_symbol;
3851 i.op[0].disps->X_op = O_symbol;
3852 }
252b5132 3853
40fb9820 3854 if (i.tm.opcode_modifier.rex64)
161a04f6 3855 i.rex |= REX_W;
252b5132 3856
29b0f896
AM		 3857 /* For 8 bit registers we need an empty rex prefix. Also if the
3858 instruction already has a prefix, we need to convert old
3859 registers to new ones. */
773f551c 3860
40fb9820 3861 if ((i.types[0].bitfield.reg8
29b0f896 3862 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3863 || (i.types[1].bitfield.reg8
29b0f896 3864 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3865 || ((i.types[0].bitfield.reg8
3866 || i.types[1].bitfield.reg8)
29b0f896
AM		 3867 && i.rex != 0))
3868 {
3869 int x;
726c5dcd 3870
29b0f896
AM		 3871 i.rex |= REX_OPCODE;
3872 for (x = 0; x < 2; x++)
3873 {
3874 /* Look for 8 bit operand that uses old registers. */
40fb9820 3875 if (i.types[x].bitfield.reg8
29b0f896 3876 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3877 {
29b0f896
AM		 3878 /* In case it is "hi" register, give up. */
3879 if (i.op[x].regs->reg_num > 3)
a540244d 3880 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3881 "instruction requiring REX prefix."),
a540244d 3882 register_prefix, i.op[x].regs->reg_name);
773f551c 3883
29b0f896
AM		 3884 /* Otherwise it is equivalent to the extended register.
3885 Since the encoding doesn't change this is merely
3886 cosmetic cleanup for debug output. */
3887
3888 i.op[x].regs = i.op[x].regs + 8;
773f551c 3889 }
29b0f896
AM		 3890 }
3891 }
773f551c 3892
7ab9ffdd 3893 if (i.rex != 0)
29b0f896
AM		 3894 add_prefix (REX_OPCODE | i.rex);
3895
3896 /* We are ready to output the insn. */
3897 output_insn ();
3898}
3899
3900static char *
e3bb37b5 3901parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3902{
3903 char *l = line;
3904 char *token_start = l;
3905 char *mnem_p;
5c6af06e 3906 int supported;
d3ce72d0 3907 const insn_template *t;
b6169b20 3908 char *dot_p = NULL;
29b0f896 3909
29b0f896
AM		 3910 while (1)
3911 {
3912 mnem_p = mnemonic;
3913 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3914 {
b6169b20
L		 3915 if (*mnem_p == '.')
3916 dot_p = mnem_p;
29b0f896
AM		 3917 mnem_p++;
3918 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3919 {
29b0f896
AM		 3920 as_bad (_("no such instruction: `%s'"), token_start);
3921 return NULL;
3922 }
3923 l++;
3924 }
3925 if (!is_space_char (*l)
3926 && *l != END_OF_INSN
e44823cf
JB		 3927 && (intel_syntax
3928 || (*l != PREFIX_SEPARATOR
3929 && *l != ',')))
29b0f896
AM		 3930 {
3931 as_bad (_("invalid character %s in mnemonic"),
3932 output_invalid (*l));
3933 return NULL;
3934 }
3935 if (token_start == l)
3936 {
e44823cf 3937 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3938 as_bad (_("expecting prefix; got nothing"));
3939 else
3940 as_bad (_("expecting mnemonic; got nothing"));
3941 return NULL;
3942 }
45288df1 3943
29b0f896 3944 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3945 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3946
29b0f896
AM		 3947 if (*l != END_OF_INSN
3948 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3949 && current_templates
40fb9820 3950 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3951 {
c6fb90c8 3952 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3953 {
3954 as_bad ((flag_code != CODE_64BIT
3955 ? _("`%s' is only supported in 64-bit mode")
3956 : _("`%s' is not supported in 64-bit mode")),
3957 current_templates->start->name);
3958 return NULL;
3959 }
29b0f896
AM		 3960 /* If we are in 16-bit mode, do not allow addr16 or data16.
3961 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3962 if ((current_templates->start->opcode_modifier.size16
3963 || current_templates->start->opcode_modifier.size32)
29b0f896 3964 && flag_code != CODE_64BIT
40fb9820 3965 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3966 ^ (flag_code == CODE_16BIT)))
3967 {
3968 as_bad (_("redundant %s prefix"),
3969 current_templates->start->name);
3970 return NULL;
45288df1 3971 }
86fa6981 3972 if (current_templates->start->opcode_length == 0)
29b0f896 3973 {
86fa6981
L		 3974 /* Handle pseudo prefixes. */
3975 switch (current_templates->start->base_opcode)
3976 {
3977 case 0x0:
3978 /* {disp8} */
3979 i.disp_encoding = disp_encoding_8bit;
3980 break;
3981 case 0x1:
3982 /* {disp32} */
3983 i.disp_encoding = disp_encoding_32bit;
3984 break;
3985 case 0x2:
3986 /* {load} */
3987 i.dir_encoding = dir_encoding_load;
3988 break;
3989 case 0x3:
3990 /* {store} */
3991 i.dir_encoding = dir_encoding_store;
3992 break;
3993 case 0x4:
3994 /* {vex2} */
3995 i.vec_encoding = vex_encoding_vex2;
3996 break;
3997 case 0x5:
3998 /* {vex3} */
3999 i.vec_encoding = vex_encoding_vex3;
4000 break;
4001 case 0x6:
4002 /* {evex} */
4003 i.vec_encoding = vex_encoding_evex;
4004 break;
4005 default:
4006 abort ();
4007 }
4008 }
4009 else
4010 {
4011 /* Add prefix, checking for repeated prefixes. */
4e9ac44a 4012 switch (add_prefix (current_templates->start->base_opcode))
86fa6981 4013 {
4e9ac44a
L		 4014 case PREFIX_EXIST:
4015 return NULL;
4016 case PREFIX_DS:
4017 if (current_templates->start->cpu_flags.bitfield.cpucet)
4018 i.notrack_prefix = current_templates->start->name;
4019 break;
4020 case PREFIX_REP:
4021 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4022 i.hle_prefix = current_templates->start->name;
4023 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4024 i.bnd_prefix = current_templates->start->name;
4025 else
4026 i.rep_prefix = current_templates->start->name;
4027 break;
4028 default:
4029 break;
86fa6981 4030 }
29b0f896
AM		 4031 }
4032 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4033 token_start = ++l;
4034 }
4035 else
4036 break;
4037 }
45288df1 4038
30a55f88 4039 if (!current_templates)
b6169b20 4040 {
f8a5c266
L		 4041 /* Check if we should swap operand or force 32bit displacement in
4042 encoding. */
30a55f88 4043 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
86fa6981 4044 i.dir_encoding = dir_encoding_store;
8d63c93e 4045 else if (mnem_p - 3 == dot_p
a501d77e
L		 4046 && dot_p[1] == 'd'
4047 && dot_p[2] == '8')
4048 i.disp_encoding = disp_encoding_8bit;
8d63c93e 4049 else if (mnem_p - 4 == dot_p
f8a5c266
L		 4050 && dot_p[1] == 'd'
4051 && dot_p[2] == '3'
4052 && dot_p[3] == '2')
a501d77e 4053 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 4054 else
4055 goto check_suffix;
4056 mnem_p = dot_p;
4057 *dot_p = '\0';
d3ce72d0 4058 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 4059 }
4060
29b0f896
AM		 4061 if (!current_templates)
4062 {
b6169b20 4063check_suffix:
29b0f896
AM		 4064 /* See if we can get a match by trimming off a suffix. */
4065 switch (mnem_p[-1])
4066 {
4067 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 4068 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4069 i.suffix = SHORT_MNEM_SUFFIX;
4070 else
1a0670f3 4071 /* Fall through. */
29b0f896
AM		 4072 case BYTE_MNEM_SUFFIX:
4073 case QWORD_MNEM_SUFFIX:
4074 i.suffix = mnem_p[-1];
4075 mnem_p[-1] = '\0';
d3ce72d0
NC		 4076 current_templates = (const templates *) hash_find (op_hash,
4077 mnemonic);
29b0f896
AM		 4078 break;
4079 case SHORT_MNEM_SUFFIX:
4080 case LONG_MNEM_SUFFIX:
4081 if (!intel_syntax)
4082 {
4083 i.suffix = mnem_p[-1];
4084 mnem_p[-1] = '\0';
d3ce72d0
NC		 4085 current_templates = (const templates *) hash_find (op_hash,
4086 mnemonic);
29b0f896
AM		 4087 }
4088 break;
252b5132 4089
29b0f896
AM		 4090 /* Intel Syntax. */
4091 case 'd':
4092 if (intel_syntax)
4093 {
9306ca4a 4094 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 4095 i.suffix = SHORT_MNEM_SUFFIX;
4096 else
4097 i.suffix = LONG_MNEM_SUFFIX;
4098 mnem_p[-1] = '\0';
d3ce72d0
NC		 4099 current_templates = (const templates *) hash_find (op_hash,
4100 mnemonic);
29b0f896
AM		 4101 }
4102 break;
4103 }
4104 if (!current_templates)
4105 {
4106 as_bad (_("no such instruction: `%s'"), token_start);
4107 return NULL;
4108 }
4109 }
252b5132 4110
40fb9820
L		 4111 if (current_templates->start->opcode_modifier.jump
4112 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 4113 {
4114 /* Check for a branch hint. We allow ",pt" and ",pn" for
4115 predict taken and predict not taken respectively.
4116 I'm not sure that branch hints actually do anything on loop
4117 and jcxz insns (JumpByte) for current Pentium4 chips. They
4118 may work in the future and it doesn't hurt to accept them
4119 now. */
4120 if (l[0] == ',' && l[1] == 'p')
4121 {
4122 if (l[2] == 't')
4123 {
4124 if (!add_prefix (DS_PREFIX_OPCODE))
4125 return NULL;
4126 l += 3;
4127 }
4128 else if (l[2] == 'n')
4129 {
4130 if (!add_prefix (CS_PREFIX_OPCODE))
4131 return NULL;
4132 l += 3;
4133 }
4134 }
4135 }
4136 /* Any other comma loses. */
4137 if (*l == ',')
4138 {
4139 as_bad (_("invalid character %s in mnemonic"),
4140 output_invalid (*l));
4141 return NULL;
4142 }
252b5132 4143
29b0f896 4144 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 4145 supported = 0;
4146 for (t = current_templates->start; t < current_templates->end; ++t)
4147 {
c0f3af97
L		 4148 supported |= cpu_flags_match (t);
4149 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 4150 goto skip;
5c6af06e 4151 }
3629bb00 4152
c0f3af97 4153 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 4154 {
4155 as_bad (flag_code == CODE_64BIT
4156 ? _("`%s' is not supported in 64-bit mode")
4157 : _("`%s' is only supported in 64-bit mode"),
4158 current_templates->start->name);
4159 return NULL;
4160 }
c0f3af97 4161 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 4162 {
3629bb00 4163 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 4164 current_templates->start->name,
41aacd83 4165 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 4166 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4167 return NULL;
29b0f896 4168 }
3629bb00
L		 4169
4170skip:
4171 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 4172 && (flag_code != CODE_16BIT))
29b0f896
AM		 4173 {
4174 as_warn (_("use .code16 to ensure correct addressing mode"));
4175 }
252b5132 4176
29b0f896
AM		 4177 return l;
4178}
252b5132 4179
29b0f896 4180static char *
e3bb37b5 4181parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4182{
4183 char *token_start;
3138f287 4184
29b0f896
AM		 4185 /* 1 if operand is pending after ','. */
4186 unsigned int expecting_operand = 0;
252b5132 4187
29b0f896
AM		 4188 /* Non-zero if operand parens not balanced. */
4189 unsigned int paren_not_balanced;
4190
4191 while (*l != END_OF_INSN)
4192 {
4193 /* Skip optional white space before operand. */
4194 if (is_space_char (*l))
4195 ++l;
d02603dc 4196 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4197 {
4198 as_bad (_("invalid character %s before operand %d"),
4199 output_invalid (*l),
4200 i.operands + 1);
4201 return NULL;
4202 }
d02603dc 4203 token_start = l; /* After white space. */
29b0f896
AM		 4204 paren_not_balanced = 0;
4205 while (paren_not_balanced || *l != ',')
4206 {
4207 if (*l == END_OF_INSN)
4208 {
4209 if (paren_not_balanced)
4210 {
4211 if (!intel_syntax)
4212 as_bad (_("unbalanced parenthesis in operand %d."),
4213 i.operands + 1);
4214 else
4215 as_bad (_("unbalanced brackets in operand %d."),
4216 i.operands + 1);
4217 return NULL;
4218 }
4219 else
4220 break; /* we are done */
4221 }
d02603dc 4222 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4223 {
4224 as_bad (_("invalid character %s in operand %d"),
4225 output_invalid (*l),
4226 i.operands + 1);
4227 return NULL;
4228 }
4229 if (!intel_syntax)
4230 {
4231 if (*l == '(')
4232 ++paren_not_balanced;
4233 if (*l == ')')
4234 --paren_not_balanced;
4235 }
4236 else
4237 {
4238 if (*l == '[')
4239 ++paren_not_balanced;
4240 if (*l == ']')
4241 --paren_not_balanced;
4242 }
4243 l++;
4244 }
4245 if (l != token_start)
4246 { /* Yes, we've read in another operand. */
4247 unsigned int operand_ok;
4248 this_operand = i.operands++;
4249 if (i.operands > MAX_OPERANDS)
4250 {
4251 as_bad (_("spurious operands; (%d operands/instruction max)"),
4252 MAX_OPERANDS);
4253 return NULL;
4254 }
9d46ce34 4255 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4256 /* Now parse operand adding info to 'i' as we go along. */
4257 END_STRING_AND_SAVE (l);
4258
4259 if (intel_syntax)
4260 operand_ok =
4261 i386_intel_operand (token_start,
4262 intel_float_operand (mnemonic));
4263 else
a7619375 4264 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4265
4266 RESTORE_END_STRING (l);
4267 if (!operand_ok)
4268 return NULL;
4269 }
4270 else
4271 {
4272 if (expecting_operand)
4273 {
4274 expecting_operand_after_comma:
4275 as_bad (_("expecting operand after ','; got nothing"));
4276 return NULL;
4277 }
4278 if (*l == ',')
4279 {
4280 as_bad (_("expecting operand before ','; got nothing"));
4281 return NULL;
4282 }
4283 }
7f3f1ea2 4284
29b0f896
AM		 4285 /* Now *l must be either ',' or END_OF_INSN. */
4286 if (*l == ',')
4287 {
4288 if (*++l == END_OF_INSN)
4289 {
4290 /* Just skip it, if it's \n complain. */
4291 goto expecting_operand_after_comma;
4292 }
4293 expecting_operand = 1;
4294 }
4295 }
4296 return l;
4297}
7f3f1ea2 4298
050dfa73 4299static void
4d456e3d 4300swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4301{
4302 union i386_op temp_op;
40fb9820 4303 i386_operand_type temp_type;
050dfa73 4304 enum bfd_reloc_code_real temp_reloc;
4eed87de 4305
050dfa73
MM		 4306 temp_type = i.types[xchg2];
4307 i.types[xchg2] = i.types[xchg1];
4308 i.types[xchg1] = temp_type;
4309 temp_op = i.op[xchg2];
4310 i.op[xchg2] = i.op[xchg1];
4311 i.op[xchg1] = temp_op;
4312 temp_reloc = i.reloc[xchg2];
4313 i.reloc[xchg2] = i.reloc[xchg1];
4314 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4315
4316 if (i.mask)
4317 {
4318 if (i.mask->operand == xchg1)
4319 i.mask->operand = xchg2;
4320 else if (i.mask->operand == xchg2)
4321 i.mask->operand = xchg1;
4322 }
4323 if (i.broadcast)
4324 {
4325 if (i.broadcast->operand == xchg1)
4326 i.broadcast->operand = xchg2;
4327 else if (i.broadcast->operand == xchg2)
4328 i.broadcast->operand = xchg1;
4329 }
4330 if (i.rounding)
4331 {
4332 if (i.rounding->operand == xchg1)
4333 i.rounding->operand = xchg2;
4334 else if (i.rounding->operand == xchg2)
4335 i.rounding->operand = xchg1;
4336 }
050dfa73
MM		 4337}
4338
29b0f896 4339static void
e3bb37b5 4340swap_operands (void)
29b0f896 4341{
b7c61d9a 4342 switch (i.operands)
050dfa73 4343 {
c0f3af97 4344 case 5:
b7c61d9a 4345 case 4:
4d456e3d 4346 swap_2_operands (1, i.operands - 2);
1a0670f3 4347 /* Fall through. */
b7c61d9a
L		 4348 case 3:
4349 case 2:
4d456e3d 4350 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4351 break;
4352 default:
4353 abort ();
29b0f896 4354 }
29b0f896
AM		 4355
4356 if (i.mem_operands == 2)
4357 {
4358 const seg_entry *temp_seg;
4359 temp_seg = i.seg[0];
4360 i.seg[0] = i.seg[1];
4361 i.seg[1] = temp_seg;
4362 }
4363}
252b5132 4364
29b0f896
AM		 4365/* Try to ensure constant immediates are represented in the smallest
4366 opcode possible. */
4367static void
e3bb37b5 4368optimize_imm (void)
29b0f896
AM		 4369{
4370 char guess_suffix = 0;
4371 int op;
252b5132 4372
29b0f896
AM		 4373 if (i.suffix)
4374 guess_suffix = i.suffix;
4375 else if (i.reg_operands)
4376 {
4377 /* Figure out a suffix from the last register operand specified.
4378 We can't do this properly yet, ie. excluding InOutPortReg,
4379 but the following works for instructions with immediates.
4380 In any case, we can't set i.suffix yet. */
4381 for (op = i.operands; --op >= 0;)
40fb9820 4382 if (i.types[op].bitfield.reg8)
7ab9ffdd 4383 {
40fb9820
L		 4384 guess_suffix = BYTE_MNEM_SUFFIX;
4385 break;
4386 }
4387 else if (i.types[op].bitfield.reg16)
252b5132 4388 {
40fb9820
L		 4389 guess_suffix = WORD_MNEM_SUFFIX;
4390 break;
4391 }
4392 else if (i.types[op].bitfield.reg32)
4393 {
4394 guess_suffix = LONG_MNEM_SUFFIX;
4395 break;
4396 }
4397 else if (i.types[op].bitfield.reg64)
4398 {
4399 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4400 break;
252b5132 4401 }
29b0f896
AM		 4402 }
4403 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4404 guess_suffix = WORD_MNEM_SUFFIX;
4405
4406 for (op = i.operands; --op >= 0;)
40fb9820 4407 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4408 {
4409 switch (i.op[op].imms->X_op)
252b5132 4410 {
29b0f896
AM		 4411 case O_constant:
4412 /* If a suffix is given, this operand may be shortened. */
4413 switch (guess_suffix)
252b5132 4414 {
29b0f896 4415 case LONG_MNEM_SUFFIX:
40fb9820
L		 4416 i.types[op].bitfield.imm32 = 1;
4417 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4418 break;
4419 case WORD_MNEM_SUFFIX:
40fb9820
L		 4420 i.types[op].bitfield.imm16 = 1;
4421 i.types[op].bitfield.imm32 = 1;
4422 i.types[op].bitfield.imm32s = 1;
4423 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4424 break;
4425 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4426 i.types[op].bitfield.imm8 = 1;
4427 i.types[op].bitfield.imm8s = 1;
4428 i.types[op].bitfield.imm16 = 1;
4429 i.types[op].bitfield.imm32 = 1;
4430 i.types[op].bitfield.imm32s = 1;
4431 i.types[op].bitfield.imm64 = 1;
29b0f896 4432 break;
252b5132 4433 }
252b5132 4434
29b0f896
AM		 4435 /* If this operand is at most 16 bits, convert it
4436 to a signed 16 bit number before trying to see
4437 whether it will fit in an even smaller size.
4438 This allows a 16-bit operand such as $0xffe0 to
4439 be recognised as within Imm8S range. */
40fb9820 4440 if ((i.types[op].bitfield.imm16)
29b0f896 4441 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4442 {
29b0f896
AM		 4443 i.op[op].imms->X_add_number =
4444 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4445 }
a28def75
L		 4446#ifdef BFD64
4447 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4448 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4449 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4450 == 0))
4451 {
4452 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4453 ^ ((offsetT) 1 << 31))
4454 - ((offsetT) 1 << 31));
4455 }
a28def75 4456#endif
40fb9820 4457 i.types[op]
c6fb90c8
L		 4458 = operand_type_or (i.types[op],
4459 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4460
29b0f896
AM		 4461 /* We must avoid matching of Imm32 templates when 64bit
4462 only immediate is available. */
4463 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4464 i.types[op].bitfield.imm32 = 0;
29b0f896 4465 break;
252b5132 4466
29b0f896
AM		 4467 case O_absent:
4468 case O_register:
4469 abort ();
4470
4471 /* Symbols and expressions. */
4472 default:
9cd96992
JB		 4473 /* Convert symbolic operand to proper sizes for matching, but don't
4474 prevent matching a set of insns that only supports sizes other
4475 than those matching the insn suffix. */
4476 {
40fb9820 4477 i386_operand_type mask, allowed;
d3ce72d0 4478 const insn_template *t;
9cd96992 4479
0dfbf9d7
L		 4480 operand_type_set (&mask, 0);
4481 operand_type_set (&allowed, 0);
40fb9820 4482
4eed87de
AM		 4483 for (t = current_templates->start;
4484 t < current_templates->end;
4485 ++t)
c6fb90c8
L		 4486 allowed = operand_type_or (allowed,
4487 t->operand_types[op]);
9cd96992
JB		 4488 switch (guess_suffix)
4489 {
4490 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4491 mask.bitfield.imm64 = 1;
4492 mask.bitfield.imm32s = 1;
9cd96992
JB		 4493 break;
4494 case LONG_MNEM_SUFFIX:
40fb9820 4495 mask.bitfield.imm32 = 1;
9cd96992
JB		 4496 break;
4497 case WORD_MNEM_SUFFIX:
40fb9820 4498 mask.bitfield.imm16 = 1;
9cd96992
JB		 4499 break;
4500 case BYTE_MNEM_SUFFIX:
40fb9820 4501 mask.bitfield.imm8 = 1;
9cd96992
JB		 4502 break;
4503 default:
9cd96992
JB		 4504 break;
4505 }
c6fb90c8 4506 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4507 if (!operand_type_all_zero (&allowed))
c6fb90c8 4508 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4509 }
29b0f896 4510 break;
252b5132 4511 }
29b0f896
AM		 4512 }
4513}
47926f60 4514
29b0f896
AM		 4515/* Try to use the smallest displacement type too. */
4516static void
e3bb37b5 4517optimize_disp (void)
29b0f896
AM		 4518{
4519 int op;
3e73aa7c 4520
29b0f896 4521 for (op = i.operands; --op >= 0;)
40fb9820 4522 if (operand_type_check (i.types[op], disp))
252b5132 4523 {
b300c311 4524 if (i.op[op].disps->X_op == O_constant)
252b5132 4525 {
91d6fa6a 4526 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4527
40fb9820 4528 if (i.types[op].bitfield.disp16
91d6fa6a 4529 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4530 {
4531 /* If this operand is at most 16 bits, convert
4532 to a signed 16 bit number and don't use 64bit
4533 displacement. */
91d6fa6a 4534 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4535 i.types[op].bitfield.disp64 = 0;
b300c311 4536 }
a28def75
L		 4537#ifdef BFD64
4538 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4539 if (i.types[op].bitfield.disp32
91d6fa6a 4540 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4541 {
4542 /* If this operand is at most 32 bits, convert
4543 to a signed 32 bit number and don't use 64bit
4544 displacement. */
91d6fa6a
NC		 4545 op_disp &= (((offsetT) 2 << 31) - 1);
4546 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4547 i.types[op].bitfield.disp64 = 0;
b300c311 4548 }
a28def75 4549#endif
91d6fa6a 4550 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4551 {
40fb9820
L		 4552 i.types[op].bitfield.disp8 = 0;
4553 i.types[op].bitfield.disp16 = 0;
4554 i.types[op].bitfield.disp32 = 0;
4555 i.types[op].bitfield.disp32s = 0;
4556 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4557 i.op[op].disps = 0;
4558 i.disp_operands--;
4559 }
4560 else if (flag_code == CODE_64BIT)
4561 {
91d6fa6a 4562 if (fits_in_signed_long (op_disp))
28a9d8f5 4563 {
40fb9820
L		 4564 i.types[op].bitfield.disp64 = 0;
4565 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4566 }
0e1147d9 4567 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4568 && fits_in_unsigned_long (op_disp))
40fb9820 4569 i.types[op].bitfield.disp32 = 1;
b300c311 4570 }
40fb9820
L		 4571 if ((i.types[op].bitfield.disp32
4572 || i.types[op].bitfield.disp32s
4573 || i.types[op].bitfield.disp16)
91d6fa6a 4574 && fits_in_signed_byte (op_disp))
40fb9820 4575 i.types[op].bitfield.disp8 = 1;
252b5132 4576 }
67a4f2b7
AO		 4577 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4578 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4579 {
4580 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4581 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4582 i.types[op].bitfield.disp8 = 0;
4583 i.types[op].bitfield.disp16 = 0;
4584 i.types[op].bitfield.disp32 = 0;
4585 i.types[op].bitfield.disp32s = 0;
4586 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4587 }
4588 else
b300c311 4589 /* We only support 64bit displacement on constants. */
40fb9820 4590 i.types[op].bitfield.disp64 = 0;
252b5132 4591 }
29b0f896
AM		 4592}
4593
6c30d220
L		 4594/* Check if operands are valid for the instruction. */
4595
4596static int
4597check_VecOperands (const insn_template *t)
4598{
43234a1e
L		 4599 unsigned int op;
4600
6c30d220
L		 4601 /* Without VSIB byte, we can't have a vector register for index. */
4602 if (!t->opcode_modifier.vecsib
4603 && i.index_reg
4604 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4605 || i.index_reg->reg_type.bitfield.regymm
4606 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4607 {
4608 i.error = unsupported_vector_index_register;
4609 return 1;
4610 }
4611
ad8ecc81
MZ		 4612 /* Check if default mask is allowed. */
4613 if (t->opcode_modifier.nodefmask
4614 && (!i.mask || i.mask->mask->reg_num == 0))
4615 {
4616 i.error = no_default_mask;
4617 return 1;
4618 }
4619
7bab8ab5
JB		 4620 /* For VSIB byte, we need a vector register for index, and all vector
4621 registers must be distinct. */
4622 if (t->opcode_modifier.vecsib)
4623 {
4624 if (!i.index_reg
6c30d220
L		 4625 || !((t->opcode_modifier.vecsib == VecSIB128
4626 && i.index_reg->reg_type.bitfield.regxmm)
4627 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4628 && i.index_reg->reg_type.bitfield.regymm)
4629 || (t->opcode_modifier.vecsib == VecSIB512
4630 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4631 {
4632 i.error = invalid_vsib_address;
4633 return 1;
4634 }
4635
43234a1e
L		 4636 gas_assert (i.reg_operands == 2 || i.mask);
4637 if (i.reg_operands == 2 && !i.mask)
4638 {
4639 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4640 || i.types[0].bitfield.regymm);
43234a1e 4641 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4642 || i.types[2].bitfield.regymm);
43234a1e
L		 4643 if (operand_check == check_none)
4644 return 0;
4645 if (register_number (i.op[0].regs)
4646 != register_number (i.index_reg)
4647 && register_number (i.op[2].regs)
4648 != register_number (i.index_reg)
4649 && register_number (i.op[0].regs)
4650 != register_number (i.op[2].regs))
4651 return 0;
4652 if (operand_check == check_error)
4653 {
4654 i.error = invalid_vector_register_set;
4655 return 1;
4656 }
4657 as_warn (_("mask, index, and destination registers should be distinct"));
4658 }
8444f82a
MZ		 4659 else if (i.reg_operands == 1 && i.mask)
4660 {
514f6023
L		 4661 if ((i.types[1].bitfield.regxmm
4662 || i.types[1].bitfield.regymm
8444f82a
MZ		 4663 || i.types[1].bitfield.regzmm)
4664 && (register_number (i.op[1].regs)
4665 == register_number (i.index_reg)))
4666 {
4667 if (operand_check == check_error)
4668 {
4669 i.error = invalid_vector_register_set;
4670 return 1;
4671 }
4672 if (operand_check != check_none)
4673 as_warn (_("index and destination registers should be distinct"));
4674 }
4675 }
43234a1e 4676 }
7bab8ab5 4677
43234a1e
L		 4678 /* Check if broadcast is supported by the instruction and is applied
4679 to the memory operand. */
4680 if (i.broadcast)
4681 {
4682 int broadcasted_opnd_size;
4683
4684 /* Check if specified broadcast is supported in this instruction,
4685 and it's applied to memory operand of DWORD or QWORD type,
4686 depending on VecESize. */
4687 if (i.broadcast->type != t->opcode_modifier.broadcast
4688 || !i.types[i.broadcast->operand].bitfield.mem
4689 || (t->opcode_modifier.vecesize == 0
4690 && !i.types[i.broadcast->operand].bitfield.dword
4691 && !i.types[i.broadcast->operand].bitfield.unspecified)
4692 || (t->opcode_modifier.vecesize == 1
4693 && !i.types[i.broadcast->operand].bitfield.qword
4694 && !i.types[i.broadcast->operand].bitfield.unspecified))
4695 goto bad_broadcast;
4696
4697 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4698 if (i.broadcast->type == BROADCAST_1TO16)
4699 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4700 else if (i.broadcast->type == BROADCAST_1TO8)
4701 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4702 else if (i.broadcast->type == BROADCAST_1TO4)
4703 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4704 else if (i.broadcast->type == BROADCAST_1TO2)
4705 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4706 else
4707 goto bad_broadcast;
4708
4709 if ((broadcasted_opnd_size == 256
4710 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4711 || (broadcasted_opnd_size == 512
4712 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4713 {
4714 bad_broadcast:
4715 i.error = unsupported_broadcast;
4716 return 1;
4717 }
4718 }
4719 /* If broadcast is supported in this instruction, we need to check if
4720 operand of one-element size isn't specified without broadcast. */
4721 else if (t->opcode_modifier.broadcast && i.mem_operands)
4722 {
4723 /* Find memory operand. */
4724 for (op = 0; op < i.operands; op++)
4725 if (operand_type_check (i.types[op], anymem))
4726 break;
4727 gas_assert (op < i.operands);
4728 /* Check size of the memory operand. */
4729 if ((t->opcode_modifier.vecesize == 0
4730 && i.types[op].bitfield.dword)
4731 || (t->opcode_modifier.vecesize == 1
4732 && i.types[op].bitfield.qword))
4733 {
4734 i.error = broadcast_needed;
4735 return 1;
4736 }
4737 }
4738
4739 /* Check if requested masking is supported. */
4740 if (i.mask
4741 && (!t->opcode_modifier.masking
4742 || (i.mask->zeroing
4743 && t->opcode_modifier.masking == MERGING_MASKING)))
4744 {
4745 i.error = unsupported_masking;
4746 return 1;
4747 }
4748
4749 /* Check if masking is applied to dest operand. */
4750 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4751 {
4752 i.error = mask_not_on_destination;
4753 return 1;
4754 }
4755
43234a1e
L		 4756 /* Check RC/SAE. */
4757 if (i.rounding)
4758 {
4759 if ((i.rounding->type != saeonly
4760 && !t->opcode_modifier.staticrounding)
4761 || (i.rounding->type == saeonly
4762 && (t->opcode_modifier.staticrounding
4763 || !t->opcode_modifier.sae)))
4764 {
4765 i.error = unsupported_rc_sae;
4766 return 1;
4767 }
4768 /* If the instruction has several immediate operands and one of
4769 them is rounding, the rounding operand should be the last
4770 immediate operand. */
4771 if (i.imm_operands > 1
4772 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4773 {
43234a1e 4774 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4775 return 1;
4776 }
6c30d220
L		 4777 }
4778
43234a1e
L		 4779 /* Check vector Disp8 operand. */
4780 if (t->opcode_modifier.disp8memshift)
4781 {
4782 if (i.broadcast)
4783 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4784 else
4785 i.memshift = t->opcode_modifier.disp8memshift;
4786
4787 for (op = 0; op < i.operands; op++)
4788 if (operand_type_check (i.types[op], disp)
4789 && i.op[op].disps->X_op == O_constant)
4790 {
4791 offsetT value = i.op[op].disps->X_add_number;
5be33403
L		 4792 int vec_disp8_ok
4793 = (i.disp_encoding != disp_encoding_32bit
4794 && fits_in_vec_disp8 (value));
43234a1e
L		 4795 if (t->operand_types [op].bitfield.vec_disp8)
4796 {
4797 if (vec_disp8_ok)
4798 i.types[op].bitfield.vec_disp8 = 1;
4799 else
4800 {
4801 /* Vector insn can only have Vec_Disp8/Disp32 in
4802 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4803 mode. */
4804 i.types[op].bitfield.disp8 = 0;
4805 if (flag_code != CODE_16BIT)
4806 i.types[op].bitfield.disp16 = 0;
4807 }
4808 }
4809 else if (flag_code != CODE_16BIT)
4810 {
4811 /* One form of this instruction supports vector Disp8.
4812 Try vector Disp8 if we need to use Disp32. */
4813 if (vec_disp8_ok && !fits_in_signed_byte (value))
4814 {
4815 i.error = try_vector_disp8;
4816 return 1;
4817 }
4818 }
4819 }
4820 }
4821 else
4822 i.memshift = -1;
4823
6c30d220
L		 4824 return 0;
4825}
4826
43f3e2ee 4827/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4828 operand types. */
4829
4830static int
4831VEX_check_operands (const insn_template *t)
4832{
86fa6981 4833 if (i.vec_encoding == vex_encoding_evex)
43234a1e 4834 {
86fa6981
L		 4835 /* This instruction must be encoded with EVEX prefix. */
4836 if (!t->opcode_modifier.evex)
4837 {
4838 i.error = unsupported;
4839 return 1;
4840 }
4841 return 0;
43234a1e
L		 4842 }
4843
a683cc34 4844 if (!t->opcode_modifier.vex)
86fa6981
L		 4845 {
4846 /* This instruction template doesn't have VEX prefix. */
4847 if (i.vec_encoding != vex_encoding_default)
4848 {
4849 i.error = unsupported;
4850 return 1;
4851 }
4852 return 0;
4853 }
a683cc34
SP		 4854
4855 /* Only check VEX_Imm4, which must be the first operand. */
4856 if (t->operand_types[0].bitfield.vec_imm4)
4857 {
4858 if (i.op[0].imms->X_op != O_constant
4859 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4860 {
a65babc9 4861 i.error = bad_imm4;
891edac4
L		 4862 return 1;
4863 }
a683cc34
SP		 4864
4865 /* Turn off Imm8 so that update_imm won't complain. */
4866 i.types[0] = vec_imm4;
4867 }
4868
4869 return 0;
4870}
4871
d3ce72d0 4872static const insn_template *
83b16ac6 4873match_template (char mnem_suffix)
29b0f896
AM		 4874{
4875 /* Points to template once we've found it. */
d3ce72d0 4876 const insn_template *t;
40fb9820 4877 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4878 i386_operand_type overlap4;
29b0f896 4879 unsigned int found_reverse_match;
83b16ac6 4880 i386_opcode_modifier suffix_check, mnemsuf_check;
40fb9820 4881 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4882 int addr_prefix_disp;
a5c311ca 4883 unsigned int j;
3629bb00 4884 unsigned int found_cpu_match;
45664ddb 4885 unsigned int check_register;
5614d22c 4886 enum i386_error specific_error = 0;
29b0f896 4887
c0f3af97
L		 4888#if MAX_OPERANDS != 5
4889# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4890#endif
4891
29b0f896 4892 found_reverse_match = 0;
539e75ad 4893 addr_prefix_disp = -1;
40fb9820
L		 4894
4895 memset (&suffix_check, 0, sizeof (suffix_check));
4896 if (i.suffix == BYTE_MNEM_SUFFIX)
4897 suffix_check.no_bsuf = 1;
4898 else if (i.suffix == WORD_MNEM_SUFFIX)
4899 suffix_check.no_wsuf = 1;
4900 else if (i.suffix == SHORT_MNEM_SUFFIX)
4901 suffix_check.no_ssuf = 1;
4902 else if (i.suffix == LONG_MNEM_SUFFIX)
4903 suffix_check.no_lsuf = 1;
4904 else if (i.suffix == QWORD_MNEM_SUFFIX)
4905 suffix_check.no_qsuf = 1;
4906 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4907 suffix_check.no_ldsuf = 1;
29b0f896 4908
83b16ac6
JB		 4909 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
4910 if (intel_syntax)
4911 {
4912 switch (mnem_suffix)
4913 {
4914 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
4915 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
4916 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
4917 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
4918 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
4919 }
4920 }
4921
01559ecc
L		 4922 /* Must have right number of operands. */
4923 i.error = number_of_operands_mismatch;
4924
45aa61fe 4925 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4926 {
539e75ad
L		 4927 addr_prefix_disp = -1;
4928
29b0f896
AM		 4929 if (i.operands != t->operands)
4930 continue;
4931
50aecf8c 4932 /* Check processor support. */
a65babc9 4933 i.error = unsupported;
c0f3af97
L		 4934 found_cpu_match = (cpu_flags_match (t)
4935 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4936 if (!found_cpu_match)
4937 continue;
4938
e1d4d893 4939 /* Check old gcc support. */
a65babc9 4940 i.error = old_gcc_only;
e1d4d893
L		 4941 if (!old_gcc && t->opcode_modifier.oldgcc)
4942 continue;
4943
4944 /* Check AT&T mnemonic. */
a65babc9 4945 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4946 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4947 continue;
4948
e92bae62 4949 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
a65babc9 4950 i.error = unsupported_syntax;
5c07affc 4951 if ((intel_syntax && t->opcode_modifier.attsyntax)
e92bae62
L		 4952 || (!intel_syntax && t->opcode_modifier.intelsyntax)
4953 || (intel64 && t->opcode_modifier.amd64)
4954 || (!intel64 && t->opcode_modifier.intel64))
1efbbeb4
L		 4955 continue;
4956
20592a94 4957 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4958 i.error = invalid_instruction_suffix;
567e4e96
L		 4959 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4960 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4961 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4962 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4963 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4964 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4965 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896 4966 continue;
83b16ac6
JB		 4967 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4968 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
4969 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
4970 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
4971 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
4972 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
4973 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
4974 continue;
29b0f896 4975
5c07affc 4976 if (!operand_size_match (t))
7d5e4556 4977 continue;
539e75ad 4978
5c07affc
L		 4979 for (j = 0; j < MAX_OPERANDS; j++)
4980 operand_types[j] = t->operand_types[j];
4981
45aa61fe
AM		 4982 /* In general, don't allow 64-bit operands in 32-bit mode. */
4983 if (i.suffix == QWORD_MNEM_SUFFIX
4984 && flag_code != CODE_64BIT
4985 && (intel_syntax
40fb9820 4986 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4987 && !intel_float_operand (t->name))
4988 : intel_float_operand (t->name) != 2)
40fb9820 4989 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4990 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4991 && !operand_types[0].bitfield.regymm
4992 && !operand_types[0].bitfield.regzmm)
40fb9820 4993 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4994 && operand_types[t->operands > 1].bitfield.regxmm
4995 && operand_types[t->operands > 1].bitfield.regymm
4996 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4997 && (t->base_opcode != 0x0fc7
4998 || t->extension_opcode != 1 /* cmpxchg8b */))
4999 continue;
5000
192dc9c6
JB		 5001 /* In general, don't allow 32-bit operands on pre-386. */
5002 else if (i.suffix == LONG_MNEM_SUFFIX
5003 && !cpu_arch_flags.bitfield.cpui386
5004 && (intel_syntax
5005 ? (!t->opcode_modifier.ignoresize
5006 && !intel_float_operand (t->name))
5007 : intel_float_operand (t->name) != 2)
5008 && ((!operand_types[0].bitfield.regmmx
5009 && !operand_types[0].bitfield.regxmm)
5010 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 5011 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 5012 continue;
5013
29b0f896 5014 /* Do not verify operands when there are none. */
50aecf8c 5015 else
29b0f896 5016 {
c6fb90c8 5017 if (!t->operands)
2dbab7d5
L		 5018 /* We've found a match; break out of loop. */
5019 break;
29b0f896 5020 }
252b5132 5021
539e75ad
L		 5022 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5023 into Disp32/Disp16/Disp32 operand. */
5024 if (i.prefix[ADDR_PREFIX] != 0)
5025 {
40fb9820 5026 /* There should be only one Disp operand. */
539e75ad
L		 5027 switch (flag_code)
5028 {
5029 case CODE_16BIT:
40fb9820
L		 5030 for (j = 0; j < MAX_OPERANDS; j++)
5031 {
5032 if (operand_types[j].bitfield.disp16)
5033 {
5034 addr_prefix_disp = j;
5035 operand_types[j].bitfield.disp32 = 1;
5036 operand_types[j].bitfield.disp16 = 0;
5037 break;
5038 }
5039 }
539e75ad
L		 5040 break;
5041 case CODE_32BIT:
40fb9820
L		 5042 for (j = 0; j < MAX_OPERANDS; j++)
5043 {
5044 if (operand_types[j].bitfield.disp32)
5045 {
5046 addr_prefix_disp = j;
5047 operand_types[j].bitfield.disp32 = 0;
5048 operand_types[j].bitfield.disp16 = 1;
5049 break;
5050 }
5051 }
539e75ad
L		 5052 break;
5053 case CODE_64BIT:
40fb9820
L		 5054 for (j = 0; j < MAX_OPERANDS; j++)
5055 {
5056 if (operand_types[j].bitfield.disp64)
5057 {
5058 addr_prefix_disp = j;
5059 operand_types[j].bitfield.disp64 = 0;
5060 operand_types[j].bitfield.disp32 = 1;
5061 break;
5062 }
5063 }
539e75ad
L		 5064 break;
5065 }
539e75ad
L		 5066 }
5067
02a86693
L		 5068 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5069 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5070 continue;
5071
56ffb741
L		 5072 /* We check register size if needed. */
5073 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 5074 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 5075 switch (t->operands)
5076 {
5077 case 1:
40fb9820 5078 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 5079 continue;
5080 break;
5081 case 2:
33eaf5de 5082 /* xchg %eax, %eax is a special case. It is an alias for nop
8b38ad71
L		 5083 only in 32bit mode and we can use opcode 0x90. In 64bit
5084 mode, we can't use 0x90 for xchg %eax, %eax since it should
5085 zero-extend %eax to %rax. */
5086 if (flag_code == CODE_64BIT
5087 && t->base_opcode == 0x90
0dfbf9d7
L		 5088 && operand_type_equal (&i.types [0], &acc32)
5089 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 5090 continue;
86fa6981
L		 5091 /* If we want store form, we reverse direction of operands. */
5092 if (i.dir_encoding == dir_encoding_store
5093 && t->opcode_modifier.d)
5094 goto check_reverse;
1a0670f3 5095 /* Fall through. */
b6169b20 5096
29b0f896 5097 case 3:
86fa6981
L		 5098 /* If we want store form, we skip the current load. */
5099 if (i.dir_encoding == dir_encoding_store
5100 && i.mem_operands == 0
5101 && t->opcode_modifier.load)
fa99fab2 5102 continue;
1a0670f3 5103 /* Fall through. */
f48ff2ae 5104 case 4:
c0f3af97 5105 case 5:
c6fb90c8 5106 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 5107 if (!operand_type_match (overlap0, i.types[0])
5108 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 5109 || (check_register
5110 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 5111 operand_types[0],
5112 overlap1, i.types[1],
5113 operand_types[1])))
29b0f896
AM		 5114 {
5115 /* Check if other direction is valid ... */
40fb9820 5116 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 5117 continue;
5118
b6169b20 5119check_reverse:
29b0f896 5120 /* Try reversing direction of operands. */
c6fb90c8
L		 5121 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5122 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 5123 if (!operand_type_match (overlap0, i.types[0])
5124 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 5125 || (check_register
5126 && !operand_type_register_match (overlap0,
5127 i.types[0],
5128 operand_types[1],
5129 overlap1,
5130 i.types[1],
5131 operand_types[0])))
29b0f896
AM		 5132 {
5133 /* Does not match either direction. */
5134 continue;
5135 }
5136 /* found_reverse_match holds which of D or FloatDR
5137 we've found. */
40fb9820 5138 if (t->opcode_modifier.d)
8a2ed489 5139 found_reverse_match = Opcode_D;
40fb9820 5140 else if (t->opcode_modifier.floatd)
8a2ed489
L		 5141 found_reverse_match = Opcode_FloatD;
5142 else
5143 found_reverse_match = 0;
40fb9820 5144 if (t->opcode_modifier.floatr)
8a2ed489 5145 found_reverse_match |= Opcode_FloatR;
29b0f896 5146 }
f48ff2ae 5147 else
29b0f896 5148 {
f48ff2ae 5149 /* Found a forward 2 operand match here. */
d1cbb4db
L		 5150 switch (t->operands)
5151 {
c0f3af97
L		 5152 case 5:
5153 overlap4 = operand_type_and (i.types[4],
5154 operand_types[4]);
1a0670f3 5155 /* Fall through. */
d1cbb4db 5156 case 4:
c6fb90c8
L		 5157 overlap3 = operand_type_and (i.types[3],
5158 operand_types[3]);
1a0670f3 5159 /* Fall through. */
d1cbb4db 5160 case 3:
c6fb90c8
L		 5161 overlap2 = operand_type_and (i.types[2],
5162 operand_types[2]);
d1cbb4db
L		 5163 break;
5164 }
29b0f896 5165
f48ff2ae
L		 5166 switch (t->operands)
5167 {
c0f3af97
L		 5168 case 5:
5169 if (!operand_type_match (overlap4, i.types[4])
5170 || !operand_type_register_match (overlap3,
5171 i.types[3],
5172 operand_types[3],
5173 overlap4,
5174 i.types[4],
5175 operand_types[4]))
5176 continue;
1a0670f3 5177 /* Fall through. */
f48ff2ae 5178 case 4:
40fb9820 5179 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 5180 || (check_register
5181 && !operand_type_register_match (overlap2,
5182 i.types[2],
5183 operand_types[2],
5184 overlap3,
5185 i.types[3],
5186 operand_types[3])))
f48ff2ae 5187 continue;
1a0670f3 5188 /* Fall through. */
f48ff2ae
L		 5189 case 3:
5190 /* Here we make use of the fact that there are no
5191 reverse match 3 operand instructions, and all 3
5192 operand instructions only need to be checked for
5193 register consistency between operands 2 and 3. */
40fb9820 5194 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 5195 || (check_register
5196 && !operand_type_register_match (overlap1,
5197 i.types[1],
5198 operand_types[1],
5199 overlap2,
5200 i.types[2],
5201 operand_types[2])))
f48ff2ae
L		 5202 continue;
5203 break;
5204 }
29b0f896 5205 }
f48ff2ae 5206 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5207 slip through to break. */
5208 }
3629bb00 5209 if (!found_cpu_match)
29b0f896
AM		 5210 {
5211 found_reverse_match = 0;
5212 continue;
5213 }
c0f3af97 5214
5614d22c
JB		 5215 /* Check if vector and VEX operands are valid. */
5216 if (check_VecOperands (t) || VEX_check_operands (t))
5217 {
5218 specific_error = i.error;
5219 continue;
5220 }
a683cc34 5221
29b0f896
AM		 5222 /* We've found a match; break out of loop. */
5223 break;
5224 }
5225
5226 if (t == current_templates->end)
5227 {
5228 /* We found no match. */
a65babc9 5229 const char *err_msg;
5614d22c 5230 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5231 {
5232 default:
5233 abort ();
86e026a4 5234 case operand_size_mismatch:
a65babc9
L		 5235 err_msg = _("operand size mismatch");
5236 break;
5237 case operand_type_mismatch:
5238 err_msg = _("operand type mismatch");
5239 break;
5240 case register_type_mismatch:
5241 err_msg = _("register type mismatch");
5242 break;
5243 case number_of_operands_mismatch:
5244 err_msg = _("number of operands mismatch");
5245 break;
5246 case invalid_instruction_suffix:
5247 err_msg = _("invalid instruction suffix");
5248 break;
5249 case bad_imm4:
4a2608e3 5250 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 5251 break;
5252 case old_gcc_only:
5253 err_msg = _("only supported with old gcc");
5254 break;
5255 case unsupported_with_intel_mnemonic:
5256 err_msg = _("unsupported with Intel mnemonic");
5257 break;
5258 case unsupported_syntax:
5259 err_msg = _("unsupported syntax");
5260 break;
5261 case unsupported:
35262a23 5262 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5263 current_templates->start->name);
5264 return NULL;
6c30d220
L		 5265 case invalid_vsib_address:
5266 err_msg = _("invalid VSIB address");
5267 break;
7bab8ab5
JB		 5268 case invalid_vector_register_set:
5269 err_msg = _("mask, index, and destination registers must be distinct");
5270 break;
6c30d220
L		 5271 case unsupported_vector_index_register:
5272 err_msg = _("unsupported vector index register");
5273 break;
43234a1e
L		 5274 case unsupported_broadcast:
5275 err_msg = _("unsupported broadcast");
5276 break;
5277 case broadcast_not_on_src_operand:
5278 err_msg = _("broadcast not on source memory operand");
5279 break;
5280 case broadcast_needed:
5281 err_msg = _("broadcast is needed for operand of such type");
5282 break;
5283 case unsupported_masking:
5284 err_msg = _("unsupported masking");
5285 break;
5286 case mask_not_on_destination:
5287 err_msg = _("mask not on destination operand");
5288 break;
5289 case no_default_mask:
5290 err_msg = _("default mask isn't allowed");
5291 break;
5292 case unsupported_rc_sae:
5293 err_msg = _("unsupported static rounding/sae");
5294 break;
5295 case rc_sae_operand_not_last_imm:
5296 if (intel_syntax)
5297 err_msg = _("RC/SAE operand must precede immediate operands");
5298 else
5299 err_msg = _("RC/SAE operand must follow immediate operands");
5300 break;
5301 case invalid_register_operand:
5302 err_msg = _("invalid register operand");
5303 break;
a65babc9
L		 5304 }
5305 as_bad (_("%s for `%s'"), err_msg,
891edac4 5306 current_templates->start->name);
fa99fab2 5307 return NULL;
29b0f896 5308 }
252b5132 5309
29b0f896
AM		 5310 if (!quiet_warnings)
5311 {
5312 if (!intel_syntax
40fb9820
L		 5313 && (i.types[0].bitfield.jumpabsolute
5314 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5315 {
5316 as_warn (_("indirect %s without `*'"), t->name);
5317 }
5318
40fb9820
L		 5319 if (t->opcode_modifier.isprefix
5320 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5321 {
5322 /* Warn them that a data or address size prefix doesn't
5323 affect assembly of the next line of code. */
5324 as_warn (_("stand-alone `%s' prefix"), t->name);
5325 }
5326 }
5327
5328 /* Copy the template we found. */
5329 i.tm = *t;
539e75ad
L		 5330
5331 if (addr_prefix_disp != -1)
5332 i.tm.operand_types[addr_prefix_disp]
5333 = operand_types[addr_prefix_disp];
5334
29b0f896
AM		 5335 if (found_reverse_match)
5336 {
5337 /* If we found a reverse match we must alter the opcode
5338 direction bit. found_reverse_match holds bits to change
5339 (different for int & float insns). */
5340
5341 i.tm.base_opcode ^= found_reverse_match;
5342
539e75ad
L		 5343 i.tm.operand_types[0] = operand_types[1];
5344 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5345 }
5346
fa99fab2 5347 return t;
29b0f896
AM		 5348}
5349
5350static int
e3bb37b5 5351check_string (void)
29b0f896 5352{
40fb9820
L		 5353 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5354 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5355 {
5356 if (i.seg[0] != NULL && i.seg[0] != &es)
5357 {
a87af027 5358 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5359 i.tm.name,
a87af027
JB		 5360 mem_op + 1,
5361 register_prefix);
29b0f896
AM		 5362 return 0;
5363 }
5364 /* There's only ever one segment override allowed per instruction.
5365 This instruction possibly has a legal segment override on the
5366 second operand, so copy the segment to where non-string
5367 instructions store it, allowing common code. */
5368 i.seg[0] = i.seg[1];
5369 }
40fb9820 5370 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5371 {
5372 if (i.seg[1] != NULL && i.seg[1] != &es)
5373 {
a87af027 5374 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5375 i.tm.name,
a87af027
JB		 5376 mem_op + 2,
5377 register_prefix);
29b0f896
AM		 5378 return 0;
5379 }
5380 }
5381 return 1;
5382}
5383
5384static int
543613e9 5385process_suffix (void)
29b0f896
AM		 5386{
5387 /* If matched instruction specifies an explicit instruction mnemonic
5388 suffix, use it. */
40fb9820
L		 5389 if (i.tm.opcode_modifier.size16)
5390 i.suffix = WORD_MNEM_SUFFIX;
5391 else if (i.tm.opcode_modifier.size32)
5392 i.suffix = LONG_MNEM_SUFFIX;
5393 else if (i.tm.opcode_modifier.size64)
5394 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5395 else if (i.reg_operands)
5396 {
5397 /* If there's no instruction mnemonic suffix we try to invent one
5398 based on register operands. */
5399 if (!i.suffix)
5400 {
5401 /* We take i.suffix from the last register operand specified,
5402 Destination register type is more significant than source
381d071f
L		 5403 register type. crc32 in SSE4.2 prefers source register
5404 type. */
5405 if (i.tm.base_opcode == 0xf20f38f1)
5406 {
40fb9820
L		 5407 if (i.types[0].bitfield.reg16)
5408 i.suffix = WORD_MNEM_SUFFIX;
5409 else if (i.types[0].bitfield.reg32)
5410 i.suffix = LONG_MNEM_SUFFIX;
5411 else if (i.types[0].bitfield.reg64)
5412 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5413 }
9344ff29 5414 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5415 {
40fb9820 5416 if (i.types[0].bitfield.reg8)
20592a94
L		 5417 i.suffix = BYTE_MNEM_SUFFIX;
5418 }
381d071f
L		 5419
5420 if (!i.suffix)
5421 {
5422 int op;
5423
20592a94
L		 5424 if (i.tm.base_opcode == 0xf20f38f1
5425 || i.tm.base_opcode == 0xf20f38f0)
5426 {
5427 /* We have to know the operand size for crc32. */
5428 as_bad (_("ambiguous memory operand size for `%s`"),
5429 i.tm.name);
5430 return 0;
5431 }
5432
381d071f 5433 for (op = i.operands; --op >= 0;)
40fb9820 5434 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5435 {
40fb9820
L		 5436 if (i.types[op].bitfield.reg8)
5437 {
5438 i.suffix = BYTE_MNEM_SUFFIX;
5439 break;
5440 }
5441 else if (i.types[op].bitfield.reg16)
5442 {
5443 i.suffix = WORD_MNEM_SUFFIX;
5444 break;
5445 }
5446 else if (i.types[op].bitfield.reg32)
5447 {
5448 i.suffix = LONG_MNEM_SUFFIX;
5449 break;
5450 }
5451 else if (i.types[op].bitfield.reg64)
5452 {
5453 i.suffix = QWORD_MNEM_SUFFIX;
5454 break;
5455 }
381d071f
L		 5456 }
5457 }
29b0f896
AM		 5458 }
5459 else if (i.suffix == BYTE_MNEM_SUFFIX)
5460 {
2eb952a4
L		 5461 if (intel_syntax
5462 && i.tm.opcode_modifier.ignoresize
5463 && i.tm.opcode_modifier.no_bsuf)
5464 i.suffix = 0;
5465 else if (!check_byte_reg ())
29b0f896
AM		 5466 return 0;
5467 }
5468 else if (i.suffix == LONG_MNEM_SUFFIX)
5469 {
2eb952a4
L		 5470 if (intel_syntax
5471 && i.tm.opcode_modifier.ignoresize
5472 && i.tm.opcode_modifier.no_lsuf)
5473 i.suffix = 0;
5474 else if (!check_long_reg ())
29b0f896
AM		 5475 return 0;
5476 }
5477 else if (i.suffix == QWORD_MNEM_SUFFIX)
5478 {
955e1e6a
L		 5479 if (intel_syntax
5480 && i.tm.opcode_modifier.ignoresize
5481 && i.tm.opcode_modifier.no_qsuf)
5482 i.suffix = 0;
5483 else if (!check_qword_reg ())
29b0f896
AM		 5484 return 0;
5485 }
5486 else if (i.suffix == WORD_MNEM_SUFFIX)
5487 {
2eb952a4
L		 5488 if (intel_syntax
5489 && i.tm.opcode_modifier.ignoresize
5490 && i.tm.opcode_modifier.no_wsuf)
5491 i.suffix = 0;
5492 else if (!check_word_reg ())
29b0f896
AM		 5493 return 0;
5494 }
c0f3af97 5495 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5496 || i.suffix == YMMWORD_MNEM_SUFFIX
5497 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5498 {
43234a1e 5499 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5500 should check if it is a valid suffix. */
5501 }
40fb9820 5502 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5503 /* Do nothing if the instruction is going to ignore the prefix. */
5504 ;
5505 else
5506 abort ();
5507 }
40fb9820 5508 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5509 && !i.suffix
5510 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5511 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5512 {
5513 i.suffix = stackop_size;
5514 }
9306ca4a
JB		 5515 else if (intel_syntax
5516 && !i.suffix
40fb9820
L		 5517 && (i.tm.operand_types[0].bitfield.jumpabsolute
5518 || i.tm.opcode_modifier.jumpbyte
5519 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5520 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5521 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5522 {
5523 switch (flag_code)
5524 {
5525 case CODE_64BIT:
40fb9820 5526 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5527 {
5528 i.suffix = QWORD_MNEM_SUFFIX;
5529 break;
5530 }
1a0670f3 5531 /* Fall through. */
9306ca4a 5532 case CODE_32BIT:
40fb9820 5533 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5534 i.suffix = LONG_MNEM_SUFFIX;
5535 break;
5536 case CODE_16BIT:
40fb9820 5537 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5538 i.suffix = WORD_MNEM_SUFFIX;
5539 break;
5540 }
5541 }
252b5132 5542
9306ca4a 5543 if (!i.suffix)
29b0f896 5544 {
9306ca4a
JB		 5545 if (!intel_syntax)
5546 {
40fb9820 5547 if (i.tm.opcode_modifier.w)
9306ca4a 5548 {
4eed87de
AM		 5549 as_bad (_("no instruction mnemonic suffix given and "
5550 "no register operands; can't size instruction"));
9306ca4a
JB		 5551 return 0;
5552 }
5553 }
5554 else
5555 {
40fb9820 5556 unsigned int suffixes;
7ab9ffdd 5557
40fb9820
L		 5558 suffixes = !i.tm.opcode_modifier.no_bsuf;
5559 if (!i.tm.opcode_modifier.no_wsuf)
5560 suffixes |= 1 << 1;
5561 if (!i.tm.opcode_modifier.no_lsuf)
5562 suffixes |= 1 << 2;
fc4adea1 5563 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5564 suffixes |= 1 << 3;
5565 if (!i.tm.opcode_modifier.no_ssuf)
5566 suffixes |= 1 << 4;
5567 if (!i.tm.opcode_modifier.no_qsuf)
5568 suffixes |= 1 << 5;
5569
5570 /* There are more than suffix matches. */
5571 if (i.tm.opcode_modifier.w
9306ca4a 5572 || ((suffixes & (suffixes - 1))
40fb9820
L		 5573 && !i.tm.opcode_modifier.defaultsize
5574 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5575 {
5576 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5577 return 0;
5578 }
5579 }
29b0f896 5580 }
252b5132 5581
9306ca4a
JB		 5582 /* Change the opcode based on the operand size given by i.suffix;
5583 We don't need to change things for byte insns. */
5584
582d5edd
L		 5585 if (i.suffix
5586 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5587 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5588 && i.suffix != YMMWORD_MNEM_SUFFIX
5589 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5590 {
5591 /* It's not a byte, select word/dword operation. */
40fb9820 5592 if (i.tm.opcode_modifier.w)
29b0f896 5593 {
40fb9820 5594 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5595 i.tm.base_opcode |= 8;
5596 else
5597 i.tm.base_opcode |= 1;
5598 }
0f3f3d8b 5599
29b0f896
AM		 5600 /* Now select between word & dword operations via the operand
5601 size prefix, except for instructions that will ignore this
5602 prefix anyway. */
ca61edf2 5603 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5604 {
ca61edf2
L		 5605 /* The address size override prefix changes the size of the
5606 first operand. */
40fb9820
L		 5607 if ((flag_code == CODE_32BIT
5608 && i.op->regs[0].reg_type.bitfield.reg16)
5609 || (flag_code != CODE_32BIT
5610 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5611 if (!add_prefix (ADDR_PREFIX_OPCODE))
5612 return 0;
5613 }
5614 else if (i.suffix != QWORD_MNEM_SUFFIX
5615 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5616 && !i.tm.opcode_modifier.ignoresize
5617 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5618 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5619 || (flag_code == CODE_64BIT
40fb9820 5620 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5621 {
5622 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5623
40fb9820 5624 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5625 prefix = ADDR_PREFIX_OPCODE;
252b5132 5626
29b0f896
AM		 5627 if (!add_prefix (prefix))
5628 return 0;
24eab124 5629 }
252b5132 5630
29b0f896
AM		 5631 /* Set mode64 for an operand. */
5632 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5633 && flag_code == CODE_64BIT
40fb9820 5634 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5635 {
5636 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5637 need rex64. cmpxchg8b is also a special case. */
5638 if (! (i.operands == 2
5639 && i.tm.base_opcode == 0x90
5640 && i.tm.extension_opcode == None
0dfbf9d7
L		 5641 && operand_type_equal (&i.types [0], &acc64)
5642 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5643 && ! (i.operands == 1
5644 && i.tm.base_opcode == 0xfc7
5645 && i.tm.extension_opcode == 1
40fb9820
L		 5646 && !operand_type_check (i.types [0], reg)
5647 && operand_type_check (i.types [0], anymem)))
f6bee062 5648 i.rex |= REX_W;
46e883c5 5649 }
3e73aa7c 5650
29b0f896
AM		 5651 /* Size floating point instruction. */
5652 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5653 if (i.tm.opcode_modifier.floatmf)
543613e9 5654 i.tm.base_opcode ^= 4;
29b0f896 5655 }
7ecd2f8b 5656
29b0f896
AM		 5657 return 1;
5658}
3e73aa7c 5659
29b0f896 5660static int
543613e9 5661check_byte_reg (void)
29b0f896
AM		 5662{
5663 int op;
543613e9 5664
29b0f896
AM		 5665 for (op = i.operands; --op >= 0;)
5666 {
5667 /* If this is an eight bit register, it's OK. If it's the 16 or
5668 32 bit version of an eight bit register, we will just use the
5669 low portion, and that's OK too. */
40fb9820 5670 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5671 continue;
5672
5a819eb9
JB		 5673 /* I/O port address operands are OK too. */
5674 if (i.tm.operand_types[op].bitfield.inoutportreg)
5675 continue;
5676
9344ff29
L		 5677 /* crc32 doesn't generate this warning. */
5678 if (i.tm.base_opcode == 0xf20f38f0)
5679 continue;
5680
40fb9820
L		 5681 if ((i.types[op].bitfield.reg16
5682 || i.types[op].bitfield.reg32
5683 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5684 && i.op[op].regs->reg_num < 4
5685 /* Prohibit these changes in 64bit mode, since the lowering
5686 would be more complicated. */
5687 && flag_code != CODE_64BIT)
29b0f896 5688 {
29b0f896 5689#if REGISTER_WARNINGS
5a819eb9 5690 if (!quiet_warnings)
a540244d
L		 5691 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5692 register_prefix,
40fb9820 5693 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5694 ? REGNAM_AL - REGNAM_AX
5695 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5696 register_prefix,
29b0f896
AM		 5697 i.op[op].regs->reg_name,
5698 i.suffix);
5699#endif
5700 continue;
5701 }
5702 /* Any other register is bad. */
40fb9820
L		 5703 if (i.types[op].bitfield.reg16
5704 || i.types[op].bitfield.reg32
5705 || i.types[op].bitfield.reg64
5706 || i.types[op].bitfield.regmmx
5707 || i.types[op].bitfield.regxmm
c0f3af97 5708 || i.types[op].bitfield.regymm
43234a1e 5709 || i.types[op].bitfield.regzmm
40fb9820
L		 5710 || i.types[op].bitfield.sreg2
5711 || i.types[op].bitfield.sreg3
5712 || i.types[op].bitfield.control
5713 || i.types[op].bitfield.debug
5714 || i.types[op].bitfield.test
5715 || i.types[op].bitfield.floatreg
5716 || i.types[op].bitfield.floatacc)
29b0f896 5717 {
a540244d
L		 5718 as_bad (_("`%s%s' not allowed with `%s%c'"),
5719 register_prefix,
29b0f896
AM		 5720 i.op[op].regs->reg_name,
5721 i.tm.name,
5722 i.suffix);
5723 return 0;
5724 }
5725 }
5726 return 1;
5727}
5728
5729static int
e3bb37b5 5730check_long_reg (void)
29b0f896
AM		 5731{
5732 int op;
5733
5734 for (op = i.operands; --op >= 0;)
5735 /* Reject eight bit registers, except where the template requires
5736 them. (eg. movzb) */
40fb9820
L		 5737 if (i.types[op].bitfield.reg8
5738 && (i.tm.operand_types[op].bitfield.reg16
5739 || i.tm.operand_types[op].bitfield.reg32
5740 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5741 {
a540244d
L		 5742 as_bad (_("`%s%s' not allowed with `%s%c'"),
5743 register_prefix,
29b0f896
AM		 5744 i.op[op].regs->reg_name,
5745 i.tm.name,
5746 i.suffix);
5747 return 0;
5748 }
e4630f71 5749 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5750 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5751 && i.types[op].bitfield.reg16
5752 && (i.tm.operand_types[op].bitfield.reg32
5753 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5754 {
5755 /* Prohibit these changes in the 64bit mode, since the
5756 lowering is more complicated. */
5757 if (flag_code == CODE_64BIT)
252b5132 5758 {
2b5d6a91 5759 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5760 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5761 i.suffix);
5762 return 0;
252b5132 5763 }
29b0f896 5764#if REGISTER_WARNINGS
cecf1424
JB		 5765 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5766 register_prefix,
5767 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5768 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5769#endif
252b5132 5770 }
e4630f71 5771 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5772 else if (i.types[op].bitfield.reg64
5773 && (i.tm.operand_types[op].bitfield.reg32
5774 || i.tm.operand_types[op].bitfield.acc))
252b5132 5775 {
34828aad 5776 if (intel_syntax
ca61edf2 5777 && i.tm.opcode_modifier.toqword
40fb9820 5778 && !i.types[0].bitfield.regxmm)
34828aad 5779 {
ca61edf2 5780 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5781 i.suffix = QWORD_MNEM_SUFFIX;
5782 }
5783 else
5784 {
2b5d6a91 5785 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5786 register_prefix, i.op[op].regs->reg_name,
5787 i.suffix);
5788 return 0;
5789 }
29b0f896
AM		 5790 }
5791 return 1;
5792}
252b5132 5793
29b0f896 5794static int
e3bb37b5 5795check_qword_reg (void)
29b0f896
AM		 5796{
5797 int op;
252b5132 5798
29b0f896
AM		 5799 for (op = i.operands; --op >= 0; )
5800 /* Reject eight bit registers, except where the template requires
5801 them. (eg. movzb) */
40fb9820
L		 5802 if (i.types[op].bitfield.reg8
5803 && (i.tm.operand_types[op].bitfield.reg16
5804 || i.tm.operand_types[op].bitfield.reg32
5805 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5806 {
a540244d
L		 5807 as_bad (_("`%s%s' not allowed with `%s%c'"),
5808 register_prefix,
29b0f896
AM		 5809 i.op[op].regs->reg_name,
5810 i.tm.name,
5811 i.suffix);
5812 return 0;
5813 }
e4630f71 5814 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5815 else if ((i.types[op].bitfield.reg16
5816 || i.types[op].bitfield.reg32)
33d0ab95 5817 && (i.tm.operand_types[op].bitfield.reg64
40fb9820 5818 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5819 {
5820 /* Prohibit these changes in the 64bit mode, since the
5821 lowering is more complicated. */
34828aad 5822 if (intel_syntax
ca61edf2 5823 && i.tm.opcode_modifier.todword
40fb9820 5824 && !i.types[0].bitfield.regxmm)
34828aad 5825 {
ca61edf2 5826 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5827 i.suffix = LONG_MNEM_SUFFIX;
5828 }
5829 else
5830 {
2b5d6a91 5831 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5832 register_prefix, i.op[op].regs->reg_name,
5833 i.suffix);
5834 return 0;
5835 }
252b5132 5836 }
29b0f896
AM		 5837 return 1;
5838}
252b5132 5839
29b0f896 5840static int
e3bb37b5 5841check_word_reg (void)
29b0f896
AM		 5842{
5843 int op;
5844 for (op = i.operands; --op >= 0;)
5845 /* Reject eight bit registers, except where the template requires
5846 them. (eg. movzb) */
40fb9820
L		 5847 if (i.types[op].bitfield.reg8
5848 && (i.tm.operand_types[op].bitfield.reg16
5849 || i.tm.operand_types[op].bitfield.reg32
5850 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5851 {
a540244d
L		 5852 as_bad (_("`%s%s' not allowed with `%s%c'"),
5853 register_prefix,
29b0f896
AM		 5854 i.op[op].regs->reg_name,
5855 i.tm.name,
5856 i.suffix);
5857 return 0;
5858 }
e4630f71 5859 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5860 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5861 && (i.types[op].bitfield.reg32
5862 || i.types[op].bitfield.reg64)
40fb9820
L		 5863 && (i.tm.operand_types[op].bitfield.reg16
5864 || i.tm.operand_types[op].bitfield.acc))
252b5132 5865 {
29b0f896
AM		 5866 /* Prohibit these changes in the 64bit mode, since the
5867 lowering is more complicated. */
5868 if (flag_code == CODE_64BIT)
252b5132 5869 {
2b5d6a91 5870 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5871 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5872 i.suffix);
5873 return 0;
252b5132 5874 }
29b0f896 5875#if REGISTER_WARNINGS
cecf1424
JB		 5876 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5877 register_prefix,
5878 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5879 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5880#endif
5881 }
5882 return 1;
5883}
252b5132 5884
29b0f896 5885static int
40fb9820 5886update_imm (unsigned int j)
29b0f896 5887{
bc0844ae 5888 i386_operand_type overlap = i.types[j];
40fb9820
L		 5889 if ((overlap.bitfield.imm8
5890 || overlap.bitfield.imm8s
5891 || overlap.bitfield.imm16
5892 || overlap.bitfield.imm32
5893 || overlap.bitfield.imm32s
5894 || overlap.bitfield.imm64)
0dfbf9d7
L		 5895 && !operand_type_equal (&overlap, &imm8)
5896 && !operand_type_equal (&overlap, &imm8s)
5897 && !operand_type_equal (&overlap, &imm16)
5898 && !operand_type_equal (&overlap, &imm32)
5899 && !operand_type_equal (&overlap, &imm32s)
5900 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5901 {
5902 if (i.suffix)
5903 {
40fb9820
L		 5904 i386_operand_type temp;
5905
0dfbf9d7 5906 operand_type_set (&temp, 0);
7ab9ffdd 5907 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5908 {
5909 temp.bitfield.imm8 = overlap.bitfield.imm8;
5910 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5911 }
5912 else if (i.suffix == WORD_MNEM_SUFFIX)
5913 temp.bitfield.imm16 = overlap.bitfield.imm16;
5914 else if (i.suffix == QWORD_MNEM_SUFFIX)
5915 {
5916 temp.bitfield.imm64 = overlap.bitfield.imm64;
5917 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5918 }
5919 else
5920 temp.bitfield.imm32 = overlap.bitfield.imm32;
5921 overlap = temp;
29b0f896 5922 }
0dfbf9d7
L		 5923 else if (operand_type_equal (&overlap, &imm16_32_32s)
5924 || operand_type_equal (&overlap, &imm16_32)
5925 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5926 {
40fb9820 5927 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5928 overlap = imm16;
40fb9820 5929 else
65da13b5 5930 overlap = imm32s;
29b0f896 5931 }
0dfbf9d7
L		 5932 if (!operand_type_equal (&overlap, &imm8)
5933 && !operand_type_equal (&overlap, &imm8s)
5934 && !operand_type_equal (&overlap, &imm16)
5935 && !operand_type_equal (&overlap, &imm32)
5936 && !operand_type_equal (&overlap, &imm32s)
5937 && !operand_type_equal (&overlap, &imm64))
29b0f896 5938 {
4eed87de
AM		 5939 as_bad (_("no instruction mnemonic suffix given; "
5940 "can't determine immediate size"));
29b0f896
AM		 5941 return 0;
5942 }
5943 }
40fb9820 5944 i.types[j] = overlap;
29b0f896 5945
40fb9820
L		 5946 return 1;
5947}
5948
5949static int
5950finalize_imm (void)
5951{
bc0844ae 5952 unsigned int j, n;
29b0f896 5953
bc0844ae
L		 5954 /* Update the first 2 immediate operands. */
5955 n = i.operands > 2 ? 2 : i.operands;
5956 if (n)
5957 {
5958 for (j = 0; j < n; j++)
5959 if (update_imm (j) == 0)
5960 return 0;
40fb9820 5961
bc0844ae
L		 5962 /* The 3rd operand can't be immediate operand. */
5963 gas_assert (operand_type_check (i.types[2], imm) == 0);
5964 }
29b0f896
AM		 5965
5966 return 1;
5967}
5968
c0f3af97
L		 5969static int
5970bad_implicit_operand (int xmm)
5971{
91d6fa6a
NC		 5972 const char *ireg = xmm ? "xmm0" : "ymm0";
5973
c0f3af97
L		 5974 if (intel_syntax)
5975 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5976 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5977 else
5978 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5979 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5980 return 0;
5981}
5982
29b0f896 5983static int
e3bb37b5 5984process_operands (void)
29b0f896
AM		 5985{
5986 /* Default segment register this instruction will use for memory
5987 accesses. 0 means unknown. This is only for optimizing out
5988 unnecessary segment overrides. */
5989 const seg_entry *default_seg = 0;
5990
2426c15f 5991 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5992 {
91d6fa6a
NC		 5993 unsigned int dupl = i.operands;
5994 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5995 unsigned int j;
5996
c0f3af97 5997 /* The destination must be an xmm register. */
9c2799c2 5998 gas_assert (i.reg_operands
91d6fa6a 5999 && MAX_OPERANDS > dupl
7ab9ffdd 6000 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 6001
6002 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 6003 {
c0f3af97 6004 /* The first operand is implicit and must be xmm0. */
9c2799c2 6005 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 6006 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 6007 return bad_implicit_operand (1);
6008
8cd7925b 6009 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 6010 {
6011 /* Keep xmm0 for instructions with VEX prefix and 3
6012 sources. */
6013 goto duplicate;
6014 }
e2ec9d29 6015 else
c0f3af97
L		 6016 {
6017 /* We remove the first xmm0 and keep the number of
6018 operands unchanged, which in fact duplicates the
6019 destination. */
6020 for (j = 1; j < i.operands; j++)
6021 {
6022 i.op[j - 1] = i.op[j];
6023 i.types[j - 1] = i.types[j];
6024 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6025 }
6026 }
6027 }
6028 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 6029 {
91d6fa6a 6030 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 6031 && (i.tm.opcode_modifier.vexsources
6032 == VEX3SOURCES));
c0f3af97
L		 6033
6034 /* Add the implicit xmm0 for instructions with VEX prefix
6035 and 3 sources. */
6036 for (j = i.operands; j > 0; j--)
6037 {
6038 i.op[j] = i.op[j - 1];
6039 i.types[j] = i.types[j - 1];
6040 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6041 }
6042 i.op[0].regs
6043 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 6044 i.types[0] = regxmm;
c0f3af97
L		 6045 i.tm.operand_types[0] = regxmm;
6046
6047 i.operands += 2;
6048 i.reg_operands += 2;
6049 i.tm.operands += 2;
6050
91d6fa6a 6051 dupl++;
c0f3af97 6052 dest++;
91d6fa6a
NC		 6053 i.op[dupl] = i.op[dest];
6054 i.types[dupl] = i.types[dest];
6055 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 6056 }
c0f3af97
L		 6057 else
6058 {
6059duplicate:
6060 i.operands++;
6061 i.reg_operands++;
6062 i.tm.operands++;
6063
91d6fa6a
NC		 6064 i.op[dupl] = i.op[dest];
6065 i.types[dupl] = i.types[dest];
6066 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 6067 }
6068
6069 if (i.tm.opcode_modifier.immext)
6070 process_immext ();
6071 }
6072 else if (i.tm.opcode_modifier.firstxmm0)
6073 {
6074 unsigned int j;
6075
43234a1e 6076 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 6077 gas_assert (i.reg_operands
7ab9ffdd 6078 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 6079 || operand_type_equal (&i.types[0], &regymm)
6080 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 6081 if (register_number (i.op[0].regs) != 0)
c0f3af97 6082 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 6083
6084 for (j = 1; j < i.operands; j++)
6085 {
6086 i.op[j - 1] = i.op[j];
6087 i.types[j - 1] = i.types[j];
6088
6089 /* We need to adjust fields in i.tm since they are used by
6090 build_modrm_byte. */
6091 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6092 }
6093
e2ec9d29
L		 6094 i.operands--;
6095 i.reg_operands--;
e2ec9d29
L		 6096 i.tm.operands--;
6097 }
920d2ddc
IT		 6098 else if (i.tm.opcode_modifier.implicitquadgroup)
6099 {
6100 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6101 gas_assert (i.operands >= 2
6102 && (operand_type_equal (&i.types[1], &regxmm)
6103 || operand_type_equal (&i.types[1], &regymm)
6104 || operand_type_equal (&i.types[1], &regzmm)));
6105 unsigned int regnum = register_number (i.op[1].regs);
6106 unsigned int first_reg_in_group = regnum & ~3;
6107 unsigned int last_reg_in_group = first_reg_in_group + 3;
6108 if (regnum != first_reg_in_group) {
6109 as_warn (_("the second source register `%s%s' implicitly denotes"
6110 " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"),
6111 register_prefix, i.op[1].regs->reg_name,
6112 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6113 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6114 i.tm.name);
6115 }
6116 }
e2ec9d29
L		 6117 else if (i.tm.opcode_modifier.regkludge)
6118 {
6119 /* The imul $imm, %reg instruction is converted into
6120 imul $imm, %reg, %reg, and the clr %reg instruction
6121 is converted into xor %reg, %reg. */
6122
6123 unsigned int first_reg_op;
6124
6125 if (operand_type_check (i.types[0], reg))
6126 first_reg_op = 0;
6127 else
6128 first_reg_op = 1;
6129 /* Pretend we saw the extra register operand. */
9c2799c2 6130 gas_assert (i.reg_operands == 1
7ab9ffdd 6131 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 6132 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6133 i.types[first_reg_op + 1] = i.types[first_reg_op];
6134 i.operands++;
6135 i.reg_operands++;
29b0f896
AM		 6136 }
6137
40fb9820 6138 if (i.tm.opcode_modifier.shortform)
29b0f896 6139 {
40fb9820
L		 6140 if (i.types[0].bitfield.sreg2
6141 || i.types[0].bitfield.sreg3)
29b0f896 6142 {
4eed87de
AM		 6143 if (i.tm.base_opcode == POP_SEG_SHORT
6144 && i.op[0].regs->reg_num == 1)
29b0f896 6145 {
a87af027 6146 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 6147 return 0;
29b0f896 6148 }
4eed87de
AM		 6149 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6150 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 6151 i.rex |= REX_B;
4eed87de
AM		 6152 }
6153 else
6154 {
7ab9ffdd 6155 /* The register or float register operand is in operand
85f10a01 6156 0 or 1. */
40fb9820 6157 unsigned int op;
7ab9ffdd
L		 6158
6159 if (i.types[0].bitfield.floatreg
6160 || operand_type_check (i.types[0], reg))
6161 op = 0;
6162 else
6163 op = 1;
4eed87de
AM		 6164 /* Register goes in low 3 bits of opcode. */
6165 i.tm.base_opcode |= i.op[op].regs->reg_num;
6166 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 6167 i.rex |= REX_B;
40fb9820 6168 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 6169 {
4eed87de
AM		 6170 /* Warn about some common errors, but press on regardless.
6171 The first case can be generated by gcc (<= 2.8.1). */
6172 if (i.operands == 2)
6173 {
6174 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 6175 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 6176 register_prefix, i.op[!intel_syntax].regs->reg_name,
6177 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 6178 }
6179 else
6180 {
6181 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 6182 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6183 register_prefix, i.op[0].regs->reg_name);
4eed87de 6184 }
29b0f896
AM		 6185 }
6186 }
6187 }
40fb9820 6188 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 6189 {
6190 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 6191 must be put into the modrm byte). Now, we make the modrm and
6192 index base bytes based on all the info we've collected. */
29b0f896
AM		 6193
6194 default_seg = build_modrm_byte ();
6195 }
8a2ed489 6196 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 6197 {
6198 default_seg = &ds;
6199 }
40fb9820 6200 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 6201 {
6202 /* For the string instructions that allow a segment override
6203 on one of their operands, the default segment is ds. */
6204 default_seg = &ds;
6205 }
6206
75178d9d
L		 6207 if (i.tm.base_opcode == 0x8d /* lea */
6208 && i.seg[0]
6209 && !quiet_warnings)
30123838 6210 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 6211
6212 /* If a segment was explicitly specified, and the specified segment
6213 is not the default, use an opcode prefix to select it. If we
6214 never figured out what the default segment is, then default_seg
6215 will be zero at this point, and the specified segment prefix will
6216 always be used. */
29b0f896
AM		 6217 if ((i.seg[0]) && (i.seg[0] != default_seg))
6218 {
6219 if (!add_prefix (i.seg[0]->seg_prefix))
6220 return 0;
6221 }
6222 return 1;
6223}
6224
6225static const seg_entry *
e3bb37b5 6226build_modrm_byte (void)
29b0f896
AM		 6227{
6228 const seg_entry *default_seg = 0;
c0f3af97 6229 unsigned int source, dest;
8cd7925b 6230 int vex_3_sources;
c0f3af97
L		 6231
6232 /* The first operand of instructions with VEX prefix and 3 sources
6233 must be VEX_Imm4. */
8cd7925b 6234 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6235 if (vex_3_sources)
6236 {
91d6fa6a 6237 unsigned int nds, reg_slot;
4c2c6516 6238 expressionS *exp;
c0f3af97 6239
922d8de8 6240 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 6241 && i.tm.opcode_modifier.immext)
6242 {
6243 dest = i.operands - 2;
6244 gas_assert (dest == 3);
6245 }
922d8de8 6246 else
a683cc34 6247 dest = i.operands - 1;
c0f3af97 6248 nds = dest - 1;
922d8de8 6249
a683cc34
SP		 6250 /* There are 2 kinds of instructions:
6251 1. 5 operands: 4 register operands or 3 register operands
6252 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 6253 VexW0 or VexW1. The destination must be either XMM, YMM or
6254 ZMM register.
a683cc34
SP		 6255 2. 4 operands: 4 register operands or 3 register operands
6256 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 6257 gas_assert ((i.reg_operands == 4
a683cc34
SP		 6258 || (i.reg_operands == 3 && i.mem_operands == 1))
6259 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6260 && (i.tm.opcode_modifier.veximmext
6261 || (i.imm_operands == 1
6262 && i.types[0].bitfield.vec_imm4
6263 && (i.tm.opcode_modifier.vexw == VEXW0
6264 || i.tm.opcode_modifier.vexw == VEXW1)
6265 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 6266 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
6267 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 6268
6269 if (i.imm_operands == 0)
6270 {
6271 /* When there is no immediate operand, generate an 8bit
6272 immediate operand to encode the first operand. */
6273 exp = &im_expressions[i.imm_operands++];
6274 i.op[i.operands].imms = exp;
6275 i.types[i.operands] = imm8;
6276 i.operands++;
6277 /* If VexW1 is set, the first operand is the source and
6278 the second operand is encoded in the immediate operand. */
6279 if (i.tm.opcode_modifier.vexw == VEXW1)
6280 {
6281 source = 0;
6282 reg_slot = 1;
6283 }
6284 else
6285 {
6286 source = 1;
6287 reg_slot = 0;
6288 }
6289
6290 /* FMA swaps REG and NDS. */
6291 if (i.tm.cpu_flags.bitfield.cpufma)
6292 {
6293 unsigned int tmp;
6294 tmp = reg_slot;
6295 reg_slot = nds;
6296 nds = tmp;
6297 }
6298
24981e7b
L		 6299 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6300 &regxmm)
a683cc34 6301 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6302 &regymm)
6303 || operand_type_equal (&i.tm.operand_types[reg_slot],
6304 &regzmm));
a683cc34 6305 exp->X_op = O_constant;
4c692bc7 6306 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6307 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6308 }
922d8de8 6309 else
a683cc34
SP		 6310 {
6311 unsigned int imm_slot;
6312
6313 if (i.tm.opcode_modifier.vexw == VEXW0)
6314 {
6315 /* If VexW0 is set, the third operand is the source and
6316 the second operand is encoded in the immediate
6317 operand. */
6318 source = 2;
6319 reg_slot = 1;
6320 }
6321 else
6322 {
6323 /* VexW1 is set, the second operand is the source and
6324 the third operand is encoded in the immediate
6325 operand. */
6326 source = 1;
6327 reg_slot = 2;
6328 }
6329
6330 if (i.tm.opcode_modifier.immext)
6331 {
33eaf5de 6332 /* When ImmExt is set, the immediate byte is the last
a683cc34
SP		 6333 operand. */
6334 imm_slot = i.operands - 1;
6335 source--;
6336 reg_slot--;
6337 }
6338 else
6339 {
6340 imm_slot = 0;
6341
6342 /* Turn on Imm8 so that output_imm will generate it. */
6343 i.types[imm_slot].bitfield.imm8 = 1;
6344 }
6345
24981e7b
L		 6346 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6347 &regxmm)
6348 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6349 &regymm)
6350 || operand_type_equal (&i.tm.operand_types[reg_slot],
6351 &regzmm));
a683cc34 6352 i.op[imm_slot].imms->X_add_number
4c692bc7 6353 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6354 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6355 }
6356
6357 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6358 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6359 &regymm)
6360 || operand_type_equal (&i.tm.operand_types[nds],
6361 &regzmm));
dae39acc 6362 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6363 }
6364 else
6365 source = dest = 0;
29b0f896
AM		 6366
6367 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6368 implicit registers do not count. If there are 3 register
6369 operands, it must be a instruction with VexNDS. For a
6370 instruction with VexNDD, the destination register is encoded
6371 in VEX prefix. If there are 4 register operands, it must be
6372 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6373 if (i.mem_operands == 0
6374 && ((i.reg_operands == 2
2426c15f 6375 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6376 || (i.reg_operands == 3
2426c15f 6377 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6378 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6379 {
cab737b9
L		 6380 switch (i.operands)
6381 {
6382 case 2:
6383 source = 0;
6384 break;
6385 case 3:
c81128dc
L		 6386 /* When there are 3 operands, one of them may be immediate,
6387 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6388 the first operand must be shift count register (cl) or it
6389 is an instruction with VexNDS. */
9c2799c2 6390 gas_assert (i.imm_operands == 1
7ab9ffdd 6391 || (i.imm_operands == 0
2426c15f 6392 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6393 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6394 if (operand_type_check (i.types[0], imm)
6395 || i.types[0].bitfield.shiftcount)
6396 source = 1;
6397 else
6398 source = 0;
cab737b9
L		 6399 break;
6400 case 4:
368d64cc
L		 6401 /* When there are 4 operands, the first two must be 8bit
6402 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6403 one.
6404
6405 For instructions with VexNDS, if the first operand
6406 an imm8, the source operand is the 2nd one. If the last
6407 operand is imm8, the source operand is the first one. */
9c2799c2 6408 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6409 && i.types[0].bitfield.imm8
6410 && i.types[1].bitfield.imm8)
2426c15f 6411 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6412 && i.imm_operands == 1
6413 && (i.types[0].bitfield.imm8
43234a1e
L		 6414 || i.types[i.operands - 1].bitfield.imm8
6415 || i.rounding)));
9f2670f2
L		 6416 if (i.imm_operands == 2)
6417 source = 2;
6418 else
c0f3af97
L		 6419 {
6420 if (i.types[0].bitfield.imm8)
6421 source = 1;
6422 else
6423 source = 0;
6424 }
c0f3af97
L		 6425 break;
6426 case 5:
43234a1e
L		 6427 if (i.tm.opcode_modifier.evex)
6428 {
6429 /* For EVEX instructions, when there are 5 operands, the
6430 first one must be immediate operand. If the second one
6431 is immediate operand, the source operand is the 3th
6432 one. If the last one is immediate operand, the source
6433 operand is the 2nd one. */
6434 gas_assert (i.imm_operands == 2
6435 && i.tm.opcode_modifier.sae
6436 && operand_type_check (i.types[0], imm));
6437 if (operand_type_check (i.types[1], imm))
6438 source = 2;
6439 else if (operand_type_check (i.types[4], imm))
6440 source = 1;
6441 else
6442 abort ();
6443 }
cab737b9
L		 6444 break;
6445 default:
6446 abort ();
6447 }
6448
c0f3af97
L		 6449 if (!vex_3_sources)
6450 {
6451 dest = source + 1;
6452
43234a1e
L		 6453 /* RC/SAE operand could be between DEST and SRC. That happens
6454 when one operand is GPR and the other one is XMM/YMM/ZMM
6455 register. */
6456 if (i.rounding && i.rounding->operand == (int) dest)
6457 dest++;
6458
2426c15f 6459 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6460 {
43234a1e
L		 6461 /* For instructions with VexNDS, the register-only source
6462 operand must be 32/64bit integer, XMM, YMM or ZMM
6463 register. It is encoded in VEX prefix. We need to
6464 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6465
6466 i386_operand_type op;
6467 unsigned int vvvv;
6468
6469 /* Check register-only source operand when two source
6470 operands are swapped. */
6471 if (!i.tm.operand_types[source].bitfield.baseindex
6472 && i.tm.operand_types[dest].bitfield.baseindex)
6473 {
6474 vvvv = source;
6475 source = dest;
6476 }
6477 else
6478 vvvv = dest;
6479
6480 op = i.tm.operand_types[vvvv];
fa99fab2 6481 op.bitfield.regmem = 0;
c0f3af97 6482 if ((dest + 1) >= i.operands
ac4eb736
AM		 6483 || (!op.bitfield.reg32
6484 && op.bitfield.reg64
f12dc422 6485 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6486 && !operand_type_equal (&op, &regymm)
6487 && !operand_type_equal (&op, &regzmm)
6488 && !operand_type_equal (&op, &regmask)))
c0f3af97 6489 abort ();
f12dc422 6490 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6491 dest++;
6492 }
6493 }
29b0f896
AM		 6494
6495 i.rm.mode = 3;
6496 /* One of the register operands will be encoded in the i.tm.reg
6497 field, the other in the combined i.tm.mode and i.tm.regmem
6498 fields. If no form of this instruction supports a memory
6499 destination operand, then we assume the source operand may
6500 sometimes be a memory operand and so we need to store the
6501 destination in the i.rm.reg field. */
40fb9820
L		 6502 if (!i.tm.operand_types[dest].bitfield.regmem
6503 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6504 {
6505 i.rm.reg = i.op[dest].regs->reg_num;
6506 i.rm.regmem = i.op[source].regs->reg_num;
6507 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6508 i.rex |= REX_R;
43234a1e
L		 6509 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6510 i.vrex |= REX_R;
29b0f896 6511 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6512 i.rex |= REX_B;
43234a1e
L		 6513 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6514 i.vrex |= REX_B;
29b0f896
AM		 6515 }
6516 else
6517 {
6518 i.rm.reg = i.op[source].regs->reg_num;
6519 i.rm.regmem = i.op[dest].regs->reg_num;
6520 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6521 i.rex |= REX_B;
43234a1e
L		 6522 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6523 i.vrex |= REX_B;
29b0f896 6524 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6525 i.rex |= REX_R;
43234a1e
L		 6526 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6527 i.vrex |= REX_R;
29b0f896 6528 }
161a04f6 6529 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6530 {
40fb9820
L		 6531 if (!i.types[0].bitfield.control
6532 && !i.types[1].bitfield.control)
c4a530c5 6533 abort ();
161a04f6 6534 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6535 add_prefix (LOCK_PREFIX_OPCODE);
6536 }
29b0f896
AM		 6537 }
6538 else
6539 { /* If it's not 2 reg operands... */
c0f3af97
L		 6540 unsigned int mem;
6541
29b0f896
AM		 6542 if (i.mem_operands)
6543 {
6544 unsigned int fake_zero_displacement = 0;
99018f42 6545 unsigned int op;
4eed87de 6546
7ab9ffdd
L		 6547 for (op = 0; op < i.operands; op++)
6548 if (operand_type_check (i.types[op], anymem))
6549 break;
7ab9ffdd 6550 gas_assert (op < i.operands);
29b0f896 6551
6c30d220
L		 6552 if (i.tm.opcode_modifier.vecsib)
6553 {
6554 if (i.index_reg->reg_num == RegEiz
6555 || i.index_reg->reg_num == RegRiz)
6556 abort ();
6557
6558 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6559 if (!i.base_reg)
6560 {
6561 i.sib.base = NO_BASE_REGISTER;
6562 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6563 /* No Vec_Disp8 if there is no base. */
6564 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6565 i.types[op].bitfield.disp8 = 0;
6566 i.types[op].bitfield.disp16 = 0;
6567 i.types[op].bitfield.disp64 = 0;
6568 if (flag_code != CODE_64BIT)
6569 {
6570 /* Must be 32 bit */
6571 i.types[op].bitfield.disp32 = 1;
6572 i.types[op].bitfield.disp32s = 0;
6573 }
6574 else
6575 {
6576 i.types[op].bitfield.disp32 = 0;
6577 i.types[op].bitfield.disp32s = 1;
6578 }
6579 }
6580 i.sib.index = i.index_reg->reg_num;
6581 if ((i.index_reg->reg_flags & RegRex) != 0)
6582 i.rex |= REX_X;
43234a1e
L		 6583 if ((i.index_reg->reg_flags & RegVRex) != 0)
6584 i.vrex |= REX_X;
6c30d220
L		 6585 }
6586
29b0f896
AM		 6587 default_seg = &ds;
6588
6589 if (i.base_reg == 0)
6590 {
6591 i.rm.mode = 0;
6592 if (!i.disp_operands)
6c30d220
L		 6593 {
6594 fake_zero_displacement = 1;
6595 /* Instructions with VSIB byte need 32bit displacement
6596 if there is no base register. */
6597 if (i.tm.opcode_modifier.vecsib)
6598 i.types[op].bitfield.disp32 = 1;
6599 }
29b0f896
AM		 6600 if (i.index_reg == 0)
6601 {
6c30d220 6602 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6603 /* Operand is just <disp> */
20f0a1fc 6604 if (flag_code == CODE_64BIT)
29b0f896
AM		 6605 {
6606 /* 64bit mode overwrites the 32bit absolute
6607 addressing by RIP relative addressing and
6608 absolute addressing is encoded by one of the
6609 redundant SIB forms. */
6610 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6611 i.sib.base = NO_BASE_REGISTER;
6612 i.sib.index = NO_INDEX_REGISTER;
fc225355 6613 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6614 ? disp32s : disp32);
20f0a1fc 6615 }
fc225355
L		 6616 else if ((flag_code == CODE_16BIT)
6617 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6618 {
6619 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6620 i.types[op] = disp16;
20f0a1fc
NC		 6621 }
6622 else
6623 {
6624 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6625 i.types[op] = disp32;
29b0f896
AM		 6626 }
6627 }
6c30d220 6628 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6629 {
6c30d220 6630 /* !i.base_reg && i.index_reg */
db51cc60
L		 6631 if (i.index_reg->reg_num == RegEiz
6632 || i.index_reg->reg_num == RegRiz)
6633 i.sib.index = NO_INDEX_REGISTER;
6634 else
6635 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6636 i.sib.base = NO_BASE_REGISTER;
6637 i.sib.scale = i.log2_scale_factor;
6638 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6639 /* No Vec_Disp8 if there is no base. */
6640 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6641 i.types[op].bitfield.disp8 = 0;
6642 i.types[op].bitfield.disp16 = 0;
6643 i.types[op].bitfield.disp64 = 0;
29b0f896 6644 if (flag_code != CODE_64BIT)
40fb9820
L		 6645 {
6646 /* Must be 32 bit */
6647 i.types[op].bitfield.disp32 = 1;
6648 i.types[op].bitfield.disp32s = 0;
6649 }
29b0f896 6650 else
40fb9820
L		 6651 {
6652 i.types[op].bitfield.disp32 = 0;
6653 i.types[op].bitfield.disp32s = 1;
6654 }
29b0f896 6655 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6656 i.rex |= REX_X;
29b0f896
AM		 6657 }
6658 }
6659 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6660 else if (i.base_reg->reg_num == RegRip ||
6661 i.base_reg->reg_num == RegEip)
29b0f896 6662 {
6c30d220 6663 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6664 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6665 i.types[op].bitfield.disp8 = 0;
6666 i.types[op].bitfield.disp16 = 0;
6667 i.types[op].bitfield.disp32 = 0;
6668 i.types[op].bitfield.disp32s = 1;
6669 i.types[op].bitfield.disp64 = 0;
43234a1e 6670 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6671 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6672 if (! i.disp_operands)
6673 fake_zero_displacement = 1;
29b0f896 6674 }
40fb9820 6675 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6676 {
6c30d220 6677 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6678 switch (i.base_reg->reg_num)
6679 {
6680 case 3: /* (%bx) */
6681 if (i.index_reg == 0)
6682 i.rm.regmem = 7;
6683 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6684 i.rm.regmem = i.index_reg->reg_num - 6;
6685 break;
6686 case 5: /* (%bp) */
6687 default_seg = &ss;
6688 if (i.index_reg == 0)
6689 {
6690 i.rm.regmem = 6;
40fb9820 6691 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6692 {
6693 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6694 if (i.tm.operand_types[op].bitfield.vec_disp8)
6695 i.types[op].bitfield.vec_disp8 = 1;
6696 else
6697 i.types[op].bitfield.disp8 = 1;
252b5132 6698 fake_zero_displacement = 1;
29b0f896
AM		 6699 }
6700 }
6701 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6702 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6703 break;
6704 default: /* (%si) -> 4 or (%di) -> 5 */
6705 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6706 }
6707 i.rm.mode = mode_from_disp_size (i.types[op]);
6708 }
6709 else /* i.base_reg and 32/64 bit mode */
6710 {
6711 if (flag_code == CODE_64BIT
40fb9820
L		 6712 && operand_type_check (i.types[op], disp))
6713 {
6714 i386_operand_type temp;
0dfbf9d7 6715 operand_type_set (&temp, 0);
40fb9820 6716 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6717 temp.bitfield.vec_disp8
6718 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6719 i.types[op] = temp;
6720 if (i.prefix[ADDR_PREFIX] == 0)
6721 i.types[op].bitfield.disp32s = 1;
6722 else
6723 i.types[op].bitfield.disp32 = 1;
6724 }
20f0a1fc 6725
6c30d220
L		 6726 if (!i.tm.opcode_modifier.vecsib)
6727 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6728 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6729 i.rex |= REX_B;
29b0f896
AM		 6730 i.sib.base = i.base_reg->reg_num;
6731 /* x86-64 ignores REX prefix bit here to avoid decoder
6732 complications. */
848930b2
JB		 6733 if (!(i.base_reg->reg_flags & RegRex)
6734 && (i.base_reg->reg_num == EBP_REG_NUM
6735 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6736 default_seg = &ss;
848930b2 6737 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6738 {
848930b2 6739 fake_zero_displacement = 1;
43234a1e
L		 6740 if (i.tm.operand_types [op].bitfield.vec_disp8)
6741 i.types[op].bitfield.vec_disp8 = 1;
6742 else
6743 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6744 }
6745 i.sib.scale = i.log2_scale_factor;
6746 if (i.index_reg == 0)
6747 {
6c30d220 6748 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6749 /* <disp>(%esp) becomes two byte modrm with no index
6750 register. We've already stored the code for esp
6751 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6752 Any base register besides %esp will not use the
6753 extra modrm byte. */
6754 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6755 }
6c30d220 6756 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6757 {
db51cc60
L		 6758 if (i.index_reg->reg_num == RegEiz
6759 || i.index_reg->reg_num == RegRiz)
6760 i.sib.index = NO_INDEX_REGISTER;
6761 else
6762 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6763 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6764 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6765 i.rex |= REX_X;
29b0f896 6766 }
67a4f2b7
AO		 6767
6768 if (i.disp_operands
6769 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6770 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6771 i.rm.mode = 0;
6772 else
a501d77e
L		 6773 {
6774 if (!fake_zero_displacement
6775 && !i.disp_operands
6776 && i.disp_encoding)
6777 {
6778 fake_zero_displacement = 1;
6779 if (i.disp_encoding == disp_encoding_8bit)
6780 i.types[op].bitfield.disp8 = 1;
6781 else
6782 i.types[op].bitfield.disp32 = 1;
6783 }
6784 i.rm.mode = mode_from_disp_size (i.types[op]);
6785 }
29b0f896 6786 }
252b5132 6787
29b0f896
AM		 6788 if (fake_zero_displacement)
6789 {
6790 /* Fakes a zero displacement assuming that i.types[op]
6791 holds the correct displacement size. */
6792 expressionS *exp;
6793
9c2799c2 6794 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6795 exp = &disp_expressions[i.disp_operands++];
6796 i.op[op].disps = exp;
6797 exp->X_op = O_constant;
6798 exp->X_add_number = 0;
6799 exp->X_add_symbol = (symbolS *) 0;
6800 exp->X_op_symbol = (symbolS *) 0;
6801 }
c0f3af97
L		 6802
6803 mem = op;
29b0f896 6804 }
c0f3af97
L		 6805 else
6806 mem = ~0;
252b5132 6807
8c43a48b 6808 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6809 {
6810 if (operand_type_check (i.types[0], imm))
6811 i.vex.register_specifier = NULL;
6812 else
6813 {
6814 /* VEX.vvvv encodes one of the sources when the first
6815 operand is not an immediate. */
1ef99a7b 6816 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6817 i.vex.register_specifier = i.op[0].regs;
6818 else
6819 i.vex.register_specifier = i.op[1].regs;
6820 }
6821
6822 /* Destination is a XMM register encoded in the ModRM.reg
6823 and VEX.R bit. */
6824 i.rm.reg = i.op[2].regs->reg_num;
6825 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6826 i.rex |= REX_R;
6827
6828 /* ModRM.rm and VEX.B encodes the other source. */
6829 if (!i.mem_operands)
6830 {
6831 i.rm.mode = 3;
6832
1ef99a7b 6833 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6834 i.rm.regmem = i.op[1].regs->reg_num;
6835 else
6836 i.rm.regmem = i.op[0].regs->reg_num;
6837
6838 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6839 i.rex |= REX_B;
6840 }
6841 }
2426c15f 6842 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6843 {
6844 i.vex.register_specifier = i.op[2].regs;
6845 if (!i.mem_operands)
6846 {
6847 i.rm.mode = 3;
6848 i.rm.regmem = i.op[1].regs->reg_num;
6849 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6850 i.rex |= REX_B;
6851 }
6852 }
29b0f896
AM		 6853 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6854 (if any) based on i.tm.extension_opcode. Again, we must be
6855 careful to make sure that segment/control/debug/test/MMX
6856 registers are coded into the i.rm.reg field. */
f88c9eb0 6857 else if (i.reg_operands)
29b0f896 6858 {
99018f42 6859 unsigned int op;
7ab9ffdd
L		 6860 unsigned int vex_reg = ~0;
6861
6862 for (op = 0; op < i.operands; op++)
6863 if (i.types[op].bitfield.reg8
6864 || i.types[op].bitfield.reg16
6865 || i.types[op].bitfield.reg32
6866 || i.types[op].bitfield.reg64
6867 || i.types[op].bitfield.regmmx
6868 || i.types[op].bitfield.regxmm
6869 || i.types[op].bitfield.regymm
7e8b059b 6870 || i.types[op].bitfield.regbnd
43234a1e
L		 6871 || i.types[op].bitfield.regzmm
6872 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6873 || i.types[op].bitfield.sreg2
6874 || i.types[op].bitfield.sreg3
6875 || i.types[op].bitfield.control
6876 || i.types[op].bitfield.debug
6877 || i.types[op].bitfield.test)
6878 break;
c0209578 6879
7ab9ffdd
L		 6880 if (vex_3_sources)
6881 op = dest;
2426c15f 6882 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6883 {
6884 /* For instructions with VexNDS, the register-only
6885 source operand is encoded in VEX prefix. */
6886 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6887
7ab9ffdd 6888 if (op > mem)
c0f3af97 6889 {
7ab9ffdd
L		 6890 vex_reg = op++;
6891 gas_assert (op < i.operands);
c0f3af97
L		 6892 }
6893 else
c0f3af97 6894 {
f12dc422
L		 6895 /* Check register-only source operand when two source
6896 operands are swapped. */
6897 if (!i.tm.operand_types[op].bitfield.baseindex
6898 && i.tm.operand_types[op + 1].bitfield.baseindex)
6899 {
6900 vex_reg = op;
6901 op += 2;
6902 gas_assert (mem == (vex_reg + 1)
6903 && op < i.operands);
6904 }
6905 else
6906 {
6907 vex_reg = op + 1;
6908 gas_assert (vex_reg < i.operands);
6909 }
c0f3af97 6910 }
7ab9ffdd 6911 }
2426c15f 6912 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6913 {
f12dc422 6914 /* For instructions with VexNDD, the register destination
7ab9ffdd 6915 is encoded in VEX prefix. */
f12dc422
L		 6916 if (i.mem_operands == 0)
6917 {
6918 /* There is no memory operand. */
6919 gas_assert ((op + 2) == i.operands);
6920 vex_reg = op + 1;
6921 }
6922 else
8d63c93e 6923 {
f12dc422
L		 6924 /* There are only 2 operands. */
6925 gas_assert (op < 2 && i.operands == 2);
6926 vex_reg = 1;
6927 }
7ab9ffdd
L		 6928 }
6929 else
6930 gas_assert (op < i.operands);
99018f42 6931
7ab9ffdd
L		 6932 if (vex_reg != (unsigned int) ~0)
6933 {
f12dc422 6934 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6935
f12dc422
L		 6936 if (type->bitfield.reg32 != 1
6937 && type->bitfield.reg64 != 1
6938 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6939 && !operand_type_equal (type, &regymm)
6940 && !operand_type_equal (type, &regzmm)
6941 && !operand_type_equal (type, &regmask))
7ab9ffdd 6942 abort ();
f88c9eb0 6943
7ab9ffdd
L		 6944 i.vex.register_specifier = i.op[vex_reg].regs;
6945 }
6946
1b9f0c97
L		 6947 /* Don't set OP operand twice. */
6948 if (vex_reg != op)
7ab9ffdd 6949 {
1b9f0c97
L		 6950 /* If there is an extension opcode to put here, the
6951 register number must be put into the regmem field. */
6952 if (i.tm.extension_opcode != None)
6953 {
6954 i.rm.regmem = i.op[op].regs->reg_num;
6955 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6956 i.rex |= REX_B;
43234a1e
L		 6957 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6958 i.vrex |= REX_B;
1b9f0c97
L		 6959 }
6960 else
6961 {
6962 i.rm.reg = i.op[op].regs->reg_num;
6963 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6964 i.rex |= REX_R;
43234a1e
L		 6965 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6966 i.vrex |= REX_R;
1b9f0c97 6967 }
7ab9ffdd 6968 }
252b5132 6969
29b0f896
AM		 6970 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6971 must set it to 3 to indicate this is a register operand
6972 in the regmem field. */
6973 if (!i.mem_operands)
6974 i.rm.mode = 3;
6975 }
252b5132 6976
29b0f896 6977 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6978 if (i.tm.extension_opcode != None)
29b0f896
AM		 6979 i.rm.reg = i.tm.extension_opcode;
6980 }
6981 return default_seg;
6982}
252b5132 6983
29b0f896 6984static void
e3bb37b5 6985output_branch (void)
29b0f896
AM		 6986{
6987 char *p;
f8a5c266 6988 int size;
29b0f896
AM		 6989 int code16;
6990 int prefix;
6991 relax_substateT subtype;
6992 symbolS *sym;
6993 offsetT off;
6994
f8a5c266 6995 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6996 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6997
6998 prefix = 0;
6999 if (i.prefix[DATA_PREFIX] != 0)
252b5132 7000 {
29b0f896
AM		 7001 prefix = 1;
7002 i.prefixes -= 1;
7003 code16 ^= CODE16;
252b5132 7004 }
29b0f896
AM		 7005 /* Pentium4 branch hints. */
7006 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7007 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 7008 {
29b0f896
AM		 7009 prefix++;
7010 i.prefixes--;
7011 }
7012 if (i.prefix[REX_PREFIX] != 0)
7013 {
7014 prefix++;
7015 i.prefixes--;
2f66722d
AM		 7016 }
7017
7e8b059b
L		 7018 /* BND prefixed jump. */
7019 if (i.prefix[BND_PREFIX] != 0)
7020 {
7021 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7022 i.prefixes -= 1;
7023 }
7024
29b0f896
AM		 7025 if (i.prefixes != 0 && !intel_syntax)
7026 as_warn (_("skipping prefixes on this instruction"));
7027
7028 /* It's always a symbol; End frag & setup for relax.
7029 Make sure there is enough room in this frag for the largest
7030 instruction we may generate in md_convert_frag. This is 2
7031 bytes for the opcode and room for the prefix and largest
7032 displacement. */
7033 frag_grow (prefix + 2 + 4);
7034 /* Prefix and 1 opcode byte go in fr_fix. */
7035 p = frag_more (prefix + 1);
7036 if (i.prefix[DATA_PREFIX] != 0)
7037 *p++ = DATA_PREFIX_OPCODE;
7038 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7039 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7040 *p++ = i.prefix[SEG_PREFIX];
7041 if (i.prefix[REX_PREFIX] != 0)
7042 *p++ = i.prefix[REX_PREFIX];
7043 *p = i.tm.base_opcode;
7044
7045 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 7046 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 7047 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 7048 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 7049 else
f8a5c266 7050 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 7051 subtype |= code16;
3e73aa7c 7052
29b0f896
AM		 7053 sym = i.op[0].disps->X_add_symbol;
7054 off = i.op[0].disps->X_add_number;
3e73aa7c 7055
29b0f896
AM		 7056 if (i.op[0].disps->X_op != O_constant
7057 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 7058 {
29b0f896
AM		 7059 /* Handle complex expressions. */
7060 sym = make_expr_symbol (i.op[0].disps);
7061 off = 0;
7062 }
3e73aa7c 7063
29b0f896
AM		 7064 /* 1 possible extra opcode + 4 byte displacement go in var part.
7065 Pass reloc in fr_var. */
d258b828 7066 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 7067}
3e73aa7c 7068
29b0f896 7069static void
e3bb37b5 7070output_jump (void)
29b0f896
AM		 7071{
7072 char *p;
7073 int size;
3e02c1cc 7074 fixS *fixP;
29b0f896 7075
40fb9820 7076 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 7077 {
7078 /* This is a loop or jecxz type instruction. */
7079 size = 1;
7080 if (i.prefix[ADDR_PREFIX] != 0)
7081 {
7082 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7083 i.prefixes -= 1;
7084 }
7085 /* Pentium4 branch hints. */
7086 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7087 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7088 {
7089 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7090 i.prefixes--;
3e73aa7c
JH		 7091 }
7092 }
29b0f896
AM		 7093 else
7094 {
7095 int code16;
3e73aa7c 7096
29b0f896
AM		 7097 code16 = 0;
7098 if (flag_code == CODE_16BIT)
7099 code16 = CODE16;
3e73aa7c 7100
29b0f896
AM		 7101 if (i.prefix[DATA_PREFIX] != 0)
7102 {
7103 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7104 i.prefixes -= 1;
7105 code16 ^= CODE16;
7106 }
252b5132 7107
29b0f896
AM		 7108 size = 4;
7109 if (code16)
7110 size = 2;
7111 }
9fcc94b6 7112
29b0f896
AM		 7113 if (i.prefix[REX_PREFIX] != 0)
7114 {
7115 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7116 i.prefixes -= 1;
7117 }
252b5132 7118
7e8b059b
L		 7119 /* BND prefixed jump. */
7120 if (i.prefix[BND_PREFIX] != 0)
7121 {
7122 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7123 i.prefixes -= 1;
7124 }
7125
29b0f896
AM		 7126 if (i.prefixes != 0 && !intel_syntax)
7127 as_warn (_("skipping prefixes on this instruction"));
e0890092 7128
42164a71
L		 7129 p = frag_more (i.tm.opcode_length + size);
7130 switch (i.tm.opcode_length)
7131 {
7132 case 2:
7133 *p++ = i.tm.base_opcode >> 8;
1a0670f3 7134 /* Fall through. */
42164a71
L		 7135 case 1:
7136 *p++ = i.tm.base_opcode;
7137 break;
7138 default:
7139 abort ();
7140 }
e0890092 7141
3e02c1cc 7142 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7143 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 7144
7145 /* All jumps handled here are signed, but don't use a signed limit
7146 check for 32 and 16 bit jumps as we want to allow wrap around at
7147 4G and 64k respectively. */
7148 if (size == 1)
7149 fixP->fx_signed = 1;
29b0f896 7150}
e0890092 7151
29b0f896 7152static void
e3bb37b5 7153output_interseg_jump (void)
29b0f896
AM		 7154{
7155 char *p;
7156 int size;
7157 int prefix;
7158 int code16;
252b5132 7159
29b0f896
AM		 7160 code16 = 0;
7161 if (flag_code == CODE_16BIT)
7162 code16 = CODE16;
a217f122 7163
29b0f896
AM		 7164 prefix = 0;
7165 if (i.prefix[DATA_PREFIX] != 0)
7166 {
7167 prefix = 1;
7168 i.prefixes -= 1;
7169 code16 ^= CODE16;
7170 }
7171 if (i.prefix[REX_PREFIX] != 0)
7172 {
7173 prefix++;
7174 i.prefixes -= 1;
7175 }
252b5132 7176
29b0f896
AM		 7177 size = 4;
7178 if (code16)
7179 size = 2;
252b5132 7180
29b0f896
AM		 7181 if (i.prefixes != 0 && !intel_syntax)
7182 as_warn (_("skipping prefixes on this instruction"));
252b5132 7183
29b0f896
AM		 7184 /* 1 opcode; 2 segment; offset */
7185 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 7186
29b0f896
AM		 7187 if (i.prefix[DATA_PREFIX] != 0)
7188 *p++ = DATA_PREFIX_OPCODE;
252b5132 7189
29b0f896
AM		 7190 if (i.prefix[REX_PREFIX] != 0)
7191 *p++ = i.prefix[REX_PREFIX];
252b5132 7192
29b0f896
AM		 7193 *p++ = i.tm.base_opcode;
7194 if (i.op[1].imms->X_op == O_constant)
7195 {
7196 offsetT n = i.op[1].imms->X_add_number;
252b5132 7197
29b0f896
AM		 7198 if (size == 2
7199 && !fits_in_unsigned_word (n)
7200 && !fits_in_signed_word (n))
7201 {
7202 as_bad (_("16-bit jump out of range"));
7203 return;
7204 }
7205 md_number_to_chars (p, n, size);
7206 }
7207 else
7208 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7209 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 7210 if (i.op[0].imms->X_op != O_constant)
7211 as_bad (_("can't handle non absolute segment in `%s'"),
7212 i.tm.name);
7213 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7214}
a217f122 7215
29b0f896 7216static void
e3bb37b5 7217output_insn (void)
29b0f896 7218{
2bbd9c25
JJ		 7219 fragS *insn_start_frag;
7220 offsetT insn_start_off;
7221
29b0f896
AM		 7222 /* Tie dwarf2 debug info to the address at the start of the insn.
7223 We can't do this after the insn has been output as the current
7224 frag may have been closed off. eg. by frag_var. */
7225 dwarf2_emit_insn (0);
7226
2bbd9c25
JJ		 7227 insn_start_frag = frag_now;
7228 insn_start_off = frag_now_fix ();
7229
29b0f896 7230 /* Output jumps. */
40fb9820 7231 if (i.tm.opcode_modifier.jump)
29b0f896 7232 output_branch ();
40fb9820
L		 7233 else if (i.tm.opcode_modifier.jumpbyte
7234 || i.tm.opcode_modifier.jumpdword)
29b0f896 7235 output_jump ();
40fb9820 7236 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7237 output_interseg_jump ();
7238 else
7239 {
7240 /* Output normal instructions here. */
7241 char *p;
7242 unsigned char *q;
47465058 7243 unsigned int j;
331d2d0d 7244 unsigned int prefix;
4dffcebc 7245
e4e00185
AS		 7246 if (avoid_fence
7247 && i.tm.base_opcode == 0xfae
7248 && i.operands == 1
7249 && i.imm_operands == 1
7250 && (i.op[0].imms->X_add_number == 0xe8
7251 || i.op[0].imms->X_add_number == 0xf0
7252 || i.op[0].imms->X_add_number == 0xf8))
7253 {
7254 /* Encode lfence, mfence, and sfence as
7255 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7256 offsetT val = 0x240483f0ULL;
7257 p = frag_more (5);
7258 md_number_to_chars (p, val, 5);
7259 return;
7260 }
7261
d022bddd
IT		 7262 /* Some processors fail on LOCK prefix. This options makes
7263 assembler ignore LOCK prefix and serves as a workaround. */
7264 if (omit_lock_prefix)
7265 {
7266 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7267 return;
7268 i.prefix[LOCK_PREFIX] = 0;
7269 }
7270
43234a1e
L		 7271 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7272 don't need the explicit prefix. */
7273 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7274 {
c0f3af97 7275 switch (i.tm.opcode_length)
bc4bd9ab 7276 {
c0f3af97
L		 7277 case 3:
7278 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7279 {
c0f3af97
L		 7280 prefix = (i.tm.base_opcode >> 24) & 0xff;
7281 goto check_prefix;
7282 }
7283 break;
7284 case 2:
7285 if ((i.tm.base_opcode & 0xff0000) != 0)
7286 {
7287 prefix = (i.tm.base_opcode >> 16) & 0xff;
7288 if (i.tm.cpu_flags.bitfield.cpupadlock)
7289 {
4dffcebc 7290check_prefix:
c0f3af97 7291 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 7292 || (i.prefix[REP_PREFIX]
c0f3af97
L		 7293 != REPE_PREFIX_OPCODE))
7294 add_prefix (prefix);
7295 }
7296 else
4dffcebc
L		 7297 add_prefix (prefix);
7298 }
c0f3af97
L		 7299 break;
7300 case 1:
7301 break;
7302 default:
7303 abort ();
bc4bd9ab 7304 }
c0f3af97 7305
6d19a37a 7306#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7307 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7308 R_X86_64_GOTTPOFF relocation so that linker can safely
7309 perform IE->LE optimization. */
7310 if (x86_elf_abi == X86_64_X32_ABI
7311 && i.operands == 2
7312 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7313 && i.prefix[REX_PREFIX] == 0)
7314 add_prefix (REX_OPCODE);
6d19a37a 7315#endif
cf61b747 7316
c0f3af97
L		 7317 /* The prefix bytes. */
7318 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7319 if (*q)
7320 FRAG_APPEND_1_CHAR (*q);
0f10071e 7321 }
ae5c1c7b 7322 else
c0f3af97
L		 7323 {
7324 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7325 if (*q)
7326 switch (j)
7327 {
7328 case REX_PREFIX:
7329 /* REX byte is encoded in VEX prefix. */
7330 break;
7331 case SEG_PREFIX:
7332 case ADDR_PREFIX:
7333 FRAG_APPEND_1_CHAR (*q);
7334 break;
7335 default:
7336 /* There should be no other prefixes for instructions
7337 with VEX prefix. */
7338 abort ();
7339 }
7340
43234a1e
L		 7341 /* For EVEX instructions i.vrex should become 0 after
7342 build_evex_prefix. For VEX instructions upper 16 registers
7343 aren't available, so VREX should be 0. */
7344 if (i.vrex)
7345 abort ();
c0f3af97
L		 7346 /* Now the VEX prefix. */
7347 p = frag_more (i.vex.length);
7348 for (j = 0; j < i.vex.length; j++)
7349 p[j] = i.vex.bytes[j];
7350 }
252b5132 7351
29b0f896 7352 /* Now the opcode; be careful about word order here! */
4dffcebc 7353 if (i.tm.opcode_length == 1)
29b0f896
AM		 7354 {
7355 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7356 }
7357 else
7358 {
4dffcebc 7359 switch (i.tm.opcode_length)
331d2d0d 7360 {
43234a1e
L		 7361 case 4:
7362 p = frag_more (4);
7363 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7364 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7365 break;
4dffcebc 7366 case 3:
331d2d0d
L		 7367 p = frag_more (3);
7368 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7369 break;
7370 case 2:
7371 p = frag_more (2);
7372 break;
7373 default:
7374 abort ();
7375 break;
331d2d0d 7376 }
0f10071e 7377
29b0f896
AM		 7378 /* Put out high byte first: can't use md_number_to_chars! */
7379 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7380 *p = i.tm.base_opcode & 0xff;
7381 }
3e73aa7c 7382
29b0f896 7383 /* Now the modrm byte and sib byte (if present). */
40fb9820 7384 if (i.tm.opcode_modifier.modrm)
29b0f896 7385 {
4a3523fa
L		 7386 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7387 | i.rm.reg << 3
7388 | i.rm.mode << 6));
29b0f896
AM		 7389 /* If i.rm.regmem == ESP (4)
7390 && i.rm.mode != (Register mode)
7391 && not 16 bit
7392 ==> need second modrm byte. */
7393 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7394 && i.rm.mode != 3
40fb9820 7395 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7396 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7397 | i.sib.index << 3
7398 | i.sib.scale << 6));
29b0f896 7399 }
3e73aa7c 7400
29b0f896 7401 if (i.disp_operands)
2bbd9c25 7402 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7403
29b0f896 7404 if (i.imm_operands)
2bbd9c25 7405 output_imm (insn_start_frag, insn_start_off);
29b0f896 7406 }
252b5132 7407
29b0f896
AM		 7408#ifdef DEBUG386
7409 if (flag_debug)
7410 {
7b81dfbb 7411 pi ("" /*line*/, &i);
29b0f896
AM		 7412 }
7413#endif /* DEBUG386 */
7414}
252b5132 7415
e205caa7
L		 7416/* Return the size of the displacement operand N. */
7417
7418static int
7419disp_size (unsigned int n)
7420{
7421 int size = 4;
43234a1e
L		 7422
7423 /* Vec_Disp8 has to be 8bit. */
7424 if (i.types[n].bitfield.vec_disp8)
7425 size = 1;
7426 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7427 size = 8;
7428 else if (i.types[n].bitfield.disp8)
7429 size = 1;
7430 else if (i.types[n].bitfield.disp16)
7431 size = 2;
e205caa7
L		 7432 return size;
7433}
7434
7435/* Return the size of the immediate operand N. */
7436
7437static int
7438imm_size (unsigned int n)
7439{
7440 int size = 4;
40fb9820
L		 7441 if (i.types[n].bitfield.imm64)
7442 size = 8;
7443 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7444 size = 1;
7445 else if (i.types[n].bitfield.imm16)
7446 size = 2;
e205caa7
L		 7447 return size;
7448}
7449
29b0f896 7450static void
64e74474 7451output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7452{
7453 char *p;
7454 unsigned int n;
252b5132 7455
29b0f896
AM		 7456 for (n = 0; n < i.operands; n++)
7457 {
43234a1e
L		 7458 if (i.types[n].bitfield.vec_disp8
7459 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7460 {
7461 if (i.op[n].disps->X_op == O_constant)
7462 {
e205caa7 7463 int size = disp_size (n);
43234a1e 7464 offsetT val = i.op[n].disps->X_add_number;
252b5132 7465
43234a1e
L		 7466 if (i.types[n].bitfield.vec_disp8)
7467 val >>= i.memshift;
7468 val = offset_in_range (val, size);
29b0f896
AM		 7469 p = frag_more (size);
7470 md_number_to_chars (p, val, size);
7471 }
7472 else
7473 {
f86103b7 7474 enum bfd_reloc_code_real reloc_type;
e205caa7 7475 int size = disp_size (n);
40fb9820 7476 int sign = i.types[n].bitfield.disp32s;
29b0f896 7477 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7478 fixS *fixP;
29b0f896 7479
e205caa7 7480 /* We can't have 8 bit displacement here. */
9c2799c2 7481 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7482
29b0f896
AM		 7483 /* The PC relative address is computed relative
7484 to the instruction boundary, so in case immediate
7485 fields follows, we need to adjust the value. */
7486 if (pcrel && i.imm_operands)
7487 {
29b0f896 7488 unsigned int n1;
e205caa7 7489 int sz = 0;
252b5132 7490
29b0f896 7491 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7492 if (operand_type_check (i.types[n1], imm))
252b5132 7493 {
e205caa7
L		 7494 /* Only one immediate is allowed for PC
7495 relative address. */
9c2799c2 7496 gas_assert (sz == 0);
e205caa7
L		 7497 sz = imm_size (n1);
7498 i.op[n].disps->X_add_number -= sz;
252b5132 7499 }
29b0f896 7500 /* We should find the immediate. */
9c2799c2 7501 gas_assert (sz != 0);
29b0f896 7502 }
520dc8e8 7503
29b0f896 7504 p = frag_more (size);
d258b828 7505 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7506 if (GOT_symbol
2bbd9c25 7507 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7508 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7509 || reloc_type == BFD_RELOC_X86_64_32S
7510 || (reloc_type == BFD_RELOC_64
7511 && object_64bit))
d6ab8113
JB		 7512 && (i.op[n].disps->X_op == O_symbol
7513 || (i.op[n].disps->X_op == O_add
7514 && ((symbol_get_value_expression
7515 (i.op[n].disps->X_op_symbol)->X_op)
7516 == O_subtract))))
7517 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7518 {
7519 offsetT add;
7520
7521 if (insn_start_frag == frag_now)
7522 add = (p - frag_now->fr_literal) - insn_start_off;
7523 else
7524 {
7525 fragS *fr;
7526
7527 add = insn_start_frag->fr_fix - insn_start_off;
7528 for (fr = insn_start_frag->fr_next;
7529 fr && fr != frag_now; fr = fr->fr_next)
7530 add += fr->fr_fix;
7531 add += p - frag_now->fr_literal;
7532 }
7533
4fa24527 7534 if (!object_64bit)
7b81dfbb
AJ		 7535 {
7536 reloc_type = BFD_RELOC_386_GOTPC;
7537 i.op[n].imms->X_add_number += add;
7538 }
7539 else if (reloc_type == BFD_RELOC_64)
7540 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7541 else
7b81dfbb
AJ		 7542 /* Don't do the adjustment for x86-64, as there
7543 the pcrel addressing is relative to the _next_
7544 insn, and that is taken care of in other code. */
d6ab8113 7545 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7546 }
02a86693
L		 7547 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7548 size, i.op[n].disps, pcrel,
7549 reloc_type);
7550 /* Check for "call/jmp *mem", "mov mem, %reg",
7551 "test %reg, mem" and "binop mem, %reg" where binop
7552 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 7553 instructions. Always generate R_386_GOT32X for
7554 "sym*GOT" operand in 32-bit mode. */
7555 if ((generate_relax_relocations
7556 || (!object_64bit
7557 && i.rm.mode == 0
7558 && i.rm.regmem == 5))
7559 && (i.rm.mode == 2
7560 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 7561 && ((i.operands == 1
7562 && i.tm.base_opcode == 0xff
7563 && (i.rm.reg == 2 || i.rm.reg == 4))
7564 || (i.operands == 2
7565 && (i.tm.base_opcode == 0x8b
7566 || i.tm.base_opcode == 0x85
7567 || (i.tm.base_opcode & 0xc7) == 0x03))))
7568 {
7569 if (object_64bit)
7570 {
7571 fixP->fx_tcbit = i.rex != 0;
7572 if (i.base_reg
7573 && (i.base_reg->reg_num == RegRip
7574 || i.base_reg->reg_num == RegEip))
7575 fixP->fx_tcbit2 = 1;
7576 }
7577 else
7578 fixP->fx_tcbit2 = 1;
7579 }
29b0f896
AM		 7580 }
7581 }
7582 }
7583}
252b5132 7584
29b0f896 7585static void
64e74474 7586output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7587{
7588 char *p;
7589 unsigned int n;
252b5132 7590
29b0f896
AM		 7591 for (n = 0; n < i.operands; n++)
7592 {
43234a1e
L		 7593 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7594 if (i.rounding && (int) n == i.rounding->operand)
7595 continue;
7596
40fb9820 7597 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7598 {
7599 if (i.op[n].imms->X_op == O_constant)
7600 {
e205caa7 7601 int size = imm_size (n);
29b0f896 7602 offsetT val;
b4cac588 7603
29b0f896
AM		 7604 val = offset_in_range (i.op[n].imms->X_add_number,
7605 size);
7606 p = frag_more (size);
7607 md_number_to_chars (p, val, size);
7608 }
7609 else
7610 {
7611 /* Not absolute_section.
7612 Need a 32-bit fixup (don't support 8bit
7613 non-absolute imms). Try to support other
7614 sizes ... */
f86103b7 7615 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7616 int size = imm_size (n);
7617 int sign;
29b0f896 7618
40fb9820 7619 if (i.types[n].bitfield.imm32s
a7d61044 7620 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7621 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7622 sign = 1;
e205caa7
L		 7623 else
7624 sign = 0;
520dc8e8 7625
29b0f896 7626 p = frag_more (size);
d258b828 7627 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7628
2bbd9c25
JJ		 7629 /* This is tough to explain. We end up with this one if we
7630 * have operands that look like
7631 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7632 * obtain the absolute address of the GOT, and it is strongly
7633 * preferable from a performance point of view to avoid using
7634 * a runtime relocation for this. The actual sequence of
7635 * instructions often look something like:
7636 *
7637 * call .L66
7638 * .L66:
7639 * popl %ebx
7640 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7641 *
7642 * The call and pop essentially return the absolute address
7643 * of the label .L66 and store it in %ebx. The linker itself
7644 * will ultimately change the first operand of the addl so
7645 * that %ebx points to the GOT, but to keep things simple, the
7646 * .o file must have this operand set so that it generates not
7647 * the absolute address of .L66, but the absolute address of
7648 * itself. This allows the linker itself simply treat a GOTPC
7649 * relocation as asking for a pcrel offset to the GOT to be
7650 * added in, and the addend of the relocation is stored in the
7651 * operand field for the instruction itself.
7652 *
7653 * Our job here is to fix the operand so that it would add
7654 * the correct offset so that %ebx would point to itself. The
7655 * thing that is tricky is that .-.L66 will point to the
7656 * beginning of the instruction, so we need to further modify
7657 * the operand so that it will point to itself. There are
7658 * other cases where you have something like:
7659 *
7660 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7661 *
7662 * and here no correction would be required. Internally in
7663 * the assembler we treat operands of this form as not being
7664 * pcrel since the '.' is explicitly mentioned, and I wonder
7665 * whether it would simplify matters to do it this way. Who
7666 * knows. In earlier versions of the PIC patches, the
7667 * pcrel_adjust field was used to store the correction, but
7668 * since the expression is not pcrel, I felt it would be
7669 * confusing to do it this way. */
7670
d6ab8113 7671 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7672 || reloc_type == BFD_RELOC_X86_64_32S
7673 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7674 && GOT_symbol
7675 && GOT_symbol == i.op[n].imms->X_add_symbol
7676 && (i.op[n].imms->X_op == O_symbol
7677 || (i.op[n].imms->X_op == O_add
7678 && ((symbol_get_value_expression
7679 (i.op[n].imms->X_op_symbol)->X_op)
7680 == O_subtract))))
7681 {
2bbd9c25
JJ		 7682 offsetT add;
7683
7684 if (insn_start_frag == frag_now)
7685 add = (p - frag_now->fr_literal) - insn_start_off;
7686 else
7687 {
7688 fragS *fr;
7689
7690 add = insn_start_frag->fr_fix - insn_start_off;
7691 for (fr = insn_start_frag->fr_next;
7692 fr && fr != frag_now; fr = fr->fr_next)
7693 add += fr->fr_fix;
7694 add += p - frag_now->fr_literal;
7695 }
7696
4fa24527 7697 if (!object_64bit)
d6ab8113 7698 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7699 else if (size == 4)
d6ab8113 7700 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7701 else if (size == 8)
7702 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7703 i.op[n].imms->X_add_number += add;
29b0f896 7704 }
29b0f896
AM		 7705 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7706 i.op[n].imms, 0, reloc_type);
7707 }
7708 }
7709 }
252b5132
RH		 7710}
7711\f
d182319b
JB		 7712/* x86_cons_fix_new is called via the expression parsing code when a
7713 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7714static int cons_sign = -1;
7715
7716void
e3bb37b5 7717x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7718 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7719{
d258b828 7720 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7721
7722#ifdef TE_PE
7723 if (exp->X_op == O_secrel)
7724 {
7725 exp->X_op = O_symbol;
7726 r = BFD_RELOC_32_SECREL;
7727 }
7728#endif
7729
7730 fix_new_exp (frag, off, len, exp, 0, r);
7731}
7732
357d1bd8
L		 7733/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7734 purpose of the `.dc.a' internal pseudo-op. */
7735
7736int
7737x86_address_bytes (void)
7738{
7739 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7740 return 4;
7741 return stdoutput->arch_info->bits_per_address / 8;
7742}
7743
d382c579
TG		 7744#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7745 || defined (LEX_AT)
d258b828 7746# define lex_got(reloc, adjust, types) NULL
718ddfc0 7747#else
f3c180ae
AM		 7748/* Parse operands of the form
7749 <symbol>@GOTOFF+<nnn>
7750 and similar .plt or .got references.
7751
7752 If we find one, set up the correct relocation in RELOC and copy the
7753 input string, minus the `@GOTOFF' into a malloc'd buffer for
7754 parsing by the calling routine. Return this buffer, and if ADJUST
7755 is non-null set it to the length of the string we removed from the
7756 input line. Otherwise return NULL. */
7757static char *
91d6fa6a 7758lex_got (enum bfd_reloc_code_real *rel,
64e74474 7759 int *adjust,
d258b828 7760 i386_operand_type *types)
f3c180ae 7761{
7b81dfbb
AJ		 7762 /* Some of the relocations depend on the size of what field is to
7763 be relocated. But in our callers i386_immediate and i386_displacement
7764 we don't yet know the operand size (this will be set by insn
7765 matching). Hence we record the word32 relocation here,
7766 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7767 static const struct {
7768 const char *str;
cff8d58a 7769 int len;
4fa24527 7770 const enum bfd_reloc_code_real rel[2];
40fb9820 7771 const i386_operand_type types64;
f3c180ae 7772 } gotrel[] = {
8ce3d284 7773#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7774 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7775 BFD_RELOC_SIZE32 },
7776 OPERAND_TYPE_IMM32_64 },
8ce3d284 7777#endif
cff8d58a
L		 7778 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7779 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7780 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7781 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7782 BFD_RELOC_X86_64_PLT32 },
40fb9820 7783 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7784 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7785 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7786 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7787 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7788 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7789 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7790 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7791 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7792 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7793 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7794 BFD_RELOC_X86_64_TLSGD },
40fb9820 7795 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7796 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7797 _dummy_first_bfd_reloc_code_real },
40fb9820 7798 OPERAND_TYPE_NONE },
cff8d58a
L		 7799 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7800 BFD_RELOC_X86_64_TLSLD },
40fb9820 7801 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7802 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7803 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7804 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7805 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7806 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7807 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7808 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7809 _dummy_first_bfd_reloc_code_real },
40fb9820 7810 OPERAND_TYPE_NONE },
cff8d58a
L		 7811 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7812 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7813 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7814 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7815 _dummy_first_bfd_reloc_code_real },
40fb9820 7816 OPERAND_TYPE_NONE },
cff8d58a
L		 7817 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7818 _dummy_first_bfd_reloc_code_real },
40fb9820 7819 OPERAND_TYPE_NONE },
cff8d58a
L		 7820 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7821 BFD_RELOC_X86_64_GOT32 },
40fb9820 7822 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7823 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7824 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7825 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7826 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7827 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7828 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7829 };
7830 char *cp;
7831 unsigned int j;
7832
d382c579 7833#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7834 if (!IS_ELF)
7835 return NULL;
d382c579 7836#endif
718ddfc0 7837
f3c180ae 7838 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7839 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7840 return NULL;
7841
47465058 7842 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7843 {
cff8d58a 7844 int len = gotrel[j].len;
28f81592 7845 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7846 {
4fa24527 7847 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7848 {
28f81592
AM		 7849 int first, second;
7850 char *tmpbuf, *past_reloc;
f3c180ae 7851
91d6fa6a 7852 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7853
3956db08
JB		 7854 if (types)
7855 {
7856 if (flag_code != CODE_64BIT)
40fb9820
L		 7857 {
7858 types->bitfield.imm32 = 1;
7859 types->bitfield.disp32 = 1;
7860 }
3956db08
JB		 7861 else
7862 *types = gotrel[j].types64;
7863 }
7864
8fd4256d 7865 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7866 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7867
28f81592 7868 /* The length of the first part of our input line. */
f3c180ae 7869 first = cp - input_line_pointer;
28f81592
AM		 7870
7871 /* The second part goes from after the reloc token until
67c11a9b 7872 (and including) an end_of_line char or comma. */
28f81592 7873 past_reloc = cp + 1 + len;
67c11a9b
AM		 7874 cp = past_reloc;
7875 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7876 ++cp;
7877 second = cp + 1 - past_reloc;
28f81592
AM		 7878
7879 /* Allocate and copy string. The trailing NUL shouldn't
7880 be necessary, but be safe. */
add39d23 7881 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 7882 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7883 if (second != 0 && *past_reloc != ' ')
7884 /* Replace the relocation token with ' ', so that
7885 errors like foo@GOTOFF1 will be detected. */
7886 tmpbuf[first++] = ' ';
af89796a
L		 7887 else
7888 /* Increment length by 1 if the relocation token is
7889 removed. */
7890 len++;
7891 if (adjust)
7892 *adjust = len;
0787a12d
AM		 7893 memcpy (tmpbuf + first, past_reloc, second);
7894 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7895 return tmpbuf;
7896 }
7897
4fa24527
JB		 7898 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7899 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7900 return NULL;
7901 }
7902 }
7903
7904 /* Might be a symbol version string. Don't as_bad here. */
7905 return NULL;
7906}
4e4f7c87 7907#endif
f3c180ae 7908
a988325c
NC		 7909#ifdef TE_PE
7910#ifdef lex_got
7911#undef lex_got
7912#endif
7913/* Parse operands of the form
7914 <symbol>@SECREL32+<nnn>
7915
7916 If we find one, set up the correct relocation in RELOC and copy the
7917 input string, minus the `@SECREL32' into a malloc'd buffer for
7918 parsing by the calling routine. Return this buffer, and if ADJUST
7919 is non-null set it to the length of the string we removed from the
34bca508
L		 7920 input line. Otherwise return NULL.
7921
a988325c
NC		 7922 This function is copied from the ELF version above adjusted for PE targets. */
7923
7924static char *
7925lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7926 int *adjust ATTRIBUTE_UNUSED,
d258b828 7927 i386_operand_type *types)
a988325c
NC		 7928{
7929 static const struct
7930 {
7931 const char *str;
7932 int len;
7933 const enum bfd_reloc_code_real rel[2];
7934 const i386_operand_type types64;
7935 }
7936 gotrel[] =
7937 {
7938 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7939 BFD_RELOC_32_SECREL },
7940 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7941 };
7942
7943 char *cp;
7944 unsigned j;
7945
7946 for (cp = input_line_pointer; *cp != '@'; cp++)
7947 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7948 return NULL;
7949
7950 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7951 {
7952 int len = gotrel[j].len;
7953
7954 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7955 {
7956 if (gotrel[j].rel[object_64bit] != 0)
7957 {
7958 int first, second;
7959 char *tmpbuf, *past_reloc;
7960
7961 *rel = gotrel[j].rel[object_64bit];
7962 if (adjust)
7963 *adjust = len;
7964
7965 if (types)
7966 {
7967 if (flag_code != CODE_64BIT)
7968 {
7969 types->bitfield.imm32 = 1;
7970 types->bitfield.disp32 = 1;
7971 }
7972 else
7973 *types = gotrel[j].types64;
7974 }
7975
7976 /* The length of the first part of our input line. */
7977 first = cp - input_line_pointer;
7978
7979 /* The second part goes from after the reloc token until
7980 (and including) an end_of_line char or comma. */
7981 past_reloc = cp + 1 + len;
7982 cp = past_reloc;
7983 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7984 ++cp;
7985 second = cp + 1 - past_reloc;
7986
7987 /* Allocate and copy string. The trailing NUL shouldn't
7988 be necessary, but be safe. */
add39d23 7989 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 7990 memcpy (tmpbuf, input_line_pointer, first);
7991 if (second != 0 && *past_reloc != ' ')
7992 /* Replace the relocation token with ' ', so that
7993 errors like foo@SECLREL321 will be detected. */
7994 tmpbuf[first++] = ' ';
7995 memcpy (tmpbuf + first, past_reloc, second);
7996 tmpbuf[first + second] = '\0';
7997 return tmpbuf;
7998 }
7999
8000 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8001 gotrel[j].str, 1 << (5 + object_64bit));
8002 return NULL;
8003 }
8004 }
8005
8006 /* Might be a symbol version string. Don't as_bad here. */
8007 return NULL;
8008}
8009
8010#endif /* TE_PE */
8011
62ebcb5c 8012bfd_reloc_code_real_type
e3bb37b5 8013x86_cons (expressionS *exp, int size)
f3c180ae 8014{
62ebcb5c
AM		 8015 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8016
ee86248c
JB		 8017 intel_syntax = -intel_syntax;
8018
3c7b9c2c 8019 exp->X_md = 0;
4fa24527 8020 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 8021 {
8022 /* Handle @GOTOFF and the like in an expression. */
8023 char *save;
8024 char *gotfree_input_line;
4a57f2cf 8025 int adjust = 0;
f3c180ae
AM		 8026
8027 save = input_line_pointer;
d258b828 8028 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 8029 if (gotfree_input_line)
8030 input_line_pointer = gotfree_input_line;
8031
8032 expression (exp);
8033
8034 if (gotfree_input_line)
8035 {
8036 /* expression () has merrily parsed up to the end of line,
8037 or a comma - in the wrong buffer. Transfer how far
8038 input_line_pointer has moved to the right buffer. */
8039 input_line_pointer = (save
8040 + (input_line_pointer - gotfree_input_line)
8041 + adjust);
8042 free (gotfree_input_line);
3992d3b7
AM		 8043 if (exp->X_op == O_constant
8044 || exp->X_op == O_absent
8045 || exp->X_op == O_illegal
0398aac5 8046 || exp->X_op == O_register
3992d3b7
AM		 8047 || exp->X_op == O_big)
8048 {
8049 char c = *input_line_pointer;
8050 *input_line_pointer = 0;
8051 as_bad (_("missing or invalid expression `%s'"), save);
8052 *input_line_pointer = c;
8053 }
f3c180ae
AM		 8054 }
8055 }
8056 else
8057 expression (exp);
ee86248c
JB		 8058
8059 intel_syntax = -intel_syntax;
8060
8061 if (intel_syntax)
8062 i386_intel_simplify (exp);
62ebcb5c
AM		 8063
8064 return got_reloc;
f3c180ae 8065}
f3c180ae 8066
9f32dd5b
L		 8067static void
8068signed_cons (int size)
6482c264 8069{
d182319b
JB		 8070 if (flag_code == CODE_64BIT)
8071 cons_sign = 1;
8072 cons (size);
8073 cons_sign = -1;
6482c264
NC		 8074}
8075
d182319b 8076#ifdef TE_PE
6482c264 8077static void
7016a5d5 8078pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 8079{
8080 expressionS exp;
8081
8082 do
8083 {
8084 expression (&exp);
8085 if (exp.X_op == O_symbol)
8086 exp.X_op = O_secrel;
8087
8088 emit_expr (&exp, 4);
8089 }
8090 while (*input_line_pointer++ == ',');
8091
8092 input_line_pointer--;
8093 demand_empty_rest_of_line ();
8094}
6482c264
NC		 8095#endif
8096
43234a1e
L		 8097/* Handle Vector operations. */
8098
8099static char *
8100check_VecOperations (char *op_string, char *op_end)
8101{
8102 const reg_entry *mask;
8103 const char *saved;
8104 char *end_op;
8105
8106 while (*op_string
8107 && (op_end == NULL || op_string < op_end))
8108 {
8109 saved = op_string;
8110 if (*op_string == '{')
8111 {
8112 op_string++;
8113
8114 /* Check broadcasts. */
8115 if (strncmp (op_string, "1to", 3) == 0)
8116 {
8117 int bcst_type;
8118
8119 if (i.broadcast)
8120 goto duplicated_vec_op;
8121
8122 op_string += 3;
8123 if (*op_string == '8')
8124 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 8125 else if (*op_string == '4')
8126 bcst_type = BROADCAST_1TO4;
8127 else if (*op_string == '2')
8128 bcst_type = BROADCAST_1TO2;
43234a1e
L		 8129 else if (*op_string == '1'
8130 && *(op_string+1) == '6')
8131 {
8132 bcst_type = BROADCAST_1TO16;
8133 op_string++;
8134 }
8135 else
8136 {
8137 as_bad (_("Unsupported broadcast: `%s'"), saved);
8138 return NULL;
8139 }
8140 op_string++;
8141
8142 broadcast_op.type = bcst_type;
8143 broadcast_op.operand = this_operand;
8144 i.broadcast = &broadcast_op;
8145 }
8146 /* Check masking operation. */
8147 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8148 {
8149 /* k0 can't be used for write mask. */
8150 if (mask->reg_num == 0)
8151 {
8152 as_bad (_("`%s' can't be used for write mask"),
8153 op_string);
8154 return NULL;
8155 }
8156
8157 if (!i.mask)
8158 {
8159 mask_op.mask = mask;
8160 mask_op.zeroing = 0;
8161 mask_op.operand = this_operand;
8162 i.mask = &mask_op;
8163 }
8164 else
8165 {
8166 if (i.mask->mask)
8167 goto duplicated_vec_op;
8168
8169 i.mask->mask = mask;
8170
8171 /* Only "{z}" is allowed here. No need to check
8172 zeroing mask explicitly. */
8173 if (i.mask->operand != this_operand)
8174 {
8175 as_bad (_("invalid write mask `%s'"), saved);
8176 return NULL;
8177 }
8178 }
8179
8180 op_string = end_op;
8181 }
8182 /* Check zeroing-flag for masking operation. */
8183 else if (*op_string == 'z')
8184 {
8185 if (!i.mask)
8186 {
8187 mask_op.mask = NULL;
8188 mask_op.zeroing = 1;
8189 mask_op.operand = this_operand;
8190 i.mask = &mask_op;
8191 }
8192 else
8193 {
8194 if (i.mask->zeroing)
8195 {
8196 duplicated_vec_op:
8197 as_bad (_("duplicated `%s'"), saved);
8198 return NULL;
8199 }
8200
8201 i.mask->zeroing = 1;
8202
8203 /* Only "{%k}" is allowed here. No need to check mask
8204 register explicitly. */
8205 if (i.mask->operand != this_operand)
8206 {
8207 as_bad (_("invalid zeroing-masking `%s'"),
8208 saved);
8209 return NULL;
8210 }
8211 }
8212
8213 op_string++;
8214 }
8215 else
8216 goto unknown_vec_op;
8217
8218 if (*op_string != '}')
8219 {
8220 as_bad (_("missing `}' in `%s'"), saved);
8221 return NULL;
8222 }
8223 op_string++;
8224 continue;
8225 }
8226 unknown_vec_op:
8227 /* We don't know this one. */
8228 as_bad (_("unknown vector operation: `%s'"), saved);
8229 return NULL;
8230 }
8231
8232 return op_string;
8233}
8234
252b5132 8235static int
70e41ade 8236i386_immediate (char *imm_start)
252b5132
RH		 8237{
8238 char *save_input_line_pointer;
f3c180ae 8239 char *gotfree_input_line;
252b5132 8240 segT exp_seg = 0;
47926f60 8241 expressionS *exp;
40fb9820
L		 8242 i386_operand_type types;
8243
0dfbf9d7 8244 operand_type_set (&types, ~0);
252b5132
RH		 8245
8246 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8247 {
31b2323c
L		 8248 as_bad (_("at most %d immediate operands are allowed"),
8249 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8250 return 0;
8251 }
8252
8253 exp = &im_expressions[i.imm_operands++];
520dc8e8 8254 i.op[this_operand].imms = exp;
252b5132
RH		 8255
8256 if (is_space_char (*imm_start))
8257 ++imm_start;
8258
8259 save_input_line_pointer = input_line_pointer;
8260 input_line_pointer = imm_start;
8261
d258b828 8262 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8263 if (gotfree_input_line)
8264 input_line_pointer = gotfree_input_line;
252b5132
RH		 8265
8266 exp_seg = expression (exp);
8267
83183c0c 8268 SKIP_WHITESPACE ();
43234a1e
L		 8269
8270 /* Handle vector operations. */
8271 if (*input_line_pointer == '{')
8272 {
8273 input_line_pointer = check_VecOperations (input_line_pointer,
8274 NULL);
8275 if (input_line_pointer == NULL)
8276 return 0;
8277 }
8278
252b5132 8279 if (*input_line_pointer)
f3c180ae 8280 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8281
8282 input_line_pointer = save_input_line_pointer;
f3c180ae 8283 if (gotfree_input_line)
ee86248c
JB		 8284 {
8285 free (gotfree_input_line);
8286
8287 if (exp->X_op == O_constant || exp->X_op == O_register)
8288 exp->X_op = O_illegal;
8289 }
8290
8291 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8292}
252b5132 8293
ee86248c
JB		 8294static int
8295i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8296 i386_operand_type types, const char *imm_start)
8297{
8298 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8299 {
313c53d1
L		 8300 if (imm_start)
8301 as_bad (_("missing or invalid immediate expression `%s'"),
8302 imm_start);
3992d3b7 8303 return 0;
252b5132 8304 }
3e73aa7c 8305 else if (exp->X_op == O_constant)
252b5132 8306 {
47926f60 8307 /* Size it properly later. */
40fb9820 8308 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8309 /* If not 64bit, sign extend val. */
8310 if (flag_code != CODE_64BIT
4eed87de
AM		 8311 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8312 exp->X_add_number
8313 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8314 }
4c63da97 8315#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8316 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8317 && exp_seg != absolute_section
47926f60 8318 && exp_seg != text_section
24eab124
AM		 8319 && exp_seg != data_section
8320 && exp_seg != bss_section
8321 && exp_seg != undefined_section
f86103b7 8322 && !bfd_is_com_section (exp_seg))
252b5132 8323 {
d0b47220 8324 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8325 return 0;
8326 }
8327#endif
a841bdf5 8328 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8329 {
313c53d1
L		 8330 if (imm_start)
8331 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8332 return 0;
8333 }
252b5132
RH		 8334 else
8335 {
8336 /* This is an address. The size of the address will be
24eab124 8337 determined later, depending on destination register,
3e73aa7c 8338 suffix, or the default for the section. */
40fb9820
L		 8339 i.types[this_operand].bitfield.imm8 = 1;
8340 i.types[this_operand].bitfield.imm16 = 1;
8341 i.types[this_operand].bitfield.imm32 = 1;
8342 i.types[this_operand].bitfield.imm32s = 1;
8343 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8344 i.types[this_operand] = operand_type_and (i.types[this_operand],
8345 types);
252b5132
RH		 8346 }
8347
8348 return 1;
8349}
8350
551c1ca1 8351static char *
e3bb37b5 8352i386_scale (char *scale)
252b5132 8353{
551c1ca1
AM		 8354 offsetT val;
8355 char *save = input_line_pointer;
252b5132 8356
551c1ca1
AM		 8357 input_line_pointer = scale;
8358 val = get_absolute_expression ();
8359
8360 switch (val)
252b5132 8361 {
551c1ca1 8362 case 1:
252b5132
RH		 8363 i.log2_scale_factor = 0;
8364 break;
551c1ca1 8365 case 2:
252b5132
RH		 8366 i.log2_scale_factor = 1;
8367 break;
551c1ca1 8368 case 4:
252b5132
RH		 8369 i.log2_scale_factor = 2;
8370 break;
551c1ca1 8371 case 8:
252b5132
RH		 8372 i.log2_scale_factor = 3;
8373 break;
8374 default:
a724f0f4
JB		 8375 {
8376 char sep = *input_line_pointer;
8377
8378 *input_line_pointer = '\0';
8379 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8380 scale);
8381 *input_line_pointer = sep;
8382 input_line_pointer = save;
8383 return NULL;
8384 }
252b5132 8385 }
29b0f896 8386 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8387 {
8388 as_warn (_("scale factor of %d without an index register"),
24eab124 8389 1 << i.log2_scale_factor);
252b5132 8390 i.log2_scale_factor = 0;
252b5132 8391 }
551c1ca1
AM		 8392 scale = input_line_pointer;
8393 input_line_pointer = save;
8394 return scale;
252b5132
RH		 8395}
8396
252b5132 8397static int
e3bb37b5 8398i386_displacement (char *disp_start, char *disp_end)
252b5132 8399{
29b0f896 8400 expressionS *exp;
252b5132
RH		 8401 segT exp_seg = 0;
8402 char *save_input_line_pointer;
f3c180ae 8403 char *gotfree_input_line;
40fb9820
L		 8404 int override;
8405 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8406 int ret;
252b5132 8407
31b2323c
L		 8408 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8409 {
8410 as_bad (_("at most %d displacement operands are allowed"),
8411 MAX_MEMORY_OPERANDS);
8412 return 0;
8413 }
8414
0dfbf9d7 8415 operand_type_set (&bigdisp, 0);
40fb9820
L		 8416 if ((i.types[this_operand].bitfield.jumpabsolute)
8417 || (!current_templates->start->opcode_modifier.jump
8418 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8419 {
40fb9820 8420 bigdisp.bitfield.disp32 = 1;
e05278af 8421 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8422 if (flag_code == CODE_64BIT)
8423 {
8424 if (!override)
8425 {
8426 bigdisp.bitfield.disp32s = 1;
8427 bigdisp.bitfield.disp64 = 1;
8428 }
8429 }
8430 else if ((flag_code == CODE_16BIT) ^ override)
8431 {
8432 bigdisp.bitfield.disp32 = 0;
8433 bigdisp.bitfield.disp16 = 1;
8434 }
e05278af
JB		 8435 }
8436 else
8437 {
8438 /* For PC-relative branches, the width of the displacement
8439 is dependent upon data size, not address size. */
e05278af 8440 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8441 if (flag_code == CODE_64BIT)
8442 {
8443 if (override || i.suffix == WORD_MNEM_SUFFIX)
8444 bigdisp.bitfield.disp16 = 1;
8445 else
8446 {
8447 bigdisp.bitfield.disp32 = 1;
8448 bigdisp.bitfield.disp32s = 1;
8449 }
8450 }
8451 else
e05278af
JB		 8452 {
8453 if (!override)
8454 override = (i.suffix == (flag_code != CODE_16BIT
8455 ? WORD_MNEM_SUFFIX
8456 : LONG_MNEM_SUFFIX));
40fb9820
L		 8457 bigdisp.bitfield.disp32 = 1;
8458 if ((flag_code == CODE_16BIT) ^ override)
8459 {
8460 bigdisp.bitfield.disp32 = 0;
8461 bigdisp.bitfield.disp16 = 1;
8462 }
e05278af 8463 }
e05278af 8464 }
c6fb90c8
L		 8465 i.types[this_operand] = operand_type_or (i.types[this_operand],
8466 bigdisp);
252b5132
RH		 8467
8468 exp = &disp_expressions[i.disp_operands];
520dc8e8 8469 i.op[this_operand].disps = exp;
252b5132
RH		 8470 i.disp_operands++;
8471 save_input_line_pointer = input_line_pointer;
8472 input_line_pointer = disp_start;
8473 END_STRING_AND_SAVE (disp_end);
8474
8475#ifndef GCC_ASM_O_HACK
8476#define GCC_ASM_O_HACK 0
8477#endif
8478#if GCC_ASM_O_HACK
8479 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8480 if (i.types[this_operand].bitfield.baseIndex
24eab124 8481 && displacement_string_end[-1] == '+')
252b5132
RH		 8482 {
8483 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8484 constraint within gcc asm statements.
8485 For instance:
8486
8487 #define _set_tssldt_desc(n,addr,limit,type) \
8488 __asm__ __volatile__ ( \
8489 "movw %w2,%0\n\t" \
8490 "movw %w1,2+%0\n\t" \
8491 "rorl $16,%1\n\t" \
8492 "movb %b1,4+%0\n\t" \
8493 "movb %4,5+%0\n\t" \
8494 "movb $0,6+%0\n\t" \
8495 "movb %h1,7+%0\n\t" \
8496 "rorl $16,%1" \
8497 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8498
8499 This works great except that the output assembler ends
8500 up looking a bit weird if it turns out that there is
8501 no offset. You end up producing code that looks like:
8502
8503 #APP
8504 movw $235,(%eax)
8505 movw %dx,2+(%eax)
8506 rorl $16,%edx
8507 movb %dl,4+(%eax)
8508 movb $137,5+(%eax)
8509 movb $0,6+(%eax)
8510 movb %dh,7+(%eax)
8511 rorl $16,%edx
8512 #NO_APP
8513
47926f60 8514 So here we provide the missing zero. */
24eab124
AM		 8515
8516 *displacement_string_end = '0';
252b5132
RH		 8517 }
8518#endif
d258b828 8519 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8520 if (gotfree_input_line)
8521 input_line_pointer = gotfree_input_line;
252b5132 8522
24eab124 8523 exp_seg = expression (exp);
252b5132 8524
636c26b0
AM		 8525 SKIP_WHITESPACE ();
8526 if (*input_line_pointer)
8527 as_bad (_("junk `%s' after expression"), input_line_pointer);
8528#if GCC_ASM_O_HACK
8529 RESTORE_END_STRING (disp_end + 1);
8530#endif
636c26b0 8531 input_line_pointer = save_input_line_pointer;
636c26b0 8532 if (gotfree_input_line)
ee86248c
JB		 8533 {
8534 free (gotfree_input_line);
8535
8536 if (exp->X_op == O_constant || exp->X_op == O_register)
8537 exp->X_op = O_illegal;
8538 }
8539
8540 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8541
8542 RESTORE_END_STRING (disp_end);
8543
8544 return ret;
8545}
8546
8547static int
8548i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8549 i386_operand_type types, const char *disp_start)
8550{
8551 i386_operand_type bigdisp;
8552 int ret = 1;
636c26b0 8553
24eab124
AM		 8554 /* We do this to make sure that the section symbol is in
8555 the symbol table. We will ultimately change the relocation
47926f60 8556 to be relative to the beginning of the section. */
1ae12ab7 8557 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8558 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8559 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8560 {
636c26b0 8561 if (exp->X_op != O_symbol)
3992d3b7 8562 goto inv_disp;
636c26b0 8563
e5cb08ac 8564 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8565 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8566 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8567 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8568 exp->X_op = O_subtract;
8569 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8570 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8571 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8572 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8573 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8574 else
29b0f896 8575 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8576 }
252b5132 8577
3992d3b7
AM		 8578 else if (exp->X_op == O_absent
8579 || exp->X_op == O_illegal
ee86248c 8580 || exp->X_op == O_big)
2daf4fd8 8581 {
3992d3b7
AM		 8582 inv_disp:
8583 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8584 disp_start);
3992d3b7 8585 ret = 0;
2daf4fd8
AM		 8586 }
8587
0e1147d9
L		 8588 else if (flag_code == CODE_64BIT
8589 && !i.prefix[ADDR_PREFIX]
8590 && exp->X_op == O_constant)
8591 {
8592 /* Since displacement is signed extended to 64bit, don't allow
8593 disp32 and turn off disp32s if they are out of range. */
8594 i.types[this_operand].bitfield.disp32 = 0;
8595 if (!fits_in_signed_long (exp->X_add_number))
8596 {
8597 i.types[this_operand].bitfield.disp32s = 0;
8598 if (i.types[this_operand].bitfield.baseindex)
8599 {
8600 as_bad (_("0x%lx out range of signed 32bit displacement"),
8601 (long) exp->X_add_number);
8602 ret = 0;
8603 }
8604 }
8605 }
8606
4c63da97 8607#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8608 else if (exp->X_op != O_constant
8609 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8610 && exp_seg != absolute_section
8611 && exp_seg != text_section
8612 && exp_seg != data_section
8613 && exp_seg != bss_section
8614 && exp_seg != undefined_section
8615 && !bfd_is_com_section (exp_seg))
24eab124 8616 {
d0b47220 8617 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8618 ret = 0;
24eab124 8619 }
252b5132 8620#endif
3956db08 8621
40fb9820
L		 8622 /* Check if this is a displacement only operand. */
8623 bigdisp = i.types[this_operand];
8624 bigdisp.bitfield.disp8 = 0;
8625 bigdisp.bitfield.disp16 = 0;
8626 bigdisp.bitfield.disp32 = 0;
8627 bigdisp.bitfield.disp32s = 0;
8628 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8629 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8630 i.types[this_operand] = operand_type_and (i.types[this_operand],
8631 types);
3956db08 8632
3992d3b7 8633 return ret;
252b5132
RH		 8634}
8635
eecb386c 8636/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8637 Return 1 on success, 0 on a failure. */
8638
252b5132 8639static int
e3bb37b5 8640i386_index_check (const char *operand_string)
252b5132 8641{
fc0763e6 8642 const char *kind = "base/index";
be05d201
L		 8643 enum flag_code addr_mode;
8644
8645 if (i.prefix[ADDR_PREFIX])
8646 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8647 else
8648 {
8649 addr_mode = flag_code;
8650
24eab124 8651#if INFER_ADDR_PREFIX
be05d201
L		 8652 if (i.mem_operands == 0)
8653 {
8654 /* Infer address prefix from the first memory operand. */
8655 const reg_entry *addr_reg = i.base_reg;
8656
8657 if (addr_reg == NULL)
8658 addr_reg = i.index_reg;
eecb386c 8659
be05d201
L		 8660 if (addr_reg)
8661 {
8662 if (addr_reg->reg_num == RegEip
8663 || addr_reg->reg_num == RegEiz
8664 || addr_reg->reg_type.bitfield.reg32)
8665 addr_mode = CODE_32BIT;
8666 else if (flag_code != CODE_64BIT
8667 && addr_reg->reg_type.bitfield.reg16)
8668 addr_mode = CODE_16BIT;
8669
8670 if (addr_mode != flag_code)
8671 {
8672 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8673 i.prefixes += 1;
8674 /* Change the size of any displacement too. At most one
8675 of Disp16 or Disp32 is set.
8676 FIXME. There doesn't seem to be any real need for
8677 separate Disp16 and Disp32 flags. The same goes for
8678 Imm16 and Imm32. Removing them would probably clean
8679 up the code quite a lot. */
8680 if (flag_code != CODE_64BIT
8681 && (i.types[this_operand].bitfield.disp16
8682 || i.types[this_operand].bitfield.disp32))
8683 i.types[this_operand]
8684 = operand_type_xor (i.types[this_operand], disp16_32);
8685 }
8686 }
8687 }
24eab124 8688#endif
be05d201
L		 8689 }
8690
fc0763e6
JB		 8691 if (current_templates->start->opcode_modifier.isstring
8692 && !current_templates->start->opcode_modifier.immext
8693 && (current_templates->end[-1].opcode_modifier.isstring
8694 || i.mem_operands))
8695 {
8696 /* Memory operands of string insns are special in that they only allow
8697 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8698 const reg_entry *expected_reg;
8699 static const char *di_si[][2] =
8700 {
8701 { "esi", "edi" },
8702 { "si", "di" },
8703 { "rsi", "rdi" }
8704 };
8705 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8706
8707 kind = "string address";
8708
8325cc63 8709 if (current_templates->start->opcode_modifier.repprefixok)
fc0763e6
JB		 8710 {
8711 i386_operand_type type = current_templates->end[-1].operand_types[0];
8712
8713 if (!type.bitfield.baseindex
8714 || ((!i.mem_operands != !intel_syntax)
8715 && current_templates->end[-1].operand_types[1]
8716 .bitfield.baseindex))
8717 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8718 expected_reg = hash_find (reg_hash,
8719 di_si[addr_mode][type.bitfield.esseg]);
8720
fc0763e6
JB		 8721 }
8722 else
be05d201 8723 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8724
be05d201
L		 8725 if (i.base_reg != expected_reg
8726 || i.index_reg
fc0763e6 8727 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8728 {
be05d201
L		 8729 /* The second memory operand must have the same size as
8730 the first one. */
8731 if (i.mem_operands
8732 && i.base_reg
8733 && !((addr_mode == CODE_64BIT
8734 && i.base_reg->reg_type.bitfield.reg64)
8735 || (addr_mode == CODE_32BIT
8736 ? i.base_reg->reg_type.bitfield.reg32
8737 : i.base_reg->reg_type.bitfield.reg16)))
8738 goto bad_address;
8739
fc0763e6
JB		 8740 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8741 operand_string,
8742 intel_syntax ? '[' : '(',
8743 register_prefix,
be05d201 8744 expected_reg->reg_name,
fc0763e6 8745 intel_syntax ? ']' : ')');
be05d201 8746 return 1;
fc0763e6 8747 }
be05d201
L		 8748 else
8749 return 1;
8750
8751bad_address:
8752 as_bad (_("`%s' is not a valid %s expression"),
8753 operand_string, kind);
8754 return 0;
3e73aa7c
JH		 8755 }
8756 else
8757 {
be05d201
L		 8758 if (addr_mode != CODE_16BIT)
8759 {
8760 /* 32-bit/64-bit checks. */
8761 if ((i.base_reg
8762 && (addr_mode == CODE_64BIT
8763 ? !i.base_reg->reg_type.bitfield.reg64
8764 : !i.base_reg->reg_type.bitfield.reg32)
8765 && (i.index_reg
8766 || (i.base_reg->reg_num
8767 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8768 || (i.index_reg
8769 && !i.index_reg->reg_type.bitfield.regxmm
8770 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8771 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8772 && ((addr_mode == CODE_64BIT
8773 ? !(i.index_reg->reg_type.bitfield.reg64
8774 || i.index_reg->reg_num == RegRiz)
8775 : !(i.index_reg->reg_type.bitfield.reg32
8776 || i.index_reg->reg_num == RegEiz))
8777 || !i.index_reg->reg_type.bitfield.baseindex)))
8778 goto bad_address;
8178be5b
JB		 8779
8780 /* bndmk, bndldx, and bndstx have special restrictions. */
8781 if (current_templates->start->base_opcode == 0xf30f1b
8782 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
8783 {
8784 /* They cannot use RIP-relative addressing. */
8785 if (i.base_reg && i.base_reg->reg_num == RegRip)
8786 {
8787 as_bad (_("`%s' cannot be used here"), operand_string);
8788 return 0;
8789 }
8790
8791 /* bndldx and bndstx ignore their scale factor. */
8792 if (current_templates->start->base_opcode != 0xf30f1b
8793 && i.log2_scale_factor)
8794 as_warn (_("register scaling is being ignored here"));
8795 }
be05d201
L		 8796 }
8797 else
3e73aa7c 8798 {
be05d201 8799 /* 16-bit checks. */
3e73aa7c 8800 if ((i.base_reg
40fb9820
L		 8801 && (!i.base_reg->reg_type.bitfield.reg16
8802 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8803 || (i.index_reg
40fb9820
L		 8804 && (!i.index_reg->reg_type.bitfield.reg16
8805 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8806 || !(i.base_reg
8807 && i.base_reg->reg_num < 6
8808 && i.index_reg->reg_num >= 6
8809 && i.log2_scale_factor == 0))))
be05d201 8810 goto bad_address;
3e73aa7c
JH		 8811 }
8812 }
be05d201 8813 return 1;
24eab124 8814}
252b5132 8815
43234a1e
L		 8816/* Handle vector immediates. */
8817
8818static int
8819RC_SAE_immediate (const char *imm_start)
8820{
8821 unsigned int match_found, j;
8822 const char *pstr = imm_start;
8823 expressionS *exp;
8824
8825 if (*pstr != '{')
8826 return 0;
8827
8828 pstr++;
8829 match_found = 0;
8830 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8831 {
8832 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8833 {
8834 if (!i.rounding)
8835 {
8836 rc_op.type = RC_NamesTable[j].type;
8837 rc_op.operand = this_operand;
8838 i.rounding = &rc_op;
8839 }
8840 else
8841 {
8842 as_bad (_("duplicated `%s'"), imm_start);
8843 return 0;
8844 }
8845 pstr += RC_NamesTable[j].len;
8846 match_found = 1;
8847 break;
8848 }
8849 }
8850 if (!match_found)
8851 return 0;
8852
8853 if (*pstr++ != '}')
8854 {
8855 as_bad (_("Missing '}': '%s'"), imm_start);
8856 return 0;
8857 }
8858 /* RC/SAE immediate string should contain nothing more. */;
8859 if (*pstr != 0)
8860 {
8861 as_bad (_("Junk after '}': '%s'"), imm_start);
8862 return 0;
8863 }
8864
8865 exp = &im_expressions[i.imm_operands++];
8866 i.op[this_operand].imms = exp;
8867
8868 exp->X_op = O_constant;
8869 exp->X_add_number = 0;
8870 exp->X_add_symbol = (symbolS *) 0;
8871 exp->X_op_symbol = (symbolS *) 0;
8872
8873 i.types[this_operand].bitfield.imm8 = 1;
8874 return 1;
8875}
8876
8325cc63
JB		 8877/* Only string instructions can have a second memory operand, so
8878 reduce current_templates to just those if it contains any. */
8879static int
8880maybe_adjust_templates (void)
8881{
8882 const insn_template *t;
8883
8884 gas_assert (i.mem_operands == 1);
8885
8886 for (t = current_templates->start; t < current_templates->end; ++t)
8887 if (t->opcode_modifier.isstring)
8888 break;
8889
8890 if (t < current_templates->end)
8891 {
8892 static templates aux_templates;
8893 bfd_boolean recheck;
8894
8895 aux_templates.start = t;
8896 for (; t < current_templates->end; ++t)
8897 if (!t->opcode_modifier.isstring)
8898 break;
8899 aux_templates.end = t;
8900
8901 /* Determine whether to re-check the first memory operand. */
8902 recheck = (aux_templates.start != current_templates->start
8903 || t != current_templates->end);
8904
8905 current_templates = &aux_templates;
8906
8907 if (recheck)
8908 {
8909 i.mem_operands = 0;
8910 if (i.memop1_string != NULL
8911 && i386_index_check (i.memop1_string) == 0)
8912 return 0;
8913 i.mem_operands = 1;
8914 }
8915 }
8916
8917 return 1;
8918}
8919
fc0763e6 8920/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8921 on error. */
252b5132 8922
252b5132 8923static int
a7619375 8924i386_att_operand (char *operand_string)
252b5132 8925{
af6bdddf
AM		 8926 const reg_entry *r;
8927 char *end_op;
24eab124 8928 char *op_string = operand_string;
252b5132 8929
24eab124 8930 if (is_space_char (*op_string))
252b5132
RH		 8931 ++op_string;
8932
24eab124 8933 /* We check for an absolute prefix (differentiating,
47926f60 8934 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8935 if (*op_string == ABSOLUTE_PREFIX)
8936 {
8937 ++op_string;
8938 if (is_space_char (*op_string))
8939 ++op_string;
40fb9820 8940 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8941 }
252b5132 8942
47926f60 8943 /* Check if operand is a register. */
4d1bb795 8944 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8945 {
40fb9820
L		 8946 i386_operand_type temp;
8947
24eab124
AM		 8948 /* Check for a segment override by searching for ':' after a
8949 segment register. */
8950 op_string = end_op;
8951 if (is_space_char (*op_string))
8952 ++op_string;
40fb9820
L		 8953 if (*op_string == ':'
8954 && (r->reg_type.bitfield.sreg2
8955 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8956 {
8957 switch (r->reg_num)
8958 {
8959 case 0:
8960 i.seg[i.mem_operands] = &es;
8961 break;
8962 case 1:
8963 i.seg[i.mem_operands] = &cs;
8964 break;
8965 case 2:
8966 i.seg[i.mem_operands] = &ss;
8967 break;
8968 case 3:
8969 i.seg[i.mem_operands] = &ds;
8970 break;
8971 case 4:
8972 i.seg[i.mem_operands] = &fs;
8973 break;
8974 case 5:
8975 i.seg[i.mem_operands] = &gs;
8976 break;
8977 }
252b5132 8978
24eab124 8979 /* Skip the ':' and whitespace. */
252b5132
RH		 8980 ++op_string;
8981 if (is_space_char (*op_string))
24eab124 8982 ++op_string;
252b5132 8983
24eab124
AM		 8984 if (!is_digit_char (*op_string)
8985 && !is_identifier_char (*op_string)
8986 && *op_string != '('
8987 && *op_string != ABSOLUTE_PREFIX)
8988 {
8989 as_bad (_("bad memory operand `%s'"), op_string);
8990 return 0;
8991 }
47926f60 8992 /* Handle case of %es:*foo. */
24eab124
AM		 8993 if (*op_string == ABSOLUTE_PREFIX)
8994 {
8995 ++op_string;
8996 if (is_space_char (*op_string))
8997 ++op_string;
40fb9820 8998 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8999 }
9000 goto do_memory_reference;
9001 }
43234a1e
L		 9002
9003 /* Handle vector operations. */
9004 if (*op_string == '{')
9005 {
9006 op_string = check_VecOperations (op_string, NULL);
9007 if (op_string == NULL)
9008 return 0;
9009 }
9010
24eab124
AM		 9011 if (*op_string)
9012 {
d0b47220 9013 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 9014 return 0;
9015 }
40fb9820
L		 9016 temp = r->reg_type;
9017 temp.bitfield.baseindex = 0;
c6fb90c8
L		 9018 i.types[this_operand] = operand_type_or (i.types[this_operand],
9019 temp);
7d5e4556 9020 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 9021 i.op[this_operand].regs = r;
24eab124
AM		 9022 i.reg_operands++;
9023 }
af6bdddf
AM		 9024 else if (*op_string == REGISTER_PREFIX)
9025 {
9026 as_bad (_("bad register name `%s'"), op_string);
9027 return 0;
9028 }
24eab124 9029 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 9030 {
24eab124 9031 ++op_string;
40fb9820 9032 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 9033 {
d0b47220 9034 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 9035 return 0;
9036 }
9037 if (!i386_immediate (op_string))
9038 return 0;
9039 }
43234a1e
L		 9040 else if (RC_SAE_immediate (operand_string))
9041 {
9042 /* If it is a RC or SAE immediate, do nothing. */
9043 ;
9044 }
24eab124
AM		 9045 else if (is_digit_char (*op_string)
9046 || is_identifier_char (*op_string)
d02603dc 9047 || *op_string == '"'
e5cb08ac 9048 || *op_string == '(')
24eab124 9049 {
47926f60 9050 /* This is a memory reference of some sort. */
af6bdddf 9051 char *base_string;
252b5132 9052
47926f60 9053 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 9054 char *displacement_string_start;
9055 char *displacement_string_end;
43234a1e 9056 char *vop_start;
252b5132 9057
24eab124 9058 do_memory_reference:
8325cc63
JB		 9059 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9060 return 0;
24eab124 9061 if ((i.mem_operands == 1
40fb9820 9062 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 9063 || i.mem_operands == 2)
9064 {
9065 as_bad (_("too many memory references for `%s'"),
9066 current_templates->start->name);
9067 return 0;
9068 }
252b5132 9069
24eab124
AM		 9070 /* Check for base index form. We detect the base index form by
9071 looking for an ')' at the end of the operand, searching
9072 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9073 after the '('. */
af6bdddf 9074 base_string = op_string + strlen (op_string);
c3332e24 9075
43234a1e
L		 9076 /* Handle vector operations. */
9077 vop_start = strchr (op_string, '{');
9078 if (vop_start && vop_start < base_string)
9079 {
9080 if (check_VecOperations (vop_start, base_string) == NULL)
9081 return 0;
9082 base_string = vop_start;
9083 }
9084
af6bdddf
AM		 9085 --base_string;
9086 if (is_space_char (*base_string))
9087 --base_string;
252b5132 9088
47926f60 9089 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 9090 displacement_string_start = op_string;
9091 displacement_string_end = base_string + 1;
252b5132 9092
24eab124
AM		 9093 if (*base_string == ')')
9094 {
af6bdddf 9095 char *temp_string;
24eab124
AM		 9096 unsigned int parens_balanced = 1;
9097 /* We've already checked that the number of left & right ()'s are
47926f60 9098 equal, so this loop will not be infinite. */
24eab124
AM		 9099 do
9100 {
9101 base_string--;
9102 if (*base_string == ')')
9103 parens_balanced++;
9104 if (*base_string == '(')
9105 parens_balanced--;
9106 }
9107 while (parens_balanced);
c3332e24 9108
af6bdddf 9109 temp_string = base_string;
c3332e24 9110
24eab124 9111 /* Skip past '(' and whitespace. */
252b5132
RH		 9112 ++base_string;
9113 if (is_space_char (*base_string))
24eab124 9114 ++base_string;
252b5132 9115
af6bdddf 9116 if (*base_string == ','
4eed87de
AM		 9117 || ((i.base_reg = parse_register (base_string, &end_op))
9118 != NULL))
252b5132 9119 {
af6bdddf 9120 displacement_string_end = temp_string;
252b5132 9121
40fb9820 9122 i.types[this_operand].bitfield.baseindex = 1;
252b5132 9123
af6bdddf 9124 if (i.base_reg)
24eab124 9125 {
24eab124
AM		 9126 base_string = end_op;
9127 if (is_space_char (*base_string))
9128 ++base_string;
af6bdddf
AM		 9129 }
9130
9131 /* There may be an index reg or scale factor here. */
9132 if (*base_string == ',')
9133 {
9134 ++base_string;
9135 if (is_space_char (*base_string))
9136 ++base_string;
9137
4eed87de
AM		 9138 if ((i.index_reg = parse_register (base_string, &end_op))
9139 != NULL)
24eab124 9140 {
af6bdddf 9141 base_string = end_op;
24eab124
AM		 9142 if (is_space_char (*base_string))
9143 ++base_string;
af6bdddf
AM		 9144 if (*base_string == ',')
9145 {
9146 ++base_string;
9147 if (is_space_char (*base_string))
9148 ++base_string;
9149 }
e5cb08ac 9150 else if (*base_string != ')')
af6bdddf 9151 {
4eed87de
AM		 9152 as_bad (_("expecting `,' or `)' "
9153 "after index register in `%s'"),
af6bdddf
AM		 9154 operand_string);
9155 return 0;
9156 }
24eab124 9157 }
af6bdddf 9158 else if (*base_string == REGISTER_PREFIX)
24eab124 9159 {
f76bf5e0
L		 9160 end_op = strchr (base_string, ',');
9161 if (end_op)
9162 *end_op = '\0';
af6bdddf 9163 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 9164 return 0;
9165 }
252b5132 9166
47926f60 9167 /* Check for scale factor. */
551c1ca1 9168 if (*base_string != ')')
af6bdddf 9169 {
551c1ca1
AM		 9170 char *end_scale = i386_scale (base_string);
9171
9172 if (!end_scale)
af6bdddf 9173 return 0;
24eab124 9174
551c1ca1 9175 base_string = end_scale;
af6bdddf
AM		 9176 if (is_space_char (*base_string))
9177 ++base_string;
9178 if (*base_string != ')')
9179 {
4eed87de
AM		 9180 as_bad (_("expecting `)' "
9181 "after scale factor in `%s'"),
af6bdddf
AM		 9182 operand_string);
9183 return 0;
9184 }
9185 }
9186 else if (!i.index_reg)
24eab124 9187 {
4eed87de
AM		 9188 as_bad (_("expecting index register or scale factor "
9189 "after `,'; got '%c'"),
af6bdddf 9190 *base_string);
24eab124
AM		 9191 return 0;
9192 }
9193 }
af6bdddf 9194 else if (*base_string != ')')
24eab124 9195 {
4eed87de
AM		 9196 as_bad (_("expecting `,' or `)' "
9197 "after base register in `%s'"),
af6bdddf 9198 operand_string);
24eab124
AM		 9199 return 0;
9200 }
c3332e24 9201 }
af6bdddf 9202 else if (*base_string == REGISTER_PREFIX)
c3332e24 9203 {
f76bf5e0
L		 9204 end_op = strchr (base_string, ',');
9205 if (end_op)
9206 *end_op = '\0';
af6bdddf 9207 as_bad (_("bad register name `%s'"), base_string);
24eab124 9208 return 0;
c3332e24 9209 }
24eab124
AM		 9210 }
9211
9212 /* If there's an expression beginning the operand, parse it,
9213 assuming displacement_string_start and
9214 displacement_string_end are meaningful. */
9215 if (displacement_string_start != displacement_string_end)
9216 {
9217 if (!i386_displacement (displacement_string_start,
9218 displacement_string_end))
9219 return 0;
9220 }
9221
9222 /* Special case for (%dx) while doing input/output op. */
9223 if (i.base_reg
0dfbf9d7
L		 9224 && operand_type_equal (&i.base_reg->reg_type,
9225 &reg16_inoutportreg)
24eab124
AM		 9226 && i.index_reg == 0
9227 && i.log2_scale_factor == 0
9228 && i.seg[i.mem_operands] == 0
40fb9820 9229 && !operand_type_check (i.types[this_operand], disp))
24eab124 9230 {
65da13b5 9231 i.types[this_operand] = inoutportreg;
24eab124
AM		 9232 return 1;
9233 }
9234
eecb386c
AM		 9235 if (i386_index_check (operand_string) == 0)
9236 return 0;
5c07affc 9237 i.types[this_operand].bitfield.mem = 1;
8325cc63
JB		 9238 if (i.mem_operands == 0)
9239 i.memop1_string = xstrdup (operand_string);
24eab124
AM		 9240 i.mem_operands++;
9241 }
9242 else
ce8a8b2f
AM		 9243 {
9244 /* It's not a memory operand; argh! */
24eab124
AM		 9245 as_bad (_("invalid char %s beginning operand %d `%s'"),
9246 output_invalid (*op_string),
9247 this_operand + 1,
9248 op_string);
9249 return 0;
9250 }
47926f60 9251 return 1; /* Normal return. */
252b5132
RH		 9252}
9253\f
fa94de6b
RM		 9254/* Calculate the maximum variable size (i.e., excluding fr_fix)
9255 that an rs_machine_dependent frag may reach. */
9256
9257unsigned int
9258i386_frag_max_var (fragS *frag)
9259{
9260 /* The only relaxable frags are for jumps.
9261 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9262 gas_assert (frag->fr_type == rs_machine_dependent);
9263 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9264}
9265
b084df0b
L		 9266#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9267static int
8dcea932 9268elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 9269{
9270 /* STT_GNU_IFUNC symbol must go through PLT. */
9271 if ((symbol_get_bfdsym (fr_symbol)->flags
9272 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9273 return 0;
9274
9275 if (!S_IS_EXTERNAL (fr_symbol))
9276 /* Symbol may be weak or local. */
9277 return !S_IS_WEAK (fr_symbol);
9278
8dcea932
L		 9279 /* Global symbols with non-default visibility can't be preempted. */
9280 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9281 return 1;
9282
9283 if (fr_var != NO_RELOC)
9284 switch ((enum bfd_reloc_code_real) fr_var)
9285 {
9286 case BFD_RELOC_386_PLT32:
9287 case BFD_RELOC_X86_64_PLT32:
33eaf5de 9288 /* Symbol with PLT relocation may be preempted. */
8dcea932
L		 9289 return 0;
9290 default:
9291 abort ();
9292 }
9293
b084df0b
L		 9294 /* Global symbols with default visibility in a shared library may be
9295 preempted by another definition. */
8dcea932 9296 return !shared;
b084df0b
L		 9297}
9298#endif
9299
ee7fcc42
AM		 9300/* md_estimate_size_before_relax()
9301
9302 Called just before relax() for rs_machine_dependent frags. The x86
9303 assembler uses these frags to handle variable size jump
9304 instructions.
9305
9306 Any symbol that is now undefined will not become defined.
9307 Return the correct fr_subtype in the frag.
9308 Return the initial "guess for variable size of frag" to caller.
9309 The guess is actually the growth beyond the fixed part. Whatever
9310 we do to grow the fixed or variable part contributes to our
9311 returned value. */
9312
252b5132 9313int
7016a5d5 9314md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9315{
252b5132 9316 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9317 check for un-relaxable symbols. On an ELF system, we can't relax
9318 an externally visible symbol, because it may be overridden by a
9319 shared library. */
9320 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9321#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9322 || (IS_ELF
8dcea932
L		 9323 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9324 fragP->fr_var))
fbeb56a4
DK		 9325#endif
9326#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9327 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9328 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9329#endif
9330 )
252b5132 9331 {
b98ef147
AM		 9332 /* Symbol is undefined in this segment, or we need to keep a
9333 reloc so that weak symbols can be overridden. */
9334 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9335 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9336 unsigned char *opcode;
9337 int old_fr_fix;
f6af82bd 9338
ee7fcc42 9339 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9340 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9341 else if (size == 2)
f6af82bd
AM		 9342 reloc_type = BFD_RELOC_16_PCREL;
9343 else
9344 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9345
ee7fcc42
AM		 9346 old_fr_fix = fragP->fr_fix;
9347 opcode = (unsigned char *) fragP->fr_opcode;
9348
fddf5b5b 9349 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9350 {
fddf5b5b
AM		 9351 case UNCOND_JUMP:
9352 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9353 opcode[0] = 0xe9;
252b5132 9354 fragP->fr_fix += size;
062cd5e7
AS		 9355 fix_new (fragP, old_fr_fix, size,
9356 fragP->fr_symbol,
9357 fragP->fr_offset, 1,
9358 reloc_type);
252b5132
RH		 9359 break;
9360
fddf5b5b 9361 case COND_JUMP86:
412167cb
AM		 9362 if (size == 2
9363 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9364 {
9365 /* Negate the condition, and branch past an
9366 unconditional jump. */
9367 opcode[0] ^= 1;
9368 opcode[1] = 3;
9369 /* Insert an unconditional jump. */
9370 opcode[2] = 0xe9;
9371 /* We added two extra opcode bytes, and have a two byte
9372 offset. */
9373 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9374 fix_new (fragP, old_fr_fix + 2, 2,
9375 fragP->fr_symbol,
9376 fragP->fr_offset, 1,
9377 reloc_type);
fddf5b5b
AM		 9378 break;
9379 }
9380 /* Fall through. */
9381
9382 case COND_JUMP:
412167cb
AM		 9383 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9384 {
3e02c1cc
AM		 9385 fixS *fixP;
9386
412167cb 9387 fragP->fr_fix += 1;
3e02c1cc
AM		 9388 fixP = fix_new (fragP, old_fr_fix, 1,
9389 fragP->fr_symbol,
9390 fragP->fr_offset, 1,
9391 BFD_RELOC_8_PCREL);
9392 fixP->fx_signed = 1;
412167cb
AM		 9393 break;
9394 }
93c2a809 9395
24eab124 9396 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9397 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9398 opcode[1] = opcode[0] + 0x10;
f6af82bd 9399 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9400 /* We've added an opcode byte. */
9401 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9402 fix_new (fragP, old_fr_fix + 1, size,
9403 fragP->fr_symbol,
9404 fragP->fr_offset, 1,
9405 reloc_type);
252b5132 9406 break;
fddf5b5b
AM		 9407
9408 default:
9409 BAD_CASE (fragP->fr_subtype);
9410 break;
252b5132
RH		 9411 }
9412 frag_wane (fragP);
ee7fcc42 9413 return fragP->fr_fix - old_fr_fix;
252b5132 9414 }
93c2a809 9415
93c2a809
AM		 9416 /* Guess size depending on current relax state. Initially the relax
9417 state will correspond to a short jump and we return 1, because
9418 the variable part of the frag (the branch offset) is one byte
9419 long. However, we can relax a section more than once and in that
9420 case we must either set fr_subtype back to the unrelaxed state,
9421 or return the value for the appropriate branch. */
9422 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9423}
9424
47926f60
KH		 9425/* Called after relax() is finished.
9426
9427 In: Address of frag.
9428 fr_type == rs_machine_dependent.
9429 fr_subtype is what the address relaxed to.
9430
9431 Out: Any fixSs and constants are set up.
9432 Caller will turn frag into a ".space 0". */
9433
252b5132 9434void
7016a5d5
TG		 9435md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9436 fragS *fragP)
252b5132 9437{
29b0f896 9438 unsigned char *opcode;
252b5132 9439 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9440 offsetT target_address;
9441 offsetT opcode_address;
252b5132 9442 unsigned int extension = 0;
847f7ad4 9443 offsetT displacement_from_opcode_start;
252b5132
RH		 9444
9445 opcode = (unsigned char *) fragP->fr_opcode;
9446
47926f60 9447 /* Address we want to reach in file space. */
252b5132 9448 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9449
47926f60 9450 /* Address opcode resides at in file space. */
252b5132
RH		 9451 opcode_address = fragP->fr_address + fragP->fr_fix;
9452
47926f60 9453 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9454 displacement_from_opcode_start = target_address - opcode_address;
9455
fddf5b5b 9456 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9457 {
47926f60
KH		 9458 /* Don't have to change opcode. */
9459 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9460 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9461 }
9462 else
9463 {
9464 if (no_cond_jump_promotion
9465 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9466 as_warn_where (fragP->fr_file, fragP->fr_line,
9467 _("long jump required"));
252b5132 9468
fddf5b5b
AM		 9469 switch (fragP->fr_subtype)
9470 {
9471 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9472 extension = 4; /* 1 opcode + 4 displacement */
9473 opcode[0] = 0xe9;
9474 where_to_put_displacement = &opcode[1];
9475 break;
252b5132 9476
fddf5b5b
AM		 9477 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9478 extension = 2; /* 1 opcode + 2 displacement */
9479 opcode[0] = 0xe9;
9480 where_to_put_displacement = &opcode[1];
9481 break;
252b5132 9482
fddf5b5b
AM		 9483 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9484 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9485 extension = 5; /* 2 opcode + 4 displacement */
9486 opcode[1] = opcode[0] + 0x10;
9487 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9488 where_to_put_displacement = &opcode[2];
9489 break;
252b5132 9490
fddf5b5b
AM		 9491 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9492 extension = 3; /* 2 opcode + 2 displacement */
9493 opcode[1] = opcode[0] + 0x10;
9494 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9495 where_to_put_displacement = &opcode[2];
9496 break;
252b5132 9497
fddf5b5b
AM		 9498 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9499 extension = 4;
9500 opcode[0] ^= 1;
9501 opcode[1] = 3;
9502 opcode[2] = 0xe9;
9503 where_to_put_displacement = &opcode[3];
9504 break;
9505
9506 default:
9507 BAD_CASE (fragP->fr_subtype);
9508 break;
9509 }
252b5132 9510 }
fddf5b5b 9511
7b81dfbb
AJ		 9512 /* If size if less then four we are sure that the operand fits,
9513 but if it's 4, then it could be that the displacement is larger
9514 then -/+ 2GB. */
9515 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9516 && object_64bit
9517 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9518 + ((addressT) 1 << 31))
9519 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9520 {
9521 as_bad_where (fragP->fr_file, fragP->fr_line,
9522 _("jump target out of range"));
9523 /* Make us emit 0. */
9524 displacement_from_opcode_start = extension;
9525 }
47926f60 9526 /* Now put displacement after opcode. */
252b5132
RH		 9527 md_number_to_chars ((char *) where_to_put_displacement,
9528 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9529 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9530 fragP->fr_fix += extension;
9531}
9532\f
7016a5d5 9533/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9534 by our caller that we have all the info we need to fix it up.
9535
7016a5d5
TG		 9536 Parameter valP is the pointer to the value of the bits.
9537
252b5132
RH		 9538 On the 386, immediates, displacements, and data pointers are all in
9539 the same (little-endian) format, so we don't need to care about which
9540 we are handling. */
9541
94f592af 9542void
7016a5d5 9543md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9544{
94f592af 9545 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9546 valueT value = *valP;
252b5132 9547
f86103b7 9548#if !defined (TE_Mach)
93382f6d
AM		 9549 if (fixP->fx_pcrel)
9550 {
9551 switch (fixP->fx_r_type)
9552 {
5865bb77
ILT		 9553 default:
9554 break;
9555
d6ab8113
JB		 9556 case BFD_RELOC_64:
9557 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9558 break;
93382f6d 9559 case BFD_RELOC_32:
ae8887b5 9560 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9561 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9562 break;
9563 case BFD_RELOC_16:
9564 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9565 break;
9566 case BFD_RELOC_8:
9567 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9568 break;
9569 }
9570 }
252b5132 9571
a161fe53 9572 if (fixP->fx_addsy != NULL
31312f95 9573 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9574 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9575 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9576 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9577 && !use_rela_relocations)
252b5132 9578 {
31312f95
AM		 9579 /* This is a hack. There should be a better way to handle this.
9580 This covers for the fact that bfd_install_relocation will
9581 subtract the current location (for partial_inplace, PC relative
9582 relocations); see more below. */
252b5132 9583#ifndef OBJ_AOUT
718ddfc0 9584 if (IS_ELF
252b5132
RH		 9585#ifdef TE_PE
9586 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9587#endif
9588 )
9589 value += fixP->fx_where + fixP->fx_frag->fr_address;
9590#endif
9591#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9592 if (IS_ELF)
252b5132 9593 {
6539b54b 9594 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9595
6539b54b 9596 if ((sym_seg == seg
2f66722d 9597 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9598 && sym_seg != absolute_section))
af65af87 9599 && !generic_force_reloc (fixP))
2f66722d
AM		 9600 {
9601 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9602 bfd_install_relocation subtracts them out again. I think
9603 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9604 it. FIXME. */
9605 value += fixP->fx_where + fixP->fx_frag->fr_address;
9606 }
252b5132
RH		 9607 }
9608#endif
9609#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9610 /* For some reason, the PE format does not store a
9611 section address offset for a PC relative symbol. */
9612 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9613 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9614 value += md_pcrel_from (fixP);
9615#endif
9616 }
fbeb56a4 9617#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9618 if (fixP->fx_addsy != NULL
9619 && S_IS_WEAK (fixP->fx_addsy)
9620 /* PR 16858: Do not modify weak function references. */
9621 && ! fixP->fx_pcrel)
fbeb56a4 9622 {
296a8689
NC		 9623#if !defined (TE_PEP)
9624 /* For x86 PE weak function symbols are neither PC-relative
9625 nor do they set S_IS_FUNCTION. So the only reliable way
9626 to detect them is to check the flags of their containing
9627 section. */
9628 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9629 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9630 ;
9631 else
9632#endif
fbeb56a4
DK		 9633 value -= S_GET_VALUE (fixP->fx_addsy);
9634 }
9635#endif
252b5132
RH		 9636
9637 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9638 and we must not disappoint it. */
252b5132 9639#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9640 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9641 switch (fixP->fx_r_type)
9642 {
9643 case BFD_RELOC_386_PLT32:
3e73aa7c 9644 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9645 /* Make the jump instruction point to the address of the operand. At
9646 runtime we merely add the offset to the actual PLT entry. */
9647 value = -4;
9648 break;
31312f95 9649
13ae64f3
JJ		 9650 case BFD_RELOC_386_TLS_GD:
9651 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9652 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9653 case BFD_RELOC_386_TLS_IE:
9654 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9655 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9656 case BFD_RELOC_X86_64_TLSGD:
9657 case BFD_RELOC_X86_64_TLSLD:
9658 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9659 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9660 value = 0; /* Fully resolved at runtime. No addend. */
9661 /* Fallthrough */
9662 case BFD_RELOC_386_TLS_LE:
9663 case BFD_RELOC_386_TLS_LDO_32:
9664 case BFD_RELOC_386_TLS_LE_32:
9665 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9666 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9667 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9668 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9669 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9670 break;
9671
67a4f2b7
AO		 9672 case BFD_RELOC_386_TLS_DESC_CALL:
9673 case BFD_RELOC_X86_64_TLSDESC_CALL:
9674 value = 0; /* Fully resolved at runtime. No addend. */
9675 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9676 fixP->fx_done = 0;
9677 return;
9678
47926f60
KH		 9679 case BFD_RELOC_VTABLE_INHERIT:
9680 case BFD_RELOC_VTABLE_ENTRY:
9681 fixP->fx_done = 0;
94f592af 9682 return;
47926f60
KH		 9683
9684 default:
9685 break;
9686 }
9687#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9688 *valP = value;
f86103b7 9689#endif /* !defined (TE_Mach) */
3e73aa7c 9690
3e73aa7c 9691 /* Are we finished with this relocation now? */
c6682705 9692 if (fixP->fx_addsy == NULL)
3e73aa7c 9693 fixP->fx_done = 1;
fbeb56a4
DK		 9694#if defined (OBJ_COFF) && defined (TE_PE)
9695 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9696 {
9697 fixP->fx_done = 0;
9698 /* Remember value for tc_gen_reloc. */
9699 fixP->fx_addnumber = value;
9700 /* Clear out the frag for now. */
9701 value = 0;
9702 }
9703#endif
3e73aa7c
JH		 9704 else if (use_rela_relocations)
9705 {
9706 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9707 /* Remember value for tc_gen_reloc. */
9708 fixP->fx_addnumber = value;
3e73aa7c
JH		 9709 value = 0;
9710 }
f86103b7 9711
94f592af 9712 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9713}
252b5132 9714\f
6d4af3c2 9715const char *
499ac353 9716md_atof (int type, char *litP, int *sizeP)
252b5132 9717{
499ac353
NC		 9718 /* This outputs the LITTLENUMs in REVERSE order;
9719 in accord with the bigendian 386. */
9720 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9721}
9722\f
2d545b82 9723static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9724
252b5132 9725static char *
e3bb37b5 9726output_invalid (int c)
252b5132 9727{
3882b010 9728 if (ISPRINT (c))
f9f21a03
L		 9729 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9730 "'%c'", c);
252b5132 9731 else
f9f21a03 9732 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9733 "(0x%x)", (unsigned char) c);
252b5132
RH		 9734 return output_invalid_buf;
9735}
9736
af6bdddf 9737/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9738
9739static const reg_entry *
4d1bb795 9740parse_real_register (char *reg_string, char **end_op)
252b5132 9741{
af6bdddf
AM		 9742 char *s = reg_string;
9743 char *p;
252b5132
RH		 9744 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9745 const reg_entry *r;
9746
9747 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9748 if (*s == REGISTER_PREFIX)
9749 ++s;
9750
9751 if (is_space_char (*s))
9752 ++s;
9753
9754 p = reg_name_given;
af6bdddf 9755 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9756 {
9757 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9758 return (const reg_entry *) NULL;
9759 s++;
252b5132
RH		 9760 }
9761
6588847e
DN		 9762 /* For naked regs, make sure that we are not dealing with an identifier.
9763 This prevents confusing an identifier like `eax_var' with register
9764 `eax'. */
9765 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9766 return (const reg_entry *) NULL;
9767
af6bdddf 9768 *end_op = s;
252b5132
RH		 9769
9770 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9771
5f47d35b 9772 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9773 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9774 {
5f47d35b
AM		 9775 if (is_space_char (*s))
9776 ++s;
9777 if (*s == '(')
9778 {
af6bdddf 9779 ++s;
5f47d35b
AM		 9780 if (is_space_char (*s))
9781 ++s;
9782 if (*s >= '0' && *s <= '7')
9783 {
db557034 9784 int fpr = *s - '0';
af6bdddf 9785 ++s;
5f47d35b
AM		 9786 if (is_space_char (*s))
9787 ++s;
9788 if (*s == ')')
9789 {
9790 *end_op = s + 1;
1e9cc1c2 9791 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9792 know (r);
9793 return r + fpr;
5f47d35b 9794 }
5f47d35b 9795 }
47926f60 9796 /* We have "%st(" then garbage. */
5f47d35b
AM		 9797 return (const reg_entry *) NULL;
9798 }
9799 }
9800
a60de03c
JB		 9801 if (r == NULL || allow_pseudo_reg)
9802 return r;
9803
0dfbf9d7 9804 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9805 return (const reg_entry *) NULL;
9806
192dc9c6
JB		 9807 if ((r->reg_type.bitfield.reg32
9808 || r->reg_type.bitfield.sreg3
9809 || r->reg_type.bitfield.control
9810 || r->reg_type.bitfield.debug
9811 || r->reg_type.bitfield.test)
9812 && !cpu_arch_flags.bitfield.cpui386)
9813 return (const reg_entry *) NULL;
9814
309d3373
JB		 9815 if (r->reg_type.bitfield.floatreg
9816 && !cpu_arch_flags.bitfield.cpu8087
9817 && !cpu_arch_flags.bitfield.cpu287
9818 && !cpu_arch_flags.bitfield.cpu387)
9819 return (const reg_entry *) NULL;
9820
1848e567 9821 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
192dc9c6
JB		 9822 return (const reg_entry *) NULL;
9823
1848e567 9824 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpuregxmm)
192dc9c6
JB		 9825 return (const reg_entry *) NULL;
9826
1848e567 9827 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuregymm)
40f12533
L		 9828 return (const reg_entry *) NULL;
9829
1848e567
L		 9830 if (r->reg_type.bitfield.regzmm && !cpu_arch_flags.bitfield.cpuregzmm)
9831 return (const reg_entry *) NULL;
9832
9833 if (r->reg_type.bitfield.regmask
9834 && !cpu_arch_flags.bitfield.cpuregmask)
43234a1e
L		 9835 return (const reg_entry *) NULL;
9836
db51cc60 9837 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9838 if (!allow_index_reg
db51cc60
L		 9839 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9840 return (const reg_entry *) NULL;
9841
43234a1e
L		 9842 /* Upper 16 vector register is only available with VREX in 64bit
9843 mode. */
9844 if ((r->reg_flags & RegVRex))
9845 {
86fa6981
L		 9846 if (i.vec_encoding == vex_encoding_default)
9847 i.vec_encoding = vex_encoding_evex;
9848
43234a1e 9849 if (!cpu_arch_flags.bitfield.cpuvrex
86fa6981 9850 || i.vec_encoding != vex_encoding_evex
43234a1e
L		 9851 || flag_code != CODE_64BIT)
9852 return (const reg_entry *) NULL;
43234a1e
L		 9853 }
9854
a60de03c
JB		 9855 if (((r->reg_flags & (RegRex64 | RegRex))
9856 || r->reg_type.bitfield.reg64)
40fb9820 9857 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9858 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9859 && flag_code != CODE_64BIT)
20f0a1fc 9860 return (const reg_entry *) NULL;
1ae00879 9861
b7240065
JB		 9862 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9863 return (const reg_entry *) NULL;
9864
252b5132
RH		 9865 return r;
9866}
4d1bb795
JB		 9867
9868/* REG_STRING starts *before* REGISTER_PREFIX. */
9869
9870static const reg_entry *
9871parse_register (char *reg_string, char **end_op)
9872{
9873 const reg_entry *r;
9874
9875 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9876 r = parse_real_register (reg_string, end_op);
9877 else
9878 r = NULL;
9879 if (!r)
9880 {
9881 char *save = input_line_pointer;
9882 char c;
9883 symbolS *symbolP;
9884
9885 input_line_pointer = reg_string;
d02603dc 9886 c = get_symbol_name (&reg_string);
4d1bb795
JB		 9887 symbolP = symbol_find (reg_string);
9888 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9889 {
9890 const expressionS *e = symbol_get_value_expression (symbolP);
9891
0398aac5 9892 know (e->X_op == O_register);
4eed87de 9893 know (e->X_add_number >= 0
c3fe08fa 9894 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9895 r = i386_regtab + e->X_add_number;
d3bb6b49 9896 if ((r->reg_flags & RegVRex))
86fa6981 9897 i.vec_encoding = vex_encoding_evex;
4d1bb795
JB		 9898 *end_op = input_line_pointer;
9899 }
9900 *input_line_pointer = c;
9901 input_line_pointer = save;
9902 }
9903 return r;
9904}
9905
9906int
9907i386_parse_name (char *name, expressionS *e, char *nextcharP)
9908{
9909 const reg_entry *r;
9910 char *end = input_line_pointer;
9911
9912 *end = *nextcharP;
9913 r = parse_register (name, &input_line_pointer);
9914 if (r && end <= input_line_pointer)
9915 {
9916 *nextcharP = *input_line_pointer;
9917 *input_line_pointer = 0;
9918 e->X_op = O_register;
9919 e->X_add_number = r - i386_regtab;
9920 return 1;
9921 }
9922 input_line_pointer = end;
9923 *end = 0;
ee86248c 9924 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9925}
9926
9927void
9928md_operand (expressionS *e)
9929{
ee86248c
JB		 9930 char *end;
9931 const reg_entry *r;
4d1bb795 9932
ee86248c
JB		 9933 switch (*input_line_pointer)
9934 {
9935 case REGISTER_PREFIX:
9936 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9937 if (r)
9938 {
9939 e->X_op = O_register;
9940 e->X_add_number = r - i386_regtab;
9941 input_line_pointer = end;
9942 }
ee86248c
JB		 9943 break;
9944
9945 case '[':
9c2799c2 9946 gas_assert (intel_syntax);
ee86248c
JB		 9947 end = input_line_pointer++;
9948 expression (e);
9949 if (*input_line_pointer == ']')
9950 {
9951 ++input_line_pointer;
9952 e->X_op_symbol = make_expr_symbol (e);
9953 e->X_add_symbol = NULL;
9954 e->X_add_number = 0;
9955 e->X_op = O_index;
9956 }
9957 else
9958 {
9959 e->X_op = O_absent;
9960 input_line_pointer = end;
9961 }
9962 break;
4d1bb795
JB		 9963 }
9964}
9965
252b5132 9966\f
4cc782b5 9967#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9968const char *md_shortopts = "kVQ:sqn";
252b5132 9969#else
12b55ccc 9970const char *md_shortopts = "qn";
252b5132 9971#endif
6e0b89ee 9972
3e73aa7c 9973#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9974#define OPTION_64 (OPTION_MD_BASE + 1)
9975#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9976#define OPTION_MARCH (OPTION_MD_BASE + 3)
9977#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9978#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9979#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9980#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9981#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9982#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9983#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9984#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9985#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9986#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9987#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9988#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9989#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9990#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9991#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 9992#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9993#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 9994#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 9995#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9996#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 9997#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
0cb4071e 9998#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
b3b91714 9999
99ad8390
NC		 10000struct option md_longopts[] =
10001{
3e73aa7c 10002 {"32", no_argument, NULL, OPTION_32},
321098a5 10003#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10004 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 10005 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 10006#endif
10007#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10008 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 10009 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 10010#endif
b3b91714 10011 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 10012 {"march", required_argument, NULL, OPTION_MARCH},
10013 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 10014 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10015 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10016 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10017 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10018 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 10019 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 10020 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 10021 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 10022 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 10023 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 10024 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10025 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 10026# if defined (TE_PE) || defined (TE_PEP)
10027 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10028#endif
d1982f93 10029 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 10030 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 10031 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 10032 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 10033 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10034 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 10035 {NULL, no_argument, NULL, 0}
10036};
10037size_t md_longopts_size = sizeof (md_longopts);
10038
10039int
17b9d67d 10040md_parse_option (int c, const char *arg)
252b5132 10041{
91d6fa6a 10042 unsigned int j;
293f5f65 10043 char *arch, *next, *saved;
9103f4f4 10044
252b5132
RH		 10045 switch (c)
10046 {
12b55ccc
L		 10047 case 'n':
10048 optimize_align_code = 0;
10049 break;
10050
a38cf1db
AM		 10051 case 'q':
10052 quiet_warnings = 1;
252b5132
RH		 10053 break;
10054
10055#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 10056 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10057 should be emitted or not. FIXME: Not implemented. */
10058 case 'Q':
252b5132
RH		 10059 break;
10060
10061 /* -V: SVR4 argument to print version ID. */
10062 case 'V':
10063 print_version_id ();
10064 break;
10065
a38cf1db
AM		 10066 /* -k: Ignore for FreeBSD compatibility. */
10067 case 'k':
252b5132 10068 break;
4cc782b5
ILT		 10069
10070 case 's':
10071 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 10072 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 10073 break;
8dcea932
L		 10074
10075 case OPTION_MSHARED:
10076 shared = 1;
10077 break;
99ad8390 10078#endif
321098a5 10079#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10080 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 10081 case OPTION_64:
10082 {
10083 const char **list, **l;
10084
3e73aa7c
JH		 10085 list = bfd_target_list ();
10086 for (l = list; *l != NULL; l++)
8620418b 10087 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 10088 || strcmp (*l, "coff-x86-64") == 0
10089 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 10090 || strcmp (*l, "pei-x86-64") == 0
10091 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 10092 {
10093 default_arch = "x86_64";
10094 break;
10095 }
3e73aa7c 10096 if (*l == NULL)
2b5d6a91 10097 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 10098 free (list);
10099 }
10100 break;
10101#endif
252b5132 10102
351f65ca 10103#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10104 case OPTION_X32:
351f65ca
L		 10105 if (IS_ELF)
10106 {
10107 const char **list, **l;
10108
10109 list = bfd_target_list ();
10110 for (l = list; *l != NULL; l++)
10111 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10112 {
10113 default_arch = "x86_64:32";
10114 break;
10115 }
10116 if (*l == NULL)
2b5d6a91 10117 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 10118 free (list);
10119 }
10120 else
10121 as_fatal (_("32bit x86_64 is only supported for ELF"));
10122 break;
10123#endif
10124
6e0b89ee
AM		 10125 case OPTION_32:
10126 default_arch = "i386";
10127 break;
10128
b3b91714
AM		 10129 case OPTION_DIVIDE:
10130#ifdef SVR4_COMMENT_CHARS
10131 {
10132 char *n, *t;
10133 const char *s;
10134
add39d23 10135 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 10136 t = n;
10137 for (s = i386_comment_chars; *s != '\0'; s++)
10138 if (*s != '/')
10139 *t++ = *s;
10140 *t = '\0';
10141 i386_comment_chars = n;
10142 }
10143#endif
10144 break;
10145
9103f4f4 10146 case OPTION_MARCH:
293f5f65
L		 10147 saved = xstrdup (arg);
10148 arch = saved;
10149 /* Allow -march=+nosse. */
10150 if (*arch == '+')
10151 arch++;
6305a203 10152 do
9103f4f4 10153 {
6305a203 10154 if (*arch == '.')
2b5d6a91 10155 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10156 next = strchr (arch, '+');
10157 if (next)
10158 *next++ = '\0';
91d6fa6a 10159 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10160 {
91d6fa6a 10161 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 10162 {
6305a203 10163 /* Processor. */
1ded5609
JB		 10164 if (! cpu_arch[j].flags.bitfield.cpui386)
10165 continue;
10166
91d6fa6a 10167 cpu_arch_name = cpu_arch[j].name;
6305a203 10168 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 10169 cpu_arch_flags = cpu_arch[j].flags;
10170 cpu_arch_isa = cpu_arch[j].type;
10171 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 10172 if (!cpu_arch_tune_set)
10173 {
10174 cpu_arch_tune = cpu_arch_isa;
10175 cpu_arch_tune_flags = cpu_arch_isa_flags;
10176 }
10177 break;
10178 }
91d6fa6a
NC		 10179 else if (*cpu_arch [j].name == '.'
10180 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203 10181 {
33eaf5de 10182 /* ISA extension. */
6305a203 10183 i386_cpu_flags flags;
309d3373 10184
293f5f65
L		 10185 flags = cpu_flags_or (cpu_arch_flags,
10186 cpu_arch[j].flags);
81486035 10187
5b64d091 10188 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 10189 {
10190 if (cpu_sub_arch_name)
10191 {
10192 char *name = cpu_sub_arch_name;
10193 cpu_sub_arch_name = concat (name,
91d6fa6a 10194 cpu_arch[j].name,
1bf57e9f 10195 (const char *) NULL);
6305a203
L		 10196 free (name);
10197 }
10198 else
91d6fa6a 10199 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 10200 cpu_arch_flags = flags;
a586129e 10201 cpu_arch_isa_flags = flags;
6305a203
L		 10202 }
10203 break;
ccc9c027 10204 }
9103f4f4 10205 }
6305a203 10206
293f5f65
L		 10207 if (j >= ARRAY_SIZE (cpu_arch))
10208 {
33eaf5de 10209 /* Disable an ISA extension. */
293f5f65
L		 10210 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10211 if (strcmp (arch, cpu_noarch [j].name) == 0)
10212 {
10213 i386_cpu_flags flags;
10214
10215 flags = cpu_flags_and_not (cpu_arch_flags,
10216 cpu_noarch[j].flags);
10217 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10218 {
10219 if (cpu_sub_arch_name)
10220 {
10221 char *name = cpu_sub_arch_name;
10222 cpu_sub_arch_name = concat (arch,
10223 (const char *) NULL);
10224 free (name);
10225 }
10226 else
10227 cpu_sub_arch_name = xstrdup (arch);
10228 cpu_arch_flags = flags;
10229 cpu_arch_isa_flags = flags;
10230 }
10231 break;
10232 }
10233
10234 if (j >= ARRAY_SIZE (cpu_noarch))
10235 j = ARRAY_SIZE (cpu_arch);
10236 }
10237
91d6fa6a 10238 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10239 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10240
10241 arch = next;
9103f4f4 10242 }
293f5f65
L		 10243 while (next != NULL);
10244 free (saved);
9103f4f4
L		 10245 break;
10246
10247 case OPTION_MTUNE:
10248 if (*arg == '.')
2b5d6a91 10249 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 10250 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10251 {
91d6fa6a 10252 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 10253 {
ccc9c027 10254 cpu_arch_tune_set = 1;
91d6fa6a
NC		 10255 cpu_arch_tune = cpu_arch [j].type;
10256 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 10257 break;
10258 }
10259 }
91d6fa6a 10260 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10261 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 10262 break;
10263
1efbbeb4
L		 10264 case OPTION_MMNEMONIC:
10265 if (strcasecmp (arg, "att") == 0)
10266 intel_mnemonic = 0;
10267 else if (strcasecmp (arg, "intel") == 0)
10268 intel_mnemonic = 1;
10269 else
2b5d6a91 10270 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 10271 break;
10272
10273 case OPTION_MSYNTAX:
10274 if (strcasecmp (arg, "att") == 0)
10275 intel_syntax = 0;
10276 else if (strcasecmp (arg, "intel") == 0)
10277 intel_syntax = 1;
10278 else
2b5d6a91 10279 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 10280 break;
10281
10282 case OPTION_MINDEX_REG:
10283 allow_index_reg = 1;
10284 break;
10285
10286 case OPTION_MNAKED_REG:
10287 allow_naked_reg = 1;
10288 break;
10289
10290 case OPTION_MOLD_GCC:
10291 old_gcc = 1;
1efbbeb4
L		 10292 break;
10293
c0f3af97
L		 10294 case OPTION_MSSE2AVX:
10295 sse2avx = 1;
10296 break;
10297
daf50ae7
L		 10298 case OPTION_MSSE_CHECK:
10299 if (strcasecmp (arg, "error") == 0)
7bab8ab5 10300 sse_check = check_error;
daf50ae7 10301 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 10302 sse_check = check_warning;
daf50ae7 10303 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10304 sse_check = check_none;
daf50ae7 10305 else
2b5d6a91 10306 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10307 break;
10308
7bab8ab5
JB		 10309 case OPTION_MOPERAND_CHECK:
10310 if (strcasecmp (arg, "error") == 0)
10311 operand_check = check_error;
10312 else if (strcasecmp (arg, "warning") == 0)
10313 operand_check = check_warning;
10314 else if (strcasecmp (arg, "none") == 0)
10315 operand_check = check_none;
10316 else
10317 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10318 break;
10319
539f890d
L		 10320 case OPTION_MAVXSCALAR:
10321 if (strcasecmp (arg, "128") == 0)
10322 avxscalar = vex128;
10323 else if (strcasecmp (arg, "256") == 0)
10324 avxscalar = vex256;
10325 else
2b5d6a91 10326 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10327 break;
10328
7e8b059b
L		 10329 case OPTION_MADD_BND_PREFIX:
10330 add_bnd_prefix = 1;
10331 break;
10332
43234a1e
L		 10333 case OPTION_MEVEXLIG:
10334 if (strcmp (arg, "128") == 0)
10335 evexlig = evexl128;
10336 else if (strcmp (arg, "256") == 0)
10337 evexlig = evexl256;
10338 else if (strcmp (arg, "512") == 0)
10339 evexlig = evexl512;
10340 else
10341 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10342 break;
10343
d3d3c6db
IT		 10344 case OPTION_MEVEXRCIG:
10345 if (strcmp (arg, "rne") == 0)
10346 evexrcig = rne;
10347 else if (strcmp (arg, "rd") == 0)
10348 evexrcig = rd;
10349 else if (strcmp (arg, "ru") == 0)
10350 evexrcig = ru;
10351 else if (strcmp (arg, "rz") == 0)
10352 evexrcig = rz;
10353 else
10354 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10355 break;
10356
43234a1e
L		 10357 case OPTION_MEVEXWIG:
10358 if (strcmp (arg, "0") == 0)
10359 evexwig = evexw0;
10360 else if (strcmp (arg, "1") == 0)
10361 evexwig = evexw1;
10362 else
10363 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10364 break;
10365
167ad85b
TG		 10366# if defined (TE_PE) || defined (TE_PEP)
10367 case OPTION_MBIG_OBJ:
10368 use_big_obj = 1;
10369 break;
10370#endif
10371
d1982f93 10372 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10373 if (strcasecmp (arg, "yes") == 0)
10374 omit_lock_prefix = 1;
10375 else if (strcasecmp (arg, "no") == 0)
10376 omit_lock_prefix = 0;
10377 else
10378 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10379 break;
10380
e4e00185
AS		 10381 case OPTION_MFENCE_AS_LOCK_ADD:
10382 if (strcasecmp (arg, "yes") == 0)
10383 avoid_fence = 1;
10384 else if (strcasecmp (arg, "no") == 0)
10385 avoid_fence = 0;
10386 else
10387 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10388 break;
10389
0cb4071e
L		 10390 case OPTION_MRELAX_RELOCATIONS:
10391 if (strcasecmp (arg, "yes") == 0)
10392 generate_relax_relocations = 1;
10393 else if (strcasecmp (arg, "no") == 0)
10394 generate_relax_relocations = 0;
10395 else
10396 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10397 break;
10398
5db04b09 10399 case OPTION_MAMD64:
e89c5eaa 10400 intel64 = 0;
5db04b09
L		 10401 break;
10402
10403 case OPTION_MINTEL64:
e89c5eaa 10404 intel64 = 1;
5db04b09
L		 10405 break;
10406
252b5132
RH		 10407 default:
10408 return 0;
10409 }
10410 return 1;
10411}
10412
8a2c8fef
L		 10413#define MESSAGE_TEMPLATE \
10414" "
10415
293f5f65
L		 10416static char *
10417output_message (FILE *stream, char *p, char *message, char *start,
10418 int *left_p, const char *name, int len)
10419{
10420 int size = sizeof (MESSAGE_TEMPLATE);
10421 int left = *left_p;
10422
10423 /* Reserve 2 spaces for ", " or ",\0" */
10424 left -= len + 2;
10425
10426 /* Check if there is any room. */
10427 if (left >= 0)
10428 {
10429 if (p != start)
10430 {
10431 *p++ = ',';
10432 *p++ = ' ';
10433 }
10434 p = mempcpy (p, name, len);
10435 }
10436 else
10437 {
10438 /* Output the current message now and start a new one. */
10439 *p++ = ',';
10440 *p = '\0';
10441 fprintf (stream, "%s\n", message);
10442 p = start;
10443 left = size - (start - message) - len - 2;
10444
10445 gas_assert (left >= 0);
10446
10447 p = mempcpy (p, name, len);
10448 }
10449
10450 *left_p = left;
10451 return p;
10452}
10453
8a2c8fef 10454static void
1ded5609 10455show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10456{
10457 static char message[] = MESSAGE_TEMPLATE;
10458 char *start = message + 27;
10459 char *p;
10460 int size = sizeof (MESSAGE_TEMPLATE);
10461 int left;
10462 const char *name;
10463 int len;
10464 unsigned int j;
10465
10466 p = start;
10467 left = size - (start - message);
10468 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10469 {
10470 /* Should it be skipped? */
10471 if (cpu_arch [j].skip)
10472 continue;
10473
10474 name = cpu_arch [j].name;
10475 len = cpu_arch [j].len;
10476 if (*name == '.')
10477 {
10478 /* It is an extension. Skip if we aren't asked to show it. */
10479 if (ext)
10480 {
10481 name++;
10482 len--;
10483 }
10484 else
10485 continue;
10486 }
10487 else if (ext)
10488 {
10489 /* It is an processor. Skip if we show only extension. */
10490 continue;
10491 }
1ded5609
JB		 10492 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10493 {
10494 /* It is an impossible processor - skip. */
10495 continue;
10496 }
8a2c8fef 10497
293f5f65 10498 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 10499 }
10500
293f5f65
L		 10501 /* Display disabled extensions. */
10502 if (ext)
10503 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10504 {
10505 name = cpu_noarch [j].name;
10506 len = cpu_noarch [j].len;
10507 p = output_message (stream, p, message, start, &left, name,
10508 len);
10509 }
10510
8a2c8fef
L		 10511 *p = '\0';
10512 fprintf (stream, "%s\n", message);
10513}
10514
252b5132 10515void
8a2c8fef 10516md_show_usage (FILE *stream)
252b5132 10517{
4cc782b5
ILT		 10518#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10519 fprintf (stream, _("\
a38cf1db
AM		 10520 -Q ignored\n\
10521 -V print assembler version number\n\
b3b91714
AM		 10522 -k ignored\n"));
10523#endif
10524 fprintf (stream, _("\
12b55ccc 10525 -n Do not optimize code alignment\n\
b3b91714
AM		 10526 -q quieten some warnings\n"));
10527#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10528 fprintf (stream, _("\
a38cf1db 10529 -s ignored\n"));
b3b91714 10530#endif
321098a5
L		 10531#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10532 || defined (TE_PE) || defined (TE_PEP))
751d281c 10533 fprintf (stream, _("\
570561f7 10534 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10535#endif
b3b91714
AM		 10536#ifdef SVR4_COMMENT_CHARS
10537 fprintf (stream, _("\
10538 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10539#else
10540 fprintf (stream, _("\
b3b91714 10541 --divide ignored\n"));
4cc782b5 10542#endif
9103f4f4 10543 fprintf (stream, _("\
6305a203 10544 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10545 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10546 show_arch (stream, 0, 1);
8a2c8fef
L		 10547 fprintf (stream, _("\
10548 EXTENSION is combination of:\n"));
1ded5609 10549 show_arch (stream, 1, 0);
6305a203 10550 fprintf (stream, _("\
8a2c8fef 10551 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10552 show_arch (stream, 0, 0);
ba104c83 10553 fprintf (stream, _("\
c0f3af97
L		 10554 -msse2avx encode SSE instructions with VEX prefix\n"));
10555 fprintf (stream, _("\
daf50ae7
L		 10556 -msse-check=[none|error|warning]\n\
10557 check SSE instructions\n"));
10558 fprintf (stream, _("\
7bab8ab5
JB		 10559 -moperand-check=[none|error|warning]\n\
10560 check operand combinations for validity\n"));
10561 fprintf (stream, _("\
539f890d
L		 10562 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10563 length\n"));
10564 fprintf (stream, _("\
43234a1e
L		 10565 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10566 length\n"));
10567 fprintf (stream, _("\
10568 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10569 for EVEX.W bit ignored instructions\n"));
10570 fprintf (stream, _("\
d3d3c6db
IT		 10571 -mevexrcig=[rne|rd|ru|rz]\n\
10572 encode EVEX instructions with specific EVEX.RC value\n\
10573 for SAE-only ignored instructions\n"));
10574 fprintf (stream, _("\
ba104c83
L		 10575 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10576 fprintf (stream, _("\
10577 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10578 fprintf (stream, _("\
10579 -mindex-reg support pseudo index registers\n"));
10580 fprintf (stream, _("\
10581 -mnaked-reg don't require `%%' prefix for registers\n"));
10582 fprintf (stream, _("\
10583 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10584 fprintf (stream, _("\
10585 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10586 fprintf (stream, _("\
10587 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10588# if defined (TE_PE) || defined (TE_PEP)
10589 fprintf (stream, _("\
10590 -mbig-obj generate big object files\n"));
10591#endif
d022bddd
IT		 10592 fprintf (stream, _("\
10593 -momit-lock-prefix=[no|yes]\n\
10594 strip all lock prefixes\n"));
5db04b09 10595 fprintf (stream, _("\
e4e00185
AS		 10596 -mfence-as-lock-add=[no|yes]\n\
10597 encode lfence, mfence and sfence as\n\
10598 lock addl $0x0, (%%{re}sp)\n"));
10599 fprintf (stream, _("\
0cb4071e
L		 10600 -mrelax-relocations=[no|yes]\n\
10601 generate relax relocations\n"));
10602 fprintf (stream, _("\
5db04b09
L		 10603 -mamd64 accept only AMD64 ISA\n"));
10604 fprintf (stream, _("\
10605 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10606}
10607
3e73aa7c 10608#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10609 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10610 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10611
10612/* Pick the target format to use. */
10613
47926f60 10614const char *
e3bb37b5 10615i386_target_format (void)
252b5132 10616{
351f65ca
L		 10617 if (!strncmp (default_arch, "x86_64", 6))
10618 {
10619 update_code_flag (CODE_64BIT, 1);
10620 if (default_arch[6] == '\0')
7f56bc95 10621 x86_elf_abi = X86_64_ABI;
351f65ca 10622 else
7f56bc95 10623 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10624 }
3e73aa7c 10625 else if (!strcmp (default_arch, "i386"))
78f12dd3 10626 update_code_flag (CODE_32BIT, 1);
5197d474
L		 10627 else if (!strcmp (default_arch, "iamcu"))
10628 {
10629 update_code_flag (CODE_32BIT, 1);
10630 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10631 {
10632 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10633 cpu_arch_name = "iamcu";
10634 cpu_sub_arch_name = NULL;
10635 cpu_arch_flags = iamcu_flags;
10636 cpu_arch_isa = PROCESSOR_IAMCU;
10637 cpu_arch_isa_flags = iamcu_flags;
10638 if (!cpu_arch_tune_set)
10639 {
10640 cpu_arch_tune = cpu_arch_isa;
10641 cpu_arch_tune_flags = cpu_arch_isa_flags;
10642 }
10643 }
8d471ec1 10644 else if (cpu_arch_isa != PROCESSOR_IAMCU)
5197d474
L		 10645 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10646 cpu_arch_name);
10647 }
3e73aa7c 10648 else
2b5d6a91 10649 as_fatal (_("unknown architecture"));
89507696
JB		 10650
10651 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10652 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10653 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10654 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10655
252b5132
RH		 10656 switch (OUTPUT_FLAVOR)
10657 {
9384f2ff 10658#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10659 case bfd_target_aout_flavour:
47926f60 10660 return AOUT_TARGET_FORMAT;
4c63da97 10661#endif
9384f2ff
AM		 10662#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10663# if defined (TE_PE) || defined (TE_PEP)
10664 case bfd_target_coff_flavour:
167ad85b
TG		 10665 if (flag_code == CODE_64BIT)
10666 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10667 else
10668 return "pe-i386";
9384f2ff 10669# elif defined (TE_GO32)
0561d57c
JK		 10670 case bfd_target_coff_flavour:
10671 return "coff-go32";
9384f2ff 10672# else
252b5132
RH		 10673 case bfd_target_coff_flavour:
10674 return "coff-i386";
9384f2ff 10675# endif
4c63da97 10676#endif
3e73aa7c 10677#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10678 case bfd_target_elf_flavour:
3e73aa7c 10679 {
351f65ca
L		 10680 const char *format;
10681
10682 switch (x86_elf_abi)
4fa24527 10683 {
351f65ca
L		 10684 default:
10685 format = ELF_TARGET_FORMAT;
10686 break;
7f56bc95 10687 case X86_64_ABI:
351f65ca 10688 use_rela_relocations = 1;
4fa24527 10689 object_64bit = 1;
351f65ca
L		 10690 format = ELF_TARGET_FORMAT64;
10691 break;
7f56bc95 10692 case X86_64_X32_ABI:
4fa24527 10693 use_rela_relocations = 1;
351f65ca 10694 object_64bit = 1;
862be3fb 10695 disallow_64bit_reloc = 1;
351f65ca
L		 10696 format = ELF_TARGET_FORMAT32;
10697 break;
4fa24527 10698 }
3632d14b 10699 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10700 {
7f56bc95 10701 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10702 as_fatal (_("Intel L1OM is 64bit only"));
10703 return ELF_TARGET_L1OM_FORMAT;
10704 }
b49f93f6 10705 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 10706 {
10707 if (x86_elf_abi != X86_64_ABI)
10708 as_fatal (_("Intel K1OM is 64bit only"));
10709 return ELF_TARGET_K1OM_FORMAT;
10710 }
81486035
L		 10711 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10712 {
10713 if (x86_elf_abi != I386_ABI)
10714 as_fatal (_("Intel MCU is 32bit only"));
10715 return ELF_TARGET_IAMCU_FORMAT;
10716 }
8a9036a4 10717 else
351f65ca 10718 return format;
3e73aa7c 10719 }
e57f8c65
TG		 10720#endif
10721#if defined (OBJ_MACH_O)
10722 case bfd_target_mach_o_flavour:
d382c579
TG		 10723 if (flag_code == CODE_64BIT)
10724 {
10725 use_rela_relocations = 1;
10726 object_64bit = 1;
10727 return "mach-o-x86-64";
10728 }
10729 else
10730 return "mach-o-i386";
4c63da97 10731#endif
252b5132
RH		 10732 default:
10733 abort ();
10734 return NULL;
10735 }
10736}
10737
47926f60 10738#endif /* OBJ_MAYBE_ more than one */
252b5132 10739\f
252b5132 10740symbolS *
7016a5d5 10741md_undefined_symbol (char *name)
252b5132 10742{
18dc2407
ILT		 10743 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10744 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10745 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10746 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10747 {
10748 if (!GOT_symbol)
10749 {
10750 if (symbol_find (name))
10751 as_bad (_("GOT already in symbol table"));
10752 GOT_symbol = symbol_new (name, undefined_section,
10753 (valueT) 0, &zero_address_frag);
10754 };
10755 return GOT_symbol;
10756 }
252b5132
RH		 10757 return 0;
10758}
10759
10760/* Round up a section size to the appropriate boundary. */
47926f60 10761
252b5132 10762valueT
7016a5d5 10763md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10764{
4c63da97
AM		 10765#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10766 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10767 {
10768 /* For a.out, force the section size to be aligned. If we don't do
10769 this, BFD will align it for us, but it will not write out the
10770 final bytes of the section. This may be a bug in BFD, but it is
10771 easier to fix it here since that is how the other a.out targets
10772 work. */
10773 int align;
10774
10775 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 10776 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 10777 }
252b5132
RH		 10778#endif
10779
10780 return size;
10781}
10782
10783/* On the i386, PC-relative offsets are relative to the start of the
10784 next instruction. That is, the address of the offset, plus its
10785 size, since the offset is always the last part of the insn. */
10786
10787long
e3bb37b5 10788md_pcrel_from (fixS *fixP)
252b5132
RH		 10789{
10790 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10791}
10792
10793#ifndef I386COFF
10794
10795static void
e3bb37b5 10796s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10797{
29b0f896 10798 int temp;
252b5132 10799
8a75718c
JB		 10800#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10801 if (IS_ELF)
10802 obj_elf_section_change_hook ();
10803#endif
252b5132
RH		 10804 temp = get_absolute_expression ();
10805 subseg_set (bss_section, (subsegT) temp);
10806 demand_empty_rest_of_line ();
10807}
10808
10809#endif
10810
252b5132 10811void
e3bb37b5 10812i386_validate_fix (fixS *fixp)
252b5132 10813{
02a86693 10814 if (fixp->fx_subsy)
252b5132 10815 {
02a86693 10816 if (fixp->fx_subsy == GOT_symbol)
23df1078 10817 {
02a86693
L		 10818 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10819 {
10820 if (!object_64bit)
10821 abort ();
10822#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10823 if (fixp->fx_tcbit2)
56ceb5b5
L		 10824 fixp->fx_r_type = (fixp->fx_tcbit
10825 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10826 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 10827 else
10828#endif
10829 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10830 }
d6ab8113 10831 else
02a86693
L		 10832 {
10833 if (!object_64bit)
10834 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10835 else
10836 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10837 }
10838 fixp->fx_subsy = 0;
23df1078 10839 }
252b5132 10840 }
02a86693
L		 10841#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10842 else if (!object_64bit)
10843 {
10844 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
10845 && fixp->fx_tcbit2)
10846 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
10847 }
10848#endif
252b5132
RH		 10849}
10850
252b5132 10851arelent *
7016a5d5 10852tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10853{
10854 arelent *rel;
10855 bfd_reloc_code_real_type code;
10856
10857 switch (fixp->fx_r_type)
10858 {
8ce3d284 10859#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10860 case BFD_RELOC_SIZE32:
10861 case BFD_RELOC_SIZE64:
10862 if (S_IS_DEFINED (fixp->fx_addsy)
10863 && !S_IS_EXTERNAL (fixp->fx_addsy))
10864 {
10865 /* Resolve size relocation against local symbol to size of
10866 the symbol plus addend. */
10867 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10868 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10869 && !fits_in_unsigned_long (value))
10870 as_bad_where (fixp->fx_file, fixp->fx_line,
10871 _("symbol size computation overflow"));
10872 fixp->fx_addsy = NULL;
10873 fixp->fx_subsy = NULL;
10874 md_apply_fix (fixp, (valueT *) &value, NULL);
10875 return NULL;
10876 }
8ce3d284 10877#endif
1a0670f3 10878 /* Fall through. */
8fd4256d 10879
3e73aa7c
JH		 10880 case BFD_RELOC_X86_64_PLT32:
10881 case BFD_RELOC_X86_64_GOT32:
10882 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10883 case BFD_RELOC_X86_64_GOTPCRELX:
10884 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 10885 case BFD_RELOC_386_PLT32:
10886 case BFD_RELOC_386_GOT32:
02a86693 10887 case BFD_RELOC_386_GOT32X:
252b5132
RH		 10888 case BFD_RELOC_386_GOTOFF:
10889 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10890 case BFD_RELOC_386_TLS_GD:
10891 case BFD_RELOC_386_TLS_LDM:
10892 case BFD_RELOC_386_TLS_LDO_32:
10893 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10894 case BFD_RELOC_386_TLS_IE:
10895 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10896 case BFD_RELOC_386_TLS_LE_32:
10897 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10898 case BFD_RELOC_386_TLS_GOTDESC:
10899 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10900 case BFD_RELOC_X86_64_TLSGD:
10901 case BFD_RELOC_X86_64_TLSLD:
10902 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10903 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10904 case BFD_RELOC_X86_64_GOTTPOFF:
10905 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10906 case BFD_RELOC_X86_64_TPOFF64:
10907 case BFD_RELOC_X86_64_GOTOFF64:
10908 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10909 case BFD_RELOC_X86_64_GOT64:
10910 case BFD_RELOC_X86_64_GOTPCREL64:
10911 case BFD_RELOC_X86_64_GOTPC64:
10912 case BFD_RELOC_X86_64_GOTPLT64:
10913 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10914 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10915 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10916 case BFD_RELOC_RVA:
10917 case BFD_RELOC_VTABLE_ENTRY:
10918 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10919#ifdef TE_PE
10920 case BFD_RELOC_32_SECREL:
10921#endif
252b5132
RH		 10922 code = fixp->fx_r_type;
10923 break;
dbbaec26
L		 10924 case BFD_RELOC_X86_64_32S:
10925 if (!fixp->fx_pcrel)
10926 {
10927 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10928 code = fixp->fx_r_type;
10929 break;
10930 }
1a0670f3 10931 /* Fall through. */
252b5132 10932 default:
93382f6d 10933 if (fixp->fx_pcrel)
252b5132 10934 {
93382f6d
AM		 10935 switch (fixp->fx_size)
10936 {
10937 default:
b091f402
AM		 10938 as_bad_where (fixp->fx_file, fixp->fx_line,
10939 _("can not do %d byte pc-relative relocation"),
10940 fixp->fx_size);
93382f6d
AM		 10941 code = BFD_RELOC_32_PCREL;
10942 break;
10943 case 1: code = BFD_RELOC_8_PCREL; break;
10944 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10945 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10946#ifdef BFD64
10947 case 8: code = BFD_RELOC_64_PCREL; break;
10948#endif
93382f6d
AM		 10949 }
10950 }
10951 else
10952 {
10953 switch (fixp->fx_size)
10954 {
10955 default:
b091f402
AM		 10956 as_bad_where (fixp->fx_file, fixp->fx_line,
10957 _("can not do %d byte relocation"),
10958 fixp->fx_size);
93382f6d
AM		 10959 code = BFD_RELOC_32;
10960 break;
10961 case 1: code = BFD_RELOC_8; break;
10962 case 2: code = BFD_RELOC_16; break;
10963 case 4: code = BFD_RELOC_32; break;
937149dd 10964#ifdef BFD64
3e73aa7c 10965 case 8: code = BFD_RELOC_64; break;
937149dd 10966#endif
93382f6d 10967 }
252b5132
RH		 10968 }
10969 break;
10970 }
252b5132 10971
d182319b
JB		 10972 if ((code == BFD_RELOC_32
10973 || code == BFD_RELOC_32_PCREL
10974 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10975 && GOT_symbol
10976 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10977 {
4fa24527 10978 if (!object_64bit)
d6ab8113
JB		 10979 code = BFD_RELOC_386_GOTPC;
10980 else
10981 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10982 }
7b81dfbb
AJ		 10983 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10984 && GOT_symbol
10985 && fixp->fx_addsy == GOT_symbol)
10986 {
10987 code = BFD_RELOC_X86_64_GOTPC64;
10988 }
252b5132 10989
add39d23
TS		 10990 rel = XNEW (arelent);
10991 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 10992 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10993
10994 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10995
3e73aa7c
JH		 10996 if (!use_rela_relocations)
10997 {
10998 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10999 vtable entry to be used in the relocation's section offset. */
11000 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11001 rel->address = fixp->fx_offset;
fbeb56a4
DK		 11002#if defined (OBJ_COFF) && defined (TE_PE)
11003 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11004 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11005 else
11006#endif
c6682705 11007 rel->addend = 0;
3e73aa7c
JH		 11008 }
11009 /* Use the rela in 64bit mode. */
252b5132 11010 else
3e73aa7c 11011 {
862be3fb
L		 11012 if (disallow_64bit_reloc)
11013 switch (code)
11014 {
862be3fb
L		 11015 case BFD_RELOC_X86_64_DTPOFF64:
11016 case BFD_RELOC_X86_64_TPOFF64:
11017 case BFD_RELOC_64_PCREL:
11018 case BFD_RELOC_X86_64_GOTOFF64:
11019 case BFD_RELOC_X86_64_GOT64:
11020 case BFD_RELOC_X86_64_GOTPCREL64:
11021 case BFD_RELOC_X86_64_GOTPC64:
11022 case BFD_RELOC_X86_64_GOTPLT64:
11023 case BFD_RELOC_X86_64_PLTOFF64:
11024 as_bad_where (fixp->fx_file, fixp->fx_line,
11025 _("cannot represent relocation type %s in x32 mode"),
11026 bfd_get_reloc_code_name (code));
11027 break;
11028 default:
11029 break;
11030 }
11031
062cd5e7
AS		 11032 if (!fixp->fx_pcrel)
11033 rel->addend = fixp->fx_offset;
11034 else
11035 switch (code)
11036 {
11037 case BFD_RELOC_X86_64_PLT32:
11038 case BFD_RELOC_X86_64_GOT32:
11039 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11040 case BFD_RELOC_X86_64_GOTPCRELX:
11041 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 11042 case BFD_RELOC_X86_64_TLSGD:
11043 case BFD_RELOC_X86_64_TLSLD:
11044 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 11045 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11046 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 11047 rel->addend = fixp->fx_offset - fixp->fx_size;
11048 break;
11049 default:
11050 rel->addend = (section->vma
11051 - fixp->fx_size
11052 + fixp->fx_addnumber
11053 + md_pcrel_from (fixp));
11054 break;
11055 }
3e73aa7c
JH		 11056 }
11057
252b5132
RH		 11058 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11059 if (rel->howto == NULL)
11060 {
11061 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 11062 _("cannot represent relocation type %s"),
252b5132
RH		 11063 bfd_get_reloc_code_name (code));
11064 /* Set howto to a garbage value so that we can keep going. */
11065 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 11066 gas_assert (rel->howto != NULL);
252b5132
RH		 11067 }
11068
11069 return rel;
11070}
11071
ee86248c 11072#include "tc-i386-intel.c"
54cfded0 11073
a60de03c
JB		 11074void
11075tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 11076{
a60de03c
JB		 11077 int saved_naked_reg;
11078 char saved_register_dot;
54cfded0 11079
a60de03c
JB		 11080 saved_naked_reg = allow_naked_reg;
11081 allow_naked_reg = 1;
11082 saved_register_dot = register_chars['.'];
11083 register_chars['.'] = '.';
11084 allow_pseudo_reg = 1;
11085 expression_and_evaluate (exp);
11086 allow_pseudo_reg = 0;
11087 register_chars['.'] = saved_register_dot;
11088 allow_naked_reg = saved_naked_reg;
11089
e96d56a1 11090 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 11091 {
a60de03c
JB		 11092 if ((addressT) exp->X_add_number < i386_regtab_size)
11093 {
11094 exp->X_op = O_constant;
11095 exp->X_add_number = i386_regtab[exp->X_add_number]
11096 .dw2_regnum[flag_code >> 1];
11097 }
11098 else
11099 exp->X_op = O_illegal;
54cfded0 11100 }
54cfded0
AM		 11101}
11102
11103void
11104tc_x86_frame_initial_instructions (void)
11105{
a60de03c
JB		 11106 static unsigned int sp_regno[2];
11107
11108 if (!sp_regno[flag_code >> 1])
11109 {
11110 char *saved_input = input_line_pointer;
11111 char sp[][4] = {"esp", "rsp"};
11112 expressionS exp;
a4447b93 11113
a60de03c
JB		 11114 input_line_pointer = sp[flag_code >> 1];
11115 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 11116 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 11117 sp_regno[flag_code >> 1] = exp.X_add_number;
11118 input_line_pointer = saved_input;
11119 }
a4447b93 11120
61ff971f
L		 11121 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11122 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 11123}
d2b2c203 11124
d7921315
L		 11125int
11126x86_dwarf2_addr_size (void)
11127{
11128#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11129 if (x86_elf_abi == X86_64_X32_ABI)
11130 return 4;
11131#endif
11132 return bfd_arch_bits_per_address (stdoutput) / 8;
11133}
11134
d2b2c203
DJ		 11135int
11136i386_elf_section_type (const char *str, size_t len)
11137{
11138 if (flag_code == CODE_64BIT
11139 && len == sizeof ("unwind") - 1
11140 && strncmp (str, "unwind", 6) == 0)
11141 return SHT_X86_64_UNWIND;
11142
11143 return -1;
11144}
bb41ade5 11145
ad5fec3b
EB		 11146#ifdef TE_SOLARIS
11147void
11148i386_solaris_fix_up_eh_frame (segT sec)
11149{
11150 if (flag_code == CODE_64BIT)
11151 elf_section_type (sec) = SHT_X86_64_UNWIND;
11152}
11153#endif
11154
bb41ade5
AM		 11155#ifdef TE_PE
11156void
11157tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11158{
91d6fa6a 11159 expressionS exp;
bb41ade5 11160
91d6fa6a
NC		 11161 exp.X_op = O_secrel;
11162 exp.X_add_symbol = symbol;
11163 exp.X_add_number = 0;
11164 emit_expr (&exp, size);
bb41ade5
AM		 11165}
11166#endif
3b22753a
L		 11167
11168#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11169/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11170
01e1a5bc 11171bfd_vma
6d4af3c2 11172x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 11173{
11174 if (flag_code == CODE_64BIT)
11175 {
11176 if (letter == 'l')
11177 return SHF_X86_64_LARGE;
11178
8f3bae45 11179 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 11180 }
3b22753a 11181 else
8f3bae45 11182 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 11183 return -1;
11184}
11185
01e1a5bc 11186bfd_vma
3b22753a
L		 11187x86_64_section_word (char *str, size_t len)
11188{
8620418b 11189 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 11190 return SHF_X86_64_LARGE;
11191
11192 return -1;
11193}
11194
11195static void
11196handle_large_common (int small ATTRIBUTE_UNUSED)
11197{
11198 if (flag_code != CODE_64BIT)
11199 {
11200 s_comm_internal (0, elf_common_parse);
11201 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11202 }
11203 else
11204 {
11205 static segT lbss_section;
11206 asection *saved_com_section_ptr = elf_com_section_ptr;
11207 asection *saved_bss_section = bss_section;
11208
11209 if (lbss_section == NULL)
11210 {
11211 flagword applicable;
11212 segT seg = now_seg;
11213 subsegT subseg = now_subseg;
11214
11215 /* The .lbss section is for local .largecomm symbols. */
11216 lbss_section = subseg_new (".lbss", 0);
11217 applicable = bfd_applicable_section_flags (stdoutput);
11218 bfd_set_section_flags (stdoutput, lbss_section,
11219 applicable & SEC_ALLOC);
11220 seg_info (lbss_section)->bss = 1;
11221
11222 subseg_set (seg, subseg);
11223 }
11224
11225 elf_com_section_ptr = &_bfd_elf_large_com_section;
11226 bss_section = lbss_section;
11227
11228 s_comm_internal (0, elf_common_parse);
11229
11230 elf_com_section_ptr = saved_com_section_ptr;
11231 bss_section = saved_bss_section;
11232 }
11233}
11234#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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