Commit | Line | Data |
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252b5132 | 1 | /* i386.c -- Assemble code for the Intel 80386 |
f7e42eb4 NC |
2 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
3 | 2000, 2001 | |
47926f60 | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | |
6 | This file is part of GAS, the GNU Assembler. | |
7 | ||
8 | GAS is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GAS is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GAS; see the file COPYING. If not, write to the Free | |
20 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
21 | 02111-1307, USA. */ | |
22 | ||
47926f60 KH |
23 | /* Intel 80386 machine specific gas. |
24 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 25 | x86_64 support by Jan Hubicka (jh@suse.cz) |
47926f60 KH |
26 | Bugs & suggestions are completely welcome. This is free software. |
27 | Please help us make it better. */ | |
252b5132 RH |
28 | |
29 | #include <ctype.h> | |
30 | ||
31 | #include "as.h" | |
32 | #include "subsegs.h" | |
316e2c05 | 33 | #include "dwarf2dbg.h" |
252b5132 RH |
34 | #include "opcode/i386.h" |
35 | ||
252b5132 RH |
36 | #ifndef REGISTER_WARNINGS |
37 | #define REGISTER_WARNINGS 1 | |
38 | #endif | |
39 | ||
c3332e24 | 40 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 41 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
42 | #endif |
43 | ||
252b5132 RH |
44 | #ifndef SCALE1_WHEN_NO_INDEX |
45 | /* Specifying a scale factor besides 1 when there is no index is | |
46 | futile. eg. `mov (%ebx,2),%al' does exactly the same as | |
47 | `mov (%ebx),%al'. To slavishly follow what the programmer | |
48 | specified, set SCALE1_WHEN_NO_INDEX to 0. */ | |
49 | #define SCALE1_WHEN_NO_INDEX 1 | |
50 | #endif | |
51 | ||
52 | #define true 1 | |
53 | #define false 0 | |
54 | ||
55 | static unsigned int mode_from_disp_size PARAMS ((unsigned int)); | |
847f7ad4 AM |
56 | static int fits_in_signed_byte PARAMS ((offsetT)); |
57 | static int fits_in_unsigned_byte PARAMS ((offsetT)); | |
58 | static int fits_in_unsigned_word PARAMS ((offsetT)); | |
59 | static int fits_in_signed_word PARAMS ((offsetT)); | |
3e73aa7c JH |
60 | static int fits_in_unsigned_long PARAMS ((offsetT)); |
61 | static int fits_in_signed_long PARAMS ((offsetT)); | |
847f7ad4 AM |
62 | static int smallest_imm_type PARAMS ((offsetT)); |
63 | static offsetT offset_in_range PARAMS ((offsetT, int)); | |
252b5132 | 64 | static int add_prefix PARAMS ((unsigned int)); |
3e73aa7c | 65 | static void set_code_flag PARAMS ((int)); |
47926f60 | 66 | static void set_16bit_gcc_code_flag PARAMS ((int)); |
252b5132 | 67 | static void set_intel_syntax PARAMS ((int)); |
e413e4e9 | 68 | static void set_cpu_arch PARAMS ((int)); |
252b5132 RH |
69 | |
70 | #ifdef BFD_ASSEMBLER | |
71 | static bfd_reloc_code_real_type reloc | |
3e73aa7c | 72 | PARAMS ((int, int, int, bfd_reloc_code_real_type)); |
f3c180ae AM |
73 | #define RELOC_ENUM enum bfd_reloc_code_real |
74 | #else | |
75 | #define RELOC_ENUM int | |
252b5132 RH |
76 | #endif |
77 | ||
3e73aa7c JH |
78 | #ifndef DEFAULT_ARCH |
79 | #define DEFAULT_ARCH "i386" | |
80 | #endif | |
81 | static char *default_arch = DEFAULT_ARCH; | |
82 | ||
252b5132 | 83 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 84 | i386_insn. */ |
252b5132 | 85 | |
520dc8e8 AM |
86 | union i386_op |
87 | { | |
88 | expressionS *disps; | |
89 | expressionS *imms; | |
90 | const reg_entry *regs; | |
91 | }; | |
92 | ||
252b5132 RH |
93 | struct _i386_insn |
94 | { | |
47926f60 | 95 | /* TM holds the template for the insn were currently assembling. */ |
252b5132 RH |
96 | template tm; |
97 | ||
98 | /* SUFFIX holds the instruction mnemonic suffix if given. | |
99 | (e.g. 'l' for 'movl') */ | |
100 | char suffix; | |
101 | ||
47926f60 | 102 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
103 | unsigned int operands; |
104 | ||
105 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
106 | of given register, displacement, memory operands and immediate | |
47926f60 | 107 | operands. */ |
252b5132 RH |
108 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
109 | ||
110 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 111 | use OP[i] for the corresponding operand. */ |
252b5132 RH |
112 | unsigned int types[MAX_OPERANDS]; |
113 | ||
520dc8e8 AM |
114 | /* Displacement expression, immediate expression, or register for each |
115 | operand. */ | |
116 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 117 | |
3e73aa7c JH |
118 | /* Flags for operands. */ |
119 | unsigned int flags[MAX_OPERANDS]; | |
120 | #define Operand_PCrel 1 | |
121 | ||
252b5132 | 122 | /* Relocation type for operand */ |
f3c180ae | 123 | RELOC_ENUM reloc[MAX_OPERANDS]; |
252b5132 | 124 | |
252b5132 RH |
125 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
126 | the base index byte below. */ | |
127 | const reg_entry *base_reg; | |
128 | const reg_entry *index_reg; | |
129 | unsigned int log2_scale_factor; | |
130 | ||
131 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 132 | explicit segment overrides are given. */ |
ce8a8b2f | 133 | const seg_entry *seg[2]; |
252b5132 RH |
134 | |
135 | /* PREFIX holds all the given prefix opcodes (usually null). | |
136 | PREFIXES is the number of prefix opcodes. */ | |
137 | unsigned int prefixes; | |
138 | unsigned char prefix[MAX_PREFIXES]; | |
139 | ||
140 | /* RM and SIB are the modrm byte and the sib byte where the | |
141 | addressing modes of this insn are encoded. */ | |
142 | ||
143 | modrm_byte rm; | |
3e73aa7c | 144 | rex_byte rex; |
252b5132 RH |
145 | sib_byte sib; |
146 | }; | |
147 | ||
148 | typedef struct _i386_insn i386_insn; | |
149 | ||
150 | /* List of chars besides those in app.c:symbol_chars that can start an | |
151 | operand. Used to prevent the scrubber eating vital white-space. */ | |
152 | #ifdef LEX_AT | |
153 | const char extra_symbol_chars[] = "*%-(@"; | |
154 | #else | |
155 | const char extra_symbol_chars[] = "*%-("; | |
156 | #endif | |
157 | ||
158 | /* This array holds the chars that always start a comment. If the | |
ce8a8b2f | 159 | pre-processor is disabled, these aren't very useful. */ |
60bcf0fa | 160 | #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD)) |
252b5132 RH |
161 | /* Putting '/' here makes it impossible to use the divide operator. |
162 | However, we need it for compatibility with SVR4 systems. */ | |
163 | const char comment_chars[] = "#/"; | |
164 | #define PREFIX_SEPARATOR '\\' | |
165 | #else | |
166 | const char comment_chars[] = "#"; | |
167 | #define PREFIX_SEPARATOR '/' | |
168 | #endif | |
169 | ||
170 | /* This array holds the chars that only start a comment at the beginning of | |
171 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
172 | .line and .file directives will appear in the pre-processed output. |
173 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 174 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
175 | #NO_APP at the beginning of its output. |
176 | Also note that comments started like this one will always work if | |
252b5132 | 177 | '/' isn't otherwise defined. */ |
60bcf0fa | 178 | #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD)) |
252b5132 RH |
179 | const char line_comment_chars[] = ""; |
180 | #else | |
181 | const char line_comment_chars[] = "/"; | |
182 | #endif | |
183 | ||
63a0b638 | 184 | const char line_separator_chars[] = ";"; |
252b5132 | 185 | |
ce8a8b2f AM |
186 | /* Chars that can be used to separate mant from exp in floating point |
187 | nums. */ | |
252b5132 RH |
188 | const char EXP_CHARS[] = "eE"; |
189 | ||
ce8a8b2f AM |
190 | /* Chars that mean this number is a floating point constant |
191 | As in 0f12.456 | |
192 | or 0d1.2345e12. */ | |
252b5132 RH |
193 | const char FLT_CHARS[] = "fFdDxX"; |
194 | ||
ce8a8b2f | 195 | /* Tables for lexical analysis. */ |
252b5132 RH |
196 | static char mnemonic_chars[256]; |
197 | static char register_chars[256]; | |
198 | static char operand_chars[256]; | |
199 | static char identifier_chars[256]; | |
200 | static char digit_chars[256]; | |
201 | ||
ce8a8b2f | 202 | /* Lexical macros. */ |
252b5132 RH |
203 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
204 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
205 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
206 | #define is_space_char(x) ((x) == ' ') | |
207 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
208 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
209 | ||
ce8a8b2f | 210 | /* All non-digit non-letter charcters that may occur in an operand. */ |
252b5132 RH |
211 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
212 | ||
213 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
214 | effect this we maintain a stack of saved characters that we've smashed | |
215 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 216 | assembler instruction). */ |
252b5132 | 217 | static char save_stack[32]; |
ce8a8b2f | 218 | static char *save_stack_p; |
252b5132 RH |
219 | #define END_STRING_AND_SAVE(s) \ |
220 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
221 | #define RESTORE_END_STRING(s) \ | |
222 | do { *(s) = *--save_stack_p; } while (0) | |
223 | ||
47926f60 | 224 | /* The instruction we're assembling. */ |
252b5132 RH |
225 | static i386_insn i; |
226 | ||
227 | /* Possible templates for current insn. */ | |
228 | static const templates *current_templates; | |
229 | ||
47926f60 | 230 | /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */ |
252b5132 RH |
231 | static expressionS disp_expressions[2], im_expressions[2]; |
232 | ||
47926f60 KH |
233 | /* Current operand we are working on. */ |
234 | static int this_operand; | |
252b5132 | 235 | |
3e73aa7c JH |
236 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
237 | these. */ | |
238 | ||
239 | enum flag_code { | |
240 | CODE_32BIT, | |
241 | CODE_16BIT, | |
242 | CODE_64BIT }; | |
f3c180ae | 243 | #define NUM_FLAG_CODE ((int) CODE_64BIT + 1) |
3e73aa7c JH |
244 | |
245 | static enum flag_code flag_code; | |
246 | static int use_rela_relocations = 0; | |
247 | ||
248 | /* The names used to print error messages. */ | |
b77a7acd | 249 | static const char *flag_code_names[] = |
3e73aa7c JH |
250 | { |
251 | "32", | |
252 | "16", | |
253 | "64" | |
254 | }; | |
252b5132 | 255 | |
47926f60 KH |
256 | /* 1 for intel syntax, |
257 | 0 if att syntax. */ | |
258 | static int intel_syntax = 0; | |
252b5132 | 259 | |
47926f60 KH |
260 | /* 1 if register prefix % not required. */ |
261 | static int allow_naked_reg = 0; | |
252b5132 | 262 | |
47926f60 KH |
263 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
264 | leave, push, and pop instructions so that gcc has the same stack | |
265 | frame as in 32 bit mode. */ | |
266 | static char stackop_size = '\0'; | |
eecb386c | 267 | |
47926f60 KH |
268 | /* Non-zero to quieten some warnings. */ |
269 | static int quiet_warnings = 0; | |
a38cf1db | 270 | |
47926f60 KH |
271 | /* CPU name. */ |
272 | static const char *cpu_arch_name = NULL; | |
a38cf1db | 273 | |
47926f60 | 274 | /* CPU feature flags. */ |
3e73aa7c | 275 | static unsigned int cpu_arch_flags = CpuUnknownFlags|CpuNo64; |
a38cf1db | 276 | |
fddf5b5b AM |
277 | /* If set, conditional jumps are not automatically promoted to handle |
278 | larger than a byte offset. */ | |
279 | static unsigned int no_cond_jump_promotion = 0; | |
280 | ||
252b5132 | 281 | /* Interface to relax_segment. |
fddf5b5b AM |
282 | There are 3 major relax states for 386 jump insns because the |
283 | different types of jumps add different sizes to frags when we're | |
284 | figuring out what sort of jump to choose to reach a given label. */ | |
252b5132 | 285 | |
47926f60 | 286 | /* Types. */ |
93c2a809 AM |
287 | #define UNCOND_JUMP 0 |
288 | #define COND_JUMP 1 | |
289 | #define COND_JUMP86 2 | |
fddf5b5b | 290 | |
47926f60 | 291 | /* Sizes. */ |
252b5132 RH |
292 | #define CODE16 1 |
293 | #define SMALL 0 | |
294 | #define SMALL16 (SMALL|CODE16) | |
295 | #define BIG 2 | |
296 | #define BIG16 (BIG|CODE16) | |
297 | ||
298 | #ifndef INLINE | |
299 | #ifdef __GNUC__ | |
300 | #define INLINE __inline__ | |
301 | #else | |
302 | #define INLINE | |
303 | #endif | |
304 | #endif | |
305 | ||
fddf5b5b AM |
306 | #define ENCODE_RELAX_STATE(type, size) \ |
307 | ((relax_substateT) (((type) << 2) | (size))) | |
308 | #define TYPE_FROM_RELAX_STATE(s) \ | |
309 | ((s) >> 2) | |
310 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
311 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
312 | |
313 | /* This table is used by relax_frag to promote short jumps to long | |
314 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
315 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
316 | don't allow a short jump in a 32 bit code segment to be promoted to | |
317 | a 16 bit offset jump because it's slower (requires data size | |
318 | prefix), and doesn't work, unless the destination is in the bottom | |
319 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
320 | ||
321 | const relax_typeS md_relax_table[] = | |
322 | { | |
24eab124 AM |
323 | /* The fields are: |
324 | 1) most positive reach of this state, | |
325 | 2) most negative reach of this state, | |
93c2a809 | 326 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 327 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 328 | |
fddf5b5b | 329 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
330 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
331 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
332 | /* dword jmp adds 4 bytes to frag: | |
333 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 334 | {0, 0, 4, 0}, |
93c2a809 AM |
335 | /* word jmp adds 2 byte2 to frag: |
336 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
337 | {0, 0, 2, 0}, |
338 | ||
93c2a809 AM |
339 | /* COND_JUMP states. */ |
340 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
341 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
342 | /* dword conditionals adds 5 bytes to frag: | |
343 | 1 extra opcode byte, 4 displacement bytes. */ | |
344 | {0, 0, 5, 0}, | |
fddf5b5b | 345 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
346 | 1 extra opcode byte, 2 displacement bytes. */ |
347 | {0, 0, 3, 0}, | |
348 | ||
349 | /* COND_JUMP86 states. */ | |
350 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
351 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
352 | /* dword conditionals adds 5 bytes to frag: | |
353 | 1 extra opcode byte, 4 displacement bytes. */ | |
354 | {0, 0, 5, 0}, | |
355 | /* word conditionals add 4 bytes to frag: | |
356 | 1 displacement byte and a 3 byte long branch insn. */ | |
357 | {0, 0, 4, 0} | |
252b5132 RH |
358 | }; |
359 | ||
e413e4e9 AM |
360 | static const arch_entry cpu_arch[] = { |
361 | {"i8086", Cpu086 }, | |
362 | {"i186", Cpu086|Cpu186 }, | |
363 | {"i286", Cpu086|Cpu186|Cpu286 }, | |
364 | {"i386", Cpu086|Cpu186|Cpu286|Cpu386 }, | |
365 | {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 }, | |
366 | {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX }, | |
367 | {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE }, | |
368 | {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX }, | |
369 | {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE }, | |
a167610d | 370 | {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 }, |
3e73aa7c JH |
371 | {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow }, |
372 | {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow }, | |
a167610d | 373 | {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 }, |
e413e4e9 AM |
374 | {NULL, 0 } |
375 | }; | |
376 | ||
252b5132 RH |
377 | void |
378 | i386_align_code (fragP, count) | |
379 | fragS *fragP; | |
380 | int count; | |
381 | { | |
ce8a8b2f AM |
382 | /* Various efficient no-op patterns for aligning code labels. |
383 | Note: Don't try to assemble the instructions in the comments. | |
384 | 0L and 0w are not legal. */ | |
252b5132 RH |
385 | static const char f32_1[] = |
386 | {0x90}; /* nop */ | |
387 | static const char f32_2[] = | |
388 | {0x89,0xf6}; /* movl %esi,%esi */ | |
389 | static const char f32_3[] = | |
390 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
391 | static const char f32_4[] = | |
392 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
393 | static const char f32_5[] = | |
394 | {0x90, /* nop */ | |
395 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
396 | static const char f32_6[] = | |
397 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
398 | static const char f32_7[] = | |
399 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
400 | static const char f32_8[] = | |
401 | {0x90, /* nop */ | |
402 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
403 | static const char f32_9[] = | |
404 | {0x89,0xf6, /* movl %esi,%esi */ | |
405 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
406 | static const char f32_10[] = | |
407 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ | |
408 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
409 | static const char f32_11[] = | |
410 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ | |
411 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
412 | static const char f32_12[] = | |
413 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
414 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
415 | static const char f32_13[] = | |
416 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
417 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
418 | static const char f32_14[] = | |
419 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ | |
420 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
421 | static const char f32_15[] = | |
422 | {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */ | |
423 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
c3332e24 AM |
424 | static const char f16_3[] = |
425 | {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ | |
252b5132 RH |
426 | static const char f16_4[] = |
427 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
428 | static const char f16_5[] = | |
429 | {0x90, /* nop */ | |
430 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
431 | static const char f16_6[] = | |
432 | {0x89,0xf6, /* mov %si,%si */ | |
433 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
434 | static const char f16_7[] = | |
435 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ | |
436 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
437 | static const char f16_8[] = | |
438 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ | |
439 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
440 | static const char *const f32_patt[] = { | |
441 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, | |
442 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15 | |
443 | }; | |
444 | static const char *const f16_patt[] = { | |
c3332e24 | 445 | f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8, |
252b5132 RH |
446 | f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15 |
447 | }; | |
448 | ||
3e73aa7c JH |
449 | /* ??? We can't use these fillers for x86_64, since they often kills the |
450 | upper halves. Solve later. */ | |
451 | if (flag_code == CODE_64BIT) | |
452 | count = 1; | |
453 | ||
252b5132 RH |
454 | if (count > 0 && count <= 15) |
455 | { | |
3e73aa7c | 456 | if (flag_code == CODE_16BIT) |
252b5132 | 457 | { |
47926f60 KH |
458 | memcpy (fragP->fr_literal + fragP->fr_fix, |
459 | f16_patt[count - 1], count); | |
460 | if (count > 8) | |
461 | /* Adjust jump offset. */ | |
252b5132 RH |
462 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; |
463 | } | |
464 | else | |
47926f60 KH |
465 | memcpy (fragP->fr_literal + fragP->fr_fix, |
466 | f32_patt[count - 1], count); | |
252b5132 RH |
467 | fragP->fr_var = count; |
468 | } | |
469 | } | |
470 | ||
471 | static char *output_invalid PARAMS ((int c)); | |
472 | static int i386_operand PARAMS ((char *operand_string)); | |
473 | static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float)); | |
474 | static const reg_entry *parse_register PARAMS ((char *reg_string, | |
475 | char **end_op)); | |
476 | ||
477 | #ifndef I386COFF | |
478 | static void s_bss PARAMS ((int)); | |
479 | #endif | |
480 | ||
ce8a8b2f | 481 | symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
252b5132 RH |
482 | |
483 | static INLINE unsigned int | |
484 | mode_from_disp_size (t) | |
485 | unsigned int t; | |
486 | { | |
3e73aa7c | 487 | return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0; |
252b5132 RH |
488 | } |
489 | ||
490 | static INLINE int | |
491 | fits_in_signed_byte (num) | |
847f7ad4 | 492 | offsetT num; |
252b5132 RH |
493 | { |
494 | return (num >= -128) && (num <= 127); | |
47926f60 | 495 | } |
252b5132 RH |
496 | |
497 | static INLINE int | |
498 | fits_in_unsigned_byte (num) | |
847f7ad4 | 499 | offsetT num; |
252b5132 RH |
500 | { |
501 | return (num & 0xff) == num; | |
47926f60 | 502 | } |
252b5132 RH |
503 | |
504 | static INLINE int | |
505 | fits_in_unsigned_word (num) | |
847f7ad4 | 506 | offsetT num; |
252b5132 RH |
507 | { |
508 | return (num & 0xffff) == num; | |
47926f60 | 509 | } |
252b5132 RH |
510 | |
511 | static INLINE int | |
512 | fits_in_signed_word (num) | |
847f7ad4 | 513 | offsetT num; |
252b5132 RH |
514 | { |
515 | return (-32768 <= num) && (num <= 32767); | |
47926f60 | 516 | } |
3e73aa7c JH |
517 | static INLINE int |
518 | fits_in_signed_long (num) | |
519 | offsetT num ATTRIBUTE_UNUSED; | |
520 | { | |
521 | #ifndef BFD64 | |
522 | return 1; | |
523 | #else | |
524 | return (!(((offsetT) -1 << 31) & num) | |
525 | || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31)); | |
526 | #endif | |
527 | } /* fits_in_signed_long() */ | |
528 | static INLINE int | |
529 | fits_in_unsigned_long (num) | |
530 | offsetT num ATTRIBUTE_UNUSED; | |
531 | { | |
532 | #ifndef BFD64 | |
533 | return 1; | |
534 | #else | |
535 | return (num & (((offsetT) 2 << 31) - 1)) == num; | |
536 | #endif | |
537 | } /* fits_in_unsigned_long() */ | |
252b5132 RH |
538 | |
539 | static int | |
540 | smallest_imm_type (num) | |
847f7ad4 | 541 | offsetT num; |
252b5132 | 542 | { |
3e73aa7c JH |
543 | if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64) |
544 | && !(cpu_arch_flags & (CpuUnknown))) | |
e413e4e9 AM |
545 | { |
546 | /* This code is disabled on the 486 because all the Imm1 forms | |
547 | in the opcode table are slower on the i486. They're the | |
548 | versions with the implicitly specified single-position | |
549 | displacement, which has another syntax if you really want to | |
550 | use that form. */ | |
551 | if (num == 1) | |
3e73aa7c | 552 | return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64; |
e413e4e9 | 553 | } |
252b5132 | 554 | return (fits_in_signed_byte (num) |
3e73aa7c | 555 | ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64) |
252b5132 | 556 | : fits_in_unsigned_byte (num) |
3e73aa7c | 557 | ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64) |
252b5132 | 558 | : (fits_in_signed_word (num) || fits_in_unsigned_word (num)) |
3e73aa7c JH |
559 | ? (Imm16 | Imm32 | Imm32S | Imm64) |
560 | : fits_in_signed_long (num) | |
561 | ? (Imm32 | Imm32S | Imm64) | |
562 | : fits_in_unsigned_long (num) | |
563 | ? (Imm32 | Imm64) | |
564 | : Imm64); | |
47926f60 | 565 | } |
252b5132 | 566 | |
847f7ad4 AM |
567 | static offsetT |
568 | offset_in_range (val, size) | |
569 | offsetT val; | |
570 | int size; | |
571 | { | |
508866be | 572 | addressT mask; |
ba2adb93 | 573 | |
847f7ad4 AM |
574 | switch (size) |
575 | { | |
508866be L |
576 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
577 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 578 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
579 | #ifdef BFD64 |
580 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
581 | #endif | |
47926f60 | 582 | default: abort (); |
847f7ad4 AM |
583 | } |
584 | ||
ba2adb93 | 585 | /* If BFD64, sign extend val. */ |
3e73aa7c JH |
586 | if (!use_rela_relocations) |
587 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) | |
588 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
ba2adb93 | 589 | |
47926f60 | 590 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
591 | { |
592 | char buf1[40], buf2[40]; | |
593 | ||
594 | sprint_value (buf1, val); | |
595 | sprint_value (buf2, val & mask); | |
596 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
597 | } | |
598 | return val & mask; | |
599 | } | |
600 | ||
252b5132 RH |
601 | /* Returns 0 if attempting to add a prefix where one from the same |
602 | class already exists, 1 if non rep/repne added, 2 if rep/repne | |
603 | added. */ | |
604 | static int | |
605 | add_prefix (prefix) | |
606 | unsigned int prefix; | |
607 | { | |
608 | int ret = 1; | |
609 | int q; | |
610 | ||
3e73aa7c JH |
611 | if (prefix >= 0x40 && prefix < 0x50 && flag_code == CODE_64BIT) |
612 | q = REX_PREFIX; | |
613 | else | |
614 | switch (prefix) | |
615 | { | |
616 | default: | |
617 | abort (); | |
618 | ||
619 | case CS_PREFIX_OPCODE: | |
620 | case DS_PREFIX_OPCODE: | |
621 | case ES_PREFIX_OPCODE: | |
622 | case FS_PREFIX_OPCODE: | |
623 | case GS_PREFIX_OPCODE: | |
624 | case SS_PREFIX_OPCODE: | |
625 | q = SEG_PREFIX; | |
626 | break; | |
252b5132 | 627 | |
3e73aa7c JH |
628 | case REPNE_PREFIX_OPCODE: |
629 | case REPE_PREFIX_OPCODE: | |
630 | ret = 2; | |
631 | /* fall thru */ | |
632 | case LOCK_PREFIX_OPCODE: | |
633 | q = LOCKREP_PREFIX; | |
634 | break; | |
252b5132 | 635 | |
3e73aa7c JH |
636 | case FWAIT_OPCODE: |
637 | q = WAIT_PREFIX; | |
638 | break; | |
252b5132 | 639 | |
3e73aa7c JH |
640 | case ADDR_PREFIX_OPCODE: |
641 | q = ADDR_PREFIX; | |
642 | break; | |
252b5132 | 643 | |
3e73aa7c JH |
644 | case DATA_PREFIX_OPCODE: |
645 | q = DATA_PREFIX; | |
646 | break; | |
647 | } | |
252b5132 RH |
648 | |
649 | if (i.prefix[q]) | |
650 | { | |
651 | as_bad (_("same type of prefix used twice")); | |
652 | return 0; | |
653 | } | |
654 | ||
655 | i.prefixes += 1; | |
656 | i.prefix[q] = prefix; | |
657 | return ret; | |
658 | } | |
659 | ||
660 | static void | |
3e73aa7c | 661 | set_code_flag (value) |
e5cb08ac | 662 | int value; |
eecb386c | 663 | { |
3e73aa7c JH |
664 | flag_code = value; |
665 | cpu_arch_flags &= ~(Cpu64 | CpuNo64); | |
666 | cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64); | |
667 | if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer)) | |
668 | { | |
669 | as_bad (_("64bit mode not supported on this CPU.")); | |
670 | } | |
671 | if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386)) | |
672 | { | |
673 | as_bad (_("32bit mode not supported on this CPU.")); | |
674 | } | |
eecb386c AM |
675 | stackop_size = '\0'; |
676 | } | |
677 | ||
678 | static void | |
3e73aa7c JH |
679 | set_16bit_gcc_code_flag (new_code_flag) |
680 | int new_code_flag; | |
252b5132 | 681 | { |
3e73aa7c JH |
682 | flag_code = new_code_flag; |
683 | cpu_arch_flags &= ~(Cpu64 | CpuNo64); | |
684 | cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64); | |
685 | stackop_size = 'l'; | |
252b5132 RH |
686 | } |
687 | ||
688 | static void | |
689 | set_intel_syntax (syntax_flag) | |
eecb386c | 690 | int syntax_flag; |
252b5132 RH |
691 | { |
692 | /* Find out if register prefixing is specified. */ | |
693 | int ask_naked_reg = 0; | |
694 | ||
695 | SKIP_WHITESPACE (); | |
696 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
697 | { | |
698 | char *string = input_line_pointer; | |
699 | int e = get_symbol_end (); | |
700 | ||
47926f60 | 701 | if (strcmp (string, "prefix") == 0) |
252b5132 | 702 | ask_naked_reg = 1; |
47926f60 | 703 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
704 | ask_naked_reg = -1; |
705 | else | |
d0b47220 | 706 | as_bad (_("bad argument to syntax directive.")); |
252b5132 RH |
707 | *input_line_pointer = e; |
708 | } | |
709 | demand_empty_rest_of_line (); | |
c3332e24 | 710 | |
252b5132 RH |
711 | intel_syntax = syntax_flag; |
712 | ||
713 | if (ask_naked_reg == 0) | |
714 | { | |
715 | #ifdef BFD_ASSEMBLER | |
716 | allow_naked_reg = (intel_syntax | |
24eab124 | 717 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); |
252b5132 | 718 | #else |
47926f60 KH |
719 | /* Conservative default. */ |
720 | allow_naked_reg = 0; | |
252b5132 RH |
721 | #endif |
722 | } | |
723 | else | |
724 | allow_naked_reg = (ask_naked_reg < 0); | |
725 | } | |
726 | ||
e413e4e9 AM |
727 | static void |
728 | set_cpu_arch (dummy) | |
47926f60 | 729 | int dummy ATTRIBUTE_UNUSED; |
e413e4e9 | 730 | { |
47926f60 | 731 | SKIP_WHITESPACE (); |
e413e4e9 AM |
732 | |
733 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
734 | { | |
735 | char *string = input_line_pointer; | |
736 | int e = get_symbol_end (); | |
737 | int i; | |
738 | ||
739 | for (i = 0; cpu_arch[i].name; i++) | |
740 | { | |
741 | if (strcmp (string, cpu_arch[i].name) == 0) | |
742 | { | |
743 | cpu_arch_name = cpu_arch[i].name; | |
fddf5b5b AM |
744 | cpu_arch_flags = (cpu_arch[i].flags |
745 | | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64)); | |
e413e4e9 AM |
746 | break; |
747 | } | |
748 | } | |
749 | if (!cpu_arch[i].name) | |
750 | as_bad (_("no such architecture: `%s'"), string); | |
751 | ||
752 | *input_line_pointer = e; | |
753 | } | |
754 | else | |
755 | as_bad (_("missing cpu architecture")); | |
756 | ||
fddf5b5b AM |
757 | no_cond_jump_promotion = 0; |
758 | if (*input_line_pointer == ',' | |
759 | && ! is_end_of_line[(unsigned char) input_line_pointer[1]]) | |
760 | { | |
761 | char *string = ++input_line_pointer; | |
762 | int e = get_symbol_end (); | |
763 | ||
764 | if (strcmp (string, "nojumps") == 0) | |
765 | no_cond_jump_promotion = 1; | |
766 | else if (strcmp (string, "jumps") == 0) | |
767 | ; | |
768 | else | |
769 | as_bad (_("no such architecture modifier: `%s'"), string); | |
770 | ||
771 | *input_line_pointer = e; | |
772 | } | |
773 | ||
e413e4e9 AM |
774 | demand_empty_rest_of_line (); |
775 | } | |
776 | ||
252b5132 RH |
777 | const pseudo_typeS md_pseudo_table[] = |
778 | { | |
252b5132 RH |
779 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) |
780 | {"align", s_align_bytes, 0}, | |
781 | #else | |
782 | {"align", s_align_ptwo, 0}, | |
e413e4e9 AM |
783 | #endif |
784 | {"arch", set_cpu_arch, 0}, | |
785 | #ifndef I386COFF | |
786 | {"bss", s_bss, 0}, | |
252b5132 RH |
787 | #endif |
788 | {"ffloat", float_cons, 'f'}, | |
789 | {"dfloat", float_cons, 'd'}, | |
790 | {"tfloat", float_cons, 'x'}, | |
791 | {"value", cons, 2}, | |
792 | {"noopt", s_ignore, 0}, | |
793 | {"optim", s_ignore, 0}, | |
3e73aa7c JH |
794 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, |
795 | {"code16", set_code_flag, CODE_16BIT}, | |
796 | {"code32", set_code_flag, CODE_32BIT}, | |
797 | {"code64", set_code_flag, CODE_64BIT}, | |
252b5132 RH |
798 | {"intel_syntax", set_intel_syntax, 1}, |
799 | {"att_syntax", set_intel_syntax, 0}, | |
316e2c05 RH |
800 | {"file", dwarf2_directive_file, 0}, |
801 | {"loc", dwarf2_directive_loc, 0}, | |
252b5132 RH |
802 | {0, 0, 0} |
803 | }; | |
804 | ||
47926f60 | 805 | /* For interface with expression (). */ |
252b5132 RH |
806 | extern char *input_line_pointer; |
807 | ||
47926f60 | 808 | /* Hash table for instruction mnemonic lookup. */ |
252b5132 | 809 | static struct hash_control *op_hash; |
47926f60 KH |
810 | |
811 | /* Hash table for register lookup. */ | |
252b5132 RH |
812 | static struct hash_control *reg_hash; |
813 | \f | |
b9d79e03 JH |
814 | #ifdef BFD_ASSEMBLER |
815 | unsigned long | |
816 | i386_mach () | |
817 | { | |
818 | if (!strcmp (default_arch, "x86_64")) | |
819 | return bfd_mach_x86_64; | |
820 | else if (!strcmp (default_arch, "i386")) | |
821 | return bfd_mach_i386_i386; | |
822 | else | |
823 | as_fatal (_("Unknown architecture")); | |
824 | } | |
825 | #endif | |
826 | \f | |
252b5132 RH |
827 | void |
828 | md_begin () | |
829 | { | |
830 | const char *hash_err; | |
831 | ||
47926f60 | 832 | /* Initialize op_hash hash table. */ |
252b5132 RH |
833 | op_hash = hash_new (); |
834 | ||
835 | { | |
836 | register const template *optab; | |
837 | register templates *core_optab; | |
838 | ||
47926f60 KH |
839 | /* Setup for loop. */ |
840 | optab = i386_optab; | |
252b5132 RH |
841 | core_optab = (templates *) xmalloc (sizeof (templates)); |
842 | core_optab->start = optab; | |
843 | ||
844 | while (1) | |
845 | { | |
846 | ++optab; | |
847 | if (optab->name == NULL | |
848 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
849 | { | |
850 | /* different name --> ship out current template list; | |
47926f60 | 851 | add to hash table; & begin anew. */ |
252b5132 RH |
852 | core_optab->end = optab; |
853 | hash_err = hash_insert (op_hash, | |
854 | (optab - 1)->name, | |
855 | (PTR) core_optab); | |
856 | if (hash_err) | |
857 | { | |
252b5132 RH |
858 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
859 | (optab - 1)->name, | |
860 | hash_err); | |
861 | } | |
862 | if (optab->name == NULL) | |
863 | break; | |
864 | core_optab = (templates *) xmalloc (sizeof (templates)); | |
865 | core_optab->start = optab; | |
866 | } | |
867 | } | |
868 | } | |
869 | ||
47926f60 | 870 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
871 | reg_hash = hash_new (); |
872 | { | |
873 | register const reg_entry *regtab; | |
874 | ||
875 | for (regtab = i386_regtab; | |
876 | regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]); | |
877 | regtab++) | |
878 | { | |
879 | hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab); | |
880 | if (hash_err) | |
3e73aa7c JH |
881 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
882 | regtab->reg_name, | |
883 | hash_err); | |
252b5132 RH |
884 | } |
885 | } | |
886 | ||
47926f60 | 887 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 RH |
888 | { |
889 | register int c; | |
890 | register char *p; | |
891 | ||
892 | for (c = 0; c < 256; c++) | |
893 | { | |
894 | if (isdigit (c)) | |
895 | { | |
896 | digit_chars[c] = c; | |
897 | mnemonic_chars[c] = c; | |
898 | register_chars[c] = c; | |
899 | operand_chars[c] = c; | |
900 | } | |
901 | else if (islower (c)) | |
902 | { | |
903 | mnemonic_chars[c] = c; | |
904 | register_chars[c] = c; | |
905 | operand_chars[c] = c; | |
906 | } | |
907 | else if (isupper (c)) | |
908 | { | |
909 | mnemonic_chars[c] = tolower (c); | |
910 | register_chars[c] = mnemonic_chars[c]; | |
911 | operand_chars[c] = c; | |
912 | } | |
913 | ||
914 | if (isalpha (c) || isdigit (c)) | |
915 | identifier_chars[c] = c; | |
916 | else if (c >= 128) | |
917 | { | |
918 | identifier_chars[c] = c; | |
919 | operand_chars[c] = c; | |
920 | } | |
921 | } | |
922 | ||
923 | #ifdef LEX_AT | |
924 | identifier_chars['@'] = '@'; | |
925 | #endif | |
252b5132 RH |
926 | digit_chars['-'] = '-'; |
927 | identifier_chars['_'] = '_'; | |
928 | identifier_chars['.'] = '.'; | |
929 | ||
930 | for (p = operand_special_chars; *p != '\0'; p++) | |
931 | operand_chars[(unsigned char) *p] = *p; | |
932 | } | |
933 | ||
934 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
935 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
936 | { | |
937 | record_alignment (text_section, 2); | |
938 | record_alignment (data_section, 2); | |
939 | record_alignment (bss_section, 2); | |
940 | } | |
941 | #endif | |
942 | } | |
943 | ||
944 | void | |
945 | i386_print_statistics (file) | |
946 | FILE *file; | |
947 | { | |
948 | hash_print_statistics (file, "i386 opcode", op_hash); | |
949 | hash_print_statistics (file, "i386 register", reg_hash); | |
950 | } | |
951 | \f | |
252b5132 RH |
952 | #ifdef DEBUG386 |
953 | ||
ce8a8b2f | 954 | /* Debugging routines for md_assemble. */ |
252b5132 RH |
955 | static void pi PARAMS ((char *, i386_insn *)); |
956 | static void pte PARAMS ((template *)); | |
957 | static void pt PARAMS ((unsigned int)); | |
958 | static void pe PARAMS ((expressionS *)); | |
959 | static void ps PARAMS ((symbolS *)); | |
960 | ||
961 | static void | |
962 | pi (line, x) | |
963 | char *line; | |
964 | i386_insn *x; | |
965 | { | |
09f131f2 | 966 | unsigned int i; |
252b5132 RH |
967 | |
968 | fprintf (stdout, "%s: template ", line); | |
969 | pte (&x->tm); | |
09f131f2 JH |
970 | fprintf (stdout, " address: base %s index %s scale %x\n", |
971 | x->base_reg ? x->base_reg->reg_name : "none", | |
972 | x->index_reg ? x->index_reg->reg_name : "none", | |
973 | x->log2_scale_factor); | |
974 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 975 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
976 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
977 | x->sib.base, x->sib.index, x->sib.scale); | |
978 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
979 | x->rex.mode64, x->rex.extX, x->rex.extY, x->rex.extZ); | |
252b5132 RH |
980 | for (i = 0; i < x->operands; i++) |
981 | { | |
982 | fprintf (stdout, " #%d: ", i + 1); | |
983 | pt (x->types[i]); | |
984 | fprintf (stdout, "\n"); | |
985 | if (x->types[i] | |
3f4438ab | 986 | & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM)) |
520dc8e8 | 987 | fprintf (stdout, "%s\n", x->op[i].regs->reg_name); |
252b5132 | 988 | if (x->types[i] & Imm) |
520dc8e8 | 989 | pe (x->op[i].imms); |
252b5132 | 990 | if (x->types[i] & Disp) |
520dc8e8 | 991 | pe (x->op[i].disps); |
252b5132 RH |
992 | } |
993 | } | |
994 | ||
995 | static void | |
996 | pte (t) | |
997 | template *t; | |
998 | { | |
09f131f2 | 999 | unsigned int i; |
252b5132 | 1000 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 1001 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
1002 | if (t->extension_opcode != None) |
1003 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
1004 | if (t->opcode_modifier & D) | |
1005 | fprintf (stdout, "D"); | |
1006 | if (t->opcode_modifier & W) | |
1007 | fprintf (stdout, "W"); | |
1008 | fprintf (stdout, "\n"); | |
1009 | for (i = 0; i < t->operands; i++) | |
1010 | { | |
1011 | fprintf (stdout, " #%d type ", i + 1); | |
1012 | pt (t->operand_types[i]); | |
1013 | fprintf (stdout, "\n"); | |
1014 | } | |
1015 | } | |
1016 | ||
1017 | static void | |
1018 | pe (e) | |
1019 | expressionS *e; | |
1020 | { | |
24eab124 | 1021 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
1022 | fprintf (stdout, " add_number %ld (%lx)\n", |
1023 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
1024 | if (e->X_add_symbol) |
1025 | { | |
1026 | fprintf (stdout, " add_symbol "); | |
1027 | ps (e->X_add_symbol); | |
1028 | fprintf (stdout, "\n"); | |
1029 | } | |
1030 | if (e->X_op_symbol) | |
1031 | { | |
1032 | fprintf (stdout, " op_symbol "); | |
1033 | ps (e->X_op_symbol); | |
1034 | fprintf (stdout, "\n"); | |
1035 | } | |
1036 | } | |
1037 | ||
1038 | static void | |
1039 | ps (s) | |
1040 | symbolS *s; | |
1041 | { | |
1042 | fprintf (stdout, "%s type %s%s", | |
1043 | S_GET_NAME (s), | |
1044 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
1045 | segment_name (S_GET_SEGMENT (s))); | |
1046 | } | |
1047 | ||
1048 | struct type_name | |
1049 | { | |
1050 | unsigned int mask; | |
1051 | char *tname; | |
1052 | } | |
1053 | ||
1054 | type_names[] = | |
1055 | { | |
1056 | { Reg8, "r8" }, | |
1057 | { Reg16, "r16" }, | |
1058 | { Reg32, "r32" }, | |
09f131f2 | 1059 | { Reg64, "r64" }, |
252b5132 RH |
1060 | { Imm8, "i8" }, |
1061 | { Imm8S, "i8s" }, | |
1062 | { Imm16, "i16" }, | |
1063 | { Imm32, "i32" }, | |
09f131f2 JH |
1064 | { Imm32S, "i32s" }, |
1065 | { Imm64, "i64" }, | |
252b5132 RH |
1066 | { Imm1, "i1" }, |
1067 | { BaseIndex, "BaseIndex" }, | |
1068 | { Disp8, "d8" }, | |
1069 | { Disp16, "d16" }, | |
1070 | { Disp32, "d32" }, | |
09f131f2 JH |
1071 | { Disp32S, "d32s" }, |
1072 | { Disp64, "d64" }, | |
252b5132 RH |
1073 | { InOutPortReg, "InOutPortReg" }, |
1074 | { ShiftCount, "ShiftCount" }, | |
1075 | { Control, "control reg" }, | |
1076 | { Test, "test reg" }, | |
1077 | { Debug, "debug reg" }, | |
1078 | { FloatReg, "FReg" }, | |
1079 | { FloatAcc, "FAcc" }, | |
1080 | { SReg2, "SReg2" }, | |
1081 | { SReg3, "SReg3" }, | |
1082 | { Acc, "Acc" }, | |
1083 | { JumpAbsolute, "Jump Absolute" }, | |
1084 | { RegMMX, "rMMX" }, | |
3f4438ab | 1085 | { RegXMM, "rXMM" }, |
252b5132 RH |
1086 | { EsSeg, "es" }, |
1087 | { 0, "" } | |
1088 | }; | |
1089 | ||
1090 | static void | |
1091 | pt (t) | |
1092 | unsigned int t; | |
1093 | { | |
1094 | register struct type_name *ty; | |
1095 | ||
09f131f2 JH |
1096 | for (ty = type_names; ty->mask; ty++) |
1097 | if (t & ty->mask) | |
1098 | fprintf (stdout, "%s, ", ty->tname); | |
252b5132 RH |
1099 | fflush (stdout); |
1100 | } | |
1101 | ||
1102 | #endif /* DEBUG386 */ | |
1103 | \f | |
1104 | int | |
1105 | tc_i386_force_relocation (fixp) | |
1106 | struct fix *fixp; | |
1107 | { | |
1108 | #ifdef BFD_ASSEMBLER | |
1109 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
1110 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1111 | return 1; | |
1112 | return 0; | |
1113 | #else | |
ce8a8b2f | 1114 | /* For COFF. */ |
f6af82bd | 1115 | return fixp->fx_r_type == 7; |
252b5132 RH |
1116 | #endif |
1117 | } | |
1118 | ||
1119 | #ifdef BFD_ASSEMBLER | |
252b5132 RH |
1120 | |
1121 | static bfd_reloc_code_real_type | |
3e73aa7c | 1122 | reloc (size, pcrel, sign, other) |
252b5132 RH |
1123 | int size; |
1124 | int pcrel; | |
3e73aa7c | 1125 | int sign; |
252b5132 RH |
1126 | bfd_reloc_code_real_type other; |
1127 | { | |
47926f60 KH |
1128 | if (other != NO_RELOC) |
1129 | return other; | |
252b5132 RH |
1130 | |
1131 | if (pcrel) | |
1132 | { | |
3e73aa7c | 1133 | if (!sign) |
e5cb08ac | 1134 | as_bad (_("There are no unsigned pc-relative relocations")); |
252b5132 RH |
1135 | switch (size) |
1136 | { | |
1137 | case 1: return BFD_RELOC_8_PCREL; | |
1138 | case 2: return BFD_RELOC_16_PCREL; | |
1139 | case 4: return BFD_RELOC_32_PCREL; | |
1140 | } | |
d0b47220 | 1141 | as_bad (_("can not do %d byte pc-relative relocation"), size); |
252b5132 RH |
1142 | } |
1143 | else | |
1144 | { | |
3e73aa7c | 1145 | if (sign) |
e5cb08ac | 1146 | switch (size) |
3e73aa7c JH |
1147 | { |
1148 | case 4: return BFD_RELOC_X86_64_32S; | |
1149 | } | |
1150 | else | |
1151 | switch (size) | |
1152 | { | |
1153 | case 1: return BFD_RELOC_8; | |
1154 | case 2: return BFD_RELOC_16; | |
1155 | case 4: return BFD_RELOC_32; | |
1156 | case 8: return BFD_RELOC_64; | |
1157 | } | |
1158 | as_bad (_("can not do %s %d byte relocation"), | |
1159 | sign ? "signed" : "unsigned", size); | |
252b5132 RH |
1160 | } |
1161 | ||
bfb32b52 | 1162 | abort (); |
252b5132 RH |
1163 | return BFD_RELOC_NONE; |
1164 | } | |
1165 | ||
47926f60 KH |
1166 | /* Here we decide which fixups can be adjusted to make them relative to |
1167 | the beginning of the section instead of the symbol. Basically we need | |
1168 | to make sure that the dynamic relocations are done correctly, so in | |
1169 | some cases we force the original symbol to be used. */ | |
1170 | ||
252b5132 | 1171 | int |
c0c949c7 | 1172 | tc_i386_fix_adjustable (fixP) |
47926f60 | 1173 | fixS *fixP; |
252b5132 | 1174 | { |
6d249963 | 1175 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
79d292aa ILT |
1176 | /* Prevent all adjustments to global symbols, or else dynamic |
1177 | linking will not work correctly. */ | |
b98ef147 AM |
1178 | if (S_IS_EXTERNAL (fixP->fx_addsy) |
1179 | || S_IS_WEAK (fixP->fx_addsy)) | |
252b5132 RH |
1180 | return 0; |
1181 | #endif | |
ce8a8b2f | 1182 | /* adjust_reloc_syms doesn't know about the GOT. */ |
252b5132 RH |
1183 | if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF |
1184 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 | |
1185 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
3e73aa7c JH |
1186 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
1187 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
80b3ee89 | 1188 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
252b5132 RH |
1189 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
1190 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1191 | return 0; | |
1192 | return 1; | |
1193 | } | |
1194 | #else | |
ec56dfb4 L |
1195 | #define reloc(SIZE,PCREL,SIGN,OTHER) 0 |
1196 | #define BFD_RELOC_16 0 | |
1197 | #define BFD_RELOC_32 0 | |
1198 | #define BFD_RELOC_16_PCREL 0 | |
1199 | #define BFD_RELOC_32_PCREL 0 | |
1200 | #define BFD_RELOC_386_PLT32 0 | |
1201 | #define BFD_RELOC_386_GOT32 0 | |
1202 | #define BFD_RELOC_386_GOTOFF 0 | |
1203 | #define BFD_RELOC_X86_64_PLT32 0 | |
1204 | #define BFD_RELOC_X86_64_GOT32 0 | |
1205 | #define BFD_RELOC_X86_64_GOTPCREL 0 | |
252b5132 RH |
1206 | #endif |
1207 | ||
47926f60 | 1208 | static int intel_float_operand PARAMS ((char *mnemonic)); |
b4cac588 AM |
1209 | |
1210 | static int | |
252b5132 RH |
1211 | intel_float_operand (mnemonic) |
1212 | char *mnemonic; | |
1213 | { | |
47926f60 | 1214 | if (mnemonic[0] == 'f' && mnemonic[1] == 'i') |
cc5ca5ce | 1215 | return 2; |
252b5132 RH |
1216 | |
1217 | if (mnemonic[0] == 'f') | |
1218 | return 1; | |
1219 | ||
1220 | return 0; | |
1221 | } | |
1222 | ||
1223 | /* This is the guts of the machine-dependent assembler. LINE points to a | |
1224 | machine dependent instruction. This function is supposed to emit | |
1225 | the frags/bytes it assembles to. */ | |
1226 | ||
1227 | void | |
1228 | md_assemble (line) | |
1229 | char *line; | |
1230 | { | |
47926f60 | 1231 | /* Points to template once we've found it. */ |
252b5132 RH |
1232 | const template *t; |
1233 | ||
fddf5b5b AM |
1234 | /* Count the size of the instruction generated. Does not include |
1235 | variable part of jump insns before relax. */ | |
252b5132 RH |
1236 | int insn_size = 0; |
1237 | ||
1238 | int j; | |
1239 | ||
1240 | char mnemonic[MAX_MNEM_SIZE]; | |
1241 | ||
47926f60 | 1242 | /* Initialize globals. */ |
252b5132 RH |
1243 | memset (&i, '\0', sizeof (i)); |
1244 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 1245 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
1246 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
1247 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 1248 | save_stack_p = save_stack; |
252b5132 RH |
1249 | |
1250 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
1251 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 1252 | start of a (possibly prefixed) mnemonic. */ |
252b5132 RH |
1253 | { |
1254 | char *l = line; | |
1255 | char *token_start = l; | |
1256 | char *mnem_p; | |
1257 | ||
47926f60 | 1258 | /* Non-zero if we found a prefix only acceptable with string insns. */ |
252b5132 RH |
1259 | const char *expecting_string_instruction = NULL; |
1260 | ||
1261 | while (1) | |
1262 | { | |
1263 | mnem_p = mnemonic; | |
1264 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
1265 | { | |
1266 | mnem_p++; | |
1267 | if (mnem_p >= mnemonic + sizeof (mnemonic)) | |
1268 | { | |
e413e4e9 | 1269 | as_bad (_("no such instruction: `%s'"), token_start); |
252b5132 RH |
1270 | return; |
1271 | } | |
1272 | l++; | |
1273 | } | |
1274 | if (!is_space_char (*l) | |
1275 | && *l != END_OF_INSN | |
1276 | && *l != PREFIX_SEPARATOR) | |
1277 | { | |
1278 | as_bad (_("invalid character %s in mnemonic"), | |
1279 | output_invalid (*l)); | |
1280 | return; | |
1281 | } | |
1282 | if (token_start == l) | |
1283 | { | |
1284 | if (*l == PREFIX_SEPARATOR) | |
1285 | as_bad (_("expecting prefix; got nothing")); | |
1286 | else | |
1287 | as_bad (_("expecting mnemonic; got nothing")); | |
1288 | return; | |
1289 | } | |
1290 | ||
1291 | /* Look up instruction (or prefix) via hash table. */ | |
1292 | current_templates = hash_find (op_hash, mnemonic); | |
1293 | ||
1294 | if (*l != END_OF_INSN | |
1295 | && (! is_space_char (*l) || l[1] != END_OF_INSN) | |
1296 | && current_templates | |
1297 | && (current_templates->start->opcode_modifier & IsPrefix)) | |
1298 | { | |
1299 | /* If we are in 16-bit mode, do not allow addr16 or data16. | |
1300 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
1301 | if ((current_templates->start->opcode_modifier & (Size16 | Size32)) | |
1302 | && (((current_templates->start->opcode_modifier & Size32) != 0) | |
3e73aa7c | 1303 | ^ (flag_code == CODE_16BIT))) |
252b5132 RH |
1304 | { |
1305 | as_bad (_("redundant %s prefix"), | |
1306 | current_templates->start->name); | |
1307 | return; | |
1308 | } | |
1309 | /* Add prefix, checking for repeated prefixes. */ | |
1310 | switch (add_prefix (current_templates->start->base_opcode)) | |
1311 | { | |
1312 | case 0: | |
1313 | return; | |
1314 | case 2: | |
47926f60 | 1315 | expecting_string_instruction = current_templates->start->name; |
252b5132 RH |
1316 | break; |
1317 | } | |
1318 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
1319 | token_start = ++l; | |
1320 | } | |
1321 | else | |
1322 | break; | |
1323 | } | |
1324 | ||
1325 | if (!current_templates) | |
1326 | { | |
24eab124 | 1327 | /* See if we can get a match by trimming off a suffix. */ |
252b5132 RH |
1328 | switch (mnem_p[-1]) |
1329 | { | |
252b5132 RH |
1330 | case WORD_MNEM_SUFFIX: |
1331 | case BYTE_MNEM_SUFFIX: | |
3e73aa7c | 1332 | case QWORD_MNEM_SUFFIX: |
252b5132 RH |
1333 | i.suffix = mnem_p[-1]; |
1334 | mnem_p[-1] = '\0'; | |
1335 | current_templates = hash_find (op_hash, mnemonic); | |
24eab124 | 1336 | break; |
f16b83df JH |
1337 | case SHORT_MNEM_SUFFIX: |
1338 | case LONG_MNEM_SUFFIX: | |
1339 | if (!intel_syntax) | |
1340 | { | |
1341 | i.suffix = mnem_p[-1]; | |
1342 | mnem_p[-1] = '\0'; | |
1343 | current_templates = hash_find (op_hash, mnemonic); | |
1344 | } | |
1345 | break; | |
24eab124 | 1346 | |
ce8a8b2f | 1347 | /* Intel Syntax. */ |
f16b83df | 1348 | case 'd': |
24eab124 AM |
1349 | if (intel_syntax) |
1350 | { | |
f16b83df JH |
1351 | if (intel_float_operand (mnemonic)) |
1352 | i.suffix = SHORT_MNEM_SUFFIX; | |
1353 | else | |
1354 | i.suffix = LONG_MNEM_SUFFIX; | |
24eab124 AM |
1355 | mnem_p[-1] = '\0'; |
1356 | current_templates = hash_find (op_hash, mnemonic); | |
24eab124 | 1357 | } |
f16b83df | 1358 | break; |
252b5132 RH |
1359 | } |
1360 | if (!current_templates) | |
1361 | { | |
e413e4e9 | 1362 | as_bad (_("no such instruction: `%s'"), token_start); |
252b5132 RH |
1363 | return; |
1364 | } | |
1365 | } | |
1366 | ||
e413e4e9 AM |
1367 | /* Check if instruction is supported on specified architecture. */ |
1368 | if (cpu_arch_flags != 0) | |
1369 | { | |
3e73aa7c JH |
1370 | if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64)) |
1371 | & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))) | |
e413e4e9 AM |
1372 | { |
1373 | as_warn (_("`%s' is not supported on `%s'"), | |
1374 | current_templates->start->name, cpu_arch_name); | |
1375 | } | |
3e73aa7c | 1376 | else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT)) |
e413e4e9 AM |
1377 | { |
1378 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
1379 | } | |
1380 | } | |
1381 | ||
ce8a8b2f | 1382 | /* Check for rep/repne without a string instruction. */ |
252b5132 RH |
1383 | if (expecting_string_instruction |
1384 | && !(current_templates->start->opcode_modifier & IsString)) | |
1385 | { | |
1386 | as_bad (_("expecting string instruction after `%s'"), | |
1387 | expecting_string_instruction); | |
1388 | return; | |
1389 | } | |
1390 | ||
47926f60 | 1391 | /* There may be operands to parse. */ |
252b5132 RH |
1392 | if (*l != END_OF_INSN) |
1393 | { | |
47926f60 | 1394 | /* 1 if operand is pending after ','. */ |
252b5132 RH |
1395 | unsigned int expecting_operand = 0; |
1396 | ||
47926f60 | 1397 | /* Non-zero if operand parens not balanced. */ |
252b5132 RH |
1398 | unsigned int paren_not_balanced; |
1399 | ||
1400 | do | |
1401 | { | |
ce8a8b2f | 1402 | /* Skip optional white space before operand. */ |
252b5132 RH |
1403 | if (is_space_char (*l)) |
1404 | ++l; | |
1405 | if (!is_operand_char (*l) && *l != END_OF_INSN) | |
1406 | { | |
1407 | as_bad (_("invalid character %s before operand %d"), | |
1408 | output_invalid (*l), | |
1409 | i.operands + 1); | |
1410 | return; | |
1411 | } | |
1412 | token_start = l; /* after white space */ | |
1413 | paren_not_balanced = 0; | |
1414 | while (paren_not_balanced || *l != ',') | |
1415 | { | |
1416 | if (*l == END_OF_INSN) | |
1417 | { | |
1418 | if (paren_not_balanced) | |
1419 | { | |
24eab124 | 1420 | if (!intel_syntax) |
252b5132 RH |
1421 | as_bad (_("unbalanced parenthesis in operand %d."), |
1422 | i.operands + 1); | |
24eab124 | 1423 | else |
252b5132 RH |
1424 | as_bad (_("unbalanced brackets in operand %d."), |
1425 | i.operands + 1); | |
1426 | return; | |
1427 | } | |
1428 | else | |
1429 | break; /* we are done */ | |
1430 | } | |
1431 | else if (!is_operand_char (*l) && !is_space_char (*l)) | |
1432 | { | |
1433 | as_bad (_("invalid character %s in operand %d"), | |
1434 | output_invalid (*l), | |
1435 | i.operands + 1); | |
1436 | return; | |
1437 | } | |
24eab124 AM |
1438 | if (!intel_syntax) |
1439 | { | |
252b5132 RH |
1440 | if (*l == '(') |
1441 | ++paren_not_balanced; | |
1442 | if (*l == ')') | |
1443 | --paren_not_balanced; | |
24eab124 AM |
1444 | } |
1445 | else | |
1446 | { | |
252b5132 RH |
1447 | if (*l == '[') |
1448 | ++paren_not_balanced; | |
1449 | if (*l == ']') | |
1450 | --paren_not_balanced; | |
24eab124 | 1451 | } |
252b5132 RH |
1452 | l++; |
1453 | } | |
1454 | if (l != token_start) | |
47926f60 | 1455 | { /* Yes, we've read in another operand. */ |
252b5132 RH |
1456 | unsigned int operand_ok; |
1457 | this_operand = i.operands++; | |
1458 | if (i.operands > MAX_OPERANDS) | |
1459 | { | |
1460 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
1461 | MAX_OPERANDS); | |
1462 | return; | |
1463 | } | |
47926f60 | 1464 | /* Now parse operand adding info to 'i' as we go along. */ |
252b5132 RH |
1465 | END_STRING_AND_SAVE (l); |
1466 | ||
24eab124 | 1467 | if (intel_syntax) |
47926f60 KH |
1468 | operand_ok = |
1469 | i386_intel_operand (token_start, | |
1470 | intel_float_operand (mnemonic)); | |
24eab124 AM |
1471 | else |
1472 | operand_ok = i386_operand (token_start); | |
252b5132 | 1473 | |
ce8a8b2f | 1474 | RESTORE_END_STRING (l); |
252b5132 RH |
1475 | if (!operand_ok) |
1476 | return; | |
1477 | } | |
1478 | else | |
1479 | { | |
1480 | if (expecting_operand) | |
1481 | { | |
1482 | expecting_operand_after_comma: | |
1483 | as_bad (_("expecting operand after ','; got nothing")); | |
1484 | return; | |
1485 | } | |
1486 | if (*l == ',') | |
1487 | { | |
1488 | as_bad (_("expecting operand before ','; got nothing")); | |
1489 | return; | |
1490 | } | |
1491 | } | |
1492 | ||
ce8a8b2f | 1493 | /* Now *l must be either ',' or END_OF_INSN. */ |
252b5132 RH |
1494 | if (*l == ',') |
1495 | { | |
1496 | if (*++l == END_OF_INSN) | |
ce8a8b2f AM |
1497 | { |
1498 | /* Just skip it, if it's \n complain. */ | |
252b5132 RH |
1499 | goto expecting_operand_after_comma; |
1500 | } | |
1501 | expecting_operand = 1; | |
1502 | } | |
1503 | } | |
ce8a8b2f | 1504 | while (*l != END_OF_INSN); |
252b5132 RH |
1505 | } |
1506 | } | |
1507 | ||
1508 | /* Now we've parsed the mnemonic into a set of templates, and have the | |
1509 | operands at hand. | |
1510 | ||
1511 | Next, we find a template that matches the given insn, | |
1512 | making sure the overlap of the given operands types is consistent | |
47926f60 | 1513 | with the template operand types. */ |
252b5132 RH |
1514 | |
1515 | #define MATCH(overlap, given, template) \ | |
3138f287 AM |
1516 | ((overlap & ~JumpAbsolute) \ |
1517 | && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute))) | |
252b5132 RH |
1518 | |
1519 | /* If given types r0 and r1 are registers they must be of the same type | |
1520 | unless the expected operand type register overlap is null. | |
1521 | Note that Acc in a template matches every size of reg. */ | |
1522 | #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \ | |
1523 | ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \ | |
1524 | ((g0) & Reg) == ((g1) & Reg) || \ | |
1525 | ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 ) | |
1526 | ||
1527 | { | |
1528 | register unsigned int overlap0, overlap1; | |
252b5132 RH |
1529 | unsigned int overlap2; |
1530 | unsigned int found_reverse_match; | |
1531 | int suffix_check; | |
1532 | ||
cc5ca5ce AM |
1533 | /* All intel opcodes have reversed operands except for "bound" and |
1534 | "enter". We also don't reverse intersegment "jmp" and "call" | |
1535 | instructions with 2 immediate operands so that the immediate segment | |
1536 | precedes the offset, as it does when in AT&T mode. "enter" and the | |
1537 | intersegment "jmp" and "call" instructions are the only ones that | |
1538 | have two immediate operands. */ | |
520dc8e8 | 1539 | if (intel_syntax && i.operands > 1 |
cc5ca5ce AM |
1540 | && (strcmp (mnemonic, "bound") != 0) |
1541 | && !((i.types[0] & Imm) && (i.types[1] & Imm))) | |
252b5132 | 1542 | { |
520dc8e8 | 1543 | union i386_op temp_op; |
24eab124 | 1544 | unsigned int temp_type; |
f3c180ae | 1545 | RELOC_ENUM temp_reloc; |
24eab124 | 1546 | int xchg1 = 0; |
ab9da554 | 1547 | int xchg2 = 0; |
252b5132 | 1548 | |
24eab124 AM |
1549 | if (i.operands == 2) |
1550 | { | |
1551 | xchg1 = 0; | |
1552 | xchg2 = 1; | |
1553 | } | |
1554 | else if (i.operands == 3) | |
1555 | { | |
1556 | xchg1 = 0; | |
1557 | xchg2 = 2; | |
1558 | } | |
520dc8e8 AM |
1559 | temp_type = i.types[xchg2]; |
1560 | i.types[xchg2] = i.types[xchg1]; | |
1561 | i.types[xchg1] = temp_type; | |
1562 | temp_op = i.op[xchg2]; | |
1563 | i.op[xchg2] = i.op[xchg1]; | |
1564 | i.op[xchg1] = temp_op; | |
1ae12ab7 AM |
1565 | temp_reloc = i.reloc[xchg2]; |
1566 | i.reloc[xchg2] = i.reloc[xchg1]; | |
1567 | i.reloc[xchg1] = temp_reloc; | |
36bf8ab9 AM |
1568 | |
1569 | if (i.mem_operands == 2) | |
1570 | { | |
1571 | const seg_entry *temp_seg; | |
1572 | temp_seg = i.seg[0]; | |
1573 | i.seg[0] = i.seg[1]; | |
1574 | i.seg[1] = temp_seg; | |
1575 | } | |
24eab124 | 1576 | } |
773f551c AM |
1577 | |
1578 | if (i.imm_operands) | |
1579 | { | |
1580 | /* Try to ensure constant immediates are represented in the smallest | |
1581 | opcode possible. */ | |
1582 | char guess_suffix = 0; | |
1583 | int op; | |
1584 | ||
1585 | if (i.suffix) | |
1586 | guess_suffix = i.suffix; | |
1587 | else if (i.reg_operands) | |
1588 | { | |
1589 | /* Figure out a suffix from the last register operand specified. | |
1590 | We can't do this properly yet, ie. excluding InOutPortReg, | |
1591 | but the following works for instructions with immediates. | |
1592 | In any case, we can't set i.suffix yet. */ | |
47926f60 | 1593 | for (op = i.operands; --op >= 0;) |
773f551c AM |
1594 | if (i.types[op] & Reg) |
1595 | { | |
1596 | if (i.types[op] & Reg8) | |
1597 | guess_suffix = BYTE_MNEM_SUFFIX; | |
1598 | else if (i.types[op] & Reg16) | |
1599 | guess_suffix = WORD_MNEM_SUFFIX; | |
3e73aa7c JH |
1600 | else if (i.types[op] & Reg32) |
1601 | guess_suffix = LONG_MNEM_SUFFIX; | |
1602 | else if (i.types[op] & Reg64) | |
1603 | guess_suffix = QWORD_MNEM_SUFFIX; | |
773f551c AM |
1604 | break; |
1605 | } | |
1606 | } | |
3e73aa7c | 1607 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
726c5dcd AM |
1608 | guess_suffix = WORD_MNEM_SUFFIX; |
1609 | ||
47926f60 | 1610 | for (op = i.operands; --op >= 0;) |
3e73aa7c | 1611 | if (i.types[op] & Imm) |
773f551c | 1612 | { |
3e73aa7c | 1613 | switch (i.op[op].imms->X_op) |
e5cb08ac | 1614 | { |
3e73aa7c JH |
1615 | case O_constant: |
1616 | /* If a suffix is given, this operand may be shortened. */ | |
1617 | switch (guess_suffix) | |
1618 | { | |
1619 | case LONG_MNEM_SUFFIX: | |
1620 | i.types[op] |= Imm32 | Imm64; | |
1621 | break; | |
1622 | case WORD_MNEM_SUFFIX: | |
1623 | i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64; | |
1624 | break; | |
1625 | case BYTE_MNEM_SUFFIX: | |
1626 | i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64; | |
1627 | break; | |
1628 | } | |
773f551c | 1629 | |
e5cb08ac KH |
1630 | /* If this operand is at most 16 bits, convert it |
1631 | to a signed 16 bit number before trying to see | |
1632 | whether it will fit in an even smaller size. | |
1633 | This allows a 16-bit operand such as $0xffe0 to | |
1634 | be recognised as within Imm8S range. */ | |
3e73aa7c | 1635 | if ((i.types[op] & Imm16) |
e5cb08ac | 1636 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
3e73aa7c JH |
1637 | { |
1638 | i.op[op].imms->X_add_number = | |
1639 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
1640 | } | |
1641 | if ((i.types[op] & Imm32) | |
1642 | && (i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) == 0) | |
1643 | { | |
1644 | i.op[op].imms->X_add_number = | |
1645 | (i.op[op].imms->X_add_number ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
1646 | } | |
1647 | i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number); | |
1648 | /* We must avoid matching of Imm32 templates when 64bit only immediate is available. */ | |
1649 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
1650 | i.types[op] &= ~Imm32; | |
1651 | break; | |
1652 | case O_absent: | |
1653 | case O_register: | |
bfb32b52 | 1654 | abort (); |
3e73aa7c JH |
1655 | /* Symbols and expressions. */ |
1656 | default: | |
1657 | /* Convert symbolic operand to proper sizes for matching. */ | |
1658 | switch (guess_suffix) | |
1659 | { | |
1660 | case QWORD_MNEM_SUFFIX: | |
1661 | i.types[op] = Imm64 | Imm32S; | |
1662 | break; | |
1663 | case LONG_MNEM_SUFFIX: | |
1664 | i.types[op] = Imm32 | Imm64; | |
1665 | break; | |
1666 | case WORD_MNEM_SUFFIX: | |
1667 | i.types[op] = Imm16 | Imm32 | Imm64; | |
1668 | break; | |
1669 | break; | |
1670 | case BYTE_MNEM_SUFFIX: | |
1671 | i.types[op] = Imm8 | Imm8S | Imm16 | Imm32S | Imm32; | |
1672 | break; | |
1673 | break; | |
1674 | } | |
1675 | break; | |
773f551c | 1676 | } |
773f551c AM |
1677 | } |
1678 | } | |
1679 | ||
45288df1 AM |
1680 | if (i.disp_operands) |
1681 | { | |
1682 | /* Try to use the smallest displacement type too. */ | |
1683 | int op; | |
1684 | ||
47926f60 | 1685 | for (op = i.operands; --op >= 0;) |
45288df1 | 1686 | if ((i.types[op] & Disp) |
1ae12ab7 | 1687 | && i.op[op].disps->X_op == O_constant) |
45288df1 AM |
1688 | { |
1689 | offsetT disp = i.op[op].disps->X_add_number; | |
1690 | ||
1691 | if (i.types[op] & Disp16) | |
1692 | { | |
1693 | /* We know this operand is at most 16 bits, so | |
1694 | convert to a signed 16 bit number before trying | |
1695 | to see whether it will fit in an even smaller | |
1696 | size. */ | |
47926f60 | 1697 | |
45288df1 AM |
1698 | disp = (((disp & 0xffff) ^ 0x8000) - 0x8000); |
1699 | } | |
3e73aa7c JH |
1700 | else if (i.types[op] & Disp32) |
1701 | { | |
1702 | /* We know this operand is at most 32 bits, so convert to a | |
1703 | signed 32 bit number before trying to see whether it will | |
1704 | fit in an even smaller size. */ | |
1705 | disp &= (((offsetT) 2 << 31) - 1); | |
1706 | disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
1707 | } | |
1708 | if (flag_code == CODE_64BIT) | |
1709 | { | |
1710 | if (fits_in_signed_long (disp)) | |
1711 | i.types[op] |= Disp32S; | |
1712 | if (fits_in_unsigned_long (disp)) | |
1713 | i.types[op] |= Disp32; | |
1714 | } | |
1715 | if ((i.types[op] & (Disp32 | Disp32S | Disp16)) | |
1716 | && fits_in_signed_byte (disp)) | |
45288df1 AM |
1717 | i.types[op] |= Disp8; |
1718 | } | |
1719 | } | |
1720 | ||
252b5132 RH |
1721 | overlap0 = 0; |
1722 | overlap1 = 0; | |
1723 | overlap2 = 0; | |
1724 | found_reverse_match = 0; | |
1725 | suffix_check = (i.suffix == BYTE_MNEM_SUFFIX | |
1726 | ? No_bSuf | |
1727 | : (i.suffix == WORD_MNEM_SUFFIX | |
1728 | ? No_wSuf | |
1729 | : (i.suffix == SHORT_MNEM_SUFFIX | |
1730 | ? No_sSuf | |
1731 | : (i.suffix == LONG_MNEM_SUFFIX | |
24eab124 | 1732 | ? No_lSuf |
3e73aa7c JH |
1733 | : (i.suffix == QWORD_MNEM_SUFFIX |
1734 | ? No_qSuf | |
1735 | : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX ? No_xSuf : 0)))))); | |
252b5132 RH |
1736 | |
1737 | for (t = current_templates->start; | |
1738 | t < current_templates->end; | |
1739 | t++) | |
1740 | { | |
47926f60 | 1741 | /* Must have right number of operands. */ |
252b5132 RH |
1742 | if (i.operands != t->operands) |
1743 | continue; | |
1744 | ||
7f3f1ea2 AM |
1745 | /* Check the suffix, except for some instructions in intel mode. */ |
1746 | if ((t->opcode_modifier & suffix_check) | |
fa2255cb DN |
1747 | && !(intel_syntax |
1748 | && (t->opcode_modifier & IgnoreSize)) | |
7f3f1ea2 AM |
1749 | && !(intel_syntax |
1750 | && t->base_opcode == 0xd9 | |
ce8a8b2f AM |
1751 | && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */ |
1752 | || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */ | |
24eab124 | 1753 | continue; |
252b5132 | 1754 | |
e2914f48 | 1755 | /* Do not verify operands when there are none. */ |
252b5132 | 1756 | else if (!t->operands) |
e2914f48 JH |
1757 | { |
1758 | if (t->cpu_flags & ~cpu_arch_flags) | |
1759 | continue; | |
1760 | /* We've found a match; break out of loop. */ | |
1761 | break; | |
e5cb08ac | 1762 | } |
252b5132 RH |
1763 | |
1764 | overlap0 = i.types[0] & t->operand_types[0]; | |
1765 | switch (t->operands) | |
1766 | { | |
1767 | case 1: | |
1768 | if (!MATCH (overlap0, i.types[0], t->operand_types[0])) | |
1769 | continue; | |
1770 | break; | |
1771 | case 2: | |
1772 | case 3: | |
1773 | overlap1 = i.types[1] & t->operand_types[1]; | |
1774 | if (!MATCH (overlap0, i.types[0], t->operand_types[0]) | |
1775 | || !MATCH (overlap1, i.types[1], t->operand_types[1]) | |
1776 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], | |
1777 | t->operand_types[0], | |
1778 | overlap1, i.types[1], | |
1779 | t->operand_types[1])) | |
1780 | { | |
47926f60 | 1781 | /* Check if other direction is valid ... */ |
252b5132 RH |
1782 | if ((t->opcode_modifier & (D|FloatD)) == 0) |
1783 | continue; | |
1784 | ||
47926f60 | 1785 | /* Try reversing direction of operands. */ |
252b5132 RH |
1786 | overlap0 = i.types[0] & t->operand_types[1]; |
1787 | overlap1 = i.types[1] & t->operand_types[0]; | |
1788 | if (!MATCH (overlap0, i.types[0], t->operand_types[1]) | |
1789 | || !MATCH (overlap1, i.types[1], t->operand_types[0]) | |
1790 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], | |
1791 | t->operand_types[1], | |
1792 | overlap1, i.types[1], | |
1793 | t->operand_types[0])) | |
1794 | { | |
47926f60 | 1795 | /* Does not match either direction. */ |
252b5132 RH |
1796 | continue; |
1797 | } | |
1798 | /* found_reverse_match holds which of D or FloatDR | |
1799 | we've found. */ | |
1800 | found_reverse_match = t->opcode_modifier & (D|FloatDR); | |
252b5132 | 1801 | } |
47926f60 | 1802 | /* Found a forward 2 operand match here. */ |
3e73aa7c | 1803 | else if (t->operands == 3) |
252b5132 RH |
1804 | { |
1805 | /* Here we make use of the fact that there are no | |
1806 | reverse match 3 operand instructions, and all 3 | |
1807 | operand instructions only need to be checked for | |
1808 | register consistency between operands 2 and 3. */ | |
1809 | overlap2 = i.types[2] & t->operand_types[2]; | |
1810 | if (!MATCH (overlap2, i.types[2], t->operand_types[2]) | |
1811 | || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1], | |
1812 | t->operand_types[1], | |
1813 | overlap2, i.types[2], | |
24eab124 | 1814 | t->operand_types[2])) |
252b5132 | 1815 | |
24eab124 | 1816 | continue; |
252b5132 | 1817 | } |
47926f60 | 1818 | /* Found either forward/reverse 2 or 3 operand match here: |
ce8a8b2f | 1819 | slip through to break. */ |
252b5132 | 1820 | } |
3e73aa7c JH |
1821 | if (t->cpu_flags & ~cpu_arch_flags) |
1822 | { | |
1823 | found_reverse_match = 0; | |
1824 | continue; | |
1825 | } | |
47926f60 KH |
1826 | /* We've found a match; break out of loop. */ |
1827 | break; | |
ce8a8b2f | 1828 | } |
252b5132 | 1829 | if (t == current_templates->end) |
47926f60 KH |
1830 | { |
1831 | /* We found no match. */ | |
252b5132 RH |
1832 | as_bad (_("suffix or operands invalid for `%s'"), |
1833 | current_templates->start->name); | |
1834 | return; | |
1835 | } | |
1836 | ||
a38cf1db | 1837 | if (!quiet_warnings) |
3138f287 | 1838 | { |
a38cf1db AM |
1839 | if (!intel_syntax |
1840 | && ((i.types[0] & JumpAbsolute) | |
1841 | != (t->operand_types[0] & JumpAbsolute))) | |
1842 | { | |
1843 | as_warn (_("indirect %s without `*'"), t->name); | |
1844 | } | |
3138f287 | 1845 | |
a38cf1db AM |
1846 | if ((t->opcode_modifier & (IsPrefix|IgnoreSize)) |
1847 | == (IsPrefix|IgnoreSize)) | |
1848 | { | |
1849 | /* Warn them that a data or address size prefix doesn't | |
1850 | affect assembly of the next line of code. */ | |
1851 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
1852 | } | |
252b5132 RH |
1853 | } |
1854 | ||
1855 | /* Copy the template we found. */ | |
1856 | i.tm = *t; | |
1857 | if (found_reverse_match) | |
1858 | { | |
7f3f1ea2 AM |
1859 | /* If we found a reverse match we must alter the opcode |
1860 | direction bit. found_reverse_match holds bits to change | |
1861 | (different for int & float insns). */ | |
1862 | ||
1863 | i.tm.base_opcode ^= found_reverse_match; | |
1864 | ||
252b5132 RH |
1865 | i.tm.operand_types[0] = t->operand_types[1]; |
1866 | i.tm.operand_types[1] = t->operand_types[0]; | |
1867 | } | |
1868 | ||
d0b47220 | 1869 | /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */ |
e5cb08ac KH |
1870 | if (SYSV386_COMPAT |
1871 | && intel_syntax | |
1872 | && (i.tm.base_opcode & 0xfffffde0) == 0xdce0) | |
1873 | i.tm.base_opcode ^= FloatR; | |
252b5132 RH |
1874 | |
1875 | if (i.tm.opcode_modifier & FWait) | |
1876 | if (! add_prefix (FWAIT_OPCODE)) | |
1877 | return; | |
1878 | ||
ce8a8b2f | 1879 | /* Check string instruction segment overrides. */ |
252b5132 RH |
1880 | if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0) |
1881 | { | |
1882 | int mem_op = (i.types[0] & AnyMem) ? 0 : 1; | |
1883 | if ((i.tm.operand_types[mem_op] & EsSeg) != 0) | |
1884 | { | |
1885 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
1886 | { | |
1887 | as_bad (_("`%s' operand %d must use `%%es' segment"), | |
1888 | i.tm.name, | |
1889 | mem_op + 1); | |
1890 | return; | |
1891 | } | |
1892 | /* There's only ever one segment override allowed per instruction. | |
1893 | This instruction possibly has a legal segment override on the | |
1894 | second operand, so copy the segment to where non-string | |
1895 | instructions store it, allowing common code. */ | |
1896 | i.seg[0] = i.seg[1]; | |
1897 | } | |
1898 | else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0) | |
1899 | { | |
1900 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
1901 | { | |
1902 | as_bad (_("`%s' operand %d must use `%%es' segment"), | |
1903 | i.tm.name, | |
1904 | mem_op + 2); | |
1905 | return; | |
1906 | } | |
1907 | } | |
1908 | } | |
1909 | ||
3e73aa7c JH |
1910 | if (i.reg_operands && flag_code < CODE_64BIT) |
1911 | { | |
1912 | int op; | |
e5cb08ac | 1913 | for (op = i.operands; --op >= 0;) |
3e73aa7c JH |
1914 | if ((i.types[op] & Reg) |
1915 | && (i.op[op].regs->reg_flags & (RegRex64|RegRex))) | |
b96d3a20 JH |
1916 | { |
1917 | as_bad (_("Extended register `%%%s' available only in 64bit mode."), | |
1918 | i.op[op].regs->reg_name); | |
1919 | return; | |
1920 | } | |
3e73aa7c JH |
1921 | } |
1922 | ||
252b5132 RH |
1923 | /* If matched instruction specifies an explicit instruction mnemonic |
1924 | suffix, use it. */ | |
3e73aa7c | 1925 | if (i.tm.opcode_modifier & (Size16 | Size32 | Size64)) |
252b5132 RH |
1926 | { |
1927 | if (i.tm.opcode_modifier & Size16) | |
1928 | i.suffix = WORD_MNEM_SUFFIX; | |
3e73aa7c JH |
1929 | else if (i.tm.opcode_modifier & Size64) |
1930 | i.suffix = QWORD_MNEM_SUFFIX; | |
252b5132 | 1931 | else |
add0c677 | 1932 | i.suffix = LONG_MNEM_SUFFIX; |
252b5132 RH |
1933 | } |
1934 | else if (i.reg_operands) | |
1935 | { | |
1936 | /* If there's no instruction mnemonic suffix we try to invent one | |
47926f60 | 1937 | based on register operands. */ |
252b5132 RH |
1938 | if (!i.suffix) |
1939 | { | |
1940 | /* We take i.suffix from the last register operand specified, | |
1941 | Destination register type is more significant than source | |
1942 | register type. */ | |
1943 | int op; | |
47926f60 | 1944 | for (op = i.operands; --op >= 0;) |
cc5ca5ce AM |
1945 | if ((i.types[op] & Reg) |
1946 | && !(i.tm.operand_types[op] & InOutPortReg)) | |
252b5132 RH |
1947 | { |
1948 | i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX : | |
1949 | (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX : | |
3e73aa7c | 1950 | (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX : |
add0c677 | 1951 | LONG_MNEM_SUFFIX); |
252b5132 RH |
1952 | break; |
1953 | } | |
1954 | } | |
1955 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
1956 | { | |
1957 | int op; | |
47926f60 | 1958 | for (op = i.operands; --op >= 0;) |
252b5132 RH |
1959 | { |
1960 | /* If this is an eight bit register, it's OK. If it's | |
1961 | the 16 or 32 bit version of an eight bit register, | |
47926f60 | 1962 | we will just use the low portion, and that's OK too. */ |
252b5132 RH |
1963 | if (i.types[op] & Reg8) |
1964 | continue; | |
1965 | ||
47926f60 | 1966 | /* movzx and movsx should not generate this warning. */ |
24eab124 AM |
1967 | if (intel_syntax |
1968 | && (i.tm.base_opcode == 0xfb7 | |
1969 | || i.tm.base_opcode == 0xfb6 | |
3e73aa7c | 1970 | || i.tm.base_opcode == 0x63 |
24eab124 AM |
1971 | || i.tm.base_opcode == 0xfbe |
1972 | || i.tm.base_opcode == 0xfbf)) | |
1973 | continue; | |
252b5132 | 1974 | |
520dc8e8 | 1975 | if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4 |
252b5132 RH |
1976 | #if 0 |
1977 | /* Check that the template allows eight bit regs | |
1978 | This kills insns such as `orb $1,%edx', which | |
1979 | maybe should be allowed. */ | |
1980 | && (i.tm.operand_types[op] & (Reg8|InOutPortReg)) | |
1981 | #endif | |
1982 | ) | |
1983 | { | |
3e73aa7c JH |
1984 | /* Prohibit these changes in the 64bit mode, since |
1985 | the lowering is more complicated. */ | |
1986 | if (flag_code == CODE_64BIT | |
1987 | && (i.tm.operand_types[op] & InOutPortReg) == 0) | |
1988 | as_bad (_("Incorrect register `%%%s' used with`%c' suffix"), | |
1989 | i.op[op].regs->reg_name, | |
1990 | i.suffix); | |
252b5132 | 1991 | #if REGISTER_WARNINGS |
a38cf1db AM |
1992 | if (!quiet_warnings |
1993 | && (i.tm.operand_types[op] & InOutPortReg) == 0) | |
252b5132 | 1994 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), |
2e98d2de AM |
1995 | (i.op[op].regs |
1996 | + (i.types[op] & Reg16 | |
1997 | ? REGNAM_AL - REGNAM_AX | |
1998 | : REGNAM_AL - REGNAM_EAX))->reg_name, | |
520dc8e8 | 1999 | i.op[op].regs->reg_name, |
252b5132 RH |
2000 | i.suffix); |
2001 | #endif | |
2002 | continue; | |
2003 | } | |
ce8a8b2f | 2004 | /* Any other register is bad. */ |
3f4438ab AM |
2005 | if (i.types[op] & (Reg | RegMMX | RegXMM |
2006 | | SReg2 | SReg3 | |
2007 | | Control | Debug | Test | |
2008 | | FloatReg | FloatAcc)) | |
252b5132 RH |
2009 | { |
2010 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
520dc8e8 | 2011 | i.op[op].regs->reg_name, |
252b5132 RH |
2012 | i.tm.name, |
2013 | i.suffix); | |
2014 | return; | |
2015 | } | |
2016 | } | |
2017 | } | |
add0c677 | 2018 | else if (i.suffix == LONG_MNEM_SUFFIX) |
252b5132 RH |
2019 | { |
2020 | int op; | |
47926f60 KH |
2021 | |
2022 | for (op = i.operands; --op >= 0;) | |
252b5132 RH |
2023 | /* Reject eight bit registers, except where the template |
2024 | requires them. (eg. movzb) */ | |
2025 | if ((i.types[op] & Reg8) != 0 | |
47926f60 | 2026 | && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) |
252b5132 RH |
2027 | { |
2028 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
520dc8e8 | 2029 | i.op[op].regs->reg_name, |
252b5132 RH |
2030 | i.tm.name, |
2031 | i.suffix); | |
2032 | return; | |
2033 | } | |
252b5132 | 2034 | /* Warn if the e prefix on a general reg is missing. */ |
3e73aa7c | 2035 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
a38cf1db | 2036 | && (i.types[op] & Reg16) != 0 |
252b5132 RH |
2037 | && (i.tm.operand_types[op] & (Reg32|Acc)) != 0) |
2038 | { | |
3e73aa7c JH |
2039 | /* Prohibit these changes in the 64bit mode, since |
2040 | the lowering is more complicated. */ | |
2041 | if (flag_code == CODE_64BIT) | |
2042 | as_bad (_("Incorrect register `%%%s' used with`%c' suffix"), | |
2043 | i.op[op].regs->reg_name, | |
2044 | i.suffix); | |
2045 | #if REGISTER_WARNINGS | |
2046 | else | |
2047 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
2e98d2de | 2048 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, |
3e73aa7c JH |
2049 | i.op[op].regs->reg_name, |
2050 | i.suffix); | |
252b5132 | 2051 | #endif |
3e73aa7c JH |
2052 | } |
2053 | /* Warn if the r prefix on a general reg is missing. */ | |
2054 | else if ((i.types[op] & Reg64) != 0 | |
2055 | && (i.tm.operand_types[op] & (Reg32|Acc)) != 0) | |
2056 | { | |
2057 | as_bad (_("Incorrect register `%%%s' used with`%c' suffix"), | |
2058 | i.op[op].regs->reg_name, | |
2059 | i.suffix); | |
2060 | } | |
2061 | } | |
2062 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
2063 | { | |
2064 | int op; | |
3e73aa7c JH |
2065 | |
2066 | for (op = i.operands; --op >= 0; ) | |
2067 | /* Reject eight bit registers, except where the template | |
2068 | requires them. (eg. movzb) */ | |
2069 | if ((i.types[op] & Reg8) != 0 | |
2070 | && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0) | |
2071 | { | |
2072 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
2073 | i.op[op].regs->reg_name, | |
2074 | i.tm.name, | |
2075 | i.suffix); | |
2076 | return; | |
2077 | } | |
2078 | /* Warn if the e prefix on a general reg is missing. */ | |
2079 | else if (((i.types[op] & Reg16) != 0 | |
2080 | || (i.types[op] & Reg32) != 0) | |
2081 | && (i.tm.operand_types[op] & (Reg32|Acc)) != 0) | |
2082 | { | |
2083 | /* Prohibit these changes in the 64bit mode, since | |
2084 | the lowering is more complicated. */ | |
2085 | as_bad (_("Incorrect register `%%%s' used with`%c' suffix"), | |
2086 | i.op[op].regs->reg_name, | |
2087 | i.suffix); | |
2088 | } | |
252b5132 RH |
2089 | } |
2090 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
2091 | { | |
2092 | int op; | |
47926f60 | 2093 | for (op = i.operands; --op >= 0;) |
252b5132 RH |
2094 | /* Reject eight bit registers, except where the template |
2095 | requires them. (eg. movzb) */ | |
2096 | if ((i.types[op] & Reg8) != 0 | |
2097 | && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0) | |
2098 | { | |
2099 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
520dc8e8 | 2100 | i.op[op].regs->reg_name, |
252b5132 RH |
2101 | i.tm.name, |
2102 | i.suffix); | |
2103 | return; | |
2104 | } | |
252b5132 | 2105 | /* Warn if the e prefix on a general reg is present. */ |
3e73aa7c | 2106 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
a38cf1db | 2107 | && (i.types[op] & Reg32) != 0 |
252b5132 RH |
2108 | && (i.tm.operand_types[op] & (Reg16|Acc)) != 0) |
2109 | { | |
3e73aa7c JH |
2110 | /* Prohibit these changes in the 64bit mode, since |
2111 | the lowering is more complicated. */ | |
2112 | if (flag_code == CODE_64BIT) | |
2113 | as_bad (_("Incorrect register `%%%s' used with`%c' suffix"), | |
2114 | i.op[op].regs->reg_name, | |
2115 | i.suffix); | |
2116 | else | |
2117 | #if REGISTER_WARNINGS | |
2118 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
2e98d2de | 2119 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, |
3e73aa7c JH |
2120 | i.op[op].regs->reg_name, |
2121 | i.suffix); | |
252b5132 | 2122 | #endif |
3e73aa7c | 2123 | } |
252b5132 | 2124 | } |
fa2255cb DN |
2125 | else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize)) |
2126 | /* Do nothing if the instruction is going to ignore the prefix. */ | |
2127 | ; | |
252b5132 | 2128 | else |
47926f60 | 2129 | abort (); |
252b5132 | 2130 | } |
eecb386c AM |
2131 | else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix) |
2132 | { | |
2133 | i.suffix = stackop_size; | |
2134 | } | |
252b5132 RH |
2135 | /* Make still unresolved immediate matches conform to size of immediate |
2136 | given in i.suffix. Note: overlap2 cannot be an immediate! */ | |
3e73aa7c | 2137 | if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S)) |
252b5132 | 2138 | && overlap0 != Imm8 && overlap0 != Imm8S |
e5cb08ac | 2139 | && overlap0 != Imm16 && overlap0 != Imm32S |
b77a7acd | 2140 | && overlap0 != Imm32 && overlap0 != Imm64) |
252b5132 RH |
2141 | { |
2142 | if (i.suffix) | |
2143 | { | |
24eab124 | 2144 | overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) : |
b77a7acd | 2145 | (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : |
3e73aa7c | 2146 | (i.suffix == QWORD_MNEM_SUFFIX ? Imm64 | Imm32S : Imm32))); |
252b5132 | 2147 | } |
3e73aa7c JH |
2148 | else if (overlap0 == (Imm16 | Imm32S | Imm32) |
2149 | || overlap0 == (Imm16 | Imm32) | |
2150 | || overlap0 == (Imm16 | Imm32S)) | |
252b5132 | 2151 | { |
24eab124 | 2152 | overlap0 = |
3e73aa7c | 2153 | ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32S; |
252b5132 | 2154 | } |
3e73aa7c JH |
2155 | if (overlap0 != Imm8 && overlap0 != Imm8S |
2156 | && overlap0 != Imm16 && overlap0 != Imm32S | |
2157 | && overlap0 != Imm32 && overlap0 != Imm64) | |
252b5132 RH |
2158 | { |
2159 | as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")); | |
2160 | return; | |
2161 | } | |
2162 | } | |
3e73aa7c | 2163 | if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32)) |
252b5132 | 2164 | && overlap1 != Imm8 && overlap1 != Imm8S |
e5cb08ac | 2165 | && overlap1 != Imm16 && overlap1 != Imm32S |
b77a7acd | 2166 | && overlap1 != Imm32 && overlap1 != Imm64) |
252b5132 RH |
2167 | { |
2168 | if (i.suffix) | |
2169 | { | |
24eab124 | 2170 | overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) : |
b77a7acd AJ |
2171 | (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : |
2172 | (i.suffix == QWORD_MNEM_SUFFIX ? Imm64 | Imm32S : Imm32))); | |
252b5132 | 2173 | } |
3e73aa7c JH |
2174 | else if (overlap1 == (Imm16 | Imm32 | Imm32S) |
2175 | || overlap1 == (Imm16 | Imm32) | |
2176 | || overlap1 == (Imm16 | Imm32S)) | |
252b5132 | 2177 | { |
24eab124 | 2178 | overlap1 = |
3e73aa7c | 2179 | ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32S; |
252b5132 | 2180 | } |
3e73aa7c JH |
2181 | if (overlap1 != Imm8 && overlap1 != Imm8S |
2182 | && overlap1 != Imm16 && overlap1 != Imm32S | |
2183 | && overlap1 != Imm32 && overlap1 != Imm64) | |
252b5132 | 2184 | { |
3e73aa7c | 2185 | as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix); |
252b5132 RH |
2186 | return; |
2187 | } | |
2188 | } | |
2189 | assert ((overlap2 & Imm) == 0); | |
2190 | ||
2191 | i.types[0] = overlap0; | |
2192 | if (overlap0 & ImplicitRegister) | |
2193 | i.reg_operands--; | |
2194 | if (overlap0 & Imm1) | |
ce8a8b2f | 2195 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 RH |
2196 | |
2197 | i.types[1] = overlap1; | |
2198 | if (overlap1 & ImplicitRegister) | |
2199 | i.reg_operands--; | |
2200 | ||
2201 | i.types[2] = overlap2; | |
2202 | if (overlap2 & ImplicitRegister) | |
2203 | i.reg_operands--; | |
2204 | ||
2205 | /* Finalize opcode. First, we change the opcode based on the operand | |
2206 | size given by i.suffix: We need not change things for byte insns. */ | |
2207 | ||
2208 | if (!i.suffix && (i.tm.opcode_modifier & W)) | |
2209 | { | |
2210 | as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction")); | |
2211 | return; | |
2212 | } | |
2213 | ||
ce8a8b2f | 2214 | /* For movzx and movsx, need to check the register type. */ |
252b5132 | 2215 | if (intel_syntax |
24eab124 | 2216 | && (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe)) |
252b5132 | 2217 | if (i.suffix && i.suffix == BYTE_MNEM_SUFFIX) |
24eab124 AM |
2218 | { |
2219 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
252b5132 | 2220 | |
520dc8e8 | 2221 | if ((i.op[1].regs->reg_type & Reg16) != 0) |
24eab124 AM |
2222 | if (!add_prefix (prefix)) |
2223 | return; | |
2224 | } | |
252b5132 RH |
2225 | |
2226 | if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX) | |
2227 | { | |
2228 | /* It's not a byte, select word/dword operation. */ | |
2229 | if (i.tm.opcode_modifier & W) | |
2230 | { | |
2231 | if (i.tm.opcode_modifier & ShortForm) | |
2232 | i.tm.base_opcode |= 8; | |
2233 | else | |
2234 | i.tm.base_opcode |= 1; | |
2235 | } | |
2236 | /* Now select between word & dword operations via the operand | |
2237 | size prefix, except for instructions that will ignore this | |
2238 | prefix anyway. */ | |
3e73aa7c JH |
2239 | if (i.suffix != QWORD_MNEM_SUFFIX |
2240 | && (i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) | |
252b5132 RH |
2241 | && !(i.tm.opcode_modifier & IgnoreSize)) |
2242 | { | |
2243 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
2244 | if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */ | |
2245 | prefix = ADDR_PREFIX_OPCODE; | |
2246 | ||
2247 | if (! add_prefix (prefix)) | |
2248 | return; | |
2249 | } | |
3e73aa7c JH |
2250 | |
2251 | /* Set mode64 for an operand. */ | |
2252 | if (i.suffix == QWORD_MNEM_SUFFIX | |
2253 | && !(i.tm.opcode_modifier & NoRex64)) | |
b96d3a20 | 2254 | { |
3e73aa7c | 2255 | i.rex.mode64 = 1; |
b96d3a20 JH |
2256 | if (flag_code < CODE_64BIT) |
2257 | { | |
e5cb08ac KH |
2258 | as_bad (_("64bit operations available only in 64bit modes.")); |
2259 | return; | |
b96d3a20 JH |
2260 | } |
2261 | } | |
3e73aa7c | 2262 | |
252b5132 | 2263 | /* Size floating point instruction. */ |
f16b83df | 2264 | if (i.suffix == LONG_MNEM_SUFFIX) |
252b5132 RH |
2265 | { |
2266 | if (i.tm.opcode_modifier & FloatMF) | |
2267 | i.tm.base_opcode ^= 4; | |
2268 | } | |
252b5132 RH |
2269 | } |
2270 | ||
3f4438ab | 2271 | if (i.tm.opcode_modifier & ImmExt) |
252b5132 | 2272 | { |
3f4438ab AM |
2273 | /* These AMD 3DNow! and Intel Katmai New Instructions have an |
2274 | opcode suffix which is coded in the same place as an 8-bit | |
2275 | immediate field would be. Here we fake an 8-bit immediate | |
2276 | operand from the opcode suffix stored in tm.extension_opcode. */ | |
252b5132 RH |
2277 | |
2278 | expressionS *exp; | |
2279 | ||
47926f60 | 2280 | assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS); |
252b5132 RH |
2281 | |
2282 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 2283 | i.op[i.operands].imms = exp; |
252b5132 RH |
2284 | i.types[i.operands++] = Imm8; |
2285 | exp->X_op = O_constant; | |
2286 | exp->X_add_number = i.tm.extension_opcode; | |
2287 | i.tm.extension_opcode = None; | |
2288 | } | |
2289 | ||
47926f60 | 2290 | /* For insns with operands there are more diddles to do to the opcode. */ |
252b5132 RH |
2291 | if (i.operands) |
2292 | { | |
24eab124 | 2293 | /* Default segment register this instruction will use |
252b5132 RH |
2294 | for memory accesses. 0 means unknown. |
2295 | This is only for optimizing out unnecessary segment overrides. */ | |
2296 | const seg_entry *default_seg = 0; | |
2297 | ||
252b5132 RH |
2298 | /* The imul $imm, %reg instruction is converted into |
2299 | imul $imm, %reg, %reg, and the clr %reg instruction | |
2300 | is converted into xor %reg, %reg. */ | |
2301 | if (i.tm.opcode_modifier & regKludge) | |
2302 | { | |
2303 | unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1; | |
47926f60 KH |
2304 | /* Pretend we saw the extra register operand. */ |
2305 | assert (i.op[first_reg_op + 1].regs == 0); | |
2306 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; | |
2307 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
252b5132 RH |
2308 | i.reg_operands = 2; |
2309 | } | |
2310 | ||
2311 | if (i.tm.opcode_modifier & ShortForm) | |
2312 | { | |
47926f60 | 2313 | /* The register or float register operand is in operand 0 or 1. */ |
252b5132 | 2314 | unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1; |
47926f60 | 2315 | /* Register goes in low 3 bits of opcode. */ |
520dc8e8 | 2316 | i.tm.base_opcode |= i.op[op].regs->reg_num; |
3e73aa7c | 2317 | if (i.op[op].regs->reg_flags & RegRex) |
e5cb08ac | 2318 | i.rex.extZ = 1; |
a38cf1db | 2319 | if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) |
252b5132 RH |
2320 | { |
2321 | /* Warn about some common errors, but press on regardless. | |
2322 | The first case can be generated by gcc (<= 2.8.1). */ | |
2323 | if (i.operands == 2) | |
2324 | { | |
47926f60 | 2325 | /* Reversed arguments on faddp, fsubp, etc. */ |
252b5132 | 2326 | as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name, |
520dc8e8 AM |
2327 | i.op[1].regs->reg_name, |
2328 | i.op[0].regs->reg_name); | |
252b5132 RH |
2329 | } |
2330 | else | |
2331 | { | |
47926f60 | 2332 | /* Extraneous `l' suffix on fp insn. */ |
252b5132 | 2333 | as_warn (_("translating to `%s %%%s'"), i.tm.name, |
520dc8e8 | 2334 | i.op[0].regs->reg_name); |
252b5132 RH |
2335 | } |
2336 | } | |
2337 | } | |
2338 | else if (i.tm.opcode_modifier & Modrm) | |
2339 | { | |
2340 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
2341 | must be put into the modrm byte). | |
2342 | Now, we make the modrm & index base bytes based on all the | |
47926f60 | 2343 | info we've collected. */ |
252b5132 RH |
2344 | |
2345 | /* i.reg_operands MUST be the number of real register operands; | |
47926f60 | 2346 | implicit registers do not count. */ |
252b5132 RH |
2347 | if (i.reg_operands == 2) |
2348 | { | |
2349 | unsigned int source, dest; | |
2350 | source = ((i.types[0] | |
3f4438ab AM |
2351 | & (Reg | RegMMX | RegXMM |
2352 | | SReg2 | SReg3 | |
2353 | | Control | Debug | Test)) | |
252b5132 RH |
2354 | ? 0 : 1); |
2355 | dest = source + 1; | |
2356 | ||
252b5132 | 2357 | i.rm.mode = 3; |
3f4438ab AM |
2358 | /* One of the register operands will be encoded in the |
2359 | i.tm.reg field, the other in the combined i.tm.mode | |
2360 | and i.tm.regmem fields. If no form of this | |
2361 | instruction supports a memory destination operand, | |
2362 | then we assume the source operand may sometimes be | |
2363 | a memory operand and so we need to store the | |
2364 | destination in the i.rm.reg field. */ | |
2365 | if ((i.tm.operand_types[dest] & AnyMem) == 0) | |
252b5132 | 2366 | { |
520dc8e8 AM |
2367 | i.rm.reg = i.op[dest].regs->reg_num; |
2368 | i.rm.regmem = i.op[source].regs->reg_num; | |
3e73aa7c | 2369 | if (i.op[dest].regs->reg_flags & RegRex) |
e5cb08ac | 2370 | i.rex.extX = 1; |
3e73aa7c | 2371 | if (i.op[source].regs->reg_flags & RegRex) |
e5cb08ac | 2372 | i.rex.extZ = 1; |
252b5132 RH |
2373 | } |
2374 | else | |
2375 | { | |
520dc8e8 AM |
2376 | i.rm.reg = i.op[source].regs->reg_num; |
2377 | i.rm.regmem = i.op[dest].regs->reg_num; | |
3e73aa7c | 2378 | if (i.op[dest].regs->reg_flags & RegRex) |
e5cb08ac | 2379 | i.rex.extZ = 1; |
3e73aa7c | 2380 | if (i.op[source].regs->reg_flags & RegRex) |
e5cb08ac | 2381 | i.rex.extX = 1; |
252b5132 RH |
2382 | } |
2383 | } | |
2384 | else | |
47926f60 | 2385 | { /* If it's not 2 reg operands... */ |
252b5132 RH |
2386 | if (i.mem_operands) |
2387 | { | |
2388 | unsigned int fake_zero_displacement = 0; | |
2389 | unsigned int op = ((i.types[0] & AnyMem) | |
2390 | ? 0 | |
2391 | : (i.types[1] & AnyMem) ? 1 : 2); | |
2392 | ||
2393 | default_seg = &ds; | |
2394 | ||
2395 | if (! i.base_reg) | |
2396 | { | |
2397 | i.rm.mode = 0; | |
2398 | if (! i.disp_operands) | |
2399 | fake_zero_displacement = 1; | |
2400 | if (! i.index_reg) | |
2401 | { | |
47926f60 | 2402 | /* Operand is just <disp> */ |
3e73aa7c | 2403 | if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) |
252b5132 RH |
2404 | { |
2405 | i.rm.regmem = NO_BASE_REGISTER_16; | |
2406 | i.types[op] &= ~Disp; | |
2407 | i.types[op] |= Disp16; | |
2408 | } | |
3e73aa7c | 2409 | else if (flag_code != CODE_64BIT) |
252b5132 RH |
2410 | { |
2411 | i.rm.regmem = NO_BASE_REGISTER; | |
2412 | i.types[op] &= ~Disp; | |
2413 | i.types[op] |= Disp32; | |
2414 | } | |
3e73aa7c JH |
2415 | else |
2416 | { | |
e5cb08ac KH |
2417 | /* 64bit mode overwrites the 32bit |
2418 | absolute addressing by RIP relative | |
2419 | addressing and absolute addressing | |
2420 | is encoded by one of the redundant | |
2421 | SIB forms. */ | |
3e73aa7c JH |
2422 | |
2423 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2424 | i.sib.base = NO_BASE_REGISTER; | |
2425 | i.sib.index = NO_INDEX_REGISTER; | |
2426 | i.types[op] &= ~Disp; | |
2427 | i.types[op] |= Disp32S; | |
2428 | } | |
252b5132 | 2429 | } |
47926f60 | 2430 | else /* ! i.base_reg && i.index_reg */ |
252b5132 RH |
2431 | { |
2432 | i.sib.index = i.index_reg->reg_num; | |
2433 | i.sib.base = NO_BASE_REGISTER; | |
2434 | i.sib.scale = i.log2_scale_factor; | |
2435 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2436 | i.types[op] &= ~Disp; | |
3e73aa7c JH |
2437 | if (flag_code != CODE_64BIT) |
2438 | i.types[op] |= Disp32; /* Must be 32 bit */ | |
2439 | else | |
2440 | i.types[op] |= Disp32S; | |
2441 | if (i.index_reg->reg_flags & RegRex) | |
e5cb08ac | 2442 | i.rex.extY = 1; |
252b5132 RH |
2443 | } |
2444 | } | |
3e73aa7c JH |
2445 | /* RIP addressing for 64bit mode. */ |
2446 | else if (i.base_reg->reg_type == BaseIndex) | |
2447 | { | |
2448 | i.rm.regmem = NO_BASE_REGISTER; | |
2449 | i.types[op] &= ~Disp; | |
2450 | i.types[op] |= Disp32S; | |
2451 | i.flags[op] = Operand_PCrel; | |
2452 | } | |
252b5132 RH |
2453 | else if (i.base_reg->reg_type & Reg16) |
2454 | { | |
2455 | switch (i.base_reg->reg_num) | |
2456 | { | |
47926f60 | 2457 | case 3: /* (%bx) */ |
252b5132 RH |
2458 | if (! i.index_reg) |
2459 | i.rm.regmem = 7; | |
47926f60 | 2460 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ |
252b5132 RH |
2461 | i.rm.regmem = i.index_reg->reg_num - 6; |
2462 | break; | |
47926f60 | 2463 | case 5: /* (%bp) */ |
252b5132 RH |
2464 | default_seg = &ss; |
2465 | if (! i.index_reg) | |
2466 | { | |
2467 | i.rm.regmem = 6; | |
2468 | if ((i.types[op] & Disp) == 0) | |
2469 | { | |
47926f60 | 2470 | /* fake (%bp) into 0(%bp) */ |
252b5132 RH |
2471 | i.types[op] |= Disp8; |
2472 | fake_zero_displacement = 1; | |
2473 | } | |
2474 | } | |
47926f60 | 2475 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ |
252b5132 RH |
2476 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; |
2477 | break; | |
47926f60 | 2478 | default: /* (%si) -> 4 or (%di) -> 5 */ |
252b5132 RH |
2479 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; |
2480 | } | |
2481 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
2482 | } | |
3e73aa7c | 2483 | else /* i.base_reg and 32/64 bit mode */ |
252b5132 | 2484 | { |
3e73aa7c JH |
2485 | if (flag_code == CODE_64BIT |
2486 | && (i.types[op] & Disp)) | |
2487 | { | |
2488 | if (i.types[op] & Disp8) | |
2489 | i.types[op] = Disp8 | Disp32S; | |
2490 | else | |
2491 | i.types[op] = Disp32S; | |
2492 | } | |
252b5132 | 2493 | i.rm.regmem = i.base_reg->reg_num; |
3e73aa7c | 2494 | if (i.base_reg->reg_flags & RegRex) |
e5cb08ac | 2495 | i.rex.extZ = 1; |
252b5132 | 2496 | i.sib.base = i.base_reg->reg_num; |
3e73aa7c JH |
2497 | /* x86-64 ignores REX prefix bit here to avoid |
2498 | decoder complications. */ | |
2499 | if ((i.base_reg->reg_num & 7) == EBP_REG_NUM) | |
252b5132 RH |
2500 | { |
2501 | default_seg = &ss; | |
2502 | if (i.disp_operands == 0) | |
2503 | { | |
2504 | fake_zero_displacement = 1; | |
2505 | i.types[op] |= Disp8; | |
2506 | } | |
2507 | } | |
2508 | else if (i.base_reg->reg_num == ESP_REG_NUM) | |
2509 | { | |
2510 | default_seg = &ss; | |
2511 | } | |
2512 | i.sib.scale = i.log2_scale_factor; | |
2513 | if (! i.index_reg) | |
2514 | { | |
2515 | /* <disp>(%esp) becomes two byte modrm | |
2516 | with no index register. We've already | |
2517 | stored the code for esp in i.rm.regmem | |
2518 | ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any | |
2519 | base register besides %esp will not use | |
2520 | the extra modrm byte. */ | |
2521 | i.sib.index = NO_INDEX_REGISTER; | |
2522 | #if ! SCALE1_WHEN_NO_INDEX | |
2523 | /* Another case where we force the second | |
2524 | modrm byte. */ | |
2525 | if (i.log2_scale_factor) | |
2526 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2527 | #endif | |
2528 | } | |
2529 | else | |
2530 | { | |
2531 | i.sib.index = i.index_reg->reg_num; | |
2532 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
3e73aa7c | 2533 | if (i.index_reg->reg_flags & RegRex) |
e5cb08ac | 2534 | i.rex.extY = 1; |
252b5132 RH |
2535 | } |
2536 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
2537 | } | |
2538 | ||
2539 | if (fake_zero_displacement) | |
2540 | { | |
2541 | /* Fakes a zero displacement assuming that i.types[op] | |
47926f60 | 2542 | holds the correct displacement size. */ |
b4cac588 AM |
2543 | expressionS *exp; |
2544 | ||
520dc8e8 | 2545 | assert (i.op[op].disps == 0); |
252b5132 | 2546 | exp = &disp_expressions[i.disp_operands++]; |
520dc8e8 | 2547 | i.op[op].disps = exp; |
252b5132 RH |
2548 | exp->X_op = O_constant; |
2549 | exp->X_add_number = 0; | |
2550 | exp->X_add_symbol = (symbolS *) 0; | |
2551 | exp->X_op_symbol = (symbolS *) 0; | |
2552 | } | |
2553 | } | |
2554 | ||
2555 | /* Fill in i.rm.reg or i.rm.regmem field with register | |
2556 | operand (if any) based on i.tm.extension_opcode. | |
2557 | Again, we must be careful to make sure that | |
2558 | segment/control/debug/test/MMX registers are coded | |
47926f60 | 2559 | into the i.rm.reg field. */ |
252b5132 RH |
2560 | if (i.reg_operands) |
2561 | { | |
2562 | unsigned int op = | |
2563 | ((i.types[0] | |
3f4438ab AM |
2564 | & (Reg | RegMMX | RegXMM |
2565 | | SReg2 | SReg3 | |
2566 | | Control | Debug | Test)) | |
252b5132 RH |
2567 | ? 0 |
2568 | : ((i.types[1] | |
3f4438ab AM |
2569 | & (Reg | RegMMX | RegXMM |
2570 | | SReg2 | SReg3 | |
2571 | | Control | Debug | Test)) | |
252b5132 RH |
2572 | ? 1 |
2573 | : 2)); | |
2574 | /* If there is an extension opcode to put here, the | |
47926f60 | 2575 | register number must be put into the regmem field. */ |
252b5132 | 2576 | if (i.tm.extension_opcode != None) |
3e73aa7c JH |
2577 | { |
2578 | i.rm.regmem = i.op[op].regs->reg_num; | |
2579 | if (i.op[op].regs->reg_flags & RegRex) | |
e5cb08ac | 2580 | i.rex.extZ = 1; |
3e73aa7c | 2581 | } |
252b5132 | 2582 | else |
3e73aa7c JH |
2583 | { |
2584 | i.rm.reg = i.op[op].regs->reg_num; | |
2585 | if (i.op[op].regs->reg_flags & RegRex) | |
e5cb08ac | 2586 | i.rex.extX = 1; |
3e73aa7c | 2587 | } |
252b5132 RH |
2588 | |
2589 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 | |
2590 | we must set it to 3 to indicate this is a register | |
2591 | operand in the regmem field. */ | |
2592 | if (!i.mem_operands) | |
2593 | i.rm.mode = 3; | |
2594 | } | |
2595 | ||
47926f60 | 2596 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
252b5132 RH |
2597 | if (i.tm.extension_opcode != None) |
2598 | i.rm.reg = i.tm.extension_opcode; | |
2599 | } | |
2600 | } | |
2601 | else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm)) | |
2602 | { | |
47926f60 KH |
2603 | if (i.tm.base_opcode == POP_SEG_SHORT |
2604 | && i.op[0].regs->reg_num == 1) | |
252b5132 RH |
2605 | { |
2606 | as_bad (_("you can't `pop %%cs'")); | |
2607 | return; | |
2608 | } | |
520dc8e8 | 2609 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
3e73aa7c JH |
2610 | if (i.op[0].regs->reg_flags & RegRex) |
2611 | i.rex.extZ = 1; | |
252b5132 RH |
2612 | } |
2613 | else if ((i.tm.base_opcode & ~(D|W)) == MOV_AX_DISP32) | |
2614 | { | |
2615 | default_seg = &ds; | |
2616 | } | |
2617 | else if ((i.tm.opcode_modifier & IsString) != 0) | |
2618 | { | |
2619 | /* For the string instructions that allow a segment override | |
2620 | on one of their operands, the default segment is ds. */ | |
2621 | default_seg = &ds; | |
2622 | } | |
2623 | ||
2624 | /* If a segment was explicitly specified, | |
2625 | and the specified segment is not the default, | |
2626 | use an opcode prefix to select it. | |
2627 | If we never figured out what the default segment is, | |
2628 | then default_seg will be zero at this point, | |
2629 | and the specified segment prefix will always be used. */ | |
2630 | if ((i.seg[0]) && (i.seg[0] != default_seg)) | |
2631 | { | |
2632 | if (! add_prefix (i.seg[0]->seg_prefix)) | |
2633 | return; | |
2634 | } | |
2635 | } | |
a38cf1db | 2636 | else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) |
252b5132 | 2637 | { |
24eab124 AM |
2638 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ |
2639 | as_warn (_("translating to `%sp'"), i.tm.name); | |
252b5132 RH |
2640 | } |
2641 | } | |
2642 | ||
47926f60 | 2643 | /* Handle conversion of 'int $3' --> special int3 insn. */ |
520dc8e8 | 2644 | if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3) |
252b5132 RH |
2645 | { |
2646 | i.tm.base_opcode = INT3_OPCODE; | |
2647 | i.imm_operands = 0; | |
2648 | } | |
2649 | ||
2f66722d | 2650 | if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword)) |
520dc8e8 | 2651 | && i.op[0].disps->X_op == O_constant) |
2f66722d AM |
2652 | { |
2653 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
2654 | the absolute address given by the constant. Since ix86 jumps and | |
2655 | calls are pc relative, we need to generate a reloc. */ | |
520dc8e8 AM |
2656 | i.op[0].disps->X_add_symbol = &abs_symbol; |
2657 | i.op[0].disps->X_op = O_symbol; | |
2f66722d AM |
2658 | } |
2659 | ||
3e73aa7c JH |
2660 | if (i.tm.opcode_modifier & Rex64) |
2661 | i.rex.mode64 = 1; | |
2662 | ||
2663 | /* For 8bit registers we would need an empty rex prefix. | |
2664 | Also in the case instruction is already having prefix, | |
2665 | we need to convert old registers to new ones. */ | |
2666 | ||
2667 | if (((i.types[0] & Reg8) && (i.op[0].regs->reg_flags & RegRex64)) | |
2668 | || ((i.types[1] & Reg8) && (i.op[1].regs->reg_flags & RegRex64)) | |
2669 | || ((i.rex.mode64 || i.rex.extX || i.rex.extY || i.rex.extZ || i.rex.empty) | |
2670 | && ((i.types[0] & Reg8) || (i.types[1] & Reg8)))) | |
2671 | { | |
2672 | int x; | |
e5cb08ac | 2673 | i.rex.empty = 1; |
3e73aa7c JH |
2674 | for (x = 0; x < 2; x++) |
2675 | { | |
2676 | /* Look for 8bit operand that does use old registers. */ | |
2677 | if (i.types[x] & Reg8 | |
2678 | && !(i.op[x].regs->reg_flags & RegRex64)) | |
2679 | { | |
2680 | /* In case it is "hi" register, give up. */ | |
2681 | if (i.op[x].regs->reg_num > 3) | |
2682 | as_bad (_("Can't encode registers '%%%s' in the instruction requiring REX prefix.\n"), | |
2683 | i.op[x].regs->reg_name); | |
2684 | ||
2685 | /* Otherwise it is equivalent to the extended register. | |
2686 | Since the encoding don't change this is merely cosmetical | |
2687 | cleanup for debug output. */ | |
2688 | ||
2689 | i.op[x].regs = i.op[x].regs + 8; | |
2690 | } | |
2691 | } | |
2692 | } | |
2693 | ||
2694 | if (i.rex.mode64 || i.rex.extX || i.rex.extY || i.rex.extZ || i.rex.empty) | |
2695 | add_prefix (0x40 | |
2696 | | (i.rex.mode64 ? 8 : 0) | |
2697 | | (i.rex.extX ? 4 : 0) | |
2698 | | (i.rex.extY ? 2 : 0) | |
2699 | | (i.rex.extZ ? 1 : 0)); | |
2700 | ||
47926f60 | 2701 | /* We are ready to output the insn. */ |
252b5132 RH |
2702 | { |
2703 | register char *p; | |
2704 | ||
47926f60 | 2705 | /* Output jumps. */ |
252b5132 RH |
2706 | if (i.tm.opcode_modifier & Jump) |
2707 | { | |
a217f122 AM |
2708 | int code16; |
2709 | int prefix; | |
252b5132 | 2710 | |
a217f122 | 2711 | code16 = 0; |
3e73aa7c | 2712 | if (flag_code == CODE_16BIT) |
a217f122 AM |
2713 | code16 = CODE16; |
2714 | ||
2715 | prefix = 0; | |
2716 | if (i.prefix[DATA_PREFIX]) | |
252b5132 | 2717 | { |
a217f122 | 2718 | prefix = 1; |
252b5132 | 2719 | i.prefixes -= 1; |
a217f122 | 2720 | code16 ^= CODE16; |
252b5132 | 2721 | } |
3e73aa7c JH |
2722 | if (i.prefix[REX_PREFIX]) |
2723 | { | |
2724 | prefix++; | |
e5cb08ac | 2725 | i.prefixes--; |
3e73aa7c | 2726 | } |
252b5132 | 2727 | |
a217f122 | 2728 | if (i.prefixes != 0 && !intel_syntax) |
252b5132 RH |
2729 | as_warn (_("skipping prefixes on this instruction")); |
2730 | ||
2f66722d AM |
2731 | /* It's always a symbol; End frag & setup for relax. |
2732 | Make sure there is enough room in this frag for the largest | |
2733 | instruction we may generate in md_convert_frag. This is 2 | |
2734 | bytes for the opcode and room for the prefix and largest | |
2735 | displacement. */ | |
fddf5b5b | 2736 | frag_grow (prefix + 2 + 4); |
2f66722d AM |
2737 | insn_size += prefix + 1; |
2738 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
2739 | p = frag_more (prefix + 1); | |
3e73aa7c | 2740 | if (i.prefix[DATA_PREFIX]) |
2f66722d | 2741 | *p++ = DATA_PREFIX_OPCODE; |
3e73aa7c JH |
2742 | if (i.prefix[REX_PREFIX]) |
2743 | *p++ = i.prefix[REX_PREFIX]; | |
2f66722d | 2744 | *p = i.tm.base_opcode; |
ee7fcc42 AM |
2745 | /* 1 possible extra opcode + displacement go in var part. |
2746 | Pass reloc in fr_var. */ | |
2f66722d | 2747 | frag_var (rs_machine_dependent, |
fddf5b5b | 2748 | 1 + 4, |
1ae12ab7 | 2749 | i.reloc[0], |
2f66722d AM |
2750 | ((unsigned char) *p == JUMP_PC_RELATIVE |
2751 | ? ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL) | code16 | |
fddf5b5b AM |
2752 | : ((cpu_arch_flags & Cpu386) != 0 |
2753 | ? ENCODE_RELAX_STATE (COND_JUMP, SMALL) | code16 | |
2754 | : ENCODE_RELAX_STATE (COND_JUMP86, SMALL) | code16)), | |
520dc8e8 AM |
2755 | i.op[0].disps->X_add_symbol, |
2756 | i.op[0].disps->X_add_number, | |
2f66722d | 2757 | p); |
252b5132 RH |
2758 | } |
2759 | else if (i.tm.opcode_modifier & (JumpByte | JumpDword)) | |
2760 | { | |
a217f122 | 2761 | int size; |
252b5132 | 2762 | |
a217f122 | 2763 | if (i.tm.opcode_modifier & JumpByte) |
252b5132 | 2764 | { |
a217f122 AM |
2765 | /* This is a loop or jecxz type instruction. */ |
2766 | size = 1; | |
252b5132 RH |
2767 | if (i.prefix[ADDR_PREFIX]) |
2768 | { | |
2769 | insn_size += 1; | |
2770 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
2771 | i.prefixes -= 1; | |
2772 | } | |
2773 | } | |
2774 | else | |
2775 | { | |
a217f122 AM |
2776 | int code16; |
2777 | ||
2778 | code16 = 0; | |
3e73aa7c | 2779 | if (flag_code == CODE_16BIT) |
a217f122 | 2780 | code16 = CODE16; |
252b5132 RH |
2781 | |
2782 | if (i.prefix[DATA_PREFIX]) | |
2783 | { | |
2784 | insn_size += 1; | |
2785 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
2786 | i.prefixes -= 1; | |
a217f122 | 2787 | code16 ^= CODE16; |
252b5132 | 2788 | } |
252b5132 | 2789 | |
a217f122 | 2790 | size = 4; |
252b5132 RH |
2791 | if (code16) |
2792 | size = 2; | |
2793 | } | |
2794 | ||
3e73aa7c JH |
2795 | if (i.prefix[REX_PREFIX]) |
2796 | { | |
2797 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); | |
2798 | insn_size++; | |
2799 | i.prefixes -= 1; | |
2800 | } | |
2801 | ||
a217f122 | 2802 | if (i.prefixes != 0 && !intel_syntax) |
252b5132 RH |
2803 | as_warn (_("skipping prefixes on this instruction")); |
2804 | ||
2805 | if (fits_in_unsigned_byte (i.tm.base_opcode)) | |
2806 | { | |
2807 | insn_size += 1 + size; | |
2808 | p = frag_more (1 + size); | |
2809 | } | |
2810 | else | |
2811 | { | |
47926f60 | 2812 | /* Opcode can be at most two bytes. */ |
a217f122 | 2813 | insn_size += 2 + size; |
252b5132 RH |
2814 | p = frag_more (2 + size); |
2815 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
2816 | } | |
2817 | *p++ = i.tm.base_opcode & 0xff; | |
2818 | ||
2f66722d | 2819 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
1ae12ab7 | 2820 | i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0])); |
252b5132 RH |
2821 | } |
2822 | else if (i.tm.opcode_modifier & JumpInterSegment) | |
2823 | { | |
2824 | int size; | |
a217f122 AM |
2825 | int prefix; |
2826 | int code16; | |
252b5132 | 2827 | |
a217f122 | 2828 | code16 = 0; |
3e73aa7c | 2829 | if (flag_code == CODE_16BIT) |
a217f122 AM |
2830 | code16 = CODE16; |
2831 | ||
2832 | prefix = 0; | |
2833 | if (i.prefix[DATA_PREFIX]) | |
252b5132 | 2834 | { |
a217f122 | 2835 | prefix = 1; |
252b5132 | 2836 | i.prefixes -= 1; |
a217f122 | 2837 | code16 ^= CODE16; |
252b5132 | 2838 | } |
3e73aa7c JH |
2839 | if (i.prefix[REX_PREFIX]) |
2840 | { | |
2841 | prefix++; | |
2842 | i.prefixes -= 1; | |
2843 | } | |
252b5132 RH |
2844 | |
2845 | size = 4; | |
252b5132 | 2846 | if (code16) |
f6af82bd | 2847 | size = 2; |
252b5132 | 2848 | |
a217f122 | 2849 | if (i.prefixes != 0 && !intel_syntax) |
252b5132 RH |
2850 | as_warn (_("skipping prefixes on this instruction")); |
2851 | ||
47926f60 KH |
2852 | /* 1 opcode; 2 segment; offset */ |
2853 | insn_size += prefix + 1 + 2 + size; | |
252b5132 | 2854 | p = frag_more (prefix + 1 + 2 + size); |
3e73aa7c JH |
2855 | |
2856 | if (i.prefix[DATA_PREFIX]) | |
252b5132 | 2857 | *p++ = DATA_PREFIX_OPCODE; |
3e73aa7c JH |
2858 | |
2859 | if (i.prefix[REX_PREFIX]) | |
2860 | *p++ = i.prefix[REX_PREFIX]; | |
2861 | ||
252b5132 | 2862 | *p++ = i.tm.base_opcode; |
520dc8e8 | 2863 | if (i.op[1].imms->X_op == O_constant) |
252b5132 | 2864 | { |
847f7ad4 | 2865 | offsetT n = i.op[1].imms->X_add_number; |
252b5132 | 2866 | |
773f551c AM |
2867 | if (size == 2 |
2868 | && !fits_in_unsigned_word (n) | |
2869 | && !fits_in_signed_word (n)) | |
252b5132 RH |
2870 | { |
2871 | as_bad (_("16-bit jump out of range")); | |
2872 | return; | |
2873 | } | |
847f7ad4 | 2874 | md_number_to_chars (p, n, size); |
252b5132 RH |
2875 | } |
2876 | else | |
2877 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
1ae12ab7 | 2878 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
520dc8e8 | 2879 | if (i.op[0].imms->X_op != O_constant) |
252b5132 RH |
2880 | as_bad (_("can't handle non absolute segment in `%s'"), |
2881 | i.tm.name); | |
520dc8e8 | 2882 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); |
252b5132 RH |
2883 | } |
2884 | else | |
2885 | { | |
47926f60 | 2886 | /* Output normal instructions here. */ |
252b5132 RH |
2887 | unsigned char *q; |
2888 | ||
7bc70a8e JH |
2889 | /* All opcodes on i386 have eighter 1 or 2 bytes. We may use third |
2890 | byte for the SSE instructions to specify prefix they require. */ | |
2891 | if (i.tm.base_opcode & 0xff0000) | |
2892 | add_prefix ((i.tm.base_opcode >> 16) & 0xff); | |
2893 | ||
47926f60 | 2894 | /* The prefix bytes. */ |
252b5132 RH |
2895 | for (q = i.prefix; |
2896 | q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]); | |
2897 | q++) | |
2898 | { | |
2899 | if (*q) | |
2900 | { | |
2901 | insn_size += 1; | |
2902 | p = frag_more (1); | |
2903 | md_number_to_chars (p, (valueT) *q, 1); | |
2904 | } | |
2905 | } | |
2906 | ||
47926f60 | 2907 | /* Now the opcode; be careful about word order here! */ |
252b5132 RH |
2908 | if (fits_in_unsigned_byte (i.tm.base_opcode)) |
2909 | { | |
2910 | insn_size += 1; | |
2911 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
2912 | } | |
7bc70a8e | 2913 | else |
252b5132 RH |
2914 | { |
2915 | insn_size += 2; | |
2916 | p = frag_more (2); | |
47926f60 | 2917 | /* Put out high byte first: can't use md_number_to_chars! */ |
252b5132 RH |
2918 | *p++ = (i.tm.base_opcode >> 8) & 0xff; |
2919 | *p = i.tm.base_opcode & 0xff; | |
2920 | } | |
252b5132 RH |
2921 | |
2922 | /* Now the modrm byte and sib byte (if present). */ | |
2923 | if (i.tm.opcode_modifier & Modrm) | |
2924 | { | |
2925 | insn_size += 1; | |
2926 | p = frag_more (1); | |
2927 | md_number_to_chars (p, | |
2928 | (valueT) (i.rm.regmem << 0 | |
2929 | | i.rm.reg << 3 | |
2930 | | i.rm.mode << 6), | |
2931 | 1); | |
2932 | /* If i.rm.regmem == ESP (4) | |
2933 | && i.rm.mode != (Register mode) | |
2934 | && not 16 bit | |
2935 | ==> need second modrm byte. */ | |
2936 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
2937 | && i.rm.mode != 3 | |
2938 | && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0)) | |
2939 | { | |
2940 | insn_size += 1; | |
2941 | p = frag_more (1); | |
2942 | md_number_to_chars (p, | |
2943 | (valueT) (i.sib.base << 0 | |
2944 | | i.sib.index << 3 | |
2945 | | i.sib.scale << 6), | |
2946 | 1); | |
2947 | } | |
2948 | } | |
2949 | ||
2950 | if (i.disp_operands) | |
2951 | { | |
2952 | register unsigned int n; | |
2953 | ||
2954 | for (n = 0; n < i.operands; n++) | |
2955 | { | |
520dc8e8 | 2956 | if (i.types[n] & Disp) |
252b5132 | 2957 | { |
520dc8e8 | 2958 | if (i.op[n].disps->X_op == O_constant) |
252b5132 | 2959 | { |
847f7ad4 AM |
2960 | int size; |
2961 | offsetT val; | |
b4cac588 | 2962 | |
847f7ad4 | 2963 | size = 4; |
3e73aa7c | 2964 | if (i.types[n] & (Disp8 | Disp16 | Disp64)) |
252b5132 | 2965 | { |
b4cac588 | 2966 | size = 2; |
b4cac588 | 2967 | if (i.types[n] & Disp8) |
847f7ad4 | 2968 | size = 1; |
3e73aa7c JH |
2969 | if (i.types[n] & Disp64) |
2970 | size = 8; | |
252b5132 | 2971 | } |
847f7ad4 AM |
2972 | val = offset_in_range (i.op[n].disps->X_add_number, |
2973 | size); | |
b4cac588 AM |
2974 | insn_size += size; |
2975 | p = frag_more (size); | |
847f7ad4 | 2976 | md_number_to_chars (p, val, size); |
252b5132 | 2977 | } |
252b5132 | 2978 | else |
520dc8e8 AM |
2979 | { |
2980 | int size = 4; | |
3e73aa7c JH |
2981 | int sign = 0; |
2982 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; | |
2983 | ||
2984 | /* The PC relative address is computed relative | |
2985 | to the instruction boundary, so in case immediate | |
2986 | fields follows, we need to adjust the value. */ | |
2987 | if (pcrel && i.imm_operands) | |
2988 | { | |
2989 | int imm_size = 4; | |
2990 | register unsigned int n1; | |
2991 | ||
2992 | for (n1 = 0; n1 < i.operands; n1++) | |
2993 | if (i.types[n1] & Imm) | |
2994 | { | |
2995 | if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64)) | |
2996 | { | |
2997 | imm_size = 2; | |
2998 | if (i.types[n1] & (Imm8 | Imm8S)) | |
2999 | imm_size = 1; | |
3000 | if (i.types[n1] & Imm64) | |
3001 | imm_size = 8; | |
3002 | } | |
3003 | break; | |
3004 | } | |
3005 | /* We should find the immediate. */ | |
3006 | if (n1 == i.operands) | |
bfb32b52 | 3007 | abort (); |
3e73aa7c JH |
3008 | i.op[n].disps->X_add_number -= imm_size; |
3009 | } | |
520dc8e8 | 3010 | |
3e73aa7c JH |
3011 | if (i.types[n] & Disp32S) |
3012 | sign = 1; | |
3013 | ||
e5cb08ac | 3014 | if (i.types[n] & (Disp16 | Disp64)) |
3e73aa7c JH |
3015 | { |
3016 | size = 2; | |
3017 | if (i.types[n] & Disp64) | |
3018 | size = 8; | |
3019 | } | |
520dc8e8 AM |
3020 | |
3021 | insn_size += size; | |
3022 | p = frag_more (size); | |
3023 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
3e73aa7c | 3024 | i.op[n].disps, pcrel, |
1ae12ab7 | 3025 | reloc (size, pcrel, sign, i.reloc[n])); |
252b5132 RH |
3026 | } |
3027 | } | |
3028 | } | |
ce8a8b2f | 3029 | } |
252b5132 | 3030 | |
47926f60 | 3031 | /* Output immediate. */ |
252b5132 RH |
3032 | if (i.imm_operands) |
3033 | { | |
3034 | register unsigned int n; | |
3035 | ||
3036 | for (n = 0; n < i.operands; n++) | |
3037 | { | |
520dc8e8 | 3038 | if (i.types[n] & Imm) |
252b5132 | 3039 | { |
520dc8e8 | 3040 | if (i.op[n].imms->X_op == O_constant) |
252b5132 | 3041 | { |
847f7ad4 AM |
3042 | int size; |
3043 | offsetT val; | |
b4cac588 | 3044 | |
847f7ad4 | 3045 | size = 4; |
3e73aa7c | 3046 | if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64)) |
252b5132 | 3047 | { |
b4cac588 | 3048 | size = 2; |
b4cac588 | 3049 | if (i.types[n] & (Imm8 | Imm8S)) |
847f7ad4 | 3050 | size = 1; |
3e73aa7c JH |
3051 | else if (i.types[n] & Imm64) |
3052 | size = 8; | |
252b5132 | 3053 | } |
847f7ad4 AM |
3054 | val = offset_in_range (i.op[n].imms->X_add_number, |
3055 | size); | |
b4cac588 AM |
3056 | insn_size += size; |
3057 | p = frag_more (size); | |
847f7ad4 | 3058 | md_number_to_chars (p, val, size); |
252b5132 RH |
3059 | } |
3060 | else | |
ce8a8b2f AM |
3061 | { |
3062 | /* Not absolute_section. | |
3063 | Need a 32-bit fixup (don't support 8bit | |
520dc8e8 | 3064 | non-absolute imms). Try to support other |
47926f60 | 3065 | sizes ... */ |
f3c180ae | 3066 | RELOC_ENUM reloc_type; |
520dc8e8 | 3067 | int size = 4; |
3e73aa7c | 3068 | int sign = 0; |
252b5132 | 3069 | |
3e73aa7c JH |
3070 | if ((i.types[n] & (Imm32S)) |
3071 | && i.suffix == QWORD_MNEM_SUFFIX) | |
3072 | sign = 1; | |
3073 | if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64)) | |
3074 | { | |
3075 | size = 2; | |
3076 | if (i.types[n] & (Imm8 | Imm8S)) | |
3077 | size = 1; | |
3078 | if (i.types[n] & Imm64) | |
3079 | size = 8; | |
3080 | } | |
520dc8e8 | 3081 | |
252b5132 RH |
3082 | insn_size += size; |
3083 | p = frag_more (size); | |
1ae12ab7 | 3084 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
252b5132 | 3085 | #ifdef BFD_ASSEMBLER |
f6af82bd | 3086 | if (reloc_type == BFD_RELOC_32 |
252b5132 | 3087 | && GOT_symbol |
520dc8e8 AM |
3088 | && GOT_symbol == i.op[n].imms->X_add_symbol |
3089 | && (i.op[n].imms->X_op == O_symbol | |
3090 | || (i.op[n].imms->X_op == O_add | |
49309057 | 3091 | && ((symbol_get_value_expression |
520dc8e8 | 3092 | (i.op[n].imms->X_op_symbol)->X_op) |
252b5132 RH |
3093 | == O_subtract)))) |
3094 | { | |
3e73aa7c JH |
3095 | /* We don't support dynamic linking on x86-64 yet. */ |
3096 | if (flag_code == CODE_64BIT) | |
bfb32b52 | 3097 | abort (); |
f6af82bd | 3098 | reloc_type = BFD_RELOC_386_GOTPC; |
520dc8e8 | 3099 | i.op[n].imms->X_add_number += 3; |
252b5132 RH |
3100 | } |
3101 | #endif | |
3102 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
520dc8e8 | 3103 | i.op[n].imms, 0, reloc_type); |
252b5132 RH |
3104 | } |
3105 | } | |
3106 | } | |
ce8a8b2f | 3107 | } |
252b5132 RH |
3108 | } |
3109 | ||
e346e481 RH |
3110 | dwarf2_emit_insn (insn_size); |
3111 | ||
252b5132 RH |
3112 | #ifdef DEBUG386 |
3113 | if (flag_debug) | |
3114 | { | |
3115 | pi (line, &i); | |
3116 | } | |
47926f60 | 3117 | #endif /* DEBUG386 */ |
252b5132 RH |
3118 | } |
3119 | } | |
3120 | \f | |
f3c180ae AM |
3121 | #ifndef LEX_AT |
3122 | static char *lex_got PARAMS ((RELOC_ENUM *, int *)); | |
3123 | ||
3124 | /* Parse operands of the form | |
3125 | <symbol>@GOTOFF+<nnn> | |
3126 | and similar .plt or .got references. | |
3127 | ||
3128 | If we find one, set up the correct relocation in RELOC and copy the | |
3129 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
3130 | parsing by the calling routine. Return this buffer, and if ADJUST | |
3131 | is non-null set it to the length of the string we removed from the | |
3132 | input line. Otherwise return NULL. */ | |
3133 | static char * | |
3134 | lex_got (reloc, adjust) | |
3135 | RELOC_ENUM *reloc; | |
3136 | int *adjust; | |
3137 | { | |
3138 | static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" }; | |
3139 | static const struct { | |
3140 | const char *str; | |
3141 | const RELOC_ENUM rel[NUM_FLAG_CODE]; | |
3142 | } gotrel[] = { | |
3143 | { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } }, | |
3144 | { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } }, | |
3145 | { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } }, | |
3146 | { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } } | |
3147 | }; | |
3148 | char *cp; | |
3149 | unsigned int j; | |
3150 | ||
3151 | for (cp = input_line_pointer; *cp != '@'; cp++) | |
3152 | if (is_end_of_line[(unsigned char) *cp]) | |
3153 | return NULL; | |
3154 | ||
3155 | for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++) | |
3156 | { | |
3157 | int len; | |
3158 | ||
3159 | len = strlen (gotrel[j].str); | |
3160 | if (strncmp (cp + 1, gotrel[j].str, len) == 0) | |
3161 | { | |
3162 | if (gotrel[j].rel[(unsigned int) flag_code] != 0) | |
3163 | { | |
3164 | int first; | |
3165 | char *tmpbuf; | |
3166 | ||
3167 | *reloc = gotrel[j].rel[(unsigned int) flag_code]; | |
3168 | ||
3169 | if (GOT_symbol == NULL) | |
3170 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
3171 | ||
3172 | /* Replace the relocation token with ' ', so that | |
3173 | errors like foo@GOTOFF1 will be detected. */ | |
3174 | first = cp - input_line_pointer; | |
3175 | tmpbuf = xmalloc (strlen (input_line_pointer)); | |
3176 | memcpy (tmpbuf, input_line_pointer, first); | |
3177 | tmpbuf[first] = ' '; | |
3178 | strcpy (tmpbuf + first + 1, cp + 1 + len); | |
3179 | if (adjust) | |
3180 | *adjust = len; | |
3181 | return tmpbuf; | |
3182 | } | |
3183 | ||
3184 | as_bad (_("@%s reloc is not supported in %s bit mode"), | |
3185 | gotrel[j].str, mode_name[(unsigned int) flag_code]); | |
3186 | return NULL; | |
3187 | } | |
3188 | } | |
3189 | ||
3190 | /* Might be a symbol version string. Don't as_bad here. */ | |
3191 | return NULL; | |
3192 | } | |
3193 | ||
3194 | /* x86_cons_fix_new is called via the expression parsing code when a | |
3195 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
3196 | static RELOC_ENUM got_reloc = NO_RELOC; | |
3197 | ||
3198 | void | |
3199 | x86_cons_fix_new (frag, off, len, exp) | |
3200 | fragS *frag; | |
3201 | unsigned int off; | |
3202 | unsigned int len; | |
3203 | expressionS *exp; | |
3204 | { | |
3205 | RELOC_ENUM r = reloc (len, 0, 0, got_reloc); | |
3206 | got_reloc = NO_RELOC; | |
3207 | fix_new_exp (frag, off, len, exp, 0, r); | |
3208 | } | |
3209 | ||
3210 | void | |
3211 | x86_cons (exp, size) | |
3212 | expressionS *exp; | |
3213 | int size; | |
3214 | { | |
3215 | if (size == 4) | |
3216 | { | |
3217 | /* Handle @GOTOFF and the like in an expression. */ | |
3218 | char *save; | |
3219 | char *gotfree_input_line; | |
3220 | int adjust; | |
3221 | ||
3222 | save = input_line_pointer; | |
3223 | gotfree_input_line = lex_got (&got_reloc, &adjust); | |
3224 | if (gotfree_input_line) | |
3225 | input_line_pointer = gotfree_input_line; | |
3226 | ||
3227 | expression (exp); | |
3228 | ||
3229 | if (gotfree_input_line) | |
3230 | { | |
3231 | /* expression () has merrily parsed up to the end of line, | |
3232 | or a comma - in the wrong buffer. Transfer how far | |
3233 | input_line_pointer has moved to the right buffer. */ | |
3234 | input_line_pointer = (save | |
3235 | + (input_line_pointer - gotfree_input_line) | |
3236 | + adjust); | |
3237 | free (gotfree_input_line); | |
3238 | } | |
3239 | } | |
3240 | else | |
3241 | expression (exp); | |
3242 | } | |
3243 | #endif | |
3244 | ||
252b5132 RH |
3245 | static int i386_immediate PARAMS ((char *)); |
3246 | ||
3247 | static int | |
3248 | i386_immediate (imm_start) | |
3249 | char *imm_start; | |
3250 | { | |
3251 | char *save_input_line_pointer; | |
f3c180ae AM |
3252 | #ifndef LEX_AT |
3253 | char *gotfree_input_line; | |
3254 | #endif | |
252b5132 | 3255 | segT exp_seg = 0; |
47926f60 | 3256 | expressionS *exp; |
252b5132 RH |
3257 | |
3258 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
3259 | { | |
d0b47220 | 3260 | as_bad (_("only 1 or 2 immediate operands are allowed")); |
252b5132 RH |
3261 | return 0; |
3262 | } | |
3263 | ||
3264 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 3265 | i.op[this_operand].imms = exp; |
252b5132 RH |
3266 | |
3267 | if (is_space_char (*imm_start)) | |
3268 | ++imm_start; | |
3269 | ||
3270 | save_input_line_pointer = input_line_pointer; | |
3271 | input_line_pointer = imm_start; | |
3272 | ||
3273 | #ifndef LEX_AT | |
f3c180ae AM |
3274 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL); |
3275 | if (gotfree_input_line) | |
3276 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
3277 | #endif |
3278 | ||
3279 | exp_seg = expression (exp); | |
3280 | ||
83183c0c | 3281 | SKIP_WHITESPACE (); |
252b5132 | 3282 | if (*input_line_pointer) |
f3c180ae | 3283 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
3284 | |
3285 | input_line_pointer = save_input_line_pointer; | |
f3c180ae AM |
3286 | #ifndef LEX_AT |
3287 | if (gotfree_input_line) | |
3288 | free (gotfree_input_line); | |
3289 | #endif | |
252b5132 | 3290 | |
2daf4fd8 | 3291 | if (exp->X_op == O_absent || exp->X_op == O_big) |
252b5132 | 3292 | { |
47926f60 | 3293 | /* Missing or bad expr becomes absolute 0. */ |
d0b47220 | 3294 | as_bad (_("missing or invalid immediate expression `%s' taken as 0"), |
24eab124 | 3295 | imm_start); |
252b5132 RH |
3296 | exp->X_op = O_constant; |
3297 | exp->X_add_number = 0; | |
3298 | exp->X_add_symbol = (symbolS *) 0; | |
3299 | exp->X_op_symbol = (symbolS *) 0; | |
252b5132 | 3300 | } |
3e73aa7c | 3301 | else if (exp->X_op == O_constant) |
252b5132 | 3302 | { |
47926f60 | 3303 | /* Size it properly later. */ |
3e73aa7c JH |
3304 | i.types[this_operand] |= Imm64; |
3305 | /* If BFD64, sign extend val. */ | |
3306 | if (!use_rela_relocations) | |
3307 | if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) | |
3308 | exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 3309 | } |
4c63da97 | 3310 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
47926f60 | 3311 | else if (1 |
4c63da97 | 3312 | #ifdef BFD_ASSEMBLER |
47926f60 | 3313 | && OUTPUT_FLAVOR == bfd_target_aout_flavour |
4c63da97 | 3314 | #endif |
47926f60 | 3315 | && exp_seg != text_section |
24eab124 AM |
3316 | && exp_seg != data_section |
3317 | && exp_seg != bss_section | |
3318 | && exp_seg != undefined_section | |
252b5132 | 3319 | #ifdef BFD_ASSEMBLER |
24eab124 | 3320 | && !bfd_is_com_section (exp_seg) |
252b5132 | 3321 | #endif |
24eab124 | 3322 | ) |
252b5132 | 3323 | { |
4c63da97 | 3324 | #ifdef BFD_ASSEMBLER |
d0b47220 | 3325 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
4c63da97 | 3326 | #else |
d0b47220 | 3327 | as_bad (_("unimplemented segment type %d in operand"), exp_seg); |
4c63da97 | 3328 | #endif |
252b5132 RH |
3329 | return 0; |
3330 | } | |
3331 | #endif | |
3332 | else | |
3333 | { | |
3334 | /* This is an address. The size of the address will be | |
24eab124 | 3335 | determined later, depending on destination register, |
3e73aa7c JH |
3336 | suffix, or the default for the section. */ |
3337 | i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64; | |
252b5132 RH |
3338 | } |
3339 | ||
3340 | return 1; | |
3341 | } | |
3342 | ||
551c1ca1 | 3343 | static char *i386_scale PARAMS ((char *)); |
252b5132 | 3344 | |
551c1ca1 | 3345 | static char * |
252b5132 RH |
3346 | i386_scale (scale) |
3347 | char *scale; | |
3348 | { | |
551c1ca1 AM |
3349 | offsetT val; |
3350 | char *save = input_line_pointer; | |
252b5132 | 3351 | |
551c1ca1 AM |
3352 | input_line_pointer = scale; |
3353 | val = get_absolute_expression (); | |
3354 | ||
3355 | switch (val) | |
252b5132 | 3356 | { |
551c1ca1 AM |
3357 | case 0: |
3358 | case 1: | |
252b5132 RH |
3359 | i.log2_scale_factor = 0; |
3360 | break; | |
551c1ca1 | 3361 | case 2: |
252b5132 RH |
3362 | i.log2_scale_factor = 1; |
3363 | break; | |
551c1ca1 | 3364 | case 4: |
252b5132 RH |
3365 | i.log2_scale_factor = 2; |
3366 | break; | |
551c1ca1 | 3367 | case 8: |
252b5132 RH |
3368 | i.log2_scale_factor = 3; |
3369 | break; | |
3370 | default: | |
252b5132 | 3371 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), |
24eab124 | 3372 | scale); |
551c1ca1 AM |
3373 | input_line_pointer = save; |
3374 | return NULL; | |
252b5132 RH |
3375 | } |
3376 | if (i.log2_scale_factor != 0 && ! i.index_reg) | |
3377 | { | |
3378 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 3379 | 1 << i.log2_scale_factor); |
252b5132 RH |
3380 | #if SCALE1_WHEN_NO_INDEX |
3381 | i.log2_scale_factor = 0; | |
3382 | #endif | |
3383 | } | |
551c1ca1 AM |
3384 | scale = input_line_pointer; |
3385 | input_line_pointer = save; | |
3386 | return scale; | |
252b5132 RH |
3387 | } |
3388 | ||
3389 | static int i386_displacement PARAMS ((char *, char *)); | |
3390 | ||
3391 | static int | |
3392 | i386_displacement (disp_start, disp_end) | |
3393 | char *disp_start; | |
3394 | char *disp_end; | |
3395 | { | |
3396 | register expressionS *exp; | |
3397 | segT exp_seg = 0; | |
3398 | char *save_input_line_pointer; | |
f3c180ae AM |
3399 | #ifndef LEX_AT |
3400 | char *gotfree_input_line; | |
3401 | #endif | |
252b5132 RH |
3402 | int bigdisp = Disp32; |
3403 | ||
3e73aa7c | 3404 | if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) |
252b5132 | 3405 | bigdisp = Disp16; |
3e73aa7c JH |
3406 | if (flag_code == CODE_64BIT) |
3407 | bigdisp = Disp64; | |
252b5132 RH |
3408 | i.types[this_operand] |= bigdisp; |
3409 | ||
3410 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 3411 | i.op[this_operand].disps = exp; |
252b5132 RH |
3412 | i.disp_operands++; |
3413 | save_input_line_pointer = input_line_pointer; | |
3414 | input_line_pointer = disp_start; | |
3415 | END_STRING_AND_SAVE (disp_end); | |
3416 | ||
3417 | #ifndef GCC_ASM_O_HACK | |
3418 | #define GCC_ASM_O_HACK 0 | |
3419 | #endif | |
3420 | #if GCC_ASM_O_HACK | |
3421 | END_STRING_AND_SAVE (disp_end + 1); | |
3422 | if ((i.types[this_operand] & BaseIndex) != 0 | |
24eab124 | 3423 | && displacement_string_end[-1] == '+') |
252b5132 RH |
3424 | { |
3425 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
3426 | constraint within gcc asm statements. |
3427 | For instance: | |
3428 | ||
3429 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
3430 | __asm__ __volatile__ ( \ | |
3431 | "movw %w2,%0\n\t" \ | |
3432 | "movw %w1,2+%0\n\t" \ | |
3433 | "rorl $16,%1\n\t" \ | |
3434 | "movb %b1,4+%0\n\t" \ | |
3435 | "movb %4,5+%0\n\t" \ | |
3436 | "movb $0,6+%0\n\t" \ | |
3437 | "movb %h1,7+%0\n\t" \ | |
3438 | "rorl $16,%1" \ | |
3439 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
3440 | ||
3441 | This works great except that the output assembler ends | |
3442 | up looking a bit weird if it turns out that there is | |
3443 | no offset. You end up producing code that looks like: | |
3444 | ||
3445 | #APP | |
3446 | movw $235,(%eax) | |
3447 | movw %dx,2+(%eax) | |
3448 | rorl $16,%edx | |
3449 | movb %dl,4+(%eax) | |
3450 | movb $137,5+(%eax) | |
3451 | movb $0,6+(%eax) | |
3452 | movb %dh,7+(%eax) | |
3453 | rorl $16,%edx | |
3454 | #NO_APP | |
3455 | ||
47926f60 | 3456 | So here we provide the missing zero. */ |
24eab124 AM |
3457 | |
3458 | *displacement_string_end = '0'; | |
252b5132 RH |
3459 | } |
3460 | #endif | |
3461 | #ifndef LEX_AT | |
f3c180ae AM |
3462 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL); |
3463 | if (gotfree_input_line) | |
3464 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
3465 | #endif |
3466 | ||
24eab124 | 3467 | exp_seg = expression (exp); |
252b5132 | 3468 | |
636c26b0 AM |
3469 | SKIP_WHITESPACE (); |
3470 | if (*input_line_pointer) | |
3471 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
3472 | #if GCC_ASM_O_HACK | |
3473 | RESTORE_END_STRING (disp_end + 1); | |
3474 | #endif | |
3475 | RESTORE_END_STRING (disp_end); | |
3476 | input_line_pointer = save_input_line_pointer; | |
3477 | #ifndef LEX_AT | |
3478 | if (gotfree_input_line) | |
3479 | free (gotfree_input_line); | |
3480 | #endif | |
3481 | ||
252b5132 | 3482 | #ifdef BFD_ASSEMBLER |
24eab124 AM |
3483 | /* We do this to make sure that the section symbol is in |
3484 | the symbol table. We will ultimately change the relocation | |
47926f60 | 3485 | to be relative to the beginning of the section. */ |
1ae12ab7 AM |
3486 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
3487 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) | |
24eab124 | 3488 | { |
636c26b0 AM |
3489 | if (exp->X_op != O_symbol) |
3490 | { | |
3491 | as_bad (_("bad expression used with @%s"), | |
3492 | (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL | |
3493 | ? "GOTPCREL" | |
3494 | : "GOTOFF")); | |
3495 | return 0; | |
3496 | } | |
3497 | ||
e5cb08ac | 3498 | if (S_IS_LOCAL (exp->X_add_symbol) |
24eab124 AM |
3499 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section) |
3500 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); | |
24eab124 AM |
3501 | exp->X_op = O_subtract; |
3502 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 AM |
3503 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
3504 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; | |
23df1078 | 3505 | else |
1ae12ab7 | 3506 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 3507 | } |
252b5132 RH |
3508 | #endif |
3509 | ||
2daf4fd8 AM |
3510 | if (exp->X_op == O_absent || exp->X_op == O_big) |
3511 | { | |
47926f60 | 3512 | /* Missing or bad expr becomes absolute 0. */ |
d0b47220 | 3513 | as_bad (_("missing or invalid displacement expression `%s' taken as 0"), |
2daf4fd8 AM |
3514 | disp_start); |
3515 | exp->X_op = O_constant; | |
3516 | exp->X_add_number = 0; | |
3517 | exp->X_add_symbol = (symbolS *) 0; | |
3518 | exp->X_op_symbol = (symbolS *) 0; | |
3519 | } | |
3520 | ||
4c63da97 | 3521 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
45288df1 | 3522 | if (exp->X_op != O_constant |
4c63da97 | 3523 | #ifdef BFD_ASSEMBLER |
45288df1 | 3524 | && OUTPUT_FLAVOR == bfd_target_aout_flavour |
4c63da97 | 3525 | #endif |
45288df1 AM |
3526 | && exp_seg != text_section |
3527 | && exp_seg != data_section | |
3528 | && exp_seg != bss_section | |
3529 | && exp_seg != undefined_section) | |
24eab124 | 3530 | { |
4c63da97 | 3531 | #ifdef BFD_ASSEMBLER |
d0b47220 | 3532 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
4c63da97 | 3533 | #else |
d0b47220 | 3534 | as_bad (_("unimplemented segment type %d in operand"), exp_seg); |
4c63da97 | 3535 | #endif |
24eab124 AM |
3536 | return 0; |
3537 | } | |
252b5132 | 3538 | #endif |
3e73aa7c JH |
3539 | else if (flag_code == CODE_64BIT) |
3540 | i.types[this_operand] |= Disp32S | Disp32; | |
252b5132 RH |
3541 | return 1; |
3542 | } | |
3543 | ||
e5cb08ac | 3544 | static int i386_index_check PARAMS ((const char *)); |
252b5132 | 3545 | |
eecb386c | 3546 | /* Make sure the memory operand we've been dealt is valid. |
47926f60 KH |
3547 | Return 1 on success, 0 on a failure. */ |
3548 | ||
252b5132 | 3549 | static int |
eecb386c AM |
3550 | i386_index_check (operand_string) |
3551 | const char *operand_string; | |
252b5132 | 3552 | { |
3e73aa7c | 3553 | int ok; |
24eab124 | 3554 | #if INFER_ADDR_PREFIX |
eecb386c AM |
3555 | int fudged = 0; |
3556 | ||
24eab124 AM |
3557 | tryprefix: |
3558 | #endif | |
3e73aa7c JH |
3559 | ok = 1; |
3560 | if (flag_code == CODE_64BIT) | |
3561 | { | |
3562 | /* 64bit checks. */ | |
3563 | if ((i.base_reg | |
3564 | && ((i.base_reg->reg_type & Reg64) == 0) | |
3565 | && (i.base_reg->reg_type != BaseIndex | |
3566 | || i.index_reg)) | |
3567 | || (i.index_reg | |
3568 | && ((i.index_reg->reg_type & (Reg64|BaseIndex)) | |
3569 | != (Reg64|BaseIndex)))) | |
3570 | ok = 0; | |
3571 | } | |
3572 | else | |
3573 | { | |
3574 | if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) | |
3575 | { | |
3576 | /* 16bit checks. */ | |
3577 | if ((i.base_reg | |
3578 | && ((i.base_reg->reg_type & (Reg16|BaseIndex|RegRex)) | |
3579 | != (Reg16|BaseIndex))) | |
3580 | || (i.index_reg | |
3581 | && (((i.index_reg->reg_type & (Reg16|BaseIndex)) | |
3582 | != (Reg16|BaseIndex)) | |
3583 | || ! (i.base_reg | |
3584 | && i.base_reg->reg_num < 6 | |
3585 | && i.index_reg->reg_num >= 6 | |
3586 | && i.log2_scale_factor == 0)))) | |
3587 | ok = 0; | |
3588 | } | |
3589 | else | |
e5cb08ac | 3590 | { |
3e73aa7c JH |
3591 | /* 32bit checks. */ |
3592 | if ((i.base_reg | |
3593 | && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32) | |
3594 | || (i.index_reg | |
3595 | && ((i.index_reg->reg_type & (Reg32|BaseIndex|RegRex)) | |
3596 | != (Reg32|BaseIndex)))) | |
e5cb08ac | 3597 | ok = 0; |
3e73aa7c JH |
3598 | } |
3599 | } | |
3600 | if (!ok) | |
24eab124 AM |
3601 | { |
3602 | #if INFER_ADDR_PREFIX | |
3e73aa7c JH |
3603 | if (flag_code != CODE_64BIT |
3604 | && i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0') | |
24eab124 AM |
3605 | { |
3606 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
3607 | i.prefixes += 1; | |
b23bac36 AM |
3608 | /* Change the size of any displacement too. At most one of |
3609 | Disp16 or Disp32 is set. | |
3610 | FIXME. There doesn't seem to be any real need for separate | |
3611 | Disp16 and Disp32 flags. The same goes for Imm16 and Imm32. | |
47926f60 | 3612 | Removing them would probably clean up the code quite a lot. */ |
b23bac36 AM |
3613 | if (i.types[this_operand] & (Disp16|Disp32)) |
3614 | i.types[this_operand] ^= (Disp16|Disp32); | |
eecb386c | 3615 | fudged = 1; |
24eab124 AM |
3616 | goto tryprefix; |
3617 | } | |
eecb386c AM |
3618 | if (fudged) |
3619 | as_bad (_("`%s' is not a valid base/index expression"), | |
3620 | operand_string); | |
3621 | else | |
c388dee8 | 3622 | #endif |
eecb386c AM |
3623 | as_bad (_("`%s' is not a valid %s bit base/index expression"), |
3624 | operand_string, | |
3e73aa7c | 3625 | flag_code_names[flag_code]); |
eecb386c | 3626 | return 0; |
24eab124 AM |
3627 | } |
3628 | return 1; | |
3629 | } | |
252b5132 | 3630 | |
252b5132 | 3631 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero |
47926f60 | 3632 | on error. */ |
252b5132 | 3633 | |
252b5132 RH |
3634 | static int |
3635 | i386_operand (operand_string) | |
3636 | char *operand_string; | |
3637 | { | |
af6bdddf AM |
3638 | const reg_entry *r; |
3639 | char *end_op; | |
24eab124 | 3640 | char *op_string = operand_string; |
252b5132 | 3641 | |
24eab124 | 3642 | if (is_space_char (*op_string)) |
252b5132 RH |
3643 | ++op_string; |
3644 | ||
24eab124 | 3645 | /* We check for an absolute prefix (differentiating, |
47926f60 | 3646 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
3647 | if (*op_string == ABSOLUTE_PREFIX) |
3648 | { | |
3649 | ++op_string; | |
3650 | if (is_space_char (*op_string)) | |
3651 | ++op_string; | |
3652 | i.types[this_operand] |= JumpAbsolute; | |
3653 | } | |
252b5132 | 3654 | |
47926f60 | 3655 | /* Check if operand is a register. */ |
af6bdddf AM |
3656 | if ((*op_string == REGISTER_PREFIX || allow_naked_reg) |
3657 | && (r = parse_register (op_string, &end_op)) != NULL) | |
24eab124 | 3658 | { |
24eab124 AM |
3659 | /* Check for a segment override by searching for ':' after a |
3660 | segment register. */ | |
3661 | op_string = end_op; | |
3662 | if (is_space_char (*op_string)) | |
3663 | ++op_string; | |
3664 | if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3))) | |
3665 | { | |
3666 | switch (r->reg_num) | |
3667 | { | |
3668 | case 0: | |
3669 | i.seg[i.mem_operands] = &es; | |
3670 | break; | |
3671 | case 1: | |
3672 | i.seg[i.mem_operands] = &cs; | |
3673 | break; | |
3674 | case 2: | |
3675 | i.seg[i.mem_operands] = &ss; | |
3676 | break; | |
3677 | case 3: | |
3678 | i.seg[i.mem_operands] = &ds; | |
3679 | break; | |
3680 | case 4: | |
3681 | i.seg[i.mem_operands] = &fs; | |
3682 | break; | |
3683 | case 5: | |
3684 | i.seg[i.mem_operands] = &gs; | |
3685 | break; | |
3686 | } | |
252b5132 | 3687 | |
24eab124 | 3688 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
3689 | ++op_string; |
3690 | if (is_space_char (*op_string)) | |
24eab124 | 3691 | ++op_string; |
252b5132 | 3692 | |
24eab124 AM |
3693 | if (!is_digit_char (*op_string) |
3694 | && !is_identifier_char (*op_string) | |
3695 | && *op_string != '(' | |
3696 | && *op_string != ABSOLUTE_PREFIX) | |
3697 | { | |
3698 | as_bad (_("bad memory operand `%s'"), op_string); | |
3699 | return 0; | |
3700 | } | |
47926f60 | 3701 | /* Handle case of %es:*foo. */ |
24eab124 AM |
3702 | if (*op_string == ABSOLUTE_PREFIX) |
3703 | { | |
3704 | ++op_string; | |
3705 | if (is_space_char (*op_string)) | |
3706 | ++op_string; | |
3707 | i.types[this_operand] |= JumpAbsolute; | |
3708 | } | |
3709 | goto do_memory_reference; | |
3710 | } | |
3711 | if (*op_string) | |
3712 | { | |
d0b47220 | 3713 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
3714 | return 0; |
3715 | } | |
3716 | i.types[this_operand] |= r->reg_type & ~BaseIndex; | |
520dc8e8 | 3717 | i.op[this_operand].regs = r; |
24eab124 AM |
3718 | i.reg_operands++; |
3719 | } | |
af6bdddf AM |
3720 | else if (*op_string == REGISTER_PREFIX) |
3721 | { | |
3722 | as_bad (_("bad register name `%s'"), op_string); | |
3723 | return 0; | |
3724 | } | |
24eab124 | 3725 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 3726 | { |
24eab124 AM |
3727 | ++op_string; |
3728 | if (i.types[this_operand] & JumpAbsolute) | |
3729 | { | |
d0b47220 | 3730 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
3731 | return 0; |
3732 | } | |
3733 | if (!i386_immediate (op_string)) | |
3734 | return 0; | |
3735 | } | |
3736 | else if (is_digit_char (*op_string) | |
3737 | || is_identifier_char (*op_string) | |
e5cb08ac | 3738 | || *op_string == '(') |
24eab124 | 3739 | { |
47926f60 | 3740 | /* This is a memory reference of some sort. */ |
af6bdddf | 3741 | char *base_string; |
252b5132 | 3742 | |
47926f60 | 3743 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
3744 | char *displacement_string_start; |
3745 | char *displacement_string_end; | |
252b5132 | 3746 | |
24eab124 | 3747 | do_memory_reference: |
24eab124 AM |
3748 | if ((i.mem_operands == 1 |
3749 | && (current_templates->start->opcode_modifier & IsString) == 0) | |
3750 | || i.mem_operands == 2) | |
3751 | { | |
3752 | as_bad (_("too many memory references for `%s'"), | |
3753 | current_templates->start->name); | |
3754 | return 0; | |
3755 | } | |
252b5132 | 3756 | |
24eab124 AM |
3757 | /* Check for base index form. We detect the base index form by |
3758 | looking for an ')' at the end of the operand, searching | |
3759 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
3760 | after the '('. */ | |
af6bdddf | 3761 | base_string = op_string + strlen (op_string); |
c3332e24 | 3762 | |
af6bdddf AM |
3763 | --base_string; |
3764 | if (is_space_char (*base_string)) | |
3765 | --base_string; | |
252b5132 | 3766 | |
47926f60 | 3767 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
3768 | displacement_string_start = op_string; |
3769 | displacement_string_end = base_string + 1; | |
252b5132 | 3770 | |
24eab124 AM |
3771 | if (*base_string == ')') |
3772 | { | |
af6bdddf | 3773 | char *temp_string; |
24eab124 AM |
3774 | unsigned int parens_balanced = 1; |
3775 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 3776 | equal, so this loop will not be infinite. */ |
24eab124 AM |
3777 | do |
3778 | { | |
3779 | base_string--; | |
3780 | if (*base_string == ')') | |
3781 | parens_balanced++; | |
3782 | if (*base_string == '(') | |
3783 | parens_balanced--; | |
3784 | } | |
3785 | while (parens_balanced); | |
c3332e24 | 3786 | |
af6bdddf | 3787 | temp_string = base_string; |
c3332e24 | 3788 | |
24eab124 | 3789 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
3790 | ++base_string; |
3791 | if (is_space_char (*base_string)) | |
24eab124 | 3792 | ++base_string; |
252b5132 | 3793 | |
af6bdddf AM |
3794 | if (*base_string == ',' |
3795 | || ((*base_string == REGISTER_PREFIX || allow_naked_reg) | |
3796 | && (i.base_reg = parse_register (base_string, &end_op)) != NULL)) | |
252b5132 | 3797 | { |
af6bdddf | 3798 | displacement_string_end = temp_string; |
252b5132 | 3799 | |
af6bdddf | 3800 | i.types[this_operand] |= BaseIndex; |
252b5132 | 3801 | |
af6bdddf | 3802 | if (i.base_reg) |
24eab124 | 3803 | { |
24eab124 AM |
3804 | base_string = end_op; |
3805 | if (is_space_char (*base_string)) | |
3806 | ++base_string; | |
af6bdddf AM |
3807 | } |
3808 | ||
3809 | /* There may be an index reg or scale factor here. */ | |
3810 | if (*base_string == ',') | |
3811 | { | |
3812 | ++base_string; | |
3813 | if (is_space_char (*base_string)) | |
3814 | ++base_string; | |
3815 | ||
3816 | if ((*base_string == REGISTER_PREFIX || allow_naked_reg) | |
3817 | && (i.index_reg = parse_register (base_string, &end_op)) != NULL) | |
24eab124 | 3818 | { |
af6bdddf | 3819 | base_string = end_op; |
24eab124 AM |
3820 | if (is_space_char (*base_string)) |
3821 | ++base_string; | |
af6bdddf AM |
3822 | if (*base_string == ',') |
3823 | { | |
3824 | ++base_string; | |
3825 | if (is_space_char (*base_string)) | |
3826 | ++base_string; | |
3827 | } | |
e5cb08ac | 3828 | else if (*base_string != ')') |
af6bdddf AM |
3829 | { |
3830 | as_bad (_("expecting `,' or `)' after index register in `%s'"), | |
3831 | operand_string); | |
3832 | return 0; | |
3833 | } | |
24eab124 | 3834 | } |
af6bdddf | 3835 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 3836 | { |
af6bdddf | 3837 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
3838 | return 0; |
3839 | } | |
252b5132 | 3840 | |
47926f60 | 3841 | /* Check for scale factor. */ |
551c1ca1 | 3842 | if (*base_string != ')') |
af6bdddf | 3843 | { |
551c1ca1 AM |
3844 | char *end_scale = i386_scale (base_string); |
3845 | ||
3846 | if (!end_scale) | |
af6bdddf | 3847 | return 0; |
24eab124 | 3848 | |
551c1ca1 | 3849 | base_string = end_scale; |
af6bdddf AM |
3850 | if (is_space_char (*base_string)) |
3851 | ++base_string; | |
3852 | if (*base_string != ')') | |
3853 | { | |
3854 | as_bad (_("expecting `)' after scale factor in `%s'"), | |
3855 | operand_string); | |
3856 | return 0; | |
3857 | } | |
3858 | } | |
3859 | else if (!i.index_reg) | |
24eab124 | 3860 | { |
af6bdddf AM |
3861 | as_bad (_("expecting index register or scale factor after `,'; got '%c'"), |
3862 | *base_string); | |
24eab124 AM |
3863 | return 0; |
3864 | } | |
3865 | } | |
af6bdddf | 3866 | else if (*base_string != ')') |
24eab124 | 3867 | { |
af6bdddf AM |
3868 | as_bad (_("expecting `,' or `)' after base register in `%s'"), |
3869 | operand_string); | |
24eab124 AM |
3870 | return 0; |
3871 | } | |
c3332e24 | 3872 | } |
af6bdddf | 3873 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 3874 | { |
af6bdddf | 3875 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 3876 | return 0; |
c3332e24 | 3877 | } |
24eab124 AM |
3878 | } |
3879 | ||
3880 | /* If there's an expression beginning the operand, parse it, | |
3881 | assuming displacement_string_start and | |
3882 | displacement_string_end are meaningful. */ | |
3883 | if (displacement_string_start != displacement_string_end) | |
3884 | { | |
3885 | if (!i386_displacement (displacement_string_start, | |
3886 | displacement_string_end)) | |
3887 | return 0; | |
3888 | } | |
3889 | ||
3890 | /* Special case for (%dx) while doing input/output op. */ | |
3891 | if (i.base_reg | |
3892 | && i.base_reg->reg_type == (Reg16 | InOutPortReg) | |
3893 | && i.index_reg == 0 | |
3894 | && i.log2_scale_factor == 0 | |
3895 | && i.seg[i.mem_operands] == 0 | |
3896 | && (i.types[this_operand] & Disp) == 0) | |
3897 | { | |
3898 | i.types[this_operand] = InOutPortReg; | |
3899 | return 1; | |
3900 | } | |
3901 | ||
eecb386c AM |
3902 | if (i386_index_check (operand_string) == 0) |
3903 | return 0; | |
24eab124 AM |
3904 | i.mem_operands++; |
3905 | } | |
3906 | else | |
ce8a8b2f AM |
3907 | { |
3908 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
3909 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
3910 | output_invalid (*op_string), | |
3911 | this_operand + 1, | |
3912 | op_string); | |
3913 | return 0; | |
3914 | } | |
47926f60 | 3915 | return 1; /* Normal return. */ |
252b5132 RH |
3916 | } |
3917 | \f | |
ee7fcc42 AM |
3918 | /* md_estimate_size_before_relax() |
3919 | ||
3920 | Called just before relax() for rs_machine_dependent frags. The x86 | |
3921 | assembler uses these frags to handle variable size jump | |
3922 | instructions. | |
3923 | ||
3924 | Any symbol that is now undefined will not become defined. | |
3925 | Return the correct fr_subtype in the frag. | |
3926 | Return the initial "guess for variable size of frag" to caller. | |
3927 | The guess is actually the growth beyond the fixed part. Whatever | |
3928 | we do to grow the fixed or variable part contributes to our | |
3929 | returned value. */ | |
3930 | ||
252b5132 RH |
3931 | int |
3932 | md_estimate_size_before_relax (fragP, segment) | |
3933 | register fragS *fragP; | |
3934 | register segT segment; | |
3935 | { | |
252b5132 | 3936 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
3937 | check for un-relaxable symbols. On an ELF system, we can't relax |
3938 | an externally visible symbol, because it may be overridden by a | |
3939 | shared library. */ | |
3940 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 3941 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
b98ef147 AM |
3942 | || S_IS_EXTERNAL (fragP->fr_symbol) |
3943 | || S_IS_WEAK (fragP->fr_symbol) | |
3944 | #endif | |
3945 | ) | |
252b5132 | 3946 | { |
b98ef147 AM |
3947 | /* Symbol is undefined in this segment, or we need to keep a |
3948 | reloc so that weak symbols can be overridden. */ | |
3949 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f3c180ae | 3950 | RELOC_ENUM reloc_type; |
ee7fcc42 AM |
3951 | unsigned char *opcode; |
3952 | int old_fr_fix; | |
f6af82bd | 3953 | |
ee7fcc42 AM |
3954 | if (fragP->fr_var != NO_RELOC) |
3955 | reloc_type = fragP->fr_var; | |
b98ef147 | 3956 | else if (size == 2) |
f6af82bd AM |
3957 | reloc_type = BFD_RELOC_16_PCREL; |
3958 | else | |
3959 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 3960 | |
ee7fcc42 AM |
3961 | old_fr_fix = fragP->fr_fix; |
3962 | opcode = (unsigned char *) fragP->fr_opcode; | |
3963 | ||
fddf5b5b | 3964 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 3965 | { |
fddf5b5b AM |
3966 | case UNCOND_JUMP: |
3967 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 3968 | opcode[0] = 0xe9; |
252b5132 RH |
3969 | fragP->fr_fix += size; |
3970 | fix_new (fragP, old_fr_fix, size, | |
3971 | fragP->fr_symbol, | |
3972 | fragP->fr_offset, 1, | |
f6af82bd | 3973 | reloc_type); |
252b5132 RH |
3974 | break; |
3975 | ||
fddf5b5b AM |
3976 | case COND_JUMP86: |
3977 | if (no_cond_jump_promotion) | |
93c2a809 AM |
3978 | goto relax_guess; |
3979 | ||
fddf5b5b AM |
3980 | if (size == 2) |
3981 | { | |
3982 | /* Negate the condition, and branch past an | |
3983 | unconditional jump. */ | |
3984 | opcode[0] ^= 1; | |
3985 | opcode[1] = 3; | |
3986 | /* Insert an unconditional jump. */ | |
3987 | opcode[2] = 0xe9; | |
3988 | /* We added two extra opcode bytes, and have a two byte | |
3989 | offset. */ | |
3990 | fragP->fr_fix += 2 + 2; | |
3991 | fix_new (fragP, old_fr_fix + 2, 2, | |
3992 | fragP->fr_symbol, | |
3993 | fragP->fr_offset, 1, | |
3994 | reloc_type); | |
3995 | break; | |
3996 | } | |
3997 | /* Fall through. */ | |
3998 | ||
3999 | case COND_JUMP: | |
4000 | if (no_cond_jump_promotion) | |
93c2a809 AM |
4001 | goto relax_guess; |
4002 | ||
24eab124 | 4003 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 4004 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 4005 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 4006 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
4007 | /* We've added an opcode byte. */ |
4008 | fragP->fr_fix += 1 + size; | |
252b5132 RH |
4009 | fix_new (fragP, old_fr_fix + 1, size, |
4010 | fragP->fr_symbol, | |
4011 | fragP->fr_offset, 1, | |
f6af82bd | 4012 | reloc_type); |
252b5132 | 4013 | break; |
fddf5b5b AM |
4014 | |
4015 | default: | |
4016 | BAD_CASE (fragP->fr_subtype); | |
4017 | break; | |
252b5132 RH |
4018 | } |
4019 | frag_wane (fragP); | |
ee7fcc42 | 4020 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 4021 | } |
93c2a809 AM |
4022 | |
4023 | relax_guess: | |
4024 | /* Guess size depending on current relax state. Initially the relax | |
4025 | state will correspond to a short jump and we return 1, because | |
4026 | the variable part of the frag (the branch offset) is one byte | |
4027 | long. However, we can relax a section more than once and in that | |
4028 | case we must either set fr_subtype back to the unrelaxed state, | |
4029 | or return the value for the appropriate branch. */ | |
4030 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
4031 | } |
4032 | ||
47926f60 KH |
4033 | /* Called after relax() is finished. |
4034 | ||
4035 | In: Address of frag. | |
4036 | fr_type == rs_machine_dependent. | |
4037 | fr_subtype is what the address relaxed to. | |
4038 | ||
4039 | Out: Any fixSs and constants are set up. | |
4040 | Caller will turn frag into a ".space 0". */ | |
4041 | ||
252b5132 RH |
4042 | #ifndef BFD_ASSEMBLER |
4043 | void | |
4044 | md_convert_frag (headers, sec, fragP) | |
a04b544b ILT |
4045 | object_headers *headers ATTRIBUTE_UNUSED; |
4046 | segT sec ATTRIBUTE_UNUSED; | |
252b5132 RH |
4047 | register fragS *fragP; |
4048 | #else | |
4049 | void | |
4050 | md_convert_frag (abfd, sec, fragP) | |
ab9da554 ILT |
4051 | bfd *abfd ATTRIBUTE_UNUSED; |
4052 | segT sec ATTRIBUTE_UNUSED; | |
252b5132 RH |
4053 | register fragS *fragP; |
4054 | #endif | |
4055 | { | |
4056 | register unsigned char *opcode; | |
4057 | unsigned char *where_to_put_displacement = NULL; | |
847f7ad4 AM |
4058 | offsetT target_address; |
4059 | offsetT opcode_address; | |
252b5132 | 4060 | unsigned int extension = 0; |
847f7ad4 | 4061 | offsetT displacement_from_opcode_start; |
252b5132 RH |
4062 | |
4063 | opcode = (unsigned char *) fragP->fr_opcode; | |
4064 | ||
47926f60 | 4065 | /* Address we want to reach in file space. */ |
252b5132 | 4066 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
47926f60 KH |
4067 | #ifdef BFD_ASSEMBLER |
4068 | /* Not needed otherwise? */ | |
49309057 | 4069 | target_address += symbol_get_frag (fragP->fr_symbol)->fr_address; |
252b5132 RH |
4070 | #endif |
4071 | ||
47926f60 | 4072 | /* Address opcode resides at in file space. */ |
252b5132 RH |
4073 | opcode_address = fragP->fr_address + fragP->fr_fix; |
4074 | ||
47926f60 | 4075 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
4076 | displacement_from_opcode_start = target_address - opcode_address; |
4077 | ||
fddf5b5b | 4078 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 4079 | { |
47926f60 KH |
4080 | /* Don't have to change opcode. */ |
4081 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 4082 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
4083 | } |
4084 | else | |
4085 | { | |
4086 | if (no_cond_jump_promotion | |
4087 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4088 | as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required")); | |
252b5132 | 4089 | |
fddf5b5b AM |
4090 | switch (fragP->fr_subtype) |
4091 | { | |
4092 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
4093 | extension = 4; /* 1 opcode + 4 displacement */ | |
4094 | opcode[0] = 0xe9; | |
4095 | where_to_put_displacement = &opcode[1]; | |
4096 | break; | |
252b5132 | 4097 | |
fddf5b5b AM |
4098 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
4099 | extension = 2; /* 1 opcode + 2 displacement */ | |
4100 | opcode[0] = 0xe9; | |
4101 | where_to_put_displacement = &opcode[1]; | |
4102 | break; | |
252b5132 | 4103 | |
fddf5b5b AM |
4104 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
4105 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
4106 | extension = 5; /* 2 opcode + 4 displacement */ | |
4107 | opcode[1] = opcode[0] + 0x10; | |
4108 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
4109 | where_to_put_displacement = &opcode[2]; | |
4110 | break; | |
252b5132 | 4111 | |
fddf5b5b AM |
4112 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
4113 | extension = 3; /* 2 opcode + 2 displacement */ | |
4114 | opcode[1] = opcode[0] + 0x10; | |
4115 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
4116 | where_to_put_displacement = &opcode[2]; | |
4117 | break; | |
252b5132 | 4118 | |
fddf5b5b AM |
4119 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
4120 | extension = 4; | |
4121 | opcode[0] ^= 1; | |
4122 | opcode[1] = 3; | |
4123 | opcode[2] = 0xe9; | |
4124 | where_to_put_displacement = &opcode[3]; | |
4125 | break; | |
4126 | ||
4127 | default: | |
4128 | BAD_CASE (fragP->fr_subtype); | |
4129 | break; | |
4130 | } | |
252b5132 | 4131 | } |
fddf5b5b | 4132 | |
47926f60 | 4133 | /* Now put displacement after opcode. */ |
252b5132 RH |
4134 | md_number_to_chars ((char *) where_to_put_displacement, |
4135 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 4136 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
4137 | fragP->fr_fix += extension; |
4138 | } | |
4139 | \f | |
47926f60 KH |
4140 | /* Size of byte displacement jmp. */ |
4141 | int md_short_jump_size = 2; | |
4142 | ||
4143 | /* Size of dword displacement jmp. */ | |
4144 | int md_long_jump_size = 5; | |
252b5132 | 4145 | |
47926f60 KH |
4146 | /* Size of relocation record. */ |
4147 | const int md_reloc_size = 8; | |
252b5132 RH |
4148 | |
4149 | void | |
4150 | md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
4151 | char *ptr; | |
4152 | addressT from_addr, to_addr; | |
ab9da554 ILT |
4153 | fragS *frag ATTRIBUTE_UNUSED; |
4154 | symbolS *to_symbol ATTRIBUTE_UNUSED; | |
252b5132 | 4155 | { |
847f7ad4 | 4156 | offsetT offset; |
252b5132 RH |
4157 | |
4158 | offset = to_addr - (from_addr + 2); | |
47926f60 KH |
4159 | /* Opcode for byte-disp jump. */ |
4160 | md_number_to_chars (ptr, (valueT) 0xeb, 1); | |
252b5132 RH |
4161 | md_number_to_chars (ptr + 1, (valueT) offset, 1); |
4162 | } | |
4163 | ||
4164 | void | |
4165 | md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
4166 | char *ptr; | |
4167 | addressT from_addr, to_addr; | |
a38cf1db AM |
4168 | fragS *frag ATTRIBUTE_UNUSED; |
4169 | symbolS *to_symbol ATTRIBUTE_UNUSED; | |
252b5132 | 4170 | { |
847f7ad4 | 4171 | offsetT offset; |
252b5132 | 4172 | |
a38cf1db AM |
4173 | offset = to_addr - (from_addr + 5); |
4174 | md_number_to_chars (ptr, (valueT) 0xe9, 1); | |
4175 | md_number_to_chars (ptr + 1, (valueT) offset, 4); | |
252b5132 RH |
4176 | } |
4177 | \f | |
4178 | /* Apply a fixup (fixS) to segment data, once it has been determined | |
4179 | by our caller that we have all the info we need to fix it up. | |
4180 | ||
4181 | On the 386, immediates, displacements, and data pointers are all in | |
4182 | the same (little-endian) format, so we don't need to care about which | |
4183 | we are handling. */ | |
4184 | ||
4185 | int | |
4186 | md_apply_fix3 (fixP, valp, seg) | |
47926f60 KH |
4187 | /* The fix we're to put in. */ |
4188 | fixS *fixP; | |
4189 | ||
4190 | /* Pointer to the value of the bits. */ | |
4191 | valueT *valp; | |
4192 | ||
4193 | /* Segment fix is from. */ | |
4194 | segT seg ATTRIBUTE_UNUSED; | |
252b5132 RH |
4195 | { |
4196 | register char *p = fixP->fx_where + fixP->fx_frag->fr_literal; | |
4197 | valueT value = *valp; | |
4198 | ||
e1b283bb | 4199 | #if defined (BFD_ASSEMBLER) && !defined (TE_Mach) |
93382f6d AM |
4200 | if (fixP->fx_pcrel) |
4201 | { | |
4202 | switch (fixP->fx_r_type) | |
4203 | { | |
5865bb77 ILT |
4204 | default: |
4205 | break; | |
4206 | ||
93382f6d AM |
4207 | case BFD_RELOC_32: |
4208 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
4209 | break; | |
4210 | case BFD_RELOC_16: | |
4211 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
4212 | break; | |
4213 | case BFD_RELOC_8: | |
4214 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
4215 | break; | |
4216 | } | |
4217 | } | |
252b5132 | 4218 | |
0723899b ILT |
4219 | /* This is a hack. There should be a better way to handle this. |
4220 | This covers for the fact that bfd_install_relocation will | |
4221 | subtract the current location (for partial_inplace, PC relative | |
4222 | relocations); see more below. */ | |
93382f6d AM |
4223 | if ((fixP->fx_r_type == BFD_RELOC_32_PCREL |
4224 | || fixP->fx_r_type == BFD_RELOC_16_PCREL | |
4225 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) | |
7c44d1d3 | 4226 | && fixP->fx_addsy && !use_rela_relocations) |
252b5132 RH |
4227 | { |
4228 | #ifndef OBJ_AOUT | |
4229 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
4230 | #ifdef TE_PE | |
4231 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
4232 | #endif | |
4233 | ) | |
4234 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
4235 | #endif | |
4236 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2f66722d | 4237 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
252b5132 | 4238 | { |
2f66722d AM |
4239 | segT fseg = S_GET_SEGMENT (fixP->fx_addsy); |
4240 | ||
4241 | if ((fseg == seg | |
4242 | || (symbol_section_p (fixP->fx_addsy) | |
4243 | && fseg != absolute_section)) | |
4244 | && ! S_IS_EXTERNAL (fixP->fx_addsy) | |
4245 | && ! S_IS_WEAK (fixP->fx_addsy) | |
4246 | && S_IS_DEFINED (fixP->fx_addsy) | |
4247 | && ! S_IS_COMMON (fixP->fx_addsy)) | |
4248 | { | |
4249 | /* Yes, we add the values in twice. This is because | |
4250 | bfd_perform_relocation subtracts them out again. I think | |
4251 | bfd_perform_relocation is broken, but I don't dare change | |
4252 | it. FIXME. */ | |
4253 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
4254 | } | |
252b5132 RH |
4255 | } |
4256 | #endif | |
4257 | #if defined (OBJ_COFF) && defined (TE_PE) | |
4258 | /* For some reason, the PE format does not store a section | |
24eab124 | 4259 | address offset for a PC relative symbol. */ |
252b5132 RH |
4260 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg) |
4261 | value += md_pcrel_from (fixP); | |
4262 | #endif | |
4263 | } | |
4264 | ||
4265 | /* Fix a few things - the dynamic linker expects certain values here, | |
47926f60 | 4266 | and we must not dissappoint it. */ |
252b5132 RH |
4267 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
4268 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
4269 | && fixP->fx_addsy) | |
47926f60 KH |
4270 | switch (fixP->fx_r_type) |
4271 | { | |
4272 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 4273 | case BFD_RELOC_X86_64_PLT32: |
47926f60 KH |
4274 | /* Make the jump instruction point to the address of the operand. At |
4275 | runtime we merely add the offset to the actual PLT entry. */ | |
4276 | value = -4; | |
4277 | break; | |
4278 | case BFD_RELOC_386_GOTPC: | |
4279 | ||
4280 | /* This is tough to explain. We end up with this one if we have | |
252b5132 RH |
4281 | * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal |
4282 | * here is to obtain the absolute address of the GOT, and it is strongly | |
4283 | * preferable from a performance point of view to avoid using a runtime | |
c3332e24 | 4284 | * relocation for this. The actual sequence of instructions often look |
252b5132 | 4285 | * something like: |
c3332e24 | 4286 | * |
24eab124 | 4287 | * call .L66 |
252b5132 | 4288 | * .L66: |
24eab124 AM |
4289 | * popl %ebx |
4290 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
c3332e24 | 4291 | * |
24eab124 | 4292 | * The call and pop essentially return the absolute address of |
252b5132 RH |
4293 | * the label .L66 and store it in %ebx. The linker itself will |
4294 | * ultimately change the first operand of the addl so that %ebx points to | |
4295 | * the GOT, but to keep things simple, the .o file must have this operand | |
4296 | * set so that it generates not the absolute address of .L66, but the | |
4297 | * absolute address of itself. This allows the linker itself simply | |
4298 | * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be | |
4299 | * added in, and the addend of the relocation is stored in the operand | |
4300 | * field for the instruction itself. | |
c3332e24 | 4301 | * |
24eab124 | 4302 | * Our job here is to fix the operand so that it would add the correct |
252b5132 RH |
4303 | * offset so that %ebx would point to itself. The thing that is tricky is |
4304 | * that .-.L66 will point to the beginning of the instruction, so we need | |
4305 | * to further modify the operand so that it will point to itself. | |
4306 | * There are other cases where you have something like: | |
c3332e24 | 4307 | * |
24eab124 | 4308 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] |
c3332e24 | 4309 | * |
252b5132 | 4310 | * and here no correction would be required. Internally in the assembler |
c3332e24 | 4311 | * we treat operands of this form as not being pcrel since the '.' is |
252b5132 RH |
4312 | * explicitly mentioned, and I wonder whether it would simplify matters |
4313 | * to do it this way. Who knows. In earlier versions of the PIC patches, | |
4314 | * the pcrel_adjust field was used to store the correction, but since the | |
47926f60 KH |
4315 | * expression is not pcrel, I felt it would be confusing to do it this |
4316 | * way. */ | |
4317 | ||
4318 | value -= 1; | |
4319 | break; | |
4320 | case BFD_RELOC_386_GOT32: | |
3e73aa7c | 4321 | case BFD_RELOC_X86_64_GOT32: |
47926f60 KH |
4322 | value = 0; /* Fully resolved at runtime. No addend. */ |
4323 | break; | |
4324 | case BFD_RELOC_386_GOTOFF: | |
3e73aa7c | 4325 | case BFD_RELOC_X86_64_GOTPCREL: |
47926f60 KH |
4326 | break; |
4327 | ||
4328 | case BFD_RELOC_VTABLE_INHERIT: | |
4329 | case BFD_RELOC_VTABLE_ENTRY: | |
4330 | fixP->fx_done = 0; | |
4331 | return 1; | |
4332 | ||
4333 | default: | |
4334 | break; | |
4335 | } | |
4336 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
93382f6d | 4337 | *valp = value; |
47926f60 | 4338 | #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */ |
3e73aa7c JH |
4339 | |
4340 | #ifndef BFD_ASSEMBLER | |
252b5132 | 4341 | md_number_to_chars (p, value, fixP->fx_size); |
3e73aa7c JH |
4342 | #else |
4343 | /* Are we finished with this relocation now? */ | |
4344 | if (fixP->fx_addsy == 0 && fixP->fx_pcrel == 0) | |
4345 | fixP->fx_done = 1; | |
4346 | else if (use_rela_relocations) | |
4347 | { | |
4348 | fixP->fx_no_overflow = 1; | |
4349 | value = 0; | |
4350 | } | |
4351 | md_number_to_chars (p, value, fixP->fx_size); | |
4352 | #endif | |
252b5132 RH |
4353 | |
4354 | return 1; | |
4355 | } | |
252b5132 | 4356 | \f |
252b5132 RH |
4357 | #define MAX_LITTLENUMS 6 |
4358 | ||
47926f60 KH |
4359 | /* Turn the string pointed to by litP into a floating point constant |
4360 | of type TYPE, and emit the appropriate bytes. The number of | |
4361 | LITTLENUMS emitted is stored in *SIZEP. An error message is | |
4362 | returned, or NULL on OK. */ | |
4363 | ||
252b5132 RH |
4364 | char * |
4365 | md_atof (type, litP, sizeP) | |
2ab9b79e | 4366 | int type; |
252b5132 RH |
4367 | char *litP; |
4368 | int *sizeP; | |
4369 | { | |
4370 | int prec; | |
4371 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
4372 | LITTLENUM_TYPE *wordP; | |
4373 | char *t; | |
4374 | ||
4375 | switch (type) | |
4376 | { | |
4377 | case 'f': | |
4378 | case 'F': | |
4379 | prec = 2; | |
4380 | break; | |
4381 | ||
4382 | case 'd': | |
4383 | case 'D': | |
4384 | prec = 4; | |
4385 | break; | |
4386 | ||
4387 | case 'x': | |
4388 | case 'X': | |
4389 | prec = 5; | |
4390 | break; | |
4391 | ||
4392 | default: | |
4393 | *sizeP = 0; | |
4394 | return _("Bad call to md_atof ()"); | |
4395 | } | |
4396 | t = atof_ieee (input_line_pointer, type, words); | |
4397 | if (t) | |
4398 | input_line_pointer = t; | |
4399 | ||
4400 | *sizeP = prec * sizeof (LITTLENUM_TYPE); | |
4401 | /* This loops outputs the LITTLENUMs in REVERSE order; in accord with | |
4402 | the bigendian 386. */ | |
4403 | for (wordP = words + prec - 1; prec--;) | |
4404 | { | |
4405 | md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE)); | |
4406 | litP += sizeof (LITTLENUM_TYPE); | |
4407 | } | |
4408 | return 0; | |
4409 | } | |
4410 | \f | |
4411 | char output_invalid_buf[8]; | |
4412 | ||
252b5132 RH |
4413 | static char * |
4414 | output_invalid (c) | |
4415 | int c; | |
4416 | { | |
4417 | if (isprint (c)) | |
4418 | sprintf (output_invalid_buf, "'%c'", c); | |
4419 | else | |
4420 | sprintf (output_invalid_buf, "(0x%x)", (unsigned) c); | |
4421 | return output_invalid_buf; | |
4422 | } | |
4423 | ||
af6bdddf | 4424 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
4425 | |
4426 | static const reg_entry * | |
4427 | parse_register (reg_string, end_op) | |
4428 | char *reg_string; | |
4429 | char **end_op; | |
4430 | { | |
af6bdddf AM |
4431 | char *s = reg_string; |
4432 | char *p; | |
252b5132 RH |
4433 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
4434 | const reg_entry *r; | |
4435 | ||
4436 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
4437 | if (*s == REGISTER_PREFIX) | |
4438 | ++s; | |
4439 | ||
4440 | if (is_space_char (*s)) | |
4441 | ++s; | |
4442 | ||
4443 | p = reg_name_given; | |
af6bdddf | 4444 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
4445 | { |
4446 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
4447 | return (const reg_entry *) NULL; |
4448 | s++; | |
252b5132 RH |
4449 | } |
4450 | ||
6588847e DN |
4451 | /* For naked regs, make sure that we are not dealing with an identifier. |
4452 | This prevents confusing an identifier like `eax_var' with register | |
4453 | `eax'. */ | |
4454 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
4455 | return (const reg_entry *) NULL; | |
4456 | ||
af6bdddf | 4457 | *end_op = s; |
252b5132 RH |
4458 | |
4459 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
4460 | ||
5f47d35b | 4461 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 4462 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 4463 | { |
5f47d35b AM |
4464 | if (is_space_char (*s)) |
4465 | ++s; | |
4466 | if (*s == '(') | |
4467 | { | |
af6bdddf | 4468 | ++s; |
5f47d35b AM |
4469 | if (is_space_char (*s)) |
4470 | ++s; | |
4471 | if (*s >= '0' && *s <= '7') | |
4472 | { | |
4473 | r = &i386_float_regtab[*s - '0']; | |
af6bdddf | 4474 | ++s; |
5f47d35b AM |
4475 | if (is_space_char (*s)) |
4476 | ++s; | |
4477 | if (*s == ')') | |
4478 | { | |
4479 | *end_op = s + 1; | |
4480 | return r; | |
4481 | } | |
5f47d35b | 4482 | } |
47926f60 | 4483 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
4484 | return (const reg_entry *) NULL; |
4485 | } | |
4486 | } | |
4487 | ||
252b5132 RH |
4488 | return r; |
4489 | } | |
4490 | \f | |
4cc782b5 | 4491 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
65172ab8 | 4492 | const char *md_shortopts = "kVQ:sq"; |
252b5132 | 4493 | #else |
65172ab8 | 4494 | const char *md_shortopts = "q"; |
252b5132 | 4495 | #endif |
6e0b89ee | 4496 | |
252b5132 | 4497 | struct option md_longopts[] = { |
3e73aa7c JH |
4498 | #define OPTION_32 (OPTION_MD_BASE + 0) |
4499 | {"32", no_argument, NULL, OPTION_32}, | |
6e0b89ee | 4500 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3e73aa7c JH |
4501 | #define OPTION_64 (OPTION_MD_BASE + 1) |
4502 | {"64", no_argument, NULL, OPTION_64}, | |
6e0b89ee | 4503 | #endif |
252b5132 RH |
4504 | {NULL, no_argument, NULL, 0} |
4505 | }; | |
4506 | size_t md_longopts_size = sizeof (md_longopts); | |
4507 | ||
4508 | int | |
4509 | md_parse_option (c, arg) | |
4510 | int c; | |
ab9da554 | 4511 | char *arg ATTRIBUTE_UNUSED; |
252b5132 RH |
4512 | { |
4513 | switch (c) | |
4514 | { | |
a38cf1db AM |
4515 | case 'q': |
4516 | quiet_warnings = 1; | |
252b5132 RH |
4517 | break; |
4518 | ||
4519 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
4520 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
4521 | should be emitted or not. FIXME: Not implemented. */ | |
4522 | case 'Q': | |
252b5132 RH |
4523 | break; |
4524 | ||
4525 | /* -V: SVR4 argument to print version ID. */ | |
4526 | case 'V': | |
4527 | print_version_id (); | |
4528 | break; | |
4529 | ||
a38cf1db AM |
4530 | /* -k: Ignore for FreeBSD compatibility. */ |
4531 | case 'k': | |
252b5132 | 4532 | break; |
4cc782b5 ILT |
4533 | |
4534 | case 's': | |
4535 | /* -s: On i386 Solaris, this tells the native assembler to use | |
4536 | .stab instead of .stab.excl. We always use .stab anyhow. */ | |
4537 | break; | |
6e0b89ee | 4538 | |
3e73aa7c JH |
4539 | case OPTION_64: |
4540 | { | |
4541 | const char **list, **l; | |
4542 | ||
3e73aa7c JH |
4543 | list = bfd_target_list (); |
4544 | for (l = list; *l != NULL; l++) | |
6e0b89ee AM |
4545 | if (strcmp (*l, "elf64-x86-64") == 0) |
4546 | { | |
4547 | default_arch = "x86_64"; | |
4548 | break; | |
4549 | } | |
3e73aa7c | 4550 | if (*l == NULL) |
6e0b89ee | 4551 | as_fatal (_("No compiled in support for x86_64")); |
3e73aa7c JH |
4552 | free (list); |
4553 | } | |
4554 | break; | |
4555 | #endif | |
252b5132 | 4556 | |
6e0b89ee AM |
4557 | case OPTION_32: |
4558 | default_arch = "i386"; | |
4559 | break; | |
4560 | ||
252b5132 RH |
4561 | default: |
4562 | return 0; | |
4563 | } | |
4564 | return 1; | |
4565 | } | |
4566 | ||
4567 | void | |
4568 | md_show_usage (stream) | |
4569 | FILE *stream; | |
4570 | { | |
4cc782b5 ILT |
4571 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
4572 | fprintf (stream, _("\ | |
a38cf1db AM |
4573 | -Q ignored\n\ |
4574 | -V print assembler version number\n\ | |
4575 | -k ignored\n\ | |
4576 | -q quieten some warnings\n\ | |
4577 | -s ignored\n")); | |
4578 | #else | |
4579 | fprintf (stream, _("\ | |
4580 | -q quieten some warnings\n")); | |
4cc782b5 | 4581 | #endif |
252b5132 RH |
4582 | } |
4583 | ||
4584 | #ifdef BFD_ASSEMBLER | |
3e73aa7c JH |
4585 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
4586 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) | |
252b5132 RH |
4587 | |
4588 | /* Pick the target format to use. */ | |
4589 | ||
47926f60 | 4590 | const char * |
252b5132 RH |
4591 | i386_target_format () |
4592 | { | |
3e73aa7c JH |
4593 | if (!strcmp (default_arch, "x86_64")) |
4594 | set_code_flag (CODE_64BIT); | |
4595 | else if (!strcmp (default_arch, "i386")) | |
4596 | set_code_flag (CODE_32BIT); | |
4597 | else | |
4598 | as_fatal (_("Unknown architecture")); | |
252b5132 RH |
4599 | switch (OUTPUT_FLAVOR) |
4600 | { | |
4c63da97 AM |
4601 | #ifdef OBJ_MAYBE_AOUT |
4602 | case bfd_target_aout_flavour: | |
47926f60 | 4603 | return AOUT_TARGET_FORMAT; |
4c63da97 AM |
4604 | #endif |
4605 | #ifdef OBJ_MAYBE_COFF | |
252b5132 RH |
4606 | case bfd_target_coff_flavour: |
4607 | return "coff-i386"; | |
4c63da97 | 4608 | #endif |
3e73aa7c | 4609 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 4610 | case bfd_target_elf_flavour: |
3e73aa7c | 4611 | { |
e5cb08ac KH |
4612 | if (flag_code == CODE_64BIT) |
4613 | use_rela_relocations = 1; | |
4614 | return flag_code == CODE_64BIT ? "elf64-x86-64" : "elf32-i386"; | |
3e73aa7c | 4615 | } |
4c63da97 | 4616 | #endif |
252b5132 RH |
4617 | default: |
4618 | abort (); | |
4619 | return NULL; | |
4620 | } | |
4621 | } | |
4622 | ||
47926f60 KH |
4623 | #endif /* OBJ_MAYBE_ more than one */ |
4624 | #endif /* BFD_ASSEMBLER */ | |
252b5132 | 4625 | \f |
252b5132 RH |
4626 | symbolS * |
4627 | md_undefined_symbol (name) | |
4628 | char *name; | |
4629 | { | |
18dc2407 ILT |
4630 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
4631 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
4632 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
4633 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
4634 | { |
4635 | if (!GOT_symbol) | |
4636 | { | |
4637 | if (symbol_find (name)) | |
4638 | as_bad (_("GOT already in symbol table")); | |
4639 | GOT_symbol = symbol_new (name, undefined_section, | |
4640 | (valueT) 0, &zero_address_frag); | |
4641 | }; | |
4642 | return GOT_symbol; | |
4643 | } | |
252b5132 RH |
4644 | return 0; |
4645 | } | |
4646 | ||
4647 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 4648 | |
252b5132 RH |
4649 | valueT |
4650 | md_section_align (segment, size) | |
ab9da554 | 4651 | segT segment ATTRIBUTE_UNUSED; |
252b5132 RH |
4652 | valueT size; |
4653 | { | |
252b5132 | 4654 | #ifdef BFD_ASSEMBLER |
4c63da97 AM |
4655 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
4656 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
4657 | { | |
4658 | /* For a.out, force the section size to be aligned. If we don't do | |
4659 | this, BFD will align it for us, but it will not write out the | |
4660 | final bytes of the section. This may be a bug in BFD, but it is | |
4661 | easier to fix it here since that is how the other a.out targets | |
4662 | work. */ | |
4663 | int align; | |
4664 | ||
4665 | align = bfd_get_section_alignment (stdoutput, segment); | |
4666 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
4667 | } | |
252b5132 RH |
4668 | #endif |
4669 | #endif | |
4670 | ||
4671 | return size; | |
4672 | } | |
4673 | ||
4674 | /* On the i386, PC-relative offsets are relative to the start of the | |
4675 | next instruction. That is, the address of the offset, plus its | |
4676 | size, since the offset is always the last part of the insn. */ | |
4677 | ||
4678 | long | |
4679 | md_pcrel_from (fixP) | |
4680 | fixS *fixP; | |
4681 | { | |
4682 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
4683 | } | |
4684 | ||
4685 | #ifndef I386COFF | |
4686 | ||
4687 | static void | |
4688 | s_bss (ignore) | |
ab9da554 | 4689 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
4690 | { |
4691 | register int temp; | |
4692 | ||
4693 | temp = get_absolute_expression (); | |
4694 | subseg_set (bss_section, (subsegT) temp); | |
4695 | demand_empty_rest_of_line (); | |
4696 | } | |
4697 | ||
4698 | #endif | |
4699 | ||
252b5132 RH |
4700 | #ifdef BFD_ASSEMBLER |
4701 | ||
4702 | void | |
4703 | i386_validate_fix (fixp) | |
4704 | fixS *fixp; | |
4705 | { | |
4706 | if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) | |
4707 | { | |
3e73aa7c | 4708 | /* GOTOFF relocation are nonsense in 64bit mode. */ |
23df1078 JH |
4709 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
4710 | { | |
4711 | if (flag_code != CODE_64BIT) | |
4712 | abort (); | |
4713 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
4714 | } | |
4715 | else | |
4716 | { | |
4717 | if (flag_code == CODE_64BIT) | |
4718 | abort (); | |
4719 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
4720 | } | |
252b5132 RH |
4721 | fixp->fx_subsy = 0; |
4722 | } | |
4723 | } | |
4724 | ||
252b5132 RH |
4725 | arelent * |
4726 | tc_gen_reloc (section, fixp) | |
ab9da554 | 4727 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
4728 | fixS *fixp; |
4729 | { | |
4730 | arelent *rel; | |
4731 | bfd_reloc_code_real_type code; | |
4732 | ||
4733 | switch (fixp->fx_r_type) | |
4734 | { | |
3e73aa7c JH |
4735 | case BFD_RELOC_X86_64_PLT32: |
4736 | case BFD_RELOC_X86_64_GOT32: | |
4737 | case BFD_RELOC_X86_64_GOTPCREL: | |
252b5132 RH |
4738 | case BFD_RELOC_386_PLT32: |
4739 | case BFD_RELOC_386_GOT32: | |
4740 | case BFD_RELOC_386_GOTOFF: | |
4741 | case BFD_RELOC_386_GOTPC: | |
3e73aa7c | 4742 | case BFD_RELOC_X86_64_32S: |
252b5132 RH |
4743 | case BFD_RELOC_RVA: |
4744 | case BFD_RELOC_VTABLE_ENTRY: | |
4745 | case BFD_RELOC_VTABLE_INHERIT: | |
4746 | code = fixp->fx_r_type; | |
4747 | break; | |
4748 | default: | |
93382f6d | 4749 | if (fixp->fx_pcrel) |
252b5132 | 4750 | { |
93382f6d AM |
4751 | switch (fixp->fx_size) |
4752 | { | |
4753 | default: | |
d0b47220 | 4754 | as_bad (_("can not do %d byte pc-relative relocation"), |
93382f6d AM |
4755 | fixp->fx_size); |
4756 | code = BFD_RELOC_32_PCREL; | |
4757 | break; | |
4758 | case 1: code = BFD_RELOC_8_PCREL; break; | |
4759 | case 2: code = BFD_RELOC_16_PCREL; break; | |
4760 | case 4: code = BFD_RELOC_32_PCREL; break; | |
4761 | } | |
4762 | } | |
4763 | else | |
4764 | { | |
4765 | switch (fixp->fx_size) | |
4766 | { | |
4767 | default: | |
d0b47220 | 4768 | as_bad (_("can not do %d byte relocation"), fixp->fx_size); |
93382f6d AM |
4769 | code = BFD_RELOC_32; |
4770 | break; | |
4771 | case 1: code = BFD_RELOC_8; break; | |
4772 | case 2: code = BFD_RELOC_16; break; | |
4773 | case 4: code = BFD_RELOC_32; break; | |
3e73aa7c | 4774 | case 8: code = BFD_RELOC_64; break; |
93382f6d | 4775 | } |
252b5132 RH |
4776 | } |
4777 | break; | |
4778 | } | |
252b5132 RH |
4779 | |
4780 | if (code == BFD_RELOC_32 | |
4781 | && GOT_symbol | |
4782 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c JH |
4783 | { |
4784 | /* We don't support GOTPC on 64bit targets. */ | |
4785 | if (flag_code == CODE_64BIT) | |
bfb32b52 | 4786 | abort (); |
3e73aa7c JH |
4787 | code = BFD_RELOC_386_GOTPC; |
4788 | } | |
252b5132 RH |
4789 | |
4790 | rel = (arelent *) xmalloc (sizeof (arelent)); | |
49309057 ILT |
4791 | rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
4792 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
4793 | |
4794 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
3e73aa7c JH |
4795 | if (!use_rela_relocations) |
4796 | { | |
4797 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
4798 | vtable entry to be used in the relocation's section offset. */ | |
4799 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
4800 | rel->address = fixp->fx_offset; | |
252b5132 | 4801 | |
3e73aa7c JH |
4802 | if (fixp->fx_pcrel) |
4803 | rel->addend = fixp->fx_addnumber; | |
4804 | else | |
4805 | rel->addend = 0; | |
4806 | } | |
4807 | /* Use the rela in 64bit mode. */ | |
252b5132 | 4808 | else |
3e73aa7c JH |
4809 | { |
4810 | rel->addend = fixp->fx_offset; | |
3e73aa7c JH |
4811 | if (fixp->fx_pcrel) |
4812 | rel->addend -= fixp->fx_size; | |
4813 | } | |
4814 | ||
252b5132 RH |
4815 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
4816 | if (rel->howto == NULL) | |
4817 | { | |
4818 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 4819 | _("cannot represent relocation type %s"), |
252b5132 RH |
4820 | bfd_get_reloc_code_name (code)); |
4821 | /* Set howto to a garbage value so that we can keep going. */ | |
4822 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
4823 | assert (rel->howto != NULL); | |
4824 | } | |
4825 | ||
4826 | return rel; | |
4827 | } | |
4828 | ||
47926f60 | 4829 | #else /* ! BFD_ASSEMBLER */ |
252b5132 RH |
4830 | |
4831 | #if (defined(OBJ_AOUT) | defined(OBJ_BOUT)) | |
4832 | void | |
4833 | tc_aout_fix_to_chars (where, fixP, segment_address_in_file) | |
4834 | char *where; | |
4835 | fixS *fixP; | |
4836 | relax_addressT segment_address_in_file; | |
4837 | { | |
47926f60 KH |
4838 | /* In: length of relocation (or of address) in chars: 1, 2 or 4. |
4839 | Out: GNU LD relocation length code: 0, 1, or 2. */ | |
252b5132 | 4840 | |
47926f60 | 4841 | static const unsigned char nbytes_r_length[] = { 42, 0, 1, 42, 2 }; |
252b5132 RH |
4842 | long r_symbolnum; |
4843 | ||
4844 | know (fixP->fx_addsy != NULL); | |
4845 | ||
4846 | md_number_to_chars (where, | |
4847 | (valueT) (fixP->fx_frag->fr_address | |
4848 | + fixP->fx_where - segment_address_in_file), | |
4849 | 4); | |
4850 | ||
4851 | r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy) | |
4852 | ? S_GET_TYPE (fixP->fx_addsy) | |
4853 | : fixP->fx_addsy->sy_number); | |
4854 | ||
4855 | where[6] = (r_symbolnum >> 16) & 0x0ff; | |
4856 | where[5] = (r_symbolnum >> 8) & 0x0ff; | |
4857 | where[4] = r_symbolnum & 0x0ff; | |
4858 | where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08) | |
4859 | | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06) | |
4860 | | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f)); | |
4861 | } | |
4862 | ||
47926f60 | 4863 | #endif /* OBJ_AOUT or OBJ_BOUT. */ |
252b5132 RH |
4864 | |
4865 | #if defined (I386COFF) | |
4866 | ||
4867 | short | |
4868 | tc_coff_fix2rtype (fixP) | |
4869 | fixS *fixP; | |
4870 | { | |
4871 | if (fixP->fx_r_type == R_IMAGEBASE) | |
4872 | return R_IMAGEBASE; | |
4873 | ||
4874 | return (fixP->fx_pcrel ? | |
4875 | (fixP->fx_size == 1 ? R_PCRBYTE : | |
4876 | fixP->fx_size == 2 ? R_PCRWORD : | |
4877 | R_PCRLONG) : | |
4878 | (fixP->fx_size == 1 ? R_RELBYTE : | |
4879 | fixP->fx_size == 2 ? R_RELWORD : | |
4880 | R_DIR32)); | |
4881 | } | |
4882 | ||
4883 | int | |
4884 | tc_coff_sizemachdep (frag) | |
4885 | fragS *frag; | |
4886 | { | |
4887 | if (frag->fr_next) | |
4888 | return (frag->fr_next->fr_address - frag->fr_address); | |
4889 | else | |
4890 | return 0; | |
4891 | } | |
4892 | ||
47926f60 | 4893 | #endif /* I386COFF */ |
252b5132 | 4894 | |
47926f60 | 4895 | #endif /* ! BFD_ASSEMBLER */ |
64a0c779 DN |
4896 | \f |
4897 | /* Parse operands using Intel syntax. This implements a recursive descent | |
4898 | parser based on the BNF grammar published in Appendix B of the MASM 6.1 | |
4899 | Programmer's Guide. | |
4900 | ||
4901 | FIXME: We do not recognize the full operand grammar defined in the MASM | |
4902 | documentation. In particular, all the structure/union and | |
4903 | high-level macro operands are missing. | |
4904 | ||
4905 | Uppercase words are terminals, lower case words are non-terminals. | |
4906 | Objects surrounded by double brackets '[[' ']]' are optional. Vertical | |
4907 | bars '|' denote choices. Most grammar productions are implemented in | |
4908 | functions called 'intel_<production>'. | |
4909 | ||
4910 | Initial production is 'expr'. | |
4911 | ||
64a0c779 DN |
4912 | addOp + | - |
4913 | ||
4914 | alpha [a-zA-Z] | |
4915 | ||
4916 | byteRegister AL | AH | BL | BH | CL | CH | DL | DH | |
4917 | ||
4918 | constant digits [[ radixOverride ]] | |
4919 | ||
4920 | dataType BYTE | WORD | DWORD | QWORD | XWORD | |
4921 | ||
4922 | digits decdigit | |
b77a7acd AJ |
4923 | | digits decdigit |
4924 | | digits hexdigit | |
64a0c779 DN |
4925 | |
4926 | decdigit [0-9] | |
4927 | ||
4928 | e05 e05 addOp e06 | |
b77a7acd | 4929 | | e06 |
64a0c779 DN |
4930 | |
4931 | e06 e06 mulOp e09 | |
b77a7acd | 4932 | | e09 |
64a0c779 DN |
4933 | |
4934 | e09 OFFSET e10 | |
4935 | | e09 PTR e10 | |
4936 | | e09 : e10 | |
4937 | | e10 | |
4938 | ||
4939 | e10 e10 [ expr ] | |
b77a7acd | 4940 | | e11 |
64a0c779 DN |
4941 | |
4942 | e11 ( expr ) | |
b77a7acd | 4943 | | [ expr ] |
64a0c779 DN |
4944 | | constant |
4945 | | dataType | |
4946 | | id | |
4947 | | $ | |
4948 | | register | |
4949 | ||
4950 | => expr SHORT e05 | |
b77a7acd | 4951 | | e05 |
64a0c779 DN |
4952 | |
4953 | gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX | |
b77a7acd | 4954 | | BP | EBP | SP | ESP | DI | EDI | SI | ESI |
64a0c779 DN |
4955 | |
4956 | hexdigit a | b | c | d | e | f | |
b77a7acd | 4957 | | A | B | C | D | E | F |
64a0c779 DN |
4958 | |
4959 | id alpha | |
b77a7acd | 4960 | | id alpha |
64a0c779 DN |
4961 | | id decdigit |
4962 | ||
4963 | mulOp * | / | MOD | |
4964 | ||
4965 | quote " | ' | |
4966 | ||
4967 | register specialRegister | |
b77a7acd | 4968 | | gpRegister |
64a0c779 DN |
4969 | | byteRegister |
4970 | ||
4971 | segmentRegister CS | DS | ES | FS | GS | SS | |
4972 | ||
4973 | specialRegister CR0 | CR2 | CR3 | |
b77a7acd | 4974 | | DR0 | DR1 | DR2 | DR3 | DR6 | DR7 |
64a0c779 DN |
4975 | | TR3 | TR4 | TR5 | TR6 | TR7 |
4976 | ||
64a0c779 DN |
4977 | We simplify the grammar in obvious places (e.g., register parsing is |
4978 | done by calling parse_register) and eliminate immediate left recursion | |
4979 | to implement a recursive-descent parser. | |
4980 | ||
4981 | expr SHORT e05 | |
b77a7acd | 4982 | | e05 |
64a0c779 DN |
4983 | |
4984 | e05 e06 e05' | |
4985 | ||
4986 | e05' addOp e06 e05' | |
b77a7acd | 4987 | | Empty |
64a0c779 DN |
4988 | |
4989 | e06 e09 e06' | |
4990 | ||
4991 | e06' mulOp e09 e06' | |
b77a7acd | 4992 | | Empty |
64a0c779 DN |
4993 | |
4994 | e09 OFFSET e10 e09' | |
b77a7acd | 4995 | | e10 e09' |
64a0c779 DN |
4996 | |
4997 | e09' PTR e10 e09' | |
b77a7acd | 4998 | | : e10 e09' |
64a0c779 DN |
4999 | | Empty |
5000 | ||
5001 | e10 e11 e10' | |
5002 | ||
5003 | e10' [ expr ] e10' | |
b77a7acd | 5004 | | Empty |
64a0c779 DN |
5005 | |
5006 | e11 ( expr ) | |
b77a7acd | 5007 | | [ expr ] |
64a0c779 DN |
5008 | | BYTE |
5009 | | WORD | |
5010 | | DWORD | |
5011 | | QWORD | |
5012 | | XWORD | |
5013 | | . | |
5014 | | $ | |
5015 | | register | |
5016 | | id | |
5017 | | constant */ | |
5018 | ||
5019 | /* Parsing structure for the intel syntax parser. Used to implement the | |
5020 | semantic actions for the operand grammar. */ | |
5021 | struct intel_parser_s | |
5022 | { | |
5023 | char *op_string; /* The string being parsed. */ | |
5024 | int got_a_float; /* Whether the operand is a float. */ | |
4a1805b1 | 5025 | int op_modifier; /* Operand modifier. */ |
64a0c779 DN |
5026 | int is_mem; /* 1 if operand is memory reference. */ |
5027 | const reg_entry *reg; /* Last register reference found. */ | |
5028 | char *disp; /* Displacement string being built. */ | |
5029 | }; | |
5030 | ||
5031 | static struct intel_parser_s intel_parser; | |
5032 | ||
5033 | /* Token structure for parsing intel syntax. */ | |
5034 | struct intel_token | |
5035 | { | |
5036 | int code; /* Token code. */ | |
5037 | const reg_entry *reg; /* Register entry for register tokens. */ | |
5038 | char *str; /* String representation. */ | |
5039 | }; | |
5040 | ||
5041 | static struct intel_token cur_token, prev_token; | |
5042 | ||
50705ef4 AM |
5043 | /* Token codes for the intel parser. Since T_SHORT is already used |
5044 | by COFF, undefine it first to prevent a warning. */ | |
64a0c779 DN |
5045 | #define T_NIL -1 |
5046 | #define T_CONST 1 | |
5047 | #define T_REG 2 | |
5048 | #define T_BYTE 3 | |
5049 | #define T_WORD 4 | |
5050 | #define T_DWORD 5 | |
5051 | #define T_QWORD 6 | |
5052 | #define T_XWORD 7 | |
50705ef4 | 5053 | #undef T_SHORT |
64a0c779 DN |
5054 | #define T_SHORT 8 |
5055 | #define T_OFFSET 9 | |
5056 | #define T_PTR 10 | |
5057 | #define T_ID 11 | |
5058 | ||
5059 | /* Prototypes for intel parser functions. */ | |
5060 | static int intel_match_token PARAMS ((int code)); | |
cce0cbdc DN |
5061 | static void intel_get_token PARAMS ((void)); |
5062 | static void intel_putback_token PARAMS ((void)); | |
5063 | static int intel_expr PARAMS ((void)); | |
5064 | static int intel_e05 PARAMS ((void)); | |
5065 | static int intel_e05_1 PARAMS ((void)); | |
5066 | static int intel_e06 PARAMS ((void)); | |
5067 | static int intel_e06_1 PARAMS ((void)); | |
5068 | static int intel_e09 PARAMS ((void)); | |
5069 | static int intel_e09_1 PARAMS ((void)); | |
5070 | static int intel_e10 PARAMS ((void)); | |
5071 | static int intel_e10_1 PARAMS ((void)); | |
5072 | static int intel_e11 PARAMS ((void)); | |
64a0c779 | 5073 | |
64a0c779 DN |
5074 | static int |
5075 | i386_intel_operand (operand_string, got_a_float) | |
5076 | char *operand_string; | |
5077 | int got_a_float; | |
5078 | { | |
5079 | int ret; | |
5080 | char *p; | |
5081 | ||
5082 | /* Initialize token holders. */ | |
5083 | cur_token.code = prev_token.code = T_NIL; | |
5084 | cur_token.reg = prev_token.reg = NULL; | |
5085 | cur_token.str = prev_token.str = NULL; | |
5086 | ||
5087 | /* Initialize parser structure. */ | |
e5cb08ac | 5088 | p = intel_parser.op_string = (char *) malloc (strlen (operand_string) + 1); |
64a0c779 DN |
5089 | if (p == NULL) |
5090 | abort (); | |
5091 | strcpy (intel_parser.op_string, operand_string); | |
5092 | intel_parser.got_a_float = got_a_float; | |
5093 | intel_parser.op_modifier = -1; | |
5094 | intel_parser.is_mem = 0; | |
5095 | intel_parser.reg = NULL; | |
e5cb08ac | 5096 | intel_parser.disp = (char *) malloc (strlen (operand_string) + 1); |
64a0c779 DN |
5097 | if (intel_parser.disp == NULL) |
5098 | abort (); | |
5099 | intel_parser.disp[0] = '\0'; | |
5100 | ||
5101 | /* Read the first token and start the parser. */ | |
5102 | intel_get_token (); | |
5103 | ret = intel_expr (); | |
5104 | ||
5105 | if (ret) | |
5106 | { | |
5107 | /* If we found a memory reference, hand it over to i386_displacement | |
5108 | to fill in the rest of the operand fields. */ | |
5109 | if (intel_parser.is_mem) | |
5110 | { | |
5111 | if ((i.mem_operands == 1 | |
5112 | && (current_templates->start->opcode_modifier & IsString) == 0) | |
5113 | || i.mem_operands == 2) | |
5114 | { | |
5115 | as_bad (_("too many memory references for '%s'"), | |
5116 | current_templates->start->name); | |
5117 | ret = 0; | |
5118 | } | |
5119 | else | |
5120 | { | |
5121 | char *s = intel_parser.disp; | |
5122 | i.mem_operands++; | |
5123 | ||
5124 | /* Add the displacement expression. */ | |
5125 | if (*s != '\0') | |
5126 | ret = i386_displacement (s, s + strlen (s)) | |
5127 | && i386_index_check (s); | |
5128 | } | |
5129 | } | |
5130 | ||
5131 | /* Constant and OFFSET expressions are handled by i386_immediate. */ | |
5132 | else if (intel_parser.op_modifier == OFFSET_FLAT | |
5133 | || intel_parser.reg == NULL) | |
5134 | ret = i386_immediate (intel_parser.disp); | |
5135 | } | |
5136 | ||
5137 | free (p); | |
5138 | free (intel_parser.disp); | |
5139 | ||
5140 | return ret; | |
5141 | } | |
5142 | ||
64a0c779 | 5143 | /* expr SHORT e05 |
b77a7acd | 5144 | | e05 */ |
64a0c779 DN |
5145 | static int |
5146 | intel_expr () | |
5147 | { | |
5148 | /* expr SHORT e05 */ | |
5149 | if (cur_token.code == T_SHORT) | |
5150 | { | |
5151 | intel_parser.op_modifier = SHORT; | |
5152 | intel_match_token (T_SHORT); | |
5153 | ||
5154 | return (intel_e05 ()); | |
5155 | } | |
5156 | ||
5157 | /* expr e05 */ | |
5158 | else | |
5159 | return intel_e05 (); | |
5160 | } | |
5161 | ||
64a0c779 DN |
5162 | /* e05 e06 e05' |
5163 | ||
4a1805b1 | 5164 | e05' addOp e06 e05' |
64a0c779 DN |
5165 | | Empty */ |
5166 | static int | |
5167 | intel_e05 () | |
5168 | { | |
5169 | return (intel_e06 () && intel_e05_1 ()); | |
5170 | } | |
5171 | ||
5172 | static int | |
5173 | intel_e05_1 () | |
5174 | { | |
5175 | /* e05' addOp e06 e05' */ | |
5176 | if (cur_token.code == '+' || cur_token.code == '-') | |
5177 | { | |
5178 | strcat (intel_parser.disp, cur_token.str); | |
5179 | intel_match_token (cur_token.code); | |
5180 | ||
5181 | return (intel_e06 () && intel_e05_1 ()); | |
5182 | } | |
5183 | ||
5184 | /* e05' Empty */ | |
5185 | else | |
5186 | return 1; | |
4a1805b1 | 5187 | } |
64a0c779 DN |
5188 | |
5189 | /* e06 e09 e06' | |
5190 | ||
5191 | e06' mulOp e09 e06' | |
b77a7acd | 5192 | | Empty */ |
64a0c779 DN |
5193 | static int |
5194 | intel_e06 () | |
5195 | { | |
5196 | return (intel_e09 () && intel_e06_1 ()); | |
5197 | } | |
5198 | ||
5199 | static int | |
5200 | intel_e06_1 () | |
5201 | { | |
5202 | /* e06' mulOp e09 e06' */ | |
5203 | if (cur_token.code == '*' || cur_token.code == '/') | |
5204 | { | |
5205 | strcat (intel_parser.disp, cur_token.str); | |
5206 | intel_match_token (cur_token.code); | |
5207 | ||
5208 | return (intel_e09 () && intel_e06_1 ()); | |
5209 | } | |
4a1805b1 | 5210 | |
64a0c779 | 5211 | /* e06' Empty */ |
4a1805b1 | 5212 | else |
64a0c779 DN |
5213 | return 1; |
5214 | } | |
5215 | ||
64a0c779 | 5216 | /* e09 OFFSET e10 e09' |
b77a7acd | 5217 | | e10 e09' |
64a0c779 DN |
5218 | |
5219 | e09' PTR e10 e09' | |
b77a7acd | 5220 | | : e10 e09' |
64a0c779 DN |
5221 | | Empty */ |
5222 | static int | |
5223 | intel_e09 () | |
5224 | { | |
5225 | /* e09 OFFSET e10 e09' */ | |
5226 | if (cur_token.code == T_OFFSET) | |
5227 | { | |
5228 | intel_parser.is_mem = 0; | |
5229 | intel_parser.op_modifier = OFFSET_FLAT; | |
5230 | intel_match_token (T_OFFSET); | |
5231 | ||
5232 | return (intel_e10 () && intel_e09_1 ()); | |
5233 | } | |
5234 | ||
5235 | /* e09 e10 e09' */ | |
5236 | else | |
5237 | return (intel_e10 () && intel_e09_1 ()); | |
5238 | } | |
5239 | ||
5240 | static int | |
5241 | intel_e09_1 () | |
5242 | { | |
5243 | /* e09' PTR e10 e09' */ | |
5244 | if (cur_token.code == T_PTR) | |
5245 | { | |
5246 | if (prev_token.code == T_BYTE) | |
5247 | i.suffix = BYTE_MNEM_SUFFIX; | |
5248 | ||
5249 | else if (prev_token.code == T_WORD) | |
5250 | { | |
5251 | if (intel_parser.got_a_float == 2) /* "fi..." */ | |
5252 | i.suffix = SHORT_MNEM_SUFFIX; | |
5253 | else | |
5254 | i.suffix = WORD_MNEM_SUFFIX; | |
5255 | } | |
5256 | ||
5257 | else if (prev_token.code == T_DWORD) | |
5258 | { | |
5259 | if (intel_parser.got_a_float == 1) /* "f..." */ | |
5260 | i.suffix = SHORT_MNEM_SUFFIX; | |
5261 | else | |
5262 | i.suffix = LONG_MNEM_SUFFIX; | |
5263 | } | |
5264 | ||
5265 | else if (prev_token.code == T_QWORD) | |
f16b83df JH |
5266 | { |
5267 | if (intel_parser.got_a_float == 1) /* "f..." */ | |
5268 | i.suffix = LONG_MNEM_SUFFIX; | |
5269 | else | |
3e73aa7c | 5270 | i.suffix = QWORD_MNEM_SUFFIX; |
f16b83df | 5271 | } |
64a0c779 DN |
5272 | |
5273 | else if (prev_token.code == T_XWORD) | |
5274 | i.suffix = LONG_DOUBLE_MNEM_SUFFIX; | |
5275 | ||
5276 | else | |
5277 | { | |
5278 | as_bad (_("Unknown operand modifier `%s'\n"), prev_token.str); | |
5279 | return 0; | |
5280 | } | |
5281 | ||
5282 | intel_match_token (T_PTR); | |
5283 | ||
5284 | return (intel_e10 () && intel_e09_1 ()); | |
5285 | } | |
5286 | ||
5287 | /* e09 : e10 e09' */ | |
5288 | else if (cur_token.code == ':') | |
5289 | { | |
21d6c4af DN |
5290 | /* Mark as a memory operand only if it's not already known to be an |
5291 | offset expression. */ | |
5292 | if (intel_parser.op_modifier != OFFSET_FLAT) | |
5293 | intel_parser.is_mem = 1; | |
64a0c779 DN |
5294 | |
5295 | return (intel_match_token (':') && intel_e10 () && intel_e09_1 ()); | |
5296 | } | |
5297 | ||
5298 | /* e09' Empty */ | |
5299 | else | |
5300 | return 1; | |
5301 | } | |
5302 | ||
5303 | /* e10 e11 e10' | |
5304 | ||
5305 | e10' [ expr ] e10' | |
b77a7acd | 5306 | | Empty */ |
64a0c779 DN |
5307 | static int |
5308 | intel_e10 () | |
5309 | { | |
5310 | return (intel_e11 () && intel_e10_1 ()); | |
5311 | } | |
5312 | ||
5313 | static int | |
5314 | intel_e10_1 () | |
5315 | { | |
5316 | /* e10' [ expr ] e10' */ | |
5317 | if (cur_token.code == '[') | |
5318 | { | |
5319 | intel_match_token ('['); | |
21d6c4af DN |
5320 | |
5321 | /* Mark as a memory operand only if it's not already known to be an | |
5322 | offset expression. If it's an offset expression, we need to keep | |
5323 | the brace in. */ | |
5324 | if (intel_parser.op_modifier != OFFSET_FLAT) | |
5325 | intel_parser.is_mem = 1; | |
5326 | else | |
5327 | strcat (intel_parser.disp, "["); | |
4a1805b1 | 5328 | |
64a0c779 | 5329 | /* Add a '+' to the displacement string if necessary. */ |
21d6c4af DN |
5330 | if (*intel_parser.disp != '\0' |
5331 | && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+') | |
64a0c779 DN |
5332 | strcat (intel_parser.disp, "+"); |
5333 | ||
21d6c4af DN |
5334 | if (intel_expr () && intel_match_token (']')) |
5335 | { | |
5336 | /* Preserve brackets when the operand is an offset expression. */ | |
5337 | if (intel_parser.op_modifier == OFFSET_FLAT) | |
5338 | strcat (intel_parser.disp, "]"); | |
5339 | ||
5340 | return intel_e10_1 (); | |
5341 | } | |
5342 | else | |
5343 | return 0; | |
64a0c779 DN |
5344 | } |
5345 | ||
5346 | /* e10' Empty */ | |
5347 | else | |
5348 | return 1; | |
5349 | } | |
5350 | ||
64a0c779 | 5351 | /* e11 ( expr ) |
b77a7acd | 5352 | | [ expr ] |
64a0c779 DN |
5353 | | BYTE |
5354 | | WORD | |
5355 | | DWORD | |
5356 | | QWORD | |
5357 | | XWORD | |
4a1805b1 | 5358 | | $ |
64a0c779 DN |
5359 | | . |
5360 | | register | |
5361 | | id | |
5362 | | constant */ | |
5363 | static int | |
5364 | intel_e11 () | |
5365 | { | |
5366 | /* e11 ( expr ) */ | |
5367 | if (cur_token.code == '(') | |
5368 | { | |
5369 | intel_match_token ('('); | |
5370 | strcat (intel_parser.disp, "("); | |
5371 | ||
5372 | if (intel_expr () && intel_match_token (')')) | |
e5cb08ac KH |
5373 | { |
5374 | strcat (intel_parser.disp, ")"); | |
5375 | return 1; | |
5376 | } | |
64a0c779 DN |
5377 | else |
5378 | return 0; | |
5379 | } | |
5380 | ||
5381 | /* e11 [ expr ] */ | |
5382 | else if (cur_token.code == '[') | |
5383 | { | |
5384 | intel_match_token ('['); | |
21d6c4af DN |
5385 | |
5386 | /* Mark as a memory operand only if it's not already known to be an | |
5387 | offset expression. If it's an offset expression, we need to keep | |
5388 | the brace in. */ | |
5389 | if (intel_parser.op_modifier != OFFSET_FLAT) | |
5390 | intel_parser.is_mem = 1; | |
5391 | else | |
5392 | strcat (intel_parser.disp, "["); | |
4a1805b1 | 5393 | |
64a0c779 DN |
5394 | /* Operands for jump/call inside brackets denote absolute addresses. */ |
5395 | if (current_templates->start->opcode_modifier & Jump | |
5396 | || current_templates->start->opcode_modifier & JumpDword | |
5397 | || current_templates->start->opcode_modifier & JumpByte | |
5398 | || current_templates->start->opcode_modifier & JumpInterSegment) | |
5399 | i.types[this_operand] |= JumpAbsolute; | |
5400 | ||
5401 | /* Add a '+' to the displacement string if necessary. */ | |
21d6c4af DN |
5402 | if (*intel_parser.disp != '\0' |
5403 | && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+') | |
64a0c779 DN |
5404 | strcat (intel_parser.disp, "+"); |
5405 | ||
21d6c4af DN |
5406 | if (intel_expr () && intel_match_token (']')) |
5407 | { | |
5408 | /* Preserve brackets when the operand is an offset expression. */ | |
5409 | if (intel_parser.op_modifier == OFFSET_FLAT) | |
5410 | strcat (intel_parser.disp, "]"); | |
5411 | ||
5412 | return 1; | |
5413 | } | |
5414 | else | |
5415 | return 0; | |
64a0c779 DN |
5416 | } |
5417 | ||
4a1805b1 | 5418 | /* e11 BYTE |
64a0c779 DN |
5419 | | WORD |
5420 | | DWORD | |
5421 | | QWORD | |
5422 | | XWORD */ | |
5423 | else if (cur_token.code == T_BYTE | |
5424 | || cur_token.code == T_WORD | |
5425 | || cur_token.code == T_DWORD | |
5426 | || cur_token.code == T_QWORD | |
5427 | || cur_token.code == T_XWORD) | |
5428 | { | |
5429 | intel_match_token (cur_token.code); | |
5430 | ||
5431 | return 1; | |
5432 | } | |
5433 | ||
5434 | /* e11 $ | |
5435 | | . */ | |
5436 | else if (cur_token.code == '$' || cur_token.code == '.') | |
5437 | { | |
5438 | strcat (intel_parser.disp, cur_token.str); | |
5439 | intel_match_token (cur_token.code); | |
21d6c4af DN |
5440 | |
5441 | /* Mark as a memory operand only if it's not already known to be an | |
5442 | offset expression. */ | |
5443 | if (intel_parser.op_modifier != OFFSET_FLAT) | |
5444 | intel_parser.is_mem = 1; | |
64a0c779 DN |
5445 | |
5446 | return 1; | |
5447 | } | |
5448 | ||
5449 | /* e11 register */ | |
5450 | else if (cur_token.code == T_REG) | |
5451 | { | |
5452 | const reg_entry *reg = intel_parser.reg = cur_token.reg; | |
5453 | ||
5454 | intel_match_token (T_REG); | |
5455 | ||
5456 | /* Check for segment change. */ | |
5457 | if (cur_token.code == ':') | |
5458 | { | |
5459 | if (reg->reg_type & (SReg2 | SReg3)) | |
5460 | { | |
5461 | switch (reg->reg_num) | |
5462 | { | |
5463 | case 0: | |
5464 | i.seg[i.mem_operands] = &es; | |
5465 | break; | |
5466 | case 1: | |
5467 | i.seg[i.mem_operands] = &cs; | |
5468 | break; | |
5469 | case 2: | |
5470 | i.seg[i.mem_operands] = &ss; | |
5471 | break; | |
5472 | case 3: | |
5473 | i.seg[i.mem_operands] = &ds; | |
5474 | break; | |
5475 | case 4: | |
5476 | i.seg[i.mem_operands] = &fs; | |
5477 | break; | |
5478 | case 5: | |
5479 | i.seg[i.mem_operands] = &gs; | |
5480 | break; | |
5481 | } | |
5482 | } | |
5483 | else | |
5484 | { | |
5485 | as_bad (_("`%s' is not a valid segment register"), reg->reg_name); | |
5486 | return 0; | |
5487 | } | |
5488 | } | |
5489 | ||
5490 | /* Not a segment register. Check for register scaling. */ | |
5491 | else if (cur_token.code == '*') | |
5492 | { | |
5493 | if (!intel_parser.is_mem) | |
5494 | { | |
5495 | as_bad (_("Register scaling only allowed in memory operands.")); | |
5496 | return 0; | |
5497 | } | |
5498 | ||
4a1805b1 | 5499 | /* What follows must be a valid scale. */ |
64a0c779 DN |
5500 | if (intel_match_token ('*') |
5501 | && strchr ("01248", *cur_token.str)) | |
5502 | { | |
5503 | i.index_reg = reg; | |
5504 | i.types[this_operand] |= BaseIndex; | |
5505 | ||
5506 | /* Set the scale after setting the register (otherwise, | |
5507 | i386_scale will complain) */ | |
5508 | i386_scale (cur_token.str); | |
5509 | intel_match_token (T_CONST); | |
5510 | } | |
5511 | else | |
5512 | { | |
5513 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
5514 | cur_token.str); | |
5515 | return 0; | |
5516 | } | |
5517 | } | |
5518 | ||
5519 | /* No scaling. If this is a memory operand, the register is either a | |
5520 | base register (first occurrence) or an index register (second | |
5521 | occurrence). */ | |
5522 | else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3))) | |
5523 | { | |
5524 | if (i.base_reg && i.index_reg) | |
5525 | { | |
5526 | as_bad (_("Too many register references in memory operand.\n")); | |
5527 | return 0; | |
5528 | } | |
5529 | ||
5530 | if (i.base_reg == NULL) | |
5531 | i.base_reg = reg; | |
5532 | else | |
5533 | i.index_reg = reg; | |
5534 | ||
5535 | i.types[this_operand] |= BaseIndex; | |
5536 | } | |
5537 | ||
5538 | /* Offset modifier. Add the register to the displacement string to be | |
5539 | parsed as an immediate expression after we're done. */ | |
5540 | else if (intel_parser.op_modifier == OFFSET_FLAT) | |
5541 | strcat (intel_parser.disp, reg->reg_name); | |
4a1805b1 | 5542 | |
64a0c779 DN |
5543 | /* It's neither base nor index nor offset. */ |
5544 | else | |
5545 | { | |
5546 | i.types[this_operand] |= reg->reg_type & ~BaseIndex; | |
5547 | i.op[this_operand].regs = reg; | |
5548 | i.reg_operands++; | |
5549 | } | |
5550 | ||
5551 | /* Since registers are not part of the displacement string (except | |
5552 | when we're parsing offset operands), we may need to remove any | |
5553 | preceding '+' from the displacement string. */ | |
5554 | if (*intel_parser.disp != '\0' | |
5555 | && intel_parser.op_modifier != OFFSET_FLAT) | |
5556 | { | |
5557 | char *s = intel_parser.disp; | |
5558 | s += strlen (s) - 1; | |
5559 | if (*s == '+') | |
5560 | *s = '\0'; | |
5561 | } | |
5562 | ||
5563 | return 1; | |
5564 | } | |
4a1805b1 | 5565 | |
64a0c779 DN |
5566 | /* e11 id */ |
5567 | else if (cur_token.code == T_ID) | |
5568 | { | |
5569 | /* Add the identifier to the displacement string. */ | |
5570 | strcat (intel_parser.disp, cur_token.str); | |
5571 | intel_match_token (T_ID); | |
5572 | ||
5573 | /* The identifier represents a memory reference only if it's not | |
5574 | preceded by an offset modifier. */ | |
21d6c4af | 5575 | if (intel_parser.op_modifier != OFFSET_FLAT) |
64a0c779 DN |
5576 | intel_parser.is_mem = 1; |
5577 | ||
5578 | return 1; | |
5579 | } | |
5580 | ||
5581 | /* e11 constant */ | |
5582 | else if (cur_token.code == T_CONST | |
e5cb08ac | 5583 | || cur_token.code == '-' |
64a0c779 DN |
5584 | || cur_token.code == '+') |
5585 | { | |
5586 | char *save_str; | |
5587 | ||
5588 | /* Allow constants that start with `+' or `-'. */ | |
5589 | if (cur_token.code == '-' || cur_token.code == '+') | |
5590 | { | |
5591 | strcat (intel_parser.disp, cur_token.str); | |
5592 | intel_match_token (cur_token.code); | |
5593 | if (cur_token.code != T_CONST) | |
5594 | { | |
5595 | as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"), | |
5596 | cur_token.str); | |
5597 | return 0; | |
5598 | } | |
5599 | } | |
5600 | ||
e5cb08ac | 5601 | save_str = (char *) malloc (strlen (cur_token.str) + 1); |
64a0c779 | 5602 | if (save_str == NULL) |
bc805888 | 5603 | abort (); |
64a0c779 DN |
5604 | strcpy (save_str, cur_token.str); |
5605 | ||
5606 | /* Get the next token to check for register scaling. */ | |
5607 | intel_match_token (cur_token.code); | |
5608 | ||
5609 | /* Check if this constant is a scaling factor for an index register. */ | |
5610 | if (cur_token.code == '*') | |
5611 | { | |
5612 | if (intel_match_token ('*') && cur_token.code == T_REG) | |
5613 | { | |
5614 | if (!intel_parser.is_mem) | |
5615 | { | |
5616 | as_bad (_("Register scaling only allowed in memory operands.")); | |
5617 | return 0; | |
5618 | } | |
5619 | ||
4a1805b1 | 5620 | /* The constant is followed by `* reg', so it must be |
64a0c779 DN |
5621 | a valid scale. */ |
5622 | if (strchr ("01248", *save_str)) | |
5623 | { | |
5624 | i.index_reg = cur_token.reg; | |
5625 | i.types[this_operand] |= BaseIndex; | |
5626 | ||
5627 | /* Set the scale after setting the register (otherwise, | |
5628 | i386_scale will complain) */ | |
5629 | i386_scale (save_str); | |
5630 | intel_match_token (T_REG); | |
5631 | ||
5632 | /* Since registers are not part of the displacement | |
5633 | string, we may need to remove any preceding '+' from | |
5634 | the displacement string. */ | |
5635 | if (*intel_parser.disp != '\0') | |
5636 | { | |
5637 | char *s = intel_parser.disp; | |
5638 | s += strlen (s) - 1; | |
5639 | if (*s == '+') | |
5640 | *s = '\0'; | |
5641 | } | |
5642 | ||
5643 | free (save_str); | |
5644 | ||
5645 | return 1; | |
5646 | } | |
5647 | else | |
5648 | return 0; | |
5649 | } | |
5650 | ||
5651 | /* The constant was not used for register scaling. Since we have | |
5652 | already consumed the token following `*' we now need to put it | |
5653 | back in the stream. */ | |
5654 | else | |
5655 | intel_putback_token (); | |
5656 | } | |
5657 | ||
5658 | /* Add the constant to the displacement string. */ | |
5659 | strcat (intel_parser.disp, save_str); | |
5660 | free (save_str); | |
5661 | ||
5662 | return 1; | |
5663 | } | |
5664 | ||
64a0c779 DN |
5665 | as_bad (_("Unrecognized token '%s'"), cur_token.str); |
5666 | return 0; | |
5667 | } | |
5668 | ||
64a0c779 DN |
5669 | /* Match the given token against cur_token. If they match, read the next |
5670 | token from the operand string. */ | |
5671 | static int | |
5672 | intel_match_token (code) | |
e5cb08ac | 5673 | int code; |
64a0c779 DN |
5674 | { |
5675 | if (cur_token.code == code) | |
5676 | { | |
5677 | intel_get_token (); | |
5678 | return 1; | |
5679 | } | |
5680 | else | |
5681 | { | |
5682 | as_bad (_("Unexpected token `%s'\n"), cur_token.str); | |
5683 | return 0; | |
5684 | } | |
5685 | } | |
5686 | ||
64a0c779 DN |
5687 | /* Read a new token from intel_parser.op_string and store it in cur_token. */ |
5688 | static void | |
5689 | intel_get_token () | |
5690 | { | |
5691 | char *end_op; | |
5692 | const reg_entry *reg; | |
5693 | struct intel_token new_token; | |
5694 | ||
5695 | new_token.code = T_NIL; | |
5696 | new_token.reg = NULL; | |
5697 | new_token.str = NULL; | |
5698 | ||
4a1805b1 | 5699 | /* Free the memory allocated to the previous token and move |
64a0c779 DN |
5700 | cur_token to prev_token. */ |
5701 | if (prev_token.str) | |
5702 | free (prev_token.str); | |
5703 | ||
5704 | prev_token = cur_token; | |
5705 | ||
5706 | /* Skip whitespace. */ | |
5707 | while (is_space_char (*intel_parser.op_string)) | |
5708 | intel_parser.op_string++; | |
5709 | ||
5710 | /* Return an empty token if we find nothing else on the line. */ | |
5711 | if (*intel_parser.op_string == '\0') | |
5712 | { | |
5713 | cur_token = new_token; | |
5714 | return; | |
5715 | } | |
5716 | ||
5717 | /* The new token cannot be larger than the remainder of the operand | |
5718 | string. */ | |
e5cb08ac | 5719 | new_token.str = (char *) malloc (strlen (intel_parser.op_string) + 1); |
64a0c779 | 5720 | if (new_token.str == NULL) |
bc805888 | 5721 | abort (); |
64a0c779 DN |
5722 | new_token.str[0] = '\0'; |
5723 | ||
5724 | if (strchr ("0123456789", *intel_parser.op_string)) | |
5725 | { | |
5726 | char *p = new_token.str; | |
5727 | char *q = intel_parser.op_string; | |
5728 | new_token.code = T_CONST; | |
5729 | ||
5730 | /* Allow any kind of identifier char to encompass floating point and | |
5731 | hexadecimal numbers. */ | |
5732 | while (is_identifier_char (*q)) | |
5733 | *p++ = *q++; | |
5734 | *p = '\0'; | |
5735 | ||
5736 | /* Recognize special symbol names [0-9][bf]. */ | |
5737 | if (strlen (intel_parser.op_string) == 2 | |
4a1805b1 | 5738 | && (intel_parser.op_string[1] == 'b' |
64a0c779 DN |
5739 | || intel_parser.op_string[1] == 'f')) |
5740 | new_token.code = T_ID; | |
5741 | } | |
5742 | ||
5743 | else if (strchr ("+-/*:[]()", *intel_parser.op_string)) | |
5744 | { | |
5745 | new_token.code = *intel_parser.op_string; | |
5746 | new_token.str[0] = *intel_parser.op_string; | |
5747 | new_token.str[1] = '\0'; | |
5748 | } | |
5749 | ||
5750 | else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg) | |
5751 | && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)) | |
5752 | { | |
5753 | new_token.code = T_REG; | |
5754 | new_token.reg = reg; | |
5755 | ||
5756 | if (*intel_parser.op_string == REGISTER_PREFIX) | |
5757 | { | |
5758 | new_token.str[0] = REGISTER_PREFIX; | |
5759 | new_token.str[1] = '\0'; | |
5760 | } | |
5761 | ||
5762 | strcat (new_token.str, reg->reg_name); | |
5763 | } | |
5764 | ||
5765 | else if (is_identifier_char (*intel_parser.op_string)) | |
5766 | { | |
5767 | char *p = new_token.str; | |
5768 | char *q = intel_parser.op_string; | |
5769 | ||
5770 | /* A '.' or '$' followed by an identifier char is an identifier. | |
5771 | Otherwise, it's operator '.' followed by an expression. */ | |
5772 | if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1))) | |
5773 | { | |
5774 | new_token.code = *q; | |
5775 | new_token.str[0] = *q; | |
5776 | new_token.str[1] = '\0'; | |
5777 | } | |
5778 | else | |
5779 | { | |
5780 | while (is_identifier_char (*q) || *q == '@') | |
5781 | *p++ = *q++; | |
5782 | *p = '\0'; | |
5783 | ||
5784 | if (strcasecmp (new_token.str, "BYTE") == 0) | |
5785 | new_token.code = T_BYTE; | |
5786 | ||
5787 | else if (strcasecmp (new_token.str, "WORD") == 0) | |
5788 | new_token.code = T_WORD; | |
5789 | ||
5790 | else if (strcasecmp (new_token.str, "DWORD") == 0) | |
5791 | new_token.code = T_DWORD; | |
5792 | ||
5793 | else if (strcasecmp (new_token.str, "QWORD") == 0) | |
5794 | new_token.code = T_QWORD; | |
5795 | ||
5796 | else if (strcasecmp (new_token.str, "XWORD") == 0) | |
5797 | new_token.code = T_XWORD; | |
5798 | ||
5799 | else if (strcasecmp (new_token.str, "PTR") == 0) | |
5800 | new_token.code = T_PTR; | |
5801 | ||
5802 | else if (strcasecmp (new_token.str, "SHORT") == 0) | |
5803 | new_token.code = T_SHORT; | |
5804 | ||
5805 | else if (strcasecmp (new_token.str, "OFFSET") == 0) | |
5806 | { | |
5807 | new_token.code = T_OFFSET; | |
5808 | ||
5809 | /* ??? This is not mentioned in the MASM grammar but gcc | |
5810 | makes use of it with -mintel-syntax. OFFSET may be | |
5811 | followed by FLAT: */ | |
5812 | if (strncasecmp (q, " FLAT:", 6) == 0) | |
5813 | strcat (new_token.str, " FLAT:"); | |
5814 | } | |
5815 | ||
5816 | /* ??? This is not mentioned in the MASM grammar. */ | |
5817 | else if (strcasecmp (new_token.str, "FLAT") == 0) | |
5818 | new_token.code = T_OFFSET; | |
5819 | ||
5820 | else | |
5821 | new_token.code = T_ID; | |
5822 | } | |
5823 | } | |
5824 | ||
5825 | else | |
5826 | as_bad (_("Unrecognized token `%s'\n"), intel_parser.op_string); | |
5827 | ||
5828 | intel_parser.op_string += strlen (new_token.str); | |
5829 | cur_token = new_token; | |
5830 | } | |
5831 | ||
64a0c779 DN |
5832 | /* Put cur_token back into the token stream and make cur_token point to |
5833 | prev_token. */ | |
5834 | static void | |
5835 | intel_putback_token () | |
5836 | { | |
5837 | intel_parser.op_string -= strlen (cur_token.str); | |
5838 | free (cur_token.str); | |
5839 | cur_token = prev_token; | |
4a1805b1 | 5840 | |
64a0c779 DN |
5841 | /* Forget prev_token. */ |
5842 | prev_token.code = T_NIL; | |
5843 | prev_token.reg = NULL; | |
5844 | prev_token.str = NULL; | |
5845 | } |