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x86: fold various AVX512* templates
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
219d1afa 2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d 68#define LOCK_PREFIX 5
4e9ac44a
L		 69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
6305a203
L		 84/* Intel Syntax. Use a non-ascii letter since since it never appears
85 in instructions. */
86#define LONG_DOUBLE_MNEM_SUFFIX '\1'
87
88#define END_OF_INSN '\0'
89
90/*
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
95 END.
96 */
97typedef struct
98{
d3ce72d0
NC		 99 const insn_template *start;
100 const insn_template *end;
6305a203
L		 101}
102templates;
103
104/* 386 operand encoding bytes: see 386 book for details of this. */
105typedef struct
106{
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
110}
111modrm_byte;
112
113/* x86-64 extension prefix. */
114typedef int rex_byte;
115
6305a203
L		 116/* 386 opcode byte to code indirect addressing. */
117typedef struct
118{
119 unsigned base;
120 unsigned index;
121 unsigned scale;
122}
123sib_byte;
124
6305a203
L		 125/* x86 arch names, types and features */
126typedef struct
127{
128 const char *name; /* arch name */
8a2c8fef 129 unsigned int len; /* arch string length */
6305a203
L		 130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 132 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 133}
134arch_entry;
135
293f5f65
L		 136/* Used to turn off indicated flags. */
137typedef struct
138{
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
142}
143noarch_entry;
144
78f12dd3 145static void update_code_flag (int, int);
e3bb37b5
L		 146static void set_code_flag (int);
147static void set_16bit_gcc_code_flag (int);
148static void set_intel_syntax (int);
1efbbeb4 149static void set_intel_mnemonic (int);
db51cc60 150static void set_allow_index_reg (int);
7bab8ab5 151static void set_check (int);
e3bb37b5 152static void set_cpu_arch (int);
6482c264 153#ifdef TE_PE
e3bb37b5 154static void pe_directive_secrel (int);
6482c264 155#endif
e3bb37b5
L		 156static void signed_cons (int);
157static char *output_invalid (int c);
ee86248c
JB		 158static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
159 const char *);
160static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
161 const char *);
a7619375 162static int i386_att_operand (char *);
e3bb37b5 163static int i386_intel_operand (char *, int);
ee86248c
JB		 164static int i386_intel_simplify (expressionS *);
165static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 166static const reg_entry *parse_register (char *, char **);
167static char *parse_insn (char *, char *);
168static char *parse_operands (char *, const char *);
169static void swap_operands (void);
4d456e3d 170static void swap_2_operands (int, int);
e3bb37b5
L		 171static void optimize_imm (void);
172static void optimize_disp (void);
83b16ac6 173static const insn_template *match_template (char);
e3bb37b5
L		 174static int check_string (void);
175static int process_suffix (void);
176static int check_byte_reg (void);
177static int check_long_reg (void);
178static int check_qword_reg (void);
179static int check_word_reg (void);
180static int finalize_imm (void);
181static int process_operands (void);
182static const seg_entry *build_modrm_byte (void);
183static void output_insn (void);
184static void output_imm (fragS *, offsetT);
185static void output_disp (fragS *, offsetT);
29b0f896 186#ifndef I386COFF
e3bb37b5 187static void s_bss (int);
252b5132 188#endif
17d4e2a2
L		 189#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190static void handle_large_common (int small ATTRIBUTE_UNUSED);
191#endif
252b5132 192
a847613f 193static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 194
43234a1e
L		 195/* This struct describes rounding control and SAE in the instruction. */
196struct RC_Operation
197{
198 enum rc_type
199 {
200 rne = 0,
201 rd,
202 ru,
203 rz,
204 saeonly
205 } type;
206 int operand;
207};
208
209static struct RC_Operation rc_op;
210
211/* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214struct Mask_Operation
215{
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
219 int operand;
220};
221
222static struct Mask_Operation mask_op;
223
224/* The struct describes broadcasting, applied to OPERAND. FACTOR is
225 broadcast factor. */
226struct Broadcast_Operation
227{
8e6e0792 228 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
43234a1e
L		 229 int type;
230
231 /* Index of broadcasted operand. */
232 int operand;
233};
234
235static struct Broadcast_Operation broadcast_op;
236
c0f3af97
L		 237/* VEX prefix. */
238typedef struct
239{
43234a1e
L		 240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes[4];
c0f3af97
L		 242 unsigned int length;
243 /* Destination or source register specifier. */
244 const reg_entry *register_specifier;
245} vex_prefix;
246
252b5132 247/* 'md_assemble ()' gathers together information and puts it into a
47926f60 248 i386_insn. */
252b5132 249
520dc8e8
AM		 250union i386_op
251 {
252 expressionS *disps;
253 expressionS *imms;
254 const reg_entry *regs;
255 };
256
a65babc9
L		 257enum i386_error
258 {
86e026a4 259 operand_size_mismatch,
a65babc9
L		 260 operand_type_mismatch,
261 register_type_mismatch,
262 number_of_operands_mismatch,
263 invalid_instruction_suffix,
264 bad_imm4,
a65babc9
L		 265 unsupported_with_intel_mnemonic,
266 unsupported_syntax,
6c30d220
L		 267 unsupported,
268 invalid_vsib_address,
7bab8ab5 269 invalid_vector_register_set,
43234a1e
L		 270 unsupported_vector_index_register,
271 unsupported_broadcast,
272 broadcast_not_on_src_operand,
273 broadcast_needed,
274 unsupported_masking,
275 mask_not_on_destination,
276 no_default_mask,
277 unsupported_rc_sae,
278 rc_sae_operand_not_last_imm,
279 invalid_register_operand,
a65babc9
L		 280 };
281
252b5132
RH		 282struct _i386_insn
283 {
47926f60 284 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 285 insn_template tm;
252b5132 286
7d5e4556
L		 287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
252b5132
RH		 289 char suffix;
290
47926f60 291 /* OPERANDS gives the number of given operands. */
252b5132
RH		 292 unsigned int operands;
293
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
47926f60 296 operands. */
252b5132
RH		 297 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
298
299 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 300 use OP[i] for the corresponding operand. */
40fb9820 301 i386_operand_type types[MAX_OPERANDS];
252b5132 302
520dc8e8
AM		 303 /* Displacement expression, immediate expression, or register for each
304 operand. */
305 union i386_op op[MAX_OPERANDS];
252b5132 306
3e73aa7c
JH		 307 /* Flags for operands. */
308 unsigned int flags[MAX_OPERANDS];
309#define Operand_PCrel 1
310
252b5132 311 /* Relocation type for operand */
f86103b7 312 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 313
252b5132
RH		 314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry *base_reg;
317 const reg_entry *index_reg;
318 unsigned int log2_scale_factor;
319
320 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 321 explicit segment overrides are given. */
ce8a8b2f 322 const seg_entry *seg[2];
252b5132 323
8325cc63
JB		 324 /* Copied first memory operand string, for re-checking. */
325 char *memop1_string;
326
252b5132
RH		 327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes;
330 unsigned char prefix[MAX_PREFIXES];
331
332 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 333 addressing modes of this insn are encoded. */
252b5132 334 modrm_byte rm;
3e73aa7c 335 rex_byte rex;
43234a1e 336 rex_byte vrex;
252b5132 337 sib_byte sib;
c0f3af97 338 vex_prefix vex;
b6169b20 339
43234a1e
L		 340 /* Masking attributes. */
341 struct Mask_Operation *mask;
342
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation *rounding;
345
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation *broadcast;
348
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift;
351
86fa6981
L		 352 /* Prefer load or store in encoding. */
353 enum
354 {
355 dir_encoding_default = 0,
356 dir_encoding_load,
357 dir_encoding_store
358 } dir_encoding;
891edac4 359
a501d77e
L		 360 /* Prefer 8bit or 32bit displacement in encoding. */
361 enum
362 {
363 disp_encoding_default = 0,
364 disp_encoding_8bit,
365 disp_encoding_32bit
366 } disp_encoding;
f8a5c266 367
6b6b6807
L		 368 /* Prefer the REX byte in encoding. */
369 bfd_boolean rex_encoding;
370
b6f8c7c4
L		 371 /* Disable instruction size optimization. */
372 bfd_boolean no_optimize;
373
86fa6981
L		 374 /* How to encode vector instructions. */
375 enum
376 {
377 vex_encoding_default = 0,
378 vex_encoding_vex2,
379 vex_encoding_vex3,
380 vex_encoding_evex
381 } vec_encoding;
382
d5de92cf
L		 383 /* REP prefix. */
384 const char *rep_prefix;
385
165de32a
L		 386 /* HLE prefix. */
387 const char *hle_prefix;
42164a71 388
7e8b059b
L		 389 /* Have BND prefix. */
390 const char *bnd_prefix;
391
04ef582a
L		 392 /* Have NOTRACK prefix. */
393 const char *notrack_prefix;
394
891edac4 395 /* Error message. */
a65babc9 396 enum i386_error error;
252b5132
RH		 397 };
398
399typedef struct _i386_insn i386_insn;
400
43234a1e
L		 401/* Link RC type with corresponding string, that'll be looked for in
402 asm. */
403struct RC_name
404{
405 enum rc_type type;
406 const char *name;
407 unsigned int len;
408};
409
410static const struct RC_name RC_NamesTable[] =
411{
412 { rne, STRING_COMMA_LEN ("rn-sae") },
413 { rd, STRING_COMMA_LEN ("rd-sae") },
414 { ru, STRING_COMMA_LEN ("ru-sae") },
415 { rz, STRING_COMMA_LEN ("rz-sae") },
416 { saeonly, STRING_COMMA_LEN ("sae") },
417};
418
252b5132
RH		 419/* List of chars besides those in app.c:symbol_chars that can start an
420 operand. Used to prevent the scrubber eating vital white-space. */
86fa6981 421const char extra_symbol_chars[] = "*%-([{}"
252b5132 422#ifdef LEX_AT
32137342
NC		 423 "@"
424#endif
425#ifdef LEX_QM
426 "?"
252b5132 427#endif
32137342 428 ;
252b5132 429
29b0f896
AM		 430#if (defined (TE_I386AIX) \
431 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 432 && !defined (TE_GNU) \
29b0f896 433 && !defined (TE_LINUX) \
8d63c93e 434 && !defined (TE_NACL) \
29b0f896 435 && !defined (TE_FreeBSD) \
5b806d27 436 && !defined (TE_DragonFly) \
29b0f896 437 && !defined (TE_NetBSD)))
252b5132 438/* This array holds the chars that always start a comment. If the
b3b91714
AM		 439 pre-processor is disabled, these aren't very useful. The option
440 --divide will remove '/' from this list. */
441const char *i386_comment_chars = "#/";
442#define SVR4_COMMENT_CHARS 1
252b5132 443#define PREFIX_SEPARATOR '\\'
252b5132 444
b3b91714
AM		 445#else
446const char *i386_comment_chars = "#";
447#define PREFIX_SEPARATOR '/'
448#endif
449
252b5132
RH		 450/* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 452 .line and .file directives will appear in the pre-processed output.
453 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 454 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 455 #NO_APP at the beginning of its output.
456 Also note that comments started like this one will always work if
252b5132 457 '/' isn't otherwise defined. */
b3b91714 458const char line_comment_chars[] = "#/";
252b5132 459
63a0b638 460const char line_separator_chars[] = ";";
252b5132 461
ce8a8b2f
AM		 462/* Chars that can be used to separate mant from exp in floating point
463 nums. */
252b5132
RH		 464const char EXP_CHARS[] = "eE";
465
ce8a8b2f
AM		 466/* Chars that mean this number is a floating point constant
467 As in 0f12.456
468 or 0d1.2345e12. */
252b5132
RH		 469const char FLT_CHARS[] = "fFdDxX";
470
ce8a8b2f 471/* Tables for lexical analysis. */
252b5132
RH		 472static char mnemonic_chars[256];
473static char register_chars[256];
474static char operand_chars[256];
475static char identifier_chars[256];
476static char digit_chars[256];
477
ce8a8b2f 478/* Lexical macros. */
252b5132
RH		 479#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
480#define is_operand_char(x) (operand_chars[(unsigned char) x])
481#define is_register_char(x) (register_chars[(unsigned char) x])
482#define is_space_char(x) ((x) == ' ')
483#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
484#define is_digit_char(x) (digit_chars[(unsigned char) x])
485
0234cb7c 486/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 487static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
488
489/* md_assemble() always leaves the strings it's passed unaltered. To
490 effect this we maintain a stack of saved characters that we've smashed
491 with '\0's (indicating end of strings for various sub-fields of the
47926f60 492 assembler instruction). */
252b5132 493static char save_stack[32];
ce8a8b2f 494static char *save_stack_p;
252b5132
RH		 495#define END_STRING_AND_SAVE(s) \
496 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
497#define RESTORE_END_STRING(s) \
498 do { *(s) = *--save_stack_p; } while (0)
499
47926f60 500/* The instruction we're assembling. */
252b5132
RH		 501static i386_insn i;
502
503/* Possible templates for current insn. */
504static const templates *current_templates;
505
31b2323c
L		 506/* Per instruction expressionS buffers: max displacements & immediates. */
507static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
508static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 509
47926f60 510/* Current operand we are working on. */
ee86248c 511static int this_operand = -1;
252b5132 512
3e73aa7c
JH		 513/* We support four different modes. FLAG_CODE variable is used to distinguish
514 these. */
515
516enum flag_code {
517 CODE_32BIT,
518 CODE_16BIT,
519 CODE_64BIT };
520
521static enum flag_code flag_code;
4fa24527 522static unsigned int object_64bit;
862be3fb 523static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 524static int use_rela_relocations = 0;
525
7af8ed2d
NC		 526#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
527 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
528 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
529
351f65ca
L		 530/* The ELF ABI to use. */
531enum x86_elf_abi
532{
533 I386_ABI,
7f56bc95
L		 534 X86_64_ABI,
535 X86_64_X32_ABI
351f65ca
L		 536};
537
538static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 539#endif
351f65ca 540
167ad85b
TG		 541#if defined (TE_PE) || defined (TE_PEP)
542/* Use big object file format. */
543static int use_big_obj = 0;
544#endif
545
8dcea932
L		 546#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547/* 1 if generating code for a shared library. */
548static int shared = 0;
549#endif
550
47926f60
KH		 551/* 1 for intel syntax,
552 0 if att syntax. */
553static int intel_syntax = 0;
252b5132 554
e89c5eaa
L		 555/* 1 for Intel64 ISA,
556 0 if AMD64 ISA. */
557static int intel64;
558
1efbbeb4
L		 559/* 1 for intel mnemonic,
560 0 if att mnemonic. */
561static int intel_mnemonic = !SYSV386_COMPAT;
562
a60de03c
JB		 563/* 1 if pseudo registers are permitted. */
564static int allow_pseudo_reg = 0;
565
47926f60
KH		 566/* 1 if register prefix % not required. */
567static int allow_naked_reg = 0;
252b5132 568
33eaf5de 569/* 1 if the assembler should add BND prefix for all control-transferring
7e8b059b
L		 570 instructions supporting it, even if this prefix wasn't specified
571 explicitly. */
572static int add_bnd_prefix = 0;
573
ba104c83 574/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 575static int allow_index_reg = 0;
576
d022bddd
IT		 577/* 1 if the assembler should ignore LOCK prefix, even if it was
578 specified explicitly. */
579static int omit_lock_prefix = 0;
580
e4e00185
AS		 581/* 1 if the assembler should encode lfence, mfence, and sfence as
582 "lock addl $0, (%{re}sp)". */
583static int avoid_fence = 0;
584
0cb4071e
L		 585/* 1 if the assembler should generate relax relocations. */
586
587static int generate_relax_relocations
588 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
589
7bab8ab5 590static enum check_kind
daf50ae7 591 {
7bab8ab5
JB		 592 check_none = 0,
593 check_warning,
594 check_error
daf50ae7 595 }
7bab8ab5 596sse_check, operand_check = check_warning;
daf50ae7 597
b6f8c7c4
L		 598/* Optimization:
599 1. Clear the REX_W bit with register operand if possible.
600 2. Above plus use 128bit vector instruction to clear the full vector
601 register.
602 */
603static int optimize = 0;
604
605/* Optimization:
606 1. Clear the REX_W bit with register operand if possible.
607 2. Above plus use 128bit vector instruction to clear the full vector
608 register.
609 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
610 "testb $imm7,%r8".
611 */
612static int optimize_for_space = 0;
613
2ca3ace5
L		 614/* Register prefix used for error message. */
615static const char *register_prefix = "%";
616
47926f60
KH		 617/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
618 leave, push, and pop instructions so that gcc has the same stack
619 frame as in 32 bit mode. */
620static char stackop_size = '\0';
eecb386c 621
12b55ccc
L		 622/* Non-zero to optimize code alignment. */
623int optimize_align_code = 1;
624
47926f60
KH		 625/* Non-zero to quieten some warnings. */
626static int quiet_warnings = 0;
a38cf1db 627
47926f60
KH		 628/* CPU name. */
629static const char *cpu_arch_name = NULL;
6305a203 630static char *cpu_sub_arch_name = NULL;
a38cf1db 631
47926f60 632/* CPU feature flags. */
40fb9820
L		 633static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
634
ccc9c027
L		 635/* If we have selected a cpu we are generating instructions for. */
636static int cpu_arch_tune_set = 0;
637
9103f4f4 638/* Cpu we are generating instructions for. */
fbf3f584 639enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 640
641/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 642static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 643
ccc9c027 644/* CPU instruction set architecture used. */
fbf3f584 645enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 646
9103f4f4 647/* CPU feature flags of instruction set architecture used. */
fbf3f584 648i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 649
fddf5b5b
AM		 650/* If set, conditional jumps are not automatically promoted to handle
651 larger than a byte offset. */
652static unsigned int no_cond_jump_promotion = 0;
653
c0f3af97
L		 654/* Encode SSE instructions with VEX prefix. */
655static unsigned int sse2avx;
656
539f890d
L		 657/* Encode scalar AVX instructions with specific vector length. */
658static enum
659 {
660 vex128 = 0,
661 vex256
662 } avxscalar;
663
43234a1e
L		 664/* Encode scalar EVEX LIG instructions with specific vector length. */
665static enum
666 {
667 evexl128 = 0,
668 evexl256,
669 evexl512
670 } evexlig;
671
672/* Encode EVEX WIG instructions with specific evex.w. */
673static enum
674 {
675 evexw0 = 0,
676 evexw1
677 } evexwig;
678
d3d3c6db
IT		 679/* Value to encode in EVEX RC bits, for SAE-only instructions. */
680static enum rc_type evexrcig = rne;
681
29b0f896 682/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 683static symbolS *GOT_symbol;
29b0f896 684
a4447b93
RH		 685/* The dwarf2 return column, adjusted for 32 or 64 bit. */
686unsigned int x86_dwarf2_return_column;
687
688/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
689int x86_cie_data_alignment;
690
252b5132 691/* Interface to relax_segment.
fddf5b5b
AM		 692 There are 3 major relax states for 386 jump insns because the
693 different types of jumps add different sizes to frags when we're
694 figuring out what sort of jump to choose to reach a given label. */
252b5132 695
47926f60 696/* Types. */
93c2a809
AM		 697#define UNCOND_JUMP 0
698#define COND_JUMP 1
699#define COND_JUMP86 2
fddf5b5b 700
47926f60 701/* Sizes. */
252b5132
RH		 702#define CODE16 1
703#define SMALL 0
29b0f896 704#define SMALL16 (SMALL | CODE16)
252b5132 705#define BIG 2
29b0f896 706#define BIG16 (BIG | CODE16)
252b5132
RH		 707
708#ifndef INLINE
709#ifdef __GNUC__
710#define INLINE __inline__
711#else
712#define INLINE
713#endif
714#endif
715
fddf5b5b
AM		 716#define ENCODE_RELAX_STATE(type, size) \
717 ((relax_substateT) (((type) << 2) | (size)))
718#define TYPE_FROM_RELAX_STATE(s) \
719 ((s) >> 2)
720#define DISP_SIZE_FROM_RELAX_STATE(s) \
721 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 722
723/* This table is used by relax_frag to promote short jumps to long
724 ones where necessary. SMALL (short) jumps may be promoted to BIG
725 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
726 don't allow a short jump in a 32 bit code segment to be promoted to
727 a 16 bit offset jump because it's slower (requires data size
728 prefix), and doesn't work, unless the destination is in the bottom
729 64k of the code segment (The top 16 bits of eip are zeroed). */
730
731const relax_typeS md_relax_table[] =
732{
24eab124
AM		 733 /* The fields are:
734 1) most positive reach of this state,
735 2) most negative reach of this state,
93c2a809 736 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 737 4) which index into the table to try if we can't fit into this one. */
252b5132 738
fddf5b5b 739 /* UNCOND_JUMP states. */
93c2a809
AM		 740 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
741 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
742 /* dword jmp adds 4 bytes to frag:
743 0 extra opcode bytes, 4 displacement bytes. */
252b5132 744 {0, 0, 4, 0},
93c2a809
AM		 745 /* word jmp adds 2 byte2 to frag:
746 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 747 {0, 0, 2, 0},
748
93c2a809
AM		 749 /* COND_JUMP states. */
750 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
751 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
752 /* dword conditionals adds 5 bytes to frag:
753 1 extra opcode byte, 4 displacement bytes. */
754 {0, 0, 5, 0},
fddf5b5b 755 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 756 1 extra opcode byte, 2 displacement bytes. */
757 {0, 0, 3, 0},
758
759 /* COND_JUMP86 states. */
760 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
761 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
762 /* dword conditionals adds 5 bytes to frag:
763 1 extra opcode byte, 4 displacement bytes. */
764 {0, 0, 5, 0},
765 /* word conditionals add 4 bytes to frag:
766 1 displacement byte and a 3 byte long branch insn. */
767 {0, 0, 4, 0}
252b5132
RH		 768};
769
9103f4f4
L		 770static const arch_entry cpu_arch[] =
771{
89507696
JB		 772 /* Do not replace the first two entries - i386_target_format()
773 relies on them being there in this order. */
8a2c8fef 774 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 775 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 776 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 777 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 778 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 779 CPU_NONE_FLAGS, 0 },
8a2c8fef 780 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 781 CPU_I186_FLAGS, 0 },
8a2c8fef 782 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 783 CPU_I286_FLAGS, 0 },
8a2c8fef 784 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 785 CPU_I386_FLAGS, 0 },
8a2c8fef 786 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 787 CPU_I486_FLAGS, 0 },
8a2c8fef 788 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 789 CPU_I586_FLAGS, 0 },
8a2c8fef 790 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 791 CPU_I686_FLAGS, 0 },
8a2c8fef 792 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 793 CPU_I586_FLAGS, 0 },
8a2c8fef 794 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 795 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 796 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 797 CPU_P2_FLAGS, 0 },
8a2c8fef 798 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 799 CPU_P3_FLAGS, 0 },
8a2c8fef 800 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 801 CPU_P4_FLAGS, 0 },
8a2c8fef 802 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 803 CPU_CORE_FLAGS, 0 },
8a2c8fef 804 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 805 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 806 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 807 CPU_CORE_FLAGS, 1 },
8a2c8fef 808 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 809 CPU_CORE_FLAGS, 0 },
8a2c8fef 810 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 811 CPU_CORE2_FLAGS, 1 },
8a2c8fef 812 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 813 CPU_CORE2_FLAGS, 0 },
8a2c8fef 814 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 815 CPU_COREI7_FLAGS, 0 },
8a2c8fef 816 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 817 CPU_L1OM_FLAGS, 0 },
7a9068fe 818 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 819 CPU_K1OM_FLAGS, 0 },
81486035 820 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 821 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 822 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 823 CPU_K6_FLAGS, 0 },
8a2c8fef 824 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 825 CPU_K6_2_FLAGS, 0 },
8a2c8fef 826 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 827 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 828 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 829 CPU_K8_FLAGS, 1 },
8a2c8fef 830 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 831 CPU_K8_FLAGS, 0 },
8a2c8fef 832 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 833 CPU_K8_FLAGS, 0 },
8a2c8fef 834 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 835 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 836 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 837 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 838 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 839 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 840 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 841 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 842 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 843 CPU_BDVER4_FLAGS, 0 },
029f3522 844 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 845 CPU_ZNVER1_FLAGS, 0 },
a9660a6f
AP		 846 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER,
847 CPU_ZNVER2_FLAGS, 0 },
7b458c12 848 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 849 CPU_BTVER1_FLAGS, 0 },
7b458c12 850 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 851 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 852 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 853 CPU_8087_FLAGS, 0 },
8a2c8fef 854 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 855 CPU_287_FLAGS, 0 },
8a2c8fef 856 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 857 CPU_387_FLAGS, 0 },
1848e567
L		 858 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
859 CPU_687_FLAGS, 0 },
8a2c8fef 860 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 861 CPU_MMX_FLAGS, 0 },
8a2c8fef 862 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 863 CPU_SSE_FLAGS, 0 },
8a2c8fef 864 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 865 CPU_SSE2_FLAGS, 0 },
8a2c8fef 866 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 867 CPU_SSE3_FLAGS, 0 },
8a2c8fef 868 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 869 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 870 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 871 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 872 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 873 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 874 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 875 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 876 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 877 CPU_AVX_FLAGS, 0 },
6c30d220 878 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 879 CPU_AVX2_FLAGS, 0 },
43234a1e 880 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 881 CPU_AVX512F_FLAGS, 0 },
43234a1e 882 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 883 CPU_AVX512CD_FLAGS, 0 },
43234a1e 884 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 885 CPU_AVX512ER_FLAGS, 0 },
43234a1e 886 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 887 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 888 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 889 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 890 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 891 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 892 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 893 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 894 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 895 CPU_VMX_FLAGS, 0 },
8729a6f6 896 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 897 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 898 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 899 CPU_SMX_FLAGS, 0 },
8a2c8fef 900 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 901 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 902 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 903 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 904 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 905 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 906 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 907 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 908 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 909 CPU_AES_FLAGS, 0 },
8a2c8fef 910 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 911 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 912 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 913 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 914 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 915 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 916 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 917 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 918 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 919 CPU_F16C_FLAGS, 0 },
6c30d220 920 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 921 CPU_BMI2_FLAGS, 0 },
8a2c8fef 922 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 923 CPU_FMA_FLAGS, 0 },
8a2c8fef 924 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 925 CPU_FMA4_FLAGS, 0 },
8a2c8fef 926 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 927 CPU_XOP_FLAGS, 0 },
8a2c8fef 928 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 929 CPU_LWP_FLAGS, 0 },
8a2c8fef 930 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 931 CPU_MOVBE_FLAGS, 0 },
60aa667e 932 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 933 CPU_CX16_FLAGS, 0 },
8a2c8fef 934 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 935 CPU_EPT_FLAGS, 0 },
6c30d220 936 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 937 CPU_LZCNT_FLAGS, 0 },
42164a71 938 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 939 CPU_HLE_FLAGS, 0 },
42164a71 940 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 941 CPU_RTM_FLAGS, 0 },
6c30d220 942 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 943 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 944 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 945 CPU_CLFLUSH_FLAGS, 0 },
22109423 946 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 947 CPU_NOP_FLAGS, 0 },
8a2c8fef 948 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 949 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 950 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 951 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 952 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 953 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 954 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 955 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 956 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 957 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 958 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 959 CPU_SVME_FLAGS, 1 },
8a2c8fef 960 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 961 CPU_SVME_FLAGS, 0 },
8a2c8fef 962 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 963 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 964 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 965 CPU_ABM_FLAGS, 0 },
87973e9f 966 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 967 CPU_BMI_FLAGS, 0 },
2a2a0f38 968 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 969 CPU_TBM_FLAGS, 0 },
e2e1fcde 970 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 971 CPU_ADX_FLAGS, 0 },
e2e1fcde 972 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 973 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 974 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 975 CPU_PRFCHW_FLAGS, 0 },
5c111e37 976 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 977 CPU_SMAP_FLAGS, 0 },
7e8b059b 978 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 979 CPU_MPX_FLAGS, 0 },
a0046408 980 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 981 CPU_SHA_FLAGS, 0 },
963f3586 982 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 983 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 984 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 985 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 986 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 987 CPU_SE1_FLAGS, 0 },
c5e7287a 988 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 989 CPU_CLWB_FLAGS, 0 },
2cc1b5aa 990 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 991 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 992 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 993 CPU_AVX512VBMI_FLAGS, 0 },
920d2ddc
IT		 994 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
995 CPU_AVX512_4FMAPS_FLAGS, 0 },
47acf0bd
IT		 996 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
997 CPU_AVX512_4VNNIW_FLAGS, 0 },
620214f7
IT		 998 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
999 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
53467f57
IT		 1000 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1001 CPU_AVX512_VBMI2_FLAGS, 0 },
8cfcb765
IT		 1002 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1003 CPU_AVX512_VNNI_FLAGS, 0 },
ee6872be
IT		 1004 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1005 CPU_AVX512_BITALG_FLAGS, 0 },
029f3522 1006 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 1007 CPU_CLZERO_FLAGS, 0 },
9916071f 1008 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 1009 CPU_MWAITX_FLAGS, 0 },
8eab4136 1010 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 1011 CPU_OSPKE_FLAGS, 0 },
8bc52696 1012 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65 1013 CPU_RDPID_FLAGS, 0 },
6b40c462
L		 1014 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1015 CPU_PTWRITE_FLAGS, 0 },
d777820b
IT		 1016 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1017 CPU_IBT_FLAGS, 0 },
1018 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1019 CPU_SHSTK_FLAGS, 0 },
48521003
IT		 1020 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1021 CPU_GFNI_FLAGS, 0 },
8dcf1fad
IT		 1022 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1023 CPU_VAES_FLAGS, 0 },
ff1982d5
IT		 1024 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1025 CPU_VPCLMULQDQ_FLAGS, 0 },
3233d7d0
IT		 1026 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1027 CPU_WBNOINVD_FLAGS, 0 },
be3a8dca
IT		 1028 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1029 CPU_PCONFIG_FLAGS, 0 },
de89d0a3
IT		 1030 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN,
1031 CPU_WAITPKG_FLAGS, 0 },
c48935d7
IT		 1032 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN,
1033 CPU_CLDEMOTE_FLAGS, 0 },
c0a30a9f
L		 1034 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN,
1035 CPU_MOVDIRI_FLAGS, 0 },
1036 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN,
1037 CPU_MOVDIR64B_FLAGS, 0 },
293f5f65
L		 1038};
1039
1040static const noarch_entry cpu_noarch[] =
1041{
1042 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1848e567
L		 1043 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1044 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1045 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
293f5f65
L		 1046 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1047 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1848e567
L		 1048 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1049 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1050 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1051 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1052 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1053 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
293f5f65 1054 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1848e567 1055 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
144b71e2
L		 1056 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1057 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1059 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1060 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1061 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1062 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1063 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1064 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
920d2ddc 1065 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
47acf0bd 1066 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
620214f7 1067 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
53467f57 1068 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
8cfcb765 1069 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
ee6872be 1070 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
d777820b
IT		 1071 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1072 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
c0a30a9f
L		 1073 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS },
1074 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS },
e413e4e9
AM		 1075};
1076
704209c0 1077#ifdef I386COFF
a6c24e68
NC		 1078/* Like s_lcomm_internal in gas/read.c but the alignment string
1079 is allowed to be optional. */
1080
1081static symbolS *
1082pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1083{
1084 addressT align = 0;
1085
1086 SKIP_WHITESPACE ();
1087
7ab9ffdd 1088 if (needs_align
a6c24e68
NC		 1089 && *input_line_pointer == ',')
1090 {
1091 align = parse_align (needs_align - 1);
7ab9ffdd 1092
a6c24e68
NC		 1093 if (align == (addressT) -1)
1094 return NULL;
1095 }
1096 else
1097 {
1098 if (size >= 8)
1099 align = 3;
1100 else if (size >= 4)
1101 align = 2;
1102 else if (size >= 2)
1103 align = 1;
1104 else
1105 align = 0;
1106 }
1107
1108 bss_alloc (symbolP, size, align);
1109 return symbolP;
1110}
1111
704209c0 1112static void
a6c24e68
NC		 1113pe_lcomm (int needs_align)
1114{
1115 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1116}
704209c0 1117#endif
a6c24e68 1118
29b0f896
AM		 1119const pseudo_typeS md_pseudo_table[] =
1120{
1121#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1122 {"align", s_align_bytes, 0},
1123#else
1124 {"align", s_align_ptwo, 0},
1125#endif
1126 {"arch", set_cpu_arch, 0},
1127#ifndef I386COFF
1128 {"bss", s_bss, 0},
a6c24e68
NC		 1129#else
1130 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1131#endif
1132 {"ffloat", float_cons, 'f'},
1133 {"dfloat", float_cons, 'd'},
1134 {"tfloat", float_cons, 'x'},
1135 {"value", cons, 2},
d182319b 1136 {"slong", signed_cons, 4},
29b0f896
AM		 1137 {"noopt", s_ignore, 0},
1138 {"optim", s_ignore, 0},
1139 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1140 {"code16", set_code_flag, CODE_16BIT},
1141 {"code32", set_code_flag, CODE_32BIT},
da5f19a2 1142#ifdef BFD64
29b0f896 1143 {"code64", set_code_flag, CODE_64BIT},
da5f19a2 1144#endif
29b0f896
AM		 1145 {"intel_syntax", set_intel_syntax, 1},
1146 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1147 {"intel_mnemonic", set_intel_mnemonic, 1},
1148 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1149 {"allow_index_reg", set_allow_index_reg, 1},
1150 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1151 {"sse_check", set_check, 0},
1152 {"operand_check", set_check, 1},
3b22753a
L		 1153#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1154 {"largecomm", handle_large_common, 0},
07a53e5c 1155#else
68d20676 1156 {"file", dwarf2_directive_file, 0},
07a53e5c
RH		 1157 {"loc", dwarf2_directive_loc, 0},
1158 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1159#endif
6482c264
NC		 1160#ifdef TE_PE
1161 {"secrel32", pe_directive_secrel, 0},
1162#endif
29b0f896
AM		 1163 {0, 0, 0}
1164};
1165
1166/* For interface with expression (). */
1167extern char *input_line_pointer;
1168
1169/* Hash table for instruction mnemonic lookup. */
1170static struct hash_control *op_hash;
1171
1172/* Hash table for register lookup. */
1173static struct hash_control *reg_hash;
1174\f
ce8a8b2f
AM		 1175 /* Various efficient no-op patterns for aligning code labels.
1176 Note: Don't try to assemble the instructions in the comments.
1177 0L and 0w are not legal. */
62a02d25
L		 1178static const unsigned char f32_1[] =
1179 {0x90}; /* nop */
1180static const unsigned char f32_2[] =
1181 {0x66,0x90}; /* xchg %ax,%ax */
1182static const unsigned char f32_3[] =
1183 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1184static const unsigned char f32_4[] =
1185 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
62a02d25
L		 1186static const unsigned char f32_6[] =
1187 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1188static const unsigned char f32_7[] =
1189 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
62a02d25 1190static const unsigned char f16_3[] =
3ae729d5 1191 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
62a02d25 1192static const unsigned char f16_4[] =
3ae729d5
L		 1193 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1194static const unsigned char jump_disp8[] =
1195 {0xeb}; /* jmp disp8 */
1196static const unsigned char jump32_disp32[] =
1197 {0xe9}; /* jmp disp32 */
1198static const unsigned char jump16_disp32[] =
1199 {0x66,0xe9}; /* jmp disp32 */
62a02d25
L		 1200/* 32-bit NOPs patterns. */
1201static const unsigned char *const f32_patt[] = {
3ae729d5 1202 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
62a02d25
L		 1203};
1204/* 16-bit NOPs patterns. */
1205static const unsigned char *const f16_patt[] = {
3ae729d5 1206 f32_1, f32_2, f16_3, f16_4
62a02d25
L		 1207};
1208/* nopl (%[re]ax) */
1209static const unsigned char alt_3[] =
1210 {0x0f,0x1f,0x00};
1211/* nopl 0(%[re]ax) */
1212static const unsigned char alt_4[] =
1213 {0x0f,0x1f,0x40,0x00};
1214/* nopl 0(%[re]ax,%[re]ax,1) */
1215static const unsigned char alt_5[] =
1216 {0x0f,0x1f,0x44,0x00,0x00};
1217/* nopw 0(%[re]ax,%[re]ax,1) */
1218static const unsigned char alt_6[] =
1219 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1220/* nopl 0L(%[re]ax) */
1221static const unsigned char alt_7[] =
1222 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1223/* nopl 0L(%[re]ax,%[re]ax,1) */
1224static const unsigned char alt_8[] =
1225 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1226/* nopw 0L(%[re]ax,%[re]ax,1) */
1227static const unsigned char alt_9[] =
1228 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1229/* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1230static const unsigned char alt_10[] =
1231 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
3ae729d5
L		 1232/* data16 nopw %cs:0L(%eax,%eax,1) */
1233static const unsigned char alt_11[] =
1234 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
62a02d25
L		 1235/* 32-bit and 64-bit NOPs patterns. */
1236static const unsigned char *const alt_patt[] = {
1237 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
3ae729d5 1238 alt_9, alt_10, alt_11
62a02d25
L		 1239};
1240
1241/* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1242 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1243
1244static void
1245i386_output_nops (char *where, const unsigned char *const *patt,
1246 int count, int max_single_nop_size)
1247
1248{
3ae729d5
L		 1249 /* Place the longer NOP first. */
1250 int last;
1251 int offset;
1252 const unsigned char *nops = patt[max_single_nop_size - 1];
1253
1254 /* Use the smaller one if the requsted one isn't available. */
1255 if (nops == NULL)
62a02d25 1256 {
3ae729d5
L		 1257 max_single_nop_size--;
1258 nops = patt[max_single_nop_size - 1];
62a02d25
L		 1259 }
1260
3ae729d5
L		 1261 last = count % max_single_nop_size;
1262
1263 count -= last;
1264 for (offset = 0; offset < count; offset += max_single_nop_size)
1265 memcpy (where + offset, nops, max_single_nop_size);
1266
1267 if (last)
1268 {
1269 nops = patt[last - 1];
1270 if (nops == NULL)
1271 {
1272 /* Use the smaller one plus one-byte NOP if the needed one
1273 isn't available. */
1274 last--;
1275 nops = patt[last - 1];
1276 memcpy (where + offset, nops, last);
1277 where[offset + last] = *patt[0];
1278 }
1279 else
1280 memcpy (where + offset, nops, last);
1281 }
62a02d25
L		 1282}
1283
3ae729d5
L		 1284static INLINE int
1285fits_in_imm7 (offsetT num)
1286{
1287 return (num & 0x7f) == num;
1288}
1289
1290static INLINE int
1291fits_in_imm31 (offsetT num)
1292{
1293 return (num & 0x7fffffff) == num;
1294}
62a02d25
L		 1295
1296/* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1297 single NOP instruction LIMIT. */
1298
1299void
3ae729d5 1300i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
62a02d25 1301{
3ae729d5 1302 const unsigned char *const *patt = NULL;
62a02d25 1303 int max_single_nop_size;
3ae729d5
L		 1304 /* Maximum number of NOPs before switching to jump over NOPs. */
1305 int max_number_of_nops;
62a02d25 1306
3ae729d5 1307 switch (fragP->fr_type)
62a02d25 1308 {
3ae729d5
L		 1309 case rs_fill_nop:
1310 case rs_align_code:
1311 break;
1312 default:
62a02d25
L		 1313 return;
1314 }
1315
ccc9c027
L		 1316 /* We need to decide which NOP sequence to use for 32bit and
1317 64bit. When -mtune= is used:
4eed87de 1318
76bc74dc
L		 1319 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1320 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1321 2. For the rest, alt_patt will be used.
1322
1323 When -mtune= isn't used, alt_patt will be used if
22109423 1324 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1325 be used.
ccc9c027
L		 1326
1327 When -march= or .arch is used, we can't use anything beyond
1328 cpu_arch_isa_flags. */
1329
1330 if (flag_code == CODE_16BIT)
1331 {
3ae729d5
L		 1332 patt = f16_patt;
1333 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1334 /* Limit number of NOPs to 2 in 16-bit mode. */
1335 max_number_of_nops = 2;
252b5132 1336 }
33fef721 1337 else
ccc9c027 1338 {
fbf3f584 1339 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1340 {
1341 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1342 switch (cpu_arch_tune)
1343 {
1344 case PROCESSOR_UNKNOWN:
1345 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1346 optimize with nops. */
1347 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1348 patt = alt_patt;
ccc9c027
L		 1349 else
1350 patt = f32_patt;
1351 break;
ccc9c027
L		 1352 case PROCESSOR_PENTIUM4:
1353 case PROCESSOR_NOCONA:
ef05d495 1354 case PROCESSOR_CORE:
76bc74dc 1355 case PROCESSOR_CORE2:
bd5295b2 1356 case PROCESSOR_COREI7:
3632d14b 1357 case PROCESSOR_L1OM:
7a9068fe 1358 case PROCESSOR_K1OM:
76bc74dc 1359 case PROCESSOR_GENERIC64:
ccc9c027
L		 1360 case PROCESSOR_K6:
1361 case PROCESSOR_ATHLON:
1362 case PROCESSOR_K8:
4eed87de 1363 case PROCESSOR_AMDFAM10:
8aedb9fe 1364 case PROCESSOR_BD:
029f3522 1365 case PROCESSOR_ZNVER:
7b458c12 1366 case PROCESSOR_BT:
80b8656c 1367 patt = alt_patt;
ccc9c027 1368 break;
76bc74dc 1369 case PROCESSOR_I386:
ccc9c027
L		 1370 case PROCESSOR_I486:
1371 case PROCESSOR_PENTIUM:
2dde1948 1372 case PROCESSOR_PENTIUMPRO:
81486035 1373 case PROCESSOR_IAMCU:
ccc9c027
L		 1374 case PROCESSOR_GENERIC32:
1375 patt = f32_patt;
1376 break;
4eed87de 1377 }
ccc9c027
L		 1378 }
1379 else
1380 {
fbf3f584 1381 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1382 {
1383 case PROCESSOR_UNKNOWN:
e6a14101 1384 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1385 PROCESSOR_UNKNOWN. */
1386 abort ();
1387 break;
1388
76bc74dc 1389 case PROCESSOR_I386:
ccc9c027
L		 1390 case PROCESSOR_I486:
1391 case PROCESSOR_PENTIUM:
81486035 1392 case PROCESSOR_IAMCU:
ccc9c027
L		 1393 case PROCESSOR_K6:
1394 case PROCESSOR_ATHLON:
1395 case PROCESSOR_K8:
4eed87de 1396 case PROCESSOR_AMDFAM10:
8aedb9fe 1397 case PROCESSOR_BD:
029f3522 1398 case PROCESSOR_ZNVER:
7b458c12 1399 case PROCESSOR_BT:
ccc9c027
L		 1400 case PROCESSOR_GENERIC32:
1401 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1402 with nops. */
1403 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1404 patt = alt_patt;
ccc9c027
L		 1405 else
1406 patt = f32_patt;
1407 break;
76bc74dc
L		 1408 case PROCESSOR_PENTIUMPRO:
1409 case PROCESSOR_PENTIUM4:
1410 case PROCESSOR_NOCONA:
1411 case PROCESSOR_CORE:
ef05d495 1412 case PROCESSOR_CORE2:
bd5295b2 1413 case PROCESSOR_COREI7:
3632d14b 1414 case PROCESSOR_L1OM:
7a9068fe 1415 case PROCESSOR_K1OM:
22109423 1416 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1417 patt = alt_patt;
ccc9c027
L		 1418 else
1419 patt = f32_patt;
1420 break;
1421 case PROCESSOR_GENERIC64:
80b8656c 1422 patt = alt_patt;
ccc9c027 1423 break;
4eed87de 1424 }
ccc9c027
L		 1425 }
1426
76bc74dc
L		 1427 if (patt == f32_patt)
1428 {
3ae729d5
L		 1429 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1430 /* Limit number of NOPs to 2 for older processors. */
1431 max_number_of_nops = 2;
76bc74dc
L		 1432 }
1433 else
1434 {
3ae729d5
L		 1435 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1436 /* Limit number of NOPs to 7 for newer processors. */
1437 max_number_of_nops = 7;
1438 }
1439 }
1440
1441 if (limit == 0)
1442 limit = max_single_nop_size;
1443
1444 if (fragP->fr_type == rs_fill_nop)
1445 {
1446 /* Output NOPs for .nop directive. */
1447 if (limit > max_single_nop_size)
1448 {
1449 as_bad_where (fragP->fr_file, fragP->fr_line,
1450 _("invalid single nop size: %d "
1451 "(expect within [0, %d])"),
1452 limit, max_single_nop_size);
1453 return;
1454 }
1455 }
1456 else
1457 fragP->fr_var = count;
1458
1459 if ((count / max_single_nop_size) > max_number_of_nops)
1460 {
1461 /* Generate jump over NOPs. */
1462 offsetT disp = count - 2;
1463 if (fits_in_imm7 (disp))
1464 {
1465 /* Use "jmp disp8" if possible. */
1466 count = disp;
1467 where[0] = jump_disp8[0];
1468 where[1] = count;
1469 where += 2;
1470 }
1471 else
1472 {
1473 unsigned int size_of_jump;
1474
1475 if (flag_code == CODE_16BIT)
1476 {
1477 where[0] = jump16_disp32[0];
1478 where[1] = jump16_disp32[1];
1479 size_of_jump = 2;
1480 }
1481 else
1482 {
1483 where[0] = jump32_disp32[0];
1484 size_of_jump = 1;
1485 }
1486
1487 count -= size_of_jump + 4;
1488 if (!fits_in_imm31 (count))
1489 {
1490 as_bad_where (fragP->fr_file, fragP->fr_line,
1491 _("jump over nop padding out of range"));
1492 return;
1493 }
1494
1495 md_number_to_chars (where + size_of_jump, count, 4);
1496 where += size_of_jump + 4;
76bc74dc 1497 }
ccc9c027 1498 }
3ae729d5
L		 1499
1500 /* Generate multiple NOPs. */
1501 i386_output_nops (where, patt, count, limit);
252b5132
RH		 1502}
1503
c6fb90c8 1504static INLINE int
0dfbf9d7 1505operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1506{
0dfbf9d7 1507 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1508 {
1509 case 3:
0dfbf9d7 1510 if (x->array[2])
c6fb90c8 1511 return 0;
1a0670f3 1512 /* Fall through. */
c6fb90c8 1513 case 2:
0dfbf9d7 1514 if (x->array[1])
c6fb90c8 1515 return 0;
1a0670f3 1516 /* Fall through. */
c6fb90c8 1517 case 1:
0dfbf9d7 1518 return !x->array[0];
c6fb90c8
L		 1519 default:
1520 abort ();
1521 }
40fb9820
L		 1522}
1523
c6fb90c8 1524static INLINE void
0dfbf9d7 1525operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1526{
0dfbf9d7 1527 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1528 {
1529 case 3:
0dfbf9d7 1530 x->array[2] = v;
1a0670f3 1531 /* Fall through. */
c6fb90c8 1532 case 2:
0dfbf9d7 1533 x->array[1] = v;
1a0670f3 1534 /* Fall through. */
c6fb90c8 1535 case 1:
0dfbf9d7 1536 x->array[0] = v;
1a0670f3 1537 /* Fall through. */
c6fb90c8
L		 1538 break;
1539 default:
1540 abort ();
1541 }
1542}
40fb9820 1543
c6fb90c8 1544static INLINE int
0dfbf9d7
L		 1545operand_type_equal (const union i386_operand_type *x,
1546 const union i386_operand_type *y)
c6fb90c8 1547{
0dfbf9d7 1548 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1549 {
1550 case 3:
0dfbf9d7 1551 if (x->array[2] != y->array[2])
c6fb90c8 1552 return 0;
1a0670f3 1553 /* Fall through. */
c6fb90c8 1554 case 2:
0dfbf9d7 1555 if (x->array[1] != y->array[1])
c6fb90c8 1556 return 0;
1a0670f3 1557 /* Fall through. */
c6fb90c8 1558 case 1:
0dfbf9d7 1559 return x->array[0] == y->array[0];
c6fb90c8
L		 1560 break;
1561 default:
1562 abort ();
1563 }
1564}
40fb9820 1565
0dfbf9d7
L		 1566static INLINE int
1567cpu_flags_all_zero (const union i386_cpu_flags *x)
1568{
1569 switch (ARRAY_SIZE(x->array))
1570 {
53467f57
IT		 1571 case 4:
1572 if (x->array[3])
1573 return 0;
1574 /* Fall through. */
0dfbf9d7
L		 1575 case 3:
1576 if (x->array[2])
1577 return 0;
1a0670f3 1578 /* Fall through. */
0dfbf9d7
L		 1579 case 2:
1580 if (x->array[1])
1581 return 0;
1a0670f3 1582 /* Fall through. */
0dfbf9d7
L		 1583 case 1:
1584 return !x->array[0];
1585 default:
1586 abort ();
1587 }
1588}
1589
0dfbf9d7
L		 1590static INLINE int
1591cpu_flags_equal (const union i386_cpu_flags *x,
1592 const union i386_cpu_flags *y)
1593{
1594 switch (ARRAY_SIZE(x->array))
1595 {
53467f57
IT		 1596 case 4:
1597 if (x->array[3] != y->array[3])
1598 return 0;
1599 /* Fall through. */
0dfbf9d7
L		 1600 case 3:
1601 if (x->array[2] != y->array[2])
1602 return 0;
1a0670f3 1603 /* Fall through. */
0dfbf9d7
L		 1604 case 2:
1605 if (x->array[1] != y->array[1])
1606 return 0;
1a0670f3 1607 /* Fall through. */
0dfbf9d7
L		 1608 case 1:
1609 return x->array[0] == y->array[0];
1610 break;
1611 default:
1612 abort ();
1613 }
1614}
c6fb90c8
L		 1615
1616static INLINE int
1617cpu_flags_check_cpu64 (i386_cpu_flags f)
1618{
1619 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1620 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1621}
1622
c6fb90c8
L		 1623static INLINE i386_cpu_flags
1624cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1625{
c6fb90c8
L		 1626 switch (ARRAY_SIZE (x.array))
1627 {
53467f57
IT		 1628 case 4:
1629 x.array [3] &= y.array [3];
1630 /* Fall through. */
c6fb90c8
L		 1631 case 3:
1632 x.array [2] &= y.array [2];
1a0670f3 1633 /* Fall through. */
c6fb90c8
L		 1634 case 2:
1635 x.array [1] &= y.array [1];
1a0670f3 1636 /* Fall through. */
c6fb90c8
L		 1637 case 1:
1638 x.array [0] &= y.array [0];
1639 break;
1640 default:
1641 abort ();
1642 }
1643 return x;
1644}
40fb9820 1645
c6fb90c8
L		 1646static INLINE i386_cpu_flags
1647cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1648{
c6fb90c8 1649 switch (ARRAY_SIZE (x.array))
40fb9820 1650 {
53467f57
IT		 1651 case 4:
1652 x.array [3] |= y.array [3];
1653 /* Fall through. */
c6fb90c8
L		 1654 case 3:
1655 x.array [2] |= y.array [2];
1a0670f3 1656 /* Fall through. */
c6fb90c8
L		 1657 case 2:
1658 x.array [1] |= y.array [1];
1a0670f3 1659 /* Fall through. */
c6fb90c8
L		 1660 case 1:
1661 x.array [0] |= y.array [0];
40fb9820
L		 1662 break;
1663 default:
1664 abort ();
1665 }
40fb9820
L		 1666 return x;
1667}
1668
309d3373
JB		 1669static INLINE i386_cpu_flags
1670cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1671{
1672 switch (ARRAY_SIZE (x.array))
1673 {
53467f57
IT		 1674 case 4:
1675 x.array [3] &= ~y.array [3];
1676 /* Fall through. */
309d3373
JB		 1677 case 3:
1678 x.array [2] &= ~y.array [2];
1a0670f3 1679 /* Fall through. */
309d3373
JB		 1680 case 2:
1681 x.array [1] &= ~y.array [1];
1a0670f3 1682 /* Fall through. */
309d3373
JB		 1683 case 1:
1684 x.array [0] &= ~y.array [0];
1685 break;
1686 default:
1687 abort ();
1688 }
1689 return x;
1690}
1691
c0f3af97
L		 1692#define CPU_FLAGS_ARCH_MATCH 0x1
1693#define CPU_FLAGS_64BIT_MATCH 0x2
1694
c0f3af97 1695#define CPU_FLAGS_PERFECT_MATCH \
db12e14e 1696 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
c0f3af97
L		 1697
1698/* Return CPU flags match bits. */
3629bb00 1699
40fb9820 1700static int
d3ce72d0 1701cpu_flags_match (const insn_template *t)
40fb9820 1702{
c0f3af97
L		 1703 i386_cpu_flags x = t->cpu_flags;
1704 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1705
1706 x.bitfield.cpu64 = 0;
1707 x.bitfield.cpuno64 = 0;
1708
0dfbf9d7 1709 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1710 {
1711 /* This instruction is available on all archs. */
db12e14e 1712 match |= CPU_FLAGS_ARCH_MATCH;
c0f3af97 1713 }
3629bb00
L		 1714 else
1715 {
c0f3af97 1716 /* This instruction is available only on some archs. */
3629bb00
L		 1717 i386_cpu_flags cpu = cpu_arch_flags;
1718
ab592e75
JB		 1719 /* AVX512VL is no standalone feature - match it and then strip it. */
1720 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1721 return match;
1722 x.bitfield.cpuavx512vl = 0;
1723
3629bb00 1724 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1725 if (!cpu_flags_all_zero (&cpu))
1726 {
a5ff0eb2
L		 1727 if (x.bitfield.cpuavx)
1728 {
929f69fa 1729 /* We need to check a few extra flags with AVX. */
b9d49817
JB		 1730 if (cpu.bitfield.cpuavx
1731 && (!t->opcode_modifier.sse2avx || sse2avx)
1732 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
929f69fa 1733 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
b9d49817
JB		 1734 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1735 match |= CPU_FLAGS_ARCH_MATCH;
a5ff0eb2 1736 }
929f69fa
JB		 1737 else if (x.bitfield.cpuavx512f)
1738 {
1739 /* We need to check a few extra flags with AVX512F. */
1740 if (cpu.bitfield.cpuavx512f
1741 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1742 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1743 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1744 match |= CPU_FLAGS_ARCH_MATCH;
1745 }
a5ff0eb2 1746 else
db12e14e 1747 match |= CPU_FLAGS_ARCH_MATCH;
c0f3af97 1748 }
3629bb00 1749 }
c0f3af97 1750 return match;
40fb9820
L		 1751}
1752
c6fb90c8
L		 1753static INLINE i386_operand_type
1754operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1755{
c6fb90c8
L		 1756 switch (ARRAY_SIZE (x.array))
1757 {
1758 case 3:
1759 x.array [2] &= y.array [2];
1a0670f3 1760 /* Fall through. */
c6fb90c8
L		 1761 case 2:
1762 x.array [1] &= y.array [1];
1a0670f3 1763 /* Fall through. */
c6fb90c8
L		 1764 case 1:
1765 x.array [0] &= y.array [0];
1766 break;
1767 default:
1768 abort ();
1769 }
1770 return x;
40fb9820
L		 1771}
1772
73053c1f
JB		 1773static INLINE i386_operand_type
1774operand_type_and_not (i386_operand_type x, i386_operand_type y)
1775{
1776 switch (ARRAY_SIZE (x.array))
1777 {
1778 case 3:
1779 x.array [2] &= ~y.array [2];
1780 /* Fall through. */
1781 case 2:
1782 x.array [1] &= ~y.array [1];
1783 /* Fall through. */
1784 case 1:
1785 x.array [0] &= ~y.array [0];
1786 break;
1787 default:
1788 abort ();
1789 }
1790 return x;
1791}
1792
c6fb90c8
L		 1793static INLINE i386_operand_type
1794operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1795{
c6fb90c8 1796 switch (ARRAY_SIZE (x.array))
40fb9820 1797 {
c6fb90c8
L		 1798 case 3:
1799 x.array [2] |= y.array [2];
1a0670f3 1800 /* Fall through. */
c6fb90c8
L		 1801 case 2:
1802 x.array [1] |= y.array [1];
1a0670f3 1803 /* Fall through. */
c6fb90c8
L		 1804 case 1:
1805 x.array [0] |= y.array [0];
40fb9820
L		 1806 break;
1807 default:
1808 abort ();
1809 }
c6fb90c8
L		 1810 return x;
1811}
40fb9820 1812
c6fb90c8
L		 1813static INLINE i386_operand_type
1814operand_type_xor (i386_operand_type x, i386_operand_type y)
1815{
1816 switch (ARRAY_SIZE (x.array))
1817 {
1818 case 3:
1819 x.array [2] ^= y.array [2];
1a0670f3 1820 /* Fall through. */
c6fb90c8
L		 1821 case 2:
1822 x.array [1] ^= y.array [1];
1a0670f3 1823 /* Fall through. */
c6fb90c8
L		 1824 case 1:
1825 x.array [0] ^= y.array [0];
1826 break;
1827 default:
1828 abort ();
1829 }
40fb9820
L		 1830 return x;
1831}
1832
1833static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1834static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
40fb9820
L		 1835static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1836static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1837static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1838static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1839static const i386_operand_type anydisp
1840 = OPERAND_TYPE_ANYDISP;
40fb9820 1841static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
43234a1e 1842static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1843static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1844static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1845static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1846static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1847static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1848static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1849static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1850static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1851static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1852static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1853
1854enum operand_type
1855{
1856 reg,
40fb9820
L		 1857 imm,
1858 disp,
1859 anymem
1860};
1861
c6fb90c8 1862static INLINE int
40fb9820
L		 1863operand_type_check (i386_operand_type t, enum operand_type c)
1864{
1865 switch (c)
1866 {
1867 case reg:
dc821c5f 1868 return t.bitfield.reg;
40fb9820 1869
40fb9820
L		 1870 case imm:
1871 return (t.bitfield.imm8
1872 || t.bitfield.imm8s
1873 || t.bitfield.imm16
1874 || t.bitfield.imm32
1875 || t.bitfield.imm32s
1876 || t.bitfield.imm64);
1877
1878 case disp:
1879 return (t.bitfield.disp8
1880 || t.bitfield.disp16
1881 || t.bitfield.disp32
1882 || t.bitfield.disp32s
1883 || t.bitfield.disp64);
1884
1885 case anymem:
1886 return (t.bitfield.disp8
1887 || t.bitfield.disp16
1888 || t.bitfield.disp32
1889 || t.bitfield.disp32s
1890 || t.bitfield.disp64
1891 || t.bitfield.baseindex);
1892
1893 default:
1894 abort ();
1895 }
2cfe26b6
AM		 1896
1897 return 0;
40fb9820
L		 1898}
1899
ca0d63fe 1900/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
5c07affc
L		 1901 operand J for instruction template T. */
1902
1903static INLINE int
3ac21baa 1904match_reg_size (const insn_template *t, unsigned int wanted, unsigned int given)
5c07affc 1905{
3ac21baa
JB		 1906 return !((i.types[given].bitfield.byte
1907 && !t->operand_types[wanted].bitfield.byte)
1908 || (i.types[given].bitfield.word
1909 && !t->operand_types[wanted].bitfield.word)
1910 || (i.types[given].bitfield.dword
1911 && !t->operand_types[wanted].bitfield.dword)
1912 || (i.types[given].bitfield.qword
1913 && !t->operand_types[wanted].bitfield.qword)
1914 || (i.types[given].bitfield.tbyte
1915 && !t->operand_types[wanted].bitfield.tbyte));
5c07affc
L		 1916}
1917
1b54b8d7
JB		 1918/* Return 1 if there is no conflict in SIMD register on
1919 operand J for instruction template T. */
1920
1921static INLINE int
3ac21baa 1922match_simd_size (const insn_template *t, unsigned int wanted, unsigned int given)
1b54b8d7 1923{
3ac21baa
JB		 1924 return !((i.types[given].bitfield.xmmword
1925 && !t->operand_types[wanted].bitfield.xmmword)
1926 || (i.types[given].bitfield.ymmword
1927 && !t->operand_types[wanted].bitfield.ymmword)
1928 || (i.types[given].bitfield.zmmword
1929 && !t->operand_types[wanted].bitfield.zmmword));
1b54b8d7
JB		 1930}
1931
5c07affc
L		 1932/* Return 1 if there is no conflict in any size on operand J for
1933 instruction template T. */
1934
1935static INLINE int
3ac21baa 1936match_mem_size (const insn_template *t, unsigned int wanted, unsigned int given)
5c07affc 1937{
3ac21baa
JB		 1938 return (match_reg_size (t, wanted, given)
1939 && !((i.types[given].bitfield.unspecified
af508cb9 1940 && !i.broadcast
3ac21baa
JB		 1941 && !t->operand_types[wanted].bitfield.unspecified)
1942 || (i.types[given].bitfield.fword
1943 && !t->operand_types[wanted].bitfield.fword)
1b54b8d7
JB		 1944 /* For scalar opcode templates to allow register and memory
1945 operands at the same time, some special casing is needed
d6793fa1
JB		 1946 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1947 down-conversion vpmov*. */
3ac21baa 1948 || ((t->operand_types[wanted].bitfield.regsimd
1b54b8d7 1949 && !t->opcode_modifier.broadcast
3ac21baa
JB		 1950 && (t->operand_types[wanted].bitfield.byte
1951 || t->operand_types[wanted].bitfield.word
1952 || t->operand_types[wanted].bitfield.dword
1953 || t->operand_types[wanted].bitfield.qword))
1954 ? (i.types[given].bitfield.xmmword
1955 || i.types[given].bitfield.ymmword
1956 || i.types[given].bitfield.zmmword)
1957 : !match_simd_size(t, wanted, given))));
5c07affc
L		 1958}
1959
3ac21baa
JB		 1960/* Return value has MATCH_STRAIGHT set if there is no size conflict on any
1961 operands for instruction template T, and it has MATCH_REVERSE set if there
1962 is no size conflict on any operands for the template with operands reversed
1963 (and the template allows for reversing in the first place). */
5c07affc 1964
3ac21baa
JB		 1965#define MATCH_STRAIGHT 1
1966#define MATCH_REVERSE 2
1967
1968static INLINE unsigned int
d3ce72d0 1969operand_size_match (const insn_template *t)
5c07affc 1970{
3ac21baa 1971 unsigned int j, match = MATCH_STRAIGHT;
5c07affc
L		 1972
1973 /* Don't check jump instructions. */
1974 if (t->opcode_modifier.jump
1975 || t->opcode_modifier.jumpbyte
1976 || t->opcode_modifier.jumpdword
1977 || t->opcode_modifier.jumpintersegment)
1978 return match;
1979
1980 /* Check memory and accumulator operand size. */
1981 for (j = 0; j < i.operands; j++)
1982 {
1b54b8d7
JB		 1983 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1984 && t->operand_types[j].bitfield.anysize)
5c07affc
L		 1985 continue;
1986
1b54b8d7 1987 if (t->operand_types[j].bitfield.reg
3ac21baa 1988 && !match_reg_size (t, j, j))
5c07affc
L		 1989 {
1990 match = 0;
1991 break;
1992 }
1993
1b54b8d7 1994 if (t->operand_types[j].bitfield.regsimd
3ac21baa 1995 && !match_simd_size (t, j, j))
1b54b8d7
JB		 1996 {
1997 match = 0;
1998 break;
1999 }
2000
2001 if (t->operand_types[j].bitfield.acc
3ac21baa 2002 && (!match_reg_size (t, j, j) || !match_simd_size (t, j, j)))
1b54b8d7
JB		 2003 {
2004 match = 0;
2005 break;
2006 }
2007
3ac21baa 2008 if (i.types[j].bitfield.mem && !match_mem_size (t, j, j))
5c07affc
L		 2009 {
2010 match = 0;
2011 break;
2012 }
2013 }
2014
3ac21baa 2015 if (!t->opcode_modifier.d)
891edac4
L		 2016 {
2017mismatch:
3ac21baa
JB		 2018 if (!match)
2019 i.error = operand_size_mismatch;
2020 return match;
891edac4 2021 }
5c07affc
L		 2022
2023 /* Check reverse. */
9c2799c2 2024 gas_assert (i.operands == 2);
5c07affc 2025
5c07affc
L		 2026 for (j = 0; j < 2; j++)
2027 {
dc821c5f
JB		 2028 if ((t->operand_types[j].bitfield.reg
2029 || t->operand_types[j].bitfield.acc)
3ac21baa 2030 && !match_reg_size (t, j, !j))
891edac4 2031 goto mismatch;
5c07affc 2032
3ac21baa
JB		 2033 if (i.types[!j].bitfield.mem
2034 && !match_mem_size (t, j, !j))
891edac4 2035 goto mismatch;
5c07affc
L		 2036 }
2037
3ac21baa 2038 return match | MATCH_REVERSE;
5c07affc
L		 2039}
2040
c6fb90c8 2041static INLINE int
40fb9820
L		 2042operand_type_match (i386_operand_type overlap,
2043 i386_operand_type given)
2044{
2045 i386_operand_type temp = overlap;
2046
2047 temp.bitfield.jumpabsolute = 0;
7d5e4556 2048 temp.bitfield.unspecified = 0;
5c07affc
L		 2049 temp.bitfield.byte = 0;
2050 temp.bitfield.word = 0;
2051 temp.bitfield.dword = 0;
2052 temp.bitfield.fword = 0;
2053 temp.bitfield.qword = 0;
2054 temp.bitfield.tbyte = 0;
2055 temp.bitfield.xmmword = 0;
c0f3af97 2056 temp.bitfield.ymmword = 0;
43234a1e 2057 temp.bitfield.zmmword = 0;
0dfbf9d7 2058 if (operand_type_all_zero (&temp))
891edac4 2059 goto mismatch;
40fb9820 2060
891edac4
L		 2061 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2062 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2063 return 1;
2064
2065mismatch:
a65babc9 2066 i.error = operand_type_mismatch;
891edac4 2067 return 0;
40fb9820
L		 2068}
2069
7d5e4556 2070/* If given types g0 and g1 are registers they must be of the same type
10c17abd
JB		 2071 unless the expected operand type register overlap is null.
2072 Memory operand size of certain SIMD instructions is also being checked
2073 here. */
40fb9820 2074
c6fb90c8 2075static INLINE int
dc821c5f 2076operand_type_register_match (i386_operand_type g0,
40fb9820 2077 i386_operand_type t0,
40fb9820
L		 2078 i386_operand_type g1,
2079 i386_operand_type t1)
2080{
10c17abd
JB		 2081 if (!g0.bitfield.reg
2082 && !g0.bitfield.regsimd
2083 && (!operand_type_check (g0, anymem)
2084 || g0.bitfield.unspecified
2085 || !t0.bitfield.regsimd))
40fb9820
L		 2086 return 1;
2087
10c17abd
JB		 2088 if (!g1.bitfield.reg
2089 && !g1.bitfield.regsimd
2090 && (!operand_type_check (g1, anymem)
2091 || g1.bitfield.unspecified
2092 || !t1.bitfield.regsimd))
40fb9820
L		 2093 return 1;
2094
dc821c5f
JB		 2095 if (g0.bitfield.byte == g1.bitfield.byte
2096 && g0.bitfield.word == g1.bitfield.word
2097 && g0.bitfield.dword == g1.bitfield.dword
10c17abd
JB		 2098 && g0.bitfield.qword == g1.bitfield.qword
2099 && g0.bitfield.xmmword == g1.bitfield.xmmword
2100 && g0.bitfield.ymmword == g1.bitfield.ymmword
2101 && g0.bitfield.zmmword == g1.bitfield.zmmword)
40fb9820
L		 2102 return 1;
2103
dc821c5f
JB		 2104 if (!(t0.bitfield.byte & t1.bitfield.byte)
2105 && !(t0.bitfield.word & t1.bitfield.word)
2106 && !(t0.bitfield.dword & t1.bitfield.dword)
10c17abd
JB		 2107 && !(t0.bitfield.qword & t1.bitfield.qword)
2108 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2109 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2110 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
891edac4
L		 2111 return 1;
2112
a65babc9 2113 i.error = register_type_mismatch;
891edac4
L		 2114
2115 return 0;
40fb9820
L		 2116}
2117
4c692bc7
JB		 2118static INLINE unsigned int
2119register_number (const reg_entry *r)
2120{
2121 unsigned int nr = r->reg_num;
2122
2123 if (r->reg_flags & RegRex)
2124 nr += 8;
2125
200cbe0f
L		 2126 if (r->reg_flags & RegVRex)
2127 nr += 16;
2128
4c692bc7
JB		 2129 return nr;
2130}
2131
252b5132 2132static INLINE unsigned int
40fb9820 2133mode_from_disp_size (i386_operand_type t)
252b5132 2134{
b5014f7a 2135 if (t.bitfield.disp8)
40fb9820
L		 2136 return 1;
2137 else if (t.bitfield.disp16
2138 || t.bitfield.disp32
2139 || t.bitfield.disp32s)
2140 return 2;
2141 else
2142 return 0;
252b5132
RH		 2143}
2144
2145static INLINE int
65879393 2146fits_in_signed_byte (addressT num)
252b5132 2147{
65879393 2148 return num + 0x80 <= 0xff;
47926f60 2149}
252b5132
RH		 2150
2151static INLINE int
65879393 2152fits_in_unsigned_byte (addressT num)
252b5132 2153{
65879393 2154 return num <= 0xff;
47926f60 2155}
252b5132
RH		 2156
2157static INLINE int
65879393 2158fits_in_unsigned_word (addressT num)
252b5132 2159{
65879393 2160 return num <= 0xffff;
47926f60 2161}
252b5132
RH		 2162
2163static INLINE int
65879393 2164fits_in_signed_word (addressT num)
252b5132 2165{
65879393 2166 return num + 0x8000 <= 0xffff;
47926f60 2167}
2a962e6d 2168
3e73aa7c 2169static INLINE int
65879393 2170fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2171{
2172#ifndef BFD64
2173 return 1;
2174#else
65879393 2175 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 2176#endif
2177} /* fits_in_signed_long() */
2a962e6d 2178
3e73aa7c 2179static INLINE int
65879393 2180fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2181{
2182#ifndef BFD64
2183 return 1;
2184#else
65879393 2185 return num <= 0xffffffff;
3e73aa7c
JH		 2186#endif
2187} /* fits_in_unsigned_long() */
252b5132 2188
43234a1e 2189static INLINE int
b5014f7a 2190fits_in_disp8 (offsetT num)
43234a1e
L		 2191{
2192 int shift = i.memshift;
2193 unsigned int mask;
2194
2195 if (shift == -1)
2196 abort ();
2197
2198 mask = (1 << shift) - 1;
2199
2200 /* Return 0 if NUM isn't properly aligned. */
2201 if ((num & mask))
2202 return 0;
2203
2204 /* Check if NUM will fit in 8bit after shift. */
2205 return fits_in_signed_byte (num >> shift);
2206}
2207
a683cc34
SP		 2208static INLINE int
2209fits_in_imm4 (offsetT num)
2210{
2211 return (num & 0xf) == num;
2212}
2213
40fb9820 2214static i386_operand_type
e3bb37b5 2215smallest_imm_type (offsetT num)
252b5132 2216{
40fb9820 2217 i386_operand_type t;
7ab9ffdd 2218
0dfbf9d7 2219 operand_type_set (&t, 0);
40fb9820
L		 2220 t.bitfield.imm64 = 1;
2221
2222 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2223 {
2224 /* This code is disabled on the 486 because all the Imm1 forms
2225 in the opcode table are slower on the i486. They're the
2226 versions with the implicitly specified single-position
2227 displacement, which has another syntax if you really want to
2228 use that form. */
40fb9820
L		 2229 t.bitfield.imm1 = 1;
2230 t.bitfield.imm8 = 1;
2231 t.bitfield.imm8s = 1;
2232 t.bitfield.imm16 = 1;
2233 t.bitfield.imm32 = 1;
2234 t.bitfield.imm32s = 1;
2235 }
2236 else if (fits_in_signed_byte (num))
2237 {
2238 t.bitfield.imm8 = 1;
2239 t.bitfield.imm8s = 1;
2240 t.bitfield.imm16 = 1;
2241 t.bitfield.imm32 = 1;
2242 t.bitfield.imm32s = 1;
2243 }
2244 else if (fits_in_unsigned_byte (num))
2245 {
2246 t.bitfield.imm8 = 1;
2247 t.bitfield.imm16 = 1;
2248 t.bitfield.imm32 = 1;
2249 t.bitfield.imm32s = 1;
2250 }
2251 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2252 {
2253 t.bitfield.imm16 = 1;
2254 t.bitfield.imm32 = 1;
2255 t.bitfield.imm32s = 1;
2256 }
2257 else if (fits_in_signed_long (num))
2258 {
2259 t.bitfield.imm32 = 1;
2260 t.bitfield.imm32s = 1;
2261 }
2262 else if (fits_in_unsigned_long (num))
2263 t.bitfield.imm32 = 1;
2264
2265 return t;
47926f60 2266}
252b5132 2267
847f7ad4 2268static offsetT
e3bb37b5 2269offset_in_range (offsetT val, int size)
847f7ad4 2270{
508866be 2271 addressT mask;
ba2adb93 2272
847f7ad4
AM		 2273 switch (size)
2274 {
508866be
L		 2275 case 1: mask = ((addressT) 1 << 8) - 1; break;
2276 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2277 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2278#ifdef BFD64
2279 case 8: mask = ((addressT) 2 << 63) - 1; break;
2280#endif
47926f60 2281 default: abort ();
847f7ad4
AM		 2282 }
2283
9de868bf
L		 2284#ifdef BFD64
2285 /* If BFD64, sign extend val for 32bit address mode. */
2286 if (flag_code != CODE_64BIT
2287 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2288 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2289 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2290#endif
ba2adb93 2291
47926f60 2292 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2293 {
2294 char buf1[40], buf2[40];
2295
2296 sprint_value (buf1, val);
2297 sprint_value (buf2, val & mask);
2298 as_warn (_("%s shortened to %s"), buf1, buf2);
2299 }
2300 return val & mask;
2301}
2302
c32fa91d
L		 2303enum PREFIX_GROUP
2304{
2305 PREFIX_EXIST = 0,
2306 PREFIX_LOCK,
2307 PREFIX_REP,
04ef582a 2308 PREFIX_DS,
c32fa91d
L		 2309 PREFIX_OTHER
2310};
2311
2312/* Returns
2313 a. PREFIX_EXIST if attempting to add a prefix where one from the
2314 same class already exists.
2315 b. PREFIX_LOCK if lock prefix is added.
2316 c. PREFIX_REP if rep/repne prefix is added.
04ef582a
L		 2317 d. PREFIX_DS if ds prefix is added.
2318 e. PREFIX_OTHER if other prefix is added.
c32fa91d
L		 2319 */
2320
2321static enum PREFIX_GROUP
e3bb37b5 2322add_prefix (unsigned int prefix)
252b5132 2323{
c32fa91d 2324 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2325 unsigned int q;
252b5132 2326
29b0f896
AM		 2327 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2328 && flag_code == CODE_64BIT)
b1905489 2329 {
161a04f6 2330 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
44846f29
JB		 2331 || (i.prefix[REX_PREFIX] & prefix & REX_R)
2332 || (i.prefix[REX_PREFIX] & prefix & REX_X)
2333 || (i.prefix[REX_PREFIX] & prefix & REX_B))
c32fa91d 2334 ret = PREFIX_EXIST;
b1905489
JB		 2335 q = REX_PREFIX;
2336 }
3e73aa7c 2337 else
b1905489
JB		 2338 {
2339 switch (prefix)
2340 {
2341 default:
2342 abort ();
2343
b1905489 2344 case DS_PREFIX_OPCODE:
04ef582a
L		 2345 ret = PREFIX_DS;
2346 /* Fall through. */
2347 case CS_PREFIX_OPCODE:
b1905489
JB		 2348 case ES_PREFIX_OPCODE:
2349 case FS_PREFIX_OPCODE:
2350 case GS_PREFIX_OPCODE:
2351 case SS_PREFIX_OPCODE:
2352 q = SEG_PREFIX;
2353 break;
2354
2355 case REPNE_PREFIX_OPCODE:
2356 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2357 q = REP_PREFIX;
2358 ret = PREFIX_REP;
2359 break;
2360
b1905489 2361 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2362 q = LOCK_PREFIX;
2363 ret = PREFIX_LOCK;
b1905489
JB		 2364 break;
2365
2366 case FWAIT_OPCODE:
2367 q = WAIT_PREFIX;
2368 break;
2369
2370 case ADDR_PREFIX_OPCODE:
2371 q = ADDR_PREFIX;
2372 break;
2373
2374 case DATA_PREFIX_OPCODE:
2375 q = DATA_PREFIX;
2376 break;
2377 }
2378 if (i.prefix[q] != 0)
c32fa91d 2379 ret = PREFIX_EXIST;
b1905489 2380 }
252b5132 2381
b1905489 2382 if (ret)
252b5132 2383 {
b1905489
JB		 2384 if (!i.prefix[q])
2385 ++i.prefixes;
2386 i.prefix[q] |= prefix;
252b5132 2387 }
b1905489
JB		 2388 else
2389 as_bad (_("same type of prefix used twice"));
252b5132 2390
252b5132
RH		 2391 return ret;
2392}
2393
2394static void
78f12dd3 2395update_code_flag (int value, int check)
eecb386c 2396{
78f12dd3
L		 2397 PRINTF_LIKE ((*as_error));
2398
1e9cc1c2 2399 flag_code = (enum flag_code) value;
40fb9820
L		 2400 if (flag_code == CODE_64BIT)
2401 {
2402 cpu_arch_flags.bitfield.cpu64 = 1;
2403 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2404 }
2405 else
2406 {
2407 cpu_arch_flags.bitfield.cpu64 = 0;
2408 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2409 }
2410 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2411 {
78f12dd3
L		 2412 if (check)
2413 as_error = as_fatal;
2414 else
2415 as_error = as_bad;
2416 (*as_error) (_("64bit mode not supported on `%s'."),
2417 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2418 }
40fb9820 2419 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2420 {
78f12dd3
L		 2421 if (check)
2422 as_error = as_fatal;
2423 else
2424 as_error = as_bad;
2425 (*as_error) (_("32bit mode not supported on `%s'."),
2426 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2427 }
eecb386c
AM		 2428 stackop_size = '\0';
2429}
2430
78f12dd3
L		 2431static void
2432set_code_flag (int value)
2433{
2434 update_code_flag (value, 0);
2435}
2436
eecb386c 2437static void
e3bb37b5 2438set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2439{
1e9cc1c2 2440 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2441 if (flag_code != CODE_16BIT)
2442 abort ();
2443 cpu_arch_flags.bitfield.cpu64 = 0;
2444 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2445 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2446}
2447
2448static void
e3bb37b5 2449set_intel_syntax (int syntax_flag)
252b5132
RH		 2450{
2451 /* Find out if register prefixing is specified. */
2452 int ask_naked_reg = 0;
2453
2454 SKIP_WHITESPACE ();
29b0f896 2455 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2456 {
d02603dc
NC		 2457 char *string;
2458 int e = get_symbol_name (&string);
252b5132 2459
47926f60 2460 if (strcmp (string, "prefix") == 0)
252b5132 2461 ask_naked_reg = 1;
47926f60 2462 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2463 ask_naked_reg = -1;
2464 else
d0b47220 2465 as_bad (_("bad argument to syntax directive."));
d02603dc 2466 (void) restore_line_pointer (e);
252b5132
RH		 2467 }
2468 demand_empty_rest_of_line ();
c3332e24 2469
252b5132
RH		 2470 intel_syntax = syntax_flag;
2471
2472 if (ask_naked_reg == 0)
f86103b7
AM		 2473 allow_naked_reg = (intel_syntax
2474 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2475 else
2476 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2477
ee86248c 2478 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2479
e4a3b5a4 2480 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2481 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2482 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2483}
2484
1efbbeb4
L		 2485static void
2486set_intel_mnemonic (int mnemonic_flag)
2487{
e1d4d893 2488 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2489}
2490
db51cc60
L		 2491static void
2492set_allow_index_reg (int flag)
2493{
2494 allow_index_reg = flag;
2495}
2496
cb19c032 2497static void
7bab8ab5 2498set_check (int what)
cb19c032 2499{
7bab8ab5
JB		 2500 enum check_kind *kind;
2501 const char *str;
2502
2503 if (what)
2504 {
2505 kind = &operand_check;
2506 str = "operand";
2507 }
2508 else
2509 {
2510 kind = &sse_check;
2511 str = "sse";
2512 }
2513
cb19c032
L		 2514 SKIP_WHITESPACE ();
2515
2516 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2517 {
d02603dc
NC		 2518 char *string;
2519 int e = get_symbol_name (&string);
cb19c032
L		 2520
2521 if (strcmp (string, "none") == 0)
7bab8ab5 2522 *kind = check_none;
cb19c032 2523 else if (strcmp (string, "warning") == 0)
7bab8ab5 2524 *kind = check_warning;
cb19c032 2525 else if (strcmp (string, "error") == 0)
7bab8ab5 2526 *kind = check_error;
cb19c032 2527 else
7bab8ab5 2528 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2529 (void) restore_line_pointer (e);
cb19c032
L		 2530 }
2531 else
7bab8ab5 2532 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2533
2534 demand_empty_rest_of_line ();
2535}
2536
8a9036a4
L		 2537static void
2538check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2539 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2540{
2541#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2542 static const char *arch;
2543
2544 /* Intel LIOM is only supported on ELF. */
2545 if (!IS_ELF)
2546 return;
2547
2548 if (!arch)
2549 {
2550 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2551 use default_arch. */
2552 arch = cpu_arch_name;
2553 if (!arch)
2554 arch = default_arch;
2555 }
2556
81486035
L		 2557 /* If we are targeting Intel MCU, we must enable it. */
2558 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2559 || new_flag.bitfield.cpuiamcu)
2560 return;
2561
3632d14b 2562 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2563 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2564 || new_flag.bitfield.cpul1om)
8a9036a4 2565 return;
76ba9986 2566
7a9068fe
L		 2567 /* If we are targeting Intel K1OM, we must enable it. */
2568 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2569 || new_flag.bitfield.cpuk1om)
2570 return;
2571
8a9036a4
L		 2572 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2573#endif
2574}
2575
e413e4e9 2576static void
e3bb37b5 2577set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2578{
47926f60 2579 SKIP_WHITESPACE ();
e413e4e9 2580
29b0f896 2581 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2582 {
d02603dc
NC		 2583 char *string;
2584 int e = get_symbol_name (&string);
91d6fa6a 2585 unsigned int j;
40fb9820 2586 i386_cpu_flags flags;
e413e4e9 2587
91d6fa6a 2588 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2589 {
91d6fa6a 2590 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2591 {
91d6fa6a 2592 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2593
5c6af06e
JB		 2594 if (*string != '.')
2595 {
91d6fa6a 2596 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2597 cpu_sub_arch_name = NULL;
91d6fa6a 2598 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2599 if (flag_code == CODE_64BIT)
2600 {
2601 cpu_arch_flags.bitfield.cpu64 = 1;
2602 cpu_arch_flags.bitfield.cpuno64 = 0;
2603 }
2604 else
2605 {
2606 cpu_arch_flags.bitfield.cpu64 = 0;
2607 cpu_arch_flags.bitfield.cpuno64 = 1;
2608 }
91d6fa6a
NC		 2609 cpu_arch_isa = cpu_arch[j].type;
2610 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2611 if (!cpu_arch_tune_set)
2612 {
2613 cpu_arch_tune = cpu_arch_isa;
2614 cpu_arch_tune_flags = cpu_arch_isa_flags;
2615 }
5c6af06e
JB		 2616 break;
2617 }
40fb9820 2618
293f5f65
L		 2619 flags = cpu_flags_or (cpu_arch_flags,
2620 cpu_arch[j].flags);
81486035 2621
5b64d091 2622 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2623 {
6305a203
L		 2624 if (cpu_sub_arch_name)
2625 {
2626 char *name = cpu_sub_arch_name;
2627 cpu_sub_arch_name = concat (name,
91d6fa6a 2628 cpu_arch[j].name,
1bf57e9f 2629 (const char *) NULL);
6305a203
L		 2630 free (name);
2631 }
2632 else
91d6fa6a 2633 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2634 cpu_arch_flags = flags;
a586129e 2635 cpu_arch_isa_flags = flags;
5c6af06e 2636 }
0089dace
L		 2637 else
2638 cpu_arch_isa_flags
2639 = cpu_flags_or (cpu_arch_isa_flags,
2640 cpu_arch[j].flags);
d02603dc 2641 (void) restore_line_pointer (e);
5c6af06e
JB		 2642 demand_empty_rest_of_line ();
2643 return;
e413e4e9
AM		 2644 }
2645 }
293f5f65
L		 2646
2647 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2648 {
33eaf5de 2649 /* Disable an ISA extension. */
293f5f65
L		 2650 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2651 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2652 {
2653 flags = cpu_flags_and_not (cpu_arch_flags,
2654 cpu_noarch[j].flags);
2655 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2656 {
2657 if (cpu_sub_arch_name)
2658 {
2659 char *name = cpu_sub_arch_name;
2660 cpu_sub_arch_name = concat (name, string,
2661 (const char *) NULL);
2662 free (name);
2663 }
2664 else
2665 cpu_sub_arch_name = xstrdup (string);
2666 cpu_arch_flags = flags;
2667 cpu_arch_isa_flags = flags;
2668 }
2669 (void) restore_line_pointer (e);
2670 demand_empty_rest_of_line ();
2671 return;
2672 }
2673
2674 j = ARRAY_SIZE (cpu_arch);
2675 }
2676
91d6fa6a 2677 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2678 as_bad (_("no such architecture: `%s'"), string);
2679
2680 *input_line_pointer = e;
2681 }
2682 else
2683 as_bad (_("missing cpu architecture"));
2684
fddf5b5b
AM		 2685 no_cond_jump_promotion = 0;
2686 if (*input_line_pointer == ','
29b0f896 2687 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2688 {
d02603dc
NC		 2689 char *string;
2690 char e;
2691
2692 ++input_line_pointer;
2693 e = get_symbol_name (&string);
fddf5b5b
AM		 2694
2695 if (strcmp (string, "nojumps") == 0)
2696 no_cond_jump_promotion = 1;
2697 else if (strcmp (string, "jumps") == 0)
2698 ;
2699 else
2700 as_bad (_("no such architecture modifier: `%s'"), string);
2701
d02603dc 2702 (void) restore_line_pointer (e);
fddf5b5b
AM		 2703 }
2704
e413e4e9
AM		 2705 demand_empty_rest_of_line ();
2706}
2707
8a9036a4
L		 2708enum bfd_architecture
2709i386_arch (void)
2710{
3632d14b 2711 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2712 {
2713 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2714 || flag_code != CODE_64BIT)
2715 as_fatal (_("Intel L1OM is 64bit ELF only"));
2716 return bfd_arch_l1om;
2717 }
7a9068fe
L		 2718 else if (cpu_arch_isa == PROCESSOR_K1OM)
2719 {
2720 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2721 || flag_code != CODE_64BIT)
2722 as_fatal (_("Intel K1OM is 64bit ELF only"));
2723 return bfd_arch_k1om;
2724 }
81486035
L		 2725 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2726 {
2727 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2728 || flag_code == CODE_64BIT)
2729 as_fatal (_("Intel MCU is 32bit ELF only"));
2730 return bfd_arch_iamcu;
2731 }
8a9036a4
L		 2732 else
2733 return bfd_arch_i386;
2734}
2735
b9d79e03 2736unsigned long
7016a5d5 2737i386_mach (void)
b9d79e03 2738{
351f65ca 2739 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2740 {
3632d14b 2741 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2742 {
351f65ca
L		 2743 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2744 || default_arch[6] != '\0')
8a9036a4
L		 2745 as_fatal (_("Intel L1OM is 64bit ELF only"));
2746 return bfd_mach_l1om;
2747 }
7a9068fe
L		 2748 else if (cpu_arch_isa == PROCESSOR_K1OM)
2749 {
2750 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2751 || default_arch[6] != '\0')
2752 as_fatal (_("Intel K1OM is 64bit ELF only"));
2753 return bfd_mach_k1om;
2754 }
351f65ca 2755 else if (default_arch[6] == '\0')
8a9036a4 2756 return bfd_mach_x86_64;
351f65ca
L		 2757 else
2758 return bfd_mach_x64_32;
8a9036a4 2759 }
5197d474
L		 2760 else if (!strcmp (default_arch, "i386")
2761 || !strcmp (default_arch, "iamcu"))
81486035
L		 2762 {
2763 if (cpu_arch_isa == PROCESSOR_IAMCU)
2764 {
2765 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2766 as_fatal (_("Intel MCU is 32bit ELF only"));
2767 return bfd_mach_i386_iamcu;
2768 }
2769 else
2770 return bfd_mach_i386_i386;
2771 }
b9d79e03 2772 else
2b5d6a91 2773 as_fatal (_("unknown architecture"));
b9d79e03 2774}
b9d79e03 2775\f
252b5132 2776void
7016a5d5 2777md_begin (void)
252b5132
RH		 2778{
2779 const char *hash_err;
2780
86fa6981
L		 2781 /* Support pseudo prefixes like {disp32}. */
2782 lex_type ['{'] = LEX_BEGIN_NAME;
2783
47926f60 2784 /* Initialize op_hash hash table. */
252b5132
RH		 2785 op_hash = hash_new ();
2786
2787 {
d3ce72d0 2788 const insn_template *optab;
29b0f896 2789 templates *core_optab;
252b5132 2790
47926f60
KH		 2791 /* Setup for loop. */
2792 optab = i386_optab;
add39d23 2793 core_optab = XNEW (templates);
252b5132
RH		 2794 core_optab->start = optab;
2795
2796 while (1)
2797 {
2798 ++optab;
2799 if (optab->name == NULL
2800 || strcmp (optab->name, (optab - 1)->name) != 0)
2801 {
2802 /* different name --> ship out current template list;
47926f60 2803 add to hash table; & begin anew. */
252b5132
RH		 2804 core_optab->end = optab;
2805 hash_err = hash_insert (op_hash,
2806 (optab - 1)->name,
5a49b8ac 2807 (void *) core_optab);
252b5132
RH		 2808 if (hash_err)
2809 {
b37df7c4 2810 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2811 (optab - 1)->name,
2812 hash_err);
2813 }
2814 if (optab->name == NULL)
2815 break;
add39d23 2816 core_optab = XNEW (templates);
252b5132
RH		 2817 core_optab->start = optab;
2818 }
2819 }
2820 }
2821
47926f60 2822 /* Initialize reg_hash hash table. */
252b5132
RH		 2823 reg_hash = hash_new ();
2824 {
29b0f896 2825 const reg_entry *regtab;
c3fe08fa 2826 unsigned int regtab_size = i386_regtab_size;
252b5132 2827
c3fe08fa 2828 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2829 {
5a49b8ac 2830 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2831 if (hash_err)
b37df7c4 2832 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2833 regtab->reg_name,
2834 hash_err);
252b5132
RH		 2835 }
2836 }
2837
47926f60 2838 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2839 {
29b0f896
AM		 2840 int c;
2841 char *p;
252b5132
RH		 2842
2843 for (c = 0; c < 256; c++)
2844 {
3882b010 2845 if (ISDIGIT (c))
252b5132
RH		 2846 {
2847 digit_chars[c] = c;
2848 mnemonic_chars[c] = c;
2849 register_chars[c] = c;
2850 operand_chars[c] = c;
2851 }
3882b010 2852 else if (ISLOWER (c))
252b5132
RH		 2853 {
2854 mnemonic_chars[c] = c;
2855 register_chars[c] = c;
2856 operand_chars[c] = c;
2857 }
3882b010 2858 else if (ISUPPER (c))
252b5132 2859 {
3882b010 2860 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2861 register_chars[c] = mnemonic_chars[c];
2862 operand_chars[c] = c;
2863 }
43234a1e 2864 else if (c == '{' || c == '}')
86fa6981
L		 2865 {
2866 mnemonic_chars[c] = c;
2867 operand_chars[c] = c;
2868 }
252b5132 2869
3882b010 2870 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2871 identifier_chars[c] = c;
2872 else if (c >= 128)
2873 {
2874 identifier_chars[c] = c;
2875 operand_chars[c] = c;
2876 }
2877 }
2878
2879#ifdef LEX_AT
2880 identifier_chars['@'] = '@';
32137342
NC		 2881#endif
2882#ifdef LEX_QM
2883 identifier_chars['?'] = '?';
2884 operand_chars['?'] = '?';
252b5132 2885#endif
252b5132 2886 digit_chars['-'] = '-';
c0f3af97 2887 mnemonic_chars['_'] = '_';
791fe849 2888 mnemonic_chars['-'] = '-';
0003779b 2889 mnemonic_chars['.'] = '.';
252b5132
RH		 2890 identifier_chars['_'] = '_';
2891 identifier_chars['.'] = '.';
2892
2893 for (p = operand_special_chars; *p != '\0'; p++)
2894 operand_chars[(unsigned char) *p] = *p;
2895 }
2896
a4447b93
RH		 2897 if (flag_code == CODE_64BIT)
2898 {
ca19b261
KT		 2899#if defined (OBJ_COFF) && defined (TE_PE)
2900 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2901 ? 32 : 16);
2902#else
a4447b93 2903 x86_dwarf2_return_column = 16;
ca19b261 2904#endif
61ff971f 2905 x86_cie_data_alignment = -8;
a4447b93
RH		 2906 }
2907 else
2908 {
2909 x86_dwarf2_return_column = 8;
2910 x86_cie_data_alignment = -4;
2911 }
252b5132
RH		 2912}
2913
2914void
e3bb37b5 2915i386_print_statistics (FILE *file)
252b5132
RH		 2916{
2917 hash_print_statistics (file, "i386 opcode", op_hash);
2918 hash_print_statistics (file, "i386 register", reg_hash);
2919}
2920\f
252b5132
RH		 2921#ifdef DEBUG386
2922
ce8a8b2f 2923/* Debugging routines for md_assemble. */
d3ce72d0 2924static void pte (insn_template *);
40fb9820 2925static void pt (i386_operand_type);
e3bb37b5
L		 2926static void pe (expressionS *);
2927static void ps (symbolS *);
252b5132
RH		 2928
2929static void
e3bb37b5 2930pi (char *line, i386_insn *x)
252b5132 2931{
09137c09 2932 unsigned int j;
252b5132
RH		 2933
2934 fprintf (stdout, "%s: template ", line);
2935 pte (&x->tm);
09f131f2
JH		 2936 fprintf (stdout, " address: base %s index %s scale %x\n",
2937 x->base_reg ? x->base_reg->reg_name : "none",
2938 x->index_reg ? x->index_reg->reg_name : "none",
2939 x->log2_scale_factor);
2940 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2941 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2942 fprintf (stdout, " sib: base %x index %x scale %x\n",
2943 x->sib.base, x->sib.index, x->sib.scale);
2944 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2945 (x->rex & REX_W) != 0,
2946 (x->rex & REX_R) != 0,
2947 (x->rex & REX_X) != 0,
2948 (x->rex & REX_B) != 0);
09137c09 2949 for (j = 0; j < x->operands; j++)
252b5132 2950 {
09137c09
SP		 2951 fprintf (stdout, " #%d: ", j + 1);
2952 pt (x->types[j]);
252b5132 2953 fprintf (stdout, "\n");
dc821c5f 2954 if (x->types[j].bitfield.reg
09137c09 2955 || x->types[j].bitfield.regmmx
1b54b8d7 2956 || x->types[j].bitfield.regsimd
09137c09
SP		 2957 || x->types[j].bitfield.sreg2
2958 || x->types[j].bitfield.sreg3
2959 || x->types[j].bitfield.control
2960 || x->types[j].bitfield.debug
2961 || x->types[j].bitfield.test)
2962 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2963 if (operand_type_check (x->types[j], imm))
2964 pe (x->op[j].imms);
2965 if (operand_type_check (x->types[j], disp))
2966 pe (x->op[j].disps);
252b5132
RH		 2967 }
2968}
2969
2970static void
d3ce72d0 2971pte (insn_template *t)
252b5132 2972{
09137c09 2973 unsigned int j;
252b5132 2974 fprintf (stdout, " %d operands ", t->operands);
47926f60 2975 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2976 if (t->extension_opcode != None)
2977 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2978 if (t->opcode_modifier.d)
252b5132 2979 fprintf (stdout, "D");
40fb9820 2980 if (t->opcode_modifier.w)
252b5132
RH		 2981 fprintf (stdout, "W");
2982 fprintf (stdout, "\n");
09137c09 2983 for (j = 0; j < t->operands; j++)
252b5132 2984 {
09137c09
SP		 2985 fprintf (stdout, " #%d type ", j + 1);
2986 pt (t->operand_types[j]);
252b5132
RH		 2987 fprintf (stdout, "\n");
2988 }
2989}
2990
2991static void
e3bb37b5 2992pe (expressionS *e)
252b5132 2993{
24eab124 2994 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2995 fprintf (stdout, " add_number %ld (%lx)\n",
2996 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2997 if (e->X_add_symbol)
2998 {
2999 fprintf (stdout, " add_symbol ");
3000 ps (e->X_add_symbol);
3001 fprintf (stdout, "\n");
3002 }
3003 if (e->X_op_symbol)
3004 {
3005 fprintf (stdout, " op_symbol ");
3006 ps (e->X_op_symbol);
3007 fprintf (stdout, "\n");
3008 }
3009}
3010
3011static void
e3bb37b5 3012ps (symbolS *s)
252b5132
RH		 3013{
3014 fprintf (stdout, "%s type %s%s",
3015 S_GET_NAME (s),
3016 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3017 segment_name (S_GET_SEGMENT (s)));
3018}
3019
7b81dfbb 3020static struct type_name
252b5132 3021 {
40fb9820
L		 3022 i386_operand_type mask;
3023 const char *name;
252b5132 3024 }
7b81dfbb 3025const type_names[] =
252b5132 3026{
40fb9820
L		 3027 { OPERAND_TYPE_REG8, "r8" },
3028 { OPERAND_TYPE_REG16, "r16" },
3029 { OPERAND_TYPE_REG32, "r32" },
3030 { OPERAND_TYPE_REG64, "r64" },
3031 { OPERAND_TYPE_IMM8, "i8" },
3032 { OPERAND_TYPE_IMM8, "i8s" },
3033 { OPERAND_TYPE_IMM16, "i16" },
3034 { OPERAND_TYPE_IMM32, "i32" },
3035 { OPERAND_TYPE_IMM32S, "i32s" },
3036 { OPERAND_TYPE_IMM64, "i64" },
3037 { OPERAND_TYPE_IMM1, "i1" },
3038 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3039 { OPERAND_TYPE_DISP8, "d8" },
3040 { OPERAND_TYPE_DISP16, "d16" },
3041 { OPERAND_TYPE_DISP32, "d32" },
3042 { OPERAND_TYPE_DISP32S, "d32s" },
3043 { OPERAND_TYPE_DISP64, "d64" },
3044 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3045 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3046 { OPERAND_TYPE_CONTROL, "control reg" },
3047 { OPERAND_TYPE_TEST, "test reg" },
3048 { OPERAND_TYPE_DEBUG, "debug reg" },
3049 { OPERAND_TYPE_FLOATREG, "FReg" },
3050 { OPERAND_TYPE_FLOATACC, "FAcc" },
3051 { OPERAND_TYPE_SREG2, "SReg2" },
3052 { OPERAND_TYPE_SREG3, "SReg3" },
3053 { OPERAND_TYPE_ACC, "Acc" },
3054 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3055 { OPERAND_TYPE_REGMMX, "rMMX" },
3056 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 3057 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 3058 { OPERAND_TYPE_REGZMM, "rZMM" },
3059 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 3060 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 3061};
3062
3063static void
40fb9820 3064pt (i386_operand_type t)
252b5132 3065{
40fb9820 3066 unsigned int j;
c6fb90c8 3067 i386_operand_type a;
252b5132 3068
40fb9820 3069 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 3070 {
3071 a = operand_type_and (t, type_names[j].mask);
0349dc08 3072 if (!operand_type_all_zero (&a))
c6fb90c8
L		 3073 fprintf (stdout, "%s, ", type_names[j].name);
3074 }
252b5132
RH		 3075 fflush (stdout);
3076}
3077
3078#endif /* DEBUG386 */
3079\f
252b5132 3080static bfd_reloc_code_real_type
3956db08 3081reloc (unsigned int size,
64e74474
AM		 3082 int pcrel,
3083 int sign,
3084 bfd_reloc_code_real_type other)
252b5132 3085{
47926f60 3086 if (other != NO_RELOC)
3956db08 3087 {
91d6fa6a 3088 reloc_howto_type *rel;
3956db08
JB		 3089
3090 if (size == 8)
3091 switch (other)
3092 {
64e74474
AM		 3093 case BFD_RELOC_X86_64_GOT32:
3094 return BFD_RELOC_X86_64_GOT64;
3095 break;
553d1284
L		 3096 case BFD_RELOC_X86_64_GOTPLT64:
3097 return BFD_RELOC_X86_64_GOTPLT64;
3098 break;
64e74474
AM		 3099 case BFD_RELOC_X86_64_PLTOFF64:
3100 return BFD_RELOC_X86_64_PLTOFF64;
3101 break;
3102 case BFD_RELOC_X86_64_GOTPC32:
3103 other = BFD_RELOC_X86_64_GOTPC64;
3104 break;
3105 case BFD_RELOC_X86_64_GOTPCREL:
3106 other = BFD_RELOC_X86_64_GOTPCREL64;
3107 break;
3108 case BFD_RELOC_X86_64_TPOFF32:
3109 other = BFD_RELOC_X86_64_TPOFF64;
3110 break;
3111 case BFD_RELOC_X86_64_DTPOFF32:
3112 other = BFD_RELOC_X86_64_DTPOFF64;
3113 break;
3114 default:
3115 break;
3956db08 3116 }
e05278af 3117
8ce3d284 3118#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 3119 if (other == BFD_RELOC_SIZE32)
3120 {
3121 if (size == 8)
1ab668bf 3122 other = BFD_RELOC_SIZE64;
8fd4256d 3123 if (pcrel)
1ab668bf
AM		 3124 {
3125 as_bad (_("there are no pc-relative size relocations"));
3126 return NO_RELOC;
3127 }
8fd4256d 3128 }
8ce3d284 3129#endif
8fd4256d 3130
e05278af 3131 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 3132 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 3133 sign = -1;
3134
91d6fa6a
NC		 3135 rel = bfd_reloc_type_lookup (stdoutput, other);
3136 if (!rel)
3956db08 3137 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 3138 else if (size != bfd_get_reloc_size (rel))
3956db08 3139 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 3140 bfd_get_reloc_size (rel),
3956db08 3141 size);
91d6fa6a 3142 else if (pcrel && !rel->pc_relative)
3956db08 3143 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 3144 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 3145 && !sign)
91d6fa6a 3146 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 3147 && sign > 0))
3956db08
JB		 3148 as_bad (_("relocated field and relocation type differ in signedness"));
3149 else
3150 return other;
3151 return NO_RELOC;
3152 }
252b5132
RH		 3153
3154 if (pcrel)
3155 {
3e73aa7c 3156 if (!sign)
3956db08 3157 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 3158 switch (size)
3159 {
3160 case 1: return BFD_RELOC_8_PCREL;
3161 case 2: return BFD_RELOC_16_PCREL;
d258b828 3162 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 3163 case 8: return BFD_RELOC_64_PCREL;
252b5132 3164 }
3956db08 3165 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 3166 }
3167 else
3168 {
3956db08 3169 if (sign > 0)
e5cb08ac 3170 switch (size)
3e73aa7c
JH		 3171 {
3172 case 4: return BFD_RELOC_X86_64_32S;
3173 }
3174 else
3175 switch (size)
3176 {
3177 case 1: return BFD_RELOC_8;
3178 case 2: return BFD_RELOC_16;
3179 case 4: return BFD_RELOC_32;
3180 case 8: return BFD_RELOC_64;
3181 }
3956db08
JB		 3182 as_bad (_("cannot do %s %u byte relocation"),
3183 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 3184 }
3185
0cc9e1d3 3186 return NO_RELOC;
252b5132
RH		 3187}
3188
47926f60
KH		 3189/* Here we decide which fixups can be adjusted to make them relative to
3190 the beginning of the section instead of the symbol. Basically we need
3191 to make sure that the dynamic relocations are done correctly, so in
3192 some cases we force the original symbol to be used. */
3193
252b5132 3194int
e3bb37b5 3195tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 3196{
6d249963 3197#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 3198 if (!IS_ELF)
31312f95
AM		 3199 return 1;
3200
a161fe53
AM		 3201 /* Don't adjust pc-relative references to merge sections in 64-bit
3202 mode. */
3203 if (use_rela_relocations
3204 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3205 && fixP->fx_pcrel)
252b5132 3206 return 0;
31312f95 3207
8d01d9a9
AJ		 3208 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3209 and changed later by validate_fix. */
3210 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3211 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3212 return 0;
3213
8fd4256d
L		 3214 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3215 for size relocations. */
3216 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3217 || fixP->fx_r_type == BFD_RELOC_SIZE64
3218 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 3219 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3220 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 3221 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3222 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3223 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3224 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3225 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3226 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3227 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3228 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3229 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3230 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3231 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3232 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3233 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3234 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3235 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3236 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3237 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3238 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3239 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3240 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3241 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3242 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3243 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3244 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3245 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3246 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3247 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3248 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3249 return 0;
31312f95 3250#endif
252b5132
RH		 3251 return 1;
3252}
252b5132 3253
b4cac588 3254static int
e3bb37b5 3255intel_float_operand (const char *mnemonic)
252b5132 3256{
9306ca4a
JB		 3257 /* Note that the value returned is meaningful only for opcodes with (memory)
3258 operands, hence the code here is free to improperly handle opcodes that
3259 have no operands (for better performance and smaller code). */
3260
3261 if (mnemonic[0] != 'f')
3262 return 0; /* non-math */
3263
3264 switch (mnemonic[1])
3265 {
3266 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3267 the fs segment override prefix not currently handled because no
3268 call path can make opcodes without operands get here */
3269 case 'i':
3270 return 2 /* integer op */;
3271 case 'l':
3272 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3273 return 3; /* fldcw/fldenv */
3274 break;
3275 case 'n':
3276 if (mnemonic[2] != 'o' /* fnop */)
3277 return 3; /* non-waiting control op */
3278 break;
3279 case 'r':
3280 if (mnemonic[2] == 's')
3281 return 3; /* frstor/frstpm */
3282 break;
3283 case 's':
3284 if (mnemonic[2] == 'a')
3285 return 3; /* fsave */
3286 if (mnemonic[2] == 't')
3287 {
3288 switch (mnemonic[3])
3289 {
3290 case 'c': /* fstcw */
3291 case 'd': /* fstdw */
3292 case 'e': /* fstenv */
3293 case 's': /* fsts[gw] */
3294 return 3;
3295 }
3296 }
3297 break;
3298 case 'x':
3299 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3300 return 0; /* fxsave/fxrstor are not really math ops */
3301 break;
3302 }
252b5132 3303
9306ca4a 3304 return 1;
252b5132
RH		 3305}
3306
c0f3af97
L		 3307/* Build the VEX prefix. */
3308
3309static void
d3ce72d0 3310build_vex_prefix (const insn_template *t)
c0f3af97
L		 3311{
3312 unsigned int register_specifier;
3313 unsigned int implied_prefix;
3314 unsigned int vector_length;
3315
3316 /* Check register specifier. */
3317 if (i.vex.register_specifier)
43234a1e
L		 3318 {
3319 register_specifier =
3320 ~register_number (i.vex.register_specifier) & 0xf;
3321 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3322 }
c0f3af97
L		 3323 else
3324 register_specifier = 0xf;
3325
33eaf5de 3326 /* Use 2-byte VEX prefix by swapping destination and source
fa99fab2 3327 operand. */
86fa6981
L		 3328 if (i.vec_encoding != vex_encoding_vex3
3329 && i.dir_encoding == dir_encoding_default
fa99fab2 3330 && i.operands == i.reg_operands
7f399153 3331 && i.tm.opcode_modifier.vexopcode == VEX0F
86fa6981 3332 && i.tm.opcode_modifier.load
fa99fab2
L		 3333 && i.rex == REX_B)
3334 {
3335 unsigned int xchg = i.operands - 1;
3336 union i386_op temp_op;
3337 i386_operand_type temp_type;
3338
3339 temp_type = i.types[xchg];
3340 i.types[xchg] = i.types[0];
3341 i.types[0] = temp_type;
3342 temp_op = i.op[xchg];
3343 i.op[xchg] = i.op[0];
3344 i.op[0] = temp_op;
3345
9c2799c2 3346 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3347
3348 i.rex = REX_R;
3349 xchg = i.rm.regmem;
3350 i.rm.regmem = i.rm.reg;
3351 i.rm.reg = xchg;
3352
3353 /* Use the next insn. */
3354 i.tm = t[1];
3355 }
3356
539f890d
L		 3357 if (i.tm.opcode_modifier.vex == VEXScalar)
3358 vector_length = avxscalar;
10c17abd
JB		 3359 else if (i.tm.opcode_modifier.vex == VEX256)
3360 vector_length = 1;
539f890d 3361 else
10c17abd
JB		 3362 {
3363 unsigned int op;
3364
3365 vector_length = 0;
3366 for (op = 0; op < t->operands; ++op)
3367 if (t->operand_types[op].bitfield.xmmword
3368 && t->operand_types[op].bitfield.ymmword
3369 && i.types[op].bitfield.ymmword)
3370 {
3371 vector_length = 1;
3372 break;
3373 }
3374 }
c0f3af97
L		 3375
3376 switch ((i.tm.base_opcode >> 8) & 0xff)
3377 {
3378 case 0:
3379 implied_prefix = 0;
3380 break;
3381 case DATA_PREFIX_OPCODE:
3382 implied_prefix = 1;
3383 break;
3384 case REPE_PREFIX_OPCODE:
3385 implied_prefix = 2;
3386 break;
3387 case REPNE_PREFIX_OPCODE:
3388 implied_prefix = 3;
3389 break;
3390 default:
3391 abort ();
3392 }
3393
3394 /* Use 2-byte VEX prefix if possible. */
86fa6981
L		 3395 if (i.vec_encoding != vex_encoding_vex3
3396 && i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3397 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3398 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3399 {
3400 /* 2-byte VEX prefix. */
3401 unsigned int r;
3402
3403 i.vex.length = 2;
3404 i.vex.bytes[0] = 0xc5;
3405
3406 /* Check the REX.R bit. */
3407 r = (i.rex & REX_R) ? 0 : 1;
3408 i.vex.bytes[1] = (r << 7
3409 | register_specifier << 3
3410 | vector_length << 2
3411 | implied_prefix);
3412 }
3413 else
3414 {
3415 /* 3-byte VEX prefix. */
3416 unsigned int m, w;
3417
f88c9eb0 3418 i.vex.length = 3;
f88c9eb0 3419
7f399153 3420 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3421 {
7f399153
L		 3422 case VEX0F:
3423 m = 0x1;
80de6e00 3424 i.vex.bytes[0] = 0xc4;
7f399153
L		 3425 break;
3426 case VEX0F38:
3427 m = 0x2;
80de6e00 3428 i.vex.bytes[0] = 0xc4;
7f399153
L		 3429 break;
3430 case VEX0F3A:
3431 m = 0x3;
80de6e00 3432 i.vex.bytes[0] = 0xc4;
7f399153
L		 3433 break;
3434 case XOP08:
5dd85c99
SP		 3435 m = 0x8;
3436 i.vex.bytes[0] = 0x8f;
7f399153
L		 3437 break;
3438 case XOP09:
f88c9eb0
SP		 3439 m = 0x9;
3440 i.vex.bytes[0] = 0x8f;
7f399153
L		 3441 break;
3442 case XOP0A:
f88c9eb0
SP		 3443 m = 0xa;
3444 i.vex.bytes[0] = 0x8f;
7f399153
L		 3445 break;
3446 default:
3447 abort ();
f88c9eb0 3448 }
c0f3af97 3449
c0f3af97
L		 3450 /* The high 3 bits of the second VEX byte are 1's compliment
3451 of RXB bits from REX. */
3452 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3453
3454 /* Check the REX.W bit. */
3455 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3456 if (i.tm.opcode_modifier.vexw == VEXW1)
3457 w = 1;
c0f3af97
L		 3458
3459 i.vex.bytes[2] = (w << 7
3460 | register_specifier << 3
3461 | vector_length << 2
3462 | implied_prefix);
3463 }
3464}
3465
e771e7c9
JB		 3466static INLINE bfd_boolean
3467is_evex_encoding (const insn_template *t)
3468{
7091c612 3469 return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift
e771e7c9
JB		 3470 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3471 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3472}
3473
43234a1e
L		 3474/* Build the EVEX prefix. */
3475
3476static void
3477build_evex_prefix (void)
3478{
3479 unsigned int register_specifier;
3480 unsigned int implied_prefix;
3481 unsigned int m, w;
3482 rex_byte vrex_used = 0;
3483
3484 /* Check register specifier. */
3485 if (i.vex.register_specifier)
3486 {
3487 gas_assert ((i.vrex & REX_X) == 0);
3488
3489 register_specifier = i.vex.register_specifier->reg_num;
3490 if ((i.vex.register_specifier->reg_flags & RegRex))
3491 register_specifier += 8;
3492 /* The upper 16 registers are encoded in the fourth byte of the
3493 EVEX prefix. */
3494 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3495 i.vex.bytes[3] = 0x8;
3496 register_specifier = ~register_specifier & 0xf;
3497 }
3498 else
3499 {
3500 register_specifier = 0xf;
3501
3502 /* Encode upper 16 vector index register in the fourth byte of
3503 the EVEX prefix. */
3504 if (!(i.vrex & REX_X))
3505 i.vex.bytes[3] = 0x8;
3506 else
3507 vrex_used |= REX_X;
3508 }
3509
3510 switch ((i.tm.base_opcode >> 8) & 0xff)
3511 {
3512 case 0:
3513 implied_prefix = 0;
3514 break;
3515 case DATA_PREFIX_OPCODE:
3516 implied_prefix = 1;
3517 break;
3518 case REPE_PREFIX_OPCODE:
3519 implied_prefix = 2;
3520 break;
3521 case REPNE_PREFIX_OPCODE:
3522 implied_prefix = 3;
3523 break;
3524 default:
3525 abort ();
3526 }
3527
3528 /* 4 byte EVEX prefix. */
3529 i.vex.length = 4;
3530 i.vex.bytes[0] = 0x62;
3531
3532 /* mmmm bits. */
3533 switch (i.tm.opcode_modifier.vexopcode)
3534 {
3535 case VEX0F:
3536 m = 1;
3537 break;
3538 case VEX0F38:
3539 m = 2;
3540 break;
3541 case VEX0F3A:
3542 m = 3;
3543 break;
3544 default:
3545 abort ();
3546 break;
3547 }
3548
3549 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3550 bits from REX. */
3551 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3552
3553 /* The fifth bit of the second EVEX byte is 1's compliment of the
3554 REX_R bit in VREX. */
3555 if (!(i.vrex & REX_R))
3556 i.vex.bytes[1] |= 0x10;
3557 else
3558 vrex_used |= REX_R;
3559
3560 if ((i.reg_operands + i.imm_operands) == i.operands)
3561 {
3562 /* When all operands are registers, the REX_X bit in REX is not
3563 used. We reuse it to encode the upper 16 registers, which is
3564 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3565 as 1's compliment. */
3566 if ((i.vrex & REX_B))
3567 {
3568 vrex_used |= REX_B;
3569 i.vex.bytes[1] &= ~0x40;
3570 }
3571 }
3572
3573 /* EVEX instructions shouldn't need the REX prefix. */
3574 i.vrex &= ~vrex_used;
3575 gas_assert (i.vrex == 0);
3576
3577 /* Check the REX.W bit. */
3578 w = (i.rex & REX_W) ? 1 : 0;
3579 if (i.tm.opcode_modifier.vexw)
3580 {
3581 if (i.tm.opcode_modifier.vexw == VEXW1)
3582 w = 1;
3583 }
3584 /* If w is not set it means we are dealing with WIG instruction. */
3585 else if (!w)
3586 {
3587 if (evexwig == evexw1)
3588 w = 1;
3589 }
3590
3591 /* Encode the U bit. */
3592 implied_prefix |= 0x4;
3593
3594 /* The third byte of the EVEX prefix. */
3595 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3596
3597 /* The fourth byte of the EVEX prefix. */
3598 /* The zeroing-masking bit. */
3599 if (i.mask && i.mask->zeroing)
3600 i.vex.bytes[3] |= 0x80;
3601
3602 /* Don't always set the broadcast bit if there is no RC. */
3603 if (!i.rounding)
3604 {
3605 /* Encode the vector length. */
3606 unsigned int vec_length;
3607
e771e7c9
JB		 3608 if (!i.tm.opcode_modifier.evex
3609 || i.tm.opcode_modifier.evex == EVEXDYN)
3610 {
3611 unsigned int op;
3612
3613 vec_length = 0;
3614 for (op = 0; op < i.tm.operands; ++op)
3615 if (i.tm.operand_types[op].bitfield.xmmword
3616 + i.tm.operand_types[op].bitfield.ymmword
3617 + i.tm.operand_types[op].bitfield.zmmword > 1)
3618 {
3619 if (i.types[op].bitfield.zmmword)
3620 i.tm.opcode_modifier.evex = EVEX512;
3621 else if (i.types[op].bitfield.ymmword)
3622 i.tm.opcode_modifier.evex = EVEX256;
3623 else if (i.types[op].bitfield.xmmword)
3624 i.tm.opcode_modifier.evex = EVEX128;
3625 else
3626 continue;
3627 break;
3628 }
3629 }
3630
43234a1e
L		 3631 switch (i.tm.opcode_modifier.evex)
3632 {
3633 case EVEXLIG: /* LL' is ignored */
3634 vec_length = evexlig << 5;
3635 break;
3636 case EVEX128:
3637 vec_length = 0 << 5;
3638 break;
3639 case EVEX256:
3640 vec_length = 1 << 5;
3641 break;
3642 case EVEX512:
3643 vec_length = 2 << 5;
3644 break;
3645 default:
3646 abort ();
3647 break;
3648 }
3649 i.vex.bytes[3] |= vec_length;
3650 /* Encode the broadcast bit. */
3651 if (i.broadcast)
3652 i.vex.bytes[3] |= 0x10;
3653 }
3654 else
3655 {
3656 if (i.rounding->type != saeonly)
3657 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3658 else
d3d3c6db 3659 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3660 }
3661
3662 if (i.mask && i.mask->mask)
3663 i.vex.bytes[3] |= i.mask->mask->reg_num;
3664}
3665
65da13b5
L		 3666static void
3667process_immext (void)
3668{
3669 expressionS *exp;
3670
4c692bc7
JB		 3671 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3672 && i.operands > 0)
65da13b5 3673 {
4c692bc7
JB		 3674 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3675 with an opcode suffix which is coded in the same place as an
3676 8-bit immediate field would be.
3677 Here we check those operands and remove them afterwards. */
65da13b5
L		 3678 unsigned int x;
3679
3680 for (x = 0; x < i.operands; x++)
4c692bc7 3681 if (register_number (i.op[x].regs) != x)
65da13b5 3682 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3683 register_prefix, i.op[x].regs->reg_name, x + 1,
3684 i.tm.name);
3685
3686 i.operands = 0;
65da13b5
L		 3687 }
3688
9916071f
AP		 3689 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3690 {
3691 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3692 suffix which is coded in the same place as an 8-bit immediate
3693 field would be.
3694 Here we check those operands and remove them afterwards. */
3695 unsigned int x;
3696
3697 if (i.operands != 3)
3698 abort();
3699
3700 for (x = 0; x < 2; x++)
3701 if (register_number (i.op[x].regs) != x)
3702 goto bad_register_operand;
3703
3704 /* Check for third operand for mwaitx/monitorx insn. */
3705 if (register_number (i.op[x].regs)
3706 != (x + (i.tm.extension_opcode == 0xfb)))
3707 {
3708bad_register_operand:
3709 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3710 register_prefix, i.op[x].regs->reg_name, x+1,
3711 i.tm.name);
3712 }
3713
3714 i.operands = 0;
3715 }
3716
c0f3af97 3717 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3718 which is coded in the same place as an 8-bit immediate field
3719 would be. Here we fake an 8-bit immediate operand from the
3720 opcode suffix stored in tm.extension_opcode.
3721
c1e679ec 3722 AVX instructions also use this encoding, for some of
c0f3af97 3723 3 argument instructions. */
65da13b5 3724
43234a1e 3725 gas_assert (i.imm_operands <= 1
7ab9ffdd 3726 && (i.operands <= 2
43234a1e 3727 || ((i.tm.opcode_modifier.vex
e771e7c9
JB		 3728 || i.tm.opcode_modifier.vexopcode
3729 || is_evex_encoding (&i.tm))
7ab9ffdd 3730 && i.operands <= 4)));
65da13b5
L		 3731
3732 exp = &im_expressions[i.imm_operands++];
3733 i.op[i.operands].imms = exp;
3734 i.types[i.operands] = imm8;
3735 i.operands++;
3736 exp->X_op = O_constant;
3737 exp->X_add_number = i.tm.extension_opcode;
3738 i.tm.extension_opcode = None;
3739}
3740
42164a71
L		 3741
3742static int
3743check_hle (void)
3744{
3745 switch (i.tm.opcode_modifier.hleprefixok)
3746 {
3747 default:
3748 abort ();
82c2def5 3749 case HLEPrefixNone:
165de32a
L		 3750 as_bad (_("invalid instruction `%s' after `%s'"),
3751 i.tm.name, i.hle_prefix);
42164a71 3752 return 0;
82c2def5 3753 case HLEPrefixLock:
42164a71
L		 3754 if (i.prefix[LOCK_PREFIX])
3755 return 1;
165de32a 3756 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3757 return 0;
82c2def5 3758 case HLEPrefixAny:
42164a71 3759 return 1;
82c2def5 3760 case HLEPrefixRelease:
42164a71
L		 3761 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3762 {
3763 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3764 i.tm.name);
3765 return 0;
3766 }
3767 if (i.mem_operands == 0
3768 || !operand_type_check (i.types[i.operands - 1], anymem))
3769 {
3770 as_bad (_("memory destination needed for instruction `%s'"
3771 " after `xrelease'"), i.tm.name);
3772 return 0;
3773 }
3774 return 1;
3775 }
3776}
3777
b6f8c7c4
L		 3778/* Try the shortest encoding by shortening operand size. */
3779
3780static void
3781optimize_encoding (void)
3782{
3783 int j;
3784
3785 if (optimize_for_space
3786 && i.reg_operands == 1
3787 && i.imm_operands == 1
3788 && !i.types[1].bitfield.byte
3789 && i.op[0].imms->X_op == O_constant
3790 && fits_in_imm7 (i.op[0].imms->X_add_number)
3791 && ((i.tm.base_opcode == 0xa8
3792 && i.tm.extension_opcode == None)
3793 || (i.tm.base_opcode == 0xf6
3794 && i.tm.extension_opcode == 0x0)))
3795 {
3796 /* Optimize: -Os:
3797 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3798 */
3799 unsigned int base_regnum = i.op[1].regs->reg_num;
3800 if (flag_code == CODE_64BIT || base_regnum < 4)
3801 {
3802 i.types[1].bitfield.byte = 1;
3803 /* Ignore the suffix. */
3804 i.suffix = 0;
3805 if (base_regnum >= 4
3806 && !(i.op[1].regs->reg_flags & RegRex))
3807 {
3808 /* Handle SP, BP, SI and DI registers. */
3809 if (i.types[1].bitfield.word)
3810 j = 16;
3811 else if (i.types[1].bitfield.dword)
3812 j = 32;
3813 else
3814 j = 48;
3815 i.op[1].regs -= j;
3816 }
3817 }
3818 }
3819 else if (flag_code == CODE_64BIT
d3d50934
L		 3820 && ((i.types[1].bitfield.qword
3821 && i.reg_operands == 1
b6f8c7c4
L		 3822 && i.imm_operands == 1
3823 && i.op[0].imms->X_op == O_constant
3824 && ((i.tm.base_opcode == 0xb0
3825 && i.tm.extension_opcode == None
3826 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3827 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3828 && (((i.tm.base_opcode == 0x24
3829 || i.tm.base_opcode == 0xa8)
3830 && i.tm.extension_opcode == None)
3831 || (i.tm.base_opcode == 0x80
3832 && i.tm.extension_opcode == 0x4)
3833 || ((i.tm.base_opcode == 0xf6
3834 || i.tm.base_opcode == 0xc6)
3835 && i.tm.extension_opcode == 0x0)))))
d3d50934
L		 3836 || (i.types[0].bitfield.qword
3837 && ((i.reg_operands == 2
3838 && i.op[0].regs == i.op[1].regs
3839 && ((i.tm.base_opcode == 0x30
3840 || i.tm.base_opcode == 0x28)
3841 && i.tm.extension_opcode == None))
3842 || (i.reg_operands == 1
3843 && i.operands == 1
3844 && i.tm.base_opcode == 0x30
3845 && i.tm.extension_opcode == None)))))
b6f8c7c4
L		 3846 {
3847 /* Optimize: -O:
3848 andq $imm31, %r64 -> andl $imm31, %r32
3849 testq $imm31, %r64 -> testl $imm31, %r32
3850 xorq %r64, %r64 -> xorl %r32, %r32
3851 subq %r64, %r64 -> subl %r32, %r32
3852 movq $imm31, %r64 -> movl $imm31, %r32
3853 movq $imm32, %r64 -> movl $imm32, %r32
3854 */
3855 i.tm.opcode_modifier.norex64 = 1;
3856 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3857 {
3858 /* Handle
3859 movq $imm31, %r64 -> movl $imm31, %r32
3860 movq $imm32, %r64 -> movl $imm32, %r32
3861 */
3862 i.tm.operand_types[0].bitfield.imm32 = 1;
3863 i.tm.operand_types[0].bitfield.imm32s = 0;
3864 i.tm.operand_types[0].bitfield.imm64 = 0;
3865 i.types[0].bitfield.imm32 = 1;
3866 i.types[0].bitfield.imm32s = 0;
3867 i.types[0].bitfield.imm64 = 0;
3868 i.types[1].bitfield.dword = 1;
3869 i.types[1].bitfield.qword = 0;
3870 if (i.tm.base_opcode == 0xc6)
3871 {
3872 /* Handle
3873 movq $imm31, %r64 -> movl $imm31, %r32
3874 */
3875 i.tm.base_opcode = 0xb0;
3876 i.tm.extension_opcode = None;
3877 i.tm.opcode_modifier.shortform = 1;
3878 i.tm.opcode_modifier.modrm = 0;
3879 }
3880 }
3881 }
3882 else if (optimize > 1
3883 && i.reg_operands == 3
3884 && i.op[0].regs == i.op[1].regs
3885 && !i.types[2].bitfield.xmmword
3886 && (i.tm.opcode_modifier.vex
7a69eac3 3887 || ((!i.mask || i.mask->zeroing)
b6f8c7c4 3888 && !i.rounding
e771e7c9 3889 && is_evex_encoding (&i.tm)
80c34c38
L		 3890 && (i.vec_encoding != vex_encoding_evex
3891 || i.tm.cpu_flags.bitfield.cpuavx512vl
7091c612
JB		 3892 || (i.tm.operand_types[2].bitfield.zmmword
3893 && i.types[2].bitfield.ymmword)
0089dace 3894 || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
b6f8c7c4
L		 3895 && ((i.tm.base_opcode == 0x55
3896 || i.tm.base_opcode == 0x6655
3897 || i.tm.base_opcode == 0x66df
3898 || i.tm.base_opcode == 0x57
3899 || i.tm.base_opcode == 0x6657
8305403a
L		 3900 || i.tm.base_opcode == 0x66ef
3901 || i.tm.base_opcode == 0x66f8
3902 || i.tm.base_opcode == 0x66f9
3903 || i.tm.base_opcode == 0x66fa
3904 || i.tm.base_opcode == 0x66fb)
b6f8c7c4
L		 3905 && i.tm.extension_opcode == None))
3906 {
3907 /* Optimize: -O2:
8305403a
L		 3908 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3909 vpsubq and vpsubw:
b6f8c7c4
L		 3910 EVEX VOP %zmmM, %zmmM, %zmmN
3911 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3912 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3913 EVEX VOP %ymmM, %ymmM, %ymmN
3914 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3915 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3916 VEX VOP %ymmM, %ymmM, %ymmN
3917 -> VEX VOP %xmmM, %xmmM, %xmmN
3918 VOP, one of vpandn and vpxor:
3919 VEX VOP %ymmM, %ymmM, %ymmN
3920 -> VEX VOP %xmmM, %xmmM, %xmmN
3921 VOP, one of vpandnd and vpandnq:
3922 EVEX VOP %zmmM, %zmmM, %zmmN
3923 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3924 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3925 EVEX VOP %ymmM, %ymmM, %ymmN
3926 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3927 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3928 VOP, one of vpxord and vpxorq:
3929 EVEX VOP %zmmM, %zmmM, %zmmN
3930 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3931 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3932 EVEX VOP %ymmM, %ymmM, %ymmN
3933 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3934 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3935 */
e771e7c9 3936 if (is_evex_encoding (&i.tm))
b6f8c7c4 3937 {
0089dace 3938 if (i.vec_encoding == vex_encoding_evex)
b6f8c7c4
L		 3939 i.tm.opcode_modifier.evex = EVEX128;
3940 else
3941 {
3942 i.tm.opcode_modifier.vex = VEX128;
3943 i.tm.opcode_modifier.vexw = VEXW0;
3944 i.tm.opcode_modifier.evex = 0;
3945 }
3946 }
3947 else
3948 i.tm.opcode_modifier.vex = VEX128;
3949
3950 if (i.tm.opcode_modifier.vex)
3951 for (j = 0; j < 3; j++)
3952 {
3953 i.types[j].bitfield.xmmword = 1;
3954 i.types[j].bitfield.ymmword = 0;
3955 }
3956 }
3957}
3958
252b5132
RH		 3959/* This is the guts of the machine-dependent assembler. LINE points to a
3960 machine dependent instruction. This function is supposed to emit
3961 the frags/bytes it assembles to. */
3962
3963void
65da13b5 3964md_assemble (char *line)
252b5132 3965{
40fb9820 3966 unsigned int j;
83b16ac6 3967 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
d3ce72d0 3968 const insn_template *t;
252b5132 3969
47926f60 3970 /* Initialize globals. */
252b5132
RH		 3971 memset (&i, '\0', sizeof (i));
3972 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3973 i.reloc[j] = NO_RELOC;
252b5132
RH		 3974 memset (disp_expressions, '\0', sizeof (disp_expressions));
3975 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3976 save_stack_p = save_stack;
252b5132
RH		 3977
3978 /* First parse an instruction mnemonic & call i386_operand for the operands.
3979 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3980 start of a (possibly prefixed) mnemonic. */
252b5132 3981
29b0f896
AM		 3982 line = parse_insn (line, mnemonic);
3983 if (line == NULL)
3984 return;
83b16ac6 3985 mnem_suffix = i.suffix;
252b5132 3986
29b0f896 3987 line = parse_operands (line, mnemonic);
ee86248c 3988 this_operand = -1;
8325cc63
JB		 3989 xfree (i.memop1_string);
3990 i.memop1_string = NULL;
29b0f896
AM		 3991 if (line == NULL)
3992 return;
252b5132 3993
29b0f896
AM		 3994 /* Now we've parsed the mnemonic into a set of templates, and have the
3995 operands at hand. */
3996
3997 /* All intel opcodes have reversed operands except for "bound" and
3998 "enter". We also don't reverse intersegment "jmp" and "call"
3999 instructions with 2 immediate operands so that the immediate segment
050dfa73 4000 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 4001 if (intel_syntax
4002 && i.operands > 1
29b0f896 4003 && (strcmp (mnemonic, "bound") != 0)
30123838 4004 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 4005 && !(operand_type_check (i.types[0], imm)
4006 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 4007 swap_operands ();
4008
ec56d5c0
JB		 4009 /* The order of the immediates should be reversed
4010 for 2 immediates extrq and insertq instructions */
4011 if (i.imm_operands == 2
4012 && (strcmp (mnemonic, "extrq") == 0
4013 || strcmp (mnemonic, "insertq") == 0))
4014 swap_2_operands (0, 1);
4015
29b0f896
AM		 4016 if (i.imm_operands)
4017 optimize_imm ();
4018
b300c311
L		 4019 /* Don't optimize displacement for movabs since it only takes 64bit
4020 displacement. */
4021 if (i.disp_operands
a501d77e 4022 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 4023 && (flag_code != CODE_64BIT
4024 || strcmp (mnemonic, "movabs") != 0))
4025 optimize_disp ();
29b0f896
AM		 4026
4027 /* Next, we find a template that matches the given insn,
4028 making sure the overlap of the given operands types is consistent
4029 with the template operand types. */
252b5132 4030
83b16ac6 4031 if (!(t = match_template (mnem_suffix)))
29b0f896 4032 return;
252b5132 4033
7bab8ab5 4034 if (sse_check != check_none
81f8a913 4035 && !i.tm.opcode_modifier.noavx
6e3e5c9e 4036 && !i.tm.cpu_flags.bitfield.cpuavx
daf50ae7
L		 4037 && (i.tm.cpu_flags.bitfield.cpusse
4038 || i.tm.cpu_flags.bitfield.cpusse2
4039 || i.tm.cpu_flags.bitfield.cpusse3
4040 || i.tm.cpu_flags.bitfield.cpussse3
4041 || i.tm.cpu_flags.bitfield.cpusse4_1
6e3e5c9e
JB		 4042 || i.tm.cpu_flags.bitfield.cpusse4_2
4043 || i.tm.cpu_flags.bitfield.cpupclmul
4044 || i.tm.cpu_flags.bitfield.cpuaes
4045 || i.tm.cpu_flags.bitfield.cpugfni))
daf50ae7 4046 {
7bab8ab5 4047 (sse_check == check_warning
daf50ae7
L		 4048 ? as_warn
4049 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4050 }
4051
321fd21e
L		 4052 /* Zap movzx and movsx suffix. The suffix has been set from
4053 "word ptr" or "byte ptr" on the source operand in Intel syntax
4054 or extracted from mnemonic in AT&T syntax. But we'll use
4055 the destination register to choose the suffix for encoding. */
4056 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 4057 {
321fd21e
L		 4058 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4059 there is no suffix, the default will be byte extension. */
4060 if (i.reg_operands != 2
4061 && !i.suffix
7ab9ffdd 4062 && intel_syntax)
321fd21e
L		 4063 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4064
4065 i.suffix = 0;
cd61ebfe 4066 }
24eab124 4067
40fb9820 4068 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 4069 if (!add_prefix (FWAIT_OPCODE))
4070 return;
252b5132 4071
d5de92cf
L		 4072 /* Check if REP prefix is OK. */
4073 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4074 {
4075 as_bad (_("invalid instruction `%s' after `%s'"),
4076 i.tm.name, i.rep_prefix);
4077 return;
4078 }
4079
c1ba0266
L		 4080 /* Check for lock without a lockable instruction. Destination operand
4081 must be memory unless it is xchg (0x86). */
c32fa91d
L		 4082 if (i.prefix[LOCK_PREFIX]
4083 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 4084 || i.mem_operands == 0
4085 || (i.tm.base_opcode != 0x86
4086 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 4087 {
4088 as_bad (_("expecting lockable instruction after `lock'"));
4089 return;
4090 }
4091
42164a71 4092 /* Check if HLE prefix is OK. */
165de32a 4093 if (i.hle_prefix && !check_hle ())
42164a71
L		 4094 return;
4095
7e8b059b
L		 4096 /* Check BND prefix. */
4097 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4098 as_bad (_("expecting valid branch instruction after `bnd'"));
4099
04ef582a 4100 /* Check NOTRACK prefix. */
9fef80d6
L		 4101 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4102 as_bad (_("expecting indirect branch instruction after `notrack'"));
04ef582a 4103
327e8c42
JB		 4104 if (i.tm.cpu_flags.bitfield.cpumpx)
4105 {
4106 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4107 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4108 else if (flag_code != CODE_16BIT
4109 ? i.prefix[ADDR_PREFIX]
4110 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4111 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4112 }
7e8b059b
L		 4113
4114 /* Insert BND prefix. */
76d3a78a
JB		 4115 if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok)
4116 {
4117 if (!i.prefix[BND_PREFIX])
4118 add_prefix (BND_PREFIX_OPCODE);
4119 else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE)
4120 {
4121 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4122 i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE;
4123 }
4124 }
7e8b059b 4125
29b0f896 4126 /* Check string instruction segment overrides. */
40fb9820 4127 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 4128 {
4129 if (!check_string ())
5dd0794d 4130 return;
fc0763e6 4131 i.disp_operands = 0;
29b0f896 4132 }
5dd0794d 4133
b6f8c7c4
L		 4134 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4135 optimize_encoding ();
4136
29b0f896
AM		 4137 if (!process_suffix ())
4138 return;
e413e4e9 4139
bc0844ae
L		 4140 /* Update operand types. */
4141 for (j = 0; j < i.operands; j++)
4142 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4143
29b0f896
AM		 4144 /* Make still unresolved immediate matches conform to size of immediate
4145 given in i.suffix. */
4146 if (!finalize_imm ())
4147 return;
252b5132 4148
40fb9820 4149 if (i.types[0].bitfield.imm1)
29b0f896 4150 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 4151
9afe6eb8
L		 4152 /* We only need to check those implicit registers for instructions
4153 with 3 operands or less. */
4154 if (i.operands <= 3)
4155 for (j = 0; j < i.operands; j++)
4156 if (i.types[j].bitfield.inoutportreg
4157 || i.types[j].bitfield.shiftcount
1b54b8d7 4158 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
9afe6eb8 4159 i.reg_operands--;
40fb9820 4160
c0f3af97
L		 4161 /* ImmExt should be processed after SSE2AVX. */
4162 if (!i.tm.opcode_modifier.sse2avx
4163 && i.tm.opcode_modifier.immext)
65da13b5 4164 process_immext ();
252b5132 4165
29b0f896
AM		 4166 /* For insns with operands there are more diddles to do to the opcode. */
4167 if (i.operands)
4168 {
4169 if (!process_operands ())
4170 return;
4171 }
40fb9820 4172 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 4173 {
4174 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4175 as_warn (_("translating to `%sp'"), i.tm.name);
4176 }
252b5132 4177
e771e7c9
JB		 4178 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.vexopcode
4179 || is_evex_encoding (&i.tm))
9e5e5283
L		 4180 {
4181 if (flag_code == CODE_16BIT)
4182 {
4183 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4184 i.tm.name);
4185 return;
4186 }
c0f3af97 4187
9e5e5283
L		 4188 if (i.tm.opcode_modifier.vex)
4189 build_vex_prefix (t);
4190 else
4191 build_evex_prefix ();
4192 }
43234a1e 4193
5dd85c99
SP		 4194 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4195 instructions may define INT_OPCODE as well, so avoid this corner
4196 case for those instructions that use MODRM. */
4197 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 4198 && !i.tm.opcode_modifier.modrm
4199 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 4200 {
4201 i.tm.base_opcode = INT3_OPCODE;
4202 i.imm_operands = 0;
4203 }
252b5132 4204
40fb9820
L		 4205 if ((i.tm.opcode_modifier.jump
4206 || i.tm.opcode_modifier.jumpbyte
4207 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 4208 && i.op[0].disps->X_op == O_constant)
4209 {
4210 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4211 the absolute address given by the constant. Since ix86 jumps and
4212 calls are pc relative, we need to generate a reloc. */
4213 i.op[0].disps->X_add_symbol = &abs_symbol;
4214 i.op[0].disps->X_op = O_symbol;
4215 }
252b5132 4216
40fb9820 4217 if (i.tm.opcode_modifier.rex64)
161a04f6 4218 i.rex |= REX_W;
252b5132 4219
29b0f896
AM		 4220 /* For 8 bit registers we need an empty rex prefix. Also if the
4221 instruction already has a prefix, we need to convert old
4222 registers to new ones. */
773f551c 4223
dc821c5f 4224 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
29b0f896 4225 && (i.op[0].regs->reg_flags & RegRex64) != 0)
dc821c5f 4226 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
29b0f896 4227 && (i.op[1].regs->reg_flags & RegRex64) != 0)
dc821c5f
JB		 4228 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4229 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
29b0f896
AM		 4230 && i.rex != 0))
4231 {
4232 int x;
726c5dcd 4233
29b0f896
AM		 4234 i.rex |= REX_OPCODE;
4235 for (x = 0; x < 2; x++)
4236 {
4237 /* Look for 8 bit operand that uses old registers. */
dc821c5f 4238 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
29b0f896 4239 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 4240 {
29b0f896
AM		 4241 /* In case it is "hi" register, give up. */
4242 if (i.op[x].regs->reg_num > 3)
a540244d 4243 as_bad (_("can't encode register '%s%s' in an "
4eed87de 4244 "instruction requiring REX prefix."),
a540244d 4245 register_prefix, i.op[x].regs->reg_name);
773f551c 4246
29b0f896
AM		 4247 /* Otherwise it is equivalent to the extended register.
4248 Since the encoding doesn't change this is merely
4249 cosmetic cleanup for debug output. */
4250
4251 i.op[x].regs = i.op[x].regs + 8;
773f551c 4252 }
29b0f896
AM		 4253 }
4254 }
773f551c 4255
6b6b6807
L		 4256 if (i.rex == 0 && i.rex_encoding)
4257 {
4258 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4259 that uses legacy register. If it is "hi" register, don't add
4260 the REX_OPCODE byte. */
4261 int x;
4262 for (x = 0; x < 2; x++)
4263 if (i.types[x].bitfield.reg
4264 && i.types[x].bitfield.byte
4265 && (i.op[x].regs->reg_flags & RegRex64) == 0
4266 && i.op[x].regs->reg_num > 3)
4267 {
4268 i.rex_encoding = FALSE;
4269 break;
4270 }
4271
4272 if (i.rex_encoding)
4273 i.rex = REX_OPCODE;
4274 }
4275
7ab9ffdd 4276 if (i.rex != 0)
29b0f896
AM		 4277 add_prefix (REX_OPCODE | i.rex);
4278
4279 /* We are ready to output the insn. */
4280 output_insn ();
4281}
4282
4283static char *
e3bb37b5 4284parse_insn (char *line, char *mnemonic)
29b0f896
AM		 4285{
4286 char *l = line;
4287 char *token_start = l;
4288 char *mnem_p;
5c6af06e 4289 int supported;
d3ce72d0 4290 const insn_template *t;
b6169b20 4291 char *dot_p = NULL;
29b0f896 4292
29b0f896
AM		 4293 while (1)
4294 {
4295 mnem_p = mnemonic;
4296 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4297 {
b6169b20
L		 4298 if (*mnem_p == '.')
4299 dot_p = mnem_p;
29b0f896
AM		 4300 mnem_p++;
4301 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 4302 {
29b0f896
AM		 4303 as_bad (_("no such instruction: `%s'"), token_start);
4304 return NULL;
4305 }
4306 l++;
4307 }
4308 if (!is_space_char (*l)
4309 && *l != END_OF_INSN
e44823cf
JB		 4310 && (intel_syntax
4311 || (*l != PREFIX_SEPARATOR
4312 && *l != ',')))
29b0f896
AM		 4313 {
4314 as_bad (_("invalid character %s in mnemonic"),
4315 output_invalid (*l));
4316 return NULL;
4317 }
4318 if (token_start == l)
4319 {
e44823cf 4320 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 4321 as_bad (_("expecting prefix; got nothing"));
4322 else
4323 as_bad (_("expecting mnemonic; got nothing"));
4324 return NULL;
4325 }
45288df1 4326
29b0f896 4327 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 4328 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 4329
29b0f896
AM		 4330 if (*l != END_OF_INSN
4331 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4332 && current_templates
40fb9820 4333 && current_templates->start->opcode_modifier.isprefix)
29b0f896 4334 {
c6fb90c8 4335 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 4336 {
4337 as_bad ((flag_code != CODE_64BIT
4338 ? _("`%s' is only supported in 64-bit mode")
4339 : _("`%s' is not supported in 64-bit mode")),
4340 current_templates->start->name);
4341 return NULL;
4342 }
29b0f896
AM		 4343 /* If we are in 16-bit mode, do not allow addr16 or data16.
4344 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 4345 if ((current_templates->start->opcode_modifier.size16
4346 || current_templates->start->opcode_modifier.size32)
29b0f896 4347 && flag_code != CODE_64BIT
40fb9820 4348 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 4349 ^ (flag_code == CODE_16BIT)))
4350 {
4351 as_bad (_("redundant %s prefix"),
4352 current_templates->start->name);
4353 return NULL;
45288df1 4354 }
86fa6981 4355 if (current_templates->start->opcode_length == 0)
29b0f896 4356 {
86fa6981
L		 4357 /* Handle pseudo prefixes. */
4358 switch (current_templates->start->base_opcode)
4359 {
4360 case 0x0:
4361 /* {disp8} */
4362 i.disp_encoding = disp_encoding_8bit;
4363 break;
4364 case 0x1:
4365 /* {disp32} */
4366 i.disp_encoding = disp_encoding_32bit;
4367 break;
4368 case 0x2:
4369 /* {load} */
4370 i.dir_encoding = dir_encoding_load;
4371 break;
4372 case 0x3:
4373 /* {store} */
4374 i.dir_encoding = dir_encoding_store;
4375 break;
4376 case 0x4:
4377 /* {vex2} */
4378 i.vec_encoding = vex_encoding_vex2;
4379 break;
4380 case 0x5:
4381 /* {vex3} */
4382 i.vec_encoding = vex_encoding_vex3;
4383 break;
4384 case 0x6:
4385 /* {evex} */
4386 i.vec_encoding = vex_encoding_evex;
4387 break;
6b6b6807
L		 4388 case 0x7:
4389 /* {rex} */
4390 i.rex_encoding = TRUE;
4391 break;
b6f8c7c4
L		 4392 case 0x8:
4393 /* {nooptimize} */
4394 i.no_optimize = TRUE;
4395 break;
86fa6981
L		 4396 default:
4397 abort ();
4398 }
4399 }
4400 else
4401 {
4402 /* Add prefix, checking for repeated prefixes. */
4e9ac44a 4403 switch (add_prefix (current_templates->start->base_opcode))
86fa6981 4404 {
4e9ac44a
L		 4405 case PREFIX_EXIST:
4406 return NULL;
4407 case PREFIX_DS:
d777820b 4408 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4e9ac44a
L		 4409 i.notrack_prefix = current_templates->start->name;
4410 break;
4411 case PREFIX_REP:
4412 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4413 i.hle_prefix = current_templates->start->name;
4414 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4415 i.bnd_prefix = current_templates->start->name;
4416 else
4417 i.rep_prefix = current_templates->start->name;
4418 break;
4419 default:
4420 break;
86fa6981 4421 }
29b0f896
AM		 4422 }
4423 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4424 token_start = ++l;
4425 }
4426 else
4427 break;
4428 }
45288df1 4429
30a55f88 4430 if (!current_templates)
b6169b20 4431 {
f8a5c266
L		 4432 /* Check if we should swap operand or force 32bit displacement in
4433 encoding. */
30a55f88 4434 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
86fa6981 4435 i.dir_encoding = dir_encoding_store;
8d63c93e 4436 else if (mnem_p - 3 == dot_p
a501d77e
L		 4437 && dot_p[1] == 'd'
4438 && dot_p[2] == '8')
4439 i.disp_encoding = disp_encoding_8bit;
8d63c93e 4440 else if (mnem_p - 4 == dot_p
f8a5c266
L		 4441 && dot_p[1] == 'd'
4442 && dot_p[2] == '3'
4443 && dot_p[3] == '2')
a501d77e 4444 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 4445 else
4446 goto check_suffix;
4447 mnem_p = dot_p;
4448 *dot_p = '\0';
d3ce72d0 4449 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 4450 }
4451
29b0f896
AM		 4452 if (!current_templates)
4453 {
b6169b20 4454check_suffix:
29b0f896
AM		 4455 /* See if we can get a match by trimming off a suffix. */
4456 switch (mnem_p[-1])
4457 {
4458 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 4459 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4460 i.suffix = SHORT_MNEM_SUFFIX;
4461 else
1a0670f3 4462 /* Fall through. */
29b0f896
AM		 4463 case BYTE_MNEM_SUFFIX:
4464 case QWORD_MNEM_SUFFIX:
4465 i.suffix = mnem_p[-1];
4466 mnem_p[-1] = '\0';
d3ce72d0
NC		 4467 current_templates = (const templates *) hash_find (op_hash,
4468 mnemonic);
29b0f896
AM		 4469 break;
4470 case SHORT_MNEM_SUFFIX:
4471 case LONG_MNEM_SUFFIX:
4472 if (!intel_syntax)
4473 {
4474 i.suffix = mnem_p[-1];
4475 mnem_p[-1] = '\0';
d3ce72d0
NC		 4476 current_templates = (const templates *) hash_find (op_hash,
4477 mnemonic);
29b0f896
AM		 4478 }
4479 break;
252b5132 4480
29b0f896
AM		 4481 /* Intel Syntax. */
4482 case 'd':
4483 if (intel_syntax)
4484 {
9306ca4a 4485 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 4486 i.suffix = SHORT_MNEM_SUFFIX;
4487 else
4488 i.suffix = LONG_MNEM_SUFFIX;
4489 mnem_p[-1] = '\0';
d3ce72d0
NC		 4490 current_templates = (const templates *) hash_find (op_hash,
4491 mnemonic);
29b0f896
AM		 4492 }
4493 break;
4494 }
4495 if (!current_templates)
4496 {
4497 as_bad (_("no such instruction: `%s'"), token_start);
4498 return NULL;
4499 }
4500 }
252b5132 4501
40fb9820
L		 4502 if (current_templates->start->opcode_modifier.jump
4503 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 4504 {
4505 /* Check for a branch hint. We allow ",pt" and ",pn" for
4506 predict taken and predict not taken respectively.
4507 I'm not sure that branch hints actually do anything on loop
4508 and jcxz insns (JumpByte) for current Pentium4 chips. They
4509 may work in the future and it doesn't hurt to accept them
4510 now. */
4511 if (l[0] == ',' && l[1] == 'p')
4512 {
4513 if (l[2] == 't')
4514 {
4515 if (!add_prefix (DS_PREFIX_OPCODE))
4516 return NULL;
4517 l += 3;
4518 }
4519 else if (l[2] == 'n')
4520 {
4521 if (!add_prefix (CS_PREFIX_OPCODE))
4522 return NULL;
4523 l += 3;
4524 }
4525 }
4526 }
4527 /* Any other comma loses. */
4528 if (*l == ',')
4529 {
4530 as_bad (_("invalid character %s in mnemonic"),
4531 output_invalid (*l));
4532 return NULL;
4533 }
252b5132 4534
29b0f896 4535 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 4536 supported = 0;
4537 for (t = current_templates->start; t < current_templates->end; ++t)
4538 {
c0f3af97
L		 4539 supported |= cpu_flags_match (t);
4540 if (supported == CPU_FLAGS_PERFECT_MATCH)
548d0ee6
JB		 4541 {
4542 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4543 as_warn (_("use .code16 to ensure correct addressing mode"));
3629bb00 4544
548d0ee6
JB		 4545 return l;
4546 }
29b0f896 4547 }
3629bb00 4548
548d0ee6
JB		 4549 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4550 as_bad (flag_code == CODE_64BIT
4551 ? _("`%s' is not supported in 64-bit mode")
4552 : _("`%s' is only supported in 64-bit mode"),
4553 current_templates->start->name);
4554 else
4555 as_bad (_("`%s' is not supported on `%s%s'"),
4556 current_templates->start->name,
4557 cpu_arch_name ? cpu_arch_name : default_arch,
4558 cpu_sub_arch_name ? cpu_sub_arch_name : "");
252b5132 4559
548d0ee6 4560 return NULL;
29b0f896 4561}
252b5132 4562
29b0f896 4563static char *
e3bb37b5 4564parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4565{
4566 char *token_start;
3138f287 4567
29b0f896
AM		 4568 /* 1 if operand is pending after ','. */
4569 unsigned int expecting_operand = 0;
252b5132 4570
29b0f896
AM		 4571 /* Non-zero if operand parens not balanced. */
4572 unsigned int paren_not_balanced;
4573
4574 while (*l != END_OF_INSN)
4575 {
4576 /* Skip optional white space before operand. */
4577 if (is_space_char (*l))
4578 ++l;
d02603dc 4579 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4580 {
4581 as_bad (_("invalid character %s before operand %d"),
4582 output_invalid (*l),
4583 i.operands + 1);
4584 return NULL;
4585 }
d02603dc 4586 token_start = l; /* After white space. */
29b0f896
AM		 4587 paren_not_balanced = 0;
4588 while (paren_not_balanced || *l != ',')
4589 {
4590 if (*l == END_OF_INSN)
4591 {
4592 if (paren_not_balanced)
4593 {
4594 if (!intel_syntax)
4595 as_bad (_("unbalanced parenthesis in operand %d."),
4596 i.operands + 1);
4597 else
4598 as_bad (_("unbalanced brackets in operand %d."),
4599 i.operands + 1);
4600 return NULL;
4601 }
4602 else
4603 break; /* we are done */
4604 }
d02603dc 4605 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4606 {
4607 as_bad (_("invalid character %s in operand %d"),
4608 output_invalid (*l),
4609 i.operands + 1);
4610 return NULL;
4611 }
4612 if (!intel_syntax)
4613 {
4614 if (*l == '(')
4615 ++paren_not_balanced;
4616 if (*l == ')')
4617 --paren_not_balanced;
4618 }
4619 else
4620 {
4621 if (*l == '[')
4622 ++paren_not_balanced;
4623 if (*l == ']')
4624 --paren_not_balanced;
4625 }
4626 l++;
4627 }
4628 if (l != token_start)
4629 { /* Yes, we've read in another operand. */
4630 unsigned int operand_ok;
4631 this_operand = i.operands++;
4632 if (i.operands > MAX_OPERANDS)
4633 {
4634 as_bad (_("spurious operands; (%d operands/instruction max)"),
4635 MAX_OPERANDS);
4636 return NULL;
4637 }
9d46ce34 4638 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4639 /* Now parse operand adding info to 'i' as we go along. */
4640 END_STRING_AND_SAVE (l);
4641
4642 if (intel_syntax)
4643 operand_ok =
4644 i386_intel_operand (token_start,
4645 intel_float_operand (mnemonic));
4646 else
a7619375 4647 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4648
4649 RESTORE_END_STRING (l);
4650 if (!operand_ok)
4651 return NULL;
4652 }
4653 else
4654 {
4655 if (expecting_operand)
4656 {
4657 expecting_operand_after_comma:
4658 as_bad (_("expecting operand after ','; got nothing"));
4659 return NULL;
4660 }
4661 if (*l == ',')
4662 {
4663 as_bad (_("expecting operand before ','; got nothing"));
4664 return NULL;
4665 }
4666 }
7f3f1ea2 4667
29b0f896
AM		 4668 /* Now *l must be either ',' or END_OF_INSN. */
4669 if (*l == ',')
4670 {
4671 if (*++l == END_OF_INSN)
4672 {
4673 /* Just skip it, if it's \n complain. */
4674 goto expecting_operand_after_comma;
4675 }
4676 expecting_operand = 1;
4677 }
4678 }
4679 return l;
4680}
7f3f1ea2 4681
050dfa73 4682static void
4d456e3d 4683swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4684{
4685 union i386_op temp_op;
40fb9820 4686 i386_operand_type temp_type;
050dfa73 4687 enum bfd_reloc_code_real temp_reloc;
4eed87de 4688
050dfa73
MM		 4689 temp_type = i.types[xchg2];
4690 i.types[xchg2] = i.types[xchg1];
4691 i.types[xchg1] = temp_type;
4692 temp_op = i.op[xchg2];
4693 i.op[xchg2] = i.op[xchg1];
4694 i.op[xchg1] = temp_op;
4695 temp_reloc = i.reloc[xchg2];
4696 i.reloc[xchg2] = i.reloc[xchg1];
4697 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4698
4699 if (i.mask)
4700 {
4701 if (i.mask->operand == xchg1)
4702 i.mask->operand = xchg2;
4703 else if (i.mask->operand == xchg2)
4704 i.mask->operand = xchg1;
4705 }
4706 if (i.broadcast)
4707 {
4708 if (i.broadcast->operand == xchg1)
4709 i.broadcast->operand = xchg2;
4710 else if (i.broadcast->operand == xchg2)
4711 i.broadcast->operand = xchg1;
4712 }
4713 if (i.rounding)
4714 {
4715 if (i.rounding->operand == xchg1)
4716 i.rounding->operand = xchg2;
4717 else if (i.rounding->operand == xchg2)
4718 i.rounding->operand = xchg1;
4719 }
050dfa73
MM		 4720}
4721
29b0f896 4722static void
e3bb37b5 4723swap_operands (void)
29b0f896 4724{
b7c61d9a 4725 switch (i.operands)
050dfa73 4726 {
c0f3af97 4727 case 5:
b7c61d9a 4728 case 4:
4d456e3d 4729 swap_2_operands (1, i.operands - 2);
1a0670f3 4730 /* Fall through. */
b7c61d9a
L		 4731 case 3:
4732 case 2:
4d456e3d 4733 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4734 break;
4735 default:
4736 abort ();
29b0f896 4737 }
29b0f896
AM		 4738
4739 if (i.mem_operands == 2)
4740 {
4741 const seg_entry *temp_seg;
4742 temp_seg = i.seg[0];
4743 i.seg[0] = i.seg[1];
4744 i.seg[1] = temp_seg;
4745 }
4746}
252b5132 4747
29b0f896
AM		 4748/* Try to ensure constant immediates are represented in the smallest
4749 opcode possible. */
4750static void
e3bb37b5 4751optimize_imm (void)
29b0f896
AM		 4752{
4753 char guess_suffix = 0;
4754 int op;
252b5132 4755
29b0f896
AM		 4756 if (i.suffix)
4757 guess_suffix = i.suffix;
4758 else if (i.reg_operands)
4759 {
4760 /* Figure out a suffix from the last register operand specified.
4761 We can't do this properly yet, ie. excluding InOutPortReg,
4762 but the following works for instructions with immediates.
4763 In any case, we can't set i.suffix yet. */
4764 for (op = i.operands; --op >= 0;)
dc821c5f 4765 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
7ab9ffdd 4766 {
40fb9820
L		 4767 guess_suffix = BYTE_MNEM_SUFFIX;
4768 break;
4769 }
dc821c5f 4770 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
252b5132 4771 {
40fb9820
L		 4772 guess_suffix = WORD_MNEM_SUFFIX;
4773 break;
4774 }
dc821c5f 4775 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
40fb9820
L		 4776 {
4777 guess_suffix = LONG_MNEM_SUFFIX;
4778 break;
4779 }
dc821c5f 4780 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
40fb9820
L		 4781 {
4782 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4783 break;
252b5132 4784 }
29b0f896
AM		 4785 }
4786 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4787 guess_suffix = WORD_MNEM_SUFFIX;
4788
4789 for (op = i.operands; --op >= 0;)
40fb9820 4790 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4791 {
4792 switch (i.op[op].imms->X_op)
252b5132 4793 {
29b0f896
AM		 4794 case O_constant:
4795 /* If a suffix is given, this operand may be shortened. */
4796 switch (guess_suffix)
252b5132 4797 {
29b0f896 4798 case LONG_MNEM_SUFFIX:
40fb9820
L		 4799 i.types[op].bitfield.imm32 = 1;
4800 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4801 break;
4802 case WORD_MNEM_SUFFIX:
40fb9820
L		 4803 i.types[op].bitfield.imm16 = 1;
4804 i.types[op].bitfield.imm32 = 1;
4805 i.types[op].bitfield.imm32s = 1;
4806 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4807 break;
4808 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4809 i.types[op].bitfield.imm8 = 1;
4810 i.types[op].bitfield.imm8s = 1;
4811 i.types[op].bitfield.imm16 = 1;
4812 i.types[op].bitfield.imm32 = 1;
4813 i.types[op].bitfield.imm32s = 1;
4814 i.types[op].bitfield.imm64 = 1;
29b0f896 4815 break;
252b5132 4816 }
252b5132 4817
29b0f896
AM		 4818 /* If this operand is at most 16 bits, convert it
4819 to a signed 16 bit number before trying to see
4820 whether it will fit in an even smaller size.
4821 This allows a 16-bit operand such as $0xffe0 to
4822 be recognised as within Imm8S range. */
40fb9820 4823 if ((i.types[op].bitfield.imm16)
29b0f896 4824 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4825 {
29b0f896
AM		 4826 i.op[op].imms->X_add_number =
4827 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4828 }
a28def75
L		 4829#ifdef BFD64
4830 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4831 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4832 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4833 == 0))
4834 {
4835 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4836 ^ ((offsetT) 1 << 31))
4837 - ((offsetT) 1 << 31));
4838 }
a28def75 4839#endif
40fb9820 4840 i.types[op]
c6fb90c8
L		 4841 = operand_type_or (i.types[op],
4842 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4843
29b0f896
AM		 4844 /* We must avoid matching of Imm32 templates when 64bit
4845 only immediate is available. */
4846 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4847 i.types[op].bitfield.imm32 = 0;
29b0f896 4848 break;
252b5132 4849
29b0f896
AM		 4850 case O_absent:
4851 case O_register:
4852 abort ();
4853
4854 /* Symbols and expressions. */
4855 default:
9cd96992
JB		 4856 /* Convert symbolic operand to proper sizes for matching, but don't
4857 prevent matching a set of insns that only supports sizes other
4858 than those matching the insn suffix. */
4859 {
40fb9820 4860 i386_operand_type mask, allowed;
d3ce72d0 4861 const insn_template *t;
9cd96992 4862
0dfbf9d7
L		 4863 operand_type_set (&mask, 0);
4864 operand_type_set (&allowed, 0);
40fb9820 4865
4eed87de
AM		 4866 for (t = current_templates->start;
4867 t < current_templates->end;
4868 ++t)
c6fb90c8
L		 4869 allowed = operand_type_or (allowed,
4870 t->operand_types[op]);
9cd96992
JB		 4871 switch (guess_suffix)
4872 {
4873 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4874 mask.bitfield.imm64 = 1;
4875 mask.bitfield.imm32s = 1;
9cd96992
JB		 4876 break;
4877 case LONG_MNEM_SUFFIX:
40fb9820 4878 mask.bitfield.imm32 = 1;
9cd96992
JB		 4879 break;
4880 case WORD_MNEM_SUFFIX:
40fb9820 4881 mask.bitfield.imm16 = 1;
9cd96992
JB		 4882 break;
4883 case BYTE_MNEM_SUFFIX:
40fb9820 4884 mask.bitfield.imm8 = 1;
9cd96992
JB		 4885 break;
4886 default:
9cd96992
JB		 4887 break;
4888 }
c6fb90c8 4889 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4890 if (!operand_type_all_zero (&allowed))
c6fb90c8 4891 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4892 }
29b0f896 4893 break;
252b5132 4894 }
29b0f896
AM		 4895 }
4896}
47926f60 4897
29b0f896
AM		 4898/* Try to use the smallest displacement type too. */
4899static void
e3bb37b5 4900optimize_disp (void)
29b0f896
AM		 4901{
4902 int op;
3e73aa7c 4903
29b0f896 4904 for (op = i.operands; --op >= 0;)
40fb9820 4905 if (operand_type_check (i.types[op], disp))
252b5132 4906 {
b300c311 4907 if (i.op[op].disps->X_op == O_constant)
252b5132 4908 {
91d6fa6a 4909 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4910
40fb9820 4911 if (i.types[op].bitfield.disp16
91d6fa6a 4912 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4913 {
4914 /* If this operand is at most 16 bits, convert
4915 to a signed 16 bit number and don't use 64bit
4916 displacement. */
91d6fa6a 4917 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4918 i.types[op].bitfield.disp64 = 0;
b300c311 4919 }
a28def75
L		 4920#ifdef BFD64
4921 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4922 if (i.types[op].bitfield.disp32
91d6fa6a 4923 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4924 {
4925 /* If this operand is at most 32 bits, convert
4926 to a signed 32 bit number and don't use 64bit
4927 displacement. */
91d6fa6a
NC		 4928 op_disp &= (((offsetT) 2 << 31) - 1);
4929 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4930 i.types[op].bitfield.disp64 = 0;
b300c311 4931 }
a28def75 4932#endif
91d6fa6a 4933 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4934 {
40fb9820
L		 4935 i.types[op].bitfield.disp8 = 0;
4936 i.types[op].bitfield.disp16 = 0;
4937 i.types[op].bitfield.disp32 = 0;
4938 i.types[op].bitfield.disp32s = 0;
4939 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4940 i.op[op].disps = 0;
4941 i.disp_operands--;
4942 }
4943 else if (flag_code == CODE_64BIT)
4944 {
91d6fa6a 4945 if (fits_in_signed_long (op_disp))
28a9d8f5 4946 {
40fb9820
L		 4947 i.types[op].bitfield.disp64 = 0;
4948 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4949 }
0e1147d9 4950 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4951 && fits_in_unsigned_long (op_disp))
40fb9820 4952 i.types[op].bitfield.disp32 = 1;
b300c311 4953 }
40fb9820
L		 4954 if ((i.types[op].bitfield.disp32
4955 || i.types[op].bitfield.disp32s
4956 || i.types[op].bitfield.disp16)
b5014f7a 4957 && fits_in_disp8 (op_disp))
40fb9820 4958 i.types[op].bitfield.disp8 = 1;
252b5132 4959 }
67a4f2b7
AO		 4960 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4961 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4962 {
4963 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4964 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4965 i.types[op].bitfield.disp8 = 0;
4966 i.types[op].bitfield.disp16 = 0;
4967 i.types[op].bitfield.disp32 = 0;
4968 i.types[op].bitfield.disp32s = 0;
4969 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4970 }
4971 else
b300c311 4972 /* We only support 64bit displacement on constants. */
40fb9820 4973 i.types[op].bitfield.disp64 = 0;
252b5132 4974 }
29b0f896
AM		 4975}
4976
6c30d220
L		 4977/* Check if operands are valid for the instruction. */
4978
4979static int
4980check_VecOperands (const insn_template *t)
4981{
43234a1e 4982 unsigned int op;
e2195274
JB		 4983 i386_cpu_flags cpu;
4984 static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
4985
4986 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
4987 any one operand are implicity requiring AVX512VL support if the actual
4988 operand size is YMMword or XMMword. Since this function runs after
4989 template matching, there's no need to check for YMMword/XMMword in
4990 the template. */
4991 cpu = cpu_flags_and (t->cpu_flags, avx512);
4992 if (!cpu_flags_all_zero (&cpu)
4993 && !t->cpu_flags.bitfield.cpuavx512vl
4994 && !cpu_arch_flags.bitfield.cpuavx512vl)
4995 {
4996 for (op = 0; op < t->operands; ++op)
4997 {
4998 if (t->operand_types[op].bitfield.zmmword
4999 && (i.types[op].bitfield.ymmword
5000 || i.types[op].bitfield.xmmword))
5001 {
5002 i.error = unsupported;
5003 return 1;
5004 }
5005 }
5006 }
43234a1e 5007
6c30d220
L		 5008 /* Without VSIB byte, we can't have a vector register for index. */
5009 if (!t->opcode_modifier.vecsib
5010 && i.index_reg
1b54b8d7
JB		 5011 && (i.index_reg->reg_type.bitfield.xmmword
5012 || i.index_reg->reg_type.bitfield.ymmword
5013 || i.index_reg->reg_type.bitfield.zmmword))
6c30d220
L		 5014 {
5015 i.error = unsupported_vector_index_register;
5016 return 1;
5017 }
5018
ad8ecc81
MZ		 5019 /* Check if default mask is allowed. */
5020 if (t->opcode_modifier.nodefmask
5021 && (!i.mask || i.mask->mask->reg_num == 0))
5022 {
5023 i.error = no_default_mask;
5024 return 1;
5025 }
5026
7bab8ab5
JB		 5027 /* For VSIB byte, we need a vector register for index, and all vector
5028 registers must be distinct. */
5029 if (t->opcode_modifier.vecsib)
5030 {
5031 if (!i.index_reg
6c30d220 5032 || !((t->opcode_modifier.vecsib == VecSIB128
1b54b8d7 5033 && i.index_reg->reg_type.bitfield.xmmword)
6c30d220 5034 || (t->opcode_modifier.vecsib == VecSIB256
1b54b8d7 5035 && i.index_reg->reg_type.bitfield.ymmword)
43234a1e 5036 || (t->opcode_modifier.vecsib == VecSIB512
1b54b8d7 5037 && i.index_reg->reg_type.bitfield.zmmword)))
7bab8ab5
JB		 5038 {
5039 i.error = invalid_vsib_address;
5040 return 1;
5041 }
5042
43234a1e
L		 5043 gas_assert (i.reg_operands == 2 || i.mask);
5044 if (i.reg_operands == 2 && !i.mask)
5045 {
1b54b8d7
JB		 5046 gas_assert (i.types[0].bitfield.regsimd);
5047 gas_assert (i.types[0].bitfield.xmmword
5048 || i.types[0].bitfield.ymmword);
5049 gas_assert (i.types[2].bitfield.regsimd);
5050 gas_assert (i.types[2].bitfield.xmmword
5051 || i.types[2].bitfield.ymmword);
43234a1e
L		 5052 if (operand_check == check_none)
5053 return 0;
5054 if (register_number (i.op[0].regs)
5055 != register_number (i.index_reg)
5056 && register_number (i.op[2].regs)
5057 != register_number (i.index_reg)
5058 && register_number (i.op[0].regs)
5059 != register_number (i.op[2].regs))
5060 return 0;
5061 if (operand_check == check_error)
5062 {
5063 i.error = invalid_vector_register_set;
5064 return 1;
5065 }
5066 as_warn (_("mask, index, and destination registers should be distinct"));
5067 }
8444f82a
MZ		 5068 else if (i.reg_operands == 1 && i.mask)
5069 {
1b54b8d7
JB		 5070 if (i.types[1].bitfield.regsimd
5071 && (i.types[1].bitfield.xmmword
5072 || i.types[1].bitfield.ymmword
5073 || i.types[1].bitfield.zmmword)
8444f82a
MZ		 5074 && (register_number (i.op[1].regs)
5075 == register_number (i.index_reg)))
5076 {
5077 if (operand_check == check_error)
5078 {
5079 i.error = invalid_vector_register_set;
5080 return 1;
5081 }
5082 if (operand_check != check_none)
5083 as_warn (_("index and destination registers should be distinct"));
5084 }
5085 }
43234a1e 5086 }
7bab8ab5 5087
43234a1e
L		 5088 /* Check if broadcast is supported by the instruction and is applied
5089 to the memory operand. */
5090 if (i.broadcast)
5091 {
8e6e0792 5092 i386_operand_type type, overlap;
43234a1e
L		 5093
5094 /* Check if specified broadcast is supported in this instruction,
c39e5b26 5095 and it's applied to memory operand of DWORD or QWORD type. */
32546502 5096 op = i.broadcast->operand;
8e6e0792 5097 if (!t->opcode_modifier.broadcast
32546502 5098 || !i.types[op].bitfield.mem
c39e5b26
JB		 5099 || (!i.types[op].bitfield.unspecified
5100 && (t->operand_types[op].bitfield.dword
5101 ? !i.types[op].bitfield.dword
5102 : !i.types[op].bitfield.qword)))
43234a1e
L		 5103 {
5104 bad_broadcast:
5105 i.error = unsupported_broadcast;
5106 return 1;
5107 }
8e6e0792
JB		 5108
5109 operand_type_set (&type, 0);
c39e5b26 5110 switch ((t->operand_types[op].bitfield.dword ? 4 : 8) * i.broadcast->type)
8e6e0792
JB		 5111 {
5112 case 8:
5113 type.bitfield.qword = 1;
5114 break;
5115 case 16:
5116 type.bitfield.xmmword = 1;
5117 break;
5118 case 32:
5119 type.bitfield.ymmword = 1;
5120 break;
5121 case 64:
5122 type.bitfield.zmmword = 1;
5123 break;
5124 default:
5125 goto bad_broadcast;
5126 }
5127
5128 overlap = operand_type_and (type, t->operand_types[op]);
5129 if (operand_type_all_zero (&overlap))
5130 goto bad_broadcast;
5131
5132 if (t->opcode_modifier.checkregsize)
5133 {
5134 unsigned int j;
5135
e2195274 5136 type.bitfield.baseindex = 1;
8e6e0792
JB		 5137 for (j = 0; j < i.operands; ++j)
5138 {
5139 if (j != op
5140 && !operand_type_register_match(i.types[j],
5141 t->operand_types[j],
5142 type,
5143 t->operand_types[op]))
5144 goto bad_broadcast;
5145 }
5146 }
43234a1e
L		 5147 }
5148 /* If broadcast is supported in this instruction, we need to check if
5149 operand of one-element size isn't specified without broadcast. */
5150 else if (t->opcode_modifier.broadcast && i.mem_operands)
5151 {
5152 /* Find memory operand. */
5153 for (op = 0; op < i.operands; op++)
5154 if (operand_type_check (i.types[op], anymem))
5155 break;
5156 gas_assert (op < i.operands);
5157 /* Check size of the memory operand. */
c39e5b26
JB		 5158 if (t->operand_types[op].bitfield.dword
5159 ? i.types[op].bitfield.dword
5160 : i.types[op].bitfield.qword)
43234a1e
L		 5161 {
5162 i.error = broadcast_needed;
5163 return 1;
5164 }
5165 }
c39e5b26
JB		 5166 else
5167 op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
43234a1e
L		 5168
5169 /* Check if requested masking is supported. */
5170 if (i.mask
5171 && (!t->opcode_modifier.masking
5172 || (i.mask->zeroing
5173 && t->opcode_modifier.masking == MERGING_MASKING)))
5174 {
5175 i.error = unsupported_masking;
5176 return 1;
5177 }
5178
5179 /* Check if masking is applied to dest operand. */
5180 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5181 {
5182 i.error = mask_not_on_destination;
5183 return 1;
5184 }
5185
43234a1e
L		 5186 /* Check RC/SAE. */
5187 if (i.rounding)
5188 {
5189 if ((i.rounding->type != saeonly
5190 && !t->opcode_modifier.staticrounding)
5191 || (i.rounding->type == saeonly
5192 && (t->opcode_modifier.staticrounding
5193 || !t->opcode_modifier.sae)))
5194 {
5195 i.error = unsupported_rc_sae;
5196 return 1;
5197 }
5198 /* If the instruction has several immediate operands and one of
5199 them is rounding, the rounding operand should be the last
5200 immediate operand. */
5201 if (i.imm_operands > 1
5202 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 5203 {
43234a1e 5204 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 5205 return 1;
5206 }
6c30d220
L		 5207 }
5208
43234a1e 5209 /* Check vector Disp8 operand. */
b5014f7a
JB		 5210 if (t->opcode_modifier.disp8memshift
5211 && i.disp_encoding != disp_encoding_32bit)
43234a1e
L		 5212 {
5213 if (i.broadcast)
c39e5b26 5214 i.memshift = t->operand_types[op].bitfield.dword ? 2 : 3;
7091c612 5215 else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL)
43234a1e 5216 i.memshift = t->opcode_modifier.disp8memshift;
7091c612
JB		 5217 else
5218 {
5219 const i386_operand_type *type = NULL;
5220
5221 i.memshift = 0;
5222 for (op = 0; op < i.operands; op++)
5223 if (operand_type_check (i.types[op], anymem))
5224 {
5225 if (t->operand_types[op].bitfield.xmmword
5226 + t->operand_types[op].bitfield.ymmword
5227 + t->operand_types[op].bitfield.zmmword <= 1)
5228 type = &t->operand_types[op];
5229 else if (!i.types[op].bitfield.unspecified)
5230 type = &i.types[op];
5231 }
5232 else if (i.types[op].bitfield.regsimd)
5233 {
5234 if (i.types[op].bitfield.zmmword)
5235 i.memshift = 6;
5236 else if (i.types[op].bitfield.ymmword && i.memshift < 5)
5237 i.memshift = 5;
5238 else if (i.types[op].bitfield.xmmword && i.memshift < 4)
5239 i.memshift = 4;
5240 }
5241
5242 if (type)
5243 {
5244 if (type->bitfield.zmmword)
5245 i.memshift = 6;
5246 else if (type->bitfield.ymmword)
5247 i.memshift = 5;
5248 else if (type->bitfield.xmmword)
5249 i.memshift = 4;
5250 }
5251
5252 /* For the check in fits_in_disp8(). */
5253 if (i.memshift == 0)
5254 i.memshift = -1;
5255 }
43234a1e
L		 5256
5257 for (op = 0; op < i.operands; op++)
5258 if (operand_type_check (i.types[op], disp)
5259 && i.op[op].disps->X_op == O_constant)
5260 {
b5014f7a 5261 if (fits_in_disp8 (i.op[op].disps->X_add_number))
43234a1e 5262 {
b5014f7a
JB		 5263 i.types[op].bitfield.disp8 = 1;
5264 return 0;
43234a1e 5265 }
b5014f7a 5266 i.types[op].bitfield.disp8 = 0;
43234a1e
L		 5267 }
5268 }
b5014f7a
JB		 5269
5270 i.memshift = 0;
43234a1e 5271
6c30d220
L		 5272 return 0;
5273}
5274
43f3e2ee 5275/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 5276 operand types. */
5277
5278static int
5279VEX_check_operands (const insn_template *t)
5280{
86fa6981 5281 if (i.vec_encoding == vex_encoding_evex)
43234a1e 5282 {
86fa6981 5283 /* This instruction must be encoded with EVEX prefix. */
e771e7c9 5284 if (!is_evex_encoding (t))
86fa6981
L		 5285 {
5286 i.error = unsupported;
5287 return 1;
5288 }
5289 return 0;
43234a1e
L		 5290 }
5291
a683cc34 5292 if (!t->opcode_modifier.vex)
86fa6981
L		 5293 {
5294 /* This instruction template doesn't have VEX prefix. */
5295 if (i.vec_encoding != vex_encoding_default)
5296 {
5297 i.error = unsupported;
5298 return 1;
5299 }
5300 return 0;
5301 }
a683cc34
SP		 5302
5303 /* Only check VEX_Imm4, which must be the first operand. */
5304 if (t->operand_types[0].bitfield.vec_imm4)
5305 {
5306 if (i.op[0].imms->X_op != O_constant
5307 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 5308 {
a65babc9 5309 i.error = bad_imm4;
891edac4
L		 5310 return 1;
5311 }
a683cc34
SP		 5312
5313 /* Turn off Imm8 so that update_imm won't complain. */
5314 i.types[0] = vec_imm4;
5315 }
5316
5317 return 0;
5318}
5319
d3ce72d0 5320static const insn_template *
83b16ac6 5321match_template (char mnem_suffix)
29b0f896
AM		 5322{
5323 /* Points to template once we've found it. */
d3ce72d0 5324 const insn_template *t;
40fb9820 5325 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 5326 i386_operand_type overlap4;
29b0f896 5327 unsigned int found_reverse_match;
83b16ac6 5328 i386_opcode_modifier suffix_check, mnemsuf_check;
40fb9820 5329 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 5330 int addr_prefix_disp;
a5c311ca 5331 unsigned int j;
3ac21baa 5332 unsigned int found_cpu_match, size_match;
45664ddb 5333 unsigned int check_register;
5614d22c 5334 enum i386_error specific_error = 0;
29b0f896 5335
c0f3af97
L		 5336#if MAX_OPERANDS != 5
5337# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 5338#endif
5339
29b0f896 5340 found_reverse_match = 0;
539e75ad 5341 addr_prefix_disp = -1;
40fb9820
L		 5342
5343 memset (&suffix_check, 0, sizeof (suffix_check));
e2195274
JB		 5344 if (intel_syntax && i.broadcast)
5345 /* nothing */;
5346 else if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5347 suffix_check.no_bsuf = 1;
5348 else if (i.suffix == WORD_MNEM_SUFFIX)
5349 suffix_check.no_wsuf = 1;
5350 else if (i.suffix == SHORT_MNEM_SUFFIX)
5351 suffix_check.no_ssuf = 1;
5352 else if (i.suffix == LONG_MNEM_SUFFIX)
5353 suffix_check.no_lsuf = 1;
5354 else if (i.suffix == QWORD_MNEM_SUFFIX)
5355 suffix_check.no_qsuf = 1;
5356 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 5357 suffix_check.no_ldsuf = 1;
29b0f896 5358
83b16ac6
JB		 5359 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5360 if (intel_syntax)
5361 {
5362 switch (mnem_suffix)
5363 {
5364 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5365 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5366 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5367 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5368 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5369 }
5370 }
5371
01559ecc
L		 5372 /* Must have right number of operands. */
5373 i.error = number_of_operands_mismatch;
5374
45aa61fe 5375 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 5376 {
539e75ad
L		 5377 addr_prefix_disp = -1;
5378
29b0f896
AM		 5379 if (i.operands != t->operands)
5380 continue;
5381
50aecf8c 5382 /* Check processor support. */
a65babc9 5383 i.error = unsupported;
c0f3af97
L		 5384 found_cpu_match = (cpu_flags_match (t)
5385 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 5386 if (!found_cpu_match)
5387 continue;
5388
e1d4d893 5389 /* Check AT&T mnemonic. */
a65babc9 5390 i.error = unsupported_with_intel_mnemonic;
e1d4d893 5391 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 5392 continue;
5393
e92bae62 5394 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
a65babc9 5395 i.error = unsupported_syntax;
5c07affc 5396 if ((intel_syntax && t->opcode_modifier.attsyntax)
e92bae62
L		 5397 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5398 || (intel64 && t->opcode_modifier.amd64)
5399 || (!intel64 && t->opcode_modifier.intel64))
1efbbeb4
L		 5400 continue;
5401
20592a94 5402 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 5403 i.error = invalid_instruction_suffix;
567e4e96
L		 5404 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5405 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5406 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5407 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5408 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5409 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5410 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896 5411 continue;
83b16ac6
JB		 5412 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5413 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5414 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5415 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5416 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5417 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5418 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5419 continue;
29b0f896 5420
3ac21baa
JB		 5421 size_match = operand_size_match (t);
5422 if (!size_match)
7d5e4556 5423 continue;
539e75ad 5424
5c07affc
L		 5425 for (j = 0; j < MAX_OPERANDS; j++)
5426 operand_types[j] = t->operand_types[j];
5427
45aa61fe
AM		 5428 /* In general, don't allow 64-bit operands in 32-bit mode. */
5429 if (i.suffix == QWORD_MNEM_SUFFIX
5430 && flag_code != CODE_64BIT
5431 && (intel_syntax
40fb9820 5432 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 5433 && !intel_float_operand (t->name))
5434 : intel_float_operand (t->name) != 2)
40fb9820 5435 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5436 && !operand_types[0].bitfield.regsimd)
40fb9820 5437 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5438 && !operand_types[t->operands > 1].bitfield.regsimd))
45aa61fe
AM		 5439 && (t->base_opcode != 0x0fc7
5440 || t->extension_opcode != 1 /* cmpxchg8b */))
5441 continue;
5442
192dc9c6
JB		 5443 /* In general, don't allow 32-bit operands on pre-386. */
5444 else if (i.suffix == LONG_MNEM_SUFFIX
5445 && !cpu_arch_flags.bitfield.cpui386
5446 && (intel_syntax
5447 ? (!t->opcode_modifier.ignoresize
5448 && !intel_float_operand (t->name))
5449 : intel_float_operand (t->name) != 2)
5450 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5451 && !operand_types[0].bitfield.regsimd)
192dc9c6 5452 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5453 && !operand_types[t->operands > 1].bitfield.regsimd)))
192dc9c6
JB		 5454 continue;
5455
29b0f896 5456 /* Do not verify operands when there are none. */
50aecf8c 5457 else
29b0f896 5458 {
c6fb90c8 5459 if (!t->operands)
2dbab7d5
L		 5460 /* We've found a match; break out of loop. */
5461 break;
29b0f896 5462 }
252b5132 5463
539e75ad
L		 5464 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5465 into Disp32/Disp16/Disp32 operand. */
5466 if (i.prefix[ADDR_PREFIX] != 0)
5467 {
40fb9820 5468 /* There should be only one Disp operand. */
539e75ad
L		 5469 switch (flag_code)
5470 {
5471 case CODE_16BIT:
40fb9820
L		 5472 for (j = 0; j < MAX_OPERANDS; j++)
5473 {
5474 if (operand_types[j].bitfield.disp16)
5475 {
5476 addr_prefix_disp = j;
5477 operand_types[j].bitfield.disp32 = 1;
5478 operand_types[j].bitfield.disp16 = 0;
5479 break;
5480 }
5481 }
539e75ad
L		 5482 break;
5483 case CODE_32BIT:
40fb9820
L		 5484 for (j = 0; j < MAX_OPERANDS; j++)
5485 {
5486 if (operand_types[j].bitfield.disp32)
5487 {
5488 addr_prefix_disp = j;
5489 operand_types[j].bitfield.disp32 = 0;
5490 operand_types[j].bitfield.disp16 = 1;
5491 break;
5492 }
5493 }
539e75ad
L		 5494 break;
5495 case CODE_64BIT:
40fb9820
L		 5496 for (j = 0; j < MAX_OPERANDS; j++)
5497 {
5498 if (operand_types[j].bitfield.disp64)
5499 {
5500 addr_prefix_disp = j;
5501 operand_types[j].bitfield.disp64 = 0;
5502 operand_types[j].bitfield.disp32 = 1;
5503 break;
5504 }
5505 }
539e75ad
L		 5506 break;
5507 }
539e75ad
L		 5508 }
5509
02a86693
L		 5510 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5511 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5512 continue;
5513
56ffb741 5514 /* We check register size if needed. */
e2195274
JB		 5515 if (t->opcode_modifier.checkregsize)
5516 {
5517 check_register = (1 << t->operands) - 1;
5518 if (i.broadcast)
5519 check_register &= ~(1 << i.broadcast->operand);
5520 }
5521 else
5522 check_register = 0;
5523
c6fb90c8 5524 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 5525 switch (t->operands)
5526 {
5527 case 1:
40fb9820 5528 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 5529 continue;
5530 break;
5531 case 2:
33eaf5de 5532 /* xchg %eax, %eax is a special case. It is an alias for nop
8b38ad71
L		 5533 only in 32bit mode and we can use opcode 0x90. In 64bit
5534 mode, we can't use 0x90 for xchg %eax, %eax since it should
5535 zero-extend %eax to %rax. */
5536 if (flag_code == CODE_64BIT
5537 && t->base_opcode == 0x90
0dfbf9d7
L		 5538 && operand_type_equal (&i.types [0], &acc32)
5539 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 5540 continue;
1212781b
JB		 5541 /* xrelease mov %eax, <disp> is another special case. It must not
5542 match the accumulator-only encoding of mov. */
5543 if (flag_code != CODE_64BIT
5544 && i.hle_prefix
5545 && t->base_opcode == 0xa0
5546 && i.types[0].bitfield.acc
5547 && operand_type_check (i.types[1], anymem))
5548 continue;
3ac21baa
JB		 5549 if (!(size_match & MATCH_STRAIGHT))
5550 goto check_reverse;
86fa6981
L		 5551 /* If we want store form, we reverse direction of operands. */
5552 if (i.dir_encoding == dir_encoding_store
5553 && t->opcode_modifier.d)
5554 goto check_reverse;
1a0670f3 5555 /* Fall through. */
b6169b20 5556
29b0f896 5557 case 3:
86fa6981
L		 5558 /* If we want store form, we skip the current load. */
5559 if (i.dir_encoding == dir_encoding_store
5560 && i.mem_operands == 0
5561 && t->opcode_modifier.load)
fa99fab2 5562 continue;
1a0670f3 5563 /* Fall through. */
f48ff2ae 5564 case 4:
c0f3af97 5565 case 5:
c6fb90c8 5566 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 5567 if (!operand_type_match (overlap0, i.types[0])
5568 || !operand_type_match (overlap1, i.types[1])
e2195274 5569 || ((check_register & 3) == 3
dc821c5f 5570 && !operand_type_register_match (i.types[0],
40fb9820 5571 operand_types[0],
dc821c5f 5572 i.types[1],
40fb9820 5573 operand_types[1])))
29b0f896
AM		 5574 {
5575 /* Check if other direction is valid ... */
38e314eb 5576 if (!t->opcode_modifier.d)
29b0f896
AM		 5577 continue;
5578
b6169b20 5579check_reverse:
3ac21baa
JB		 5580 if (!(size_match & MATCH_REVERSE))
5581 continue;
29b0f896 5582 /* Try reversing direction of operands. */
c6fb90c8
L		 5583 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5584 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 5585 if (!operand_type_match (overlap0, i.types[0])
5586 || !operand_type_match (overlap1, i.types[1])
45664ddb 5587 || (check_register
dc821c5f 5588 && !operand_type_register_match (i.types[0],
45664ddb 5589 operand_types[1],
45664ddb
L		 5590 i.types[1],
5591 operand_types[0])))
29b0f896
AM		 5592 {
5593 /* Does not match either direction. */
5594 continue;
5595 }
38e314eb 5596 /* found_reverse_match holds which of D or FloatR
29b0f896 5597 we've found. */
38e314eb
JB		 5598 if (!t->opcode_modifier.d)
5599 found_reverse_match = 0;
5600 else if (operand_types[0].bitfield.tbyte)
8a2ed489
L		 5601 found_reverse_match = Opcode_FloatD;
5602 else
38e314eb 5603 found_reverse_match = Opcode_D;
40fb9820 5604 if (t->opcode_modifier.floatr)
8a2ed489 5605 found_reverse_match |= Opcode_FloatR;
29b0f896 5606 }
f48ff2ae 5607 else
29b0f896 5608 {
f48ff2ae 5609 /* Found a forward 2 operand match here. */
d1cbb4db
L		 5610 switch (t->operands)
5611 {
c0f3af97
L		 5612 case 5:
5613 overlap4 = operand_type_and (i.types[4],
5614 operand_types[4]);
1a0670f3 5615 /* Fall through. */
d1cbb4db 5616 case 4:
c6fb90c8
L		 5617 overlap3 = operand_type_and (i.types[3],
5618 operand_types[3]);
1a0670f3 5619 /* Fall through. */
d1cbb4db 5620 case 3:
c6fb90c8
L		 5621 overlap2 = operand_type_and (i.types[2],
5622 operand_types[2]);
d1cbb4db
L		 5623 break;
5624 }
29b0f896 5625
f48ff2ae
L		 5626 switch (t->operands)
5627 {
c0f3af97
L		 5628 case 5:
5629 if (!operand_type_match (overlap4, i.types[4])
dc821c5f 5630 || !operand_type_register_match (i.types[3],
c0f3af97 5631 operand_types[3],
c0f3af97
L		 5632 i.types[4],
5633 operand_types[4]))
5634 continue;
1a0670f3 5635 /* Fall through. */
f48ff2ae 5636 case 4:
40fb9820 5637 if (!operand_type_match (overlap3, i.types[3])
e2195274
JB		 5638 || ((check_register & 0xa) == 0xa
5639 && !operand_type_register_match (i.types[1],
f7768225
JB		 5640 operand_types[1],
5641 i.types[3],
e2195274
JB		 5642 operand_types[3]))
5643 || ((check_register & 0xc) == 0xc
5644 && !operand_type_register_match (i.types[2],
5645 operand_types[2],
5646 i.types[3],
5647 operand_types[3])))
f48ff2ae 5648 continue;
1a0670f3 5649 /* Fall through. */
f48ff2ae
L		 5650 case 3:
5651 /* Here we make use of the fact that there are no
23e42951 5652 reverse match 3 operand instructions. */
40fb9820 5653 if (!operand_type_match (overlap2, i.types[2])
e2195274
JB		 5654 || ((check_register & 5) == 5
5655 && !operand_type_register_match (i.types[0],
23e42951
JB		 5656 operand_types[0],
5657 i.types[2],
e2195274
JB		 5658 operand_types[2]))
5659 || ((check_register & 6) == 6
5660 && !operand_type_register_match (i.types[1],
5661 operand_types[1],
5662 i.types[2],
5663 operand_types[2])))
f48ff2ae
L		 5664 continue;
5665 break;
5666 }
29b0f896 5667 }
f48ff2ae 5668 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5669 slip through to break. */
5670 }
3629bb00 5671 if (!found_cpu_match)
29b0f896
AM		 5672 {
5673 found_reverse_match = 0;
5674 continue;
5675 }
c0f3af97 5676
5614d22c
JB		 5677 /* Check if vector and VEX operands are valid. */
5678 if (check_VecOperands (t) || VEX_check_operands (t))
5679 {
5680 specific_error = i.error;
5681 continue;
5682 }
a683cc34 5683
29b0f896
AM		 5684 /* We've found a match; break out of loop. */
5685 break;
5686 }
5687
5688 if (t == current_templates->end)
5689 {
5690 /* We found no match. */
a65babc9 5691 const char *err_msg;
5614d22c 5692 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5693 {
5694 default:
5695 abort ();
86e026a4 5696 case operand_size_mismatch:
a65babc9
L		 5697 err_msg = _("operand size mismatch");
5698 break;
5699 case operand_type_mismatch:
5700 err_msg = _("operand type mismatch");
5701 break;
5702 case register_type_mismatch:
5703 err_msg = _("register type mismatch");
5704 break;
5705 case number_of_operands_mismatch:
5706 err_msg = _("number of operands mismatch");
5707 break;
5708 case invalid_instruction_suffix:
5709 err_msg = _("invalid instruction suffix");
5710 break;
5711 case bad_imm4:
4a2608e3 5712 err_msg = _("constant doesn't fit in 4 bits");
a65babc9 5713 break;
a65babc9
L		 5714 case unsupported_with_intel_mnemonic:
5715 err_msg = _("unsupported with Intel mnemonic");
5716 break;
5717 case unsupported_syntax:
5718 err_msg = _("unsupported syntax");
5719 break;
5720 case unsupported:
35262a23 5721 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5722 current_templates->start->name);
5723 return NULL;
6c30d220
L		 5724 case invalid_vsib_address:
5725 err_msg = _("invalid VSIB address");
5726 break;
7bab8ab5
JB		 5727 case invalid_vector_register_set:
5728 err_msg = _("mask, index, and destination registers must be distinct");
5729 break;
6c30d220
L		 5730 case unsupported_vector_index_register:
5731 err_msg = _("unsupported vector index register");
5732 break;
43234a1e
L		 5733 case unsupported_broadcast:
5734 err_msg = _("unsupported broadcast");
5735 break;
5736 case broadcast_not_on_src_operand:
5737 err_msg = _("broadcast not on source memory operand");
5738 break;
5739 case broadcast_needed:
5740 err_msg = _("broadcast is needed for operand of such type");
5741 break;
5742 case unsupported_masking:
5743 err_msg = _("unsupported masking");
5744 break;
5745 case mask_not_on_destination:
5746 err_msg = _("mask not on destination operand");
5747 break;
5748 case no_default_mask:
5749 err_msg = _("default mask isn't allowed");
5750 break;
5751 case unsupported_rc_sae:
5752 err_msg = _("unsupported static rounding/sae");
5753 break;
5754 case rc_sae_operand_not_last_imm:
5755 if (intel_syntax)
5756 err_msg = _("RC/SAE operand must precede immediate operands");
5757 else
5758 err_msg = _("RC/SAE operand must follow immediate operands");
5759 break;
5760 case invalid_register_operand:
5761 err_msg = _("invalid register operand");
5762 break;
a65babc9
L		 5763 }
5764 as_bad (_("%s for `%s'"), err_msg,
891edac4 5765 current_templates->start->name);
fa99fab2 5766 return NULL;
29b0f896 5767 }
252b5132 5768
29b0f896
AM		 5769 if (!quiet_warnings)
5770 {
5771 if (!intel_syntax
40fb9820
L		 5772 && (i.types[0].bitfield.jumpabsolute
5773 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5774 {
5775 as_warn (_("indirect %s without `*'"), t->name);
5776 }
5777
40fb9820
L		 5778 if (t->opcode_modifier.isprefix
5779 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5780 {
5781 /* Warn them that a data or address size prefix doesn't
5782 affect assembly of the next line of code. */
5783 as_warn (_("stand-alone `%s' prefix"), t->name);
5784 }
5785 }
5786
5787 /* Copy the template we found. */
5788 i.tm = *t;
539e75ad
L		 5789
5790 if (addr_prefix_disp != -1)
5791 i.tm.operand_types[addr_prefix_disp]
5792 = operand_types[addr_prefix_disp];
5793
29b0f896
AM		 5794 if (found_reverse_match)
5795 {
5796 /* If we found a reverse match we must alter the opcode
5797 direction bit. found_reverse_match holds bits to change
5798 (different for int & float insns). */
5799
5800 i.tm.base_opcode ^= found_reverse_match;
5801
539e75ad
L		 5802 i.tm.operand_types[0] = operand_types[1];
5803 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5804 }
5805
fa99fab2 5806 return t;
29b0f896
AM		 5807}
5808
5809static int
e3bb37b5 5810check_string (void)
29b0f896 5811{
40fb9820
L		 5812 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5813 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5814 {
5815 if (i.seg[0] != NULL && i.seg[0] != &es)
5816 {
a87af027 5817 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5818 i.tm.name,
a87af027
JB		 5819 mem_op + 1,
5820 register_prefix);
29b0f896
AM		 5821 return 0;
5822 }
5823 /* There's only ever one segment override allowed per instruction.
5824 This instruction possibly has a legal segment override on the
5825 second operand, so copy the segment to where non-string
5826 instructions store it, allowing common code. */
5827 i.seg[0] = i.seg[1];
5828 }
40fb9820 5829 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5830 {
5831 if (i.seg[1] != NULL && i.seg[1] != &es)
5832 {
a87af027 5833 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5834 i.tm.name,
a87af027
JB		 5835 mem_op + 2,
5836 register_prefix);
29b0f896
AM		 5837 return 0;
5838 }
5839 }
5840 return 1;
5841}
5842
5843static int
543613e9 5844process_suffix (void)
29b0f896
AM		 5845{
5846 /* If matched instruction specifies an explicit instruction mnemonic
5847 suffix, use it. */
40fb9820
L		 5848 if (i.tm.opcode_modifier.size16)
5849 i.suffix = WORD_MNEM_SUFFIX;
5850 else if (i.tm.opcode_modifier.size32)
5851 i.suffix = LONG_MNEM_SUFFIX;
5852 else if (i.tm.opcode_modifier.size64)
5853 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5854 else if (i.reg_operands)
5855 {
5856 /* If there's no instruction mnemonic suffix we try to invent one
5857 based on register operands. */
5858 if (!i.suffix)
5859 {
5860 /* We take i.suffix from the last register operand specified,
5861 Destination register type is more significant than source
381d071f
L		 5862 register type. crc32 in SSE4.2 prefers source register
5863 type. */
5864 if (i.tm.base_opcode == 0xf20f38f1)
5865 {
dc821c5f 5866 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
40fb9820 5867 i.suffix = WORD_MNEM_SUFFIX;
dc821c5f 5868 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
40fb9820 5869 i.suffix = LONG_MNEM_SUFFIX;
dc821c5f 5870 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
40fb9820 5871 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5872 }
9344ff29 5873 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5874 {
dc821c5f 5875 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
20592a94
L		 5876 i.suffix = BYTE_MNEM_SUFFIX;
5877 }
381d071f
L		 5878
5879 if (!i.suffix)
5880 {
5881 int op;
5882
20592a94
L		 5883 if (i.tm.base_opcode == 0xf20f38f1
5884 || i.tm.base_opcode == 0xf20f38f0)
5885 {
5886 /* We have to know the operand size for crc32. */
5887 as_bad (_("ambiguous memory operand size for `%s`"),
5888 i.tm.name);
5889 return 0;
5890 }
5891
381d071f 5892 for (op = i.operands; --op >= 0;)
b76bc5d5
JB		 5893 if (!i.tm.operand_types[op].bitfield.inoutportreg
5894 && !i.tm.operand_types[op].bitfield.shiftcount)
381d071f 5895 {
8819ada6
JB		 5896 if (!i.types[op].bitfield.reg)
5897 continue;
5898 if (i.types[op].bitfield.byte)
5899 i.suffix = BYTE_MNEM_SUFFIX;
5900 else if (i.types[op].bitfield.word)
5901 i.suffix = WORD_MNEM_SUFFIX;
5902 else if (i.types[op].bitfield.dword)
5903 i.suffix = LONG_MNEM_SUFFIX;
5904 else if (i.types[op].bitfield.qword)
5905 i.suffix = QWORD_MNEM_SUFFIX;
5906 else
5907 continue;
5908 break;
381d071f
L		 5909 }
5910 }
29b0f896
AM		 5911 }
5912 else if (i.suffix == BYTE_MNEM_SUFFIX)
5913 {
2eb952a4
L		 5914 if (intel_syntax
5915 && i.tm.opcode_modifier.ignoresize
5916 && i.tm.opcode_modifier.no_bsuf)
5917 i.suffix = 0;
5918 else if (!check_byte_reg ())
29b0f896
AM		 5919 return 0;
5920 }
5921 else if (i.suffix == LONG_MNEM_SUFFIX)
5922 {
2eb952a4
L		 5923 if (intel_syntax
5924 && i.tm.opcode_modifier.ignoresize
9f123b91
JB		 5925 && i.tm.opcode_modifier.no_lsuf
5926 && !i.tm.opcode_modifier.todword
5927 && !i.tm.opcode_modifier.toqword)
2eb952a4
L		 5928 i.suffix = 0;
5929 else if (!check_long_reg ())
29b0f896
AM		 5930 return 0;
5931 }
5932 else if (i.suffix == QWORD_MNEM_SUFFIX)
5933 {
955e1e6a
L		 5934 if (intel_syntax
5935 && i.tm.opcode_modifier.ignoresize
9f123b91
JB		 5936 && i.tm.opcode_modifier.no_qsuf
5937 && !i.tm.opcode_modifier.todword
5938 && !i.tm.opcode_modifier.toqword)
955e1e6a
L		 5939 i.suffix = 0;
5940 else if (!check_qword_reg ())
29b0f896
AM		 5941 return 0;
5942 }
5943 else if (i.suffix == WORD_MNEM_SUFFIX)
5944 {
2eb952a4
L		 5945 if (intel_syntax
5946 && i.tm.opcode_modifier.ignoresize
5947 && i.tm.opcode_modifier.no_wsuf)
5948 i.suffix = 0;
5949 else if (!check_word_reg ())
29b0f896
AM		 5950 return 0;
5951 }
40fb9820 5952 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5953 /* Do nothing if the instruction is going to ignore the prefix. */
5954 ;
5955 else
5956 abort ();
5957 }
40fb9820 5958 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5959 && !i.suffix
5960 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5961 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5962 {
5963 i.suffix = stackop_size;
5964 }
9306ca4a
JB		 5965 else if (intel_syntax
5966 && !i.suffix
40fb9820
L		 5967 && (i.tm.operand_types[0].bitfield.jumpabsolute
5968 || i.tm.opcode_modifier.jumpbyte
5969 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5970 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5971 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5972 {
5973 switch (flag_code)
5974 {
5975 case CODE_64BIT:
40fb9820 5976 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5977 {
5978 i.suffix = QWORD_MNEM_SUFFIX;
5979 break;
5980 }
1a0670f3 5981 /* Fall through. */
9306ca4a 5982 case CODE_32BIT:
40fb9820 5983 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5984 i.suffix = LONG_MNEM_SUFFIX;
5985 break;
5986 case CODE_16BIT:
40fb9820 5987 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5988 i.suffix = WORD_MNEM_SUFFIX;
5989 break;
5990 }
5991 }
252b5132 5992
9306ca4a 5993 if (!i.suffix)
29b0f896 5994 {
9306ca4a
JB		 5995 if (!intel_syntax)
5996 {
40fb9820 5997 if (i.tm.opcode_modifier.w)
9306ca4a 5998 {
4eed87de
AM		 5999 as_bad (_("no instruction mnemonic suffix given and "
6000 "no register operands; can't size instruction"));
9306ca4a
JB		 6001 return 0;
6002 }
6003 }
6004 else
6005 {
40fb9820 6006 unsigned int suffixes;
7ab9ffdd 6007
40fb9820
L		 6008 suffixes = !i.tm.opcode_modifier.no_bsuf;
6009 if (!i.tm.opcode_modifier.no_wsuf)
6010 suffixes |= 1 << 1;
6011 if (!i.tm.opcode_modifier.no_lsuf)
6012 suffixes |= 1 << 2;
fc4adea1 6013 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 6014 suffixes |= 1 << 3;
6015 if (!i.tm.opcode_modifier.no_ssuf)
6016 suffixes |= 1 << 4;
c2b9da16 6017 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
40fb9820
L		 6018 suffixes |= 1 << 5;
6019
6020 /* There are more than suffix matches. */
6021 if (i.tm.opcode_modifier.w
9306ca4a 6022 || ((suffixes & (suffixes - 1))
40fb9820
L		 6023 && !i.tm.opcode_modifier.defaultsize
6024 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 6025 {
6026 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
6027 return 0;
6028 }
6029 }
29b0f896 6030 }
252b5132 6031
d2224064
JB		 6032 /* Change the opcode based on the operand size given by i.suffix. */
6033 switch (i.suffix)
29b0f896 6034 {
d2224064
JB		 6035 /* Size floating point instruction. */
6036 case LONG_MNEM_SUFFIX:
6037 if (i.tm.opcode_modifier.floatmf)
6038 {
6039 i.tm.base_opcode ^= 4;
6040 break;
6041 }
6042 /* fall through */
6043 case WORD_MNEM_SUFFIX:
6044 case QWORD_MNEM_SUFFIX:
29b0f896 6045 /* It's not a byte, select word/dword operation. */
40fb9820 6046 if (i.tm.opcode_modifier.w)
29b0f896 6047 {
40fb9820 6048 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 6049 i.tm.base_opcode |= 8;
6050 else
6051 i.tm.base_opcode |= 1;
6052 }
d2224064
JB		 6053 /* fall through */
6054 case SHORT_MNEM_SUFFIX:
29b0f896
AM		 6055 /* Now select between word & dword operations via the operand
6056 size prefix, except for instructions that will ignore this
6057 prefix anyway. */
75c0a438
L		 6058 if (i.reg_operands > 0
6059 && i.types[0].bitfield.reg
6060 && i.tm.opcode_modifier.addrprefixopreg
6061 && (i.tm.opcode_modifier.immext
6062 || i.operands == 1))
cb712a9e 6063 {
ca61edf2
L		 6064 /* The address size override prefix changes the size of the
6065 first operand. */
40fb9820 6066 if ((flag_code == CODE_32BIT
75c0a438 6067 && i.op[0].regs->reg_type.bitfield.word)
40fb9820 6068 || (flag_code != CODE_32BIT
75c0a438 6069 && i.op[0].regs->reg_type.bitfield.dword))
cb712a9e
L		 6070 if (!add_prefix (ADDR_PREFIX_OPCODE))
6071 return 0;
6072 }
6073 else if (i.suffix != QWORD_MNEM_SUFFIX
40fb9820
L		 6074 && !i.tm.opcode_modifier.ignoresize
6075 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 6076 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
6077 || (flag_code == CODE_64BIT
40fb9820 6078 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 6079 {
6080 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 6081
40fb9820 6082 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 6083 prefix = ADDR_PREFIX_OPCODE;
252b5132 6084
29b0f896
AM		 6085 if (!add_prefix (prefix))
6086 return 0;
24eab124 6087 }
252b5132 6088
29b0f896
AM		 6089 /* Set mode64 for an operand. */
6090 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 6091 && flag_code == CODE_64BIT
d2224064 6092 && !i.tm.opcode_modifier.norex64
46e883c5 6093 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d2224064
JB		 6094 need rex64. */
6095 && ! (i.operands == 2
6096 && i.tm.base_opcode == 0x90
6097 && i.tm.extension_opcode == None
6098 && operand_type_equal (&i.types [0], &acc64)
6099 && operand_type_equal (&i.types [1], &acc64)))
6100 i.rex |= REX_W;
3e73aa7c 6101
d2224064 6102 break;
29b0f896 6103 }
7ecd2f8b 6104
c0a30a9f
L		 6105 if (i.reg_operands != 0
6106 && i.operands > 1
6107 && i.tm.opcode_modifier.addrprefixopreg
6108 && !i.tm.opcode_modifier.immext)
6109 {
6110 /* Check invalid register operand when the address size override
6111 prefix changes the size of register operands. */
6112 unsigned int op;
6113 enum { need_word, need_dword, need_qword } need;
6114
6115 if (flag_code == CODE_32BIT)
6116 need = i.prefix[ADDR_PREFIX] ? need_word : need_dword;
6117 else
6118 {
6119 if (i.prefix[ADDR_PREFIX])
6120 need = need_dword;
6121 else
6122 need = flag_code == CODE_64BIT ? need_qword : need_word;
6123 }
6124
6125 for (op = 0; op < i.operands; op++)
6126 if (i.types[op].bitfield.reg
6127 && ((need == need_word
6128 && !i.op[op].regs->reg_type.bitfield.word)
6129 || (need == need_dword
6130 && !i.op[op].regs->reg_type.bitfield.dword)
6131 || (need == need_qword
6132 && !i.op[op].regs->reg_type.bitfield.qword)))
6133 {
6134 as_bad (_("invalid register operand size for `%s'"),
6135 i.tm.name);
6136 return 0;
6137 }
6138 }
6139
29b0f896
AM		 6140 return 1;
6141}
3e73aa7c 6142
29b0f896 6143static int
543613e9 6144check_byte_reg (void)
29b0f896
AM		 6145{
6146 int op;
543613e9 6147
29b0f896
AM		 6148 for (op = i.operands; --op >= 0;)
6149 {
dc821c5f
JB		 6150 /* Skip non-register operands. */
6151 if (!i.types[op].bitfield.reg)
6152 continue;
6153
29b0f896
AM		 6154 /* If this is an eight bit register, it's OK. If it's the 16 or
6155 32 bit version of an eight bit register, we will just use the
6156 low portion, and that's OK too. */
dc821c5f 6157 if (i.types[op].bitfield.byte)
29b0f896
AM		 6158 continue;
6159
5a819eb9
JB		 6160 /* I/O port address operands are OK too. */
6161 if (i.tm.operand_types[op].bitfield.inoutportreg)
6162 continue;
6163
9344ff29
L		 6164 /* crc32 doesn't generate this warning. */
6165 if (i.tm.base_opcode == 0xf20f38f0)
6166 continue;
6167
dc821c5f
JB		 6168 if ((i.types[op].bitfield.word
6169 || i.types[op].bitfield.dword
6170 || i.types[op].bitfield.qword)
5a819eb9
JB		 6171 && i.op[op].regs->reg_num < 4
6172 /* Prohibit these changes in 64bit mode, since the lowering
6173 would be more complicated. */
6174 && flag_code != CODE_64BIT)
29b0f896 6175 {
29b0f896 6176#if REGISTER_WARNINGS
5a819eb9 6177 if (!quiet_warnings)
a540244d
L		 6178 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6179 register_prefix,
dc821c5f 6180 (i.op[op].regs + (i.types[op].bitfield.word
29b0f896
AM		 6181 ? REGNAM_AL - REGNAM_AX
6182 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 6183 register_prefix,
29b0f896
AM		 6184 i.op[op].regs->reg_name,
6185 i.suffix);
6186#endif
6187 continue;
6188 }
6189 /* Any other register is bad. */
dc821c5f 6190 if (i.types[op].bitfield.reg
40fb9820 6191 || i.types[op].bitfield.regmmx
1b54b8d7 6192 || i.types[op].bitfield.regsimd
40fb9820
L		 6193 || i.types[op].bitfield.sreg2
6194 || i.types[op].bitfield.sreg3
6195 || i.types[op].bitfield.control
6196 || i.types[op].bitfield.debug
ca0d63fe 6197 || i.types[op].bitfield.test)
29b0f896 6198 {
a540244d
L		 6199 as_bad (_("`%s%s' not allowed with `%s%c'"),
6200 register_prefix,
29b0f896
AM		 6201 i.op[op].regs->reg_name,
6202 i.tm.name,
6203 i.suffix);
6204 return 0;
6205 }
6206 }
6207 return 1;
6208}
6209
6210static int
e3bb37b5 6211check_long_reg (void)
29b0f896
AM		 6212{
6213 int op;
6214
6215 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 6216 /* Skip non-register operands. */
6217 if (!i.types[op].bitfield.reg)
6218 continue;
29b0f896
AM		 6219 /* Reject eight bit registers, except where the template requires
6220 them. (eg. movzb) */
dc821c5f
JB		 6221 else if (i.types[op].bitfield.byte
6222 && (i.tm.operand_types[op].bitfield.reg
6223 || i.tm.operand_types[op].bitfield.acc)
6224 && (i.tm.operand_types[op].bitfield.word
6225 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6226 {
a540244d
L		 6227 as_bad (_("`%s%s' not allowed with `%s%c'"),
6228 register_prefix,
29b0f896
AM		 6229 i.op[op].regs->reg_name,
6230 i.tm.name,
6231 i.suffix);
6232 return 0;
6233 }
e4630f71 6234 /* Warn if the e prefix on a general reg is missing. */
29b0f896 6235 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 6236 && i.types[op].bitfield.word
6237 && (i.tm.operand_types[op].bitfield.reg
6238 || i.tm.operand_types[op].bitfield.acc)
6239 && i.tm.operand_types[op].bitfield.dword)
29b0f896
AM		 6240 {
6241 /* Prohibit these changes in the 64bit mode, since the
6242 lowering is more complicated. */
6243 if (flag_code == CODE_64BIT)
252b5132 6244 {
2b5d6a91 6245 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 6246 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 6247 i.suffix);
6248 return 0;
252b5132 6249 }
29b0f896 6250#if REGISTER_WARNINGS
cecf1424
JB		 6251 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6252 register_prefix,
6253 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6254 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 6255#endif
252b5132 6256 }
e4630f71 6257 /* Warn if the r prefix on a general reg is present. */
dc821c5f
JB		 6258 else if (i.types[op].bitfield.qword
6259 && (i.tm.operand_types[op].bitfield.reg
6260 || i.tm.operand_types[op].bitfield.acc)
6261 && i.tm.operand_types[op].bitfield.dword)
252b5132 6262 {
34828aad 6263 if (intel_syntax
ca61edf2 6264 && i.tm.opcode_modifier.toqword
1b54b8d7 6265 && !i.types[0].bitfield.regsimd)
34828aad 6266 {
ca61edf2 6267 /* Convert to QWORD. We want REX byte. */
34828aad
L		 6268 i.suffix = QWORD_MNEM_SUFFIX;
6269 }
6270 else
6271 {
2b5d6a91 6272 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 6273 register_prefix, i.op[op].regs->reg_name,
6274 i.suffix);
6275 return 0;
6276 }
29b0f896
AM		 6277 }
6278 return 1;
6279}
252b5132 6280
29b0f896 6281static int
e3bb37b5 6282check_qword_reg (void)
29b0f896
AM		 6283{
6284 int op;
252b5132 6285
29b0f896 6286 for (op = i.operands; --op >= 0; )
dc821c5f
JB		 6287 /* Skip non-register operands. */
6288 if (!i.types[op].bitfield.reg)
6289 continue;
29b0f896
AM		 6290 /* Reject eight bit registers, except where the template requires
6291 them. (eg. movzb) */
dc821c5f
JB		 6292 else if (i.types[op].bitfield.byte
6293 && (i.tm.operand_types[op].bitfield.reg
6294 || i.tm.operand_types[op].bitfield.acc)
6295 && (i.tm.operand_types[op].bitfield.word
6296 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6297 {
a540244d
L		 6298 as_bad (_("`%s%s' not allowed with `%s%c'"),
6299 register_prefix,
29b0f896
AM		 6300 i.op[op].regs->reg_name,
6301 i.tm.name,
6302 i.suffix);
6303 return 0;
6304 }
e4630f71 6305 /* Warn if the r prefix on a general reg is missing. */
dc821c5f
JB		 6306 else if ((i.types[op].bitfield.word
6307 || i.types[op].bitfield.dword)
6308 && (i.tm.operand_types[op].bitfield.reg
6309 || i.tm.operand_types[op].bitfield.acc)
6310 && i.tm.operand_types[op].bitfield.qword)
29b0f896
AM		 6311 {
6312 /* Prohibit these changes in the 64bit mode, since the
6313 lowering is more complicated. */
34828aad 6314 if (intel_syntax
ca61edf2 6315 && i.tm.opcode_modifier.todword
1b54b8d7 6316 && !i.types[0].bitfield.regsimd)
34828aad 6317 {
ca61edf2 6318 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 6319 i.suffix = LONG_MNEM_SUFFIX;
6320 }
6321 else
6322 {
2b5d6a91 6323 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 6324 register_prefix, i.op[op].regs->reg_name,
6325 i.suffix);
6326 return 0;
6327 }
252b5132 6328 }
29b0f896
AM		 6329 return 1;
6330}
252b5132 6331
29b0f896 6332static int
e3bb37b5 6333check_word_reg (void)
29b0f896
AM		 6334{
6335 int op;
6336 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 6337 /* Skip non-register operands. */
6338 if (!i.types[op].bitfield.reg)
6339 continue;
29b0f896
AM		 6340 /* Reject eight bit registers, except where the template requires
6341 them. (eg. movzb) */
dc821c5f
JB		 6342 else if (i.types[op].bitfield.byte
6343 && (i.tm.operand_types[op].bitfield.reg
6344 || i.tm.operand_types[op].bitfield.acc)
6345 && (i.tm.operand_types[op].bitfield.word
6346 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6347 {
a540244d
L		 6348 as_bad (_("`%s%s' not allowed with `%s%c'"),
6349 register_prefix,
29b0f896
AM		 6350 i.op[op].regs->reg_name,
6351 i.tm.name,
6352 i.suffix);
6353 return 0;
6354 }
e4630f71 6355 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 6356 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 6357 && (i.types[op].bitfield.dword
6358 || i.types[op].bitfield.qword)
6359 && (i.tm.operand_types[op].bitfield.reg
6360 || i.tm.operand_types[op].bitfield.acc)
6361 && i.tm.operand_types[op].bitfield.word)
252b5132 6362 {
29b0f896
AM		 6363 /* Prohibit these changes in the 64bit mode, since the
6364 lowering is more complicated. */
6365 if (flag_code == CODE_64BIT)
252b5132 6366 {
2b5d6a91 6367 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 6368 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 6369 i.suffix);
6370 return 0;
252b5132 6371 }
29b0f896 6372#if REGISTER_WARNINGS
cecf1424
JB		 6373 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6374 register_prefix,
6375 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6376 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 6377#endif
6378 }
6379 return 1;
6380}
252b5132 6381
29b0f896 6382static int
40fb9820 6383update_imm (unsigned int j)
29b0f896 6384{
bc0844ae 6385 i386_operand_type overlap = i.types[j];
40fb9820
L		 6386 if ((overlap.bitfield.imm8
6387 || overlap.bitfield.imm8s
6388 || overlap.bitfield.imm16
6389 || overlap.bitfield.imm32
6390 || overlap.bitfield.imm32s
6391 || overlap.bitfield.imm64)
0dfbf9d7
L		 6392 && !operand_type_equal (&overlap, &imm8)
6393 && !operand_type_equal (&overlap, &imm8s)
6394 && !operand_type_equal (&overlap, &imm16)
6395 && !operand_type_equal (&overlap, &imm32)
6396 && !operand_type_equal (&overlap, &imm32s)
6397 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 6398 {
6399 if (i.suffix)
6400 {
40fb9820
L		 6401 i386_operand_type temp;
6402
0dfbf9d7 6403 operand_type_set (&temp, 0);
7ab9ffdd 6404 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 6405 {
6406 temp.bitfield.imm8 = overlap.bitfield.imm8;
6407 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6408 }
6409 else if (i.suffix == WORD_MNEM_SUFFIX)
6410 temp.bitfield.imm16 = overlap.bitfield.imm16;
6411 else if (i.suffix == QWORD_MNEM_SUFFIX)
6412 {
6413 temp.bitfield.imm64 = overlap.bitfield.imm64;
6414 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6415 }
6416 else
6417 temp.bitfield.imm32 = overlap.bitfield.imm32;
6418 overlap = temp;
29b0f896 6419 }
0dfbf9d7
L		 6420 else if (operand_type_equal (&overlap, &imm16_32_32s)
6421 || operand_type_equal (&overlap, &imm16_32)
6422 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 6423 {
40fb9820 6424 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 6425 overlap = imm16;
40fb9820 6426 else
65da13b5 6427 overlap = imm32s;
29b0f896 6428 }
0dfbf9d7
L		 6429 if (!operand_type_equal (&overlap, &imm8)
6430 && !operand_type_equal (&overlap, &imm8s)
6431 && !operand_type_equal (&overlap, &imm16)
6432 && !operand_type_equal (&overlap, &imm32)
6433 && !operand_type_equal (&overlap, &imm32s)
6434 && !operand_type_equal (&overlap, &imm64))
29b0f896 6435 {
4eed87de
AM		 6436 as_bad (_("no instruction mnemonic suffix given; "
6437 "can't determine immediate size"));
29b0f896
AM		 6438 return 0;
6439 }
6440 }
40fb9820 6441 i.types[j] = overlap;
29b0f896 6442
40fb9820
L		 6443 return 1;
6444}
6445
6446static int
6447finalize_imm (void)
6448{
bc0844ae 6449 unsigned int j, n;
29b0f896 6450
bc0844ae
L		 6451 /* Update the first 2 immediate operands. */
6452 n = i.operands > 2 ? 2 : i.operands;
6453 if (n)
6454 {
6455 for (j = 0; j < n; j++)
6456 if (update_imm (j) == 0)
6457 return 0;
40fb9820 6458
bc0844ae
L		 6459 /* The 3rd operand can't be immediate operand. */
6460 gas_assert (operand_type_check (i.types[2], imm) == 0);
6461 }
29b0f896
AM		 6462
6463 return 1;
6464}
6465
6466static int
e3bb37b5 6467process_operands (void)
29b0f896
AM		 6468{
6469 /* Default segment register this instruction will use for memory
6470 accesses. 0 means unknown. This is only for optimizing out
6471 unnecessary segment overrides. */
6472 const seg_entry *default_seg = 0;
6473
2426c15f 6474 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 6475 {
91d6fa6a
NC		 6476 unsigned int dupl = i.operands;
6477 unsigned int dest = dupl - 1;
9fcfb3d7
L		 6478 unsigned int j;
6479
c0f3af97 6480 /* The destination must be an xmm register. */
9c2799c2 6481 gas_assert (i.reg_operands
91d6fa6a 6482 && MAX_OPERANDS > dupl
7ab9ffdd 6483 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97 6484
1b54b8d7
JB		 6485 if (i.tm.operand_types[0].bitfield.acc
6486 && i.tm.operand_types[0].bitfield.xmmword)
e2ec9d29 6487 {
8cd7925b 6488 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 6489 {
6490 /* Keep xmm0 for instructions with VEX prefix and 3
6491 sources. */
1b54b8d7
JB		 6492 i.tm.operand_types[0].bitfield.acc = 0;
6493 i.tm.operand_types[0].bitfield.regsimd = 1;
c0f3af97
L		 6494 goto duplicate;
6495 }
e2ec9d29 6496 else
c0f3af97
L		 6497 {
6498 /* We remove the first xmm0 and keep the number of
6499 operands unchanged, which in fact duplicates the
6500 destination. */
6501 for (j = 1; j < i.operands; j++)
6502 {
6503 i.op[j - 1] = i.op[j];
6504 i.types[j - 1] = i.types[j];
6505 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6506 }
6507 }
6508 }
6509 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 6510 {
91d6fa6a 6511 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 6512 && (i.tm.opcode_modifier.vexsources
6513 == VEX3SOURCES));
c0f3af97
L		 6514
6515 /* Add the implicit xmm0 for instructions with VEX prefix
6516 and 3 sources. */
6517 for (j = i.operands; j > 0; j--)
6518 {
6519 i.op[j] = i.op[j - 1];
6520 i.types[j] = i.types[j - 1];
6521 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6522 }
6523 i.op[0].regs
6524 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 6525 i.types[0] = regxmm;
c0f3af97
L		 6526 i.tm.operand_types[0] = regxmm;
6527
6528 i.operands += 2;
6529 i.reg_operands += 2;
6530 i.tm.operands += 2;
6531
91d6fa6a 6532 dupl++;
c0f3af97 6533 dest++;
91d6fa6a
NC		 6534 i.op[dupl] = i.op[dest];
6535 i.types[dupl] = i.types[dest];
6536 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 6537 }
c0f3af97
L		 6538 else
6539 {
6540duplicate:
6541 i.operands++;
6542 i.reg_operands++;
6543 i.tm.operands++;
6544
91d6fa6a
NC		 6545 i.op[dupl] = i.op[dest];
6546 i.types[dupl] = i.types[dest];
6547 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 6548 }
6549
6550 if (i.tm.opcode_modifier.immext)
6551 process_immext ();
6552 }
1b54b8d7
JB		 6553 else if (i.tm.operand_types[0].bitfield.acc
6554 && i.tm.operand_types[0].bitfield.xmmword)
c0f3af97
L		 6555 {
6556 unsigned int j;
6557
9fcfb3d7
L		 6558 for (j = 1; j < i.operands; j++)
6559 {
6560 i.op[j - 1] = i.op[j];
6561 i.types[j - 1] = i.types[j];
6562
6563 /* We need to adjust fields in i.tm since they are used by
6564 build_modrm_byte. */
6565 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6566 }
6567
e2ec9d29
L		 6568 i.operands--;
6569 i.reg_operands--;
e2ec9d29
L		 6570 i.tm.operands--;
6571 }
920d2ddc
IT		 6572 else if (i.tm.opcode_modifier.implicitquadgroup)
6573 {
a477a8c4
JB		 6574 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6575
920d2ddc 6576 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
10c17abd 6577 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
a477a8c4
JB		 6578 regnum = register_number (i.op[1].regs);
6579 first_reg_in_group = regnum & ~3;
6580 last_reg_in_group = first_reg_in_group + 3;
6581 if (regnum != first_reg_in_group)
6582 as_warn (_("source register `%s%s' implicitly denotes"
6583 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6584 register_prefix, i.op[1].regs->reg_name,
6585 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6586 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6587 i.tm.name);
6588 }
e2ec9d29
L		 6589 else if (i.tm.opcode_modifier.regkludge)
6590 {
6591 /* The imul $imm, %reg instruction is converted into
6592 imul $imm, %reg, %reg, and the clr %reg instruction
6593 is converted into xor %reg, %reg. */
6594
6595 unsigned int first_reg_op;
6596
6597 if (operand_type_check (i.types[0], reg))
6598 first_reg_op = 0;
6599 else
6600 first_reg_op = 1;
6601 /* Pretend we saw the extra register operand. */
9c2799c2 6602 gas_assert (i.reg_operands == 1
7ab9ffdd 6603 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 6604 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6605 i.types[first_reg_op + 1] = i.types[first_reg_op];
6606 i.operands++;
6607 i.reg_operands++;
29b0f896
AM		 6608 }
6609
40fb9820 6610 if (i.tm.opcode_modifier.shortform)
29b0f896 6611 {
40fb9820
L		 6612 if (i.types[0].bitfield.sreg2
6613 || i.types[0].bitfield.sreg3)
29b0f896 6614 {
4eed87de
AM		 6615 if (i.tm.base_opcode == POP_SEG_SHORT
6616 && i.op[0].regs->reg_num == 1)
29b0f896 6617 {
a87af027 6618 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 6619 return 0;
29b0f896 6620 }
4eed87de
AM		 6621 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6622 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 6623 i.rex |= REX_B;
4eed87de
AM		 6624 }
6625 else
6626 {
7ab9ffdd 6627 /* The register or float register operand is in operand
85f10a01 6628 0 or 1. */
40fb9820 6629 unsigned int op;
7ab9ffdd 6630
ca0d63fe 6631 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
7ab9ffdd
L		 6632 || operand_type_check (i.types[0], reg))
6633 op = 0;
6634 else
6635 op = 1;
4eed87de
AM		 6636 /* Register goes in low 3 bits of opcode. */
6637 i.tm.base_opcode |= i.op[op].regs->reg_num;
6638 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 6639 i.rex |= REX_B;
40fb9820 6640 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 6641 {
4eed87de
AM		 6642 /* Warn about some common errors, but press on regardless.
6643 The first case can be generated by gcc (<= 2.8.1). */
6644 if (i.operands == 2)
6645 {
6646 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 6647 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 6648 register_prefix, i.op[!intel_syntax].regs->reg_name,
6649 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 6650 }
6651 else
6652 {
6653 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 6654 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6655 register_prefix, i.op[0].regs->reg_name);
4eed87de 6656 }
29b0f896
AM		 6657 }
6658 }
6659 }
40fb9820 6660 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 6661 {
6662 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 6663 must be put into the modrm byte). Now, we make the modrm and
6664 index base bytes based on all the info we've collected. */
29b0f896
AM		 6665
6666 default_seg = build_modrm_byte ();
6667 }
8a2ed489 6668 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 6669 {
6670 default_seg = &ds;
6671 }
40fb9820 6672 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 6673 {
6674 /* For the string instructions that allow a segment override
6675 on one of their operands, the default segment is ds. */
6676 default_seg = &ds;
6677 }
6678
75178d9d
L		 6679 if (i.tm.base_opcode == 0x8d /* lea */
6680 && i.seg[0]
6681 && !quiet_warnings)
30123838 6682 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 6683
6684 /* If a segment was explicitly specified, and the specified segment
6685 is not the default, use an opcode prefix to select it. If we
6686 never figured out what the default segment is, then default_seg
6687 will be zero at this point, and the specified segment prefix will
6688 always be used. */
29b0f896
AM		 6689 if ((i.seg[0]) && (i.seg[0] != default_seg))
6690 {
6691 if (!add_prefix (i.seg[0]->seg_prefix))
6692 return 0;
6693 }
6694 return 1;
6695}
6696
6697static const seg_entry *
e3bb37b5 6698build_modrm_byte (void)
29b0f896
AM		 6699{
6700 const seg_entry *default_seg = 0;
c0f3af97 6701 unsigned int source, dest;
8cd7925b 6702 int vex_3_sources;
c0f3af97 6703
8cd7925b 6704 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6705 if (vex_3_sources)
6706 {
91d6fa6a 6707 unsigned int nds, reg_slot;
4c2c6516 6708 expressionS *exp;
c0f3af97 6709
6b8d3588 6710 dest = i.operands - 1;
c0f3af97 6711 nds = dest - 1;
922d8de8 6712
a683cc34 6713 /* There are 2 kinds of instructions:
bed3d976
JB		 6714 1. 5 operands: 4 register operands or 3 register operands
6715 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6716 VexW0 or VexW1. The destination must be either XMM, YMM or
43234a1e 6717 ZMM register.
bed3d976 6718 2. 4 operands: 4 register operands or 3 register operands
2f1bada2 6719 plus 1 memory operand, with VexXDS. */
922d8de8 6720 gas_assert ((i.reg_operands == 4
bed3d976
JB		 6721 || (i.reg_operands == 3 && i.mem_operands == 1))
6722 && i.tm.opcode_modifier.vexvvvv == VEXXDS
dcd7e323
JB		 6723 && i.tm.opcode_modifier.vexw
6724 && i.tm.operand_types[dest].bitfield.regsimd);
a683cc34 6725
48db9223
JB		 6726 /* If VexW1 is set, the first non-immediate operand is the source and
6727 the second non-immediate one is encoded in the immediate operand. */
6728 if (i.tm.opcode_modifier.vexw == VEXW1)
6729 {
6730 source = i.imm_operands;
6731 reg_slot = i.imm_operands + 1;
6732 }
6733 else
6734 {
6735 source = i.imm_operands + 1;
6736 reg_slot = i.imm_operands;
6737 }
6738
a683cc34 6739 if (i.imm_operands == 0)
bed3d976
JB		 6740 {
6741 /* When there is no immediate operand, generate an 8bit
6742 immediate operand to encode the first operand. */
6743 exp = &im_expressions[i.imm_operands++];
6744 i.op[i.operands].imms = exp;
6745 i.types[i.operands] = imm8;
6746 i.operands++;
6747
6748 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6749 exp->X_op = O_constant;
6750 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6751 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6752 }
922d8de8 6753 else
bed3d976
JB		 6754 {
6755 unsigned int imm_slot;
a683cc34 6756
2f1bada2
JB		 6757 gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4);
6758
bed3d976
JB		 6759 if (i.tm.opcode_modifier.immext)
6760 {
6761 /* When ImmExt is set, the immediate byte is the last
6762 operand. */
6763 imm_slot = i.operands - 1;
6764 source--;
6765 reg_slot--;
6766 }
6767 else
6768 {
6769 imm_slot = 0;
6770
6771 /* Turn on Imm8 so that output_imm will generate it. */
6772 i.types[imm_slot].bitfield.imm8 = 1;
6773 }
6774
6775 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6776 i.op[imm_slot].imms->X_add_number
6777 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6778 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
bed3d976 6779 }
a683cc34 6780
10c17abd 6781 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
dae39acc 6782 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6783 }
6784 else
6785 source = dest = 0;
29b0f896
AM		 6786
6787 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6788 implicit registers do not count. If there are 3 register
6789 operands, it must be a instruction with VexNDS. For a
6790 instruction with VexNDD, the destination register is encoded
6791 in VEX prefix. If there are 4 register operands, it must be
6792 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6793 if (i.mem_operands == 0
6794 && ((i.reg_operands == 2
2426c15f 6795 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6796 || (i.reg_operands == 3
2426c15f 6797 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6798 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6799 {
cab737b9
L		 6800 switch (i.operands)
6801 {
6802 case 2:
6803 source = 0;
6804 break;
6805 case 3:
c81128dc
L		 6806 /* When there are 3 operands, one of them may be immediate,
6807 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6808 the first operand must be shift count register (cl) or it
6809 is an instruction with VexNDS. */
9c2799c2 6810 gas_assert (i.imm_operands == 1
7ab9ffdd 6811 || (i.imm_operands == 0
2426c15f 6812 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6813 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6814 if (operand_type_check (i.types[0], imm)
6815 || i.types[0].bitfield.shiftcount)
6816 source = 1;
6817 else
6818 source = 0;
cab737b9
L		 6819 break;
6820 case 4:
368d64cc
L		 6821 /* When there are 4 operands, the first two must be 8bit
6822 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6823 one.
6824
6825 For instructions with VexNDS, if the first operand
6826 an imm8, the source operand is the 2nd one. If the last
6827 operand is imm8, the source operand is the first one. */
9c2799c2 6828 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6829 && i.types[0].bitfield.imm8
6830 && i.types[1].bitfield.imm8)
2426c15f 6831 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6832 && i.imm_operands == 1
6833 && (i.types[0].bitfield.imm8
43234a1e
L		 6834 || i.types[i.operands - 1].bitfield.imm8
6835 || i.rounding)));
9f2670f2
L		 6836 if (i.imm_operands == 2)
6837 source = 2;
6838 else
c0f3af97
L		 6839 {
6840 if (i.types[0].bitfield.imm8)
6841 source = 1;
6842 else
6843 source = 0;
6844 }
c0f3af97
L		 6845 break;
6846 case 5:
e771e7c9 6847 if (is_evex_encoding (&i.tm))
43234a1e
L		 6848 {
6849 /* For EVEX instructions, when there are 5 operands, the
6850 first one must be immediate operand. If the second one
6851 is immediate operand, the source operand is the 3th
6852 one. If the last one is immediate operand, the source
6853 operand is the 2nd one. */
6854 gas_assert (i.imm_operands == 2
6855 && i.tm.opcode_modifier.sae
6856 && operand_type_check (i.types[0], imm));
6857 if (operand_type_check (i.types[1], imm))
6858 source = 2;
6859 else if (operand_type_check (i.types[4], imm))
6860 source = 1;
6861 else
6862 abort ();
6863 }
cab737b9
L		 6864 break;
6865 default:
6866 abort ();
6867 }
6868
c0f3af97
L		 6869 if (!vex_3_sources)
6870 {
6871 dest = source + 1;
6872
43234a1e
L		 6873 /* RC/SAE operand could be between DEST and SRC. That happens
6874 when one operand is GPR and the other one is XMM/YMM/ZMM
6875 register. */
6876 if (i.rounding && i.rounding->operand == (int) dest)
6877 dest++;
6878
2426c15f 6879 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6880 {
43234a1e 6881 /* For instructions with VexNDS, the register-only source
c5d0745b 6882 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
43234a1e
L		 6883 register. It is encoded in VEX prefix. We need to
6884 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6885
6886 i386_operand_type op;
6887 unsigned int vvvv;
6888
6889 /* Check register-only source operand when two source
6890 operands are swapped. */
6891 if (!i.tm.operand_types[source].bitfield.baseindex
6892 && i.tm.operand_types[dest].bitfield.baseindex)
6893 {
6894 vvvv = source;
6895 source = dest;
6896 }
6897 else
6898 vvvv = dest;
6899
6900 op = i.tm.operand_types[vvvv];
fa99fab2 6901 op.bitfield.regmem = 0;
c0f3af97 6902 if ((dest + 1) >= i.operands
dc821c5f
JB		 6903 || ((!op.bitfield.reg
6904 || (!op.bitfield.dword && !op.bitfield.qword))
10c17abd 6905 && !op.bitfield.regsimd
43234a1e 6906 && !operand_type_equal (&op, &regmask)))
c0f3af97 6907 abort ();
f12dc422 6908 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6909 dest++;
6910 }
6911 }
29b0f896
AM		 6912
6913 i.rm.mode = 3;
6914 /* One of the register operands will be encoded in the i.tm.reg
6915 field, the other in the combined i.tm.mode and i.tm.regmem
6916 fields. If no form of this instruction supports a memory
6917 destination operand, then we assume the source operand may
6918 sometimes be a memory operand and so we need to store the
6919 destination in the i.rm.reg field. */
40fb9820
L		 6920 if (!i.tm.operand_types[dest].bitfield.regmem
6921 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6922 {
6923 i.rm.reg = i.op[dest].regs->reg_num;
6924 i.rm.regmem = i.op[source].regs->reg_num;
6925 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6926 i.rex |= REX_R;
43234a1e
L		 6927 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6928 i.vrex |= REX_R;
29b0f896 6929 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6930 i.rex |= REX_B;
43234a1e
L		 6931 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6932 i.vrex |= REX_B;
29b0f896
AM		 6933 }
6934 else
6935 {
6936 i.rm.reg = i.op[source].regs->reg_num;
6937 i.rm.regmem = i.op[dest].regs->reg_num;
6938 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6939 i.rex |= REX_B;
43234a1e
L		 6940 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6941 i.vrex |= REX_B;
29b0f896 6942 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6943 i.rex |= REX_R;
43234a1e
L		 6944 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6945 i.vrex |= REX_R;
29b0f896 6946 }
e0c7f900 6947 if (flag_code != CODE_64BIT && (i.rex & REX_R))
c4a530c5 6948 {
e0c7f900 6949 if (!i.types[i.tm.operand_types[0].bitfield.regmem].bitfield.control)
c4a530c5 6950 abort ();
e0c7f900 6951 i.rex &= ~REX_R;
c4a530c5
JB		 6952 add_prefix (LOCK_PREFIX_OPCODE);
6953 }
29b0f896
AM		 6954 }
6955 else
6956 { /* If it's not 2 reg operands... */
c0f3af97
L		 6957 unsigned int mem;
6958
29b0f896
AM		 6959 if (i.mem_operands)
6960 {
6961 unsigned int fake_zero_displacement = 0;
99018f42 6962 unsigned int op;
4eed87de 6963
7ab9ffdd
L		 6964 for (op = 0; op < i.operands; op++)
6965 if (operand_type_check (i.types[op], anymem))
6966 break;
7ab9ffdd 6967 gas_assert (op < i.operands);
29b0f896 6968
6c30d220
L		 6969 if (i.tm.opcode_modifier.vecsib)
6970 {
6971 if (i.index_reg->reg_num == RegEiz
6972 || i.index_reg->reg_num == RegRiz)
6973 abort ();
6974
6975 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6976 if (!i.base_reg)
6977 {
6978 i.sib.base = NO_BASE_REGISTER;
6979 i.sib.scale = i.log2_scale_factor;
6980 i.types[op].bitfield.disp8 = 0;
6981 i.types[op].bitfield.disp16 = 0;
6982 i.types[op].bitfield.disp64 = 0;
43083a50 6983 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6c30d220
L		 6984 {
6985 /* Must be 32 bit */
6986 i.types[op].bitfield.disp32 = 1;
6987 i.types[op].bitfield.disp32s = 0;
6988 }
6989 else
6990 {
6991 i.types[op].bitfield.disp32 = 0;
6992 i.types[op].bitfield.disp32s = 1;
6993 }
6994 }
6995 i.sib.index = i.index_reg->reg_num;
6996 if ((i.index_reg->reg_flags & RegRex) != 0)
6997 i.rex |= REX_X;
43234a1e
L		 6998 if ((i.index_reg->reg_flags & RegVRex) != 0)
6999 i.vrex |= REX_X;
6c30d220
L		 7000 }
7001
29b0f896
AM		 7002 default_seg = &ds;
7003
7004 if (i.base_reg == 0)
7005 {
7006 i.rm.mode = 0;
7007 if (!i.disp_operands)
9bb129e8 7008 fake_zero_displacement = 1;
29b0f896
AM		 7009 if (i.index_reg == 0)
7010 {
73053c1f
JB		 7011 i386_operand_type newdisp;
7012
6c30d220 7013 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 7014 /* Operand is just <disp> */
20f0a1fc 7015 if (flag_code == CODE_64BIT)
29b0f896
AM		 7016 {
7017 /* 64bit mode overwrites the 32bit absolute
7018 addressing by RIP relative addressing and
7019 absolute addressing is encoded by one of the
7020 redundant SIB forms. */
7021 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7022 i.sib.base = NO_BASE_REGISTER;
7023 i.sib.index = NO_INDEX_REGISTER;
73053c1f 7024 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
20f0a1fc 7025 }
fc225355
L		 7026 else if ((flag_code == CODE_16BIT)
7027 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 7028 {
7029 i.rm.regmem = NO_BASE_REGISTER_16;
73053c1f 7030 newdisp = disp16;
20f0a1fc
NC		 7031 }
7032 else
7033 {
7034 i.rm.regmem = NO_BASE_REGISTER;
73053c1f 7035 newdisp = disp32;
29b0f896 7036 }
73053c1f
JB		 7037 i.types[op] = operand_type_and_not (i.types[op], anydisp);
7038 i.types[op] = operand_type_or (i.types[op], newdisp);
29b0f896 7039 }
6c30d220 7040 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 7041 {
6c30d220 7042 /* !i.base_reg && i.index_reg */
db51cc60
L		 7043 if (i.index_reg->reg_num == RegEiz
7044 || i.index_reg->reg_num == RegRiz)
7045 i.sib.index = NO_INDEX_REGISTER;
7046 else
7047 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 7048 i.sib.base = NO_BASE_REGISTER;
7049 i.sib.scale = i.log2_scale_factor;
7050 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 7051 i.types[op].bitfield.disp8 = 0;
7052 i.types[op].bitfield.disp16 = 0;
7053 i.types[op].bitfield.disp64 = 0;
43083a50 7054 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
40fb9820
L		 7055 {
7056 /* Must be 32 bit */
7057 i.types[op].bitfield.disp32 = 1;
7058 i.types[op].bitfield.disp32s = 0;
7059 }
29b0f896 7060 else
40fb9820
L		 7061 {
7062 i.types[op].bitfield.disp32 = 0;
7063 i.types[op].bitfield.disp32s = 1;
7064 }
29b0f896 7065 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 7066 i.rex |= REX_X;
29b0f896
AM		 7067 }
7068 }
7069 /* RIP addressing for 64bit mode. */
9a04903e
JB		 7070 else if (i.base_reg->reg_num == RegRip ||
7071 i.base_reg->reg_num == RegEip)
29b0f896 7072 {
6c30d220 7073 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 7074 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 7075 i.types[op].bitfield.disp8 = 0;
7076 i.types[op].bitfield.disp16 = 0;
7077 i.types[op].bitfield.disp32 = 0;
7078 i.types[op].bitfield.disp32s = 1;
7079 i.types[op].bitfield.disp64 = 0;
71903a11 7080 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 7081 if (! i.disp_operands)
7082 fake_zero_displacement = 1;
29b0f896 7083 }
dc821c5f 7084 else if (i.base_reg->reg_type.bitfield.word)
29b0f896 7085 {
6c30d220 7086 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 7087 switch (i.base_reg->reg_num)
7088 {
7089 case 3: /* (%bx) */
7090 if (i.index_reg == 0)
7091 i.rm.regmem = 7;
7092 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7093 i.rm.regmem = i.index_reg->reg_num - 6;
7094 break;
7095 case 5: /* (%bp) */
7096 default_seg = &ss;
7097 if (i.index_reg == 0)
7098 {
7099 i.rm.regmem = 6;
40fb9820 7100 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 7101 {
7102 /* fake (%bp) into 0(%bp) */
b5014f7a 7103 i.types[op].bitfield.disp8 = 1;
252b5132 7104 fake_zero_displacement = 1;
29b0f896
AM		 7105 }
7106 }
7107 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7108 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
7109 break;
7110 default: /* (%si) -> 4 or (%di) -> 5 */
7111 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
7112 }
7113 i.rm.mode = mode_from_disp_size (i.types[op]);
7114 }
7115 else /* i.base_reg and 32/64 bit mode */
7116 {
7117 if (flag_code == CODE_64BIT
40fb9820
L		 7118 && operand_type_check (i.types[op], disp))
7119 {
73053c1f
JB		 7120 i.types[op].bitfield.disp16 = 0;
7121 i.types[op].bitfield.disp64 = 0;
40fb9820 7122 if (i.prefix[ADDR_PREFIX] == 0)
73053c1f
JB		 7123 {
7124 i.types[op].bitfield.disp32 = 0;
7125 i.types[op].bitfield.disp32s = 1;
7126 }
40fb9820 7127 else
73053c1f
JB		 7128 {
7129 i.types[op].bitfield.disp32 = 1;
7130 i.types[op].bitfield.disp32s = 0;
7131 }
40fb9820 7132 }
20f0a1fc 7133
6c30d220
L		 7134 if (!i.tm.opcode_modifier.vecsib)
7135 i.rm.regmem = i.base_reg->reg_num;
29b0f896 7136 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 7137 i.rex |= REX_B;
29b0f896
AM		 7138 i.sib.base = i.base_reg->reg_num;
7139 /* x86-64 ignores REX prefix bit here to avoid decoder
7140 complications. */
848930b2
JB		 7141 if (!(i.base_reg->reg_flags & RegRex)
7142 && (i.base_reg->reg_num == EBP_REG_NUM
7143 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 7144 default_seg = &ss;
848930b2 7145 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 7146 {
848930b2 7147 fake_zero_displacement = 1;
b5014f7a 7148 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 7149 }
7150 i.sib.scale = i.log2_scale_factor;
7151 if (i.index_reg == 0)
7152 {
6c30d220 7153 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 7154 /* <disp>(%esp) becomes two byte modrm with no index
7155 register. We've already stored the code for esp
7156 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7157 Any base register besides %esp will not use the
7158 extra modrm byte. */
7159 i.sib.index = NO_INDEX_REGISTER;
29b0f896 7160 }
6c30d220 7161 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 7162 {
db51cc60
L		 7163 if (i.index_reg->reg_num == RegEiz
7164 || i.index_reg->reg_num == RegRiz)
7165 i.sib.index = NO_INDEX_REGISTER;
7166 else
7167 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 7168 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7169 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 7170 i.rex |= REX_X;
29b0f896 7171 }
67a4f2b7
AO		 7172
7173 if (i.disp_operands
7174 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7175 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7176 i.rm.mode = 0;
7177 else
a501d77e
L		 7178 {
7179 if (!fake_zero_displacement
7180 && !i.disp_operands
7181 && i.disp_encoding)
7182 {
7183 fake_zero_displacement = 1;
7184 if (i.disp_encoding == disp_encoding_8bit)
7185 i.types[op].bitfield.disp8 = 1;
7186 else
7187 i.types[op].bitfield.disp32 = 1;
7188 }
7189 i.rm.mode = mode_from_disp_size (i.types[op]);
7190 }
29b0f896 7191 }
252b5132 7192
29b0f896
AM		 7193 if (fake_zero_displacement)
7194 {
7195 /* Fakes a zero displacement assuming that i.types[op]
7196 holds the correct displacement size. */
7197 expressionS *exp;
7198
9c2799c2 7199 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 7200 exp = &disp_expressions[i.disp_operands++];
7201 i.op[op].disps = exp;
7202 exp->X_op = O_constant;
7203 exp->X_add_number = 0;
7204 exp->X_add_symbol = (symbolS *) 0;
7205 exp->X_op_symbol = (symbolS *) 0;
7206 }
c0f3af97
L		 7207
7208 mem = op;
29b0f896 7209 }
c0f3af97
L		 7210 else
7211 mem = ~0;
252b5132 7212
8c43a48b 7213 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 7214 {
7215 if (operand_type_check (i.types[0], imm))
7216 i.vex.register_specifier = NULL;
7217 else
7218 {
7219 /* VEX.vvvv encodes one of the sources when the first
7220 operand is not an immediate. */
1ef99a7b 7221 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 7222 i.vex.register_specifier = i.op[0].regs;
7223 else
7224 i.vex.register_specifier = i.op[1].regs;
7225 }
7226
7227 /* Destination is a XMM register encoded in the ModRM.reg
7228 and VEX.R bit. */
7229 i.rm.reg = i.op[2].regs->reg_num;
7230 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7231 i.rex |= REX_R;
7232
7233 /* ModRM.rm and VEX.B encodes the other source. */
7234 if (!i.mem_operands)
7235 {
7236 i.rm.mode = 3;
7237
1ef99a7b 7238 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 7239 i.rm.regmem = i.op[1].regs->reg_num;
7240 else
7241 i.rm.regmem = i.op[0].regs->reg_num;
7242
7243 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7244 i.rex |= REX_B;
7245 }
7246 }
2426c15f 7247 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 7248 {
7249 i.vex.register_specifier = i.op[2].regs;
7250 if (!i.mem_operands)
7251 {
7252 i.rm.mode = 3;
7253 i.rm.regmem = i.op[1].regs->reg_num;
7254 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7255 i.rex |= REX_B;
7256 }
7257 }
29b0f896
AM		 7258 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7259 (if any) based on i.tm.extension_opcode. Again, we must be
7260 careful to make sure that segment/control/debug/test/MMX
7261 registers are coded into the i.rm.reg field. */
f88c9eb0 7262 else if (i.reg_operands)
29b0f896 7263 {
99018f42 7264 unsigned int op;
7ab9ffdd
L		 7265 unsigned int vex_reg = ~0;
7266
7267 for (op = 0; op < i.operands; op++)
dc821c5f 7268 if (i.types[op].bitfield.reg
7ab9ffdd 7269 || i.types[op].bitfield.regmmx
1b54b8d7 7270 || i.types[op].bitfield.regsimd
7e8b059b 7271 || i.types[op].bitfield.regbnd
43234a1e 7272 || i.types[op].bitfield.regmask
7ab9ffdd
L		 7273 || i.types[op].bitfield.sreg2
7274 || i.types[op].bitfield.sreg3
7275 || i.types[op].bitfield.control
7276 || i.types[op].bitfield.debug
7277 || i.types[op].bitfield.test)
7278 break;
c0209578 7279
7ab9ffdd
L		 7280 if (vex_3_sources)
7281 op = dest;
2426c15f 7282 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 7283 {
7284 /* For instructions with VexNDS, the register-only
7285 source operand is encoded in VEX prefix. */
7286 gas_assert (mem != (unsigned int) ~0);
c0f3af97 7287
7ab9ffdd 7288 if (op > mem)
c0f3af97 7289 {
7ab9ffdd
L		 7290 vex_reg = op++;
7291 gas_assert (op < i.operands);
c0f3af97
L		 7292 }
7293 else
c0f3af97 7294 {
f12dc422
L		 7295 /* Check register-only source operand when two source
7296 operands are swapped. */
7297 if (!i.tm.operand_types[op].bitfield.baseindex
7298 && i.tm.operand_types[op + 1].bitfield.baseindex)
7299 {
7300 vex_reg = op;
7301 op += 2;
7302 gas_assert (mem == (vex_reg + 1)
7303 && op < i.operands);
7304 }
7305 else
7306 {
7307 vex_reg = op + 1;
7308 gas_assert (vex_reg < i.operands);
7309 }
c0f3af97 7310 }
7ab9ffdd 7311 }
2426c15f 7312 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 7313 {
f12dc422 7314 /* For instructions with VexNDD, the register destination
7ab9ffdd 7315 is encoded in VEX prefix. */
f12dc422
L		 7316 if (i.mem_operands == 0)
7317 {
7318 /* There is no memory operand. */
7319 gas_assert ((op + 2) == i.operands);
7320 vex_reg = op + 1;
7321 }
7322 else
8d63c93e 7323 {
ed438a93
JB		 7324 /* There are only 2 non-immediate operands. */
7325 gas_assert (op < i.imm_operands + 2
7326 && i.operands == i.imm_operands + 2);
7327 vex_reg = i.imm_operands + 1;
f12dc422 7328 }
7ab9ffdd
L		 7329 }
7330 else
7331 gas_assert (op < i.operands);
99018f42 7332
7ab9ffdd
L		 7333 if (vex_reg != (unsigned int) ~0)
7334 {
f12dc422 7335 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 7336
dc821c5f
JB		 7337 if ((!type->bitfield.reg
7338 || (!type->bitfield.dword && !type->bitfield.qword))
10c17abd 7339 && !type->bitfield.regsimd
43234a1e 7340 && !operand_type_equal (type, &regmask))
7ab9ffdd 7341 abort ();
f88c9eb0 7342
7ab9ffdd
L		 7343 i.vex.register_specifier = i.op[vex_reg].regs;
7344 }
7345
1b9f0c97
L		 7346 /* Don't set OP operand twice. */
7347 if (vex_reg != op)
7ab9ffdd 7348 {
1b9f0c97
L		 7349 /* If there is an extension opcode to put here, the
7350 register number must be put into the regmem field. */
7351 if (i.tm.extension_opcode != None)
7352 {
7353 i.rm.regmem = i.op[op].regs->reg_num;
7354 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7355 i.rex |= REX_B;
43234a1e
L		 7356 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7357 i.vrex |= REX_B;
1b9f0c97
L		 7358 }
7359 else
7360 {
7361 i.rm.reg = i.op[op].regs->reg_num;
7362 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7363 i.rex |= REX_R;
43234a1e
L		 7364 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7365 i.vrex |= REX_R;
1b9f0c97 7366 }
7ab9ffdd 7367 }
252b5132 7368
29b0f896
AM		 7369 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7370 must set it to 3 to indicate this is a register operand
7371 in the regmem field. */
7372 if (!i.mem_operands)
7373 i.rm.mode = 3;
7374 }
252b5132 7375
29b0f896 7376 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 7377 if (i.tm.extension_opcode != None)
29b0f896
AM		 7378 i.rm.reg = i.tm.extension_opcode;
7379 }
7380 return default_seg;
7381}
252b5132 7382
29b0f896 7383static void
e3bb37b5 7384output_branch (void)
29b0f896
AM		 7385{
7386 char *p;
f8a5c266 7387 int size;
29b0f896
AM		 7388 int code16;
7389 int prefix;
7390 relax_substateT subtype;
7391 symbolS *sym;
7392 offsetT off;
7393
f8a5c266 7394 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 7395 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 7396
7397 prefix = 0;
7398 if (i.prefix[DATA_PREFIX] != 0)
252b5132 7399 {
29b0f896
AM		 7400 prefix = 1;
7401 i.prefixes -= 1;
7402 code16 ^= CODE16;
252b5132 7403 }
29b0f896
AM		 7404 /* Pentium4 branch hints. */
7405 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7406 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 7407 {
29b0f896
AM		 7408 prefix++;
7409 i.prefixes--;
7410 }
7411 if (i.prefix[REX_PREFIX] != 0)
7412 {
7413 prefix++;
7414 i.prefixes--;
2f66722d
AM		 7415 }
7416
7e8b059b
L		 7417 /* BND prefixed jump. */
7418 if (i.prefix[BND_PREFIX] != 0)
7419 {
7420 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7421 i.prefixes -= 1;
7422 }
7423
29b0f896
AM		 7424 if (i.prefixes != 0 && !intel_syntax)
7425 as_warn (_("skipping prefixes on this instruction"));
7426
7427 /* It's always a symbol; End frag & setup for relax.
7428 Make sure there is enough room in this frag for the largest
7429 instruction we may generate in md_convert_frag. This is 2
7430 bytes for the opcode and room for the prefix and largest
7431 displacement. */
7432 frag_grow (prefix + 2 + 4);
7433 /* Prefix and 1 opcode byte go in fr_fix. */
7434 p = frag_more (prefix + 1);
7435 if (i.prefix[DATA_PREFIX] != 0)
7436 *p++ = DATA_PREFIX_OPCODE;
7437 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7438 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7439 *p++ = i.prefix[SEG_PREFIX];
7440 if (i.prefix[REX_PREFIX] != 0)
7441 *p++ = i.prefix[REX_PREFIX];
7442 *p = i.tm.base_opcode;
7443
7444 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 7445 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 7446 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 7447 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 7448 else
f8a5c266 7449 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 7450 subtype |= code16;
3e73aa7c 7451
29b0f896
AM		 7452 sym = i.op[0].disps->X_add_symbol;
7453 off = i.op[0].disps->X_add_number;
3e73aa7c 7454
29b0f896
AM		 7455 if (i.op[0].disps->X_op != O_constant
7456 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 7457 {
29b0f896
AM		 7458 /* Handle complex expressions. */
7459 sym = make_expr_symbol (i.op[0].disps);
7460 off = 0;
7461 }
3e73aa7c 7462
29b0f896
AM		 7463 /* 1 possible extra opcode + 4 byte displacement go in var part.
7464 Pass reloc in fr_var. */
d258b828 7465 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 7466}
3e73aa7c 7467
bd7ab16b
L		 7468#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7469/* Return TRUE iff PLT32 relocation should be used for branching to
7470 symbol S. */
7471
7472static bfd_boolean
7473need_plt32_p (symbolS *s)
7474{
7475 /* PLT32 relocation is ELF only. */
7476 if (!IS_ELF)
7477 return FALSE;
7478
7479 /* Since there is no need to prepare for PLT branch on x86-64, we
7480 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7481 be used as a marker for 32-bit PC-relative branches. */
7482 if (!object_64bit)
7483 return FALSE;
7484
7485 /* Weak or undefined symbol need PLT32 relocation. */
7486 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7487 return TRUE;
7488
7489 /* Non-global symbol doesn't need PLT32 relocation. */
7490 if (! S_IS_EXTERNAL (s))
7491 return FALSE;
7492
7493 /* Other global symbols need PLT32 relocation. NB: Symbol with
7494 non-default visibilities are treated as normal global symbol
7495 so that PLT32 relocation can be used as a marker for 32-bit
7496 PC-relative branches. It is useful for linker relaxation. */
7497 return TRUE;
7498}
7499#endif
7500
29b0f896 7501static void
e3bb37b5 7502output_jump (void)
29b0f896
AM		 7503{
7504 char *p;
7505 int size;
3e02c1cc 7506 fixS *fixP;
bd7ab16b 7507 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
29b0f896 7508
40fb9820 7509 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 7510 {
7511 /* This is a loop or jecxz type instruction. */
7512 size = 1;
7513 if (i.prefix[ADDR_PREFIX] != 0)
7514 {
7515 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7516 i.prefixes -= 1;
7517 }
7518 /* Pentium4 branch hints. */
7519 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7520 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7521 {
7522 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7523 i.prefixes--;
3e73aa7c
JH		 7524 }
7525 }
29b0f896
AM		 7526 else
7527 {
7528 int code16;
3e73aa7c 7529
29b0f896
AM		 7530 code16 = 0;
7531 if (flag_code == CODE_16BIT)
7532 code16 = CODE16;
3e73aa7c 7533
29b0f896
AM		 7534 if (i.prefix[DATA_PREFIX] != 0)
7535 {
7536 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7537 i.prefixes -= 1;
7538 code16 ^= CODE16;
7539 }
252b5132 7540
29b0f896
AM		 7541 size = 4;
7542 if (code16)
7543 size = 2;
7544 }
9fcc94b6 7545
29b0f896
AM		 7546 if (i.prefix[REX_PREFIX] != 0)
7547 {
7548 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7549 i.prefixes -= 1;
7550 }
252b5132 7551
7e8b059b
L		 7552 /* BND prefixed jump. */
7553 if (i.prefix[BND_PREFIX] != 0)
7554 {
7555 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7556 i.prefixes -= 1;
7557 }
7558
29b0f896
AM		 7559 if (i.prefixes != 0 && !intel_syntax)
7560 as_warn (_("skipping prefixes on this instruction"));
e0890092 7561
42164a71
L		 7562 p = frag_more (i.tm.opcode_length + size);
7563 switch (i.tm.opcode_length)
7564 {
7565 case 2:
7566 *p++ = i.tm.base_opcode >> 8;
1a0670f3 7567 /* Fall through. */
42164a71
L		 7568 case 1:
7569 *p++ = i.tm.base_opcode;
7570 break;
7571 default:
7572 abort ();
7573 }
e0890092 7574
bd7ab16b
L		 7575#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7576 if (size == 4
7577 && jump_reloc == NO_RELOC
7578 && need_plt32_p (i.op[0].disps->X_add_symbol))
7579 jump_reloc = BFD_RELOC_X86_64_PLT32;
7580#endif
7581
7582 jump_reloc = reloc (size, 1, 1, jump_reloc);
7583
3e02c1cc 7584 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
bd7ab16b 7585 i.op[0].disps, 1, jump_reloc);
3e02c1cc
AM		 7586
7587 /* All jumps handled here are signed, but don't use a signed limit
7588 check for 32 and 16 bit jumps as we want to allow wrap around at
7589 4G and 64k respectively. */
7590 if (size == 1)
7591 fixP->fx_signed = 1;
29b0f896 7592}
e0890092 7593
29b0f896 7594static void
e3bb37b5 7595output_interseg_jump (void)
29b0f896
AM		 7596{
7597 char *p;
7598 int size;
7599 int prefix;
7600 int code16;
252b5132 7601
29b0f896
AM		 7602 code16 = 0;
7603 if (flag_code == CODE_16BIT)
7604 code16 = CODE16;
a217f122 7605
29b0f896
AM		 7606 prefix = 0;
7607 if (i.prefix[DATA_PREFIX] != 0)
7608 {
7609 prefix = 1;
7610 i.prefixes -= 1;
7611 code16 ^= CODE16;
7612 }
7613 if (i.prefix[REX_PREFIX] != 0)
7614 {
7615 prefix++;
7616 i.prefixes -= 1;
7617 }
252b5132 7618
29b0f896
AM		 7619 size = 4;
7620 if (code16)
7621 size = 2;
252b5132 7622
29b0f896
AM		 7623 if (i.prefixes != 0 && !intel_syntax)
7624 as_warn (_("skipping prefixes on this instruction"));
252b5132 7625
29b0f896
AM		 7626 /* 1 opcode; 2 segment; offset */
7627 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 7628
29b0f896
AM		 7629 if (i.prefix[DATA_PREFIX] != 0)
7630 *p++ = DATA_PREFIX_OPCODE;
252b5132 7631
29b0f896
AM		 7632 if (i.prefix[REX_PREFIX] != 0)
7633 *p++ = i.prefix[REX_PREFIX];
252b5132 7634
29b0f896
AM		 7635 *p++ = i.tm.base_opcode;
7636 if (i.op[1].imms->X_op == O_constant)
7637 {
7638 offsetT n = i.op[1].imms->X_add_number;
252b5132 7639
29b0f896
AM		 7640 if (size == 2
7641 && !fits_in_unsigned_word (n)
7642 && !fits_in_signed_word (n))
7643 {
7644 as_bad (_("16-bit jump out of range"));
7645 return;
7646 }
7647 md_number_to_chars (p, n, size);
7648 }
7649 else
7650 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7651 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 7652 if (i.op[0].imms->X_op != O_constant)
7653 as_bad (_("can't handle non absolute segment in `%s'"),
7654 i.tm.name);
7655 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7656}
a217f122 7657
29b0f896 7658static void
e3bb37b5 7659output_insn (void)
29b0f896 7660{
2bbd9c25
JJ		 7661 fragS *insn_start_frag;
7662 offsetT insn_start_off;
7663
29b0f896
AM		 7664 /* Tie dwarf2 debug info to the address at the start of the insn.
7665 We can't do this after the insn has been output as the current
7666 frag may have been closed off. eg. by frag_var. */
7667 dwarf2_emit_insn (0);
7668
2bbd9c25
JJ		 7669 insn_start_frag = frag_now;
7670 insn_start_off = frag_now_fix ();
7671
29b0f896 7672 /* Output jumps. */
40fb9820 7673 if (i.tm.opcode_modifier.jump)
29b0f896 7674 output_branch ();
40fb9820
L		 7675 else if (i.tm.opcode_modifier.jumpbyte
7676 || i.tm.opcode_modifier.jumpdword)
29b0f896 7677 output_jump ();
40fb9820 7678 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7679 output_interseg_jump ();
7680 else
7681 {
7682 /* Output normal instructions here. */
7683 char *p;
7684 unsigned char *q;
47465058 7685 unsigned int j;
331d2d0d 7686 unsigned int prefix;
4dffcebc 7687
e4e00185
AS		 7688 if (avoid_fence
7689 && i.tm.base_opcode == 0xfae
7690 && i.operands == 1
7691 && i.imm_operands == 1
7692 && (i.op[0].imms->X_add_number == 0xe8
7693 || i.op[0].imms->X_add_number == 0xf0
7694 || i.op[0].imms->X_add_number == 0xf8))
7695 {
7696 /* Encode lfence, mfence, and sfence as
7697 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7698 offsetT val = 0x240483f0ULL;
7699 p = frag_more (5);
7700 md_number_to_chars (p, val, 5);
7701 return;
7702 }
7703
d022bddd
IT		 7704 /* Some processors fail on LOCK prefix. This options makes
7705 assembler ignore LOCK prefix and serves as a workaround. */
7706 if (omit_lock_prefix)
7707 {
7708 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7709 return;
7710 i.prefix[LOCK_PREFIX] = 0;
7711 }
7712
43234a1e
L		 7713 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7714 don't need the explicit prefix. */
7715 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7716 {
c0f3af97 7717 switch (i.tm.opcode_length)
bc4bd9ab 7718 {
c0f3af97
L		 7719 case 3:
7720 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7721 {
c0f3af97 7722 prefix = (i.tm.base_opcode >> 24) & 0xff;
bd59a631 7723 add_prefix (prefix);
c0f3af97
L		 7724 }
7725 break;
7726 case 2:
7727 if ((i.tm.base_opcode & 0xff0000) != 0)
7728 {
7729 prefix = (i.tm.base_opcode >> 16) & 0xff;
bd59a631
JB		 7730 if (!i.tm.cpu_flags.bitfield.cpupadlock
7731 || prefix != REPE_PREFIX_OPCODE
7732 || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE))
4dffcebc
L		 7733 add_prefix (prefix);
7734 }
c0f3af97
L		 7735 break;
7736 case 1:
7737 break;
390c91cf
L		 7738 case 0:
7739 /* Check for pseudo prefixes. */
7740 as_bad_where (insn_start_frag->fr_file,
7741 insn_start_frag->fr_line,
7742 _("pseudo prefix without instruction"));
7743 return;
c0f3af97
L		 7744 default:
7745 abort ();
bc4bd9ab 7746 }
c0f3af97 7747
6d19a37a 7748#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7749 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7750 R_X86_64_GOTTPOFF relocation so that linker can safely
7751 perform IE->LE optimization. */
7752 if (x86_elf_abi == X86_64_X32_ABI
7753 && i.operands == 2
7754 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7755 && i.prefix[REX_PREFIX] == 0)
7756 add_prefix (REX_OPCODE);
6d19a37a 7757#endif
cf61b747 7758
c0f3af97
L		 7759 /* The prefix bytes. */
7760 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7761 if (*q)
7762 FRAG_APPEND_1_CHAR (*q);
0f10071e 7763 }
ae5c1c7b 7764 else
c0f3af97
L		 7765 {
7766 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7767 if (*q)
7768 switch (j)
7769 {
7770 case REX_PREFIX:
7771 /* REX byte is encoded in VEX prefix. */
7772 break;
7773 case SEG_PREFIX:
7774 case ADDR_PREFIX:
7775 FRAG_APPEND_1_CHAR (*q);
7776 break;
7777 default:
7778 /* There should be no other prefixes for instructions
7779 with VEX prefix. */
7780 abort ();
7781 }
7782
43234a1e
L		 7783 /* For EVEX instructions i.vrex should become 0 after
7784 build_evex_prefix. For VEX instructions upper 16 registers
7785 aren't available, so VREX should be 0. */
7786 if (i.vrex)
7787 abort ();
c0f3af97
L		 7788 /* Now the VEX prefix. */
7789 p = frag_more (i.vex.length);
7790 for (j = 0; j < i.vex.length; j++)
7791 p[j] = i.vex.bytes[j];
7792 }
252b5132 7793
29b0f896 7794 /* Now the opcode; be careful about word order here! */
4dffcebc 7795 if (i.tm.opcode_length == 1)
29b0f896
AM		 7796 {
7797 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7798 }
7799 else
7800 {
4dffcebc 7801 switch (i.tm.opcode_length)
331d2d0d 7802 {
43234a1e
L		 7803 case 4:
7804 p = frag_more (4);
7805 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7806 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7807 break;
4dffcebc 7808 case 3:
331d2d0d
L		 7809 p = frag_more (3);
7810 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7811 break;
7812 case 2:
7813 p = frag_more (2);
7814 break;
7815 default:
7816 abort ();
7817 break;
331d2d0d 7818 }
0f10071e 7819
29b0f896
AM		 7820 /* Put out high byte first: can't use md_number_to_chars! */
7821 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7822 *p = i.tm.base_opcode & 0xff;
7823 }
3e73aa7c 7824
29b0f896 7825 /* Now the modrm byte and sib byte (if present). */
40fb9820 7826 if (i.tm.opcode_modifier.modrm)
29b0f896 7827 {
4a3523fa
L		 7828 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7829 | i.rm.reg << 3
7830 | i.rm.mode << 6));
29b0f896
AM		 7831 /* If i.rm.regmem == ESP (4)
7832 && i.rm.mode != (Register mode)
7833 && not 16 bit
7834 ==> need second modrm byte. */
7835 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7836 && i.rm.mode != 3
dc821c5f 7837 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
4a3523fa
L		 7838 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7839 | i.sib.index << 3
7840 | i.sib.scale << 6));
29b0f896 7841 }
3e73aa7c 7842
29b0f896 7843 if (i.disp_operands)
2bbd9c25 7844 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7845
29b0f896 7846 if (i.imm_operands)
2bbd9c25 7847 output_imm (insn_start_frag, insn_start_off);
29b0f896 7848 }
252b5132 7849
29b0f896
AM		 7850#ifdef DEBUG386
7851 if (flag_debug)
7852 {
7b81dfbb 7853 pi ("" /*line*/, &i);
29b0f896
AM		 7854 }
7855#endif /* DEBUG386 */
7856}
252b5132 7857
e205caa7
L		 7858/* Return the size of the displacement operand N. */
7859
7860static int
7861disp_size (unsigned int n)
7862{
7863 int size = 4;
43234a1e 7864
b5014f7a 7865 if (i.types[n].bitfield.disp64)
40fb9820
L		 7866 size = 8;
7867 else if (i.types[n].bitfield.disp8)
7868 size = 1;
7869 else if (i.types[n].bitfield.disp16)
7870 size = 2;
e205caa7
L		 7871 return size;
7872}
7873
7874/* Return the size of the immediate operand N. */
7875
7876static int
7877imm_size (unsigned int n)
7878{
7879 int size = 4;
40fb9820
L		 7880 if (i.types[n].bitfield.imm64)
7881 size = 8;
7882 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7883 size = 1;
7884 else if (i.types[n].bitfield.imm16)
7885 size = 2;
e205caa7
L		 7886 return size;
7887}
7888
29b0f896 7889static void
64e74474 7890output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7891{
7892 char *p;
7893 unsigned int n;
252b5132 7894
29b0f896
AM		 7895 for (n = 0; n < i.operands; n++)
7896 {
b5014f7a 7897 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 7898 {
7899 if (i.op[n].disps->X_op == O_constant)
7900 {
e205caa7 7901 int size = disp_size (n);
43234a1e 7902 offsetT val = i.op[n].disps->X_add_number;
252b5132 7903
b5014f7a 7904 val = offset_in_range (val >> i.memshift, size);
29b0f896
AM		 7905 p = frag_more (size);
7906 md_number_to_chars (p, val, size);
7907 }
7908 else
7909 {
f86103b7 7910 enum bfd_reloc_code_real reloc_type;
e205caa7 7911 int size = disp_size (n);
40fb9820 7912 int sign = i.types[n].bitfield.disp32s;
29b0f896 7913 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7914 fixS *fixP;
29b0f896 7915
e205caa7 7916 /* We can't have 8 bit displacement here. */
9c2799c2 7917 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7918
29b0f896
AM		 7919 /* The PC relative address is computed relative
7920 to the instruction boundary, so in case immediate
7921 fields follows, we need to adjust the value. */
7922 if (pcrel && i.imm_operands)
7923 {
29b0f896 7924 unsigned int n1;
e205caa7 7925 int sz = 0;
252b5132 7926
29b0f896 7927 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7928 if (operand_type_check (i.types[n1], imm))
252b5132 7929 {
e205caa7
L		 7930 /* Only one immediate is allowed for PC
7931 relative address. */
9c2799c2 7932 gas_assert (sz == 0);
e205caa7
L		 7933 sz = imm_size (n1);
7934 i.op[n].disps->X_add_number -= sz;
252b5132 7935 }
29b0f896 7936 /* We should find the immediate. */
9c2799c2 7937 gas_assert (sz != 0);
29b0f896 7938 }
520dc8e8 7939
29b0f896 7940 p = frag_more (size);
d258b828 7941 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7942 if (GOT_symbol
2bbd9c25 7943 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7944 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7945 || reloc_type == BFD_RELOC_X86_64_32S
7946 || (reloc_type == BFD_RELOC_64
7947 && object_64bit))
d6ab8113
JB		 7948 && (i.op[n].disps->X_op == O_symbol
7949 || (i.op[n].disps->X_op == O_add
7950 && ((symbol_get_value_expression
7951 (i.op[n].disps->X_op_symbol)->X_op)
7952 == O_subtract))))
7953 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7954 {
7955 offsetT add;
7956
7957 if (insn_start_frag == frag_now)
7958 add = (p - frag_now->fr_literal) - insn_start_off;
7959 else
7960 {
7961 fragS *fr;
7962
7963 add = insn_start_frag->fr_fix - insn_start_off;
7964 for (fr = insn_start_frag->fr_next;
7965 fr && fr != frag_now; fr = fr->fr_next)
7966 add += fr->fr_fix;
7967 add += p - frag_now->fr_literal;
7968 }
7969
4fa24527 7970 if (!object_64bit)
7b81dfbb
AJ		 7971 {
7972 reloc_type = BFD_RELOC_386_GOTPC;
7973 i.op[n].imms->X_add_number += add;
7974 }
7975 else if (reloc_type == BFD_RELOC_64)
7976 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7977 else
7b81dfbb
AJ		 7978 /* Don't do the adjustment for x86-64, as there
7979 the pcrel addressing is relative to the _next_
7980 insn, and that is taken care of in other code. */
d6ab8113 7981 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7982 }
02a86693
L		 7983 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7984 size, i.op[n].disps, pcrel,
7985 reloc_type);
7986 /* Check for "call/jmp *mem", "mov mem, %reg",
7987 "test %reg, mem" and "binop mem, %reg" where binop
7988 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 7989 instructions. Always generate R_386_GOT32X for
7990 "sym*GOT" operand in 32-bit mode. */
7991 if ((generate_relax_relocations
7992 || (!object_64bit
7993 && i.rm.mode == 0
7994 && i.rm.regmem == 5))
7995 && (i.rm.mode == 2
7996 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 7997 && ((i.operands == 1
7998 && i.tm.base_opcode == 0xff
7999 && (i.rm.reg == 2 || i.rm.reg == 4))
8000 || (i.operands == 2
8001 && (i.tm.base_opcode == 0x8b
8002 || i.tm.base_opcode == 0x85
8003 || (i.tm.base_opcode & 0xc7) == 0x03))))
8004 {
8005 if (object_64bit)
8006 {
8007 fixP->fx_tcbit = i.rex != 0;
8008 if (i.base_reg
8009 && (i.base_reg->reg_num == RegRip
8010 || i.base_reg->reg_num == RegEip))
8011 fixP->fx_tcbit2 = 1;
8012 }
8013 else
8014 fixP->fx_tcbit2 = 1;
8015 }
29b0f896
AM		 8016 }
8017 }
8018 }
8019}
252b5132 8020
29b0f896 8021static void
64e74474 8022output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 8023{
8024 char *p;
8025 unsigned int n;
252b5132 8026
29b0f896
AM		 8027 for (n = 0; n < i.operands; n++)
8028 {
43234a1e
L		 8029 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8030 if (i.rounding && (int) n == i.rounding->operand)
8031 continue;
8032
40fb9820 8033 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 8034 {
8035 if (i.op[n].imms->X_op == O_constant)
8036 {
e205caa7 8037 int size = imm_size (n);
29b0f896 8038 offsetT val;
b4cac588 8039
29b0f896
AM		 8040 val = offset_in_range (i.op[n].imms->X_add_number,
8041 size);
8042 p = frag_more (size);
8043 md_number_to_chars (p, val, size);
8044 }
8045 else
8046 {
8047 /* Not absolute_section.
8048 Need a 32-bit fixup (don't support 8bit
8049 non-absolute imms). Try to support other
8050 sizes ... */
f86103b7 8051 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 8052 int size = imm_size (n);
8053 int sign;
29b0f896 8054
40fb9820 8055 if (i.types[n].bitfield.imm32s
a7d61044 8056 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 8057 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 8058 sign = 1;
e205caa7
L		 8059 else
8060 sign = 0;
520dc8e8 8061
29b0f896 8062 p = frag_more (size);
d258b828 8063 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 8064
2bbd9c25
JJ		 8065 /* This is tough to explain. We end up with this one if we
8066 * have operands that look like
8067 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8068 * obtain the absolute address of the GOT, and it is strongly
8069 * preferable from a performance point of view to avoid using
8070 * a runtime relocation for this. The actual sequence of
8071 * instructions often look something like:
8072 *
8073 * call .L66
8074 * .L66:
8075 * popl %ebx
8076 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8077 *
8078 * The call and pop essentially return the absolute address
8079 * of the label .L66 and store it in %ebx. The linker itself
8080 * will ultimately change the first operand of the addl so
8081 * that %ebx points to the GOT, but to keep things simple, the
8082 * .o file must have this operand set so that it generates not
8083 * the absolute address of .L66, but the absolute address of
8084 * itself. This allows the linker itself simply treat a GOTPC
8085 * relocation as asking for a pcrel offset to the GOT to be
8086 * added in, and the addend of the relocation is stored in the
8087 * operand field for the instruction itself.
8088 *
8089 * Our job here is to fix the operand so that it would add
8090 * the correct offset so that %ebx would point to itself. The
8091 * thing that is tricky is that .-.L66 will point to the
8092 * beginning of the instruction, so we need to further modify
8093 * the operand so that it will point to itself. There are
8094 * other cases where you have something like:
8095 *
8096 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8097 *
8098 * and here no correction would be required. Internally in
8099 * the assembler we treat operands of this form as not being
8100 * pcrel since the '.' is explicitly mentioned, and I wonder
8101 * whether it would simplify matters to do it this way. Who
8102 * knows. In earlier versions of the PIC patches, the
8103 * pcrel_adjust field was used to store the correction, but
8104 * since the expression is not pcrel, I felt it would be
8105 * confusing to do it this way. */
8106
d6ab8113 8107 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 8108 || reloc_type == BFD_RELOC_X86_64_32S
8109 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 8110 && GOT_symbol
8111 && GOT_symbol == i.op[n].imms->X_add_symbol
8112 && (i.op[n].imms->X_op == O_symbol
8113 || (i.op[n].imms->X_op == O_add
8114 && ((symbol_get_value_expression
8115 (i.op[n].imms->X_op_symbol)->X_op)
8116 == O_subtract))))
8117 {
2bbd9c25
JJ		 8118 offsetT add;
8119
8120 if (insn_start_frag == frag_now)
8121 add = (p - frag_now->fr_literal) - insn_start_off;
8122 else
8123 {
8124 fragS *fr;
8125
8126 add = insn_start_frag->fr_fix - insn_start_off;
8127 for (fr = insn_start_frag->fr_next;
8128 fr && fr != frag_now; fr = fr->fr_next)
8129 add += fr->fr_fix;
8130 add += p - frag_now->fr_literal;
8131 }
8132
4fa24527 8133 if (!object_64bit)
d6ab8113 8134 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 8135 else if (size == 4)
d6ab8113 8136 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 8137 else if (size == 8)
8138 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 8139 i.op[n].imms->X_add_number += add;
29b0f896 8140 }
29b0f896
AM		 8141 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8142 i.op[n].imms, 0, reloc_type);
8143 }
8144 }
8145 }
252b5132
RH		 8146}
8147\f
d182319b
JB		 8148/* x86_cons_fix_new is called via the expression parsing code when a
8149 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 8150static int cons_sign = -1;
8151
8152void
e3bb37b5 8153x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 8154 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 8155{
d258b828 8156 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 8157
8158#ifdef TE_PE
8159 if (exp->X_op == O_secrel)
8160 {
8161 exp->X_op = O_symbol;
8162 r = BFD_RELOC_32_SECREL;
8163 }
8164#endif
8165
8166 fix_new_exp (frag, off, len, exp, 0, r);
8167}
8168
357d1bd8
L		 8169/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8170 purpose of the `.dc.a' internal pseudo-op. */
8171
8172int
8173x86_address_bytes (void)
8174{
8175 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8176 return 4;
8177 return stdoutput->arch_info->bits_per_address / 8;
8178}
8179
d382c579
TG		 8180#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8181 || defined (LEX_AT)
d258b828 8182# define lex_got(reloc, adjust, types) NULL
718ddfc0 8183#else
f3c180ae
AM		 8184/* Parse operands of the form
8185 <symbol>@GOTOFF+<nnn>
8186 and similar .plt or .got references.
8187
8188 If we find one, set up the correct relocation in RELOC and copy the
8189 input string, minus the `@GOTOFF' into a malloc'd buffer for
8190 parsing by the calling routine. Return this buffer, and if ADJUST
8191 is non-null set it to the length of the string we removed from the
8192 input line. Otherwise return NULL. */
8193static char *
91d6fa6a 8194lex_got (enum bfd_reloc_code_real *rel,
64e74474 8195 int *adjust,
d258b828 8196 i386_operand_type *types)
f3c180ae 8197{
7b81dfbb
AJ		 8198 /* Some of the relocations depend on the size of what field is to
8199 be relocated. But in our callers i386_immediate and i386_displacement
8200 we don't yet know the operand size (this will be set by insn
8201 matching). Hence we record the word32 relocation here,
8202 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 8203 static const struct {
8204 const char *str;
cff8d58a 8205 int len;
4fa24527 8206 const enum bfd_reloc_code_real rel[2];
40fb9820 8207 const i386_operand_type types64;
f3c180ae 8208 } gotrel[] = {
8ce3d284 8209#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 8210 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8211 BFD_RELOC_SIZE32 },
8212 OPERAND_TYPE_IMM32_64 },
8ce3d284 8213#endif
cff8d58a
L		 8214 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8215 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 8216 OPERAND_TYPE_IMM64 },
cff8d58a
L		 8217 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8218 BFD_RELOC_X86_64_PLT32 },
40fb9820 8219 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8220 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8221 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 8222 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 8223 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8224 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 8225 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 8226 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8227 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 8228 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8229 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8230 BFD_RELOC_X86_64_TLSGD },
40fb9820 8231 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8232 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8233 _dummy_first_bfd_reloc_code_real },
40fb9820 8234 OPERAND_TYPE_NONE },
cff8d58a
L		 8235 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8236 BFD_RELOC_X86_64_TLSLD },
40fb9820 8237 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8238 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8239 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 8240 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8241 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8242 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 8243 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 8244 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8245 _dummy_first_bfd_reloc_code_real },
40fb9820 8246 OPERAND_TYPE_NONE },
cff8d58a
L		 8247 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8248 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 8249 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 8250 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8251 _dummy_first_bfd_reloc_code_real },
40fb9820 8252 OPERAND_TYPE_NONE },
cff8d58a
L		 8253 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8254 _dummy_first_bfd_reloc_code_real },
40fb9820 8255 OPERAND_TYPE_NONE },
cff8d58a
L		 8256 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8257 BFD_RELOC_X86_64_GOT32 },
40fb9820 8258 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 8259 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8260 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 8261 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8262 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8263 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 8264 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 8265 };
8266 char *cp;
8267 unsigned int j;
8268
d382c579 8269#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 8270 if (!IS_ELF)
8271 return NULL;
d382c579 8272#endif
718ddfc0 8273
f3c180ae 8274 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 8275 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 8276 return NULL;
8277
47465058 8278 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 8279 {
cff8d58a 8280 int len = gotrel[j].len;
28f81592 8281 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 8282 {
4fa24527 8283 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 8284 {
28f81592
AM		 8285 int first, second;
8286 char *tmpbuf, *past_reloc;
f3c180ae 8287
91d6fa6a 8288 *rel = gotrel[j].rel[object_64bit];
f3c180ae 8289
3956db08
JB		 8290 if (types)
8291 {
8292 if (flag_code != CODE_64BIT)
40fb9820
L		 8293 {
8294 types->bitfield.imm32 = 1;
8295 types->bitfield.disp32 = 1;
8296 }
3956db08
JB		 8297 else
8298 *types = gotrel[j].types64;
8299 }
8300
8fd4256d 8301 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 8302 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8303
28f81592 8304 /* The length of the first part of our input line. */
f3c180ae 8305 first = cp - input_line_pointer;
28f81592
AM		 8306
8307 /* The second part goes from after the reloc token until
67c11a9b 8308 (and including) an end_of_line char or comma. */
28f81592 8309 past_reloc = cp + 1 + len;
67c11a9b
AM		 8310 cp = past_reloc;
8311 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8312 ++cp;
8313 second = cp + 1 - past_reloc;
28f81592
AM		 8314
8315 /* Allocate and copy string. The trailing NUL shouldn't
8316 be necessary, but be safe. */
add39d23 8317 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 8318 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 8319 if (second != 0 && *past_reloc != ' ')
8320 /* Replace the relocation token with ' ', so that
8321 errors like foo@GOTOFF1 will be detected. */
8322 tmpbuf[first++] = ' ';
af89796a
L		 8323 else
8324 /* Increment length by 1 if the relocation token is
8325 removed. */
8326 len++;
8327 if (adjust)
8328 *adjust = len;
0787a12d
AM		 8329 memcpy (tmpbuf + first, past_reloc, second);
8330 tmpbuf[first + second] = '\0';
f3c180ae
AM		 8331 return tmpbuf;
8332 }
8333
4fa24527
JB		 8334 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8335 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 8336 return NULL;
8337 }
8338 }
8339
8340 /* Might be a symbol version string. Don't as_bad here. */
8341 return NULL;
8342}
4e4f7c87 8343#endif
f3c180ae 8344
a988325c
NC		 8345#ifdef TE_PE
8346#ifdef lex_got
8347#undef lex_got
8348#endif
8349/* Parse operands of the form
8350 <symbol>@SECREL32+<nnn>
8351
8352 If we find one, set up the correct relocation in RELOC and copy the
8353 input string, minus the `@SECREL32' into a malloc'd buffer for
8354 parsing by the calling routine. Return this buffer, and if ADJUST
8355 is non-null set it to the length of the string we removed from the
34bca508
L		 8356 input line. Otherwise return NULL.
8357
a988325c
NC		 8358 This function is copied from the ELF version above adjusted for PE targets. */
8359
8360static char *
8361lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8362 int *adjust ATTRIBUTE_UNUSED,
d258b828 8363 i386_operand_type *types)
a988325c
NC		 8364{
8365 static const struct
8366 {
8367 const char *str;
8368 int len;
8369 const enum bfd_reloc_code_real rel[2];
8370 const i386_operand_type types64;
8371 }
8372 gotrel[] =
8373 {
8374 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8375 BFD_RELOC_32_SECREL },
8376 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8377 };
8378
8379 char *cp;
8380 unsigned j;
8381
8382 for (cp = input_line_pointer; *cp != '@'; cp++)
8383 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8384 return NULL;
8385
8386 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8387 {
8388 int len = gotrel[j].len;
8389
8390 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8391 {
8392 if (gotrel[j].rel[object_64bit] != 0)
8393 {
8394 int first, second;
8395 char *tmpbuf, *past_reloc;
8396
8397 *rel = gotrel[j].rel[object_64bit];
8398 if (adjust)
8399 *adjust = len;
8400
8401 if (types)
8402 {
8403 if (flag_code != CODE_64BIT)
8404 {
8405 types->bitfield.imm32 = 1;
8406 types->bitfield.disp32 = 1;
8407 }
8408 else
8409 *types = gotrel[j].types64;
8410 }
8411
8412 /* The length of the first part of our input line. */
8413 first = cp - input_line_pointer;
8414
8415 /* The second part goes from after the reloc token until
8416 (and including) an end_of_line char or comma. */
8417 past_reloc = cp + 1 + len;
8418 cp = past_reloc;
8419 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8420 ++cp;
8421 second = cp + 1 - past_reloc;
8422
8423 /* Allocate and copy string. The trailing NUL shouldn't
8424 be necessary, but be safe. */
add39d23 8425 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 8426 memcpy (tmpbuf, input_line_pointer, first);
8427 if (second != 0 && *past_reloc != ' ')
8428 /* Replace the relocation token with ' ', so that
8429 errors like foo@SECLREL321 will be detected. */
8430 tmpbuf[first++] = ' ';
8431 memcpy (tmpbuf + first, past_reloc, second);
8432 tmpbuf[first + second] = '\0';
8433 return tmpbuf;
8434 }
8435
8436 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8437 gotrel[j].str, 1 << (5 + object_64bit));
8438 return NULL;
8439 }
8440 }
8441
8442 /* Might be a symbol version string. Don't as_bad here. */
8443 return NULL;
8444}
8445
8446#endif /* TE_PE */
8447
62ebcb5c 8448bfd_reloc_code_real_type
e3bb37b5 8449x86_cons (expressionS *exp, int size)
f3c180ae 8450{
62ebcb5c
AM		 8451 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8452
ee86248c
JB		 8453 intel_syntax = -intel_syntax;
8454
3c7b9c2c 8455 exp->X_md = 0;
4fa24527 8456 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 8457 {
8458 /* Handle @GOTOFF and the like in an expression. */
8459 char *save;
8460 char *gotfree_input_line;
4a57f2cf 8461 int adjust = 0;
f3c180ae
AM		 8462
8463 save = input_line_pointer;
d258b828 8464 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 8465 if (gotfree_input_line)
8466 input_line_pointer = gotfree_input_line;
8467
8468 expression (exp);
8469
8470 if (gotfree_input_line)
8471 {
8472 /* expression () has merrily parsed up to the end of line,
8473 or a comma - in the wrong buffer. Transfer how far
8474 input_line_pointer has moved to the right buffer. */
8475 input_line_pointer = (save
8476 + (input_line_pointer - gotfree_input_line)
8477 + adjust);
8478 free (gotfree_input_line);
3992d3b7
AM		 8479 if (exp->X_op == O_constant
8480 || exp->X_op == O_absent
8481 || exp->X_op == O_illegal
0398aac5 8482 || exp->X_op == O_register
3992d3b7
AM		 8483 || exp->X_op == O_big)
8484 {
8485 char c = *input_line_pointer;
8486 *input_line_pointer = 0;
8487 as_bad (_("missing or invalid expression `%s'"), save);
8488 *input_line_pointer = c;
8489 }
f3c180ae
AM		 8490 }
8491 }
8492 else
8493 expression (exp);
ee86248c
JB		 8494
8495 intel_syntax = -intel_syntax;
8496
8497 if (intel_syntax)
8498 i386_intel_simplify (exp);
62ebcb5c
AM		 8499
8500 return got_reloc;
f3c180ae 8501}
f3c180ae 8502
9f32dd5b
L		 8503static void
8504signed_cons (int size)
6482c264 8505{
d182319b
JB		 8506 if (flag_code == CODE_64BIT)
8507 cons_sign = 1;
8508 cons (size);
8509 cons_sign = -1;
6482c264
NC		 8510}
8511
d182319b 8512#ifdef TE_PE
6482c264 8513static void
7016a5d5 8514pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 8515{
8516 expressionS exp;
8517
8518 do
8519 {
8520 expression (&exp);
8521 if (exp.X_op == O_symbol)
8522 exp.X_op = O_secrel;
8523
8524 emit_expr (&exp, 4);
8525 }
8526 while (*input_line_pointer++ == ',');
8527
8528 input_line_pointer--;
8529 demand_empty_rest_of_line ();
8530}
6482c264
NC		 8531#endif
8532
43234a1e
L		 8533/* Handle Vector operations. */
8534
8535static char *
8536check_VecOperations (char *op_string, char *op_end)
8537{
8538 const reg_entry *mask;
8539 const char *saved;
8540 char *end_op;
8541
8542 while (*op_string
8543 && (op_end == NULL || op_string < op_end))
8544 {
8545 saved = op_string;
8546 if (*op_string == '{')
8547 {
8548 op_string++;
8549
8550 /* Check broadcasts. */
8551 if (strncmp (op_string, "1to", 3) == 0)
8552 {
8553 int bcst_type;
8554
8555 if (i.broadcast)
8556 goto duplicated_vec_op;
8557
8558 op_string += 3;
8559 if (*op_string == '8')
8e6e0792 8560 bcst_type = 8;
b28d1bda 8561 else if (*op_string == '4')
8e6e0792 8562 bcst_type = 4;
b28d1bda 8563 else if (*op_string == '2')
8e6e0792 8564 bcst_type = 2;
43234a1e
L		 8565 else if (*op_string == '1'
8566 && *(op_string+1) == '6')
8567 {
8e6e0792 8568 bcst_type = 16;
43234a1e
L		 8569 op_string++;
8570 }
8571 else
8572 {
8573 as_bad (_("Unsupported broadcast: `%s'"), saved);
8574 return NULL;
8575 }
8576 op_string++;
8577
8578 broadcast_op.type = bcst_type;
8579 broadcast_op.operand = this_operand;
8580 i.broadcast = &broadcast_op;
8581 }
8582 /* Check masking operation. */
8583 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8584 {
8585 /* k0 can't be used for write mask. */
6d2cd6b2 8586 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
43234a1e 8587 {
6d2cd6b2
JB		 8588 as_bad (_("`%s%s' can't be used for write mask"),
8589 register_prefix, mask->reg_name);
43234a1e
L		 8590 return NULL;
8591 }
8592
8593 if (!i.mask)
8594 {
8595 mask_op.mask = mask;
8596 mask_op.zeroing = 0;
8597 mask_op.operand = this_operand;
8598 i.mask = &mask_op;
8599 }
8600 else
8601 {
8602 if (i.mask->mask)
8603 goto duplicated_vec_op;
8604
8605 i.mask->mask = mask;
8606
8607 /* Only "{z}" is allowed here. No need to check
8608 zeroing mask explicitly. */
8609 if (i.mask->operand != this_operand)
8610 {
8611 as_bad (_("invalid write mask `%s'"), saved);
8612 return NULL;
8613 }
8614 }
8615
8616 op_string = end_op;
8617 }
8618 /* Check zeroing-flag for masking operation. */
8619 else if (*op_string == 'z')
8620 {
8621 if (!i.mask)
8622 {
8623 mask_op.mask = NULL;
8624 mask_op.zeroing = 1;
8625 mask_op.operand = this_operand;
8626 i.mask = &mask_op;
8627 }
8628 else
8629 {
8630 if (i.mask->zeroing)
8631 {
8632 duplicated_vec_op:
8633 as_bad (_("duplicated `%s'"), saved);
8634 return NULL;
8635 }
8636
8637 i.mask->zeroing = 1;
8638
8639 /* Only "{%k}" is allowed here. No need to check mask
8640 register explicitly. */
8641 if (i.mask->operand != this_operand)
8642 {
8643 as_bad (_("invalid zeroing-masking `%s'"),
8644 saved);
8645 return NULL;
8646 }
8647 }
8648
8649 op_string++;
8650 }
8651 else
8652 goto unknown_vec_op;
8653
8654 if (*op_string != '}')
8655 {
8656 as_bad (_("missing `}' in `%s'"), saved);
8657 return NULL;
8658 }
8659 op_string++;
0ba3a731
L		 8660
8661 /* Strip whitespace since the addition of pseudo prefixes
8662 changed how the scrubber treats '{'. */
8663 if (is_space_char (*op_string))
8664 ++op_string;
8665
43234a1e
L		 8666 continue;
8667 }
8668 unknown_vec_op:
8669 /* We don't know this one. */
8670 as_bad (_("unknown vector operation: `%s'"), saved);
8671 return NULL;
8672 }
8673
6d2cd6b2
JB		 8674 if (i.mask && i.mask->zeroing && !i.mask->mask)
8675 {
8676 as_bad (_("zeroing-masking only allowed with write mask"));
8677 return NULL;
8678 }
8679
43234a1e
L		 8680 return op_string;
8681}
8682
252b5132 8683static int
70e41ade 8684i386_immediate (char *imm_start)
252b5132
RH		 8685{
8686 char *save_input_line_pointer;
f3c180ae 8687 char *gotfree_input_line;
252b5132 8688 segT exp_seg = 0;
47926f60 8689 expressionS *exp;
40fb9820
L		 8690 i386_operand_type types;
8691
0dfbf9d7 8692 operand_type_set (&types, ~0);
252b5132
RH		 8693
8694 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8695 {
31b2323c
L		 8696 as_bad (_("at most %d immediate operands are allowed"),
8697 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8698 return 0;
8699 }
8700
8701 exp = &im_expressions[i.imm_operands++];
520dc8e8 8702 i.op[this_operand].imms = exp;
252b5132
RH		 8703
8704 if (is_space_char (*imm_start))
8705 ++imm_start;
8706
8707 save_input_line_pointer = input_line_pointer;
8708 input_line_pointer = imm_start;
8709
d258b828 8710 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8711 if (gotfree_input_line)
8712 input_line_pointer = gotfree_input_line;
252b5132
RH		 8713
8714 exp_seg = expression (exp);
8715
83183c0c 8716 SKIP_WHITESPACE ();
43234a1e
L		 8717
8718 /* Handle vector operations. */
8719 if (*input_line_pointer == '{')
8720 {
8721 input_line_pointer = check_VecOperations (input_line_pointer,
8722 NULL);
8723 if (input_line_pointer == NULL)
8724 return 0;
8725 }
8726
252b5132 8727 if (*input_line_pointer)
f3c180ae 8728 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8729
8730 input_line_pointer = save_input_line_pointer;
f3c180ae 8731 if (gotfree_input_line)
ee86248c
JB		 8732 {
8733 free (gotfree_input_line);
8734
8735 if (exp->X_op == O_constant || exp->X_op == O_register)
8736 exp->X_op = O_illegal;
8737 }
8738
8739 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8740}
252b5132 8741
ee86248c
JB		 8742static int
8743i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8744 i386_operand_type types, const char *imm_start)
8745{
8746 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8747 {
313c53d1
L		 8748 if (imm_start)
8749 as_bad (_("missing or invalid immediate expression `%s'"),
8750 imm_start);
3992d3b7 8751 return 0;
252b5132 8752 }
3e73aa7c 8753 else if (exp->X_op == O_constant)
252b5132 8754 {
47926f60 8755 /* Size it properly later. */
40fb9820 8756 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8757 /* If not 64bit, sign extend val. */
8758 if (flag_code != CODE_64BIT
4eed87de
AM		 8759 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8760 exp->X_add_number
8761 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8762 }
4c63da97 8763#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8764 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8765 && exp_seg != absolute_section
47926f60 8766 && exp_seg != text_section
24eab124
AM		 8767 && exp_seg != data_section
8768 && exp_seg != bss_section
8769 && exp_seg != undefined_section
f86103b7 8770 && !bfd_is_com_section (exp_seg))
252b5132 8771 {
d0b47220 8772 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8773 return 0;
8774 }
8775#endif
a841bdf5 8776 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8777 {
313c53d1
L		 8778 if (imm_start)
8779 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8780 return 0;
8781 }
252b5132
RH		 8782 else
8783 {
8784 /* This is an address. The size of the address will be
24eab124 8785 determined later, depending on destination register,
3e73aa7c 8786 suffix, or the default for the section. */
40fb9820
L		 8787 i.types[this_operand].bitfield.imm8 = 1;
8788 i.types[this_operand].bitfield.imm16 = 1;
8789 i.types[this_operand].bitfield.imm32 = 1;
8790 i.types[this_operand].bitfield.imm32s = 1;
8791 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8792 i.types[this_operand] = operand_type_and (i.types[this_operand],
8793 types);
252b5132
RH		 8794 }
8795
8796 return 1;
8797}
8798
551c1ca1 8799static char *
e3bb37b5 8800i386_scale (char *scale)
252b5132 8801{
551c1ca1
AM		 8802 offsetT val;
8803 char *save = input_line_pointer;
252b5132 8804
551c1ca1
AM		 8805 input_line_pointer = scale;
8806 val = get_absolute_expression ();
8807
8808 switch (val)
252b5132 8809 {
551c1ca1 8810 case 1:
252b5132
RH		 8811 i.log2_scale_factor = 0;
8812 break;
551c1ca1 8813 case 2:
252b5132
RH		 8814 i.log2_scale_factor = 1;
8815 break;
551c1ca1 8816 case 4:
252b5132
RH		 8817 i.log2_scale_factor = 2;
8818 break;
551c1ca1 8819 case 8:
252b5132
RH		 8820 i.log2_scale_factor = 3;
8821 break;
8822 default:
a724f0f4
JB		 8823 {
8824 char sep = *input_line_pointer;
8825
8826 *input_line_pointer = '\0';
8827 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8828 scale);
8829 *input_line_pointer = sep;
8830 input_line_pointer = save;
8831 return NULL;
8832 }
252b5132 8833 }
29b0f896 8834 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8835 {
8836 as_warn (_("scale factor of %d without an index register"),
24eab124 8837 1 << i.log2_scale_factor);
252b5132 8838 i.log2_scale_factor = 0;
252b5132 8839 }
551c1ca1
AM		 8840 scale = input_line_pointer;
8841 input_line_pointer = save;
8842 return scale;
252b5132
RH		 8843}
8844
252b5132 8845static int
e3bb37b5 8846i386_displacement (char *disp_start, char *disp_end)
252b5132 8847{
29b0f896 8848 expressionS *exp;
252b5132
RH		 8849 segT exp_seg = 0;
8850 char *save_input_line_pointer;
f3c180ae 8851 char *gotfree_input_line;
40fb9820
L		 8852 int override;
8853 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8854 int ret;
252b5132 8855
31b2323c
L		 8856 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8857 {
8858 as_bad (_("at most %d displacement operands are allowed"),
8859 MAX_MEMORY_OPERANDS);
8860 return 0;
8861 }
8862
0dfbf9d7 8863 operand_type_set (&bigdisp, 0);
40fb9820
L		 8864 if ((i.types[this_operand].bitfield.jumpabsolute)
8865 || (!current_templates->start->opcode_modifier.jump
8866 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8867 {
40fb9820 8868 bigdisp.bitfield.disp32 = 1;
e05278af 8869 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8870 if (flag_code == CODE_64BIT)
8871 {
8872 if (!override)
8873 {
8874 bigdisp.bitfield.disp32s = 1;
8875 bigdisp.bitfield.disp64 = 1;
8876 }
8877 }
8878 else if ((flag_code == CODE_16BIT) ^ override)
8879 {
8880 bigdisp.bitfield.disp32 = 0;
8881 bigdisp.bitfield.disp16 = 1;
8882 }
e05278af
JB		 8883 }
8884 else
8885 {
8886 /* For PC-relative branches, the width of the displacement
8887 is dependent upon data size, not address size. */
e05278af 8888 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8889 if (flag_code == CODE_64BIT)
8890 {
8891 if (override || i.suffix == WORD_MNEM_SUFFIX)
8892 bigdisp.bitfield.disp16 = 1;
8893 else
8894 {
8895 bigdisp.bitfield.disp32 = 1;
8896 bigdisp.bitfield.disp32s = 1;
8897 }
8898 }
8899 else
e05278af
JB		 8900 {
8901 if (!override)
8902 override = (i.suffix == (flag_code != CODE_16BIT
8903 ? WORD_MNEM_SUFFIX
8904 : LONG_MNEM_SUFFIX));
40fb9820
L		 8905 bigdisp.bitfield.disp32 = 1;
8906 if ((flag_code == CODE_16BIT) ^ override)
8907 {
8908 bigdisp.bitfield.disp32 = 0;
8909 bigdisp.bitfield.disp16 = 1;
8910 }
e05278af 8911 }
e05278af 8912 }
c6fb90c8
L		 8913 i.types[this_operand] = operand_type_or (i.types[this_operand],
8914 bigdisp);
252b5132
RH		 8915
8916 exp = &disp_expressions[i.disp_operands];
520dc8e8 8917 i.op[this_operand].disps = exp;
252b5132
RH		 8918 i.disp_operands++;
8919 save_input_line_pointer = input_line_pointer;
8920 input_line_pointer = disp_start;
8921 END_STRING_AND_SAVE (disp_end);
8922
8923#ifndef GCC_ASM_O_HACK
8924#define GCC_ASM_O_HACK 0
8925#endif
8926#if GCC_ASM_O_HACK
8927 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8928 if (i.types[this_operand].bitfield.baseIndex
24eab124 8929 && displacement_string_end[-1] == '+')
252b5132
RH		 8930 {
8931 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8932 constraint within gcc asm statements.
8933 For instance:
8934
8935 #define _set_tssldt_desc(n,addr,limit,type) \
8936 __asm__ __volatile__ ( \
8937 "movw %w2,%0\n\t" \
8938 "movw %w1,2+%0\n\t" \
8939 "rorl $16,%1\n\t" \
8940 "movb %b1,4+%0\n\t" \
8941 "movb %4,5+%0\n\t" \
8942 "movb $0,6+%0\n\t" \
8943 "movb %h1,7+%0\n\t" \
8944 "rorl $16,%1" \
8945 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8946
8947 This works great except that the output assembler ends
8948 up looking a bit weird if it turns out that there is
8949 no offset. You end up producing code that looks like:
8950
8951 #APP
8952 movw $235,(%eax)
8953 movw %dx,2+(%eax)
8954 rorl $16,%edx
8955 movb %dl,4+(%eax)
8956 movb $137,5+(%eax)
8957 movb $0,6+(%eax)
8958 movb %dh,7+(%eax)
8959 rorl $16,%edx
8960 #NO_APP
8961
47926f60 8962 So here we provide the missing zero. */
24eab124
AM		 8963
8964 *displacement_string_end = '0';
252b5132
RH		 8965 }
8966#endif
d258b828 8967 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8968 if (gotfree_input_line)
8969 input_line_pointer = gotfree_input_line;
252b5132 8970
24eab124 8971 exp_seg = expression (exp);
252b5132 8972
636c26b0
AM		 8973 SKIP_WHITESPACE ();
8974 if (*input_line_pointer)
8975 as_bad (_("junk `%s' after expression"), input_line_pointer);
8976#if GCC_ASM_O_HACK
8977 RESTORE_END_STRING (disp_end + 1);
8978#endif
636c26b0 8979 input_line_pointer = save_input_line_pointer;
636c26b0 8980 if (gotfree_input_line)
ee86248c
JB		 8981 {
8982 free (gotfree_input_line);
8983
8984 if (exp->X_op == O_constant || exp->X_op == O_register)
8985 exp->X_op = O_illegal;
8986 }
8987
8988 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8989
8990 RESTORE_END_STRING (disp_end);
8991
8992 return ret;
8993}
8994
8995static int
8996i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8997 i386_operand_type types, const char *disp_start)
8998{
8999 i386_operand_type bigdisp;
9000 int ret = 1;
636c26b0 9001
24eab124
AM		 9002 /* We do this to make sure that the section symbol is in
9003 the symbol table. We will ultimately change the relocation
47926f60 9004 to be relative to the beginning of the section. */
1ae12ab7 9005 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 9006 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
9007 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 9008 {
636c26b0 9009 if (exp->X_op != O_symbol)
3992d3b7 9010 goto inv_disp;
636c26b0 9011
e5cb08ac 9012 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 9013 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
9014 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 9015 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 9016 exp->X_op = O_subtract;
9017 exp->X_op_symbol = GOT_symbol;
1ae12ab7 9018 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 9019 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 9020 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
9021 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 9022 else
29b0f896 9023 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 9024 }
252b5132 9025
3992d3b7
AM		 9026 else if (exp->X_op == O_absent
9027 || exp->X_op == O_illegal
ee86248c 9028 || exp->X_op == O_big)
2daf4fd8 9029 {
3992d3b7
AM		 9030 inv_disp:
9031 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 9032 disp_start);
3992d3b7 9033 ret = 0;
2daf4fd8
AM		 9034 }
9035
0e1147d9
L		 9036 else if (flag_code == CODE_64BIT
9037 && !i.prefix[ADDR_PREFIX]
9038 && exp->X_op == O_constant)
9039 {
9040 /* Since displacement is signed extended to 64bit, don't allow
9041 disp32 and turn off disp32s if they are out of range. */
9042 i.types[this_operand].bitfield.disp32 = 0;
9043 if (!fits_in_signed_long (exp->X_add_number))
9044 {
9045 i.types[this_operand].bitfield.disp32s = 0;
9046 if (i.types[this_operand].bitfield.baseindex)
9047 {
9048 as_bad (_("0x%lx out range of signed 32bit displacement"),
9049 (long) exp->X_add_number);
9050 ret = 0;
9051 }
9052 }
9053 }
9054
4c63da97 9055#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 9056 else if (exp->X_op != O_constant
9057 && OUTPUT_FLAVOR == bfd_target_aout_flavour
9058 && exp_seg != absolute_section
9059 && exp_seg != text_section
9060 && exp_seg != data_section
9061 && exp_seg != bss_section
9062 && exp_seg != undefined_section
9063 && !bfd_is_com_section (exp_seg))
24eab124 9064 {
d0b47220 9065 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 9066 ret = 0;
24eab124 9067 }
252b5132 9068#endif
3956db08 9069
40fb9820
L		 9070 /* Check if this is a displacement only operand. */
9071 bigdisp = i.types[this_operand];
9072 bigdisp.bitfield.disp8 = 0;
9073 bigdisp.bitfield.disp16 = 0;
9074 bigdisp.bitfield.disp32 = 0;
9075 bigdisp.bitfield.disp32s = 0;
9076 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 9077 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 9078 i.types[this_operand] = operand_type_and (i.types[this_operand],
9079 types);
3956db08 9080
3992d3b7 9081 return ret;
252b5132
RH		 9082}
9083
2abc2bec
JB		 9084/* Return the active addressing mode, taking address override and
9085 registers forming the address into consideration. Update the
9086 address override prefix if necessary. */
47926f60 9087
2abc2bec
JB		 9088static enum flag_code
9089i386_addressing_mode (void)
252b5132 9090{
be05d201
L		 9091 enum flag_code addr_mode;
9092
9093 if (i.prefix[ADDR_PREFIX])
9094 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
9095 else
9096 {
9097 addr_mode = flag_code;
9098
24eab124 9099#if INFER_ADDR_PREFIX
be05d201
L		 9100 if (i.mem_operands == 0)
9101 {
9102 /* Infer address prefix from the first memory operand. */
9103 const reg_entry *addr_reg = i.base_reg;
9104
9105 if (addr_reg == NULL)
9106 addr_reg = i.index_reg;
eecb386c 9107
be05d201
L		 9108 if (addr_reg)
9109 {
9110 if (addr_reg->reg_num == RegEip
9111 || addr_reg->reg_num == RegEiz
dc821c5f 9112 || addr_reg->reg_type.bitfield.dword)
be05d201
L		 9113 addr_mode = CODE_32BIT;
9114 else if (flag_code != CODE_64BIT
dc821c5f 9115 && addr_reg->reg_type.bitfield.word)
be05d201
L		 9116 addr_mode = CODE_16BIT;
9117
9118 if (addr_mode != flag_code)
9119 {
9120 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
9121 i.prefixes += 1;
9122 /* Change the size of any displacement too. At most one
9123 of Disp16 or Disp32 is set.
9124 FIXME. There doesn't seem to be any real need for
9125 separate Disp16 and Disp32 flags. The same goes for
9126 Imm16 and Imm32. Removing them would probably clean
9127 up the code quite a lot. */
9128 if (flag_code != CODE_64BIT
9129 && (i.types[this_operand].bitfield.disp16
9130 || i.types[this_operand].bitfield.disp32))
9131 i.types[this_operand]
9132 = operand_type_xor (i.types[this_operand], disp16_32);
9133 }
9134 }
9135 }
24eab124 9136#endif
be05d201
L		 9137 }
9138
2abc2bec
JB		 9139 return addr_mode;
9140}
9141
9142/* Make sure the memory operand we've been dealt is valid.
9143 Return 1 on success, 0 on a failure. */
9144
9145static int
9146i386_index_check (const char *operand_string)
9147{
9148 const char *kind = "base/index";
9149 enum flag_code addr_mode = i386_addressing_mode ();
9150
fc0763e6
JB		 9151 if (current_templates->start->opcode_modifier.isstring
9152 && !current_templates->start->opcode_modifier.immext
9153 && (current_templates->end[-1].opcode_modifier.isstring
9154 || i.mem_operands))
9155 {
9156 /* Memory operands of string insns are special in that they only allow
9157 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 9158 const reg_entry *expected_reg;
9159 static const char *di_si[][2] =
9160 {
9161 { "esi", "edi" },
9162 { "si", "di" },
9163 { "rsi", "rdi" }
9164 };
9165 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 9166
9167 kind = "string address";
9168
8325cc63 9169 if (current_templates->start->opcode_modifier.repprefixok)
fc0763e6
JB		 9170 {
9171 i386_operand_type type = current_templates->end[-1].operand_types[0];
9172
9173 if (!type.bitfield.baseindex
9174 || ((!i.mem_operands != !intel_syntax)
9175 && current_templates->end[-1].operand_types[1]
9176 .bitfield.baseindex))
9177 type = current_templates->end[-1].operand_types[1];
be05d201
L		 9178 expected_reg = hash_find (reg_hash,
9179 di_si[addr_mode][type.bitfield.esseg]);
9180
fc0763e6
JB		 9181 }
9182 else
be05d201 9183 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 9184
be05d201
L		 9185 if (i.base_reg != expected_reg
9186 || i.index_reg
fc0763e6 9187 || operand_type_check (i.types[this_operand], disp))
fc0763e6 9188 {
be05d201
L		 9189 /* The second memory operand must have the same size as
9190 the first one. */
9191 if (i.mem_operands
9192 && i.base_reg
9193 && !((addr_mode == CODE_64BIT
dc821c5f 9194 && i.base_reg->reg_type.bitfield.qword)
be05d201 9195 || (addr_mode == CODE_32BIT
dc821c5f
JB		 9196 ? i.base_reg->reg_type.bitfield.dword
9197 : i.base_reg->reg_type.bitfield.word)))
be05d201
L		 9198 goto bad_address;
9199
fc0763e6
JB		 9200 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9201 operand_string,
9202 intel_syntax ? '[' : '(',
9203 register_prefix,
be05d201 9204 expected_reg->reg_name,
fc0763e6 9205 intel_syntax ? ']' : ')');
be05d201 9206 return 1;
fc0763e6 9207 }
be05d201
L		 9208 else
9209 return 1;
9210
9211bad_address:
9212 as_bad (_("`%s' is not a valid %s expression"),
9213 operand_string, kind);
9214 return 0;
3e73aa7c
JH		 9215 }
9216 else
9217 {
be05d201
L		 9218 if (addr_mode != CODE_16BIT)
9219 {
9220 /* 32-bit/64-bit checks. */
9221 if ((i.base_reg
9222 && (addr_mode == CODE_64BIT
dc821c5f
JB		 9223 ? !i.base_reg->reg_type.bitfield.qword
9224 : !i.base_reg->reg_type.bitfield.dword)
be05d201
L		 9225 && (i.index_reg
9226 || (i.base_reg->reg_num
9227 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9228 || (i.index_reg
1b54b8d7
JB		 9229 && !i.index_reg->reg_type.bitfield.xmmword
9230 && !i.index_reg->reg_type.bitfield.ymmword
9231 && !i.index_reg->reg_type.bitfield.zmmword
be05d201 9232 && ((addr_mode == CODE_64BIT
dc821c5f 9233 ? !(i.index_reg->reg_type.bitfield.qword
be05d201 9234 || i.index_reg->reg_num == RegRiz)
dc821c5f 9235 : !(i.index_reg->reg_type.bitfield.dword
be05d201
L		 9236 || i.index_reg->reg_num == RegEiz))
9237 || !i.index_reg->reg_type.bitfield.baseindex)))
9238 goto bad_address;
8178be5b
JB		 9239
9240 /* bndmk, bndldx, and bndstx have special restrictions. */
9241 if (current_templates->start->base_opcode == 0xf30f1b
9242 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9243 {
9244 /* They cannot use RIP-relative addressing. */
9245 if (i.base_reg && i.base_reg->reg_num == RegRip)
9246 {
9247 as_bad (_("`%s' cannot be used here"), operand_string);
9248 return 0;
9249 }
9250
9251 /* bndldx and bndstx ignore their scale factor. */
9252 if (current_templates->start->base_opcode != 0xf30f1b
9253 && i.log2_scale_factor)
9254 as_warn (_("register scaling is being ignored here"));
9255 }
be05d201
L		 9256 }
9257 else
3e73aa7c 9258 {
be05d201 9259 /* 16-bit checks. */
3e73aa7c 9260 if ((i.base_reg
dc821c5f 9261 && (!i.base_reg->reg_type.bitfield.word
40fb9820 9262 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 9263 || (i.index_reg
dc821c5f 9264 && (!i.index_reg->reg_type.bitfield.word
40fb9820 9265 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 9266 || !(i.base_reg
9267 && i.base_reg->reg_num < 6
9268 && i.index_reg->reg_num >= 6
9269 && i.log2_scale_factor == 0))))
be05d201 9270 goto bad_address;
3e73aa7c
JH		 9271 }
9272 }
be05d201 9273 return 1;
24eab124 9274}
252b5132 9275
43234a1e
L		 9276/* Handle vector immediates. */
9277
9278static int
9279RC_SAE_immediate (const char *imm_start)
9280{
9281 unsigned int match_found, j;
9282 const char *pstr = imm_start;
9283 expressionS *exp;
9284
9285 if (*pstr != '{')
9286 return 0;
9287
9288 pstr++;
9289 match_found = 0;
9290 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9291 {
9292 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9293 {
9294 if (!i.rounding)
9295 {
9296 rc_op.type = RC_NamesTable[j].type;
9297 rc_op.operand = this_operand;
9298 i.rounding = &rc_op;
9299 }
9300 else
9301 {
9302 as_bad (_("duplicated `%s'"), imm_start);
9303 return 0;
9304 }
9305 pstr += RC_NamesTable[j].len;
9306 match_found = 1;
9307 break;
9308 }
9309 }
9310 if (!match_found)
9311 return 0;
9312
9313 if (*pstr++ != '}')
9314 {
9315 as_bad (_("Missing '}': '%s'"), imm_start);
9316 return 0;
9317 }
9318 /* RC/SAE immediate string should contain nothing more. */;
9319 if (*pstr != 0)
9320 {
9321 as_bad (_("Junk after '}': '%s'"), imm_start);
9322 return 0;
9323 }
9324
9325 exp = &im_expressions[i.imm_operands++];
9326 i.op[this_operand].imms = exp;
9327
9328 exp->X_op = O_constant;
9329 exp->X_add_number = 0;
9330 exp->X_add_symbol = (symbolS *) 0;
9331 exp->X_op_symbol = (symbolS *) 0;
9332
9333 i.types[this_operand].bitfield.imm8 = 1;
9334 return 1;
9335}
9336
8325cc63
JB		 9337/* Only string instructions can have a second memory operand, so
9338 reduce current_templates to just those if it contains any. */
9339static int
9340maybe_adjust_templates (void)
9341{
9342 const insn_template *t;
9343
9344 gas_assert (i.mem_operands == 1);
9345
9346 for (t = current_templates->start; t < current_templates->end; ++t)
9347 if (t->opcode_modifier.isstring)
9348 break;
9349
9350 if (t < current_templates->end)
9351 {
9352 static templates aux_templates;
9353 bfd_boolean recheck;
9354
9355 aux_templates.start = t;
9356 for (; t < current_templates->end; ++t)
9357 if (!t->opcode_modifier.isstring)
9358 break;
9359 aux_templates.end = t;
9360
9361 /* Determine whether to re-check the first memory operand. */
9362 recheck = (aux_templates.start != current_templates->start
9363 || t != current_templates->end);
9364
9365 current_templates = &aux_templates;
9366
9367 if (recheck)
9368 {
9369 i.mem_operands = 0;
9370 if (i.memop1_string != NULL
9371 && i386_index_check (i.memop1_string) == 0)
9372 return 0;
9373 i.mem_operands = 1;
9374 }
9375 }
9376
9377 return 1;
9378}
9379
fc0763e6 9380/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 9381 on error. */
252b5132 9382
252b5132 9383static int
a7619375 9384i386_att_operand (char *operand_string)
252b5132 9385{
af6bdddf
AM		 9386 const reg_entry *r;
9387 char *end_op;
24eab124 9388 char *op_string = operand_string;
252b5132 9389
24eab124 9390 if (is_space_char (*op_string))
252b5132
RH		 9391 ++op_string;
9392
24eab124 9393 /* We check for an absolute prefix (differentiating,
47926f60 9394 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 9395 if (*op_string == ABSOLUTE_PREFIX)
9396 {
9397 ++op_string;
9398 if (is_space_char (*op_string))
9399 ++op_string;
40fb9820 9400 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 9401 }
252b5132 9402
47926f60 9403 /* Check if operand is a register. */
4d1bb795 9404 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 9405 {
40fb9820
L		 9406 i386_operand_type temp;
9407
24eab124
AM		 9408 /* Check for a segment override by searching for ':' after a
9409 segment register. */
9410 op_string = end_op;
9411 if (is_space_char (*op_string))
9412 ++op_string;
40fb9820
L		 9413 if (*op_string == ':'
9414 && (r->reg_type.bitfield.sreg2
9415 || r->reg_type.bitfield.sreg3))
24eab124
AM		 9416 {
9417 switch (r->reg_num)
9418 {
9419 case 0:
9420 i.seg[i.mem_operands] = &es;
9421 break;
9422 case 1:
9423 i.seg[i.mem_operands] = &cs;
9424 break;
9425 case 2:
9426 i.seg[i.mem_operands] = &ss;
9427 break;
9428 case 3:
9429 i.seg[i.mem_operands] = &ds;
9430 break;
9431 case 4:
9432 i.seg[i.mem_operands] = &fs;
9433 break;
9434 case 5:
9435 i.seg[i.mem_operands] = &gs;
9436 break;
9437 }
252b5132 9438
24eab124 9439 /* Skip the ':' and whitespace. */
252b5132
RH		 9440 ++op_string;
9441 if (is_space_char (*op_string))
24eab124 9442 ++op_string;
252b5132 9443
24eab124
AM		 9444 if (!is_digit_char (*op_string)
9445 && !is_identifier_char (*op_string)
9446 && *op_string != '('
9447 && *op_string != ABSOLUTE_PREFIX)
9448 {
9449 as_bad (_("bad memory operand `%s'"), op_string);
9450 return 0;
9451 }
47926f60 9452 /* Handle case of %es:*foo. */
24eab124
AM		 9453 if (*op_string == ABSOLUTE_PREFIX)
9454 {
9455 ++op_string;
9456 if (is_space_char (*op_string))
9457 ++op_string;
40fb9820 9458 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 9459 }
9460 goto do_memory_reference;
9461 }
43234a1e
L		 9462
9463 /* Handle vector operations. */
9464 if (*op_string == '{')
9465 {
9466 op_string = check_VecOperations (op_string, NULL);
9467 if (op_string == NULL)
9468 return 0;
9469 }
9470
24eab124
AM		 9471 if (*op_string)
9472 {
d0b47220 9473 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 9474 return 0;
9475 }
40fb9820
L		 9476 temp = r->reg_type;
9477 temp.bitfield.baseindex = 0;
c6fb90c8
L		 9478 i.types[this_operand] = operand_type_or (i.types[this_operand],
9479 temp);
7d5e4556 9480 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 9481 i.op[this_operand].regs = r;
24eab124
AM		 9482 i.reg_operands++;
9483 }
af6bdddf
AM		 9484 else if (*op_string == REGISTER_PREFIX)
9485 {
9486 as_bad (_("bad register name `%s'"), op_string);
9487 return 0;
9488 }
24eab124 9489 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 9490 {
24eab124 9491 ++op_string;
40fb9820 9492 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 9493 {
d0b47220 9494 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 9495 return 0;
9496 }
9497 if (!i386_immediate (op_string))
9498 return 0;
9499 }
43234a1e
L		 9500 else if (RC_SAE_immediate (operand_string))
9501 {
9502 /* If it is a RC or SAE immediate, do nothing. */
9503 ;
9504 }
24eab124
AM		 9505 else if (is_digit_char (*op_string)
9506 || is_identifier_char (*op_string)
d02603dc 9507 || *op_string == '"'
e5cb08ac 9508 || *op_string == '(')
24eab124 9509 {
47926f60 9510 /* This is a memory reference of some sort. */
af6bdddf 9511 char *base_string;
252b5132 9512
47926f60 9513 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 9514 char *displacement_string_start;
9515 char *displacement_string_end;
43234a1e 9516 char *vop_start;
252b5132 9517
24eab124 9518 do_memory_reference:
8325cc63
JB		 9519 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9520 return 0;
24eab124 9521 if ((i.mem_operands == 1
40fb9820 9522 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 9523 || i.mem_operands == 2)
9524 {
9525 as_bad (_("too many memory references for `%s'"),
9526 current_templates->start->name);
9527 return 0;
9528 }
252b5132 9529
24eab124
AM		 9530 /* Check for base index form. We detect the base index form by
9531 looking for an ')' at the end of the operand, searching
9532 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9533 after the '('. */
af6bdddf 9534 base_string = op_string + strlen (op_string);
c3332e24 9535
43234a1e
L		 9536 /* Handle vector operations. */
9537 vop_start = strchr (op_string, '{');
9538 if (vop_start && vop_start < base_string)
9539 {
9540 if (check_VecOperations (vop_start, base_string) == NULL)
9541 return 0;
9542 base_string = vop_start;
9543 }
9544
af6bdddf
AM		 9545 --base_string;
9546 if (is_space_char (*base_string))
9547 --base_string;
252b5132 9548
47926f60 9549 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 9550 displacement_string_start = op_string;
9551 displacement_string_end = base_string + 1;
252b5132 9552
24eab124
AM		 9553 if (*base_string == ')')
9554 {
af6bdddf 9555 char *temp_string;
24eab124
AM		 9556 unsigned int parens_balanced = 1;
9557 /* We've already checked that the number of left & right ()'s are
47926f60 9558 equal, so this loop will not be infinite. */
24eab124
AM		 9559 do
9560 {
9561 base_string--;
9562 if (*base_string == ')')
9563 parens_balanced++;
9564 if (*base_string == '(')
9565 parens_balanced--;
9566 }
9567 while (parens_balanced);
c3332e24 9568
af6bdddf 9569 temp_string = base_string;
c3332e24 9570
24eab124 9571 /* Skip past '(' and whitespace. */
252b5132
RH		 9572 ++base_string;
9573 if (is_space_char (*base_string))
24eab124 9574 ++base_string;
252b5132 9575
af6bdddf 9576 if (*base_string == ','
4eed87de
AM		 9577 || ((i.base_reg = parse_register (base_string, &end_op))
9578 != NULL))
252b5132 9579 {
af6bdddf 9580 displacement_string_end = temp_string;
252b5132 9581
40fb9820 9582 i.types[this_operand].bitfield.baseindex = 1;
252b5132 9583
af6bdddf 9584 if (i.base_reg)
24eab124 9585 {
24eab124
AM		 9586 base_string = end_op;
9587 if (is_space_char (*base_string))
9588 ++base_string;
af6bdddf
AM		 9589 }
9590
9591 /* There may be an index reg or scale factor here. */
9592 if (*base_string == ',')
9593 {
9594 ++base_string;
9595 if (is_space_char (*base_string))
9596 ++base_string;
9597
4eed87de
AM		 9598 if ((i.index_reg = parse_register (base_string, &end_op))
9599 != NULL)
24eab124 9600 {
af6bdddf 9601 base_string = end_op;
24eab124
AM		 9602 if (is_space_char (*base_string))
9603 ++base_string;
af6bdddf
AM		 9604 if (*base_string == ',')
9605 {
9606 ++base_string;
9607 if (is_space_char (*base_string))
9608 ++base_string;
9609 }
e5cb08ac 9610 else if (*base_string != ')')
af6bdddf 9611 {
4eed87de
AM		 9612 as_bad (_("expecting `,' or `)' "
9613 "after index register in `%s'"),
af6bdddf
AM		 9614 operand_string);
9615 return 0;
9616 }
24eab124 9617 }
af6bdddf 9618 else if (*base_string == REGISTER_PREFIX)
24eab124 9619 {
f76bf5e0
L		 9620 end_op = strchr (base_string, ',');
9621 if (end_op)
9622 *end_op = '\0';
af6bdddf 9623 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 9624 return 0;
9625 }
252b5132 9626
47926f60 9627 /* Check for scale factor. */
551c1ca1 9628 if (*base_string != ')')
af6bdddf 9629 {
551c1ca1
AM		 9630 char *end_scale = i386_scale (base_string);
9631
9632 if (!end_scale)
af6bdddf 9633 return 0;
24eab124 9634
551c1ca1 9635 base_string = end_scale;
af6bdddf
AM		 9636 if (is_space_char (*base_string))
9637 ++base_string;
9638 if (*base_string != ')')
9639 {
4eed87de
AM		 9640 as_bad (_("expecting `)' "
9641 "after scale factor in `%s'"),
af6bdddf
AM		 9642 operand_string);
9643 return 0;
9644 }
9645 }
9646 else if (!i.index_reg)
24eab124 9647 {
4eed87de
AM		 9648 as_bad (_("expecting index register or scale factor "
9649 "after `,'; got '%c'"),
af6bdddf 9650 *base_string);
24eab124
AM		 9651 return 0;
9652 }
9653 }
af6bdddf 9654 else if (*base_string != ')')
24eab124 9655 {
4eed87de
AM		 9656 as_bad (_("expecting `,' or `)' "
9657 "after base register in `%s'"),
af6bdddf 9658 operand_string);
24eab124
AM		 9659 return 0;
9660 }
c3332e24 9661 }
af6bdddf 9662 else if (*base_string == REGISTER_PREFIX)
c3332e24 9663 {
f76bf5e0
L		 9664 end_op = strchr (base_string, ',');
9665 if (end_op)
9666 *end_op = '\0';
af6bdddf 9667 as_bad (_("bad register name `%s'"), base_string);
24eab124 9668 return 0;
c3332e24 9669 }
24eab124
AM		 9670 }
9671
9672 /* If there's an expression beginning the operand, parse it,
9673 assuming displacement_string_start and
9674 displacement_string_end are meaningful. */
9675 if (displacement_string_start != displacement_string_end)
9676 {
9677 if (!i386_displacement (displacement_string_start,
9678 displacement_string_end))
9679 return 0;
9680 }
9681
9682 /* Special case for (%dx) while doing input/output op. */
9683 if (i.base_reg
2fb5be8d 9684 && i.base_reg->reg_type.bitfield.inoutportreg
24eab124
AM		 9685 && i.index_reg == 0
9686 && i.log2_scale_factor == 0
9687 && i.seg[i.mem_operands] == 0
40fb9820 9688 && !operand_type_check (i.types[this_operand], disp))
24eab124 9689 {
2fb5be8d 9690 i.types[this_operand] = i.base_reg->reg_type;
24eab124
AM		 9691 return 1;
9692 }
9693
eecb386c
AM		 9694 if (i386_index_check (operand_string) == 0)
9695 return 0;
5c07affc 9696 i.types[this_operand].bitfield.mem = 1;
8325cc63
JB		 9697 if (i.mem_operands == 0)
9698 i.memop1_string = xstrdup (operand_string);
24eab124
AM		 9699 i.mem_operands++;
9700 }
9701 else
ce8a8b2f
AM		 9702 {
9703 /* It's not a memory operand; argh! */
24eab124
AM		 9704 as_bad (_("invalid char %s beginning operand %d `%s'"),
9705 output_invalid (*op_string),
9706 this_operand + 1,
9707 op_string);
9708 return 0;
9709 }
47926f60 9710 return 1; /* Normal return. */
252b5132
RH		 9711}
9712\f
fa94de6b
RM		 9713/* Calculate the maximum variable size (i.e., excluding fr_fix)
9714 that an rs_machine_dependent frag may reach. */
9715
9716unsigned int
9717i386_frag_max_var (fragS *frag)
9718{
9719 /* The only relaxable frags are for jumps.
9720 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9721 gas_assert (frag->fr_type == rs_machine_dependent);
9722 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9723}
9724
b084df0b
L		 9725#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9726static int
8dcea932 9727elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 9728{
9729 /* STT_GNU_IFUNC symbol must go through PLT. */
9730 if ((symbol_get_bfdsym (fr_symbol)->flags
9731 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9732 return 0;
9733
9734 if (!S_IS_EXTERNAL (fr_symbol))
9735 /* Symbol may be weak or local. */
9736 return !S_IS_WEAK (fr_symbol);
9737
8dcea932
L		 9738 /* Global symbols with non-default visibility can't be preempted. */
9739 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9740 return 1;
9741
9742 if (fr_var != NO_RELOC)
9743 switch ((enum bfd_reloc_code_real) fr_var)
9744 {
9745 case BFD_RELOC_386_PLT32:
9746 case BFD_RELOC_X86_64_PLT32:
33eaf5de 9747 /* Symbol with PLT relocation may be preempted. */
8dcea932
L		 9748 return 0;
9749 default:
9750 abort ();
9751 }
9752
b084df0b
L		 9753 /* Global symbols with default visibility in a shared library may be
9754 preempted by another definition. */
8dcea932 9755 return !shared;
b084df0b
L		 9756}
9757#endif
9758
ee7fcc42
AM		 9759/* md_estimate_size_before_relax()
9760
9761 Called just before relax() for rs_machine_dependent frags. The x86
9762 assembler uses these frags to handle variable size jump
9763 instructions.
9764
9765 Any symbol that is now undefined will not become defined.
9766 Return the correct fr_subtype in the frag.
9767 Return the initial "guess for variable size of frag" to caller.
9768 The guess is actually the growth beyond the fixed part. Whatever
9769 we do to grow the fixed or variable part contributes to our
9770 returned value. */
9771
252b5132 9772int
7016a5d5 9773md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9774{
252b5132 9775 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9776 check for un-relaxable symbols. On an ELF system, we can't relax
9777 an externally visible symbol, because it may be overridden by a
9778 shared library. */
9779 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9780#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9781 || (IS_ELF
8dcea932
L		 9782 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9783 fragP->fr_var))
fbeb56a4
DK		 9784#endif
9785#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9786 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9787 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9788#endif
9789 )
252b5132 9790 {
b98ef147
AM		 9791 /* Symbol is undefined in this segment, or we need to keep a
9792 reloc so that weak symbols can be overridden. */
9793 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9794 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9795 unsigned char *opcode;
9796 int old_fr_fix;
f6af82bd 9797
ee7fcc42 9798 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9799 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9800 else if (size == 2)
f6af82bd 9801 reloc_type = BFD_RELOC_16_PCREL;
bd7ab16b
L		 9802#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9803 else if (need_plt32_p (fragP->fr_symbol))
9804 reloc_type = BFD_RELOC_X86_64_PLT32;
9805#endif
f6af82bd
AM		 9806 else
9807 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9808
ee7fcc42
AM		 9809 old_fr_fix = fragP->fr_fix;
9810 opcode = (unsigned char *) fragP->fr_opcode;
9811
fddf5b5b 9812 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9813 {
fddf5b5b
AM		 9814 case UNCOND_JUMP:
9815 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9816 opcode[0] = 0xe9;
252b5132 9817 fragP->fr_fix += size;
062cd5e7
AS		 9818 fix_new (fragP, old_fr_fix, size,
9819 fragP->fr_symbol,
9820 fragP->fr_offset, 1,
9821 reloc_type);
252b5132
RH		 9822 break;
9823
fddf5b5b 9824 case COND_JUMP86:
412167cb
AM		 9825 if (size == 2
9826 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9827 {
9828 /* Negate the condition, and branch past an
9829 unconditional jump. */
9830 opcode[0] ^= 1;
9831 opcode[1] = 3;
9832 /* Insert an unconditional jump. */
9833 opcode[2] = 0xe9;
9834 /* We added two extra opcode bytes, and have a two byte
9835 offset. */
9836 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9837 fix_new (fragP, old_fr_fix + 2, 2,
9838 fragP->fr_symbol,
9839 fragP->fr_offset, 1,
9840 reloc_type);
fddf5b5b
AM		 9841 break;
9842 }
9843 /* Fall through. */
9844
9845 case COND_JUMP:
412167cb
AM		 9846 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9847 {
3e02c1cc
AM		 9848 fixS *fixP;
9849
412167cb 9850 fragP->fr_fix += 1;
3e02c1cc
AM		 9851 fixP = fix_new (fragP, old_fr_fix, 1,
9852 fragP->fr_symbol,
9853 fragP->fr_offset, 1,
9854 BFD_RELOC_8_PCREL);
9855 fixP->fx_signed = 1;
412167cb
AM		 9856 break;
9857 }
93c2a809 9858
24eab124 9859 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9860 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9861 opcode[1] = opcode[0] + 0x10;
f6af82bd 9862 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9863 /* We've added an opcode byte. */
9864 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9865 fix_new (fragP, old_fr_fix + 1, size,
9866 fragP->fr_symbol,
9867 fragP->fr_offset, 1,
9868 reloc_type);
252b5132 9869 break;
fddf5b5b
AM		 9870
9871 default:
9872 BAD_CASE (fragP->fr_subtype);
9873 break;
252b5132
RH		 9874 }
9875 frag_wane (fragP);
ee7fcc42 9876 return fragP->fr_fix - old_fr_fix;
252b5132 9877 }
93c2a809 9878
93c2a809
AM		 9879 /* Guess size depending on current relax state. Initially the relax
9880 state will correspond to a short jump and we return 1, because
9881 the variable part of the frag (the branch offset) is one byte
9882 long. However, we can relax a section more than once and in that
9883 case we must either set fr_subtype back to the unrelaxed state,
9884 or return the value for the appropriate branch. */
9885 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9886}
9887
47926f60
KH		 9888/* Called after relax() is finished.
9889
9890 In: Address of frag.
9891 fr_type == rs_machine_dependent.
9892 fr_subtype is what the address relaxed to.
9893
9894 Out: Any fixSs and constants are set up.
9895 Caller will turn frag into a ".space 0". */
9896
252b5132 9897void
7016a5d5
TG		 9898md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9899 fragS *fragP)
252b5132 9900{
29b0f896 9901 unsigned char *opcode;
252b5132 9902 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9903 offsetT target_address;
9904 offsetT opcode_address;
252b5132 9905 unsigned int extension = 0;
847f7ad4 9906 offsetT displacement_from_opcode_start;
252b5132
RH		 9907
9908 opcode = (unsigned char *) fragP->fr_opcode;
9909
47926f60 9910 /* Address we want to reach in file space. */
252b5132 9911 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9912
47926f60 9913 /* Address opcode resides at in file space. */
252b5132
RH		 9914 opcode_address = fragP->fr_address + fragP->fr_fix;
9915
47926f60 9916 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9917 displacement_from_opcode_start = target_address - opcode_address;
9918
fddf5b5b 9919 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9920 {
47926f60
KH		 9921 /* Don't have to change opcode. */
9922 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9923 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9924 }
9925 else
9926 {
9927 if (no_cond_jump_promotion
9928 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9929 as_warn_where (fragP->fr_file, fragP->fr_line,
9930 _("long jump required"));
252b5132 9931
fddf5b5b
AM		 9932 switch (fragP->fr_subtype)
9933 {
9934 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9935 extension = 4; /* 1 opcode + 4 displacement */
9936 opcode[0] = 0xe9;
9937 where_to_put_displacement = &opcode[1];
9938 break;
252b5132 9939
fddf5b5b
AM		 9940 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9941 extension = 2; /* 1 opcode + 2 displacement */
9942 opcode[0] = 0xe9;
9943 where_to_put_displacement = &opcode[1];
9944 break;
252b5132 9945
fddf5b5b
AM		 9946 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9947 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9948 extension = 5; /* 2 opcode + 4 displacement */
9949 opcode[1] = opcode[0] + 0x10;
9950 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9951 where_to_put_displacement = &opcode[2];
9952 break;
252b5132 9953
fddf5b5b
AM		 9954 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9955 extension = 3; /* 2 opcode + 2 displacement */
9956 opcode[1] = opcode[0] + 0x10;
9957 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9958 where_to_put_displacement = &opcode[2];
9959 break;
252b5132 9960
fddf5b5b
AM		 9961 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9962 extension = 4;
9963 opcode[0] ^= 1;
9964 opcode[1] = 3;
9965 opcode[2] = 0xe9;
9966 where_to_put_displacement = &opcode[3];
9967 break;
9968
9969 default:
9970 BAD_CASE (fragP->fr_subtype);
9971 break;
9972 }
252b5132 9973 }
fddf5b5b 9974
7b81dfbb
AJ		 9975 /* If size if less then four we are sure that the operand fits,
9976 but if it's 4, then it could be that the displacement is larger
9977 then -/+ 2GB. */
9978 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9979 && object_64bit
9980 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9981 + ((addressT) 1 << 31))
9982 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9983 {
9984 as_bad_where (fragP->fr_file, fragP->fr_line,
9985 _("jump target out of range"));
9986 /* Make us emit 0. */
9987 displacement_from_opcode_start = extension;
9988 }
47926f60 9989 /* Now put displacement after opcode. */
252b5132
RH		 9990 md_number_to_chars ((char *) where_to_put_displacement,
9991 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9992 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9993 fragP->fr_fix += extension;
9994}
9995\f
7016a5d5 9996/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9997 by our caller that we have all the info we need to fix it up.
9998
7016a5d5
TG		 9999 Parameter valP is the pointer to the value of the bits.
10000
252b5132
RH		 10001 On the 386, immediates, displacements, and data pointers are all in
10002 the same (little-endian) format, so we don't need to care about which
10003 we are handling. */
10004
94f592af 10005void
7016a5d5 10006md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 10007{
94f592af 10008 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 10009 valueT value = *valP;
252b5132 10010
f86103b7 10011#if !defined (TE_Mach)
93382f6d
AM		 10012 if (fixP->fx_pcrel)
10013 {
10014 switch (fixP->fx_r_type)
10015 {
5865bb77
ILT		 10016 default:
10017 break;
10018
d6ab8113
JB		 10019 case BFD_RELOC_64:
10020 fixP->fx_r_type = BFD_RELOC_64_PCREL;
10021 break;
93382f6d 10022 case BFD_RELOC_32:
ae8887b5 10023 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 10024 fixP->fx_r_type = BFD_RELOC_32_PCREL;
10025 break;
10026 case BFD_RELOC_16:
10027 fixP->fx_r_type = BFD_RELOC_16_PCREL;
10028 break;
10029 case BFD_RELOC_8:
10030 fixP->fx_r_type = BFD_RELOC_8_PCREL;
10031 break;
10032 }
10033 }
252b5132 10034
a161fe53 10035 if (fixP->fx_addsy != NULL
31312f95 10036 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 10037 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 10038 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 10039 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 10040 && !use_rela_relocations)
252b5132 10041 {
31312f95
AM		 10042 /* This is a hack. There should be a better way to handle this.
10043 This covers for the fact that bfd_install_relocation will
10044 subtract the current location (for partial_inplace, PC relative
10045 relocations); see more below. */
252b5132 10046#ifndef OBJ_AOUT
718ddfc0 10047 if (IS_ELF
252b5132
RH		 10048#ifdef TE_PE
10049 || OUTPUT_FLAVOR == bfd_target_coff_flavour
10050#endif
10051 )
10052 value += fixP->fx_where + fixP->fx_frag->fr_address;
10053#endif
10054#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 10055 if (IS_ELF)
252b5132 10056 {
6539b54b 10057 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 10058
6539b54b 10059 if ((sym_seg == seg
2f66722d 10060 || (symbol_section_p (fixP->fx_addsy)
6539b54b 10061 && sym_seg != absolute_section))
af65af87 10062 && !generic_force_reloc (fixP))
2f66722d
AM		 10063 {
10064 /* Yes, we add the values in twice. This is because
6539b54b
AM		 10065 bfd_install_relocation subtracts them out again. I think
10066 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 10067 it. FIXME. */
10068 value += fixP->fx_where + fixP->fx_frag->fr_address;
10069 }
252b5132
RH		 10070 }
10071#endif
10072#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 10073 /* For some reason, the PE format does not store a
10074 section address offset for a PC relative symbol. */
10075 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 10076 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 10077 value += md_pcrel_from (fixP);
10078#endif
10079 }
fbeb56a4 10080#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 10081 if (fixP->fx_addsy != NULL
10082 && S_IS_WEAK (fixP->fx_addsy)
10083 /* PR 16858: Do not modify weak function references. */
10084 && ! fixP->fx_pcrel)
fbeb56a4 10085 {
296a8689
NC		 10086#if !defined (TE_PEP)
10087 /* For x86 PE weak function symbols are neither PC-relative
10088 nor do they set S_IS_FUNCTION. So the only reliable way
10089 to detect them is to check the flags of their containing
10090 section. */
10091 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
10092 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
10093 ;
10094 else
10095#endif
fbeb56a4
DK		 10096 value -= S_GET_VALUE (fixP->fx_addsy);
10097 }
10098#endif
252b5132
RH		 10099
10100 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 10101 and we must not disappoint it. */
252b5132 10102#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 10103 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 10104 switch (fixP->fx_r_type)
10105 {
10106 case BFD_RELOC_386_PLT32:
3e73aa7c 10107 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 10108 /* Make the jump instruction point to the address of the operand. At
10109 runtime we merely add the offset to the actual PLT entry. */
10110 value = -4;
10111 break;
31312f95 10112
13ae64f3
JJ		 10113 case BFD_RELOC_386_TLS_GD:
10114 case BFD_RELOC_386_TLS_LDM:
13ae64f3 10115 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10116 case BFD_RELOC_386_TLS_IE:
10117 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 10118 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 10119 case BFD_RELOC_X86_64_TLSGD:
10120 case BFD_RELOC_X86_64_TLSLD:
10121 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 10122 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 10123 value = 0; /* Fully resolved at runtime. No addend. */
10124 /* Fallthrough */
10125 case BFD_RELOC_386_TLS_LE:
10126 case BFD_RELOC_386_TLS_LDO_32:
10127 case BFD_RELOC_386_TLS_LE_32:
10128 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10129 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 10130 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 10131 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 10132 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10133 break;
10134
67a4f2b7
AO		 10135 case BFD_RELOC_386_TLS_DESC_CALL:
10136 case BFD_RELOC_X86_64_TLSDESC_CALL:
10137 value = 0; /* Fully resolved at runtime. No addend. */
10138 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10139 fixP->fx_done = 0;
10140 return;
10141
47926f60
KH		 10142 case BFD_RELOC_VTABLE_INHERIT:
10143 case BFD_RELOC_VTABLE_ENTRY:
10144 fixP->fx_done = 0;
94f592af 10145 return;
47926f60
KH		 10146
10147 default:
10148 break;
10149 }
10150#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 10151 *valP = value;
f86103b7 10152#endif /* !defined (TE_Mach) */
3e73aa7c 10153
3e73aa7c 10154 /* Are we finished with this relocation now? */
c6682705 10155 if (fixP->fx_addsy == NULL)
3e73aa7c 10156 fixP->fx_done = 1;
fbeb56a4
DK		 10157#if defined (OBJ_COFF) && defined (TE_PE)
10158 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10159 {
10160 fixP->fx_done = 0;
10161 /* Remember value for tc_gen_reloc. */
10162 fixP->fx_addnumber = value;
10163 /* Clear out the frag for now. */
10164 value = 0;
10165 }
10166#endif
3e73aa7c
JH		 10167 else if (use_rela_relocations)
10168 {
10169 fixP->fx_no_overflow = 1;
062cd5e7
AS		 10170 /* Remember value for tc_gen_reloc. */
10171 fixP->fx_addnumber = value;
3e73aa7c
JH		 10172 value = 0;
10173 }
f86103b7 10174
94f592af 10175 md_number_to_chars (p, value, fixP->fx_size);
252b5132 10176}
252b5132 10177\f
6d4af3c2 10178const char *
499ac353 10179md_atof (int type, char *litP, int *sizeP)
252b5132 10180{
499ac353
NC		 10181 /* This outputs the LITTLENUMs in REVERSE order;
10182 in accord with the bigendian 386. */
10183 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 10184}
10185\f
2d545b82 10186static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 10187
252b5132 10188static char *
e3bb37b5 10189output_invalid (int c)
252b5132 10190{
3882b010 10191 if (ISPRINT (c))
f9f21a03
L		 10192 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10193 "'%c'", c);
252b5132 10194 else
f9f21a03 10195 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 10196 "(0x%x)", (unsigned char) c);
252b5132
RH		 10197 return output_invalid_buf;
10198}
10199
af6bdddf 10200/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 10201
10202static const reg_entry *
4d1bb795 10203parse_real_register (char *reg_string, char **end_op)
252b5132 10204{
af6bdddf
AM		 10205 char *s = reg_string;
10206 char *p;
252b5132
RH		 10207 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10208 const reg_entry *r;
10209
10210 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10211 if (*s == REGISTER_PREFIX)
10212 ++s;
10213
10214 if (is_space_char (*s))
10215 ++s;
10216
10217 p = reg_name_given;
af6bdddf 10218 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 10219 {
10220 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 10221 return (const reg_entry *) NULL;
10222 s++;
252b5132
RH		 10223 }
10224
6588847e
DN		 10225 /* For naked regs, make sure that we are not dealing with an identifier.
10226 This prevents confusing an identifier like `eax_var' with register
10227 `eax'. */
10228 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10229 return (const reg_entry *) NULL;
10230
af6bdddf 10231 *end_op = s;
252b5132
RH		 10232
10233 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10234
5f47d35b 10235 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 10236 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 10237 {
0e0eea78
JB		 10238 if (!cpu_arch_flags.bitfield.cpu8087
10239 && !cpu_arch_flags.bitfield.cpu287
10240 && !cpu_arch_flags.bitfield.cpu387)
10241 return (const reg_entry *) NULL;
10242
5f47d35b
AM		 10243 if (is_space_char (*s))
10244 ++s;
10245 if (*s == '(')
10246 {
af6bdddf 10247 ++s;
5f47d35b
AM		 10248 if (is_space_char (*s))
10249 ++s;
10250 if (*s >= '0' && *s <= '7')
10251 {
db557034 10252 int fpr = *s - '0';
af6bdddf 10253 ++s;
5f47d35b
AM		 10254 if (is_space_char (*s))
10255 ++s;
10256 if (*s == ')')
10257 {
10258 *end_op = s + 1;
1e9cc1c2 10259 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 10260 know (r);
10261 return r + fpr;
5f47d35b 10262 }
5f47d35b 10263 }
47926f60 10264 /* We have "%st(" then garbage. */
5f47d35b
AM		 10265 return (const reg_entry *) NULL;
10266 }
10267 }
10268
a60de03c
JB		 10269 if (r == NULL || allow_pseudo_reg)
10270 return r;
10271
0dfbf9d7 10272 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 10273 return (const reg_entry *) NULL;
10274
dc821c5f 10275 if ((r->reg_type.bitfield.dword
192dc9c6
JB		 10276 || r->reg_type.bitfield.sreg3
10277 || r->reg_type.bitfield.control
10278 || r->reg_type.bitfield.debug
10279 || r->reg_type.bitfield.test)
10280 && !cpu_arch_flags.bitfield.cpui386)
10281 return (const reg_entry *) NULL;
10282
6e041cf4 10283 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
192dc9c6
JB		 10284 return (const reg_entry *) NULL;
10285
6e041cf4
JB		 10286 if (!cpu_arch_flags.bitfield.cpuavx512f)
10287 {
10288 if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask)
10289 return (const reg_entry *) NULL;
40f12533 10290
6e041cf4
JB		 10291 if (!cpu_arch_flags.bitfield.cpuavx)
10292 {
10293 if (r->reg_type.bitfield.ymmword)
10294 return (const reg_entry *) NULL;
1848e567 10295
6e041cf4
JB		 10296 if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword)
10297 return (const reg_entry *) NULL;
10298 }
10299 }
43234a1e 10300
1adf7f56
JB		 10301 if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx)
10302 return (const reg_entry *) NULL;
10303
db51cc60 10304 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 10305 if (!allow_index_reg
db51cc60
L		 10306 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10307 return (const reg_entry *) NULL;
10308
1d3f8286
JB		 10309 /* Upper 16 vector registers are only available with VREX in 64bit
10310 mode, and require EVEX encoding. */
10311 if (r->reg_flags & RegVRex)
43234a1e
L		 10312 {
10313 if (!cpu_arch_flags.bitfield.cpuvrex
10314 || flag_code != CODE_64BIT)
10315 return (const reg_entry *) NULL;
1d3f8286
JB		 10316
10317 i.vec_encoding = vex_encoding_evex;
43234a1e
L		 10318 }
10319
4787f4a5
JB		 10320 if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword)
10321 && (!cpu_arch_flags.bitfield.cpulm || !r->reg_type.bitfield.control)
1ae00879 10322 && flag_code != CODE_64BIT)
20f0a1fc 10323 return (const reg_entry *) NULL;
1ae00879 10324
b7240065
JB		 10325 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10326 return (const reg_entry *) NULL;
10327
252b5132
RH		 10328 return r;
10329}
4d1bb795
JB		 10330
10331/* REG_STRING starts *before* REGISTER_PREFIX. */
10332
10333static const reg_entry *
10334parse_register (char *reg_string, char **end_op)
10335{
10336 const reg_entry *r;
10337
10338 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10339 r = parse_real_register (reg_string, end_op);
10340 else
10341 r = NULL;
10342 if (!r)
10343 {
10344 char *save = input_line_pointer;
10345 char c;
10346 symbolS *symbolP;
10347
10348 input_line_pointer = reg_string;
d02603dc 10349 c = get_symbol_name (&reg_string);
4d1bb795
JB		 10350 symbolP = symbol_find (reg_string);
10351 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10352 {
10353 const expressionS *e = symbol_get_value_expression (symbolP);
10354
0398aac5 10355 know (e->X_op == O_register);
4eed87de 10356 know (e->X_add_number >= 0
c3fe08fa 10357 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 10358 r = i386_regtab + e->X_add_number;
d3bb6b49 10359 if ((r->reg_flags & RegVRex))
86fa6981 10360 i.vec_encoding = vex_encoding_evex;
4d1bb795
JB		 10361 *end_op = input_line_pointer;
10362 }
10363 *input_line_pointer = c;
10364 input_line_pointer = save;
10365 }
10366 return r;
10367}
10368
10369int
10370i386_parse_name (char *name, expressionS *e, char *nextcharP)
10371{
10372 const reg_entry *r;
10373 char *end = input_line_pointer;
10374
10375 *end = *nextcharP;
10376 r = parse_register (name, &input_line_pointer);
10377 if (r && end <= input_line_pointer)
10378 {
10379 *nextcharP = *input_line_pointer;
10380 *input_line_pointer = 0;
10381 e->X_op = O_register;
10382 e->X_add_number = r - i386_regtab;
10383 return 1;
10384 }
10385 input_line_pointer = end;
10386 *end = 0;
ee86248c 10387 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 10388}
10389
10390void
10391md_operand (expressionS *e)
10392{
ee86248c
JB		 10393 char *end;
10394 const reg_entry *r;
4d1bb795 10395
ee86248c
JB		 10396 switch (*input_line_pointer)
10397 {
10398 case REGISTER_PREFIX:
10399 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 10400 if (r)
10401 {
10402 e->X_op = O_register;
10403 e->X_add_number = r - i386_regtab;
10404 input_line_pointer = end;
10405 }
ee86248c
JB		 10406 break;
10407
10408 case '[':
9c2799c2 10409 gas_assert (intel_syntax);
ee86248c
JB		 10410 end = input_line_pointer++;
10411 expression (e);
10412 if (*input_line_pointer == ']')
10413 {
10414 ++input_line_pointer;
10415 e->X_op_symbol = make_expr_symbol (e);
10416 e->X_add_symbol = NULL;
10417 e->X_add_number = 0;
10418 e->X_op = O_index;
10419 }
10420 else
10421 {
10422 e->X_op = O_absent;
10423 input_line_pointer = end;
10424 }
10425 break;
4d1bb795
JB		 10426 }
10427}
10428
252b5132 10429\f
4cc782b5 10430#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
b6f8c7c4 10431const char *md_shortopts = "kVQ:sqnO::";
252b5132 10432#else
b6f8c7c4 10433const char *md_shortopts = "qnO::";
252b5132 10434#endif
6e0b89ee 10435
3e73aa7c 10436#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 10437#define OPTION_64 (OPTION_MD_BASE + 1)
10438#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 10439#define OPTION_MARCH (OPTION_MD_BASE + 3)
10440#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 10441#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10442#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10443#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10444#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
bd5dea88 10445#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
c0f3af97 10446#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 10447#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 10448#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10449#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10450#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 10451#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 10452#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10453#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 10454#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 10455#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 10456#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 10457#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 10458#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10459#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 10460#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
b3b91714 10461
99ad8390
NC		 10462struct option md_longopts[] =
10463{
3e73aa7c 10464 {"32", no_argument, NULL, OPTION_32},
321098a5 10465#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10466 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 10467 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 10468#endif
10469#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10470 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 10471 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 10472#endif
b3b91714 10473 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 10474 {"march", required_argument, NULL, OPTION_MARCH},
10475 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 10476 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10477 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10478 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10479 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
c0f3af97 10480 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 10481 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 10482 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 10483 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 10484 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 10485 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10486 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 10487# if defined (TE_PE) || defined (TE_PEP)
10488 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10489#endif
d1982f93 10490 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 10491 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 10492 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 10493 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 10494 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10495 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 10496 {NULL, no_argument, NULL, 0}
10497};
10498size_t md_longopts_size = sizeof (md_longopts);
10499
10500int
17b9d67d 10501md_parse_option (int c, const char *arg)
252b5132 10502{
91d6fa6a 10503 unsigned int j;
293f5f65 10504 char *arch, *next, *saved;
9103f4f4 10505
252b5132
RH		 10506 switch (c)
10507 {
12b55ccc
L		 10508 case 'n':
10509 optimize_align_code = 0;
10510 break;
10511
a38cf1db
AM		 10512 case 'q':
10513 quiet_warnings = 1;
252b5132
RH		 10514 break;
10515
10516#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 10517 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10518 should be emitted or not. FIXME: Not implemented. */
10519 case 'Q':
252b5132
RH		 10520 break;
10521
10522 /* -V: SVR4 argument to print version ID. */
10523 case 'V':
10524 print_version_id ();
10525 break;
10526
a38cf1db
AM		 10527 /* -k: Ignore for FreeBSD compatibility. */
10528 case 'k':
252b5132 10529 break;
4cc782b5
ILT		 10530
10531 case 's':
10532 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 10533 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 10534 break;
8dcea932
L		 10535
10536 case OPTION_MSHARED:
10537 shared = 1;
10538 break;
99ad8390 10539#endif
321098a5 10540#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10541 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 10542 case OPTION_64:
10543 {
10544 const char **list, **l;
10545
3e73aa7c
JH		 10546 list = bfd_target_list ();
10547 for (l = list; *l != NULL; l++)
8620418b 10548 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 10549 || strcmp (*l, "coff-x86-64") == 0
10550 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 10551 || strcmp (*l, "pei-x86-64") == 0
10552 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 10553 {
10554 default_arch = "x86_64";
10555 break;
10556 }
3e73aa7c 10557 if (*l == NULL)
2b5d6a91 10558 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 10559 free (list);
10560 }
10561 break;
10562#endif
252b5132 10563
351f65ca 10564#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10565 case OPTION_X32:
351f65ca
L		 10566 if (IS_ELF)
10567 {
10568 const char **list, **l;
10569
10570 list = bfd_target_list ();
10571 for (l = list; *l != NULL; l++)
10572 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10573 {
10574 default_arch = "x86_64:32";
10575 break;
10576 }
10577 if (*l == NULL)
2b5d6a91 10578 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 10579 free (list);
10580 }
10581 else
10582 as_fatal (_("32bit x86_64 is only supported for ELF"));
10583 break;
10584#endif
10585
6e0b89ee
AM		 10586 case OPTION_32:
10587 default_arch = "i386";
10588 break;
10589
b3b91714
AM		 10590 case OPTION_DIVIDE:
10591#ifdef SVR4_COMMENT_CHARS
10592 {
10593 char *n, *t;
10594 const char *s;
10595
add39d23 10596 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 10597 t = n;
10598 for (s = i386_comment_chars; *s != '\0'; s++)
10599 if (*s != '/')
10600 *t++ = *s;
10601 *t = '\0';
10602 i386_comment_chars = n;
10603 }
10604#endif
10605 break;
10606
9103f4f4 10607 case OPTION_MARCH:
293f5f65
L		 10608 saved = xstrdup (arg);
10609 arch = saved;
10610 /* Allow -march=+nosse. */
10611 if (*arch == '+')
10612 arch++;
6305a203 10613 do
9103f4f4 10614 {
6305a203 10615 if (*arch == '.')
2b5d6a91 10616 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10617 next = strchr (arch, '+');
10618 if (next)
10619 *next++ = '\0';
91d6fa6a 10620 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10621 {
91d6fa6a 10622 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 10623 {
6305a203 10624 /* Processor. */
1ded5609
JB		 10625 if (! cpu_arch[j].flags.bitfield.cpui386)
10626 continue;
10627
91d6fa6a 10628 cpu_arch_name = cpu_arch[j].name;
6305a203 10629 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 10630 cpu_arch_flags = cpu_arch[j].flags;
10631 cpu_arch_isa = cpu_arch[j].type;
10632 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 10633 if (!cpu_arch_tune_set)
10634 {
10635 cpu_arch_tune = cpu_arch_isa;
10636 cpu_arch_tune_flags = cpu_arch_isa_flags;
10637 }
10638 break;
10639 }
91d6fa6a
NC		 10640 else if (*cpu_arch [j].name == '.'
10641 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203 10642 {
33eaf5de 10643 /* ISA extension. */
6305a203 10644 i386_cpu_flags flags;
309d3373 10645
293f5f65
L		 10646 flags = cpu_flags_or (cpu_arch_flags,
10647 cpu_arch[j].flags);
81486035 10648
5b64d091 10649 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 10650 {
10651 if (cpu_sub_arch_name)
10652 {
10653 char *name = cpu_sub_arch_name;
10654 cpu_sub_arch_name = concat (name,
91d6fa6a 10655 cpu_arch[j].name,
1bf57e9f 10656 (const char *) NULL);
6305a203
L		 10657 free (name);
10658 }
10659 else
91d6fa6a 10660 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 10661 cpu_arch_flags = flags;
a586129e 10662 cpu_arch_isa_flags = flags;
6305a203 10663 }
0089dace
L		 10664 else
10665 cpu_arch_isa_flags
10666 = cpu_flags_or (cpu_arch_isa_flags,
10667 cpu_arch[j].flags);
6305a203 10668 break;
ccc9c027 10669 }
9103f4f4 10670 }
6305a203 10671
293f5f65
L		 10672 if (j >= ARRAY_SIZE (cpu_arch))
10673 {
33eaf5de 10674 /* Disable an ISA extension. */
293f5f65
L		 10675 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10676 if (strcmp (arch, cpu_noarch [j].name) == 0)
10677 {
10678 i386_cpu_flags flags;
10679
10680 flags = cpu_flags_and_not (cpu_arch_flags,
10681 cpu_noarch[j].flags);
10682 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10683 {
10684 if (cpu_sub_arch_name)
10685 {
10686 char *name = cpu_sub_arch_name;
10687 cpu_sub_arch_name = concat (arch,
10688 (const char *) NULL);
10689 free (name);
10690 }
10691 else
10692 cpu_sub_arch_name = xstrdup (arch);
10693 cpu_arch_flags = flags;
10694 cpu_arch_isa_flags = flags;
10695 }
10696 break;
10697 }
10698
10699 if (j >= ARRAY_SIZE (cpu_noarch))
10700 j = ARRAY_SIZE (cpu_arch);
10701 }
10702
91d6fa6a 10703 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10704 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10705
10706 arch = next;
9103f4f4 10707 }
293f5f65
L		 10708 while (next != NULL);
10709 free (saved);
9103f4f4
L		 10710 break;
10711
10712 case OPTION_MTUNE:
10713 if (*arg == '.')
2b5d6a91 10714 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 10715 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10716 {
91d6fa6a 10717 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 10718 {
ccc9c027 10719 cpu_arch_tune_set = 1;
91d6fa6a
NC		 10720 cpu_arch_tune = cpu_arch [j].type;
10721 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 10722 break;
10723 }
10724 }
91d6fa6a 10725 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10726 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 10727 break;
10728
1efbbeb4
L		 10729 case OPTION_MMNEMONIC:
10730 if (strcasecmp (arg, "att") == 0)
10731 intel_mnemonic = 0;
10732 else if (strcasecmp (arg, "intel") == 0)
10733 intel_mnemonic = 1;
10734 else
2b5d6a91 10735 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 10736 break;
10737
10738 case OPTION_MSYNTAX:
10739 if (strcasecmp (arg, "att") == 0)
10740 intel_syntax = 0;
10741 else if (strcasecmp (arg, "intel") == 0)
10742 intel_syntax = 1;
10743 else
2b5d6a91 10744 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 10745 break;
10746
10747 case OPTION_MINDEX_REG:
10748 allow_index_reg = 1;
10749 break;
10750
10751 case OPTION_MNAKED_REG:
10752 allow_naked_reg = 1;
10753 break;
10754
c0f3af97
L		 10755 case OPTION_MSSE2AVX:
10756 sse2avx = 1;
10757 break;
10758
daf50ae7
L		 10759 case OPTION_MSSE_CHECK:
10760 if (strcasecmp (arg, "error") == 0)
7bab8ab5 10761 sse_check = check_error;
daf50ae7 10762 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 10763 sse_check = check_warning;
daf50ae7 10764 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10765 sse_check = check_none;
daf50ae7 10766 else
2b5d6a91 10767 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10768 break;
10769
7bab8ab5
JB		 10770 case OPTION_MOPERAND_CHECK:
10771 if (strcasecmp (arg, "error") == 0)
10772 operand_check = check_error;
10773 else if (strcasecmp (arg, "warning") == 0)
10774 operand_check = check_warning;
10775 else if (strcasecmp (arg, "none") == 0)
10776 operand_check = check_none;
10777 else
10778 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10779 break;
10780
539f890d
L		 10781 case OPTION_MAVXSCALAR:
10782 if (strcasecmp (arg, "128") == 0)
10783 avxscalar = vex128;
10784 else if (strcasecmp (arg, "256") == 0)
10785 avxscalar = vex256;
10786 else
2b5d6a91 10787 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10788 break;
10789
7e8b059b
L		 10790 case OPTION_MADD_BND_PREFIX:
10791 add_bnd_prefix = 1;
10792 break;
10793
43234a1e
L		 10794 case OPTION_MEVEXLIG:
10795 if (strcmp (arg, "128") == 0)
10796 evexlig = evexl128;
10797 else if (strcmp (arg, "256") == 0)
10798 evexlig = evexl256;
10799 else if (strcmp (arg, "512") == 0)
10800 evexlig = evexl512;
10801 else
10802 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10803 break;
10804
d3d3c6db
IT		 10805 case OPTION_MEVEXRCIG:
10806 if (strcmp (arg, "rne") == 0)
10807 evexrcig = rne;
10808 else if (strcmp (arg, "rd") == 0)
10809 evexrcig = rd;
10810 else if (strcmp (arg, "ru") == 0)
10811 evexrcig = ru;
10812 else if (strcmp (arg, "rz") == 0)
10813 evexrcig = rz;
10814 else
10815 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10816 break;
10817
43234a1e
L		 10818 case OPTION_MEVEXWIG:
10819 if (strcmp (arg, "0") == 0)
10820 evexwig = evexw0;
10821 else if (strcmp (arg, "1") == 0)
10822 evexwig = evexw1;
10823 else
10824 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10825 break;
10826
167ad85b
TG		 10827# if defined (TE_PE) || defined (TE_PEP)
10828 case OPTION_MBIG_OBJ:
10829 use_big_obj = 1;
10830 break;
10831#endif
10832
d1982f93 10833 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10834 if (strcasecmp (arg, "yes") == 0)
10835 omit_lock_prefix = 1;
10836 else if (strcasecmp (arg, "no") == 0)
10837 omit_lock_prefix = 0;
10838 else
10839 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10840 break;
10841
e4e00185
AS		 10842 case OPTION_MFENCE_AS_LOCK_ADD:
10843 if (strcasecmp (arg, "yes") == 0)
10844 avoid_fence = 1;
10845 else if (strcasecmp (arg, "no") == 0)
10846 avoid_fence = 0;
10847 else
10848 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10849 break;
10850
0cb4071e
L		 10851 case OPTION_MRELAX_RELOCATIONS:
10852 if (strcasecmp (arg, "yes") == 0)
10853 generate_relax_relocations = 1;
10854 else if (strcasecmp (arg, "no") == 0)
10855 generate_relax_relocations = 0;
10856 else
10857 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10858 break;
10859
5db04b09 10860 case OPTION_MAMD64:
e89c5eaa 10861 intel64 = 0;
5db04b09
L		 10862 break;
10863
10864 case OPTION_MINTEL64:
e89c5eaa 10865 intel64 = 1;
5db04b09
L		 10866 break;
10867
b6f8c7c4
L		 10868 case 'O':
10869 if (arg == NULL)
10870 {
10871 optimize = 1;
10872 /* Turn off -Os. */
10873 optimize_for_space = 0;
10874 }
10875 else if (*arg == 's')
10876 {
10877 optimize_for_space = 1;
10878 /* Turn on all encoding optimizations. */
10879 optimize = -1;
10880 }
10881 else
10882 {
10883 optimize = atoi (arg);
10884 /* Turn off -Os. */
10885 optimize_for_space = 0;
10886 }
10887 break;
10888
252b5132
RH		 10889 default:
10890 return 0;
10891 }
10892 return 1;
10893}
10894
8a2c8fef
L		 10895#define MESSAGE_TEMPLATE \
10896" "
10897
293f5f65
L		 10898static char *
10899output_message (FILE *stream, char *p, char *message, char *start,
10900 int *left_p, const char *name, int len)
10901{
10902 int size = sizeof (MESSAGE_TEMPLATE);
10903 int left = *left_p;
10904
10905 /* Reserve 2 spaces for ", " or ",\0" */
10906 left -= len + 2;
10907
10908 /* Check if there is any room. */
10909 if (left >= 0)
10910 {
10911 if (p != start)
10912 {
10913 *p++ = ',';
10914 *p++ = ' ';
10915 }
10916 p = mempcpy (p, name, len);
10917 }
10918 else
10919 {
10920 /* Output the current message now and start a new one. */
10921 *p++ = ',';
10922 *p = '\0';
10923 fprintf (stream, "%s\n", message);
10924 p = start;
10925 left = size - (start - message) - len - 2;
10926
10927 gas_assert (left >= 0);
10928
10929 p = mempcpy (p, name, len);
10930 }
10931
10932 *left_p = left;
10933 return p;
10934}
10935
8a2c8fef 10936static void
1ded5609 10937show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10938{
10939 static char message[] = MESSAGE_TEMPLATE;
10940 char *start = message + 27;
10941 char *p;
10942 int size = sizeof (MESSAGE_TEMPLATE);
10943 int left;
10944 const char *name;
10945 int len;
10946 unsigned int j;
10947
10948 p = start;
10949 left = size - (start - message);
10950 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10951 {
10952 /* Should it be skipped? */
10953 if (cpu_arch [j].skip)
10954 continue;
10955
10956 name = cpu_arch [j].name;
10957 len = cpu_arch [j].len;
10958 if (*name == '.')
10959 {
10960 /* It is an extension. Skip if we aren't asked to show it. */
10961 if (ext)
10962 {
10963 name++;
10964 len--;
10965 }
10966 else
10967 continue;
10968 }
10969 else if (ext)
10970 {
10971 /* It is an processor. Skip if we show only extension. */
10972 continue;
10973 }
1ded5609
JB		 10974 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10975 {
10976 /* It is an impossible processor - skip. */
10977 continue;
10978 }
8a2c8fef 10979
293f5f65 10980 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 10981 }
10982
293f5f65
L		 10983 /* Display disabled extensions. */
10984 if (ext)
10985 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10986 {
10987 name = cpu_noarch [j].name;
10988 len = cpu_noarch [j].len;
10989 p = output_message (stream, p, message, start, &left, name,
10990 len);
10991 }
10992
8a2c8fef
L		 10993 *p = '\0';
10994 fprintf (stream, "%s\n", message);
10995}
10996
252b5132 10997void
8a2c8fef 10998md_show_usage (FILE *stream)
252b5132 10999{
4cc782b5
ILT		 11000#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11001 fprintf (stream, _("\
a38cf1db
AM		 11002 -Q ignored\n\
11003 -V print assembler version number\n\
b3b91714
AM		 11004 -k ignored\n"));
11005#endif
11006 fprintf (stream, _("\
12b55ccc 11007 -n Do not optimize code alignment\n\
b3b91714
AM		 11008 -q quieten some warnings\n"));
11009#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11010 fprintf (stream, _("\
a38cf1db 11011 -s ignored\n"));
b3b91714 11012#endif
321098a5
L		 11013#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11014 || defined (TE_PE) || defined (TE_PEP))
751d281c 11015 fprintf (stream, _("\
570561f7 11016 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 11017#endif
b3b91714
AM		 11018#ifdef SVR4_COMMENT_CHARS
11019 fprintf (stream, _("\
11020 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 11021#else
11022 fprintf (stream, _("\
b3b91714 11023 --divide ignored\n"));
4cc782b5 11024#endif
9103f4f4 11025 fprintf (stream, _("\
6305a203 11026 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 11027 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 11028 show_arch (stream, 0, 1);
8a2c8fef
L		 11029 fprintf (stream, _("\
11030 EXTENSION is combination of:\n"));
1ded5609 11031 show_arch (stream, 1, 0);
6305a203 11032 fprintf (stream, _("\
8a2c8fef 11033 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 11034 show_arch (stream, 0, 0);
ba104c83 11035 fprintf (stream, _("\
c0f3af97
L		 11036 -msse2avx encode SSE instructions with VEX prefix\n"));
11037 fprintf (stream, _("\
daf50ae7
L		 11038 -msse-check=[none|error|warning]\n\
11039 check SSE instructions\n"));
11040 fprintf (stream, _("\
7bab8ab5
JB		 11041 -moperand-check=[none|error|warning]\n\
11042 check operand combinations for validity\n"));
11043 fprintf (stream, _("\
539f890d
L		 11044 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
11045 length\n"));
11046 fprintf (stream, _("\
43234a1e
L		 11047 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
11048 length\n"));
11049 fprintf (stream, _("\
11050 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
11051 for EVEX.W bit ignored instructions\n"));
11052 fprintf (stream, _("\
d3d3c6db
IT		 11053 -mevexrcig=[rne|rd|ru|rz]\n\
11054 encode EVEX instructions with specific EVEX.RC value\n\
11055 for SAE-only ignored instructions\n"));
11056 fprintf (stream, _("\
ba104c83
L		 11057 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
11058 fprintf (stream, _("\
11059 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
11060 fprintf (stream, _("\
11061 -mindex-reg support pseudo index registers\n"));
11062 fprintf (stream, _("\
11063 -mnaked-reg don't require `%%' prefix for registers\n"));
11064 fprintf (stream, _("\
7e8b059b 11065 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 11066 fprintf (stream, _("\
11067 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 11068# if defined (TE_PE) || defined (TE_PEP)
11069 fprintf (stream, _("\
11070 -mbig-obj generate big object files\n"));
11071#endif
d022bddd
IT		 11072 fprintf (stream, _("\
11073 -momit-lock-prefix=[no|yes]\n\
11074 strip all lock prefixes\n"));
5db04b09 11075 fprintf (stream, _("\
e4e00185
AS		 11076 -mfence-as-lock-add=[no|yes]\n\
11077 encode lfence, mfence and sfence as\n\
11078 lock addl $0x0, (%%{re}sp)\n"));
11079 fprintf (stream, _("\
0cb4071e
L		 11080 -mrelax-relocations=[no|yes]\n\
11081 generate relax relocations\n"));
11082 fprintf (stream, _("\
5db04b09
L		 11083 -mamd64 accept only AMD64 ISA\n"));
11084 fprintf (stream, _("\
11085 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 11086}
11087
3e73aa7c 11088#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 11089 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 11090 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 11091
11092/* Pick the target format to use. */
11093
47926f60 11094const char *
e3bb37b5 11095i386_target_format (void)
252b5132 11096{
351f65ca
L		 11097 if (!strncmp (default_arch, "x86_64", 6))
11098 {
11099 update_code_flag (CODE_64BIT, 1);
11100 if (default_arch[6] == '\0')
7f56bc95 11101 x86_elf_abi = X86_64_ABI;
351f65ca 11102 else
7f56bc95 11103 x86_elf_abi = X86_64_X32_ABI;
351f65ca 11104 }
3e73aa7c 11105 else if (!strcmp (default_arch, "i386"))
78f12dd3 11106 update_code_flag (CODE_32BIT, 1);
5197d474
L		 11107 else if (!strcmp (default_arch, "iamcu"))
11108 {
11109 update_code_flag (CODE_32BIT, 1);
11110 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
11111 {
11112 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
11113 cpu_arch_name = "iamcu";
11114 cpu_sub_arch_name = NULL;
11115 cpu_arch_flags = iamcu_flags;
11116 cpu_arch_isa = PROCESSOR_IAMCU;
11117 cpu_arch_isa_flags = iamcu_flags;
11118 if (!cpu_arch_tune_set)
11119 {
11120 cpu_arch_tune = cpu_arch_isa;
11121 cpu_arch_tune_flags = cpu_arch_isa_flags;
11122 }
11123 }
8d471ec1 11124 else if (cpu_arch_isa != PROCESSOR_IAMCU)
5197d474
L		 11125 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11126 cpu_arch_name);
11127 }
3e73aa7c 11128 else
2b5d6a91 11129 as_fatal (_("unknown architecture"));
89507696
JB		 11130
11131 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11132 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11133 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11134 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11135
252b5132
RH		 11136 switch (OUTPUT_FLAVOR)
11137 {
9384f2ff 11138#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 11139 case bfd_target_aout_flavour:
47926f60 11140 return AOUT_TARGET_FORMAT;
4c63da97 11141#endif
9384f2ff
AM		 11142#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11143# if defined (TE_PE) || defined (TE_PEP)
11144 case bfd_target_coff_flavour:
167ad85b
TG		 11145 if (flag_code == CODE_64BIT)
11146 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11147 else
11148 return "pe-i386";
9384f2ff 11149# elif defined (TE_GO32)
0561d57c
JK		 11150 case bfd_target_coff_flavour:
11151 return "coff-go32";
9384f2ff 11152# else
252b5132
RH		 11153 case bfd_target_coff_flavour:
11154 return "coff-i386";
9384f2ff 11155# endif
4c63da97 11156#endif
3e73aa7c 11157#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 11158 case bfd_target_elf_flavour:
3e73aa7c 11159 {
351f65ca
L		 11160 const char *format;
11161
11162 switch (x86_elf_abi)
4fa24527 11163 {
351f65ca
L		 11164 default:
11165 format = ELF_TARGET_FORMAT;
11166 break;
7f56bc95 11167 case X86_64_ABI:
351f65ca 11168 use_rela_relocations = 1;
4fa24527 11169 object_64bit = 1;
351f65ca
L		 11170 format = ELF_TARGET_FORMAT64;
11171 break;
7f56bc95 11172 case X86_64_X32_ABI:
4fa24527 11173 use_rela_relocations = 1;
351f65ca 11174 object_64bit = 1;
862be3fb 11175 disallow_64bit_reloc = 1;
351f65ca
L		 11176 format = ELF_TARGET_FORMAT32;
11177 break;
4fa24527 11178 }
3632d14b 11179 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 11180 {
7f56bc95 11181 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 11182 as_fatal (_("Intel L1OM is 64bit only"));
11183 return ELF_TARGET_L1OM_FORMAT;
11184 }
b49f93f6 11185 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 11186 {
11187 if (x86_elf_abi != X86_64_ABI)
11188 as_fatal (_("Intel K1OM is 64bit only"));
11189 return ELF_TARGET_K1OM_FORMAT;
11190 }
81486035
L		 11191 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11192 {
11193 if (x86_elf_abi != I386_ABI)
11194 as_fatal (_("Intel MCU is 32bit only"));
11195 return ELF_TARGET_IAMCU_FORMAT;
11196 }
8a9036a4 11197 else
351f65ca 11198 return format;
3e73aa7c 11199 }
e57f8c65
TG		 11200#endif
11201#if defined (OBJ_MACH_O)
11202 case bfd_target_mach_o_flavour:
d382c579
TG		 11203 if (flag_code == CODE_64BIT)
11204 {
11205 use_rela_relocations = 1;
11206 object_64bit = 1;
11207 return "mach-o-x86-64";
11208 }
11209 else
11210 return "mach-o-i386";
4c63da97 11211#endif
252b5132
RH		 11212 default:
11213 abort ();
11214 return NULL;
11215 }
11216}
11217
47926f60 11218#endif /* OBJ_MAYBE_ more than one */
252b5132 11219\f
252b5132 11220symbolS *
7016a5d5 11221md_undefined_symbol (char *name)
252b5132 11222{
18dc2407
ILT		 11223 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11224 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11225 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11226 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 11227 {
11228 if (!GOT_symbol)
11229 {
11230 if (symbol_find (name))
11231 as_bad (_("GOT already in symbol table"));
11232 GOT_symbol = symbol_new (name, undefined_section,
11233 (valueT) 0, &zero_address_frag);
11234 };
11235 return GOT_symbol;
11236 }
252b5132
RH		 11237 return 0;
11238}
11239
11240/* Round up a section size to the appropriate boundary. */
47926f60 11241
252b5132 11242valueT
7016a5d5 11243md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 11244{
4c63da97
AM		 11245#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11246 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11247 {
11248 /* For a.out, force the section size to be aligned. If we don't do
11249 this, BFD will align it for us, but it will not write out the
11250 final bytes of the section. This may be a bug in BFD, but it is
11251 easier to fix it here since that is how the other a.out targets
11252 work. */
11253 int align;
11254
11255 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 11256 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 11257 }
252b5132
RH		 11258#endif
11259
11260 return size;
11261}
11262
11263/* On the i386, PC-relative offsets are relative to the start of the
11264 next instruction. That is, the address of the offset, plus its
11265 size, since the offset is always the last part of the insn. */
11266
11267long
e3bb37b5 11268md_pcrel_from (fixS *fixP)
252b5132
RH		 11269{
11270 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11271}
11272
11273#ifndef I386COFF
11274
11275static void
e3bb37b5 11276s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 11277{
29b0f896 11278 int temp;
252b5132 11279
8a75718c
JB		 11280#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11281 if (IS_ELF)
11282 obj_elf_section_change_hook ();
11283#endif
252b5132
RH		 11284 temp = get_absolute_expression ();
11285 subseg_set (bss_section, (subsegT) temp);
11286 demand_empty_rest_of_line ();
11287}
11288
11289#endif
11290
252b5132 11291void
e3bb37b5 11292i386_validate_fix (fixS *fixp)
252b5132 11293{
02a86693 11294 if (fixp->fx_subsy)
252b5132 11295 {
02a86693 11296 if (fixp->fx_subsy == GOT_symbol)
23df1078 11297 {
02a86693
L		 11298 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11299 {
11300 if (!object_64bit)
11301 abort ();
11302#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11303 if (fixp->fx_tcbit2)
56ceb5b5
L		 11304 fixp->fx_r_type = (fixp->fx_tcbit
11305 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11306 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 11307 else
11308#endif
11309 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11310 }
d6ab8113 11311 else
02a86693
L		 11312 {
11313 if (!object_64bit)
11314 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11315 else
11316 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11317 }
11318 fixp->fx_subsy = 0;
23df1078 11319 }
252b5132 11320 }
02a86693
L		 11321#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11322 else if (!object_64bit)
11323 {
11324 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11325 && fixp->fx_tcbit2)
11326 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11327 }
11328#endif
252b5132
RH		 11329}
11330
252b5132 11331arelent *
7016a5d5 11332tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 11333{
11334 arelent *rel;
11335 bfd_reloc_code_real_type code;
11336
11337 switch (fixp->fx_r_type)
11338 {
8ce3d284 11339#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 11340 case BFD_RELOC_SIZE32:
11341 case BFD_RELOC_SIZE64:
11342 if (S_IS_DEFINED (fixp->fx_addsy)
11343 && !S_IS_EXTERNAL (fixp->fx_addsy))
11344 {
11345 /* Resolve size relocation against local symbol to size of
11346 the symbol plus addend. */
11347 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11348 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11349 && !fits_in_unsigned_long (value))
11350 as_bad_where (fixp->fx_file, fixp->fx_line,
11351 _("symbol size computation overflow"));
11352 fixp->fx_addsy = NULL;
11353 fixp->fx_subsy = NULL;
11354 md_apply_fix (fixp, (valueT *) &value, NULL);
11355 return NULL;
11356 }
8ce3d284 11357#endif
1a0670f3 11358 /* Fall through. */
8fd4256d 11359
3e73aa7c
JH		 11360 case BFD_RELOC_X86_64_PLT32:
11361 case BFD_RELOC_X86_64_GOT32:
11362 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11363 case BFD_RELOC_X86_64_GOTPCRELX:
11364 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 11365 case BFD_RELOC_386_PLT32:
11366 case BFD_RELOC_386_GOT32:
02a86693 11367 case BFD_RELOC_386_GOT32X:
252b5132
RH		 11368 case BFD_RELOC_386_GOTOFF:
11369 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 11370 case BFD_RELOC_386_TLS_GD:
11371 case BFD_RELOC_386_TLS_LDM:
11372 case BFD_RELOC_386_TLS_LDO_32:
11373 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 11374 case BFD_RELOC_386_TLS_IE:
11375 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 11376 case BFD_RELOC_386_TLS_LE_32:
11377 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 11378 case BFD_RELOC_386_TLS_GOTDESC:
11379 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 11380 case BFD_RELOC_X86_64_TLSGD:
11381 case BFD_RELOC_X86_64_TLSLD:
11382 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 11383 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 11384 case BFD_RELOC_X86_64_GOTTPOFF:
11385 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 11386 case BFD_RELOC_X86_64_TPOFF64:
11387 case BFD_RELOC_X86_64_GOTOFF64:
11388 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 11389 case BFD_RELOC_X86_64_GOT64:
11390 case BFD_RELOC_X86_64_GOTPCREL64:
11391 case BFD_RELOC_X86_64_GOTPC64:
11392 case BFD_RELOC_X86_64_GOTPLT64:
11393 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 11394 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11395 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 11396 case BFD_RELOC_RVA:
11397 case BFD_RELOC_VTABLE_ENTRY:
11398 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 11399#ifdef TE_PE
11400 case BFD_RELOC_32_SECREL:
11401#endif
252b5132
RH		 11402 code = fixp->fx_r_type;
11403 break;
dbbaec26
L		 11404 case BFD_RELOC_X86_64_32S:
11405 if (!fixp->fx_pcrel)
11406 {
11407 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11408 code = fixp->fx_r_type;
11409 break;
11410 }
1a0670f3 11411 /* Fall through. */
252b5132 11412 default:
93382f6d 11413 if (fixp->fx_pcrel)
252b5132 11414 {
93382f6d
AM		 11415 switch (fixp->fx_size)
11416 {
11417 default:
b091f402
AM		 11418 as_bad_where (fixp->fx_file, fixp->fx_line,
11419 _("can not do %d byte pc-relative relocation"),
11420 fixp->fx_size);
93382f6d
AM		 11421 code = BFD_RELOC_32_PCREL;
11422 break;
11423 case 1: code = BFD_RELOC_8_PCREL; break;
11424 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 11425 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 11426#ifdef BFD64
11427 case 8: code = BFD_RELOC_64_PCREL; break;
11428#endif
93382f6d
AM		 11429 }
11430 }
11431 else
11432 {
11433 switch (fixp->fx_size)
11434 {
11435 default:
b091f402
AM		 11436 as_bad_where (fixp->fx_file, fixp->fx_line,
11437 _("can not do %d byte relocation"),
11438 fixp->fx_size);
93382f6d
AM		 11439 code = BFD_RELOC_32;
11440 break;
11441 case 1: code = BFD_RELOC_8; break;
11442 case 2: code = BFD_RELOC_16; break;
11443 case 4: code = BFD_RELOC_32; break;
937149dd 11444#ifdef BFD64
3e73aa7c 11445 case 8: code = BFD_RELOC_64; break;
937149dd 11446#endif
93382f6d 11447 }
252b5132
RH		 11448 }
11449 break;
11450 }
252b5132 11451
d182319b
JB		 11452 if ((code == BFD_RELOC_32
11453 || code == BFD_RELOC_32_PCREL
11454 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 11455 && GOT_symbol
11456 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 11457 {
4fa24527 11458 if (!object_64bit)
d6ab8113
JB		 11459 code = BFD_RELOC_386_GOTPC;
11460 else
11461 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 11462 }
7b81dfbb
AJ		 11463 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11464 && GOT_symbol
11465 && fixp->fx_addsy == GOT_symbol)
11466 {
11467 code = BFD_RELOC_X86_64_GOTPC64;
11468 }
252b5132 11469
add39d23
TS		 11470 rel = XNEW (arelent);
11471 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 11472 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 11473
11474 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 11475
3e73aa7c
JH		 11476 if (!use_rela_relocations)
11477 {
11478 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11479 vtable entry to be used in the relocation's section offset. */
11480 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11481 rel->address = fixp->fx_offset;
fbeb56a4
DK		 11482#if defined (OBJ_COFF) && defined (TE_PE)
11483 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11484 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11485 else
11486#endif
c6682705 11487 rel->addend = 0;
3e73aa7c
JH		 11488 }
11489 /* Use the rela in 64bit mode. */
252b5132 11490 else
3e73aa7c 11491 {
862be3fb
L		 11492 if (disallow_64bit_reloc)
11493 switch (code)
11494 {
862be3fb
L		 11495 case BFD_RELOC_X86_64_DTPOFF64:
11496 case BFD_RELOC_X86_64_TPOFF64:
11497 case BFD_RELOC_64_PCREL:
11498 case BFD_RELOC_X86_64_GOTOFF64:
11499 case BFD_RELOC_X86_64_GOT64:
11500 case BFD_RELOC_X86_64_GOTPCREL64:
11501 case BFD_RELOC_X86_64_GOTPC64:
11502 case BFD_RELOC_X86_64_GOTPLT64:
11503 case BFD_RELOC_X86_64_PLTOFF64:
11504 as_bad_where (fixp->fx_file, fixp->fx_line,
11505 _("cannot represent relocation type %s in x32 mode"),
11506 bfd_get_reloc_code_name (code));
11507 break;
11508 default:
11509 break;
11510 }
11511
062cd5e7
AS		 11512 if (!fixp->fx_pcrel)
11513 rel->addend = fixp->fx_offset;
11514 else
11515 switch (code)
11516 {
11517 case BFD_RELOC_X86_64_PLT32:
11518 case BFD_RELOC_X86_64_GOT32:
11519 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11520 case BFD_RELOC_X86_64_GOTPCRELX:
11521 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 11522 case BFD_RELOC_X86_64_TLSGD:
11523 case BFD_RELOC_X86_64_TLSLD:
11524 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 11525 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11526 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 11527 rel->addend = fixp->fx_offset - fixp->fx_size;
11528 break;
11529 default:
11530 rel->addend = (section->vma
11531 - fixp->fx_size
11532 + fixp->fx_addnumber
11533 + md_pcrel_from (fixp));
11534 break;
11535 }
3e73aa7c
JH		 11536 }
11537
252b5132
RH		 11538 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11539 if (rel->howto == NULL)
11540 {
11541 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 11542 _("cannot represent relocation type %s"),
252b5132
RH		 11543 bfd_get_reloc_code_name (code));
11544 /* Set howto to a garbage value so that we can keep going. */
11545 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 11546 gas_assert (rel->howto != NULL);
252b5132
RH		 11547 }
11548
11549 return rel;
11550}
11551
ee86248c 11552#include "tc-i386-intel.c"
54cfded0 11553
a60de03c
JB		 11554void
11555tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 11556{
a60de03c
JB		 11557 int saved_naked_reg;
11558 char saved_register_dot;
54cfded0 11559
a60de03c
JB		 11560 saved_naked_reg = allow_naked_reg;
11561 allow_naked_reg = 1;
11562 saved_register_dot = register_chars['.'];
11563 register_chars['.'] = '.';
11564 allow_pseudo_reg = 1;
11565 expression_and_evaluate (exp);
11566 allow_pseudo_reg = 0;
11567 register_chars['.'] = saved_register_dot;
11568 allow_naked_reg = saved_naked_reg;
11569
e96d56a1 11570 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 11571 {
a60de03c
JB		 11572 if ((addressT) exp->X_add_number < i386_regtab_size)
11573 {
11574 exp->X_op = O_constant;
11575 exp->X_add_number = i386_regtab[exp->X_add_number]
11576 .dw2_regnum[flag_code >> 1];
11577 }
11578 else
11579 exp->X_op = O_illegal;
54cfded0 11580 }
54cfded0
AM		 11581}
11582
11583void
11584tc_x86_frame_initial_instructions (void)
11585{
a60de03c
JB		 11586 static unsigned int sp_regno[2];
11587
11588 if (!sp_regno[flag_code >> 1])
11589 {
11590 char *saved_input = input_line_pointer;
11591 char sp[][4] = {"esp", "rsp"};
11592 expressionS exp;
a4447b93 11593
a60de03c
JB		 11594 input_line_pointer = sp[flag_code >> 1];
11595 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 11596 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 11597 sp_regno[flag_code >> 1] = exp.X_add_number;
11598 input_line_pointer = saved_input;
11599 }
a4447b93 11600
61ff971f
L		 11601 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11602 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 11603}
d2b2c203 11604
d7921315
L		 11605int
11606x86_dwarf2_addr_size (void)
11607{
11608#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11609 if (x86_elf_abi == X86_64_X32_ABI)
11610 return 4;
11611#endif
11612 return bfd_arch_bits_per_address (stdoutput) / 8;
11613}
11614
d2b2c203
DJ		 11615int
11616i386_elf_section_type (const char *str, size_t len)
11617{
11618 if (flag_code == CODE_64BIT
11619 && len == sizeof ("unwind") - 1
11620 && strncmp (str, "unwind", 6) == 0)
11621 return SHT_X86_64_UNWIND;
11622
11623 return -1;
11624}
bb41ade5 11625
ad5fec3b
EB		 11626#ifdef TE_SOLARIS
11627void
11628i386_solaris_fix_up_eh_frame (segT sec)
11629{
11630 if (flag_code == CODE_64BIT)
11631 elf_section_type (sec) = SHT_X86_64_UNWIND;
11632}
11633#endif
11634
bb41ade5
AM		 11635#ifdef TE_PE
11636void
11637tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11638{
91d6fa6a 11639 expressionS exp;
bb41ade5 11640
91d6fa6a
NC		 11641 exp.X_op = O_secrel;
11642 exp.X_add_symbol = symbol;
11643 exp.X_add_number = 0;
11644 emit_expr (&exp, size);
bb41ade5
AM		 11645}
11646#endif
3b22753a
L		 11647
11648#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11649/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11650
01e1a5bc 11651bfd_vma
6d4af3c2 11652x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 11653{
11654 if (flag_code == CODE_64BIT)
11655 {
11656 if (letter == 'l')
11657 return SHF_X86_64_LARGE;
11658
8f3bae45 11659 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 11660 }
3b22753a 11661 else
8f3bae45 11662 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 11663 return -1;
11664}
11665
01e1a5bc 11666bfd_vma
3b22753a
L		 11667x86_64_section_word (char *str, size_t len)
11668{
8620418b 11669 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 11670 return SHF_X86_64_LARGE;
11671
11672 return -1;
11673}
11674
11675static void
11676handle_large_common (int small ATTRIBUTE_UNUSED)
11677{
11678 if (flag_code != CODE_64BIT)
11679 {
11680 s_comm_internal (0, elf_common_parse);
11681 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11682 }
11683 else
11684 {
11685 static segT lbss_section;
11686 asection *saved_com_section_ptr = elf_com_section_ptr;
11687 asection *saved_bss_section = bss_section;
11688
11689 if (lbss_section == NULL)
11690 {
11691 flagword applicable;
11692 segT seg = now_seg;
11693 subsegT subseg = now_subseg;
11694
11695 /* The .lbss section is for local .largecomm symbols. */
11696 lbss_section = subseg_new (".lbss", 0);
11697 applicable = bfd_applicable_section_flags (stdoutput);
11698 bfd_set_section_flags (stdoutput, lbss_section,
11699 applicable & SEC_ALLOC);
11700 seg_info (lbss_section)->bss = 1;
11701
11702 subseg_set (seg, subseg);
11703 }
11704
11705 elf_com_section_ptr = &_bfd_elf_large_com_section;
11706 bss_section = lbss_section;
11707
11708 s_comm_internal (0, elf_common_parse);
11709
11710 elf_com_section_ptr = saved_com_section_ptr;
11711 bss_section = saved_bss_section;
11712 }
11713}
11714#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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